From b0f0d2e9ca18d8604225bed3c984e4cf1b4c4b3c Mon Sep 17 00:00:00 2001 From: Dimitri Sokolyuk Date: Wed, 10 Feb 2016 20:31:09 +0100 Subject: Initial import --- Board.h | 808 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 808 insertions(+) create mode 100644 Board.h (limited to 'Board.h') diff --git a/Board.h b/Board.h new file mode 100644 index 0000000..6153abd --- /dev/null +++ b/Board.h @@ -0,0 +1,808 @@ +////////////////////////////////////////////////////////////////////////////// +// +// Filename: Board.h +// Version: +// Data: +// +// Author: Liu, Zemin +// Company: JYE Tech Ltd. +// Web: www.jyetech.com +// +//----------------------------------------------------------------------------- +// +// Target: STM32F103C8 +// Tool chain: CodeSourcery G++ +// +//----------------------------------------------------------------------------- +// Required files: +// +//----------------------------------------------------------------------------- +// Notes: +// +// +//----------------------------------------------------------------------------- +// Revision History: +// +/////////////////////////////////////////////////////////////////////////////// +// +// + +#ifndef Board_h + +#define Board_h + +#include "Common.h" + +#include "stm32f10x.h" +//#include "stm32f10x_conf.h" + +// TFT control ports + +#define TFT_nRESET_Port GPIOB +#define TFT_nRESET_Bit 11 +#define TFT_RS_Port GPIOC +#define TFT_RS_Bit 14 +#define TFT_nCS_Port GPIOC +#define TFT_nCS_Bit 13 +#define TFT_nWR_Port GPIOC +#define TFT_nWR_Bit 15 +#define TFT_nRD_Port GPIOB +#define TFT_nRD_Bit 10 + +#define TFT_Port (GPIOB->ODR) + +#define LED_Base GPIOA +#define LED_Port (GPIOA->ODR) +#define LED_Bit 15 + +// Pushbuttons +#define PB_Port (GPIOB->IDR) +#define PB_Bits 0xF000 + + +// ======== STM32 Register Constants ===================== + +// -------- Register address ----------------- +// RCC registers +#define RCC_AHBENR (*((unsigned int *)(0x40021014))) +#define RCC_APB2ENR (*((unsigned int *)(0x40021018))) +#define RCC_APB1ENR (*((unsigned int *)(0x4002101C))) + +// GPIO registers +#define GPIOA_CRL (*((unsigned int *)(0x40010800))) +#define GPIOA_BSRR (*((unsigned int *)(0x40010810))) +#define GPIOA_BRR (*((unsigned int *)(0x40010814))) + +#define GPIOB_CRL (*((unsigned int *)(0x40010C00))) +#define GPIOB_CRH (*((unsigned int *)(0x40010C04))) +#define GPIOB_IDR (*((unsigned int *)(0x40010C08))) +#define GPIOB_ODR (*((unsigned int *)(0x40010C0C))) +#define GPIOB_BSRR (*((unsigned int *)(0x40010C10))) +#define GPIOB_BRR (*((unsigned int *)(0x40010C14))) +#define GPIOB_LCKR (*((unsigned int *)(0x40010C18))) + +#define GPIOD_CRL (*((unsigned int *)(0x40011400))) +#define GPIOD_CRH (*((unsigned int *)(0x40011404))) +#define GPIOD_IDR (*((unsigned int *)(0x40011408))) +#define GPIOD_ODR (*((unsigned int *)(0x4001140C))) +#define GPIOD_BSRR (*((unsigned int *)(0x40011410))) +#define GPIOD_BRR (*((unsigned int *)(0x40011414))) +#define GPIOD_LCKR (*((unsigned int *)(0x40011418))) + +#define GPIOE_CRL (*((unsigned int *)(0x40011800))) +#define GPIOE_CRH (*((unsigned int *)(0x40011804))) +#define GPIOE_IDR (*((unsigned int *)(0x40011808))) +#define GPIOE_ODR (*((unsigned int *)(0x4001180C))) +#define GPIOE_BSRR (*((unsigned int *)(0x40011810))) +#define GPIOE_BRR (*((unsigned int *)(0x40011814))) +#define GPIOE_LCKR (*((unsigned int *)(0x40011818))) + +// FSMC registers +#define FSMC_BCR1 (*((U32 *)(0xA0000000))) +#define FSMC_BTR1 (*((U32 *)(0xA0000004))) +#define FSMC_BWTR1 (*((U32 *)(0xA0000104))) + +#define FSMC_BCR2 (*((U32 *)(0xA0000008))) +#define FSMC_BTR2 (*((U32 *)(0xA000000C))) +#define FSMC_BWTR2 (*((U32 *)(0xA000010C))) + +// ---------------- Bit fields ------------------------ +// Clock control +//-- AHBENR +#define SDIOEN 10 +#define FSMCEN 8 +#define CRCEN 6 +#define FLITFEN 4 +#define SRAMEN 2 +#define DMA2EN 1 +#define DMA1EN 0 + +//-- APB1ENR +#define DACEN 29 +#define PWREN 28 +#define BKPEN 27 +#define CANEN 25 +#define USBEN 23 +#define I2C2EN 22 +#define I2C1EN 21 +#define UART5EN 20 +#define UART4EN 19 +#define USART3EN 18 +#define USART2EN 17 + +#define SPI3EN 15 +#define SPI2EN 14 +#define WWDGEN 11 +#define TIM7EN 5 +#define TIM6EN 4 +#define TIM5EN 3 +#define TIM4EN 2 +#define TIM3EN 1 +#define TIM2EN 0 + +//-- APB2ENR +#define ADC3EN 15 +#define USART1EN 14 +#define TIM8EN 13 +#define SPI1EN 12 +#define TIM1EN 11 +#define ADC2EN 10 +#define ADC1EN 9 +#define IOPGEN 8 +#define IOPFEN 7 +#define IOPEEN 6 +#define IOPDEN 5 +#define IOPCEN 4 +#define IOPBEN 3 +#define IOPAEN 2 +#define AFIOEN 0 + + +// ---------------- Bit fields ------------------------ +// Clock control +// +/******************** Bit definition for RCC_CR register ********************/ +#define HSION 0 /*!< Internal High Speed clock enable */ +#define HSIRDY 1 /*!< Internal High Speed clock ready flag */ +#define HSITRIM 3 /*!< Internal High Speed clock trimming */ +#define HSICAL 8 /*!< Internal High Speed clock Calibration */ +#define HSEON 16 /*!< External High Speed clock enable */ +#define HSERDY 17 /*!< External High Speed clock ready flag */ +#define HSEBYP 18 /*!< External High Speed clock Bypass */ +#define CSSON 19 /*!< Clock Security System enable */ +#define PLLON 24 /*!< PLL enable */ +#define PLLRDY 25 /*!< PLL clock ready flag */ + +/******************* Bit definition for RCC_CFGR register *******************/ +/*!< SW configuration */ +#define SW 0 /*!< SW[1:0] bits (System clock Switch) */ + +/*!< SWS configuration */ +#define SWS 2 /*!< SWS[1:0] bits (System Clock Switch Status) */ + +/*!< HPRE configuration */ +#define HPRE 4 /*!< HPRE[3:0] bits (AHB prescaler) */ + +/*!< PPRE1 configuration */ +#define PPRE1 8 /*!< PRE1[2:0] bits (APB1 prescaler) */ + +/*!< PPRE2 configuration */ +#define PPRE2 11 /*!< PRE2[2:0] bits (APB2 prescaler) */ + +/*!< ADCPPRE configuration */ +#define ADCPRE 14 /*!< ADCPRE[1:0] bits (ADC prescaler) */ + +#define PLLSRC 16 /*!< PLL entry clock source */ + +#define PLLXTPRE 17 /*!< HSE divider for PLL entry */ + +/*!< PLLMUL configuration */ +#define PLLMULL 18 /*!< PLLMUL[3:0] bits (PLL multiplication factor) */ + + #define USBPRE 22 /*!< USB Device prescaler */ + +/*!< MCO configuration */ +#define MCO 24 /*!< MCO[2:0] bits (Microcontroller Clock Output) */ + +/*!<****************** Bit definition for RCC_CIR register ********************/ +#define LSIRDYF 0 /*!< LSI Ready Interrupt flag */ +#define LSERDYF 1 /*!< LSE Ready Interrupt flag */ +#define HSIRDYF 2 /*!< HSI Ready Interrupt flag */ +#define HSERDYF 3 /*!< HSE Ready Interrupt flag */ +#define PLLRDYF 4 /*!< PLL Ready Interrupt flag */ +#define CSSF 7 /*!< Clock Security System Interrupt flag */ +#define LSIRDYIE 8 /*!< LSI Ready Interrupt Enable */ +#define LSERDYIE 9 /*!< LSE Ready Interrupt Enable */ +#define HSIRDYIE 10 /*!< HSI Ready Interrupt Enable */ +#define HSERDYIE 11 /*!< HSE Ready Interrupt Enable */ +#define PLLRDYIE 12 /*!< PLL Ready Interrupt Enable */ +#define LSIRDYC 16 /*!< LSI Ready Interrupt Clear */ +#define LSERDYC 17 /*!< LSE Ready Interrupt Clear */ +#define HSIRDYC 18 /*!< HSI Ready Interrupt Clear */ +#define HSERDYC 19 /*!< HSE Ready Interrupt Clear */ +#define PLLRDYC 20 /*!< PLL Ready Interrupt Clear */ +#define CSSC 23 /*!< Clock Security System Interrupt Clear */ + +/***************** Bit definition for RCC_APB2RSTR register *****************/ +#define AFIORST 0 /*!< Alternate Function I/O reset */ +#define IOPARST 2 /*!< I/O port A reset */ +#define IOPBRST 3 /*!< I/O port B reset */ +#define IOPCRST 4 /*!< I/O port C reset */ +#define IOPDRST 5 /*!< I/O port D reset */ +#define IOPERST 6 /*!< I/O port E reset */ +#define IOPFRST 7 /*!< I/O port F reset */ +#define IOPGRST 8 /*!< I/O port G reset */ +#define ADC1RST 9 /*!< ADC 1 interface reset */ +#define ADC2RST 10 /*!< ADC 2 interface reset */ +#define TIM1RST 11 /*!< TIM1 Timer reset */ +#define SPI1RST 12 /*!< SPI 1 reset */ +#define TIM8RST 13 /*!< TIM8 Timer reset */ +#define USART1RST 14 /*!< USART1 reset */ +#define ADC3RST 15 /*!< ADC3 interface reset */ + +/***************** Bit definition for RCC_APB1RSTR register *****************/ +#define TIM2RST 0 /*!< Timer 2 reset */ +#define TIM3RST 1 /*!< Timer 3 reset */ +#define TIM4RST 2 /*!< Timer 4 reset */ +#define TIM5RST 3 /*!< Timer 5 reset */ +#define TIM6RST 4 /*!< Timer 6 reset */ +#define TIM7RST 5 /*!< Timer 7 reset */ +#define WWDGRST 11 /*!< Window Watchdog reset */ +#define SPI2RST 14 /*!< SPI 2 reset */ +#define SPI3RST 15 /*!< SPI 3 reset */ +#define USART2RST 17 /*!< USART 2 reset */ +#define USART3RST 18 /*!< RUSART 3 reset */ +#define UART4RST 19 /*!< UART 4 reset */ +#define UART5RST 20 /*!< UART 5 reset */ +#define I2C1RST 21 /*!< I2C 1 reset */ +#define I2C2RST 22 /*!< I2C 2 reset */ +#define USBRST 23 /*!< USB Device reset */ +#define CAN1RST 25 /*!< CAN1 reset */ +#define BKPRST 27 /*!< Backup interface reset */ +#define PWRRST 28 /*!< Power interface reset */ +#define DACRST 29 /*!< DAC interface reset */ + +/****************** Bit definition for RCC_AHBENR register ******************/ +#define DMA1EN 0 /*!< DMA1 clock enable */ +#define DMA2EN 1 /*!< DMA2 clock enable */ +#define SRAMEN 2 /*!< SRAM interface clock enable */ +#define FLITFEN 4 /*!< FLITF clock enable */ +#define CRCEN 6 /*!< CRC clock enable */ +#define FSMCEN 8 /*!< FSMC clock enable */ +#define SDIOEN 10 /*!< SDIO clock enable */ + +/****************** Bit definition for RCC_APB2ENR register *****************/ +#define AFIOEN 0 /*!< Alternate Function I/O clock enable */ +#define IOPAEN 2 /*!< I/O port A clock enable */ +#define IOPBEN 3 /*!< I/O port B clock enable */ +#define IOPCEN 4 /*!< I/O port C clock enable */ +#define IOPDEN 5 /*!< I/O port D clock enable */ +#define IOPEEN 6 /*!< I/O port E clock enable */ +#define IOPFEN 7 /*!< I/O port F clock enable */ +#define IOPGEN 8 /*!< I/O port G clock enable */ +#define ADC1EN 9 /*!< ADC 1 interface clock enable */ +#define ADC2EN 10 /*!< ADC 2 interface clock enable */ +#define TIM1EN 11 /*!< TIM1 Timer clock enable */ +#define SPI1EN 12 /*!< SPI 1 clock enable */ +#define TIM8EN 13 /*!< TIM8 Timer clock enable */ +#define USART1EN 14 /*!< USART1 clock enable */ +#define ADC3EN 15 /*!< DMA1 clock enable */ + +/***************** Bit definition for RCC_APB1ENR register ******************/ +#define TIM2EN 0 /*!< Timer 2 clock enabled*/ +#define TIM3EN 1 /*!< Timer 3 clock enable */ +#define TIM4EN 2 /*!< Timer 4 clock enable */ +#define TIM5EN 3 /*!< Timer 5 clock enable */ +#define TIM6EN 4 /*!< Timer 6 clock enable */ +#define TIM7EN 5 /*!< Timer 7 clock enable */ +#define WWDGEN 11 /*!< Window Watchdog clock enable */ +#define SPI2EN 14 /*!< SPI 2 clock enable */ +#define SPI3EN 15 /*!< SPI 3 clock enable */ +#define USART2EN 17 /*!< USART 2 clock enable */ +#define USART3EN 18 /*!< USART 3 clock enable */ +#define UART4EN 19 /*!< UART 4 clock enable */ +#define UART5EN 20 /*!< UART 5 clock enable */ +#define I2C1EN 21 /*!< I2C 1 clock enable */ +#define I2C2EN 22 /*!< I2C 2 clock enable */ +#define USBEN 23 /*!< USB Device clock enable */ +#define CAN1EN 25 /*!< CAN1 clock enable */ +#define BKPEN 27 /*!< Backup interface clock enable */ +#define PWREN 28 /*!< Power interface clock enable */ +#define DACEN 29 /*!< DAC interface clock enable */ + + +/******************* Bit definition for RCC_BDCR register *******************/ +#define LSEON 0 /*!< External Low Speed oscillator enable */ +#define LSERDY 1 /*!< External Low Speed oscillator Ready */ +#define LSEBYP 2 /*!< External Low Speed oscillator Bypass */ + +#define RTCSEL 8 /*!< RTCSEL[1:0] bits (RTC clock source selection) */ + +#define RTCEN 15 /*!< RTC clock enable */ +#define BDRST 16 /*!< Backup domain software reset */ + +/******************* Bit definition for RCC_CSR register ********************/ +#define LSION 0 /*!< Internal Low Speed oscillator enable */ +#define LSIRDY 1 /*!< Internal Low Speed oscillator Ready */ +#define RMVF 24 /*!< Remove reset flag */ +#define PINRSTF 26 /*!< PIN reset flag */ +#define PORRSTF 27 /*!< POR/PDR reset flag */ +#define SFTRSTF 28 /*!< Software Reset flag */ +#define IWDGRSTF 29 /*!< Independent Watchdog reset flag */ +#define WWDGRSTF 30 /*!< Window watchdog reset flag */ +#define LPWRRSTF 31 /*!< Low-Power reset flag */ + +/******************************************************************************/ +/* */ +/* TIM */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for TIM_CR1 register ********************/ +#define CEN 0 /*!