From 67d25d837ac55f28a366c0a3b262e439a6e75fc3 Mon Sep 17 00:00:00 2001 From: Dimitri Sokolyuk Date: Sat, 19 Aug 2017 12:15:28 +0200 Subject: Add AmForth --- amforth-6.5/avr8/devices/at90can32/device.inc | 1707 +++++++++++++++++++++++++ 1 file changed, 1707 insertions(+) create mode 100644 amforth-6.5/avr8/devices/at90can32/device.inc (limited to 'amforth-6.5/avr8/devices/at90can32/device.inc') diff --git a/amforth-6.5/avr8/devices/at90can32/device.inc b/amforth-6.5/avr8/devices/at90can32/device.inc new file mode 100644 index 0000000..4b27471 --- /dev/null +++ b/amforth-6.5/avr8/devices/at90can32/device.inc @@ -0,0 +1,1707 @@ +; Partname: AT90CAN32 +; generated automatically, no not edit + +.if WANT_PORTA == 1 +; ( -- addr ) System Constant +; R( -- ) +; Port A Data Register +VE_PORTA: + .dw $ff05 + .db "PORTA",0 + .dw VE_HEAD + .set VE_HEAD=VE_PORTA +XT_PORTA: + .dw PFA_DOVARIABLE +PFA_PORTA: + .dw 34 +; ( -- addr ) System Constant +; R( -- ) +; Port A Data Direction Register +VE_DDRA: + .dw $ff04 + .db "DDRA" + .dw VE_HEAD + .set VE_HEAD=VE_DDRA +XT_DDRA: + .dw PFA_DOVARIABLE +PFA_DDRA: + .dw 33 +; ( -- addr ) System Constant +; R( -- ) +; Port A Input Pins +VE_PINA: + .dw $ff04 + .db "PINA" + .dw VE_HEAD + .set VE_HEAD=VE_PINA +XT_PINA: + .dw PFA_DOVARIABLE +PFA_PINA: + .dw 32 + +.endif +.if WANT_PORTB == 1 +; ( -- addr ) System Constant +; R( -- ) +; Port B Data Register +VE_PORTB: + .dw $ff05 + .db "PORTB",0 + .dw VE_HEAD + .set VE_HEAD=VE_PORTB +XT_PORTB: + .dw PFA_DOVARIABLE +PFA_PORTB: + .dw 37 +; ( -- addr ) System Constant +; R( -- ) +; Port B Data Direction Register +VE_DDRB: + .dw $ff04 + .db "DDRB" + .dw VE_HEAD + .set VE_HEAD=VE_DDRB +XT_DDRB: + .dw PFA_DOVARIABLE +PFA_DDRB: + .dw 36 +; ( -- addr ) System Constant +; R( -- ) +; Port B Input Pins +VE_PINB: + .dw $ff04 + .db "PINB" + .dw VE_HEAD + .set VE_HEAD=VE_PINB +XT_PINB: + .dw PFA_DOVARIABLE +PFA_PINB: + .dw 35 + +.endif +.if WANT_PORTC == 1 +; ( -- addr ) System Constant +; R( -- ) +; Port C Data Register +VE_PORTC: + .dw $ff05 + .db "PORTC",0 + .dw VE_HEAD + .set VE_HEAD=VE_PORTC +XT_PORTC: + .dw PFA_DOVARIABLE +PFA_PORTC: + .dw 40 +; ( -- addr ) System Constant +; R( -- ) +; Port C Data Direction Register +VE_DDRC: + .dw $ff04 + .db "DDRC" + .dw VE_HEAD + .set VE_HEAD=VE_DDRC +XT_DDRC: + .dw PFA_DOVARIABLE +PFA_DDRC: + .dw 39 +; ( -- addr ) System Constant +; R( -- ) +; Port C Input Pins +VE_PINC: + .dw $ff04 + .db "PINC" + .dw VE_HEAD + .set VE_HEAD=VE_PINC +XT_PINC: + .dw PFA_DOVARIABLE +PFA_PINC: + .dw 38 + +.endif +.if WANT_PORTD == 1 +; ( -- addr ) System Constant +; R( -- ) +; Port D Data Register +VE_PORTD: + .dw $ff05 + .db "PORTD",0 + .dw VE_HEAD + .set VE_HEAD=VE_PORTD +XT_PORTD: + .dw PFA_DOVARIABLE +PFA_PORTD: + .dw 43 +; ( -- addr ) System Constant +; R( -- ) +; Port D Data Direction Register +VE_DDRD: + .dw $ff04 + .db "DDRD" + .dw VE_HEAD + .set VE_HEAD=VE_DDRD +XT_DDRD: + .dw PFA_DOVARIABLE +PFA_DDRD: + .dw 42 +; ( -- addr ) System Constant +; R( -- ) +; Port D Input Pins +VE_PIND: + .dw $ff04 + .db "PIND" + .dw VE_HEAD + .set VE_HEAD=VE_PIND +XT_PIND: + .dw PFA_DOVARIABLE +PFA_PIND: + .dw 41 + +.endif +.if WANT_PORTE == 1 +; ( -- addr ) System Constant +; R( -- ) +; Data Register, Port E +VE_PORTE: + .dw $ff05 + .db "PORTE",0 + .dw VE_HEAD + .set VE_HEAD=VE_PORTE +XT_PORTE: + .dw PFA_DOVARIABLE +PFA_PORTE: + .dw 46 +; ( -- addr ) System Constant +; R( -- ) +; Data Direction Register, Port E +VE_DDRE: + .dw $ff04 + .db "DDRE" + .dw VE_HEAD + .set VE_HEAD=VE_DDRE +XT_DDRE: + .dw PFA_DOVARIABLE +PFA_DDRE: + .dw 45 +; ( -- addr ) System Constant +; R( -- ) +; Input Pins, Port E +VE_PINE: + .dw $ff04 + .db "PINE" + .dw VE_HEAD + .set VE_HEAD=VE_PINE +XT_PINE: + .dw PFA_DOVARIABLE +PFA_PINE: + .dw 44 + +.endif +.if WANT_PORTF == 1 +; ( -- addr ) System Constant +; R( -- ) +; Data Register, Port F +VE_PORTF: + .dw $ff05 + .db "PORTF",0 + .dw VE_HEAD + .set VE_HEAD=VE_PORTF +XT_PORTF: + .dw PFA_DOVARIABLE +PFA_PORTF: + .dw 49 +; ( -- addr ) System Constant +; R( -- ) +; Data Direction Register, Port F +VE_DDRF: + .dw $ff04 + .db "DDRF" + .dw VE_HEAD + .set VE_HEAD=VE_DDRF +XT_DDRF: + .dw PFA_DOVARIABLE +PFA_DDRF: + .dw 48 +; ( -- addr ) System Constant +; R( -- ) +; Input Pins, Port F +VE_PINF: + .dw $ff04 + .db "PINF" + .dw VE_HEAD + .set VE_HEAD=VE_PINF +XT_PINF: + .dw PFA_DOVARIABLE +PFA_PINF: + .dw 47 + +.endif +.if WANT_PORTG == 1 +; ( -- addr ) System Constant +; R( -- ) +; Data Register, Port G +VE_PORTG: + .dw $ff05 + .db "PORTG",0 + .dw VE_HEAD + .set VE_HEAD=VE_PORTG +XT_PORTG: + .dw PFA_DOVARIABLE +PFA_PORTG: + .dw 52 +; ( -- addr ) System Constant +; R( -- ) +; Data Direction Register, Port G +VE_DDRG: + .dw $ff04 + .db "DDRG" + .dw VE_HEAD + .set VE_HEAD=VE_DDRG +XT_DDRG: + .dw PFA_DOVARIABLE +PFA_DDRG: + .dw 51 +; ( -- addr ) System Constant +; R( -- ) +; Input Pins, Port G +VE_PING: + .dw $ff04 + .db "PING" + .dw VE_HEAD + .set VE_HEAD=VE_PING +XT_PING: + .dw PFA_DOVARIABLE +PFA_PING: + .dw 50 + +.endif +.if WANT_JTAG == 1 +; ( -- addr ) System Constant +; R( -- ) +; On-Chip Debug Related Register in I/O Memory +VE_OCDR: + .dw $ff04 + .db "OCDR" + .dw VE_HEAD + .set VE_HEAD=VE_OCDR +XT_OCDR: + .dw PFA_DOVARIABLE +PFA_OCDR: + .dw 81 +; ( -- addr ) System Constant +; R( -- ) +; MCU Control Register +VE_MCUCR: + .dw $ff05 + .db "MCUCR",0 + .dw VE_HEAD + .set VE_HEAD=VE_MCUCR +XT_MCUCR: + .dw PFA_DOVARIABLE +PFA_MCUCR: + .dw 85 +; ( -- addr ) System Constant +; R( -- ) +; MCU Status Register +VE_MCUSR: + .dw $ff05 + .db "MCUSR",0 + .dw VE_HEAD + .set VE_HEAD=VE_MCUSR +XT_MCUSR: + .dw PFA_DOVARIABLE +PFA_MCUSR: + .dw 84 + +.endif +.if WANT_SPI == 1 +; ( -- addr ) System Constant +; R( -- ) +; SPI Control Register +VE_SPCR: + .dw $ff04 + .db "SPCR" + .dw VE_HEAD + .set VE_HEAD=VE_SPCR +XT_SPCR: + .dw PFA_DOVARIABLE +PFA_SPCR: + .dw 76 +; ( -- addr ) System Constant +; R( -- ) +; SPI Status Register +VE_SPSR: + .dw $ff04 + .db "SPSR" + .dw VE_HEAD + .set VE_HEAD=VE_SPSR +XT_SPSR: + .dw PFA_DOVARIABLE +PFA_SPSR: + .dw 77 +; ( -- addr ) System Constant +; R( -- ) +; SPI Data Register +VE_SPDR: + .dw $ff04 + .db "SPDR" + .dw VE_HEAD + .set VE_HEAD=VE_SPDR +XT_SPDR: + .dw PFA_DOVARIABLE +PFA_SPDR: + .dw 78 + +.endif +.if WANT_TWI == 1 +; ( -- addr ) System Constant +; R( -- ) +; TWI Bit Rate register +VE_TWBR: + .dw $ff04 + .db "TWBR" + .dw VE_HEAD + .set VE_HEAD=VE_TWBR +XT_TWBR: + .dw PFA_DOVARIABLE +PFA_TWBR: + .dw 184 +; ( -- addr ) System Constant +; R( -- ) +; TWI Control Register +VE_TWCR: + .dw $ff04 + .db "TWCR" + .dw VE_HEAD + .set VE_HEAD=VE_TWCR +XT_TWCR: + .dw PFA_DOVARIABLE +PFA_TWCR: + .dw 188 +; ( -- addr ) System Constant +; R( -- ) +; TWI Status Register +VE_TWSR: + .dw $ff04 + .db "TWSR" + .dw VE_HEAD + .set VE_HEAD=VE_TWSR +XT_TWSR: + .dw PFA_DOVARIABLE +PFA_TWSR: + .dw 185 +; ( -- addr ) System Constant +; R( -- ) +; TWI Data register +VE_TWDR: + .dw $ff04 + .db "TWDR" + .dw VE_HEAD + .set VE_HEAD=VE_TWDR +XT_TWDR: + .dw PFA_DOVARIABLE +PFA_TWDR: + .dw 187 +; ( -- addr ) System Constant +; R( -- ) +; TWI (Slave) Address register +VE_TWAR: + .dw $ff04 + .db "TWAR" + .dw VE_HEAD + .set VE_HEAD=VE_TWAR +XT_TWAR: + .dw PFA_DOVARIABLE +PFA_TWAR: + .dw 186 + +.endif +.if WANT_USART0 == 1 +; ( -- addr ) System Constant +; R( -- ) +; USART I/O Data Register +VE_UDR0: + .dw $ff04 + .db "UDR0" + .dw VE_HEAD + .set VE_HEAD=VE_UDR0 +XT_UDR0: + .dw PFA_DOVARIABLE +PFA_UDR0: + .dw 198 +; ( -- addr ) System Constant +; R( -- ) +; USART Control and Status Register A +VE_UCSR0A: + .dw $ff06 + .db "UCSR0A" + .dw VE_HEAD + .set VE_HEAD=VE_UCSR0A +XT_UCSR0A: + .dw PFA_DOVARIABLE +PFA_UCSR0A: + .dw 192 +; ( -- addr ) System Constant +; R( -- ) +; USART Control and Status Register B +VE_UCSR0B: + .dw $ff06 + .db "UCSR0B" + .dw VE_HEAD + .set VE_HEAD=VE_UCSR0B +XT_UCSR0B: + .dw PFA_DOVARIABLE +PFA_UCSR0B: + .dw 193 +; ( -- addr ) System Constant +; R( -- ) +; USART Control and Status Register C +VE_UCSR0C: + .dw $ff06 + .db "UCSR0C" + .dw VE_HEAD + .set VE_HEAD=VE_UCSR0C +XT_UCSR0C: + .dw PFA_DOVARIABLE +PFA_UCSR0C: + .dw 194 +; ( -- addr ) System Constant +; R( -- ) +; USART Baud Rate Register t Bytes +VE_UBRR0: + .dw $ff05 + .db "UBRR0",0 + .dw VE_HEAD + .set VE_HEAD=VE_UBRR0 +XT_UBRR0: + .dw PFA_DOVARIABLE +PFA_UBRR0: + .dw 196 + +.endif +.if WANT_USART1 == 1 +; ( -- addr ) System Constant +; R( -- ) +; USART I/O Data Register +VE_UDR1: + .dw $ff04 + .db "UDR1" + .dw VE_HEAD + .set VE_HEAD=VE_UDR1 +XT_UDR1: + .dw PFA_DOVARIABLE +PFA_UDR1: + .dw 206 +; ( -- addr ) System Constant +; R( -- ) +; USART Control and Status Register A +VE_UCSR1A: + .dw $ff06 + .db "UCSR1A" + .dw VE_HEAD + .set VE_HEAD=VE_UCSR1A +XT_UCSR1A: + .dw PFA_DOVARIABLE +PFA_UCSR1A: + .dw 200 +; ( -- addr ) System Constant +; R( -- ) +; USART Control and Status Register B +VE_UCSR1B: + .dw $ff06 + .db "UCSR1B" + .dw VE_HEAD + .set VE_HEAD=VE_UCSR1B +XT_UCSR1B: + .dw PFA_DOVARIABLE +PFA_UCSR1B: + .dw 201 +; ( -- addr ) System Constant +; R( -- ) +; USART Control and Status Register C +VE_UCSR1C: + .dw $ff06 + .db "UCSR1C" + .dw VE_HEAD + .set VE_HEAD=VE_UCSR1C +XT_UCSR1C: + .dw PFA_DOVARIABLE +PFA_UCSR1C: + .dw 202 +; ( -- addr ) System Constant +; R( -- ) +; USART Baud Rate Register t Bytes +VE_UBRR1: + .dw $ff05 + .db "UBRR1",0 + .dw VE_HEAD + .set VE_HEAD=VE_UBRR1 +XT_UBRR1: + .dw PFA_DOVARIABLE +PFA_UBRR1: + .dw 204 + +.endif +.if WANT_CPU == 1 +; ( -- addr ) System Constant +; R( -- ) +; Status Register +VE_SREG: + .dw $ff04 + .db "SREG" + .dw VE_HEAD + .set VE_HEAD=VE_SREG +XT_SREG: + .dw PFA_DOVARIABLE +PFA_SREG: + .dw 95 +; ( -- addr ) System Constant +; R( -- ) +; Stack Pointer +VE_SP: + .dw $ff02 + .db "SP" + .dw VE_HEAD + .set VE_HEAD=VE_SP +XT_SP: + .dw PFA_DOVARIABLE +PFA_SP: + .dw 93 +; ( -- addr ) System Constant +; R( -- ) +; External Memory Control Register A +VE_XMCRA: + .dw $ff05 + .db "XMCRA",0 + .dw VE_HEAD + .set VE_HEAD=VE_XMCRA +XT_XMCRA: + .dw PFA_DOVARIABLE +PFA_XMCRA: + .dw 116 +; ( -- addr ) System Constant +; R( -- ) +; External Memory Control Register B +VE_XMCRB: + .dw $ff05 + .db "XMCRB",0 + .dw VE_HEAD + .set VE_HEAD=VE_XMCRB +XT_XMCRB: + .dw PFA_DOVARIABLE +PFA_XMCRB: + .dw 117 +; ( -- addr ) System Constant +; R( -- ) +; Oscillator Calibration Value +VE_OSCCAL: + .dw $ff06 + .db "OSCCAL" + .dw VE_HEAD + .set VE_HEAD=VE_OSCCAL +XT_OSCCAL: + .dw PFA_DOVARIABLE +PFA_OSCCAL: + .dw 102 +; ( -- addr ) System Constant +; R( -- ) +; Clock Prescale Register +VE_CLKPR: + .dw $ff05 + .db "CLKPR",0 + .dw VE_HEAD + .set VE_HEAD=VE_CLKPR +XT_CLKPR: + .dw PFA_DOVARIABLE +PFA_CLKPR: + .dw 97 +; ( -- addr ) System Constant +; R( -- ) +; Sleep Mode Control Register +VE_SMCR: + .dw $ff04 + .db "SMCR" + .dw VE_HEAD + .set VE_HEAD=VE_SMCR +XT_SMCR: + .dw PFA_DOVARIABLE +PFA_SMCR: + .dw 83 +; ( -- addr ) System Constant +; R( -- ) +; RAM Page Z Select Register - Not used. +VE_RAMPZ: + .dw $ff05 + .db "RAMPZ",0 + .dw VE_HEAD + .set VE_HEAD=VE_RAMPZ +XT_RAMPZ: + .dw PFA_DOVARIABLE +PFA_RAMPZ: + .dw 91 +; ( -- addr ) System Constant +; R( -- ) +; General Purpose IO Register 2 +VE_GPIOR2: + .dw $ff06 + .db "GPIOR2" + .dw VE_HEAD + .set VE_HEAD=VE_GPIOR2 +XT_GPIOR2: + .dw PFA_DOVARIABLE +PFA_GPIOR2: + .dw 75 +; ( -- addr ) System Constant +; R( -- ) +; General Purpose IO Register 1 +VE_GPIOR1: + .dw $ff06 + .db "GPIOR1" + .dw VE_HEAD + .set VE_HEAD=VE_GPIOR1 +XT_GPIOR1: + .dw PFA_DOVARIABLE +PFA_GPIOR1: + .dw 74 +; ( -- addr ) System Constant +; R( -- ) +; General Purpose IO Register 0 +VE_GPIOR0: + .dw $ff06 + .db "GPIOR0" + .dw VE_HEAD + .set VE_HEAD=VE_GPIOR0 +XT_GPIOR0: + .dw PFA_DOVARIABLE +PFA_GPIOR0: + .dw 62 + +.endif +.if WANT_BOOT_LOAD == 1 +; ( -- addr ) System Constant +; R( -- ) +; Store Program Memory Control Register +VE_SPMCSR: + .dw $ff06 + .db "SPMCSR" + .dw VE_HEAD + .set VE_HEAD=VE_SPMCSR +XT_SPMCSR: + .dw PFA_DOVARIABLE +PFA_SPMCSR: + .dw 87 + +.endif +.if WANT_EXTERNAL_INTERRUPT == 1 +; ( -- addr ) System Constant +; R( -- ) +; External Interrupt Control Register A +VE_EICRA: + .dw $ff05 + .db "EICRA",0 + .dw VE_HEAD + .set VE_HEAD=VE_EICRA +XT_EICRA: + .dw PFA_DOVARIABLE +PFA_EICRA: + .dw 105 +; ( -- addr ) System Constant +; R( -- ) +; External Interrupt Control Register B +VE_EICRB: + .dw $ff05 + .db "EICRB",0 + .dw VE_HEAD + .set VE_HEAD=VE_EICRB +XT_EICRB: + .dw PFA_DOVARIABLE +PFA_EICRB: + .dw 106 +; ( -- addr ) System Constant +; R( -- ) +; External Interrupt Mask Register +VE_EIMSK: + .dw $ff05 + .db "EIMSK",0 + .dw VE_HEAD + .set VE_HEAD=VE_EIMSK +XT_EIMSK: + .dw PFA_DOVARIABLE +PFA_EIMSK: + .dw 61 +; ( -- addr ) System Constant +; R( -- ) +; External Interrupt Flag Register +VE_EIFR: + .dw $ff04 + .db "EIFR" + .dw VE_HEAD + .set VE_HEAD=VE_EIFR +XT_EIFR: + .dw PFA_DOVARIABLE +PFA_EIFR: + .dw 60 + +.endif +.if WANT_EEPROM == 1 +; ( -- addr ) System Constant +; R( -- ) +; EEPROM Read/Write Access Bytes +VE_EEAR: + .dw $ff04 + .db "EEAR" + .dw VE_HEAD + .set VE_HEAD=VE_EEAR +XT_EEAR: + .dw PFA_DOVARIABLE +PFA_EEAR: + .dw 65 +; ( -- addr ) System Constant +; R( -- ) +; EEPROM Data Register +VE_EEDR: + .dw $ff04 + .db "EEDR" + .dw VE_HEAD + .set VE_HEAD=VE_EEDR +XT_EEDR: + .dw PFA_DOVARIABLE +PFA_EEDR: + .dw 64 +; ( -- addr ) System Constant +; R( -- ) +; EEPROM Control Register +VE_EECR: + .dw $ff04 + .db "EECR" + .dw VE_HEAD + .set VE_HEAD=VE_EECR +XT_EECR: + .dw PFA_DOVARIABLE +PFA_EECR: + .dw 63 + +.endif +.if WANT_TIMER_COUNTER_0 == 1 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter0 Control Register +VE_TCCR0A: + .dw $ff06 + .db "TCCR0A" + .dw VE_HEAD + .set VE_HEAD=VE_TCCR0A +XT_TCCR0A: + .dw PFA_DOVARIABLE +PFA_TCCR0A: + .dw 68 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter0 +VE_TCNT0: + .dw $ff05 + .db "TCNT0",0 + .dw VE_HEAD + .set VE_HEAD=VE_TCNT0 +XT_TCNT0: + .dw PFA_DOVARIABLE +PFA_TCNT0: + .dw 70 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter0 Output Compare Register +VE_OCR0A: + .dw $ff05 + .db "OCR0A",0 + .dw VE_HEAD + .set VE_HEAD=VE_OCR0A +XT_OCR0A: + .dw PFA_DOVARIABLE +PFA_OCR0A: + .dw 71 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter0 Interrupt Mask Register +VE_TIMSK0: + .dw $ff06 + .db "TIMSK0" + .dw VE_HEAD + .set VE_HEAD=VE_TIMSK0 +XT_TIMSK0: + .dw PFA_DOVARIABLE +PFA_TIMSK0: + .dw 110 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter0 Interrupt Flag register +VE_TIFR0: + .dw $ff05 + .db "TIFR0",0 + .dw VE_HEAD + .set VE_HEAD=VE_TIFR0 +XT_TIFR0: + .dw PFA_DOVARIABLE +PFA_TIFR0: + .dw 53 +; ( -- addr ) System Constant +; R( -- ) +; General Timer/Control Register +VE_GTCCR: + .dw $ff05 + .db "GTCCR",0 + .dw VE_HEAD + .set VE_HEAD=VE_GTCCR +XT_GTCCR: + .dw PFA_DOVARIABLE +PFA_GTCCR: + .dw 67 + +.endif +.if WANT_TIMER_COUNTER_2 == 1 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter2 Control Register +VE_TCCR2: + .dw $ff05 + .db "TCCR2",0 + .dw VE_HEAD + .set VE_HEAD=VE_TCCR2 +XT_TCCR2: + .dw PFA_DOVARIABLE +PFA_TCCR2: + .dw 176 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter2 +VE_TCNT2: + .dw $ff05 + .db "TCNT2",0 + .dw VE_HEAD + .set VE_HEAD=VE_TCNT2 +XT_TCNT2: + .dw PFA_DOVARIABLE +PFA_TCNT2: + .dw 178 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter2 Output Compare Register +VE_OCR2A: + .dw $ff05 + .db "OCR2A",0 + .dw VE_HEAD + .set VE_HEAD=VE_OCR2A +XT_OCR2A: + .dw PFA_DOVARIABLE +PFA_OCR2A: + .dw 179 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter Interrupt Mask register +VE_TIMSK2: + .dw $ff06 + .db "TIMSK2" + .dw VE_HEAD + .set VE_HEAD=VE_TIMSK2 +XT_TIMSK2: + .dw PFA_DOVARIABLE +PFA_TIMSK2: + .dw 112 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter Interrupt Flag Register +VE_TIFR2: + .dw $ff05 + .db "TIFR2",0 + .dw VE_HEAD + .set VE_HEAD=VE_TIFR2 +XT_TIFR2: + .dw PFA_DOVARIABLE +PFA_TIFR2: + .dw 55 +; ( -- addr ) System Constant +; R( -- ) +; Asynchronous Status Register +VE_ASSR: + .dw $ff04 + .db "ASSR" + .dw VE_HEAD + .set VE_HEAD=VE_ASSR +XT_ASSR: + .dw PFA_DOVARIABLE +PFA_ASSR: + .dw 182 + +.endif +.if WANT_TIMER_COUNTER_1 == 1 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter1 Control Register A +VE_TCCR1A: + .dw $ff06 + .db "TCCR1A" + .dw VE_HEAD + .set VE_HEAD=VE_TCCR1A +XT_TCCR1A: + .dw PFA_DOVARIABLE +PFA_TCCR1A: + .dw 128 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter1 Control Register B +VE_TCCR1B: + .dw $ff06 + .db "TCCR1B" + .dw VE_HEAD + .set VE_HEAD=VE_TCCR1B +XT_TCCR1B: + .dw PFA_DOVARIABLE +PFA_TCCR1B: + .dw 129 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter 1 Control Register C +VE_TCCR1C: + .dw $ff06 + .db "TCCR1C" + .dw VE_HEAD + .set VE_HEAD=VE_TCCR1C +XT_TCCR1C: + .dw PFA_DOVARIABLE +PFA_TCCR1C: + .dw 130 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter1 Bytes +VE_TCNT1: + .dw $ff05 + .db "TCNT1",0 + .dw VE_HEAD + .set VE_HEAD=VE_TCNT1 +XT_TCNT1: + .dw PFA_DOVARIABLE +PFA_TCNT1: + .dw 132 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter1 Output Compare Register Bytes +VE_OCR1A: + .dw $ff05 + .db "OCR1A",0 + .dw VE_HEAD + .set VE_HEAD=VE_OCR1A +XT_OCR1A: + .dw PFA_DOVARIABLE +PFA_OCR1A: + .dw 136 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter1 Output Compare Register Bytes +VE_OCR1B: + .dw $ff05 + .db "OCR1B",0 + .dw VE_HEAD + .set VE_HEAD=VE_OCR1B +XT_OCR1B: + .dw PFA_DOVARIABLE +PFA_OCR1B: + .dw 138 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter1 Output Compare Register Bytes +VE_OCR1C: + .dw $ff05 + .db "OCR1C",0 + .dw VE_HEAD + .set VE_HEAD=VE_OCR1C +XT_OCR1C: + .dw PFA_DOVARIABLE +PFA_OCR1C: + .dw 140 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter1 Input Capture Register Bytes +VE_ICR1: + .dw $ff04 + .db "ICR1" + .dw VE_HEAD + .set VE_HEAD=VE_ICR1 +XT_ICR1: + .dw PFA_DOVARIABLE +PFA_ICR1: + .dw 134 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter Interrupt Mask Register +VE_TIMSK1: + .dw $ff06 + .db "TIMSK1" + .dw VE_HEAD + .set VE_HEAD=VE_TIMSK1 +XT_TIMSK1: + .dw PFA_DOVARIABLE +PFA_TIMSK1: + .dw 111 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter Interrupt Flag register +VE_TIFR1: + .dw $ff05 + .db "TIFR1",0 + .dw VE_HEAD + .set VE_HEAD=VE_TIFR1 +XT_TIFR1: + .dw PFA_DOVARIABLE +PFA_TIFR1: + .dw 54 + +.endif +.if WANT_TIMER_COUNTER_3 == 1 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter3 Control Register A +VE_TCCR3A: + .dw $ff06 + .db "TCCR3A" + .dw VE_HEAD + .set VE_HEAD=VE_TCCR3A +XT_TCCR3A: + .dw PFA_DOVARIABLE +PFA_TCCR3A: + .dw 144 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter3 Control Register B +VE_TCCR3B: + .dw $ff06 + .db "TCCR3B" + .dw VE_HEAD + .set VE_HEAD=VE_TCCR3B +XT_TCCR3B: + .dw PFA_DOVARIABLE +PFA_TCCR3B: + .dw 145 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter 3 Control Register C +VE_TCCR3C: + .dw $ff06 + .db "TCCR3C" + .dw VE_HEAD + .set VE_HEAD=VE_TCCR3C +XT_TCCR3C: + .dw PFA_DOVARIABLE +PFA_TCCR3C: + .dw 146 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter3 Bytes +VE_TCNT3: + .dw $ff05 + .db "TCNT3",0 + .dw VE_HEAD + .set VE_HEAD=VE_TCNT3 +XT_TCNT3: + .dw PFA_DOVARIABLE +PFA_TCNT3: + .dw 148 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter3 Output Compare Register Bytes +VE_OCR3A: + .dw $ff05 + .db "OCR3A",0 + .dw VE_HEAD + .set VE_HEAD=VE_OCR3A +XT_OCR3A: + .dw PFA_DOVARIABLE +PFA_OCR3A: + .dw 152 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter3 Output Compare Register Bytes +VE_OCR3B: + .dw $ff05 + .db "OCR3B",0 + .dw VE_HEAD + .set VE_HEAD=VE_OCR3B +XT_OCR3B: + .dw PFA_DOVARIABLE +PFA_OCR3B: + .dw 154 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter3 Output Compare Register Bytes +VE_OCR3C: + .dw $ff05 + .db "OCR3C",0 + .dw VE_HEAD + .set VE_HEAD=VE_OCR3C +XT_OCR3C: + .dw PFA_DOVARIABLE +PFA_OCR3C: + .dw 156 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter3 Input Capture Register Bytes +VE_ICR3: + .dw $ff04 + .db "ICR3" + .dw VE_HEAD + .set VE_HEAD=VE_ICR3 +XT_ICR3: + .dw PFA_DOVARIABLE +PFA_ICR3: + .dw 150 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter Interrupt Mask Register +VE_TIMSK3: + .dw $ff06 + .db "TIMSK3" + .dw VE_HEAD + .set VE_HEAD=VE_TIMSK3 +XT_TIMSK3: + .dw PFA_DOVARIABLE +PFA_TIMSK3: + .dw 113 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter Interrupt Flag register +VE_TIFR3: + .dw $ff05 + .db "TIFR3",0 + .dw VE_HEAD + .set VE_HEAD=VE_TIFR3 +XT_TIFR3: + .dw PFA_DOVARIABLE +PFA_TIFR3: + .dw 56 + +.endif +.if WANT_WATCHDOG == 1 +; ( -- addr ) System Constant +; R( -- ) +; Watchdog Timer Control Register +VE_WDTCR: + .dw $ff05 + .db "WDTCR",0 + .dw VE_HEAD + .set VE_HEAD=VE_WDTCR +XT_WDTCR: + .dw PFA_DOVARIABLE +PFA_WDTCR: + .dw 96 + +.endif +.if WANT_AD_CONVERTER == 1 +; ( -- addr ) System Constant +; R( -- ) +; The ADC multiplexer Selection Register +VE_ADMUX: + .dw $ff05 + .db "ADMUX",0 + .dw VE_HEAD + .set VE_HEAD=VE_ADMUX +XT_ADMUX: + .dw PFA_DOVARIABLE +PFA_ADMUX: + .dw 124 +; ( -- addr ) System Constant +; R( -- ) +; The ADC Control and Status register +VE_ADCSRA: + .dw $ff06 + .db "ADCSRA" + .dw VE_HEAD + .set VE_HEAD=VE_ADCSRA +XT_ADCSRA: + .dw PFA_DOVARIABLE +PFA_ADCSRA: + .dw 122 +; ( -- addr ) System Constant +; R( -- ) +; ADC Data Register Bytes +VE_ADC: + .dw $ff03 + .db "ADC",0 + .dw VE_HEAD + .set VE_HEAD=VE_ADC +XT_ADC: + .dw PFA_DOVARIABLE +PFA_ADC: + .dw 120 +; ( -- addr ) System Constant +; R( -- ) +; ADC Control and Status Register B +VE_ADCSRB: + .dw $ff06 + .db "ADCSRB" + .dw VE_HEAD + .set VE_HEAD=VE_ADCSRB +XT_ADCSRB: + .dw PFA_DOVARIABLE +PFA_ADCSRB: + .dw 123 +; ( -- addr ) System Constant +; R( -- ) +; Digital Input Disable Register 1 +VE_DIDR0: + .dw $ff05 + .db "DIDR0",0 + .dw VE_HEAD + .set VE_HEAD=VE_DIDR0 +XT_DIDR0: + .dw PFA_DOVARIABLE +PFA_DIDR0: + .dw 126 + +.endif +.if WANT_ANALOG_COMPARATOR == 1 +; ( -- addr ) System Constant +; R( -- ) +; Analog Comparator Control And Status Register +VE_ACSR: + .dw $ff04 + .db "ACSR" + .dw VE_HEAD + .set VE_HEAD=VE_ACSR +XT_ACSR: + .dw PFA_DOVARIABLE +PFA_ACSR: + .dw 80 +; ( -- addr ) System Constant +; R( -- ) +; +VE_DIDR1: + .dw $ff05 + .db "DIDR1",0 + .dw VE_HEAD + .set VE_HEAD=VE_DIDR1 +XT_DIDR1: + .dw PFA_DOVARIABLE +PFA_DIDR1: + .dw 127 + +.endif +.if WANT_CAN == 1 +; ( -- addr ) System Constant +; R( -- ) +; CAN General Control Register +VE_CANGCON: + .dw $ff07 + .db "CANGCON",0 + .dw VE_HEAD + .set VE_HEAD=VE_CANGCON +XT_CANGCON: + .dw PFA_DOVARIABLE +PFA_CANGCON: + .dw 216 +; ( -- addr ) System Constant +; R( -- ) +; CAN General Status Register +VE_CANGSTA: + .dw $ff07 + .db "CANGSTA",0 + .dw VE_HEAD + .set VE_HEAD=VE_CANGSTA +XT_CANGSTA: + .dw PFA_DOVARIABLE +PFA_CANGSTA: + .dw 217 +; ( -- addr ) System Constant +; R( -- ) +; CAN General Interrupt Register +VE_CANGIT: + .dw $ff06 + .db "CANGIT" + .dw VE_HEAD + .set VE_HEAD=VE_CANGIT +XT_CANGIT: + .dw PFA_DOVARIABLE +PFA_CANGIT: + .dw 218 +; ( -- addr ) System Constant +; R( -- ) +; CAN General Interrupt Enable Register +VE_CANGIE: + .dw $ff06 + .db "CANGIE" + .dw VE_HEAD + .set VE_HEAD=VE_CANGIE +XT_CANGIE: + .dw PFA_DOVARIABLE +PFA_CANGIE: + .dw 219 +; ( -- addr ) System Constant +; R( -- ) +; Enable MOb Register +VE_CANEN2: + .dw $ff06 + .db "CANEN2" + .dw VE_HEAD + .set VE_HEAD=VE_CANEN2 +XT_CANEN2: + .dw PFA_DOVARIABLE +PFA_CANEN2: + .dw 220 +; ( -- addr ) System Constant +; R( -- ) +; Enable MOb Register +VE_CANEN1: + .dw $ff06 + .db "CANEN1" + .dw VE_HEAD + .set VE_HEAD=VE_CANEN1 +XT_CANEN1: + .dw PFA_DOVARIABLE +PFA_CANEN1: + .dw 221 +; ( -- addr ) System Constant +; R( -- ) +; Enable Interrupt MOb Register +VE_CANIE2: + .dw $ff06 + .db "CANIE2" + .dw VE_HEAD + .set VE_HEAD=VE_CANIE2 +XT_CANIE2: + .dw PFA_DOVARIABLE +PFA_CANIE2: + .dw 222 +; ( -- addr ) System Constant +; R( -- ) +; Enable Interrupt MOb Register +VE_CANIE1: + .dw $ff06 + .db "CANIE1" + .dw VE_HEAD + .set VE_HEAD=VE_CANIE1 +XT_CANIE1: + .dw PFA_DOVARIABLE +PFA_CANIE1: + .dw 223 +; ( -- addr ) System Constant +; R( -- ) +; CAN Status Interrupt MOb Register +VE_CANSIT2: + .dw $ff07 + .db "CANSIT2",0 + .dw VE_HEAD + .set VE_HEAD=VE_CANSIT2 +XT_CANSIT2: + .dw PFA_DOVARIABLE +PFA_CANSIT2: + .dw 224 +; ( -- addr ) System Constant +; R( -- ) +; CAN Status Interrupt MOb Register +VE_CANSIT1: + .dw $ff07 + .db "CANSIT1",0 + .dw VE_HEAD + .set VE_HEAD=VE_CANSIT1 +XT_CANSIT1: + .dw PFA_DOVARIABLE +PFA_CANSIT1: + .dw 225 +; ( -- addr ) System Constant +; R( -- ) +; Bit Timing Register 1 +VE_CANBT1: + .dw $ff06 + .db "CANBT1" + .dw VE_HEAD + .set VE_HEAD=VE_CANBT1 +XT_CANBT1: + .dw PFA_DOVARIABLE +PFA_CANBT1: + .dw 226 +; ( -- addr ) System Constant +; R( -- ) +; Bit Timing Register 2 +VE_CANBT2: + .dw $ff06 + .db "CANBT2" + .dw VE_HEAD + .set VE_HEAD=VE_CANBT2 +XT_CANBT2: + .dw PFA_DOVARIABLE +PFA_CANBT2: + .dw 227 +; ( -- addr ) System Constant +; R( -- ) +; Bit Timing Register 3 +VE_CANBT3: + .dw $ff06 + .db "CANBT3" + .dw VE_HEAD + .set VE_HEAD=VE_CANBT3 +XT_CANBT3: + .dw PFA_DOVARIABLE +PFA_CANBT3: + .dw 228 +; ( -- addr ) System Constant +; R( -- ) +; Timer Control Register +VE_CANTCON: + .dw $ff07 + .db "CANTCON",0 + .dw VE_HEAD + .set VE_HEAD=VE_CANTCON +XT_CANTCON: + .dw PFA_DOVARIABLE +PFA_CANTCON: + .dw 229 +; ( -- addr ) System Constant +; R( -- ) +; Timer Register Low +VE_CANTIML: + .dw $ff07 + .db "CANTIML",0 + .dw VE_HEAD + .set VE_HEAD=VE_CANTIML +XT_CANTIML: + .dw PFA_DOVARIABLE +PFA_CANTIML: + .dw 230 +; ( -- addr ) System Constant +; R( -- ) +; Timer Register High +VE_CANTIMH: + .dw $ff07 + .db "CANTIMH",0 + .dw VE_HEAD + .set VE_HEAD=VE_CANTIMH +XT_CANTIMH: + .dw PFA_DOVARIABLE +PFA_CANTIMH: + .dw 231 +; ( -- addr ) System Constant +; R( -- ) +; TTC Timer Register Low +VE_CANTTCL: + .dw $ff07 + .db "CANTTCL",0 + .dw VE_HEAD + .set VE_HEAD=VE_CANTTCL +XT_CANTTCL: + .dw PFA_DOVARIABLE +PFA_CANTTCL: + .dw 232 +; ( -- addr ) System Constant +; R( -- ) +; TTC Timer Register High +VE_CANTTCH: + .dw $ff07 + .db "CANTTCH",0 + .dw VE_HEAD + .set VE_HEAD=VE_CANTTCH +XT_CANTTCH: + .dw PFA_DOVARIABLE +PFA_CANTTCH: + .dw 233 +; ( -- addr ) System Constant +; R( -- ) +; Transmit Error Counter Register +VE_CANTEC: + .dw $ff06 + .db "CANTEC" + .dw VE_HEAD + .set VE_HEAD=VE_CANTEC +XT_CANTEC: + .dw PFA_DOVARIABLE +PFA_CANTEC: + .dw 234 +; ( -- addr ) System Constant +; R( -- ) +; Receive Error Counter Register +VE_CANREC: + .dw $ff06 + .db "CANREC" + .dw VE_HEAD + .set VE_HEAD=VE_CANREC +XT_CANREC: + .dw PFA_DOVARIABLE +PFA_CANREC: + .dw 235 +; ( -- addr ) System Constant +; R( -- ) +; Highest Priority MOb Register +VE_CANHPMOB: + .dw $ff08 + .db "CANHPMOB" + .dw VE_HEAD + .set VE_HEAD=VE_CANHPMOB +XT_CANHPMOB: + .dw PFA_DOVARIABLE +PFA_CANHPMOB: + .dw 236 +; ( -- addr ) System Constant +; R( -- ) +; Page MOb Register +VE_CANPAGE: + .dw $ff07 + .db "CANPAGE",0 + .dw VE_HEAD + .set VE_HEAD=VE_CANPAGE +XT_CANPAGE: + .dw PFA_DOVARIABLE +PFA_CANPAGE: + .dw 237 +; ( -- addr ) System Constant +; R( -- ) +; MOb Status Register +VE_CANSTMOB: + .dw $ff08 + .db "CANSTMOB" + .dw VE_HEAD + .set VE_HEAD=VE_CANSTMOB +XT_CANSTMOB: + .dw PFA_DOVARIABLE +PFA_CANSTMOB: + .dw 238 +; ( -- addr ) System Constant +; R( -- ) +; MOb Control and DLC Register +VE_CANCDMOB: + .dw $ff08 + .db "CANCDMOB" + .dw VE_HEAD + .set VE_HEAD=VE_CANCDMOB +XT_CANCDMOB: + .dw PFA_DOVARIABLE +PFA_CANCDMOB: + .dw 239 +; ( -- addr ) System Constant +; R( -- ) +; Identifier Tag Register 4 +VE_CANIDT4: + .dw $ff07 + .db "CANIDT4",0 + .dw VE_HEAD + .set VE_HEAD=VE_CANIDT4 +XT_CANIDT4: + .dw PFA_DOVARIABLE +PFA_CANIDT4: + .dw 240 +; ( -- addr ) System Constant +; R( -- ) +; Identifier Tag Register 3 +VE_CANIDT3: + .dw $ff07 + .db "CANIDT3",0 + .dw VE_HEAD + .set VE_HEAD=VE_CANIDT3 +XT_CANIDT3: + .dw PFA_DOVARIABLE +PFA_CANIDT3: + .dw 241 +; ( -- addr ) System Constant +; R( -- ) +; Identifier Tag Register 2 +VE_CANIDT2: + .dw $ff07 + .db "CANIDT2",0 + .dw VE_HEAD + .set VE_HEAD=VE_CANIDT2 +XT_CANIDT2: + .dw PFA_DOVARIABLE +PFA_CANIDT2: + .dw 242 +; ( -- addr ) System Constant +; R( -- ) +; Identifier Tag Register 1 +VE_CANIDT1: + .dw $ff07 + .db "CANIDT1",0 + .dw VE_HEAD + .set VE_HEAD=VE_CANIDT1 +XT_CANIDT1: + .dw PFA_DOVARIABLE +PFA_CANIDT1: + .dw 243 +; ( -- addr ) System Constant +; R( -- ) +; Identifier Mask Register 4 +VE_CANIDM4: + .dw $ff07 + .db "CANIDM4",0 + .dw VE_HEAD + .set VE_HEAD=VE_CANIDM4 +XT_CANIDM4: + .dw PFA_DOVARIABLE +PFA_CANIDM4: + .dw 244 +; ( -- addr ) System Constant +; R( -- ) +; Identifier Mask Register 3 +VE_CANIDM3: + .dw $ff07 + .db "CANIDM3",0 + .dw VE_HEAD + .set VE_HEAD=VE_CANIDM3 +XT_CANIDM3: + .dw PFA_DOVARIABLE +PFA_CANIDM3: + .dw 245 +; ( -- addr ) System Constant +; R( -- ) +; Identifier Mask Register 2 +VE_CANIDM2: + .dw $ff07 + .db "CANIDM2",0 + .dw VE_HEAD + .set VE_HEAD=VE_CANIDM2 +XT_CANIDM2: + .dw PFA_DOVARIABLE +PFA_CANIDM2: + .dw 246 +; ( -- addr ) System Constant +; R( -- ) +; Identifier Mask Register 1 +VE_CANIDM1: + .dw $ff07 + .db "CANIDM1",0 + .dw VE_HEAD + .set VE_HEAD=VE_CANIDM1 +XT_CANIDM1: + .dw PFA_DOVARIABLE +PFA_CANIDM1: + .dw 247 +; ( -- addr ) System Constant +; R( -- ) +; Time Stamp Register Low +VE_CANSTML: + .dw $ff07 + .db "CANSTML",0 + .dw VE_HEAD + .set VE_HEAD=VE_CANSTML +XT_CANSTML: + .dw PFA_DOVARIABLE +PFA_CANSTML: + .dw 248 +; ( -- addr ) System Constant +; R( -- ) +; Time Stamp Register High +VE_CANSTMH: + .dw $ff07 + .db "CANSTMH",0 + .dw VE_HEAD + .set VE_HEAD=VE_CANSTMH +XT_CANSTMH: + .dw PFA_DOVARIABLE +PFA_CANSTMH: + .dw 249 +; ( -- addr ) System Constant +; R( -- ) +; Message Data Register +VE_CANMSG: + .dw $ff06 + .db "CANMSG" + .dw VE_HEAD + .set VE_HEAD=VE_CANMSG +XT_CANMSG: + .dw PFA_DOVARIABLE +PFA_CANMSG: + .dw 250 + +.endif -- cgit v1.2.3