From d80736ab6e8e3cad2f1a30c6eaba2d6883dbe967 Mon Sep 17 00:00:00 2001 From: Dimitri Sokolyuk Date: Sat, 26 Aug 2017 20:31:40 +0200 Subject: Remove AmForth --- amforth-6.5/avr8/devices/at90can32/at90can32.frt | 465 ------ amforth-6.5/avr8/devices/at90can32/device.asm | 139 -- amforth-6.5/avr8/devices/at90can32/device.inc | 1707 -------------------- amforth-6.5/avr8/devices/at90can32/device.py | 507 ------ .../avr8/devices/at90can32/words/no-jtag.asm | 14 - .../avr8/devices/at90can32/words/no-wdt.asm | 22 - amforth-6.5/avr8/devices/at90can32/words/sleep.asm | 19 - 7 files changed, 2873 deletions(-) delete mode 100644 amforth-6.5/avr8/devices/at90can32/at90can32.frt delete mode 100644 amforth-6.5/avr8/devices/at90can32/device.asm delete mode 100644 amforth-6.5/avr8/devices/at90can32/device.inc delete mode 100644 amforth-6.5/avr8/devices/at90can32/device.py delete mode 100644 amforth-6.5/avr8/devices/at90can32/words/no-jtag.asm delete mode 100644 amforth-6.5/avr8/devices/at90can32/words/no-wdt.asm delete mode 100644 amforth-6.5/avr8/devices/at90can32/words/sleep.asm (limited to 'amforth-6.5/avr8/devices/at90can32') diff --git a/amforth-6.5/avr8/devices/at90can32/at90can32.frt b/amforth-6.5/avr8/devices/at90can32/at90can32.frt deleted file mode 100644 index 56a906a..0000000 --- a/amforth-6.5/avr8/devices/at90can32/at90can32.frt +++ /dev/null @@ -1,465 +0,0 @@ -\ Partname: AT90CAN32 -\ generated automatically - -\ PORTA -&34 constant PORTA \ Port A Data Register -&33 constant DDRA \ Port A Data Direction Register -&32 constant PINA \ Port A Input Pins -\ PORTB -&37 constant PORTB \ Port B Data Register -&36 constant DDRB \ Port B Data Direction Register -&35 constant PINB \ Port B Input Pins -\ PORTC -&40 constant PORTC \ Port C Data Register -&39 constant DDRC \ Port C Data Direction Register -&38 constant PINC \ Port C Input Pins -\ PORTD -&43 constant PORTD \ Port D Data Register -&42 constant DDRD \ Port D Data Direction Register -&41 constant PIND \ Port D Input Pins -\ PORTE -&46 constant PORTE \ Data Register, Port E -&45 constant DDRE \ Data Direction Register, Port E -&44 constant PINE \ Input Pins, Port E -\ PORTF -&49 constant PORTF \ Data Register, Port F -&48 constant DDRF \ Data Direction Register, Port F -&47 constant PINF \ Input Pins, Port F -\ PORTG -&52 constant PORTG \ Data Register, Port G -&51 constant DDRG \ Data Direction Register, Port G -&50 constant PING \ Input Pins, Port G -\ JTAG -&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory -&85 constant MCUCR \ MCU Control Register - $80 constant MCUCR_JTD \ JTAG Interface Disable -&84 constant MCUSR \ MCU Status Register - $10 constant MCUSR_JTRF \ JTAG Reset Flag -\ SPI -&76 constant SPCR \ SPI Control Register - $80 constant SPCR_SPIE \ SPI Interrupt Enable - $40 constant SPCR_SPE \ SPI Enable - $20 constant SPCR_DORD \ Data Order - $10 constant SPCR_MSTR \ Master/Slave Select - $08 constant SPCR_CPOL \ Clock polarity - $04 constant SPCR_CPHA \ Clock Phase - $03 constant SPCR_SPR \ SPI Clock Rate Selects -&77 constant SPSR \ SPI Status Register - $80 constant SPSR_SPIF \ SPI Interrupt Flag - $40 constant SPSR_WCOL \ Write Collision Flag - $01 constant SPSR_SPI2X \ Double SPI Speed Bit -&78 constant SPDR \ SPI Data Register -\ TWI -&184 constant TWBR \ TWI Bit Rate register -&188 constant TWCR \ TWI Control Register - $80 constant TWCR_TWINT \ TWI Interrupt Flag - $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit - $20 constant TWCR_TWSTA \ TWI Start Condition Bit - $10 constant TWCR_TWSTO \ TWI Stop Condition Bit - $08 constant TWCR_TWWC \ TWI Write Collition Flag - $04 constant TWCR_TWEN \ TWI Enable Bit - $01 constant TWCR_TWIE \ TWI Interrupt Enable -&185 constant TWSR \ TWI Status Register - $F8 constant TWSR_TWS \ TWI Status - $03 constant TWSR_TWPS \ TWI Prescaler -&187 constant TWDR \ TWI Data register -&186 constant TWAR \ TWI (Slave) Address register - $FE constant TWAR_TWA \ TWI (Slave) Address register Bits - $01 constant TWAR_TWGCE \ TWI General Call Recognition Enable Bit -\ USART0 -&198 constant UDR0 \ USART I/O Data Register -&192 constant UCSR0A \ USART Control and Status Register A - $80 constant UCSR0A_RXC0 \ USART Receive Complete - $40 constant UCSR0A_TXC0 \ USART Transmitt Complete - $20 constant UCSR0A_UDRE0 \ USART Data Register Empty - $10 constant UCSR0A_FE0 \ Framing Error - $08 constant UCSR0A_DOR0 \ Data overRun - $04 constant UCSR0A_UPE0 \ Parity Error - $02 constant UCSR0A_U2X0 \ Double the USART transmission speed - $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode -&193 constant UCSR0B \ USART Control and Status Register B - $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable - $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable - $20 constant UCSR0B_UDRIE0 \ USART Data register Empty Interrupt Enable - $10 constant UCSR0B_RXEN0 \ Receiver Enable - $08 constant UCSR0B_TXEN0 \ Transmitter Enable - $04 constant UCSR0B_UCSZ02 \ Character Size - $02 constant UCSR0B_RXB80 \ Receive Data Bit 8 - $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8 -&194 constant UCSR0C \ USART Control and Status Register C - $40 constant UCSR0C_UMSEL0 \ USART Mode Select - $30 constant UCSR0C_UPM0 \ Parity Mode Bits - $08 constant UCSR0C_USBS0 \ Stop Bit Select - $06 constant UCSR0C_UCSZ0 \ Character Size - $01 constant UCSR0C_UCPOL0 \ Clock Polarity -&196 constant UBRR0 \ USART Baud Rate Register t Bytes -\ USART1 -&206 constant UDR1 \ USART I/O Data Register -&200 constant UCSR1A \ USART Control and Status Register A - $80 constant UCSR1A_RXC1 \ USART Receive Complete - $40 constant UCSR1A_TXC1 \ USART Transmitt Complete - $20 constant UCSR1A_UDRE1 \ USART Data Register Empty - $10 constant UCSR1A_FE1 \ Framing Error - $08 constant UCSR1A_DOR1 \ Data overRun - $04 constant UCSR1A_UPE1 \ Parity Error - $02 constant UCSR1A_U2X1 \ Double the USART transmission speed - $01 constant UCSR1A_MPCM1 \ Multi-processor Communication Mode -&201 constant UCSR1B \ USART Control and Status Register B - $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable - $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable - $20 constant UCSR1B_UDRIE1 \ USART Data register Empty Interrupt Enable - $10 constant UCSR1B_RXEN1 \ Receiver Enable - $08 constant UCSR1B_TXEN1 \ Transmitter Enable - $04 constant UCSR1B_UCSZ12 \ Character Size - $02 constant UCSR1B_RXB81 \ Receive Data Bit 8 - $01 constant UCSR1B_TXB81 \ Transmit Data Bit 8 -&202 constant UCSR1C \ USART Control and Status Register C - $40 constant UCSR1C_UMSEL1 \ USART Mode Select - $30 constant UCSR1C_UPM1 \ Parity Mode Bits - $08 constant UCSR1C_USBS1 \ Stop Bit Select - $06 constant UCSR1C_UCSZ1 \ Character Size - $01 constant UCSR1C_UCPOL1 \ Clock Polarity -&204 constant UBRR1 \ USART Baud Rate Register t Bytes -\ CPU -&95 constant SREG \ Status Register - $80 constant SREG_I \ Global Interrupt Enable - $40 constant SREG_T \ Bit Copy Storage - $20 constant SREG_H \ Half Carry Flag - $10 constant SREG_S \ Sign Bit - $08 constant SREG_V \ Two's Complement Overflow Flag - $04 constant SREG_N \ Negative Flag - $02 constant SREG_Z \ Zero Flag - $01 constant SREG_C \ Carry Flag -&93 constant SP \ Stack Pointer -&116 constant XMCRA \ External Memory Control Register A - $80 constant XMCRA_SRE \ External SRAM Enable - $70 constant XMCRA_SRL \ Wait state page limit - $0C constant XMCRA_SRW1 \ Wait state select bit upper page - $03 constant XMCRA_SRW0 \ Wait state select bit lower page -&117 constant XMCRB \ External Memory Control Register B - $80 constant XMCRB_XMBK \ External Memory Bus Keeper Enable - $07 constant XMCRB_XMM \ External Memory High Mask -&102 constant OSCCAL \ Oscillator Calibration Value -&97 constant CLKPR \ Clock Prescale Register - $80 constant CLKPR_CLKPCE \ - $0F constant CLKPR_CLKPS \ -&83 constant SMCR \ Sleep Mode Control Register - $0E constant SMCR_SM \ Sleep Mode Select bits - $01 constant SMCR_SE \ Sleep Enable -&91 constant RAMPZ \ RAM Page Z Select Register - Not used. - $01 constant RAMPZ_RAMPZ0 \ RAM Page Z Select Register Bit 0 -&75 constant GPIOR2 \ General Purpose IO Register 2 - $FF constant GPIOR2_GPIOR \ General Purpose IO Register 2 bis -&74 constant GPIOR1 \ General Purpose IO Register 1 - $FF constant GPIOR1_GPIOR \ General Purpose IO Register 1 bis -&62 constant GPIOR0 \ General Purpose IO Register 0 - $80 constant GPIOR0_GPIOR07 \ General Purpose IO Register 0 bit 7 - $40 constant GPIOR0_GPIOR06 \ General Purpose IO Register 0 bit 6 - $20 constant GPIOR0_GPIOR05 \ General Purpose IO Register 0 bit 5 - $10 constant GPIOR0_GPIOR04 \ General Purpose IO Register 0 bit 4 - $08 constant GPIOR0_GPIOR03 \ General Purpose IO Register 0 bit 3 - $04 constant GPIOR0_GPIOR02 \ General Purpose IO Register 0 bit 2 - $02 constant GPIOR0_GPIOR01 \ General Purpose IO Register 0 bit 1 - $01 constant GPIOR0_GPIOR00 \ General Purpose IO Register 0 bit 0 -\ BOOT_LOAD -&87 constant SPMCSR \ Store Program Memory Control Register - $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable - $40 constant SPMCSR_RWWSB \ Read While Write Section Busy - $10 constant SPMCSR_RWWSRE \ Read While Write section read enable - $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set - $04 constant SPMCSR_PGWRT \ Page Write - $02 constant SPMCSR_PGERS \ Page Erase - $01 constant SPMCSR_SPMEN \ Store Program Memory Enable -\ EXTERNAL_INTERRUPT -&105 constant EICRA \ External Interrupt Control Register A - $C0 constant EICRA_ISC3 \ External Interrupt Sense Control Bit - $30 constant EICRA_ISC2 \ External Interrupt Sense Control Bit - $0C constant EICRA_ISC1 \ External Interrupt Sense Control Bit - $03 constant EICRA_ISC0 \ External Interrupt Sense Control Bit -&106 constant EICRB \ External Interrupt Control Register B - $C0 constant EICRB_ISC7 \ External Interrupt 7-4 Sense Control Bit - $30 constant EICRB_ISC6 \ External Interrupt 7-4 Sense Control Bit - $0C constant EICRB_ISC5 \ External Interrupt 7-4 Sense Control Bit - $03 constant EICRB_ISC4 \ External Interrupt 7-4 Sense Control Bit -&61 constant EIMSK \ External Interrupt Mask Register - $FF constant EIMSK_INT \ External Interrupt Request 7 Enable -&60 constant EIFR \ External Interrupt Flag Register - $FF constant EIFR_INTF \ External Interrupt Flags -\ EEPROM -&65 constant EEAR \ EEPROM Read/Write Access Bytes -&64 constant EEDR \ EEPROM Data Register -&63 constant EECR \ EEPROM Control Register - $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable - $04 constant EECR_EEMWE \ EEPROM Master Write Enable - $02 constant EECR_EEWE \ EEPROM Write Enable - $01 constant EECR_EERE \ EEPROM Read Enable -\ TIMER_COUNTER_0 -&68 constant TCCR0A \ Timer/Counter0 Control Register - $80 constant TCCR0A_FOC0A \ Force Output Compare - $40 constant TCCR0A_WGM00 \ Waveform Generation Mode 0 - $30 constant TCCR0A_COM0A \ Compare Match Output Modes - $08 constant TCCR0A_WGM01 \ Waveform Generation Mode 1 - $07 constant TCCR0A_CS0 \ Clock Selects -&70 constant TCNT0 \ Timer/Counter0 -&71 constant OCR0A \ Timer/Counter0 Output Compare Register -&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register - $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match Interrupt Enable - $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable -&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register - $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0 - $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag -&67 constant GTCCR \ General Timer/Control Register - $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode - $01 constant GTCCR_PSR310 \ Prescaler Reset Timer/Counter1 and Timer/Counter0 -\ TIMER_COUNTER_2 -&176 constant TCCR2 \ Timer/Counter2 Control Register - $80 constant TCCR2_FOC2A \ Force Output Compare - $40 constant TCCR2_WGM20 \ Waveform Genration Mode - $30 constant TCCR2_COM2A \ Compare Output Mode bits - $08 constant TCCR2_WGM21 \ Waveform Generation Mode - $07 constant TCCR2_CS2 \ Clock Select bits -&178 constant TCNT2 \ Timer/Counter2 -&179 constant OCR2A \ Timer/Counter2 Output Compare Register -&112 constant TIMSK2 \ Timer/Counter Interrupt Mask register - $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match Interrupt Enable - $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable -&55 constant TIFR2 \ Timer/Counter Interrupt Flag Register - $02 constant TIFR2_OCF2A \ Output Compare Flag 2 - $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag -&182 constant ASSR \ Asynchronous Status Register - $10 constant ASSR_EXCLK \ Enable External Clock Interrupt - $08 constant ASSR_AS2 \ AS2: Asynchronous Timer/Counter2 - $04 constant ASSR_TCN2UB \ TCN2UB: Timer/Counter2 Update Busy - $02 constant ASSR_OCR2UB \ Output Compare Register2 Update Busy - $01 constant ASSR_TCR2UB \ TCR2UB: Timer/Counter Control Register2 Update Busy -\ TIMER_COUNTER_1 -&128 constant TCCR1A \ Timer/Counter1 Control Register A - $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits - $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits - $0C constant TCCR1A_COM1C \ Compare Output Mode 1C, bits - $03 constant TCCR1A_WGM1 \ Waveform Generation Mode -&129 constant TCCR1B \ Timer/Counter1 Control Register B - $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler - $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select - $18 constant TCCR1B_WGM1 \ Waveform Generation Mode - $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1 -&130 constant TCCR1C \ Timer/Counter 1 Control Register C - $80 constant TCCR1C_FOC1A \ Force Output Compare 1A - $40 constant TCCR1C_FOC1B \ Force Output Compare 1B - $20 constant TCCR1C_FOC1C \ Force Output Compare 1C -&132 constant TCNT1 \ Timer/Counter1 Bytes -&136 constant OCR1A \ Timer/Counter1 Output Compare Register Bytes -&138 constant OCR1B \ Timer/Counter1 Output Compare Register Bytes -&140 constant OCR1C \ Timer/Counter1 Output Compare Register Bytes -&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes -&111 constant TIMSK1 \ Timer/Counter Interrupt Mask Register - $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable - $08 constant TIMSK1_OCIE1C \ Timer/Counter1 Output CompareC Match Interrupt Enable - $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output CompareB Match Interrupt Enable - $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output CompareA Match Interrupt Enable - $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable -&54 constant TIFR1 \ Timer/Counter Interrupt Flag register - $20 constant TIFR1_ICF1 \ Input Capture Flag 1 - $08 constant TIFR1_OCF1C \ Output Compare Flag 1C - $04 constant TIFR1_OCF1B \ Output Compare Flag 1B - $02 constant TIFR1_OCF1A \ Output Compare Flag 1A - $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag -\ TIMER_COUNTER_3 -&144 constant TCCR3A \ Timer/Counter3 Control Register A - $C0 constant TCCR3A_COM3A \ Compare Output Mode 3A, bits - $30 constant TCCR3A_COM3B \ Compare Output Mode 3B, bits - $0C constant TCCR3A_COM3C \ Compare Output Mode 3C, bits - $03 constant TCCR3A_WGM3 \ Waveform Generation Mode -&145 constant TCCR3B \ Timer/Counter3 Control Register B - $80 constant TCCR3B_ICNC3 \ Input Capture 3 Noise Canceler - $40 constant TCCR3B_ICES3 \ Input Capture 3 Edge Select - $18 constant TCCR3B_WGM3 \ Waveform Generation Mode - $07 constant TCCR3B_CS3 \ Prescaler source of Timer/Counter 3 -&146 constant TCCR3C \ Timer/Counter 3 Control Register C - $80 constant TCCR3C_FOC3A \ Force Output Compare 3A - $40 constant TCCR3C_FOC3B \ Force Output Compare 3B - $20 constant TCCR3C_FOC3C \ Force Output Compare 3C -&148 constant TCNT3 \ Timer/Counter3 Bytes -&152 constant OCR3A \ Timer/Counter3 Output Compare Register Bytes -&154 constant OCR3B \ Timer/Counter3 Output Compare Register Bytes -&156 constant OCR3C \ Timer/Counter3 Output Compare Register Bytes -&150 constant ICR3 \ Timer/Counter3 Input Capture Register Bytes -&113 constant TIMSK3 \ Timer/Counter Interrupt Mask Register - $20 constant TIMSK3_ICIE3 \ Timer/Counter3 Input Capture Interrupt Enable - $08 constant TIMSK3_OCIE3C \ Timer/Counter3 Output CompareC Match Interrupt Enable - $04 constant TIMSK3_OCIE3B \ Timer/Counter3 Output CompareB Match Interrupt Enable - $02 constant TIMSK3_OCIE3A \ Timer/Counter3 Output CompareA Match Interrupt Enable - $01 constant TIMSK3_TOIE3 \ Timer/Counter3 Overflow Interrupt Enable -&56 constant TIFR3 \ Timer/Counter Interrupt Flag register - $20 constant TIFR3_ICF3 \ Input Capture Flag 3 - $08 constant TIFR3_OCF3C \ Output Compare Flag 3C - $04 constant TIFR3_OCF3B \ Output Compare Flag 3B - $02 constant TIFR3_OCF3A \ Output Compare Flag 3A - $01 constant TIFR3_TOV3 \ Timer/Counter3 Overflow Flag -\ WATCHDOG -&96 constant WDTCR \ Watchdog Timer Control Register - $10 constant WDTCR_WDCE \ Watchdog Change Enable - $08 constant WDTCR_WDE \ Watch Dog Enable - $07 constant WDTCR_WDP \ Watch Dog Timer Prescaler bits -\ AD_CONVERTER -&124 constant ADMUX \ The ADC multiplexer Selection Register - $C0 constant ADMUX_REFS \ Reference Selection Bits - $20 constant ADMUX_ADLAR \ Left Adjust Result - $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits -&122 constant ADCSRA \ The ADC Control and Status register - $80 constant ADCSRA_ADEN \ ADC Enable - $40 constant ADCSRA_ADSC \ ADC Start Conversion - $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable - $10 constant ADCSRA_ADIF \ ADC Interrupt Flag - $08 constant ADCSRA_ADIE \ ADC Interrupt Enable - $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits -&120 constant ADC \ ADC Data Register Bytes -&123 constant ADCSRB \ ADC Control and Status Register B - $80 constant ADCSRB_ADHSM \ ADC High Speed Mode - $07 constant ADCSRB_ADTS \ ADC Auto Trigger Sources -&126 constant DIDR0 \ Digital Input Disable Register 1 - $80 constant DIDR0_ADC7D \ ADC7 Digital input Disable - $40 constant DIDR0_ADC6D \ ADC6 Digital input Disable - $20 constant DIDR0_ADC5D \ ADC5 Digital input Disable - $10 constant DIDR0_ADC4D \ ADC4 Digital input Disable - $08 constant DIDR0_ADC3D \ ADC3 Digital input Disable - $04 constant DIDR0_ADC2D \ ADC2 Digital input Disable - $02 constant DIDR0_ADC1D \ ADC1 Digital input Disable - $01 constant DIDR0_ADC0D \ ADC0 Digital input Disable -\ ANALOG_COMPARATOR -&80 constant ACSR \ Analog Comparator Control And Status Register - $80 constant ACSR_ACD \ Analog Comparator Disable - $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select - $20 constant ACSR_ACO \ Analog Compare Output - $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag - $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable - $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable - $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits -&127 constant DIDR1 \ - $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable - $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable -\ CAN -&216 constant CANGCON \ CAN General Control Register - $80 constant CANGCON_ABRQ \ Abort Request - $40 constant CANGCON_OVRQ \ Overload Frame Request - $20 constant CANGCON_TTC \ Time Trigger Communication - $10 constant CANGCON_SYNTTC \ Synchronization of TTC - $08 constant CANGCON_LISTEN \ Listening Mode - $04 constant CANGCON_TEST \ Test Mode - $02 constant CANGCON_ENASTB \ Enable / Standby - $01 constant CANGCON_SWRES \ Software Reset Request -&217 constant CANGSTA \ CAN General Status Register - $40 constant CANGSTA_OVRG \ Overload Frame Flag - $10 constant CANGSTA_TXBSY \ Transmitter Busy - $08 constant CANGSTA_RXBSY \ Receiver Busy - $04 constant CANGSTA_ENFG \ Enable Flag - $02 constant CANGSTA_BOFF \ Bus Off Mode - $01 constant CANGSTA_ERRP \ Error Passive Mode -&218 constant CANGIT \ CAN General Interrupt Register - $80 constant CANGIT_CANIT \ General Interrupt Flag - $40 constant CANGIT_BOFFIT \ Bus Off Interrupt Flag - $20 constant CANGIT_OVRTIM \ Overrun CAN Timer - $10 constant CANGIT_BXOK \ Burst Receive Interrupt - $08 constant CANGIT_SERG \ Stuff Error General - $04 constant CANGIT_CERG \ CRC Error General - $02 constant CANGIT_FERG \ Form Error General - $01 constant CANGIT_AERG \ Ackknowledgement Error General -&219 constant CANGIE \ CAN General Interrupt Enable Register - $80 constant CANGIE_ENIT \ Enable all Interrupts - $40 constant CANGIE_ENBOFF \ Enable Bus Off INterrupt - $20 constant CANGIE_ENRX \ Enable Receive Interrupt - $10 constant CANGIE_ENTX \ Enable Transmitt Interrupt - $08 constant CANGIE_ENERR \ Enable MOb Error Interrupt - $04 constant CANGIE_ENBX \ Enable Burst Receive Interrupt - $02 constant CANGIE_ENERG \ Enable General Error Interrupt - $01 constant CANGIE_ENOVRT \ Enable CAN Timer Overrun Interrupt -&220 constant CANEN2 \ Enable MOb Register -&221 constant CANEN1 \ Enable MOb Register -&222 constant CANIE2 \ Enable Interrupt MOb Register -&223 constant CANIE1 \ Enable Interrupt MOb Register -&224 constant CANSIT2 \ CAN Status Interrupt MOb Register -&225 constant CANSIT1 \ CAN Status Interrupt MOb Register -&226 constant CANBT1 \ Bit Timing Register 1 - $7E constant CANBT1_BRP \ Baud Rate Prescaler bits -&227 constant CANBT2 \ Bit Timing Register 2 - $60 constant CANBT2_SJW \ Re-Sync Jump Width - $0E constant CANBT2_PRS \ Propagation Time Segment -&228 constant CANBT3 \ Bit Timing Register 3 - $70 constant CANBT3_PHS2 \ Phase Segments - $0E constant CANBT3_PHS1 \ Phase Segment 1 - $01 constant CANBT3_SMP \ Sample Type -&229 constant CANTCON \ Timer Control Register -&230 constant CANTIML \ Timer Register Low -&231 constant CANTIMH \ Timer Register High -&232 constant CANTTCL \ TTC Timer Register Low -&233 constant CANTTCH \ TTC Timer Register High -&234 constant CANTEC \ Transmit Error Counter Register -&235 constant CANREC \ Receive Error Counter Register -&236 constant CANHPMOB \ Highest Priority MOb Register -&237 constant CANPAGE \ Page MOb Register - $F0 constant CANPAGE_MOBNB \ MOb Number Bits - $08 constant CANPAGE_AINC \ MOb Data Buffer Auto Increment - $07 constant CANPAGE_INDX \ Data Buffer Index Bits -&238 constant CANSTMOB \ MOb Status Register - $80 constant CANSTMOB_DLCW \ Data Length Code Warning - $40 constant CANSTMOB_TXOK \ Transmit OK - $20 constant CANSTMOB_RXOK \ Receive OK - $10 constant CANSTMOB_BERR \ Bit Error - $08 constant CANSTMOB_SERR \ Stuff Error - $04 constant CANSTMOB_CERR \ CRC Error - $02 constant CANSTMOB_FERR \ Form Error - $01 constant CANSTMOB_AERR \ Ackknowledgement Error -&239 constant CANCDMOB \ MOb Control and DLC Register - $C0 constant CANCDMOB_CONMOB \ MOb Config Bits - $20 constant CANCDMOB_RPLV \ Reply Valid - $10 constant CANCDMOB_IDE \ Identifier Extension - $0F constant CANCDMOB_DLC \ Data Length Code Bits -&240 constant CANIDT4 \ Identifier Tag Register 4 -&241 constant CANIDT3 \ Identifier Tag Register 3 -&242 constant CANIDT2 \ Identifier Tag Register 2 -&243 constant CANIDT1 \ Identifier Tag Register 1 -&244 constant CANIDM4 \ Identifier Mask Register 4 -&245 constant CANIDM3 \ Identifier Mask Register 3 -&246 constant CANIDM2 \ Identifier Mask Register 2 -&247 constant CANIDM1 \ Identifier Mask Register 1 -&248 constant CANSTML \ Time Stamp Register Low -&249 constant CANSTMH \ Time Stamp Register High -&250 constant CANMSG \ Message Data Register - -\ Interrupts -&2 constant INT0Addr \ External Interrupt Request 0 -&4 constant INT1Addr \ External Interrupt Request 1 -&6 constant INT2Addr \ External Interrupt Request 2 -&8 constant INT3Addr \ External Interrupt Request 3 -&10 constant INT4Addr \ External Interrupt Request 4 -&12 constant INT5Addr \ External Interrupt Request 5 -&14 constant INT6Addr \ External Interrupt Request 6 -&16 constant INT7Addr \ External Interrupt Request 7 -&18 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match -&20 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow -&22 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event -&24 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A -&26 constant TIMER1_COMPBAddr \ Timer/Counter Compare Match B -&28 constant TIMER1_COMPCAddr \ Timer/Counter1 Compare Match C -&30 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow -&32 constant TIMER0_COMPAddr \ Timer/Counter0 Compare Match -&34 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow -&36 constant CANITAddr \ CAN Transfer Complete or Error -&38 constant OVRITAddr \ CAN Timer Overrun -&40 constant SPI__STCAddr \ SPI Serial Transfer Complete -&42 constant USART0__RXAddr \ USART0, Rx Complete -&44 constant USART0__UDREAddr \ USART0 Data Register Empty -&46 constant USART0__TXAddr \ USART0, Tx Complete -&48 constant ANALOG_COMPAddr \ Analog Comparator -&50 constant ADCAddr \ ADC Conversion Complete -&52 constant EE_READYAddr \ EEPROM Ready -&54 constant TIMER3_CAPTAddr \ Timer/Counter3 Capture Event -&56 constant TIMER3_COMPAAddr \ Timer/Counter3 Compare Match A -&58 constant TIMER3_COMPBAddr \ Timer/Counter3 Compare Match B -&60 constant TIMER3_COMPCAddr \ Timer/Counter3 Compare Match C -&62 constant TIMER3_OVFAddr \ Timer/Counter3 Overflow -&64 constant USART1__RXAddr \ USART1, Rx Complete -&66 constant USART1__UDREAddr \ USART1, Data Register Empty -&68 constant USART1__TXAddr \ USART1, Tx Complete -&70 constant TWIAddr \ 2-wire Serial Interface -&72 constant SPM_READYAddr \ Store Program Memory Read diff --git a/amforth-6.5/avr8/devices/at90can32/device.asm b/amforth-6.5/avr8/devices/at90can32/device.asm deleted file mode 100644 index 3ca443f..0000000 --- a/amforth-6.5/avr8/devices/at90can32/device.asm +++ /dev/null @@ -1,139 +0,0 @@ -; Partname: AT90CAN32 -; generated automatically, do not edit - -.nolist - .include "can32def.inc" -.list - -.equ ramstart = 256 -.equ CELLSIZE = 2 -.macro readflashcell - lsl zl - rol zh - lpm @0, Z+ - lpm @1, Z+ -.endmacro -.macro writeflashcell - lsl zl - rol zh -.endmacro -.set WANT_PORTA = 0 -.set WANT_PORTB = 0 -.set WANT_PORTC = 0 -.set WANT_PORTD = 0 -.set WANT_PORTE = 0 -.set WANT_PORTF = 0 -.set WANT_PORTG = 0 -.set WANT_JTAG = 0 -.set WANT_SPI = 0 -.set WANT_TWI = 0 -.set WANT_USART0 = 0 -.set WANT_USART1 = 0 -.set WANT_CPU = 0 -.set WANT_BOOT_LOAD = 0 -.set WANT_EXTERNAL_INTERRUPT = 0 -.set WANT_EEPROM = 0 -.set WANT_TIMER_COUNTER_0 = 0 -.set WANT_TIMER_COUNTER_2 = 0 -.set WANT_TIMER_COUNTER_1 = 0 -.set WANT_TIMER_COUNTER_3 = 0 -.set WANT_WATCHDOG = 0 -.set WANT_AD_CONVERTER = 0 -.set WANT_ANALOG_COMPARATOR = 0 -.set WANT_CAN = 0 -.equ intvecsize = 2 ; please verify; flash size: 32768 bytes -.equ pclen = 2 ; please verify -.overlap -.org 2 - rcall isr ; External Interrupt Request 0 -.org 4 - rcall isr ; External Interrupt Request 1 -.org 6 - rcall isr ; External Interrupt Request 2 -.org 8 - rcall isr ; External Interrupt Request 3 -.org 10 - rcall isr ; External Interrupt Request 4 -.org 12 - rcall isr ; External Interrupt Request 5 -.org 14 - rcall isr ; External Interrupt Request 6 -.org 16 - rcall isr ; External Interrupt Request 7 -.org 18 - rcall isr ; Timer/Counter2 Compare Match -.org 20 - rcall isr ; Timer/Counter2 Overflow -.org 22 - rcall isr ; Timer/Counter1 Capture Event -.org 24 - rcall isr ; Timer/Counter1 Compare Match A -.org 26 - rcall isr ; Timer/Counter Compare Match B -.org 28 - rcall isr ; Timer/Counter1 Compare Match C -.org 30 - rcall isr ; Timer/Counter1 Overflow -.org 32 - rcall isr ; Timer/Counter0 Compare Match -.org 34 - rcall isr ; Timer/Counter0 Overflow -.org 36 - rcall isr ; CAN Transfer Complete or Error -.org 38 - rcall isr ; CAN Timer Overrun -.org 40 - rcall isr ; SPI Serial Transfer Complete -.org 42 - rcall isr ; USART0, Rx Complete -.org 44 - rcall isr ; USART0 Data Register Empty -.org 46 - rcall isr ; USART0, Tx Complete -.org 48 - rcall isr ; Analog Comparator -.org 50 - rcall isr ; ADC Conversion Complete -.org 52 - rcall isr ; EEPROM Ready -.org 54 - rcall isr ; Timer/Counter3 Capture Event -.org 56 - rcall isr ; Timer/Counter3 Compare Match A -.org 58 - rcall isr ; Timer/Counter3 Compare Match B -.org 60 - rcall isr ; Timer/Counter3 Compare Match C -.org 62 - rcall isr ; Timer/Counter3 Overflow -.org 64 - rcall isr ; USART1, Rx Complete -.org 66 - rcall isr ; USART1, Data Register Empty -.org 68 - rcall isr ; USART1, Tx Complete -.org 70 - rcall isr ; 2-wire Serial Interface -.org 72 - rcall isr ; Store Program Memory Read -.equ INTVECTORS = 37 -.nooverlap - -; compatability layer (maybe empty) -.equ EEPE = EEWE -.equ EEMPE = EEMWE - -; controller data area, environment query mcu-info -mcu_info: -mcu_ramsize: - .dw 2048 -mcu_eepromsize: - .dw 1024 -mcu_maxdp: - .dw 24576 -mcu_numints: - .dw 37 -mcu_name: - .dw 9 - .db "AT90CAN32",0 -.set codestart=pc diff --git a/amforth-6.5/avr8/devices/at90can32/device.inc b/amforth-6.5/avr8/devices/at90can32/device.inc deleted file mode 100644 index 4b27471..0000000 --- a/amforth-6.5/avr8/devices/at90can32/device.inc +++ /dev/null @@ -1,1707 +0,0 @@ -; Partname: AT90CAN32 -; generated automatically, no not edit - -.if WANT_PORTA == 1 -; ( -- addr ) System Constant -; R( -- ) -; Port A Data Register -VE_PORTA: - .dw $ff05 - .db "PORTA",0 - .dw VE_HEAD - .set VE_HEAD=VE_PORTA -XT_PORTA: - .dw PFA_DOVARIABLE -PFA_PORTA: - .dw 34 -; ( -- addr ) System Constant -; R( -- ) -; Port A Data Direction Register -VE_DDRA: - .dw $ff04 - .db "DDRA" - .dw VE_HEAD - .set VE_HEAD=VE_DDRA -XT_DDRA: - .dw PFA_DOVARIABLE -PFA_DDRA: - .dw 33 -; ( -- addr ) System Constant -; R( -- ) -; Port A Input Pins -VE_PINA: - .dw $ff04 - .db "PINA" - .dw VE_HEAD - .set VE_HEAD=VE_PINA -XT_PINA: - .dw PFA_DOVARIABLE -PFA_PINA: - .dw 32 - -.endif -.if WANT_PORTB == 1 -; ( -- addr ) System Constant -; R( -- ) -; Port B Data Register -VE_PORTB: - .dw $ff05 - .db "PORTB",0 - .dw VE_HEAD - .set VE_HEAD=VE_PORTB -XT_PORTB: - .dw PFA_DOVARIABLE -PFA_PORTB: - .dw 37 -; ( -- addr ) System Constant -; R( -- ) -; Port B Data Direction Register -VE_DDRB: - .dw $ff04 - .db "DDRB" - .dw VE_HEAD - .set VE_HEAD=VE_DDRB -XT_DDRB: - .dw PFA_DOVARIABLE -PFA_DDRB: - .dw 36 -; ( -- addr ) System Constant -; R( -- ) -; Port B Input Pins -VE_PINB: - .dw $ff04 - .db "PINB" - .dw VE_HEAD - .set VE_HEAD=VE_PINB -XT_PINB: - .dw PFA_DOVARIABLE -PFA_PINB: - .dw 35 - -.endif -.if WANT_PORTC == 1 -; ( -- addr ) System Constant -; R( -- ) -; Port C Data Register -VE_PORTC: - .dw $ff05 - .db "PORTC",0 - .dw VE_HEAD - .set VE_HEAD=VE_PORTC -XT_PORTC: - .dw PFA_DOVARIABLE -PFA_PORTC: - .dw 40 -; ( -- addr ) System Constant -; R( -- ) -; Port C Data Direction Register -VE_DDRC: - .dw $ff04 - .db "DDRC" - .dw VE_HEAD - .set VE_HEAD=VE_DDRC -XT_DDRC: - .dw PFA_DOVARIABLE -PFA_DDRC: - .dw 39 -; ( -- addr ) System Constant -; R( -- ) -; Port C Input Pins -VE_PINC: - .dw $ff04 - .db "PINC" - .dw VE_HEAD - .set VE_HEAD=VE_PINC -XT_PINC: - .dw PFA_DOVARIABLE -PFA_PINC: - .dw 38 - -.endif -.if WANT_PORTD == 1 -; ( -- addr ) System Constant -; R( -- ) -; Port D Data Register -VE_PORTD: - .dw $ff05 - .db "PORTD",0 - .dw VE_HEAD - .set VE_HEAD=VE_PORTD -XT_PORTD: - .dw PFA_DOVARIABLE -PFA_PORTD: - .dw 43 -; ( -- addr ) System Constant -; R( -- ) -; Port D Data Direction Register -VE_DDRD: - .dw $ff04 - .db "DDRD" - .dw VE_HEAD - .set VE_HEAD=VE_DDRD -XT_DDRD: - .dw PFA_DOVARIABLE -PFA_DDRD: - .dw 42 -; ( -- addr ) System Constant -; R( -- ) -; Port D Input Pins -VE_PIND: - .dw $ff04 - .db "PIND" - .dw VE_HEAD - .set VE_HEAD=VE_PIND -XT_PIND: - .dw PFA_DOVARIABLE -PFA_PIND: - .dw 41 - -.endif -.if WANT_PORTE == 1 -; ( -- addr ) System Constant -; R( -- ) -; Data Register, Port E -VE_PORTE: - .dw $ff05 - .db "PORTE",0 - .dw VE_HEAD - .set VE_HEAD=VE_PORTE -XT_PORTE: - .dw PFA_DOVARIABLE -PFA_PORTE: - .dw 46 -; ( -- addr ) System Constant -; R( -- ) -; Data Direction Register, Port E -VE_DDRE: - .dw $ff04 - .db "DDRE" - .dw VE_HEAD - .set VE_HEAD=VE_DDRE -XT_DDRE: - .dw PFA_DOVARIABLE -PFA_DDRE: - .dw 45 -; ( -- addr ) System Constant -; R( -- ) -; Input Pins, Port E -VE_PINE: - .dw $ff04 - .db "PINE" - .dw VE_HEAD - .set VE_HEAD=VE_PINE -XT_PINE: - .dw PFA_DOVARIABLE -PFA_PINE: - .dw 44 - -.endif -.if WANT_PORTF == 1 -; ( -- addr ) System Constant -; R( -- ) -; Data Register, Port F -VE_PORTF: - .dw $ff05 - .db "PORTF",0 - .dw VE_HEAD - .set VE_HEAD=VE_PORTF -XT_PORTF: - .dw PFA_DOVARIABLE -PFA_PORTF: - .dw 49 -; ( -- addr ) System Constant -; R( -- ) -; Data Direction Register, Port F -VE_DDRF: - .dw $ff04 - .db "DDRF" - .dw VE_HEAD - .set VE_HEAD=VE_DDRF -XT_DDRF: - .dw PFA_DOVARIABLE -PFA_DDRF: - .dw 48 -; ( -- addr ) System Constant -; R( -- ) -; Input Pins, Port F -VE_PINF: - .dw $ff04 - .db "PINF" - .dw VE_HEAD - .set VE_HEAD=VE_PINF -XT_PINF: - .dw PFA_DOVARIABLE -PFA_PINF: - .dw 47 - -.endif -.if WANT_PORTG == 1 -; ( -- addr ) System Constant -; R( -- ) -; Data Register, Port G -VE_PORTG: - .dw $ff05 - .db "PORTG",0 - .dw VE_HEAD - .set VE_HEAD=VE_PORTG -XT_PORTG: - .dw PFA_DOVARIABLE -PFA_PORTG: - .dw 52 -; ( -- addr ) System Constant -; R( -- ) -; Data Direction Register, Port G -VE_DDRG: - .dw $ff04 - .db "DDRG" - .dw VE_HEAD - .set VE_HEAD=VE_DDRG -XT_DDRG: - .dw PFA_DOVARIABLE -PFA_DDRG: - .dw 51 -; ( -- addr ) System Constant -; R( -- ) -; Input Pins, Port G -VE_PING: - .dw $ff04 - .db "PING" - .dw VE_HEAD - .set VE_HEAD=VE_PING -XT_PING: - .dw PFA_DOVARIABLE -PFA_PING: - .dw 50 - -.endif -.if WANT_JTAG == 1 -; ( -- addr ) System Constant -; R( -- ) -; On-Chip Debug Related Register in I/O Memory -VE_OCDR: - .dw $ff04 - .db "OCDR" - .dw VE_HEAD - .set VE_HEAD=VE_OCDR -XT_OCDR: - .dw PFA_DOVARIABLE -PFA_OCDR: - .dw 81 -; ( -- addr ) System Constant -; R( -- ) -; MCU Control Register -VE_MCUCR: - .dw $ff05 - .db "MCUCR",0 - .dw VE_HEAD - .set VE_HEAD=VE_MCUCR -XT_MCUCR: - .dw PFA_DOVARIABLE -PFA_MCUCR: - .dw 85 -; ( -- addr ) System Constant -; R( -- ) -; MCU Status Register -VE_MCUSR: - .dw $ff05 - .db "MCUSR",0 - .dw VE_HEAD - .set VE_HEAD=VE_MCUSR -XT_MCUSR: - .dw PFA_DOVARIABLE -PFA_MCUSR: - .dw 84 - -.endif -.if WANT_SPI == 1 -; ( -- addr ) System Constant -; R( -- ) -; SPI Control Register -VE_SPCR: - .dw $ff04 - .db "SPCR" - .dw VE_HEAD - .set VE_HEAD=VE_SPCR -XT_SPCR: - .dw PFA_DOVARIABLE -PFA_SPCR: - .dw 76 -; ( -- addr ) System Constant -; R( -- ) -; SPI Status Register -VE_SPSR: - .dw $ff04 - .db "SPSR" - .dw VE_HEAD - .set VE_HEAD=VE_SPSR -XT_SPSR: - .dw PFA_DOVARIABLE -PFA_SPSR: - .dw 77 -; ( -- addr ) System Constant -; R( -- ) -; SPI Data Register -VE_SPDR: - .dw $ff04 - .db "SPDR" - .dw VE_HEAD - .set VE_HEAD=VE_SPDR -XT_SPDR: - .dw PFA_DOVARIABLE -PFA_SPDR: - .dw 78 - -.endif -.if WANT_TWI == 1 -; ( -- addr ) System Constant -; R( -- ) -; TWI Bit Rate register -VE_TWBR: - .dw $ff04 - .db "TWBR" - .dw VE_HEAD - .set VE_HEAD=VE_TWBR -XT_TWBR: - .dw PFA_DOVARIABLE -PFA_TWBR: - .dw 184 -; ( -- addr ) System Constant -; R( -- ) -; TWI Control Register -VE_TWCR: - .dw $ff04 - .db "TWCR" - .dw VE_HEAD - .set VE_HEAD=VE_TWCR -XT_TWCR: - .dw PFA_DOVARIABLE -PFA_TWCR: - .dw 188 -; ( -- addr ) System Constant -; R( -- ) -; TWI Status Register -VE_TWSR: - .dw $ff04 - .db "TWSR" - .dw VE_HEAD - .set VE_HEAD=VE_TWSR -XT_TWSR: - .dw PFA_DOVARIABLE -PFA_TWSR: - .dw 185 -; ( -- addr ) System Constant -; R( -- ) -; TWI Data register -VE_TWDR: - .dw $ff04 - .db "TWDR" - .dw VE_HEAD - .set VE_HEAD=VE_TWDR -XT_TWDR: - .dw PFA_DOVARIABLE -PFA_TWDR: - .dw 187 -; ( -- addr ) System Constant -; R( -- ) -; TWI (Slave) Address register -VE_TWAR: - .dw $ff04 - .db "TWAR" - .dw VE_HEAD - .set VE_HEAD=VE_TWAR -XT_TWAR: - .dw PFA_DOVARIABLE -PFA_TWAR: - .dw 186 - -.endif -.if WANT_USART0 == 1 -; ( -- addr ) System Constant -; R( -- ) -; USART I/O Data Register -VE_UDR0: - .dw $ff04 - .db "UDR0" - .dw VE_HEAD - .set VE_HEAD=VE_UDR0 -XT_UDR0: - .dw PFA_DOVARIABLE -PFA_UDR0: - .dw 198 -; ( -- addr ) System Constant -; R( -- ) -; USART Control and Status Register A -VE_UCSR0A: - .dw $ff06 - .db "UCSR0A" - .dw VE_HEAD - .set VE_HEAD=VE_UCSR0A -XT_UCSR0A: - .dw PFA_DOVARIABLE -PFA_UCSR0A: - .dw 192 -; ( -- addr ) System Constant -; R( -- ) -; USART Control and Status Register B -VE_UCSR0B: - .dw $ff06 - .db "UCSR0B" - .dw VE_HEAD - .set VE_HEAD=VE_UCSR0B -XT_UCSR0B: - .dw PFA_DOVARIABLE -PFA_UCSR0B: - .dw 193 -; ( -- addr ) System Constant -; R( -- ) -; USART Control and Status Register C -VE_UCSR0C: - .dw $ff06 - .db "UCSR0C" - .dw VE_HEAD - .set VE_HEAD=VE_UCSR0C -XT_UCSR0C: - .dw PFA_DOVARIABLE -PFA_UCSR0C: - .dw 194 -; ( -- addr ) System Constant -; R( -- ) -; USART Baud Rate Register t Bytes -VE_UBRR0: - .dw $ff05 - .db "UBRR0",0 - .dw VE_HEAD - .set VE_HEAD=VE_UBRR0 -XT_UBRR0: - .dw PFA_DOVARIABLE -PFA_UBRR0: - .dw 196 - -.endif -.if WANT_USART1 == 1 -; ( -- addr ) System Constant -; R( -- ) -; USART I/O Data Register -VE_UDR1: - .dw $ff04 - .db "UDR1" - .dw VE_HEAD - .set VE_HEAD=VE_UDR1 -XT_UDR1: - .dw PFA_DOVARIABLE -PFA_UDR1: - .dw 206 -; ( -- addr ) System Constant -; R( -- ) -; USART Control and Status Register A -VE_UCSR1A: - .dw $ff06 - .db "UCSR1A" - .dw VE_HEAD - .set VE_HEAD=VE_UCSR1A -XT_UCSR1A: - .dw PFA_DOVARIABLE -PFA_UCSR1A: - .dw 200 -; ( -- addr ) System Constant -; R( -- ) -; USART Control and Status Register B -VE_UCSR1B: - .dw $ff06 - .db "UCSR1B" - .dw VE_HEAD - .set VE_HEAD=VE_UCSR1B -XT_UCSR1B: - .dw PFA_DOVARIABLE -PFA_UCSR1B: - .dw 201 -; ( -- addr ) System Constant -; R( -- ) -; USART Control and Status Register C -VE_UCSR1C: - .dw $ff06 - .db "UCSR1C" - .dw VE_HEAD - .set VE_HEAD=VE_UCSR1C -XT_UCSR1C: - .dw PFA_DOVARIABLE -PFA_UCSR1C: - .dw 202 -; ( -- addr ) System Constant -; R( -- ) -; USART Baud Rate Register t Bytes -VE_UBRR1: - .dw $ff05 - .db "UBRR1",0 - .dw VE_HEAD - .set VE_HEAD=VE_UBRR1 -XT_UBRR1: - .dw PFA_DOVARIABLE -PFA_UBRR1: - .dw 204 - -.endif -.if WANT_CPU == 1 -; ( -- addr ) System Constant -; R( -- ) -; Status Register -VE_SREG: - .dw $ff04 - .db "SREG" - .dw VE_HEAD - .set VE_HEAD=VE_SREG -XT_SREG: - .dw PFA_DOVARIABLE -PFA_SREG: - .dw 95 -; ( -- addr ) System Constant -; R( -- ) -; Stack Pointer -VE_SP: - .dw $ff02 - .db "SP" - .dw VE_HEAD - .set VE_HEAD=VE_SP -XT_SP: - .dw PFA_DOVARIABLE -PFA_SP: - .dw 93 -; ( -- addr ) System Constant -; R( -- ) -; External Memory Control Register A -VE_XMCRA: - .dw $ff05 - .db "XMCRA",0 - .dw VE_HEAD - .set VE_HEAD=VE_XMCRA -XT_XMCRA: - .dw PFA_DOVARIABLE -PFA_XMCRA: - .dw 116 -; ( -- addr ) System Constant -; R( -- ) -; External Memory Control Register B -VE_XMCRB: - .dw $ff05 - .db "XMCRB",0 - .dw VE_HEAD - .set VE_HEAD=VE_XMCRB -XT_XMCRB: - .dw PFA_DOVARIABLE -PFA_XMCRB: - .dw 117 -; ( -- addr ) System Constant -; R( -- ) -; Oscillator Calibration Value -VE_OSCCAL: - .dw $ff06 - .db "OSCCAL" - .dw VE_HEAD - .set VE_HEAD=VE_OSCCAL -XT_OSCCAL: - .dw PFA_DOVARIABLE -PFA_OSCCAL: - .dw 102 -; ( -- addr ) System Constant -; R( -- ) -; Clock Prescale Register -VE_CLKPR: - .dw $ff05 - .db "CLKPR",0 - .dw VE_HEAD - .set VE_HEAD=VE_CLKPR -XT_CLKPR: - .dw PFA_DOVARIABLE -PFA_CLKPR: - .dw 97 -; ( -- addr ) System Constant -; R( -- ) -; Sleep Mode Control Register -VE_SMCR: - .dw $ff04 - .db "SMCR" - .dw VE_HEAD - .set VE_HEAD=VE_SMCR -XT_SMCR: - .dw PFA_DOVARIABLE -PFA_SMCR: - .dw 83 -; ( -- addr ) System Constant -; R( -- ) -; RAM Page Z Select Register - Not used. -VE_RAMPZ: - .dw $ff05 - .db "RAMPZ",0 - .dw VE_HEAD - .set VE_HEAD=VE_RAMPZ -XT_RAMPZ: - .dw PFA_DOVARIABLE -PFA_RAMPZ: - .dw 91 -; ( -- addr ) System Constant -; R( -- ) -; General Purpose IO Register 2 -VE_GPIOR2: - .dw $ff06 - .db "GPIOR2" - .dw VE_HEAD - .set VE_HEAD=VE_GPIOR2 -XT_GPIOR2: - .dw PFA_DOVARIABLE -PFA_GPIOR2: - .dw 75 -; ( -- addr ) System Constant -; R( -- ) -; General Purpose IO Register 1 -VE_GPIOR1: - .dw $ff06 - .db "GPIOR1" - .dw VE_HEAD - .set VE_HEAD=VE_GPIOR1 -XT_GPIOR1: - .dw PFA_DOVARIABLE -PFA_GPIOR1: - .dw 74 -; ( -- addr ) System Constant -; R( -- ) -; General Purpose IO Register 0 -VE_GPIOR0: - .dw $ff06 - .db "GPIOR0" - .dw VE_HEAD - .set VE_HEAD=VE_GPIOR0 -XT_GPIOR0: - .dw PFA_DOVARIABLE -PFA_GPIOR0: - .dw 62 - -.endif -.if WANT_BOOT_LOAD == 1 -; ( -- addr ) System Constant -; R( -- ) -; Store Program Memory Control Register -VE_SPMCSR: - .dw $ff06 - .db "SPMCSR" - .dw VE_HEAD - .set VE_HEAD=VE_SPMCSR -XT_SPMCSR: - .dw PFA_DOVARIABLE -PFA_SPMCSR: - .dw 87 - -.endif -.if WANT_EXTERNAL_INTERRUPT == 1 -; ( -- addr ) System Constant -; R( -- ) -; External Interrupt Control Register A -VE_EICRA: - .dw $ff05 - .db "EICRA",0 - .dw VE_HEAD - .set VE_HEAD=VE_EICRA -XT_EICRA: - .dw PFA_DOVARIABLE -PFA_EICRA: - .dw 105 -; ( -- addr ) System Constant -; R( -- ) -; External Interrupt Control Register B -VE_EICRB: - .dw $ff05 - .db "EICRB",0 - .dw VE_HEAD - .set VE_HEAD=VE_EICRB -XT_EICRB: - .dw PFA_DOVARIABLE -PFA_EICRB: - .dw 106 -; ( -- addr ) System Constant -; R( -- ) -; External Interrupt Mask Register -VE_EIMSK: - .dw $ff05 - .db "EIMSK",0 - .dw VE_HEAD - .set VE_HEAD=VE_EIMSK -XT_EIMSK: - .dw PFA_DOVARIABLE -PFA_EIMSK: - .dw 61 -; ( -- addr ) System Constant -; R( -- ) -; External Interrupt Flag Register -VE_EIFR: - .dw $ff04 - .db "EIFR" - .dw VE_HEAD - .set VE_HEAD=VE_EIFR -XT_EIFR: - .dw PFA_DOVARIABLE -PFA_EIFR: - .dw 60 - -.endif -.if WANT_EEPROM == 1 -; ( -- addr ) System Constant -; R( -- ) -; EEPROM Read/Write Access Bytes -VE_EEAR: - .dw $ff04 - .db "EEAR" - .dw VE_HEAD - .set VE_HEAD=VE_EEAR -XT_EEAR: - .dw PFA_DOVARIABLE -PFA_EEAR: - .dw 65 -; ( -- addr ) System Constant -; R( -- ) -; EEPROM Data Register -VE_EEDR: - .dw $ff04 - .db "EEDR" - .dw VE_HEAD - .set VE_HEAD=VE_EEDR -XT_EEDR: - .dw PFA_DOVARIABLE -PFA_EEDR: - .dw 64 -; ( -- addr ) System Constant -; R( -- ) -; EEPROM Control Register -VE_EECR: - .dw $ff04 - .db "EECR" - .dw VE_HEAD - .set VE_HEAD=VE_EECR -XT_EECR: - .dw PFA_DOVARIABLE -PFA_EECR: - .dw 63 - -.endif -.if WANT_TIMER_COUNTER_0 == 1 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter0 Control Register -VE_TCCR0A: - .dw $ff06 - .db "TCCR0A" - .dw VE_HEAD - .set VE_HEAD=VE_TCCR0A -XT_TCCR0A: - .dw PFA_DOVARIABLE -PFA_TCCR0A: - .dw 68 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter0 -VE_TCNT0: - .dw $ff05 - .db "TCNT0",0 - .dw VE_HEAD - .set VE_HEAD=VE_TCNT0 -XT_TCNT0: - .dw PFA_DOVARIABLE -PFA_TCNT0: - .dw 70 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter0 Output Compare Register -VE_OCR0A: - .dw $ff05 - .db "OCR0A",0 - .dw VE_HEAD - .set VE_HEAD=VE_OCR0A -XT_OCR0A: - .dw PFA_DOVARIABLE -PFA_OCR0A: - .dw 71 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter0 Interrupt Mask Register -VE_TIMSK0: - .dw $ff06 - .db "TIMSK0" - .dw VE_HEAD - .set VE_HEAD=VE_TIMSK0 -XT_TIMSK0: - .dw PFA_DOVARIABLE -PFA_TIMSK0: - .dw 110 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter0 Interrupt Flag register -VE_TIFR0: - .dw $ff05 - .db "TIFR0",0 - .dw VE_HEAD - .set VE_HEAD=VE_TIFR0 -XT_TIFR0: - .dw PFA_DOVARIABLE -PFA_TIFR0: - .dw 53 -; ( -- addr ) System Constant -; R( -- ) -; General Timer/Control Register -VE_GTCCR: - .dw $ff05 - .db "GTCCR",0 - .dw VE_HEAD - .set VE_HEAD=VE_GTCCR -XT_GTCCR: - .dw PFA_DOVARIABLE -PFA_GTCCR: - .dw 67 - -.endif -.if WANT_TIMER_COUNTER_2 == 1 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter2 Control Register -VE_TCCR2: - .dw $ff05 - .db "TCCR2",0 - .dw VE_HEAD - .set VE_HEAD=VE_TCCR2 -XT_TCCR2: - .dw PFA_DOVARIABLE -PFA_TCCR2: - .dw 176 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter2 -VE_TCNT2: - .dw $ff05 - .db "TCNT2",0 - .dw VE_HEAD - .set VE_HEAD=VE_TCNT2 -XT_TCNT2: - .dw PFA_DOVARIABLE -PFA_TCNT2: - .dw 178 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter2 Output Compare Register -VE_OCR2A: - .dw $ff05 - .db "OCR2A",0 - .dw VE_HEAD - .set VE_HEAD=VE_OCR2A -XT_OCR2A: - .dw PFA_DOVARIABLE -PFA_OCR2A: - .dw 179 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter Interrupt Mask register -VE_TIMSK2: - .dw $ff06 - .db "TIMSK2" - .dw VE_HEAD - .set VE_HEAD=VE_TIMSK2 -XT_TIMSK2: - .dw PFA_DOVARIABLE -PFA_TIMSK2: - .dw 112 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter Interrupt Flag Register -VE_TIFR2: - .dw $ff05 - .db "TIFR2",0 - .dw VE_HEAD - .set VE_HEAD=VE_TIFR2 -XT_TIFR2: - .dw PFA_DOVARIABLE -PFA_TIFR2: - .dw 55 -; ( -- addr ) System Constant -; R( -- ) -; Asynchronous Status Register -VE_ASSR: - .dw $ff04 - .db "ASSR" - .dw VE_HEAD - .set VE_HEAD=VE_ASSR -XT_ASSR: - .dw PFA_DOVARIABLE -PFA_ASSR: - .dw 182 - -.endif -.if WANT_TIMER_COUNTER_1 == 1 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter1 Control Register A -VE_TCCR1A: - .dw $ff06 - .db "TCCR1A" - .dw VE_HEAD - .set VE_HEAD=VE_TCCR1A -XT_TCCR1A: - .dw PFA_DOVARIABLE -PFA_TCCR1A: - .dw 128 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter1 Control Register B -VE_TCCR1B: - .dw $ff06 - .db "TCCR1B" - .dw VE_HEAD - .set VE_HEAD=VE_TCCR1B -XT_TCCR1B: - .dw PFA_DOVARIABLE -PFA_TCCR1B: - .dw 129 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter 1 Control Register C -VE_TCCR1C: - .dw $ff06 - .db "TCCR1C" - .dw VE_HEAD - .set VE_HEAD=VE_TCCR1C -XT_TCCR1C: - .dw PFA_DOVARIABLE -PFA_TCCR1C: - .dw 130 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter1 Bytes -VE_TCNT1: - .dw $ff05 - .db "TCNT1",0 - .dw VE_HEAD - .set VE_HEAD=VE_TCNT1 -XT_TCNT1: - .dw PFA_DOVARIABLE -PFA_TCNT1: - .dw 132 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter1 Output Compare Register Bytes -VE_OCR1A: - .dw $ff05 - .db "OCR1A",0 - .dw VE_HEAD - .set VE_HEAD=VE_OCR1A -XT_OCR1A: - .dw PFA_DOVARIABLE -PFA_OCR1A: - .dw 136 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter1 Output Compare Register Bytes -VE_OCR1B: - .dw $ff05 - .db "OCR1B",0 - .dw VE_HEAD - .set VE_HEAD=VE_OCR1B -XT_OCR1B: - .dw PFA_DOVARIABLE -PFA_OCR1B: - .dw 138 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter1 Output Compare Register Bytes -VE_OCR1C: - .dw $ff05 - .db "OCR1C",0 - .dw VE_HEAD - .set VE_HEAD=VE_OCR1C -XT_OCR1C: - .dw PFA_DOVARIABLE -PFA_OCR1C: - .dw 140 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter1 Input Capture Register Bytes -VE_ICR1: - .dw $ff04 - .db "ICR1" - .dw VE_HEAD - .set VE_HEAD=VE_ICR1 -XT_ICR1: - .dw PFA_DOVARIABLE -PFA_ICR1: - .dw 134 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter Interrupt Mask Register -VE_TIMSK1: - .dw $ff06 - .db "TIMSK1" - .dw VE_HEAD - .set VE_HEAD=VE_TIMSK1 -XT_TIMSK1: - .dw PFA_DOVARIABLE -PFA_TIMSK1: - .dw 111 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter Interrupt Flag register -VE_TIFR1: - .dw $ff05 - .db "TIFR1",0 - .dw VE_HEAD - .set VE_HEAD=VE_TIFR1 -XT_TIFR1: - .dw PFA_DOVARIABLE -PFA_TIFR1: - .dw 54 - -.endif -.if WANT_TIMER_COUNTER_3 == 1 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter3 Control Register A -VE_TCCR3A: - .dw $ff06 - .db "TCCR3A" - .dw VE_HEAD - .set VE_HEAD=VE_TCCR3A -XT_TCCR3A: - .dw PFA_DOVARIABLE -PFA_TCCR3A: - .dw 144 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter3 Control Register B -VE_TCCR3B: - .dw $ff06 - .db "TCCR3B" - .dw VE_HEAD - .set VE_HEAD=VE_TCCR3B -XT_TCCR3B: - .dw PFA_DOVARIABLE -PFA_TCCR3B: - .dw 145 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter 3 Control Register C -VE_TCCR3C: - .dw $ff06 - .db "TCCR3C" - .dw VE_HEAD - .set VE_HEAD=VE_TCCR3C -XT_TCCR3C: - .dw PFA_DOVARIABLE -PFA_TCCR3C: - .dw 146 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter3 Bytes -VE_TCNT3: - .dw $ff05 - .db "TCNT3",0 - .dw VE_HEAD - .set VE_HEAD=VE_TCNT3 -XT_TCNT3: - .dw PFA_DOVARIABLE -PFA_TCNT3: - .dw 148 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter3 Output Compare Register Bytes -VE_OCR3A: - .dw $ff05 - .db "OCR3A",0 - .dw VE_HEAD - .set VE_HEAD=VE_OCR3A -XT_OCR3A: - .dw PFA_DOVARIABLE -PFA_OCR3A: - .dw 152 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter3 Output Compare Register Bytes -VE_OCR3B: - .dw $ff05 - .db "OCR3B",0 - .dw VE_HEAD - .set VE_HEAD=VE_OCR3B -XT_OCR3B: - .dw PFA_DOVARIABLE -PFA_OCR3B: - .dw 154 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter3 Output Compare Register Bytes -VE_OCR3C: - .dw $ff05 - .db "OCR3C",0 - .dw VE_HEAD - .set VE_HEAD=VE_OCR3C -XT_OCR3C: - .dw PFA_DOVARIABLE -PFA_OCR3C: - .dw 156 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter3 Input Capture Register Bytes -VE_ICR3: - .dw $ff04 - .db "ICR3" - .dw VE_HEAD - .set VE_HEAD=VE_ICR3 -XT_ICR3: - .dw PFA_DOVARIABLE -PFA_ICR3: - .dw 150 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter Interrupt Mask Register -VE_TIMSK3: - .dw $ff06 - .db "TIMSK3" - .dw VE_HEAD - .set VE_HEAD=VE_TIMSK3 -XT_TIMSK3: - .dw PFA_DOVARIABLE -PFA_TIMSK3: - .dw 113 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter Interrupt Flag register -VE_TIFR3: - .dw $ff05 - .db "TIFR3",0 - .dw VE_HEAD - .set VE_HEAD=VE_TIFR3 -XT_TIFR3: - .dw PFA_DOVARIABLE -PFA_TIFR3: - .dw 56 - -.endif -.if WANT_WATCHDOG == 1 -; ( -- addr ) System Constant -; R( -- ) -; Watchdog Timer Control Register -VE_WDTCR: - .dw $ff05 - .db "WDTCR",0 - .dw VE_HEAD - .set VE_HEAD=VE_WDTCR -XT_WDTCR: - .dw PFA_DOVARIABLE -PFA_WDTCR: - .dw 96 - -.endif -.if WANT_AD_CONVERTER == 1 -; ( -- addr ) System Constant -; R( -- ) -; The ADC multiplexer Selection Register -VE_ADMUX: - .dw $ff05 - .db "ADMUX",0 - .dw VE_HEAD - .set VE_HEAD=VE_ADMUX -XT_ADMUX: - .dw PFA_DOVARIABLE -PFA_ADMUX: - .dw 124 -; ( -- addr ) System Constant -; R( -- ) -; The ADC Control and Status register -VE_ADCSRA: - .dw $ff06 - .db "ADCSRA" - .dw VE_HEAD - .set VE_HEAD=VE_ADCSRA -XT_ADCSRA: - .dw PFA_DOVARIABLE -PFA_ADCSRA: - .dw 122 -; ( -- addr ) System Constant -; R( -- ) -; ADC Data Register Bytes -VE_ADC: - .dw $ff03 - .db "ADC",0 - .dw VE_HEAD - .set VE_HEAD=VE_ADC -XT_ADC: - .dw PFA_DOVARIABLE -PFA_ADC: - .dw 120 -; ( -- addr ) System Constant -; R( -- ) -; ADC Control and Status Register B -VE_ADCSRB: - .dw $ff06 - .db "ADCSRB" - .dw VE_HEAD - .set VE_HEAD=VE_ADCSRB -XT_ADCSRB: - .dw PFA_DOVARIABLE -PFA_ADCSRB: - .dw 123 -; ( -- addr ) System Constant -; R( -- ) -; Digital Input Disable Register 1 -VE_DIDR0: - .dw $ff05 - .db "DIDR0",0 - .dw VE_HEAD - .set VE_HEAD=VE_DIDR0 -XT_DIDR0: - .dw PFA_DOVARIABLE -PFA_DIDR0: - .dw 126 - -.endif -.if WANT_ANALOG_COMPARATOR == 1 -; ( -- addr ) System Constant -; R( -- ) -; Analog Comparator Control And Status Register -VE_ACSR: - .dw $ff04 - .db "ACSR" - .dw VE_HEAD - .set VE_HEAD=VE_ACSR -XT_ACSR: - .dw PFA_DOVARIABLE -PFA_ACSR: - .dw 80 -; ( -- addr ) System Constant -; R( -- ) -; -VE_DIDR1: - .dw $ff05 - .db "DIDR1",0 - .dw VE_HEAD - .set VE_HEAD=VE_DIDR1 -XT_DIDR1: - .dw PFA_DOVARIABLE -PFA_DIDR1: - .dw 127 - -.endif -.if WANT_CAN == 1 -; ( -- addr ) System Constant -; R( -- ) -; CAN General Control Register -VE_CANGCON: - .dw $ff07 - .db "CANGCON",0 - .dw VE_HEAD - .set VE_HEAD=VE_CANGCON -XT_CANGCON: - .dw PFA_DOVARIABLE -PFA_CANGCON: - .dw 216 -; ( -- addr ) System Constant -; R( -- ) -; CAN General Status Register -VE_CANGSTA: - .dw $ff07 - .db "CANGSTA",0 - .dw VE_HEAD - .set VE_HEAD=VE_CANGSTA -XT_CANGSTA: - .dw PFA_DOVARIABLE -PFA_CANGSTA: - .dw 217 -; ( -- addr ) System Constant -; R( -- ) -; CAN General Interrupt Register -VE_CANGIT: - .dw $ff06 - .db "CANGIT" - .dw VE_HEAD - .set VE_HEAD=VE_CANGIT -XT_CANGIT: - .dw PFA_DOVARIABLE -PFA_CANGIT: - .dw 218 -; ( -- addr ) System Constant -; R( -- ) -; CAN General Interrupt Enable Register -VE_CANGIE: - .dw $ff06 - .db "CANGIE" - .dw VE_HEAD - .set VE_HEAD=VE_CANGIE -XT_CANGIE: - .dw PFA_DOVARIABLE -PFA_CANGIE: - .dw 219 -; ( -- addr ) System Constant -; R( -- ) -; Enable MOb Register -VE_CANEN2: - .dw $ff06 - .db "CANEN2" - .dw VE_HEAD - .set VE_HEAD=VE_CANEN2 -XT_CANEN2: - .dw PFA_DOVARIABLE -PFA_CANEN2: - .dw 220 -; ( -- addr ) System Constant -; R( -- ) -; Enable MOb Register -VE_CANEN1: - .dw $ff06 - .db "CANEN1" - .dw VE_HEAD - .set VE_HEAD=VE_CANEN1 -XT_CANEN1: - .dw PFA_DOVARIABLE -PFA_CANEN1: - .dw 221 -; ( -- addr ) System Constant -; R( -- ) -; Enable Interrupt MOb Register -VE_CANIE2: - .dw $ff06 - .db "CANIE2" - .dw VE_HEAD - .set VE_HEAD=VE_CANIE2 -XT_CANIE2: - .dw PFA_DOVARIABLE -PFA_CANIE2: - .dw 222 -; ( -- addr ) System Constant -; R( -- ) -; Enable Interrupt MOb Register -VE_CANIE1: - .dw $ff06 - .db "CANIE1" - .dw VE_HEAD - .set VE_HEAD=VE_CANIE1 -XT_CANIE1: - .dw PFA_DOVARIABLE -PFA_CANIE1: - .dw 223 -; ( -- addr ) System Constant -; R( -- ) -; CAN Status Interrupt MOb Register -VE_CANSIT2: - .dw $ff07 - .db "CANSIT2",0 - .dw VE_HEAD - .set VE_HEAD=VE_CANSIT2 -XT_CANSIT2: - .dw PFA_DOVARIABLE -PFA_CANSIT2: - .dw 224 -; ( -- addr ) System Constant -; R( -- ) -; CAN Status Interrupt MOb Register -VE_CANSIT1: - .dw $ff07 - .db "CANSIT1",0 - .dw VE_HEAD - .set VE_HEAD=VE_CANSIT1 -XT_CANSIT1: - .dw PFA_DOVARIABLE -PFA_CANSIT1: - .dw 225 -; ( -- addr ) System Constant -; R( -- ) -; Bit Timing Register 1 -VE_CANBT1: - .dw $ff06 - .db "CANBT1" - .dw VE_HEAD - .set VE_HEAD=VE_CANBT1 -XT_CANBT1: - .dw PFA_DOVARIABLE -PFA_CANBT1: - .dw 226 -; ( -- addr ) System Constant -; R( -- ) -; Bit Timing Register 2 -VE_CANBT2: - .dw $ff06 - .db "CANBT2" - .dw VE_HEAD - .set VE_HEAD=VE_CANBT2 -XT_CANBT2: - .dw PFA_DOVARIABLE -PFA_CANBT2: - .dw 227 -; ( -- addr ) System Constant -; R( -- ) -; Bit Timing Register 3 -VE_CANBT3: - .dw $ff06 - .db "CANBT3" - .dw VE_HEAD - .set VE_HEAD=VE_CANBT3 -XT_CANBT3: - .dw PFA_DOVARIABLE -PFA_CANBT3: - .dw 228 -; ( -- addr ) System Constant -; R( -- ) -; Timer Control Register -VE_CANTCON: - .dw $ff07 - .db "CANTCON",0 - .dw VE_HEAD - .set VE_HEAD=VE_CANTCON -XT_CANTCON: - .dw PFA_DOVARIABLE -PFA_CANTCON: - .dw 229 -; ( -- addr ) System Constant -; R( -- ) -; Timer Register Low -VE_CANTIML: - .dw $ff07 - .db "CANTIML",0 - .dw VE_HEAD - .set VE_HEAD=VE_CANTIML -XT_CANTIML: - .dw PFA_DOVARIABLE -PFA_CANTIML: - .dw 230 -; ( -- addr ) System Constant -; R( -- ) -; Timer Register High -VE_CANTIMH: - .dw $ff07 - .db "CANTIMH",0 - .dw VE_HEAD - .set VE_HEAD=VE_CANTIMH -XT_CANTIMH: - .dw PFA_DOVARIABLE -PFA_CANTIMH: - .dw 231 -; ( -- addr ) System Constant -; R( -- ) -; TTC Timer Register Low -VE_CANTTCL: - .dw $ff07 - .db "CANTTCL",0 - .dw VE_HEAD - .set VE_HEAD=VE_CANTTCL -XT_CANTTCL: - .dw PFA_DOVARIABLE -PFA_CANTTCL: - .dw 232 -; ( -- addr ) System Constant -; R( -- ) -; TTC Timer Register High -VE_CANTTCH: - .dw $ff07 - .db "CANTTCH",0 - .dw VE_HEAD - .set VE_HEAD=VE_CANTTCH -XT_CANTTCH: - .dw PFA_DOVARIABLE -PFA_CANTTCH: - .dw 233 -; ( -- addr ) System Constant -; R( -- ) -; Transmit Error Counter Register -VE_CANTEC: - .dw $ff06 - .db "CANTEC" - .dw VE_HEAD - .set VE_HEAD=VE_CANTEC -XT_CANTEC: - .dw PFA_DOVARIABLE -PFA_CANTEC: - .dw 234 -; ( -- addr ) System Constant -; R( -- ) -; Receive Error Counter Register -VE_CANREC: - .dw $ff06 - .db "CANREC" - .dw VE_HEAD - .set VE_HEAD=VE_CANREC -XT_CANREC: - .dw PFA_DOVARIABLE -PFA_CANREC: - .dw 235 -; ( -- addr ) System Constant -; R( -- ) -; Highest Priority MOb Register -VE_CANHPMOB: - .dw $ff08 - .db "CANHPMOB" - .dw VE_HEAD - .set VE_HEAD=VE_CANHPMOB -XT_CANHPMOB: - .dw PFA_DOVARIABLE -PFA_CANHPMOB: - .dw 236 -; ( -- addr ) System Constant -; R( -- ) -; Page MOb Register -VE_CANPAGE: - .dw $ff07 - .db "CANPAGE",0 - .dw VE_HEAD - .set VE_HEAD=VE_CANPAGE -XT_CANPAGE: - .dw PFA_DOVARIABLE -PFA_CANPAGE: - .dw 237 -; ( -- addr ) System Constant -; R( -- ) -; MOb Status Register -VE_CANSTMOB: - .dw $ff08 - .db "CANSTMOB" - .dw VE_HEAD - .set VE_HEAD=VE_CANSTMOB -XT_CANSTMOB: - .dw PFA_DOVARIABLE -PFA_CANSTMOB: - .dw 238 -; ( -- addr ) System Constant -; R( -- ) -; MOb Control and DLC Register -VE_CANCDMOB: - .dw $ff08 - .db "CANCDMOB" - .dw VE_HEAD - .set VE_HEAD=VE_CANCDMOB -XT_CANCDMOB: - .dw PFA_DOVARIABLE -PFA_CANCDMOB: - .dw 239 -; ( -- addr ) System Constant -; R( -- ) -; Identifier Tag Register 4 -VE_CANIDT4: - .dw $ff07 - .db "CANIDT4",0 - .dw VE_HEAD - .set VE_HEAD=VE_CANIDT4 -XT_CANIDT4: - .dw PFA_DOVARIABLE -PFA_CANIDT4: - .dw 240 -; ( -- addr ) System Constant -; R( -- ) -; Identifier Tag Register 3 -VE_CANIDT3: - .dw $ff07 - .db "CANIDT3",0 - .dw VE_HEAD - .set VE_HEAD=VE_CANIDT3 -XT_CANIDT3: - .dw PFA_DOVARIABLE -PFA_CANIDT3: - .dw 241 -; ( -- addr ) System Constant -; R( -- ) -; Identifier Tag Register 2 -VE_CANIDT2: - .dw $ff07 - .db "CANIDT2",0 - .dw VE_HEAD - .set VE_HEAD=VE_CANIDT2 -XT_CANIDT2: - .dw PFA_DOVARIABLE -PFA_CANIDT2: - .dw 242 -; ( -- addr ) System Constant -; R( -- ) -; Identifier Tag Register 1 -VE_CANIDT1: - .dw $ff07 - .db "CANIDT1",0 - .dw VE_HEAD - .set VE_HEAD=VE_CANIDT1 -XT_CANIDT1: - .dw PFA_DOVARIABLE -PFA_CANIDT1: - .dw 243 -; ( -- addr ) System Constant -; R( -- ) -; Identifier Mask Register 4 -VE_CANIDM4: - .dw $ff07 - .db "CANIDM4",0 - .dw VE_HEAD - .set VE_HEAD=VE_CANIDM4 -XT_CANIDM4: - .dw PFA_DOVARIABLE -PFA_CANIDM4: - .dw 244 -; ( -- addr ) System Constant -; R( -- ) -; Identifier Mask Register 3 -VE_CANIDM3: - .dw $ff07 - .db "CANIDM3",0 - .dw VE_HEAD - .set VE_HEAD=VE_CANIDM3 -XT_CANIDM3: - .dw PFA_DOVARIABLE -PFA_CANIDM3: - .dw 245 -; ( -- addr ) System Constant -; R( -- ) -; Identifier Mask Register 2 -VE_CANIDM2: - .dw $ff07 - .db "CANIDM2",0 - .dw VE_HEAD - .set VE_HEAD=VE_CANIDM2 -XT_CANIDM2: - .dw PFA_DOVARIABLE -PFA_CANIDM2: - .dw 246 -; ( -- addr ) System Constant -; R( -- ) -; Identifier Mask Register 1 -VE_CANIDM1: - .dw $ff07 - .db "CANIDM1",0 - .dw VE_HEAD - .set VE_HEAD=VE_CANIDM1 -XT_CANIDM1: - .dw PFA_DOVARIABLE -PFA_CANIDM1: - .dw 247 -; ( -- addr ) System Constant -; R( -- ) -; Time Stamp Register Low -VE_CANSTML: - .dw $ff07 - .db "CANSTML",0 - .dw VE_HEAD - .set VE_HEAD=VE_CANSTML -XT_CANSTML: - .dw PFA_DOVARIABLE -PFA_CANSTML: - .dw 248 -; ( -- addr ) System Constant -; R( -- ) -; Time Stamp Register High -VE_CANSTMH: - .dw $ff07 - .db "CANSTMH",0 - .dw VE_HEAD - .set VE_HEAD=VE_CANSTMH -XT_CANSTMH: - .dw PFA_DOVARIABLE -PFA_CANSTMH: - .dw 249 -; ( -- addr ) System Constant -; R( -- ) -; Message Data Register -VE_CANMSG: - .dw $ff06 - .db "CANMSG" - .dw VE_HEAD - .set VE_HEAD=VE_CANMSG -XT_CANMSG: - .dw PFA_DOVARIABLE -PFA_CANMSG: - .dw 250 - -.endif diff --git a/amforth-6.5/avr8/devices/at90can32/device.py b/amforth-6.5/avr8/devices/at90can32/device.py deleted file mode 100644 index b907435..0000000 --- a/amforth-6.5/avr8/devices/at90can32/device.py +++ /dev/null @@ -1,507 +0,0 @@ -# Generated Automatically - -# Partname AT90CAN32 - -MCUREGS = { -# Interrupt Vectors - 'INT0Addr' : '#2', # External Interrupt Request 0 - 'INT1Addr' : '#4', # External Interrupt Request 1 - 'INT2Addr' : '#6', # External Interrupt Request 2 - 'INT3Addr' : '#8', # External Interrupt Request 3 - 'INT4Addr' : '#10', # External Interrupt Request 4 - 'INT5Addr' : '#12', # External Interrupt Request 5 - 'INT6Addr' : '#14', # External Interrupt Request 6 - 'INT7Addr' : '#16', # External Interrupt Request 7 - 'TIMER2_COMPAddr' : '#18', # Timer/Counter2 Compare Match - 'TIMER2_OVFAddr' : '#20', # Timer/Counter2 Overflow - 'TIMER1_CAPTAddr' : '#22', # Timer/Counter1 Capture Event - 'TIMER1_COMPAAddr' : '#24', # Timer/Counter1 Compare Match A - 'TIMER1_COMPBAddr' : '#26', # Timer/Counter Compare Match B - 'TIMER1_COMPCAddr' : '#28', # Timer/Counter1 Compare Match C - 'TIMER1_OVFAddr' : '#30', # Timer/Counter1 Overflow - 'TIMER0_COMPAddr' : '#32', # Timer/Counter0 Compare Match - 'TIMER0_OVFAddr' : '#34', # Timer/Counter0 Overflow - 'CANITAddr' : '#36', # CAN Transfer Complete or Error - 'OVRITAddr' : '#38', # CAN Timer Overrun - 'SPI_STCAddr' : '#40', # SPI Serial Transfer Complete - 'USART0_RXAddr' : '#42', # USART0, Rx Complete - 'USART0_UDREAddr' : '#44', # USART0 Data Register Empty - 'USART0_TXAddr' : '#46', # USART0, Tx Complete - 'ANALOG_COMPAddr' : '#48', # Analog Comparator - 'ADCAddr' : '#50', # ADC Conversion Complete - 'EE_READYAddr' : '#52', # EEPROM Ready - 'TIMER3_CAPTAddr' : '#54', # Timer/Counter3 Capture Event - 'TIMER3_COMPAAddr' : '#56', # Timer/Counter3 Compare Match A - 'TIMER3_COMPBAddr' : '#58', # Timer/Counter3 Compare Match B - 'TIMER3_COMPCAddr' : '#60', # Timer/Counter3 Compare Match C - 'TIMER3_OVFAddr' : '#62', # Timer/Counter3 Overflow - 'USART1_RXAddr' : '#64', # USART1, Rx Complete - 'USART1_UDREAddr' : '#66', # USART1, Data Register Empty - 'USART1_TXAddr' : '#68', # USART1, Tx Complete - 'TWIAddr' : '#70', # 2-wire Serial Interface - 'SPM_READYAddr' : '#72', # Store Program Memory Read - -# Module PORTA - 'PORTA' : '$22', # Port A Data Register - 'DDRA' : '$21', # Port A Data Direction Register - 'PINA' : '$20', # Port A Input Pins - -# Module PORTB - 'PORTB' : '$25', # Port B Data Register - 'DDRB' : '$24', # Port B Data Direction Register - 'PINB' : '$23', # Port B Input Pins - -# Module PORTC - 'PORTC' : '$28', # Port C Data Register - 'DDRC' : '$27', # Port C Data Direction Register - 'PINC' : '$26', # Port C Input Pins - -# Module PORTD - 'PORTD' : '$2b', # Port D Data Register - 'DDRD' : '$2a', # Port D Data Direction Register - 'PIND' : '$29', # Port D Input Pins - -# Module PORTE - 'PORTE' : '$2e', # Data Register, Port E - 'DDRE' : '$2d', # Data Direction Register, Port - 'PINE' : '$2c', # Input Pins, Port E - -# Module PORTF - 'PORTF' : '$31', # Data Register, Port F - 'DDRF' : '$30', # Data Direction Register, Port - 'PINF' : '$2f', # Input Pins, Port F - -# Module PORTG - 'PORTG' : '$34', # Data Register, Port G - 'DDRG' : '$33', # Data Direction Register, Port - 'PING' : '$32', # Input Pins, Port G - -# Module JTAG - 'OCDR' : '$51', # On-Chip Debug Related Register - 'MCUCR' : '$55', # MCU Control Register - 'MCUCR_JTD': '$80', # JTAG Interface Disable - 'MCUSR' : '$54', # MCU Status Register - 'MCUSR_JTRF': '$10', # JTAG Reset Flag - -# Module SPI - 'SPCR' : '$4c', # SPI Control Register - 'SPCR_SPIE': '$80', # SPI Interrupt Enable - 'SPCR_SPE': '$40', # SPI Enable - 'SPCR_DORD': '$20', # Data Order - 'SPCR_MSTR': '$10', # Master/Slave Select - 'SPCR_CPOL': '$8', # Clock polarity - 'SPCR_CPHA': '$4', # Clock Phase - 'SPCR_SPR': '$3', # SPI Clock Rate Selects - 'SPSR' : '$4d', # SPI Status Register - 'SPSR_SPIF': '$80', # SPI Interrupt Flag - 'SPSR_WCOL': '$40', # Write Collision Flag - 'SPSR_SPI2X': '$1', # Double SPI Speed Bit - 'SPDR' : '$4e', # SPI Data Register - -# Module TWI - 'TWBR' : '$b8', # TWI Bit Rate register - 'TWCR' : '$bc', # TWI Control Register - 'TWCR_TWINT': '$80', # TWI Interrupt Flag - 'TWCR_TWEA': '$40', # TWI Enable Acknowledge Bit - 'TWCR_TWSTA': '$20', # TWI Start Condition Bit - 'TWCR_TWSTO': '$10', # TWI Stop Condition Bit - 'TWCR_TWWC': '$8', # TWI Write Collition Flag - 'TWCR_TWEN': '$4', # TWI Enable Bit - 'TWCR_TWIE': '$1', # TWI Interrupt Enable - 'TWSR' : '$b9', # TWI Status Register - 'TWSR_TWS': '$f8', # TWI Status - 'TWSR_TWPS': '$3', # TWI Prescaler - 'TWDR' : '$bb', # TWI Data register - 'TWAR' : '$ba', # TWI (Slave) Address register - 'TWAR_TWA': '$fe', # TWI (Slave) Address register B - 'TWAR_TWGCE': '$1', # TWI General Call Recognition E - -# Module USART0 - 'UDR0' : '$c6', # USART I/O Data Register - 'UCSR0A' : '$c0', # USART Control and Status Regis - 'UCSR0A_RXC0': '$80', # USART Receive Complete - 'UCSR0A_TXC0': '$40', # USART Transmitt Complete - 'UCSR0A_UDRE0': '$20', # USART Data Register Empty - 'UCSR0A_FE0': '$10', # Framing Error - 'UCSR0A_DOR0': '$8', # Data overRun - 'UCSR0A_UPE0': '$4', # Parity Error - 'UCSR0A_U2X0': '$2', # Double the USART transmission - 'UCSR0A_MPCM0': '$1', # Multi-processor Communication - 'UCSR0B' : '$c1', # USART Control and Status Regis - 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable - 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable - 'UCSR0B_UDRIE0': '$20', # USART Data register Empty Inte - 'UCSR0B_RXEN0': '$10', # Receiver Enable - 'UCSR0B_TXEN0': '$8', # Transmitter Enable - 'UCSR0B_UCSZ02': '$4', # Character Size - 'UCSR0B_RXB80': '$2', # Receive Data Bit 8 - 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8 - 'UCSR0C' : '$c2', # USART Control and Status Regis - 'UCSR0C_UMSEL0': '$40', # USART Mode Select - 'UCSR0C_UPM0': '$30', # Parity Mode Bits - 'UCSR0C_USBS0': '$8', # Stop Bit Select - 'UCSR0C_UCSZ0': '$6', # Character Size - 'UCSR0C_UCPOL0': '$1', # Clock Polarity - 'UBRR0' : '$c4', # USART Baud Rate Register t Byt - -# Module USART1 - 'UDR1' : '$ce', # USART I/O Data Register - 'UCSR1A' : '$c8', # USART Control and Status Regis - 'UCSR1A_RXC1': '$80', # USART Receive Complete - 'UCSR1A_TXC1': '$40', # USART Transmitt Complete - 'UCSR1A_UDRE1': '$20', # USART Data Register Empty - 'UCSR1A_FE1': '$10', # Framing Error - 'UCSR1A_DOR1': '$8', # Data overRun - 'UCSR1A_UPE1': '$4', # Parity Error - 'UCSR1A_U2X1': '$2', # Double the USART transmission - 'UCSR1A_MPCM1': '$1', # Multi-processor Communication - 'UCSR1B' : '$c9', # USART Control and Status Regis - 'UCSR1B_RXCIE1': '$80', # RX Complete Interrupt Enable - 'UCSR1B_TXCIE1': '$40', # TX Complete Interrupt Enable - 'UCSR1B_UDRIE1': '$20', # USART Data register Empty Inte - 'UCSR1B_RXEN1': '$10', # Receiver Enable - 'UCSR1B_TXEN1': '$8', # Transmitter Enable - 'UCSR1B_UCSZ12': '$4', # Character Size - 'UCSR1B_RXB81': '$2', # Receive Data Bit 8 - 'UCSR1B_TXB81': '$1', # Transmit Data Bit 8 - 'UCSR1C' : '$ca', # USART Control and Status Regis - 'UCSR1C_UMSEL1': '$40', # USART Mode Select - 'UCSR1C_UPM1': '$30', # Parity Mode Bits - 'UCSR1C_USBS1': '$8', # Stop Bit Select - 'UCSR1C_UCSZ1': '$6', # Character Size - 'UCSR1C_UCPOL1': '$1', # Clock Polarity - 'UBRR1' : '$cc', # USART Baud Rate Register t Byt - -# Module CPU - 'SREG' : '$5f', # Status Register - 'SREG_I': '$80', # Global Interrupt Enable - 'SREG_T': '$40', # Bit Copy Storage - 'SREG_H': '$20', # Half Carry Flag - 'SREG_S': '$10', # Sign Bit - 'SREG_V': '$8', # Two's Complement Overflow Flag - 'SREG_N': '$4', # Negative Flag - 'SREG_Z': '$2', # Zero Flag - 'SREG_C': '$1', # Carry Flag - 'SP' : '$5d', # Stack Pointer - 'MCUCR' : '$55', # MCU Control Register - 'MCUCR_PUD': '$10', # Pull-up disable - 'MCUCR_IVSEL': '$2', # Interrupt Vector Select - 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable - 'MCUSR' : '$54', # MCU Status Register - 'MCUSR_JTRF': '$10', # JTAG Reset Flag - 'MCUSR_WDRF': '$8', # Watchdog Reset Flag - 'MCUSR_BORF': '$4', # Brown-out Reset Flag - 'MCUSR_EXTRF': '$2', # External Reset Flag - 'MCUSR_PORF': '$1', # Power-on reset flag - 'XMCRA' : '$74', # External Memory Control Regist - 'XMCRA_SRE': '$80', # External SRAM Enable - 'XMCRA_SRL': '$70', # Wait state page limit - 'XMCRA_SRW1': '$c', # Wait state select bit upper pa - 'XMCRA_SRW0': '$3', # Wait state select bit lower pa - 'XMCRB' : '$75', # External Memory Control Regist - 'XMCRB_XMBK': '$80', # External Memory Bus Keeper Ena - 'XMCRB_XMM': '$7', # External Memory High Mask - 'OSCCAL' : '$66', # Oscillator Calibration Value - 'CLKPR' : '$61', # Clock Prescale Register - 'CLKPR_CLKPCE': '$80', # - 'CLKPR_CLKPS': '$f', # - 'SMCR' : '$53', # Sleep Mode Control Register - 'SMCR_SM': '$e', # Sleep Mode Select bits - 'SMCR_SE': '$1', # Sleep Enable - 'RAMPZ' : '$5b', # RAM Page Z Select Register - N - 'RAMPZ_RAMPZ0': '$1', # RAM Page Z Select Register Bit - 'GPIOR2' : '$4b', # General Purpose IO Register 2 - 'GPIOR2_GPIOR': '$ff', # General Purpose IO Register 2 - 'GPIOR1' : '$4a', # General Purpose IO Register 1 - 'GPIOR1_GPIOR': '$ff', # General Purpose IO Register 1 - 'GPIOR0' : '$3e', # General Purpose IO Register 0 - 'GPIOR0_GPIOR07': '$80', # General Purpose IO Register 0 - 'GPIOR0_GPIOR06': '$40', # General Purpose IO Register 0 - 'GPIOR0_GPIOR05': '$20', # General Purpose IO Register 0 - 'GPIOR0_GPIOR04': '$10', # General Purpose IO Register 0 - 'GPIOR0_GPIOR03': '$8', # General Purpose IO Register 0 - 'GPIOR0_GPIOR02': '$4', # General Purpose IO Register 0 - 'GPIOR0_GPIOR01': '$2', # General Purpose IO Register 0 - 'GPIOR0_GPIOR00': '$1', # General Purpose IO Register 0 - -# Module BOOT_LOAD - 'SPMCSR' : '$57', # Store Program Memory Control R - 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable - 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy - 'SPMCSR_RWWSRE': '$10', # Read While Write section read - 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set - 'SPMCSR_PGWRT': '$4', # Page Write - 'SPMCSR_PGERS': '$2', # Page Erase - 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable - -# Module EXTERNAL_INTERRUPT - 'EICRA' : '$69', # External Interrupt Control Reg - 'EICRA_ISC3': '$c0', # External Interrupt Sense Contr - 'EICRA_ISC2': '$30', # External Interrupt Sense Contr - 'EICRA_ISC1': '$c', # External Interrupt Sense Contr - 'EICRA_ISC0': '$3', # External Interrupt Sense Contr - 'EICRB' : '$6a', # External Interrupt Control Reg - 'EICRB_ISC7': '$c0', # External Interrupt 7-4 Sense C - 'EICRB_ISC6': '$30', # External Interrupt 7-4 Sense C - 'EICRB_ISC5': '$c', # External Interrupt 7-4 Sense C - 'EICRB_ISC4': '$3', # External Interrupt 7-4 Sense C - 'EIMSK' : '$3d', # External Interrupt Mask Regist - 'EIMSK_INT': '$ff', # External Interrupt Request 7 E - 'EIFR' : '$3c', # External Interrupt Flag Regist - 'EIFR_INTF': '$ff', # External Interrupt Flags - -# Module EEPROM - 'EEAR' : '$41', # EEPROM Read/Write Access Byte - 'EEDR' : '$40', # EEPROM Data Register - 'EECR' : '$3f', # EEPROM Control Register - 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable - 'EECR_EEMWE': '$4', # EEPROM Master Write Enable - 'EECR_EEWE': '$2', # EEPROM Write Enable - 'EECR_EERE': '$1', # EEPROM Read Enable - -# Module TIMER_COUNTER_0 - 'TCCR0A' : '$44', # Timer/Counter0 Control Registe - 'TCCR0A_FOC0A': '$80', # Force Output Compare - 'TCCR0A_WGM00': '$40', # Waveform Generation Mode 0 - 'TCCR0A_COM0A': '$30', # Compare Match Output Modes - 'TCCR0A_WGM01': '$8', # Waveform Generation Mode 1 - 'TCCR0A_CS0': '$7', # Clock Selects - 'TCNT0' : '$46', # Timer/Counter0 - 'OCR0A' : '$47', # Timer/Counter0 Output Compare - 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask - 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare - 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr - 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag - 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare - 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag - 'GTCCR' : '$43', # General Timer/Control Register - 'GTCCR_TSM': '$80', # Timer/Counter Synchronization - 'GTCCR_PSR310': '$1', # Prescaler Reset Timer/Counter1 - -# Module TIMER_COUNTER_2 - 'TCCR2' : '$b0', # Timer/Counter2 Control Registe - 'TCCR2_FOC2A': '$80', # Force Output Compare - 'TCCR2_WGM20': '$40', # Waveform Genration Mode - 'TCCR2_COM2A': '$30', # Compare Output Mode bits - 'TCCR2_WGM21': '$8', # Waveform Generation Mode - 'TCCR2_CS2': '$7', # Clock Select bits - 'TCNT2' : '$b2', # Timer/Counter2 - 'OCR2A' : '$b3', # Timer/Counter2 Output Compare - 'TIMSK2' : '$70', # Timer/Counter Interrupt Mask r - 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare - 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr - 'TIFR2' : '$37', # Timer/Counter Interrupt Flag R - 'TIFR2_OCF2A': '$2', # Output Compare Flag 2 - 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag - 'GTCCR' : '$43', # General Timer/Counter Control - 'GTCCR_PSR2': '$2', # Prescaler Reset Timer/Counter2 - 'ASSR' : '$b6', # Asynchronous Status Register - 'ASSR_EXCLK': '$10', # Enable External Clock Interrup - 'ASSR_AS2': '$8', # AS2: Asynchronous Timer/Counte - 'ASSR_TCN2UB': '$4', # TCN2UB: Timer/Counter2 Update - 'ASSR_OCR2UB': '$2', # Output Compare Register2 Updat - 'ASSR_TCR2UB': '$1', # TCR2UB: Timer/Counter Control - -# Module TIMER_COUNTER_1 - 'TCCR1A' : '$80', # Timer/Counter1 Control Registe - 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits - 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits - 'TCCR1A_COM1C': '$c', # Compare Output Mode 1C, bits - 'TCCR1A_WGM1': '$3', # Waveform Generation Mode - 'TCCR1B' : '$81', # Timer/Counter1 Control Registe - 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler - 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select - 'TCCR1B_WGM1': '$18', # Waveform Generation Mode - 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun - 'TCCR1C' : '$82', # Timer/Counter 1 Control Regist - 'TCCR1C_FOC1A': '$80', # Force Output Compare 1A - 'TCCR1C_FOC1B': '$40', # Force Output Compare 1B - 'TCCR1C_FOC1C': '$20', # Force Output Compare 1C - 'TCNT1' : '$84', # Timer/Counter1 Bytes - 'OCR1A' : '$88', # Timer/Counter1 Output Compare - 'OCR1B' : '$8a', # Timer/Counter1 Output Compare - 'OCR1C' : '$8c', # Timer/Counter1 Output Compare - 'ICR1' : '$86', # Timer/Counter1 Input Capture R - 'TIMSK1' : '$6f', # Timer/Counter Interrupt Mask R - 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I - 'TIMSK1_OCIE1C': '$8', # Timer/Counter1 Output CompareC - 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output CompareB - 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output CompareA - 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr - 'TIFR1' : '$36', # Timer/Counter Interrupt Flag r - 'TIFR1_ICF1': '$20', # Input Capture Flag 1 - 'TIFR1_OCF1C': '$8', # Output Compare Flag 1C - 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B - 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A - 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag - -# Module TIMER_COUNTER_3 - 'TCCR3A' : '$90', # Timer/Counter3 Control Registe - 'TCCR3A_COM3A': '$c0', # Compare Output Mode 3A, bits - 'TCCR3A_COM3B': '$30', # Compare Output Mode 3B, bits - 'TCCR3A_COM3C': '$c', # Compare Output Mode 3C, bits - 'TCCR3A_WGM3': '$3', # Waveform Generation Mode - 'TCCR3B' : '$91', # Timer/Counter3 Control Registe - 'TCCR3B_ICNC3': '$80', # Input Capture 3 Noise Canceler - 'TCCR3B_ICES3': '$40', # Input Capture 3 Edge Select - 'TCCR3B_WGM3': '$18', # Waveform Generation Mode - 'TCCR3B_CS3': '$7', # Prescaler source of Timer/Coun - 'TCCR3C' : '$92', # Timer/Counter 3 Control Regist - 'TCCR3C_FOC3A': '$80', # Force Output Compare 3A - 'TCCR3C_FOC3B': '$40', # Force Output Compare 3B - 'TCCR3C_FOC3C': '$20', # Force Output Compare 3C - 'TCNT3' : '$94', # Timer/Counter3 Bytes - 'OCR3A' : '$98', # Timer/Counter3 Output Compare - 'OCR3B' : '$9a', # Timer/Counter3 Output Compare - 'OCR3C' : '$9c', # Timer/Counter3 Output Compare - 'ICR3' : '$96', # Timer/Counter3 Input Capture R - 'TIMSK3' : '$71', # Timer/Counter Interrupt Mask R - 'TIMSK3_ICIE3': '$20', # Timer/Counter3 Input Capture I - 'TIMSK3_OCIE3C': '$8', # Timer/Counter3 Output CompareC - 'TIMSK3_OCIE3B': '$4', # Timer/Counter3 Output CompareB - 'TIMSK3_OCIE3A': '$2', # Timer/Counter3 Output CompareA - 'TIMSK3_TOIE3': '$1', # Timer/Counter3 Overflow Interr - 'TIFR3' : '$38', # Timer/Counter Interrupt Flag r - 'TIFR3_ICF3': '$20', # Input Capture Flag 3 - 'TIFR3_OCF3C': '$8', # Output Compare Flag 3C - 'TIFR3_OCF3B': '$4', # Output Compare Flag 3B - 'TIFR3_OCF3A': '$2', # Output Compare Flag 3A - 'TIFR3_TOV3': '$1', # Timer/Counter3 Overflow Flag - -# Module WATCHDOG - 'WDTCR' : '$60', # Watchdog Timer Control Registe - 'WDTCR_WDCE': '$10', # Watchdog Change Enable - 'WDTCR_WDE': '$8', # Watch Dog Enable - 'WDTCR_WDP': '$7', # Watch Dog Timer Prescaler bits - -# Module AD_CONVERTER - 'ADMUX' : '$7c', # The ADC multiplexer Selection - 'ADMUX_REFS': '$c0', # Reference Selection Bits - 'ADMUX_ADLAR': '$20', # Left Adjust Result - 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select - 'ADCSRA' : '$7a', # The ADC Control and Status reg - 'ADCSRA_ADEN': '$80', # ADC Enable - 'ADCSRA_ADSC': '$40', # ADC Start Conversion - 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable - 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag - 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable - 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits - 'ADC' : '$78', # ADC Data Register Bytes - 'ADCSRB' : '$7b', # ADC Control and Status Registe - 'ADCSRB_ADHSM': '$80', # ADC High Speed Mode - 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Sources - 'DIDR0' : '$7e', # Digital Input Disable Register - 'DIDR0_ADC7D': '$80', # ADC7 Digital input Disable - 'DIDR0_ADC6D': '$40', # ADC6 Digital input Disable - 'DIDR0_ADC5D': '$20', # ADC5 Digital input Disable - 'DIDR0_ADC4D': '$10', # ADC4 Digital input Disable - 'DIDR0_ADC3D': '$8', # ADC3 Digital input Disable - 'DIDR0_ADC2D': '$4', # ADC2 Digital input Disable - 'DIDR0_ADC1D': '$2', # ADC1 Digital input Disable - 'DIDR0_ADC0D': '$1', # ADC0 Digital input Disable - -# Module ANALOG_COMPARATOR - 'ADCSRB' : '$7b', # ADC Control and Status Registe - 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer - 'ACSR' : '$50', # Analog Comparator Control And - 'ACSR_ACD': '$80', # Analog Comparator Disable - 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele - 'ACSR_ACO': '$20', # Analog Compare Output - 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl - 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En - 'ACSR_ACIC': '$4', # Analog Comparator Input Captur - 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo - 'DIDR1' : '$7f', # - 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable - 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable - -# Module CAN - 'CANGCON' : '$d8', # CAN General Control Register - 'CANGCON_ABRQ': '$80', # Abort Request - 'CANGCON_OVRQ': '$40', # Overload Frame Request - 'CANGCON_TTC': '$20', # Time Trigger Communication - 'CANGCON_SYNTTC': '$10', # Synchronization of TTC - 'CANGCON_LISTEN': '$8', # Listening Mode - 'CANGCON_TEST': '$4', # Test Mode - 'CANGCON_ENASTB': '$2', # Enable / Standby - 'CANGCON_SWRES': '$1', # Software Reset Request - 'CANGSTA' : '$d9', # CAN General Status Register - 'CANGSTA_OVRG': '$40', # Overload Frame Flag - 'CANGSTA_TXBSY': '$10', # Transmitter Busy - 'CANGSTA_RXBSY': '$8', # Receiver Busy - 'CANGSTA_ENFG': '$4', # Enable Flag - 'CANGSTA_BOFF': '$2', # Bus Off Mode - 'CANGSTA_ERRP': '$1', # Error Passive Mode - 'CANGIT' : '$da', # CAN General Interrupt Register - 'CANGIT_CANIT': '$80', # General Interrupt Flag - 'CANGIT_BOFFIT': '$40', # Bus Off Interrupt Flag - 'CANGIT_OVRTIM': '$20', # Overrun CAN Timer - 'CANGIT_BXOK': '$10', # Burst Receive Interrupt - 'CANGIT_SERG': '$8', # Stuff Error General - 'CANGIT_CERG': '$4', # CRC Error General - 'CANGIT_FERG': '$2', # Form Error General - 'CANGIT_AERG': '$1', # Ackknowledgement Error General - 'CANGIE' : '$db', # CAN General Interrupt Enable R - 'CANGIE_ENIT': '$80', # Enable all Interrupts - 'CANGIE_ENBOFF': '$40', # Enable Bus Off INterrupt - 'CANGIE_ENRX': '$20', # Enable Receive Interrupt - 'CANGIE_ENTX': '$10', # Enable Transmitt Interrupt - 'CANGIE_ENERR': '$8', # Enable MOb Error Interrupt - 'CANGIE_ENBX': '$4', # Enable Burst Receive Interrupt - 'CANGIE_ENERG': '$2', # Enable General Error Interrupt - 'CANGIE_ENOVRT': '$1', # Enable CAN Timer Overrun Inter - 'CANEN2' : '$dc', # Enable MOb Register - 'CANEN1' : '$dd', # Enable MOb Register - 'CANIE2' : '$de', # Enable Interrupt MOb Register - 'CANIE1' : '$df', # Enable Interrupt MOb Register - 'CANSIT2' : '$e0', # CAN Status Interrupt MOb Regis - 'CANSIT1' : '$e1', # CAN Status Interrupt MOb Regis - 'CANBT1' : '$e2', # Bit Timing Register 1 - 'CANBT1_BRP': '$7e', # Baud Rate Prescaler bits - 'CANBT2' : '$e3', # Bit Timing Register 2 - 'CANBT2_SJW': '$60', # Re-Sync Jump Width - 'CANBT2_PRS': '$e', # Propagation Time Segment - 'CANBT3' : '$e4', # Bit Timing Register 3 - 'CANBT3_PHS2': '$70', # Phase Segments - 'CANBT3_PHS1': '$e', # Phase Segment 1 - 'CANBT3_SMP': '$1', # Sample Type - 'CANTCON' : '$e5', # Timer Control Register - 'CANTIML' : '$e6', # Timer Register Low - 'CANTIMH' : '$e7', # Timer Register High - 'CANTTCL' : '$e8', # TTC Timer Register Low - 'CANTTCH' : '$e9', # TTC Timer Register High - 'CANTEC' : '$ea', # Transmit Error Counter Registe - 'CANREC' : '$eb', # Receive Error Counter Register - 'CANHPMOB' : '$ec', # Highest Priority MOb Register - 'CANPAGE' : '$ed', # Page MOb Register - 'CANPAGE_MOBNB': '$f0', # MOb Number Bits - 'CANPAGE_AINC': '$8', # MOb Data Buffer Auto Increment - 'CANPAGE_INDX': '$7', # Data Buffer Index Bits - 'CANSTMOB' : '$ee', # MOb Status Register - 'CANSTMOB_DLCW': '$80', # Data Length Code Warning - 'CANSTMOB_TXOK': '$40', # Transmit OK - 'CANSTMOB_RXOK': '$20', # Receive OK - 'CANSTMOB_BERR': '$10', # Bit Error - 'CANSTMOB_SERR': '$8', # Stuff Error - 'CANSTMOB_CERR': '$4', # CRC Error - 'CANSTMOB_FERR': '$2', # Form Error - 'CANSTMOB_AERR': '$1', # Ackknowledgement Error - 'CANCDMOB' : '$ef', # MOb Control and DLC Register - 'CANCDMOB_CONMOB': '$c0', # MOb Config Bits - 'CANCDMOB_RPLV': '$20', # Reply Valid - 'CANCDMOB_IDE': '$10', # Identifier Extension - 'CANCDMOB_DLC': '$f', # Data Length Code Bits - 'CANIDT4' : '$f0', # Identifier Tag Register 4 - 'CANIDT3' : '$f1', # Identifier Tag Register 3 - 'CANIDT2' : '$f2', # Identifier Tag Register 2 - 'CANIDT1' : '$f3', # Identifier Tag Register 1 - 'CANIDM4' : '$f4', # Identifier Mask Register 4 - 'CANIDM3' : '$f5', # Identifier Mask Register 3 - 'CANIDM2' : '$f6', # Identifier Mask Register 2 - 'CANIDM1' : '$f7', # Identifier Mask Register 1 - 'CANSTML' : '$f8', # Time Stamp Register Low - 'CANSTMH' : '$f9', # Time Stamp Register High - 'CANMSG' : '$fa', # Message Data Register - - '__amforth_dummy':'0' -} diff --git a/amforth-6.5/avr8/devices/at90can32/words/no-jtag.asm b/amforth-6.5/avr8/devices/at90can32/words/no-jtag.asm deleted file mode 100644 index 352a4bb..0000000 --- a/amforth-6.5/avr8/devices/at90can32/words/no-jtag.asm +++ /dev/null @@ -1,14 +0,0 @@ -; ( -- ) -; ( -- ) -; MCU -; disable jtag at runtime -VE_NOJTAG: - .dw $FF05 - .db "-jtag",0 - .dw VE_HEAD - .set VE_HEAD = VE_NOJTAG -XT_NOJTAG: - .dw PFA_NOJTAG -PFA_NOJTAG: - - jmp_ DO_NEXT diff --git a/amforth-6.5/avr8/devices/at90can32/words/no-wdt.asm b/amforth-6.5/avr8/devices/at90can32/words/no-wdt.asm deleted file mode 100644 index 4a12261..0000000 --- a/amforth-6.5/avr8/devices/at90can32/words/no-wdt.asm +++ /dev/null @@ -1,22 +0,0 @@ -; ( -- ) -; MCU -; disable watch dog timer at runtime -VE_NOWDT: - .dw $ff04 - .db "-wdt" - .dw VE_HEAD - .set VE_HEAD = VE_NOWDT -XT_NOWDT: - .dw PFA_NOWDT -PFA_NOWDT: - -; Reset WDT - wdr -; Write logical one to WDTOE and WDE - in_ temp1, WDTCR - ori temp1, (1<