From 67d25d837ac55f28a366c0a3b262e439a6e75fc3 Mon Sep 17 00:00:00 2001 From: Dimitri Sokolyuk Date: Sat, 19 Aug 2017 12:15:28 +0200 Subject: Add AmForth --- amforth-6.5/avr8/devices/at90pwm161/blocks/SPI.frt | 27 ++++++++++++++++++++++ 1 file changed, 27 insertions(+) create mode 100644 amforth-6.5/avr8/devices/at90pwm161/blocks/SPI.frt (limited to 'amforth-6.5/avr8/devices/at90pwm161/blocks/SPI.frt') diff --git a/amforth-6.5/avr8/devices/at90pwm161/blocks/SPI.frt b/amforth-6.5/avr8/devices/at90pwm161/blocks/SPI.frt new file mode 100644 index 0000000..190bab5 --- /dev/null +++ b/amforth-6.5/avr8/devices/at90pwm161/blocks/SPI.frt @@ -0,0 +1,27 @@ +\ Generated automatically for at90pwm161 +\ #require bitnames.frt + +\ SPI +$37 constant SPCR \ SPI Control Register + $80 constant SPCR_SPIE \ SPI Interrupt Enable + 37 $80 bitmask: SPCR.SPIE \ SPI Interrupt Enable + $40 constant SPCR_SPE \ SPI Enable + 37 $40 bitmask: SPCR.SPE \ SPI Enable + $20 constant SPCR_DORD \ Data Order + 37 $20 bitmask: SPCR.DORD \ Data Order + $10 constant SPCR_MSTR \ Master/Slave Select + 37 $10 bitmask: SPCR.MSTR \ Master/Slave Select + $8 constant SPCR_CPOL \ Clock polarity + 37 $8 bitmask: SPCR.CPOL \ Clock polarity + $4 constant SPCR_CPHA \ Clock Phase + 37 $4 bitmask: SPCR.CPHA \ Clock Phase + $3 constant SPCR_SPR \ SPI Clock Rate Selects + 37 $3 bitmask: SPCR.SPR \ SPI Clock Rate Selects +$38 constant SPSR \ SPI Status Register + $80 constant SPSR_SPIF \ SPI Interrupt Flag + 38 $80 bitmask: SPSR.SPIF \ SPI Interrupt Flag + $40 constant SPSR_WCOL \ Write Collision Flag + 38 $40 bitmask: SPSR.WCOL \ Write Collision Flag + $1 constant SPSR_SPI2X \ Double SPI Speed Bit + 38 $1 bitmask: SPSR.SPI2X \ Double SPI Speed Bit +$56 constant SPDR \ SPI Data Register -- cgit v1.2.3