From 67d25d837ac55f28a366c0a3b262e439a6e75fc3 Mon Sep 17 00:00:00 2001 From: Dimitri Sokolyuk Date: Sat, 19 Aug 2017 12:15:28 +0200 Subject: Add AmForth --- amforth-6.5/avr8/devices/atmega128/atmega128.frt | 329 ++++++ amforth-6.5/avr8/devices/atmega128/device.asm | 141 +++ amforth-6.5/avr8/devices/atmega128/device.inc | 1179 ++++++++++++++++++++ amforth-6.5/avr8/devices/atmega128/device.py | 403 +++++++ .../avr8/devices/atmega128/words/no-jtag.asm | 14 + .../avr8/devices/atmega128/words/no-wdt.asm | 22 + amforth-6.5/avr8/devices/atmega128/words/sleep.asm | 24 + 7 files changed, 2112 insertions(+) create mode 100644 amforth-6.5/avr8/devices/atmega128/atmega128.frt create mode 100644 amforth-6.5/avr8/devices/atmega128/device.asm create mode 100644 amforth-6.5/avr8/devices/atmega128/device.inc create mode 100644 amforth-6.5/avr8/devices/atmega128/device.py create mode 100644 amforth-6.5/avr8/devices/atmega128/words/no-jtag.asm create mode 100644 amforth-6.5/avr8/devices/atmega128/words/no-wdt.asm create mode 100644 amforth-6.5/avr8/devices/atmega128/words/sleep.asm (limited to 'amforth-6.5/avr8/devices/atmega128') diff --git a/amforth-6.5/avr8/devices/atmega128/atmega128.frt b/amforth-6.5/avr8/devices/atmega128/atmega128.frt new file mode 100644 index 0000000..7441912 --- /dev/null +++ b/amforth-6.5/avr8/devices/atmega128/atmega128.frt @@ -0,0 +1,329 @@ +\ Partname: ATmega128 +\ generated automatically + +\ ANALOG_COMPARATOR +&64 constant SFIOR \ Special Function IO Register + $08 constant SFIOR_ACME \ Analog Comparator Multiplexer Enable +&40 constant ACSR \ Analog Comparator Control And Status Register + $80 constant ACSR_ACD \ Analog Comparator Disable + $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select + $20 constant ACSR_ACO \ Analog Compare Output + $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag + $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable + $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable + $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits +\ SPI +&47 constant SPDR \ SPI Data Register +&46 constant SPSR \ SPI Status Register + $80 constant SPSR_SPIF \ SPI Interrupt Flag + $40 constant SPSR_WCOL \ Write Collision Flag + $01 constant SPSR_SPI2X \ Double SPI Speed Bit +&45 constant SPCR \ SPI Control Register + $80 constant SPCR_SPIE \ SPI Interrupt Enable + $40 constant SPCR_SPE \ SPI Enable + $20 constant SPCR_DORD \ Data Order + $10 constant SPCR_MSTR \ Master/Slave Select + $08 constant SPCR_CPOL \ Clock polarity + $04 constant SPCR_CPHA \ Clock Phase + $03 constant SPCR_SPR \ SPI Clock Rate Selects +\ TWI +&112 constant TWBR \ TWI Bit Rate register +&116 constant TWCR \ TWI Control Register + $80 constant TWCR_TWINT \ TWI Interrupt Flag + $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit + $20 constant TWCR_TWSTA \ TWI Start Condition Bit + $10 constant TWCR_TWSTO \ TWI Stop Condition Bit + $08 constant TWCR_TWWC \ TWI Write Collition Flag + $04 constant TWCR_TWEN \ TWI Enable Bit + $01 constant TWCR_TWIE \ TWI Interrupt Enable +&113 constant TWSR \ TWI Status Register + $F8 constant TWSR_TWS \ TWI Status + $03 constant TWSR_TWPS \ TWI Prescaler +&115 constant TWDR \ TWI Data register +&114 constant TWAR \ TWI (Slave) Address register + $FE constant TWAR_TWA \ TWI (Slave) Address register Bits + $01 constant TWAR_TWGCE \ TWI General Call Recognition Enable Bit +\ USART0 +&44 constant UDR0 \ USART I/O Data Register +&43 constant UCSR0A \ USART Control and Status Register A + $80 constant UCSR0A_RXC0 \ USART Receive Complete + $40 constant UCSR0A_TXC0 \ USART Transmitt Complete + $20 constant UCSR0A_UDRE0 \ USART Data Register Empty + $10 constant UCSR0A_FE0 \ Framing Error + $08 constant UCSR0A_DOR0 \ Data overRun + $04 constant UCSR0A_UPE0 \ Parity Error + $02 constant UCSR0A_U2X0 \ Double the USART transmission speed + $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode +&42 constant UCSR0B \ USART Control and Status Register B + $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable + $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable + $20 constant UCSR0B_UDRIE0 \ USART Data register Empty Interrupt Enable + $10 constant UCSR0B_RXEN0 \ Receiver Enable + $08 constant UCSR0B_TXEN0 \ Transmitter Enable + $04 constant UCSR0B_UCSZ02 \ Character Size + $02 constant UCSR0B_RXB80 \ Receive Data Bit 8 + $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8 +&149 constant UCSR0C \ USART Control and Status Register C + $40 constant UCSR0C_UMSEL0 \ USART Mode Select + $30 constant UCSR0C_UPM0 \ Parity Mode Bits + $08 constant UCSR0C_USBS0 \ Stop Bit Select + $06 constant UCSR0C_UCSZ0 \ Character Size + $01 constant UCSR0C_UCPOL0 \ Clock Polarity +&144 constant UBRR0H \ USART Baud Rate Register Hight Byte +&41 constant UBRR0L \ USART Baud Rate Register Low Byte +\ USART1 +&156 constant UDR1 \ USART I/O Data Register +&155 constant UCSR1A \ USART Control and Status Register A + $80 constant UCSR1A_RXC1 \ USART Receive Complete + $40 constant UCSR1A_TXC1 \ USART Transmitt Complete + $20 constant UCSR1A_UDRE1 \ USART Data Register Empty + $10 constant UCSR1A_FE1 \ Framing Error + $08 constant UCSR1A_DOR1 \ Data overRun + $04 constant UCSR1A_UPE1 \ Parity Error + $02 constant UCSR1A_U2X1 \ Double the USART transmission speed + $01 constant UCSR1A_MPCM1 \ Multi-processor Communication Mode +&154 constant UCSR1B \ USART Control and Status Register B + $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable + $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable + $20 constant UCSR1B_UDRIE1 \ USART Data register Empty Interrupt Enable + $10 constant UCSR1B_RXEN1 \ Receiver Enable + $08 constant UCSR1B_TXEN1 \ Transmitter Enable + $04 constant UCSR1B_UCSZ12 \ Character Size + $02 constant UCSR1B_RXB81 \ Receive Data Bit 8 + $01 constant UCSR1B_TXB81 \ Transmit Data Bit 8 +&157 constant UCSR1C \ USART Control and Status Register C + $40 constant UCSR1C_UMSEL1 \ USART Mode Select + $30 constant UCSR1C_UPM1 \ Parity Mode Bits + $08 constant UCSR1C_USBS1 \ Stop Bit Select + $06 constant UCSR1C_UCSZ1 \ Character Size + $01 constant UCSR1C_UCPOL1 \ Clock Polarity +&152 constant UBRR1H \ USART Baud Rate Register Hight Byte +&153 constant UBRR1L \ USART Baud Rate Register Low Byte +\ CPU +&95 constant SREG \ Status Register + $80 constant SREG_I \ Global Interrupt Enable + $40 constant SREG_T \ Bit Copy Storage + $20 constant SREG_H \ Half Carry Flag + $10 constant SREG_S \ Sign Bit + $08 constant SREG_V \ Two's Complement Overflow Flag + $04 constant SREG_N \ Negative Flag + $02 constant SREG_Z \ Zero Flag + $01 constant SREG_C \ Carry Flag +&93 constant SP \ Stack Pointer +&85 constant MCUCR \ MCU Control Register + $80 constant MCUCR_SRE \ External SRAM Enable + $40 constant MCUCR_SRW10 \ External SRAM Wait State Select + $20 constant MCUCR_SE \ Sleep Enable + $18 constant MCUCR_SM \ Sleep Mode Select + $04 constant MCUCR_SM2 \ Sleep Mode Select + $02 constant MCUCR_IVSEL \ Interrupt Vector Select + $01 constant MCUCR_IVCE \ Interrupt Vector Change Enable +&84 constant MCUCSR \ MCU Control And Status Register + $80 constant MCUCSR_JTD \ JTAG Interface Disable + $10 constant MCUCSR_JTRF \ JTAG Reset Flag + $08 constant MCUCSR_WDRF \ Watchdog Reset Flag + $04 constant MCUCSR_BORF \ Brown-out Reset Flag + $02 constant MCUCSR_EXTRF \ External Reset Flag + $01 constant MCUCSR_PORF \ Power-on reset flag +&109 constant XMCRA \ External Memory Control Register A + $70 constant XMCRA_SRL \ Wait state page limit + $0C constant XMCRA_SRW0 \ Wait state select bit lower page + $02 constant XMCRA_SRW11 \ Wait state select bit upper page +&108 constant XMCRB \ External Memory Control Register B + $80 constant XMCRB_XMBK \ External Memory Bus Keeper Enable + $07 constant XMCRB_XMM \ External Memory High Mask +&111 constant OSCCAL \ Oscillator Calibration Value +&92 constant XDIV \ XTAL Divide Control Register +&91 constant RAMPZ \ RAM Page Z Select Register + $01 constant RAMPZ_RAMPZ0 \ RAM Page Z Select Register Bit 0 +\ BOOT_LOAD +&104 constant SPMCSR \ Store Program Memory Control Register + $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable + $40 constant SPMCSR_RWWSB \ Read While Write Section Busy + $10 constant SPMCSR_RWWSRE \ Read While Write section read enable + $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set + $04 constant SPMCSR_PGWRT \ Page Write + $02 constant SPMCSR_PGERS \ Page Erase + $01 constant SPMCSR_SPMEN \ Store Program Memory Enable +\ JTAG +&66 constant OCDR \ On-Chip Debug Related Register in I/O Memory + $FF constant OCDR_OCDR \ On-Chip Debug Register Bits +\ MISC +\ EXTERNAL_INTERRUPT +&106 constant EICRA \ External Interrupt Control Register A + $C0 constant EICRA_ISC3 \ External Interrupt Sense Control Bit + $30 constant EICRA_ISC2 \ External Interrupt Sense Control Bit + $0C constant EICRA_ISC1 \ External Interrupt Sense Control Bit + $03 constant EICRA_ISC0 \ External Interrupt Sense Control Bit +&90 constant EICRB \ External Interrupt Control Register B + $C0 constant EICRB_ISC7 \ External Interrupt 7-4 Sense Control Bit + $30 constant EICRB_ISC6 \ External Interrupt 7-4 Sense Control Bit + $0C constant EICRB_ISC5 \ External Interrupt 7-4 Sense Control Bit + $03 constant EICRB_ISC4 \ External Interrupt 7-4 Sense Control Bit +&89 constant EIMSK \ External Interrupt Mask Register + $FF constant EIMSK_INT \ External Interrupt Request 7 Enable +&88 constant EIFR \ External Interrupt Flag Register + $FF constant EIFR_INTF \ External Interrupt Flags +\ EEPROM +&62 constant EEAR \ EEPROM Read/Write Access Bytes +&61 constant EEDR \ EEPROM Data Register +&60 constant EECR \ EEPROM Control Register + $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable + $04 constant EECR_EEMWE \ EEPROM Master Write Enable + $02 constant EECR_EEWE \ EEPROM Write Enable + $01 constant EECR_EERE \ EEPROM Read Enable +\ PORTA +&59 constant PORTA \ Port A Data Register +&58 constant DDRA \ Port A Data Direction Register +&57 constant PINA \ Port A Input Pins +\ PORTB +&56 constant PORTB \ Port B Data Register +&55 constant DDRB \ Port B Data Direction Register +&54 constant PINB \ Port B Input Pins +\ PORTC +&53 constant PORTC \ Port C Data Register +&52 constant DDRC \ Port C Data Direction Register +&51 constant PINC \ Port C Input Pins +\ PORTD +&50 constant PORTD \ Port D Data Register +&49 constant DDRD \ Port D Data Direction Register +&48 constant PIND \ Port D Input Pins +\ PORTE +&35 constant PORTE \ Data Register, Port E +&34 constant DDRE \ Data Direction Register, Port E +&33 constant PINE \ Input Pins, Port E +\ PORTF +&98 constant PORTF \ Data Register, Port F +&97 constant DDRF \ Data Direction Register, Port F +&32 constant PINF \ Input Pins, Port F +\ PORTG +&101 constant PORTG \ Data Register, Port G +&100 constant DDRG \ Data Direction Register, Port G +&99 constant PING \ Input Pins, Port G +\ TIMER_COUNTER_0 +&83 constant TCCR0 \ Timer/Counter Control Register + $80 constant TCCR0_FOC0 \ Force Output Compare + $40 constant TCCR0_WGM00 \ Waveform Generation Mode 0 + $30 constant TCCR0_COM0 \ Compare Match Output Modes + $08 constant TCCR0_WGM01 \ Waveform Generation Mode 1 + $07 constant TCCR0_CS0 \ Clock Selects +&82 constant TCNT0 \ Timer/Counter Register +&81 constant OCR0 \ Output Compare Register +&80 constant ASSR \ Asynchronus Status Register + $08 constant ASSR_AS0 \ Asynchronus Timer/Counter 0 + $04 constant ASSR_TCN0UB \ Timer/Counter0 Update Busy + $02 constant ASSR_OCR0UB \ Output Compare register 0 Busy + $01 constant ASSR_TCR0UB \ Timer/Counter Control Register 0 Update Busy +&87 constant TIMSK \ Timer/Counter Interrupt Mask Register + $02 constant TIMSK_OCIE0 \ Timer/Counter0 Output Compare Match Interrupt register + $01 constant TIMSK_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable +&86 constant TIFR \ Timer/Counter Interrupt Flag register + $02 constant TIFR_OCF0 \ Output Compare Flag 0 + $01 constant TIFR_TOV0 \ Timer/Counter0 Overflow Flag +\ TIMER_COUNTER_1 +&125 constant ETIMSK \ Extended Timer/Counter Interrupt Mask Register + $01 constant ETIMSK_OCIE1C \ Timer/Counter 1, Output Compare Match C Interrupt Enable +&124 constant ETIFR \ Extended Timer/Counter Interrupt Flag register + $01 constant ETIFR_OCF1C \ Timer/Counter 1, Output Compare C Match Flag +&79 constant TCCR1A \ Timer/Counter1 Control Register A + $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits + $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits + $0C constant TCCR1A_COM1C \ Compare Output Mode 1C, bits + $03 constant TCCR1A_WGM1 \ Waveform Generation Mode Bits +&78 constant TCCR1B \ Timer/Counter1 Control Register B + $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler + $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select + $18 constant TCCR1B_WGM1 \ Waveform Generation Mode + $07 constant TCCR1B_CS1 \ Clock Select1 bits +&122 constant TCCR1C \ Timer/Counter1 Control Register C + $80 constant TCCR1C_FOC1A \ Force Output Compare for channel A + $40 constant TCCR1C_FOC1B \ Force Output Compare for channel B + $20 constant TCCR1C_FOC1C \ Force Output Compare for channel C +&76 constant TCNT1 \ Timer/Counter1 Bytes +&74 constant OCR1A \ Timer/Counter1 Output Compare Register Bytes +&72 constant OCR1B \ Timer/Counter1 Output Compare Register Bytes +&120 constant OCR1C \ Timer/Counter1 Output Compare Register Bytes +&70 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes +\ TIMER_COUNTER_2 +&69 constant TCCR2 \ Timer/Counter Control Register + $80 constant TCCR2_FOC2 \ Force Output Compare + $40 constant TCCR2_WGM20 \ Wafeform Generation Mode + $30 constant TCCR2_COM2 \ Compare Match Output Mode + $08 constant TCCR2_WGM21 \ Waveform Generation Mode + $07 constant TCCR2_CS2 \ Clock Select +&68 constant TCNT2 \ Timer/Counter Register +&67 constant OCR2 \ Output Compare Register +\ TIMER_COUNTER_3 +&139 constant TCCR3A \ Timer/Counter3 Control Register A + $C0 constant TCCR3A_COM3A \ Compare Output Mode 3A, bits + $30 constant TCCR3A_COM3B \ Compare Output Mode 3B, bits + $0C constant TCCR3A_COM3C \ Compare Output Mode 3C, bits + $03 constant TCCR3A_WGM3 \ Waveform Generation Mode Bits +&138 constant TCCR3B \ Timer/Counter3 Control Register B + $80 constant TCCR3B_ICNC3 \ Input Capture 3 Noise Canceler + $40 constant TCCR3B_ICES3 \ Input Capture 3 Edge Select + $18 constant TCCR3B_WGM3 \ Waveform Generation Mode + $07 constant TCCR3B_CS3 \ Clock Select3 bits +&140 constant TCCR3C \ Timer/Counter3 Control Register C + $80 constant TCCR3C_FOC3A \ Force Output Compare for channel A + $40 constant TCCR3C_FOC3B \ Force Output Compare for channel B + $20 constant TCCR3C_FOC3C \ Force Output Compare for channel C +&136 constant TCNT3 \ Timer/Counter3 Bytes +&134 constant OCR3A \ Timer/Counter3 Output Compare Register A Bytes +&132 constant OCR3B \ Timer/Counter3 Output Compare Register B Bytes +&130 constant OCR3C \ Timer/Counter3 Output compare Register C Bytes +&128 constant ICR3 \ Timer/Counter3 Input Capture Register Bytes +\ WATCHDOG +&65 constant WDTCR \ Watchdog Timer Control Register + $10 constant WDTCR_WDCE \ Watchdog Change Enable + $08 constant WDTCR_WDE \ Watch Dog Enable + $07 constant WDTCR_WDP \ Watch Dog Timer Prescaler bits +\ AD_CONVERTER +&39 constant ADMUX \ The ADC multiplexer Selection Register + $C0 constant ADMUX_REFS \ Reference Selection Bits + $20 constant ADMUX_ADLAR \ Left Adjust Result + $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits +&38 constant ADCSRA \ The ADC Control and Status register + $80 constant ADCSRA_ADEN \ ADC Enable + $40 constant ADCSRA_ADSC \ ADC Start Conversion + $20 constant ADCSRA_ADFR \ ADC Free Running Select + $10 constant ADCSRA_ADIF \ ADC Interrupt Flag + $08 constant ADCSRA_ADIE \ ADC Interrupt Enable + $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits +&36 constant ADC \ ADC Data Register Bytes + +\ Interrupts +&2 constant INT0Addr \ External Interrupt Request 0 +&4 constant INT1Addr \ External Interrupt Request 1 +&6 constant INT2Addr \ External Interrupt Request 2 +&8 constant INT3Addr \ External Interrupt Request 3 +&10 constant INT4Addr \ External Interrupt Request 4 +&12 constant INT5Addr \ External Interrupt Request 5 +&14 constant INT6Addr \ External Interrupt Request 6 +&16 constant INT7Addr \ External Interrupt Request 7 +&18 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match +&20 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow +&22 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event +&24 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A +&26 constant TIMER1_COMPBAddr \ Timer/Counter Compare Match B +&28 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow +&30 constant TIMER0_COMPAddr \ Timer/Counter0 Compare Match +&32 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow +&34 constant SPI__STCAddr \ SPI Serial Transfer Complete +&36 constant USART0__RXAddr \ USART0, Rx Complete +&38 constant USART0__UDREAddr \ USART0 Data Register Empty +&40 constant USART0__TXAddr \ USART0, Tx Complete +&42 constant ADCAddr \ ADC Conversion Complete +&44 constant EE_READYAddr \ EEPROM Ready +&46 constant ANALOG_COMPAddr \ Analog Comparator +&48 constant TIMER1_COMPCAddr \ Timer/Counter1 Compare Match C +&50 constant TIMER3_CAPTAddr \ Timer/Counter3 Capture Event +&52 constant TIMER3_COMPAAddr \ Timer/Counter3 Compare Match A +&54 constant TIMER3_COMPBAddr \ Timer/Counter3 Compare Match B +&56 constant TIMER3_COMPCAddr \ Timer/Counter3 Compare Match C +&58 constant TIMER3_OVFAddr \ Timer/Counter3 Overflow +&60 constant USART1__RXAddr \ USART1, Rx Complete +&62 constant USART1__UDREAddr \ USART1, Data Register Empty +&64 constant USART1__TXAddr \ USART1, Tx Complete +&66 constant TWIAddr \ 2-wire Serial Interface +&68 constant SPM_READYAddr \ Store Program Memory Read diff --git a/amforth-6.5/avr8/devices/atmega128/device.asm b/amforth-6.5/avr8/devices/atmega128/device.asm new file mode 100644 index 0000000..2466ed0 --- /dev/null +++ b/amforth-6.5/avr8/devices/atmega128/device.asm @@ -0,0 +1,141 @@ +; Partname: ATmega128 +; generated automatically, do not edit + +.nolist + .include "m128def.inc" +.list + +.equ ramstart = 256 +.equ CELLSIZE = 2 +.macro readflashcell + clr temp7 + lsl zl + rol zh + rol temp7 + out_ RAMPZ, temp7 + elpm @0, Z+ + elpm @1, Z+ +.endmacro +.macro writeflashcell + clr temp7 + lsl zl + rol zh + rol temp7 + out_ RAMPZ, temp7 +.endmacro +.set WANT_ANALOG_COMPARATOR = 0 +.set WANT_SPI = 0 +.set WANT_TWI = 0 +.set WANT_USART0 = 0 +.set WANT_USART1 = 0 +.set WANT_CPU = 0 +.set WANT_BOOT_LOAD = 0 +.set WANT_JTAG = 0 +.set WANT_MISC = 0 +.set WANT_EXTERNAL_INTERRUPT = 0 +.set WANT_EEPROM = 0 +.set WANT_PORTA = 0 +.set WANT_PORTB = 0 +.set WANT_PORTC = 0 +.set WANT_PORTD = 0 +.set WANT_PORTE = 0 +.set WANT_PORTF = 0 +.set WANT_PORTG = 0 +.set WANT_TIMER_COUNTER_0 = 0 +.set WANT_TIMER_COUNTER_1 = 0 +.set WANT_TIMER_COUNTER_2 = 0 +.set WANT_TIMER_COUNTER_3 = 0 +.set WANT_WATCHDOG = 0 +.set WANT_AD_CONVERTER = 0 +.equ intvecsize = 2 ; please verify; flash size: 131072 bytes +.equ pclen = 2 ; please verify +.overlap +.org 2 + rcall isr ; External Interrupt Request 0 +.org 4 + rcall isr ; External Interrupt Request 1 +.org 6 + rcall isr ; External Interrupt Request 2 +.org 8 + rcall isr ; External Interrupt Request 3 +.org 10 + rcall isr ; External Interrupt Request 4 +.org 12 + rcall isr ; External Interrupt Request 5 +.org 14 + rcall isr ; External Interrupt Request 6 +.org 16 + rcall isr ; External Interrupt Request 7 +.org 18 + rcall isr ; Timer/Counter2 Compare Match +.org 20 + rcall isr ; Timer/Counter2 Overflow +.org 22 + rcall isr ; Timer/Counter1 Capture Event +.org 24 + rcall isr ; Timer/Counter1 Compare Match A +.org 26 + rcall isr ; Timer/Counter Compare Match B +.org 28 + rcall isr ; Timer/Counter1 Overflow +.org 30 + rcall isr ; Timer/Counter0 Compare Match +.org 32 + rcall isr ; Timer/Counter0 Overflow +.org 34 + rcall isr ; SPI Serial Transfer Complete +.org 36 + rcall isr ; USART0, Rx Complete +.org 38 + rcall isr ; USART0 Data Register Empty +.org 40 + rcall isr ; USART0, Tx Complete +.org 42 + rcall isr ; ADC Conversion Complete +.org 44 + rcall isr ; EEPROM Ready +.org 46 + rcall isr ; Analog Comparator +.org 48 + rcall isr ; Timer/Counter1 Compare Match C +.org 50 + rcall isr ; Timer/Counter3 Capture Event +.org 52 + rcall isr ; Timer/Counter3 Compare Match A +.org 54 + rcall isr ; Timer/Counter3 Compare Match B +.org 56 + rcall isr ; Timer/Counter3 Compare Match C +.org 58 + rcall isr ; Timer/Counter3 Overflow +.org 60 + rcall isr ; USART1, Rx Complete +.org 62 + rcall isr ; USART1, Data Register Empty +.org 64 + rcall isr ; USART1, Tx Complete +.org 66 + rcall isr ; 2-wire Serial Interface +.org 68 + rcall isr ; Store Program Memory Read +.equ INTVECTORS = 35 +.nooverlap + +; compatability layer (maybe empty) +.equ EEPE = EEWE +.equ EEMPE = EEMWE + +; controller data area, environment query mcu-info +mcu_info: +mcu_ramsize: + .dw 4096 +mcu_eepromsize: + .dw 4096 +mcu_maxdp: + .dw 65535 +mcu_numints: + .dw 35 +mcu_name: + .dw 9 + .db "ATmega128",0 +.set codestart=pc diff --git a/amforth-6.5/avr8/devices/atmega128/device.inc b/amforth-6.5/avr8/devices/atmega128/device.inc new file mode 100644 index 0000000..e6ee249 --- /dev/null +++ b/amforth-6.5/avr8/devices/atmega128/device.inc @@ -0,0 +1,1179 @@ +; Partname: ATmega128 +; generated automatically, no not edit + +.if WANT_ANALOG_COMPARATOR == 1 +; ( -- addr ) System Constant +; R( -- ) +; Special Function IO Register +VE_SFIOR: + .dw $ff05 + .db "SFIOR",0 + .dw VE_HEAD + .set VE_HEAD=VE_SFIOR +XT_SFIOR: + .dw PFA_DOVARIABLE +PFA_SFIOR: + .dw 64 +; ( -- addr ) System Constant +; R( -- ) +; Analog Comparator Control And Status Register +VE_ACSR: + .dw $ff04 + .db "ACSR" + .dw VE_HEAD + .set VE_HEAD=VE_ACSR +XT_ACSR: + .dw PFA_DOVARIABLE +PFA_ACSR: + .dw 40 + +.endif +.if WANT_SPI == 1 +; ( -- addr ) System Constant +; R( -- ) +; SPI Data Register +VE_SPDR: + .dw $ff04 + .db "SPDR" + .dw VE_HEAD + .set VE_HEAD=VE_SPDR +XT_SPDR: + .dw PFA_DOVARIABLE +PFA_SPDR: + .dw 47 +; ( -- addr ) System Constant +; R( -- ) +; SPI Status Register +VE_SPSR: + .dw $ff04 + .db "SPSR" + .dw VE_HEAD + .set VE_HEAD=VE_SPSR +XT_SPSR: + .dw PFA_DOVARIABLE +PFA_SPSR: + .dw 46 +; ( -- addr ) System Constant +; R( -- ) +; SPI Control Register +VE_SPCR: + .dw $ff04 + .db "SPCR" + .dw VE_HEAD + .set VE_HEAD=VE_SPCR +XT_SPCR: + .dw PFA_DOVARIABLE +PFA_SPCR: + .dw 45 + +.endif +.if WANT_TWI == 1 +; ( -- addr ) System Constant +; R( -- ) +; TWI Bit Rate register +VE_TWBR: + .dw $ff04 + .db "TWBR" + .dw VE_HEAD + .set VE_HEAD=VE_TWBR +XT_TWBR: + .dw PFA_DOVARIABLE +PFA_TWBR: + .dw 112 +; ( -- addr ) System Constant +; R( -- ) +; TWI Control Register +VE_TWCR: + .dw $ff04 + .db "TWCR" + .dw VE_HEAD + .set VE_HEAD=VE_TWCR +XT_TWCR: + .dw PFA_DOVARIABLE +PFA_TWCR: + .dw 116 +; ( -- addr ) System Constant +; R( -- ) +; TWI Status Register +VE_TWSR: + .dw $ff04 + .db "TWSR" + .dw VE_HEAD + .set VE_HEAD=VE_TWSR +XT_TWSR: + .dw PFA_DOVARIABLE +PFA_TWSR: + .dw 113 +; ( -- addr ) System Constant +; R( -- ) +; TWI Data register +VE_TWDR: + .dw $ff04 + .db "TWDR" + .dw VE_HEAD + .set VE_HEAD=VE_TWDR +XT_TWDR: + .dw PFA_DOVARIABLE +PFA_TWDR: + .dw 115 +; ( -- addr ) System Constant +; R( -- ) +; TWI (Slave) Address register +VE_TWAR: + .dw $ff04 + .db "TWAR" + .dw VE_HEAD + .set VE_HEAD=VE_TWAR +XT_TWAR: + .dw PFA_DOVARIABLE +PFA_TWAR: + .dw 114 + +.endif +.if WANT_USART0 == 1 +; ( -- addr ) System Constant +; R( -- ) +; USART I/O Data Register +VE_UDR0: + .dw $ff04 + .db "UDR0" + .dw VE_HEAD + .set VE_HEAD=VE_UDR0 +XT_UDR0: + .dw PFA_DOVARIABLE +PFA_UDR0: + .dw 44 +; ( -- addr ) System Constant +; R( -- ) +; USART Control and Status Register A +VE_UCSR0A: + .dw $ff06 + .db "UCSR0A" + .dw VE_HEAD + .set VE_HEAD=VE_UCSR0A +XT_UCSR0A: + .dw PFA_DOVARIABLE +PFA_UCSR0A: + .dw 43 +; ( -- addr ) System Constant +; R( -- ) +; USART Control and Status Register B +VE_UCSR0B: + .dw $ff06 + .db "UCSR0B" + .dw VE_HEAD + .set VE_HEAD=VE_UCSR0B +XT_UCSR0B: + .dw PFA_DOVARIABLE +PFA_UCSR0B: + .dw 42 +; ( -- addr ) System Constant +; R( -- ) +; USART Control and Status Register C +VE_UCSR0C: + .dw $ff06 + .db "UCSR0C" + .dw VE_HEAD + .set VE_HEAD=VE_UCSR0C +XT_UCSR0C: + .dw PFA_DOVARIABLE +PFA_UCSR0C: + .dw 149 +; ( -- addr ) System Constant +; R( -- ) +; USART Baud Rate Register Hight Byte +VE_UBRR0H: + .dw $ff06 + .db "UBRR0H" + .dw VE_HEAD + .set VE_HEAD=VE_UBRR0H +XT_UBRR0H: + .dw PFA_DOVARIABLE +PFA_UBRR0H: + .dw 144 +; ( -- addr ) System Constant +; R( -- ) +; USART Baud Rate Register Low Byte +VE_UBRR0L: + .dw $ff06 + .db "UBRR0L" + .dw VE_HEAD + .set VE_HEAD=VE_UBRR0L +XT_UBRR0L: + .dw PFA_DOVARIABLE +PFA_UBRR0L: + .dw 41 + +.endif +.if WANT_USART1 == 1 +; ( -- addr ) System Constant +; R( -- ) +; USART I/O Data Register +VE_UDR1: + .dw $ff04 + .db "UDR1" + .dw VE_HEAD + .set VE_HEAD=VE_UDR1 +XT_UDR1: + .dw PFA_DOVARIABLE +PFA_UDR1: + .dw 156 +; ( -- addr ) System Constant +; R( -- ) +; USART Control and Status Register A +VE_UCSR1A: + .dw $ff06 + .db "UCSR1A" + .dw VE_HEAD + .set VE_HEAD=VE_UCSR1A +XT_UCSR1A: + .dw PFA_DOVARIABLE +PFA_UCSR1A: + .dw 155 +; ( -- addr ) System Constant +; R( -- ) +; USART Control and Status Register B +VE_UCSR1B: + .dw $ff06 + .db "UCSR1B" + .dw VE_HEAD + .set VE_HEAD=VE_UCSR1B +XT_UCSR1B: + .dw PFA_DOVARIABLE +PFA_UCSR1B: + .dw 154 +; ( -- addr ) System Constant +; R( -- ) +; USART Control and Status Register C +VE_UCSR1C: + .dw $ff06 + .db "UCSR1C" + .dw VE_HEAD + .set VE_HEAD=VE_UCSR1C +XT_UCSR1C: + .dw PFA_DOVARIABLE +PFA_UCSR1C: + .dw 157 +; ( -- addr ) System Constant +; R( -- ) +; USART Baud Rate Register Hight Byte +VE_UBRR1H: + .dw $ff06 + .db "UBRR1H" + .dw VE_HEAD + .set VE_HEAD=VE_UBRR1H +XT_UBRR1H: + .dw PFA_DOVARIABLE +PFA_UBRR1H: + .dw 152 +; ( -- addr ) System Constant +; R( -- ) +; USART Baud Rate Register Low Byte +VE_UBRR1L: + .dw $ff06 + .db "UBRR1L" + .dw VE_HEAD + .set VE_HEAD=VE_UBRR1L +XT_UBRR1L: + .dw PFA_DOVARIABLE +PFA_UBRR1L: + .dw 153 + +.endif +.if WANT_CPU == 1 +; ( -- addr ) System Constant +; R( -- ) +; Status Register +VE_SREG: + .dw $ff04 + .db "SREG" + .dw VE_HEAD + .set VE_HEAD=VE_SREG +XT_SREG: + .dw PFA_DOVARIABLE +PFA_SREG: + .dw 95 +; ( -- addr ) System Constant +; R( -- ) +; Stack Pointer +VE_SP: + .dw $ff02 + .db "SP" + .dw VE_HEAD + .set VE_HEAD=VE_SP +XT_SP: + .dw PFA_DOVARIABLE +PFA_SP: + .dw 93 +; ( -- addr ) System Constant +; R( -- ) +; MCU Control Register +VE_MCUCR: + .dw $ff05 + .db "MCUCR",0 + .dw VE_HEAD + .set VE_HEAD=VE_MCUCR +XT_MCUCR: + .dw PFA_DOVARIABLE +PFA_MCUCR: + .dw 85 +; ( -- addr ) System Constant +; R( -- ) +; MCU Control And Status Register +VE_MCUCSR: + .dw $ff06 + .db "MCUCSR" + .dw VE_HEAD + .set VE_HEAD=VE_MCUCSR +XT_MCUCSR: + .dw PFA_DOVARIABLE +PFA_MCUCSR: + .dw 84 +; ( -- addr ) System Constant +; R( -- ) +; External Memory Control Register A +VE_XMCRA: + .dw $ff05 + .db "XMCRA",0 + .dw VE_HEAD + .set VE_HEAD=VE_XMCRA +XT_XMCRA: + .dw PFA_DOVARIABLE +PFA_XMCRA: + .dw 109 +; ( -- addr ) System Constant +; R( -- ) +; External Memory Control Register B +VE_XMCRB: + .dw $ff05 + .db "XMCRB",0 + .dw VE_HEAD + .set VE_HEAD=VE_XMCRB +XT_XMCRB: + .dw PFA_DOVARIABLE +PFA_XMCRB: + .dw 108 +; ( -- addr ) System Constant +; R( -- ) +; Oscillator Calibration Value +VE_OSCCAL: + .dw $ff06 + .db "OSCCAL" + .dw VE_HEAD + .set VE_HEAD=VE_OSCCAL +XT_OSCCAL: + .dw PFA_DOVARIABLE +PFA_OSCCAL: + .dw 111 +; ( -- addr ) System Constant +; R( -- ) +; XTAL Divide Control Register +VE_XDIV: + .dw $ff04 + .db "XDIV" + .dw VE_HEAD + .set VE_HEAD=VE_XDIV +XT_XDIV: + .dw PFA_DOVARIABLE +PFA_XDIV: + .dw 92 +; ( -- addr ) System Constant +; R( -- ) +; RAM Page Z Select Register +VE_RAMPZ: + .dw $ff05 + .db "RAMPZ",0 + .dw VE_HEAD + .set VE_HEAD=VE_RAMPZ +XT_RAMPZ: + .dw PFA_DOVARIABLE +PFA_RAMPZ: + .dw 91 + +.endif +.if WANT_BOOT_LOAD == 1 +; ( -- addr ) System Constant +; R( -- ) +; Store Program Memory Control Register +VE_SPMCSR: + .dw $ff06 + .db "SPMCSR" + .dw VE_HEAD + .set VE_HEAD=VE_SPMCSR +XT_SPMCSR: + .dw PFA_DOVARIABLE +PFA_SPMCSR: + .dw 104 + +.endif +.if WANT_JTAG == 1 +; ( -- addr ) System Constant +; R( -- ) +; On-Chip Debug Related Register in I/O Memory +VE_OCDR: + .dw $ff04 + .db "OCDR" + .dw VE_HEAD + .set VE_HEAD=VE_OCDR +XT_OCDR: + .dw PFA_DOVARIABLE +PFA_OCDR: + .dw 66 + +.endif +.if WANT_MISC == 1 + +.endif +.if WANT_EXTERNAL_INTERRUPT == 1 +; ( -- addr ) System Constant +; R( -- ) +; External Interrupt Control Register A +VE_EICRA: + .dw $ff05 + .db "EICRA",0 + .dw VE_HEAD + .set VE_HEAD=VE_EICRA +XT_EICRA: + .dw PFA_DOVARIABLE +PFA_EICRA: + .dw 106 +; ( -- addr ) System Constant +; R( -- ) +; External Interrupt Control Register B +VE_EICRB: + .dw $ff05 + .db "EICRB",0 + .dw VE_HEAD + .set VE_HEAD=VE_EICRB +XT_EICRB: + .dw PFA_DOVARIABLE +PFA_EICRB: + .dw 90 +; ( -- addr ) System Constant +; R( -- ) +; External Interrupt Mask Register +VE_EIMSK: + .dw $ff05 + .db "EIMSK",0 + .dw VE_HEAD + .set VE_HEAD=VE_EIMSK +XT_EIMSK: + .dw PFA_DOVARIABLE +PFA_EIMSK: + .dw 89 +; ( -- addr ) System Constant +; R( -- ) +; External Interrupt Flag Register +VE_EIFR: + .dw $ff04 + .db "EIFR" + .dw VE_HEAD + .set VE_HEAD=VE_EIFR +XT_EIFR: + .dw PFA_DOVARIABLE +PFA_EIFR: + .dw 88 + +.endif +.if WANT_EEPROM == 1 +; ( -- addr ) System Constant +; R( -- ) +; EEPROM Read/Write Access Bytes +VE_EEAR: + .dw $ff04 + .db "EEAR" + .dw VE_HEAD + .set VE_HEAD=VE_EEAR +XT_EEAR: + .dw PFA_DOVARIABLE +PFA_EEAR: + .dw 62 +; ( -- addr ) System Constant +; R( -- ) +; EEPROM Data Register +VE_EEDR: + .dw $ff04 + .db "EEDR" + .dw VE_HEAD + .set VE_HEAD=VE_EEDR +XT_EEDR: + .dw PFA_DOVARIABLE +PFA_EEDR: + .dw 61 +; ( -- addr ) System Constant +; R( -- ) +; EEPROM Control Register +VE_EECR: + .dw $ff04 + .db "EECR" + .dw VE_HEAD + .set VE_HEAD=VE_EECR +XT_EECR: + .dw PFA_DOVARIABLE +PFA_EECR: + .dw 60 + +.endif +.if WANT_PORTA == 1 +; ( -- addr ) System Constant +; R( -- ) +; Port A Data Register +VE_PORTA: + .dw $ff05 + .db "PORTA",0 + .dw VE_HEAD + .set VE_HEAD=VE_PORTA +XT_PORTA: + .dw PFA_DOVARIABLE +PFA_PORTA: + .dw 59 +; ( -- addr ) System Constant +; R( -- ) +; Port A Data Direction Register +VE_DDRA: + .dw $ff04 + .db "DDRA" + .dw VE_HEAD + .set VE_HEAD=VE_DDRA +XT_DDRA: + .dw PFA_DOVARIABLE +PFA_DDRA: + .dw 58 +; ( -- addr ) System Constant +; R( -- ) +; Port A Input Pins +VE_PINA: + .dw $ff04 + .db "PINA" + .dw VE_HEAD + .set VE_HEAD=VE_PINA +XT_PINA: + .dw PFA_DOVARIABLE +PFA_PINA: + .dw 57 + +.endif +.if WANT_PORTB == 1 +; ( -- addr ) System Constant +; R( -- ) +; Port B Data Register +VE_PORTB: + .dw $ff05 + .db "PORTB",0 + .dw VE_HEAD + .set VE_HEAD=VE_PORTB +XT_PORTB: + .dw PFA_DOVARIABLE +PFA_PORTB: + .dw 56 +; ( -- addr ) System Constant +; R( -- ) +; Port B Data Direction Register +VE_DDRB: + .dw $ff04 + .db "DDRB" + .dw VE_HEAD + .set VE_HEAD=VE_DDRB +XT_DDRB: + .dw PFA_DOVARIABLE +PFA_DDRB: + .dw 55 +; ( -- addr ) System Constant +; R( -- ) +; Port B Input Pins +VE_PINB: + .dw $ff04 + .db "PINB" + .dw VE_HEAD + .set VE_HEAD=VE_PINB +XT_PINB: + .dw PFA_DOVARIABLE +PFA_PINB: + .dw 54 + +.endif +.if WANT_PORTC == 1 +; ( -- addr ) System Constant +; R( -- ) +; Port C Data Register +VE_PORTC: + .dw $ff05 + .db "PORTC",0 + .dw VE_HEAD + .set VE_HEAD=VE_PORTC +XT_PORTC: + .dw PFA_DOVARIABLE +PFA_PORTC: + .dw 53 +; ( -- addr ) System Constant +; R( -- ) +; Port C Data Direction Register +VE_DDRC: + .dw $ff04 + .db "DDRC" + .dw VE_HEAD + .set VE_HEAD=VE_DDRC +XT_DDRC: + .dw PFA_DOVARIABLE +PFA_DDRC: + .dw 52 +; ( -- addr ) System Constant +; R( -- ) +; Port C Input Pins +VE_PINC: + .dw $ff04 + .db "PINC" + .dw VE_HEAD + .set VE_HEAD=VE_PINC +XT_PINC: + .dw PFA_DOVARIABLE +PFA_PINC: + .dw 51 + +.endif +.if WANT_PORTD == 1 +; ( -- addr ) System Constant +; R( -- ) +; Port D Data Register +VE_PORTD: + .dw $ff05 + .db "PORTD",0 + .dw VE_HEAD + .set VE_HEAD=VE_PORTD +XT_PORTD: + .dw PFA_DOVARIABLE +PFA_PORTD: + .dw 50 +; ( -- addr ) System Constant +; R( -- ) +; Port D Data Direction Register +VE_DDRD: + .dw $ff04 + .db "DDRD" + .dw VE_HEAD + .set VE_HEAD=VE_DDRD +XT_DDRD: + .dw PFA_DOVARIABLE +PFA_DDRD: + .dw 49 +; ( -- addr ) System Constant +; R( -- ) +; Port D Input Pins +VE_PIND: + .dw $ff04 + .db "PIND" + .dw VE_HEAD + .set VE_HEAD=VE_PIND +XT_PIND: + .dw PFA_DOVARIABLE +PFA_PIND: + .dw 48 + +.endif +.if WANT_PORTE == 1 +; ( -- addr ) System Constant +; R( -- ) +; Data Register, Port E +VE_PORTE: + .dw $ff05 + .db "PORTE",0 + .dw VE_HEAD + .set VE_HEAD=VE_PORTE +XT_PORTE: + .dw PFA_DOVARIABLE +PFA_PORTE: + .dw 35 +; ( -- addr ) System Constant +; R( -- ) +; Data Direction Register, Port E +VE_DDRE: + .dw $ff04 + .db "DDRE" + .dw VE_HEAD + .set VE_HEAD=VE_DDRE +XT_DDRE: + .dw PFA_DOVARIABLE +PFA_DDRE: + .dw 34 +; ( -- addr ) System Constant +; R( -- ) +; Input Pins, Port E +VE_PINE: + .dw $ff04 + .db "PINE" + .dw VE_HEAD + .set VE_HEAD=VE_PINE +XT_PINE: + .dw PFA_DOVARIABLE +PFA_PINE: + .dw 33 + +.endif +.if WANT_PORTF == 1 +; ( -- addr ) System Constant +; R( -- ) +; Data Register, Port F +VE_PORTF: + .dw $ff05 + .db "PORTF",0 + .dw VE_HEAD + .set VE_HEAD=VE_PORTF +XT_PORTF: + .dw PFA_DOVARIABLE +PFA_PORTF: + .dw 98 +; ( -- addr ) System Constant +; R( -- ) +; Data Direction Register, Port F +VE_DDRF: + .dw $ff04 + .db "DDRF" + .dw VE_HEAD + .set VE_HEAD=VE_DDRF +XT_DDRF: + .dw PFA_DOVARIABLE +PFA_DDRF: + .dw 97 +; ( -- addr ) System Constant +; R( -- ) +; Input Pins, Port F +VE_PINF: + .dw $ff04 + .db "PINF" + .dw VE_HEAD + .set VE_HEAD=VE_PINF +XT_PINF: + .dw PFA_DOVARIABLE +PFA_PINF: + .dw 32 + +.endif +.if WANT_PORTG == 1 +; ( -- addr ) System Constant +; R( -- ) +; Data Register, Port G +VE_PORTG: + .dw $ff05 + .db "PORTG",0 + .dw VE_HEAD + .set VE_HEAD=VE_PORTG +XT_PORTG: + .dw PFA_DOVARIABLE +PFA_PORTG: + .dw 101 +; ( -- addr ) System Constant +; R( -- ) +; Data Direction Register, Port G +VE_DDRG: + .dw $ff04 + .db "DDRG" + .dw VE_HEAD + .set VE_HEAD=VE_DDRG +XT_DDRG: + .dw PFA_DOVARIABLE +PFA_DDRG: + .dw 100 +; ( -- addr ) System Constant +; R( -- ) +; Input Pins, Port G +VE_PING: + .dw $ff04 + .db "PING" + .dw VE_HEAD + .set VE_HEAD=VE_PING +XT_PING: + .dw PFA_DOVARIABLE +PFA_PING: + .dw 99 + +.endif +.if WANT_TIMER_COUNTER_0 == 1 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter Control Register +VE_TCCR0: + .dw $ff05 + .db "TCCR0",0 + .dw VE_HEAD + .set VE_HEAD=VE_TCCR0 +XT_TCCR0: + .dw PFA_DOVARIABLE +PFA_TCCR0: + .dw 83 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter Register +VE_TCNT0: + .dw $ff05 + .db "TCNT0",0 + .dw VE_HEAD + .set VE_HEAD=VE_TCNT0 +XT_TCNT0: + .dw PFA_DOVARIABLE +PFA_TCNT0: + .dw 82 +; ( -- addr ) System Constant +; R( -- ) +; Output Compare Register +VE_OCR0: + .dw $ff04 + .db "OCR0" + .dw VE_HEAD + .set VE_HEAD=VE_OCR0 +XT_OCR0: + .dw PFA_DOVARIABLE +PFA_OCR0: + .dw 81 +; ( -- addr ) System Constant +; R( -- ) +; Asynchronus Status Register +VE_ASSR: + .dw $ff04 + .db "ASSR" + .dw VE_HEAD + .set VE_HEAD=VE_ASSR +XT_ASSR: + .dw PFA_DOVARIABLE +PFA_ASSR: + .dw 80 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter Interrupt Mask Register +VE_TIMSK: + .dw $ff05 + .db "TIMSK",0 + .dw VE_HEAD + .set VE_HEAD=VE_TIMSK +XT_TIMSK: + .dw PFA_DOVARIABLE +PFA_TIMSK: + .dw 87 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter Interrupt Flag register +VE_TIFR: + .dw $ff04 + .db "TIFR" + .dw VE_HEAD + .set VE_HEAD=VE_TIFR +XT_TIFR: + .dw PFA_DOVARIABLE +PFA_TIFR: + .dw 86 + +.endif +.if WANT_TIMER_COUNTER_1 == 1 +; ( -- addr ) System Constant +; R( -- ) +; Extended Timer/Counter Interrupt Mask Register +VE_ETIMSK: + .dw $ff06 + .db "ETIMSK" + .dw VE_HEAD + .set VE_HEAD=VE_ETIMSK +XT_ETIMSK: + .dw PFA_DOVARIABLE +PFA_ETIMSK: + .dw 125 +; ( -- addr ) System Constant +; R( -- ) +; Extended Timer/Counter Interrupt Flag register +VE_ETIFR: + .dw $ff05 + .db "ETIFR",0 + .dw VE_HEAD + .set VE_HEAD=VE_ETIFR +XT_ETIFR: + .dw PFA_DOVARIABLE +PFA_ETIFR: + .dw 124 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter1 Control Register A +VE_TCCR1A: + .dw $ff06 + .db "TCCR1A" + .dw VE_HEAD + .set VE_HEAD=VE_TCCR1A +XT_TCCR1A: + .dw PFA_DOVARIABLE +PFA_TCCR1A: + .dw 79 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter1 Control Register B +VE_TCCR1B: + .dw $ff06 + .db "TCCR1B" + .dw VE_HEAD + .set VE_HEAD=VE_TCCR1B +XT_TCCR1B: + .dw PFA_DOVARIABLE +PFA_TCCR1B: + .dw 78 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter1 Control Register C +VE_TCCR1C: + .dw $ff06 + .db "TCCR1C" + .dw VE_HEAD + .set VE_HEAD=VE_TCCR1C +XT_TCCR1C: + .dw PFA_DOVARIABLE +PFA_TCCR1C: + .dw 122 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter1 Bytes +VE_TCNT1: + .dw $ff05 + .db "TCNT1",0 + .dw VE_HEAD + .set VE_HEAD=VE_TCNT1 +XT_TCNT1: + .dw PFA_DOVARIABLE +PFA_TCNT1: + .dw 76 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter1 Output Compare Register Bytes +VE_OCR1A: + .dw $ff05 + .db "OCR1A",0 + .dw VE_HEAD + .set VE_HEAD=VE_OCR1A +XT_OCR1A: + .dw PFA_DOVARIABLE +PFA_OCR1A: + .dw 74 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter1 Output Compare Register Bytes +VE_OCR1B: + .dw $ff05 + .db "OCR1B",0 + .dw VE_HEAD + .set VE_HEAD=VE_OCR1B +XT_OCR1B: + .dw PFA_DOVARIABLE +PFA_OCR1B: + .dw 72 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter1 Output Compare Register Bytes +VE_OCR1C: + .dw $ff05 + .db "OCR1C",0 + .dw VE_HEAD + .set VE_HEAD=VE_OCR1C +XT_OCR1C: + .dw PFA_DOVARIABLE +PFA_OCR1C: + .dw 120 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter1 Input Capture Register Bytes +VE_ICR1: + .dw $ff04 + .db "ICR1" + .dw VE_HEAD + .set VE_HEAD=VE_ICR1 +XT_ICR1: + .dw PFA_DOVARIABLE +PFA_ICR1: + .dw 70 + +.endif +.if WANT_TIMER_COUNTER_2 == 1 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter Control Register +VE_TCCR2: + .dw $ff05 + .db "TCCR2",0 + .dw VE_HEAD + .set VE_HEAD=VE_TCCR2 +XT_TCCR2: + .dw PFA_DOVARIABLE +PFA_TCCR2: + .dw 69 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter Register +VE_TCNT2: + .dw $ff05 + .db "TCNT2",0 + .dw VE_HEAD + .set VE_HEAD=VE_TCNT2 +XT_TCNT2: + .dw PFA_DOVARIABLE +PFA_TCNT2: + .dw 68 +; ( -- addr ) System Constant +; R( -- ) +; Output Compare Register +VE_OCR2: + .dw $ff04 + .db "OCR2" + .dw VE_HEAD + .set VE_HEAD=VE_OCR2 +XT_OCR2: + .dw PFA_DOVARIABLE +PFA_OCR2: + .dw 67 + +.endif +.if WANT_TIMER_COUNTER_3 == 1 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter3 Control Register A +VE_TCCR3A: + .dw $ff06 + .db "TCCR3A" + .dw VE_HEAD + .set VE_HEAD=VE_TCCR3A +XT_TCCR3A: + .dw PFA_DOVARIABLE +PFA_TCCR3A: + .dw 139 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter3 Control Register B +VE_TCCR3B: + .dw $ff06 + .db "TCCR3B" + .dw VE_HEAD + .set VE_HEAD=VE_TCCR3B +XT_TCCR3B: + .dw PFA_DOVARIABLE +PFA_TCCR3B: + .dw 138 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter3 Control Register C +VE_TCCR3C: + .dw $ff06 + .db "TCCR3C" + .dw VE_HEAD + .set VE_HEAD=VE_TCCR3C +XT_TCCR3C: + .dw PFA_DOVARIABLE +PFA_TCCR3C: + .dw 140 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter3 Bytes +VE_TCNT3: + .dw $ff05 + .db "TCNT3",0 + .dw VE_HEAD + .set VE_HEAD=VE_TCNT3 +XT_TCNT3: + .dw PFA_DOVARIABLE +PFA_TCNT3: + .dw 136 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter3 Output Compare Register A Bytes +VE_OCR3A: + .dw $ff05 + .db "OCR3A",0 + .dw VE_HEAD + .set VE_HEAD=VE_OCR3A +XT_OCR3A: + .dw PFA_DOVARIABLE +PFA_OCR3A: + .dw 134 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter3 Output Compare Register B Bytes +VE_OCR3B: + .dw $ff05 + .db "OCR3B",0 + .dw VE_HEAD + .set VE_HEAD=VE_OCR3B +XT_OCR3B: + .dw PFA_DOVARIABLE +PFA_OCR3B: + .dw 132 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter3 Output compare Register C Bytes +VE_OCR3C: + .dw $ff05 + .db "OCR3C",0 + .dw VE_HEAD + .set VE_HEAD=VE_OCR3C +XT_OCR3C: + .dw PFA_DOVARIABLE +PFA_OCR3C: + .dw 130 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter3 Input Capture Register Bytes +VE_ICR3: + .dw $ff04 + .db "ICR3" + .dw VE_HEAD + .set VE_HEAD=VE_ICR3 +XT_ICR3: + .dw PFA_DOVARIABLE +PFA_ICR3: + .dw 128 + +.endif +.if WANT_WATCHDOG == 1 +; ( -- addr ) System Constant +; R( -- ) +; Watchdog Timer Control Register +VE_WDTCR: + .dw $ff05 + .db "WDTCR",0 + .dw VE_HEAD + .set VE_HEAD=VE_WDTCR +XT_WDTCR: + .dw PFA_DOVARIABLE +PFA_WDTCR: + .dw 65 + +.endif +.if WANT_AD_CONVERTER == 1 +; ( -- addr ) System Constant +; R( -- ) +; The ADC multiplexer Selection Register +VE_ADMUX: + .dw $ff05 + .db "ADMUX",0 + .dw VE_HEAD + .set VE_HEAD=VE_ADMUX +XT_ADMUX: + .dw PFA_DOVARIABLE +PFA_ADMUX: + .dw 39 +; ( -- addr ) System Constant +; R( -- ) +; The ADC Control and Status register +VE_ADCSRA: + .dw $ff06 + .db "ADCSRA" + .dw VE_HEAD + .set VE_HEAD=VE_ADCSRA +XT_ADCSRA: + .dw PFA_DOVARIABLE +PFA_ADCSRA: + .dw 38 +; ( -- addr ) System Constant +; R( -- ) +; ADC Data Register Bytes +VE_ADC: + .dw $ff03 + .db "ADC",0 + .dw VE_HEAD + .set VE_HEAD=VE_ADC +XT_ADC: + .dw PFA_DOVARIABLE +PFA_ADC: + .dw 36 + +.endif diff --git a/amforth-6.5/avr8/devices/atmega128/device.py b/amforth-6.5/avr8/devices/atmega128/device.py new file mode 100644 index 0000000..fbb8cb1 --- /dev/null +++ b/amforth-6.5/avr8/devices/atmega128/device.py @@ -0,0 +1,403 @@ +# Generated Automatically + +# Partname ATmega128 + +MCUREGS = { +# Interrupt Vectors + 'INT0Addr' : '#2', # External Interrupt Request 0 + 'INT1Addr' : '#4', # External Interrupt Request 1 + 'INT2Addr' : '#6', # External Interrupt Request 2 + 'INT3Addr' : '#8', # External Interrupt Request 3 + 'INT4Addr' : '#10', # External Interrupt Request 4 + 'INT5Addr' : '#12', # External Interrupt Request 5 + 'INT6Addr' : '#14', # External Interrupt Request 6 + 'INT7Addr' : '#16', # External Interrupt Request 7 + 'TIMER2_COMPAddr' : '#18', # Timer/Counter2 Compare Match + 'TIMER2_OVFAddr' : '#20', # Timer/Counter2 Overflow + 'TIMER1_CAPTAddr' : '#22', # Timer/Counter1 Capture Event + 'TIMER1_COMPAAddr' : '#24', # Timer/Counter1 Compare Match A + 'TIMER1_COMPBAddr' : '#26', # Timer/Counter Compare Match B + 'TIMER1_OVFAddr' : '#28', # Timer/Counter1 Overflow + 'TIMER0_COMPAddr' : '#30', # Timer/Counter0 Compare Match + 'TIMER0_OVFAddr' : '#32', # Timer/Counter0 Overflow + 'SPI_STCAddr' : '#34', # SPI Serial Transfer Complete + 'USART0_RXAddr' : '#36', # USART0, Rx Complete + 'USART0_UDREAddr' : '#38', # USART0 Data Register Empty + 'USART0_TXAddr' : '#40', # USART0, Tx Complete + 'ADCAddr' : '#42', # ADC Conversion Complete + 'EE_READYAddr' : '#44', # EEPROM Ready + 'ANALOG_COMPAddr' : '#46', # Analog Comparator + 'TIMER1_COMPCAddr' : '#48', # Timer/Counter1 Compare Match C + 'TIMER3_CAPTAddr' : '#50', # Timer/Counter3 Capture Event + 'TIMER3_COMPAAddr' : '#52', # Timer/Counter3 Compare Match A + 'TIMER3_COMPBAddr' : '#54', # Timer/Counter3 Compare Match B + 'TIMER3_COMPCAddr' : '#56', # Timer/Counter3 Compare Match C + 'TIMER3_OVFAddr' : '#58', # Timer/Counter3 Overflow + 'USART1_RXAddr' : '#60', # USART1, Rx Complete + 'USART1_UDREAddr' : '#62', # USART1, Data Register Empty + 'USART1_TXAddr' : '#64', # USART1, Tx Complete + 'TWIAddr' : '#66', # 2-wire Serial Interface + 'SPM_READYAddr' : '#68', # Store Program Memory Read + +# Module ANALOG_COMPARATOR + 'SFIOR' : '$40', # Special Function IO Register + 'SFIOR_ACME': '$8', # Analog Comparator Multiplexer + 'ACSR' : '$28', # Analog Comparator Control And + 'ACSR_ACD': '$80', # Analog Comparator Disable + 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele + 'ACSR_ACO': '$20', # Analog Compare Output + 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl + 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En + 'ACSR_ACIC': '$4', # Analog Comparator Input Captur + 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo + +# Module SPI + 'SPDR' : '$2f', # SPI Data Register + 'SPSR' : '$2e', # SPI Status Register + 'SPSR_SPIF': '$80', # SPI Interrupt Flag + 'SPSR_WCOL': '$40', # Write Collision Flag + 'SPSR_SPI2X': '$1', # Double SPI Speed Bit + 'SPCR' : '$2d', # SPI Control Register + 'SPCR_SPIE': '$80', # SPI Interrupt Enable + 'SPCR_SPE': '$40', # SPI Enable + 'SPCR_DORD': '$20', # Data Order + 'SPCR_MSTR': '$10', # Master/Slave Select + 'SPCR_CPOL': '$8', # Clock polarity + 'SPCR_CPHA': '$4', # Clock Phase + 'SPCR_SPR': '$3', # SPI Clock Rate Selects + +# Module TWI + 'TWBR' : '$70', # TWI Bit Rate register + 'TWCR' : '$74', # TWI Control Register + 'TWCR_TWINT': '$80', # TWI Interrupt Flag + 'TWCR_TWEA': '$40', # TWI Enable Acknowledge Bit + 'TWCR_TWSTA': '$20', # TWI Start Condition Bit + 'TWCR_TWSTO': '$10', # TWI Stop Condition Bit + 'TWCR_TWWC': '$8', # TWI Write Collition Flag + 'TWCR_TWEN': '$4', # TWI Enable Bit + 'TWCR_TWIE': '$1', # TWI Interrupt Enable + 'TWSR' : '$71', # TWI Status Register + 'TWSR_TWS': '$f8', # TWI Status + 'TWSR_TWPS': '$3', # TWI Prescaler + 'TWDR' : '$73', # TWI Data register + 'TWAR' : '$72', # TWI (Slave) Address register + 'TWAR_TWA': '$fe', # TWI (Slave) Address register B + 'TWAR_TWGCE': '$1', # TWI General Call Recognition E + +# Module USART0 + 'UDR0' : '$2c', # USART I/O Data Register + 'UCSR0A' : '$2b', # USART Control and Status Regis + 'UCSR0A_RXC0': '$80', # USART Receive Complete + 'UCSR0A_TXC0': '$40', # USART Transmitt Complete + 'UCSR0A_UDRE0': '$20', # USART Data Register Empty + 'UCSR0A_FE0': '$10', # Framing Error + 'UCSR0A_DOR0': '$8', # Data overRun + 'UCSR0A_UPE0': '$4', # Parity Error + 'UCSR0A_U2X0': '$2', # Double the USART transmission + 'UCSR0A_MPCM0': '$1', # Multi-processor Communication + 'UCSR0B' : '$2a', # USART Control and Status Regis + 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable + 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable + 'UCSR0B_UDRIE0': '$20', # USART Data register Empty Inte + 'UCSR0B_RXEN0': '$10', # Receiver Enable + 'UCSR0B_TXEN0': '$8', # Transmitter Enable + 'UCSR0B_UCSZ02': '$4', # Character Size + 'UCSR0B_RXB80': '$2', # Receive Data Bit 8 + 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8 + 'UCSR0C' : '$95', # USART Control and Status Regis + 'UCSR0C_UMSEL0': '$40', # USART Mode Select + 'UCSR0C_UPM0': '$30', # Parity Mode Bits + 'UCSR0C_USBS0': '$8', # Stop Bit Select + 'UCSR0C_UCSZ0': '$6', # Character Size + 'UCSR0C_UCPOL0': '$1', # Clock Polarity + 'UBRR0H' : '$90', # USART Baud Rate Register Hight + 'UBRR0L' : '$29', # USART Baud Rate Register Low B + +# Module USART1 + 'UDR1' : '$9c', # USART I/O Data Register + 'UCSR1A' : '$9b', # USART Control and Status Regis + 'UCSR1A_RXC1': '$80', # USART Receive Complete + 'UCSR1A_TXC1': '$40', # USART Transmitt Complete + 'UCSR1A_UDRE1': '$20', # USART Data Register Empty + 'UCSR1A_FE1': '$10', # Framing Error + 'UCSR1A_DOR1': '$8', # Data overRun + 'UCSR1A_UPE1': '$4', # Parity Error + 'UCSR1A_U2X1': '$2', # Double the USART transmission + 'UCSR1A_MPCM1': '$1', # Multi-processor Communication + 'UCSR1B' : '$9a', # USART Control and Status Regis + 'UCSR1B_RXCIE1': '$80', # RX Complete Interrupt Enable + 'UCSR1B_TXCIE1': '$40', # TX Complete Interrupt Enable + 'UCSR1B_UDRIE1': '$20', # USART Data register Empty Inte + 'UCSR1B_RXEN1': '$10', # Receiver Enable + 'UCSR1B_TXEN1': '$8', # Transmitter Enable + 'UCSR1B_UCSZ12': '$4', # Character Size + 'UCSR1B_RXB81': '$2', # Receive Data Bit 8 + 'UCSR1B_TXB81': '$1', # Transmit Data Bit 8 + 'UCSR1C' : '$9d', # USART Control and Status Regis + 'UCSR1C_UMSEL1': '$40', # USART Mode Select + 'UCSR1C_UPM1': '$30', # Parity Mode Bits + 'UCSR1C_USBS1': '$8', # Stop Bit Select + 'UCSR1C_UCSZ1': '$6', # Character Size + 'UCSR1C_UCPOL1': '$1', # Clock Polarity + 'UBRR1H' : '$98', # USART Baud Rate Register Hight + 'UBRR1L' : '$99', # USART Baud Rate Register Low B + +# Module CPU + 'SREG' : '$5f', # Status Register + 'SREG_I': '$80', # Global Interrupt Enable + 'SREG_T': '$40', # Bit Copy Storage + 'SREG_H': '$20', # Half Carry Flag + 'SREG_S': '$10', # Sign Bit + 'SREG_V': '$8', # Two's Complement Overflow Flag + 'SREG_N': '$4', # Negative Flag + 'SREG_Z': '$2', # Zero Flag + 'SREG_C': '$1', # Carry Flag + 'SP' : '$5d', # Stack Pointer + 'MCUCR' : '$55', # MCU Control Register + 'MCUCR_SRE': '$80', # External SRAM Enable + 'MCUCR_SRW10': '$40', # External SRAM Wait State Selec + 'MCUCR_SE': '$20', # Sleep Enable + 'MCUCR_SM': '$18', # Sleep Mode Select + 'MCUCR_SM2': '$4', # Sleep Mode Select + 'MCUCR_IVSEL': '$2', # Interrupt Vector Select + 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable + 'MCUCSR' : '$54', # MCU Control And Status Registe + 'MCUCSR_JTD': '$80', # JTAG Interface Disable + 'MCUCSR_JTRF': '$10', # JTAG Reset Flag + 'MCUCSR_WDRF': '$8', # Watchdog Reset Flag + 'MCUCSR_BORF': '$4', # Brown-out Reset Flag + 'MCUCSR_EXTRF': '$2', # External Reset Flag + 'MCUCSR_PORF': '$1', # Power-on reset flag + 'XMCRA' : '$6d', # External Memory Control Regist + 'XMCRA_SRL': '$70', # Wait state page limit + 'XMCRA_SRW0': '$c', # Wait state select bit lower pa + 'XMCRA_SRW11': '$2', # Wait state select bit upper pa + 'XMCRB' : '$6c', # External Memory Control Regist + 'XMCRB_XMBK': '$80', # External Memory Bus Keeper Ena + 'XMCRB_XMM': '$7', # External Memory High Mask + 'OSCCAL' : '$6f', # Oscillator Calibration Value + 'XDIV' : '$5c', # XTAL Divide Control Register + 'RAMPZ' : '$5b', # RAM Page Z Select Register + 'RAMPZ_RAMPZ0': '$1', # RAM Page Z Select Register Bit + +# Module BOOT_LOAD + 'SPMCSR' : '$68', # Store Program Memory Control R + 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable + 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy + 'SPMCSR_RWWSRE': '$10', # Read While Write section read + 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set + 'SPMCSR_PGWRT': '$4', # Page Write + 'SPMCSR_PGERS': '$2', # Page Erase + 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable + +# Module JTAG + 'OCDR' : '$42', # On-Chip Debug Related Register + 'OCDR_OCDR': '$ff', # On-Chip Debug Register Bits + 'MCUCSR' : '$54', # MCU Control And Status Registe + 'MCUCSR_JTD': '$80', # JTAG Interface Disable + 'MCUCSR_JTRF': '$10', # JTAG Reset Flag + +# Module MISC + 'SFIOR' : '$40', # Special Function IO Register + 'SFIOR_TSM': '$80', # Timer/Counter Synchronization + 'SFIOR_ACME': '$8', # Analog Comparator Multiplexer + 'SFIOR_PUD': '$4', # Pull Up Disable + 'SFIOR_PSR0': '$2', # Prescaler Reset Timer/Counter0 + 'SFIOR_PSR321': '$1', # Prescaler Reset Timer/Counter3 + +# Module EXTERNAL_INTERRUPT + 'EICRA' : '$6a', # External Interrupt Control Reg + 'EICRA_ISC3': '$c0', # External Interrupt Sense Contr + 'EICRA_ISC2': '$30', # External Interrupt Sense Contr + 'EICRA_ISC1': '$c', # External Interrupt Sense Contr + 'EICRA_ISC0': '$3', # External Interrupt Sense Contr + 'EICRB' : '$5a', # External Interrupt Control Reg + 'EICRB_ISC7': '$c0', # External Interrupt 7-4 Sense C + 'EICRB_ISC6': '$30', # External Interrupt 7-4 Sense C + 'EICRB_ISC5': '$c', # External Interrupt 7-4 Sense C + 'EICRB_ISC4': '$3', # External Interrupt 7-4 Sense C + 'EIMSK' : '$59', # External Interrupt Mask Regist + 'EIMSK_INT': '$ff', # External Interrupt Request 7 E + 'EIFR' : '$58', # External Interrupt Flag Regist + 'EIFR_INTF': '$ff', # External Interrupt Flags + +# Module EEPROM + 'EEAR' : '$3e', # EEPROM Read/Write Access Byte + 'EEDR' : '$3d', # EEPROM Data Register + 'EECR' : '$3c', # EEPROM Control Register + 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable + 'EECR_EEMWE': '$4', # EEPROM Master Write Enable + 'EECR_EEWE': '$2', # EEPROM Write Enable + 'EECR_EERE': '$1', # EEPROM Read Enable + +# Module PORTA + 'PORTA' : '$3b', # Port A Data Register + 'DDRA' : '$3a', # Port A Data Direction Register + 'PINA' : '$39', # Port A Input Pins + +# Module PORTB + 'PORTB' : '$38', # Port B Data Register + 'DDRB' : '$37', # Port B Data Direction Register + 'PINB' : '$36', # Port B Input Pins + +# Module PORTC + 'PORTC' : '$35', # Port C Data Register + 'DDRC' : '$34', # Port C Data Direction Register + 'PINC' : '$33', # Port C Input Pins + +# Module PORTD + 'PORTD' : '$32', # Port D Data Register + 'DDRD' : '$31', # Port D Data Direction Register + 'PIND' : '$30', # Port D Input Pins + +# Module PORTE + 'PORTE' : '$23', # Data Register, Port E + 'DDRE' : '$22', # Data Direction Register, Port + 'PINE' : '$21', # Input Pins, Port E + +# Module PORTF + 'PORTF' : '$62', # Data Register, Port F + 'DDRF' : '$61', # Data Direction Register, Port + 'PINF' : '$20', # Input Pins, Port F + +# Module PORTG + 'PORTG' : '$65', # Data Register, Port G + 'DDRG' : '$64', # Data Direction Register, Port + 'PING' : '$63', # Input Pins, Port G + +# Module TIMER_COUNTER_0 + 'TCCR0' : '$53', # Timer/Counter Control Register + 'TCCR0_FOC0': '$80', # Force Output Compare + 'TCCR0_WGM00': '$40', # Waveform Generation Mode 0 + 'TCCR0_COM0': '$30', # Compare Match Output Modes + 'TCCR0_WGM01': '$8', # Waveform Generation Mode 1 + 'TCCR0_CS0': '$7', # Clock Selects + 'TCNT0' : '$52', # Timer/Counter Register + 'OCR0' : '$51', # Output Compare Register + 'ASSR' : '$50', # Asynchronus Status Register + 'ASSR_AS0': '$8', # Asynchronus Timer/Counter 0 + 'ASSR_TCN0UB': '$4', # Timer/Counter0 Update Busy + 'ASSR_OCR0UB': '$2', # Output Compare register 0 Busy + 'ASSR_TCR0UB': '$1', # Timer/Counter Control Register + 'TIMSK' : '$57', # Timer/Counter Interrupt Mask R + 'TIMSK_OCIE0': '$2', # Timer/Counter0 Output Compare + 'TIMSK_TOIE0': '$1', # Timer/Counter0 Overflow Interr + 'TIFR' : '$56', # Timer/Counter Interrupt Flag r + 'TIFR_OCF0': '$2', # Output Compare Flag 0 + 'TIFR_TOV0': '$1', # Timer/Counter0 Overflow Flag + 'SFIOR' : '$40', # Special Function IO Register + 'SFIOR_TSM': '$80', # Timer/Counter Synchronization + 'SFIOR_PSR0': '$2', # Prescaler Reset Timer/Counter0 + +# Module TIMER_COUNTER_1 + 'TIMSK' : '$57', # Timer/Counter Interrupt Mask R + 'TIMSK_TICIE1': '$20', # Timer/Counter1 Input Capture I + 'TIMSK_OCIE1A': '$10', # Timer/Counter1 Output CompareA + 'TIMSK_OCIE1B': '$8', # Timer/Counter1 Output CompareB + 'TIMSK_TOIE1': '$4', # Timer/Counter1 Overflow Interr + 'ETIMSK' : '$7d', # Extended Timer/Counter Interru + 'ETIMSK_OCIE1C': '$1', # Timer/Counter 1, Output Compar + 'TIFR' : '$56', # Timer/Counter Interrupt Flag r + 'TIFR_ICF1': '$20', # Input Capture Flag 1 + 'TIFR_OCF1A': '$10', # Output Compare Flag 1A + 'TIFR_OCF1B': '$8', # Output Compare Flag 1B + 'TIFR_TOV1': '$4', # Timer/Counter1 Overflow Flag + 'ETIFR' : '$7c', # Extended Timer/Counter Interru + 'ETIFR_OCF1C': '$1', # Timer/Counter 1, Output Compar + 'SFIOR' : '$40', # Special Function IO Register + 'SFIOR_TSM': '$80', # Timer/Counter Synchronization + 'SFIOR_PSR321': '$1', # Prescaler Reset, T/C3, T/C2, T + 'TCCR1A' : '$4f', # Timer/Counter1 Control Registe + 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits + 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits + 'TCCR1A_COM1C': '$c', # Compare Output Mode 1C, bits + 'TCCR1A_WGM1': '$3', # Waveform Generation Mode Bits + 'TCCR1B' : '$4e', # Timer/Counter1 Control Registe + 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler + 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select + 'TCCR1B_WGM1': '$18', # Waveform Generation Mode + 'TCCR1B_CS1': '$7', # Clock Select1 bits + 'TCCR1C' : '$7a', # Timer/Counter1 Control Registe + 'TCCR1C_FOC1A': '$80', # Force Output Compare for chann + 'TCCR1C_FOC1B': '$40', # Force Output Compare for chann + 'TCCR1C_FOC1C': '$20', # Force Output Compare for chann + 'TCNT1' : '$4c', # Timer/Counter1 Bytes + 'OCR1A' : '$4a', # Timer/Counter1 Output Compare + 'OCR1B' : '$48', # Timer/Counter1 Output Compare + 'OCR1C' : '$78', # Timer/Counter1 Output Compare + 'ICR1' : '$46', # Timer/Counter1 Input Capture R + +# Module TIMER_COUNTER_2 + 'TCCR2' : '$45', # Timer/Counter Control Register + 'TCCR2_FOC2': '$80', # Force Output Compare + 'TCCR2_WGM20': '$40', # Wafeform Generation Mode + 'TCCR2_COM2': '$30', # Compare Match Output Mode + 'TCCR2_WGM21': '$8', # Waveform Generation Mode + 'TCCR2_CS2': '$7', # Clock Select + 'TCNT2' : '$44', # Timer/Counter Register + 'OCR2' : '$43', # Output Compare Register + 'TIFR' : '$56', # Timer/Counter Interrupt Flag R + 'TIFR_OCF2': '$80', # Output Compare Flag 2 + 'TIFR_TOV2': '$40', # Timer/Counter2 Overflow Flag + 'TIMSK' : '$57', # + 'TIMSK_OCIE2': '$80', # + 'TIMSK_TOIE2': '$40', # + +# Module TIMER_COUNTER_3 + 'ETIMSK' : '$7d', # Extended Timer/Counter Interru + 'ETIMSK_TICIE3': '$20', # Timer/Counter3 Input Capture I + 'ETIMSK_OCIE3A': '$10', # Timer/Counter3 Output CompareA + 'ETIMSK_OCIE3B': '$8', # Timer/Counter3 Output CompareB + 'ETIMSK_TOIE3': '$4', # Timer/Counter3 Overflow Interr + 'ETIMSK_OCIE3C': '$2', # Timer/Counter3, Output Compare + 'ETIFR' : '$7c', # Extended Timer/Counter Interru + 'ETIFR_ICF3': '$20', # Input Capture Flag 1 + 'ETIFR_OCF3A': '$10', # Output Compare Flag 1A + 'ETIFR_OCF3B': '$8', # Output Compare Flag 1B + 'ETIFR_TOV3': '$4', # Timer/Counter3 Overflow Flag + 'ETIFR_OCF3C': '$2', # Timer/Counter3 Output Compare + 'SFIOR' : '$40', # Special Function IO Register + 'SFIOR_TSM': '$80', # Timer/Counter Synchronization + 'SFIOR_PSR321': '$1', # Prescaler Reset, T/C3, T/C2, T + 'TCCR3A' : '$8b', # Timer/Counter3 Control Registe + 'TCCR3A_COM3A': '$c0', # Compare Output Mode 3A, bits + 'TCCR3A_COM3B': '$30', # Compare Output Mode 3B, bits + 'TCCR3A_COM3C': '$c', # Compare Output Mode 3C, bits + 'TCCR3A_WGM3': '$3', # Waveform Generation Mode Bits + 'TCCR3B' : '$8a', # Timer/Counter3 Control Registe + 'TCCR3B_ICNC3': '$80', # Input Capture 3 Noise Cancele + 'TCCR3B_ICES3': '$40', # Input Capture 3 Edge Select + 'TCCR3B_WGM3': '$18', # Waveform Generation Mode + 'TCCR3B_CS3': '$7', # Clock Select3 bits + 'TCCR3C' : '$8c', # Timer/Counter3 Control Registe + 'TCCR3C_FOC3A': '$80', # Force Output Compare for chann + 'TCCR3C_FOC3B': '$40', # Force Output Compare for chann + 'TCCR3C_FOC3C': '$20', # Force Output Compare for chann + 'TCNT3' : '$88', # Timer/Counter3 Bytes + 'OCR3A' : '$86', # Timer/Counter3 Output Compare + 'OCR3B' : '$84', # Timer/Counter3 Output Compare + 'OCR3C' : '$82', # Timer/Counter3 Output compare + 'ICR3' : '$80', # Timer/Counter3 Input Capture R + +# Module WATCHDOG + 'WDTCR' : '$41', # Watchdog Timer Control Registe + 'WDTCR_WDCE': '$10', # Watchdog Change Enable + 'WDTCR_WDE': '$8', # Watch Dog Enable + 'WDTCR_WDP': '$7', # Watch Dog Timer Prescaler bits + +# Module AD_CONVERTER + 'ADMUX' : '$27', # The ADC multiplexer Selection + 'ADMUX_REFS': '$c0', # Reference Selection Bits + 'ADMUX_ADLAR': '$20', # Left Adjust Result + 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select + 'ADCSRA' : '$26', # The ADC Control and Status reg + 'ADCSRA_ADEN': '$80', # ADC Enable + 'ADCSRA_ADSC': '$40', # ADC Start Conversion + 'ADCSRA_ADFR': '$20', # ADC Free Running Select + 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag + 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable + 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits + 'ADC' : '$24', # ADC Data Register Bytes + + '__amforth_dummy':'0' +} diff --git a/amforth-6.5/avr8/devices/atmega128/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega128/words/no-jtag.asm new file mode 100644 index 0000000..352a4bb --- /dev/null +++ b/amforth-6.5/avr8/devices/atmega128/words/no-jtag.asm @@ -0,0 +1,14 @@ +; ( -- ) +; ( -- ) +; MCU +; disable jtag at runtime +VE_NOJTAG: + .dw $FF05 + .db "-jtag",0 + .dw VE_HEAD + .set VE_HEAD = VE_NOJTAG +XT_NOJTAG: + .dw PFA_NOJTAG +PFA_NOJTAG: + + jmp_ DO_NEXT diff --git a/amforth-6.5/avr8/devices/atmega128/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega128/words/no-wdt.asm new file mode 100644 index 0000000..4a12261 --- /dev/null +++ b/amforth-6.5/avr8/devices/atmega128/words/no-wdt.asm @@ -0,0 +1,22 @@ +; ( -- ) +; MCU +; disable watch dog timer at runtime +VE_NOWDT: + .dw $ff04 + .db "-wdt" + .dw VE_HEAD + .set VE_HEAD = VE_NOWDT +XT_NOWDT: + .dw PFA_NOWDT +PFA_NOWDT: + +; Reset WDT + wdr +; Write logical one to WDTOE and WDE + in_ temp1, WDTCR + ori temp1, (1<