From 67d25d837ac55f28a366c0a3b262e439a6e75fc3 Mon Sep 17 00:00:00 2001 From: Dimitri Sokolyuk Date: Sat, 19 Aug 2017 12:15:28 +0200 Subject: Add AmForth --- amforth-6.5/avr8/devices/atmega162/atmega162.frt | 289 +++++++ amforth-6.5/avr8/devices/atmega162/device.asm | 117 +++ amforth-6.5/avr8/devices/atmega162/device.inc | 924 +++++++++++++++++++++ amforth-6.5/avr8/devices/atmega162/device.py | 332 ++++++++ .../avr8/devices/atmega162/words/no-jtag.asm | 14 + .../avr8/devices/atmega162/words/no-wdt.asm | 22 + amforth-6.5/avr8/devices/atmega162/words/sleep.asm | 24 + 7 files changed, 1722 insertions(+) create mode 100644 amforth-6.5/avr8/devices/atmega162/atmega162.frt create mode 100644 amforth-6.5/avr8/devices/atmega162/device.asm create mode 100644 amforth-6.5/avr8/devices/atmega162/device.inc create mode 100644 amforth-6.5/avr8/devices/atmega162/device.py create mode 100644 amforth-6.5/avr8/devices/atmega162/words/no-jtag.asm create mode 100644 amforth-6.5/avr8/devices/atmega162/words/no-wdt.asm create mode 100644 amforth-6.5/avr8/devices/atmega162/words/sleep.asm (limited to 'amforth-6.5/avr8/devices/atmega162') diff --git a/amforth-6.5/avr8/devices/atmega162/atmega162.frt b/amforth-6.5/avr8/devices/atmega162/atmega162.frt new file mode 100644 index 0000000..e656277 --- /dev/null +++ b/amforth-6.5/avr8/devices/atmega162/atmega162.frt @@ -0,0 +1,289 @@ +\ Partname: ATmega162 +\ generated automatically + +\ TIMER_COUNTER_1 +&89 constant TIMSK \ Timer/Counter Interrupt Mask Register + $80 constant TIMSK_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable + $40 constant TIMSK_OCIE1A \ Timer/Counter1 Output CompareA Match Interrupt Enable + $20 constant TIMSK_OCIE1B \ Timer/Counter1 Output CompareB Match Interrupt Enable + $08 constant TIMSK_TICIE1 \ Timer/Counter1 Input Capture Interrupt Enable +&88 constant TIFR \ Timer/Counter Interrupt Flag register + $80 constant TIFR_TOV1 \ Timer/Counter1 Overflow Flag + $40 constant TIFR_OCF1A \ Output Compare Flag 1A + $20 constant TIFR_OCF1B \ Output Compare Flag 1B + $08 constant TIFR_ICF1 \ Input Capture Flag 1 +&79 constant TCCR1A \ Timer/Counter1 Control Register A + $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits + $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits + $08 constant TCCR1A_FOC1A \ Force Output Compare for Channel A + $04 constant TCCR1A_FOC1B \ Force Output Compare for Channel B + $03 constant TCCR1A_WGM1 \ Pulse Width Modulator Select Bits +&78 constant TCCR1B \ Timer/Counter1 Control Register B + $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler + $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select + $18 constant TCCR1B_WGM1 \ Pulse Width Modulator Select Bits + $07 constant TCCR1B_CS1 \ Clock Select1 bits +&76 constant TCNT1 \ Timer/Counter1 Bytes +&74 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes +&72 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes +&68 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes +\ TIMER_COUNTER_2 +&71 constant TCCR2 \ Timer/Counter Control Register + $80 constant TCCR2_FOC2 \ Forde Output Compare + $40 constant TCCR2_WGM20 \ Pulse Width Modulator Select Bit 0 + $30 constant TCCR2_COM2 \ Compare Match Output Mode + $08 constant TCCR2_WGM21 \ Pulse Width Modulator Select Bit 1 + $07 constant TCCR2_CS2 \ Clock Select +&67 constant TCNT2 \ Timer/Counter Register +&66 constant OCR2 \ Output Compare Register +&70 constant ASSR \ Asynchronous Status Register + $08 constant ASSR_AS2 \ Asynchronous Timer 2 + $04 constant ASSR_TCN2UB \ Timer/Counter2 Update Busy + $02 constant ASSR_OCR2UB \ Output Compare Register2 Update Busy + $01 constant ASSR_TCR2UB \ Timer/Counter Control Register2 Update Busy +\ TIMER_COUNTER_3 +&125 constant ETIMSK \ Extended Timer/Counter Interrupt Mask Register + $20 constant ETIMSK_TICIE3 \ Timer/Counter3 Input Capture Interrupt Enable + $10 constant ETIMSK_OCIE3A \ Timer/Counter3 Output CompareA Match Interrupt Enable + $08 constant ETIMSK_OCIE3B \ Timer/Counter3 Output CompareB Match Interrupt Enable + $04 constant ETIMSK_TOIE3 \ Timer/Counter3 Overflow Interrupt Enable +&124 constant ETIFR \ Extended Timer/Counter Interrupt Flag register + $20 constant ETIFR_ICF3 \ Input Capture Flag 3 + $10 constant ETIFR_OCF3A \ Output Compare Flag 3A + $08 constant ETIFR_OCF3B \ Output Compare Flag 3B + $04 constant ETIFR_TOV3 \ Timer/Counter3 Overflow Flag +&139 constant TCCR3A \ Timer/Counter3 Control Register A + $C0 constant TCCR3A_COM3A \ Compare Output Mode 3A, bits + $30 constant TCCR3A_COM3B \ Compare Output Mode 3B, bits + $08 constant TCCR3A_FOC3A \ Force Output Compare for Channel A + $04 constant TCCR3A_FOC3B \ Force Output Compare for Channel B + $03 constant TCCR3A_WGM3 \ Pulse Width Modulator Select Bits +&138 constant TCCR3B \ Timer/Counter3 Control Register B + $80 constant TCCR3B_ICNC3 \ Input Capture 3 Noise Canceler + $40 constant TCCR3B_ICES3 \ Input Capture 3 Edge Select + $18 constant TCCR3B_WGM3 \ Pulse Width Modulator Select Bits + $07 constant TCCR3B_CS3 \ Clock Select3 bits +&136 constant TCNT3 \ Timer/Counter3 Bytes +&134 constant OCR3A \ Timer/Counter3 Output Compare Register A Bytes +&132 constant OCR3B \ Timer/Counte3 Output Compare Register B Bytes +&128 constant ICR3 \ Timer/Counter3 Input Capture Register Bytes +\ ANALOG_COMPARATOR +&40 constant ACSR \ Analog Comparator Control And Status Register + $80 constant ACSR_ACD \ Analog Comparator Disable + $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select + $20 constant ACSR_ACO \ Analog Compare Output + $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag + $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable + $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable + $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits +\ USART0 +&44 constant UDR0 \ USART I/O Data Register +&43 constant UCSR0A \ USART Control and Status Register A + $80 constant UCSR0A_RXC0 \ USART Receive Complete + $40 constant UCSR0A_TXC0 \ USART Transmitt Complete + $20 constant UCSR0A_UDRE0 \ USART Data Register Empty + $10 constant UCSR0A_FE0 \ Framing Error + $08 constant UCSR0A_DOR0 \ Data overRun + $04 constant UCSR0A_UPE0 \ Parity Error + $02 constant UCSR0A_U2X0 \ Double the USART transmission speed + $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode +&42 constant UCSR0B \ USART Control and Status Register B + $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable + $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable + $20 constant UCSR0B_UDRIE0 \ USART Data register Empty Interrupt Enable + $10 constant UCSR0B_RXEN0 \ Receiver Enable + $08 constant UCSR0B_TXEN0 \ Transmitter Enable + $04 constant UCSR0B_UCSZ02 \ Character Size + $02 constant UCSR0B_RXB80 \ Receive Data Bit 8 + $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8 +&64 constant UCSR0C \ USART Control and Status Register C + $80 constant UCSR0C_URSEL0 \ Register Select + $40 constant UCSR0C_UMSEL0 \ USART Mode Select + $30 constant UCSR0C_UPM0 \ Parity Mode Bits + $08 constant UCSR0C_USBS0 \ Stop Bit Select + $06 constant UCSR0C_UCSZ0 \ Character Size + $01 constant UCSR0C_UCPOL0 \ Clock Polarity +&64 constant UBRR0H \ USART Baud Rate Register Hight Byte +&41 constant UBRR0L \ USART Baud Rate Register Low Byte +\ USART1 +&35 constant UDR \ USART I/O Data Register +&34 constant UCSR1A \ USART Control and Status Register A + $80 constant UCSR1A_RXC1 \ USART Receive Complete + $40 constant UCSR1A_TXC1 \ USART Transmitt Complete + $20 constant UCSR1A_UDRE1 \ USART Data Register Empty + $10 constant UCSR1A_FE1 \ Framing Error + $08 constant UCSR1A_DOR1 \ Data overRun + $04 constant UCSR1A_UPE1 \ Parity Error + $02 constant UCSR1A_U2X1 \ Double the USART transmission speed + $01 constant UCSR1A_MPCM1 \ Multi-processor Communication Mode +&33 constant UCSR1B \ USART Control and Status Register B + $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable + $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable + $20 constant UCSR1B_UDRIE1 \ USART Data register Empty Interrupt Enable + $10 constant UCSR1B_RXEN1 \ Receiver Enable + $08 constant UCSR1B_TXEN1 \ Transmitter Enable + $04 constant UCSR1B_UCSZ12 \ Character Size + $02 constant UCSR1B_RXB81 \ Receive Data Bit 8 + $01 constant UCSR1B_TXB81 \ Transmit Data Bit 8 +&92 constant UCSR1C \ USART Control and Status Register C + $80 constant UCSR1C_URSEL1 \ Register Select + $40 constant UCSR1C_UMSEL1 \ USART Mode Select + $30 constant UCSR1C_UPM1 \ Parity Mode Bits + $08 constant UCSR1C_USBS1 \ Stop Bit Select + $06 constant UCSR1C_UCSZ1 \ Character Size + $01 constant UCSR1C_UCPOL1 \ Clock Polarity +&92 constant UBRR1H \ USART Baud Rate Register Highg Byte +&32 constant UBRR1L \ USART Baud Rate Register Low Byte +\ SPI +&45 constant SPCR \ SPI Control Register + $80 constant SPCR_SPIE \ SPI Interrupt Enable + $40 constant SPCR_SPE \ SPI Enable + $20 constant SPCR_DORD \ Data Order + $10 constant SPCR_MSTR \ Master/Slave Select + $08 constant SPCR_CPOL \ Clock polarity + $04 constant SPCR_CPHA \ Clock Phase + $03 constant SPCR_SPR \ SPI Clock Rate Selects +&46 constant SPSR \ SPI Status Register + $80 constant SPSR_SPIF \ SPI Interrupt Flag + $40 constant SPSR_WCOL \ Write Collision Flag + $01 constant SPSR_SPI2X \ Double SPI Speed Bit +&47 constant SPDR \ SPI Data Register +\ CPU +&95 constant SREG \ Status Register + $80 constant SREG_I \ Global Interrupt Enable + $40 constant SREG_T \ Bit Copy Storage + $20 constant SREG_H \ Half Carry Flag + $10 constant SREG_S \ Sign Bit + $08 constant SREG_V \ Two's Complement Overflow Flag + $04 constant SREG_N \ Negative Flag + $02 constant SREG_Z \ Zero Flag + $01 constant SREG_C \ Carry Flag +&93 constant SP \ Stack Pointer +&85 constant MCUCR \ MCU Control Register + $80 constant MCUCR_SRE \ External SRAM Enable + $40 constant MCUCR_SRW10 \ External SRAM Wait State Select + $20 constant MCUCR_SE \ Sleep Enable + $10 constant MCUCR_SM1 \ Sleep Mode Select + $0C constant MCUCR_ISC1 \ Interrupt Sense Control 1 bits + $03 constant MCUCR_ISC0 \ Interrupt Sense Control 0 bits +&84 constant MCUCSR \ MCU Control And Status Register + $80 constant MCUCSR_JDT \ JTAG Interface Disable + $20 constant MCUCSR_SM2 \ Sleep Mode Select Bit 2 + $10 constant MCUCSR_JTRF \ JTAG Reset Flag + $08 constant MCUCSR_WDRF \ Watchdog Reset Flag + $04 constant MCUCSR_BORF \ Brown-out Reset Flag + $02 constant MCUCSR_EXTRF \ External Reset Flag + $01 constant MCUCSR_PORF \ Power-on reset flag +&86 constant EMCUCR \ Extended MCU Control Register + $80 constant EMCUCR_SM0 \ Sleep mode Select Bit 0 + $70 constant EMCUCR_SRL \ Wait State Sector Limit Bits + $0C constant EMCUCR_SRW0 \ Wait State Select Bit 1 for Lower Sector + $02 constant EMCUCR_SRW11 \ Wait State Select Bit 1 for Upper Sector + $01 constant EMCUCR_ISC2 \ Interrupt Sense Control 2 +&36 constant OSCCAL \ Oscillator Calibration Value +&97 constant CLKPR \ Clock prescale register + $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable + $0F constant CLKPR_CLKPS \ Clock Prescaler Select Bits +&80 constant SFIOR \ Special Function IO Register + $80 constant SFIOR_TSM \ Timer/Counter Synchronization Mode + $40 constant SFIOR_XMBK \ External Memory Bus Keeper Enable + $38 constant SFIOR_XMM \ External Memory High Mask Bits + $04 constant SFIOR_PUD \ Pull-up Disable + $02 constant SFIOR_PSR2 \ Prescaler Reset Timer/Counter2 + $01 constant SFIOR_PSR310 \ Prescaler Reset Timer/Counter3, Timer/Counter1 and Timer/Counter0 +\ JTAG +&36 constant OCDR \ On-Chip Debug Related Register in I/O Memory + $FF constant OCDR_OCDR \ On-Chip Debug Register Bits +\ BOOT_LOAD +&87 constant SPMCR \ Store Program Memory Control Register + $80 constant SPMCR_SPMIE \ SPM Interrupt Enable + $40 constant SPMCR_RWWSB \ Read While Write Section Busy + $10 constant SPMCR_RWWSRE \ Read While Write secion read enable + $08 constant SPMCR_BLBSET \ Boot Lock Bit Set + $04 constant SPMCR_PGWRT \ Page Write + $02 constant SPMCR_PGERS \ Page Erase + $01 constant SPMCR_SPMEN \ Store Program Memory Enable +\ EEPROM +&62 constant EEAR \ EEPROM Address Register Bytes +&61 constant EEDR \ EEPROM Data Register +&60 constant EECR \ EEPROM Control Register + $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable + $04 constant EECR_EEMWE \ EEPROM Master Write Enable + $02 constant EECR_EEWE \ EEPROM Write Enable + $01 constant EECR_EERE \ EEPROM Read Enable +\ PORTA +&59 constant PORTA \ Port A Data Register +&58 constant DDRA \ Port A Data Direction Register +&57 constant PINA \ Port A Input Pins +\ PORTB +&56 constant PORTB \ Port B Data Register +&55 constant DDRB \ Port B Data Direction Register +&54 constant PINB \ Port B Input Pins +\ PORTC +&53 constant PORTC \ Port C Data Register +&52 constant DDRC \ Port C Data Direction Register +&51 constant PINC \ Port C Input Pins +\ PORTD +&50 constant PORTD \ Port D Data Register +&49 constant DDRD \ Port D Data Direction Register +&48 constant PIND \ Port D Input Pins +\ TIMER_COUNTER_0 +&83 constant TCCR0 \ Timer/Counter 0 Control Register + $80 constant TCCR0_FOC0 \ Force Output Compare + $40 constant TCCR0_WGM00 \ Waveform Generation Mode 0 + $30 constant TCCR0_COM0 \ Compare Match Output Modes + $08 constant TCCR0_WGM01 \ Waveform Generation Mode 1 + $07 constant TCCR0_CS0 \ Clock Selects +&82 constant TCNT0 \ Timer/Counter 0 Register +&81 constant OCR0 \ Timer/Counter 0 Output Compare Register +\ WATCHDOG +&65 constant WDTCR \ Watchdog Timer Control Register + $10 constant WDTCR_WDCE \ Watchdog Change Enable + $08 constant WDTCR_WDE \ Watch Dog Enable + $07 constant WDTCR_WDP \ Watch Dog Timer Prescaler bits +\ PORTE +&39 constant PORTE \ Data Register, Port E +&38 constant DDRE \ Data Direction Register, Port E +&37 constant PINE \ Input Pins, Port E +\ EXTERNAL_INTERRUPT +&91 constant GICR \ General Interrupt Control Register + $C0 constant GICR_INT \ External Interrupt Request 1 Enable + $20 constant GICR_INT2 \ External Interrupt Request 2 Enable + $18 constant GICR_PCIE \ Pin Change Interrupt Enables + $02 constant GICR_IVSEL \ Interrupt Vector Select + $01 constant GICR_IVCE \ Interrupt Vector Change Enable +&90 constant GIFR \ General Interrupt Flag Register + $C0 constant GIFR_INTF \ External Interrupt Flags + $20 constant GIFR_INTF2 \ External Interrupt Flag 2 + $18 constant GIFR_PCIF \ Pin Change Interrupt Flags +&108 constant PCMSK1 \ Pin Change Mask Register 1 +&107 constant PCMSK0 \ Pin Change Enable Mask + +\ Interrupts +&2 constant INT0Addr \ External Interrupt Request 0 +&4 constant INT1Addr \ External Interrupt Request 1 +&6 constant INT2Addr \ External Interrupt Request 2 +&8 constant PCINT0Addr \ Pin Change Interrupt Request 0 +&10 constant PCINT1Addr \ Pin Change Interrupt Request 1 +&12 constant TIMER3_CAPTAddr \ Timer/Counter3 Capture Event +&14 constant TIMER3_COMPAAddr \ Timer/Counter3 Compare Match A +&16 constant TIMER3_COMPBAddr \ Timer/Counter3 Compare Match B +&18 constant TIMER3_OVFAddr \ Timer/Counter3 Overflow +&20 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match +&22 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow +&24 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event +&26 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A +&28 constant TIMER1_COMPBAddr \ Timer/Counter Compare Match B +&30 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow +&32 constant TIMER0_COMPAddr \ Timer/Counter0 Compare Match +&34 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow +&36 constant SPI__STCAddr \ SPI Serial Transfer Complete +&38 constant USART0__RXCAddr \ USART0, Rx Complete +&40 constant USART1__RXCAddr \ USART1, Rx Complete +&42 constant USART0__UDREAddr \ USART0 Data register Empty +&44 constant USART1__UDREAddr \ USART1, Data register Empty +&46 constant USART0__TXCAddr \ USART0, Tx Complete +&48 constant USART1__TXCAddr \ USART1, Tx Complete +&50 constant EE_RDYAddr \ EEPROM Ready +&52 constant ANA_COMPAddr \ Analog Comparator +&54 constant SPM_RDYAddr \ Store Program Memory Read diff --git a/amforth-6.5/avr8/devices/atmega162/device.asm b/amforth-6.5/avr8/devices/atmega162/device.asm new file mode 100644 index 0000000..b61f439 --- /dev/null +++ b/amforth-6.5/avr8/devices/atmega162/device.asm @@ -0,0 +1,117 @@ +; Partname: ATmega162 +; generated automatically, do not edit + +.nolist + .include "m162def.inc" +.list + +.equ ramstart = 256 +.equ CELLSIZE = 2 +.macro readflashcell + lsl zl + rol zh + lpm @0, Z+ + lpm @1, Z+ +.endmacro +.macro writeflashcell + lsl zl + rol zh +.endmacro +.set WANT_TIMER_COUNTER_1 = 0 +.set WANT_TIMER_COUNTER_2 = 0 +.set WANT_TIMER_COUNTER_3 = 0 +.set WANT_ANALOG_COMPARATOR = 0 +.set WANT_USART0 = 0 +.set WANT_USART1 = 0 +.set WANT_SPI = 0 +.set WANT_CPU = 0 +.set WANT_JTAG = 0 +.set WANT_BOOT_LOAD = 0 +.set WANT_EEPROM = 0 +.set WANT_PORTA = 0 +.set WANT_PORTB = 0 +.set WANT_PORTC = 0 +.set WANT_PORTD = 0 +.set WANT_TIMER_COUNTER_0 = 0 +.set WANT_WATCHDOG = 0 +.set WANT_PORTE = 0 +.set WANT_EXTERNAL_INTERRUPT = 0 +.equ intvecsize = 2 ; please verify; flash size: 16384 bytes +.equ pclen = 2 ; please verify +.overlap +.org 2 + rcall isr ; External Interrupt Request 0 +.org 4 + rcall isr ; External Interrupt Request 1 +.org 6 + rcall isr ; External Interrupt Request 2 +.org 8 + rcall isr ; Pin Change Interrupt Request 0 +.org 10 + rcall isr ; Pin Change Interrupt Request 1 +.org 12 + rcall isr ; Timer/Counter3 Capture Event +.org 14 + rcall isr ; Timer/Counter3 Compare Match A +.org 16 + rcall isr ; Timer/Counter3 Compare Match B +.org 18 + rcall isr ; Timer/Counter3 Overflow +.org 20 + rcall isr ; Timer/Counter2 Compare Match +.org 22 + rcall isr ; Timer/Counter2 Overflow +.org 24 + rcall isr ; Timer/Counter1 Capture Event +.org 26 + rcall isr ; Timer/Counter1 Compare Match A +.org 28 + rcall isr ; Timer/Counter Compare Match B +.org 30 + rcall isr ; Timer/Counter1 Overflow +.org 32 + rcall isr ; Timer/Counter0 Compare Match +.org 34 + rcall isr ; Timer/Counter0 Overflow +.org 36 + rcall isr ; SPI Serial Transfer Complete +.org 38 + rcall isr ; USART0, Rx Complete +.org 40 + rcall isr ; USART1, Rx Complete +.org 42 + rcall isr ; USART0 Data register Empty +.org 44 + rcall isr ; USART1, Data register Empty +.org 46 + rcall isr ; USART0, Tx Complete +.org 48 + rcall isr ; USART1, Tx Complete +.org 50 + rcall isr ; EEPROM Ready +.org 52 + rcall isr ; Analog Comparator +.org 54 + rcall isr ; Store Program Memory Read +.equ INTVECTORS = 28 +.nooverlap + +; compatability layer (maybe empty) +.equ SPMCSR = SPMCR +.equ EEPE = EEWE +.equ EEMPE = EEMWE + +; controller data area, environment query mcu-info +mcu_info: +mcu_ramsize: + .dw 1024 +mcu_eepromsize: + .dw 512 +mcu_maxdp: + .dw 14336 +mcu_numints: + .dw 28 +mcu_name: + .dw 9 + .db "ATmega162",0 +.set codestart=pc diff --git a/amforth-6.5/avr8/devices/atmega162/device.inc b/amforth-6.5/avr8/devices/atmega162/device.inc new file mode 100644 index 0000000..8d0e695 --- /dev/null +++ b/amforth-6.5/avr8/devices/atmega162/device.inc @@ -0,0 +1,924 @@ +; Partname: ATmega162 +; generated automatically, no not edit + +.if WANT_TIMER_COUNTER_1 == 1 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter Interrupt Mask Register +VE_TIMSK: + .dw $ff05 + .db "TIMSK",0 + .dw VE_HEAD + .set VE_HEAD=VE_TIMSK +XT_TIMSK: + .dw PFA_DOVARIABLE +PFA_TIMSK: + .dw 89 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter Interrupt Flag register +VE_TIFR: + .dw $ff04 + .db "TIFR" + .dw VE_HEAD + .set VE_HEAD=VE_TIFR +XT_TIFR: + .dw PFA_DOVARIABLE +PFA_TIFR: + .dw 88 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter1 Control Register A +VE_TCCR1A: + .dw $ff06 + .db "TCCR1A" + .dw VE_HEAD + .set VE_HEAD=VE_TCCR1A +XT_TCCR1A: + .dw PFA_DOVARIABLE +PFA_TCCR1A: + .dw 79 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter1 Control Register B +VE_TCCR1B: + .dw $ff06 + .db "TCCR1B" + .dw VE_HEAD + .set VE_HEAD=VE_TCCR1B +XT_TCCR1B: + .dw PFA_DOVARIABLE +PFA_TCCR1B: + .dw 78 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter1 Bytes +VE_TCNT1: + .dw $ff05 + .db "TCNT1",0 + .dw VE_HEAD + .set VE_HEAD=VE_TCNT1 +XT_TCNT1: + .dw PFA_DOVARIABLE +PFA_TCNT1: + .dw 76 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter1 Output Compare Register A Bytes +VE_OCR1A: + .dw $ff05 + .db "OCR1A",0 + .dw VE_HEAD + .set VE_HEAD=VE_OCR1A +XT_OCR1A: + .dw PFA_DOVARIABLE +PFA_OCR1A: + .dw 74 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter1 Output Compare Register B Bytes +VE_OCR1B: + .dw $ff05 + .db "OCR1B",0 + .dw VE_HEAD + .set VE_HEAD=VE_OCR1B +XT_OCR1B: + .dw PFA_DOVARIABLE +PFA_OCR1B: + .dw 72 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter1 Input Capture Register Bytes +VE_ICR1: + .dw $ff04 + .db "ICR1" + .dw VE_HEAD + .set VE_HEAD=VE_ICR1 +XT_ICR1: + .dw PFA_DOVARIABLE +PFA_ICR1: + .dw 68 + +.endif +.if WANT_TIMER_COUNTER_2 == 1 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter Control Register +VE_TCCR2: + .dw $ff05 + .db "TCCR2",0 + .dw VE_HEAD + .set VE_HEAD=VE_TCCR2 +XT_TCCR2: + .dw PFA_DOVARIABLE +PFA_TCCR2: + .dw 71 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter Register +VE_TCNT2: + .dw $ff05 + .db "TCNT2",0 + .dw VE_HEAD + .set VE_HEAD=VE_TCNT2 +XT_TCNT2: + .dw PFA_DOVARIABLE +PFA_TCNT2: + .dw 67 +; ( -- addr ) System Constant +; R( -- ) +; Output Compare Register +VE_OCR2: + .dw $ff04 + .db "OCR2" + .dw VE_HEAD + .set VE_HEAD=VE_OCR2 +XT_OCR2: + .dw PFA_DOVARIABLE +PFA_OCR2: + .dw 66 +; ( -- addr ) System Constant +; R( -- ) +; Asynchronous Status Register +VE_ASSR: + .dw $ff04 + .db "ASSR" + .dw VE_HEAD + .set VE_HEAD=VE_ASSR +XT_ASSR: + .dw PFA_DOVARIABLE +PFA_ASSR: + .dw 70 + +.endif +.if WANT_TIMER_COUNTER_3 == 1 +; ( -- addr ) System Constant +; R( -- ) +; Extended Timer/Counter Interrupt Mask Register +VE_ETIMSK: + .dw $ff06 + .db "ETIMSK" + .dw VE_HEAD + .set VE_HEAD=VE_ETIMSK +XT_ETIMSK: + .dw PFA_DOVARIABLE +PFA_ETIMSK: + .dw 125 +; ( -- addr ) System Constant +; R( -- ) +; Extended Timer/Counter Interrupt Flag register +VE_ETIFR: + .dw $ff05 + .db "ETIFR",0 + .dw VE_HEAD + .set VE_HEAD=VE_ETIFR +XT_ETIFR: + .dw PFA_DOVARIABLE +PFA_ETIFR: + .dw 124 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter3 Control Register A +VE_TCCR3A: + .dw $ff06 + .db "TCCR3A" + .dw VE_HEAD + .set VE_HEAD=VE_TCCR3A +XT_TCCR3A: + .dw PFA_DOVARIABLE +PFA_TCCR3A: + .dw 139 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter3 Control Register B +VE_TCCR3B: + .dw $ff06 + .db "TCCR3B" + .dw VE_HEAD + .set VE_HEAD=VE_TCCR3B +XT_TCCR3B: + .dw PFA_DOVARIABLE +PFA_TCCR3B: + .dw 138 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter3 Bytes +VE_TCNT3: + .dw $ff05 + .db "TCNT3",0 + .dw VE_HEAD + .set VE_HEAD=VE_TCNT3 +XT_TCNT3: + .dw PFA_DOVARIABLE +PFA_TCNT3: + .dw 136 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter3 Output Compare Register A Bytes +VE_OCR3A: + .dw $ff05 + .db "OCR3A",0 + .dw VE_HEAD + .set VE_HEAD=VE_OCR3A +XT_OCR3A: + .dw PFA_DOVARIABLE +PFA_OCR3A: + .dw 134 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counte3 Output Compare Register B Bytes +VE_OCR3B: + .dw $ff05 + .db "OCR3B",0 + .dw VE_HEAD + .set VE_HEAD=VE_OCR3B +XT_OCR3B: + .dw PFA_DOVARIABLE +PFA_OCR3B: + .dw 132 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter3 Input Capture Register Bytes +VE_ICR3: + .dw $ff04 + .db "ICR3" + .dw VE_HEAD + .set VE_HEAD=VE_ICR3 +XT_ICR3: + .dw PFA_DOVARIABLE +PFA_ICR3: + .dw 128 + +.endif +.if WANT_ANALOG_COMPARATOR == 1 +; ( -- addr ) System Constant +; R( -- ) +; Analog Comparator Control And Status Register +VE_ACSR: + .dw $ff04 + .db "ACSR" + .dw VE_HEAD + .set VE_HEAD=VE_ACSR +XT_ACSR: + .dw PFA_DOVARIABLE +PFA_ACSR: + .dw 40 + +.endif +.if WANT_USART0 == 1 +; ( -- addr ) System Constant +; R( -- ) +; USART I/O Data Register +VE_UDR0: + .dw $ff04 + .db "UDR0" + .dw VE_HEAD + .set VE_HEAD=VE_UDR0 +XT_UDR0: + .dw PFA_DOVARIABLE +PFA_UDR0: + .dw 44 +; ( -- addr ) System Constant +; R( -- ) +; USART Control and Status Register A +VE_UCSR0A: + .dw $ff06 + .db "UCSR0A" + .dw VE_HEAD + .set VE_HEAD=VE_UCSR0A +XT_UCSR0A: + .dw PFA_DOVARIABLE +PFA_UCSR0A: + .dw 43 +; ( -- addr ) System Constant +; R( -- ) +; USART Control and Status Register B +VE_UCSR0B: + .dw $ff06 + .db "UCSR0B" + .dw VE_HEAD + .set VE_HEAD=VE_UCSR0B +XT_UCSR0B: + .dw PFA_DOVARIABLE +PFA_UCSR0B: + .dw 42 +; ( -- addr ) System Constant +; R( -- ) +; USART Control and Status Register C +VE_UCSR0C: + .dw $ff06 + .db "UCSR0C" + .dw VE_HEAD + .set VE_HEAD=VE_UCSR0C +XT_UCSR0C: + .dw PFA_DOVARIABLE +PFA_UCSR0C: + .dw 64 +; ( -- addr ) System Constant +; R( -- ) +; USART Baud Rate Register Hight Byte +VE_UBRR0H: + .dw $ff06 + .db "UBRR0H" + .dw VE_HEAD + .set VE_HEAD=VE_UBRR0H +XT_UBRR0H: + .dw PFA_DOVARIABLE +PFA_UBRR0H: + .dw 64 +; ( -- addr ) System Constant +; R( -- ) +; USART Baud Rate Register Low Byte +VE_UBRR0L: + .dw $ff06 + .db "UBRR0L" + .dw VE_HEAD + .set VE_HEAD=VE_UBRR0L +XT_UBRR0L: + .dw PFA_DOVARIABLE +PFA_UBRR0L: + .dw 41 + +.endif +.if WANT_USART1 == 1 +; ( -- addr ) System Constant +; R( -- ) +; USART I/O Data Register +VE_UDR: + .dw $ff03 + .db "UDR",0 + .dw VE_HEAD + .set VE_HEAD=VE_UDR +XT_UDR: + .dw PFA_DOVARIABLE +PFA_UDR: + .dw 35 +; ( -- addr ) System Constant +; R( -- ) +; USART Control and Status Register A +VE_UCSR1A: + .dw $ff06 + .db "UCSR1A" + .dw VE_HEAD + .set VE_HEAD=VE_UCSR1A +XT_UCSR1A: + .dw PFA_DOVARIABLE +PFA_UCSR1A: + .dw 34 +; ( -- addr ) System Constant +; R( -- ) +; USART Control and Status Register B +VE_UCSR1B: + .dw $ff06 + .db "UCSR1B" + .dw VE_HEAD + .set VE_HEAD=VE_UCSR1B +XT_UCSR1B: + .dw PFA_DOVARIABLE +PFA_UCSR1B: + .dw 33 +; ( -- addr ) System Constant +; R( -- ) +; USART Control and Status Register C +VE_UCSR1C: + .dw $ff06 + .db "UCSR1C" + .dw VE_HEAD + .set VE_HEAD=VE_UCSR1C +XT_UCSR1C: + .dw PFA_DOVARIABLE +PFA_UCSR1C: + .dw 92 +; ( -- addr ) System Constant +; R( -- ) +; USART Baud Rate Register Highg Byte +VE_UBRR1H: + .dw $ff06 + .db "UBRR1H" + .dw VE_HEAD + .set VE_HEAD=VE_UBRR1H +XT_UBRR1H: + .dw PFA_DOVARIABLE +PFA_UBRR1H: + .dw 92 +; ( -- addr ) System Constant +; R( -- ) +; USART Baud Rate Register Low Byte +VE_UBRR1L: + .dw $ff06 + .db "UBRR1L" + .dw VE_HEAD + .set VE_HEAD=VE_UBRR1L +XT_UBRR1L: + .dw PFA_DOVARIABLE +PFA_UBRR1L: + .dw 32 + +.endif +.if WANT_SPI == 1 +; ( -- addr ) System Constant +; R( -- ) +; SPI Control Register +VE_SPCR: + .dw $ff04 + .db "SPCR" + .dw VE_HEAD + .set VE_HEAD=VE_SPCR +XT_SPCR: + .dw PFA_DOVARIABLE +PFA_SPCR: + .dw 45 +; ( -- addr ) System Constant +; R( -- ) +; SPI Status Register +VE_SPSR: + .dw $ff04 + .db "SPSR" + .dw VE_HEAD + .set VE_HEAD=VE_SPSR +XT_SPSR: + .dw PFA_DOVARIABLE +PFA_SPSR: + .dw 46 +; ( -- addr ) System Constant +; R( -- ) +; SPI Data Register +VE_SPDR: + .dw $ff04 + .db "SPDR" + .dw VE_HEAD + .set VE_HEAD=VE_SPDR +XT_SPDR: + .dw PFA_DOVARIABLE +PFA_SPDR: + .dw 47 + +.endif +.if WANT_CPU == 1 +; ( -- addr ) System Constant +; R( -- ) +; Status Register +VE_SREG: + .dw $ff04 + .db "SREG" + .dw VE_HEAD + .set VE_HEAD=VE_SREG +XT_SREG: + .dw PFA_DOVARIABLE +PFA_SREG: + .dw 95 +; ( -- addr ) System Constant +; R( -- ) +; Stack Pointer +VE_SP: + .dw $ff02 + .db "SP" + .dw VE_HEAD + .set VE_HEAD=VE_SP +XT_SP: + .dw PFA_DOVARIABLE +PFA_SP: + .dw 93 +; ( -- addr ) System Constant +; R( -- ) +; MCU Control Register +VE_MCUCR: + .dw $ff05 + .db "MCUCR",0 + .dw VE_HEAD + .set VE_HEAD=VE_MCUCR +XT_MCUCR: + .dw PFA_DOVARIABLE +PFA_MCUCR: + .dw 85 +; ( -- addr ) System Constant +; R( -- ) +; MCU Control And Status Register +VE_MCUCSR: + .dw $ff06 + .db "MCUCSR" + .dw VE_HEAD + .set VE_HEAD=VE_MCUCSR +XT_MCUCSR: + .dw PFA_DOVARIABLE +PFA_MCUCSR: + .dw 84 +; ( -- addr ) System Constant +; R( -- ) +; Extended MCU Control Register +VE_EMCUCR: + .dw $ff06 + .db "EMCUCR" + .dw VE_HEAD + .set VE_HEAD=VE_EMCUCR +XT_EMCUCR: + .dw PFA_DOVARIABLE +PFA_EMCUCR: + .dw 86 +; ( -- addr ) System Constant +; R( -- ) +; Oscillator Calibration Value +VE_OSCCAL: + .dw $ff06 + .db "OSCCAL" + .dw VE_HEAD + .set VE_HEAD=VE_OSCCAL +XT_OSCCAL: + .dw PFA_DOVARIABLE +PFA_OSCCAL: + .dw 36 +; ( -- addr ) System Constant +; R( -- ) +; Clock prescale register +VE_CLKPR: + .dw $ff05 + .db "CLKPR",0 + .dw VE_HEAD + .set VE_HEAD=VE_CLKPR +XT_CLKPR: + .dw PFA_DOVARIABLE +PFA_CLKPR: + .dw 97 +; ( -- addr ) System Constant +; R( -- ) +; Special Function IO Register +VE_SFIOR: + .dw $ff05 + .db "SFIOR",0 + .dw VE_HEAD + .set VE_HEAD=VE_SFIOR +XT_SFIOR: + .dw PFA_DOVARIABLE +PFA_SFIOR: + .dw 80 + +.endif +.if WANT_JTAG == 1 +; ( -- addr ) System Constant +; R( -- ) +; On-Chip Debug Related Register in I/O Memory +VE_OCDR: + .dw $ff04 + .db "OCDR" + .dw VE_HEAD + .set VE_HEAD=VE_OCDR +XT_OCDR: + .dw PFA_DOVARIABLE +PFA_OCDR: + .dw 36 + +.endif +.if WANT_BOOT_LOAD == 1 +; ( -- addr ) System Constant +; R( -- ) +; Store Program Memory Control Register +VE_SPMCR: + .dw $ff05 + .db "SPMCR",0 + .dw VE_HEAD + .set VE_HEAD=VE_SPMCR +XT_SPMCR: + .dw PFA_DOVARIABLE +PFA_SPMCR: + .dw 87 + +.endif +.if WANT_EEPROM == 1 +; ( -- addr ) System Constant +; R( -- ) +; EEPROM Address Register Bytes +VE_EEAR: + .dw $ff04 + .db "EEAR" + .dw VE_HEAD + .set VE_HEAD=VE_EEAR +XT_EEAR: + .dw PFA_DOVARIABLE +PFA_EEAR: + .dw 62 +; ( -- addr ) System Constant +; R( -- ) +; EEPROM Data Register +VE_EEDR: + .dw $ff04 + .db "EEDR" + .dw VE_HEAD + .set VE_HEAD=VE_EEDR +XT_EEDR: + .dw PFA_DOVARIABLE +PFA_EEDR: + .dw 61 +; ( -- addr ) System Constant +; R( -- ) +; EEPROM Control Register +VE_EECR: + .dw $ff04 + .db "EECR" + .dw VE_HEAD + .set VE_HEAD=VE_EECR +XT_EECR: + .dw PFA_DOVARIABLE +PFA_EECR: + .dw 60 + +.endif +.if WANT_PORTA == 1 +; ( -- addr ) System Constant +; R( -- ) +; Port A Data Register +VE_PORTA: + .dw $ff05 + .db "PORTA",0 + .dw VE_HEAD + .set VE_HEAD=VE_PORTA +XT_PORTA: + .dw PFA_DOVARIABLE +PFA_PORTA: + .dw 59 +; ( -- addr ) System Constant +; R( -- ) +; Port A Data Direction Register +VE_DDRA: + .dw $ff04 + .db "DDRA" + .dw VE_HEAD + .set VE_HEAD=VE_DDRA +XT_DDRA: + .dw PFA_DOVARIABLE +PFA_DDRA: + .dw 58 +; ( -- addr ) System Constant +; R( -- ) +; Port A Input Pins +VE_PINA: + .dw $ff04 + .db "PINA" + .dw VE_HEAD + .set VE_HEAD=VE_PINA +XT_PINA: + .dw PFA_DOVARIABLE +PFA_PINA: + .dw 57 + +.endif +.if WANT_PORTB == 1 +; ( -- addr ) System Constant +; R( -- ) +; Port B Data Register +VE_PORTB: + .dw $ff05 + .db "PORTB",0 + .dw VE_HEAD + .set VE_HEAD=VE_PORTB +XT_PORTB: + .dw PFA_DOVARIABLE +PFA_PORTB: + .dw 56 +; ( -- addr ) System Constant +; R( -- ) +; Port B Data Direction Register +VE_DDRB: + .dw $ff04 + .db "DDRB" + .dw VE_HEAD + .set VE_HEAD=VE_DDRB +XT_DDRB: + .dw PFA_DOVARIABLE +PFA_DDRB: + .dw 55 +; ( -- addr ) System Constant +; R( -- ) +; Port B Input Pins +VE_PINB: + .dw $ff04 + .db "PINB" + .dw VE_HEAD + .set VE_HEAD=VE_PINB +XT_PINB: + .dw PFA_DOVARIABLE +PFA_PINB: + .dw 54 + +.endif +.if WANT_PORTC == 1 +; ( -- addr ) System Constant +; R( -- ) +; Port C Data Register +VE_PORTC: + .dw $ff05 + .db "PORTC",0 + .dw VE_HEAD + .set VE_HEAD=VE_PORTC +XT_PORTC: + .dw PFA_DOVARIABLE +PFA_PORTC: + .dw 53 +; ( -- addr ) System Constant +; R( -- ) +; Port C Data Direction Register +VE_DDRC: + .dw $ff04 + .db "DDRC" + .dw VE_HEAD + .set VE_HEAD=VE_DDRC +XT_DDRC: + .dw PFA_DOVARIABLE +PFA_DDRC: + .dw 52 +; ( -- addr ) System Constant +; R( -- ) +; Port C Input Pins +VE_PINC: + .dw $ff04 + .db "PINC" + .dw VE_HEAD + .set VE_HEAD=VE_PINC +XT_PINC: + .dw PFA_DOVARIABLE +PFA_PINC: + .dw 51 + +.endif +.if WANT_PORTD == 1 +; ( -- addr ) System Constant +; R( -- ) +; Port D Data Register +VE_PORTD: + .dw $ff05 + .db "PORTD",0 + .dw VE_HEAD + .set VE_HEAD=VE_PORTD +XT_PORTD: + .dw PFA_DOVARIABLE +PFA_PORTD: + .dw 50 +; ( -- addr ) System Constant +; R( -- ) +; Port D Data Direction Register +VE_DDRD: + .dw $ff04 + .db "DDRD" + .dw VE_HEAD + .set VE_HEAD=VE_DDRD +XT_DDRD: + .dw PFA_DOVARIABLE +PFA_DDRD: + .dw 49 +; ( -- addr ) System Constant +; R( -- ) +; Port D Input Pins +VE_PIND: + .dw $ff04 + .db "PIND" + .dw VE_HEAD + .set VE_HEAD=VE_PIND +XT_PIND: + .dw PFA_DOVARIABLE +PFA_PIND: + .dw 48 + +.endif +.if WANT_TIMER_COUNTER_0 == 1 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter 0 Control Register +VE_TCCR0: + .dw $ff05 + .db "TCCR0",0 + .dw VE_HEAD + .set VE_HEAD=VE_TCCR0 +XT_TCCR0: + .dw PFA_DOVARIABLE +PFA_TCCR0: + .dw 83 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter 0 Register +VE_TCNT0: + .dw $ff05 + .db "TCNT0",0 + .dw VE_HEAD + .set VE_HEAD=VE_TCNT0 +XT_TCNT0: + .dw PFA_DOVARIABLE +PFA_TCNT0: + .dw 82 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter 0 Output Compare Register +VE_OCR0: + .dw $ff04 + .db "OCR0" + .dw VE_HEAD + .set VE_HEAD=VE_OCR0 +XT_OCR0: + .dw PFA_DOVARIABLE +PFA_OCR0: + .dw 81 + +.endif +.if WANT_WATCHDOG == 1 +; ( -- addr ) System Constant +; R( -- ) +; Watchdog Timer Control Register +VE_WDTCR: + .dw $ff05 + .db "WDTCR",0 + .dw VE_HEAD + .set VE_HEAD=VE_WDTCR +XT_WDTCR: + .dw PFA_DOVARIABLE +PFA_WDTCR: + .dw 65 + +.endif +.if WANT_PORTE == 1 +; ( -- addr ) System Constant +; R( -- ) +; Data Register, Port E +VE_PORTE: + .dw $ff05 + .db "PORTE",0 + .dw VE_HEAD + .set VE_HEAD=VE_PORTE +XT_PORTE: + .dw PFA_DOVARIABLE +PFA_PORTE: + .dw 39 +; ( -- addr ) System Constant +; R( -- ) +; Data Direction Register, Port E +VE_DDRE: + .dw $ff04 + .db "DDRE" + .dw VE_HEAD + .set VE_HEAD=VE_DDRE +XT_DDRE: + .dw PFA_DOVARIABLE +PFA_DDRE: + .dw 38 +; ( -- addr ) System Constant +; R( -- ) +; Input Pins, Port E +VE_PINE: + .dw $ff04 + .db "PINE" + .dw VE_HEAD + .set VE_HEAD=VE_PINE +XT_PINE: + .dw PFA_DOVARIABLE +PFA_PINE: + .dw 37 + +.endif +.if WANT_EXTERNAL_INTERRUPT == 1 +; ( -- addr ) System Constant +; R( -- ) +; General Interrupt Control Register +VE_GICR: + .dw $ff04 + .db "GICR" + .dw VE_HEAD + .set VE_HEAD=VE_GICR +XT_GICR: + .dw PFA_DOVARIABLE +PFA_GICR: + .dw 91 +; ( -- addr ) System Constant +; R( -- ) +; General Interrupt Flag Register +VE_GIFR: + .dw $ff04 + .db "GIFR" + .dw VE_HEAD + .set VE_HEAD=VE_GIFR +XT_GIFR: + .dw PFA_DOVARIABLE +PFA_GIFR: + .dw 90 +; ( -- addr ) System Constant +; R( -- ) +; Pin Change Mask Register 1 +VE_PCMSK1: + .dw $ff06 + .db "PCMSK1" + .dw VE_HEAD + .set VE_HEAD=VE_PCMSK1 +XT_PCMSK1: + .dw PFA_DOVARIABLE +PFA_PCMSK1: + .dw 108 +; ( -- addr ) System Constant +; R( -- ) +; Pin Change Enable Mask +VE_PCMSK0: + .dw $ff06 + .db "PCMSK0" + .dw VE_HEAD + .set VE_HEAD=VE_PCMSK0 +XT_PCMSK0: + .dw PFA_DOVARIABLE +PFA_PCMSK0: + .dw 107 + +.endif diff --git a/amforth-6.5/avr8/devices/atmega162/device.py b/amforth-6.5/avr8/devices/atmega162/device.py new file mode 100644 index 0000000..850bee2 --- /dev/null +++ b/amforth-6.5/avr8/devices/atmega162/device.py @@ -0,0 +1,332 @@ +# Generated Automatically + +# Partname ATmega162 + +MCUREGS = { +# Interrupt Vectors + 'INT0Addr' : '#2', # External Interrupt Request 0 + 'INT1Addr' : '#4', # External Interrupt Request 1 + 'INT2Addr' : '#6', # External Interrupt Request 2 + 'PCINT0Addr' : '#8', # Pin Change Interrupt Request 0 + 'PCINT1Addr' : '#10', # Pin Change Interrupt Request 1 + 'TIMER3_CAPTAddr' : '#12', # Timer/Counter3 Capture Event + 'TIMER3_COMPAAddr' : '#14', # Timer/Counter3 Compare Match A + 'TIMER3_COMPBAddr' : '#16', # Timer/Counter3 Compare Match B + 'TIMER3_OVFAddr' : '#18', # Timer/Counter3 Overflow + 'TIMER2_COMPAddr' : '#20', # Timer/Counter2 Compare Match + 'TIMER2_OVFAddr' : '#22', # Timer/Counter2 Overflow + 'TIMER1_CAPTAddr' : '#24', # Timer/Counter1 Capture Event + 'TIMER1_COMPAAddr' : '#26', # Timer/Counter1 Compare Match A + 'TIMER1_COMPBAddr' : '#28', # Timer/Counter Compare Match B + 'TIMER1_OVFAddr' : '#30', # Timer/Counter1 Overflow + 'TIMER0_COMPAddr' : '#32', # Timer/Counter0 Compare Match + 'TIMER0_OVFAddr' : '#34', # Timer/Counter0 Overflow + 'SPI_STCAddr' : '#36', # SPI Serial Transfer Complete + 'USART0_RXCAddr' : '#38', # USART0, Rx Complete + 'USART1_RXCAddr' : '#40', # USART1, Rx Complete + 'USART0_UDREAddr' : '#42', # USART0 Data register Empty + 'USART1_UDREAddr' : '#44', # USART1, Data register Empty + 'USART0_TXCAddr' : '#46', # USART0, Tx Complete + 'USART1_TXCAddr' : '#48', # USART1, Tx Complete + 'EE_RDYAddr' : '#50', # EEPROM Ready + 'ANA_COMPAddr' : '#52', # Analog Comparator + 'SPM_RDYAddr' : '#54', # Store Program Memory Read + +# Module TIMER_COUNTER_1 + 'TIMSK' : '$59', # Timer/Counter Interrupt Mask R + 'TIMSK_TOIE1': '$80', # Timer/Counter1 Overflow Interr + 'TIMSK_OCIE1A': '$40', # Timer/Counter1 Output CompareA + 'TIMSK_OCIE1B': '$20', # Timer/Counter1 Output CompareB + 'TIMSK_TICIE1': '$8', # Timer/Counter1 Input Capture I + 'TIFR' : '$58', # Timer/Counter Interrupt Flag r + 'TIFR_TOV1': '$80', # Timer/Counter1 Overflow Flag + 'TIFR_OCF1A': '$40', # Output Compare Flag 1A + 'TIFR_OCF1B': '$20', # Output Compare Flag 1B + 'TIFR_ICF1': '$8', # Input Capture Flag 1 + 'TCCR1A' : '$4f', # Timer/Counter1 Control Registe + 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits + 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits + 'TCCR1A_FOC1A': '$8', # Force Output Compare for Chann + 'TCCR1A_FOC1B': '$4', # Force Output Compare for Chann + 'TCCR1A_WGM1': '$3', # Pulse Width Modulator Select B + 'TCCR1B' : '$4e', # Timer/Counter1 Control Registe + 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler + 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select + 'TCCR1B_WGM1': '$18', # Pulse Width Modulator Select B + 'TCCR1B_CS1': '$7', # Clock Select1 bits + 'TCNT1' : '$4c', # Timer/Counter1 Bytes + 'OCR1A' : '$4a', # Timer/Counter1 Output Compare + 'OCR1B' : '$48', # Timer/Counter1 Output Compare + 'ICR1' : '$44', # Timer/Counter1 Input Capture R + +# Module TIMER_COUNTER_2 + 'TCCR2' : '$47', # Timer/Counter Control Register + 'TCCR2_FOC2': '$80', # Forde Output Compare + 'TCCR2_WGM20': '$40', # Pulse Width Modulator Select B + 'TCCR2_COM2': '$30', # Compare Match Output Mode + 'TCCR2_WGM21': '$8', # Pulse Width Modulator Select B + 'TCCR2_CS2': '$7', # Clock Select + 'TCNT2' : '$43', # Timer/Counter Register + 'OCR2' : '$42', # Output Compare Register + 'TIMSK' : '$59', # Timer/Counter Interrupt Mask R + 'TIMSK_OCIE2': '$10', # Timer/Counter2 Output Compare + 'TIMSK_TOIE2': '$4', # Timer/Counter2 Overflow Interr + 'TIFR' : '$58', # Timer/Counter Interrupt Flag R + 'TIFR_OCF2': '$10', # Output Compare Flag 2 + 'TIFR_TOV2': '$4', # Timer/Counter2 Overflow Flag + 'ASSR' : '$46', # Asynchronous Status Register + 'ASSR_AS2': '$8', # Asynchronous Timer 2 + 'ASSR_TCN2UB': '$4', # Timer/Counter2 Update Busy + 'ASSR_OCR2UB': '$2', # Output Compare Register2 Updat + 'ASSR_TCR2UB': '$1', # Timer/Counter Control Register + +# Module TIMER_COUNTER_3 + 'ETIMSK' : '$7d', # Extended Timer/Counter Interru + 'ETIMSK_TICIE3': '$20', # Timer/Counter3 Input Capture I + 'ETIMSK_OCIE3A': '$10', # Timer/Counter3 Output CompareA + 'ETIMSK_OCIE3B': '$8', # Timer/Counter3 Output CompareB + 'ETIMSK_TOIE3': '$4', # Timer/Counter3 Overflow Interr + 'ETIFR' : '$7c', # Extended Timer/Counter Interru + 'ETIFR_ICF3': '$20', # Input Capture Flag 3 + 'ETIFR_OCF3A': '$10', # Output Compare Flag 3A + 'ETIFR_OCF3B': '$8', # Output Compare Flag 3B + 'ETIFR_TOV3': '$4', # Timer/Counter3 Overflow Flag + 'TCCR3A' : '$8b', # Timer/Counter3 Control Registe + 'TCCR3A_COM3A': '$c0', # Compare Output Mode 3A, bits + 'TCCR3A_COM3B': '$30', # Compare Output Mode 3B, bits + 'TCCR3A_FOC3A': '$8', # Force Output Compare for Chann + 'TCCR3A_FOC3B': '$4', # Force Output Compare for Chann + 'TCCR3A_WGM3': '$3', # Pulse Width Modulator Select B + 'TCCR3B' : '$8a', # Timer/Counter3 Control Registe + 'TCCR3B_ICNC3': '$80', # Input Capture 3 Noise Canceler + 'TCCR3B_ICES3': '$40', # Input Capture 3 Edge Select + 'TCCR3B_WGM3': '$18', # Pulse Width Modulator Select B + 'TCCR3B_CS3': '$7', # Clock Select3 bits + 'TCNT3' : '$88', # Timer/Counter3 Bytes + 'OCR3A' : '$86', # Timer/Counter3 Output Compare + 'OCR3B' : '$84', # Timer/Counte3 Output Compare R + 'ICR3' : '$80', # Timer/Counter3 Input Capture R + +# Module ANALOG_COMPARATOR + 'ACSR' : '$28', # Analog Comparator Control And + 'ACSR_ACD': '$80', # Analog Comparator Disable + 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele + 'ACSR_ACO': '$20', # Analog Compare Output + 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl + 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En + 'ACSR_ACIC': '$4', # Analog Comparator Input Captur + 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo + +# Module USART0 + 'UDR0' : '$2c', # USART I/O Data Register + 'UCSR0A' : '$2b', # USART Control and Status Regis + 'UCSR0A_RXC0': '$80', # USART Receive Complete + 'UCSR0A_TXC0': '$40', # USART Transmitt Complete + 'UCSR0A_UDRE0': '$20', # USART Data Register Empty + 'UCSR0A_FE0': '$10', # Framing Error + 'UCSR0A_DOR0': '$8', # Data overRun + 'UCSR0A_UPE0': '$4', # Parity Error + 'UCSR0A_U2X0': '$2', # Double the USART transmission + 'UCSR0A_MPCM0': '$1', # Multi-processor Communication + 'UCSR0B' : '$2a', # USART Control and Status Regis + 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable + 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable + 'UCSR0B_UDRIE0': '$20', # USART Data register Empty Inte + 'UCSR0B_RXEN0': '$10', # Receiver Enable + 'UCSR0B_TXEN0': '$8', # Transmitter Enable + 'UCSR0B_UCSZ02': '$4', # Character Size + 'UCSR0B_RXB80': '$2', # Receive Data Bit 8 + 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8 + 'UCSR0C' : '$40', # USART Control and Status Regis + 'UCSR0C_URSEL0': '$80', # Register Select + 'UCSR0C_UMSEL0': '$40', # USART Mode Select + 'UCSR0C_UPM0': '$30', # Parity Mode Bits + 'UCSR0C_USBS0': '$8', # Stop Bit Select + 'UCSR0C_UCSZ0': '$6', # Character Size + 'UCSR0C_UCPOL0': '$1', # Clock Polarity + 'UBRR0H' : '$40', # USART Baud Rate Register Hight + 'UBRR0L' : '$29', # USART Baud Rate Register Low B + +# Module USART1 + 'UDR' : '$23', # USART I/O Data Register + 'UCSR1A' : '$22', # USART Control and Status Regis + 'UCSR1A_RXC1': '$80', # USART Receive Complete + 'UCSR1A_TXC1': '$40', # USART Transmitt Complete + 'UCSR1A_UDRE1': '$20', # USART Data Register Empty + 'UCSR1A_FE1': '$10', # Framing Error + 'UCSR1A_DOR1': '$8', # Data overRun + 'UCSR1A_UPE1': '$4', # Parity Error + 'UCSR1A_U2X1': '$2', # Double the USART transmission + 'UCSR1A_MPCM1': '$1', # Multi-processor Communication + 'UCSR1B' : '$21', # USART Control and Status Regis + 'UCSR1B_RXCIE1': '$80', # RX Complete Interrupt Enable + 'UCSR1B_TXCIE1': '$40', # TX Complete Interrupt Enable + 'UCSR1B_UDRIE1': '$20', # USART Data register Empty Inte + 'UCSR1B_RXEN1': '$10', # Receiver Enable + 'UCSR1B_TXEN1': '$8', # Transmitter Enable + 'UCSR1B_UCSZ12': '$4', # Character Size + 'UCSR1B_RXB81': '$2', # Receive Data Bit 8 + 'UCSR1B_TXB81': '$1', # Transmit Data Bit 8 + 'UCSR1C' : '$5c', # USART Control and Status Regis + 'UCSR1C_URSEL1': '$80', # Register Select + 'UCSR1C_UMSEL1': '$40', # USART Mode Select + 'UCSR1C_UPM1': '$30', # Parity Mode Bits + 'UCSR1C_USBS1': '$8', # Stop Bit Select + 'UCSR1C_UCSZ1': '$6', # Character Size + 'UCSR1C_UCPOL1': '$1', # Clock Polarity + 'UBRR1H' : '$5c', # USART Baud Rate Register Highg + 'UBRR1L' : '$20', # USART Baud Rate Register Low B + +# Module SPI + 'SPCR' : '$2d', # SPI Control Register + 'SPCR_SPIE': '$80', # SPI Interrupt Enable + 'SPCR_SPE': '$40', # SPI Enable + 'SPCR_DORD': '$20', # Data Order + 'SPCR_MSTR': '$10', # Master/Slave Select + 'SPCR_CPOL': '$8', # Clock polarity + 'SPCR_CPHA': '$4', # Clock Phase + 'SPCR_SPR': '$3', # SPI Clock Rate Selects + 'SPSR' : '$2e', # SPI Status Register + 'SPSR_SPIF': '$80', # SPI Interrupt Flag + 'SPSR_WCOL': '$40', # Write Collision Flag + 'SPSR_SPI2X': '$1', # Double SPI Speed Bit + 'SPDR' : '$2f', # SPI Data Register + +# Module CPU + 'SREG' : '$5f', # Status Register + 'SREG_I': '$80', # Global Interrupt Enable + 'SREG_T': '$40', # Bit Copy Storage + 'SREG_H': '$20', # Half Carry Flag + 'SREG_S': '$10', # Sign Bit + 'SREG_V': '$8', # Two's Complement Overflow Flag + 'SREG_N': '$4', # Negative Flag + 'SREG_Z': '$2', # Zero Flag + 'SREG_C': '$1', # Carry Flag + 'SP' : '$5d', # Stack Pointer + 'MCUCR' : '$55', # MCU Control Register + 'MCUCR_SRE': '$80', # External SRAM Enable + 'MCUCR_SRW10': '$40', # External SRAM Wait State Selec + 'MCUCR_SE': '$20', # Sleep Enable + 'MCUCR_SM1': '$10', # Sleep Mode Select + 'MCUCR_ISC1': '$c', # Interrupt Sense Control 1 bits + 'MCUCR_ISC0': '$3', # Interrupt Sense Control 0 bits + 'MCUCSR' : '$54', # MCU Control And Status Registe + 'MCUCSR_JDT': '$80', # JTAG Interface Disable + 'MCUCSR_SM2': '$20', # Sleep Mode Select Bit 2 + 'MCUCSR_JTRF': '$10', # JTAG Reset Flag + 'MCUCSR_WDRF': '$8', # Watchdog Reset Flag + 'MCUCSR_BORF': '$4', # Brown-out Reset Flag + 'MCUCSR_EXTRF': '$2', # External Reset Flag + 'MCUCSR_PORF': '$1', # Power-on reset flag + 'EMCUCR' : '$56', # Extended MCU Control Register + 'EMCUCR_SM0': '$80', # Sleep mode Select Bit 0 + 'EMCUCR_SRL': '$70', # Wait State Sector Limit Bits + 'EMCUCR_SRW0': '$c', # Wait State Select Bit 1 for Lo + 'EMCUCR_SRW11': '$2', # Wait State Select Bit 1 for Up + 'EMCUCR_ISC2': '$1', # Interrupt Sense Control 2 + 'OSCCAL' : '$24', # Oscillator Calibration Value + 'CLKPR' : '$61', # Clock prescale register + 'CLKPR_CLKPCE': '$80', # Clock Prescaler Change Enable + 'CLKPR_CLKPS': '$f', # Clock Prescaler Select Bits + 'SFIOR' : '$50', # Special Function IO Register + 'SFIOR_TSM': '$80', # Timer/Counter Synchronization + 'SFIOR_XMBK': '$40', # External Memory Bus Keeper Ena + 'SFIOR_XMM': '$38', # External Memory High Mask Bits + 'SFIOR_PUD': '$4', # Pull-up Disable + 'SFIOR_PSR2': '$2', # Prescaler Reset Timer/Counter2 + 'SFIOR_PSR310': '$1', # Prescaler Reset Timer/Counter3 + +# Module JTAG + 'OCDR' : '$24', # On-Chip Debug Related Register + 'OCDR_OCDR': '$ff', # On-Chip Debug Register Bits + 'MCUCSR' : '$54', # MCU Control And Status Registe + 'MCUCSR_JTD': '$80', # JTAG Interface Disable + 'MCUCSR_JTRF': '$10', # JTAG Reset Flag + +# Module BOOT_LOAD + 'SPMCR' : '$57', # Store Program Memory Control R + 'SPMCR_SPMIE': '$80', # SPM Interrupt Enable + 'SPMCR_RWWSB': '$40', # Read While Write Section Busy + 'SPMCR_RWWSRE': '$10', # Read While Write secion read e + 'SPMCR_BLBSET': '$8', # Boot Lock Bit Set + 'SPMCR_PGWRT': '$4', # Page Write + 'SPMCR_PGERS': '$2', # Page Erase + 'SPMCR_SPMEN': '$1', # Store Program Memory Enable + +# Module EEPROM + 'EEAR' : '$3e', # EEPROM Address Register Bytes + 'EEDR' : '$3d', # EEPROM Data Register + 'EECR' : '$3c', # EEPROM Control Register + 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable + 'EECR_EEMWE': '$4', # EEPROM Master Write Enable + 'EECR_EEWE': '$2', # EEPROM Write Enable + 'EECR_EERE': '$1', # EEPROM Read Enable + +# Module PORTA + 'PORTA' : '$3b', # Port A Data Register + 'DDRA' : '$3a', # Port A Data Direction Register + 'PINA' : '$39', # Port A Input Pins + +# Module PORTB + 'PORTB' : '$38', # Port B Data Register + 'DDRB' : '$37', # Port B Data Direction Register + 'PINB' : '$36', # Port B Input Pins + +# Module PORTC + 'PORTC' : '$35', # Port C Data Register + 'DDRC' : '$34', # Port C Data Direction Register + 'PINC' : '$33', # Port C Input Pins + +# Module PORTD + 'PORTD' : '$32', # Port D Data Register + 'DDRD' : '$31', # Port D Data Direction Register + 'PIND' : '$30', # Port D Input Pins + +# Module TIMER_COUNTER_0 + 'TCCR0' : '$53', # Timer/Counter 0 Control Regist + 'TCCR0_FOC0': '$80', # Force Output Compare + 'TCCR0_WGM00': '$40', # Waveform Generation Mode 0 + 'TCCR0_COM0': '$30', # Compare Match Output Modes + 'TCCR0_WGM01': '$8', # Waveform Generation Mode 1 + 'TCCR0_CS0': '$7', # Clock Selects + 'TCNT0' : '$52', # Timer/Counter 0 Register + 'OCR0' : '$51', # Timer/Counter 0 Output Compare + 'TIMSK' : '$59', # Timer/Counter Interrupt Mask R + 'TIMSK_TOIE0': '$2', # Timer/Counter0 Overflow Interr + 'TIMSK_OCIE0': '$1', # Timer/Counter0 Output Compare + 'TIFR' : '$58', # Timer/Counter Interrupt Flag r + 'TIFR_TOV0': '$2', # Timer/Counter0 Overflow Flag + 'TIFR_OCF0': '$1', # Output Compare Flag 0 + +# Module WATCHDOG + 'WDTCR' : '$41', # Watchdog Timer Control Registe + 'WDTCR_WDCE': '$10', # Watchdog Change Enable + 'WDTCR_WDE': '$8', # Watch Dog Enable + 'WDTCR_WDP': '$7', # Watch Dog Timer Prescaler bits + +# Module PORTE + 'PORTE' : '$27', # Data Register, Port E + 'DDRE' : '$26', # Data Direction Register, Port + 'PINE' : '$25', # Input Pins, Port E + +# Module EXTERNAL_INTERRUPT + 'MCUCR' : '$55', # MCU Control Register + 'MCUCR_ISC1': '$c', # Interrupt Sense Control 1 Bits + 'MCUCR_ISC0': '$3', # Interrupt Sense Control 0 Bits + 'EMCUCR' : '$56', # Extended MCU Control Register + 'EMCUCR_ISC2': '$1', # Interrupt Sense Control 2 + 'GICR' : '$5b', # General Interrupt Control Regi + 'GICR_INT': '$c0', # External Interrupt Request 1 E + 'GICR_INT2': '$20', # External Interrupt Request 2 E + 'GICR_PCIE': '$18', # Pin Change Interrupt Enables + 'GICR_IVSEL': '$2', # Interrupt Vector Select + 'GICR_IVCE': '$1', # Interrupt Vector Change Enable + 'GIFR' : '$5a', # General Interrupt Flag Registe + 'GIFR_INTF': '$c0', # External Interrupt Flags + 'GIFR_INTF2': '$20', # External Interrupt Flag 2 + 'GIFR_PCIF': '$18', # Pin Change Interrupt Flags + 'PCMSK1' : '$6c', # Pin Change Mask Register 1 + 'PCMSK0' : '$6b', # Pin Change Enable Mask + + '__amforth_dummy':'0' +} diff --git a/amforth-6.5/avr8/devices/atmega162/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega162/words/no-jtag.asm new file mode 100644 index 0000000..352a4bb --- /dev/null +++ b/amforth-6.5/avr8/devices/atmega162/words/no-jtag.asm @@ -0,0 +1,14 @@ +; ( -- ) +; ( -- ) +; MCU +; disable jtag at runtime +VE_NOJTAG: + .dw $FF05 + .db "-jtag",0 + .dw VE_HEAD + .set VE_HEAD = VE_NOJTAG +XT_NOJTAG: + .dw PFA_NOJTAG +PFA_NOJTAG: + + jmp_ DO_NEXT diff --git a/amforth-6.5/avr8/devices/atmega162/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega162/words/no-wdt.asm new file mode 100644 index 0000000..4a12261 --- /dev/null +++ b/amforth-6.5/avr8/devices/atmega162/words/no-wdt.asm @@ -0,0 +1,22 @@ +; ( -- ) +; MCU +; disable watch dog timer at runtime +VE_NOWDT: + .dw $ff04 + .db "-wdt" + .dw VE_HEAD + .set VE_HEAD = VE_NOWDT +XT_NOWDT: + .dw PFA_NOWDT +PFA_NOWDT: + +; Reset WDT + wdr +; Write logical one to WDTOE and WDE + in_ temp1, WDTCR + ori temp1, (1<