From 67d25d837ac55f28a366c0a3b262e439a6e75fc3 Mon Sep 17 00:00:00 2001 From: Dimitri Sokolyuk Date: Sat, 19 Aug 2017 12:15:28 +0200 Subject: Add AmForth --- amforth-6.5/avr8/devices/atmega163/atmega163.frt | 121 ++++ amforth-6.5/avr8/devices/atmega163/device.asm | 108 +++ amforth-6.5/avr8/devices/atmega163/device.inc | 861 +++++++++++++++++++++++ amforth-6.5/avr8/devices/atmega163/device.py | 85 +++ 4 files changed, 1175 insertions(+) create mode 100644 amforth-6.5/avr8/devices/atmega163/atmega163.frt create mode 100644 amforth-6.5/avr8/devices/atmega163/device.asm create mode 100644 amforth-6.5/avr8/devices/atmega163/device.inc create mode 100644 amforth-6.5/avr8/devices/atmega163/device.py (limited to 'amforth-6.5/avr8/devices/atmega163') diff --git a/amforth-6.5/avr8/devices/atmega163/atmega163.frt b/amforth-6.5/avr8/devices/atmega163/atmega163.frt new file mode 100644 index 0000000..796fd3f --- /dev/null +++ b/amforth-6.5/avr8/devices/atmega163/atmega163.frt @@ -0,0 +1,121 @@ +\ Partname: ATmega163 +\ Built using part description XML file version 207 +\ generated automatically + +hex + +\ AD_CONVERTER +25 constant ADCH \ ADC Data Register High Byte +24 constant ADCL \ ADC Data Register Low Byte +26 constant ADCSR \ The ADC Control and Status register +27 constant ADMUX \ The ADC multiplexer Selection Register + +\ ANALOG_COMPARATOR +28 constant ACSR \ Analog Comparator Control And Status Register +50 constant SFIOR \ Special Function IO Register + +\ BOOT_LOAD +57 constant SPMCR \ Store Program Memory Control Register + +\ CPU +55 constant MCUCR \ MCU Control register +54 constant MCUSR \ MCU Status Register +51 constant OSCCAL \ Oscillator Calibration Value +5E constant SPH \ Stack Pointer High +5D constant SPL \ Stack Pointer Low +5F constant SREG \ Status Register + +\ EEPROM +3F constant EEARH \ EEPROM Address Register High Byte +3E constant EEARL \ EEPROM Address Register Low Byte +3C constant EECR \ EEPROM Control Register +3D constant EEDR \ EEPROM Data Register + +\ EXTERNAL_INTERRUPT +5A constant GIFR \ General Interrupt Flag register +5B constant GIMSK \ General Interrupt Mask Register + +\ PORTA +3A constant DDRA \ Port A Data Direction Register +39 constant PINA \ Port A Input Pins +3B constant PORTA \ Port A Data Register + +\ PORTB +37 constant DDRB \ Port B Data Direction Register +36 constant PINB \ Port B Input Pins +38 constant PORTB \ Port B Data Register + +\ PORTC +34 constant DDRC \ Port C Data Direction Register +33 constant PINC \ Port C Input Pins +35 constant PORTC \ Port C Data Register + +\ PORTD +31 constant DDRD \ Port D Data Direction Register +30 constant PIND \ Port D Input Pins +32 constant PORTD \ Port D Data Register + +\ SPI +2D constant SPCR \ SPI Control Register +2F constant SPDR \ SPI Data Register +2E constant SPSR \ SPI Status Register + +\ TIMER_COUNTER_0 +53 constant TCCR0 \ Timer/Counter0 Control Register +52 constant TCNT0 \ Timer Counter 0 +58 constant TIFR \ Timer/Counter Interrupt Flag register +59 constant TIMSK \ Timer/Counter Interrupt Mask Register + +\ TIMER_COUNTER_1 +47 constant ICR1H \ Timer/Counter1 Input Capture Register High Byte +46 constant ICR1L \ Timer/Counter1 Input Capture Register Low Byte +4B constant OCR1AH \ Timer/Counter1 Output Compare Register High Byte +4A constant OCR1AL \ Timer/Counter1 Output Compare Register Low Byte +49 constant OCR1BH \ Timer/Counter1 Output Compare Register High Byte +48 constant OCR1BL \ Timer/Counter1 Output Compare Register Low Byte +4F constant TCCR1A \ Timer/Counter1 Control Register A +4E constant TCCR1B \ Timer/Counter1 Control Register B +4D constant TCNT1H \ Timer/Counter1 High Byte +4C constant TCNT1L \ Timer/Counter1 Low Byte + +\ TIMER_COUNTER_2 +42 constant ASSR \ Asynchronous Status Register +43 constant OCR2 \ Timer/Counter2 Output Compare Register +45 constant TCCR2 \ Timer/Counter2 Control Register +44 constant TCNT2 \ Timer/Counter2 + +\ TWI +22 constant TWAR \ TWI (Slave) Address register +20 constant TWBR \ TWI Bit Rate register +56 constant TWCR \ TWI Control Register +23 constant TWDR \ TWI Data register +21 constant TWSR \ TWI Status Register + +\ UART +29 constant UBRR \ UART Baud Rate Register +40 constant UBRRHI \ UART Baud Rate Register High Byte +2B constant UCSRA \ UART Control and Status register A +2A constant UCSRB \ UART Control an Status register B +2C constant UDR \ UART I/O Data Register + +\ WATCHDOG +41 constant WDTCR \ Watchdog Timer Control Register + +\ Interrupts +002 constant INT0Addr \ External Interrupt 0 +004 constant INT1Addr \ External Interrupt 1 +006 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match +008 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow +00A constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event +00C constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A +00E constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B +010 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow +012 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow +014 constant SPISTCAddr \ SPI Serial Transfer Complete +016 constant UARTRXAddr \ UART, RX Complete +018 constant UARTUDREAddr \ UART Data Register Empty +01A constant UARTTXAddr \ UART, TX Complete +01C constant ADCAddr \ ADC Conversion Complete +01E constant EE_RDYAddr \ EEPROM Ready +020 constant ANA_COMPAddr \ Analog Comparator +022 constant TWIAddr \ 2-Wire Serial Interface diff --git a/amforth-6.5/avr8/devices/atmega163/device.asm b/amforth-6.5/avr8/devices/atmega163/device.asm new file mode 100644 index 0000000..2a6a80f --- /dev/null +++ b/amforth-6.5/avr8/devices/atmega163/device.asm @@ -0,0 +1,108 @@ +; Partname: ATmega163 +; Built using part description XML file version 207 +; generated automatically, do not edit + +.nolist + .include "m163def.inc" +.list + +.equ ramstart = $60 +.equ CELLSIZE = 2 +.macro readflashcell + lsl zl + rol zh + lpm @0, Z+ + lpm @1, Z+ +.endmacro +.macro writeflashcell + lsl zl + rol zh +.endmacro + +; the following definitions are shortcuts for the respective forth source segments if set to 1 +.set WANT_AD_CONVERTER = 0 +.set WANT_ANALOG_COMPARATOR = 0 +.set WANT_BOOT_LOAD = 0 +.set WANT_CPU = 0 +.set WANT_EEPROM = 0 +.set WANT_EXTERNAL_INTERRUPT = 0 +.set WANT_PORTA = 0 +.set WANT_PORTB = 0 +.set WANT_PORTC = 0 +.set WANT_PORTD = 0 +.set WANT_SPI = 0 +.set WANT_TIMER_COUNTER_0 = 0 +.set WANT_TIMER_COUNTER_1 = 0 +.set WANT_TIMER_COUNTER_2 = 0 +.set WANT_TWI = 0 +.set WANT_UART = 0 +.set WANT_WATCHDOG = 0 + + +.ifndef SPMEN + .equ SPMEN = SELFPRGEN +.endif + +.ifndef SPMCSR + .equ SPMCSR = SPMCR +.endif + +.ifndef EEPE + .equ EEPE = EEWE +.endif + +.ifndef EEMPE + .equ EEMPE = EEMWE +.endif +.equ intvecsize = 2 ; please verify; flash size: 16384 bytes +.equ pclen = 2 ; please verify +.overlap +.equ INTVECTORS = 18 +.org $002 + rcall isr ; External Interrupt 0 +.org $004 + rcall isr ; External Interrupt 1 +.org $006 + rcall isr ; Timer/Counter2 Compare Match +.org $008 + rcall isr ; Timer/Counter2 Overflow +.org $00A + rcall isr ; Timer/Counter1 Capture Event +.org $00C + rcall isr ; Timer/Counter1 Compare Match A +.org $00E + rcall isr ; Timer/Counter1 Compare Match B +.org $010 + rcall isr ; Timer/Counter1 Overflow +.org $012 + rcall isr ; Timer/Counter0 Overflow +.org $014 + rcall isr ; SPI Serial Transfer Complete +.org $016 + rcall isr ; UART, RX Complete +.org $018 + rcall isr ; UART Data Register Empty +.org $01A + rcall isr ; UART, TX Complete +.org $01C + rcall isr ; ADC Conversion Complete +.org $01E + rcall isr ; EEPROM Ready +.org $020 + rcall isr ; Analog Comparator +.org $022 + rcall isr ; 2-Wire Serial Interface +.nooverlap +mcu_info: +mcu_ramsize: + .dw 1024 +mcu_eepromsize: + .dw 512 +mcu_maxdp: + .dw 0 ; minimum of 0 (from XML) and 0xffff +mcu_numints: + .dw 18 +mcu_name: + .dw 9 + .db "ATmega163",0 +.set codestart=pc diff --git a/amforth-6.5/avr8/devices/atmega163/device.inc b/amforth-6.5/avr8/devices/atmega163/device.inc new file mode 100644 index 0000000..6f6359e --- /dev/null +++ b/amforth-6.5/avr8/devices/atmega163/device.inc @@ -0,0 +1,861 @@ +; Partname: ATmega163 +; Built using part description XML file version 207 +; generated automatically, no not edit + +; ******** +.if WANT_AD_CONVERTER == 1 +; ******** +; ( -- addr ) System Constant +; R( -- ) +; ADC Data Register High Byte +VE_ADCH: + .dw $ff04 + .db "ADCH" + .dw VE_HEAD + .set VE_HEAD=VE_ADCH +XT_ADCH: + .dw PFA_DOVARIABLE +PFA_ADCH: + .dw $25 +; ( -- addr ) System Constant +; R( -- ) +; ADC Data Register Low Byte +VE_ADCL: + .dw $ff04 + .db "ADCL" + .dw VE_HEAD + .set VE_HEAD=VE_ADCL +XT_ADCL: + .dw PFA_DOVARIABLE +PFA_ADCL: + .dw $24 +; ( -- addr ) System Constant +; R( -- ) +; The ADC Control and Status register +VE_ADCSR: + .dw $ff05 + .db "ADCSR",0 + .dw VE_HEAD + .set VE_HEAD=VE_ADCSR +XT_ADCSR: + .dw PFA_DOVARIABLE +PFA_ADCSR: + .dw $26 +; ( -- addr ) System Constant +; R( -- ) +; The ADC multiplexer Selection Register +VE_ADMUX: + .dw $ff05 + .db "ADMUX",0 + .dw VE_HEAD + .set VE_HEAD=VE_ADMUX +XT_ADMUX: + .dw PFA_DOVARIABLE +PFA_ADMUX: + .dw $27 + +.endif + +; ******** +.if WANT_ANALOG_COMPARATOR == 1 +; ******** +; ( -- addr ) System Constant +; R( -- ) +; Analog Comparator Control And Status Register +VE_ACSR: + .dw $ff04 + .db "ACSR" + .dw VE_HEAD + .set VE_HEAD=VE_ACSR +XT_ACSR: + .dw PFA_DOVARIABLE +PFA_ACSR: + .dw $28 +; ( -- addr ) System Constant +; R( -- ) +; Special Function IO Register +VE_SFIOR: + .dw $ff05 + .db "SFIOR",0 + .dw VE_HEAD + .set VE_HEAD=VE_SFIOR +XT_SFIOR: + .dw PFA_DOVARIABLE +PFA_SFIOR: + .dw $50 + +.endif + +; ******** +.if WANT_BOOT_LOAD == 1 +; ******** +; ( -- addr ) System Constant +; R( -- ) +; Store Program Memory Control Register +VE_SPMCR: + .dw $ff05 + .db "SPMCR",0 + .dw VE_HEAD + .set VE_HEAD=VE_SPMCR +XT_SPMCR: + .dw PFA_DOVARIABLE +PFA_SPMCR: + .dw $57 + +.endif + +; ******** +.if WANT_CPU == 1 +; ******** +; ( -- addr ) System Constant +; R( -- ) +; MCU Control register +VE_MCUCR: + .dw $ff05 + .db "MCUCR",0 + .dw VE_HEAD + .set VE_HEAD=VE_MCUCR +XT_MCUCR: + .dw PFA_DOVARIABLE +PFA_MCUCR: + .dw $55 +; ( -- addr ) System Constant +; R( -- ) +; MCU Status Register +VE_MCUSR: + .dw $ff05 + .db "MCUSR",0 + .dw VE_HEAD + .set VE_HEAD=VE_MCUSR +XT_MCUSR: + .dw PFA_DOVARIABLE +PFA_MCUSR: + .dw $54 +; ( -- addr ) System Constant +; R( -- ) +; Oscillator Calibration Value +VE_OSCCAL: + .dw $ff06 + .db "OSCCAL" + .dw VE_HEAD + .set VE_HEAD=VE_OSCCAL +XT_OSCCAL: + .dw PFA_DOVARIABLE +PFA_OSCCAL: + .dw $51 +; ( -- addr ) System Constant +; R( -- ) +; Stack Pointer High +VE_SPH: + .dw $ff03 + .db "SPH",0 + .dw VE_HEAD + .set VE_HEAD=VE_SPH +XT_SPH: + .dw PFA_DOVARIABLE +PFA_SPH: + .dw $5E +; ( -- addr ) System Constant +; R( -- ) +; Stack Pointer Low +VE_SPL: + .dw $ff03 + .db "SPL",0 + .dw VE_HEAD + .set VE_HEAD=VE_SPL +XT_SPL: + .dw PFA_DOVARIABLE +PFA_SPL: + .dw $5D +; ( -- addr ) System Constant +; R( -- ) +; Status Register +VE_SREG: + .dw $ff04 + .db "SREG" + .dw VE_HEAD + .set VE_HEAD=VE_SREG +XT_SREG: + .dw PFA_DOVARIABLE +PFA_SREG: + .dw $5F + +.endif + +; ******** +.if WANT_EEPROM == 1 +; ******** +; ( -- addr ) System Constant +; R( -- ) +; EEPROM Address Register High Byte +VE_EEARH: + .dw $ff05 + .db "EEARH",0 + .dw VE_HEAD + .set VE_HEAD=VE_EEARH +XT_EEARH: + .dw PFA_DOVARIABLE +PFA_EEARH: + .dw $3F +; ( -- addr ) System Constant +; R( -- ) +; EEPROM Address Register Low Byte +VE_EEARL: + .dw $ff05 + .db "EEARL",0 + .dw VE_HEAD + .set VE_HEAD=VE_EEARL +XT_EEARL: + .dw PFA_DOVARIABLE +PFA_EEARL: + .dw $3E +; ( -- addr ) System Constant +; R( -- ) +; EEPROM Control Register +VE_EECR: + .dw $ff04 + .db "EECR" + .dw VE_HEAD + .set VE_HEAD=VE_EECR +XT_EECR: + .dw PFA_DOVARIABLE +PFA_EECR: + .dw $3C +; ( -- addr ) System Constant +; R( -- ) +; EEPROM Data Register +VE_EEDR: + .dw $ff04 + .db "EEDR" + .dw VE_HEAD + .set VE_HEAD=VE_EEDR +XT_EEDR: + .dw PFA_DOVARIABLE +PFA_EEDR: + .dw $3D + +.endif + +; ******** +.if WANT_EXTERNAL_INTERRUPT == 1 +; ******** +; ( -- addr ) System Constant +; R( -- ) +; General Interrupt Flag register +VE_GIFR: + .dw $ff04 + .db "GIFR" + .dw VE_HEAD + .set VE_HEAD=VE_GIFR +XT_GIFR: + .dw PFA_DOVARIABLE +PFA_GIFR: + .dw $5A +; ( -- addr ) System Constant +; R( -- ) +; General Interrupt Mask Register +VE_GIMSK: + .dw $ff05 + .db "GIMSK",0 + .dw VE_HEAD + .set VE_HEAD=VE_GIMSK +XT_GIMSK: + .dw PFA_DOVARIABLE +PFA_GIMSK: + .dw $5B + +.endif + +; ******** +.if WANT_PORTA == 1 +; ******** +; ( -- addr ) System Constant +; R( -- ) +; Port A Data Direction Register +VE_DDRA: + .dw $ff04 + .db "DDRA" + .dw VE_HEAD + .set VE_HEAD=VE_DDRA +XT_DDRA: + .dw PFA_DOVARIABLE +PFA_DDRA: + .dw $3A +; ( -- addr ) System Constant +; R( -- ) +; Port A Input Pins +VE_PINA: + .dw $ff04 + .db "PINA" + .dw VE_HEAD + .set VE_HEAD=VE_PINA +XT_PINA: + .dw PFA_DOVARIABLE +PFA_PINA: + .dw $39 +; ( -- addr ) System Constant +; R( -- ) +; Port A Data Register +VE_PORTA: + .dw $ff05 + .db "PORTA",0 + .dw VE_HEAD + .set VE_HEAD=VE_PORTA +XT_PORTA: + .dw PFA_DOVARIABLE +PFA_PORTA: + .dw $3B + +.endif + +; ******** +.if WANT_PORTB == 1 +; ******** +; ( -- addr ) System Constant +; R( -- ) +; Port B Data Direction Register +VE_DDRB: + .dw $ff04 + .db "DDRB" + .dw VE_HEAD + .set VE_HEAD=VE_DDRB +XT_DDRB: + .dw PFA_DOVARIABLE +PFA_DDRB: + .dw $37 +; ( -- addr ) System Constant +; R( -- ) +; Port B Input Pins +VE_PINB: + .dw $ff04 + .db "PINB" + .dw VE_HEAD + .set VE_HEAD=VE_PINB +XT_PINB: + .dw PFA_DOVARIABLE +PFA_PINB: + .dw $36 +; ( -- addr ) System Constant +; R( -- ) +; Port B Data Register +VE_PORTB: + .dw $ff05 + .db "PORTB",0 + .dw VE_HEAD + .set VE_HEAD=VE_PORTB +XT_PORTB: + .dw PFA_DOVARIABLE +PFA_PORTB: + .dw $38 + +.endif + +; ******** +.if WANT_PORTC == 1 +; ******** +; ( -- addr ) System Constant +; R( -- ) +; Port C Data Direction Register +VE_DDRC: + .dw $ff04 + .db "DDRC" + .dw VE_HEAD + .set VE_HEAD=VE_DDRC +XT_DDRC: + .dw PFA_DOVARIABLE +PFA_DDRC: + .dw $34 +; ( -- addr ) System Constant +; R( -- ) +; Port C Input Pins +VE_PINC: + .dw $ff04 + .db "PINC" + .dw VE_HEAD + .set VE_HEAD=VE_PINC +XT_PINC: + .dw PFA_DOVARIABLE +PFA_PINC: + .dw $33 +; ( -- addr ) System Constant +; R( -- ) +; Port C Data Register +VE_PORTC: + .dw $ff05 + .db "PORTC",0 + .dw VE_HEAD + .set VE_HEAD=VE_PORTC +XT_PORTC: + .dw PFA_DOVARIABLE +PFA_PORTC: + .dw $35 + +.endif + +; ******** +.if WANT_PORTD == 1 +; ******** +; ( -- addr ) System Constant +; R( -- ) +; Port D Data Direction Register +VE_DDRD: + .dw $ff04 + .db "DDRD" + .dw VE_HEAD + .set VE_HEAD=VE_DDRD +XT_DDRD: + .dw PFA_DOVARIABLE +PFA_DDRD: + .dw $31 +; ( -- addr ) System Constant +; R( -- ) +; Port D Input Pins +VE_PIND: + .dw $ff04 + .db "PIND" + .dw VE_HEAD + .set VE_HEAD=VE_PIND +XT_PIND: + .dw PFA_DOVARIABLE +PFA_PIND: + .dw $30 +; ( -- addr ) System Constant +; R( -- ) +; Port D Data Register +VE_PORTD: + .dw $ff05 + .db "PORTD",0 + .dw VE_HEAD + .set VE_HEAD=VE_PORTD +XT_PORTD: + .dw PFA_DOVARIABLE +PFA_PORTD: + .dw $32 + +.endif + +; ******** +.if WANT_SPI == 1 +; ******** +; ( -- addr ) System Constant +; R( -- ) +; SPI Control Register +VE_SPCR: + .dw $ff04 + .db "SPCR" + .dw VE_HEAD + .set VE_HEAD=VE_SPCR +XT_SPCR: + .dw PFA_DOVARIABLE +PFA_SPCR: + .dw $2D +; ( -- addr ) System Constant +; R( -- ) +; SPI Data Register +VE_SPDR: + .dw $ff04 + .db "SPDR" + .dw VE_HEAD + .set VE_HEAD=VE_SPDR +XT_SPDR: + .dw PFA_DOVARIABLE +PFA_SPDR: + .dw $2F +; ( -- addr ) System Constant +; R( -- ) +; SPI Status Register +VE_SPSR: + .dw $ff04 + .db "SPSR" + .dw VE_HEAD + .set VE_HEAD=VE_SPSR +XT_SPSR: + .dw PFA_DOVARIABLE +PFA_SPSR: + .dw $2E + +.endif + +; ******** +.if WANT_TIMER_COUNTER_0 == 1 +; ******** +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter0 Control Register +VE_TCCR0: + .dw $ff05 + .db "TCCR0",0 + .dw VE_HEAD + .set VE_HEAD=VE_TCCR0 +XT_TCCR0: + .dw PFA_DOVARIABLE +PFA_TCCR0: + .dw $53 +; ( -- addr ) System Constant +; R( -- ) +; Timer Counter 0 +VE_TCNT0: + .dw $ff05 + .db "TCNT0",0 + .dw VE_HEAD + .set VE_HEAD=VE_TCNT0 +XT_TCNT0: + .dw PFA_DOVARIABLE +PFA_TCNT0: + .dw $52 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter Interrupt Flag register +VE_TIFR: + .dw $ff04 + .db "TIFR" + .dw VE_HEAD + .set VE_HEAD=VE_TIFR +XT_TIFR: + .dw PFA_DOVARIABLE +PFA_TIFR: + .dw $58 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter Interrupt Mask Register +VE_TIMSK: + .dw $ff05 + .db "TIMSK",0 + .dw VE_HEAD + .set VE_HEAD=VE_TIMSK +XT_TIMSK: + .dw PFA_DOVARIABLE +PFA_TIMSK: + .dw $59 + +.endif + +; ******** +.if WANT_TIMER_COUNTER_1 == 1 +; ******** +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter1 Input Capture Register High Byte +VE_ICR1H: + .dw $ff05 + .db "ICR1H",0 + .dw VE_HEAD + .set VE_HEAD=VE_ICR1H +XT_ICR1H: + .dw PFA_DOVARIABLE +PFA_ICR1H: + .dw $47 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter1 Input Capture Register Low Byte +VE_ICR1L: + .dw $ff05 + .db "ICR1L",0 + .dw VE_HEAD + .set VE_HEAD=VE_ICR1L +XT_ICR1L: + .dw PFA_DOVARIABLE +PFA_ICR1L: + .dw $46 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter1 Output Compare Register High Byte +VE_OCR1AH: + .dw $ff06 + .db "OCR1AH" + .dw VE_HEAD + .set VE_HEAD=VE_OCR1AH +XT_OCR1AH: + .dw PFA_DOVARIABLE +PFA_OCR1AH: + .dw $4B +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter1 Output Compare Register Low Byte +VE_OCR1AL: + .dw $ff06 + .db "OCR1AL" + .dw VE_HEAD + .set VE_HEAD=VE_OCR1AL +XT_OCR1AL: + .dw PFA_DOVARIABLE +PFA_OCR1AL: + .dw $4A +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter1 Output Compare Register High Byte +VE_OCR1BH: + .dw $ff06 + .db "OCR1BH" + .dw VE_HEAD + .set VE_HEAD=VE_OCR1BH +XT_OCR1BH: + .dw PFA_DOVARIABLE +PFA_OCR1BH: + .dw $49 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter1 Output Compare Register Low Byte +VE_OCR1BL: + .dw $ff06 + .db "OCR1BL" + .dw VE_HEAD + .set VE_HEAD=VE_OCR1BL +XT_OCR1BL: + .dw PFA_DOVARIABLE +PFA_OCR1BL: + .dw $48 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter1 Control Register A +VE_TCCR1A: + .dw $ff06 + .db "TCCR1A" + .dw VE_HEAD + .set VE_HEAD=VE_TCCR1A +XT_TCCR1A: + .dw PFA_DOVARIABLE +PFA_TCCR1A: + .dw $4F +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter1 Control Register B +VE_TCCR1B: + .dw $ff06 + .db "TCCR1B" + .dw VE_HEAD + .set VE_HEAD=VE_TCCR1B +XT_TCCR1B: + .dw PFA_DOVARIABLE +PFA_TCCR1B: + .dw $4E +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter1 High Byte +VE_TCNT1H: + .dw $ff06 + .db "TCNT1H" + .dw VE_HEAD + .set VE_HEAD=VE_TCNT1H +XT_TCNT1H: + .dw PFA_DOVARIABLE +PFA_TCNT1H: + .dw $4D +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter1 Low Byte +VE_TCNT1L: + .dw $ff06 + .db "TCNT1L" + .dw VE_HEAD + .set VE_HEAD=VE_TCNT1L +XT_TCNT1L: + .dw PFA_DOVARIABLE +PFA_TCNT1L: + .dw $4C + +.endif + +; ******** +.if WANT_TIMER_COUNTER_2 == 1 +; ******** +; ( -- addr ) System Constant +; R( -- ) +; Asynchronous Status Register +VE_ASSR: + .dw $ff04 + .db "ASSR" + .dw VE_HEAD + .set VE_HEAD=VE_ASSR +XT_ASSR: + .dw PFA_DOVARIABLE +PFA_ASSR: + .dw $42 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter2 Output Compare Register +VE_OCR2: + .dw $ff04 + .db "OCR2" + .dw VE_HEAD + .set VE_HEAD=VE_OCR2 +XT_OCR2: + .dw PFA_DOVARIABLE +PFA_OCR2: + .dw $43 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter2 Control Register +VE_TCCR2: + .dw $ff05 + .db "TCCR2",0 + .dw VE_HEAD + .set VE_HEAD=VE_TCCR2 +XT_TCCR2: + .dw PFA_DOVARIABLE +PFA_TCCR2: + .dw $45 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter2 +VE_TCNT2: + .dw $ff05 + .db "TCNT2",0 + .dw VE_HEAD + .set VE_HEAD=VE_TCNT2 +XT_TCNT2: + .dw PFA_DOVARIABLE +PFA_TCNT2: + .dw $44 + +.endif + +; ******** +.if WANT_TWI == 1 +; ******** +; ( -- addr ) System Constant +; R( -- ) +; TWI (Slave) Address register +VE_TWAR: + .dw $ff04 + .db "TWAR" + .dw VE_HEAD + .set VE_HEAD=VE_TWAR +XT_TWAR: + .dw PFA_DOVARIABLE +PFA_TWAR: + .dw $22 +; ( -- addr ) System Constant +; R( -- ) +; TWI Bit Rate register +VE_TWBR: + .dw $ff04 + .db "TWBR" + .dw VE_HEAD + .set VE_HEAD=VE_TWBR +XT_TWBR: + .dw PFA_DOVARIABLE +PFA_TWBR: + .dw $20 +; ( -- addr ) System Constant +; R( -- ) +; TWI Control Register +VE_TWCR: + .dw $ff04 + .db "TWCR" + .dw VE_HEAD + .set VE_HEAD=VE_TWCR +XT_TWCR: + .dw PFA_DOVARIABLE +PFA_TWCR: + .dw $56 +; ( -- addr ) System Constant +; R( -- ) +; TWI Data register +VE_TWDR: + .dw $ff04 + .db "TWDR" + .dw VE_HEAD + .set VE_HEAD=VE_TWDR +XT_TWDR: + .dw PFA_DOVARIABLE +PFA_TWDR: + .dw $23 +; ( -- addr ) System Constant +; R( -- ) +; TWI Status Register +VE_TWSR: + .dw $ff04 + .db "TWSR" + .dw VE_HEAD + .set VE_HEAD=VE_TWSR +XT_TWSR: + .dw PFA_DOVARIABLE +PFA_TWSR: + .dw $21 + +.endif + +; ******** +.if WANT_UART == 1 +; ******** +; ( -- addr ) System Constant +; R( -- ) +; UART Baud Rate Register +VE_UBRR: + .dw $ff04 + .db "UBRR" + .dw VE_HEAD + .set VE_HEAD=VE_UBRR +XT_UBRR: + .dw PFA_DOVARIABLE +PFA_UBRR: + .dw $29 +; ( -- addr ) System Constant +; R( -- ) +; UART Baud Rate Register High Byte +VE_UBRRHI: + .dw $ff06 + .db "UBRRHI" + .dw VE_HEAD + .set VE_HEAD=VE_UBRRHI +XT_UBRRHI: + .dw PFA_DOVARIABLE +PFA_UBRRHI: + .dw $40 +; ( -- addr ) System Constant +; R( -- ) +; UART Control and Status register A +VE_UCSRA: + .dw $ff05 + .db "UCSRA",0 + .dw VE_HEAD + .set VE_HEAD=VE_UCSRA +XT_UCSRA: + .dw PFA_DOVARIABLE +PFA_UCSRA: + .dw $2B +; ( -- addr ) System Constant +; R( -- ) +; UART Control an Status register B +VE_UCSRB: + .dw $ff05 + .db "UCSRB",0 + .dw VE_HEAD + .set VE_HEAD=VE_UCSRB +XT_UCSRB: + .dw PFA_DOVARIABLE +PFA_UCSRB: + .dw $2A +; ( -- addr ) System Constant +; R( -- ) +; UART I/O Data Register +VE_UDR: + .dw $ff03 + .db "UDR",0 + .dw VE_HEAD + .set VE_HEAD=VE_UDR +XT_UDR: + .dw PFA_DOVARIABLE +PFA_UDR: + .dw $2C + +.endif + +; ******** +.if WANT_WATCHDOG == 1 +; ******** +; ( -- addr ) System Constant +; R( -- ) +; Watchdog Timer Control Register +VE_WDTCR: + .dw $ff05 + .db "WDTCR",0 + .dw VE_HEAD + .set VE_HEAD=VE_WDTCR +XT_WDTCR: + .dw PFA_DOVARIABLE +PFA_WDTCR: + .dw $41 + +.endif diff --git a/amforth-6.5/avr8/devices/atmega163/device.py b/amforth-6.5/avr8/devices/atmega163/device.py new file mode 100644 index 0000000..f344075 --- /dev/null +++ b/amforth-6.5/avr8/devices/atmega163/device.py @@ -0,0 +1,85 @@ +# Partname: ATmega163 +# Built using part description XML file version 207 +# generated automatically, do not edit +MCUREGS = { + 'ADCH': '$25', + 'ADCL': '$24', + 'ADCSR': '$26', + 'ADMUX': '$27', + 'ACSR': '$28', + 'SFIOR': '$50', + 'SPMCR': '$57', + 'MCUCR': '$55', + 'MCUSR': '$54', + 'OSCCAL': '$51', + 'SPH': '$5E', + 'SPL': '$5D', + 'SREG': '$5F', + 'EEARH': '$3F', + 'EEARL': '$3E', + 'EECR': '$3C', + 'EEDR': '$3D', + 'GIFR': '$5A', + 'GIMSK': '$5B', + 'DDRA': '$3A', + 'PINA': '$39', + 'PORTA': '$3B', + 'DDRB': '$37', + 'PINB': '$36', + 'PORTB': '$38', + 'DDRC': '$34', + 'PINC': '$33', + 'PORTC': '$35', + 'DDRD': '$31', + 'PIND': '$30', + 'PORTD': '$32', + 'SPCR': '$2D', + 'SPDR': '$2F', + 'SPSR': '$2E', + 'TCCR0': '$53', + 'TCNT0': '$52', + 'TIFR': '$58', + 'TIMSK': '$59', + 'ICR1H': '$47', + 'ICR1L': '$46', + 'OCR1AH': '$4B', + 'OCR1AL': '$4A', + 'OCR1BH': '$49', + 'OCR1BL': '$48', + 'TCCR1A': '$4F', + 'TCCR1B': '$4E', + 'TCNT1H': '$4D', + 'TCNT1L': '$4C', + 'ASSR': '$42', + 'OCR2': '$43', + 'TCCR2': '$45', + 'TCNT2': '$44', + 'TWAR': '$22', + 'TWBR': '$20', + 'TWCR': '$56', + 'TWDR': '$23', + 'TWSR': '$21', + 'UBRR': '$29', + 'UBRRHI': '$40', + 'UCSRA': '$2B', + 'UCSRB': '$2A', + 'UDR': '$2C', + 'WDTCR': '$41', + 'INT0Addr': '$002', + 'INT1Addr': '$004', + 'TIMER2_COMPAddr': '$006', + 'TIMER2_OVFAddr': '$008', + 'TIMER1_CAPTAddr': '$00A', + 'TIMER1_COMPAAddr': '$00C', + 'TIMER1_COMPBAddr': '$00E', + 'TIMER1_OVFAddr': '$010', + 'TIMER0_OVFAddr': '$012', + 'SPISTCAddr': '$014', + 'UARTRXAddr': '$016', + 'UARTUDREAddr': '$018', + 'UARTTXAddr': '$01A', + 'ADCAddr': '$01C', + 'EE_RDYAddr': '$01E', + 'ANA_COMPAddr': '$020', + 'TWIAddr': '$022' +} \ No newline at end of file -- cgit v1.2.3