From d80736ab6e8e3cad2f1a30c6eaba2d6883dbe967 Mon Sep 17 00:00:00 2001 From: Dimitri Sokolyuk Date: Sat, 26 Aug 2017 20:31:40 +0200 Subject: Remove AmForth --- amforth-6.5/avr8/devices/atmega16/atmega16.frt | 221 ------ amforth-6.5/avr8/devices/atmega16/device.asm | 101 --- amforth-6.5/avr8/devices/atmega16/device.inc | 765 --------------------- amforth-6.5/avr8/devices/atmega16/device.py | 284 -------- .../avr8/devices/atmega16/words/no-jtag.asm | 14 - amforth-6.5/avr8/devices/atmega16/words/no-wdt.asm | 22 - amforth-6.5/avr8/devices/atmega16/words/sleep.asm | 24 - 7 files changed, 1431 deletions(-) delete mode 100644 amforth-6.5/avr8/devices/atmega16/atmega16.frt delete mode 100644 amforth-6.5/avr8/devices/atmega16/device.asm delete mode 100644 amforth-6.5/avr8/devices/atmega16/device.inc delete mode 100644 amforth-6.5/avr8/devices/atmega16/device.py delete mode 100644 amforth-6.5/avr8/devices/atmega16/words/no-jtag.asm delete mode 100644 amforth-6.5/avr8/devices/atmega16/words/no-wdt.asm delete mode 100644 amforth-6.5/avr8/devices/atmega16/words/sleep.asm (limited to 'amforth-6.5/avr8/devices/atmega16') diff --git a/amforth-6.5/avr8/devices/atmega16/atmega16.frt b/amforth-6.5/avr8/devices/atmega16/atmega16.frt deleted file mode 100644 index 2f95ec1..0000000 --- a/amforth-6.5/avr8/devices/atmega16/atmega16.frt +++ /dev/null @@ -1,221 +0,0 @@ -\ Partname: ATmega16 -\ generated automatically - -\ TIMER_COUNTER_0 -&83 constant TCCR0 \ Timer/Counter Control Register - $80 constant TCCR0_FOC0 \ Force Output Compare - $40 constant TCCR0_WGM00 \ Waveform Generation Mode 0 - $30 constant TCCR0_COM0 \ Compare Match Output Modes - $08 constant TCCR0_WGM01 \ Waveform Generation Mode 1 - $07 constant TCCR0_CS0 \ Clock Selects -&82 constant TCNT0 \ Timer/Counter Register -&92 constant OCR0 \ Output Compare Register -&89 constant TIMSK \ Timer/Counter Interrupt Mask Register - $02 constant TIMSK_OCIE0 \ Timer/Counter0 Output Compare Match Interrupt register - $01 constant TIMSK_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable -&88 constant TIFR \ Timer/Counter Interrupt Flag register - $02 constant TIFR_OCF0 \ Output Compare Flag 0 - $01 constant TIFR_TOV0 \ Timer/Counter0 Overflow Flag -&80 constant SFIOR \ Special Function IO Register - $01 constant SFIOR_PSR10 \ Prescaler Reset Timer/Counter1 and Timer/Counter0 -\ TIMER_COUNTER_1 -&79 constant TCCR1A \ Timer/Counter1 Control Register A - $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits - $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits - $08 constant TCCR1A_FOC1A \ Force Output Compare 1A - $04 constant TCCR1A_FOC1B \ Force Output Compare 1B - $03 constant TCCR1A_WGM1 \ Waveform Generation Mode -&78 constant TCCR1B \ Timer/Counter1 Control Register B - $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler - $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select - $18 constant TCCR1B_WGM1 \ Waveform Generation Mode - $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1 -&76 constant TCNT1 \ Timer/Counter1 Bytes -&74 constant OCR1A \ Timer/Counter1 Output Compare Register Bytes -&72 constant OCR1B \ Timer/Counter1 Output Compare Register Bytes -&70 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes -\ EXTERNAL_INTERRUPT -&91 constant GICR \ General Interrupt Control Register - $C0 constant GICR_INT \ External Interrupt Request 1 Enable - $20 constant GICR_INT2 \ External Interrupt Request 2 Enable - $02 constant GICR_IVSEL \ Interrupt Vector Select - $01 constant GICR_IVCE \ Interrupt Vector Change Enable -&90 constant GIFR \ General Interrupt Flag Register - $C0 constant GIFR_INTF \ External Interrupt Flags - $20 constant GIFR_INTF2 \ External Interrupt Flag 2 -&85 constant MCUCR \ General Interrupt Control Register - $0C constant MCUCR_ISC1 \ Interrupt Sense Control 1 Bits - $03 constant MCUCR_ISC0 \ Interrupt Sense Control 0 Bits -&84 constant MCUCSR \ MCU Control And Status Register - $40 constant MCUCSR_ISC2 \ Interrupt Sense Control 2 -\ EEPROM -&62 constant EEAR \ EEPROM Address Register Bytes -&61 constant EEDR \ EEPROM Data Register -&60 constant EECR \ EEPROM Control Register - $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable - $04 constant EECR_EEMWE \ EEPROM Master Write Enable - $02 constant EECR_EEWE \ EEPROM Write Enable - $01 constant EECR_EERE \ EEPROM Read Enable -\ CPU -&95 constant SREG \ Status Register - $80 constant SREG_I \ Global Interrupt Enable - $40 constant SREG_T \ Bit Copy Storage - $20 constant SREG_H \ Half Carry Flag - $10 constant SREG_S \ Sign Bit - $08 constant SREG_V \ Two's Complement Overflow Flag - $04 constant SREG_N \ Negative Flag - $02 constant SREG_Z \ Zero Flag - $01 constant SREG_C \ Carry Flag -&93 constant SP \ Stack Pointer -&81 constant OSCCAL \ Oscillator Calibration Value -\ TIMER_COUNTER_2 -&69 constant TCCR2 \ Timer/Counter2 Control Register - $80 constant TCCR2_FOC2 \ Force Output Compare - $40 constant TCCR2_WGM20 \ Waveform Genration Mode - $30 constant TCCR2_COM2 \ Compare Output Mode bits - $08 constant TCCR2_WGM21 \ Waveform Generation Mode - $07 constant TCCR2_CS2 \ Clock Select bits -&68 constant TCNT2 \ Timer/Counter2 -&67 constant OCR2 \ Timer/Counter2 Output Compare Register -&66 constant ASSR \ Asynchronous Status Register - $08 constant ASSR_AS2 \ Asynchronous Timer/counter2 - $04 constant ASSR_TCN2UB \ Timer/Counter2 Update Busy - $02 constant ASSR_OCR2UB \ Output Compare Register2 Update Busy - $01 constant ASSR_TCR2UB \ Timer/counter Control Register2 Update Busy -\ SPI -&47 constant SPDR \ SPI Data Register -&46 constant SPSR \ SPI Status Register - $80 constant SPSR_SPIF \ SPI Interrupt Flag - $40 constant SPSR_WCOL \ Write Collision Flag - $01 constant SPSR_SPI2X \ Double SPI Speed Bit -&45 constant SPCR \ SPI Control Register - $80 constant SPCR_SPIE \ SPI Interrupt Enable - $40 constant SPCR_SPE \ SPI Enable - $20 constant SPCR_DORD \ Data Order - $10 constant SPCR_MSTR \ Master/Slave Select - $08 constant SPCR_CPOL \ Clock polarity - $04 constant SPCR_CPHA \ Clock Phase - $03 constant SPCR_SPR \ SPI Clock Rate Selects -\ USART -&44 constant UDR \ USART I/O Data Register -&43 constant UCSRA \ USART Control and Status Register A - $80 constant UCSRA_RXC \ USART Receive Complete - $40 constant UCSRA_TXC \ USART Transmitt Complete - $20 constant UCSRA_UDRE \ USART Data Register Empty - $10 constant UCSRA_FE \ Framing Error - $08 constant UCSRA_DOR \ Data overRun - $04 constant UCSRA_UPE \ Parity Error - $02 constant UCSRA_U2X \ Double the USART transmission speed - $01 constant UCSRA_MPCM \ Multi-processor Communication Mode -&42 constant UCSRB \ USART Control and Status Register B - $80 constant UCSRB_RXCIE \ RX Complete Interrupt Enable - $40 constant UCSRB_TXCIE \ TX Complete Interrupt Enable - $20 constant UCSRB_UDRIE \ USART Data register Empty Interrupt Enable - $10 constant UCSRB_RXEN \ Receiver Enable - $08 constant UCSRB_TXEN \ Transmitter Enable - $04 constant UCSRB_UCSZ2 \ Character Size - $02 constant UCSRB_RXB8 \ Receive Data Bit 8 - $01 constant UCSRB_TXB8 \ Transmit Data Bit 8 -&64 constant UCSRC \ USART Control and Status Register C - $80 constant UCSRC_URSEL \ Register Select - $40 constant UCSRC_UMSEL \ USART Mode Select - $30 constant UCSRC_UPM \ Parity Mode Bits - $08 constant UCSRC_USBS \ Stop Bit Select - $06 constant UCSRC_UCSZ \ Character Size - $01 constant UCSRC_UCPOL \ Clock Polarity -&64 constant UBRRH \ USART Baud Rate Register Hight Byte -&41 constant UBRRL \ USART Baud Rate Register Low Byte -\ TWI -&32 constant TWBR \ TWI Bit Rate register -&86 constant TWCR \ TWI Control Register - $80 constant TWCR_TWINT \ TWI Interrupt Flag - $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit - $20 constant TWCR_TWSTA \ TWI Start Condition Bit - $10 constant TWCR_TWSTO \ TWI Stop Condition Bit - $08 constant TWCR_TWWC \ TWI Write Collition Flag - $04 constant TWCR_TWEN \ TWI Enable Bit - $01 constant TWCR_TWIE \ TWI Interrupt Enable -&33 constant TWSR \ TWI Status Register - $F8 constant TWSR_TWS \ TWI Status - $03 constant TWSR_TWPS \ TWI Prescaler -&35 constant TWDR \ TWI Data register -&34 constant TWAR \ TWI (Slave) Address register - $FE constant TWAR_TWA \ TWI (Slave) Address register Bits - $01 constant TWAR_TWGCE \ TWI General Call Recognition Enable Bit -\ ANALOG_COMPARATOR -&40 constant ACSR \ Analog Comparator Control And Status Register - $80 constant ACSR_ACD \ Analog Comparator Disable - $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select - $20 constant ACSR_ACO \ Analog Compare Output - $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag - $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable - $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable - $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits -\ AD_CONVERTER -&39 constant ADMUX \ The ADC multiplexer Selection Register - $C0 constant ADMUX_REFS \ Reference Selection Bits - $20 constant ADMUX_ADLAR \ Left Adjust Result - $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits -&38 constant ADCSRA \ The ADC Control and Status register - $80 constant ADCSRA_ADEN \ ADC Enable - $40 constant ADCSRA_ADSC \ ADC Start Conversion - $20 constant ADCSRA_ADATE \ When this bit is written to one,the Timer/Counter2 prescaler will be reset.The bit will be cleared by hardware after the operation is performed.Writing a zero to this bit will have no effect.This bit will always be read as zero if Timer/Counter2 is clocked by the internal CPU clock.If this bit is written when Timer/Counter2 is operating in asynchronous mode,the bit will remain one until the prescaler has been reset. - $10 constant ADCSRA_ADIF \ ADC Interrupt Flag - $08 constant ADCSRA_ADIE \ ADC Interrupt Enable - $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits -&36 constant ADC \ ADC Data Register Bytes -\ JTAG -&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory - $FF constant OCDR_OCDR \ On-Chip Debug Register Bits -\ BOOT_LOAD -&87 constant SPMCSR \ Store Program Memory Control Register - $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable - $40 constant SPMCSR_RWWSB \ Read While Write Section Busy - $10 constant SPMCSR_RWWSRE \ Read While Write section read enable - $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set - $04 constant SPMCSR_PGWRT \ Page Write - $02 constant SPMCSR_PGERS \ Page Erase - $01 constant SPMCSR_SPMEN \ Store Program Memory Enable -\ PORTA -&59 constant PORTA \ Port A Data Register -&58 constant DDRA \ Port A Data Direction Register -&57 constant PINA \ Port A Input Pins -\ PORTB -&56 constant PORTB \ Port B Data Register -&55 constant DDRB \ Port B Data Direction Register -&54 constant PINB \ Port B Input Pins -\ PORTC -&53 constant PORTC \ Port C Data Register -&52 constant DDRC \ Port C Data Direction Register -&51 constant PINC \ Port C Input Pins -\ PORTD -&50 constant PORTD \ Port D Data Register -&49 constant DDRD \ Port D Data Direction Register -&48 constant PIND \ Port D Input Pins -\ WATCHDOG -&65 constant WDTCR \ Watchdog Timer Control Register - $10 constant WDTCR_WDTOE \ RW - $08 constant WDTCR_WDE \ Watch Dog Enable - $07 constant WDTCR_WDP \ Watch Dog Timer Prescaler bits - -\ Interrupts -&2 constant INT0Addr \ External Interrupt Request 0 -&4 constant INT1Addr \ External Interrupt Request 1 -&6 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match -&8 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow -&10 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event -&12 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A -&14 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B -&16 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow -&18 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow -&20 constant SPI_STCAddr \ Serial Transfer Complete -&22 constant USART_RXCAddr \ USART, Rx Complete -&24 constant USART_UDREAddr \ USART Data Register Empty -&26 constant USART_TXCAddr \ USART, Tx Complete -&28 constant ADCAddr \ ADC Conversion Complete -&30 constant EE_RDYAddr \ EEPROM Ready -&32 constant ANA_COMPAddr \ Analog Comparator -&34 constant TWIAddr \ 2-wire Serial Interface -&36 constant INT2Addr \ External Interrupt Request 2 -&38 constant TIMER0_COMPAddr \ Timer/Counter0 Compare Match -&40 constant SPM_RDYAddr \ Store Program Memory Ready diff --git a/amforth-6.5/avr8/devices/atmega16/device.asm b/amforth-6.5/avr8/devices/atmega16/device.asm deleted file mode 100644 index f0ec3af..0000000 --- a/amforth-6.5/avr8/devices/atmega16/device.asm +++ /dev/null @@ -1,101 +0,0 @@ -; Partname: ATmega16 -; generated automatically, do not edit - -.nolist - .include "m16def.inc" -.list - -.equ ramstart = 96 -.equ CELLSIZE = 2 -.macro readflashcell - lsl zl - rol zh - lpm @0, Z+ - lpm @1, Z+ -.endmacro -.macro writeflashcell - lsl zl - rol zh -.endmacro -.set WANT_TIMER_COUNTER_0 = 0 -.set WANT_TIMER_COUNTER_1 = 0 -.set WANT_EXTERNAL_INTERRUPT = 0 -.set WANT_EEPROM = 0 -.set WANT_CPU = 0 -.set WANT_TIMER_COUNTER_2 = 0 -.set WANT_SPI = 0 -.set WANT_USART = 0 -.set WANT_TWI = 0 -.set WANT_ANALOG_COMPARATOR = 0 -.set WANT_AD_CONVERTER = 0 -.set WANT_JTAG = 0 -.set WANT_BOOT_LOAD = 0 -.set WANT_PORTA = 0 -.set WANT_PORTB = 0 -.set WANT_PORTC = 0 -.set WANT_PORTD = 0 -.set WANT_WATCHDOG = 0 -.equ intvecsize = 2 ; please verify; flash size: 16384 bytes -.equ pclen = 2 ; please verify -.overlap -.org 2 - rcall isr ; External Interrupt Request 0 -.org 4 - rcall isr ; External Interrupt Request 1 -.org 6 - rcall isr ; Timer/Counter2 Compare Match -.org 8 - rcall isr ; Timer/Counter2 Overflow -.org 10 - rcall isr ; Timer/Counter1 Capture Event -.org 12 - rcall isr ; Timer/Counter1 Compare Match A -.org 14 - rcall isr ; Timer/Counter1 Compare Match B -.org 16 - rcall isr ; Timer/Counter1 Overflow -.org 18 - rcall isr ; Timer/Counter0 Overflow -.org 20 - rcall isr ; Serial Transfer Complete -.org 22 - rcall isr ; USART, Rx Complete -.org 24 - rcall isr ; USART Data Register Empty -.org 26 - rcall isr ; USART, Tx Complete -.org 28 - rcall isr ; ADC Conversion Complete -.org 30 - rcall isr ; EEPROM Ready -.org 32 - rcall isr ; Analog Comparator -.org 34 - rcall isr ; 2-wire Serial Interface -.org 36 - rcall isr ; External Interrupt Request 2 -.org 38 - rcall isr ; Timer/Counter0 Compare Match -.org 40 - rcall isr ; Store Program Memory Ready -.equ INTVECTORS = 21 -.nooverlap - -; compatability layer (maybe empty) -.equ EEPE = EEWE -.equ EEMPE = EEMWE - -; controller data area, environment query mcu-info -mcu_info: -mcu_ramsize: - .dw 1024 -mcu_eepromsize: - .dw 512 -mcu_maxdp: - .dw 14336 -mcu_numints: - .dw 21 -mcu_name: - .dw 8 - .db "ATmega16" -.set codestart=pc diff --git a/amforth-6.5/avr8/devices/atmega16/device.inc b/amforth-6.5/avr8/devices/atmega16/device.inc deleted file mode 100644 index 04e4766..0000000 --- a/amforth-6.5/avr8/devices/atmega16/device.inc +++ /dev/null @@ -1,765 +0,0 @@ -; Partname: ATmega16 -; generated automatically, no not edit - -.if WANT_TIMER_COUNTER_0 == 1 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter Control Register -VE_TCCR0: - .dw $ff05 - .db "TCCR0",0 - .dw VE_HEAD - .set VE_HEAD=VE_TCCR0 -XT_TCCR0: - .dw PFA_DOVARIABLE -PFA_TCCR0: - .dw 83 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter Register -VE_TCNT0: - .dw $ff05 - .db "TCNT0",0 - .dw VE_HEAD - .set VE_HEAD=VE_TCNT0 -XT_TCNT0: - .dw PFA_DOVARIABLE -PFA_TCNT0: - .dw 82 -; ( -- addr ) System Constant -; R( -- ) -; Output Compare Register -VE_OCR0: - .dw $ff04 - .db "OCR0" - .dw VE_HEAD - .set VE_HEAD=VE_OCR0 -XT_OCR0: - .dw PFA_DOVARIABLE -PFA_OCR0: - .dw 92 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter Interrupt Mask Register -VE_TIMSK: - .dw $ff05 - .db "TIMSK",0 - .dw VE_HEAD - .set VE_HEAD=VE_TIMSK -XT_TIMSK: - .dw PFA_DOVARIABLE -PFA_TIMSK: - .dw 89 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter Interrupt Flag register -VE_TIFR: - .dw $ff04 - .db "TIFR" - .dw VE_HEAD - .set VE_HEAD=VE_TIFR -XT_TIFR: - .dw PFA_DOVARIABLE -PFA_TIFR: - .dw 88 -; ( -- addr ) System Constant -; R( -- ) -; Special Function IO Register -VE_SFIOR: - .dw $ff05 - .db "SFIOR",0 - .dw VE_HEAD - .set VE_HEAD=VE_SFIOR -XT_SFIOR: - .dw PFA_DOVARIABLE -PFA_SFIOR: - .dw 80 - -.endif -.if WANT_TIMER_COUNTER_1 == 1 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter1 Control Register A -VE_TCCR1A: - .dw $ff06 - .db "TCCR1A" - .dw VE_HEAD - .set VE_HEAD=VE_TCCR1A -XT_TCCR1A: - .dw PFA_DOVARIABLE -PFA_TCCR1A: - .dw 79 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter1 Control Register B -VE_TCCR1B: - .dw $ff06 - .db "TCCR1B" - .dw VE_HEAD - .set VE_HEAD=VE_TCCR1B -XT_TCCR1B: - .dw PFA_DOVARIABLE -PFA_TCCR1B: - .dw 78 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter1 Bytes -VE_TCNT1: - .dw $ff05 - .db "TCNT1",0 - .dw VE_HEAD - .set VE_HEAD=VE_TCNT1 -XT_TCNT1: - .dw PFA_DOVARIABLE -PFA_TCNT1: - .dw 76 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter1 Output Compare Register Bytes -VE_OCR1A: - .dw $ff05 - .db "OCR1A",0 - .dw VE_HEAD - .set VE_HEAD=VE_OCR1A -XT_OCR1A: - .dw PFA_DOVARIABLE -PFA_OCR1A: - .dw 74 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter1 Output Compare Register Bytes -VE_OCR1B: - .dw $ff05 - .db "OCR1B",0 - .dw VE_HEAD - .set VE_HEAD=VE_OCR1B -XT_OCR1B: - .dw PFA_DOVARIABLE -PFA_OCR1B: - .dw 72 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter1 Input Capture Register Bytes -VE_ICR1: - .dw $ff04 - .db "ICR1" - .dw VE_HEAD - .set VE_HEAD=VE_ICR1 -XT_ICR1: - .dw PFA_DOVARIABLE -PFA_ICR1: - .dw 70 - -.endif -.if WANT_EXTERNAL_INTERRUPT == 1 -; ( -- addr ) System Constant -; R( -- ) -; General Interrupt Control Register -VE_GICR: - .dw $ff04 - .db "GICR" - .dw VE_HEAD - .set VE_HEAD=VE_GICR -XT_GICR: - .dw PFA_DOVARIABLE -PFA_GICR: - .dw 91 -; ( -- addr ) System Constant -; R( -- ) -; General Interrupt Flag Register -VE_GIFR: - .dw $ff04 - .db "GIFR" - .dw VE_HEAD - .set VE_HEAD=VE_GIFR -XT_GIFR: - .dw PFA_DOVARIABLE -PFA_GIFR: - .dw 90 -; ( -- addr ) System Constant -; R( -- ) -; General Interrupt Control Register -VE_MCUCR: - .dw $ff05 - .db "MCUCR",0 - .dw VE_HEAD - .set VE_HEAD=VE_MCUCR -XT_MCUCR: - .dw PFA_DOVARIABLE -PFA_MCUCR: - .dw 85 -; ( -- addr ) System Constant -; R( -- ) -; MCU Control And Status Register -VE_MCUCSR: - .dw $ff06 - .db "MCUCSR" - .dw VE_HEAD - .set VE_HEAD=VE_MCUCSR -XT_MCUCSR: - .dw PFA_DOVARIABLE -PFA_MCUCSR: - .dw 84 - -.endif -.if WANT_EEPROM == 1 -; ( -- addr ) System Constant -; R( -- ) -; EEPROM Address Register Bytes -VE_EEAR: - .dw $ff04 - .db "EEAR" - .dw VE_HEAD - .set VE_HEAD=VE_EEAR -XT_EEAR: - .dw PFA_DOVARIABLE -PFA_EEAR: - .dw 62 -; ( -- addr ) System Constant -; R( -- ) -; EEPROM Data Register -VE_EEDR: - .dw $ff04 - .db "EEDR" - .dw VE_HEAD - .set VE_HEAD=VE_EEDR -XT_EEDR: - .dw PFA_DOVARIABLE -PFA_EEDR: - .dw 61 -; ( -- addr ) System Constant -; R( -- ) -; EEPROM Control Register -VE_EECR: - .dw $ff04 - .db "EECR" - .dw VE_HEAD - .set VE_HEAD=VE_EECR -XT_EECR: - .dw PFA_DOVARIABLE -PFA_EECR: - .dw 60 - -.endif -.if WANT_CPU == 1 -; ( -- addr ) System Constant -; R( -- ) -; Status Register -VE_SREG: - .dw $ff04 - .db "SREG" - .dw VE_HEAD - .set VE_HEAD=VE_SREG -XT_SREG: - .dw PFA_DOVARIABLE -PFA_SREG: - .dw 95 -; ( -- addr ) System Constant -; R( -- ) -; Stack Pointer -VE_SP: - .dw $ff02 - .db "SP" - .dw VE_HEAD - .set VE_HEAD=VE_SP -XT_SP: - .dw PFA_DOVARIABLE -PFA_SP: - .dw 93 -; ( -- addr ) System Constant -; R( -- ) -; Oscillator Calibration Value -VE_OSCCAL: - .dw $ff06 - .db "OSCCAL" - .dw VE_HEAD - .set VE_HEAD=VE_OSCCAL -XT_OSCCAL: - .dw PFA_DOVARIABLE -PFA_OSCCAL: - .dw 81 - -.endif -.if WANT_TIMER_COUNTER_2 == 1 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter2 Control Register -VE_TCCR2: - .dw $ff05 - .db "TCCR2",0 - .dw VE_HEAD - .set VE_HEAD=VE_TCCR2 -XT_TCCR2: - .dw PFA_DOVARIABLE -PFA_TCCR2: - .dw 69 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter2 -VE_TCNT2: - .dw $ff05 - .db "TCNT2",0 - .dw VE_HEAD - .set VE_HEAD=VE_TCNT2 -XT_TCNT2: - .dw PFA_DOVARIABLE -PFA_TCNT2: - .dw 68 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter2 Output Compare Register -VE_OCR2: - .dw $ff04 - .db "OCR2" - .dw VE_HEAD - .set VE_HEAD=VE_OCR2 -XT_OCR2: - .dw PFA_DOVARIABLE -PFA_OCR2: - .dw 67 -; ( -- addr ) System Constant -; R( -- ) -; Asynchronous Status Register -VE_ASSR: - .dw $ff04 - .db "ASSR" - .dw VE_HEAD - .set VE_HEAD=VE_ASSR -XT_ASSR: - .dw PFA_DOVARIABLE -PFA_ASSR: - .dw 66 - -.endif -.if WANT_SPI == 1 -; ( -- addr ) System Constant -; R( -- ) -; SPI Data Register -VE_SPDR: - .dw $ff04 - .db "SPDR" - .dw VE_HEAD - .set VE_HEAD=VE_SPDR -XT_SPDR: - .dw PFA_DOVARIABLE -PFA_SPDR: - .dw 47 -; ( -- addr ) System Constant -; R( -- ) -; SPI Status Register -VE_SPSR: - .dw $ff04 - .db "SPSR" - .dw VE_HEAD - .set VE_HEAD=VE_SPSR -XT_SPSR: - .dw PFA_DOVARIABLE -PFA_SPSR: - .dw 46 -; ( -- addr ) System Constant -; R( -- ) -; SPI Control Register -VE_SPCR: - .dw $ff04 - .db "SPCR" - .dw VE_HEAD - .set VE_HEAD=VE_SPCR -XT_SPCR: - .dw PFA_DOVARIABLE -PFA_SPCR: - .dw 45 - -.endif -.if WANT_USART == 1 -; ( -- addr ) System Constant -; R( -- ) -; USART I/O Data Register -VE_UDR: - .dw $ff03 - .db "UDR",0 - .dw VE_HEAD - .set VE_HEAD=VE_UDR -XT_UDR: - .dw PFA_DOVARIABLE -PFA_UDR: - .dw 44 -; ( -- addr ) System Constant -; R( -- ) -; USART Control and Status Register A -VE_UCSRA: - .dw $ff05 - .db "UCSRA",0 - .dw VE_HEAD - .set VE_HEAD=VE_UCSRA -XT_UCSRA: - .dw PFA_DOVARIABLE -PFA_UCSRA: - .dw 43 -; ( -- addr ) System Constant -; R( -- ) -; USART Control and Status Register B -VE_UCSRB: - .dw $ff05 - .db "UCSRB",0 - .dw VE_HEAD - .set VE_HEAD=VE_UCSRB -XT_UCSRB: - .dw PFA_DOVARIABLE -PFA_UCSRB: - .dw 42 -; ( -- addr ) System Constant -; R( -- ) -; USART Control and Status Register C -VE_UCSRC: - .dw $ff05 - .db "UCSRC",0 - .dw VE_HEAD - .set VE_HEAD=VE_UCSRC -XT_UCSRC: - .dw PFA_DOVARIABLE -PFA_UCSRC: - .dw 64 -; ( -- addr ) System Constant -; R( -- ) -; USART Baud Rate Register Hight Byte -VE_UBRRH: - .dw $ff05 - .db "UBRRH",0 - .dw VE_HEAD - .set VE_HEAD=VE_UBRRH -XT_UBRRH: - .dw PFA_DOVARIABLE -PFA_UBRRH: - .dw 64 -; ( -- addr ) System Constant -; R( -- ) -; USART Baud Rate Register Low Byte -VE_UBRRL: - .dw $ff05 - .db "UBRRL",0 - .dw VE_HEAD - .set VE_HEAD=VE_UBRRL -XT_UBRRL: - .dw PFA_DOVARIABLE -PFA_UBRRL: - .dw 41 - -.endif -.if WANT_TWI == 1 -; ( -- addr ) System Constant -; R( -- ) -; TWI Bit Rate register -VE_TWBR: - .dw $ff04 - .db "TWBR" - .dw VE_HEAD - .set VE_HEAD=VE_TWBR -XT_TWBR: - .dw PFA_DOVARIABLE -PFA_TWBR: - .dw 32 -; ( -- addr ) System Constant -; R( -- ) -; TWI Control Register -VE_TWCR: - .dw $ff04 - .db "TWCR" - .dw VE_HEAD - .set VE_HEAD=VE_TWCR -XT_TWCR: - .dw PFA_DOVARIABLE -PFA_TWCR: - .dw 86 -; ( -- addr ) System Constant -; R( -- ) -; TWI Status Register -VE_TWSR: - .dw $ff04 - .db "TWSR" - .dw VE_HEAD - .set VE_HEAD=VE_TWSR -XT_TWSR: - .dw PFA_DOVARIABLE -PFA_TWSR: - .dw 33 -; ( -- addr ) System Constant -; R( -- ) -; TWI Data register -VE_TWDR: - .dw $ff04 - .db "TWDR" - .dw VE_HEAD - .set VE_HEAD=VE_TWDR -XT_TWDR: - .dw PFA_DOVARIABLE -PFA_TWDR: - .dw 35 -; ( -- addr ) System Constant -; R( -- ) -; TWI (Slave) Address register -VE_TWAR: - .dw $ff04 - .db "TWAR" - .dw VE_HEAD - .set VE_HEAD=VE_TWAR -XT_TWAR: - .dw PFA_DOVARIABLE -PFA_TWAR: - .dw 34 - -.endif -.if WANT_ANALOG_COMPARATOR == 1 -; ( -- addr ) System Constant -; R( -- ) -; Analog Comparator Control And Status Register -VE_ACSR: - .dw $ff04 - .db "ACSR" - .dw VE_HEAD - .set VE_HEAD=VE_ACSR -XT_ACSR: - .dw PFA_DOVARIABLE -PFA_ACSR: - .dw 40 - -.endif -.if WANT_AD_CONVERTER == 1 -; ( -- addr ) System Constant -; R( -- ) -; The ADC multiplexer Selection Register -VE_ADMUX: - .dw $ff05 - .db "ADMUX",0 - .dw VE_HEAD - .set VE_HEAD=VE_ADMUX -XT_ADMUX: - .dw PFA_DOVARIABLE -PFA_ADMUX: - .dw 39 -; ( -- addr ) System Constant -; R( -- ) -; The ADC Control and Status register -VE_ADCSRA: - .dw $ff06 - .db "ADCSRA" - .dw VE_HEAD - .set VE_HEAD=VE_ADCSRA -XT_ADCSRA: - .dw PFA_DOVARIABLE -PFA_ADCSRA: - .dw 38 -; ( -- addr ) System Constant -; R( -- ) -; ADC Data Register Bytes -VE_ADC: - .dw $ff03 - .db "ADC",0 - .dw VE_HEAD - .set VE_HEAD=VE_ADC -XT_ADC: - .dw PFA_DOVARIABLE -PFA_ADC: - .dw 36 - -.endif -.if WANT_JTAG == 1 -; ( -- addr ) System Constant -; R( -- ) -; On-Chip Debug Related Register in I/O Memory -VE_OCDR: - .dw $ff04 - .db "OCDR" - .dw VE_HEAD - .set VE_HEAD=VE_OCDR -XT_OCDR: - .dw PFA_DOVARIABLE -PFA_OCDR: - .dw 81 - -.endif -.if WANT_BOOT_LOAD == 1 -; ( -- addr ) System Constant -; R( -- ) -; Store Program Memory Control Register -VE_SPMCSR: - .dw $ff06 - .db "SPMCSR" - .dw VE_HEAD - .set VE_HEAD=VE_SPMCSR -XT_SPMCSR: - .dw PFA_DOVARIABLE -PFA_SPMCSR: - .dw 87 - -.endif -.if WANT_PORTA == 1 -; ( -- addr ) System Constant -; R( -- ) -; Port A Data Register -VE_PORTA: - .dw $ff05 - .db "PORTA",0 - .dw VE_HEAD - .set VE_HEAD=VE_PORTA -XT_PORTA: - .dw PFA_DOVARIABLE -PFA_PORTA: - .dw 59 -; ( -- addr ) System Constant -; R( -- ) -; Port A Data Direction Register -VE_DDRA: - .dw $ff04 - .db "DDRA" - .dw VE_HEAD - .set VE_HEAD=VE_DDRA -XT_DDRA: - .dw PFA_DOVARIABLE -PFA_DDRA: - .dw 58 -; ( -- addr ) System Constant -; R( -- ) -; Port A Input Pins -VE_PINA: - .dw $ff04 - .db "PINA" - .dw VE_HEAD - .set VE_HEAD=VE_PINA -XT_PINA: - .dw PFA_DOVARIABLE -PFA_PINA: - .dw 57 - -.endif -.if WANT_PORTB == 1 -; ( -- addr ) System Constant -; R( -- ) -; Port B Data Register -VE_PORTB: - .dw $ff05 - .db "PORTB",0 - .dw VE_HEAD - .set VE_HEAD=VE_PORTB -XT_PORTB: - .dw PFA_DOVARIABLE -PFA_PORTB: - .dw 56 -; ( -- addr ) System Constant -; R( -- ) -; Port B Data Direction Register -VE_DDRB: - .dw $ff04 - .db "DDRB" - .dw VE_HEAD - .set VE_HEAD=VE_DDRB -XT_DDRB: - .dw PFA_DOVARIABLE -PFA_DDRB: - .dw 55 -; ( -- addr ) System Constant -; R( -- ) -; Port B Input Pins -VE_PINB: - .dw $ff04 - .db "PINB" - .dw VE_HEAD - .set VE_HEAD=VE_PINB -XT_PINB: - .dw PFA_DOVARIABLE -PFA_PINB: - .dw 54 - -.endif -.if WANT_PORTC == 1 -; ( -- addr ) System Constant -; R( -- ) -; Port C Data Register -VE_PORTC: - .dw $ff05 - .db "PORTC",0 - .dw VE_HEAD - .set VE_HEAD=VE_PORTC -XT_PORTC: - .dw PFA_DOVARIABLE -PFA_PORTC: - .dw 53 -; ( -- addr ) System Constant -; R( -- ) -; Port C Data Direction Register -VE_DDRC: - .dw $ff04 - .db "DDRC" - .dw VE_HEAD - .set VE_HEAD=VE_DDRC -XT_DDRC: - .dw PFA_DOVARIABLE -PFA_DDRC: - .dw 52 -; ( -- addr ) System Constant -; R( -- ) -; Port C Input Pins -VE_PINC: - .dw $ff04 - .db "PINC" - .dw VE_HEAD - .set VE_HEAD=VE_PINC -XT_PINC: - .dw PFA_DOVARIABLE -PFA_PINC: - .dw 51 - -.endif -.if WANT_PORTD == 1 -; ( -- addr ) System Constant -; R( -- ) -; Port D Data Register -VE_PORTD: - .dw $ff05 - .db "PORTD",0 - .dw VE_HEAD - .set VE_HEAD=VE_PORTD -XT_PORTD: - .dw PFA_DOVARIABLE -PFA_PORTD: - .dw 50 -; ( -- addr ) System Constant -; R( -- ) -; Port D Data Direction Register -VE_DDRD: - .dw $ff04 - .db "DDRD" - .dw VE_HEAD - .set VE_HEAD=VE_DDRD -XT_DDRD: - .dw PFA_DOVARIABLE -PFA_DDRD: - .dw 49 -; ( -- addr ) System Constant -; R( -- ) -; Port D Input Pins -VE_PIND: - .dw $ff04 - .db "PIND" - .dw VE_HEAD - .set VE_HEAD=VE_PIND -XT_PIND: - .dw PFA_DOVARIABLE -PFA_PIND: - .dw 48 - -.endif -.if WANT_WATCHDOG == 1 -; ( -- addr ) System Constant -; R( -- ) -; Watchdog Timer Control Register -VE_WDTCR: - .dw $ff05 - .db "WDTCR",0 - .dw VE_HEAD - .set VE_HEAD=VE_WDTCR -XT_WDTCR: - .dw PFA_DOVARIABLE -PFA_WDTCR: - .dw 65 - -.endif diff --git a/amforth-6.5/avr8/devices/atmega16/device.py b/amforth-6.5/avr8/devices/atmega16/device.py deleted file mode 100644 index cd9f581..0000000 --- a/amforth-6.5/avr8/devices/atmega16/device.py +++ /dev/null @@ -1,284 +0,0 @@ -# Generated Automatically - -# Partname ATmega16 - -MCUREGS = { -# Interrupt Vectors - 'INT0Addr' : '#2', # External Interrupt Request 0 - 'INT1Addr' : '#4', # External Interrupt Request 1 - 'TIMER2_COMPAddr' : '#6', # Timer/Counter2 Compare Match - 'TIMER2_OVFAddr' : '#8', # Timer/Counter2 Overflow - 'TIMER1_CAPTAddr' : '#10', # Timer/Counter1 Capture Event - 'TIMER1_COMPAAddr' : '#12', # Timer/Counter1 Compare Match A - 'TIMER1_COMPBAddr' : '#14', # Timer/Counter1 Compare Match B - 'TIMER1_OVFAddr' : '#16', # Timer/Counter1 Overflow - 'TIMER0_OVFAddr' : '#18', # Timer/Counter0 Overflow - 'SPI_STCAddr' : '#20', # Serial Transfer Complete - 'USART_RXCAddr' : '#22', # USART, Rx Complete - 'USART_UDREAddr' : '#24', # USART Data Register Empty - 'USART_TXCAddr' : '#26', # USART, Tx Complete - 'ADCAddr' : '#28', # ADC Conversion Complete - 'EE_RDYAddr' : '#30', # EEPROM Ready - 'ANA_COMPAddr' : '#32', # Analog Comparator - 'TWIAddr' : '#34', # 2-wire Serial Interface - 'INT2Addr' : '#36', # External Interrupt Request 2 - 'TIMER0_COMPAddr' : '#38', # Timer/Counter0 Compare Match - 'SPM_RDYAddr' : '#40', # Store Program Memory Ready - -# Module TIMER_COUNTER_0 - 'TCCR0' : '$53', # Timer/Counter Control Register - 'TCCR0_FOC0': '$80', # Force Output Compare - 'TCCR0_WGM00': '$40', # Waveform Generation Mode 0 - 'TCCR0_COM0': '$30', # Compare Match Output Modes - 'TCCR0_WGM01': '$8', # Waveform Generation Mode 1 - 'TCCR0_CS0': '$7', # Clock Selects - 'TCNT0' : '$52', # Timer/Counter Register - 'OCR0' : '$5c', # Output Compare Register - 'TIMSK' : '$59', # Timer/Counter Interrupt Mask R - 'TIMSK_OCIE0': '$2', # Timer/Counter0 Output Compare - 'TIMSK_TOIE0': '$1', # Timer/Counter0 Overflow Interr - 'TIFR' : '$58', # Timer/Counter Interrupt Flag r - 'TIFR_OCF0': '$2', # Output Compare Flag 0 - 'TIFR_TOV0': '$1', # Timer/Counter0 Overflow Flag - 'SFIOR' : '$50', # Special Function IO Register - 'SFIOR_PSR10': '$1', # Prescaler Reset Timer/Counter1 - -# Module TIMER_COUNTER_1 - 'TIMSK' : '$59', # Timer/Counter Interrupt Mask R - 'TIMSK_TICIE1': '$20', # Timer/Counter1 Input Capture I - 'TIMSK_OCIE1A': '$10', # Timer/Counter1 Output CompareA - 'TIMSK_OCIE1B': '$8', # Timer/Counter1 Output CompareB - 'TIMSK_TOIE1': '$4', # Timer/Counter1 Overflow Interr - 'TIFR' : '$58', # Timer/Counter Interrupt Flag r - 'TIFR_ICF1': '$20', # Input Capture Flag 1 - 'TIFR_OCF1A': '$10', # Output Compare Flag 1A - 'TIFR_OCF1B': '$8', # Output Compare Flag 1B - 'TIFR_TOV1': '$4', # Timer/Counter1 Overflow Flag - 'TCCR1A' : '$4f', # Timer/Counter1 Control Registe - 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits - 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits - 'TCCR1A_FOC1A': '$8', # Force Output Compare 1A - 'TCCR1A_FOC1B': '$4', # Force Output Compare 1B - 'TCCR1A_WGM1': '$3', # Waveform Generation Mode - 'TCCR1B' : '$4e', # Timer/Counter1 Control Registe - 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler - 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select - 'TCCR1B_WGM1': '$18', # Waveform Generation Mode - 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun - 'TCNT1' : '$4c', # Timer/Counter1 Bytes - 'OCR1A' : '$4a', # Timer/Counter1 Output Compare - 'OCR1B' : '$48', # Timer/Counter1 Output Compare - 'ICR1' : '$46', # Timer/Counter1 Input Capture R - -# Module EXTERNAL_INTERRUPT - 'GICR' : '$5b', # General Interrupt Control Regi - 'GICR_INT': '$c0', # External Interrupt Request 1 E - 'GICR_INT2': '$20', # External Interrupt Request 2 E - 'GICR_IVSEL': '$2', # Interrupt Vector Select - 'GICR_IVCE': '$1', # Interrupt Vector Change Enable - 'GIFR' : '$5a', # General Interrupt Flag Registe - 'GIFR_INTF': '$c0', # External Interrupt Flags - 'GIFR_INTF2': '$20', # External Interrupt Flag 2 - 'MCUCR' : '$55', # General Interrupt Control Regi - 'MCUCR_ISC1': '$c', # Interrupt Sense Control 1 Bits - 'MCUCR_ISC0': '$3', # Interrupt Sense Control 0 Bits - 'MCUCSR' : '$54', # MCU Control And Status Registe - 'MCUCSR_ISC2': '$40', # Interrupt Sense Control 2 - -# Module EEPROM - 'EEAR' : '$3e', # EEPROM Address Register Bytes - 'EEDR' : '$3d', # EEPROM Data Register - 'EECR' : '$3c', # EEPROM Control Register - 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable - 'EECR_EEMWE': '$4', # EEPROM Master Write Enable - 'EECR_EEWE': '$2', # EEPROM Write Enable - 'EECR_EERE': '$1', # EEPROM Read Enable - -# Module CPU - 'SREG' : '$5f', # Status Register - 'SREG_I': '$80', # Global Interrupt Enable - 'SREG_T': '$40', # Bit Copy Storage - 'SREG_H': '$20', # Half Carry Flag - 'SREG_S': '$10', # Sign Bit - 'SREG_V': '$8', # Two's Complement Overflow Flag - 'SREG_N': '$4', # Negative Flag - 'SREG_Z': '$2', # Zero Flag - 'SREG_C': '$1', # Carry Flag - 'SP' : '$5d', # Stack Pointer - 'MCUCR' : '$55', # MCU Control Register - 'MCUCR_SM': '$b0', # Sleep Mode Select - 'MCUCR_SE': '$40', # Sleep Enable - 'MCUCR_ISC1': '$c', # Interrupt Sense Control 1 Bits - 'MCUCR_ISC0': '$3', # Interrupt Sense Control 0 Bits - 'MCUCSR' : '$54', # MCU Control And Status Registe - 'MCUCSR_JTD': '$80', # JTAG Interface Disable - 'MCUCSR_JTRF': '$10', # JTAG Reset Flag - 'MCUCSR_WDRF': '$8', # Watchdog Reset Flag - 'MCUCSR_BORF': '$4', # Brown-out Reset Flag - 'MCUCSR_EXTRF': '$2', # External Reset Flag - 'MCUCSR_PORF': '$1', # Power-on reset flag - 'OSCCAL' : '$51', # Oscillator Calibration Value - 'SFIOR' : '$50', # Special function I/O register - 'SFIOR_PUD': '$4', # Pull-up Disable - 'SFIOR_PSR2': '$2', # Prescaler reset - 'SFIOR_PSR10': '$1', # Prescaler reset - -# Module TIMER_COUNTER_2 - 'TIMSK' : '$59', # Timer/Counter Interrupt Mask r - 'TIMSK_OCIE2': '$80', # Timer/Counter2 Output Compare - 'TIMSK_TOIE2': '$40', # Timer/Counter2 Overflow Interr - 'TIFR' : '$58', # Timer/Counter Interrupt Flag R - 'TIFR_OCF2': '$80', # Output Compare Flag 2 - 'TIFR_TOV2': '$40', # Timer/Counter2 Overflow Flag - 'TCCR2' : '$45', # Timer/Counter2 Control Registe - 'TCCR2_FOC2': '$80', # Force Output Compare - 'TCCR2_WGM20': '$40', # Waveform Genration Mode - 'TCCR2_COM2': '$30', # Compare Output Mode bits - 'TCCR2_WGM21': '$8', # Waveform Generation Mode - 'TCCR2_CS2': '$7', # Clock Select bits - 'TCNT2' : '$44', # Timer/Counter2 - 'OCR2' : '$43', # Timer/Counter2 Output Compare - 'ASSR' : '$42', # Asynchronous Status Register - 'ASSR_AS2': '$8', # Asynchronous Timer/counter2 - 'ASSR_TCN2UB': '$4', # Timer/Counter2 Update Busy - 'ASSR_OCR2UB': '$2', # Output Compare Register2 Updat - 'ASSR_TCR2UB': '$1', # Timer/counter Control Register - 'SFIOR' : '$50', # Special Function IO Register - 'SFIOR_PSR2': '$2', # Prescaler Reset Timer/Counter2 - -# Module SPI - 'SPDR' : '$2f', # SPI Data Register - 'SPSR' : '$2e', # SPI Status Register - 'SPSR_SPIF': '$80', # SPI Interrupt Flag - 'SPSR_WCOL': '$40', # Write Collision Flag - 'SPSR_SPI2X': '$1', # Double SPI Speed Bit - 'SPCR' : '$2d', # SPI Control Register - 'SPCR_SPIE': '$80', # SPI Interrupt Enable - 'SPCR_SPE': '$40', # SPI Enable - 'SPCR_DORD': '$20', # Data Order - 'SPCR_MSTR': '$10', # Master/Slave Select - 'SPCR_CPOL': '$8', # Clock polarity - 'SPCR_CPHA': '$4', # Clock Phase - 'SPCR_SPR': '$3', # SPI Clock Rate Selects - -# Module USART - 'UDR' : '$2c', # USART I/O Data Register - 'UCSRA' : '$2b', # USART Control and Status Regis - 'UCSRA_RXC': '$80', # USART Receive Complete - 'UCSRA_TXC': '$40', # USART Transmitt Complete - 'UCSRA_UDRE': '$20', # USART Data Register Empty - 'UCSRA_FE': '$10', # Framing Error - 'UCSRA_DOR': '$8', # Data overRun - 'UCSRA_UPE': '$4', # Parity Error - 'UCSRA_U2X': '$2', # Double the USART transmission - 'UCSRA_MPCM': '$1', # Multi-processor Communication - 'UCSRB' : '$2a', # USART Control and Status Regis - 'UCSRB_RXCIE': '$80', # RX Complete Interrupt Enable - 'UCSRB_TXCIE': '$40', # TX Complete Interrupt Enable - 'UCSRB_UDRIE': '$20', # USART Data register Empty Inte - 'UCSRB_RXEN': '$10', # Receiver Enable - 'UCSRB_TXEN': '$8', # Transmitter Enable - 'UCSRB_UCSZ2': '$4', # Character Size - 'UCSRB_RXB8': '$2', # Receive Data Bit 8 - 'UCSRB_TXB8': '$1', # Transmit Data Bit 8 - 'UCSRC' : '$40', # USART Control and Status Regis - 'UCSRC_URSEL': '$80', # Register Select - 'UCSRC_UMSEL': '$40', # USART Mode Select - 'UCSRC_UPM': '$30', # Parity Mode Bits - 'UCSRC_USBS': '$8', # Stop Bit Select - 'UCSRC_UCSZ': '$6', # Character Size - 'UCSRC_UCPOL': '$1', # Clock Polarity - 'UBRRH' : '$40', # USART Baud Rate Register Hight - 'UBRRL' : '$29', # USART Baud Rate Register Low B - -# Module TWI - 'TWBR' : '$20', # TWI Bit Rate register - 'TWCR' : '$56', # TWI Control Register - 'TWCR_TWINT': '$80', # TWI Interrupt Flag - 'TWCR_TWEA': '$40', # TWI Enable Acknowledge Bit - 'TWCR_TWSTA': '$20', # TWI Start Condition Bit - 'TWCR_TWSTO': '$10', # TWI Stop Condition Bit - 'TWCR_TWWC': '$8', # TWI Write Collition Flag - 'TWCR_TWEN': '$4', # TWI Enable Bit - 'TWCR_TWIE': '$1', # TWI Interrupt Enable - 'TWSR' : '$21', # TWI Status Register - 'TWSR_TWS': '$f8', # TWI Status - 'TWSR_TWPS': '$3', # TWI Prescaler - 'TWDR' : '$23', # TWI Data register - 'TWAR' : '$22', # TWI (Slave) Address register - 'TWAR_TWA': '$fe', # TWI (Slave) Address register B - 'TWAR_TWGCE': '$1', # TWI General Call Recognition E - -# Module ANALOG_COMPARATOR - 'SFIOR' : '$50', # Special Function IO Register - 'SFIOR_ACME': '$8', # Analog Comparator Multiplexer - 'ACSR' : '$28', # Analog Comparator Control And - 'ACSR_ACD': '$80', # Analog Comparator Disable - 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele - 'ACSR_ACO': '$20', # Analog Compare Output - 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl - 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En - 'ACSR_ACIC': '$4', # Analog Comparator Input Captur - 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo - -# Module AD_CONVERTER - 'ADMUX' : '$27', # The ADC multiplexer Selection - 'ADMUX_REFS': '$c0', # Reference Selection Bits - 'ADMUX_ADLAR': '$20', # Left Adjust Result - 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select - 'ADCSRA' : '$26', # The ADC Control and Status reg - 'ADCSRA_ADEN': '$80', # ADC Enable - 'ADCSRA_ADSC': '$40', # ADC Start Conversion - 'ADCSRA_ADATE': '$20', # When this bit is written to on - 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag - 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable - 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits - 'ADC' : '$24', # ADC Data Register Bytes - 'SFIOR' : '$50', # Special Function IO Register - 'SFIOR_ADTS': '$e0', # ADC Auto Trigger Sources - -# Module JTAG - 'OCDR' : '$51', # On-Chip Debug Related Register - 'OCDR_OCDR': '$ff', # On-Chip Debug Register Bits - 'MCUCSR' : '$54', # MCU Control And Status Registe - 'MCUCSR_JTD': '$80', # JTAG Interface Disable - 'MCUCSR_JTRF': '$10', # JTAG Reset Flag - -# Module BOOT_LOAD - 'SPMCSR' : '$57', # Store Program Memory Control R - 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable - 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy - 'SPMCSR_RWWSRE': '$10', # Read While Write section read - 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set - 'SPMCSR_PGWRT': '$4', # Page Write - 'SPMCSR_PGERS': '$2', # Page Erase - 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable - -# Module PORTA - 'PORTA' : '$3b', # Port A Data Register - 'DDRA' : '$3a', # Port A Data Direction Register - 'PINA' : '$39', # Port A Input Pins - -# Module PORTB - 'PORTB' : '$38', # Port B Data Register - 'DDRB' : '$37', # Port B Data Direction Register - 'PINB' : '$36', # Port B Input Pins - -# Module PORTC - 'PORTC' : '$35', # Port C Data Register - 'DDRC' : '$34', # Port C Data Direction Register - 'PINC' : '$33', # Port C Input Pins - -# Module PORTD - 'PORTD' : '$32', # Port D Data Register - 'DDRD' : '$31', # Port D Data Direction Register - 'PIND' : '$30', # Port D Input Pins - -# Module WATCHDOG - 'WDTCR' : '$41', # Watchdog Timer Control Registe - 'WDTCR_WDTOE': '$10', # RW - 'WDTCR_WDE': '$8', # Watch Dog Enable - 'WDTCR_WDP': '$7', # Watch Dog Timer Prescaler bits - - '__amforth_dummy':'0' -} diff --git a/amforth-6.5/avr8/devices/atmega16/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega16/words/no-jtag.asm deleted file mode 100644 index 352a4bb..0000000 --- a/amforth-6.5/avr8/devices/atmega16/words/no-jtag.asm +++ /dev/null @@ -1,14 +0,0 @@ -; ( -- ) -; ( -- ) -; MCU -; disable jtag at runtime -VE_NOJTAG: - .dw $FF05 - .db "-jtag",0 - .dw VE_HEAD - .set VE_HEAD = VE_NOJTAG -XT_NOJTAG: - .dw PFA_NOJTAG -PFA_NOJTAG: - - jmp_ DO_NEXT diff --git a/amforth-6.5/avr8/devices/atmega16/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega16/words/no-wdt.asm deleted file mode 100644 index 4a12261..0000000 --- a/amforth-6.5/avr8/devices/atmega16/words/no-wdt.asm +++ /dev/null @@ -1,22 +0,0 @@ -; ( -- ) -; MCU -; disable watch dog timer at runtime -VE_NOWDT: - .dw $ff04 - .db "-wdt" - .dw VE_HEAD - .set VE_HEAD = VE_NOWDT -XT_NOWDT: - .dw PFA_NOWDT -PFA_NOWDT: - -; Reset WDT - wdr -; Write logical one to WDTOE and WDE - in_ temp1, WDTCR - ori temp1, (1<