From 67d25d837ac55f28a366c0a3b262e439a6e75fc3 Mon Sep 17 00:00:00 2001 From: Dimitri Sokolyuk Date: Sat, 19 Aug 2017 12:15:28 +0200 Subject: Add AmForth --- .../avr8/devices/atmega256rfr2/blocks/BOOT_LOAD.frt | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) create mode 100644 amforth-6.5/avr8/devices/atmega256rfr2/blocks/BOOT_LOAD.frt (limited to 'amforth-6.5/avr8/devices/atmega256rfr2/blocks/BOOT_LOAD.frt') diff --git a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/BOOT_LOAD.frt b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/BOOT_LOAD.frt new file mode 100644 index 0000000..d38b796 --- /dev/null +++ b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/BOOT_LOAD.frt @@ -0,0 +1,21 @@ +\ Generated automatically for atmega256rfr2 +\ #require bitnames.frt + +\ BOOT_LOAD +$57 constant SPMCSR \ Store Program Memory Control R + $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable + 57 $80 bitmask: SPMCSR.SPMIE \ SPM Interrupt Enable + $40 constant SPMCSR_RWWSB \ Read While Write Section Busy + 57 $40 bitmask: SPMCSR.RWWSB \ Read While Write Section Busy + $20 constant SPMCSR_SIGRD \ Signature Row Read + 57 $20 bitmask: SPMCSR.SIGRD \ Signature Row Read + $10 constant SPMCSR_RWWSRE \ Read While Write Section Read + 57 $10 bitmask: SPMCSR.RWWSRE \ Read While Write Section Read + $8 constant SPMCSR_BLBSET \ Boot Lock Bit Set + 57 $8 bitmask: SPMCSR.BLBSET \ Boot Lock Bit Set + $4 constant SPMCSR_PGWRT \ Page Write + 57 $4 bitmask: SPMCSR.PGWRT \ Page Write + $2 constant SPMCSR_PGERS \ Page Erase + 57 $2 bitmask: SPMCSR.PGERS \ Page Erase + $1 constant SPMCSR_SPMEN \ Store Program Memory Enable + 57 $1 bitmask: SPMCSR.SPMEN \ Store Program Memory Enable -- cgit v1.2.3