From 67d25d837ac55f28a366c0a3b262e439a6e75fc3 Mon Sep 17 00:00:00 2001 From: Dimitri Sokolyuk Date: Sat, 19 Aug 2017 12:15:28 +0200 Subject: Add AmForth --- .../devices/atmega256rfr2/blocks/AD_CONVERTER.frt | 79 + .../atmega256rfr2/blocks/ANALOG_COMPARATOR.frt | 27 + .../devices/atmega256rfr2/blocks/BOOT_LOAD.frt | 21 + .../avr8/devices/atmega256rfr2/blocks/CPU.frt | 129 ++ .../avr8/devices/atmega256rfr2/blocks/EEPROM.frt | 19 + .../atmega256rfr2/blocks/EXTERNAL_INTERRUPT.frt | 45 + .../avr8/devices/atmega256rfr2/blocks/FLASH.frt | 16 + .../avr8/devices/atmega256rfr2/blocks/JTAG.frt | 13 + .../avr8/devices/atmega256rfr2/blocks/PORTA.frt | 7 + .../avr8/devices/atmega256rfr2/blocks/PORTB.frt | 7 + .../avr8/devices/atmega256rfr2/blocks/PORTC.frt | 7 + .../avr8/devices/atmega256rfr2/blocks/PORTD.frt | 7 + .../avr8/devices/atmega256rfr2/blocks/PORTE.frt | 7 + .../avr8/devices/atmega256rfr2/blocks/PORTF.frt | 7 + .../avr8/devices/atmega256rfr2/blocks/PORTG.frt | 7 + .../avr8/devices/atmega256rfr2/blocks/PWRCTRL.frt | 81 + .../avr8/devices/atmega256rfr2/blocks/SPI.frt | 29 + .../avr8/devices/atmega256rfr2/blocks/SYMCNT.frt | 156 ++ .../atmega256rfr2/blocks/TIMER_COUNTER_0.frt | 54 + .../atmega256rfr2/blocks/TIMER_COUNTER_1.frt | 68 + .../atmega256rfr2/blocks/TIMER_COUNTER_2.frt | 67 + .../atmega256rfr2/blocks/TIMER_COUNTER_3.frt | 68 + .../atmega256rfr2/blocks/TIMER_COUNTER_4.frt | 68 + .../atmega256rfr2/blocks/TIMER_COUNTER_5.frt | 68 + .../avr8/devices/atmega256rfr2/blocks/TRX24.frt | 495 ++++++ .../avr8/devices/atmega256rfr2/blocks/TWI.frt | 40 + .../avr8/devices/atmega256rfr2/blocks/USART0.frt | 51 + .../devices/atmega256rfr2/blocks/USART0_SPI.frt | 29 + .../avr8/devices/atmega256rfr2/blocks/USART1.frt | 51 + .../devices/atmega256rfr2/blocks/USART1_SPI.frt | 29 + .../avr8/devices/atmega256rfr2/blocks/WATCHDOG.frt | 15 + amforth-6.5/avr8/devices/atmega256rfr2/device.asm | 166 ++ amforth-6.5/avr8/devices/atmega256rfr2/device.frt | 1753 ++++++++++++++++++++ amforth-6.5/avr8/devices/atmega256rfr2/device.py | 1104 ++++++++++++ 34 files changed, 4790 insertions(+) create mode 100644 amforth-6.5/avr8/devices/atmega256rfr2/blocks/AD_CONVERTER.frt create mode 100644 amforth-6.5/avr8/devices/atmega256rfr2/blocks/ANALOG_COMPARATOR.frt create mode 100644 amforth-6.5/avr8/devices/atmega256rfr2/blocks/BOOT_LOAD.frt create mode 100644 amforth-6.5/avr8/devices/atmega256rfr2/blocks/CPU.frt create mode 100644 amforth-6.5/avr8/devices/atmega256rfr2/blocks/EEPROM.frt create mode 100644 amforth-6.5/avr8/devices/atmega256rfr2/blocks/EXTERNAL_INTERRUPT.frt create mode 100644 amforth-6.5/avr8/devices/atmega256rfr2/blocks/FLASH.frt create mode 100644 amforth-6.5/avr8/devices/atmega256rfr2/blocks/JTAG.frt create mode 100644 amforth-6.5/avr8/devices/atmega256rfr2/blocks/PORTA.frt create mode 100644 amforth-6.5/avr8/devices/atmega256rfr2/blocks/PORTB.frt create mode 100644 amforth-6.5/avr8/devices/atmega256rfr2/blocks/PORTC.frt create mode 100644 amforth-6.5/avr8/devices/atmega256rfr2/blocks/PORTD.frt create mode 100644 amforth-6.5/avr8/devices/atmega256rfr2/blocks/PORTE.frt create mode 100644 amforth-6.5/avr8/devices/atmega256rfr2/blocks/PORTF.frt create mode 100644 amforth-6.5/avr8/devices/atmega256rfr2/blocks/PORTG.frt create mode 100644 amforth-6.5/avr8/devices/atmega256rfr2/blocks/PWRCTRL.frt create mode 100644 amforth-6.5/avr8/devices/atmega256rfr2/blocks/SPI.frt create mode 100644 amforth-6.5/avr8/devices/atmega256rfr2/blocks/SYMCNT.frt create mode 100644 amforth-6.5/avr8/devices/atmega256rfr2/blocks/TIMER_COUNTER_0.frt create mode 100644 amforth-6.5/avr8/devices/atmega256rfr2/blocks/TIMER_COUNTER_1.frt create mode 100644 amforth-6.5/avr8/devices/atmega256rfr2/blocks/TIMER_COUNTER_2.frt create mode 100644 amforth-6.5/avr8/devices/atmega256rfr2/blocks/TIMER_COUNTER_3.frt create mode 100644 amforth-6.5/avr8/devices/atmega256rfr2/blocks/TIMER_COUNTER_4.frt create mode 100644 amforth-6.5/avr8/devices/atmega256rfr2/blocks/TIMER_COUNTER_5.frt create mode 100644 amforth-6.5/avr8/devices/atmega256rfr2/blocks/TRX24.frt create mode 100644 amforth-6.5/avr8/devices/atmega256rfr2/blocks/TWI.frt create mode 100644 amforth-6.5/avr8/devices/atmega256rfr2/blocks/USART0.frt create mode 100644 amforth-6.5/avr8/devices/atmega256rfr2/blocks/USART0_SPI.frt create mode 100644 amforth-6.5/avr8/devices/atmega256rfr2/blocks/USART1.frt create mode 100644 amforth-6.5/avr8/devices/atmega256rfr2/blocks/USART1_SPI.frt create mode 100644 amforth-6.5/avr8/devices/atmega256rfr2/blocks/WATCHDOG.frt create mode 100644 amforth-6.5/avr8/devices/atmega256rfr2/device.asm create mode 100644 amforth-6.5/avr8/devices/atmega256rfr2/device.frt create mode 100644 amforth-6.5/avr8/devices/atmega256rfr2/device.py (limited to 'amforth-6.5/avr8/devices/atmega256rfr2') diff --git a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/AD_CONVERTER.frt b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/AD_CONVERTER.frt new file mode 100644 index 0000000..17d6c7e --- /dev/null +++ b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/AD_CONVERTER.frt @@ -0,0 +1,79 @@ +\ Generated automatically for atmega256rfr2 +\ #require bitnames.frt + +\ AD_CONVERTER +$7c constant ADMUX \ The ADC Multiplexer Selection + $c0 constant ADMUX_REFS \ Reference Selection Bits + 7c $c0 bitmask: ADMUX.REFS \ Reference Selection Bits + $20 constant ADMUX_ADLAR \ ADC Left Adjust Result + 7c $20 bitmask: ADMUX.ADLAR \ ADC Left Adjust Result + $1f constant ADMUX_MUX \ Analog Channel and Gain Select + 7c $1f bitmask: ADMUX.MUX \ Analog Channel and Gain Select +$78 constant ADC \ ADC Data Register Bytes +$7a constant ADCSRA \ The ADC Control and Status Reg + $80 constant ADCSRA_ADEN \ ADC Enable + 7a $80 bitmask: ADCSRA.ADEN \ ADC Enable + $40 constant ADCSRA_ADSC \ ADC Start Conversion + 7a $40 bitmask: ADCSRA.ADSC \ ADC Start Conversion + $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable + 7a $20 bitmask: ADCSRA.ADATE \ ADC Auto Trigger Enable + $10 constant ADCSRA_ADIF \ ADC Interrupt Flag + 7a $10 bitmask: ADCSRA.ADIF \ ADC Interrupt Flag + $8 constant ADCSRA_ADIE \ ADC Interrupt Enable + 7a $8 bitmask: ADCSRA.ADIE \ ADC Interrupt Enable + $7 constant ADCSRA_ADPS \ ADC Prescaler Select Bits + 7a $7 bitmask: ADCSRA.ADPS \ ADC Prescaler Select Bits +$7b constant ADCSRB \ The ADC Control and Status Reg + $80 constant ADCSRB_AVDDOK \ AVDD Supply Voltage OK + 7b $80 bitmask: ADCSRB.AVDDOK \ AVDD Supply Voltage OK + $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer + 7b $40 bitmask: ADCSRB.ACME \ Analog Comparator Multiplexer + $20 constant ADCSRB_REFOK \ Reference Voltage OK + 7b $20 bitmask: ADCSRB.REFOK \ Reference Voltage OK + $10 constant ADCSRB_ACCH \ Analog Channel Change + 7b $10 bitmask: ADCSRB.ACCH \ Analog Channel Change + $8 constant ADCSRB_MUX5 \ Analog Channel and Gain Select + 7b $8 bitmask: ADCSRB.MUX5 \ Analog Channel and Gain Select + $7 constant ADCSRB_ADTS \ ADC Auto Trigger Source + 7b $7 bitmask: ADCSRB.ADTS \ ADC Auto Trigger Source +$77 constant ADCSRC \ The ADC Control and Status Reg + $c0 constant ADCSRC_ADTHT \ ADC Track-and-Hold Time + 77 $c0 bitmask: ADCSRC.ADTHT \ ADC Track-and-Hold Time + $20 constant ADCSRC_Res0 \ Reserved + 77 $20 bitmask: ADCSRC.Res0 \ Reserved + $1f constant ADCSRC_ADSUT \ ADC Start-up Time + 77 $1f bitmask: ADCSRC.ADSUT \ ADC Start-up Time +$7d constant DIDR2 \ Digital Input Disable Register + $80 constant DIDR2_ADC15D \ Reserved Bits + 7d $80 bitmask: DIDR2.ADC15D \ Reserved Bits + $40 constant DIDR2_ADC14D \ Reserved Bits + 7d $40 bitmask: DIDR2.ADC14D \ Reserved Bits + $20 constant DIDR2_ADC13D \ Reserved Bits + 7d $20 bitmask: DIDR2.ADC13D \ Reserved Bits + $10 constant DIDR2_ADC12D \ Reserved Bits + 7d $10 bitmask: DIDR2.ADC12D \ Reserved Bits + $8 constant DIDR2_ADC11D \ Reserved Bits + 7d $8 bitmask: DIDR2.ADC11D \ Reserved Bits + $4 constant DIDR2_ADC10D \ Reserved Bits + 7d $4 bitmask: DIDR2.ADC10D \ Reserved Bits + $2 constant DIDR2_ADC9D \ Reserved Bits + 7d $2 bitmask: DIDR2.ADC9D \ Reserved Bits + $1 constant DIDR2_ADC8D \ Reserved Bits + 7d $1 bitmask: DIDR2.ADC8D \ Reserved Bits +$7e constant DIDR0 \ Digital Input Disable Register + $80 constant DIDR0_ADC7D \ Disable ADC7:0 Digital Input + 7e $80 bitmask: DIDR0.ADC7D \ Disable ADC7:0 Digital Input + $40 constant DIDR0_ADC6D \ Disable ADC7:0 Digital Input + 7e $40 bitmask: DIDR0.ADC6D \ Disable ADC7:0 Digital Input + $20 constant DIDR0_ADC5D \ Disable ADC7:0 Digital Input + 7e $20 bitmask: DIDR0.ADC5D \ Disable ADC7:0 Digital Input + $10 constant DIDR0_ADC4D \ Disable ADC7:0 Digital Input + 7e $10 bitmask: DIDR0.ADC4D \ Disable ADC7:0 Digital Input + $8 constant DIDR0_ADC3D \ Disable ADC7:0 Digital Input + 7e $8 bitmask: DIDR0.ADC3D \ Disable ADC7:0 Digital Input + $4 constant DIDR0_ADC2D \ Disable ADC7:0 Digital Input + 7e $4 bitmask: DIDR0.ADC2D \ Disable ADC7:0 Digital Input + $2 constant DIDR0_ADC1D \ Disable ADC7:0 Digital Input + 7e $2 bitmask: DIDR0.ADC1D \ Disable ADC7:0 Digital Input + $1 constant DIDR0_ADC0D \ Disable ADC7:0 Digital Input + 7e $1 bitmask: DIDR0.ADC0D \ Disable ADC7:0 Digital Input diff --git a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/ANALOG_COMPARATOR.frt b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/ANALOG_COMPARATOR.frt new file mode 100644 index 0000000..cf9e656 --- /dev/null +++ b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/ANALOG_COMPARATOR.frt @@ -0,0 +1,27 @@ +\ Generated automatically for atmega256rfr2 +\ #require bitnames.frt + +\ ANALOG_COMPARATOR +$7b constant ADCSRB \ ADC Control and Status Registe + $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer + 7b $40 bitmask: ADCSRB.ACME \ Analog Comparator Multiplexer +$50 constant ACSR \ Analog Comparator Control And + $80 constant ACSR_ACD \ Analog Comparator Disable + 50 $80 bitmask: ACSR.ACD \ Analog Comparator Disable + $40 constant ACSR_ACBG \ Analog Comparator Bandgap Sele + 50 $40 bitmask: ACSR.ACBG \ Analog Comparator Bandgap Sele + $20 constant ACSR_ACO \ Analog Compare Output + 50 $20 bitmask: ACSR.ACO \ Analog Compare Output + $10 constant ACSR_ACI \ Analog Comparator Interrupt Fl + 50 $10 bitmask: ACSR.ACI \ Analog Comparator Interrupt Fl + $8 constant ACSR_ACIE \ Analog Comparator Interrupt En + 50 $8 bitmask: ACSR.ACIE \ Analog Comparator Interrupt En + $4 constant ACSR_ACIC \ Analog Comparator Input Captur + 50 $4 bitmask: ACSR.ACIC \ Analog Comparator Input Captur + $3 constant ACSR_ACIS \ Analog Comparator Interrupt Mo + 50 $3 bitmask: ACSR.ACIS \ Analog Comparator Interrupt Mo +$7f constant DIDR1 \ Digital Input Disable Register + $2 constant DIDR1_AIN1D \ AIN1 Digital Input Disable + 7f $2 bitmask: DIDR1.AIN1D \ AIN1 Digital Input Disable + $1 constant DIDR1_AIN0D \ AIN0 Digital Input Disable + 7f $1 bitmask: DIDR1.AIN0D \ AIN0 Digital Input Disable diff --git a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/BOOT_LOAD.frt b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/BOOT_LOAD.frt new file mode 100644 index 0000000..d38b796 --- /dev/null +++ b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/BOOT_LOAD.frt @@ -0,0 +1,21 @@ +\ Generated automatically for atmega256rfr2 +\ #require bitnames.frt + +\ BOOT_LOAD +$57 constant SPMCSR \ Store Program Memory Control R + $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable + 57 $80 bitmask: SPMCSR.SPMIE \ SPM Interrupt Enable + $40 constant SPMCSR_RWWSB \ Read While Write Section Busy + 57 $40 bitmask: SPMCSR.RWWSB \ Read While Write Section Busy + $20 constant SPMCSR_SIGRD \ Signature Row Read + 57 $20 bitmask: SPMCSR.SIGRD \ Signature Row Read + $10 constant SPMCSR_RWWSRE \ Read While Write Section Read + 57 $10 bitmask: SPMCSR.RWWSRE \ Read While Write Section Read + $8 constant SPMCSR_BLBSET \ Boot Lock Bit Set + 57 $8 bitmask: SPMCSR.BLBSET \ Boot Lock Bit Set + $4 constant SPMCSR_PGWRT \ Page Write + 57 $4 bitmask: SPMCSR.PGWRT \ Page Write + $2 constant SPMCSR_PGERS \ Page Erase + 57 $2 bitmask: SPMCSR.PGERS \ Page Erase + $1 constant SPMCSR_SPMEN \ Store Program Memory Enable + 57 $1 bitmask: SPMCSR.SPMEN \ Store Program Memory Enable diff --git a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/CPU.frt b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/CPU.frt new file mode 100644 index 0000000..f15f877 --- /dev/null +++ b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/CPU.frt @@ -0,0 +1,129 @@ +\ Generated automatically for atmega256rfr2 +\ #require bitnames.frt + +\ CPU +$5f constant SREG \ Status Register + $80 constant SREG_I \ Global Interrupt Enable + 5f $80 bitmask: SREG.I \ Global Interrupt Enable + $40 constant SREG_T \ Bit Copy Storage + 5f $40 bitmask: SREG.T \ Bit Copy Storage + $20 constant SREG_H \ Half Carry Flag + 5f $20 bitmask: SREG.H \ Half Carry Flag + $10 constant SREG_S \ Sign Bit + 5f $10 bitmask: SREG.S \ Sign Bit + $8 constant SREG_V \ Two's Complement Overflow Flag + 5f $8 bitmask: SREG.V \ Two's Complement Overflow Flag + $4 constant SREG_N \ Negative Flag + 5f $4 bitmask: SREG.N \ Negative Flag + $2 constant SREG_Z \ Zero Flag + 5f $2 bitmask: SREG.Z \ Zero Flag + $1 constant SREG_C \ Carry Flag + 5f $1 bitmask: SREG.C \ Carry Flag +$5d constant SP \ Stack Pointer +$55 constant MCUCR \ MCU Control Register + $80 constant MCUCR_JTD \ JTAG Interface Disable + 55 $80 bitmask: MCUCR.JTD \ JTAG Interface Disable + $60 constant MCUCR_Res \ Reserved + 55 $60 bitmask: MCUCR.Res \ Reserved + $10 constant MCUCR_PUD \ Pull-up Disable + 55 $10 bitmask: MCUCR.PUD \ Pull-up Disable + $c constant MCUCR_Res \ Reserved + 55 $c bitmask: MCUCR.Res \ Reserved + $2 constant MCUCR_IVSEL \ Interrupt Vector Select + 55 $2 bitmask: MCUCR.IVSEL \ Interrupt Vector Select + $1 constant MCUCR_IVCE \ Interrupt Vector Change Enable + 55 $1 bitmask: MCUCR.IVCE \ Interrupt Vector Change Enable +$54 constant MCUSR \ MCU Status Register + $e0 constant MCUSR_Res \ Reserved + 54 $e0 bitmask: MCUSR.Res \ Reserved + $10 constant MCUSR_JTRF \ JTAG Reset Flag + 54 $10 bitmask: MCUSR.JTRF \ JTAG Reset Flag + $8 constant MCUSR_WDRF \ Watchdog Reset Flag + 54 $8 bitmask: MCUSR.WDRF \ Watchdog Reset Flag + $4 constant MCUSR_BORF \ Brown-out Reset Flag + 54 $4 bitmask: MCUSR.BORF \ Brown-out Reset Flag + $2 constant MCUSR_EXTRF \ External Reset Flag + 54 $2 bitmask: MCUSR.EXTRF \ External Reset Flag + $1 constant MCUSR_PORF \ Power-on Reset Flag + 54 $1 bitmask: MCUSR.PORF \ Power-on Reset Flag +$66 constant OSCCAL \ Oscillator Calibration Value + $ff constant OSCCAL_CAL \ Oscillator Calibration Tuning + 66 $ff bitmask: OSCCAL.CAL \ Oscillator Calibration Tuning +$61 constant CLKPR \ Clock Prescale Register + $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable + 61 $80 bitmask: CLKPR.CLKPCE \ Clock Prescaler Change Enable + $70 constant CLKPR_Res \ Reserved + 61 $70 bitmask: CLKPR.Res \ Reserved + $f constant CLKPR_CLKPS \ Clock Prescaler Select Bits + 61 $f bitmask: CLKPR.CLKPS \ Clock Prescaler Select Bits +$53 constant SMCR \ Sleep Mode Control Register + $f0 constant SMCR_Res \ Reserved + 53 $f0 bitmask: SMCR.Res \ Reserved + $e constant SMCR_SM \ Sleep Mode Select bits + 53 $e bitmask: SMCR.SM \ Sleep Mode Select bits + $1 constant SMCR_SE \ Sleep Enable + 53 $1 bitmask: SMCR.SE \ Sleep Enable +$5c constant EIND \ Extended Indirect Register +$5b constant RAMPZ \ Extended Z-pointer Register fo + $fc constant RAMPZ_Res \ Reserved + 5b $fc bitmask: RAMPZ.Res \ Reserved + $3 constant RAMPZ_RAMPZ \ Extended Z-Pointer Value + 5b $3 bitmask: RAMPZ.RAMPZ \ Extended Z-Pointer Value +$4b constant GPIOR2 \ General Purpose I/O Register 2 + $ff constant GPIOR2_GPIOR \ General Purpose I/O Register 2 + 4b $ff bitmask: GPIOR2.GPIOR \ General Purpose I/O Register 2 +$4a constant GPIOR1 \ General Purpose IO Register 1 + $ff constant GPIOR1_GPIOR \ General Purpose I/O Register 1 + 4a $ff bitmask: GPIOR1.GPIOR \ General Purpose I/O Register 1 +$3e constant GPIOR0 \ General Purpose IO Register 0 + $80 constant GPIOR0_GPIOR07 \ General Purpose I/O Register 0 + 3e $80 bitmask: GPIOR0.GPIOR07 \ General Purpose I/O Register 0 + $40 constant GPIOR0_GPIOR06 \ General Purpose I/O Register 0 + 3e $40 bitmask: GPIOR0.GPIOR06 \ General Purpose I/O Register 0 + $20 constant GPIOR0_GPIOR05 \ General Purpose I/O Register 0 + 3e $20 bitmask: GPIOR0.GPIOR05 \ General Purpose I/O Register 0 + $10 constant GPIOR0_GPIOR04 \ General Purpose I/O Register 0 + 3e $10 bitmask: GPIOR0.GPIOR04 \ General Purpose I/O Register 0 + $8 constant GPIOR0_GPIOR03 \ General Purpose I/O Register 0 + 3e $8 bitmask: GPIOR0.GPIOR03 \ General Purpose I/O Register 0 + $4 constant GPIOR0_GPIOR02 \ General Purpose I/O Register 0 + 3e $4 bitmask: GPIOR0.GPIOR02 \ General Purpose I/O Register 0 + $2 constant GPIOR0_GPIOR01 \ General Purpose I/O Register 0 + 3e $2 bitmask: GPIOR0.GPIOR01 \ General Purpose I/O Register 0 + $1 constant GPIOR0_GPIOR00 \ General Purpose I/O Register 0 + 3e $1 bitmask: GPIOR0.GPIOR00 \ General Purpose I/O Register 0 +$63 constant PRR2 \ Power Reduction Register 2 + $f0 constant PRR2_Res \ Reserved Bit + 63 $f0 bitmask: PRR2.Res \ Reserved Bit + $f constant PRR2_PRRAM \ Power Reduction SRAMs + 63 $f bitmask: PRR2.PRRAM \ Power Reduction SRAMs +$65 constant PRR1 \ Power Reduction Register 1 + $80 constant PRR1_Res \ Reserved Bit + 65 $80 bitmask: PRR1.Res \ Reserved Bit + $40 constant PRR1_PRTRX24 \ Power Reduction Transceiver + 65 $40 bitmask: PRR1.PRTRX24 \ Power Reduction Transceiver + $20 constant PRR1_PRTIM5 \ Power Reduction Timer/Counter5 + 65 $20 bitmask: PRR1.PRTIM5 \ Power Reduction Timer/Counter5 + $10 constant PRR1_PRTIM4 \ Power Reduction Timer/Counter4 + 65 $10 bitmask: PRR1.PRTIM4 \ Power Reduction Timer/Counter4 + $8 constant PRR1_PRTIM3 \ Power Reduction Timer/Counter3 + 65 $8 bitmask: PRR1.PRTIM3 \ Power Reduction Timer/Counter3 + $1 constant PRR1_PRUSART1 \ Power Reduction USART1 + 65 $1 bitmask: PRR1.PRUSART1 \ Power Reduction USART1 +$64 constant PRR0 \ Power Reduction Register0 + $80 constant PRR0_PRTWI \ Power Reduction TWI + 64 $80 bitmask: PRR0.PRTWI \ Power Reduction TWI + $40 constant PRR0_PRTIM2 \ Power Reduction Timer/Counter2 + 64 $40 bitmask: PRR0.PRTIM2 \ Power Reduction Timer/Counter2 + $20 constant PRR0_PRTIM0 \ Power Reduction Timer/Counter0 + 64 $20 bitmask: PRR0.PRTIM0 \ Power Reduction Timer/Counter0 + $10 constant PRR0_PRPGA \ Power Reduction PGA + 64 $10 bitmask: PRR0.PRPGA \ Power Reduction PGA + $8 constant PRR0_PRTIM1 \ Power Reduction Timer/Counter1 + 64 $8 bitmask: PRR0.PRTIM1 \ Power Reduction Timer/Counter1 + $4 constant PRR0_PRSPI \ Power Reduction Serial Periphe + 64 $4 bitmask: PRR0.PRSPI \ Power Reduction Serial Periphe + $2 constant PRR0_PRUSART0 \ Power Reduction USART + 64 $2 bitmask: PRR0.PRUSART0 \ Power Reduction USART + $1 constant PRR0_PRADC \ Power Reduction ADC + 64 $1 bitmask: PRR0.PRADC \ Power Reduction ADC diff --git a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/EEPROM.frt b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/EEPROM.frt new file mode 100644 index 0000000..e56ad19 --- /dev/null +++ b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/EEPROM.frt @@ -0,0 +1,19 @@ +\ Generated automatically for atmega256rfr2 +\ #require bitnames.frt + +\ EEPROM +$41 constant EEAR \ EEPROM Address Register Bytes +$40 constant EEDR \ EEPROM Data Register +$3f constant EECR \ EEPROM Control Register + $c0 constant EECR_Res \ Reserved + 3f $c0 bitmask: EECR.Res \ Reserved + $30 constant EECR_EEPM \ EEPROM Programming Mode + 3f $30 bitmask: EECR.EEPM \ EEPROM Programming Mode + $8 constant EECR_EERIE \ EEPROM Ready Interrupt Enable + 3f $8 bitmask: EECR.EERIE \ EEPROM Ready Interrupt Enable + $4 constant EECR_EEMPE \ EEPROM Master Write Enable + 3f $4 bitmask: EECR.EEMPE \ EEPROM Master Write Enable + $2 constant EECR_EEPE \ EEPROM Programming Enable + 3f $2 bitmask: EECR.EEPE \ EEPROM Programming Enable + $1 constant EECR_EERE \ EEPROM Read Enable + 3f $1 bitmask: EECR.EERE \ EEPROM Read Enable diff --git a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/EXTERNAL_INTERRUPT.frt b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/EXTERNAL_INTERRUPT.frt new file mode 100644 index 0000000..4e7c1fc --- /dev/null +++ b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/EXTERNAL_INTERRUPT.frt @@ -0,0 +1,45 @@ +\ Generated automatically for atmega256rfr2 +\ #require bitnames.frt + +\ EXTERNAL_INTERRUPT +$69 constant EICRA \ External Interrupt Control Reg + $c0 constant EICRA_ISC3 \ External Interrupt 3 Sense Con + 69 $c0 bitmask: EICRA.ISC3 \ External Interrupt 3 Sense Con + $30 constant EICRA_ISC2 \ External Interrupt 2 Sense Con + 69 $30 bitmask: EICRA.ISC2 \ External Interrupt 2 Sense Con + $c constant EICRA_ISC1 \ External Interrupt 1 Sense Con + 69 $c bitmask: EICRA.ISC1 \ External Interrupt 1 Sense Con + $3 constant EICRA_ISC0 \ External Interrupt 0 Sense Con + 69 $3 bitmask: EICRA.ISC0 \ External Interrupt 0 Sense Con +$6a constant EICRB \ External Interrupt Control Reg + $c0 constant EICRB_ISC7 \ External Interrupt 7 Sense Con + 6a $c0 bitmask: EICRB.ISC7 \ External Interrupt 7 Sense Con + $30 constant EICRB_ISC6 \ External Interrupt 6 Sense Con + 6a $30 bitmask: EICRB.ISC6 \ External Interrupt 6 Sense Con + $c constant EICRB_ISC5 \ External Interrupt 5 Sense Con + 6a $c bitmask: EICRB.ISC5 \ External Interrupt 5 Sense Con + $3 constant EICRB_ISC4 \ External Interrupt 4 Sense Con + 6a $3 bitmask: EICRB.ISC4 \ External Interrupt 4 Sense Con +$3d constant EIMSK \ External Interrupt Mask Regist + $ff constant EIMSK_INT \ External Interrupt Request Ena + 3d $ff bitmask: EIMSK.INT \ External Interrupt Request Ena +$3c constant EIFR \ External Interrupt Flag Regist + $ff constant EIFR_INTF \ External Interrupt Flag + 3c $ff bitmask: EIFR.INTF \ External Interrupt Flag +$6d constant PCMSK2 \ Pin Change Mask Register 2 + $ff constant PCMSK2_PCINT \ Pin Change Enable Mask + 6d $ff bitmask: PCMSK2.PCINT \ Pin Change Enable Mask +$6c constant PCMSK1 \ Pin Change Mask Register 1 + $ff constant PCMSK1_PCINT \ Pin Change Enable Mask + 6c $ff bitmask: PCMSK1.PCINT \ Pin Change Enable Mask +$6b constant PCMSK0 \ Pin Change Mask Register 0 +$3b constant PCIFR \ Pin Change Interrupt Flag Regi + $f8 constant PCIFR_Res \ Reserved Bit + 3b $f8 bitmask: PCIFR.Res \ Reserved Bit + $7 constant PCIFR_PCIF \ Pin Change Interrupt Flags + 3b $7 bitmask: PCIFR.PCIF \ Pin Change Interrupt Flags +$68 constant PCICR \ Pin Change Interrupt Control R + $f8 constant PCICR_Res \ Reserved Bit + 68 $f8 bitmask: PCICR.Res \ Reserved Bit + $7 constant PCICR_PCIE \ Pin Change Interrupt Enables + 68 $7 bitmask: PCICR.PCIE \ Pin Change Interrupt Enables diff --git a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/FLASH.frt b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/FLASH.frt new file mode 100644 index 0000000..c219192 --- /dev/null +++ b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/FLASH.frt @@ -0,0 +1,16 @@ +\ Generated automatically for atmega256rfr2 +\ #require bitnames.frt + +\ FLASH +$75 constant NEMCR \ Flash Extended-Mode Control-Re + $40 constant NEMCR_ENEAM \ Enable Extended Address Mode f + 75 $40 bitmask: NEMCR.ENEAM \ Enable Extended Address Mode f + $30 constant NEMCR_AEAM \ Address for Extended Address M + 75 $30 bitmask: NEMCR.AEAM \ Address for Extended Address M +$67 constant BGCR \ Reference Voltage Calibration + $80 constant BGCR_Res \ Reserved Bit + 67 $80 bitmask: BGCR.Res \ Reserved Bit + $78 constant BGCR_BGCAL_FINE \ Fine Calibration Bits + 67 $78 bitmask: BGCR.BGCAL_FINE \ Fine Calibration Bits + $7 constant BGCR_BGCAL \ Coarse Calibration Bits + 67 $7 bitmask: BGCR.BGCAL \ Coarse Calibration Bits diff --git a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/JTAG.frt b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/JTAG.frt new file mode 100644 index 0000000..1960eac --- /dev/null +++ b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/JTAG.frt @@ -0,0 +1,13 @@ +\ Generated automatically for atmega256rfr2 +\ #require bitnames.frt + +\ JTAG +$51 constant OCDR \ On-Chip Debug Register + $ff constant OCDR_OCDR \ On-Chip Debug Register Data + 51 $ff bitmask: OCDR.OCDR \ On-Chip Debug Register Data +$55 constant MCUCR \ MCU Control Register + $80 constant MCUCR_JTD \ JTAG Interface Disable + 55 $80 bitmask: MCUCR.JTD \ JTAG Interface Disable +$54 constant MCUSR \ MCU Status Register + $10 constant MCUSR_JTRF \ JTAG Reset Flag + 54 $10 bitmask: MCUSR.JTRF \ JTAG Reset Flag diff --git a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/PORTA.frt b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/PORTA.frt new file mode 100644 index 0000000..0c4e462 --- /dev/null +++ b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/PORTA.frt @@ -0,0 +1,7 @@ +\ Generated automatically for atmega256rfr2 +\ #require bitnames.frt + +\ PORTA +$22 constant PORTA \ Port A Data Register +$21 constant DDRA \ Port A Data Direction Register +$20 constant PINA \ Port A Input Pins Address diff --git a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/PORTB.frt b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/PORTB.frt new file mode 100644 index 0000000..493d57a --- /dev/null +++ b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/PORTB.frt @@ -0,0 +1,7 @@ +\ Generated automatically for atmega256rfr2 +\ #require bitnames.frt + +\ PORTB +$25 constant PORTB \ Port B Data Register +$24 constant DDRB \ Port B Data Direction Register +$23 constant PINB \ Port B Input Pins Address diff --git a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/PORTC.frt b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/PORTC.frt new file mode 100644 index 0000000..dfb169b --- /dev/null +++ b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/PORTC.frt @@ -0,0 +1,7 @@ +\ Generated automatically for atmega256rfr2 +\ #require bitnames.frt + +\ PORTC +$28 constant PORTC \ Port C Data Register +$27 constant DDRC \ Port C Data Direction Register +$26 constant PINC \ Port C Input Pins Address diff --git a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/PORTD.frt b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/PORTD.frt new file mode 100644 index 0000000..d46daaa --- /dev/null +++ b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/PORTD.frt @@ -0,0 +1,7 @@ +\ Generated automatically for atmega256rfr2 +\ #require bitnames.frt + +\ PORTD +$2b constant PORTD \ Port D Data Register +$2a constant DDRD \ Port D Data Direction Register +$29 constant PIND \ Port D Input Pins Address diff --git a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/PORTE.frt b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/PORTE.frt new file mode 100644 index 0000000..feadc5c --- /dev/null +++ b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/PORTE.frt @@ -0,0 +1,7 @@ +\ Generated automatically for atmega256rfr2 +\ #require bitnames.frt + +\ PORTE +$2e constant PORTE \ Port E Data Register +$2d constant DDRE \ Port E Data Direction Register +$2c constant PINE \ Port E Input Pins Address diff --git a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/PORTF.frt b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/PORTF.frt new file mode 100644 index 0000000..d4c2e02 --- /dev/null +++ b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/PORTF.frt @@ -0,0 +1,7 @@ +\ Generated automatically for atmega256rfr2 +\ #require bitnames.frt + +\ PORTF +$31 constant PORTF \ Port F Data Register +$30 constant DDRF \ Port F Data Direction Register +$2f constant PINF \ Port F Input Pins Address diff --git a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/PORTG.frt b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/PORTG.frt new file mode 100644 index 0000000..53a190c --- /dev/null +++ b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/PORTG.frt @@ -0,0 +1,7 @@ +\ Generated automatically for atmega256rfr2 +\ #require bitnames.frt + +\ PORTG +$34 constant PORTG \ Port G Data Register +$33 constant DDRG \ Port G Data Direction Register +$32 constant PING \ Port G Input Pins Address diff --git a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/PWRCTRL.frt b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/PWRCTRL.frt new file mode 100644 index 0000000..2ba9d2e --- /dev/null +++ b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/PWRCTRL.frt @@ -0,0 +1,81 @@ +\ Generated automatically for atmega256rfr2 +\ #require bitnames.frt + +\ PWRCTRL +$139 constant TRXPR \ Transceiver Pin Register + $f0 constant TRXPR_Res \ Reserved + 139 $f0 bitmask: TRXPR.Res \ Reserved + $2 constant TRXPR_SLPTR \ Multi-purpose Transceiver Cont + 139 $2 bitmask: TRXPR.SLPTR \ Multi-purpose Transceiver Cont + $1 constant TRXPR_TRXRST \ Force Transceiver Reset + 139 $1 bitmask: TRXPR.TRXRST \ Force Transceiver Reset +$135 constant DRTRAM0 \ Data Retention Configuration R + $c0 constant DRTRAM0_Res \ Reserved + 135 $c0 bitmask: DRTRAM0.Res \ Reserved + $20 constant DRTRAM0_DRTSWOK \ DRT Switch OK + 135 $20 bitmask: DRTRAM0.DRTSWOK \ DRT Switch OK + $10 constant DRTRAM0_ENDRT \ Enable SRAM Data Retention + 135 $10 bitmask: DRTRAM0.ENDRT \ Enable SRAM Data Retention +$134 constant DRTRAM1 \ Data Retention Configuration R + $c0 constant DRTRAM1_Res \ Reserved + 134 $c0 bitmask: DRTRAM1.Res \ Reserved + $20 constant DRTRAM1_DRTSWOK \ DRT Switch OK + 134 $20 bitmask: DRTRAM1.DRTSWOK \ DRT Switch OK + $10 constant DRTRAM1_ENDRT \ Enable SRAM Data Retention + 134 $10 bitmask: DRTRAM1.ENDRT \ Enable SRAM Data Retention +$133 constant DRTRAM2 \ Data Retention Configuration R + $40 constant DRTRAM2_Res \ Reserved Bit + 133 $40 bitmask: DRTRAM2.Res \ Reserved Bit + $20 constant DRTRAM2_DRTSWOK \ DRT Switch OK + 133 $20 bitmask: DRTRAM2.DRTSWOK \ DRT Switch OK + $10 constant DRTRAM2_ENDRT \ Enable SRAM Data Retention + 133 $10 bitmask: DRTRAM2.ENDRT \ Enable SRAM Data Retention +$132 constant DRTRAM3 \ Data Retention Configuration R + $c0 constant DRTRAM3_Res \ Reserved + 132 $c0 bitmask: DRTRAM3.Res \ Reserved + $20 constant DRTRAM3_DRTSWOK \ DRT Switch OK + 132 $20 bitmask: DRTRAM3.DRTSWOK \ DRT Switch OK + $10 constant DRTRAM3_ENDRT \ Enable SRAM Data Retention + 132 $10 bitmask: DRTRAM3.ENDRT \ Enable SRAM Data Retention +$130 constant LLDRL \ Low Leakage Voltage Regulator + $f0 constant LLDRL_Res \ Reserved + 130 $f0 bitmask: LLDRL.Res \ Reserved + $f constant LLDRL_LLDRL \ Low-Byte Data Register Bits + 130 $f bitmask: LLDRL.LLDRL \ Low-Byte Data Register Bits +$131 constant LLDRH \ Low Leakage Voltage Regulator + $e0 constant LLDRH_Res \ Reserved + 131 $e0 bitmask: LLDRH.Res \ Reserved + $1f constant LLDRH_LLDRH \ High-Byte Data Register Bits + 131 $1f bitmask: LLDRH.LLDRH \ High-Byte Data Register Bits +$12f constant LLCR \ Low Leakage Voltage Regulator + $c0 constant LLCR_Res \ Reserved Bit + 12f $c0 bitmask: LLCR.Res \ Reserved Bit + $20 constant LLCR_LLDONE \ Calibration Done + 12f $20 bitmask: LLCR.LLDONE \ Calibration Done + $10 constant LLCR_LLCOMP \ Comparator Output + 12f $10 bitmask: LLCR.LLCOMP \ Comparator Output + $8 constant LLCR_LLCAL \ Calibration Active + 12f $8 bitmask: LLCR.LLCAL \ Calibration Active + $4 constant LLCR_LLTCO \ Temperature Coefficient of Cur + 12f $4 bitmask: LLCR.LLTCO \ Temperature Coefficient of Cur + $2 constant LLCR_LLSHORT \ Short Lower Calibration Circui + 12f $2 bitmask: LLCR.LLSHORT \ Short Lower Calibration Circui + $1 constant LLCR_LLENCAL \ Enable Automatic Calibration + 12f $1 bitmask: LLCR.LLENCAL \ Enable Automatic Calibration +$136 constant DPDS0 \ Port Driver Strength Register + $c0 constant DPDS0_PFDRV \ Driver Strength Port F + 136 $c0 bitmask: DPDS0.PFDRV \ Driver Strength Port F + $30 constant DPDS0_PEDRV \ Driver Strength Port E + 136 $30 bitmask: DPDS0.PEDRV \ Driver Strength Port E + $c constant DPDS0_PDDRV \ Driver Strength Port D + 136 $c bitmask: DPDS0.PDDRV \ Driver Strength Port D + $3 constant DPDS0_PBDRV \ Driver Strength Port B + 136 $3 bitmask: DPDS0.PBDRV \ Driver Strength Port B +$137 constant DPDS1 \ Port Driver Strength Register + $fc constant DPDS1_Res \ Reserved + 137 $fc bitmask: DPDS1.Res \ Reserved + $3 constant DPDS1_PGDRV \ Driver Strength Port G + 137 $3 bitmask: DPDS1.PGDRV \ Driver Strength Port G +$55 constant MCUCR \ MCU Control Register + $10 constant MCUCR_PUD \ Pull-up Disable + 55 $10 bitmask: MCUCR.PUD \ Pull-up Disable diff --git a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/SPI.frt b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/SPI.frt new file mode 100644 index 0000000..53bae0e --- /dev/null +++ b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/SPI.frt @@ -0,0 +1,29 @@ +\ Generated automatically for atmega256rfr2 +\ #require bitnames.frt + +\ SPI +$4c constant SPCR \ SPI Control Register + $80 constant SPCR_SPIE \ SPI Interrupt Enable + 4c $80 bitmask: SPCR.SPIE \ SPI Interrupt Enable + $40 constant SPCR_SPE \ SPI Enable + 4c $40 bitmask: SPCR.SPE \ SPI Enable + $20 constant SPCR_DORD \ Data Order + 4c $20 bitmask: SPCR.DORD \ Data Order + $10 constant SPCR_MSTR \ Master/Slave Select + 4c $10 bitmask: SPCR.MSTR \ Master/Slave Select + $8 constant SPCR_CPOL \ Clock polarity + 4c $8 bitmask: SPCR.CPOL \ Clock polarity + $4 constant SPCR_CPHA \ Clock Phase + 4c $4 bitmask: SPCR.CPHA \ Clock Phase + $3 constant SPCR_SPR \ SPI Clock Rate Select 1 and 0 + 4c $3 bitmask: SPCR.SPR \ SPI Clock Rate Select 1 and 0 +$4d constant SPSR \ SPI Status Register + $80 constant SPSR_SPIF \ SPI Interrupt Flag + 4d $80 bitmask: SPSR.SPIF \ SPI Interrupt Flag + $40 constant SPSR_WCOL \ Write Collision Flag + 4d $40 bitmask: SPSR.WCOL \ Write Collision Flag + $3e constant SPSR_Res \ Reserved + 4d $3e bitmask: SPSR.Res \ Reserved + $1 constant SPSR_SPI2X \ Double SPI Speed Bit + 4d $1 bitmask: SPSR.SPI2X \ Double SPI Speed Bit +$4e constant SPDR \ SPI Data Register diff --git a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/SYMCNT.frt b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/SYMCNT.frt new file mode 100644 index 0000000..26c4758 --- /dev/null +++ b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/SYMCNT.frt @@ -0,0 +1,156 @@ +\ Generated automatically for atmega256rfr2 +\ #require bitnames.frt + +\ SYMCNT +$fc constant SCTSTRHH \ Symbol Counter Transmit Frame + $ff constant SCTSTRHH_SCTSTRHH \ Symbol Counter Transmit Frame + fc $ff bitmask: SCTSTRHH.SCTSTRHH \ Symbol Counter Transmit Frame +$fb constant SCTSTRHL \ Symbol Counter Transmit Frame + $ff constant SCTSTRHL_SCTSTRHL \ Symbol Counter Transmit Frame + fb $ff bitmask: SCTSTRHL.SCTSTRHL \ Symbol Counter Transmit Frame +$fa constant SCTSTRLH \ Symbol Counter Transmit Frame + $ff constant SCTSTRLH_SCTSTRLH \ Symbol Counter Transmit Frame + fa $ff bitmask: SCTSTRLH.SCTSTRLH \ Symbol Counter Transmit Frame +$f9 constant SCTSTRLL \ Symbol Counter Transmit Frame + $ff constant SCTSTRLL_SCTSTRLL \ Symbol Counter Transmit Frame + f9 $ff bitmask: SCTSTRLL.SCTSTRLL \ Symbol Counter Transmit Frame +$f8 constant SCOCR1HH \ Symbol Counter Output Compare + $ff constant SCOCR1HH_SCOCR1HH \ Symbol Counter Output Compare + f8 $ff bitmask: SCOCR1HH.SCOCR1HH \ Symbol Counter Output Compare +$f7 constant SCOCR1HL \ Symbol Counter Output Compare + $ff constant SCOCR1HL_SCOCR1HL \ Symbol Counter Output Compare + f7 $ff bitmask: SCOCR1HL.SCOCR1HL \ Symbol Counter Output Compare +$f6 constant SCOCR1LH \ Symbol Counter Output Compare + $ff constant SCOCR1LH_SCOCR1LH \ Symbol Counter Output Compare + f6 $ff bitmask: SCOCR1LH.SCOCR1LH \ Symbol Counter Output Compare +$f5 constant SCOCR1LL \ Symbol Counter Output Compare + $ff constant SCOCR1LL_SCOCR1LL \ Symbol Counter Output Compare + f5 $ff bitmask: SCOCR1LL.SCOCR1LL \ Symbol Counter Output Compare +$f4 constant SCOCR2HH \ Symbol Counter Output Compare + $ff constant SCOCR2HH_SCOCR2HH \ Symbol Counter Output Compare + f4 $ff bitmask: SCOCR2HH.SCOCR2HH \ Symbol Counter Output Compare +$f3 constant SCOCR2HL \ Symbol Counter Output Compare + $ff constant SCOCR2HL_SCOCR2HL \ Symbol Counter Output Compare + f3 $ff bitmask: SCOCR2HL.SCOCR2HL \ Symbol Counter Output Compare +$f2 constant SCOCR2LH \ Symbol Counter Output Compare + $ff constant SCOCR2LH_SCOCR2LH \ Symbol Counter Output Compare + f2 $ff bitmask: SCOCR2LH.SCOCR2LH \ Symbol Counter Output Compare +$f1 constant SCOCR2LL \ Symbol Counter Output Compare + $ff constant SCOCR2LL_SCOCR2LL \ Symbol Counter Output Compare + f1 $ff bitmask: SCOCR2LL.SCOCR2LL \ Symbol Counter Output Compare +$f0 constant SCOCR3HH \ Symbol Counter Output Compare + $ff constant SCOCR3HH_SCOCR3HH \ Symbol Counter Output Compare + f0 $ff bitmask: SCOCR3HH.SCOCR3HH \ Symbol Counter Output Compare +$ef constant SCOCR3HL \ Symbol Counter Output Compare + $ff constant SCOCR3HL_SCOCR3HL \ Symbol Counter Output Compare + ef $ff bitmask: SCOCR3HL.SCOCR3HL \ Symbol Counter Output Compare +$ee constant SCOCR3LH \ Symbol Counter Output Compare + $ff constant SCOCR3LH_SCOCR3LH \ Symbol Counter Output Compare + ee $ff bitmask: SCOCR3LH.SCOCR3LH \ Symbol Counter Output Compare +$ed constant SCOCR3LL \ Symbol Counter Output Compare + $ff constant SCOCR3LL_SCOCR3LL \ Symbol Counter Output Compare + ed $ff bitmask: SCOCR3LL.SCOCR3LL \ Symbol Counter Output Compare +$ec constant SCTSRHH \ Symbol Counter Frame Timestamp + $ff constant SCTSRHH_SCTSRHH \ Symbol Counter Frame Timestamp + ec $ff bitmask: SCTSRHH.SCTSRHH \ Symbol Counter Frame Timestamp +$eb constant SCTSRHL \ Symbol Counter Frame Timestamp + $ff constant SCTSRHL_SCTSRHL \ Symbol Counter Frame Timestamp + eb $ff bitmask: SCTSRHL.SCTSRHL \ Symbol Counter Frame Timestamp +$ea constant SCTSRLH \ Symbol Counter Frame Timestamp + $ff constant SCTSRLH_SCTSRLH \ Symbol Counter Frame Timestamp + ea $ff bitmask: SCTSRLH.SCTSRLH \ Symbol Counter Frame Timestamp +$e9 constant SCTSRLL \ Symbol Counter Frame Timestamp + $ff constant SCTSRLL_SCTSRLL \ Symbol Counter Frame Timestamp + e9 $ff bitmask: SCTSRLL.SCTSRLL \ Symbol Counter Frame Timestamp +$e8 constant SCBTSRHH \ Symbol Counter Beacon Timestam + $ff constant SCBTSRHH_SCBTSRHH \ Symbol Counter Beacon Timestam + e8 $ff bitmask: SCBTSRHH.SCBTSRHH \ Symbol Counter Beacon Timestam +$e7 constant SCBTSRHL \ Symbol Counter Beacon Timestam + $ff constant SCBTSRHL_SCBTSRHL \ Symbol Counter Beacon Timestam + e7 $ff bitmask: SCBTSRHL.SCBTSRHL \ Symbol Counter Beacon Timestam +$e6 constant SCBTSRLH \ Symbol Counter Beacon Timestam + $ff constant SCBTSRLH_SCBTSRLH \ Symbol Counter Beacon Timestam + e6 $ff bitmask: SCBTSRLH.SCBTSRLH \ Symbol Counter Beacon Timestam +$e5 constant SCBTSRLL \ Symbol Counter Beacon Timestam + $ff constant SCBTSRLL_SCBTSRLL \ Symbol Counter Beacon Timestam + e5 $ff bitmask: SCBTSRLL.SCBTSRLL \ Symbol Counter Beacon Timestam +$e4 constant SCCNTHH \ Symbol Counter Register HH-Byt + $ff constant SCCNTHH_SCCNTHH \ Symbol Counter Register HH-Byt + e4 $ff bitmask: SCCNTHH.SCCNTHH \ Symbol Counter Register HH-Byt +$e3 constant SCCNTHL \ Symbol Counter Register HL-Byt + $ff constant SCCNTHL_SCCNTHL \ Symbol Counter Register HL-Byt + e3 $ff bitmask: SCCNTHL.SCCNTHL \ Symbol Counter Register HL-Byt +$e2 constant SCCNTLH \ Symbol Counter Register LH-Byt + $ff constant SCCNTLH_SCCNTLH \ Symbol Counter Register LH-Byt + e2 $ff bitmask: SCCNTLH.SCCNTLH \ Symbol Counter Register LH-Byt +$e1 constant SCCNTLL \ Symbol Counter Register LL-Byt + $ff constant SCCNTLL_SCCNTLL \ Symbol Counter Register LL-Byt + e1 $ff bitmask: SCCNTLL.SCCNTLL \ Symbol Counter Register LL-Byt +$e0 constant SCIRQS \ Symbol Counter Interrupt Statu + $e0 constant SCIRQS_Res \ Reserved Bit + e0 $e0 bitmask: SCIRQS.Res \ Reserved Bit + $10 constant SCIRQS_IRQSBO \ Backoff Slot Counter IRQ + e0 $10 bitmask: SCIRQS.IRQSBO \ Backoff Slot Counter IRQ + $8 constant SCIRQS_IRQSOF \ Symbol Counter Overflow IRQ + e0 $8 bitmask: SCIRQS.IRQSOF \ Symbol Counter Overflow IRQ + $7 constant SCIRQS_IRQSCP \ Compare Unit 3 Compare Match I + e0 $7 bitmask: SCIRQS.IRQSCP \ Compare Unit 3 Compare Match I +$df constant SCIRQM \ Symbol Counter Interrupt Mask + $e0 constant SCIRQM_Res \ Reserved Bit + df $e0 bitmask: SCIRQM.Res \ Reserved Bit + $10 constant SCIRQM_IRQMBO \ Backoff Slot Counter IRQ enabl + df $10 bitmask: SCIRQM.IRQMBO \ Backoff Slot Counter IRQ enabl + $8 constant SCIRQM_IRQMOF \ Symbol Counter Overflow IRQ en + df $8 bitmask: SCIRQM.IRQMOF \ Symbol Counter Overflow IRQ en + $7 constant SCIRQM_IRQMCP \ Symbol Counter Compare Match 3 + df $7 bitmask: SCIRQM.IRQMCP \ Symbol Counter Compare Match 3 +$de constant SCSR \ Symbol Counter Status Register + $fe constant SCSR_Res \ Reserved Bit + de $fe bitmask: SCSR.Res \ Reserved Bit + $1 constant SCSR_SCBSY \ Symbol Counter busy + de $1 bitmask: SCSR.SCBSY \ Symbol Counter busy +$dd constant SCCR1 \ Symbol Counter Control Registe + $c0 constant SCCR1_Res \ Reserved Bit + dd $c0 bitmask: SCCR1.Res \ Reserved Bit + $20 constant SCCR1_SCBTSM \ Symbol Counter Beacon Timestam + dd $20 bitmask: SCCR1.SCBTSM \ Symbol Counter Beacon Timestam + $1c constant SCCR1_SCCKDIV \ Clock divider for synchronous + dd $1c bitmask: SCCR1.SCCKDIV \ Clock divider for synchronous + $2 constant SCCR1_SCEECLK \ Enable External Clock Source o + dd $2 bitmask: SCCR1.SCEECLK \ Enable External Clock Source o + $1 constant SCCR1_SCENBO \ Backoff Slot Counter enable + dd $1 bitmask: SCCR1.SCENBO \ Backoff Slot Counter enable +$dc constant SCCR0 \ Symbol Counter Control Registe + $80 constant SCCR0_SCRES \ Symbol Counter Synchronization + dc $80 bitmask: SCCR0.SCRES \ Symbol Counter Synchronization + $40 constant SCCR0_SCMBTS \ Manual Beacon Timestamp + dc $40 bitmask: SCCR0.SCMBTS \ Manual Beacon Timestamp + $20 constant SCCR0_SCEN \ Symbol Counter enable + dc $20 bitmask: SCCR0.SCEN \ Symbol Counter enable + $10 constant SCCR0_SCCKSEL \ Symbol Counter Clock Source se + dc $10 bitmask: SCCR0.SCCKSEL \ Symbol Counter Clock Source se + $8 constant SCCR0_SCTSE \ Symbol Counter Automatic Times + dc $8 bitmask: SCCR0.SCTSE \ Symbol Counter Automatic Times + $7 constant SCCR0_SCCMP \ Symbol Counter Compare Unit 3 + dc $7 bitmask: SCCR0.SCCMP \ Symbol Counter Compare Unit 3 +$db constant SCCSR \ Symbol Counter Compare Source + $c0 constant SCCSR_Res \ Reserved Bit + db $c0 bitmask: SCCSR.Res \ Reserved Bit + $30 constant SCCSR_SCCS3 \ Symbol Counter Compare Source + db $30 bitmask: SCCSR.SCCS3 \ Symbol Counter Compare Source + $c constant SCCSR_SCCS2 \ Symbol Counter Compare Source + db $c bitmask: SCCSR.SCCS2 \ Symbol Counter Compare Source + $3 constant SCCSR_SCCS1 \ Symbol Counter Compare Source + db $3 bitmask: SCCSR.SCCS1 \ Symbol Counter Compare Source +$da constant SCRSTRHH \ Symbol Counter Received Frame + $ff constant SCRSTRHH_SCRSTRHH \ Symbol Counter Received Frame + da $ff bitmask: SCRSTRHH.SCRSTRHH \ Symbol Counter Received Frame +$d9 constant SCRSTRHL \ Symbol Counter Received Frame + $ff constant SCRSTRHL_SCRSTRHL \ Symbol Counter Received Frame + d9 $ff bitmask: SCRSTRHL.SCRSTRHL \ Symbol Counter Received Frame +$d8 constant SCRSTRLH \ Symbol Counter Received Frame + $ff constant SCRSTRLH_SCRSTRLH \ Symbol Counter Received Frame + d8 $ff bitmask: SCRSTRLH.SCRSTRLH \ Symbol Counter Received Frame +$d7 constant SCRSTRLL \ Symbol Counter Received Frame + $ff constant SCRSTRLL_SCRSTRLL \ Symbol Counter Received Frame + d7 $ff bitmask: SCRSTRLL.SCRSTRLL \ Symbol Counter Received Frame diff --git a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/TIMER_COUNTER_0.frt b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/TIMER_COUNTER_0.frt new file mode 100644 index 0000000..50f60a9 --- /dev/null +++ b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/TIMER_COUNTER_0.frt @@ -0,0 +1,54 @@ +\ Generated automatically for atmega256rfr2 +\ #require bitnames.frt + +\ TIMER_COUNTER_0 +$48 constant OCR0B \ Timer/Counter0 Output Compare +$47 constant OCR0A \ Timer/Counter0 Output Compare +$46 constant TCNT0 \ Timer/Counter0 Register +$45 constant TCCR0B \ Timer/Counter0 Control Registe + $80 constant TCCR0B_FOC0A \ Force Output Compare A + 45 $80 bitmask: TCCR0B.FOC0A \ Force Output Compare A + $40 constant TCCR0B_FOC0B \ Force Output Compare B + 45 $40 bitmask: TCCR0B.FOC0B \ Force Output Compare B + $30 constant TCCR0B_Res \ Reserved Bit + 45 $30 bitmask: TCCR0B.Res \ Reserved Bit + $8 constant TCCR0B_WGM02 \ + 45 $8 bitmask: TCCR0B.WGM02 \ + $7 constant TCCR0B_CS0 \ Clock Select + 45 $7 bitmask: TCCR0B.CS0 \ Clock Select +$44 constant TCCR0A \ Timer/Counter0 Control Registe + $c0 constant TCCR0A_COM0A \ Compare Match Output A Mode + 44 $c0 bitmask: TCCR0A.COM0A \ Compare Match Output A Mode + $30 constant TCCR0A_COM0B \ Compare Match Output B Mode + 44 $30 bitmask: TCCR0A.COM0B \ Compare Match Output B Mode + $c constant TCCR0A_Res \ Reserved Bit + 44 $c bitmask: TCCR0A.Res \ Reserved Bit + $3 constant TCCR0A_WGM0 \ Waveform Generation Mode + 44 $3 bitmask: TCCR0A.WGM0 \ Waveform Generation Mode +$6e constant TIMSK0 \ Timer/Counter0 Interrupt Mask + $f8 constant TIMSK0_Res \ Reserved + 6e $f8 bitmask: TIMSK0.Res \ Reserved + $4 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare + 6e $4 bitmask: TIMSK0.OCIE0B \ Timer/Counter0 Output Compare + $2 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare + 6e $2 bitmask: TIMSK0.OCIE0A \ Timer/Counter0 Output Compare + $1 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interr + 6e $1 bitmask: TIMSK0.TOIE0 \ Timer/Counter0 Overflow Interr +$35 constant TIFR0 \ Timer/Counter0 Interrupt Flag + $f8 constant TIFR0_Res \ Reserved + 35 $f8 bitmask: TIFR0.Res \ Reserved + $4 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare + 35 $4 bitmask: TIFR0.OCF0B \ Timer/Counter0 Output Compare + $2 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare + 35 $2 bitmask: TIFR0.OCF0A \ Timer/Counter0 Output Compare + $1 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag + 35 $1 bitmask: TIFR0.TOV0 \ Timer/Counter0 Overflow Flag +$43 constant GTCCR \ General Timer/Counter Control + $80 constant GTCCR_TSM \ Timer/Counter Synchronization + 43 $80 bitmask: GTCCR.TSM \ Timer/Counter Synchronization + $7c constant GTCCR_Res \ Reserved + 43 $7c bitmask: GTCCR.Res \ Reserved + $2 constant GTCCR_PSRASY \ Prescaler Reset Timer/Counter2 + 43 $2 bitmask: GTCCR.PSRASY \ Prescaler Reset Timer/Counter2 + $1 constant GTCCR_PSRSYNC \ Prescaler Reset for Synchronou + 43 $1 bitmask: GTCCR.PSRSYNC \ Prescaler Reset for Synchronou diff --git a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/TIMER_COUNTER_1.frt b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/TIMER_COUNTER_1.frt new file mode 100644 index 0000000..d3b8f20 --- /dev/null +++ b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/TIMER_COUNTER_1.frt @@ -0,0 +1,68 @@ +\ Generated automatically for atmega256rfr2 +\ #require bitnames.frt + +\ TIMER_COUNTER_1 +$80 constant TCCR1A \ Timer/Counter1 Control Registe + $c0 constant TCCR1A_COM1A \ Compare Output Mode for Channe + 80 $c0 bitmask: TCCR1A.COM1A \ Compare Output Mode for Channe + $30 constant TCCR1A_COM1B \ Compare Output Mode for Channe + 80 $30 bitmask: TCCR1A.COM1B \ Compare Output Mode for Channe + $c constant TCCR1A_COM1C \ Compare Output Mode for Channe + 80 $c bitmask: TCCR1A.COM1C \ Compare Output Mode for Channe + $3 constant TCCR1A_WGM1 \ Waveform Generation Mode + 80 $3 bitmask: TCCR1A.WGM1 \ Waveform Generation Mode +$81 constant TCCR1B \ Timer/Counter1 Control Registe + $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Cancelle + 81 $80 bitmask: TCCR1B.ICNC1 \ Input Capture 1 Noise Cancelle + $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select + 81 $40 bitmask: TCCR1B.ICES1 \ Input Capture 1 Edge Select + $20 constant TCCR1B_Res \ Reserved Bit + 81 $20 bitmask: TCCR1B.Res \ Reserved Bit + $18 constant TCCR1B_WGM1 \ Waveform Generation Mode + 81 $18 bitmask: TCCR1B.WGM1 \ Waveform Generation Mode + $7 constant TCCR1B_CS1 \ Clock Select + 81 $7 bitmask: TCCR1B.CS1 \ Clock Select +$82 constant TCCR1C \ Timer/Counter1 Control Registe + $80 constant TCCR1C_FOC1A \ Force Output Compare for Chann + 82 $80 bitmask: TCCR1C.FOC1A \ Force Output Compare for Chann + $40 constant TCCR1C_FOC1B \ Force Output Compare for Chann + 82 $40 bitmask: TCCR1C.FOC1B \ Force Output Compare for Chann + $20 constant TCCR1C_FOC1C \ Force Output Compare for Chann + 82 $20 bitmask: TCCR1C.FOC1C \ Force Output Compare for Chann + $1f constant TCCR1C_Res \ Reserved + 82 $1f bitmask: TCCR1C.Res \ Reserved +$84 constant TCNT1 \ Timer/Counter1 Bytes +$88 constant OCR1A \ Timer/Counter1 Output Compare +$8a constant OCR1B \ Timer/Counter1 Output Compare +$8c constant OCR1C \ Timer/Counter1 Output Compare +$86 constant ICR1 \ Timer/Counter1 Input Capture R +$6f constant TIMSK1 \ Timer/Counter1 Interrupt Mask + $c0 constant TIMSK1_Res \ Reserved Bit + 6f $c0 bitmask: TIMSK1.Res \ Reserved Bit + $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture I + 6f $20 bitmask: TIMSK1.ICIE1 \ Timer/Counter1 Input Capture I + $10 constant TIMSK1_Res \ Reserved Bit + 6f $10 bitmask: TIMSK1.Res \ Reserved Bit + $8 constant TIMSK1_OCIE1C \ Timer/Counter1 Output Compare + 6f $8 bitmask: TIMSK1.OCIE1C \ Timer/Counter1 Output Compare + $4 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare + 6f $4 bitmask: TIMSK1.OCIE1B \ Timer/Counter1 Output Compare + $2 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare + 6f $2 bitmask: TIMSK1.OCIE1A \ Timer/Counter1 Output Compare + $1 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interr + 6f $1 bitmask: TIMSK1.TOIE1 \ Timer/Counter1 Overflow Interr +$36 constant TIFR1 \ Timer/Counter1 Interrupt Flag + $c0 constant TIFR1_Res \ Reserved Bit + 36 $c0 bitmask: TIFR1.Res \ Reserved Bit + $20 constant TIFR1_ICF1 \ Timer/Counter1 Input Capture F + 36 $20 bitmask: TIFR1.ICF1 \ Timer/Counter1 Input Capture F + $10 constant TIFR1_Res \ Reserved Bit + 36 $10 bitmask: TIFR1.Res \ Reserved Bit + $8 constant TIFR1_OCF1C \ Timer/Counter1 Output Compare + 36 $8 bitmask: TIFR1.OCF1C \ Timer/Counter1 Output Compare + $4 constant TIFR1_OCF1B \ Timer/Counter1 Output Compare + 36 $4 bitmask: TIFR1.OCF1B \ Timer/Counter1 Output Compare + $2 constant TIFR1_OCF1A \ Timer/Counter1 Output Compare + 36 $2 bitmask: TIFR1.OCF1A \ Timer/Counter1 Output Compare + $1 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag + 36 $1 bitmask: TIFR1.TOV1 \ Timer/Counter1 Overflow Flag diff --git a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/TIMER_COUNTER_2.frt b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/TIMER_COUNTER_2.frt new file mode 100644 index 0000000..748cd79 --- /dev/null +++ b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/TIMER_COUNTER_2.frt @@ -0,0 +1,67 @@ +\ Generated automatically for atmega256rfr2 +\ #require bitnames.frt + +\ TIMER_COUNTER_2 +$70 constant TIMSK2 \ Timer/Counter Interrupt Mask r + $f8 constant TIMSK2_Res \ Reserved Bit + 70 $f8 bitmask: TIMSK2.Res \ Reserved Bit + $4 constant TIMSK2_OCIE2B \ Timer/Counter2 Output Compare + 70 $4 bitmask: TIMSK2.OCIE2B \ Timer/Counter2 Output Compare + $2 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare + 70 $2 bitmask: TIMSK2.OCIE2A \ Timer/Counter2 Output Compare + $1 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interr + 70 $1 bitmask: TIMSK2.TOIE2 \ Timer/Counter2 Overflow Interr +$37 constant TIFR2 \ Timer/Counter Interrupt Flag R + $f8 constant TIFR2_Res \ Reserved Bit + 37 $f8 bitmask: TIFR2.Res \ Reserved Bit + $4 constant TIFR2_OCF2B \ Output Compare Flag 2 B + 37 $4 bitmask: TIFR2.OCF2B \ Output Compare Flag 2 B + $2 constant TIFR2_OCF2A \ Output Compare Flag 2 A + 37 $2 bitmask: TIFR2.OCF2A \ Output Compare Flag 2 A + $1 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag + 37 $1 bitmask: TIFR2.TOV2 \ Timer/Counter2 Overflow Flag +$b0 constant TCCR2A \ Timer/Counter2 Control Registe + $c0 constant TCCR2A_COM2A \ Compare Match Output A Mode + b0 $c0 bitmask: TCCR2A.COM2A \ Compare Match Output A Mode + $30 constant TCCR2A_COM2B \ Compare Match Output B Mode + b0 $30 bitmask: TCCR2A.COM2B \ Compare Match Output B Mode + $c constant TCCR2A_Res \ Reserved + b0 $c bitmask: TCCR2A.Res \ Reserved + $3 constant TCCR2A_WGM2 \ Waveform Generation Mode + b0 $3 bitmask: TCCR2A.WGM2 \ Waveform Generation Mode +$b1 constant TCCR2B \ Timer/Counter2 Control Registe + $80 constant TCCR2B_FOC2A \ Force Output Compare A + b1 $80 bitmask: TCCR2B.FOC2A \ Force Output Compare A + $40 constant TCCR2B_FOC2B \ Force Output Compare B + b1 $40 bitmask: TCCR2B.FOC2B \ Force Output Compare B + $30 constant TCCR2B_Res \ Reserved + b1 $30 bitmask: TCCR2B.Res \ Reserved + $8 constant TCCR2B_WGM22 \ Waveform Generation Mode + b1 $8 bitmask: TCCR2B.WGM22 \ Waveform Generation Mode + $7 constant TCCR2B_CS2 \ Clock Select + b1 $7 bitmask: TCCR2B.CS2 \ Clock Select +$b2 constant TCNT2 \ Timer/Counter2 +$b4 constant OCR2B \ Timer/Counter2 Output Compare +$b3 constant OCR2A \ Timer/Counter2 Output Compare +$b6 constant ASSR \ Asynchronous Status Register + $80 constant ASSR_EXCLKAMR \ Enable External Clock Input fo + b6 $80 bitmask: ASSR.EXCLKAMR \ Enable External Clock Input fo + $40 constant ASSR_EXCLK \ Enable External Clock Input + b6 $40 bitmask: ASSR.EXCLK \ Enable External Clock Input + $20 constant ASSR_AS2 \ Timer/Counter2 Asynchronous Mo + b6 $20 bitmask: ASSR.AS2 \ Timer/Counter2 Asynchronous Mo + $10 constant ASSR_TCN2UB \ Timer/Counter2 Update Busy + b6 $10 bitmask: ASSR.TCN2UB \ Timer/Counter2 Update Busy + $8 constant ASSR_OCR2AUB \ Timer/Counter2 Output Compare + b6 $8 bitmask: ASSR.OCR2AUB \ Timer/Counter2 Output Compare + $4 constant ASSR_OCR2BUB \ Timer/Counter2 Output Compare + b6 $4 bitmask: ASSR.OCR2BUB \ Timer/Counter2 Output Compare + $2 constant ASSR_TCR2AUB \ Timer/Counter2 Control Registe + b6 $2 bitmask: ASSR.TCR2AUB \ Timer/Counter2 Control Registe + $1 constant ASSR_TCR2BUB \ Timer/Counter2 Control Registe + b6 $1 bitmask: ASSR.TCR2BUB \ Timer/Counter2 Control Registe +$43 constant GTCCR \ General Timer Counter Control + $80 constant GTCCR_TSM \ Timer/Counter Synchronization + 43 $80 bitmask: GTCCR.TSM \ Timer/Counter Synchronization + $2 constant GTCCR_PSRASY \ Prescaler Reset Timer/Counter2 + 43 $2 bitmask: GTCCR.PSRASY \ Prescaler Reset Timer/Counter2 diff --git a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/TIMER_COUNTER_3.frt b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/TIMER_COUNTER_3.frt new file mode 100644 index 0000000..30d6566 --- /dev/null +++ b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/TIMER_COUNTER_3.frt @@ -0,0 +1,68 @@ +\ Generated automatically for atmega256rfr2 +\ #require bitnames.frt + +\ TIMER_COUNTER_3 +$90 constant TCCR3A \ Timer/Counter3 Control Registe + $c0 constant TCCR3A_COM3A \ Compare Output Mode for Channe + 90 $c0 bitmask: TCCR3A.COM3A \ Compare Output Mode for Channe + $30 constant TCCR3A_COM3B \ Compare Output Mode for Channe + 90 $30 bitmask: TCCR3A.COM3B \ Compare Output Mode for Channe + $c constant TCCR3A_COM3C \ Compare Output Mode for Channe + 90 $c bitmask: TCCR3A.COM3C \ Compare Output Mode for Channe + $3 constant TCCR3A_WGM3 \ Waveform Generation Mode + 90 $3 bitmask: TCCR3A.WGM3 \ Waveform Generation Mode +$91 constant TCCR3B \ Timer/Counter3 Control Registe + $80 constant TCCR3B_ICNC3 \ Input Capture 3 Noise Cancelle + 91 $80 bitmask: TCCR3B.ICNC3 \ Input Capture 3 Noise Cancelle + $40 constant TCCR3B_ICES3 \ Input Capture 3 Edge Select + 91 $40 bitmask: TCCR3B.ICES3 \ Input Capture 3 Edge Select + $20 constant TCCR3B_Res \ Reserved Bit + 91 $20 bitmask: TCCR3B.Res \ Reserved Bit + $18 constant TCCR3B_WGM3 \ Waveform Generation Mode + 91 $18 bitmask: TCCR3B.WGM3 \ Waveform Generation Mode + $7 constant TCCR3B_CS3 \ Clock Select + 91 $7 bitmask: TCCR3B.CS3 \ Clock Select +$92 constant TCCR3C \ Timer/Counter3 Control Registe + $80 constant TCCR3C_FOC3A \ Force Output Compare for Chann + 92 $80 bitmask: TCCR3C.FOC3A \ Force Output Compare for Chann + $40 constant TCCR3C_FOC3B \ Force Output Compare for Chann + 92 $40 bitmask: TCCR3C.FOC3B \ Force Output Compare for Chann + $20 constant TCCR3C_FOC3C \ Force Output Compare for Chann + 92 $20 bitmask: TCCR3C.FOC3C \ Force Output Compare for Chann + $1f constant TCCR3C_Res \ Reserved + 92 $1f bitmask: TCCR3C.Res \ Reserved +$94 constant TCNT3 \ Timer/Counter3 Bytes +$98 constant OCR3A \ Timer/Counter3 Output Compare +$9a constant OCR3B \ Timer/Counter3 Output Compare +$9c constant OCR3C \ Timer/Counter3 Output Compare +$96 constant ICR3 \ Timer/Counter3 Input Capture R +$71 constant TIMSK3 \ Timer/Counter3 Interrupt Mask + $c0 constant TIMSK3_Res \ Reserved Bit + 71 $c0 bitmask: TIMSK3.Res \ Reserved Bit + $20 constant TIMSK3_ICIE3 \ Timer/Counter3 Input Capture I + 71 $20 bitmask: TIMSK3.ICIE3 \ Timer/Counter3 Input Capture I + $10 constant TIMSK3_Res \ Reserved Bit + 71 $10 bitmask: TIMSK3.Res \ Reserved Bit + $8 constant TIMSK3_OCIE3C \ Timer/Counter3 Output Compare + 71 $8 bitmask: TIMSK3.OCIE3C \ Timer/Counter3 Output Compare + $4 constant TIMSK3_OCIE3B \ Timer/Counter3 Output Compare + 71 $4 bitmask: TIMSK3.OCIE3B \ Timer/Counter3 Output Compare + $2 constant TIMSK3_OCIE3A \ Timer/Counter3 Output Compare + 71 $2 bitmask: TIMSK3.OCIE3A \ Timer/Counter3 Output Compare + $1 constant TIMSK3_TOIE3 \ Timer/Counter3 Overflow Interr + 71 $1 bitmask: TIMSK3.TOIE3 \ Timer/Counter3 Overflow Interr +$38 constant TIFR3 \ Timer/Counter3 Interrupt Flag + $c0 constant TIFR3_Res \ Reserved Bit + 38 $c0 bitmask: TIFR3.Res \ Reserved Bit + $20 constant TIFR3_ICF3 \ Timer/Counter3 Input Capture F + 38 $20 bitmask: TIFR3.ICF3 \ Timer/Counter3 Input Capture F + $10 constant TIFR3_Res \ Reserved Bit + 38 $10 bitmask: TIFR3.Res \ Reserved Bit + $8 constant TIFR3_OCF3C \ Timer/Counter3 Output Compare + 38 $8 bitmask: TIFR3.OCF3C \ Timer/Counter3 Output Compare + $4 constant TIFR3_OCF3B \ Timer/Counter3 Output Compare + 38 $4 bitmask: TIFR3.OCF3B \ Timer/Counter3 Output Compare + $2 constant TIFR3_OCF3A \ Timer/Counter3 Output Compare + 38 $2 bitmask: TIFR3.OCF3A \ Timer/Counter3 Output Compare + $1 constant TIFR3_TOV3 \ Timer/Counter3 Overflow Flag + 38 $1 bitmask: TIFR3.TOV3 \ Timer/Counter3 Overflow Flag diff --git a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/TIMER_COUNTER_4.frt b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/TIMER_COUNTER_4.frt new file mode 100644 index 0000000..4ed5cb6 --- /dev/null +++ b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/TIMER_COUNTER_4.frt @@ -0,0 +1,68 @@ +\ Generated automatically for atmega256rfr2 +\ #require bitnames.frt + +\ TIMER_COUNTER_4 +$a0 constant TCCR4A \ Timer/Counter4 Control Registe + $c0 constant TCCR4A_COM4A \ Compare Output Mode for Channe + a0 $c0 bitmask: TCCR4A.COM4A \ Compare Output Mode for Channe + $30 constant TCCR4A_COM4B \ Compare Output Mode for Channe + a0 $30 bitmask: TCCR4A.COM4B \ Compare Output Mode for Channe + $c constant TCCR4A_COM4C \ Compare Output Mode for Channe + a0 $c bitmask: TCCR4A.COM4C \ Compare Output Mode for Channe + $3 constant TCCR4A_WGM4 \ Waveform Generation Mode + a0 $3 bitmask: TCCR4A.WGM4 \ Waveform Generation Mode +$a1 constant TCCR4B \ Timer/Counter4 Control Registe + $80 constant TCCR4B_ICNC4 \ Input Capture 4 Noise Cancelle + a1 $80 bitmask: TCCR4B.ICNC4 \ Input Capture 4 Noise Cancelle + $40 constant TCCR4B_ICES4 \ Input Capture 4 Edge Select + a1 $40 bitmask: TCCR4B.ICES4 \ Input Capture 4 Edge Select + $20 constant TCCR4B_Res \ Reserved Bit + a1 $20 bitmask: TCCR4B.Res \ Reserved Bit + $18 constant TCCR4B_WGM4 \ Waveform Generation Mode + a1 $18 bitmask: TCCR4B.WGM4 \ Waveform Generation Mode + $7 constant TCCR4B_CS4 \ Clock Select + a1 $7 bitmask: TCCR4B.CS4 \ Clock Select +$a2 constant TCCR4C \ Timer/Counter4 Control Registe + $80 constant TCCR4C_FOC4A \ Force Output Compare for Chann + a2 $80 bitmask: TCCR4C.FOC4A \ Force Output Compare for Chann + $40 constant TCCR4C_FOC4B \ Force Output Compare for Chann + a2 $40 bitmask: TCCR4C.FOC4B \ Force Output Compare for Chann + $20 constant TCCR4C_FOC4C \ Force Output Compare for Chann + a2 $20 bitmask: TCCR4C.FOC4C \ Force Output Compare for Chann + $1f constant TCCR4C_Res \ Reserved + a2 $1f bitmask: TCCR4C.Res \ Reserved +$a4 constant TCNT4 \ Timer/Counter4 Bytes +$a8 constant OCR4A \ Timer/Counter4 Output Compare +$aa constant OCR4B \ Timer/Counter4 Output Compare +$ac constant OCR4C \ Timer/Counter4 Output Compare +$a6 constant ICR4 \ Timer/Counter4 Input Capture R +$72 constant TIMSK4 \ Timer/Counter4 Interrupt Mask + $c0 constant TIMSK4_Res \ Reserved Bit + 72 $c0 bitmask: TIMSK4.Res \ Reserved Bit + $20 constant TIMSK4_ICIE4 \ Timer/Counter4 Input Capture I + 72 $20 bitmask: TIMSK4.ICIE4 \ Timer/Counter4 Input Capture I + $10 constant TIMSK4_Res \ Reserved Bit + 72 $10 bitmask: TIMSK4.Res \ Reserved Bit + $8 constant TIMSK4_OCIE4C \ Timer/Counter4 Output Compare + 72 $8 bitmask: TIMSK4.OCIE4C \ Timer/Counter4 Output Compare + $4 constant TIMSK4_OCIE4B \ Timer/Counter4 Output Compare + 72 $4 bitmask: TIMSK4.OCIE4B \ Timer/Counter4 Output Compare + $2 constant TIMSK4_OCIE4A \ Timer/Counter4 Output Compare + 72 $2 bitmask: TIMSK4.OCIE4A \ Timer/Counter4 Output Compare + $1 constant TIMSK4_TOIE4 \ Timer/Counter4 Overflow Interr + 72 $1 bitmask: TIMSK4.TOIE4 \ Timer/Counter4 Overflow Interr +$39 constant TIFR4 \ Timer/Counter4 Interrupt Flag + $c0 constant TIFR4_Res \ Reserved Bit + 39 $c0 bitmask: TIFR4.Res \ Reserved Bit + $20 constant TIFR4_ICF4 \ Timer/Counter4 Input Capture F + 39 $20 bitmask: TIFR4.ICF4 \ Timer/Counter4 Input Capture F + $10 constant TIFR4_Res \ Reserved Bit + 39 $10 bitmask: TIFR4.Res \ Reserved Bit + $8 constant TIFR4_OCF4C \ Timer/Counter4 Output Compare + 39 $8 bitmask: TIFR4.OCF4C \ Timer/Counter4 Output Compare + $4 constant TIFR4_OCF4B \ Timer/Counter4 Output Compare + 39 $4 bitmask: TIFR4.OCF4B \ Timer/Counter4 Output Compare + $2 constant TIFR4_OCF4A \ Timer/Counter4 Output Compare + 39 $2 bitmask: TIFR4.OCF4A \ Timer/Counter4 Output Compare + $1 constant TIFR4_TOV4 \ Timer/Counter4 Overflow Flag + 39 $1 bitmask: TIFR4.TOV4 \ Timer/Counter4 Overflow Flag diff --git a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/TIMER_COUNTER_5.frt b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/TIMER_COUNTER_5.frt new file mode 100644 index 0000000..434ee3b --- /dev/null +++ b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/TIMER_COUNTER_5.frt @@ -0,0 +1,68 @@ +\ Generated automatically for atmega256rfr2 +\ #require bitnames.frt + +\ TIMER_COUNTER_5 +$120 constant TCCR5A \ Timer/Counter5 Control Registe + $c0 constant TCCR5A_COM5A \ Compare Output Mode for Channe + 120 $c0 bitmask: TCCR5A.COM5A \ Compare Output Mode for Channe + $30 constant TCCR5A_COM5B \ Compare Output Mode for Channe + 120 $30 bitmask: TCCR5A.COM5B \ Compare Output Mode for Channe + $c constant TCCR5A_COM5C \ Compare Output Mode for Channe + 120 $c bitmask: TCCR5A.COM5C \ Compare Output Mode for Channe + $3 constant TCCR5A_WGM5 \ Waveform Generation Mode + 120 $3 bitmask: TCCR5A.WGM5 \ Waveform Generation Mode +$121 constant TCCR5B \ Timer/Counter5 Control Registe + $80 constant TCCR5B_ICNC5 \ Input Capture 5 Noise Cancelle + 121 $80 bitmask: TCCR5B.ICNC5 \ Input Capture 5 Noise Cancelle + $40 constant TCCR5B_ICES5 \ Input Capture 5 Edge Select + 121 $40 bitmask: TCCR5B.ICES5 \ Input Capture 5 Edge Select + $20 constant TCCR5B_Res \ Reserved Bit + 121 $20 bitmask: TCCR5B.Res \ Reserved Bit + $18 constant TCCR5B_WGM5 \ Waveform Generation Mode + 121 $18 bitmask: TCCR5B.WGM5 \ Waveform Generation Mode + $7 constant TCCR5B_CS5 \ Clock Select + 121 $7 bitmask: TCCR5B.CS5 \ Clock Select +$122 constant TCCR5C \ Timer/Counter5 Control Registe + $80 constant TCCR5C_FOC5A \ Force Output Compare for Chann + 122 $80 bitmask: TCCR5C.FOC5A \ Force Output Compare for Chann + $40 constant TCCR5C_FOC5B \ Force Output Compare for Chann + 122 $40 bitmask: TCCR5C.FOC5B \ Force Output Compare for Chann + $20 constant TCCR5C_FOC5C \ Force Output Compare for Chann + 122 $20 bitmask: TCCR5C.FOC5C \ Force Output Compare for Chann + $1f constant TCCR5C_Res \ Reserved + 122 $1f bitmask: TCCR5C.Res \ Reserved +$124 constant TCNT5 \ Timer/Counter5 Bytes +$128 constant OCR5A \ Timer/Counter5 Output Compare +$12a constant OCR5B \ Timer/Counter5 Output Compare +$12c constant OCR5C \ Timer/Counter5 Output Compare +$126 constant ICR5 \ Timer/Counter5 Input Capture R +$73 constant TIMSK5 \ Timer/Counter5 Interrupt Mask + $c0 constant TIMSK5_Res \ Reserved Bit + 73 $c0 bitmask: TIMSK5.Res \ Reserved Bit + $20 constant TIMSK5_ICIE5 \ Timer/Counter5 Input Capture I + 73 $20 bitmask: TIMSK5.ICIE5 \ Timer/Counter5 Input Capture I + $10 constant TIMSK5_Res \ Reserved Bit + 73 $10 bitmask: TIMSK5.Res \ Reserved Bit + $8 constant TIMSK5_OCIE5C \ Timer/Counter5 Output Compare + 73 $8 bitmask: TIMSK5.OCIE5C \ Timer/Counter5 Output Compare + $4 constant TIMSK5_OCIE5B \ Timer/Counter5 Output Compare + 73 $4 bitmask: TIMSK5.OCIE5B \ Timer/Counter5 Output Compare + $2 constant TIMSK5_OCIE5A \ Timer/Counter5 Output Compare + 73 $2 bitmask: TIMSK5.OCIE5A \ Timer/Counter5 Output Compare + $1 constant TIMSK5_TOIE5 \ Timer/Counter5 Overflow Interr + 73 $1 bitmask: TIMSK5.TOIE5 \ Timer/Counter5 Overflow Interr +$3a constant TIFR5 \ Timer/Counter5 Interrupt Flag + $c0 constant TIFR5_Res \ Reserved Bit + 3a $c0 bitmask: TIFR5.Res \ Reserved Bit + $20 constant TIFR5_ICF5 \ Timer/Counter5 Input Capture F + 3a $20 bitmask: TIFR5.ICF5 \ Timer/Counter5 Input Capture F + $10 constant TIFR5_Res \ Reserved Bit + 3a $10 bitmask: TIFR5.Res \ Reserved Bit + $8 constant TIFR5_OCF5C \ Timer/Counter5 Output Compare + 3a $8 bitmask: TIFR5.OCF5C \ Timer/Counter5 Output Compare + $4 constant TIFR5_OCF5B \ Timer/Counter5 Output Compare + 3a $4 bitmask: TIFR5.OCF5B \ Timer/Counter5 Output Compare + $2 constant TIFR5_OCF5A \ Timer/Counter5 Output Compare + 3a $2 bitmask: TIFR5.OCF5A \ Timer/Counter5 Output Compare + $1 constant TIFR5_TOV5 \ Timer/Counter5 Overflow Flag + 3a $1 bitmask: TIFR5.TOV5 \ Timer/Counter5 Overflow Flag diff --git a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/TRX24.frt b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/TRX24.frt new file mode 100644 index 0000000..d8c6290 --- /dev/null +++ b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/TRX24.frt @@ -0,0 +1,495 @@ +\ Generated automatically for atmega256rfr2 +\ #require bitnames.frt + +\ TRX24 +$138 constant PARCR \ Power Amplifier Ramp up/down C + $e0 constant PARCR_PALTD \ ext. PA Ramp Down Lead Time + 138 $e0 bitmask: PARCR.PALTD \ ext. PA Ramp Down Lead Time + $1c constant PARCR_PALTU \ ext. PA Ramp Up Lead Time + 138 $1c bitmask: PARCR.PALTU \ ext. PA Ramp Up Lead Time + $2 constant PARCR_PARDFI \ Power Amplifier Ramp Down Freq + 138 $2 bitmask: PARCR.PARDFI \ Power Amplifier Ramp Down Freq + $1 constant PARCR_PARUFI \ Power Amplifier Ramp Up Freque + 138 $1 bitmask: PARCR.PARUFI \ Power Amplifier Ramp Up Freque +$10e constant MAFSA0L \ Transceiver MAC Short Address + $ff constant MAFSA0L_MAFSA0L \ MAC Short Address low Byte for + 10e $ff bitmask: MAFSA0L.MAFSA0L \ MAC Short Address low Byte for +$10f constant MAFSA0H \ Transceiver MAC Short Address + $ff constant MAFSA0H_MAFSA0H \ MAC Short Address high Byte fo + 10f $ff bitmask: MAFSA0H.MAFSA0H \ MAC Short Address high Byte fo +$110 constant MAFPA0L \ Transceiver Personal Area Netw + $ff constant MAFPA0L_MAFPA0L \ MAC Personal Area Network ID l + 110 $ff bitmask: MAFPA0L.MAFPA0L \ MAC Personal Area Network ID l +$111 constant MAFPA0H \ Transceiver Personal Area Netw + $ff constant MAFPA0H_MAFPA0H \ MAC Personal Area Network ID h + 111 $ff bitmask: MAFPA0H.MAFPA0H \ MAC Personal Area Network ID h +$112 constant MAFSA1L \ Transceiver MAC Short Address + $ff constant MAFSA1L_MAFSA1L \ MAC Short Address low Byte for + 112 $ff bitmask: MAFSA1L.MAFSA1L \ MAC Short Address low Byte for +$113 constant MAFSA1H \ Transceiver MAC Short Address + $ff constant MAFSA1H_MAFSA1H \ MAC Short Address high Byte fo + 113 $ff bitmask: MAFSA1H.MAFSA1H \ MAC Short Address high Byte fo +$114 constant MAFPA1L \ Transceiver Personal Area Netw + $ff constant MAFPA1L_MAFPA1L \ MAC Personal Area Network ID l + 114 $ff bitmask: MAFPA1L.MAFPA1L \ MAC Personal Area Network ID l +$115 constant MAFPA1H \ Transceiver Personal Area Netw + $ff constant MAFPA1H_MAFPA1H \ MAC Personal Area Network ID h + 115 $ff bitmask: MAFPA1H.MAFPA1H \ MAC Personal Area Network ID h +$116 constant MAFSA2L \ Transceiver MAC Short Address + $ff constant MAFSA2L_MAFSA2L \ MAC Short Address low Byte for + 116 $ff bitmask: MAFSA2L.MAFSA2L \ MAC Short Address low Byte for +$117 constant MAFSA2H \ Transceiver MAC Short Address + $ff constant MAFSA2H_MAFSA2H \ MAC Short Address high Byte fo + 117 $ff bitmask: MAFSA2H.MAFSA2H \ MAC Short Address high Byte fo +$118 constant MAFPA2L \ Transceiver Personal Area Netw + $ff constant MAFPA2L_MAFPA2L \ MAC Personal Area Network ID l + 118 $ff bitmask: MAFPA2L.MAFPA2L \ MAC Personal Area Network ID l +$119 constant MAFPA2H \ Transceiver Personal Area Netw + $ff constant MAFPA2H_MAFPA2H \ MAC Personal Area Network ID h + 119 $ff bitmask: MAFPA2H.MAFPA2H \ MAC Personal Area Network ID h +$11a constant MAFSA3L \ Transceiver MAC Short Address + $ff constant MAFSA3L_MAFSA3L \ MAC Short Address low Byte for + 11a $ff bitmask: MAFSA3L.MAFSA3L \ MAC Short Address low Byte for +$11b constant MAFSA3H \ Transceiver MAC Short Address + $ff constant MAFSA3H_MAFSA3H \ MAC Short Address high Byte fo + 11b $ff bitmask: MAFSA3H.MAFSA3H \ MAC Short Address high Byte fo +$11c constant MAFPA3L \ Transceiver Personal Area Netw + $ff constant MAFPA3L_MAFPA3L \ MAC Personal Area Network ID l + 11c $ff bitmask: MAFPA3L.MAFPA3L \ MAC Personal Area Network ID l +$11d constant MAFPA3H \ Transceiver Personal Area Netw + $ff constant MAFPA3H_MAFPA3H \ MAC Personal Area Network ID h + 11d $ff bitmask: MAFPA3H.MAFPA3H \ MAC Personal Area Network ID h +$10c constant MAFCR0 \ Multiple Address Filter Config + $f0 constant MAFCR0_Res \ Reserved Bit + 10c $f0 bitmask: MAFCR0.Res \ Reserved Bit + $8 constant MAFCR0_MAF3EN \ Multiple Address Filter 3 Enab + 10c $8 bitmask: MAFCR0.MAF3EN \ Multiple Address Filter 3 Enab + $4 constant MAFCR0_MAF2EN \ Multiple Address Filter 2 Enab + 10c $4 bitmask: MAFCR0.MAF2EN \ Multiple Address Filter 2 Enab + $2 constant MAFCR0_MAF1EN \ Multiple Address Filter 1 Enab + 10c $2 bitmask: MAFCR0.MAF1EN \ Multiple Address Filter 1 Enab + $1 constant MAFCR0_MAF0EN \ Multiple Address Filter 0 Enab + 10c $1 bitmask: MAFCR0.MAF0EN \ Multiple Address Filter 0 Enab +$10d constant MAFCR1 \ Multiple Address Filter Config + $80 constant MAFCR1_AACK_3_SET_PD \ Set Data Pending bit for addre + 10d $80 bitmask: MAFCR1.AACK_3_SET_PD \ Set Data Pending bit for addre + $40 constant MAFCR1_AACK_3_I_AM_COORD \ Enable PAN Coordinator mode fo + 10d $40 bitmask: MAFCR1.AACK_3_I_AM_COORD \ Enable PAN Coordinator mode fo + $20 constant MAFCR1_AACK_2_SET_PD \ Set Data Pending bit for addre + 10d $20 bitmask: MAFCR1.AACK_2_SET_PD \ Set Data Pending bit for addre + $10 constant MAFCR1_AACK_2_I_AM_COORD \ Enable PAN Coordinator mode fo + 10d $10 bitmask: MAFCR1.AACK_2_I_AM_COORD \ Enable PAN Coordinator mode fo + $8 constant MAFCR1_AACK_1_SET_PD \ Set Data Pending bit for addre + 10d $8 bitmask: MAFCR1.AACK_1_SET_PD \ Set Data Pending bit for addre + $4 constant MAFCR1_AACK_1_I_AM_COORD \ Enable PAN Coordinator mode fo + 10d $4 bitmask: MAFCR1.AACK_1_I_AM_COORD \ Enable PAN Coordinator mode fo + $2 constant MAFCR1_AACK_0_SET_PD \ Set Data Pending bit for addre + 10d $2 bitmask: MAFCR1.AACK_0_SET_PD \ Set Data Pending bit for addre + $1 constant MAFCR1_AACK_0_I_AM_COORD \ Enable PAN Coordinator mode fo + 10d $1 bitmask: MAFCR1.AACK_0_I_AM_COORD \ Enable PAN Coordinator mode fo +$13c constant AES_CTRL \ AES Control Register + $80 constant AES_CTRL_AES_REQUEST \ Request AES Operation. + 13c $80 bitmask: AES_CTRL.AES_REQUEST \ Request AES Operation. + $40 constant AES_CTRL_Res \ Reserved Bit + 13c $40 bitmask: AES_CTRL.Res \ Reserved Bit + $20 constant AES_CTRL_AES_MODE \ Set AES Operation Mode + 13c $20 bitmask: AES_CTRL.AES_MODE \ Set AES Operation Mode + $10 constant AES_CTRL_Res \ Reserved Bit + 13c $10 bitmask: AES_CTRL.Res \ Reserved Bit + $8 constant AES_CTRL_AES_DIR \ Set AES Operation Direction + 13c $8 bitmask: AES_CTRL.AES_DIR \ Set AES Operation Direction + $4 constant AES_CTRL_AES_IM \ AES Interrupt Enable + 13c $4 bitmask: AES_CTRL.AES_IM \ AES Interrupt Enable + $3 constant AES_CTRL_Res \ Reserved Bit + 13c $3 bitmask: AES_CTRL.Res \ Reserved Bit +$13d constant AES_STATUS \ AES Status Register + $80 constant AES_STATUS_AES_ER \ AES Operation Finished with Er + 13d $80 bitmask: AES_STATUS.AES_ER \ AES Operation Finished with Er + $7e constant AES_STATUS_Res \ Reserved + 13d $7e bitmask: AES_STATUS.Res \ Reserved + $1 constant AES_STATUS_AES_DONE \ AES Operation Finished with Su + 13d $1 bitmask: AES_STATUS.AES_DONE \ AES Operation Finished with Su +$13e constant AES_STATE \ AES Plain and Cipher Text Buff + $ff constant AES_STATE_AES_STATE \ AES Plain and Cipher Text Buff + 13e $ff bitmask: AES_STATE.AES_STATE \ AES Plain and Cipher Text Buff +$13f constant AES_KEY \ AES Encryption and Decryption + $ff constant AES_KEY_AES_KEY \ AES Encryption/Decryption Key + 13f $ff bitmask: AES_KEY.AES_KEY \ AES Encryption/Decryption Key +$141 constant TRX_STATUS \ Transceiver Status Register + $80 constant TRX_STATUS_CCA_DONE \ CCA Algorithm Status + 141 $80 bitmask: TRX_STATUS.CCA_DONE \ CCA Algorithm Status + $40 constant TRX_STATUS_CCA_STATUS \ CCA Status Result + 141 $40 bitmask: TRX_STATUS.CCA_STATUS \ CCA Status Result + $20 constant TRX_STATUS_TST_STATUS \ Test mode status + 141 $20 bitmask: TRX_STATUS.TST_STATUS \ Test mode status + $1f constant TRX_STATUS_TRX_STATUS \ Transceiver Main Status + 141 $1f bitmask: TRX_STATUS.TRX_STATUS \ Transceiver Main Status +$142 constant TRX_STATE \ Transceiver State Control Regi + $e0 constant TRX_STATE_TRAC_STATUS \ Transaction Status + 142 $e0 bitmask: TRX_STATE.TRAC_STATUS \ Transaction Status + $1f constant TRX_STATE_TRX_CMD \ State Control Command + 142 $1f bitmask: TRX_STATE.TRX_CMD \ State Control Command +$143 constant TRX_CTRL_0 \ Reserved + $80 constant TRX_CTRL_0_Res7 \ Reserved + 143 $80 bitmask: TRX_CTRL_0.Res7 \ Reserved + $40 constant TRX_CTRL_0_PMU_EN \ Enable Phase Measurement Unit + 143 $40 bitmask: TRX_CTRL_0.PMU_EN \ Enable Phase Measurement Unit + $20 constant TRX_CTRL_0_PMU_START \ Start of Phase Measurement Uni + 143 $20 bitmask: TRX_CTRL_0.PMU_START \ Start of Phase Measurement Uni + $10 constant TRX_CTRL_0_PMU_IF_INV \ PMU IF Inverse + 143 $10 bitmask: TRX_CTRL_0.PMU_IF_INV \ PMU IF Inverse + $f constant TRX_CTRL_0_Res \ Reserved + 143 $f bitmask: TRX_CTRL_0.Res \ Reserved +$144 constant TRX_CTRL_1 \ Transceiver Control Register 1 + $80 constant TRX_CTRL_1_PA_EXT_EN \ External PA support enable + 144 $80 bitmask: TRX_CTRL_1.PA_EXT_EN \ External PA support enable + $40 constant TRX_CTRL_1_IRQ_2_EXT_EN \ Connect Frame Start IRQ to TC1 + 144 $40 bitmask: TRX_CTRL_1.IRQ_2_EXT_EN \ Connect Frame Start IRQ to TC1 + $20 constant TRX_CTRL_1_TX_AUTO_CRC_ON \ Enable Automatic CRC Calculati + 144 $20 bitmask: TRX_CTRL_1.TX_AUTO_CRC_ON \ Enable Automatic CRC Calculati + $10 constant TRX_CTRL_1_PLL_TX_FLT \ Enable PLL TX filter + 144 $10 bitmask: TRX_CTRL_1.PLL_TX_FLT \ Enable PLL TX filter + $f constant TRX_CTRL_1_Res \ Reserved + 144 $f bitmask: TRX_CTRL_1.Res \ Reserved +$145 constant PHY_TX_PWR \ Transceiver Transmit Power Con + $f0 constant PHY_TX_PWR_Res \ Reserved + 145 $f0 bitmask: PHY_TX_PWR.Res \ Reserved + $f constant PHY_TX_PWR_TX_PWR \ Transmit Power Setting + 145 $f bitmask: PHY_TX_PWR.TX_PWR \ Transmit Power Setting +$146 constant PHY_RSSI \ Receiver Signal Strength Indic + $80 constant PHY_RSSI_RX_CRC_VALID \ Received Frame CRC Status + 146 $80 bitmask: PHY_RSSI.RX_CRC_VALID \ Received Frame CRC Status + $60 constant PHY_RSSI_RND_VALUE \ Random Value + 146 $60 bitmask: PHY_RSSI.RND_VALUE \ Random Value + $1f constant PHY_RSSI_RSSI \ Receiver Signal Strength Indic + 146 $1f bitmask: PHY_RSSI.RSSI \ Receiver Signal Strength Indic +$147 constant PHY_ED_LEVEL \ Transceiver Energy Detection L + $ff constant PHY_ED_LEVEL_ED_LEVEL \ Energy Detection Level + 147 $ff bitmask: PHY_ED_LEVEL.ED_LEVEL \ Energy Detection Level +$148 constant PHY_CC_CCA \ Transceiver Clear Channel Asse + $80 constant PHY_CC_CCA_CCA_REQUEST \ Manual CCA Measurement Request + 148 $80 bitmask: PHY_CC_CCA.CCA_REQUEST \ Manual CCA Measurement Request + $60 constant PHY_CC_CCA_CCA_MODE \ Select CCA Measurement Mode + 148 $60 bitmask: PHY_CC_CCA.CCA_MODE \ Select CCA Measurement Mode + $1f constant PHY_CC_CCA_CHANNEL \ RX/TX Channel Selection + 148 $1f bitmask: PHY_CC_CCA.CHANNEL \ RX/TX Channel Selection +$149 constant CCA_THRES \ Transceiver CCA Threshold Sett + $f0 constant CCA_THRES_CCA_CS_THRES \ CS Threshold Level for CCA Mea + 149 $f0 bitmask: CCA_THRES.CCA_CS_THRES \ CS Threshold Level for CCA Mea + $f constant CCA_THRES_CCA_ED_THRES \ ED Threshold Level for CCA Mea + 149 $f bitmask: CCA_THRES.CCA_ED_THRES \ ED Threshold Level for CCA Mea +$14a constant RX_CTRL \ Transceiver Receive Control Re + $f constant RX_CTRL_PDT_THRES \ Receiver Sensitivity Control + 14a $f bitmask: RX_CTRL.PDT_THRES \ Receiver Sensitivity Control +$14b constant SFD_VALUE \ Start of Frame Delimiter Value + $ff constant SFD_VALUE_SFD_VALUE \ Start of Frame Delimiter Value + 14b $ff bitmask: SFD_VALUE.SFD_VALUE \ Start of Frame Delimiter Value +$14c constant TRX_CTRL_2 \ Transceiver Control Register 2 + $80 constant TRX_CTRL_2_RX_SAFE_MODE \ RX Safe Mode + 14c $80 bitmask: TRX_CTRL_2.RX_SAFE_MODE \ RX Safe Mode + $7c constant TRX_CTRL_2_Res \ Reserved + 14c $7c bitmask: TRX_CTRL_2.Res \ Reserved + $3 constant TRX_CTRL_2_OQPSK_DATA_RATE \ Data Rate Selection + 14c $3 bitmask: TRX_CTRL_2.OQPSK_DATA_RATE \ Data Rate Selection +$14d constant ANT_DIV \ Antenna Diversity Control Regi + $80 constant ANT_DIV_ANT_SEL \ Antenna Diversity Antenna Stat + 14d $80 bitmask: ANT_DIV.ANT_SEL \ Antenna Diversity Antenna Stat + $70 constant ANT_DIV_Res \ Reserved + 14d $70 bitmask: ANT_DIV.Res \ Reserved + $8 constant ANT_DIV_ANT_DIV_EN \ Enable Antenna Diversity + 14d $8 bitmask: ANT_DIV.ANT_DIV_EN \ Enable Antenna Diversity + $4 constant ANT_DIV_ANT_EXT_SW_EN \ Enable External Antenna Switch + 14d $4 bitmask: ANT_DIV.ANT_EXT_SW_EN \ Enable External Antenna Switch + $3 constant ANT_DIV_ANT_CTRL \ Static Antenna Diversity Switc + 14d $3 bitmask: ANT_DIV.ANT_CTRL \ Static Antenna Diversity Switc +$14e constant IRQ_MASK \ Transceiver Interrupt Enable R + $80 constant IRQ_MASK_AWAKE_EN \ Awake Interrupt Enable + 14e $80 bitmask: IRQ_MASK.AWAKE_EN \ Awake Interrupt Enable + $40 constant IRQ_MASK_TX_END_EN \ TX_END Interrupt Enable + 14e $40 bitmask: IRQ_MASK.TX_END_EN \ TX_END Interrupt Enable + $20 constant IRQ_MASK_AMI_EN \ Address Match Interrupt Enable + 14e $20 bitmask: IRQ_MASK.AMI_EN \ Address Match Interrupt Enable + $10 constant IRQ_MASK_CCA_ED_DONE_EN \ End of ED Measurement Interrup + 14e $10 bitmask: IRQ_MASK.CCA_ED_DONE_EN \ End of ED Measurement Interrup + $8 constant IRQ_MASK_RX_END_EN \ RX_END Interrupt Enable + 14e $8 bitmask: IRQ_MASK.RX_END_EN \ RX_END Interrupt Enable + $4 constant IRQ_MASK_RX_START_EN \ RX_START Interrupt Enable + 14e $4 bitmask: IRQ_MASK.RX_START_EN \ RX_START Interrupt Enable + $2 constant IRQ_MASK_PLL_UNLOCK_EN \ PLL Unlock Interrupt Enable + 14e $2 bitmask: IRQ_MASK.PLL_UNLOCK_EN \ PLL Unlock Interrupt Enable + $1 constant IRQ_MASK_PLL_LOCK_EN \ PLL Lock Interrupt Enable + 14e $1 bitmask: IRQ_MASK.PLL_LOCK_EN \ PLL Lock Interrupt Enable +$14f constant IRQ_STATUS \ Transceiver Interrupt Status R + $80 constant IRQ_STATUS_AWAKE \ Awake Interrupt Status + 14f $80 bitmask: IRQ_STATUS.AWAKE \ Awake Interrupt Status + $40 constant IRQ_STATUS_TX_END \ TX_END Interrupt Status + 14f $40 bitmask: IRQ_STATUS.TX_END \ TX_END Interrupt Status + $20 constant IRQ_STATUS_AMI \ Address Match Interrupt Status + 14f $20 bitmask: IRQ_STATUS.AMI \ Address Match Interrupt Status + $10 constant IRQ_STATUS_CCA_ED_DONE \ End of ED Measurement Interrup + 14f $10 bitmask: IRQ_STATUS.CCA_ED_DONE \ End of ED Measurement Interrup + $8 constant IRQ_STATUS_RX_END \ RX_END Interrupt Status + 14f $8 bitmask: IRQ_STATUS.RX_END \ RX_END Interrupt Status + $4 constant IRQ_STATUS_RX_START \ RX_START Interrupt Status + 14f $4 bitmask: IRQ_STATUS.RX_START \ RX_START Interrupt Status + $2 constant IRQ_STATUS_PLL_UNLOCK \ PLL Unlock Interrupt Status + 14f $2 bitmask: IRQ_STATUS.PLL_UNLOCK \ PLL Unlock Interrupt Status + $1 constant IRQ_STATUS_PLL_LOCK \ PLL Lock Interrupt Status + 14f $1 bitmask: IRQ_STATUS.PLL_LOCK \ PLL Lock Interrupt Status +$be constant IRQ_MASK1 \ Transceiver Interrupt Enable R + $e0 constant IRQ_MASK1_Res \ Reserved Bit + be $e0 bitmask: IRQ_MASK1.Res \ Reserved Bit + $10 constant IRQ_MASK1_MAF_3_AMI_EN \ Address Match Interrupt enable + be $10 bitmask: IRQ_MASK1.MAF_3_AMI_EN \ Address Match Interrupt enable + $8 constant IRQ_MASK1_MAF_2_AMI_EN \ Address Match Interrupt enable + be $8 bitmask: IRQ_MASK1.MAF_2_AMI_EN \ Address Match Interrupt enable + $4 constant IRQ_MASK1_MAF_1_AMI_EN \ Address Match Interrupt enable + be $4 bitmask: IRQ_MASK1.MAF_1_AMI_EN \ Address Match Interrupt enable + $2 constant IRQ_MASK1_MAF_0_AMI_EN \ Address Match Interrupt enable + be $2 bitmask: IRQ_MASK1.MAF_0_AMI_EN \ Address Match Interrupt enable + $1 constant IRQ_MASK1_TX_START_EN \ Transmit Start Interrupt enabl + be $1 bitmask: IRQ_MASK1.TX_START_EN \ Transmit Start Interrupt enabl +$bf constant IRQ_STATUS1 \ Transceiver Interrupt Status R + $e0 constant IRQ_STATUS1_Res \ Reserved Bit + bf $e0 bitmask: IRQ_STATUS1.Res \ Reserved Bit + $10 constant IRQ_STATUS1_MAF_3_AMI \ Address Match Interrupt Status + bf $10 bitmask: IRQ_STATUS1.MAF_3_AMI \ Address Match Interrupt Status + $8 constant IRQ_STATUS1_MAF_2_AMI \ Address Match Interrupt Status + bf $8 bitmask: IRQ_STATUS1.MAF_2_AMI \ Address Match Interrupt Status + $4 constant IRQ_STATUS1_MAF_1_AMI \ Address Match Interrupt Status + bf $4 bitmask: IRQ_STATUS1.MAF_1_AMI \ Address Match Interrupt Status + $2 constant IRQ_STATUS1_MAF_0_AMI \ Address Match Interrupt Status + bf $2 bitmask: IRQ_STATUS1.MAF_0_AMI \ Address Match Interrupt Status + $1 constant IRQ_STATUS1_TX_START \ Transmit Start Interrupt Statu + bf $1 bitmask: IRQ_STATUS1.TX_START \ Transmit Start Interrupt Statu +$150 constant VREG_CTRL \ Voltage Regulator Control and + $80 constant VREG_CTRL_AVREG_EXT \ Use External AVDD Regulator + 150 $80 bitmask: VREG_CTRL.AVREG_EXT \ Use External AVDD Regulator + $40 constant VREG_CTRL_AVDD_OK \ AVDD Supply Voltage Valid + 150 $40 bitmask: VREG_CTRL.AVDD_OK \ AVDD Supply Voltage Valid + $8 constant VREG_CTRL_DVREG_EXT \ Use External DVDD Regulator + 150 $8 bitmask: VREG_CTRL.DVREG_EXT \ Use External DVDD Regulator + $4 constant VREG_CTRL_DVDD_OK \ DVDD Supply Voltage Valid + 150 $4 bitmask: VREG_CTRL.DVDD_OK \ DVDD Supply Voltage Valid +$151 constant BATMON \ Battery Monitor Control and St + $80 constant BATMON_BAT_LOW \ Battery Monitor Interrupt Stat + 151 $80 bitmask: BATMON.BAT_LOW \ Battery Monitor Interrupt Stat + $40 constant BATMON_BAT_LOW_EN \ Battery Monitor Interrupt Enab + 151 $40 bitmask: BATMON.BAT_LOW_EN \ Battery Monitor Interrupt Enab + $20 constant BATMON_BATMON_OK \ Battery Monitor Status + 151 $20 bitmask: BATMON.BATMON_OK \ Battery Monitor Status + $10 constant BATMON_BATMON_HR \ Battery Monitor Voltage Range + 151 $10 bitmask: BATMON.BATMON_HR \ Battery Monitor Voltage Range + $f constant BATMON_BATMON_VTH \ Battery Monitor Threshold Volt + 151 $f bitmask: BATMON.BATMON_VTH \ Battery Monitor Threshold Volt +$152 constant XOSC_CTRL \ Crystal Oscillator Control Reg + $f0 constant XOSC_CTRL_XTAL_MODE \ Crystal Oscillator Operating M + 152 $f0 bitmask: XOSC_CTRL.XTAL_MODE \ Crystal Oscillator Operating M + $f constant XOSC_CTRL_XTAL_TRIM \ Crystal Oscillator Load Capaci + 152 $f bitmask: XOSC_CTRL.XTAL_TRIM \ Crystal Oscillator Load Capaci +$153 constant CC_CTRL_0 \ Channel Control Register 0 + $ff constant CC_CTRL_0_CC_NUMBER \ Channel Number + 153 $ff bitmask: CC_CTRL_0.CC_NUMBER \ Channel Number +$154 constant CC_CTRL_1 \ Channel Control Register 1 + $f constant CC_CTRL_1_CC_BAND \ Channel Band + 154 $f bitmask: CC_CTRL_1.CC_BAND \ Channel Band +$155 constant RX_SYN \ Transceiver Receiver Sensitivi + $80 constant RX_SYN_RX_PDT_DIS \ Prevent Frame Reception + 155 $80 bitmask: RX_SYN.RX_PDT_DIS \ Prevent Frame Reception + $40 constant RX_SYN_RX_OVERRIDE \ Receiver Override Function + 155 $40 bitmask: RX_SYN.RX_OVERRIDE \ Receiver Override Function + $30 constant RX_SYN_Res \ Reserved + 155 $30 bitmask: RX_SYN.Res \ Reserved + $f constant RX_SYN_RX_PDT_LEVEL \ Reduce Receiver Sensitivity + 155 $f bitmask: RX_SYN.RX_PDT_LEVEL \ Reduce Receiver Sensitivity +$156 constant TRX_RPC \ Transceiver Reduced Power Cons + $c0 constant TRX_RPC_RX_RPC_CTRL \ Smart Receiving Mode Timing + 156 $c0 bitmask: TRX_RPC.RX_RPC_CTRL \ Smart Receiving Mode Timing + $20 constant TRX_RPC_RX_RPC_EN \ Reciver Smart Receiving Mode E + 156 $20 bitmask: TRX_RPC.RX_RPC_EN \ Reciver Smart Receiving Mode E + $10 constant TRX_RPC_PDT_RPC_EN \ Smart Receiving Mode Reduced S + 156 $10 bitmask: TRX_RPC.PDT_RPC_EN \ Smart Receiving Mode Reduced S + $8 constant TRX_RPC_PLL_RPC_EN \ PLL Smart Receiving Mode Enabl + 156 $8 bitmask: TRX_RPC.PLL_RPC_EN \ PLL Smart Receiving Mode Enabl + $4 constant TRX_RPC_Res0 \ Reserved + 156 $4 bitmask: TRX_RPC.Res0 \ Reserved + $2 constant TRX_RPC_IPAN_RPC_EN \ Smart Receiving Mode IPAN Hand + 156 $2 bitmask: TRX_RPC.IPAN_RPC_EN \ Smart Receiving Mode IPAN Hand + $1 constant TRX_RPC_XAH_RPC_EN \ Smart Receiving in Extended Op + 156 $1 bitmask: TRX_RPC.XAH_RPC_EN \ Smart Receiving in Extended Op +$157 constant XAH_CTRL_1 \ Transceiver Acknowledgment Fra + $c0 constant XAH_CTRL_1_Res \ Reserved Bit + 157 $c0 bitmask: XAH_CTRL_1.Res \ Reserved Bit + $20 constant XAH_CTRL_1_AACK_FLTR_RES_FT \ Filter Reserved Frames + 157 $20 bitmask: XAH_CTRL_1.AACK_FLTR_RES_FT \ Filter Reserved Frames + $10 constant XAH_CTRL_1_AACK_UPLD_RES_FT \ Process Reserved Frames + 157 $10 bitmask: XAH_CTRL_1.AACK_UPLD_RES_FT \ Process Reserved Frames + $8 constant XAH_CTRL_1_Res \ Reserved Bit + 157 $8 bitmask: XAH_CTRL_1.Res \ Reserved Bit + $4 constant XAH_CTRL_1_AACK_ACK_TIME \ Reduce Acknowledgment Time + 157 $4 bitmask: XAH_CTRL_1.AACK_ACK_TIME \ Reduce Acknowledgment Time + $2 constant XAH_CTRL_1_AACK_PROM_MODE \ Enable Promiscuous Mode + 157 $2 bitmask: XAH_CTRL_1.AACK_PROM_MODE \ Enable Promiscuous Mode + $1 constant XAH_CTRL_1_Res \ Reserved Bit + 157 $1 bitmask: XAH_CTRL_1.Res \ Reserved Bit +$158 constant FTN_CTRL \ Transceiver Filter Tuning Cont + $80 constant FTN_CTRL_FTN_START \ Start Calibration Loop of Filt + 158 $80 bitmask: FTN_CTRL.FTN_START \ Start Calibration Loop of Filt +$15a constant PLL_CF \ Transceiver Center Frequency C + $80 constant PLL_CF_PLL_CF_START \ Start Center Frequency Calibra + 15a $80 bitmask: PLL_CF.PLL_CF_START \ Start Center Frequency Calibra +$15b constant PLL_DCU \ Transceiver Delay Cell Calibra + $80 constant PLL_DCU_PLL_DCU_START \ Start Delay Cell Calibration + 15b $80 bitmask: PLL_DCU.PLL_DCU_START \ Start Delay Cell Calibration +$15c constant PART_NUM \ Device Identification Register + $ff constant PART_NUM_PART_NUM \ Part Number + 15c $ff bitmask: PART_NUM.PART_NUM \ Part Number +$15d constant VERSION_NUM \ Device Identification Register + $ff constant VERSION_NUM_VERSION_NUM \ Version Number + 15d $ff bitmask: VERSION_NUM.VERSION_NUM \ Version Number +$15e constant MAN_ID_0 \ Device Identification Register + $80 constant MAN_ID_0_MAN_ID_07 \ Manufacturer ID (Low Byte) + 15e $80 bitmask: MAN_ID_0.MAN_ID_07 \ Manufacturer ID (Low Byte) + $40 constant MAN_ID_0_MAN_ID_06 \ Manufacturer ID (Low Byte) + 15e $40 bitmask: MAN_ID_0.MAN_ID_06 \ Manufacturer ID (Low Byte) + $20 constant MAN_ID_0_MAN_ID_05 \ Manufacturer ID (Low Byte) + 15e $20 bitmask: MAN_ID_0.MAN_ID_05 \ Manufacturer ID (Low Byte) + $10 constant MAN_ID_0_MAN_ID_04 \ Manufacturer ID (Low Byte) + 15e $10 bitmask: MAN_ID_0.MAN_ID_04 \ Manufacturer ID (Low Byte) + $8 constant MAN_ID_0_MAN_ID_03 \ Manufacturer ID (Low Byte) + 15e $8 bitmask: MAN_ID_0.MAN_ID_03 \ Manufacturer ID (Low Byte) + $4 constant MAN_ID_0_MAN_ID_02 \ Manufacturer ID (Low Byte) + 15e $4 bitmask: MAN_ID_0.MAN_ID_02 \ Manufacturer ID (Low Byte) + $2 constant MAN_ID_0_MAN_ID_01 \ Manufacturer ID (Low Byte) + 15e $2 bitmask: MAN_ID_0.MAN_ID_01 \ Manufacturer ID (Low Byte) + $1 constant MAN_ID_0_MAN_ID_00 \ Manufacturer ID (Low Byte) + 15e $1 bitmask: MAN_ID_0.MAN_ID_00 \ Manufacturer ID (Low Byte) +$15f constant MAN_ID_1 \ Device Identification Register + $ff constant MAN_ID_1_MAN_ID_ \ Manufacturer ID (High Byte) + 15f $ff bitmask: MAN_ID_1.MAN_ID_ \ Manufacturer ID (High Byte) +$160 constant SHORT_ADDR_0 \ Transceiver MAC Short Address + $80 constant SHORT_ADDR_0_SHORT_ADDR_07 \ MAC Short Address + 160 $80 bitmask: SHORT_ADDR_0.SHORT_ADDR_07 \ MAC Short Address + $40 constant SHORT_ADDR_0_SHORT_ADDR_06 \ MAC Short Address + 160 $40 bitmask: SHORT_ADDR_0.SHORT_ADDR_06 \ MAC Short Address + $20 constant SHORT_ADDR_0_SHORT_ADDR_05 \ MAC Short Address + 160 $20 bitmask: SHORT_ADDR_0.SHORT_ADDR_05 \ MAC Short Address + $10 constant SHORT_ADDR_0_SHORT_ADDR_04 \ MAC Short Address + 160 $10 bitmask: SHORT_ADDR_0.SHORT_ADDR_04 \ MAC Short Address + $8 constant SHORT_ADDR_0_SHORT_ADDR_03 \ MAC Short Address + 160 $8 bitmask: SHORT_ADDR_0.SHORT_ADDR_03 \ MAC Short Address + $4 constant SHORT_ADDR_0_SHORT_ADDR_02 \ MAC Short Address + 160 $4 bitmask: SHORT_ADDR_0.SHORT_ADDR_02 \ MAC Short Address + $2 constant SHORT_ADDR_0_SHORT_ADDR_01 \ MAC Short Address + 160 $2 bitmask: SHORT_ADDR_0.SHORT_ADDR_01 \ MAC Short Address + $1 constant SHORT_ADDR_0_SHORT_ADDR_00 \ MAC Short Address + 160 $1 bitmask: SHORT_ADDR_0.SHORT_ADDR_00 \ MAC Short Address +$161 constant SHORT_ADDR_1 \ Transceiver MAC Short Address + $ff constant SHORT_ADDR_1_SHORT_ADDR_ \ MAC Short Address + 161 $ff bitmask: SHORT_ADDR_1.SHORT_ADDR_ \ MAC Short Address +$162 constant PAN_ID_0 \ Transceiver Personal Area Netw + $80 constant PAN_ID_0_PAN_ID_07 \ MAC Personal Area Network ID + 162 $80 bitmask: PAN_ID_0.PAN_ID_07 \ MAC Personal Area Network ID + $40 constant PAN_ID_0_PAN_ID_06 \ MAC Personal Area Network ID + 162 $40 bitmask: PAN_ID_0.PAN_ID_06 \ MAC Personal Area Network ID + $20 constant PAN_ID_0_PAN_ID_05 \ MAC Personal Area Network ID + 162 $20 bitmask: PAN_ID_0.PAN_ID_05 \ MAC Personal Area Network ID + $10 constant PAN_ID_0_PAN_ID_04 \ MAC Personal Area Network ID + 162 $10 bitmask: PAN_ID_0.PAN_ID_04 \ MAC Personal Area Network ID + $8 constant PAN_ID_0_PAN_ID_03 \ MAC Personal Area Network ID + 162 $8 bitmask: PAN_ID_0.PAN_ID_03 \ MAC Personal Area Network ID + $4 constant PAN_ID_0_PAN_ID_02 \ MAC Personal Area Network ID + 162 $4 bitmask: PAN_ID_0.PAN_ID_02 \ MAC Personal Area Network ID + $2 constant PAN_ID_0_PAN_ID_01 \ MAC Personal Area Network ID + 162 $2 bitmask: PAN_ID_0.PAN_ID_01 \ MAC Personal Area Network ID + $1 constant PAN_ID_0_PAN_ID_00 \ MAC Personal Area Network ID + 162 $1 bitmask: PAN_ID_0.PAN_ID_00 \ MAC Personal Area Network ID +$163 constant PAN_ID_1 \ Transceiver Personal Area Netw + $ff constant PAN_ID_1_PAN_ID_ \ MAC Personal Area Network ID + 163 $ff bitmask: PAN_ID_1.PAN_ID_ \ MAC Personal Area Network ID +$164 constant IEEE_ADDR_0 \ Transceiver MAC IEEE Address R + $80 constant IEEE_ADDR_0_IEEE_ADDR_07 \ MAC IEEE Address + 164 $80 bitmask: IEEE_ADDR_0.IEEE_ADDR_07 \ MAC IEEE Address + $40 constant IEEE_ADDR_0_IEEE_ADDR_06 \ MAC IEEE Address + 164 $40 bitmask: IEEE_ADDR_0.IEEE_ADDR_06 \ MAC IEEE Address + $20 constant IEEE_ADDR_0_IEEE_ADDR_05 \ MAC IEEE Address + 164 $20 bitmask: IEEE_ADDR_0.IEEE_ADDR_05 \ MAC IEEE Address + $10 constant IEEE_ADDR_0_IEEE_ADDR_04 \ MAC IEEE Address + 164 $10 bitmask: IEEE_ADDR_0.IEEE_ADDR_04 \ MAC IEEE Address + $8 constant IEEE_ADDR_0_IEEE_ADDR_03 \ MAC IEEE Address + 164 $8 bitmask: IEEE_ADDR_0.IEEE_ADDR_03 \ MAC IEEE Address + $4 constant IEEE_ADDR_0_IEEE_ADDR_02 \ MAC IEEE Address + 164 $4 bitmask: IEEE_ADDR_0.IEEE_ADDR_02 \ MAC IEEE Address + $2 constant IEEE_ADDR_0_IEEE_ADDR_01 \ MAC IEEE Address + 164 $2 bitmask: IEEE_ADDR_0.IEEE_ADDR_01 \ MAC IEEE Address + $1 constant IEEE_ADDR_0_IEEE_ADDR_00 \ MAC IEEE Address + 164 $1 bitmask: IEEE_ADDR_0.IEEE_ADDR_00 \ MAC IEEE Address +$165 constant IEEE_ADDR_1 \ Transceiver MAC IEEE Address R + $ff constant IEEE_ADDR_1_IEEE_ADDR_ \ MAC IEEE Address + 165 $ff bitmask: IEEE_ADDR_1.IEEE_ADDR_ \ MAC IEEE Address +$166 constant IEEE_ADDR_2 \ Transceiver MAC IEEE Address R + $ff constant IEEE_ADDR_2_IEEE_ADDR_ \ MAC IEEE Address + 166 $ff bitmask: IEEE_ADDR_2.IEEE_ADDR_ \ MAC IEEE Address +$167 constant IEEE_ADDR_3 \ Transceiver MAC IEEE Address R + $ff constant IEEE_ADDR_3_IEEE_ADDR_ \ MAC IEEE Address + 167 $ff bitmask: IEEE_ADDR_3.IEEE_ADDR_ \ MAC IEEE Address +$168 constant IEEE_ADDR_4 \ Transceiver MAC IEEE Address R + $ff constant IEEE_ADDR_4_IEEE_ADDR_ \ MAC IEEE Address + 168 $ff bitmask: IEEE_ADDR_4.IEEE_ADDR_ \ MAC IEEE Address +$169 constant IEEE_ADDR_5 \ Transceiver MAC IEEE Address R + $ff constant IEEE_ADDR_5_IEEE_ADDR_ \ MAC IEEE Address + 169 $ff bitmask: IEEE_ADDR_5.IEEE_ADDR_ \ MAC IEEE Address +$16a constant IEEE_ADDR_6 \ Transceiver MAC IEEE Address R + $ff constant IEEE_ADDR_6_IEEE_ADDR_ \ MAC IEEE Address + 16a $ff bitmask: IEEE_ADDR_6.IEEE_ADDR_ \ MAC IEEE Address +$16b constant IEEE_ADDR_7 \ Transceiver MAC IEEE Address R + $ff constant IEEE_ADDR_7_IEEE_ADDR_ \ MAC IEEE Address + 16b $ff bitmask: IEEE_ADDR_7.IEEE_ADDR_ \ MAC IEEE Address +$16c constant XAH_CTRL_0 \ Transceiver Extended Operating + $f0 constant XAH_CTRL_0_MAX_FRAME_RETRIES \ Maximum Number of Frame Re-tra + 16c $f0 bitmask: XAH_CTRL_0.MAX_FRAME_RETRIES \ Maximum Number of Frame Re-tra + $e constant XAH_CTRL_0_MAX_CSMA_RETRIES \ Maximum Number of CSMA-CA Proc + 16c $e bitmask: XAH_CTRL_0.MAX_CSMA_RETRIES \ Maximum Number of CSMA-CA Proc + $1 constant XAH_CTRL_0_SLOTTED_OPERATION \ Set Slotted Acknowledgment + 16c $1 bitmask: XAH_CTRL_0.SLOTTED_OPERATION \ Set Slotted Acknowledgment +$16d constant CSMA_SEED_0 \ Transceiver CSMA-CA Random Num + $80 constant CSMA_SEED_0_CSMA_SEED_07 \ Seed Value for CSMA Random Num + 16d $80 bitmask: CSMA_SEED_0.CSMA_SEED_07 \ Seed Value for CSMA Random Num + $40 constant CSMA_SEED_0_CSMA_SEED_06 \ Seed Value for CSMA Random Num + 16d $40 bitmask: CSMA_SEED_0.CSMA_SEED_06 \ Seed Value for CSMA Random Num + $20 constant CSMA_SEED_0_CSMA_SEED_05 \ Seed Value for CSMA Random Num + 16d $20 bitmask: CSMA_SEED_0.CSMA_SEED_05 \ Seed Value for CSMA Random Num + $10 constant CSMA_SEED_0_CSMA_SEED_04 \ Seed Value for CSMA Random Num + 16d $10 bitmask: CSMA_SEED_0.CSMA_SEED_04 \ Seed Value for CSMA Random Num + $8 constant CSMA_SEED_0_CSMA_SEED_03 \ Seed Value for CSMA Random Num + 16d $8 bitmask: CSMA_SEED_0.CSMA_SEED_03 \ Seed Value for CSMA Random Num + $4 constant CSMA_SEED_0_CSMA_SEED_02 \ Seed Value for CSMA Random Num + 16d $4 bitmask: CSMA_SEED_0.CSMA_SEED_02 \ Seed Value for CSMA Random Num + $2 constant CSMA_SEED_0_CSMA_SEED_01 \ Seed Value for CSMA Random Num + 16d $2 bitmask: CSMA_SEED_0.CSMA_SEED_01 \ Seed Value for CSMA Random Num + $1 constant CSMA_SEED_0_CSMA_SEED_00 \ Seed Value for CSMA Random Num + 16d $1 bitmask: CSMA_SEED_0.CSMA_SEED_00 \ Seed Value for CSMA Random Num +$16e constant CSMA_SEED_1 \ Transceiver Acknowledgment Fra + $c0 constant CSMA_SEED_1_AACK_FVN_MODE \ Acknowledgment Frame Filter Mo + 16e $c0 bitmask: CSMA_SEED_1.AACK_FVN_MODE \ Acknowledgment Frame Filter Mo + $20 constant CSMA_SEED_1_AACK_SET_PD \ Set Frame Pending Sub-field + 16e $20 bitmask: CSMA_SEED_1.AACK_SET_PD \ Set Frame Pending Sub-field + $10 constant CSMA_SEED_1_AACK_DIS_ACK \ Disable Acknowledgment Frame T + 16e $10 bitmask: CSMA_SEED_1.AACK_DIS_ACK \ Disable Acknowledgment Frame T + $8 constant CSMA_SEED_1_AACK_I_AM_COORD \ Set Personal Area Network Coor + 16e $8 bitmask: CSMA_SEED_1.AACK_I_AM_COORD \ Set Personal Area Network Coor + $7 constant CSMA_SEED_1_CSMA_SEED_1 \ Seed Value for CSMA Random Num + 16e $7 bitmask: CSMA_SEED_1.CSMA_SEED_1 \ Seed Value for CSMA Random Num +$16f constant CSMA_BE \ Transceiver CSMA-CA Back-off E + $f0 constant CSMA_BE_MAX_BE \ Maximum Back-off Exponent + 16f $f0 bitmask: CSMA_BE.MAX_BE \ Maximum Back-off Exponent + $f constant CSMA_BE_MIN_BE \ Minimum Back-off Exponent + 16f $f bitmask: CSMA_BE.MIN_BE \ Minimum Back-off Exponent +$176 constant TST_CTRL_DIGI \ Transceiver Digital Test Contr + $f constant TST_CTRL_DIGI_TST_CTRL_DIG \ Digital Test Controller Regist + 176 $f bitmask: TST_CTRL_DIGI.TST_CTRL_DIG \ Digital Test Controller Regist +$17b constant TST_RX_LENGTH \ Transceiver Received Frame Len + $ff constant TST_RX_LENGTH_RX_LENGTH \ Received Frame Length + 17b $ff bitmask: TST_RX_LENGTH.RX_LENGTH \ Received Frame Length +$180 constant TRXFBST \ Start of frame buffer +$1ff constant TRXFBEND \ End of frame buffer diff --git a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/TWI.frt b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/TWI.frt new file mode 100644 index 0000000..7ac98fa --- /dev/null +++ b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/TWI.frt @@ -0,0 +1,40 @@ +\ Generated automatically for atmega256rfr2 +\ #require bitnames.frt + +\ TWI +$bd constant TWAMR \ TWI (Slave) Address Mask Regis + $fe constant TWAMR_TWAM \ TWI Address Mask + bd $fe bitmask: TWAMR.TWAM \ TWI Address Mask + $1 constant TWAMR_Res \ Reserved Bit + bd $1 bitmask: TWAMR.Res \ Reserved Bit +$b8 constant TWBR \ TWI Bit Rate Register +$bc constant TWCR \ TWI Control Register + $80 constant TWCR_TWINT \ TWI Interrupt Flag + bc $80 bitmask: TWCR.TWINT \ TWI Interrupt Flag + $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit + bc $40 bitmask: TWCR.TWEA \ TWI Enable Acknowledge Bit + $20 constant TWCR_TWSTA \ TWI START Condition Bit + bc $20 bitmask: TWCR.TWSTA \ TWI START Condition Bit + $10 constant TWCR_TWSTO \ TWI STOP Condition Bit + bc $10 bitmask: TWCR.TWSTO \ TWI STOP Condition Bit + $8 constant TWCR_TWWC \ TWI Write Collision Flag + bc $8 bitmask: TWCR.TWWC \ TWI Write Collision Flag + $4 constant TWCR_TWEN \ TWI Enable Bit + bc $4 bitmask: TWCR.TWEN \ TWI Enable Bit + $2 constant TWCR_Res \ Reserved Bit + bc $2 bitmask: TWCR.Res \ Reserved Bit + $1 constant TWCR_TWIE \ TWI Interrupt Enable + bc $1 bitmask: TWCR.TWIE \ TWI Interrupt Enable +$b9 constant TWSR \ TWI Status Register + $f8 constant TWSR_TWS \ TWI Status + b9 $f8 bitmask: TWSR.TWS \ TWI Status + $4 constant TWSR_Res \ Reserved Bit + b9 $4 bitmask: TWSR.Res \ Reserved Bit + $3 constant TWSR_TWPS \ TWI Prescaler Bits + b9 $3 bitmask: TWSR.TWPS \ TWI Prescaler Bits +$bb constant TWDR \ TWI Data Register +$ba constant TWAR \ TWI (Slave) Address Register + $fe constant TWAR_TWA \ TWI (Slave) Address + ba $fe bitmask: TWAR.TWA \ TWI (Slave) Address + $1 constant TWAR_TWGCE \ TWI General Call Recognition E + ba $1 bitmask: TWAR.TWGCE \ TWI General Call Recognition E diff --git a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/USART0.frt b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/USART0.frt new file mode 100644 index 0000000..3a4431e --- /dev/null +++ b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/USART0.frt @@ -0,0 +1,51 @@ +\ Generated automatically for atmega256rfr2 +\ #require bitnames.frt + +\ USART0 +$c6 constant UDR0 \ USART0 I/O Data Register +$c0 constant UCSR0A \ USART0 Control and Status Regi + $80 constant UCSR0A_RXC0 \ USART Receive Complete + c0 $80 bitmask: UCSR0A.RXC0 \ USART Receive Complete + $40 constant UCSR0A_TXC0 \ USART Transmit Complete + c0 $40 bitmask: UCSR0A.TXC0 \ USART Transmit Complete + $20 constant UCSR0A_UDRE0 \ USART Data Register Empty + c0 $20 bitmask: UCSR0A.UDRE0 \ USART Data Register Empty + $10 constant UCSR0A_FE0 \ Frame Error + c0 $10 bitmask: UCSR0A.FE0 \ Frame Error + $8 constant UCSR0A_DOR0 \ Data OverRun + c0 $8 bitmask: UCSR0A.DOR0 \ Data OverRun + $4 constant UCSR0A_UPE0 \ USART Parity Error + c0 $4 bitmask: UCSR0A.UPE0 \ USART Parity Error + $2 constant UCSR0A_U2X0 \ Double the USART Transmission + c0 $2 bitmask: UCSR0A.U2X0 \ Double the USART Transmission + $1 constant UCSR0A_MPCM0 \ Multi-processor Communication + c0 $1 bitmask: UCSR0A.MPCM0 \ Multi-processor Communication +$c1 constant UCSR0B \ USART0 Control and Status Regi + $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable + c1 $80 bitmask: UCSR0B.RXCIE0 \ RX Complete Interrupt Enable + $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable + c1 $40 bitmask: UCSR0B.TXCIE0 \ TX Complete Interrupt Enable + $20 constant UCSR0B_UDRIE0 \ USART Data Register Empty Inte + c1 $20 bitmask: UCSR0B.UDRIE0 \ USART Data Register Empty Inte + $10 constant UCSR0B_RXEN0 \ Receiver Enable + c1 $10 bitmask: UCSR0B.RXEN0 \ Receiver Enable + $8 constant UCSR0B_TXEN0 \ Transmitter Enable + c1 $8 bitmask: UCSR0B.TXEN0 \ Transmitter Enable + $4 constant UCSR0B_UCSZ02 \ Character Size + c1 $4 bitmask: UCSR0B.UCSZ02 \ Character Size + $2 constant UCSR0B_RXB80 \ Receive Data Bit 8 + c1 $2 bitmask: UCSR0B.RXB80 \ Receive Data Bit 8 + $1 constant UCSR0B_TXB80 \ Transmit Data Bit 8 + c1 $1 bitmask: UCSR0B.TXB80 \ Transmit Data Bit 8 +$c2 constant UCSR0C \ USART0 Control and Status Regi + $c0 constant UCSR0C_UMSEL0 \ USART Mode Select + c2 $c0 bitmask: UCSR0C.UMSEL0 \ USART Mode Select + $30 constant UCSR0C_UPM0 \ Parity Mode + c2 $30 bitmask: UCSR0C.UPM0 \ Parity Mode + $8 constant UCSR0C_USBS0 \ Stop Bit Select + c2 $8 bitmask: UCSR0C.USBS0 \ Stop Bit Select + $6 constant UCSR0C_UCSZ0 \ Character Size + c2 $6 bitmask: UCSR0C.UCSZ0 \ Character Size + $1 constant UCSR0C_UCPOL0 \ Clock Polarity + c2 $1 bitmask: UCSR0C.UCPOL0 \ Clock Polarity +$c4 constant UBRR0 \ USART0 Baud Rate Register Byt diff --git a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/USART0_SPI.frt b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/USART0_SPI.frt new file mode 100644 index 0000000..0acd6b4 --- /dev/null +++ b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/USART0_SPI.frt @@ -0,0 +1,29 @@ +\ Generated automatically for atmega256rfr2 +\ #require bitnames.frt + +\ USART0_SPI +$c0 constant UCSR0A \ USART0 MSPIM Control and Statu + $80 constant UCSR0A_RXC0 \ USART Receive Complete + c0 $80 bitmask: UCSR0A.RXC0 \ USART Receive Complete + $40 constant UCSR0A_TXC0 \ USART Transmit Complete + c0 $40 bitmask: UCSR0A.TXC0 \ USART Transmit Complete + $20 constant UCSR0A_UDRE0 \ USART Data Register Empty + c0 $20 bitmask: UCSR0A.UDRE0 \ USART Data Register Empty +$c1 constant UCSR0B \ USART0 MSPIM Control and Statu + $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable + c1 $80 bitmask: UCSR0B.RXCIE0 \ RX Complete Interrupt Enable + $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable + c1 $40 bitmask: UCSR0B.TXCIE0 \ TX Complete Interrupt Enable + $20 constant UCSR0B_UDRIE0 \ USART Data Register Empty Inte + c1 $20 bitmask: UCSR0B.UDRIE0 \ USART Data Register Empty Inte + $10 constant UCSR0B_RXEN0 \ Receiver Enable + c1 $10 bitmask: UCSR0B.RXEN0 \ Receiver Enable + $8 constant UCSR0B_TXEN0 \ Transmitter Enable + c1 $8 bitmask: UCSR0B.TXEN0 \ Transmitter Enable +$c2 constant UCSR0C \ USART0 MSPIM Control and Statu + $4 constant UCSR0C_UDORD0 \ Data Order + c2 $4 bitmask: UCSR0C.UDORD0 \ Data Order + $2 constant UCSR0C_UCPHA0 \ Clock Phase + c2 $2 bitmask: UCSR0C.UCPHA0 \ Clock Phase + $1 constant UCSR0C_UCPOL0 \ Clock Polarity + c2 $1 bitmask: UCSR0C.UCPOL0 \ Clock Polarity diff --git a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/USART1.frt b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/USART1.frt new file mode 100644 index 0000000..0852262 --- /dev/null +++ b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/USART1.frt @@ -0,0 +1,51 @@ +\ Generated automatically for atmega256rfr2 +\ #require bitnames.frt + +\ USART1 +$ce constant UDR1 \ USART1 I/O Data Register +$c8 constant UCSR1A \ USART1 Control and Status Regi + $80 constant UCSR1A_RXC1 \ USART Receive Complete + c8 $80 bitmask: UCSR1A.RXC1 \ USART Receive Complete + $40 constant UCSR1A_TXC1 \ USART Transmit Complete + c8 $40 bitmask: UCSR1A.TXC1 \ USART Transmit Complete + $20 constant UCSR1A_UDRE1 \ USART Data Register Empty + c8 $20 bitmask: UCSR1A.UDRE1 \ USART Data Register Empty + $10 constant UCSR1A_FE1 \ Frame Error + c8 $10 bitmask: UCSR1A.FE1 \ Frame Error + $8 constant UCSR1A_DOR1 \ Data OverRun + c8 $8 bitmask: UCSR1A.DOR1 \ Data OverRun + $4 constant UCSR1A_UPE1 \ USART Parity Error + c8 $4 bitmask: UCSR1A.UPE1 \ USART Parity Error + $2 constant UCSR1A_U2X1 \ Double the USART Transmission + c8 $2 bitmask: UCSR1A.U2X1 \ Double the USART Transmission + $1 constant UCSR1A_MPCM1 \ Multi-processor Communication + c8 $1 bitmask: UCSR1A.MPCM1 \ Multi-processor Communication +$c9 constant UCSR1B \ USART1 Control and Status Regi + $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable + c9 $80 bitmask: UCSR1B.RXCIE1 \ RX Complete Interrupt Enable + $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable + c9 $40 bitmask: UCSR1B.TXCIE1 \ TX Complete Interrupt Enable + $20 constant UCSR1B_UDRIE1 \ USART Data Register Empty Inte + c9 $20 bitmask: UCSR1B.UDRIE1 \ USART Data Register Empty Inte + $10 constant UCSR1B_RXEN1 \ Receiver Enable + c9 $10 bitmask: UCSR1B.RXEN1 \ Receiver Enable + $8 constant UCSR1B_TXEN1 \ Transmitter Enable + c9 $8 bitmask: UCSR1B.TXEN1 \ Transmitter Enable + $4 constant UCSR1B_UCSZ12 \ Character Size + c9 $4 bitmask: UCSR1B.UCSZ12 \ Character Size + $2 constant UCSR1B_RXB81 \ Receive Data Bit 8 + c9 $2 bitmask: UCSR1B.RXB81 \ Receive Data Bit 8 + $1 constant UCSR1B_TXB81 \ Transmit Data Bit 8 + c9 $1 bitmask: UCSR1B.TXB81 \ Transmit Data Bit 8 +$ca constant UCSR1C \ USART1 Control and Status Regi + $c0 constant UCSR1C_UMSEL1 \ USART Mode Select + ca $c0 bitmask: UCSR1C.UMSEL1 \ USART Mode Select + $30 constant UCSR1C_UPM1 \ Parity Mode + ca $30 bitmask: UCSR1C.UPM1 \ Parity Mode + $8 constant UCSR1C_USBS1 \ Stop Bit Select + ca $8 bitmask: UCSR1C.USBS1 \ Stop Bit Select + $6 constant UCSR1C_UCSZ1 \ Character Size + ca $6 bitmask: UCSR1C.UCSZ1 \ Character Size + $1 constant UCSR1C_UCPOL1 \ Clock Polarity + ca $1 bitmask: UCSR1C.UCPOL1 \ Clock Polarity +$cc constant UBRR1 \ USART1 Baud Rate Register Byt diff --git a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/USART1_SPI.frt b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/USART1_SPI.frt new file mode 100644 index 0000000..fa56346 --- /dev/null +++ b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/USART1_SPI.frt @@ -0,0 +1,29 @@ +\ Generated automatically for atmega256rfr2 +\ #require bitnames.frt + +\ USART1_SPI +$c8 constant UCSR1A \ USART1 MSPIM Control and Statu + $80 constant UCSR1A_RXC1 \ USART Receive Complete + c8 $80 bitmask: UCSR1A.RXC1 \ USART Receive Complete + $40 constant UCSR1A_TXC1 \ USART Transmit Complete + c8 $40 bitmask: UCSR1A.TXC1 \ USART Transmit Complete + $20 constant UCSR1A_UDRE1 \ USART Data Register Empty + c8 $20 bitmask: UCSR1A.UDRE1 \ USART Data Register Empty +$c9 constant UCSR1B \ USART1 MSPIM Control and Statu + $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable + c9 $80 bitmask: UCSR1B.RXCIE1 \ RX Complete Interrupt Enable + $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable + c9 $40 bitmask: UCSR1B.TXCIE1 \ TX Complete Interrupt Enable + $20 constant UCSR1B_UDRIE1 \ USART Data Register Empty Inte + c9 $20 bitmask: UCSR1B.UDRIE1 \ USART Data Register Empty Inte + $10 constant UCSR1B_RXEN1 \ Receiver Enable + c9 $10 bitmask: UCSR1B.RXEN1 \ Receiver Enable + $8 constant UCSR1B_TXEN1 \ Transmitter Enable + c9 $8 bitmask: UCSR1B.TXEN1 \ Transmitter Enable +$ca constant UCSR1C \ USART1 MSPIM Control and Statu + $4 constant UCSR1C_UDORD1 \ Data Order + ca $4 bitmask: UCSR1C.UDORD1 \ Data Order + $2 constant UCSR1C_UCPHA1 \ Clock Phase + ca $2 bitmask: UCSR1C.UCPHA1 \ Clock Phase + $1 constant UCSR1C_UCPOL1 \ Clock Polarity + ca $1 bitmask: UCSR1C.UCPOL1 \ Clock Polarity diff --git a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/WATCHDOG.frt b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/WATCHDOG.frt new file mode 100644 index 0000000..c695cba --- /dev/null +++ b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/WATCHDOG.frt @@ -0,0 +1,15 @@ +\ Generated automatically for atmega256rfr2 +\ #require bitnames.frt + +\ WATCHDOG +$60 constant WDTCSR \ Watchdog Timer Control Registe + $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Fla + 60 $80 bitmask: WDTCSR.WDIF \ Watchdog Timeout Interrupt Fla + $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Ena + 60 $40 bitmask: WDTCSR.WDIE \ Watchdog Timeout Interrupt Ena + $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits + 60 $27 bitmask: WDTCSR.WDP \ Watchdog Timer Prescaler Bits + $10 constant WDTCSR_WDCE \ Watchdog Change Enable + 60 $10 bitmask: WDTCSR.WDCE \ Watchdog Change Enable + $8 constant WDTCSR_WDE \ Watch Dog Enable + 60 $8 bitmask: WDTCSR.WDE \ Watch Dog Enable diff --git a/amforth-6.5/avr8/devices/atmega256rfr2/device.asm b/amforth-6.5/avr8/devices/atmega256rfr2/device.asm new file mode 100644 index 0000000..9b76f0a --- /dev/null +++ b/amforth-6.5/avr8/devices/atmega256rfr2/device.asm @@ -0,0 +1,166 @@ +; Generated Automatically + +.nolist + include "m256RFR2def.inc" +.list +FLASHSTART = 0 +FLASHSIZE = 262144 +RAMEND = 33280 +IRAMSTART = 512 +IRAMSIZE = 32768 +EEPROMSIZE = 8192 +; Interrupt Vectors +.overlap +.org 2 + rcall isr ; External Interrupt Request 0 +.org 4 + rcall isr ; External Interrupt Request 1 +.org 6 + rcall isr ; External Interrupt Request 2 +.org 8 + rcall isr ; External Interrupt Request 3 +.org 10 + rcall isr ; External Interrupt Request 4 +.org 12 + rcall isr ; External Interrupt Request 5 +.org 14 + rcall isr ; External Interrupt Request 6 +.org 16 + rcall isr ; External Interrupt Request 7 +.org 18 + rcall isr ; Pin Change Interrupt Request 0 +.org 20 + rcall isr ; Pin Change Interrupt Request 1 +.org 22 + rcall isr ; Pin Change Interrupt Request 2 +.org 24 + rcall isr ; Watchdog Time-out Interrupt +.org 26 + rcall isr ; Timer/Counter2 Compare Match A +.org 28 + rcall isr ; Timer/Counter2 Compare Match B +.org 30 + rcall isr ; Timer/Counter2 Overflow +.org 32 + rcall isr ; Timer/Counter1 Capture Event +.org 34 + rcall isr ; Timer/Counter1 Compare Match A +.org 36 + rcall isr ; Timer/Counter1 Compare Match B +.org 38 + rcall isr ; Timer/Counter1 Compare Match C +.org 40 + rcall isr ; Timer/Counter1 Overflow +.org 42 + rcall isr ; Timer/Counter0 Compare Match A +.org 44 + rcall isr ; Timer/Counter0 Compare Match B +.org 46 + rcall isr ; Timer/Counter0 Overflow +.org 48 + rcall isr ; SPI Serial Transfer Complete +.org 50 + rcall isr ; USART0, Rx Complete +.org 52 + rcall isr ; USART0 Data register Empty +.org 54 + rcall isr ; USART0, Tx Complete +.org 56 + rcall isr ; Analog Comparator +.org 58 + rcall isr ; ADC Conversion Complete +.org 60 + rcall isr ; EEPROM Ready +.org 62 + rcall isr ; Timer/Counter3 Capture Event +.org 64 + rcall isr ; Timer/Counter3 Compare Match A +.org 66 + rcall isr ; Timer/Counter3 Compare Match B +.org 68 + rcall isr ; Timer/Counter3 Compare Match C +.org 70 + rcall isr ; Timer/Counter3 Overflow +.org 72 + rcall isr ; USART1, Rx Complete +.org 74 + rcall isr ; USART1 Data register Empty +.org 76 + rcall isr ; USART1, Tx Complete +.org 78 + rcall isr ; 2-wire Serial Interface +.org 80 + rcall isr ; Store Program Memory Read +.org 82 + rcall isr ; Timer/Counter4 Capture Event +.org 84 + rcall isr ; Timer/Counter4 Compare Match A +.org 86 + rcall isr ; Timer/Counter4 Compare Match B +.org 88 + rcall isr ; Timer/Counter4 Compare Match C +.org 90 + rcall isr ; Timer/Counter4 Overflow +.org 92 + rcall isr ; Timer/Counter5 Capture Event +.org 94 + rcall isr ; Timer/Counter5 Compare Match A +.org 96 + rcall isr ; Timer/Counter5 Compare Match B +.org 98 + rcall isr ; Timer/Counter5 Compare Match C +.org 100 + rcall isr ; Timer/Counter5 Overflow +.org 102 + rcall isr ; USART2, Rx Complete +.org 104 + rcall isr ; USART2 Data register Empty +.org 106 + rcall isr ; USART2, Tx Complete +.org 108 + rcall isr ; USART3, Rx Complete +.org 110 + rcall isr ; USART3 Data register Empty +.org 112 + rcall isr ; USART3, Tx Complete +.org 114 + rcall isr ; TRX24 - PLL lock interrupt +.org 116 + rcall isr ; TRX24 - PLL unlock interrupt +.org 118 + rcall isr ; TRX24 - Receive start interrupt +.org 120 + rcall isr ; TRX24 - RX_END interrupt +.org 122 + rcall isr ; TRX24 - CCA/ED done interrupt +.org 124 + rcall isr ; TRX24 - XAH - AMI +.org 126 + rcall isr ; TRX24 - TX_END interrupt +.org 128 + rcall isr ; TRX24 AWAKE - tranceiver is reaching state TRX_OFF +.org 130 + rcall isr ; Symbol counter - compare match 1 interrupt +.org 132 + rcall isr ; Symbol counter - compare match 2 interrupt +.org 134 + rcall isr ; Symbol counter - compare match 3 interrupt +.org 136 + rcall isr ; Symbol counter - overflow interrupt +.org 138 + rcall isr ; Symbol counter - backoff interrupt +.org 140 + rcall isr ; AES engine ready interrupt +.org 142 + rcall isr ; Battery monitor indicates supply voltage below threshold +.org 144 + rcall isr ; TRX24 TX start interrupt +.org 146 + rcall isr ; Address match interrupt of address filter 0 +.org 148 + rcall isr ; Address match interrupt of address filter 1 +.org 150 + rcall isr ; Address match interrupt of address filter 2 +.org 152 + rcall isr ; Address match interrupt of address filter 3 +.nooverlap diff --git a/amforth-6.5/avr8/devices/atmega256rfr2/device.frt b/amforth-6.5/avr8/devices/atmega256rfr2/device.frt new file mode 100644 index 0000000..4ff689f --- /dev/null +++ b/amforth-6.5/avr8/devices/atmega256rfr2/device.frt @@ -0,0 +1,1753 @@ +\ Generated Automatically + +\ Interrupt Vectors +#2 constant INT0Addr \ External Interrupt Request 0 +#4 constant INT1Addr \ External Interrupt Request 1 +#6 constant INT2Addr \ External Interrupt Request 2 +#8 constant INT3Addr \ External Interrupt Request 3 +#10 constant INT4Addr \ External Interrupt Request 4 +#12 constant INT5Addr \ External Interrupt Request 5 +#14 constant INT6Addr \ External Interrupt Request 6 +#16 constant INT7Addr \ External Interrupt Request 7 +#18 constant PCINT0Addr \ Pin Change Interrupt Request 0 +#20 constant PCINT1Addr \ Pin Change Interrupt Request 1 +#22 constant PCINT2Addr \ Pin Change Interrupt Request 2 +#24 constant WDTAddr \ Watchdog Time-out Interrupt +#26 constant TIMER2_COMPAAddr \ Timer/Counter2 Compare Match A +#28 constant TIMER2_COMPBAddr \ Timer/Counter2 Compare Match B +#30 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow +#32 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event +#34 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A +#36 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B +#38 constant TIMER1_COMPCAddr \ Timer/Counter1 Compare Match C +#40 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow +#42 constant TIMER0_COMPAAddr \ Timer/Counter0 Compare Match A +#44 constant TIMER0_COMPBAddr \ Timer/Counter0 Compare Match B +#46 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow +#48 constant SPI_STCAddr \ SPI Serial Transfer Complete +#50 constant USART0_RXAddr \ USART0, Rx Complete +#52 constant USART0_UDREAddr \ USART0 Data register Empty +#54 constant USART0_TXAddr \ USART0, Tx Complete +#56 constant ANALOG_COMPAddr \ Analog Comparator +#58 constant ADCAddr \ ADC Conversion Complete +#60 constant EE_READYAddr \ EEPROM Ready +#62 constant TIMER3_CAPTAddr \ Timer/Counter3 Capture Event +#64 constant TIMER3_COMPAAddr \ Timer/Counter3 Compare Match A +#66 constant TIMER3_COMPBAddr \ Timer/Counter3 Compare Match B +#68 constant TIMER3_COMPCAddr \ Timer/Counter3 Compare Match C +#70 constant TIMER3_OVFAddr \ Timer/Counter3 Overflow +#72 constant USART1_RXAddr \ USART1, Rx Complete +#74 constant USART1_UDREAddr \ USART1 Data register Empty +#76 constant USART1_TXAddr \ USART1, Tx Complete +#78 constant TWIAddr \ 2-wire Serial Interface +#80 constant SPM_READYAddr \ Store Program Memory Read +#82 constant TIMER4_CAPTAddr \ Timer/Counter4 Capture Event +#84 constant TIMER4_COMPAAddr \ Timer/Counter4 Compare Match A +#86 constant TIMER4_COMPBAddr \ Timer/Counter4 Compare Match B +#88 constant TIMER4_COMPCAddr \ Timer/Counter4 Compare Match C +#90 constant TIMER4_OVFAddr \ Timer/Counter4 Overflow +#92 constant TIMER5_CAPTAddr \ Timer/Counter5 Capture Event +#94 constant TIMER5_COMPAAddr \ Timer/Counter5 Compare Match A +#96 constant TIMER5_COMPBAddr \ Timer/Counter5 Compare Match B +#98 constant TIMER5_COMPCAddr \ Timer/Counter5 Compare Match C +#100 constant TIMER5_OVFAddr \ Timer/Counter5 Overflow +#102 constant USART2_RXAddr \ USART2, Rx Complete +#104 constant USART2_UDREAddr \ USART2 Data register Empty +#106 constant USART2_TXAddr \ USART2, Tx Complete +#108 constant USART3_RXAddr \ USART3, Rx Complete +#110 constant USART3_UDREAddr \ USART3 Data register Empty +#112 constant USART3_TXAddr \ USART3, Tx Complete +#114 constant TRX24_PLL_LOCKAddr \ TRX24 - PLL lock interrupt +#116 constant TRX24_PLL_UNLOCKAddr \ TRX24 - PLL unlock interrupt +#118 constant TRX24_RX_STARTAddr \ TRX24 - Receive start interrupt +#120 constant TRX24_RX_ENDAddr \ TRX24 - RX_END interrupt +#122 constant TRX24_CCA_ED_DONEAddr \ TRX24 - CCA/ED done interrupt +#124 constant TRX24_XAH_AMIAddr \ TRX24 - XAH - AMI +#126 constant TRX24_TX_ENDAddr \ TRX24 - TX_END interrupt +#128 constant TRX24_AWAKEAddr \ TRX24 AWAKE - tranceiver is reaching state TRX_OFF +#130 constant SCNT_CMP1Addr \ Symbol counter - compare match 1 interrupt +#132 constant SCNT_CMP2Addr \ Symbol counter - compare match 2 interrupt +#134 constant SCNT_CMP3Addr \ Symbol counter - compare match 3 interrupt +#136 constant SCNT_OVFLAddr \ Symbol counter - overflow interrupt +#138 constant SCNT_BACKOFFAddr \ Symbol counter - backoff interrupt +#140 constant AES_READYAddr \ AES engine ready interrupt +#142 constant BAT_LOWAddr \ Battery monitor indicates supply voltage below threshold +#144 constant TRX24_TX_STARTAddr \ TRX24 TX start interrupt +#146 constant TRX24_AMI0Addr \ Address match interrupt of address filter 0 +#148 constant TRX24_AMI1Addr \ Address match interrupt of address filter 1 +#150 constant TRX24_AMI2Addr \ Address match interrupt of address filter 2 +#152 constant TRX24_AMI3Addr \ Address match interrupt of address filter 3 +\ ANALOG_COMPARATOR +$7b constant ADCSRB \ ADC Control and Status Registe + $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer + 7b $40 bitmask: ADCSRB.ACME \ Analog Comparator Multiplexer +$50 constant ACSR \ Analog Comparator Control And + $80 constant ACSR_ACD \ Analog Comparator Disable + 50 $80 bitmask: ACSR.ACD \ Analog Comparator Disable + $40 constant ACSR_ACBG \ Analog Comparator Bandgap Sele + 50 $40 bitmask: ACSR.ACBG \ Analog Comparator Bandgap Sele + $20 constant ACSR_ACO \ Analog Compare Output + 50 $20 bitmask: ACSR.ACO \ Analog Compare Output + $10 constant ACSR_ACI \ Analog Comparator Interrupt Fl + 50 $10 bitmask: ACSR.ACI \ Analog Comparator Interrupt Fl + $8 constant ACSR_ACIE \ Analog Comparator Interrupt En + 50 $8 bitmask: ACSR.ACIE \ Analog Comparator Interrupt En + $4 constant ACSR_ACIC \ Analog Comparator Input Captur + 50 $4 bitmask: ACSR.ACIC \ Analog Comparator Input Captur + $3 constant ACSR_ACIS \ Analog Comparator Interrupt Mo + 50 $3 bitmask: ACSR.ACIS \ Analog Comparator Interrupt Mo +$7f constant DIDR1 \ Digital Input Disable Register + $2 constant DIDR1_AIN1D \ AIN1 Digital Input Disable + 7f $2 bitmask: DIDR1.AIN1D \ AIN1 Digital Input Disable + $1 constant DIDR1_AIN0D \ AIN0 Digital Input Disable + 7f $1 bitmask: DIDR1.AIN0D \ AIN0 Digital Input Disable +\ USART0 +$c6 constant UDR0 \ USART0 I/O Data Register +$c0 constant UCSR0A \ USART0 Control and Status Regi + $80 constant UCSR0A_RXC0 \ USART Receive Complete + c0 $80 bitmask: UCSR0A.RXC0 \ USART Receive Complete + $40 constant UCSR0A_TXC0 \ USART Transmit Complete + c0 $40 bitmask: UCSR0A.TXC0 \ USART Transmit Complete + $20 constant UCSR0A_UDRE0 \ USART Data Register Empty + c0 $20 bitmask: UCSR0A.UDRE0 \ USART Data Register Empty + $10 constant UCSR0A_FE0 \ Frame Error + c0 $10 bitmask: UCSR0A.FE0 \ Frame Error + $8 constant UCSR0A_DOR0 \ Data OverRun + c0 $8 bitmask: UCSR0A.DOR0 \ Data OverRun + $4 constant UCSR0A_UPE0 \ USART Parity Error + c0 $4 bitmask: UCSR0A.UPE0 \ USART Parity Error + $2 constant UCSR0A_U2X0 \ Double the USART Transmission + c0 $2 bitmask: UCSR0A.U2X0 \ Double the USART Transmission + $1 constant UCSR0A_MPCM0 \ Multi-processor Communication + c0 $1 bitmask: UCSR0A.MPCM0 \ Multi-processor Communication +$c1 constant UCSR0B \ USART0 Control and Status Regi + $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable + c1 $80 bitmask: UCSR0B.RXCIE0 \ RX Complete Interrupt Enable + $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable + c1 $40 bitmask: UCSR0B.TXCIE0 \ TX Complete Interrupt Enable + $20 constant UCSR0B_UDRIE0 \ USART Data Register Empty Inte + c1 $20 bitmask: UCSR0B.UDRIE0 \ USART Data Register Empty Inte + $10 constant UCSR0B_RXEN0 \ Receiver Enable + c1 $10 bitmask: UCSR0B.RXEN0 \ Receiver Enable + $8 constant UCSR0B_TXEN0 \ Transmitter Enable + c1 $8 bitmask: UCSR0B.TXEN0 \ Transmitter Enable + $4 constant UCSR0B_UCSZ02 \ Character Size + c1 $4 bitmask: UCSR0B.UCSZ02 \ Character Size + $2 constant UCSR0B_RXB80 \ Receive Data Bit 8 + c1 $2 bitmask: UCSR0B.RXB80 \ Receive Data Bit 8 + $1 constant UCSR0B_TXB80 \ Transmit Data Bit 8 + c1 $1 bitmask: UCSR0B.TXB80 \ Transmit Data Bit 8 +$c2 constant UCSR0C \ USART0 Control and Status Regi + $c0 constant UCSR0C_UMSEL0 \ USART Mode Select + c2 $c0 bitmask: UCSR0C.UMSEL0 \ USART Mode Select + $30 constant UCSR0C_UPM0 \ Parity Mode + c2 $30 bitmask: UCSR0C.UPM0 \ Parity Mode + $8 constant UCSR0C_USBS0 \ Stop Bit Select + c2 $8 bitmask: UCSR0C.USBS0 \ Stop Bit Select + $6 constant UCSR0C_UCSZ0 \ Character Size + c2 $6 bitmask: UCSR0C.UCSZ0 \ Character Size + $1 constant UCSR0C_UCPOL0 \ Clock Polarity + c2 $1 bitmask: UCSR0C.UCPOL0 \ Clock Polarity +$c4 constant UBRR0 \ USART0 Baud Rate Register Byt +\ USART1 +$ce constant UDR1 \ USART1 I/O Data Register +$c8 constant UCSR1A \ USART1 Control and Status Regi + $80 constant UCSR1A_RXC1 \ USART Receive Complete + c8 $80 bitmask: UCSR1A.RXC1 \ USART Receive Complete + $40 constant UCSR1A_TXC1 \ USART Transmit Complete + c8 $40 bitmask: UCSR1A.TXC1 \ USART Transmit Complete + $20 constant UCSR1A_UDRE1 \ USART Data Register Empty + c8 $20 bitmask: UCSR1A.UDRE1 \ USART Data Register Empty + $10 constant UCSR1A_FE1 \ Frame Error + c8 $10 bitmask: UCSR1A.FE1 \ Frame Error + $8 constant UCSR1A_DOR1 \ Data OverRun + c8 $8 bitmask: UCSR1A.DOR1 \ Data OverRun + $4 constant UCSR1A_UPE1 \ USART Parity Error + c8 $4 bitmask: UCSR1A.UPE1 \ USART Parity Error + $2 constant UCSR1A_U2X1 \ Double the USART Transmission + c8 $2 bitmask: UCSR1A.U2X1 \ Double the USART Transmission + $1 constant UCSR1A_MPCM1 \ Multi-processor Communication + c8 $1 bitmask: UCSR1A.MPCM1 \ Multi-processor Communication +$c9 constant UCSR1B \ USART1 Control and Status Regi + $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable + c9 $80 bitmask: UCSR1B.RXCIE1 \ RX Complete Interrupt Enable + $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable + c9 $40 bitmask: UCSR1B.TXCIE1 \ TX Complete Interrupt Enable + $20 constant UCSR1B_UDRIE1 \ USART Data Register Empty Inte + c9 $20 bitmask: UCSR1B.UDRIE1 \ USART Data Register Empty Inte + $10 constant UCSR1B_RXEN1 \ Receiver Enable + c9 $10 bitmask: UCSR1B.RXEN1 \ Receiver Enable + $8 constant UCSR1B_TXEN1 \ Transmitter Enable + c9 $8 bitmask: UCSR1B.TXEN1 \ Transmitter Enable + $4 constant UCSR1B_UCSZ12 \ Character Size + c9 $4 bitmask: UCSR1B.UCSZ12 \ Character Size + $2 constant UCSR1B_RXB81 \ Receive Data Bit 8 + c9 $2 bitmask: UCSR1B.RXB81 \ Receive Data Bit 8 + $1 constant UCSR1B_TXB81 \ Transmit Data Bit 8 + c9 $1 bitmask: UCSR1B.TXB81 \ Transmit Data Bit 8 +$ca constant UCSR1C \ USART1 Control and Status Regi + $c0 constant UCSR1C_UMSEL1 \ USART Mode Select + ca $c0 bitmask: UCSR1C.UMSEL1 \ USART Mode Select + $30 constant UCSR1C_UPM1 \ Parity Mode + ca $30 bitmask: UCSR1C.UPM1 \ Parity Mode + $8 constant UCSR1C_USBS1 \ Stop Bit Select + ca $8 bitmask: UCSR1C.USBS1 \ Stop Bit Select + $6 constant UCSR1C_UCSZ1 \ Character Size + ca $6 bitmask: UCSR1C.UCSZ1 \ Character Size + $1 constant UCSR1C_UCPOL1 \ Clock Polarity + ca $1 bitmask: UCSR1C.UCPOL1 \ Clock Polarity +$cc constant UBRR1 \ USART1 Baud Rate Register Byt +\ TWI +$bd constant TWAMR \ TWI (Slave) Address Mask Regis + $fe constant TWAMR_TWAM \ TWI Address Mask + bd $fe bitmask: TWAMR.TWAM \ TWI Address Mask + $1 constant TWAMR_Res \ Reserved Bit + bd $1 bitmask: TWAMR.Res \ Reserved Bit +$b8 constant TWBR \ TWI Bit Rate Register +$bc constant TWCR \ TWI Control Register + $80 constant TWCR_TWINT \ TWI Interrupt Flag + bc $80 bitmask: TWCR.TWINT \ TWI Interrupt Flag + $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit + bc $40 bitmask: TWCR.TWEA \ TWI Enable Acknowledge Bit + $20 constant TWCR_TWSTA \ TWI START Condition Bit + bc $20 bitmask: TWCR.TWSTA \ TWI START Condition Bit + $10 constant TWCR_TWSTO \ TWI STOP Condition Bit + bc $10 bitmask: TWCR.TWSTO \ TWI STOP Condition Bit + $8 constant TWCR_TWWC \ TWI Write Collision Flag + bc $8 bitmask: TWCR.TWWC \ TWI Write Collision Flag + $4 constant TWCR_TWEN \ TWI Enable Bit + bc $4 bitmask: TWCR.TWEN \ TWI Enable Bit + $2 constant TWCR_Res \ Reserved Bit + bc $2 bitmask: TWCR.Res \ Reserved Bit + $1 constant TWCR_TWIE \ TWI Interrupt Enable + bc $1 bitmask: TWCR.TWIE \ TWI Interrupt Enable +$b9 constant TWSR \ TWI Status Register + $f8 constant TWSR_TWS \ TWI Status + b9 $f8 bitmask: TWSR.TWS \ TWI Status + $4 constant TWSR_Res \ Reserved Bit + b9 $4 bitmask: TWSR.Res \ Reserved Bit + $3 constant TWSR_TWPS \ TWI Prescaler Bits + b9 $3 bitmask: TWSR.TWPS \ TWI Prescaler Bits +$bb constant TWDR \ TWI Data Register +$ba constant TWAR \ TWI (Slave) Address Register + $fe constant TWAR_TWA \ TWI (Slave) Address + ba $fe bitmask: TWAR.TWA \ TWI (Slave) Address + $1 constant TWAR_TWGCE \ TWI General Call Recognition E + ba $1 bitmask: TWAR.TWGCE \ TWI General Call Recognition E +\ SPI +$4c constant SPCR \ SPI Control Register + $80 constant SPCR_SPIE \ SPI Interrupt Enable + 4c $80 bitmask: SPCR.SPIE \ SPI Interrupt Enable + $40 constant SPCR_SPE \ SPI Enable + 4c $40 bitmask: SPCR.SPE \ SPI Enable + $20 constant SPCR_DORD \ Data Order + 4c $20 bitmask: SPCR.DORD \ Data Order + $10 constant SPCR_MSTR \ Master/Slave Select + 4c $10 bitmask: SPCR.MSTR \ Master/Slave Select + $8 constant SPCR_CPOL \ Clock polarity + 4c $8 bitmask: SPCR.CPOL \ Clock polarity + $4 constant SPCR_CPHA \ Clock Phase + 4c $4 bitmask: SPCR.CPHA \ Clock Phase + $3 constant SPCR_SPR \ SPI Clock Rate Select 1 and 0 + 4c $3 bitmask: SPCR.SPR \ SPI Clock Rate Select 1 and 0 +$4d constant SPSR \ SPI Status Register + $80 constant SPSR_SPIF \ SPI Interrupt Flag + 4d $80 bitmask: SPSR.SPIF \ SPI Interrupt Flag + $40 constant SPSR_WCOL \ Write Collision Flag + 4d $40 bitmask: SPSR.WCOL \ Write Collision Flag + $3e constant SPSR_Res \ Reserved + 4d $3e bitmask: SPSR.Res \ Reserved + $1 constant SPSR_SPI2X \ Double SPI Speed Bit + 4d $1 bitmask: SPSR.SPI2X \ Double SPI Speed Bit +$4e constant SPDR \ SPI Data Register +\ PORTA +$22 constant PORTA \ Port A Data Register +$21 constant DDRA \ Port A Data Direction Register +$20 constant PINA \ Port A Input Pins Address +\ PORTB +$25 constant PORTB \ Port B Data Register +$24 constant DDRB \ Port B Data Direction Register +$23 constant PINB \ Port B Input Pins Address +\ PORTC +$28 constant PORTC \ Port C Data Register +$27 constant DDRC \ Port C Data Direction Register +$26 constant PINC \ Port C Input Pins Address +\ PORTD +$2b constant PORTD \ Port D Data Register +$2a constant DDRD \ Port D Data Direction Register +$29 constant PIND \ Port D Input Pins Address +\ PORTE +$2e constant PORTE \ Port E Data Register +$2d constant DDRE \ Port E Data Direction Register +$2c constant PINE \ Port E Input Pins Address +\ PORTF +$31 constant PORTF \ Port F Data Register +$30 constant DDRF \ Port F Data Direction Register +$2f constant PINF \ Port F Input Pins Address +\ PORTG +$34 constant PORTG \ Port G Data Register +$33 constant DDRG \ Port G Data Direction Register +$32 constant PING \ Port G Input Pins Address +\ TIMER_COUNTER_0 +$48 constant OCR0B \ Timer/Counter0 Output Compare +$47 constant OCR0A \ Timer/Counter0 Output Compare +$46 constant TCNT0 \ Timer/Counter0 Register +$45 constant TCCR0B \ Timer/Counter0 Control Registe + $80 constant TCCR0B_FOC0A \ Force Output Compare A + 45 $80 bitmask: TCCR0B.FOC0A \ Force Output Compare A + $40 constant TCCR0B_FOC0B \ Force Output Compare B + 45 $40 bitmask: TCCR0B.FOC0B \ Force Output Compare B + $30 constant TCCR0B_Res \ Reserved Bit + 45 $30 bitmask: TCCR0B.Res \ Reserved Bit + $8 constant TCCR0B_WGM02 \ + 45 $8 bitmask: TCCR0B.WGM02 \ + $7 constant TCCR0B_CS0 \ Clock Select + 45 $7 bitmask: TCCR0B.CS0 \ Clock Select +$44 constant TCCR0A \ Timer/Counter0 Control Registe + $c0 constant TCCR0A_COM0A \ Compare Match Output A Mode + 44 $c0 bitmask: TCCR0A.COM0A \ Compare Match Output A Mode + $30 constant TCCR0A_COM0B \ Compare Match Output B Mode + 44 $30 bitmask: TCCR0A.COM0B \ Compare Match Output B Mode + $c constant TCCR0A_Res \ Reserved Bit + 44 $c bitmask: TCCR0A.Res \ Reserved Bit + $3 constant TCCR0A_WGM0 \ Waveform Generation Mode + 44 $3 bitmask: TCCR0A.WGM0 \ Waveform Generation Mode +$6e constant TIMSK0 \ Timer/Counter0 Interrupt Mask + $f8 constant TIMSK0_Res \ Reserved + 6e $f8 bitmask: TIMSK0.Res \ Reserved + $4 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare + 6e $4 bitmask: TIMSK0.OCIE0B \ Timer/Counter0 Output Compare + $2 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare + 6e $2 bitmask: TIMSK0.OCIE0A \ Timer/Counter0 Output Compare + $1 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interr + 6e $1 bitmask: TIMSK0.TOIE0 \ Timer/Counter0 Overflow Interr +$35 constant TIFR0 \ Timer/Counter0 Interrupt Flag + $f8 constant TIFR0_Res \ Reserved + 35 $f8 bitmask: TIFR0.Res \ Reserved + $4 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare + 35 $4 bitmask: TIFR0.OCF0B \ Timer/Counter0 Output Compare + $2 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare + 35 $2 bitmask: TIFR0.OCF0A \ Timer/Counter0 Output Compare + $1 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag + 35 $1 bitmask: TIFR0.TOV0 \ Timer/Counter0 Overflow Flag +$43 constant GTCCR \ General Timer/Counter Control + $80 constant GTCCR_TSM \ Timer/Counter Synchronization + 43 $80 bitmask: GTCCR.TSM \ Timer/Counter Synchronization + $7c constant GTCCR_Res \ Reserved + 43 $7c bitmask: GTCCR.Res \ Reserved + $2 constant GTCCR_PSRASY \ Prescaler Reset Timer/Counter2 + 43 $2 bitmask: GTCCR.PSRASY \ Prescaler Reset Timer/Counter2 + $1 constant GTCCR_PSRSYNC \ Prescaler Reset for Synchronou + 43 $1 bitmask: GTCCR.PSRSYNC \ Prescaler Reset for Synchronou +\ TIMER_COUNTER_2 +$70 constant TIMSK2 \ Timer/Counter Interrupt Mask r + $f8 constant TIMSK2_Res \ Reserved Bit + 70 $f8 bitmask: TIMSK2.Res \ Reserved Bit + $4 constant TIMSK2_OCIE2B \ Timer/Counter2 Output Compare + 70 $4 bitmask: TIMSK2.OCIE2B \ Timer/Counter2 Output Compare + $2 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare + 70 $2 bitmask: TIMSK2.OCIE2A \ Timer/Counter2 Output Compare + $1 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interr + 70 $1 bitmask: TIMSK2.TOIE2 \ Timer/Counter2 Overflow Interr +$37 constant TIFR2 \ Timer/Counter Interrupt Flag R + $f8 constant TIFR2_Res \ Reserved Bit + 37 $f8 bitmask: TIFR2.Res \ Reserved Bit + $4 constant TIFR2_OCF2B \ Output Compare Flag 2 B + 37 $4 bitmask: TIFR2.OCF2B \ Output Compare Flag 2 B + $2 constant TIFR2_OCF2A \ Output Compare Flag 2 A + 37 $2 bitmask: TIFR2.OCF2A \ Output Compare Flag 2 A + $1 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag + 37 $1 bitmask: TIFR2.TOV2 \ Timer/Counter2 Overflow Flag +$b0 constant TCCR2A \ Timer/Counter2 Control Registe + $c0 constant TCCR2A_COM2A \ Compare Match Output A Mode + b0 $c0 bitmask: TCCR2A.COM2A \ Compare Match Output A Mode + $30 constant TCCR2A_COM2B \ Compare Match Output B Mode + b0 $30 bitmask: TCCR2A.COM2B \ Compare Match Output B Mode + $c constant TCCR2A_Res \ Reserved + b0 $c bitmask: TCCR2A.Res \ Reserved + $3 constant TCCR2A_WGM2 \ Waveform Generation Mode + b0 $3 bitmask: TCCR2A.WGM2 \ Waveform Generation Mode +$b1 constant TCCR2B \ Timer/Counter2 Control Registe + $80 constant TCCR2B_FOC2A \ Force Output Compare A + b1 $80 bitmask: TCCR2B.FOC2A \ Force Output Compare A + $40 constant TCCR2B_FOC2B \ Force Output Compare B + b1 $40 bitmask: TCCR2B.FOC2B \ Force Output Compare B + $30 constant TCCR2B_Res \ Reserved + b1 $30 bitmask: TCCR2B.Res \ Reserved + $8 constant TCCR2B_WGM22 \ Waveform Generation Mode + b1 $8 bitmask: TCCR2B.WGM22 \ Waveform Generation Mode + $7 constant TCCR2B_CS2 \ Clock Select + b1 $7 bitmask: TCCR2B.CS2 \ Clock Select +$b2 constant TCNT2 \ Timer/Counter2 +$b4 constant OCR2B \ Timer/Counter2 Output Compare +$b3 constant OCR2A \ Timer/Counter2 Output Compare +$b6 constant ASSR \ Asynchronous Status Register + $80 constant ASSR_EXCLKAMR \ Enable External Clock Input fo + b6 $80 bitmask: ASSR.EXCLKAMR \ Enable External Clock Input fo + $40 constant ASSR_EXCLK \ Enable External Clock Input + b6 $40 bitmask: ASSR.EXCLK \ Enable External Clock Input + $20 constant ASSR_AS2 \ Timer/Counter2 Asynchronous Mo + b6 $20 bitmask: ASSR.AS2 \ Timer/Counter2 Asynchronous Mo + $10 constant ASSR_TCN2UB \ Timer/Counter2 Update Busy + b6 $10 bitmask: ASSR.TCN2UB \ Timer/Counter2 Update Busy + $8 constant ASSR_OCR2AUB \ Timer/Counter2 Output Compare + b6 $8 bitmask: ASSR.OCR2AUB \ Timer/Counter2 Output Compare + $4 constant ASSR_OCR2BUB \ Timer/Counter2 Output Compare + b6 $4 bitmask: ASSR.OCR2BUB \ Timer/Counter2 Output Compare + $2 constant ASSR_TCR2AUB \ Timer/Counter2 Control Registe + b6 $2 bitmask: ASSR.TCR2AUB \ Timer/Counter2 Control Registe + $1 constant ASSR_TCR2BUB \ Timer/Counter2 Control Registe + b6 $1 bitmask: ASSR.TCR2BUB \ Timer/Counter2 Control Registe +$43 constant GTCCR \ General Timer Counter Control + $80 constant GTCCR_TSM \ Timer/Counter Synchronization + 43 $80 bitmask: GTCCR.TSM \ Timer/Counter Synchronization + $2 constant GTCCR_PSRASY \ Prescaler Reset Timer/Counter2 + 43 $2 bitmask: GTCCR.PSRASY \ Prescaler Reset Timer/Counter2 +\ WATCHDOG +$60 constant WDTCSR \ Watchdog Timer Control Registe + $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Fla + 60 $80 bitmask: WDTCSR.WDIF \ Watchdog Timeout Interrupt Fla + $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Ena + 60 $40 bitmask: WDTCSR.WDIE \ Watchdog Timeout Interrupt Ena + $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits + 60 $27 bitmask: WDTCSR.WDP \ Watchdog Timer Prescaler Bits + $10 constant WDTCSR_WDCE \ Watchdog Change Enable + 60 $10 bitmask: WDTCSR.WDCE \ Watchdog Change Enable + $8 constant WDTCSR_WDE \ Watch Dog Enable + 60 $8 bitmask: WDTCSR.WDE \ Watch Dog Enable +\ TIMER_COUNTER_5 +$120 constant TCCR5A \ Timer/Counter5 Control Registe + $c0 constant TCCR5A_COM5A \ Compare Output Mode for Channe + 120 $c0 bitmask: TCCR5A.COM5A \ Compare Output Mode for Channe + $30 constant TCCR5A_COM5B \ Compare Output Mode for Channe + 120 $30 bitmask: TCCR5A.COM5B \ Compare Output Mode for Channe + $c constant TCCR5A_COM5C \ Compare Output Mode for Channe + 120 $c bitmask: TCCR5A.COM5C \ Compare Output Mode for Channe + $3 constant TCCR5A_WGM5 \ Waveform Generation Mode + 120 $3 bitmask: TCCR5A.WGM5 \ Waveform Generation Mode +$121 constant TCCR5B \ Timer/Counter5 Control Registe + $80 constant TCCR5B_ICNC5 \ Input Capture 5 Noise Cancelle + 121 $80 bitmask: TCCR5B.ICNC5 \ Input Capture 5 Noise Cancelle + $40 constant TCCR5B_ICES5 \ Input Capture 5 Edge Select + 121 $40 bitmask: TCCR5B.ICES5 \ Input Capture 5 Edge Select + $20 constant TCCR5B_Res \ Reserved Bit + 121 $20 bitmask: TCCR5B.Res \ Reserved Bit + $18 constant TCCR5B_WGM5 \ Waveform Generation Mode + 121 $18 bitmask: TCCR5B.WGM5 \ Waveform Generation Mode + $7 constant TCCR5B_CS5 \ Clock Select + 121 $7 bitmask: TCCR5B.CS5 \ Clock Select +$122 constant TCCR5C \ Timer/Counter5 Control Registe + $80 constant TCCR5C_FOC5A \ Force Output Compare for Chann + 122 $80 bitmask: TCCR5C.FOC5A \ Force Output Compare for Chann + $40 constant TCCR5C_FOC5B \ Force Output Compare for Chann + 122 $40 bitmask: TCCR5C.FOC5B \ Force Output Compare for Chann + $20 constant TCCR5C_FOC5C \ Force Output Compare for Chann + 122 $20 bitmask: TCCR5C.FOC5C \ Force Output Compare for Chann + $1f constant TCCR5C_Res \ Reserved + 122 $1f bitmask: TCCR5C.Res \ Reserved +$124 constant TCNT5 \ Timer/Counter5 Bytes +$128 constant OCR5A \ Timer/Counter5 Output Compare +$12a constant OCR5B \ Timer/Counter5 Output Compare +$12c constant OCR5C \ Timer/Counter5 Output Compare +$126 constant ICR5 \ Timer/Counter5 Input Capture R +$73 constant TIMSK5 \ Timer/Counter5 Interrupt Mask + $c0 constant TIMSK5_Res \ Reserved Bit + 73 $c0 bitmask: TIMSK5.Res \ Reserved Bit + $20 constant TIMSK5_ICIE5 \ Timer/Counter5 Input Capture I + 73 $20 bitmask: TIMSK5.ICIE5 \ Timer/Counter5 Input Capture I + $10 constant TIMSK5_Res \ Reserved Bit + 73 $10 bitmask: TIMSK5.Res \ Reserved Bit + $8 constant TIMSK5_OCIE5C \ Timer/Counter5 Output Compare + 73 $8 bitmask: TIMSK5.OCIE5C \ Timer/Counter5 Output Compare + $4 constant TIMSK5_OCIE5B \ Timer/Counter5 Output Compare + 73 $4 bitmask: TIMSK5.OCIE5B \ Timer/Counter5 Output Compare + $2 constant TIMSK5_OCIE5A \ Timer/Counter5 Output Compare + 73 $2 bitmask: TIMSK5.OCIE5A \ Timer/Counter5 Output Compare + $1 constant TIMSK5_TOIE5 \ Timer/Counter5 Overflow Interr + 73 $1 bitmask: TIMSK5.TOIE5 \ Timer/Counter5 Overflow Interr +$3a constant TIFR5 \ Timer/Counter5 Interrupt Flag + $c0 constant TIFR5_Res \ Reserved Bit + 3a $c0 bitmask: TIFR5.Res \ Reserved Bit + $20 constant TIFR5_ICF5 \ Timer/Counter5 Input Capture F + 3a $20 bitmask: TIFR5.ICF5 \ Timer/Counter5 Input Capture F + $10 constant TIFR5_Res \ Reserved Bit + 3a $10 bitmask: TIFR5.Res \ Reserved Bit + $8 constant TIFR5_OCF5C \ Timer/Counter5 Output Compare + 3a $8 bitmask: TIFR5.OCF5C \ Timer/Counter5 Output Compare + $4 constant TIFR5_OCF5B \ Timer/Counter5 Output Compare + 3a $4 bitmask: TIFR5.OCF5B \ Timer/Counter5 Output Compare + $2 constant TIFR5_OCF5A \ Timer/Counter5 Output Compare + 3a $2 bitmask: TIFR5.OCF5A \ Timer/Counter5 Output Compare + $1 constant TIFR5_TOV5 \ Timer/Counter5 Overflow Flag + 3a $1 bitmask: TIFR5.TOV5 \ Timer/Counter5 Overflow Flag +\ TIMER_COUNTER_4 +$a0 constant TCCR4A \ Timer/Counter4 Control Registe + $c0 constant TCCR4A_COM4A \ Compare Output Mode for Channe + a0 $c0 bitmask: TCCR4A.COM4A \ Compare Output Mode for Channe + $30 constant TCCR4A_COM4B \ Compare Output Mode for Channe + a0 $30 bitmask: TCCR4A.COM4B \ Compare Output Mode for Channe + $c constant TCCR4A_COM4C \ Compare Output Mode for Channe + a0 $c bitmask: TCCR4A.COM4C \ Compare Output Mode for Channe + $3 constant TCCR4A_WGM4 \ Waveform Generation Mode + a0 $3 bitmask: TCCR4A.WGM4 \ Waveform Generation Mode +$a1 constant TCCR4B \ Timer/Counter4 Control Registe + $80 constant TCCR4B_ICNC4 \ Input Capture 4 Noise Cancelle + a1 $80 bitmask: TCCR4B.ICNC4 \ Input Capture 4 Noise Cancelle + $40 constant TCCR4B_ICES4 \ Input Capture 4 Edge Select + a1 $40 bitmask: TCCR4B.ICES4 \ Input Capture 4 Edge Select + $20 constant TCCR4B_Res \ Reserved Bit + a1 $20 bitmask: TCCR4B.Res \ Reserved Bit + $18 constant TCCR4B_WGM4 \ Waveform Generation Mode + a1 $18 bitmask: TCCR4B.WGM4 \ Waveform Generation Mode + $7 constant TCCR4B_CS4 \ Clock Select + a1 $7 bitmask: TCCR4B.CS4 \ Clock Select +$a2 constant TCCR4C \ Timer/Counter4 Control Registe + $80 constant TCCR4C_FOC4A \ Force Output Compare for Chann + a2 $80 bitmask: TCCR4C.FOC4A \ Force Output Compare for Chann + $40 constant TCCR4C_FOC4B \ Force Output Compare for Chann + a2 $40 bitmask: TCCR4C.FOC4B \ Force Output Compare for Chann + $20 constant TCCR4C_FOC4C \ Force Output Compare for Chann + a2 $20 bitmask: TCCR4C.FOC4C \ Force Output Compare for Chann + $1f constant TCCR4C_Res \ Reserved + a2 $1f bitmask: TCCR4C.Res \ Reserved +$a4 constant TCNT4 \ Timer/Counter4 Bytes +$a8 constant OCR4A \ Timer/Counter4 Output Compare +$aa constant OCR4B \ Timer/Counter4 Output Compare +$ac constant OCR4C \ Timer/Counter4 Output Compare +$a6 constant ICR4 \ Timer/Counter4 Input Capture R +$72 constant TIMSK4 \ Timer/Counter4 Interrupt Mask + $c0 constant TIMSK4_Res \ Reserved Bit + 72 $c0 bitmask: TIMSK4.Res \ Reserved Bit + $20 constant TIMSK4_ICIE4 \ Timer/Counter4 Input Capture I + 72 $20 bitmask: TIMSK4.ICIE4 \ Timer/Counter4 Input Capture I + $10 constant TIMSK4_Res \ Reserved Bit + 72 $10 bitmask: TIMSK4.Res \ Reserved Bit + $8 constant TIMSK4_OCIE4C \ Timer/Counter4 Output Compare + 72 $8 bitmask: TIMSK4.OCIE4C \ Timer/Counter4 Output Compare + $4 constant TIMSK4_OCIE4B \ Timer/Counter4 Output Compare + 72 $4 bitmask: TIMSK4.OCIE4B \ Timer/Counter4 Output Compare + $2 constant TIMSK4_OCIE4A \ Timer/Counter4 Output Compare + 72 $2 bitmask: TIMSK4.OCIE4A \ Timer/Counter4 Output Compare + $1 constant TIMSK4_TOIE4 \ Timer/Counter4 Overflow Interr + 72 $1 bitmask: TIMSK4.TOIE4 \ Timer/Counter4 Overflow Interr +$39 constant TIFR4 \ Timer/Counter4 Interrupt Flag + $c0 constant TIFR4_Res \ Reserved Bit + 39 $c0 bitmask: TIFR4.Res \ Reserved Bit + $20 constant TIFR4_ICF4 \ Timer/Counter4 Input Capture F + 39 $20 bitmask: TIFR4.ICF4 \ Timer/Counter4 Input Capture F + $10 constant TIFR4_Res \ Reserved Bit + 39 $10 bitmask: TIFR4.Res \ Reserved Bit + $8 constant TIFR4_OCF4C \ Timer/Counter4 Output Compare + 39 $8 bitmask: TIFR4.OCF4C \ Timer/Counter4 Output Compare + $4 constant TIFR4_OCF4B \ Timer/Counter4 Output Compare + 39 $4 bitmask: TIFR4.OCF4B \ Timer/Counter4 Output Compare + $2 constant TIFR4_OCF4A \ Timer/Counter4 Output Compare + 39 $2 bitmask: TIFR4.OCF4A \ Timer/Counter4 Output Compare + $1 constant TIFR4_TOV4 \ Timer/Counter4 Overflow Flag + 39 $1 bitmask: TIFR4.TOV4 \ Timer/Counter4 Overflow Flag +\ TIMER_COUNTER_3 +$90 constant TCCR3A \ Timer/Counter3 Control Registe + $c0 constant TCCR3A_COM3A \ Compare Output Mode for Channe + 90 $c0 bitmask: TCCR3A.COM3A \ Compare Output Mode for Channe + $30 constant TCCR3A_COM3B \ Compare Output Mode for Channe + 90 $30 bitmask: TCCR3A.COM3B \ Compare Output Mode for Channe + $c constant TCCR3A_COM3C \ Compare Output Mode for Channe + 90 $c bitmask: TCCR3A.COM3C \ Compare Output Mode for Channe + $3 constant TCCR3A_WGM3 \ Waveform Generation Mode + 90 $3 bitmask: TCCR3A.WGM3 \ Waveform Generation Mode +$91 constant TCCR3B \ Timer/Counter3 Control Registe + $80 constant TCCR3B_ICNC3 \ Input Capture 3 Noise Cancelle + 91 $80 bitmask: TCCR3B.ICNC3 \ Input Capture 3 Noise Cancelle + $40 constant TCCR3B_ICES3 \ Input Capture 3 Edge Select + 91 $40 bitmask: TCCR3B.ICES3 \ Input Capture 3 Edge Select + $20 constant TCCR3B_Res \ Reserved Bit + 91 $20 bitmask: TCCR3B.Res \ Reserved Bit + $18 constant TCCR3B_WGM3 \ Waveform Generation Mode + 91 $18 bitmask: TCCR3B.WGM3 \ Waveform Generation Mode + $7 constant TCCR3B_CS3 \ Clock Select + 91 $7 bitmask: TCCR3B.CS3 \ Clock Select +$92 constant TCCR3C \ Timer/Counter3 Control Registe + $80 constant TCCR3C_FOC3A \ Force Output Compare for Chann + 92 $80 bitmask: TCCR3C.FOC3A \ Force Output Compare for Chann + $40 constant TCCR3C_FOC3B \ Force Output Compare for Chann + 92 $40 bitmask: TCCR3C.FOC3B \ Force Output Compare for Chann + $20 constant TCCR3C_FOC3C \ Force Output Compare for Chann + 92 $20 bitmask: TCCR3C.FOC3C \ Force Output Compare for Chann + $1f constant TCCR3C_Res \ Reserved + 92 $1f bitmask: TCCR3C.Res \ Reserved +$94 constant TCNT3 \ Timer/Counter3 Bytes +$98 constant OCR3A \ Timer/Counter3 Output Compare +$9a constant OCR3B \ Timer/Counter3 Output Compare +$9c constant OCR3C \ Timer/Counter3 Output Compare +$96 constant ICR3 \ Timer/Counter3 Input Capture R +$71 constant TIMSK3 \ Timer/Counter3 Interrupt Mask + $c0 constant TIMSK3_Res \ Reserved Bit + 71 $c0 bitmask: TIMSK3.Res \ Reserved Bit + $20 constant TIMSK3_ICIE3 \ Timer/Counter3 Input Capture I + 71 $20 bitmask: TIMSK3.ICIE3 \ Timer/Counter3 Input Capture I + $10 constant TIMSK3_Res \ Reserved Bit + 71 $10 bitmask: TIMSK3.Res \ Reserved Bit + $8 constant TIMSK3_OCIE3C \ Timer/Counter3 Output Compare + 71 $8 bitmask: TIMSK3.OCIE3C \ Timer/Counter3 Output Compare + $4 constant TIMSK3_OCIE3B \ Timer/Counter3 Output Compare + 71 $4 bitmask: TIMSK3.OCIE3B \ Timer/Counter3 Output Compare + $2 constant TIMSK3_OCIE3A \ Timer/Counter3 Output Compare + 71 $2 bitmask: TIMSK3.OCIE3A \ Timer/Counter3 Output Compare + $1 constant TIMSK3_TOIE3 \ Timer/Counter3 Overflow Interr + 71 $1 bitmask: TIMSK3.TOIE3 \ Timer/Counter3 Overflow Interr +$38 constant TIFR3 \ Timer/Counter3 Interrupt Flag + $c0 constant TIFR3_Res \ Reserved Bit + 38 $c0 bitmask: TIFR3.Res \ Reserved Bit + $20 constant TIFR3_ICF3 \ Timer/Counter3 Input Capture F + 38 $20 bitmask: TIFR3.ICF3 \ Timer/Counter3 Input Capture F + $10 constant TIFR3_Res \ Reserved Bit + 38 $10 bitmask: TIFR3.Res \ Reserved Bit + $8 constant TIFR3_OCF3C \ Timer/Counter3 Output Compare + 38 $8 bitmask: TIFR3.OCF3C \ Timer/Counter3 Output Compare + $4 constant TIFR3_OCF3B \ Timer/Counter3 Output Compare + 38 $4 bitmask: TIFR3.OCF3B \ Timer/Counter3 Output Compare + $2 constant TIFR3_OCF3A \ Timer/Counter3 Output Compare + 38 $2 bitmask: TIFR3.OCF3A \ Timer/Counter3 Output Compare + $1 constant TIFR3_TOV3 \ Timer/Counter3 Overflow Flag + 38 $1 bitmask: TIFR3.TOV3 \ Timer/Counter3 Overflow Flag +\ TIMER_COUNTER_1 +$80 constant TCCR1A \ Timer/Counter1 Control Registe + $c0 constant TCCR1A_COM1A \ Compare Output Mode for Channe + 80 $c0 bitmask: TCCR1A.COM1A \ Compare Output Mode for Channe + $30 constant TCCR1A_COM1B \ Compare Output Mode for Channe + 80 $30 bitmask: TCCR1A.COM1B \ Compare Output Mode for Channe + $c constant TCCR1A_COM1C \ Compare Output Mode for Channe + 80 $c bitmask: TCCR1A.COM1C \ Compare Output Mode for Channe + $3 constant TCCR1A_WGM1 \ Waveform Generation Mode + 80 $3 bitmask: TCCR1A.WGM1 \ Waveform Generation Mode +$81 constant TCCR1B \ Timer/Counter1 Control Registe + $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Cancelle + 81 $80 bitmask: TCCR1B.ICNC1 \ Input Capture 1 Noise Cancelle + $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select + 81 $40 bitmask: TCCR1B.ICES1 \ Input Capture 1 Edge Select + $20 constant TCCR1B_Res \ Reserved Bit + 81 $20 bitmask: TCCR1B.Res \ Reserved Bit + $18 constant TCCR1B_WGM1 \ Waveform Generation Mode + 81 $18 bitmask: TCCR1B.WGM1 \ Waveform Generation Mode + $7 constant TCCR1B_CS1 \ Clock Select + 81 $7 bitmask: TCCR1B.CS1 \ Clock Select +$82 constant TCCR1C \ Timer/Counter1 Control Registe + $80 constant TCCR1C_FOC1A \ Force Output Compare for Chann + 82 $80 bitmask: TCCR1C.FOC1A \ Force Output Compare for Chann + $40 constant TCCR1C_FOC1B \ Force Output Compare for Chann + 82 $40 bitmask: TCCR1C.FOC1B \ Force Output Compare for Chann + $20 constant TCCR1C_FOC1C \ Force Output Compare for Chann + 82 $20 bitmask: TCCR1C.FOC1C \ Force Output Compare for Chann + $1f constant TCCR1C_Res \ Reserved + 82 $1f bitmask: TCCR1C.Res \ Reserved +$84 constant TCNT1 \ Timer/Counter1 Bytes +$88 constant OCR1A \ Timer/Counter1 Output Compare +$8a constant OCR1B \ Timer/Counter1 Output Compare +$8c constant OCR1C \ Timer/Counter1 Output Compare +$86 constant ICR1 \ Timer/Counter1 Input Capture R +$6f constant TIMSK1 \ Timer/Counter1 Interrupt Mask + $c0 constant TIMSK1_Res \ Reserved Bit + 6f $c0 bitmask: TIMSK1.Res \ Reserved Bit + $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture I + 6f $20 bitmask: TIMSK1.ICIE1 \ Timer/Counter1 Input Capture I + $10 constant TIMSK1_Res \ Reserved Bit + 6f $10 bitmask: TIMSK1.Res \ Reserved Bit + $8 constant TIMSK1_OCIE1C \ Timer/Counter1 Output Compare + 6f $8 bitmask: TIMSK1.OCIE1C \ Timer/Counter1 Output Compare + $4 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare + 6f $4 bitmask: TIMSK1.OCIE1B \ Timer/Counter1 Output Compare + $2 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare + 6f $2 bitmask: TIMSK1.OCIE1A \ Timer/Counter1 Output Compare + $1 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interr + 6f $1 bitmask: TIMSK1.TOIE1 \ Timer/Counter1 Overflow Interr +$36 constant TIFR1 \ Timer/Counter1 Interrupt Flag + $c0 constant TIFR1_Res \ Reserved Bit + 36 $c0 bitmask: TIFR1.Res \ Reserved Bit + $20 constant TIFR1_ICF1 \ Timer/Counter1 Input Capture F + 36 $20 bitmask: TIFR1.ICF1 \ Timer/Counter1 Input Capture F + $10 constant TIFR1_Res \ Reserved Bit + 36 $10 bitmask: TIFR1.Res \ Reserved Bit + $8 constant TIFR1_OCF1C \ Timer/Counter1 Output Compare + 36 $8 bitmask: TIFR1.OCF1C \ Timer/Counter1 Output Compare + $4 constant TIFR1_OCF1B \ Timer/Counter1 Output Compare + 36 $4 bitmask: TIFR1.OCF1B \ Timer/Counter1 Output Compare + $2 constant TIFR1_OCF1A \ Timer/Counter1 Output Compare + 36 $2 bitmask: TIFR1.OCF1A \ Timer/Counter1 Output Compare + $1 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag + 36 $1 bitmask: TIFR1.TOV1 \ Timer/Counter1 Overflow Flag +\ TRX24 +$138 constant PARCR \ Power Amplifier Ramp up/down C + $e0 constant PARCR_PALTD \ ext. PA Ramp Down Lead Time + 138 $e0 bitmask: PARCR.PALTD \ ext. PA Ramp Down Lead Time + $1c constant PARCR_PALTU \ ext. PA Ramp Up Lead Time + 138 $1c bitmask: PARCR.PALTU \ ext. PA Ramp Up Lead Time + $2 constant PARCR_PARDFI \ Power Amplifier Ramp Down Freq + 138 $2 bitmask: PARCR.PARDFI \ Power Amplifier Ramp Down Freq + $1 constant PARCR_PARUFI \ Power Amplifier Ramp Up Freque + 138 $1 bitmask: PARCR.PARUFI \ Power Amplifier Ramp Up Freque +$10e constant MAFSA0L \ Transceiver MAC Short Address + $ff constant MAFSA0L_MAFSA0L \ MAC Short Address low Byte for + 10e $ff bitmask: MAFSA0L.MAFSA0L \ MAC Short Address low Byte for +$10f constant MAFSA0H \ Transceiver MAC Short Address + $ff constant MAFSA0H_MAFSA0H \ MAC Short Address high Byte fo + 10f $ff bitmask: MAFSA0H.MAFSA0H \ MAC Short Address high Byte fo +$110 constant MAFPA0L \ Transceiver Personal Area Netw + $ff constant MAFPA0L_MAFPA0L \ MAC Personal Area Network ID l + 110 $ff bitmask: MAFPA0L.MAFPA0L \ MAC Personal Area Network ID l +$111 constant MAFPA0H \ Transceiver Personal Area Netw + $ff constant MAFPA0H_MAFPA0H \ MAC Personal Area Network ID h + 111 $ff bitmask: MAFPA0H.MAFPA0H \ MAC Personal Area Network ID h +$112 constant MAFSA1L \ Transceiver MAC Short Address + $ff constant MAFSA1L_MAFSA1L \ MAC Short Address low Byte for + 112 $ff bitmask: MAFSA1L.MAFSA1L \ MAC Short Address low Byte for +$113 constant MAFSA1H \ Transceiver MAC Short Address + $ff constant MAFSA1H_MAFSA1H \ MAC Short Address high Byte fo + 113 $ff bitmask: MAFSA1H.MAFSA1H \ MAC Short Address high Byte fo +$114 constant MAFPA1L \ Transceiver Personal Area Netw + $ff constant MAFPA1L_MAFPA1L \ MAC Personal Area Network ID l + 114 $ff bitmask: MAFPA1L.MAFPA1L \ MAC Personal Area Network ID l +$115 constant MAFPA1H \ Transceiver Personal Area Netw + $ff constant MAFPA1H_MAFPA1H \ MAC Personal Area Network ID h + 115 $ff bitmask: MAFPA1H.MAFPA1H \ MAC Personal Area Network ID h +$116 constant MAFSA2L \ Transceiver MAC Short Address + $ff constant MAFSA2L_MAFSA2L \ MAC Short Address low Byte for + 116 $ff bitmask: MAFSA2L.MAFSA2L \ MAC Short Address low Byte for +$117 constant MAFSA2H \ Transceiver MAC Short Address + $ff constant MAFSA2H_MAFSA2H \ MAC Short Address high Byte fo + 117 $ff bitmask: MAFSA2H.MAFSA2H \ MAC Short Address high Byte fo +$118 constant MAFPA2L \ Transceiver Personal Area Netw + $ff constant MAFPA2L_MAFPA2L \ MAC Personal Area Network ID l + 118 $ff bitmask: MAFPA2L.MAFPA2L \ MAC Personal Area Network ID l +$119 constant MAFPA2H \ Transceiver Personal Area Netw + $ff constant MAFPA2H_MAFPA2H \ MAC Personal Area Network ID h + 119 $ff bitmask: MAFPA2H.MAFPA2H \ MAC Personal Area Network ID h +$11a constant MAFSA3L \ Transceiver MAC Short Address + $ff constant MAFSA3L_MAFSA3L \ MAC Short Address low Byte for + 11a $ff bitmask: MAFSA3L.MAFSA3L \ MAC Short Address low Byte for +$11b constant MAFSA3H \ Transceiver MAC Short Address + $ff constant MAFSA3H_MAFSA3H \ MAC Short Address high Byte fo + 11b $ff bitmask: MAFSA3H.MAFSA3H \ MAC Short Address high Byte fo +$11c constant MAFPA3L \ Transceiver Personal Area Netw + $ff constant MAFPA3L_MAFPA3L \ MAC Personal Area Network ID l + 11c $ff bitmask: MAFPA3L.MAFPA3L \ MAC Personal Area Network ID l +$11d constant MAFPA3H \ Transceiver Personal Area Netw + $ff constant MAFPA3H_MAFPA3H \ MAC Personal Area Network ID h + 11d $ff bitmask: MAFPA3H.MAFPA3H \ MAC Personal Area Network ID h +$10c constant MAFCR0 \ Multiple Address Filter Config + $f0 constant MAFCR0_Res \ Reserved Bit + 10c $f0 bitmask: MAFCR0.Res \ Reserved Bit + $8 constant MAFCR0_MAF3EN \ Multiple Address Filter 3 Enab + 10c $8 bitmask: MAFCR0.MAF3EN \ Multiple Address Filter 3 Enab + $4 constant MAFCR0_MAF2EN \ Multiple Address Filter 2 Enab + 10c $4 bitmask: MAFCR0.MAF2EN \ Multiple Address Filter 2 Enab + $2 constant MAFCR0_MAF1EN \ Multiple Address Filter 1 Enab + 10c $2 bitmask: MAFCR0.MAF1EN \ Multiple Address Filter 1 Enab + $1 constant MAFCR0_MAF0EN \ Multiple Address Filter 0 Enab + 10c $1 bitmask: MAFCR0.MAF0EN \ Multiple Address Filter 0 Enab +$10d constant MAFCR1 \ Multiple Address Filter Config + $80 constant MAFCR1_AACK_3_SET_PD \ Set Data Pending bit for addre + 10d $80 bitmask: MAFCR1.AACK_3_SET_PD \ Set Data Pending bit for addre + $40 constant MAFCR1_AACK_3_I_AM_COORD \ Enable PAN Coordinator mode fo + 10d $40 bitmask: MAFCR1.AACK_3_I_AM_COORD \ Enable PAN Coordinator mode fo + $20 constant MAFCR1_AACK_2_SET_PD \ Set Data Pending bit for addre + 10d $20 bitmask: MAFCR1.AACK_2_SET_PD \ Set Data Pending bit for addre + $10 constant MAFCR1_AACK_2_I_AM_COORD \ Enable PAN Coordinator mode fo + 10d $10 bitmask: MAFCR1.AACK_2_I_AM_COORD \ Enable PAN Coordinator mode fo + $8 constant MAFCR1_AACK_1_SET_PD \ Set Data Pending bit for addre + 10d $8 bitmask: MAFCR1.AACK_1_SET_PD \ Set Data Pending bit for addre + $4 constant MAFCR1_AACK_1_I_AM_COORD \ Enable PAN Coordinator mode fo + 10d $4 bitmask: MAFCR1.AACK_1_I_AM_COORD \ Enable PAN Coordinator mode fo + $2 constant MAFCR1_AACK_0_SET_PD \ Set Data Pending bit for addre + 10d $2 bitmask: MAFCR1.AACK_0_SET_PD \ Set Data Pending bit for addre + $1 constant MAFCR1_AACK_0_I_AM_COORD \ Enable PAN Coordinator mode fo + 10d $1 bitmask: MAFCR1.AACK_0_I_AM_COORD \ Enable PAN Coordinator mode fo +$13c constant AES_CTRL \ AES Control Register + $80 constant AES_CTRL_AES_REQUEST \ Request AES Operation. + 13c $80 bitmask: AES_CTRL.AES_REQUEST \ Request AES Operation. + $40 constant AES_CTRL_Res \ Reserved Bit + 13c $40 bitmask: AES_CTRL.Res \ Reserved Bit + $20 constant AES_CTRL_AES_MODE \ Set AES Operation Mode + 13c $20 bitmask: AES_CTRL.AES_MODE \ Set AES Operation Mode + $10 constant AES_CTRL_Res \ Reserved Bit + 13c $10 bitmask: AES_CTRL.Res \ Reserved Bit + $8 constant AES_CTRL_AES_DIR \ Set AES Operation Direction + 13c $8 bitmask: AES_CTRL.AES_DIR \ Set AES Operation Direction + $4 constant AES_CTRL_AES_IM \ AES Interrupt Enable + 13c $4 bitmask: AES_CTRL.AES_IM \ AES Interrupt Enable + $3 constant AES_CTRL_Res \ Reserved Bit + 13c $3 bitmask: AES_CTRL.Res \ Reserved Bit +$13d constant AES_STATUS \ AES Status Register + $80 constant AES_STATUS_AES_ER \ AES Operation Finished with Er + 13d $80 bitmask: AES_STATUS.AES_ER \ AES Operation Finished with Er + $7e constant AES_STATUS_Res \ Reserved + 13d $7e bitmask: AES_STATUS.Res \ Reserved + $1 constant AES_STATUS_AES_DONE \ AES Operation Finished with Su + 13d $1 bitmask: AES_STATUS.AES_DONE \ AES Operation Finished with Su +$13e constant AES_STATE \ AES Plain and Cipher Text Buff + $ff constant AES_STATE_AES_STATE \ AES Plain and Cipher Text Buff + 13e $ff bitmask: AES_STATE.AES_STATE \ AES Plain and Cipher Text Buff +$13f constant AES_KEY \ AES Encryption and Decryption + $ff constant AES_KEY_AES_KEY \ AES Encryption/Decryption Key + 13f $ff bitmask: AES_KEY.AES_KEY \ AES Encryption/Decryption Key +$141 constant TRX_STATUS \ Transceiver Status Register + $80 constant TRX_STATUS_CCA_DONE \ CCA Algorithm Status + 141 $80 bitmask: TRX_STATUS.CCA_DONE \ CCA Algorithm Status + $40 constant TRX_STATUS_CCA_STATUS \ CCA Status Result + 141 $40 bitmask: TRX_STATUS.CCA_STATUS \ CCA Status Result + $20 constant TRX_STATUS_TST_STATUS \ Test mode status + 141 $20 bitmask: TRX_STATUS.TST_STATUS \ Test mode status + $1f constant TRX_STATUS_TRX_STATUS \ Transceiver Main Status + 141 $1f bitmask: TRX_STATUS.TRX_STATUS \ Transceiver Main Status +$142 constant TRX_STATE \ Transceiver State Control Regi + $e0 constant TRX_STATE_TRAC_STATUS \ Transaction Status + 142 $e0 bitmask: TRX_STATE.TRAC_STATUS \ Transaction Status + $1f constant TRX_STATE_TRX_CMD \ State Control Command + 142 $1f bitmask: TRX_STATE.TRX_CMD \ State Control Command +$143 constant TRX_CTRL_0 \ Reserved + $80 constant TRX_CTRL_0_Res7 \ Reserved + 143 $80 bitmask: TRX_CTRL_0.Res7 \ Reserved + $40 constant TRX_CTRL_0_PMU_EN \ Enable Phase Measurement Unit + 143 $40 bitmask: TRX_CTRL_0.PMU_EN \ Enable Phase Measurement Unit + $20 constant TRX_CTRL_0_PMU_START \ Start of Phase Measurement Uni + 143 $20 bitmask: TRX_CTRL_0.PMU_START \ Start of Phase Measurement Uni + $10 constant TRX_CTRL_0_PMU_IF_INV \ PMU IF Inverse + 143 $10 bitmask: TRX_CTRL_0.PMU_IF_INV \ PMU IF Inverse + $f constant TRX_CTRL_0_Res \ Reserved + 143 $f bitmask: TRX_CTRL_0.Res \ Reserved +$144 constant TRX_CTRL_1 \ Transceiver Control Register 1 + $80 constant TRX_CTRL_1_PA_EXT_EN \ External PA support enable + 144 $80 bitmask: TRX_CTRL_1.PA_EXT_EN \ External PA support enable + $40 constant TRX_CTRL_1_IRQ_2_EXT_EN \ Connect Frame Start IRQ to TC1 + 144 $40 bitmask: TRX_CTRL_1.IRQ_2_EXT_EN \ Connect Frame Start IRQ to TC1 + $20 constant TRX_CTRL_1_TX_AUTO_CRC_ON \ Enable Automatic CRC Calculati + 144 $20 bitmask: TRX_CTRL_1.TX_AUTO_CRC_ON \ Enable Automatic CRC Calculati + $10 constant TRX_CTRL_1_PLL_TX_FLT \ Enable PLL TX filter + 144 $10 bitmask: TRX_CTRL_1.PLL_TX_FLT \ Enable PLL TX filter + $f constant TRX_CTRL_1_Res \ Reserved + 144 $f bitmask: TRX_CTRL_1.Res \ Reserved +$145 constant PHY_TX_PWR \ Transceiver Transmit Power Con + $f0 constant PHY_TX_PWR_Res \ Reserved + 145 $f0 bitmask: PHY_TX_PWR.Res \ Reserved + $f constant PHY_TX_PWR_TX_PWR \ Transmit Power Setting + 145 $f bitmask: PHY_TX_PWR.TX_PWR \ Transmit Power Setting +$146 constant PHY_RSSI \ Receiver Signal Strength Indic + $80 constant PHY_RSSI_RX_CRC_VALID \ Received Frame CRC Status + 146 $80 bitmask: PHY_RSSI.RX_CRC_VALID \ Received Frame CRC Status + $60 constant PHY_RSSI_RND_VALUE \ Random Value + 146 $60 bitmask: PHY_RSSI.RND_VALUE \ Random Value + $1f constant PHY_RSSI_RSSI \ Receiver Signal Strength Indic + 146 $1f bitmask: PHY_RSSI.RSSI \ Receiver Signal Strength Indic +$147 constant PHY_ED_LEVEL \ Transceiver Energy Detection L + $ff constant PHY_ED_LEVEL_ED_LEVEL \ Energy Detection Level + 147 $ff bitmask: PHY_ED_LEVEL.ED_LEVEL \ Energy Detection Level +$148 constant PHY_CC_CCA \ Transceiver Clear Channel Asse + $80 constant PHY_CC_CCA_CCA_REQUEST \ Manual CCA Measurement Request + 148 $80 bitmask: PHY_CC_CCA.CCA_REQUEST \ Manual CCA Measurement Request + $60 constant PHY_CC_CCA_CCA_MODE \ Select CCA Measurement Mode + 148 $60 bitmask: PHY_CC_CCA.CCA_MODE \ Select CCA Measurement Mode + $1f constant PHY_CC_CCA_CHANNEL \ RX/TX Channel Selection + 148 $1f bitmask: PHY_CC_CCA.CHANNEL \ RX/TX Channel Selection +$149 constant CCA_THRES \ Transceiver CCA Threshold Sett + $f0 constant CCA_THRES_CCA_CS_THRES \ CS Threshold Level for CCA Mea + 149 $f0 bitmask: CCA_THRES.CCA_CS_THRES \ CS Threshold Level for CCA Mea + $f constant CCA_THRES_CCA_ED_THRES \ ED Threshold Level for CCA Mea + 149 $f bitmask: CCA_THRES.CCA_ED_THRES \ ED Threshold Level for CCA Mea +$14a constant RX_CTRL \ Transceiver Receive Control Re + $f constant RX_CTRL_PDT_THRES \ Receiver Sensitivity Control + 14a $f bitmask: RX_CTRL.PDT_THRES \ Receiver Sensitivity Control +$14b constant SFD_VALUE \ Start of Frame Delimiter Value + $ff constant SFD_VALUE_SFD_VALUE \ Start of Frame Delimiter Value + 14b $ff bitmask: SFD_VALUE.SFD_VALUE \ Start of Frame Delimiter Value +$14c constant TRX_CTRL_2 \ Transceiver Control Register 2 + $80 constant TRX_CTRL_2_RX_SAFE_MODE \ RX Safe Mode + 14c $80 bitmask: TRX_CTRL_2.RX_SAFE_MODE \ RX Safe Mode + $7c constant TRX_CTRL_2_Res \ Reserved + 14c $7c bitmask: TRX_CTRL_2.Res \ Reserved + $3 constant TRX_CTRL_2_OQPSK_DATA_RATE \ Data Rate Selection + 14c $3 bitmask: TRX_CTRL_2.OQPSK_DATA_RATE \ Data Rate Selection +$14d constant ANT_DIV \ Antenna Diversity Control Regi + $80 constant ANT_DIV_ANT_SEL \ Antenna Diversity Antenna Stat + 14d $80 bitmask: ANT_DIV.ANT_SEL \ Antenna Diversity Antenna Stat + $70 constant ANT_DIV_Res \ Reserved + 14d $70 bitmask: ANT_DIV.Res \ Reserved + $8 constant ANT_DIV_ANT_DIV_EN \ Enable Antenna Diversity + 14d $8 bitmask: ANT_DIV.ANT_DIV_EN \ Enable Antenna Diversity + $4 constant ANT_DIV_ANT_EXT_SW_EN \ Enable External Antenna Switch + 14d $4 bitmask: ANT_DIV.ANT_EXT_SW_EN \ Enable External Antenna Switch + $3 constant ANT_DIV_ANT_CTRL \ Static Antenna Diversity Switc + 14d $3 bitmask: ANT_DIV.ANT_CTRL \ Static Antenna Diversity Switc +$14e constant IRQ_MASK \ Transceiver Interrupt Enable R + $80 constant IRQ_MASK_AWAKE_EN \ Awake Interrupt Enable + 14e $80 bitmask: IRQ_MASK.AWAKE_EN \ Awake Interrupt Enable + $40 constant IRQ_MASK_TX_END_EN \ TX_END Interrupt Enable + 14e $40 bitmask: IRQ_MASK.TX_END_EN \ TX_END Interrupt Enable + $20 constant IRQ_MASK_AMI_EN \ Address Match Interrupt Enable + 14e $20 bitmask: IRQ_MASK.AMI_EN \ Address Match Interrupt Enable + $10 constant IRQ_MASK_CCA_ED_DONE_EN \ End of ED Measurement Interrup + 14e $10 bitmask: IRQ_MASK.CCA_ED_DONE_EN \ End of ED Measurement Interrup + $8 constant IRQ_MASK_RX_END_EN \ RX_END Interrupt Enable + 14e $8 bitmask: IRQ_MASK.RX_END_EN \ RX_END Interrupt Enable + $4 constant IRQ_MASK_RX_START_EN \ RX_START Interrupt Enable + 14e $4 bitmask: IRQ_MASK.RX_START_EN \ RX_START Interrupt Enable + $2 constant IRQ_MASK_PLL_UNLOCK_EN \ PLL Unlock Interrupt Enable + 14e $2 bitmask: IRQ_MASK.PLL_UNLOCK_EN \ PLL Unlock Interrupt Enable + $1 constant IRQ_MASK_PLL_LOCK_EN \ PLL Lock Interrupt Enable + 14e $1 bitmask: IRQ_MASK.PLL_LOCK_EN \ PLL Lock Interrupt Enable +$14f constant IRQ_STATUS \ Transceiver Interrupt Status R + $80 constant IRQ_STATUS_AWAKE \ Awake Interrupt Status + 14f $80 bitmask: IRQ_STATUS.AWAKE \ Awake Interrupt Status + $40 constant IRQ_STATUS_TX_END \ TX_END Interrupt Status + 14f $40 bitmask: IRQ_STATUS.TX_END \ TX_END Interrupt Status + $20 constant IRQ_STATUS_AMI \ Address Match Interrupt Status + 14f $20 bitmask: IRQ_STATUS.AMI \ Address Match Interrupt Status + $10 constant IRQ_STATUS_CCA_ED_DONE \ End of ED Measurement Interrup + 14f $10 bitmask: IRQ_STATUS.CCA_ED_DONE \ End of ED Measurement Interrup + $8 constant IRQ_STATUS_RX_END \ RX_END Interrupt Status + 14f $8 bitmask: IRQ_STATUS.RX_END \ RX_END Interrupt Status + $4 constant IRQ_STATUS_RX_START \ RX_START Interrupt Status + 14f $4 bitmask: IRQ_STATUS.RX_START \ RX_START Interrupt Status + $2 constant IRQ_STATUS_PLL_UNLOCK \ PLL Unlock Interrupt Status + 14f $2 bitmask: IRQ_STATUS.PLL_UNLOCK \ PLL Unlock Interrupt Status + $1 constant IRQ_STATUS_PLL_LOCK \ PLL Lock Interrupt Status + 14f $1 bitmask: IRQ_STATUS.PLL_LOCK \ PLL Lock Interrupt Status +$be constant IRQ_MASK1 \ Transceiver Interrupt Enable R + $e0 constant IRQ_MASK1_Res \ Reserved Bit + be $e0 bitmask: IRQ_MASK1.Res \ Reserved Bit + $10 constant IRQ_MASK1_MAF_3_AMI_EN \ Address Match Interrupt enable + be $10 bitmask: IRQ_MASK1.MAF_3_AMI_EN \ Address Match Interrupt enable + $8 constant IRQ_MASK1_MAF_2_AMI_EN \ Address Match Interrupt enable + be $8 bitmask: IRQ_MASK1.MAF_2_AMI_EN \ Address Match Interrupt enable + $4 constant IRQ_MASK1_MAF_1_AMI_EN \ Address Match Interrupt enable + be $4 bitmask: IRQ_MASK1.MAF_1_AMI_EN \ Address Match Interrupt enable + $2 constant IRQ_MASK1_MAF_0_AMI_EN \ Address Match Interrupt enable + be $2 bitmask: IRQ_MASK1.MAF_0_AMI_EN \ Address Match Interrupt enable + $1 constant IRQ_MASK1_TX_START_EN \ Transmit Start Interrupt enabl + be $1 bitmask: IRQ_MASK1.TX_START_EN \ Transmit Start Interrupt enabl +$bf constant IRQ_STATUS1 \ Transceiver Interrupt Status R + $e0 constant IRQ_STATUS1_Res \ Reserved Bit + bf $e0 bitmask: IRQ_STATUS1.Res \ Reserved Bit + $10 constant IRQ_STATUS1_MAF_3_AMI \ Address Match Interrupt Status + bf $10 bitmask: IRQ_STATUS1.MAF_3_AMI \ Address Match Interrupt Status + $8 constant IRQ_STATUS1_MAF_2_AMI \ Address Match Interrupt Status + bf $8 bitmask: IRQ_STATUS1.MAF_2_AMI \ Address Match Interrupt Status + $4 constant IRQ_STATUS1_MAF_1_AMI \ Address Match Interrupt Status + bf $4 bitmask: IRQ_STATUS1.MAF_1_AMI \ Address Match Interrupt Status + $2 constant IRQ_STATUS1_MAF_0_AMI \ Address Match Interrupt Status + bf $2 bitmask: IRQ_STATUS1.MAF_0_AMI \ Address Match Interrupt Status + $1 constant IRQ_STATUS1_TX_START \ Transmit Start Interrupt Statu + bf $1 bitmask: IRQ_STATUS1.TX_START \ Transmit Start Interrupt Statu +$150 constant VREG_CTRL \ Voltage Regulator Control and + $80 constant VREG_CTRL_AVREG_EXT \ Use External AVDD Regulator + 150 $80 bitmask: VREG_CTRL.AVREG_EXT \ Use External AVDD Regulator + $40 constant VREG_CTRL_AVDD_OK \ AVDD Supply Voltage Valid + 150 $40 bitmask: VREG_CTRL.AVDD_OK \ AVDD Supply Voltage Valid + $8 constant VREG_CTRL_DVREG_EXT \ Use External DVDD Regulator + 150 $8 bitmask: VREG_CTRL.DVREG_EXT \ Use External DVDD Regulator + $4 constant VREG_CTRL_DVDD_OK \ DVDD Supply Voltage Valid + 150 $4 bitmask: VREG_CTRL.DVDD_OK \ DVDD Supply Voltage Valid +$151 constant BATMON \ Battery Monitor Control and St + $80 constant BATMON_BAT_LOW \ Battery Monitor Interrupt Stat + 151 $80 bitmask: BATMON.BAT_LOW \ Battery Monitor Interrupt Stat + $40 constant BATMON_BAT_LOW_EN \ Battery Monitor Interrupt Enab + 151 $40 bitmask: BATMON.BAT_LOW_EN \ Battery Monitor Interrupt Enab + $20 constant BATMON_BATMON_OK \ Battery Monitor Status + 151 $20 bitmask: BATMON.BATMON_OK \ Battery Monitor Status + $10 constant BATMON_BATMON_HR \ Battery Monitor Voltage Range + 151 $10 bitmask: BATMON.BATMON_HR \ Battery Monitor Voltage Range + $f constant BATMON_BATMON_VTH \ Battery Monitor Threshold Volt + 151 $f bitmask: BATMON.BATMON_VTH \ Battery Monitor Threshold Volt +$152 constant XOSC_CTRL \ Crystal Oscillator Control Reg + $f0 constant XOSC_CTRL_XTAL_MODE \ Crystal Oscillator Operating M + 152 $f0 bitmask: XOSC_CTRL.XTAL_MODE \ Crystal Oscillator Operating M + $f constant XOSC_CTRL_XTAL_TRIM \ Crystal Oscillator Load Capaci + 152 $f bitmask: XOSC_CTRL.XTAL_TRIM \ Crystal Oscillator Load Capaci +$153 constant CC_CTRL_0 \ Channel Control Register 0 + $ff constant CC_CTRL_0_CC_NUMBER \ Channel Number + 153 $ff bitmask: CC_CTRL_0.CC_NUMBER \ Channel Number +$154 constant CC_CTRL_1 \ Channel Control Register 1 + $f constant CC_CTRL_1_CC_BAND \ Channel Band + 154 $f bitmask: CC_CTRL_1.CC_BAND \ Channel Band +$155 constant RX_SYN \ Transceiver Receiver Sensitivi + $80 constant RX_SYN_RX_PDT_DIS \ Prevent Frame Reception + 155 $80 bitmask: RX_SYN.RX_PDT_DIS \ Prevent Frame Reception + $40 constant RX_SYN_RX_OVERRIDE \ Receiver Override Function + 155 $40 bitmask: RX_SYN.RX_OVERRIDE \ Receiver Override Function + $30 constant RX_SYN_Res \ Reserved + 155 $30 bitmask: RX_SYN.Res \ Reserved + $f constant RX_SYN_RX_PDT_LEVEL \ Reduce Receiver Sensitivity + 155 $f bitmask: RX_SYN.RX_PDT_LEVEL \ Reduce Receiver Sensitivity +$156 constant TRX_RPC \ Transceiver Reduced Power Cons + $c0 constant TRX_RPC_RX_RPC_CTRL \ Smart Receiving Mode Timing + 156 $c0 bitmask: TRX_RPC.RX_RPC_CTRL \ Smart Receiving Mode Timing + $20 constant TRX_RPC_RX_RPC_EN \ Reciver Smart Receiving Mode E + 156 $20 bitmask: TRX_RPC.RX_RPC_EN \ Reciver Smart Receiving Mode E + $10 constant TRX_RPC_PDT_RPC_EN \ Smart Receiving Mode Reduced S + 156 $10 bitmask: TRX_RPC.PDT_RPC_EN \ Smart Receiving Mode Reduced S + $8 constant TRX_RPC_PLL_RPC_EN \ PLL Smart Receiving Mode Enabl + 156 $8 bitmask: TRX_RPC.PLL_RPC_EN \ PLL Smart Receiving Mode Enabl + $4 constant TRX_RPC_Res0 \ Reserved + 156 $4 bitmask: TRX_RPC.Res0 \ Reserved + $2 constant TRX_RPC_IPAN_RPC_EN \ Smart Receiving Mode IPAN Hand + 156 $2 bitmask: TRX_RPC.IPAN_RPC_EN \ Smart Receiving Mode IPAN Hand + $1 constant TRX_RPC_XAH_RPC_EN \ Smart Receiving in Extended Op + 156 $1 bitmask: TRX_RPC.XAH_RPC_EN \ Smart Receiving in Extended Op +$157 constant XAH_CTRL_1 \ Transceiver Acknowledgment Fra + $c0 constant XAH_CTRL_1_Res \ Reserved Bit + 157 $c0 bitmask: XAH_CTRL_1.Res \ Reserved Bit + $20 constant XAH_CTRL_1_AACK_FLTR_RES_FT \ Filter Reserved Frames + 157 $20 bitmask: XAH_CTRL_1.AACK_FLTR_RES_FT \ Filter Reserved Frames + $10 constant XAH_CTRL_1_AACK_UPLD_RES_FT \ Process Reserved Frames + 157 $10 bitmask: XAH_CTRL_1.AACK_UPLD_RES_FT \ Process Reserved Frames + $8 constant XAH_CTRL_1_Res \ Reserved Bit + 157 $8 bitmask: XAH_CTRL_1.Res \ Reserved Bit + $4 constant XAH_CTRL_1_AACK_ACK_TIME \ Reduce Acknowledgment Time + 157 $4 bitmask: XAH_CTRL_1.AACK_ACK_TIME \ Reduce Acknowledgment Time + $2 constant XAH_CTRL_1_AACK_PROM_MODE \ Enable Promiscuous Mode + 157 $2 bitmask: XAH_CTRL_1.AACK_PROM_MODE \ Enable Promiscuous Mode + $1 constant XAH_CTRL_1_Res \ Reserved Bit + 157 $1 bitmask: XAH_CTRL_1.Res \ Reserved Bit +$158 constant FTN_CTRL \ Transceiver Filter Tuning Cont + $80 constant FTN_CTRL_FTN_START \ Start Calibration Loop of Filt + 158 $80 bitmask: FTN_CTRL.FTN_START \ Start Calibration Loop of Filt +$15a constant PLL_CF \ Transceiver Center Frequency C + $80 constant PLL_CF_PLL_CF_START \ Start Center Frequency Calibra + 15a $80 bitmask: PLL_CF.PLL_CF_START \ Start Center Frequency Calibra +$15b constant PLL_DCU \ Transceiver Delay Cell Calibra + $80 constant PLL_DCU_PLL_DCU_START \ Start Delay Cell Calibration + 15b $80 bitmask: PLL_DCU.PLL_DCU_START \ Start Delay Cell Calibration +$15c constant PART_NUM \ Device Identification Register + $ff constant PART_NUM_PART_NUM \ Part Number + 15c $ff bitmask: PART_NUM.PART_NUM \ Part Number +$15d constant VERSION_NUM \ Device Identification Register + $ff constant VERSION_NUM_VERSION_NUM \ Version Number + 15d $ff bitmask: VERSION_NUM.VERSION_NUM \ Version Number +$15e constant MAN_ID_0 \ Device Identification Register + $80 constant MAN_ID_0_MAN_ID_07 \ Manufacturer ID (Low Byte) + 15e $80 bitmask: MAN_ID_0.MAN_ID_07 \ Manufacturer ID (Low Byte) + $40 constant MAN_ID_0_MAN_ID_06 \ Manufacturer ID (Low Byte) + 15e $40 bitmask: MAN_ID_0.MAN_ID_06 \ Manufacturer ID (Low Byte) + $20 constant MAN_ID_0_MAN_ID_05 \ Manufacturer ID (Low Byte) + 15e $20 bitmask: MAN_ID_0.MAN_ID_05 \ Manufacturer ID (Low Byte) + $10 constant MAN_ID_0_MAN_ID_04 \ Manufacturer ID (Low Byte) + 15e $10 bitmask: MAN_ID_0.MAN_ID_04 \ Manufacturer ID (Low Byte) + $8 constant MAN_ID_0_MAN_ID_03 \ Manufacturer ID (Low Byte) + 15e $8 bitmask: MAN_ID_0.MAN_ID_03 \ Manufacturer ID (Low Byte) + $4 constant MAN_ID_0_MAN_ID_02 \ Manufacturer ID (Low Byte) + 15e $4 bitmask: MAN_ID_0.MAN_ID_02 \ Manufacturer ID (Low Byte) + $2 constant MAN_ID_0_MAN_ID_01 \ Manufacturer ID (Low Byte) + 15e $2 bitmask: MAN_ID_0.MAN_ID_01 \ Manufacturer ID (Low Byte) + $1 constant MAN_ID_0_MAN_ID_00 \ Manufacturer ID (Low Byte) + 15e $1 bitmask: MAN_ID_0.MAN_ID_00 \ Manufacturer ID (Low Byte) +$15f constant MAN_ID_1 \ Device Identification Register + $ff constant MAN_ID_1_MAN_ID_ \ Manufacturer ID (High Byte) + 15f $ff bitmask: MAN_ID_1.MAN_ID_ \ Manufacturer ID (High Byte) +$160 constant SHORT_ADDR_0 \ Transceiver MAC Short Address + $80 constant SHORT_ADDR_0_SHORT_ADDR_07 \ MAC Short Address + 160 $80 bitmask: SHORT_ADDR_0.SHORT_ADDR_07 \ MAC Short Address + $40 constant SHORT_ADDR_0_SHORT_ADDR_06 \ MAC Short Address + 160 $40 bitmask: SHORT_ADDR_0.SHORT_ADDR_06 \ MAC Short Address + $20 constant SHORT_ADDR_0_SHORT_ADDR_05 \ MAC Short Address + 160 $20 bitmask: SHORT_ADDR_0.SHORT_ADDR_05 \ MAC Short Address + $10 constant SHORT_ADDR_0_SHORT_ADDR_04 \ MAC Short Address + 160 $10 bitmask: SHORT_ADDR_0.SHORT_ADDR_04 \ MAC Short Address + $8 constant SHORT_ADDR_0_SHORT_ADDR_03 \ MAC Short Address + 160 $8 bitmask: SHORT_ADDR_0.SHORT_ADDR_03 \ MAC Short Address + $4 constant SHORT_ADDR_0_SHORT_ADDR_02 \ MAC Short Address + 160 $4 bitmask: SHORT_ADDR_0.SHORT_ADDR_02 \ MAC Short Address + $2 constant SHORT_ADDR_0_SHORT_ADDR_01 \ MAC Short Address + 160 $2 bitmask: SHORT_ADDR_0.SHORT_ADDR_01 \ MAC Short Address + $1 constant SHORT_ADDR_0_SHORT_ADDR_00 \ MAC Short Address + 160 $1 bitmask: SHORT_ADDR_0.SHORT_ADDR_00 \ MAC Short Address +$161 constant SHORT_ADDR_1 \ Transceiver MAC Short Address + $ff constant SHORT_ADDR_1_SHORT_ADDR_ \ MAC Short Address + 161 $ff bitmask: SHORT_ADDR_1.SHORT_ADDR_ \ MAC Short Address +$162 constant PAN_ID_0 \ Transceiver Personal Area Netw + $80 constant PAN_ID_0_PAN_ID_07 \ MAC Personal Area Network ID + 162 $80 bitmask: PAN_ID_0.PAN_ID_07 \ MAC Personal Area Network ID + $40 constant PAN_ID_0_PAN_ID_06 \ MAC Personal Area Network ID + 162 $40 bitmask: PAN_ID_0.PAN_ID_06 \ MAC Personal Area Network ID + $20 constant PAN_ID_0_PAN_ID_05 \ MAC Personal Area Network ID + 162 $20 bitmask: PAN_ID_0.PAN_ID_05 \ MAC Personal Area Network ID + $10 constant PAN_ID_0_PAN_ID_04 \ MAC Personal Area Network ID + 162 $10 bitmask: PAN_ID_0.PAN_ID_04 \ MAC Personal Area Network ID + $8 constant PAN_ID_0_PAN_ID_03 \ MAC Personal Area Network ID + 162 $8 bitmask: PAN_ID_0.PAN_ID_03 \ MAC Personal Area Network ID + $4 constant PAN_ID_0_PAN_ID_02 \ MAC Personal Area Network ID + 162 $4 bitmask: PAN_ID_0.PAN_ID_02 \ MAC Personal Area Network ID + $2 constant PAN_ID_0_PAN_ID_01 \ MAC Personal Area Network ID + 162 $2 bitmask: PAN_ID_0.PAN_ID_01 \ MAC Personal Area Network ID + $1 constant PAN_ID_0_PAN_ID_00 \ MAC Personal Area Network ID + 162 $1 bitmask: PAN_ID_0.PAN_ID_00 \ MAC Personal Area Network ID +$163 constant PAN_ID_1 \ Transceiver Personal Area Netw + $ff constant PAN_ID_1_PAN_ID_ \ MAC Personal Area Network ID + 163 $ff bitmask: PAN_ID_1.PAN_ID_ \ MAC Personal Area Network ID +$164 constant IEEE_ADDR_0 \ Transceiver MAC IEEE Address R + $80 constant IEEE_ADDR_0_IEEE_ADDR_07 \ MAC IEEE Address + 164 $80 bitmask: IEEE_ADDR_0.IEEE_ADDR_07 \ MAC IEEE Address + $40 constant IEEE_ADDR_0_IEEE_ADDR_06 \ MAC IEEE Address + 164 $40 bitmask: IEEE_ADDR_0.IEEE_ADDR_06 \ MAC IEEE Address + $20 constant IEEE_ADDR_0_IEEE_ADDR_05 \ MAC IEEE Address + 164 $20 bitmask: IEEE_ADDR_0.IEEE_ADDR_05 \ MAC IEEE Address + $10 constant IEEE_ADDR_0_IEEE_ADDR_04 \ MAC IEEE Address + 164 $10 bitmask: IEEE_ADDR_0.IEEE_ADDR_04 \ MAC IEEE Address + $8 constant IEEE_ADDR_0_IEEE_ADDR_03 \ MAC IEEE Address + 164 $8 bitmask: IEEE_ADDR_0.IEEE_ADDR_03 \ MAC IEEE Address + $4 constant IEEE_ADDR_0_IEEE_ADDR_02 \ MAC IEEE Address + 164 $4 bitmask: IEEE_ADDR_0.IEEE_ADDR_02 \ MAC IEEE Address + $2 constant IEEE_ADDR_0_IEEE_ADDR_01 \ MAC IEEE Address + 164 $2 bitmask: IEEE_ADDR_0.IEEE_ADDR_01 \ MAC IEEE Address + $1 constant IEEE_ADDR_0_IEEE_ADDR_00 \ MAC IEEE Address + 164 $1 bitmask: IEEE_ADDR_0.IEEE_ADDR_00 \ MAC IEEE Address +$165 constant IEEE_ADDR_1 \ Transceiver MAC IEEE Address R + $ff constant IEEE_ADDR_1_IEEE_ADDR_ \ MAC IEEE Address + 165 $ff bitmask: IEEE_ADDR_1.IEEE_ADDR_ \ MAC IEEE Address +$166 constant IEEE_ADDR_2 \ Transceiver MAC IEEE Address R + $ff constant IEEE_ADDR_2_IEEE_ADDR_ \ MAC IEEE Address + 166 $ff bitmask: IEEE_ADDR_2.IEEE_ADDR_ \ MAC IEEE Address +$167 constant IEEE_ADDR_3 \ Transceiver MAC IEEE Address R + $ff constant IEEE_ADDR_3_IEEE_ADDR_ \ MAC IEEE Address + 167 $ff bitmask: IEEE_ADDR_3.IEEE_ADDR_ \ MAC IEEE Address +$168 constant IEEE_ADDR_4 \ Transceiver MAC IEEE Address R + $ff constant IEEE_ADDR_4_IEEE_ADDR_ \ MAC IEEE Address + 168 $ff bitmask: IEEE_ADDR_4.IEEE_ADDR_ \ MAC IEEE Address +$169 constant IEEE_ADDR_5 \ Transceiver MAC IEEE Address R + $ff constant IEEE_ADDR_5_IEEE_ADDR_ \ MAC IEEE Address + 169 $ff bitmask: IEEE_ADDR_5.IEEE_ADDR_ \ MAC IEEE Address +$16a constant IEEE_ADDR_6 \ Transceiver MAC IEEE Address R + $ff constant IEEE_ADDR_6_IEEE_ADDR_ \ MAC IEEE Address + 16a $ff bitmask: IEEE_ADDR_6.IEEE_ADDR_ \ MAC IEEE Address +$16b constant IEEE_ADDR_7 \ Transceiver MAC IEEE Address R + $ff constant IEEE_ADDR_7_IEEE_ADDR_ \ MAC IEEE Address + 16b $ff bitmask: IEEE_ADDR_7.IEEE_ADDR_ \ MAC IEEE Address +$16c constant XAH_CTRL_0 \ Transceiver Extended Operating + $f0 constant XAH_CTRL_0_MAX_FRAME_RETRIES \ Maximum Number of Frame Re-tra + 16c $f0 bitmask: XAH_CTRL_0.MAX_FRAME_RETRIES \ Maximum Number of Frame Re-tra + $e constant XAH_CTRL_0_MAX_CSMA_RETRIES \ Maximum Number of CSMA-CA Proc + 16c $e bitmask: XAH_CTRL_0.MAX_CSMA_RETRIES \ Maximum Number of CSMA-CA Proc + $1 constant XAH_CTRL_0_SLOTTED_OPERATION \ Set Slotted Acknowledgment + 16c $1 bitmask: XAH_CTRL_0.SLOTTED_OPERATION \ Set Slotted Acknowledgment +$16d constant CSMA_SEED_0 \ Transceiver CSMA-CA Random Num + $80 constant CSMA_SEED_0_CSMA_SEED_07 \ Seed Value for CSMA Random Num + 16d $80 bitmask: CSMA_SEED_0.CSMA_SEED_07 \ Seed Value for CSMA Random Num + $40 constant CSMA_SEED_0_CSMA_SEED_06 \ Seed Value for CSMA Random Num + 16d $40 bitmask: CSMA_SEED_0.CSMA_SEED_06 \ Seed Value for CSMA Random Num + $20 constant CSMA_SEED_0_CSMA_SEED_05 \ Seed Value for CSMA Random Num + 16d $20 bitmask: CSMA_SEED_0.CSMA_SEED_05 \ Seed Value for CSMA Random Num + $10 constant CSMA_SEED_0_CSMA_SEED_04 \ Seed Value for CSMA Random Num + 16d $10 bitmask: CSMA_SEED_0.CSMA_SEED_04 \ Seed Value for CSMA Random Num + $8 constant CSMA_SEED_0_CSMA_SEED_03 \ Seed Value for CSMA Random Num + 16d $8 bitmask: CSMA_SEED_0.CSMA_SEED_03 \ Seed Value for CSMA Random Num + $4 constant CSMA_SEED_0_CSMA_SEED_02 \ Seed Value for CSMA Random Num + 16d $4 bitmask: CSMA_SEED_0.CSMA_SEED_02 \ Seed Value for CSMA Random Num + $2 constant CSMA_SEED_0_CSMA_SEED_01 \ Seed Value for CSMA Random Num + 16d $2 bitmask: CSMA_SEED_0.CSMA_SEED_01 \ Seed Value for CSMA Random Num + $1 constant CSMA_SEED_0_CSMA_SEED_00 \ Seed Value for CSMA Random Num + 16d $1 bitmask: CSMA_SEED_0.CSMA_SEED_00 \ Seed Value for CSMA Random Num +$16e constant CSMA_SEED_1 \ Transceiver Acknowledgment Fra + $c0 constant CSMA_SEED_1_AACK_FVN_MODE \ Acknowledgment Frame Filter Mo + 16e $c0 bitmask: CSMA_SEED_1.AACK_FVN_MODE \ Acknowledgment Frame Filter Mo + $20 constant CSMA_SEED_1_AACK_SET_PD \ Set Frame Pending Sub-field + 16e $20 bitmask: CSMA_SEED_1.AACK_SET_PD \ Set Frame Pending Sub-field + $10 constant CSMA_SEED_1_AACK_DIS_ACK \ Disable Acknowledgment Frame T + 16e $10 bitmask: CSMA_SEED_1.AACK_DIS_ACK \ Disable Acknowledgment Frame T + $8 constant CSMA_SEED_1_AACK_I_AM_COORD \ Set Personal Area Network Coor + 16e $8 bitmask: CSMA_SEED_1.AACK_I_AM_COORD \ Set Personal Area Network Coor + $7 constant CSMA_SEED_1_CSMA_SEED_1 \ Seed Value for CSMA Random Num + 16e $7 bitmask: CSMA_SEED_1.CSMA_SEED_1 \ Seed Value for CSMA Random Num +$16f constant CSMA_BE \ Transceiver CSMA-CA Back-off E + $f0 constant CSMA_BE_MAX_BE \ Maximum Back-off Exponent + 16f $f0 bitmask: CSMA_BE.MAX_BE \ Maximum Back-off Exponent + $f constant CSMA_BE_MIN_BE \ Minimum Back-off Exponent + 16f $f bitmask: CSMA_BE.MIN_BE \ Minimum Back-off Exponent +$176 constant TST_CTRL_DIGI \ Transceiver Digital Test Contr + $f constant TST_CTRL_DIGI_TST_CTRL_DIG \ Digital Test Controller Regist + 176 $f bitmask: TST_CTRL_DIGI.TST_CTRL_DIG \ Digital Test Controller Regist +$17b constant TST_RX_LENGTH \ Transceiver Received Frame Len + $ff constant TST_RX_LENGTH_RX_LENGTH \ Received Frame Length + 17b $ff bitmask: TST_RX_LENGTH.RX_LENGTH \ Received Frame Length +$180 constant TRXFBST \ Start of frame buffer +$1ff constant TRXFBEND \ End of frame buffer +\ SYMCNT +$fc constant SCTSTRHH \ Symbol Counter Transmit Frame + $ff constant SCTSTRHH_SCTSTRHH \ Symbol Counter Transmit Frame + fc $ff bitmask: SCTSTRHH.SCTSTRHH \ Symbol Counter Transmit Frame +$fb constant SCTSTRHL \ Symbol Counter Transmit Frame + $ff constant SCTSTRHL_SCTSTRHL \ Symbol Counter Transmit Frame + fb $ff bitmask: SCTSTRHL.SCTSTRHL \ Symbol Counter Transmit Frame +$fa constant SCTSTRLH \ Symbol Counter Transmit Frame + $ff constant SCTSTRLH_SCTSTRLH \ Symbol Counter Transmit Frame + fa $ff bitmask: SCTSTRLH.SCTSTRLH \ Symbol Counter Transmit Frame +$f9 constant SCTSTRLL \ Symbol Counter Transmit Frame + $ff constant SCTSTRLL_SCTSTRLL \ Symbol Counter Transmit Frame + f9 $ff bitmask: SCTSTRLL.SCTSTRLL \ Symbol Counter Transmit Frame +$f8 constant SCOCR1HH \ Symbol Counter Output Compare + $ff constant SCOCR1HH_SCOCR1HH \ Symbol Counter Output Compare + f8 $ff bitmask: SCOCR1HH.SCOCR1HH \ Symbol Counter Output Compare +$f7 constant SCOCR1HL \ Symbol Counter Output Compare + $ff constant SCOCR1HL_SCOCR1HL \ Symbol Counter Output Compare + f7 $ff bitmask: SCOCR1HL.SCOCR1HL \ Symbol Counter Output Compare +$f6 constant SCOCR1LH \ Symbol Counter Output Compare + $ff constant SCOCR1LH_SCOCR1LH \ Symbol Counter Output Compare + f6 $ff bitmask: SCOCR1LH.SCOCR1LH \ Symbol Counter Output Compare +$f5 constant SCOCR1LL \ Symbol Counter Output Compare + $ff constant SCOCR1LL_SCOCR1LL \ Symbol Counter Output Compare + f5 $ff bitmask: SCOCR1LL.SCOCR1LL \ Symbol Counter Output Compare +$f4 constant SCOCR2HH \ Symbol Counter Output Compare + $ff constant SCOCR2HH_SCOCR2HH \ Symbol Counter Output Compare + f4 $ff bitmask: SCOCR2HH.SCOCR2HH \ Symbol Counter Output Compare +$f3 constant SCOCR2HL \ Symbol Counter Output Compare + $ff constant SCOCR2HL_SCOCR2HL \ Symbol Counter Output Compare + f3 $ff bitmask: SCOCR2HL.SCOCR2HL \ Symbol Counter Output Compare +$f2 constant SCOCR2LH \ Symbol Counter Output Compare + $ff constant SCOCR2LH_SCOCR2LH \ Symbol Counter Output Compare + f2 $ff bitmask: SCOCR2LH.SCOCR2LH \ Symbol Counter Output Compare +$f1 constant SCOCR2LL \ Symbol Counter Output Compare + $ff constant SCOCR2LL_SCOCR2LL \ Symbol Counter Output Compare + f1 $ff bitmask: SCOCR2LL.SCOCR2LL \ Symbol Counter Output Compare +$f0 constant SCOCR3HH \ Symbol Counter Output Compare + $ff constant SCOCR3HH_SCOCR3HH \ Symbol Counter Output Compare + f0 $ff bitmask: SCOCR3HH.SCOCR3HH \ Symbol Counter Output Compare +$ef constant SCOCR3HL \ Symbol Counter Output Compare + $ff constant SCOCR3HL_SCOCR3HL \ Symbol Counter Output Compare + ef $ff bitmask: SCOCR3HL.SCOCR3HL \ Symbol Counter Output Compare +$ee constant SCOCR3LH \ Symbol Counter Output Compare + $ff constant SCOCR3LH_SCOCR3LH \ Symbol Counter Output Compare + ee $ff bitmask: SCOCR3LH.SCOCR3LH \ Symbol Counter Output Compare +$ed constant SCOCR3LL \ Symbol Counter Output Compare + $ff constant SCOCR3LL_SCOCR3LL \ Symbol Counter Output Compare + ed $ff bitmask: SCOCR3LL.SCOCR3LL \ Symbol Counter Output Compare +$ec constant SCTSRHH \ Symbol Counter Frame Timestamp + $ff constant SCTSRHH_SCTSRHH \ Symbol Counter Frame Timestamp + ec $ff bitmask: SCTSRHH.SCTSRHH \ Symbol Counter Frame Timestamp +$eb constant SCTSRHL \ Symbol Counter Frame Timestamp + $ff constant SCTSRHL_SCTSRHL \ Symbol Counter Frame Timestamp + eb $ff bitmask: SCTSRHL.SCTSRHL \ Symbol Counter Frame Timestamp +$ea constant SCTSRLH \ Symbol Counter Frame Timestamp + $ff constant SCTSRLH_SCTSRLH \ Symbol Counter Frame Timestamp + ea $ff bitmask: SCTSRLH.SCTSRLH \ Symbol Counter Frame Timestamp +$e9 constant SCTSRLL \ Symbol Counter Frame Timestamp + $ff constant SCTSRLL_SCTSRLL \ Symbol Counter Frame Timestamp + e9 $ff bitmask: SCTSRLL.SCTSRLL \ Symbol Counter Frame Timestamp +$e8 constant SCBTSRHH \ Symbol Counter Beacon Timestam + $ff constant SCBTSRHH_SCBTSRHH \ Symbol Counter Beacon Timestam + e8 $ff bitmask: SCBTSRHH.SCBTSRHH \ Symbol Counter Beacon Timestam +$e7 constant SCBTSRHL \ Symbol Counter Beacon Timestam + $ff constant SCBTSRHL_SCBTSRHL \ Symbol Counter Beacon Timestam + e7 $ff bitmask: SCBTSRHL.SCBTSRHL \ Symbol Counter Beacon Timestam +$e6 constant SCBTSRLH \ Symbol Counter Beacon Timestam + $ff constant SCBTSRLH_SCBTSRLH \ Symbol Counter Beacon Timestam + e6 $ff bitmask: SCBTSRLH.SCBTSRLH \ Symbol Counter Beacon Timestam +$e5 constant SCBTSRLL \ Symbol Counter Beacon Timestam + $ff constant SCBTSRLL_SCBTSRLL \ Symbol Counter Beacon Timestam + e5 $ff bitmask: SCBTSRLL.SCBTSRLL \ Symbol Counter Beacon Timestam +$e4 constant SCCNTHH \ Symbol Counter Register HH-Byt + $ff constant SCCNTHH_SCCNTHH \ Symbol Counter Register HH-Byt + e4 $ff bitmask: SCCNTHH.SCCNTHH \ Symbol Counter Register HH-Byt +$e3 constant SCCNTHL \ Symbol Counter Register HL-Byt + $ff constant SCCNTHL_SCCNTHL \ Symbol Counter Register HL-Byt + e3 $ff bitmask: SCCNTHL.SCCNTHL \ Symbol Counter Register HL-Byt +$e2 constant SCCNTLH \ Symbol Counter Register LH-Byt + $ff constant SCCNTLH_SCCNTLH \ Symbol Counter Register LH-Byt + e2 $ff bitmask: SCCNTLH.SCCNTLH \ Symbol Counter Register LH-Byt +$e1 constant SCCNTLL \ Symbol Counter Register LL-Byt + $ff constant SCCNTLL_SCCNTLL \ Symbol Counter Register LL-Byt + e1 $ff bitmask: SCCNTLL.SCCNTLL \ Symbol Counter Register LL-Byt +$e0 constant SCIRQS \ Symbol Counter Interrupt Statu + $e0 constant SCIRQS_Res \ Reserved Bit + e0 $e0 bitmask: SCIRQS.Res \ Reserved Bit + $10 constant SCIRQS_IRQSBO \ Backoff Slot Counter IRQ + e0 $10 bitmask: SCIRQS.IRQSBO \ Backoff Slot Counter IRQ + $8 constant SCIRQS_IRQSOF \ Symbol Counter Overflow IRQ + e0 $8 bitmask: SCIRQS.IRQSOF \ Symbol Counter Overflow IRQ + $7 constant SCIRQS_IRQSCP \ Compare Unit 3 Compare Match I + e0 $7 bitmask: SCIRQS.IRQSCP \ Compare Unit 3 Compare Match I +$df constant SCIRQM \ Symbol Counter Interrupt Mask + $e0 constant SCIRQM_Res \ Reserved Bit + df $e0 bitmask: SCIRQM.Res \ Reserved Bit + $10 constant SCIRQM_IRQMBO \ Backoff Slot Counter IRQ enabl + df $10 bitmask: SCIRQM.IRQMBO \ Backoff Slot Counter IRQ enabl + $8 constant SCIRQM_IRQMOF \ Symbol Counter Overflow IRQ en + df $8 bitmask: SCIRQM.IRQMOF \ Symbol Counter Overflow IRQ en + $7 constant SCIRQM_IRQMCP \ Symbol Counter Compare Match 3 + df $7 bitmask: SCIRQM.IRQMCP \ Symbol Counter Compare Match 3 +$de constant SCSR \ Symbol Counter Status Register + $fe constant SCSR_Res \ Reserved Bit + de $fe bitmask: SCSR.Res \ Reserved Bit + $1 constant SCSR_SCBSY \ Symbol Counter busy + de $1 bitmask: SCSR.SCBSY \ Symbol Counter busy +$dd constant SCCR1 \ Symbol Counter Control Registe + $c0 constant SCCR1_Res \ Reserved Bit + dd $c0 bitmask: SCCR1.Res \ Reserved Bit + $20 constant SCCR1_SCBTSM \ Symbol Counter Beacon Timestam + dd $20 bitmask: SCCR1.SCBTSM \ Symbol Counter Beacon Timestam + $1c constant SCCR1_SCCKDIV \ Clock divider for synchronous + dd $1c bitmask: SCCR1.SCCKDIV \ Clock divider for synchronous + $2 constant SCCR1_SCEECLK \ Enable External Clock Source o + dd $2 bitmask: SCCR1.SCEECLK \ Enable External Clock Source o + $1 constant SCCR1_SCENBO \ Backoff Slot Counter enable + dd $1 bitmask: SCCR1.SCENBO \ Backoff Slot Counter enable +$dc constant SCCR0 \ Symbol Counter Control Registe + $80 constant SCCR0_SCRES \ Symbol Counter Synchronization + dc $80 bitmask: SCCR0.SCRES \ Symbol Counter Synchronization + $40 constant SCCR0_SCMBTS \ Manual Beacon Timestamp + dc $40 bitmask: SCCR0.SCMBTS \ Manual Beacon Timestamp + $20 constant SCCR0_SCEN \ Symbol Counter enable + dc $20 bitmask: SCCR0.SCEN \ Symbol Counter enable + $10 constant SCCR0_SCCKSEL \ Symbol Counter Clock Source se + dc $10 bitmask: SCCR0.SCCKSEL \ Symbol Counter Clock Source se + $8 constant SCCR0_SCTSE \ Symbol Counter Automatic Times + dc $8 bitmask: SCCR0.SCTSE \ Symbol Counter Automatic Times + $7 constant SCCR0_SCCMP \ Symbol Counter Compare Unit 3 + dc $7 bitmask: SCCR0.SCCMP \ Symbol Counter Compare Unit 3 +$db constant SCCSR \ Symbol Counter Compare Source + $c0 constant SCCSR_Res \ Reserved Bit + db $c0 bitmask: SCCSR.Res \ Reserved Bit + $30 constant SCCSR_SCCS3 \ Symbol Counter Compare Source + db $30 bitmask: SCCSR.SCCS3 \ Symbol Counter Compare Source + $c constant SCCSR_SCCS2 \ Symbol Counter Compare Source + db $c bitmask: SCCSR.SCCS2 \ Symbol Counter Compare Source + $3 constant SCCSR_SCCS1 \ Symbol Counter Compare Source + db $3 bitmask: SCCSR.SCCS1 \ Symbol Counter Compare Source +$da constant SCRSTRHH \ Symbol Counter Received Frame + $ff constant SCRSTRHH_SCRSTRHH \ Symbol Counter Received Frame + da $ff bitmask: SCRSTRHH.SCRSTRHH \ Symbol Counter Received Frame +$d9 constant SCRSTRHL \ Symbol Counter Received Frame + $ff constant SCRSTRHL_SCRSTRHL \ Symbol Counter Received Frame + d9 $ff bitmask: SCRSTRHL.SCRSTRHL \ Symbol Counter Received Frame +$d8 constant SCRSTRLH \ Symbol Counter Received Frame + $ff constant SCRSTRLH_SCRSTRLH \ Symbol Counter Received Frame + d8 $ff bitmask: SCRSTRLH.SCRSTRLH \ Symbol Counter Received Frame +$d7 constant SCRSTRLL \ Symbol Counter Received Frame + $ff constant SCRSTRLL_SCRSTRLL \ Symbol Counter Received Frame + d7 $ff bitmask: SCRSTRLL.SCRSTRLL \ Symbol Counter Received Frame +\ EEPROM +$41 constant EEAR \ EEPROM Address Register Bytes +$40 constant EEDR \ EEPROM Data Register +$3f constant EECR \ EEPROM Control Register + $c0 constant EECR_Res \ Reserved + 3f $c0 bitmask: EECR.Res \ Reserved + $30 constant EECR_EEPM \ EEPROM Programming Mode + 3f $30 bitmask: EECR.EEPM \ EEPROM Programming Mode + $8 constant EECR_EERIE \ EEPROM Ready Interrupt Enable + 3f $8 bitmask: EECR.EERIE \ EEPROM Ready Interrupt Enable + $4 constant EECR_EEMPE \ EEPROM Master Write Enable + 3f $4 bitmask: EECR.EEMPE \ EEPROM Master Write Enable + $2 constant EECR_EEPE \ EEPROM Programming Enable + 3f $2 bitmask: EECR.EEPE \ EEPROM Programming Enable + $1 constant EECR_EERE \ EEPROM Read Enable + 3f $1 bitmask: EECR.EERE \ EEPROM Read Enable +\ JTAG +$51 constant OCDR \ On-Chip Debug Register + $ff constant OCDR_OCDR \ On-Chip Debug Register Data + 51 $ff bitmask: OCDR.OCDR \ On-Chip Debug Register Data +$55 constant MCUCR \ MCU Control Register + $80 constant MCUCR_JTD \ JTAG Interface Disable + 55 $80 bitmask: MCUCR.JTD \ JTAG Interface Disable +$54 constant MCUSR \ MCU Status Register + $10 constant MCUSR_JTRF \ JTAG Reset Flag + 54 $10 bitmask: MCUSR.JTRF \ JTAG Reset Flag +\ EXTERNAL_INTERRUPT +$69 constant EICRA \ External Interrupt Control Reg + $c0 constant EICRA_ISC3 \ External Interrupt 3 Sense Con + 69 $c0 bitmask: EICRA.ISC3 \ External Interrupt 3 Sense Con + $30 constant EICRA_ISC2 \ External Interrupt 2 Sense Con + 69 $30 bitmask: EICRA.ISC2 \ External Interrupt 2 Sense Con + $c constant EICRA_ISC1 \ External Interrupt 1 Sense Con + 69 $c bitmask: EICRA.ISC1 \ External Interrupt 1 Sense Con + $3 constant EICRA_ISC0 \ External Interrupt 0 Sense Con + 69 $3 bitmask: EICRA.ISC0 \ External Interrupt 0 Sense Con +$6a constant EICRB \ External Interrupt Control Reg + $c0 constant EICRB_ISC7 \ External Interrupt 7 Sense Con + 6a $c0 bitmask: EICRB.ISC7 \ External Interrupt 7 Sense Con + $30 constant EICRB_ISC6 \ External Interrupt 6 Sense Con + 6a $30 bitmask: EICRB.ISC6 \ External Interrupt 6 Sense Con + $c constant EICRB_ISC5 \ External Interrupt 5 Sense Con + 6a $c bitmask: EICRB.ISC5 \ External Interrupt 5 Sense Con + $3 constant EICRB_ISC4 \ External Interrupt 4 Sense Con + 6a $3 bitmask: EICRB.ISC4 \ External Interrupt 4 Sense Con +$3d constant EIMSK \ External Interrupt Mask Regist + $ff constant EIMSK_INT \ External Interrupt Request Ena + 3d $ff bitmask: EIMSK.INT \ External Interrupt Request Ena +$3c constant EIFR \ External Interrupt Flag Regist + $ff constant EIFR_INTF \ External Interrupt Flag + 3c $ff bitmask: EIFR.INTF \ External Interrupt Flag +$6d constant PCMSK2 \ Pin Change Mask Register 2 + $ff constant PCMSK2_PCINT \ Pin Change Enable Mask + 6d $ff bitmask: PCMSK2.PCINT \ Pin Change Enable Mask +$6c constant PCMSK1 \ Pin Change Mask Register 1 + $ff constant PCMSK1_PCINT \ Pin Change Enable Mask + 6c $ff bitmask: PCMSK1.PCINT \ Pin Change Enable Mask +$6b constant PCMSK0 \ Pin Change Mask Register 0 +$3b constant PCIFR \ Pin Change Interrupt Flag Regi + $f8 constant PCIFR_Res \ Reserved Bit + 3b $f8 bitmask: PCIFR.Res \ Reserved Bit + $7 constant PCIFR_PCIF \ Pin Change Interrupt Flags + 3b $7 bitmask: PCIFR.PCIF \ Pin Change Interrupt Flags +$68 constant PCICR \ Pin Change Interrupt Control R + $f8 constant PCICR_Res \ Reserved Bit + 68 $f8 bitmask: PCICR.Res \ Reserved Bit + $7 constant PCICR_PCIE \ Pin Change Interrupt Enables + 68 $7 bitmask: PCICR.PCIE \ Pin Change Interrupt Enables +\ AD_CONVERTER +$7c constant ADMUX \ The ADC Multiplexer Selection + $c0 constant ADMUX_REFS \ Reference Selection Bits + 7c $c0 bitmask: ADMUX.REFS \ Reference Selection Bits + $20 constant ADMUX_ADLAR \ ADC Left Adjust Result + 7c $20 bitmask: ADMUX.ADLAR \ ADC Left Adjust Result + $1f constant ADMUX_MUX \ Analog Channel and Gain Select + 7c $1f bitmask: ADMUX.MUX \ Analog Channel and Gain Select +$78 constant ADC \ ADC Data Register Bytes +$7a constant ADCSRA \ The ADC Control and Status Reg + $80 constant ADCSRA_ADEN \ ADC Enable + 7a $80 bitmask: ADCSRA.ADEN \ ADC Enable + $40 constant ADCSRA_ADSC \ ADC Start Conversion + 7a $40 bitmask: ADCSRA.ADSC \ ADC Start Conversion + $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable + 7a $20 bitmask: ADCSRA.ADATE \ ADC Auto Trigger Enable + $10 constant ADCSRA_ADIF \ ADC Interrupt Flag + 7a $10 bitmask: ADCSRA.ADIF \ ADC Interrupt Flag + $8 constant ADCSRA_ADIE \ ADC Interrupt Enable + 7a $8 bitmask: ADCSRA.ADIE \ ADC Interrupt Enable + $7 constant ADCSRA_ADPS \ ADC Prescaler Select Bits + 7a $7 bitmask: ADCSRA.ADPS \ ADC Prescaler Select Bits +$7b constant ADCSRB \ The ADC Control and Status Reg + $80 constant ADCSRB_AVDDOK \ AVDD Supply Voltage OK + 7b $80 bitmask: ADCSRB.AVDDOK \ AVDD Supply Voltage OK + $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer + 7b $40 bitmask: ADCSRB.ACME \ Analog Comparator Multiplexer + $20 constant ADCSRB_REFOK \ Reference Voltage OK + 7b $20 bitmask: ADCSRB.REFOK \ Reference Voltage OK + $10 constant ADCSRB_ACCH \ Analog Channel Change + 7b $10 bitmask: ADCSRB.ACCH \ Analog Channel Change + $8 constant ADCSRB_MUX5 \ Analog Channel and Gain Select + 7b $8 bitmask: ADCSRB.MUX5 \ Analog Channel and Gain Select + $7 constant ADCSRB_ADTS \ ADC Auto Trigger Source + 7b $7 bitmask: ADCSRB.ADTS \ ADC Auto Trigger Source +$77 constant ADCSRC \ The ADC Control and Status Reg + $c0 constant ADCSRC_ADTHT \ ADC Track-and-Hold Time + 77 $c0 bitmask: ADCSRC.ADTHT \ ADC Track-and-Hold Time + $20 constant ADCSRC_Res0 \ Reserved + 77 $20 bitmask: ADCSRC.Res0 \ Reserved + $1f constant ADCSRC_ADSUT \ ADC Start-up Time + 77 $1f bitmask: ADCSRC.ADSUT \ ADC Start-up Time +$7d constant DIDR2 \ Digital Input Disable Register + $80 constant DIDR2_ADC15D \ Reserved Bits + 7d $80 bitmask: DIDR2.ADC15D \ Reserved Bits + $40 constant DIDR2_ADC14D \ Reserved Bits + 7d $40 bitmask: DIDR2.ADC14D \ Reserved Bits + $20 constant DIDR2_ADC13D \ Reserved Bits + 7d $20 bitmask: DIDR2.ADC13D \ Reserved Bits + $10 constant DIDR2_ADC12D \ Reserved Bits + 7d $10 bitmask: DIDR2.ADC12D \ Reserved Bits + $8 constant DIDR2_ADC11D \ Reserved Bits + 7d $8 bitmask: DIDR2.ADC11D \ Reserved Bits + $4 constant DIDR2_ADC10D \ Reserved Bits + 7d $4 bitmask: DIDR2.ADC10D \ Reserved Bits + $2 constant DIDR2_ADC9D \ Reserved Bits + 7d $2 bitmask: DIDR2.ADC9D \ Reserved Bits + $1 constant DIDR2_ADC8D \ Reserved Bits + 7d $1 bitmask: DIDR2.ADC8D \ Reserved Bits +$7e constant DIDR0 \ Digital Input Disable Register + $80 constant DIDR0_ADC7D \ Disable ADC7:0 Digital Input + 7e $80 bitmask: DIDR0.ADC7D \ Disable ADC7:0 Digital Input + $40 constant DIDR0_ADC6D \ Disable ADC7:0 Digital Input + 7e $40 bitmask: DIDR0.ADC6D \ Disable ADC7:0 Digital Input + $20 constant DIDR0_ADC5D \ Disable ADC7:0 Digital Input + 7e $20 bitmask: DIDR0.ADC5D \ Disable ADC7:0 Digital Input + $10 constant DIDR0_ADC4D \ Disable ADC7:0 Digital Input + 7e $10 bitmask: DIDR0.ADC4D \ Disable ADC7:0 Digital Input + $8 constant DIDR0_ADC3D \ Disable ADC7:0 Digital Input + 7e $8 bitmask: DIDR0.ADC3D \ Disable ADC7:0 Digital Input + $4 constant DIDR0_ADC2D \ Disable ADC7:0 Digital Input + 7e $4 bitmask: DIDR0.ADC2D \ Disable ADC7:0 Digital Input + $2 constant DIDR0_ADC1D \ Disable ADC7:0 Digital Input + 7e $2 bitmask: DIDR0.ADC1D \ Disable ADC7:0 Digital Input + $1 constant DIDR0_ADC0D \ Disable ADC7:0 Digital Input + 7e $1 bitmask: DIDR0.ADC0D \ Disable ADC7:0 Digital Input +\ BOOT_LOAD +$57 constant SPMCSR \ Store Program Memory Control R + $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable + 57 $80 bitmask: SPMCSR.SPMIE \ SPM Interrupt Enable + $40 constant SPMCSR_RWWSB \ Read While Write Section Busy + 57 $40 bitmask: SPMCSR.RWWSB \ Read While Write Section Busy + $20 constant SPMCSR_SIGRD \ Signature Row Read + 57 $20 bitmask: SPMCSR.SIGRD \ Signature Row Read + $10 constant SPMCSR_RWWSRE \ Read While Write Section Read + 57 $10 bitmask: SPMCSR.RWWSRE \ Read While Write Section Read + $8 constant SPMCSR_BLBSET \ Boot Lock Bit Set + 57 $8 bitmask: SPMCSR.BLBSET \ Boot Lock Bit Set + $4 constant SPMCSR_PGWRT \ Page Write + 57 $4 bitmask: SPMCSR.PGWRT \ Page Write + $2 constant SPMCSR_PGERS \ Page Erase + 57 $2 bitmask: SPMCSR.PGERS \ Page Erase + $1 constant SPMCSR_SPMEN \ Store Program Memory Enable + 57 $1 bitmask: SPMCSR.SPMEN \ Store Program Memory Enable +\ CPU +$5f constant SREG \ Status Register + $80 constant SREG_I \ Global Interrupt Enable + 5f $80 bitmask: SREG.I \ Global Interrupt Enable + $40 constant SREG_T \ Bit Copy Storage + 5f $40 bitmask: SREG.T \ Bit Copy Storage + $20 constant SREG_H \ Half Carry Flag + 5f $20 bitmask: SREG.H \ Half Carry Flag + $10 constant SREG_S \ Sign Bit + 5f $10 bitmask: SREG.S \ Sign Bit + $8 constant SREG_V \ Two's Complement Overflow Flag + 5f $8 bitmask: SREG.V \ Two's Complement Overflow Flag + $4 constant SREG_N \ Negative Flag + 5f $4 bitmask: SREG.N \ Negative Flag + $2 constant SREG_Z \ Zero Flag + 5f $2 bitmask: SREG.Z \ Zero Flag + $1 constant SREG_C \ Carry Flag + 5f $1 bitmask: SREG.C \ Carry Flag +$5d constant SP \ Stack Pointer +$55 constant MCUCR \ MCU Control Register + $80 constant MCUCR_JTD \ JTAG Interface Disable + 55 $80 bitmask: MCUCR.JTD \ JTAG Interface Disable + $60 constant MCUCR_Res \ Reserved + 55 $60 bitmask: MCUCR.Res \ Reserved + $10 constant MCUCR_PUD \ Pull-up Disable + 55 $10 bitmask: MCUCR.PUD \ Pull-up Disable + $c constant MCUCR_Res \ Reserved + 55 $c bitmask: MCUCR.Res \ Reserved + $2 constant MCUCR_IVSEL \ Interrupt Vector Select + 55 $2 bitmask: MCUCR.IVSEL \ Interrupt Vector Select + $1 constant MCUCR_IVCE \ Interrupt Vector Change Enable + 55 $1 bitmask: MCUCR.IVCE \ Interrupt Vector Change Enable +$54 constant MCUSR \ MCU Status Register + $e0 constant MCUSR_Res \ Reserved + 54 $e0 bitmask: MCUSR.Res \ Reserved + $10 constant MCUSR_JTRF \ JTAG Reset Flag + 54 $10 bitmask: MCUSR.JTRF \ JTAG Reset Flag + $8 constant MCUSR_WDRF \ Watchdog Reset Flag + 54 $8 bitmask: MCUSR.WDRF \ Watchdog Reset Flag + $4 constant MCUSR_BORF \ Brown-out Reset Flag + 54 $4 bitmask: MCUSR.BORF \ Brown-out Reset Flag + $2 constant MCUSR_EXTRF \ External Reset Flag + 54 $2 bitmask: MCUSR.EXTRF \ External Reset Flag + $1 constant MCUSR_PORF \ Power-on Reset Flag + 54 $1 bitmask: MCUSR.PORF \ Power-on Reset Flag +$66 constant OSCCAL \ Oscillator Calibration Value + $ff constant OSCCAL_CAL \ Oscillator Calibration Tuning + 66 $ff bitmask: OSCCAL.CAL \ Oscillator Calibration Tuning +$61 constant CLKPR \ Clock Prescale Register + $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable + 61 $80 bitmask: CLKPR.CLKPCE \ Clock Prescaler Change Enable + $70 constant CLKPR_Res \ Reserved + 61 $70 bitmask: CLKPR.Res \ Reserved + $f constant CLKPR_CLKPS \ Clock Prescaler Select Bits + 61 $f bitmask: CLKPR.CLKPS \ Clock Prescaler Select Bits +$53 constant SMCR \ Sleep Mode Control Register + $f0 constant SMCR_Res \ Reserved + 53 $f0 bitmask: SMCR.Res \ Reserved + $e constant SMCR_SM \ Sleep Mode Select bits + 53 $e bitmask: SMCR.SM \ Sleep Mode Select bits + $1 constant SMCR_SE \ Sleep Enable + 53 $1 bitmask: SMCR.SE \ Sleep Enable +$5c constant EIND \ Extended Indirect Register +$5b constant RAMPZ \ Extended Z-pointer Register fo + $fc constant RAMPZ_Res \ Reserved + 5b $fc bitmask: RAMPZ.Res \ Reserved + $3 constant RAMPZ_RAMPZ \ Extended Z-Pointer Value + 5b $3 bitmask: RAMPZ.RAMPZ \ Extended Z-Pointer Value +$4b constant GPIOR2 \ General Purpose I/O Register 2 + $ff constant GPIOR2_GPIOR \ General Purpose I/O Register 2 + 4b $ff bitmask: GPIOR2.GPIOR \ General Purpose I/O Register 2 +$4a constant GPIOR1 \ General Purpose IO Register 1 + $ff constant GPIOR1_GPIOR \ General Purpose I/O Register 1 + 4a $ff bitmask: GPIOR1.GPIOR \ General Purpose I/O Register 1 +$3e constant GPIOR0 \ General Purpose IO Register 0 + $80 constant GPIOR0_GPIOR07 \ General Purpose I/O Register 0 + 3e $80 bitmask: GPIOR0.GPIOR07 \ General Purpose I/O Register 0 + $40 constant GPIOR0_GPIOR06 \ General Purpose I/O Register 0 + 3e $40 bitmask: GPIOR0.GPIOR06 \ General Purpose I/O Register 0 + $20 constant GPIOR0_GPIOR05 \ General Purpose I/O Register 0 + 3e $20 bitmask: GPIOR0.GPIOR05 \ General Purpose I/O Register 0 + $10 constant GPIOR0_GPIOR04 \ General Purpose I/O Register 0 + 3e $10 bitmask: GPIOR0.GPIOR04 \ General Purpose I/O Register 0 + $8 constant GPIOR0_GPIOR03 \ General Purpose I/O Register 0 + 3e $8 bitmask: GPIOR0.GPIOR03 \ General Purpose I/O Register 0 + $4 constant GPIOR0_GPIOR02 \ General Purpose I/O Register 0 + 3e $4 bitmask: GPIOR0.GPIOR02 \ General Purpose I/O Register 0 + $2 constant GPIOR0_GPIOR01 \ General Purpose I/O Register 0 + 3e $2 bitmask: GPIOR0.GPIOR01 \ General Purpose I/O Register 0 + $1 constant GPIOR0_GPIOR00 \ General Purpose I/O Register 0 + 3e $1 bitmask: GPIOR0.GPIOR00 \ General Purpose I/O Register 0 +$63 constant PRR2 \ Power Reduction Register 2 + $f0 constant PRR2_Res \ Reserved Bit + 63 $f0 bitmask: PRR2.Res \ Reserved Bit + $f constant PRR2_PRRAM \ Power Reduction SRAMs + 63 $f bitmask: PRR2.PRRAM \ Power Reduction SRAMs +$65 constant PRR1 \ Power Reduction Register 1 + $80 constant PRR1_Res \ Reserved Bit + 65 $80 bitmask: PRR1.Res \ Reserved Bit + $40 constant PRR1_PRTRX24 \ Power Reduction Transceiver + 65 $40 bitmask: PRR1.PRTRX24 \ Power Reduction Transceiver + $20 constant PRR1_PRTIM5 \ Power Reduction Timer/Counter5 + 65 $20 bitmask: PRR1.PRTIM5 \ Power Reduction Timer/Counter5 + $10 constant PRR1_PRTIM4 \ Power Reduction Timer/Counter4 + 65 $10 bitmask: PRR1.PRTIM4 \ Power Reduction Timer/Counter4 + $8 constant PRR1_PRTIM3 \ Power Reduction Timer/Counter3 + 65 $8 bitmask: PRR1.PRTIM3 \ Power Reduction Timer/Counter3 + $1 constant PRR1_PRUSART1 \ Power Reduction USART1 + 65 $1 bitmask: PRR1.PRUSART1 \ Power Reduction USART1 +$64 constant PRR0 \ Power Reduction Register0 + $80 constant PRR0_PRTWI \ Power Reduction TWI + 64 $80 bitmask: PRR0.PRTWI \ Power Reduction TWI + $40 constant PRR0_PRTIM2 \ Power Reduction Timer/Counter2 + 64 $40 bitmask: PRR0.PRTIM2 \ Power Reduction Timer/Counter2 + $20 constant PRR0_PRTIM0 \ Power Reduction Timer/Counter0 + 64 $20 bitmask: PRR0.PRTIM0 \ Power Reduction Timer/Counter0 + $10 constant PRR0_PRPGA \ Power Reduction PGA + 64 $10 bitmask: PRR0.PRPGA \ Power Reduction PGA + $8 constant PRR0_PRTIM1 \ Power Reduction Timer/Counter1 + 64 $8 bitmask: PRR0.PRTIM1 \ Power Reduction Timer/Counter1 + $4 constant PRR0_PRSPI \ Power Reduction Serial Periphe + 64 $4 bitmask: PRR0.PRSPI \ Power Reduction Serial Periphe + $2 constant PRR0_PRUSART0 \ Power Reduction USART + 64 $2 bitmask: PRR0.PRUSART0 \ Power Reduction USART + $1 constant PRR0_PRADC \ Power Reduction ADC + 64 $1 bitmask: PRR0.PRADC \ Power Reduction ADC +\ FLASH +$75 constant NEMCR \ Flash Extended-Mode Control-Re + $40 constant NEMCR_ENEAM \ Enable Extended Address Mode f + 75 $40 bitmask: NEMCR.ENEAM \ Enable Extended Address Mode f + $30 constant NEMCR_AEAM \ Address for Extended Address M + 75 $30 bitmask: NEMCR.AEAM \ Address for Extended Address M +$67 constant BGCR \ Reference Voltage Calibration + $80 constant BGCR_Res \ Reserved Bit + 67 $80 bitmask: BGCR.Res \ Reserved Bit + $78 constant BGCR_BGCAL_FINE \ Fine Calibration Bits + 67 $78 bitmask: BGCR.BGCAL_FINE \ Fine Calibration Bits + $7 constant BGCR_BGCAL \ Coarse Calibration Bits + 67 $7 bitmask: BGCR.BGCAL \ Coarse Calibration Bits +\ PWRCTRL +$139 constant TRXPR \ Transceiver Pin Register + $f0 constant TRXPR_Res \ Reserved + 139 $f0 bitmask: TRXPR.Res \ Reserved + $2 constant TRXPR_SLPTR \ Multi-purpose Transceiver Cont + 139 $2 bitmask: TRXPR.SLPTR \ Multi-purpose Transceiver Cont + $1 constant TRXPR_TRXRST \ Force Transceiver Reset + 139 $1 bitmask: TRXPR.TRXRST \ Force Transceiver Reset +$135 constant DRTRAM0 \ Data Retention Configuration R + $c0 constant DRTRAM0_Res \ Reserved + 135 $c0 bitmask: DRTRAM0.Res \ Reserved + $20 constant DRTRAM0_DRTSWOK \ DRT Switch OK + 135 $20 bitmask: DRTRAM0.DRTSWOK \ DRT Switch OK + $10 constant DRTRAM0_ENDRT \ Enable SRAM Data Retention + 135 $10 bitmask: DRTRAM0.ENDRT \ Enable SRAM Data Retention +$134 constant DRTRAM1 \ Data Retention Configuration R + $c0 constant DRTRAM1_Res \ Reserved + 134 $c0 bitmask: DRTRAM1.Res \ Reserved + $20 constant DRTRAM1_DRTSWOK \ DRT Switch OK + 134 $20 bitmask: DRTRAM1.DRTSWOK \ DRT Switch OK + $10 constant DRTRAM1_ENDRT \ Enable SRAM Data Retention + 134 $10 bitmask: DRTRAM1.ENDRT \ Enable SRAM Data Retention +$133 constant DRTRAM2 \ Data Retention Configuration R + $40 constant DRTRAM2_Res \ Reserved Bit + 133 $40 bitmask: DRTRAM2.Res \ Reserved Bit + $20 constant DRTRAM2_DRTSWOK \ DRT Switch OK + 133 $20 bitmask: DRTRAM2.DRTSWOK \ DRT Switch OK + $10 constant DRTRAM2_ENDRT \ Enable SRAM Data Retention + 133 $10 bitmask: DRTRAM2.ENDRT \ Enable SRAM Data Retention +$132 constant DRTRAM3 \ Data Retention Configuration R + $c0 constant DRTRAM3_Res \ Reserved + 132 $c0 bitmask: DRTRAM3.Res \ Reserved + $20 constant DRTRAM3_DRTSWOK \ DRT Switch OK + 132 $20 bitmask: DRTRAM3.DRTSWOK \ DRT Switch OK + $10 constant DRTRAM3_ENDRT \ Enable SRAM Data Retention + 132 $10 bitmask: DRTRAM3.ENDRT \ Enable SRAM Data Retention +$130 constant LLDRL \ Low Leakage Voltage Regulator + $f0 constant LLDRL_Res \ Reserved + 130 $f0 bitmask: LLDRL.Res \ Reserved + $f constant LLDRL_LLDRL \ Low-Byte Data Register Bits + 130 $f bitmask: LLDRL.LLDRL \ Low-Byte Data Register Bits +$131 constant LLDRH \ Low Leakage Voltage Regulator + $e0 constant LLDRH_Res \ Reserved + 131 $e0 bitmask: LLDRH.Res \ Reserved + $1f constant LLDRH_LLDRH \ High-Byte Data Register Bits + 131 $1f bitmask: LLDRH.LLDRH \ High-Byte Data Register Bits +$12f constant LLCR \ Low Leakage Voltage Regulator + $c0 constant LLCR_Res \ Reserved Bit + 12f $c0 bitmask: LLCR.Res \ Reserved Bit + $20 constant LLCR_LLDONE \ Calibration Done + 12f $20 bitmask: LLCR.LLDONE \ Calibration Done + $10 constant LLCR_LLCOMP \ Comparator Output + 12f $10 bitmask: LLCR.LLCOMP \ Comparator Output + $8 constant LLCR_LLCAL \ Calibration Active + 12f $8 bitmask: LLCR.LLCAL \ Calibration Active + $4 constant LLCR_LLTCO \ Temperature Coefficient of Cur + 12f $4 bitmask: LLCR.LLTCO \ Temperature Coefficient of Cur + $2 constant LLCR_LLSHORT \ Short Lower Calibration Circui + 12f $2 bitmask: LLCR.LLSHORT \ Short Lower Calibration Circui + $1 constant LLCR_LLENCAL \ Enable Automatic Calibration + 12f $1 bitmask: LLCR.LLENCAL \ Enable Automatic Calibration +$136 constant DPDS0 \ Port Driver Strength Register + $c0 constant DPDS0_PFDRV \ Driver Strength Port F + 136 $c0 bitmask: DPDS0.PFDRV \ Driver Strength Port F + $30 constant DPDS0_PEDRV \ Driver Strength Port E + 136 $30 bitmask: DPDS0.PEDRV \ Driver Strength Port E + $c constant DPDS0_PDDRV \ Driver Strength Port D + 136 $c bitmask: DPDS0.PDDRV \ Driver Strength Port D + $3 constant DPDS0_PBDRV \ Driver Strength Port B + 136 $3 bitmask: DPDS0.PBDRV \ Driver Strength Port B +$137 constant DPDS1 \ Port Driver Strength Register + $fc constant DPDS1_Res \ Reserved + 137 $fc bitmask: DPDS1.Res \ Reserved + $3 constant DPDS1_PGDRV \ Driver Strength Port G + 137 $3 bitmask: DPDS1.PGDRV \ Driver Strength Port G +$55 constant MCUCR \ MCU Control Register + $10 constant MCUCR_PUD \ Pull-up Disable + 55 $10 bitmask: MCUCR.PUD \ Pull-up Disable +\ USART0_SPI +$c0 constant UCSR0A \ USART0 MSPIM Control and Statu + $80 constant UCSR0A_RXC0 \ USART Receive Complete + c0 $80 bitmask: UCSR0A.RXC0 \ USART Receive Complete + $40 constant UCSR0A_TXC0 \ USART Transmit Complete + c0 $40 bitmask: UCSR0A.TXC0 \ USART Transmit Complete + $20 constant UCSR0A_UDRE0 \ USART Data Register Empty + c0 $20 bitmask: UCSR0A.UDRE0 \ USART Data Register Empty +$c1 constant UCSR0B \ USART0 MSPIM Control and Statu + $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable + c1 $80 bitmask: UCSR0B.RXCIE0 \ RX Complete Interrupt Enable + $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable + c1 $40 bitmask: UCSR0B.TXCIE0 \ TX Complete Interrupt Enable + $20 constant UCSR0B_UDRIE0 \ USART Data Register Empty Inte + c1 $20 bitmask: UCSR0B.UDRIE0 \ USART Data Register Empty Inte + $10 constant UCSR0B_RXEN0 \ Receiver Enable + c1 $10 bitmask: UCSR0B.RXEN0 \ Receiver Enable + $8 constant UCSR0B_TXEN0 \ Transmitter Enable + c1 $8 bitmask: UCSR0B.TXEN0 \ Transmitter Enable +$c2 constant UCSR0C \ USART0 MSPIM Control and Statu + $4 constant UCSR0C_UDORD0 \ Data Order + c2 $4 bitmask: UCSR0C.UDORD0 \ Data Order + $2 constant UCSR0C_UCPHA0 \ Clock Phase + c2 $2 bitmask: UCSR0C.UCPHA0 \ Clock Phase + $1 constant UCSR0C_UCPOL0 \ Clock Polarity + c2 $1 bitmask: UCSR0C.UCPOL0 \ Clock Polarity +\ USART1_SPI +$c8 constant UCSR1A \ USART1 MSPIM Control and Statu + $80 constant UCSR1A_RXC1 \ USART Receive Complete + c8 $80 bitmask: UCSR1A.RXC1 \ USART Receive Complete + $40 constant UCSR1A_TXC1 \ USART Transmit Complete + c8 $40 bitmask: UCSR1A.TXC1 \ USART Transmit Complete + $20 constant UCSR1A_UDRE1 \ USART Data Register Empty + c8 $20 bitmask: UCSR1A.UDRE1 \ USART Data Register Empty +$c9 constant UCSR1B \ USART1 MSPIM Control and Statu + $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable + c9 $80 bitmask: UCSR1B.RXCIE1 \ RX Complete Interrupt Enable + $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable + c9 $40 bitmask: UCSR1B.TXCIE1 \ TX Complete Interrupt Enable + $20 constant UCSR1B_UDRIE1 \ USART Data Register Empty Inte + c9 $20 bitmask: UCSR1B.UDRIE1 \ USART Data Register Empty Inte + $10 constant UCSR1B_RXEN1 \ Receiver Enable + c9 $10 bitmask: UCSR1B.RXEN1 \ Receiver Enable + $8 constant UCSR1B_TXEN1 \ Transmitter Enable + c9 $8 bitmask: UCSR1B.TXEN1 \ Transmitter Enable +$ca constant UCSR1C \ USART1 MSPIM Control and Statu + $4 constant UCSR1C_UDORD1 \ Data Order + ca $4 bitmask: UCSR1C.UDORD1 \ Data Order + $2 constant UCSR1C_UCPHA1 \ Clock Phase + ca $2 bitmask: UCSR1C.UCPHA1 \ Clock Phase + $1 constant UCSR1C_UCPOL1 \ Clock Polarity + ca $1 bitmask: UCSR1C.UCPOL1 \ Clock Polarity diff --git a/amforth-6.5/avr8/devices/atmega256rfr2/device.py b/amforth-6.5/avr8/devices/atmega256rfr2/device.py new file mode 100644 index 0000000..14b2cdc --- /dev/null +++ b/amforth-6.5/avr8/devices/atmega256rfr2/device.py @@ -0,0 +1,1104 @@ +# Generated Automatically + +# Partname ATmega256RFR2 + +MCUREGS = { +# Interrupt Vectors + 'INT0Addr' : '#2', # External Interrupt Request 0 + 'INT1Addr' : '#4', # External Interrupt Request 1 + 'INT2Addr' : '#6', # External Interrupt Request 2 + 'INT3Addr' : '#8', # External Interrupt Request 3 + 'INT4Addr' : '#10', # External Interrupt Request 4 + 'INT5Addr' : '#12', # External Interrupt Request 5 + 'INT6Addr' : '#14', # External Interrupt Request 6 + 'INT7Addr' : '#16', # External Interrupt Request 7 + 'PCINT0Addr' : '#18', # Pin Change Interrupt Request 0 + 'PCINT1Addr' : '#20', # Pin Change Interrupt Request 1 + 'PCINT2Addr' : '#22', # Pin Change Interrupt Request 2 + 'WDTAddr' : '#24', # Watchdog Time-out Interrupt + 'TIMER2_COMPAAddr' : '#26', # Timer/Counter2 Compare Match A + 'TIMER2_COMPBAddr' : '#28', # Timer/Counter2 Compare Match B + 'TIMER2_OVFAddr' : '#30', # Timer/Counter2 Overflow + 'TIMER1_CAPTAddr' : '#32', # Timer/Counter1 Capture Event + 'TIMER1_COMPAAddr' : '#34', # Timer/Counter1 Compare Match A + 'TIMER1_COMPBAddr' : '#36', # Timer/Counter1 Compare Match B + 'TIMER1_COMPCAddr' : '#38', # Timer/Counter1 Compare Match C + 'TIMER1_OVFAddr' : '#40', # Timer/Counter1 Overflow + 'TIMER0_COMPAAddr' : '#42', # Timer/Counter0 Compare Match A + 'TIMER0_COMPBAddr' : '#44', # Timer/Counter0 Compare Match B + 'TIMER0_OVFAddr' : '#46', # Timer/Counter0 Overflow + 'SPI_STCAddr' : '#48', # SPI Serial Transfer Complete + 'USART0_RXAddr' : '#50', # USART0, Rx Complete + 'USART0_UDREAddr' : '#52', # USART0 Data register Empty + 'USART0_TXAddr' : '#54', # USART0, Tx Complete + 'ANALOG_COMPAddr' : '#56', # Analog Comparator + 'ADCAddr' : '#58', # ADC Conversion Complete + 'EE_READYAddr' : '#60', # EEPROM Ready + 'TIMER3_CAPTAddr' : '#62', # Timer/Counter3 Capture Event + 'TIMER3_COMPAAddr' : '#64', # Timer/Counter3 Compare Match A + 'TIMER3_COMPBAddr' : '#66', # Timer/Counter3 Compare Match B + 'TIMER3_COMPCAddr' : '#68', # Timer/Counter3 Compare Match C + 'TIMER3_OVFAddr' : '#70', # Timer/Counter3 Overflow + 'USART1_RXAddr' : '#72', # USART1, Rx Complete + 'USART1_UDREAddr' : '#74', # USART1 Data register Empty + 'USART1_TXAddr' : '#76', # USART1, Tx Complete + 'TWIAddr' : '#78', # 2-wire Serial Interface + 'SPM_READYAddr' : '#80', # Store Program Memory Read + 'TIMER4_CAPTAddr' : '#82', # Timer/Counter4 Capture Event + 'TIMER4_COMPAAddr' : '#84', # Timer/Counter4 Compare Match A + 'TIMER4_COMPBAddr' : '#86', # Timer/Counter4 Compare Match B + 'TIMER4_COMPCAddr' : '#88', # Timer/Counter4 Compare Match C + 'TIMER4_OVFAddr' : '#90', # Timer/Counter4 Overflow + 'TIMER5_CAPTAddr' : '#92', # Timer/Counter5 Capture Event + 'TIMER5_COMPAAddr' : '#94', # Timer/Counter5 Compare Match A + 'TIMER5_COMPBAddr' : '#96', # Timer/Counter5 Compare Match B + 'TIMER5_COMPCAddr' : '#98', # Timer/Counter5 Compare Match C + 'TIMER5_OVFAddr' : '#100', # Timer/Counter5 Overflow + 'USART2_RXAddr' : '#102', # USART2, Rx Complete + 'USART2_UDREAddr' : '#104', # USART2 Data register Empty + 'USART2_TXAddr' : '#106', # USART2, Tx Complete + 'USART3_RXAddr' : '#108', # USART3, Rx Complete + 'USART3_UDREAddr' : '#110', # USART3 Data register Empty + 'USART3_TXAddr' : '#112', # USART3, Tx Complete + 'TRX24_PLL_LOCKAddr' : '#114', # TRX24 - PLL lock interrupt + 'TRX24_PLL_UNLOCKAddr' : '#116', # TRX24 - PLL unlock interrupt + 'TRX24_RX_STARTAddr' : '#118', # TRX24 - Receive start interrupt + 'TRX24_RX_ENDAddr' : '#120', # TRX24 - RX_END interrupt + 'TRX24_CCA_ED_DONEAddr' : '#122', # TRX24 - CCA/ED done interrupt + 'TRX24_XAH_AMIAddr' : '#124', # TRX24 - XAH - AMI + 'TRX24_TX_ENDAddr' : '#126', # TRX24 - TX_END interrupt + 'TRX24_AWAKEAddr' : '#128', # TRX24 AWAKE - tranceiver is reaching state TRX_OFF + 'SCNT_CMP1Addr' : '#130', # Symbol counter - compare match 1 interrupt + 'SCNT_CMP2Addr' : '#132', # Symbol counter - compare match 2 interrupt + 'SCNT_CMP3Addr' : '#134', # Symbol counter - compare match 3 interrupt + 'SCNT_OVFLAddr' : '#136', # Symbol counter - overflow interrupt + 'SCNT_BACKOFFAddr' : '#138', # Symbol counter - backoff interrupt + 'AES_READYAddr' : '#140', # AES engine ready interrupt + 'BAT_LOWAddr' : '#142', # Battery monitor indicates supply voltage below threshold + 'TRX24_TX_STARTAddr' : '#144', # TRX24 TX start interrupt + 'TRX24_AMI0Addr' : '#146', # Address match interrupt of address filter 0 + 'TRX24_AMI1Addr' : '#148', # Address match interrupt of address filter 1 + 'TRX24_AMI2Addr' : '#150', # Address match interrupt of address filter 2 + 'TRX24_AMI3Addr' : '#152', # Address match interrupt of address filter 3 + +# Module ANALOG_COMPARATOR + 'ADCSRB' : '$7b', # ADC Control and Status Registe + 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer + 'ACSR' : '$50', # Analog Comparator Control And + 'ACSR_ACD': '$80', # Analog Comparator Disable + 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele + 'ACSR_ACO': '$20', # Analog Compare Output + 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl + 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En + 'ACSR_ACIC': '$4', # Analog Comparator Input Captur + 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo + 'DIDR1' : '$7f', # Digital Input Disable Register + 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable + 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable + +# Module USART0 + 'UDR0' : '$c6', # USART0 I/O Data Register + 'UCSR0A' : '$c0', # USART0 Control and Status Regi + 'UCSR0A_RXC0': '$80', # USART Receive Complete + 'UCSR0A_TXC0': '$40', # USART Transmit Complete + 'UCSR0A_UDRE0': '$20', # USART Data Register Empty + 'UCSR0A_FE0': '$10', # Frame Error + 'UCSR0A_DOR0': '$8', # Data OverRun + 'UCSR0A_UPE0': '$4', # USART Parity Error + 'UCSR0A_U2X0': '$2', # Double the USART Transmission + 'UCSR0A_MPCM0': '$1', # Multi-processor Communication + 'UCSR0B' : '$c1', # USART0 Control and Status Regi + 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable + 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable + 'UCSR0B_UDRIE0': '$20', # USART Data Register Empty Inte + 'UCSR0B_RXEN0': '$10', # Receiver Enable + 'UCSR0B_TXEN0': '$8', # Transmitter Enable + 'UCSR0B_UCSZ02': '$4', # Character Size + 'UCSR0B_RXB80': '$2', # Receive Data Bit 8 + 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8 + 'UCSR0C' : '$c2', # USART0 Control and Status Regi + 'UCSR0C_UMSEL0': '$c0', # USART Mode Select + 'UCSR0C_UPM0': '$30', # Parity Mode + 'UCSR0C_USBS0': '$8', # Stop Bit Select + 'UCSR0C_UCSZ0': '$6', # Character Size + 'UCSR0C_UCPOL0': '$1', # Clock Polarity + 'UBRR0' : '$c4', # USART0 Baud Rate Register Byt + +# Module USART1 + 'UDR1' : '$ce', # USART1 I/O Data Register + 'UCSR1A' : '$c8', # USART1 Control and Status Regi + 'UCSR1A_RXC1': '$80', # USART Receive Complete + 'UCSR1A_TXC1': '$40', # USART Transmit Complete + 'UCSR1A_UDRE1': '$20', # USART Data Register Empty + 'UCSR1A_FE1': '$10', # Frame Error + 'UCSR1A_DOR1': '$8', # Data OverRun + 'UCSR1A_UPE1': '$4', # USART Parity Error + 'UCSR1A_U2X1': '$2', # Double the USART Transmission + 'UCSR1A_MPCM1': '$1', # Multi-processor Communication + 'UCSR1B' : '$c9', # USART1 Control and Status Regi + 'UCSR1B_RXCIE1': '$80', # RX Complete Interrupt Enable + 'UCSR1B_TXCIE1': '$40', # TX Complete Interrupt Enable + 'UCSR1B_UDRIE1': '$20', # USART Data Register Empty Inte + 'UCSR1B_RXEN1': '$10', # Receiver Enable + 'UCSR1B_TXEN1': '$8', # Transmitter Enable + 'UCSR1B_UCSZ12': '$4', # Character Size + 'UCSR1B_RXB81': '$2', # Receive Data Bit 8 + 'UCSR1B_TXB81': '$1', # Transmit Data Bit 8 + 'UCSR1C' : '$ca', # USART1 Control and Status Regi + 'UCSR1C_UMSEL1': '$c0', # USART Mode Select + 'UCSR1C_UPM1': '$30', # Parity Mode + 'UCSR1C_USBS1': '$8', # Stop Bit Select + 'UCSR1C_UCSZ1': '$6', # Character Size + 'UCSR1C_UCPOL1': '$1', # Clock Polarity + 'UBRR1' : '$cc', # USART1 Baud Rate Register Byt + +# Module TWI + 'TWAMR' : '$bd', # TWI (Slave) Address Mask Regis + 'TWAMR_TWAM': '$fe', # TWI Address Mask + 'TWAMR_Res': '$1', # Reserved Bit + 'TWBR' : '$b8', # TWI Bit Rate Register + 'TWCR' : '$bc', # TWI Control Register + 'TWCR_TWINT': '$80', # TWI Interrupt Flag + 'TWCR_TWEA': '$40', # TWI Enable Acknowledge Bit + 'TWCR_TWSTA': '$20', # TWI START Condition Bit + 'TWCR_TWSTO': '$10', # TWI STOP Condition Bit + 'TWCR_TWWC': '$8', # TWI Write Collision Flag + 'TWCR_TWEN': '$4', # TWI Enable Bit + 'TWCR_Res': '$2', # Reserved Bit + 'TWCR_TWIE': '$1', # TWI Interrupt Enable + 'TWSR' : '$b9', # TWI Status Register + 'TWSR_TWS': '$f8', # TWI Status + 'TWSR_Res': '$4', # Reserved Bit + 'TWSR_TWPS': '$3', # TWI Prescaler Bits + 'TWDR' : '$bb', # TWI Data Register + 'TWAR' : '$ba', # TWI (Slave) Address Register + 'TWAR_TWA': '$fe', # TWI (Slave) Address + 'TWAR_TWGCE': '$1', # TWI General Call Recognition E + +# Module SPI + 'SPCR' : '$4c', # SPI Control Register + 'SPCR_SPIE': '$80', # SPI Interrupt Enable + 'SPCR_SPE': '$40', # SPI Enable + 'SPCR_DORD': '$20', # Data Order + 'SPCR_MSTR': '$10', # Master/Slave Select + 'SPCR_CPOL': '$8', # Clock polarity + 'SPCR_CPHA': '$4', # Clock Phase + 'SPCR_SPR': '$3', # SPI Clock Rate Select 1 and 0 + 'SPSR' : '$4d', # SPI Status Register + 'SPSR_SPIF': '$80', # SPI Interrupt Flag + 'SPSR_WCOL': '$40', # Write Collision Flag + 'SPSR_Res': '$3e', # Reserved + 'SPSR_SPI2X': '$1', # Double SPI Speed Bit + 'SPDR' : '$4e', # SPI Data Register + +# Module PORTA + 'PORTA' : '$22', # Port A Data Register + 'DDRA' : '$21', # Port A Data Direction Register + 'PINA' : '$20', # Port A Input Pins Address + +# Module PORTB + 'PORTB' : '$25', # Port B Data Register + 'DDRB' : '$24', # Port B Data Direction Register + 'PINB' : '$23', # Port B Input Pins Address + +# Module PORTC + 'PORTC' : '$28', # Port C Data Register + 'DDRC' : '$27', # Port C Data Direction Register + 'PINC' : '$26', # Port C Input Pins Address + +# Module PORTD + 'PORTD' : '$2b', # Port D Data Register + 'DDRD' : '$2a', # Port D Data Direction Register + 'PIND' : '$29', # Port D Input Pins Address + +# Module PORTE + 'PORTE' : '$2e', # Port E Data Register + 'DDRE' : '$2d', # Port E Data Direction Register + 'PINE' : '$2c', # Port E Input Pins Address + +# Module PORTF + 'PORTF' : '$31', # Port F Data Register + 'DDRF' : '$30', # Port F Data Direction Register + 'PINF' : '$2f', # Port F Input Pins Address + +# Module PORTG + 'PORTG' : '$34', # Port G Data Register + 'DDRG' : '$33', # Port G Data Direction Register + 'PING' : '$32', # Port G Input Pins Address + +# Module TIMER_COUNTER_0 + 'OCR0B' : '$48', # Timer/Counter0 Output Compare + 'OCR0A' : '$47', # Timer/Counter0 Output Compare + 'TCNT0' : '$46', # Timer/Counter0 Register + 'TCCR0B' : '$45', # Timer/Counter0 Control Registe + 'TCCR0B_FOC0A': '$80', # Force Output Compare A + 'TCCR0B_FOC0B': '$40', # Force Output Compare B + 'TCCR0B_Res': '$30', # Reserved Bit + 'TCCR0B_WGM02': '$8', # + 'TCCR0B_CS0': '$7', # Clock Select + 'TCCR0A' : '$44', # Timer/Counter0 Control Registe + 'TCCR0A_COM0A': '$c0', # Compare Match Output A Mode + 'TCCR0A_COM0B': '$30', # Compare Match Output B Mode + 'TCCR0A_Res': '$c', # Reserved Bit + 'TCCR0A_WGM0': '$3', # Waveform Generation Mode + 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask + 'TIMSK0_Res': '$f8', # Reserved + 'TIMSK0_OCIE0B': '$4', # Timer/Counter0 Output Compare + 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare + 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr + 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag + 'TIFR0_Res': '$f8', # Reserved + 'TIFR0_OCF0B': '$4', # Timer/Counter0 Output Compare + 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare + 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag + 'GTCCR' : '$43', # General Timer/Counter Control + 'GTCCR_TSM': '$80', # Timer/Counter Synchronization + 'GTCCR_Res': '$7c', # Reserved + 'GTCCR_PSRASY': '$2', # Prescaler Reset Timer/Counter2 + 'GTCCR_PSRSYNC': '$1', # Prescaler Reset for Synchronou + +# Module TIMER_COUNTER_2 + 'TIMSK2' : '$70', # Timer/Counter Interrupt Mask r + 'TIMSK2_Res': '$f8', # Reserved Bit + 'TIMSK2_OCIE2B': '$4', # Timer/Counter2 Output Compare + 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare + 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr + 'TIFR2' : '$37', # Timer/Counter Interrupt Flag R + 'TIFR2_Res': '$f8', # Reserved Bit + 'TIFR2_OCF2B': '$4', # Output Compare Flag 2 B + 'TIFR2_OCF2A': '$2', # Output Compare Flag 2 A + 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag + 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe + 'TCCR2A_COM2A': '$c0', # Compare Match Output A Mode + 'TCCR2A_COM2B': '$30', # Compare Match Output B Mode + 'TCCR2A_Res': '$c', # Reserved + 'TCCR2A_WGM2': '$3', # Waveform Generation Mode + 'TCCR2B' : '$b1', # Timer/Counter2 Control Registe + 'TCCR2B_FOC2A': '$80', # Force Output Compare A + 'TCCR2B_FOC2B': '$40', # Force Output Compare B + 'TCCR2B_Res': '$30', # Reserved + 'TCCR2B_WGM22': '$8', # Waveform Generation Mode + 'TCCR2B_CS2': '$7', # Clock Select + 'TCNT2' : '$b2', # Timer/Counter2 + 'OCR2B' : '$b4', # Timer/Counter2 Output Compare + 'OCR2A' : '$b3', # Timer/Counter2 Output Compare + 'ASSR' : '$b6', # Asynchronous Status Register + 'ASSR_EXCLKAMR': '$80', # Enable External Clock Input fo + 'ASSR_EXCLK': '$40', # Enable External Clock Input + 'ASSR_AS2': '$20', # Timer/Counter2 Asynchronous Mo + 'ASSR_TCN2UB': '$10', # Timer/Counter2 Update Busy + 'ASSR_OCR2AUB': '$8', # Timer/Counter2 Output Compare + 'ASSR_OCR2BUB': '$4', # Timer/Counter2 Output Compare + 'ASSR_TCR2AUB': '$2', # Timer/Counter2 Control Registe + 'ASSR_TCR2BUB': '$1', # Timer/Counter2 Control Registe + 'GTCCR' : '$43', # General Timer Counter Control + 'GTCCR_TSM': '$80', # Timer/Counter Synchronization + 'GTCCR_PSRASY': '$2', # Prescaler Reset Timer/Counter2 + +# Module WATCHDOG + 'WDTCSR' : '$60', # Watchdog Timer Control Registe + 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla + 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena + 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits + 'WDTCSR_WDCE': '$10', # Watchdog Change Enable + 'WDTCSR_WDE': '$8', # Watch Dog Enable + +# Module TIMER_COUNTER_5 + 'TCCR5A' : '$120', # Timer/Counter5 Control Registe + 'TCCR5A_COM5A': '$c0', # Compare Output Mode for Channe + 'TCCR5A_COM5B': '$30', # Compare Output Mode for Channe + 'TCCR5A_COM5C': '$c', # Compare Output Mode for Channe + 'TCCR5A_WGM5': '$3', # Waveform Generation Mode + 'TCCR5B' : '$121', # Timer/Counter5 Control Registe + 'TCCR5B_ICNC5': '$80', # Input Capture 5 Noise Cancelle + 'TCCR5B_ICES5': '$40', # Input Capture 5 Edge Select + 'TCCR5B_Res': '$20', # Reserved Bit + 'TCCR5B_WGM5': '$18', # Waveform Generation Mode + 'TCCR5B_CS5': '$7', # Clock Select + 'TCCR5C' : '$122', # Timer/Counter5 Control Registe + 'TCCR5C_FOC5A': '$80', # Force Output Compare for Chann + 'TCCR5C_FOC5B': '$40', # Force Output Compare for Chann + 'TCCR5C_FOC5C': '$20', # Force Output Compare for Chann + 'TCCR5C_Res': '$1f', # Reserved + 'TCNT5' : '$124', # Timer/Counter5 Bytes + 'OCR5A' : '$128', # Timer/Counter5 Output Compare + 'OCR5B' : '$12a', # Timer/Counter5 Output Compare + 'OCR5C' : '$12c', # Timer/Counter5 Output Compare + 'ICR5' : '$126', # Timer/Counter5 Input Capture R + 'TIMSK5' : '$73', # Timer/Counter5 Interrupt Mask + 'TIMSK5_Res': '$c0', # Reserved Bit + 'TIMSK5_ICIE5': '$20', # Timer/Counter5 Input Capture I + 'TIMSK5_Res': '$10', # Reserved Bit + 'TIMSK5_OCIE5C': '$8', # Timer/Counter5 Output Compare + 'TIMSK5_OCIE5B': '$4', # Timer/Counter5 Output Compare + 'TIMSK5_OCIE5A': '$2', # Timer/Counter5 Output Compare + 'TIMSK5_TOIE5': '$1', # Timer/Counter5 Overflow Interr + 'TIFR5' : '$3a', # Timer/Counter5 Interrupt Flag + 'TIFR5_Res': '$c0', # Reserved Bit + 'TIFR5_ICF5': '$20', # Timer/Counter5 Input Capture F + 'TIFR5_Res': '$10', # Reserved Bit + 'TIFR5_OCF5C': '$8', # Timer/Counter5 Output Compare + 'TIFR5_OCF5B': '$4', # Timer/Counter5 Output Compare + 'TIFR5_OCF5A': '$2', # Timer/Counter5 Output Compare + 'TIFR5_TOV5': '$1', # Timer/Counter5 Overflow Flag + +# Module TIMER_COUNTER_4 + 'TCCR4A' : '$a0', # Timer/Counter4 Control Registe + 'TCCR4A_COM4A': '$c0', # Compare Output Mode for Channe + 'TCCR4A_COM4B': '$30', # Compare Output Mode for Channe + 'TCCR4A_COM4C': '$c', # Compare Output Mode for Channe + 'TCCR4A_WGM4': '$3', # Waveform Generation Mode + 'TCCR4B' : '$a1', # Timer/Counter4 Control Registe + 'TCCR4B_ICNC4': '$80', # Input Capture 4 Noise Cancelle + 'TCCR4B_ICES4': '$40', # Input Capture 4 Edge Select + 'TCCR4B_Res': '$20', # Reserved Bit + 'TCCR4B_WGM4': '$18', # Waveform Generation Mode + 'TCCR4B_CS4': '$7', # Clock Select + 'TCCR4C' : '$a2', # Timer/Counter4 Control Registe + 'TCCR4C_FOC4A': '$80', # Force Output Compare for Chann + 'TCCR4C_FOC4B': '$40', # Force Output Compare for Chann + 'TCCR4C_FOC4C': '$20', # Force Output Compare for Chann + 'TCCR4C_Res': '$1f', # Reserved + 'TCNT4' : '$a4', # Timer/Counter4 Bytes + 'OCR4A' : '$a8', # Timer/Counter4 Output Compare + 'OCR4B' : '$aa', # Timer/Counter4 Output Compare + 'OCR4C' : '$ac', # Timer/Counter4 Output Compare + 'ICR4' : '$a6', # Timer/Counter4 Input Capture R + 'TIMSK4' : '$72', # Timer/Counter4 Interrupt Mask + 'TIMSK4_Res': '$c0', # Reserved Bit + 'TIMSK4_ICIE4': '$20', # Timer/Counter4 Input Capture I + 'TIMSK4_Res': '$10', # Reserved Bit + 'TIMSK4_OCIE4C': '$8', # Timer/Counter4 Output Compare + 'TIMSK4_OCIE4B': '$4', # Timer/Counter4 Output Compare + 'TIMSK4_OCIE4A': '$2', # Timer/Counter4 Output Compare + 'TIMSK4_TOIE4': '$1', # Timer/Counter4 Overflow Interr + 'TIFR4' : '$39', # Timer/Counter4 Interrupt Flag + 'TIFR4_Res': '$c0', # Reserved Bit + 'TIFR4_ICF4': '$20', # Timer/Counter4 Input Capture F + 'TIFR4_Res': '$10', # Reserved Bit + 'TIFR4_OCF4C': '$8', # Timer/Counter4 Output Compare + 'TIFR4_OCF4B': '$4', # Timer/Counter4 Output Compare + 'TIFR4_OCF4A': '$2', # Timer/Counter4 Output Compare + 'TIFR4_TOV4': '$1', # Timer/Counter4 Overflow Flag + +# Module TIMER_COUNTER_3 + 'TCCR3A' : '$90', # Timer/Counter3 Control Registe + 'TCCR3A_COM3A': '$c0', # Compare Output Mode for Channe + 'TCCR3A_COM3B': '$30', # Compare Output Mode for Channe + 'TCCR3A_COM3C': '$c', # Compare Output Mode for Channe + 'TCCR3A_WGM3': '$3', # Waveform Generation Mode + 'TCCR3B' : '$91', # Timer/Counter3 Control Registe + 'TCCR3B_ICNC3': '$80', # Input Capture 3 Noise Cancelle + 'TCCR3B_ICES3': '$40', # Input Capture 3 Edge Select + 'TCCR3B_Res': '$20', # Reserved Bit + 'TCCR3B_WGM3': '$18', # Waveform Generation Mode + 'TCCR3B_CS3': '$7', # Clock Select + 'TCCR3C' : '$92', # Timer/Counter3 Control Registe + 'TCCR3C_FOC3A': '$80', # Force Output Compare for Chann + 'TCCR3C_FOC3B': '$40', # Force Output Compare for Chann + 'TCCR3C_FOC3C': '$20', # Force Output Compare for Chann + 'TCCR3C_Res': '$1f', # Reserved + 'TCNT3' : '$94', # Timer/Counter3 Bytes + 'OCR3A' : '$98', # Timer/Counter3 Output Compare + 'OCR3B' : '$9a', # Timer/Counter3 Output Compare + 'OCR3C' : '$9c', # Timer/Counter3 Output Compare + 'ICR3' : '$96', # Timer/Counter3 Input Capture R + 'TIMSK3' : '$71', # Timer/Counter3 Interrupt Mask + 'TIMSK3_Res': '$c0', # Reserved Bit + 'TIMSK3_ICIE3': '$20', # Timer/Counter3 Input Capture I + 'TIMSK3_Res': '$10', # Reserved Bit + 'TIMSK3_OCIE3C': '$8', # Timer/Counter3 Output Compare + 'TIMSK3_OCIE3B': '$4', # Timer/Counter3 Output Compare + 'TIMSK3_OCIE3A': '$2', # Timer/Counter3 Output Compare + 'TIMSK3_TOIE3': '$1', # Timer/Counter3 Overflow Interr + 'TIFR3' : '$38', # Timer/Counter3 Interrupt Flag + 'TIFR3_Res': '$c0', # Reserved Bit + 'TIFR3_ICF3': '$20', # Timer/Counter3 Input Capture F + 'TIFR3_Res': '$10', # Reserved Bit + 'TIFR3_OCF3C': '$8', # Timer/Counter3 Output Compare + 'TIFR3_OCF3B': '$4', # Timer/Counter3 Output Compare + 'TIFR3_OCF3A': '$2', # Timer/Counter3 Output Compare + 'TIFR3_TOV3': '$1', # Timer/Counter3 Overflow Flag + +# Module TIMER_COUNTER_1 + 'TCCR1A' : '$80', # Timer/Counter1 Control Registe + 'TCCR1A_COM1A': '$c0', # Compare Output Mode for Channe + 'TCCR1A_COM1B': '$30', # Compare Output Mode for Channe + 'TCCR1A_COM1C': '$c', # Compare Output Mode for Channe + 'TCCR1A_WGM1': '$3', # Waveform Generation Mode + 'TCCR1B' : '$81', # Timer/Counter1 Control Registe + 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Cancelle + 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select + 'TCCR1B_Res': '$20', # Reserved Bit + 'TCCR1B_WGM1': '$18', # Waveform Generation Mode + 'TCCR1B_CS1': '$7', # Clock Select + 'TCCR1C' : '$82', # Timer/Counter1 Control Registe + 'TCCR1C_FOC1A': '$80', # Force Output Compare for Chann + 'TCCR1C_FOC1B': '$40', # Force Output Compare for Chann + 'TCCR1C_FOC1C': '$20', # Force Output Compare for Chann + 'TCCR1C_Res': '$1f', # Reserved + 'TCNT1' : '$84', # Timer/Counter1 Bytes + 'OCR1A' : '$88', # Timer/Counter1 Output Compare + 'OCR1B' : '$8a', # Timer/Counter1 Output Compare + 'OCR1C' : '$8c', # Timer/Counter1 Output Compare + 'ICR1' : '$86', # Timer/Counter1 Input Capture R + 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask + 'TIMSK1_Res': '$c0', # Reserved Bit + 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I + 'TIMSK1_Res': '$10', # Reserved Bit + 'TIMSK1_OCIE1C': '$8', # Timer/Counter1 Output Compare + 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare + 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare + 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr + 'TIFR1' : '$36', # Timer/Counter1 Interrupt Flag + 'TIFR1_Res': '$c0', # Reserved Bit + 'TIFR1_ICF1': '$20', # Timer/Counter1 Input Capture F + 'TIFR1_Res': '$10', # Reserved Bit + 'TIFR1_OCF1C': '$8', # Timer/Counter1 Output Compare + 'TIFR1_OCF1B': '$4', # Timer/Counter1 Output Compare + 'TIFR1_OCF1A': '$2', # Timer/Counter1 Output Compare + 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag + +# Module TRX24 + 'PARCR' : '$138', # Power Amplifier Ramp up/down C + 'PARCR_PALTD': '$e0', # ext. PA Ramp Down Lead Time + 'PARCR_PALTU': '$1c', # ext. PA Ramp Up Lead Time + 'PARCR_PARDFI': '$2', # Power Amplifier Ramp Down Freq + 'PARCR_PARUFI': '$1', # Power Amplifier Ramp Up Freque + 'MAFSA0L' : '$10e', # Transceiver MAC Short Address + 'MAFSA0L_MAFSA0L': '$ff', # MAC Short Address low Byte for + 'MAFSA0H' : '$10f', # Transceiver MAC Short Address + 'MAFSA0H_MAFSA0H': '$ff', # MAC Short Address high Byte fo + 'MAFPA0L' : '$110', # Transceiver Personal Area Netw + 'MAFPA0L_MAFPA0L': '$ff', # MAC Personal Area Network ID l + 'MAFPA0H' : '$111', # Transceiver Personal Area Netw + 'MAFPA0H_MAFPA0H': '$ff', # MAC Personal Area Network ID h + 'MAFSA1L' : '$112', # Transceiver MAC Short Address + 'MAFSA1L_MAFSA1L': '$ff', # MAC Short Address low Byte for + 'MAFSA1H' : '$113', # Transceiver MAC Short Address + 'MAFSA1H_MAFSA1H': '$ff', # MAC Short Address high Byte fo + 'MAFPA1L' : '$114', # Transceiver Personal Area Netw + 'MAFPA1L_MAFPA1L': '$ff', # MAC Personal Area Network ID l + 'MAFPA1H' : '$115', # Transceiver Personal Area Netw + 'MAFPA1H_MAFPA1H': '$ff', # MAC Personal Area Network ID h + 'MAFSA2L' : '$116', # Transceiver MAC Short Address + 'MAFSA2L_MAFSA2L': '$ff', # MAC Short Address low Byte for + 'MAFSA2H' : '$117', # Transceiver MAC Short Address + 'MAFSA2H_MAFSA2H': '$ff', # MAC Short Address high Byte fo + 'MAFPA2L' : '$118', # Transceiver Personal Area Netw + 'MAFPA2L_MAFPA2L': '$ff', # MAC Personal Area Network ID l + 'MAFPA2H' : '$119', # Transceiver Personal Area Netw + 'MAFPA2H_MAFPA2H': '$ff', # MAC Personal Area Network ID h + 'MAFSA3L' : '$11a', # Transceiver MAC Short Address + 'MAFSA3L_MAFSA3L': '$ff', # MAC Short Address low Byte for + 'MAFSA3H' : '$11b', # Transceiver MAC Short Address + 'MAFSA3H_MAFSA3H': '$ff', # MAC Short Address high Byte fo + 'MAFPA3L' : '$11c', # Transceiver Personal Area Netw + 'MAFPA3L_MAFPA3L': '$ff', # MAC Personal Area Network ID l + 'MAFPA3H' : '$11d', # Transceiver Personal Area Netw + 'MAFPA3H_MAFPA3H': '$ff', # MAC Personal Area Network ID h + 'MAFCR0' : '$10c', # Multiple Address Filter Config + 'MAFCR0_Res': '$f0', # Reserved Bit + 'MAFCR0_MAF3EN': '$8', # Multiple Address Filter 3 Enab + 'MAFCR0_MAF2EN': '$4', # Multiple Address Filter 2 Enab + 'MAFCR0_MAF1EN': '$2', # Multiple Address Filter 1 Enab + 'MAFCR0_MAF0EN': '$1', # Multiple Address Filter 0 Enab + 'MAFCR1' : '$10d', # Multiple Address Filter Config + 'MAFCR1_AACK_3_SET_PD': '$80', # Set Data Pending bit for addre + 'MAFCR1_AACK_3_I_AM_COORD': '$40', # Enable PAN Coordinator mode fo + 'MAFCR1_AACK_2_SET_PD': '$20', # Set Data Pending bit for addre + 'MAFCR1_AACK_2_I_AM_COORD': '$10', # Enable PAN Coordinator mode fo + 'MAFCR1_AACK_1_SET_PD': '$8', # Set Data Pending bit for addre + 'MAFCR1_AACK_1_I_AM_COORD': '$4', # Enable PAN Coordinator mode fo + 'MAFCR1_AACK_0_SET_PD': '$2', # Set Data Pending bit for addre + 'MAFCR1_AACK_0_I_AM_COORD': '$1', # Enable PAN Coordinator mode fo + 'AES_CTRL' : '$13c', # AES Control Register + 'AES_CTRL_AES_REQUEST': '$80', # Request AES Operation. + 'AES_CTRL_Res': '$40', # Reserved Bit + 'AES_CTRL_AES_MODE': '$20', # Set AES Operation Mode + 'AES_CTRL_Res': '$10', # Reserved Bit + 'AES_CTRL_AES_DIR': '$8', # Set AES Operation Direction + 'AES_CTRL_AES_IM': '$4', # AES Interrupt Enable + 'AES_CTRL_Res': '$3', # Reserved Bit + 'AES_STATUS' : '$13d', # AES Status Register + 'AES_STATUS_AES_ER': '$80', # AES Operation Finished with Er + 'AES_STATUS_Res': '$7e', # Reserved + 'AES_STATUS_AES_DONE': '$1', # AES Operation Finished with Su + 'AES_STATE' : '$13e', # AES Plain and Cipher Text Buff + 'AES_STATE_AES_STATE': '$ff', # AES Plain and Cipher Text Buff + 'AES_KEY' : '$13f', # AES Encryption and Decryption + 'AES_KEY_AES_KEY': '$ff', # AES Encryption/Decryption Key + 'TRX_STATUS' : '$141', # Transceiver Status Register + 'TRX_STATUS_CCA_DONE': '$80', # CCA Algorithm Status + 'TRX_STATUS_CCA_STATUS': '$40', # CCA Status Result + 'TRX_STATUS_TST_STATUS': '$20', # Test mode status + 'TRX_STATUS_TRX_STATUS': '$1f', # Transceiver Main Status + 'TRX_STATE' : '$142', # Transceiver State Control Regi + 'TRX_STATE_TRAC_STATUS': '$e0', # Transaction Status + 'TRX_STATE_TRX_CMD': '$1f', # State Control Command + 'TRX_CTRL_0' : '$143', # Reserved + 'TRX_CTRL_0_Res7': '$80', # Reserved + 'TRX_CTRL_0_PMU_EN': '$40', # Enable Phase Measurement Unit + 'TRX_CTRL_0_PMU_START': '$20', # Start of Phase Measurement Uni + 'TRX_CTRL_0_PMU_IF_INV': '$10', # PMU IF Inverse + 'TRX_CTRL_0_Res': '$f', # Reserved + 'TRX_CTRL_1' : '$144', # Transceiver Control Register 1 + 'TRX_CTRL_1_PA_EXT_EN': '$80', # External PA support enable + 'TRX_CTRL_1_IRQ_2_EXT_EN': '$40', # Connect Frame Start IRQ to TC1 + 'TRX_CTRL_1_TX_AUTO_CRC_ON': '$20', # Enable Automatic CRC Calculati + 'TRX_CTRL_1_PLL_TX_FLT': '$10', # Enable PLL TX filter + 'TRX_CTRL_1_Res': '$f', # Reserved + 'PHY_TX_PWR' : '$145', # Transceiver Transmit Power Con + 'PHY_TX_PWR_Res': '$f0', # Reserved + 'PHY_TX_PWR_TX_PWR': '$f', # Transmit Power Setting + 'PHY_RSSI' : '$146', # Receiver Signal Strength Indic + 'PHY_RSSI_RX_CRC_VALID': '$80', # Received Frame CRC Status + 'PHY_RSSI_RND_VALUE': '$60', # Random Value + 'PHY_RSSI_RSSI': '$1f', # Receiver Signal Strength Indic + 'PHY_ED_LEVEL' : '$147', # Transceiver Energy Detection L + 'PHY_ED_LEVEL_ED_LEVEL': '$ff', # Energy Detection Level + 'PHY_CC_CCA' : '$148', # Transceiver Clear Channel Asse + 'PHY_CC_CCA_CCA_REQUEST': '$80', # Manual CCA Measurement Request + 'PHY_CC_CCA_CCA_MODE': '$60', # Select CCA Measurement Mode + 'PHY_CC_CCA_CHANNEL': '$1f', # RX/TX Channel Selection + 'CCA_THRES' : '$149', # Transceiver CCA Threshold Sett + 'CCA_THRES_CCA_CS_THRES': '$f0', # CS Threshold Level for CCA Mea + 'CCA_THRES_CCA_ED_THRES': '$f', # ED Threshold Level for CCA Mea + 'RX_CTRL' : '$14a', # Transceiver Receive Control Re + 'RX_CTRL_PDT_THRES': '$f', # Receiver Sensitivity Control + 'SFD_VALUE' : '$14b', # Start of Frame Delimiter Value + 'SFD_VALUE_SFD_VALUE': '$ff', # Start of Frame Delimiter Value + 'TRX_CTRL_2' : '$14c', # Transceiver Control Register 2 + 'TRX_CTRL_2_RX_SAFE_MODE': '$80', # RX Safe Mode + 'TRX_CTRL_2_Res': '$7c', # Reserved + 'TRX_CTRL_2_OQPSK_DATA_RATE': '$3', # Data Rate Selection + 'ANT_DIV' : '$14d', # Antenna Diversity Control Regi + 'ANT_DIV_ANT_SEL': '$80', # Antenna Diversity Antenna Stat + 'ANT_DIV_Res': '$70', # Reserved + 'ANT_DIV_ANT_DIV_EN': '$8', # Enable Antenna Diversity + 'ANT_DIV_ANT_EXT_SW_EN': '$4', # Enable External Antenna Switch + 'ANT_DIV_ANT_CTRL': '$3', # Static Antenna Diversity Switc + 'IRQ_MASK' : '$14e', # Transceiver Interrupt Enable R + 'IRQ_MASK_AWAKE_EN': '$80', # Awake Interrupt Enable + 'IRQ_MASK_TX_END_EN': '$40', # TX_END Interrupt Enable + 'IRQ_MASK_AMI_EN': '$20', # Address Match Interrupt Enable + 'IRQ_MASK_CCA_ED_DONE_EN': '$10', # End of ED Measurement Interrup + 'IRQ_MASK_RX_END_EN': '$8', # RX_END Interrupt Enable + 'IRQ_MASK_RX_START_EN': '$4', # RX_START Interrupt Enable + 'IRQ_MASK_PLL_UNLOCK_EN': '$2', # PLL Unlock Interrupt Enable + 'IRQ_MASK_PLL_LOCK_EN': '$1', # PLL Lock Interrupt Enable + 'IRQ_STATUS' : '$14f', # Transceiver Interrupt Status R + 'IRQ_STATUS_AWAKE': '$80', # Awake Interrupt Status + 'IRQ_STATUS_TX_END': '$40', # TX_END Interrupt Status + 'IRQ_STATUS_AMI': '$20', # Address Match Interrupt Status + 'IRQ_STATUS_CCA_ED_DONE': '$10', # End of ED Measurement Interrup + 'IRQ_STATUS_RX_END': '$8', # RX_END Interrupt Status + 'IRQ_STATUS_RX_START': '$4', # RX_START Interrupt Status + 'IRQ_STATUS_PLL_UNLOCK': '$2', # PLL Unlock Interrupt Status + 'IRQ_STATUS_PLL_LOCK': '$1', # PLL Lock Interrupt Status + 'IRQ_MASK1' : '$be', # Transceiver Interrupt Enable R + 'IRQ_MASK1_Res': '$e0', # Reserved Bit + 'IRQ_MASK1_MAF_3_AMI_EN': '$10', # Address Match Interrupt enable + 'IRQ_MASK1_MAF_2_AMI_EN': '$8', # Address Match Interrupt enable + 'IRQ_MASK1_MAF_1_AMI_EN': '$4', # Address Match Interrupt enable + 'IRQ_MASK1_MAF_0_AMI_EN': '$2', # Address Match Interrupt enable + 'IRQ_MASK1_TX_START_EN': '$1', # Transmit Start Interrupt enabl + 'IRQ_STATUS1' : '$bf', # Transceiver Interrupt Status R + 'IRQ_STATUS1_Res': '$e0', # Reserved Bit + 'IRQ_STATUS1_MAF_3_AMI': '$10', # Address Match Interrupt Status + 'IRQ_STATUS1_MAF_2_AMI': '$8', # Address Match Interrupt Status + 'IRQ_STATUS1_MAF_1_AMI': '$4', # Address Match Interrupt Status + 'IRQ_STATUS1_MAF_0_AMI': '$2', # Address Match Interrupt Status + 'IRQ_STATUS1_TX_START': '$1', # Transmit Start Interrupt Statu + 'VREG_CTRL' : '$150', # Voltage Regulator Control and + 'VREG_CTRL_AVREG_EXT': '$80', # Use External AVDD Regulator + 'VREG_CTRL_AVDD_OK': '$40', # AVDD Supply Voltage Valid + 'VREG_CTRL_DVREG_EXT': '$8', # Use External DVDD Regulator + 'VREG_CTRL_DVDD_OK': '$4', # DVDD Supply Voltage Valid + 'BATMON' : '$151', # Battery Monitor Control and St + 'BATMON_BAT_LOW': '$80', # Battery Monitor Interrupt Stat + 'BATMON_BAT_LOW_EN': '$40', # Battery Monitor Interrupt Enab + 'BATMON_BATMON_OK': '$20', # Battery Monitor Status + 'BATMON_BATMON_HR': '$10', # Battery Monitor Voltage Range + 'BATMON_BATMON_VTH': '$f', # Battery Monitor Threshold Volt + 'XOSC_CTRL' : '$152', # Crystal Oscillator Control Reg + 'XOSC_CTRL_XTAL_MODE': '$f0', # Crystal Oscillator Operating M + 'XOSC_CTRL_XTAL_TRIM': '$f', # Crystal Oscillator Load Capaci + 'CC_CTRL_0' : '$153', # Channel Control Register 0 + 'CC_CTRL_0_CC_NUMBER': '$ff', # Channel Number + 'CC_CTRL_1' : '$154', # Channel Control Register 1 + 'CC_CTRL_1_CC_BAND': '$f', # Channel Band + 'RX_SYN' : '$155', # Transceiver Receiver Sensitivi + 'RX_SYN_RX_PDT_DIS': '$80', # Prevent Frame Reception + 'RX_SYN_RX_OVERRIDE': '$40', # Receiver Override Function + 'RX_SYN_Res': '$30', # Reserved + 'RX_SYN_RX_PDT_LEVEL': '$f', # Reduce Receiver Sensitivity + 'TRX_RPC' : '$156', # Transceiver Reduced Power Cons + 'TRX_RPC_RX_RPC_CTRL': '$c0', # Smart Receiving Mode Timing + 'TRX_RPC_RX_RPC_EN': '$20', # Reciver Smart Receiving Mode E + 'TRX_RPC_PDT_RPC_EN': '$10', # Smart Receiving Mode Reduced S + 'TRX_RPC_PLL_RPC_EN': '$8', # PLL Smart Receiving Mode Enabl + 'TRX_RPC_Res0': '$4', # Reserved + 'TRX_RPC_IPAN_RPC_EN': '$2', # Smart Receiving Mode IPAN Hand + 'TRX_RPC_XAH_RPC_EN': '$1', # Smart Receiving in Extended Op + 'XAH_CTRL_1' : '$157', # Transceiver Acknowledgment Fra + 'XAH_CTRL_1_Res': '$c0', # Reserved Bit + 'XAH_CTRL_1_AACK_FLTR_RES_FT': '$20', # Filter Reserved Frames + 'XAH_CTRL_1_AACK_UPLD_RES_FT': '$10', # Process Reserved Frames + 'XAH_CTRL_1_Res': '$8', # Reserved Bit + 'XAH_CTRL_1_AACK_ACK_TIME': '$4', # Reduce Acknowledgment Time + 'XAH_CTRL_1_AACK_PROM_MODE': '$2', # Enable Promiscuous Mode + 'XAH_CTRL_1_Res': '$1', # Reserved Bit + 'FTN_CTRL' : '$158', # Transceiver Filter Tuning Cont + 'FTN_CTRL_FTN_START': '$80', # Start Calibration Loop of Filt + 'PLL_CF' : '$15a', # Transceiver Center Frequency C + 'PLL_CF_PLL_CF_START': '$80', # Start Center Frequency Calibra + 'PLL_DCU' : '$15b', # Transceiver Delay Cell Calibra + 'PLL_DCU_PLL_DCU_START': '$80', # Start Delay Cell Calibration + 'PART_NUM' : '$15c', # Device Identification Register + 'PART_NUM_PART_NUM': '$ff', # Part Number + 'VERSION_NUM' : '$15d', # Device Identification Register + 'VERSION_NUM_VERSION_NUM': '$ff', # Version Number + 'MAN_ID_0' : '$15e', # Device Identification Register + 'MAN_ID_0_MAN_ID_07': '$80', # Manufacturer ID (Low Byte) + 'MAN_ID_0_MAN_ID_06': '$40', # Manufacturer ID (Low Byte) + 'MAN_ID_0_MAN_ID_05': '$20', # Manufacturer ID (Low Byte) + 'MAN_ID_0_MAN_ID_04': '$10', # Manufacturer ID (Low Byte) + 'MAN_ID_0_MAN_ID_03': '$8', # Manufacturer ID (Low Byte) + 'MAN_ID_0_MAN_ID_02': '$4', # Manufacturer ID (Low Byte) + 'MAN_ID_0_MAN_ID_01': '$2', # Manufacturer ID (Low Byte) + 'MAN_ID_0_MAN_ID_00': '$1', # Manufacturer ID (Low Byte) + 'MAN_ID_1' : '$15f', # Device Identification Register + 'MAN_ID_1_MAN_ID_': '$ff', # Manufacturer ID (High Byte) + 'SHORT_ADDR_0' : '$160', # Transceiver MAC Short Address + 'SHORT_ADDR_0_SHORT_ADDR_07': '$80', # MAC Short Address + 'SHORT_ADDR_0_SHORT_ADDR_06': '$40', # MAC Short Address + 'SHORT_ADDR_0_SHORT_ADDR_05': '$20', # MAC Short Address + 'SHORT_ADDR_0_SHORT_ADDR_04': '$10', # MAC Short Address + 'SHORT_ADDR_0_SHORT_ADDR_03': '$8', # MAC Short Address + 'SHORT_ADDR_0_SHORT_ADDR_02': '$4', # MAC Short Address + 'SHORT_ADDR_0_SHORT_ADDR_01': '$2', # MAC Short Address + 'SHORT_ADDR_0_SHORT_ADDR_00': '$1', # MAC Short Address + 'SHORT_ADDR_1' : '$161', # Transceiver MAC Short Address + 'SHORT_ADDR_1_SHORT_ADDR_': '$ff', # MAC Short Address + 'PAN_ID_0' : '$162', # Transceiver Personal Area Netw + 'PAN_ID_0_PAN_ID_07': '$80', # MAC Personal Area Network ID + 'PAN_ID_0_PAN_ID_06': '$40', # MAC Personal Area Network ID + 'PAN_ID_0_PAN_ID_05': '$20', # MAC Personal Area Network ID + 'PAN_ID_0_PAN_ID_04': '$10', # MAC Personal Area Network ID + 'PAN_ID_0_PAN_ID_03': '$8', # MAC Personal Area Network ID + 'PAN_ID_0_PAN_ID_02': '$4', # MAC Personal Area Network ID + 'PAN_ID_0_PAN_ID_01': '$2', # MAC Personal Area Network ID + 'PAN_ID_0_PAN_ID_00': '$1', # MAC Personal Area Network ID + 'PAN_ID_1' : '$163', # Transceiver Personal Area Netw + 'PAN_ID_1_PAN_ID_': '$ff', # MAC Personal Area Network ID + 'IEEE_ADDR_0' : '$164', # Transceiver MAC IEEE Address R + 'IEEE_ADDR_0_IEEE_ADDR_07': '$80', # MAC IEEE Address + 'IEEE_ADDR_0_IEEE_ADDR_06': '$40', # MAC IEEE Address + 'IEEE_ADDR_0_IEEE_ADDR_05': '$20', # MAC IEEE Address + 'IEEE_ADDR_0_IEEE_ADDR_04': '$10', # MAC IEEE Address + 'IEEE_ADDR_0_IEEE_ADDR_03': '$8', # MAC IEEE Address + 'IEEE_ADDR_0_IEEE_ADDR_02': '$4', # MAC IEEE Address + 'IEEE_ADDR_0_IEEE_ADDR_01': '$2', # MAC IEEE Address + 'IEEE_ADDR_0_IEEE_ADDR_00': '$1', # MAC IEEE Address + 'IEEE_ADDR_1' : '$165', # Transceiver MAC IEEE Address R + 'IEEE_ADDR_1_IEEE_ADDR_': '$ff', # MAC IEEE Address + 'IEEE_ADDR_2' : '$166', # Transceiver MAC IEEE Address R + 'IEEE_ADDR_2_IEEE_ADDR_': '$ff', # MAC IEEE Address + 'IEEE_ADDR_3' : '$167', # Transceiver MAC IEEE Address R + 'IEEE_ADDR_3_IEEE_ADDR_': '$ff', # MAC IEEE Address + 'IEEE_ADDR_4' : '$168', # Transceiver MAC IEEE Address R + 'IEEE_ADDR_4_IEEE_ADDR_': '$ff', # MAC IEEE Address + 'IEEE_ADDR_5' : '$169', # Transceiver MAC IEEE Address R + 'IEEE_ADDR_5_IEEE_ADDR_': '$ff', # MAC IEEE Address + 'IEEE_ADDR_6' : '$16a', # Transceiver MAC IEEE Address R + 'IEEE_ADDR_6_IEEE_ADDR_': '$ff', # MAC IEEE Address + 'IEEE_ADDR_7' : '$16b', # Transceiver MAC IEEE Address R + 'IEEE_ADDR_7_IEEE_ADDR_': '$ff', # MAC IEEE Address + 'XAH_CTRL_0' : '$16c', # Transceiver Extended Operating + 'XAH_CTRL_0_MAX_FRAME_RETRIES': '$f0', # Maximum Number of Frame Re-tra + 'XAH_CTRL_0_MAX_CSMA_RETRIES': '$e', # Maximum Number of CSMA-CA Proc + 'XAH_CTRL_0_SLOTTED_OPERATION': '$1', # Set Slotted Acknowledgment + 'CSMA_SEED_0' : '$16d', # Transceiver CSMA-CA Random Num + 'CSMA_SEED_0_CSMA_SEED_07': '$80', # Seed Value for CSMA Random Num + 'CSMA_SEED_0_CSMA_SEED_06': '$40', # Seed Value for CSMA Random Num + 'CSMA_SEED_0_CSMA_SEED_05': '$20', # Seed Value for CSMA Random Num + 'CSMA_SEED_0_CSMA_SEED_04': '$10', # Seed Value for CSMA Random Num + 'CSMA_SEED_0_CSMA_SEED_03': '$8', # Seed Value for CSMA Random Num + 'CSMA_SEED_0_CSMA_SEED_02': '$4', # Seed Value for CSMA Random Num + 'CSMA_SEED_0_CSMA_SEED_01': '$2', # Seed Value for CSMA Random Num + 'CSMA_SEED_0_CSMA_SEED_00': '$1', # Seed Value for CSMA Random Num + 'CSMA_SEED_1' : '$16e', # Transceiver Acknowledgment Fra + 'CSMA_SEED_1_AACK_FVN_MODE': '$c0', # Acknowledgment Frame Filter Mo + 'CSMA_SEED_1_AACK_SET_PD': '$20', # Set Frame Pending Sub-field + 'CSMA_SEED_1_AACK_DIS_ACK': '$10', # Disable Acknowledgment Frame T + 'CSMA_SEED_1_AACK_I_AM_COORD': '$8', # Set Personal Area Network Coor + 'CSMA_SEED_1_CSMA_SEED_1': '$7', # Seed Value for CSMA Random Num + 'CSMA_BE' : '$16f', # Transceiver CSMA-CA Back-off E + 'CSMA_BE_MAX_BE': '$f0', # Maximum Back-off Exponent + 'CSMA_BE_MIN_BE': '$f', # Minimum Back-off Exponent + 'TST_CTRL_DIGI' : '$176', # Transceiver Digital Test Contr + 'TST_CTRL_DIGI_TST_CTRL_DIG': '$f', # Digital Test Controller Regist + 'TST_RX_LENGTH' : '$17b', # Transceiver Received Frame Len + 'TST_RX_LENGTH_RX_LENGTH': '$ff', # Received Frame Length + 'TRXFBST' : '$180', # Start of frame buffer + 'TRXFBEND' : '$1ff', # End of frame buffer + +# Module SYMCNT + 'SCTSTRHH' : '$fc', # Symbol Counter Transmit Frame + 'SCTSTRHH_SCTSTRHH': '$ff', # Symbol Counter Transmit Frame + 'SCTSTRHL' : '$fb', # Symbol Counter Transmit Frame + 'SCTSTRHL_SCTSTRHL': '$ff', # Symbol Counter Transmit Frame + 'SCTSTRLH' : '$fa', # Symbol Counter Transmit Frame + 'SCTSTRLH_SCTSTRLH': '$ff', # Symbol Counter Transmit Frame + 'SCTSTRLL' : '$f9', # Symbol Counter Transmit Frame + 'SCTSTRLL_SCTSTRLL': '$ff', # Symbol Counter Transmit Frame + 'SCOCR1HH' : '$f8', # Symbol Counter Output Compare + 'SCOCR1HH_SCOCR1HH': '$ff', # Symbol Counter Output Compare + 'SCOCR1HL' : '$f7', # Symbol Counter Output Compare + 'SCOCR1HL_SCOCR1HL': '$ff', # Symbol Counter Output Compare + 'SCOCR1LH' : '$f6', # Symbol Counter Output Compare + 'SCOCR1LH_SCOCR1LH': '$ff', # Symbol Counter Output Compare + 'SCOCR1LL' : '$f5', # Symbol Counter Output Compare + 'SCOCR1LL_SCOCR1LL': '$ff', # Symbol Counter Output Compare + 'SCOCR2HH' : '$f4', # Symbol Counter Output Compare + 'SCOCR2HH_SCOCR2HH': '$ff', # Symbol Counter Output Compare + 'SCOCR2HL' : '$f3', # Symbol Counter Output Compare + 'SCOCR2HL_SCOCR2HL': '$ff', # Symbol Counter Output Compare + 'SCOCR2LH' : '$f2', # Symbol Counter Output Compare + 'SCOCR2LH_SCOCR2LH': '$ff', # Symbol Counter Output Compare + 'SCOCR2LL' : '$f1', # Symbol Counter Output Compare + 'SCOCR2LL_SCOCR2LL': '$ff', # Symbol Counter Output Compare + 'SCOCR3HH' : '$f0', # Symbol Counter Output Compare + 'SCOCR3HH_SCOCR3HH': '$ff', # Symbol Counter Output Compare + 'SCOCR3HL' : '$ef', # Symbol Counter Output Compare + 'SCOCR3HL_SCOCR3HL': '$ff', # Symbol Counter Output Compare + 'SCOCR3LH' : '$ee', # Symbol Counter Output Compare + 'SCOCR3LH_SCOCR3LH': '$ff', # Symbol Counter Output Compare + 'SCOCR3LL' : '$ed', # Symbol Counter Output Compare + 'SCOCR3LL_SCOCR3LL': '$ff', # Symbol Counter Output Compare + 'SCTSRHH' : '$ec', # Symbol Counter Frame Timestamp + 'SCTSRHH_SCTSRHH': '$ff', # Symbol Counter Frame Timestamp + 'SCTSRHL' : '$eb', # Symbol Counter Frame Timestamp + 'SCTSRHL_SCTSRHL': '$ff', # Symbol Counter Frame Timestamp + 'SCTSRLH' : '$ea', # Symbol Counter Frame Timestamp + 'SCTSRLH_SCTSRLH': '$ff', # Symbol Counter Frame Timestamp + 'SCTSRLL' : '$e9', # Symbol Counter Frame Timestamp + 'SCTSRLL_SCTSRLL': '$ff', # Symbol Counter Frame Timestamp + 'SCBTSRHH' : '$e8', # Symbol Counter Beacon Timestam + 'SCBTSRHH_SCBTSRHH': '$ff', # Symbol Counter Beacon Timestam + 'SCBTSRHL' : '$e7', # Symbol Counter Beacon Timestam + 'SCBTSRHL_SCBTSRHL': '$ff', # Symbol Counter Beacon Timestam + 'SCBTSRLH' : '$e6', # Symbol Counter Beacon Timestam + 'SCBTSRLH_SCBTSRLH': '$ff', # Symbol Counter Beacon Timestam + 'SCBTSRLL' : '$e5', # Symbol Counter Beacon Timestam + 'SCBTSRLL_SCBTSRLL': '$ff', # Symbol Counter Beacon Timestam + 'SCCNTHH' : '$e4', # Symbol Counter Register HH-Byt + 'SCCNTHH_SCCNTHH': '$ff', # Symbol Counter Register HH-Byt + 'SCCNTHL' : '$e3', # Symbol Counter Register HL-Byt + 'SCCNTHL_SCCNTHL': '$ff', # Symbol Counter Register HL-Byt + 'SCCNTLH' : '$e2', # Symbol Counter Register LH-Byt + 'SCCNTLH_SCCNTLH': '$ff', # Symbol Counter Register LH-Byt + 'SCCNTLL' : '$e1', # Symbol Counter Register LL-Byt + 'SCCNTLL_SCCNTLL': '$ff', # Symbol Counter Register LL-Byt + 'SCIRQS' : '$e0', # Symbol Counter Interrupt Statu + 'SCIRQS_Res': '$e0', # Reserved Bit + 'SCIRQS_IRQSBO': '$10', # Backoff Slot Counter IRQ + 'SCIRQS_IRQSOF': '$8', # Symbol Counter Overflow IRQ + 'SCIRQS_IRQSCP': '$7', # Compare Unit 3 Compare Match I + 'SCIRQM' : '$df', # Symbol Counter Interrupt Mask + 'SCIRQM_Res': '$e0', # Reserved Bit + 'SCIRQM_IRQMBO': '$10', # Backoff Slot Counter IRQ enabl + 'SCIRQM_IRQMOF': '$8', # Symbol Counter Overflow IRQ en + 'SCIRQM_IRQMCP': '$7', # Symbol Counter Compare Match 3 + 'SCSR' : '$de', # Symbol Counter Status Register + 'SCSR_Res': '$fe', # Reserved Bit + 'SCSR_SCBSY': '$1', # Symbol Counter busy + 'SCCR1' : '$dd', # Symbol Counter Control Registe + 'SCCR1_Res': '$c0', # Reserved Bit + 'SCCR1_SCBTSM': '$20', # Symbol Counter Beacon Timestam + 'SCCR1_SCCKDIV': '$1c', # Clock divider for synchronous + 'SCCR1_SCEECLK': '$2', # Enable External Clock Source o + 'SCCR1_SCENBO': '$1', # Backoff Slot Counter enable + 'SCCR0' : '$dc', # Symbol Counter Control Registe + 'SCCR0_SCRES': '$80', # Symbol Counter Synchronization + 'SCCR0_SCMBTS': '$40', # Manual Beacon Timestamp + 'SCCR0_SCEN': '$20', # Symbol Counter enable + 'SCCR0_SCCKSEL': '$10', # Symbol Counter Clock Source se + 'SCCR0_SCTSE': '$8', # Symbol Counter Automatic Times + 'SCCR0_SCCMP': '$7', # Symbol Counter Compare Unit 3 + 'SCCSR' : '$db', # Symbol Counter Compare Source + 'SCCSR_Res': '$c0', # Reserved Bit + 'SCCSR_SCCS3': '$30', # Symbol Counter Compare Source + 'SCCSR_SCCS2': '$c', # Symbol Counter Compare Source + 'SCCSR_SCCS1': '$3', # Symbol Counter Compare Source + 'SCRSTRHH' : '$da', # Symbol Counter Received Frame + 'SCRSTRHH_SCRSTRHH': '$ff', # Symbol Counter Received Frame + 'SCRSTRHL' : '$d9', # Symbol Counter Received Frame + 'SCRSTRHL_SCRSTRHL': '$ff', # Symbol Counter Received Frame + 'SCRSTRLH' : '$d8', # Symbol Counter Received Frame + 'SCRSTRLH_SCRSTRLH': '$ff', # Symbol Counter Received Frame + 'SCRSTRLL' : '$d7', # Symbol Counter Received Frame + 'SCRSTRLL_SCRSTRLL': '$ff', # Symbol Counter Received Frame + +# Module EEPROM + 'EEAR' : '$41', # EEPROM Address Register Bytes + 'EEDR' : '$40', # EEPROM Data Register + 'EECR' : '$3f', # EEPROM Control Register + 'EECR_Res': '$c0', # Reserved + 'EECR_EEPM': '$30', # EEPROM Programming Mode + 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable + 'EECR_EEMPE': '$4', # EEPROM Master Write Enable + 'EECR_EEPE': '$2', # EEPROM Programming Enable + 'EECR_EERE': '$1', # EEPROM Read Enable + +# Module JTAG + 'OCDR' : '$51', # On-Chip Debug Register + 'OCDR_OCDR': '$ff', # On-Chip Debug Register Data + 'MCUCR' : '$55', # MCU Control Register + 'MCUCR_JTD': '$80', # JTAG Interface Disable + 'MCUSR' : '$54', # MCU Status Register + 'MCUSR_JTRF': '$10', # JTAG Reset Flag + +# Module EXTERNAL_INTERRUPT + 'EICRA' : '$69', # External Interrupt Control Reg + 'EICRA_ISC3': '$c0', # External Interrupt 3 Sense Con + 'EICRA_ISC2': '$30', # External Interrupt 2 Sense Con + 'EICRA_ISC1': '$c', # External Interrupt 1 Sense Con + 'EICRA_ISC0': '$3', # External Interrupt 0 Sense Con + 'EICRB' : '$6a', # External Interrupt Control Reg + 'EICRB_ISC7': '$c0', # External Interrupt 7 Sense Con + 'EICRB_ISC6': '$30', # External Interrupt 6 Sense Con + 'EICRB_ISC5': '$c', # External Interrupt 5 Sense Con + 'EICRB_ISC4': '$3', # External Interrupt 4 Sense Con + 'EIMSK' : '$3d', # External Interrupt Mask Regist + 'EIMSK_INT': '$ff', # External Interrupt Request Ena + 'EIFR' : '$3c', # External Interrupt Flag Regist + 'EIFR_INTF': '$ff', # External Interrupt Flag + 'PCMSK2' : '$6d', # Pin Change Mask Register 2 + 'PCMSK2_PCINT': '$ff', # Pin Change Enable Mask + 'PCMSK1' : '$6c', # Pin Change Mask Register 1 + 'PCMSK1_PCINT': '$ff', # Pin Change Enable Mask + 'PCMSK0' : '$6b', # Pin Change Mask Register 0 + 'PCIFR' : '$3b', # Pin Change Interrupt Flag Regi + 'PCIFR_Res': '$f8', # Reserved Bit + 'PCIFR_PCIF': '$7', # Pin Change Interrupt Flags + 'PCICR' : '$68', # Pin Change Interrupt Control R + 'PCICR_Res': '$f8', # Reserved Bit + 'PCICR_PCIE': '$7', # Pin Change Interrupt Enables + +# Module AD_CONVERTER + 'ADMUX' : '$7c', # The ADC Multiplexer Selection + 'ADMUX_REFS': '$c0', # Reference Selection Bits + 'ADMUX_ADLAR': '$20', # ADC Left Adjust Result + 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select + 'ADC' : '$78', # ADC Data Register Bytes + 'ADCSRA' : '$7a', # The ADC Control and Status Reg + 'ADCSRA_ADEN': '$80', # ADC Enable + 'ADCSRA_ADSC': '$40', # ADC Start Conversion + 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable + 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag + 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable + 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits + 'ADCSRB' : '$7b', # The ADC Control and Status Reg + 'ADCSRB_AVDDOK': '$80', # AVDD Supply Voltage OK + 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer + 'ADCSRB_REFOK': '$20', # Reference Voltage OK + 'ADCSRB_ACCH': '$10', # Analog Channel Change + 'ADCSRB_MUX5': '$8', # Analog Channel and Gain Select + 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Source + 'ADCSRC' : '$77', # The ADC Control and Status Reg + 'ADCSRC_ADTHT': '$c0', # ADC Track-and-Hold Time + 'ADCSRC_Res0': '$20', # Reserved + 'ADCSRC_ADSUT': '$1f', # ADC Start-up Time + 'DIDR2' : '$7d', # Digital Input Disable Register + 'DIDR2_ADC15D': '$80', # Reserved Bits + 'DIDR2_ADC14D': '$40', # Reserved Bits + 'DIDR2_ADC13D': '$20', # Reserved Bits + 'DIDR2_ADC12D': '$10', # Reserved Bits + 'DIDR2_ADC11D': '$8', # Reserved Bits + 'DIDR2_ADC10D': '$4', # Reserved Bits + 'DIDR2_ADC9D': '$2', # Reserved Bits + 'DIDR2_ADC8D': '$1', # Reserved Bits + 'DIDR0' : '$7e', # Digital Input Disable Register + 'DIDR0_ADC7D': '$80', # Disable ADC7:0 Digital Input + 'DIDR0_ADC6D': '$40', # Disable ADC7:0 Digital Input + 'DIDR0_ADC5D': '$20', # Disable ADC7:0 Digital Input + 'DIDR0_ADC4D': '$10', # Disable ADC7:0 Digital Input + 'DIDR0_ADC3D': '$8', # Disable ADC7:0 Digital Input + 'DIDR0_ADC2D': '$4', # Disable ADC7:0 Digital Input + 'DIDR0_ADC1D': '$2', # Disable ADC7:0 Digital Input + 'DIDR0_ADC0D': '$1', # Disable ADC7:0 Digital Input + +# Module BOOT_LOAD + 'SPMCSR' : '$57', # Store Program Memory Control R + 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable + 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy + 'SPMCSR_SIGRD': '$20', # Signature Row Read + 'SPMCSR_RWWSRE': '$10', # Read While Write Section Read + 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set + 'SPMCSR_PGWRT': '$4', # Page Write + 'SPMCSR_PGERS': '$2', # Page Erase + 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable + +# Module CPU + 'SREG' : '$5f', # Status Register + 'SREG_I': '$80', # Global Interrupt Enable + 'SREG_T': '$40', # Bit Copy Storage + 'SREG_H': '$20', # Half Carry Flag + 'SREG_S': '$10', # Sign Bit + 'SREG_V': '$8', # Two's Complement Overflow Flag + 'SREG_N': '$4', # Negative Flag + 'SREG_Z': '$2', # Zero Flag + 'SREG_C': '$1', # Carry Flag + 'SP' : '$5d', # Stack Pointer + 'MCUCR' : '$55', # MCU Control Register + 'MCUCR_JTD': '$80', # JTAG Interface Disable + 'MCUCR_Res': '$60', # Reserved + 'MCUCR_PUD': '$10', # Pull-up Disable + 'MCUCR_Res': '$c', # Reserved + 'MCUCR_IVSEL': '$2', # Interrupt Vector Select + 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable + 'MCUSR' : '$54', # MCU Status Register + 'MCUSR_Res': '$e0', # Reserved + 'MCUSR_JTRF': '$10', # JTAG Reset Flag + 'MCUSR_WDRF': '$8', # Watchdog Reset Flag + 'MCUSR_BORF': '$4', # Brown-out Reset Flag + 'MCUSR_EXTRF': '$2', # External Reset Flag + 'MCUSR_PORF': '$1', # Power-on Reset Flag + 'OSCCAL' : '$66', # Oscillator Calibration Value + 'OSCCAL_CAL': '$ff', # Oscillator Calibration Tuning + 'CLKPR' : '$61', # Clock Prescale Register + 'CLKPR_CLKPCE': '$80', # Clock Prescaler Change Enable + 'CLKPR_Res': '$70', # Reserved + 'CLKPR_CLKPS': '$f', # Clock Prescaler Select Bits + 'SMCR' : '$53', # Sleep Mode Control Register + 'SMCR_Res': '$f0', # Reserved + 'SMCR_SM': '$e', # Sleep Mode Select bits + 'SMCR_SE': '$1', # Sleep Enable + 'EIND' : '$5c', # Extended Indirect Register + 'RAMPZ' : '$5b', # Extended Z-pointer Register fo + 'RAMPZ_Res': '$fc', # Reserved + 'RAMPZ_RAMPZ': '$3', # Extended Z-Pointer Value + 'GPIOR2' : '$4b', # General Purpose I/O Register 2 + 'GPIOR2_GPIOR': '$ff', # General Purpose I/O Register 2 + 'GPIOR1' : '$4a', # General Purpose IO Register 1 + 'GPIOR1_GPIOR': '$ff', # General Purpose I/O Register 1 + 'GPIOR0' : '$3e', # General Purpose IO Register 0 + 'GPIOR0_GPIOR07': '$80', # General Purpose I/O Register 0 + 'GPIOR0_GPIOR06': '$40', # General Purpose I/O Register 0 + 'GPIOR0_GPIOR05': '$20', # General Purpose I/O Register 0 + 'GPIOR0_GPIOR04': '$10', # General Purpose I/O Register 0 + 'GPIOR0_GPIOR03': '$8', # General Purpose I/O Register 0 + 'GPIOR0_GPIOR02': '$4', # General Purpose I/O Register 0 + 'GPIOR0_GPIOR01': '$2', # General Purpose I/O Register 0 + 'GPIOR0_GPIOR00': '$1', # General Purpose I/O Register 0 + 'PRR2' : '$63', # Power Reduction Register 2 + 'PRR2_Res': '$f0', # Reserved Bit + 'PRR2_PRRAM': '$f', # Power Reduction SRAMs + 'PRR1' : '$65', # Power Reduction Register 1 + 'PRR1_Res': '$80', # Reserved Bit + 'PRR1_PRTRX24': '$40', # Power Reduction Transceiver + 'PRR1_PRTIM5': '$20', # Power Reduction Timer/Counter5 + 'PRR1_PRTIM4': '$10', # Power Reduction Timer/Counter4 + 'PRR1_PRTIM3': '$8', # Power Reduction Timer/Counter3 + 'PRR1_PRUSART1': '$1', # Power Reduction USART1 + 'PRR0' : '$64', # Power Reduction Register0 + 'PRR0_PRTWI': '$80', # Power Reduction TWI + 'PRR0_PRTIM2': '$40', # Power Reduction Timer/Counter2 + 'PRR0_PRTIM0': '$20', # Power Reduction Timer/Counter0 + 'PRR0_PRPGA': '$10', # Power Reduction PGA + 'PRR0_PRTIM1': '$8', # Power Reduction Timer/Counter1 + 'PRR0_PRSPI': '$4', # Power Reduction Serial Periphe + 'PRR0_PRUSART0': '$2', # Power Reduction USART + 'PRR0_PRADC': '$1', # Power Reduction ADC + +# Module FLASH + 'NEMCR' : '$75', # Flash Extended-Mode Control-Re + 'NEMCR_ENEAM': '$40', # Enable Extended Address Mode f + 'NEMCR_AEAM': '$30', # Address for Extended Address M + 'BGCR' : '$67', # Reference Voltage Calibration + 'BGCR_Res': '$80', # Reserved Bit + 'BGCR_BGCAL_FINE': '$78', # Fine Calibration Bits + 'BGCR_BGCAL': '$7', # Coarse Calibration Bits + +# Module PWRCTRL + 'TRXPR' : '$139', # Transceiver Pin Register + 'TRXPR_Res': '$f0', # Reserved + 'TRXPR_SLPTR': '$2', # Multi-purpose Transceiver Cont + 'TRXPR_TRXRST': '$1', # Force Transceiver Reset + 'DRTRAM0' : '$135', # Data Retention Configuration R + 'DRTRAM0_Res': '$c0', # Reserved + 'DRTRAM0_DRTSWOK': '$20', # DRT Switch OK + 'DRTRAM0_ENDRT': '$10', # Enable SRAM Data Retention + 'DRTRAM1' : '$134', # Data Retention Configuration R + 'DRTRAM1_Res': '$c0', # Reserved + 'DRTRAM1_DRTSWOK': '$20', # DRT Switch OK + 'DRTRAM1_ENDRT': '$10', # Enable SRAM Data Retention + 'DRTRAM2' : '$133', # Data Retention Configuration R + 'DRTRAM2_Res': '$40', # Reserved Bit + 'DRTRAM2_DRTSWOK': '$20', # DRT Switch OK + 'DRTRAM2_ENDRT': '$10', # Enable SRAM Data Retention + 'DRTRAM3' : '$132', # Data Retention Configuration R + 'DRTRAM3_Res': '$c0', # Reserved + 'DRTRAM3_DRTSWOK': '$20', # DRT Switch OK + 'DRTRAM3_ENDRT': '$10', # Enable SRAM Data Retention + 'LLDRL' : '$130', # Low Leakage Voltage Regulator + 'LLDRL_Res': '$f0', # Reserved + 'LLDRL_LLDRL': '$f', # Low-Byte Data Register Bits + 'LLDRH' : '$131', # Low Leakage Voltage Regulator + 'LLDRH_Res': '$e0', # Reserved + 'LLDRH_LLDRH': '$1f', # High-Byte Data Register Bits + 'LLCR' : '$12f', # Low Leakage Voltage Regulator + 'LLCR_Res': '$c0', # Reserved Bit + 'LLCR_LLDONE': '$20', # Calibration Done + 'LLCR_LLCOMP': '$10', # Comparator Output + 'LLCR_LLCAL': '$8', # Calibration Active + 'LLCR_LLTCO': '$4', # Temperature Coefficient of Cur + 'LLCR_LLSHORT': '$2', # Short Lower Calibration Circui + 'LLCR_LLENCAL': '$1', # Enable Automatic Calibration + 'DPDS0' : '$136', # Port Driver Strength Register + 'DPDS0_PFDRV': '$c0', # Driver Strength Port F + 'DPDS0_PEDRV': '$30', # Driver Strength Port E + 'DPDS0_PDDRV': '$c', # Driver Strength Port D + 'DPDS0_PBDRV': '$3', # Driver Strength Port B + 'DPDS1' : '$137', # Port Driver Strength Register + 'DPDS1_Res': '$fc', # Reserved + 'DPDS1_PGDRV': '$3', # Driver Strength Port G + 'MCUCR' : '$55', # MCU Control Register + 'MCUCR_PUD': '$10', # Pull-up Disable + +# Module USART0_SPI + 'UCSR0A' : '$c0', # USART0 MSPIM Control and Statu + 'UCSR0A_RXC0': '$80', # USART Receive Complete + 'UCSR0A_TXC0': '$40', # USART Transmit Complete + 'UCSR0A_UDRE0': '$20', # USART Data Register Empty + 'UCSR0B' : '$c1', # USART0 MSPIM Control and Statu + 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable + 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable + 'UCSR0B_UDRIE0': '$20', # USART Data Register Empty Inte + 'UCSR0B_RXEN0': '$10', # Receiver Enable + 'UCSR0B_TXEN0': '$8', # Transmitter Enable + 'UCSR0C' : '$c2', # USART0 MSPIM Control and Statu + 'UCSR0C_UDORD0': '$4', # Data Order + 'UCSR0C_UCPHA0': '$2', # Clock Phase + 'UCSR0C_UCPOL0': '$1', # Clock Polarity + +# Module USART1_SPI + 'UCSR1A' : '$c8', # USART1 MSPIM Control and Statu + 'UCSR1A_RXC1': '$80', # USART Receive Complete + 'UCSR1A_TXC1': '$40', # USART Transmit Complete + 'UCSR1A_UDRE1': '$20', # USART Data Register Empty + 'UCSR1B' : '$c9', # USART1 MSPIM Control and Statu + 'UCSR1B_RXCIE1': '$80', # RX Complete Interrupt Enable + 'UCSR1B_TXCIE1': '$40', # TX Complete Interrupt Enable + 'UCSR1B_UDRIE1': '$20', # USART Data Register Empty Inte + 'UCSR1B_RXEN1': '$10', # Receiver Enable + 'UCSR1B_TXEN1': '$8', # Transmitter Enable + 'UCSR1C' : '$ca', # USART1 MSPIM Control and Statu + 'UCSR1C_UDORD1': '$4', # Data Order + 'UCSR1C_UCPHA1': '$2', # Clock Phase + 'UCSR1C_UCPOL1': '$1', # Clock Polarity + + '__amforth_dummy':'0' +} -- cgit v1.2.3