From d80736ab6e8e3cad2f1a30c6eaba2d6883dbe967 Mon Sep 17 00:00:00 2001 From: Dimitri Sokolyuk Date: Sat, 26 Aug 2017 20:31:40 +0200 Subject: Remove AmForth --- amforth-6.5/avr8/devices/atmega640/atmega640.frt | 579 ------ amforth-6.5/avr8/devices/atmega640/device.asm | 184 -- amforth-6.5/avr8/devices/atmega640/device.inc | 1968 -------------------- amforth-6.5/avr8/devices/atmega640/device.py | 632 ------- .../avr8/devices/atmega640/words/no-jtag.asm | 14 - .../avr8/devices/atmega640/words/no-wdt.asm | 34 - amforth-6.5/avr8/devices/atmega640/words/sleep.asm | 19 - 7 files changed, 3430 deletions(-) delete mode 100644 amforth-6.5/avr8/devices/atmega640/atmega640.frt delete mode 100644 amforth-6.5/avr8/devices/atmega640/device.asm delete mode 100644 amforth-6.5/avr8/devices/atmega640/device.inc delete mode 100644 amforth-6.5/avr8/devices/atmega640/device.py delete mode 100644 amforth-6.5/avr8/devices/atmega640/words/no-jtag.asm delete mode 100644 amforth-6.5/avr8/devices/atmega640/words/no-wdt.asm delete mode 100644 amforth-6.5/avr8/devices/atmega640/words/sleep.asm (limited to 'amforth-6.5/avr8/devices/atmega640') diff --git a/amforth-6.5/avr8/devices/atmega640/atmega640.frt b/amforth-6.5/avr8/devices/atmega640/atmega640.frt deleted file mode 100644 index 2432b5b..0000000 --- a/amforth-6.5/avr8/devices/atmega640/atmega640.frt +++ /dev/null @@ -1,579 +0,0 @@ -\ Partname: ATmega640 -\ generated automatically - -\ ANALOG_COMPARATOR -&123 constant ADCSRB \ ADC Control and Status Register B - $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer Enable -&80 constant ACSR \ Analog Comparator Control And Status Register - $80 constant ACSR_ACD \ Analog Comparator Disable - $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select - $20 constant ACSR_ACO \ Analog Compare Output - $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag - $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable - $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable - $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits -&127 constant DIDR1 \ Digital Input Disable Register 1 - $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable - $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable -\ USART0 -&198 constant UDR0 \ USART I/O Data Register -&192 constant UCSR0A \ USART Control and Status Register A - $80 constant UCSR0A_RXC0 \ USART Receive Complete - $40 constant UCSR0A_TXC0 \ USART Transmitt Complete - $20 constant UCSR0A_UDRE0 \ USART Data Register Empty - $10 constant UCSR0A_FE0 \ Framing Error - $08 constant UCSR0A_DOR0 \ Data overRun - $04 constant UCSR0A_UPE0 \ Parity Error - $02 constant UCSR0A_U2X0 \ Double the USART transmission speed - $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode -&193 constant UCSR0B \ USART Control and Status Register B - $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable - $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable - $20 constant UCSR0B_UDRIE0 \ USART Data register Empty Interrupt Enable - $10 constant UCSR0B_RXEN0 \ Receiver Enable - $08 constant UCSR0B_TXEN0 \ Transmitter Enable - $04 constant UCSR0B_UCSZ02 \ Character Size - $02 constant UCSR0B_RXB80 \ Receive Data Bit 8 - $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8 -&194 constant UCSR0C \ USART Control and Status Register C - $C0 constant UCSR0C_UMSEL0 \ USART Mode Select - $30 constant UCSR0C_UPM0 \ Parity Mode Bits - $08 constant UCSR0C_USBS0 \ Stop Bit Select - $06 constant UCSR0C_UCSZ0 \ Character Size - $01 constant UCSR0C_UCPOL0 \ Clock Polarity -&196 constant UBRR0 \ USART Baud Rate Register Bytes -\ TWI -&189 constant TWAMR \ TWI (Slave) Address Mask Register - $FE constant TWAMR_TWAM \ -&184 constant TWBR \ TWI Bit Rate register -&188 constant TWCR \ TWI Control Register - $80 constant TWCR_TWINT \ TWI Interrupt Flag - $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit - $20 constant TWCR_TWSTA \ TWI Start Condition Bit - $10 constant TWCR_TWSTO \ TWI Stop Condition Bit - $08 constant TWCR_TWWC \ TWI Write Collition Flag - $04 constant TWCR_TWEN \ TWI Enable Bit - $01 constant TWCR_TWIE \ TWI Interrupt Enable -&185 constant TWSR \ TWI Status Register - $F8 constant TWSR_TWS \ TWI Status - $03 constant TWSR_TWPS \ TWI Prescaler -&187 constant TWDR \ TWI Data register -&186 constant TWAR \ TWI (Slave) Address register - $FE constant TWAR_TWA \ TWI (Slave) Address register Bits - $01 constant TWAR_TWGCE \ TWI General Call Recognition Enable Bit -\ SPI -&76 constant SPCR \ SPI Control Register - $80 constant SPCR_SPIE \ SPI Interrupt Enable - $40 constant SPCR_SPE \ SPI Enable - $20 constant SPCR_DORD \ Data Order - $10 constant SPCR_MSTR \ Master/Slave Select - $08 constant SPCR_CPOL \ Clock polarity - $04 constant SPCR_CPHA \ Clock Phase - $03 constant SPCR_SPR \ SPI Clock Rate Selects -&77 constant SPSR \ SPI Status Register - $80 constant SPSR_SPIF \ SPI Interrupt Flag - $40 constant SPSR_WCOL \ Write Collision Flag - $01 constant SPSR_SPI2X \ Double SPI Speed Bit -&78 constant SPDR \ SPI Data Register -\ PORTA -&34 constant PORTA \ Port A Data Register -&33 constant DDRA \ Port A Data Direction Register -&32 constant PINA \ Port A Input Pins -\ PORTB -&37 constant PORTB \ Port B Data Register -&36 constant DDRB \ Port B Data Direction Register -&35 constant PINB \ Port B Input Pins -\ PORTC -&40 constant PORTC \ Port C Data Register -&39 constant DDRC \ Port C Data Direction Register -&38 constant PINC \ Port C Input Pins -\ PORTD -&43 constant PORTD \ Port D Data Register -&42 constant DDRD \ Port D Data Direction Register -&41 constant PIND \ Port D Input Pins -\ PORTE -&46 constant PORTE \ Data Register, Port E -&45 constant DDRE \ Data Direction Register, Port E -&44 constant PINE \ Input Pins, Port E -\ PORTF -&49 constant PORTF \ Data Register, Port F -&48 constant DDRF \ Data Direction Register, Port F -&47 constant PINF \ Input Pins, Port F -\ PORTG -&52 constant PORTG \ Data Register, Port G -&51 constant DDRG \ Data Direction Register, Port G -&50 constant PING \ Input Pins, Port G -\ PORTH -&258 constant PORTH \ PORT H Data Register -&257 constant DDRH \ PORT H Data Direction Register -&256 constant PINH \ PORT H Input Pins -\ PORTJ -&261 constant PORTJ \ PORT J Data Register -&260 constant DDRJ \ PORT J Data Direction Register -&259 constant PINJ \ PORT J Input Pins -\ PORTK -&264 constant PORTK \ PORT K Data Register -&263 constant DDRK \ PORT K Data Direction Register -&262 constant PINK \ PORT K Input Pins -\ PORTL -&267 constant PORTL \ PORT L Data Register -&266 constant DDRL \ PORT L Data Direction Register -&265 constant PINL \ PORT L Input Pins -\ TIMER_COUNTER_0 -&72 constant OCR0B \ Timer/Counter0 Output Compare Register -&71 constant OCR0A \ Timer/Counter0 Output Compare Register -&70 constant TCNT0 \ Timer/Counter0 -&69 constant TCCR0B \ Timer/Counter Control Register B - $80 constant TCCR0B_FOC0A \ Force Output Compare A - $40 constant TCCR0B_FOC0B \ Force Output Compare B - $08 constant TCCR0B_WGM02 \ - $07 constant TCCR0B_CS0 \ Clock Select -&68 constant TCCR0A \ Timer/Counter Control Register A - $C0 constant TCCR0A_COM0A \ Compare Output Mode, Phase Correct PWM Mode - $30 constant TCCR0A_COM0B \ Compare Output Mode, Fast PWm - $03 constant TCCR0A_WGM0 \ Waveform Generation Mode -&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register - $04 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare Match B Interrupt Enable - $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match A Interrupt Enable - $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable -&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register - $04 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare Flag 0B - $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0A - $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag -&67 constant GTCCR \ General Timer/Counter Control Register - $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode - $01 constant GTCCR_PSRSYNC \ Prescaler Reset Timer/Counter1 and Timer/Counter0 -\ TIMER_COUNTER_2 -&112 constant TIMSK2 \ Timer/Counter Interrupt Mask register - $04 constant TIMSK2_OCIE2B \ Timer/Counter2 Output Compare Match B Interrupt Enable - $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match A Interrupt Enable - $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable -&55 constant TIFR2 \ Timer/Counter Interrupt Flag Register - $04 constant TIFR2_OCF2B \ Output Compare Flag 2B - $02 constant TIFR2_OCF2A \ Output Compare Flag 2A - $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag -&176 constant TCCR2A \ Timer/Counter2 Control Register A - $C0 constant TCCR2A_COM2A \ Compare Output Mode bits - $30 constant TCCR2A_COM2B \ Compare Output Mode bits - $03 constant TCCR2A_WGM2 \ Waveform Genration Mode -&177 constant TCCR2B \ Timer/Counter2 Control Register B - $80 constant TCCR2B_FOC2A \ Force Output Compare A - $40 constant TCCR2B_FOC2B \ Force Output Compare B - $08 constant TCCR2B_WGM22 \ Waveform Generation Mode - $07 constant TCCR2B_CS2 \ Clock Select bits -&178 constant TCNT2 \ Timer/Counter2 -&180 constant OCR2B \ Timer/Counter2 Output Compare Register B -&179 constant OCR2A \ Timer/Counter2 Output Compare Register A -&182 constant ASSR \ Asynchronous Status Register - $40 constant ASSR_EXCLK \ Enable External Clock Input - $20 constant ASSR_AS2 \ Asynchronous Timer/Counter2 - $10 constant ASSR_TCN2UB \ Timer/Counter2 Update Busy - $08 constant ASSR_OCR2AUB \ Output Compare Register2 Update Busy - $04 constant ASSR_OCR2BUB \ Output Compare Register 2 Update Busy - $02 constant ASSR_TCR2AUB \ Timer/Counter Control Register2 Update Busy - $01 constant ASSR_TCR2BUB \ Timer/Counter Control Register2 Update Busy -\ WATCHDOG -&96 constant WDTCSR \ Watchdog Timer Control Register - $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Flag - $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Enable - $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits - $10 constant WDTCSR_WDCE \ Watchdog Change Enable - $08 constant WDTCSR_WDE \ Watch Dog Enable -\ USART1 -&206 constant UDR1 \ USART I/O Data Register -&200 constant UCSR1A \ USART Control and Status Register A - $80 constant UCSR1A_RXC1 \ USART Receive Complete - $40 constant UCSR1A_TXC1 \ USART Transmitt Complete - $20 constant UCSR1A_UDRE1 \ USART Data Register Empty - $10 constant UCSR1A_FE1 \ Framing Error - $08 constant UCSR1A_DOR1 \ Data overRun - $04 constant UCSR1A_UPE1 \ Parity Error - $02 constant UCSR1A_U2X1 \ Double the USART transmission speed - $01 constant UCSR1A_MPCM1 \ Multi-processor Communication Mode -&201 constant UCSR1B \ USART Control and Status Register B - $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable - $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable - $20 constant UCSR1B_UDRIE1 \ USART Data register Empty Interrupt Enable - $10 constant UCSR1B_RXEN1 \ Receiver Enable - $08 constant UCSR1B_TXEN1 \ Transmitter Enable - $04 constant UCSR1B_UCSZ12 \ Character Size - $02 constant UCSR1B_RXB81 \ Receive Data Bit 8 - $01 constant UCSR1B_TXB81 \ Transmit Data Bit 8 -&202 constant UCSR1C \ USART Control and Status Register C - $C0 constant UCSR1C_UMSEL1 \ USART Mode Select - $30 constant UCSR1C_UPM1 \ Parity Mode Bits - $08 constant UCSR1C_USBS1 \ Stop Bit Select - $06 constant UCSR1C_UCSZ1 \ Character Size - $01 constant UCSR1C_UCPOL1 \ Clock Polarity -&204 constant UBRR1 \ USART Baud Rate Register Bytes -\ EEPROM -&65 constant EEAR \ EEPROM Address Register Low Bytes -&64 constant EEDR \ EEPROM Data Register -&63 constant EECR \ EEPROM Control Register - $30 constant EECR_EEPM \ EEPROM Programming Mode Bits - $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable - $04 constant EECR_EEMPE \ EEPROM Master Write Enable - $02 constant EECR_EEPE \ EEPROM Write Enable - $01 constant EECR_EERE \ EEPROM Read Enable -\ TIMER_COUNTER_5 -&288 constant TCCR5A \ Timer/Counter5 Control Register A - $C0 constant TCCR5A_COM5A \ Compare Output Mode 1A, bits - $30 constant TCCR5A_COM5B \ Compare Output Mode 5B, bits - $0C constant TCCR5A_COM5C \ Compare Output Mode 5C, bits - $03 constant TCCR5A_WGM5 \ Waveform Generation Mode -&289 constant TCCR5B \ Timer/Counter5 Control Register B - $80 constant TCCR5B_ICNC5 \ Input Capture 5 Noise Canceler - $40 constant TCCR5B_ICES5 \ Input Capture 5 Edge Select - $18 constant TCCR5B_WGM5 \ Waveform Generation Mode - $07 constant TCCR5B_CS5 \ Prescaler source of Timer/Counter 5 -&290 constant TCCR5C \ Timer/Counter 5 Control Register C - $80 constant TCCR5C_FOC5A \ Force Output Compare 5A - $40 constant TCCR5C_FOC5B \ Force Output Compare 5B - $20 constant TCCR5C_FOC5C \ Force Output Compare 5C -&292 constant TCNT5 \ Timer/Counter5 Bytes -&296 constant OCR5A \ Timer/Counter5 Output Compare Register A Bytes -&298 constant OCR5B \ Timer/Counter5 Output Compare Register B Bytes -&300 constant OCR5C \ Timer/Counter5 Output Compare Register B Bytes -&294 constant ICR5 \ Timer/Counter5 Input Capture Register Bytes -&115 constant TIMSK5 \ Timer/Counter5 Interrupt Mask Register - $20 constant TIMSK5_ICIE5 \ Timer/Counter5 Input Capture Interrupt Enable - $08 constant TIMSK5_OCIE5C \ Timer/Counter5 Output Compare C Match Interrupt Enable - $04 constant TIMSK5_OCIE5B \ Timer/Counter5 Output Compare B Match Interrupt Enable - $02 constant TIMSK5_OCIE5A \ Timer/Counter5 Output Compare A Match Interrupt Enable - $01 constant TIMSK5_TOIE5 \ Timer/Counter5 Overflow Interrupt Enable -&58 constant TIFR5 \ Timer/Counter5 Interrupt Flag register - $20 constant TIFR5_ICF5 \ Input Capture Flag 5 - $08 constant TIFR5_OCF5C \ Output Compare Flag 5C - $04 constant TIFR5_OCF5B \ Output Compare Flag 5B - $02 constant TIFR5_OCF5A \ Output Compare Flag 5A - $01 constant TIFR5_TOV5 \ Timer/Counter5 Overflow Flag -\ TIMER_COUNTER_4 -&160 constant TCCR4A \ Timer/Counter4 Control Register A - $C0 constant TCCR4A_COM4A \ Compare Output Mode 1A, bits - $30 constant TCCR4A_COM4B \ Compare Output Mode 4B, bits - $0C constant TCCR4A_COM4C \ Compare Output Mode 4C, bits - $03 constant TCCR4A_WGM4 \ Waveform Generation Mode -&161 constant TCCR4B \ Timer/Counter4 Control Register B - $80 constant TCCR4B_ICNC4 \ Input Capture 4 Noise Canceler - $40 constant TCCR4B_ICES4 \ Input Capture 4 Edge Select - $18 constant TCCR4B_WGM4 \ Waveform Generation Mode - $07 constant TCCR4B_CS4 \ Prescaler source of Timer/Counter 4 -&162 constant TCCR4C \ Timer/Counter 4 Control Register C - $80 constant TCCR4C_FOC4A \ Force Output Compare 4A - $40 constant TCCR4C_FOC4B \ Force Output Compare 4B - $20 constant TCCR4C_FOC4C \ Force Output Compare 4C -&164 constant TCNT4 \ Timer/Counter4 Bytes -&168 constant OCR4A \ Timer/Counter4 Output Compare Register A Bytes -&170 constant OCR4B \ Timer/Counter4 Output Compare Register B Bytes -&172 constant OCR4C \ Timer/Counter4 Output Compare Register B Bytes -&166 constant ICR4 \ Timer/Counter4 Input Capture Register Bytes -&114 constant TIMSK4 \ Timer/Counter4 Interrupt Mask Register - $20 constant TIMSK4_ICIE4 \ Timer/Counter4 Input Capture Interrupt Enable - $08 constant TIMSK4_OCIE4C \ Timer/Counter4 Output Compare C Match Interrupt Enable - $04 constant TIMSK4_OCIE4B \ Timer/Counter4 Output Compare B Match Interrupt Enable - $02 constant TIMSK4_OCIE4A \ Timer/Counter4 Output Compare A Match Interrupt Enable - $01 constant TIMSK4_TOIE4 \ Timer/Counter4 Overflow Interrupt Enable -&57 constant TIFR4 \ Timer/Counter4 Interrupt Flag register - $20 constant TIFR4_ICF4 \ Input Capture Flag 4 - $08 constant TIFR4_OCF4C \ Output Compare Flag 4C - $04 constant TIFR4_OCF4B \ Output Compare Flag 4B - $02 constant TIFR4_OCF4A \ Output Compare Flag 4A - $01 constant TIFR4_TOV4 \ Timer/Counter4 Overflow Flag -\ TIMER_COUNTER_3 -&144 constant TCCR3A \ Timer/Counter3 Control Register A - $C0 constant TCCR3A_COM3A \ Compare Output Mode 1A, bits - $30 constant TCCR3A_COM3B \ Compare Output Mode 3B, bits - $0C constant TCCR3A_COM3C \ Compare Output Mode 3C, bits - $03 constant TCCR3A_WGM3 \ Waveform Generation Mode -&145 constant TCCR3B \ Timer/Counter3 Control Register B - $80 constant TCCR3B_ICNC3 \ Input Capture 3 Noise Canceler - $40 constant TCCR3B_ICES3 \ Input Capture 3 Edge Select - $18 constant TCCR3B_WGM3 \ Waveform Generation Mode - $07 constant TCCR3B_CS3 \ Prescaler source of Timer/Counter 3 -&146 constant TCCR3C \ Timer/Counter 3 Control Register C - $80 constant TCCR3C_FOC3A \ Force Output Compare 3A - $40 constant TCCR3C_FOC3B \ Force Output Compare 3B - $20 constant TCCR3C_FOC3C \ Force Output Compare 3C -&148 constant TCNT3 \ Timer/Counter3 Bytes -&152 constant OCR3A \ Timer/Counter3 Output Compare Register A Bytes -&154 constant OCR3B \ Timer/Counter3 Output Compare Register B Bytes -&156 constant OCR3C \ Timer/Counter3 Output Compare Register B Bytes -&150 constant ICR3 \ Timer/Counter3 Input Capture Register Bytes -&113 constant TIMSK3 \ Timer/Counter3 Interrupt Mask Register - $20 constant TIMSK3_ICIE3 \ Timer/Counter3 Input Capture Interrupt Enable - $08 constant TIMSK3_OCIE3C \ Timer/Counter3 Output Compare C Match Interrupt Enable - $04 constant TIMSK3_OCIE3B \ Timer/Counter3 Output Compare B Match Interrupt Enable - $02 constant TIMSK3_OCIE3A \ Timer/Counter3 Output Compare A Match Interrupt Enable - $01 constant TIMSK3_TOIE3 \ Timer/Counter3 Overflow Interrupt Enable -&56 constant TIFR3 \ Timer/Counter3 Interrupt Flag register - $20 constant TIFR3_ICF3 \ Input Capture Flag 3 - $08 constant TIFR3_OCF3C \ Output Compare Flag 3C - $04 constant TIFR3_OCF3B \ Output Compare Flag 3B - $02 constant TIFR3_OCF3A \ Output Compare Flag 3A - $01 constant TIFR3_TOV3 \ Timer/Counter3 Overflow Flag -\ TIMER_COUNTER_1 -&128 constant TCCR1A \ Timer/Counter1 Control Register A - $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits - $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits - $0C constant TCCR1A_COM1C \ Compare Output Mode 1C, bits - $03 constant TCCR1A_WGM1 \ Waveform Generation Mode -&129 constant TCCR1B \ Timer/Counter1 Control Register B - $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler - $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select - $18 constant TCCR1B_WGM1 \ Waveform Generation Mode - $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1 -&130 constant TCCR1C \ Timer/Counter 1 Control Register C - $80 constant TCCR1C_FOC1A \ Force Output Compare 1A - $40 constant TCCR1C_FOC1B \ Force Output Compare 1B - $20 constant TCCR1C_FOC1C \ Force Output Compare 1C -&132 constant TCNT1 \ Timer/Counter1 Bytes -&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes -&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes -&140 constant OCR1C \ Timer/Counter1 Output Compare Register C Bytes -&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes -&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register - $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable - $08 constant TIMSK1_OCIE1C \ Timer/Counter1 Output Compare C Match Interrupt Enable - $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable - $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable - $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable -&54 constant TIFR1 \ Timer/Counter1 Interrupt Flag register - $20 constant TIFR1_ICF1 \ Input Capture Flag 1 - $08 constant TIFR1_OCF1C \ Output Compare Flag 1C - $04 constant TIFR1_OCF1B \ Output Compare Flag 1B - $02 constant TIFR1_OCF1A \ Output Compare Flag 1A - $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag -\ JTAG -&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory -&85 constant MCUCR \ MCU Control Register - $80 constant MCUCR_JTD \ JTAG Interface Disable -&84 constant MCUSR \ MCU Status Register - $10 constant MCUSR_JTRF \ JTAG Reset Flag -\ EXTERNAL_INTERRUPT -&105 constant EICRA \ External Interrupt Control Register A - $C0 constant EICRA_ISC3 \ External Interrupt Sense Control Bit - $30 constant EICRA_ISC2 \ External Interrupt Sense Control Bit - $0C constant EICRA_ISC1 \ External Interrupt Sense Control Bit - $03 constant EICRA_ISC0 \ External Interrupt Sense Control Bit -&106 constant EICRB \ External Interrupt Control Register B - $C0 constant EICRB_ISC7 \ External Interrupt 7-4 Sense Control Bit - $30 constant EICRB_ISC6 \ External Interrupt 7-4 Sense Control Bit - $0C constant EICRB_ISC5 \ External Interrupt 7-4 Sense Control Bit - $03 constant EICRB_ISC4 \ External Interrupt 7-4 Sense Control Bit -&61 constant EIMSK \ External Interrupt Mask Register - $FF constant EIMSK_INT \ External Interrupt Request 7 Enable -&60 constant EIFR \ External Interrupt Flag Register - $FF constant EIFR_INTF \ External Interrupt Flags -&109 constant PCMSK2 \ Pin Change Mask Register 2 -&108 constant PCMSK1 \ Pin Change Mask Register 1 -&107 constant PCMSK0 \ Pin Change Mask Register 0 -&59 constant PCIFR \ Pin Change Interrupt Flag Register - $07 constant PCIFR_PCIF \ Pin Change Interrupt Flags -&104 constant PCICR \ Pin Change Interrupt Control Register - $07 constant PCICR_PCIE \ Pin Change Interrupt Enables -\ CPU -&95 constant SREG \ Status Register - $80 constant SREG_I \ Global Interrupt Enable - $40 constant SREG_T \ Bit Copy Storage - $20 constant SREG_H \ Half Carry Flag - $10 constant SREG_S \ Sign Bit - $08 constant SREG_V \ Two's Complement Overflow Flag - $04 constant SREG_N \ Negative Flag - $02 constant SREG_Z \ Zero Flag - $01 constant SREG_C \ Carry Flag -&93 constant SP \ Stack Pointer -&116 constant XMCRA \ External Memory Control Register A - $80 constant XMCRA_SRE \ External SRAM Enable - $70 constant XMCRA_SRL \ Wait state page limit - $0C constant XMCRA_SRW1 \ Wait state select bit upper page - $03 constant XMCRA_SRW0 \ Wait state select bit lower page -&117 constant XMCRB \ External Memory Control Register B - $80 constant XMCRB_XMBK \ External Memory Bus Keeper Enable - $07 constant XMCRB_XMM \ External Memory High Mask -&102 constant OSCCAL \ Oscillator Calibration Value -&97 constant CLKPR \ - $80 constant CLKPR_CLKPCE \ - $0F constant CLKPR_CLKPS \ -&83 constant SMCR \ Sleep Mode Control Register - $0E constant SMCR_SM \ Sleep Mode Select bits - $01 constant SMCR_SE \ Sleep Enable -&92 constant EIND \ Extended Indirect Register -&75 constant GPIOR2 \ General Purpose IO Register 2 - $FF constant GPIOR2_GPIOR \ General Purpose IO Register 2 bis -&74 constant GPIOR1 \ General Purpose IO Register 1 - $FF constant GPIOR1_GPIOR \ General Purpose IO Register 1 bis -&62 constant GPIOR0 \ General Purpose IO Register 0 - $80 constant GPIOR0_GPIOR07 \ General Purpose IO Register 0 bit 7 - $40 constant GPIOR0_GPIOR06 \ General Purpose IO Register 0 bit 6 - $20 constant GPIOR0_GPIOR05 \ General Purpose IO Register 0 bit 5 - $10 constant GPIOR0_GPIOR04 \ General Purpose IO Register 0 bit 4 - $08 constant GPIOR0_GPIOR03 \ General Purpose IO Register 0 bit 3 - $04 constant GPIOR0_GPIOR02 \ General Purpose IO Register 0 bit 2 - $02 constant GPIOR0_GPIOR01 \ General Purpose IO Register 0 bit 1 - $01 constant GPIOR0_GPIOR00 \ General Purpose IO Register 0 bit 0 -&101 constant PRR1 \ Power Reduction Register1 - $20 constant PRR1_PRTIM5 \ Power Reduction Timer/Counter5 - $10 constant PRR1_PRTIM4 \ Power Reduction Timer/Counter4 - $08 constant PRR1_PRTIM3 \ Power Reduction Timer/Counter3 - $07 constant PRR1_PRUSART \ Power Reduction USART3 -&100 constant PRR0 \ Power Reduction Register0 - $80 constant PRR0_PRTWI \ Power Reduction TWI - $40 constant PRR0_PRTIM2 \ Power Reduction Timer/Counter2 - $20 constant PRR0_PRTIM0 \ Power Reduction Timer/Counter0 - $08 constant PRR0_PRTIM1 \ Power Reduction Timer/Counter1 - $04 constant PRR0_PRSPI \ Power Reduction Serial Peripheral Interface - $02 constant PRR0_PRUSART0 \ Power Reduction USART - $01 constant PRR0_PRADC \ Power Reduction ADC -\ AD_CONVERTER -&124 constant ADMUX \ The ADC multiplexer Selection Register - $C0 constant ADMUX_REFS \ Reference Selection Bits - $20 constant ADMUX_ADLAR \ Left Adjust Result - $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits -&120 constant ADC \ ADC Data Register Bytes -&122 constant ADCSRA \ The ADC Control and Status register A - $80 constant ADCSRA_ADEN \ ADC Enable - $40 constant ADCSRA_ADSC \ ADC Start Conversion - $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable - $10 constant ADCSRA_ADIF \ ADC Interrupt Flag - $08 constant ADCSRA_ADIE \ ADC Interrupt Enable - $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits -&125 constant DIDR2 \ Digital Input Disable Register - $80 constant DIDR2_ADC15D \ - $40 constant DIDR2_ADC14D \ - $20 constant DIDR2_ADC13D \ - $10 constant DIDR2_ADC12D \ - $08 constant DIDR2_ADC11D \ - $04 constant DIDR2_ADC10D \ - $02 constant DIDR2_ADC9D \ - $01 constant DIDR2_ADC8D \ -&126 constant DIDR0 \ Digital Input Disable Register - $80 constant DIDR0_ADC7D \ - $40 constant DIDR0_ADC6D \ - $20 constant DIDR0_ADC5D \ - $10 constant DIDR0_ADC4D \ - $08 constant DIDR0_ADC3D \ - $04 constant DIDR0_ADC2D \ - $02 constant DIDR0_ADC1D \ - $01 constant DIDR0_ADC0D \ -\ BOOT_LOAD -&87 constant SPMCSR \ Store Program Memory Control Register - $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable - $40 constant SPMCSR_RWWSB \ Read While Write Section Busy - $20 constant SPMCSR_SIGRD \ Signature Row Read - $10 constant SPMCSR_RWWSRE \ Read While Write section read enable - $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set - $04 constant SPMCSR_PGWRT \ Page Write - $02 constant SPMCSR_PGERS \ Page Erase - $01 constant SPMCSR_SPMEN \ Store Program Memory Enable -\ USART2 -&214 constant UDR2 \ USART I/O Data Register -&208 constant UCSR2A \ USART Control and Status Register A - $80 constant UCSR2A_RXC2 \ USART Receive Complete - $40 constant UCSR2A_TXC2 \ USART Transmitt Complete - $20 constant UCSR2A_UDRE2 \ USART Data Register Empty - $10 constant UCSR2A_FE2 \ Framing Error - $08 constant UCSR2A_DOR2 \ Data overRun - $04 constant UCSR2A_UPE2 \ Parity Error - $02 constant UCSR2A_U2X2 \ Double the USART transmission speed - $01 constant UCSR2A_MPCM2 \ Multi-processor Communication Mode -&209 constant UCSR2B \ USART Control and Status Register B - $80 constant UCSR2B_RXCIE2 \ RX Complete Interrupt Enable - $40 constant UCSR2B_TXCIE2 \ TX Complete Interrupt Enable - $20 constant UCSR2B_UDRIE2 \ USART Data register Empty Interrupt Enable - $10 constant UCSR2B_RXEN2 \ Receiver Enable - $08 constant UCSR2B_TXEN2 \ Transmitter Enable - $04 constant UCSR2B_UCSZ22 \ Character Size - $02 constant UCSR2B_RXB82 \ Receive Data Bit 8 - $01 constant UCSR2B_TXB82 \ Transmit Data Bit 8 -&210 constant UCSR2C \ USART Control and Status Register C - $C0 constant UCSR2C_UMSEL2 \ USART Mode Select - $30 constant UCSR2C_UPM2 \ Parity Mode Bits - $08 constant UCSR2C_USBS2 \ Stop Bit Select - $06 constant UCSR2C_UCSZ2 \ Character Size - $01 constant UCSR2C_UCPOL2 \ Clock Polarity -&212 constant UBRR2 \ USART Baud Rate Register Bytes -\ USART3 -&310 constant UDR3 \ USART I/O Data Register -&304 constant UCSR3A \ USART Control and Status Register A - $80 constant UCSR3A_RXC3 \ USART Receive Complete - $40 constant UCSR3A_TXC3 \ USART Transmitt Complete - $20 constant UCSR3A_UDRE3 \ USART Data Register Empty - $10 constant UCSR3A_FE3 \ Framing Error - $08 constant UCSR3A_DOR3 \ Data overRun - $04 constant UCSR3A_UPE3 \ Parity Error - $02 constant UCSR3A_U2X3 \ Double the USART transmission speed - $01 constant UCSR3A_MPCM3 \ Multi-processor Communication Mode -&305 constant UCSR3B \ USART Control and Status Register B - $80 constant UCSR3B_RXCIE3 \ RX Complete Interrupt Enable - $40 constant UCSR3B_TXCIE3 \ TX Complete Interrupt Enable - $20 constant UCSR3B_UDRIE3 \ USART Data register Empty Interrupt Enable - $10 constant UCSR3B_RXEN3 \ Receiver Enable - $08 constant UCSR3B_TXEN3 \ Transmitter Enable - $04 constant UCSR3B_UCSZ32 \ Character Size - $02 constant UCSR3B_RXB83 \ Receive Data Bit 8 - $01 constant UCSR3B_TXB83 \ Transmit Data Bit 8 -&306 constant UCSR3C \ USART Control and Status Register C - $C0 constant UCSR3C_UMSEL3 \ USART Mode Select - $30 constant UCSR3C_UPM3 \ Parity Mode Bits - $08 constant UCSR3C_USBS3 \ Stop Bit Select - $06 constant UCSR3C_UCSZ3 \ Character Size - $01 constant UCSR3C_UCPOL3 \ Clock Polarity -&308 constant UBRR3 \ USART Baud Rate Register Bytes - -\ Interrupts -&2 constant INT0Addr \ External Interrupt Request 0 -&4 constant INT1Addr \ External Interrupt Request 1 -&6 constant INT2Addr \ External Interrupt Request 2 -&8 constant INT3Addr \ External Interrupt Request 3 -&10 constant INT4Addr \ External Interrupt Request 4 -&12 constant INT5Addr \ External Interrupt Request 5 -&14 constant INT6Addr \ External Interrupt Request 6 -&16 constant INT7Addr \ External Interrupt Request 7 -&18 constant PCINT0Addr \ Pin Change Interrupt Request 0 -&20 constant PCINT1Addr \ Pin Change Interrupt Request 1 -&22 constant PCINT2Addr \ Pin Change Interrupt Request 2 -&24 constant WDTAddr \ Watchdog Time-out Interrupt -&26 constant TIMER2_COMPAAddr \ Timer/Counter2 Compare Match A -&28 constant TIMER2_COMPBAddr \ Timer/Counter2 Compare Match B -&30 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow -&32 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event -&34 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A -&36 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B -&38 constant TIMER1_COMPCAddr \ Timer/Counter1 Compare Match C -&40 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow -&42 constant TIMER0_COMPAAddr \ Timer/Counter0 Compare Match A -&44 constant TIMER0_COMPBAddr \ Timer/Counter0 Compare Match B -&46 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow -&48 constant SPI__STCAddr \ SPI Serial Transfer Complete -&50 constant USART0__RXAddr \ USART0, Rx Complete -&52 constant USART0__UDREAddr \ USART0 Data register Empty -&54 constant USART0__TXAddr \ USART0, Tx Complete -&56 constant ANALOG_COMPAddr \ Analog Comparator -&58 constant ADCAddr \ ADC Conversion Complete -&60 constant EE_READYAddr \ EEPROM Ready -&62 constant TIMER3_CAPTAddr \ Timer/Counter3 Capture Event -&64 constant TIMER3_COMPAAddr \ Timer/Counter3 Compare Match A -&66 constant TIMER3_COMPBAddr \ Timer/Counter3 Compare Match B -&68 constant TIMER3_COMPCAddr \ Timer/Counter3 Compare Match C -&70 constant TIMER3_OVFAddr \ Timer/Counter3 Overflow -&72 constant USART1__RXAddr \ USART1, Rx Complete -&74 constant USART1__UDREAddr \ USART1 Data register Empty -&76 constant USART1__TXAddr \ USART1, Tx Complete -&78 constant TWIAddr \ 2-wire Serial Interface -&80 constant SPM_READYAddr \ Store Program Memory Read -&82 constant TIMER4_CAPTAddr \ Timer/Counter4 Capture Event -&84 constant TIMER4_COMPAAddr \ Timer/Counter4 Compare Match A -&86 constant TIMER4_COMPBAddr \ Timer/Counter4 Compare Match B -&88 constant TIMER4_COMPCAddr \ Timer/Counter4 Compare Match C -&90 constant TIMER4_OVFAddr \ Timer/Counter4 Overflow -&92 constant TIMER5_CAPTAddr \ Timer/Counter5 Capture Event -&94 constant TIMER5_COMPAAddr \ Timer/Counter5 Compare Match A -&96 constant TIMER5_COMPBAddr \ Timer/Counter5 Compare Match B -&98 constant TIMER5_COMPCAddr \ Timer/Counter5 Compare Match C -&100 constant TIMER5_OVFAddr \ Timer/Counter5 Overflow -&102 constant USART2__RXAddr \ USART2, Rx Complete -&104 constant USART2__UDREAddr \ USART2 Data register Empty -&106 constant USART2__TXAddr \ USART2, Tx Complete -&108 constant USART3__RXAddr \ USART3, Rx Complete -&110 constant USART3__UDREAddr \ USART3 Data register Empty -&112 constant USART3__TXAddr \ USART3, Tx Complete diff --git a/amforth-6.5/avr8/devices/atmega640/device.asm b/amforth-6.5/avr8/devices/atmega640/device.asm deleted file mode 100644 index 32d7b10..0000000 --- a/amforth-6.5/avr8/devices/atmega640/device.asm +++ /dev/null @@ -1,184 +0,0 @@ -; Partname: ATmega640 -; generated automatically, do not edit - -.nolist - .include "m640def.inc" -.list - -.equ ramstart = 512 -.equ CELLSIZE = 2 -.macro readflashcell - lsl zl - rol zh - lpm @0, Z+ - lpm @1, Z+ -.endmacro -.macro writeflashcell - lsl zl - rol zh -.endmacro -.set WANT_ANALOG_COMPARATOR = 0 -.set WANT_USART0 = 0 -.set WANT_TWI = 0 -.set WANT_SPI = 0 -.set WANT_PORTA = 0 -.set WANT_PORTB = 0 -.set WANT_PORTC = 0 -.set WANT_PORTD = 0 -.set WANT_PORTE = 0 -.set WANT_PORTF = 0 -.set WANT_PORTG = 0 -.set WANT_PORTH = 0 -.set WANT_PORTJ = 0 -.set WANT_PORTK = 0 -.set WANT_PORTL = 0 -.set WANT_TIMER_COUNTER_0 = 0 -.set WANT_TIMER_COUNTER_2 = 0 -.set WANT_WATCHDOG = 0 -.set WANT_USART1 = 0 -.set WANT_EEPROM = 0 -.set WANT_TIMER_COUNTER_5 = 0 -.set WANT_TIMER_COUNTER_4 = 0 -.set WANT_TIMER_COUNTER_3 = 0 -.set WANT_TIMER_COUNTER_1 = 0 -.set WANT_JTAG = 0 -.set WANT_EXTERNAL_INTERRUPT = 0 -.set WANT_CPU = 0 -.set WANT_AD_CONVERTER = 0 -.set WANT_BOOT_LOAD = 0 -.set WANT_USART2 = 0 -.set WANT_USART3 = 0 -.equ intvecsize = 2 ; please verify; flash size: 65536 bytes -.equ pclen = 2 ; please verify -.overlap -.org 2 - rcall isr ; External Interrupt Request 0 -.org 4 - rcall isr ; External Interrupt Request 1 -.org 6 - rcall isr ; External Interrupt Request 2 -.org 8 - rcall isr ; External Interrupt Request 3 -.org 10 - rcall isr ; External Interrupt Request 4 -.org 12 - rcall isr ; External Interrupt Request 5 -.org 14 - rcall isr ; External Interrupt Request 6 -.org 16 - rcall isr ; External Interrupt Request 7 -.org 18 - rcall isr ; Pin Change Interrupt Request 0 -.org 20 - rcall isr ; Pin Change Interrupt Request 1 -.org 22 - rcall isr ; Pin Change Interrupt Request 2 -.org 24 - rcall isr ; Watchdog Time-out Interrupt -.org 26 - rcall isr ; Timer/Counter2 Compare Match A -.org 28 - rcall isr ; Timer/Counter2 Compare Match B -.org 30 - rcall isr ; Timer/Counter2 Overflow -.org 32 - rcall isr ; Timer/Counter1 Capture Event -.org 34 - rcall isr ; Timer/Counter1 Compare Match A -.org 36 - rcall isr ; Timer/Counter1 Compare Match B -.org 38 - rcall isr ; Timer/Counter1 Compare Match C -.org 40 - rcall isr ; Timer/Counter1 Overflow -.org 42 - rcall isr ; Timer/Counter0 Compare Match A -.org 44 - rcall isr ; Timer/Counter0 Compare Match B -.org 46 - rcall isr ; Timer/Counter0 Overflow -.org 48 - rcall isr ; SPI Serial Transfer Complete -.org 50 - rcall isr ; USART0, Rx Complete -.org 52 - rcall isr ; USART0 Data register Empty -.org 54 - rcall isr ; USART0, Tx Complete -.org 56 - rcall isr ; Analog Comparator -.org 58 - rcall isr ; ADC Conversion Complete -.org 60 - rcall isr ; EEPROM Ready -.org 62 - rcall isr ; Timer/Counter3 Capture Event -.org 64 - rcall isr ; Timer/Counter3 Compare Match A -.org 66 - rcall isr ; Timer/Counter3 Compare Match B -.org 68 - rcall isr ; Timer/Counter3 Compare Match C -.org 70 - rcall isr ; Timer/Counter3 Overflow -.org 72 - rcall isr ; USART1, Rx Complete -.org 74 - rcall isr ; USART1 Data register Empty -.org 76 - rcall isr ; USART1, Tx Complete -.org 78 - rcall isr ; 2-wire Serial Interface -.org 80 - rcall isr ; Store Program Memory Read -.org 82 - rcall isr ; Timer/Counter4 Capture Event -.org 84 - rcall isr ; Timer/Counter4 Compare Match A -.org 86 - rcall isr ; Timer/Counter4 Compare Match B -.org 88 - rcall isr ; Timer/Counter4 Compare Match C -.org 90 - rcall isr ; Timer/Counter4 Overflow -.org 92 - rcall isr ; Timer/Counter5 Capture Event -.org 94 - rcall isr ; Timer/Counter5 Compare Match A -.org 96 - rcall isr ; Timer/Counter5 Compare Match B -.org 98 - rcall isr ; Timer/Counter5 Compare Match C -.org 100 - rcall isr ; Timer/Counter5 Overflow -.org 102 - rcall isr ; USART2, Rx Complete -.org 104 - rcall isr ; USART2 Data register Empty -.org 106 - rcall isr ; USART2, Tx Complete -.org 108 - rcall isr ; USART3, Rx Complete -.org 110 - rcall isr ; USART3 Data register Empty -.org 112 - rcall isr ; USART3, Tx Complete -.equ INTVECTORS = 57 -.nooverlap - -; compatability layer (maybe empty) - -; controller data area, environment query mcu-info -mcu_info: -mcu_ramsize: - .dw 8192 -mcu_eepromsize: - .dw 4096 -mcu_maxdp: - .dw 57344 -mcu_numints: - .dw 57 -mcu_name: - .dw 9 - .db "ATmega640",0 -.set codestart=pc diff --git a/amforth-6.5/avr8/devices/atmega640/device.inc b/amforth-6.5/avr8/devices/atmega640/device.inc deleted file mode 100644 index 5c15876..0000000 --- a/amforth-6.5/avr8/devices/atmega640/device.inc +++ /dev/null @@ -1,1968 +0,0 @@ -; Partname: ATmega640 -; generated automatically, no not edit - -.if WANT_ANALOG_COMPARATOR == 1 -; ( -- addr ) System Constant -; R( -- ) -; ADC Control and Status Register B -VE_ADCSRB: - .dw $ff06 - .db "ADCSRB" - .dw VE_HEAD - .set VE_HEAD=VE_ADCSRB -XT_ADCSRB: - .dw PFA_DOVARIABLE -PFA_ADCSRB: - .dw 123 -; ( -- addr ) System Constant -; R( -- ) -; Analog Comparator Control And Status Register -VE_ACSR: - .dw $ff04 - .db "ACSR" - .dw VE_HEAD - .set VE_HEAD=VE_ACSR -XT_ACSR: - .dw PFA_DOVARIABLE -PFA_ACSR: - .dw 80 -; ( -- addr ) System Constant -; R( -- ) -; Digital Input Disable Register 1 -VE_DIDR1: - .dw $ff05 - .db "DIDR1",0 - .dw VE_HEAD - .set VE_HEAD=VE_DIDR1 -XT_DIDR1: - .dw PFA_DOVARIABLE -PFA_DIDR1: - .dw 127 - -.endif -.if WANT_USART0 == 1 -; ( -- addr ) System Constant -; R( -- ) -; USART I/O Data Register -VE_UDR0: - .dw $ff04 - .db "UDR0" - .dw VE_HEAD - .set VE_HEAD=VE_UDR0 -XT_UDR0: - .dw PFA_DOVARIABLE -PFA_UDR0: - .dw 198 -; ( -- addr ) System Constant -; R( -- ) -; USART Control and Status Register A -VE_UCSR0A: - .dw $ff06 - .db "UCSR0A" - .dw VE_HEAD - .set VE_HEAD=VE_UCSR0A -XT_UCSR0A: - .dw PFA_DOVARIABLE -PFA_UCSR0A: - .dw 192 -; ( -- addr ) System Constant -; R( -- ) -; USART Control and Status Register B -VE_UCSR0B: - .dw $ff06 - .db "UCSR0B" - .dw VE_HEAD - .set VE_HEAD=VE_UCSR0B -XT_UCSR0B: - .dw PFA_DOVARIABLE -PFA_UCSR0B: - .dw 193 -; ( -- addr ) System Constant -; R( -- ) -; USART Control and Status Register C -VE_UCSR0C: - .dw $ff06 - .db "UCSR0C" - .dw VE_HEAD - .set VE_HEAD=VE_UCSR0C -XT_UCSR0C: - .dw PFA_DOVARIABLE -PFA_UCSR0C: - .dw 194 -; ( -- addr ) System Constant -; R( -- ) -; USART Baud Rate Register Bytes -VE_UBRR0: - .dw $ff05 - .db "UBRR0",0 - .dw VE_HEAD - .set VE_HEAD=VE_UBRR0 -XT_UBRR0: - .dw PFA_DOVARIABLE -PFA_UBRR0: - .dw 196 - -.endif -.if WANT_TWI == 1 -; ( -- addr ) System Constant -; R( -- ) -; TWI (Slave) Address Mask Register -VE_TWAMR: - .dw $ff05 - .db "TWAMR",0 - .dw VE_HEAD - .set VE_HEAD=VE_TWAMR -XT_TWAMR: - .dw PFA_DOVARIABLE -PFA_TWAMR: - .dw 189 -; ( -- addr ) System Constant -; R( -- ) -; TWI Bit Rate register -VE_TWBR: - .dw $ff04 - .db "TWBR" - .dw VE_HEAD - .set VE_HEAD=VE_TWBR -XT_TWBR: - .dw PFA_DOVARIABLE -PFA_TWBR: - .dw 184 -; ( -- addr ) System Constant -; R( -- ) -; TWI Control Register -VE_TWCR: - .dw $ff04 - .db "TWCR" - .dw VE_HEAD - .set VE_HEAD=VE_TWCR -XT_TWCR: - .dw PFA_DOVARIABLE -PFA_TWCR: - .dw 188 -; ( -- addr ) System Constant -; R( -- ) -; TWI Status Register -VE_TWSR: - .dw $ff04 - .db "TWSR" - .dw VE_HEAD - .set VE_HEAD=VE_TWSR -XT_TWSR: - .dw PFA_DOVARIABLE -PFA_TWSR: - .dw 185 -; ( -- addr ) System Constant -; R( -- ) -; TWI Data register -VE_TWDR: - .dw $ff04 - .db "TWDR" - .dw VE_HEAD - .set VE_HEAD=VE_TWDR -XT_TWDR: - .dw PFA_DOVARIABLE -PFA_TWDR: - .dw 187 -; ( -- addr ) System Constant -; R( -- ) -; TWI (Slave) Address register -VE_TWAR: - .dw $ff04 - .db "TWAR" - .dw VE_HEAD - .set VE_HEAD=VE_TWAR -XT_TWAR: - .dw PFA_DOVARIABLE -PFA_TWAR: - .dw 186 - -.endif -.if WANT_SPI == 1 -; ( -- addr ) System Constant -; R( -- ) -; SPI Control Register -VE_SPCR: - .dw $ff04 - .db "SPCR" - .dw VE_HEAD - .set VE_HEAD=VE_SPCR -XT_SPCR: - .dw PFA_DOVARIABLE -PFA_SPCR: - .dw 76 -; ( -- addr ) System Constant -; R( -- ) -; SPI Status Register -VE_SPSR: - .dw $ff04 - .db "SPSR" - .dw VE_HEAD - .set VE_HEAD=VE_SPSR -XT_SPSR: - .dw PFA_DOVARIABLE -PFA_SPSR: - .dw 77 -; ( -- addr ) System Constant -; R( -- ) -; SPI Data Register -VE_SPDR: - .dw $ff04 - .db "SPDR" - .dw VE_HEAD - .set VE_HEAD=VE_SPDR -XT_SPDR: - .dw PFA_DOVARIABLE -PFA_SPDR: - .dw 78 - -.endif -.if WANT_PORTA == 1 -; ( -- addr ) System Constant -; R( -- ) -; Port A Data Register -VE_PORTA: - .dw $ff05 - .db "PORTA",0 - .dw VE_HEAD - .set VE_HEAD=VE_PORTA -XT_PORTA: - .dw PFA_DOVARIABLE -PFA_PORTA: - .dw 34 -; ( -- addr ) System Constant -; R( -- ) -; Port A Data Direction Register -VE_DDRA: - .dw $ff04 - .db "DDRA" - .dw VE_HEAD - .set VE_HEAD=VE_DDRA -XT_DDRA: - .dw PFA_DOVARIABLE -PFA_DDRA: - .dw 33 -; ( -- addr ) System Constant -; R( -- ) -; Port A Input Pins -VE_PINA: - .dw $ff04 - .db "PINA" - .dw VE_HEAD - .set VE_HEAD=VE_PINA -XT_PINA: - .dw PFA_DOVARIABLE -PFA_PINA: - .dw 32 - -.endif -.if WANT_PORTB == 1 -; ( -- addr ) System Constant -; R( -- ) -; Port B Data Register -VE_PORTB: - .dw $ff05 - .db "PORTB",0 - .dw VE_HEAD - .set VE_HEAD=VE_PORTB -XT_PORTB: - .dw PFA_DOVARIABLE -PFA_PORTB: - .dw 37 -; ( -- addr ) System Constant -; R( -- ) -; Port B Data Direction Register -VE_DDRB: - .dw $ff04 - .db "DDRB" - .dw VE_HEAD - .set VE_HEAD=VE_DDRB -XT_DDRB: - .dw PFA_DOVARIABLE -PFA_DDRB: - .dw 36 -; ( -- addr ) System Constant -; R( -- ) -; Port B Input Pins -VE_PINB: - .dw $ff04 - .db "PINB" - .dw VE_HEAD - .set VE_HEAD=VE_PINB -XT_PINB: - .dw PFA_DOVARIABLE -PFA_PINB: - .dw 35 - -.endif -.if WANT_PORTC == 1 -; ( -- addr ) System Constant -; R( -- ) -; Port C Data Register -VE_PORTC: - .dw $ff05 - .db "PORTC",0 - .dw VE_HEAD - .set VE_HEAD=VE_PORTC -XT_PORTC: - .dw PFA_DOVARIABLE -PFA_PORTC: - .dw 40 -; ( -- addr ) System Constant -; R( -- ) -; Port C Data Direction Register -VE_DDRC: - .dw $ff04 - .db "DDRC" - .dw VE_HEAD - .set VE_HEAD=VE_DDRC -XT_DDRC: - .dw PFA_DOVARIABLE -PFA_DDRC: - .dw 39 -; ( -- addr ) System Constant -; R( -- ) -; Port C Input Pins -VE_PINC: - .dw $ff04 - .db "PINC" - .dw VE_HEAD - .set VE_HEAD=VE_PINC -XT_PINC: - .dw PFA_DOVARIABLE -PFA_PINC: - .dw 38 - -.endif -.if WANT_PORTD == 1 -; ( -- addr ) System Constant -; R( -- ) -; Port D Data Register -VE_PORTD: - .dw $ff05 - .db "PORTD",0 - .dw VE_HEAD - .set VE_HEAD=VE_PORTD -XT_PORTD: - .dw PFA_DOVARIABLE -PFA_PORTD: - .dw 43 -; ( -- addr ) System Constant -; R( -- ) -; Port D Data Direction Register -VE_DDRD: - .dw $ff04 - .db "DDRD" - .dw VE_HEAD - .set VE_HEAD=VE_DDRD -XT_DDRD: - .dw PFA_DOVARIABLE -PFA_DDRD: - .dw 42 -; ( -- addr ) System Constant -; R( -- ) -; Port D Input Pins -VE_PIND: - .dw $ff04 - .db "PIND" - .dw VE_HEAD - .set VE_HEAD=VE_PIND -XT_PIND: - .dw PFA_DOVARIABLE -PFA_PIND: - .dw 41 - -.endif -.if WANT_PORTE == 1 -; ( -- addr ) System Constant -; R( -- ) -; Data Register, Port E -VE_PORTE: - .dw $ff05 - .db "PORTE",0 - .dw VE_HEAD - .set VE_HEAD=VE_PORTE -XT_PORTE: - .dw PFA_DOVARIABLE -PFA_PORTE: - .dw 46 -; ( -- addr ) System Constant -; R( -- ) -; Data Direction Register, Port E -VE_DDRE: - .dw $ff04 - .db "DDRE" - .dw VE_HEAD - .set VE_HEAD=VE_DDRE -XT_DDRE: - .dw PFA_DOVARIABLE -PFA_DDRE: - .dw 45 -; ( -- addr ) System Constant -; R( -- ) -; Input Pins, Port E -VE_PINE: - .dw $ff04 - .db "PINE" - .dw VE_HEAD - .set VE_HEAD=VE_PINE -XT_PINE: - .dw PFA_DOVARIABLE -PFA_PINE: - .dw 44 - -.endif -.if WANT_PORTF == 1 -; ( -- addr ) System Constant -; R( -- ) -; Data Register, Port F -VE_PORTF: - .dw $ff05 - .db "PORTF",0 - .dw VE_HEAD - .set VE_HEAD=VE_PORTF -XT_PORTF: - .dw PFA_DOVARIABLE -PFA_PORTF: - .dw 49 -; ( -- addr ) System Constant -; R( -- ) -; Data Direction Register, Port F -VE_DDRF: - .dw $ff04 - .db "DDRF" - .dw VE_HEAD - .set VE_HEAD=VE_DDRF -XT_DDRF: - .dw PFA_DOVARIABLE -PFA_DDRF: - .dw 48 -; ( -- addr ) System Constant -; R( -- ) -; Input Pins, Port F -VE_PINF: - .dw $ff04 - .db "PINF" - .dw VE_HEAD - .set VE_HEAD=VE_PINF -XT_PINF: - .dw PFA_DOVARIABLE -PFA_PINF: - .dw 47 - -.endif -.if WANT_PORTG == 1 -; ( -- addr ) System Constant -; R( -- ) -; Data Register, Port G -VE_PORTG: - .dw $ff05 - .db "PORTG",0 - .dw VE_HEAD - .set VE_HEAD=VE_PORTG -XT_PORTG: - .dw PFA_DOVARIABLE -PFA_PORTG: - .dw 52 -; ( -- addr ) System Constant -; R( -- ) -; Data Direction Register, Port G -VE_DDRG: - .dw $ff04 - .db "DDRG" - .dw VE_HEAD - .set VE_HEAD=VE_DDRG -XT_DDRG: - .dw PFA_DOVARIABLE -PFA_DDRG: - .dw 51 -; ( -- addr ) System Constant -; R( -- ) -; Input Pins, Port G -VE_PING: - .dw $ff04 - .db "PING" - .dw VE_HEAD - .set VE_HEAD=VE_PING -XT_PING: - .dw PFA_DOVARIABLE -PFA_PING: - .dw 50 - -.endif -.if WANT_PORTH == 1 -; ( -- addr ) System Constant -; R( -- ) -; PORT H Data Register -VE_PORTH: - .dw $ff05 - .db "PORTH",0 - .dw VE_HEAD - .set VE_HEAD=VE_PORTH -XT_PORTH: - .dw PFA_DOVARIABLE -PFA_PORTH: - .dw 258 -; ( -- addr ) System Constant -; R( -- ) -; PORT H Data Direction Register -VE_DDRH: - .dw $ff04 - .db "DDRH" - .dw VE_HEAD - .set VE_HEAD=VE_DDRH -XT_DDRH: - .dw PFA_DOVARIABLE -PFA_DDRH: - .dw 257 -; ( -- addr ) System Constant -; R( -- ) -; PORT H Input Pins -VE_PINH: - .dw $ff04 - .db "PINH" - .dw VE_HEAD - .set VE_HEAD=VE_PINH -XT_PINH: - .dw PFA_DOVARIABLE -PFA_PINH: - .dw 256 - -.endif -.if WANT_PORTJ == 1 -; ( -- addr ) System Constant -; R( -- ) -; PORT J Data Register -VE_PORTJ: - .dw $ff05 - .db "PORTJ",0 - .dw VE_HEAD - .set VE_HEAD=VE_PORTJ -XT_PORTJ: - .dw PFA_DOVARIABLE -PFA_PORTJ: - .dw 261 -; ( -- addr ) System Constant -; R( -- ) -; PORT J Data Direction Register -VE_DDRJ: - .dw $ff04 - .db "DDRJ" - .dw VE_HEAD - .set VE_HEAD=VE_DDRJ -XT_DDRJ: - .dw PFA_DOVARIABLE -PFA_DDRJ: - .dw 260 -; ( -- addr ) System Constant -; R( -- ) -; PORT J Input Pins -VE_PINJ: - .dw $ff04 - .db "PINJ" - .dw VE_HEAD - .set VE_HEAD=VE_PINJ -XT_PINJ: - .dw PFA_DOVARIABLE -PFA_PINJ: - .dw 259 - -.endif -.if WANT_PORTK == 1 -; ( -- addr ) System Constant -; R( -- ) -; PORT K Data Register -VE_PORTK: - .dw $ff05 - .db "PORTK",0 - .dw VE_HEAD - .set VE_HEAD=VE_PORTK -XT_PORTK: - .dw PFA_DOVARIABLE -PFA_PORTK: - .dw 264 -; ( -- addr ) System Constant -; R( -- ) -; PORT K Data Direction Register -VE_DDRK: - .dw $ff04 - .db "DDRK" - .dw VE_HEAD - .set VE_HEAD=VE_DDRK -XT_DDRK: - .dw PFA_DOVARIABLE -PFA_DDRK: - .dw 263 -; ( -- addr ) System Constant -; R( -- ) -; PORT K Input Pins -VE_PINK: - .dw $ff04 - .db "PINK" - .dw VE_HEAD - .set VE_HEAD=VE_PINK -XT_PINK: - .dw PFA_DOVARIABLE -PFA_PINK: - .dw 262 - -.endif -.if WANT_PORTL == 1 -; ( -- addr ) System Constant -; R( -- ) -; PORT L Data Register -VE_PORTL: - .dw $ff05 - .db "PORTL",0 - .dw VE_HEAD - .set VE_HEAD=VE_PORTL -XT_PORTL: - .dw PFA_DOVARIABLE -PFA_PORTL: - .dw 267 -; ( -- addr ) System Constant -; R( -- ) -; PORT L Data Direction Register -VE_DDRL: - .dw $ff04 - .db "DDRL" - .dw VE_HEAD - .set VE_HEAD=VE_DDRL -XT_DDRL: - .dw PFA_DOVARIABLE -PFA_DDRL: - .dw 266 -; ( -- addr ) System Constant -; R( -- ) -; PORT L Input Pins -VE_PINL: - .dw $ff04 - .db "PINL" - .dw VE_HEAD - .set VE_HEAD=VE_PINL -XT_PINL: - .dw PFA_DOVARIABLE -PFA_PINL: - .dw 265 - -.endif -.if WANT_TIMER_COUNTER_0 == 1 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter0 Output Compare Register -VE_OCR0B: - .dw $ff05 - .db "OCR0B",0 - .dw VE_HEAD - .set VE_HEAD=VE_OCR0B -XT_OCR0B: - .dw PFA_DOVARIABLE -PFA_OCR0B: - .dw 72 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter0 Output Compare Register -VE_OCR0A: - .dw $ff05 - .db "OCR0A",0 - .dw VE_HEAD - .set VE_HEAD=VE_OCR0A -XT_OCR0A: - .dw PFA_DOVARIABLE -PFA_OCR0A: - .dw 71 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter0 -VE_TCNT0: - .dw $ff05 - .db "TCNT0",0 - .dw VE_HEAD - .set VE_HEAD=VE_TCNT0 -XT_TCNT0: - .dw PFA_DOVARIABLE -PFA_TCNT0: - .dw 70 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter Control Register B -VE_TCCR0B: - .dw $ff06 - .db "TCCR0B" - .dw VE_HEAD - .set VE_HEAD=VE_TCCR0B -XT_TCCR0B: - .dw PFA_DOVARIABLE -PFA_TCCR0B: - .dw 69 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter Control Register A -VE_TCCR0A: - .dw $ff06 - .db "TCCR0A" - .dw VE_HEAD - .set VE_HEAD=VE_TCCR0A -XT_TCCR0A: - .dw PFA_DOVARIABLE -PFA_TCCR0A: - .dw 68 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter0 Interrupt Mask Register -VE_TIMSK0: - .dw $ff06 - .db "TIMSK0" - .dw VE_HEAD - .set VE_HEAD=VE_TIMSK0 -XT_TIMSK0: - .dw PFA_DOVARIABLE -PFA_TIMSK0: - .dw 110 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter0 Interrupt Flag register -VE_TIFR0: - .dw $ff05 - .db "TIFR0",0 - .dw VE_HEAD - .set VE_HEAD=VE_TIFR0 -XT_TIFR0: - .dw PFA_DOVARIABLE -PFA_TIFR0: - .dw 53 -; ( -- addr ) System Constant -; R( -- ) -; General Timer/Counter Control Register -VE_GTCCR: - .dw $ff05 - .db "GTCCR",0 - .dw VE_HEAD - .set VE_HEAD=VE_GTCCR -XT_GTCCR: - .dw PFA_DOVARIABLE -PFA_GTCCR: - .dw 67 - -.endif -.if WANT_TIMER_COUNTER_2 == 1 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter Interrupt Mask register -VE_TIMSK2: - .dw $ff06 - .db "TIMSK2" - .dw VE_HEAD - .set VE_HEAD=VE_TIMSK2 -XT_TIMSK2: - .dw PFA_DOVARIABLE -PFA_TIMSK2: - .dw 112 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter Interrupt Flag Register -VE_TIFR2: - .dw $ff05 - .db "TIFR2",0 - .dw VE_HEAD - .set VE_HEAD=VE_TIFR2 -XT_TIFR2: - .dw PFA_DOVARIABLE -PFA_TIFR2: - .dw 55 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter2 Control Register A -VE_TCCR2A: - .dw $ff06 - .db "TCCR2A" - .dw VE_HEAD - .set VE_HEAD=VE_TCCR2A -XT_TCCR2A: - .dw PFA_DOVARIABLE -PFA_TCCR2A: - .dw 176 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter2 Control Register B -VE_TCCR2B: - .dw $ff06 - .db "TCCR2B" - .dw VE_HEAD - .set VE_HEAD=VE_TCCR2B -XT_TCCR2B: - .dw PFA_DOVARIABLE -PFA_TCCR2B: - .dw 177 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter2 -VE_TCNT2: - .dw $ff05 - .db "TCNT2",0 - .dw VE_HEAD - .set VE_HEAD=VE_TCNT2 -XT_TCNT2: - .dw PFA_DOVARIABLE -PFA_TCNT2: - .dw 178 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter2 Output Compare Register B -VE_OCR2B: - .dw $ff05 - .db "OCR2B",0 - .dw VE_HEAD - .set VE_HEAD=VE_OCR2B -XT_OCR2B: - .dw PFA_DOVARIABLE -PFA_OCR2B: - .dw 180 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter2 Output Compare Register A -VE_OCR2A: - .dw $ff05 - .db "OCR2A",0 - .dw VE_HEAD - .set VE_HEAD=VE_OCR2A -XT_OCR2A: - .dw PFA_DOVARIABLE -PFA_OCR2A: - .dw 179 -; ( -- addr ) System Constant -; R( -- ) -; Asynchronous Status Register -VE_ASSR: - .dw $ff04 - .db "ASSR" - .dw VE_HEAD - .set VE_HEAD=VE_ASSR -XT_ASSR: - .dw PFA_DOVARIABLE -PFA_ASSR: - .dw 182 - -.endif -.if WANT_WATCHDOG == 1 -; ( -- addr ) System Constant -; R( -- ) -; Watchdog Timer Control Register -VE_WDTCSR: - .dw $ff06 - .db "WDTCSR" - .dw VE_HEAD - .set VE_HEAD=VE_WDTCSR -XT_WDTCSR: - .dw PFA_DOVARIABLE -PFA_WDTCSR: - .dw 96 - -.endif -.if WANT_USART1 == 1 -; ( -- addr ) System Constant -; R( -- ) -; USART I/O Data Register -VE_UDR1: - .dw $ff04 - .db "UDR1" - .dw VE_HEAD - .set VE_HEAD=VE_UDR1 -XT_UDR1: - .dw PFA_DOVARIABLE -PFA_UDR1: - .dw 206 -; ( -- addr ) System Constant -; R( -- ) -; USART Control and Status Register A -VE_UCSR1A: - .dw $ff06 - .db "UCSR1A" - .dw VE_HEAD - .set VE_HEAD=VE_UCSR1A -XT_UCSR1A: - .dw PFA_DOVARIABLE -PFA_UCSR1A: - .dw 200 -; ( -- addr ) System Constant -; R( -- ) -; USART Control and Status Register B -VE_UCSR1B: - .dw $ff06 - .db "UCSR1B" - .dw VE_HEAD - .set VE_HEAD=VE_UCSR1B -XT_UCSR1B: - .dw PFA_DOVARIABLE -PFA_UCSR1B: - .dw 201 -; ( -- addr ) System Constant -; R( -- ) -; USART Control and Status Register C -VE_UCSR1C: - .dw $ff06 - .db "UCSR1C" - .dw VE_HEAD - .set VE_HEAD=VE_UCSR1C -XT_UCSR1C: - .dw PFA_DOVARIABLE -PFA_UCSR1C: - .dw 202 -; ( -- addr ) System Constant -; R( -- ) -; USART Baud Rate Register Bytes -VE_UBRR1: - .dw $ff05 - .db "UBRR1",0 - .dw VE_HEAD - .set VE_HEAD=VE_UBRR1 -XT_UBRR1: - .dw PFA_DOVARIABLE -PFA_UBRR1: - .dw 204 - -.endif -.if WANT_EEPROM == 1 -; ( -- addr ) System Constant -; R( -- ) -; EEPROM Address Register Low Bytes -VE_EEAR: - .dw $ff04 - .db "EEAR" - .dw VE_HEAD - .set VE_HEAD=VE_EEAR -XT_EEAR: - .dw PFA_DOVARIABLE -PFA_EEAR: - .dw 65 -; ( -- addr ) System Constant -; R( -- ) -; EEPROM Data Register -VE_EEDR: - .dw $ff04 - .db "EEDR" - .dw VE_HEAD - .set VE_HEAD=VE_EEDR -XT_EEDR: - .dw PFA_DOVARIABLE -PFA_EEDR: - .dw 64 -; ( -- addr ) System Constant -; R( -- ) -; EEPROM Control Register -VE_EECR: - .dw $ff04 - .db "EECR" - .dw VE_HEAD - .set VE_HEAD=VE_EECR -XT_EECR: - .dw PFA_DOVARIABLE -PFA_EECR: - .dw 63 - -.endif -.if WANT_TIMER_COUNTER_5 == 1 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter5 Control Register A -VE_TCCR5A: - .dw $ff06 - .db "TCCR5A" - .dw VE_HEAD - .set VE_HEAD=VE_TCCR5A -XT_TCCR5A: - .dw PFA_DOVARIABLE -PFA_TCCR5A: - .dw 288 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter5 Control Register B -VE_TCCR5B: - .dw $ff06 - .db "TCCR5B" - .dw VE_HEAD - .set VE_HEAD=VE_TCCR5B -XT_TCCR5B: - .dw PFA_DOVARIABLE -PFA_TCCR5B: - .dw 289 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter 5 Control Register C -VE_TCCR5C: - .dw $ff06 - .db "TCCR5C" - .dw VE_HEAD - .set VE_HEAD=VE_TCCR5C -XT_TCCR5C: - .dw PFA_DOVARIABLE -PFA_TCCR5C: - .dw 290 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter5 Bytes -VE_TCNT5: - .dw $ff05 - .db "TCNT5",0 - .dw VE_HEAD - .set VE_HEAD=VE_TCNT5 -XT_TCNT5: - .dw PFA_DOVARIABLE -PFA_TCNT5: - .dw 292 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter5 Output Compare Register A Bytes -VE_OCR5A: - .dw $ff05 - .db "OCR5A",0 - .dw VE_HEAD - .set VE_HEAD=VE_OCR5A -XT_OCR5A: - .dw PFA_DOVARIABLE -PFA_OCR5A: - .dw 296 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter5 Output Compare Register B Bytes -VE_OCR5B: - .dw $ff05 - .db "OCR5B",0 - .dw VE_HEAD - .set VE_HEAD=VE_OCR5B -XT_OCR5B: - .dw PFA_DOVARIABLE -PFA_OCR5B: - .dw 298 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter5 Output Compare Register B Bytes -VE_OCR5C: - .dw $ff05 - .db "OCR5C",0 - .dw VE_HEAD - .set VE_HEAD=VE_OCR5C -XT_OCR5C: - .dw PFA_DOVARIABLE -PFA_OCR5C: - .dw 300 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter5 Input Capture Register Bytes -VE_ICR5: - .dw $ff04 - .db "ICR5" - .dw VE_HEAD - .set VE_HEAD=VE_ICR5 -XT_ICR5: - .dw PFA_DOVARIABLE -PFA_ICR5: - .dw 294 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter5 Interrupt Mask Register -VE_TIMSK5: - .dw $ff06 - .db "TIMSK5" - .dw VE_HEAD - .set VE_HEAD=VE_TIMSK5 -XT_TIMSK5: - .dw PFA_DOVARIABLE -PFA_TIMSK5: - .dw 115 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter5 Interrupt Flag register -VE_TIFR5: - .dw $ff05 - .db "TIFR5",0 - .dw VE_HEAD - .set VE_HEAD=VE_TIFR5 -XT_TIFR5: - .dw PFA_DOVARIABLE -PFA_TIFR5: - .dw 58 - -.endif -.if WANT_TIMER_COUNTER_4 == 1 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter4 Control Register A -VE_TCCR4A: - .dw $ff06 - .db "TCCR4A" - .dw VE_HEAD - .set VE_HEAD=VE_TCCR4A -XT_TCCR4A: - .dw PFA_DOVARIABLE -PFA_TCCR4A: - .dw 160 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter4 Control Register B -VE_TCCR4B: - .dw $ff06 - .db "TCCR4B" - .dw VE_HEAD - .set VE_HEAD=VE_TCCR4B -XT_TCCR4B: - .dw PFA_DOVARIABLE -PFA_TCCR4B: - .dw 161 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter 4 Control Register C -VE_TCCR4C: - .dw $ff06 - .db "TCCR4C" - .dw VE_HEAD - .set VE_HEAD=VE_TCCR4C -XT_TCCR4C: - .dw PFA_DOVARIABLE -PFA_TCCR4C: - .dw 162 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter4 Bytes -VE_TCNT4: - .dw $ff05 - .db "TCNT4",0 - .dw VE_HEAD - .set VE_HEAD=VE_TCNT4 -XT_TCNT4: - .dw PFA_DOVARIABLE -PFA_TCNT4: - .dw 164 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter4 Output Compare Register A Bytes -VE_OCR4A: - .dw $ff05 - .db "OCR4A",0 - .dw VE_HEAD - .set VE_HEAD=VE_OCR4A -XT_OCR4A: - .dw PFA_DOVARIABLE -PFA_OCR4A: - .dw 168 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter4 Output Compare Register B Bytes -VE_OCR4B: - .dw $ff05 - .db "OCR4B",0 - .dw VE_HEAD - .set VE_HEAD=VE_OCR4B -XT_OCR4B: - .dw PFA_DOVARIABLE -PFA_OCR4B: - .dw 170 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter4 Output Compare Register B Bytes -VE_OCR4C: - .dw $ff05 - .db "OCR4C",0 - .dw VE_HEAD - .set VE_HEAD=VE_OCR4C -XT_OCR4C: - .dw PFA_DOVARIABLE -PFA_OCR4C: - .dw 172 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter4 Input Capture Register Bytes -VE_ICR4: - .dw $ff04 - .db "ICR4" - .dw VE_HEAD - .set VE_HEAD=VE_ICR4 -XT_ICR4: - .dw PFA_DOVARIABLE -PFA_ICR4: - .dw 166 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter4 Interrupt Mask Register -VE_TIMSK4: - .dw $ff06 - .db "TIMSK4" - .dw VE_HEAD - .set VE_HEAD=VE_TIMSK4 -XT_TIMSK4: - .dw PFA_DOVARIABLE -PFA_TIMSK4: - .dw 114 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter4 Interrupt Flag register -VE_TIFR4: - .dw $ff05 - .db "TIFR4",0 - .dw VE_HEAD - .set VE_HEAD=VE_TIFR4 -XT_TIFR4: - .dw PFA_DOVARIABLE -PFA_TIFR4: - .dw 57 - -.endif -.if WANT_TIMER_COUNTER_3 == 1 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter3 Control Register A -VE_TCCR3A: - .dw $ff06 - .db "TCCR3A" - .dw VE_HEAD - .set VE_HEAD=VE_TCCR3A -XT_TCCR3A: - .dw PFA_DOVARIABLE -PFA_TCCR3A: - .dw 144 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter3 Control Register B -VE_TCCR3B: - .dw $ff06 - .db "TCCR3B" - .dw VE_HEAD - .set VE_HEAD=VE_TCCR3B -XT_TCCR3B: - .dw PFA_DOVARIABLE -PFA_TCCR3B: - .dw 145 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter 3 Control Register C -VE_TCCR3C: - .dw $ff06 - .db "TCCR3C" - .dw VE_HEAD - .set VE_HEAD=VE_TCCR3C -XT_TCCR3C: - .dw PFA_DOVARIABLE -PFA_TCCR3C: - .dw 146 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter3 Bytes -VE_TCNT3: - .dw $ff05 - .db "TCNT3",0 - .dw VE_HEAD - .set VE_HEAD=VE_TCNT3 -XT_TCNT3: - .dw PFA_DOVARIABLE -PFA_TCNT3: - .dw 148 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter3 Output Compare Register A Bytes -VE_OCR3A: - .dw $ff05 - .db "OCR3A",0 - .dw VE_HEAD - .set VE_HEAD=VE_OCR3A -XT_OCR3A: - .dw PFA_DOVARIABLE -PFA_OCR3A: - .dw 152 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter3 Output Compare Register B Bytes -VE_OCR3B: - .dw $ff05 - .db "OCR3B",0 - .dw VE_HEAD - .set VE_HEAD=VE_OCR3B -XT_OCR3B: - .dw PFA_DOVARIABLE -PFA_OCR3B: - .dw 154 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter3 Output Compare Register B Bytes -VE_OCR3C: - .dw $ff05 - .db "OCR3C",0 - .dw VE_HEAD - .set VE_HEAD=VE_OCR3C -XT_OCR3C: - .dw PFA_DOVARIABLE -PFA_OCR3C: - .dw 156 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter3 Input Capture Register Bytes -VE_ICR3: - .dw $ff04 - .db "ICR3" - .dw VE_HEAD - .set VE_HEAD=VE_ICR3 -XT_ICR3: - .dw PFA_DOVARIABLE -PFA_ICR3: - .dw 150 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter3 Interrupt Mask Register -VE_TIMSK3: - .dw $ff06 - .db "TIMSK3" - .dw VE_HEAD - .set VE_HEAD=VE_TIMSK3 -XT_TIMSK3: - .dw PFA_DOVARIABLE -PFA_TIMSK3: - .dw 113 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter3 Interrupt Flag register -VE_TIFR3: - .dw $ff05 - .db "TIFR3",0 - .dw VE_HEAD - .set VE_HEAD=VE_TIFR3 -XT_TIFR3: - .dw PFA_DOVARIABLE -PFA_TIFR3: - .dw 56 - -.endif -.if WANT_TIMER_COUNTER_1 == 1 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter1 Control Register A -VE_TCCR1A: - .dw $ff06 - .db "TCCR1A" - .dw VE_HEAD - .set VE_HEAD=VE_TCCR1A -XT_TCCR1A: - .dw PFA_DOVARIABLE -PFA_TCCR1A: - .dw 128 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter1 Control Register B -VE_TCCR1B: - .dw $ff06 - .db "TCCR1B" - .dw VE_HEAD - .set VE_HEAD=VE_TCCR1B -XT_TCCR1B: - .dw PFA_DOVARIABLE -PFA_TCCR1B: - .dw 129 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter 1 Control Register C -VE_TCCR1C: - .dw $ff06 - .db "TCCR1C" - .dw VE_HEAD - .set VE_HEAD=VE_TCCR1C -XT_TCCR1C: - .dw PFA_DOVARIABLE -PFA_TCCR1C: - .dw 130 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter1 Bytes -VE_TCNT1: - .dw $ff05 - .db "TCNT1",0 - .dw VE_HEAD - .set VE_HEAD=VE_TCNT1 -XT_TCNT1: - .dw PFA_DOVARIABLE -PFA_TCNT1: - .dw 132 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter1 Output Compare Register A Bytes -VE_OCR1A: - .dw $ff05 - .db "OCR1A",0 - .dw VE_HEAD - .set VE_HEAD=VE_OCR1A -XT_OCR1A: - .dw PFA_DOVARIABLE -PFA_OCR1A: - .dw 136 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter1 Output Compare Register B Bytes -VE_OCR1B: - .dw $ff05 - .db "OCR1B",0 - .dw VE_HEAD - .set VE_HEAD=VE_OCR1B -XT_OCR1B: - .dw PFA_DOVARIABLE -PFA_OCR1B: - .dw 138 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter1 Output Compare Register C Bytes -VE_OCR1C: - .dw $ff05 - .db "OCR1C",0 - .dw VE_HEAD - .set VE_HEAD=VE_OCR1C -XT_OCR1C: - .dw PFA_DOVARIABLE -PFA_OCR1C: - .dw 140 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter1 Input Capture Register Bytes -VE_ICR1: - .dw $ff04 - .db "ICR1" - .dw VE_HEAD - .set VE_HEAD=VE_ICR1 -XT_ICR1: - .dw PFA_DOVARIABLE -PFA_ICR1: - .dw 134 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter1 Interrupt Mask Register -VE_TIMSK1: - .dw $ff06 - .db "TIMSK1" - .dw VE_HEAD - .set VE_HEAD=VE_TIMSK1 -XT_TIMSK1: - .dw PFA_DOVARIABLE -PFA_TIMSK1: - .dw 111 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter1 Interrupt Flag register -VE_TIFR1: - .dw $ff05 - .db "TIFR1",0 - .dw VE_HEAD - .set VE_HEAD=VE_TIFR1 -XT_TIFR1: - .dw PFA_DOVARIABLE -PFA_TIFR1: - .dw 54 - -.endif -.if WANT_JTAG == 1 -; ( -- addr ) System Constant -; R( -- ) -; On-Chip Debug Related Register in I/O Memory -VE_OCDR: - .dw $ff04 - .db "OCDR" - .dw VE_HEAD - .set VE_HEAD=VE_OCDR -XT_OCDR: - .dw PFA_DOVARIABLE -PFA_OCDR: - .dw 81 -; ( -- addr ) System Constant -; R( -- ) -; MCU Control Register -VE_MCUCR: - .dw $ff05 - .db "MCUCR",0 - .dw VE_HEAD - .set VE_HEAD=VE_MCUCR -XT_MCUCR: - .dw PFA_DOVARIABLE -PFA_MCUCR: - .dw 85 -; ( -- addr ) System Constant -; R( -- ) -; MCU Status Register -VE_MCUSR: - .dw $ff05 - .db "MCUSR",0 - .dw VE_HEAD - .set VE_HEAD=VE_MCUSR -XT_MCUSR: - .dw PFA_DOVARIABLE -PFA_MCUSR: - .dw 84 - -.endif -.if WANT_EXTERNAL_INTERRUPT == 1 -; ( -- addr ) System Constant -; R( -- ) -; External Interrupt Control Register A -VE_EICRA: - .dw $ff05 - .db "EICRA",0 - .dw VE_HEAD - .set VE_HEAD=VE_EICRA -XT_EICRA: - .dw PFA_DOVARIABLE -PFA_EICRA: - .dw 105 -; ( -- addr ) System Constant -; R( -- ) -; External Interrupt Control Register B -VE_EICRB: - .dw $ff05 - .db "EICRB",0 - .dw VE_HEAD - .set VE_HEAD=VE_EICRB -XT_EICRB: - .dw PFA_DOVARIABLE -PFA_EICRB: - .dw 106 -; ( -- addr ) System Constant -; R( -- ) -; External Interrupt Mask Register -VE_EIMSK: - .dw $ff05 - .db "EIMSK",0 - .dw VE_HEAD - .set VE_HEAD=VE_EIMSK -XT_EIMSK: - .dw PFA_DOVARIABLE -PFA_EIMSK: - .dw 61 -; ( -- addr ) System Constant -; R( -- ) -; External Interrupt Flag Register -VE_EIFR: - .dw $ff04 - .db "EIFR" - .dw VE_HEAD - .set VE_HEAD=VE_EIFR -XT_EIFR: - .dw PFA_DOVARIABLE -PFA_EIFR: - .dw 60 -; ( -- addr ) System Constant -; R( -- ) -; Pin Change Mask Register 2 -VE_PCMSK2: - .dw $ff06 - .db "PCMSK2" - .dw VE_HEAD - .set VE_HEAD=VE_PCMSK2 -XT_PCMSK2: - .dw PFA_DOVARIABLE -PFA_PCMSK2: - .dw 109 -; ( -- addr ) System Constant -; R( -- ) -; Pin Change Mask Register 1 -VE_PCMSK1: - .dw $ff06 - .db "PCMSK1" - .dw VE_HEAD - .set VE_HEAD=VE_PCMSK1 -XT_PCMSK1: - .dw PFA_DOVARIABLE -PFA_PCMSK1: - .dw 108 -; ( -- addr ) System Constant -; R( -- ) -; Pin Change Mask Register 0 -VE_PCMSK0: - .dw $ff06 - .db "PCMSK0" - .dw VE_HEAD - .set VE_HEAD=VE_PCMSK0 -XT_PCMSK0: - .dw PFA_DOVARIABLE -PFA_PCMSK0: - .dw 107 -; ( -- addr ) System Constant -; R( -- ) -; Pin Change Interrupt Flag Register -VE_PCIFR: - .dw $ff05 - .db "PCIFR",0 - .dw VE_HEAD - .set VE_HEAD=VE_PCIFR -XT_PCIFR: - .dw PFA_DOVARIABLE -PFA_PCIFR: - .dw 59 -; ( -- addr ) System Constant -; R( -- ) -; Pin Change Interrupt Control Register -VE_PCICR: - .dw $ff05 - .db "PCICR",0 - .dw VE_HEAD - .set VE_HEAD=VE_PCICR -XT_PCICR: - .dw PFA_DOVARIABLE -PFA_PCICR: - .dw 104 - -.endif -.if WANT_CPU == 1 -; ( -- addr ) System Constant -; R( -- ) -; Status Register -VE_SREG: - .dw $ff04 - .db "SREG" - .dw VE_HEAD - .set VE_HEAD=VE_SREG -XT_SREG: - .dw PFA_DOVARIABLE -PFA_SREG: - .dw 95 -; ( -- addr ) System Constant -; R( -- ) -; Stack Pointer -VE_SP: - .dw $ff02 - .db "SP" - .dw VE_HEAD - .set VE_HEAD=VE_SP -XT_SP: - .dw PFA_DOVARIABLE -PFA_SP: - .dw 93 -; ( -- addr ) System Constant -; R( -- ) -; External Memory Control Register A -VE_XMCRA: - .dw $ff05 - .db "XMCRA",0 - .dw VE_HEAD - .set VE_HEAD=VE_XMCRA -XT_XMCRA: - .dw PFA_DOVARIABLE -PFA_XMCRA: - .dw 116 -; ( -- addr ) System Constant -; R( -- ) -; External Memory Control Register B -VE_XMCRB: - .dw $ff05 - .db "XMCRB",0 - .dw VE_HEAD - .set VE_HEAD=VE_XMCRB -XT_XMCRB: - .dw PFA_DOVARIABLE -PFA_XMCRB: - .dw 117 -; ( -- addr ) System Constant -; R( -- ) -; Oscillator Calibration Value -VE_OSCCAL: - .dw $ff06 - .db "OSCCAL" - .dw VE_HEAD - .set VE_HEAD=VE_OSCCAL -XT_OSCCAL: - .dw PFA_DOVARIABLE -PFA_OSCCAL: - .dw 102 -; ( -- addr ) System Constant -; R( -- ) -; -VE_CLKPR: - .dw $ff05 - .db "CLKPR",0 - .dw VE_HEAD - .set VE_HEAD=VE_CLKPR -XT_CLKPR: - .dw PFA_DOVARIABLE -PFA_CLKPR: - .dw 97 -; ( -- addr ) System Constant -; R( -- ) -; Sleep Mode Control Register -VE_SMCR: - .dw $ff04 - .db "SMCR" - .dw VE_HEAD - .set VE_HEAD=VE_SMCR -XT_SMCR: - .dw PFA_DOVARIABLE -PFA_SMCR: - .dw 83 -; ( -- addr ) System Constant -; R( -- ) -; Extended Indirect Register -VE_EIND: - .dw $ff04 - .db "EIND" - .dw VE_HEAD - .set VE_HEAD=VE_EIND -XT_EIND: - .dw PFA_DOVARIABLE -PFA_EIND: - .dw 92 -; ( -- addr ) System Constant -; R( -- ) -; General Purpose IO Register 2 -VE_GPIOR2: - .dw $ff06 - .db "GPIOR2" - .dw VE_HEAD - .set VE_HEAD=VE_GPIOR2 -XT_GPIOR2: - .dw PFA_DOVARIABLE -PFA_GPIOR2: - .dw 75 -; ( -- addr ) System Constant -; R( -- ) -; General Purpose IO Register 1 -VE_GPIOR1: - .dw $ff06 - .db "GPIOR1" - .dw VE_HEAD - .set VE_HEAD=VE_GPIOR1 -XT_GPIOR1: - .dw PFA_DOVARIABLE -PFA_GPIOR1: - .dw 74 -; ( -- addr ) System Constant -; R( -- ) -; General Purpose IO Register 0 -VE_GPIOR0: - .dw $ff06 - .db "GPIOR0" - .dw VE_HEAD - .set VE_HEAD=VE_GPIOR0 -XT_GPIOR0: - .dw PFA_DOVARIABLE -PFA_GPIOR0: - .dw 62 -; ( -- addr ) System Constant -; R( -- ) -; Power Reduction Register1 -VE_PRR1: - .dw $ff04 - .db "PRR1" - .dw VE_HEAD - .set VE_HEAD=VE_PRR1 -XT_PRR1: - .dw PFA_DOVARIABLE -PFA_PRR1: - .dw 101 -; ( -- addr ) System Constant -; R( -- ) -; Power Reduction Register0 -VE_PRR0: - .dw $ff04 - .db "PRR0" - .dw VE_HEAD - .set VE_HEAD=VE_PRR0 -XT_PRR0: - .dw PFA_DOVARIABLE -PFA_PRR0: - .dw 100 - -.endif -.if WANT_AD_CONVERTER == 1 -; ( -- addr ) System Constant -; R( -- ) -; The ADC multiplexer Selection Register -VE_ADMUX: - .dw $ff05 - .db "ADMUX",0 - .dw VE_HEAD - .set VE_HEAD=VE_ADMUX -XT_ADMUX: - .dw PFA_DOVARIABLE -PFA_ADMUX: - .dw 124 -; ( -- addr ) System Constant -; R( -- ) -; ADC Data Register Bytes -VE_ADC: - .dw $ff03 - .db "ADC",0 - .dw VE_HEAD - .set VE_HEAD=VE_ADC -XT_ADC: - .dw PFA_DOVARIABLE -PFA_ADC: - .dw 120 -; ( -- addr ) System Constant -; R( -- ) -; The ADC Control and Status register A -VE_ADCSRA: - .dw $ff06 - .db "ADCSRA" - .dw VE_HEAD - .set VE_HEAD=VE_ADCSRA -XT_ADCSRA: - .dw PFA_DOVARIABLE -PFA_ADCSRA: - .dw 122 -; ( -- addr ) System Constant -; R( -- ) -; Digital Input Disable Register -VE_DIDR2: - .dw $ff05 - .db "DIDR2",0 - .dw VE_HEAD - .set VE_HEAD=VE_DIDR2 -XT_DIDR2: - .dw PFA_DOVARIABLE -PFA_DIDR2: - .dw 125 -; ( -- addr ) System Constant -; R( -- ) -; Digital Input Disable Register -VE_DIDR0: - .dw $ff05 - .db "DIDR0",0 - .dw VE_HEAD - .set VE_HEAD=VE_DIDR0 -XT_DIDR0: - .dw PFA_DOVARIABLE -PFA_DIDR0: - .dw 126 - -.endif -.if WANT_BOOT_LOAD == 1 -; ( -- addr ) System Constant -; R( -- ) -; Store Program Memory Control Register -VE_SPMCSR: - .dw $ff06 - .db "SPMCSR" - .dw VE_HEAD - .set VE_HEAD=VE_SPMCSR -XT_SPMCSR: - .dw PFA_DOVARIABLE -PFA_SPMCSR: - .dw 87 - -.endif -.if WANT_USART2 == 1 -; ( -- addr ) System Constant -; R( -- ) -; USART I/O Data Register -VE_UDR2: - .dw $ff04 - .db "UDR2" - .dw VE_HEAD - .set VE_HEAD=VE_UDR2 -XT_UDR2: - .dw PFA_DOVARIABLE -PFA_UDR2: - .dw 214 -; ( -- addr ) System Constant -; R( -- ) -; USART Control and Status Register A -VE_UCSR2A: - .dw $ff06 - .db "UCSR2A" - .dw VE_HEAD - .set VE_HEAD=VE_UCSR2A -XT_UCSR2A: - .dw PFA_DOVARIABLE -PFA_UCSR2A: - .dw 208 -; ( -- addr ) System Constant -; R( -- ) -; USART Control and Status Register B -VE_UCSR2B: - .dw $ff06 - .db "UCSR2B" - .dw VE_HEAD - .set VE_HEAD=VE_UCSR2B -XT_UCSR2B: - .dw PFA_DOVARIABLE -PFA_UCSR2B: - .dw 209 -; ( -- addr ) System Constant -; R( -- ) -; USART Control and Status Register C -VE_UCSR2C: - .dw $ff06 - .db "UCSR2C" - .dw VE_HEAD - .set VE_HEAD=VE_UCSR2C -XT_UCSR2C: - .dw PFA_DOVARIABLE -PFA_UCSR2C: - .dw 210 -; ( -- addr ) System Constant -; R( -- ) -; USART Baud Rate Register Bytes -VE_UBRR2: - .dw $ff05 - .db "UBRR2",0 - .dw VE_HEAD - .set VE_HEAD=VE_UBRR2 -XT_UBRR2: - .dw PFA_DOVARIABLE -PFA_UBRR2: - .dw 212 - -.endif -.if WANT_USART3 == 1 -; ( -- addr ) System Constant -; R( -- ) -; USART I/O Data Register -VE_UDR3: - .dw $ff04 - .db "UDR3" - .dw VE_HEAD - .set VE_HEAD=VE_UDR3 -XT_UDR3: - .dw PFA_DOVARIABLE -PFA_UDR3: - .dw 310 -; ( -- addr ) System Constant -; R( -- ) -; USART Control and Status Register A -VE_UCSR3A: - .dw $ff06 - .db "UCSR3A" - .dw VE_HEAD - .set VE_HEAD=VE_UCSR3A -XT_UCSR3A: - .dw PFA_DOVARIABLE -PFA_UCSR3A: - .dw 304 -; ( -- addr ) System Constant -; R( -- ) -; USART Control and Status Register B -VE_UCSR3B: - .dw $ff06 - .db "UCSR3B" - .dw VE_HEAD - .set VE_HEAD=VE_UCSR3B -XT_UCSR3B: - .dw PFA_DOVARIABLE -PFA_UCSR3B: - .dw 305 -; ( -- addr ) System Constant -; R( -- ) -; USART Control and Status Register C -VE_UCSR3C: - .dw $ff06 - .db "UCSR3C" - .dw VE_HEAD - .set VE_HEAD=VE_UCSR3C -XT_UCSR3C: - .dw PFA_DOVARIABLE -PFA_UCSR3C: - .dw 306 -; ( -- addr ) System Constant -; R( -- ) -; USART Baud Rate Register Bytes -VE_UBRR3: - .dw $ff05 - .db "UBRR3",0 - .dw VE_HEAD - .set VE_HEAD=VE_UBRR3 -XT_UBRR3: - .dw PFA_DOVARIABLE -PFA_UBRR3: - .dw 308 - -.endif diff --git a/amforth-6.5/avr8/devices/atmega640/device.py b/amforth-6.5/avr8/devices/atmega640/device.py deleted file mode 100644 index 526b8ed..0000000 --- a/amforth-6.5/avr8/devices/atmega640/device.py +++ /dev/null @@ -1,632 +0,0 @@ -# Generated Automatically - -# Partname ATmega640 - -MCUREGS = { -# Interrupt Vectors - 'INT0Addr' : '#2', # External Interrupt Request 0 - 'INT1Addr' : '#4', # External Interrupt Request 1 - 'INT2Addr' : '#6', # External Interrupt Request 2 - 'INT3Addr' : '#8', # External Interrupt Request 3 - 'INT4Addr' : '#10', # External Interrupt Request 4 - 'INT5Addr' : '#12', # External Interrupt Request 5 - 'INT6Addr' : '#14', # External Interrupt Request 6 - 'INT7Addr' : '#16', # External Interrupt Request 7 - 'PCINT0Addr' : '#18', # Pin Change Interrupt Request 0 - 'PCINT1Addr' : '#20', # Pin Change Interrupt Request 1 - 'PCINT2Addr' : '#22', # Pin Change Interrupt Request 2 - 'WDTAddr' : '#24', # Watchdog Time-out Interrupt - 'TIMER2_COMPAAddr' : '#26', # Timer/Counter2 Compare Match A - 'TIMER2_COMPBAddr' : '#28', # Timer/Counter2 Compare Match B - 'TIMER2_OVFAddr' : '#30', # Timer/Counter2 Overflow - 'TIMER1_CAPTAddr' : '#32', # Timer/Counter1 Capture Event - 'TIMER1_COMPAAddr' : '#34', # Timer/Counter1 Compare Match A - 'TIMER1_COMPBAddr' : '#36', # Timer/Counter1 Compare Match B - 'TIMER1_COMPCAddr' : '#38', # Timer/Counter1 Compare Match C - 'TIMER1_OVFAddr' : '#40', # Timer/Counter1 Overflow - 'TIMER0_COMPAAddr' : '#42', # Timer/Counter0 Compare Match A - 'TIMER0_COMPBAddr' : '#44', # Timer/Counter0 Compare Match B - 'TIMER0_OVFAddr' : '#46', # Timer/Counter0 Overflow - 'SPI_STCAddr' : '#48', # SPI Serial Transfer Complete - 'USART0_RXAddr' : '#50', # USART0, Rx Complete - 'USART0_UDREAddr' : '#52', # USART0 Data register Empty - 'USART0_TXAddr' : '#54', # USART0, Tx Complete - 'ANALOG_COMPAddr' : '#56', # Analog Comparator - 'ADCAddr' : '#58', # ADC Conversion Complete - 'EE_READYAddr' : '#60', # EEPROM Ready - 'TIMER3_CAPTAddr' : '#62', # Timer/Counter3 Capture Event - 'TIMER3_COMPAAddr' : '#64', # Timer/Counter3 Compare Match A - 'TIMER3_COMPBAddr' : '#66', # Timer/Counter3 Compare Match B - 'TIMER3_COMPCAddr' : '#68', # Timer/Counter3 Compare Match C - 'TIMER3_OVFAddr' : '#70', # Timer/Counter3 Overflow - 'USART1_RXAddr' : '#72', # USART1, Rx Complete - 'USART1_UDREAddr' : '#74', # USART1 Data register Empty - 'USART1_TXAddr' : '#76', # USART1, Tx Complete - 'TWIAddr' : '#78', # 2-wire Serial Interface - 'SPM_READYAddr' : '#80', # Store Program Memory Read - 'TIMER4_CAPTAddr' : '#82', # Timer/Counter4 Capture Event - 'TIMER4_COMPAAddr' : '#84', # Timer/Counter4 Compare Match A - 'TIMER4_COMPBAddr' : '#86', # Timer/Counter4 Compare Match B - 'TIMER4_COMPCAddr' : '#88', # Timer/Counter4 Compare Match C - 'TIMER4_OVFAddr' : '#90', # Timer/Counter4 Overflow - 'TIMER5_CAPTAddr' : '#92', # Timer/Counter5 Capture Event - 'TIMER5_COMPAAddr' : '#94', # Timer/Counter5 Compare Match A - 'TIMER5_COMPBAddr' : '#96', # Timer/Counter5 Compare Match B - 'TIMER5_COMPCAddr' : '#98', # Timer/Counter5 Compare Match C - 'TIMER5_OVFAddr' : '#100', # Timer/Counter5 Overflow - 'USART2_RXAddr' : '#102', # USART2, Rx Complete - 'USART2_UDREAddr' : '#104', # USART2 Data register Empty - 'USART2_TXAddr' : '#106', # USART2, Tx Complete - 'USART3_RXAddr' : '#108', # USART3, Rx Complete - 'USART3_UDREAddr' : '#110', # USART3 Data register Empty - 'USART3_TXAddr' : '#112', # USART3, Tx Complete - -# Module ANALOG_COMPARATOR - 'ADCSRB' : '$7b', # ADC Control and Status Registe - 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer - 'ACSR' : '$50', # Analog Comparator Control And - 'ACSR_ACD': '$80', # Analog Comparator Disable - 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele - 'ACSR_ACO': '$20', # Analog Compare Output - 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl - 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En - 'ACSR_ACIC': '$4', # Analog Comparator Input Captur - 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo - 'DIDR1' : '$7f', # Digital Input Disable Register - 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable - 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable - -# Module USART0 - 'UDR0' : '$c6', # USART I/O Data Register - 'UCSR0A' : '$c0', # USART Control and Status Regis - 'UCSR0A_RXC0': '$80', # USART Receive Complete - 'UCSR0A_TXC0': '$40', # USART Transmitt Complete - 'UCSR0A_UDRE0': '$20', # USART Data Register Empty - 'UCSR0A_FE0': '$10', # Framing Error - 'UCSR0A_DOR0': '$8', # Data overRun - 'UCSR0A_UPE0': '$4', # Parity Error - 'UCSR0A_U2X0': '$2', # Double the USART transmission - 'UCSR0A_MPCM0': '$1', # Multi-processor Communication - 'UCSR0B' : '$c1', # USART Control and Status Regis - 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable - 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable - 'UCSR0B_UDRIE0': '$20', # USART Data register Empty Inte - 'UCSR0B_RXEN0': '$10', # Receiver Enable - 'UCSR0B_TXEN0': '$8', # Transmitter Enable - 'UCSR0B_UCSZ02': '$4', # Character Size - 'UCSR0B_RXB80': '$2', # Receive Data Bit 8 - 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8 - 'UCSR0C' : '$c2', # USART Control and Status Regis - 'UCSR0C_UMSEL0': '$c0', # USART Mode Select - 'UCSR0C_UPM0': '$30', # Parity Mode Bits - 'UCSR0C_USBS0': '$8', # Stop Bit Select - 'UCSR0C_UCSZ0': '$6', # Character Size - 'UCSR0C_UCPOL0': '$1', # Clock Polarity - 'UBRR0' : '$c4', # USART Baud Rate Register Byte - -# Module TWI - 'TWAMR' : '$bd', # TWI (Slave) Address Mask Regis - 'TWAMR_TWAM': '$fe', # - 'TWBR' : '$b8', # TWI Bit Rate register - 'TWCR' : '$bc', # TWI Control Register - 'TWCR_TWINT': '$80', # TWI Interrupt Flag - 'TWCR_TWEA': '$40', # TWI Enable Acknowledge Bit - 'TWCR_TWSTA': '$20', # TWI Start Condition Bit - 'TWCR_TWSTO': '$10', # TWI Stop Condition Bit - 'TWCR_TWWC': '$8', # TWI Write Collition Flag - 'TWCR_TWEN': '$4', # TWI Enable Bit - 'TWCR_TWIE': '$1', # TWI Interrupt Enable - 'TWSR' : '$b9', # TWI Status Register - 'TWSR_TWS': '$f8', # TWI Status - 'TWSR_TWPS': '$3', # TWI Prescaler - 'TWDR' : '$bb', # TWI Data register - 'TWAR' : '$ba', # TWI (Slave) Address register - 'TWAR_TWA': '$fe', # TWI (Slave) Address register B - 'TWAR_TWGCE': '$1', # TWI General Call Recognition E - -# Module SPI - 'SPCR' : '$4c', # SPI Control Register - 'SPCR_SPIE': '$80', # SPI Interrupt Enable - 'SPCR_SPE': '$40', # SPI Enable - 'SPCR_DORD': '$20', # Data Order - 'SPCR_MSTR': '$10', # Master/Slave Select - 'SPCR_CPOL': '$8', # Clock polarity - 'SPCR_CPHA': '$4', # Clock Phase - 'SPCR_SPR': '$3', # SPI Clock Rate Selects - 'SPSR' : '$4d', # SPI Status Register - 'SPSR_SPIF': '$80', # SPI Interrupt Flag - 'SPSR_WCOL': '$40', # Write Collision Flag - 'SPSR_SPI2X': '$1', # Double SPI Speed Bit - 'SPDR' : '$4e', # SPI Data Register - -# Module PORTA - 'PORTA' : '$22', # Port A Data Register - 'DDRA' : '$21', # Port A Data Direction Register - 'PINA' : '$20', # Port A Input Pins - -# Module PORTB - 'PORTB' : '$25', # Port B Data Register - 'DDRB' : '$24', # Port B Data Direction Register - 'PINB' : '$23', # Port B Input Pins - -# Module PORTC - 'PORTC' : '$28', # Port C Data Register - 'DDRC' : '$27', # Port C Data Direction Register - 'PINC' : '$26', # Port C Input Pins - -# Module PORTD - 'PORTD' : '$2b', # Port D Data Register - 'DDRD' : '$2a', # Port D Data Direction Register - 'PIND' : '$29', # Port D Input Pins - -# Module PORTE - 'PORTE' : '$2e', # Data Register, Port E - 'DDRE' : '$2d', # Data Direction Register, Port - 'PINE' : '$2c', # Input Pins, Port E - -# Module PORTF - 'PORTF' : '$31', # Data Register, Port F - 'DDRF' : '$30', # Data Direction Register, Port - 'PINF' : '$2f', # Input Pins, Port F - -# Module PORTG - 'PORTG' : '$34', # Data Register, Port G - 'DDRG' : '$33', # Data Direction Register, Port - 'PING' : '$32', # Input Pins, Port G - -# Module PORTH - 'PORTH' : '$102', # PORT H Data Register - 'DDRH' : '$101', # PORT H Data Direction Register - 'PINH' : '$100', # PORT H Input Pins - -# Module PORTJ - 'PORTJ' : '$105', # PORT J Data Register - 'DDRJ' : '$104', # PORT J Data Direction Register - 'PINJ' : '$103', # PORT J Input Pins - -# Module PORTK - 'PORTK' : '$108', # PORT K Data Register - 'DDRK' : '$107', # PORT K Data Direction Register - 'PINK' : '$106', # PORT K Input Pins - -# Module PORTL - 'PORTL' : '$10b', # PORT L Data Register - 'DDRL' : '$10a', # PORT L Data Direction Register - 'PINL' : '$109', # PORT L Input Pins - -# Module TIMER_COUNTER_0 - 'OCR0B' : '$48', # Timer/Counter0 Output Compare - 'OCR0A' : '$47', # Timer/Counter0 Output Compare - 'TCNT0' : '$46', # Timer/Counter0 - 'TCCR0B' : '$45', # Timer/Counter Control Register - 'TCCR0B_FOC0A': '$80', # Force Output Compare A - 'TCCR0B_FOC0B': '$40', # Force Output Compare B - 'TCCR0B_WGM02': '$8', # - 'TCCR0B_CS0': '$7', # Clock Select - 'TCCR0A' : '$44', # Timer/Counter Control Registe - 'TCCR0A_COM0A': '$c0', # Compare Output Mode, Phase Cor - 'TCCR0A_COM0B': '$30', # Compare Output Mode, Fast PWm - 'TCCR0A_WGM0': '$3', # Waveform Generation Mode - 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask - 'TIMSK0_OCIE0B': '$4', # Timer/Counter0 Output Compare - 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare - 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr - 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag - 'TIFR0_OCF0B': '$4', # Timer/Counter0 Output Compare - 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare - 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag - 'GTCCR' : '$43', # General Timer/Counter Control - 'GTCCR_TSM': '$80', # Timer/Counter Synchronization - 'GTCCR_PSRSYNC': '$1', # Prescaler Reset Timer/Counter1 - -# Module TIMER_COUNTER_2 - 'TIMSK2' : '$70', # Timer/Counter Interrupt Mask r - 'TIMSK2_OCIE2B': '$4', # Timer/Counter2 Output Compare - 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare - 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr - 'TIFR2' : '$37', # Timer/Counter Interrupt Flag R - 'TIFR2_OCF2B': '$4', # Output Compare Flag 2B - 'TIFR2_OCF2A': '$2', # Output Compare Flag 2A - 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag - 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe - 'TCCR2A_COM2A': '$c0', # Compare Output Mode bits - 'TCCR2A_COM2B': '$30', # Compare Output Mode bits - 'TCCR2A_WGM2': '$3', # Waveform Genration Mode - 'TCCR2B' : '$b1', # Timer/Counter2 Control Registe - 'TCCR2B_FOC2A': '$80', # Force Output Compare A - 'TCCR2B_FOC2B': '$40', # Force Output Compare B - 'TCCR2B_WGM22': '$8', # Waveform Generation Mode - 'TCCR2B_CS2': '$7', # Clock Select bits - 'TCNT2' : '$b2', # Timer/Counter2 - 'OCR2B' : '$b4', # Timer/Counter2 Output Compare - 'OCR2A' : '$b3', # Timer/Counter2 Output Compare - 'ASSR' : '$b6', # Asynchronous Status Register - 'ASSR_EXCLK': '$40', # Enable External Clock Input - 'ASSR_AS2': '$20', # Asynchronous Timer/Counter2 - 'ASSR_TCN2UB': '$10', # Timer/Counter2 Update Busy - 'ASSR_OCR2AUB': '$8', # Output Compare Register2 Updat - 'ASSR_OCR2BUB': '$4', # Output Compare Register 2 Upda - 'ASSR_TCR2AUB': '$2', # Timer/Counter Control Register - 'ASSR_TCR2BUB': '$1', # Timer/Counter Control Register - 'GTCCR' : '$43', # General Timer Counter Control - 'GTCCR_TSM': '$80', # Timer/Counter Synchronization - 'GTCCR_PSRASY': '$2', # Prescaler Reset Timer/Counter2 - -# Module WATCHDOG - 'WDTCSR' : '$60', # Watchdog Timer Control Registe - 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla - 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena - 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits - 'WDTCSR_WDCE': '$10', # Watchdog Change Enable - 'WDTCSR_WDE': '$8', # Watch Dog Enable - -# Module USART1 - 'UDR1' : '$ce', # USART I/O Data Register - 'UCSR1A' : '$c8', # USART Control and Status Regis - 'UCSR1A_RXC1': '$80', # USART Receive Complete - 'UCSR1A_TXC1': '$40', # USART Transmitt Complete - 'UCSR1A_UDRE1': '$20', # USART Data Register Empty - 'UCSR1A_FE1': '$10', # Framing Error - 'UCSR1A_DOR1': '$8', # Data overRun - 'UCSR1A_UPE1': '$4', # Parity Error - 'UCSR1A_U2X1': '$2', # Double the USART transmission - 'UCSR1A_MPCM1': '$1', # Multi-processor Communication - 'UCSR1B' : '$c9', # USART Control and Status Regis - 'UCSR1B_RXCIE1': '$80', # RX Complete Interrupt Enable - 'UCSR1B_TXCIE1': '$40', # TX Complete Interrupt Enable - 'UCSR1B_UDRIE1': '$20', # USART Data register Empty Inte - 'UCSR1B_RXEN1': '$10', # Receiver Enable - 'UCSR1B_TXEN1': '$8', # Transmitter Enable - 'UCSR1B_UCSZ12': '$4', # Character Size - 'UCSR1B_RXB81': '$2', # Receive Data Bit 8 - 'UCSR1B_TXB81': '$1', # Transmit Data Bit 8 - 'UCSR1C' : '$ca', # USART Control and Status Regis - 'UCSR1C_UMSEL1': '$c0', # USART Mode Select - 'UCSR1C_UPM1': '$30', # Parity Mode Bits - 'UCSR1C_USBS1': '$8', # Stop Bit Select - 'UCSR1C_UCSZ1': '$6', # Character Size - 'UCSR1C_UCPOL1': '$1', # Clock Polarity - 'UBRR1' : '$cc', # USART Baud Rate Register Byte - -# Module EEPROM - 'EEAR' : '$41', # EEPROM Address Register Low By - 'EEDR' : '$40', # EEPROM Data Register - 'EECR' : '$3f', # EEPROM Control Register - 'EECR_EEPM': '$30', # EEPROM Programming Mode Bits - 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable - 'EECR_EEMPE': '$4', # EEPROM Master Write Enable - 'EECR_EEPE': '$2', # EEPROM Write Enable - 'EECR_EERE': '$1', # EEPROM Read Enable - -# Module TIMER_COUNTER_5 - 'TCCR5A' : '$120', # Timer/Counter5 Control Registe - 'TCCR5A_COM5A': '$c0', # Compare Output Mode 1A, bits - 'TCCR5A_COM5B': '$30', # Compare Output Mode 5B, bits - 'TCCR5A_COM5C': '$c', # Compare Output Mode 5C, bits - 'TCCR5A_WGM5': '$3', # Waveform Generation Mode - 'TCCR5B' : '$121', # Timer/Counter5 Control Registe - 'TCCR5B_ICNC5': '$80', # Input Capture 5 Noise Canceler - 'TCCR5B_ICES5': '$40', # Input Capture 5 Edge Select - 'TCCR5B_WGM5': '$18', # Waveform Generation Mode - 'TCCR5B_CS5': '$7', # Prescaler source of Timer/Coun - 'TCCR5C' : '$122', # Timer/Counter 5 Control Regist - 'TCCR5C_FOC5A': '$80', # Force Output Compare 5A - 'TCCR5C_FOC5B': '$40', # Force Output Compare 5B - 'TCCR5C_FOC5C': '$20', # Force Output Compare 5C - 'TCNT5' : '$124', # Timer/Counter5 Bytes - 'OCR5A' : '$128', # Timer/Counter5 Output Compare - 'OCR5B' : '$12a', # Timer/Counter5 Output Compare - 'OCR5C' : '$12c', # Timer/Counter5 Output Compare - 'ICR5' : '$126', # Timer/Counter5 Input Capture R - 'TIMSK5' : '$73', # Timer/Counter5 Interrupt Mask - 'TIMSK5_ICIE5': '$20', # Timer/Counter5 Input Capture I - 'TIMSK5_OCIE5C': '$8', # Timer/Counter5 Output Compare - 'TIMSK5_OCIE5B': '$4', # Timer/Counter5 Output Compare - 'TIMSK5_OCIE5A': '$2', # Timer/Counter5 Output Compare - 'TIMSK5_TOIE5': '$1', # Timer/Counter5 Overflow Interr - 'TIFR5' : '$3a', # Timer/Counter5 Interrupt Flag - 'TIFR5_ICF5': '$20', # Input Capture Flag 5 - 'TIFR5_OCF5C': '$8', # Output Compare Flag 5C - 'TIFR5_OCF5B': '$4', # Output Compare Flag 5B - 'TIFR5_OCF5A': '$2', # Output Compare Flag 5A - 'TIFR5_TOV5': '$1', # Timer/Counter5 Overflow Flag - -# Module TIMER_COUNTER_4 - 'TCCR4A' : '$a0', # Timer/Counter4 Control Registe - 'TCCR4A_COM4A': '$c0', # Compare Output Mode 1A, bits - 'TCCR4A_COM4B': '$30', # Compare Output Mode 4B, bits - 'TCCR4A_COM4C': '$c', # Compare Output Mode 4C, bits - 'TCCR4A_WGM4': '$3', # Waveform Generation Mode - 'TCCR4B' : '$a1', # Timer/Counter4 Control Registe - 'TCCR4B_ICNC4': '$80', # Input Capture 4 Noise Canceler - 'TCCR4B_ICES4': '$40', # Input Capture 4 Edge Select - 'TCCR4B_WGM4': '$18', # Waveform Generation Mode - 'TCCR4B_CS4': '$7', # Prescaler source of Timer/Coun - 'TCCR4C' : '$a2', # Timer/Counter 4 Control Regist - 'TCCR4C_FOC4A': '$80', # Force Output Compare 4A - 'TCCR4C_FOC4B': '$40', # Force Output Compare 4B - 'TCCR4C_FOC4C': '$20', # Force Output Compare 4C - 'TCNT4' : '$a4', # Timer/Counter4 Bytes - 'OCR4A' : '$a8', # Timer/Counter4 Output Compare - 'OCR4B' : '$aa', # Timer/Counter4 Output Compare - 'OCR4C' : '$ac', # Timer/Counter4 Output Compare - 'ICR4' : '$a6', # Timer/Counter4 Input Capture R - 'TIMSK4' : '$72', # Timer/Counter4 Interrupt Mask - 'TIMSK4_ICIE4': '$20', # Timer/Counter4 Input Capture I - 'TIMSK4_OCIE4C': '$8', # Timer/Counter4 Output Compare - 'TIMSK4_OCIE4B': '$4', # Timer/Counter4 Output Compare - 'TIMSK4_OCIE4A': '$2', # Timer/Counter4 Output Compare - 'TIMSK4_TOIE4': '$1', # Timer/Counter4 Overflow Interr - 'TIFR4' : '$39', # Timer/Counter4 Interrupt Flag - 'TIFR4_ICF4': '$20', # Input Capture Flag 4 - 'TIFR4_OCF4C': '$8', # Output Compare Flag 4C - 'TIFR4_OCF4B': '$4', # Output Compare Flag 4B - 'TIFR4_OCF4A': '$2', # Output Compare Flag 4A - 'TIFR4_TOV4': '$1', # Timer/Counter4 Overflow Flag - -# Module TIMER_COUNTER_3 - 'TCCR3A' : '$90', # Timer/Counter3 Control Registe - 'TCCR3A_COM3A': '$c0', # Compare Output Mode 1A, bits - 'TCCR3A_COM3B': '$30', # Compare Output Mode 3B, bits - 'TCCR3A_COM3C': '$c', # Compare Output Mode 3C, bits - 'TCCR3A_WGM3': '$3', # Waveform Generation Mode - 'TCCR3B' : '$91', # Timer/Counter3 Control Registe - 'TCCR3B_ICNC3': '$80', # Input Capture 3 Noise Canceler - 'TCCR3B_ICES3': '$40', # Input Capture 3 Edge Select - 'TCCR3B_WGM3': '$18', # Waveform Generation Mode - 'TCCR3B_CS3': '$7', # Prescaler source of Timer/Coun - 'TCCR3C' : '$92', # Timer/Counter 3 Control Regist - 'TCCR3C_FOC3A': '$80', # Force Output Compare 3A - 'TCCR3C_FOC3B': '$40', # Force Output Compare 3B - 'TCCR3C_FOC3C': '$20', # Force Output Compare 3C - 'TCNT3' : '$94', # Timer/Counter3 Bytes - 'OCR3A' : '$98', # Timer/Counter3 Output Compare - 'OCR3B' : '$9a', # Timer/Counter3 Output Compare - 'OCR3C' : '$9c', # Timer/Counter3 Output Compare - 'ICR3' : '$96', # Timer/Counter3 Input Capture R - 'TIMSK3' : '$71', # Timer/Counter3 Interrupt Mask - 'TIMSK3_ICIE3': '$20', # Timer/Counter3 Input Capture I - 'TIMSK3_OCIE3C': '$8', # Timer/Counter3 Output Compare - 'TIMSK3_OCIE3B': '$4', # Timer/Counter3 Output Compare - 'TIMSK3_OCIE3A': '$2', # Timer/Counter3 Output Compare - 'TIMSK3_TOIE3': '$1', # Timer/Counter3 Overflow Interr - 'TIFR3' : '$38', # Timer/Counter3 Interrupt Flag - 'TIFR3_ICF3': '$20', # Input Capture Flag 3 - 'TIFR3_OCF3C': '$8', # Output Compare Flag 3C - 'TIFR3_OCF3B': '$4', # Output Compare Flag 3B - 'TIFR3_OCF3A': '$2', # Output Compare Flag 3A - 'TIFR3_TOV3': '$1', # Timer/Counter3 Overflow Flag - -# Module TIMER_COUNTER_1 - 'TCCR1A' : '$80', # Timer/Counter1 Control Registe - 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits - 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits - 'TCCR1A_COM1C': '$c', # Compare Output Mode 1C, bits - 'TCCR1A_WGM1': '$3', # Waveform Generation Mode - 'TCCR1B' : '$81', # Timer/Counter1 Control Registe - 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler - 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select - 'TCCR1B_WGM1': '$18', # Waveform Generation Mode - 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun - 'TCCR1C' : '$82', # Timer/Counter 1 Control Regist - 'TCCR1C_FOC1A': '$80', # Force Output Compare 1A - 'TCCR1C_FOC1B': '$40', # Force Output Compare 1B - 'TCCR1C_FOC1C': '$20', # Force Output Compare 1C - 'TCNT1' : '$84', # Timer/Counter1 Bytes - 'OCR1A' : '$88', # Timer/Counter1 Output Compare - 'OCR1B' : '$8a', # Timer/Counter1 Output Compare - 'OCR1C' : '$8c', # Timer/Counter1 Output Compare - 'ICR1' : '$86', # Timer/Counter1 Input Capture R - 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask - 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I - 'TIMSK1_OCIE1C': '$8', # Timer/Counter1 Output Compare - 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare - 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare - 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr - 'TIFR1' : '$36', # Timer/Counter1 Interrupt Flag - 'TIFR1_ICF1': '$20', # Input Capture Flag 1 - 'TIFR1_OCF1C': '$8', # Output Compare Flag 1C - 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B - 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A - 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag - -# Module JTAG - 'OCDR' : '$51', # On-Chip Debug Related Register - 'MCUCR' : '$55', # MCU Control Register - 'MCUCR_JTD': '$80', # JTAG Interface Disable - 'MCUSR' : '$54', # MCU Status Register - 'MCUSR_JTRF': '$10', # JTAG Reset Flag - -# Module EXTERNAL_INTERRUPT - 'EICRA' : '$69', # External Interrupt Control Reg - 'EICRA_ISC3': '$c0', # External Interrupt Sense Contr - 'EICRA_ISC2': '$30', # External Interrupt Sense Contr - 'EICRA_ISC1': '$c', # External Interrupt Sense Contr - 'EICRA_ISC0': '$3', # External Interrupt Sense Contr - 'EICRB' : '$6a', # External Interrupt Control Reg - 'EICRB_ISC7': '$c0', # External Interrupt 7-4 Sense C - 'EICRB_ISC6': '$30', # External Interrupt 7-4 Sense C - 'EICRB_ISC5': '$c', # External Interrupt 7-4 Sense C - 'EICRB_ISC4': '$3', # External Interrupt 7-4 Sense C - 'EIMSK' : '$3d', # External Interrupt Mask Regist - 'EIMSK_INT': '$ff', # External Interrupt Request 7 E - 'EIFR' : '$3c', # External Interrupt Flag Regist - 'EIFR_INTF': '$ff', # External Interrupt Flags - 'PCMSK2' : '$6d', # Pin Change Mask Register 2 - 'PCMSK1' : '$6c', # Pin Change Mask Register 1 - 'PCMSK0' : '$6b', # Pin Change Mask Register 0 - 'PCIFR' : '$3b', # Pin Change Interrupt Flag Regi - 'PCIFR_PCIF': '$7', # Pin Change Interrupt Flags - 'PCICR' : '$68', # Pin Change Interrupt Control R - 'PCICR_PCIE': '$7', # Pin Change Interrupt Enables - -# Module CPU - 'SREG' : '$5f', # Status Register - 'SREG_I': '$80', # Global Interrupt Enable - 'SREG_T': '$40', # Bit Copy Storage - 'SREG_H': '$20', # Half Carry Flag - 'SREG_S': '$10', # Sign Bit - 'SREG_V': '$8', # Two's Complement Overflow Flag - 'SREG_N': '$4', # Negative Flag - 'SREG_Z': '$2', # Zero Flag - 'SREG_C': '$1', # Carry Flag - 'SP' : '$5d', # Stack Pointer - 'MCUCR' : '$55', # MCU Control Register - 'MCUCR_JTD': '$80', # JTAG Interface Disable - 'MCUCR_PUD': '$10', # Pull-up disable - 'MCUCR_IVSEL': '$2', # Interrupt Vector Select - 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable - 'MCUSR' : '$54', # MCU Status Register - 'MCUSR_JTRF': '$10', # JTAG Reset Flag - 'MCUSR_WDRF': '$8', # Watchdog Reset Flag - 'MCUSR_BORF': '$4', # Brown-out Reset Flag - 'MCUSR_EXTRF': '$2', # External Reset Flag - 'MCUSR_PORF': '$1', # Power-on reset flag - 'XMCRA' : '$74', # External Memory Control Regist - 'XMCRA_SRE': '$80', # External SRAM Enable - 'XMCRA_SRL': '$70', # Wait state page limit - 'XMCRA_SRW1': '$c', # Wait state select bit upper pa - 'XMCRA_SRW0': '$3', # Wait state select bit lower pa - 'XMCRB' : '$75', # External Memory Control Regist - 'XMCRB_XMBK': '$80', # External Memory Bus Keeper Ena - 'XMCRB_XMM': '$7', # External Memory High Mask - 'OSCCAL' : '$66', # Oscillator Calibration Value - 'CLKPR' : '$61', # - 'CLKPR_CLKPCE': '$80', # - 'CLKPR_CLKPS': '$f', # - 'SMCR' : '$53', # Sleep Mode Control Register - 'SMCR_SM': '$e', # Sleep Mode Select bits - 'SMCR_SE': '$1', # Sleep Enable - 'EIND' : '$5c', # Extended Indirect Register - 'GPIOR2' : '$4b', # General Purpose IO Register 2 - 'GPIOR2_GPIOR': '$ff', # General Purpose IO Register 2 - 'GPIOR1' : '$4a', # General Purpose IO Register 1 - 'GPIOR1_GPIOR': '$ff', # General Purpose IO Register 1 - 'GPIOR0' : '$3e', # General Purpose IO Register 0 - 'GPIOR0_GPIOR07': '$80', # General Purpose IO Register 0 - 'GPIOR0_GPIOR06': '$40', # General Purpose IO Register 0 - 'GPIOR0_GPIOR05': '$20', # General Purpose IO Register 0 - 'GPIOR0_GPIOR04': '$10', # General Purpose IO Register 0 - 'GPIOR0_GPIOR03': '$8', # General Purpose IO Register 0 - 'GPIOR0_GPIOR02': '$4', # General Purpose IO Register 0 - 'GPIOR0_GPIOR01': '$2', # General Purpose IO Register 0 - 'GPIOR0_GPIOR00': '$1', # General Purpose IO Register 0 - 'PRR1' : '$65', # Power Reduction Register1 - 'PRR1_PRTIM5': '$20', # Power Reduction Timer/Counter5 - 'PRR1_PRTIM4': '$10', # Power Reduction Timer/Counter4 - 'PRR1_PRTIM3': '$8', # Power Reduction Timer/Counter3 - 'PRR1_PRUSART': '$7', # Power Reduction USART3 - 'PRR0' : '$64', # Power Reduction Register0 - 'PRR0_PRTWI': '$80', # Power Reduction TWI - 'PRR0_PRTIM2': '$40', # Power Reduction Timer/Counter2 - 'PRR0_PRTIM0': '$20', # Power Reduction Timer/Counter0 - 'PRR0_PRTIM1': '$8', # Power Reduction Timer/Counter1 - 'PRR0_PRSPI': '$4', # Power Reduction Serial Periphe - 'PRR0_PRUSART0': '$2', # Power Reduction USART - 'PRR0_PRADC': '$1', # Power Reduction ADC - -# Module AD_CONVERTER - 'ADMUX' : '$7c', # The ADC multiplexer Selection - 'ADMUX_REFS': '$c0', # Reference Selection Bits - 'ADMUX_ADLAR': '$20', # Left Adjust Result - 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select - 'ADC' : '$78', # ADC Data Register Bytes - 'ADCSRA' : '$7a', # The ADC Control and Status reg - 'ADCSRA_ADEN': '$80', # ADC Enable - 'ADCSRA_ADSC': '$40', # ADC Start Conversion - 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable - 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag - 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable - 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits - 'ADCSRB' : '$7b', # The ADC Control and Status reg - 'ADCSRB_ACME': '$40', # - 'ADCSRB_MUX5': '$8', # Analog Channel and Gain Select - 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Source bits - 'DIDR2' : '$7d', # Digital Input Disable Register - 'DIDR2_ADC15D': '$80', # - 'DIDR2_ADC14D': '$40', # - 'DIDR2_ADC13D': '$20', # - 'DIDR2_ADC12D': '$10', # - 'DIDR2_ADC11D': '$8', # - 'DIDR2_ADC10D': '$4', # - 'DIDR2_ADC9D': '$2', # - 'DIDR2_ADC8D': '$1', # - 'DIDR0' : '$7e', # Digital Input Disable Register - 'DIDR0_ADC7D': '$80', # - 'DIDR0_ADC6D': '$40', # - 'DIDR0_ADC5D': '$20', # - 'DIDR0_ADC4D': '$10', # - 'DIDR0_ADC3D': '$8', # - 'DIDR0_ADC2D': '$4', # - 'DIDR0_ADC1D': '$2', # - 'DIDR0_ADC0D': '$1', # - -# Module BOOT_LOAD - 'SPMCSR' : '$57', # Store Program Memory Control R - 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable - 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy - 'SPMCSR_SIGRD': '$20', # Signature Row Read - 'SPMCSR_RWWSRE': '$10', # Read While Write section read - 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set - 'SPMCSR_PGWRT': '$4', # Page Write - 'SPMCSR_PGERS': '$2', # Page Erase - 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable - -# Module USART2 - 'UDR2' : '$d6', # USART I/O Data Register - 'UCSR2A' : '$d0', # USART Control and Status Regis - 'UCSR2A_RXC2': '$80', # USART Receive Complete - 'UCSR2A_TXC2': '$40', # USART Transmitt Complete - 'UCSR2A_UDRE2': '$20', # USART Data Register Empty - 'UCSR2A_FE2': '$10', # Framing Error - 'UCSR2A_DOR2': '$8', # Data overRun - 'UCSR2A_UPE2': '$4', # Parity Error - 'UCSR2A_U2X2': '$2', # Double the USART transmission - 'UCSR2A_MPCM2': '$1', # Multi-processor Communication - 'UCSR2B' : '$d1', # USART Control and Status Regis - 'UCSR2B_RXCIE2': '$80', # RX Complete Interrupt Enable - 'UCSR2B_TXCIE2': '$40', # TX Complete Interrupt Enable - 'UCSR2B_UDRIE2': '$20', # USART Data register Empty Inte - 'UCSR2B_RXEN2': '$10', # Receiver Enable - 'UCSR2B_TXEN2': '$8', # Transmitter Enable - 'UCSR2B_UCSZ22': '$4', # Character Size - 'UCSR2B_RXB82': '$2', # Receive Data Bit 8 - 'UCSR2B_TXB82': '$1', # Transmit Data Bit 8 - 'UCSR2C' : '$d2', # USART Control and Status Regis - 'UCSR2C_UMSEL2': '$c0', # USART Mode Select - 'UCSR2C_UPM2': '$30', # Parity Mode Bits - 'UCSR2C_USBS2': '$8', # Stop Bit Select - 'UCSR2C_UCSZ2': '$6', # Character Size - 'UCSR2C_UCPOL2': '$1', # Clock Polarity - 'UBRR2' : '$d4', # USART Baud Rate Register Byte - -# Module USART3 - 'UDR3' : '$136', # USART I/O Data Register - 'UCSR3A' : '$130', # USART Control and Status Regis - 'UCSR3A_RXC3': '$80', # USART Receive Complete - 'UCSR3A_TXC3': '$40', # USART Transmitt Complete - 'UCSR3A_UDRE3': '$20', # USART Data Register Empty - 'UCSR3A_FE3': '$10', # Framing Error - 'UCSR3A_DOR3': '$8', # Data overRun - 'UCSR3A_UPE3': '$4', # Parity Error - 'UCSR3A_U2X3': '$2', # Double the USART transmission - 'UCSR3A_MPCM3': '$1', # Multi-processor Communication - 'UCSR3B' : '$131', # USART Control and Status Regis - 'UCSR3B_RXCIE3': '$80', # RX Complete Interrupt Enable - 'UCSR3B_TXCIE3': '$40', # TX Complete Interrupt Enable - 'UCSR3B_UDRIE3': '$20', # USART Data register Empty Inte - 'UCSR3B_RXEN3': '$10', # Receiver Enable - 'UCSR3B_TXEN3': '$8', # Transmitter Enable - 'UCSR3B_UCSZ32': '$4', # Character Size - 'UCSR3B_RXB83': '$2', # Receive Data Bit 8 - 'UCSR3B_TXB83': '$1', # Transmit Data Bit 8 - 'UCSR3C' : '$132', # USART Control and Status Regis - 'UCSR3C_UMSEL3': '$c0', # USART Mode Select - 'UCSR3C_UPM3': '$30', # Parity Mode Bits - 'UCSR3C_USBS3': '$8', # Stop Bit Select - 'UCSR3C_UCSZ3': '$6', # Character Size - 'UCSR3C_UCPOL3': '$1', # Clock Polarity - 'UBRR3' : '$134', # USART Baud Rate Register Byte - - '__amforth_dummy':'0' -} diff --git a/amforth-6.5/avr8/devices/atmega640/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega640/words/no-jtag.asm deleted file mode 100644 index 352a4bb..0000000 --- a/amforth-6.5/avr8/devices/atmega640/words/no-jtag.asm +++ /dev/null @@ -1,14 +0,0 @@ -; ( -- ) -; ( -- ) -; MCU -; disable jtag at runtime -VE_NOJTAG: - .dw $FF05 - .db "-jtag",0 - .dw VE_HEAD - .set VE_HEAD = VE_NOJTAG -XT_NOJTAG: - .dw PFA_NOJTAG -PFA_NOJTAG: - - jmp_ DO_NEXT diff --git a/amforth-6.5/avr8/devices/atmega640/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega640/words/no-wdt.asm deleted file mode 100644 index ff6ddd1..0000000 --- a/amforth-6.5/avr8/devices/atmega640/words/no-wdt.asm +++ /dev/null @@ -1,34 +0,0 @@ -; ( -- ) -; MCU -; disable watch dog timer at runtime -VE_NOWDT: - .dw $ff04 - .db "-wdt" - .dw VE_HEAD - .set VE_HEAD = VE_NOWDT -XT_NOWDT: - .dw PFA_NOWDT -PFA_NOWDT: - - in temp1,SREG - push temp1 - ; Turn always off global interrupt. - cli - ; Reset Watchdog Timer - wdr - ; Clear WDRF in MCUSR - in temp1, MCUSR - andi temp1, (0xff & (0<