From d80736ab6e8e3cad2f1a30c6eaba2d6883dbe967 Mon Sep 17 00:00:00 2001 From: Dimitri Sokolyuk Date: Sat, 26 Aug 2017 20:31:40 +0200 Subject: Remove AmForth --- .../avr8/devices/atmega6450p/atmega6450p.frt | 298 ----- amforth-6.5/avr8/devices/atmega6450p/device.asm | 114 -- amforth-6.5/avr8/devices/atmega6450p/device.inc | 1152 -------------------- amforth-6.5/avr8/devices/atmega6450p/device.py | 333 ------ .../avr8/devices/atmega6450p/words/no-jtag.asm | 14 - .../avr8/devices/atmega6450p/words/no-wdt.asm | 22 - .../avr8/devices/atmega6450p/words/sleep.asm | 19 - 7 files changed, 1952 deletions(-) delete mode 100644 amforth-6.5/avr8/devices/atmega6450p/atmega6450p.frt delete mode 100644 amforth-6.5/avr8/devices/atmega6450p/device.asm delete mode 100644 amforth-6.5/avr8/devices/atmega6450p/device.inc delete mode 100644 amforth-6.5/avr8/devices/atmega6450p/device.py delete mode 100644 amforth-6.5/avr8/devices/atmega6450p/words/no-jtag.asm delete mode 100644 amforth-6.5/avr8/devices/atmega6450p/words/no-wdt.asm delete mode 100644 amforth-6.5/avr8/devices/atmega6450p/words/sleep.asm (limited to 'amforth-6.5/avr8/devices/atmega6450p') diff --git a/amforth-6.5/avr8/devices/atmega6450p/atmega6450p.frt b/amforth-6.5/avr8/devices/atmega6450p/atmega6450p.frt deleted file mode 100644 index 6051089..0000000 --- a/amforth-6.5/avr8/devices/atmega6450p/atmega6450p.frt +++ /dev/null @@ -1,298 +0,0 @@ -\ Partname: ATmega6450P -\ generated automatically - -\ AD_CONVERTER -&124 constant ADMUX \ The ADC multiplexer Selection Register - $C0 constant ADMUX_REFS \ Reference Selection Bits - $20 constant ADMUX_ADLAR \ Left Adjust Result - $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits -&122 constant ADCSRA \ The ADC Control and Status register - $80 constant ADCSRA_ADEN \ ADC Enable - $40 constant ADCSRA_ADSC \ ADC Start Conversion - $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable - $10 constant ADCSRA_ADIF \ ADC Interrupt Flag - $08 constant ADCSRA_ADIE \ ADC Interrupt Enable - $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits -&120 constant ADC \ ADC Data Register Bytes -&123 constant ADCSRB \ ADC Control and Status Register B - $07 constant ADCSRB_ADTS \ ADC Auto Trigger Sources -&126 constant DIDR0 \ Digital Input Disable Register 0 - $80 constant DIDR0_ADC7D \ ADC7 Digital input Disable - $40 constant DIDR0_ADC6D \ ADC6 Digital input Disable - $20 constant DIDR0_ADC5D \ ADC5 Digital input Disable - $10 constant DIDR0_ADC4D \ ADC4 Digital input Disable - $08 constant DIDR0_ADC3D \ ADC3 Digital input Disable - $04 constant DIDR0_ADC2D \ ADC2 Digital input Disable - $02 constant DIDR0_ADC1D \ ADC1 Digital input Disable - $01 constant DIDR0_ADC0D \ ADC0 Digital input Disable -\ ANALOG_COMPARATOR -&80 constant ACSR \ Analog Comparator Control And Status Register - $80 constant ACSR_ACD \ Analog Comparator Disable - $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select - $20 constant ACSR_ACO \ Analog Compare Output - $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag - $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable - $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable - $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits -&127 constant DIDR1 \ Digital Input Disable Register 1 - $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable - $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable -\ SPI -&76 constant SPCR \ SPI Control Register - $80 constant SPCR_SPIE \ SPI Interrupt Enable - $40 constant SPCR_SPE \ SPI Enable - $20 constant SPCR_DORD \ Data Order - $10 constant SPCR_MSTR \ Master/Slave Select - $08 constant SPCR_CPOL \ Clock polarity - $04 constant SPCR_CPHA \ Clock Phase - $03 constant SPCR_SPR \ SPI Clock Rate Selects -&77 constant SPSR \ SPI Status Register - $80 constant SPSR_SPIF \ SPI Interrupt Flag - $40 constant SPSR_WCOL \ Write Collision Flag - $01 constant SPSR_SPI2X \ Double SPI Speed Bit -&78 constant SPDR \ SPI Data Register -\ USI -&186 constant USIDR \ USI Data Register -&185 constant USISR \ USI Status Register - $80 constant USISR_USISIF \ Start Condition Interrupt Flag - $40 constant USISR_USIOIF \ Counter Overflow Interrupt Flag - $20 constant USISR_USIPF \ Stop Condition Flag - $10 constant USISR_USIDC \ Data Output Collision - $0F constant USISR_USICNT \ USI Counter Value Bits -&184 constant USICR \ USI Control Register - $80 constant USICR_USISIE \ Start Condition Interrupt Enable - $40 constant USICR_USIOIE \ Counter Overflow Interrupt Enable - $30 constant USICR_USIWM \ USI Wire Mode Bits - $0C constant USICR_USICS \ USI Clock Source Select Bits - $02 constant USICR_USICLK \ Clock Strobe - $01 constant USICR_USITC \ Toggle Clock Port Pin -\ USART0 -&198 constant UDR0 \ USART I/O Data Register -&192 constant UCSR0A \ USART Control and Status Register A - $80 constant UCSR0A_RXC0 \ USART Receive Complete - $40 constant UCSR0A_TXC0 \ USART Transmit Complete - $20 constant UCSR0A_UDRE0 \ USART Data Register Empty - $10 constant UCSR0A_FE0 \ Framing Error - $08 constant UCSR0A_DOR0 \ Data OverRun - $04 constant UCSR0A_UPE0 \ USART Parity Error - $02 constant UCSR0A_U2X0 \ Double the USART Transmission Speed - $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode -&193 constant UCSR0B \ USART Control and Status Register B - $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable - $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable - $20 constant UCSR0B_UDRIE0 \ USART Data Register Empty Interrupt Enable - $10 constant UCSR0B_RXEN0 \ Receiver Enable - $08 constant UCSR0B_TXEN0 \ Transmitter Enable - $04 constant UCSR0B_UCSZ02 \ Character Size - $02 constant UCSR0B_RXB80 \ Receive Data Bit 8 - $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8 -&194 constant UCSR0C \ USART Control and Status Register C - $40 constant UCSR0C_UMSEL0 \ USART Mode Select - $30 constant UCSR0C_UPM0 \ Parity Mode Bits - $08 constant UCSR0C_USBS0 \ Stop Bit Select - $06 constant UCSR0C_UCSZ0 \ Character Size - $01 constant UCSR0C_UCPOL0 \ Clock Polarity -&196 constant UBRR0 \ USART Baud Rate Register Bytes -\ CPU -&95 constant SREG \ Status Register - $80 constant SREG_I \ Global Interrupt Enable - $40 constant SREG_T \ Bit Copy Storage - $20 constant SREG_H \ Half Carry Flag - $10 constant SREG_S \ Sign Bit - $08 constant SREG_V \ Two's Complement Overflow Flag - $04 constant SREG_N \ Negative Flag - $02 constant SREG_Z \ Zero Flag - $01 constant SREG_C \ Carry Flag -&93 constant SP \ Stack Pointer -&85 constant MCUCR \ MCU Control Register - $10 constant MCUCR_PUD \ Pull-up disable - $02 constant MCUCR_IVSEL \ Interrupt Vector Select - $01 constant MCUCR_IVCE \ Interrupt Vector Change Enable -&84 constant MCUSR \ MCU Status Register - $10 constant MCUSR_JTRF \ JTAG Reset Flag - $08 constant MCUSR_WDRF \ Watchdog Reset Flag - $04 constant MCUSR_BORF \ Brown-out Reset Flag - $02 constant MCUSR_EXTRF \ External Reset Flag - $01 constant MCUSR_PORF \ Power-on reset flag -&102 constant OSCCAL \ Oscillator Calibration Value -&97 constant CLKPR \ Clock Prescale Register - $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable - $0F constant CLKPR_CLKPS \ Clock Prescaler Select Bits -&100 constant PRR \ Power Reduction Register - $10 constant PRR_PRLCD \ Power Reduction LCD - $08 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1 - $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface - $02 constant PRR_PRUSART0 \ Power Reduction USART - $01 constant PRR_PRADC \ Power Reduction ADC -&83 constant SMCR \ Sleep Mode Control Register - $0E constant SMCR_SM \ Sleep Mode Select bits - $01 constant SMCR_SE \ Sleep Enable -&75 constant GPIOR2 \ General Purpose IO Register 2 -&74 constant GPIOR1 \ General Purpose IO Register 1 -&62 constant GPIOR0 \ General Purpose IO Register 0 -\ JTAG -&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory -\ EEPROM -&65 constant EEAR \ EEPROM Read/Write Access Bytes -&64 constant EEDR \ EEPROM Data Register -&63 constant EECR \ EEPROM Control Register - $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable - $04 constant EECR_EEMWE \ EEPROM Master Write Enable - $02 constant EECR_EEWE \ EEPROM Write Enable - $01 constant EECR_EERE \ EEPROM Read Enable -\ PORTA -&34 constant PORTA \ Port A Data Register -&33 constant DDRA \ Port A Data Direction Register -&32 constant PINA \ Port A Input Pins -\ PORTB -&37 constant PORTB \ Port B Data Register -&36 constant DDRB \ Port B Data Direction Register -&35 constant PINB \ Port B Input Pins -\ PORTC -&40 constant PORTC \ Port C Data Register -&39 constant DDRC \ Port C Data Direction Register -&38 constant PINC \ Port C Input Pins -\ PORTD -&43 constant PORTD \ Port D Data Register -&42 constant DDRD \ Port D Data Direction Register -&41 constant PIND \ Port D Input Pins -\ PORTE -&46 constant PORTE \ Data Register, Port E -&45 constant DDRE \ Data Direction Register, Port E -&44 constant PINE \ Input Pins, Port E -\ PORTF -&49 constant PORTF \ Data Register, Port F -&48 constant DDRF \ Data Direction Register, Port F -&47 constant PINF \ Input Pins, Port F -\ PORTG -&52 constant PORTG \ Port G Data Register -&51 constant DDRG \ Port G Data Direction Register -&50 constant PING \ Port G Input Pins -\ TIMER_COUNTER_0 -&68 constant TCCR0A \ Timer/Counter0 Control Register - $80 constant TCCR0A_FOC0A \ Force Output Compare - $40 constant TCCR0A_WGM00 \ Waveform Generation Mode 0 - $30 constant TCCR0A_COM0A \ Compare Match Output Modes - $08 constant TCCR0A_WGM01 \ Waveform Generation Mode 1 - $07 constant TCCR0A_CS0 \ Clock Selects -&70 constant TCNT0 \ Timer/Counter0 -&71 constant OCR0A \ Timer/Counter0 Output Compare Register -&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register - $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match Interrupt Enable - $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable -&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register - $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0 - $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag -&67 constant GTCCR \ General Timer/Control Register - $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode - $01 constant GTCCR_PSR310 \ Prescaler Reset Timer/Counter1 and Timer/Counter0 -\ TIMER_COUNTER_2 -&176 constant TCCR2A \ Timer/Counter2 Control Register - $80 constant TCCR2A_FOC2A \ Force Output Compare A - $40 constant TCCR2A_WGM20 \ Waveform Generation Mode - $30 constant TCCR2A_COM2A \ Compare Output Mode bits - $08 constant TCCR2A_WGM21 \ Waveform Generation Mode - $07 constant TCCR2A_CS2 \ Clock Select bits -&178 constant TCNT2 \ Timer/Counter2 -&179 constant OCR2A \ Timer/Counter2 Output Compare Register -&112 constant TIMSK2 \ Timer/Counter2 Interrupt Mask register - $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match Interrupt Enable - $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable -&55 constant TIFR2 \ Timer/Counter2 Interrupt Flag Register - $02 constant TIFR2_OCF2A \ Timer/Counter2 Output Compare Flag 2 - $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag -&182 constant ASSR \ Asynchronous Status Register - $10 constant ASSR_EXCLK \ Enable External Clock Interrupt - $08 constant ASSR_AS2 \ AS2: Asynchronous Timer/Counter2 - $04 constant ASSR_TCN2UB \ TCN2UB: Timer/Counter2 Update Busy - $02 constant ASSR_OCR2UB \ Output Compare Register2 Update Busy - $01 constant ASSR_TCR2UB \ TCR2UB: Timer/Counter Control Register2 Update Busy -\ TIMER_COUNTER_1 -&128 constant TCCR1A \ Timer/Counter1 Control Register A - $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits - $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits - $03 constant TCCR1A_WGM1 \ Waveform Generation Mode -&129 constant TCCR1B \ Timer/Counter1 Control Register B - $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler - $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select - $18 constant TCCR1B_WGM1 \ Waveform Generation Mode - $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1 -&130 constant TCCR1C \ Timer/Counter 1 Control Register C - $80 constant TCCR1C_FOC1A \ Force Output Compare 1A - $40 constant TCCR1C_FOC1B \ Force Output Compare 1B -&132 constant TCNT1 \ Timer/Counter1 Bytes -&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes -&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes -&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes -&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register - $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable - $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable - $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable - $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable -&54 constant TIFR1 \ Timer/Counter1 Interrupt Flag register - $20 constant TIFR1_ICF1 \ Input Capture Flag 1 - $04 constant TIFR1_OCF1B \ Output Compare Flag 1B - $02 constant TIFR1_OCF1A \ Output Compare Flag 1A - $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag -\ WATCHDOG -&96 constant WDTCR \ Watchdog Timer Control Register - $10 constant WDTCR_WDCE \ Watchdog Change Enable - $08 constant WDTCR_WDE \ Watch Dog Enable - $07 constant WDTCR_WDP \ Watch Dog Timer Prescaler bits -\ BOOT_LOAD -&87 constant SPMCSR \ Store Program Memory Control Register - $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable - $40 constant SPMCSR_RWWSB \ Read While Write Section Busy - $10 constant SPMCSR_RWWSRE \ Read While Write section read enable - $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set - $04 constant SPMCSR_PGWRT \ Page Write - $02 constant SPMCSR_PGERS \ Page Erase - $01 constant SPMCSR_SPMEN \ Store Program Memory Enable -\ PORTH -&218 constant PORTH \ PORT H Data Register -&217 constant DDRH \ PORT H Data Direction Register -&216 constant PINH \ PORT H Input Pins -\ PORTJ -&221 constant PORTJ \ PORT J Data Register -&220 constant DDRJ \ PORT J Data Direction Register -&219 constant PINJ \ PORT J Input Pins -\ EXTERNAL_INTERRUPT -&105 constant EICRA \ External Interrupt Control Register A - $02 constant EICRA_ISC01 \ External Interrupt Sense Control 0 Bit 1 - $01 constant EICRA_ISC00 \ External Interrupt Sense Control 0 Bit 0 -&61 constant EIMSK \ External Interrupt Mask Register - $F0 constant EIMSK_PCIE \ Pin Change Interrupt Enables - $01 constant EIMSK_INT0 \ External Interrupt Request 0 Enable -&60 constant EIFR \ External Interrupt Flag Register - $F0 constant EIFR_PCIF \ Pin Change Interrupt Flags - $01 constant EIFR_INTF0 \ External Interrupt Flag 0 -&115 constant PCMSK3 \ Pin Change Mask Register 3 -&109 constant PCMSK2 \ Pin Change Mask Register 2 -&108 constant PCMSK1 \ Pin Change Mask Register 1 -&107 constant PCMSK0 \ Pin Change Mask Register 0 - -\ Interrupts -&2 constant INT0Addr \ External Interrupt Request 0 -&4 constant PCINT0Addr \ Pin Change Interrupt Request 0 -&6 constant PCINT1Addr \ Pin Change Interrupt Request 1 -&8 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match -&10 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow -&12 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event -&14 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A -&16 constant TIMER1_COMPBAddr \ Timer/Counter Compare Match B -&18 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow -&20 constant TIMER0_COMPAddr \ Timer/Counter0 Compare Match -&22 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow -&24 constant SPI__STCAddr \ SPI Serial Transfer Complete -&26 constant USART__RXAddr \ USART, Rx Complete -&28 constant USART__UDREAddr \ USART Data register Empty -&30 constant USART0__TXAddr \ USART0, Tx Complete -&32 constant USI_STARTAddr \ USI Start Condition -&34 constant USI_OVERFLOWAddr \ USI Overflow -&36 constant ANALOG_COMPAddr \ Analog Comparator -&38 constant ADCAddr \ ADC Conversion Complete -&40 constant EE_READYAddr \ EEPROM Ready -&42 constant SPM_READYAddr \ Store Program Memory Read -&44 constant NOT_USEDAddr \ RESERVED -&46 constant PCINT2Addr \ Pin Change Interrupt Request 2 -&48 constant PCINT3Addr \ Pin Change Interrupt Request 3 diff --git a/amforth-6.5/avr8/devices/atmega6450p/device.asm b/amforth-6.5/avr8/devices/atmega6450p/device.asm deleted file mode 100644 index 235783e..0000000 --- a/amforth-6.5/avr8/devices/atmega6450p/device.asm +++ /dev/null @@ -1,114 +0,0 @@ -; Partname: ATmega6450P -; generated automatically, do not edit - -.nolist - .include "m6450Pdef.inc" -.list - -.equ ramstart = 256 -.equ CELLSIZE = 2 -.macro readflashcell - lsl zl - rol zh - lpm @0, Z+ - lpm @1, Z+ -.endmacro -.macro writeflashcell - lsl zl - rol zh -.endmacro -.set WANT_AD_CONVERTER = 0 -.set WANT_ANALOG_COMPARATOR = 0 -.set WANT_SPI = 0 -.set WANT_USI = 0 -.set WANT_USART0 = 0 -.set WANT_CPU = 0 -.set WANT_JTAG = 0 -.set WANT_EEPROM = 0 -.set WANT_PORTA = 0 -.set WANT_PORTB = 0 -.set WANT_PORTC = 0 -.set WANT_PORTD = 0 -.set WANT_PORTE = 0 -.set WANT_PORTF = 0 -.set WANT_PORTG = 0 -.set WANT_TIMER_COUNTER_0 = 0 -.set WANT_TIMER_COUNTER_2 = 0 -.set WANT_TIMER_COUNTER_1 = 0 -.set WANT_WATCHDOG = 0 -.set WANT_BOOT_LOAD = 0 -.set WANT_PORTH = 0 -.set WANT_PORTJ = 0 -.set WANT_EXTERNAL_INTERRUPT = 0 -.equ intvecsize = 2 ; please verify; flash size: 65536 bytes -.equ pclen = 2 ; please verify -.overlap -.org 2 - rcall isr ; External Interrupt Request 0 -.org 4 - rcall isr ; Pin Change Interrupt Request 0 -.org 6 - rcall isr ; Pin Change Interrupt Request 1 -.org 8 - rcall isr ; Timer/Counter2 Compare Match -.org 10 - rcall isr ; Timer/Counter2 Overflow -.org 12 - rcall isr ; Timer/Counter1 Capture Event -.org 14 - rcall isr ; Timer/Counter1 Compare Match A -.org 16 - rcall isr ; Timer/Counter Compare Match B -.org 18 - rcall isr ; Timer/Counter1 Overflow -.org 20 - rcall isr ; Timer/Counter0 Compare Match -.org 22 - rcall isr ; Timer/Counter0 Overflow -.org 24 - rcall isr ; SPI Serial Transfer Complete -.org 26 - rcall isr ; USART, Rx Complete -.org 28 - rcall isr ; USART Data register Empty -.org 30 - rcall isr ; USART0, Tx Complete -.org 32 - rcall isr ; USI Start Condition -.org 34 - rcall isr ; USI Overflow -.org 36 - rcall isr ; Analog Comparator -.org 38 - rcall isr ; ADC Conversion Complete -.org 40 - rcall isr ; EEPROM Ready -.org 42 - rcall isr ; Store Program Memory Read -.org 44 - rcall isr ; RESERVED -.org 46 - rcall isr ; Pin Change Interrupt Request 2 -.org 48 - rcall isr ; Pin Change Interrupt Request 3 -.equ INTVECTORS = 25 -.nooverlap - -; compatability layer (maybe empty) -.equ EEPE = EEWE -.equ EEMPE = EEMWE - -; controller data area, environment query mcu-info -mcu_info: -mcu_ramsize: - .dw 4096 -mcu_eepromsize: - .dw 2048 -mcu_maxdp: - .dw 57344 -mcu_numints: - .dw 25 -mcu_name: - .dw 11 - .db "ATmega6450P",0 -.set codestart=pc diff --git a/amforth-6.5/avr8/devices/atmega6450p/device.inc b/amforth-6.5/avr8/devices/atmega6450p/device.inc deleted file mode 100644 index 1d056aa..0000000 --- a/amforth-6.5/avr8/devices/atmega6450p/device.inc +++ /dev/null @@ -1,1152 +0,0 @@ -; Partname: ATmega6450P -; generated automatically, no not edit - -.if WANT_AD_CONVERTER == 1 -; ( -- addr ) System Constant -; R( -- ) -; The ADC multiplexer Selection Register -VE_ADMUX: - .dw $ff05 - .db "ADMUX",0 - .dw VE_HEAD - .set VE_HEAD=VE_ADMUX -XT_ADMUX: - .dw PFA_DOVARIABLE -PFA_ADMUX: - .dw 124 -; ( -- addr ) System Constant -; R( -- ) -; The ADC Control and Status register -VE_ADCSRA: - .dw $ff06 - .db "ADCSRA" - .dw VE_HEAD - .set VE_HEAD=VE_ADCSRA -XT_ADCSRA: - .dw PFA_DOVARIABLE -PFA_ADCSRA: - .dw 122 -; ( -- addr ) System Constant -; R( -- ) -; ADC Data Register Bytes -VE_ADC: - .dw $ff03 - .db "ADC",0 - .dw VE_HEAD - .set VE_HEAD=VE_ADC -XT_ADC: - .dw PFA_DOVARIABLE -PFA_ADC: - .dw 120 -; ( -- addr ) System Constant -; R( -- ) -; ADC Control and Status Register B -VE_ADCSRB: - .dw $ff06 - .db "ADCSRB" - .dw VE_HEAD - .set VE_HEAD=VE_ADCSRB -XT_ADCSRB: - .dw PFA_DOVARIABLE -PFA_ADCSRB: - .dw 123 -; ( -- addr ) System Constant -; R( -- ) -; Digital Input Disable Register 0 -VE_DIDR0: - .dw $ff05 - .db "DIDR0",0 - .dw VE_HEAD - .set VE_HEAD=VE_DIDR0 -XT_DIDR0: - .dw PFA_DOVARIABLE -PFA_DIDR0: - .dw 126 - -.endif -.if WANT_ANALOG_COMPARATOR == 1 -; ( -- addr ) System Constant -; R( -- ) -; Analog Comparator Control And Status Register -VE_ACSR: - .dw $ff04 - .db "ACSR" - .dw VE_HEAD - .set VE_HEAD=VE_ACSR -XT_ACSR: - .dw PFA_DOVARIABLE -PFA_ACSR: - .dw 80 -; ( -- addr ) System Constant -; R( -- ) -; Digital Input Disable Register 1 -VE_DIDR1: - .dw $ff05 - .db "DIDR1",0 - .dw VE_HEAD - .set VE_HEAD=VE_DIDR1 -XT_DIDR1: - .dw PFA_DOVARIABLE -PFA_DIDR1: - .dw 127 - -.endif -.if WANT_SPI == 1 -; ( -- addr ) System Constant -; R( -- ) -; SPI Control Register -VE_SPCR: - .dw $ff04 - .db "SPCR" - .dw VE_HEAD - .set VE_HEAD=VE_SPCR -XT_SPCR: - .dw PFA_DOVARIABLE -PFA_SPCR: - .dw 76 -; ( -- addr ) System Constant -; R( -- ) -; SPI Status Register -VE_SPSR: - .dw $ff04 - .db "SPSR" - .dw VE_HEAD - .set VE_HEAD=VE_SPSR -XT_SPSR: - .dw PFA_DOVARIABLE -PFA_SPSR: - .dw 77 -; ( -- addr ) System Constant -; R( -- ) -; SPI Data Register -VE_SPDR: - .dw $ff04 - .db "SPDR" - .dw VE_HEAD - .set VE_HEAD=VE_SPDR -XT_SPDR: - .dw PFA_DOVARIABLE -PFA_SPDR: - .dw 78 - -.endif -.if WANT_USI == 1 -; ( -- addr ) System Constant -; R( -- ) -; USI Data Register -VE_USIDR: - .dw $ff05 - .db "USIDR",0 - .dw VE_HEAD - .set VE_HEAD=VE_USIDR -XT_USIDR: - .dw PFA_DOVARIABLE -PFA_USIDR: - .dw 186 -; ( -- addr ) System Constant -; R( -- ) -; USI Status Register -VE_USISR: - .dw $ff05 - .db "USISR",0 - .dw VE_HEAD - .set VE_HEAD=VE_USISR -XT_USISR: - .dw PFA_DOVARIABLE -PFA_USISR: - .dw 185 -; ( -- addr ) System Constant -; R( -- ) -; USI Control Register -VE_USICR: - .dw $ff05 - .db "USICR",0 - .dw VE_HEAD - .set VE_HEAD=VE_USICR -XT_USICR: - .dw PFA_DOVARIABLE -PFA_USICR: - .dw 184 - -.endif -.if WANT_USART0 == 1 -; ( -- addr ) System Constant -; R( -- ) -; USART I/O Data Register -VE_UDR0: - .dw $ff04 - .db "UDR0" - .dw VE_HEAD - .set VE_HEAD=VE_UDR0 -XT_UDR0: - .dw PFA_DOVARIABLE -PFA_UDR0: - .dw 198 -; ( -- addr ) System Constant -; R( -- ) -; USART Control and Status Register A -VE_UCSR0A: - .dw $ff06 - .db "UCSR0A" - .dw VE_HEAD - .set VE_HEAD=VE_UCSR0A -XT_UCSR0A: - .dw PFA_DOVARIABLE -PFA_UCSR0A: - .dw 192 -; ( -- addr ) System Constant -; R( -- ) -; USART Control and Status Register B -VE_UCSR0B: - .dw $ff06 - .db "UCSR0B" - .dw VE_HEAD - .set VE_HEAD=VE_UCSR0B -XT_UCSR0B: - .dw PFA_DOVARIABLE -PFA_UCSR0B: - .dw 193 -; ( -- addr ) System Constant -; R( -- ) -; USART Control and Status Register C -VE_UCSR0C: - .dw $ff06 - .db "UCSR0C" - .dw VE_HEAD - .set VE_HEAD=VE_UCSR0C -XT_UCSR0C: - .dw PFA_DOVARIABLE -PFA_UCSR0C: - .dw 194 -; ( -- addr ) System Constant -; R( -- ) -; USART Baud Rate Register Bytes -VE_UBRR0: - .dw $ff05 - .db "UBRR0",0 - .dw VE_HEAD - .set VE_HEAD=VE_UBRR0 -XT_UBRR0: - .dw PFA_DOVARIABLE -PFA_UBRR0: - .dw 196 - -.endif -.if WANT_CPU == 1 -; ( -- addr ) System Constant -; R( -- ) -; Status Register -VE_SREG: - .dw $ff04 - .db "SREG" - .dw VE_HEAD - .set VE_HEAD=VE_SREG -XT_SREG: - .dw PFA_DOVARIABLE -PFA_SREG: - .dw 95 -; ( -- addr ) System Constant -; R( -- ) -; Stack Pointer -VE_SP: - .dw $ff02 - .db "SP" - .dw VE_HEAD - .set VE_HEAD=VE_SP -XT_SP: - .dw PFA_DOVARIABLE -PFA_SP: - .dw 93 -; ( -- addr ) System Constant -; R( -- ) -; MCU Control Register -VE_MCUCR: - .dw $ff05 - .db "MCUCR",0 - .dw VE_HEAD - .set VE_HEAD=VE_MCUCR -XT_MCUCR: - .dw PFA_DOVARIABLE -PFA_MCUCR: - .dw 85 -; ( -- addr ) System Constant -; R( -- ) -; MCU Status Register -VE_MCUSR: - .dw $ff05 - .db "MCUSR",0 - .dw VE_HEAD - .set VE_HEAD=VE_MCUSR -XT_MCUSR: - .dw PFA_DOVARIABLE -PFA_MCUSR: - .dw 84 -; ( -- addr ) System Constant -; R( -- ) -; Oscillator Calibration Value -VE_OSCCAL: - .dw $ff06 - .db "OSCCAL" - .dw VE_HEAD - .set VE_HEAD=VE_OSCCAL -XT_OSCCAL: - .dw PFA_DOVARIABLE -PFA_OSCCAL: - .dw 102 -; ( -- addr ) System Constant -; R( -- ) -; Clock Prescale Register -VE_CLKPR: - .dw $ff05 - .db "CLKPR",0 - .dw VE_HEAD - .set VE_HEAD=VE_CLKPR -XT_CLKPR: - .dw PFA_DOVARIABLE -PFA_CLKPR: - .dw 97 -; ( -- addr ) System Constant -; R( -- ) -; Power Reduction Register -VE_PRR: - .dw $ff03 - .db "PRR",0 - .dw VE_HEAD - .set VE_HEAD=VE_PRR -XT_PRR: - .dw PFA_DOVARIABLE -PFA_PRR: - .dw 100 -; ( -- addr ) System Constant -; R( -- ) -; Sleep Mode Control Register -VE_SMCR: - .dw $ff04 - .db "SMCR" - .dw VE_HEAD - .set VE_HEAD=VE_SMCR -XT_SMCR: - .dw PFA_DOVARIABLE -PFA_SMCR: - .dw 83 -; ( -- addr ) System Constant -; R( -- ) -; General Purpose IO Register 2 -VE_GPIOR2: - .dw $ff06 - .db "GPIOR2" - .dw VE_HEAD - .set VE_HEAD=VE_GPIOR2 -XT_GPIOR2: - .dw PFA_DOVARIABLE -PFA_GPIOR2: - .dw 75 -; ( -- addr ) System Constant -; R( -- ) -; General Purpose IO Register 1 -VE_GPIOR1: - .dw $ff06 - .db "GPIOR1" - .dw VE_HEAD - .set VE_HEAD=VE_GPIOR1 -XT_GPIOR1: - .dw PFA_DOVARIABLE -PFA_GPIOR1: - .dw 74 -; ( -- addr ) System Constant -; R( -- ) -; General Purpose IO Register 0 -VE_GPIOR0: - .dw $ff06 - .db "GPIOR0" - .dw VE_HEAD - .set VE_HEAD=VE_GPIOR0 -XT_GPIOR0: - .dw PFA_DOVARIABLE -PFA_GPIOR0: - .dw 62 - -.endif -.if WANT_JTAG == 1 -; ( -- addr ) System Constant -; R( -- ) -; On-Chip Debug Related Register in I/O Memory -VE_OCDR: - .dw $ff04 - .db "OCDR" - .dw VE_HEAD - .set VE_HEAD=VE_OCDR -XT_OCDR: - .dw PFA_DOVARIABLE -PFA_OCDR: - .dw 81 - -.endif -.if WANT_EEPROM == 1 -; ( -- addr ) System Constant -; R( -- ) -; EEPROM Read/Write Access Bytes -VE_EEAR: - .dw $ff04 - .db "EEAR" - .dw VE_HEAD - .set VE_HEAD=VE_EEAR -XT_EEAR: - .dw PFA_DOVARIABLE -PFA_EEAR: - .dw 65 -; ( -- addr ) System Constant -; R( -- ) -; EEPROM Data Register -VE_EEDR: - .dw $ff04 - .db "EEDR" - .dw VE_HEAD - .set VE_HEAD=VE_EEDR -XT_EEDR: - .dw PFA_DOVARIABLE -PFA_EEDR: - .dw 64 -; ( -- addr ) System Constant -; R( -- ) -; EEPROM Control Register -VE_EECR: - .dw $ff04 - .db "EECR" - .dw VE_HEAD - .set VE_HEAD=VE_EECR -XT_EECR: - .dw PFA_DOVARIABLE -PFA_EECR: - .dw 63 - -.endif -.if WANT_PORTA == 1 -; ( -- addr ) System Constant -; R( -- ) -; Port A Data Register -VE_PORTA: - .dw $ff05 - .db "PORTA",0 - .dw VE_HEAD - .set VE_HEAD=VE_PORTA -XT_PORTA: - .dw PFA_DOVARIABLE -PFA_PORTA: - .dw 34 -; ( -- addr ) System Constant -; R( -- ) -; Port A Data Direction Register -VE_DDRA: - .dw $ff04 - .db "DDRA" - .dw VE_HEAD - .set VE_HEAD=VE_DDRA -XT_DDRA: - .dw PFA_DOVARIABLE -PFA_DDRA: - .dw 33 -; ( -- addr ) System Constant -; R( -- ) -; Port A Input Pins -VE_PINA: - .dw $ff04 - .db "PINA" - .dw VE_HEAD - .set VE_HEAD=VE_PINA -XT_PINA: - .dw PFA_DOVARIABLE -PFA_PINA: - .dw 32 - -.endif -.if WANT_PORTB == 1 -; ( -- addr ) System Constant -; R( -- ) -; Port B Data Register -VE_PORTB: - .dw $ff05 - .db "PORTB",0 - .dw VE_HEAD - .set VE_HEAD=VE_PORTB -XT_PORTB: - .dw PFA_DOVARIABLE -PFA_PORTB: - .dw 37 -; ( -- addr ) System Constant -; R( -- ) -; Port B Data Direction Register -VE_DDRB: - .dw $ff04 - .db "DDRB" - .dw VE_HEAD - .set VE_HEAD=VE_DDRB -XT_DDRB: - .dw PFA_DOVARIABLE -PFA_DDRB: - .dw 36 -; ( -- addr ) System Constant -; R( -- ) -; Port B Input Pins -VE_PINB: - .dw $ff04 - .db "PINB" - .dw VE_HEAD - .set VE_HEAD=VE_PINB -XT_PINB: - .dw PFA_DOVARIABLE -PFA_PINB: - .dw 35 - -.endif -.if WANT_PORTC == 1 -; ( -- addr ) System Constant -; R( -- ) -; Port C Data Register -VE_PORTC: - .dw $ff05 - .db "PORTC",0 - .dw VE_HEAD - .set VE_HEAD=VE_PORTC -XT_PORTC: - .dw PFA_DOVARIABLE -PFA_PORTC: - .dw 40 -; ( -- addr ) System Constant -; R( -- ) -; Port C Data Direction Register -VE_DDRC: - .dw $ff04 - .db "DDRC" - .dw VE_HEAD - .set VE_HEAD=VE_DDRC -XT_DDRC: - .dw PFA_DOVARIABLE -PFA_DDRC: - .dw 39 -; ( -- addr ) System Constant -; R( -- ) -; Port C Input Pins -VE_PINC: - .dw $ff04 - .db "PINC" - .dw VE_HEAD - .set VE_HEAD=VE_PINC -XT_PINC: - .dw PFA_DOVARIABLE -PFA_PINC: - .dw 38 - -.endif -.if WANT_PORTD == 1 -; ( -- addr ) System Constant -; R( -- ) -; Port D Data Register -VE_PORTD: - .dw $ff05 - .db "PORTD",0 - .dw VE_HEAD - .set VE_HEAD=VE_PORTD -XT_PORTD: - .dw PFA_DOVARIABLE -PFA_PORTD: - .dw 43 -; ( -- addr ) System Constant -; R( -- ) -; Port D Data Direction Register -VE_DDRD: - .dw $ff04 - .db "DDRD" - .dw VE_HEAD - .set VE_HEAD=VE_DDRD -XT_DDRD: - .dw PFA_DOVARIABLE -PFA_DDRD: - .dw 42 -; ( -- addr ) System Constant -; R( -- ) -; Port D Input Pins -VE_PIND: - .dw $ff04 - .db "PIND" - .dw VE_HEAD - .set VE_HEAD=VE_PIND -XT_PIND: - .dw PFA_DOVARIABLE -PFA_PIND: - .dw 41 - -.endif -.if WANT_PORTE == 1 -; ( -- addr ) System Constant -; R( -- ) -; Data Register, Port E -VE_PORTE: - .dw $ff05 - .db "PORTE",0 - .dw VE_HEAD - .set VE_HEAD=VE_PORTE -XT_PORTE: - .dw PFA_DOVARIABLE -PFA_PORTE: - .dw 46 -; ( -- addr ) System Constant -; R( -- ) -; Data Direction Register, Port E -VE_DDRE: - .dw $ff04 - .db "DDRE" - .dw VE_HEAD - .set VE_HEAD=VE_DDRE -XT_DDRE: - .dw PFA_DOVARIABLE -PFA_DDRE: - .dw 45 -; ( -- addr ) System Constant -; R( -- ) -; Input Pins, Port E -VE_PINE: - .dw $ff04 - .db "PINE" - .dw VE_HEAD - .set VE_HEAD=VE_PINE -XT_PINE: - .dw PFA_DOVARIABLE -PFA_PINE: - .dw 44 - -.endif -.if WANT_PORTF == 1 -; ( -- addr ) System Constant -; R( -- ) -; Data Register, Port F -VE_PORTF: - .dw $ff05 - .db "PORTF",0 - .dw VE_HEAD - .set VE_HEAD=VE_PORTF -XT_PORTF: - .dw PFA_DOVARIABLE -PFA_PORTF: - .dw 49 -; ( -- addr ) System Constant -; R( -- ) -; Data Direction Register, Port F -VE_DDRF: - .dw $ff04 - .db "DDRF" - .dw VE_HEAD - .set VE_HEAD=VE_DDRF -XT_DDRF: - .dw PFA_DOVARIABLE -PFA_DDRF: - .dw 48 -; ( -- addr ) System Constant -; R( -- ) -; Input Pins, Port F -VE_PINF: - .dw $ff04 - .db "PINF" - .dw VE_HEAD - .set VE_HEAD=VE_PINF -XT_PINF: - .dw PFA_DOVARIABLE -PFA_PINF: - .dw 47 - -.endif -.if WANT_PORTG == 1 -; ( -- addr ) System Constant -; R( -- ) -; Port G Data Register -VE_PORTG: - .dw $ff05 - .db "PORTG",0 - .dw VE_HEAD - .set VE_HEAD=VE_PORTG -XT_PORTG: - .dw PFA_DOVARIABLE -PFA_PORTG: - .dw 52 -; ( -- addr ) System Constant -; R( -- ) -; Port G Data Direction Register -VE_DDRG: - .dw $ff04 - .db "DDRG" - .dw VE_HEAD - .set VE_HEAD=VE_DDRG -XT_DDRG: - .dw PFA_DOVARIABLE -PFA_DDRG: - .dw 51 -; ( -- addr ) System Constant -; R( -- ) -; Port G Input Pins -VE_PING: - .dw $ff04 - .db "PING" - .dw VE_HEAD - .set VE_HEAD=VE_PING -XT_PING: - .dw PFA_DOVARIABLE -PFA_PING: - .dw 50 - -.endif -.if WANT_TIMER_COUNTER_0 == 1 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter0 Control Register -VE_TCCR0A: - .dw $ff06 - .db "TCCR0A" - .dw VE_HEAD - .set VE_HEAD=VE_TCCR0A -XT_TCCR0A: - .dw PFA_DOVARIABLE -PFA_TCCR0A: - .dw 68 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter0 -VE_TCNT0: - .dw $ff05 - .db "TCNT0",0 - .dw VE_HEAD - .set VE_HEAD=VE_TCNT0 -XT_TCNT0: - .dw PFA_DOVARIABLE -PFA_TCNT0: - .dw 70 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter0 Output Compare Register -VE_OCR0A: - .dw $ff05 - .db "OCR0A",0 - .dw VE_HEAD - .set VE_HEAD=VE_OCR0A -XT_OCR0A: - .dw PFA_DOVARIABLE -PFA_OCR0A: - .dw 71 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter0 Interrupt Mask Register -VE_TIMSK0: - .dw $ff06 - .db "TIMSK0" - .dw VE_HEAD - .set VE_HEAD=VE_TIMSK0 -XT_TIMSK0: - .dw PFA_DOVARIABLE -PFA_TIMSK0: - .dw 110 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter0 Interrupt Flag register -VE_TIFR0: - .dw $ff05 - .db "TIFR0",0 - .dw VE_HEAD - .set VE_HEAD=VE_TIFR0 -XT_TIFR0: - .dw PFA_DOVARIABLE -PFA_TIFR0: - .dw 53 -; ( -- addr ) System Constant -; R( -- ) -; General Timer/Control Register -VE_GTCCR: - .dw $ff05 - .db "GTCCR",0 - .dw VE_HEAD - .set VE_HEAD=VE_GTCCR -XT_GTCCR: - .dw PFA_DOVARIABLE -PFA_GTCCR: - .dw 67 - -.endif -.if WANT_TIMER_COUNTER_2 == 1 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter2 Control Register -VE_TCCR2A: - .dw $ff06 - .db "TCCR2A" - .dw VE_HEAD - .set VE_HEAD=VE_TCCR2A -XT_TCCR2A: - .dw PFA_DOVARIABLE -PFA_TCCR2A: - .dw 176 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter2 -VE_TCNT2: - .dw $ff05 - .db "TCNT2",0 - .dw VE_HEAD - .set VE_HEAD=VE_TCNT2 -XT_TCNT2: - .dw PFA_DOVARIABLE -PFA_TCNT2: - .dw 178 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter2 Output Compare Register -VE_OCR2A: - .dw $ff05 - .db "OCR2A",0 - .dw VE_HEAD - .set VE_HEAD=VE_OCR2A -XT_OCR2A: - .dw PFA_DOVARIABLE -PFA_OCR2A: - .dw 179 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter2 Interrupt Mask register -VE_TIMSK2: - .dw $ff06 - .db "TIMSK2" - .dw VE_HEAD - .set VE_HEAD=VE_TIMSK2 -XT_TIMSK2: - .dw PFA_DOVARIABLE -PFA_TIMSK2: - .dw 112 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter2 Interrupt Flag Register -VE_TIFR2: - .dw $ff05 - .db "TIFR2",0 - .dw VE_HEAD - .set VE_HEAD=VE_TIFR2 -XT_TIFR2: - .dw PFA_DOVARIABLE -PFA_TIFR2: - .dw 55 -; ( -- addr ) System Constant -; R( -- ) -; Asynchronous Status Register -VE_ASSR: - .dw $ff04 - .db "ASSR" - .dw VE_HEAD - .set VE_HEAD=VE_ASSR -XT_ASSR: - .dw PFA_DOVARIABLE -PFA_ASSR: - .dw 182 - -.endif -.if WANT_TIMER_COUNTER_1 == 1 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter1 Control Register A -VE_TCCR1A: - .dw $ff06 - .db "TCCR1A" - .dw VE_HEAD - .set VE_HEAD=VE_TCCR1A -XT_TCCR1A: - .dw PFA_DOVARIABLE -PFA_TCCR1A: - .dw 128 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter1 Control Register B -VE_TCCR1B: - .dw $ff06 - .db "TCCR1B" - .dw VE_HEAD - .set VE_HEAD=VE_TCCR1B -XT_TCCR1B: - .dw PFA_DOVARIABLE -PFA_TCCR1B: - .dw 129 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter 1 Control Register C -VE_TCCR1C: - .dw $ff06 - .db "TCCR1C" - .dw VE_HEAD - .set VE_HEAD=VE_TCCR1C -XT_TCCR1C: - .dw PFA_DOVARIABLE -PFA_TCCR1C: - .dw 130 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter1 Bytes -VE_TCNT1: - .dw $ff05 - .db "TCNT1",0 - .dw VE_HEAD - .set VE_HEAD=VE_TCNT1 -XT_TCNT1: - .dw PFA_DOVARIABLE -PFA_TCNT1: - .dw 132 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter1 Output Compare Register A Bytes -VE_OCR1A: - .dw $ff05 - .db "OCR1A",0 - .dw VE_HEAD - .set VE_HEAD=VE_OCR1A -XT_OCR1A: - .dw PFA_DOVARIABLE -PFA_OCR1A: - .dw 136 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter1 Output Compare Register B Bytes -VE_OCR1B: - .dw $ff05 - .db "OCR1B",0 - .dw VE_HEAD - .set VE_HEAD=VE_OCR1B -XT_OCR1B: - .dw PFA_DOVARIABLE -PFA_OCR1B: - .dw 138 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter1 Input Capture Register Bytes -VE_ICR1: - .dw $ff04 - .db "ICR1" - .dw VE_HEAD - .set VE_HEAD=VE_ICR1 -XT_ICR1: - .dw PFA_DOVARIABLE -PFA_ICR1: - .dw 134 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter1 Interrupt Mask Register -VE_TIMSK1: - .dw $ff06 - .db "TIMSK1" - .dw VE_HEAD - .set VE_HEAD=VE_TIMSK1 -XT_TIMSK1: - .dw PFA_DOVARIABLE -PFA_TIMSK1: - .dw 111 -; ( -- addr ) System Constant -; R( -- ) -; Timer/Counter1 Interrupt Flag register -VE_TIFR1: - .dw $ff05 - .db "TIFR1",0 - .dw VE_HEAD - .set VE_HEAD=VE_TIFR1 -XT_TIFR1: - .dw PFA_DOVARIABLE -PFA_TIFR1: - .dw 54 - -.endif -.if WANT_WATCHDOG == 1 -; ( -- addr ) System Constant -; R( -- ) -; Watchdog Timer Control Register -VE_WDTCR: - .dw $ff05 - .db "WDTCR",0 - .dw VE_HEAD - .set VE_HEAD=VE_WDTCR -XT_WDTCR: - .dw PFA_DOVARIABLE -PFA_WDTCR: - .dw 96 - -.endif -.if WANT_BOOT_LOAD == 1 -; ( -- addr ) System Constant -; R( -- ) -; Store Program Memory Control Register -VE_SPMCSR: - .dw $ff06 - .db "SPMCSR" - .dw VE_HEAD - .set VE_HEAD=VE_SPMCSR -XT_SPMCSR: - .dw PFA_DOVARIABLE -PFA_SPMCSR: - .dw 87 - -.endif -.if WANT_PORTH == 1 -; ( -- addr ) System Constant -; R( -- ) -; PORT H Data Register -VE_PORTH: - .dw $ff05 - .db "PORTH",0 - .dw VE_HEAD - .set VE_HEAD=VE_PORTH -XT_PORTH: - .dw PFA_DOVARIABLE -PFA_PORTH: - .dw 218 -; ( -- addr ) System Constant -; R( -- ) -; PORT H Data Direction Register -VE_DDRH: - .dw $ff04 - .db "DDRH" - .dw VE_HEAD - .set VE_HEAD=VE_DDRH -XT_DDRH: - .dw PFA_DOVARIABLE -PFA_DDRH: - .dw 217 -; ( -- addr ) System Constant -; R( -- ) -; PORT H Input Pins -VE_PINH: - .dw $ff04 - .db "PINH" - .dw VE_HEAD - .set VE_HEAD=VE_PINH -XT_PINH: - .dw PFA_DOVARIABLE -PFA_PINH: - .dw 216 - -.endif -.if WANT_PORTJ == 1 -; ( -- addr ) System Constant -; R( -- ) -; PORT J Data Register -VE_PORTJ: - .dw $ff05 - .db "PORTJ",0 - .dw VE_HEAD - .set VE_HEAD=VE_PORTJ -XT_PORTJ: - .dw PFA_DOVARIABLE -PFA_PORTJ: - .dw 221 -; ( -- addr ) System Constant -; R( -- ) -; PORT J Data Direction Register -VE_DDRJ: - .dw $ff04 - .db "DDRJ" - .dw VE_HEAD - .set VE_HEAD=VE_DDRJ -XT_DDRJ: - .dw PFA_DOVARIABLE -PFA_DDRJ: - .dw 220 -; ( -- addr ) System Constant -; R( -- ) -; PORT J Input Pins -VE_PINJ: - .dw $ff04 - .db "PINJ" - .dw VE_HEAD - .set VE_HEAD=VE_PINJ -XT_PINJ: - .dw PFA_DOVARIABLE -PFA_PINJ: - .dw 219 - -.endif -.if WANT_EXTERNAL_INTERRUPT == 1 -; ( -- addr ) System Constant -; R( -- ) -; External Interrupt Control Register A -VE_EICRA: - .dw $ff05 - .db "EICRA",0 - .dw VE_HEAD - .set VE_HEAD=VE_EICRA -XT_EICRA: - .dw PFA_DOVARIABLE -PFA_EICRA: - .dw 105 -; ( -- addr ) System Constant -; R( -- ) -; External Interrupt Mask Register -VE_EIMSK: - .dw $ff05 - .db "EIMSK",0 - .dw VE_HEAD - .set VE_HEAD=VE_EIMSK -XT_EIMSK: - .dw PFA_DOVARIABLE -PFA_EIMSK: - .dw 61 -; ( -- addr ) System Constant -; R( -- ) -; External Interrupt Flag Register -VE_EIFR: - .dw $ff04 - .db "EIFR" - .dw VE_HEAD - .set VE_HEAD=VE_EIFR -XT_EIFR: - .dw PFA_DOVARIABLE -PFA_EIFR: - .dw 60 -; ( -- addr ) System Constant -; R( -- ) -; Pin Change Mask Register 3 -VE_PCMSK3: - .dw $ff06 - .db "PCMSK3" - .dw VE_HEAD - .set VE_HEAD=VE_PCMSK3 -XT_PCMSK3: - .dw PFA_DOVARIABLE -PFA_PCMSK3: - .dw 115 -; ( -- addr ) System Constant -; R( -- ) -; Pin Change Mask Register 2 -VE_PCMSK2: - .dw $ff06 - .db "PCMSK2" - .dw VE_HEAD - .set VE_HEAD=VE_PCMSK2 -XT_PCMSK2: - .dw PFA_DOVARIABLE -PFA_PCMSK2: - .dw 109 -; ( -- addr ) System Constant -; R( -- ) -; Pin Change Mask Register 1 -VE_PCMSK1: - .dw $ff06 - .db "PCMSK1" - .dw VE_HEAD - .set VE_HEAD=VE_PCMSK1 -XT_PCMSK1: - .dw PFA_DOVARIABLE -PFA_PCMSK1: - .dw 108 -; ( -- addr ) System Constant -; R( -- ) -; Pin Change Mask Register 0 -VE_PCMSK0: - .dw $ff06 - .db "PCMSK0" - .dw VE_HEAD - .set VE_HEAD=VE_PCMSK0 -XT_PCMSK0: - .dw PFA_DOVARIABLE -PFA_PCMSK0: - .dw 107 - -.endif diff --git a/amforth-6.5/avr8/devices/atmega6450p/device.py b/amforth-6.5/avr8/devices/atmega6450p/device.py deleted file mode 100644 index d034f86..0000000 --- a/amforth-6.5/avr8/devices/atmega6450p/device.py +++ /dev/null @@ -1,333 +0,0 @@ -# Generated Automatically - -# Partname ATmega6450P - -MCUREGS = { -# Interrupt Vectors - 'INT0Addr' : '#2', # External Interrupt Request 0 - 'PCINT0Addr' : '#4', # Pin Change Interrupt Request 0 - 'PCINT1Addr' : '#6', # Pin Change Interrupt Request 1 - 'TIMER2_COMPAddr' : '#8', # Timer/Counter2 Compare Match - 'TIMER2_OVFAddr' : '#10', # Timer/Counter2 Overflow - 'TIMER1_CAPTAddr' : '#12', # Timer/Counter1 Capture Event - 'TIMER1_COMPAAddr' : '#14', # Timer/Counter1 Compare Match A - 'TIMER1_COMPBAddr' : '#16', # Timer/Counter Compare Match B - 'TIMER1_OVFAddr' : '#18', # Timer/Counter1 Overflow - 'TIMER0_COMPAddr' : '#20', # Timer/Counter0 Compare Match - 'TIMER0_OVFAddr' : '#22', # Timer/Counter0 Overflow - 'SPI_STCAddr' : '#24', # SPI Serial Transfer Complete - 'USART_RXAddr' : '#26', # USART, Rx Complete - 'USART_UDREAddr' : '#28', # USART Data register Empty - 'USART0_TXAddr' : '#30', # USART0, Tx Complete - 'USI_STARTAddr' : '#32', # USI Start Condition - 'USI_OVERFLOWAddr' : '#34', # USI Overflow - 'ANALOG_COMPAddr' : '#36', # Analog Comparator - 'ADCAddr' : '#38', # ADC Conversion Complete - 'EE_READYAddr' : '#40', # EEPROM Ready - 'SPM_READYAddr' : '#42', # Store Program Memory Read - 'NOT_USEDAddr' : '#44', # RESERVED - 'PCINT2Addr' : '#46', # Pin Change Interrupt Request 2 - 'PCINT3Addr' : '#48', # Pin Change Interrupt Request 3 - -# Module AD_CONVERTER - 'ADMUX' : '$7c', # The ADC multiplexer Selection - 'ADMUX_REFS': '$c0', # Reference Selection Bits - 'ADMUX_ADLAR': '$20', # Left Adjust Result - 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select - 'ADCSRA' : '$7a', # The ADC Control and Status reg - 'ADCSRA_ADEN': '$80', # ADC Enable - 'ADCSRA_ADSC': '$40', # ADC Start Conversion - 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable - 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag - 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable - 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits - 'ADC' : '$78', # ADC Data Register Bytes - 'ADCSRB' : '$7b', # ADC Control and Status Registe - 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Sources - 'DIDR0' : '$7e', # Digital Input Disable Register - 'DIDR0_ADC7D': '$80', # ADC7 Digital input Disable - 'DIDR0_ADC6D': '$40', # ADC6 Digital input Disable - 'DIDR0_ADC5D': '$20', # ADC5 Digital input Disable - 'DIDR0_ADC4D': '$10', # ADC4 Digital input Disable - 'DIDR0_ADC3D': '$8', # ADC3 Digital input Disable - 'DIDR0_ADC2D': '$4', # ADC2 Digital input Disable - 'DIDR0_ADC1D': '$2', # ADC1 Digital input Disable - 'DIDR0_ADC0D': '$1', # ADC0 Digital input Disable - -# Module ANALOG_COMPARATOR - 'ADCSRB' : '$7b', # ADC Control and Status Registe - 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer - 'ACSR' : '$50', # Analog Comparator Control And - 'ACSR_ACD': '$80', # Analog Comparator Disable - 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele - 'ACSR_ACO': '$20', # Analog Compare Output - 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl - 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En - 'ACSR_ACIC': '$4', # Analog Comparator Input Captur - 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo - 'DIDR1' : '$7f', # Digital Input Disable Register - 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable - 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable - -# Module SPI - 'SPCR' : '$4c', # SPI Control Register - 'SPCR_SPIE': '$80', # SPI Interrupt Enable - 'SPCR_SPE': '$40', # SPI Enable - 'SPCR_DORD': '$20', # Data Order - 'SPCR_MSTR': '$10', # Master/Slave Select - 'SPCR_CPOL': '$8', # Clock polarity - 'SPCR_CPHA': '$4', # Clock Phase - 'SPCR_SPR': '$3', # SPI Clock Rate Selects - 'SPSR' : '$4d', # SPI Status Register - 'SPSR_SPIF': '$80', # SPI Interrupt Flag - 'SPSR_WCOL': '$40', # Write Collision Flag - 'SPSR_SPI2X': '$1', # Double SPI Speed Bit - 'SPDR' : '$4e', # SPI Data Register - -# Module USI - 'USIDR' : '$ba', # USI Data Register - 'USISR' : '$b9', # USI Status Register - 'USISR_USISIF': '$80', # Start Condition Interrupt Flag - 'USISR_USIOIF': '$40', # Counter Overflow Interrupt Fla - 'USISR_USIPF': '$20', # Stop Condition Flag - 'USISR_USIDC': '$10', # Data Output Collision - 'USISR_USICNT': '$f', # USI Counter Value Bits - 'USICR' : '$b8', # USI Control Register - 'USICR_USISIE': '$80', # Start Condition Interrupt Enab - 'USICR_USIOIE': '$40', # Counter Overflow Interrupt Ena - 'USICR_USIWM': '$30', # USI Wire Mode Bits - 'USICR_USICS': '$c', # USI Clock Source Select Bits - 'USICR_USICLK': '$2', # Clock Strobe - 'USICR_USITC': '$1', # Toggle Clock Port Pin - -# Module USART0 - 'UDR0' : '$c6', # USART I/O Data Register - 'UCSR0A' : '$c0', # USART Control and Status Regis - 'UCSR0A_RXC0': '$80', # USART Receive Complete - 'UCSR0A_TXC0': '$40', # USART Transmit Complete - 'UCSR0A_UDRE0': '$20', # USART Data Register Empty - 'UCSR0A_FE0': '$10', # Framing Error - 'UCSR0A_DOR0': '$8', # Data OverRun - 'UCSR0A_UPE0': '$4', # USART Parity Error - 'UCSR0A_U2X0': '$2', # Double the USART Transmission - 'UCSR0A_MPCM0': '$1', # Multi-processor Communication - 'UCSR0B' : '$c1', # USART Control and Status Regis - 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable - 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable - 'UCSR0B_UDRIE0': '$20', # USART Data Register Empty Inte - 'UCSR0B_RXEN0': '$10', # Receiver Enable - 'UCSR0B_TXEN0': '$8', # Transmitter Enable - 'UCSR0B_UCSZ02': '$4', # Character Size - 'UCSR0B_RXB80': '$2', # Receive Data Bit 8 - 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8 - 'UCSR0C' : '$c2', # USART Control and Status Regis - 'UCSR0C_UMSEL0': '$40', # USART Mode Select - 'UCSR0C_UPM0': '$30', # Parity Mode Bits - 'UCSR0C_USBS0': '$8', # Stop Bit Select - 'UCSR0C_UCSZ0': '$6', # Character Size - 'UCSR0C_UCPOL0': '$1', # Clock Polarity - 'UBRR0' : '$c4', # USART Baud Rate Register Byte - -# Module CPU - 'SREG' : '$5f', # Status Register - 'SREG_I': '$80', # Global Interrupt Enable - 'SREG_T': '$40', # Bit Copy Storage - 'SREG_H': '$20', # Half Carry Flag - 'SREG_S': '$10', # Sign Bit - 'SREG_V': '$8', # Two's Complement Overflow Flag - 'SREG_N': '$4', # Negative Flag - 'SREG_Z': '$2', # Zero Flag - 'SREG_C': '$1', # Carry Flag - 'SP' : '$5d', # Stack Pointer - 'MCUCR' : '$55', # MCU Control Register - 'MCUCR_PUD': '$10', # Pull-up disable - 'MCUCR_IVSEL': '$2', # Interrupt Vector Select - 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable - 'MCUSR' : '$54', # MCU Status Register - 'MCUSR_JTRF': '$10', # JTAG Reset Flag - 'MCUSR_WDRF': '$8', # Watchdog Reset Flag - 'MCUSR_BORF': '$4', # Brown-out Reset Flag - 'MCUSR_EXTRF': '$2', # External Reset Flag - 'MCUSR_PORF': '$1', # Power-on reset flag - 'OSCCAL' : '$66', # Oscillator Calibration Value - 'CLKPR' : '$61', # Clock Prescale Register - 'CLKPR_CLKPCE': '$80', # Clock Prescaler Change Enable - 'CLKPR_CLKPS': '$f', # Clock Prescaler Select Bits - 'PRR' : '$64', # Power Reduction Register - 'PRR_PRLCD': '$10', # Power Reduction LCD - 'PRR_PRTIM1': '$8', # Power Reduction Timer/Counter1 - 'PRR_PRSPI': '$4', # Power Reduction Serial Periphe - 'PRR_PRUSART0': '$2', # Power Reduction USART - 'PRR_PRADC': '$1', # Power Reduction ADC - 'SMCR' : '$53', # Sleep Mode Control Register - 'SMCR_SM': '$e', # Sleep Mode Select bits - 'SMCR_SE': '$1', # Sleep Enable - 'GPIOR2' : '$4b', # General Purpose IO Register 2 - 'GPIOR1' : '$4a', # General Purpose IO Register 1 - 'GPIOR0' : '$3e', # General Purpose IO Register 0 - -# Module JTAG - 'OCDR' : '$51', # On-Chip Debug Related Register - 'MCUCR' : '$55', # MCU Control Register - 'MCUCR_JTD': '$80', # JTAG Interface Disable - 'MCUSR' : '$54', # MCU Status Register - 'MCUSR_JTRF': '$10', # JTAG Reset Flag - -# Module EEPROM - 'EEAR' : '$41', # EEPROM Read/Write Access Byte - 'EEDR' : '$40', # EEPROM Data Register - 'EECR' : '$3f', # EEPROM Control Register - 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable - 'EECR_EEMWE': '$4', # EEPROM Master Write Enable - 'EECR_EEWE': '$2', # EEPROM Write Enable - 'EECR_EERE': '$1', # EEPROM Read Enable - -# Module PORTA - 'PORTA' : '$22', # Port A Data Register - 'DDRA' : '$21', # Port A Data Direction Register - 'PINA' : '$20', # Port A Input Pins - -# Module PORTB - 'PORTB' : '$25', # Port B Data Register - 'DDRB' : '$24', # Port B Data Direction Register - 'PINB' : '$23', # Port B Input Pins - -# Module PORTC - 'PORTC' : '$28', # Port C Data Register - 'DDRC' : '$27', # Port C Data Direction Register - 'PINC' : '$26', # Port C Input Pins - -# Module PORTD - 'PORTD' : '$2b', # Port D Data Register - 'DDRD' : '$2a', # Port D Data Direction Register - 'PIND' : '$29', # Port D Input Pins - -# Module PORTE - 'PORTE' : '$2e', # Data Register, Port E - 'DDRE' : '$2d', # Data Direction Register, Port - 'PINE' : '$2c', # Input Pins, Port E - -# Module PORTF - 'PORTF' : '$31', # Data Register, Port F - 'DDRF' : '$30', # Data Direction Register, Port - 'PINF' : '$2f', # Input Pins, Port F - -# Module PORTG - 'PORTG' : '$34', # Port G Data Register - 'DDRG' : '$33', # Port G Data Direction Register - 'PING' : '$32', # Port G Input Pins - -# Module TIMER_COUNTER_0 - 'TCCR0A' : '$44', # Timer/Counter0 Control Registe - 'TCCR0A_FOC0A': '$80', # Force Output Compare - 'TCCR0A_WGM00': '$40', # Waveform Generation Mode 0 - 'TCCR0A_COM0A': '$30', # Compare Match Output Modes - 'TCCR0A_WGM01': '$8', # Waveform Generation Mode 1 - 'TCCR0A_CS0': '$7', # Clock Selects - 'TCNT0' : '$46', # Timer/Counter0 - 'OCR0A' : '$47', # Timer/Counter0 Output Compare - 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask - 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare - 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr - 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag - 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare - 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag - 'GTCCR' : '$43', # General Timer/Control Register - 'GTCCR_TSM': '$80', # Timer/Counter Synchronization - 'GTCCR_PSR310': '$1', # Prescaler Reset Timer/Counter1 - -# Module TIMER_COUNTER_2 - 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe - 'TCCR2A_FOC2A': '$80', # Force Output Compare A - 'TCCR2A_WGM20': '$40', # Waveform Generation Mode - 'TCCR2A_COM2A': '$30', # Compare Output Mode bits - 'TCCR2A_WGM21': '$8', # Waveform Generation Mode - 'TCCR2A_CS2': '$7', # Clock Select bits - 'TCNT2' : '$b2', # Timer/Counter2 - 'OCR2A' : '$b3', # Timer/Counter2 Output Compare - 'TIMSK2' : '$70', # Timer/Counter2 Interrupt Mask - 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare - 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr - 'TIFR2' : '$37', # Timer/Counter2 Interrupt Flag - 'TIFR2_OCF2A': '$2', # Timer/Counter2 Output Compare - 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag - 'GTCCR' : '$43', # General Timer/Counter Control - 'GTCCR_PSR2': '$2', # Prescaler Reset Timer/Counter2 - 'ASSR' : '$b6', # Asynchronous Status Register - 'ASSR_EXCLK': '$10', # Enable External Clock Interrup - 'ASSR_AS2': '$8', # AS2: Asynchronous Timer/Counte - 'ASSR_TCN2UB': '$4', # TCN2UB: Timer/Counter2 Update - 'ASSR_OCR2UB': '$2', # Output Compare Register2 Updat - 'ASSR_TCR2UB': '$1', # TCR2UB: Timer/Counter Control - -# Module TIMER_COUNTER_1 - 'TCCR1A' : '$80', # Timer/Counter1 Control Registe - 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits - 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits - 'TCCR1A_WGM1': '$3', # Waveform Generation Mode - 'TCCR1B' : '$81', # Timer/Counter1 Control Registe - 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler - 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select - 'TCCR1B_WGM1': '$18', # Waveform Generation Mode - 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun - 'TCCR1C' : '$82', # Timer/Counter 1 Control Regist - 'TCCR1C_FOC1A': '$80', # Force Output Compare 1A - 'TCCR1C_FOC1B': '$40', # Force Output Compare 1B - 'TCNT1' : '$84', # Timer/Counter1 Bytes - 'OCR1A' : '$88', # Timer/Counter1 Output Compare - 'OCR1B' : '$8a', # Timer/Counter1 Output Compare - 'ICR1' : '$86', # Timer/Counter1 Input Capture R - 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask - 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I - 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare - 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare - 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr - 'TIFR1' : '$36', # Timer/Counter1 Interrupt Flag - 'TIFR1_ICF1': '$20', # Input Capture Flag 1 - 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B - 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A - 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag - -# Module WATCHDOG - 'WDTCR' : '$60', # Watchdog Timer Control Registe - 'WDTCR_WDCE': '$10', # Watchdog Change Enable - 'WDTCR_WDE': '$8', # Watch Dog Enable - 'WDTCR_WDP': '$7', # Watch Dog Timer Prescaler bits - -# Module BOOT_LOAD - 'SPMCSR' : '$57', # Store Program Memory Control R - 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable - 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy - 'SPMCSR_RWWSRE': '$10', # Read While Write section read - 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set - 'SPMCSR_PGWRT': '$4', # Page Write - 'SPMCSR_PGERS': '$2', # Page Erase - 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable - -# Module PORTH - 'PORTH' : '$da', # PORT H Data Register - 'DDRH' : '$d9', # PORT H Data Direction Register - 'PINH' : '$d8', # PORT H Input Pins - -# Module PORTJ - 'PORTJ' : '$dd', # PORT J Data Register - 'DDRJ' : '$dc', # PORT J Data Direction Register - 'PINJ' : '$db', # PORT J Input Pins - -# Module EXTERNAL_INTERRUPT - 'EICRA' : '$69', # External Interrupt Control Reg - 'EICRA_ISC01': '$2', # External Interrupt Sense Contr - 'EICRA_ISC00': '$1', # External Interrupt Sense Contr - 'EIMSK' : '$3d', # External Interrupt Mask Regist - 'EIMSK_PCIE': '$f0', # Pin Change Interrupt Enables - 'EIMSK_INT0': '$1', # External Interrupt Request 0 E - 'EIFR' : '$3c', # External Interrupt Flag Regist - 'EIFR_PCIF': '$f0', # Pin Change Interrupt Flags - 'EIFR_INTF0': '$1', # External Interrupt Flag 0 - 'PCMSK3' : '$73', # Pin Change Mask Register 3 - 'PCMSK2' : '$6d', # Pin Change Mask Register 2 - 'PCMSK1' : '$6c', # Pin Change Mask Register 1 - 'PCMSK0' : '$6b', # Pin Change Mask Register 0 - - '__amforth_dummy':'0' -} diff --git a/amforth-6.5/avr8/devices/atmega6450p/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega6450p/words/no-jtag.asm deleted file mode 100644 index 352a4bb..0000000 --- a/amforth-6.5/avr8/devices/atmega6450p/words/no-jtag.asm +++ /dev/null @@ -1,14 +0,0 @@ -; ( -- ) -; ( -- ) -; MCU -; disable jtag at runtime -VE_NOJTAG: - .dw $FF05 - .db "-jtag",0 - .dw VE_HEAD - .set VE_HEAD = VE_NOJTAG -XT_NOJTAG: - .dw PFA_NOJTAG -PFA_NOJTAG: - - jmp_ DO_NEXT diff --git a/amforth-6.5/avr8/devices/atmega6450p/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega6450p/words/no-wdt.asm deleted file mode 100644 index 4a12261..0000000 --- a/amforth-6.5/avr8/devices/atmega6450p/words/no-wdt.asm +++ /dev/null @@ -1,22 +0,0 @@ -; ( -- ) -; MCU -; disable watch dog timer at runtime -VE_NOWDT: - .dw $ff04 - .db "-wdt" - .dw VE_HEAD - .set VE_HEAD = VE_NOWDT -XT_NOWDT: - .dw PFA_NOWDT -PFA_NOWDT: - -; Reset WDT - wdr -; Write logical one to WDTOE and WDE - in_ temp1, WDTCR - ori temp1, (1<