From 67d25d837ac55f28a366c0a3b262e439a6e75fc3 Mon Sep 17 00:00:00 2001 From: Dimitri Sokolyuk Date: Sat, 19 Aug 2017 12:15:28 +0200 Subject: Add AmForth --- amforth-6.5/avr8/devices/atmega8515/atmega8515.frt | 193 ++++++ amforth-6.5/avr8/devices/atmega8515/device.asm | 90 +++ amforth-6.5/avr8/devices/atmega8515/device.inc | 645 +++++++++++++++++++++ amforth-6.5/avr8/devices/atmega8515/device.py | 178 ++++++ .../avr8/devices/atmega8515/words/no-jtag.asm | 14 + .../avr8/devices/atmega8515/words/no-wdt.asm | 22 + .../avr8/devices/atmega8515/words/sleep.asm | 24 + 7 files changed, 1166 insertions(+) create mode 100644 amforth-6.5/avr8/devices/atmega8515/atmega8515.frt create mode 100644 amforth-6.5/avr8/devices/atmega8515/device.asm create mode 100644 amforth-6.5/avr8/devices/atmega8515/device.inc create mode 100644 amforth-6.5/avr8/devices/atmega8515/device.py create mode 100644 amforth-6.5/avr8/devices/atmega8515/words/no-jtag.asm create mode 100644 amforth-6.5/avr8/devices/atmega8515/words/no-wdt.asm create mode 100644 amforth-6.5/avr8/devices/atmega8515/words/sleep.asm (limited to 'amforth-6.5/avr8/devices/atmega8515') diff --git a/amforth-6.5/avr8/devices/atmega8515/atmega8515.frt b/amforth-6.5/avr8/devices/atmega8515/atmega8515.frt new file mode 100644 index 0000000..576e9e6 --- /dev/null +++ b/amforth-6.5/avr8/devices/atmega8515/atmega8515.frt @@ -0,0 +1,193 @@ +\ Partname: ATmega8515 +\ generated automatically + +\ ANALOG_COMPARATOR +&40 constant ACSR \ Analog Comparator Control And Status Register + $80 constant ACSR_ACD \ Analog Comparator Disable + $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select + $20 constant ACSR_ACO \ Analog Compare Output + $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag + $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable + $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable + $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits +\ USART +&44 constant UDR \ USART I/O Data Register +&43 constant UCSRA \ USART Control and Status Register A + $80 constant UCSRA_RXC \ USART Receive Complete + $40 constant UCSRA_TXC \ USART Transmitt Complete + $20 constant UCSRA_UDRE \ USART Data Register Empty + $10 constant UCSRA_FE \ Framing Error + $08 constant UCSRA_DOR \ Data overRun + $04 constant UCSRA_UPE \ Parity Error + $02 constant UCSRA_U2X \ Double the USART transmission speed + $01 constant UCSRA_MPCM \ Multi-processor Communication Mode +&42 constant UCSRB \ USART Control and Status Register B + $80 constant UCSRB_RXCIE \ RX Complete Interrupt Enable + $40 constant UCSRB_TXCIE \ TX Complete Interrupt Enable + $20 constant UCSRB_UDRIE \ USART Data register Empty Interrupt Enable + $10 constant UCSRB_RXEN \ Receiver Enable + $08 constant UCSRB_TXEN \ Transmitter Enable + $04 constant UCSRB_UCSZ2 \ Character Size Bit 2 + $02 constant UCSRB_RXB8 \ Receive Data Bit 8 + $01 constant UCSRB_TXB8 \ Transmit Data Bit 8 +&64 constant UCSRC \ USART Control and Status Register C + $80 constant UCSRC_URSEL \ Register Select + $40 constant UCSRC_UMSEL \ USART Mode Select + $30 constant UCSRC_UPM \ Parity Mode Bits + $08 constant UCSRC_USBS \ Stop Bit Select + $06 constant UCSRC_UCSZ \ Character Size Bits + $01 constant UCSRC_UCPOL \ Clock Polarity +&64 constant UBRRH \ USART Baud Rate Register High Byte + $80 constant UBRRH_URSEL \ Register Select + $0C constant UBRRH_UBRR1 \ USART Baud Rate Register bit 11 + $03 constant UBRRH_UBRR \ USART Baud Rate Register bits +&41 constant UBRRL \ USART Baud Rate Register Low Byte +\ SPI +&47 constant SPDR \ SPI Data Register +&46 constant SPSR \ SPI Status Register + $80 constant SPSR_SPIF \ SPI Interrupt Flag + $40 constant SPSR_WCOL \ Write Collision Flag + $01 constant SPSR_SPI2X \ Double SPI Speed Bit +&45 constant SPCR \ SPI Control Register + $80 constant SPCR_SPIE \ SPI Interrupt Enable + $40 constant SPCR_SPE \ SPI Enable + $20 constant SPCR_DORD \ Data Order + $10 constant SPCR_MSTR \ Master/Slave Select + $08 constant SPCR_CPOL \ Clock polarity + $04 constant SPCR_CPHA \ Clock Phase + $03 constant SPCR_SPR \ SPI Clock Rate Selects +\ CPU +&95 constant SREG \ Status Register + $80 constant SREG_I \ Global Interrupt Enable + $40 constant SREG_T \ Bit Copy Storage + $20 constant SREG_H \ Half Carry Flag + $10 constant SREG_S \ Sign Bit + $08 constant SREG_V \ Two's Complement Overflow Flag + $04 constant SREG_N \ Negative Flag + $02 constant SREG_Z \ Zero Flag + $01 constant SREG_C \ Carry Flag +&93 constant SP \ Stack Pointer +&86 constant EMCUCR \ Extended MCU Control Register + $80 constant EMCUCR_SM0 \ Sleep Mode Select Bit 0 + $70 constant EMCUCR_SRL \ Wait State Selector Limit bits + $0C constant EMCUCR_SRW0 \ Wait State Select Bits for Lower Sector, bits + $02 constant EMCUCR_SRW11 \ Wait State Select Bits for Upper Sector, bit 1 + $01 constant EMCUCR_ISC2 \ Interrupt Sense Control 2 +&85 constant MCUCR \ MCU Control Register + $80 constant MCUCR_SRE \ External SRAM/XMEM Enable + $40 constant MCUCR_SRW10 \ Wait State Select Bits for Upper Sector, bit 0 + $20 constant MCUCR_SE \ Sleep Enable + $10 constant MCUCR_SM1 \ Sleep Mode Select Bit 1 + $0C constant MCUCR_ISC1 \ Interrupt Sense Control 1 Bits + $03 constant MCUCR_ISC0 \ Interrupt Sense Control 0 Bits +&84 constant MCUCSR \ MCU Control And Status Register + $20 constant MCUCSR_SM2 \ Sleep Mode Select Bit 2 + $08 constant MCUCSR_WDRF \ Watchdog Reset Flag + $04 constant MCUCSR_BORF \ Brown-out Reset Flag + $02 constant MCUCSR_EXTRF \ External Reset Flag + $01 constant MCUCSR_PORF \ Power-on reset flag +&36 constant OSCCAL \ Oscillator Calibration Value +&87 constant SPMCR \ Store Program Memory Control Register + $80 constant SPMCR_SPMIE \ SPM Interrupt Enable + $40 constant SPMCR_RWWSB \ Read-While-Write Section Busy + $10 constant SPMCR_RWWSRE \ Read-While-Write Section Read Enable + $08 constant SPMCR_BLBSET \ Boot Lock Bit Set + $04 constant SPMCR_PGWRT \ Page Write + $02 constant SPMCR_PGERS \ Page Erase + $01 constant SPMCR_SPMEN \ Store Program Memory Enable +&80 constant SFIOR \ Special Function IO Register + $40 constant SFIOR_XMBK \ External Memory Bus Keeper Enable + $38 constant SFIOR_XMM \ External Memory High Mask Bits + $04 constant SFIOR_PUD \ Pull-up Disable + $01 constant SFIOR_PSR10 \ Prescaler Reset Timer / Counter 1 and Timer / Counter 0 +\ EXTERNAL_INTERRUPT +&91 constant GICR \ General Interrupt Control Register + $C0 constant GICR_INT \ External Interrupt Request 1 Enable + $20 constant GICR_INT2 \ External Interrupt Request 2 Enable + $02 constant GICR_IVSEL \ Interrupt Vector Select + $01 constant GICR_IVCE \ Interrupt Vector Change Enable +&90 constant GIFR \ General Interrupt Flag Register + $C0 constant GIFR_INTF \ External Interrupt Flags + $20 constant GIFR_INTF2 \ External Interrupt Flag 2 +\ WATCHDOG +&65 constant WDTCR \ Watchdog Timer Control Register + $10 constant WDTCR_WDCE \ Watchdog Change Enable + $08 constant WDTCR_WDE \ Watch Dog Enable + $07 constant WDTCR_WDP \ Watch Dog Timer Prescaler bits +\ TIMER_COUNTER_0 +&83 constant TCCR0 \ Timer/Counter 0 Control Register + $80 constant TCCR0_FOC0 \ Force Output Compare + $40 constant TCCR0_WGM00 \ Waveform Generation Mode 0 + $30 constant TCCR0_COM0 \ Compare Match Output Modes + $08 constant TCCR0_WGM01 \ Waveform Generation Mode 1 + $07 constant TCCR0_CS0 \ Clock Selects +&82 constant TCNT0 \ Timer/Counter 0 Register +&81 constant OCR0 \ Timer/Counter 0 Output Compare Register +&89 constant TIMSK \ Timer/Counter Interrupt Mask Register + $02 constant TIMSK_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable + $01 constant TIMSK_OCIE0 \ Timer/Counter0 Output Compare Match Interrupt register +&88 constant TIFR \ Timer/Counter Interrupt Flag register + $02 constant TIFR_TOV0 \ Timer/Counter0 Overflow Flag + $01 constant TIFR_OCF0 \ Output Compare Flag 0 +\ TIMER_COUNTER_1 +&79 constant TCCR1A \ Timer/Counter1 Control Register A + $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits + $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits + $08 constant TCCR1A_FOC1A \ Force Output Compare for Channel A + $04 constant TCCR1A_FOC1B \ Force Output Compare for Channel B + $03 constant TCCR1A_WGM1 \ Pulse Width Modulator Select Bits +&78 constant TCCR1B \ Timer/Counter1 Control Register B + $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler + $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select + $18 constant TCCR1B_WGM1 \ Pulse Width Modulator Select Bits + $07 constant TCCR1B_CS1 \ Clock Select1 bits +&76 constant TCNT1 \ Timer/Counter1 Bytes +&74 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes +&72 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes +&68 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes +\ PORTA +&59 constant PORTA \ Port A Data Register +&58 constant DDRA \ Port A Data Direction Register +&57 constant PINA \ Port A Input Pins +\ PORTB +&56 constant PORTB \ Port B Data Register +&55 constant DDRB \ Port B Data Direction Register +&54 constant PINB \ Port B Input Pins +\ PORTC +&53 constant PORTC \ Port C Data Register +&52 constant DDRC \ Port C Data Direction Register +&51 constant PINC \ Port C Input Pins +\ PORTD +&50 constant PORTD \ Port D Data Register +&49 constant DDRD \ Port D Data Direction Register +&48 constant PIND \ Port D Input Pins +\ PORTE +&39 constant PORTE \ Port E Data Register +&38 constant DDRE \ Port E Data Direction Register +&37 constant PINE \ Port E Input Pins +\ EEPROM +&62 constant EEAR \ EEPROM Address Register Bytes +&61 constant EEDR \ EEPROM Data Register +&60 constant EECR \ EEPROM Control Register + $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable + $04 constant EECR_EEMWE \ EEPROM Master Write Enable + $02 constant EECR_EEWE \ EEPROM Write Enable + $01 constant EECR_EERE \ EEPROM Read Enable + +\ Interrupts +&1 constant INT0Addr \ External Interrupt Request 0 +&2 constant INT1Addr \ External Interrupt Request 1 +&3 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event +&4 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A +&5 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare MatchB +&6 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow +&7 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow +&8 constant SPI_STCAddr \ Serial Transfer Complete +&9 constant USART_RXAddr \ USART, Rx Complete +&10 constant USART_UDREAddr \ USART Data Register Empty +&11 constant USART__TXAddr \ USART, Tx Complete +&12 constant ANA_COMPAddr \ Analog Comparator +&13 constant INT2Addr \ External Interrupt Request 2 +&14 constant TIMER0_COMPAddr \ Timer 0 Compare Match +&15 constant EE_RDYAddr \ EEPROM Ready +&16 constant SPM_RDYAddr \ Store Program Memory Ready diff --git a/amforth-6.5/avr8/devices/atmega8515/device.asm b/amforth-6.5/avr8/devices/atmega8515/device.asm new file mode 100644 index 0000000..801e9dc --- /dev/null +++ b/amforth-6.5/avr8/devices/atmega8515/device.asm @@ -0,0 +1,90 @@ +; Partname: ATmega8515 +; generated automatically, do not edit + +.nolist + .include "m8515def.inc" +.list + +.equ ramstart = 96 +.equ CELLSIZE = 2 +.macro readflashcell + lsl zl + rol zh + lpm @0, Z+ + lpm @1, Z+ +.endmacro +.macro writeflashcell + lsl zl + rol zh +.endmacro +.set WANT_ANALOG_COMPARATOR = 0 +.set WANT_USART = 0 +.set WANT_SPI = 0 +.set WANT_CPU = 0 +.set WANT_EXTERNAL_INTERRUPT = 0 +.set WANT_WATCHDOG = 0 +.set WANT_TIMER_COUNTER_0 = 0 +.set WANT_TIMER_COUNTER_1 = 0 +.set WANT_PORTA = 0 +.set WANT_PORTB = 0 +.set WANT_PORTC = 0 +.set WANT_PORTD = 0 +.set WANT_PORTE = 0 +.set WANT_EEPROM = 0 +.equ intvecsize = 1 ; please verify; flash size: 8192 bytes +.equ pclen = 2 ; please verify +.overlap +.org 1 + rcall isr ; External Interrupt Request 0 +.org 2 + rcall isr ; External Interrupt Request 1 +.org 3 + rcall isr ; Timer/Counter1 Capture Event +.org 4 + rcall isr ; Timer/Counter1 Compare Match A +.org 5 + rcall isr ; Timer/Counter1 Compare MatchB +.org 6 + rcall isr ; Timer/Counter1 Overflow +.org 7 + rcall isr ; Timer/Counter0 Overflow +.org 8 + rcall isr ; Serial Transfer Complete +.org 9 + rcall isr ; USART, Rx Complete +.org 10 + rcall isr ; USART Data Register Empty +.org 11 + rcall isr ; USART, Tx Complete +.org 12 + rcall isr ; Analog Comparator +.org 13 + rcall isr ; External Interrupt Request 2 +.org 14 + rcall isr ; Timer 0 Compare Match +.org 15 + rcall isr ; EEPROM Ready +.org 16 + rcall isr ; Store Program Memory Ready +.equ INTVECTORS = 17 +.nooverlap + +; compatability layer (maybe empty) +.equ SPMCSR = SPMCR +.equ EEPE = EEWE +.equ EEMPE = EEMWE + +; controller data area, environment query mcu-info +mcu_info: +mcu_ramsize: + .dw 512 +mcu_eepromsize: + .dw 512 +mcu_maxdp: + .dw 6144 +mcu_numints: + .dw 17 +mcu_name: + .dw 10 + .db "ATmega8515" +.set codestart=pc diff --git a/amforth-6.5/avr8/devices/atmega8515/device.inc b/amforth-6.5/avr8/devices/atmega8515/device.inc new file mode 100644 index 0000000..a8b7e91 --- /dev/null +++ b/amforth-6.5/avr8/devices/atmega8515/device.inc @@ -0,0 +1,645 @@ +; Partname: ATmega8515 +; generated automatically, no not edit + +.if WANT_ANALOG_COMPARATOR == 1 +; ( -- addr ) System Constant +; R( -- ) +; Analog Comparator Control And Status Register +VE_ACSR: + .dw $ff04 + .db "ACSR" + .dw VE_HEAD + .set VE_HEAD=VE_ACSR +XT_ACSR: + .dw PFA_DOVARIABLE +PFA_ACSR: + .dw 40 + +.endif +.if WANT_USART == 1 +; ( -- addr ) System Constant +; R( -- ) +; USART I/O Data Register +VE_UDR: + .dw $ff03 + .db "UDR",0 + .dw VE_HEAD + .set VE_HEAD=VE_UDR +XT_UDR: + .dw PFA_DOVARIABLE +PFA_UDR: + .dw 44 +; ( -- addr ) System Constant +; R( -- ) +; USART Control and Status Register A +VE_UCSRA: + .dw $ff05 + .db "UCSRA",0 + .dw VE_HEAD + .set VE_HEAD=VE_UCSRA +XT_UCSRA: + .dw PFA_DOVARIABLE +PFA_UCSRA: + .dw 43 +; ( -- addr ) System Constant +; R( -- ) +; USART Control and Status Register B +VE_UCSRB: + .dw $ff05 + .db "UCSRB",0 + .dw VE_HEAD + .set VE_HEAD=VE_UCSRB +XT_UCSRB: + .dw PFA_DOVARIABLE +PFA_UCSRB: + .dw 42 +; ( -- addr ) System Constant +; R( -- ) +; USART Control and Status Register C +VE_UCSRC: + .dw $ff05 + .db "UCSRC",0 + .dw VE_HEAD + .set VE_HEAD=VE_UCSRC +XT_UCSRC: + .dw PFA_DOVARIABLE +PFA_UCSRC: + .dw 64 +; ( -- addr ) System Constant +; R( -- ) +; USART Baud Rate Register High Byte +VE_UBRRH: + .dw $ff05 + .db "UBRRH",0 + .dw VE_HEAD + .set VE_HEAD=VE_UBRRH +XT_UBRRH: + .dw PFA_DOVARIABLE +PFA_UBRRH: + .dw 64 +; ( -- addr ) System Constant +; R( -- ) +; USART Baud Rate Register Low Byte +VE_UBRRL: + .dw $ff05 + .db "UBRRL",0 + .dw VE_HEAD + .set VE_HEAD=VE_UBRRL +XT_UBRRL: + .dw PFA_DOVARIABLE +PFA_UBRRL: + .dw 41 + +.endif +.if WANT_SPI == 1 +; ( -- addr ) System Constant +; R( -- ) +; SPI Data Register +VE_SPDR: + .dw $ff04 + .db "SPDR" + .dw VE_HEAD + .set VE_HEAD=VE_SPDR +XT_SPDR: + .dw PFA_DOVARIABLE +PFA_SPDR: + .dw 47 +; ( -- addr ) System Constant +; R( -- ) +; SPI Status Register +VE_SPSR: + .dw $ff04 + .db "SPSR" + .dw VE_HEAD + .set VE_HEAD=VE_SPSR +XT_SPSR: + .dw PFA_DOVARIABLE +PFA_SPSR: + .dw 46 +; ( -- addr ) System Constant +; R( -- ) +; SPI Control Register +VE_SPCR: + .dw $ff04 + .db "SPCR" + .dw VE_HEAD + .set VE_HEAD=VE_SPCR +XT_SPCR: + .dw PFA_DOVARIABLE +PFA_SPCR: + .dw 45 + +.endif +.if WANT_CPU == 1 +; ( -- addr ) System Constant +; R( -- ) +; Status Register +VE_SREG: + .dw $ff04 + .db "SREG" + .dw VE_HEAD + .set VE_HEAD=VE_SREG +XT_SREG: + .dw PFA_DOVARIABLE +PFA_SREG: + .dw 95 +; ( -- addr ) System Constant +; R( -- ) +; Stack Pointer +VE_SP: + .dw $ff02 + .db "SP" + .dw VE_HEAD + .set VE_HEAD=VE_SP +XT_SP: + .dw PFA_DOVARIABLE +PFA_SP: + .dw 93 +; ( -- addr ) System Constant +; R( -- ) +; Extended MCU Control Register +VE_EMCUCR: + .dw $ff06 + .db "EMCUCR" + .dw VE_HEAD + .set VE_HEAD=VE_EMCUCR +XT_EMCUCR: + .dw PFA_DOVARIABLE +PFA_EMCUCR: + .dw 86 +; ( -- addr ) System Constant +; R( -- ) +; MCU Control Register +VE_MCUCR: + .dw $ff05 + .db "MCUCR",0 + .dw VE_HEAD + .set VE_HEAD=VE_MCUCR +XT_MCUCR: + .dw PFA_DOVARIABLE +PFA_MCUCR: + .dw 85 +; ( -- addr ) System Constant +; R( -- ) +; MCU Control And Status Register +VE_MCUCSR: + .dw $ff06 + .db "MCUCSR" + .dw VE_HEAD + .set VE_HEAD=VE_MCUCSR +XT_MCUCSR: + .dw PFA_DOVARIABLE +PFA_MCUCSR: + .dw 84 +; ( -- addr ) System Constant +; R( -- ) +; Oscillator Calibration Value +VE_OSCCAL: + .dw $ff06 + .db "OSCCAL" + .dw VE_HEAD + .set VE_HEAD=VE_OSCCAL +XT_OSCCAL: + .dw PFA_DOVARIABLE +PFA_OSCCAL: + .dw 36 +; ( -- addr ) System Constant +; R( -- ) +; Store Program Memory Control Register +VE_SPMCR: + .dw $ff05 + .db "SPMCR",0 + .dw VE_HEAD + .set VE_HEAD=VE_SPMCR +XT_SPMCR: + .dw PFA_DOVARIABLE +PFA_SPMCR: + .dw 87 +; ( -- addr ) System Constant +; R( -- ) +; Special Function IO Register +VE_SFIOR: + .dw $ff05 + .db "SFIOR",0 + .dw VE_HEAD + .set VE_HEAD=VE_SFIOR +XT_SFIOR: + .dw PFA_DOVARIABLE +PFA_SFIOR: + .dw 80 + +.endif +.if WANT_EXTERNAL_INTERRUPT == 1 +; ( -- addr ) System Constant +; R( -- ) +; General Interrupt Control Register +VE_GICR: + .dw $ff04 + .db "GICR" + .dw VE_HEAD + .set VE_HEAD=VE_GICR +XT_GICR: + .dw PFA_DOVARIABLE +PFA_GICR: + .dw 91 +; ( -- addr ) System Constant +; R( -- ) +; General Interrupt Flag Register +VE_GIFR: + .dw $ff04 + .db "GIFR" + .dw VE_HEAD + .set VE_HEAD=VE_GIFR +XT_GIFR: + .dw PFA_DOVARIABLE +PFA_GIFR: + .dw 90 + +.endif +.if WANT_WATCHDOG == 1 +; ( -- addr ) System Constant +; R( -- ) +; Watchdog Timer Control Register +VE_WDTCR: + .dw $ff05 + .db "WDTCR",0 + .dw VE_HEAD + .set VE_HEAD=VE_WDTCR +XT_WDTCR: + .dw PFA_DOVARIABLE +PFA_WDTCR: + .dw 65 + +.endif +.if WANT_TIMER_COUNTER_0 == 1 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter 0 Control Register +VE_TCCR0: + .dw $ff05 + .db "TCCR0",0 + .dw VE_HEAD + .set VE_HEAD=VE_TCCR0 +XT_TCCR0: + .dw PFA_DOVARIABLE +PFA_TCCR0: + .dw 83 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter 0 Register +VE_TCNT0: + .dw $ff05 + .db "TCNT0",0 + .dw VE_HEAD + .set VE_HEAD=VE_TCNT0 +XT_TCNT0: + .dw PFA_DOVARIABLE +PFA_TCNT0: + .dw 82 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter 0 Output Compare Register +VE_OCR0: + .dw $ff04 + .db "OCR0" + .dw VE_HEAD + .set VE_HEAD=VE_OCR0 +XT_OCR0: + .dw PFA_DOVARIABLE +PFA_OCR0: + .dw 81 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter Interrupt Mask Register +VE_TIMSK: + .dw $ff05 + .db "TIMSK",0 + .dw VE_HEAD + .set VE_HEAD=VE_TIMSK +XT_TIMSK: + .dw PFA_DOVARIABLE +PFA_TIMSK: + .dw 89 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter Interrupt Flag register +VE_TIFR: + .dw $ff04 + .db "TIFR" + .dw VE_HEAD + .set VE_HEAD=VE_TIFR +XT_TIFR: + .dw PFA_DOVARIABLE +PFA_TIFR: + .dw 88 + +.endif +.if WANT_TIMER_COUNTER_1 == 1 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter1 Control Register A +VE_TCCR1A: + .dw $ff06 + .db "TCCR1A" + .dw VE_HEAD + .set VE_HEAD=VE_TCCR1A +XT_TCCR1A: + .dw PFA_DOVARIABLE +PFA_TCCR1A: + .dw 79 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter1 Control Register B +VE_TCCR1B: + .dw $ff06 + .db "TCCR1B" + .dw VE_HEAD + .set VE_HEAD=VE_TCCR1B +XT_TCCR1B: + .dw PFA_DOVARIABLE +PFA_TCCR1B: + .dw 78 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter1 Bytes +VE_TCNT1: + .dw $ff05 + .db "TCNT1",0 + .dw VE_HEAD + .set VE_HEAD=VE_TCNT1 +XT_TCNT1: + .dw PFA_DOVARIABLE +PFA_TCNT1: + .dw 76 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter1 Output Compare Register A Bytes +VE_OCR1A: + .dw $ff05 + .db "OCR1A",0 + .dw VE_HEAD + .set VE_HEAD=VE_OCR1A +XT_OCR1A: + .dw PFA_DOVARIABLE +PFA_OCR1A: + .dw 74 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter1 Output Compare Register B Bytes +VE_OCR1B: + .dw $ff05 + .db "OCR1B",0 + .dw VE_HEAD + .set VE_HEAD=VE_OCR1B +XT_OCR1B: + .dw PFA_DOVARIABLE +PFA_OCR1B: + .dw 72 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter1 Input Capture Register Bytes +VE_ICR1: + .dw $ff04 + .db "ICR1" + .dw VE_HEAD + .set VE_HEAD=VE_ICR1 +XT_ICR1: + .dw PFA_DOVARIABLE +PFA_ICR1: + .dw 68 + +.endif +.if WANT_PORTA == 1 +; ( -- addr ) System Constant +; R( -- ) +; Port A Data Register +VE_PORTA: + .dw $ff05 + .db "PORTA",0 + .dw VE_HEAD + .set VE_HEAD=VE_PORTA +XT_PORTA: + .dw PFA_DOVARIABLE +PFA_PORTA: + .dw 59 +; ( -- addr ) System Constant +; R( -- ) +; Port A Data Direction Register +VE_DDRA: + .dw $ff04 + .db "DDRA" + .dw VE_HEAD + .set VE_HEAD=VE_DDRA +XT_DDRA: + .dw PFA_DOVARIABLE +PFA_DDRA: + .dw 58 +; ( -- addr ) System Constant +; R( -- ) +; Port A Input Pins +VE_PINA: + .dw $ff04 + .db "PINA" + .dw VE_HEAD + .set VE_HEAD=VE_PINA +XT_PINA: + .dw PFA_DOVARIABLE +PFA_PINA: + .dw 57 + +.endif +.if WANT_PORTB == 1 +; ( -- addr ) System Constant +; R( -- ) +; Port B Data Register +VE_PORTB: + .dw $ff05 + .db "PORTB",0 + .dw VE_HEAD + .set VE_HEAD=VE_PORTB +XT_PORTB: + .dw PFA_DOVARIABLE +PFA_PORTB: + .dw 56 +; ( -- addr ) System Constant +; R( -- ) +; Port B Data Direction Register +VE_DDRB: + .dw $ff04 + .db "DDRB" + .dw VE_HEAD + .set VE_HEAD=VE_DDRB +XT_DDRB: + .dw PFA_DOVARIABLE +PFA_DDRB: + .dw 55 +; ( -- addr ) System Constant +; R( -- ) +; Port B Input Pins +VE_PINB: + .dw $ff04 + .db "PINB" + .dw VE_HEAD + .set VE_HEAD=VE_PINB +XT_PINB: + .dw PFA_DOVARIABLE +PFA_PINB: + .dw 54 + +.endif +.if WANT_PORTC == 1 +; ( -- addr ) System Constant +; R( -- ) +; Port C Data Register +VE_PORTC: + .dw $ff05 + .db "PORTC",0 + .dw VE_HEAD + .set VE_HEAD=VE_PORTC +XT_PORTC: + .dw PFA_DOVARIABLE +PFA_PORTC: + .dw 53 +; ( -- addr ) System Constant +; R( -- ) +; Port C Data Direction Register +VE_DDRC: + .dw $ff04 + .db "DDRC" + .dw VE_HEAD + .set VE_HEAD=VE_DDRC +XT_DDRC: + .dw PFA_DOVARIABLE +PFA_DDRC: + .dw 52 +; ( -- addr ) System Constant +; R( -- ) +; Port C Input Pins +VE_PINC: + .dw $ff04 + .db "PINC" + .dw VE_HEAD + .set VE_HEAD=VE_PINC +XT_PINC: + .dw PFA_DOVARIABLE +PFA_PINC: + .dw 51 + +.endif +.if WANT_PORTD == 1 +; ( -- addr ) System Constant +; R( -- ) +; Port D Data Register +VE_PORTD: + .dw $ff05 + .db "PORTD",0 + .dw VE_HEAD + .set VE_HEAD=VE_PORTD +XT_PORTD: + .dw PFA_DOVARIABLE +PFA_PORTD: + .dw 50 +; ( -- addr ) System Constant +; R( -- ) +; Port D Data Direction Register +VE_DDRD: + .dw $ff04 + .db "DDRD" + .dw VE_HEAD + .set VE_HEAD=VE_DDRD +XT_DDRD: + .dw PFA_DOVARIABLE +PFA_DDRD: + .dw 49 +; ( -- addr ) System Constant +; R( -- ) +; Port D Input Pins +VE_PIND: + .dw $ff04 + .db "PIND" + .dw VE_HEAD + .set VE_HEAD=VE_PIND +XT_PIND: + .dw PFA_DOVARIABLE +PFA_PIND: + .dw 48 + +.endif +.if WANT_PORTE == 1 +; ( -- addr ) System Constant +; R( -- ) +; Port E Data Register +VE_PORTE: + .dw $ff05 + .db "PORTE",0 + .dw VE_HEAD + .set VE_HEAD=VE_PORTE +XT_PORTE: + .dw PFA_DOVARIABLE +PFA_PORTE: + .dw 39 +; ( -- addr ) System Constant +; R( -- ) +; Port E Data Direction Register +VE_DDRE: + .dw $ff04 + .db "DDRE" + .dw VE_HEAD + .set VE_HEAD=VE_DDRE +XT_DDRE: + .dw PFA_DOVARIABLE +PFA_DDRE: + .dw 38 +; ( -- addr ) System Constant +; R( -- ) +; Port E Input Pins +VE_PINE: + .dw $ff04 + .db "PINE" + .dw VE_HEAD + .set VE_HEAD=VE_PINE +XT_PINE: + .dw PFA_DOVARIABLE +PFA_PINE: + .dw 37 + +.endif +.if WANT_EEPROM == 1 +; ( -- addr ) System Constant +; R( -- ) +; EEPROM Address Register Bytes +VE_EEAR: + .dw $ff04 + .db "EEAR" + .dw VE_HEAD + .set VE_HEAD=VE_EEAR +XT_EEAR: + .dw PFA_DOVARIABLE +PFA_EEAR: + .dw 62 +; ( -- addr ) System Constant +; R( -- ) +; EEPROM Data Register +VE_EEDR: + .dw $ff04 + .db "EEDR" + .dw VE_HEAD + .set VE_HEAD=VE_EEDR +XT_EEDR: + .dw PFA_DOVARIABLE +PFA_EEDR: + .dw 61 +; ( -- addr ) System Constant +; R( -- ) +; EEPROM Control Register +VE_EECR: + .dw $ff04 + .db "EECR" + .dw VE_HEAD + .set VE_HEAD=VE_EECR +XT_EECR: + .dw PFA_DOVARIABLE +PFA_EECR: + .dw 60 + +.endif diff --git a/amforth-6.5/avr8/devices/atmega8515/device.py b/amforth-6.5/avr8/devices/atmega8515/device.py new file mode 100644 index 0000000..463fdb8 --- /dev/null +++ b/amforth-6.5/avr8/devices/atmega8515/device.py @@ -0,0 +1,178 @@ +# Partname: ATmega8515 +# generated automatically, do not edit +MCUREGS = { + 'ACSR': '&40', + 'ACSR_ACD': '$80', + 'ACSR_ACBG': '$40', + 'ACSR_ACO': '$20', + 'ACSR_ACI': '$10', + 'ACSR_ACIE': '$08', + 'ACSR_ACIC': '$04', + 'ACSR_ACIS': '$03', + 'UDR': '&44', + 'UCSRA': '&43', + 'UCSRA_RXC': '$80', + 'UCSRA_TXC': '$40', + 'UCSRA_UDRE': '$20', + 'UCSRA_FE': '$10', + 'UCSRA_DOR': '$08', + 'UCSRA_UPE': '$04', + 'UCSRA_U2X': '$02', + 'UCSRA_MPCM': '$01', + 'UCSRB': '&42', + 'UCSRB_RXCIE': '$80', + 'UCSRB_TXCIE': '$40', + 'UCSRB_UDRIE': '$20', + 'UCSRB_RXEN': '$10', + 'UCSRB_TXEN': '$08', + 'UCSRB_UCSZ2': '$04', + 'UCSRB_RXB8': '$02', + 'UCSRB_TXB8': '$01', + 'UCSRC': '&64', + 'UCSRC_URSEL': '$80', + 'UCSRC_UMSEL': '$40', + 'UCSRC_UPM': '$30', + 'UCSRC_USBS': '$08', + 'UCSRC_UCSZ': '$06', + 'UCSRC_UCPOL': '$01', + 'UBRRH': '&64', + 'UBRRH_URSEL': '$80', + 'UBRRH_UBRR1': '$0C', + 'UBRRH_UBRR': '$03', + 'UBRRL': '&41', + 'SPDR': '&47', + 'SPSR': '&46', + 'SPSR_SPIF': '$80', + 'SPSR_WCOL': '$40', + 'SPSR_SPI2X': '$01', + 'SPCR': '&45', + 'SPCR_SPIE': '$80', + 'SPCR_SPE': '$40', + 'SPCR_DORD': '$20', + 'SPCR_MSTR': '$10', + 'SPCR_CPOL': '$08', + 'SPCR_CPHA': '$04', + 'SPCR_SPR': '$03', + 'SREG': '&95', + 'SREG_I': '$80', + 'SREG_T': '$40', + 'SREG_H': '$20', + 'SREG_S': '$10', + 'SREG_V': '$08', + 'SREG_N': '$04', + 'SREG_Z': '$02', + 'SREG_C': '$01', + 'SP': '&93', + 'EMCUCR': '&86', + 'EMCUCR_SM0': '$80', + 'EMCUCR_SRL': '$70', + 'EMCUCR_SRW0': '$0C', + 'EMCUCR_SRW11': '$02', + 'EMCUCR_ISC2': '$01', + 'MCUCR': '&85', + 'MCUCR_SRE': '$80', + 'MCUCR_SRW10': '$40', + 'MCUCR_SE': '$20', + 'MCUCR_SM1': '$10', + 'MCUCR_ISC1': '$0C', + 'MCUCR_ISC0': '$03', + 'MCUCSR': '&84', + 'MCUCSR_SM2': '$20', + 'MCUCSR_WDRF': '$08', + 'MCUCSR_BORF': '$04', + 'MCUCSR_EXTRF': '$02', + 'MCUCSR_PORF': '$01', + 'OSCCAL': '&36', + 'SPMCR': '&87', + 'SPMCR_SPMIE': '$80', + 'SPMCR_RWWSB': '$40', + 'SPMCR_RWWSRE': '$10', + 'SPMCR_BLBSET': '$08', + 'SPMCR_PGWRT': '$04', + 'SPMCR_PGERS': '$02', + 'SPMCR_SPMEN': '$01', + 'SFIOR': '&80', + 'SFIOR_XMBK': '$40', + 'SFIOR_XMM': '$38', + 'SFIOR_PUD': '$04', + 'SFIOR_PSR10': '$01', + 'GICR': '&91', + 'GICR_INT': '$C0', + 'GICR_INT2': '$20', + 'GICR_IVSEL': '$02', + 'GICR_IVCE': '$01', + 'GIFR': '&90', + 'GIFR_INTF': '$C0', + 'GIFR_INTF2': '$20', + 'WDTCR': '&65', + 'WDTCR_WDCE': '$10', + 'WDTCR_WDE': '$08', + 'WDTCR_WDP': '$07', + 'TCCR0': '&83', + 'TCCR0_FOC0': '$80', + 'TCCR0_WGM00': '$40', + 'TCCR0_COM0': '$30', + 'TCCR0_WGM01': '$08', + 'TCCR0_CS0': '$07', + 'TCNT0': '&82', + 'OCR0': '&81', + 'TIMSK': '&89', + 'TIMSK_TOIE0': '$02', + 'TIMSK_OCIE0': '$01', + 'TIFR': '&88', + 'TIFR_TOV0': '$02', + 'TIFR_OCF0': '$01', + 'TCCR1A': '&79', + 'TCCR1A_COM1A': '$C0', + 'TCCR1A_COM1B': '$30', + 'TCCR1A_FOC1A': '$08', + 'TCCR1A_FOC1B': '$04', + 'TCCR1A_WGM1': '$03', + 'TCCR1B': '&78', + 'TCCR1B_ICNC1': '$80', + 'TCCR1B_ICES1': '$40', + 'TCCR1B_WGM1': '$18', + 'TCCR1B_CS1': '$07', + 'TCNT1': '&76', + 'OCR1A': '&74', + 'OCR1B': '&72', + 'ICR1': '&68', + 'PORTA': '&59', + 'DDRA': '&58', + 'PINA': '&57', + 'PORTB': '&56', + 'DDRB': '&55', + 'PINB': '&54', + 'PORTC': '&53', + 'DDRC': '&52', + 'PINC': '&51', + 'PORTD': '&50', + 'DDRD': '&49', + 'PIND': '&48', + 'PORTE': '&39', + 'DDRE': '&38', + 'PINE': '&37', + 'EEAR': '&62', + 'EEDR': '&61', + 'EECR': '&60', + 'EECR_EERIE': '$08', + 'EECR_EEMWE': '$04', + 'EECR_EEWE': '$02', + 'EECR_EERE': '$01', + 'INT0Addr': '1', + 'INT1Addr': '2', + 'TIMER1_CAPTAddr': '3', + 'TIMER1_COMPAAddr': '4', + 'TIMER1_COMPBAddr': '5', + 'TIMER1_OVFAddr': '6', + 'TIMER0_OVFAddr': '7', + 'SPI_STCAddr': '8', + 'USART_RXAddr': '9', + 'USART_UDREAddr': '10', + 'USART__TXAddr': '11', + 'ANA_COMPAddr': '12', + 'INT2Addr': '13', + 'TIMER0_COMPAddr': '14', + 'EE_RDYAddr': '15', + 'SPM_RDYAddr': '16' +} \ No newline at end of file diff --git a/amforth-6.5/avr8/devices/atmega8515/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega8515/words/no-jtag.asm new file mode 100644 index 0000000..352a4bb --- /dev/null +++ b/amforth-6.5/avr8/devices/atmega8515/words/no-jtag.asm @@ -0,0 +1,14 @@ +; ( -- ) +; ( -- ) +; MCU +; disable jtag at runtime +VE_NOJTAG: + .dw $FF05 + .db "-jtag",0 + .dw VE_HEAD + .set VE_HEAD = VE_NOJTAG +XT_NOJTAG: + .dw PFA_NOJTAG +PFA_NOJTAG: + + jmp_ DO_NEXT diff --git a/amforth-6.5/avr8/devices/atmega8515/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega8515/words/no-wdt.asm new file mode 100644 index 0000000..4a12261 --- /dev/null +++ b/amforth-6.5/avr8/devices/atmega8515/words/no-wdt.asm @@ -0,0 +1,22 @@ +; ( -- ) +; MCU +; disable watch dog timer at runtime +VE_NOWDT: + .dw $ff04 + .db "-wdt" + .dw VE_HEAD + .set VE_HEAD = VE_NOWDT +XT_NOWDT: + .dw PFA_NOWDT +PFA_NOWDT: + +; Reset WDT + wdr +; Write logical one to WDTOE and WDE + in_ temp1, WDTCR + ori temp1, (1<