From 67d25d837ac55f28a366c0a3b262e439a6e75fc3 Mon Sep 17 00:00:00 2001 From: Dimitri Sokolyuk Date: Sat, 19 Aug 2017 12:15:28 +0200 Subject: Add AmForth --- amforth-6.5/avr8/devices/atmega8535/device.py | 203 ++++++++++++++++++++++++++ 1 file changed, 203 insertions(+) create mode 100644 amforth-6.5/avr8/devices/atmega8535/device.py (limited to 'amforth-6.5/avr8/devices/atmega8535/device.py') diff --git a/amforth-6.5/avr8/devices/atmega8535/device.py b/amforth-6.5/avr8/devices/atmega8535/device.py new file mode 100644 index 0000000..413668b --- /dev/null +++ b/amforth-6.5/avr8/devices/atmega8535/device.py @@ -0,0 +1,203 @@ +# Partname: ATmega8535 +# generated automatically, do not edit +MCUREGS = { + 'ADMUX': '&39', + 'ADMUX_REFS': '$C0', + 'ADMUX_ADLAR': '$20', + 'ADMUX_MUX': '$1F', + 'ADCSRA': '&38', + 'ADCSRA_ADEN': '$80', + 'ADCSRA_ADSC': '$40', + 'ADCSRA_ADATE': '$20', + 'ADCSRA_ADIF': '$10', + 'ADCSRA_ADIE': '$08', + 'ADCSRA_ADPS': '$07', + 'ADC': '&36', + 'SFIOR': '&80', + 'SFIOR_ADTS': '$E0', + 'ACSR': '&40', + 'ACSR_ACD': '$80', + 'ACSR_ACBG': '$40', + 'ACSR_ACO': '$20', + 'ACSR_ACI': '$10', + 'ACSR_ACIE': '$08', + 'ACSR_ACIC': '$04', + 'ACSR_ACIS': '$03', + 'TWBR': '&32', + 'TWCR': '&86', + 'TWCR_TWINT': '$80', + 'TWCR_TWEA': '$40', + 'TWCR_TWSTA': '$20', + 'TWCR_TWSTO': '$10', + 'TWCR_TWWC': '$08', + 'TWCR_TWEN': '$04', + 'TWCR_TWIE': '$01', + 'TWSR': '&33', + 'TWSR_TWS': '$F8', + 'TWSR_TWPS': '$03', + 'TWDR': '&35', + 'TWAR': '&34', + 'TWAR_TWA': '$FE', + 'TWAR_TWGCE': '$01', + 'UDR': '&44', + 'UCSRA': '&43', + 'UCSRA_RXC': '$80', + 'UCSRA_TXC': '$40', + 'UCSRA_UDRE': '$20', + 'UCSRA_FE': '$10', + 'UCSRA_DOR': '$08', + 'UCSRA_UPE': '$04', + 'UCSRA_U2X': '$02', + 'UCSRA_MPCM': '$01', + 'UCSRB': '&42', + 'UCSRB_RXCIE': '$80', + 'UCSRB_TXCIE': '$40', + 'UCSRB_UDRIE': '$20', + 'UCSRB_RXEN': '$10', + 'UCSRB_TXEN': '$08', + 'UCSRB_UCSZ2': '$04', + 'UCSRB_RXB8': '$02', + 'UCSRB_TXB8': '$01', + 'UCSRC': '&64', + 'UCSRC_URSEL': '$80', + 'UCSRC_UMSEL': '$40', + 'UCSRC_UPM': '$30', + 'UCSRC_USBS': '$08', + 'UCSRC_UCSZ': '$06', + 'UCSRC_UCPOL': '$01', + 'UBRRH': '&64', + 'UBRRH_URSEL': '$80', + 'UBRRH_UBRR1': '$0C', + 'UBRRH_UBRR': '$03', + 'UBRRL': '&41', + 'PORTA': '&59', + 'DDRA': '&58', + 'PINA': '&57', + 'PORTB': '&56', + 'DDRB': '&55', + 'PINB': '&54', + 'PORTC': '&53', + 'DDRC': '&52', + 'PINC': '&51', + 'PORTD': '&50', + 'DDRD': '&49', + 'PIND': '&48', + 'SPDR': '&47', + 'SPSR': '&46', + 'SPSR_SPIF': '$80', + 'SPSR_WCOL': '$40', + 'SPSR_SPI2X': '$01', + 'SPCR': '&45', + 'SPCR_SPIE': '$80', + 'SPCR_SPE': '$40', + 'SPCR_DORD': '$20', + 'SPCR_MSTR': '$10', + 'SPCR_CPOL': '$08', + 'SPCR_CPHA': '$04', + 'SPCR_SPR': '$03', + 'EEAR': '&62', + 'EEDR': '&61', + 'EECR': '&60', + 'EECR_EERIE': '$08', + 'EECR_EEMWE': '$04', + 'EECR_EEWE': '$02', + 'EECR_EERE': '$01', + 'TCCR0': '&83', + 'TCCR0_FOC0': '$80', + 'TCCR0_WGM00': '$40', + 'TCCR0_COM0': '$30', + 'TCCR0_WGM01': '$08', + 'TCCR0_CS0': '$07', + 'TCNT0': '&82', + 'OCR0': '&92', + 'TIMSK': '&89', + 'TIMSK_OCIE0': '$02', + 'TIMSK_TOIE0': '$01', + 'TIFR': '&88', + 'TIFR_OCF0': '$02', + 'TIFR_TOV0': '$01', + 'TCCR1A': '&79', + 'TCCR1A_COM1A': '$C0', + 'TCCR1A_COM1B': '$30', + 'TCCR1A_FOC1A': '$08', + 'TCCR1A_FOC1B': '$04', + 'TCCR1A_WGM1': '$03', + 'TCCR1B': '&78', + 'TCCR1B_ICNC1': '$80', + 'TCCR1B_ICES1': '$40', + 'TCCR1B_WGM1': '$18', + 'TCCR1B_CS1': '$07', + 'TCNT1': '&76', + 'OCR1A': '&74', + 'OCR1B': '&72', + 'ICR1': '&70', + 'TCCR2': '&69', + 'TCCR2_FOC2': '$80', + 'TCCR2_WGM20': '$40', + 'TCCR2_COM2': '$30', + 'TCCR2_WGM21': '$08', + 'TCCR2_CS2': '$07', + 'TCNT2': '&68', + 'OCR2': '&67', + 'ASSR': '&66', + 'ASSR_AS2': '$08', + 'ASSR_TCN2UB': '$04', + 'ASSR_OCR2UB': '$02', + 'ASSR_TCR2UB': '$01', + 'GICR': '&91', + 'GICR_INT': '$C0', + 'GICR_INT2': '$20', + 'GICR_IVSEL': '$02', + 'GICR_IVCE': '$01', + 'GIFR': '&90', + 'GIFR_INTF': '$C0', + 'GIFR_INTF2': '$20', + 'MCUCR': '&85', + 'MCUCR_ISC1': '$0C', + 'MCUCR_ISC0': '$03', + 'MCUCSR': '&84', + 'MCUCSR_ISC2': '$40', + 'WDTCR': '&65', + 'WDTCR_WDCE': '$10', + 'WDTCR_WDE': '$08', + 'WDTCR_WDP': '$07', + 'SREG': '&95', + 'SREG_I': '$80', + 'SREG_T': '$40', + 'SREG_H': '$20', + 'SREG_S': '$10', + 'SREG_V': '$08', + 'SREG_N': '$04', + 'SREG_Z': '$02', + 'SREG_C': '$01', + 'SP': '&93', + 'OSCCAL': '&81', + 'SPMCR': '&87', + 'SPMCR_SPMIE': '$80', + 'SPMCR_RWWSB': '$40', + 'SPMCR_RWWSRE': '$10', + 'SPMCR_BLBSET': '$08', + 'SPMCR_PGWRT': '$04', + 'SPMCR_PGERS': '$02', + 'SPMCR_SPMEN': '$01', + 'INT0Addr': '1', + 'INT1Addr': '2', + 'TIMER2_COMPAddr': '3', + 'TIMER2_OVFAddr': '4', + 'TIMER1_CAPTAddr': '5', + 'TIMER1_COMPAAddr': '6', + 'TIMER1_COMPBAddr': '7', + 'TIMER1_OVFAddr': '8', + 'TIMER0_OVFAddr': '9', + 'SPI_STCAddr': '10', + 'USART_RXAddr': '11', + 'USART_UDREAddr': '12', + 'USART_TXAddr': '13', + 'ADCAddr': '14', + 'EE_RDYAddr': '15', + 'ANA_COMPAddr': '16', + 'TWIAddr': '17', + 'INT2Addr': '18', + 'TIMER0_COMPAddr': '19', + 'SPM_RDYAddr': '20' +} \ No newline at end of file -- cgit v1.2.3