From 67d25d837ac55f28a366c0a3b262e439a6e75fc3 Mon Sep 17 00:00:00 2001 From: Dimitri Sokolyuk Date: Sat, 19 Aug 2017 12:15:28 +0200 Subject: Add AmForth --- amforth-6.5/avr8/devices/atmega88a/atmega88a.frt | 297 ++++++ amforth-6.5/avr8/devices/atmega88a/device.asm | 107 +++ amforth-6.5/avr8/devices/atmega88a/device.inc | 996 +++++++++++++++++++++ amforth-6.5/avr8/devices/atmega88a/device.py | 281 ++++++ .../avr8/devices/atmega88a/words/no-jtag.asm | 14 + .../avr8/devices/atmega88a/words/no-wdt.asm | 34 + amforth-6.5/avr8/devices/atmega88a/words/sleep.asm | 19 + 7 files changed, 1748 insertions(+) create mode 100644 amforth-6.5/avr8/devices/atmega88a/atmega88a.frt create mode 100644 amforth-6.5/avr8/devices/atmega88a/device.asm create mode 100644 amforth-6.5/avr8/devices/atmega88a/device.inc create mode 100644 amforth-6.5/avr8/devices/atmega88a/device.py create mode 100644 amforth-6.5/avr8/devices/atmega88a/words/no-jtag.asm create mode 100644 amforth-6.5/avr8/devices/atmega88a/words/no-wdt.asm create mode 100644 amforth-6.5/avr8/devices/atmega88a/words/sleep.asm (limited to 'amforth-6.5/avr8/devices/atmega88a') diff --git a/amforth-6.5/avr8/devices/atmega88a/atmega88a.frt b/amforth-6.5/avr8/devices/atmega88a/atmega88a.frt new file mode 100644 index 0000000..657734d --- /dev/null +++ b/amforth-6.5/avr8/devices/atmega88a/atmega88a.frt @@ -0,0 +1,297 @@ +\ Partname: ATmega88A +\ generated automatically + +\ USART0 +&198 constant UDR0 \ USART I/O Data Register +&192 constant UCSR0A \ USART Control and Status Register A + $80 constant UCSR0A_RXC0 \ USART Receive Complete + $40 constant UCSR0A_TXC0 \ USART Transmitt Complete + $20 constant UCSR0A_UDRE0 \ USART Data Register Empty + $10 constant UCSR0A_FE0 \ Framing Error + $08 constant UCSR0A_DOR0 \ Data overRun + $04 constant UCSR0A_UPE0 \ Parity Error + $02 constant UCSR0A_U2X0 \ Double the USART transmission speed + $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode +&193 constant UCSR0B \ USART Control and Status Register B + $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable + $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable + $20 constant UCSR0B_UDRIE0 \ USART Data register Empty Interrupt Enable + $10 constant UCSR0B_RXEN0 \ Receiver Enable + $08 constant UCSR0B_TXEN0 \ Transmitter Enable + $04 constant UCSR0B_UCSZ02 \ Character Size + $02 constant UCSR0B_RXB80 \ Receive Data Bit 8 + $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8 +&194 constant UCSR0C \ USART Control and Status Register C + $C0 constant UCSR0C_UMSEL0 \ USART Mode Select + $30 constant UCSR0C_UPM0 \ Parity Mode Bits + $08 constant UCSR0C_USBS0 \ Stop Bit Select + $06 constant UCSR0C_UCSZ0 \ Character Size + $01 constant UCSR0C_UCPOL0 \ Clock Polarity +&196 constant UBRR0 \ USART Baud Rate Register Bytes +\ TWI +&189 constant TWAMR \ TWI (Slave) Address Mask Register + $FE constant TWAMR_TWAM \ +&184 constant TWBR \ TWI Bit Rate register +&188 constant TWCR \ TWI Control Register + $80 constant TWCR_TWINT \ TWI Interrupt Flag + $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit + $20 constant TWCR_TWSTA \ TWI Start Condition Bit + $10 constant TWCR_TWSTO \ TWI Stop Condition Bit + $08 constant TWCR_TWWC \ TWI Write Collition Flag + $04 constant TWCR_TWEN \ TWI Enable Bit + $01 constant TWCR_TWIE \ TWI Interrupt Enable +&185 constant TWSR \ TWI Status Register + $F8 constant TWSR_TWS \ TWI Status + $03 constant TWSR_TWPS \ TWI Prescaler +&187 constant TWDR \ TWI Data register +&186 constant TWAR \ TWI (Slave) Address register + $FE constant TWAR_TWA \ TWI (Slave) Address register Bits + $01 constant TWAR_TWGCE \ TWI General Call Recognition Enable Bit +\ TIMER_COUNTER_1 +&111 constant TIMSK1 \ Timer/Counter Interrupt Mask Register + $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable + $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output CompareB Match Interrupt Enable + $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output CompareA Match Interrupt Enable + $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable +&54 constant TIFR1 \ Timer/Counter Interrupt Flag register + $20 constant TIFR1_ICF1 \ Input Capture Flag 1 + $04 constant TIFR1_OCF1B \ Output Compare Flag 1B + $02 constant TIFR1_OCF1A \ Output Compare Flag 1A + $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag +&128 constant TCCR1A \ Timer/Counter1 Control Register A + $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits + $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits + $03 constant TCCR1A_WGM1 \ Waveform Generation Mode +&129 constant TCCR1B \ Timer/Counter1 Control Register B + $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler + $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select + $18 constant TCCR1B_WGM1 \ Waveform Generation Mode + $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1 +&130 constant TCCR1C \ Timer/Counter1 Control Register C + $80 constant TCCR1C_FOC1A \ + $40 constant TCCR1C_FOC1B \ +&132 constant TCNT1 \ Timer/Counter1 Bytes +&136 constant OCR1A \ Timer/Counter1 Output Compare Register Bytes +&138 constant OCR1B \ Timer/Counter1 Output Compare Register Bytes +&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes +&67 constant GTCCR \ General Timer/Counter Control Register + $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode + $01 constant GTCCR_PSRSYNC \ Prescaler Reset Timer/Counter1 and Timer/Counter0 +\ TIMER_COUNTER_2 +&112 constant TIMSK2 \ Timer/Counter Interrupt Mask register + $04 constant TIMSK2_OCIE2B \ Timer/Counter2 Output Compare Match B Interrupt Enable + $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match A Interrupt Enable + $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable +&55 constant TIFR2 \ Timer/Counter Interrupt Flag Register + $04 constant TIFR2_OCF2B \ Output Compare Flag 2B + $02 constant TIFR2_OCF2A \ Output Compare Flag 2A + $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag +&176 constant TCCR2A \ Timer/Counter2 Control Register A + $C0 constant TCCR2A_COM2A \ Compare Output Mode bits + $30 constant TCCR2A_COM2B \ Compare Output Mode bits + $03 constant TCCR2A_WGM2 \ Waveform Genration Mode +&177 constant TCCR2B \ Timer/Counter2 Control Register B + $80 constant TCCR2B_FOC2A \ Force Output Compare A + $40 constant TCCR2B_FOC2B \ Force Output Compare B + $08 constant TCCR2B_WGM22 \ Waveform Generation Mode + $07 constant TCCR2B_CS2 \ Clock Select bits +&178 constant TCNT2 \ Timer/Counter2 +&180 constant OCR2B \ Timer/Counter2 Output Compare Register B +&179 constant OCR2A \ Timer/Counter2 Output Compare Register A +&182 constant ASSR \ Asynchronous Status Register + $40 constant ASSR_EXCLK \ Enable External Clock Input + $20 constant ASSR_AS2 \ Asynchronous Timer/Counter2 + $10 constant ASSR_TCN2UB \ Timer/Counter2 Update Busy + $08 constant ASSR_OCR2AUB \ Output Compare Register2 Update Busy + $04 constant ASSR_OCR2BUB \ Output Compare Register 2 Update Busy + $02 constant ASSR_TCR2AUB \ Timer/Counter Control Register2 Update Busy + $01 constant ASSR_TCR2BUB \ Timer/Counter Control Register2 Update Busy +\ AD_CONVERTER +&124 constant ADMUX \ The ADC multiplexer Selection Register + $C0 constant ADMUX_REFS \ Reference Selection Bits + $20 constant ADMUX_ADLAR \ Left Adjust Result + $0F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits +&120 constant ADC \ ADC Data Register Bytes +&122 constant ADCSRA \ The ADC Control and Status register A + $80 constant ADCSRA_ADEN \ ADC Enable + $40 constant ADCSRA_ADSC \ ADC Start Conversion + $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable + $10 constant ADCSRA_ADIF \ ADC Interrupt Flag + $08 constant ADCSRA_ADIE \ ADC Interrupt Enable + $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits +&123 constant ADCSRB \ The ADC Control and Status register B + $40 constant ADCSRB_ACME \ + $07 constant ADCSRB_ADTS \ ADC Auto Trigger Source bits +&126 constant DIDR0 \ Digital Input Disable Register + $20 constant DIDR0_ADC5D \ + $10 constant DIDR0_ADC4D \ + $08 constant DIDR0_ADC3D \ + $04 constant DIDR0_ADC2D \ + $02 constant DIDR0_ADC1D \ + $01 constant DIDR0_ADC0D \ +\ ANALOG_COMPARATOR +&80 constant ACSR \ Analog Comparator Control And Status Register + $80 constant ACSR_ACD \ Analog Comparator Disable + $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select + $20 constant ACSR_ACO \ Analog Compare Output + $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag + $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable + $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable + $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits +&127 constant DIDR1 \ Digital Input Disable Register 1 + $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable + $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable +\ PORTB +&37 constant PORTB \ Port B Data Register +&36 constant DDRB \ Port B Data Direction Register +&35 constant PINB \ Port B Input Pins +\ PORTC +&40 constant PORTC \ Port C Data Register +&39 constant DDRC \ Port C Data Direction Register +&38 constant PINC \ Port C Input Pins +\ PORTD +&43 constant PORTD \ Port D Data Register +&42 constant DDRD \ Port D Data Direction Register +&41 constant PIND \ Port D Input Pins +\ TIMER_COUNTER_0 +&72 constant OCR0B \ Timer/Counter0 Output Compare Register +&71 constant OCR0A \ Timer/Counter0 Output Compare Register +&70 constant TCNT0 \ Timer/Counter0 +&69 constant TCCR0B \ Timer/Counter Control Register B + $80 constant TCCR0B_FOC0A \ Force Output Compare A + $40 constant TCCR0B_FOC0B \ Force Output Compare B + $08 constant TCCR0B_WGM02 \ + $07 constant TCCR0B_CS0 \ Clock Select +&68 constant TCCR0A \ Timer/Counter Control Register A + $C0 constant TCCR0A_COM0A \ Compare Output Mode, Phase Correct PWM Mode + $30 constant TCCR0A_COM0B \ Compare Output Mode, Fast PWm + $03 constant TCCR0A_WGM0 \ Waveform Generation Mode +&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register + $04 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare Match B Interrupt Enable + $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match A Interrupt Enable + $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable +&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register + $04 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare Flag 0B + $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0A + $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag +\ EXTERNAL_INTERRUPT +&105 constant EICRA \ External Interrupt Control Register + $0C constant EICRA_ISC1 \ External Interrupt Sense Control 1 Bits + $03 constant EICRA_ISC0 \ External Interrupt Sense Control 0 Bits +&61 constant EIMSK \ External Interrupt Mask Register + $03 constant EIMSK_INT \ External Interrupt Request 1 Enable +&60 constant EIFR \ External Interrupt Flag Register + $03 constant EIFR_INTF \ External Interrupt Flags +&104 constant PCICR \ Pin Change Interrupt Control Register + $07 constant PCICR_PCIE \ Pin Change Interrupt Enables +&109 constant PCMSK2 \ Pin Change Mask Register 2 + $FF constant PCMSK2_PCINT \ Pin Change Enable Masks +&108 constant PCMSK1 \ Pin Change Mask Register 1 + $7F constant PCMSK1_PCINT \ Pin Change Enable Masks +&107 constant PCMSK0 \ Pin Change Mask Register 0 + $FF constant PCMSK0_PCINT \ Pin Change Enable Masks +&59 constant PCIFR \ Pin Change Interrupt Flag Register + $07 constant PCIFR_PCIF \ Pin Change Interrupt Flags +\ SPI +&78 constant SPDR \ SPI Data Register +&77 constant SPSR \ SPI Status Register + $80 constant SPSR_SPIF \ SPI Interrupt Flag + $40 constant SPSR_WCOL \ Write Collision Flag + $01 constant SPSR_SPI2X \ Double SPI Speed Bit +&76 constant SPCR \ SPI Control Register + $80 constant SPCR_SPIE \ SPI Interrupt Enable + $40 constant SPCR_SPE \ SPI Enable + $20 constant SPCR_DORD \ Data Order + $10 constant SPCR_MSTR \ Master/Slave Select + $08 constant SPCR_CPOL \ Clock polarity + $04 constant SPCR_CPHA \ Clock Phase + $03 constant SPCR_SPR \ SPI Clock Rate Selects +\ WATCHDOG +&96 constant WDTCSR \ Watchdog Timer Control Register + $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Flag + $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Enable + $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits + $10 constant WDTCSR_WDCE \ Watchdog Change Enable + $08 constant WDTCSR_WDE \ Watch Dog Enable +\ EEPROM +&65 constant EEAR \ EEPROM Address Register Bytes +&64 constant EEDR \ EEPROM Data Register +&63 constant EECR \ EEPROM Control Register + $30 constant EECR_EEPM \ EEPROM Programming Mode Bits + $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable + $04 constant EECR_EEMPE \ EEPROM Master Write Enable + $02 constant EECR_EEPE \ EEPROM Write Enable + $01 constant EECR_EERE \ EEPROM Read Enable +\ CPU +&100 constant PRR \ Power Reduction Register + $80 constant PRR_PRTWI \ Power Reduction TWI + $40 constant PRR_PRTIM2 \ Power Reduction Timer/Counter2 + $20 constant PRR_PRTIM0 \ Power Reduction Timer/Counter0 + $08 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1 + $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface + $02 constant PRR_PRUSART0 \ Power Reduction USART + $01 constant PRR_PRADC \ Power Reduction ADC +&102 constant OSCCAL \ Oscillator Calibration Value +&97 constant CLKPR \ Clock Prescale Register + $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable + $0F constant CLKPR_CLKPS \ Clock Prescaler Select Bits +&95 constant SREG \ Status Register + $80 constant SREG_I \ Global Interrupt Enable + $40 constant SREG_T \ Bit Copy Storage + $20 constant SREG_H \ Half Carry Flag + $10 constant SREG_S \ Sign Bit + $08 constant SREG_V \ Two's Complement Overflow Flag + $04 constant SREG_N \ Negative Flag + $02 constant SREG_Z \ Zero Flag + $01 constant SREG_C \ Carry Flag +&93 constant SP \ Stack Pointer +&87 constant SPMCSR \ Store Program Memory Control and Status Register + $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable + $40 constant SPMCSR_RWWSB \ Read-While-Write Section Busy + $10 constant SPMCSR_RWWSRE \ Read-While-Write section read enable + $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set + $04 constant SPMCSR_PGWRT \ Page Write + $02 constant SPMCSR_PGERS \ Page Erase + $01 constant SPMCSR_SELFPRGEN \ Self Programming Enable +&85 constant MCUCR \ MCU Control Register + $10 constant MCUCR_PUD \ + $02 constant MCUCR_IVSEL \ + $01 constant MCUCR_IVCE \ +&84 constant MCUSR \ MCU Status Register + $08 constant MCUSR_WDRF \ Watchdog Reset Flag + $04 constant MCUSR_BORF \ Brown-out Reset Flag + $02 constant MCUSR_EXTRF \ External Reset Flag + $01 constant MCUSR_PORF \ Power-on reset flag +&83 constant SMCR \ Sleep Mode Control Register + $0E constant SMCR_SM \ Sleep Mode Select Bits + $01 constant SMCR_SE \ Sleep Enable +&75 constant GPIOR2 \ General Purpose I/O Register 2 +&74 constant GPIOR1 \ General Purpose I/O Register 1 +&62 constant GPIOR0 \ General Purpose I/O Register 0 + +\ Interrupts +&1 constant INT0Addr \ External Interrupt Request 0 +&2 constant INT1Addr \ External Interrupt Request 1 +&3 constant PCINT0Addr \ Pin Change Interrupt Request 0 +&4 constant PCINT1Addr \ Pin Change Interrupt Request 0 +&5 constant PCINT2Addr \ Pin Change Interrupt Request 1 +&6 constant WDTAddr \ Watchdog Time-out Interrupt +&7 constant TIMER2_COMPAAddr \ Timer/Counter2 Compare Match A +&8 constant TIMER2_COMPBAddr \ Timer/Counter2 Compare Match A +&9 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow +&10 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event +&11 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A +&12 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B +&13 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow +&14 constant TIMER0_COMPAAddr \ TimerCounter0 Compare Match A +&15 constant TIMER0_COMPBAddr \ TimerCounter0 Compare Match B +&16 constant TIMER0_OVFAddr \ Timer/Couner0 Overflow +&17 constant SPI__STCAddr \ SPI Serial Transfer Complete +&18 constant USART__RXAddr \ USART Rx Complete +&19 constant USART__UDREAddr \ USART, Data Register Empty +&20 constant USART__TXAddr \ USART Tx Complete +&21 constant ADCAddr \ ADC Conversion Complete +&22 constant EE_READYAddr \ EEPROM Ready +&23 constant ANALOG_COMPAddr \ Analog Comparator +&24 constant TWIAddr \ Two-wire Serial Interface +&25 constant SPM_ReadyAddr \ Store Program Memory Read diff --git a/amforth-6.5/avr8/devices/atmega88a/device.asm b/amforth-6.5/avr8/devices/atmega88a/device.asm new file mode 100644 index 0000000..1195a9c --- /dev/null +++ b/amforth-6.5/avr8/devices/atmega88a/device.asm @@ -0,0 +1,107 @@ +; Partname: ATmega88A +; generated automatically, do not edit + +.nolist + .include "m88Adef.inc" +.list + +.equ ramstart = 256 +.equ CELLSIZE = 2 +.macro readflashcell + lsl zl + rol zh + lpm @0, Z+ + lpm @1, Z+ +.endmacro +.macro writeflashcell + lsl zl + rol zh +.endmacro +.set WANT_USART0 = 0 +.set WANT_TWI = 0 +.set WANT_TIMER_COUNTER_1 = 0 +.set WANT_TIMER_COUNTER_2 = 0 +.set WANT_AD_CONVERTER = 0 +.set WANT_ANALOG_COMPARATOR = 0 +.set WANT_PORTB = 0 +.set WANT_PORTC = 0 +.set WANT_PORTD = 0 +.set WANT_TIMER_COUNTER_0 = 0 +.set WANT_EXTERNAL_INTERRUPT = 0 +.set WANT_SPI = 0 +.set WANT_WATCHDOG = 0 +.set WANT_EEPROM = 0 +.set WANT_CPU = 0 +.equ intvecsize = 1 ; please verify; flash size: 8192 bytes +.equ pclen = 2 ; please verify +.overlap +.org 1 + rcall isr ; External Interrupt Request 0 +.org 2 + rcall isr ; External Interrupt Request 1 +.org 3 + rcall isr ; Pin Change Interrupt Request 0 +.org 4 + rcall isr ; Pin Change Interrupt Request 0 +.org 5 + rcall isr ; Pin Change Interrupt Request 1 +.org 6 + rcall isr ; Watchdog Time-out Interrupt +.org 7 + rcall isr ; Timer/Counter2 Compare Match A +.org 8 + rcall isr ; Timer/Counter2 Compare Match A +.org 9 + rcall isr ; Timer/Counter2 Overflow +.org 10 + rcall isr ; Timer/Counter1 Capture Event +.org 11 + rcall isr ; Timer/Counter1 Compare Match A +.org 12 + rcall isr ; Timer/Counter1 Compare Match B +.org 13 + rcall isr ; Timer/Counter1 Overflow +.org 14 + rcall isr ; TimerCounter0 Compare Match A +.org 15 + rcall isr ; TimerCounter0 Compare Match B +.org 16 + rcall isr ; Timer/Couner0 Overflow +.org 17 + rcall isr ; SPI Serial Transfer Complete +.org 18 + rcall isr ; USART Rx Complete +.org 19 + rcall isr ; USART, Data Register Empty +.org 20 + rcall isr ; USART Tx Complete +.org 21 + rcall isr ; ADC Conversion Complete +.org 22 + rcall isr ; EEPROM Ready +.org 23 + rcall isr ; Analog Comparator +.org 24 + rcall isr ; Two-wire Serial Interface +.org 25 + rcall isr ; Store Program Memory Read +.equ INTVECTORS = 26 +.nooverlap + +; compatability layer (maybe empty) +.equ SPMEN = SELFPRGEN + +; controller data area, environment query mcu-info +mcu_info: +mcu_ramsize: + .dw 1024 +mcu_eepromsize: + .dw 512 +mcu_maxdp: + .dw 6144 +mcu_numints: + .dw 26 +mcu_name: + .dw 9 + .db "ATmega88A",0 +.set codestart=pc diff --git a/amforth-6.5/avr8/devices/atmega88a/device.inc b/amforth-6.5/avr8/devices/atmega88a/device.inc new file mode 100644 index 0000000..446e57e --- /dev/null +++ b/amforth-6.5/avr8/devices/atmega88a/device.inc @@ -0,0 +1,996 @@ +; Partname: ATmega88A +; generated automatically, no not edit + +.if WANT_USART0 == 1 +; ( -- addr ) System Constant +; R( -- ) +; USART I/O Data Register +VE_UDR0: + .dw $ff04 + .db "UDR0" + .dw VE_HEAD + .set VE_HEAD=VE_UDR0 +XT_UDR0: + .dw PFA_DOVARIABLE +PFA_UDR0: + .dw 198 +; ( -- addr ) System Constant +; R( -- ) +; USART Control and Status Register A +VE_UCSR0A: + .dw $ff06 + .db "UCSR0A" + .dw VE_HEAD + .set VE_HEAD=VE_UCSR0A +XT_UCSR0A: + .dw PFA_DOVARIABLE +PFA_UCSR0A: + .dw 192 +; ( -- addr ) System Constant +; R( -- ) +; USART Control and Status Register B +VE_UCSR0B: + .dw $ff06 + .db "UCSR0B" + .dw VE_HEAD + .set VE_HEAD=VE_UCSR0B +XT_UCSR0B: + .dw PFA_DOVARIABLE +PFA_UCSR0B: + .dw 193 +; ( -- addr ) System Constant +; R( -- ) +; USART Control and Status Register C +VE_UCSR0C: + .dw $ff06 + .db "UCSR0C" + .dw VE_HEAD + .set VE_HEAD=VE_UCSR0C +XT_UCSR0C: + .dw PFA_DOVARIABLE +PFA_UCSR0C: + .dw 194 +; ( -- addr ) System Constant +; R( -- ) +; USART Baud Rate Register Bytes +VE_UBRR0: + .dw $ff05 + .db "UBRR0",0 + .dw VE_HEAD + .set VE_HEAD=VE_UBRR0 +XT_UBRR0: + .dw PFA_DOVARIABLE +PFA_UBRR0: + .dw 196 + +.endif +.if WANT_TWI == 1 +; ( -- addr ) System Constant +; R( -- ) +; TWI (Slave) Address Mask Register +VE_TWAMR: + .dw $ff05 + .db "TWAMR",0 + .dw VE_HEAD + .set VE_HEAD=VE_TWAMR +XT_TWAMR: + .dw PFA_DOVARIABLE +PFA_TWAMR: + .dw 189 +; ( -- addr ) System Constant +; R( -- ) +; TWI Bit Rate register +VE_TWBR: + .dw $ff04 + .db "TWBR" + .dw VE_HEAD + .set VE_HEAD=VE_TWBR +XT_TWBR: + .dw PFA_DOVARIABLE +PFA_TWBR: + .dw 184 +; ( -- addr ) System Constant +; R( -- ) +; TWI Control Register +VE_TWCR: + .dw $ff04 + .db "TWCR" + .dw VE_HEAD + .set VE_HEAD=VE_TWCR +XT_TWCR: + .dw PFA_DOVARIABLE +PFA_TWCR: + .dw 188 +; ( -- addr ) System Constant +; R( -- ) +; TWI Status Register +VE_TWSR: + .dw $ff04 + .db "TWSR" + .dw VE_HEAD + .set VE_HEAD=VE_TWSR +XT_TWSR: + .dw PFA_DOVARIABLE +PFA_TWSR: + .dw 185 +; ( -- addr ) System Constant +; R( -- ) +; TWI Data register +VE_TWDR: + .dw $ff04 + .db "TWDR" + .dw VE_HEAD + .set VE_HEAD=VE_TWDR +XT_TWDR: + .dw PFA_DOVARIABLE +PFA_TWDR: + .dw 187 +; ( -- addr ) System Constant +; R( -- ) +; TWI (Slave) Address register +VE_TWAR: + .dw $ff04 + .db "TWAR" + .dw VE_HEAD + .set VE_HEAD=VE_TWAR +XT_TWAR: + .dw PFA_DOVARIABLE +PFA_TWAR: + .dw 186 + +.endif +.if WANT_TIMER_COUNTER_1 == 1 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter Interrupt Mask Register +VE_TIMSK1: + .dw $ff06 + .db "TIMSK1" + .dw VE_HEAD + .set VE_HEAD=VE_TIMSK1 +XT_TIMSK1: + .dw PFA_DOVARIABLE +PFA_TIMSK1: + .dw 111 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter Interrupt Flag register +VE_TIFR1: + .dw $ff05 + .db "TIFR1",0 + .dw VE_HEAD + .set VE_HEAD=VE_TIFR1 +XT_TIFR1: + .dw PFA_DOVARIABLE +PFA_TIFR1: + .dw 54 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter1 Control Register A +VE_TCCR1A: + .dw $ff06 + .db "TCCR1A" + .dw VE_HEAD + .set VE_HEAD=VE_TCCR1A +XT_TCCR1A: + .dw PFA_DOVARIABLE +PFA_TCCR1A: + .dw 128 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter1 Control Register B +VE_TCCR1B: + .dw $ff06 + .db "TCCR1B" + .dw VE_HEAD + .set VE_HEAD=VE_TCCR1B +XT_TCCR1B: + .dw PFA_DOVARIABLE +PFA_TCCR1B: + .dw 129 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter1 Control Register C +VE_TCCR1C: + .dw $ff06 + .db "TCCR1C" + .dw VE_HEAD + .set VE_HEAD=VE_TCCR1C +XT_TCCR1C: + .dw PFA_DOVARIABLE +PFA_TCCR1C: + .dw 130 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter1 Bytes +VE_TCNT1: + .dw $ff05 + .db "TCNT1",0 + .dw VE_HEAD + .set VE_HEAD=VE_TCNT1 +XT_TCNT1: + .dw PFA_DOVARIABLE +PFA_TCNT1: + .dw 132 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter1 Output Compare Register Bytes +VE_OCR1A: + .dw $ff05 + .db "OCR1A",0 + .dw VE_HEAD + .set VE_HEAD=VE_OCR1A +XT_OCR1A: + .dw PFA_DOVARIABLE +PFA_OCR1A: + .dw 136 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter1 Output Compare Register Bytes +VE_OCR1B: + .dw $ff05 + .db "OCR1B",0 + .dw VE_HEAD + .set VE_HEAD=VE_OCR1B +XT_OCR1B: + .dw PFA_DOVARIABLE +PFA_OCR1B: + .dw 138 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter1 Input Capture Register Bytes +VE_ICR1: + .dw $ff04 + .db "ICR1" + .dw VE_HEAD + .set VE_HEAD=VE_ICR1 +XT_ICR1: + .dw PFA_DOVARIABLE +PFA_ICR1: + .dw 134 +; ( -- addr ) System Constant +; R( -- ) +; General Timer/Counter Control Register +VE_GTCCR: + .dw $ff05 + .db "GTCCR",0 + .dw VE_HEAD + .set VE_HEAD=VE_GTCCR +XT_GTCCR: + .dw PFA_DOVARIABLE +PFA_GTCCR: + .dw 67 + +.endif +.if WANT_TIMER_COUNTER_2 == 1 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter Interrupt Mask register +VE_TIMSK2: + .dw $ff06 + .db "TIMSK2" + .dw VE_HEAD + .set VE_HEAD=VE_TIMSK2 +XT_TIMSK2: + .dw PFA_DOVARIABLE +PFA_TIMSK2: + .dw 112 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter Interrupt Flag Register +VE_TIFR2: + .dw $ff05 + .db "TIFR2",0 + .dw VE_HEAD + .set VE_HEAD=VE_TIFR2 +XT_TIFR2: + .dw PFA_DOVARIABLE +PFA_TIFR2: + .dw 55 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter2 Control Register A +VE_TCCR2A: + .dw $ff06 + .db "TCCR2A" + .dw VE_HEAD + .set VE_HEAD=VE_TCCR2A +XT_TCCR2A: + .dw PFA_DOVARIABLE +PFA_TCCR2A: + .dw 176 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter2 Control Register B +VE_TCCR2B: + .dw $ff06 + .db "TCCR2B" + .dw VE_HEAD + .set VE_HEAD=VE_TCCR2B +XT_TCCR2B: + .dw PFA_DOVARIABLE +PFA_TCCR2B: + .dw 177 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter2 +VE_TCNT2: + .dw $ff05 + .db "TCNT2",0 + .dw VE_HEAD + .set VE_HEAD=VE_TCNT2 +XT_TCNT2: + .dw PFA_DOVARIABLE +PFA_TCNT2: + .dw 178 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter2 Output Compare Register B +VE_OCR2B: + .dw $ff05 + .db "OCR2B",0 + .dw VE_HEAD + .set VE_HEAD=VE_OCR2B +XT_OCR2B: + .dw PFA_DOVARIABLE +PFA_OCR2B: + .dw 180 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter2 Output Compare Register A +VE_OCR2A: + .dw $ff05 + .db "OCR2A",0 + .dw VE_HEAD + .set VE_HEAD=VE_OCR2A +XT_OCR2A: + .dw PFA_DOVARIABLE +PFA_OCR2A: + .dw 179 +; ( -- addr ) System Constant +; R( -- ) +; Asynchronous Status Register +VE_ASSR: + .dw $ff04 + .db "ASSR" + .dw VE_HEAD + .set VE_HEAD=VE_ASSR +XT_ASSR: + .dw PFA_DOVARIABLE +PFA_ASSR: + .dw 182 + +.endif +.if WANT_AD_CONVERTER == 1 +; ( -- addr ) System Constant +; R( -- ) +; The ADC multiplexer Selection Register +VE_ADMUX: + .dw $ff05 + .db "ADMUX",0 + .dw VE_HEAD + .set VE_HEAD=VE_ADMUX +XT_ADMUX: + .dw PFA_DOVARIABLE +PFA_ADMUX: + .dw 124 +; ( -- addr ) System Constant +; R( -- ) +; ADC Data Register Bytes +VE_ADC: + .dw $ff03 + .db "ADC",0 + .dw VE_HEAD + .set VE_HEAD=VE_ADC +XT_ADC: + .dw PFA_DOVARIABLE +PFA_ADC: + .dw 120 +; ( -- addr ) System Constant +; R( -- ) +; The ADC Control and Status register A +VE_ADCSRA: + .dw $ff06 + .db "ADCSRA" + .dw VE_HEAD + .set VE_HEAD=VE_ADCSRA +XT_ADCSRA: + .dw PFA_DOVARIABLE +PFA_ADCSRA: + .dw 122 +; ( -- addr ) System Constant +; R( -- ) +; The ADC Control and Status register B +VE_ADCSRB: + .dw $ff06 + .db "ADCSRB" + .dw VE_HEAD + .set VE_HEAD=VE_ADCSRB +XT_ADCSRB: + .dw PFA_DOVARIABLE +PFA_ADCSRB: + .dw 123 +; ( -- addr ) System Constant +; R( -- ) +; Digital Input Disable Register +VE_DIDR0: + .dw $ff05 + .db "DIDR0",0 + .dw VE_HEAD + .set VE_HEAD=VE_DIDR0 +XT_DIDR0: + .dw PFA_DOVARIABLE +PFA_DIDR0: + .dw 126 + +.endif +.if WANT_ANALOG_COMPARATOR == 1 +; ( -- addr ) System Constant +; R( -- ) +; Analog Comparator Control And Status Register +VE_ACSR: + .dw $ff04 + .db "ACSR" + .dw VE_HEAD + .set VE_HEAD=VE_ACSR +XT_ACSR: + .dw PFA_DOVARIABLE +PFA_ACSR: + .dw 80 +; ( -- addr ) System Constant +; R( -- ) +; Digital Input Disable Register 1 +VE_DIDR1: + .dw $ff05 + .db "DIDR1",0 + .dw VE_HEAD + .set VE_HEAD=VE_DIDR1 +XT_DIDR1: + .dw PFA_DOVARIABLE +PFA_DIDR1: + .dw 127 + +.endif +.if WANT_PORTB == 1 +; ( -- addr ) System Constant +; R( -- ) +; Port B Data Register +VE_PORTB: + .dw $ff05 + .db "PORTB",0 + .dw VE_HEAD + .set VE_HEAD=VE_PORTB +XT_PORTB: + .dw PFA_DOVARIABLE +PFA_PORTB: + .dw 37 +; ( -- addr ) System Constant +; R( -- ) +; Port B Data Direction Register +VE_DDRB: + .dw $ff04 + .db "DDRB" + .dw VE_HEAD + .set VE_HEAD=VE_DDRB +XT_DDRB: + .dw PFA_DOVARIABLE +PFA_DDRB: + .dw 36 +; ( -- addr ) System Constant +; R( -- ) +; Port B Input Pins +VE_PINB: + .dw $ff04 + .db "PINB" + .dw VE_HEAD + .set VE_HEAD=VE_PINB +XT_PINB: + .dw PFA_DOVARIABLE +PFA_PINB: + .dw 35 + +.endif +.if WANT_PORTC == 1 +; ( -- addr ) System Constant +; R( -- ) +; Port C Data Register +VE_PORTC: + .dw $ff05 + .db "PORTC",0 + .dw VE_HEAD + .set VE_HEAD=VE_PORTC +XT_PORTC: + .dw PFA_DOVARIABLE +PFA_PORTC: + .dw 40 +; ( -- addr ) System Constant +; R( -- ) +; Port C Data Direction Register +VE_DDRC: + .dw $ff04 + .db "DDRC" + .dw VE_HEAD + .set VE_HEAD=VE_DDRC +XT_DDRC: + .dw PFA_DOVARIABLE +PFA_DDRC: + .dw 39 +; ( -- addr ) System Constant +; R( -- ) +; Port C Input Pins +VE_PINC: + .dw $ff04 + .db "PINC" + .dw VE_HEAD + .set VE_HEAD=VE_PINC +XT_PINC: + .dw PFA_DOVARIABLE +PFA_PINC: + .dw 38 + +.endif +.if WANT_PORTD == 1 +; ( -- addr ) System Constant +; R( -- ) +; Port D Data Register +VE_PORTD: + .dw $ff05 + .db "PORTD",0 + .dw VE_HEAD + .set VE_HEAD=VE_PORTD +XT_PORTD: + .dw PFA_DOVARIABLE +PFA_PORTD: + .dw 43 +; ( -- addr ) System Constant +; R( -- ) +; Port D Data Direction Register +VE_DDRD: + .dw $ff04 + .db "DDRD" + .dw VE_HEAD + .set VE_HEAD=VE_DDRD +XT_DDRD: + .dw PFA_DOVARIABLE +PFA_DDRD: + .dw 42 +; ( -- addr ) System Constant +; R( -- ) +; Port D Input Pins +VE_PIND: + .dw $ff04 + .db "PIND" + .dw VE_HEAD + .set VE_HEAD=VE_PIND +XT_PIND: + .dw PFA_DOVARIABLE +PFA_PIND: + .dw 41 + +.endif +.if WANT_TIMER_COUNTER_0 == 1 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter0 Output Compare Register +VE_OCR0B: + .dw $ff05 + .db "OCR0B",0 + .dw VE_HEAD + .set VE_HEAD=VE_OCR0B +XT_OCR0B: + .dw PFA_DOVARIABLE +PFA_OCR0B: + .dw 72 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter0 Output Compare Register +VE_OCR0A: + .dw $ff05 + .db "OCR0A",0 + .dw VE_HEAD + .set VE_HEAD=VE_OCR0A +XT_OCR0A: + .dw PFA_DOVARIABLE +PFA_OCR0A: + .dw 71 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter0 +VE_TCNT0: + .dw $ff05 + .db "TCNT0",0 + .dw VE_HEAD + .set VE_HEAD=VE_TCNT0 +XT_TCNT0: + .dw PFA_DOVARIABLE +PFA_TCNT0: + .dw 70 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter Control Register B +VE_TCCR0B: + .dw $ff06 + .db "TCCR0B" + .dw VE_HEAD + .set VE_HEAD=VE_TCCR0B +XT_TCCR0B: + .dw PFA_DOVARIABLE +PFA_TCCR0B: + .dw 69 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter Control Register A +VE_TCCR0A: + .dw $ff06 + .db "TCCR0A" + .dw VE_HEAD + .set VE_HEAD=VE_TCCR0A +XT_TCCR0A: + .dw PFA_DOVARIABLE +PFA_TCCR0A: + .dw 68 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter0 Interrupt Mask Register +VE_TIMSK0: + .dw $ff06 + .db "TIMSK0" + .dw VE_HEAD + .set VE_HEAD=VE_TIMSK0 +XT_TIMSK0: + .dw PFA_DOVARIABLE +PFA_TIMSK0: + .dw 110 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter0 Interrupt Flag register +VE_TIFR0: + .dw $ff05 + .db "TIFR0",0 + .dw VE_HEAD + .set VE_HEAD=VE_TIFR0 +XT_TIFR0: + .dw PFA_DOVARIABLE +PFA_TIFR0: + .dw 53 + +.endif +.if WANT_EXTERNAL_INTERRUPT == 1 +; ( -- addr ) System Constant +; R( -- ) +; External Interrupt Control Register +VE_EICRA: + .dw $ff05 + .db "EICRA",0 + .dw VE_HEAD + .set VE_HEAD=VE_EICRA +XT_EICRA: + .dw PFA_DOVARIABLE +PFA_EICRA: + .dw 105 +; ( -- addr ) System Constant +; R( -- ) +; External Interrupt Mask Register +VE_EIMSK: + .dw $ff05 + .db "EIMSK",0 + .dw VE_HEAD + .set VE_HEAD=VE_EIMSK +XT_EIMSK: + .dw PFA_DOVARIABLE +PFA_EIMSK: + .dw 61 +; ( -- addr ) System Constant +; R( -- ) +; External Interrupt Flag Register +VE_EIFR: + .dw $ff04 + .db "EIFR" + .dw VE_HEAD + .set VE_HEAD=VE_EIFR +XT_EIFR: + .dw PFA_DOVARIABLE +PFA_EIFR: + .dw 60 +; ( -- addr ) System Constant +; R( -- ) +; Pin Change Interrupt Control Register +VE_PCICR: + .dw $ff05 + .db "PCICR",0 + .dw VE_HEAD + .set VE_HEAD=VE_PCICR +XT_PCICR: + .dw PFA_DOVARIABLE +PFA_PCICR: + .dw 104 +; ( -- addr ) System Constant +; R( -- ) +; Pin Change Mask Register 2 +VE_PCMSK2: + .dw $ff06 + .db "PCMSK2" + .dw VE_HEAD + .set VE_HEAD=VE_PCMSK2 +XT_PCMSK2: + .dw PFA_DOVARIABLE +PFA_PCMSK2: + .dw 109 +; ( -- addr ) System Constant +; R( -- ) +; Pin Change Mask Register 1 +VE_PCMSK1: + .dw $ff06 + .db "PCMSK1" + .dw VE_HEAD + .set VE_HEAD=VE_PCMSK1 +XT_PCMSK1: + .dw PFA_DOVARIABLE +PFA_PCMSK1: + .dw 108 +; ( -- addr ) System Constant +; R( -- ) +; Pin Change Mask Register 0 +VE_PCMSK0: + .dw $ff06 + .db "PCMSK0" + .dw VE_HEAD + .set VE_HEAD=VE_PCMSK0 +XT_PCMSK0: + .dw PFA_DOVARIABLE +PFA_PCMSK0: + .dw 107 +; ( -- addr ) System Constant +; R( -- ) +; Pin Change Interrupt Flag Register +VE_PCIFR: + .dw $ff05 + .db "PCIFR",0 + .dw VE_HEAD + .set VE_HEAD=VE_PCIFR +XT_PCIFR: + .dw PFA_DOVARIABLE +PFA_PCIFR: + .dw 59 + +.endif +.if WANT_SPI == 1 +; ( -- addr ) System Constant +; R( -- ) +; SPI Data Register +VE_SPDR: + .dw $ff04 + .db "SPDR" + .dw VE_HEAD + .set VE_HEAD=VE_SPDR +XT_SPDR: + .dw PFA_DOVARIABLE +PFA_SPDR: + .dw 78 +; ( -- addr ) System Constant +; R( -- ) +; SPI Status Register +VE_SPSR: + .dw $ff04 + .db "SPSR" + .dw VE_HEAD + .set VE_HEAD=VE_SPSR +XT_SPSR: + .dw PFA_DOVARIABLE +PFA_SPSR: + .dw 77 +; ( -- addr ) System Constant +; R( -- ) +; SPI Control Register +VE_SPCR: + .dw $ff04 + .db "SPCR" + .dw VE_HEAD + .set VE_HEAD=VE_SPCR +XT_SPCR: + .dw PFA_DOVARIABLE +PFA_SPCR: + .dw 76 + +.endif +.if WANT_WATCHDOG == 1 +; ( -- addr ) System Constant +; R( -- ) +; Watchdog Timer Control Register +VE_WDTCSR: + .dw $ff06 + .db "WDTCSR" + .dw VE_HEAD + .set VE_HEAD=VE_WDTCSR +XT_WDTCSR: + .dw PFA_DOVARIABLE +PFA_WDTCSR: + .dw 96 + +.endif +.if WANT_EEPROM == 1 +; ( -- addr ) System Constant +; R( -- ) +; EEPROM Address Register Bytes +VE_EEAR: + .dw $ff04 + .db "EEAR" + .dw VE_HEAD + .set VE_HEAD=VE_EEAR +XT_EEAR: + .dw PFA_DOVARIABLE +PFA_EEAR: + .dw 65 +; ( -- addr ) System Constant +; R( -- ) +; EEPROM Data Register +VE_EEDR: + .dw $ff04 + .db "EEDR" + .dw VE_HEAD + .set VE_HEAD=VE_EEDR +XT_EEDR: + .dw PFA_DOVARIABLE +PFA_EEDR: + .dw 64 +; ( -- addr ) System Constant +; R( -- ) +; EEPROM Control Register +VE_EECR: + .dw $ff04 + .db "EECR" + .dw VE_HEAD + .set VE_HEAD=VE_EECR +XT_EECR: + .dw PFA_DOVARIABLE +PFA_EECR: + .dw 63 + +.endif +.if WANT_CPU == 1 +; ( -- addr ) System Constant +; R( -- ) +; Power Reduction Register +VE_PRR: + .dw $ff03 + .db "PRR",0 + .dw VE_HEAD + .set VE_HEAD=VE_PRR +XT_PRR: + .dw PFA_DOVARIABLE +PFA_PRR: + .dw 100 +; ( -- addr ) System Constant +; R( -- ) +; Oscillator Calibration Value +VE_OSCCAL: + .dw $ff06 + .db "OSCCAL" + .dw VE_HEAD + .set VE_HEAD=VE_OSCCAL +XT_OSCCAL: + .dw PFA_DOVARIABLE +PFA_OSCCAL: + .dw 102 +; ( -- addr ) System Constant +; R( -- ) +; Clock Prescale Register +VE_CLKPR: + .dw $ff05 + .db "CLKPR",0 + .dw VE_HEAD + .set VE_HEAD=VE_CLKPR +XT_CLKPR: + .dw PFA_DOVARIABLE +PFA_CLKPR: + .dw 97 +; ( -- addr ) System Constant +; R( -- ) +; Status Register +VE_SREG: + .dw $ff04 + .db "SREG" + .dw VE_HEAD + .set VE_HEAD=VE_SREG +XT_SREG: + .dw PFA_DOVARIABLE +PFA_SREG: + .dw 95 +; ( -- addr ) System Constant +; R( -- ) +; Stack Pointer +VE_SP: + .dw $ff02 + .db "SP" + .dw VE_HEAD + .set VE_HEAD=VE_SP +XT_SP: + .dw PFA_DOVARIABLE +PFA_SP: + .dw 93 +; ( -- addr ) System Constant +; R( -- ) +; Store Program Memory Control and Status Register +VE_SPMCSR: + .dw $ff06 + .db "SPMCSR" + .dw VE_HEAD + .set VE_HEAD=VE_SPMCSR +XT_SPMCSR: + .dw PFA_DOVARIABLE +PFA_SPMCSR: + .dw 87 +; ( -- addr ) System Constant +; R( -- ) +; MCU Control Register +VE_MCUCR: + .dw $ff05 + .db "MCUCR",0 + .dw VE_HEAD + .set VE_HEAD=VE_MCUCR +XT_MCUCR: + .dw PFA_DOVARIABLE +PFA_MCUCR: + .dw 85 +; ( -- addr ) System Constant +; R( -- ) +; MCU Status Register +VE_MCUSR: + .dw $ff05 + .db "MCUSR",0 + .dw VE_HEAD + .set VE_HEAD=VE_MCUSR +XT_MCUSR: + .dw PFA_DOVARIABLE +PFA_MCUSR: + .dw 84 +; ( -- addr ) System Constant +; R( -- ) +; Sleep Mode Control Register +VE_SMCR: + .dw $ff04 + .db "SMCR" + .dw VE_HEAD + .set VE_HEAD=VE_SMCR +XT_SMCR: + .dw PFA_DOVARIABLE +PFA_SMCR: + .dw 83 +; ( -- addr ) System Constant +; R( -- ) +; General Purpose I/O Register 2 +VE_GPIOR2: + .dw $ff06 + .db "GPIOR2" + .dw VE_HEAD + .set VE_HEAD=VE_GPIOR2 +XT_GPIOR2: + .dw PFA_DOVARIABLE +PFA_GPIOR2: + .dw 75 +; ( -- addr ) System Constant +; R( -- ) +; General Purpose I/O Register 1 +VE_GPIOR1: + .dw $ff06 + .db "GPIOR1" + .dw VE_HEAD + .set VE_HEAD=VE_GPIOR1 +XT_GPIOR1: + .dw PFA_DOVARIABLE +PFA_GPIOR1: + .dw 74 +; ( -- addr ) System Constant +; R( -- ) +; General Purpose I/O Register 0 +VE_GPIOR0: + .dw $ff06 + .db "GPIOR0" + .dw VE_HEAD + .set VE_HEAD=VE_GPIOR0 +XT_GPIOR0: + .dw PFA_DOVARIABLE +PFA_GPIOR0: + .dw 62 + +.endif diff --git a/amforth-6.5/avr8/devices/atmega88a/device.py b/amforth-6.5/avr8/devices/atmega88a/device.py new file mode 100644 index 0000000..4c18ee9 --- /dev/null +++ b/amforth-6.5/avr8/devices/atmega88a/device.py @@ -0,0 +1,281 @@ +# Partname: ATmega88A +# generated automatically, do not edit +MCUREGS = { + 'UDR0': '&198', + 'UCSR0A': '&192', + 'UCSR0A_RXC0': '$80', + 'UCSR0A_TXC0': '$40', + 'UCSR0A_UDRE0': '$20', + 'UCSR0A_FE0': '$10', + 'UCSR0A_DOR0': '$08', + 'UCSR0A_UPE0': '$04', + 'UCSR0A_U2X0': '$02', + 'UCSR0A_MPCM0': '$01', + 'UCSR0B': '&193', + 'UCSR0B_RXCIE0': '$80', + 'UCSR0B_TXCIE0': '$40', + 'UCSR0B_UDRIE0': '$20', + 'UCSR0B_RXEN0': '$10', + 'UCSR0B_TXEN0': '$08', + 'UCSR0B_UCSZ02': '$04', + 'UCSR0B_RXB80': '$02', + 'UCSR0B_TXB80': '$01', + 'UCSR0C': '&194', + 'UCSR0C_UMSEL0': '$C0', + 'UCSR0C_UPM0': '$30', + 'UCSR0C_USBS0': '$08', + 'UCSR0C_UCSZ0': '$06', + 'UCSR0C_UCPOL0': '$01', + 'UBRR0': '&196', + 'TWAMR': '&189', + 'TWAMR_TWAM': '$FE', + 'TWBR': '&184', + 'TWCR': '&188', + 'TWCR_TWINT': '$80', + 'TWCR_TWEA': '$40', + 'TWCR_TWSTA': '$20', + 'TWCR_TWSTO': '$10', + 'TWCR_TWWC': '$08', + 'TWCR_TWEN': '$04', + 'TWCR_TWIE': '$01', + 'TWSR': '&185', + 'TWSR_TWS': '$F8', + 'TWSR_TWPS': '$03', + 'TWDR': '&187', + 'TWAR': '&186', + 'TWAR_TWA': '$FE', + 'TWAR_TWGCE': '$01', + 'TIMSK1': '&111', + 'TIMSK1_ICIE1': '$20', + 'TIMSK1_OCIE1B': '$04', + 'TIMSK1_OCIE1A': '$02', + 'TIMSK1_TOIE1': '$01', + 'TIFR1': '&54', + 'TIFR1_ICF1': '$20', + 'TIFR1_OCF1B': '$04', + 'TIFR1_OCF1A': '$02', + 'TIFR1_TOV1': '$01', + 'TCCR1A': '&128', + 'TCCR1A_COM1A': '$C0', + 'TCCR1A_COM1B': '$30', + 'TCCR1A_WGM1': '$03', + 'TCCR1B': '&129', + 'TCCR1B_ICNC1': '$80', + 'TCCR1B_ICES1': '$40', + 'TCCR1B_WGM1': '$18', + 'TCCR1B_CS1': '$07', + 'TCCR1C': '&130', + 'TCCR1C_FOC1A': '$80', + 'TCCR1C_FOC1B': '$40', + 'TCNT1': '&132', + 'OCR1A': '&136', + 'OCR1B': '&138', + 'ICR1': '&134', + 'GTCCR': '&67', + 'GTCCR_TSM': '$80', + 'GTCCR_PSRSYNC': '$01', + 'TIMSK2': '&112', + 'TIMSK2_OCIE2B': '$04', + 'TIMSK2_OCIE2A': '$02', + 'TIMSK2_TOIE2': '$01', + 'TIFR2': '&55', + 'TIFR2_OCF2B': '$04', + 'TIFR2_OCF2A': '$02', + 'TIFR2_TOV2': '$01', + 'TCCR2A': '&176', + 'TCCR2A_COM2A': '$C0', + 'TCCR2A_COM2B': '$30', + 'TCCR2A_WGM2': '$03', + 'TCCR2B': '&177', + 'TCCR2B_FOC2A': '$80', + 'TCCR2B_FOC2B': '$40', + 'TCCR2B_WGM22': '$08', + 'TCCR2B_CS2': '$07', + 'TCNT2': '&178', + 'OCR2B': '&180', + 'OCR2A': '&179', + 'ASSR': '&182', + 'ASSR_EXCLK': '$40', + 'ASSR_AS2': '$20', + 'ASSR_TCN2UB': '$10', + 'ASSR_OCR2AUB': '$08', + 'ASSR_OCR2BUB': '$04', + 'ASSR_TCR2AUB': '$02', + 'ASSR_TCR2BUB': '$01', + 'ADMUX': '&124', + 'ADMUX_REFS': '$C0', + 'ADMUX_ADLAR': '$20', + 'ADMUX_MUX': '$0F', + 'ADC': '&120', + 'ADCSRA': '&122', + 'ADCSRA_ADEN': '$80', + 'ADCSRA_ADSC': '$40', + 'ADCSRA_ADATE': '$20', + 'ADCSRA_ADIF': '$10', + 'ADCSRA_ADIE': '$08', + 'ADCSRA_ADPS': '$07', + 'ADCSRB': '&123', + 'ADCSRB_ACME': '$40', + 'ADCSRB_ADTS': '$07', + 'DIDR0': '&126', + 'DIDR0_ADC5D': '$20', + 'DIDR0_ADC4D': '$10', + 'DIDR0_ADC3D': '$08', + 'DIDR0_ADC2D': '$04', + 'DIDR0_ADC1D': '$02', + 'DIDR0_ADC0D': '$01', + 'ACSR': '&80', + 'ACSR_ACD': '$80', + 'ACSR_ACBG': '$40', + 'ACSR_ACO': '$20', + 'ACSR_ACI': '$10', + 'ACSR_ACIE': '$08', + 'ACSR_ACIC': '$04', + 'ACSR_ACIS': '$03', + 'DIDR1': '&127', + 'DIDR1_AIN1D': '$02', + 'DIDR1_AIN0D': '$01', + 'PORTB': '&37', + 'DDRB': '&36', + 'PINB': '&35', + 'PORTC': '&40', + 'DDRC': '&39', + 'PINC': '&38', + 'PORTD': '&43', + 'DDRD': '&42', + 'PIND': '&41', + 'OCR0B': '&72', + 'OCR0A': '&71', + 'TCNT0': '&70', + 'TCCR0B': '&69', + 'TCCR0B_FOC0A': '$80', + 'TCCR0B_FOC0B': '$40', + 'TCCR0B_WGM02': '$08', + 'TCCR0B_CS0': '$07', + 'TCCR0A': '&68', + 'TCCR0A_COM0A': '$C0', + 'TCCR0A_COM0B': '$30', + 'TCCR0A_WGM0': '$03', + 'TIMSK0': '&110', + 'TIMSK0_OCIE0B': '$04', + 'TIMSK0_OCIE0A': '$02', + 'TIMSK0_TOIE0': '$01', + 'TIFR0': '&53', + 'TIFR0_OCF0B': '$04', + 'TIFR0_OCF0A': '$02', + 'TIFR0_TOV0': '$01', + 'EICRA': '&105', + 'EICRA_ISC1': '$0C', + 'EICRA_ISC0': '$03', + 'EIMSK': '&61', + 'EIMSK_INT': '$03', + 'EIFR': '&60', + 'EIFR_INTF': '$03', + 'PCICR': '&104', + 'PCICR_PCIE': '$07', + 'PCMSK2': '&109', + 'PCMSK2_PCINT': '$FF', + 'PCMSK1': '&108', + 'PCMSK1_PCINT': '$7F', + 'PCMSK0': '&107', + 'PCMSK0_PCINT': '$FF', + 'PCIFR': '&59', + 'PCIFR_PCIF': '$07', + 'SPDR': '&78', + 'SPSR': '&77', + 'SPSR_SPIF': '$80', + 'SPSR_WCOL': '$40', + 'SPSR_SPI2X': '$01', + 'SPCR': '&76', + 'SPCR_SPIE': '$80', + 'SPCR_SPE': '$40', + 'SPCR_DORD': '$20', + 'SPCR_MSTR': '$10', + 'SPCR_CPOL': '$08', + 'SPCR_CPHA': '$04', + 'SPCR_SPR': '$03', + 'WDTCSR': '&96', + 'WDTCSR_WDIF': '$80', + 'WDTCSR_WDIE': '$40', + 'WDTCSR_WDP': '$27', + 'WDTCSR_WDCE': '$10', + 'WDTCSR_WDE': '$08', + 'EEAR': '&65', + 'EEDR': '&64', + 'EECR': '&63', + 'EECR_EEPM': '$30', + 'EECR_EERIE': '$08', + 'EECR_EEMPE': '$04', + 'EECR_EEPE': '$02', + 'EECR_EERE': '$01', + 'PRR': '&100', + 'PRR_PRTWI': '$80', + 'PRR_PRTIM2': '$40', + 'PRR_PRTIM0': '$20', + 'PRR_PRTIM1': '$08', + 'PRR_PRSPI': '$04', + 'PRR_PRUSART0': '$02', + 'PRR_PRADC': '$01', + 'OSCCAL': '&102', + 'CLKPR': '&97', + 'CLKPR_CLKPCE': '$80', + 'CLKPR_CLKPS': '$0F', + 'SREG': '&95', + 'SREG_I': '$80', + 'SREG_T': '$40', + 'SREG_H': '$20', + 'SREG_S': '$10', + 'SREG_V': '$08', + 'SREG_N': '$04', + 'SREG_Z': '$02', + 'SREG_C': '$01', + 'SP': '&93', + 'SPMCSR': '&87', + 'SPMCSR_SPMIE': '$80', + 'SPMCSR_RWWSB': '$40', + 'SPMCSR_RWWSRE': '$10', + 'SPMCSR_BLBSET': '$08', + 'SPMCSR_PGWRT': '$04', + 'SPMCSR_PGERS': '$02', + 'SPMCSR_SELFPRGEN': '$01', + 'MCUCR': '&85', + 'MCUCR_PUD': '$10', + 'MCUCR_IVSEL': '$02', + 'MCUCR_IVCE': '$01', + 'MCUSR': '&84', + 'MCUSR_WDRF': '$08', + 'MCUSR_BORF': '$04', + 'MCUSR_EXTRF': '$02', + 'MCUSR_PORF': '$01', + 'SMCR': '&83', + 'SMCR_SM': '$0E', + 'SMCR_SE': '$01', + 'GPIOR2': '&75', + 'GPIOR1': '&74', + 'GPIOR0': '&62', + 'INT0Addr': '1', + 'INT1Addr': '2', + 'PCINT0Addr': '3', + 'PCINT1Addr': '4', + 'PCINT2Addr': '5', + 'WDTAddr': '6', + 'TIMER2_COMPAAddr': '7', + 'TIMER2_COMPBAddr': '8', + 'TIMER2_OVFAddr': '9', + 'TIMER1_CAPTAddr': '10', + 'TIMER1_COMPAAddr': '11', + 'TIMER1_COMPBAddr': '12', + 'TIMER1_OVFAddr': '13', + 'TIMER0_COMPAAddr': '14', + 'TIMER0_COMPBAddr': '15', + 'TIMER0_OVFAddr': '16', + 'SPI__STCAddr': '17', + 'USART__RXAddr': '18', + 'USART__UDREAddr': '19', + 'USART__TXAddr': '20', + 'ADCAddr': '21', + 'EE_READYAddr': '22', + 'ANALOG_COMPAddr': '23', + 'TWIAddr': '24', + 'SPM_ReadyAddr': '25' +} \ No newline at end of file diff --git a/amforth-6.5/avr8/devices/atmega88a/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega88a/words/no-jtag.asm new file mode 100644 index 0000000..352a4bb --- /dev/null +++ b/amforth-6.5/avr8/devices/atmega88a/words/no-jtag.asm @@ -0,0 +1,14 @@ +; ( -- ) +; ( -- ) +; MCU +; disable jtag at runtime +VE_NOJTAG: + .dw $FF05 + .db "-jtag",0 + .dw VE_HEAD + .set VE_HEAD = VE_NOJTAG +XT_NOJTAG: + .dw PFA_NOJTAG +PFA_NOJTAG: + + jmp_ DO_NEXT diff --git a/amforth-6.5/avr8/devices/atmega88a/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega88a/words/no-wdt.asm new file mode 100644 index 0000000..ff6ddd1 --- /dev/null +++ b/amforth-6.5/avr8/devices/atmega88a/words/no-wdt.asm @@ -0,0 +1,34 @@ +; ( -- ) +; MCU +; disable watch dog timer at runtime +VE_NOWDT: + .dw $ff04 + .db "-wdt" + .dw VE_HEAD + .set VE_HEAD = VE_NOWDT +XT_NOWDT: + .dw PFA_NOWDT +PFA_NOWDT: + + in temp1,SREG + push temp1 + ; Turn always off global interrupt. + cli + ; Reset Watchdog Timer + wdr + ; Clear WDRF in MCUSR + in temp1, MCUSR + andi temp1, (0xff & (0<