From 67d25d837ac55f28a366c0a3b262e439a6e75fc3 Mon Sep 17 00:00:00 2001 From: Dimitri Sokolyuk Date: Sat, 19 Aug 2017 12:15:28 +0200 Subject: Add AmForth --- amforth-6.5/avr8/devices/atmega88pa/device.py | 283 ++++++++++++++++++++++++++ 1 file changed, 283 insertions(+) create mode 100644 amforth-6.5/avr8/devices/atmega88pa/device.py (limited to 'amforth-6.5/avr8/devices/atmega88pa/device.py') diff --git a/amforth-6.5/avr8/devices/atmega88pa/device.py b/amforth-6.5/avr8/devices/atmega88pa/device.py new file mode 100644 index 0000000..d814349 --- /dev/null +++ b/amforth-6.5/avr8/devices/atmega88pa/device.py @@ -0,0 +1,283 @@ +# Partname: ATmega88PA +# generated automatically, do not edit +MCUREGS = { + 'UDR0': '&198', + 'UCSR0A': '&192', + 'UCSR0A_RXC0': '$80', + 'UCSR0A_TXC0': '$40', + 'UCSR0A_UDRE0': '$20', + 'UCSR0A_FE0': '$10', + 'UCSR0A_DOR0': '$08', + 'UCSR0A_UPE0': '$04', + 'UCSR0A_U2X0': '$02', + 'UCSR0A_MPCM0': '$01', + 'UCSR0B': '&193', + 'UCSR0B_RXCIE0': '$80', + 'UCSR0B_TXCIE0': '$40', + 'UCSR0B_UDRIE0': '$20', + 'UCSR0B_RXEN0': '$10', + 'UCSR0B_TXEN0': '$08', + 'UCSR0B_UCSZ02': '$04', + 'UCSR0B_RXB80': '$02', + 'UCSR0B_TXB80': '$01', + 'UCSR0C': '&194', + 'UCSR0C_UMSEL0': '$C0', + 'UCSR0C_UPM0': '$30', + 'UCSR0C_USBS0': '$08', + 'UCSR0C_UCSZ0': '$06', + 'UCSR0C_UCPOL0': '$01', + 'UBRR0': '&196', + 'TWAMR': '&189', + 'TWAMR_TWAM': '$FE', + 'TWBR': '&184', + 'TWCR': '&188', + 'TWCR_TWINT': '$80', + 'TWCR_TWEA': '$40', + 'TWCR_TWSTA': '$20', + 'TWCR_TWSTO': '$10', + 'TWCR_TWWC': '$08', + 'TWCR_TWEN': '$04', + 'TWCR_TWIE': '$01', + 'TWSR': '&185', + 'TWSR_TWS': '$F8', + 'TWSR_TWPS': '$03', + 'TWDR': '&187', + 'TWAR': '&186', + 'TWAR_TWA': '$FE', + 'TWAR_TWGCE': '$01', + 'TIMSK1': '&111', + 'TIMSK1_ICIE1': '$20', + 'TIMSK1_OCIE1B': '$04', + 'TIMSK1_OCIE1A': '$02', + 'TIMSK1_TOIE1': '$01', + 'TIFR1': '&54', + 'TIFR1_ICF1': '$20', + 'TIFR1_OCF1B': '$04', + 'TIFR1_OCF1A': '$02', + 'TIFR1_TOV1': '$01', + 'TCCR1A': '&128', + 'TCCR1A_COM1A': '$C0', + 'TCCR1A_COM1B': '$30', + 'TCCR1A_WGM1': '$03', + 'TCCR1B': '&129', + 'TCCR1B_ICNC1': '$80', + 'TCCR1B_ICES1': '$40', + 'TCCR1B_WGM1': '$18', + 'TCCR1B_CS1': '$07', + 'TCCR1C': '&130', + 'TCCR1C_FOC1A': '$80', + 'TCCR1C_FOC1B': '$40', + 'TCNT1': '&132', + 'OCR1A': '&136', + 'OCR1B': '&138', + 'ICR1': '&134', + 'GTCCR': '&67', + 'GTCCR_TSM': '$80', + 'GTCCR_PSRSYNC': '$01', + 'TIMSK2': '&112', + 'TIMSK2_OCIE2B': '$04', + 'TIMSK2_OCIE2A': '$02', + 'TIMSK2_TOIE2': '$01', + 'TIFR2': '&55', + 'TIFR2_OCF2B': '$04', + 'TIFR2_OCF2A': '$02', + 'TIFR2_TOV2': '$01', + 'TCCR2A': '&176', + 'TCCR2A_COM2A': '$C0', + 'TCCR2A_COM2B': '$30', + 'TCCR2A_WGM2': '$03', + 'TCCR2B': '&177', + 'TCCR2B_FOC2A': '$80', + 'TCCR2B_FOC2B': '$40', + 'TCCR2B_WGM22': '$08', + 'TCCR2B_CS2': '$07', + 'TCNT2': '&178', + 'OCR2B': '&180', + 'OCR2A': '&179', + 'ASSR': '&182', + 'ASSR_EXCLK': '$40', + 'ASSR_AS2': '$20', + 'ASSR_TCN2UB': '$10', + 'ASSR_OCR2AUB': '$08', + 'ASSR_OCR2BUB': '$04', + 'ASSR_TCR2AUB': '$02', + 'ASSR_TCR2BUB': '$01', + 'ADMUX': '&124', + 'ADMUX_REFS': '$C0', + 'ADMUX_ADLAR': '$20', + 'ADMUX_MUX': '$0F', + 'ADC': '&120', + 'ADCSRA': '&122', + 'ADCSRA_ADEN': '$80', + 'ADCSRA_ADSC': '$40', + 'ADCSRA_ADATE': '$20', + 'ADCSRA_ADIF': '$10', + 'ADCSRA_ADIE': '$08', + 'ADCSRA_ADPS': '$07', + 'ADCSRB': '&123', + 'ADCSRB_ACME': '$40', + 'ADCSRB_ADTS': '$07', + 'DIDR0': '&126', + 'DIDR0_ADC5D': '$20', + 'DIDR0_ADC4D': '$10', + 'DIDR0_ADC3D': '$08', + 'DIDR0_ADC2D': '$04', + 'DIDR0_ADC1D': '$02', + 'DIDR0_ADC0D': '$01', + 'ACSR': '&80', + 'ACSR_ACD': '$80', + 'ACSR_ACBG': '$40', + 'ACSR_ACO': '$20', + 'ACSR_ACI': '$10', + 'ACSR_ACIE': '$08', + 'ACSR_ACIC': '$04', + 'ACSR_ACIS': '$03', + 'DIDR1': '&127', + 'DIDR1_AIN1D': '$02', + 'DIDR1_AIN0D': '$01', + 'PORTB': '&37', + 'DDRB': '&36', + 'PINB': '&35', + 'PORTC': '&40', + 'DDRC': '&39', + 'PINC': '&38', + 'PORTD': '&43', + 'DDRD': '&42', + 'PIND': '&41', + 'OCR0B': '&72', + 'OCR0A': '&71', + 'TCNT0': '&70', + 'TCCR0B': '&69', + 'TCCR0B_FOC0A': '$80', + 'TCCR0B_FOC0B': '$40', + 'TCCR0B_WGM02': '$08', + 'TCCR0B_CS0': '$07', + 'TCCR0A': '&68', + 'TCCR0A_COM0A': '$C0', + 'TCCR0A_COM0B': '$30', + 'TCCR0A_WGM0': '$03', + 'TIMSK0': '&110', + 'TIMSK0_OCIE0B': '$04', + 'TIMSK0_OCIE0A': '$02', + 'TIMSK0_TOIE0': '$01', + 'TIFR0': '&53', + 'TIFR0_OCF0B': '$04', + 'TIFR0_OCF0A': '$02', + 'TIFR0_TOV0': '$01', + 'EICRA': '&105', + 'EICRA_ISC1': '$0C', + 'EICRA_ISC0': '$03', + 'EIMSK': '&61', + 'EIMSK_INT': '$03', + 'EIFR': '&60', + 'EIFR_INTF': '$03', + 'PCICR': '&104', + 'PCICR_PCIE': '$07', + 'PCMSK2': '&109', + 'PCMSK2_PCINT': '$FF', + 'PCMSK1': '&108', + 'PCMSK1_PCINT': '$7F', + 'PCMSK0': '&107', + 'PCMSK0_PCINT': '$FF', + 'PCIFR': '&59', + 'PCIFR_PCIF': '$07', + 'SPDR': '&78', + 'SPSR': '&77', + 'SPSR_SPIF': '$80', + 'SPSR_WCOL': '$40', + 'SPSR_SPI2X': '$01', + 'SPCR': '&76', + 'SPCR_SPIE': '$80', + 'SPCR_SPE': '$40', + 'SPCR_DORD': '$20', + 'SPCR_MSTR': '$10', + 'SPCR_CPOL': '$08', + 'SPCR_CPHA': '$04', + 'SPCR_SPR': '$03', + 'WDTCSR': '&96', + 'WDTCSR_WDIF': '$80', + 'WDTCSR_WDIE': '$40', + 'WDTCSR_WDP': '$27', + 'WDTCSR_WDCE': '$10', + 'WDTCSR_WDE': '$08', + 'EEAR': '&65', + 'EEDR': '&64', + 'EECR': '&63', + 'EECR_EEPM': '$30', + 'EECR_EERIE': '$08', + 'EECR_EEMPE': '$04', + 'EECR_EEPE': '$02', + 'EECR_EERE': '$01', + 'PRR': '&100', + 'PRR_PRTWI': '$80', + 'PRR_PRTIM2': '$40', + 'PRR_PRTIM0': '$20', + 'PRR_PRTIM1': '$08', + 'PRR_PRSPI': '$04', + 'PRR_PRUSART0': '$02', + 'PRR_PRADC': '$01', + 'OSCCAL': '&102', + 'CLKPR': '&97', + 'CLKPR_CLKPCE': '$80', + 'CLKPR_CLKPS': '$0F', + 'SREG': '&95', + 'SREG_I': '$80', + 'SREG_T': '$40', + 'SREG_H': '$20', + 'SREG_S': '$10', + 'SREG_V': '$08', + 'SREG_N': '$04', + 'SREG_Z': '$02', + 'SREG_C': '$01', + 'SP': '&93', + 'SPMCSR': '&87', + 'SPMCSR_SPMIE': '$80', + 'SPMCSR_RWWSB': '$40', + 'SPMCSR_RWWSRE': '$10', + 'SPMCSR_BLBSET': '$08', + 'SPMCSR_PGWRT': '$04', + 'SPMCSR_PGERS': '$02', + 'SPMCSR_SELFPRGEN': '$01', + 'MCUCR': '&85', + 'MCUCR_BODS': '$40', + 'MCUCR_BODSE': '$20', + 'MCUCR_PUD': '$10', + 'MCUCR_IVSEL': '$02', + 'MCUCR_IVCE': '$01', + 'MCUSR': '&84', + 'MCUSR_WDRF': '$08', + 'MCUSR_BORF': '$04', + 'MCUSR_EXTRF': '$02', + 'MCUSR_PORF': '$01', + 'SMCR': '&83', + 'SMCR_SM': '$0E', + 'SMCR_SE': '$01', + 'GPIOR2': '&75', + 'GPIOR1': '&74', + 'GPIOR0': '&62', + 'INT0Addr': '1', + 'INT1Addr': '2', + 'PCINT0Addr': '3', + 'PCINT1Addr': '4', + 'PCINT2Addr': '5', + 'WDTAddr': '6', + 'TIMER2_COMPAAddr': '7', + 'TIMER2_COMPBAddr': '8', + 'TIMER2_OVFAddr': '9', + 'TIMER1_CAPTAddr': '10', + 'TIMER1_COMPAAddr': '11', + 'TIMER1_COMPBAddr': '12', + 'TIMER1_OVFAddr': '13', + 'TIMER0_COMPAAddr': '14', + 'TIMER0_COMPBAddr': '15', + 'TIMER0_OVFAddr': '16', + 'SPI__STCAddr': '17', + 'USART__RXAddr': '18', + 'USART__UDREAddr': '19', + 'USART__TXAddr': '20', + 'ADCAddr': '21', + 'EE_READYAddr': '22', + 'ANALOG_COMPAddr': '23', + 'TWIAddr': '24', + 'SPM_ReadyAddr': '25' +} \ No newline at end of file -- cgit v1.2.3