From 67d25d837ac55f28a366c0a3b262e439a6e75fc3 Mon Sep 17 00:00:00 2001 From: Dimitri Sokolyuk Date: Sat, 19 Aug 2017 12:15:28 +0200 Subject: Add AmForth --- amforth-6.5/avr8/devices/atmega8hva/atmega8hva.frt | 140 +++ amforth-6.5/avr8/devices/atmega8hva/device.asm | 114 +++ amforth-6.5/avr8/devices/atmega8hva/device.inc | 1053 ++++++++++++++++++++ amforth-6.5/avr8/devices/atmega8hva/device.py | 104 ++ 4 files changed, 1411 insertions(+) create mode 100644 amforth-6.5/avr8/devices/atmega8hva/atmega8hva.frt create mode 100644 amforth-6.5/avr8/devices/atmega8hva/device.asm create mode 100644 amforth-6.5/avr8/devices/atmega8hva/device.inc create mode 100644 amforth-6.5/avr8/devices/atmega8hva/device.py (limited to 'amforth-6.5/avr8/devices/atmega8hva') diff --git a/amforth-6.5/avr8/devices/atmega8hva/atmega8hva.frt b/amforth-6.5/avr8/devices/atmega8hva/atmega8hva.frt new file mode 100644 index 0000000..a2b741b --- /dev/null +++ b/amforth-6.5/avr8/devices/atmega8hva/atmega8hva.frt @@ -0,0 +1,140 @@ +\ Partname: ATmega8HVA +\ Built using part description XML file version 1 +\ generated automatically + +hex + +\ AD_CONVERTER +79 constant VADCH \ VADC Data Register High Byte +78 constant VADCL \ VADC Data Register Low Byte +7A constant VADCSR \ The VADC Control and Status register +7C constant VADMUX \ The VADC multiplexer Selection Register + +\ BANDGAP +D0 constant BGCCR \ Bandgap Calibration Register +D1 constant BGCRR \ Bandgap Calibration of Resistor Ladder + +\ BATTERY_PROTECTION +F9 constant BPCHCD \ Battery Protection Charge-High-current Detection Level Register +F7 constant BPCOCD \ Battery Protection Charge-Over-current Detection Level Register +FD constant BPCR \ Battery Protection Control Register +F8 constant BPDHCD \ Battery Protection Discharge-High-current Detection Level Register +F6 constant BPDOCD \ Battery Protection Discharge-Over-current Detection Level Register +FC constant BPHCTR \ Battery Protection Short-current Timing Register +F3 constant BPIFR \ Battery Protection Interrupt Flag Register +F2 constant BPIMSK \ Battery Protection Interrupt Mask Register +FB constant BPOCTR \ Battery Protection Over-current Timing Register +FE constant BPPLR \ Battery Protection Parameter Lock Register +F5 constant BPSCD \ Battery Protection Short-Circuit Detection Level Register +FA constant BPSCTR \ Battery Protection Short-current Timing Register + +\ BOOT_LOAD +57 constant SPMCSR \ Store Program Memory Control and Status Register + +\ COULOMB_COUNTER +E0 constant CADAC0 \ ADC Accumulate Current +E1 constant CADAC1 \ ADC Accumulate Current +E2 constant CADAC2 \ ADC Accumulate Current +E3 constant CADAC3 \ ADC Accumulate Current +E4 constant CADCSRA \ CC-ADC Control and Status Register A +E5 constant CADCSRB \ CC-ADC Control and Status Register B +E9 constant CADICH \ CC-ADC Instantaneous Current +E8 constant CADICL \ CC-ADC Instantaneous Current +E6 constant CADRC \ CC-ADC Regular Current + +\ CPU +61 constant CLKPR \ Clock Prescale Register +7E constant DIDR0 \ Digital Input Disable Register +66 constant FOSCCAL \ Fast Oscillator Calibration Value +3E constant GPIOR0 \ General Purpose IO Register 0 +4A constant GPIOR1 \ General Purpose IO Register 1 +4B constant GPIOR2 \ General Purpose IO Register 2 +55 constant MCUCR \ MCU Control Register +54 constant MCUSR \ MCU Status Register +37 constant OSICSR \ Oscillator Sampling Interface Control and Status Register +64 constant PRR0 \ Power Reduction Register 0 +53 constant SMCR \ Sleep Mode Control Register +5E constant SPH \ Stack Pointer High +5D constant SPL \ Stack Pointer Low +5F constant SREG \ Status Register + +\ EEPROM +41 constant EEAR \ EEPROM Read/Write Access +3F constant EECR \ EEPROM Control Register +40 constant EEDR \ EEPROM Data Register + +\ EXTERNAL_INTERRUPT +69 constant EICRA \ External Interrupt Control Register +3C constant EIFR \ External Interrupt Flag Register +3D constant EIMSK \ External Interrupt Mask Register + +\ FET +F0 constant FCSR \ FET Control and Status Register + +\ PORTA +21 constant DDRA \ Port A Data Direction Register +20 constant PINA \ Port A Input Pins +22 constant PORTA \ Port A Data Register + +\ PORTB +24 constant DDRB \ Data Direction Register, Port B +23 constant PINB \ Input Pins, Port B +25 constant PORTB \ Data Register, Port B + +\ PORTC +26 constant PINC \ Port C Input Pins +28 constant PORTC \ Port C Data Register + +\ SPI +4c constant SPCR \ SPI Control Register +4e constant SPDR \ SPI Data Register +4d constant SPSR \ SPI Status Register + +\ TIMER_COUNTER_0 +48 constant OCR0A \ Output compare Register A +49 constant OCR0B \ Output compare Register B +44 constant TCCR0A \ Timer/Counter0 Control Register +45 constant TCCR0B \ Timer/Counter0 Control Register +47 constant TCNT0H \ Timer Counter 0 High Byte +46 constant TCNT0L \ Timer Counter 0 Low Byte +35 constant TIFR0 \ Timer/Counter Interrupt Flag register +6E constant TIMSK0 \ Timer/Counter Interrupt Mask Register + +\ TIMER_COUNTER_1 +43 constant GTCCR \ General Timer/Counter Control Register +88 constant OCR1A \ Output Compare Register 1A +89 constant OCR1B \ Output Compare Register B +80 constant TCCR1A \ Timer/Counter 1 Control Register A +81 constant TCCR1B \ Timer/Counter1 Control Register B +85 constant TCNT1H \ Timer Counter 1 High Byte +84 constant TCNT1L \ Timer Counter 1 Low Byte +36 constant TIFR1 \ Timer/Counter Interrupt Flag register +6F constant TIMSK1 \ Timer/Counter Interrupt Mask Register + +\ VOLTAGE_REGULATOR +C8 constant ROCR \ Regulator Operating Condition Register + +\ WATCHDOG +60 constant WDTCSR \ Watchdog Timer Control Register + +\ Interrupts +0001 constant BPINTAddr \ Battery Protection Interrupt +0002 constant VREGMONAddr \ Voltage regulator monitor interrupt +0003 constant INT0Addr \ External Interrupt Request 0 +0004 constant INT1Addr \ External Interrupt Request 1 +0005 constant INT2Addr \ External Interrupt Request 2 +0006 constant WDTAddr \ Watchdog Timeout Interrupt +0007 constant TIMER1_ICAddr \ Timer 1 Input capture +0008 constant TIMER1_COMPAAddr \ Timer 1 Compare Match A +0009 constant TIMER1_COMPBAddr \ Timer 1 Compare Match B +000A constant TIMER1_OVFAddr \ Timer 1 overflow +000B constant TIMER0_ICAddr \ Timer 0 Input Capture +000C constant TIMER0_COMPAAddr \ Timer 0 Comapre Match A +000D constant TIMER0_COMPBAddr \ Timer 0 Compare Match B +000E constant TIMER0_OVFAddr \ Timer 0 Overflow +000F constant SPI;STCAddr \ SPI Serial transfer complete +0010 constant VADCAddr \ Voltage ADC Conversion Complete +0011 constant CCADC_CONVAddr \ Coulomb Counter ADC Conversion Complete +0012 constant CCADC_REG_CURAddr \ Coloumb Counter ADC Regular Current +0013 constant CCADC_ACCAddr \ Coloumb Counter ADC Accumulator +014 constant EE_READYAddr \ EEPROM Ready diff --git a/amforth-6.5/avr8/devices/atmega8hva/device.asm b/amforth-6.5/avr8/devices/atmega8hva/device.asm new file mode 100644 index 0000000..c556dc6 --- /dev/null +++ b/amforth-6.5/avr8/devices/atmega8hva/device.asm @@ -0,0 +1,114 @@ +; Partname: ATmega8HVA +; Built using part description XML file version 1 +; generated automatically, do not edit + +.nolist + .include "m8HVAdef.inc" +.list + +.equ ramstart = $100 +.equ CELLSIZE = 2 +.macro readflashcell + lsl zl + rol zh + lpm @0, Z+ + lpm @1, Z+ +.endmacro +.macro writeflashcell + lsl zl + rol zh +.endmacro + +; the following definitions are shortcuts for the respective forth source segments if set to 1 +.set WANT_AD_CONVERTER = 0 +.set WANT_BANDGAP = 0 +.set WANT_BATTERY_PROTECTION = 0 +.set WANT_BOOT_LOAD = 0 +.set WANT_COULOMB_COUNTER = 0 +.set WANT_CPU = 0 +.set WANT_EEPROM = 0 +.set WANT_EXTERNAL_INTERRUPT = 0 +.set WANT_FET = 0 +.set WANT_PORTA = 0 +.set WANT_PORTB = 0 +.set WANT_PORTC = 0 +.set WANT_SPI = 0 +.set WANT_TIMER_COUNTER_0 = 0 +.set WANT_TIMER_COUNTER_1 = 0 +.set WANT_VOLTAGE_REGULATOR = 0 +.set WANT_WATCHDOG = 0 + + +.ifndef SPMEN + .equ SPMEN = SELFPRGEN +.endif + +.ifndef SPMCSR + .equ SPMCSR = SPMCR +.endif + +.ifndef EEPE + .equ EEPE = EEWE +.endif + +.ifndef EEMPE + .equ EEMPE = EEMWE +.endif +.equ intvecsize = 1 ; please verify; flash size: 8192 bytes +.equ pclen = 2 ; please verify +.overlap +.equ INTVECTORS = 21 +.org $0001 + rcall isr ; Battery Protection Interrupt +.org $0002 + rcall isr ; Voltage regulator monitor interrupt +.org $0003 + rcall isr ; External Interrupt Request 0 +.org $0004 + rcall isr ; External Interrupt Request 1 +.org $0005 + rcall isr ; External Interrupt Request 2 +.org $0006 + rcall isr ; Watchdog Timeout Interrupt +.org $0007 + rcall isr ; Timer 1 Input capture +.org $0008 + rcall isr ; Timer 1 Compare Match A +.org $0009 + rcall isr ; Timer 1 Compare Match B +.org $000A + rcall isr ; Timer 1 overflow +.org $000B + rcall isr ; Timer 0 Input Capture +.org $000C + rcall isr ; Timer 0 Comapre Match A +.org $000D + rcall isr ; Timer 0 Compare Match B +.org $000E + rcall isr ; Timer 0 Overflow +.org $000F + rcall isr ; SPI Serial transfer complete +.org $0010 + rcall isr ; Voltage ADC Conversion Complete +.org $0011 + rcall isr ; Coulomb Counter ADC Conversion Complete +.org $0012 + rcall isr ; Coloumb Counter ADC Regular Current +.org $0013 + rcall isr ; Coloumb Counter ADC Accumulator +.org $014 + rcall isr ; EEPROM Ready +.nooverlap +mcu_info: +mcu_ramsize: + .dw 512 +mcu_eepromsize: + .dw 256 +mcu_maxdp: + .dw 0 ; minimum of 0 (from XML) and 0xffff +mcu_numints: + .dw 21 +mcu_name: + .dw 10 + .db "ATmega8HVA" +.set codestart=pc diff --git a/amforth-6.5/avr8/devices/atmega8hva/device.inc b/amforth-6.5/avr8/devices/atmega8hva/device.inc new file mode 100644 index 0000000..0405071 --- /dev/null +++ b/amforth-6.5/avr8/devices/atmega8hva/device.inc @@ -0,0 +1,1053 @@ +; Partname: ATmega8HVA +; Built using part description XML file version 1 +; generated automatically, no not edit + +; ******** +.if WANT_AD_CONVERTER == 1 +; ******** +; ( -- addr ) System Constant +; R( -- ) +; VADC Data Register High Byte +VE_VADCH: + .dw $ff05 + .db "VADCH",0 + .dw VE_HEAD + .set VE_HEAD=VE_VADCH +XT_VADCH: + .dw PFA_DOVARIABLE +PFA_VADCH: + .dw $79 +; ( -- addr ) System Constant +; R( -- ) +; VADC Data Register Low Byte +VE_VADCL: + .dw $ff05 + .db "VADCL",0 + .dw VE_HEAD + .set VE_HEAD=VE_VADCL +XT_VADCL: + .dw PFA_DOVARIABLE +PFA_VADCL: + .dw $78 +; ( -- addr ) System Constant +; R( -- ) +; The VADC Control and Status register +VE_VADCSR: + .dw $ff06 + .db "VADCSR" + .dw VE_HEAD + .set VE_HEAD=VE_VADCSR +XT_VADCSR: + .dw PFA_DOVARIABLE +PFA_VADCSR: + .dw $7A +; ( -- addr ) System Constant +; R( -- ) +; The VADC multiplexer Selection Register +VE_VADMUX: + .dw $ff06 + .db "VADMUX" + .dw VE_HEAD + .set VE_HEAD=VE_VADMUX +XT_VADMUX: + .dw PFA_DOVARIABLE +PFA_VADMUX: + .dw $7C + +.endif + +; ******** +.if WANT_BANDGAP == 1 +; ******** +; ( -- addr ) System Constant +; R( -- ) +; Bandgap Calibration Register +VE_BGCCR: + .dw $ff05 + .db "BGCCR",0 + .dw VE_HEAD + .set VE_HEAD=VE_BGCCR +XT_BGCCR: + .dw PFA_DOVARIABLE +PFA_BGCCR: + .dw $D0 +; ( -- addr ) System Constant +; R( -- ) +; Bandgap Calibration of Resistor Ladder +VE_BGCRR: + .dw $ff05 + .db "BGCRR",0 + .dw VE_HEAD + .set VE_HEAD=VE_BGCRR +XT_BGCRR: + .dw PFA_DOVARIABLE +PFA_BGCRR: + .dw $D1 + +.endif + +; ******** +.if WANT_BATTERY_PROTECTION == 1 +; ******** +; ( -- addr ) System Constant +; R( -- ) +; Battery Protection Charge-High-current Detection Level Register +VE_BPCHCD: + .dw $ff06 + .db "BPCHCD" + .dw VE_HEAD + .set VE_HEAD=VE_BPCHCD +XT_BPCHCD: + .dw PFA_DOVARIABLE +PFA_BPCHCD: + .dw $F9 +; ( -- addr ) System Constant +; R( -- ) +; Battery Protection Charge-Over-current Detection Level Register +VE_BPCOCD: + .dw $ff06 + .db "BPCOCD" + .dw VE_HEAD + .set VE_HEAD=VE_BPCOCD +XT_BPCOCD: + .dw PFA_DOVARIABLE +PFA_BPCOCD: + .dw $F7 +; ( -- addr ) System Constant +; R( -- ) +; Battery Protection Control Register +VE_BPCR: + .dw $ff04 + .db "BPCR" + .dw VE_HEAD + .set VE_HEAD=VE_BPCR +XT_BPCR: + .dw PFA_DOVARIABLE +PFA_BPCR: + .dw $FD +; ( -- addr ) System Constant +; R( -- ) +; Battery Protection Discharge-High-current Detection Level Register +VE_BPDHCD: + .dw $ff06 + .db "BPDHCD" + .dw VE_HEAD + .set VE_HEAD=VE_BPDHCD +XT_BPDHCD: + .dw PFA_DOVARIABLE +PFA_BPDHCD: + .dw $F8 +; ( -- addr ) System Constant +; R( -- ) +; Battery Protection Discharge-Over-current Detection Level Register +VE_BPDOCD: + .dw $ff06 + .db "BPDOCD" + .dw VE_HEAD + .set VE_HEAD=VE_BPDOCD +XT_BPDOCD: + .dw PFA_DOVARIABLE +PFA_BPDOCD: + .dw $F6 +; ( -- addr ) System Constant +; R( -- ) +; Battery Protection Short-current Timing Register +VE_BPHCTR: + .dw $ff06 + .db "BPHCTR" + .dw VE_HEAD + .set VE_HEAD=VE_BPHCTR +XT_BPHCTR: + .dw PFA_DOVARIABLE +PFA_BPHCTR: + .dw $FC +; ( -- addr ) System Constant +; R( -- ) +; Battery Protection Interrupt Flag Register +VE_BPIFR: + .dw $ff05 + .db "BPIFR",0 + .dw VE_HEAD + .set VE_HEAD=VE_BPIFR +XT_BPIFR: + .dw PFA_DOVARIABLE +PFA_BPIFR: + .dw $F3 +; ( -- addr ) System Constant +; R( -- ) +; Battery Protection Interrupt Mask Register +VE_BPIMSK: + .dw $ff06 + .db "BPIMSK" + .dw VE_HEAD + .set VE_HEAD=VE_BPIMSK +XT_BPIMSK: + .dw PFA_DOVARIABLE +PFA_BPIMSK: + .dw $F2 +; ( -- addr ) System Constant +; R( -- ) +; Battery Protection Over-current Timing Register +VE_BPOCTR: + .dw $ff06 + .db "BPOCTR" + .dw VE_HEAD + .set VE_HEAD=VE_BPOCTR +XT_BPOCTR: + .dw PFA_DOVARIABLE +PFA_BPOCTR: + .dw $FB +; ( -- addr ) System Constant +; R( -- ) +; Battery Protection Parameter Lock Register +VE_BPPLR: + .dw $ff05 + .db "BPPLR",0 + .dw VE_HEAD + .set VE_HEAD=VE_BPPLR +XT_BPPLR: + .dw PFA_DOVARIABLE +PFA_BPPLR: + .dw $FE +; ( -- addr ) System Constant +; R( -- ) +; Battery Protection Short-Circuit Detection Level Register +VE_BPSCD: + .dw $ff05 + .db "BPSCD",0 + .dw VE_HEAD + .set VE_HEAD=VE_BPSCD +XT_BPSCD: + .dw PFA_DOVARIABLE +PFA_BPSCD: + .dw $F5 +; ( -- addr ) System Constant +; R( -- ) +; Battery Protection Short-current Timing Register +VE_BPSCTR: + .dw $ff06 + .db "BPSCTR" + .dw VE_HEAD + .set VE_HEAD=VE_BPSCTR +XT_BPSCTR: + .dw PFA_DOVARIABLE +PFA_BPSCTR: + .dw $FA + +.endif + +; ******** +.if WANT_BOOT_LOAD == 1 +; ******** +; ( -- addr ) System Constant +; R( -- ) +; Store Program Memory Control and Status Register +VE_SPMCSR: + .dw $ff06 + .db "SPMCSR" + .dw VE_HEAD + .set VE_HEAD=VE_SPMCSR +XT_SPMCSR: + .dw PFA_DOVARIABLE +PFA_SPMCSR: + .dw $57 + +.endif + +; ******** +.if WANT_COULOMB_COUNTER == 1 +; ******** +; ( -- addr ) System Constant +; R( -- ) +; ADC Accumulate Current +VE_CADAC0: + .dw $ff06 + .db "CADAC0" + .dw VE_HEAD + .set VE_HEAD=VE_CADAC0 +XT_CADAC0: + .dw PFA_DOVARIABLE +PFA_CADAC0: + .dw $E0 +; ( -- addr ) System Constant +; R( -- ) +; ADC Accumulate Current +VE_CADAC1: + .dw $ff06 + .db "CADAC1" + .dw VE_HEAD + .set VE_HEAD=VE_CADAC1 +XT_CADAC1: + .dw PFA_DOVARIABLE +PFA_CADAC1: + .dw $E1 +; ( -- addr ) System Constant +; R( -- ) +; ADC Accumulate Current +VE_CADAC2: + .dw $ff06 + .db "CADAC2" + .dw VE_HEAD + .set VE_HEAD=VE_CADAC2 +XT_CADAC2: + .dw PFA_DOVARIABLE +PFA_CADAC2: + .dw $E2 +; ( -- addr ) System Constant +; R( -- ) +; ADC Accumulate Current +VE_CADAC3: + .dw $ff06 + .db "CADAC3" + .dw VE_HEAD + .set VE_HEAD=VE_CADAC3 +XT_CADAC3: + .dw PFA_DOVARIABLE +PFA_CADAC3: + .dw $E3 +; ( -- addr ) System Constant +; R( -- ) +; CC-ADC Control and Status Register A +VE_CADCSRA: + .dw $ff07 + .db "CADCSRA",0 + .dw VE_HEAD + .set VE_HEAD=VE_CADCSRA +XT_CADCSRA: + .dw PFA_DOVARIABLE +PFA_CADCSRA: + .dw $E4 +; ( -- addr ) System Constant +; R( -- ) +; CC-ADC Control and Status Register B +VE_CADCSRB: + .dw $ff07 + .db "CADCSRB",0 + .dw VE_HEAD + .set VE_HEAD=VE_CADCSRB +XT_CADCSRB: + .dw PFA_DOVARIABLE +PFA_CADCSRB: + .dw $E5 +; ( -- addr ) System Constant +; R( -- ) +; CC-ADC Instantaneous Current +VE_CADICH: + .dw $ff06 + .db "CADICH" + .dw VE_HEAD + .set VE_HEAD=VE_CADICH +XT_CADICH: + .dw PFA_DOVARIABLE +PFA_CADICH: + .dw $E9 +; ( -- addr ) System Constant +; R( -- ) +; CC-ADC Instantaneous Current +VE_CADICL: + .dw $ff06 + .db "CADICL" + .dw VE_HEAD + .set VE_HEAD=VE_CADICL +XT_CADICL: + .dw PFA_DOVARIABLE +PFA_CADICL: + .dw $E8 +; ( -- addr ) System Constant +; R( -- ) +; CC-ADC Regular Current +VE_CADRC: + .dw $ff05 + .db "CADRC",0 + .dw VE_HEAD + .set VE_HEAD=VE_CADRC +XT_CADRC: + .dw PFA_DOVARIABLE +PFA_CADRC: + .dw $E6 + +.endif + +; ******** +.if WANT_CPU == 1 +; ******** +; ( -- addr ) System Constant +; R( -- ) +; Clock Prescale Register +VE_CLKPR: + .dw $ff05 + .db "CLKPR",0 + .dw VE_HEAD + .set VE_HEAD=VE_CLKPR +XT_CLKPR: + .dw PFA_DOVARIABLE +PFA_CLKPR: + .dw $61 +; ( -- addr ) System Constant +; R( -- ) +; Digital Input Disable Register +VE_DIDR0: + .dw $ff05 + .db "DIDR0",0 + .dw VE_HEAD + .set VE_HEAD=VE_DIDR0 +XT_DIDR0: + .dw PFA_DOVARIABLE +PFA_DIDR0: + .dw $7E +; ( -- addr ) System Constant +; R( -- ) +; Fast Oscillator Calibration Value +VE_FOSCCAL: + .dw $ff07 + .db "FOSCCAL",0 + .dw VE_HEAD + .set VE_HEAD=VE_FOSCCAL +XT_FOSCCAL: + .dw PFA_DOVARIABLE +PFA_FOSCCAL: + .dw $66 +; ( -- addr ) System Constant +; R( -- ) +; General Purpose IO Register 0 +VE_GPIOR0: + .dw $ff06 + .db "GPIOR0" + .dw VE_HEAD + .set VE_HEAD=VE_GPIOR0 +XT_GPIOR0: + .dw PFA_DOVARIABLE +PFA_GPIOR0: + .dw $3E +; ( -- addr ) System Constant +; R( -- ) +; General Purpose IO Register 1 +VE_GPIOR1: + .dw $ff06 + .db "GPIOR1" + .dw VE_HEAD + .set VE_HEAD=VE_GPIOR1 +XT_GPIOR1: + .dw PFA_DOVARIABLE +PFA_GPIOR1: + .dw $4A +; ( -- addr ) System Constant +; R( -- ) +; General Purpose IO Register 2 +VE_GPIOR2: + .dw $ff06 + .db "GPIOR2" + .dw VE_HEAD + .set VE_HEAD=VE_GPIOR2 +XT_GPIOR2: + .dw PFA_DOVARIABLE +PFA_GPIOR2: + .dw $4B +; ( -- addr ) System Constant +; R( -- ) +; MCU Control Register +VE_MCUCR: + .dw $ff05 + .db "MCUCR",0 + .dw VE_HEAD + .set VE_HEAD=VE_MCUCR +XT_MCUCR: + .dw PFA_DOVARIABLE +PFA_MCUCR: + .dw $55 +; ( -- addr ) System Constant +; R( -- ) +; MCU Status Register +VE_MCUSR: + .dw $ff05 + .db "MCUSR",0 + .dw VE_HEAD + .set VE_HEAD=VE_MCUSR +XT_MCUSR: + .dw PFA_DOVARIABLE +PFA_MCUSR: + .dw $54 +; ( -- addr ) System Constant +; R( -- ) +; Oscillator Sampling Interface Control and Status Register +VE_OSICSR: + .dw $ff06 + .db "OSICSR" + .dw VE_HEAD + .set VE_HEAD=VE_OSICSR +XT_OSICSR: + .dw PFA_DOVARIABLE +PFA_OSICSR: + .dw $37 +; ( -- addr ) System Constant +; R( -- ) +; Power Reduction Register 0 +VE_PRR0: + .dw $ff04 + .db "PRR0" + .dw VE_HEAD + .set VE_HEAD=VE_PRR0 +XT_PRR0: + .dw PFA_DOVARIABLE +PFA_PRR0: + .dw $64 +; ( -- addr ) System Constant +; R( -- ) +; Sleep Mode Control Register +VE_SMCR: + .dw $ff04 + .db "SMCR" + .dw VE_HEAD + .set VE_HEAD=VE_SMCR +XT_SMCR: + .dw PFA_DOVARIABLE +PFA_SMCR: + .dw $53 +; ( -- addr ) System Constant +; R( -- ) +; Stack Pointer High +VE_SPH: + .dw $ff03 + .db "SPH",0 + .dw VE_HEAD + .set VE_HEAD=VE_SPH +XT_SPH: + .dw PFA_DOVARIABLE +PFA_SPH: + .dw $5E +; ( -- addr ) System Constant +; R( -- ) +; Stack Pointer Low +VE_SPL: + .dw $ff03 + .db "SPL",0 + .dw VE_HEAD + .set VE_HEAD=VE_SPL +XT_SPL: + .dw PFA_DOVARIABLE +PFA_SPL: + .dw $5D +; ( -- addr ) System Constant +; R( -- ) +; Status Register +VE_SREG: + .dw $ff04 + .db "SREG" + .dw VE_HEAD + .set VE_HEAD=VE_SREG +XT_SREG: + .dw PFA_DOVARIABLE +PFA_SREG: + .dw $5F + +.endif + +; ******** +.if WANT_EEPROM == 1 +; ******** +; ( -- addr ) System Constant +; R( -- ) +; EEPROM Read/Write Access +VE_EEAR: + .dw $ff04 + .db "EEAR" + .dw VE_HEAD + .set VE_HEAD=VE_EEAR +XT_EEAR: + .dw PFA_DOVARIABLE +PFA_EEAR: + .dw $41 +; ( -- addr ) System Constant +; R( -- ) +; EEPROM Control Register +VE_EECR: + .dw $ff04 + .db "EECR" + .dw VE_HEAD + .set VE_HEAD=VE_EECR +XT_EECR: + .dw PFA_DOVARIABLE +PFA_EECR: + .dw $3F +; ( -- addr ) System Constant +; R( -- ) +; EEPROM Data Register +VE_EEDR: + .dw $ff04 + .db "EEDR" + .dw VE_HEAD + .set VE_HEAD=VE_EEDR +XT_EEDR: + .dw PFA_DOVARIABLE +PFA_EEDR: + .dw $40 + +.endif + +; ******** +.if WANT_EXTERNAL_INTERRUPT == 1 +; ******** +; ( -- addr ) System Constant +; R( -- ) +; External Interrupt Control Register +VE_EICRA: + .dw $ff05 + .db "EICRA",0 + .dw VE_HEAD + .set VE_HEAD=VE_EICRA +XT_EICRA: + .dw PFA_DOVARIABLE +PFA_EICRA: + .dw $69 +; ( -- addr ) System Constant +; R( -- ) +; External Interrupt Flag Register +VE_EIFR: + .dw $ff04 + .db "EIFR" + .dw VE_HEAD + .set VE_HEAD=VE_EIFR +XT_EIFR: + .dw PFA_DOVARIABLE +PFA_EIFR: + .dw $3C +; ( -- addr ) System Constant +; R( -- ) +; External Interrupt Mask Register +VE_EIMSK: + .dw $ff05 + .db "EIMSK",0 + .dw VE_HEAD + .set VE_HEAD=VE_EIMSK +XT_EIMSK: + .dw PFA_DOVARIABLE +PFA_EIMSK: + .dw $3D + +.endif + +; ******** +.if WANT_FET == 1 +; ******** +; ( -- addr ) System Constant +; R( -- ) +; FET Control and Status Register +VE_FCSR: + .dw $ff04 + .db "FCSR" + .dw VE_HEAD + .set VE_HEAD=VE_FCSR +XT_FCSR: + .dw PFA_DOVARIABLE +PFA_FCSR: + .dw $F0 + +.endif + +; ******** +.if WANT_PORTA == 1 +; ******** +; ( -- addr ) System Constant +; R( -- ) +; Port A Data Direction Register +VE_DDRA: + .dw $ff04 + .db "DDRA" + .dw VE_HEAD + .set VE_HEAD=VE_DDRA +XT_DDRA: + .dw PFA_DOVARIABLE +PFA_DDRA: + .dw $21 +; ( -- addr ) System Constant +; R( -- ) +; Port A Input Pins +VE_PINA: + .dw $ff04 + .db "PINA" + .dw VE_HEAD + .set VE_HEAD=VE_PINA +XT_PINA: + .dw PFA_DOVARIABLE +PFA_PINA: + .dw $20 +; ( -- addr ) System Constant +; R( -- ) +; Port A Data Register +VE_PORTA: + .dw $ff05 + .db "PORTA",0 + .dw VE_HEAD + .set VE_HEAD=VE_PORTA +XT_PORTA: + .dw PFA_DOVARIABLE +PFA_PORTA: + .dw $22 + +.endif + +; ******** +.if WANT_PORTB == 1 +; ******** +; ( -- addr ) System Constant +; R( -- ) +; Data Direction Register, Port B +VE_DDRB: + .dw $ff04 + .db "DDRB" + .dw VE_HEAD + .set VE_HEAD=VE_DDRB +XT_DDRB: + .dw PFA_DOVARIABLE +PFA_DDRB: + .dw $24 +; ( -- addr ) System Constant +; R( -- ) +; Input Pins, Port B +VE_PINB: + .dw $ff04 + .db "PINB" + .dw VE_HEAD + .set VE_HEAD=VE_PINB +XT_PINB: + .dw PFA_DOVARIABLE +PFA_PINB: + .dw $23 +; ( -- addr ) System Constant +; R( -- ) +; Data Register, Port B +VE_PORTB: + .dw $ff05 + .db "PORTB",0 + .dw VE_HEAD + .set VE_HEAD=VE_PORTB +XT_PORTB: + .dw PFA_DOVARIABLE +PFA_PORTB: + .dw $25 + +.endif + +; ******** +.if WANT_PORTC == 1 +; ******** +; ( -- addr ) System Constant +; R( -- ) +; Port C Input Pins +VE_PINC: + .dw $ff04 + .db "PINC" + .dw VE_HEAD + .set VE_HEAD=VE_PINC +XT_PINC: + .dw PFA_DOVARIABLE +PFA_PINC: + .dw $26 +; ( -- addr ) System Constant +; R( -- ) +; Port C Data Register +VE_PORTC: + .dw $ff05 + .db "PORTC",0 + .dw VE_HEAD + .set VE_HEAD=VE_PORTC +XT_PORTC: + .dw PFA_DOVARIABLE +PFA_PORTC: + .dw $28 + +.endif + +; ******** +.if WANT_SPI == 1 +; ******** +; ( -- addr ) System Constant +; R( -- ) +; SPI Control Register +VE_SPCR: + .dw $ff04 + .db "SPCR" + .dw VE_HEAD + .set VE_HEAD=VE_SPCR +XT_SPCR: + .dw PFA_DOVARIABLE +PFA_SPCR: + .dw $4c +; ( -- addr ) System Constant +; R( -- ) +; SPI Data Register +VE_SPDR: + .dw $ff04 + .db "SPDR" + .dw VE_HEAD + .set VE_HEAD=VE_SPDR +XT_SPDR: + .dw PFA_DOVARIABLE +PFA_SPDR: + .dw $4e +; ( -- addr ) System Constant +; R( -- ) +; SPI Status Register +VE_SPSR: + .dw $ff04 + .db "SPSR" + .dw VE_HEAD + .set VE_HEAD=VE_SPSR +XT_SPSR: + .dw PFA_DOVARIABLE +PFA_SPSR: + .dw $4d + +.endif + +; ******** +.if WANT_TIMER_COUNTER_0 == 1 +; ******** +; ( -- addr ) System Constant +; R( -- ) +; Output compare Register A +VE_OCR0A: + .dw $ff05 + .db "OCR0A",0 + .dw VE_HEAD + .set VE_HEAD=VE_OCR0A +XT_OCR0A: + .dw PFA_DOVARIABLE +PFA_OCR0A: + .dw $48 +; ( -- addr ) System Constant +; R( -- ) +; Output compare Register B +VE_OCR0B: + .dw $ff05 + .db "OCR0B",0 + .dw VE_HEAD + .set VE_HEAD=VE_OCR0B +XT_OCR0B: + .dw PFA_DOVARIABLE +PFA_OCR0B: + .dw $49 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter0 Control Register +VE_TCCR0A: + .dw $ff06 + .db "TCCR0A" + .dw VE_HEAD + .set VE_HEAD=VE_TCCR0A +XT_TCCR0A: + .dw PFA_DOVARIABLE +PFA_TCCR0A: + .dw $44 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter0 Control Register +VE_TCCR0B: + .dw $ff06 + .db "TCCR0B" + .dw VE_HEAD + .set VE_HEAD=VE_TCCR0B +XT_TCCR0B: + .dw PFA_DOVARIABLE +PFA_TCCR0B: + .dw $45 +; ( -- addr ) System Constant +; R( -- ) +; Timer Counter 0 High Byte +VE_TCNT0H: + .dw $ff06 + .db "TCNT0H" + .dw VE_HEAD + .set VE_HEAD=VE_TCNT0H +XT_TCNT0H: + .dw PFA_DOVARIABLE +PFA_TCNT0H: + .dw $47 +; ( -- addr ) System Constant +; R( -- ) +; Timer Counter 0 Low Byte +VE_TCNT0L: + .dw $ff06 + .db "TCNT0L" + .dw VE_HEAD + .set VE_HEAD=VE_TCNT0L +XT_TCNT0L: + .dw PFA_DOVARIABLE +PFA_TCNT0L: + .dw $46 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter Interrupt Flag register +VE_TIFR0: + .dw $ff05 + .db "TIFR0",0 + .dw VE_HEAD + .set VE_HEAD=VE_TIFR0 +XT_TIFR0: + .dw PFA_DOVARIABLE +PFA_TIFR0: + .dw $35 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter Interrupt Mask Register +VE_TIMSK0: + .dw $ff06 + .db "TIMSK0" + .dw VE_HEAD + .set VE_HEAD=VE_TIMSK0 +XT_TIMSK0: + .dw PFA_DOVARIABLE +PFA_TIMSK0: + .dw $6E + +.endif + +; ******** +.if WANT_TIMER_COUNTER_1 == 1 +; ******** +; ( -- addr ) System Constant +; R( -- ) +; General Timer/Counter Control Register +VE_GTCCR: + .dw $ff05 + .db "GTCCR",0 + .dw VE_HEAD + .set VE_HEAD=VE_GTCCR +XT_GTCCR: + .dw PFA_DOVARIABLE +PFA_GTCCR: + .dw $43 +; ( -- addr ) System Constant +; R( -- ) +; Output Compare Register 1A +VE_OCR1A: + .dw $ff05 + .db "OCR1A",0 + .dw VE_HEAD + .set VE_HEAD=VE_OCR1A +XT_OCR1A: + .dw PFA_DOVARIABLE +PFA_OCR1A: + .dw $88 +; ( -- addr ) System Constant +; R( -- ) +; Output Compare Register B +VE_OCR1B: + .dw $ff05 + .db "OCR1B",0 + .dw VE_HEAD + .set VE_HEAD=VE_OCR1B +XT_OCR1B: + .dw PFA_DOVARIABLE +PFA_OCR1B: + .dw $89 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter 1 Control Register A +VE_TCCR1A: + .dw $ff06 + .db "TCCR1A" + .dw VE_HEAD + .set VE_HEAD=VE_TCCR1A +XT_TCCR1A: + .dw PFA_DOVARIABLE +PFA_TCCR1A: + .dw $80 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter1 Control Register B +VE_TCCR1B: + .dw $ff06 + .db "TCCR1B" + .dw VE_HEAD + .set VE_HEAD=VE_TCCR1B +XT_TCCR1B: + .dw PFA_DOVARIABLE +PFA_TCCR1B: + .dw $81 +; ( -- addr ) System Constant +; R( -- ) +; Timer Counter 1 High Byte +VE_TCNT1H: + .dw $ff06 + .db "TCNT1H" + .dw VE_HEAD + .set VE_HEAD=VE_TCNT1H +XT_TCNT1H: + .dw PFA_DOVARIABLE +PFA_TCNT1H: + .dw $85 +; ( -- addr ) System Constant +; R( -- ) +; Timer Counter 1 Low Byte +VE_TCNT1L: + .dw $ff06 + .db "TCNT1L" + .dw VE_HEAD + .set VE_HEAD=VE_TCNT1L +XT_TCNT1L: + .dw PFA_DOVARIABLE +PFA_TCNT1L: + .dw $84 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter Interrupt Flag register +VE_TIFR1: + .dw $ff05 + .db "TIFR1",0 + .dw VE_HEAD + .set VE_HEAD=VE_TIFR1 +XT_TIFR1: + .dw PFA_DOVARIABLE +PFA_TIFR1: + .dw $36 +; ( -- addr ) System Constant +; R( -- ) +; Timer/Counter Interrupt Mask Register +VE_TIMSK1: + .dw $ff06 + .db "TIMSK1" + .dw VE_HEAD + .set VE_HEAD=VE_TIMSK1 +XT_TIMSK1: + .dw PFA_DOVARIABLE +PFA_TIMSK1: + .dw $6F + +.endif + +; ******** +.if WANT_VOLTAGE_REGULATOR == 1 +; ******** +; ( -- addr ) System Constant +; R( -- ) +; Regulator Operating Condition Register +VE_ROCR: + .dw $ff04 + .db "ROCR" + .dw VE_HEAD + .set VE_HEAD=VE_ROCR +XT_ROCR: + .dw PFA_DOVARIABLE +PFA_ROCR: + .dw $C8 + +.endif + +; ******** +.if WANT_WATCHDOG == 1 +; ******** +; ( -- addr ) System Constant +; R( -- ) +; Watchdog Timer Control Register +VE_WDTCSR: + .dw $ff06 + .db "WDTCSR" + .dw VE_HEAD + .set VE_HEAD=VE_WDTCSR +XT_WDTCSR: + .dw PFA_DOVARIABLE +PFA_WDTCSR: + .dw $60 + +.endif diff --git a/amforth-6.5/avr8/devices/atmega8hva/device.py b/amforth-6.5/avr8/devices/atmega8hva/device.py new file mode 100644 index 0000000..d16cdad --- /dev/null +++ b/amforth-6.5/avr8/devices/atmega8hva/device.py @@ -0,0 +1,104 @@ +# Partname: ATmega8HVA +# Built using part description XML file version 1 +# generated automatically, do not edit +MCUREGS = { + 'VADCH': '$79', + 'VADCL': '$78', + 'VADCSR': '$7A', + 'VADMUX': '$7C', + 'BGCCR': '$D0', + 'BGCRR': '$D1', + 'BPCHCD': '$F9', + 'BPCOCD': '$F7', + 'BPCR': '$FD', + 'BPDHCD': '$F8', + 'BPDOCD': '$F6', + 'BPHCTR': '$FC', + 'BPIFR': '$F3', + 'BPIMSK': '$F2', + 'BPOCTR': '$FB', + 'BPPLR': '$FE', + 'BPSCD': '$F5', + 'BPSCTR': '$FA', + 'SPMCSR': '$57', + 'CADAC0': '$E0', + 'CADAC1': '$E1', + 'CADAC2': '$E2', + 'CADAC3': '$E3', + 'CADCSRA': '$E4', + 'CADCSRB': '$E5', + 'CADICH': '$E9', + 'CADICL': '$E8', + 'CADRC': '$E6', + 'CLKPR': '$61', + 'DIDR0': '$7E', + 'FOSCCAL': '$66', + 'GPIOR0': '$3E', + 'GPIOR1': '$4A', + 'GPIOR2': '$4B', + 'MCUCR': '$55', + 'MCUSR': '$54', + 'OSICSR': '$37', + 'PRR0': '$64', + 'SMCR': '$53', + 'SPH': '$5E', + 'SPL': '$5D', + 'SREG': '$5F', + 'EEAR': '$41', + 'EECR': '$3F', + 'EEDR': '$40', + 'EICRA': '$69', + 'EIFR': '$3C', + 'EIMSK': '$3D', + 'FCSR': '$F0', + 'DDRA': '$21', + 'PINA': '$20', + 'PORTA': '$22', + 'DDRB': '$24', + 'PINB': '$23', + 'PORTB': '$25', + 'PINC': '$26', + 'PORTC': '$28', + 'SPCR': '$4c', + 'SPDR': '$4e', + 'SPSR': '$4d', + 'OCR0A': '$48', + 'OCR0B': '$49', + 'TCCR0A': '$44', + 'TCCR0B': '$45', + 'TCNT0H': '$47', + 'TCNT0L': '$46', + 'TIFR0': '$35', + 'TIMSK0': '$6E', + 'GTCCR': '$43', + 'OCR1A': '$88', + 'OCR1B': '$89', + 'TCCR1A': '$80', + 'TCCR1B': '$81', + 'TCNT1H': '$85', + 'TCNT1L': '$84', + 'TIFR1': '$36', + 'TIMSK1': '$6F', + 'ROCR': '$C8', + 'WDTCSR': '$60', + 'BPINTAddr': '$0001', + 'VREGMONAddr': '$0002', + 'INT0Addr': '$0003', + 'INT1Addr': '$0004', + 'INT2Addr': '$0005', + 'WDTAddr': '$0006', + 'TIMER1_ICAddr': '$0007', + 'TIMER1_COMPAAddr': '$0008', + 'TIMER1_COMPBAddr': '$0009', + 'TIMER1_OVFAddr': '$000A', + 'TIMER0_ICAddr': '$000B', + 'TIMER0_COMPAAddr': '$000C', + 'TIMER0_COMPBAddr': '$000D', + 'TIMER0_OVFAddr': '$000E', + 'SPI;STCAddr': '$000F', + 'VADCAddr': '$0010', + 'CCADC_CONVAddr': '$0011', + 'CCADC_REG_CURAddr': '$0012', + 'CCADC_ACCAddr': '$0013', + 'EE_READYAddr': '$014' +} \ No newline at end of file -- cgit v1.2.3