From 67d25d837ac55f28a366c0a3b262e439a6e75fc3 Mon Sep 17 00:00:00 2001 From: Dimitri Sokolyuk Date: Sat, 19 Aug 2017 12:15:28 +0200 Subject: Add AmForth --- amforth-6.5/msp430/devices/msp430f5529/device.asm | 16 + amforth-6.5/msp430/devices/msp430f5529/drivers.asm | 3 + amforth-6.5/msp430/devices/msp430f5529/init.asm | 3 + .../msp430/devices/msp430f5529/msp430f5529.inc | 4371 ++++++++++++++++++++ .../msp430/devices/msp430f5529/words/cold.asm | 41 + .../devices/msp430f5529/words/env-mcu-info.asm | 10 + .../devices/msp430f5529/words/usart-init.asm | 16 + amforth-6.5/msp430/devices/msp430fr5969/device.asm | 16 + .../msp430/devices/msp430fr5969/drivers.asm | 3 + amforth-6.5/msp430/devices/msp430fr5969/init.asm | 4 + .../msp430/devices/msp430fr5969/msp430fr5969.inc | 3908 +++++++++++++++++ .../msp430/devices/msp430fr5969/words/cold.asm | 30 + .../devices/msp430fr5969/words/env-mcu-info.asm | 11 + .../devices/msp430fr5969/words/usart-init.asm | 25 + amforth-6.5/msp430/devices/msp430g2553/device.asm | 36 + amforth-6.5/msp430/devices/msp430g2553/device.py | 16 + amforth-6.5/msp430/devices/msp430g2553/drivers.asm | 3 + amforth-6.5/msp430/devices/msp430g2553/init.asm | 3 + .../msp430/devices/msp430g2553/msp430g2553.inc | 851 ++++ .../msp430/devices/msp430g2553/words/cold.asm | 41 + .../devices/msp430g2553/words/env-mcu-info.asm | 10 + .../devices/msp430g2553/words/usart-init.asm | 13 + 22 files changed, 9430 insertions(+) create mode 100644 amforth-6.5/msp430/devices/msp430f5529/device.asm create mode 100644 amforth-6.5/msp430/devices/msp430f5529/drivers.asm create mode 100644 amforth-6.5/msp430/devices/msp430f5529/init.asm create mode 100644 amforth-6.5/msp430/devices/msp430f5529/msp430f5529.inc create mode 100644 amforth-6.5/msp430/devices/msp430f5529/words/cold.asm create mode 100644 amforth-6.5/msp430/devices/msp430f5529/words/env-mcu-info.asm create mode 100644 amforth-6.5/msp430/devices/msp430f5529/words/usart-init.asm create mode 100644 amforth-6.5/msp430/devices/msp430fr5969/device.asm create mode 100644 amforth-6.5/msp430/devices/msp430fr5969/drivers.asm create mode 100644 amforth-6.5/msp430/devices/msp430fr5969/init.asm create mode 100644 amforth-6.5/msp430/devices/msp430fr5969/msp430fr5969.inc create mode 100644 amforth-6.5/msp430/devices/msp430fr5969/words/cold.asm create mode 100644 amforth-6.5/msp430/devices/msp430fr5969/words/env-mcu-info.asm create mode 100644 amforth-6.5/msp430/devices/msp430fr5969/words/usart-init.asm create mode 100644 amforth-6.5/msp430/devices/msp430g2553/device.asm create mode 100644 amforth-6.5/msp430/devices/msp430g2553/device.py create mode 100644 amforth-6.5/msp430/devices/msp430g2553/drivers.asm create mode 100644 amforth-6.5/msp430/devices/msp430g2553/init.asm create mode 100644 amforth-6.5/msp430/devices/msp430g2553/msp430g2553.inc create mode 100644 amforth-6.5/msp430/devices/msp430g2553/words/cold.asm create mode 100644 amforth-6.5/msp430/devices/msp430g2553/words/env-mcu-info.asm create mode 100644 amforth-6.5/msp430/devices/msp430g2553/words/usart-init.asm (limited to 'amforth-6.5/msp430/devices') diff --git a/amforth-6.5/msp430/devices/msp430f5529/device.asm b/amforth-6.5/msp430/devices/msp430f5529/device.asm new file mode 100644 index 0000000..22112b1 --- /dev/null +++ b/amforth-6.5/msp430/devices/msp430f5529/device.asm @@ -0,0 +1,16 @@ +; device specific +.include "msp430f5529.inc" ; MCU-specific register equates + +RAMSTART equ 2400h +RAMEND equ 4400h +INFOSTART equ 01800h +INFOEND equ 0198Fh ; do not allow config flash to be erased +FLASHSTART equ 04400h +FLASHEND equ 0DFFFh +MAINSEG equ 512 +INFOSEG equ 64 +INFO_SIZE equ 128 ; bytes + +.org 0FFFEh + + DC16 reset ; FFFE - Reset diff --git a/amforth-6.5/msp430/devices/msp430f5529/drivers.asm b/amforth-6.5/msp430/devices/msp430f5529/drivers.asm new file mode 100644 index 0000000..2793ccf --- /dev/null +++ b/amforth-6.5/msp430/devices/msp430f5529/drivers.asm @@ -0,0 +1,3 @@ + +.include "drivers/flash.inc" + diff --git a/amforth-6.5/msp430/devices/msp430f5529/init.asm b/amforth-6.5/msp430/devices/msp430f5529/init.asm new file mode 100644 index 0000000..3ce33c3 --- /dev/null +++ b/amforth-6.5/msp430/devices/msp430f5529/init.asm @@ -0,0 +1,3 @@ + +mcu_name: + .db 11,"MSP430F5529" diff --git a/amforth-6.5/msp430/devices/msp430f5529/msp430f5529.inc b/amforth-6.5/msp430/devices/msp430f5529/msp430f5529.inc new file mode 100644 index 0000000..610358a --- /dev/null +++ b/amforth-6.5/msp430/devices/msp430f5529/msp430f5529.inc @@ -0,0 +1,4371 @@ +/* ============================================================================ */ +/* Copyright (c) 2015, Texas Instruments Incorporated */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following conditions */ +/* are met: */ +/* */ +/* * Redistributions of source code must retain the above copyright */ +/* notice, this list of conditions and the following disclaimer. */ +/* */ +/* * Redistributions in binary form must reproduce the above copyright */ +/* notice, this list of conditions and the following disclaimer in the */ +/* documentation and/or other materials provided with the distribution. */ +/* */ +/* * Neither the name of Texas Instruments Incorporated nor the names of */ +/* its contributors may be used to endorse or promote products derived */ +/* from this software without specific prior written permission. */ +/* */ +/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" */ +/* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, */ +/* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR */ +/* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR */ +/* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, */ +/* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, */ +/* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; */ +/* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, */ +/* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR */ +/* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ============================================================================ */ + +/******************************************************************** +* +* Standard register and bit definitions for the Texas Instruments +* MSP430 microcontroller. +* +* This file supports assembler and C development for +* MSP430F5529 devices. +* +* Texas Instruments, Version 1.4 +* +* Rev. 1.0, Setup +* Rev. 1.1, Fixed Error in DMA Trigger Definitons +* Rev. 1.2, fixed SYSUNIV_BUSIFG definition +* fixed wrong bit definition in PM5CTL0 (LOCKLPM5) +* Rev. 1.3, Changed access type of DMAxSZ registers to word only +* Rev. 1.4 Changed access type of TimerA/B registers to word only +* +********************************************************************/ + +/************************************************************ +* STANDARD BITS +************************************************************/ + +#define BIT0 (0x0001) +#define BIT1 (0x0002) +#define BIT2 (0x0004) +#define BIT3 (0x0008) +#define BIT4 (0x0010) +#define BIT5 (0x0020) +#define BIT6 (0x0040) +#define BIT7 (0x0080) +#define BIT8 (0x0100) +#define BIT9 (0x0200) +#define BITA (0x0400) +#define BITB (0x0800) +#define BITC (0x1000) +#define BITD (0x2000) +#define BITE (0x4000) +#define BITF (0x8000) + +/************************************************************ +* STATUS REGISTER BITS +************************************************************/ + +#define C (0x0001) +#define Z (0x0002) +#define N (0x0004) +#define V (0x0100) +#define GIE (0x0008) +#define CPUOFF (0x0010) +#define OSCOFF (0x0020) +#define SCG0 (0x0040) +#define SCG1 (0x0080) + +/* Low Power Modes coded with Bits 4-7 in SR */ + +#define LPM0 (CPUOFF) +#define LPM1 (SCG0+CPUOFF) +#define LPM2 (SCG1+CPUOFF) +#define LPM3 (SCG1+SCG0+CPUOFF) +#define LPM4 (SCG1+SCG0+OSCOFF+CPUOFF) +/* End #defines for assembler */ + +/************************************************************ +* CPU +************************************************************/ + +/************************************************************ +* PERIPHERAL FILE MAP +************************************************************/ + + +/************************************************************ +* ADC12 PLUS +************************************************************/ + +#define ADC12CTL0 0x0700 /* ADC12+ Control 0 */ +#define ADC12CTL1 0x0702 /* ADC12+ Control 1 */ +#define ADC12CTL2 0x0704 /* ADC12+ Control 2 */ +#define ADC12IFG 0x070A /* ADC12+ Interrupt Flag */ +#define ADC12IE 0x070C /* ADC12+ Interrupt Enable */ +#define ADC12IV 0x070E /* ADC12+ Interrupt Vector Word */ +#define ADC12MEM0 0x0720 /* ADC12 Conversion Memory 0 */ +#define ADC12MEM1 0x0722 /* ADC12 Conversion Memory 1 */ +#define ADC12MEM2 0x0724 /* ADC12 Conversion Memory 2 */ +#define ADC12MEM3 0x0726 /* ADC12 Conversion Memory 3 */ +#define ADC12MEM4 0x0728 /* ADC12 Conversion Memory 4 */ +#define ADC12MEM5 0x072A /* ADC12 Conversion Memory 5 */ +#define ADC12MEM6 0x072C /* ADC12 Conversion Memory 6 */ +#define ADC12MEM7 0x072E /* ADC12 Conversion Memory 7 */ +#define ADC12MEM8 0x0730 /* ADC12 Conversion Memory 8 */ +#define ADC12MEM9 0x0732 /* ADC12 Conversion Memory 9 */ +#define ADC12MEM10 0x0734 /* ADC12 Conversion Memory 10 */ +#define ADC12MEM11 0x0736 /* ADC12 Conversion Memory 11 */ +#define ADC12MEM12 0x0738 /* ADC12 Conversion Memory 12 */ +#define ADC12MEM13 0x073A /* ADC12 Conversion Memory 13 */ +#define ADC12MEM14 0x073C /* ADC12 Conversion Memory 14 */ +#define ADC12MEM15 0x073E /* ADC12 Conversion Memory 15 */ +#define ADC12MEM ADC12MEM0 /* ADC12 Conversion Memory (for assembler) */ + +#define ADC12MCTL0 0x0710 /* ADC12 Memory Control 0 */ +#define ADC12MCTL1 0x0711 /* ADC12 Memory Control 1 */ +#define ADC12MCTL2 0x0712 /* ADC12 Memory Control 2 */ +#define ADC12MCTL3 0x0713 /* ADC12 Memory Control 3 */ +#define ADC12MCTL4 0x0714 /* ADC12 Memory Control 4 */ +#define ADC12MCTL5 0x0715 /* ADC12 Memory Control 5 */ +#define ADC12MCTL6 0x0716 /* ADC12 Memory Control 6 */ +#define ADC12MCTL7 0x0717 /* ADC12 Memory Control 7 */ +#define ADC12MCTL8 0x0718 /* ADC12 Memory Control 8 */ +#define ADC12MCTL9 0x0719 /* ADC12 Memory Control 9 */ +#define ADC12MCTL10 0x071A /* ADC12 Memory Control 10 */ +#define ADC12MCTL11 0x071B /* ADC12 Memory Control 11 */ +#define ADC12MCTL12 0x071C /* ADC12 Memory Control 12 */ +#define ADC12MCTL13 0x071D /* ADC12 Memory Control 13 */ +#define ADC12MCTL14 0x071E /* ADC12 Memory Control 14 */ +#define ADC12MCTL15 0x071F /* ADC12 Memory Control 15 */ +#define ADC12MCTL ADC12MCTL0 /* ADC12 Memory Control (for assembler) */ + +/* ADC12CTL0 Control Bits */ +#define ADC12SC (0x0001) /* ADC12 Start Conversion */ +#define ADC12ENC (0x0002) /* ADC12 Enable Conversion */ +#define ADC12TOVIE (0x0004) /* ADC12 Timer Overflow interrupt enable */ +#define ADC12OVIE (0x0008) /* ADC12 Overflow interrupt enable */ +#define ADC12ON (0x0010) /* ADC12 On/enable */ +#define ADC12REFON (0x0020) /* ADC12 Reference on */ +#define ADC12REF2_5V (0x0040) /* ADC12 Ref 0:1.5V / 1:2.5V */ +#define ADC12MSC (0x0080) /* ADC12 Multiple SampleConversion */ +#define ADC12SHT00 (0x0100) /* ADC12 Sample Hold 0 Select Bit: 0 */ +#define ADC12SHT01 (0x0200) /* ADC12 Sample Hold 0 Select Bit: 1 */ +#define ADC12SHT02 (0x0400) /* ADC12 Sample Hold 0 Select Bit: 2 */ +#define ADC12SHT03 (0x0800) /* ADC12 Sample Hold 0 Select Bit: 3 */ +#define ADC12SHT10 (0x1000) /* ADC12 Sample Hold 1 Select Bit: 0 */ +#define ADC12SHT11 (0x2000) /* ADC12 Sample Hold 1 Select Bit: 1 */ +#define ADC12SHT12 (0x4000) /* ADC12 Sample Hold 1 Select Bit: 2 */ +#define ADC12SHT13 (0x8000) /* ADC12 Sample Hold 1 Select Bit: 3 */ + +/* ADC12CTL0 Control Bits */ +#define ADC12SC_L (0x0001) /* ADC12 Start Conversion */ +#define ADC12ENC_L (0x0002) /* ADC12 Enable Conversion */ +#define ADC12TOVIE_L (0x0004) /* ADC12 Timer Overflow interrupt enable */ +#define ADC12OVIE_L (0x0008) /* ADC12 Overflow interrupt enable */ +#define ADC12ON_L (0x0010) /* ADC12 On/enable */ +#define ADC12REFON_L (0x0020) /* ADC12 Reference on */ +#define ADC12REF2_5V_L (0x0040) /* ADC12 Ref 0:1.5V / 1:2.5V */ +#define ADC12MSC_L (0x0080) /* ADC12 Multiple SampleConversion */ + +/* ADC12CTL0 Control Bits */ +#define ADC12SHT00_H (0x0001) /* ADC12 Sample Hold 0 Select Bit: 0 */ +#define ADC12SHT01_H (0x0002) /* ADC12 Sample Hold 0 Select Bit: 1 */ +#define ADC12SHT02_H (0x0004) /* ADC12 Sample Hold 0 Select Bit: 2 */ +#define ADC12SHT03_H (0x0008) /* ADC12 Sample Hold 0 Select Bit: 3 */ +#define ADC12SHT10_H (0x0010) /* ADC12 Sample Hold 1 Select Bit: 0 */ +#define ADC12SHT11_H (0x0020) /* ADC12 Sample Hold 1 Select Bit: 1 */ +#define ADC12SHT12_H (0x0040) /* ADC12 Sample Hold 1 Select Bit: 2 */ +#define ADC12SHT13_H (0x0080) /* ADC12 Sample Hold 1 Select Bit: 3 */ + +#define ADC12SHT0_0 (0x0000) /* ADC12 Sample Hold 0 Select Bit: 0 */ +#define ADC12SHT0_1 (0x0100) /* ADC12 Sample Hold 0 Select Bit: 1 */ +#define ADC12SHT0_2 (0x0200) /* ADC12 Sample Hold 0 Select Bit: 2 */ +#define ADC12SHT0_3 (0x0300) /* ADC12 Sample Hold 0 Select Bit: 3 */ +#define ADC12SHT0_4 (0x0400) /* ADC12 Sample Hold 0 Select Bit: 4 */ +#define ADC12SHT0_5 (0x0500) /* ADC12 Sample Hold 0 Select Bit: 5 */ +#define ADC12SHT0_6 (0x0600) /* ADC12 Sample Hold 0 Select Bit: 6 */ +#define ADC12SHT0_7 (0x0700) /* ADC12 Sample Hold 0 Select Bit: 7 */ +#define ADC12SHT0_8 (0x0800) /* ADC12 Sample Hold 0 Select Bit: 8 */ +#define ADC12SHT0_9 (0x0900) /* ADC12 Sample Hold 0 Select Bit: 9 */ +#define ADC12SHT0_10 (0x0A00) /* ADC12 Sample Hold 0 Select Bit: 10 */ +#define ADC12SHT0_11 (0x0B00) /* ADC12 Sample Hold 0 Select Bit: 11 */ +#define ADC12SHT0_12 (0x0C00) /* ADC12 Sample Hold 0 Select Bit: 12 */ +#define ADC12SHT0_13 (0x0D00) /* ADC12 Sample Hold 0 Select Bit: 13 */ +#define ADC12SHT0_14 (0x0E00) /* ADC12 Sample Hold 0 Select Bit: 14 */ +#define ADC12SHT0_15 (0x0F00) /* ADC12 Sample Hold 0 Select Bit: 15 */ + +#define ADC12SHT1_0 (0x0000) /* ADC12 Sample Hold 1 Select Bit: 0 */ +#define ADC12SHT1_1 (0x1000) /* ADC12 Sample Hold 1 Select Bit: 1 */ +#define ADC12SHT1_2 (0x2000) /* ADC12 Sample Hold 1 Select Bit: 2 */ +#define ADC12SHT1_3 (0x3000) /* ADC12 Sample Hold 1 Select Bit: 3 */ +#define ADC12SHT1_4 (0x4000) /* ADC12 Sample Hold 1 Select Bit: 4 */ +#define ADC12SHT1_5 (0x5000) /* ADC12 Sample Hold 1 Select Bit: 5 */ +#define ADC12SHT1_6 (0x6000) /* ADC12 Sample Hold 1 Select Bit: 6 */ +#define ADC12SHT1_7 (0x7000) /* ADC12 Sample Hold 1 Select Bit: 7 */ +#define ADC12SHT1_8 (0x8000) /* ADC12 Sample Hold 1 Select Bit: 8 */ +#define ADC12SHT1_9 (0x9000) /* ADC12 Sample Hold 1 Select Bit: 9 */ +#define ADC12SHT1_10 (0xA000) /* ADC12 Sample Hold 1 Select Bit: 10 */ +#define ADC12SHT1_11 (0xB000) /* ADC12 Sample Hold 1 Select Bit: 11 */ +#define ADC12SHT1_12 (0xC000) /* ADC12 Sample Hold 1 Select Bit: 12 */ +#define ADC12SHT1_13 (0xD000) /* ADC12 Sample Hold 1 Select Bit: 13 */ +#define ADC12SHT1_14 (0xE000) /* ADC12 Sample Hold 1 Select Bit: 14 */ +#define ADC12SHT1_15 (0xF000) /* ADC12 Sample Hold 1 Select Bit: 15 */ + +/* ADC12CTL1 Control Bits */ +#define ADC12BUSY (0x0001) /* ADC12 Busy */ +#define ADC12CONSEQ0 (0x0002) /* ADC12 Conversion Sequence Select Bit: 0 */ +#define ADC12CONSEQ1 (0x0004) /* ADC12 Conversion Sequence Select Bit: 1 */ +#define ADC12SSEL0 (0x0008) /* ADC12 Clock Source Select Bit: 0 */ +#define ADC12SSEL1 (0x0010) /* ADC12 Clock Source Select Bit: 1 */ +#define ADC12DIV0 (0x0020) /* ADC12 Clock Divider Select Bit: 0 */ +#define ADC12DIV1 (0x0040) /* ADC12 Clock Divider Select Bit: 1 */ +#define ADC12DIV2 (0x0080) /* ADC12 Clock Divider Select Bit: 2 */ +#define ADC12ISSH (0x0100) /* ADC12 Invert Sample Hold Signal */ +#define ADC12SHP (0x0200) /* ADC12 Sample/Hold Pulse Mode */ +#define ADC12SHS0 (0x0400) /* ADC12 Sample/Hold Source Bit: 0 */ +#define ADC12SHS1 (0x0800) /* ADC12 Sample/Hold Source Bit: 1 */ +#define ADC12CSTARTADD0 (0x1000) /* ADC12 Conversion Start Address Bit: 0 */ +#define ADC12CSTARTADD1 (0x2000) /* ADC12 Conversion Start Address Bit: 1 */ +#define ADC12CSTARTADD2 (0x4000) /* ADC12 Conversion Start Address Bit: 2 */ +#define ADC12CSTARTADD3 (0x8000) /* ADC12 Conversion Start Address Bit: 3 */ + +/* ADC12CTL1 Control Bits */ +#define ADC12BUSY_L (0x0001) /* ADC12 Busy */ +#define ADC12CONSEQ0_L (0x0002) /* ADC12 Conversion Sequence Select Bit: 0 */ +#define ADC12CONSEQ1_L (0x0004) /* ADC12 Conversion Sequence Select Bit: 1 */ +#define ADC12SSEL0_L (0x0008) /* ADC12 Clock Source Select Bit: 0 */ +#define ADC12SSEL1_L (0x0010) /* ADC12 Clock Source Select Bit: 1 */ +#define ADC12DIV0_L (0x0020) /* ADC12 Clock Divider Select Bit: 0 */ +#define ADC12DIV1_L (0x0040) /* ADC12 Clock Divider Select Bit: 1 */ +#define ADC12DIV2_L (0x0080) /* ADC12 Clock Divider Select Bit: 2 */ + +/* ADC12CTL1 Control Bits */ +#define ADC12ISSH_H (0x0001) /* ADC12 Invert Sample Hold Signal */ +#define ADC12SHP_H (0x0002) /* ADC12 Sample/Hold Pulse Mode */ +#define ADC12SHS0_H (0x0004) /* ADC12 Sample/Hold Source Bit: 0 */ +#define ADC12SHS1_H (0x0008) /* ADC12 Sample/Hold Source Bit: 1 */ +#define ADC12CSTARTADD0_H (0x0010) /* ADC12 Conversion Start Address Bit: 0 */ +#define ADC12CSTARTADD1_H (0x0020) /* ADC12 Conversion Start Address Bit: 1 */ +#define ADC12CSTARTADD2_H (0x0040) /* ADC12 Conversion Start Address Bit: 2 */ +#define ADC12CSTARTADD3_H (0x0080) /* ADC12 Conversion Start Address Bit: 3 */ + +#define ADC12CONSEQ_0 (0x0000) /* ADC12 Conversion Sequence Select: 0 */ +#define ADC12CONSEQ_1 (0x0002) /* ADC12 Conversion Sequence Select: 1 */ +#define ADC12CONSEQ_2 (0x0004) /* ADC12 Conversion Sequence Select: 2 */ +#define ADC12CONSEQ_3 (0x0006) /* ADC12 Conversion Sequence Select: 3 */ + +#define ADC12SSEL_0 (0x0000) /* ADC12 Clock Source Select: 0 */ +#define ADC12SSEL_1 (0x0008) /* ADC12 Clock Source Select: 1 */ +#define ADC12SSEL_2 (0x0010) /* ADC12 Clock Source Select: 2 */ +#define ADC12SSEL_3 (0x0018) /* ADC12 Clock Source Select: 3 */ + +#define ADC12DIV_0 (0x0000) /* ADC12 Clock Divider Select: 0 */ +#define ADC12DIV_1 (0x0020) /* ADC12 Clock Divider Select: 1 */ +#define ADC12DIV_2 (0x0040) /* ADC12 Clock Divider Select: 2 */ +#define ADC12DIV_3 (0x0060) /* ADC12 Clock Divider Select: 3 */ +#define ADC12DIV_4 (0x0080) /* ADC12 Clock Divider Select: 4 */ +#define ADC12DIV_5 (0x00A0) /* ADC12 Clock Divider Select: 5 */ +#define ADC12DIV_6 (0x00C0) /* ADC12 Clock Divider Select: 6 */ +#define ADC12DIV_7 (0x00E0) /* ADC12 Clock Divider Select: 7 */ + +#define ADC12SHS_0 (0x0000) /* ADC12 Sample/Hold Source: 0 */ +#define ADC12SHS_1 (0x0400) /* ADC12 Sample/Hold Source: 1 */ +#define ADC12SHS_2 (0x0800) /* ADC12 Sample/Hold Source: 2 */ +#define ADC12SHS_3 (0x0C00) /* ADC12 Sample/Hold Source: 3 */ + +#define ADC12CSTARTADD_0 (0x0000) /* ADC12 Conversion Start Address: 0 */ +#define ADC12CSTARTADD_1 (0x1000) /* ADC12 Conversion Start Address: 1 */ +#define ADC12CSTARTADD_2 (0x2000) /* ADC12 Conversion Start Address: 2 */ +#define ADC12CSTARTADD_3 (0x3000) /* ADC12 Conversion Start Address: 3 */ +#define ADC12CSTARTADD_4 (0x4000) /* ADC12 Conversion Start Address: 4 */ +#define ADC12CSTARTADD_5 (0x5000) /* ADC12 Conversion Start Address: 5 */ +#define ADC12CSTARTADD_6 (0x6000) /* ADC12 Conversion Start Address: 6 */ +#define ADC12CSTARTADD_7 (0x7000) /* ADC12 Conversion Start Address: 7 */ +#define ADC12CSTARTADD_8 (0x8000) /* ADC12 Conversion Start Address: 8 */ +#define ADC12CSTARTADD_9 (0x9000) /* ADC12 Conversion Start Address: 9 */ +#define ADC12CSTARTADD_10 (0xA000) /* ADC12 Conversion Start Address: 10 */ +#define ADC12CSTARTADD_11 (0xB000) /* ADC12 Conversion Start Address: 11 */ +#define ADC12CSTARTADD_12 (0xC000) /* ADC12 Conversion Start Address: 12 */ +#define ADC12CSTARTADD_13 (0xD000) /* ADC12 Conversion Start Address: 13 */ +#define ADC12CSTARTADD_14 (0xE000) /* ADC12 Conversion Start Address: 14 */ +#define ADC12CSTARTADD_15 (0xF000) /* ADC12 Conversion Start Address: 15 */ + +/* ADC12CTL2 Control Bits */ +#define ADC12REFBURST (0x0001) /* ADC12+ Reference Burst */ +#define ADC12REFOUT (0x0002) /* ADC12+ Reference Out */ +#define ADC12SR (0x0004) /* ADC12+ Sampling Rate */ +#define ADC12DF (0x0008) /* ADC12+ Data Format */ +#define ADC12RES0 (0x0010) /* ADC12+ Resolution Bit: 0 */ +#define ADC12RES1 (0x0020) /* ADC12+ Resolution Bit: 1 */ +#define ADC12TCOFF (0x0080) /* ADC12+ Temperature Sensor Off */ +#define ADC12PDIV (0x0100) /* ADC12+ predivider 0:/1 1:/4 */ + +/* ADC12CTL2 Control Bits */ +#define ADC12REFBURST_L (0x0001) /* ADC12+ Reference Burst */ +#define ADC12REFOUT_L (0x0002) /* ADC12+ Reference Out */ +#define ADC12SR_L (0x0004) /* ADC12+ Sampling Rate */ +#define ADC12DF_L (0x0008) /* ADC12+ Data Format */ +#define ADC12RES0_L (0x0010) /* ADC12+ Resolution Bit: 0 */ +#define ADC12RES1_L (0x0020) /* ADC12+ Resolution Bit: 1 */ +#define ADC12TCOFF_L (0x0080) /* ADC12+ Temperature Sensor Off */ + +/* ADC12CTL2 Control Bits */ +#define ADC12PDIV_H (0x0001) /* ADC12+ predivider 0:/1 1:/4 */ + +#define ADC12RES_0 (0x0000) /* ADC12+ Resolution : 8 Bit */ +#define ADC12RES_1 (0x0010) /* ADC12+ Resolution : 10 Bit */ +#define ADC12RES_2 (0x0020) /* ADC12+ Resolution : 12 Bit */ +#define ADC12RES_3 (0x0030) /* ADC12+ Resolution : reserved */ + +/* ADC12MCTLx Control Bits */ +#define ADC12INCH0 (0x0001) /* ADC12 Input Channel Select Bit 0 */ +#define ADC12INCH1 (0x0002) /* ADC12 Input Channel Select Bit 1 */ +#define ADC12INCH2 (0x0004) /* ADC12 Input Channel Select Bit 2 */ +#define ADC12INCH3 (0x0008) /* ADC12 Input Channel Select Bit 3 */ +#define ADC12SREF0 (0x0010) /* ADC12 Select Reference Bit 0 */ +#define ADC12SREF1 (0x0020) /* ADC12 Select Reference Bit 1 */ +#define ADC12SREF2 (0x0040) /* ADC12 Select Reference Bit 2 */ +#define ADC12EOS (0x0080) /* ADC12 End of Sequence */ + +#define ADC12INCH_0 (0x0000) /* ADC12 Input Channel 0 */ +#define ADC12INCH_1 (0x0001) /* ADC12 Input Channel 1 */ +#define ADC12INCH_2 (0x0002) /* ADC12 Input Channel 2 */ +#define ADC12INCH_3 (0x0003) /* ADC12 Input Channel 3 */ +#define ADC12INCH_4 (0x0004) /* ADC12 Input Channel 4 */ +#define ADC12INCH_5 (0x0005) /* ADC12 Input Channel 5 */ +#define ADC12INCH_6 (0x0006) /* ADC12 Input Channel 6 */ +#define ADC12INCH_7 (0x0007) /* ADC12 Input Channel 7 */ +#define ADC12INCH_8 (0x0008) /* ADC12 Input Channel 8 */ +#define ADC12INCH_9 (0x0009) /* ADC12 Input Channel 9 */ +#define ADC12INCH_10 (0x000A) /* ADC12 Input Channel 10 */ +#define ADC12INCH_11 (0x000B) /* ADC12 Input Channel 11 */ +#define ADC12INCH_12 (0x000C) /* ADC12 Input Channel 12 */ +#define ADC12INCH_13 (0x000D) /* ADC12 Input Channel 13 */ +#define ADC12INCH_14 (0x000E) /* ADC12 Input Channel 14 */ +#define ADC12INCH_15 (0x000F) /* ADC12 Input Channel 15 */ + +#define ADC12SREF_0 (0x0000) /* ADC12 Select Reference 0 */ +#define ADC12SREF_1 (0x0010) /* ADC12 Select Reference 1 */ +#define ADC12SREF_2 (0x0020) /* ADC12 Select Reference 2 */ +#define ADC12SREF_3 (0x0030) /* ADC12 Select Reference 3 */ +#define ADC12SREF_4 (0x0040) /* ADC12 Select Reference 4 */ +#define ADC12SREF_5 (0x0050) /* ADC12 Select Reference 5 */ +#define ADC12SREF_6 (0x0060) /* ADC12 Select Reference 6 */ +#define ADC12SREF_7 (0x0070) /* ADC12 Select Reference 7 */ + +#define ADC12IE0 (0x0001) /* ADC12 Memory 0 Interrupt Enable */ +#define ADC12IE1 (0x0002) /* ADC12 Memory 1 Interrupt Enable */ +#define ADC12IE2 (0x0004) /* ADC12 Memory 2 Interrupt Enable */ +#define ADC12IE3 (0x0008) /* ADC12 Memory 3 Interrupt Enable */ +#define ADC12IE4 (0x0010) /* ADC12 Memory 4 Interrupt Enable */ +#define ADC12IE5 (0x0020) /* ADC12 Memory 5 Interrupt Enable */ +#define ADC12IE6 (0x0040) /* ADC12 Memory 6 Interrupt Enable */ +#define ADC12IE7 (0x0080) /* ADC12 Memory 7 Interrupt Enable */ +#define ADC12IE8 (0x0100) /* ADC12 Memory 8 Interrupt Enable */ +#define ADC12IE9 (0x0200) /* ADC12 Memory 9 Interrupt Enable */ +#define ADC12IE10 (0x0400) /* ADC12 Memory 10 Interrupt Enable */ +#define ADC12IE11 (0x0800) /* ADC12 Memory 11 Interrupt Enable */ +#define ADC12IE12 (0x1000) /* ADC12 Memory 12 Interrupt Enable */ +#define ADC12IE13 (0x2000) /* ADC12 Memory 13 Interrupt Enable */ +#define ADC12IE14 (0x4000) /* ADC12 Memory 14 Interrupt Enable */ +#define ADC12IE15 (0x8000) /* ADC12 Memory 15 Interrupt Enable */ + +#define ADC12IE0_L (0x0001) /* ADC12 Memory 0 Interrupt Enable */ +#define ADC12IE1_L (0x0002) /* ADC12 Memory 1 Interrupt Enable */ +#define ADC12IE2_L (0x0004) /* ADC12 Memory 2 Interrupt Enable */ +#define ADC12IE3_L (0x0008) /* ADC12 Memory 3 Interrupt Enable */ +#define ADC12IE4_L (0x0010) /* ADC12 Memory 4 Interrupt Enable */ +#define ADC12IE5_L (0x0020) /* ADC12 Memory 5 Interrupt Enable */ +#define ADC12IE6_L (0x0040) /* ADC12 Memory 6 Interrupt Enable */ +#define ADC12IE7_L (0x0080) /* ADC12 Memory 7 Interrupt Enable */ + +#define ADC12IE8_H (0x0001) /* ADC12 Memory 8 Interrupt Enable */ +#define ADC12IE9_H (0x0002) /* ADC12 Memory 9 Interrupt Enable */ +#define ADC12IE10_H (0x0004) /* ADC12 Memory 10 Interrupt Enable */ +#define ADC12IE11_H (0x0008) /* ADC12 Memory 11 Interrupt Enable */ +#define ADC12IE12_H (0x0010) /* ADC12 Memory 12 Interrupt Enable */ +#define ADC12IE13_H (0x0020) /* ADC12 Memory 13 Interrupt Enable */ +#define ADC12IE14_H (0x0040) /* ADC12 Memory 14 Interrupt Enable */ +#define ADC12IE15_H (0x0080) /* ADC12 Memory 15 Interrupt Enable */ + +#define ADC12IFG0 (0x0001) /* ADC12 Memory 0 Interrupt Flag */ +#define ADC12IFG1 (0x0002) /* ADC12 Memory 1 Interrupt Flag */ +#define ADC12IFG2 (0x0004) /* ADC12 Memory 2 Interrupt Flag */ +#define ADC12IFG3 (0x0008) /* ADC12 Memory 3 Interrupt Flag */ +#define ADC12IFG4 (0x0010) /* ADC12 Memory 4 Interrupt Flag */ +#define ADC12IFG5 (0x0020) /* ADC12 Memory 5 Interrupt Flag */ +#define ADC12IFG6 (0x0040) /* ADC12 Memory 6 Interrupt Flag */ +#define ADC12IFG7 (0x0080) /* ADC12 Memory 7 Interrupt Flag */ +#define ADC12IFG8 (0x0100) /* ADC12 Memory 8 Interrupt Flag */ +#define ADC12IFG9 (0x0200) /* ADC12 Memory 9 Interrupt Flag */ +#define ADC12IFG10 (0x0400) /* ADC12 Memory 10 Interrupt Flag */ +#define ADC12IFG11 (0x0800) /* ADC12 Memory 11 Interrupt Flag */ +#define ADC12IFG12 (0x1000) /* ADC12 Memory 12 Interrupt Flag */ +#define ADC12IFG13 (0x2000) /* ADC12 Memory 13 Interrupt Flag */ +#define ADC12IFG14 (0x4000) /* ADC12 Memory 14 Interrupt Flag */ +#define ADC12IFG15 (0x8000) /* ADC12 Memory 15 Interrupt Flag */ + +#define ADC12IFG0_L (0x0001) /* ADC12 Memory 0 Interrupt Flag */ +#define ADC12IFG1_L (0x0002) /* ADC12 Memory 1 Interrupt Flag */ +#define ADC12IFG2_L (0x0004) /* ADC12 Memory 2 Interrupt Flag */ +#define ADC12IFG3_L (0x0008) /* ADC12 Memory 3 Interrupt Flag */ +#define ADC12IFG4_L (0x0010) /* ADC12 Memory 4 Interrupt Flag */ +#define ADC12IFG5_L (0x0020) /* ADC12 Memory 5 Interrupt Flag */ +#define ADC12IFG6_L (0x0040) /* ADC12 Memory 6 Interrupt Flag */ +#define ADC12IFG7_L (0x0080) /* ADC12 Memory 7 Interrupt Flag */ + +#define ADC12IFG8_H (0x0001) /* ADC12 Memory 8 Interrupt Flag */ +#define ADC12IFG9_H (0x0002) /* ADC12 Memory 9 Interrupt Flag */ +#define ADC12IFG10_H (0x0004) /* ADC12 Memory 10 Interrupt Flag */ +#define ADC12IFG11_H (0x0008) /* ADC12 Memory 11 Interrupt Flag */ +#define ADC12IFG12_H (0x0010) /* ADC12 Memory 12 Interrupt Flag */ +#define ADC12IFG13_H (0x0020) /* ADC12 Memory 13 Interrupt Flag */ +#define ADC12IFG14_H (0x0040) /* ADC12 Memory 14 Interrupt Flag */ +#define ADC12IFG15_H (0x0080) /* ADC12 Memory 15 Interrupt Flag */ + +/* ADC12IV Definitions */ +#define ADC12IV_NONE (0x0000) /* No Interrupt pending */ +#define ADC12IV_ADC12OVIFG (0x0002) /* ADC12OVIFG */ +#define ADC12IV_ADC12TOVIFG (0x0004) /* ADC12TOVIFG */ +#define ADC12IV_ADC12IFG0 (0x0006) /* ADC12IFG0 */ +#define ADC12IV_ADC12IFG1 (0x0008) /* ADC12IFG1 */ +#define ADC12IV_ADC12IFG2 (0x000A) /* ADC12IFG2 */ +#define ADC12IV_ADC12IFG3 (0x000C) /* ADC12IFG3 */ +#define ADC12IV_ADC12IFG4 (0x000E) /* ADC12IFG4 */ +#define ADC12IV_ADC12IFG5 (0x0010) /* ADC12IFG5 */ +#define ADC12IV_ADC12IFG6 (0x0012) /* ADC12IFG6 */ +#define ADC12IV_ADC12IFG7 (0x0014) /* ADC12IFG7 */ +#define ADC12IV_ADC12IFG8 (0x0016) /* ADC12IFG8 */ +#define ADC12IV_ADC12IFG9 (0x0018) /* ADC12IFG9 */ +#define ADC12IV_ADC12IFG10 (0x001A) /* ADC12IFG10 */ +#define ADC12IV_ADC12IFG11 (0x001C) /* ADC12IFG11 */ +#define ADC12IV_ADC12IFG12 (0x001E) /* ADC12IFG12 */ +#define ADC12IV_ADC12IFG13 (0x0020) /* ADC12IFG13 */ +#define ADC12IV_ADC12IFG14 (0x0022) /* ADC12IFG14 */ +#define ADC12IV_ADC12IFG15 (0x0024) /* ADC12IFG15 */ + +/************************************************************ +* Comparator B +************************************************************/ +#define __MSP430_HAS_COMPB_ /* Definition to show that Module is available */ +#define __MSP430_BASEADDRESS_COMPB_ 0x08C0 +#define COMP_B_BASE __MSP430_BASEADDRESS_COMPB__ + +#define CBCTL0 0x08C0 /* Comparator B Control Register 0 */ +#define CBCTL1 0x08C2 /* Comparator B Control Register 1 */ +#define CBCTL2 0x08C4 /* Comparator B Control Register 2 */ +#define CBCTL3 0x08C6 /* Comparator B Control Register 3 */ +#define CBINT 0x08CC /* Comparator B Interrupt Register */ +#define CBIV 0x08CE /* Comparator B Interrupt Vector Word */ + + +/* CBCTL0 Control Bits */ +#define CBIPSEL0 (0x0001) /* Comp. B Pos. Channel Input Select 0 */ +#define CBIPSEL1 (0x0002) /* Comp. B Pos. Channel Input Select 1 */ +#define CBIPSEL2 (0x0004) /* Comp. B Pos. Channel Input Select 2 */ +#define CBIPSEL3 (0x0008) /* Comp. B Pos. Channel Input Select 3 */ +//#define RESERVED (0x0010) /* Comp. B */ +//#define RESERVED (0x0020) /* Comp. B */ +//#define RESERVED (0x0040) /* Comp. B */ +#define CBIPEN (0x0080) /* Comp. B Pos. Channel Input Enable */ +#define CBIMSEL0 (0x0100) /* Comp. B Neg. Channel Input Select 0 */ +#define CBIMSEL1 (0x0200) /* Comp. B Neg. Channel Input Select 1 */ +#define CBIMSEL2 (0x0400) /* Comp. B Neg. Channel Input Select 2 */ +#define CBIMSEL3 (0x0800) /* Comp. B Neg. Channel Input Select 3 */ +//#define RESERVED (0x1000) /* Comp. B */ +//#define RESERVED (0x2000) /* Comp. B */ +//#define RESERVED (0x4000) /* Comp. B */ +#define CBIMEN (0x8000) /* Comp. B Neg. Channel Input Enable */ + +/* CBCTL0 Control Bits */ +#define CBIPSEL0_L (0x0001) /* Comp. B Pos. Channel Input Select 0 */ +#define CBIPSEL1_L (0x0002) /* Comp. B Pos. Channel Input Select 1 */ +#define CBIPSEL2_L (0x0004) /* Comp. B Pos. Channel Input Select 2 */ +#define CBIPSEL3_L (0x0008) /* Comp. B Pos. Channel Input Select 3 */ +//#define RESERVED (0x0010) /* Comp. B */ +//#define RESERVED (0x0020) /* Comp. B */ +//#define RESERVED (0x0040) /* Comp. B */ +#define CBIPEN_L (0x0080) /* Comp. B Pos. Channel Input Enable */ +//#define RESERVED (0x1000) /* Comp. B */ +//#define RESERVED (0x2000) /* Comp. B */ +//#define RESERVED (0x4000) /* Comp. B */ + +/* CBCTL0 Control Bits */ +//#define RESERVED (0x0010) /* Comp. B */ +//#define RESERVED (0x0020) /* Comp. B */ +//#define RESERVED (0x0040) /* Comp. B */ +#define CBIMSEL0_H (0x0001) /* Comp. B Neg. Channel Input Select 0 */ +#define CBIMSEL1_H (0x0002) /* Comp. B Neg. Channel Input Select 1 */ +#define CBIMSEL2_H (0x0004) /* Comp. B Neg. Channel Input Select 2 */ +#define CBIMSEL3_H (0x0008) /* Comp. B Neg. Channel Input Select 3 */ +//#define RESERVED (0x1000) /* Comp. B */ +//#define RESERVED (0x2000) /* Comp. B */ +//#define RESERVED (0x4000) /* Comp. B */ +#define CBIMEN_H (0x0080) /* Comp. B Neg. Channel Input Enable */ + +#define CBIPSEL_0 (0x0000) /* Comp. B V+ terminal Input Select: Channel 0 */ +#define CBIPSEL_1 (0x0001) /* Comp. B V+ terminal Input Select: Channel 1 */ +#define CBIPSEL_2 (0x0002) /* Comp. B V+ terminal Input Select: Channel 2 */ +#define CBIPSEL_3 (0x0003) /* Comp. B V+ terminal Input Select: Channel 3 */ +#define CBIPSEL_4 (0x0004) /* Comp. B V+ terminal Input Select: Channel 4 */ +#define CBIPSEL_5 (0x0005) /* Comp. B V+ terminal Input Select: Channel 5 */ +#define CBIPSEL_6 (0x0006) /* Comp. B V+ terminal Input Select: Channel 6 */ +#define CBIPSEL_7 (0x0007) /* Comp. B V+ terminal Input Select: Channel 7 */ +#define CBIPSEL_8 (0x0008) /* Comp. B V+ terminal Input Select: Channel 8 */ +#define CBIPSEL_9 (0x0009) /* Comp. B V+ terminal Input Select: Channel 9 */ +#define CBIPSEL_10 (0x000A) /* Comp. B V+ terminal Input Select: Channel 10 */ +#define CBIPSEL_11 (0x000B) /* Comp. B V+ terminal Input Select: Channel 11 */ +#define CBIPSEL_12 (0x000C) /* Comp. B V+ terminal Input Select: Channel 12 */ +#define CBIPSEL_13 (0x000D) /* Comp. B V+ terminal Input Select: Channel 13 */ +#define CBIPSEL_14 (0x000E) /* Comp. B V+ terminal Input Select: Channel 14 */ +#define CBIPSEL_15 (0x000F) /* Comp. B V+ terminal Input Select: Channel 15 */ + +#define CBIMSEL_0 (0x0000) /* Comp. B V- Terminal Input Select: Channel 0 */ +#define CBIMSEL_1 (0x0100) /* Comp. B V- Terminal Input Select: Channel 1 */ +#define CBIMSEL_2 (0x0200) /* Comp. B V- Terminal Input Select: Channel 2 */ +#define CBIMSEL_3 (0x0300) /* Comp. B V- Terminal Input Select: Channel 3 */ +#define CBIMSEL_4 (0x0400) /* Comp. B V- Terminal Input Select: Channel 4 */ +#define CBIMSEL_5 (0x0500) /* Comp. B V- Terminal Input Select: Channel 5 */ +#define CBIMSEL_6 (0x0600) /* Comp. B V- Terminal Input Select: Channel 6 */ +#define CBIMSEL_7 (0x0700) /* Comp. B V- Terminal Input Select: Channel 7 */ +#define CBIMSEL_8 (0x0800) /* Comp. B V- terminal Input Select: Channel 8 */ +#define CBIMSEL_9 (0x0900) /* Comp. B V- terminal Input Select: Channel 9 */ +#define CBIMSEL_10 (0x0A00) /* Comp. B V- terminal Input Select: Channel 10 */ +#define CBIMSEL_11 (0x0B00) /* Comp. B V- terminal Input Select: Channel 11 */ +#define CBIMSEL_12 (0x0C00) /* Comp. B V- terminal Input Select: Channel 12 */ +#define CBIMSEL_13 (0x0D00) /* Comp. B V- terminal Input Select: Channel 13 */ +#define CBIMSEL_14 (0x0E00) /* Comp. B V- terminal Input Select: Channel 14 */ +#define CBIMSEL_15 (0x0F00) /* Comp. B V- terminal Input Select: Channel 15 */ + +/* CBCTL1 Control Bits */ +#define CBOUT (0x0001) /* Comp. B Output */ +#define CBOUTPOL (0x0002) /* Comp. B Output Polarity */ +#define CBF (0x0004) /* Comp. B Enable Output Filter */ +#define CBIES (0x0008) /* Comp. B Interrupt Edge Select */ +#define CBSHORT (0x0010) /* Comp. B Input Short */ +#define CBEX (0x0020) /* Comp. B Exchange Inputs */ +#define CBFDLY0 (0x0040) /* Comp. B Filter delay Bit 0 */ +#define CBFDLY1 (0x0080) /* Comp. B Filter delay Bit 1 */ +#define CBPWRMD0 (0x0100) /* Comp. B Power Mode Bit 0 */ +#define CBPWRMD1 (0x0200) /* Comp. B Power Mode Bit 1 */ +#define CBON (0x0400) /* Comp. B enable */ +#define CBMRVL (0x0800) /* Comp. B CBMRV Level */ +#define CBMRVS (0x1000) /* Comp. B Output selects between VREF0 or VREF1*/ +//#define RESERVED (0x2000) /* Comp. B */ +//#define RESERVED (0x4000) /* Comp. B */ +//#define RESERVED (0x8000) /* Comp. B */ + +/* CBCTL1 Control Bits */ +#define CBOUT_L (0x0001) /* Comp. B Output */ +#define CBOUTPOL_L (0x0002) /* Comp. B Output Polarity */ +#define CBF_L (0x0004) /* Comp. B Enable Output Filter */ +#define CBIES_L (0x0008) /* Comp. B Interrupt Edge Select */ +#define CBSHORT_L (0x0010) /* Comp. B Input Short */ +#define CBEX_L (0x0020) /* Comp. B Exchange Inputs */ +#define CBFDLY0_L (0x0040) /* Comp. B Filter delay Bit 0 */ +#define CBFDLY1_L (0x0080) /* Comp. B Filter delay Bit 1 */ +//#define RESERVED (0x2000) /* Comp. B */ +//#define RESERVED (0x4000) /* Comp. B */ +//#define RESERVED (0x8000) /* Comp. B */ + +/* CBCTL1 Control Bits */ +#define CBPWRMD0_H (0x0001) /* Comp. B Power Mode Bit 0 */ +#define CBPWRMD1_H (0x0002) /* Comp. B Power Mode Bit 1 */ +#define CBON_H (0x0004) /* Comp. B enable */ +#define CBMRVL_H (0x0008) /* Comp. B CBMRV Level */ +#define CBMRVS_H (0x0010) /* Comp. B Output selects between VREF0 or VREF1*/ +//#define RESERVED (0x2000) /* Comp. B */ +//#define RESERVED (0x4000) /* Comp. B */ +//#define RESERVED (0x8000) /* Comp. B */ + +#define CBFDLY_0 (0x0000) /* Comp. B Filter delay 0 : 450ns */ +#define CBFDLY_1 (0x0040) /* Comp. B Filter delay 1 : 900ns */ +#define CBFDLY_2 (0x0080) /* Comp. B Filter delay 2 : 1800ns */ +#define CBFDLY_3 (0x00C0) /* Comp. B Filter delay 3 : 3600ns */ + +#define CBPWRMD_0 (0x0000) /* Comp. B Power Mode 0 : High speed */ +#define CBPWRMD_1 (0x0100) /* Comp. B Power Mode 1 : Normal */ +#define CBPWRMD_2 (0x0200) /* Comp. B Power Mode 2 : Ultra-Low*/ +#define CBPWRMD_3 (0x0300) /* Comp. B Power Mode 3 : Reserved */ + + +/* CBCTL2 Control Bits */ +#define CBREF00 (0x0001) /* Comp. B Reference 0 Resistor Select Bit : 0 */ +#define CBREF01 (0x0002) /* Comp. B Reference 0 Resistor Select Bit : 1 */ +#define CBREF02 (0x0004) /* Comp. B Reference 0 Resistor Select Bit : 2 */ +#define CBREF03 (0x0008) /* Comp. B Reference 0 Resistor Select Bit : 3 */ +#define CBREF04 (0x0010) /* Comp. B Reference 0 Resistor Select Bit : 4 */ +#define CBRSEL (0x0020) /* Comp. B Reference select */ +#define CBRS0 (0x0040) /* Comp. B Reference Source Bit : 0 */ +#define CBRS1 (0x0080) /* Comp. B Reference Source Bit : 1 */ +#define CBREF10 (0x0100) /* Comp. B Reference 1 Resistor Select Bit : 0 */ +#define CBREF11 (0x0200) /* Comp. B Reference 1 Resistor Select Bit : 1 */ +#define CBREF12 (0x0400) /* Comp. B Reference 1 Resistor Select Bit : 2 */ +#define CBREF13 (0x0800) /* Comp. B Reference 1 Resistor Select Bit : 3 */ +#define CBREF14 (0x1000) /* Comp. B Reference 1 Resistor Select Bit : 4 */ +#define CBREFL0 (0x2000) /* Comp. B Reference voltage level Bit : 0 */ +#define CBREFL1 (0x4000) /* Comp. B Reference voltage level Bit : 1 */ +#define CBREFACC (0x8000) /* Comp. B Reference Accuracy */ + +/* CBCTL2 Control Bits */ +#define CBREF00_L (0x0001) /* Comp. B Reference 0 Resistor Select Bit : 0 */ +#define CBREF01_L (0x0002) /* Comp. B Reference 0 Resistor Select Bit : 1 */ +#define CBREF02_L (0x0004) /* Comp. B Reference 0 Resistor Select Bit : 2 */ +#define CBREF03_L (0x0008) /* Comp. B Reference 0 Resistor Select Bit : 3 */ +#define CBREF04_L (0x0010) /* Comp. B Reference 0 Resistor Select Bit : 4 */ +#define CBRSEL_L (0x0020) /* Comp. B Reference select */ +#define CBRS0_L (0x0040) /* Comp. B Reference Source Bit : 0 */ +#define CBRS1_L (0x0080) /* Comp. B Reference Source Bit : 1 */ + +/* CBCTL2 Control Bits */ +#define CBREF10_H (0x0001) /* Comp. B Reference 1 Resistor Select Bit : 0 */ +#define CBREF11_H (0x0002) /* Comp. B Reference 1 Resistor Select Bit : 1 */ +#define CBREF12_H (0x0004) /* Comp. B Reference 1 Resistor Select Bit : 2 */ +#define CBREF13_H (0x0008) /* Comp. B Reference 1 Resistor Select Bit : 3 */ +#define CBREF14_H (0x0010) /* Comp. B Reference 1 Resistor Select Bit : 4 */ +#define CBREFL0_H (0x0020) /* Comp. B Reference voltage level Bit : 0 */ +#define CBREFL1_H (0x0040) /* Comp. B Reference voltage level Bit : 1 */ +#define CBREFACC_H (0x0080) /* Comp. B Reference Accuracy */ + +#define CBREF0_0 (0x0000) /* Comp. B Int. Ref.0 Select 0 : 1/32 */ +#define CBREF0_1 (0x0001) /* Comp. B Int. Ref.0 Select 1 : 2/32 */ +#define CBREF0_2 (0x0002) /* Comp. B Int. Ref.0 Select 2 : 3/32 */ +#define CBREF0_3 (0x0003) /* Comp. B Int. Ref.0 Select 3 : 4/32 */ +#define CBREF0_4 (0x0004) /* Comp. B Int. Ref.0 Select 4 : 5/32 */ +#define CBREF0_5 (0x0005) /* Comp. B Int. Ref.0 Select 5 : 6/32 */ +#define CBREF0_6 (0x0006) /* Comp. B Int. Ref.0 Select 6 : 7/32 */ +#define CBREF0_7 (0x0007) /* Comp. B Int. Ref.0 Select 7 : 8/32 */ +#define CBREF0_8 (0x0008) /* Comp. B Int. Ref.0 Select 0 : 9/32 */ +#define CBREF0_9 (0x0009) /* Comp. B Int. Ref.0 Select 1 : 10/32 */ +#define CBREF0_10 (0x000A) /* Comp. B Int. Ref.0 Select 2 : 11/32 */ +#define CBREF0_11 (0x000B) /* Comp. B Int. Ref.0 Select 3 : 12/32 */ +#define CBREF0_12 (0x000C) /* Comp. B Int. Ref.0 Select 4 : 13/32 */ +#define CBREF0_13 (0x000D) /* Comp. B Int. Ref.0 Select 5 : 14/32 */ +#define CBREF0_14 (0x000E) /* Comp. B Int. Ref.0 Select 6 : 15/32 */ +#define CBREF0_15 (0x000F) /* Comp. B Int. Ref.0 Select 7 : 16/32 */ +#define CBREF0_16 (0x0010) /* Comp. B Int. Ref.0 Select 0 : 17/32 */ +#define CBREF0_17 (0x0011) /* Comp. B Int. Ref.0 Select 1 : 18/32 */ +#define CBREF0_18 (0x0012) /* Comp. B Int. Ref.0 Select 2 : 19/32 */ +#define CBREF0_19 (0x0013) /* Comp. B Int. Ref.0 Select 3 : 20/32 */ +#define CBREF0_20 (0x0014) /* Comp. B Int. Ref.0 Select 4 : 21/32 */ +#define CBREF0_21 (0x0015) /* Comp. B Int. Ref.0 Select 5 : 22/32 */ +#define CBREF0_22 (0x0016) /* Comp. B Int. Ref.0 Select 6 : 23/32 */ +#define CBREF0_23 (0x0017) /* Comp. B Int. Ref.0 Select 7 : 24/32 */ +#define CBREF0_24 (0x0018) /* Comp. B Int. Ref.0 Select 0 : 25/32 */ +#define CBREF0_25 (0x0019) /* Comp. B Int. Ref.0 Select 1 : 26/32 */ +#define CBREF0_26 (0x001A) /* Comp. B Int. Ref.0 Select 2 : 27/32 */ +#define CBREF0_27 (0x001B) /* Comp. B Int. Ref.0 Select 3 : 28/32 */ +#define CBREF0_28 (0x001C) /* Comp. B Int. Ref.0 Select 4 : 29/32 */ +#define CBREF0_29 (0x001D) /* Comp. B Int. Ref.0 Select 5 : 30/32 */ +#define CBREF0_30 (0x001E) /* Comp. B Int. Ref.0 Select 6 : 31/32 */ +#define CBREF0_31 (0x001F) /* Comp. B Int. Ref.0 Select 7 : 32/32 */ + +#define CBRS_0 (0x0000) /* Comp. B Reference Source 0 : Off */ +#define CBRS_1 (0x0040) /* Comp. B Reference Source 1 : Vcc */ +#define CBRS_2 (0x0080) /* Comp. B Reference Source 2 : Shared Ref. */ +#define CBRS_3 (0x00C0) /* Comp. B Reference Source 3 : Shared Ref. / Off */ + +#define CBREF1_0 (0x0000) /* Comp. B Int. Ref.1 Select 0 : 1/32 */ +#define CBREF1_1 (0x0100) /* Comp. B Int. Ref.1 Select 1 : 2/32 */ +#define CBREF1_2 (0x0200) /* Comp. B Int. Ref.1 Select 2 : 3/32 */ +#define CBREF1_3 (0x0300) /* Comp. B Int. Ref.1 Select 3 : 4/32 */ +#define CBREF1_4 (0x0400) /* Comp. B Int. Ref.1 Select 4 : 5/32 */ +#define CBREF1_5 (0x0500) /* Comp. B Int. Ref.1 Select 5 : 6/32 */ +#define CBREF1_6 (0x0600) /* Comp. B Int. Ref.1 Select 6 : 7/32 */ +#define CBREF1_7 (0x0700) /* Comp. B Int. Ref.1 Select 7 : 8/32 */ +#define CBREF1_8 (0x0800) /* Comp. B Int. Ref.1 Select 0 : 9/32 */ +#define CBREF1_9 (0x0900) /* Comp. B Int. Ref.1 Select 1 : 10/32 */ +#define CBREF1_10 (0x0A00) /* Comp. B Int. Ref.1 Select 2 : 11/32 */ +#define CBREF1_11 (0x0B00) /* Comp. B Int. Ref.1 Select 3 : 12/32 */ +#define CBREF1_12 (0x0C00) /* Comp. B Int. Ref.1 Select 4 : 13/32 */ +#define CBREF1_13 (0x0D00) /* Comp. B Int. Ref.1 Select 5 : 14/32 */ +#define CBREF1_14 (0x0E00) /* Comp. B Int. Ref.1 Select 6 : 15/32 */ +#define CBREF1_15 (0x0F00) /* Comp. B Int. Ref.1 Select 7 : 16/32 */ +#define CBREF1_16 (0x1000) /* Comp. B Int. Ref.1 Select 0 : 17/32 */ +#define CBREF1_17 (0x1100) /* Comp. B Int. Ref.1 Select 1 : 18/32 */ +#define CBREF1_18 (0x1200) /* Comp. B Int. Ref.1 Select 2 : 19/32 */ +#define CBREF1_19 (0x1300) /* Comp. B Int. Ref.1 Select 3 : 20/32 */ +#define CBREF1_20 (0x1400) /* Comp. B Int. Ref.1 Select 4 : 21/32 */ +#define CBREF1_21 (0x1500) /* Comp. B Int. Ref.1 Select 5 : 22/32 */ +#define CBREF1_22 (0x1600) /* Comp. B Int. Ref.1 Select 6 : 23/32 */ +#define CBREF1_23 (0x1700) /* Comp. B Int. Ref.1 Select 7 : 24/32 */ +#define CBREF1_24 (0x1800) /* Comp. B Int. Ref.1 Select 0 : 25/32 */ +#define CBREF1_25 (0x1900) /* Comp. B Int. Ref.1 Select 1 : 26/32 */ +#define CBREF1_26 (0x1A00) /* Comp. B Int. Ref.1 Select 2 : 27/32 */ +#define CBREF1_27 (0x1B00) /* Comp. B Int. Ref.1 Select 3 : 28/32 */ +#define CBREF1_28 (0x1C00) /* Comp. B Int. Ref.1 Select 4 : 29/32 */ +#define CBREF1_29 (0x1D00) /* Comp. B Int. Ref.1 Select 5 : 30/32 */ +#define CBREF1_30 (0x1E00) /* Comp. B Int. Ref.1 Select 6 : 31/32 */ +#define CBREF1_31 (0x1F00) /* Comp. B Int. Ref.1 Select 7 : 32/32 */ + +#define CBREFL_0 (0x0000) /* Comp. B Reference voltage level 0 : None */ +#define CBREFL_1 (0x2000) /* Comp. B Reference voltage level 1 : 1.5V */ +#define CBREFL_2 (0x4000) /* Comp. B Reference voltage level 2 : 2.0V */ +#define CBREFL_3 (0x6000) /* Comp. B Reference voltage level 3 : 2.5V */ + + +#define CBPD0 (0x0001) /* Comp. B Disable Input Buffer of Port Register .0 */ +#define CBPD1 (0x0002) /* Comp. B Disable Input Buffer of Port Register .1 */ +#define CBPD2 (0x0004) /* Comp. B Disable Input Buffer of Port Register .2 */ +#define CBPD3 (0x0008) /* Comp. B Disable Input Buffer of Port Register .3 */ +#define CBPD4 (0x0010) /* Comp. B Disable Input Buffer of Port Register .4 */ +#define CBPD5 (0x0020) /* Comp. B Disable Input Buffer of Port Register .5 */ +#define CBPD6 (0x0040) /* Comp. B Disable Input Buffer of Port Register .6 */ +#define CBPD7 (0x0080) /* Comp. B Disable Input Buffer of Port Register .7 */ +#define CBPD8 (0x0100) /* Comp. B Disable Input Buffer of Port Register .8 */ +#define CBPD9 (0x0200) /* Comp. B Disable Input Buffer of Port Register .9 */ +#define CBPD10 (0x0400) /* Comp. B Disable Input Buffer of Port Register .10 */ +#define CBPD11 (0x0800) /* Comp. B Disable Input Buffer of Port Register .11 */ +#define CBPD12 (0x1000) /* Comp. B Disable Input Buffer of Port Register .12 */ +#define CBPD13 (0x2000) /* Comp. B Disable Input Buffer of Port Register .13 */ +#define CBPD14 (0x4000) /* Comp. B Disable Input Buffer of Port Register .14 */ +#define CBPD15 (0x8000) /* Comp. B Disable Input Buffer of Port Register .15 */ + +#define CBPD0_L (0x0001) /* Comp. B Disable Input Buffer of Port Register .0 */ +#define CBPD1_L (0x0002) /* Comp. B Disable Input Buffer of Port Register .1 */ +#define CBPD2_L (0x0004) /* Comp. B Disable Input Buffer of Port Register .2 */ +#define CBPD3_L (0x0008) /* Comp. B Disable Input Buffer of Port Register .3 */ +#define CBPD4_L (0x0010) /* Comp. B Disable Input Buffer of Port Register .4 */ +#define CBPD5_L (0x0020) /* Comp. B Disable Input Buffer of Port Register .5 */ +#define CBPD6_L (0x0040) /* Comp. B Disable Input Buffer of Port Register .6 */ +#define CBPD7_L (0x0080) /* Comp. B Disable Input Buffer of Port Register .7 */ + +#define CBPD8_H (0x0001) /* Comp. B Disable Input Buffer of Port Register .8 */ +#define CBPD9_H (0x0002) /* Comp. B Disable Input Buffer of Port Register .9 */ +#define CBPD10_H (0x0004) /* Comp. B Disable Input Buffer of Port Register .10 */ +#define CBPD11_H (0x0008) /* Comp. B Disable Input Buffer of Port Register .11 */ +#define CBPD12_H (0x0010) /* Comp. B Disable Input Buffer of Port Register .12 */ +#define CBPD13_H (0x0020) /* Comp. B Disable Input Buffer of Port Register .13 */ +#define CBPD14_H (0x0040) /* Comp. B Disable Input Buffer of Port Register .14 */ +#define CBPD15_H (0x0080) /* Comp. B Disable Input Buffer of Port Register .15 */ + + +/* CBINT Control Bits */ +#define CBIFG (0x0001) /* Comp. B Interrupt Flag */ +#define CBIIFG (0x0002) /* Comp. B Interrupt Flag Inverted Polarity */ +//#define RESERVED (0x0004) /* Comp. B */ +//#define RESERVED (0x0008) /* Comp. B */ +//#define RESERVED (0x0010) /* Comp. B */ +//#define RESERVED (0x0020) /* Comp. B */ +//#define RESERVED (0x0040) /* Comp. B */ +//#define RESERVED (0x0080) /* Comp. B */ +#define CBIE (0x0100) /* Comp. B Interrupt Enable */ +#define CBIIE (0x0200) /* Comp. B Interrupt Enable Inverted Polarity */ +//#define RESERVED (0x0400) /* Comp. B */ +//#define RESERVED (0x0800) /* Comp. B */ +//#define RESERVED (0x1000) /* Comp. B */ +//#define RESERVED (0x2000) /* Comp. B */ +//#define RESERVED (0x4000) /* Comp. B */ +//#define RESERVED (0x8000) /* Comp. B */ + +/* CBINT Control Bits */ +#define CBIFG_L (0x0001) /* Comp. B Interrupt Flag */ +#define CBIIFG_L (0x0002) /* Comp. B Interrupt Flag Inverted Polarity */ +//#define RESERVED (0x0004) /* Comp. B */ +//#define RESERVED (0x0008) /* Comp. B */ +//#define RESERVED (0x0010) /* Comp. B */ +//#define RESERVED (0x0020) /* Comp. B */ +//#define RESERVED (0x0040) /* Comp. B */ +//#define RESERVED (0x0080) /* Comp. B */ +//#define RESERVED (0x0400) /* Comp. B */ +//#define RESERVED (0x0800) /* Comp. B */ +//#define RESERVED (0x1000) /* Comp. B */ +//#define RESERVED (0x2000) /* Comp. B */ +//#define RESERVED (0x4000) /* Comp. B */ +//#define RESERVED (0x8000) /* Comp. B */ + +/* CBINT Control Bits */ +//#define RESERVED (0x0004) /* Comp. B */ +//#define RESERVED (0x0008) /* Comp. B */ +//#define RESERVED (0x0010) /* Comp. B */ +//#define RESERVED (0x0020) /* Comp. B */ +//#define RESERVED (0x0040) /* Comp. B */ +//#define RESERVED (0x0080) /* Comp. B */ +#define CBIE_H (0x0001) /* Comp. B Interrupt Enable */ +#define CBIIE_H (0x0002) /* Comp. B Interrupt Enable Inverted Polarity */ +//#define RESERVED (0x0400) /* Comp. B */ +//#define RESERVED (0x0800) /* Comp. B */ +//#define RESERVED (0x1000) /* Comp. B */ +//#define RESERVED (0x2000) /* Comp. B */ +//#define RESERVED (0x4000) /* Comp. B */ +//#define RESERVED (0x8000) /* Comp. B */ + +/* CBIV Definitions */ +#define CBIV_NONE (0x0000) /* No Interrupt pending */ +#define CBIV_CBIFG (0x0002) /* CBIFG */ +#define CBIV_CBIIFG (0x0004) /* CBIIFG */ + +/************************************************************* +* CRC Module +*************************************************************/ + +#define CRCDI 0x0150 /* CRC Data In Register */ +#define CRCDIRB 0x0152 /* CRC data in reverse byte Register */ +#define CRCINIRES 0x0154 /* CRC Initialisation Register and Result Register */ +#define CRCRESR 0x0156 /* CRC reverse result Register */ + +/************************************************************ +* DMA_X +************************************************************/ +#define __MSP430_HAS_DMAX_3_ /* Definition to show that Module is available */ +#define __MSP430_BASEADDRESS_DMAX_3_ 0x0500 +#define DMA_BASE __MSP430_BASEADDRESS_DMAX_3__ + +#define DMACTL0 0x0500 /* DMA Module Control 0 */ +#define DMACTL1 0x0502 /* DMA Module Control 1 */ +#define DMACTL2 0x0504 /* DMA Module Control 2 */ +#define DMACTL3 0x0506 /* DMA Module Control 3 */ +#define DMACTL4 0x0508 /* DMA Module Control 4 */ +#define DMAIV 0x050E /* DMA Interrupt Vector Word */ + +#define DMA0CTL 0x0510 /* DMA Channel 0 Control */ +#define DMA0SA 0x0512 /* DMA Channel 0 Source Address */ +#define DMA0DA 0x0516 /* DMA Channel 0 Destination Address */ +#define DMA0SZ 0x051A /* DMA Channel 0 Transfer Size */ + +#define DMA1CTL 0x0520 /* DMA Channel 1 Control */ +#define DMA1SA 0x0522 /* DMA Channel 1 Source Address */ +#define DMA1DA 0x0526 /* DMA Channel 1 Destination Address */ +#define DMA1SZ 0x052A /* DMA Channel 1 Transfer Size */ + +#define DMA2CTL 0x0530 /* DMA Channel 2 Control */ +#define DMA2SA 0x0532 /* DMA Channel 2 Source Address */ +#define DMA2DA 0x0536 /* DMA Channel 2 Destination Address */ +#define DMA2SZ 0x053A /* DMA Channel 2 Transfer Size */ + +/* DMACTL0 Control Bits */ +#define DMA0TSEL0 (0x0001) /* DMA channel 0 transfer select bit 0 */ +#define DMA0TSEL1 (0x0002) /* DMA channel 0 transfer select bit 1 */ +#define DMA0TSEL2 (0x0004) /* DMA channel 0 transfer select bit 2 */ +#define DMA0TSEL3 (0x0008) /* DMA channel 0 transfer select bit 3 */ +#define DMA0TSEL4 (0x0010) /* DMA channel 0 transfer select bit 4 */ +#define DMA1TSEL0 (0x0100) /* DMA channel 1 transfer select bit 0 */ +#define DMA1TSEL1 (0x0200) /* DMA channel 1 transfer select bit 1 */ +#define DMA1TSEL2 (0x0400) /* DMA channel 1 transfer select bit 2 */ +#define DMA1TSEL3 (0x0800) /* DMA channel 1 transfer select bit 3 */ +#define DMA1TSEL4 (0x1000) /* DMA channel 1 transfer select bit 4 */ + +/* DMACTL0 Control Bits */ +#define DMA0TSEL0_L (0x0001) /* DMA channel 0 transfer select bit 0 */ +#define DMA0TSEL1_L (0x0002) /* DMA channel 0 transfer select bit 1 */ +#define DMA0TSEL2_L (0x0004) /* DMA channel 0 transfer select bit 2 */ +#define DMA0TSEL3_L (0x0008) /* DMA channel 0 transfer select bit 3 */ +#define DMA0TSEL4_L (0x0010) /* DMA channel 0 transfer select bit 4 */ + +/* DMACTL0 Control Bits */ +#define DMA1TSEL0_H (0x0001) /* DMA channel 1 transfer select bit 0 */ +#define DMA1TSEL1_H (0x0002) /* DMA channel 1 transfer select bit 1 */ +#define DMA1TSEL2_H (0x0004) /* DMA channel 1 transfer select bit 2 */ +#define DMA1TSEL3_H (0x0008) /* DMA channel 1 transfer select bit 3 */ +#define DMA1TSEL4_H (0x0010) /* DMA channel 1 transfer select bit 4 */ + +/* DMACTL01 Control Bits */ +#define DMA2TSEL0 (0x0001) /* DMA channel 2 transfer select bit 0 */ +#define DMA2TSEL1 (0x0002) /* DMA channel 2 transfer select bit 1 */ +#define DMA2TSEL2 (0x0004) /* DMA channel 2 transfer select bit 2 */ +#define DMA2TSEL3 (0x0008) /* DMA channel 2 transfer select bit 3 */ +#define DMA2TSEL4 (0x0010) /* DMA channel 2 transfer select bit 4 */ + +/* DMACTL01 Control Bits */ +#define DMA2TSEL0_L (0x0001) /* DMA channel 2 transfer select bit 0 */ +#define DMA2TSEL1_L (0x0002) /* DMA channel 2 transfer select bit 1 */ +#define DMA2TSEL2_L (0x0004) /* DMA channel 2 transfer select bit 2 */ +#define DMA2TSEL3_L (0x0008) /* DMA channel 2 transfer select bit 3 */ +#define DMA2TSEL4_L (0x0010) /* DMA channel 2 transfer select bit 4 */ + + +/* DMACTL4 Control Bits */ +#define ENNMI (0x0001) /* Enable NMI interruption of DMA */ +#define ROUNDROBIN (0x0002) /* Round-Robin DMA channel priorities */ +#define DMARMWDIS (0x0004) /* Inhibited DMA transfers during read-modify-write CPU operations */ + +/* DMACTL4 Control Bits */ +#define ENNMI_L (0x0001) /* Enable NMI interruption of DMA */ +#define ROUNDROBIN_L (0x0002) /* Round-Robin DMA channel priorities */ +#define DMARMWDIS_L (0x0004) /* Inhibited DMA transfers during read-modify-write CPU operations */ + + + +/* DMAxCTL Control Bits */ +#define DMAREQ (0x0001) /* Initiate DMA transfer with DMATSEL */ +#define DMAABORT (0x0002) /* DMA transfer aborted by NMI */ +#define DMAIE (0x0004) /* DMA interrupt enable */ +#define DMAIFG (0x0008) /* DMA interrupt flag */ +#define DMAEN (0x0010) /* DMA enable */ +#define DMALEVEL (0x0020) /* DMA level sensitive trigger select */ +#define DMASRCBYTE (0x0040) /* DMA source byte */ +#define DMADSTBYTE (0x0080) /* DMA destination byte */ +#define DMASRCINCR0 (0x0100) /* DMA source increment bit 0 */ +#define DMASRCINCR1 (0x0200) /* DMA source increment bit 1 */ +#define DMADSTINCR0 (0x0400) /* DMA destination increment bit 0 */ +#define DMADSTINCR1 (0x0800) /* DMA destination increment bit 1 */ +#define DMADT0 (0x1000) /* DMA transfer mode bit 0 */ +#define DMADT1 (0x2000) /* DMA transfer mode bit 1 */ +#define DMADT2 (0x4000) /* DMA transfer mode bit 2 */ + +/* DMAxCTL Control Bits */ +#define DMAREQ_L (0x0001) /* Initiate DMA transfer with DMATSEL */ +#define DMAABORT_L (0x0002) /* DMA transfer aborted by NMI */ +#define DMAIE_L (0x0004) /* DMA interrupt enable */ +#define DMAIFG_L (0x0008) /* DMA interrupt flag */ +#define DMAEN_L (0x0010) /* DMA enable */ +#define DMALEVEL_L (0x0020) /* DMA level sensitive trigger select */ +#define DMASRCBYTE_L (0x0040) /* DMA source byte */ +#define DMADSTBYTE_L (0x0080) /* DMA destination byte */ + +/* DMAxCTL Control Bits */ +#define DMASRCINCR0_H (0x0001) /* DMA source increment bit 0 */ +#define DMASRCINCR1_H (0x0002) /* DMA source increment bit 1 */ +#define DMADSTINCR0_H (0x0004) /* DMA destination increment bit 0 */ +#define DMADSTINCR1_H (0x0008) /* DMA destination increment bit 1 */ +#define DMADT0_H (0x0010) /* DMA transfer mode bit 0 */ +#define DMADT1_H (0x0020) /* DMA transfer mode bit 1 */ +#define DMADT2_H (0x0040) /* DMA transfer mode bit 2 */ + +#define DMASWDW (0x0000) /* DMA transfer: source word to destination word */ +#define DMASBDW (0x0040) /* DMA transfer: source byte to destination word */ +#define DMASWDB (0x0080) /* DMA transfer: source word to destination byte */ +#define DMASBDB (0x00C0) /* DMA transfer: source byte to destination byte */ + +#define DMASRCINCR_0 (0x0000) /* DMA source increment 0: source address unchanged */ +#define DMASRCINCR_1 (0x0100) /* DMA source increment 1: source address unchanged */ +#define DMASRCINCR_2 (0x0200) /* DMA source increment 2: source address decremented */ +#define DMASRCINCR_3 (0x0300) /* DMA source increment 3: source address incremented */ + +#define DMADSTINCR_0 (0x0000) /* DMA destination increment 0: destination address unchanged */ +#define DMADSTINCR_1 (0x0400) /* DMA destination increment 1: destination address unchanged */ +#define DMADSTINCR_2 (0x0800) /* DMA destination increment 2: destination address decremented */ +#define DMADSTINCR_3 (0x0C00) /* DMA destination increment 3: destination address incremented */ + +#define DMADT_0 (0x0000) /* DMA transfer mode 0: Single transfer */ +#define DMADT_1 (0x1000) /* DMA transfer mode 1: Block transfer */ +#define DMADT_2 (0x2000) /* DMA transfer mode 2: Burst-Block transfer */ +#define DMADT_3 (0x3000) /* DMA transfer mode 3: Burst-Block transfer */ +#define DMADT_4 (0x4000) /* DMA transfer mode 4: Repeated Single transfer */ +#define DMADT_5 (0x5000) /* DMA transfer mode 5: Repeated Block transfer */ +#define DMADT_6 (0x6000) /* DMA transfer mode 6: Repeated Burst-Block transfer */ +#define DMADT_7 (0x7000) /* DMA transfer mode 7: Repeated Burst-Block transfer */ + +/* DMAIV Definitions */ +#define DMAIV_NONE (0x0000) /* No Interrupt pending */ +#define DMAIV_DMA0IFG (0x0002) /* DMA0IFG*/ +#define DMAIV_DMA1IFG (0x0004) /* DMA1IFG*/ +#define DMAIV_DMA2IFG (0x0006) /* DMA2IFG*/ + +#define DMA0TSEL_0 (0x0000) /* DMA channel 0 transfer select 0: DMA_REQ (sw) */ +#define DMA0TSEL_1 (0x0001) /* DMA channel 0 transfer select 1: Timer0_A (TA0CCR0.IFG) */ +#define DMA0TSEL_2 (0x0002) /* DMA channel 0 transfer select 2: Timer0_A (TA0CCR2.IFG) */ +#define DMA0TSEL_3 (0x0003) /* DMA channel 0 transfer select 3: Timer1_A (TA1CCR0.IFG) */ +#define DMA0TSEL_4 (0x0004) /* DMA channel 0 transfer select 4: Timer1_A (TA1CCR2.IFG) */ +#define DMA0TSEL_5 (0x0005) /* DMA channel 0 transfer select 5: Timer2_A (TA2CCR0.IFG) */ +#define DMA0TSEL_6 (0x0006) /* DMA channel 0 transfer select 6: Timer2_A (TA2CCR2.IFG) */ +#define DMA0TSEL_7 (0x0007) /* DMA channel 0 transfer select 7: TimerB (TB0CCR0.IFG) */ +#define DMA0TSEL_8 (0x0008) /* DMA channel 0 transfer select 8: TimerB (TB0CCR2.IFG) */ +#define DMA0TSEL_9 (0x0009) /* DMA channel 0 transfer select 9: Reserved */ +#define DMA0TSEL_10 (0x000A) /* DMA channel 0 transfer select 10: Reserved */ +#define DMA0TSEL_11 (0x000B) /* DMA channel 0 transfer select 11: Reserved */ +#define DMA0TSEL_12 (0x000C) /* DMA channel 0 transfer select 12: Reserved */ +#define DMA0TSEL_13 (0x000D) /* DMA channel 0 transfer select 13: Reserved */ +#define DMA0TSEL_14 (0x000E) /* DMA channel 0 transfer select 14: Reserved */ +#define DMA0TSEL_15 (0x000F) /* DMA channel 0 transfer select 15: Reserved */ +#define DMA0TSEL_16 (0x0010) /* DMA channel 0 transfer select 16: USCIA0 receive */ +#define DMA0TSEL_17 (0x0011) /* DMA channel 0 transfer select 17: USCIA0 transmit */ +#define DMA0TSEL_18 (0x0012) /* DMA channel 0 transfer select 18: USCIB0 receive */ +#define DMA0TSEL_19 (0x0013) /* DMA channel 0 transfer select 19: USCIB0 transmit */ +#define DMA0TSEL_20 (0x0014) /* DMA channel 0 transfer select 20: USCIA1 receive */ +#define DMA0TSEL_21 (0x0015) /* DMA channel 0 transfer select 21: USCIA1 transmit */ +#define DMA0TSEL_22 (0x0016) /* DMA channel 0 transfer select 22: USCIB1 receive */ +#define DMA0TSEL_23 (0x0017) /* DMA channel 0 transfer select 23: USCIB1 transmit */ +#define DMA0TSEL_24 (0x0018) /* DMA channel 0 transfer select 24: ADC12IFGx */ +#define DMA0TSEL_25 (0x0019) /* DMA channel 0 transfer select 25: Reserved */ +#define DMA0TSEL_26 (0x001A) /* DMA channel 0 transfer select 26: Reserved */ +#define DMA0TSEL_27 (0x001B) /* DMA channel 0 transfer select 27: USB FNRXD */ +#define DMA0TSEL_28 (0x001C) /* DMA channel 0 transfer select 28: USB ready */ +#define DMA0TSEL_29 (0x001D) /* DMA channel 0 transfer select 29: Multiplier ready */ +#define DMA0TSEL_30 (0x001E) /* DMA channel 0 transfer select 30: previous DMA channel DMA2IFG */ +#define DMA0TSEL_31 (0x001F) /* DMA channel 0 transfer select 31: ext. Trigger (DMAE0) */ + +#define DMA1TSEL_0 (0x0000) /* DMA channel 1 transfer select 0: DMA_REQ (sw) */ +#define DMA1TSEL_1 (0x0100) /* DMA channel 1 transfer select 1: Timer0_A (TA0CCR0.IFG) */ +#define DMA1TSEL_2 (0x0200) /* DMA channel 1 transfer select 2: Timer0_A (TA0CCR2.IFG) */ +#define DMA1TSEL_3 (0x0300) /* DMA channel 1 transfer select 3: Timer1_A (TA1CCR0.IFG) */ +#define DMA1TSEL_4 (0x0400) /* DMA channel 1 transfer select 4: Timer1_A (TA1CCR2.IFG) */ +#define DMA1TSEL_5 (0x0500) /* DMA channel 1 transfer select 5: Timer2_A (TA2CCR0.IFG) */ +#define DMA1TSEL_6 (0x0600) /* DMA channel 1 transfer select 6: Timer2_A (TA2CCR2.IFG) */ +#define DMA1TSEL_7 (0x0700) /* DMA channel 1 transfer select 7: TimerB (TB0CCR0.IFG) */ +#define DMA1TSEL_8 (0x0800) /* DMA channel 1 transfer select 8: TimerB (TB0CCR2.IFG) */ +#define DMA1TSEL_9 (0x0900) /* DMA channel 1 transfer select 9: Reserved */ +#define DMA1TSEL_10 (0x0A00) /* DMA channel 1 transfer select 10: Reserved */ +#define DMA1TSEL_11 (0x0B00) /* DMA channel 1 transfer select 11: Reserved */ +#define DMA1TSEL_12 (0x0C00) /* DMA channel 1 transfer select 12: Reserved */ +#define DMA1TSEL_13 (0x0D00) /* DMA channel 1 transfer select 13: Reserved */ +#define DMA1TSEL_14 (0x0E00) /* DMA channel 1 transfer select 14: Reserved */ +#define DMA1TSEL_15 (0x0F00) /* DMA channel 1 transfer select 15: Reserved */ +#define DMA1TSEL_16 (0x1000) /* DMA channel 1 transfer select 16: USCIA0 receive */ +#define DMA1TSEL_17 (0x1100) /* DMA channel 1 transfer select 17: USCIA0 transmit */ +#define DMA1TSEL_18 (0x1200) /* DMA channel 1 transfer select 18: USCIB0 receive */ +#define DMA1TSEL_19 (0x1300) /* DMA channel 1 transfer select 19: USCIB0 transmit */ +#define DMA1TSEL_20 (0x1400) /* DMA channel 1 transfer select 20: USCIA1 receive */ +#define DMA1TSEL_21 (0x1500) /* DMA channel 1 transfer select 21: USCIA1 transmit */ +#define DMA1TSEL_22 (0x1600) /* DMA channel 1 transfer select 22: USCIB1 receive */ +#define DMA1TSEL_23 (0x1700) /* DMA channel 1 transfer select 23: USCIB1 transmit */ +#define DMA1TSEL_24 (0x1800) /* DMA channel 1 transfer select 24: ADC12IFGx */ +#define DMA1TSEL_25 (0x1900) /* DMA channel 1 transfer select 25: Reserved */ +#define DMA1TSEL_26 (0x1A00) /* DMA channel 1 transfer select 26: Reserved */ +#define DMA1TSEL_27 (0x1B00) /* DMA channel 1 transfer select 27: USB FNRXD */ +#define DMA1TSEL_28 (0x1C00) /* DMA channel 1 transfer select 28: USB ready */ +#define DMA1TSEL_29 (0x1D00) /* DMA channel 1 transfer select 29: Multiplier ready */ +#define DMA1TSEL_30 (0x1E00) /* DMA channel 1 transfer select 30: previous DMA channel DMA0IFG */ +#define DMA1TSEL_31 (0x1F00) /* DMA channel 1 transfer select 31: ext. Trigger (DMAE0) */ + +#define DMA2TSEL_0 (0x0000) /* DMA channel 2 transfer select 0: DMA_REQ (sw) */ +#define DMA2TSEL_1 (0x0001) /* DMA channel 2 transfer select 1: Timer0_A (TA0CCR0.IFG) */ +#define DMA2TSEL_2 (0x0002) /* DMA channel 2 transfer select 2: Timer0_A (TA0CCR2.IFG) */ +#define DMA2TSEL_3 (0x0003) /* DMA channel 2 transfer select 3: Timer1_A (TA1CCR0.IFG) */ +#define DMA2TSEL_4 (0x0004) /* DMA channel 2 transfer select 4: Timer1_A (TA1CCR2.IFG) */ +#define DMA2TSEL_5 (0x0005) /* DMA channel 2 transfer select 5: Timer2_A (TA2CCR0.IFG) */ +#define DMA2TSEL_6 (0x0006) /* DMA channel 2 transfer select 6: Timer2_A (TA2CCR2.IFG) */ +#define DMA2TSEL_7 (0x0007) /* DMA channel 2 transfer select 7: TimerB (TB0CCR0.IFG) */ +#define DMA2TSEL_8 (0x0008) /* DMA channel 2 transfer select 8: TimerB (TB0CCR2.IFG) */ +#define DMA2TSEL_9 (0x0009) /* DMA channel 2 transfer select 9: Reserved */ +#define DMA2TSEL_10 (0x000A) /* DMA channel 2 transfer select 10: Reserved */ +#define DMA2TSEL_11 (0x000B) /* DMA channel 2 transfer select 11: Reserved */ +#define DMA2TSEL_12 (0x000C) /* DMA channel 2 transfer select 12: Reserved */ +#define DMA2TSEL_13 (0x000D) /* DMA channel 2 transfer select 13: Reserved */ +#define DMA2TSEL_14 (0x000E) /* DMA channel 2 transfer select 14: Reserved */ +#define DMA2TSEL_15 (0x000F) /* DMA channel 2 transfer select 15: Reserved */ +#define DMA2TSEL_16 (0x0010) /* DMA channel 2 transfer select 16: USCIA0 receive */ +#define DMA2TSEL_17 (0x0011) /* DMA channel 2 transfer select 17: USCIA0 transmit */ +#define DMA2TSEL_18 (0x0012) /* DMA channel 2 transfer select 18: USCIB0 receive */ +#define DMA2TSEL_19 (0x0013) /* DMA channel 2 transfer select 19: USCIB0 transmit */ +#define DMA2TSEL_20 (0x0014) /* DMA channel 2 transfer select 20: USCIA1 receive */ +#define DMA2TSEL_21 (0x0015) /* DMA channel 2 transfer select 21: USCIA1 transmit */ +#define DMA2TSEL_22 (0x0016) /* DMA channel 2 transfer select 22: USCIB1 receive */ +#define DMA2TSEL_23 (0x0017) /* DMA channel 2 transfer select 23: USCIB1 transmit */ +#define DMA2TSEL_24 (0x0018) /* DMA channel 2 transfer select 24: ADC12IFGx */ +#define DMA2TSEL_25 (0x0019) /* DMA channel 2 transfer select 25: Reserved */ +#define DMA2TSEL_26 (0x001A) /* DMA channel 2 transfer select 26: Reserved */ +#define DMA2TSEL_27 (0x001B) /* DMA channel 2 transfer select 27: USB FNRXD */ +#define DMA2TSEL_28 (0x001C) /* DMA channel 2 transfer select 28: USB ready */ +#define DMA2TSEL_29 (0x001D) /* DMA channel 2 transfer select 29: Multiplier ready */ +#define DMA2TSEL_30 (0x001E) /* DMA channel 2 transfer select 30: previous DMA channel DMA1IFG */ +#define DMA2TSEL_31 (0x001F) /* DMA channel 2 transfer select 31: ext. Trigger (DMAE0) */ + +#define DMA0TSEL__DMA_REQ (0x0000) /* DMA channel 0 transfer select 0: DMA_REQ (sw) */ +#define DMA0TSEL__TA0CCR0 (0x0001) /* DMA channel 0 transfer select 1: Timer0_A (TA0CCR0.IFG) */ +#define DMA0TSEL__TA0CCR2 (0x0002) /* DMA channel 0 transfer select 2: Timer0_A (TA0CCR2.IFG) */ +#define DMA0TSEL__TA1CCR0 (0x0003) /* DMA channel 0 transfer select 3: Timer1_A (TA1CCR0.IFG) */ +#define DMA0TSEL__TA1CCR2 (0x0004) /* DMA channel 0 transfer select 4: Timer1_A (TA1CCR2.IFG) */ +#define DMA0TSEL__TA2CCR0 (0x0005) /* DMA channel 0 transfer select 5: Timer2_A (TA2CCR0.IFG) */ +#define DMA0TSEL__TA2CCR2 (0x0006) /* DMA channel 0 transfer select 6: Timer2_A (TA2CCR2.IFG) */ +#define DMA0TSEL__TB0CCR0 (0x0007) /* DMA channel 0 transfer select 7: TimerB (TB0CCR0.IFG) */ +#define DMA0TSEL__TB0CCR2 (0x0008) /* DMA channel 0 transfer select 8: TimerB (TB0CCR2.IFG) */ +#define DMA0TSEL__RES9 (0x0009) /* DMA channel 0 transfer select 9: Reserved */ +#define DMA0TSEL__RES10 (0x000A) /* DMA channel 0 transfer select 10: Reserved */ +#define DMA0TSEL__RES11 (0x000B) /* DMA channel 0 transfer select 11: Reserved */ +#define DMA0TSEL__RES12 (0x000C) /* DMA channel 0 transfer select 12: Reserved */ +#define DMA0TSEL__RES13 (0x000D) /* DMA channel 0 transfer select 13: Reserved */ +#define DMA0TSEL__RES14 (0x000E) /* DMA channel 0 transfer select 14: Reserved */ +#define DMA0TSEL__RES15 (0x000F) /* DMA channel 0 transfer select 15: Reserved */ +#define DMA0TSEL__USCIA0RX (0x0010) /* DMA channel 0 transfer select 16: USCIA0 receive */ +#define DMA0TSEL__USCIA0TX (0x0011) /* DMA channel 0 transfer select 17: USCIA0 transmit */ +#define DMA0TSEL__USCIB0RX (0x0012) /* DMA channel 0 transfer select 18: USCIB0 receive */ +#define DMA0TSEL__USCIB0TX (0x0013) /* DMA channel 0 transfer select 19: USCIB0 transmit */ +#define DMA0TSEL__USCIA1RX (0x0014) /* DMA channel 0 transfer select 20: USCIA1 receive */ +#define DMA0TSEL__USCIA1TX (0x0015) /* DMA channel 0 transfer select 21: USCIA1 transmit */ +#define DMA0TSEL__USCIB1RX (0x0016) /* DMA channel 0 transfer select 22: USCIB1 receive */ +#define DMA0TSEL__USCIB1TX (0x0017) /* DMA channel 0 transfer select 23: USCIB1 transmit */ +#define DMA0TSEL__ADC12IFG (0x0018) /* DMA channel 0 transfer select 24: ADC12IFGx */ +#define DMA0TSEL__RES25 (0x0019) /* DMA channel 0 transfer select 25: Reserved */ +#define DMA0TSEL__RES26 (0x001A) /* DMA channel 0 transfer select 26: Reserved */ +#define DMA0TSEL__USB_FNRXD (0x001B) /* DMA channel 0 transfer select 27: USB FNRXD */ +#define DMA0TSEL__USB_READY (0x001C) /* DMA channel 0 transfer select 28: USB ready */ +#define DMA0TSEL__MPY (0x001D) /* DMA channel 0 transfer select 29: Multiplier ready */ +#define DMA0TSEL__DMA2IFG (0x001E) /* DMA channel 0 transfer select 30: previous DMA channel DMA2IFG */ +#define DMA0TSEL__DMAE0 (0x001F) /* DMA channel 0 transfer select 31: ext. Trigger (DMAE0) */ + +#define DMA1TSEL__DMA_REQ (0x0000) /* DMA channel 1 transfer select 0: DMA_REQ (sw) */ +#define DMA1TSEL__TA0CCR0 (0x0100) /* DMA channel 1 transfer select 1: Timer0_A (TA0CCR0.IFG) */ +#define DMA1TSEL__TA0CCR2 (0x0200) /* DMA channel 1 transfer select 2: Timer0_A (TA0CCR2.IFG) */ +#define DMA1TSEL__TA1CCR0 (0x0300) /* DMA channel 1 transfer select 3: Timer1_A (TA1CCR0.IFG) */ +#define DMA1TSEL__TA1CCR2 (0x0400) /* DMA channel 1 transfer select 4: Timer1_A (TA1CCR2.IFG) */ +#define DMA1TSEL__TA2CCR0 (0x0500) /* DMA channel 1 transfer select 5: Timer2_A (TA2CCR0.IFG) */ +#define DMA1TSEL__TA2CCR2 (0x0600) /* DMA channel 1 transfer select 6: Timer2_A (TA2CCR2.IFG) */ +#define DMA1TSEL__TB0CCR0 (0x0700) /* DMA channel 1 transfer select 7: TimerB (TB0CCR0.IFG) */ +#define DMA1TSEL__TB0CCR2 (0x0800) /* DMA channel 1 transfer select 8: TimerB (TB0CCR2.IFG) */ +#define DMA1TSEL__RES9 (0x0900) /* DMA channel 1 transfer select 9: Reserved */ +#define DMA1TSEL__RES10 (0x0A00) /* DMA channel 1 transfer select 10: Reserved */ +#define DMA1TSEL__RES11 (0x0B00) /* DMA channel 1 transfer select 11: Reserved */ +#define DMA1TSEL__RES12 (0x0C00) /* DMA channel 1 transfer select 12: Reserved */ +#define DMA1TSEL__RES13 (0x0D00) /* DMA channel 1 transfer select 13: Reserved */ +#define DMA1TSEL__RES14 (0x0E00) /* DMA channel 1 transfer select 14: Reserved */ +#define DMA1TSEL__RES15 (0x0F00) /* DMA channel 1 transfer select 15: Reserved */ +#define DMA1TSEL__USCIA0RX (0x1000) /* DMA channel 1 transfer select 16: USCIA0 receive */ +#define DMA1TSEL__USCIA0TX (0x1100) /* DMA channel 1 transfer select 17: USCIA0 transmit */ +#define DMA1TSEL__USCIB0RX (0x1200) /* DMA channel 1 transfer select 18: USCIB0 receive */ +#define DMA1TSEL__USCIB0TX (0x1300) /* DMA channel 1 transfer select 19: USCIB0 transmit */ +#define DMA1TSEL__USCIA1RX (0x1400) /* DMA channel 1 transfer select 20: USCIA1 receive */ +#define DMA1TSEL__USCIA1TX (0x1500) /* DMA channel 1 transfer select 21: USCIA1 transmit */ +#define DMA1TSEL__USCIB1RX (0x1600) /* DMA channel 1 transfer select 22: USCIB1 receive */ +#define DMA1TSEL__USCIB1TX (0x1700) /* DMA channel 1 transfer select 23: USCIB1 transmit */ +#define DMA1TSEL__ADC12IFG (0x1800) /* DMA channel 1 transfer select 24: ADC12IFGx */ +#define DMA1TSEL__RES25 (0x1900) /* DMA channel 1 transfer select 25: Reserved */ +#define DMA1TSEL__RES26 (0x1A00) /* DMA channel 1 transfer select 26: Reserved */ +#define DMA1TSEL__USB_FNRXD (0x1B00) /* DMA channel 1 transfer select 27: USB FNRXD */ +#define DMA1TSEL__USB_READY (0x1C00) /* DMA channel 1 transfer select 28: USB ready */ +#define DMA1TSEL__MPY (0x1D00) /* DMA channel 1 transfer select 29: Multiplier ready */ +#define DMA1TSEL__DMA0IFG (0x1E00) /* DMA channel 1 transfer select 30: previous DMA channel DMA0IFG */ +#define DMA1TSEL__DMAE0 (0x1F00) /* DMA channel 1 transfer select 31: ext. Trigger (DMAE0) */ + +#define DMA2TSEL__DMA_REQ (0x0000) /* DMA channel 2 transfer select 0: DMA_REQ (sw) */ +#define DMA2TSEL__TA0CCR0 (0x0001) /* DMA channel 2 transfer select 1: Timer0_A (TA0CCR0.IFG) */ +#define DMA2TSEL__TA0CCR2 (0x0002) /* DMA channel 2 transfer select 2: Timer0_A (TA0CCR2.IFG) */ +#define DMA2TSEL__TA1CCR0 (0x0003) /* DMA channel 2 transfer select 3: Timer1_A (TA1CCR0.IFG) */ +#define DMA2TSEL__TA1CCR2 (0x0004) /* DMA channel 2 transfer select 4: Timer1_A (TA1CCR2.IFG) */ +#define DMA2TSEL__TA2CCR0 (0x0005) /* DMA channel 2 transfer select 5: Timer2_A (TA2CCR0.IFG) */ +#define DMA2TSEL__TA2CCR2 (0x0006) /* DMA channel 2 transfer select 6: Timer2_A (TA2CCR2.IFG) */ +#define DMA2TSEL__TB0CCR0 (0x0007) /* DMA channel 2 transfer select 7: TimerB (TB0CCR0.IFG) */ +#define DMA2TSEL__TB0CCR2 (0x0008) /* DMA channel 2 transfer select 8: TimerB (TB0CCR2.IFG) */ +#define DMA2TSEL__RES9 (0x0009) /* DMA channel 2 transfer select 9: Reserved */ +#define DMA2TSEL__RES10 (0x000A) /* DMA channel 2 transfer select 10: Reserved */ +#define DMA2TSEL__RES11 (0x000B) /* DMA channel 2 transfer select 11: Reserved */ +#define DMA2TSEL__RES12 (0x000C) /* DMA channel 2 transfer select 12: Reserved */ +#define DMA2TSEL__RES13 (0x000D) /* DMA channel 2 transfer select 13: Reserved */ +#define DMA2TSEL__RES14 (0x000E) /* DMA channel 2 transfer select 14: Reserved */ +#define DMA2TSEL__RES15 (0x000F) /* DMA channel 2 transfer select 15: Reserved */ +#define DMA2TSEL__USCIA0RX (0x0010) /* DMA channel 2 transfer select 16: USCIA0 receive */ +#define DMA2TSEL__USCIA0TX (0x0011) /* DMA channel 2 transfer select 17: USCIA0 transmit */ +#define DMA2TSEL__USCIB0RX (0x0012) /* DMA channel 2 transfer select 18: USCIB0 receive */ +#define DMA2TSEL__USCIB0TX (0x0013) /* DMA channel 2 transfer select 19: USCIB0 transmit */ +#define DMA2TSEL__USCIA1RX (0x0014) /* DMA channel 2 transfer select 20: USCIA1 receive */ +#define DMA2TSEL__USCIA1TX (0x0015) /* DMA channel 2 transfer select 21: USCIA1 transmit */ +#define DMA2TSEL__USCIB1RX (0x0016) /* DMA channel 2 transfer select 22: USCIB1 receive */ +#define DMA2TSEL__USCIB1TX (0x0017) /* DMA channel 2 transfer select 23: USCIB1 transmit */ +#define DMA2TSEL__ADC12IFG (0x0018) /* DMA channel 2 transfer select 24: ADC12IFGx */ +#define DMA2TSEL__RES25 (0x0019) /* DMA channel 2 transfer select 25: Reserved */ +#define DMA2TSEL__RES26 (0x001A) /* DMA channel 2 transfer select 26: Reserved */ +#define DMA2TSEL__USB_FNRXD (0x001B) /* DMA channel 2 transfer select 27: USB FNRXD */ +#define DMA2TSEL__USB_READY (0x001C) /* DMA channel 2 transfer select 28: USB ready */ +#define DMA2TSEL__MPY (0x001D) /* DMA channel 2 transfer select 29: Multiplier ready */ +#define DMA2TSEL__DMA1IFG (0x001E) /* DMA channel 2 transfer select 30: previous DMA channel DMA1IFG */ +#define DMA2TSEL__DMAE0 (0x001F) /* DMA channel 2 transfer select 31: ext. Trigger (DMAE0) */ + +/************************************************************* +* Flash Memory +*************************************************************/ + +#define FCTL1 0x0140 /* FLASH Control 1 */ +//sfrbw FCTL2 (0x0142) /* FLASH Control 2 */ +#define FCTL3 0x0144 /* FLASH Control 3 */ +#define FCTL4 0x0146 /* FLASH Control 4 */ + +#define FRPW (0x9600) /* Flash password returned by read */ +#define FWPW (0xA500) /* Flash password for write */ +#define FXPW (0x3300) /* for use with XOR instruction */ +#define FRKEY (0x9600) /* (legacy definition) Flash key returned by read */ +#define FWKEY (0xA500) /* (legacy definition) Flash key for write */ +#define FXKEY (0x3300) /* (legacy definition) for use with XOR instruction */ + +/* FCTL1 Control Bits */ +//#define RESERVED (0x0001) /* Reserved */ +#define ERASE (0x0002) /* Enable bit for Flash segment erase */ +#define MERAS (0x0004) /* Enable bit for Flash mass erase */ +//#define RESERVED (0x0008) /* Reserved */ +//#define RESERVED (0x0010) /* Reserved */ +#define SWRT (0x0020) /* Smart Write enable */ +#define WRT (0x0040) /* Enable bit for Flash write */ +#define BLKWRT (0x0080) /* Enable bit for Flash segment write */ + +/* FCTL1 Control Bits */ +//#define RESERVED (0x0001) /* Reserved */ +#define ERASE_L (0x0002) /* Enable bit for Flash segment erase */ +#define MERAS_L (0x0004) /* Enable bit for Flash mass erase */ +//#define RESERVED (0x0008) /* Reserved */ +//#define RESERVED (0x0010) /* Reserved */ +#define SWRT_L (0x0020) /* Smart Write enable */ +#define WRT_L (0x0040) /* Enable bit for Flash write */ +#define BLKWRT_L (0x0080) /* Enable bit for Flash segment write */ + + +/* FCTL3 Control Bits */ +#define BUSY (0x0001) /* Flash busy: 1 */ +#define KEYV (0x0002) /* Flash Key violation flag */ +#define ACCVIFG (0x0004) /* Flash Access violation flag */ +#define WAIT (0x0008) /* Wait flag for segment write */ +#define LOCK (0x0010) /* Lock bit: 1 - Flash is locked (read only) */ +#define EMEX (0x0020) /* Flash Emergency Exit */ +#define LOCKA (0x0040) /* Segment A Lock bit: read = 1 - Segment is locked (read only) */ +//#define RESERVED (0x0080) /* Reserved */ + +/* FCTL3 Control Bits */ +#define BUSY_L (0x0001) /* Flash busy: 1 */ +#define KEYV_L (0x0002) /* Flash Key violation flag */ +#define ACCVIFG_L (0x0004) /* Flash Access violation flag */ +#define WAIT_L (0x0008) /* Wait flag for segment write */ +#define LOCK_L (0x0010) /* Lock bit: 1 - Flash is locked (read only) */ +#define EMEX_L (0x0020) /* Flash Emergency Exit */ +#define LOCKA_L (0x0040) /* Segment A Lock bit: read = 1 - Segment is locked (read only) */ +//#define RESERVED (0x0080) /* Reserved */ + + +/* FCTL4 Control Bits */ +#define VPE (0x0001) /* Voltage Changed during Program Error Flag */ +#define MGR0 (0x0010) /* Marginal read 0 mode. */ +#define MGR1 (0x0020) /* Marginal read 1 mode. */ +#define LOCKINFO (0x0080) /* Lock INFO Memory bit: read = 1 - Segment is locked (read only) */ + +/* FCTL4 Control Bits */ +#define VPE_L (0x0001) /* Voltage Changed during Program Error Flag */ +#define MGR0_L (0x0010) /* Marginal read 0 mode. */ +#define MGR1_L (0x0020) /* Marginal read 1 mode. */ +#define LOCKINFO_L (0x0080) /* Lock INFO Memory bit: read = 1 - Segment is locked (read only) */ + + +/************************************************************ +* HARDWARE MULTIPLIER 32Bit +************************************************************/ + +#define MPY 0x04C0 /* Multiply Unsigned/Operand 1 */ +#define MPYS 0x04C2 /* Multiply Signed/Operand 1 */ +#define MAC 0x04C4 /* Multiply Unsigned and Accumulate/Operand 1 */ +#define MACS 0x04C6 /* Multiply Signed and Accumulate/Operand 1 */ +#define OP2 0x04C8 /* Operand 2 */ +#define RESLO 0x04CA /* Result Low Word */ +#define RESHI 0x04CC /* Result High Word */ +#define SUMEXT 0x04CE /* Sum Extend */ + +#define MPY32L 0x04D0 /* 32-bit operand 1 - multiply - low word */ +#define MPY32H 0x04D2 /* 32-bit operand 1 - multiply - high word */ +#define MPYS32L 0x04D4 /* 32-bit operand 1 - signed multiply - low word */ +#define MPYS32H 0x04D6 /* 32-bit operand 1 - signed multiply - high word */ +#define MAC32L 0x04D8 /* 32-bit operand 1 - multiply accumulate - low word */ +#define MAC32H 0x04DA /* 32-bit operand 1 - multiply accumulate - high word */ +#define MACS32L 0x04DC /* 32-bit operand 1 - signed multiply accumulate - low word */ +#define MACS32H 0x04DE /* 32-bit operand 1 - signed multiply accumulate - high word */ +#define OP2L 0x04E0 /* 32-bit operand 2 - low word */ +#define OP2H 0x04E2 /* 32-bit operand 2 - high word */ +#define RES0 0x04E4 /* 32x32-bit result 0 - least significant word */ +#define RES1 0x04E6 /* 32x32-bit result 1 */ +#define RES2 0x04E8 /* 32x32-bit result 2 */ +#define RES3 0x04EA /* 32x32-bit result 3 - most significant word */ +#define MPY32CTL0 0x04EC /* MPY32 Control Register 0 */ + +#define MPY_B MPY_L /* Multiply Unsigned/Operand 1 (Byte Access) */ +#define MPYS_B MPYS_L /* Multiply Signed/Operand 1 (Byte Access) */ +#define MAC_B MAC_L /* Multiply Unsigned and Accumulate/Operand 1 (Byte Access) */ +#define MACS_B MACS_L /* Multiply Signed and Accumulate/Operand 1 (Byte Access) */ +#define OP2_B OP2_L /* Operand 2 (Byte Access) */ +#define MPY32L_B MPY32L_L /* 32-bit operand 1 - multiply - low word (Byte Access) */ +#define MPY32H_B MPY32H_L /* 32-bit operand 1 - multiply - high word (Byte Access) */ +#define MPYS32L_B MPYS32L_L /* 32-bit operand 1 - signed multiply - low word (Byte Access) */ +#define MPYS32H_B MPYS32H_L /* 32-bit operand 1 - signed multiply - high word (Byte Access) */ +#define MAC32L_B MAC32L_L /* 32-bit operand 1 - multiply accumulate - low word (Byte Access) */ +#define MAC32H_B MAC32H_L /* 32-bit operand 1 - multiply accumulate - high word (Byte Access) */ +#define MACS32L_B MACS32L_L /* 32-bit operand 1 - signed multiply accumulate - low word (Byte Access) */ +#define MACS32H_B MACS32H_L /* 32-bit operand 1 - signed multiply accumulate - high word (Byte Access) */ +#define OP2L_B OP2L_L /* 32-bit operand 2 - low word (Byte Access) */ +#define OP2H_B OP2H_L /* 32-bit operand 2 - high word (Byte Access) */ + + +/* MPY32CTL0 Control Bits */ +#define MPYC (0x0001) /* Carry of the multiplier */ +//#define RESERVED (0x0002) /* Reserved */ +#define MPYFRAC (0x0004) /* Fractional mode */ +#define MPYSAT (0x0008) /* Saturation mode */ +#define MPYM0 (0x0010) /* Multiplier mode Bit:0 */ +#define MPYM1 (0x0020) /* Multiplier mode Bit:1 */ +#define OP1_32 (0x0040) /* Bit-width of operand 1 0:16Bit / 1:32Bit */ +#define OP2_32 (0x0080) /* Bit-width of operand 2 0:16Bit / 1:32Bit */ +#define MPYDLYWRTEN (0x0100) /* Delayed write enable */ +#define MPYDLY32 (0x0200) /* Delayed write mode */ + +/* MPY32CTL0 Control Bits */ +#define MPYC_L (0x0001) /* Carry of the multiplier */ +//#define RESERVED (0x0002) /* Reserved */ +#define MPYFRAC_L (0x0004) /* Fractional mode */ +#define MPYSAT_L (0x0008) /* Saturation mode */ +#define MPYM0_L (0x0010) /* Multiplier mode Bit:0 */ +#define MPYM1_L (0x0020) /* Multiplier mode Bit:1 */ +#define OP1_32_L (0x0040) /* Bit-width of operand 1 0:16Bit / 1:32Bit */ +#define OP2_32_L (0x0080) /* Bit-width of operand 2 0:16Bit / 1:32Bit */ + +/* MPY32CTL0 Control Bits */ +//#define RESERVED (0x0002) /* Reserved */ +#define MPYDLYWRTEN_H (0x0001) /* Delayed write enable */ +#define MPYDLY32_H (0x0002) /* Delayed write mode */ + +#define MPYM_0 (0x0000) /* Multiplier mode: MPY */ +#define MPYM_1 (0x0010) /* Multiplier mode: MPYS */ +#define MPYM_2 (0x0020) /* Multiplier mode: MAC */ +#define MPYM_3 (0x0030) /* Multiplier mode: MACS */ +#define MPYM__MPY (0x0000) /* Multiplier mode: MPY */ +#define MPYM__MPYS (0x0010) /* Multiplier mode: MPYS */ +#define MPYM__MAC (0x0020) /* Multiplier mode: MAC */ +#define MPYM__MACS (0x0030) /* Multiplier mode: MACS */ + +/************************************************************ +* DIGITAL I/O Port1/2 Pull up / Pull down Resistors +************************************************************/ + +#define PAIN 0x0200 /* Port A Input */ +#define PAOUT 0x0202 /* Port A Output */ +#define PADIR 0x0204 /* Port A Direction */ +#define PAREN 0x0206 /* Port A Resistor Enable */ +#define PADS 0x0208 /* Port A Drive Strenght */ +#define PASEL 0x020A /* Port A Selection */ +#define PASEL_L (PASEL) +#define PASEL_H (PASEL+1) +#define PAIES 0x0218 /* Port A Interrupt Edge Select */ +#define PAIE 0x021A /* Port A Interrupt Enable */ +#define PAIFG 0x021C /* Port A Interrupt Flag */ + +#define P1IV 0x020E /* Port 1 Interrupt Vector Word */ +#define P2IV 0x021E /* Port 2 Interrupt Vector Word */ +#define P1IN (PAIN_L) /* Port 1 Input */ +#define P1OUT (PAOUT_L) /* Port 1 Output */ +#define P1DIR (PADIR_L) /* Port 1 Direction */ +#define P1REN (PAREN_L) /* Port 1 Resistor Enable */ +#define P1DS (PADS_L) /* Port 1 Drive Strenght */ +#define P1SEL (PASEL_L) /* Port 1 Selection */ +#define P1IES (PAIES_L) /* Port 1 Interrupt Edge Select */ +#define P1IE (PAIE_L) /* Port 1 Interrupt Enable */ +#define P1IFG (PAIFG_L) /* Port 1 Interrupt Flag */ + +//Definitions for P1IV +#define P1IV_NONE (0x0000) /* No Interrupt pending */ +#define P1IV_P1IFG0 (0x0002) /* P1IV P1IFG.0 */ +#define P1IV_P1IFG1 (0x0004) /* P1IV P1IFG.1 */ +#define P1IV_P1IFG2 (0x0006) /* P1IV P1IFG.2 */ +#define P1IV_P1IFG3 (0x0008) /* P1IV P1IFG.3 */ +#define P1IV_P1IFG4 (0x000A) /* P1IV P1IFG.4 */ +#define P1IV_P1IFG5 (0x000C) /* P1IV P1IFG.5 */ +#define P1IV_P1IFG6 (0x000E) /* P1IV P1IFG.6 */ +#define P1IV_P1IFG7 (0x0010) /* P1IV P1IFG.7 */ + + +#define P2IN (PAIN_H) /* Port 2 Input */ +#define P2OUT (PAOUT_H) /* Port 2 Output */ +#define P2DIR (PADIR_H) /* Port 2 Direction */ +#define P2REN (PAREN_H) /* Port 2 Resistor Enable */ +#define P2DS (PADS_H) /* Port 2 Drive Strenght */ +#define P2SEL (PASEL_H) /* Port 2 Selection */ +#define P2IES (PAIES_H) /* Port 2 Interrupt Edge Select */ +#define P2IE (PAIE_H) /* Port 2 Interrupt Enable */ +#define P2IFG (PAIFG_H) /* Port 2 Interrupt Flag */ + +//Definitions for P2IV +#define P2IV_NONE (0x0000) /* No Interrupt pending */ +#define P2IV_P2IFG0 (0x0002) /* P2IV P2IFG.0 */ +#define P2IV_P2IFG1 (0x0004) /* P2IV P2IFG.1 */ +#define P2IV_P2IFG2 (0x0006) /* P2IV P2IFG.2 */ +#define P2IV_P2IFG3 (0x0008) /* P2IV P2IFG.3 */ +#define P2IV_P2IFG4 (0x000A) /* P2IV P2IFG.4 */ +#define P2IV_P2IFG5 (0x000C) /* P2IV P2IFG.5 */ +#define P2IV_P2IFG6 (0x000E) /* P2IV P2IFG.6 */ +#define P2IV_P2IFG7 (0x0010) /* P2IV P2IFG.7 */ + + + +/************************************************************ +* DIGITAL I/O Port3/4 Pull up / Pull down Resistors +************************************************************/ + +#define PBIN 0x0220 /* Port B Input */ +#define PBOUT 0x0222 /* Port B Output */ +#define PBDIR 0x0224 /* Port B Direction */ +#define PBREN 0x0226 /* Port B Resistor Enable */ +#define PBDS 0x0228 /* Port B Drive Strenght */ +#define PBSEL 0x022A /* Port B Selection */ +#define PBSEL_H (PBSEL+1) + +#define P3IN (PBIN_L) /* Port 3 Input */ +#define P3OUT (PBOUT_L) /* Port 3 Output */ +#define P3DIR (PBDIR_L) /* Port 3 Direction */ +#define P3REN (PBREN_L) /* Port 3 Resistor Enable */ +#define P3DS (PBDS_L) /* Port 3 Drive Strenght */ +#define P3SEL (PBSEL_L) /* Port 3 Selection */ + + +#define P4IN (PBIN_H) /* Port 4 Input */ +#define P4OUT (PBOUT_H) /* Port 4 Output */ +#define P4DIR (PBDIR_H) /* Port 4 Direction */ +#define P4REN (PBREN_H) /* Port 4 Resistor Enable */ +#define P4DS (PBDS_H) /* Port 4 Drive Strenght */ +#define P4SEL (PBSEL_H) /* Port 4 Selection */ + + + +/************************************************************ +* DIGITAL I/O Port5/6 Pull up / Pull down Resistors +************************************************************/ + +#define PCIN 0x0240 /* Port C Input */ +#define PCOUT 0x0242 /* Port C Output */ +#define PCDIR 0x0244 /* Port C Direction */ +#define PCREN 0x0246 /* Port C Resistor Enable */ +#define PCDS 0x0248 /* Port C Drive Strenght */ +#define PCSEL 0x024A /* Port C Selection */ + +#define P5IN (PCIN_L) /* Port 5 Input */ +#define P5OUT (PCOUT_L) /* Port 5 Output */ +#define P5DIR (PCDIR_L) /* Port 5 Direction */ +#define P5REN (PCREN_L) /* Port 5 Resistor Enable */ +#define P5DS (PCDS_L) /* Port 5 Drive Strenght */ +#define P5SEL (PCSEL_L) /* Port 5 Selection */ + + +#define P6IN (PCIN_H) /* Port 6 Input */ +#define P6OUT (PCOUT_H) /* Port 6 Output */ +#define P6DIR (PCDIR_H) /* Port 6 Direction */ +#define P6REN (PCREN_H) /* Port 6 Resistor Enable */ +#define P6DS (PCDS_H) /* Port 6 Drive Strenght */ +#define P6SEL (PCSEL_H) /* Port 6 Selection */ + + + +/************************************************************ +* DIGITAL I/O Port7/8 Pull up / Pull down Resistors +************************************************************/ + +#define PDIN 0x0260 /* Port D Input */ +#define PDOUT 0x0262 /* Port D Output */ +#define PDDIR 0x0264 /* Port D Direction */ +#define PDREN 0x0266 /* Port D Resistor Enable */ +#define PDDS 0x0268 /* Port D Drive Strenght */ +#define PDSEL 0x026A /* Port D Selection */ + +#define P7IN (PDIN_L) /* Port 7 Input */ +#define P7OUT (PDOUT_L) /* Port 7 Output */ +#define P7DIR (PDDIR_L) /* Port 7 Direction */ +#define P7REN (PDREN_L) /* Port 7 Resistor Enable */ +#define P7DS (PDDS_L) /* Port 7 Drive Strenght */ +#define P7SEL (PDSEL_L) /* Port 7 Selection */ + + +#define P8IN (PDIN_H) /* Port 8 Input */ +#define P8OUT (PDOUT_H) /* Port 8 Output */ +#define P8DIR (PDDIR_H) /* Port 8 Direction */ +#define P8REN (PDREN_H) /* Port 8 Resistor Enable */ +#define P8DS (PDDS_H) /* Port 8 Drive Strenght */ +#define P8SEL (PDSEL_H) /* Port 8 Selection */ + + + +/************************************************************ +* DIGITAL I/O PortJ Pull up / Pull down Resistors +************************************************************/ + +#define PJIN 0x0320 /* Port J Input */ +#define PJOUT 0x0322 /* Port J Output */ +#define PJDIR 0x0324 /* Port J Direction */ +#define PJREN 0x0326 /* Port J Resistor Enable */ +#define PJDS 0x0328 /* Port J Drive Strenght */ + +/************************************************************ +* PORT MAPPING CONTROLLER +************************************************************/ +#define PMAPKEYID 0x01C0 /* Port Mapping Key register */ +#define PMAPCTL 0x01C2 /* Port Mapping control register */ + +#define PMAPKEY (0x2D52) /* Port Mapping Key */ +#define PMAPPWD PMAPKEYID /* Legacy Definition: Mapping Key register */ +#define PMAPPW (0x2D52) /* Legacy Definition: Port Mapping Password */ + +/* PMAPCTL Control Bits */ +#define PMAPLOCKED (0x0001) /* Port Mapping Lock bit. Read only */ +#define PMAPRECFG (0x0002) /* Port Mapping re-configuration control bit */ + +/* PMAPCTL Control Bits */ +#define PMAPLOCKED_L (0x0001) /* Port Mapping Lock bit. Read only */ +#define PMAPRECFG_L (0x0002) /* Port Mapping re-configuration control bit */ + + +/************************************************************ +* PORT 4 MAPPING CONTROLLER +************************************************************/ + +#define P4MAP01 0x01E0 /* Port P4.0/1 mapping register */ +#define P4MAP23 0x01E2 /* Port P4.2/3 mapping register */ +#define P4MAP45 0x01E4 /* Port P4.4/5 mapping register */ +#define P4MAP67 0x01E6 /* Port P4.6/7 mapping register */ + +#define P4MAP0 P4MAP01_L /* Port P4.0 mapping register */ +#define P4MAP1 P4MAP01_H /* Port P4.1 mapping register */ +#define P4MAP2 P4MAP23_L /* Port P4.2 mapping register */ +#define P4MAP3 P4MAP23_H /* Port P4.3 mapping register */ +#define P4MAP4 P4MAP45_L /* Port P4.4 mapping register */ +#define P4MAP5 P4MAP45_H /* Port P4.5 mapping register */ +#define P4MAP6 P4MAP67_L /* Port P4.6 mapping register */ +#define P4MAP7 P4MAP67_H /* Port P4.7 mapping register */ + +#define PM_NONE 0 +#define PM_CBOUT0 1 +#define PM_TB0CLK 1 +#define PM_ADC12CLK 2 +#define PM_DMAE0 2 +#define PM_SVMOUT 3 +#define PM_TB0OUTH 3 +#define PM_TB0CCR0A 4 +#define PM_TB0CCR1A 5 +#define PM_TB0CCR2A 6 +#define PM_TB0CCR3A 7 +#define PM_TB0CCR4A 8 +#define PM_TB0CCR5A 9 +#define PM_TB0CCR6A 10 +#define PM_UCA1RXD 11 +#define PM_UCA1SOMI 11 +#define PM_UCA1TXD 12 +#define PM_UCA1SIMO 12 +#define PM_UCA1CLK 13 +#define PM_UCB1STE 13 +#define PM_UCB1SOMI 14 +#define PM_UCB1SCL 14 +#define PM_UCB1SIMO 15 +#define PM_UCB1SDA 15 +#define PM_UCB1CLK 16 +#define PM_UCA1STE 16 +#define PM_CBOUT1 17 +#define PM_MCLK 18 +#define PM_ANALOG 31 + +/************************************************************ +* PMM - Power Management System +************************************************************/ + +#define PMMCTL0 0x0120 /* PMM Control 0 */ +#define PMMCTL1 0x0122 /* PMM Control 1 */ +#define SVSMHCTL 0x0124 /* SVS and SVM high side control register */ +#define SVSMLCTL 0x0126 /* SVS and SVM low side control register */ +#define SVSMIO 0x0128 /* SVSIN and SVSOUT control register */ +#define PMMIFG 0x012C /* PMM Interrupt Flag */ +#define PMMRIE 0x012E /* PMM and RESET Interrupt Enable */ +#define PM5CTL0 0x0130 /* PMM Power Mode 5 Control Register 0 */ + +#define PMMPW (0xA500) /* PMM Register Write Password */ +#define PMMPW_H (0xA5) /* PMM Register Write Password for high word access */ + +/* PMMCTL0 Control Bits */ +#define PMMCOREV0 (0x0001) /* PMM Core Voltage Bit: 0 */ +#define PMMCOREV1 (0x0002) /* PMM Core Voltage Bit: 1 */ +#define PMMSWBOR (0x0004) /* PMM Software BOR */ +#define PMMSWPOR (0x0008) /* PMM Software POR */ +#define PMMREGOFF (0x0010) /* PMM Turn Regulator off */ +#define PMMHPMRE (0x0080) /* PMM Global High Power Module Request Enable */ + +/* PMMCTL0 Control Bits */ +#define PMMCOREV0_L (0x0001) /* PMM Core Voltage Bit: 0 */ +#define PMMCOREV1_L (0x0002) /* PMM Core Voltage Bit: 1 */ +#define PMMSWBOR_L (0x0004) /* PMM Software BOR */ +#define PMMSWPOR_L (0x0008) /* PMM Software POR */ +#define PMMREGOFF_L (0x0010) /* PMM Turn Regulator off */ +#define PMMHPMRE_L (0x0080) /* PMM Global High Power Module Request Enable */ + + +#define PMMCOREV_0 (0x0000) /* PMM Core Voltage 0 (1.35V) */ +#define PMMCOREV_1 (0x0001) /* PMM Core Voltage 1 (1.55V) */ +#define PMMCOREV_2 (0x0002) /* PMM Core Voltage 2 (1.75V) */ +#define PMMCOREV_3 (0x0003) /* PMM Core Voltage 3 (1.85V) */ + + +/* PMMCTL1 Control Bits */ +#define PMMREFMD (0x0001) /* PMM Reference Mode */ +#define PMMCMD0 (0x0010) /* PMM Voltage Regulator Current Mode Bit: 0 */ +#define PMMCMD1 (0x0020) /* PMM Voltage Regulator Current Mode Bit: 1 */ + +/* PMMCTL1 Control Bits */ +#define PMMREFMD_L (0x0001) /* PMM Reference Mode */ +#define PMMCMD0_L (0x0010) /* PMM Voltage Regulator Current Mode Bit: 0 */ +#define PMMCMD1_L (0x0020) /* PMM Voltage Regulator Current Mode Bit: 1 */ + + +/* SVSMHCTL Control Bits */ +#define SVSMHRRL0 (0x0001) /* SVS and SVM high side Reset Release Voltage Level Bit: 0 */ +#define SVSMHRRL1 (0x0002) /* SVS and SVM high side Reset Release Voltage Level Bit: 1 */ +#define SVSMHRRL2 (0x0004) /* SVS and SVM high side Reset Release Voltage Level Bit: 2 */ +#define SVSMHDLYST (0x0008) /* SVS and SVM high side delay status */ +#define SVSHMD (0x0010) /* SVS high side mode */ +#define SVSMHEVM (0x0040) /* SVS and SVM high side event mask */ +#define SVSMHACE (0x0080) /* SVS and SVM high side auto control enable */ +#define SVSHRVL0 (0x0100) /* SVS high side reset voltage level Bit: 0 */ +#define SVSHRVL1 (0x0200) /* SVS high side reset voltage level Bit: 1 */ +#define SVSHE (0x0400) /* SVS high side enable */ +#define SVSHFP (0x0800) /* SVS high side full performace mode */ +#define SVMHOVPE (0x1000) /* SVM high side over-voltage enable */ +#define SVMHE (0x4000) /* SVM high side enable */ +#define SVMHFP (0x8000) /* SVM high side full performace mode */ + +/* SVSMHCTL Control Bits */ +#define SVSMHRRL0_L (0x0001) /* SVS and SVM high side Reset Release Voltage Level Bit: 0 */ +#define SVSMHRRL1_L (0x0002) /* SVS and SVM high side Reset Release Voltage Level Bit: 1 */ +#define SVSMHRRL2_L (0x0004) /* SVS and SVM high side Reset Release Voltage Level Bit: 2 */ +#define SVSMHDLYST_L (0x0008) /* SVS and SVM high side delay status */ +#define SVSHMD_L (0x0010) /* SVS high side mode */ +#define SVSMHEVM_L (0x0040) /* SVS and SVM high side event mask */ +#define SVSMHACE_L (0x0080) /* SVS and SVM high side auto control enable */ + +/* SVSMHCTL Control Bits */ +#define SVSHRVL0_H (0x0001) /* SVS high side reset voltage level Bit: 0 */ +#define SVSHRVL1_H (0x0002) /* SVS high side reset voltage level Bit: 1 */ +#define SVSHE_H (0x0004) /* SVS high side enable */ +#define SVSHFP_H (0x0008) /* SVS high side full performace mode */ +#define SVMHOVPE_H (0x0010) /* SVM high side over-voltage enable */ +#define SVMHE_H (0x0040) /* SVM high side enable */ +#define SVMHFP_H (0x0080) /* SVM high side full performace mode */ + +#define SVSMHRRL_0 (0x0000) /* SVS and SVM high side Reset Release Voltage Level 0 */ +#define SVSMHRRL_1 (0x0001) /* SVS and SVM high side Reset Release Voltage Level 1 */ +#define SVSMHRRL_2 (0x0002) /* SVS and SVM high side Reset Release Voltage Level 2 */ +#define SVSMHRRL_3 (0x0003) /* SVS and SVM high side Reset Release Voltage Level 3 */ +#define SVSMHRRL_4 (0x0004) /* SVS and SVM high side Reset Release Voltage Level 4 */ +#define SVSMHRRL_5 (0x0005) /* SVS and SVM high side Reset Release Voltage Level 5 */ +#define SVSMHRRL_6 (0x0006) /* SVS and SVM high side Reset Release Voltage Level 6 */ +#define SVSMHRRL_7 (0x0007) /* SVS and SVM high side Reset Release Voltage Level 7 */ + +#define SVSHRVL_0 (0x0000) /* SVS high side Reset Release Voltage Level 0 */ +#define SVSHRVL_1 (0x0100) /* SVS high side Reset Release Voltage Level 1 */ +#define SVSHRVL_2 (0x0200) /* SVS high side Reset Release Voltage Level 2 */ +#define SVSHRVL_3 (0x0300) /* SVS high side Reset Release Voltage Level 3 */ + + +/* SVSMLCTL Control Bits */ +#define SVSMLRRL0 (0x0001) /* SVS and SVM low side Reset Release Voltage Level Bit: 0 */ +#define SVSMLRRL1 (0x0002) /* SVS and SVM low side Reset Release Voltage Level Bit: 1 */ +#define SVSMLRRL2 (0x0004) /* SVS and SVM low side Reset Release Voltage Level Bit: 2 */ +#define SVSMLDLYST (0x0008) /* SVS and SVM low side delay status */ +#define SVSLMD (0x0010) /* SVS low side mode */ +#define SVSMLEVM (0x0040) /* SVS and SVM low side event mask */ +#define SVSMLACE (0x0080) /* SVS and SVM low side auto control enable */ +#define SVSLRVL0 (0x0100) /* SVS low side reset voltage level Bit: 0 */ +#define SVSLRVL1 (0x0200) /* SVS low side reset voltage level Bit: 1 */ +#define SVSLE (0x0400) /* SVS low side enable */ +#define SVSLFP (0x0800) /* SVS low side full performace mode */ +#define SVMLOVPE (0x1000) /* SVM low side over-voltage enable */ +#define SVMLE (0x4000) /* SVM low side enable */ +#define SVMLFP (0x8000) /* SVM low side full performace mode */ + +/* SVSMLCTL Control Bits */ +#define SVSMLRRL0_L (0x0001) /* SVS and SVM low side Reset Release Voltage Level Bit: 0 */ +#define SVSMLRRL1_L (0x0002) /* SVS and SVM low side Reset Release Voltage Level Bit: 1 */ +#define SVSMLRRL2_L (0x0004) /* SVS and SVM low side Reset Release Voltage Level Bit: 2 */ +#define SVSMLDLYST_L (0x0008) /* SVS and SVM low side delay status */ +#define SVSLMD_L (0x0010) /* SVS low side mode */ +#define SVSMLEVM_L (0x0040) /* SVS and SVM low side event mask */ +#define SVSMLACE_L (0x0080) /* SVS and SVM low side auto control enable */ + +/* SVSMLCTL Control Bits */ +#define SVSLRVL0_H (0x0001) /* SVS low side reset voltage level Bit: 0 */ +#define SVSLRVL1_H (0x0002) /* SVS low side reset voltage level Bit: 1 */ +#define SVSLE_H (0x0004) /* SVS low side enable */ +#define SVSLFP_H (0x0008) /* SVS low side full performace mode */ +#define SVMLOVPE_H (0x0010) /* SVM low side over-voltage enable */ +#define SVMLE_H (0x0040) /* SVM low side enable */ +#define SVMLFP_H (0x0080) /* SVM low side full performace mode */ + +#define SVSMLRRL_0 (0x0000) /* SVS and SVM low side Reset Release Voltage Level 0 */ +#define SVSMLRRL_1 (0x0001) /* SVS and SVM low side Reset Release Voltage Level 1 */ +#define SVSMLRRL_2 (0x0002) /* SVS and SVM low side Reset Release Voltage Level 2 */ +#define SVSMLRRL_3 (0x0003) /* SVS and SVM low side Reset Release Voltage Level 3 */ +#define SVSMLRRL_4 (0x0004) /* SVS and SVM low side Reset Release Voltage Level 4 */ +#define SVSMLRRL_5 (0x0005) /* SVS and SVM low side Reset Release Voltage Level 5 */ +#define SVSMLRRL_6 (0x0006) /* SVS and SVM low side Reset Release Voltage Level 6 */ +#define SVSMLRRL_7 (0x0007) /* SVS and SVM low side Reset Release Voltage Level 7 */ + +#define SVSLRVL_0 (0x0000) /* SVS low side Reset Release Voltage Level 0 */ +#define SVSLRVL_1 (0x0100) /* SVS low side Reset Release Voltage Level 1 */ +#define SVSLRVL_2 (0x0200) /* SVS low side Reset Release Voltage Level 2 */ +#define SVSLRVL_3 (0x0300) /* SVS low side Reset Release Voltage Level 3 */ + + +/* SVSMIO Control Bits */ +#define SVMLOE (0x0008) /* SVM low side output enable */ +#define SVMLVLROE (0x0010) /* SVM low side voltage level reached output enable */ +#define SVMOUTPOL (0x0020) /* SVMOUT pin polarity */ +#define SVMHOE (0x0800) /* SVM high side output enable */ +#define SVMHVLROE (0x1000) /* SVM high side voltage level reached output enable */ + +/* SVSMIO Control Bits */ +#define SVMLOE_L (0x0008) /* SVM low side output enable */ +#define SVMLVLROE_L (0x0010) /* SVM low side voltage level reached output enable */ +#define SVMOUTPOL_L (0x0020) /* SVMOUT pin polarity */ + +/* SVSMIO Control Bits */ +#define SVMHOE_H (0x0008) /* SVM high side output enable */ +#define SVMHVLROE_H (0x0010) /* SVM high side voltage level reached output enable */ + + +/* PMMIFG Control Bits */ +#define SVSMLDLYIFG (0x0001) /* SVS and SVM low side Delay expired interrupt flag */ +#define SVMLIFG (0x0002) /* SVM low side interrupt flag */ +#define SVMLVLRIFG (0x0004) /* SVM low side Voltage Level Reached interrupt flag */ +#define SVSMHDLYIFG (0x0010) /* SVS and SVM high side Delay expired interrupt flag */ +#define SVMHIFG (0x0020) /* SVM high side interrupt flag */ +#define SVMHVLRIFG (0x0040) /* SVM high side Voltage Level Reached interrupt flag */ +#define PMMBORIFG (0x0100) /* PMM Software BOR interrupt flag */ +#define PMMRSTIFG (0x0200) /* PMM RESET pin interrupt flag */ +#define PMMPORIFG (0x0400) /* PMM Software POR interrupt flag */ +#define SVSHIFG (0x1000) /* SVS low side interrupt flag */ +#define SVSLIFG (0x2000) /* SVS high side interrupt flag */ +#define PMMLPM5IFG (0x8000) /* LPM5 indication Flag */ + +/* PMMIFG Control Bits */ +#define SVSMLDLYIFG_L (0x0001) /* SVS and SVM low side Delay expired interrupt flag */ +#define SVMLIFG_L (0x0002) /* SVM low side interrupt flag */ +#define SVMLVLRIFG_L (0x0004) /* SVM low side Voltage Level Reached interrupt flag */ +#define SVSMHDLYIFG_L (0x0010) /* SVS and SVM high side Delay expired interrupt flag */ +#define SVMHIFG_L (0x0020) /* SVM high side interrupt flag */ +#define SVMHVLRIFG_L (0x0040) /* SVM high side Voltage Level Reached interrupt flag */ + +/* PMMIFG Control Bits */ +#define PMMBORIFG_H (0x0001) /* PMM Software BOR interrupt flag */ +#define PMMRSTIFG_H (0x0002) /* PMM RESET pin interrupt flag */ +#define PMMPORIFG_H (0x0004) /* PMM Software POR interrupt flag */ +#define SVSHIFG_H (0x0010) /* SVS low side interrupt flag */ +#define SVSLIFG_H (0x0020) /* SVS high side interrupt flag */ +#define PMMLPM5IFG_H (0x0080) /* LPM5 indication Flag */ + +#define PMMRSTLPM5IFG PMMLPM5IFG /* LPM5 indication Flag */ + + +/* PMMIE and RESET Control Bits */ +#define SVSMLDLYIE (0x0001) /* SVS and SVM low side Delay expired interrupt enable */ +#define SVMLIE (0x0002) /* SVM low side interrupt enable */ +#define SVMLVLRIE (0x0004) /* SVM low side Voltage Level Reached interrupt enable */ +#define SVSMHDLYIE (0x0010) /* SVS and SVM high side Delay expired interrupt enable */ +#define SVMHIE (0x0020) /* SVM high side interrupt enable */ +#define SVMHVLRIE (0x0040) /* SVM high side Voltage Level Reached interrupt enable */ +#define SVSLPE (0x0100) /* SVS low side POR enable */ +#define SVMLVLRPE (0x0200) /* SVM low side Voltage Level reached POR enable */ +#define SVSHPE (0x1000) /* SVS high side POR enable */ +#define SVMHVLRPE (0x2000) /* SVM high side Voltage Level reached POR enable */ + +/* PMMIE and RESET Control Bits */ +#define SVSMLDLYIE_L (0x0001) /* SVS and SVM low side Delay expired interrupt enable */ +#define SVMLIE_L (0x0002) /* SVM low side interrupt enable */ +#define SVMLVLRIE_L (0x0004) /* SVM low side Voltage Level Reached interrupt enable */ +#define SVSMHDLYIE_L (0x0010) /* SVS and SVM high side Delay expired interrupt enable */ +#define SVMHIE_L (0x0020) /* SVM high side interrupt enable */ +#define SVMHVLRIE_L (0x0040) /* SVM high side Voltage Level Reached interrupt enable */ + +/* PMMIE and RESET Control Bits */ +#define SVSLPE_H (0x0001) /* SVS low side POR enable */ +#define SVMLVLRPE_H (0x0002) /* SVM low side Voltage Level reached POR enable */ +#define SVSHPE_H (0x0010) /* SVS high side POR enable */ +#define SVMHVLRPE_H (0x0020) /* SVM high side Voltage Level reached POR enable */ + +/* PM5CTL0 Power Mode 5 Control Bits */ +#define LOCKLPM5 (0x0001) /* Lock I/O pin configuration upon entry/exit to/from LPM5 */ + +/* PM5CTL0 Power Mode 5 Control Bits */ +#define LOCKLPM5_L (0x0001) /* Lock I/O pin configuration upon entry/exit to/from LPM5 */ + +#define LOCKIO LOCKLPM5 /* Lock I/O pin configuration upon entry/exit to/from LPM5 */ + +/************************************************************* +* RAM Control Module +*************************************************************/ + +#define RCCTL0 0x0158 /* Ram Controller Control Register */ + +/* RCCTL0 Control Bits */ +#define RCRS0OFF (0x0001) /* RAM Controller RAM Sector 0 Off */ +#define RCRS1OFF (0x0002) /* RAM Controller RAM Sector 1 Off */ +#define RCRS2OFF (0x0004) /* RAM Controller RAM Sector 2 Off */ +#define RCRS3OFF (0x0008) /* RAM Controller RAM Sector 3 Off */ +#define RCRS7OFF (0x0080) /* RAM Controller RAM Sector 7 (USB) Off */ + +/* RCCTL0 Control Bits */ +#define RCRS0OFF_L (0x0001) /* RAM Controller RAM Sector 0 Off */ +#define RCRS1OFF_L (0x0002) /* RAM Controller RAM Sector 1 Off */ +#define RCRS2OFF_L (0x0004) /* RAM Controller RAM Sector 2 Off */ +#define RCRS3OFF_L (0x0008) /* RAM Controller RAM Sector 3 Off */ +#define RCRS7OFF_L (0x0080) /* RAM Controller RAM Sector 7 (USB) Off */ + + +#define RCKEY (0x5A00) + +/************************************************************ +* Shared Reference +************************************************************/ + +#define REFCTL0 0x01B0 /* REF Shared Reference control register 0 */ + +/* REFCTL0 Control Bits */ +#define REFON (0x0001) /* REF Reference On */ +#define REFOUT (0x0002) /* REF Reference output Buffer On */ +//#define RESERVED (0x0004) /* Reserved */ +#define REFTCOFF (0x0008) /* REF Temp.Sensor off */ +#define REFVSEL0 (0x0010) /* REF Reference Voltage Level Select Bit:0 */ +#define REFVSEL1 (0x0020) /* REF Reference Voltage Level Select Bit:1 */ +//#define RESERVED (0x0040) /* Reserved */ +#define REFMSTR (0x0080) /* REF Master Control */ +#define REFGENACT (0x0100) /* REF Reference generator active */ +#define REFBGACT (0x0200) /* REF Reference bandgap active */ +#define REFGENBUSY (0x0400) /* REF Reference generator busy */ +#define BGMODE (0x0800) /* REF Bandgap mode */ +//#define RESERVED (0x1000) /* Reserved */ +//#define RESERVED (0x2000) /* Reserved */ +//#define RESERVED (0x4000) /* Reserved */ +//#define RESERVED (0x8000) /* Reserved */ + +/* REFCTL0 Control Bits */ +#define REFON_L (0x0001) /* REF Reference On */ +#define REFOUT_L (0x0002) /* REF Reference output Buffer On */ +//#define RESERVED (0x0004) /* Reserved */ +#define REFTCOFF_L (0x0008) /* REF Temp.Sensor off */ +#define REFVSEL0_L (0x0010) /* REF Reference Voltage Level Select Bit:0 */ +#define REFVSEL1_L (0x0020) /* REF Reference Voltage Level Select Bit:1 */ +//#define RESERVED (0x0040) /* Reserved */ +#define REFMSTR_L (0x0080) /* REF Master Control */ +//#define RESERVED (0x1000) /* Reserved */ +//#define RESERVED (0x2000) /* Reserved */ +//#define RESERVED (0x4000) /* Reserved */ +//#define RESERVED (0x8000) /* Reserved */ + +/* REFCTL0 Control Bits */ +//#define RESERVED (0x0004) /* Reserved */ +//#define RESERVED (0x0040) /* Reserved */ +#define REFGENACT_H (0x0001) /* REF Reference generator active */ +#define REFBGACT_H (0x0002) /* REF Reference bandgap active */ +#define REFGENBUSY_H (0x0004) /* REF Reference generator busy */ +#define BGMODE_H (0x0008) /* REF Bandgap mode */ +//#define RESERVED (0x1000) /* Reserved */ +//#define RESERVED (0x2000) /* Reserved */ +//#define RESERVED (0x4000) /* Reserved */ +//#define RESERVED (0x8000) /* Reserved */ + +#define REFVSEL_0 (0x0000) /* REF Reference Voltage Level Select 1.5V */ +#define REFVSEL_1 (0x0010) /* REF Reference Voltage Level Select 2.0V */ +#define REFVSEL_2 (0x0020) /* REF Reference Voltage Level Select 2.5V */ +#define REFVSEL_3 (0x0030) /* REF Reference Voltage Level Select 2.5V */ + +/************************************************************ +* Real Time Clock +************************************************************/ + +#define RTCCTL01 0x04A0 /* Real Timer Control 0/1 */ +#define RTCCTL23 0x04A2 /* Real Timer Control 2/3 */ +#define RTCPS0CTL 0x04A8 /* Real Timer Prescale Timer 0 Control */ +#define RTCPS1CTL 0x04AA /* Real Timer Prescale Timer 1 Control */ +#define RTCPS 0x04AC /* Real Timer Prescale Timer Control */ +#define RTCIV 0x04AE /* Real Time Clock Interrupt Vector */ +#define RTCTIM0 0x04B0 /* Real Time Clock Time 0 */ +#define RTCTIM1 0x04B2 /* Real Time Clock Time 1 */ +#define RTCDATE 0x04B4 /* Real Time Clock Date */ +#define RTCYEAR 0x04B6 /* Real Time Clock Year */ +#define RTCAMINHR 0x04B8 /* Real Time Clock Alarm Min/Hour */ +#define RTCADOWDAY 0x04BA /* Real Time Clock Alarm day of week/day */ + +#define RTCCTL0 RTCCTL01_L /* Real Time Clock Control 0 */ +#define RTCCTL1 RTCCTL01_H /* Real Time Clock Control 1 */ +#define RTCCTL2 RTCCTL23_L /* Real Time Clock Control 2 */ +#define RTCCTL3 RTCCTL23_H /* Real Time Clock Control 3 */ +#define RTCNT12 RTCTIM0 +#define RTCNT34 RTCTIM1 +#define RTCNT1 RTCTIM0_L +#define RTCNT2 RTCTIM0_H +#define RTCNT3 RTCTIM1_L +#define RTCNT4 RTCTIM1_H +#define RTCSEC RTCTIM0_L +#define RTCMIN RTCTIM0_H +#define RTCHOUR RTCTIM1_L +#define RTCDOW RTCTIM1_H +#define RTCDAY RTCDATE_L +#define RTCMON RTCDATE_H +#define RTCYEARL RTCYEAR_L +#define RTCYEARH RTCYEAR_H +#define RT0PS RTCPS_L +#define RT1PS RTCPS_H +#define RTCAMIN RTCAMINHR_L /* Real Time Clock Alarm Min */ +#define RTCAHOUR RTCAMINHR_H /* Real Time Clock Alarm Hour */ +#define RTCADOW RTCADOWDAY_L /* Real Time Clock Alarm day of week */ +#define RTCADAY RTCADOWDAY_H /* Real Time Clock Alarm day */ + +/* RTCCTL01 Control Bits */ +#define RTCBCD (0x8000) /* RTC BCD 0:Binary / 1:BCD */ +#define RTCHOLD (0x4000) /* RTC Hold */ +#define RTCMODE (0x2000) /* RTC Mode 0:Counter / 1: Calendar */ +#define RTCRDY (0x1000) /* RTC Ready */ +#define RTCSSEL1 (0x0800) /* RTC Source Select 1 */ +#define RTCSSEL0 (0x0400) /* RTC Source Select 0 */ +#define RTCTEV1 (0x0200) /* RTC Time Event 1 */ +#define RTCTEV0 (0x0100) /* RTC Time Event 0 */ +//#define Reserved (0x0080) +#define RTCTEVIE (0x0040) /* RTC Time Event Interrupt Enable Flag */ +#define RTCAIE (0x0020) /* RTC Alarm Interrupt Enable Flag */ +#define RTCRDYIE (0x0010) /* RTC Ready Interrupt Enable Flag */ +//#define Reserved (0x0008) +#define RTCTEVIFG (0x0004) /* RTC Time Event Interrupt Flag */ +#define RTCAIFG (0x0002) /* RTC Alarm Interrupt Flag */ +#define RTCRDYIFG (0x0001) /* RTC Ready Interrupt Flag */ + +/* RTCCTL01 Control Bits */ +//#define Reserved (0x0080) +#define RTCTEVIE_L (0x0040) /* RTC Time Event Interrupt Enable Flag */ +#define RTCAIE_L (0x0020) /* RTC Alarm Interrupt Enable Flag */ +#define RTCRDYIE_L (0x0010) /* RTC Ready Interrupt Enable Flag */ +//#define Reserved (0x0008) +#define RTCTEVIFG_L (0x0004) /* RTC Time Event Interrupt Flag */ +#define RTCAIFG_L (0x0002) /* RTC Alarm Interrupt Flag */ +#define RTCRDYIFG_L (0x0001) /* RTC Ready Interrupt Flag */ + +/* RTCCTL01 Control Bits */ +#define RTCBCD_H (0x0080) /* RTC BCD 0:Binary / 1:BCD */ +#define RTCHOLD_H (0x0040) /* RTC Hold */ +#define RTCMODE_H (0x0020) /* RTC Mode 0:Counter / 1: Calendar */ +#define RTCRDY_H (0x0010) /* RTC Ready */ +#define RTCSSEL1_H (0x0008) /* RTC Source Select 1 */ +#define RTCSSEL0_H (0x0004) /* RTC Source Select 0 */ +#define RTCTEV1_H (0x0002) /* RTC Time Event 1 */ +#define RTCTEV0_H (0x0001) /* RTC Time Event 0 */ +//#define Reserved (0x0080) +//#define Reserved (0x0008) + +#define RTCSSEL_0 (0x0000) /* RTC Source Select ACLK */ +#define RTCSSEL_1 (0x0400) /* RTC Source Select SMCLK */ +#define RTCSSEL_2 (0x0800) /* RTC Source Select RT1PS */ +#define RTCSSEL_3 (0x0C00) /* RTC Source Select RT1PS */ +#define RTCSSEL__ACLK (0x0000) /* RTC Source Select ACLK */ +#define RTCSSEL__SMCLK (0x0400) /* RTC Source Select SMCLK */ +#define RTCSSEL__RT1PS (0x0800) /* RTC Source Select RT1PS */ +#define RTCTEV_0 (0x0000) /* RTC Time Event: 0 (Min. changed) */ +#define RTCTEV_1 (0x0100) /* RTC Time Event: 1 (Hour changed) */ +#define RTCTEV_2 (0x0200) /* RTC Time Event: 2 (12:00 changed) */ +#define RTCTEV_3 (0x0300) /* RTC Time Event: 3 (00:00 changed) */ +#define RTCTEV__MIN (0x0000) /* RTC Time Event: 0 (Min. changed) */ +#define RTCTEV__HOUR (0x0100) /* RTC Time Event: 1 (Hour changed) */ +#define RTCTEV__0000 (0x0200) /* RTC Time Event: 2 (00:00 changed) */ +#define RTCTEV__1200 (0x0300) /* RTC Time Event: 3 (12:00 changed) */ + +/* RTCCTL23 Control Bits */ +#define RTCCALF1 (0x0200) /* RTC Calibration Frequency Bit 1 */ +#define RTCCALF0 (0x0100) /* RTC Calibration Frequency Bit 0 */ +#define RTCCALS (0x0080) /* RTC Calibration Sign */ +//#define Reserved (0x0040) +#define RTCCAL5 (0x0020) /* RTC Calibration Bit 5 */ +#define RTCCAL4 (0x0010) /* RTC Calibration Bit 4 */ +#define RTCCAL3 (0x0008) /* RTC Calibration Bit 3 */ +#define RTCCAL2 (0x0004) /* RTC Calibration Bit 2 */ +#define RTCCAL1 (0x0002) /* RTC Calibration Bit 1 */ +#define RTCCAL0 (0x0001) /* RTC Calibration Bit 0 */ + +/* RTCCTL23 Control Bits */ +#define RTCCALS_L (0x0080) /* RTC Calibration Sign */ +//#define Reserved (0x0040) +#define RTCCAL5_L (0x0020) /* RTC Calibration Bit 5 */ +#define RTCCAL4_L (0x0010) /* RTC Calibration Bit 4 */ +#define RTCCAL3_L (0x0008) /* RTC Calibration Bit 3 */ +#define RTCCAL2_L (0x0004) /* RTC Calibration Bit 2 */ +#define RTCCAL1_L (0x0002) /* RTC Calibration Bit 1 */ +#define RTCCAL0_L (0x0001) /* RTC Calibration Bit 0 */ + +/* RTCCTL23 Control Bits */ +#define RTCCALF1_H (0x0002) /* RTC Calibration Frequency Bit 1 */ +#define RTCCALF0_H (0x0001) /* RTC Calibration Frequency Bit 0 */ +//#define Reserved (0x0040) + +#define RTCCALF_0 (0x0000) /* RTC Calibration Frequency: No Output */ +#define RTCCALF_1 (0x0100) /* RTC Calibration Frequency: 512 Hz */ +#define RTCCALF_2 (0x0200) /* RTC Calibration Frequency: 256 Hz */ +#define RTCCALF_3 (0x0300) /* RTC Calibration Frequency: 1 Hz */ + + + +#define RTCAE (0x80) /* Real Time Clock Alarm enable */ + + + + +/* RTCPS0CTL Control Bits */ +//#define Reserved (0x8000) +#define RT0SSEL (0x4000) /* RTC Prescale Timer 0 Source Select 0:ACLK / 1:SMCLK */ +#define RT0PSDIV2 (0x2000) /* RTC Prescale Timer 0 Clock Divide Bit: 2 */ +#define RT0PSDIV1 (0x1000) /* RTC Prescale Timer 0 Clock Divide Bit: 1 */ +#define RT0PSDIV0 (0x0800) /* RTC Prescale Timer 0 Clock Divide Bit: 0 */ +//#define Reserved (0x0400) +//#define Reserved (0x0200) +#define RT0PSHOLD (0x0100) /* RTC Prescale Timer 0 Hold */ +//#define Reserved (0x0080) +//#define Reserved (0x0040) +//#define Reserved (0x0020) +#define RT0IP2 (0x0010) /* RTC Prescale Timer 0 Interrupt Interval Bit: 2 */ +#define RT0IP1 (0x0008) /* RTC Prescale Timer 0 Interrupt Interval Bit: 1 */ +#define RT0IP0 (0x0004) /* RTC Prescale Timer 0 Interrupt Interval Bit: 0 */ +#define RT0PSIE (0x0002) /* RTC Prescale Timer 0 Interrupt Enable Flag */ +#define RT0PSIFG (0x0001) /* RTC Prescale Timer 0 Interrupt Flag */ + +/* RTCPS0CTL Control Bits */ +//#define Reserved (0x8000) +//#define Reserved (0x0400) +//#define Reserved (0x0200) +//#define Reserved (0x0080) +//#define Reserved (0x0040) +//#define Reserved (0x0020) +#define RT0IP2_L (0x0010) /* RTC Prescale Timer 0 Interrupt Interval Bit: 2 */ +#define RT0IP1_L (0x0008) /* RTC Prescale Timer 0 Interrupt Interval Bit: 1 */ +#define RT0IP0_L (0x0004) /* RTC Prescale Timer 0 Interrupt Interval Bit: 0 */ +#define RT0PSIE_L (0x0002) /* RTC Prescale Timer 0 Interrupt Enable Flag */ +#define RT0PSIFG_L (0x0001) /* RTC Prescale Timer 0 Interrupt Flag */ + +/* RTCPS0CTL Control Bits */ +//#define Reserved (0x8000) +#define RT0SSEL_H (0x0040) /* RTC Prescale Timer 0 Source Select 0:ACLK / 1:SMCLK */ +#define RT0PSDIV2_H (0x0020) /* RTC Prescale Timer 0 Clock Divide Bit: 2 */ +#define RT0PSDIV1_H (0x0010) /* RTC Prescale Timer 0 Clock Divide Bit: 1 */ +#define RT0PSDIV0_H (0x0008) /* RTC Prescale Timer 0 Clock Divide Bit: 0 */ +//#define Reserved (0x0400) +//#define Reserved (0x0200) +#define RT0PSHOLD_H (0x0001) /* RTC Prescale Timer 0 Hold */ +//#define Reserved (0x0080) +//#define Reserved (0x0040) +//#define Reserved (0x0020) + +#define RT0IP_0 (0x0000) /* RTC Prescale Timer 0 Interrupt Interval /2 */ +#define RT0IP_1 (0x0004) /* RTC Prescale Timer 0 Interrupt Interval /4 */ +#define RT0IP_2 (0x0008) /* RTC Prescale Timer 0 Interrupt Interval /8 */ +#define RT0IP_3 (0x000C) /* RTC Prescale Timer 0 Interrupt Interval /16 */ +#define RT0IP_4 (0x0010) /* RTC Prescale Timer 0 Interrupt Interval /32 */ +#define RT0IP_5 (0x0014) /* RTC Prescale Timer 0 Interrupt Interval /64 */ +#define RT0IP_6 (0x0018) /* RTC Prescale Timer 0 Interrupt Interval /128 */ +#define RT0IP_7 (0x001C) /* RTC Prescale Timer 0 Interrupt Interval /256 */ + +#define RT0PSDIV_0 (0x0000) /* RTC Prescale Timer 0 Clock Divide /2 */ +#define RT0PSDIV_1 (0x0800) /* RTC Prescale Timer 0 Clock Divide /4 */ +#define RT0PSDIV_2 (0x1000) /* RTC Prescale Timer 0 Clock Divide /8 */ +#define RT0PSDIV_3 (0x1800) /* RTC Prescale Timer 0 Clock Divide /16 */ +#define RT0PSDIV_4 (0x2000) /* RTC Prescale Timer 0 Clock Divide /32 */ +#define RT0PSDIV_5 (0x2800) /* RTC Prescale Timer 0 Clock Divide /64 */ +#define RT0PSDIV_6 (0x3000) /* RTC Prescale Timer 0 Clock Divide /128 */ +#define RT0PSDIV_7 (0x3800) /* RTC Prescale Timer 0 Clock Divide /256 */ + + +/* RTCPS1CTL Control Bits */ +#define RT1SSEL1 (0x8000) /* RTC Prescale Timer 1 Source Select Bit 1 */ +#define RT1SSEL0 (0x4000) /* RTC Prescale Timer 1 Source Select Bit 0 */ +#define RT1PSDIV2 (0x2000) /* RTC Prescale Timer 1 Clock Divide Bit: 2 */ +#define RT1PSDIV1 (0x1000) /* RTC Prescale Timer 1 Clock Divide Bit: 1 */ +#define RT1PSDIV0 (0x0800) /* RTC Prescale Timer 1 Clock Divide Bit: 0 */ +//#define Reserved (0x0400) +//#define Reserved (0x0200) +#define RT1PSHOLD (0x0100) /* RTC Prescale Timer 1 Hold */ +//#define Reserved (0x0080) +//#define Reserved (0x0040) +//#define Reserved (0x0020) +#define RT1IP2 (0x0010) /* RTC Prescale Timer 1 Interrupt Interval Bit: 2 */ +#define RT1IP1 (0x0008) /* RTC Prescale Timer 1 Interrupt Interval Bit: 1 */ +#define RT1IP0 (0x0004) /* RTC Prescale Timer 1 Interrupt Interval Bit: 0 */ +#define RT1PSIE (0x0002) /* RTC Prescale Timer 1 Interrupt Enable Flag */ +#define RT1PSIFG (0x0001) /* RTC Prescale Timer 1 Interrupt Flag */ + +/* RTCPS1CTL Control Bits */ +//#define Reserved (0x0400) +//#define Reserved (0x0200) +//#define Reserved (0x0080) +//#define Reserved (0x0040) +//#define Reserved (0x0020) +#define RT1IP2_L (0x0010) /* RTC Prescale Timer 1 Interrupt Interval Bit: 2 */ +#define RT1IP1_L (0x0008) /* RTC Prescale Timer 1 Interrupt Interval Bit: 1 */ +#define RT1IP0_L (0x0004) /* RTC Prescale Timer 1 Interrupt Interval Bit: 0 */ +#define RT1PSIE_L (0x0002) /* RTC Prescale Timer 1 Interrupt Enable Flag */ +#define RT1PSIFG_L (0x0001) /* RTC Prescale Timer 1 Interrupt Flag */ + +/* RTCPS1CTL Control Bits */ +#define RT1SSEL1_H (0x0080) /* RTC Prescale Timer 1 Source Select Bit 1 */ +#define RT1SSEL0_H (0x0040) /* RTC Prescale Timer 1 Source Select Bit 0 */ +#define RT1PSDIV2_H (0x0020) /* RTC Prescale Timer 1 Clock Divide Bit: 2 */ +#define RT1PSDIV1_H (0x0010) /* RTC Prescale Timer 1 Clock Divide Bit: 1 */ +#define RT1PSDIV0_H (0x0008) /* RTC Prescale Timer 1 Clock Divide Bit: 0 */ +//#define Reserved (0x0400) +//#define Reserved (0x0200) +#define RT1PSHOLD_H (0x0001) /* RTC Prescale Timer 1 Hold */ +//#define Reserved (0x0080) +//#define Reserved (0x0040) +//#define Reserved (0x0020) + +#define RT1IP_0 (0x0000) /* RTC Prescale Timer 1 Interrupt Interval /2 */ +#define RT1IP_1 (0x0004) /* RTC Prescale Timer 1 Interrupt Interval /4 */ +#define RT1IP_2 (0x0008) /* RTC Prescale Timer 1 Interrupt Interval /8 */ +#define RT1IP_3 (0x000C) /* RTC Prescale Timer 1 Interrupt Interval /16 */ +#define RT1IP_4 (0x0010) /* RTC Prescale Timer 1 Interrupt Interval /32 */ +#define RT1IP_5 (0x0014) /* RTC Prescale Timer 1 Interrupt Interval /64 */ +#define RT1IP_6 (0x0018) /* RTC Prescale Timer 1 Interrupt Interval /128 */ +#define RT1IP_7 (0x001C) /* RTC Prescale Timer 1 Interrupt Interval /256 */ + +#define RT1PSDIV_0 (0x0000) /* RTC Prescale Timer 1 Clock Divide /2 */ +#define RT1PSDIV_1 (0x0800) /* RTC Prescale Timer 1 Clock Divide /4 */ +#define RT1PSDIV_2 (0x1000) /* RTC Prescale Timer 1 Clock Divide /8 */ +#define RT1PSDIV_3 (0x1800) /* RTC Prescale Timer 1 Clock Divide /16 */ +#define RT1PSDIV_4 (0x2000) /* RTC Prescale Timer 1 Clock Divide /32 */ +#define RT1PSDIV_5 (0x2800) /* RTC Prescale Timer 1 Clock Divide /64 */ +#define RT1PSDIV_6 (0x3000) /* RTC Prescale Timer 1 Clock Divide /128 */ +#define RT1PSDIV_7 (0x3800) /* RTC Prescale Timer 1 Clock Divide /256 */ + +#define RT1SSEL_0 (0x0000) /* RTC Prescale Timer Source Select ACLK */ +#define RT1SSEL_1 (0x4000) /* RTC Prescale Timer Source Select SMCLK */ +#define RT1SSEL_2 (0x8000) /* RTC Prescale Timer Source Select RT0PS */ +#define RT1SSEL_3 (0xC000) /* RTC Prescale Timer Source Select RT0PS */ + +/* RTC Definitions */ +#define RTCIV_NONE (0x0000) /* No Interrupt pending */ +#define RTCIV_RTCRDYIFG (0x0002) /* RTC ready: RTCRDYIFG */ +#define RTCIV_RTCTEVIFG (0x0004) /* RTC interval timer: RTCTEVIFG */ +#define RTCIV_RTCAIFG (0x0006) /* RTC user alarm: RTCAIFG */ +#define RTCIV_RT0PSIFG (0x0008) /* RTC prescaler 0: RT0PSIFG */ +#define RTCIV_RT1PSIFG (0x000A) /* RTC prescaler 1: RT1PSIFG */ + +/* Legacy Definitions */ +#define RTC_NONE (0x0000) /* No Interrupt pending */ +#define RTC_RTCRDYIFG (0x0002) /* RTC ready: RTCRDYIFG */ +#define RTC_RTCTEVIFG (0x0004) /* RTC interval timer: RTCTEVIFG */ +#define RTC_RTCAIFG (0x0006) /* RTC user alarm: RTCAIFG */ +#define RTC_RT0PSIFG (0x0008) /* RTC prescaler 0: RT0PSIFG */ +#define RTC_RT1PSIFG (0x000A) /* RTC prescaler 1: RT1PSIFG */ + +/************************************************************ +* SFR - Special Function Register Module +************************************************************/ + +#define SFRIE1 0x0100 /* Interrupt Enable 1 */ + +/* SFRIE1 Control Bits */ +#define WDTIE (0x0001) /* WDT Interrupt Enable */ +#define OFIE (0x0002) /* Osc Fault Enable */ +//#define Reserved (0x0004) +#define VMAIE (0x0008) /* Vacant Memory Interrupt Enable */ +#define NMIIE (0x0010) /* NMI Interrupt Enable */ +#define ACCVIE (0x0020) /* Flash Access Violation Interrupt Enable */ +#define JMBINIE (0x0040) /* JTAG Mail Box input Interrupt Enable */ +#define JMBOUTIE (0x0080) /* JTAG Mail Box output Interrupt Enable */ + +#define WDTIE_L (0x0001) /* WDT Interrupt Enable */ +#define OFIE_L (0x0002) /* Osc Fault Enable */ +//#define Reserved (0x0004) +#define VMAIE_L (0x0008) /* Vacant Memory Interrupt Enable */ +#define NMIIE_L (0x0010) /* NMI Interrupt Enable */ +#define ACCVIE_L (0x0020) /* Flash Access Violation Interrupt Enable */ +#define JMBINIE_L (0x0040) /* JTAG Mail Box input Interrupt Enable */ +#define JMBOUTIE_L (0x0080) /* JTAG Mail Box output Interrupt Enable */ + + +#define SFRIFG1 0x0102 /* Interrupt Flag 1 */ +/* SFRIFG1 Control Bits */ +#define WDTIFG (0x0001) /* WDT Interrupt Flag */ +#define OFIFG (0x0002) /* Osc Fault Flag */ +//#define Reserved (0x0004) +#define VMAIFG (0x0008) /* Vacant Memory Interrupt Flag */ +#define NMIIFG (0x0010) /* NMI Interrupt Flag */ +//#define Reserved (0x0020) +#define JMBINIFG (0x0040) /* JTAG Mail Box input Interrupt Flag */ +#define JMBOUTIFG (0x0080) /* JTAG Mail Box output Interrupt Flag */ + +#define WDTIFG_L (0x0001) /* WDT Interrupt Flag */ +#define OFIFG_L (0x0002) /* Osc Fault Flag */ +//#define Reserved (0x0004) +#define VMAIFG_L (0x0008) /* Vacant Memory Interrupt Flag */ +#define NMIIFG_L (0x0010) /* NMI Interrupt Flag */ +//#define Reserved (0x0020) +#define JMBINIFG_L (0x0040) /* JTAG Mail Box input Interrupt Flag */ +#define JMBOUTIFG_L (0x0080) /* JTAG Mail Box output Interrupt Flag */ + + +#define SFRRPCR 0x0104 /* RESET Pin Control Register */ +/* SFRRPCR Control Bits */ +#define SYSNMI (0x0001) /* NMI select */ +#define SYSNMIIES (0x0002) /* NMI edge select */ +#define SYSRSTUP (0x0004) /* RESET Pin pull down/up select */ +#define SYSRSTRE (0x0008) /* RESET Pin Resistor enable */ + +#define SYSNMI_L (0x0001) /* NMI select */ +#define SYSNMIIES_L (0x0002) /* NMI edge select */ +#define SYSRSTUP_L (0x0004) /* RESET Pin pull down/up select */ +#define SYSRSTRE_L (0x0008) /* RESET Pin Resistor enable */ + + +/************************************************************ +* SYS - System Module +************************************************************/ + +#define SYSCTL 0x0180 /* System control */ +#define SYSBSLC 0x0182 /* Boot strap configuration area */ +#define SYSJMBC 0x0186 /* JTAG mailbox control */ +#define SYSJMBI0 0x0188 /* JTAG mailbox input 0 */ +#define SYSJMBI1 0x018A /* JTAG mailbox input 1 */ +#define SYSJMBO0 0x018C /* JTAG mailbox output 0 */ +#define SYSJMBO1 0x018E /* JTAG mailbox output 1 */ + +#define SYSBERRIV 0x0198 /* Bus Error vector generator */ +#define SYSUNIV 0x019A /* User NMI vector generator */ +#define SYSSNIV 0x019C /* System NMI vector generator */ +#define SYSRSTIV 0x019E /* Reset vector generator */ + +/* SYSCTL Control Bits */ +#define SYSRIVECT (0x0001) /* SYS - RAM based interrupt vectors */ +//#define RESERVED (0x0002) /* SYS - Reserved */ +#define SYSPMMPE (0x0004) /* SYS - PMM access protect */ +//#define RESERVED (0x0008) /* SYS - Reserved */ +#define SYSBSLIND (0x0010) /* SYS - TCK/RST indication detected */ +#define SYSJTAGPIN (0x0020) /* SYS - Dedicated JTAG pins enabled */ +//#define RESERVED (0x0040) /* SYS - Reserved */ +//#define RESERVED (0x0080) /* SYS - Reserved */ +//#define RESERVED (0x0100) /* SYS - Reserved */ +//#define RESERVED (0x0200) /* SYS - Reserved */ +//#define RESERVED (0x0400) /* SYS - Reserved */ +//#define RESERVED (0x0800) /* SYS - Reserved */ +//#define RESERVED (0x1000) /* SYS - Reserved */ +//#define RESERVED (0x2000) /* SYS - Reserved */ +//#define RESERVED (0x4000) /* SYS - Reserved */ +//#define RESERVED (0x8000) /* SYS - Reserved */ + +/* SYSCTL Control Bits */ +#define SYSRIVECT_L (0x0001) /* SYS - RAM based interrupt vectors */ +//#define RESERVED (0x0002) /* SYS - Reserved */ +#define SYSPMMPE_L (0x0004) /* SYS - PMM access protect */ +//#define RESERVED (0x0008) /* SYS - Reserved */ +#define SYSBSLIND_L (0x0010) /* SYS - TCK/RST indication detected */ +#define SYSJTAGPIN_L (0x0020) /* SYS - Dedicated JTAG pins enabled */ +//#define RESERVED (0x0040) /* SYS - Reserved */ +//#define RESERVED (0x0080) /* SYS - Reserved */ +//#define RESERVED (0x0100) /* SYS - Reserved */ +//#define RESERVED (0x0200) /* SYS - Reserved */ +//#define RESERVED (0x0400) /* SYS - Reserved */ +//#define RESERVED (0x0800) /* SYS - Reserved */ +//#define RESERVED (0x1000) /* SYS - Reserved */ +//#define RESERVED (0x2000) /* SYS - Reserved */ +//#define RESERVED (0x4000) /* SYS - Reserved */ +//#define RESERVED (0x8000) /* SYS - Reserved */ + + +/* SYSBSLC Control Bits */ +#define SYSBSLSIZE0 (0x0001) /* SYS - BSL Protection Size 0 */ +#define SYSBSLSIZE1 (0x0002) /* SYS - BSL Protection Size 1 */ +#define SYSBSLR (0x0004) /* SYS - RAM assigned to BSL */ +//#define RESERVED (0x0008) /* SYS - Reserved */ +//#define RESERVED (0x0010) /* SYS - Reserved */ +//#define RESERVED (0x0020) /* SYS - Reserved */ +//#define RESERVED (0x0040) /* SYS - Reserved */ +//#define RESERVED (0x0080) /* SYS - Reserved */ +//#define RESERVED (0x0100) /* SYS - Reserved */ +//#define RESERVED (0x0200) /* SYS - Reserved */ +//#define RESERVED (0x0400) /* SYS - Reserved */ +//#define RESERVED (0x0800) /* SYS - Reserved */ +//#define RESERVED (0x1000) /* SYS - Reserved */ +//#define RESERVED (0x2000) /* SYS - Reserved */ +#define SYSBSLOFF (0x4000) /* SYS - BSL Memory disabled */ +#define SYSBSLPE (0x8000) /* SYS - BSL Memory protection enabled */ + +/* SYSBSLC Control Bits */ +#define SYSBSLSIZE0_L (0x0001) /* SYS - BSL Protection Size 0 */ +#define SYSBSLSIZE1_L (0x0002) /* SYS - BSL Protection Size 1 */ +#define SYSBSLR_L (0x0004) /* SYS - RAM assigned to BSL */ +//#define RESERVED (0x0008) /* SYS - Reserved */ +//#define RESERVED (0x0010) /* SYS - Reserved */ +//#define RESERVED (0x0020) /* SYS - Reserved */ +//#define RESERVED (0x0040) /* SYS - Reserved */ +//#define RESERVED (0x0080) /* SYS - Reserved */ +//#define RESERVED (0x0100) /* SYS - Reserved */ +//#define RESERVED (0x0200) /* SYS - Reserved */ +//#define RESERVED (0x0400) /* SYS - Reserved */ +//#define RESERVED (0x0800) /* SYS - Reserved */ +//#define RESERVED (0x1000) /* SYS - Reserved */ +//#define RESERVED (0x2000) /* SYS - Reserved */ + +/* SYSBSLC Control Bits */ +//#define RESERVED (0x0008) /* SYS - Reserved */ +//#define RESERVED (0x0010) /* SYS - Reserved */ +//#define RESERVED (0x0020) /* SYS - Reserved */ +//#define RESERVED (0x0040) /* SYS - Reserved */ +//#define RESERVED (0x0080) /* SYS - Reserved */ +//#define RESERVED (0x0100) /* SYS - Reserved */ +//#define RESERVED (0x0200) /* SYS - Reserved */ +//#define RESERVED (0x0400) /* SYS - Reserved */ +//#define RESERVED (0x0800) /* SYS - Reserved */ +//#define RESERVED (0x1000) /* SYS - Reserved */ +//#define RESERVED (0x2000) /* SYS - Reserved */ +#define SYSBSLOFF_H (0x0040) /* SYS - BSL Memory disabled */ +#define SYSBSLPE_H (0x0080) /* SYS - BSL Memory protection enabled */ + +/* SYSJMBC Control Bits */ +#define JMBIN0FG (0x0001) /* SYS - Incoming JTAG Mailbox 0 Flag */ +#define JMBIN1FG (0x0002) /* SYS - Incoming JTAG Mailbox 1 Flag */ +#define JMBOUT0FG (0x0004) /* SYS - Outgoing JTAG Mailbox 0 Flag */ +#define JMBOUT1FG (0x0008) /* SYS - Outgoing JTAG Mailbox 1 Flag */ +#define JMBMODE (0x0010) /* SYS - JMB 16/32 Bit Mode */ +//#define RESERVED (0x0020) /* SYS - Reserved */ +#define JMBCLR0OFF (0x0040) /* SYS - Incoming JTAG Mailbox 0 Flag auto-clear disalbe */ +#define JMBCLR1OFF (0x0080) /* SYS - Incoming JTAG Mailbox 1 Flag auto-clear disalbe */ +//#define RESERVED (0x0100) /* SYS - Reserved */ +//#define RESERVED (0x0200) /* SYS - Reserved */ +//#define RESERVED (0x0400) /* SYS - Reserved */ +//#define RESERVED (0x0800) /* SYS - Reserved */ +//#define RESERVED (0x1000) /* SYS - Reserved */ +//#define RESERVED (0x2000) /* SYS - Reserved */ +//#define RESERVED (0x4000) /* SYS - Reserved */ +//#define RESERVED (0x8000) /* SYS - Reserved */ + +/* SYSJMBC Control Bits */ +#define JMBIN0FG_L (0x0001) /* SYS - Incoming JTAG Mailbox 0 Flag */ +#define JMBIN1FG_L (0x0002) /* SYS - Incoming JTAG Mailbox 1 Flag */ +#define JMBOUT0FG_L (0x0004) /* SYS - Outgoing JTAG Mailbox 0 Flag */ +#define JMBOUT1FG_L (0x0008) /* SYS - Outgoing JTAG Mailbox 1 Flag */ +#define JMBMODE_L (0x0010) /* SYS - JMB 16/32 Bit Mode */ +//#define RESERVED (0x0020) /* SYS - Reserved */ +#define JMBCLR0OFF_L (0x0040) /* SYS - Incoming JTAG Mailbox 0 Flag auto-clear disalbe */ +#define JMBCLR1OFF_L (0x0080) /* SYS - Incoming JTAG Mailbox 1 Flag auto-clear disalbe */ +//#define RESERVED (0x0100) /* SYS - Reserved */ +//#define RESERVED (0x0200) /* SYS - Reserved */ +//#define RESERVED (0x0400) /* SYS - Reserved */ +//#define RESERVED (0x0800) /* SYS - Reserved */ +//#define RESERVED (0x1000) /* SYS - Reserved */ +//#define RESERVED (0x2000) /* SYS - Reserved */ +//#define RESERVED (0x4000) /* SYS - Reserved */ +//#define RESERVED (0x8000) /* SYS - Reserved */ + + + + + + + +/* SYSUNIV Definitions */ +#define SYSUNIV_NONE (0x0000) /* No Interrupt pending */ +#define SYSUNIV_NMIIFG (0x0002) /* SYSUNIV : NMIIFG */ +#define SYSUNIV_OFIFG (0x0004) /* SYSUNIV : Osc. Fail - OFIFG */ +#define SYSUNIV_ACCVIFG (0x0006) /* SYSUNIV : Access Violation - ACCVIFG */ +#define SYSUNIV_BUSIFG (0x0008) /* SYSUNIV : Bus Error */ +#define SYSUNIV_SYSBUSIV (0x0008) /* SYSUNIV : Bus Error - SYSBERRIFG (legacy) */ + +/* SYSSNIV Definitions */ +#define SYSSNIV_NONE (0x0000) /* No Interrupt pending */ +#define SYSSNIV_SVMLIFG (0x0002) /* SYSSNIV : SVMLIFG */ +#define SYSSNIV_SVMHIFG (0x0004) /* SYSSNIV : SVMHIFG */ +#define SYSSNIV_DLYLIFG (0x0006) /* SYSSNIV : DLYLIFG */ +#define SYSSNIV_DLYHIFG (0x0008) /* SYSSNIV : DLYHIFG */ +#define SYSSNIV_VMAIFG (0x000A) /* SYSSNIV : VMAIFG */ +#define SYSSNIV_JMBINIFG (0x000C) /* SYSSNIV : JMBINIFG */ +#define SYSSNIV_JMBOUTIFG (0x000E) /* SYSSNIV : JMBOUTIFG */ +#define SYSSNIV_VLRLIFG (0x0010) /* SYSSNIV : VLRLIFG */ +#define SYSSNIV_VLRHIFG (0x0012) /* SYSSNIV : VLRHIFG */ + +/* SYSRSTIV Definitions */ +#define SYSRSTIV_NONE (0x0000) /* No Interrupt pending */ +#define SYSRSTIV_BOR (0x0002) /* SYSRSTIV : BOR */ +#define SYSRSTIV_RSTNMI (0x0004) /* SYSRSTIV : RST/NMI */ +#define SYSRSTIV_DOBOR (0x0006) /* SYSRSTIV : Do BOR */ +#define SYSRSTIV_LPM5WU (0x0008) /* SYSRSTIV : Port LPM5 Wake Up */ +#define SYSRSTIV_SECYV (0x000A) /* SYSRSTIV : Security violation */ +#define SYSRSTIV_SVSL (0x000C) /* SYSRSTIV : SVSL */ +#define SYSRSTIV_SVSH (0x000E) /* SYSRSTIV : SVSH */ +#define SYSRSTIV_SVML_OVP (0x0010) /* SYSRSTIV : SVML_OVP */ +#define SYSRSTIV_SVMH_OVP (0x0012) /* SYSRSTIV : SVMH_OVP */ +#define SYSRSTIV_DOPOR (0x0014) /* SYSRSTIV : Do POR */ +#define SYSRSTIV_WDTTO (0x0016) /* SYSRSTIV : WDT Time out */ +#define SYSRSTIV_WDTKEY (0x0018) /* SYSRSTIV : WDTKEY violation */ +#define SYSRSTIV_KEYV (0x001A) /* SYSRSTIV : Flash Key violation */ +#define SYSRSTIV_FLLUL (0x001C) /* SYSRSTIV : FLL unlock */ +#define SYSRSTIV_PERF (0x001E) /* SYSRSTIV : peripheral/config area fetch */ +#define SYSRSTIV_PMMKEY (0x0020) /* SYSRSTIV : PMMKEY violation */ + +/************************************************************ +* Timer0_A5 +************************************************************/ + +#define TA0CTL 0x0340 /* Timer0_A5 Control */ +#define TA0CCTL0 0x0342 /* Timer0_A5 Capture/Compare Control 0 */ +#define TA0CCTL1 0x0344 /* Timer0_A5 Capture/Compare Control 1 */ +#define TA0CCTL2 0x0346 /* Timer0_A5 Capture/Compare Control 2 */ +#define TA0CCTL3 0x0348 /* Timer0_A5 Capture/Compare Control 3 */ +#define TA0CCTL4 0x034A /* Timer0_A5 Capture/Compare Control 4 */ +#define TA0R 0x0350 /* Timer0_A5 */ +#define TA0CCR0 0x0352 /* Timer0_A5 Capture/Compare 0 */ +#define TA0CCR1 0x0354 /* Timer0_A5 Capture/Compare 1 */ +#define TA0CCR2 0x0356 /* Timer0_A5 Capture/Compare 2 */ +#define TA0CCR3 0x0358 /* Timer0_A5 Capture/Compare 3 */ +#define TA0CCR4 0x035A /* Timer0_A5 Capture/Compare 4 */ +#define TA0IV 0x036E /* Timer0_A5 Interrupt Vector Word */ +#define TA0EX0 0x0360 /* Timer0_A5 Expansion Register 0 */ + +/* TAxCTL Control Bits */ +#define TASSEL1 (0x0200) /* Timer A clock source select 1 */ +#define TASSEL0 (0x0100) /* Timer A clock source select 0 */ +#define ID1 (0x0080) /* Timer A clock input divider 1 */ +#define ID0 (0x0040) /* Timer A clock input divider 0 */ +#define MC1 (0x0020) /* Timer A mode control 1 */ +#define MC0 (0x0010) /* Timer A mode control 0 */ +#define TACLR (0x0004) /* Timer A counter clear */ +#define TAIE (0x0002) /* Timer A counter interrupt enable */ +#define TAIFG (0x0001) /* Timer A counter interrupt flag */ + +#define MC_0 (0x0000) /* Timer A mode control: 0 - Stop */ +#define MC_1 (0x0010) /* Timer A mode control: 1 - Up to CCR0 */ +#define MC_2 (0x0020) /* Timer A mode control: 2 - Continuous up */ +#define MC_3 (0x0030) /* Timer A mode control: 3 - Up/Down */ +#define ID_0 (0x0000) /* Timer A input divider: 0 - /1 */ +#define ID_1 (0x0040) /* Timer A input divider: 1 - /2 */ +#define ID_2 (0x0080) /* Timer A input divider: 2 - /4 */ +#define ID_3 (0x00C0) /* Timer A input divider: 3 - /8 */ +#define TASSEL_0 (0x0000) /* Timer A clock source select: 0 - TACLK */ +#define TASSEL_1 (0x0100) /* Timer A clock source select: 1 - ACLK */ +#define TASSEL_2 (0x0200) /* Timer A clock source select: 2 - SMCLK */ +#define TASSEL_3 (0x0300) /* Timer A clock source select: 3 - INCLK */ +#define MC__STOP (0x0000) /* Timer A mode control: 0 - Stop */ +#define MC__UP (0x0010) /* Timer A mode control: 1 - Up to CCR0 */ +#define MC__CONTINUOUS (0x0020) /* Timer A mode control: 2 - Continuous up */ +#define MC__CONTINOUS (0x0020) /* Legacy define */ +#define MC__UPDOWN (0x0030) /* Timer A mode control: 3 - Up/Down */ +#define ID__1 (0x0000) /* Timer A input divider: 0 - /1 */ +#define ID__2 (0x0040) /* Timer A input divider: 1 - /2 */ +#define ID__4 (0x0080) /* Timer A input divider: 2 - /4 */ +#define ID__8 (0x00C0) /* Timer A input divider: 3 - /8 */ +#define TASSEL__TACLK (0x0000) /* Timer A clock source select: 0 - TACLK */ +#define TASSEL__ACLK (0x0100) /* Timer A clock source select: 1 - ACLK */ +#define TASSEL__SMCLK (0x0200) /* Timer A clock source select: 2 - SMCLK */ +#define TASSEL__INCLK (0x0300) /* Timer A clock source select: 3 - INCLK */ + +/* TAxCCTLx Control Bits */ +#define CM1 (0x8000) /* Capture mode 1 */ +#define CM0 (0x4000) /* Capture mode 0 */ +#define CCIS1 (0x2000) /* Capture input select 1 */ +#define CCIS0 (0x1000) /* Capture input select 0 */ +#define SCS (0x0800) /* Capture sychronize */ +#define SCCI (0x0400) /* Latched capture signal (read) */ +#define CAP (0x0100) /* Capture mode: 1 /Compare mode : 0 */ +#define OUTMOD2 (0x0080) /* Output mode 2 */ +#define OUTMOD1 (0x0040) /* Output mode 1 */ +#define OUTMOD0 (0x0020) /* Output mode 0 */ +#define CCIE (0x0010) /* Capture/compare interrupt enable */ +#define CCI (0x0008) /* Capture input signal (read) */ +#define OUT (0x0004) /* PWM Output signal if output mode 0 */ +#define COV (0x0002) /* Capture/compare overflow flag */ +#define CCIFG (0x0001) /* Capture/compare interrupt flag */ + +#define OUTMOD_0 (0x0000) /* PWM output mode: 0 - output only */ +#define OUTMOD_1 (0x0020) /* PWM output mode: 1 - set */ +#define OUTMOD_2 (0x0040) /* PWM output mode: 2 - PWM toggle/reset */ +#define OUTMOD_3 (0x0060) /* PWM output mode: 3 - PWM set/reset */ +#define OUTMOD_4 (0x0080) /* PWM output mode: 4 - toggle */ +#define OUTMOD_5 (0x00A0) /* PWM output mode: 5 - Reset */ +#define OUTMOD_6 (0x00C0) /* PWM output mode: 6 - PWM toggle/set */ +#define OUTMOD_7 (0x00E0) /* PWM output mode: 7 - PWM reset/set */ +#define CCIS_0 (0x0000) /* Capture input select: 0 - CCIxA */ +#define CCIS_1 (0x1000) /* Capture input select: 1 - CCIxB */ +#define CCIS_2 (0x2000) /* Capture input select: 2 - GND */ +#define CCIS_3 (0x3000) /* Capture input select: 3 - Vcc */ +#define CM_0 (0x0000) /* Capture mode: 0 - disabled */ +#define CM_1 (0x4000) /* Capture mode: 1 - pos. edge */ +#define CM_2 (0x8000) /* Capture mode: 1 - neg. edge */ +#define CM_3 (0xC000) /* Capture mode: 1 - both edges */ + + +/* TAxEX0 Control Bits */ +#define TAIDEX0 (0x0001) /* Timer A Input divider expansion Bit: 0 */ +#define TAIDEX1 (0x0002) /* Timer A Input divider expansion Bit: 1 */ +#define TAIDEX2 (0x0004) /* Timer A Input divider expansion Bit: 2 */ + +#define TAIDEX_0 (0x0000) /* Timer A Input divider expansion : /1 */ +#define TAIDEX_1 (0x0001) /* Timer A Input divider expansion : /2 */ +#define TAIDEX_2 (0x0002) /* Timer A Input divider expansion : /3 */ +#define TAIDEX_3 (0x0003) /* Timer A Input divider expansion : /4 */ +#define TAIDEX_4 (0x0004) /* Timer A Input divider expansion : /5 */ +#define TAIDEX_5 (0x0005) /* Timer A Input divider expansion : /6 */ +#define TAIDEX_6 (0x0006) /* Timer A Input divider expansion : /7 */ +#define TAIDEX_7 (0x0007) /* Timer A Input divider expansion : /8 */ + +/* T0A5IV Definitions */ +#define TA0IV_NONE (0x0000) /* No Interrupt pending */ +#define TA0IV_TACCR1 (0x0002) /* TA0CCR1_CCIFG */ +#define TA0IV_TACCR2 (0x0004) /* TA0CCR2_CCIFG */ +#define TA0IV_TACCR3 (0x0006) /* TA0CCR3_CCIFG */ +#define TA0IV_TACCR4 (0x0008) /* TA0CCR4_CCIFG */ +#define TA0IV_5 (0x000A) /* Reserved */ +#define TA0IV_6 (0x000C) /* Reserved */ +#define TA0IV_TAIFG (0x000E) /* TA0IFG */ + +/* Legacy Defines */ +#define TA0IV_TA0CCR1 (0x0002) /* TA0CCR1_CCIFG */ +#define TA0IV_TA0CCR2 (0x0004) /* TA0CCR2_CCIFG */ +#define TA0IV_TA0CCR3 (0x0006) /* TA0CCR3_CCIFG */ +#define TA0IV_TA0CCR4 (0x0008) /* TA0CCR4_CCIFG */ +#define TA0IV_TA0IFG (0x000E) /* TA0IFG */ + +/************************************************************ +* Timer1_A3 +************************************************************/ + +#define TA1CTL 0x0380 /* Timer1_A3 Control */ +#define TA1CCTL0 0x0382 /* Timer1_A3 Capture/Compare Control 0 */ +#define TA1CCTL1 0x0384 /* Timer1_A3 Capture/Compare Control 1 */ +#define TA1CCTL2 0x0386 /* Timer1_A3 Capture/Compare Control 2 */ +#define TA1R 0x0390 /* Timer1_A3 */ +#define TA1CCR0 0x0392 /* Timer1_A3 Capture/Compare 0 */ +#define TA1CCR1 0x0394 /* Timer1_A3 Capture/Compare 1 */ +#define TA1CCR2 0x0396 /* Timer1_A3 Capture/Compare 2 */ +#define TA1IV 0x03AE /* Timer1_A3 Interrupt Vector Word */ +#define TA1EX0 0x03A0 /* Timer1_A3 Expansion Register 0 */ + +/* Bits are already defined within the Timer0_Ax */ + +/* TA1IV Definitions */ +#define TA1IV_NONE (0x0000) /* No Interrupt pending */ +#define TA1IV_TACCR1 (0x0002) /* TA1CCR1_CCIFG */ +#define TA1IV_TACCR2 (0x0004) /* TA1CCR2_CCIFG */ +#define TA1IV_3 (0x0006) /* Reserved */ +#define TA1IV_4 (0x0008) /* Reserved */ +#define TA1IV_5 (0x000A) /* Reserved */ +#define TA1IV_6 (0x000C) /* Reserved */ +#define TA1IV_TAIFG (0x000E) /* TA1IFG */ + +/* Legacy Defines */ +#define TA1IV_TA1CCR1 (0x0002) /* TA1CCR1_CCIFG */ +#define TA1IV_TA1CCR2 (0x0004) /* TA1CCR2_CCIFG */ +#define TA1IV_TA1IFG (0x000E) /* TA1IFG */ + +/************************************************************ +* Timer2_A3 +************************************************************/ + +#define TA2CTL 0x0400 /* Timer2_A3 Control */ +#define TA2CCTL0 0x0402 /* Timer2_A3 Capture/Compare Control 0 */ +#define TA2CCTL1 0x0404 /* Timer2_A3 Capture/Compare Control 1 */ +#define TA2CCTL2 0x0406 /* Timer2_A3 Capture/Compare Control 2 */ +#define TA2R 0x0410 /* Timer2_A3 */ +#define TA2CCR0 0x0412 /* Timer2_A3 Capture/Compare 0 */ +#define TA2CCR1 0x0414 /* Timer2_A3 Capture/Compare 1 */ +#define TA2CCR2 0x0416 /* Timer2_A3 Capture/Compare 2 */ +#define TA2IV 0x042E /* Timer2_A3 Interrupt Vector Word */ +#define TA2EX0 0x0420 /* Timer2_A3 Expansion Register 0 */ + +/* Bits are already defined within the Timer0_Ax */ + +/* TA2IV Definitions */ +#define TA2IV_NONE (0x0000) /* No Interrupt pending */ +#define TA2IV_TACCR1 (0x0002) /* TA2CCR1_CCIFG */ +#define TA2IV_TACCR2 (0x0004) /* TA2CCR2_CCIFG */ +#define TA2IV_3 (0x0006) /* Reserved */ +#define TA2IV_4 (0x0008) /* Reserved */ +#define TA2IV_5 (0x000A) /* Reserved */ +#define TA2IV_6 (0x000C) /* Reserved */ +#define TA2IV_TAIFG (0x000E) /* TA2IFG */ + +/* Legacy Defines */ +#define TA2IV_TA2CCR1 (0x0002) /* TA2CCR1_CCIFG */ +#define TA2IV_TA2CCR2 (0x0004) /* TA2CCR2_CCIFG */ +#define TA2IV_TA2IFG (0x000E) /* TA2IFG */ + +/************************************************************ +* Timer0_B7 +************************************************************/ + +#define TB0CTL 0x03C0 /* Timer0_B7 Control */ +#define TB0CCTL0 0x03C2 /* Timer0_B7 Capture/Compare Control 0 */ +#define TB0CCTL1 0x03C4 /* Timer0_B7 Capture/Compare Control 1 */ +#define TB0CCTL2 0x03C6 /* Timer0_B7 Capture/Compare Control 2 */ +#define TB0CCTL3 0x03C8 /* Timer0_B7 Capture/Compare Control 3 */ +#define TB0CCTL4 0x03CA /* Timer0_B7 Capture/Compare Control 4 */ +#define TB0CCTL5 0x03CC /* Timer0_B7 Capture/Compare Control 5 */ +#define TB0CCTL6 0x03CE /* Timer0_B7 Capture/Compare Control 6 */ +#define TB0R 0x03D0 /* Timer0_B7 */ +#define TB0CCR0 0x03D2 /* Timer0_B7 Capture/Compare 0 */ +#define TB0CCR1 0x03D4 /* Timer0_B7 Capture/Compare 1 */ +#define TB0CCR2 0x03D6 /* Timer0_B7 Capture/Compare 2 */ +#define TB0CCR3 0x03D8 /* Timer0_B7 Capture/Compare 3 */ +#define TB0CCR4 0x03DA /* Timer0_B7 Capture/Compare 4 */ +#define TB0CCR5 0x03DC /* Timer0_B7 Capture/Compare 5 */ +#define TB0CCR6 0x03DE /* Timer0_B7 Capture/Compare 6 */ +#define TB0EX0 0x03E0 /* Timer0_B7 Expansion Register 0 */ +#define TB0IV 0x03EE /* Timer0_B7 Interrupt Vector Word */ + +/* Legacy Type Definitions for TimerB */ +#define TBCTL TB0CTL /* Timer0_B7 Control */ +#define TBCCTL0 TB0CCTL0 /* Timer0_B7 Capture/Compare Control 0 */ +#define TBCCTL1 TB0CCTL1 /* Timer0_B7 Capture/Compare Control 1 */ +#define TBCCTL2 TB0CCTL2 /* Timer0_B7 Capture/Compare Control 2 */ +#define TBCCTL3 TB0CCTL3 /* Timer0_B7 Capture/Compare Control 3 */ +#define TBCCTL4 TB0CCTL4 /* Timer0_B7 Capture/Compare Control 4 */ +#define TBCCTL5 TB0CCTL5 /* Timer0_B7 Capture/Compare Control 5 */ +#define TBCCTL6 TB0CCTL6 /* Timer0_B7 Capture/Compare Control 6 */ +#define TBR TB0R /* Timer0_B7 */ +#define TBCCR0 TB0CCR0 /* Timer0_B7 Capture/Compare 0 */ +#define TBCCR1 TB0CCR1 /* Timer0_B7 Capture/Compare 1 */ +#define TBCCR2 TB0CCR2 /* Timer0_B7 Capture/Compare 2 */ +#define TBCCR3 TB0CCR3 /* Timer0_B7 Capture/Compare 3 */ +#define TBCCR4 TB0CCR4 /* Timer0_B7 Capture/Compare 4 */ +#define TBCCR5 TB0CCR5 /* Timer0_B7 Capture/Compare 5 */ +#define TBCCR6 TB0CCR6 /* Timer0_B7 Capture/Compare 6 */ +#define TBEX0 TB0EX0 /* Timer0_B7 Expansion Register 0 */ +#define TBIV TB0IV /* Timer0_B7 Interrupt Vector Word */ +#define TIMERB1_VECTOR TIMER0_B1_VECTOR /* Timer0_B7 CC1-6, TB */ +#define TIMERB0_VECTOR TIMER0_B0_VECTOR /* Timer0_B7 CC0 */ + + +/* TBxCTL Control Bits */ +#define TBCLGRP1 (0x4000) /* Timer0_B7 Compare latch load group 1 */ +#define TBCLGRP0 (0x2000) /* Timer0_B7 Compare latch load group 0 */ +#define CNTL1 (0x1000) /* Counter lenght 1 */ +#define CNTL0 (0x0800) /* Counter lenght 0 */ +#define TBSSEL1 (0x0200) /* Clock source 1 */ +#define TBSSEL0 (0x0100) /* Clock source 0 */ +#define TBCLR (0x0004) /* Timer0_B7 counter clear */ +#define TBIE (0x0002) /* Timer0_B7 interrupt enable */ +#define TBIFG (0x0001) /* Timer0_B7 interrupt flag */ + +#define SHR1 (0x4000) /* Timer0_B7 Compare latch load group 1 */ +#define SHR0 (0x2000) /* Timer0_B7 Compare latch load group 0 */ + +#define TBSSEL_0 (0x0000) /* Clock Source: TBCLK */ +#define TBSSEL_1 (0x0100) /* Clock Source: ACLK */ +#define TBSSEL_2 (0x0200) /* Clock Source: SMCLK */ +#define TBSSEL_3 (0x0300) /* Clock Source: INCLK */ +#define CNTL_0 (0x0000) /* Counter lenght: 16 bit */ +#define CNTL_1 (0x0800) /* Counter lenght: 12 bit */ +#define CNTL_2 (0x1000) /* Counter lenght: 10 bit */ +#define CNTL_3 (0x1800) /* Counter lenght: 8 bit */ +#define SHR_0 (0x0000) /* Timer0_B7 Group: 0 - individually */ +#define SHR_1 (0x2000) /* Timer0_B7 Group: 1 - 3 groups (1-2, 3-4, 5-6) */ +#define SHR_2 (0x4000) /* Timer0_B7 Group: 2 - 2 groups (1-3, 4-6)*/ +#define SHR_3 (0x6000) /* Timer0_B7 Group: 3 - 1 group (all) */ +#define TBCLGRP_0 (0x0000) /* Timer0_B7 Group: 0 - individually */ +#define TBCLGRP_1 (0x2000) /* Timer0_B7 Group: 1 - 3 groups (1-2, 3-4, 5-6) */ +#define TBCLGRP_2 (0x4000) /* Timer0_B7 Group: 2 - 2 groups (1-3, 4-6)*/ +#define TBCLGRP_3 (0x6000) /* Timer0_B7 Group: 3 - 1 group (all) */ +#define TBSSEL__TBCLK (0x0000) /* Timer0_B7 clock source select: 0 - TBCLK */ +#define TBSSEL__TACLK (0x0000) /* Timer0_B7 clock source select: 0 - TBCLK (legacy) */ +#define TBSSEL__ACLK (0x0100) /* Timer0_B7 clock source select: 1 - ACLK */ +#define TBSSEL__SMCLK (0x0200) /* Timer0_B7 clock source select: 2 - SMCLK */ +#define TBSSEL__INCLK (0x0300) /* Timer0_B7 clock source select: 3 - INCLK */ +#define CNTL__16 (0x0000) /* Counter lenght: 16 bit */ +#define CNTL__12 (0x0800) /* Counter lenght: 12 bit */ +#define CNTL__10 (0x1000) /* Counter lenght: 10 bit */ +#define CNTL__8 (0x1800) /* Counter lenght: 8 bit */ + +/* Additional Timer B Control Register bits are defined in Timer A */ +/* TBxCCTLx Control Bits */ +#define CLLD1 (0x0400) /* Compare latch load source 1 */ +#define CLLD0 (0x0200) /* Compare latch load source 0 */ + +#define SLSHR1 (0x0400) /* Compare latch load source 1 */ +#define SLSHR0 (0x0200) /* Compare latch load source 0 */ + +#define SLSHR_0 (0x0000) /* Compare latch load sourec : 0 - immediate */ +#define SLSHR_1 (0x0200) /* Compare latch load sourec : 1 - TBR counts to 0 */ +#define SLSHR_2 (0x0400) /* Compare latch load sourec : 2 - up/down */ +#define SLSHR_3 (0x0600) /* Compare latch load sourec : 3 - TBR counts to TBCTL0 */ + +#define CLLD_0 (0x0000) /* Compare latch load sourec : 0 - immediate */ +#define CLLD_1 (0x0200) /* Compare latch load sourec : 1 - TBR counts to 0 */ +#define CLLD_2 (0x0400) /* Compare latch load sourec : 2 - up/down */ +#define CLLD_3 (0x0600) /* Compare latch load sourec : 3 - TBR counts to TBCTL0 */ + +/* TBxEX0 Control Bits */ +#define TBIDEX0 (0x0001) /* Timer0_B7 Input divider expansion Bit: 0 */ +#define TBIDEX1 (0x0002) /* Timer0_B7 Input divider expansion Bit: 1 */ +#define TBIDEX2 (0x0004) /* Timer0_B7 Input divider expansion Bit: 2 */ + +#define TBIDEX_0 (0x0000) /* Timer0_B7 Input divider expansion : /1 */ +#define TBIDEX_1 (0x0001) /* Timer0_B7 Input divider expansion : /2 */ +#define TBIDEX_2 (0x0002) /* Timer0_B7 Input divider expansion : /3 */ +#define TBIDEX_3 (0x0003) /* Timer0_B7 Input divider expansion : /4 */ +#define TBIDEX_4 (0x0004) /* Timer0_B7 Input divider expansion : /5 */ +#define TBIDEX_5 (0x0005) /* Timer0_B7 Input divider expansion : /6 */ +#define TBIDEX_6 (0x0006) /* Timer0_B7 Input divider expansion : /7 */ +#define TBIDEX_7 (0x0007) /* Timer0_B7 Input divider expansion : /8 */ +#define TBIDEX__1 (0x0000) /* Timer0_B7 Input divider expansion : /1 */ +#define TBIDEX__2 (0x0001) /* Timer0_B7 Input divider expansion : /2 */ +#define TBIDEX__3 (0x0002) /* Timer0_B7 Input divider expansion : /3 */ +#define TBIDEX__4 (0x0003) /* Timer0_B7 Input divider expansion : /4 */ +#define TBIDEX__5 (0x0004) /* Timer0_B7 Input divider expansion : /5 */ +#define TBIDEX__6 (0x0005) /* Timer0_B7 Input divider expansion : /6 */ +#define TBIDEX__7 (0x0006) /* Timer0_B7 Input divider expansion : /7 */ +#define TBIDEX__8 (0x0007) /* Timer0_B7 Input divider expansion : /8 */ + +/* TB0IV Definitions */ +#define TB0IV_NONE (0x0000) /* No Interrupt pending */ +#define TB0IV_TBCCR1 (0x0002) /* TB0CCR1_CCIFG */ +#define TB0IV_TBCCR2 (0x0004) /* TB0CCR2_CCIFG */ +#define TB0IV_TBCCR3 (0x0006) /* TB0CCR3_CCIFG */ +#define TB0IV_TBCCR4 (0x0008) /* TB0CCR4_CCIFG */ +#define TB0IV_TBCCR5 (0x000A) /* TB0CCR5_CCIFG */ +#define TB0IV_TBCCR6 (0x000C) /* TB0CCR6_CCIFG */ +#define TB0IV_TBIFG (0x000E) /* TB0IFG */ + +/* Legacy Defines */ +#define TB0IV_TB0CCR1 (0x0002) /* TB0CCR1_CCIFG */ +#define TB0IV_TB0CCR2 (0x0004) /* TB0CCR2_CCIFG */ +#define TB0IV_TB0CCR3 (0x0006) /* TB0CCR3_CCIFG */ +#define TB0IV_TB0CCR4 (0x0008) /* TB0CCR4_CCIFG */ +#define TB0IV_TB0CCR5 (0x000A) /* TB0CCR5_CCIFG */ +#define TB0IV_TB0CCR6 (0x000C) /* TB0CCR6_CCIFG */ +#define TB0IV_TB0IFG (0x000E) /* TB0IFG */ + + +/************************************************************ +* USB +************************************************************/ + +/* ========================================================================= */ +/* USB Configuration Registers */ +/* ========================================================================= */ +#define USBKEYID 0x0900 /* USB Controller key register */ +#define USBCNF 0x0902 /* USB Module configuration register */ +#define USBPHYCTL 0x0904 /* USB PHY control register */ +#define USBPWRCTL 0x0908 /* USB Power control register */ +#define USBPLLCTL 0x0910 /* USB PLL control register */ +#define USBPLLDIVB 0x0912 /* USB PLL Clock Divider Buffer control register */ +#define USBPLLIR 0x0914 /* USB PLL Interrupt control register */ + +#define USBKEYPID USBKEYID /* Legacy Definition: USB Controller key register */ +#define USBKEY (0x9628) /* USB Control Register key */ + +/* USBCNF Control Bits */ +#define USB_EN (0x0001) /* USB - Module enable */ +#define PUR_EN (0x0002) /* USB - PUR pin enable */ +#define PUR_IN (0x0004) /* USB - PUR pin input value */ +#define BLKRDY (0x0008) /* USB - Block ready signal for DMA */ +#define FNTEN (0x0010) /* USB - Frame Number receive Trigger enable for DMA */ +//#define RESERVED (0x0020) /* USB - */ +//#define RESERVED (0x0040) /* USB - */ +//#define RESERVED (0x0080) /* USB - */ +//#define RESERVED (0x0100) /* USB - */ +//#define RESERVED (0x0200) /* USB - */ +//#define RESERVED (0x0400) /* USB - */ +//#define RESERVED (0x0800) /* USB - */ +//#define RESERVED (0x1000) /* USB - */ +//#define RESERVED (0x2000) /* USB - */ +//#define RESERVED (0x4000) /* USB - */ +//#define RESERVED (0x8000) /* USB - */ + +/* USBCNF Control Bits */ +#define USB_EN_L (0x0001) /* USB - Module enable */ +#define PUR_EN_L (0x0002) /* USB - PUR pin enable */ +#define PUR_IN_L (0x0004) /* USB - PUR pin input value */ +#define BLKRDY_L (0x0008) /* USB - Block ready signal for DMA */ +#define FNTEN_L (0x0010) /* USB - Frame Number receive Trigger enable for DMA */ +//#define RESERVED (0x0020) /* USB - */ +//#define RESERVED (0x0040) /* USB - */ +//#define RESERVED (0x0080) /* USB - */ +//#define RESERVED (0x0100) /* USB - */ +//#define RESERVED (0x0200) /* USB - */ +//#define RESERVED (0x0400) /* USB - */ +//#define RESERVED (0x0800) /* USB - */ +//#define RESERVED (0x1000) /* USB - */ +//#define RESERVED (0x2000) /* USB - */ +//#define RESERVED (0x4000) /* USB - */ +//#define RESERVED (0x8000) /* USB - */ + + +/* USBPHYCTL Control Bits */ +#define PUOUT0 (0x0001) /* USB - USB Port Output Signal Bit 0 */ +#define PUOUT1 (0x0002) /* USB - USB Port Output Signal Bit 1 */ +#define PUIN0 (0x0004) /* USB - PU0/DP Input Data */ +#define PUIN1 (0x0008) /* USB - PU1/DM Input Data */ +//#define RESERVED (0x0010) /* USB - */ +#define PUOPE (0x0020) /* USB - USB Port Output Enable */ +//#define RESERVED (0x0040) /* USB - */ +#define PUSEL (0x0080) /* USB - USB Port Function Select */ +#define PUIPE (0x0100) /* USB - PHY Single Ended Input enable */ +//#define RESERVED (0x0200) /* USB - */ +//#define RESERVED (0x0100) /* USB - */ +//#define RESERVED (0x0200) /* USB - */ +//#define RESERVED (0x0400) /* USB - */ +//#define RESERVED (0x0800) /* USB - */ +//#define RESERVED (0x1000) /* USB - */ +//#define RESERVED (0x2000) /* USB - */ +//#define RESERVED (0x4000) /* USB - */ +//#define RESERVED (0x8000) /* USB - */ + +/* USBPHYCTL Control Bits */ +#define PUOUT0_L (0x0001) /* USB - USB Port Output Signal Bit 0 */ +#define PUOUT1_L (0x0002) /* USB - USB Port Output Signal Bit 1 */ +#define PUIN0_L (0x0004) /* USB - PU0/DP Input Data */ +#define PUIN1_L (0x0008) /* USB - PU1/DM Input Data */ +//#define RESERVED (0x0010) /* USB - */ +#define PUOPE_L (0x0020) /* USB - USB Port Output Enable */ +//#define RESERVED (0x0040) /* USB - */ +#define PUSEL_L (0x0080) /* USB - USB Port Function Select */ +//#define RESERVED (0x0200) /* USB - */ +//#define RESERVED (0x0100) /* USB - */ +//#define RESERVED (0x0200) /* USB - */ +//#define RESERVED (0x0400) /* USB - */ +//#define RESERVED (0x0800) /* USB - */ +//#define RESERVED (0x1000) /* USB - */ +//#define RESERVED (0x2000) /* USB - */ +//#define RESERVED (0x4000) /* USB - */ +//#define RESERVED (0x8000) /* USB - */ + +/* USBPHYCTL Control Bits */ +//#define RESERVED (0x0010) /* USB - */ +//#define RESERVED (0x0040) /* USB - */ +#define PUIPE_H (0x0001) /* USB - PHY Single Ended Input enable */ +//#define RESERVED (0x0200) /* USB - */ +//#define RESERVED (0x0100) /* USB - */ +//#define RESERVED (0x0200) /* USB - */ +//#define RESERVED (0x0400) /* USB - */ +//#define RESERVED (0x0800) /* USB - */ +//#define RESERVED (0x1000) /* USB - */ +//#define RESERVED (0x2000) /* USB - */ +//#define RESERVED (0x4000) /* USB - */ +//#define RESERVED (0x8000) /* USB - */ + +#define PUDIR (0x0020) /* USB - Legacy Definition: USB Port Output Enable */ +#define PSEIEN (0x0100) /* USB - Legacy Definition: PHY Single Ended Input enable */ + +/* USBPWRCTL Control Bits */ +#define VUOVLIFG (0x0001) /* USB - VUSB Overload Interrupt Flag */ +#define VBONIFG (0x0002) /* USB - VBUS "Coming ON" Interrupt Flag */ +#define VBOFFIFG (0x0004) /* USB - VBUS "Going OFF" Interrupt Flag */ +#define USBBGVBV (0x0008) /* USB - USB Bandgap and VBUS valid */ +#define USBDETEN (0x0010) /* USB - VBUS on/off events enable */ +#define OVLAOFF (0x0020) /* USB - LDO overload auto off enable */ +#define SLDOAON (0x0040) /* USB - Secondary LDO auto on enable */ +//#define RESERVED (0x0080) /* USB - */ +#define VUOVLIE (0x0100) /* USB - Overload indication Interrupt Enable */ +#define VBONIE (0x0200) /* USB - VBUS "Coming ON" Interrupt Enable */ +#define VBOFFIE (0x0400) /* USB - VBUS "Going OFF" Interrupt Enable */ +#define VUSBEN (0x0800) /* USB - LDO Enable (3.3V) */ +#define SLDOEN (0x1000) /* USB - Secondary LDO Enable (1.8V) */ +//#define RESERVED (0x2000) /* USB - */ +//#define RESERVED (0x4000) /* USB - */ +//#define RESERVED (0x8000) /* USB - */ + +/* USBPWRCTL Control Bits */ +#define VUOVLIFG_L (0x0001) /* USB - VUSB Overload Interrupt Flag */ +#define VBONIFG_L (0x0002) /* USB - VBUS "Coming ON" Interrupt Flag */ +#define VBOFFIFG_L (0x0004) /* USB - VBUS "Going OFF" Interrupt Flag */ +#define USBBGVBV_L (0x0008) /* USB - USB Bandgap and VBUS valid */ +#define USBDETEN_L (0x0010) /* USB - VBUS on/off events enable */ +#define OVLAOFF_L (0x0020) /* USB - LDO overload auto off enable */ +#define SLDOAON_L (0x0040) /* USB - Secondary LDO auto on enable */ +//#define RESERVED (0x0080) /* USB - */ +//#define RESERVED (0x2000) /* USB - */ +//#define RESERVED (0x4000) /* USB - */ +//#define RESERVED (0x8000) /* USB - */ + +/* USBPWRCTL Control Bits */ +//#define RESERVED (0x0080) /* USB - */ +#define VUOVLIE_H (0x0001) /* USB - Overload indication Interrupt Enable */ +#define VBONIE_H (0x0002) /* USB - VBUS "Coming ON" Interrupt Enable */ +#define VBOFFIE_H (0x0004) /* USB - VBUS "Going OFF" Interrupt Enable */ +#define VUSBEN_H (0x0008) /* USB - LDO Enable (3.3V) */ +#define SLDOEN_H (0x0010) /* USB - Secondary LDO Enable (1.8V) */ +//#define RESERVED (0x2000) /* USB - */ +//#define RESERVED (0x4000) /* USB - */ +//#define RESERVED (0x8000) /* USB - */ + + +/* USBPLLCTL Control Bits */ +//#define RESERVED (0x0001) /* USB - */ +//#define RESERVED (0x0002) /* USB - */ +//#define RESERVED (0x0004) /* USB - */ +//#define RESERVED (0x0008) /* USB - */ +//#define RESERVED (0x0010) /* USB - */ +//#define RESERVED (0x0020) /* USB - */ +#define UCLKSEL0 (0x0040) /* USB - Module Clock Select Bit 0 */ +#define UCLKSEL1 (0x0080) /* USB - Module Clock Select Bit 1 */ +#define UPLLEN (0x0100) /* USB - PLL enable */ +#define UPFDEN (0x0200) /* USB - Phase Freq. Discriminator enable */ +//#define RESERVED (0x0400) /* USB - */ +//#define RESERVED (0x0800) /* USB - */ +//#define RESERVED (0x1000) /* USB - */ +//#define RESERVED (0x2000) /* USB - */ +//#define RESERVED (0x4000) /* USB - */ +//#define RESERVED (0x8000) /* USB - */ + +/* USBPLLCTL Control Bits */ +//#define RESERVED (0x0001) /* USB - */ +//#define RESERVED (0x0002) /* USB - */ +//#define RESERVED (0x0004) /* USB - */ +//#define RESERVED (0x0008) /* USB - */ +//#define RESERVED (0x0010) /* USB - */ +//#define RESERVED (0x0020) /* USB - */ +#define UCLKSEL0_L (0x0040) /* USB - Module Clock Select Bit 0 */ +#define UCLKSEL1_L (0x0080) /* USB - Module Clock Select Bit 1 */ +//#define RESERVED (0x0400) /* USB - */ +//#define RESERVED (0x0800) /* USB - */ +//#define RESERVED (0x1000) /* USB - */ +//#define RESERVED (0x2000) /* USB - */ +//#define RESERVED (0x4000) /* USB - */ +//#define RESERVED (0x8000) /* USB - */ + +/* USBPLLCTL Control Bits */ +//#define RESERVED (0x0001) /* USB - */ +//#define RESERVED (0x0002) /* USB - */ +//#define RESERVED (0x0004) /* USB - */ +//#define RESERVED (0x0008) /* USB - */ +//#define RESERVED (0x0010) /* USB - */ +//#define RESERVED (0x0020) /* USB - */ +#define UPLLEN_H (0x0001) /* USB - PLL enable */ +#define UPFDEN_H (0x0002) /* USB - Phase Freq. Discriminator enable */ +//#define RESERVED (0x0400) /* USB - */ +//#define RESERVED (0x0800) /* USB - */ +//#define RESERVED (0x1000) /* USB - */ +//#define RESERVED (0x2000) /* USB - */ +//#define RESERVED (0x4000) /* USB - */ +//#define RESERVED (0x8000) /* USB - */ + +#define UCLKSEL_0 (0x0000) /* USB - Module Clock Select: 0 */ +#define UCLKSEL_1 (0x0040) /* USB - Module Clock Select: 1 */ +#define UCLKSEL_2 (0x0080) /* USB - Module Clock Select: 2 */ +#define UCLKSEL_3 (0x00C0) /* USB - Module Clock Select: 3 (Reserved) */ + +#define UCLKSEL__PLLCLK (0x0000) /* USB - Module Clock Select: PLLCLK */ +#define UCLKSEL__XT1CLK (0x0040) /* USB - Module Clock Select: XT1CLK */ +#define UCLKSEL__XT2CLK (0x0080) /* USB - Module Clock Select: XT2CLK */ + +/* USBPLLDIVB Control Bits */ +#define UPMB0 (0x0001) /* USB - PLL feedback divider buffer Bit 0 */ +#define UPMB1 (0x0002) /* USB - PLL feedback divider buffer Bit 1 */ +#define UPMB2 (0x0004) /* USB - PLL feedback divider buffer Bit 2 */ +#define UPMB3 (0x0008) /* USB - PLL feedback divider buffer Bit 3 */ +#define UPMB4 (0x0010) /* USB - PLL feedback divider buffer Bit 4 */ +#define UPMB5 (0x0020) /* USB - PLL feedback divider buffer Bit 5 */ +//#define RESERVED (0x0040) /* USB - */ +//#define RESERVED (0x0080) /* USB - */ +#define UPQB0 (0x0100) /* USB - PLL prescale divider buffer Bit 0 */ +#define UPQB1 (0x0200) /* USB - PLL prescale divider buffer Bit 1 */ +#define UPQB2 (0x0400) /* USB - PLL prescale divider buffer Bit 2 */ +//#define RESERVED (0x0800) /* USB - */ +//#define RESERVED (0x1000) /* USB - */ +//#define RESERVED (0x2000) /* USB - */ +//#define RESERVED (0x4000) /* USB - */ +//#define RESERVED (0x8000) /* USB - */ + +/* USBPLLDIVB Control Bits */ +#define UPMB0_L (0x0001) /* USB - PLL feedback divider buffer Bit 0 */ +#define UPMB1_L (0x0002) /* USB - PLL feedback divider buffer Bit 1 */ +#define UPMB2_L (0x0004) /* USB - PLL feedback divider buffer Bit 2 */ +#define UPMB3_L (0x0008) /* USB - PLL feedback divider buffer Bit 3 */ +#define UPMB4_L (0x0010) /* USB - PLL feedback divider buffer Bit 4 */ +#define UPMB5_L (0x0020) /* USB - PLL feedback divider buffer Bit 5 */ +//#define RESERVED (0x0040) /* USB - */ +//#define RESERVED (0x0080) /* USB - */ +//#define RESERVED (0x0800) /* USB - */ +//#define RESERVED (0x1000) /* USB - */ +//#define RESERVED (0x2000) /* USB - */ +//#define RESERVED (0x4000) /* USB - */ +//#define RESERVED (0x8000) /* USB - */ + +/* USBPLLDIVB Control Bits */ +//#define RESERVED (0x0040) /* USB - */ +//#define RESERVED (0x0080) /* USB - */ +#define UPQB0_H (0x0001) /* USB - PLL prescale divider buffer Bit 0 */ +#define UPQB1_H (0x0002) /* USB - PLL prescale divider buffer Bit 1 */ +#define UPQB2_H (0x0004) /* USB - PLL prescale divider buffer Bit 2 */ +//#define RESERVED (0x0800) /* USB - */ +//#define RESERVED (0x1000) /* USB - */ +//#define RESERVED (0x2000) /* USB - */ +//#define RESERVED (0x4000) /* USB - */ +//#define RESERVED (0x8000) /* USB - */ + +#define USBPLL_SETCLK_1_5 (UPMB0*31 | UPQB0*0) /* USB - PLL Set for 1.5 MHz input clock */ +#define USBPLL_SETCLK_1_6 (UPMB0*29 | UPQB0*0) /* USB - PLL Set for 1.6 MHz input clock */ +#define USBPLL_SETCLK_1_7778 (UPMB0*26 | UPQB0*0) /* USB - PLL Set for 1.7778 MHz input clock */ +#define USBPLL_SETCLK_1_8432 (UPMB0*25 | UPQB0*0) /* USB - PLL Set for 1.8432 MHz input clock */ +#define USBPLL_SETCLK_1_8461 (UPMB0*25 | UPQB0*0) /* USB - PLL Set for 1.8461 MHz input clock */ +#define USBPLL_SETCLK_1_92 (UPMB0*24 | UPQB0*0) /* USB - PLL Set for 1.92 MHz input clock */ +#define USBPLL_SETCLK_2_0 (UPMB0*23 | UPQB0*0) /* USB - PLL Set for 2.0 MHz input clock */ +#define USBPLL_SETCLK_2_4 (UPMB0*19 | UPQB0*0) /* USB - PLL Set for 2.4 MHz input clock */ +#define USBPLL_SETCLK_2_6667 (UPMB0*17 | UPQB0*0) /* USB - PLL Set for 2.6667 MHz input clock */ +#define USBPLL_SETCLK_3_0 (UPMB0*15 | UPQB0*0) /* USB - PLL Set for 3.0 MHz input clock */ +#define USBPLL_SETCLK_3_2 (UPMB0*29 | UPQB0*1) /* USB - PLL Set for 3.2 MHz input clock */ +#define USBPLL_SETCLK_3_5556 (UPMB0*26 | UPQB0*1) /* USB - PLL Set for 3.5556 MHz input clock */ +#define USBPLL_SETCLK_3_579545 (UPMB0*26 | UPQB0*1) /* USB - PLL Set for 3.579546 MHz input clock */ +#define USBPLL_SETCLK_3_84 (UPMB0*24 | UPQB0*1) /* USB - PLL Set for 3.84 MHz input clock */ +#define USBPLL_SETCLK_4_0 (UPMB0*23 | UPQB0*1) /* USB - PLL Set for 4.0 MHz input clock */ +#define USBPLL_SETCLK_4_1739 (UPMB0*22 | UPQB0*1) /* USB - PLL Set for 4.1739 MHz input clock */ +#define USBPLL_SETCLK_4_1943 (UPMB0*22 | UPQB0*1) /* USB - PLL Set for 4.1943 MHz input clock */ +#define USBPLL_SETCLK_4_332 (UPMB0*21 | UPQB0*1) /* USB - PLL Set for 4.332 MHz input clock */ +#define USBPLL_SETCLK_4_3636 (UPMB0*21 | UPQB0*1) /* USB - PLL Set for 4.3636 MHz input clock */ +#define USBPLL_SETCLK_4_5 (UPMB0*31 | UPQB0*2) /* USB - PLL Set for 4.5 MHz input clock */ +#define USBPLL_SETCLK_4_8 (UPMB0*19 | UPQB0*1) /* USB - PLL Set for 4.8 MHz input clock */ +#define USBPLL_SETCLK_5_33 (UPMB0*17 | UPQB0*1) /* USB - PLL Set for 5.33 MHz input clock */ +#define USBPLL_SETCLK_5_76 (UPMB0*24 | UPQB0*2) /* USB - PLL Set for 5.76 MHz input clock */ +#define USBPLL_SETCLK_6_0 (UPMB0*23 | UPQB0*2) /* USB - PLL Set for 6.0 MHz input clock */ +#define USBPLL_SETCLK_6_4 (UPMB0*29 | UPQB0*3) /* USB - PLL Set for 6.4 MHz input clock */ +#define USBPLL_SETCLK_7_2 (UPMB0*19 | UPQB0*2) /* USB - PLL Set for 7.2 MHz input clock */ +#define USBPLL_SETCLK_7_68 (UPMB0*24 | UPQB0*3) /* USB - PLL Set for 7.68 MHz input clock */ +#define USBPLL_SETCLK_8_0 (UPMB0*17 | UPQB0*2) /* USB - PLL Set for 8.0 MHz input clock */ +#define USBPLL_SETCLK_9_0 (UPMB0*15 | UPQB0*2) /* USB - PLL Set for 9.0 MHz input clock */ +#define USBPLL_SETCLK_9_6 (UPMB0*19 | UPQB0*3) /* USB - PLL Set for 9.6 MHz input clock */ +#define USBPLL_SETCLK_10_66 (UPMB0*17 | UPQB0*3) /* USB - PLL Set for 10.66 MHz input clock */ +#define USBPLL_SETCLK_12_0 (UPMB0*15 | UPQB0*3) /* USB - PLL Set for 12.0 MHz input clock */ +#define USBPLL_SETCLK_12_8 (UPMB0*29 | UPQB0*5) /* USB - PLL Set for 12.8 MHz input clock */ +#define USBPLL_SETCLK_14_4 (UPMB0*19 | UPQB0*4) /* USB - PLL Set for 14.4 MHz input clock */ +#define USBPLL_SETCLK_16_0 (UPMB0*17 | UPQB0*4) /* USB - PLL Set for 16.0 MHz input clock */ +#define USBPLL_SETCLK_16_9344 (UPMB0*16 | UPQB0*4) /* USB - PLL Set for 16.9344 MHz input clock */ +#define USBPLL_SETCLK_16_94118 (UPMB0*16 | UPQB0*4) /* USB - PLL Set for 16.94118 MHz input clock */ +#define USBPLL_SETCLK_18_0 (UPMB0*15 | UPQB0*4) /* USB - PLL Set for 18.0 MHz input clock */ +#define USBPLL_SETCLK_19_2 (UPMB0*19 | UPQB0*5) /* USB - PLL Set for 19.2 MHz input clock */ +#define USBPLL_SETCLK_24_0 (UPMB0*15 | UPQB0*5) /* USB - PLL Set for 24.0 MHz input clock */ +#define USBPLL_SETCLK_25_6 (UPMB0*29 | UPQB0*7) /* USB - PLL Set for 25.6 MHz input clock */ +#define USBPLL_SETCLK_26_0 (UPMB0*23 | UPQB0*6) /* USB - PLL Set for 26.0 MHz input clock */ +#define USBPLL_SETCLK_32_0 (UPMB0*23 | UPQB0*7) /* USB - PLL Set for 32.0 MHz input clock */ + + +/* USBPLLIR Control Bits */ +#define USBOOLIFG (0x0001) /* USB - PLL out of lock Interrupt Flag */ +#define USBLOSIFG (0x0002) /* USB - PLL loss of signal Interrupt Flag */ +#define USBOORIFG (0x0004) /* USB - PLL out of range Interrupt Flag */ +//#define RESERVED (0x0008) /* USB - */ +//#define RESERVED (0x0010) /* USB - */ +//#define RESERVED (0x0020) /* USB - */ +//#define RESERVED (0x0040) /* USB - */ +//#define RESERVED (0x0080) /* USB - */ +#define USBOOLIE (0x0100) /* USB - PLL out of lock Interrupt enable */ +#define USBLOSIE (0x0200) /* USB - PLL loss of signal Interrupt enable */ +#define USBOORIE (0x0400) /* USB - PLL out of range Interrupt enable */ +//#define RESERVED (0x0800) /* USB - */ +//#define RESERVED (0x1000) /* USB - */ +//#define RESERVED (0x2000) /* USB - */ +//#define RESERVED (0x4000) /* USB - */ +//#define RESERVED (0x8000) /* USB - */ + +/* USBPLLIR Control Bits */ +#define USBOOLIFG_L (0x0001) /* USB - PLL out of lock Interrupt Flag */ +#define USBLOSIFG_L (0x0002) /* USB - PLL loss of signal Interrupt Flag */ +#define USBOORIFG_L (0x0004) /* USB - PLL out of range Interrupt Flag */ +//#define RESERVED (0x0008) /* USB - */ +//#define RESERVED (0x0010) /* USB - */ +//#define RESERVED (0x0020) /* USB - */ +//#define RESERVED (0x0040) /* USB - */ +//#define RESERVED (0x0080) /* USB - */ +//#define RESERVED (0x0800) /* USB - */ +//#define RESERVED (0x1000) /* USB - */ +//#define RESERVED (0x2000) /* USB - */ +//#define RESERVED (0x4000) /* USB - */ +//#define RESERVED (0x8000) /* USB - */ + +/* USBPLLIR Control Bits */ +//#define RESERVED (0x0008) /* USB - */ +//#define RESERVED (0x0010) /* USB - */ +//#define RESERVED (0x0020) /* USB - */ +//#define RESERVED (0x0040) /* USB - */ +//#define RESERVED (0x0080) /* USB - */ +#define USBOOLIE_H (0x0001) /* USB - PLL out of lock Interrupt enable */ +#define USBLOSIE_H (0x0002) /* USB - PLL loss of signal Interrupt enable */ +#define USBOORIE_H (0x0004) /* USB - PLL out of range Interrupt enable */ +//#define RESERVED (0x0800) /* USB - */ +//#define RESERVED (0x1000) /* USB - */ +//#define RESERVED (0x2000) /* USB - */ +//#define RESERVED (0x4000) /* USB - */ +//#define RESERVED (0x8000) /* USB - */ + + + +/* ========================================================================= */ +/* USB Control Registers */ +/* ========================================================================= */ +#define USBIEPCNF_0 0x0920 /* USB Input endpoint_0: Configuration */ +#define USBIEPCNT_0 0x0921 /* USB Input endpoint_0: Byte Count */ +#define USBOEPCNF_0 0x0922 /* USB Output endpoint_0: Configuration */ +#define USBOEPCNT_0 0x0923 /* USB Output endpoint_0: byte count */ +#define USBIEPIE 0x092E /* USB Input endpoint interrupt enable flags */ +#define USBOEPIE 0x092F /* USB Output endpoint interrupt enable flags */ +#define USBIEPIFG 0x0930 /* USB Input endpoint interrupt flags */ +#define USBOEPIFG 0x0931 /* USB Output endpoint interrupt flags */ +#define USBVECINT 0x0932 /* USB Vector interrupt register */ +#define USBMAINT 0x0936 /* USB maintenance register */ +#define USBTSREG 0x0938 /* USB Time Stamp register */ +#define USBFN 0x093A /* USB Frame number */ +#define USBCTL 0x093C /* USB control register */ +#define USBIE 0x093D /* USB interrupt enable register */ +#define USBIFG 0x093E /* USB interrupt flag register */ +#define USBFUNADR 0x093F /* USB Function address register */ + +#define USBIV USBVECINT /* USB Vector interrupt register (alternate define) */ + +/* USBIEPCNF_0 Control Bits */ +/* USBOEPCNF_0 Control Bits */ +//#define RESERVED (0x0001) /* USB - */ +//#define RESERVED (0x0001) /* USB - */ +#define USBIIE (0x0004) /* USB - Transaction Interrupt indication enable */ +#define STALL (0x0008) /* USB - Stall Condition */ +//#define RESERVED (0x0010) /* USB - */ +#define TOGGLE (0x0020) /* USB - Toggle Bit */ +//#define RESERVED (0x0040) /* USB - */ +#define UBME (0x0080) /* USB - UBM In-Endpoint Enable */ + +/* USBIEPBCNT_0 Control Bits */ +/* USBOEPBCNT_0 Control Bits */ +#define CNT0 (0x0001) /* USB - Byte Count Bit 0 */ +#define CNT1 (0x0001) /* USB - Byte Count Bit 1 */ +#define CNT2 (0x0004) /* USB - Byte Count Bit 2 */ +#define CNT3 (0x0008) /* USB - Byte Count Bit 3 */ +//#define RESERVED (0x0010) /* USB - */ +//#define RESERVED (0x0020) /* USB - */ +//#define RESERVED (0x0040) /* USB - */ +#define NAK (0x0080) /* USB - No Acknowledge Status Bit */ + + +/* USBMAINT Control Bits */ +#define UTIFG (0x0001) /* USB - Timer Interrupt Flag */ +#define UTIE (0x0002) /* USB - Timer Interrupt Enable */ +//#define RESERVED (0x0004) /* USB - */ +//#define RESERVED (0x0008) /* USB - */ +//#define RESERVED (0x0010) /* USB - */ +//#define RESERVED (0x0020) /* USB - */ +//#define RESERVED (0x0040) /* USB - */ +//#define RESERVED (0x0080) /* USB - */ +#define TSGEN (0x0100) /* USB - Time Stamp Generator Enable */ +#define TSESEL0 (0x0200) /* USB - Time Stamp Event Select Bit 0 */ +#define TSESEL1 (0x0400) /* USB - Time Stamp Event Select Bit 1 */ +#define TSE3 (0x0800) /* USB - Time Stamp Event #3 Bit */ +//#define RESERVED (0x1000) /* USB - */ +#define UTSEL0 (0x2000) /* USB - Timer Select Bit 0 */ +#define UTSEL1 (0x4000) /* USB - Timer Select Bit 1 */ +#define UTSEL2 (0x8000) /* USB - Timer Select Bit 2 */ + +/* USBMAINT Control Bits */ +#define UTIFG_L (0x0001) /* USB - Timer Interrupt Flag */ +#define UTIE_L (0x0002) /* USB - Timer Interrupt Enable */ +//#define RESERVED (0x0004) /* USB - */ +//#define RESERVED (0x0008) /* USB - */ +//#define RESERVED (0x0010) /* USB - */ +//#define RESERVED (0x0020) /* USB - */ +//#define RESERVED (0x0040) /* USB - */ +//#define RESERVED (0x0080) /* USB - */ +//#define RESERVED (0x1000) /* USB - */ + +/* USBMAINT Control Bits */ +//#define RESERVED (0x0004) /* USB - */ +//#define RESERVED (0x0008) /* USB - */ +//#define RESERVED (0x0010) /* USB - */ +//#define RESERVED (0x0020) /* USB - */ +//#define RESERVED (0x0040) /* USB - */ +//#define RESERVED (0x0080) /* USB - */ +#define TSGEN_H (0x0001) /* USB - Time Stamp Generator Enable */ +#define TSESEL0_H (0x0002) /* USB - Time Stamp Event Select Bit 0 */ +#define TSESEL1_H (0x0004) /* USB - Time Stamp Event Select Bit 1 */ +#define TSE3_H (0x0008) /* USB - Time Stamp Event #3 Bit */ +//#define RESERVED (0x1000) /* USB - */ +#define UTSEL0_H (0x0020) /* USB - Timer Select Bit 0 */ +#define UTSEL1_H (0x0040) /* USB - Timer Select Bit 1 */ +#define UTSEL2_H (0x0080) /* USB - Timer Select Bit 2 */ + +#define TSESEL_0 (0x0000) /* USB - Time Stamp Event Select: 0 */ +#define TSESEL_1 (0x0200) /* USB - Time Stamp Event Select: 1 */ +#define TSESEL_2 (0x0400) /* USB - Time Stamp Event Select: 2 */ +#define TSESEL_3 (0x0600) /* USB - Time Stamp Event Select: 3 */ + +#define UTSEL_0 (0x0000) /* USB - Timer Select: 0 */ +#define UTSEL_1 (0x2000) /* USB - Timer Select: 1 */ +#define UTSEL_2 (0x4000) /* USB - Timer Select: 2 */ +#define UTSEL_3 (0x6000) /* USB - Timer Select: 3 */ +#define UTSEL_4 (0x8000) /* USB - Timer Select: 4 */ +#define UTSEL_5 (0xA000) /* USB - Timer Select: 5 */ +#define UTSEL_6 (0xC000) /* USB - Timer Select: 6 */ +#define UTSEL_7 (0xE000) /* USB - Timer Select: 7 */ + +/* USBCTL Control Bits */ +#define DIR (0x0001) /* USB - Data Response Bit */ +//#define RESERVED (0x0002) /* USB - */ +//#define RESERVED (0x0004) /* USB - */ +//#define RESERVED (0x0008) /* USB - */ +#define FRSTE (0x0010) /* USB - Function Reset Connection Enable */ +#define RWUP (0x0020) /* USB - Device Remote Wakeup Request */ +#define FEN (0x0040) /* USB - Function Enable Bit */ +//#define RESERVED (0x0080) /* USB - */ + +/* USBIE Control Bits */ +#define STPOWIE (0x0001) /* USB - Setup Overwrite Interrupt Enable */ +//#define RESERVED (0x0002) /* USB - */ +#define SETUPIE (0x0004) /* USB - Setup Interrupt Enable */ +//#define RESERVED (0x0008) /* USB - */ +//#define RESERVED (0x0010) /* USB - */ +#define RESRIE (0x0020) /* USB - Function Resume Request Interrupt Enable */ +#define SUSRIE (0x0040) /* USB - Function Suspend Request Interrupt Enable */ +#define RSTRIE (0x0080) /* USB - Function Reset Request Interrupt Enable */ + +/* USBIFG Control Bits */ +#define STPOWIFG (0x0001) /* USB - Setup Overwrite Interrupt Flag */ +//#define RESERVED (0x0002) /* USB - */ +#define SETUPIFG (0x0004) /* USB - Setup Interrupt Flag */ +//#define RESERVED (0x0008) /* USB - */ +//#define RESERVED (0x0010) /* USB - */ +#define RESRIFG (0x0020) /* USB - Function Resume Request Interrupt Flag */ +#define SUSRIFG (0x0040) /* USB - Function Suspend Request Interrupt Flag */ +#define RSTRIFG (0x0080) /* USB - Function Reset Request Interrupt Flag */ + +//values of USBVECINT when USB-interrupt occured +#define USBVECINT_NONE 0x00 +#define USBVECINT_PWR_DROP 0x02 +#define USBVECINT_PLL_LOCK 0x04 +#define USBVECINT_PLL_SIGNAL 0x06 +#define USBVECINT_PLL_RANGE 0x08 +#define USBVECINT_PWR_VBUSOn 0x0A +#define USBVECINT_PWR_VBUSOff 0x0C +#define USBVECINT_USB_TIMESTAMP 0x10 +#define USBVECINT_INPUT_ENDPOINT0 0x12 +#define USBVECINT_OUTPUT_ENDPOINT0 0x14 +#define USBVECINT_RSTR 0x16 +#define USBVECINT_SUSR 0x18 +#define USBVECINT_RESR 0x1A +#define USBVECINT_SETUP_PACKET_RECEIVED 0x20 +#define USBVECINT_STPOW_PACKET_RECEIVED 0x22 +#define USBVECINT_INPUT_ENDPOINT1 0x24 +#define USBVECINT_INPUT_ENDPOINT2 0x26 +#define USBVECINT_INPUT_ENDPOINT3 0x28 +#define USBVECINT_INPUT_ENDPOINT4 0x2A +#define USBVECINT_INPUT_ENDPOINT5 0x2C +#define USBVECINT_INPUT_ENDPOINT6 0x2E +#define USBVECINT_INPUT_ENDPOINT7 0x30 +#define USBVECINT_OUTPUT_ENDPOINT1 0x32 +#define USBVECINT_OUTPUT_ENDPOINT2 0x34 +#define USBVECINT_OUTPUT_ENDPOINT3 0x36 +#define USBVECINT_OUTPUT_ENDPOINT4 0x38 +#define USBVECINT_OUTPUT_ENDPOINT5 0x3A +#define USBVECINT_OUTPUT_ENDPOINT6 0x3C +#define USBVECINT_OUTPUT_ENDPOINT7 0x3E + + +/* ========================================================================= */ +/* USB Operation Registers */ +/* ========================================================================= */ + +#define USBIEPSIZXY_7 0x23FF /* Input Endpoint_7: X/Y-buffer size */ +#define USBIEPBCTY_7 0x23FE /* Input Endpoint_7: Y-byte count */ +#define USBIEPBBAY_7 0x23FD /* Input Endpoint_7: Y-buffer base addr. */ +//sfrb Spare (0x23FC) /* Not used */ +//sfrb Spare (0x23FB) /* Not used */ +#define USBIEPBCTX_7 0x23FA /* Input Endpoint_7: X-byte count */ +#define USBIEPBBAX_7 0x23F9 /* Input Endpoint_7: X-buffer base addr. */ +#define USBIEPCNF_7 0x23F8 /* Input Endpoint_7: Configuration */ +#define USBIEPSIZXY_6 0x23F7 /* Input Endpoint_6: X/Y-buffer size */ +#define USBIEPBCTY_6 0x23F6 /* Input Endpoint_6: Y-byte count */ +#define USBIEPBBAY_6 0x23F5 /* Input Endpoint_6: Y-buffer base addr. */ +//sfrb Spare (0x23F4) /* Not used */ +//sfrb Spare (0x23F3) /* Not used */ +#define USBIEPBCTX_6 0x23F2 /* Input Endpoint_6: X-byte count */ +#define USBIEPBBAX_6 0x23F1 /* Input Endpoint_6: X-buffer base addr. */ +#define USBIEPCNF_6 0x23F0 /* Input Endpoint_6: Configuration */ +#define USBIEPSIZXY_5 0x23EF /* Input Endpoint_5: X/Y-buffer size */ +#define USBIEPBCTY_5 0x23EE /* Input Endpoint_5: Y-byte count */ +#define USBIEPBBAY_5 0x23ED /* Input Endpoint_5: Y-buffer base addr. */ +//sfrb Spare (0x23EC) /* Not used */ +//sfrb Spare (0x23EB) /* Not used */ +#define USBIEPBCTX_5 0x23EA /* Input Endpoint_5: X-byte count */ +#define USBIEPBBAX_5 0x23E9 /* Input Endpoint_5: X-buffer base addr. */ +#define USBIEPCNF_5 0x23E8 /* Input Endpoint_5: Configuration */ +#define USBIEPSIZXY_4 0x23E7 /* Input Endpoint_4: X/Y-buffer size */ +#define USBIEPBCTY_4 0x23E6 /* Input Endpoint_4: Y-byte count */ +#define USBIEPBBAY_4 0x23E5 /* Input Endpoint_4: Y-buffer base addr. */ +//sfrb Spare (0x23E4) /* Not used */ +//sfrb Spare (0x23E3) /* Not used */ +#define USBIEPBCTX_4 0x23E2 /* Input Endpoint_4: X-byte count */ +#define USBIEPBBAX_4 0x23E1 /* Input Endpoint_4: X-buffer base addr. */ +#define USBIEPCNF_4 0x23E0 /* Input Endpoint_4: Configuration */ +#define USBIEPSIZXY_3 0x23DF /* Input Endpoint_3: X/Y-buffer size */ +#define USBIEPBCTY_3 0x23DE /* Input Endpoint_3: Y-byte count */ +#define USBIEPBBAY_3 0x23DD /* Input Endpoint_3: Y-buffer base addr. */ +//sfrb Spare (0x23DC) /* Not used */ +//sfrb Spare (0x23DB) /* Not used */ +#define USBIEPBCTX_3 0x23DA /* Input Endpoint_3: X-byte count */ +#define USBIEPBBAX_3 0x23D9 /* Input Endpoint_3: X-buffer base addr. */ +#define USBIEPCNF_3 0x23D8 /* Input Endpoint_3: Configuration */ +#define USBIEPSIZXY_2 0x23D7 /* Input Endpoint_2: X/Y-buffer size */ +#define USBIEPBCTY_2 0x23D6 /* Input Endpoint_2: Y-byte count */ +#define USBIEPBBAY_2 0x23D5 /* Input Endpoint_2: Y-buffer base addr. */ +//sfrb Spare (0x23D4) /* Not used */ +//sfrb Spare (0x23D3) /* Not used */ +#define USBIEPBCTX_2 0x23D2 /* Input Endpoint_2: X-byte count */ +#define USBIEPBBAX_2 0x23D1 /* Input Endpoint_2: X-buffer base addr. */ +#define USBIEPCNF_2 0x23D0 /* Input Endpoint_2: Configuration */ +#define USBIEPSIZXY_1 0x23CF /* Input Endpoint_1: X/Y-buffer size */ +#define USBIEPBCTY_1 0x23CE /* Input Endpoint_1: Y-byte count */ +#define USBIEPBBAY_1 0x23CD /* Input Endpoint_1: Y-buffer base addr. */ +//sfrb Spare (0x23CC) /* Not used */ +//sfrb Spare (0x23CB) /* Not used */ +#define USBIEPBCTX_1 0x23CA /* Input Endpoint_1: X-byte count */ +#define USBIEPBBAX_1 0x23C9 /* Input Endpoint_1: X-buffer base addr. */ +#define USBIEPCNF_1 0x23C8 /* Input Endpoint_1: Configuration */ +//sfrb (0x23C7) /* */ +//sfrb RESERVED (0x1C00) /* */ +//sfrb (0x23C0) /* */ +#define USBOEPSIZXY_7 0x23BF /* Output Endpoint_7: X/Y-buffer size */ +#define USBOEPBCTY_7 0x23BE /* Output Endpoint_7: Y-byte count */ +#define USBOEPBBAY_7 0x23BD /* Output Endpoint_7: Y-buffer base addr. */ +//sfrb Spare (0x23BC) /* Not used */ +//sfrb Spare (0x23BB) /* Not used */ +#define USBOEPBCTX_7 0x23BA /* Output Endpoint_7: X-byte count */ +#define USBOEPBBAX_7 0x23B9 /* Output Endpoint_7: X-buffer base addr. */ +#define USBOEPCNF_7 0x23B8 /* Output Endpoint_7: Configuration */ +#define USBOEPSIZXY_6 0x23B7 /* Output Endpoint_6: X/Y-buffer size */ +#define USBOEPBCTY_6 0x23B6 /* Output Endpoint_6: Y-byte count */ +#define USBOEPBBAY_6 0x23B5 /* Output Endpoint_6: Y-buffer base addr. */ +//sfrb Spare (0x23B4) /* Not used */ +//sfrb Spare (0x23B3) /* Not used */ +#define USBOEPBCTX_6 0x23B2 /* Output Endpoint_6: X-byte count */ +#define USBOEPBBAX_6 0x23B1 /* Output Endpoint_6: X-buffer base addr. */ +#define USBOEPCNF_6 0x23B0 /* Output Endpoint_6: Configuration */ +#define USBOEPSIZXY_5 0x23AF /* Output Endpoint_5: X/Y-buffer size */ +#define USBOEPBCTY_5 0x23AE /* Output Endpoint_5: Y-byte count */ +#define USBOEPBBAY_5 0x23AD /* Output Endpoint_5: Y-buffer base addr. */ +//sfrb Spare (0x23AC) /* Not used */ +//sfrb Spare (0x23AB) /* Not used */ +#define USBOEPBCTX_5 0x23AA /* Output Endpoint_5: X-byte count */ +#define USBOEPBBAX_5 0x23A9 /* Output Endpoint_5: X-buffer base addr. */ +#define USBOEPCNF_5 0x23A8 /* Output Endpoint_5: Configuration */ +#define USBOEPSIZXY_4 0x23A7 /* Output Endpoint_4: X/Y-buffer size */ +#define USBOEPBCTY_4 0x23A6 /* Output Endpoint_4: Y-byte count */ +#define USBOEPBBAY_4 0x23A5 /* Output Endpoint_4: Y-buffer base addr. */ +//sfrb Spare (0x23A4) /* Not used */ +//sfrb Spare (0x23A3) /* Not used */ +#define USBOEPBCTX_4 0x23A2 /* Output Endpoint_4: X-byte count */ +#define USBOEPBBAX_4 0x23A1 /* Output Endpoint_4: X-buffer base addr. */ +#define USBOEPCNF_4 0x23A0 /* Output Endpoint_4: Configuration */ +#define USBOEPSIZXY_3 0x239F /* Output Endpoint_3: X/Y-buffer size */ +#define USBOEPBCTY_3 0x239E /* Output Endpoint_3: Y-byte count */ +#define USBOEPBBAY_3 0x239D /* Output Endpoint_3: Y-buffer base addr. */ +//sfrb Spare (0x239C) /* Not used */ +//sfrb Spare (0x239B) /* Not used */ +#define USBOEPBCTX_3 0x239A /* Output Endpoint_3: X-byte count */ +#define USBOEPBBAX_3 0x2399 /* Output Endpoint_3: X-buffer base addr. */ +#define USBOEPCNF_3 0x2398 /* Output Endpoint_3: Configuration */ +#define USBOEPSIZXY_2 0x2397 /* Output Endpoint_2: X/Y-buffer size */ +#define USBOEPBCTY_2 0x2396 /* Output Endpoint_2: Y-byte count */ +#define USBOEPBBAY_2 0x2395 /* Output Endpoint_2: Y-buffer base addr. */ +//sfrb Spare (0x2394) /* Not used */ +//sfrb Spare (0x2393) /* Not used */ +#define USBOEPBCTX_2 0x2392 /* Output Endpoint_2: X-byte count */ +#define USBOEPBBAX_2 0x2391 /* Output Endpoint_2: X-buffer base addr. */ +#define USBOEPCNF_2 0x2390 /* Output Endpoint_2: Configuration */ +#define USBOEPSIZXY_1 0x238F /* Output Endpoint_1: X/Y-buffer size */ +#define USBOEPBCTY_1 0x238E /* Output Endpoint_1: Y-byte count */ +#define USBOEPBBAY_1 0x238D /* Output Endpoint_1: Y-buffer base addr. */ +//sfrb Spare (0x238C) /* Not used */ +//sfrb Spare (0x238B) /* Not used */ +#define USBOEPBCTX_1 0x238A /* Output Endpoint_1: X-byte count */ +#define USBOEPBBAX_1 0x2389 /* Output Endpoint_1: X-buffer base addr. */ +#define USBOEPCNF_1 0x2388 /* Output Endpoint_1: Configuration */ +#define USBSUBLK 0x2380 /* Setup Packet Block */ +#define USBIEP0BUF 0x2378 /* Input endpoint_0 buffer */ +#define USBOEP0BUF 0x2370 /* Output endpoint_0 buffer */ +#define USBTOPBUFF 0x236F /* Top of buffer space */ +// (1904 Bytes) /* Buffer space */ +#define USBSTABUFF 0x1C00 /* Start of buffer space */ + +/* USBIEPCNF_n Control Bits */ +/* USBOEPCNF_n Control Bits */ +//#define RESERVED (0x0001) /* USB - */ +//#define RESERVED (0x0001) /* USB - */ +#define DBUF (0x0010) /* USB - Double Buffer Enable */ +//#define RESERVED (0x0040) /* USB - */ + +/* USBIEPBCNT_n Control Bits */ +/* USBOEPBCNT_n Control Bits */ +#define CNT4 (0x0010) /* USB - Byte Count Bit 3 */ +#define CNT5 (0x0020) /* USB - Byte Count Bit 3 */ +#define CNT6 (0x0040) /* USB - Byte Count Bit 3 */ +/************************************************************ +* UNIFIED CLOCK SYSTEM +************************************************************/ + +#define UCSCTL0 0x0160 /* UCS Control Register 0 */ +#define UCSCTL1 0x0162 /* UCS Control Register 1 */ +#define UCSCTL2 0x0164 /* UCS Control Register 2 */ +#define UCSCTL3 0x0166 /* UCS Control Register 3 */ +#define UCSCTL4 0x0168 /* UCS Control Register 4 */ +#define UCSCTL5 0x016A /* UCS Control Register 5 */ +#define UCSCTL6 0x016C /* UCS Control Register 6 */ +#define UCSCTL7 0x016E /* UCS Control Register 7 */ +#define UCSCTL8 0x0170 /* UCS Control Register 8 */ + +/* UCSCTL0 Control Bits */ +//#define RESERVED (0x0001) /* RESERVED */ +//#define RESERVED (0x0002) /* RESERVED */ +//#define RESERVED (0x0004) /* RESERVED */ +#define MOD0 (0x0008) /* Modulation Bit Counter Bit : 0 */ +#define MOD1 (0x0010) /* Modulation Bit Counter Bit : 1 */ +#define MOD2 (0x0020) /* Modulation Bit Counter Bit : 2 */ +#define MOD3 (0x0040) /* Modulation Bit Counter Bit : 3 */ +#define MOD4 (0x0080) /* Modulation Bit Counter Bit : 4 */ +#define DCO0 (0x0100) /* DCO TAP Bit : 0 */ +#define DCO1 (0x0200) /* DCO TAP Bit : 1 */ +#define DCO2 (0x0400) /* DCO TAP Bit : 2 */ +#define DCO3 (0x0800) /* DCO TAP Bit : 3 */ +#define DCO4 (0x1000) /* DCO TAP Bit : 4 */ +//#define RESERVED (0x2000) /* RESERVED */ +//#define RESERVED (0x4000) /* RESERVED */ +//#define RESERVED (0x8000) /* RESERVED */ + +/* UCSCTL0 Control Bits */ +//#define RESERVED (0x0001) /* RESERVED */ +//#define RESERVED (0x0002) /* RESERVED */ +//#define RESERVED (0x0004) /* RESERVED */ +#define MOD0_L (0x0008) /* Modulation Bit Counter Bit : 0 */ +#define MOD1_L (0x0010) /* Modulation Bit Counter Bit : 1 */ +#define MOD2_L (0x0020) /* Modulation Bit Counter Bit : 2 */ +#define MOD3_L (0x0040) /* Modulation Bit Counter Bit : 3 */ +#define MOD4_L (0x0080) /* Modulation Bit Counter Bit : 4 */ +//#define RESERVED (0x2000) /* RESERVED */ +//#define RESERVED (0x4000) /* RESERVED */ +//#define RESERVED (0x8000) /* RESERVED */ + +/* UCSCTL0 Control Bits */ +//#define RESERVED (0x0001) /* RESERVED */ +//#define RESERVED (0x0002) /* RESERVED */ +//#define RESERVED (0x0004) /* RESERVED */ +#define DCO0_H (0x0001) /* DCO TAP Bit : 0 */ +#define DCO1_H (0x0002) /* DCO TAP Bit : 1 */ +#define DCO2_H (0x0004) /* DCO TAP Bit : 2 */ +#define DCO3_H (0x0008) /* DCO TAP Bit : 3 */ +#define DCO4_H (0x0010) /* DCO TAP Bit : 4 */ +//#define RESERVED (0x2000) /* RESERVED */ +//#define RESERVED (0x4000) /* RESERVED */ +//#define RESERVED (0x8000) /* RESERVED */ + +/* UCSCTL1 Control Bits */ +#define DISMOD (0x0001) /* Disable Modulation */ +//#define RESERVED (0x0002) /* RESERVED */ +//#define RESERVED (0x0004) /* RESERVED */ +//#define RESERVED (0x0008) /* RESERVED */ +#define DCORSEL0 (0x0010) /* DCO Freq. Range Select Bit : 0 */ +#define DCORSEL1 (0x0020) /* DCO Freq. Range Select Bit : 1 */ +#define DCORSEL2 (0x0040) /* DCO Freq. Range Select Bit : 2 */ +//#define RESERVED (0x0080) /* RESERVED */ +//#define RESERVED (0x0100) /* RESERVED */ +//#define RESERVED (0x0200) /* RESERVED */ +//#define RESERVED (0x0400) /* RESERVED */ +//#define RESERVED (0x0800) /* RESERVED */ +//#define RESERVED (0x1000) /* RESERVED */ +//#define RESERVED (0x2000) /* RESERVED */ +//#define RESERVED (0x4000) /* RESERVED */ +//#define RESERVED (0x8000) /* RESERVED */ + +/* UCSCTL1 Control Bits */ +#define DISMOD_L (0x0001) /* Disable Modulation */ +//#define RESERVED (0x0002) /* RESERVED */ +//#define RESERVED (0x0004) /* RESERVED */ +//#define RESERVED (0x0008) /* RESERVED */ +#define DCORSEL0_L (0x0010) /* DCO Freq. Range Select Bit : 0 */ +#define DCORSEL1_L (0x0020) /* DCO Freq. Range Select Bit : 1 */ +#define DCORSEL2_L (0x0040) /* DCO Freq. Range Select Bit : 2 */ +//#define RESERVED (0x0080) /* RESERVED */ +//#define RESERVED (0x0100) /* RESERVED */ +//#define RESERVED (0x0200) /* RESERVED */ +//#define RESERVED (0x0400) /* RESERVED */ +//#define RESERVED (0x0800) /* RESERVED */ +//#define RESERVED (0x1000) /* RESERVED */ +//#define RESERVED (0x2000) /* RESERVED */ +//#define RESERVED (0x4000) /* RESERVED */ +//#define RESERVED (0x8000) /* RESERVED */ + + +#define DCORSEL_0 (0x0000) /* DCO RSEL 0 */ +#define DCORSEL_1 (0x0010) /* DCO RSEL 1 */ +#define DCORSEL_2 (0x0020) /* DCO RSEL 2 */ +#define DCORSEL_3 (0x0030) /* DCO RSEL 3 */ +#define DCORSEL_4 (0x0040) /* DCO RSEL 4 */ +#define DCORSEL_5 (0x0050) /* DCO RSEL 5 */ +#define DCORSEL_6 (0x0060) /* DCO RSEL 6 */ +#define DCORSEL_7 (0x0070) /* DCO RSEL 7 */ + + +/* UCSCTL2 Control Bits */ +#define FLLN0 (0x0001) /* FLL Multipier Bit : 0 */ +#define FLLN1 (0x0002) /* FLL Multipier Bit : 1 */ +#define FLLN2 (0x0004) /* FLL Multipier Bit : 2 */ +#define FLLN3 (0x0008) /* FLL Multipier Bit : 3 */ +#define FLLN4 (0x0010) /* FLL Multipier Bit : 4 */ +#define FLLN5 (0x0020) /* FLL Multipier Bit : 5 */ +#define FLLN6 (0x0040) /* FLL Multipier Bit : 6 */ +#define FLLN7 (0x0080) /* FLL Multipier Bit : 7 */ +#define FLLN8 (0x0100) /* FLL Multipier Bit : 8 */ +#define FLLN9 (0x0200) /* FLL Multipier Bit : 9 */ +//#define RESERVED (0x0400) /* RESERVED */ +//#define RESERVED (0x0800) /* RESERVED */ +#define FLLD0 (0x1000) /* Loop Divider Bit : 0 */ +#define FLLD1 (0x2000) /* Loop Divider Bit : 1 */ +#define FLLD2 (0x4000) /* Loop Divider Bit : 1 */ +//#define RESERVED (0x8000) /* RESERVED */ + +/* UCSCTL2 Control Bits */ +#define FLLN0_L (0x0001) /* FLL Multipier Bit : 0 */ +#define FLLN1_L (0x0002) /* FLL Multipier Bit : 1 */ +#define FLLN2_L (0x0004) /* FLL Multipier Bit : 2 */ +#define FLLN3_L (0x0008) /* FLL Multipier Bit : 3 */ +#define FLLN4_L (0x0010) /* FLL Multipier Bit : 4 */ +#define FLLN5_L (0x0020) /* FLL Multipier Bit : 5 */ +#define FLLN6_L (0x0040) /* FLL Multipier Bit : 6 */ +#define FLLN7_L (0x0080) /* FLL Multipier Bit : 7 */ +//#define RESERVED (0x0400) /* RESERVED */ +//#define RESERVED (0x0800) /* RESERVED */ +//#define RESERVED (0x8000) /* RESERVED */ + +/* UCSCTL2 Control Bits */ +#define FLLN8_H (0x0001) /* FLL Multipier Bit : 8 */ +#define FLLN9_H (0x0002) /* FLL Multipier Bit : 9 */ +//#define RESERVED (0x0400) /* RESERVED */ +//#define RESERVED (0x0800) /* RESERVED */ +#define FLLD0_H (0x0010) /* Loop Divider Bit : 0 */ +#define FLLD1_H (0x0020) /* Loop Divider Bit : 1 */ +#define FLLD2_H (0x0040) /* Loop Divider Bit : 1 */ +//#define RESERVED (0x8000) /* RESERVED */ + +#define FLLD_0 (0x0000) /* Multiply Selected Loop Freq. 1 */ +#define FLLD_1 (0x1000) /* Multiply Selected Loop Freq. 2 */ +#define FLLD_2 (0x2000) /* Multiply Selected Loop Freq. 4 */ +#define FLLD_3 (0x3000) /* Multiply Selected Loop Freq. 8 */ +#define FLLD_4 (0x4000) /* Multiply Selected Loop Freq. 16 */ +#define FLLD_5 (0x5000) /* Multiply Selected Loop Freq. 32 */ +#define FLLD_6 (0x6000) /* Multiply Selected Loop Freq. 32 */ +#define FLLD_7 (0x7000) /* Multiply Selected Loop Freq. 32 */ +#define FLLD__1 (0x0000) /* Multiply Selected Loop Freq. By 1 */ +#define FLLD__2 (0x1000) /* Multiply Selected Loop Freq. By 2 */ +#define FLLD__4 (0x2000) /* Multiply Selected Loop Freq. By 4 */ +#define FLLD__8 (0x3000) /* Multiply Selected Loop Freq. By 8 */ +#define FLLD__16 (0x4000) /* Multiply Selected Loop Freq. By 16 */ +#define FLLD__32 (0x5000) /* Multiply Selected Loop Freq. By 32 */ + + +/* UCSCTL3 Control Bits */ +#define FLLREFDIV0 (0x0001) /* Reference Divider Bit : 0 */ +#define FLLREFDIV1 (0x0002) /* Reference Divider Bit : 1 */ +#define FLLREFDIV2 (0x0004) /* Reference Divider Bit : 2 */ +//#define RESERVED (0x0008) /* RESERVED */ +#define SELREF0 (0x0010) /* FLL Reference Clock Select Bit : 0 */ +#define SELREF1 (0x0020) /* FLL Reference Clock Select Bit : 1 */ +#define SELREF2 (0x0040) /* FLL Reference Clock Select Bit : 2 */ +//#define RESERVED (0x0080) /* RESERVED */ +//#define RESERVED (0x0100) /* RESERVED */ +//#define RESERVED (0x0200) /* RESERVED */ +//#define RESERVED (0x0400) /* RESERVED */ +//#define RESERVED (0x0800) /* RESERVED */ +//#define RESERVED (0x1000) /* RESERVED */ +//#define RESERVED (0x2000) /* RESERVED */ +//#define RESERVED (0x4000) /* RESERVED */ +//#define RESERVED (0x8000) /* RESERVED */ + +/* UCSCTL3 Control Bits */ +#define FLLREFDIV0_L (0x0001) /* Reference Divider Bit : 0 */ +#define FLLREFDIV1_L (0x0002) /* Reference Divider Bit : 1 */ +#define FLLREFDIV2_L (0x0004) /* Reference Divider Bit : 2 */ +//#define RESERVED (0x0008) /* RESERVED */ +#define SELREF0_L (0x0010) /* FLL Reference Clock Select Bit : 0 */ +#define SELREF1_L (0x0020) /* FLL Reference Clock Select Bit : 1 */ +#define SELREF2_L (0x0040) /* FLL Reference Clock Select Bit : 2 */ +//#define RESERVED (0x0080) /* RESERVED */ +//#define RESERVED (0x0100) /* RESERVED */ +//#define RESERVED (0x0200) /* RESERVED */ +//#define RESERVED (0x0400) /* RESERVED */ +//#define RESERVED (0x0800) /* RESERVED */ +//#define RESERVED (0x1000) /* RESERVED */ +//#define RESERVED (0x2000) /* RESERVED */ +//#define RESERVED (0x4000) /* RESERVED */ +//#define RESERVED (0x8000) /* RESERVED */ + + +#define FLLREFDIV_0 (0x0000) /* Reference Divider: f(LFCLK)/1 */ +#define FLLREFDIV_1 (0x0001) /* Reference Divider: f(LFCLK)/2 */ +#define FLLREFDIV_2 (0x0002) /* Reference Divider: f(LFCLK)/4 */ +#define FLLREFDIV_3 (0x0003) /* Reference Divider: f(LFCLK)/8 */ +#define FLLREFDIV_4 (0x0004) /* Reference Divider: f(LFCLK)/12 */ +#define FLLREFDIV_5 (0x0005) /* Reference Divider: f(LFCLK)/16 */ +#define FLLREFDIV_6 (0x0006) /* Reference Divider: f(LFCLK)/16 */ +#define FLLREFDIV_7 (0x0007) /* Reference Divider: f(LFCLK)/16 */ +#define FLLREFDIV__1 (0x0000) /* Reference Divider: f(LFCLK)/1 */ +#define FLLREFDIV__2 (0x0001) /* Reference Divider: f(LFCLK)/2 */ +#define FLLREFDIV__4 (0x0002) /* Reference Divider: f(LFCLK)/4 */ +#define FLLREFDIV__8 (0x0003) /* Reference Divider: f(LFCLK)/8 */ +#define FLLREFDIV__12 (0x0004) /* Reference Divider: f(LFCLK)/12 */ +#define FLLREFDIV__16 (0x0005) /* Reference Divider: f(LFCLK)/16 */ +#define SELREF_0 (0x0000) /* FLL Reference Clock Select 0 */ +#define SELREF_1 (0x0010) /* FLL Reference Clock Select 1 */ +#define SELREF_2 (0x0020) /* FLL Reference Clock Select 2 */ +#define SELREF_3 (0x0030) /* FLL Reference Clock Select 3 */ +#define SELREF_4 (0x0040) /* FLL Reference Clock Select 4 */ +#define SELREF_5 (0x0050) /* FLL Reference Clock Select 5 */ +#define SELREF_6 (0x0060) /* FLL Reference Clock Select 6 */ +#define SELREF_7 (0x0070) /* FLL Reference Clock Select 7 */ +#define SELREF__XT1CLK (0x0000) /* Multiply Selected Loop Freq. By XT1CLK */ +#define SELREF__REFOCLK (0x0020) /* Multiply Selected Loop Freq. By REFOCLK */ +#define SELREF__XT2CLK (0x0050) /* Multiply Selected Loop Freq. By XT2CLK */ + +/* UCSCTL4 Control Bits */ +#define SELM0 (0x0001) /* MCLK Source Select Bit: 0 */ +#define SELM1 (0x0002) /* MCLK Source Select Bit: 1 */ +#define SELM2 (0x0004) /* MCLK Source Select Bit: 2 */ +//#define RESERVED (0x0008) /* RESERVED */ +#define SELS0 (0x0010) /* SMCLK Source Select Bit: 0 */ +#define SELS1 (0x0020) /* SMCLK Source Select Bit: 1 */ +#define SELS2 (0x0040) /* SMCLK Source Select Bit: 2 */ +//#define RESERVED (0x0080) /* RESERVED */ +#define SELA0 (0x0100) /* ACLK Source Select Bit: 0 */ +#define SELA1 (0x0200) /* ACLK Source Select Bit: 1 */ +#define SELA2 (0x0400) /* ACLK Source Select Bit: 2 */ +//#define RESERVED (0x0800) /* RESERVED */ +//#define RESERVED (0x1000) /* RESERVED */ +//#define RESERVED (0x2000) /* RESERVED */ +//#define RESERVED (0x4000) /* RESERVED */ +//#define RESERVED (0x8000) /* RESERVED */ + +/* UCSCTL4 Control Bits */ +#define SELM0_L (0x0001) /* MCLK Source Select Bit: 0 */ +#define SELM1_L (0x0002) /* MCLK Source Select Bit: 1 */ +#define SELM2_L (0x0004) /* MCLK Source Select Bit: 2 */ +//#define RESERVED (0x0008) /* RESERVED */ +#define SELS0_L (0x0010) /* SMCLK Source Select Bit: 0 */ +#define SELS1_L (0x0020) /* SMCLK Source Select Bit: 1 */ +#define SELS2_L (0x0040) /* SMCLK Source Select Bit: 2 */ +//#define RESERVED (0x0080) /* RESERVED */ +//#define RESERVED (0x0800) /* RESERVED */ +//#define RESERVED (0x1000) /* RESERVED */ +//#define RESERVED (0x2000) /* RESERVED */ +//#define RESERVED (0x4000) /* RESERVED */ +//#define RESERVED (0x8000) /* RESERVED */ + +/* UCSCTL4 Control Bits */ +//#define RESERVED (0x0008) /* RESERVED */ +//#define RESERVED (0x0080) /* RESERVED */ +#define SELA0_H (0x0001) /* ACLK Source Select Bit: 0 */ +#define SELA1_H (0x0002) /* ACLK Source Select Bit: 1 */ +#define SELA2_H (0x0004) /* ACLK Source Select Bit: 2 */ +//#define RESERVED (0x0800) /* RESERVED */ +//#define RESERVED (0x1000) /* RESERVED */ +//#define RESERVED (0x2000) /* RESERVED */ +//#define RESERVED (0x4000) /* RESERVED */ +//#define RESERVED (0x8000) /* RESERVED */ + +#define SELM_0 (0x0000) /* MCLK Source Select 0 */ +#define SELM_1 (0x0001) /* MCLK Source Select 1 */ +#define SELM_2 (0x0002) /* MCLK Source Select 2 */ +#define SELM_3 (0x0003) /* MCLK Source Select 3 */ +#define SELM_4 (0x0004) /* MCLK Source Select 4 */ +#define SELM_5 (0x0005) /* MCLK Source Select 5 */ +#define SELM_6 (0x0006) /* MCLK Source Select 6 */ +#define SELM_7 (0x0007) /* MCLK Source Select 7 */ +#define SELM__XT1CLK (0x0000) /* MCLK Source Select XT1CLK */ +#define SELM__VLOCLK (0x0001) /* MCLK Source Select VLOCLK */ +#define SELM__REFOCLK (0x0002) /* MCLK Source Select REFOCLK */ +#define SELM__DCOCLK (0x0003) /* MCLK Source Select DCOCLK */ +#define SELM__DCOCLKDIV (0x0004) /* MCLK Source Select DCOCLKDIV */ +#define SELM__XT2CLK (0x0005) /* MCLK Source Select XT2CLK */ + +#define SELS_0 (0x0000) /* SMCLK Source Select 0 */ +#define SELS_1 (0x0010) /* SMCLK Source Select 1 */ +#define SELS_2 (0x0020) /* SMCLK Source Select 2 */ +#define SELS_3 (0x0030) /* SMCLK Source Select 3 */ +#define SELS_4 (0x0040) /* SMCLK Source Select 4 */ +#define SELS_5 (0x0050) /* SMCLK Source Select 5 */ +#define SELS_6 (0x0060) /* SMCLK Source Select 6 */ +#define SELS_7 (0x0070) /* SMCLK Source Select 7 */ +#define SELS__XT1CLK (0x0000) /* SMCLK Source Select XT1CLK */ +#define SELS__VLOCLK (0x0010) /* SMCLK Source Select VLOCLK */ +#define SELS__REFOCLK (0x0020) /* SMCLK Source Select REFOCLK */ +#define SELS__DCOCLK (0x0030) /* SMCLK Source Select DCOCLK */ +#define SELS__DCOCLKDIV (0x0040) /* SMCLK Source Select DCOCLKDIV */ +#define SELS__XT2CLK (0x0050) /* SMCLK Source Select XT2CLK */ + +#define SELA_0 (0x0000) /* ACLK Source Select 0 */ +#define SELA_1 (0x0100) /* ACLK Source Select 1 */ +#define SELA_2 (0x0200) /* ACLK Source Select 2 */ +#define SELA_3 (0x0300) /* ACLK Source Select 3 */ +#define SELA_4 (0x0400) /* ACLK Source Select 4 */ +#define SELA_5 (0x0500) /* ACLK Source Select 5 */ +#define SELA_6 (0x0600) /* ACLK Source Select 6 */ +#define SELA_7 (0x0700) /* ACLK Source Select 7 */ +#define SELA__XT1CLK (0x0000) /* ACLK Source Select XT1CLK */ +#define SELA__VLOCLK (0x0100) /* ACLK Source Select VLOCLK */ +#define SELA__REFOCLK (0x0200) /* ACLK Source Select REFOCLK */ +#define SELA__DCOCLK (0x0300) /* ACLK Source Select DCOCLK */ +#define SELA__DCOCLKDIV (0x0400) /* ACLK Source Select DCOCLKDIV */ +#define SELA__XT2CLK (0x0500) /* ACLK Source Select XT2CLK */ + +/* UCSCTL5 Control Bits */ +#define DIVM0 (0x0001) /* MCLK Divider Bit: 0 */ +#define DIVM1 (0x0002) /* MCLK Divider Bit: 1 */ +#define DIVM2 (0x0004) /* MCLK Divider Bit: 2 */ +//#define RESERVED (0x0008) /* RESERVED */ +#define DIVS0 (0x0010) /* SMCLK Divider Bit: 0 */ +#define DIVS1 (0x0020) /* SMCLK Divider Bit: 1 */ +#define DIVS2 (0x0040) /* SMCLK Divider Bit: 2 */ +//#define RESERVED (0x0080) /* RESERVED */ +#define DIVA0 (0x0100) /* ACLK Divider Bit: 0 */ +#define DIVA1 (0x0200) /* ACLK Divider Bit: 1 */ +#define DIVA2 (0x0400) /* ACLK Divider Bit: 2 */ +//#define RESERVED (0x0800) /* RESERVED */ +#define DIVPA0 (0x1000) /* ACLK from Pin Divider Bit: 0 */ +#define DIVPA1 (0x2000) /* ACLK from Pin Divider Bit: 1 */ +#define DIVPA2 (0x4000) /* ACLK from Pin Divider Bit: 2 */ +//#define RESERVED (0x8000) /* RESERVED */ + +/* UCSCTL5 Control Bits */ +#define DIVM0_L (0x0001) /* MCLK Divider Bit: 0 */ +#define DIVM1_L (0x0002) /* MCLK Divider Bit: 1 */ +#define DIVM2_L (0x0004) /* MCLK Divider Bit: 2 */ +//#define RESERVED (0x0008) /* RESERVED */ +#define DIVS0_L (0x0010) /* SMCLK Divider Bit: 0 */ +#define DIVS1_L (0x0020) /* SMCLK Divider Bit: 1 */ +#define DIVS2_L (0x0040) /* SMCLK Divider Bit: 2 */ +//#define RESERVED (0x0080) /* RESERVED */ +//#define RESERVED (0x0800) /* RESERVED */ +//#define RESERVED (0x8000) /* RESERVED */ + +/* UCSCTL5 Control Bits */ +//#define RESERVED (0x0008) /* RESERVED */ +//#define RESERVED (0x0080) /* RESERVED */ +#define DIVA0_H (0x0001) /* ACLK Divider Bit: 0 */ +#define DIVA1_H (0x0002) /* ACLK Divider Bit: 1 */ +#define DIVA2_H (0x0004) /* ACLK Divider Bit: 2 */ +//#define RESERVED (0x0800) /* RESERVED */ +#define DIVPA0_H (0x0010) /* ACLK from Pin Divider Bit: 0 */ +#define DIVPA1_H (0x0020) /* ACLK from Pin Divider Bit: 1 */ +#define DIVPA2_H (0x0040) /* ACLK from Pin Divider Bit: 2 */ +//#define RESERVED (0x8000) /* RESERVED */ + +#define DIVM_0 (0x0000) /* MCLK Source Divider 0 */ +#define DIVM_1 (0x0001) /* MCLK Source Divider 1 */ +#define DIVM_2 (0x0002) /* MCLK Source Divider 2 */ +#define DIVM_3 (0x0003) /* MCLK Source Divider 3 */ +#define DIVM_4 (0x0004) /* MCLK Source Divider 4 */ +#define DIVM_5 (0x0005) /* MCLK Source Divider 5 */ +#define DIVM_6 (0x0006) /* MCLK Source Divider 6 */ +#define DIVM_7 (0x0007) /* MCLK Source Divider 7 */ +#define DIVM__1 (0x0000) /* MCLK Source Divider f(MCLK)/1 */ +#define DIVM__2 (0x0001) /* MCLK Source Divider f(MCLK)/2 */ +#define DIVM__4 (0x0002) /* MCLK Source Divider f(MCLK)/4 */ +#define DIVM__8 (0x0003) /* MCLK Source Divider f(MCLK)/8 */ +#define DIVM__16 (0x0004) /* MCLK Source Divider f(MCLK)/16 */ +#define DIVM__32 (0x0005) /* MCLK Source Divider f(MCLK)/32 */ + +#define DIVS_0 (0x0000) /* SMCLK Source Divider 0 */ +#define DIVS_1 (0x0010) /* SMCLK Source Divider 1 */ +#define DIVS_2 (0x0020) /* SMCLK Source Divider 2 */ +#define DIVS_3 (0x0030) /* SMCLK Source Divider 3 */ +#define DIVS_4 (0x0040) /* SMCLK Source Divider 4 */ +#define DIVS_5 (0x0050) /* SMCLK Source Divider 5 */ +#define DIVS_6 (0x0060) /* SMCLK Source Divider 6 */ +#define DIVS_7 (0x0070) /* SMCLK Source Divider 7 */ +#define DIVS__1 (0x0000) /* SMCLK Source Divider f(SMCLK)/1 */ +#define DIVS__2 (0x0010) /* SMCLK Source Divider f(SMCLK)/2 */ +#define DIVS__4 (0x0020) /* SMCLK Source Divider f(SMCLK)/4 */ +#define DIVS__8 (0x0030) /* SMCLK Source Divider f(SMCLK)/8 */ +#define DIVS__16 (0x0040) /* SMCLK Source Divider f(SMCLK)/16 */ +#define DIVS__32 (0x0050) /* SMCLK Source Divider f(SMCLK)/32 */ + +#define DIVA_0 (0x0000) /* ACLK Source Divider 0 */ +#define DIVA_1 (0x0100) /* ACLK Source Divider 1 */ +#define DIVA_2 (0x0200) /* ACLK Source Divider 2 */ +#define DIVA_3 (0x0300) /* ACLK Source Divider 3 */ +#define DIVA_4 (0x0400) /* ACLK Source Divider 4 */ +#define DIVA_5 (0x0500) /* ACLK Source Divider 5 */ +#define DIVA_6 (0x0600) /* ACLK Source Divider 6 */ +#define DIVA_7 (0x0700) /* ACLK Source Divider 7 */ +#define DIVA__1 (0x0000) /* ACLK Source Divider f(ACLK)/1 */ +#define DIVA__2 (0x0100) /* ACLK Source Divider f(ACLK)/2 */ +#define DIVA__4 (0x0200) /* ACLK Source Divider f(ACLK)/4 */ +#define DIVA__8 (0x0300) /* ACLK Source Divider f(ACLK)/8 */ +#define DIVA__16 (0x0400) /* ACLK Source Divider f(ACLK)/16 */ +#define DIVA__32 (0x0500) /* ACLK Source Divider f(ACLK)/32 */ + +#define DIVPA_0 (0x0000) /* ACLK from Pin Source Divider 0 */ +#define DIVPA_1 (0x1000) /* ACLK from Pin Source Divider 1 */ +#define DIVPA_2 (0x2000) /* ACLK from Pin Source Divider 2 */ +#define DIVPA_3 (0x3000) /* ACLK from Pin Source Divider 3 */ +#define DIVPA_4 (0x4000) /* ACLK from Pin Source Divider 4 */ +#define DIVPA_5 (0x5000) /* ACLK from Pin Source Divider 5 */ +#define DIVPA_6 (0x6000) /* ACLK from Pin Source Divider 6 */ +#define DIVPA_7 (0x7000) /* ACLK from Pin Source Divider 7 */ +#define DIVPA__1 (0x0000) /* ACLK from Pin Source Divider f(ACLK)/1 */ +#define DIVPA__2 (0x1000) /* ACLK from Pin Source Divider f(ACLK)/2 */ +#define DIVPA__4 (0x2000) /* ACLK from Pin Source Divider f(ACLK)/4 */ +#define DIVPA__8 (0x3000) /* ACLK from Pin Source Divider f(ACLK)/8 */ +#define DIVPA__16 (0x4000) /* ACLK from Pin Source Divider f(ACLK)/16 */ +#define DIVPA__32 (0x5000) /* ACLK from Pin Source Divider f(ACLK)/32 */ + + +/* UCSCTL6 Control Bits */ +#define XT1OFF (0x0001) /* High Frequency Oscillator 1 (XT1) disable */ +#define SMCLKOFF (0x0002) /* SMCLK Off */ +#define XCAP0 (0x0004) /* XIN/XOUT Cap Bit: 0 */ +#define XCAP1 (0x0008) /* XIN/XOUT Cap Bit: 1 */ +#define XT1BYPASS (0x0010) /* XT1 bypass mode : 0: internal 1:sourced from external pin */ +#define XTS (0x0020) /* 1: Selects high-freq. oscillator */ +#define XT1DRIVE0 (0x0040) /* XT1 Drive Level mode Bit 0 */ +#define XT1DRIVE1 (0x0080) /* XT1 Drive Level mode Bit 1 */ +#define XT2OFF (0x0100) /* High Frequency Oscillator 2 (XT2) disable */ +//#define RESERVED (0x0200) /* RESERVED */ +//#define RESERVED (0x0400) /* RESERVED */ +//#define RESERVED (0x0800) /* RESERVED */ +#define XT2BYPASS (0x1000) /* XT2 bypass mode : 0: internal 1:sourced from external pin */ +//#define RESERVED (0x2000) /* RESERVED */ +#define XT2DRIVE0 (0x4000) /* XT2 Drive Level mode Bit 0 */ +#define XT2DRIVE1 (0x8000) /* XT2 Drive Level mode Bit 1 */ + +/* UCSCTL6 Control Bits */ +#define XT1OFF_L (0x0001) /* High Frequency Oscillator 1 (XT1) disable */ +#define SMCLKOFF_L (0x0002) /* SMCLK Off */ +#define XCAP0_L (0x0004) /* XIN/XOUT Cap Bit: 0 */ +#define XCAP1_L (0x0008) /* XIN/XOUT Cap Bit: 1 */ +#define XT1BYPASS_L (0x0010) /* XT1 bypass mode : 0: internal 1:sourced from external pin */ +#define XTS_L (0x0020) /* 1: Selects high-freq. oscillator */ +#define XT1DRIVE0_L (0x0040) /* XT1 Drive Level mode Bit 0 */ +#define XT1DRIVE1_L (0x0080) /* XT1 Drive Level mode Bit 1 */ +//#define RESERVED (0x0200) /* RESERVED */ +//#define RESERVED (0x0400) /* RESERVED */ +//#define RESERVED (0x0800) /* RESERVED */ +//#define RESERVED (0x2000) /* RESERVED */ + +/* UCSCTL6 Control Bits */ +#define XT2OFF_H (0x0001) /* High Frequency Oscillator 2 (XT2) disable */ +//#define RESERVED (0x0200) /* RESERVED */ +//#define RESERVED (0x0400) /* RESERVED */ +//#define RESERVED (0x0800) /* RESERVED */ +#define XT2BYPASS_H (0x0010) /* XT2 bypass mode : 0: internal 1:sourced from external pin */ +//#define RESERVED (0x2000) /* RESERVED */ +#define XT2DRIVE0_H (0x0040) /* XT2 Drive Level mode Bit 0 */ +#define XT2DRIVE1_H (0x0080) /* XT2 Drive Level mode Bit 1 */ + +#define XCAP_0 (0x0000) /* XIN/XOUT Cap 0 */ +#define XCAP_1 (0x0004) /* XIN/XOUT Cap 1 */ +#define XCAP_2 (0x0008) /* XIN/XOUT Cap 2 */ +#define XCAP_3 (0x000C) /* XIN/XOUT Cap 3 */ +#define XT1DRIVE_0 (0x0000) /* XT1 Drive Level mode: 0 */ +#define XT1DRIVE_1 (0x0040) /* XT1 Drive Level mode: 1 */ +#define XT1DRIVE_2 (0x0080) /* XT1 Drive Level mode: 2 */ +#define XT1DRIVE_3 (0x00C0) /* XT1 Drive Level mode: 3 */ +#define XT2DRIVE_0 (0x0000) /* XT2 Drive Level mode: 0 */ +#define XT2DRIVE_1 (0x4000) /* XT2 Drive Level mode: 1 */ +#define XT2DRIVE_2 (0x8000) /* XT2 Drive Level mode: 2 */ +#define XT2DRIVE_3 (0xC000) /* XT2 Drive Level mode: 3 */ + + +/* UCSCTL7 Control Bits */ +#define DCOFFG (0x0001) /* DCO Fault Flag */ +#define XT1LFOFFG (0x0002) /* XT1 Low Frequency Oscillator Fault Flag */ +//#define RESERVED (0x0004) /* RESERVED */ +#define XT2OFFG (0x0008) /* High Frequency Oscillator 2 Fault Flag */ +//#define RESERVED (0x0010) /* RESERVED */ +//#define RESERVED (0x0020) /* RESERVED */ +//#define RESERVED (0x0040) /* RESERVED */ +//#define RESERVED (0x0080) /* RESERVED */ +//#define RESERVED (0x0100) /* RESERVED */ +//#define RESERVED (0x0200) /* RESERVED */ +//#define RESERVED (0x0400) /* RESERVED */ +//#define RESERVED (0x0800) /* RESERVED */ +//#define RESERVED (0x1000) /* RESERVED */ +//#define RESERVED (0x2000) /* RESERVED */ +//#define RESERVED (0x4000) /* RESERVED */ +//#define RESERVED (0x8000) /* RESERVED */ + +/* UCSCTL7 Control Bits */ +#define DCOFFG_L (0x0001) /* DCO Fault Flag */ +#define XT1LFOFFG_L (0x0002) /* XT1 Low Frequency Oscillator Fault Flag */ +//#define RESERVED (0x0004) /* RESERVED */ +#define XT2OFFG_L (0x0008) /* High Frequency Oscillator 2 Fault Flag */ +//#define RESERVED (0x0010) /* RESERVED */ +//#define RESERVED (0x0020) /* RESERVED */ +//#define RESERVED (0x0040) /* RESERVED */ +//#define RESERVED (0x0080) /* RESERVED */ +//#define RESERVED (0x0100) /* RESERVED */ +//#define RESERVED (0x0200) /* RESERVED */ +//#define RESERVED (0x0400) /* RESERVED */ +//#define RESERVED (0x0800) /* RESERVED */ +//#define RESERVED (0x1000) /* RESERVED */ +//#define RESERVED (0x2000) /* RESERVED */ +//#define RESERVED (0x4000) /* RESERVED */ +//#define RESERVED (0x8000) /* RESERVED */ + + + +/* UCSCTL8 Control Bits */ +#define ACLKREQEN (0x0001) /* ACLK Clock Request Enable */ +#define MCLKREQEN (0x0002) /* MCLK Clock Request Enable */ +#define SMCLKREQEN (0x0004) /* SMCLK Clock Request Enable */ +#define MODOSCREQEN (0x0008) /* MODOSC Clock Request Enable */ +//#define RESERVED (0x0010) /* RESERVED */ +//#define RESERVED (0x0020) /* RESERVED */ +//#define RESERVED (0x0040) /* RESERVED */ +//#define RESERVED (0x0080) /* RESERVED */ +//#define RESERVED (0x0100) /* RESERVED */ +//#define RESERVED (0x0200) /* RESERVED */ +//#define RESERVED (0x0400) /* RESERVED */ +//#define RESERVED (0x0800) /* RESERVED */ +//#define RESERVED (0x1000) /* RESERVED */ +//#define RESERVED (0x2000) /* RESERVED */ +//#define RESERVED (0x4000) /* RESERVED */ +//#define RESERVED (0x8000) /* RESERVED */ + +/* UCSCTL8 Control Bits */ +#define ACLKREQEN_L (0x0001) /* ACLK Clock Request Enable */ +#define MCLKREQEN_L (0x0002) /* MCLK Clock Request Enable */ +#define SMCLKREQEN_L (0x0004) /* SMCLK Clock Request Enable */ +#define MODOSCREQEN_L (0x0008) /* MODOSC Clock Request Enable */ +//#define RESERVED (0x0010) /* RESERVED */ +//#define RESERVED (0x0020) /* RESERVED */ +//#define RESERVED (0x0040) /* RESERVED */ +//#define RESERVED (0x0080) /* RESERVED */ +//#define RESERVED (0x0100) /* RESERVED */ +//#define RESERVED (0x0200) /* RESERVED */ +//#define RESERVED (0x0400) /* RESERVED */ +//#define RESERVED (0x0800) /* RESERVED */ +//#define RESERVED (0x1000) /* RESERVED */ +//#define RESERVED (0x2000) /* RESERVED */ +//#define RESERVED (0x4000) /* RESERVED */ +//#define RESERVED (0x8000) /* RESERVED */ + + +/************************************************************ +* USCI A0 +************************************************************/ + +#define UCA0CTLW0 0x05C0 /* USCI A0 Control Word Register 0 */ +#define UCA0CTL1 UCA0CTLW0_L /* USCI A0 Control Register 1 */ +#define UCA0CTL0 UCA0CTLW0_H /* USCI A0 Control Register 0 */ +#define UCA0BRW 0x05C6 /* USCI A0 Baud Word Rate 0 */ +#define UCA0BRW_L (UCA0BRW) +#define UCA0BRW_H (UCA0BRW+1) +#define UCA0BR0 UCA0BRW_L /* USCI A0 Baud Rate 0 */ +#define UCA0BR1 UCA0BRW_H /* USCI A0 Baud Rate 1 */ +#define UCA0MCTL 0x05C8 /* USCI A0 Modulation Control */ +#define UCA0STAT 0x05CA /* USCI A0 Status Register */ +#define UCA0RXBUF 0x05CC /* USCI A0 Receive Buffer */ +#define UCA0TXBUF 0x05CE /* USCI A0 Transmit Buffer */ +#define UCA0ABCTL 0x05D0 /* USCI A0 LIN Control */ +#define UCA0IRCTL 0x05D2 /* USCI A0 IrDA Transmit Control */ +#define UCA0IRTCTL UCA0IRCTL_L /* USCI A0 IrDA Transmit Control */ +#define UCA0IRRCTL UCA0IRCTL_H /* USCI A0 IrDA Receive Control */ +#define UCA0ICTL 0x05DC /* USCI A0 Interrupt Enable Register */ +#define UCA0IE UCA0ICTL_L /* USCI A0 Interrupt Enable Register */ +#define UCA0IFG UCA0ICTL_H /* USCI A0 Interrupt Flags Register */ +#define UCA0IV 0x05DE /* USCI A0 Interrupt Vector Register */ + + +/************************************************************ +* USCI B0 +************************************************************/ + +#define UCB0CTLW0 0x05E0 /* USCI B0 Control Word Register 0 */ +#define UCB0CTL1 UCB0CTLW0_L /* USCI B0 Control Register 1 */ +#define UCB0CTL0 UCB0CTLW0_H /* USCI B0 Control Register 0 */ +#define UCB0BRW 0x05E6 /* USCI B0 Baud Word Rate 0 */ +#define UCB0BR0 UCB0BRW_L /* USCI B0 Baud Rate 0 */ +#define UCB0BR1 UCB0BRW_H /* USCI B0 Baud Rate 1 */ +#define UCB0STAT 0x05EA /* USCI B0 Status Register */ +#define UCB0RXBUF 0x05EC /* USCI B0 Receive Buffer */ +#define UCB0TXBUF 0x05EE /* USCI B0 Transmit Buffer */ +#define UCB0I2COA 0x05F0 /* USCI B0 I2C Own Address */ +#define UCB0I2CSA 0x05F2 /* USCI B0 I2C Slave Address */ +#define UCB0ICTL 0x05FC /* USCI B0 Interrupt Enable Register */ +#define UCB0IE UCB0ICTL_L /* USCI B0 Interrupt Enable Register */ +#define UCB0IFG UCB0ICTL_H /* USCI B0 Interrupt Flags Register */ +#define UCB0IV 0x05FE /* USCI B0 Interrupt Vector Register */ + + +// UCAxCTL0 UART-Mode Control Bits +#define UCPEN (0x80) /* Async. Mode: Parity enable */ +#define UCPAR (0x40) /* Async. Mode: Parity 0:odd / 1:even */ +#define UCMSB (0x20) /* Async. Mode: MSB first 0:LSB / 1:MSB */ +#define UC7BIT (0x10) /* Async. Mode: Data Bits 0:8-bits / 1:7-bits */ +#define UCSPB (0x08) /* Async. Mode: Stop Bits 0:one / 1: two */ +#define UCMODE1 (0x04) /* Async. Mode: USCI Mode 1 */ +#define UCMODE0 (0x02) /* Async. Mode: USCI Mode 0 */ +#define UCSYNC (0x01) /* Sync-Mode 0:UART-Mode / 1:SPI-Mode */ + +// UCxxCTL0 SPI-Mode Control Bits +#define UCCKPH (0x80) /* Sync. Mode: Clock Phase */ +#define UCCKPL (0x40) /* Sync. Mode: Clock Polarity */ +#define UCMST (0x08) /* Sync. Mode: Master Select */ + +// UCBxCTL0 I2C-Mode Control Bits +#define UCA10 (0x80) /* 10-bit Address Mode */ +#define UCSLA10 (0x40) /* 10-bit Slave Address Mode */ +#define UCMM (0x20) /* Multi-Master Environment */ +//#define res (0x10) /* reserved */ +#define UCMODE_0 (0x00) /* Sync. Mode: USCI Mode: 0 */ +#define UCMODE_1 (0x02) /* Sync. Mode: USCI Mode: 1 */ +#define UCMODE_2 (0x04) /* Sync. Mode: USCI Mode: 2 */ +#define UCMODE_3 (0x06) /* Sync. Mode: USCI Mode: 3 */ + +// UCAxCTL1 UART-Mode Control Bits +#define UCSSEL1 (0x80) /* USCI 0 Clock Source Select 1 */ +#define UCSSEL0 (0x40) /* USCI 0 Clock Source Select 0 */ +#define UCRXEIE (0x20) /* RX Error interrupt enable */ +#define UCBRKIE (0x10) /* Break interrupt enable */ +#define UCDORM (0x08) /* Dormant (Sleep) Mode */ +#define UCTXADDR (0x04) /* Send next Data as Address */ +#define UCTXBRK (0x02) /* Send next Data as Break */ +#define UCSWRST (0x01) /* USCI Software Reset */ + +// UCxxCTL1 SPI-Mode Control Bits +//#define res (0x20) /* reserved */ +//#define res (0x10) /* reserved */ +//#define res (0x08) /* reserved */ +//#define res (0x04) /* reserved */ +//#define res (0x02) /* reserved */ + +// UCBxCTL1 I2C-Mode Control Bits +//#define res (0x20) /* reserved */ +#define UCTR (0x10) /* Transmit/Receive Select/Flag */ +#define UCTXNACK (0x08) /* Transmit NACK */ +#define UCTXSTP (0x04) /* Transmit STOP */ +#define UCTXSTT (0x02) /* Transmit START */ +#define UCSSEL_0 (0x00) /* USCI 0 Clock Source: 0 */ +#define UCSSEL_1 (0x40) /* USCI 0 Clock Source: 1 */ +#define UCSSEL_2 (0x80) /* USCI 0 Clock Source: 2 */ +#define UCSSEL_3 (0xC0) /* USCI 0 Clock Source: 3 */ +#define UCSSEL__UCLK (0x00) /* USCI 0 Clock Source: UCLK */ +#define UCSSEL__ACLK (0x40) /* USCI 0 Clock Source: ACLK */ +#define UCSSEL__SMCLK (0x80) /* USCI 0 Clock Source: SMCLK */ + +/* UCAxMCTL Control Bits */ +#define UCBRF3 (0x80) /* USCI First Stage Modulation Select 3 */ +#define UCBRF2 (0x40) /* USCI First Stage Modulation Select 2 */ +#define UCBRF1 (0x20) /* USCI First Stage Modulation Select 1 */ +#define UCBRF0 (0x10) /* USCI First Stage Modulation Select 0 */ +#define UCBRS2 (0x08) /* USCI Second Stage Modulation Select 2 */ +#define UCBRS1 (0x04) /* USCI Second Stage Modulation Select 1 */ +#define UCBRS0 (0x02) /* USCI Second Stage Modulation Select 0 */ +#define UCOS16 (0x01) /* USCI 16-times Oversampling enable */ + +#define UCBRF_0 (0x00) /* USCI First Stage Modulation: 0 */ +#define UCBRF_1 (0x10) /* USCI First Stage Modulation: 1 */ +#define UCBRF_2 (0x20) /* USCI First Stage Modulation: 2 */ +#define UCBRF_3 (0x30) /* USCI First Stage Modulation: 3 */ +#define UCBRF_4 (0x40) /* USCI First Stage Modulation: 4 */ +#define UCBRF_5 (0x50) /* USCI First Stage Modulation: 5 */ +#define UCBRF_6 (0x60) /* USCI First Stage Modulation: 6 */ +#define UCBRF_7 (0x70) /* USCI First Stage Modulation: 7 */ +#define UCBRF_8 (0x80) /* USCI First Stage Modulation: 8 */ +#define UCBRF_9 (0x90) /* USCI First Stage Modulation: 9 */ +#define UCBRF_10 (0xA0) /* USCI First Stage Modulation: A */ +#define UCBRF_11 (0xB0) /* USCI First Stage Modulation: B */ +#define UCBRF_12 (0xC0) /* USCI First Stage Modulation: C */ +#define UCBRF_13 (0xD0) /* USCI First Stage Modulation: D */ +#define UCBRF_14 (0xE0) /* USCI First Stage Modulation: E */ +#define UCBRF_15 (0xF0) /* USCI First Stage Modulation: F */ + +#define UCBRS_0 (0x00) /* USCI Second Stage Modulation: 0 */ +#define UCBRS_1 (0x02) /* USCI Second Stage Modulation: 1 */ +#define UCBRS_2 (0x04) /* USCI Second Stage Modulation: 2 */ +#define UCBRS_3 (0x06) /* USCI Second Stage Modulation: 3 */ +#define UCBRS_4 (0x08) /* USCI Second Stage Modulation: 4 */ +#define UCBRS_5 (0x0A) /* USCI Second Stage Modulation: 5 */ +#define UCBRS_6 (0x0C) /* USCI Second Stage Modulation: 6 */ +#define UCBRS_7 (0x0E) /* USCI Second Stage Modulation: 7 */ + +/* UCAxSTAT Control Bits */ +#define UCLISTEN (0x80) /* USCI Listen mode */ +#define UCFE (0x40) /* USCI Frame Error Flag */ +#define UCOE (0x20) /* USCI Overrun Error Flag */ +#define UCPE (0x10) /* USCI Parity Error Flag */ +#define UCBRK (0x08) /* USCI Break received */ +#define UCRXERR (0x04) /* USCI RX Error Flag */ +#define UCADDR (0x02) /* USCI Address received Flag */ +#define UCBUSY (0x01) /* USCI Busy Flag */ +#define UCIDLE (0x02) /* USCI Idle line detected Flag */ + + +/* UCBxSTAT Control Bits */ +#define UCSCLLOW (0x40) /* SCL low */ +#define UCGC (0x20) /* General Call address received Flag */ +#define UCBBUSY (0x10) /* Bus Busy Flag */ + +/* UCAxIRTCTL Control Bits */ +#define UCIRTXPL5 (0x80) /* IRDA Transmit Pulse Length 5 */ +#define UCIRTXPL4 (0x40) /* IRDA Transmit Pulse Length 4 */ +#define UCIRTXPL3 (0x20) /* IRDA Transmit Pulse Length 3 */ +#define UCIRTXPL2 (0x10) /* IRDA Transmit Pulse Length 2 */ +#define UCIRTXPL1 (0x08) /* IRDA Transmit Pulse Length 1 */ +#define UCIRTXPL0 (0x04) /* IRDA Transmit Pulse Length 0 */ +#define UCIRTXCLK (0x02) /* IRDA Transmit Pulse Clock Select */ +#define UCIREN (0x01) /* IRDA Encoder/Decoder enable */ + +/* UCAxIRRCTL Control Bits */ +#define UCIRRXFL5 (0x80) /* IRDA Receive Filter Length 5 */ +#define UCIRRXFL4 (0x40) /* IRDA Receive Filter Length 4 */ +#define UCIRRXFL3 (0x20) /* IRDA Receive Filter Length 3 */ +#define UCIRRXFL2 (0x10) /* IRDA Receive Filter Length 2 */ +#define UCIRRXFL1 (0x08) /* IRDA Receive Filter Length 1 */ +#define UCIRRXFL0 (0x04) /* IRDA Receive Filter Length 0 */ +#define UCIRRXPL (0x02) /* IRDA Receive Input Polarity */ +#define UCIRRXFE (0x01) /* IRDA Receive Filter enable */ + +/* UCAxABCTL Control Bits */ +//#define res (0x80) /* reserved */ +//#define res (0x40) /* reserved */ +#define UCDELIM1 (0x20) /* Break Sync Delimiter 1 */ +#define UCDELIM0 (0x10) /* Break Sync Delimiter 0 */ +#define UCSTOE (0x08) /* Sync-Field Timeout error */ +#define UCBTOE (0x04) /* Break Timeout error */ +//#define res (0x02) /* reserved */ +#define UCABDEN (0x01) /* Auto Baud Rate detect enable */ + +/* UCBxI2COA Control Bits */ +#define UCGCEN (0x8000) /* I2C General Call enable */ +#define UCOA9 (0x0200) /* I2C Own Address 9 */ +#define UCOA8 (0x0100) /* I2C Own Address 8 */ +#define UCOA7 (0x0080) /* I2C Own Address 7 */ +#define UCOA6 (0x0040) /* I2C Own Address 6 */ +#define UCOA5 (0x0020) /* I2C Own Address 5 */ +#define UCOA4 (0x0010) /* I2C Own Address 4 */ +#define UCOA3 (0x0008) /* I2C Own Address 3 */ +#define UCOA2 (0x0004) /* I2C Own Address 2 */ +#define UCOA1 (0x0002) /* I2C Own Address 1 */ +#define UCOA0 (0x0001) /* I2C Own Address 0 */ + +/* UCBxI2COA Control Bits */ +#define UCOA7_L (0x0080) /* I2C Own Address 7 */ +#define UCOA6_L (0x0040) /* I2C Own Address 6 */ +#define UCOA5_L (0x0020) /* I2C Own Address 5 */ +#define UCOA4_L (0x0010) /* I2C Own Address 4 */ +#define UCOA3_L (0x0008) /* I2C Own Address 3 */ +#define UCOA2_L (0x0004) /* I2C Own Address 2 */ +#define UCOA1_L (0x0002) /* I2C Own Address 1 */ +#define UCOA0_L (0x0001) /* I2C Own Address 0 */ + +/* UCBxI2COA Control Bits */ +#define UCGCEN_H (0x0080) /* I2C General Call enable */ +#define UCOA9_H (0x0002) /* I2C Own Address 9 */ +#define UCOA8_H (0x0001) /* I2C Own Address 8 */ + +/* UCBxI2CSA Control Bits */ +#define UCSA9 (0x0200) /* I2C Slave Address 9 */ +#define UCSA8 (0x0100) /* I2C Slave Address 8 */ +#define UCSA7 (0x0080) /* I2C Slave Address 7 */ +#define UCSA6 (0x0040) /* I2C Slave Address 6 */ +#define UCSA5 (0x0020) /* I2C Slave Address 5 */ +#define UCSA4 (0x0010) /* I2C Slave Address 4 */ +#define UCSA3 (0x0008) /* I2C Slave Address 3 */ +#define UCSA2 (0x0004) /* I2C Slave Address 2 */ +#define UCSA1 (0x0002) /* I2C Slave Address 1 */ +#define UCSA0 (0x0001) /* I2C Slave Address 0 */ + +/* UCBxI2CSA Control Bits */ +#define UCSA7_L (0x0080) /* I2C Slave Address 7 */ +#define UCSA6_L (0x0040) /* I2C Slave Address 6 */ +#define UCSA5_L (0x0020) /* I2C Slave Address 5 */ +#define UCSA4_L (0x0010) /* I2C Slave Address 4 */ +#define UCSA3_L (0x0008) /* I2C Slave Address 3 */ +#define UCSA2_L (0x0004) /* I2C Slave Address 2 */ +#define UCSA1_L (0x0002) /* I2C Slave Address 1 */ +#define UCSA0_L (0x0001) /* I2C Slave Address 0 */ + +/* UCBxI2CSA Control Bits */ +#define UCSA9_H (0x0002) /* I2C Slave Address 9 */ +#define UCSA8_H (0x0001) /* I2C Slave Address 8 */ + +/* UCAxIE Control Bits */ +#define UCTXIE (0x0002) /* USCI Transmit Interrupt Enable */ +#define UCRXIE (0x0001) /* USCI Receive Interrupt Enable */ + +/* UCBxIE Control Bits */ +#define UCNACKIE (0x0020) /* NACK Condition interrupt enable */ +#define UCALIE (0x0010) /* Arbitration Lost interrupt enable */ +#define UCSTPIE (0x0008) /* STOP Condition interrupt enable */ +#define UCSTTIE (0x0004) /* START Condition interrupt enable */ + +/* UCAxIFG Control Bits */ +#define UCTXIFG (0x0002) /* USCI Transmit Interrupt Flag */ +#define UCRXIFG (0x0001) /* USCI Receive Interrupt Flag */ + +/* UCBxIFG Control Bits */ +#define UCNACKIFG (0x0020) /* NAK Condition interrupt Flag */ +#define UCALIFG (0x0010) /* Arbitration Lost interrupt Flag */ +#define UCSTPIFG (0x0008) /* STOP Condition interrupt Flag */ +#define UCSTTIFG (0x0004) /* START Condition interrupt Flag */ + +/* USCI Definitions */ +#define USCI_NONE (0x0000) /* No Interrupt pending */ +#define USCI_UCRXIFG (0x0002) /* USCI UCRXIFG */ +#define USCI_UCTXIFG (0x0004) /* USCI UCTXIFG */ +#define USCI_I2C_UCALIFG (0x0002) /* USCI I2C Mode: UCALIFG */ +#define USCI_I2C_UCNACKIFG (0x0004) /* USCI I2C Mode: UCNACKIFG */ +#define USCI_I2C_UCSTTIFG (0x0006) /* USCI I2C Mode: UCSTTIFG*/ +#define USCI_I2C_UCSTPIFG (0x0008) /* USCI I2C Mode: UCSTPIFG*/ +#define USCI_I2C_UCRXIFG (0x000A) /* USCI I2C Mode: UCRXIFG */ +#define USCI_I2C_UCTXIFG (0x000C) /* USCI I2C Mode: UCTXIFG */ + +/************************************************************ +* USCI A1 +************************************************************/ + +#define UCA1CTLW0 0x0600 /* USCI A1 Control Word Register 0 */ +#define UCA1CTLW0_L (UCA1CTLW0) +#define UCA1CTLW0_H (UCA1CTLW0+1) +#define UCA1CTL1 UCA1CTLW0_L /* USCI A1 Control Register 1 */ +#define UCA1CTL0 UCA1CTLW0_H /* USCI A1 Control Register 0 */ +#define UCA1BRW 0x0606 /* USCI A1 Baud Word Rate 0 */ +#define UCA1BRW_L (UCA1BRW) +#define UCA1BRW_H (UCA1BRW+1) +#define UCA1BR0 UCA1BRW_L /* USCI A1 Baud Rate 0 */ +#define UCA1BR1 UCA1BRW_H /* USCI A1 Baud Rate 1 */ +#define UCA1MCTL 0x0608 /* USCI A1 Modulation Control */ +#define UCA1STAT 0x060A /* USCI A1 Status Register */ +#define UCA1RXBUF 0x060C /* USCI A1 Receive Buffer */ +#define UCA1TXBUF 0x060E /* USCI A1 Transmit Buffer */ +#define UCA1ABCTL 0x0610 /* USCI A1 LIN Control */ +#define UCA1IRCTL 0x0612 /* USCI A1 IrDA Transmit Control */ +#define UCA1IRTCTL UCA1IRCTL_L /* USCI A1 IrDA Transmit Control */ +#define UCA1IRRCTL UCA1IRCTL_H /* USCI A1 IrDA Receive Control */ +#define UCA1ICTL 0x061C /* USCI A1 Interrupt Enable Register */ +#define UCA1ICTL_L (UCA1ICTL) +#define UCA1ICTL_H (UCA1ICTL+1) + +#define UCA1IE UCA1ICTL_L /* USCI A1 Interrupt Enable Register */ +#define UCA1IFG UCA1ICTL_H /* USCI A1 Interrupt Flags Register */ +#define UCA1IV 0x061E /* USCI A1 Interrupt Vector Register */ + + +/************************************************************ +* USCI B1 +************************************************************/ + +#define UCB1CTLW0 0x0620 /* USCI B1 Control Word Register 0 */ +#define UCB1CTL1 UCB1CTLW0_L /* USCI B1 Control Register 1 */ +#define UCB1CTL0 UCB1CTLW0_H /* USCI B1 Control Register 0 */ +#define UCB1BRW 0x0626 /* USCI B1 Baud Word Rate 0 */ +#define UCB1BR0 UCB1BRW_L /* USCI B1 Baud Rate 0 */ +#define UCB1BR1 UCB1BRW_H /* USCI B1 Baud Rate 1 */ +#define UCB1STAT 0x062A /* USCI B1 Status Register */ +#define UCB1RXBUF 0x062C /* USCI B1 Receive Buffer */ +#define UCB1TXBUF 0x062E /* USCI B1 Transmit Buffer */ +#define UCB1I2COA 0x0630 /* USCI B1 I2C Own Address */ +#define UCB1I2CSA 0x0632 /* USCI B1 I2C Slave Address */ +#define UCB1ICTL 0x063C /* USCI B1 Interrupt Enable Register */ +#define UCB1IE UCB1ICTL_L /* USCI B1 Interrupt Enable Register */ +#define UCB1IFG UCB1ICTL_H /* USCI B1 Interrupt Flags Register */ +#define UCB1IV 0x063E /* USCI B1 Interrupt Vector Register */ + +/************************************************************ +* WATCHDOG TIMER A +************************************************************/ +#define WDTCTL 0x015C /* Watchdog Timer Control */ +/* The bit names have been prefixed with "WDT" */ +/* WDTCTL Control Bits */ +#define WDTIS0 (0x0001) /* WDT - Timer Interval Select 0 */ +#define WDTIS1 (0x0002) /* WDT - Timer Interval Select 1 */ +#define WDTIS2 (0x0004) /* WDT - Timer Interval Select 2 */ +#define WDTCNTCL (0x0008) /* WDT - Timer Clear */ +#define WDTTMSEL (0x0010) /* WDT - Timer Mode Select */ +#define WDTSSEL0 (0x0020) /* WDT - Timer Clock Source Select 0 */ +#define WDTSSEL1 (0x0040) /* WDT - Timer Clock Source Select 1 */ +#define WDTHOLD (0x0080) /* WDT - Timer hold */ + +/* WDTCTL Control Bits */ +#define WDTIS0_L (0x0001) /* WDT - Timer Interval Select 0 */ +#define WDTIS1_L (0x0002) /* WDT - Timer Interval Select 1 */ +#define WDTIS2_L (0x0004) /* WDT - Timer Interval Select 2 */ +#define WDTCNTCL_L (0x0008) /* WDT - Timer Clear */ +#define WDTTMSEL_L (0x0010) /* WDT - Timer Mode Select */ +#define WDTSSEL0_L (0x0020) /* WDT - Timer Clock Source Select 0 */ +#define WDTSSEL1_L (0x0040) /* WDT - Timer Clock Source Select 1 */ +#define WDTHOLD_L (0x0080) /* WDT - Timer hold */ + + +#define WDTPW (0x5A00) + +#define WDTIS_0 (0x0000) /* WDT - Timer Interval Select: /2G */ +#define WDTIS_1 (0x0001) /* WDT - Timer Interval Select: /128M */ +#define WDTIS_2 (0x0002) /* WDT - Timer Interval Select: /8192k */ +#define WDTIS_3 (0x0003) /* WDT - Timer Interval Select: /512k */ +#define WDTIS_4 (0x0004) /* WDT - Timer Interval Select: /32k */ +#define WDTIS_5 (0x0005) /* WDT - Timer Interval Select: /8192 */ +#define WDTIS_6 (0x0006) /* WDT - Timer Interval Select: /512 */ +#define WDTIS_7 (0x0007) /* WDT - Timer Interval Select: /64 */ +#define WDTIS__2G (0x0000) /* WDT - Timer Interval Select: /2G */ +#define WDTIS__128M (0x0001) /* WDT - Timer Interval Select: /128M */ +#define WDTIS__8192K (0x0002) /* WDT - Timer Interval Select: /8192k */ +#define WDTIS__512K (0x0003) /* WDT - Timer Interval Select: /512k */ +#define WDTIS__32K (0x0004) /* WDT - Timer Interval Select: /32k */ +#define WDTIS__8192 (0x0005) /* WDT - Timer Interval Select: /8192 */ +#define WDTIS__512 (0x0006) /* WDT - Timer Interval Select: /512 */ +#define WDTIS__64 (0x0007) /* WDT - Timer Interval Select: /64 */ + +#define WDTSSEL_0 (0x0000) /* WDT - Timer Clock Source Select: SMCLK */ +#define WDTSSEL_1 (0x0020) /* WDT - Timer Clock Source Select: ACLK */ +#define WDTSSEL_2 (0x0040) /* WDT - Timer Clock Source Select: VLO_CLK */ +#define WDTSSEL_3 (0x0060) /* WDT - Timer Clock Source Select: reserved */ +#define WDTSSEL__SMCLK (0x0000) /* WDT - Timer Clock Source Select: SMCLK */ +#define WDTSSEL__ACLK (0x0020) /* WDT - Timer Clock Source Select: ACLK */ +#define WDTSSEL__VLO (0x0040) /* WDT - Timer Clock Source Select: VLO_CLK */ + + +/* WDT-interval times [1ms] coded with Bits 0-2 */ +/* WDT is clocked by fSMCLK (assumed 1MHz) */ +#define WDT_MDLY_32 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2) /* 32ms interval (default) */ +#define WDT_MDLY_8 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTIS0) /* 8ms " */ +#define WDT_MDLY_0_5 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTIS1) /* 0.5ms " */ +#define WDT_MDLY_0_064 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTIS1+WDTIS0) /* 0.064ms " */ +/* WDT is clocked by fACLK (assumed 32KHz) */ +#define WDT_ADLY_1000 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0) /* 1000ms " */ +#define WDT_ADLY_250 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0+WDTIS0) /* 250ms " */ +#define WDT_ADLY_16 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0+WDTIS1) /* 16ms " */ +#define WDT_ADLY_1_9 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0+WDTIS1+WDTIS0) /* 1.9ms " */ +/* Watchdog mode -> reset after expired time */ +/* WDT is clocked by fSMCLK (assumed 1MHz) */ +#define WDT_MRST_32 (WDTPW+WDTCNTCL+WDTIS2) /* 32ms interval (default) */ +#define WDT_MRST_8 (WDTPW+WDTCNTCL+WDTIS2+WDTIS0) /* 8ms " */ +#define WDT_MRST_0_5 (WDTPW+WDTCNTCL+WDTIS2+WDTIS1) /* 0.5ms " */ +#define WDT_MRST_0_064 (WDTPW+WDTCNTCL+WDTIS2+WDTIS1+WDTIS0) /* 0.064ms " */ +/* WDT is clocked by fACLK (assumed 32KHz) */ +#define WDT_ARST_1000 (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2) /* 1000ms " */ +#define WDT_ARST_250 (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2+WDTIS0) /* 250ms " */ +#define WDT_ARST_16 (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2+WDTIS1) /* 16ms " */ +#define WDT_ARST_1_9 (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2+WDTIS1+WDTIS0) /* 1.9ms " */ + + +/************************************************************ +* TLV Descriptors +************************************************************/ + +#define TLV_CRC_LENGTH (0x1A01) /* CRC length of the TLV structure */ +#define TLV_CRC_VALUE (0x1A02) /* CRC value of the TLV structure */ +#define TLV_START (0x1A08) /* Start Address of the TLV structure */ +#define TLV_END (0x1AFF) /* End Address of the TLV structure */ + +#define TLV_LDTAG (0x01) /* Legacy descriptor (1xx, 2xx, 4xx families) */ +#define TLV_PDTAG (0x02) /* Peripheral discovery descriptor */ +#define TLV_Reserved3 (0x03) /* Future usage */ +#define TLV_Reserved4 (0x04) /* Future usage */ +#define TLV_BLANK (0x05) /* Blank descriptor */ +#define TLV_Reserved6 (0x06) /* Future usage */ +#define TLV_Reserved7 (0x07) /* Serial Number */ +#define TLV_DIERECORD (0x08) /* Die Record */ +#define TLV_ADCCAL (0x11) /* ADC12 calibration */ +#define TLV_ADC12CAL (0x11) /* ADC12 calibration */ +#define TLV_ADC10CAL (0x13) /* ADC10 calibration */ +#define TLV_REFCAL (0x12) /* REF calibration */ +#define TLV_TAGEXT (0xFE) /* Tag extender */ +#define TLV_TAGEND (0xFF) // Tag End of Table + + +/************************************************************ +* Interrupt Vectors (offset from 0xFF80) +************************************************************/ + + +#define RTC_VECTOR (42) /* 0xFFD2 RTC */ +#define PORT2_VECTOR (43) /* 0xFFD4 Port 2 */ +#define TIMER2_A1_VECTOR (44) /* 0xFFD6 Timer2_A5 CC1-4, TA */ +#define TIMER2_A0_VECTOR (45) /* 0xFFD8 Timer2_A5 CC0 */ +#define USCI_B1_VECTOR (46) /* 0xFFDA USCI B1 Receive/Transmit */ +#define USCI_A1_VECTOR (47) /* 0xFFDC USCI A1 Receive/Transmit */ +#define PORT1_VECTOR (48) /* 0xFFDE Port 1 */ +#define TIMER1_A1_VECTOR (49) /* 0xFFE0 Timer1_A3 CC1-2, TA1 */ +#define TIMER1_A0_VECTOR (50) /* 0xFFE2 Timer1_A3 CC0 */ +#define DMA_VECTOR (51) /* 0xFFE4 DMA */ +#define USB_UBM_VECTOR (52) /* 0xFFE6 USB Timer / cable event / USB reset */ +#define TIMER0_A1_VECTOR (53) /* 0xFFE8 Timer0_A5 CC1-4, TA */ +#define TIMER0_A0_VECTOR (54) /* 0xFFEA Timer0_A5 CC0 */ +#define ADC12_VECTOR (55) /* 0xFFEC ADC */ +#define USCI_B0_VECTOR (56) /* 0xFFEE USCI B0 Receive/Transmit */ +#define USCI_A0_VECTOR (57) /* 0xFFF0 USCI A0 Receive/Transmit */ +#define WDT_VECTOR (58) /* 0xFFF2 Watchdog Timer */ +#define TIMER0_B1_VECTOR (59) /* 0xFFF4 Timer0_B7 CC1-6, TB */ +#define TIMER0_B0_VECTOR (60) /* 0xFFF6 Timer0_B7 CC0 */ +#define COMP_B_VECTOR (61) /* 0xFFF8 Comparator B */ +#define UNMI_VECTOR (62) /* 0xFFFA User Non-maskable */ +#define SYSNMI_VECTOR (63) /* 0xFFFC System Non-maskable */ +#define RESET_VECTOR ("reset") /* 0xFFFE Reset [Highest Priority] */ + +/************************************************************ +* End of Modules +************************************************************/ + diff --git a/amforth-6.5/msp430/devices/msp430f5529/words/cold.asm b/amforth-6.5/msp430/devices/msp430f5529/words/cold.asm new file mode 100644 index 0000000..b16f18f --- /dev/null +++ b/amforth-6.5/msp430/devices/msp430f5529/words/cold.asm @@ -0,0 +1,41 @@ +CODEHEADER(XT_COLD, 4, "cold") +; ---------------------------------------------------------------------- + +main: ; Debugger requires the 'main' symbol. +reset: + + mov #5A80h, &WDTCTL ; Watchdog off + + ; Now it is time to initialize hardware. (Porting: Change this !) + + ;------------------------------------------------------------------------------ + ; Init Clock + + bis.w #40h, r2 + mov.w #20h, &166h + mov.w #144h, &168h + mov.w #1308h, &160h + mov.w #40h, &162h + mov.w #0F4h, &164h + nop + nop + nop + bic.w #40h, r2 + +reset_loop: + mov.w #0h, &16Eh + bic.w #2h, &102h + bit.w #2h, &102h + jc reset_loop + + ;------------------------------------------------------------------------------ + +; Forth registers + MOV #RSTACK,SP ; set up stack + MOV #PSTACK,PSP + MOV #UAREA,UP ; initial user pointer + CLR R15 + +; now hand over to Forth with WARM (a colon word) + MOV #XT_WARM+2,IP + NEXT diff --git a/amforth-6.5/msp430/devices/msp430f5529/words/env-mcu-info.asm b/amforth-6.5/msp430/devices/msp430f5529/words/env-mcu-info.asm new file mode 100644 index 0000000..621fc72 --- /dev/null +++ b/amforth-6.5/msp430/devices/msp430f5529/words/env-mcu-info.asm @@ -0,0 +1,10 @@ +ENVIRONMENT(XT_ENV_MCU_INFO,8,"mcu-info") + .DW XT_DOLITERAL + .dw mcuinfo + .DW XT_EXIT +mcuinfo: + ; first fixed sized elements + .dw RAMEND-RAMSTART ; RAM Size + .dw 0 ; EEPROM Size + .dw AMFORTH_START-1 ; max-dp + .dw 1 ; number of interrupts diff --git a/amforth-6.5/msp430/devices/msp430f5529/words/usart-init.asm b/amforth-6.5/msp430/devices/msp430f5529/words/usart-init.asm new file mode 100644 index 0000000..4bcd00c --- /dev/null +++ b/amforth-6.5/msp430/devices/msp430f5529/words/usart-init.asm @@ -0,0 +1,16 @@ + CODEHEADER(XT_USART,6,"+usart") + ; USCI_A0 + mov.b #030h, &P4SEL ; Use P4.4/P4.5 for USCI_A1 TXD/RXD + + ;------------------------------------------------------------------------------ + ; Init serial communication + + mov.b #UCSWRST, &UCA1CTL1 ; **Put state machine in reset** + bis.b #UCSSEL_2, &UCA1CTL1 ; SMCLK + + mov.w #4, &UCA1BRW ; 8 MHz 115200 Baud + mov.b #3Bh, &UCA1MCTL ; Modulation UCBRSx=5, UCBRFx=3, UCOS16 + + bic.b #UCSWRST, &UCA1CTL1 ; **Initialize USCI state machine** + + NEXT diff --git a/amforth-6.5/msp430/devices/msp430fr5969/device.asm b/amforth-6.5/msp430/devices/msp430fr5969/device.asm new file mode 100644 index 0000000..45c9b5e --- /dev/null +++ b/amforth-6.5/msp430/devices/msp430fr5969/device.asm @@ -0,0 +1,16 @@ +; device specific +.include "msp430fr5969.inc" ; MCU-specific register equates + +RAMSTART equ 1C00h +RAMEND equ 2400h +INFOSTART equ 01800h ; INFO D Area +INFOEND equ 0197fh ; do not allow config flash to be erased +FLASHSTART equ 4400h +FLASHEND equ 0FFFFh +MAINSEG equ 512 +INFOSEG equ 64 +INFO_SIZE equ 128 ; bytes + +.org 0FFFEh + + DC16 reset ; FFFE - Reset diff --git a/amforth-6.5/msp430/devices/msp430fr5969/drivers.asm b/amforth-6.5/msp430/devices/msp430fr5969/drivers.asm new file mode 100644 index 0000000..fbdf81a --- /dev/null +++ b/amforth-6.5/msp430/devices/msp430fr5969/drivers.asm @@ -0,0 +1,3 @@ + +.include "drivers/fram.inc" + diff --git a/amforth-6.5/msp430/devices/msp430fr5969/init.asm b/amforth-6.5/msp430/devices/msp430fr5969/init.asm new file mode 100644 index 0000000..32451c5 --- /dev/null +++ b/amforth-6.5/msp430/devices/msp430fr5969/init.asm @@ -0,0 +1,4 @@ + +mcu_name: + .db 12,"MSP430FR5969" + .align 16 diff --git a/amforth-6.5/msp430/devices/msp430fr5969/msp430fr5969.inc b/amforth-6.5/msp430/devices/msp430fr5969/msp430fr5969.inc new file mode 100644 index 0000000..116f915 --- /dev/null +++ b/amforth-6.5/msp430/devices/msp430fr5969/msp430fr5969.inc @@ -0,0 +1,3908 @@ +/* ============================================================================ */ +/* Copyright (c) 2015, Texas Instruments Incorporated */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following conditions */ +/* are met: */ +/* */ +/* * Redistributions of source code must retain the above copyright */ +/* notice, this list of conditions and the following disclaimer. */ +/* */ +/* * Redistributions in binary form must reproduce the above copyright */ +/* notice, this list of conditions and the following disclaimer in the */ +/* documentation and/or other materials provided with the distribution. */ +/* */ +/* * Neither the name of Texas Instruments Incorporated nor the names of */ +/* its contributors may be used to endorse or promote products derived */ +/* from this software without specific prior written permission. */ +/* */ +/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" */ +/* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, */ +/* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR */ +/* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR */ +/* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, */ +/* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, */ +/* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; */ +/* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, */ +/* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR */ +/* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ============================================================================ */ + +/******************************************************************** +* +* Standard register and bit definitions for the Texas Instruments +* MSP430 microcontroller. +* +* This file supports assembler and C development for +* MSP430FR5969 devices. +* +* Texas Instruments, Version 1.4 +* +* Rev. 1.0, Setup +* Rev. 1.1 updated PxSELC register address to offset 0x16 (instead of 0x10) +* replaced Comperator B with Comperator E +* Rev. 1.2 fixed typo in SYSRSTIV_MPUSEG defintions +* replaced COMP_B with COMP_E +* Rev. 1.3 removed not available PxDS Register definitions +* Rev. 1.4 replaced NACCESSx with NWAITSx +* +********************************************************************/ + +/************************************************************ +* STANDARD BITS +************************************************************/ + +#define BIT0 (0x0001) +#define BIT1 (0x0002) +#define BIT2 (0x0004) +#define BIT3 (0x0008) +#define BIT4 (0x0010) +#define BIT5 (0x0020) +#define BIT6 (0x0040) +#define BIT7 (0x0080) +#define BIT8 (0x0100) +#define BIT9 (0x0200) +#define BITA (0x0400) +#define BITB (0x0800) +#define BITC (0x1000) +#define BITD (0x2000) +#define BITE (0x4000) +#define BITF (0x8000) + +/************************************************************ +* STATUS REGISTER BITS +************************************************************/ + +#define C (0x0001) +#define Z (0x0002) +#define N (0x0004) +#define V (0x0100) +#define GIE (0x0008) +#define CPUOFF (0x0010) +#define OSCOFF (0x0020) +#define SCG0 (0x0040) +#define SCG1 (0x0080) + +/* Low Power Modes coded with Bits 4-7 in SR */ + +#ifndef __STDC_ /* Begin #defines for assembler */ +#define LPM0 (CPUOFF) +#define LPM1 (SCG0+CPUOFF) +#define LPM2 (SCG1+CPUOFF) +#define LPM3 (SCG1+SCG0+CPUOFF) +#define LPM4 (SCG1+SCG0+OSCOFF+CPUOFF) +/* End #defines for assembler */ + +#else /* Begin #defines for C */ +#define LPM0_bits (CPUOFF) +#define LPM1_bits (SCG0+CPUOFF) +#define LPM2_bits (SCG1+CPUOFF) +#define LPM3_bits (SCG1+SCG0+CPUOFF) +#define LPM4_bits (SCG1+SCG0+OSCOFF+CPUOFF) + +#include "in430.h" + +#define LPM0 __bis_SR_register(LPM0_bits) /* Enter Low Power Mode 0 */ +#define LPM0_EXIT __bic_SR_register_on_exit(LPM0_bits) /* Exit Low Power Mode 0 */ +#define LPM1 __bis_SR_register(LPM1_bits) /* Enter Low Power Mode 1 */ +#define LPM1_EXIT __bic_SR_register_on_exit(LPM1_bits) /* Exit Low Power Mode 1 */ +#define LPM2 __bis_SR_register(LPM2_bits) /* Enter Low Power Mode 2 */ +#define LPM2_EXIT __bic_SR_register_on_exit(LPM2_bits) /* Exit Low Power Mode 2 */ +#define LPM3 __bis_SR_register(LPM3_bits) /* Enter Low Power Mode 3 */ +#define LPM3_EXIT __bic_SR_register_on_exit(LPM3_bits) /* Exit Low Power Mode 3 */ +#define LPM4 __bis_SR_register(LPM4_bits) /* Enter Low Power Mode 4 */ +#define LPM4_EXIT __bic_SR_register_on_exit(LPM4_bits) /* Exit Low Power Mode 4 */ +#endif /* End #defines for C */ + +/************************************************************ +* CPU +************************************************************/ + +/************************************************************ +* PERIPHERAL FILE MAP +************************************************************/ + + +/************************************************************ +* ADC12_B +************************************************************/ + +#define ADC12CTL0 0x0800 /* ADC12 B Control 0 */ +#define ADC12CTL1 0x0802 /* ADC12 B Control 1 */ +#define ADC12CTL2 0x0804 /* ADC12 B Control 2 */ +#define ADC12CTL3 0x0806 /* ADC12 B Control 3 */ +#define ADC12LO 0x0808 /* ADC12 B Window Comparator High Threshold */ +#define ADC12HI 0x080A /* ADC12 B Window Comparator High Threshold */ +#define ADC12IFGR0 0x080C /* ADC12 B Interrupt Flag 0 */ +#define ADC12IFGR1 0x080E /* ADC12 B Interrupt Flag 1 */ +#define ADC12IFGR2 0x0810 /* ADC12 B Interrupt Flag 2 */ +#define ADC12IER0 0x0812 /* ADC12 B Interrupt Enable 0 */ +#define ADC12IER1 0x0814 /* ADC12 B Interrupt Enable 1 */ +#define ADC12IER2 0x0816 /* ADC12 B Interrupt Enable 2 */ +#define ADC12IV 0x0818 /* ADC12 B Interrupt Vector Word */ + +#define ADC12MCTL0 0x0820 /* ADC12 Memory Control 0 */ +#define ADC12MCTL1 0x0822 /* ADC12 Memory Control 1 */ +#define ADC12MCTL2 0x0824 /* ADC12 Memory Control 2 */ +#define ADC12MCTL3 0x0826 /* ADC12 Memory Control 3 */ +#define ADC12MCTL4 0x0828 /* ADC12 Memory Control 4 */ +#define ADC12MCTL5 0x082A /* ADC12 Memory Control 5 */ +#define ADC12MCTL6 0x082C /* ADC12 Memory Control 6 */ +#define ADC12MCTL7 0x082E /* ADC12 Memory Control 7 */ +#define ADC12MCTL8 0x0830 /* ADC12 Memory Control 8 */ +#define ADC12MCTL9 0x0832 /* ADC12 Memory Control 9 */ +#define ADC12MCTL10 0x0834 /* ADC12 Memory Control 10 */ +#define ADC12MCTL11 0x0836 /* ADC12 Memory Control 11 */ +#define ADC12MCTL12 0x0838 /* ADC12 Memory Control 12 */ +#define ADC12MCTL13 0x083A /* ADC12 Memory Control 13 */ +#define ADC12MCTL14 0x083C /* ADC12 Memory Control 14 */ +#define ADC12MCTL15 0x083E /* ADC12 Memory Control 15 */ +#define ADC12MCTL16 0x0840 /* ADC12 Memory Control 16 */ +#define ADC12MCTL17 0x0842 /* ADC12 Memory Control 17 */ +#define ADC12MCTL18 0x0844 /* ADC12 Memory Control 18 */ +#define ADC12MCTL19 0x0846 /* ADC12 Memory Control 19 */ +#define ADC12MCTL20 0x0848 /* ADC12 Memory Control 20 */ +#define ADC12MCTL21 0x084A /* ADC12 Memory Control 21 */ +#define ADC12MCTL22 0x084C /* ADC12 Memory Control 22 */ +#define ADC12MCTL23 0x084E /* ADC12 Memory Control 23 */ +#define ADC12MCTL24 0x0850 /* ADC12 Memory Control 24 */ +#define ADC12MCTL25 0x0852 /* ADC12 Memory Control 25 */ +#define ADC12MCTL26 0x0854 /* ADC12 Memory Control 26 */ +#define ADC12MCTL27 0x0856 /* ADC12 Memory Control 27 */ +#define ADC12MCTL28 0x0858 /* ADC12 Memory Control 28 */ +#define ADC12MCTL29 0x085A /* ADC12 Memory Control 29 */ +#define ADC12MCTL30 0x085C /* ADC12 Memory Control 30 */ +#define ADC12MCTL31 0x085E /* ADC12 Memory Control 31 */ +#define ADC12MCTL ADC12MCTL0 /* ADC12 Memory Control (for assembler) */ + + +#define ADC12MEM0 0x0860 /* ADC12 Conversion Memory 0 */ +#define ADC12MEM1 0x0862 /* ADC12 Conversion Memory 1 */ +#define ADC12MEM2 0x0864 /* ADC12 Conversion Memory 2 */ +#define ADC12MEM3 0x0866 /* ADC12 Conversion Memory 3 */ +#define ADC12MEM4 0x0868 /* ADC12 Conversion Memory 4 */ +#define ADC12MEM5 0x086A /* ADC12 Conversion Memory 5 */ +#define ADC12MEM6 0x086C /* ADC12 Conversion Memory 6 */ +#define ADC12MEM7 0x086E /* ADC12 Conversion Memory 7 */ +#define ADC12MEM8 0x0870 /* ADC12 Conversion Memory 8 */ +#define ADC12MEM9 0x0872 /* ADC12 Conversion Memory 9 */ +#define ADC12MEM10 0x0874 /* ADC12 Conversion Memory 10 */ +#define ADC12MEM11 0x0876 /* ADC12 Conversion Memory 11 */ +#define ADC12MEM12 0x0878 /* ADC12 Conversion Memory 12 */ +#define ADC12MEM13 0x087A /* ADC12 Conversion Memory 13 */ +#define ADC12MEM14 0x087C /* ADC12 Conversion Memory 14 */ +#define ADC12MEM15 0x087E /* ADC12 Conversion Memory 15 */ +#define ADC12MEM16 0x0880 /* ADC12 Conversion Memory 16 */ +#define ADC12MEM17 0x0882 /* ADC12 Conversion Memory 17 */ +#define ADC12MEM18 0x0884 /* ADC12 Conversion Memory 18 */ +#define ADC12MEM19 0x0886 /* ADC12 Conversion Memory 19 */ +#define ADC12MEM20 0x0888 /* ADC12 Conversion Memory 20 */ +#define ADC12MEM21 0x088A /* ADC12 Conversion Memory 21 */ +#define ADC12MEM22 0x088C /* ADC12 Conversion Memory 22 */ +#define ADC12MEM23 0x088E /* ADC12 Conversion Memory 23 */ +#define ADC12MEM24 0x0890 /* ADC12 Conversion Memory 24 */ +#define ADC12MEM25 0x0892 /* ADC12 Conversion Memory 25 */ +#define ADC12MEM26 0x0894 /* ADC12 Conversion Memory 26 */ +#define ADC12MEM27 0x0896 /* ADC12 Conversion Memory 27 */ +#define ADC12MEM28 0x0898 /* ADC12 Conversion Memory 28 */ +#define ADC12MEM29 0x089A /* ADC12 Conversion Memory 29 */ +#define ADC12MEM30 0x089C /* ADC12 Conversion Memory 30 */ +#define ADC12MEM31 0x089E /* ADC12 Conversion Memory 31 */ +#define ADC12MEM ADC12MEM0 /* ADC12 Conversion Memory (for assembler) */ + +/* ADC12CTL0 Control Bits */ +#define ADC12SC (0x0001) /* ADC12 Start Conversion */ +#define ADC12ENC (0x0002) /* ADC12 Enable Conversion */ +#define ADC12ON (0x0010) /* ADC12 On/enable */ +#define ADC12MSC (0x0080) /* ADC12 Multiple SampleConversion */ +#define ADC12SHT00 (0x0100) /* ADC12 Sample Hold 0 Select Bit: 0 */ +#define ADC12SHT01 (0x0200) /* ADC12 Sample Hold 0 Select Bit: 1 */ +#define ADC12SHT02 (0x0400) /* ADC12 Sample Hold 0 Select Bit: 2 */ +#define ADC12SHT03 (0x0800) /* ADC12 Sample Hold 0 Select Bit: 3 */ +#define ADC12SHT10 (0x1000) /* ADC12 Sample Hold 1 Select Bit: 0 */ +#define ADC12SHT11 (0x2000) /* ADC12 Sample Hold 1 Select Bit: 1 */ +#define ADC12SHT12 (0x4000) /* ADC12 Sample Hold 1 Select Bit: 2 */ +#define ADC12SHT13 (0x8000) /* ADC12 Sample Hold 1 Select Bit: 3 */ + +/* ADC12CTL0 Control Bits */ +#define ADC12SC_L (0x0001) /* ADC12 Start Conversion */ +#define ADC12ENC_L (0x0002) /* ADC12 Enable Conversion */ +#define ADC12ON_L (0x0010) /* ADC12 On/enable */ +#define ADC12MSC_L (0x0080) /* ADC12 Multiple SampleConversion */ + +/* ADC12CTL0 Control Bits */ +#define ADC12SHT00_H (0x0001) /* ADC12 Sample Hold 0 Select Bit: 0 */ +#define ADC12SHT01_H (0x0002) /* ADC12 Sample Hold 0 Select Bit: 1 */ +#define ADC12SHT02_H (0x0004) /* ADC12 Sample Hold 0 Select Bit: 2 */ +#define ADC12SHT03_H (0x0008) /* ADC12 Sample Hold 0 Select Bit: 3 */ +#define ADC12SHT10_H (0x0010) /* ADC12 Sample Hold 1 Select Bit: 0 */ +#define ADC12SHT11_H (0x0020) /* ADC12 Sample Hold 1 Select Bit: 1 */ +#define ADC12SHT12_H (0x0040) /* ADC12 Sample Hold 1 Select Bit: 2 */ +#define ADC12SHT13_H (0x0080) /* ADC12 Sample Hold 1 Select Bit: 3 */ + +#define ADC12SHT0_0 (0x0000) /* ADC12 Sample Hold 0 Select Bit: 0 */ +#define ADC12SHT0_1 (0x0100) /* ADC12 Sample Hold 0 Select Bit: 1 */ +#define ADC12SHT0_2 (0x0200) /* ADC12 Sample Hold 0 Select Bit: 2 */ +#define ADC12SHT0_3 (0x0300) /* ADC12 Sample Hold 0 Select Bit: 3 */ +#define ADC12SHT0_4 (0x0400) /* ADC12 Sample Hold 0 Select Bit: 4 */ +#define ADC12SHT0_5 (0x0500) /* ADC12 Sample Hold 0 Select Bit: 5 */ +#define ADC12SHT0_6 (0x0600) /* ADC12 Sample Hold 0 Select Bit: 6 */ +#define ADC12SHT0_7 (0x0700) /* ADC12 Sample Hold 0 Select Bit: 7 */ +#define ADC12SHT0_8 (0x0800) /* ADC12 Sample Hold 0 Select Bit: 8 */ +#define ADC12SHT0_9 (0x0900) /* ADC12 Sample Hold 0 Select Bit: 9 */ +#define ADC12SHT0_10 (0x0A00) /* ADC12 Sample Hold 0 Select Bit: 10 */ +#define ADC12SHT0_11 (0x0B00) /* ADC12 Sample Hold 0 Select Bit: 11 */ +#define ADC12SHT0_12 (0x0C00) /* ADC12 Sample Hold 0 Select Bit: 12 */ +#define ADC12SHT0_13 (0x0D00) /* ADC12 Sample Hold 0 Select Bit: 13 */ +#define ADC12SHT0_14 (0x0E00) /* ADC12 Sample Hold 0 Select Bit: 14 */ +#define ADC12SHT0_15 (0x0F00) /* ADC12 Sample Hold 0 Select Bit: 15 */ + +#define ADC12SHT1_0 (0x0000) /* ADC12 Sample Hold 1 Select Bit: 0 */ +#define ADC12SHT1_1 (0x1000) /* ADC12 Sample Hold 1 Select Bit: 1 */ +#define ADC12SHT1_2 (0x2000) /* ADC12 Sample Hold 1 Select Bit: 2 */ +#define ADC12SHT1_3 (0x3000) /* ADC12 Sample Hold 1 Select Bit: 3 */ +#define ADC12SHT1_4 (0x4000) /* ADC12 Sample Hold 1 Select Bit: 4 */ +#define ADC12SHT1_5 (0x5000) /* ADC12 Sample Hold 1 Select Bit: 5 */ +#define ADC12SHT1_6 (0x6000) /* ADC12 Sample Hold 1 Select Bit: 6 */ +#define ADC12SHT1_7 (0x7000) /* ADC12 Sample Hold 1 Select Bit: 7 */ +#define ADC12SHT1_8 (0x8000) /* ADC12 Sample Hold 1 Select Bit: 8 */ +#define ADC12SHT1_9 (0x9000) /* ADC12 Sample Hold 1 Select Bit: 9 */ +#define ADC12SHT1_10 (0xA000) /* ADC12 Sample Hold 1 Select Bit: 10 */ +#define ADC12SHT1_11 (0xB000) /* ADC12 Sample Hold 1 Select Bit: 11 */ +#define ADC12SHT1_12 (0xC000) /* ADC12 Sample Hold 1 Select Bit: 12 */ +#define ADC12SHT1_13 (0xD000) /* ADC12 Sample Hold 1 Select Bit: 13 */ +#define ADC12SHT1_14 (0xE000) /* ADC12 Sample Hold 1 Select Bit: 14 */ +#define ADC12SHT1_15 (0xF000) /* ADC12 Sample Hold 1 Select Bit: 15 */ + +/* ADC12CTL1 Control Bits */ +#define ADC12BUSY (0x0001) /* ADC12 Busy */ +#define ADC12CONSEQ0 (0x0002) /* ADC12 Conversion Sequence Select Bit: 0 */ +#define ADC12CONSEQ1 (0x0004) /* ADC12 Conversion Sequence Select Bit: 1 */ +#define ADC12SSEL0 (0x0008) /* ADC12 Clock Source Select Bit: 0 */ +#define ADC12SSEL1 (0x0010) /* ADC12 Clock Source Select Bit: 1 */ +#define ADC12DIV0 (0x0020) /* ADC12 Clock Divider Select Bit: 0 */ +#define ADC12DIV1 (0x0040) /* ADC12 Clock Divider Select Bit: 1 */ +#define ADC12DIV2 (0x0080) /* ADC12 Clock Divider Select Bit: 2 */ +#define ADC12ISSH (0x0100) /* ADC12 Invert Sample Hold Signal */ +#define ADC12SHP (0x0200) /* ADC12 Sample/Hold Pulse Mode */ +#define ADC12SHS0 (0x0400) /* ADC12 Sample/Hold Source Bit: 0 */ +#define ADC12SHS1 (0x0800) /* ADC12 Sample/Hold Source Bit: 1 */ +#define ADC12SHS2 (0x1000) /* ADC12 Sample/Hold Source Bit: 2 */ +#define ADC12PDIV0 (0x2000) /* ADC12 Predivider Bit: 0 */ +#define ADC12PDIV1 (0x4000) /* ADC12 Predivider Bit: 1 */ + +/* ADC12CTL1 Control Bits */ +#define ADC12BUSY_L (0x0001) /* ADC12 Busy */ +#define ADC12CONSEQ0_L (0x0002) /* ADC12 Conversion Sequence Select Bit: 0 */ +#define ADC12CONSEQ1_L (0x0004) /* ADC12 Conversion Sequence Select Bit: 1 */ +#define ADC12SSEL0_L (0x0008) /* ADC12 Clock Source Select Bit: 0 */ +#define ADC12SSEL1_L (0x0010) /* ADC12 Clock Source Select Bit: 1 */ +#define ADC12DIV0_L (0x0020) /* ADC12 Clock Divider Select Bit: 0 */ +#define ADC12DIV1_L (0x0040) /* ADC12 Clock Divider Select Bit: 1 */ +#define ADC12DIV2_L (0x0080) /* ADC12 Clock Divider Select Bit: 2 */ + +/* ADC12CTL1 Control Bits */ +#define ADC12ISSH_H (0x0001) /* ADC12 Invert Sample Hold Signal */ +#define ADC12SHP_H (0x0002) /* ADC12 Sample/Hold Pulse Mode */ +#define ADC12SHS0_H (0x0004) /* ADC12 Sample/Hold Source Bit: 0 */ +#define ADC12SHS1_H (0x0008) /* ADC12 Sample/Hold Source Bit: 1 */ +#define ADC12SHS2_H (0x0010) /* ADC12 Sample/Hold Source Bit: 2 */ +#define ADC12PDIV0_H (0x0020) /* ADC12 Predivider Bit: 0 */ +#define ADC12PDIV1_H (0x0040) /* ADC12 Predivider Bit: 1 */ + +#define ADC12CONSEQ_0 (0x0000) /* ADC12 Conversion Sequence Select: 0 */ +#define ADC12CONSEQ_1 (0x0002) /* ADC12 Conversion Sequence Select: 1 */ +#define ADC12CONSEQ_2 (0x0004) /* ADC12 Conversion Sequence Select: 2 */ +#define ADC12CONSEQ_3 (0x0006) /* ADC12 Conversion Sequence Select: 3 */ + +#define ADC12SSEL_0 (0x0000) /* ADC12 Clock Source Select: 0 */ +#define ADC12SSEL_1 (0x0008) /* ADC12 Clock Source Select: 1 */ +#define ADC12SSEL_2 (0x0010) /* ADC12 Clock Source Select: 2 */ +#define ADC12SSEL_3 (0x0018) /* ADC12 Clock Source Select: 3 */ + +#define ADC12DIV_0 (0x0000) /* ADC12 Clock Divider Select: 0 */ +#define ADC12DIV_1 (0x0020) /* ADC12 Clock Divider Select: 1 */ +#define ADC12DIV_2 (0x0040) /* ADC12 Clock Divider Select: 2 */ +#define ADC12DIV_3 (0x0060) /* ADC12 Clock Divider Select: 3 */ +#define ADC12DIV_4 (0x0080) /* ADC12 Clock Divider Select: 4 */ +#define ADC12DIV_5 (0x00A0) /* ADC12 Clock Divider Select: 5 */ +#define ADC12DIV_6 (0x00C0) /* ADC12 Clock Divider Select: 6 */ +#define ADC12DIV_7 (0x00E0) /* ADC12 Clock Divider Select: 7 */ + +#define ADC12SHS_0 (0x0000) /* ADC12 Sample/Hold Source: 0 */ +#define ADC12SHS_1 (0x0400) /* ADC12 Sample/Hold Source: 1 */ +#define ADC12SHS_2 (0x0800) /* ADC12 Sample/Hold Source: 2 */ +#define ADC12SHS_3 (0x0C00) /* ADC12 Sample/Hold Source: 3 */ +#define ADC12SHS_4 (0x1000) /* ADC12 Sample/Hold Source: 4 */ +#define ADC12SHS_5 (0x1400) /* ADC12 Sample/Hold Source: 5 */ +#define ADC12SHS_6 (0x1800) /* ADC12 Sample/Hold Source: 6 */ +#define ADC12SHS_7 (0x1C00) /* ADC12 Sample/Hold Source: 7 */ + +#define ADC12PDIV_0 (0x0000) /* ADC12 Clock predivider Select 0 */ +#define ADC12PDIV_1 (0x2000) /* ADC12 Clock predivider Select 1 */ +#define ADC12PDIV_2 (0x4000) /* ADC12 Clock predivider Select 2 */ +#define ADC12PDIV_3 (0x6000) /* ADC12 Clock predivider Select 3 */ +#define ADC12PDIV__1 (0x0000) /* ADC12 Clock predivider Select: /1 */ +#define ADC12PDIV__4 (0x2000) /* ADC12 Clock predivider Select: /4 */ +#define ADC12PDIV__32 (0x4000) /* ADC12 Clock predivider Select: /32 */ +#define ADC12PDIV__64 (0x6000) /* ADC12 Clock predivider Select: /64 */ + +/* ADC12CTL2 Control Bits */ +#define ADC12PWRMD (0x0001) /* ADC12 Power Mode */ +#define ADC12DF (0x0008) /* ADC12 Data Format */ +#define ADC12RES0 (0x0010) /* ADC12 Resolution Bit: 0 */ +#define ADC12RES1 (0x0020) /* ADC12 Resolution Bit: 1 */ + +/* ADC12CTL2 Control Bits */ +#define ADC12PWRMD_L (0x0001) /* ADC12 Power Mode */ +#define ADC12DF_L (0x0008) /* ADC12 Data Format */ +#define ADC12RES0_L (0x0010) /* ADC12 Resolution Bit: 0 */ +#define ADC12RES1_L (0x0020) /* ADC12 Resolution Bit: 1 */ + + +#define ADC12RES_0 (0x0000) /* ADC12+ Resolution : 8 Bit */ +#define ADC12RES_1 (0x0010) /* ADC12+ Resolution : 10 Bit */ +#define ADC12RES_2 (0x0020) /* ADC12+ Resolution : 12 Bit */ +#define ADC12RES_3 (0x0030) /* ADC12+ Resolution : reserved */ + +#define ADC12RES__8BIT (0x0000) /* ADC12+ Resolution : 8 Bit */ +#define ADC12RES__10BIT (0x0010) /* ADC12+ Resolution : 10 Bit */ +#define ADC12RES__12BIT (0x0020) /* ADC12+ Resolution : 12 Bit */ + +/* ADC12CTL3 Control Bits */ +#define ADC12CSTARTADD0 (0x0001) /* ADC12 Conversion Start Address Bit: 0 */ +#define ADC12CSTARTADD1 (0x0002) /* ADC12 Conversion Start Address Bit: 1 */ +#define ADC12CSTARTADD2 (0x0004) /* ADC12 Conversion Start Address Bit: 2 */ +#define ADC12CSTARTADD3 (0x0008) /* ADC12 Conversion Start Address Bit: 3 */ +#define ADC12CSTARTADD4 (0x0010) /* ADC12 Conversion Start Address Bit: 4 */ +#define ADC12BATMAP (0x0040) /* ADC12 Internal AVCC/2 select */ +#define ADC12TCMAP (0x0080) /* ADC12 Internal TempSensor select */ +#define ADC12ICH0MAP (0x0100) /* ADC12 Internal Channel 0 select */ +#define ADC12ICH1MAP (0x0200) /* ADC12 Internal Channel 1 select */ +#define ADC12ICH2MAP (0x0400) /* ADC12 Internal Channel 2 select */ +#define ADC12ICH3MAP (0x0800) /* ADC12 Internal Channel 3 select */ + +/* ADC12CTL3 Control Bits */ +#define ADC12CSTARTADD0_L (0x0001) /* ADC12 Conversion Start Address Bit: 0 */ +#define ADC12CSTARTADD1_L (0x0002) /* ADC12 Conversion Start Address Bit: 1 */ +#define ADC12CSTARTADD2_L (0x0004) /* ADC12 Conversion Start Address Bit: 2 */ +#define ADC12CSTARTADD3_L (0x0008) /* ADC12 Conversion Start Address Bit: 3 */ +#define ADC12CSTARTADD4_L (0x0010) /* ADC12 Conversion Start Address Bit: 4 */ +#define ADC12BATMAP_L (0x0040) /* ADC12 Internal AVCC/2 select */ +#define ADC12TCMAP_L (0x0080) /* ADC12 Internal TempSensor select */ + +/* ADC12CTL3 Control Bits */ +#define ADC12ICH0MAP_H (0x0001) /* ADC12 Internal Channel 0 select */ +#define ADC12ICH1MAP_H (0x0002) /* ADC12 Internal Channel 1 select */ +#define ADC12ICH2MAP_H (0x0004) /* ADC12 Internal Channel 2 select */ +#define ADC12ICH3MAP_H (0x0008) /* ADC12 Internal Channel 3 select */ + +#define ADC12CSTARTADD_0 (0x0000) /* ADC12 Conversion Start Address: 0 */ +#define ADC12CSTARTADD_1 (0x0001) /* ADC12 Conversion Start Address: 1 */ +#define ADC12CSTARTADD_2 (0x0002) /* ADC12 Conversion Start Address: 2 */ +#define ADC12CSTARTADD_3 (0x0003) /* ADC12 Conversion Start Address: 3 */ +#define ADC12CSTARTADD_4 (0x0004) /* ADC12 Conversion Start Address: 4 */ +#define ADC12CSTARTADD_5 (0x0005) /* ADC12 Conversion Start Address: 5 */ +#define ADC12CSTARTADD_6 (0x0006) /* ADC12 Conversion Start Address: 6 */ +#define ADC12CSTARTADD_7 (0x0007) /* ADC12 Conversion Start Address: 7 */ +#define ADC12CSTARTADD_8 (0x0008) /* ADC12 Conversion Start Address: 8 */ +#define ADC12CSTARTADD_9 (0x0009) /* ADC12 Conversion Start Address: 9 */ +#define ADC12CSTARTADD_10 (0x000A) /* ADC12 Conversion Start Address: 10 */ +#define ADC12CSTARTADD_11 (0x000B) /* ADC12 Conversion Start Address: 11 */ +#define ADC12CSTARTADD_12 (0x000C) /* ADC12 Conversion Start Address: 12 */ +#define ADC12CSTARTADD_13 (0x000D) /* ADC12 Conversion Start Address: 13 */ +#define ADC12CSTARTADD_14 (0x000E) /* ADC12 Conversion Start Address: 14 */ +#define ADC12CSTARTADD_15 (0x000F) /* ADC12 Conversion Start Address: 15 */ +#define ADC12CSTARTADD_16 (0x0010) /* ADC12 Conversion Start Address: 16 */ +#define ADC12CSTARTADD_17 (0x0011) /* ADC12 Conversion Start Address: 17 */ +#define ADC12CSTARTADD_18 (0x0012) /* ADC12 Conversion Start Address: 18 */ +#define ADC12CSTARTADD_19 (0x0013) /* ADC12 Conversion Start Address: 19 */ +#define ADC12CSTARTADD_20 (0x0014) /* ADC12 Conversion Start Address: 20 */ +#define ADC12CSTARTADD_21 (0x0015) /* ADC12 Conversion Start Address: 21 */ +#define ADC12CSTARTADD_22 (0x0016) /* ADC12 Conversion Start Address: 22 */ +#define ADC12CSTARTADD_23 (0x0017) /* ADC12 Conversion Start Address: 23 */ +#define ADC12CSTARTADD_24 (0x0018) /* ADC12 Conversion Start Address: 24 */ +#define ADC12CSTARTADD_25 (0x0019) /* ADC12 Conversion Start Address: 25 */ +#define ADC12CSTARTADD_26 (0x001A) /* ADC12 Conversion Start Address: 26 */ +#define ADC12CSTARTADD_27 (0x001B) /* ADC12 Conversion Start Address: 27 */ +#define ADC12CSTARTADD_28 (0x001C) /* ADC12 Conversion Start Address: 28 */ +#define ADC12CSTARTADD_29 (0x001D) /* ADC12 Conversion Start Address: 29 */ +#define ADC12CSTARTADD_30 (0x001E) /* ADC12 Conversion Start Address: 30 */ +#define ADC12CSTARTADD_31 (0x001F) /* ADC12 Conversion Start Address: 31 */ + +/* ADC12MCTLx Control Bits */ +#define ADC12INCH0 (0x0001) /* ADC12 Input Channel Select Bit 0 */ +#define ADC12INCH1 (0x0002) /* ADC12 Input Channel Select Bit 1 */ +#define ADC12INCH2 (0x0004) /* ADC12 Input Channel Select Bit 2 */ +#define ADC12INCH3 (0x0008) /* ADC12 Input Channel Select Bit 3 */ +#define ADC12INCH4 (0x0010) /* ADC12 Input Channel Select Bit 4 */ +#define ADC12EOS (0x0080) /* ADC12 End of Sequence */ +#define ADC12VRSEL0 (0x0100) /* ADC12 VR Select Bit 0 */ +#define ADC12VRSEL1 (0x0200) /* ADC12 VR Select Bit 1 */ +#define ADC12VRSEL2 (0x0400) /* ADC12 VR Select Bit 2 */ +#define ADC12VRSEL3 (0x0800) /* ADC12 VR Select Bit 3 */ +#define ADC12DIF (0x2000) /* ADC12 Differential mode (only for even Registers) */ +#define ADC12WINC (0x4000) /* ADC12 Comparator window enable */ + +/* ADC12MCTLx Control Bits */ +#define ADC12INCH0_L (0x0001) /* ADC12 Input Channel Select Bit 0 */ +#define ADC12INCH1_L (0x0002) /* ADC12 Input Channel Select Bit 1 */ +#define ADC12INCH2_L (0x0004) /* ADC12 Input Channel Select Bit 2 */ +#define ADC12INCH3_L (0x0008) /* ADC12 Input Channel Select Bit 3 */ +#define ADC12INCH4_L (0x0010) /* ADC12 Input Channel Select Bit 4 */ +#define ADC12EOS_L (0x0080) /* ADC12 End of Sequence */ + +/* ADC12MCTLx Control Bits */ +#define ADC12VRSEL0_H (0x0001) /* ADC12 VR Select Bit 0 */ +#define ADC12VRSEL1_H (0x0002) /* ADC12 VR Select Bit 1 */ +#define ADC12VRSEL2_H (0x0004) /* ADC12 VR Select Bit 2 */ +#define ADC12VRSEL3_H (0x0008) /* ADC12 VR Select Bit 3 */ +#define ADC12DIF_H (0x0020) /* ADC12 Differential mode (only for even Registers) */ +#define ADC12WINC_H (0x0040) /* ADC12 Comparator window enable */ + + + + +#define ADC12INCH_0 (0x0000) /* ADC12 Input Channel 0 */ +#define ADC12INCH_1 (0x0001) /* ADC12 Input Channel 1 */ +#define ADC12INCH_2 (0x0002) /* ADC12 Input Channel 2 */ +#define ADC12INCH_3 (0x0003) /* ADC12 Input Channel 3 */ +#define ADC12INCH_4 (0x0004) /* ADC12 Input Channel 4 */ +#define ADC12INCH_5 (0x0005) /* ADC12 Input Channel 5 */ +#define ADC12INCH_6 (0x0006) /* ADC12 Input Channel 6 */ +#define ADC12INCH_7 (0x0007) /* ADC12 Input Channel 7 */ +#define ADC12INCH_8 (0x0008) /* ADC12 Input Channel 8 */ +#define ADC12INCH_9 (0x0009) /* ADC12 Input Channel 9 */ +#define ADC12INCH_10 (0x000A) /* ADC12 Input Channel 10 */ +#define ADC12INCH_11 (0x000B) /* ADC12 Input Channel 11 */ +#define ADC12INCH_12 (0x000C) /* ADC12 Input Channel 12 */ +#define ADC12INCH_13 (0x000D) /* ADC12 Input Channel 13 */ +#define ADC12INCH_14 (0x000E) /* ADC12 Input Channel 14 */ +#define ADC12INCH_15 (0x000F) /* ADC12 Input Channel 15 */ +#define ADC12INCH_16 (0x0010) /* ADC12 Input Channel 16 */ +#define ADC12INCH_17 (0x0011) /* ADC12 Input Channel 17 */ +#define ADC12INCH_18 (0x0012) /* ADC12 Input Channel 18 */ +#define ADC12INCH_19 (0x0013) /* ADC12 Input Channel 19 */ +#define ADC12INCH_20 (0x0014) /* ADC12 Input Channel 20 */ +#define ADC12INCH_21 (0x0015) /* ADC12 Input Channel 21 */ +#define ADC12INCH_22 (0x0016) /* ADC12 Input Channel 22 */ +#define ADC12INCH_23 (0x0017) /* ADC12 Input Channel 23 */ +#define ADC12INCH_24 (0x0018) /* ADC12 Input Channel 24 */ +#define ADC12INCH_25 (0x0019) /* ADC12 Input Channel 25 */ +#define ADC12INCH_26 (0x001A) /* ADC12 Input Channel 26 */ +#define ADC12INCH_27 (0x001B) /* ADC12 Input Channel 27 */ +#define ADC12INCH_28 (0x001C) /* ADC12 Input Channel 28 */ +#define ADC12INCH_29 (0x001D) /* ADC12 Input Channel 29 */ +#define ADC12INCH_30 (0x001E) /* ADC12 Input Channel 30 */ +#define ADC12INCH_31 (0x001F) /* ADC12 Input Channel 31 */ + +#define ADC12VRSEL_0 (0x0000) /* ADC12 Select Reference 0 */ +#define ADC12VRSEL_1 (0x0100) /* ADC12 Select Reference 1 */ +#define ADC12VRSEL_2 (0x0200) /* ADC12 Select Reference 2 */ +#define ADC12VRSEL_3 (0x0300) /* ADC12 Select Reference 3 */ +#define ADC12VRSEL_4 (0x0400) /* ADC12 Select Reference 4 */ +#define ADC12VRSEL_5 (0x0500) /* ADC12 Select Reference 5 */ +#define ADC12VRSEL_6 (0x0600) /* ADC12 Select Reference 6 */ +#define ADC12VRSEL_7 (0x0700) /* ADC12 Select Reference 7 */ +#define ADC12VRSEL_8 (0x0800) /* ADC12 Select Reference 8 */ +#define ADC12VRSEL_9 (0x0900) /* ADC12 Select Reference 9 */ +#define ADC12VRSEL_10 (0x0A00) /* ADC12 Select Reference 10 */ +#define ADC12VRSEL_11 (0x0B00) /* ADC12 Select Reference 11 */ +#define ADC12VRSEL_12 (0x0C00) /* ADC12 Select Reference 12 */ +#define ADC12VRSEL_13 (0x0D00) /* ADC12 Select Reference 13 */ +#define ADC12VRSEL_14 (0x0E00) /* ADC12 Select Reference 14 */ +#define ADC12VRSEL_15 (0x0F00) /* ADC12 Select Reference 15 */ + +/* ADC12HI Control Bits */ + + +/* ADC12LO Control Bits */ + + + +/* ADC12IER0 Control Bits */ +#define ADC12IE0 (0x0001) /* ADC12 Memory 0 Interrupt Enable */ +#define ADC12IE1 (0x0002) /* ADC12 Memory 1 Interrupt Enable */ +#define ADC12IE2 (0x0004) /* ADC12 Memory 2 Interrupt Enable */ +#define ADC12IE3 (0x0008) /* ADC12 Memory 3 Interrupt Enable */ +#define ADC12IE4 (0x0010) /* ADC12 Memory 4 Interrupt Enable */ +#define ADC12IE5 (0x0020) /* ADC12 Memory 5 Interrupt Enable */ +#define ADC12IE6 (0x0040) /* ADC12 Memory 6 Interrupt Enable */ +#define ADC12IE7 (0x0080) /* ADC12 Memory 7 Interrupt Enable */ +#define ADC12IE8 (0x0100) /* ADC12 Memory 8 Interrupt Enable */ +#define ADC12IE9 (0x0200) /* ADC12 Memory 9 Interrupt Enable */ +#define ADC12IE10 (0x0400) /* ADC12 Memory 10 Interrupt Enable */ +#define ADC12IE11 (0x0800) /* ADC12 Memory 11 Interrupt Enable */ +#define ADC12IE12 (0x1000) /* ADC12 Memory 12 Interrupt Enable */ +#define ADC12IE13 (0x2000) /* ADC12 Memory 13 Interrupt Enable */ +#define ADC12IE14 (0x4000) /* ADC12 Memory 14 Interrupt Enable */ +#define ADC12IE15 (0x8000) /* ADC12 Memory 15 Interrupt Enable */ + +/* ADC12IER0 Control Bits */ +#define ADC12IE0_L (0x0001) /* ADC12 Memory 0 Interrupt Enable */ +#define ADC12IE1_L (0x0002) /* ADC12 Memory 1 Interrupt Enable */ +#define ADC12IE2_L (0x0004) /* ADC12 Memory 2 Interrupt Enable */ +#define ADC12IE3_L (0x0008) /* ADC12 Memory 3 Interrupt Enable */ +#define ADC12IE4_L (0x0010) /* ADC12 Memory 4 Interrupt Enable */ +#define ADC12IE5_L (0x0020) /* ADC12 Memory 5 Interrupt Enable */ +#define ADC12IE6_L (0x0040) /* ADC12 Memory 6 Interrupt Enable */ +#define ADC12IE7_L (0x0080) /* ADC12 Memory 7 Interrupt Enable */ + +/* ADC12IER0 Control Bits */ +#define ADC12IE8_H (0x0001) /* ADC12 Memory 8 Interrupt Enable */ +#define ADC12IE9_H (0x0002) /* ADC12 Memory 9 Interrupt Enable */ +#define ADC12IE10_H (0x0004) /* ADC12 Memory 10 Interrupt Enable */ +#define ADC12IE11_H (0x0008) /* ADC12 Memory 11 Interrupt Enable */ +#define ADC12IE12_H (0x0010) /* ADC12 Memory 12 Interrupt Enable */ +#define ADC12IE13_H (0x0020) /* ADC12 Memory 13 Interrupt Enable */ +#define ADC12IE14_H (0x0040) /* ADC12 Memory 14 Interrupt Enable */ +#define ADC12IE15_H (0x0080) /* ADC12 Memory 15 Interrupt Enable */ + +/* ADC12IER1 Control Bits */ +#define ADC12IE16 (0x0001) /* ADC12 Memory 16 Interrupt Enable */ +#define ADC12IE17 (0x0002) /* ADC12 Memory 17 Interrupt Enable */ +#define ADC12IE18 (0x0004) /* ADC12 Memory 18 Interrupt Enable */ +#define ADC12IE19 (0x0008) /* ADC12 Memory 19 Interrupt Enable */ +#define ADC12IE20 (0x0010) /* ADC12 Memory 20 Interrupt Enable */ +#define ADC12IE21 (0x0020) /* ADC12 Memory 21 Interrupt Enable */ +#define ADC12IE22 (0x0040) /* ADC12 Memory 22 Interrupt Enable */ +#define ADC12IE23 (0x0080) /* ADC12 Memory 23 Interrupt Enable */ +#define ADC12IE24 (0x0100) /* ADC12 Memory 24 Interrupt Enable */ +#define ADC12IE25 (0x0200) /* ADC12 Memory 25 Interrupt Enable */ +#define ADC12IE26 (0x0400) /* ADC12 Memory 26 Interrupt Enable */ +#define ADC12IE27 (0x0800) /* ADC12 Memory 27 Interrupt Enable */ +#define ADC12IE28 (0x1000) /* ADC12 Memory 28 Interrupt Enable */ +#define ADC12IE29 (0x2000) /* ADC12 Memory 29 Interrupt Enable */ +#define ADC12IE30 (0x4000) /* ADC12 Memory 30 Interrupt Enable */ +#define ADC12IE31 (0x8000) /* ADC12 Memory 31 Interrupt Enable */ + +/* ADC12IER1 Control Bits */ +#define ADC12IE16_L (0x0001) /* ADC12 Memory 16 Interrupt Enable */ +#define ADC12IE17_L (0x0002) /* ADC12 Memory 17 Interrupt Enable */ +#define ADC12IE18_L (0x0004) /* ADC12 Memory 18 Interrupt Enable */ +#define ADC12IE19_L (0x0008) /* ADC12 Memory 19 Interrupt Enable */ +#define ADC12IE20_L (0x0010) /* ADC12 Memory 20 Interrupt Enable */ +#define ADC12IE21_L (0x0020) /* ADC12 Memory 21 Interrupt Enable */ +#define ADC12IE22_L (0x0040) /* ADC12 Memory 22 Interrupt Enable */ +#define ADC12IE23_L (0x0080) /* ADC12 Memory 23 Interrupt Enable */ + +/* ADC12IER1 Control Bits */ +#define ADC12IE24_H (0x0001) /* ADC12 Memory 24 Interrupt Enable */ +#define ADC12IE25_H (0x0002) /* ADC12 Memory 25 Interrupt Enable */ +#define ADC12IE26_H (0x0004) /* ADC12 Memory 26 Interrupt Enable */ +#define ADC12IE27_H (0x0008) /* ADC12 Memory 27 Interrupt Enable */ +#define ADC12IE28_H (0x0010) /* ADC12 Memory 28 Interrupt Enable */ +#define ADC12IE29_H (0x0020) /* ADC12 Memory 29 Interrupt Enable */ +#define ADC12IE30_H (0x0040) /* ADC12 Memory 30 Interrupt Enable */ +#define ADC12IE31_H (0x0080) /* ADC12 Memory 31 Interrupt Enable */ + +/* ADC12IER2 Control Bits */ +#define ADC12INIE (0x0002) /* ADC12 Interrupt enable for the inside of window of the Window comparator */ +#define ADC12LOIE (0x0004) /* ADC12 Interrupt enable for lower threshold of the Window comparator */ +#define ADC12HIIE (0x0008) /* ADC12 Interrupt enable for upper threshold of the Window comparator */ +#define ADC12OVIE (0x0010) /* ADC12 ADC12MEMx Overflow interrupt enable */ +#define ADC12TOVIE (0x0020) /* ADC12 Timer Overflow interrupt enable */ +#define ADC12RDYIE (0x0040) /* ADC12 local buffered reference ready interrupt enable */ + +/* ADC12IER2 Control Bits */ +#define ADC12INIE_L (0x0002) /* ADC12 Interrupt enable for the inside of window of the Window comparator */ +#define ADC12LOIE_L (0x0004) /* ADC12 Interrupt enable for lower threshold of the Window comparator */ +#define ADC12HIIE_L (0x0008) /* ADC12 Interrupt enable for upper threshold of the Window comparator */ +#define ADC12OVIE_L (0x0010) /* ADC12 ADC12MEMx Overflow interrupt enable */ +#define ADC12TOVIE_L (0x0020) /* ADC12 Timer Overflow interrupt enable */ +#define ADC12RDYIE_L (0x0040) /* ADC12 local buffered reference ready interrupt enable */ + + +/* ADC12IFGR0 Control Bits */ +#define ADC12IFG0 (0x0001) /* ADC12 Memory 0 Interrupt Flag */ +#define ADC12IFG1 (0x0002) /* ADC12 Memory 1 Interrupt Flag */ +#define ADC12IFG2 (0x0004) /* ADC12 Memory 2 Interrupt Flag */ +#define ADC12IFG3 (0x0008) /* ADC12 Memory 3 Interrupt Flag */ +#define ADC12IFG4 (0x0010) /* ADC12 Memory 4 Interrupt Flag */ +#define ADC12IFG5 (0x0020) /* ADC12 Memory 5 Interrupt Flag */ +#define ADC12IFG6 (0x0040) /* ADC12 Memory 6 Interrupt Flag */ +#define ADC12IFG7 (0x0080) /* ADC12 Memory 7 Interrupt Flag */ +#define ADC12IFG8 (0x0100) /* ADC12 Memory 8 Interrupt Flag */ +#define ADC12IFG9 (0x0200) /* ADC12 Memory 9 Interrupt Flag */ +#define ADC12IFG10 (0x0400) /* ADC12 Memory 10 Interrupt Flag */ +#define ADC12IFG11 (0x0800) /* ADC12 Memory 11 Interrupt Flag */ +#define ADC12IFG12 (0x1000) /* ADC12 Memory 12 Interrupt Flag */ +#define ADC12IFG13 (0x2000) /* ADC12 Memory 13 Interrupt Flag */ +#define ADC12IFG14 (0x4000) /* ADC12 Memory 14 Interrupt Flag */ +#define ADC12IFG15 (0x8000) /* ADC12 Memory 15 Interrupt Flag */ + +/* ADC12IFGR0 Control Bits */ +#define ADC12IFG0_L (0x0001) /* ADC12 Memory 0 Interrupt Flag */ +#define ADC12IFG1_L (0x0002) /* ADC12 Memory 1 Interrupt Flag */ +#define ADC12IFG2_L (0x0004) /* ADC12 Memory 2 Interrupt Flag */ +#define ADC12IFG3_L (0x0008) /* ADC12 Memory 3 Interrupt Flag */ +#define ADC12IFG4_L (0x0010) /* ADC12 Memory 4 Interrupt Flag */ +#define ADC12IFG5_L (0x0020) /* ADC12 Memory 5 Interrupt Flag */ +#define ADC12IFG6_L (0x0040) /* ADC12 Memory 6 Interrupt Flag */ +#define ADC12IFG7_L (0x0080) /* ADC12 Memory 7 Interrupt Flag */ + +/* ADC12IFGR0 Control Bits */ +#define ADC12IFG8_H (0x0001) /* ADC12 Memory 8 Interrupt Flag */ +#define ADC12IFG9_H (0x0002) /* ADC12 Memory 9 Interrupt Flag */ +#define ADC12IFG10_H (0x0004) /* ADC12 Memory 10 Interrupt Flag */ +#define ADC12IFG11_H (0x0008) /* ADC12 Memory 11 Interrupt Flag */ +#define ADC12IFG12_H (0x0010) /* ADC12 Memory 12 Interrupt Flag */ +#define ADC12IFG13_H (0x0020) /* ADC12 Memory 13 Interrupt Flag */ +#define ADC12IFG14_H (0x0040) /* ADC12 Memory 14 Interrupt Flag */ +#define ADC12IFG15_H (0x0080) /* ADC12 Memory 15 Interrupt Flag */ + +/* ADC12IFGR1 Control Bits */ +#define ADC12IFG16 (0x0001) /* ADC12 Memory 16 Interrupt Flag */ +#define ADC12IFG17 (0x0002) /* ADC12 Memory 17 Interrupt Flag */ +#define ADC12IFG18 (0x0004) /* ADC12 Memory 18 Interrupt Flag */ +#define ADC12IFG19 (0x0008) /* ADC12 Memory 19 Interrupt Flag */ +#define ADC12IFG20 (0x0010) /* ADC12 Memory 20 Interrupt Flag */ +#define ADC12IFG21 (0x0020) /* ADC12 Memory 21 Interrupt Flag */ +#define ADC12IFG22 (0x0040) /* ADC12 Memory 22 Interrupt Flag */ +#define ADC12IFG23 (0x0080) /* ADC12 Memory 23 Interrupt Flag */ +#define ADC12IFG24 (0x0100) /* ADC12 Memory 24 Interrupt Flag */ +#define ADC12IFG25 (0x0200) /* ADC12 Memory 25 Interrupt Flag */ +#define ADC12IFG26 (0x0400) /* ADC12 Memory 26 Interrupt Flag */ +#define ADC12IFG27 (0x0800) /* ADC12 Memory 27 Interrupt Flag */ +#define ADC12IFG28 (0x1000) /* ADC12 Memory 28 Interrupt Flag */ +#define ADC12IFG29 (0x2000) /* ADC12 Memory 29 Interrupt Flag */ +#define ADC12IFG30 (0x4000) /* ADC12 Memory 30 Interrupt Flag */ +#define ADC12IFG31 (0x8000) /* ADC12 Memory 31 Interrupt Flag */ + +/* ADC12IFGR1 Control Bits */ +#define ADC12IFG16_L (0x0001) /* ADC12 Memory 16 Interrupt Flag */ +#define ADC12IFG17_L (0x0002) /* ADC12 Memory 17 Interrupt Flag */ +#define ADC12IFG18_L (0x0004) /* ADC12 Memory 18 Interrupt Flag */ +#define ADC12IFG19_L (0x0008) /* ADC12 Memory 19 Interrupt Flag */ +#define ADC12IFG20_L (0x0010) /* ADC12 Memory 20 Interrupt Flag */ +#define ADC12IFG21_L (0x0020) /* ADC12 Memory 21 Interrupt Flag */ +#define ADC12IFG22_L (0x0040) /* ADC12 Memory 22 Interrupt Flag */ +#define ADC12IFG23_L (0x0080) /* ADC12 Memory 23 Interrupt Flag */ + +/* ADC12IFGR1 Control Bits */ +#define ADC12IFG24_H (0x0001) /* ADC12 Memory 24 Interrupt Flag */ +#define ADC12IFG25_H (0x0002) /* ADC12 Memory 25 Interrupt Flag */ +#define ADC12IFG26_H (0x0004) /* ADC12 Memory 26 Interrupt Flag */ +#define ADC12IFG27_H (0x0008) /* ADC12 Memory 27 Interrupt Flag */ +#define ADC12IFG28_H (0x0010) /* ADC12 Memory 28 Interrupt Flag */ +#define ADC12IFG29_H (0x0020) /* ADC12 Memory 29 Interrupt Flag */ +#define ADC12IFG30_H (0x0040) /* ADC12 Memory 30 Interrupt Flag */ +#define ADC12IFG31_H (0x0080) /* ADC12 Memory 31 Interrupt Flag */ + +/* ADC12IFGR2 Control Bits */ +#define ADC12INIFG (0x0002) /* ADC12 Interrupt Flag for the inside of window of the Window comparator */ +#define ADC12LOIFG (0x0004) /* ADC12 Interrupt Flag for lower threshold of the Window comparator */ +#define ADC12HIIFG (0x0008) /* ADC12 Interrupt Flag for upper threshold of the Window comparator */ +#define ADC12OVIFG (0x0010) /* ADC12 ADC12MEMx Overflow interrupt Flag */ +#define ADC12TOVIFG (0x0020) /* ADC12 Timer Overflow interrupt Flag */ +#define ADC12RDYIFG (0x0040) /* ADC12 local buffered reference ready interrupt Flag */ + +/* ADC12IFGR2 Control Bits */ +#define ADC12INIFG_L (0x0002) /* ADC12 Interrupt Flag for the inside of window of the Window comparator */ +#define ADC12LOIFG_L (0x0004) /* ADC12 Interrupt Flag for lower threshold of the Window comparator */ +#define ADC12HIIFG_L (0x0008) /* ADC12 Interrupt Flag for upper threshold of the Window comparator */ +#define ADC12OVIFG_L (0x0010) /* ADC12 ADC12MEMx Overflow interrupt Flag */ +#define ADC12TOVIFG_L (0x0020) /* ADC12 Timer Overflow interrupt Flag */ +#define ADC12RDYIFG_L (0x0040) /* ADC12 local buffered reference ready interrupt Flag */ + + +/* ADC12IV Definitions */ +#define ADC12IV_NONE (0x0000) /* No Interrupt pending */ +#define ADC12IV_ADC12OVIFG (0x0002) /* ADC12OVIFG */ +#define ADC12IV_ADC12TOVIFG (0x0004) /* ADC12TOVIFG */ +#define ADC12IV_ADC12HIIFG (0x0006) /* ADC12HIIFG */ +#define ADC12IV_ADC12LOIFG (0x0008) /* ADC12LOIFG */ +#define ADC12IV_ADC12INIFG (0x000A) /* ADC12INIFG */ +#define ADC12IV_ADC12IFG0 (0x000C) /* ADC12IFG0 */ +#define ADC12IV_ADC12IFG1 (0x000E) /* ADC12IFG1 */ +#define ADC12IV_ADC12IFG2 (0x0010) /* ADC12IFG2 */ +#define ADC12IV_ADC12IFG3 (0x0012) /* ADC12IFG3 */ +#define ADC12IV_ADC12IFG4 (0x0014) /* ADC12IFG4 */ +#define ADC12IV_ADC12IFG5 (0x0016) /* ADC12IFG5 */ +#define ADC12IV_ADC12IFG6 (0x0018) /* ADC12IFG6 */ +#define ADC12IV_ADC12IFG7 (0x001A) /* ADC12IFG7 */ +#define ADC12IV_ADC12IFG8 (0x001C) /* ADC12IFG8 */ +#define ADC12IV_ADC12IFG9 (0x001E) /* ADC12IFG9 */ +#define ADC12IV_ADC12IFG10 (0x0020) /* ADC12IFG10 */ +#define ADC12IV_ADC12IFG11 (0x0022) /* ADC12IFG11 */ +#define ADC12IV_ADC12IFG12 (0x0024) /* ADC12IFG12 */ +#define ADC12IV_ADC12IFG13 (0x0026) /* ADC12IFG13 */ +#define ADC12IV_ADC12IFG14 (0x0028) /* ADC12IFG14 */ +#define ADC12IV_ADC12IFG15 (0x002A) /* ADC12IFG15 */ +#define ADC12IV_ADC12IFG16 (0x002C) /* ADC12IFG16 */ +#define ADC12IV_ADC12IFG17 (0x002E) /* ADC12IFG17 */ +#define ADC12IV_ADC12IFG18 (0x0030) /* ADC12IFG18 */ +#define ADC12IV_ADC12IFG19 (0x0032) /* ADC12IFG19 */ +#define ADC12IV_ADC12IFG20 (0x0034) /* ADC12IFG20 */ +#define ADC12IV_ADC12IFG21 (0x0036) /* ADC12IFG21 */ +#define ADC12IV_ADC12IFG22 (0x0038) /* ADC12IFG22 */ +#define ADC12IV_ADC12IFG23 (0x003A) /* ADC12IFG23 */ +#define ADC12IV_ADC12IFG24 (0x003C) /* ADC12IFG24 */ +#define ADC12IV_ADC12IFG25 (0x003E) /* ADC12IFG25 */ +#define ADC12IV_ADC12IFG26 (0x0040) /* ADC12IFG26 */ +#define ADC12IV_ADC12IFG27 (0x0042) /* ADC12IFG27 */ +#define ADC12IV_ADC12IFG28 (0x0044) /* ADC12IFG28 */ +#define ADC12IV_ADC12IFG29 (0x0046) /* ADC12IFG29 */ +#define ADC12IV_ADC12IFG30 (0x0048) /* ADC12IFG30 */ +#define ADC12IV_ADC12IFG31 (0x004A) /* ADC12IFG31 */ +#define ADC12IV_ADC12RDYIFG (0x004C) /* ADC12RDYIFG */ + + +/************************************************************ +* AES256 Accelerator +************************************************************/ + +#define AESACTL0 0x09C0 /* AES accelerator control register 0 */ +#define AESACTL1 0x09C2 /* AES accelerator control register 1 */ +#define AESASTAT 0x09C4 /* AES accelerator status register */ +#define AESAKEY 0x09C6 /* AES accelerator key register */ +#define AESADIN 0x09C8 /* AES accelerator data in register */ +#define AESADOUT 0x09CA /* AES accelerator data out register */ +#define AESAXDIN 0x09CC /* AES accelerator XORed data in register */ +#define AESAXIN 0x09CE /* AES accelerator XORed data in register (no trigger) */ + + +/* AESACTL0 Control Bits */ +#define AESOP0 (0x0001) /* AES Operation Bit: 0 */ +#define AESOP1 (0x0002) /* AES Operation Bit: 1 */ +#define AESKL0 (0x0004) /* AES Key length Bit: 0 */ +#define AESKL1 (0x0008) /* AES Key length Bit: 1 */ +#define AESTRIG (0x0010) /* AES Trigger Select */ +#define AESCM0 (0x0020) /* AES Cipher mode select Bit: 0 */ +#define AESCM1 (0x0040) /* AES Cipher mode select Bit: 1 */ +#define AESSWRST (0x0080) /* AES Software Reset */ +#define AESRDYIFG (0x0100) /* AES ready interrupt flag */ +#define AESERRFG (0x0800) /* AES Error Flag */ +#define AESRDYIE (0x1000) /* AES ready interrupt enable*/ +#define AESCMEN (0x8000) /* AES DMA cipher mode enable*/ + +/* AESACTL0 Control Bits */ +#define AESOP0_L (0x0001) /* AES Operation Bit: 0 */ +#define AESOP1_L (0x0002) /* AES Operation Bit: 1 */ +#define AESKL0_L (0x0004) /* AES Key length Bit: 0 */ +#define AESKL1_L (0x0008) /* AES Key length Bit: 1 */ +#define AESTRIG_L (0x0010) /* AES Trigger Select */ +#define AESCM0_L (0x0020) /* AES Cipher mode select Bit: 0 */ +#define AESCM1_L (0x0040) /* AES Cipher mode select Bit: 1 */ +#define AESSWRST_L (0x0080) /* AES Software Reset */ + +/* AESACTL0 Control Bits */ +#define AESRDYIFG_H (0x0001) /* AES ready interrupt flag */ +#define AESERRFG_H (0x0008) /* AES Error Flag */ +#define AESRDYIE_H (0x0010) /* AES ready interrupt enable*/ +#define AESCMEN_H (0x0080) /* AES DMA cipher mode enable*/ + +#define AESOP_0 (0x0000) /* AES Operation: Encrypt */ +#define AESOP_1 (0x0001) /* AES Operation: Decrypt (same Key) */ +#define AESOP_2 (0x0002) /* AES Operation: Decrypt (frist round Key) */ +#define AESOP_3 (0x0003) /* AES Operation: Generate first round Key */ + +#define AESKL_0 (0x0000) /* AES Key length: AES128 */ +#define AESKL_1 (0x0004) /* AES Key length: AES192 */ +#define AESKL_2 (0x0008) /* AES Key length: AES256 */ +#define AESKL__128 (0x0000) /* AES Key length: AES128 */ +#define AESKL__192 (0x0004) /* AES Key length: AES192 */ +#define AESKL__256 (0x0008) /* AES Key length: AES256 */ + +#define AESCM_0 (0x0000) /* AES Cipher mode select: ECB */ +#define AESCM_1 (0x0020) /* AES Cipher mode select: CBC */ +#define AESCM_2 (0x0040) /* AES Cipher mode select: OFB */ +#define AESCM_3 (0x0060) /* AES Cipher mode select: CFB */ +#define AESCM__ECB (0x0000) /* AES Cipher mode select: ECB */ +#define AESCM__CBC (0x0020) /* AES Cipher mode select: CBC */ +#define AESCM__OFB (0x0040) /* AES Cipher mode select: OFB */ +#define AESCM__CFB (0x0060) /* AES Cipher mode select: CFB */ + + +/* AESACTL1 Control Bits */ +#define AESBLKCNT0 (0x0001) /* AES Cipher Block Counter Bit: 0 */ +#define AESBLKCNT1 (0x0002) /* AES Cipher Block Counter Bit: 1 */ +#define AESBLKCNT2 (0x0004) /* AES Cipher Block Counter Bit: 2 */ +#define AESBLKCNT3 (0x0008) /* AES Cipher Block Counter Bit: 3 */ +#define AESBLKCNT4 (0x0010) /* AES Cipher Block Counter Bit: 4 */ +#define AESBLKCNT5 (0x0020) /* AES Cipher Block Counter Bit: 5 */ +#define AESBLKCNT6 (0x0040) /* AES Cipher Block Counter Bit: 6 */ +#define AESBLKCNT7 (0x0080) /* AES Cipher Block Counter Bit: 7 */ + +/* AESACTL1 Control Bits */ +#define AESBLKCNT0_L (0x0001) /* AES Cipher Block Counter Bit: 0 */ +#define AESBLKCNT1_L (0x0002) /* AES Cipher Block Counter Bit: 1 */ +#define AESBLKCNT2_L (0x0004) /* AES Cipher Block Counter Bit: 2 */ +#define AESBLKCNT3_L (0x0008) /* AES Cipher Block Counter Bit: 3 */ +#define AESBLKCNT4_L (0x0010) /* AES Cipher Block Counter Bit: 4 */ +#define AESBLKCNT5_L (0x0020) /* AES Cipher Block Counter Bit: 5 */ +#define AESBLKCNT6_L (0x0040) /* AES Cipher Block Counter Bit: 6 */ +#define AESBLKCNT7_L (0x0080) /* AES Cipher Block Counter Bit: 7 */ + + +/* AESASTAT Control Bits */ +#define AESBUSY (0x0001) /* AES Busy */ +#define AESKEYWR (0x0002) /* AES All 16 bytes written to AESAKEY */ +#define AESDINWR (0x0004) /* AES All 16 bytes written to AESADIN */ +#define AESDOUTRD (0x0008) /* AES All 16 bytes read from AESADOUT */ +#define AESKEYCNT0 (0x0010) /* AES Bytes written via AESAKEY Bit: 0 */ +#define AESKEYCNT1 (0x0020) /* AES Bytes written via AESAKEY Bit: 1 */ +#define AESKEYCNT2 (0x0040) /* AES Bytes written via AESAKEY Bit: 2 */ +#define AESKEYCNT3 (0x0080) /* AES Bytes written via AESAKEY Bit: 3 */ +#define AESDINCNT0 (0x0100) /* AES Bytes written via AESADIN Bit: 0 */ +#define AESDINCNT1 (0x0200) /* AES Bytes written via AESADIN Bit: 1 */ +#define AESDINCNT2 (0x0400) /* AES Bytes written via AESADIN Bit: 2 */ +#define AESDINCNT3 (0x0800) /* AES Bytes written via AESADIN Bit: 3 */ +#define AESDOUTCNT0 (0x1000) /* AES Bytes read via AESADOUT Bit: 0 */ +#define AESDOUTCNT1 (0x2000) /* AES Bytes read via AESADOUT Bit: 1 */ +#define AESDOUTCNT2 (0x4000) /* AES Bytes read via AESADOUT Bit: 2 */ +#define AESDOUTCNT3 (0x8000) /* AES Bytes read via AESADOUT Bit: 3 */ + +/* AESASTAT Control Bits */ +#define AESBUSY_L (0x0001) /* AES Busy */ +#define AESKEYWR_L (0x0002) /* AES All 16 bytes written to AESAKEY */ +#define AESDINWR_L (0x0004) /* AES All 16 bytes written to AESADIN */ +#define AESDOUTRD_L (0x0008) /* AES All 16 bytes read from AESADOUT */ +#define AESKEYCNT0_L (0x0010) /* AES Bytes written via AESAKEY Bit: 0 */ +#define AESKEYCNT1_L (0x0020) /* AES Bytes written via AESAKEY Bit: 1 */ +#define AESKEYCNT2_L (0x0040) /* AES Bytes written via AESAKEY Bit: 2 */ +#define AESKEYCNT3_L (0x0080) /* AES Bytes written via AESAKEY Bit: 3 */ + +/* AESASTAT Control Bits */ +#define AESDINCNT0_H (0x0001) /* AES Bytes written via AESADIN Bit: 0 */ +#define AESDINCNT1_H (0x0002) /* AES Bytes written via AESADIN Bit: 1 */ +#define AESDINCNT2_H (0x0004) /* AES Bytes written via AESADIN Bit: 2 */ +#define AESDINCNT3_H (0x0008) /* AES Bytes written via AESADIN Bit: 3 */ +#define AESDOUTCNT0_H (0x0010) /* AES Bytes read via AESADOUT Bit: 0 */ +#define AESDOUTCNT1_H (0x0020) /* AES Bytes read via AESADOUT Bit: 1 */ +#define AESDOUTCNT2_H (0x0040) /* AES Bytes read via AESADOUT Bit: 2 */ +#define AESDOUTCNT3_H (0x0080) /* AES Bytes read via AESADOUT Bit: 3 */ + +/************************************************************ +* Capacitive_Touch_IO 0 +************************************************************/ + +#define CAPTIO0CTL 0x043E /* Capacitive_Touch_IO 0 control register */ +#define CAPSIO0CTL CAPTIO0CTL /* legacy define */ + +/************************************************************ +* Capacitive_Touch_IO 1 +************************************************************/ + +#define CAPTIO1CTL 0x047E /* Capacitive_Touch_IO 1 control register */ + +#define CAPSIO1CTL CAPTIO1CTL /* legacy define */ + +/* CAPTIOxCTL Control Bits */ +#define CAPTIOPISEL0 (0x0002) /* CapTouchIO Pin Select Bit: 0 */ +#define CAPTIOPISEL1 (0x0004) /* CapTouchIO Pin Select Bit: 1 */ +#define CAPTIOPISEL2 (0x0008) /* CapTouchIO Pin Select Bit: 2 */ +#define CAPTIOPOSEL0 (0x0010) /* CapTouchIO Port Select Bit: 0 */ +#define CAPTIOPOSEL1 (0x0020) /* CapTouchIO Port Select Bit: 1 */ +#define CAPTIOPOSEL2 (0x0040) /* CapTouchIO Port Select Bit: 2 */ +#define CAPTIOPOSEL3 (0x0080) /* CapTouchIO Port Select Bit: 3 */ +#define CAPTIOEN (0x0100) /* CapTouchIO Enable */ +#define CAPTIO (0x0200) /* CapTouchIO state */ + +/* CAPTIOxCTL Control Bits */ +#define CAPTIOPISEL0_L (0x0002) /* CapTouchIO Pin Select Bit: 0 */ +#define CAPTIOPISEL1_L (0x0004) /* CapTouchIO Pin Select Bit: 1 */ +#define CAPTIOPISEL2_L (0x0008) /* CapTouchIO Pin Select Bit: 2 */ +#define CAPTIOPOSEL0_L (0x0010) /* CapTouchIO Port Select Bit: 0 */ +#define CAPTIOPOSEL1_L (0x0020) /* CapTouchIO Port Select Bit: 1 */ +#define CAPTIOPOSEL2_L (0x0040) /* CapTouchIO Port Select Bit: 2 */ +#define CAPTIOPOSEL3_L (0x0080) /* CapTouchIO Port Select Bit: 3 */ + +/* CAPTIOxCTL Control Bits */ +#define CAPTIOEN_H (0x0001) /* CapTouchIO Enable */ +#define CAPTIO_H (0x0002) /* CapTouchIO state */ + +/* Legacy defines */ +#define CAPSIOPISEL0 (0x0002) /* CapTouchIO Pin Select Bit: 0 */ +#define CAPSIOPISEL1 (0x0004) /* CapTouchIO Pin Select Bit: 1 */ +#define CAPSIOPISEL2 (0x0008) /* CapTouchIO Pin Select Bit: 2 */ +#define CAPSIOPOSEL0 (0x0010) /* CapTouchIO Port Select Bit: 0 */ +#define CAPSIOPOSEL1 (0x0020) /* CapTouchIO Port Select Bit: 1 */ +#define CAPSIOPOSEL2 (0x0040) /* CapTouchIO Port Select Bit: 2 */ +#define CAPSIOPOSEL3 (0x0080) /* CapTouchIO Port Select Bit: 3 */ +#define CAPSIOEN (0x0100) /* CapTouchIO Enable */ +#define CAPSIO (0x0200) /* CapTouchIO state */ + +/************************************************************ +* Comparator E +************************************************************/ + +#define CECTL0 0x08C0 /* Comparator E Control Register 0 */ +#define CECTL1 0x08C2 /* Comparator E Control Register 1 */ +#define CECTL2 0x08C4 /* Comparator E Control Register 2 */ +#define CECTL3 0x08C6 /* Comparator E Control Register 3 */ +#define CEINT 0x08CC /* Comparator E Interrupt Register */ +#define CEIV 0x08CE /* Comparator E Interrupt Vector Word */ + +/* CECTL0 Control Bits */ +#define CEIPSEL0 (0x0001) /* Comp. E Pos. Channel Input Select 0 */ +#define CEIPSEL1 (0x0002) /* Comp. E Pos. Channel Input Select 1 */ +#define CEIPSEL2 (0x0004) /* Comp. E Pos. Channel Input Select 2 */ +#define CEIPSEL3 (0x0008) /* Comp. E Pos. Channel Input Select 3 */ +//#define RESERVED (0x0010) /* Comp. E */ +//#define RESERVED (0x0020) /* Comp. E */ +//#define RESERVED (0x0040) /* Comp. E */ +#define CEIPEN (0x0080) /* Comp. E Pos. Channel Input Enable */ +#define CEIMSEL0 (0x0100) /* Comp. E Neg. Channel Input Select 0 */ +#define CEIMSEL1 (0x0200) /* Comp. E Neg. Channel Input Select 1 */ +#define CEIMSEL2 (0x0400) /* Comp. E Neg. Channel Input Select 2 */ +#define CEIMSEL3 (0x0800) /* Comp. E Neg. Channel Input Select 3 */ +//#define RESERVED (0x1000) /* Comp. E */ +//#define RESERVED (0x2000) /* Comp. E */ +//#define RESERVED (0x4000) /* Comp. E */ +#define CEIMEN (0x8000) /* Comp. E Neg. Channel Input Enable */ + +/* CECTL0 Control Bits */ +#define CEIPSEL0_L (0x0001) /* Comp. E Pos. Channel Input Select 0 */ +#define CEIPSEL1_L (0x0002) /* Comp. E Pos. Channel Input Select 1 */ +#define CEIPSEL2_L (0x0004) /* Comp. E Pos. Channel Input Select 2 */ +#define CEIPSEL3_L (0x0008) /* Comp. E Pos. Channel Input Select 3 */ +//#define RESERVED (0x0010) /* Comp. E */ +//#define RESERVED (0x0020) /* Comp. E */ +//#define RESERVED (0x0040) /* Comp. E */ +#define CEIPEN_L (0x0080) /* Comp. E Pos. Channel Input Enable */ +//#define RESERVED (0x1000) /* Comp. E */ +//#define RESERVED (0x2000) /* Comp. E */ +//#define RESERVED (0x4000) /* Comp. E */ + +/* CECTL0 Control Bits */ +//#define RESERVED (0x0010) /* Comp. E */ +//#define RESERVED (0x0020) /* Comp. E */ +//#define RESERVED (0x0040) /* Comp. E */ +#define CEIMSEL0_H (0x0001) /* Comp. E Neg. Channel Input Select 0 */ +#define CEIMSEL1_H (0x0002) /* Comp. E Neg. Channel Input Select 1 */ +#define CEIMSEL2_H (0x0004) /* Comp. E Neg. Channel Input Select 2 */ +#define CEIMSEL3_H (0x0008) /* Comp. E Neg. Channel Input Select 3 */ +//#define RESERVED (0x1000) /* Comp. E */ +//#define RESERVED (0x2000) /* Comp. E */ +//#define RESERVED (0x4000) /* Comp. E */ +#define CEIMEN_H (0x0080) /* Comp. E Neg. Channel Input Enable */ + +#define CEIPSEL_0 (0x0000) /* Comp. E V+ terminal Input Select: Channel 0 */ +#define CEIPSEL_1 (0x0001) /* Comp. E V+ terminal Input Select: Channel 1 */ +#define CEIPSEL_2 (0x0002) /* Comp. E V+ terminal Input Select: Channel 2 */ +#define CEIPSEL_3 (0x0003) /* Comp. E V+ terminal Input Select: Channel 3 */ +#define CEIPSEL_4 (0x0004) /* Comp. E V+ terminal Input Select: Channel 4 */ +#define CEIPSEL_5 (0x0005) /* Comp. E V+ terminal Input Select: Channel 5 */ +#define CEIPSEL_6 (0x0006) /* Comp. E V+ terminal Input Select: Channel 6 */ +#define CEIPSEL_7 (0x0007) /* Comp. E V+ terminal Input Select: Channel 7 */ +#define CEIPSEL_8 (0x0008) /* Comp. E V+ terminal Input Select: Channel 8 */ +#define CEIPSEL_9 (0x0009) /* Comp. E V+ terminal Input Select: Channel 9 */ +#define CEIPSEL_10 (0x000A) /* Comp. E V+ terminal Input Select: Channel 10 */ +#define CEIPSEL_11 (0x000B) /* Comp. E V+ terminal Input Select: Channel 11 */ +#define CEIPSEL_12 (0x000C) /* Comp. E V+ terminal Input Select: Channel 12 */ +#define CEIPSEL_13 (0x000D) /* Comp. E V+ terminal Input Select: Channel 13 */ +#define CEIPSEL_14 (0x000E) /* Comp. E V+ terminal Input Select: Channel 14 */ +#define CEIPSEL_15 (0x000F) /* Comp. E V+ terminal Input Select: Channel 15 */ + +#define CEIMSEL_0 (0x0000) /* Comp. E V- Terminal Input Select: Channel 0 */ +#define CEIMSEL_1 (0x0100) /* Comp. E V- Terminal Input Select: Channel 1 */ +#define CEIMSEL_2 (0x0200) /* Comp. E V- Terminal Input Select: Channel 2 */ +#define CEIMSEL_3 (0x0300) /* Comp. E V- Terminal Input Select: Channel 3 */ +#define CEIMSEL_4 (0x0400) /* Comp. E V- Terminal Input Select: Channel 4 */ +#define CEIMSEL_5 (0x0500) /* Comp. E V- Terminal Input Select: Channel 5 */ +#define CEIMSEL_6 (0x0600) /* Comp. E V- Terminal Input Select: Channel 6 */ +#define CEIMSEL_7 (0x0700) /* Comp. E V- Terminal Input Select: Channel 7 */ +#define CEIMSEL_8 (0x0800) /* Comp. E V- terminal Input Select: Channel 8 */ +#define CEIMSEL_9 (0x0900) /* Comp. E V- terminal Input Select: Channel 9 */ +#define CEIMSEL_10 (0x0A00) /* Comp. E V- terminal Input Select: Channel 10 */ +#define CEIMSEL_11 (0x0B00) /* Comp. E V- terminal Input Select: Channel 11 */ +#define CEIMSEL_12 (0x0C00) /* Comp. E V- terminal Input Select: Channel 12 */ +#define CEIMSEL_13 (0x0D00) /* Comp. E V- terminal Input Select: Channel 13 */ +#define CEIMSEL_14 (0x0E00) /* Comp. E V- terminal Input Select: Channel 14 */ +#define CEIMSEL_15 (0x0F00) /* Comp. E V- terminal Input Select: Channel 15 */ + +/* CECTL1 Control Bits */ +#define CEOUT (0x0001) /* Comp. E Output */ +#define CEOUTPOL (0x0002) /* Comp. E Output Polarity */ +#define CEF (0x0004) /* Comp. E Enable Output Filter */ +#define CEIES (0x0008) /* Comp. E Interrupt Edge Select */ +#define CESHORT (0x0010) /* Comp. E Input Short */ +#define CEEX (0x0020) /* Comp. E Exchange Inputs */ +#define CEFDLY0 (0x0040) /* Comp. E Filter delay Bit 0 */ +#define CEFDLY1 (0x0080) /* Comp. E Filter delay Bit 1 */ +#define CEPWRMD0 (0x0100) /* Comp. E Power mode Bit 0 */ +#define CEPWRMD1 (0x0200) /* Comp. E Power mode Bit 1 */ +#define CEON (0x0400) /* Comp. E enable */ +#define CEMRVL (0x0800) /* Comp. E CEMRV Level */ +#define CEMRVS (0x1000) /* Comp. E Output selects between VREF0 or VREF1*/ +//#define RESERVED (0x2000) /* Comp. E */ +//#define RESERVED (0x4000) /* Comp. E */ +//#define RESERVED (0x8000) /* Comp. E */ + +/* CECTL1 Control Bits */ +#define CEOUT_L (0x0001) /* Comp. E Output */ +#define CEOUTPOL_L (0x0002) /* Comp. E Output Polarity */ +#define CEF_L (0x0004) /* Comp. E Enable Output Filter */ +#define CEIES_L (0x0008) /* Comp. E Interrupt Edge Select */ +#define CESHORT_L (0x0010) /* Comp. E Input Short */ +#define CEEX_L (0x0020) /* Comp. E Exchange Inputs */ +#define CEFDLY0_L (0x0040) /* Comp. E Filter delay Bit 0 */ +#define CEFDLY1_L (0x0080) /* Comp. E Filter delay Bit 1 */ +//#define RESERVED (0x2000) /* Comp. E */ +//#define RESERVED (0x4000) /* Comp. E */ +//#define RESERVED (0x8000) /* Comp. E */ + +/* CECTL1 Control Bits */ +#define CEPWRMD0_H (0x0001) /* Comp. E Power mode Bit 0 */ +#define CEPWRMD1_H (0x0002) /* Comp. E Power mode Bit 1 */ +#define CEON_H (0x0004) /* Comp. E enable */ +#define CEMRVL_H (0x0008) /* Comp. E CEMRV Level */ +#define CEMRVS_H (0x0010) /* Comp. E Output selects between VREF0 or VREF1*/ +//#define RESERVED (0x2000) /* Comp. E */ +//#define RESERVED (0x4000) /* Comp. E */ +//#define RESERVED (0x8000) /* Comp. E */ + +#define CEPWRMD_0 (0x0000) /* Comp. E Power mode 0 */ +#define CEPWRMD_1 (0x0100) /* Comp. E Power mode 1 */ +#define CEPWRMD_2 (0x0200) /* Comp. E Power mode 2 */ +#define CEPWRMD_3 (0x0300) /* Comp. E Power mode 3*/ + +#define CEFDLY_0 (0x0000) /* Comp. E Filter delay 0 : 450ns */ +#define CEFDLY_1 (0x0040) /* Comp. E Filter delay 1 : 900ns */ +#define CEFDLY_2 (0x0080) /* Comp. E Filter delay 2 : 1800ns */ +#define CEFDLY_3 (0x00C0) /* Comp. E Filter delay 3 : 3600ns */ + + +/* CECTL2 Control Bits */ +#define CEREF00 (0x0001) /* Comp. E Reference 0 Resistor Select Bit : 0 */ +#define CEREF01 (0x0002) /* Comp. E Reference 0 Resistor Select Bit : 1 */ +#define CEREF02 (0x0004) /* Comp. E Reference 0 Resistor Select Bit : 2 */ +#define CEREF03 (0x0008) /* Comp. E Reference 0 Resistor Select Bit : 3 */ +#define CEREF04 (0x0010) /* Comp. E Reference 0 Resistor Select Bit : 4 */ +#define CERSEL (0x0020) /* Comp. E Reference select */ +#define CERS0 (0x0040) /* Comp. E Reference Source Bit : 0 */ +#define CERS1 (0x0080) /* Comp. E Reference Source Bit : 1 */ +#define CEREF10 (0x0100) /* Comp. E Reference 1 Resistor Select Bit : 0 */ +#define CEREF11 (0x0200) /* Comp. E Reference 1 Resistor Select Bit : 1 */ +#define CEREF12 (0x0400) /* Comp. E Reference 1 Resistor Select Bit : 2 */ +#define CEREF13 (0x0800) /* Comp. E Reference 1 Resistor Select Bit : 3 */ +#define CEREF14 (0x1000) /* Comp. E Reference 1 Resistor Select Bit : 4 */ +#define CEREFL0 (0x2000) /* Comp. E Reference voltage level Bit : 0 */ +#define CEREFL1 (0x4000) /* Comp. E Reference voltage level Bit : 1 */ +#define CEREFACC (0x8000) /* Comp. E Reference Accuracy */ + +/* CECTL2 Control Bits */ +#define CEREF00_L (0x0001) /* Comp. E Reference 0 Resistor Select Bit : 0 */ +#define CEREF01_L (0x0002) /* Comp. E Reference 0 Resistor Select Bit : 1 */ +#define CEREF02_L (0x0004) /* Comp. E Reference 0 Resistor Select Bit : 2 */ +#define CEREF03_L (0x0008) /* Comp. E Reference 0 Resistor Select Bit : 3 */ +#define CEREF04_L (0x0010) /* Comp. E Reference 0 Resistor Select Bit : 4 */ +#define CERSEL_L (0x0020) /* Comp. E Reference select */ +#define CERS0_L (0x0040) /* Comp. E Reference Source Bit : 0 */ +#define CERS1_L (0x0080) /* Comp. E Reference Source Bit : 1 */ + +/* CECTL2 Control Bits */ +#define CEREF10_H (0x0001) /* Comp. E Reference 1 Resistor Select Bit : 0 */ +#define CEREF11_H (0x0002) /* Comp. E Reference 1 Resistor Select Bit : 1 */ +#define CEREF12_H (0x0004) /* Comp. E Reference 1 Resistor Select Bit : 2 */ +#define CEREF13_H (0x0008) /* Comp. E Reference 1 Resistor Select Bit : 3 */ +#define CEREF14_H (0x0010) /* Comp. E Reference 1 Resistor Select Bit : 4 */ +#define CEREFL0_H (0x0020) /* Comp. E Reference voltage level Bit : 0 */ +#define CEREFL1_H (0x0040) /* Comp. E Reference voltage level Bit : 1 */ +#define CEREFACC_H (0x0080) /* Comp. E Reference Accuracy */ + +#define CEREF0_0 (0x0000) /* Comp. E Int. Ref.0 Select 0 : 1/32 */ +#define CEREF0_1 (0x0001) /* Comp. E Int. Ref.0 Select 1 : 2/32 */ +#define CEREF0_2 (0x0002) /* Comp. E Int. Ref.0 Select 2 : 3/32 */ +#define CEREF0_3 (0x0003) /* Comp. E Int. Ref.0 Select 3 : 4/32 */ +#define CEREF0_4 (0x0004) /* Comp. E Int. Ref.0 Select 4 : 5/32 */ +#define CEREF0_5 (0x0005) /* Comp. E Int. Ref.0 Select 5 : 6/32 */ +#define CEREF0_6 (0x0006) /* Comp. E Int. Ref.0 Select 6 : 7/32 */ +#define CEREF0_7 (0x0007) /* Comp. E Int. Ref.0 Select 7 : 8/32 */ +#define CEREF0_8 (0x0008) /* Comp. E Int. Ref.0 Select 0 : 9/32 */ +#define CEREF0_9 (0x0009) /* Comp. E Int. Ref.0 Select 1 : 10/32 */ +#define CEREF0_10 (0x000A) /* Comp. E Int. Ref.0 Select 2 : 11/32 */ +#define CEREF0_11 (0x000B) /* Comp. E Int. Ref.0 Select 3 : 12/32 */ +#define CEREF0_12 (0x000C) /* Comp. E Int. Ref.0 Select 4 : 13/32 */ +#define CEREF0_13 (0x000D) /* Comp. E Int. Ref.0 Select 5 : 14/32 */ +#define CEREF0_14 (0x000E) /* Comp. E Int. Ref.0 Select 6 : 15/32 */ +#define CEREF0_15 (0x000F) /* Comp. E Int. Ref.0 Select 7 : 16/32 */ +#define CEREF0_16 (0x0010) /* Comp. E Int. Ref.0 Select 0 : 17/32 */ +#define CEREF0_17 (0x0011) /* Comp. E Int. Ref.0 Select 1 : 18/32 */ +#define CEREF0_18 (0x0012) /* Comp. E Int. Ref.0 Select 2 : 19/32 */ +#define CEREF0_19 (0x0013) /* Comp. E Int. Ref.0 Select 3 : 20/32 */ +#define CEREF0_20 (0x0014) /* Comp. E Int. Ref.0 Select 4 : 21/32 */ +#define CEREF0_21 (0x0015) /* Comp. E Int. Ref.0 Select 5 : 22/32 */ +#define CEREF0_22 (0x0016) /* Comp. E Int. Ref.0 Select 6 : 23/32 */ +#define CEREF0_23 (0x0017) /* Comp. E Int. Ref.0 Select 7 : 24/32 */ +#define CEREF0_24 (0x0018) /* Comp. E Int. Ref.0 Select 0 : 25/32 */ +#define CEREF0_25 (0x0019) /* Comp. E Int. Ref.0 Select 1 : 26/32 */ +#define CEREF0_26 (0x001A) /* Comp. E Int. Ref.0 Select 2 : 27/32 */ +#define CEREF0_27 (0x001B) /* Comp. E Int. Ref.0 Select 3 : 28/32 */ +#define CEREF0_28 (0x001C) /* Comp. E Int. Ref.0 Select 4 : 29/32 */ +#define CEREF0_29 (0x001D) /* Comp. E Int. Ref.0 Select 5 : 30/32 */ +#define CEREF0_30 (0x001E) /* Comp. E Int. Ref.0 Select 6 : 31/32 */ +#define CEREF0_31 (0x001F) /* Comp. E Int. Ref.0 Select 7 : 32/32 */ + +#define CERS_0 (0x0000) /* Comp. E Reference Source 0 : Off */ +#define CERS_1 (0x0040) /* Comp. E Reference Source 1 : Vcc */ +#define CERS_2 (0x0080) /* Comp. E Reference Source 2 : Shared Ref. */ +#define CERS_3 (0x00C0) /* Comp. E Reference Source 3 : Shared Ref. / Off */ + +#define CEREF1_0 (0x0000) /* Comp. E Int. Ref.1 Select 0 : 1/32 */ +#define CEREF1_1 (0x0100) /* Comp. E Int. Ref.1 Select 1 : 2/32 */ +#define CEREF1_2 (0x0200) /* Comp. E Int. Ref.1 Select 2 : 3/32 */ +#define CEREF1_3 (0x0300) /* Comp. E Int. Ref.1 Select 3 : 4/32 */ +#define CEREF1_4 (0x0400) /* Comp. E Int. Ref.1 Select 4 : 5/32 */ +#define CEREF1_5 (0x0500) /* Comp. E Int. Ref.1 Select 5 : 6/32 */ +#define CEREF1_6 (0x0600) /* Comp. E Int. Ref.1 Select 6 : 7/32 */ +#define CEREF1_7 (0x0700) /* Comp. E Int. Ref.1 Select 7 : 8/32 */ +#define CEREF1_8 (0x0800) /* Comp. E Int. Ref.1 Select 0 : 9/32 */ +#define CEREF1_9 (0x0900) /* Comp. E Int. Ref.1 Select 1 : 10/32 */ +#define CEREF1_10 (0x0A00) /* Comp. E Int. Ref.1 Select 2 : 11/32 */ +#define CEREF1_11 (0x0B00) /* Comp. E Int. Ref.1 Select 3 : 12/32 */ +#define CEREF1_12 (0x0C00) /* Comp. E Int. Ref.1 Select 4 : 13/32 */ +#define CEREF1_13 (0x0D00) /* Comp. E Int. Ref.1 Select 5 : 14/32 */ +#define CEREF1_14 (0x0E00) /* Comp. E Int. Ref.1 Select 6 : 15/32 */ +#define CEREF1_15 (0x0F00) /* Comp. E Int. Ref.1 Select 7 : 16/32 */ +#define CEREF1_16 (0x1000) /* Comp. E Int. Ref.1 Select 0 : 17/32 */ +#define CEREF1_17 (0x1100) /* Comp. E Int. Ref.1 Select 1 : 18/32 */ +#define CEREF1_18 (0x1200) /* Comp. E Int. Ref.1 Select 2 : 19/32 */ +#define CEREF1_19 (0x1300) /* Comp. E Int. Ref.1 Select 3 : 20/32 */ +#define CEREF1_20 (0x1400) /* Comp. E Int. Ref.1 Select 4 : 21/32 */ +#define CEREF1_21 (0x1500) /* Comp. E Int. Ref.1 Select 5 : 22/32 */ +#define CEREF1_22 (0x1600) /* Comp. E Int. Ref.1 Select 6 : 23/32 */ +#define CEREF1_23 (0x1700) /* Comp. E Int. Ref.1 Select 7 : 24/32 */ +#define CEREF1_24 (0x1800) /* Comp. E Int. Ref.1 Select 0 : 25/32 */ +#define CEREF1_25 (0x1900) /* Comp. E Int. Ref.1 Select 1 : 26/32 */ +#define CEREF1_26 (0x1A00) /* Comp. E Int. Ref.1 Select 2 : 27/32 */ +#define CEREF1_27 (0x1B00) /* Comp. E Int. Ref.1 Select 3 : 28/32 */ +#define CEREF1_28 (0x1C00) /* Comp. E Int. Ref.1 Select 4 : 29/32 */ +#define CEREF1_29 (0x1D00) /* Comp. E Int. Ref.1 Select 5 : 30/32 */ +#define CEREF1_30 (0x1E00) /* Comp. E Int. Ref.1 Select 6 : 31/32 */ +#define CEREF1_31 (0x1F00) /* Comp. E Int. Ref.1 Select 7 : 32/32 */ + +#define CEREFL_0 (0x0000) /* Comp. E Reference voltage level 0 : None */ +#define CEREFL_1 (0x2000) /* Comp. E Reference voltage level 1 : 1.2V */ +#define CEREFL_2 (0x4000) /* Comp. E Reference voltage level 2 : 2.0V */ +#define CEREFL_3 (0x6000) /* Comp. E Reference voltage level 3 : 2.5V */ + + +#define CEPD0 (0x0001) /* Comp. E Disable Input Buffer of Port Register .0 */ +#define CEPD1 (0x0002) /* Comp. E Disable Input Buffer of Port Register .1 */ +#define CEPD2 (0x0004) /* Comp. E Disable Input Buffer of Port Register .2 */ +#define CEPD3 (0x0008) /* Comp. E Disable Input Buffer of Port Register .3 */ +#define CEPD4 (0x0010) /* Comp. E Disable Input Buffer of Port Register .4 */ +#define CEPD5 (0x0020) /* Comp. E Disable Input Buffer of Port Register .5 */ +#define CEPD6 (0x0040) /* Comp. E Disable Input Buffer of Port Register .6 */ +#define CEPD7 (0x0080) /* Comp. E Disable Input Buffer of Port Register .7 */ +#define CEPD8 (0x0100) /* Comp. E Disable Input Buffer of Port Register .8 */ +#define CEPD9 (0x0200) /* Comp. E Disable Input Buffer of Port Register .9 */ +#define CEPD10 (0x0400) /* Comp. E Disable Input Buffer of Port Register .10 */ +#define CEPD11 (0x0800) /* Comp. E Disable Input Buffer of Port Register .11 */ +#define CEPD12 (0x1000) /* Comp. E Disable Input Buffer of Port Register .12 */ +#define CEPD13 (0x2000) /* Comp. E Disable Input Buffer of Port Register .13 */ +#define CEPD14 (0x4000) /* Comp. E Disable Input Buffer of Port Register .14 */ +#define CEPD15 (0x8000) /* Comp. E Disable Input Buffer of Port Register .15 */ + +#define CEPD0_L (0x0001) /* Comp. E Disable Input Buffer of Port Register .0 */ +#define CEPD1_L (0x0002) /* Comp. E Disable Input Buffer of Port Register .1 */ +#define CEPD2_L (0x0004) /* Comp. E Disable Input Buffer of Port Register .2 */ +#define CEPD3_L (0x0008) /* Comp. E Disable Input Buffer of Port Register .3 */ +#define CEPD4_L (0x0010) /* Comp. E Disable Input Buffer of Port Register .4 */ +#define CEPD5_L (0x0020) /* Comp. E Disable Input Buffer of Port Register .5 */ +#define CEPD6_L (0x0040) /* Comp. E Disable Input Buffer of Port Register .6 */ +#define CEPD7_L (0x0080) /* Comp. E Disable Input Buffer of Port Register .7 */ + +#define CEPD8_H (0x0001) /* Comp. E Disable Input Buffer of Port Register .8 */ +#define CEPD9_H (0x0002) /* Comp. E Disable Input Buffer of Port Register .9 */ +#define CEPD10_H (0x0004) /* Comp. E Disable Input Buffer of Port Register .10 */ +#define CEPD11_H (0x0008) /* Comp. E Disable Input Buffer of Port Register .11 */ +#define CEPD12_H (0x0010) /* Comp. E Disable Input Buffer of Port Register .12 */ +#define CEPD13_H (0x0020) /* Comp. E Disable Input Buffer of Port Register .13 */ +#define CEPD14_H (0x0040) /* Comp. E Disable Input Buffer of Port Register .14 */ +#define CEPD15_H (0x0080) /* Comp. E Disable Input Buffer of Port Register .15 */ + + +/* CEINT Control Bits */ +#define CEIFG (0x0001) /* Comp. E Interrupt Flag */ +#define CEIIFG (0x0002) /* Comp. E Interrupt Flag Inverted Polarity */ +//#define RESERVED (0x0004) /* Comp. E */ +//#define RESERVED (0x0008) /* Comp. E */ +#define CERDYIFG (0x0010) /* Comp. E Comparator_E ready interrupt flag */ +//#define RESERVED (0x0020) /* Comp. E */ +//#define RESERVED (0x0040) /* Comp. E */ +//#define RESERVED (0x0080) /* Comp. E */ +#define CEIE (0x0100) /* Comp. E Interrupt Enable */ +#define CEIIE (0x0200) /* Comp. E Interrupt Enable Inverted Polarity */ +//#define RESERVED (0x0400) /* Comp. E */ +//#define RESERVED (0x0800) /* Comp. E */ +#define CERDYIE (0x1000) /* Comp. E Comparator_E ready interrupt enable */ +//#define RESERVED (0x2000) /* Comp. E */ +//#define RESERVED (0x4000) /* Comp. E */ +//#define RESERVED (0x8000) /* Comp. E */ + +/* CEINT Control Bits */ +#define CEIFG_L (0x0001) /* Comp. E Interrupt Flag */ +#define CEIIFG_L (0x0002) /* Comp. E Interrupt Flag Inverted Polarity */ +//#define RESERVED (0x0004) /* Comp. E */ +//#define RESERVED (0x0008) /* Comp. E */ +#define CERDYIFG_L (0x0010) /* Comp. E Comparator_E ready interrupt flag */ +//#define RESERVED (0x0020) /* Comp. E */ +//#define RESERVED (0x0040) /* Comp. E */ +//#define RESERVED (0x0080) /* Comp. E */ +//#define RESERVED (0x0400) /* Comp. E */ +//#define RESERVED (0x0800) /* Comp. E */ +//#define RESERVED (0x2000) /* Comp. E */ +//#define RESERVED (0x4000) /* Comp. E */ +//#define RESERVED (0x8000) /* Comp. E */ + +/* CEINT Control Bits */ +//#define RESERVED (0x0004) /* Comp. E */ +//#define RESERVED (0x0008) /* Comp. E */ +//#define RESERVED (0x0020) /* Comp. E */ +//#define RESERVED (0x0040) /* Comp. E */ +//#define RESERVED (0x0080) /* Comp. E */ +#define CEIE_H (0x0001) /* Comp. E Interrupt Enable */ +#define CEIIE_H (0x0002) /* Comp. E Interrupt Enable Inverted Polarity */ +//#define RESERVED (0x0400) /* Comp. E */ +//#define RESERVED (0x0800) /* Comp. E */ +#define CERDYIE_H (0x0010) /* Comp. E Comparator_E ready interrupt enable */ +//#define RESERVED (0x2000) /* Comp. E */ +//#define RESERVED (0x4000) /* Comp. E */ +//#define RESERVED (0x8000) /* Comp. E */ + +/* CEIV Definitions */ +#define CEIV_NONE (0x0000) /* No Interrupt pending */ +#define CEIV_CEIFG (0x0002) /* CEIFG */ +#define CEIV_CEIIFG (0x0004) /* CEIIFG */ +#define CEIV_CERDYIFG (0x000A) /* CERDYIFG */ + +/************************************************************* +* CRC Module +*************************************************************/ + +#define CRCDI 0x0150 /* CRC Data In Register */ +#define CRCDIRB 0x0152 /* CRC data in reverse byte Register */ +#define CRCINIRES 0x0154 /* CRC Initialisation Register and Result Register */ +#define CRCRESR 0x0156 /* CRC reverse result Register */ + +/************************************************************ +* CLOCK SYSTEM +************************************************************/ + +#define CSCTL0 0x0160 /* CS Control Register 0 */ +#define CSCTL1 0x0162 /* CS Control Register 1 */ +#define CSCTL2 0x0164 /* CS Control Register 2 */ +#define CSCTL3 0x0166 /* CS Control Register 3 */ +#define CSCTL4 0x0168 /* CS Control Register 4 */ +#define CSCTL5 0x016A /* CS Control Register 5 */ +#define CSCTL6 0x016C /* CS Control Register 6 */ + +/* CSCTL0 Control Bits */ + +#define CSKEY (0xA500) /* CS Password */ +#define CSKEY_H (0xA5) /* CS Password for high byte access */ + +/* CSCTL1 Control Bits */ +#define DCOFSEL0 (0x0002) /* DCO frequency select Bit: 0 */ +#define DCOFSEL1 (0x0004) /* DCO frequency select Bit: 1 */ +#define DCOFSEL2 (0x0008) /* DCO frequency select Bit: 2 */ +#define DCORSEL (0x0040) /* DCO range select. */ + +/* CSCTL1 Control Bits */ +#define DCOFSEL0_L (0x0002) /* DCO frequency select Bit: 0 */ +#define DCOFSEL1_L (0x0004) /* DCO frequency select Bit: 1 */ +#define DCOFSEL2_L (0x0008) /* DCO frequency select Bit: 2 */ +#define DCORSEL_L (0x0040) /* DCO range select. */ + + +#define DCOFSEL_0 (0x0000) /* DCO frequency select: 0 */ +#define DCOFSEL_1 (0x0002) /* DCO frequency select: 1 */ +#define DCOFSEL_2 (0x0004) /* DCO frequency select: 2 */ +#define DCOFSEL_3 (0x0006) /* DCO frequency select: 3 */ +#define DCOFSEL_4 (0x0008) /* DCO frequency select: 4 */ +#define DCOFSEL_5 (0x000A) /* DCO frequency select: 5 */ +#define DCOFSEL_6 (0x000C) /* DCO frequency select: 6 */ +#define DCOFSEL_7 (0x000E) /* DCO frequency select: 7 */ + + +/* CSCTL2 Control Bits */ +#define SELM0 (0x0001) /* MCLK Source Select Bit: 0 */ +#define SELM1 (0x0002) /* MCLK Source Select Bit: 1 */ +#define SELM2 (0x0004) /* MCLK Source Select Bit: 2 */ +//#define RESERVED (0x0004) /* RESERVED */ +//#define RESERVED (0x0008) /* RESERVED */ +#define SELS0 (0x0010) /* SMCLK Source Select Bit: 0 */ +#define SELS1 (0x0020) /* SMCLK Source Select Bit: 1 */ +#define SELS2 (0x0040) /* SMCLK Source Select Bit: 2 */ +//#define RESERVED (0x0040) /* RESERVED */ +//#define RESERVED (0x0080) /* RESERVED */ +#define SELA0 (0x0100) /* ACLK Source Select Bit: 0 */ +#define SELA1 (0x0200) /* ACLK Source Select Bit: 1 */ +#define SELA2 (0x0400) /* ACLK Source Select Bit: 2 */ +//#define RESERVED (0x0400) /* RESERVED */ +//#define RESERVED (0x0800) /* RESERVED */ +//#define RESERVED (0x1000) /* RESERVED */ +//#define RESERVED (0x2000) /* RESERVED */ +//#define RESERVED (0x4000) /* RESERVED */ +//#define RESERVED (0x8000) /* RESERVED */ + +/* CSCTL2 Control Bits */ +#define SELM0_L (0x0001) /* MCLK Source Select Bit: 0 */ +#define SELM1_L (0x0002) /* MCLK Source Select Bit: 1 */ +#define SELM2_L (0x0004) /* MCLK Source Select Bit: 2 */ +//#define RESERVED (0x0004) /* RESERVED */ +//#define RESERVED (0x0008) /* RESERVED */ +#define SELS0_L (0x0010) /* SMCLK Source Select Bit: 0 */ +#define SELS1_L (0x0020) /* SMCLK Source Select Bit: 1 */ +#define SELS2_L (0x0040) /* SMCLK Source Select Bit: 2 */ +//#define RESERVED (0x0040) /* RESERVED */ +//#define RESERVED (0x0080) /* RESERVED */ +//#define RESERVED (0x0400) /* RESERVED */ +//#define RESERVED (0x0800) /* RESERVED */ +//#define RESERVED (0x1000) /* RESERVED */ +//#define RESERVED (0x2000) /* RESERVED */ +//#define RESERVED (0x4000) /* RESERVED */ +//#define RESERVED (0x8000) /* RESERVED */ + +/* CSCTL2 Control Bits */ +//#define RESERVED (0x0004) /* RESERVED */ +//#define RESERVED (0x0008) /* RESERVED */ +//#define RESERVED (0x0040) /* RESERVED */ +//#define RESERVED (0x0080) /* RESERVED */ +#define SELA0_H (0x0001) /* ACLK Source Select Bit: 0 */ +#define SELA1_H (0x0002) /* ACLK Source Select Bit: 1 */ +#define SELA2_H (0x0004) /* ACLK Source Select Bit: 2 */ +//#define RESERVED (0x0400) /* RESERVED */ +//#define RESERVED (0x0800) /* RESERVED */ +//#define RESERVED (0x1000) /* RESERVED */ +//#define RESERVED (0x2000) /* RESERVED */ +//#define RESERVED (0x4000) /* RESERVED */ +//#define RESERVED (0x8000) /* RESERVED */ + +#define SELM_0 (0x0000) /* MCLK Source Select 0 */ +#define SELM_1 (0x0001) /* MCLK Source Select 1 */ +#define SELM_2 (0x0002) /* MCLK Source Select 2 */ +#define SELM_3 (0x0003) /* MCLK Source Select 3 */ +#define SELM_4 (0x0004) /* MCLK Source Select 4 */ +#define SELM_5 (0x0005) /* MCLK Source Select 5 */ +#define SELM_6 (0x0006) /* MCLK Source Select 6 */ +#define SELM_7 (0x0007) /* MCLK Source Select 7 */ +#define SELM__LFXTCLK (0x0000) /* MCLK Source Select LFXTCLK */ +#define SELM__VLOCLK (0x0001) /* MCLK Source Select VLOCLK */ +#define SELM__LFMODCLK (0x0002) /* MCLK Source Select LFMODOSC */ +#define SELM__LFMODOSC (0x0002) /* MCLK Source Select LFMODOSC (legacy) */ +#define SELM__DCOCLK (0x0003) /* MCLK Source Select DCOCLK */ +#define SELM__MODCLK (0x0004) /* MCLK Source Select MODOSC */ +#define SELM__MODOSC (0x0004) /* MCLK Source Select MODOSC (legacy) */ +#define SELM__HFXTCLK (0x0005) /* MCLK Source Select HFXTCLK */ + +#define SELS_0 (0x0000) /* SMCLK Source Select 0 */ +#define SELS_1 (0x0010) /* SMCLK Source Select 1 */ +#define SELS_2 (0x0020) /* SMCLK Source Select 2 */ +#define SELS_3 (0x0030) /* SMCLK Source Select 3 */ +#define SELS_4 (0x0040) /* SMCLK Source Select 4 */ +#define SELS_5 (0x0050) /* SMCLK Source Select 5 */ +#define SELS_6 (0x0060) /* SMCLK Source Select 6 */ +#define SELS_7 (0x0070) /* SMCLK Source Select 7 */ +#define SELS__LFXTCLK (0x0000) /* SMCLK Source Select LFXTCLK */ +#define SELS__VLOCLK (0x0010) /* SMCLK Source Select VLOCLK */ +#define SELS__LFMODCLK (0x0020) /* SMCLK Source Select LFMODOSC */ +#define SELS__LFMODOSC (0x0020) /* SMCLK Source Select LFMODOSC (legacy) */ +#define SELS__DCOCLK (0x0030) /* SMCLK Source Select DCOCLK */ +#define SELS__MODCLK (0x0040) /* SMCLK Source Select MODOSC */ +#define SELS__MODOSC (0x0040) /* SMCLK Source Select MODOSC (legacy) */ +#define SELS__HFXTCLK (0x0050) /* SMCLK Source Select HFXTCLK */ + +#define SELA_0 (0x0000) /* ACLK Source Select 0 */ +#define SELA_1 (0x0100) /* ACLK Source Select 1 */ +#define SELA_2 (0x0200) /* ACLK Source Select 2 */ +#define SELA_3 (0x0300) /* ACLK Source Select 3 */ +#define SELA_4 (0x0400) /* ACLK Source Select 4 */ +#define SELA_5 (0x0500) /* ACLK Source Select 5 */ +#define SELA_6 (0x0600) /* ACLK Source Select 6 */ +#define SELA_7 (0x0700) /* ACLK Source Select 7 */ +#define SELA__LFXTCLK (0x0000) /* ACLK Source Select LFXTCLK */ +#define SELA__VLOCLK (0x0100) /* ACLK Source Select VLOCLK */ +#define SELA__LFMODCLK (0x0200) /* ACLK Source Select LFMODOSC */ +#define SELA__LFMODOSC (0x0200) /* ACLK Source Select LFMODOSC (legacy) */ + +/* CSCTL3 Control Bits */ +#define DIVM0 (0x0001) /* MCLK Divider Bit: 0 */ +#define DIVM1 (0x0002) /* MCLK Divider Bit: 1 */ +#define DIVM2 (0x0004) /* MCLK Divider Bit: 2 */ +//#define RESERVED (0x0004) /* RESERVED */ +//#define RESERVED (0x0008) /* RESERVED */ +#define DIVS0 (0x0010) /* SMCLK Divider Bit: 0 */ +#define DIVS1 (0x0020) /* SMCLK Divider Bit: 1 */ +#define DIVS2 (0x0040) /* SMCLK Divider Bit: 2 */ +//#define RESERVED (0x0040) /* RESERVED */ +//#define RESERVED (0x0080) /* RESERVED */ +#define DIVA0 (0x0100) /* ACLK Divider Bit: 0 */ +#define DIVA1 (0x0200) /* ACLK Divider Bit: 1 */ +#define DIVA2 (0x0400) /* ACLK Divider Bit: 2 */ +//#define RESERVED (0x0400) /* RESERVED */ +//#define RESERVED (0x0800) /* RESERVED */ +//#define RESERVED (0x1000) /* RESERVED */ +//#define RESERVED (0x2000) /* RESERVED */ +//#define RESERVED (0x4000) /* RESERVED */ +//#define RESERVED (0x8000) /* RESERVED */ + +/* CSCTL3 Control Bits */ +#define DIVM0_L (0x0001) /* MCLK Divider Bit: 0 */ +#define DIVM1_L (0x0002) /* MCLK Divider Bit: 1 */ +#define DIVM2_L (0x0004) /* MCLK Divider Bit: 2 */ +//#define RESERVED (0x0004) /* RESERVED */ +//#define RESERVED (0x0008) /* RESERVED */ +#define DIVS0_L (0x0010) /* SMCLK Divider Bit: 0 */ +#define DIVS1_L (0x0020) /* SMCLK Divider Bit: 1 */ +#define DIVS2_L (0x0040) /* SMCLK Divider Bit: 2 */ +//#define RESERVED (0x0040) /* RESERVED */ +//#define RESERVED (0x0080) /* RESERVED */ +//#define RESERVED (0x0400) /* RESERVED */ +//#define RESERVED (0x0800) /* RESERVED */ +//#define RESERVED (0x1000) /* RESERVED */ +//#define RESERVED (0x2000) /* RESERVED */ +//#define RESERVED (0x4000) /* RESERVED */ +//#define RESERVED (0x8000) /* RESERVED */ + +/* CSCTL3 Control Bits */ +//#define RESERVED (0x0004) /* RESERVED */ +//#define RESERVED (0x0008) /* RESERVED */ +//#define RESERVED (0x0040) /* RESERVED */ +//#define RESERVED (0x0080) /* RESERVED */ +#define DIVA0_H (0x0001) /* ACLK Divider Bit: 0 */ +#define DIVA1_H (0x0002) /* ACLK Divider Bit: 1 */ +#define DIVA2_H (0x0004) /* ACLK Divider Bit: 2 */ +//#define RESERVED (0x0400) /* RESERVED */ +//#define RESERVED (0x0800) /* RESERVED */ +//#define RESERVED (0x1000) /* RESERVED */ +//#define RESERVED (0x2000) /* RESERVED */ +//#define RESERVED (0x4000) /* RESERVED */ +//#define RESERVED (0x8000) /* RESERVED */ + +#define DIVM_0 (0x0000) /* MCLK Source Divider 0 */ +#define DIVM_1 (0x0001) /* MCLK Source Divider 1 */ +#define DIVM_2 (0x0002) /* MCLK Source Divider 2 */ +#define DIVM_3 (0x0003) /* MCLK Source Divider 3 */ +#define DIVM_4 (0x0004) /* MCLK Source Divider 4 */ +#define DIVM_5 (0x0005) /* MCLK Source Divider 5 */ +#define DIVM__1 (0x0000) /* MCLK Source Divider f(MCLK)/1 */ +#define DIVM__2 (0x0001) /* MCLK Source Divider f(MCLK)/2 */ +#define DIVM__4 (0x0002) /* MCLK Source Divider f(MCLK)/4 */ +#define DIVM__8 (0x0003) /* MCLK Source Divider f(MCLK)/8 */ +#define DIVM__16 (0x0004) /* MCLK Source Divider f(MCLK)/16 */ +#define DIVM__32 (0x0005) /* MCLK Source Divider f(MCLK)/32 */ + +#define DIVS_0 (0x0000) /* SMCLK Source Divider 0 */ +#define DIVS_1 (0x0010) /* SMCLK Source Divider 1 */ +#define DIVS_2 (0x0020) /* SMCLK Source Divider 2 */ +#define DIVS_3 (0x0030) /* SMCLK Source Divider 3 */ +#define DIVS_4 (0x0040) /* SMCLK Source Divider 4 */ +#define DIVS_5 (0x0050) /* SMCLK Source Divider 5 */ +#define DIVS__1 (0x0000) /* SMCLK Source Divider f(SMCLK)/1 */ +#define DIVS__2 (0x0010) /* SMCLK Source Divider f(SMCLK)/2 */ +#define DIVS__4 (0x0020) /* SMCLK Source Divider f(SMCLK)/4 */ +#define DIVS__8 (0x0030) /* SMCLK Source Divider f(SMCLK)/8 */ +#define DIVS__16 (0x0040) /* SMCLK Source Divider f(SMCLK)/16 */ +#define DIVS__32 (0x0050) /* SMCLK Source Divider f(SMCLK)/32 */ + +#define DIVA_0 (0x0000) /* ACLK Source Divider 0 */ +#define DIVA_1 (0x0100) /* ACLK Source Divider 1 */ +#define DIVA_2 (0x0200) /* ACLK Source Divider 2 */ +#define DIVA_3 (0x0300) /* ACLK Source Divider 3 */ +#define DIVA_4 (0x0400) /* ACLK Source Divider 4 */ +#define DIVA_5 (0x0500) /* ACLK Source Divider 5 */ +#define DIVA__1 (0x0000) /* ACLK Source Divider f(ACLK)/1 */ +#define DIVA__2 (0x0100) /* ACLK Source Divider f(ACLK)/2 */ +#define DIVA__4 (0x0200) /* ACLK Source Divider f(ACLK)/4 */ +#define DIVA__8 (0x0300) /* ACLK Source Divider f(ACLK)/8 */ +#define DIVA__16 (0x0400) /* ACLK Source Divider f(ACLK)/16 */ +#define DIVA__32 (0x0500) /* ACLK Source Divider f(ACLK)/32 */ + + +/* CSCTL4 Control Bits */ +#define LFXTOFF (0x0001) /* Low Frequency Oscillator (LFXT) disable */ +#define SMCLKOFF (0x0002) /* SMCLK Off */ +#define VLOOFF (0x0008) /* VLO Off */ +#define LFXTBYPASS (0x0010) /* LFXT bypass mode : 0: internal 1:sourced from external pin */ +#define LFXTDRIVE0 (0x0040) /* LFXT Drive Level mode Bit 0 */ +#define LFXTDRIVE1 (0x0080) /* LFXT Drive Level mode Bit 1 */ +#define HFXTOFF (0x0100) /* High Frequency Oscillator disable */ +#define HFFREQ0 (0x0400) /* HFXT frequency selection Bit 1 */ +#define HFFREQ1 (0x0800) /* HFXT frequency selection Bit 0 */ +#define HFXTBYPASS (0x1000) /* HFXT bypass mode : 0: internal 1:sourced from external pin */ +#define HFXTDRIVE0 (0x4000) /* HFXT Drive Level mode Bit 0 */ +#define HFXTDRIVE1 (0x8000) /* HFXT Drive Level mode Bit 1 */ + +/* CSCTL4 Control Bits */ +#define LFXTOFF_L (0x0001) /* Low Frequency Oscillator (LFXT) disable */ +#define SMCLKOFF_L (0x0002) /* SMCLK Off */ +#define VLOOFF_L (0x0008) /* VLO Off */ +#define LFXTBYPASS_L (0x0010) /* LFXT bypass mode : 0: internal 1:sourced from external pin */ +#define LFXTDRIVE0_L (0x0040) /* LFXT Drive Level mode Bit 0 */ +#define LFXTDRIVE1_L (0x0080) /* LFXT Drive Level mode Bit 1 */ + +/* CSCTL4 Control Bits */ +#define HFXTOFF_H (0x0001) /* High Frequency Oscillator disable */ +#define HFFREQ0_H (0x0004) /* HFXT frequency selection Bit 1 */ +#define HFFREQ1_H (0x0008) /* HFXT frequency selection Bit 0 */ +#define HFXTBYPASS_H (0x0010) /* HFXT bypass mode : 0: internal 1:sourced from external pin */ +#define HFXTDRIVE0_H (0x0040) /* HFXT Drive Level mode Bit 0 */ +#define HFXTDRIVE1_H (0x0080) /* HFXT Drive Level mode Bit 1 */ + +#define LFXTDRIVE_0 (0x0000) /* LFXT Drive Level mode: 0 */ +#define LFXTDRIVE_1 (0x0040) /* LFXT Drive Level mode: 1 */ +#define LFXTDRIVE_2 (0x0080) /* LFXT Drive Level mode: 2 */ +#define LFXTDRIVE_3 (0x00C0) /* LFXT Drive Level mode: 3 */ + +#define HFFREQ_0 (0x0000) /* HFXT frequency selection: 0 */ +#define HFFREQ_1 (0x0400) /* HFXT frequency selection: 1 */ +#define HFFREQ_2 (0x0800) /* HFXT frequency selection: 2 */ +#define HFFREQ_3 (0x0C00) /* HFXT frequency selection: 3 */ + +#define HFXTDRIVE_0 (0x0000) /* HFXT Drive Level mode: 0 */ +#define HFXTDRIVE_1 (0x4000) /* HFXT Drive Level mode: 1 */ +#define HFXTDRIVE_2 (0x8000) /* HFXT Drive Level mode: 2 */ +#define HFXTDRIVE_3 (0xC000) /* HFXT Drive Level mode: 3 */ + +/* CSCTL5 Control Bits */ +#define LFXTOFFG (0x0001) /* LFXT Low Frequency Oscillator Fault Flag */ +#define HFXTOFFG (0x0002) /* HFXT High Frequency Oscillator Fault Flag */ +#define ENSTFCNT1 (0x0040) /* Enable start counter for XT1 */ +#define ENSTFCNT2 (0x0080) /* Enable start counter for XT2 */ + +/* CSCTL5 Control Bits */ +#define LFXTOFFG_L (0x0001) /* LFXT Low Frequency Oscillator Fault Flag */ +#define HFXTOFFG_L (0x0002) /* HFXT High Frequency Oscillator Fault Flag */ +#define ENSTFCNT1_L (0x0040) /* Enable start counter for XT1 */ +#define ENSTFCNT2_L (0x0080) /* Enable start counter for XT2 */ + + +/* CSCTL6 Control Bits */ +#define ACLKREQEN (0x0001) /* ACLK Clock Request Enable */ +#define MCLKREQEN (0x0002) /* MCLK Clock Request Enable */ +#define SMCLKREQEN (0x0004) /* SMCLK Clock Request Enable */ +#define MODCLKREQEN (0x0008) /* MODOSC Clock Request Enable */ + +/* CSCTL6 Control Bits */ +#define ACLKREQEN_L (0x0001) /* ACLK Clock Request Enable */ +#define MCLKREQEN_L (0x0002) /* MCLK Clock Request Enable */ +#define SMCLKREQEN_L (0x0004) /* SMCLK Clock Request Enable */ +#define MODCLKREQEN_L (0x0008) /* MODOSC Clock Request Enable */ + + +/************************************************************ +* DMA_X +************************************************************/ + +#define DMACTL0 0x0500 /* DMA Module Control 0 */ +#define DMACTL1 0x0502 /* DMA Module Control 1 */ +#define DMACTL2 0x0504 /* DMA Module Control 2 */ +#define DMACTL3 0x0506 /* DMA Module Control 3 */ +#define DMACTL4 0x0508 /* DMA Module Control 4 */ +#define DMAIV 0x050E /* DMA Interrupt Vector Word */ + +#define DMA0CTL 0x0510 /* DMA Channel 0 Control */ +#define DMA0SA 0x0512 /* DMA Channel 0 Source Address */ +#define DMA0DA 0x0516 /* DMA Channel 0 Destination Address */ +#define DMA0SZ 0x051A /* DMA Channel 0 Transfer Size */ + +#define DMA1CTL 0x0520 /* DMA Channel 1 Control */ +#define DMA1SA 0x0522 /* DMA Channel 1 Source Address */ +#define DMA1DA 0x0526 /* DMA Channel 1 Destination Address */ +#define DMA1SZ 0x052A /* DMA Channel 1 Transfer Size */ + +#define DMA2CTL 0x0530 /* DMA Channel 2 Control */ +#define DMA2SA 0x0532 /* DMA Channel 2 Source Address */ +#define DMA2DA 0x0536 /* DMA Channel 2 Destination Address */ +#define DMA2SZ 0x053A /* DMA Channel 2 Transfer Size */ + +/* DMACTL0 Control Bits */ +#define DMA0TSEL0 (0x0001) /* DMA channel 0 transfer select bit 0 */ +#define DMA0TSEL1 (0x0002) /* DMA channel 0 transfer select bit 1 */ +#define DMA0TSEL2 (0x0004) /* DMA channel 0 transfer select bit 2 */ +#define DMA0TSEL3 (0x0008) /* DMA channel 0 transfer select bit 3 */ +#define DMA0TSEL4 (0x0010) /* DMA channel 0 transfer select bit 4 */ +#define DMA1TSEL0 (0x0100) /* DMA channel 1 transfer select bit 0 */ +#define DMA1TSEL1 (0x0200) /* DMA channel 1 transfer select bit 1 */ +#define DMA1TSEL2 (0x0400) /* DMA channel 1 transfer select bit 2 */ +#define DMA1TSEL3 (0x0800) /* DMA channel 1 transfer select bit 3 */ +#define DMA1TSEL4 (0x1000) /* DMA channel 1 transfer select bit 4 */ + +/* DMACTL0 Control Bits */ +#define DMA0TSEL0_L (0x0001) /* DMA channel 0 transfer select bit 0 */ +#define DMA0TSEL1_L (0x0002) /* DMA channel 0 transfer select bit 1 */ +#define DMA0TSEL2_L (0x0004) /* DMA channel 0 transfer select bit 2 */ +#define DMA0TSEL3_L (0x0008) /* DMA channel 0 transfer select bit 3 */ +#define DMA0TSEL4_L (0x0010) /* DMA channel 0 transfer select bit 4 */ + +/* DMACTL0 Control Bits */ +#define DMA1TSEL0_H (0x0001) /* DMA channel 1 transfer select bit 0 */ +#define DMA1TSEL1_H (0x0002) /* DMA channel 1 transfer select bit 1 */ +#define DMA1TSEL2_H (0x0004) /* DMA channel 1 transfer select bit 2 */ +#define DMA1TSEL3_H (0x0008) /* DMA channel 1 transfer select bit 3 */ +#define DMA1TSEL4_H (0x0010) /* DMA channel 1 transfer select bit 4 */ + +/* DMACTL01 Control Bits */ +#define DMA2TSEL0 (0x0001) /* DMA channel 2 transfer select bit 0 */ +#define DMA2TSEL1 (0x0002) /* DMA channel 2 transfer select bit 1 */ +#define DMA2TSEL2 (0x0004) /* DMA channel 2 transfer select bit 2 */ +#define DMA2TSEL3 (0x0008) /* DMA channel 2 transfer select bit 3 */ +#define DMA2TSEL4 (0x0010) /* DMA channel 2 transfer select bit 4 */ + +/* DMACTL01 Control Bits */ +#define DMA2TSEL0_L (0x0001) /* DMA channel 2 transfer select bit 0 */ +#define DMA2TSEL1_L (0x0002) /* DMA channel 2 transfer select bit 1 */ +#define DMA2TSEL2_L (0x0004) /* DMA channel 2 transfer select bit 2 */ +#define DMA2TSEL3_L (0x0008) /* DMA channel 2 transfer select bit 3 */ +#define DMA2TSEL4_L (0x0010) /* DMA channel 2 transfer select bit 4 */ + + +/* DMACTL4 Control Bits */ +#define ENNMI (0x0001) /* Enable NMI interruption of DMA */ +#define ROUNDROBIN (0x0002) /* Round-Robin DMA channel priorities */ +#define DMARMWDIS (0x0004) /* Inhibited DMA transfers during read-modify-write CPU operations */ + +/* DMACTL4 Control Bits */ +#define ENNMI_L (0x0001) /* Enable NMI interruption of DMA */ +#define ROUNDROBIN_L (0x0002) /* Round-Robin DMA channel priorities */ +#define DMARMWDIS_L (0x0004) /* Inhibited DMA transfers during read-modify-write CPU operations */ + + + +/* DMAxCTL Control Bits */ +#define DMAREQ (0x0001) /* Initiate DMA transfer with DMATSEL */ +#define DMAABORT (0x0002) /* DMA transfer aborted by NMI */ +#define DMAIE (0x0004) /* DMA interrupt enable */ +#define DMAIFG (0x0008) /* DMA interrupt flag */ +#define DMAEN (0x0010) /* DMA enable */ +#define DMALEVEL (0x0020) /* DMA level sensitive trigger select */ +#define DMASRCBYTE (0x0040) /* DMA source byte */ +#define DMADSTBYTE (0x0080) /* DMA destination byte */ +#define DMASRCINCR0 (0x0100) /* DMA source increment bit 0 */ +#define DMASRCINCR1 (0x0200) /* DMA source increment bit 1 */ +#define DMADSTINCR0 (0x0400) /* DMA destination increment bit 0 */ +#define DMADSTINCR1 (0x0800) /* DMA destination increment bit 1 */ +#define DMADT0 (0x1000) /* DMA transfer mode bit 0 */ +#define DMADT1 (0x2000) /* DMA transfer mode bit 1 */ +#define DMADT2 (0x4000) /* DMA transfer mode bit 2 */ + +/* DMAxCTL Control Bits */ +#define DMAREQ_L (0x0001) /* Initiate DMA transfer with DMATSEL */ +#define DMAABORT_L (0x0002) /* DMA transfer aborted by NMI */ +#define DMAIE_L (0x0004) /* DMA interrupt enable */ +#define DMAIFG_L (0x0008) /* DMA interrupt flag */ +#define DMAEN_L (0x0010) /* DMA enable */ +#define DMALEVEL_L (0x0020) /* DMA level sensitive trigger select */ +#define DMASRCBYTE_L (0x0040) /* DMA source byte */ +#define DMADSTBYTE_L (0x0080) /* DMA destination byte */ + +/* DMAxCTL Control Bits */ +#define DMASRCINCR0_H (0x0001) /* DMA source increment bit 0 */ +#define DMASRCINCR1_H (0x0002) /* DMA source increment bit 1 */ +#define DMADSTINCR0_H (0x0004) /* DMA destination increment bit 0 */ +#define DMADSTINCR1_H (0x0008) /* DMA destination increment bit 1 */ +#define DMADT0_H (0x0010) /* DMA transfer mode bit 0 */ +#define DMADT1_H (0x0020) /* DMA transfer mode bit 1 */ +#define DMADT2_H (0x0040) /* DMA transfer mode bit 2 */ + +#define DMASWDW (0x0000) /* DMA transfer: source word to destination word */ +#define DMASBDW (0x0040) /* DMA transfer: source byte to destination word */ +#define DMASWDB (0x0080) /* DMA transfer: source word to destination byte */ +#define DMASBDB (0x00C0) /* DMA transfer: source byte to destination byte */ + +#define DMASRCINCR_0 (0x0000) /* DMA source increment 0: source address unchanged */ +#define DMASRCINCR_1 (0x0100) /* DMA source increment 1: source address unchanged */ +#define DMASRCINCR_2 (0x0200) /* DMA source increment 2: source address decremented */ +#define DMASRCINCR_3 (0x0300) /* DMA source increment 3: source address incremented */ + +#define DMADSTINCR_0 (0x0000) /* DMA destination increment 0: destination address unchanged */ +#define DMADSTINCR_1 (0x0400) /* DMA destination increment 1: destination address unchanged */ +#define DMADSTINCR_2 (0x0800) /* DMA destination increment 2: destination address decremented */ +#define DMADSTINCR_3 (0x0C00) /* DMA destination increment 3: destination address incremented */ + +#define DMADT_0 (0x0000) /* DMA transfer mode 0: Single transfer */ +#define DMADT_1 (0x1000) /* DMA transfer mode 1: Block transfer */ +#define DMADT_2 (0x2000) /* DMA transfer mode 2: Burst-Block transfer */ +#define DMADT_3 (0x3000) /* DMA transfer mode 3: Burst-Block transfer */ +#define DMADT_4 (0x4000) /* DMA transfer mode 4: Repeated Single transfer */ +#define DMADT_5 (0x5000) /* DMA transfer mode 5: Repeated Block transfer */ +#define DMADT_6 (0x6000) /* DMA transfer mode 6: Repeated Burst-Block transfer */ +#define DMADT_7 (0x7000) /* DMA transfer mode 7: Repeated Burst-Block transfer */ + +/* DMAIV Definitions */ +#define DMAIV_NONE (0x0000) /* No Interrupt pending */ +#define DMAIV_DMA0IFG (0x0002) /* DMA0IFG*/ +#define DMAIV_DMA1IFG (0x0004) /* DMA1IFG*/ +#define DMAIV_DMA2IFG (0x0006) /* DMA2IFG*/ + +#define DMA0TSEL_0 (0x0000) /* DMA channel 0 transfer select 0: DMA_REQ (sw) */ +#define DMA0TSEL_1 (0x0001) /* DMA channel 0 transfer select 1: */ +#define DMA0TSEL_2 (0x0002) /* DMA channel 0 transfer select 2: */ +#define DMA0TSEL_3 (0x0003) /* DMA channel 0 transfer select 3: */ +#define DMA0TSEL_4 (0x0004) /* DMA channel 0 transfer select 4: */ +#define DMA0TSEL_5 (0x0005) /* DMA channel 0 transfer select 5: */ +#define DMA0TSEL_6 (0x0006) /* DMA channel 0 transfer select 6: */ +#define DMA0TSEL_7 (0x0007) /* DMA channel 0 transfer select 7: */ +#define DMA0TSEL_8 (0x0008) /* DMA channel 0 transfer select 8: */ +#define DMA0TSEL_9 (0x0009) /* DMA channel 0 transfer select 9: */ +#define DMA0TSEL_10 (0x000A) /* DMA channel 0 transfer select 10: */ +#define DMA0TSEL_11 (0x000B) /* DMA channel 0 transfer select 11: */ +#define DMA0TSEL_12 (0x000C) /* DMA channel 0 transfer select 12: */ +#define DMA0TSEL_13 (0x000D) /* DMA channel 0 transfer select 13: */ +#define DMA0TSEL_14 (0x000E) /* DMA channel 0 transfer select 14: */ +#define DMA0TSEL_15 (0x000F) /* DMA channel 0 transfer select 15: */ +#define DMA0TSEL_16 (0x0010) /* DMA channel 0 transfer select 16: */ +#define DMA0TSEL_17 (0x0011) /* DMA channel 0 transfer select 17: */ +#define DMA0TSEL_18 (0x0012) /* DMA channel 0 transfer select 18: */ +#define DMA0TSEL_19 (0x0013) /* DMA channel 0 transfer select 19: */ +#define DMA0TSEL_20 (0x0014) /* DMA channel 0 transfer select 20: */ +#define DMA0TSEL_21 (0x0015) /* DMA channel 0 transfer select 21: */ +#define DMA0TSEL_22 (0x0016) /* DMA channel 0 transfer select 22: */ +#define DMA0TSEL_23 (0x0017) /* DMA channel 0 transfer select 23: */ +#define DMA0TSEL_24 (0x0018) /* DMA channel 0 transfer select 24: */ +#define DMA0TSEL_25 (0x0019) /* DMA channel 0 transfer select 25: */ +#define DMA0TSEL_26 (0x001A) /* DMA channel 0 transfer select 26: */ +#define DMA0TSEL_27 (0x001B) /* DMA channel 0 transfer select 27: */ +#define DMA0TSEL_28 (0x001C) /* DMA channel 0 transfer select 28: */ +#define DMA0TSEL_29 (0x001D) /* DMA channel 0 transfer select 29: */ +#define DMA0TSEL_30 (0x001E) /* DMA channel 0 transfer select 30: previous DMA channel DMA2IFG */ +#define DMA0TSEL_31 (0x001F) /* DMA channel 0 transfer select 31: ext. Trigger (DMAE0) */ + +#define DMA1TSEL_0 (0x0000) /* DMA channel 1 transfer select 0: DMA_REQ (sw) */ +#define DMA1TSEL_1 (0x0100) /* DMA channel 1 transfer select 1: */ +#define DMA1TSEL_2 (0x0200) /* DMA channel 1 transfer select 2: */ +#define DMA1TSEL_3 (0x0300) /* DMA channel 1 transfer select 3: */ +#define DMA1TSEL_4 (0x0400) /* DMA channel 1 transfer select 4: */ +#define DMA1TSEL_5 (0x0500) /* DMA channel 1 transfer select 5: */ +#define DMA1TSEL_6 (0x0600) /* DMA channel 1 transfer select 6: */ +#define DMA1TSEL_7 (0x0700) /* DMA channel 1 transfer select 7: */ +#define DMA1TSEL_8 (0x0800) /* DMA channel 1 transfer select 8: */ +#define DMA1TSEL_9 (0x0900) /* DMA channel 1 transfer select 9: */ +#define DMA1TSEL_10 (0x0A00) /* DMA channel 1 transfer select 10: */ +#define DMA1TSEL_11 (0x0B00) /* DMA channel 1 transfer select 11: */ +#define DMA1TSEL_12 (0x0C00) /* DMA channel 1 transfer select 12: */ +#define DMA1TSEL_13 (0x0D00) /* DMA channel 1 transfer select 13: */ +#define DMA1TSEL_14 (0x0E00) /* DMA channel 1 transfer select 14: */ +#define DMA1TSEL_15 (0x0F00) /* DMA channel 1 transfer select 15: */ +#define DMA1TSEL_16 (0x1000) /* DMA channel 1 transfer select 16: */ +#define DMA1TSEL_17 (0x1100) /* DMA channel 1 transfer select 17: */ +#define DMA1TSEL_18 (0x1200) /* DMA channel 1 transfer select 18: */ +#define DMA1TSEL_19 (0x1300) /* DMA channel 1 transfer select 19: */ +#define DMA1TSEL_20 (0x1400) /* DMA channel 1 transfer select 20: */ +#define DMA1TSEL_21 (0x1500) /* DMA channel 1 transfer select 21: */ +#define DMA1TSEL_22 (0x1600) /* DMA channel 1 transfer select 22: */ +#define DMA1TSEL_23 (0x1700) /* DMA channel 1 transfer select 23: */ +#define DMA1TSEL_24 (0x1800) /* DMA channel 1 transfer select 24: */ +#define DMA1TSEL_25 (0x1900) /* DMA channel 1 transfer select 25: */ +#define DMA1TSEL_26 (0x1A00) /* DMA channel 1 transfer select 26: */ +#define DMA1TSEL_27 (0x1B00) /* DMA channel 1 transfer select 27: */ +#define DMA1TSEL_28 (0x1C00) /* DMA channel 1 transfer select 28: */ +#define DMA1TSEL_29 (0x1D00) /* DMA channel 1 transfer select 29: */ +#define DMA1TSEL_30 (0x1E00) /* DMA channel 1 transfer select 30: previous DMA channel DMA0IFG */ +#define DMA1TSEL_31 (0x1F00) /* DMA channel 1 transfer select 31: ext. Trigger (DMAE0) */ + +#define DMA2TSEL_0 (0x0000) /* DMA channel 2 transfer select 0: DMA_REQ (sw) */ +#define DMA2TSEL_1 (0x0001) /* DMA channel 2 transfer select 1: */ +#define DMA2TSEL_2 (0x0002) /* DMA channel 2 transfer select 2: */ +#define DMA2TSEL_3 (0x0003) /* DMA channel 2 transfer select 3: */ +#define DMA2TSEL_4 (0x0004) /* DMA channel 2 transfer select 4: */ +#define DMA2TSEL_5 (0x0005) /* DMA channel 2 transfer select 5: */ +#define DMA2TSEL_6 (0x0006) /* DMA channel 2 transfer select 6: */ +#define DMA2TSEL_7 (0x0007) /* DMA channel 2 transfer select 7: */ +#define DMA2TSEL_8 (0x0008) /* DMA channel 2 transfer select 8: */ +#define DMA2TSEL_9 (0x0009) /* DMA channel 2 transfer select 9: */ +#define DMA2TSEL_10 (0x000A) /* DMA channel 2 transfer select 10: */ +#define DMA2TSEL_11 (0x000B) /* DMA channel 2 transfer select 11: */ +#define DMA2TSEL_12 (0x000C) /* DMA channel 2 transfer select 12: */ +#define DMA2TSEL_13 (0x000D) /* DMA channel 2 transfer select 13: */ +#define DMA2TSEL_14 (0x000E) /* DMA channel 2 transfer select 14: */ +#define DMA2TSEL_15 (0x000F) /* DMA channel 2 transfer select 15: */ +#define DMA2TSEL_16 (0x0010) /* DMA channel 2 transfer select 16: */ +#define DMA2TSEL_17 (0x0011) /* DMA channel 2 transfer select 17: */ +#define DMA2TSEL_18 (0x0012) /* DMA channel 2 transfer select 18: */ +#define DMA2TSEL_19 (0x0013) /* DMA channel 2 transfer select 19: */ +#define DMA2TSEL_20 (0x0014) /* DMA channel 2 transfer select 20: */ +#define DMA2TSEL_21 (0x0015) /* DMA channel 2 transfer select 21: */ +#define DMA2TSEL_22 (0x0016) /* DMA channel 2 transfer select 22: */ +#define DMA2TSEL_23 (0x0017) /* DMA channel 2 transfer select 23: */ +#define DMA2TSEL_24 (0x0018) /* DMA channel 2 transfer select 24: */ +#define DMA2TSEL_25 (0x0019) /* DMA channel 2 transfer select 25: */ +#define DMA2TSEL_26 (0x001A) /* DMA channel 2 transfer select 26: */ +#define DMA2TSEL_27 (0x001B) /* DMA channel 2 transfer select 27: */ +#define DMA2TSEL_28 (0x001C) /* DMA channel 2 transfer select 28: */ +#define DMA2TSEL_29 (0x001D) /* DMA channel 2 transfer select 29: */ +#define DMA2TSEL_30 (0x001E) /* DMA channel 2 transfer select 30: previous DMA channel DMA1IFG */ +#define DMA2TSEL_31 (0x001F) /* DMA channel 2 transfer select 31: ext. Trigger (DMAE0) */ + +#define DMA0TSEL__DMAREQ (0x0000) /* DMA channel 0 transfer select 0: DMA_REQ (sw) */ +#define DMA0TSEL__TA0CCR0 (0x0001) /* DMA channel 0 transfer select 1: TA0CCR0 */ +#define DMA0TSEL__TA0CCR2 (0x0002) /* DMA channel 0 transfer select 2: TA0CCR2 */ +#define DMA0TSEL__TA1CCR0 (0x0003) /* DMA channel 0 transfer select 3: TA1CCR0 */ +#define DMA0TSEL__TA1CCR2 (0x0004) /* DMA channel 0 transfer select 4: TA1CCR2 */ +#define DMA0TSEL__TA2CCR0 (0x0005) /* DMA channel 0 transfer select 3: TA2CCR0 */ +#define DMA0TSEL__TA3CCR0 (0x0006) /* DMA channel 0 transfer select 4: TA3CCR0 */ +#define DMA0TSEL__TB0CCR0 (0x0007) /* DMA channel 0 transfer select 7: TB0CCR0 */ +#define DMA0TSEL__TB0CCR2 (0x0008) /* DMA channel 0 transfer select 8: TB0CCR2 */ +#define DMA0TSEL__RES9 (0x0009) /* DMA channel 0 transfer select 9: RES9 */ +#define DMA0TSEL__RES10 (0x000A) /* DMA channel 0 transfer select 10: RES10 */ +#define DMA0TSEL__RES11 (0x000B) /* DMA channel 0 transfer select 11: RES11 */ +#define DMA0TSEL__RES12 (0x000C) /* DMA channel 0 transfer select 12: RES12 */ +#define DMA0TSEL__RES13 (0x000D) /* DMA channel 0 transfer select 13: RES13 */ +#define DMA0TSEL__UCA0RXIFG (0x000E) /* DMA channel 0 transfer select 14: UCA0RXIFG */ +#define DMA0TSEL__UCA0TXIFG (0x000F) /* DMA channel 0 transfer select 15: UCA0TXIFG */ +#define DMA0TSEL__UCA1RXIFG (0x0010) /* DMA channel 0 transfer select 16: UCA1RXIFG */ +#define DMA0TSEL__UCA1TXIFG (0x0011) /* DMA channel 0 transfer select 17: UCA1TXIFG */ +#define DMA0TSEL__UCB0RXIFG0 (0x0012) /* DMA channel 0 transfer select 18: UCB0RXIFG0 */ +#define DMA0TSEL__UCB0TXIFG0 (0x0013) /* DMA channel 0 transfer select 19: UCB0TXIFG0 */ +#define DMA0TSEL__UCB0RXIFG1 (0x0014) /* DMA channel 0 transfer select 20: UCB0RXIFG1 */ +#define DMA0TSEL__UCB0TXIFG1 (0x0015) /* DMA channel 0 transfer select 21: UCB0TXIFG1 */ +#define DMA0TSEL__UCB0RXIFG2 (0x0016) /* DMA channel 0 transfer select 22: UCB0RXIFG2 */ +#define DMA0TSEL__UCB0TXIFG2 (0x0017) /* DMA channel 0 transfer select 23: UCB0TXIFG2 */ +#define DMA0TSEL__UCB0RXIFG3 (0x0018) /* DMA channel 0 transfer select 24: UCB0RXIFG3 */ +#define DMA0TSEL__UCB0TXIFG3 (0x0019) /* DMA channel 0 transfer select 25: UCB0TXIFG3 */ +#define DMA0TSEL__ADC12IFG (0x001A) /* DMA channel 0 transfer select 26: ADC12IFG */ +#define DMA0TSEL__RES27 (0x001B) /* DMA channel 0 transfer select 27: RES27 */ +#define DMA0TSEL__RES28 (0x001C) /* DMA channel 0 transfer select 28: RES28 */ +#define DMA0TSEL__MPY (0x001D) /* DMA channel 0 transfer select 29: MPY */ +#define DMA0TSEL__DMA2IFG (0x001E) /* DMA channel 0 transfer select 30: previous DMA channel DMA2IFG */ +#define DMA0TSEL__DMAE0 (0x001F) /* DMA channel 0 transfer select 31: ext. Trigger (DMAE0) */ + +#define DMA1TSEL__DMAREQ (0x0000) /* DMA channel 1 transfer select 0: DMA_REQ (sw) */ +#define DMA1TSEL__TA0CCR0 (0x0100) /* DMA channel 1 transfer select 1: TA0CCR0 */ +#define DMA1TSEL__TA0CCR2 (0x0200) /* DMA channel 1 transfer select 2: TA0CCR2 */ +#define DMA1TSEL__TA1CCR0 (0x0300) /* DMA channel 1 transfer select 3: TA1CCR0 */ +#define DMA1TSEL__TA1CCR2 (0x0400) /* DMA channel 1 transfer select 4: TA1CCR2 */ +#define DMA1TSEL__TA2CCR0 (0x0500) /* DMA channel 1 transfer select 5: TA2CCR0 */ +#define DMA1TSEL__TA3CCR0 (0x0600) /* DMA channel 1 transfer select 6: TA3CCR0 */ +#define DMA1TSEL__TB0CCR0 (0x0700) /* DMA channel 1 transfer select 7: TB0CCR0 */ +#define DMA1TSEL__TB0CCR2 (0x0800) /* DMA channel 1 transfer select 8: TB0CCR2 */ +#define DMA1TSEL__RES9 (0x0900) /* DMA channel 1 transfer select 9: RES9 */ +#define DMA1TSEL__RES10 (0x0A00) /* DMA channel 1 transfer select 10: RES10 */ +#define DMA1TSEL__RES11 (0x0B00) /* DMA channel 1 transfer select 11: RES11 */ +#define DMA1TSEL__RES12 (0x0C00) /* DMA channel 1 transfer select 12: RES12 */ +#define DMA1TSEL__RES13 (0x0D00) /* DMA channel 1 transfer select 13: RES13 */ +#define DMA1TSEL__UCA0RXIFG (0x0E00) /* DMA channel 1 transfer select 14: UCA0RXIFG */ +#define DMA1TSEL__UCA0TXIFG (0x0F00) /* DMA channel 1 transfer select 15: UCA0TXIFG */ +#define DMA1TSEL__UCA1RXIFG (0x1000) /* DMA channel 1 transfer select 16: UCA1RXIFG */ +#define DMA1TSEL__UCA1TXIFG (0x1100) /* DMA channel 1 transfer select 17: UCA1TXIFG */ +#define DMA1TSEL__UCB0RXIFG0 (0x1200) /* DMA channel 1 transfer select 18: UCB0RXIFG0 */ +#define DMA1TSEL__UCB0TXIFG0 (0x1300) /* DMA channel 1 transfer select 19: UCB0TXIFG0 */ +#define DMA1TSEL__UCB0RXIFG1 (0x1400) /* DMA channel 1 transfer select 20: UCB0RXIFG1 */ +#define DMA1TSEL__UCB0TXIFG1 (0x1500) /* DMA channel 1 transfer select 21: UCB0TXIFG1 */ +#define DMA1TSEL__UCB0RXIFG2 (0x1600) /* DMA channel 1 transfer select 22: UCB0RXIFG2 */ +#define DMA1TSEL__UCB0TXIFG2 (0x1700) /* DMA channel 1 transfer select 23: UCB0TXIFG2 */ +#define DMA1TSEL__UCB0RXIFG3 (0x1800) /* DMA channel 1 transfer select 24: UCB0RXIFG3 */ +#define DMA1TSEL__UCB0TXIFG3 (0x1900) /* DMA channel 1 transfer select 25: UCB0TXIFG3 */ +#define DMA1TSEL__ADC12IFG (0x1A00) /* DMA channel 1 transfer select 26: ADC12IFG */ +#define DMA1TSEL__RES27 (0x1B00) /* DMA channel 1 transfer select 27: RES27 */ +#define DMA1TSEL__RES28 (0x1C00) /* DMA channel 1 transfer select 28: RES28 */ +#define DMA1TSEL__MPY (0x1D00) /* DMA channel 1 transfer select 29: MPY */ +#define DMA1TSEL__DMA2IFG (0x1E00) /* DMA channel 1 transfer select 30: previous DMA channel DMA2IFG */ +#define DMA1TSEL__DMAE0 (0x1F00) /* DMA channel 1 transfer select 31: ext. Trigger (DMAE0) */ + +#define DMA2TSEL__DMAREQ (0x0000) /* DMA channel 2 transfer select 0: DMA_REQ (sw) */ +#define DMA2TSEL__TA0CCR0 (0x0001) /* DMA channel 2 transfer select 1: TA0CCR0 */ +#define DMA2TSEL__TA0CCR2 (0x0002) /* DMA channel 2 transfer select 2: TA0CCR2 */ +#define DMA2TSEL__TA1CCR0 (0x0003) /* DMA channel 2 transfer select 3: TA1CCR0 */ +#define DMA2TSEL__TA1CCR2 (0x0004) /* DMA channel 2 transfer select 4: TA1CCR2 */ +#define DMA2TSEL__TA2CCR0 (0x0005) /* DMA channel 2 transfer select 5: TA2CCR0 */ +#define DMA2TSEL__TA3CCR0 (0x0006) /* DMA channel 2 transfer select 6: TA3CCR0 */ +#define DMA2TSEL__TB0CCR0 (0x0007) /* DMA channel 2 transfer select 7: TB0CCR0 */ +#define DMA2TSEL__TB0CCR2 (0x0008) /* DMA channel 2 transfer select 8: TB0CCR2 */ +#define DMA2TSEL__RES9 (0x0009) /* DMA channel 2 transfer select 9: RES9 */ +#define DMA2TSEL__RES10 (0x000A) /* DMA channel 2 transfer select 10: RES10 */ +#define DMA2TSEL__RES11 (0x000B) /* DMA channel 2 transfer select 11: RES11 */ +#define DMA2TSEL__RES12 (0x000C) /* DMA channel 2 transfer select 12: RES12 */ +#define DMA2TSEL__RES13 (0x000D) /* DMA channel 2 transfer select 13: RES13 */ +#define DMA2TSEL__UCA0RXIFG (0x000E) /* DMA channel 2 transfer select 14: UCA0RXIFG */ +#define DMA2TSEL__UCA0TXIFG (0x000F) /* DMA channel 2 transfer select 15: UCA0TXIFG */ +#define DMA2TSEL__UCA1RXIFG (0x0010) /* DMA channel 2 transfer select 16: UCA1RXIFG */ +#define DMA2TSEL__UCA1TXIFG (0x0011) /* DMA channel 2 transfer select 17: UCA1TXIFG */ +#define DMA2TSEL__UCB0RXIFG0 (0x0012) /* DMA channel 2 transfer select 18: UCB0RXIFG0 */ +#define DMA2TSEL__UCB0TXIFG0 (0x0013) /* DMA channel 2 transfer select 19: UCB0TXIFG0 */ +#define DMA2TSEL__UCB0RXIFG1 (0x0014) /* DMA channel 2 transfer select 20: UCB0RXIFG1 */ +#define DMA2TSEL__UCB0TXIFG1 (0x0015) /* DMA channel 2 transfer select 21: UCB0TXIFG1 */ +#define DMA2TSEL__UCB0RXIFG2 (0x0016) /* DMA channel 2 transfer select 22: UCB0RXIFG2 */ +#define DMA2TSEL__UCB0TXIFG2 (0x0017) /* DMA channel 2 transfer select 23: UCB0TXIFG2 */ +#define DMA2TSEL__UCB0RXIFG3 (0x0018) /* DMA channel 2 transfer select 24: UCB0RXIFG3 */ +#define DMA2TSEL__UCB0TXIFG3 (0x0019) /* DMA channel 2 transfer select 25: UCB0TXIFG3 */ +#define DMA2TSEL__ADC12IFG (0x001A) /* DMA channel 2 transfer select 26: ADC12IFG */ +#define DMA2TSEL__RES27 (0x001B) /* DMA channel 2 transfer select 27: RES27 */ +#define DMA2TSEL__RES28 (0x001C) /* DMA channel 2 transfer select 28: RES28 */ +#define DMA2TSEL__MPY (0x001D) /* DMA channel 2 transfer select 29: MPY */ +#define DMA2TSEL__DMA2IFG (0x001E) /* DMA channel 2 transfer select 30: previous DMA channel DMA2IFG */ +#define DMA2TSEL__DMAE0 (0x001F) /* DMA channel 2 transfer select 31: ext. Trigger (DMAE0) */ + +/************************************************************* +* FRAM Memory +*************************************************************/ + +#define FRCTL0 0x0140 /* FRAM Controller Control 0 */ +#define GCCTL0 0x0144 /* General Control 0 */ +#define GCCTL1 0x0146 /* General Control 1 */ + +#define FRCTLPW (0xA500) /* FRAM password for write */ +#define FRPW (0x9600) /* FRAM password returned by read */ +#define FWPW (0xA500) /* FRAM password for write */ +#define FXPW (0x3300) /* for use with XOR instruction */ + +/* FRCTL0 Control Bits */ +//#define RESERVED (0x0001) /* RESERVED */ +//#define RESERVED (0x0002) /* RESERVED */ +//#define RESERVED (0x0004) /* RESERVED */ +#define NWAITS0 (0x0010) /* FRAM Wait state control Bit: 0 */ +#define NWAITS1 (0x0020) /* FRAM Wait state control Bit: 1 */ +#define NWAITS2 (0x0040) /* FRAM Wait state control Bit: 2 */ +//#define RESERVED (0x0080) /* RESERVED */ + +/* FRCTL0 Control Bits */ +//#define RESERVED (0x0001) /* RESERVED */ +//#define RESERVED (0x0002) /* RESERVED */ +//#define RESERVED (0x0004) /* RESERVED */ +#define NWAITS0_L (0x0010) /* FRAM Wait state control Bit: 0 */ +#define NWAITS1_L (0x0020) /* FRAM Wait state control Bit: 1 */ +#define NWAITS2_L (0x0040) /* FRAM Wait state control Bit: 2 */ +//#define RESERVED (0x0080) /* RESERVED */ + + +#define NWAITS_0 (0x0000) /* FRAM Wait state control: 0 */ +#define NWAITS_1 (0x0010) /* FRAM Wait state control: 1 */ +#define NWAITS_2 (0x0020) /* FRAM Wait state control: 2 */ +#define NWAITS_3 (0x0030) /* FRAM Wait state control: 3 */ +#define NWAITS_4 (0x0040) /* FRAM Wait state control: 4 */ +#define NWAITS_5 (0x0050) /* FRAM Wait state control: 5 */ +#define NWAITS_6 (0x0060) /* FRAM Wait state control: 6 */ +#define NWAITS_7 (0x0070) /* FRAM Wait state control: 7 */ + +/* Legacy Defines */ +#define NACCESS0 (0x0010) /* FRAM Wait state Generator Access Time control Bit: 0 */ +#define NACCESS1 (0x0020) /* FRAM Wait state Generator Access Time control Bit: 1 */ +#define NACCESS2 (0x0040) /* FRAM Wait state Generator Access Time control Bit: 2 */ +#define NACCESS_0 (0x0000) /* FRAM Wait state Generator Access Time control: 0 */ +#define NACCESS_1 (0x0010) /* FRAM Wait state Generator Access Time control: 1 */ +#define NACCESS_2 (0x0020) /* FRAM Wait state Generator Access Time control: 2 */ +#define NACCESS_3 (0x0030) /* FRAM Wait state Generator Access Time control: 3 */ +#define NACCESS_4 (0x0040) /* FRAM Wait state Generator Access Time control: 4 */ +#define NACCESS_5 (0x0050) /* FRAM Wait state Generator Access Time control: 5 */ +#define NACCESS_6 (0x0060) /* FRAM Wait state Generator Access Time control: 6 */ +#define NACCESS_7 (0x0070) /* FRAM Wait state Generator Access Time control: 7 */ + + +/* GCCTL0 Control Bits */ +//#define RESERVED (0x0001) /* RESERVED */ +#define FRLPMPWR (0x0002) /* FRAM Enable FRAM auto power up after LPM */ +#define FRPWR (0x0004) /* FRAM Power Control */ +#define ACCTEIE (0x0008) /* RESERVED */ +//#define RESERVED (0x0010) /* RESERVED */ +#define CBDIE (0x0020) /* Enable NMI event if correctable bit error detected */ +#define UBDIE (0x0040) /* Enable NMI event if uncorrectable bit error detected */ +#define UBDRSTEN (0x0080) /* Enable Power Up Clear (PUC) reset if FRAM uncorrectable bit error detected */ + +/* GCCTL0 Control Bits */ +//#define RESERVED (0x0001) /* RESERVED */ +#define FRLPMPWR_L (0x0002) /* FRAM Enable FRAM auto power up after LPM */ +#define FRPWR_L (0x0004) /* FRAM Power Control */ +#define ACCTEIE_L (0x0008) /* RESERVED */ +//#define RESERVED (0x0010) /* RESERVED */ +#define CBDIE_L (0x0020) /* Enable NMI event if correctable bit error detected */ +#define UBDIE_L (0x0040) /* Enable NMI event if uncorrectable bit error detected */ +#define UBDRSTEN_L (0x0080) /* Enable Power Up Clear (PUC) reset if FRAM uncorrectable bit error detected */ + + +/* GCCTL1 Control Bits */ +//#define RESERVED (0x0001) /* RESERVED */ +#define CBDIFG (0x0002) /* FRAM correctable bit error flag */ +#define UBDIFG (0x0004) /* FRAM uncorrectable bit error flag */ +#define ACCTEIFG (0x0008) /* Access time error flag */ + +/* GCCTL1 Control Bits */ +//#define RESERVED (0x0001) /* RESERVED */ +#define CBDIFG_L (0x0002) /* FRAM correctable bit error flag */ +#define UBDIFG_L (0x0004) /* FRAM uncorrectable bit error flag */ +#define ACCTEIFG_L (0x0008) /* Access time error flag */ + + +/************************************************************ +* Memory Protection Unit +************************************************************/ + +#define MPUCTL0 0x05A0 /* MPU Control Register 0 */ +#define MPUCTL1 0x05A2 /* MPU Control Register 1 */ +#define MPUSEGB2 0x05A4 /* MPU Segmentation Border 2 Register */ +#define MPUSEGB1 0x05A6 /* MPU Segmentation Border 1 Register */ +#define MPUSAM 0x05A8 /* MPU Access Management Register */ +#define MPUIPC0 0x05AA /* MPU IP Control 0 Register */ +#define MPUIPSEGB2 0x05AC /* MPU IP Segment Border 2 Register */ +#define MPUIPSEGB1 0x05AE /* MPU IP Segment Border 1 Register */ + +/* MPUCTL0 Control Bits */ +#define MPUENA (0x0001) /* MPU Enable */ +#define MPULOCK (0x0002) /* MPU Lock */ +#define MPUSEGIE (0x0010) /* MPU Enable NMI on Segment violation */ + +/* MPUCTL0 Control Bits */ +#define MPUENA_L (0x0001) /* MPU Enable */ +#define MPULOCK_L (0x0002) /* MPU Lock */ +#define MPUSEGIE_L (0x0010) /* MPU Enable NMI on Segment violation */ + +#define MPUPW (0xA500) /* MPU Access Password */ +#define MPUPW_H (0xA5) /* MPU Access Password */ + +/* MPUCTL1 Control Bits */ +#define MPUSEG1IFG (0x0001) /* MPU Main Memory Segment 1 violation interupt flag */ +#define MPUSEG2IFG (0x0002) /* MPU Main Memory Segment 2 violation interupt flag */ +#define MPUSEG3IFG (0x0004) /* MPU Main Memory Segment 3 violation interupt flag */ +#define MPUSEGIIFG (0x0008) /* MPU Info Memory Segment violation interupt flag */ +#define MPUSEGIPIFG (0x0010) /* MPU IP Memory Segment violation interupt flag */ + +/* MPUCTL1 Control Bits */ +#define MPUSEG1IFG_L (0x0001) /* MPU Main Memory Segment 1 violation interupt flag */ +#define MPUSEG2IFG_L (0x0002) /* MPU Main Memory Segment 2 violation interupt flag */ +#define MPUSEG3IFG_L (0x0004) /* MPU Main Memory Segment 3 violation interupt flag */ +#define MPUSEGIIFG_L (0x0008) /* MPU Info Memory Segment violation interupt flag */ +#define MPUSEGIPIFG_L (0x0010) /* MPU IP Memory Segment violation interupt flag */ + + +/* MPUSEGB2 Control Bits */ + +/* MPUSEGB2 Control Bits */ + +/* MPUSEGB2 Control Bits */ + +/* MPUSEGB1 Control Bits */ + +/* MPUSEGB1 Control Bits */ + +/* MPUSEGB1 Control Bits */ + +/* MPUSAM Control Bits */ +#define MPUSEG1RE (0x0001) /* MPU Main memory Segment 1 Read enable */ +#define MPUSEG1WE (0x0002) /* MPU Main memory Segment 1 Write enable */ +#define MPUSEG1XE (0x0004) /* MPU Main memory Segment 1 Execute enable */ +#define MPUSEG1VS (0x0008) /* MPU Main memory Segment 1 Violation select */ +#define MPUSEG2RE (0x0010) /* MPU Main memory Segment 2 Read enable */ +#define MPUSEG2WE (0x0020) /* MPU Main memory Segment 2 Write enable */ +#define MPUSEG2XE (0x0040) /* MPU Main memory Segment 2 Execute enable */ +#define MPUSEG2VS (0x0080) /* MPU Main memory Segment 2 Violation select */ +#define MPUSEG3RE (0x0100) /* MPU Main memory Segment 3 Read enable */ +#define MPUSEG3WE (0x0200) /* MPU Main memory Segment 3 Write enable */ +#define MPUSEG3XE (0x0400) /* MPU Main memory Segment 3 Execute enable */ +#define MPUSEG3VS (0x0800) /* MPU Main memory Segment 3 Violation select */ +#define MPUSEGIRE (0x1000) /* MPU Info memory Segment Read enable */ +#define MPUSEGIWE (0x2000) /* MPU Info memory Segment Write enable */ +#define MPUSEGIXE (0x4000) /* MPU Info memory Segment Execute enable */ +#define MPUSEGIVS (0x8000) /* MPU Info memory Segment Violation select */ + +/* MPUSAM Control Bits */ +#define MPUSEG1RE_L (0x0001) /* MPU Main memory Segment 1 Read enable */ +#define MPUSEG1WE_L (0x0002) /* MPU Main memory Segment 1 Write enable */ +#define MPUSEG1XE_L (0x0004) /* MPU Main memory Segment 1 Execute enable */ +#define MPUSEG1VS_L (0x0008) /* MPU Main memory Segment 1 Violation select */ +#define MPUSEG2RE_L (0x0010) /* MPU Main memory Segment 2 Read enable */ +#define MPUSEG2WE_L (0x0020) /* MPU Main memory Segment 2 Write enable */ +#define MPUSEG2XE_L (0x0040) /* MPU Main memory Segment 2 Execute enable */ +#define MPUSEG2VS_L (0x0080) /* MPU Main memory Segment 2 Violation select */ + +/* MPUSAM Control Bits */ +#define MPUSEG3RE_H (0x0001) /* MPU Main memory Segment 3 Read enable */ +#define MPUSEG3WE_H (0x0002) /* MPU Main memory Segment 3 Write enable */ +#define MPUSEG3XE_H (0x0004) /* MPU Main memory Segment 3 Execute enable */ +#define MPUSEG3VS_H (0x0008) /* MPU Main memory Segment 3 Violation select */ +#define MPUSEGIRE_H (0x0010) /* MPU Info memory Segment Read enable */ +#define MPUSEGIWE_H (0x0020) /* MPU Info memory Segment Write enable */ +#define MPUSEGIXE_H (0x0040) /* MPU Info memory Segment Execute enable */ +#define MPUSEGIVS_H (0x0080) /* MPU Info memory Segment Violation select */ + +/* MPUIPC0 Control Bits */ +#define MPUIPVS (0x0020) /* MPU MPU IP protection segment Violation Select */ +#define MPUIPENA (0x0040) /* MPU MPU IP Protection Enable */ +#define MPUIPLOCK (0x0080) /* MPU IP Protection Lock */ + +/* MPUIPC0 Control Bits */ +#define MPUIPVS_L (0x0020) /* MPU MPU IP protection segment Violation Select */ +#define MPUIPENA_L (0x0040) /* MPU MPU IP Protection Enable */ +#define MPUIPLOCK_L (0x0080) /* MPU IP Protection Lock */ + + +/* MPUIPSEGB2 Control Bits */ + +/* MPUIPSEGB2 Control Bits */ + +/* MPUIPSEGB2 Control Bits */ + +/* MPUIPSEGB1 Control Bits */ + +/* MPUIPSEGB1 Control Bits */ + +/* MPUIPSEGB1 Control Bits */ + +/************************************************************ +* HARDWARE MULTIPLIER 32Bit +************************************************************/ + +#define MPY 0x04C0 /* Multiply Unsigned/Operand 1 */ +#define MPYS 0x04C2 /* Multiply Signed/Operand 1 */ +#define MAC 0x04C4 /* Multiply Unsigned and Accumulate/Operand 1 */ +#define MACS 0x04C6 /* Multiply Signed and Accumulate/Operand 1 */ +#define OP2 0x04C8 /* Operand 2 */ +#define RESLO 0x04CA /* Result Low Word */ +#define RESHI 0x04CC /* Result High Word */ +#define SUMEXT 0x04CE /* Sum Extend */ + +#define MPY32L 0x04D0 /* 32-bit operand 1 - multiply - low word */ +#define MPY32H 0x04D2 /* 32-bit operand 1 - multiply - high word */ +#define MPYS32L 0x04D4 /* 32-bit operand 1 - signed multiply - low word */ +#define MPYS32H 0x04D6 /* 32-bit operand 1 - signed multiply - high word */ +#define MAC32L 0x04D8 /* 32-bit operand 1 - multiply accumulate - low word */ +#define MAC32H 0x04DA /* 32-bit operand 1 - multiply accumulate - high word */ +#define MACS32L 0x04DC /* 32-bit operand 1 - signed multiply accumulate - low word */ +#define MACS32H 0x04DE /* 32-bit operand 1 - signed multiply accumulate - high word */ +#define OP2L 0x04E0 /* 32-bit operand 2 - low word */ +#define OP2H 0x04E2 /* 32-bit operand 2 - high word */ +#define RES0 0x04E4 /* 32x32-bit result 0 - least significant word */ +#define RES1 0x04E6 /* 32x32-bit result 1 */ +#define RES2 0x04E8 /* 32x32-bit result 2 */ +#define RES3 0x04EA /* 32x32-bit result 3 - most significant word */ +#define MPY32CTL0 0x04EC /* MPY32 Control Register 0 */ + +#define MPY_B MPY_L /* Multiply Unsigned/Operand 1 (Byte Access) */ +#define MPYS_B MPYS_L /* Multiply Signed/Operand 1 (Byte Access) */ +#define MAC_B MAC_L /* Multiply Unsigned and Accumulate/Operand 1 (Byte Access) */ +#define MACS_B MACS_L /* Multiply Signed and Accumulate/Operand 1 (Byte Access) */ +#define OP2_B OP2_L /* Operand 2 (Byte Access) */ +#define MPY32L_B MPY32L_L /* 32-bit operand 1 - multiply - low word (Byte Access) */ +#define MPY32H_B MPY32H_L /* 32-bit operand 1 - multiply - high word (Byte Access) */ +#define MPYS32L_B MPYS32L_L /* 32-bit operand 1 - signed multiply - low word (Byte Access) */ +#define MPYS32H_B MPYS32H_L /* 32-bit operand 1 - signed multiply - high word (Byte Access) */ +#define MAC32L_B MAC32L_L /* 32-bit operand 1 - multiply accumulate - low word (Byte Access) */ +#define MAC32H_B MAC32H_L /* 32-bit operand 1 - multiply accumulate - high word (Byte Access) */ +#define MACS32L_B MACS32L_L /* 32-bit operand 1 - signed multiply accumulate - low word (Byte Access) */ +#define MACS32H_B MACS32H_L /* 32-bit operand 1 - signed multiply accumulate - high word (Byte Access) */ +#define OP2L_B OP2L_L /* 32-bit operand 2 - low word (Byte Access) */ +#define OP2H_B OP2H_L /* 32-bit operand 2 - high word (Byte Access) */ + + +/* MPY32CTL0 Control Bits */ +#define MPYC (0x0001) /* Carry of the multiplier */ +//#define RESERVED (0x0002) /* Reserved */ +#define MPYFRAC (0x0004) /* Fractional mode */ +#define MPYSAT (0x0008) /* Saturation mode */ +#define MPYM0 (0x0010) /* Multiplier mode Bit:0 */ +#define MPYM1 (0x0020) /* Multiplier mode Bit:1 */ +#define OP1_32 (0x0040) /* Bit-width of operand 1 0:16Bit / 1:32Bit */ +#define OP2_32 (0x0080) /* Bit-width of operand 2 0:16Bit / 1:32Bit */ +#define MPYDLYWRTEN (0x0100) /* Delayed write enable */ +#define MPYDLY32 (0x0200) /* Delayed write mode */ + +/* MPY32CTL0 Control Bits */ +#define MPYC_L (0x0001) /* Carry of the multiplier */ +//#define RESERVED (0x0002) /* Reserved */ +#define MPYFRAC_L (0x0004) /* Fractional mode */ +#define MPYSAT_L (0x0008) /* Saturation mode */ +#define MPYM0_L (0x0010) /* Multiplier mode Bit:0 */ +#define MPYM1_L (0x0020) /* Multiplier mode Bit:1 */ +#define OP1_32_L (0x0040) /* Bit-width of operand 1 0:16Bit / 1:32Bit */ +#define OP2_32_L (0x0080) /* Bit-width of operand 2 0:16Bit / 1:32Bit */ + +/* MPY32CTL0 Control Bits */ +//#define RESERVED (0x0002) /* Reserved */ +#define MPYDLYWRTEN_H (0x0001) /* Delayed write enable */ +#define MPYDLY32_H (0x0002) /* Delayed write mode */ + +#define MPYM_0 (0x0000) /* Multiplier mode: MPY */ +#define MPYM_1 (0x0010) /* Multiplier mode: MPYS */ +#define MPYM_2 (0x0020) /* Multiplier mode: MAC */ +#define MPYM_3 (0x0030) /* Multiplier mode: MACS */ +#define MPYM__MPY (0x0000) /* Multiplier mode: MPY */ +#define MPYM__MPYS (0x0010) /* Multiplier mode: MPYS */ +#define MPYM__MAC (0x0020) /* Multiplier mode: MAC */ +#define MPYM__MACS (0x0030) /* Multiplier mode: MACS */ + +/************************************************************ +* PMM - Power Management System for FRAM +************************************************************/ + +#define PMMCTL0 0x0120 /* PMM Control 0 */ +#define PMMIFG 0x012A /* PMM Interrupt Flag */ +#define PM5CTL0 0x0130 /* PMM Power Mode 5 Control Register 0 */ + +#define PMMPW (0xA500) /* PMM Register Write Password */ +#define PMMPW_H (0xA5) /* PMM Register Write Password for high word access */ + +/* PMMCTL0 Control Bits */ +#define PMMSWBOR (0x0004) /* PMM Software BOR */ +#define PMMSWPOR (0x0008) /* PMM Software POR */ +#define PMMREGOFF (0x0010) /* PMM Turn Regulator off */ +#define SVSHE (0x0040) /* SVS high side enable */ +#define PMMLPRST (0x0080) /* PMM Low-Power Reset Enable */ + +/* PMMCTL0 Control Bits */ +#define PMMSWBOR_L (0x0004) /* PMM Software BOR */ +#define PMMSWPOR_L (0x0008) /* PMM Software POR */ +#define PMMREGOFF_L (0x0010) /* PMM Turn Regulator off */ +#define SVSHE_L (0x0040) /* SVS high side enable */ +#define PMMLPRST_L (0x0080) /* PMM Low-Power Reset Enable */ + + +/* PMMIFG Control Bits */ +#define PMMBORIFG (0x0100) /* PMM Software BOR interrupt flag */ +#define PMMRSTIFG (0x0200) /* PMM RESET pin interrupt flag */ +#define PMMPORIFG (0x0400) /* PMM Software POR interrupt flag */ +#define SVSHIFG (0x2000) /* SVS low side interrupt flag */ +#define PMMLPM5IFG (0x8000) /* LPM5 indication Flag */ + +/* PMMIFG Control Bits */ +#define PMMBORIFG_H (0x0001) /* PMM Software BOR interrupt flag */ +#define PMMRSTIFG_H (0x0002) /* PMM RESET pin interrupt flag */ +#define PMMPORIFG_H (0x0004) /* PMM Software POR interrupt flag */ +#define SVSHIFG_H (0x0020) /* SVS low side interrupt flag */ +#define PMMLPM5IFG_H (0x0080) /* LPM5 indication Flag */ + + +/* PM5CTL0 Power Mode 5 Control Bits */ +#define LOCKLPM5 (0x0001) /* Lock I/O pin configuration upon entry/exit to/from LPM5 */ + +/* PM5CTL0 Power Mode 5 Control Bits */ +#define LOCKLPM5_L (0x0001) /* Lock I/O pin configuration upon entry/exit to/from LPM5 */ + + + +/************************************************************ +* DIGITAL I/O Port1/2 Pull up / Pull down Resistors +************************************************************/ + +#define PAIN 0x0200 /* Port A Input */ +#define PAOUT 0x0202 /* Port A Output */ +#define PADIR 0x0204 /* Port A Direction */ +#define PAREN 0x0206 /* Port A Resistor Enable */ +#define PASEL0 0x020A /* Port A Selection 0 */ +#define PASEL0_H (PASEL0) +#define PASEL1 0x020C /* Port A Selection 1 */ +#define PASEL1_H (PASEL1+1) +#define PASELC 0x0216 /* Port A Complement Selection */ +#define PAIES 0x0218 /* Port A Interrupt Edge Select */ +#define PAIE 0x021A /* Port A Interrupt Enable */ +#define PAIFG 0x021C /* Port A Interrupt Flag */ + +#define P1IV 0x020E /* Port 1 Interrupt Vector Word */ +#define P2IV 0x021E /* Port 2 Interrupt Vector Word */ +#define P1IN (PAIN_L) /* Port 1 Input */ +#define P1OUT (PAOUT_L) /* Port 1 Output */ +#define P1DIR (PADIR_L) /* Port 1 Direction */ +#define P1REN (PAREN_L) /* Port 1 Resistor Enable */ +#define P1SEL0 (PASEL0_L) /* Port 1 Selection 0 */ +#define P1SEL1 (PASEL1_L) /* Port 1 Selection 1 */ +#define P1SELC (PASELC_L) /* Port 1 Complement Selection */ +#define P1IES (PAIES_L) /* Port 1 Interrupt Edge Select */ +#define P1IE (PAIE_L) /* Port 1 Interrupt Enable */ +#define P1IFG (PAIFG_L) /* Port 1 Interrupt Flag */ + +//Definitions for P1IV +#define P1IV_NONE (0x0000) /* No Interrupt pending */ +#define P1IV_P1IFG0 (0x0002) /* P1IV P1IFG.0 */ +#define P1IV_P1IFG1 (0x0004) /* P1IV P1IFG.1 */ +#define P1IV_P1IFG2 (0x0006) /* P1IV P1IFG.2 */ +#define P1IV_P1IFG3 (0x0008) /* P1IV P1IFG.3 */ +#define P1IV_P1IFG4 (0x000A) /* P1IV P1IFG.4 */ +#define P1IV_P1IFG5 (0x000C) /* P1IV P1IFG.5 */ +#define P1IV_P1IFG6 (0x000E) /* P1IV P1IFG.6 */ +#define P1IV_P1IFG7 (0x0010) /* P1IV P1IFG.7 */ + + +#define P2IN (PAIN_H) /* Port 2 Input */ +#define P2OUT (PAOUT_H) /* Port 2 Output */ +#define P2DIR (PADIR_H) /* Port 2 Direction */ +#define P2REN (PAREN_H) /* Port 2 Resistor Enable */ +#define P2SEL0 (PASEL0_H) /* Port 2 Selection 0 */ +#define P2SEL1 (PASEL1_H) /* Port 2 Selection 1 */ +#define P2SELC (PASELC_H) /* Port 2 Complement Selection */ +#define P2IES (PAIES_H) /* Port 2 Interrupt Edge Select */ +#define P2IE (PAIE_H) /* Port 2 Interrupt Enable */ +#define P2IFG (PAIFG_H) /* Port 2 Interrupt Flag */ + +//Definitions for P2IV +#define P2IV_NONE (0x0000) /* No Interrupt pending */ +#define P2IV_P2IFG0 (0x0002) /* P2IV P2IFG.0 */ +#define P2IV_P2IFG1 (0x0004) /* P2IV P2IFG.1 */ +#define P2IV_P2IFG2 (0x0006) /* P2IV P2IFG.2 */ +#define P2IV_P2IFG3 (0x0008) /* P2IV P2IFG.3 */ +#define P2IV_P2IFG4 (0x000A) /* P2IV P2IFG.4 */ +#define P2IV_P2IFG5 (0x000C) /* P2IV P2IFG.5 */ +#define P2IV_P2IFG6 (0x000E) /* P2IV P2IFG.6 */ +#define P2IV_P2IFG7 (0x0010) /* P2IV P2IFG.7 */ + + + +/************************************************************ +* DIGITAL I/O Port3/4 Pull up / Pull down Resistors +************************************************************/ + +#define PBIN 0x0220 /* Port B Input */ +#define PBOUT 0x0222 /* Port B Output */ +#define PBDIR 0x0224 /* Port B Direction */ +#define PBREN 0x0226 /* Port B Resistor Enable */ +#define PBSEL0 0x022A /* Port B Selection 0 */ +#define PBSEL1 0x022C /* Port B Selection 1 */ +#define PBSELC 0x0236 /* Port B Complement Selection */ +#define PBIES 0x0238 /* Port B Interrupt Edge Select */ +#define PBIE 0x023A /* Port B Interrupt Enable */ +#define PBIFG 0x023C /* Port B Interrupt Flag */ + +#define P3IV 0x022E /* Port 3 Interrupt Vector Word */ +#define P4IV 0x023E /* Port 4 Interrupt Vector Word */ +#define P3IN (PBIN_L) /* Port 3 Input */ +#define P3OUT (PBOUT_L) /* Port 3 Output */ +#define P3DIR (PBDIR_L) /* Port 3 Direction */ +#define P3REN (PBREN_L) /* Port 3 Resistor Enable */ +#define P3SEL0 (PBSEL0_L) /* Port 3 Selection 0 */ +#define P3SEL1 (PBSEL1_L) /* Port 3 Selection 1 */ +#define P3SELC (PBSELC_L) /* Port 3 Complement Selection */ +#define P3IES (PBIES_L) /* Port 3 Interrupt Edge Select */ +#define P3IE (PBIE_L) /* Port 3 Interrupt Enable */ +#define P3IFG (PBIFG_L) /* Port 3 Interrupt Flag */ + +//Definitions for P3IV +#define P3IV_NONE (0x0000) /* No Interrupt pending */ +#define P3IV_P3IFG0 (0x0002) /* P3IV P3IFG.0 */ +#define P3IV_P3IFG1 (0x0004) /* P3IV P3IFG.1 */ +#define P3IV_P3IFG2 (0x0006) /* P3IV P3IFG.2 */ +#define P3IV_P3IFG3 (0x0008) /* P3IV P3IFG.3 */ +#define P3IV_P3IFG4 (0x000A) /* P3IV P3IFG.4 */ +#define P3IV_P3IFG5 (0x000C) /* P3IV P3IFG.5 */ +#define P3IV_P3IFG6 (0x000E) /* P3IV P3IFG.6 */ +#define P3IV_P3IFG7 (0x0010) /* P3IV P3IFG.7 */ + + +#define P4IN (PBIN_H) /* Port 4 Input */ +#define P4OUT (PBOUT_H) /* Port 4 Output */ +#define P4DIR (PBDIR_H) /* Port 4 Direction */ +#define P4REN (PBREN_H) /* Port 4 Resistor Enable */ +#define P4SEL0 (PBSEL0_H) /* Port 4 Selection 0 */ +#define P4SEL1 (PBSEL1_H) /* Port 4 Selection 1 */ +#define P4SELC (PBSELC_H) /* Port 4 Complement Selection */ +#define P4IES (PBIES_H) /* Port 4 Interrupt Edge Select */ +#define P4IE (PBIE_H) /* Port 4 Interrupt Enable */ +#define P4IFG (PBIFG_H) /* Port 4 Interrupt Flag */ + +//Definitions for P4IV +#define P4IV_NONE (0x0000) /* No Interrupt pending */ +#define P4IV_P4IFG0 (0x0002) /* P4IV P4IFG.0 */ +#define P4IV_P4IFG1 (0x0004) /* P4IV P4IFG.1 */ +#define P4IV_P4IFG2 (0x0006) /* P4IV P4IFG.2 */ +#define P4IV_P4IFG3 (0x0008) /* P4IV P4IFG.3 */ +#define P4IV_P4IFG4 (0x000A) /* P4IV P4IFG.4 */ +#define P4IV_P4IFG5 (0x000C) /* P4IV P4IFG.5 */ +#define P4IV_P4IFG6 (0x000E) /* P4IV P4IFG.6 */ +#define P4IV_P4IFG7 (0x0010) /* P4IV P4IFG.7 */ + + + +/************************************************************ +* DIGITAL I/O PortJ Pull up / Pull down Resistors +************************************************************/ + +#define PJIN 0x0320 /* Port J Input */ +#define PJOUT 0x0322 /* Port J Output */ +#define PJDIR 0x0324 /* Port J Direction */ +#define PJREN 0x0326 /* Port J Resistor Enable */ +#define PJSEL0 0x032A /* Port J Selection 0 */ +#define PJSEL1 0x032C /* Port J Selection 1 */ +#define PJSELC 0x0336 /* Port J Complement Selection */ + +/************************************************************ +* Shared Reference +************************************************************/ + +#define REFCTL0 0x01B0 /* REF Shared Reference control register 0 */ + +/* REFCTL0 Control Bits */ +#define REFON (0x0001) /* REF Reference On */ +#define REFOUT (0x0002) /* REF Reference output Buffer On */ +//#define RESERVED (0x0004) /* Reserved */ +#define REFTCOFF (0x0008) /* REF Temp.Sensor off */ +#define REFVSEL0 (0x0010) /* REF Reference Voltage Level Select Bit:0 */ +#define REFVSEL1 (0x0020) /* REF Reference Voltage Level Select Bit:1 */ +#define REFGENOT (0x0040) /* REF Reference generator one-time trigger */ +#define REFBGOT (0x0080) /* REF Bandgap and bandgap buffer one-time trigger */ +#define REFGENACT (0x0100) /* REF Reference generator active */ +#define REFBGACT (0x0200) /* REF Reference bandgap active */ +#define REFGENBUSY (0x0400) /* REF Reference generator busy */ +#define BGMODE (0x0800) /* REF Bandgap mode */ +#define REFGENRDY (0x1000) /* REF Reference generator ready */ +#define REFBGRDY (0x2000) /* REF Reference bandgap ready */ +//#define RESERVED (0x4000) /* Reserved */ +//#define RESERVED (0x8000) /* Reserved */ + +/* REFCTL0 Control Bits */ +#define REFON_L (0x0001) /* REF Reference On */ +#define REFOUT_L (0x0002) /* REF Reference output Buffer On */ +//#define RESERVED (0x0004) /* Reserved */ +#define REFTCOFF_L (0x0008) /* REF Temp.Sensor off */ +#define REFVSEL0_L (0x0010) /* REF Reference Voltage Level Select Bit:0 */ +#define REFVSEL1_L (0x0020) /* REF Reference Voltage Level Select Bit:1 */ +#define REFGENOT_L (0x0040) /* REF Reference generator one-time trigger */ +#define REFBGOT_L (0x0080) /* REF Bandgap and bandgap buffer one-time trigger */ +//#define RESERVED (0x4000) /* Reserved */ +//#define RESERVED (0x8000) /* Reserved */ + +/* REFCTL0 Control Bits */ +//#define RESERVED (0x0004) /* Reserved */ +#define REFGENACT_H (0x0001) /* REF Reference generator active */ +#define REFBGACT_H (0x0002) /* REF Reference bandgap active */ +#define REFGENBUSY_H (0x0004) /* REF Reference generator busy */ +#define BGMODE_H (0x0008) /* REF Bandgap mode */ +#define REFGENRDY_H (0x0010) /* REF Reference generator ready */ +#define REFBGRDY_H (0x0020) /* REF Reference bandgap ready */ +//#define RESERVED (0x4000) /* Reserved */ +//#define RESERVED (0x8000) /* Reserved */ + +#define REFVSEL_0 (0x0000) /* REF Reference Voltage Level Select 1.2V */ +#define REFVSEL_1 (0x0010) /* REF Reference Voltage Level Select 2.0V */ +#define REFVSEL_2 (0x0020) /* REF Reference Voltage Level Select 2.5V */ +#define REFVSEL_3 (0x0030) /* REF Reference Voltage Level Select 2.5V */ + +/************************************************************ +* Real Time Clock +************************************************************/ + +#define RTCCTL01 0x04A0 /* Real Timer Control 0/1 */ +#define RTCCTL23 0x04A2 /* Real Timer Control 2/3 */ +#define RTCPS0CTL 0x04A8 /* Real Timer Prescale Timer 0 Control */ +#define RTCPS1CTL 0x04AA /* Real Timer Prescale Timer 1 Control */ +#define RTCPS 0x04AC /* Real Timer Prescale Timer Control */ +#define RTCIV 0x04AE /* Real Time Clock Interrupt Vector */ +#define RTCTIM0 0x04B0 /* Real Time Clock Time 0 */ +#define RTCTIM1 0x04B2 /* Real Time Clock Time 1 */ +#define RTCDATE 0x04B4 /* Real Time Clock Date */ +#define RTCYEAR 0x04B6 /* Real Time Clock Year */ +#define RTCAMINHR 0x04B8 /* Real Time Clock Alarm Min/Hour */ +#define RTCADOWDAY 0x04BA /* Real Time Clock Alarm day of week/day */ +#define BIN2BCD 0x04BC /* Real Time Binary-to-BCD conversion register */ +#define BCD2BIN 0x04BE /* Real Time BCD-to-binary conversion register */ + +#define RTCCTL0 RTCCTL01_L /* Real Time Clock Control 0 */ +#define RTCCTL1 RTCCTL01_H /* Real Time Clock Control 1 */ +#define RTCCTL2 RTCCTL23_L /* Real Time Clock Control 2 */ +#define RTCCTL3 RTCCTL23_H /* Real Time Clock Control 3 */ +#define RTCNT12 RTCTIM0 +#define RTCNT34 RTCTIM1 +#define RTCNT1 RTCTIM0_L +#define RTCNT2 RTCTIM0_H +#define RTCNT3 RTCTIM1_L +#define RTCNT4 RTCTIM1_H +#define RTCSEC RTCTIM0_L +#define RTCMIN RTCTIM0_H +#define RTCHOUR RTCTIM1_L +#define RTCDOW RTCTIM1_H +#define RTCDAY RTCDATE_L +#define RTCMON RTCDATE_H +#define RTCYEARL RTCYEAR_L +#define RTCYEARH RTCYEAR_H +#define RT0PS RTCPS_L +#define RT1PS RTCPS_H +#define RTCAMIN RTCAMINHR_L /* Real Time Clock Alarm Min */ +#define RTCAHOUR RTCAMINHR_H /* Real Time Clock Alarm Hour */ +#define RTCADOW RTCADOWDAY_L /* Real Time Clock Alarm day of week */ +#define RTCADAY RTCADOWDAY_H /* Real Time Clock Alarm day */ + +/* RTCCTL01 Control Bits */ +#define RTCBCD (0x8000) /* RTC BCD 0:Binary / 1:BCD */ +#define RTCHOLD (0x4000) /* RTC Hold */ +//#define RESERVED (0x2000) /* RESERVED */ +#define RTCRDY (0x1000) /* RTC Ready */ +//#define RESERVED (0x0800) /* RESERVED */ +//#define RESERVED (0x0400) /* RESERVED */ +#define RTCTEV1 (0x0200) /* RTC Time Event 1 */ +#define RTCTEV0 (0x0100) /* RTC Time Event 0 */ +#define RTCOFIE (0x0080) /* RTC 32kHz cyrstal oscillator fault interrupt enable */ +#define RTCTEVIE (0x0040) /* RTC Time Event Interrupt Enable Flag */ +#define RTCAIE (0x0020) /* RTC Alarm Interrupt Enable Flag */ +#define RTCRDYIE (0x0010) /* RTC Ready Interrupt Enable Flag */ +#define RTCOFIFG (0x0008) /* RTC 32kHz cyrstal oscillator fault interrupt flag */ +#define RTCTEVIFG (0x0004) /* RTC Time Event Interrupt Flag */ +#define RTCAIFG (0x0002) /* RTC Alarm Interrupt Flag */ +#define RTCRDYIFG (0x0001) /* RTC Ready Interrupt Flag */ + +/* RTCCTL01 Control Bits */ +//#define RESERVED (0x2000) /* RESERVED */ +//#define RESERVED (0x0800) /* RESERVED */ +//#define RESERVED (0x0400) /* RESERVED */ +#define RTCOFIE_L (0x0080) /* RTC 32kHz cyrstal oscillator fault interrupt enable */ +#define RTCTEVIE_L (0x0040) /* RTC Time Event Interrupt Enable Flag */ +#define RTCAIE_L (0x0020) /* RTC Alarm Interrupt Enable Flag */ +#define RTCRDYIE_L (0x0010) /* RTC Ready Interrupt Enable Flag */ +#define RTCOFIFG_L (0x0008) /* RTC 32kHz cyrstal oscillator fault interrupt flag */ +#define RTCTEVIFG_L (0x0004) /* RTC Time Event Interrupt Flag */ +#define RTCAIFG_L (0x0002) /* RTC Alarm Interrupt Flag */ +#define RTCRDYIFG_L (0x0001) /* RTC Ready Interrupt Flag */ + +/* RTCCTL01 Control Bits */ +#define RTCBCD_H (0x0080) /* RTC BCD 0:Binary / 1:BCD */ +#define RTCHOLD_H (0x0040) /* RTC Hold */ +//#define RESERVED (0x2000) /* RESERVED */ +#define RTCRDY_H (0x0010) /* RTC Ready */ +//#define RESERVED (0x0800) /* RESERVED */ +//#define RESERVED (0x0400) /* RESERVED */ +#define RTCTEV1_H (0x0002) /* RTC Time Event 1 */ +#define RTCTEV0_H (0x0001) /* RTC Time Event 0 */ + +#define RTCTEV_0 (0x0000) /* RTC Time Event: 0 (Min. changed) */ +#define RTCTEV_1 (0x0100) /* RTC Time Event: 1 (Hour changed) */ +#define RTCTEV_2 (0x0200) /* RTC Time Event: 2 (12:00 changed) */ +#define RTCTEV_3 (0x0300) /* RTC Time Event: 3 (00:00 changed) */ +#define RTCTEV__MIN (0x0000) /* RTC Time Event: 0 (Min. changed) */ +#define RTCTEV__HOUR (0x0100) /* RTC Time Event: 1 (Hour changed) */ +#define RTCTEV__0000 (0x0200) /* RTC Time Event: 2 (00:00 changed) */ +#define RTCTEV__1200 (0x0300) /* RTC Time Event: 3 (12:00 changed) */ + +/* RTCCTL23 Control Bits */ +#define RTCCALF1 (0x0200) /* RTC Calibration Frequency Bit 1 */ +#define RTCCALF0 (0x0100) /* RTC Calibration Frequency Bit 0 */ +#define RTCCALS (0x0080) /* RTC Calibration Sign */ +//#define Reserved (0x0040) +#define RTCCAL5 (0x0020) /* RTC Calibration Bit 5 */ +#define RTCCAL4 (0x0010) /* RTC Calibration Bit 4 */ +#define RTCCAL3 (0x0008) /* RTC Calibration Bit 3 */ +#define RTCCAL2 (0x0004) /* RTC Calibration Bit 2 */ +#define RTCCAL1 (0x0002) /* RTC Calibration Bit 1 */ +#define RTCCAL0 (0x0001) /* RTC Calibration Bit 0 */ + +/* RTCCTL23 Control Bits */ +#define RTCCALS_L (0x0080) /* RTC Calibration Sign */ +//#define Reserved (0x0040) +#define RTCCAL5_L (0x0020) /* RTC Calibration Bit 5 */ +#define RTCCAL4_L (0x0010) /* RTC Calibration Bit 4 */ +#define RTCCAL3_L (0x0008) /* RTC Calibration Bit 3 */ +#define RTCCAL2_L (0x0004) /* RTC Calibration Bit 2 */ +#define RTCCAL1_L (0x0002) /* RTC Calibration Bit 1 */ +#define RTCCAL0_L (0x0001) /* RTC Calibration Bit 0 */ + +/* RTCCTL23 Control Bits */ +#define RTCCALF1_H (0x0002) /* RTC Calibration Frequency Bit 1 */ +#define RTCCALF0_H (0x0001) /* RTC Calibration Frequency Bit 0 */ +//#define Reserved (0x0040) + +#define RTCCALF_0 (0x0000) /* RTC Calibration Frequency: No Output */ +#define RTCCALF_1 (0x0100) /* RTC Calibration Frequency: 512 Hz */ +#define RTCCALF_2 (0x0200) /* RTC Calibration Frequency: 256 Hz */ +#define RTCCALF_3 (0x0300) /* RTC Calibration Frequency: 1 Hz */ + + +#define RTCAE (0x80) /* Real Time Clock Alarm enable */ + + + + +/* RTCPS0CTL Control Bits */ +//#define Reserved (0x0080) +//#define Reserved (0x0040) +//#define Reserved (0x0020) +#define RT0IP2 (0x0010) /* RTC Prescale Timer 0 Interrupt Interval Bit: 2 */ +#define RT0IP1 (0x0008) /* RTC Prescale Timer 0 Interrupt Interval Bit: 1 */ +#define RT0IP0 (0x0004) /* RTC Prescale Timer 0 Interrupt Interval Bit: 0 */ +#define RT0PSIE (0x0002) /* RTC Prescale Timer 0 Interrupt Enable Flag */ +#define RT0PSIFG (0x0001) /* RTC Prescale Timer 0 Interrupt Flag */ + +/* RTCPS0CTL Control Bits */ +//#define Reserved (0x0080) +//#define Reserved (0x0040) +//#define Reserved (0x0020) +#define RT0IP2_L (0x0010) /* RTC Prescale Timer 0 Interrupt Interval Bit: 2 */ +#define RT0IP1_L (0x0008) /* RTC Prescale Timer 0 Interrupt Interval Bit: 1 */ +#define RT0IP0_L (0x0004) /* RTC Prescale Timer 0 Interrupt Interval Bit: 0 */ +#define RT0PSIE_L (0x0002) /* RTC Prescale Timer 0 Interrupt Enable Flag */ +#define RT0PSIFG_L (0x0001) /* RTC Prescale Timer 0 Interrupt Flag */ + + +#define RT0IP_0 (0x0000) /* RTC Prescale Timer 0 Interrupt Interval /2 */ +#define RT0IP_1 (0x0004) /* RTC Prescale Timer 0 Interrupt Interval /4 */ +#define RT0IP_2 (0x0008) /* RTC Prescale Timer 0 Interrupt Interval /8 */ +#define RT0IP_3 (0x000C) /* RTC Prescale Timer 0 Interrupt Interval /16 */ +#define RT0IP_4 (0x0010) /* RTC Prescale Timer 0 Interrupt Interval /32 */ +#define RT0IP_5 (0x0014) /* RTC Prescale Timer 0 Interrupt Interval /64 */ +#define RT0IP_6 (0x0018) /* RTC Prescale Timer 0 Interrupt Interval /128 */ +#define RT0IP_7 (0x001C) /* RTC Prescale Timer 0 Interrupt Interval /256 */ + +#define RT0IP__2 (0x0000) /* RTC Prescale Timer 0 Interrupt Interval /2 */ +#define RT0IP__4 (0x0004) /* RTC Prescale Timer 0 Interrupt Interval /4 */ +#define RT0IP__8 (0x0008) /* RTC Prescale Timer 0 Interrupt Interval /8 */ +#define RT0IP__16 (0x000C) /* RTC Prescale Timer 0 Interrupt Interval /16 */ +#define RT0IP__32 (0x0010) /* RTC Prescale Timer 0 Interrupt Interval /32 */ +#define RT0IP__64 (0x0014) /* RTC Prescale Timer 0 Interrupt Interval /64 */ +#define RT0IP__128 (0x0018) /* RTC Prescale Timer 0 Interrupt Interval /128 */ +#define RT0IP__256 (0x001C) /* RTC Prescale Timer 0 Interrupt Interval /256 */ + + +/* RTCPS1CTL Control Bits */ +//#define Reserved (0x0080) +//#define Reserved (0x0040) +//#define Reserved (0x0020) +#define RT1IP2 (0x0010) /* RTC Prescale Timer 1 Interrupt Interval Bit: 2 */ +#define RT1IP1 (0x0008) /* RTC Prescale Timer 1 Interrupt Interval Bit: 1 */ +#define RT1IP0 (0x0004) /* RTC Prescale Timer 1 Interrupt Interval Bit: 0 */ +#define RT1PSIE (0x0002) /* RTC Prescale Timer 1 Interrupt Enable Flag */ +#define RT1PSIFG (0x0001) /* RTC Prescale Timer 1 Interrupt Flag */ + +/* RTCPS1CTL Control Bits */ +//#define Reserved (0x0080) +//#define Reserved (0x0040) +//#define Reserved (0x0020) +#define RT1IP2_L (0x0010) /* RTC Prescale Timer 1 Interrupt Interval Bit: 2 */ +#define RT1IP1_L (0x0008) /* RTC Prescale Timer 1 Interrupt Interval Bit: 1 */ +#define RT1IP0_L (0x0004) /* RTC Prescale Timer 1 Interrupt Interval Bit: 0 */ +#define RT1PSIE_L (0x0002) /* RTC Prescale Timer 1 Interrupt Enable Flag */ +#define RT1PSIFG_L (0x0001) /* RTC Prescale Timer 1 Interrupt Flag */ + + +#define RT1IP_0 (0x0000) /* RTC Prescale Timer 1 Interrupt Interval /2 */ +#define RT1IP_1 (0x0004) /* RTC Prescale Timer 1 Interrupt Interval /4 */ +#define RT1IP_2 (0x0008) /* RTC Prescale Timer 1 Interrupt Interval /8 */ +#define RT1IP_3 (0x000C) /* RTC Prescale Timer 1 Interrupt Interval /16 */ +#define RT1IP_4 (0x0010) /* RTC Prescale Timer 1 Interrupt Interval /32 */ +#define RT1IP_5 (0x0014) /* RTC Prescale Timer 1 Interrupt Interval /64 */ +#define RT1IP_6 (0x0018) /* RTC Prescale Timer 1 Interrupt Interval /128 */ +#define RT1IP_7 (0x001C) /* RTC Prescale Timer 1 Interrupt Interval /256 */ + +#define RT1IP__2 (0x0000) /* RTC Prescale Timer 1 Interrupt Interval /2 */ +#define RT1IP__4 (0x0004) /* RTC Prescale Timer 1 Interrupt Interval /4 */ +#define RT1IP__8 (0x0008) /* RTC Prescale Timer 1 Interrupt Interval /8 */ +#define RT1IP__16 (0x000C) /* RTC Prescale Timer 1 Interrupt Interval /16 */ +#define RT1IP__32 (0x0010) /* RTC Prescale Timer 1 Interrupt Interval /32 */ +#define RT1IP__64 (0x0014) /* RTC Prescale Timer 1 Interrupt Interval /64 */ +#define RT1IP__128 (0x0018) /* RTC Prescale Timer 1 Interrupt Interval /128 */ +#define RT1IP__256 (0x001C) /* RTC Prescale Timer 1 Interrupt Interval /256 */ + + +/* RTC Definitions */ +#define RTCIV_NONE (0x0000) /* No Interrupt pending */ +#define RTCIV_RTCRDYIFG (0x0002) /* RTC ready: RTCRDYIFG */ +#define RTCIV_RTCTEVIFG (0x0004) /* RTC interval timer: RTCTEVIFG */ +#define RTCIV_RTCAIFG (0x0006) /* RTC user alarm: RTCAIFG */ +#define RTCIV_RT0PSIFG (0x0008) /* RTC prescaler 0: RT0PSIFG */ +#define RTCIV_RT1PSIFG (0x000A) /* RTC prescaler 1: RT1PSIFG */ +#define RTCIV_RTCOFIFG (0x000C) /* RTC Oscillator fault */ + +/* Legacy Definitions */ +#define RTC_NONE (0x0000) /* No Interrupt pending */ +#define RTC_RTCRDYIFG (0x0002) /* RTC ready: RTCRDYIFG */ +#define RTC_RTCTEVIFG (0x0004) /* RTC interval timer: RTCTEVIFG */ +#define RTC_RTCAIFG (0x0006) /* RTC user alarm: RTCAIFG */ +#define RTC_RT0PSIFG (0x0008) /* RTC prescaler 0: RT0PSIFG */ +#define RTC_RT1PSIFG (0x000A) /* RTC prescaler 1: RT1PSIFG */ +#define RTC_RTCOFIFG (0x000C) /* RTC Oscillator fault */ + +/************************************************************ +* SFR - Special Function Register Module +************************************************************/ + +#define SFRIE1 0x0100 /* Interrupt Enable 1 */ + +/* SFRIE1 Control Bits */ +#define WDTIE (0x0001) /* WDT Interrupt Enable */ +#define OFIE (0x0002) /* Osc Fault Enable */ +//#define Reserved (0x0004) +#define VMAIE (0x0008) /* Vacant Memory Interrupt Enable */ +#define NMIIE (0x0010) /* NMI Interrupt Enable */ +#define JMBINIE (0x0040) /* JTAG Mail Box input Interrupt Enable */ +#define JMBOUTIE (0x0080) /* JTAG Mail Box output Interrupt Enable */ + +#define WDTIE_L (0x0001) /* WDT Interrupt Enable */ +#define OFIE_L (0x0002) /* Osc Fault Enable */ +//#define Reserved (0x0004) +#define VMAIE_L (0x0008) /* Vacant Memory Interrupt Enable */ +#define NMIIE_L (0x0010) /* NMI Interrupt Enable */ +#define JMBINIE_L (0x0040) /* JTAG Mail Box input Interrupt Enable */ +#define JMBOUTIE_L (0x0080) /* JTAG Mail Box output Interrupt Enable */ + + +#define SFRIFG1 0x0102 /* Interrupt Flag 1 */ +/* SFRIFG1 Control Bits */ +#define WDTIFG (0x0001) /* WDT Interrupt Flag */ +#define OFIFG (0x0002) /* Osc Fault Flag */ +//#define Reserved (0x0004) +#define VMAIFG (0x0008) /* Vacant Memory Interrupt Flag */ +#define NMIIFG (0x0010) /* NMI Interrupt Flag */ +//#define Reserved (0x0020) +#define JMBINIFG (0x0040) /* JTAG Mail Box input Interrupt Flag */ +#define JMBOUTIFG (0x0080) /* JTAG Mail Box output Interrupt Flag */ + +#define WDTIFG_L (0x0001) /* WDT Interrupt Flag */ +#define OFIFG_L (0x0002) /* Osc Fault Flag */ +//#define Reserved (0x0004) +#define VMAIFG_L (0x0008) /* Vacant Memory Interrupt Flag */ +#define NMIIFG_L (0x0010) /* NMI Interrupt Flag */ +//#define Reserved (0x0020) +#define JMBINIFG_L (0x0040) /* JTAG Mail Box input Interrupt Flag */ +#define JMBOUTIFG_L (0x0080) /* JTAG Mail Box output Interrupt Flag */ + + +#define SFRRPCR 0x0104 /* RESET Pin Control Register */ +/* SFRRPCR Control Bits */ +#define SYSNMI (0x0001) /* NMI select */ +#define SYSNMIIES (0x0002) /* NMI edge select */ +#define SYSRSTUP (0x0004) /* RESET Pin pull down/up select */ +#define SYSRSTRE (0x0008) /* RESET Pin Resistor enable */ + +#define SYSNMI_L (0x0001) /* NMI select */ +#define SYSNMIIES_L (0x0002) /* NMI edge select */ +#define SYSRSTUP_L (0x0004) /* RESET Pin pull down/up select */ +#define SYSRSTRE_L (0x0008) /* RESET Pin Resistor enable */ + + +/************************************************************ +* SYS - System Module +************************************************************/ + +#define SYSCTL 0x0180 /* System control */ +#define SYSJMBC 0x0186 /* JTAG mailbox control */ +#define SYSJMBI0 0x0188 /* JTAG mailbox input 0 */ +#define SYSJMBI1 0x018A /* JTAG mailbox input 1 */ +#define SYSJMBO0 0x018C /* JTAG mailbox output 0 */ +#define SYSJMBO1 0x018E /* JTAG mailbox output 1 */ + +#define SYSUNIV 0x019A /* User NMI vector generator */ +#define SYSSNIV 0x019C /* System NMI vector generator */ +#define SYSRSTIV 0x019E /* Reset vector generator */ + +/* SYSCTL Control Bits */ +#define SYSRIVECT (0x0001) /* SYS - RAM based interrupt vectors */ +//#define RESERVED (0x0002) /* SYS - Reserved */ +#define SYSPMMPE (0x0004) /* SYS - PMM access protect */ +//#define RESERVED (0x0008) /* SYS - Reserved */ +#define SYSBSLIND (0x0010) /* SYS - TCK/RST indication detected */ +#define SYSJTAGPIN (0x0020) /* SYS - Dedicated JTAG pins enabled */ +//#define RESERVED (0x0040) /* SYS - Reserved */ +//#define RESERVED (0x0080) /* SYS - Reserved */ +//#define RESERVED (0x0100) /* SYS - Reserved */ +//#define RESERVED (0x0200) /* SYS - Reserved */ +//#define RESERVED (0x0400) /* SYS - Reserved */ +//#define RESERVED (0x0800) /* SYS - Reserved */ +//#define RESERVED (0x1000) /* SYS - Reserved */ +//#define RESERVED (0x2000) /* SYS - Reserved */ +//#define RESERVED (0x4000) /* SYS - Reserved */ +//#define RESERVED (0x8000) /* SYS - Reserved */ + +/* SYSCTL Control Bits */ +#define SYSRIVECT_L (0x0001) /* SYS - RAM based interrupt vectors */ +//#define RESERVED (0x0002) /* SYS - Reserved */ +#define SYSPMMPE_L (0x0004) /* SYS - PMM access protect */ +//#define RESERVED (0x0008) /* SYS - Reserved */ +#define SYSBSLIND_L (0x0010) /* SYS - TCK/RST indication detected */ +#define SYSJTAGPIN_L (0x0020) /* SYS - Dedicated JTAG pins enabled */ +//#define RESERVED (0x0040) /* SYS - Reserved */ +//#define RESERVED (0x0080) /* SYS - Reserved */ +//#define RESERVED (0x0100) /* SYS - Reserved */ +//#define RESERVED (0x0200) /* SYS - Reserved */ +//#define RESERVED (0x0400) /* SYS - Reserved */ +//#define RESERVED (0x0800) /* SYS - Reserved */ +//#define RESERVED (0x1000) /* SYS - Reserved */ +//#define RESERVED (0x2000) /* SYS - Reserved */ +//#define RESERVED (0x4000) /* SYS - Reserved */ +//#define RESERVED (0x8000) /* SYS - Reserved */ + + +/* SYSJMBC Control Bits */ +#define JMBIN0FG (0x0001) /* SYS - Incoming JTAG Mailbox 0 Flag */ +#define JMBIN1FG (0x0002) /* SYS - Incoming JTAG Mailbox 1 Flag */ +#define JMBOUT0FG (0x0004) /* SYS - Outgoing JTAG Mailbox 0 Flag */ +#define JMBOUT1FG (0x0008) /* SYS - Outgoing JTAG Mailbox 1 Flag */ +#define JMBMODE (0x0010) /* SYS - JMB 16/32 Bit Mode */ +//#define RESERVED (0x0020) /* SYS - Reserved */ +#define JMBCLR0OFF (0x0040) /* SYS - Incoming JTAG Mailbox 0 Flag auto-clear disalbe */ +#define JMBCLR1OFF (0x0080) /* SYS - Incoming JTAG Mailbox 1 Flag auto-clear disalbe */ +//#define RESERVED (0x0100) /* SYS - Reserved */ +//#define RESERVED (0x0200) /* SYS - Reserved */ +//#define RESERVED (0x0400) /* SYS - Reserved */ +//#define RESERVED (0x0800) /* SYS - Reserved */ +//#define RESERVED (0x1000) /* SYS - Reserved */ +//#define RESERVED (0x2000) /* SYS - Reserved */ +//#define RESERVED (0x4000) /* SYS - Reserved */ +//#define RESERVED (0x8000) /* SYS - Reserved */ + +/* SYSJMBC Control Bits */ +#define JMBIN0FG_L (0x0001) /* SYS - Incoming JTAG Mailbox 0 Flag */ +#define JMBIN1FG_L (0x0002) /* SYS - Incoming JTAG Mailbox 1 Flag */ +#define JMBOUT0FG_L (0x0004) /* SYS - Outgoing JTAG Mailbox 0 Flag */ +#define JMBOUT1FG_L (0x0008) /* SYS - Outgoing JTAG Mailbox 1 Flag */ +#define JMBMODE_L (0x0010) /* SYS - JMB 16/32 Bit Mode */ +//#define RESERVED (0x0020) /* SYS - Reserved */ +#define JMBCLR0OFF_L (0x0040) /* SYS - Incoming JTAG Mailbox 0 Flag auto-clear disalbe */ +#define JMBCLR1OFF_L (0x0080) /* SYS - Incoming JTAG Mailbox 1 Flag auto-clear disalbe */ +//#define RESERVED (0x0100) /* SYS - Reserved */ +//#define RESERVED (0x0200) /* SYS - Reserved */ +//#define RESERVED (0x0400) /* SYS - Reserved */ +//#define RESERVED (0x0800) /* SYS - Reserved */ +//#define RESERVED (0x1000) /* SYS - Reserved */ +//#define RESERVED (0x2000) /* SYS - Reserved */ +//#define RESERVED (0x4000) /* SYS - Reserved */ +//#define RESERVED (0x8000) /* SYS - Reserved */ + + + + + + + + +/* SYSUNIV Definitions */ +#define SYSUNIV_NONE (0x0000) /* No Interrupt pending */ +#define SYSUNIV_NMIIFG (0x0002) /* SYSUNIV : NMIIFG */ +#define SYSUNIV_OFIFG (0x0004) /* SYSUNIV : Osc. Fail - OFIFG */ + +/* SYSSNIV Definitions */ +#define SYSSNIV_NONE (0x0000) /* No Interrupt pending */ +#define SYSSNIV_RES02 (0x0002) /* SYSSNIV : Reserved */ +#define SYSSNIV_UBDIFG (0x0004) /* SYSSNIV : FRAM Uncorrectable bit Error */ +#define SYSSNIV_RES06 (0x0006) /* SYSSNIV : Reserved */ +#define SYSSNIV_MPUSEGPIFG (0x0008) /* SYSSNIV : MPUSEGPIFG violation */ +#define SYSSNIV_MPUSEGIIFG (0x000A) /* SYSSNIV : MPUSEGIIFG violation */ +#define SYSSNIV_MPUSEG1IFG (0x000C) /* SYSSNIV : MPUSEG1IFG violation */ +#define SYSSNIV_MPUSEG2IFG (0x000E) /* SYSSNIV : MPUSEG2IFG violation */ +#define SYSSNIV_MPUSEG3IFG (0x0010) /* SYSSNIV : MPUSEG3IFG violation */ +#define SYSSNIV_VMAIFG (0x0012) /* SYSSNIV : VMAIFG */ +#define SYSSNIV_JMBINIFG (0x0014) /* SYSSNIV : JMBINIFG */ +#define SYSSNIV_JMBOUTIFG (0x0016) /* SYSSNIV : JMBOUTIFG */ +#define SYSSNIV_CBDIFG (0x0018) /* SYSSNIV : FRAM Correctable Bit error */ + +/* SYSRSTIV Definitions */ +#define SYSRSTIV_NONE (0x0000) /* No Interrupt pending */ +#define SYSRSTIV_BOR (0x0002) /* SYSRSTIV : BOR */ +#define SYSRSTIV_RSTNMI (0x0004) /* SYSRSTIV : RST/NMI */ +#define SYSRSTIV_DOBOR (0x0006) /* SYSRSTIV : Do BOR */ +#define SYSRSTIV_LPM5WU (0x0008) /* SYSRSTIV : Port LPM5 Wake Up */ +#define SYSRSTIV_SECYV (0x000A) /* SYSRSTIV : Security violation */ +#define SYSRSTIV_RES0C (0x000C) /* SYSRSTIV : Reserved */ +#define SYSRSTIV_SVSHIFG (0x000E) /* SYSRSTIV : SVSHIFG */ +#define SYSRSTIV_RES10 (0x0010) /* SYSRSTIV : Reserved */ +#define SYSRSTIV_RES12 (0x0012) /* SYSRSTIV : Reserved */ +#define SYSRSTIV_DOPOR (0x0014) /* SYSRSTIV : Do POR */ +#define SYSRSTIV_WDTTO (0x0016) /* SYSRSTIV : WDT Time out */ +#define SYSRSTIV_WDTKEY (0x0018) /* SYSRSTIV : WDTKEY violation */ +#define SYSRSTIV_FRCTLPW (0x001A) /* SYSRSTIV : FRAM Key violation */ +#define SYSRSTIV_UBDIFG (0x001C) /* SYSRSTIV : FRAM Uncorrectable bit Error */ +#define SYSRSTIV_PERF (0x001E) /* SYSRSTIV : peripheral/config area fetch */ +#define SYSRSTIV_PMMPW (0x0020) /* SYSRSTIV : PMM Password violation */ +#define SYSRSTIV_MPUPW (0x0022) /* SYSRSTIV : MPU Password violation */ +#define SYSRSTIV_CSPW (0x0024) /* SYSRSTIV : CS Password violation */ +#define SYSRSTIV_MPUSEGPIFG (0x0026) /* SYSRSTIV : MPUSEGPIFG violation */ +#define SYSRSTIV_MPUSEGIIFG (0x0028) /* SYSRSTIV : MPUSEGIIFG violation */ +#define SYSRSTIV_MPUSEG1IFG (0x002A) /* SYSRSTIV : MPUSEG1IFG violation */ +#define SYSRSTIV_MPUSEG2IFG (0x002C) /* SYSRSTIV : MPUSEG2IFG violation */ +#define SYSRSTIV_MPUSEG3IFG (0x002E) /* SYSRSTIV : MPUSEG3IFG violation */ +#define SYSRSTIV_ACCTEIFG (0x0030) /* SYSRSTIV : ACCTEIFG access time error */ + +/************************************************************ +* Timer0_A3 +************************************************************/ + +#define TA0CTL 0x0340 /* Timer0_A3 Control */ +#define TA0CCTL0 0x0342 /* Timer0_A3 Capture/Compare Control 0 */ +#define TA0CCTL1 0x0344 /* Timer0_A3 Capture/Compare Control 1 */ +#define TA0CCTL2 0x0346 /* Timer0_A3 Capture/Compare Control 2 */ +#define TA0R 0x0350 /* Timer0_A3 */ +#define TA0CCR0 0x0352 /* Timer0_A3 Capture/Compare 0 */ +#define TA0CCR1 0x0354 /* Timer0_A3 Capture/Compare 1 */ +#define TA0CCR2 0x0356 /* Timer0_A3 Capture/Compare 2 */ +#define TA0IV 0x036E /* Timer0_A3 Interrupt Vector Word */ +#define TA0EX0 0x0360 /* Timer0_A3 Expansion Register 0 */ + +/* TAxCTL Control Bits */ +#define TASSEL1 (0x0200) /* Timer A clock source select 1 */ +#define TASSEL0 (0x0100) /* Timer A clock source select 0 */ +#define ID1 (0x0080) /* Timer A clock input divider 1 */ +#define ID0 (0x0040) /* Timer A clock input divider 0 */ +#define MC1 (0x0020) /* Timer A mode control 1 */ +#define MC0 (0x0010) /* Timer A mode control 0 */ +#define TACLR (0x0004) /* Timer A counter clear */ +#define TAIE (0x0002) /* Timer A counter interrupt enable */ +#define TAIFG (0x0001) /* Timer A counter interrupt flag */ + +#define MC_0 (0x0000) /* Timer A mode control: 0 - Stop */ +#define MC_1 (0x0010) /* Timer A mode control: 1 - Up to CCR0 */ +#define MC_2 (0x0020) /* Timer A mode control: 2 - Continuous up */ +#define MC_3 (0x0030) /* Timer A mode control: 3 - Up/Down */ +#define ID_0 (0x0000) /* Timer A input divider: 0 - /1 */ +#define ID_1 (0x0040) /* Timer A input divider: 1 - /2 */ +#define ID_2 (0x0080) /* Timer A input divider: 2 - /4 */ +#define ID_3 (0x00C0) /* Timer A input divider: 3 - /8 */ +#define TASSEL_0 (0x0000) /* Timer A clock source select: 0 - TACLK */ +#define TASSEL_1 (0x0100) /* Timer A clock source select: 1 - ACLK */ +#define TASSEL_2 (0x0200) /* Timer A clock source select: 2 - SMCLK */ +#define TASSEL_3 (0x0300) /* Timer A clock source select: 3 - INCLK */ +#define MC__STOP (0x0000) /* Timer A mode control: 0 - Stop */ +#define MC__UP (0x0010) /* Timer A mode control: 1 - Up to CCR0 */ +#define MC__CONTINUOUS (0x0020) /* Timer A mode control: 2 - Continuous up */ +#define MC__CONTINOUS (0x0020) /* Legacy define */ +#define MC__UPDOWN (0x0030) /* Timer A mode control: 3 - Up/Down */ +#define ID__1 (0x0000) /* Timer A input divider: 0 - /1 */ +#define ID__2 (0x0040) /* Timer A input divider: 1 - /2 */ +#define ID__4 (0x0080) /* Timer A input divider: 2 - /4 */ +#define ID__8 (0x00C0) /* Timer A input divider: 3 - /8 */ +#define TASSEL__TACLK (0x0000) /* Timer A clock source select: 0 - TACLK */ +#define TASSEL__ACLK (0x0100) /* Timer A clock source select: 1 - ACLK */ +#define TASSEL__SMCLK (0x0200) /* Timer A clock source select: 2 - SMCLK */ +#define TASSEL__INCLK (0x0300) /* Timer A clock source select: 3 - INCLK */ + +/* TAxCCTLx Control Bits */ +#define CM1 (0x8000) /* Capture mode 1 */ +#define CM0 (0x4000) /* Capture mode 0 */ +#define CCIS1 (0x2000) /* Capture input select 1 */ +#define CCIS0 (0x1000) /* Capture input select 0 */ +#define SCS (0x0800) /* Capture sychronize */ +#define SCCI (0x0400) /* Latched capture signal (read) */ +#define CAP (0x0100) /* Capture mode: 1 /Compare mode : 0 */ +#define OUTMOD2 (0x0080) /* Output mode 2 */ +#define OUTMOD1 (0x0040) /* Output mode 1 */ +#define OUTMOD0 (0x0020) /* Output mode 0 */ +#define CCIE (0x0010) /* Capture/compare interrupt enable */ +#define CCI (0x0008) /* Capture input signal (read) */ +#define OUT (0x0004) /* PWM Output signal if output mode 0 */ +#define COV (0x0002) /* Capture/compare overflow flag */ +#define CCIFG (0x0001) /* Capture/compare interrupt flag */ + +#define OUTMOD_0 (0x0000) /* PWM output mode: 0 - output only */ +#define OUTMOD_1 (0x0020) /* PWM output mode: 1 - set */ +#define OUTMOD_2 (0x0040) /* PWM output mode: 2 - PWM toggle/reset */ +#define OUTMOD_3 (0x0060) /* PWM output mode: 3 - PWM set/reset */ +#define OUTMOD_4 (0x0080) /* PWM output mode: 4 - toggle */ +#define OUTMOD_5 (0x00A0) /* PWM output mode: 5 - Reset */ +#define OUTMOD_6 (0x00C0) /* PWM output mode: 6 - PWM toggle/set */ +#define OUTMOD_7 (0x00E0) /* PWM output mode: 7 - PWM reset/set */ +#define CCIS_0 (0x0000) /* Capture input select: 0 - CCIxA */ +#define CCIS_1 (0x1000) /* Capture input select: 1 - CCIxB */ +#define CCIS_2 (0x2000) /* Capture input select: 2 - GND */ +#define CCIS_3 (0x3000) /* Capture input select: 3 - Vcc */ +#define CM_0 (0x0000) /* Capture mode: 0 - disabled */ +#define CM_1 (0x4000) /* Capture mode: 1 - pos. edge */ +#define CM_2 (0x8000) /* Capture mode: 1 - neg. edge */ +#define CM_3 (0xC000) /* Capture mode: 1 - both edges */ + + +/* TAxEX0 Control Bits */ +#define TAIDEX0 (0x0001) /* Timer A Input divider expansion Bit: 0 */ +#define TAIDEX1 (0x0002) /* Timer A Input divider expansion Bit: 1 */ +#define TAIDEX2 (0x0004) /* Timer A Input divider expansion Bit: 2 */ + +#define TAIDEX_0 (0x0000) /* Timer A Input divider expansion : /1 */ +#define TAIDEX_1 (0x0001) /* Timer A Input divider expansion : /2 */ +#define TAIDEX_2 (0x0002) /* Timer A Input divider expansion : /3 */ +#define TAIDEX_3 (0x0003) /* Timer A Input divider expansion : /4 */ +#define TAIDEX_4 (0x0004) /* Timer A Input divider expansion : /5 */ +#define TAIDEX_5 (0x0005) /* Timer A Input divider expansion : /6 */ +#define TAIDEX_6 (0x0006) /* Timer A Input divider expansion : /7 */ +#define TAIDEX_7 (0x0007) /* Timer A Input divider expansion : /8 */ + +/* T0A3IV Definitions */ +#define TA0IV_NONE (0x0000) /* No Interrupt pending */ +#define TA0IV_TACCR1 (0x0002) /* TA0CCR1_CCIFG */ +#define TA0IV_TACCR2 (0x0004) /* TA0CCR2_CCIFG */ +#define TA0IV_3 (0x0006) /* Reserved */ +#define TA0IV_4 (0x0008) /* Reserved */ +#define TA0IV_5 (0x000A) /* Reserved */ +#define TA0IV_6 (0x000C) /* Reserved */ +#define TA0IV_TAIFG (0x000E) /* TA0IFG */ + +/* Legacy Defines */ +#define TA0IV_TA0CCR1 (0x0002) /* TA0CCR1_CCIFG */ +#define TA0IV_TA0CCR2 (0x0004) /* TA0CCR2_CCIFG */ +#define TA0IV_TA0IFG (0x000E) /* TA0IFG */ + +/************************************************************ +* Timer1_A3 +************************************************************/ + +#define TA1CTL 0x0380 /* Timer1_A3 Control */ +#define TA1CCTL0 0x0382 /* Timer1_A3 Capture/Compare Control 0 */ +#define TA1CCTL1 0x0384 /* Timer1_A3 Capture/Compare Control 1 */ +#define TA1CCTL2 0x0386 /* Timer1_A3 Capture/Compare Control 2 */ +#define TA1R 0x0390 /* Timer1_A3 */ +#define TA1CCR0 0x0392 /* Timer1_A3 Capture/Compare 0 */ +#define TA1CCR1 0x0394 /* Timer1_A3 Capture/Compare 1 */ +#define TA1CCR2 0x0396 /* Timer1_A3 Capture/Compare 2 */ +#define TA1IV 0x03AE /* Timer1_A3 Interrupt Vector Word */ +#define TA1EX0 0x03A0 /* Timer1_A3 Expansion Register 0 */ + +/* Bits are already defined within the Timer0_Ax */ + +/* TA1IV Definitions */ +#define TA1IV_NONE (0x0000) /* No Interrupt pending */ +#define TA1IV_TACCR1 (0x0002) /* TA1CCR1_CCIFG */ +#define TA1IV_TACCR2 (0x0004) /* TA1CCR2_CCIFG */ +#define TA1IV_3 (0x0006) /* Reserved */ +#define TA1IV_4 (0x0008) /* Reserved */ +#define TA1IV_5 (0x000A) /* Reserved */ +#define TA1IV_6 (0x000C) /* Reserved */ +#define TA1IV_TAIFG (0x000E) /* TA1IFG */ + +/* Legacy Defines */ +#define TA1IV_TA1CCR1 (0x0002) /* TA1CCR1_CCIFG */ +#define TA1IV_TA1CCR2 (0x0004) /* TA1CCR2_CCIFG */ +#define TA1IV_TA1IFG (0x000E) /* TA1IFG */ + +/************************************************************ +* Timer2_A2 +************************************************************/ + +#define TA2CTL 0x0400 /* Timer2_A2 Control */ +#define TA2CCTL0 0x0402 /* Timer2_A2 Capture/Compare Control 0 */ +#define TA2CCTL1 0x0404 /* Timer2_A2 Capture/Compare Control 1 */ +#define TA2R 0x0410 /* Timer2_A2 */ +#define TA2CCR0 0x0412 /* Timer2_A2 Capture/Compare 0 */ +#define TA2CCR1 0x0414 /* Timer2_A2 Capture/Compare 1 */ +#define TA2IV 0x042E /* Timer2_A2 Interrupt Vector Word */ +#define TA2EX0 0x0420 /* Timer2_A2 Expansion Register 0 */ + +/* Bits are already defined within the Timer0_Ax */ + +/* TA2IV Definitions */ +#define TA2IV_NONE (0x0000) /* No Interrupt pending */ +#define TA2IV_TACCR1 (0x0002) /* TA2CCR1_CCIFG */ +#define TA2IV_3 (0x0006) /* Reserved */ +#define TA2IV_4 (0x0008) /* Reserved */ +#define TA2IV_5 (0x000A) /* Reserved */ +#define TA2IV_6 (0x000C) /* Reserved */ +#define TA2IV_TAIFG (0x000E) /* TA2IFG */ + +/* Legacy Defines */ +#define TA2IV_TA2CCR1 (0x0002) /* TA2CCR1_CCIFG */ +#define TA2IV_TA2IFG (0x000E) /* TA2IFG */ + +/************************************************************ +* Timer3_A2 +************************************************************/ + +#define TA3CTL 0x0440 /* Timer3_A2 Control */ +#define TA3CCTL0 0x0442 /* Timer3_A2 Capture/Compare Control 0 */ +#define TA3CCTL1 0x0444 /* Timer3_A2 Capture/Compare Control 1 */ +#define TA3R 0x0450 /* Timer3_A2 */ +#define TA3CCR0 0x0452 /* Timer3_A2 Capture/Compare 0 */ +#define TA3CCR1 0x0454 /* Timer3_A2 Capture/Compare 1 */ +#define TA3IV 0x046E /* Timer3_A2 Interrupt Vector Word */ +#define TA3EX0 0x0460 /* Timer3_A2 Expansion Register 0 */ + +/* Bits are already defined within the Timer0_Ax */ + +/* TA3IV Definitions */ +#define TA3IV_NONE (0x0000) /* No Interrupt pending */ +#define TA3IV_TACCR1 (0x0002) /* TA3CCR1_CCIFG */ +#define TA3IV_3 (0x0006) /* Reserved */ +#define TA3IV_4 (0x0008) /* Reserved */ +#define TA3IV_5 (0x000A) /* Reserved */ +#define TA3IV_6 (0x000C) /* Reserved */ +#define TA3IV_TAIFG (0x000E) /* TA3IFG */ + +/* Legacy Defines */ +#define TA3IV_TA3CCR1 (0x0002) /* TA3CCR1_CCIFG */ +#define TA3IV_TA3IFG (0x000E) /* TA3IFG */ + +/************************************************************ +* Timer0_B7 +************************************************************/ + +#define TB0CTL 0x03C0 /* Timer0_B7 Control */ +#define TB0CCTL0 0x03C2 /* Timer0_B7 Capture/Compare Control 0 */ +#define TB0CCTL1 0x03C4 /* Timer0_B7 Capture/Compare Control 1 */ +#define TB0CCTL2 0x03C6 /* Timer0_B7 Capture/Compare Control 2 */ +#define TB0CCTL3 0x03C8 /* Timer0_B7 Capture/Compare Control 3 */ +#define TB0CCTL4 0x03CA /* Timer0_B7 Capture/Compare Control 4 */ +#define TB0CCTL5 0x03CC /* Timer0_B7 Capture/Compare Control 5 */ +#define TB0CCTL6 0x03CE /* Timer0_B7 Capture/Compare Control 6 */ +#define TB0R 0x03D0 /* Timer0_B7 */ +#define TB0CCR0 0x03D2 /* Timer0_B7 Capture/Compare 0 */ +#define TB0CCR1 0x03D4 /* Timer0_B7 Capture/Compare 1 */ +#define TB0CCR2 0x03D6 /* Timer0_B7 Capture/Compare 2 */ +#define TB0CCR3 0x03D8 /* Timer0_B7 Capture/Compare 3 */ +#define TB0CCR4 0x03DA /* Timer0_B7 Capture/Compare 4 */ +#define TB0CCR5 0x03DC /* Timer0_B7 Capture/Compare 5 */ +#define TB0CCR6 0x03DE /* Timer0_B7 Capture/Compare 6 */ +#define TB0EX0 0x03E0 /* Timer0_B7 Expansion Register 0 */ +#define TB0IV 0x03EE /* Timer0_B7 Interrupt Vector Word */ + +/* Legacy Type Definitions for TimerB */ +#define TBCTL TB0CTL /* Timer0_B7 Control */ +#define TBCCTL0 TB0CCTL0 /* Timer0_B7 Capture/Compare Control 0 */ +#define TBCCTL1 TB0CCTL1 /* Timer0_B7 Capture/Compare Control 1 */ +#define TBCCTL2 TB0CCTL2 /* Timer0_B7 Capture/Compare Control 2 */ +#define TBCCTL3 TB0CCTL3 /* Timer0_B7 Capture/Compare Control 3 */ +#define TBCCTL4 TB0CCTL4 /* Timer0_B7 Capture/Compare Control 4 */ +#define TBCCTL5 TB0CCTL5 /* Timer0_B7 Capture/Compare Control 5 */ +#define TBCCTL6 TB0CCTL6 /* Timer0_B7 Capture/Compare Control 6 */ +#define TBR TB0R /* Timer0_B7 */ +#define TBCCR0 TB0CCR0 /* Timer0_B7 Capture/Compare 0 */ +#define TBCCR1 TB0CCR1 /* Timer0_B7 Capture/Compare 1 */ +#define TBCCR2 TB0CCR2 /* Timer0_B7 Capture/Compare 2 */ +#define TBCCR3 TB0CCR3 /* Timer0_B7 Capture/Compare 3 */ +#define TBCCR4 TB0CCR4 /* Timer0_B7 Capture/Compare 4 */ +#define TBCCR5 TB0CCR5 /* Timer0_B7 Capture/Compare 5 */ +#define TBCCR6 TB0CCR6 /* Timer0_B7 Capture/Compare 6 */ +#define TBEX0 TB0EX0 /* Timer0_B7 Expansion Register 0 */ +#define TBIV TB0IV /* Timer0_B7 Interrupt Vector Word */ +#define TIMERB1_VECTOR TIMER0_B1_VECTOR /* Timer0_B7 CC1-6, TB */ +#define TIMERB0_VECTOR TIMER0_B0_VECTOR /* Timer0_B7 CC0 */ + + +/* TBxCTL Control Bits */ +#define TBCLGRP1 (0x4000) /* Timer0_B7 Compare latch load group 1 */ +#define TBCLGRP0 (0x2000) /* Timer0_B7 Compare latch load group 0 */ +#define CNTL1 (0x1000) /* Counter lenght 1 */ +#define CNTL0 (0x0800) /* Counter lenght 0 */ +#define TBSSEL1 (0x0200) /* Clock source 1 */ +#define TBSSEL0 (0x0100) /* Clock source 0 */ +#define TBCLR (0x0004) /* Timer0_B7 counter clear */ +#define TBIE (0x0002) /* Timer0_B7 interrupt enable */ +#define TBIFG (0x0001) /* Timer0_B7 interrupt flag */ + +#define SHR1 (0x4000) /* Timer0_B7 Compare latch load group 1 */ +#define SHR0 (0x2000) /* Timer0_B7 Compare latch load group 0 */ + +#define TBSSEL_0 (0x0000) /* Clock Source: TBCLK */ +#define TBSSEL_1 (0x0100) /* Clock Source: ACLK */ +#define TBSSEL_2 (0x0200) /* Clock Source: SMCLK */ +#define TBSSEL_3 (0x0300) /* Clock Source: INCLK */ +#define CNTL_0 (0x0000) /* Counter lenght: 16 bit */ +#define CNTL_1 (0x0800) /* Counter lenght: 12 bit */ +#define CNTL_2 (0x1000) /* Counter lenght: 10 bit */ +#define CNTL_3 (0x1800) /* Counter lenght: 8 bit */ +#define SHR_0 (0x0000) /* Timer0_B7 Group: 0 - individually */ +#define SHR_1 (0x2000) /* Timer0_B7 Group: 1 - 3 groups (1-2, 3-4, 5-6) */ +#define SHR_2 (0x4000) /* Timer0_B7 Group: 2 - 2 groups (1-3, 4-6)*/ +#define SHR_3 (0x6000) /* Timer0_B7 Group: 3 - 1 group (all) */ +#define TBCLGRP_0 (0x0000) /* Timer0_B7 Group: 0 - individually */ +#define TBCLGRP_1 (0x2000) /* Timer0_B7 Group: 1 - 3 groups (1-2, 3-4, 5-6) */ +#define TBCLGRP_2 (0x4000) /* Timer0_B7 Group: 2 - 2 groups (1-3, 4-6)*/ +#define TBCLGRP_3 (0x6000) /* Timer0_B7 Group: 3 - 1 group (all) */ +#define TBSSEL__TBCLK (0x0000) /* Timer0_B7 clock source select: 0 - TBCLK */ +#define TBSSEL__TACLK (0x0000) /* Timer0_B7 clock source select: 0 - TBCLK (legacy) */ +#define TBSSEL__ACLK (0x0100) /* Timer0_B7 clock source select: 1 - ACLK */ +#define TBSSEL__SMCLK (0x0200) /* Timer0_B7 clock source select: 2 - SMCLK */ +#define TBSSEL__INCLK (0x0300) /* Timer0_B7 clock source select: 3 - INCLK */ +#define CNTL__16 (0x0000) /* Counter lenght: 16 bit */ +#define CNTL__12 (0x0800) /* Counter lenght: 12 bit */ +#define CNTL__10 (0x1000) /* Counter lenght: 10 bit */ +#define CNTL__8 (0x1800) /* Counter lenght: 8 bit */ + +/* Additional Timer B Control Register bits are defined in Timer A */ +/* TBxCCTLx Control Bits */ +#define CLLD1 (0x0400) /* Compare latch load source 1 */ +#define CLLD0 (0x0200) /* Compare latch load source 0 */ + +#define SLSHR1 (0x0400) /* Compare latch load source 1 */ +#define SLSHR0 (0x0200) /* Compare latch load source 0 */ + +#define SLSHR_0 (0x0000) /* Compare latch load sourec : 0 - immediate */ +#define SLSHR_1 (0x0200) /* Compare latch load sourec : 1 - TBR counts to 0 */ +#define SLSHR_2 (0x0400) /* Compare latch load sourec : 2 - up/down */ +#define SLSHR_3 (0x0600) /* Compare latch load sourec : 3 - TBR counts to TBCTL0 */ + +#define CLLD_0 (0x0000) /* Compare latch load sourec : 0 - immediate */ +#define CLLD_1 (0x0200) /* Compare latch load sourec : 1 - TBR counts to 0 */ +#define CLLD_2 (0x0400) /* Compare latch load sourec : 2 - up/down */ +#define CLLD_3 (0x0600) /* Compare latch load sourec : 3 - TBR counts to TBCTL0 */ + +/* TBxEX0 Control Bits */ +#define TBIDEX0 (0x0001) /* Timer0_B7 Input divider expansion Bit: 0 */ +#define TBIDEX1 (0x0002) /* Timer0_B7 Input divider expansion Bit: 1 */ +#define TBIDEX2 (0x0004) /* Timer0_B7 Input divider expansion Bit: 2 */ + +#define TBIDEX_0 (0x0000) /* Timer0_B7 Input divider expansion : /1 */ +#define TBIDEX_1 (0x0001) /* Timer0_B7 Input divider expansion : /2 */ +#define TBIDEX_2 (0x0002) /* Timer0_B7 Input divider expansion : /3 */ +#define TBIDEX_3 (0x0003) /* Timer0_B7 Input divider expansion : /4 */ +#define TBIDEX_4 (0x0004) /* Timer0_B7 Input divider expansion : /5 */ +#define TBIDEX_5 (0x0005) /* Timer0_B7 Input divider expansion : /6 */ +#define TBIDEX_6 (0x0006) /* Timer0_B7 Input divider expansion : /7 */ +#define TBIDEX_7 (0x0007) /* Timer0_B7 Input divider expansion : /8 */ +#define TBIDEX__1 (0x0000) /* Timer0_B7 Input divider expansion : /1 */ +#define TBIDEX__2 (0x0001) /* Timer0_B7 Input divider expansion : /2 */ +#define TBIDEX__3 (0x0002) /* Timer0_B7 Input divider expansion : /3 */ +#define TBIDEX__4 (0x0003) /* Timer0_B7 Input divider expansion : /4 */ +#define TBIDEX__5 (0x0004) /* Timer0_B7 Input divider expansion : /5 */ +#define TBIDEX__6 (0x0005) /* Timer0_B7 Input divider expansion : /6 */ +#define TBIDEX__7 (0x0006) /* Timer0_B7 Input divider expansion : /7 */ +#define TBIDEX__8 (0x0007) /* Timer0_B7 Input divider expansion : /8 */ + +/* TB0IV Definitions */ +#define TB0IV_NONE (0x0000) /* No Interrupt pending */ +#define TB0IV_TBCCR1 (0x0002) /* TB0CCR1_CCIFG */ +#define TB0IV_TBCCR2 (0x0004) /* TB0CCR2_CCIFG */ +#define TB0IV_TBCCR3 (0x0006) /* TB0CCR3_CCIFG */ +#define TB0IV_TBCCR4 (0x0008) /* TB0CCR4_CCIFG */ +#define TB0IV_TBCCR5 (0x000A) /* TB0CCR5_CCIFG */ +#define TB0IV_TBCCR6 (0x000C) /* TB0CCR6_CCIFG */ +#define TB0IV_TBIFG (0x000E) /* TB0IFG */ + +/* Legacy Defines */ +#define TB0IV_TB0CCR1 (0x0002) /* TB0CCR1_CCIFG */ +#define TB0IV_TB0CCR2 (0x0004) /* TB0CCR2_CCIFG */ +#define TB0IV_TB0CCR3 (0x0006) /* TB0CCR3_CCIFG */ +#define TB0IV_TB0CCR4 (0x0008) /* TB0CCR4_CCIFG */ +#define TB0IV_TB0CCR5 (0x000A) /* TB0CCR5_CCIFG */ +#define TB0IV_TB0CCR6 (0x000C) /* TB0CCR6_CCIFG */ +#define TB0IV_TB0IFG (0x000E) /* TB0IFG */ + + +/************************************************************ +* USCI A0 +************************************************************/ + +#define UCA0CTLW0 0x05C0 /* USCI A0 Control Word Register 0 */ +#define UCA0CTL1 UCA0CTLW0_L /* USCI A0 Control Register 1 */ +#define UCA0CTL0 UCA0CTLW0_H /* USCI A0 Control Register 0 */ +#define UCA0CTLW1 0x05C2 /* USCI A0 Control Word Register 1 */ +#define UCA0BRW 0x05C6 /* USCI A0 Baud Word Rate 0 */ +#define UCA0BR0 UCA0BRW_L /* USCI A0 Baud Rate 0 */ +#define UCA0BR1 UCA0BRW_H /* USCI A0 Baud Rate 1 */ +#define UCA0MCTLW 0x05C8 /* USCI A0 Modulation Control */ +#define UCA0STATW 0x05CA /* USCI A0 Status Register */ +#define UCA0RXBUF 0x05CC /* USCI A0 Receive Buffer */ +#define UCA0TXBUF 0x05CE /* USCI A0 Transmit Buffer */ +#define UCA0ABCTL 0x05D0 /* USCI A0 LIN Control */ +#define UCA0IRCTL 0x05D2 /* USCI A0 IrDA Transmit Control */ +#define UCA0IRTCTL UCA0IRCTL_L /* USCI A0 IrDA Transmit Control */ +#define UCA0IRRCTL UCA0IRCTL_H /* USCI A0 IrDA Receive Control */ +#define UCA0IE 0x05DA /* USCI A0 Interrupt Enable Register */ +#define UCA0IFG 0x05DC /* USCI A0 Interrupt Flags Register */ +#define UCA0IV 0x05DE /* USCI A0 Interrupt Vector Register */ + + +/************************************************************ +* USCI A1 +************************************************************/ + +#define UCA1CTLW0 0x05E0 /* USCI A1 Control Word Register 0 */ +#define UCA1CTL1 UCA1CTLW0_L /* USCI A1 Control Register 1 */ +#define UCA1CTL0 UCA1CTLW0_H /* USCI A1 Control Register 0 */ +#define UCA1CTLW1 0x05E2 /* USCI A1 Control Word Register 1 */ +#define UCA1BRW 0x05E6 /* USCI A1 Baud Word Rate 0 */ +#define UCA1BR0 UCA1BRW_L /* USCI A1 Baud Rate 0 */ +#define UCA1BR1 UCA1BRW_H /* USCI A1 Baud Rate 1 */ +#define UCA1MCTLW 0x05E8 /* USCI A1 Modulation Control */ +#define UCA1STATW 0x05EA /* USCI A1 Status Register */ +#define UCA1RXBUF 0x05EC /* USCI A1 Receive Buffer */ +#define UCA1TXBUF 0x05EE /* USCI A1 Transmit Buffer */ +#define UCA1ABCTL 0x05F0 /* USCI A1 LIN Control */ +#define UCA1IRCTL 0x05F2 /* USCI A1 IrDA Transmit Control */ +#define UCA1IRTCTL UCA1IRCTL_L /* USCI A1 IrDA Transmit Control */ +#define UCA1IRRCTL UCA1IRCTL_H /* USCI A1 IrDA Receive Control */ +#define UCA1IE 0x05FA /* USCI A1 Interrupt Enable Register */ +#define UCA1IFG 0x05FC /* USCI A1 Interrupt Flags Register */ +#define UCA1IV 0x05FE /* USCI A1 Interrupt Vector Register */ + + +/************************************************************ +* USCI B0 +************************************************************/ + + +#define UCB0CTLW0 0x0640 /* USCI B0 Control Word Register 0 */ +#define UCB0CTL1 UCB0CTLW0_L /* USCI B0 Control Register 1 */ +#define UCB0CTL0 UCB0CTLW0_H /* USCI B0 Control Register 0 */ +#define UCB0CTLW1 0x0642 /* USCI B0 Control Word Register 1 */ +#define UCB0BRW 0x0646 /* USCI B0 Baud Word Rate 0 */ +#define UCB0BR0 UCB0BRW_L /* USCI B0 Baud Rate 0 */ +#define UCB0BR1 UCB0BRW_H /* USCI B0 Baud Rate 1 */ +#define UCB0STATW 0x0648 /* USCI B0 Status Word Register */ +#define UCB0STAT UCB0STATW_L /* USCI B0 Status Register */ +#define UCB0BCNT UCB0STATW_H /* USCI B0 Byte Counter Register */ +#define UCB0TBCNT 0x064A /* USCI B0 Byte Counter Threshold Register */ +#define UCB0RXBUF 0x064C /* USCI B0 Receive Buffer */ +#define UCB0TXBUF 0x064E /* USCI B0 Transmit Buffer */ +#define UCB0I2COA0 0x0654 /* USCI B0 I2C Own Address 0 */ +#define UCB0I2COA1 0x0656 /* USCI B0 I2C Own Address 1 */ +#define UCB0I2COA2 0x0658 /* USCI B0 I2C Own Address 2 */ +#define UCB0I2COA3 0x065A /* USCI B0 I2C Own Address 3 */ +#define UCB0ADDRX 0x065C /* USCI B0 Received Address Register */ +#define UCB0ADDMASK 0x065E /* USCI B0 Address Mask Register */ +#define UCB0I2CSA 0x0660 /* USCI B0 I2C Slave Address */ +#define UCB0IE 0x066A /* USCI B0 Interrupt Enable Register */ +#define UCB0IFG 0x066C /* USCI B0 Interrupt Flags Register */ +#define UCB0IV 0x066E /* USCI B0 Interrupt Vector Register */ + + +// UCAxCTLW0 UART-Mode Control Bits +#define UCPEN (0x8000) /* Async. Mode: Parity enable */ +#define UCPAR (0x4000) /* Async. Mode: Parity 0:odd / 1:even */ +#define UCMSB (0x2000) /* Async. Mode: MSB first 0:LSB / 1:MSB */ +#define UC7BIT (0x1000) /* Async. Mode: Data Bits 0:8-bits / 1:7-bits */ +#define UCSPB (0x0800) /* Async. Mode: Stop Bits 0:one / 1: two */ +#define UCMODE1 (0x0400) /* Async. Mode: USCI Mode 1 */ +#define UCMODE0 (0x0200) /* Async. Mode: USCI Mode 0 */ +#define UCSYNC (0x0100) /* Sync-Mode 0:UART-Mode / 1:SPI-Mode */ +#define UCSSEL1 (0x0080) /* USCI 0 Clock Source Select 1 */ +#define UCSSEL0 (0x0040) /* USCI 0 Clock Source Select 0 */ +#define UCRXEIE (0x0020) /* RX Error interrupt enable */ +#define UCBRKIE (0x0010) /* Break interrupt enable */ +#define UCDORM (0x0008) /* Dormant (Sleep) Mode */ +#define UCTXADDR (0x0004) /* Send next Data as Address */ +#define UCTXBRK (0x0002) /* Send next Data as Break */ +#define UCSWRST (0x0001) /* USCI Software Reset */ + +// UCAxCTLW0 UART-Mode Control Bits +#define UCSSEL1_L (0x0080) /* USCI 0 Clock Source Select 1 */ +#define UCSSEL0_L (0x0040) /* USCI 0 Clock Source Select 0 */ +#define UCRXEIE_L (0x0020) /* RX Error interrupt enable */ +#define UCBRKIE_L (0x0010) /* Break interrupt enable */ +#define UCDORM_L (0x0008) /* Dormant (Sleep) Mode */ +#define UCTXADDR_L (0x0004) /* Send next Data as Address */ +#define UCTXBRK_L (0x0002) /* Send next Data as Break */ +#define UCSWRST_L (0x0001) /* USCI Software Reset */ + +// UCAxCTLW0 UART-Mode Control Bits +#define UCPEN_H (0x0080) /* Async. Mode: Parity enable */ +#define UCPAR_H (0x0040) /* Async. Mode: Parity 0:odd / 1:even */ +#define UCMSB_H (0x0020) /* Async. Mode: MSB first 0:LSB / 1:MSB */ +#define UC7BIT_H (0x0010) /* Async. Mode: Data Bits 0:8-bits / 1:7-bits */ +#define UCSPB_H (0x0008) /* Async. Mode: Stop Bits 0:one / 1: two */ +#define UCMODE1_H (0x0004) /* Async. Mode: USCI Mode 1 */ +#define UCMODE0_H (0x0002) /* Async. Mode: USCI Mode 0 */ +#define UCSYNC_H (0x0001) /* Sync-Mode 0:UART-Mode / 1:SPI-Mode */ + +// UCxxCTLW0 SPI-Mode Control Bits +#define UCCKPH (0x8000) /* Sync. Mode: Clock Phase */ +#define UCCKPL (0x4000) /* Sync. Mode: Clock Polarity */ +#define UCMST (0x0800) /* Sync. Mode: Master Select */ +//#define res (0x0020) /* reserved */ +//#define res (0x0010) /* reserved */ +//#define res (0x0008) /* reserved */ +//#define res (0x0004) /* reserved */ +#define UCSTEM (0x0002) /* USCI STE Mode */ + +// UCBxCTLW0 I2C-Mode Control Bits +#define UCA10 (0x8000) /* 10-bit Address Mode */ +#define UCSLA10 (0x4000) /* 10-bit Slave Address Mode */ +#define UCMM (0x2000) /* Multi-Master Environment */ +//#define res (0x1000) /* reserved */ +//#define res (0x0100) /* reserved */ +#define UCTXACK (0x0020) /* Transmit ACK */ +#define UCTR (0x0010) /* Transmit/Receive Select/Flag */ +#define UCTXNACK (0x0008) /* Transmit NACK */ +#define UCTXSTP (0x0004) /* Transmit STOP */ +#define UCTXSTT (0x0002) /* Transmit START */ + +// UCBxCTLW0 I2C-Mode Control Bits +//#define res (0x1000) /* reserved */ +//#define res (0x0100) /* reserved */ +#define UCTXACK_L (0x0020) /* Transmit ACK */ +#define UCTR_L (0x0010) /* Transmit/Receive Select/Flag */ +#define UCTXNACK_L (0x0008) /* Transmit NACK */ +#define UCTXSTP_L (0x0004) /* Transmit STOP */ +#define UCTXSTT_L (0x0002) /* Transmit START */ + +// UCBxCTLW0 I2C-Mode Control Bits +#define UCA10_H (0x0080) /* 10-bit Address Mode */ +#define UCSLA10_H (0x0040) /* 10-bit Slave Address Mode */ +#define UCMM_H (0x0020) /* Multi-Master Environment */ +//#define res (0x1000) /* reserved */ +//#define res (0x0100) /* reserved */ + +#define UCMODE_0 (0x0000) /* Sync. Mode: USCI Mode: 0 */ +#define UCMODE_1 (0x0200) /* Sync. Mode: USCI Mode: 1 */ +#define UCMODE_2 (0x0400) /* Sync. Mode: USCI Mode: 2 */ +#define UCMODE_3 (0x0600) /* Sync. Mode: USCI Mode: 3 */ + +#define UCSSEL_0 (0x0000) /* USCI 0 Clock Source: 0 */ +#define UCSSEL_1 (0x0040) /* USCI 0 Clock Source: 1 */ +#define UCSSEL_2 (0x0080) /* USCI 0 Clock Source: 2 */ +#define UCSSEL_3 (0x00C0) /* USCI 0 Clock Source: 3 */ +#define UCSSEL__UCLK (0x0000) /* USCI 0 Clock Source: UCLK */ +#define UCSSEL__ACLK (0x0040) /* USCI 0 Clock Source: ACLK */ +#define UCSSEL__SMCLK (0x0080) /* USCI 0 Clock Source: SMCLK */ + + +// UCAxCTLW1 UART-Mode Control Bits +#define UCGLIT1 (0x0002) /* USCI Deglitch Time Bit 1 */ +#define UCGLIT0 (0x0001) /* USCI Deglitch Time Bit 0 */ + +// UCAxCTLW1 UART-Mode Control Bits +#define UCGLIT1_L (0x0002) /* USCI Deglitch Time Bit 1 */ +#define UCGLIT0_L (0x0001) /* USCI Deglitch Time Bit 0 */ + + +// UCBxCTLW1 I2C-Mode Control Bits +#define UCETXINT (0x0100) /* USCI Early UCTXIFG0 */ +#define UCCLTO1 (0x0080) /* USCI Clock low timeout Bit: 1 */ +#define UCCLTO0 (0x0040) /* USCI Clock low timeout Bit: 0 */ +#define UCSTPNACK (0x0020) /* USCI Acknowledge Stop last byte */ +#define UCSWACK (0x0010) /* USCI Software controlled ACK */ +#define UCASTP1 (0x0008) /* USCI Automatic Stop condition generation Bit: 1 */ +#define UCASTP0 (0x0004) /* USCI Automatic Stop condition generation Bit: 0 */ + +// UCBxCTLW1 I2C-Mode Control Bits +#define UCCLTO1_L (0x0080) /* USCI Clock low timeout Bit: 1 */ +#define UCCLTO0_L (0x0040) /* USCI Clock low timeout Bit: 0 */ +#define UCSTPNACK_L (0x0020) /* USCI Acknowledge Stop last byte */ +#define UCSWACK_L (0x0010) /* USCI Software controlled ACK */ +#define UCASTP1_L (0x0008) /* USCI Automatic Stop condition generation Bit: 1 */ +#define UCASTP0_L (0x0004) /* USCI Automatic Stop condition generation Bit: 0 */ + +// UCBxCTLW1 I2C-Mode Control Bits +#define UCETXINT_H (0x0001) /* USCI Early UCTXIFG0 */ + +#define UCGLIT_0 (0x0000) /* USCI Deglitch time: 0 */ +#define UCGLIT_1 (0x0001) /* USCI Deglitch time: 1 */ +#define UCGLIT_2 (0x0002) /* USCI Deglitch time: 2 */ +#define UCGLIT_3 (0x0003) /* USCI Deglitch time: 3 */ + +#define UCASTP_0 (0x0000) /* USCI Automatic Stop condition generation: 0 */ +#define UCASTP_1 (0x0004) /* USCI Automatic Stop condition generation: 1 */ +#define UCASTP_2 (0x0008) /* USCI Automatic Stop condition generation: 2 */ +#define UCASTP_3 (0x000C) /* USCI Automatic Stop condition generation: 3 */ + +#define UCCLTO_0 (0x0000) /* USCI Clock low timeout: 0 */ +#define UCCLTO_1 (0x0040) /* USCI Clock low timeout: 1 */ +#define UCCLTO_2 (0x0080) /* USCI Clock low timeout: 2 */ +#define UCCLTO_3 (0x00C0) /* USCI Clock low timeout: 3 */ + + +/* UCAxMCTLW Control Bits */ +#define UCBRS7 (0x8000) /* USCI Second Stage Modulation Select 7 */ +#define UCBRS6 (0x4000) /* USCI Second Stage Modulation Select 6 */ +#define UCBRS5 (0x2000) /* USCI Second Stage Modulation Select 5 */ +#define UCBRS4 (0x1000) /* USCI Second Stage Modulation Select 4 */ +#define UCBRS3 (0x0800) /* USCI Second Stage Modulation Select 3 */ +#define UCBRS2 (0x0400) /* USCI Second Stage Modulation Select 2 */ +#define UCBRS1 (0x0200) /* USCI Second Stage Modulation Select 1 */ +#define UCBRS0 (0x0100) /* USCI Second Stage Modulation Select 0 */ +#define UCBRF3 (0x0080) /* USCI First Stage Modulation Select 3 */ +#define UCBRF2 (0x0040) /* USCI First Stage Modulation Select 2 */ +#define UCBRF1 (0x0020) /* USCI First Stage Modulation Select 1 */ +#define UCBRF0 (0x0010) /* USCI First Stage Modulation Select 0 */ +#define UCOS16 (0x0001) /* USCI 16-times Oversampling enable */ + +/* UCAxMCTLW Control Bits */ +#define UCBRF3_L (0x0080) /* USCI First Stage Modulation Select 3 */ +#define UCBRF2_L (0x0040) /* USCI First Stage Modulation Select 2 */ +#define UCBRF1_L (0x0020) /* USCI First Stage Modulation Select 1 */ +#define UCBRF0_L (0x0010) /* USCI First Stage Modulation Select 0 */ +#define UCOS16_L (0x0001) /* USCI 16-times Oversampling enable */ + +/* UCAxMCTLW Control Bits */ +#define UCBRS7_H (0x0080) /* USCI Second Stage Modulation Select 7 */ +#define UCBRS6_H (0x0040) /* USCI Second Stage Modulation Select 6 */ +#define UCBRS5_H (0x0020) /* USCI Second Stage Modulation Select 5 */ +#define UCBRS4_H (0x0010) /* USCI Second Stage Modulation Select 4 */ +#define UCBRS3_H (0x0008) /* USCI Second Stage Modulation Select 3 */ +#define UCBRS2_H (0x0004) /* USCI Second Stage Modulation Select 2 */ +#define UCBRS1_H (0x0002) /* USCI Second Stage Modulation Select 1 */ +#define UCBRS0_H (0x0001) /* USCI Second Stage Modulation Select 0 */ + +#define UCBRF_0 (0x00) /* USCI First Stage Modulation: 0 */ +#define UCBRF_1 (0x10) /* USCI First Stage Modulation: 1 */ +#define UCBRF_2 (0x20) /* USCI First Stage Modulation: 2 */ +#define UCBRF_3 (0x30) /* USCI First Stage Modulation: 3 */ +#define UCBRF_4 (0x40) /* USCI First Stage Modulation: 4 */ +#define UCBRF_5 (0x50) /* USCI First Stage Modulation: 5 */ +#define UCBRF_6 (0x60) /* USCI First Stage Modulation: 6 */ +#define UCBRF_7 (0x70) /* USCI First Stage Modulation: 7 */ +#define UCBRF_8 (0x80) /* USCI First Stage Modulation: 8 */ +#define UCBRF_9 (0x90) /* USCI First Stage Modulation: 9 */ +#define UCBRF_10 (0xA0) /* USCI First Stage Modulation: A */ +#define UCBRF_11 (0xB0) /* USCI First Stage Modulation: B */ +#define UCBRF_12 (0xC0) /* USCI First Stage Modulation: C */ +#define UCBRF_13 (0xD0) /* USCI First Stage Modulation: D */ +#define UCBRF_14 (0xE0) /* USCI First Stage Modulation: E */ +#define UCBRF_15 (0xF0) /* USCI First Stage Modulation: F */ + + +/* UCAxSTATW Control Bits */ +#define UCLISTEN (0x0080) /* USCI Listen mode */ +#define UCFE (0x0040) /* USCI Frame Error Flag */ +#define UCOE (0x0020) /* USCI Overrun Error Flag */ +#define UCPE (0x0010) /* USCI Parity Error Flag */ +#define UCBRK (0x0008) /* USCI Break received */ +#define UCRXERR (0x0004) /* USCI RX Error Flag */ +#define UCADDR (0x0002) /* USCI Address received Flag */ +#define UCBUSY (0x0001) /* USCI Busy Flag */ +#define UCIDLE (0x0002) /* USCI Idle line detected Flag */ + + +/* UCBxSTATW I2C Control Bits */ +#define UCBCNT7 (0x8000) /* USCI Byte Counter Bit 7 */ +#define UCBCNT6 (0x4000) /* USCI Byte Counter Bit 6 */ +#define UCBCNT5 (0x2000) /* USCI Byte Counter Bit 5 */ +#define UCBCNT4 (0x1000) /* USCI Byte Counter Bit 4 */ +#define UCBCNT3 (0x0800) /* USCI Byte Counter Bit 3 */ +#define UCBCNT2 (0x0400) /* USCI Byte Counter Bit 2 */ +#define UCBCNT1 (0x0200) /* USCI Byte Counter Bit 1 */ +#define UCBCNT0 (0x0100) /* USCI Byte Counter Bit 0 */ +#define UCSCLLOW (0x0040) /* SCL low */ +#define UCGC (0x0020) /* General Call address received Flag */ +#define UCBBUSY (0x0010) /* Bus Busy Flag */ + +/* UCBxTBCNT I2C Control Bits */ +#define UCTBCNT7 (0x0080) /* USCI Byte Counter Bit 7 */ +#define UCTBCNT6 (0x0040) /* USCI Byte Counter Bit 6 */ +#define UCTBCNT5 (0x0020) /* USCI Byte Counter Bit 5 */ +#define UCTBCNT4 (0x0010) /* USCI Byte Counter Bit 4 */ +#define UCTBCNT3 (0x0008) /* USCI Byte Counter Bit 3 */ +#define UCTBCNT2 (0x0004) /* USCI Byte Counter Bit 2 */ +#define UCTBCNT1 (0x0002) /* USCI Byte Counter Bit 1 */ +#define UCTBCNT0 (0x0001) /* USCI Byte Counter Bit 0 */ + +/* UCAxIRCTL Control Bits */ +#define UCIRRXFL5 (0x8000) /* IRDA Receive Filter Length 5 */ +#define UCIRRXFL4 (0x4000) /* IRDA Receive Filter Length 4 */ +#define UCIRRXFL3 (0x2000) /* IRDA Receive Filter Length 3 */ +#define UCIRRXFL2 (0x1000) /* IRDA Receive Filter Length 2 */ +#define UCIRRXFL1 (0x0800) /* IRDA Receive Filter Length 1 */ +#define UCIRRXFL0 (0x0400) /* IRDA Receive Filter Length 0 */ +#define UCIRRXPL (0x0200) /* IRDA Receive Input Polarity */ +#define UCIRRXFE (0x0100) /* IRDA Receive Filter enable */ +#define UCIRTXPL5 (0x0080) /* IRDA Transmit Pulse Length 5 */ +#define UCIRTXPL4 (0x0040) /* IRDA Transmit Pulse Length 4 */ +#define UCIRTXPL3 (0x0020) /* IRDA Transmit Pulse Length 3 */ +#define UCIRTXPL2 (0x0010) /* IRDA Transmit Pulse Length 2 */ +#define UCIRTXPL1 (0x0008) /* IRDA Transmit Pulse Length 1 */ +#define UCIRTXPL0 (0x0004) /* IRDA Transmit Pulse Length 0 */ +#define UCIRTXCLK (0x0002) /* IRDA Transmit Pulse Clock Select */ +#define UCIREN (0x0001) /* IRDA Encoder/Decoder enable */ + +/* UCAxIRCTL Control Bits */ +#define UCIRTXPL5_L (0x0080) /* IRDA Transmit Pulse Length 5 */ +#define UCIRTXPL4_L (0x0040) /* IRDA Transmit Pulse Length 4 */ +#define UCIRTXPL3_L (0x0020) /* IRDA Transmit Pulse Length 3 */ +#define UCIRTXPL2_L (0x0010) /* IRDA Transmit Pulse Length 2 */ +#define UCIRTXPL1_L (0x0008) /* IRDA Transmit Pulse Length 1 */ +#define UCIRTXPL0_L (0x0004) /* IRDA Transmit Pulse Length 0 */ +#define UCIRTXCLK_L (0x0002) /* IRDA Transmit Pulse Clock Select */ +#define UCIREN_L (0x0001) /* IRDA Encoder/Decoder enable */ + +/* UCAxIRCTL Control Bits */ +#define UCIRRXFL5_H (0x0080) /* IRDA Receive Filter Length 5 */ +#define UCIRRXFL4_H (0x0040) /* IRDA Receive Filter Length 4 */ +#define UCIRRXFL3_H (0x0020) /* IRDA Receive Filter Length 3 */ +#define UCIRRXFL2_H (0x0010) /* IRDA Receive Filter Length 2 */ +#define UCIRRXFL1_H (0x0008) /* IRDA Receive Filter Length 1 */ +#define UCIRRXFL0_H (0x0004) /* IRDA Receive Filter Length 0 */ +#define UCIRRXPL_H (0x0002) /* IRDA Receive Input Polarity */ +#define UCIRRXFE_H (0x0001) /* IRDA Receive Filter enable */ + + +/* UCAxABCTL Control Bits */ +//#define res (0x80) /* reserved */ +//#define res (0x40) /* reserved */ +#define UCDELIM1 (0x20) /* Break Sync Delimiter 1 */ +#define UCDELIM0 (0x10) /* Break Sync Delimiter 0 */ +#define UCSTOE (0x08) /* Sync-Field Timeout error */ +#define UCBTOE (0x04) /* Break Timeout error */ +//#define res (0x02) /* reserved */ +#define UCABDEN (0x01) /* Auto Baud Rate detect enable */ + +/* UCBxI2COA0 Control Bits */ +#define UCGCEN (0x8000) /* I2C General Call enable */ +#define UCOAEN (0x0400) /* I2C Own Address enable */ +#define UCOA9 (0x0200) /* I2C Own Address Bit 9 */ +#define UCOA8 (0x0100) /* I2C Own Address Bit 8 */ +#define UCOA7 (0x0080) /* I2C Own Address Bit 7 */ +#define UCOA6 (0x0040) /* I2C Own Address Bit 6 */ +#define UCOA5 (0x0020) /* I2C Own Address Bit 5 */ +#define UCOA4 (0x0010) /* I2C Own Address Bit 4 */ +#define UCOA3 (0x0008) /* I2C Own Address Bit 3 */ +#define UCOA2 (0x0004) /* I2C Own Address Bit 2 */ +#define UCOA1 (0x0002) /* I2C Own Address Bit 1 */ +#define UCOA0 (0x0001) /* I2C Own Address Bit 0 */ + +/* UCBxI2COA0 Control Bits */ +#define UCOA7_L (0x0080) /* I2C Own Address Bit 7 */ +#define UCOA6_L (0x0040) /* I2C Own Address Bit 6 */ +#define UCOA5_L (0x0020) /* I2C Own Address Bit 5 */ +#define UCOA4_L (0x0010) /* I2C Own Address Bit 4 */ +#define UCOA3_L (0x0008) /* I2C Own Address Bit 3 */ +#define UCOA2_L (0x0004) /* I2C Own Address Bit 2 */ +#define UCOA1_L (0x0002) /* I2C Own Address Bit 1 */ +#define UCOA0_L (0x0001) /* I2C Own Address Bit 0 */ + +/* UCBxI2COA0 Control Bits */ +#define UCGCEN_H (0x0080) /* I2C General Call enable */ +#define UCOAEN_H (0x0004) /* I2C Own Address enable */ +#define UCOA9_H (0x0002) /* I2C Own Address Bit 9 */ +#define UCOA8_H (0x0001) /* I2C Own Address Bit 8 */ + +/* UCBxADDRX Control Bits */ +#define UCADDRX9 (0x0200) /* I2C Receive Address Bit 9 */ +#define UCADDRX8 (0x0100) /* I2C Receive Address Bit 8 */ +#define UCADDRX7 (0x0080) /* I2C Receive Address Bit 7 */ +#define UCADDRX6 (0x0040) /* I2C Receive Address Bit 6 */ +#define UCADDRX5 (0x0020) /* I2C Receive Address Bit 5 */ +#define UCADDRX4 (0x0010) /* I2C Receive Address Bit 4 */ +#define UCADDRX3 (0x0008) /* I2C Receive Address Bit 3 */ +#define UCADDRX2 (0x0004) /* I2C Receive Address Bit 2 */ +#define UCADDRX1 (0x0002) /* I2C Receive Address Bit 1 */ +#define UCADDRX0 (0x0001) /* I2C Receive Address Bit 0 */ + +/* UCBxADDRX Control Bits */ +#define UCADDRX7_L (0x0080) /* I2C Receive Address Bit 7 */ +#define UCADDRX6_L (0x0040) /* I2C Receive Address Bit 6 */ +#define UCADDRX5_L (0x0020) /* I2C Receive Address Bit 5 */ +#define UCADDRX4_L (0x0010) /* I2C Receive Address Bit 4 */ +#define UCADDRX3_L (0x0008) /* I2C Receive Address Bit 3 */ +#define UCADDRX2_L (0x0004) /* I2C Receive Address Bit 2 */ +#define UCADDRX1_L (0x0002) /* I2C Receive Address Bit 1 */ +#define UCADDRX0_L (0x0001) /* I2C Receive Address Bit 0 */ + +/* UCBxADDRX Control Bits */ +#define UCADDRX9_H (0x0002) /* I2C Receive Address Bit 9 */ +#define UCADDRX8_H (0x0001) /* I2C Receive Address Bit 8 */ + +/* UCBxADDMASK Control Bits */ +#define UCADDMASK9 (0x0200) /* I2C Address Mask Bit 9 */ +#define UCADDMASK8 (0x0100) /* I2C Address Mask Bit 8 */ +#define UCADDMASK7 (0x0080) /* I2C Address Mask Bit 7 */ +#define UCADDMASK6 (0x0040) /* I2C Address Mask Bit 6 */ +#define UCADDMASK5 (0x0020) /* I2C Address Mask Bit 5 */ +#define UCADDMASK4 (0x0010) /* I2C Address Mask Bit 4 */ +#define UCADDMASK3 (0x0008) /* I2C Address Mask Bit 3 */ +#define UCADDMASK2 (0x0004) /* I2C Address Mask Bit 2 */ +#define UCADDMASK1 (0x0002) /* I2C Address Mask Bit 1 */ +#define UCADDMASK0 (0x0001) /* I2C Address Mask Bit 0 */ + +/* UCBxADDMASK Control Bits */ +#define UCADDMASK7_L (0x0080) /* I2C Address Mask Bit 7 */ +#define UCADDMASK6_L (0x0040) /* I2C Address Mask Bit 6 */ +#define UCADDMASK5_L (0x0020) /* I2C Address Mask Bit 5 */ +#define UCADDMASK4_L (0x0010) /* I2C Address Mask Bit 4 */ +#define UCADDMASK3_L (0x0008) /* I2C Address Mask Bit 3 */ +#define UCADDMASK2_L (0x0004) /* I2C Address Mask Bit 2 */ +#define UCADDMASK1_L (0x0002) /* I2C Address Mask Bit 1 */ +#define UCADDMASK0_L (0x0001) /* I2C Address Mask Bit 0 */ + +/* UCBxADDMASK Control Bits */ +#define UCADDMASK9_H (0x0002) /* I2C Address Mask Bit 9 */ +#define UCADDMASK8_H (0x0001) /* I2C Address Mask Bit 8 */ + +/* UCBxI2CSA Control Bits */ +#define UCSA9 (0x0200) /* I2C Slave Address Bit 9 */ +#define UCSA8 (0x0100) /* I2C Slave Address Bit 8 */ +#define UCSA7 (0x0080) /* I2C Slave Address Bit 7 */ +#define UCSA6 (0x0040) /* I2C Slave Address Bit 6 */ +#define UCSA5 (0x0020) /* I2C Slave Address Bit 5 */ +#define UCSA4 (0x0010) /* I2C Slave Address Bit 4 */ +#define UCSA3 (0x0008) /* I2C Slave Address Bit 3 */ +#define UCSA2 (0x0004) /* I2C Slave Address Bit 2 */ +#define UCSA1 (0x0002) /* I2C Slave Address Bit 1 */ +#define UCSA0 (0x0001) /* I2C Slave Address Bit 0 */ + +/* UCBxI2CSA Control Bits */ +#define UCSA7_L (0x0080) /* I2C Slave Address Bit 7 */ +#define UCSA6_L (0x0040) /* I2C Slave Address Bit 6 */ +#define UCSA5_L (0x0020) /* I2C Slave Address Bit 5 */ +#define UCSA4_L (0x0010) /* I2C Slave Address Bit 4 */ +#define UCSA3_L (0x0008) /* I2C Slave Address Bit 3 */ +#define UCSA2_L (0x0004) /* I2C Slave Address Bit 2 */ +#define UCSA1_L (0x0002) /* I2C Slave Address Bit 1 */ +#define UCSA0_L (0x0001) /* I2C Slave Address Bit 0 */ + +/* UCBxI2CSA Control Bits */ +#define UCSA9_H (0x0002) /* I2C Slave Address Bit 9 */ +#define UCSA8_H (0x0001) /* I2C Slave Address Bit 8 */ + +/* UCAxIE UART Control Bits */ +#define UCTXCPTIE (0x0008) /* UART Transmit Complete Interrupt Enable */ +#define UCSTTIE (0x0004) /* UART Start Bit Interrupt Enalble */ +#define UCTXIE (0x0002) /* UART Transmit Interrupt Enable */ +#define UCRXIE (0x0001) /* UART Receive Interrupt Enable */ + +/* UCAxIE/UCBxIE SPI Control Bits */ + +/* UCBxIE I2C Control Bits */ +#define UCBIT9IE (0x4000) /* I2C Bit 9 Position Interrupt Enable 3 */ +#define UCTXIE3 (0x2000) /* I2C Transmit Interrupt Enable 3 */ +#define UCRXIE3 (0x1000) /* I2C Receive Interrupt Enable 3 */ +#define UCTXIE2 (0x0800) /* I2C Transmit Interrupt Enable 2 */ +#define UCRXIE2 (0x0400) /* I2C Receive Interrupt Enable 2 */ +#define UCTXIE1 (0x0200) /* I2C Transmit Interrupt Enable 1 */ +#define UCRXIE1 (0x0100) /* I2C Receive Interrupt Enable 1 */ +#define UCCLTOIE (0x0080) /* I2C Clock Low Timeout interrupt enable */ +#define UCBCNTIE (0x0040) /* I2C Automatic stop assertion interrupt enable */ +#define UCNACKIE (0x0020) /* I2C NACK Condition interrupt enable */ +#define UCALIE (0x0010) /* I2C Arbitration Lost interrupt enable */ +#define UCSTPIE (0x0008) /* I2C STOP Condition interrupt enable */ +#define UCTXIE0 (0x0002) /* I2C Transmit Interrupt Enable 0 */ +#define UCRXIE0 (0x0001) /* I2C Receive Interrupt Enable 0 */ + +/* UCAxIFG UART Control Bits */ +#define UCTXCPTIFG (0x0008) /* UART Transmit Complete Interrupt Flag */ +#define UCSTTIFG (0x0004) /* UART Start Bit Interrupt Flag */ +#define UCTXIFG (0x0002) /* UART Transmit Interrupt Flag */ +#define UCRXIFG (0x0001) /* UART Receive Interrupt Flag */ + +/* UCBxIFG Control Bits */ +#define UCBIT9IFG (0x4000) /* I2C Bit 9 Possition Interrupt Flag 3 */ +#define UCTXIFG3 (0x2000) /* I2C Transmit Interrupt Flag 3 */ +#define UCRXIFG3 (0x1000) /* I2C Receive Interrupt Flag 3 */ +#define UCTXIFG2 (0x0800) /* I2C Transmit Interrupt Flag 2 */ +#define UCRXIFG2 (0x0400) /* I2C Receive Interrupt Flag 2 */ +#define UCTXIFG1 (0x0200) /* I2C Transmit Interrupt Flag 1 */ +#define UCRXIFG1 (0x0100) /* I2C Receive Interrupt Flag 1 */ +#define UCCLTOIFG (0x0080) /* I2C Clock low Timeout interrupt Flag */ +#define UCBCNTIFG (0x0040) /* I2C Byte counter interrupt flag */ +#define UCNACKIFG (0x0020) /* I2C NACK Condition interrupt Flag */ +#define UCALIFG (0x0010) /* I2C Arbitration Lost interrupt Flag */ +#define UCSTPIFG (0x0008) /* I2C STOP Condition interrupt Flag */ +// #define UCSTTIFG (0x0004) /* I2C START Condition interrupt Flag */ +#define UCTXIFG0 (0x0002) /* I2C Transmit Interrupt Flag 0 */ +#define UCRXIFG0 (0x0001) /* I2C Receive Interrupt Flag 0 */ + +/* USCI UART Definitions */ +#define USCI_NONE (0x0000) /* No Interrupt pending */ +#define USCI_UART_UCRXIFG (0x0002) /* USCI UCRXIFG */ +#define USCI_UART_UCTXIFG (0x0004) /* USCI UCTXIFG */ +#define USCI_UART_UCSTTIFG (0x0006) /* USCI UCSTTIFG */ +#define USCI_UART_UCTXCPTIFG (0x0008) /* USCI UCTXCPTIFG */ + +/* USCI SPI Definitions */ +#define USCI_SPI_UCRXIFG (0x0002) /* USCI UCRXIFG */ +#define USCI_SPI_UCTXIFG (0x0004) /* USCI UCTXIFG */ + +/* USCI I2C Definitions */ +#define USCI_I2C_UCALIFG (0x0002) /* USCI I2C Mode: UCALIFG */ +#define USCI_I2C_UCNACKIFG (0x0004) /* USCI I2C Mode: UCNACKIFG */ +#define USCI_I2C_UCSTTIFG (0x0006) /* USCI I2C Mode: UCSTTIFG*/ +#define USCI_I2C_UCSTPIFG (0x0008) /* USCI I2C Mode: UCSTPIFG*/ +#define USCI_I2C_UCRXIFG3 (0x000A) /* USCI I2C Mode: UCRXIFG3 */ +#define USCI_I2C_UCTXIFG3 (0x000C) /* USCI I2C Mode: UCTXIFG3 */ +#define USCI_I2C_UCRXIFG2 (0x000E) /* USCI I2C Mode: UCRXIFG2 */ +#define USCI_I2C_UCTXIFG2 (0x0010) /* USCI I2C Mode: UCTXIFG2 */ +#define USCI_I2C_UCRXIFG1 (0x0012) /* USCI I2C Mode: UCRXIFG1 */ +#define USCI_I2C_UCTXIFG1 (0x0014) /* USCI I2C Mode: UCTXIFG1 */ +#define USCI_I2C_UCRXIFG0 (0x0016) /* USCI I2C Mode: UCRXIFG0 */ +#define USCI_I2C_UCTXIFG0 (0x0018) /* USCI I2C Mode: UCTXIFG0 */ +#define USCI_I2C_UCBCNTIFG (0x001A) /* USCI I2C Mode: UCBCNTIFG */ +#define USCI_I2C_UCCLTOIFG (0x001C) /* USCI I2C Mode: UCCLTOIFG */ +#define USCI_I2C_UCBIT9IFG (0x001E) /* USCI I2C Mode: UCBIT9IFG */ + +/************************************************************ +* WATCHDOG TIMER A +************************************************************/ + +#define WDTCTL 0x015C /* Watchdog Timer Control */ +/* The bit names have been prefixed with "WDT" */ +/* WDTCTL Control Bits */ +#define WDTIS0 (0x0001) /* WDT - Timer Interval Select 0 */ +#define WDTIS1 (0x0002) /* WDT - Timer Interval Select 1 */ +#define WDTIS2 (0x0004) /* WDT - Timer Interval Select 2 */ +#define WDTCNTCL (0x0008) /* WDT - Timer Clear */ +#define WDTTMSEL (0x0010) /* WDT - Timer Mode Select */ +#define WDTSSEL0 (0x0020) /* WDT - Timer Clock Source Select 0 */ +#define WDTSSEL1 (0x0040) /* WDT - Timer Clock Source Select 1 */ +#define WDTHOLD (0x0080) /* WDT - Timer hold */ + +/* WDTCTL Control Bits */ +#define WDTIS0_L (0x0001) /* WDT - Timer Interval Select 0 */ +#define WDTIS1_L (0x0002) /* WDT - Timer Interval Select 1 */ +#define WDTIS2_L (0x0004) /* WDT - Timer Interval Select 2 */ +#define WDTCNTCL_L (0x0008) /* WDT - Timer Clear */ +#define WDTTMSEL_L (0x0010) /* WDT - Timer Mode Select */ +#define WDTSSEL0_L (0x0020) /* WDT - Timer Clock Source Select 0 */ +#define WDTSSEL1_L (0x0040) /* WDT - Timer Clock Source Select 1 */ +#define WDTHOLD_L (0x0080) /* WDT - Timer hold */ + + +#define WDTPW (0x5A00) + +#define WDTIS_0 (0x0000) /* WDT - Timer Interval Select: /2G */ +#define WDTIS_1 (0x0001) /* WDT - Timer Interval Select: /128M */ +#define WDTIS_2 (0x0002) /* WDT - Timer Interval Select: /8192k */ +#define WDTIS_3 (0x0003) /* WDT - Timer Interval Select: /512k */ +#define WDTIS_4 (0x0004) /* WDT - Timer Interval Select: /32k */ +#define WDTIS_5 (0x0005) /* WDT - Timer Interval Select: /8192 */ +#define WDTIS_6 (0x0006) /* WDT - Timer Interval Select: /512 */ +#define WDTIS_7 (0x0007) /* WDT - Timer Interval Select: /64 */ +#define WDTIS__2G (0x0000) /* WDT - Timer Interval Select: /2G */ +#define WDTIS__128M (0x0001) /* WDT - Timer Interval Select: /128M */ +#define WDTIS__8192K (0x0002) /* WDT - Timer Interval Select: /8192k */ +#define WDTIS__512K (0x0003) /* WDT - Timer Interval Select: /512k */ +#define WDTIS__32K (0x0004) /* WDT - Timer Interval Select: /32k */ +#define WDTIS__8192 (0x0005) /* WDT - Timer Interval Select: /8192 */ +#define WDTIS__512 (0x0006) /* WDT - Timer Interval Select: /512 */ +#define WDTIS__64 (0x0007) /* WDT - Timer Interval Select: /64 */ + +#define WDTSSEL_0 (0x0000) /* WDT - Timer Clock Source Select: SMCLK */ +#define WDTSSEL_1 (0x0020) /* WDT - Timer Clock Source Select: ACLK */ +#define WDTSSEL_2 (0x0040) /* WDT - Timer Clock Source Select: VLO_CLK */ +#define WDTSSEL_3 (0x0060) /* WDT - Timer Clock Source Select: reserved */ +#define WDTSSEL__SMCLK (0x0000) /* WDT - Timer Clock Source Select: SMCLK */ +#define WDTSSEL__ACLK (0x0020) /* WDT - Timer Clock Source Select: ACLK */ +#define WDTSSEL__VLO (0x0040) /* WDT - Timer Clock Source Select: VLO_CLK */ + + +/* WDT-interval times [1ms] coded with Bits 0-2 */ +/* WDT is clocked by fSMCLK (assumed 1MHz) */ +#define WDT_MDLY_32 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2) /* 32ms interval (default) */ +#define WDT_MDLY_8 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTIS0) /* 8ms " */ +#define WDT_MDLY_0_5 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTIS1) /* 0.5ms " */ +#define WDT_MDLY_0_064 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTIS1+WDTIS0) /* 0.064ms " */ +/* WDT is clocked by fACLK (assumed 32KHz) */ +#define WDT_ADLY_1000 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0) /* 1000ms " */ +#define WDT_ADLY_250 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0+WDTIS0) /* 250ms " */ +#define WDT_ADLY_16 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0+WDTIS1) /* 16ms " */ +#define WDT_ADLY_1_9 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0+WDTIS1+WDTIS0) /* 1.9ms " */ +/* Watchdog mode -> reset after expired time */ +/* WDT is clocked by fSMCLK (assumed 1MHz) */ +#define WDT_MRST_32 (WDTPW+WDTCNTCL+WDTIS2) /* 32ms interval (default) */ +#define WDT_MRST_8 (WDTPW+WDTCNTCL+WDTIS2+WDTIS0) /* 8ms " */ +#define WDT_MRST_0_5 (WDTPW+WDTCNTCL+WDTIS2+WDTIS1) /* 0.5ms " */ +#define WDT_MRST_0_064 (WDTPW+WDTCNTCL+WDTIS2+WDTIS1+WDTIS0) /* 0.064ms " */ +/* WDT is clocked by fACLK (assumed 32KHz) */ +#define WDT_ARST_1000 (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2) /* 1000ms " */ +#define WDT_ARST_250 (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2+WDTIS0) /* 250ms " */ +#define WDT_ARST_16 (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2+WDTIS1) /* 16ms " */ +#define WDT_ARST_1_9 (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2+WDTIS1+WDTIS0) /* 1.9ms " */ + + +/************************************************************ +* TLV Descriptors +************************************************************/ + +#define TLV_CRC_LENGTH (0x1A01) /* CRC length of the TLV structure */ +#define TLV_CRC_VALUE (0x1A02) /* CRC value of the TLV structure */ +#define TLV_START (0x1A08) /* Start Address of the TLV structure */ +#define TLV_END (0x1AFF) /* End Address of the TLV structure */ + +#define TLV_LDTAG (0x01) /* Legacy descriptor (1xx, 2xx, 4xx families) */ +#define TLV_PDTAG (0x02) /* Peripheral discovery descriptor */ +#define TLV_Reserved3 (0x03) /* Future usage */ +#define TLV_Reserved4 (0x04) /* Future usage */ +#define TLV_BLANK (0x05) /* Blank descriptor */ +#define TLV_Reserved6 (0x06) /* Future usage */ +#define TLV_Reserved7 (0x07) /* Serial Number */ +#define TLV_DIERECORD (0x08) /* Die Record */ +#define TLV_ADCCAL (0x11) /* ADC12 calibration */ +#define TLV_ADC12CAL (0x11) /* ADC12 calibration */ +#define TLV_ADC10CAL (0x13) /* ADC10 calibration */ +#define TLV_REFCAL (0x12) /* REF calibration */ +#define TLV_TAGEXT (0xFE) /* Tag extender */ +#define TLV_TAGEND (0xFF) // Tag End of Table + + +/************************************************************ +* Interrupt Vectors (offset from 0xFF80 + 0x10 for Password) +************************************************************/ + + +#define AES256_VECTOR (31) /* 0xFFCC AES256 */ +#define RTC_VECTOR (32) /* 0xFFCE RTC */ +#define PORT4_VECTOR (33) /* 0xFFD0 Port 4 */ +#define PORT3_VECTOR (34) /* 0xFFD2 Port 3 */ +#define TIMER3_A1_VECTOR (35) /* 0xFFD4 Timer3_A2 CC1, TA */ +#define TIMER3_A0_VECTOR (36) /* 0xFFD6 Timer3_A2 CC0 */ +#define PORT2_VECTOR (37) /* 0xFFD8 Port 2 */ +#define TIMER2_A1_VECTOR (38) /* 0xFFDA Timer2_A2 CC1, TA */ +#define TIMER2_A0_VECTOR (39) /* 0xFFDC Timer2_A2 CC0 */ +#define PORT1_VECTOR (40) /* 0xFFDE Port 1 */ +#define TIMER1_A1_VECTOR (41) /* 0xFFE0 Timer1_A3 CC1-2, TA */ +#define TIMER1_A0_VECTOR (42) /* 0xFFE2 Timer1_A3 CC0 */ +#define DMA_VECTOR (43) /* 0xFFE4 DMA */ +#define USCI_A1_VECTOR (44) /* 0xFFE6 USCI A1 Receive/Transmit */ +#define TIMER0_A1_VECTOR (45) /* 0xFFE8 Timer0_A3 CC1-2, TA */ +#define TIMER0_A0_VECTOR (46) /* 0xFFEA Timer0_A3 CC0 */ +#define ADC12_VECTOR (47) /* 0xFFEC ADC */ +#define USCI_B0_VECTOR (48) /* 0xFFEE USCI B0 Receive/Transmit */ +#define USCI_A0_VECTOR (49) /* 0xFFF0 USCI A0 Receive/Transmit */ +#define WDT_VECTOR (50) /* 0xFFF2 Watchdog Timer */ +#define TIMER0_B1_VECTOR (51) /* 0xFFF4 Timer0_B7 CC1-6, TB */ +#define TIMER0_B0_VECTOR (52) /* 0xFFF6 Timer0_B7 CC0 */ +#define COMP_E_VECTOR (53) /* 0xFFF8 Comparator E */ +#define UNMI_VECTOR (54) /* 0xFFFA User Non-maskable */ +#define SYSNMI_VECTOR (55) /* 0xFFFC System Non-maskable */ +#define RESET_VECTOR ("reset") /* 0xFFFE Reset [Highest Priority] */ + +/************************************************************ +* End of Modules +************************************************************/ diff --git a/amforth-6.5/msp430/devices/msp430fr5969/words/cold.asm b/amforth-6.5/msp430/devices/msp430fr5969/words/cold.asm new file mode 100644 index 0000000..6abf0ba --- /dev/null +++ b/amforth-6.5/msp430/devices/msp430fr5969/words/cold.asm @@ -0,0 +1,30 @@ +CODEHEADER(XT_COLD,4,"cold") +main: ; Debugger requires the 'main' symbol. +reset: + mov #5A80h, &WDTCTL ; Watchdog off + + mov #0A500h, &MPUCTL0 ; Write password to enable access to MPU + mov FLASHSTART>>4, &MPUSEGB1 ; B1 = Start of memory + mov AMFORTH_START>>4, &MPUSEGB2 ; B2 = 0x10000 (Segment 3 is upper mem) + mov #7577h, &MPUSAM ; write protect core system. + mov #0A501h, &MPUCTL0 ; Enable MPU + mov.b #0, &MPUCTL0+1 ; Disable MPU access + + ;------------------------------------------------------------------------------ + ; Init Clock + + mov #0A500h, &CSCTL0 ; Enable access to clock registers + mov #0, &CSCTL3 ; Set all clock dividers to /1 + mov.b #0, &CSCTL0+1 ; Disable access to clock registers + + + ;------------------------------------------------------------------------------ + ; Forth registers + MOV #RSTACK,SP ; set up stack + MOV #PSTACK,PSP + MOV #UAREA,UP ; initial user pointer + + CLR R15 + ; now hand over to Forth with WARM (a colon word) + MOV #XT_WARM+2,IP + NEXT diff --git a/amforth-6.5/msp430/devices/msp430fr5969/words/env-mcu-info.asm b/amforth-6.5/msp430/devices/msp430fr5969/words/env-mcu-info.asm new file mode 100644 index 0000000..ec52936 --- /dev/null +++ b/amforth-6.5/msp430/devices/msp430fr5969/words/env-mcu-info.asm @@ -0,0 +1,11 @@ +ENVIRONMENT(XT_ENV_MCU_INFO,8,"mcu-info") + .DW XT_DOLITERAL + .dw mcuinfo + .DW XT_EXIT +mcuinfo: + ; first fixed sized elements + .dw RAMEND-RAMSTART ; RAM Size + .dw 0 ; EEPROM Size + .dw AMFORTH_START-1 ; max-dp + .dw 1 ; number of interrupts + diff --git a/amforth-6.5/msp430/devices/msp430fr5969/words/usart-init.asm b/amforth-6.5/msp430/devices/msp430fr5969/words/usart-init.asm new file mode 100644 index 0000000..322f05a --- /dev/null +++ b/amforth-6.5/msp430/devices/msp430fr5969/words/usart-init.asm @@ -0,0 +1,25 @@ + CODEHEADER(XT_USART,6,"+usart") + + ;------------------------------------------------------------------------------ + ; Init IO + + bic #LOCKLPM5, &PM5CTL0 ; Unlock I/O pins + mov.b #3, &P2SEL1 ; Use P2.0/P2.1 pins for Communication + mov.b #0, &P2SEL0 + + ;------------------------------------------------------------------------------ + ; Init serial communication + + ; f Baud UCOS16 UCBR UCBRF UCBRS + ; 8000000 115200 1 4 5 0x55 + + mov #UCSWRST, &UCA0CTLW0 ; **Put state machine in reset** + bis #UCSSEL__SMCLK, &UCA0CTLW0 ; SMCLK + + mov #4, &UCA0BRW ; 8 MHz 115200 Baud + mov #05501h|UCBRF_5, &UCA0MCTLW ; Modulation UCBRSx=55h, UCBRFx=5, UCOS16 + + bic #UCSWRST, &UCA0CTLW0 ; **Initialize USCI state machine** + ;------------------------------------------------------------------------------ + + NEXT diff --git a/amforth-6.5/msp430/devices/msp430g2553/device.asm b/amforth-6.5/msp430/devices/msp430g2553/device.asm new file mode 100644 index 0000000..eaf7c8b --- /dev/null +++ b/amforth-6.5/msp430/devices/msp430g2553/device.asm @@ -0,0 +1,36 @@ +; device specific +.include "msp430g2553.inc" ; MCU-specific register equates + +RAMSTART equ 0200h +RAMEND equ 0400h + +INFOSTART equ 01000h +INFOEND equ 010BFh ; do not allow config flash to be erased +FLASHSTART equ 0C000h +FLASHEND equ 0DFFFh +MAINSEG equ 512 +INFOSEG equ 64 +INFO_SIZE equ 128 ; bytes + +.if WANT_INTERRUPTS == 1 +.org 0FFE0h + + DC16 null_handler ; 01: 0FFE0 Unused + DC16 null_handler ; 02: 0FFE2 Unused + DC16 irq1_handler ; 03: 0FFE4 Port 1 + DC16 irq2_handler ; 04: 0FFE6 Port 2 + DC16 null_handler ; 05: 0FFE8 Unused + DC16 irq3_handler ; 06: 0FFEA ADC10 + DC16 irq4_handler ; 07: 0FFEC USCI Transmit - Terminal is polled + DC16 irq5_handler ; 08: 0FFEE USCI Receive - no use for them + DC16 irq6_handler ; 09: 0FFF0 Timer A + DC16 irq7_handler ; 10: 0FFF2 Timer A + DC16 null_handler ; 11: 0FFF4 Watchdog + DC16 irq8_handler ; 12: 0FFF6 Comparantor + DC16 irq9_handler ; 13: 0FFF8 Timer B + DC16 irq10_handler ; 14: 0FFFA Timer B + DC16 null_handler ; 15: 0FFFC NMI. Unused. +.endif + +.org 0FFFEh + DC16 reset ; FFFE - Reset diff --git a/amforth-6.5/msp430/devices/msp430g2553/device.py b/amforth-6.5/msp430/devices/msp430g2553/device.py new file mode 100644 index 0000000..513824d --- /dev/null +++ b/amforth-6.5/msp430/devices/msp430g2553/device.py @@ -0,0 +1,16 @@ +MCUREGS = { + 'P1IN': '$20', + 'P1OUT':'$21', + 'P1DIR':'$22', + 'P1REN':'$27', + + 'P2IN' :'$28', + 'P2OUT':'$29', + 'P2DIR':'$2a', + 'P2REN':'$2f', + + 'P3IN': '$18', + 'P3OUT':'$19', + 'P3DIR':'$1a', + 'P3REN':'$10', + } diff --git a/amforth-6.5/msp430/devices/msp430g2553/drivers.asm b/amforth-6.5/msp430/devices/msp430g2553/drivers.asm new file mode 100644 index 0000000..2793ccf --- /dev/null +++ b/amforth-6.5/msp430/devices/msp430g2553/drivers.asm @@ -0,0 +1,3 @@ + +.include "drivers/flash.inc" + diff --git a/amforth-6.5/msp430/devices/msp430g2553/init.asm b/amforth-6.5/msp430/devices/msp430g2553/init.asm new file mode 100644 index 0000000..f3806ca --- /dev/null +++ b/amforth-6.5/msp430/devices/msp430g2553/init.asm @@ -0,0 +1,3 @@ + +mcu_name: + .db 11,"MSP430G2553" diff --git a/amforth-6.5/msp430/devices/msp430g2553/msp430g2553.inc b/amforth-6.5/msp430/devices/msp430g2553/msp430g2553.inc new file mode 100644 index 0000000..71cba98 --- /dev/null +++ b/amforth-6.5/msp430/devices/msp430g2553/msp430g2553.inc @@ -0,0 +1,851 @@ +/******************************************************************** +* +* Standard register and bit definitions for the Texas Instruments +* MSP430G2553 microcontroller. +* +* Adapted for naken_asm - B. Rodriguez 1 mar 2014. +* +* Texas Instruments, Version 1.0 +* +* Rev. 1.0, Setup +* +********************************************************************/ + +/* ============================================================================ */ +/* Copyright (c) 2012, Texas Instruments Incorporated */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following conditions */ +/* are met: */ +/* */ +/* * Redistributions of source code must retain the above copyright */ +/* notice, this list of conditions and the following disclaimer. */ +/* */ +/* * Redistributions in binary form must reproduce the above copyright */ +/* notice, this list of conditions and the following disclaimer in the */ +/* documentation and/or other materials provided with the distribution. */ +/* */ +/* * Neither the name of Texas Instruments Incorporated nor the names of */ +/* its contributors may be used to endorse or promote products derived */ +/* from this software without specific prior written permission. */ +/* */ +/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" */ +/* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, */ +/* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR */ +/* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR */ +/* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, */ +/* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, */ +/* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; */ +/* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, */ +/* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR */ +/* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ============================================================================ */ + +/************************************************************ +* STANDARD BITS +************************************************************/ + +#define BIT0 (0x0001) +#define BIT1 (0x0002) +#define BIT2 (0x0004) +#define BIT3 (0x0008) +#define BIT4 (0x0010) +#define BIT5 (0x0020) +#define BIT6 (0x0040) +#define BIT7 (0x0080) +#define BIT8 (0x0100) +#define BIT9 (0x0200) +#define BITA (0x0400) +#define BITB (0x0800) +#define BITC (0x1000) +#define BITD (0x2000) +#define BITE (0x4000) +#define BITF (0x8000) + +/************************************************************ +* STATUS REGISTER BITS +************************************************************/ + +#define C (0x0001) +#define Z (0x0002) +#define N (0x0004) +#define V (0x0100) +#define GIE (0x0008) +#define CPUOFF (0x0010) +#define OSCOFF (0x0020) +#define SCG0 (0x0040) +#define SCG1 (0x0080) + +/* Low Power Modes coded with Bits 4-7 in SR */ + +#define LPM0 (CPUOFF) +#define LPM1 (SCG0+CPUOFF) +#define LPM2 (SCG1+CPUOFF) +#define LPM3 (SCG1+SCG0+CPUOFF) +#define LPM4 (SCG1+SCG0+OSCOFF+CPUOFF) + +/************************************************************ +* PERIPHERAL FILE MAP +************************************************************/ + +/************************************************************ +* SPECIAL FUNCTION REGISTER ADDRESSES + CONTROL BITS +************************************************************/ + +#define IE1 0x0000 /* Interrupt Enable 1 */ +#define WDTIE (0x01) /* Watchdog Interrupt Enable */ +#define OFIE (0x02) /* Osc. Fault Interrupt Enable */ +#define NMIIE (0x10) /* NMI Interrupt Enable */ +#define ACCVIE (0x20) /* Flash Access Violation Interrupt Enable */ + +#define IFG1 0x0002 /* Interrupt Flag 1 */ +#define WDTIFG (0x01) /* Watchdog Interrupt Flag */ +#define OFIFG (0x02) /* Osc. Fault Interrupt Flag */ +#define PORIFG (0x04) /* Power On Interrupt Flag */ +#define RSTIFG (0x08) /* Reset Interrupt Flag */ +#define NMIIFG (0x10) /* NMI Interrupt Flag */ + +#define IE2 0x0001 /* Interrupt Enable 2 */ +#define UC0IE IE2 +#define UCA0RXIE (0x01) +#define UCA0TXIE (0x02) +#define UCB0RXIE (0x04) +#define UCB0TXIE (0x08) + +#define IFG2 0x0003 /* Interrupt Flag 2 */ +#define UC0IFG IFG2 +#define UCA0RXIFG (0x01) +#define UCA0TXIFG (0x02) +#define UCB0RXIFG (0x04) +#define UCB0TXIFG (0x08) + + +/************************************************************ +* ADC10 +************************************************************/ +#define __MSP430_HAS_ADC10__ /* Definition to show that Module is available */ + +#define ADC10DTC0 0x0048 /* ADC10 Data Transfer Control 0 */ +#define ADC10DTC1 0x0049 /* ADC10 Data Transfer Control 1 */ +#define ADC10AE0 0x004A /* ADC10 Analog Enable 0 */ + +#define ADC10CTL0 0x01B0 /* ADC10 Control 0 */ +#define ADC10CTL1 0x01B2 /* ADC10 Control 1 */ +#define ADC10MEM 0x01B4 /* ADC10 Memory */ +#define ADC10SA 0x01BC /* ADC10 Data Transfer Start Address */ + +/* ADC10CTL0 */ +#define ADC10SC (0x001) /* ADC10 Start Conversion */ +#define ENC (0x002) /* ADC10 Enable Conversion */ +#define ADC10IFG (0x004) /* ADC10 Interrupt Flag */ +#define ADC10IE (0x008) /* ADC10 Interrupt Enalbe */ +#define ADC10ON (0x010) /* ADC10 On/Enable */ +#define REFON (0x020) /* ADC10 Reference on */ +#define REF2_5V (0x040) /* ADC10 Ref 0:1.5V / 1:2.5V */ +#define MSC (0x080) /* ADC10 Multiple SampleConversion */ +#define REFBURST (0x100) /* ADC10 Reference Burst Mode */ +#define REFOUT (0x200) /* ADC10 Enalbe output of Ref. */ +#define ADC10SR (0x400) /* ADC10 Sampling Rate 0:200ksps / 1:50ksps */ +#define ADC10SHT0 (0x800) /* ADC10 Sample Hold Select Bit: 0 */ +#define ADC10SHT1 (0x1000) /* ADC10 Sample Hold Select Bit: 1 */ +#define SREF0 (0x2000) /* ADC10 Reference Select Bit: 0 */ +#define SREF1 (0x4000) /* ADC10 Reference Select Bit: 1 */ +#define SREF2 (0x8000) /* ADC10 Reference Select Bit: 2 */ +#define ADC10SHT_0 (0x0000) /* 4 x ADC10CLKs */ +#define ADC10SHT_1 (0x0800) /* 8 x ADC10CLKs */ +#define ADC10SHT_2 (0x1000) /* 16 x ADC10CLKs */ +#define ADC10SHT_3 (0x1800) /* 64 x ADC10CLKs */ + +#define SREF_0 (0x0000) /* VR+ = AVCC and VR- = AVSS */ +#define SREF_1 (0x2000) /* VR+ = VREF+ and VR- = AVSS */ +#define SREF_2 (0x4000) /* VR+ = VEREF+ and VR- = AVSS */ +#define SREF_3 (0x6000) /* VR+ = VEREF+ and VR- = AVSS */ +#define SREF_4 (0x8000) /* VR+ = AVCC and VR- = VREF-/VEREF- */ +#define SREF_5 (0xA000) /* VR+ = VREF+ and VR- = VREF-/VEREF- */ +#define SREF_6 (0xC000) /* VR+ = VEREF+ and VR- = VREF-/VEREF- */ +#define SREF_7 (0xE000) /* VR+ = VEREF+ and VR- = VREF-/VEREF- */ + +/* ADC10CTL1 */ +#define ADC10BUSY (0x0001) /* ADC10 BUSY */ +#define CONSEQ0 (0x0002) /* ADC10 Conversion Sequence Select 0 */ +#define CONSEQ1 (0x0004) /* ADC10 Conversion Sequence Select 1 */ +#define ADC10SSEL0 (0x0008) /* ADC10 Clock Source Select Bit: 0 */ +#define ADC10SSEL1 (0x0010) /* ADC10 Clock Source Select Bit: 1 */ +#define ADC10DIV0 (0x0020) /* ADC10 Clock Divider Select Bit: 0 */ +#define ADC10DIV1 (0x0040) /* ADC10 Clock Divider Select Bit: 1 */ +#define ADC10DIV2 (0x0080) /* ADC10 Clock Divider Select Bit: 2 */ +#define ISSH (0x0100) /* ADC10 Invert Sample Hold Signal */ +#define ADC10DF (0x0200) /* ADC10 Data Format 0:binary 1:2's complement */ +#define SHS0 (0x0400) /* ADC10 Sample/Hold Source Bit: 0 */ +#define SHS1 (0x0800) /* ADC10 Sample/Hold Source Bit: 1 */ +#define INCH0 (0x1000) /* ADC10 Input Channel Select Bit: 0 */ +#define INCH1 (0x2000) /* ADC10 Input Channel Select Bit: 1 */ +#define INCH2 (0x4000) /* ADC10 Input Channel Select Bit: 2 */ +#define INCH3 (0x8000) /* ADC10 Input Channel Select Bit: 3 */ + +#define CONSEQ_0 (0x0000) /* Single channel single conversion */ +#define CONSEQ_1 (0x0002) /* Sequence of channels */ +#define CONSEQ_2 (0x0004) /* Repeat single channel */ +#define CONSEQ_3 (0x0006) /* Repeat sequence of channels */ + +#define ADC10SSEL_0 (0x0000) /* ADC10OSC */ +#define ADC10SSEL_1 (0x0008) /* ACLK */ +#define ADC10SSEL_2 (0x0010) /* MCLK */ +#define ADC10SSEL_3 (0x0018) /* SMCLK */ + +#define ADC10DIV_0 (0x0000) /* ADC10 Clock Divider Select 0 */ +#define ADC10DIV_1 (0x0020) /* ADC10 Clock Divider Select 1 */ +#define ADC10DIV_2 (0x0040) /* ADC10 Clock Divider Select 2 */ +#define ADC10DIV_3 (0x0060) /* ADC10 Clock Divider Select 3 */ +#define ADC10DIV_4 (0x0080) /* ADC10 Clock Divider Select 4 */ +#define ADC10DIV_5 (0x00A0) /* ADC10 Clock Divider Select 5 */ +#define ADC10DIV_6 (0x00C0) /* ADC10 Clock Divider Select 6 */ +#define ADC10DIV_7 (0x00E0) /* ADC10 Clock Divider Select 7 */ + +#define SHS_0 (0x0000) /* ADC10SC */ +#define SHS_1 (0x0400) /* TA3 OUT1 */ +#define SHS_2 (0x0800) /* TA3 OUT0 */ +#define SHS_3 (0x0C00) /* TA3 OUT2 */ + +#define INCH_0 (0x0000) /* Selects Channel 0 */ +#define INCH_1 (0x1000) /* Selects Channel 1 */ +#define INCH_2 (0x2000) /* Selects Channel 2 */ +#define INCH_3 (0x3000) /* Selects Channel 3 */ +#define INCH_4 (0x4000) /* Selects Channel 4 */ +#define INCH_5 (0x5000) /* Selects Channel 5 */ +#define INCH_6 (0x6000) /* Selects Channel 6 */ +#define INCH_7 (0x7000) /* Selects Channel 7 */ +#define INCH_8 (0x8000) /* Selects Channel 8 */ +#define INCH_9 (0x9000) /* Selects Channel 9 */ +#define INCH_10 (0xA000) /* Selects Channel 10 */ +#define INCH_11 (0xB000) /* Selects Channel 11 */ +#define INCH_12 (0xC000) /* Selects Channel 12 */ +#define INCH_13 (0xD000) /* Selects Channel 13 */ +#define INCH_14 (0xE000) /* Selects Channel 14 */ +#define INCH_15 (0xF000) /* Selects Channel 15 */ + +/* ADC10DTC0 */ +#define ADC10FETCH (0x001) /* This bit should normally be reset */ +#define ADC10B1 (0x002) /* ADC10 block one */ +#define ADC10CT (0x004) /* ADC10 continuous transfer */ +#define ADC10TB (0x008) /* ADC10 two-block mode */ +#define ADC10DISABLE (0x000) /* ADC10DTC1 */ + +/************************************************************ +* Basic Clock Module +************************************************************/ +#define __MSP430_HAS_BC2__ /* Definition to show that Module is available */ + +#define DCOCTL 0x0056 /* DCO Clock Frequency Control */ +#define BCSCTL1 0x0057 /* Basic Clock System Control 1 */ +#define BCSCTL2 0x0058 /* Basic Clock System Control 2 */ +#define BCSCTL3 0x0053 /* Basic Clock System Control 3 */ + +#define MOD0 (0x01) /* Modulation Bit 0 */ +#define MOD1 (0x02) /* Modulation Bit 1 */ +#define MOD2 (0x04) /* Modulation Bit 2 */ +#define MOD3 (0x08) /* Modulation Bit 3 */ +#define MOD4 (0x10) /* Modulation Bit 4 */ +#define DCO0 (0x20) /* DCO Select Bit 0 */ +#define DCO1 (0x40) /* DCO Select Bit 1 */ +#define DCO2 (0x80) /* DCO Select Bit 2 */ + +#define RSEL0 (0x01) /* Range Select Bit 0 */ +#define RSEL1 (0x02) /* Range Select Bit 1 */ +#define RSEL2 (0x04) /* Range Select Bit 2 */ +#define RSEL3 (0x08) /* Range Select Bit 3 */ +#define DIVA0 (0x10) /* ACLK Divider 0 */ +#define DIVA1 (0x20) /* ACLK Divider 1 */ +#define XTS (0x40) /* LFXTCLK 0:Low Freq. / 1: High Freq. */ +#define XT2OFF (0x80) /* Enable XT2CLK */ + +#define DIVA_0 (0x00) /* ACLK Divider 0: /1 */ +#define DIVA_1 (0x10) /* ACLK Divider 1: /2 */ +#define DIVA_2 (0x20) /* ACLK Divider 2: /4 */ +#define DIVA_3 (0x30) /* ACLK Divider 3: /8 */ + +#define DIVS0 (0x02) /* SMCLK Divider 0 */ +#define DIVS1 (0x04) /* SMCLK Divider 1 */ +#define SELS (0x08) /* SMCLK Source Select 0:DCOCLK / 1:XT2CLK/LFXTCLK */ +#define DIVM0 (0x10) /* MCLK Divider 0 */ +#define DIVM1 (0x20) /* MCLK Divider 1 */ +#define SELM0 (0x40) /* MCLK Source Select 0 */ +#define SELM1 (0x80) /* MCLK Source Select 1 */ + +#define DIVS_0 (0x00) /* SMCLK Divider 0: /1 */ +#define DIVS_1 (0x02) /* SMCLK Divider 1: /2 */ +#define DIVS_2 (0x04) /* SMCLK Divider 2: /4 */ +#define DIVS_3 (0x06) /* SMCLK Divider 3: /8 */ + +#define DIVM_0 (0x00) /* MCLK Divider 0: /1 */ +#define DIVM_1 (0x10) /* MCLK Divider 1: /2 */ +#define DIVM_2 (0x20) /* MCLK Divider 2: /4 */ +#define DIVM_3 (0x30) /* MCLK Divider 3: /8 */ + +#define SELM_0 (0x00) /* MCLK Source Select 0: DCOCLK */ +#define SELM_1 (0x40) /* MCLK Source Select 1: DCOCLK */ +#define SELM_2 (0x80) /* MCLK Source Select 2: XT2CLK/LFXTCLK */ +#define SELM_3 (0xC0) /* MCLK Source Select 3: LFXTCLK */ + +#define LFXT1OF (0x01) /* Low/high Frequency Oscillator Fault Flag */ +#define XT2OF (0x02) /* High frequency oscillator 2 fault flag */ +#define XCAP0 (0x04) /* XIN/XOUT Cap 0 */ +#define XCAP1 (0x08) /* XIN/XOUT Cap 1 */ +#define LFXT1S0 (0x10) /* Mode 0 for LFXT1 (XTS = 0) */ +#define LFXT1S1 (0x20) /* Mode 1 for LFXT1 (XTS = 0) */ +#define XT2S0 (0x40) /* Mode 0 for XT2 */ +#define XT2S1 (0x80) /* Mode 1 for XT2 */ + +#define XCAP_0 (0x00) /* XIN/XOUT Cap : 0 pF */ +#define XCAP_1 (0x04) /* XIN/XOUT Cap : 6 pF */ +#define XCAP_2 (0x08) /* XIN/XOUT Cap : 10 pF */ +#define XCAP_3 (0x0C) /* XIN/XOUT Cap : 12.5 pF */ + +#define LFXT1S_0 (0x00) /* Mode 0 for LFXT1 : Normal operation */ +#define LFXT1S_1 (0x10) /* Mode 1 for LFXT1 : Reserved */ +#define LFXT1S_2 (0x20) /* Mode 2 for LFXT1 : VLO */ +#define LFXT1S_3 (0x30) /* Mode 3 for LFXT1 : Digital input signal */ + +#define XT2S_0 (0x00) /* Mode 0 for XT2 : 0.4 - 1 MHz */ +#define XT2S_1 (0x40) /* Mode 1 for XT2 : 1 - 4 MHz */ +#define XT2S_2 (0x80) /* Mode 2 for XT2 : 2 - 16 MHz */ +#define XT2S_3 (0xC0) /* Mode 3 for XT2 : Digital input signal */ + +/************************************************************ +* Comparator A +************************************************************/ +#define __MSP430_HAS_CAPLUS__ /* Definition to show that Module is available */ + +#define CACTL1 0x0059 /* Comparator A Control 1 */ +#define CACTL2 0x005A /* Comparator A Control 2 */ +#define CAPD 0x005B /* Comparator A Port Disable */ + +#define CAIFG (0x01) /* Comp. A Interrupt Flag */ +#define CAIE (0x02) /* Comp. A Interrupt Enable */ +#define CAIES (0x04) /* Comp. A Int. Edge Select: 0:rising / 1:falling */ +#define CAON (0x08) /* Comp. A enable */ +#define CAREF0 (0x10) /* Comp. A Internal Reference Select 0 */ +#define CAREF1 (0x20) /* Comp. A Internal Reference Select 1 */ +#define CARSEL (0x40) /* Comp. A Internal Reference Enable */ +#define CAEX (0x80) /* Comp. A Exchange Inputs */ + +#define CAREF_0 (0x00) /* Comp. A Int. Ref. Select 0 : Off */ +#define CAREF_1 (0x10) /* Comp. A Int. Ref. Select 1 : 0.25*Vcc */ +#define CAREF_2 (0x20) /* Comp. A Int. Ref. Select 2 : 0.5*Vcc */ +#define CAREF_3 (0x30) /* Comp. A Int. Ref. Select 3 : Vt*/ + +#define CAOUT (0x01) /* Comp. A Output */ +#define CAF (0x02) /* Comp. A Enable Output Filter */ +#define P2CA0 (0x04) /* Comp. A +Terminal Multiplexer */ +#define P2CA1 (0x08) /* Comp. A -Terminal Multiplexer */ +#define P2CA2 (0x10) /* Comp. A -Terminal Multiplexer */ +#define P2CA3 (0x20) /* Comp. A -Terminal Multiplexer */ +#define P2CA4 (0x40) /* Comp. A +Terminal Multiplexer */ +#define CASHORT (0x80) /* Comp. A Short + and - Terminals */ + +#define CAPD0 (0x01) /* Comp. A Disable Input Buffer of Port Register .0 */ +#define CAPD1 (0x02) /* Comp. A Disable Input Buffer of Port Register .1 */ +#define CAPD2 (0x04) /* Comp. A Disable Input Buffer of Port Register .2 */ +#define CAPD3 (0x08) /* Comp. A Disable Input Buffer of Port Register .3 */ +#define CAPD4 (0x10) /* Comp. A Disable Input Buffer of Port Register .4 */ +#define CAPD5 (0x20) /* Comp. A Disable Input Buffer of Port Register .5 */ +#define CAPD6 (0x40) /* Comp. A Disable Input Buffer of Port Register .6 */ +#define CAPD7 (0x80) /* Comp. A Disable Input Buffer of Port Register .7 */ + +/************************************************************* +* Flash Memory +*************************************************************/ +#define __MSP430_HAS_FLASH2__ /* Definition to show that Module is available */ + +#define FCTL1 0x0128 /* FLASH Control 1 */ +#define FCTL2 0x012A /* FLASH Control 2 */ +#define FCTL3 0x012C /* FLASH Control 3 */ + +#define FRKEY (0x9600) /* Flash key returned by read */ +#define FWKEY (0xA500) /* Flash key for write */ +#define FXKEY (0x3300) /* for use with XOR instruction */ + +#define ERASE (0x0002) /* Enable bit for Flash segment erase */ +#define MERAS (0x0004) /* Enable bit for Flash mass erase */ +#define WRT (0x0040) /* Enable bit for Flash write */ +#define BLKWRT (0x0080) /* Enable bit for Flash segment write */ +#define SEGWRT (0x0080) /* old definition */ /* Enable bit for Flash segment write */ + +#define FN0 (0x0001) /* Divide Flash clock by 1 to 64 using FN0 to FN5 according to: */ +#define FN1 (0x0002) /* 32*FN5 + 16*FN4 + 8*FN3 + 4*FN2 + 2*FN1 + FN0 + 1 */ +#define FN2 (0x0004) +#define FN3 (0x0008) +#define FN4 (0x0010) +#define FN5 (0x0020) +#define FSSEL0 (0x0040) /* Flash clock select 0 */ /* to distinguish from USART SSELx */ +#define FSSEL1 (0x0080) /* Flash clock select 1 */ + +#define FSSEL_0 (0x0000) /* Flash clock select: 0 - ACLK */ +#define FSSEL_1 (0x0040) /* Flash clock select: 1 - MCLK */ +#define FSSEL_2 (0x0080) /* Flash clock select: 2 - SMCLK */ +#define FSSEL_3 (0x00C0) /* Flash clock select: 3 - SMCLK */ + +#define BUSY (0x0001) /* Flash busy: 1 */ +#define KEYV (0x0002) /* Flash Key violation flag */ +#define ACCVIFG (0x0004) /* Flash Access violation flag */ +#define WAIT (0x0008) /* Wait flag for segment write */ +#define LOCK (0x0010) /* Lock bit: 1 - Flash is locked (read only) */ +#define EMEX (0x0020) /* Flash Emergency Exit */ +#define LOCKA (0x0040) /* Segment A Lock bit: read = 1 - Segment is locked (read only) */ +#define FAIL (0x0080) /* Last Program or Erase failed */ + +/************************************************************ +* DIGITAL I/O Port1/2 Pull up / Pull down Resistors +************************************************************/ +#define __MSP430_HAS_PORT1_R__ /* Definition to show that Module is available */ +#define __MSP430_HAS_PORT2_R__ /* Definition to show that Module is available */ + +#define P1IN 0x0020 /* Port 1 Input */ +#define P1OUT 0x0021 /* Port 1 Output */ +#define P1DIR 0x0022 /* Port 1 Direction */ +#define P1IFG 0x0023 /* Port 1 Interrupt Flag */ +#define P1IES 0x0024 /* Port 1 Interrupt Edge Select */ +#define P1IE 0x0025 /* Port 1 Interrupt Enable */ +#define P1SEL 0x0026 /* Port 1 Selection */ +#define P1SEL2 0x0041 /* Port 1 Selection 2 */ +#define P1REN 0x0027 /* Port 1 Resistor Enable */ + +#define P2IN 0x0028 /* Port 2 Input */ +#define P2OUT 0x0029 /* Port 2 Output */ +#define P2DIR 0x002A /* Port 2 Direction */ +#define P2IFG 0x002B /* Port 2 Interrupt Flag */ +#define P2IES 0x002C /* Port 2 Interrupt Edge Select */ +#define P2IE 0x002D /* Port 2 Interrupt Enable */ +#define P2SEL 0x002E /* Port 2 Selection */ +#define P2SEL2 0x0042 /* Port 2 Selection 2 */ +#define P2REN 0x002F /* Port 2 Resistor Enable */ + +/************************************************************ +* DIGITAL I/O Port3 Pull up / Pull down Resistors +************************************************************/ +#define __MSP430_HAS_PORT3_R__ /* Definition to show that Module is available */ + +#define P3IN 0x0018 /* Port 3 Input */ +#define P3OUT 0x0019 /* Port 3 Output */ +#define P3DIR 0x001A /* Port 3 Direction */ +#define P3SEL 0x001B /* Port 3 Selection */ +#define P3SEL2 0x0043 /* Port 3 Selection 2 */ +#define P3REN 0x0010 /* Port 3 Resistor Enable */ + +/************************************************************ +* Timer0_A3 +************************************************************/ +#define __MSP430_HAS_TA3__ /* Definition to show that Module is available */ + +#define TA0IV 0x012E /* Timer0_A3 Interrupt Vector Word */ +#define TA0CTL 0x0160 /* Timer0_A3 Control */ +#define TA0CCTL0 0x0162 /* Timer0_A3 Capture/Compare Control 0 */ +#define TA0CCTL1 0x0164 /* Timer0_A3 Capture/Compare Control 1 */ +#define TA0CCTL2 0x0166 /* Timer0_A3 Capture/Compare Control 2 */ +#define TA0R 0x0170 /* Timer0_A3 */ +#define TA0CCR0 0x0172 /* Timer0_A3 Capture/Compare 0 */ +#define TA0CCR1 0x0174 /* Timer0_A3 Capture/Compare 1 */ +#define TA0CCR2 0x0176 /* Timer0_A3 Capture/Compare 2 */ + +/* Alternate register names */ +#define TAIV TA0IV /* Timer A Interrupt Vector Word */ +#define TACTL TA0CTL /* Timer A Control */ +#define TACCTL0 TA0CCTL0 /* Timer A Capture/Compare Control 0 */ +#define TACCTL1 TA0CCTL1 /* Timer A Capture/Compare Control 1 */ +#define TACCTL2 TA0CCTL2 /* Timer A Capture/Compare Control 2 */ +#define TAR TA0R /* Timer A */ +#define TACCR0 TA0CCR0 /* Timer A Capture/Compare 0 */ +#define TACCR1 TA0CCR1 /* Timer A Capture/Compare 1 */ +#define TACCR2 TA0CCR2 /* Timer A Capture/Compare 2 */ +#define TAIV_ TA0IV_ /* Timer A Interrupt Vector Word */ +#define TACTL_ TA0CTL_ /* Timer A Control */ +#define TACCTL0_ TA0CCTL0_ /* Timer A Capture/Compare Control 0 */ +#define TACCTL1_ TA0CCTL1_ /* Timer A Capture/Compare Control 1 */ +#define TACCTL2_ TA0CCTL2_ /* Timer A Capture/Compare Control 2 */ +#define TAR_ TA0R_ /* Timer A */ +#define TACCR0_ TA0CCR0_ /* Timer A Capture/Compare 0 */ +#define TACCR1_ TA0CCR1_ /* Timer A Capture/Compare 1 */ +#define TACCR2_ TA0CCR2_ /* Timer A Capture/Compare 2 */ + +/* Alternate register names 2 */ +#define CCTL0 TACCTL0 /* Timer A Capture/Compare Control 0 */ +#define CCTL1 TACCTL1 /* Timer A Capture/Compare Control 1 */ +#define CCTL2 TACCTL2 /* Timer A Capture/Compare Control 2 */ +#define CCR0 TACCR0 /* Timer A Capture/Compare 0 */ +#define CCR1 TACCR1 /* Timer A Capture/Compare 1 */ +#define CCR2 TACCR2 /* Timer A Capture/Compare 2 */ +#define CCTL0_ TACCTL0_ /* Timer A Capture/Compare Control 0 */ +#define CCTL1_ TACCTL1_ /* Timer A Capture/Compare Control 1 */ +#define CCTL2_ TACCTL2_ /* Timer A Capture/Compare Control 2 */ +#define CCR0_ TACCR0_ /* Timer A Capture/Compare 0 */ +#define CCR1_ TACCR1_ /* Timer A Capture/Compare 1 */ +#define CCR2_ TACCR2_ /* Timer A Capture/Compare 2 */ + +#define TASSEL1 (0x0200) /* Timer A clock source select 1 */ +#define TASSEL0 (0x0100) /* Timer A clock source select 0 */ +#define ID1 (0x0080) /* Timer A clock input divider 1 */ +#define ID0 (0x0040) /* Timer A clock input divider 0 */ +#define MC1 (0x0020) /* Timer A mode control 1 */ +#define MC0 (0x0010) /* Timer A mode control 0 */ +#define TACLR (0x0004) /* Timer A counter clear */ +#define TAIE (0x0002) /* Timer A counter interrupt enable */ +#define TAIFG (0x0001) /* Timer A counter interrupt flag */ + +#define MC_0 (0x0000) /* Timer A mode control: 0 - Stop */ +#define MC_1 (0x0010) /* Timer A mode control: 1 - Up to CCR0 */ +#define MC_2 (0x0020) /* Timer A mode control: 2 - Continous up */ +#define MC_3 (0x0030) /* Timer A mode control: 3 - Up/Down */ +#define ID_0 (0x0000) /* Timer A input divider: 0 - /1 */ +#define ID_1 (0x0040) /* Timer A input divider: 1 - /2 */ +#define ID_2 (0x0080) /* Timer A input divider: 2 - /4 */ +#define ID_3 (0x00C0) /* Timer A input divider: 3 - /8 */ +#define TASSEL_0 (0x0000) /* Timer A clock source select: 0 - TACLK */ +#define TASSEL_1 (0x0100) /* Timer A clock source select: 1 - ACLK */ +#define TASSEL_2 (0x0200) /* Timer A clock source select: 2 - SMCLK */ +#define TASSEL_3 (0x0300) /* Timer A clock source select: 3 - INCLK */ + +#define CM1 (0x8000) /* Capture mode 1 */ +#define CM0 (0x4000) /* Capture mode 0 */ +#define CCIS1 (0x2000) /* Capture input select 1 */ +#define CCIS0 (0x1000) /* Capture input select 0 */ +#define SCS (0x0800) /* Capture sychronize */ +#define SCCI (0x0400) /* Latched capture signal (read) */ +#define CAP (0x0100) /* Capture mode: 1 /Compare mode : 0 */ +#define OUTMOD2 (0x0080) /* Output mode 2 */ +#define OUTMOD1 (0x0040) /* Output mode 1 */ +#define OUTMOD0 (0x0020) /* Output mode 0 */ +#define CCIE (0x0010) /* Capture/compare interrupt enable */ +#define CCI (0x0008) /* Capture input signal (read) */ +#define OUT (0x0004) /* PWM Output signal if output mode 0 */ +#define COV (0x0002) /* Capture/compare overflow flag */ +#define CCIFG (0x0001) /* Capture/compare interrupt flag */ + +#define OUTMOD_0 (0x0000) /* PWM output mode: 0 - output only */ +#define OUTMOD_1 (0x0020) /* PWM output mode: 1 - set */ +#define OUTMOD_2 (0x0040) /* PWM output mode: 2 - PWM toggle/reset */ +#define OUTMOD_3 (0x0060) /* PWM output mode: 3 - PWM set/reset */ +#define OUTMOD_4 (0x0080) /* PWM output mode: 4 - toggle */ +#define OUTMOD_5 (0x00A0) /* PWM output mode: 5 - Reset */ +#define OUTMOD_6 (0x00C0) /* PWM output mode: 6 - PWM toggle/set */ +#define OUTMOD_7 (0x00E0) /* PWM output mode: 7 - PWM reset/set */ +#define CCIS_0 (0x0000) /* Capture input select: 0 - CCIxA */ +#define CCIS_1 (0x1000) /* Capture input select: 1 - CCIxB */ +#define CCIS_2 (0x2000) /* Capture input select: 2 - GND */ +#define CCIS_3 (0x3000) /* Capture input select: 3 - Vcc */ +#define CM_0 (0x0000) /* Capture mode: 0 - disabled */ +#define CM_1 (0x4000) /* Capture mode: 1 - pos. edge */ +#define CM_2 (0x8000) /* Capture mode: 1 - neg. edge */ +#define CM_3 (0xC000) /* Capture mode: 1 - both edges */ + +/* T0_A3IV Definitions */ +#define TA0IV_NONE (0x0000) /* No Interrupt pending */ +#define TA0IV_TACCR1 (0x0002) /* TA0CCR1_CCIFG */ +#define TA0IV_TACCR2 (0x0004) /* TA0CCR2_CCIFG */ +#define TA0IV_6 (0x0006) /* Reserved */ +#define TA0IV_8 (0x0008) /* Reserved */ +#define TA0IV_TAIFG (0x000A) /* TA0IFG */ + +/************************************************************ +* Timer1_A3 +************************************************************/ +#define __MSP430_HAS_T1A3__ /* Definition to show that Module is available */ + +#define TA1IV 0x011E /* Timer1_A3 Interrupt Vector Word */ +#define TA1CTL 0x0180 /* Timer1_A3 Control */ +#define TA1CCTL0 0x0182 /* Timer1_A3 Capture/Compare Control 0 */ +#define TA1CCTL1 0x0184 /* Timer1_A3 Capture/Compare Control 1 */ +#define TA1CCTL2 0x0186 /* Timer1_A3 Capture/Compare Control 2 */ +#define TA1R 0x0190 /* Timer1_A3 */ +#define TA1CCR0 0x0192 /* Timer1_A3 Capture/Compare 0 */ +#define TA1CCR1 0x0194 /* Timer1_A3 Capture/Compare 1 */ +#define TA1CCR2 0x0196 /* Timer1_A3 Capture/Compare 2 */ + +/* Bits are already defined within the Timer0_Ax */ + +/* T1_A3IV Definitions */ +#define TA1IV_NONE (0x0000) /* No Interrupt pending */ +#define TA1IV_TACCR1 (0x0002) /* TA1CCR1_CCIFG */ +#define TA1IV_TACCR2 (0x0004) /* TA1CCR2_CCIFG */ +#define TA1IV_TAIFG (0x000A) /* TA1IFG */ + +/************************************************************ +* USCI +************************************************************/ +#define __MSP430_HAS_USCI__ /* Definition to show that Module is available */ + +#define UCA0CTL0 0x0060 /* USCI A0 Control Register 0 */ +#define UCA0CTL1 0x0061 /* USCI A0 Control Register 1 */ +#define UCA0BR0 0x0062 /* USCI A0 Baud Rate 0 */ +#define UCA0BR1 0x0063 /* USCI A0 Baud Rate 1 */ +#define UCA0MCTL 0x0064 /* USCI A0 Modulation Control */ +#define UCA0STAT 0x0065 /* USCI A0 Status Register */ +#define UCA0RXBUF 0x0066 /* USCI A0 Receive Buffer */ +#define UCA0TXBUF 0x0067 /* USCI A0 Transmit Buffer */ +#define UCA0ABCTL 0x005D /* USCI A0 LIN Control */ +#define UCA0IRTCTL 0x005E /* USCI A0 IrDA Transmit Control */ +#define UCA0IRRCTL 0x005F /* USCI A0 IrDA Receive Control */ + +#define UCB0CTL0 0x0068 /* USCI B0 Control Register 0 */ +#define UCB0CTL1 0x0069 /* USCI B0 Control Register 1 */ +#define UCB0BR0 0x006A /* USCI B0 Baud Rate 0 */ +#define UCB0BR1 0x006B /* USCI B0 Baud Rate 1 */ +#define UCB0I2CIE 0x006C /* USCI B0 I2C Interrupt Enable Register */ +#define UCB0STAT 0x006D /* USCI B0 Status Register */ +#define UCB0RXBUF 0x006E /* USCI B0 Receive Buffer */ +#define UCB0TXBUF 0x006F /* USCI B0 Transmit Buffer */ +#define UCB0I2COA 0x0118 /* USCI B0 I2C Own Address */ +#define UCB0I2CSA 0x011A /* USCI B0 I2C Slave Address */ + +// UART-Mode Bits +#define UCPEN (0x80) /* Async. Mode: Parity enable */ +#define UCPAR (0x40) /* Async. Mode: Parity 0:odd / 1:even */ +#define UCMSB (0x20) /* Async. Mode: MSB first 0:LSB / 1:MSB */ +#define UC7BIT (0x10) /* Async. Mode: Data Bits 0:8-bits / 1:7-bits */ +#define UCSPB (0x08) /* Async. Mode: Stop Bits 0:one / 1: two */ +#define UCMODE1 (0x04) /* Async. Mode: USCI Mode 1 */ +#define UCMODE0 (0x02) /* Async. Mode: USCI Mode 0 */ +#define UCSYNC (0x01) /* Sync-Mode 0:UART-Mode / 1:SPI-Mode */ + +// SPI-Mode Bits +#define UCCKPH (0x80) /* Sync. Mode: Clock Phase */ +#define UCCKPL (0x40) /* Sync. Mode: Clock Polarity */ +#define UCMST (0x08) /* Sync. Mode: Master Select */ + +// I2C-Mode Bits +#define UCA10 (0x80) /* 10-bit Address Mode */ +#define UCSLA10 (0x40) /* 10-bit Slave Address Mode */ +#define UCMM (0x20) /* Multi-Master Environment */ +//#define res (0x10) /* reserved */ +#define UCMODE_0 (0x00) /* Sync. Mode: USCI Mode: 0 */ +#define UCMODE_1 (0x02) /* Sync. Mode: USCI Mode: 1 */ +#define UCMODE_2 (0x04) /* Sync. Mode: USCI Mode: 2 */ +#define UCMODE_3 (0x06) /* Sync. Mode: USCI Mode: 3 */ + +// UART-Mode Bits +#define UCSSEL1 (0x80) /* USCI 0 Clock Source Select 1 */ +#define UCSSEL0 (0x40) /* USCI 0 Clock Source Select 0 */ +#define UCRXEIE (0x20) /* RX Error interrupt enable */ +#define UCBRKIE (0x10) /* Break interrupt enable */ +#define UCDORM (0x08) /* Dormant (Sleep) Mode */ +#define UCTXADDR (0x04) /* Send next Data as Address */ +#define UCTXBRK (0x02) /* Send next Data as Break */ +#define UCSWRST (0x01) /* USCI Software Reset */ + +// SPI-Mode Bits +//#define res (0x20) /* reserved */ +//#define res (0x10) /* reserved */ +//#define res (0x08) /* reserved */ +//#define res (0x04) /* reserved */ +//#define res (0x02) /* reserved */ + +// I2C-Mode Bits +//#define res (0x20) /* reserved */ +#define UCTR (0x10) /* Transmit/Receive Select/Flag */ +#define UCTXNACK (0x08) /* Transmit NACK */ +#define UCTXSTP (0x04) /* Transmit STOP */ +#define UCTXSTT (0x02) /* Transmit START */ +#define UCSSEL_0 (0x00) /* USCI 0 Clock Source: 0 */ +#define UCSSEL_1 (0x40) /* USCI 0 Clock Source: 1 */ +#define UCSSEL_2 (0x80) /* USCI 0 Clock Source: 2 */ +#define UCSSEL_3 (0xC0) /* USCI 0 Clock Source: 3 */ + +#define UCBRF3 (0x80) /* USCI First Stage Modulation Select 3 */ +#define UCBRF2 (0x40) /* USCI First Stage Modulation Select 2 */ +#define UCBRF1 (0x20) /* USCI First Stage Modulation Select 1 */ +#define UCBRF0 (0x10) /* USCI First Stage Modulation Select 0 */ +#define UCBRS2 (0x08) /* USCI Second Stage Modulation Select 2 */ +#define UCBRS1 (0x04) /* USCI Second Stage Modulation Select 1 */ +#define UCBRS0 (0x02) /* USCI Second Stage Modulation Select 0 */ +#define UCOS16 (0x01) /* USCI 16-times Oversampling enable */ + +#define UCBRF_0 (0x00) /* USCI First Stage Modulation: 0 */ +#define UCBRF_1 (0x10) /* USCI First Stage Modulation: 1 */ +#define UCBRF_2 (0x20) /* USCI First Stage Modulation: 2 */ +#define UCBRF_3 (0x30) /* USCI First Stage Modulation: 3 */ +#define UCBRF_4 (0x40) /* USCI First Stage Modulation: 4 */ +#define UCBRF_5 (0x50) /* USCI First Stage Modulation: 5 */ +#define UCBRF_6 (0x60) /* USCI First Stage Modulation: 6 */ +#define UCBRF_7 (0x70) /* USCI First Stage Modulation: 7 */ +#define UCBRF_8 (0x80) /* USCI First Stage Modulation: 8 */ +#define UCBRF_9 (0x90) /* USCI First Stage Modulation: 9 */ +#define UCBRF_10 (0xA0) /* USCI First Stage Modulation: A */ +#define UCBRF_11 (0xB0) /* USCI First Stage Modulation: B */ +#define UCBRF_12 (0xC0) /* USCI First Stage Modulation: C */ +#define UCBRF_13 (0xD0) /* USCI First Stage Modulation: D */ +#define UCBRF_14 (0xE0) /* USCI First Stage Modulation: E */ +#define UCBRF_15 (0xF0) /* USCI First Stage Modulation: F */ + +#define UCBRS_0 (0x00) /* USCI Second Stage Modulation: 0 */ +#define UCBRS_1 (0x02) /* USCI Second Stage Modulation: 1 */ +#define UCBRS_2 (0x04) /* USCI Second Stage Modulation: 2 */ +#define UCBRS_3 (0x06) /* USCI Second Stage Modulation: 3 */ +#define UCBRS_4 (0x08) /* USCI Second Stage Modulation: 4 */ +#define UCBRS_5 (0x0A) /* USCI Second Stage Modulation: 5 */ +#define UCBRS_6 (0x0C) /* USCI Second Stage Modulation: 6 */ +#define UCBRS_7 (0x0E) /* USCI Second Stage Modulation: 7 */ + +#define UCLISTEN (0x80) /* USCI Listen mode */ +#define UCFE (0x40) /* USCI Frame Error Flag */ +#define UCOE (0x20) /* USCI Overrun Error Flag */ +#define UCPE (0x10) /* USCI Parity Error Flag */ +#define UCBRK (0x08) /* USCI Break received */ +#define UCRXERR (0x04) /* USCI RX Error Flag */ +#define UCADDR (0x02) /* USCI Address received Flag */ +#define UCBUSY (0x01) /* USCI Busy Flag */ +#define UCIDLE (0x02) /* USCI Idle line detected Flag */ + +//#define res (0x80) /* reserved */ +//#define res (0x40) /* reserved */ +//#define res (0x20) /* reserved */ +//#define res (0x10) /* reserved */ +#define UCNACKIE (0x08) /* NACK Condition interrupt enable */ +#define UCSTPIE (0x04) /* STOP Condition interrupt enable */ +#define UCSTTIE (0x02) /* START Condition interrupt enable */ +#define UCALIE (0x01) /* Arbitration Lost interrupt enable */ + + +#define UCSCLLOW (0x40) /* SCL low */ +#define UCGC (0x20) /* General Call address received Flag */ +#define UCBBUSY (0x10) /* Bus Busy Flag */ +#define UCNACKIFG (0x08) /* NAK Condition interrupt Flag */ +#define UCSTPIFG (0x04) /* STOP Condition interrupt Flag */ +#define UCSTTIFG (0x02) /* START Condition interrupt Flag */ +#define UCALIFG (0x01) /* Arbitration Lost interrupt Flag */ + +#define UCIRTXPL5 (0x80) /* IRDA Transmit Pulse Length 5 */ +#define UCIRTXPL4 (0x40) /* IRDA Transmit Pulse Length 4 */ +#define UCIRTXPL3 (0x20) /* IRDA Transmit Pulse Length 3 */ +#define UCIRTXPL2 (0x10) /* IRDA Transmit Pulse Length 2 */ +#define UCIRTXPL1 (0x08) /* IRDA Transmit Pulse Length 1 */ +#define UCIRTXPL0 (0x04) /* IRDA Transmit Pulse Length 0 */ +#define UCIRTXCLK (0x02) /* IRDA Transmit Pulse Clock Select */ +#define UCIREN (0x01) /* IRDA Encoder/Decoder enable */ + +#define UCIRRXFL5 (0x80) /* IRDA Receive Filter Length 5 */ +#define UCIRRXFL4 (0x40) /* IRDA Receive Filter Length 4 */ +#define UCIRRXFL3 (0x20) /* IRDA Receive Filter Length 3 */ +#define UCIRRXFL2 (0x10) /* IRDA Receive Filter Length 2 */ +#define UCIRRXFL1 (0x08) /* IRDA Receive Filter Length 1 */ +#define UCIRRXFL0 (0x04) /* IRDA Receive Filter Length 0 */ +#define UCIRRXPL (0x02) /* IRDA Receive Input Polarity */ +#define UCIRRXFE (0x01) /* IRDA Receive Filter enable */ + +//#define res (0x80) /* reserved */ +//#define res (0x40) /* reserved */ +#define UCDELIM1 (0x20) /* Break Sync Delimiter 1 */ +#define UCDELIM0 (0x10) /* Break Sync Delimiter 0 */ +#define UCSTOE (0x08) /* Sync-Field Timeout error */ +#define UCBTOE (0x04) /* Break Timeout error */ +//#define res (0x02) /* reserved */ +#define UCABDEN (0x01) /* Auto Baud Rate detect enable */ + +#define UCGCEN (0x8000) /* I2C General Call enable */ +#define UCOA9 (0x0200) /* I2C Own Address 9 */ +#define UCOA8 (0x0100) /* I2C Own Address 8 */ +#define UCOA7 (0x0080) /* I2C Own Address 7 */ +#define UCOA6 (0x0040) /* I2C Own Address 6 */ +#define UCOA5 (0x0020) /* I2C Own Address 5 */ +#define UCOA4 (0x0010) /* I2C Own Address 4 */ +#define UCOA3 (0x0008) /* I2C Own Address 3 */ +#define UCOA2 (0x0004) /* I2C Own Address 2 */ +#define UCOA1 (0x0002) /* I2C Own Address 1 */ +#define UCOA0 (0x0001) /* I2C Own Address 0 */ + +#define UCSA9 (0x0200) /* I2C Slave Address 9 */ +#define UCSA8 (0x0100) /* I2C Slave Address 8 */ +#define UCSA7 (0x0080) /* I2C Slave Address 7 */ +#define UCSA6 (0x0040) /* I2C Slave Address 6 */ +#define UCSA5 (0x0020) /* I2C Slave Address 5 */ +#define UCSA4 (0x0010) /* I2C Slave Address 4 */ +#define UCSA3 (0x0008) /* I2C Slave Address 3 */ +#define UCSA2 (0x0004) /* I2C Slave Address 2 */ +#define UCSA1 (0x0002) /* I2C Slave Address 1 */ +#define UCSA0 (0x0001) /* I2C Slave Address 0 */ + +/************************************************************ +* WATCHDOG TIMER +************************************************************/ +#define __MSP430_HAS_WDT__ /* Definition to show that Module is available */ + +#define WDTCTL 0x0120 /* Watchdog Timer Control */ +/* The bit names have been prefixed with "WDT" */ +#define WDTIS0 (0x0001) +#define WDTIS1 (0x0002) +#define WDTSSEL (0x0004) +#define WDTCNTCL (0x0008) +#define WDTTMSEL (0x0010) +#define WDTNMI (0x0020) +#define WDTNMIES (0x0040) +#define WDTHOLD (0x0080) + +#define WDTPW (0x5A00) + +/* WDT-interval times [1ms] coded with Bits 0-2 */ +/* WDT is clocked by fSMCLK (assumed 1MHz) */ +#define WDT_MDLY_32 (WDTPW+WDTTMSEL+WDTCNTCL) /* 32ms interval (default) */ +#define WDT_MDLY_8 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS0) /* 8ms " */ +#define WDT_MDLY_0_5 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS1) /* 0.5ms " */ +#define WDT_MDLY_0_064 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS1+WDTIS0) /* 0.064ms " */ +/* WDT is clocked by fACLK (assumed 32KHz) */ +#define WDT_ADLY_1000 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL) /* 1000ms " */ +#define WDT_ADLY_250 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS0) /* 250ms " */ +#define WDT_ADLY_16 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS1) /* 16ms " */ +#define WDT_ADLY_1_9 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS1+WDTIS0) /* 1.9ms " */ +/* Watchdog mode -> reset after expired time */ +/* WDT is clocked by fSMCLK (assumed 1MHz) */ +#define WDT_MRST_32 (WDTPW+WDTCNTCL) /* 32ms interval (default) */ +#define WDT_MRST_8 (WDTPW+WDTCNTCL+WDTIS0) /* 8ms " */ +#define WDT_MRST_0_5 (WDTPW+WDTCNTCL+WDTIS1) /* 0.5ms " */ +#define WDT_MRST_0_064 (WDTPW+WDTCNTCL+WDTIS1+WDTIS0) /* 0.064ms " */ +/* WDT is clocked by fACLK (assumed 32KHz) */ +#define WDT_ARST_1000 (WDTPW+WDTCNTCL+WDTSSEL) /* 1000ms " */ +#define WDT_ARST_250 (WDTPW+WDTCNTCL+WDTSSEL+WDTIS0) /* 250ms " */ +#define WDT_ARST_16 (WDTPW+WDTCNTCL+WDTSSEL+WDTIS1) /* 16ms " */ +#define WDT_ARST_1_9 (WDTPW+WDTCNTCL+WDTSSEL+WDTIS1+WDTIS0) /* 1.9ms " */ + +/* INTERRUPT CONTROL */ +/* These two bits are defined in the Special Function Registers */ +/* #define WDTIE 0x01 */ +/* #define WDTIFG 0x01 */ + +/************************************************************ +* Calibration Data in Info Mem +************************************************************/ + +#ifndef __DisableCalData + +#define CALDCO_16MHZ 0x10F8 /* DCOCTL Calibration Data for 16MHz */ +#define CALBC1_16MHZ 0x10F9 /* BCSCTL1 Calibration Data for 16MHz */ +#define CALDCO_12MHZ 0x10FA /* DCOCTL Calibration Data for 12MHz */ +#define CALBC1_12MHZ 0x10FB /* BCSCTL1 Calibration Data for 12MHz */ +#define CALDCO_8MHZ 0x10FC /* DCOCTL Calibration Data for 8MHz */ +#define CALBC1_8MHZ 0x10FD /* BCSCTL1 Calibration Data for 8MHz */ +#define CALDCO_1MHZ 0x10FE /* DCOCTL Calibration Data for 1MHz */ +#define CALBC1_1MHZ 0x10FF /* BCSCTL1 Calibration Data for 1MHz */ + +#endif /* #ifndef __DisableCalData */ + + +/************************************************************ +* Interrupt Vectors (offset from 0xFFE0) +************************************************************/ + +#define PORT1_VECTOR (0x0004) /* 0xFFE4 Port 1 */ +#define PORT2_VECTOR (0x0006) /* 0xFFE6 Port 2 */ +#define ADC10_VECTOR (0x000A) /* 0xFFEA ADC10 */ +#define USCIAB0TX_VECTOR (0x000C) /* 0xFFEC USCI A0/B0 Transmit */ +#define USCIAB0RX_VECTOR (0x000E) /* 0xFFEE USCI A0/B0 Receive */ +#define TIMER0_A1_VECTOR (0x0010) /* 0xFFF0 Timer0)A CC1, TA0 */ +#define TIMER0_A0_VECTOR (0x0012) /* 0xFFF2 Timer0_A CC0 */ +#define WDT_VECTOR (0x0014) /* 0xFFF4 Watchdog Timer */ +#define COMPARATORA_VECTOR (0x0016) /* 0xFFF6 Comparator A */ +#define TIMER1_A1_VECTOR (0x0018) /* 0xFFF8 Timer1_A CC1-4, TA1 */ +#define TIMER1_A0_VECTOR (0x001A) /* 0xFFFA Timer1_A CC0 */ +#define NMI_VECTOR (0x001C) /* 0xFFFC Non-maskable */ +#define RESET_VECTOR (0x001E) /* 0xFFFE Reset [Highest Priority] */ + +/************************************************************ +* End of Modules +************************************************************/ diff --git a/amforth-6.5/msp430/devices/msp430g2553/words/cold.asm b/amforth-6.5/msp430/devices/msp430g2553/words/cold.asm new file mode 100644 index 0000000..0828eb4 --- /dev/null +++ b/amforth-6.5/msp430/devices/msp430g2553/words/cold.asm @@ -0,0 +1,41 @@ +CODEHEADER(XT_COLD,4,"cold") +main: ; Debugger requires the 'main' symbol. +reset: + ; Watchdog Timer + MOV #(WDTPW+WDTHOLD),&WDTCTL ; stop watchdog timer + + ; Basic Clock Module + ; My thanks to the 4e4th team for the following two lines! + MOV.B &CALBC1_8MHZ, &BCSCTL1 ; Set DCO + MOV.B &CALDCO_8MHZ, &DCOCTL ; to 8 MHz. + + MOV.B #00h,&BCSCTL2 ; MCLK=DCO/1, SMCLK=DCO/1 + + ; Flash Memory Controller + ; Flash Timing Generator frequency must be 257-476 kHz. + ; 8 MHZ/17 = 470.59 kHz. tFTG=2.125 msec. + ; At 470 kHz, byte/word program time is 35*tFTG = 75 usec. + ; Cumulative program time to any 64-byte block (between erasures) + ; must not exceed 4 msec, thus 53 writes at 250 kHz. Therefore, + ; do not use exclusively byte writes in a 64-byte block. + ; Also, "a flash word (low + high byte) must not + ; be written more than twice between erasures." + ; Program/Erase endurance is 10,000 cycles minimum. + MOV #FWKEY+0,&FCTL1 ; write & erase modes OFF + MOV #FWKEY+FSSEL1+16,&FCTL2 ; SMCLK/17 = 471 kHz. + MOV #FWKEY+LOCK,&FCTL3 ; lock flash memory against writing + + ; Interrupt Enables + MOV.B #0,&IE1 ; no interrupts enabled + MOV.B #0,&IE2 ; no interrupts enabled + + ; Forth registers + MOV #RSTACK,SP ; set up stack + MOV #PSTACK,PSP + MOV #UAREA,UP ; initial user pointer + + CLR R15 + + ; now hand over to Forth with WARM (a colon word) + MOV #XT_WARM+2,IP + NEXT diff --git a/amforth-6.5/msp430/devices/msp430g2553/words/env-mcu-info.asm b/amforth-6.5/msp430/devices/msp430g2553/words/env-mcu-info.asm new file mode 100644 index 0000000..621fc72 --- /dev/null +++ b/amforth-6.5/msp430/devices/msp430g2553/words/env-mcu-info.asm @@ -0,0 +1,10 @@ +ENVIRONMENT(XT_ENV_MCU_INFO,8,"mcu-info") + .DW XT_DOLITERAL + .dw mcuinfo + .DW XT_EXIT +mcuinfo: + ; first fixed sized elements + .dw RAMEND-RAMSTART ; RAM Size + .dw 0 ; EEPROM Size + .dw AMFORTH_START-1 ; max-dp + .dw 1 ; number of interrupts diff --git a/amforth-6.5/msp430/devices/msp430g2553/words/usart-init.asm b/amforth-6.5/msp430/devices/msp430g2553/words/usart-init.asm new file mode 100644 index 0000000..e8c7693 --- /dev/null +++ b/amforth-6.5/msp430/devices/msp430g2553/words/usart-init.asm @@ -0,0 +1,13 @@ + CODEHEADER(XT_USART,6,"+usart") + ; USCI_A0 + MOV.B #06,&P1SEL ; P1.1,2 are UART + MOV.B #06,&P1SEL2 ; P1.1,2 are UART + + BIS.B #UCSWRST,&UCA0CTL1 ; SWRST while configuring! + MOV.B #00h,&UCA0CTL0 ; UART, 8N1, LSB first + MOV.B #81h,&UCA0CTL1 ; BRCLK = SMCLK, SWRST set + MOV.B #41h,&UCA0BR0 ; 9600 Baud at 8 MHz + MOV.B #03h,&UCA0BR1 + MOV.B #04h,&UCA0MCTL ; UCBRFx=0, UCBRSx=2 for 9600 baud + BIC.B #UCSWRST,&UCA0CTL1 ; done configuring + NEXT -- cgit v1.2.3