# Partname: ATmega8515 # generated automatically, do not edit MCUREGS = { 'ACSR': '&40', 'ACSR_ACD': '$80', 'ACSR_ACBG': '$40', 'ACSR_ACO': '$20', 'ACSR_ACI': '$10', 'ACSR_ACIE': '$08', 'ACSR_ACIC': '$04', 'ACSR_ACIS': '$03', 'UDR': '&44', 'UCSRA': '&43', 'UCSRA_RXC': '$80', 'UCSRA_TXC': '$40', 'UCSRA_UDRE': '$20', 'UCSRA_FE': '$10', 'UCSRA_DOR': '$08', 'UCSRA_UPE': '$04', 'UCSRA_U2X': '$02', 'UCSRA_MPCM': '$01', 'UCSRB': '&42', 'UCSRB_RXCIE': '$80', 'UCSRB_TXCIE': '$40', 'UCSRB_UDRIE': '$20', 'UCSRB_RXEN': '$10', 'UCSRB_TXEN': '$08', 'UCSRB_UCSZ2': '$04', 'UCSRB_RXB8': '$02', 'UCSRB_TXB8': '$01', 'UCSRC': '&64', 'UCSRC_URSEL': '$80', 'UCSRC_UMSEL': '$40', 'UCSRC_UPM': '$30', 'UCSRC_USBS': '$08', 'UCSRC_UCSZ': '$06', 'UCSRC_UCPOL': '$01', 'UBRRH': '&64', 'UBRRH_URSEL': '$80', 'UBRRH_UBRR1': '$0C', 'UBRRH_UBRR': '$03', 'UBRRL': '&41', 'SPDR': '&47', 'SPSR': '&46', 'SPSR_SPIF': '$80', 'SPSR_WCOL': '$40', 'SPSR_SPI2X': '$01', 'SPCR': '&45', 'SPCR_SPIE': '$80', 'SPCR_SPE': '$40', 'SPCR_DORD': '$20', 'SPCR_MSTR': '$10', 'SPCR_CPOL': '$08', 'SPCR_CPHA': '$04', 'SPCR_SPR': '$03', 'SREG': '&95', 'SREG_I': '$80', 'SREG_T': '$40', 'SREG_H': '$20', 'SREG_S': '$10', 'SREG_V': '$08', 'SREG_N': '$04', 'SREG_Z': '$02', 'SREG_C': '$01', 'SP': '&93', 'EMCUCR': '&86', 'EMCUCR_SM0': '$80', 'EMCUCR_SRL': '$70', 'EMCUCR_SRW0': '$0C', 'EMCUCR_SRW11': '$02', 'EMCUCR_ISC2': '$01', 'MCUCR': '&85', 'MCUCR_SRE': '$80', 'MCUCR_SRW10': '$40', 'MCUCR_SE': '$20', 'MCUCR_SM1': '$10', 'MCUCR_ISC1': '$0C', 'MCUCR_ISC0': '$03', 'MCUCSR': '&84', 'MCUCSR_SM2': '$20', 'MCUCSR_WDRF': '$08', 'MCUCSR_BORF': '$04', 'MCUCSR_EXTRF': '$02', 'MCUCSR_PORF': '$01', 'OSCCAL': '&36', 'SPMCR': '&87', 'SPMCR_SPMIE': '$80', 'SPMCR_RWWSB': '$40', 'SPMCR_RWWSRE': '$10', 'SPMCR_BLBSET': '$08', 'SPMCR_PGWRT': '$04', 'SPMCR_PGERS': '$02', 'SPMCR_SPMEN': '$01', 'SFIOR': '&80', 'SFIOR_XMBK': '$40', 'SFIOR_XMM': '$38', 'SFIOR_PUD': '$04', 'SFIOR_PSR10': '$01', 'GICR': '&91', 'GICR_INT': '$C0', 'GICR_INT2': '$20', 'GICR_IVSEL': '$02', 'GICR_IVCE': '$01', 'GIFR': '&90', 'GIFR_INTF': '$C0', 'GIFR_INTF2': '$20', 'WDTCR': '&65', 'WDTCR_WDCE': '$10', 'WDTCR_WDE': '$08', 'WDTCR_WDP': '$07', 'TCCR0': '&83', 'TCCR0_FOC0': '$80', 'TCCR0_WGM00': '$40', 'TCCR0_COM0': '$30', 'TCCR0_WGM01': '$08', 'TCCR0_CS0': '$07', 'TCNT0': '&82', 'OCR0': '&81', 'TIMSK': '&89', 'TIMSK_TOIE0': '$02', 'TIMSK_OCIE0': '$01', 'TIFR': '&88', 'TIFR_TOV0': '$02', 'TIFR_OCF0': '$01', 'TCCR1A': '&79', 'TCCR1A_COM1A': '$C0', 'TCCR1A_COM1B': '$30', 'TCCR1A_FOC1A': '$08', 'TCCR1A_FOC1B': '$04', 'TCCR1A_WGM1': '$03', 'TCCR1B': '&78', 'TCCR1B_ICNC1': '$80', 'TCCR1B_ICES1': '$40', 'TCCR1B_WGM1': '$18', 'TCCR1B_CS1': '$07', 'TCNT1': '&76', 'OCR1A': '&74', 'OCR1B': '&72', 'ICR1': '&68', 'PORTA': '&59', 'DDRA': '&58', 'PINA': '&57', 'PORTB': '&56', 'DDRB': '&55', 'PINB': '&54', 'PORTC': '&53', 'DDRC': '&52', 'PINC': '&51', 'PORTD': '&50', 'DDRD': '&49', 'PIND': '&48', 'PORTE': '&39', 'DDRE': '&38', 'PINE': '&37', 'EEAR': '&62', 'EEDR': '&61', 'EECR': '&60', 'EECR_EERIE': '$08', 'EECR_EEMWE': '$04', 'EECR_EEWE': '$02', 'EECR_EERE': '$01', 'INT0Addr': '1', 'INT1Addr': '2', 'TIMER1_CAPTAddr': '3', 'TIMER1_COMPAAddr': '4', 'TIMER1_COMPBAddr': '5', 'TIMER1_OVFAddr': '6', 'TIMER0_OVFAddr': '7', 'SPI_STCAddr': '8', 'USART_RXAddr': '9', 'USART_UDREAddr': '10', 'USART__TXAddr': '11', 'ANA_COMPAddr': '12', 'INT2Addr': '13', 'TIMER0_COMPAddr': '14', 'EE_RDYAddr': '15', 'SPM_RDYAddr': '16' }