From cf01b391440fc9de43597b907acfc22dba1aa15e Mon Sep 17 00:00:00 2001 From: Dimitri Sokolyuk Date: Sun, 18 Jun 2017 14:38:03 +0200 Subject: Add j1 --- j1 | 1 - j1/verilog/stack.v | 22 ++++++++++++++++++++++ 2 files changed, 22 insertions(+), 1 deletion(-) delete mode 160000 j1 create mode 100644 j1/verilog/stack.v (limited to 'j1/verilog/stack.v') diff --git a/j1 b/j1 deleted file mode 160000 index 9114396..0000000 --- a/j1 +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 911439641c002a8f7a6e306ce1b1d3fd4b389fd6 diff --git a/j1/verilog/stack.v b/j1/verilog/stack.v new file mode 100644 index 0000000..e5cee8a --- /dev/null +++ b/j1/verilog/stack.v @@ -0,0 +1,22 @@ +`include "common.h" + +module stack + #(parameter DEPTH=4) + (input wire clk, + /* verilator lint_off UNUSED */ + input wire resetq, + /* verilator lint_on UNUSED */ + input wire [DEPTH-1:0] ra, + output wire [`WIDTH-1:0] rd, + input wire we, + input wire [DEPTH-1:0] wa, + input wire [`WIDTH-1:0] wd); + + reg [`WIDTH-1:0] store[0:(2**DEPTH)-1]; + + always @(posedge clk) + if (we) + store[wa] <= wd; + + assign rd = store[ra]; +endmodule -- cgit v1.2.3