From a76977af62010a392c16010c367185e61e856ffe Mon Sep 17 00:00:00 2001 From: Dimitri Sokolyuk Date: Wed, 30 Oct 2019 20:04:56 +0100 Subject: mv to docs --- j1/verilog/testbench.v | 30 ------------------------------ 1 file changed, 30 deletions(-) delete mode 100644 j1/verilog/testbench.v (limited to 'j1/verilog/testbench.v') diff --git a/j1/verilog/testbench.v b/j1/verilog/testbench.v deleted file mode 100644 index 2ec2b5e..0000000 --- a/j1/verilog/testbench.v +++ /dev/null @@ -1,30 +0,0 @@ -`timescale 1ns/1ps -`default_nettype none - -module testbench(); - - reg clk; - reg resetq; - integer t; - - top #(.FIRMWARE("build/firmware/")) dut(.clk(clk), .resetq(resetq)); - - initial begin - clk = 1; - t = 0; - resetq = 0; - #1; - resetq = 1; - - $dumpfile("test.vcd"); - $dumpvars(0, dut); - end - - always #5.0 clk = ~clk; - - always @(posedge clk) begin - t <= t + 1; - if (t == 300) - $finish; - end -endmodule -- cgit v1.2.3