From cf01b391440fc9de43597b907acfc22dba1aa15e Mon Sep 17 00:00:00 2001 From: Dimitri Sokolyuk Date: Sun, 18 Jun 2017 14:38:03 +0200 Subject: Add j1 --- j1 | 1 - j1/verilog/testbench.v | 30 ++++++++++++++++++++++++++++++ 2 files changed, 30 insertions(+), 1 deletion(-) delete mode 160000 j1 create mode 100644 j1/verilog/testbench.v (limited to 'j1/verilog/testbench.v') diff --git a/j1 b/j1 deleted file mode 160000 index 9114396..0000000 --- a/j1 +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 911439641c002a8f7a6e306ce1b1d3fd4b389fd6 diff --git a/j1/verilog/testbench.v b/j1/verilog/testbench.v new file mode 100644 index 0000000..2ec2b5e --- /dev/null +++ b/j1/verilog/testbench.v @@ -0,0 +1,30 @@ +`timescale 1ns/1ps +`default_nettype none + +module testbench(); + + reg clk; + reg resetq; + integer t; + + top #(.FIRMWARE("build/firmware/")) dut(.clk(clk), .resetq(resetq)); + + initial begin + clk = 1; + t = 0; + resetq = 0; + #1; + resetq = 1; + + $dumpfile("test.vcd"); + $dumpvars(0, dut); + end + + always #5.0 clk = ~clk; + + always @(posedge clk) begin + t <= t + 1; + if (t == 300) + $finish; + end +endmodule -- cgit v1.2.3