From a76977af62010a392c16010c367185e61e856ffe Mon Sep 17 00:00:00 2001 From: Dimitri Sokolyuk Date: Wed, 30 Oct 2019 20:04:56 +0100 Subject: mv to docs --- j1/xilinx/.gitignore | 44 ----------- j1/xilinx/Makefile | 11 --- j1/xilinx/go | 22 ------ j1/xilinx/j1-papilioduo.bmm | 24 ------ j1/xilinx/j1-papilioduo.ucf | 183 -------------------------------------------- j1/xilinx/shell.py | 78 ------------------- j1/xilinx/xilinx.mk | 176 ------------------------------------------ j1/xilinx/xilinx.opt | 42 ---------- 8 files changed, 580 deletions(-) delete mode 100644 j1/xilinx/.gitignore delete mode 100644 j1/xilinx/Makefile delete mode 100644 j1/xilinx/go delete mode 100644 j1/xilinx/j1-papilioduo.bmm delete mode 100644 j1/xilinx/j1-papilioduo.ucf delete mode 100644 j1/xilinx/shell.py delete mode 100644 j1/xilinx/xilinx.mk delete mode 100644 j1/xilinx/xilinx.opt (limited to 'j1/xilinx') diff --git a/j1/xilinx/.gitignore b/j1/xilinx/.gitignore deleted file mode 100644 index e138931..0000000 --- a/j1/xilinx/.gitignore +++ /dev/null @@ -1,44 +0,0 @@ -*.bgn -*.bit -*_bitgen.xwbt -*.bld -*.cfi -*.drc -*.map -*.mcs -*.mrp -*.ncd -*.ngc -*.ngc_xst.xrpt -*.ngd -*_ngdbuild.xrpt -*.ngm -*_par.grf -*_par.ncd -*_par.pad -*_par_pad.csv -*_par_pad.txt -*_par.par -*_par.ptwx -*_par.unroutes -*_par.xpi -*.pcf -*.prj -*.prm -*.psr -*.scr -*.srp -*.xml -*.html -_impactbatch.log -netlist.lst -smartguide.ncd -top.lso -top_map.xrpt -top_par.xrpt -usage_statistics_webtalk.html -webtalk.log -xlnx_auto_0_xdb -_xmsgs -xst -unused/ diff --git a/j1/xilinx/Makefile b/j1/xilinx/Makefile deleted file mode 100644 index 481513b..0000000 --- a/j1/xilinx/Makefile +++ /dev/null @@ -1,11 +0,0 @@ -project = j1-papilioduo -vendor = xilinx -family = spartan3s -part = xc6slx9-2-tqg144 -# part = xc3s200an-4ftg256 -top_module = top -flashsize = 2048 - -vfiles = ../verilog/xilinx-top.v ../verilog/uart.v ../verilog/j1.v ../verilog/stack.v - -include xilinx.mk diff --git a/j1/xilinx/go b/j1/xilinx/go deleted file mode 100644 index c527f4c..0000000 --- a/j1/xilinx/go +++ /dev/null @@ -1,22 +0,0 @@ -set -e -cd ../toolchain -sh go -cd ../xilinx - -$HOME/Downloads/DesignLab-1.0.5/tools/Papilio_Loader/programmer/linux32/papilio-prog -v -f j1-papilioduo.bit -python shell.py -h /dev/ttyUSB2 -i ../build/firmware/nuc.hex ; exit - -make clean -make -if false -then - cp ../build/firmware/nuc.hex ../build/firmware/nuc.mem - data2mem -bm j1-papilioduo_bd.bmm -bd ../build/firmware/nuc.mem -bt j1-papilioduo.bit - trce -v 10 j1-papilioduo.ncd j1-papilioduo.pcf -o j1-papilioduo.twr - DL=j1-papilioduo_rp.bit -else - DL=j1-papilioduo.bit -fi -$HOME/Downloads/DesignLab-1.0.5/tools/Papilio_Loader/programmer/linux32/papilio-prog -v -f $DL -python shell.py -h /dev/ttyUSB2 -i ../build/firmware/nuc.hex ; exit -# miniterm.py /dev/ttyUSB0 115200 diff --git a/j1/xilinx/j1-papilioduo.bmm b/j1/xilinx/j1-papilioduo.bmm deleted file mode 100644 index 3dea0be..0000000 --- a/j1/xilinx/j1-papilioduo.bmm +++ /dev/null @@ -1,24 +0,0 @@ -// BMM LOC annotation file. -// -// Release 14.6 - P.20131013, build 3.0.10 Apr 3, 2013 -// Copyright (c) 1995-2015 Xilinx, Inc. All rights reserved. - - -/////////////////////////////////////////////////////////////////////////////// -// -// Address space 'j1' 0x00000000:0x000007FF (2 KBytes). -// -/////////////////////////////////////////////////////////////////////////////// - -// ADDRESS_SPACE j1 RAMB16 [0xffff0000:0xffff3FFF] -// BUS_BLOCK -// ram/nram/Mram_mem7 RAMB16 [3:0] [0:4095]; -// ram/nram/Mram_mem6 RAMB16 [7:4] [0:4095]; -// ram/nram/Mram_mem5 RAMB16 [11:8] [0:4095]; -// ram/nram/Mram_mem4 RAMB16 [15:12] [0:4095]; -// ram/nram/Mram_mem3 RAMB16 [19:16] [0:4095]; -// ram/nram/Mram_mem2 RAMB16 [23:20] [0:4095]; -// ram/nram/Mram_mem1 RAMB16 [27:24] [0:4095]; -// ram/nram/Mram_mem0 RAMB16 [31:28] [0:4095]; -// END_BUS_BLOCK; -// END_ADDRESS_SPACE; diff --git a/j1/xilinx/j1-papilioduo.ucf b/j1/xilinx/j1-papilioduo.ucf deleted file mode 100644 index e06e002..0000000 --- a/j1/xilinx/j1-papilioduo.ucf +++ /dev/null @@ -1,183 +0,0 @@ -# UCF file for the Papilio DUO board -# Generated by pin_converter, written by Kevin Lindsey -# https://github.com/thelonious/papilio_pins/tree/development/pin_converter - -# Main board wing pin [] to FPGA pin Pxx map -# -------C------- -------B------- -------A------- -# [GND] [C00] P114 [GND] [B00] P99 P100 [A15] -# [2V5] [C01] P115 [2V5] [B01] P97 P98 [A14] -# [3V3] [C02] P116 [3V3] [B02] P92 P93 [A13] -# [5V0] [C03] P117 [5V0] [B03] P87 P88 [A12] -# [C04] P118 [B04] P84 P85 [A11] [5V0] -# [C05] P119 [B05] P82 P83 [A10] [3V3] -# [C06] P120 [B06] P80 P81 [A09] [2V5] -# [C07] P121 [B07] P78 P79 [A08] [GND] -# [GND] [C08] P123 [GND] [B08] P74 P75 [A07] -# [2V5] [C09] P124 [2V5] [B09] P95 P67 [A06] -# [3V3] [C10] P126 [3V3] [B10] P62 P66 [A05] -# [5V0] [C11] P127 [5V0] [B11] P59 P61 [A04] -# [C12] P131 [B12] P57 P58 [A03] [5V0] -# [C13] P132 [B13] P55 P56 [A02] [3V3] -# [C14] P133 [B14] P50 P51 [A01] [2V5] -# [C15] P134 [B15] P47 P48 [A00] [GND] - -## Prohibit the automatic placement of pins that are connected to VCC or GND for configuration. -CONFIG PROHIBIT=P144; -CONFIG PROHIBIT=P69; -CONFIG PROHIBIT=P60; - -#NET "*" IOSTANDARD = LVTTL; - -NET CLK LOC="P94" | IOSTANDARD=LVTTL; # CLK -TIMESPEC TS_Period_1 = PERIOD "CLK" 31.25 ns HIGH 50%; -NET TXD LOC="P141" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; -NET RXD LOC="P46" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; -NET DTR LOC="P137" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=SLOW; - -// NET "fclk" PERIOD = 6 ns HIGH 50%; - -# -# NET Arduino_0 LOC="P116" | IOSTANDARD=LVTTL; # A0 -# NET Arduino_1 LOC="P117" | IOSTANDARD=LVTTL; # A1 -# NET Arduino_2 LOC="P118" | IOSTANDARD=LVTTL; # A2 -# NET Arduino_3 LOC="P119" | IOSTANDARD=LVTTL; # A3 -# NET Arduino_4 LOC="P120" | IOSTANDARD=LVTTL; # A4 -# NET Arduino_5 LOC="P121" | IOSTANDARD=LVTTL; # A5 -# NET Arduino_6 LOC="P123" | IOSTANDARD=LVTTL; # A6 -# NET Arduino_7 LOC="P124" | IOSTANDARD=LVTTL; # A7 -# NET Arduino_8 LOC="P126" | IOSTANDARD=LVTTL; # A8 -# NET Arduino_9 LOC="P127" | IOSTANDARD=LVTTL; # A9 -# NET Arduino_10 LOC="P131" | IOSTANDARD=LVTTL; # A10 -# NET Arduino_11 LOC="P132" | IOSTANDARD=LVTTL; # A11 -# NET Arduino_12 LOC="P133" | IOSTANDARD=LVTTL; # A12 -# NET Arduino_13 LOC="P134" | IOSTANDARD=LVTTL; # A13 -# -# NET Arduino_14 LOC="P115" | IOSTANDARD=LVTTL; # B0 -# NET Arduino_15 LOC="P114" | IOSTANDARD=LVTTL; # B1 -# NET Arduino_16 LOC="P112" | IOSTANDARD=LVTTL; # B2 -# NET Arduino_17 LOC="P111" | IOSTANDARD=LVTTL; # B3 -# NET Arduino_18 LOC="P105" | IOSTANDARD=LVTTL; # B4 -# NET Arduino_19 LOC="P102" | IOSTANDARD=LVTTL; # B5 -# NET Arduino_20 LOC="P101" | IOSTANDARD=LVTTL; # B6 -# NET Arduino_21 LOC="P100" | IOSTANDARD=LVTTL; # B7 -# -# NET Arduino_22 LOC="P99" | IOSTANDARD=LVTTL; # C0 -# NET Arduino_24 LOC="P97" | IOSTANDARD=LVTTL; # C1 -# NET Arduino_26 LOC="P93" | IOSTANDARD=LVTTL; # C2 -# NET Arduino_28 LOC="P88" | IOSTANDARD=LVTTL; # C3 -# NET Arduino_30 LOC="P85" | IOSTANDARD=LVTTL; # C4 -# NET Arduino_32 LOC="P83" | IOSTANDARD=LVTTL; # C5 -# NET Arduino_34 LOC="P81" | IOSTANDARD=LVTTL; # C6 -# NET Arduino_36 LOC="P79" | IOSTANDARD=LVTTL; # C7 -# NET Arduino_38 LOC="P75" | IOSTANDARD=LVTTL; # C8 -# NET Arduino_40 LOC="P67" | IOSTANDARD=LVTTL; # C9 -# NET Arduino_42 LOC="P62" | IOSTANDARD=LVTTL; # C10 -# NET Arduino_44 LOC="P59" | IOSTANDARD=LVTTL; # C11 -# NET Arduino_46 LOC="P57" | IOSTANDARD=LVTTL; # C12 -# NET Arduino_48 LOC="P55" | IOSTANDARD=LVTTL; # C13 -# NET Arduino_50 LOC="P50" | IOSTANDARD=LVTTL; # C14 -# NET Arduino_52 LOC="P47" | IOSTANDARD=LVTTL; # C15 -# -# NET Arduino_23 LOC="P98" | IOSTANDARD=LVTTL ; -# NET Arduino_25 LOC="P95" | IOSTANDARD=LVTTL ; -# NET Arduino_27 LOC="P92" | IOSTANDARD=LVTTL ; -# NET Arduino_29 LOC="P87" | IOSTANDARD=LVTTL ; -# NET Arduino_31 LOC="P84" | IOSTANDARD=LVTTL ; -# NET Arduino_33 LOC="P82" | IOSTANDARD=LVTTL ; -# NET Arduino_35 LOC="P80" | IOSTANDARD=LVTTL ; -# NET Arduino_37 LOC="P78" | IOSTANDARD=LVTTL ; -# NET Arduino_39 LOC="P74" | IOSTANDARD=LVTTL ; -# NET Arduino_41 LOC="P66" | IOSTANDARD=LVTTL ; -# NET Arduino_43 LOC="P61" | IOSTANDARD=LVTTL ; -# NET Arduino_45 LOC="P58" | IOSTANDARD=LVTTL ; -# NET Arduino_47 LOC="P56" | IOSTANDARD=LVTTL ; -# NET Arduino_49 LOC="P51" | IOSTANDARD=LVTTL ; -# NET Arduino_51 LOC="P48" | IOSTANDARD=LVTTL ; -# NET Arduino_53 LOC="P39" | IOSTANDARD=LVTTL ; -# -# # SRAM -# -# NET "sram_addr<0>" LOC = "P7" | IOSTANDARD=LVTTL | SLEW=FAST; -# NET "sram_addr<1>" LOC = "P8" | IOSTANDARD=LVTTL | SLEW=FAST ; -# NET "sram_addr<2>" LOC = "P9" | IOSTANDARD=LVTTL | SLEW=FAST ; -# NET "sram_addr<3>" LOC = "P10" | IOSTANDARD=LVTTL | SLEW=FAST ; -# NET "sram_addr<4>" LOC = "P11" | IOSTANDARD=LVTTL | SLEW=FAST ; -# NET "sram_addr<5>" LOC = "P5" | IOSTANDARD=LVTTL | SLEW=FAST ; -# NET "sram_addr<6>" LOC = "P2" | IOSTANDARD=LVTTL | SLEW=FAST ; -# NET "sram_addr<7>" LOC = "P1" | IOSTANDARD=LVTTL | SLEW=FAST ; -# NET "sram_addr<8>" LOC = "P143" | IOSTANDARD=LVTTL | SLEW=FAST ; -# NET "sram_addr<9>" LOC = "P142" | IOSTANDARD=LVTTL | SLEW=FAST ; -# NET "sram_addr<10>" LOC = "P43" | IOSTANDARD=LVTTL | SLEW=FAST ; -# NET "sram_addr<11>" LOC = "P41" | IOSTANDARD=LVTTL | SLEW=FAST ; -# NET "sram_addr<12>" LOC = "P40" | IOSTANDARD=LVTTL | SLEW=FAST; -# NET "sram_addr<13>" LOC = "P35" | IOSTANDARD=LVTTL | SLEW=FAST ; -# NET "sram_addr<14>" LOC = "P34" | IOSTANDARD=LVTTL | SLEW=FAST ; -# NET "sram_addr<15>" LOC = "P27" | IOSTANDARD=LVTTL | SLEW=FAST ; -# NET "sram_addr<16>" LOC = "P29" | IOSTANDARD=LVTTL | SLEW=FAST ; -# NET "sram_addr<17>" LOC = "P33" | IOSTANDARD=LVTTL | SLEW=FAST ; -# NET "sram_addr<18>" LOC = "P32" | IOSTANDARD=LVTTL | SLEW=FAST ; -# #NET "sram_addr<19>" LOC = "P44" | IOSTANDARD=LVTTL | SLEW=FAST ; -# #NET "sram_addr<20>" LOC = "P30" | IOSTANDARD=LVTTL | SLEW=FAST ; -# -# # Data lines -# NET "sram_data<0>" LOC = "P14" | IOSTANDARD=LVTTL | SLEW=FAST ; -# NET "sram_data<1>" LOC = "P15" | IOSTANDARD=LVTTL | SLEW=FAST ; -# NET "sram_data<2>" LOC = "P16" | IOSTANDARD=LVTTL | SLEW=FAST ; -# NET "sram_data<3>" LOC = "P17" | IOSTANDARD=LVTTL | SLEW=FAST ; -# NET "sram_data<4>" LOC = "P21" | IOSTANDARD=LVTTL | SLEW=FAST ; -# NET "sram_data<5>" LOC = "P22" | IOSTANDARD=LVTTL | SLEW=FAST ; -# NET "sram_data<6>" LOC = "P23" | IOSTANDARD=LVTTL | SLEW=FAST ; -# NET "sram_data<7>" LOC = "P24" | IOSTANDARD=LVTTL | SLEW=FAST ; -# -# # Control lines -# NET "sram_ce" LOC = "P12" | IOSTANDARD=LVTTL | SLEW=FAST; -# NET "sram_we" LOC = "P6" | IOSTANDARD=LVTTL | SLEW=FAST ; -# NET "sram_oe" LOC = "P26" | IOSTANDARD=LVTTL | SLEW=FAST; -# -# NET SPI_CS LOC="P38" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # FLASH_CS OK -# NET SPI_SCK LOC="P70" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # FLASH_CK OK -# NET SPI_MOSI LOC="P64" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # FLASH_SI OK -# NET SPI_MISO LOC="P65" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # FLASH_SO OK -# -# #Dragon MPSSE -# NET BD0_MPSSE_TCK LOC="P46" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=SLOW; -# NET BD1_MPSSE_TDI LOC="P141" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=SLOW; -# NET BD2_MPSSE_TDO LOC="P140" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=SLOW; -# NET BD3_MPSSE_TMS LOC="P138" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=SLOW; -# NET BD4_MPSSE_DTR LOC="P137" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=SLOW; -# -# #Arduino JTAG -# NET ARD_JTAG_TDI LOC="P88" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=SLOW; -# NET ARD_JTAG_TDO LOC="P85" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=SLOW; -# NET ARD_JTAG_TMS LOC="P83" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=SLOW; -# NET ARD_JTAG_TCK LOC="P81" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=SLOW; -# -# #Arduino SPI -# NET ARD_SPI_MISO LOC="P133" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=SLOW; -# NET ARD_SPI_MOSI LOC="P132" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=SLOW; -# NET ARD_SPI_SCLK LOC="P134" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=SLOW; -# -# #Dragon SPI -# NET DRAGON_SPI_GND LOC="P78" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=SLOW; -# NET DRAGON_SPI_RESET LOC="P79" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=SLOW; -# #NET DRAGON_SPI_RESET LOC="P79" | IOSTANDARD=LVTTL | DRIVE=8 | PULLUP | SLEW=SLOW; -# NET DRAGON_SPI_MOSI LOC="P74" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=SLOW; -# NET DRAGON_SPI_SCK LOC="P75" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=SLOW; -# NET DRAGON_SPI_VTG LOC="P66" | IOSTANDARD=LVTTL | DRIVE=24 | SLEW=SLOW; -# NET DRAGON_SPI_MISO LOC="P67" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=SLOW; -# -# #Dragon JTAG -# NET DRAGON_JTAG_TCK LOC="P47" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=SLOW; -# NET DRAGON_JTAG_GND LOC="P39" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=SLOW; -# NET DRAGON_JTAG_TDO LOC="P50" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=SLOW; -# NET DRAGON_JTAG_VTG LOC="P48" | IOSTANDARD=LVTTL | DRIVE=24 | SLEW=SLOW; -# NET DRAGON_JTAG_TMS LOC="P55" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=SLOW; -# NET DRAGON_JTAG_RESET LOC="P51" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=SLOW; -# #NET DRAGON_JTAG_RESET LOC="P51" | IOSTANDARD=LVTTL | DRIVE=8 | PULLUP | SLEW=SLOW; -# NET DRAGON_JTAG_TDI LOC="P59" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=SLOW; -# NET DRAGON_JTAG_GND2 LOC="P58" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=SLOW; -# -# #Dragon Misc -NET DUO_SW1 LOC="P104" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=SLOW; -# NET ARD_RESET LOC="P139" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=SLOW; # ARD_RESET -NET DUO_LED LOC="P134" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=SLOW; diff --git a/j1/xilinx/shell.py b/j1/xilinx/shell.py deleted file mode 100644 index 814e6a2..0000000 --- a/j1/xilinx/shell.py +++ /dev/null @@ -1,78 +0,0 @@ -#!/usr/bin/env python - -import sys -from datetime import datetime -import time -import array -import struct -import os - -try: - import serial -except: - print "This tool needs PySerial, but it was not found" - sys.exit(1) - -import swapforth as sf - -class TetheredJ1b(sf.TetheredFT900): - def __init__(self, port): - ser = serial.Serial(port, 115200, timeout=None, rtscts=0) - self.ser = ser - self.searchpath = ['.'] - self.log = open("log", "w") - - def boot(self, bootfile = None): - ser = self.ser - ser.setDTR(1) - ser.setDTR(0) - boot = array.array('I', [int(l, 16) for l in open(bootfile)]) - boot = boot[:0x3f80 / 4] # remove bootloader itself (top 128 bytes) - while boot[-1] == 0: # remove any unused words - boot = boot[:-1] - boot = boot.tostring() - ser.write(chr(27)) - print 'wrote 27' - # print repr(ser.read(1)) - - ser.write(struct.pack('I', len(boot))) - ser.write(boot) - print 'completed load of %d bytes' % len(boot) - # print repr(ser.read(1)) - -if __name__ == '__main__': - port = '/dev/ttyUSB0' - image = None - - r = None - - args = sys.argv[1:] - while args: - a = args[0] - if a.startswith('-i'): - image = args[1] - args = args[2:] - elif a.startswith('-h'): - port = args[1] - args = args[2:] - else: - if not r: - r = TetheredJ1b(port) - r.boot(image) - if a.startswith('-e'): - print r.shellcmd(args[1]) - args = args[2:] - else: - try: - r.include(a) - except sf.Bye: - pass - args = args[1:] - if not r: - r = TetheredJ1b(port) - r.boot(image) - - print repr(r.ser.read(1)) - # r.interactive_command(None) - r.shell(False) - # r.listen() diff --git a/j1/xilinx/xilinx.mk b/j1/xilinx/xilinx.mk deleted file mode 100644 index f71dede..0000000 --- a/j1/xilinx/xilinx.mk +++ /dev/null @@ -1,176 +0,0 @@ -# The top level module should define the variables below then include -# this file. The files listed should be in the same directory as the -# Makefile. -# -# variable description -# ---------- ------------- -# project project name (top level module should match this name) -# top_module top level module of the project -# libdir path to library directory -# libs library modules used -# vfiles all local .v files -# xilinx_cores all local .xco files -# vendor vendor of FPGA (xilinx, altera, etc.) -# family FPGA device family (spartan3e) -# part FPGA part name (xc4vfx12-10-sf363) -# flashsize size of flash for mcs file (16384) -# optfile (optional) xst extra opttions file to put in .scr -# map_opts (optional) options to give to map -# par_opts (optional) options to give to par -# intstyle (optional) intstyle option to all tools -# -# files description -# ---------- ------------ -# $(project).ucf ucf file -# -# Library modules should have a modules.mk in their root directory, -# namely $(libdir)//module.mk, that simply adds to the vfiles -# and xilinx_cores variable. -# -# all the .xco files listed in xilinx_cores will be generated with core, with -# the resulting .v and .ngc files placed back in the same directory as -# the .xco file. -# -# TODO: .xco files are device dependant, should use a template based system - -coregen_work_dir ?= ./coregen-tmp -map_opts ?= -timing -ol high -detail -pr b -register_duplication -w -par_opts ?= -ol high -isedir ?= /data/Xilinx/14.7/ISE_DS -xil_env ?= . $(isedir)/settings64.sh -flashsize ?= 8192 - -libmks = $(patsubst %,$(libdir)/%/module.mk,$(libs)) -mkfiles = Makefile $(libmks) xilinx.mk -include $(libmks) - -corengcs = $(foreach core,$(xilinx_cores),$(core:.xco=.ngc)) -local_corengcs = $(foreach ngc,$(corengcs),$(notdir $(ngc))) -vfiles += $(foreach core,$(xilinx_cores),$(core:.xco=.v)) -junk += $(local_corengcs) - -.PHONY: default xilinx_cores clean twr etwr -default: $(project).bit $(project).mcs -xilinx_cores: $(corengcs) -twr: $(project).twr -etwr: $(project)_err.twr - -define cp_template -$(2): $(1) - cp $(1) $(2) -endef -$(foreach ngc,$(corengcs),$(eval $(call cp_template,$(ngc),$(notdir $(ngc))))) - -%.ngc %.v: %.xco - @echo "=== rebuilding $@" - if [ -d $(coregen_work_dir) ]; then \ - rm -rf $(coregen_work_dir)/*; \ - else \ - mkdir -p $(coregen_work_dir); \ - fi - cd $(coregen_work_dir); \ - $(xil_env); \ - coregen -b $$OLDPWD/$<; \ - cd - - xcodir=`dirname $<`; \ - basename=`basename $< .xco`; \ - if [ ! -r $(coregen_work_dir/$$basename.ngc) ]; then \ - echo "'$@' wasn't created."; \ - exit 1; \ - else \ - cp $(coregen_work_dir)/$$basename.v $(coregen_work_dir)/$$basename.ngc $$xcodir; \ - fi -junk += $(coregen_work_dir) - -date = $(shell date +%F-%H-%M) - -# some common junk -junk += *.xrpt - -programming_files: $(project).bit $(project).mcs - mkdir -p $@/$(date) - mkdir -p $@/latest - for x in .bit .mcs .cfi _bd.bmm; do cp $(project)$$x $@/$(date)/$(project)$$x; cp $(project)$$x $@/latest/$(project)$$x; done - $(xil_env); xst -help | head -1 | sed 's/^/#/' | cat - $(project).scr > $@/$(date)/$(project).scr - -$(project).mcs: $(project).bit - $(xil_env); \ - promgen -w -s $(flashsize) -p mcs -o $@ -u 0 $^ -junk += $(project).mcs $(project).cfi $(project).prm - -$(project).bit: $(project)_par.ncd - $(xil_env); \ - bitgen $(intstyle) -g UserID:0x09470947 -g DriveDone:yes -g StartupClk:Cclk -w $(project)_par.ncd $(project).bit - # bitgen $(intstyle) -g compress -g UserID:0x09470947 -g DriveDone:yes -g StartupClk:Cclk -w $(project)_par.ncd $(project).bit - # bitgen $(intstyle) -g UserID:0x09470947 -g DriveDone:yes -g StartupClk:Cclk -w $(project)_par.ncd $(project).bit -junk += $(project).bgn $(project).bit $(project).drc $(project)_bd.bmm - - -$(project)_par.ncd: $(project).ncd - $(xil_env); \ - if par $(intstyle) $(par_opts) -w $(project).ncd $(project)_par.ncd; then \ - :; \ - else \ - $(MAKE) etwr; \ - fi -junk += $(project)_par.ncd $(project)_par.par $(project)_par.pad -junk += $(project)_par_pad.csv $(project)_par_pad.txt -junk += $(project)_par.grf $(project)_par.ptwx -junk += $(project)_par.unroutes $(project)_par.xpi - -$(project).ncd: $(project).ngd - if [ -r $(project)_par.ncd ]; then \ - cp $(project)_par.ncd smartguide.ncd; \ - smartguide="-smartguide smartguide.ncd"; \ - else \ - smartguide=""; \ - fi; \ - $(xil_env); \ - map $(intstyle) $(map_opts) $$smartguide $< -junk += $(project).ncd $(project).pcf $(project).ngm $(project).mrp $(project).map -junk += smartguide.ncd $(project).psr -junk += $(project)_summary.xml $(project)_usage.xml - -$(project).ngd: $(project).ngc $(project).ucf $(project).bmm - $(xil_env); ngdbuild $(intstyle) $(project).ngc -bm $(project).bmm -junk += $(project).ngd $(project).bld - -$(project).ngc: $(vfiles) $(local_corengcs) $(project).scr $(project).prj - $(xil_env); xst $(intstyle) -ifn $(project).scr -junk += xlnx_auto* $(top_module).lso $(project).srp -junk += netlist.lst xst $(project).ngc - -$(project).prj: $(vfiles) $(mkfiles) - for src in $(vfiles); do echo "verilog work $$src" >> $(project).tmpprj; done - sort -u $(project).tmpprj > $(project).prj - rm -f $(project).tmpprj -junk += $(project).prj - -optfile += $(wildcard $(project).opt) -top_module ?= $(project) -$(project).scr: $(optfile) $(mkfiles) ./xilinx.opt - echo "run" > $@ - echo "-p $(part)" >> $@ - echo "-top $(top_module)" >> $@ - echo "-ifn $(project).prj" >> $@ - echo "-ofn $(project).ngc" >> $@ - cat ./xilinx.opt $(optfile) >> $@ -junk += $(project).scr - -$(project).post_map.twr: $(project).ncd - $(xil_env); trce -e 10 $< $(project).pcf -o $@ -junk += $(project).post_map.twr $(project).post_map.twx smartpreview.twr - -$(project).twr: $(project)_par.ncd - $(xil_env); trce $< $(project).pcf -o $(project).twr -junk += $(project).twr $(project).twx smartpreview.twr - -$(project)_err.twr: $(project)_par.ncd - $(xil_env); trce -e 10 $< $(project).pcf -o $(project)_err.twr -junk += $(project)_err.twr $(project)_err.twx - -.gitignore: $(mkfiles) - echo programming_files $(junk) | sed 's, ,\n,g' > .gitignore - -clean:: - rm -rf $(junk) diff --git a/j1/xilinx/xilinx.opt b/j1/xilinx/xilinx.opt deleted file mode 100644 index c9e5ab7..0000000 --- a/j1/xilinx/xilinx.opt +++ /dev/null @@ -1,42 +0,0 @@ --ifmt mixed --ofmt NGC --opt_mode speed --opt_level 1 --iuc NO --keep_hierarchy no --netlist_hierarchy as_optimized --rtlview no --glob_opt AllClockNets --read_cores yes --write_timing_constraints NO --cross_clock_analysis NO --hierarchy_separator / --bus_delimiter <> --case maintain --slice_utilization_ratio 100 --bram_utilization_ratio 100 -#-dsp_utilization_ratio 100 --safe_implementation No --fsm_extract YES --fsm_encoding Auto --fsm_style lut --ram_extract Yes --ram_style Auto --rom_extract Yes --rom_style Auto --shreg_extract YES --auto_bram_packing NO --resource_sharing NO --async_to_sync NO -#-use_dsp48 auto --iobuf YES --max_fanout 500 --register_duplication YES --register_balancing No --optimize_primitives NO --use_clock_enable Auto --use_sync_set Auto --use_sync_reset Auto --iob auto --equivalent_register_removal YES --slice_utilization_ratio_maxmargin 5 -- cgit v1.2.3