From 6f86ce7057dd7cd1b491e8f09501258822d2ea74 Mon Sep 17 00:00:00 2001 From: Dimitri Sokolyuk Date: Tue, 23 May 2017 17:06:09 +0200 Subject: Import j1demo --- j1demo/synth/Makefile | 9 +++++++++ 1 file changed, 9 insertions(+) create mode 100644 j1demo/synth/Makefile (limited to 'j1demo/synth/Makefile') diff --git a/j1demo/synth/Makefile b/j1demo/synth/Makefile new file mode 100644 index 0000000..4cec0ac --- /dev/null +++ b/j1demo/synth/Makefile @@ -0,0 +1,9 @@ +project = j1 +vendor = xilinx +family = spartan3s +part = xc3s1000-4ft256 +top_module = top + +vfiles = ../verilog/top.v ../verilog/j1.v ../verilog/ck_div.v ../verilog/uart.v + +include xilinx.mk -- cgit v1.2.3