From 6f86ce7057dd7cd1b491e8f09501258822d2ea74 Mon Sep 17 00:00:00 2001 From: Dimitri Sokolyuk Date: Tue, 23 May 2017 17:06:09 +0200 Subject: Import j1demo --- j1demo/verilog/ck_div.v | 41 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) create mode 100644 j1demo/verilog/ck_div.v (limited to 'j1demo/verilog/ck_div.v') diff --git a/j1demo/verilog/ck_div.v b/j1demo/verilog/ck_div.v new file mode 100644 index 0000000..a753804 --- /dev/null +++ b/j1demo/verilog/ck_div.v @@ -0,0 +1,41 @@ +module ck_div( +input ck_in, +output ck_out, +input sys_rst_i +//output locked; +); +parameter DIV_BY = 1; +parameter MULT_BY = 1; + +wire ck_fb; + +//DCM #( +// .CLKDV_DIVIDE(DIV_BY), +// .DFS_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for frequency synthesis +// .DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE +// .STARTUP_WAIT("TRUE") // Delay configuration DONE until DCM LOCK, TRUE/FALSE +//) DCM_inst ( +// .CLK0(ck_fb), +// .CLKDV(ck_out), +// .CLKFB(ck_fb), // DCM clock feedback +// .CLKIN(ck_in), // Clock input (from IBUFG, BUFG or DCM) +// .RST(0) +//); + +DCM #( + .CLKFX_MULTIPLY(MULT_BY), + .CLKFX_DIVIDE(DIV_BY), + .DFS_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for frequency synthesis + .DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE + .STARTUP_WAIT("TRUE") // Delay configuration DONE until DCM LOCK, TRUE/FALSE +) DCM_inst ( + .CLK0(ck_fb), + .CLKFX(ck_out), + .CLKFB(ck_fb), // DCM clock feedback + .CLKIN(ck_in), // Clock input (from IBUFG, BUFG or DCM) + .RST(0) +); + +//BUFG BUFG_inst(.I(ck_int), .O(ck_out)); + +endmodule -- cgit v1.2.3