From a76977af62010a392c16010c367185e61e856ffe Mon Sep 17 00:00:00 2001 From: Dimitri Sokolyuk Date: Wed, 30 Oct 2019 20:04:56 +0100 Subject: mv to docs --- j1demo/verilog/rams.v | 36 ------------------------------------ 1 file changed, 36 deletions(-) delete mode 100644 j1demo/verilog/rams.v (limited to 'j1demo/verilog/rams.v') diff --git a/j1demo/verilog/rams.v b/j1demo/verilog/rams.v deleted file mode 100644 index 620a831..0000000 --- a/j1demo/verilog/rams.v +++ /dev/null @@ -1,36 +0,0 @@ -module ram8_8( - input [7:0] dia, - output [7:0] doa, - input wea, - input ena, - input clka, - input [10:0] addra, - - input [7:0] dib, - output [7:0] dob, - input web, - input enb, - input clkb, - input [10:0] addrb - ); -genvar i; -generate - for (i = 0; i < 4; i=i+1) begin : ramx - RAMB16_S2_S2 ramx( - .DIA(dia[2 * i + 1: 2 * i]), - .WEA(wea), - .ENA(ena), - .CLKA(clka), - .ADDRA(addra), - .DOA(doa[2 * i + 1: 2 * i]), - - .DIB(dib[2 * i + 1: 2 * i]), - .WEB(web), - .ENB(enb), - .CLKB(clkb), - .ADDRB(addrb), - .DOB(dob[2 * i + 1: 2 * i]) - ); - end -endgenerate -endmodule -- cgit v1.2.3