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-rw-r--r--amforth-6.5/avr8/devices/at90pwm161/blocks/AD_CONVERTER.frt71
-rw-r--r--amforth-6.5/avr8/devices/at90pwm161/blocks/ANALOG_COMPARATOR.frt69
-rw-r--r--amforth-6.5/avr8/devices/at90pwm161/blocks/BOOT_LOAD.frt21
-rw-r--r--amforth-6.5/avr8/devices/at90pwm161/blocks/CPU.frt114
-rw-r--r--amforth-6.5/avr8/devices/at90pwm161/blocks/DA_CONVERTER.frt19
-rw-r--r--amforth-6.5/avr8/devices/at90pwm161/blocks/EEPROM.frt21
-rw-r--r--amforth-6.5/avr8/devices/at90pwm161/blocks/EXTERNAL_INTERRUPT.frt17
-rw-r--r--amforth-6.5/avr8/devices/at90pwm161/blocks/PORTB.frt7
-rw-r--r--amforth-6.5/avr8/devices/at90pwm161/blocks/PORTD.frt7
-rw-r--r--amforth-6.5/avr8/devices/at90pwm161/blocks/PORTE.frt7
-rw-r--r--amforth-6.5/avr8/devices/at90pwm161/blocks/PSC0.frt90
-rw-r--r--amforth-6.5/avr8/devices/at90pwm161/blocks/PSC2.frt126
-rw-r--r--amforth-6.5/avr8/devices/at90pwm161/blocks/SPI.frt27
-rw-r--r--amforth-6.5/avr8/devices/at90pwm161/blocks/TIMER_COUNTER_1.frt25
-rw-r--r--amforth-6.5/avr8/devices/at90pwm161/blocks/WATCHDOG.frt15
-rw-r--r--amforth-6.5/avr8/devices/at90pwm161/device.asm52
-rw-r--r--amforth-6.5/avr8/devices/at90pwm161/device.frt613
-rw-r--r--amforth-6.5/avr8/devices/at90pwm161/device.py389
18 files changed, 1690 insertions, 0 deletions
diff --git a/amforth-6.5/avr8/devices/at90pwm161/blocks/AD_CONVERTER.frt b/amforth-6.5/avr8/devices/at90pwm161/blocks/AD_CONVERTER.frt
new file mode 100644
index 0000000..9464801
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90pwm161/blocks/AD_CONVERTER.frt
@@ -0,0 +1,71 @@
+\ Generated automatically for at90pwm161
+\ #require bitnames.frt
+
+\ AD_CONVERTER
+$28 constant ADMUX \ The ADC multiplexer Selection
+ $c0 constant ADMUX_REFS \ Reference Selection Bits
+ 28 $c0 bitmask: ADMUX.REFS \ Reference Selection Bits
+ $20 constant ADMUX_ADLAR \ Left Adjust Result
+ 28 $20 bitmask: ADMUX.ADLAR \ Left Adjust Result
+ $f constant ADMUX_MUX \ Analog Channel and Gain Select
+ 28 $f bitmask: ADMUX.MUX \ Analog Channel and Gain Select
+$26 constant ADCSRA \ The ADC Control and Status reg
+ $80 constant ADCSRA_ADEN \ ADC Enable
+ 26 $80 bitmask: ADCSRA.ADEN \ ADC Enable
+ $40 constant ADCSRA_ADSC \ ADC Start Conversion
+ 26 $40 bitmask: ADCSRA.ADSC \ ADC Start Conversion
+ $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
+ 26 $20 bitmask: ADCSRA.ADATE \ ADC Auto Trigger Enable
+ $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
+ 26 $10 bitmask: ADCSRA.ADIF \ ADC Interrupt Flag
+ $8 constant ADCSRA_ADIE \ ADC Interrupt Enable
+ 26 $8 bitmask: ADCSRA.ADIE \ ADC Interrupt Enable
+ $7 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
+ 26 $7 bitmask: ADCSRA.ADPS \ ADC Prescaler Select Bits
+$4c constant ADC \ ADC Data Register Bytes
+$27 constant ADCSRB \ ADC Control and Status Registe
+ $80 constant ADCSRB_ADHSM \ ADC High Speed Mode
+ 27 $80 bitmask: ADCSRB.ADHSM \ ADC High Speed Mode
+ $40 constant ADCSRB_ADNCDIS \ ADC Noise Canceller Disable
+ 27 $40 bitmask: ADCSRB.ADNCDIS \ ADC Noise Canceller Disable
+ $10 constant ADCSRB_ADSSEN \ ADC Single Shot Enable on PSC'
+ 27 $10 bitmask: ADCSRB.ADSSEN \ ADC Single Shot Enable on PSC'
+ $f constant ADCSRB_ADTS \ ADC Auto Trigger Sources
+ 27 $f bitmask: ADCSRB.ADTS \ ADC Auto Trigger Sources
+$77 constant DIDR0 \ Digital Input Disable Register
+ $80 constant DIDR0_ADC7D \
+ 77 $80 bitmask: DIDR0.ADC7D \
+ $40 constant DIDR0_ADC6D \ ADC7 Digital input Disable
+ 77 $40 bitmask: DIDR0.ADC6D \ ADC7 Digital input Disable
+ $20 constant DIDR0_ADC5D \ ADC5 Digital input Disable
+ 77 $20 bitmask: DIDR0.ADC5D \ ADC5 Digital input Disable
+ $10 constant DIDR0_ADC4D \ ADC4 Digital input Disable
+ 77 $10 bitmask: DIDR0.ADC4D \ ADC4 Digital input Disable
+ $8 constant DIDR0_ADC3D \ ADC3 Digital input Disable
+ 77 $8 bitmask: DIDR0.ADC3D \ ADC3 Digital input Disable
+ $4 constant DIDR0_ADC2D \ ADC2 Digital input Disable
+ 77 $4 bitmask: DIDR0.ADC2D \ ADC2 Digital input Disable
+ $2 constant DIDR0_ADC1D \ ADC1 Digital input Disable
+ 77 $2 bitmask: DIDR0.ADC1D \ ADC1 Digital input Disable
+ $1 constant DIDR0_ADC0D \ ADC0 Digital input Disable
+ 77 $1 bitmask: DIDR0.ADC0D \ ADC0 Digital input Disable
+$78 constant DIDR1 \ Digital Input Disable Register
+ $8 constant DIDR1_ACMP1MD \
+ 78 $8 bitmask: DIDR1.ACMP1MD \
+ $4 constant DIDR1_AMP0POSD \
+ 78 $4 bitmask: DIDR1.AMP0POSD \
+ $2 constant DIDR1_ADC10D \
+ 78 $2 bitmask: DIDR1.ADC10D \
+ $1 constant DIDR1_ADC9D \
+ 78 $1 bitmask: DIDR1.ADC9D \
+$79 constant AMP0CSR \
+ $80 constant AMP0CSR_AMP0EN \
+ 79 $80 bitmask: AMP0CSR.AMP0EN \
+ $40 constant AMP0CSR_AMP0IS \
+ 79 $40 bitmask: AMP0CSR.AMP0IS \
+ $30 constant AMP0CSR_AMP0G \
+ 79 $30 bitmask: AMP0CSR.AMP0G \
+ $8 constant AMP0CSR_AMP0GS \
+ 79 $8 bitmask: AMP0CSR.AMP0GS \
+ $3 constant AMP0CSR_AMP0TS \
+ 79 $3 bitmask: AMP0CSR.AMP0TS \
diff --git a/amforth-6.5/avr8/devices/at90pwm161/blocks/ANALOG_COMPARATOR.frt b/amforth-6.5/avr8/devices/at90pwm161/blocks/ANALOG_COMPARATOR.frt
new file mode 100644
index 0000000..1db32bc
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90pwm161/blocks/ANALOG_COMPARATOR.frt
@@ -0,0 +1,69 @@
+\ Generated automatically for at90pwm161
+\ #require bitnames.frt
+
+\ ANALOG_COMPARATOR
+$7f constant AC3CON \ Analog Comparator3 Control Reg
+ $80 constant AC3CON_AC3EN \ Analog Comparator3 Enable Bit
+ 7f $80 bitmask: AC3CON.AC3EN \ Analog Comparator3 Enable Bit
+ $40 constant AC3CON_AC3IE \ Analog Comparator 3 Interrupt
+ 7f $40 bitmask: AC3CON.AC3IE \ Analog Comparator 3 Interrupt
+ $30 constant AC3CON_AC3IS \ Analog Comparator 3 Interrupt
+ 7f $30 bitmask: AC3CON.AC3IS \ Analog Comparator 3 Interrupt
+ $8 constant AC3CON_AC3OEA \ Analog Comparator 3 Alternate
+ 7f $8 bitmask: AC3CON.AC3OEA \ Analog Comparator 3 Alternate
+ $7 constant AC3CON_AC3M \ Analog Comparator 3 Multiplexe
+ 7f $7 bitmask: AC3CON.AC3M \ Analog Comparator 3 Multiplexe
+$7d constant AC1CON \ Analog Comparator 1 Control Re
+ $80 constant AC1CON_AC1EN \ Analog Comparator 1 Enable Bit
+ 7d $80 bitmask: AC1CON.AC1EN \ Analog Comparator 1 Enable Bit
+ $40 constant AC1CON_AC1IE \ Analog Comparator 1 Interrupt
+ 7d $40 bitmask: AC1CON.AC1IE \ Analog Comparator 1 Interrupt
+ $30 constant AC1CON_AC1IS \ Analog Comparator 1 Interrupt
+ 7d $30 bitmask: AC1CON.AC1IS \ Analog Comparator 1 Interrupt
+ $7 constant AC1CON_AC1M \ Analog Comparator 1 Multiplexe
+ 7d $7 bitmask: AC1CON.AC1M \ Analog Comparator 1 Multiplexe
+$7e constant AC2CON \ Analog Comparator 2 Control Re
+ $80 constant AC2CON_AC2EN \ Analog Comparator 2 Enable Bit
+ 7e $80 bitmask: AC2CON.AC2EN \ Analog Comparator 2 Enable Bit
+ $40 constant AC2CON_AC2IE \ Analog Comparator 2 Interrupt
+ 7e $40 bitmask: AC2CON.AC2IE \ Analog Comparator 2 Interrupt
+ $30 constant AC2CON_AC2IS \ Analog Comparator 2 Interrupt
+ 7e $30 bitmask: AC2CON.AC2IS \ Analog Comparator 2 Interrupt
+ $7 constant AC2CON_AC2M \ Analog Comparator 2 Multiplexe
+ 7e $7 bitmask: AC2CON.AC2M \ Analog Comparator 2 Multiplexe
+$20 constant ACSR \ Analog Comparator Status Regis
+ $80 constant ACSR_AC3IF \ Analog Comparator 3 Interrupt
+ 20 $80 bitmask: ACSR.AC3IF \ Analog Comparator 3 Interrupt
+ $40 constant ACSR_AC2IF \ Analog Comparator 2 Interrupt
+ 20 $40 bitmask: ACSR.AC2IF \ Analog Comparator 2 Interrupt
+ $20 constant ACSR_AC1IF \ Analog Comparator 1 Interrupt
+ 20 $20 bitmask: ACSR.AC1IF \ Analog Comparator 1 Interrupt
+ $8 constant ACSR_AC3O \ Analog Comparator 3 Output Bit
+ 20 $8 bitmask: ACSR.AC3O \ Analog Comparator 3 Output Bit
+ $4 constant ACSR_AC2O \ Analog Comparator 2 Output Bit
+ 20 $4 bitmask: ACSR.AC2O \ Analog Comparator 2 Output Bit
+ $2 constant ACSR_AC1O \ Analog Comparator 1 Output Bit
+ 20 $2 bitmask: ACSR.AC1O \ Analog Comparator 1 Output Bit
+$7c constant AC3ECON \
+ $20 constant AC3ECON_AC3OI \ Analog Comparator Ouput Invert
+ 7c $20 bitmask: AC3ECON.AC3OI \ Analog Comparator Ouput Invert
+ $10 constant AC3ECON_AC3OE \ Analog Comparator Ouput Enable
+ 7c $10 bitmask: AC3ECON.AC3OE \ Analog Comparator Ouput Enable
+ $7 constant AC3ECON_AC3H \ Analog Comparator Hysteresis S
+ 7c $7 bitmask: AC3ECON.AC3H \ Analog Comparator Hysteresis S
+$7b constant AC2ECON \
+ $20 constant AC2ECON_AC2OI \ Analog Comparator Ouput Invert
+ 7b $20 bitmask: AC2ECON.AC2OI \ Analog Comparator Ouput Invert
+ $10 constant AC2ECON_AC2OE \ Analog Comparator Ouput Enable
+ 7b $10 bitmask: AC2ECON.AC2OE \ Analog Comparator Ouput Enable
+ $7 constant AC2ECON_AC2H \ Analog Comparator Hysteresis S
+ 7b $7 bitmask: AC2ECON.AC2H \ Analog Comparator Hysteresis S
+$7a constant AC1ECON \
+ $20 constant AC1ECON_AC1OI \ Analog Comparator Ouput Invert
+ 7a $20 bitmask: AC1ECON.AC1OI \ Analog Comparator Ouput Invert
+ $10 constant AC1ECON_AC1OE \ Analog Comparator Ouput Enable
+ 7a $10 bitmask: AC1ECON.AC1OE \ Analog Comparator Ouput Enable
+ $8 constant AC1ECON_AC1ICE \ Analog Comparator Interrupt Ca
+ 7a $8 bitmask: AC1ECON.AC1ICE \ Analog Comparator Interrupt Ca
+ $7 constant AC1ECON_AC1H \ Analog Comparator Hysteresis S
+ 7a $7 bitmask: AC1ECON.AC1H \ Analog Comparator Hysteresis S
diff --git a/amforth-6.5/avr8/devices/at90pwm161/blocks/BOOT_LOAD.frt b/amforth-6.5/avr8/devices/at90pwm161/blocks/BOOT_LOAD.frt
new file mode 100644
index 0000000..37089a7
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90pwm161/blocks/BOOT_LOAD.frt
@@ -0,0 +1,21 @@
+\ Generated automatically for at90pwm161
+\ #require bitnames.frt
+
+\ BOOT_LOAD
+$57 constant SPMCSR \ Store Program Memory Control R
+ $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
+ 57 $80 bitmask: SPMCSR.SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
+ 57 $40 bitmask: SPMCSR.RWWSB \ Read While Write Section Busy
+ $20 constant SPMCSR_SIGRD \ Signature Row Read
+ 57 $20 bitmask: SPMCSR.SIGRD \ Signature Row Read
+ $10 constant SPMCSR_RWWSRE \ Read While Write section read
+ 57 $10 bitmask: SPMCSR.RWWSRE \ Read While Write section read
+ $8 constant SPMCSR_BLBSET \ Boot Lock Bit Set
+ 57 $8 bitmask: SPMCSR.BLBSET \ Boot Lock Bit Set
+ $4 constant SPMCSR_PGWRT \ Page Write
+ 57 $4 bitmask: SPMCSR.PGWRT \ Page Write
+ $2 constant SPMCSR_PGERS \ Page Erase
+ 57 $2 bitmask: SPMCSR.PGERS \ Page Erase
+ $1 constant SPMCSR_SPMEN \ Store Program Memory Enable
+ 57 $1 bitmask: SPMCSR.SPMEN \ Store Program Memory Enable
diff --git a/amforth-6.5/avr8/devices/at90pwm161/blocks/CPU.frt b/amforth-6.5/avr8/devices/at90pwm161/blocks/CPU.frt
new file mode 100644
index 0000000..37032ab
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90pwm161/blocks/CPU.frt
@@ -0,0 +1,114 @@
+\ Generated automatically for at90pwm161
+\ #require bitnames.frt
+
+\ CPU
+$5f constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ 5f $80 bitmask: SREG.I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ 5f $40 bitmask: SREG.T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ 5f $20 bitmask: SREG.H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ 5f $10 bitmask: SREG.S \ Sign Bit
+ $8 constant SREG_V \ Two's Complement Overflow Flag
+ 5f $8 bitmask: SREG.V \ Two's Complement Overflow Flag
+ $4 constant SREG_N \ Negative Flag
+ 5f $4 bitmask: SREG.N \ Negative Flag
+ $2 constant SREG_Z \ Zero Flag
+ 5f $2 bitmask: SREG.Z \ Zero Flag
+ $1 constant SREG_C \ Carry Flag
+ 5f $1 bitmask: SREG.C \ Carry Flag
+$5d constant SP \ Stack Pointer
+$55 constant MCUCR \ MCU Control Register
+ $10 constant MCUCR_PUD \ Pull-up disable
+ 55 $10 bitmask: MCUCR.PUD \ Pull-up disable
+ $8 constant MCUCR_RSTDIS \ Reset Pin Disable
+ 55 $8 bitmask: MCUCR.RSTDIS \ Reset Pin Disable
+ $4 constant MCUCR_CKRC81 \ Frequency Selection of the Cal
+ 55 $4 bitmask: MCUCR.CKRC81 \ Frequency Selection of the Cal
+ $2 constant MCUCR_IVSEL \ Interrupt Vector Select
+ 55 $2 bitmask: MCUCR.IVSEL \ Interrupt Vector Select
+ $1 constant MCUCR_IVCE \ Interrupt Vector Change Enable
+ 55 $1 bitmask: MCUCR.IVCE \ Interrupt Vector Change Enable
+$54 constant MCUSR \ MCU Status Register
+ $8 constant MCUSR_WDRF \ Watchdog Reset Flag
+ 54 $8 bitmask: MCUSR.WDRF \ Watchdog Reset Flag
+ $4 constant MCUSR_BORF \ Brown-out Reset Flag
+ 54 $4 bitmask: MCUSR.BORF \ Brown-out Reset Flag
+ $2 constant MCUSR_EXTRF \ External Reset Flag
+ 54 $2 bitmask: MCUSR.EXTRF \ External Reset Flag
+ $1 constant MCUSR_PORF \ Power-on reset flag
+ 54 $1 bitmask: MCUSR.PORF \ Power-on reset flag
+$88 constant OSCCAL \ Oscillator Calibration Value
+$83 constant CLKPR \
+ $80 constant CLKPR_CLKPCE \
+ 83 $80 bitmask: CLKPR.CLKPCE \
+ $f constant CLKPR_CLKPS \
+ 83 $f bitmask: CLKPR.CLKPS \
+$53 constant SMCR \ Sleep Mode Control Register
+ $e constant SMCR_SM \ Sleep Mode Select bits
+ 53 $e bitmask: SMCR.SM \ Sleep Mode Select bits
+ $1 constant SMCR_SE \ Sleep Enable
+ 53 $1 bitmask: SMCR.SE \ Sleep Enable
+$3b constant GPIOR2 \ General Purpose IO Register 2
+ $ff constant GPIOR2_GPIOR \ General Purpose IO Register 2
+ 3b $ff bitmask: GPIOR2.GPIOR \ General Purpose IO Register 2
+$3a constant GPIOR1 \ General Purpose IO Register 1
+ $ff constant GPIOR1_GPIOR \ General Purpose IO Register 1
+ 3a $ff bitmask: GPIOR1.GPIOR \ General Purpose IO Register 1
+$39 constant GPIOR0 \ General Purpose IO Register 0
+ $80 constant GPIOR0_GPIOR07 \ General Purpose IO Register 0
+ 39 $80 bitmask: GPIOR0.GPIOR07 \ General Purpose IO Register 0
+ $40 constant GPIOR0_GPIOR06 \ General Purpose IO Register 0
+ 39 $40 bitmask: GPIOR0.GPIOR06 \ General Purpose IO Register 0
+ $20 constant GPIOR0_GPIOR05 \ General Purpose IO Register 0
+ 39 $20 bitmask: GPIOR0.GPIOR05 \ General Purpose IO Register 0
+ $10 constant GPIOR0_GPIOR04 \ General Purpose IO Register 0
+ 39 $10 bitmask: GPIOR0.GPIOR04 \ General Purpose IO Register 0
+ $8 constant GPIOR0_GPIOR03 \ General Purpose IO Register 0
+ 39 $8 bitmask: GPIOR0.GPIOR03 \ General Purpose IO Register 0
+ $4 constant GPIOR0_GPIOR02 \ General Purpose IO Register 0
+ 39 $4 bitmask: GPIOR0.GPIOR02 \ General Purpose IO Register 0
+ $2 constant GPIOR0_GPIOR01 \ General Purpose IO Register 0
+ 39 $2 bitmask: GPIOR0.GPIOR01 \ General Purpose IO Register 0
+ $1 constant GPIOR0_GPIOR00 \ General Purpose IO Register 0
+ 39 $1 bitmask: GPIOR0.GPIOR00 \ General Purpose IO Register 0
+$87 constant PLLCSR \ PLL Control And Status Registe
+ $3c constant PLLCSR_PLLF \
+ 87 $3c bitmask: PLLCSR.PLLF \
+ $2 constant PLLCSR_PLLE \ PLL Enable
+ 87 $2 bitmask: PLLCSR.PLLE \ PLL Enable
+ $1 constant PLLCSR_PLOCK \ PLL Lock Detector
+ 87 $1 bitmask: PLLCSR.PLOCK \ PLL Lock Detector
+$86 constant PRR \ Power Reduction Register
+ $80 constant PRR_PRPSC2 \ Power Reduction PSC2
+ 86 $80 bitmask: PRR.PRPSC2 \ Power Reduction PSC2
+ $20 constant PRR_PRPSCR \ Power Reduction PSC0
+ 86 $20 bitmask: PRR.PRPSCR \ Power Reduction PSC0
+ $10 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
+ 86 $10 bitmask: PRR.PRTIM1 \ Power Reduction Timer/Counter1
+ $4 constant PRR_PRSPI \ Power Reduction Serial Periphe
+ 86 $4 bitmask: PRR.PRSPI \ Power Reduction Serial Periphe
+ $1 constant PRR_PRADC \ Power Reduction ADC
+ 86 $1 bitmask: PRR.PRADC \ Power Reduction ADC
+$84 constant CLKCSR \
+ $80 constant CLKCSR_CLKCCE \ Clock Control Change Enable
+ 84 $80 bitmask: CLKCSR.CLKCCE \ Clock Control Change Enable
+ $10 constant CLKCSR_CLKRDY \ Clock Ready Flag
+ 84 $10 bitmask: CLKCSR.CLKRDY \ Clock Ready Flag
+ $f constant CLKCSR_CLKC \ Clock Control
+ 84 $f bitmask: CLKCSR.CLKC \ Clock Control
+$85 constant CLKSELR \
+ $40 constant CLKSELR_COUT \ Clock OUT
+ 85 $40 bitmask: CLKSELR.COUT \ Clock OUT
+ $30 constant CLKSELR_CSUT \ Clock Start up Time
+ 85 $30 bitmask: CLKSELR.CSUT \ Clock Start up Time
+ $f constant CLKSELR_CKSEL \ Clock Source Select
+ 85 $f bitmask: CLKSELR.CKSEL \ Clock Source Select
+$81 constant BGCCR \ BandGap Current Calibration Re
+ $f constant BGCCR_BGCC \
+ 81 $f bitmask: BGCCR.BGCC \
+$80 constant BGCRR \ BandGap Resistor Calibration R
+ $f constant BGCRR_BGCR \
+ 80 $f bitmask: BGCRR.BGCR \
diff --git a/amforth-6.5/avr8/devices/at90pwm161/blocks/DA_CONVERTER.frt b/amforth-6.5/avr8/devices/at90pwm161/blocks/DA_CONVERTER.frt
new file mode 100644
index 0000000..9c36fb7
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90pwm161/blocks/DA_CONVERTER.frt
@@ -0,0 +1,19 @@
+\ Generated automatically for at90pwm161
+\ #require bitnames.frt
+
+\ DA_CONVERTER
+$59 constant DACH \ DAC Data Register High Byte
+ $ff constant DACH_DACH \ DAC Data Register High Byte Bi
+ 59 $ff bitmask: DACH.DACH \ DAC Data Register High Byte Bi
+$58 constant DACL \ DAC Data Register Low Byte
+ $ff constant DACL_DACL \ DAC Data Register Low Byte Bit
+ 58 $ff bitmask: DACL.DACL \ DAC Data Register Low Byte Bit
+$76 constant DACON \ DAC Control Register
+ $80 constant DACON_DAATE \ DAC Auto Trigger Enable Bit
+ 76 $80 bitmask: DACON.DAATE \ DAC Auto Trigger Enable Bit
+ $70 constant DACON_DATS \ DAC Trigger Selection Bits
+ 76 $70 bitmask: DACON.DATS \ DAC Trigger Selection Bits
+ $4 constant DACON_DALA \ DAC Left Adjust
+ 76 $4 bitmask: DACON.DALA \ DAC Left Adjust
+ $1 constant DACON_DAEN \ DAC Enable Bit
+ 76 $1 bitmask: DACON.DAEN \ DAC Enable Bit
diff --git a/amforth-6.5/avr8/devices/at90pwm161/blocks/EEPROM.frt b/amforth-6.5/avr8/devices/at90pwm161/blocks/EEPROM.frt
new file mode 100644
index 0000000..b30d081
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90pwm161/blocks/EEPROM.frt
@@ -0,0 +1,21 @@
+\ Generated automatically for at90pwm161
+\ #require bitnames.frt
+
+\ EEPROM
+$3e constant EEAR \ EEPROM Read/Write Access Byte
+$3d constant EEDR \ EEPROM Data Register
+$3c constant EECR \ EEPROM Control Register
+ $80 constant EECR_NVMBSY \ None Volatile Busy Memory Busy
+ 3c $80 bitmask: EECR.NVMBSY \ None Volatile Busy Memory Busy
+ $40 constant EECR_EEPAGE \ EEPROM Page Access
+ 3c $40 bitmask: EECR.EEPAGE \ EEPROM Page Access
+ $30 constant EECR_EEPM \ EEPROM Programming Mode
+ 3c $30 bitmask: EECR.EEPM \ EEPROM Programming Mode
+ $8 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
+ 3c $8 bitmask: EECR.EERIE \ EEPROM Ready Interrupt Enable
+ $4 constant EECR_EEMWE \ EEPROM Master Write Enable
+ 3c $4 bitmask: EECR.EEMWE \ EEPROM Master Write Enable
+ $2 constant EECR_EEWE \ EEPROM Write Enable
+ 3c $2 bitmask: EECR.EEWE \ EEPROM Write Enable
+ $1 constant EECR_EERE \ EEPROM Read Enable
+ 3c $1 bitmask: EECR.EERE \ EEPROM Read Enable
diff --git a/amforth-6.5/avr8/devices/at90pwm161/blocks/EXTERNAL_INTERRUPT.frt b/amforth-6.5/avr8/devices/at90pwm161/blocks/EXTERNAL_INTERRUPT.frt
new file mode 100644
index 0000000..6a0ecdc
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90pwm161/blocks/EXTERNAL_INTERRUPT.frt
@@ -0,0 +1,17 @@
+\ Generated automatically for at90pwm161
+\ #require bitnames.frt
+
+\ EXTERNAL_INTERRUPT
+$89 constant EICRA \ External Interrupt Control Reg
+ $30 constant EICRA_ISC2 \ External Interrupt Sense Contr
+ 89 $30 bitmask: EICRA.ISC2 \ External Interrupt Sense Contr
+ $c constant EICRA_ISC1 \ External Interrupt Sense Contr
+ 89 $c bitmask: EICRA.ISC1 \ External Interrupt Sense Contr
+ $3 constant EICRA_ISC0 \ External Interrupt Sense Contr
+ 89 $3 bitmask: EICRA.ISC0 \ External Interrupt Sense Contr
+$41 constant EIMSK \ External Interrupt Mask Regist
+ $7 constant EIMSK_INT \ External Interrupt Request 2 E
+ 41 $7 bitmask: EIMSK.INT \ External Interrupt Request 2 E
+$40 constant EIFR \ External Interrupt Flag Regist
+ $7 constant EIFR_INTF \ External Interrupt Flags
+ 40 $7 bitmask: EIFR.INTF \ External Interrupt Flags
diff --git a/amforth-6.5/avr8/devices/at90pwm161/blocks/PORTB.frt b/amforth-6.5/avr8/devices/at90pwm161/blocks/PORTB.frt
new file mode 100644
index 0000000..14612b5
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90pwm161/blocks/PORTB.frt
@@ -0,0 +1,7 @@
+\ Generated automatically for at90pwm161
+\ #require bitnames.frt
+
+\ PORTB
+$25 constant PORTB \ Port B Data Register
+$24 constant DDRB \ Port B Data Direction Register
+$23 constant PINB \ Port B Input Pins
diff --git a/amforth-6.5/avr8/devices/at90pwm161/blocks/PORTD.frt b/amforth-6.5/avr8/devices/at90pwm161/blocks/PORTD.frt
new file mode 100644
index 0000000..a45e474
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90pwm161/blocks/PORTD.frt
@@ -0,0 +1,7 @@
+\ Generated automatically for at90pwm161
+\ #require bitnames.frt
+
+\ PORTD
+$2b constant PORTD \ Port D Data Register
+$2a constant DDRD \ Port D Data Direction Register
+$29 constant PIND \ Port D Input Pins
diff --git a/amforth-6.5/avr8/devices/at90pwm161/blocks/PORTE.frt b/amforth-6.5/avr8/devices/at90pwm161/blocks/PORTE.frt
new file mode 100644
index 0000000..f774d19
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90pwm161/blocks/PORTE.frt
@@ -0,0 +1,7 @@
+\ Generated automatically for at90pwm161
+\ #require bitnames.frt
+
+\ PORTE
+$2e constant PORTE \ Port E Data Register
+$2d constant DDRE \ Port E Data Direction Register
+$2c constant PINE \ Port E Input Pins
diff --git a/amforth-6.5/avr8/devices/at90pwm161/blocks/PSC0.frt b/amforth-6.5/avr8/devices/at90pwm161/blocks/PSC0.frt
new file mode 100644
index 0000000..3774cfe
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90pwm161/blocks/PSC0.frt
@@ -0,0 +1,90 @@
+\ Generated automatically for at90pwm161
+\ #require bitnames.frt
+
+\ PSC0
+$68 constant PICR0 \ PSC 0 Input Capture Register
+$63 constant PFRC0B \ PSC 0 Input B Control
+ $80 constant PFRC0B_PCAE0B \ PSC 0 Capture Enable Input Par
+ 63 $80 bitmask: PFRC0B.PCAE0B \ PSC 0 Capture Enable Input Par
+ $40 constant PFRC0B_PISEL0B \ PSC 0 Input Select for Part B
+ 63 $40 bitmask: PFRC0B.PISEL0B \ PSC 0 Input Select for Part B
+ $20 constant PFRC0B_PELEV0B \ PSC 0 Edge Level Selector on I
+ 63 $20 bitmask: PFRC0B.PELEV0B \ PSC 0 Edge Level Selector on I
+ $10 constant PFRC0B_PFLTE0B \ PSC 0 Filter Enable on Input P
+ 63 $10 bitmask: PFRC0B.PFLTE0B \ PSC 0 Filter Enable on Input P
+ $f constant PFRC0B_PRFM0B \ PSC 0 Retrigger and Fault Mode
+ 63 $f bitmask: PFRC0B.PRFM0B \ PSC 0 Retrigger and Fault Mode
+$62 constant PFRC0A \ PSC 0 Input A Control
+ $80 constant PFRC0A_PCAE0A \ PSC 0 Capture Enable Input Par
+ 62 $80 bitmask: PFRC0A.PCAE0A \ PSC 0 Capture Enable Input Par
+ $40 constant PFRC0A_PISEL0A \ PSC 0 Input Select for Part A
+ 62 $40 bitmask: PFRC0A.PISEL0A \ PSC 0 Input Select for Part A
+ $20 constant PFRC0A_PELEV0A \ PSC 0 Edge Level Selector on I
+ 62 $20 bitmask: PFRC0A.PELEV0A \ PSC 0 Edge Level Selector on I
+ $10 constant PFRC0A_PFLTE0A \ PSC 0 Filter Enable on Input P
+ 62 $10 bitmask: PFRC0A.PFLTE0A \ PSC 0 Filter Enable on Input P
+ $f constant PFRC0A_PRFM0A \ PSC 0 Retrigger and Fault Mode
+ 62 $f bitmask: PFRC0A.PRFM0A \ PSC 0 Retrigger and Fault Mode
+$32 constant PCTL0 \ PSC 0 Control Register
+ $c0 constant PCTL0_PPRE0 \ PSC 0 Prescaler Selects
+ 32 $c0 bitmask: PCTL0.PPRE0 \ PSC 0 Prescaler Selects
+ $24 constant PCTL0_PBFM0 \ PSC 0 Balance Flank Width Modu
+ 32 $24 bitmask: PCTL0.PBFM0 \ PSC 0 Balance Flank Width Modu
+ $10 constant PCTL0_PAOC0B \ PSC 0 Asynchronous Output Cont
+ 32 $10 bitmask: PCTL0.PAOC0B \ PSC 0 Asynchronous Output Cont
+ $8 constant PCTL0_PAOC0A \ PSC 0 Asynchronous Output Cont
+ 32 $8 bitmask: PCTL0.PAOC0A \ PSC 0 Asynchronous Output Cont
+ $2 constant PCTL0_PCCYC0 \ PSC0 Complete Cycle
+ 32 $2 bitmask: PCTL0.PCCYC0 \ PSC0 Complete Cycle
+ $1 constant PCTL0_PRUN0 \ PSC 0 Run
+ 32 $1 bitmask: PCTL0.PRUN0 \ PSC 0 Run
+$31 constant PCNF0 \ PSC 0 Configuration Register
+ $80 constant PCNF0_PFIFTY0 \ PSC 0 Fifty
+ 31 $80 bitmask: PCNF0.PFIFTY0 \ PSC 0 Fifty
+ $40 constant PCNF0_PALOCK0 \ PSC 0 Autolock
+ 31 $40 bitmask: PCNF0.PALOCK0 \ PSC 0 Autolock
+ $20 constant PCNF0_PLOCK0 \ PSC 0 Lock
+ 31 $20 bitmask: PCNF0.PLOCK0 \ PSC 0 Lock
+ $18 constant PCNF0_PMODE0 \ PSC 0 Mode
+ 31 $18 bitmask: PCNF0.PMODE0 \ PSC 0 Mode
+ $4 constant PCNF0_POP0 \ PSC 0 Output Polarity
+ 31 $4 bitmask: PCNF0.POP0 \ PSC 0 Output Polarity
+ $2 constant PCNF0_PCLKSEL0 \ PSC 0 Input Clock Select
+ 31 $2 bitmask: PCNF0.PCLKSEL0 \ PSC 0 Input Clock Select
+$44 constant OCR0RB \ Output Compare RB Register
+$42 constant OCR0SB \ Output Compare SB Register
+$4a constant OCR0RA \ Output Compare RA Register
+$60 constant OCR0SA \ Output Compare SA Register
+$6a constant PSOC0 \ PSC0 Synchro and Output Config
+ $80 constant PSOC0_PISEL0A1 \ PSC Input Select
+ 6a $80 bitmask: PSOC0.PISEL0A1 \ PSC Input Select
+ $40 constant PSOC0_PISEL0B1 \ PSC Input Select
+ 6a $40 bitmask: PSOC0.PISEL0B1 \ PSC Input Select
+ $30 constant PSOC0_PSYNC0 \ Synchronisation out for ADC se
+ 6a $30 bitmask: PSOC0.PSYNC0 \ Synchronisation out for ADC se
+ $4 constant PSOC0_POEN0B \ PSCOUT01 Output Enable
+ 6a $4 bitmask: PSOC0.POEN0B \ PSCOUT01 Output Enable
+ $1 constant PSOC0_POEN0A \ PSCOUT00 Output Enable
+ 6a $1 bitmask: PSOC0.POEN0A \ PSCOUT00 Output Enable
+$2f constant PIM0 \ PSC0 Interrupt Mask Register
+ $10 constant PIM0_PEVE0B \ External Event B Interrupt Ena
+ 2f $10 bitmask: PIM0.PEVE0B \ External Event B Interrupt Ena
+ $8 constant PIM0_PEVE0A \ External Event A Interrupt Ena
+ 2f $8 bitmask: PIM0.PEVE0A \ External Event A Interrupt Ena
+ $2 constant PIM0_PEOEPE0 \ End of Enhanced Cycle Enable
+ 2f $2 bitmask: PIM0.PEOEPE0 \ End of Enhanced Cycle Enable
+ $1 constant PIM0_PEOPE0 \ End of Cycle Interrupt Enable
+ 2f $1 bitmask: PIM0.PEOPE0 \ End of Cycle Interrupt Enable
+$30 constant PIFR0 \ PSC0 Interrupt Flag Register
+ $80 constant PIFR0_POAC0B \ PSC 0 Output A Activity
+ 30 $80 bitmask: PIFR0.POAC0B \ PSC 0 Output A Activity
+ $40 constant PIFR0_POAC0A \ PSC 0 Output A Activity
+ 30 $40 bitmask: PIFR0.POAC0A \ PSC 0 Output A Activity
+ $10 constant PIFR0_PEV0B \ External Event B Interrupt
+ 30 $10 bitmask: PIFR0.PEV0B \ External Event B Interrupt
+ $8 constant PIFR0_PEV0A \ External Event A Interrupt
+ 30 $8 bitmask: PIFR0.PEV0A \ External Event A Interrupt
+ $6 constant PIFR0_PRN0 \ Ramp Number
+ 30 $6 bitmask: PIFR0.PRN0 \ Ramp Number
+ $1 constant PIFR0_PEOP0 \ End of PSC0 Interrupt
+ 30 $1 bitmask: PIFR0.PEOP0 \ End of PSC0 Interrupt
diff --git a/amforth-6.5/avr8/devices/at90pwm161/blocks/PSC2.frt b/amforth-6.5/avr8/devices/at90pwm161/blocks/PSC2.frt
new file mode 100644
index 0000000..68acc9f
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90pwm161/blocks/PSC2.frt
@@ -0,0 +1,126 @@
+\ Generated automatically for at90pwm161
+\ #require bitnames.frt
+
+\ PSC2
+$6d constant PICR2H \ PSC 2 Input Capture Register H
+ $80 constant PICR2H_PCST2 \ PSC 2 Capture Software Trigger
+ 6d $80 bitmask: PICR2H.PCST2 \ PSC 2 Capture Software Trigger
+ $c constant PICR2H_PICR21 \
+ 6d $c bitmask: PICR2H.PICR21 \
+ $3 constant PICR2H_PICR2 \
+ 6d $3 bitmask: PICR2H.PICR2 \
+$6c constant PICR2L \ PSC 2 Input Capture Register L
+$67 constant PFRC2B \ PSC 2 Input B Control
+ $80 constant PFRC2B_PCAE2B \ PSC 2 Capture Enable Input Par
+ 67 $80 bitmask: PFRC2B.PCAE2B \ PSC 2 Capture Enable Input Par
+ $40 constant PFRC2B_PISEL2B \ PSC 2 Input Select for Part B
+ 67 $40 bitmask: PFRC2B.PISEL2B \ PSC 2 Input Select for Part B
+ $20 constant PFRC2B_PELEV2B \ PSC 2 Edge Level Selector on I
+ 67 $20 bitmask: PFRC2B.PELEV2B \ PSC 2 Edge Level Selector on I
+ $10 constant PFRC2B_PFLTE2B \ PSC 2 Filter Enable on Input P
+ 67 $10 bitmask: PFRC2B.PFLTE2B \ PSC 2 Filter Enable on Input P
+ $f constant PFRC2B_PRFM2B \ PSC 2 Retrigger and Fault Mode
+ 67 $f bitmask: PFRC2B.PRFM2B \ PSC 2 Retrigger and Fault Mode
+$66 constant PFRC2A \ PSC 2 Input B Control
+ $80 constant PFRC2A_PCAE2A \ PSC 2 Capture Enable Input Par
+ 66 $80 bitmask: PFRC2A.PCAE2A \ PSC 2 Capture Enable Input Par
+ $40 constant PFRC2A_PISEL2A \ PSC 2 Input Select for Part A
+ 66 $40 bitmask: PFRC2A.PISEL2A \ PSC 2 Input Select for Part A
+ $20 constant PFRC2A_PELEV2A \ PSC 2 Edge Level Selector on I
+ 66 $20 bitmask: PFRC2A.PELEV2A \ PSC 2 Edge Level Selector on I
+ $10 constant PFRC2A_PFLTE2A \ PSC 2 Filter Enable on Input P
+ 66 $10 bitmask: PFRC2A.PFLTE2A \ PSC 2 Filter Enable on Input P
+ $f constant PFRC2A_PRFM2A \ PSC 2 Retrigger and Fault Mode
+ 66 $f bitmask: PFRC2A.PRFM2A \ PSC 2 Retrigger and Fault Mode
+$36 constant PCTL2 \ PSC 2 Control Register
+ $c0 constant PCTL2_PPRE2 \ PSC 2 Prescaler Selects
+ 36 $c0 bitmask: PCTL2.PPRE2 \ PSC 2 Prescaler Selects
+ $20 constant PCTL2_PBFM2 \ Balance Flank Width Modulation
+ 36 $20 bitmask: PCTL2.PBFM2 \ Balance Flank Width Modulation
+ $10 constant PCTL2_PAOC2B \ PSC 2 Asynchronous Output Cont
+ 36 $10 bitmask: PCTL2.PAOC2B \ PSC 2 Asynchronous Output Cont
+ $8 constant PCTL2_PAOC2A \ PSC 2 Asynchronous Output Cont
+ 36 $8 bitmask: PCTL2.PAOC2A \ PSC 2 Asynchronous Output Cont
+ $4 constant PCTL2_PARUN2 \ PSC2 Auto Run
+ 36 $4 bitmask: PCTL2.PARUN2 \ PSC2 Auto Run
+ $2 constant PCTL2_PCCYC2 \ PSC2 Complete Cycle
+ 36 $2 bitmask: PCTL2.PCCYC2 \ PSC2 Complete Cycle
+ $1 constant PCTL2_PRUN2 \ PSC 2 Run
+ 36 $1 bitmask: PCTL2.PRUN2 \ PSC 2 Run
+$35 constant PCNF2 \ PSC 2 Configuration Register
+ $80 constant PCNF2_PFIFTY2 \ PSC 2 Fifty
+ 35 $80 bitmask: PCNF2.PFIFTY2 \ PSC 2 Fifty
+ $40 constant PCNF2_PALOCK2 \ PSC 2 Autolock
+ 35 $40 bitmask: PCNF2.PALOCK2 \ PSC 2 Autolock
+ $20 constant PCNF2_PLOCK2 \ PSC 2 Lock
+ 35 $20 bitmask: PCNF2.PLOCK2 \ PSC 2 Lock
+ $18 constant PCNF2_PMODE2 \ PSC 2 Mode
+ 35 $18 bitmask: PCNF2.PMODE2 \ PSC 2 Mode
+ $4 constant PCNF2_POP2 \ PSC 2 Output Polarity
+ 35 $4 bitmask: PCNF2.POP2 \ PSC 2 Output Polarity
+ $2 constant PCNF2_PCLKSEL2 \ PSC 2 Input Clock Select
+ 35 $2 bitmask: PCNF2.PCLKSEL2 \ PSC 2 Input Clock Select
+ $1 constant PCNF2_POME2 \ PSC 2 Output Matrix Enable
+ 35 $1 bitmask: PCNF2.POME2 \ PSC 2 Output Matrix Enable
+$70 constant PCNFE2 \ PSC 2 Enhanced Configuration R
+ $e0 constant PCNFE2_PASDLK2 \
+ 70 $e0 bitmask: PCNFE2.PASDLK2 \
+ $10 constant PCNFE2_PBFM21 \
+ 70 $10 bitmask: PCNFE2.PBFM21 \
+ $8 constant PCNFE2_PELEV2A1 \
+ 70 $8 bitmask: PCNFE2.PELEV2A1 \
+ $4 constant PCNFE2_PELEV2B1 \
+ 70 $4 bitmask: PCNFE2.PELEV2B1 \
+ $2 constant PCNFE2_PISEL2A1 \
+ 70 $2 bitmask: PCNFE2.PISEL2A1 \
+ $1 constant PCNFE2_PISEL2B1 \
+ 70 $1 bitmask: PCNFE2.PISEL2B1 \
+$48 constant OCR2RB \ Output Compare RB Register
+$46 constant OCR2SB \ Output Compare SB Register
+$4e constant OCR2RA \ Output Compare RA Register
+$64 constant OCR2SA \ Output Compare SA Register
+$6f constant POM2 \ PSC 2 Output Matrix
+ $f0 constant POM2_POMV2B \ Output Matrix Output B Ramps
+ 6f $f0 bitmask: POM2.POMV2B \ Output Matrix Output B Ramps
+ $f constant POM2_POMV2A \ Output Matrix Output A Ramps
+ 6f $f bitmask: POM2.POMV2A \ Output Matrix Output A Ramps
+$6e constant PSOC2 \ PSC2 Synchro and Output Config
+ $c0 constant PSOC2_POS2 \ PSC 2 Output 23 Select
+ 6e $c0 bitmask: PSOC2.POS2 \ PSC 2 Output 23 Select
+ $30 constant PSOC2_PSYNC2 \ Synchronization Out for ADC Se
+ 6e $30 bitmask: PSOC2.PSYNC2 \ Synchronization Out for ADC Se
+ $8 constant PSOC2_POEN2D \ PSCOUT23 Output Enable
+ 6e $8 bitmask: PSOC2.POEN2D \ PSCOUT23 Output Enable
+ $4 constant PSOC2_POEN2B \ PSCOUT21 Output Enable
+ 6e $4 bitmask: PSOC2.POEN2B \ PSCOUT21 Output Enable
+ $2 constant PSOC2_POEN2C \ PSCOUT22 Output Enable
+ 6e $2 bitmask: PSOC2.POEN2C \ PSCOUT22 Output Enable
+ $1 constant PSOC2_POEN2A \ PSCOUT20 Output Enable
+ 6e $1 bitmask: PSOC2.POEN2A \ PSCOUT20 Output Enable
+$33 constant PIM2 \ PSC2 Interrupt Mask Register
+ $20 constant PIM2_PSEIE2 \ PSC 2 Synchro Error Interrupt
+ 33 $20 bitmask: PIM2.PSEIE2 \ PSC 2 Synchro Error Interrupt
+ $10 constant PIM2_PEVE2B \ External Event B Interrupt Ena
+ 33 $10 bitmask: PIM2.PEVE2B \ External Event B Interrupt Ena
+ $8 constant PIM2_PEVE2A \ External Event A Interrupt Ena
+ 33 $8 bitmask: PIM2.PEVE2A \ External Event A Interrupt Ena
+ $2 constant PIM2_PEOEPE2 \ End of Enhanced Cycle Interrup
+ 33 $2 bitmask: PIM2.PEOEPE2 \ End of Enhanced Cycle Interrup
+ $1 constant PIM2_PEOPE2 \ End of Cycle Interrupt Enable
+ 33 $1 bitmask: PIM2.PEOPE2 \ End of Cycle Interrupt Enable
+$34 constant PIFR2 \ PSC2 Interrupt Flag Register
+ $80 constant PIFR2_POAC2B \ PSC 2 Output A Activity
+ 34 $80 bitmask: PIFR2.POAC2B \ PSC 2 Output A Activity
+ $40 constant PIFR2_POAC2A \ PSC 2 Output A Activity
+ 34 $40 bitmask: PIFR2.POAC2A \ PSC 2 Output A Activity
+ $20 constant PIFR2_PSEI2 \ PSC 2 Synchro Error Interrupt
+ 34 $20 bitmask: PIFR2.PSEI2 \ PSC 2 Synchro Error Interrupt
+ $10 constant PIFR2_PEV2B \ External Event B Interrupt
+ 34 $10 bitmask: PIFR2.PEV2B \ External Event B Interrupt
+ $8 constant PIFR2_PEV2A \ External Event A Interrupt
+ 34 $8 bitmask: PIFR2.PEV2A \ External Event A Interrupt
+ $6 constant PIFR2_PRN2 \ Ramp Number
+ 34 $6 bitmask: PIFR2.PRN2 \ Ramp Number
+ $1 constant PIFR2_PEOP2 \ End of PSC2 Interrupt
+ 34 $1 bitmask: PIFR2.PEOP2 \ End of PSC2 Interrupt
+$71 constant PASDLY2 \ Analog Synchronization Delay R
diff --git a/amforth-6.5/avr8/devices/at90pwm161/blocks/SPI.frt b/amforth-6.5/avr8/devices/at90pwm161/blocks/SPI.frt
new file mode 100644
index 0000000..190bab5
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90pwm161/blocks/SPI.frt
@@ -0,0 +1,27 @@
+\ Generated automatically for at90pwm161
+\ #require bitnames.frt
+
+\ SPI
+$37 constant SPCR \ SPI Control Register
+ $80 constant SPCR_SPIE \ SPI Interrupt Enable
+ 37 $80 bitmask: SPCR.SPIE \ SPI Interrupt Enable
+ $40 constant SPCR_SPE \ SPI Enable
+ 37 $40 bitmask: SPCR.SPE \ SPI Enable
+ $20 constant SPCR_DORD \ Data Order
+ 37 $20 bitmask: SPCR.DORD \ Data Order
+ $10 constant SPCR_MSTR \ Master/Slave Select
+ 37 $10 bitmask: SPCR.MSTR \ Master/Slave Select
+ $8 constant SPCR_CPOL \ Clock polarity
+ 37 $8 bitmask: SPCR.CPOL \ Clock polarity
+ $4 constant SPCR_CPHA \ Clock Phase
+ 37 $4 bitmask: SPCR.CPHA \ Clock Phase
+ $3 constant SPCR_SPR \ SPI Clock Rate Selects
+ 37 $3 bitmask: SPCR.SPR \ SPI Clock Rate Selects
+$38 constant SPSR \ SPI Status Register
+ $80 constant SPSR_SPIF \ SPI Interrupt Flag
+ 38 $80 bitmask: SPSR.SPIF \ SPI Interrupt Flag
+ $40 constant SPSR_WCOL \ Write Collision Flag
+ 38 $40 bitmask: SPSR.WCOL \ Write Collision Flag
+ $1 constant SPSR_SPI2X \ Double SPI Speed Bit
+ 38 $1 bitmask: SPSR.SPI2X \ Double SPI Speed Bit
+$56 constant SPDR \ SPI Data Register
diff --git a/amforth-6.5/avr8/devices/at90pwm161/blocks/TIMER_COUNTER_1.frt b/amforth-6.5/avr8/devices/at90pwm161/blocks/TIMER_COUNTER_1.frt
new file mode 100644
index 0000000..3e17b16
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90pwm161/blocks/TIMER_COUNTER_1.frt
@@ -0,0 +1,25 @@
+\ Generated automatically for at90pwm161
+\ #require bitnames.frt
+
+\ TIMER_COUNTER_1
+$21 constant TIMSK1 \ Timer/Counter Interrupt Mask R
+ $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture I
+ 21 $20 bitmask: TIMSK1.ICIE1 \ Timer/Counter1 Input Capture I
+ $1 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interr
+ 21 $1 bitmask: TIMSK1.TOIE1 \ Timer/Counter1 Overflow Interr
+$22 constant TIFR1 \ Timer/Counter Interrupt Flag r
+ $20 constant TIFR1_ICF1 \ Input Capture Flag 1
+ 22 $20 bitmask: TIFR1.ICF1 \ Input Capture Flag 1
+ $1 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
+ 22 $1 bitmask: TIFR1.TOV1 \ Timer/Counter1 Overflow Flag
+$8a constant TCCR1B \ Timer/Counter1 Control Registe
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
+ 8a $80 bitmask: TCCR1B.ICNC1 \ Input Capture 1 Noise Canceler
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ 8a $40 bitmask: TCCR1B.ICES1 \ Input Capture 1 Edge Select
+ $10 constant TCCR1B_WGM13 \ Waveform Generation Mode
+ 8a $10 bitmask: TCCR1B.WGM13 \ Waveform Generation Mode
+ $7 constant TCCR1B_CS1 \ Prescaler source of Timer/Coun
+ 8a $7 bitmask: TCCR1B.CS1 \ Prescaler source of Timer/Coun
+$5a constant TCNT1 \ Timer/Counter1 Bytes
+$8c constant ICR1 \ Timer/Counter1 Input Capture R
diff --git a/amforth-6.5/avr8/devices/at90pwm161/blocks/WATCHDOG.frt b/amforth-6.5/avr8/devices/at90pwm161/blocks/WATCHDOG.frt
new file mode 100644
index 0000000..1772bac
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90pwm161/blocks/WATCHDOG.frt
@@ -0,0 +1,15 @@
+\ Generated automatically for at90pwm161
+\ #require bitnames.frt
+
+\ WATCHDOG
+$82 constant WDTCSR \ Watchdog Timer Control Registe
+ $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Fla
+ 82 $80 bitmask: WDTCSR.WDIF \ Watchdog Timeout Interrupt Fla
+ $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Ena
+ 82 $40 bitmask: WDTCSR.WDIE \ Watchdog Timeout Interrupt Ena
+ $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
+ 82 $27 bitmask: WDTCSR.WDP \ Watchdog Timer Prescaler Bits
+ $10 constant WDTCSR_WDCE \ Watchdog Change Enable
+ 82 $10 bitmask: WDTCSR.WDCE \ Watchdog Change Enable
+ $8 constant WDTCSR_WDE \ Watch Dog Enable
+ 82 $8 bitmask: WDTCSR.WDE \ Watch Dog Enable
diff --git a/amforth-6.5/avr8/devices/at90pwm161/device.asm b/amforth-6.5/avr8/devices/at90pwm161/device.asm
new file mode 100644
index 0000000..8bf16d2
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90pwm161/device.asm
@@ -0,0 +1,52 @@
+; Generated Automatically
+
+.nolist
+ include "pwm161def.inc"
+.list
+FLASHSTART = 0
+FLASHSIZE = 16384
+RAMEND = 1280
+IRAMSTART = 256
+IRAMSIZE = 1024
+EEPROMSIZE = 512
+; Interrupt Vectors
+.overlap
+.org 2
+ rcall isr ; PSC2 Capture Event
+.org 4
+ rcall isr ; PSC2 End Cycle
+.org 6
+ rcall isr ; PSC2 End Of Enhanced Cycle
+.org 8
+ rcall isr ; PSC0 Capture Event
+.org 10
+ rcall isr ; PSC0 End Cycle
+.org 12
+ rcall isr ; PSC0 End Of Enhanced Cycle
+.org 14
+ rcall isr ; Analog Comparator 1
+.org 16
+ rcall isr ; Analog Comparator 2
+.org 18
+ rcall isr ; Analog Comparator 3
+.org 20
+ rcall isr ; External Interrupt Request 0
+.org 22
+ rcall isr ; Timer/Counter1 Capture Event
+.org 24
+ rcall isr ; Timer/Counter1 Overflow
+.org 26
+ rcall isr ; ADC Conversion Complete
+.org 28
+ rcall isr ; External Interrupt Request 1
+.org 30
+ rcall isr ; SPI Serial Transfer Complet
+.org 32
+ rcall isr ; External Interrupt Request 2
+.org 34
+ rcall isr ; Watchdog Timeout Interrupt
+.org 36
+ rcall isr ; EEPROM Ready
+.org 38
+ rcall isr ; Store Program Memory Read
+.nooverlap
diff --git a/amforth-6.5/avr8/devices/at90pwm161/device.frt b/amforth-6.5/avr8/devices/at90pwm161/device.frt
new file mode 100644
index 0000000..00c4728
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90pwm161/device.frt
@@ -0,0 +1,613 @@
+\ Generated Automatically
+
+\ Interrupt Vectors
+#2 constant PSC2_CAPTAddr \ PSC2 Capture Event
+#4 constant PSC2_ECAddr \ PSC2 End Cycle
+#6 constant PSC2_EECAddr \ PSC2 End Of Enhanced Cycle
+#8 constant PSC0_CAPTAddr \ PSC0 Capture Event
+#10 constant PSC0_ECAddr \ PSC0 End Cycle
+#12 constant PSC0_EECAddr \ PSC0 End Of Enhanced Cycle
+#14 constant ANALOG_COMP_1Addr \ Analog Comparator 1
+#16 constant ANALOG_COMP_2Addr \ Analog Comparator 2
+#18 constant ANALOG_COMP_3Addr \ Analog Comparator 3
+#20 constant INT0Addr \ External Interrupt Request 0
+#22 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+#24 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+#26 constant ADCAddr \ ADC Conversion Complete
+#28 constant INT1Addr \ External Interrupt Request 1
+#30 constant SPI_STCAddr \ SPI Serial Transfer Complet
+#32 constant INT2Addr \ External Interrupt Request 2
+#34 constant WDTAddr \ Watchdog Timeout Interrupt
+#36 constant EE_READYAddr \ EEPROM Ready
+#38 constant SPM_READYAddr \ Store Program Memory Read
+\ PORTB
+$25 constant PORTB \ Port B Data Register
+$24 constant DDRB \ Port B Data Direction Register
+$23 constant PINB \ Port B Input Pins
+\ PORTD
+$2b constant PORTD \ Port D Data Register
+$2a constant DDRD \ Port D Data Direction Register
+$29 constant PIND \ Port D Input Pins
+\ DA_CONVERTER
+$59 constant DACH \ DAC Data Register High Byte
+ $ff constant DACH_DACH \ DAC Data Register High Byte Bi
+ 59 $ff bitmask: DACH.DACH \ DAC Data Register High Byte Bi
+$58 constant DACL \ DAC Data Register Low Byte
+ $ff constant DACL_DACL \ DAC Data Register Low Byte Bit
+ 58 $ff bitmask: DACL.DACL \ DAC Data Register Low Byte Bit
+$76 constant DACON \ DAC Control Register
+ $80 constant DACON_DAATE \ DAC Auto Trigger Enable Bit
+ 76 $80 bitmask: DACON.DAATE \ DAC Auto Trigger Enable Bit
+ $70 constant DACON_DATS \ DAC Trigger Selection Bits
+ 76 $70 bitmask: DACON.DATS \ DAC Trigger Selection Bits
+ $4 constant DACON_DALA \ DAC Left Adjust
+ 76 $4 bitmask: DACON.DALA \ DAC Left Adjust
+ $1 constant DACON_DAEN \ DAC Enable Bit
+ 76 $1 bitmask: DACON.DAEN \ DAC Enable Bit
+\ PORTE
+$2e constant PORTE \ Port E Data Register
+$2d constant DDRE \ Port E Data Direction Register
+$2c constant PINE \ Port E Input Pins
+\ SPI
+$37 constant SPCR \ SPI Control Register
+ $80 constant SPCR_SPIE \ SPI Interrupt Enable
+ 37 $80 bitmask: SPCR.SPIE \ SPI Interrupt Enable
+ $40 constant SPCR_SPE \ SPI Enable
+ 37 $40 bitmask: SPCR.SPE \ SPI Enable
+ $20 constant SPCR_DORD \ Data Order
+ 37 $20 bitmask: SPCR.DORD \ Data Order
+ $10 constant SPCR_MSTR \ Master/Slave Select
+ 37 $10 bitmask: SPCR.MSTR \ Master/Slave Select
+ $8 constant SPCR_CPOL \ Clock polarity
+ 37 $8 bitmask: SPCR.CPOL \ Clock polarity
+ $4 constant SPCR_CPHA \ Clock Phase
+ 37 $4 bitmask: SPCR.CPHA \ Clock Phase
+ $3 constant SPCR_SPR \ SPI Clock Rate Selects
+ 37 $3 bitmask: SPCR.SPR \ SPI Clock Rate Selects
+$38 constant SPSR \ SPI Status Register
+ $80 constant SPSR_SPIF \ SPI Interrupt Flag
+ 38 $80 bitmask: SPSR.SPIF \ SPI Interrupt Flag
+ $40 constant SPSR_WCOL \ Write Collision Flag
+ 38 $40 bitmask: SPSR.WCOL \ Write Collision Flag
+ $1 constant SPSR_SPI2X \ Double SPI Speed Bit
+ 38 $1 bitmask: SPSR.SPI2X \ Double SPI Speed Bit
+$56 constant SPDR \ SPI Data Register
+\ WATCHDOG
+$82 constant WDTCSR \ Watchdog Timer Control Registe
+ $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Fla
+ 82 $80 bitmask: WDTCSR.WDIF \ Watchdog Timeout Interrupt Fla
+ $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Ena
+ 82 $40 bitmask: WDTCSR.WDIE \ Watchdog Timeout Interrupt Ena
+ $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
+ 82 $27 bitmask: WDTCSR.WDP \ Watchdog Timer Prescaler Bits
+ $10 constant WDTCSR_WDCE \ Watchdog Change Enable
+ 82 $10 bitmask: WDTCSR.WDCE \ Watchdog Change Enable
+ $8 constant WDTCSR_WDE \ Watch Dog Enable
+ 82 $8 bitmask: WDTCSR.WDE \ Watch Dog Enable
+\ EXTERNAL_INTERRUPT
+$89 constant EICRA \ External Interrupt Control Reg
+ $30 constant EICRA_ISC2 \ External Interrupt Sense Contr
+ 89 $30 bitmask: EICRA.ISC2 \ External Interrupt Sense Contr
+ $c constant EICRA_ISC1 \ External Interrupt Sense Contr
+ 89 $c bitmask: EICRA.ISC1 \ External Interrupt Sense Contr
+ $3 constant EICRA_ISC0 \ External Interrupt Sense Contr
+ 89 $3 bitmask: EICRA.ISC0 \ External Interrupt Sense Contr
+$41 constant EIMSK \ External Interrupt Mask Regist
+ $7 constant EIMSK_INT \ External Interrupt Request 2 E
+ 41 $7 bitmask: EIMSK.INT \ External Interrupt Request 2 E
+$40 constant EIFR \ External Interrupt Flag Regist
+ $7 constant EIFR_INTF \ External Interrupt Flags
+ 40 $7 bitmask: EIFR.INTF \ External Interrupt Flags
+\ AD_CONVERTER
+$28 constant ADMUX \ The ADC multiplexer Selection
+ $c0 constant ADMUX_REFS \ Reference Selection Bits
+ 28 $c0 bitmask: ADMUX.REFS \ Reference Selection Bits
+ $20 constant ADMUX_ADLAR \ Left Adjust Result
+ 28 $20 bitmask: ADMUX.ADLAR \ Left Adjust Result
+ $f constant ADMUX_MUX \ Analog Channel and Gain Select
+ 28 $f bitmask: ADMUX.MUX \ Analog Channel and Gain Select
+$26 constant ADCSRA \ The ADC Control and Status reg
+ $80 constant ADCSRA_ADEN \ ADC Enable
+ 26 $80 bitmask: ADCSRA.ADEN \ ADC Enable
+ $40 constant ADCSRA_ADSC \ ADC Start Conversion
+ 26 $40 bitmask: ADCSRA.ADSC \ ADC Start Conversion
+ $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
+ 26 $20 bitmask: ADCSRA.ADATE \ ADC Auto Trigger Enable
+ $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
+ 26 $10 bitmask: ADCSRA.ADIF \ ADC Interrupt Flag
+ $8 constant ADCSRA_ADIE \ ADC Interrupt Enable
+ 26 $8 bitmask: ADCSRA.ADIE \ ADC Interrupt Enable
+ $7 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
+ 26 $7 bitmask: ADCSRA.ADPS \ ADC Prescaler Select Bits
+$4c constant ADC \ ADC Data Register Bytes
+$27 constant ADCSRB \ ADC Control and Status Registe
+ $80 constant ADCSRB_ADHSM \ ADC High Speed Mode
+ 27 $80 bitmask: ADCSRB.ADHSM \ ADC High Speed Mode
+ $40 constant ADCSRB_ADNCDIS \ ADC Noise Canceller Disable
+ 27 $40 bitmask: ADCSRB.ADNCDIS \ ADC Noise Canceller Disable
+ $10 constant ADCSRB_ADSSEN \ ADC Single Shot Enable on PSC'
+ 27 $10 bitmask: ADCSRB.ADSSEN \ ADC Single Shot Enable on PSC'
+ $f constant ADCSRB_ADTS \ ADC Auto Trigger Sources
+ 27 $f bitmask: ADCSRB.ADTS \ ADC Auto Trigger Sources
+$77 constant DIDR0 \ Digital Input Disable Register
+ $80 constant DIDR0_ADC7D \
+ 77 $80 bitmask: DIDR0.ADC7D \
+ $40 constant DIDR0_ADC6D \ ADC7 Digital input Disable
+ 77 $40 bitmask: DIDR0.ADC6D \ ADC7 Digital input Disable
+ $20 constant DIDR0_ADC5D \ ADC5 Digital input Disable
+ 77 $20 bitmask: DIDR0.ADC5D \ ADC5 Digital input Disable
+ $10 constant DIDR0_ADC4D \ ADC4 Digital input Disable
+ 77 $10 bitmask: DIDR0.ADC4D \ ADC4 Digital input Disable
+ $8 constant DIDR0_ADC3D \ ADC3 Digital input Disable
+ 77 $8 bitmask: DIDR0.ADC3D \ ADC3 Digital input Disable
+ $4 constant DIDR0_ADC2D \ ADC2 Digital input Disable
+ 77 $4 bitmask: DIDR0.ADC2D \ ADC2 Digital input Disable
+ $2 constant DIDR0_ADC1D \ ADC1 Digital input Disable
+ 77 $2 bitmask: DIDR0.ADC1D \ ADC1 Digital input Disable
+ $1 constant DIDR0_ADC0D \ ADC0 Digital input Disable
+ 77 $1 bitmask: DIDR0.ADC0D \ ADC0 Digital input Disable
+$78 constant DIDR1 \ Digital Input Disable Register
+ $8 constant DIDR1_ACMP1MD \
+ 78 $8 bitmask: DIDR1.ACMP1MD \
+ $4 constant DIDR1_AMP0POSD \
+ 78 $4 bitmask: DIDR1.AMP0POSD \
+ $2 constant DIDR1_ADC10D \
+ 78 $2 bitmask: DIDR1.ADC10D \
+ $1 constant DIDR1_ADC9D \
+ 78 $1 bitmask: DIDR1.ADC9D \
+$79 constant AMP0CSR \
+ $80 constant AMP0CSR_AMP0EN \
+ 79 $80 bitmask: AMP0CSR.AMP0EN \
+ $40 constant AMP0CSR_AMP0IS \
+ 79 $40 bitmask: AMP0CSR.AMP0IS \
+ $30 constant AMP0CSR_AMP0G \
+ 79 $30 bitmask: AMP0CSR.AMP0G \
+ $8 constant AMP0CSR_AMP0GS \
+ 79 $8 bitmask: AMP0CSR.AMP0GS \
+ $3 constant AMP0CSR_AMP0TS \
+ 79 $3 bitmask: AMP0CSR.AMP0TS \
+\ ANALOG_COMPARATOR
+$7f constant AC3CON \ Analog Comparator3 Control Reg
+ $80 constant AC3CON_AC3EN \ Analog Comparator3 Enable Bit
+ 7f $80 bitmask: AC3CON.AC3EN \ Analog Comparator3 Enable Bit
+ $40 constant AC3CON_AC3IE \ Analog Comparator 3 Interrupt
+ 7f $40 bitmask: AC3CON.AC3IE \ Analog Comparator 3 Interrupt
+ $30 constant AC3CON_AC3IS \ Analog Comparator 3 Interrupt
+ 7f $30 bitmask: AC3CON.AC3IS \ Analog Comparator 3 Interrupt
+ $8 constant AC3CON_AC3OEA \ Analog Comparator 3 Alternate
+ 7f $8 bitmask: AC3CON.AC3OEA \ Analog Comparator 3 Alternate
+ $7 constant AC3CON_AC3M \ Analog Comparator 3 Multiplexe
+ 7f $7 bitmask: AC3CON.AC3M \ Analog Comparator 3 Multiplexe
+$7d constant AC1CON \ Analog Comparator 1 Control Re
+ $80 constant AC1CON_AC1EN \ Analog Comparator 1 Enable Bit
+ 7d $80 bitmask: AC1CON.AC1EN \ Analog Comparator 1 Enable Bit
+ $40 constant AC1CON_AC1IE \ Analog Comparator 1 Interrupt
+ 7d $40 bitmask: AC1CON.AC1IE \ Analog Comparator 1 Interrupt
+ $30 constant AC1CON_AC1IS \ Analog Comparator 1 Interrupt
+ 7d $30 bitmask: AC1CON.AC1IS \ Analog Comparator 1 Interrupt
+ $7 constant AC1CON_AC1M \ Analog Comparator 1 Multiplexe
+ 7d $7 bitmask: AC1CON.AC1M \ Analog Comparator 1 Multiplexe
+$7e constant AC2CON \ Analog Comparator 2 Control Re
+ $80 constant AC2CON_AC2EN \ Analog Comparator 2 Enable Bit
+ 7e $80 bitmask: AC2CON.AC2EN \ Analog Comparator 2 Enable Bit
+ $40 constant AC2CON_AC2IE \ Analog Comparator 2 Interrupt
+ 7e $40 bitmask: AC2CON.AC2IE \ Analog Comparator 2 Interrupt
+ $30 constant AC2CON_AC2IS \ Analog Comparator 2 Interrupt
+ 7e $30 bitmask: AC2CON.AC2IS \ Analog Comparator 2 Interrupt
+ $7 constant AC2CON_AC2M \ Analog Comparator 2 Multiplexe
+ 7e $7 bitmask: AC2CON.AC2M \ Analog Comparator 2 Multiplexe
+$20 constant ACSR \ Analog Comparator Status Regis
+ $80 constant ACSR_AC3IF \ Analog Comparator 3 Interrupt
+ 20 $80 bitmask: ACSR.AC3IF \ Analog Comparator 3 Interrupt
+ $40 constant ACSR_AC2IF \ Analog Comparator 2 Interrupt
+ 20 $40 bitmask: ACSR.AC2IF \ Analog Comparator 2 Interrupt
+ $20 constant ACSR_AC1IF \ Analog Comparator 1 Interrupt
+ 20 $20 bitmask: ACSR.AC1IF \ Analog Comparator 1 Interrupt
+ $8 constant ACSR_AC3O \ Analog Comparator 3 Output Bit
+ 20 $8 bitmask: ACSR.AC3O \ Analog Comparator 3 Output Bit
+ $4 constant ACSR_AC2O \ Analog Comparator 2 Output Bit
+ 20 $4 bitmask: ACSR.AC2O \ Analog Comparator 2 Output Bit
+ $2 constant ACSR_AC1O \ Analog Comparator 1 Output Bit
+ 20 $2 bitmask: ACSR.AC1O \ Analog Comparator 1 Output Bit
+$7c constant AC3ECON \
+ $20 constant AC3ECON_AC3OI \ Analog Comparator Ouput Invert
+ 7c $20 bitmask: AC3ECON.AC3OI \ Analog Comparator Ouput Invert
+ $10 constant AC3ECON_AC3OE \ Analog Comparator Ouput Enable
+ 7c $10 bitmask: AC3ECON.AC3OE \ Analog Comparator Ouput Enable
+ $7 constant AC3ECON_AC3H \ Analog Comparator Hysteresis S
+ 7c $7 bitmask: AC3ECON.AC3H \ Analog Comparator Hysteresis S
+$7b constant AC2ECON \
+ $20 constant AC2ECON_AC2OI \ Analog Comparator Ouput Invert
+ 7b $20 bitmask: AC2ECON.AC2OI \ Analog Comparator Ouput Invert
+ $10 constant AC2ECON_AC2OE \ Analog Comparator Ouput Enable
+ 7b $10 bitmask: AC2ECON.AC2OE \ Analog Comparator Ouput Enable
+ $7 constant AC2ECON_AC2H \ Analog Comparator Hysteresis S
+ 7b $7 bitmask: AC2ECON.AC2H \ Analog Comparator Hysteresis S
+$7a constant AC1ECON \
+ $20 constant AC1ECON_AC1OI \ Analog Comparator Ouput Invert
+ 7a $20 bitmask: AC1ECON.AC1OI \ Analog Comparator Ouput Invert
+ $10 constant AC1ECON_AC1OE \ Analog Comparator Ouput Enable
+ 7a $10 bitmask: AC1ECON.AC1OE \ Analog Comparator Ouput Enable
+ $8 constant AC1ECON_AC1ICE \ Analog Comparator Interrupt Ca
+ 7a $8 bitmask: AC1ECON.AC1ICE \ Analog Comparator Interrupt Ca
+ $7 constant AC1ECON_AC1H \ Analog Comparator Hysteresis S
+ 7a $7 bitmask: AC1ECON.AC1H \ Analog Comparator Hysteresis S
+\ CPU
+$5f constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ 5f $80 bitmask: SREG.I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ 5f $40 bitmask: SREG.T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ 5f $20 bitmask: SREG.H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ 5f $10 bitmask: SREG.S \ Sign Bit
+ $8 constant SREG_V \ Two's Complement Overflow Flag
+ 5f $8 bitmask: SREG.V \ Two's Complement Overflow Flag
+ $4 constant SREG_N \ Negative Flag
+ 5f $4 bitmask: SREG.N \ Negative Flag
+ $2 constant SREG_Z \ Zero Flag
+ 5f $2 bitmask: SREG.Z \ Zero Flag
+ $1 constant SREG_C \ Carry Flag
+ 5f $1 bitmask: SREG.C \ Carry Flag
+$5d constant SP \ Stack Pointer
+$55 constant MCUCR \ MCU Control Register
+ $10 constant MCUCR_PUD \ Pull-up disable
+ 55 $10 bitmask: MCUCR.PUD \ Pull-up disable
+ $8 constant MCUCR_RSTDIS \ Reset Pin Disable
+ 55 $8 bitmask: MCUCR.RSTDIS \ Reset Pin Disable
+ $4 constant MCUCR_CKRC81 \ Frequency Selection of the Cal
+ 55 $4 bitmask: MCUCR.CKRC81 \ Frequency Selection of the Cal
+ $2 constant MCUCR_IVSEL \ Interrupt Vector Select
+ 55 $2 bitmask: MCUCR.IVSEL \ Interrupt Vector Select
+ $1 constant MCUCR_IVCE \ Interrupt Vector Change Enable
+ 55 $1 bitmask: MCUCR.IVCE \ Interrupt Vector Change Enable
+$54 constant MCUSR \ MCU Status Register
+ $8 constant MCUSR_WDRF \ Watchdog Reset Flag
+ 54 $8 bitmask: MCUSR.WDRF \ Watchdog Reset Flag
+ $4 constant MCUSR_BORF \ Brown-out Reset Flag
+ 54 $4 bitmask: MCUSR.BORF \ Brown-out Reset Flag
+ $2 constant MCUSR_EXTRF \ External Reset Flag
+ 54 $2 bitmask: MCUSR.EXTRF \ External Reset Flag
+ $1 constant MCUSR_PORF \ Power-on reset flag
+ 54 $1 bitmask: MCUSR.PORF \ Power-on reset flag
+$88 constant OSCCAL \ Oscillator Calibration Value
+$83 constant CLKPR \
+ $80 constant CLKPR_CLKPCE \
+ 83 $80 bitmask: CLKPR.CLKPCE \
+ $f constant CLKPR_CLKPS \
+ 83 $f bitmask: CLKPR.CLKPS \
+$53 constant SMCR \ Sleep Mode Control Register
+ $e constant SMCR_SM \ Sleep Mode Select bits
+ 53 $e bitmask: SMCR.SM \ Sleep Mode Select bits
+ $1 constant SMCR_SE \ Sleep Enable
+ 53 $1 bitmask: SMCR.SE \ Sleep Enable
+$3b constant GPIOR2 \ General Purpose IO Register 2
+ $ff constant GPIOR2_GPIOR \ General Purpose IO Register 2
+ 3b $ff bitmask: GPIOR2.GPIOR \ General Purpose IO Register 2
+$3a constant GPIOR1 \ General Purpose IO Register 1
+ $ff constant GPIOR1_GPIOR \ General Purpose IO Register 1
+ 3a $ff bitmask: GPIOR1.GPIOR \ General Purpose IO Register 1
+$39 constant GPIOR0 \ General Purpose IO Register 0
+ $80 constant GPIOR0_GPIOR07 \ General Purpose IO Register 0
+ 39 $80 bitmask: GPIOR0.GPIOR07 \ General Purpose IO Register 0
+ $40 constant GPIOR0_GPIOR06 \ General Purpose IO Register 0
+ 39 $40 bitmask: GPIOR0.GPIOR06 \ General Purpose IO Register 0
+ $20 constant GPIOR0_GPIOR05 \ General Purpose IO Register 0
+ 39 $20 bitmask: GPIOR0.GPIOR05 \ General Purpose IO Register 0
+ $10 constant GPIOR0_GPIOR04 \ General Purpose IO Register 0
+ 39 $10 bitmask: GPIOR0.GPIOR04 \ General Purpose IO Register 0
+ $8 constant GPIOR0_GPIOR03 \ General Purpose IO Register 0
+ 39 $8 bitmask: GPIOR0.GPIOR03 \ General Purpose IO Register 0
+ $4 constant GPIOR0_GPIOR02 \ General Purpose IO Register 0
+ 39 $4 bitmask: GPIOR0.GPIOR02 \ General Purpose IO Register 0
+ $2 constant GPIOR0_GPIOR01 \ General Purpose IO Register 0
+ 39 $2 bitmask: GPIOR0.GPIOR01 \ General Purpose IO Register 0
+ $1 constant GPIOR0_GPIOR00 \ General Purpose IO Register 0
+ 39 $1 bitmask: GPIOR0.GPIOR00 \ General Purpose IO Register 0
+$87 constant PLLCSR \ PLL Control And Status Registe
+ $3c constant PLLCSR_PLLF \
+ 87 $3c bitmask: PLLCSR.PLLF \
+ $2 constant PLLCSR_PLLE \ PLL Enable
+ 87 $2 bitmask: PLLCSR.PLLE \ PLL Enable
+ $1 constant PLLCSR_PLOCK \ PLL Lock Detector
+ 87 $1 bitmask: PLLCSR.PLOCK \ PLL Lock Detector
+$86 constant PRR \ Power Reduction Register
+ $80 constant PRR_PRPSC2 \ Power Reduction PSC2
+ 86 $80 bitmask: PRR.PRPSC2 \ Power Reduction PSC2
+ $20 constant PRR_PRPSCR \ Power Reduction PSC0
+ 86 $20 bitmask: PRR.PRPSCR \ Power Reduction PSC0
+ $10 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
+ 86 $10 bitmask: PRR.PRTIM1 \ Power Reduction Timer/Counter1
+ $4 constant PRR_PRSPI \ Power Reduction Serial Periphe
+ 86 $4 bitmask: PRR.PRSPI \ Power Reduction Serial Periphe
+ $1 constant PRR_PRADC \ Power Reduction ADC
+ 86 $1 bitmask: PRR.PRADC \ Power Reduction ADC
+$84 constant CLKCSR \
+ $80 constant CLKCSR_CLKCCE \ Clock Control Change Enable
+ 84 $80 bitmask: CLKCSR.CLKCCE \ Clock Control Change Enable
+ $10 constant CLKCSR_CLKRDY \ Clock Ready Flag
+ 84 $10 bitmask: CLKCSR.CLKRDY \ Clock Ready Flag
+ $f constant CLKCSR_CLKC \ Clock Control
+ 84 $f bitmask: CLKCSR.CLKC \ Clock Control
+$85 constant CLKSELR \
+ $40 constant CLKSELR_COUT \ Clock OUT
+ 85 $40 bitmask: CLKSELR.COUT \ Clock OUT
+ $30 constant CLKSELR_CSUT \ Clock Start up Time
+ 85 $30 bitmask: CLKSELR.CSUT \ Clock Start up Time
+ $f constant CLKSELR_CKSEL \ Clock Source Select
+ 85 $f bitmask: CLKSELR.CKSEL \ Clock Source Select
+$81 constant BGCCR \ BandGap Current Calibration Re
+ $f constant BGCCR_BGCC \
+ 81 $f bitmask: BGCCR.BGCC \
+$80 constant BGCRR \ BandGap Resistor Calibration R
+ $f constant BGCRR_BGCR \
+ 80 $f bitmask: BGCRR.BGCR \
+\ EEPROM
+$3e constant EEAR \ EEPROM Read/Write Access Byte
+$3d constant EEDR \ EEPROM Data Register
+$3c constant EECR \ EEPROM Control Register
+ $80 constant EECR_NVMBSY \ None Volatile Busy Memory Busy
+ 3c $80 bitmask: EECR.NVMBSY \ None Volatile Busy Memory Busy
+ $40 constant EECR_EEPAGE \ EEPROM Page Access
+ 3c $40 bitmask: EECR.EEPAGE \ EEPROM Page Access
+ $30 constant EECR_EEPM \ EEPROM Programming Mode
+ 3c $30 bitmask: EECR.EEPM \ EEPROM Programming Mode
+ $8 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
+ 3c $8 bitmask: EECR.EERIE \ EEPROM Ready Interrupt Enable
+ $4 constant EECR_EEMWE \ EEPROM Master Write Enable
+ 3c $4 bitmask: EECR.EEMWE \ EEPROM Master Write Enable
+ $2 constant EECR_EEWE \ EEPROM Write Enable
+ 3c $2 bitmask: EECR.EEWE \ EEPROM Write Enable
+ $1 constant EECR_EERE \ EEPROM Read Enable
+ 3c $1 bitmask: EECR.EERE \ EEPROM Read Enable
+\ PSC0
+$68 constant PICR0 \ PSC 0 Input Capture Register
+$63 constant PFRC0B \ PSC 0 Input B Control
+ $80 constant PFRC0B_PCAE0B \ PSC 0 Capture Enable Input Par
+ 63 $80 bitmask: PFRC0B.PCAE0B \ PSC 0 Capture Enable Input Par
+ $40 constant PFRC0B_PISEL0B \ PSC 0 Input Select for Part B
+ 63 $40 bitmask: PFRC0B.PISEL0B \ PSC 0 Input Select for Part B
+ $20 constant PFRC0B_PELEV0B \ PSC 0 Edge Level Selector on I
+ 63 $20 bitmask: PFRC0B.PELEV0B \ PSC 0 Edge Level Selector on I
+ $10 constant PFRC0B_PFLTE0B \ PSC 0 Filter Enable on Input P
+ 63 $10 bitmask: PFRC0B.PFLTE0B \ PSC 0 Filter Enable on Input P
+ $f constant PFRC0B_PRFM0B \ PSC 0 Retrigger and Fault Mode
+ 63 $f bitmask: PFRC0B.PRFM0B \ PSC 0 Retrigger and Fault Mode
+$62 constant PFRC0A \ PSC 0 Input A Control
+ $80 constant PFRC0A_PCAE0A \ PSC 0 Capture Enable Input Par
+ 62 $80 bitmask: PFRC0A.PCAE0A \ PSC 0 Capture Enable Input Par
+ $40 constant PFRC0A_PISEL0A \ PSC 0 Input Select for Part A
+ 62 $40 bitmask: PFRC0A.PISEL0A \ PSC 0 Input Select for Part A
+ $20 constant PFRC0A_PELEV0A \ PSC 0 Edge Level Selector on I
+ 62 $20 bitmask: PFRC0A.PELEV0A \ PSC 0 Edge Level Selector on I
+ $10 constant PFRC0A_PFLTE0A \ PSC 0 Filter Enable on Input P
+ 62 $10 bitmask: PFRC0A.PFLTE0A \ PSC 0 Filter Enable on Input P
+ $f constant PFRC0A_PRFM0A \ PSC 0 Retrigger and Fault Mode
+ 62 $f bitmask: PFRC0A.PRFM0A \ PSC 0 Retrigger and Fault Mode
+$32 constant PCTL0 \ PSC 0 Control Register
+ $c0 constant PCTL0_PPRE0 \ PSC 0 Prescaler Selects
+ 32 $c0 bitmask: PCTL0.PPRE0 \ PSC 0 Prescaler Selects
+ $24 constant PCTL0_PBFM0 \ PSC 0 Balance Flank Width Modu
+ 32 $24 bitmask: PCTL0.PBFM0 \ PSC 0 Balance Flank Width Modu
+ $10 constant PCTL0_PAOC0B \ PSC 0 Asynchronous Output Cont
+ 32 $10 bitmask: PCTL0.PAOC0B \ PSC 0 Asynchronous Output Cont
+ $8 constant PCTL0_PAOC0A \ PSC 0 Asynchronous Output Cont
+ 32 $8 bitmask: PCTL0.PAOC0A \ PSC 0 Asynchronous Output Cont
+ $2 constant PCTL0_PCCYC0 \ PSC0 Complete Cycle
+ 32 $2 bitmask: PCTL0.PCCYC0 \ PSC0 Complete Cycle
+ $1 constant PCTL0_PRUN0 \ PSC 0 Run
+ 32 $1 bitmask: PCTL0.PRUN0 \ PSC 0 Run
+$31 constant PCNF0 \ PSC 0 Configuration Register
+ $80 constant PCNF0_PFIFTY0 \ PSC 0 Fifty
+ 31 $80 bitmask: PCNF0.PFIFTY0 \ PSC 0 Fifty
+ $40 constant PCNF0_PALOCK0 \ PSC 0 Autolock
+ 31 $40 bitmask: PCNF0.PALOCK0 \ PSC 0 Autolock
+ $20 constant PCNF0_PLOCK0 \ PSC 0 Lock
+ 31 $20 bitmask: PCNF0.PLOCK0 \ PSC 0 Lock
+ $18 constant PCNF0_PMODE0 \ PSC 0 Mode
+ 31 $18 bitmask: PCNF0.PMODE0 \ PSC 0 Mode
+ $4 constant PCNF0_POP0 \ PSC 0 Output Polarity
+ 31 $4 bitmask: PCNF0.POP0 \ PSC 0 Output Polarity
+ $2 constant PCNF0_PCLKSEL0 \ PSC 0 Input Clock Select
+ 31 $2 bitmask: PCNF0.PCLKSEL0 \ PSC 0 Input Clock Select
+$44 constant OCR0RB \ Output Compare RB Register
+$42 constant OCR0SB \ Output Compare SB Register
+$4a constant OCR0RA \ Output Compare RA Register
+$60 constant OCR0SA \ Output Compare SA Register
+$6a constant PSOC0 \ PSC0 Synchro and Output Config
+ $80 constant PSOC0_PISEL0A1 \ PSC Input Select
+ 6a $80 bitmask: PSOC0.PISEL0A1 \ PSC Input Select
+ $40 constant PSOC0_PISEL0B1 \ PSC Input Select
+ 6a $40 bitmask: PSOC0.PISEL0B1 \ PSC Input Select
+ $30 constant PSOC0_PSYNC0 \ Synchronisation out for ADC se
+ 6a $30 bitmask: PSOC0.PSYNC0 \ Synchronisation out for ADC se
+ $4 constant PSOC0_POEN0B \ PSCOUT01 Output Enable
+ 6a $4 bitmask: PSOC0.POEN0B \ PSCOUT01 Output Enable
+ $1 constant PSOC0_POEN0A \ PSCOUT00 Output Enable
+ 6a $1 bitmask: PSOC0.POEN0A \ PSCOUT00 Output Enable
+$2f constant PIM0 \ PSC0 Interrupt Mask Register
+ $10 constant PIM0_PEVE0B \ External Event B Interrupt Ena
+ 2f $10 bitmask: PIM0.PEVE0B \ External Event B Interrupt Ena
+ $8 constant PIM0_PEVE0A \ External Event A Interrupt Ena
+ 2f $8 bitmask: PIM0.PEVE0A \ External Event A Interrupt Ena
+ $2 constant PIM0_PEOEPE0 \ End of Enhanced Cycle Enable
+ 2f $2 bitmask: PIM0.PEOEPE0 \ End of Enhanced Cycle Enable
+ $1 constant PIM0_PEOPE0 \ End of Cycle Interrupt Enable
+ 2f $1 bitmask: PIM0.PEOPE0 \ End of Cycle Interrupt Enable
+$30 constant PIFR0 \ PSC0 Interrupt Flag Register
+ $80 constant PIFR0_POAC0B \ PSC 0 Output A Activity
+ 30 $80 bitmask: PIFR0.POAC0B \ PSC 0 Output A Activity
+ $40 constant PIFR0_POAC0A \ PSC 0 Output A Activity
+ 30 $40 bitmask: PIFR0.POAC0A \ PSC 0 Output A Activity
+ $10 constant PIFR0_PEV0B \ External Event B Interrupt
+ 30 $10 bitmask: PIFR0.PEV0B \ External Event B Interrupt
+ $8 constant PIFR0_PEV0A \ External Event A Interrupt
+ 30 $8 bitmask: PIFR0.PEV0A \ External Event A Interrupt
+ $6 constant PIFR0_PRN0 \ Ramp Number
+ 30 $6 bitmask: PIFR0.PRN0 \ Ramp Number
+ $1 constant PIFR0_PEOP0 \ End of PSC0 Interrupt
+ 30 $1 bitmask: PIFR0.PEOP0 \ End of PSC0 Interrupt
+\ PSC2
+$6d constant PICR2H \ PSC 2 Input Capture Register H
+ $80 constant PICR2H_PCST2 \ PSC 2 Capture Software Trigger
+ 6d $80 bitmask: PICR2H.PCST2 \ PSC 2 Capture Software Trigger
+ $c constant PICR2H_PICR21 \
+ 6d $c bitmask: PICR2H.PICR21 \
+ $3 constant PICR2H_PICR2 \
+ 6d $3 bitmask: PICR2H.PICR2 \
+$6c constant PICR2L \ PSC 2 Input Capture Register L
+$67 constant PFRC2B \ PSC 2 Input B Control
+ $80 constant PFRC2B_PCAE2B \ PSC 2 Capture Enable Input Par
+ 67 $80 bitmask: PFRC2B.PCAE2B \ PSC 2 Capture Enable Input Par
+ $40 constant PFRC2B_PISEL2B \ PSC 2 Input Select for Part B
+ 67 $40 bitmask: PFRC2B.PISEL2B \ PSC 2 Input Select for Part B
+ $20 constant PFRC2B_PELEV2B \ PSC 2 Edge Level Selector on I
+ 67 $20 bitmask: PFRC2B.PELEV2B \ PSC 2 Edge Level Selector on I
+ $10 constant PFRC2B_PFLTE2B \ PSC 2 Filter Enable on Input P
+ 67 $10 bitmask: PFRC2B.PFLTE2B \ PSC 2 Filter Enable on Input P
+ $f constant PFRC2B_PRFM2B \ PSC 2 Retrigger and Fault Mode
+ 67 $f bitmask: PFRC2B.PRFM2B \ PSC 2 Retrigger and Fault Mode
+$66 constant PFRC2A \ PSC 2 Input B Control
+ $80 constant PFRC2A_PCAE2A \ PSC 2 Capture Enable Input Par
+ 66 $80 bitmask: PFRC2A.PCAE2A \ PSC 2 Capture Enable Input Par
+ $40 constant PFRC2A_PISEL2A \ PSC 2 Input Select for Part A
+ 66 $40 bitmask: PFRC2A.PISEL2A \ PSC 2 Input Select for Part A
+ $20 constant PFRC2A_PELEV2A \ PSC 2 Edge Level Selector on I
+ 66 $20 bitmask: PFRC2A.PELEV2A \ PSC 2 Edge Level Selector on I
+ $10 constant PFRC2A_PFLTE2A \ PSC 2 Filter Enable on Input P
+ 66 $10 bitmask: PFRC2A.PFLTE2A \ PSC 2 Filter Enable on Input P
+ $f constant PFRC2A_PRFM2A \ PSC 2 Retrigger and Fault Mode
+ 66 $f bitmask: PFRC2A.PRFM2A \ PSC 2 Retrigger and Fault Mode
+$36 constant PCTL2 \ PSC 2 Control Register
+ $c0 constant PCTL2_PPRE2 \ PSC 2 Prescaler Selects
+ 36 $c0 bitmask: PCTL2.PPRE2 \ PSC 2 Prescaler Selects
+ $20 constant PCTL2_PBFM2 \ Balance Flank Width Modulation
+ 36 $20 bitmask: PCTL2.PBFM2 \ Balance Flank Width Modulation
+ $10 constant PCTL2_PAOC2B \ PSC 2 Asynchronous Output Cont
+ 36 $10 bitmask: PCTL2.PAOC2B \ PSC 2 Asynchronous Output Cont
+ $8 constant PCTL2_PAOC2A \ PSC 2 Asynchronous Output Cont
+ 36 $8 bitmask: PCTL2.PAOC2A \ PSC 2 Asynchronous Output Cont
+ $4 constant PCTL2_PARUN2 \ PSC2 Auto Run
+ 36 $4 bitmask: PCTL2.PARUN2 \ PSC2 Auto Run
+ $2 constant PCTL2_PCCYC2 \ PSC2 Complete Cycle
+ 36 $2 bitmask: PCTL2.PCCYC2 \ PSC2 Complete Cycle
+ $1 constant PCTL2_PRUN2 \ PSC 2 Run
+ 36 $1 bitmask: PCTL2.PRUN2 \ PSC 2 Run
+$35 constant PCNF2 \ PSC 2 Configuration Register
+ $80 constant PCNF2_PFIFTY2 \ PSC 2 Fifty
+ 35 $80 bitmask: PCNF2.PFIFTY2 \ PSC 2 Fifty
+ $40 constant PCNF2_PALOCK2 \ PSC 2 Autolock
+ 35 $40 bitmask: PCNF2.PALOCK2 \ PSC 2 Autolock
+ $20 constant PCNF2_PLOCK2 \ PSC 2 Lock
+ 35 $20 bitmask: PCNF2.PLOCK2 \ PSC 2 Lock
+ $18 constant PCNF2_PMODE2 \ PSC 2 Mode
+ 35 $18 bitmask: PCNF2.PMODE2 \ PSC 2 Mode
+ $4 constant PCNF2_POP2 \ PSC 2 Output Polarity
+ 35 $4 bitmask: PCNF2.POP2 \ PSC 2 Output Polarity
+ $2 constant PCNF2_PCLKSEL2 \ PSC 2 Input Clock Select
+ 35 $2 bitmask: PCNF2.PCLKSEL2 \ PSC 2 Input Clock Select
+ $1 constant PCNF2_POME2 \ PSC 2 Output Matrix Enable
+ 35 $1 bitmask: PCNF2.POME2 \ PSC 2 Output Matrix Enable
+$70 constant PCNFE2 \ PSC 2 Enhanced Configuration R
+ $e0 constant PCNFE2_PASDLK2 \
+ 70 $e0 bitmask: PCNFE2.PASDLK2 \
+ $10 constant PCNFE2_PBFM21 \
+ 70 $10 bitmask: PCNFE2.PBFM21 \
+ $8 constant PCNFE2_PELEV2A1 \
+ 70 $8 bitmask: PCNFE2.PELEV2A1 \
+ $4 constant PCNFE2_PELEV2B1 \
+ 70 $4 bitmask: PCNFE2.PELEV2B1 \
+ $2 constant PCNFE2_PISEL2A1 \
+ 70 $2 bitmask: PCNFE2.PISEL2A1 \
+ $1 constant PCNFE2_PISEL2B1 \
+ 70 $1 bitmask: PCNFE2.PISEL2B1 \
+$48 constant OCR2RB \ Output Compare RB Register
+$46 constant OCR2SB \ Output Compare SB Register
+$4e constant OCR2RA \ Output Compare RA Register
+$64 constant OCR2SA \ Output Compare SA Register
+$6f constant POM2 \ PSC 2 Output Matrix
+ $f0 constant POM2_POMV2B \ Output Matrix Output B Ramps
+ 6f $f0 bitmask: POM2.POMV2B \ Output Matrix Output B Ramps
+ $f constant POM2_POMV2A \ Output Matrix Output A Ramps
+ 6f $f bitmask: POM2.POMV2A \ Output Matrix Output A Ramps
+$6e constant PSOC2 \ PSC2 Synchro and Output Config
+ $c0 constant PSOC2_POS2 \ PSC 2 Output 23 Select
+ 6e $c0 bitmask: PSOC2.POS2 \ PSC 2 Output 23 Select
+ $30 constant PSOC2_PSYNC2 \ Synchronization Out for ADC Se
+ 6e $30 bitmask: PSOC2.PSYNC2 \ Synchronization Out for ADC Se
+ $8 constant PSOC2_POEN2D \ PSCOUT23 Output Enable
+ 6e $8 bitmask: PSOC2.POEN2D \ PSCOUT23 Output Enable
+ $4 constant PSOC2_POEN2B \ PSCOUT21 Output Enable
+ 6e $4 bitmask: PSOC2.POEN2B \ PSCOUT21 Output Enable
+ $2 constant PSOC2_POEN2C \ PSCOUT22 Output Enable
+ 6e $2 bitmask: PSOC2.POEN2C \ PSCOUT22 Output Enable
+ $1 constant PSOC2_POEN2A \ PSCOUT20 Output Enable
+ 6e $1 bitmask: PSOC2.POEN2A \ PSCOUT20 Output Enable
+$33 constant PIM2 \ PSC2 Interrupt Mask Register
+ $20 constant PIM2_PSEIE2 \ PSC 2 Synchro Error Interrupt
+ 33 $20 bitmask: PIM2.PSEIE2 \ PSC 2 Synchro Error Interrupt
+ $10 constant PIM2_PEVE2B \ External Event B Interrupt Ena
+ 33 $10 bitmask: PIM2.PEVE2B \ External Event B Interrupt Ena
+ $8 constant PIM2_PEVE2A \ External Event A Interrupt Ena
+ 33 $8 bitmask: PIM2.PEVE2A \ External Event A Interrupt Ena
+ $2 constant PIM2_PEOEPE2 \ End of Enhanced Cycle Interrup
+ 33 $2 bitmask: PIM2.PEOEPE2 \ End of Enhanced Cycle Interrup
+ $1 constant PIM2_PEOPE2 \ End of Cycle Interrupt Enable
+ 33 $1 bitmask: PIM2.PEOPE2 \ End of Cycle Interrupt Enable
+$34 constant PIFR2 \ PSC2 Interrupt Flag Register
+ $80 constant PIFR2_POAC2B \ PSC 2 Output A Activity
+ 34 $80 bitmask: PIFR2.POAC2B \ PSC 2 Output A Activity
+ $40 constant PIFR2_POAC2A \ PSC 2 Output A Activity
+ 34 $40 bitmask: PIFR2.POAC2A \ PSC 2 Output A Activity
+ $20 constant PIFR2_PSEI2 \ PSC 2 Synchro Error Interrupt
+ 34 $20 bitmask: PIFR2.PSEI2 \ PSC 2 Synchro Error Interrupt
+ $10 constant PIFR2_PEV2B \ External Event B Interrupt
+ 34 $10 bitmask: PIFR2.PEV2B \ External Event B Interrupt
+ $8 constant PIFR2_PEV2A \ External Event A Interrupt
+ 34 $8 bitmask: PIFR2.PEV2A \ External Event A Interrupt
+ $6 constant PIFR2_PRN2 \ Ramp Number
+ 34 $6 bitmask: PIFR2.PRN2 \ Ramp Number
+ $1 constant PIFR2_PEOP2 \ End of PSC2 Interrupt
+ 34 $1 bitmask: PIFR2.PEOP2 \ End of PSC2 Interrupt
+$71 constant PASDLY2 \ Analog Synchronization Delay R
+\ TIMER_COUNTER_1
+$21 constant TIMSK1 \ Timer/Counter Interrupt Mask R
+ $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture I
+ 21 $20 bitmask: TIMSK1.ICIE1 \ Timer/Counter1 Input Capture I
+ $1 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interr
+ 21 $1 bitmask: TIMSK1.TOIE1 \ Timer/Counter1 Overflow Interr
+$22 constant TIFR1 \ Timer/Counter Interrupt Flag r
+ $20 constant TIFR1_ICF1 \ Input Capture Flag 1
+ 22 $20 bitmask: TIFR1.ICF1 \ Input Capture Flag 1
+ $1 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
+ 22 $1 bitmask: TIFR1.TOV1 \ Timer/Counter1 Overflow Flag
+$8a constant TCCR1B \ Timer/Counter1 Control Registe
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
+ 8a $80 bitmask: TCCR1B.ICNC1 \ Input Capture 1 Noise Canceler
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ 8a $40 bitmask: TCCR1B.ICES1 \ Input Capture 1 Edge Select
+ $10 constant TCCR1B_WGM13 \ Waveform Generation Mode
+ 8a $10 bitmask: TCCR1B.WGM13 \ Waveform Generation Mode
+ $7 constant TCCR1B_CS1 \ Prescaler source of Timer/Coun
+ 8a $7 bitmask: TCCR1B.CS1 \ Prescaler source of Timer/Coun
+$5a constant TCNT1 \ Timer/Counter1 Bytes
+$8c constant ICR1 \ Timer/Counter1 Input Capture R
+\ BOOT_LOAD
+$57 constant SPMCSR \ Store Program Memory Control R
+ $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
+ 57 $80 bitmask: SPMCSR.SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
+ 57 $40 bitmask: SPMCSR.RWWSB \ Read While Write Section Busy
+ $20 constant SPMCSR_SIGRD \ Signature Row Read
+ 57 $20 bitmask: SPMCSR.SIGRD \ Signature Row Read
+ $10 constant SPMCSR_RWWSRE \ Read While Write section read
+ 57 $10 bitmask: SPMCSR.RWWSRE \ Read While Write section read
+ $8 constant SPMCSR_BLBSET \ Boot Lock Bit Set
+ 57 $8 bitmask: SPMCSR.BLBSET \ Boot Lock Bit Set
+ $4 constant SPMCSR_PGWRT \ Page Write
+ 57 $4 bitmask: SPMCSR.PGWRT \ Page Write
+ $2 constant SPMCSR_PGERS \ Page Erase
+ 57 $2 bitmask: SPMCSR.PGERS \ Page Erase
+ $1 constant SPMCSR_SPMEN \ Store Program Memory Enable
+ 57 $1 bitmask: SPMCSR.SPMEN \ Store Program Memory Enable
diff --git a/amforth-6.5/avr8/devices/at90pwm161/device.py b/amforth-6.5/avr8/devices/at90pwm161/device.py
new file mode 100644
index 0000000..6a000b9
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90pwm161/device.py
@@ -0,0 +1,389 @@
+# Generated Automatically
+
+# Partname AT90PWM161
+
+MCUREGS = {
+# Interrupt Vectors
+ 'PSC2_CAPTAddr' : '#2', # PSC2 Capture Event
+ 'PSC2_ECAddr' : '#4', # PSC2 End Cycle
+ 'PSC2_EECAddr' : '#6', # PSC2 End Of Enhanced Cycle
+ 'PSC0_CAPTAddr' : '#8', # PSC0 Capture Event
+ 'PSC0_ECAddr' : '#10', # PSC0 End Cycle
+ 'PSC0_EECAddr' : '#12', # PSC0 End Of Enhanced Cycle
+ 'ANALOG_COMP_1Addr' : '#14', # Analog Comparator 1
+ 'ANALOG_COMP_2Addr' : '#16', # Analog Comparator 2
+ 'ANALOG_COMP_3Addr' : '#18', # Analog Comparator 3
+ 'INT0Addr' : '#20', # External Interrupt Request 0
+ 'TIMER1_CAPTAddr' : '#22', # Timer/Counter1 Capture Event
+ 'TIMER1_OVFAddr' : '#24', # Timer/Counter1 Overflow
+ 'ADCAddr' : '#26', # ADC Conversion Complete
+ 'INT1Addr' : '#28', # External Interrupt Request 1
+ 'SPI_STCAddr' : '#30', # SPI Serial Transfer Complet
+ 'INT2Addr' : '#32', # External Interrupt Request 2
+ 'WDTAddr' : '#34', # Watchdog Timeout Interrupt
+ 'EE_READYAddr' : '#36', # EEPROM Ready
+ 'SPM_READYAddr' : '#38', # Store Program Memory Read
+
+# Module PORTB
+ 'PORTB' : '$25', # Port B Data Register
+ 'DDRB' : '$24', # Port B Data Direction Register
+ 'PINB' : '$23', # Port B Input Pins
+
+# Module PORTD
+ 'PORTD' : '$2b', # Port D Data Register
+ 'DDRD' : '$2a', # Port D Data Direction Register
+ 'PIND' : '$29', # Port D Input Pins
+
+# Module DA_CONVERTER
+ 'DACH' : '$59', # DAC Data Register High Byte
+ 'DACH_DACH': '$ff', # DAC Data Register High Byte Bi
+ 'DACL' : '$58', # DAC Data Register Low Byte
+ 'DACL_DACL': '$ff', # DAC Data Register Low Byte Bit
+ 'DACON' : '$76', # DAC Control Register
+ 'DACON_DAATE': '$80', # DAC Auto Trigger Enable Bit
+ 'DACON_DATS': '$70', # DAC Trigger Selection Bits
+ 'DACON_DALA': '$4', # DAC Left Adjust
+ 'DACON_DAEN': '$1', # DAC Enable Bit
+
+# Module PORTE
+ 'PORTE' : '$2e', # Port E Data Register
+ 'DDRE' : '$2d', # Port E Data Direction Register
+ 'PINE' : '$2c', # Port E Input Pins
+
+# Module SPI
+ 'SPCR' : '$37', # SPI Control Register
+ 'SPCR_SPIE': '$80', # SPI Interrupt Enable
+ 'SPCR_SPE': '$40', # SPI Enable
+ 'SPCR_DORD': '$20', # Data Order
+ 'SPCR_MSTR': '$10', # Master/Slave Select
+ 'SPCR_CPOL': '$8', # Clock polarity
+ 'SPCR_CPHA': '$4', # Clock Phase
+ 'SPCR_SPR': '$3', # SPI Clock Rate Selects
+ 'SPSR' : '$38', # SPI Status Register
+ 'SPSR_SPIF': '$80', # SPI Interrupt Flag
+ 'SPSR_WCOL': '$40', # Write Collision Flag
+ 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
+ 'SPDR' : '$56', # SPI Data Register
+
+# Module WATCHDOG
+ 'WDTCSR' : '$82', # Watchdog Timer Control Registe
+ 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
+ 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
+ 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
+ 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
+ 'WDTCSR_WDE': '$8', # Watch Dog Enable
+
+# Module EXTERNAL_INTERRUPT
+ 'EICRA' : '$89', # External Interrupt Control Reg
+ 'EICRA_ISC2': '$30', # External Interrupt Sense Contr
+ 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
+ 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
+ 'EIMSK' : '$41', # External Interrupt Mask Regist
+ 'EIMSK_INT': '$7', # External Interrupt Request 2 E
+ 'EIFR' : '$40', # External Interrupt Flag Regist
+ 'EIFR_INTF': '$7', # External Interrupt Flags
+
+# Module AD_CONVERTER
+ 'ADMUX' : '$28', # The ADC multiplexer Selection
+ 'ADMUX_REFS': '$c0', # Reference Selection Bits
+ 'ADMUX_ADLAR': '$20', # Left Adjust Result
+ 'ADMUX_MUX': '$f', # Analog Channel and Gain Select
+ 'ADCSRA' : '$26', # The ADC Control and Status reg
+ 'ADCSRA_ADEN': '$80', # ADC Enable
+ 'ADCSRA_ADSC': '$40', # ADC Start Conversion
+ 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
+ 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
+ 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
+ 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
+ 'ADC' : '$4c', # ADC Data Register Bytes
+ 'ADCSRB' : '$27', # ADC Control and Status Registe
+ 'ADCSRB_ADHSM': '$80', # ADC High Speed Mode
+ 'ADCSRB_ADNCDIS': '$40', # ADC Noise Canceller Disable
+ 'ADCSRB_ADSSEN': '$10', # ADC Single Shot Enable on PSC'
+ 'ADCSRB_ADTS': '$f', # ADC Auto Trigger Sources
+ 'DIDR0' : '$77', # Digital Input Disable Register
+ 'DIDR0_ADC7D': '$80', #
+ 'DIDR0_ADC6D': '$40', # ADC7 Digital input Disable
+ 'DIDR0_ADC5D': '$20', # ADC5 Digital input Disable
+ 'DIDR0_ADC4D': '$10', # ADC4 Digital input Disable
+ 'DIDR0_ADC3D': '$8', # ADC3 Digital input Disable
+ 'DIDR0_ADC2D': '$4', # ADC2 Digital input Disable
+ 'DIDR0_ADC1D': '$2', # ADC1 Digital input Disable
+ 'DIDR0_ADC0D': '$1', # ADC0 Digital input Disable
+ 'DIDR1' : '$78', # Digital Input Disable Register
+ 'DIDR1_ACMP1MD': '$8', #
+ 'DIDR1_AMP0POSD': '$4', #
+ 'DIDR1_ADC10D': '$2', #
+ 'DIDR1_ADC9D': '$1', #
+ 'AMP0CSR' : '$79', #
+ 'AMP0CSR_AMP0EN': '$80', #
+ 'AMP0CSR_AMP0IS': '$40', #
+ 'AMP0CSR_AMP0G': '$30', #
+ 'AMP0CSR_AMP0GS': '$8', #
+ 'AMP0CSR_AMP0TS': '$3', #
+
+# Module ANALOG_COMPARATOR
+ 'AC3CON' : '$7f', # Analog Comparator3 Control Reg
+ 'AC3CON_AC3EN': '$80', # Analog Comparator3 Enable Bit
+ 'AC3CON_AC3IE': '$40', # Analog Comparator 3 Interrupt
+ 'AC3CON_AC3IS': '$30', # Analog Comparator 3 Interrupt
+ 'AC3CON_AC3OEA': '$8', # Analog Comparator 3 Alternate
+ 'AC3CON_AC3M': '$7', # Analog Comparator 3 Multiplexe
+ 'AC1CON' : '$7d', # Analog Comparator 1 Control Re
+ 'AC1CON_AC1EN': '$80', # Analog Comparator 1 Enable Bit
+ 'AC1CON_AC1IE': '$40', # Analog Comparator 1 Interrupt
+ 'AC1CON_AC1IS': '$30', # Analog Comparator 1 Interrupt
+ 'AC1CON_AC1M': '$7', # Analog Comparator 1 Multiplexe
+ 'AC2CON' : '$7e', # Analog Comparator 2 Control Re
+ 'AC2CON_AC2EN': '$80', # Analog Comparator 2 Enable Bit
+ 'AC2CON_AC2IE': '$40', # Analog Comparator 2 Interrupt
+ 'AC2CON_AC2IS': '$30', # Analog Comparator 2 Interrupt
+ 'AC2CON_AC2M': '$7', # Analog Comparator 2 Multiplexe
+ 'ACSR' : '$20', # Analog Comparator Status Regis
+ 'ACSR_AC3IF': '$80', # Analog Comparator 3 Interrupt
+ 'ACSR_AC2IF': '$40', # Analog Comparator 2 Interrupt
+ 'ACSR_AC1IF': '$20', # Analog Comparator 1 Interrupt
+ 'ACSR_AC3O': '$8', # Analog Comparator 3 Output Bit
+ 'ACSR_AC2O': '$4', # Analog Comparator 2 Output Bit
+ 'ACSR_AC1O': '$2', # Analog Comparator 1 Output Bit
+ 'AC3ECON' : '$7c', #
+ 'AC3ECON_AC3OI': '$20', # Analog Comparator Ouput Invert
+ 'AC3ECON_AC3OE': '$10', # Analog Comparator Ouput Enable
+ 'AC3ECON_AC3H': '$7', # Analog Comparator Hysteresis S
+ 'AC2ECON' : '$7b', #
+ 'AC2ECON_AC2OI': '$20', # Analog Comparator Ouput Invert
+ 'AC2ECON_AC2OE': '$10', # Analog Comparator Ouput Enable
+ 'AC2ECON_AC2H': '$7', # Analog Comparator Hysteresis S
+ 'AC1ECON' : '$7a', #
+ 'AC1ECON_AC1OI': '$20', # Analog Comparator Ouput Invert
+ 'AC1ECON_AC1OE': '$10', # Analog Comparator Ouput Enable
+ 'AC1ECON_AC1ICE': '$8', # Analog Comparator Interrupt Ca
+ 'AC1ECON_AC1H': '$7', # Analog Comparator Hysteresis S
+
+# Module CPU
+ 'SREG' : '$5f', # Status Register
+ 'SREG_I': '$80', # Global Interrupt Enable
+ 'SREG_T': '$40', # Bit Copy Storage
+ 'SREG_H': '$20', # Half Carry Flag
+ 'SREG_S': '$10', # Sign Bit
+ 'SREG_V': '$8', # Two's Complement Overflow Flag
+ 'SREG_N': '$4', # Negative Flag
+ 'SREG_Z': '$2', # Zero Flag
+ 'SREG_C': '$1', # Carry Flag
+ 'SP' : '$5d', # Stack Pointer
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_PUD': '$10', # Pull-up disable
+ 'MCUCR_RSTDIS': '$8', # Reset Pin Disable
+ 'MCUCR_CKRC81': '$4', # Frequency Selection of the Cal
+ 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
+ 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
+ 'MCUSR_BORF': '$4', # Brown-out Reset Flag
+ 'MCUSR_EXTRF': '$2', # External Reset Flag
+ 'MCUSR_PORF': '$1', # Power-on reset flag
+ 'OSCCAL' : '$88', # Oscillator Calibration Value
+ 'CLKPR' : '$83', #
+ 'CLKPR_CLKPCE': '$80', #
+ 'CLKPR_CLKPS': '$f', #
+ 'SMCR' : '$53', # Sleep Mode Control Register
+ 'SMCR_SM': '$e', # Sleep Mode Select bits
+ 'SMCR_SE': '$1', # Sleep Enable
+ 'GPIOR2' : '$3b', # General Purpose IO Register 2
+ 'GPIOR2_GPIOR': '$ff', # General Purpose IO Register 2
+ 'GPIOR1' : '$3a', # General Purpose IO Register 1
+ 'GPIOR1_GPIOR': '$ff', # General Purpose IO Register 1
+ 'GPIOR0' : '$39', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR07': '$80', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR06': '$40', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR05': '$20', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR04': '$10', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR03': '$8', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR02': '$4', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR01': '$2', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR00': '$1', # General Purpose IO Register 0
+ 'PLLCSR' : '$87', # PLL Control And Status Registe
+ 'PLLCSR_PLLF': '$3c', #
+ 'PLLCSR_PLLE': '$2', # PLL Enable
+ 'PLLCSR_PLOCK': '$1', # PLL Lock Detector
+ 'PRR' : '$86', # Power Reduction Register
+ 'PRR_PRPSC2': '$80', # Power Reduction PSC2
+ 'PRR_PRPSCR': '$20', # Power Reduction PSC0
+ 'PRR_PRTIM1': '$10', # Power Reduction Timer/Counter1
+ 'PRR_PRSPI': '$4', # Power Reduction Serial Periphe
+ 'PRR_PRADC': '$1', # Power Reduction ADC
+ 'CLKCSR' : '$84', #
+ 'CLKCSR_CLKCCE': '$80', # Clock Control Change Enable
+ 'CLKCSR_CLKRDY': '$10', # Clock Ready Flag
+ 'CLKCSR_CLKC': '$f', # Clock Control
+ 'CLKSELR' : '$85', #
+ 'CLKSELR_COUT': '$40', # Clock OUT
+ 'CLKSELR_CSUT': '$30', # Clock Start up Time
+ 'CLKSELR_CKSEL': '$f', # Clock Source Select
+ 'BGCCR' : '$81', # BandGap Current Calibration Re
+ 'BGCCR_BGCC': '$f', #
+ 'BGCRR' : '$80', # BandGap Resistor Calibration R
+ 'BGCRR_BGCR': '$f', #
+
+# Module EEPROM
+ 'EEAR' : '$3e', # EEPROM Read/Write Access Byte
+ 'EEDR' : '$3d', # EEPROM Data Register
+ 'EECR' : '$3c', # EEPROM Control Register
+ 'EECR_NVMBSY': '$80', # None Volatile Busy Memory Busy
+ 'EECR_EEPAGE': '$40', # EEPROM Page Access
+ 'EECR_EEPM': '$30', # EEPROM Programming Mode
+ 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
+ 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
+ 'EECR_EEWE': '$2', # EEPROM Write Enable
+ 'EECR_EERE': '$1', # EEPROM Read Enable
+
+# Module PSC0
+ 'PICR0' : '$68', # PSC 0 Input Capture Register
+ 'PFRC0B' : '$63', # PSC 0 Input B Control
+ 'PFRC0B_PCAE0B': '$80', # PSC 0 Capture Enable Input Par
+ 'PFRC0B_PISEL0B': '$40', # PSC 0 Input Select for Part B
+ 'PFRC0B_PELEV0B': '$20', # PSC 0 Edge Level Selector on I
+ 'PFRC0B_PFLTE0B': '$10', # PSC 0 Filter Enable on Input P
+ 'PFRC0B_PRFM0B': '$f', # PSC 0 Retrigger and Fault Mode
+ 'PFRC0A' : '$62', # PSC 0 Input A Control
+ 'PFRC0A_PCAE0A': '$80', # PSC 0 Capture Enable Input Par
+ 'PFRC0A_PISEL0A': '$40', # PSC 0 Input Select for Part A
+ 'PFRC0A_PELEV0A': '$20', # PSC 0 Edge Level Selector on I
+ 'PFRC0A_PFLTE0A': '$10', # PSC 0 Filter Enable on Input P
+ 'PFRC0A_PRFM0A': '$f', # PSC 0 Retrigger and Fault Mode
+ 'PCTL0' : '$32', # PSC 0 Control Register
+ 'PCTL0_PPRE0': '$c0', # PSC 0 Prescaler Selects
+ 'PCTL0_PBFM0': '$24', # PSC 0 Balance Flank Width Modu
+ 'PCTL0_PAOC0B': '$10', # PSC 0 Asynchronous Output Cont
+ 'PCTL0_PAOC0A': '$8', # PSC 0 Asynchronous Output Cont
+ 'PCTL0_PCCYC0': '$2', # PSC0 Complete Cycle
+ 'PCTL0_PRUN0': '$1', # PSC 0 Run
+ 'PCNF0' : '$31', # PSC 0 Configuration Register
+ 'PCNF0_PFIFTY0': '$80', # PSC 0 Fifty
+ 'PCNF0_PALOCK0': '$40', # PSC 0 Autolock
+ 'PCNF0_PLOCK0': '$20', # PSC 0 Lock
+ 'PCNF0_PMODE0': '$18', # PSC 0 Mode
+ 'PCNF0_POP0': '$4', # PSC 0 Output Polarity
+ 'PCNF0_PCLKSEL0': '$2', # PSC 0 Input Clock Select
+ 'OCR0RB' : '$44', # Output Compare RB Register
+ 'OCR0SB' : '$42', # Output Compare SB Register
+ 'OCR0RA' : '$4a', # Output Compare RA Register
+ 'OCR0SA' : '$60', # Output Compare SA Register
+ 'PSOC0' : '$6a', # PSC0 Synchro and Output Config
+ 'PSOC0_PISEL0A1': '$80', # PSC Input Select
+ 'PSOC0_PISEL0B1': '$40', # PSC Input Select
+ 'PSOC0_PSYNC0': '$30', # Synchronisation out for ADC se
+ 'PSOC0_POEN0B': '$4', # PSCOUT01 Output Enable
+ 'PSOC0_POEN0A': '$1', # PSCOUT00 Output Enable
+ 'PIM0' : '$2f', # PSC0 Interrupt Mask Register
+ 'PIM0_PEVE0B': '$10', # External Event B Interrupt Ena
+ 'PIM0_PEVE0A': '$8', # External Event A Interrupt Ena
+ 'PIM0_PEOEPE0': '$2', # End of Enhanced Cycle Enable
+ 'PIM0_PEOPE0': '$1', # End of Cycle Interrupt Enable
+ 'PIFR0' : '$30', # PSC0 Interrupt Flag Register
+ 'PIFR0_POAC0B': '$80', # PSC 0 Output A Activity
+ 'PIFR0_POAC0A': '$40', # PSC 0 Output A Activity
+ 'PIFR0_PEV0B': '$10', # External Event B Interrupt
+ 'PIFR0_PEV0A': '$8', # External Event A Interrupt
+ 'PIFR0_PRN0': '$6', # Ramp Number
+ 'PIFR0_PEOP0': '$1', # End of PSC0 Interrupt
+
+# Module PSC2
+ 'PICR2H' : '$6d', # PSC 2 Input Capture Register H
+ 'PICR2H_PCST2': '$80', # PSC 2 Capture Software Trigger
+ 'PICR2H_PICR21': '$c', #
+ 'PICR2H_PICR2': '$3', #
+ 'PICR2L' : '$6c', # PSC 2 Input Capture Register L
+ 'PFRC2B' : '$67', # PSC 2 Input B Control
+ 'PFRC2B_PCAE2B': '$80', # PSC 2 Capture Enable Input Par
+ 'PFRC2B_PISEL2B': '$40', # PSC 2 Input Select for Part B
+ 'PFRC2B_PELEV2B': '$20', # PSC 2 Edge Level Selector on I
+ 'PFRC2B_PFLTE2B': '$10', # PSC 2 Filter Enable on Input P
+ 'PFRC2B_PRFM2B': '$f', # PSC 2 Retrigger and Fault Mode
+ 'PFRC2A' : '$66', # PSC 2 Input B Control
+ 'PFRC2A_PCAE2A': '$80', # PSC 2 Capture Enable Input Par
+ 'PFRC2A_PISEL2A': '$40', # PSC 2 Input Select for Part A
+ 'PFRC2A_PELEV2A': '$20', # PSC 2 Edge Level Selector on I
+ 'PFRC2A_PFLTE2A': '$10', # PSC 2 Filter Enable on Input P
+ 'PFRC2A_PRFM2A': '$f', # PSC 2 Retrigger and Fault Mode
+ 'PCTL2' : '$36', # PSC 2 Control Register
+ 'PCTL2_PPRE2': '$c0', # PSC 2 Prescaler Selects
+ 'PCTL2_PBFM2': '$20', # Balance Flank Width Modulation
+ 'PCTL2_PAOC2B': '$10', # PSC 2 Asynchronous Output Cont
+ 'PCTL2_PAOC2A': '$8', # PSC 2 Asynchronous Output Cont
+ 'PCTL2_PARUN2': '$4', # PSC2 Auto Run
+ 'PCTL2_PCCYC2': '$2', # PSC2 Complete Cycle
+ 'PCTL2_PRUN2': '$1', # PSC 2 Run
+ 'PCNF2' : '$35', # PSC 2 Configuration Register
+ 'PCNF2_PFIFTY2': '$80', # PSC 2 Fifty
+ 'PCNF2_PALOCK2': '$40', # PSC 2 Autolock
+ 'PCNF2_PLOCK2': '$20', # PSC 2 Lock
+ 'PCNF2_PMODE2': '$18', # PSC 2 Mode
+ 'PCNF2_POP2': '$4', # PSC 2 Output Polarity
+ 'PCNF2_PCLKSEL2': '$2', # PSC 2 Input Clock Select
+ 'PCNF2_POME2': '$1', # PSC 2 Output Matrix Enable
+ 'PCNFE2' : '$70', # PSC 2 Enhanced Configuration R
+ 'PCNFE2_PASDLK2': '$e0', #
+ 'PCNFE2_PBFM21': '$10', #
+ 'PCNFE2_PELEV2A1': '$8', #
+ 'PCNFE2_PELEV2B1': '$4', #
+ 'PCNFE2_PISEL2A1': '$2', #
+ 'PCNFE2_PISEL2B1': '$1', #
+ 'OCR2RB' : '$48', # Output Compare RB Register
+ 'OCR2SB' : '$46', # Output Compare SB Register
+ 'OCR2RA' : '$4e', # Output Compare RA Register
+ 'OCR2SA' : '$64', # Output Compare SA Register
+ 'POM2' : '$6f', # PSC 2 Output Matrix
+ 'POM2_POMV2B': '$f0', # Output Matrix Output B Ramps
+ 'POM2_POMV2A': '$f', # Output Matrix Output A Ramps
+ 'PSOC2' : '$6e', # PSC2 Synchro and Output Config
+ 'PSOC2_POS2': '$c0', # PSC 2 Output 23 Select
+ 'PSOC2_PSYNC2': '$30', # Synchronization Out for ADC Se
+ 'PSOC2_POEN2D': '$8', # PSCOUT23 Output Enable
+ 'PSOC2_POEN2B': '$4', # PSCOUT21 Output Enable
+ 'PSOC2_POEN2C': '$2', # PSCOUT22 Output Enable
+ 'PSOC2_POEN2A': '$1', # PSCOUT20 Output Enable
+ 'PIM2' : '$33', # PSC2 Interrupt Mask Register
+ 'PIM2_PSEIE2': '$20', # PSC 2 Synchro Error Interrupt
+ 'PIM2_PEVE2B': '$10', # External Event B Interrupt Ena
+ 'PIM2_PEVE2A': '$8', # External Event A Interrupt Ena
+ 'PIM2_PEOEPE2': '$2', # End of Enhanced Cycle Interrup
+ 'PIM2_PEOPE2': '$1', # End of Cycle Interrupt Enable
+ 'PIFR2' : '$34', # PSC2 Interrupt Flag Register
+ 'PIFR2_POAC2B': '$80', # PSC 2 Output A Activity
+ 'PIFR2_POAC2A': '$40', # PSC 2 Output A Activity
+ 'PIFR2_PSEI2': '$20', # PSC 2 Synchro Error Interrupt
+ 'PIFR2_PEV2B': '$10', # External Event B Interrupt
+ 'PIFR2_PEV2A': '$8', # External Event A Interrupt
+ 'PIFR2_PRN2': '$6', # Ramp Number
+ 'PIFR2_PEOP2': '$1', # End of PSC2 Interrupt
+ 'PASDLY2' : '$71', # Analog Synchronization Delay R
+
+# Module TIMER_COUNTER_1
+ 'TIMSK1' : '$21', # Timer/Counter Interrupt Mask R
+ 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
+ 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
+ 'TIFR1' : '$22', # Timer/Counter Interrupt Flag r
+ 'TIFR1_ICF1': '$20', # Input Capture Flag 1
+ 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
+ 'TCCR1B' : '$8a', # Timer/Counter1 Control Registe
+ 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
+ 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
+ 'TCCR1B_WGM13': '$10', # Waveform Generation Mode
+ 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
+ 'TCNT1' : '$5a', # Timer/Counter1 Bytes
+ 'ICR1' : '$8c', # Timer/Counter1 Input Capture R
+
+# Module BOOT_LOAD
+ 'SPMCSR' : '$57', # Store Program Memory Control R
+ 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
+ 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
+ 'SPMCSR_SIGRD': '$20', # Signature Row Read
+ 'SPMCSR_RWWSRE': '$10', # Read While Write section read
+ 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
+ 'SPMCSR_PGWRT': '$4', # Page Write
+ 'SPMCSR_PGERS': '$2', # Page Erase
+ 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
+
+ '__amforth_dummy':'0'
+}