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-rw-r--r--j1/verilog/stack.v22
1 files changed, 0 insertions, 22 deletions
diff --git a/j1/verilog/stack.v b/j1/verilog/stack.v
deleted file mode 100644
index e5cee8a..0000000
--- a/j1/verilog/stack.v
+++ /dev/null
@@ -1,22 +0,0 @@
-`include "common.h"
-
-module stack
- #(parameter DEPTH=4)
- (input wire clk,
- /* verilator lint_off UNUSED */
- input wire resetq,
- /* verilator lint_on UNUSED */
- input wire [DEPTH-1:0] ra,
- output wire [`WIDTH-1:0] rd,
- input wire we,
- input wire [DEPTH-1:0] wa,
- input wire [`WIDTH-1:0] wd);
-
- reg [`WIDTH-1:0] store[0:(2**DEPTH)-1];
-
- always @(posedge clk)
- if (we)
- store[wa] <= wd;
-
- assign rd = store[ra];
-endmodule