1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
|
/* $Id$ */
/*
* Copyright (c) 2012 Dimitri Sokolyuk <demon@dim13.org>
*
* Permission to use, copy, modify, and distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, dATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#include <stdio.h>
#include <unistd.h>
#include "dcpu16.h"
static unsigned short *mem;
static unsigned short *reg;
static unsigned short skip = 0;
static unsigned short run = 1;
static unsigned short cycle = 0;
void ext(unsigned short *a, unsigned short *b);
void set(unsigned short *a, unsigned short *b);
void add(unsigned short *a, unsigned short *b);
void sub(unsigned short *a, unsigned short *b);
void mul(unsigned short *a, unsigned short *b);
void div(unsigned short *a, unsigned short *b);
void mod(unsigned short *a, unsigned short *b);
void shl(unsigned short *a, unsigned short *b);
void shr(unsigned short *a, unsigned short *b);
void and(unsigned short *a, unsigned short *b);
void bor(unsigned short *a, unsigned short *b);
void xor(unsigned short *a, unsigned short *b);
void ife(unsigned short *a, unsigned short *b);
void ifn(unsigned short *a, unsigned short *b);
void ifg(unsigned short *a, unsigned short *b);
void ifb(unsigned short *a, unsigned short *b);
void (*op[nOpt])(unsigned short *a, unsigned short *b) = {
[EXT] = ext,
[SET] = set,
[ADD] = add,
[SUB] = sub,
[MUL] = mul,
[DIV] = div,
[MOD] = mod,
[SHL] = shl,
[SHR] = shr,
[AND] = and,
[BOR] = bor,
[XOR] = xor,
[IFE] = ife,
[IFN] = ifn,
[IFG] = ifg,
[IFB] = ifb,
};
void jsr(unsigned short *a);
void stop(unsigned short *a);
void (*extop[nExt])(unsigned short *a) = {
[Res] = stop, /* die on wrong opcode */
[JSR] = jsr,
[BRK] = stop,
};
void
ext(unsigned short *a, unsigned short *b)
{
extop[*a](b);
}
void
set(unsigned short *a, unsigned short *b)
{
*a = *b;
cycle += 1;
}
void
add(unsigned short *a, unsigned short *b)
{
int tmp = *a;
tmp += *b;
reg[O] = tmp > 0xFFFF;
*a = tmp;
cycle += 2;
}
void
sub(unsigned short *a, unsigned short *b)
{
int tmp = *a;
tmp -= *b;
reg[O] = tmp < 0;
*a = tmp;
cycle += 2;
}
void
mul(unsigned short *a, unsigned short *b)
{
int tmp = *a;
tmp *= *b;
reg[O] = tmp >> 16;
*a = tmp;
cycle += 2;
}
void
div(unsigned short *a, unsigned short *b)
{
int tmp = *a;
if (*b == 0) {
reg[O] = 0;
*a = 0;
} else {
reg[O] = ((tmp << 16) / *b);
*a /= *b;
}
cycle += 3;
}
void
mod(unsigned short *a, unsigned short *b)
{
if (*b == 0)
*a = 0;
else
*a %= *b;
cycle += 3;
}
void
shl(unsigned short *a, unsigned short *b)
{
int tmp = *a;
reg[O] = ((tmp << *b) >> 16);
*a <<= *b;
cycle += 2;
}
void
shr(unsigned short *a, unsigned short *b)
{
int tmp = *a;
reg[O] = ((tmp << 16) >> *b);
*a >>= *b;
cycle += 2;
}
void
and(unsigned short *a, unsigned short *b)
{
*a &= *b;
cycle += 1;
}
void
bor(unsigned short *a, unsigned short *b)
{
*a |= *b;
cycle += 1;
}
void
xor(unsigned short *a, unsigned short *b)
{
*a ^= *b;
cycle += 1;
}
void
ife(unsigned short *a, unsigned short *b)
{
skip = !(*a == *b);
cycle += skip ? 3 : 2;
}
void
ifn(unsigned short *a, unsigned short *b)
{
skip = !(*a != *b);
cycle += skip ? 3 : 2;
}
void
ifg(unsigned short *a, unsigned short *b)
{
skip = !(*a > *b);
cycle += skip ? 3 : 2;
}
void
ifb(unsigned short *a, unsigned short *b)
{
skip = !(*a & *b);
cycle += skip ? 3 : 2;
}
void
jsr(unsigned short *a)
{
mem[--reg[SP]] = reg[PC];
reg[PC] = *a;
cycle += 2;
}
void
stop(unsigned short *a)
{
run = 0;
}
unsigned short *
fetcharg(int a)
{
switch (a) {
case 0x00:
case 0x01:
case 0x02:
case 0x03:
case 0x04:
case 0x05:
case 0x06:
case 0x07:
/* register */
return ®[a];
case 0x08:
case 0x09:
case 0x0a:
case 0x0b:
case 0x0c:
case 0x0d:
case 0x0e:
case 0x0f:
/* [register] */
return &mem[reg[a - 0x08]];
case 0x10:
case 0x11:
case 0x12:
case 0x13:
case 0x14:
case 0x15:
case 0x16:
case 0x17:
/* [next word + register] */
cycle += 1;
return &mem[mem[reg[PC]++] + reg[a - 0x10]];
case 0x18:
/* pop */
return &mem[reg[SP]++];
case 0x19:
/* peek */
return &mem[reg[SP]];
case 0x1a:
/* push */
return &mem[--reg[SP]];
case 0x1b:
/* SP */
return ®[SP];
case 0x1c:
/* PC */
return ®[PC];
case 0x1d:
/* O */
return ®[O];
case 0x1e:
/* [next word] */
cycle += 1;
return &mem[mem[reg[PC]++]];
case 0x1f:
/* next word */
cycle += 1;
return &mem[reg[PC]++];
default:
/* literal */
reg[Aux] = a - 0x20;
return ®[Aux];
}
}
int
step(unsigned short *m, unsigned short *r)
{
unsigned short c, o, *a, *b, s;
if (!run)
return -1;
mem = m;
reg = r;
cycle = 0;
c = mem[reg[PC]++];
s = reg[SP]; /* store SP */
o = c & 0x0f;
reg[Aux] = (c >> 4) & 0x3f;
/* don't fetch first arg for extended opcodes */
a = o ? fetcharg(reg[Aux]) : ®[Aux];
b = fetcharg((c >> 10) & 0x3f);
if (skip) {
skip = 0;
reg[SP] = s; /* restore SP on skipped opcode */
} else
op[o](a, b);
usleep(10 * cycle); /* 100kHz */
return 0;
}
|