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authorDimitri Sokolyuk <demon@dim13.org>2017-08-19 12:15:28 +0200
committerDimitri Sokolyuk <demon@dim13.org>2017-08-19 12:15:28 +0200
commit67d25d837ac55f28a366c0a3b262e439a6e75fc3 (patch)
treedf7715c7724c5935ab87c807f3b8b4ef529315e3 /amforth-6.5/avr8/devices
parente0d6784e89dba33226c0edb815bb974486fa7c48 (diff)
Add AmForth
Diffstat (limited to 'amforth-6.5/avr8/devices')
-rw-r--r--amforth-6.5/avr8/devices/at90can128/at90can128.frt465
-rw-r--r--amforth-6.5/avr8/devices/at90can128/device.asm145
-rw-r--r--amforth-6.5/avr8/devices/at90can128/device.inc1707
-rw-r--r--amforth-6.5/avr8/devices/at90can128/device.py507
-rw-r--r--amforth-6.5/avr8/devices/at90can128/words/no-jtag.asm14
-rw-r--r--amforth-6.5/avr8/devices/at90can128/words/no-wdt.asm22
-rw-r--r--amforth-6.5/avr8/devices/at90can128/words/sleep.asm19
-rw-r--r--amforth-6.5/avr8/devices/at90can32/at90can32.frt465
-rw-r--r--amforth-6.5/avr8/devices/at90can32/device.asm139
-rw-r--r--amforth-6.5/avr8/devices/at90can32/device.inc1707
-rw-r--r--amforth-6.5/avr8/devices/at90can32/device.py507
-rw-r--r--amforth-6.5/avr8/devices/at90can32/words/no-jtag.asm14
-rw-r--r--amforth-6.5/avr8/devices/at90can32/words/no-wdt.asm22
-rw-r--r--amforth-6.5/avr8/devices/at90can32/words/sleep.asm19
-rw-r--r--amforth-6.5/avr8/devices/at90can64/at90can64.frt465
-rw-r--r--amforth-6.5/avr8/devices/at90can64/device.asm139
-rw-r--r--amforth-6.5/avr8/devices/at90can64/device.inc1707
-rw-r--r--amforth-6.5/avr8/devices/at90can64/device.py507
-rw-r--r--amforth-6.5/avr8/devices/at90can64/words/no-jtag.asm14
-rw-r--r--amforth-6.5/avr8/devices/at90can64/words/no-wdt.asm22
-rw-r--r--amforth-6.5/avr8/devices/at90can64/words/sleep.asm19
-rw-r--r--amforth-6.5/avr8/devices/at90pwm1/at90pwm1.frt381
-rw-r--r--amforth-6.5/avr8/devices/at90pwm1/device.asm121
-rw-r--r--amforth-6.5/avr8/devices/at90pwm1/device.inc1143
-rw-r--r--amforth-6.5/avr8/devices/at90pwm1/device.py404
-rw-r--r--amforth-6.5/avr8/devices/at90pwm1/words/no-jtag.asm14
-rw-r--r--amforth-6.5/avr8/devices/at90pwm1/words/no-wdt.asm34
-rw-r--r--amforth-6.5/avr8/devices/at90pwm1/words/sleep.asm19
-rw-r--r--amforth-6.5/avr8/devices/at90pwm161/blocks/AD_CONVERTER.frt71
-rw-r--r--amforth-6.5/avr8/devices/at90pwm161/blocks/ANALOG_COMPARATOR.frt69
-rw-r--r--amforth-6.5/avr8/devices/at90pwm161/blocks/BOOT_LOAD.frt21
-rw-r--r--amforth-6.5/avr8/devices/at90pwm161/blocks/CPU.frt114
-rw-r--r--amforth-6.5/avr8/devices/at90pwm161/blocks/DA_CONVERTER.frt19
-rw-r--r--amforth-6.5/avr8/devices/at90pwm161/blocks/EEPROM.frt21
-rw-r--r--amforth-6.5/avr8/devices/at90pwm161/blocks/EXTERNAL_INTERRUPT.frt17
-rw-r--r--amforth-6.5/avr8/devices/at90pwm161/blocks/PORTB.frt7
-rw-r--r--amforth-6.5/avr8/devices/at90pwm161/blocks/PORTD.frt7
-rw-r--r--amforth-6.5/avr8/devices/at90pwm161/blocks/PORTE.frt7
-rw-r--r--amforth-6.5/avr8/devices/at90pwm161/blocks/PSC0.frt90
-rw-r--r--amforth-6.5/avr8/devices/at90pwm161/blocks/PSC2.frt126
-rw-r--r--amforth-6.5/avr8/devices/at90pwm161/blocks/SPI.frt27
-rw-r--r--amforth-6.5/avr8/devices/at90pwm161/blocks/TIMER_COUNTER_1.frt25
-rw-r--r--amforth-6.5/avr8/devices/at90pwm161/blocks/WATCHDOG.frt15
-rw-r--r--amforth-6.5/avr8/devices/at90pwm161/device.asm52
-rw-r--r--amforth-6.5/avr8/devices/at90pwm161/device.frt613
-rw-r--r--amforth-6.5/avr8/devices/at90pwm161/device.py389
-rw-r--r--amforth-6.5/avr8/devices/at90pwm2/at90pwm2.frt193
-rw-r--r--amforth-6.5/avr8/devices/at90pwm2/device.asm137
-rw-r--r--amforth-6.5/avr8/devices/at90pwm2/device.inc1539
-rw-r--r--amforth-6.5/avr8/devices/at90pwm2/device.py155
-rw-r--r--amforth-6.5/avr8/devices/at90pwm216/at90pwm216.frt423
-rw-r--r--amforth-6.5/avr8/devices/at90pwm216/device.asm123
-rw-r--r--amforth-6.5/avr8/devices/at90pwm216/device.inc1281
-rw-r--r--amforth-6.5/avr8/devices/at90pwm216/device.py448
-rw-r--r--amforth-6.5/avr8/devices/at90pwm216/words/no-jtag.asm14
-rw-r--r--amforth-6.5/avr8/devices/at90pwm216/words/no-wdt.asm34
-rw-r--r--amforth-6.5/avr8/devices/at90pwm216/words/sleep.asm19
-rw-r--r--amforth-6.5/avr8/devices/at90pwm2b/at90pwm2b.frt423
-rw-r--r--amforth-6.5/avr8/devices/at90pwm2b/device.asm123
-rw-r--r--amforth-6.5/avr8/devices/at90pwm2b/device.inc1281
-rw-r--r--amforth-6.5/avr8/devices/at90pwm2b/device.py448
-rw-r--r--amforth-6.5/avr8/devices/at90pwm2b/words/no-jtag.asm14
-rw-r--r--amforth-6.5/avr8/devices/at90pwm2b/words/no-wdt.asm34
-rw-r--r--amforth-6.5/avr8/devices/at90pwm2b/words/sleep.asm19
-rw-r--r--amforth-6.5/avr8/devices/at90pwm3/at90pwm3.frt217
-rw-r--r--amforth-6.5/avr8/devices/at90pwm3/device.asm139
-rw-r--r--amforth-6.5/avr8/devices/at90pwm3/device.inc1791
-rw-r--r--amforth-6.5/avr8/devices/at90pwm3/device.py175
-rw-r--r--amforth-6.5/avr8/devices/at90pwm316/at90pwm316.frt478
-rw-r--r--amforth-6.5/avr8/devices/at90pwm316/device.asm125
-rw-r--r--amforth-6.5/avr8/devices/at90pwm316/device.inc1467
-rw-r--r--amforth-6.5/avr8/devices/at90pwm316/device.py505
-rw-r--r--amforth-6.5/avr8/devices/at90pwm316/words/no-jtag.asm14
-rw-r--r--amforth-6.5/avr8/devices/at90pwm316/words/no-wdt.asm34
-rw-r--r--amforth-6.5/avr8/devices/at90pwm316/words/sleep.asm19
-rw-r--r--amforth-6.5/avr8/devices/at90pwm3b/at90pwm3b.frt478
-rw-r--r--amforth-6.5/avr8/devices/at90pwm3b/device.asm125
-rw-r--r--amforth-6.5/avr8/devices/at90pwm3b/device.inc1467
-rw-r--r--amforth-6.5/avr8/devices/at90pwm3b/device.py505
-rw-r--r--amforth-6.5/avr8/devices/at90pwm3b/words/no-jtag.asm14
-rw-r--r--amforth-6.5/avr8/devices/at90pwm3b/words/no-wdt.asm34
-rw-r--r--amforth-6.5/avr8/devices/at90pwm3b/words/sleep.asm19
-rw-r--r--amforth-6.5/avr8/devices/at90pwm81/at90pwm81.frt370
-rw-r--r--amforth-6.5/avr8/devices/at90pwm81/device.asm96
-rw-r--r--amforth-6.5/avr8/devices/at90pwm81/device.inc1080
-rw-r--r--amforth-6.5/avr8/devices/at90pwm81/device.py389
-rw-r--r--amforth-6.5/avr8/devices/at90pwm81/words/no-jtag.asm14
-rw-r--r--amforth-6.5/avr8/devices/at90pwm81/words/no-wdt.asm34
-rw-r--r--amforth-6.5/avr8/devices/at90pwm81/words/sleep.asm19
-rw-r--r--amforth-6.5/avr8/devices/at90usb1286/at90usb1286.frt486
-rw-r--r--amforth-6.5/avr8/devices/at90usb1286/device.asm145
-rw-r--r--amforth-6.5/avr8/devices/at90usb1286/device.inc1611
-rw-r--r--amforth-6.5/avr8/devices/at90usb1286/device.py523
-rw-r--r--amforth-6.5/avr8/devices/at90usb1286/words/no-jtag.asm14
-rw-r--r--amforth-6.5/avr8/devices/at90usb1286/words/no-wdt.asm34
-rw-r--r--amforth-6.5/avr8/devices/at90usb1286/words/sleep.asm19
-rw-r--r--amforth-6.5/avr8/devices/at90usb1287/at90usb1287.frt587
-rw-r--r--amforth-6.5/avr8/devices/at90usb1287/device.asm146
-rw-r--r--amforth-6.5/avr8/devices/at90usb1287/device.inc1914
-rw-r--r--amforth-6.5/avr8/devices/at90usb1287/device.py625
-rw-r--r--amforth-6.5/avr8/devices/at90usb1287/words/no-jtag.asm14
-rw-r--r--amforth-6.5/avr8/devices/at90usb1287/words/no-wdt.asm34
-rw-r--r--amforth-6.5/avr8/devices/at90usb1287/words/sleep.asm19
-rw-r--r--amforth-6.5/avr8/devices/at90usb162/at90usb162.frt367
-rw-r--r--amforth-6.5/avr8/devices/at90usb162/device.asm113
-rw-r--r--amforth-6.5/avr8/devices/at90usb162/device.inc1155
-rw-r--r--amforth-6.5/avr8/devices/at90usb162/device.py387
-rw-r--r--amforth-6.5/avr8/devices/at90usb162/words/no-jtag.asm14
-rw-r--r--amforth-6.5/avr8/devices/at90usb162/words/no-wdt.asm34
-rw-r--r--amforth-6.5/avr8/devices/at90usb162/words/sleep.asm19
-rw-r--r--amforth-6.5/avr8/devices/at90usb646/at90usb646.frt587
-rw-r--r--amforth-6.5/avr8/devices/at90usb646/device.asm140
-rw-r--r--amforth-6.5/avr8/devices/at90usb646/device.inc1914
-rw-r--r--amforth-6.5/avr8/devices/at90usb646/device.py625
-rw-r--r--amforth-6.5/avr8/devices/at90usb646/words/no-jtag.asm14
-rw-r--r--amforth-6.5/avr8/devices/at90usb646/words/no-wdt.asm34
-rw-r--r--amforth-6.5/avr8/devices/at90usb646/words/sleep.asm19
-rw-r--r--amforth-6.5/avr8/devices/at90usb647/at90usb647.frt587
-rw-r--r--amforth-6.5/avr8/devices/at90usb647/device.asm140
-rw-r--r--amforth-6.5/avr8/devices/at90usb647/device.inc1914
-rw-r--r--amforth-6.5/avr8/devices/at90usb647/device.py625
-rw-r--r--amforth-6.5/avr8/devices/at90usb647/words/no-jtag.asm14
-rw-r--r--amforth-6.5/avr8/devices/at90usb647/words/no-wdt.asm34
-rw-r--r--amforth-6.5/avr8/devices/at90usb647/words/sleep.asm19
-rw-r--r--amforth-6.5/avr8/devices/at90usb82/at90usb82.frt367
-rw-r--r--amforth-6.5/avr8/devices/at90usb82/device.asm113
-rw-r--r--amforth-6.5/avr8/devices/at90usb82/device.inc1155
-rw-r--r--amforth-6.5/avr8/devices/at90usb82/device.py387
-rw-r--r--amforth-6.5/avr8/devices/at90usb82/words/no-jtag.asm14
-rw-r--r--amforth-6.5/avr8/devices/at90usb82/words/no-wdt.asm34
-rw-r--r--amforth-6.5/avr8/devices/at90usb82/words/sleep.asm19
-rw-r--r--amforth-6.5/avr8/devices/atmega103/atmega103.frt124
-rw-r--r--amforth-6.5/avr8/devices/atmega103/device.asm126
-rw-r--r--amforth-6.5/avr8/devices/atmega103/device.inc825
-rw-r--r--amforth-6.5/avr8/devices/atmega103/device.py88
-rw-r--r--amforth-6.5/avr8/devices/atmega128/atmega128.frt329
-rw-r--r--amforth-6.5/avr8/devices/atmega128/device.asm141
-rw-r--r--amforth-6.5/avr8/devices/atmega128/device.inc1179
-rw-r--r--amforth-6.5/avr8/devices/atmega128/device.py403
-rw-r--r--amforth-6.5/avr8/devices/atmega128/words/no-jtag.asm14
-rw-r--r--amforth-6.5/avr8/devices/atmega128/words/no-wdt.asm22
-rw-r--r--amforth-6.5/avr8/devices/atmega128/words/sleep.asm24
-rw-r--r--amforth-6.5/avr8/devices/atmega1280/atmega1280.frt580
-rw-r--r--amforth-6.5/avr8/devices/atmega1280/device.asm190
-rw-r--r--amforth-6.5/avr8/devices/atmega1280/device.inc1980
-rw-r--r--amforth-6.5/avr8/devices/atmega1280/device.py633
-rw-r--r--amforth-6.5/avr8/devices/atmega1280/words/no-jtag.asm14
-rw-r--r--amforth-6.5/avr8/devices/atmega1280/words/no-wdt.asm34
-rw-r--r--amforth-6.5/avr8/devices/atmega1280/words/sleep.asm19
-rw-r--r--amforth-6.5/avr8/devices/atmega1281/atmega1281.frt509
-rw-r--r--amforth-6.5/avr8/devices/atmega1281/device.asm184
-rw-r--r--amforth-6.5/avr8/devices/atmega1281/device.inc1686
-rw-r--r--amforth-6.5/avr8/devices/atmega1281/device.py556
-rw-r--r--amforth-6.5/avr8/devices/atmega1281/words/no-jtag.asm14
-rw-r--r--amforth-6.5/avr8/devices/atmega1281/words/no-wdt.asm34
-rw-r--r--amforth-6.5/avr8/devices/atmega1281/words/sleep.asm19
-rw-r--r--amforth-6.5/avr8/devices/atmega1284/atmega1284.frt380
-rw-r--r--amforth-6.5/avr8/devices/atmega1284/device.asm135
-rw-r--r--amforth-6.5/avr8/devices/atmega1284/device.inc1263
-rw-r--r--amforth-6.5/avr8/devices/atmega1284/device.py421
-rw-r--r--amforth-6.5/avr8/devices/atmega1284/words/no-jtag.asm14
-rw-r--r--amforth-6.5/avr8/devices/atmega1284/words/no-wdt.asm34
-rw-r--r--amforth-6.5/avr8/devices/atmega1284/words/sleep.asm19
-rw-r--r--amforth-6.5/avr8/devices/atmega1284p/atmega1284p.frt380
-rw-r--r--amforth-6.5/avr8/devices/atmega1284p/device.asm135
-rw-r--r--amforth-6.5/avr8/devices/atmega1284p/device.inc1263
-rw-r--r--amforth-6.5/avr8/devices/atmega1284p/device.py423
-rw-r--r--amforth-6.5/avr8/devices/atmega1284p/words/no-jtag.asm14
-rw-r--r--amforth-6.5/avr8/devices/atmega1284p/words/no-wdt.asm34
-rw-r--r--amforth-6.5/avr8/devices/atmega1284p/words/sleep.asm19
-rw-r--r--amforth-6.5/avr8/devices/atmega1284rfr2/blocks/AD_CONVERTER.frt79
-rw-r--r--amforth-6.5/avr8/devices/atmega1284rfr2/blocks/ANALOG_COMPARATOR.frt27
-rw-r--r--amforth-6.5/avr8/devices/atmega1284rfr2/blocks/BOOT_LOAD.frt21
-rw-r--r--amforth-6.5/avr8/devices/atmega1284rfr2/blocks/CPU.frt128
-rw-r--r--amforth-6.5/avr8/devices/atmega1284rfr2/blocks/EEPROM.frt19
-rw-r--r--amforth-6.5/avr8/devices/atmega1284rfr2/blocks/EXTERNAL_INTERRUPT.frt45
-rw-r--r--amforth-6.5/avr8/devices/atmega1284rfr2/blocks/FLASH.frt16
-rw-r--r--amforth-6.5/avr8/devices/atmega1284rfr2/blocks/JTAG.frt13
-rw-r--r--amforth-6.5/avr8/devices/atmega1284rfr2/blocks/PORTA.frt7
-rw-r--r--amforth-6.5/avr8/devices/atmega1284rfr2/blocks/PORTB.frt7
-rw-r--r--amforth-6.5/avr8/devices/atmega1284rfr2/blocks/PORTC.frt7
-rw-r--r--amforth-6.5/avr8/devices/atmega1284rfr2/blocks/PORTD.frt7
-rw-r--r--amforth-6.5/avr8/devices/atmega1284rfr2/blocks/PORTE.frt7
-rw-r--r--amforth-6.5/avr8/devices/atmega1284rfr2/blocks/PORTF.frt7
-rw-r--r--amforth-6.5/avr8/devices/atmega1284rfr2/blocks/PORTG.frt7
-rw-r--r--amforth-6.5/avr8/devices/atmega1284rfr2/blocks/PWRCTRL.frt81
-rw-r--r--amforth-6.5/avr8/devices/atmega1284rfr2/blocks/SPI.frt29
-rw-r--r--amforth-6.5/avr8/devices/atmega1284rfr2/blocks/SYMCNT.frt156
-rw-r--r--amforth-6.5/avr8/devices/atmega1284rfr2/blocks/TIMER_COUNTER_0.frt54
-rw-r--r--amforth-6.5/avr8/devices/atmega1284rfr2/blocks/TIMER_COUNTER_1.frt68
-rw-r--r--amforth-6.5/avr8/devices/atmega1284rfr2/blocks/TIMER_COUNTER_2.frt67
-rw-r--r--amforth-6.5/avr8/devices/atmega1284rfr2/blocks/TIMER_COUNTER_3.frt68
-rw-r--r--amforth-6.5/avr8/devices/atmega1284rfr2/blocks/TIMER_COUNTER_4.frt68
-rw-r--r--amforth-6.5/avr8/devices/atmega1284rfr2/blocks/TIMER_COUNTER_5.frt68
-rw-r--r--amforth-6.5/avr8/devices/atmega1284rfr2/blocks/TRX24.frt495
-rw-r--r--amforth-6.5/avr8/devices/atmega1284rfr2/blocks/TWI.frt40
-rw-r--r--amforth-6.5/avr8/devices/atmega1284rfr2/blocks/USART0.frt51
-rw-r--r--amforth-6.5/avr8/devices/atmega1284rfr2/blocks/USART0_SPI.frt29
-rw-r--r--amforth-6.5/avr8/devices/atmega1284rfr2/blocks/USART1.frt51
-rw-r--r--amforth-6.5/avr8/devices/atmega1284rfr2/blocks/USART1_SPI.frt29
-rw-r--r--amforth-6.5/avr8/devices/atmega1284rfr2/blocks/WATCHDOG.frt15
-rw-r--r--amforth-6.5/avr8/devices/atmega1284rfr2/device.asm166
-rw-r--r--amforth-6.5/avr8/devices/atmega1284rfr2/device.frt1752
-rw-r--r--amforth-6.5/avr8/devices/atmega1284rfr2/device.py1103
-rw-r--r--amforth-6.5/avr8/devices/atmega128a/atmega128a.frt329
-rw-r--r--amforth-6.5/avr8/devices/atmega128a/device.asm141
-rw-r--r--amforth-6.5/avr8/devices/atmega128a/device.inc1179
-rw-r--r--amforth-6.5/avr8/devices/atmega128a/device.py403
-rw-r--r--amforth-6.5/avr8/devices/atmega128a/words/no-jtag.asm14
-rw-r--r--amforth-6.5/avr8/devices/atmega128a/words/no-wdt.asm22
-rw-r--r--amforth-6.5/avr8/devices/atmega128a/words/sleep.asm24
-rw-r--r--amforth-6.5/avr8/devices/atmega128rfa1/atmega128rfa1.frt902
-rw-r--r--amforth-6.5/avr8/devices/atmega128rfa1/device.asm220
-rw-r--r--amforth-6.5/avr8/devices/atmega128rfa1/device.inc2808
-rw-r--r--amforth-6.5/avr8/devices/atmega128rfa1/device.py991
-rw-r--r--amforth-6.5/avr8/devices/atmega128rfa1/words/no-jtag.asm14
-rw-r--r--amforth-6.5/avr8/devices/atmega128rfa1/words/no-wdt.asm34
-rw-r--r--amforth-6.5/avr8/devices/atmega128rfa1/words/sleep.asm19
-rw-r--r--amforth-6.5/avr8/devices/atmega128rfr2/blocks/AD_CONVERTER.frt79
-rw-r--r--amforth-6.5/avr8/devices/atmega128rfr2/blocks/ANALOG_COMPARATOR.frt27
-rw-r--r--amforth-6.5/avr8/devices/atmega128rfr2/blocks/BOOT_LOAD.frt21
-rw-r--r--amforth-6.5/avr8/devices/atmega128rfr2/blocks/CPU.frt128
-rw-r--r--amforth-6.5/avr8/devices/atmega128rfr2/blocks/EEPROM.frt19
-rw-r--r--amforth-6.5/avr8/devices/atmega128rfr2/blocks/EXTERNAL_INTERRUPT.frt45
-rw-r--r--amforth-6.5/avr8/devices/atmega128rfr2/blocks/FLASH.frt16
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-rw-r--r--amforth-6.5/avr8/devices/atmega88pa/atmega88pa.frt299
-rw-r--r--amforth-6.5/avr8/devices/atmega88pa/device.asm107
-rw-r--r--amforth-6.5/avr8/devices/atmega88pa/device.inc996
-rw-r--r--amforth-6.5/avr8/devices/atmega88pa/device.py283
-rw-r--r--amforth-6.5/avr8/devices/atmega88pa/words/no-jtag.asm14
-rw-r--r--amforth-6.5/avr8/devices/atmega88pa/words/no-wdt.asm34
-rw-r--r--amforth-6.5/avr8/devices/atmega88pa/words/sleep.asm19
-rw-r--r--amforth-6.5/avr8/devices/atmega8a/atmega8a.frt207
-rw-r--r--amforth-6.5/avr8/devices/atmega8a/device.asm95
-rw-r--r--amforth-6.5/avr8/devices/atmega8a/device.inc696
-rw-r--r--amforth-6.5/avr8/devices/atmega8a/device.py191
-rw-r--r--amforth-6.5/avr8/devices/atmega8a/words/no-jtag.asm14
-rw-r--r--amforth-6.5/avr8/devices/atmega8a/words/no-wdt.asm22
-rw-r--r--amforth-6.5/avr8/devices/atmega8a/words/sleep.asm24
-rw-r--r--amforth-6.5/avr8/devices/atmega8hva/atmega8hva.frt140
-rw-r--r--amforth-6.5/avr8/devices/atmega8hva/device.asm114
-rw-r--r--amforth-6.5/avr8/devices/atmega8hva/device.inc1053
-rw-r--r--amforth-6.5/avr8/devices/atmega8hva/device.py104
-rw-r--r--amforth-6.5/avr8/devices/atmega8u2/atmega8u2.frt357
-rw-r--r--amforth-6.5/avr8/devices/atmega8u2/device.asm112
-rw-r--r--amforth-6.5/avr8/devices/atmega8u2/device.inc1128
-rw-r--r--amforth-6.5/avr8/devices/atmega8u2/device.py341
-rw-r--r--amforth-6.5/avr8/devices/atmega8u2/words/no-jtag.asm14
-rw-r--r--amforth-6.5/avr8/devices/atmega8u2/words/no-wdt.asm34
-rw-r--r--amforth-6.5/avr8/devices/atmega8u2/words/sleep.asm19
960 files changed, 267202 insertions, 0 deletions
diff --git a/amforth-6.5/avr8/devices/at90can128/at90can128.frt b/amforth-6.5/avr8/devices/at90can128/at90can128.frt
new file mode 100644
index 0000000..28cb0af
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90can128/at90can128.frt
@@ -0,0 +1,465 @@
+\ Partname: AT90CAN128
+\ generated automatically
+
+\ PORTA
+&34 constant PORTA \ Port A Data Register
+&33 constant DDRA \ Port A Data Direction Register
+&32 constant PINA \ Port A Input Pins
+\ PORTB
+&37 constant PORTB \ Port B Data Register
+&36 constant DDRB \ Port B Data Direction Register
+&35 constant PINB \ Port B Input Pins
+\ PORTC
+&40 constant PORTC \ Port C Data Register
+&39 constant DDRC \ Port C Data Direction Register
+&38 constant PINC \ Port C Input Pins
+\ PORTD
+&43 constant PORTD \ Port D Data Register
+&42 constant DDRD \ Port D Data Direction Register
+&41 constant PIND \ Port D Input Pins
+\ PORTE
+&46 constant PORTE \ Data Register, Port E
+&45 constant DDRE \ Data Direction Register, Port E
+&44 constant PINE \ Input Pins, Port E
+\ PORTF
+&49 constant PORTF \ Data Register, Port F
+&48 constant DDRF \ Data Direction Register, Port F
+&47 constant PINF \ Input Pins, Port F
+\ JTAG
+&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
+&85 constant MCUCR \ MCU Control Register
+ $80 constant MCUCR_JTD \ JTAG Interface Disable
+&84 constant MCUSR \ MCU Status Register
+ $10 constant MCUSR_JTRF \ JTAG Reset Flag
+\ SPI
+&76 constant SPCR \ SPI Control Register
+ $80 constant SPCR_SPIE \ SPI Interrupt Enable
+ $40 constant SPCR_SPE \ SPI Enable
+ $20 constant SPCR_DORD \ Data Order
+ $10 constant SPCR_MSTR \ Master/Slave Select
+ $08 constant SPCR_CPOL \ Clock polarity
+ $04 constant SPCR_CPHA \ Clock Phase
+ $03 constant SPCR_SPR \ SPI Clock Rate Selects
+&77 constant SPSR \ SPI Status Register
+ $80 constant SPSR_SPIF \ SPI Interrupt Flag
+ $40 constant SPSR_WCOL \ Write Collision Flag
+ $01 constant SPSR_SPI2X \ Double SPI Speed Bit
+&78 constant SPDR \ SPI Data Register
+\ TWI
+&184 constant TWBR \ TWI Bit Rate register
+&188 constant TWCR \ TWI Control Register
+ $80 constant TWCR_TWINT \ TWI Interrupt Flag
+ $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
+ $20 constant TWCR_TWSTA \ TWI Start Condition Bit
+ $10 constant TWCR_TWSTO \ TWI Stop Condition Bit
+ $08 constant TWCR_TWWC \ TWI Write Collition Flag
+ $04 constant TWCR_TWEN \ TWI Enable Bit
+ $01 constant TWCR_TWIE \ TWI Interrupt Enable
+&185 constant TWSR \ TWI Status Register
+ $F8 constant TWSR_TWS \ TWI Status
+ $03 constant TWSR_TWPS \ TWI Prescaler
+&187 constant TWDR \ TWI Data register
+&186 constant TWAR \ TWI (Slave) Address register
+ $FE constant TWAR_TWA \ TWI (Slave) Address register Bits
+ $01 constant TWAR_TWGCE \ TWI General Call Recognition Enable Bit
+\ USART0
+&198 constant UDR0 \ USART I/O Data Register
+&192 constant UCSR0A \ USART Control and Status Register A
+ $80 constant UCSR0A_RXC0 \ USART Receive Complete
+ $40 constant UCSR0A_TXC0 \ USART Transmitt Complete
+ $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
+ $10 constant UCSR0A_FE0 \ Framing Error
+ $08 constant UCSR0A_DOR0 \ Data overRun
+ $04 constant UCSR0A_UPE0 \ Parity Error
+ $02 constant UCSR0A_U2X0 \ Double the USART transmission speed
+ $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
+&193 constant UCSR0B \ USART Control and Status Register B
+ $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
+ $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
+ $20 constant UCSR0B_UDRIE0 \ USART Data register Empty Interrupt Enable
+ $10 constant UCSR0B_RXEN0 \ Receiver Enable
+ $08 constant UCSR0B_TXEN0 \ Transmitter Enable
+ $04 constant UCSR0B_UCSZ02 \ Character Size
+ $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
+ $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
+&194 constant UCSR0C \ USART Control and Status Register C
+ $40 constant UCSR0C_UMSEL0 \ USART Mode Select
+ $30 constant UCSR0C_UPM0 \ Parity Mode Bits
+ $08 constant UCSR0C_USBS0 \ Stop Bit Select
+ $06 constant UCSR0C_UCSZ0 \ Character Size
+ $01 constant UCSR0C_UCPOL0 \ Clock Polarity
+&196 constant UBRR0 \ USART Baud Rate Register t Bytes
+\ USART1
+&206 constant UDR1 \ USART I/O Data Register
+&200 constant UCSR1A \ USART Control and Status Register A
+ $80 constant UCSR1A_RXC1 \ USART Receive Complete
+ $40 constant UCSR1A_TXC1 \ USART Transmitt Complete
+ $20 constant UCSR1A_UDRE1 \ USART Data Register Empty
+ $10 constant UCSR1A_FE1 \ Framing Error
+ $08 constant UCSR1A_DOR1 \ Data overRun
+ $04 constant UCSR1A_UPE1 \ Parity Error
+ $02 constant UCSR1A_U2X1 \ Double the USART transmission speed
+ $01 constant UCSR1A_MPCM1 \ Multi-processor Communication Mode
+&201 constant UCSR1B \ USART Control and Status Register B
+ $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable
+ $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable
+ $20 constant UCSR1B_UDRIE1 \ USART Data register Empty Interrupt Enable
+ $10 constant UCSR1B_RXEN1 \ Receiver Enable
+ $08 constant UCSR1B_TXEN1 \ Transmitter Enable
+ $04 constant UCSR1B_UCSZ12 \ Character Size
+ $02 constant UCSR1B_RXB81 \ Receive Data Bit 8
+ $01 constant UCSR1B_TXB81 \ Transmit Data Bit 8
+&202 constant UCSR1C \ USART Control and Status Register C
+ $40 constant UCSR1C_UMSEL1 \ USART Mode Select
+ $30 constant UCSR1C_UPM1 \ Parity Mode Bits
+ $08 constant UCSR1C_USBS1 \ Stop Bit Select
+ $06 constant UCSR1C_UCSZ1 \ Character Size
+ $01 constant UCSR1C_UCPOL1 \ Clock Polarity
+&204 constant UBRR1 \ USART Baud Rate Register t Bytes
+\ CPU
+&95 constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ $08 constant SREG_V \ Two's Complement Overflow Flag
+ $04 constant SREG_N \ Negative Flag
+ $02 constant SREG_Z \ Zero Flag
+ $01 constant SREG_C \ Carry Flag
+&93 constant SP \ Stack Pointer
+&116 constant XMCRA \ External Memory Control Register A
+ $80 constant XMCRA_SRE \ External SRAM Enable
+ $70 constant XMCRA_SRL \ Wait state page limit
+ $0C constant XMCRA_SRW1 \ Wait state select bit upper page
+ $03 constant XMCRA_SRW0 \ Wait state select bit lower page
+&117 constant XMCRB \ External Memory Control Register B
+ $80 constant XMCRB_XMBK \ External Memory Bus Keeper Enable
+ $07 constant XMCRB_XMM \ External Memory High Mask
+&102 constant OSCCAL \ Oscillator Calibration Value
+&97 constant CLKPR \ Clock Prescale Register
+ $80 constant CLKPR_CLKPCE \
+ $0F constant CLKPR_CLKPS \
+&83 constant SMCR \ Sleep Mode Control Register
+ $0E constant SMCR_SM \ Sleep Mode Select bits
+ $01 constant SMCR_SE \ Sleep Enable
+&91 constant RAMPZ \ RAM Page Z Select Register
+ $01 constant RAMPZ_RAMPZ0 \ RAM Page Z Select Register Bit 0
+&75 constant GPIOR2 \ General Purpose IO Register 2
+ $FF constant GPIOR2_GPIOR \ General Purpose IO Register 2 bis
+&74 constant GPIOR1 \ General Purpose IO Register 1
+ $FF constant GPIOR1_GPIOR \ General Purpose IO Register 1 bis
+&62 constant GPIOR0 \ General Purpose IO Register 0
+ $80 constant GPIOR0_GPIOR07 \ General Purpose IO Register 0 bit 7
+ $40 constant GPIOR0_GPIOR06 \ General Purpose IO Register 0 bit 6
+ $20 constant GPIOR0_GPIOR05 \ General Purpose IO Register 0 bit 5
+ $10 constant GPIOR0_GPIOR04 \ General Purpose IO Register 0 bit 4
+ $08 constant GPIOR0_GPIOR03 \ General Purpose IO Register 0 bit 3
+ $04 constant GPIOR0_GPIOR02 \ General Purpose IO Register 0 bit 2
+ $02 constant GPIOR0_GPIOR01 \ General Purpose IO Register 0 bit 1
+ $01 constant GPIOR0_GPIOR00 \ General Purpose IO Register 0 bit 0
+\ BOOT_LOAD
+&87 constant SPMCSR \ Store Program Memory Control Register
+ $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
+ $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
+ $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
+ $04 constant SPMCSR_PGWRT \ Page Write
+ $02 constant SPMCSR_PGERS \ Page Erase
+ $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
+\ EXTERNAL_INTERRUPT
+&105 constant EICRA \ External Interrupt Control Register A
+ $C0 constant EICRA_ISC3 \ External Interrupt Sense Control Bit
+ $30 constant EICRA_ISC2 \ External Interrupt Sense Control Bit
+ $0C constant EICRA_ISC1 \ External Interrupt Sense Control Bit
+ $03 constant EICRA_ISC0 \ External Interrupt Sense Control Bit
+&106 constant EICRB \ External Interrupt Control Register B
+ $C0 constant EICRB_ISC7 \ External Interrupt 7-4 Sense Control Bit
+ $30 constant EICRB_ISC6 \ External Interrupt 7-4 Sense Control Bit
+ $0C constant EICRB_ISC5 \ External Interrupt 7-4 Sense Control Bit
+ $03 constant EICRB_ISC4 \ External Interrupt 7-4 Sense Control Bit
+&61 constant EIMSK \ External Interrupt Mask Register
+ $FF constant EIMSK_INT \ External Interrupt Request 7 Enable
+&60 constant EIFR \ External Interrupt Flag Register
+ $FF constant EIFR_INTF \ External Interrupt Flags
+\ EEPROM
+&65 constant EEAR \ EEPROM Read/Write Access Bytes
+&64 constant EEDR \ EEPROM Data Register
+&63 constant EECR \ EEPROM Control Register
+ $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
+ $04 constant EECR_EEMWE \ EEPROM Master Write Enable
+ $02 constant EECR_EEWE \ EEPROM Write Enable
+ $01 constant EECR_EERE \ EEPROM Read Enable
+\ PORTG
+&52 constant PORTG \ Data Register, Port G
+&51 constant DDRG \ Data Direction Register, Port G
+&50 constant PING \ Input Pins, Port G
+\ TIMER_COUNTER_0
+&68 constant TCCR0A \ Timer/Counter0 Control Register
+ $80 constant TCCR0A_FOC0A \ Force Output Compare
+ $40 constant TCCR0A_WGM00 \ Waveform Generation Mode 0
+ $30 constant TCCR0A_COM0A \ Compare Match Output Modes
+ $08 constant TCCR0A_WGM01 \ Waveform Generation Mode 1
+ $07 constant TCCR0A_CS0 \ Clock Selects
+&70 constant TCNT0 \ Timer/Counter0
+&71 constant OCR0A \ Timer/Counter0 Output Compare Register
+&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
+ $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match Interrupt Enable
+ $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
+&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
+ $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0
+ $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
+&67 constant GTCCR \ General Timer/Control Register
+ $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
+ $01 constant GTCCR_PSR310 \ Prescaler Reset Timer/Counter1 and Timer/Counter0
+\ TIMER_COUNTER_1
+&128 constant TCCR1A \ Timer/Counter1 Control Register A
+ $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
+ $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
+ $0C constant TCCR1A_COM1C \ Compare Output Mode 1C, bits
+ $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
+&129 constant TCCR1B \ Timer/Counter1 Control Register B
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
+ $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
+&130 constant TCCR1C \ Timer/Counter 1 Control Register C
+ $80 constant TCCR1C_FOC1A \ Force Output Compare 1A
+ $40 constant TCCR1C_FOC1B \ Force Output Compare 1B
+ $20 constant TCCR1C_FOC1C \ Force Output Compare 1C
+&132 constant TCNT1 \ Timer/Counter1 Bytes
+&136 constant OCR1A \ Timer/Counter1 Output Compare Register Bytes
+&138 constant OCR1B \ Timer/Counter1 Output Compare Register Bytes
+&140 constant OCR1C \ Timer/Counter1 Output Compare Register Bytes
+&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
+&111 constant TIMSK1 \ Timer/Counter Interrupt Mask Register
+ $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
+ $08 constant TIMSK1_OCIE1C \ Timer/Counter1 Output CompareC Match Interrupt Enable
+ $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output CompareB Match Interrupt Enable
+ $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output CompareA Match Interrupt Enable
+ $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
+&54 constant TIFR1 \ Timer/Counter Interrupt Flag register
+ $20 constant TIFR1_ICF1 \ Input Capture Flag 1
+ $08 constant TIFR1_OCF1C \ Output Compare Flag 1C
+ $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
+ $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
+ $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
+\ TIMER_COUNTER_3
+&144 constant TCCR3A \ Timer/Counter3 Control Register A
+ $C0 constant TCCR3A_COM3A \ Compare Output Mode 3A, bits
+ $30 constant TCCR3A_COM3B \ Compare Output Mode 3B, bits
+ $0C constant TCCR3A_COM3C \ Compare Output Mode 3C, bits
+ $03 constant TCCR3A_WGM3 \ Waveform Generation Mode
+&145 constant TCCR3B \ Timer/Counter3 Control Register B
+ $80 constant TCCR3B_ICNC3 \ Input Capture 3 Noise Canceler
+ $40 constant TCCR3B_ICES3 \ Input Capture 3 Edge Select
+ $18 constant TCCR3B_WGM3 \ Waveform Generation Mode
+ $07 constant TCCR3B_CS3 \ Prescaler source of Timer/Counter 3
+&146 constant TCCR3C \ Timer/Counter 3 Control Register C
+ $80 constant TCCR3C_FOC3A \ Force Output Compare 3A
+ $40 constant TCCR3C_FOC3B \ Force Output Compare 3B
+ $20 constant TCCR3C_FOC3C \ Force Output Compare 3C
+&148 constant TCNT3 \ Timer/Counter3 Bytes
+&152 constant OCR3A \ Timer/Counter3 Output Compare Register Bytes
+&154 constant OCR3B \ Timer/Counter3 Output Compare Register Bytes
+&156 constant OCR3C \ Timer/Counter3 Output Compare Register Bytes
+&150 constant ICR3 \ Timer/Counter3 Input Capture Register Bytes
+&113 constant TIMSK3 \ Timer/Counter Interrupt Mask Register
+ $20 constant TIMSK3_ICIE3 \ Timer/Counter3 Input Capture Interrupt Enable
+ $08 constant TIMSK3_OCIE3C \ Timer/Counter3 Output CompareC Match Interrupt Enable
+ $04 constant TIMSK3_OCIE3B \ Timer/Counter3 Output CompareB Match Interrupt Enable
+ $02 constant TIMSK3_OCIE3A \ Timer/Counter3 Output CompareA Match Interrupt Enable
+ $01 constant TIMSK3_TOIE3 \ Timer/Counter3 Overflow Interrupt Enable
+&56 constant TIFR3 \ Timer/Counter Interrupt Flag register
+ $20 constant TIFR3_ICF3 \ Input Capture Flag 3
+ $08 constant TIFR3_OCF3C \ Output Compare Flag 3C
+ $04 constant TIFR3_OCF3B \ Output Compare Flag 3B
+ $02 constant TIFR3_OCF3A \ Output Compare Flag 3A
+ $01 constant TIFR3_TOV3 \ Timer/Counter3 Overflow Flag
+\ TIMER_COUNTER_2
+&176 constant TCCR2 \ Timer/Counter2 Control Register
+ $80 constant TCCR2_FOC2A \ Force Output Compare
+ $40 constant TCCR2_WGM20 \ Waveform Genration Mode
+ $30 constant TCCR2_COM2A \ Compare Output Mode bits
+ $08 constant TCCR2_WGM21 \ Waveform Generation Mode
+ $07 constant TCCR2_CS2 \ Clock Select bits
+&178 constant TCNT2 \ Timer/Counter2
+&179 constant OCR2A \ Timer/Counter2 Output Compare Register
+&112 constant TIMSK2 \ Timer/Counter Interrupt Mask register
+ $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match Interrupt Enable
+ $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
+&55 constant TIFR2 \ Timer/Counter Interrupt Flag Register
+ $02 constant TIFR2_OCF2A \ Output Compare Flag 2
+ $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
+&182 constant ASSR \ Asynchronous Status Register
+ $10 constant ASSR_EXCLK \ Enable External Clock Interrupt
+ $08 constant ASSR_AS2 \ AS2: Asynchronous Timer/Counter2
+ $04 constant ASSR_TCN2UB \ TCN2UB: Timer/Counter2 Update Busy
+ $02 constant ASSR_OCR2UB \ Output Compare Register2 Update Busy
+ $01 constant ASSR_TCR2UB \ TCR2UB: Timer/Counter Control Register2 Update Busy
+\ WATCHDOG
+&96 constant WDTCR \ Watchdog Timer Control Register
+ $10 constant WDTCR_WDCE \ Watchdog Change Enable
+ $08 constant WDTCR_WDE \ Watch Dog Enable
+ $07 constant WDTCR_WDP \ Watch Dog Timer Prescaler bits
+\ AD_CONVERTER
+&124 constant ADMUX \ The ADC multiplexer Selection Register
+ $C0 constant ADMUX_REFS \ Reference Selection Bits
+ $20 constant ADMUX_ADLAR \ Left Adjust Result
+ $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
+&122 constant ADCSRA \ The ADC Control and Status register
+ $80 constant ADCSRA_ADEN \ ADC Enable
+ $40 constant ADCSRA_ADSC \ ADC Start Conversion
+ $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
+ $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
+ $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
+ $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
+&120 constant ADC \ ADC Data Register Bytes
+&123 constant ADCSRB \ ADC Control and Status Register B
+ $80 constant ADCSRB_ADHSM \ ADC High Speed Mode
+ $07 constant ADCSRB_ADTS \ ADC Auto Trigger Sources
+&126 constant DIDR0 \ Digital Input Disable Register 1
+ $80 constant DIDR0_ADC7D \ ADC7 Digital input Disable
+ $40 constant DIDR0_ADC6D \ ADC6 Digital input Disable
+ $20 constant DIDR0_ADC5D \ ADC5 Digital input Disable
+ $10 constant DIDR0_ADC4D \ ADC4 Digital input Disable
+ $08 constant DIDR0_ADC3D \ ADC3 Digital input Disable
+ $04 constant DIDR0_ADC2D \ ADC2 Digital input Disable
+ $02 constant DIDR0_ADC1D \ ADC1 Digital input Disable
+ $01 constant DIDR0_ADC0D \ ADC0 Digital input Disable
+\ ANALOG_COMPARATOR
+&80 constant ACSR \ Analog Comparator Control And Status Register
+ $80 constant ACSR_ACD \ Analog Comparator Disable
+ $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
+ $20 constant ACSR_ACO \ Analog Compare Output
+ $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
+ $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
+ $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
+ $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
+&127 constant DIDR1 \
+ $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
+ $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
+\ CAN
+&216 constant CANGCON \ CAN General Control Register
+ $80 constant CANGCON_ABRQ \ Abort Request
+ $40 constant CANGCON_OVRQ \ Overload Frame Request
+ $20 constant CANGCON_TTC \ Time Trigger Communication
+ $10 constant CANGCON_SYNTTC \ Synchronization of TTC
+ $08 constant CANGCON_LISTEN \ Listening Mode
+ $04 constant CANGCON_TEST \ Test Mode
+ $02 constant CANGCON_ENASTB \ Enable / Standby
+ $01 constant CANGCON_SWRES \ Software Reset Request
+&217 constant CANGSTA \ CAN General Status Register
+ $40 constant CANGSTA_OVRG \ Overload Frame Flag
+ $10 constant CANGSTA_TXBSY \ Transmitter Busy
+ $08 constant CANGSTA_RXBSY \ Receiver Busy
+ $04 constant CANGSTA_ENFG \ Enable Flag
+ $02 constant CANGSTA_BOFF \ Bus Off Mode
+ $01 constant CANGSTA_ERRP \ Error Passive Mode
+&218 constant CANGIT \ CAN General Interrupt Register
+ $80 constant CANGIT_CANIT \ General Interrupt Flag
+ $40 constant CANGIT_BOFFIT \ Bus Off Interrupt Flag
+ $20 constant CANGIT_OVRTIM \ Overrun CAN Timer
+ $10 constant CANGIT_BXOK \ Burst Receive Interrupt
+ $08 constant CANGIT_SERG \ Stuff Error General
+ $04 constant CANGIT_CERG \ CRC Error General
+ $02 constant CANGIT_FERG \ Form Error General
+ $01 constant CANGIT_AERG \ Ackknowledgement Error General
+&219 constant CANGIE \ CAN General Interrupt Enable Register
+ $80 constant CANGIE_ENIT \ Enable all Interrupts
+ $40 constant CANGIE_ENBOFF \ Enable Bus Off INterrupt
+ $20 constant CANGIE_ENRX \ Enable Receive Interrupt
+ $10 constant CANGIE_ENTX \ Enable Transmitt Interrupt
+ $08 constant CANGIE_ENERR \ Enable MOb Error Interrupt
+ $04 constant CANGIE_ENBX \ Enable Burst Receive Interrupt
+ $02 constant CANGIE_ENERG \ Enable General Error Interrupt
+ $01 constant CANGIE_ENOVRT \ Enable CAN Timer Overrun Interrupt
+&220 constant CANEN2 \ Enable MOb Register
+&221 constant CANEN1 \ Enable MOb Register
+&222 constant CANIE2 \ Enable Interrupt MOb Register
+&223 constant CANIE1 \ Enable Interrupt MOb Register
+&224 constant CANSIT2 \ CAN Status Interrupt MOb Register
+&225 constant CANSIT1 \ CAN Status Interrupt MOb Register
+&226 constant CANBT1 \ Bit Timing Register 1
+ $7E constant CANBT1_BRP \ Baud Rate Prescaler bits
+&227 constant CANBT2 \ Bit Timing Register 2
+ $60 constant CANBT2_SJW \ Re-Sync Jump Width
+ $0E constant CANBT2_PRS \ Propagation Time Segment
+&228 constant CANBT3 \ Bit Timing Register 3
+ $70 constant CANBT3_PHS2 \ Phase Segments
+ $0E constant CANBT3_PHS1 \ Phase Segment 1
+ $01 constant CANBT3_SMP \ Sample Type
+&229 constant CANTCON \ Timer Control Register
+&230 constant CANTIML \ Timer Register Low
+&231 constant CANTIMH \ Timer Register High
+&232 constant CANTTCL \ TTC Timer Register Low
+&233 constant CANTTCH \ TTC Timer Register High
+&234 constant CANTEC \ Transmit Error Counter Register
+&235 constant CANREC \ Receive Error Counter Register
+&236 constant CANHPMOB \ Highest Priority MOb Register
+&237 constant CANPAGE \ Page MOb Register
+ $F0 constant CANPAGE_MOBNB \ MOb Number Bits
+ $08 constant CANPAGE_AINC \ MOb Data Buffer Auto Increment
+ $07 constant CANPAGE_INDX \ Data Buffer Index Bits
+&238 constant CANSTMOB \ MOb Status Register
+ $80 constant CANSTMOB_DLCW \ Data Length Code Warning
+ $40 constant CANSTMOB_TXOK \ Transmit OK
+ $20 constant CANSTMOB_RXOK \ Receive OK
+ $10 constant CANSTMOB_BERR \ Bit Error
+ $08 constant CANSTMOB_SERR \ Stuff Error
+ $04 constant CANSTMOB_CERR \ CRC Error
+ $02 constant CANSTMOB_FERR \ Form Error
+ $01 constant CANSTMOB_AERR \ Ackknowledgement Error
+&239 constant CANCDMOB \ MOb Control and DLC Register
+ $C0 constant CANCDMOB_CONMOB \ MOb Config Bits
+ $20 constant CANCDMOB_RPLV \ Reply Valid
+ $10 constant CANCDMOB_IDE \ Identifier Extension
+ $0F constant CANCDMOB_DLC \ Data Length Code Bits
+&240 constant CANIDT4 \ Identifier Tag Register 4
+&241 constant CANIDT3 \ Identifier Tag Register 3
+&242 constant CANIDT2 \ Identifier Tag Register 2
+&243 constant CANIDT1 \ Identifier Tag Register 1
+&244 constant CANIDM4 \ Identifier Mask Register 4
+&245 constant CANIDM3 \ Identifier Mask Register 3
+&246 constant CANIDM2 \ Identifier Mask Register 2
+&247 constant CANIDM1 \ Identifier Mask Register 1
+&248 constant CANSTML \ Time Stamp Register Low
+&249 constant CANSTMH \ Time Stamp Register High
+&250 constant CANMSG \ Message Data Register
+
+\ Interrupts
+&2 constant INT0Addr \ External Interrupt Request 0
+&4 constant INT1Addr \ External Interrupt Request 1
+&6 constant INT2Addr \ External Interrupt Request 2
+&8 constant INT3Addr \ External Interrupt Request 3
+&10 constant INT4Addr \ External Interrupt Request 4
+&12 constant INT5Addr \ External Interrupt Request 5
+&14 constant INT6Addr \ External Interrupt Request 6
+&16 constant INT7Addr \ External Interrupt Request 7
+&18 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
+&20 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
+&22 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+&24 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
+&26 constant TIMER1_COMPBAddr \ Timer/Counter Compare Match B
+&28 constant TIMER1_COMPCAddr \ Timer/Counter1 Compare Match C
+&30 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+&32 constant TIMER0_COMPAddr \ Timer/Counter0 Compare Match
+&34 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
+&36 constant CANITAddr \ CAN Transfer Complete or Error
+&38 constant OVRITAddr \ CAN Timer Overrun
+&40 constant SPI__STCAddr \ SPI Serial Transfer Complete
+&42 constant USART0__RXAddr \ USART0, Rx Complete
+&44 constant USART0__UDREAddr \ USART0 Data Register Empty
+&46 constant USART0__TXAddr \ USART0, Tx Complete
+&48 constant ANALOG_COMPAddr \ Analog Comparator
+&50 constant ADCAddr \ ADC Conversion Complete
+&52 constant EE_READYAddr \ EEPROM Ready
+&54 constant TIMER3_CAPTAddr \ Timer/Counter3 Capture Event
+&56 constant TIMER3_COMPAAddr \ Timer/Counter3 Compare Match A
+&58 constant TIMER3_COMPBAddr \ Timer/Counter3 Compare Match B
+&60 constant TIMER3_COMPCAddr \ Timer/Counter3 Compare Match C
+&62 constant TIMER3_OVFAddr \ Timer/Counter3 Overflow
+&64 constant USART1__RXAddr \ USART1, Rx Complete
+&66 constant USART1__UDREAddr \ USART1, Data Register Empty
+&68 constant USART1__TXAddr \ USART1, Tx Complete
+&70 constant TWIAddr \ 2-wire Serial Interface
+&72 constant SPM_READYAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/at90can128/device.asm b/amforth-6.5/avr8/devices/at90can128/device.asm
new file mode 100644
index 0000000..e669742
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90can128/device.asm
@@ -0,0 +1,145 @@
+; Partname: AT90CAN128
+; generated automatically, do not edit
+
+.nolist
+ .include "can128def.inc"
+.list
+
+.equ ramstart = 256
+.equ CELLSIZE = 2
+.macro readflashcell
+ clr temp7
+ lsl zl
+ rol zh
+ rol temp7
+ out_ RAMPZ, temp7
+ elpm @0, Z+
+ elpm @1, Z+
+.endmacro
+.macro writeflashcell
+ clr temp7
+ lsl zl
+ rol zh
+ rol temp7
+ out_ RAMPZ, temp7
+.endmacro
+.set WANT_PORTA = 0
+.set WANT_PORTB = 0
+.set WANT_PORTC = 0
+.set WANT_PORTD = 0
+.set WANT_PORTE = 0
+.set WANT_PORTF = 0
+.set WANT_JTAG = 0
+.set WANT_SPI = 0
+.set WANT_TWI = 0
+.set WANT_USART0 = 0
+.set WANT_USART1 = 0
+.set WANT_CPU = 0
+.set WANT_BOOT_LOAD = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_EEPROM = 0
+.set WANT_PORTG = 0
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_TIMER_COUNTER_3 = 0
+.set WANT_TIMER_COUNTER_2 = 0
+.set WANT_WATCHDOG = 0
+.set WANT_AD_CONVERTER = 0
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_CAN = 0
+.equ intvecsize = 2 ; please verify; flash size: 131072 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.org 2
+ rcall isr ; External Interrupt Request 0
+.org 4
+ rcall isr ; External Interrupt Request 1
+.org 6
+ rcall isr ; External Interrupt Request 2
+.org 8
+ rcall isr ; External Interrupt Request 3
+.org 10
+ rcall isr ; External Interrupt Request 4
+.org 12
+ rcall isr ; External Interrupt Request 5
+.org 14
+ rcall isr ; External Interrupt Request 6
+.org 16
+ rcall isr ; External Interrupt Request 7
+.org 18
+ rcall isr ; Timer/Counter2 Compare Match
+.org 20
+ rcall isr ; Timer/Counter2 Overflow
+.org 22
+ rcall isr ; Timer/Counter1 Capture Event
+.org 24
+ rcall isr ; Timer/Counter1 Compare Match A
+.org 26
+ rcall isr ; Timer/Counter Compare Match B
+.org 28
+ rcall isr ; Timer/Counter1 Compare Match C
+.org 30
+ rcall isr ; Timer/Counter1 Overflow
+.org 32
+ rcall isr ; Timer/Counter0 Compare Match
+.org 34
+ rcall isr ; Timer/Counter0 Overflow
+.org 36
+ rcall isr ; CAN Transfer Complete or Error
+.org 38
+ rcall isr ; CAN Timer Overrun
+.org 40
+ rcall isr ; SPI Serial Transfer Complete
+.org 42
+ rcall isr ; USART0, Rx Complete
+.org 44
+ rcall isr ; USART0 Data Register Empty
+.org 46
+ rcall isr ; USART0, Tx Complete
+.org 48
+ rcall isr ; Analog Comparator
+.org 50
+ rcall isr ; ADC Conversion Complete
+.org 52
+ rcall isr ; EEPROM Ready
+.org 54
+ rcall isr ; Timer/Counter3 Capture Event
+.org 56
+ rcall isr ; Timer/Counter3 Compare Match A
+.org 58
+ rcall isr ; Timer/Counter3 Compare Match B
+.org 60
+ rcall isr ; Timer/Counter3 Compare Match C
+.org 62
+ rcall isr ; Timer/Counter3 Overflow
+.org 64
+ rcall isr ; USART1, Rx Complete
+.org 66
+ rcall isr ; USART1, Data Register Empty
+.org 68
+ rcall isr ; USART1, Tx Complete
+.org 70
+ rcall isr ; 2-wire Serial Interface
+.org 72
+ rcall isr ; Store Program Memory Read
+.equ INTVECTORS = 37
+.nooverlap
+
+; compatability layer (maybe empty)
+.equ EEPE = EEWE
+.equ EEMPE = EEMWE
+
+; controller data area, environment query mcu-info
+mcu_info:
+mcu_ramsize:
+ .dw 4096
+mcu_eepromsize:
+ .dw 4096
+mcu_maxdp:
+ .dw 65535
+mcu_numints:
+ .dw 37
+mcu_name:
+ .dw 10
+ .db "AT90CAN128"
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/at90can128/device.inc b/amforth-6.5/avr8/devices/at90can128/device.inc
new file mode 100644
index 0000000..59c6d52
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90can128/device.inc
@@ -0,0 +1,1707 @@
+; Partname: AT90CAN128
+; generated automatically, no not edit
+
+.if WANT_PORTA == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Register
+VE_PORTA:
+ .dw $ff05
+ .db "PORTA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTA
+XT_PORTA:
+ .dw PFA_DOVARIABLE
+PFA_PORTA:
+ .dw 34
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Direction Register
+VE_DDRA:
+ .dw $ff04
+ .db "DDRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRA
+XT_DDRA:
+ .dw PFA_DOVARIABLE
+PFA_DDRA:
+ .dw 33
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Input Pins
+VE_PINA:
+ .dw $ff04
+ .db "PINA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINA
+XT_PINA:
+ .dw PFA_DOVARIABLE
+PFA_PINA:
+ .dw 32
+
+.endif
+.if WANT_PORTB == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw 37
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw 36
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw 35
+
+.endif
+.if WANT_PORTC == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Register
+VE_PORTC:
+ .dw $ff05
+ .db "PORTC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTC
+XT_PORTC:
+ .dw PFA_DOVARIABLE
+PFA_PORTC:
+ .dw 40
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Direction Register
+VE_DDRC:
+ .dw $ff04
+ .db "DDRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRC
+XT_DDRC:
+ .dw PFA_DOVARIABLE
+PFA_DDRC:
+ .dw 39
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Input Pins
+VE_PINC:
+ .dw $ff04
+ .db "PINC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINC
+XT_PINC:
+ .dw PFA_DOVARIABLE
+PFA_PINC:
+ .dw 38
+
+.endif
+.if WANT_PORTD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw 43
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw 42
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw 41
+
+.endif
+.if WANT_PORTE == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port E
+VE_PORTE:
+ .dw $ff05
+ .db "PORTE",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTE
+XT_PORTE:
+ .dw PFA_DOVARIABLE
+PFA_PORTE:
+ .dw 46
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port E
+VE_DDRE:
+ .dw $ff04
+ .db "DDRE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRE
+XT_DDRE:
+ .dw PFA_DOVARIABLE
+PFA_DDRE:
+ .dw 45
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port E
+VE_PINE:
+ .dw $ff04
+ .db "PINE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINE
+XT_PINE:
+ .dw PFA_DOVARIABLE
+PFA_PINE:
+ .dw 44
+
+.endif
+.if WANT_PORTF == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port F
+VE_PORTF:
+ .dw $ff05
+ .db "PORTF",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTF
+XT_PORTF:
+ .dw PFA_DOVARIABLE
+PFA_PORTF:
+ .dw 49
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port F
+VE_DDRF:
+ .dw $ff04
+ .db "DDRF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRF
+XT_DDRF:
+ .dw PFA_DOVARIABLE
+PFA_DDRF:
+ .dw 48
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port F
+VE_PINF:
+ .dw $ff04
+ .db "PINF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINF
+XT_PINF:
+ .dw PFA_DOVARIABLE
+PFA_PINF:
+ .dw 47
+
+.endif
+.if WANT_JTAG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; On-Chip Debug Related Register in I/O Memory
+VE_OCDR:
+ .dw $ff04
+ .db "OCDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCDR
+XT_OCDR:
+ .dw PFA_DOVARIABLE
+PFA_OCDR:
+ .dw 81
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw 85
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Status Register
+VE_MCUSR:
+ .dw $ff05
+ .db "MCUSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUSR
+XT_MCUSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUSR:
+ .dw 84
+
+.endif
+.if WANT_SPI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR:
+ .dw $ff04
+ .db "SPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR
+XT_SPCR:
+ .dw PFA_DOVARIABLE
+PFA_SPCR:
+ .dw 76
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR:
+ .dw $ff04
+ .db "SPSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR
+XT_SPSR:
+ .dw PFA_DOVARIABLE
+PFA_SPSR:
+ .dw 77
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR:
+ .dw $ff04
+ .db "SPDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR
+XT_SPDR:
+ .dw PFA_DOVARIABLE
+PFA_SPDR:
+ .dw 78
+
+.endif
+.if WANT_TWI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Bit Rate register
+VE_TWBR:
+ .dw $ff04
+ .db "TWBR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWBR
+XT_TWBR:
+ .dw PFA_DOVARIABLE
+PFA_TWBR:
+ .dw 184
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Control Register
+VE_TWCR:
+ .dw $ff04
+ .db "TWCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWCR
+XT_TWCR:
+ .dw PFA_DOVARIABLE
+PFA_TWCR:
+ .dw 188
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Status Register
+VE_TWSR:
+ .dw $ff04
+ .db "TWSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWSR
+XT_TWSR:
+ .dw PFA_DOVARIABLE
+PFA_TWSR:
+ .dw 185
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Data register
+VE_TWDR:
+ .dw $ff04
+ .db "TWDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWDR
+XT_TWDR:
+ .dw PFA_DOVARIABLE
+PFA_TWDR:
+ .dw 187
+; ( -- addr ) System Constant
+; R( -- )
+; TWI (Slave) Address register
+VE_TWAR:
+ .dw $ff04
+ .db "TWAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWAR
+XT_TWAR:
+ .dw PFA_DOVARIABLE
+PFA_TWAR:
+ .dw 186
+
+.endif
+.if WANT_USART0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR0:
+ .dw $ff04
+ .db "UDR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR0
+XT_UDR0:
+ .dw PFA_DOVARIABLE
+PFA_UDR0:
+ .dw 198
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR0A:
+ .dw $ff06
+ .db "UCSR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0A
+XT_UCSR0A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0A:
+ .dw 192
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR0B:
+ .dw $ff06
+ .db "UCSR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0B
+XT_UCSR0B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0B:
+ .dw 193
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR0C:
+ .dw $ff06
+ .db "UCSR0C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0C
+XT_UCSR0C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0C:
+ .dw 194
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register t Bytes
+VE_UBRR0:
+ .dw $ff05
+ .db "UBRR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR0
+XT_UBRR0:
+ .dw PFA_DOVARIABLE
+PFA_UBRR0:
+ .dw 196
+
+.endif
+.if WANT_USART1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR1:
+ .dw $ff04
+ .db "UDR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR1
+XT_UDR1:
+ .dw PFA_DOVARIABLE
+PFA_UDR1:
+ .dw 206
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR1A:
+ .dw $ff06
+ .db "UCSR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1A
+XT_UCSR1A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1A:
+ .dw 200
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR1B:
+ .dw $ff06
+ .db "UCSR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1B
+XT_UCSR1B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1B:
+ .dw 201
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR1C:
+ .dw $ff06
+ .db "UCSR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1C
+XT_UCSR1C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1C:
+ .dw 202
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register t Bytes
+VE_UBRR1:
+ .dw $ff05
+ .db "UBRR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR1
+XT_UBRR1:
+ .dw PFA_DOVARIABLE
+PFA_UBRR1:
+ .dw 204
+
+.endif
+.if WANT_CPU == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw 95
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer
+VE_SP:
+ .dw $ff02
+ .db "SP"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SP
+XT_SP:
+ .dw PFA_DOVARIABLE
+PFA_SP:
+ .dw 93
+; ( -- addr ) System Constant
+; R( -- )
+; External Memory Control Register A
+VE_XMCRA:
+ .dw $ff05
+ .db "XMCRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_XMCRA
+XT_XMCRA:
+ .dw PFA_DOVARIABLE
+PFA_XMCRA:
+ .dw 116
+; ( -- addr ) System Constant
+; R( -- )
+; External Memory Control Register B
+VE_XMCRB:
+ .dw $ff05
+ .db "XMCRB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_XMCRB
+XT_XMCRB:
+ .dw PFA_DOVARIABLE
+PFA_XMCRB:
+ .dw 117
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Calibration Value
+VE_OSCCAL:
+ .dw $ff06
+ .db "OSCCAL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSCCAL
+XT_OSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_OSCCAL:
+ .dw 102
+; ( -- addr ) System Constant
+; R( -- )
+; Clock Prescale Register
+VE_CLKPR:
+ .dw $ff05
+ .db "CLKPR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKPR
+XT_CLKPR:
+ .dw PFA_DOVARIABLE
+PFA_CLKPR:
+ .dw 97
+; ( -- addr ) System Constant
+; R( -- )
+; Sleep Mode Control Register
+VE_SMCR:
+ .dw $ff04
+ .db "SMCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SMCR
+XT_SMCR:
+ .dw PFA_DOVARIABLE
+PFA_SMCR:
+ .dw 83
+; ( -- addr ) System Constant
+; R( -- )
+; RAM Page Z Select Register
+VE_RAMPZ:
+ .dw $ff05
+ .db "RAMPZ",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_RAMPZ
+XT_RAMPZ:
+ .dw PFA_DOVARIABLE
+PFA_RAMPZ:
+ .dw 91
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 2
+VE_GPIOR2:
+ .dw $ff06
+ .db "GPIOR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR2
+XT_GPIOR2:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR2:
+ .dw 75
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 1
+VE_GPIOR1:
+ .dw $ff06
+ .db "GPIOR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR1
+XT_GPIOR1:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR1:
+ .dw 74
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 0
+VE_GPIOR0:
+ .dw $ff06
+ .db "GPIOR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR0
+XT_GPIOR0:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR0:
+ .dw 62
+
+.endif
+.if WANT_BOOT_LOAD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control Register
+VE_SPMCSR:
+ .dw $ff06
+ .db "SPMCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCSR
+XT_SPMCSR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCSR:
+ .dw 87
+
+.endif
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register A
+VE_EICRA:
+ .dw $ff05
+ .db "EICRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRA
+XT_EICRA:
+ .dw PFA_DOVARIABLE
+PFA_EICRA:
+ .dw 105
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register B
+VE_EICRB:
+ .dw $ff05
+ .db "EICRB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRB
+XT_EICRB:
+ .dw PFA_DOVARIABLE
+PFA_EICRB:
+ .dw 106
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Mask Register
+VE_EIMSK:
+ .dw $ff05
+ .db "EIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIMSK
+XT_EIMSK:
+ .dw PFA_DOVARIABLE
+PFA_EIMSK:
+ .dw 61
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Flag Register
+VE_EIFR:
+ .dw $ff04
+ .db "EIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIFR
+XT_EIFR:
+ .dw PFA_DOVARIABLE
+PFA_EIFR:
+ .dw 60
+
+.endif
+.if WANT_EEPROM == 1
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Read/Write Access Bytes
+VE_EEAR:
+ .dw $ff04
+ .db "EEAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEAR
+XT_EEAR:
+ .dw PFA_DOVARIABLE
+PFA_EEAR:
+ .dw 65
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw 64
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw 63
+
+.endif
+.if WANT_PORTG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port G
+VE_PORTG:
+ .dw $ff05
+ .db "PORTG",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTG
+XT_PORTG:
+ .dw PFA_DOVARIABLE
+PFA_PORTG:
+ .dw 52
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port G
+VE_DDRG:
+ .dw $ff04
+ .db "DDRG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRG
+XT_DDRG:
+ .dw PFA_DOVARIABLE
+PFA_DDRG:
+ .dw 51
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port G
+VE_PING:
+ .dw $ff04
+ .db "PING"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PING
+XT_PING:
+ .dw PFA_DOVARIABLE
+PFA_PING:
+ .dw 50
+
+.endif
+.if WANT_TIMER_COUNTER_0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Control Register
+VE_TCCR0A:
+ .dw $ff06
+ .db "TCCR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0A
+XT_TCCR0A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0A:
+ .dw 68
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw 70
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0A:
+ .dw $ff05
+ .db "OCR0A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0A
+XT_OCR0A:
+ .dw PFA_DOVARIABLE
+PFA_OCR0A:
+ .dw 71
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Mask Register
+VE_TIMSK0:
+ .dw $ff06
+ .db "TIMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK0
+XT_TIMSK0:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK0:
+ .dw 110
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Flag register
+VE_TIFR0:
+ .dw $ff05
+ .db "TIFR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR0
+XT_TIFR0:
+ .dw PFA_DOVARIABLE
+PFA_TIFR0:
+ .dw 53
+; ( -- addr ) System Constant
+; R( -- )
+; General Timer/Control Register
+VE_GTCCR:
+ .dw $ff05
+ .db "GTCCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GTCCR
+XT_GTCCR:
+ .dw PFA_DOVARIABLE
+PFA_GTCCR:
+ .dw 67
+
+.endif
+.if WANT_TIMER_COUNTER_1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw 128
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw 129
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter 1 Control Register C
+VE_TCCR1C:
+ .dw $ff06
+ .db "TCCR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1C
+XT_TCCR1C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1C:
+ .dw 130
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Bytes
+VE_TCNT1:
+ .dw $ff05
+ .db "TCNT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1
+XT_TCNT1:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1:
+ .dw 132
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register Bytes
+VE_OCR1A:
+ .dw $ff05
+ .db "OCR1A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1A
+XT_OCR1A:
+ .dw PFA_DOVARIABLE
+PFA_OCR1A:
+ .dw 136
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register Bytes
+VE_OCR1B:
+ .dw $ff05
+ .db "OCR1B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1B
+XT_OCR1B:
+ .dw PFA_DOVARIABLE
+PFA_OCR1B:
+ .dw 138
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register Bytes
+VE_OCR1C:
+ .dw $ff05
+ .db "OCR1C",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1C
+XT_OCR1C:
+ .dw PFA_DOVARIABLE
+PFA_OCR1C:
+ .dw 140
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Bytes
+VE_ICR1:
+ .dw $ff04
+ .db "ICR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1
+XT_ICR1:
+ .dw PFA_DOVARIABLE
+PFA_ICR1:
+ .dw 134
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Mask Register
+VE_TIMSK1:
+ .dw $ff06
+ .db "TIMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK1
+XT_TIMSK1:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK1:
+ .dw 111
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Flag register
+VE_TIFR1:
+ .dw $ff05
+ .db "TIFR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR1
+XT_TIFR1:
+ .dw PFA_DOVARIABLE
+PFA_TIFR1:
+ .dw 54
+
+.endif
+.if WANT_TIMER_COUNTER_3 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Control Register A
+VE_TCCR3A:
+ .dw $ff06
+ .db "TCCR3A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR3A
+XT_TCCR3A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR3A:
+ .dw 144
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Control Register B
+VE_TCCR3B:
+ .dw $ff06
+ .db "TCCR3B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR3B
+XT_TCCR3B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR3B:
+ .dw 145
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter 3 Control Register C
+VE_TCCR3C:
+ .dw $ff06
+ .db "TCCR3C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR3C
+XT_TCCR3C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR3C:
+ .dw 146
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Bytes
+VE_TCNT3:
+ .dw $ff05
+ .db "TCNT3",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT3
+XT_TCNT3:
+ .dw PFA_DOVARIABLE
+PFA_TCNT3:
+ .dw 148
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Output Compare Register Bytes
+VE_OCR3A:
+ .dw $ff05
+ .db "OCR3A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR3A
+XT_OCR3A:
+ .dw PFA_DOVARIABLE
+PFA_OCR3A:
+ .dw 152
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Output Compare Register Bytes
+VE_OCR3B:
+ .dw $ff05
+ .db "OCR3B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR3B
+XT_OCR3B:
+ .dw PFA_DOVARIABLE
+PFA_OCR3B:
+ .dw 154
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Output Compare Register Bytes
+VE_OCR3C:
+ .dw $ff05
+ .db "OCR3C",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR3C
+XT_OCR3C:
+ .dw PFA_DOVARIABLE
+PFA_OCR3C:
+ .dw 156
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Input Capture Register Bytes
+VE_ICR3:
+ .dw $ff04
+ .db "ICR3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR3
+XT_ICR3:
+ .dw PFA_DOVARIABLE
+PFA_ICR3:
+ .dw 150
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Mask Register
+VE_TIMSK3:
+ .dw $ff06
+ .db "TIMSK3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK3
+XT_TIMSK3:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK3:
+ .dw 113
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Flag register
+VE_TIFR3:
+ .dw $ff05
+ .db "TIFR3",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR3
+XT_TIFR3:
+ .dw PFA_DOVARIABLE
+PFA_TIFR3:
+ .dw 56
+
+.endif
+.if WANT_TIMER_COUNTER_2 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register
+VE_TCCR2:
+ .dw $ff05
+ .db "TCCR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2
+XT_TCCR2:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2:
+ .dw 176
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2
+VE_TCNT2:
+ .dw $ff05
+ .db "TCNT2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT2
+XT_TCNT2:
+ .dw PFA_DOVARIABLE
+PFA_TCNT2:
+ .dw 178
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register
+VE_OCR2A:
+ .dw $ff05
+ .db "OCR2A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2A
+XT_OCR2A:
+ .dw PFA_DOVARIABLE
+PFA_OCR2A:
+ .dw 179
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Mask register
+VE_TIMSK2:
+ .dw $ff06
+ .db "TIMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK2
+XT_TIMSK2:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK2:
+ .dw 112
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Flag Register
+VE_TIFR2:
+ .dw $ff05
+ .db "TIFR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR2
+XT_TIFR2:
+ .dw PFA_DOVARIABLE
+PFA_TIFR2:
+ .dw 55
+; ( -- addr ) System Constant
+; R( -- )
+; Asynchronous Status Register
+VE_ASSR:
+ .dw $ff04
+ .db "ASSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ASSR
+XT_ASSR:
+ .dw PFA_DOVARIABLE
+PFA_ASSR:
+ .dw 182
+
+.endif
+.if WANT_WATCHDOG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCR:
+ .dw $ff05
+ .db "WDTCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCR
+XT_WDTCR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCR:
+ .dw 96
+
+.endif
+.if WANT_AD_CONVERTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC multiplexer Selection Register
+VE_ADMUX:
+ .dw $ff05
+ .db "ADMUX",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADMUX
+XT_ADMUX:
+ .dw PFA_DOVARIABLE
+PFA_ADMUX:
+ .dw 124
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register
+VE_ADCSRA:
+ .dw $ff06
+ .db "ADCSRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRA
+XT_ADCSRA:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRA:
+ .dw 122
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register Bytes
+VE_ADC:
+ .dw $ff03
+ .db "ADC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADC
+XT_ADC:
+ .dw PFA_DOVARIABLE
+PFA_ADC:
+ .dw 120
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Control and Status Register B
+VE_ADCSRB:
+ .dw $ff06
+ .db "ADCSRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRB
+XT_ADCSRB:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRB:
+ .dw 123
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 1
+VE_DIDR0:
+ .dw $ff05
+ .db "DIDR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR0
+XT_DIDR0:
+ .dw PFA_DOVARIABLE
+PFA_DIDR0:
+ .dw 126
+
+.endif
+.if WANT_ANALOG_COMPARATOR == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Control And Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw 80
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_DIDR1:
+ .dw $ff05
+ .db "DIDR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR1
+XT_DIDR1:
+ .dw PFA_DOVARIABLE
+PFA_DIDR1:
+ .dw 127
+
+.endif
+.if WANT_CAN == 1
+; ( -- addr ) System Constant
+; R( -- )
+; CAN General Control Register
+VE_CANGCON:
+ .dw $ff07
+ .db "CANGCON",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANGCON
+XT_CANGCON:
+ .dw PFA_DOVARIABLE
+PFA_CANGCON:
+ .dw 216
+; ( -- addr ) System Constant
+; R( -- )
+; CAN General Status Register
+VE_CANGSTA:
+ .dw $ff07
+ .db "CANGSTA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANGSTA
+XT_CANGSTA:
+ .dw PFA_DOVARIABLE
+PFA_CANGSTA:
+ .dw 217
+; ( -- addr ) System Constant
+; R( -- )
+; CAN General Interrupt Register
+VE_CANGIT:
+ .dw $ff06
+ .db "CANGIT"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANGIT
+XT_CANGIT:
+ .dw PFA_DOVARIABLE
+PFA_CANGIT:
+ .dw 218
+; ( -- addr ) System Constant
+; R( -- )
+; CAN General Interrupt Enable Register
+VE_CANGIE:
+ .dw $ff06
+ .db "CANGIE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANGIE
+XT_CANGIE:
+ .dw PFA_DOVARIABLE
+PFA_CANGIE:
+ .dw 219
+; ( -- addr ) System Constant
+; R( -- )
+; Enable MOb Register
+VE_CANEN2:
+ .dw $ff06
+ .db "CANEN2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANEN2
+XT_CANEN2:
+ .dw PFA_DOVARIABLE
+PFA_CANEN2:
+ .dw 220
+; ( -- addr ) System Constant
+; R( -- )
+; Enable MOb Register
+VE_CANEN1:
+ .dw $ff06
+ .db "CANEN1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANEN1
+XT_CANEN1:
+ .dw PFA_DOVARIABLE
+PFA_CANEN1:
+ .dw 221
+; ( -- addr ) System Constant
+; R( -- )
+; Enable Interrupt MOb Register
+VE_CANIE2:
+ .dw $ff06
+ .db "CANIE2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANIE2
+XT_CANIE2:
+ .dw PFA_DOVARIABLE
+PFA_CANIE2:
+ .dw 222
+; ( -- addr ) System Constant
+; R( -- )
+; Enable Interrupt MOb Register
+VE_CANIE1:
+ .dw $ff06
+ .db "CANIE1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANIE1
+XT_CANIE1:
+ .dw PFA_DOVARIABLE
+PFA_CANIE1:
+ .dw 223
+; ( -- addr ) System Constant
+; R( -- )
+; CAN Status Interrupt MOb Register
+VE_CANSIT2:
+ .dw $ff07
+ .db "CANSIT2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANSIT2
+XT_CANSIT2:
+ .dw PFA_DOVARIABLE
+PFA_CANSIT2:
+ .dw 224
+; ( -- addr ) System Constant
+; R( -- )
+; CAN Status Interrupt MOb Register
+VE_CANSIT1:
+ .dw $ff07
+ .db "CANSIT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANSIT1
+XT_CANSIT1:
+ .dw PFA_DOVARIABLE
+PFA_CANSIT1:
+ .dw 225
+; ( -- addr ) System Constant
+; R( -- )
+; Bit Timing Register 1
+VE_CANBT1:
+ .dw $ff06
+ .db "CANBT1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANBT1
+XT_CANBT1:
+ .dw PFA_DOVARIABLE
+PFA_CANBT1:
+ .dw 226
+; ( -- addr ) System Constant
+; R( -- )
+; Bit Timing Register 2
+VE_CANBT2:
+ .dw $ff06
+ .db "CANBT2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANBT2
+XT_CANBT2:
+ .dw PFA_DOVARIABLE
+PFA_CANBT2:
+ .dw 227
+; ( -- addr ) System Constant
+; R( -- )
+; Bit Timing Register 3
+VE_CANBT3:
+ .dw $ff06
+ .db "CANBT3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANBT3
+XT_CANBT3:
+ .dw PFA_DOVARIABLE
+PFA_CANBT3:
+ .dw 228
+; ( -- addr ) System Constant
+; R( -- )
+; Timer Control Register
+VE_CANTCON:
+ .dw $ff07
+ .db "CANTCON",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANTCON
+XT_CANTCON:
+ .dw PFA_DOVARIABLE
+PFA_CANTCON:
+ .dw 229
+; ( -- addr ) System Constant
+; R( -- )
+; Timer Register Low
+VE_CANTIML:
+ .dw $ff07
+ .db "CANTIML",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANTIML
+XT_CANTIML:
+ .dw PFA_DOVARIABLE
+PFA_CANTIML:
+ .dw 230
+; ( -- addr ) System Constant
+; R( -- )
+; Timer Register High
+VE_CANTIMH:
+ .dw $ff07
+ .db "CANTIMH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANTIMH
+XT_CANTIMH:
+ .dw PFA_DOVARIABLE
+PFA_CANTIMH:
+ .dw 231
+; ( -- addr ) System Constant
+; R( -- )
+; TTC Timer Register Low
+VE_CANTTCL:
+ .dw $ff07
+ .db "CANTTCL",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANTTCL
+XT_CANTTCL:
+ .dw PFA_DOVARIABLE
+PFA_CANTTCL:
+ .dw 232
+; ( -- addr ) System Constant
+; R( -- )
+; TTC Timer Register High
+VE_CANTTCH:
+ .dw $ff07
+ .db "CANTTCH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANTTCH
+XT_CANTTCH:
+ .dw PFA_DOVARIABLE
+PFA_CANTTCH:
+ .dw 233
+; ( -- addr ) System Constant
+; R( -- )
+; Transmit Error Counter Register
+VE_CANTEC:
+ .dw $ff06
+ .db "CANTEC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANTEC
+XT_CANTEC:
+ .dw PFA_DOVARIABLE
+PFA_CANTEC:
+ .dw 234
+; ( -- addr ) System Constant
+; R( -- )
+; Receive Error Counter Register
+VE_CANREC:
+ .dw $ff06
+ .db "CANREC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANREC
+XT_CANREC:
+ .dw PFA_DOVARIABLE
+PFA_CANREC:
+ .dw 235
+; ( -- addr ) System Constant
+; R( -- )
+; Highest Priority MOb Register
+VE_CANHPMOB:
+ .dw $ff08
+ .db "CANHPMOB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANHPMOB
+XT_CANHPMOB:
+ .dw PFA_DOVARIABLE
+PFA_CANHPMOB:
+ .dw 236
+; ( -- addr ) System Constant
+; R( -- )
+; Page MOb Register
+VE_CANPAGE:
+ .dw $ff07
+ .db "CANPAGE",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANPAGE
+XT_CANPAGE:
+ .dw PFA_DOVARIABLE
+PFA_CANPAGE:
+ .dw 237
+; ( -- addr ) System Constant
+; R( -- )
+; MOb Status Register
+VE_CANSTMOB:
+ .dw $ff08
+ .db "CANSTMOB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANSTMOB
+XT_CANSTMOB:
+ .dw PFA_DOVARIABLE
+PFA_CANSTMOB:
+ .dw 238
+; ( -- addr ) System Constant
+; R( -- )
+; MOb Control and DLC Register
+VE_CANCDMOB:
+ .dw $ff08
+ .db "CANCDMOB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANCDMOB
+XT_CANCDMOB:
+ .dw PFA_DOVARIABLE
+PFA_CANCDMOB:
+ .dw 239
+; ( -- addr ) System Constant
+; R( -- )
+; Identifier Tag Register 4
+VE_CANIDT4:
+ .dw $ff07
+ .db "CANIDT4",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANIDT4
+XT_CANIDT4:
+ .dw PFA_DOVARIABLE
+PFA_CANIDT4:
+ .dw 240
+; ( -- addr ) System Constant
+; R( -- )
+; Identifier Tag Register 3
+VE_CANIDT3:
+ .dw $ff07
+ .db "CANIDT3",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANIDT3
+XT_CANIDT3:
+ .dw PFA_DOVARIABLE
+PFA_CANIDT3:
+ .dw 241
+; ( -- addr ) System Constant
+; R( -- )
+; Identifier Tag Register 2
+VE_CANIDT2:
+ .dw $ff07
+ .db "CANIDT2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANIDT2
+XT_CANIDT2:
+ .dw PFA_DOVARIABLE
+PFA_CANIDT2:
+ .dw 242
+; ( -- addr ) System Constant
+; R( -- )
+; Identifier Tag Register 1
+VE_CANIDT1:
+ .dw $ff07
+ .db "CANIDT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANIDT1
+XT_CANIDT1:
+ .dw PFA_DOVARIABLE
+PFA_CANIDT1:
+ .dw 243
+; ( -- addr ) System Constant
+; R( -- )
+; Identifier Mask Register 4
+VE_CANIDM4:
+ .dw $ff07
+ .db "CANIDM4",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANIDM4
+XT_CANIDM4:
+ .dw PFA_DOVARIABLE
+PFA_CANIDM4:
+ .dw 244
+; ( -- addr ) System Constant
+; R( -- )
+; Identifier Mask Register 3
+VE_CANIDM3:
+ .dw $ff07
+ .db "CANIDM3",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANIDM3
+XT_CANIDM3:
+ .dw PFA_DOVARIABLE
+PFA_CANIDM3:
+ .dw 245
+; ( -- addr ) System Constant
+; R( -- )
+; Identifier Mask Register 2
+VE_CANIDM2:
+ .dw $ff07
+ .db "CANIDM2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANIDM2
+XT_CANIDM2:
+ .dw PFA_DOVARIABLE
+PFA_CANIDM2:
+ .dw 246
+; ( -- addr ) System Constant
+; R( -- )
+; Identifier Mask Register 1
+VE_CANIDM1:
+ .dw $ff07
+ .db "CANIDM1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANIDM1
+XT_CANIDM1:
+ .dw PFA_DOVARIABLE
+PFA_CANIDM1:
+ .dw 247
+; ( -- addr ) System Constant
+; R( -- )
+; Time Stamp Register Low
+VE_CANSTML:
+ .dw $ff07
+ .db "CANSTML",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANSTML
+XT_CANSTML:
+ .dw PFA_DOVARIABLE
+PFA_CANSTML:
+ .dw 248
+; ( -- addr ) System Constant
+; R( -- )
+; Time Stamp Register High
+VE_CANSTMH:
+ .dw $ff07
+ .db "CANSTMH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANSTMH
+XT_CANSTMH:
+ .dw PFA_DOVARIABLE
+PFA_CANSTMH:
+ .dw 249
+; ( -- addr ) System Constant
+; R( -- )
+; Message Data Register
+VE_CANMSG:
+ .dw $ff06
+ .db "CANMSG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANMSG
+XT_CANMSG:
+ .dw PFA_DOVARIABLE
+PFA_CANMSG:
+ .dw 250
+
+.endif
diff --git a/amforth-6.5/avr8/devices/at90can128/device.py b/amforth-6.5/avr8/devices/at90can128/device.py
new file mode 100644
index 0000000..778b42e
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90can128/device.py
@@ -0,0 +1,507 @@
+# Generated Automatically
+
+# Partname AT90CAN128
+
+MCUREGS = {
+# Interrupt Vectors
+ 'INT0Addr' : '#2', # External Interrupt Request 0
+ 'INT1Addr' : '#4', # External Interrupt Request 1
+ 'INT2Addr' : '#6', # External Interrupt Request 2
+ 'INT3Addr' : '#8', # External Interrupt Request 3
+ 'INT4Addr' : '#10', # External Interrupt Request 4
+ 'INT5Addr' : '#12', # External Interrupt Request 5
+ 'INT6Addr' : '#14', # External Interrupt Request 6
+ 'INT7Addr' : '#16', # External Interrupt Request 7
+ 'TIMER2_COMPAddr' : '#18', # Timer/Counter2 Compare Match
+ 'TIMER2_OVFAddr' : '#20', # Timer/Counter2 Overflow
+ 'TIMER1_CAPTAddr' : '#22', # Timer/Counter1 Capture Event
+ 'TIMER1_COMPAAddr' : '#24', # Timer/Counter1 Compare Match A
+ 'TIMER1_COMPBAddr' : '#26', # Timer/Counter Compare Match B
+ 'TIMER1_COMPCAddr' : '#28', # Timer/Counter1 Compare Match C
+ 'TIMER1_OVFAddr' : '#30', # Timer/Counter1 Overflow
+ 'TIMER0_COMPAddr' : '#32', # Timer/Counter0 Compare Match
+ 'TIMER0_OVFAddr' : '#34', # Timer/Counter0 Overflow
+ 'CANITAddr' : '#36', # CAN Transfer Complete or Error
+ 'OVRITAddr' : '#38', # CAN Timer Overrun
+ 'SPI_STCAddr' : '#40', # SPI Serial Transfer Complete
+ 'USART0_RXAddr' : '#42', # USART0, Rx Complete
+ 'USART0_UDREAddr' : '#44', # USART0 Data Register Empty
+ 'USART0_TXAddr' : '#46', # USART0, Tx Complete
+ 'ANALOG_COMPAddr' : '#48', # Analog Comparator
+ 'ADCAddr' : '#50', # ADC Conversion Complete
+ 'EE_READYAddr' : '#52', # EEPROM Ready
+ 'TIMER3_CAPTAddr' : '#54', # Timer/Counter3 Capture Event
+ 'TIMER3_COMPAAddr' : '#56', # Timer/Counter3 Compare Match A
+ 'TIMER3_COMPBAddr' : '#58', # Timer/Counter3 Compare Match B
+ 'TIMER3_COMPCAddr' : '#60', # Timer/Counter3 Compare Match C
+ 'TIMER3_OVFAddr' : '#62', # Timer/Counter3 Overflow
+ 'USART1_RXAddr' : '#64', # USART1, Rx Complete
+ 'USART1_UDREAddr' : '#66', # USART1, Data Register Empty
+ 'USART1_TXAddr' : '#68', # USART1, Tx Complete
+ 'TWIAddr' : '#70', # 2-wire Serial Interface
+ 'SPM_READYAddr' : '#72', # Store Program Memory Read
+
+# Module PORTA
+ 'PORTA' : '$22', # Port A Data Register
+ 'DDRA' : '$21', # Port A Data Direction Register
+ 'PINA' : '$20', # Port A Input Pins
+
+# Module PORTB
+ 'PORTB' : '$25', # Port B Data Register
+ 'DDRB' : '$24', # Port B Data Direction Register
+ 'PINB' : '$23', # Port B Input Pins
+
+# Module PORTC
+ 'PORTC' : '$28', # Port C Data Register
+ 'DDRC' : '$27', # Port C Data Direction Register
+ 'PINC' : '$26', # Port C Input Pins
+
+# Module PORTD
+ 'PORTD' : '$2b', # Port D Data Register
+ 'DDRD' : '$2a', # Port D Data Direction Register
+ 'PIND' : '$29', # Port D Input Pins
+
+# Module PORTE
+ 'PORTE' : '$2e', # Data Register, Port E
+ 'DDRE' : '$2d', # Data Direction Register, Port
+ 'PINE' : '$2c', # Input Pins, Port E
+
+# Module PORTF
+ 'PORTF' : '$31', # Data Register, Port F
+ 'DDRF' : '$30', # Data Direction Register, Port
+ 'PINF' : '$2f', # Input Pins, Port F
+
+# Module JTAG
+ 'OCDR' : '$51', # On-Chip Debug Related Register
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_JTD': '$80', # JTAG Interface Disable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+
+# Module SPI
+ 'SPCR' : '$4c', # SPI Control Register
+ 'SPCR_SPIE': '$80', # SPI Interrupt Enable
+ 'SPCR_SPE': '$40', # SPI Enable
+ 'SPCR_DORD': '$20', # Data Order
+ 'SPCR_MSTR': '$10', # Master/Slave Select
+ 'SPCR_CPOL': '$8', # Clock polarity
+ 'SPCR_CPHA': '$4', # Clock Phase
+ 'SPCR_SPR': '$3', # SPI Clock Rate Selects
+ 'SPSR' : '$4d', # SPI Status Register
+ 'SPSR_SPIF': '$80', # SPI Interrupt Flag
+ 'SPSR_WCOL': '$40', # Write Collision Flag
+ 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
+ 'SPDR' : '$4e', # SPI Data Register
+
+# Module TWI
+ 'TWBR' : '$b8', # TWI Bit Rate register
+ 'TWCR' : '$bc', # TWI Control Register
+ 'TWCR_TWINT': '$80', # TWI Interrupt Flag
+ 'TWCR_TWEA': '$40', # TWI Enable Acknowledge Bit
+ 'TWCR_TWSTA': '$20', # TWI Start Condition Bit
+ 'TWCR_TWSTO': '$10', # TWI Stop Condition Bit
+ 'TWCR_TWWC': '$8', # TWI Write Collition Flag
+ 'TWCR_TWEN': '$4', # TWI Enable Bit
+ 'TWCR_TWIE': '$1', # TWI Interrupt Enable
+ 'TWSR' : '$b9', # TWI Status Register
+ 'TWSR_TWS': '$f8', # TWI Status
+ 'TWSR_TWPS': '$3', # TWI Prescaler
+ 'TWDR' : '$bb', # TWI Data register
+ 'TWAR' : '$ba', # TWI (Slave) Address register
+ 'TWAR_TWA': '$fe', # TWI (Slave) Address register B
+ 'TWAR_TWGCE': '$1', # TWI General Call Recognition E
+
+# Module USART0
+ 'UDR0' : '$c6', # USART I/O Data Register
+ 'UCSR0A' : '$c0', # USART Control and Status Regis
+ 'UCSR0A_RXC0': '$80', # USART Receive Complete
+ 'UCSR0A_TXC0': '$40', # USART Transmitt Complete
+ 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
+ 'UCSR0A_FE0': '$10', # Framing Error
+ 'UCSR0A_DOR0': '$8', # Data overRun
+ 'UCSR0A_UPE0': '$4', # Parity Error
+ 'UCSR0A_U2X0': '$2', # Double the USART transmission
+ 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
+ 'UCSR0B' : '$c1', # USART Control and Status Regis
+ 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
+ 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
+ 'UCSR0B_UDRIE0': '$20', # USART Data register Empty Inte
+ 'UCSR0B_RXEN0': '$10', # Receiver Enable
+ 'UCSR0B_TXEN0': '$8', # Transmitter Enable
+ 'UCSR0B_UCSZ02': '$4', # Character Size
+ 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
+ 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
+ 'UCSR0C' : '$c2', # USART Control and Status Regis
+ 'UCSR0C_UMSEL0': '$40', # USART Mode Select
+ 'UCSR0C_UPM0': '$30', # Parity Mode Bits
+ 'UCSR0C_USBS0': '$8', # Stop Bit Select
+ 'UCSR0C_UCSZ0': '$6', # Character Size
+ 'UCSR0C_UCPOL0': '$1', # Clock Polarity
+ 'UBRR0' : '$c4', # USART Baud Rate Register t Byt
+
+# Module USART1
+ 'UDR1' : '$ce', # USART I/O Data Register
+ 'UCSR1A' : '$c8', # USART Control and Status Regis
+ 'UCSR1A_RXC1': '$80', # USART Receive Complete
+ 'UCSR1A_TXC1': '$40', # USART Transmitt Complete
+ 'UCSR1A_UDRE1': '$20', # USART Data Register Empty
+ 'UCSR1A_FE1': '$10', # Framing Error
+ 'UCSR1A_DOR1': '$8', # Data overRun
+ 'UCSR1A_UPE1': '$4', # Parity Error
+ 'UCSR1A_U2X1': '$2', # Double the USART transmission
+ 'UCSR1A_MPCM1': '$1', # Multi-processor Communication
+ 'UCSR1B' : '$c9', # USART Control and Status Regis
+ 'UCSR1B_RXCIE1': '$80', # RX Complete Interrupt Enable
+ 'UCSR1B_TXCIE1': '$40', # TX Complete Interrupt Enable
+ 'UCSR1B_UDRIE1': '$20', # USART Data register Empty Inte
+ 'UCSR1B_RXEN1': '$10', # Receiver Enable
+ 'UCSR1B_TXEN1': '$8', # Transmitter Enable
+ 'UCSR1B_UCSZ12': '$4', # Character Size
+ 'UCSR1B_RXB81': '$2', # Receive Data Bit 8
+ 'UCSR1B_TXB81': '$1', # Transmit Data Bit 8
+ 'UCSR1C' : '$ca', # USART Control and Status Regis
+ 'UCSR1C_UMSEL1': '$40', # USART Mode Select
+ 'UCSR1C_UPM1': '$30', # Parity Mode Bits
+ 'UCSR1C_USBS1': '$8', # Stop Bit Select
+ 'UCSR1C_UCSZ1': '$6', # Character Size
+ 'UCSR1C_UCPOL1': '$1', # Clock Polarity
+ 'UBRR1' : '$cc', # USART Baud Rate Register t Byt
+
+# Module CPU
+ 'SREG' : '$5f', # Status Register
+ 'SREG_I': '$80', # Global Interrupt Enable
+ 'SREG_T': '$40', # Bit Copy Storage
+ 'SREG_H': '$20', # Half Carry Flag
+ 'SREG_S': '$10', # Sign Bit
+ 'SREG_V': '$8', # Two's Complement Overflow Flag
+ 'SREG_N': '$4', # Negative Flag
+ 'SREG_Z': '$2', # Zero Flag
+ 'SREG_C': '$1', # Carry Flag
+ 'SP' : '$5d', # Stack Pointer
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_PUD': '$10', # Pull-up disable
+ 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
+ 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+ 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
+ 'MCUSR_BORF': '$4', # Brown-out Reset Flag
+ 'MCUSR_EXTRF': '$2', # External Reset Flag
+ 'MCUSR_PORF': '$1', # Power-on reset flag
+ 'XMCRA' : '$74', # External Memory Control Regist
+ 'XMCRA_SRE': '$80', # External SRAM Enable
+ 'XMCRA_SRL': '$70', # Wait state page limit
+ 'XMCRA_SRW1': '$c', # Wait state select bit upper pa
+ 'XMCRA_SRW0': '$3', # Wait state select bit lower pa
+ 'XMCRB' : '$75', # External Memory Control Regist
+ 'XMCRB_XMBK': '$80', # External Memory Bus Keeper Ena
+ 'XMCRB_XMM': '$7', # External Memory High Mask
+ 'OSCCAL' : '$66', # Oscillator Calibration Value
+ 'CLKPR' : '$61', # Clock Prescale Register
+ 'CLKPR_CLKPCE': '$80', #
+ 'CLKPR_CLKPS': '$f', #
+ 'SMCR' : '$53', # Sleep Mode Control Register
+ 'SMCR_SM': '$e', # Sleep Mode Select bits
+ 'SMCR_SE': '$1', # Sleep Enable
+ 'RAMPZ' : '$5b', # RAM Page Z Select Register
+ 'RAMPZ_RAMPZ0': '$1', # RAM Page Z Select Register Bit
+ 'GPIOR2' : '$4b', # General Purpose IO Register 2
+ 'GPIOR2_GPIOR': '$ff', # General Purpose IO Register 2
+ 'GPIOR1' : '$4a', # General Purpose IO Register 1
+ 'GPIOR1_GPIOR': '$ff', # General Purpose IO Register 1
+ 'GPIOR0' : '$3e', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR07': '$80', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR06': '$40', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR05': '$20', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR04': '$10', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR03': '$8', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR02': '$4', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR01': '$2', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR00': '$1', # General Purpose IO Register 0
+
+# Module BOOT_LOAD
+ 'SPMCSR' : '$57', # Store Program Memory Control R
+ 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
+ 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
+ 'SPMCSR_RWWSRE': '$10', # Read While Write section read
+ 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
+ 'SPMCSR_PGWRT': '$4', # Page Write
+ 'SPMCSR_PGERS': '$2', # Page Erase
+ 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
+
+# Module EXTERNAL_INTERRUPT
+ 'EICRA' : '$69', # External Interrupt Control Reg
+ 'EICRA_ISC3': '$c0', # External Interrupt Sense Contr
+ 'EICRA_ISC2': '$30', # External Interrupt Sense Contr
+ 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
+ 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
+ 'EICRB' : '$6a', # External Interrupt Control Reg
+ 'EICRB_ISC7': '$c0', # External Interrupt 7-4 Sense C
+ 'EICRB_ISC6': '$30', # External Interrupt 7-4 Sense C
+ 'EICRB_ISC5': '$c', # External Interrupt 7-4 Sense C
+ 'EICRB_ISC4': '$3', # External Interrupt 7-4 Sense C
+ 'EIMSK' : '$3d', # External Interrupt Mask Regist
+ 'EIMSK_INT': '$ff', # External Interrupt Request 7 E
+ 'EIFR' : '$3c', # External Interrupt Flag Regist
+ 'EIFR_INTF': '$ff', # External Interrupt Flags
+
+# Module EEPROM
+ 'EEAR' : '$41', # EEPROM Read/Write Access Byte
+ 'EEDR' : '$40', # EEPROM Data Register
+ 'EECR' : '$3f', # EEPROM Control Register
+ 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
+ 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
+ 'EECR_EEWE': '$2', # EEPROM Write Enable
+ 'EECR_EERE': '$1', # EEPROM Read Enable
+
+# Module PORTG
+ 'PORTG' : '$34', # Data Register, Port G
+ 'DDRG' : '$33', # Data Direction Register, Port
+ 'PING' : '$32', # Input Pins, Port G
+
+# Module TIMER_COUNTER_0
+ 'TCCR0A' : '$44', # Timer/Counter0 Control Registe
+ 'TCCR0A_FOC0A': '$80', # Force Output Compare
+ 'TCCR0A_WGM00': '$40', # Waveform Generation Mode 0
+ 'TCCR0A_COM0A': '$30', # Compare Match Output Modes
+ 'TCCR0A_WGM01': '$8', # Waveform Generation Mode 1
+ 'TCCR0A_CS0': '$7', # Clock Selects
+ 'TCNT0' : '$46', # Timer/Counter0
+ 'OCR0A' : '$47', # Timer/Counter0 Output Compare
+ 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
+ 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
+ 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
+ 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
+ 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
+ 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Control Register
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSR310': '$1', # Prescaler Reset Timer/Counter1
+
+# Module TIMER_COUNTER_1
+ 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
+ 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
+ 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
+ 'TCCR1A_COM1C': '$c', # Compare Output Mode 1C, bits
+ 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
+ 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
+ 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
+ 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
+ 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
+ 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
+ 'TCCR1C' : '$82', # Timer/Counter 1 Control Regist
+ 'TCCR1C_FOC1A': '$80', # Force Output Compare 1A
+ 'TCCR1C_FOC1B': '$40', # Force Output Compare 1B
+ 'TCCR1C_FOC1C': '$20', # Force Output Compare 1C
+ 'TCNT1' : '$84', # Timer/Counter1 Bytes
+ 'OCR1A' : '$88', # Timer/Counter1 Output Compare
+ 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
+ 'OCR1C' : '$8c', # Timer/Counter1 Output Compare
+ 'ICR1' : '$86', # Timer/Counter1 Input Capture R
+ 'TIMSK1' : '$6f', # Timer/Counter Interrupt Mask R
+ 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
+ 'TIMSK1_OCIE1C': '$8', # Timer/Counter1 Output CompareC
+ 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output CompareB
+ 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output CompareA
+ 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
+ 'TIFR1' : '$36', # Timer/Counter Interrupt Flag r
+ 'TIFR1_ICF1': '$20', # Input Capture Flag 1
+ 'TIFR1_OCF1C': '$8', # Output Compare Flag 1C
+ 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
+ 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
+ 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
+
+# Module TIMER_COUNTER_3
+ 'TCCR3A' : '$90', # Timer/Counter3 Control Registe
+ 'TCCR3A_COM3A': '$c0', # Compare Output Mode 3A, bits
+ 'TCCR3A_COM3B': '$30', # Compare Output Mode 3B, bits
+ 'TCCR3A_COM3C': '$c', # Compare Output Mode 3C, bits
+ 'TCCR3A_WGM3': '$3', # Waveform Generation Mode
+ 'TCCR3B' : '$91', # Timer/Counter3 Control Registe
+ 'TCCR3B_ICNC3': '$80', # Input Capture 3 Noise Canceler
+ 'TCCR3B_ICES3': '$40', # Input Capture 3 Edge Select
+ 'TCCR3B_WGM3': '$18', # Waveform Generation Mode
+ 'TCCR3B_CS3': '$7', # Prescaler source of Timer/Coun
+ 'TCCR3C' : '$92', # Timer/Counter 3 Control Regist
+ 'TCCR3C_FOC3A': '$80', # Force Output Compare 3A
+ 'TCCR3C_FOC3B': '$40', # Force Output Compare 3B
+ 'TCCR3C_FOC3C': '$20', # Force Output Compare 3C
+ 'TCNT3' : '$94', # Timer/Counter3 Bytes
+ 'OCR3A' : '$98', # Timer/Counter3 Output Compare
+ 'OCR3B' : '$9a', # Timer/Counter3 Output Compare
+ 'OCR3C' : '$9c', # Timer/Counter3 Output Compare
+ 'ICR3' : '$96', # Timer/Counter3 Input Capture R
+ 'TIMSK3' : '$71', # Timer/Counter Interrupt Mask R
+ 'TIMSK3_ICIE3': '$20', # Timer/Counter3 Input Capture I
+ 'TIMSK3_OCIE3C': '$8', # Timer/Counter3 Output CompareC
+ 'TIMSK3_OCIE3B': '$4', # Timer/Counter3 Output CompareB
+ 'TIMSK3_OCIE3A': '$2', # Timer/Counter3 Output CompareA
+ 'TIMSK3_TOIE3': '$1', # Timer/Counter3 Overflow Interr
+ 'TIFR3' : '$38', # Timer/Counter Interrupt Flag r
+ 'TIFR3_ICF3': '$20', # Input Capture Flag 3
+ 'TIFR3_OCF3C': '$8', # Output Compare Flag 3C
+ 'TIFR3_OCF3B': '$4', # Output Compare Flag 3B
+ 'TIFR3_OCF3A': '$2', # Output Compare Flag 3A
+ 'TIFR3_TOV3': '$1', # Timer/Counter3 Overflow Flag
+
+# Module TIMER_COUNTER_2
+ 'TCCR2' : '$b0', # Timer/Counter2 Control Registe
+ 'TCCR2_FOC2A': '$80', # Force Output Compare
+ 'TCCR2_WGM20': '$40', # Waveform Genration Mode
+ 'TCCR2_COM2A': '$30', # Compare Output Mode bits
+ 'TCCR2_WGM21': '$8', # Waveform Generation Mode
+ 'TCCR2_CS2': '$7', # Clock Select bits
+ 'TCNT2' : '$b2', # Timer/Counter2
+ 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
+ 'TIMSK2' : '$70', # Timer/Counter Interrupt Mask r
+ 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
+ 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
+ 'TIFR2' : '$37', # Timer/Counter Interrupt Flag R
+ 'TIFR2_OCF2A': '$2', # Output Compare Flag 2
+ 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_PSR2': '$2', # Prescaler Reset Timer/Counter2
+ 'ASSR' : '$b6', # Asynchronous Status Register
+ 'ASSR_EXCLK': '$10', # Enable External Clock Interrup
+ 'ASSR_AS2': '$8', # AS2: Asynchronous Timer/Counte
+ 'ASSR_TCN2UB': '$4', # TCN2UB: Timer/Counter2 Update
+ 'ASSR_OCR2UB': '$2', # Output Compare Register2 Updat
+ 'ASSR_TCR2UB': '$1', # TCR2UB: Timer/Counter Control
+
+# Module WATCHDOG
+ 'WDTCR' : '$60', # Watchdog Timer Control Registe
+ 'WDTCR_WDCE': '$10', # Watchdog Change Enable
+ 'WDTCR_WDE': '$8', # Watch Dog Enable
+ 'WDTCR_WDP': '$7', # Watch Dog Timer Prescaler bits
+
+# Module AD_CONVERTER
+ 'ADMUX' : '$7c', # The ADC multiplexer Selection
+ 'ADMUX_REFS': '$c0', # Reference Selection Bits
+ 'ADMUX_ADLAR': '$20', # Left Adjust Result
+ 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
+ 'ADCSRA' : '$7a', # The ADC Control and Status reg
+ 'ADCSRA_ADEN': '$80', # ADC Enable
+ 'ADCSRA_ADSC': '$40', # ADC Start Conversion
+ 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
+ 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
+ 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
+ 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
+ 'ADC' : '$78', # ADC Data Register Bytes
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ADHSM': '$80', # ADC High Speed Mode
+ 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Sources
+ 'DIDR0' : '$7e', # Digital Input Disable Register
+ 'DIDR0_ADC7D': '$80', # ADC7 Digital input Disable
+ 'DIDR0_ADC6D': '$40', # ADC6 Digital input Disable
+ 'DIDR0_ADC5D': '$20', # ADC5 Digital input Disable
+ 'DIDR0_ADC4D': '$10', # ADC4 Digital input Disable
+ 'DIDR0_ADC3D': '$8', # ADC3 Digital input Disable
+ 'DIDR0_ADC2D': '$4', # ADC2 Digital input Disable
+ 'DIDR0_ADC1D': '$2', # ADC1 Digital input Disable
+ 'DIDR0_ADC0D': '$1', # ADC0 Digital input Disable
+
+# Module ANALOG_COMPARATOR
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
+ 'ACSR' : '$50', # Analog Comparator Control And
+ 'ACSR_ACD': '$80', # Analog Comparator Disable
+ 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
+ 'ACSR_ACO': '$20', # Analog Compare Output
+ 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
+ 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
+ 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
+ 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
+ 'DIDR1' : '$7f', #
+ 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
+ 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
+
+# Module CAN
+ 'CANGCON' : '$d8', # CAN General Control Register
+ 'CANGCON_ABRQ': '$80', # Abort Request
+ 'CANGCON_OVRQ': '$40', # Overload Frame Request
+ 'CANGCON_TTC': '$20', # Time Trigger Communication
+ 'CANGCON_SYNTTC': '$10', # Synchronization of TTC
+ 'CANGCON_LISTEN': '$8', # Listening Mode
+ 'CANGCON_TEST': '$4', # Test Mode
+ 'CANGCON_ENASTB': '$2', # Enable / Standby
+ 'CANGCON_SWRES': '$1', # Software Reset Request
+ 'CANGSTA' : '$d9', # CAN General Status Register
+ 'CANGSTA_OVRG': '$40', # Overload Frame Flag
+ 'CANGSTA_TXBSY': '$10', # Transmitter Busy
+ 'CANGSTA_RXBSY': '$8', # Receiver Busy
+ 'CANGSTA_ENFG': '$4', # Enable Flag
+ 'CANGSTA_BOFF': '$2', # Bus Off Mode
+ 'CANGSTA_ERRP': '$1', # Error Passive Mode
+ 'CANGIT' : '$da', # CAN General Interrupt Register
+ 'CANGIT_CANIT': '$80', # General Interrupt Flag
+ 'CANGIT_BOFFIT': '$40', # Bus Off Interrupt Flag
+ 'CANGIT_OVRTIM': '$20', # Overrun CAN Timer
+ 'CANGIT_BXOK': '$10', # Burst Receive Interrupt
+ 'CANGIT_SERG': '$8', # Stuff Error General
+ 'CANGIT_CERG': '$4', # CRC Error General
+ 'CANGIT_FERG': '$2', # Form Error General
+ 'CANGIT_AERG': '$1', # Ackknowledgement Error General
+ 'CANGIE' : '$db', # CAN General Interrupt Enable R
+ 'CANGIE_ENIT': '$80', # Enable all Interrupts
+ 'CANGIE_ENBOFF': '$40', # Enable Bus Off INterrupt
+ 'CANGIE_ENRX': '$20', # Enable Receive Interrupt
+ 'CANGIE_ENTX': '$10', # Enable Transmitt Interrupt
+ 'CANGIE_ENERR': '$8', # Enable MOb Error Interrupt
+ 'CANGIE_ENBX': '$4', # Enable Burst Receive Interrupt
+ 'CANGIE_ENERG': '$2', # Enable General Error Interrupt
+ 'CANGIE_ENOVRT': '$1', # Enable CAN Timer Overrun Inter
+ 'CANEN2' : '$dc', # Enable MOb Register
+ 'CANEN1' : '$dd', # Enable MOb Register
+ 'CANIE2' : '$de', # Enable Interrupt MOb Register
+ 'CANIE1' : '$df', # Enable Interrupt MOb Register
+ 'CANSIT2' : '$e0', # CAN Status Interrupt MOb Regis
+ 'CANSIT1' : '$e1', # CAN Status Interrupt MOb Regis
+ 'CANBT1' : '$e2', # Bit Timing Register 1
+ 'CANBT1_BRP': '$7e', # Baud Rate Prescaler bits
+ 'CANBT2' : '$e3', # Bit Timing Register 2
+ 'CANBT2_SJW': '$60', # Re-Sync Jump Width
+ 'CANBT2_PRS': '$e', # Propagation Time Segment
+ 'CANBT3' : '$e4', # Bit Timing Register 3
+ 'CANBT3_PHS2': '$70', # Phase Segments
+ 'CANBT3_PHS1': '$e', # Phase Segment 1
+ 'CANBT3_SMP': '$1', # Sample Type
+ 'CANTCON' : '$e5', # Timer Control Register
+ 'CANTIML' : '$e6', # Timer Register Low
+ 'CANTIMH' : '$e7', # Timer Register High
+ 'CANTTCL' : '$e8', # TTC Timer Register Low
+ 'CANTTCH' : '$e9', # TTC Timer Register High
+ 'CANTEC' : '$ea', # Transmit Error Counter Registe
+ 'CANREC' : '$eb', # Receive Error Counter Register
+ 'CANHPMOB' : '$ec', # Highest Priority MOb Register
+ 'CANPAGE' : '$ed', # Page MOb Register
+ 'CANPAGE_MOBNB': '$f0', # MOb Number Bits
+ 'CANPAGE_AINC': '$8', # MOb Data Buffer Auto Increment
+ 'CANPAGE_INDX': '$7', # Data Buffer Index Bits
+ 'CANSTMOB' : '$ee', # MOb Status Register
+ 'CANSTMOB_DLCW': '$80', # Data Length Code Warning
+ 'CANSTMOB_TXOK': '$40', # Transmit OK
+ 'CANSTMOB_RXOK': '$20', # Receive OK
+ 'CANSTMOB_BERR': '$10', # Bit Error
+ 'CANSTMOB_SERR': '$8', # Stuff Error
+ 'CANSTMOB_CERR': '$4', # CRC Error
+ 'CANSTMOB_FERR': '$2', # Form Error
+ 'CANSTMOB_AERR': '$1', # Ackknowledgement Error
+ 'CANCDMOB' : '$ef', # MOb Control and DLC Register
+ 'CANCDMOB_CONMOB': '$c0', # MOb Config Bits
+ 'CANCDMOB_RPLV': '$20', # Reply Valid
+ 'CANCDMOB_IDE': '$10', # Identifier Extension
+ 'CANCDMOB_DLC': '$f', # Data Length Code Bits
+ 'CANIDT4' : '$f0', # Identifier Tag Register 4
+ 'CANIDT3' : '$f1', # Identifier Tag Register 3
+ 'CANIDT2' : '$f2', # Identifier Tag Register 2
+ 'CANIDT1' : '$f3', # Identifier Tag Register 1
+ 'CANIDM4' : '$f4', # Identifier Mask Register 4
+ 'CANIDM3' : '$f5', # Identifier Mask Register 3
+ 'CANIDM2' : '$f6', # Identifier Mask Register 2
+ 'CANIDM1' : '$f7', # Identifier Mask Register 1
+ 'CANSTML' : '$f8', # Time Stamp Register Low
+ 'CANSTMH' : '$f9', # Time Stamp Register High
+ 'CANMSG' : '$fa', # Message Data Register
+
+ '__amforth_dummy':'0'
+}
diff --git a/amforth-6.5/avr8/devices/at90can128/words/no-jtag.asm b/amforth-6.5/avr8/devices/at90can128/words/no-jtag.asm
new file mode 100644
index 0000000..352a4bb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90can128/words/no-jtag.asm
@@ -0,0 +1,14 @@
+; ( -- )
+; ( -- )
+; MCU
+; disable jtag at runtime
+VE_NOJTAG:
+ .dw $FF05
+ .db "-jtag",0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOJTAG
+XT_NOJTAG:
+ .dw PFA_NOJTAG
+PFA_NOJTAG:
+
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/at90can128/words/no-wdt.asm b/amforth-6.5/avr8/devices/at90can128/words/no-wdt.asm
new file mode 100644
index 0000000..4a12261
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90can128/words/no-wdt.asm
@@ -0,0 +1,22 @@
+; ( -- )
+; MCU
+; disable watch dog timer at runtime
+VE_NOWDT:
+ .dw $ff04
+ .db "-wdt"
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOWDT
+XT_NOWDT:
+ .dw PFA_NOWDT
+PFA_NOWDT:
+
+; Reset WDT
+ wdr
+; Write logical one to WDTOE and WDE
+ in_ temp1, WDTCR
+ ori temp1, (1<<WDTOE)|(1<<WDE)
+ out WDTCR, temp1
+; Turn off WDT
+ ldi temp1, (0<<WDE)
+ out_ WDTCR, temp1
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/at90can128/words/sleep.asm b/amforth-6.5/avr8/devices/at90can128/words/sleep.asm
new file mode 100644
index 0000000..256249c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90can128/words/sleep.asm
@@ -0,0 +1,19 @@
+; ( mode -- )
+; MCU
+; put the controller into the specified sleep mode
+VE_SLEEP:
+ .dw $ff05
+ .db "sleep", 0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_SLEEP
+XT_SLEEP:
+ .dw PFA_SLEEP
+PFA_SLEEP:
+ andi tosl, 7 ; leave only legal mode bits
+ lsl tosl ; move to correct location (bits 3-1)
+ ori tosl, 1 ; set the SE bit
+ out_ SMCR, tosl ; set the sleep config
+ sleep ; nighty-night
+ out_ SMCR, zerol ; 0 protects against accidental sleeps
+ loadtos ; pop argument from stack
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/at90can32/at90can32.frt b/amforth-6.5/avr8/devices/at90can32/at90can32.frt
new file mode 100644
index 0000000..56a906a
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90can32/at90can32.frt
@@ -0,0 +1,465 @@
+\ Partname: AT90CAN32
+\ generated automatically
+
+\ PORTA
+&34 constant PORTA \ Port A Data Register
+&33 constant DDRA \ Port A Data Direction Register
+&32 constant PINA \ Port A Input Pins
+\ PORTB
+&37 constant PORTB \ Port B Data Register
+&36 constant DDRB \ Port B Data Direction Register
+&35 constant PINB \ Port B Input Pins
+\ PORTC
+&40 constant PORTC \ Port C Data Register
+&39 constant DDRC \ Port C Data Direction Register
+&38 constant PINC \ Port C Input Pins
+\ PORTD
+&43 constant PORTD \ Port D Data Register
+&42 constant DDRD \ Port D Data Direction Register
+&41 constant PIND \ Port D Input Pins
+\ PORTE
+&46 constant PORTE \ Data Register, Port E
+&45 constant DDRE \ Data Direction Register, Port E
+&44 constant PINE \ Input Pins, Port E
+\ PORTF
+&49 constant PORTF \ Data Register, Port F
+&48 constant DDRF \ Data Direction Register, Port F
+&47 constant PINF \ Input Pins, Port F
+\ PORTG
+&52 constant PORTG \ Data Register, Port G
+&51 constant DDRG \ Data Direction Register, Port G
+&50 constant PING \ Input Pins, Port G
+\ JTAG
+&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
+&85 constant MCUCR \ MCU Control Register
+ $80 constant MCUCR_JTD \ JTAG Interface Disable
+&84 constant MCUSR \ MCU Status Register
+ $10 constant MCUSR_JTRF \ JTAG Reset Flag
+\ SPI
+&76 constant SPCR \ SPI Control Register
+ $80 constant SPCR_SPIE \ SPI Interrupt Enable
+ $40 constant SPCR_SPE \ SPI Enable
+ $20 constant SPCR_DORD \ Data Order
+ $10 constant SPCR_MSTR \ Master/Slave Select
+ $08 constant SPCR_CPOL \ Clock polarity
+ $04 constant SPCR_CPHA \ Clock Phase
+ $03 constant SPCR_SPR \ SPI Clock Rate Selects
+&77 constant SPSR \ SPI Status Register
+ $80 constant SPSR_SPIF \ SPI Interrupt Flag
+ $40 constant SPSR_WCOL \ Write Collision Flag
+ $01 constant SPSR_SPI2X \ Double SPI Speed Bit
+&78 constant SPDR \ SPI Data Register
+\ TWI
+&184 constant TWBR \ TWI Bit Rate register
+&188 constant TWCR \ TWI Control Register
+ $80 constant TWCR_TWINT \ TWI Interrupt Flag
+ $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
+ $20 constant TWCR_TWSTA \ TWI Start Condition Bit
+ $10 constant TWCR_TWSTO \ TWI Stop Condition Bit
+ $08 constant TWCR_TWWC \ TWI Write Collition Flag
+ $04 constant TWCR_TWEN \ TWI Enable Bit
+ $01 constant TWCR_TWIE \ TWI Interrupt Enable
+&185 constant TWSR \ TWI Status Register
+ $F8 constant TWSR_TWS \ TWI Status
+ $03 constant TWSR_TWPS \ TWI Prescaler
+&187 constant TWDR \ TWI Data register
+&186 constant TWAR \ TWI (Slave) Address register
+ $FE constant TWAR_TWA \ TWI (Slave) Address register Bits
+ $01 constant TWAR_TWGCE \ TWI General Call Recognition Enable Bit
+\ USART0
+&198 constant UDR0 \ USART I/O Data Register
+&192 constant UCSR0A \ USART Control and Status Register A
+ $80 constant UCSR0A_RXC0 \ USART Receive Complete
+ $40 constant UCSR0A_TXC0 \ USART Transmitt Complete
+ $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
+ $10 constant UCSR0A_FE0 \ Framing Error
+ $08 constant UCSR0A_DOR0 \ Data overRun
+ $04 constant UCSR0A_UPE0 \ Parity Error
+ $02 constant UCSR0A_U2X0 \ Double the USART transmission speed
+ $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
+&193 constant UCSR0B \ USART Control and Status Register B
+ $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
+ $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
+ $20 constant UCSR0B_UDRIE0 \ USART Data register Empty Interrupt Enable
+ $10 constant UCSR0B_RXEN0 \ Receiver Enable
+ $08 constant UCSR0B_TXEN0 \ Transmitter Enable
+ $04 constant UCSR0B_UCSZ02 \ Character Size
+ $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
+ $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
+&194 constant UCSR0C \ USART Control and Status Register C
+ $40 constant UCSR0C_UMSEL0 \ USART Mode Select
+ $30 constant UCSR0C_UPM0 \ Parity Mode Bits
+ $08 constant UCSR0C_USBS0 \ Stop Bit Select
+ $06 constant UCSR0C_UCSZ0 \ Character Size
+ $01 constant UCSR0C_UCPOL0 \ Clock Polarity
+&196 constant UBRR0 \ USART Baud Rate Register t Bytes
+\ USART1
+&206 constant UDR1 \ USART I/O Data Register
+&200 constant UCSR1A \ USART Control and Status Register A
+ $80 constant UCSR1A_RXC1 \ USART Receive Complete
+ $40 constant UCSR1A_TXC1 \ USART Transmitt Complete
+ $20 constant UCSR1A_UDRE1 \ USART Data Register Empty
+ $10 constant UCSR1A_FE1 \ Framing Error
+ $08 constant UCSR1A_DOR1 \ Data overRun
+ $04 constant UCSR1A_UPE1 \ Parity Error
+ $02 constant UCSR1A_U2X1 \ Double the USART transmission speed
+ $01 constant UCSR1A_MPCM1 \ Multi-processor Communication Mode
+&201 constant UCSR1B \ USART Control and Status Register B
+ $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable
+ $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable
+ $20 constant UCSR1B_UDRIE1 \ USART Data register Empty Interrupt Enable
+ $10 constant UCSR1B_RXEN1 \ Receiver Enable
+ $08 constant UCSR1B_TXEN1 \ Transmitter Enable
+ $04 constant UCSR1B_UCSZ12 \ Character Size
+ $02 constant UCSR1B_RXB81 \ Receive Data Bit 8
+ $01 constant UCSR1B_TXB81 \ Transmit Data Bit 8
+&202 constant UCSR1C \ USART Control and Status Register C
+ $40 constant UCSR1C_UMSEL1 \ USART Mode Select
+ $30 constant UCSR1C_UPM1 \ Parity Mode Bits
+ $08 constant UCSR1C_USBS1 \ Stop Bit Select
+ $06 constant UCSR1C_UCSZ1 \ Character Size
+ $01 constant UCSR1C_UCPOL1 \ Clock Polarity
+&204 constant UBRR1 \ USART Baud Rate Register t Bytes
+\ CPU
+&95 constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ $08 constant SREG_V \ Two's Complement Overflow Flag
+ $04 constant SREG_N \ Negative Flag
+ $02 constant SREG_Z \ Zero Flag
+ $01 constant SREG_C \ Carry Flag
+&93 constant SP \ Stack Pointer
+&116 constant XMCRA \ External Memory Control Register A
+ $80 constant XMCRA_SRE \ External SRAM Enable
+ $70 constant XMCRA_SRL \ Wait state page limit
+ $0C constant XMCRA_SRW1 \ Wait state select bit upper page
+ $03 constant XMCRA_SRW0 \ Wait state select bit lower page
+&117 constant XMCRB \ External Memory Control Register B
+ $80 constant XMCRB_XMBK \ External Memory Bus Keeper Enable
+ $07 constant XMCRB_XMM \ External Memory High Mask
+&102 constant OSCCAL \ Oscillator Calibration Value
+&97 constant CLKPR \ Clock Prescale Register
+ $80 constant CLKPR_CLKPCE \
+ $0F constant CLKPR_CLKPS \
+&83 constant SMCR \ Sleep Mode Control Register
+ $0E constant SMCR_SM \ Sleep Mode Select bits
+ $01 constant SMCR_SE \ Sleep Enable
+&91 constant RAMPZ \ RAM Page Z Select Register - Not used.
+ $01 constant RAMPZ_RAMPZ0 \ RAM Page Z Select Register Bit 0
+&75 constant GPIOR2 \ General Purpose IO Register 2
+ $FF constant GPIOR2_GPIOR \ General Purpose IO Register 2 bis
+&74 constant GPIOR1 \ General Purpose IO Register 1
+ $FF constant GPIOR1_GPIOR \ General Purpose IO Register 1 bis
+&62 constant GPIOR0 \ General Purpose IO Register 0
+ $80 constant GPIOR0_GPIOR07 \ General Purpose IO Register 0 bit 7
+ $40 constant GPIOR0_GPIOR06 \ General Purpose IO Register 0 bit 6
+ $20 constant GPIOR0_GPIOR05 \ General Purpose IO Register 0 bit 5
+ $10 constant GPIOR0_GPIOR04 \ General Purpose IO Register 0 bit 4
+ $08 constant GPIOR0_GPIOR03 \ General Purpose IO Register 0 bit 3
+ $04 constant GPIOR0_GPIOR02 \ General Purpose IO Register 0 bit 2
+ $02 constant GPIOR0_GPIOR01 \ General Purpose IO Register 0 bit 1
+ $01 constant GPIOR0_GPIOR00 \ General Purpose IO Register 0 bit 0
+\ BOOT_LOAD
+&87 constant SPMCSR \ Store Program Memory Control Register
+ $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
+ $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
+ $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
+ $04 constant SPMCSR_PGWRT \ Page Write
+ $02 constant SPMCSR_PGERS \ Page Erase
+ $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
+\ EXTERNAL_INTERRUPT
+&105 constant EICRA \ External Interrupt Control Register A
+ $C0 constant EICRA_ISC3 \ External Interrupt Sense Control Bit
+ $30 constant EICRA_ISC2 \ External Interrupt Sense Control Bit
+ $0C constant EICRA_ISC1 \ External Interrupt Sense Control Bit
+ $03 constant EICRA_ISC0 \ External Interrupt Sense Control Bit
+&106 constant EICRB \ External Interrupt Control Register B
+ $C0 constant EICRB_ISC7 \ External Interrupt 7-4 Sense Control Bit
+ $30 constant EICRB_ISC6 \ External Interrupt 7-4 Sense Control Bit
+ $0C constant EICRB_ISC5 \ External Interrupt 7-4 Sense Control Bit
+ $03 constant EICRB_ISC4 \ External Interrupt 7-4 Sense Control Bit
+&61 constant EIMSK \ External Interrupt Mask Register
+ $FF constant EIMSK_INT \ External Interrupt Request 7 Enable
+&60 constant EIFR \ External Interrupt Flag Register
+ $FF constant EIFR_INTF \ External Interrupt Flags
+\ EEPROM
+&65 constant EEAR \ EEPROM Read/Write Access Bytes
+&64 constant EEDR \ EEPROM Data Register
+&63 constant EECR \ EEPROM Control Register
+ $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
+ $04 constant EECR_EEMWE \ EEPROM Master Write Enable
+ $02 constant EECR_EEWE \ EEPROM Write Enable
+ $01 constant EECR_EERE \ EEPROM Read Enable
+\ TIMER_COUNTER_0
+&68 constant TCCR0A \ Timer/Counter0 Control Register
+ $80 constant TCCR0A_FOC0A \ Force Output Compare
+ $40 constant TCCR0A_WGM00 \ Waveform Generation Mode 0
+ $30 constant TCCR0A_COM0A \ Compare Match Output Modes
+ $08 constant TCCR0A_WGM01 \ Waveform Generation Mode 1
+ $07 constant TCCR0A_CS0 \ Clock Selects
+&70 constant TCNT0 \ Timer/Counter0
+&71 constant OCR0A \ Timer/Counter0 Output Compare Register
+&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
+ $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match Interrupt Enable
+ $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
+&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
+ $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0
+ $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
+&67 constant GTCCR \ General Timer/Control Register
+ $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
+ $01 constant GTCCR_PSR310 \ Prescaler Reset Timer/Counter1 and Timer/Counter0
+\ TIMER_COUNTER_2
+&176 constant TCCR2 \ Timer/Counter2 Control Register
+ $80 constant TCCR2_FOC2A \ Force Output Compare
+ $40 constant TCCR2_WGM20 \ Waveform Genration Mode
+ $30 constant TCCR2_COM2A \ Compare Output Mode bits
+ $08 constant TCCR2_WGM21 \ Waveform Generation Mode
+ $07 constant TCCR2_CS2 \ Clock Select bits
+&178 constant TCNT2 \ Timer/Counter2
+&179 constant OCR2A \ Timer/Counter2 Output Compare Register
+&112 constant TIMSK2 \ Timer/Counter Interrupt Mask register
+ $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match Interrupt Enable
+ $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
+&55 constant TIFR2 \ Timer/Counter Interrupt Flag Register
+ $02 constant TIFR2_OCF2A \ Output Compare Flag 2
+ $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
+&182 constant ASSR \ Asynchronous Status Register
+ $10 constant ASSR_EXCLK \ Enable External Clock Interrupt
+ $08 constant ASSR_AS2 \ AS2: Asynchronous Timer/Counter2
+ $04 constant ASSR_TCN2UB \ TCN2UB: Timer/Counter2 Update Busy
+ $02 constant ASSR_OCR2UB \ Output Compare Register2 Update Busy
+ $01 constant ASSR_TCR2UB \ TCR2UB: Timer/Counter Control Register2 Update Busy
+\ TIMER_COUNTER_1
+&128 constant TCCR1A \ Timer/Counter1 Control Register A
+ $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
+ $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
+ $0C constant TCCR1A_COM1C \ Compare Output Mode 1C, bits
+ $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
+&129 constant TCCR1B \ Timer/Counter1 Control Register B
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
+ $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
+&130 constant TCCR1C \ Timer/Counter 1 Control Register C
+ $80 constant TCCR1C_FOC1A \ Force Output Compare 1A
+ $40 constant TCCR1C_FOC1B \ Force Output Compare 1B
+ $20 constant TCCR1C_FOC1C \ Force Output Compare 1C
+&132 constant TCNT1 \ Timer/Counter1 Bytes
+&136 constant OCR1A \ Timer/Counter1 Output Compare Register Bytes
+&138 constant OCR1B \ Timer/Counter1 Output Compare Register Bytes
+&140 constant OCR1C \ Timer/Counter1 Output Compare Register Bytes
+&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
+&111 constant TIMSK1 \ Timer/Counter Interrupt Mask Register
+ $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
+ $08 constant TIMSK1_OCIE1C \ Timer/Counter1 Output CompareC Match Interrupt Enable
+ $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output CompareB Match Interrupt Enable
+ $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output CompareA Match Interrupt Enable
+ $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
+&54 constant TIFR1 \ Timer/Counter Interrupt Flag register
+ $20 constant TIFR1_ICF1 \ Input Capture Flag 1
+ $08 constant TIFR1_OCF1C \ Output Compare Flag 1C
+ $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
+ $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
+ $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
+\ TIMER_COUNTER_3
+&144 constant TCCR3A \ Timer/Counter3 Control Register A
+ $C0 constant TCCR3A_COM3A \ Compare Output Mode 3A, bits
+ $30 constant TCCR3A_COM3B \ Compare Output Mode 3B, bits
+ $0C constant TCCR3A_COM3C \ Compare Output Mode 3C, bits
+ $03 constant TCCR3A_WGM3 \ Waveform Generation Mode
+&145 constant TCCR3B \ Timer/Counter3 Control Register B
+ $80 constant TCCR3B_ICNC3 \ Input Capture 3 Noise Canceler
+ $40 constant TCCR3B_ICES3 \ Input Capture 3 Edge Select
+ $18 constant TCCR3B_WGM3 \ Waveform Generation Mode
+ $07 constant TCCR3B_CS3 \ Prescaler source of Timer/Counter 3
+&146 constant TCCR3C \ Timer/Counter 3 Control Register C
+ $80 constant TCCR3C_FOC3A \ Force Output Compare 3A
+ $40 constant TCCR3C_FOC3B \ Force Output Compare 3B
+ $20 constant TCCR3C_FOC3C \ Force Output Compare 3C
+&148 constant TCNT3 \ Timer/Counter3 Bytes
+&152 constant OCR3A \ Timer/Counter3 Output Compare Register Bytes
+&154 constant OCR3B \ Timer/Counter3 Output Compare Register Bytes
+&156 constant OCR3C \ Timer/Counter3 Output Compare Register Bytes
+&150 constant ICR3 \ Timer/Counter3 Input Capture Register Bytes
+&113 constant TIMSK3 \ Timer/Counter Interrupt Mask Register
+ $20 constant TIMSK3_ICIE3 \ Timer/Counter3 Input Capture Interrupt Enable
+ $08 constant TIMSK3_OCIE3C \ Timer/Counter3 Output CompareC Match Interrupt Enable
+ $04 constant TIMSK3_OCIE3B \ Timer/Counter3 Output CompareB Match Interrupt Enable
+ $02 constant TIMSK3_OCIE3A \ Timer/Counter3 Output CompareA Match Interrupt Enable
+ $01 constant TIMSK3_TOIE3 \ Timer/Counter3 Overflow Interrupt Enable
+&56 constant TIFR3 \ Timer/Counter Interrupt Flag register
+ $20 constant TIFR3_ICF3 \ Input Capture Flag 3
+ $08 constant TIFR3_OCF3C \ Output Compare Flag 3C
+ $04 constant TIFR3_OCF3B \ Output Compare Flag 3B
+ $02 constant TIFR3_OCF3A \ Output Compare Flag 3A
+ $01 constant TIFR3_TOV3 \ Timer/Counter3 Overflow Flag
+\ WATCHDOG
+&96 constant WDTCR \ Watchdog Timer Control Register
+ $10 constant WDTCR_WDCE \ Watchdog Change Enable
+ $08 constant WDTCR_WDE \ Watch Dog Enable
+ $07 constant WDTCR_WDP \ Watch Dog Timer Prescaler bits
+\ AD_CONVERTER
+&124 constant ADMUX \ The ADC multiplexer Selection Register
+ $C0 constant ADMUX_REFS \ Reference Selection Bits
+ $20 constant ADMUX_ADLAR \ Left Adjust Result
+ $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
+&122 constant ADCSRA \ The ADC Control and Status register
+ $80 constant ADCSRA_ADEN \ ADC Enable
+ $40 constant ADCSRA_ADSC \ ADC Start Conversion
+ $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
+ $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
+ $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
+ $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
+&120 constant ADC \ ADC Data Register Bytes
+&123 constant ADCSRB \ ADC Control and Status Register B
+ $80 constant ADCSRB_ADHSM \ ADC High Speed Mode
+ $07 constant ADCSRB_ADTS \ ADC Auto Trigger Sources
+&126 constant DIDR0 \ Digital Input Disable Register 1
+ $80 constant DIDR0_ADC7D \ ADC7 Digital input Disable
+ $40 constant DIDR0_ADC6D \ ADC6 Digital input Disable
+ $20 constant DIDR0_ADC5D \ ADC5 Digital input Disable
+ $10 constant DIDR0_ADC4D \ ADC4 Digital input Disable
+ $08 constant DIDR0_ADC3D \ ADC3 Digital input Disable
+ $04 constant DIDR0_ADC2D \ ADC2 Digital input Disable
+ $02 constant DIDR0_ADC1D \ ADC1 Digital input Disable
+ $01 constant DIDR0_ADC0D \ ADC0 Digital input Disable
+\ ANALOG_COMPARATOR
+&80 constant ACSR \ Analog Comparator Control And Status Register
+ $80 constant ACSR_ACD \ Analog Comparator Disable
+ $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
+ $20 constant ACSR_ACO \ Analog Compare Output
+ $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
+ $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
+ $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
+ $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
+&127 constant DIDR1 \
+ $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
+ $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
+\ CAN
+&216 constant CANGCON \ CAN General Control Register
+ $80 constant CANGCON_ABRQ \ Abort Request
+ $40 constant CANGCON_OVRQ \ Overload Frame Request
+ $20 constant CANGCON_TTC \ Time Trigger Communication
+ $10 constant CANGCON_SYNTTC \ Synchronization of TTC
+ $08 constant CANGCON_LISTEN \ Listening Mode
+ $04 constant CANGCON_TEST \ Test Mode
+ $02 constant CANGCON_ENASTB \ Enable / Standby
+ $01 constant CANGCON_SWRES \ Software Reset Request
+&217 constant CANGSTA \ CAN General Status Register
+ $40 constant CANGSTA_OVRG \ Overload Frame Flag
+ $10 constant CANGSTA_TXBSY \ Transmitter Busy
+ $08 constant CANGSTA_RXBSY \ Receiver Busy
+ $04 constant CANGSTA_ENFG \ Enable Flag
+ $02 constant CANGSTA_BOFF \ Bus Off Mode
+ $01 constant CANGSTA_ERRP \ Error Passive Mode
+&218 constant CANGIT \ CAN General Interrupt Register
+ $80 constant CANGIT_CANIT \ General Interrupt Flag
+ $40 constant CANGIT_BOFFIT \ Bus Off Interrupt Flag
+ $20 constant CANGIT_OVRTIM \ Overrun CAN Timer
+ $10 constant CANGIT_BXOK \ Burst Receive Interrupt
+ $08 constant CANGIT_SERG \ Stuff Error General
+ $04 constant CANGIT_CERG \ CRC Error General
+ $02 constant CANGIT_FERG \ Form Error General
+ $01 constant CANGIT_AERG \ Ackknowledgement Error General
+&219 constant CANGIE \ CAN General Interrupt Enable Register
+ $80 constant CANGIE_ENIT \ Enable all Interrupts
+ $40 constant CANGIE_ENBOFF \ Enable Bus Off INterrupt
+ $20 constant CANGIE_ENRX \ Enable Receive Interrupt
+ $10 constant CANGIE_ENTX \ Enable Transmitt Interrupt
+ $08 constant CANGIE_ENERR \ Enable MOb Error Interrupt
+ $04 constant CANGIE_ENBX \ Enable Burst Receive Interrupt
+ $02 constant CANGIE_ENERG \ Enable General Error Interrupt
+ $01 constant CANGIE_ENOVRT \ Enable CAN Timer Overrun Interrupt
+&220 constant CANEN2 \ Enable MOb Register
+&221 constant CANEN1 \ Enable MOb Register
+&222 constant CANIE2 \ Enable Interrupt MOb Register
+&223 constant CANIE1 \ Enable Interrupt MOb Register
+&224 constant CANSIT2 \ CAN Status Interrupt MOb Register
+&225 constant CANSIT1 \ CAN Status Interrupt MOb Register
+&226 constant CANBT1 \ Bit Timing Register 1
+ $7E constant CANBT1_BRP \ Baud Rate Prescaler bits
+&227 constant CANBT2 \ Bit Timing Register 2
+ $60 constant CANBT2_SJW \ Re-Sync Jump Width
+ $0E constant CANBT2_PRS \ Propagation Time Segment
+&228 constant CANBT3 \ Bit Timing Register 3
+ $70 constant CANBT3_PHS2 \ Phase Segments
+ $0E constant CANBT3_PHS1 \ Phase Segment 1
+ $01 constant CANBT3_SMP \ Sample Type
+&229 constant CANTCON \ Timer Control Register
+&230 constant CANTIML \ Timer Register Low
+&231 constant CANTIMH \ Timer Register High
+&232 constant CANTTCL \ TTC Timer Register Low
+&233 constant CANTTCH \ TTC Timer Register High
+&234 constant CANTEC \ Transmit Error Counter Register
+&235 constant CANREC \ Receive Error Counter Register
+&236 constant CANHPMOB \ Highest Priority MOb Register
+&237 constant CANPAGE \ Page MOb Register
+ $F0 constant CANPAGE_MOBNB \ MOb Number Bits
+ $08 constant CANPAGE_AINC \ MOb Data Buffer Auto Increment
+ $07 constant CANPAGE_INDX \ Data Buffer Index Bits
+&238 constant CANSTMOB \ MOb Status Register
+ $80 constant CANSTMOB_DLCW \ Data Length Code Warning
+ $40 constant CANSTMOB_TXOK \ Transmit OK
+ $20 constant CANSTMOB_RXOK \ Receive OK
+ $10 constant CANSTMOB_BERR \ Bit Error
+ $08 constant CANSTMOB_SERR \ Stuff Error
+ $04 constant CANSTMOB_CERR \ CRC Error
+ $02 constant CANSTMOB_FERR \ Form Error
+ $01 constant CANSTMOB_AERR \ Ackknowledgement Error
+&239 constant CANCDMOB \ MOb Control and DLC Register
+ $C0 constant CANCDMOB_CONMOB \ MOb Config Bits
+ $20 constant CANCDMOB_RPLV \ Reply Valid
+ $10 constant CANCDMOB_IDE \ Identifier Extension
+ $0F constant CANCDMOB_DLC \ Data Length Code Bits
+&240 constant CANIDT4 \ Identifier Tag Register 4
+&241 constant CANIDT3 \ Identifier Tag Register 3
+&242 constant CANIDT2 \ Identifier Tag Register 2
+&243 constant CANIDT1 \ Identifier Tag Register 1
+&244 constant CANIDM4 \ Identifier Mask Register 4
+&245 constant CANIDM3 \ Identifier Mask Register 3
+&246 constant CANIDM2 \ Identifier Mask Register 2
+&247 constant CANIDM1 \ Identifier Mask Register 1
+&248 constant CANSTML \ Time Stamp Register Low
+&249 constant CANSTMH \ Time Stamp Register High
+&250 constant CANMSG \ Message Data Register
+
+\ Interrupts
+&2 constant INT0Addr \ External Interrupt Request 0
+&4 constant INT1Addr \ External Interrupt Request 1
+&6 constant INT2Addr \ External Interrupt Request 2
+&8 constant INT3Addr \ External Interrupt Request 3
+&10 constant INT4Addr \ External Interrupt Request 4
+&12 constant INT5Addr \ External Interrupt Request 5
+&14 constant INT6Addr \ External Interrupt Request 6
+&16 constant INT7Addr \ External Interrupt Request 7
+&18 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
+&20 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
+&22 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+&24 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
+&26 constant TIMER1_COMPBAddr \ Timer/Counter Compare Match B
+&28 constant TIMER1_COMPCAddr \ Timer/Counter1 Compare Match C
+&30 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+&32 constant TIMER0_COMPAddr \ Timer/Counter0 Compare Match
+&34 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
+&36 constant CANITAddr \ CAN Transfer Complete or Error
+&38 constant OVRITAddr \ CAN Timer Overrun
+&40 constant SPI__STCAddr \ SPI Serial Transfer Complete
+&42 constant USART0__RXAddr \ USART0, Rx Complete
+&44 constant USART0__UDREAddr \ USART0 Data Register Empty
+&46 constant USART0__TXAddr \ USART0, Tx Complete
+&48 constant ANALOG_COMPAddr \ Analog Comparator
+&50 constant ADCAddr \ ADC Conversion Complete
+&52 constant EE_READYAddr \ EEPROM Ready
+&54 constant TIMER3_CAPTAddr \ Timer/Counter3 Capture Event
+&56 constant TIMER3_COMPAAddr \ Timer/Counter3 Compare Match A
+&58 constant TIMER3_COMPBAddr \ Timer/Counter3 Compare Match B
+&60 constant TIMER3_COMPCAddr \ Timer/Counter3 Compare Match C
+&62 constant TIMER3_OVFAddr \ Timer/Counter3 Overflow
+&64 constant USART1__RXAddr \ USART1, Rx Complete
+&66 constant USART1__UDREAddr \ USART1, Data Register Empty
+&68 constant USART1__TXAddr \ USART1, Tx Complete
+&70 constant TWIAddr \ 2-wire Serial Interface
+&72 constant SPM_READYAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/at90can32/device.asm b/amforth-6.5/avr8/devices/at90can32/device.asm
new file mode 100644
index 0000000..3ca443f
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90can32/device.asm
@@ -0,0 +1,139 @@
+; Partname: AT90CAN32
+; generated automatically, do not edit
+
+.nolist
+ .include "can32def.inc"
+.list
+
+.equ ramstart = 256
+.equ CELLSIZE = 2
+.macro readflashcell
+ lsl zl
+ rol zh
+ lpm @0, Z+
+ lpm @1, Z+
+.endmacro
+.macro writeflashcell
+ lsl zl
+ rol zh
+.endmacro
+.set WANT_PORTA = 0
+.set WANT_PORTB = 0
+.set WANT_PORTC = 0
+.set WANT_PORTD = 0
+.set WANT_PORTE = 0
+.set WANT_PORTF = 0
+.set WANT_PORTG = 0
+.set WANT_JTAG = 0
+.set WANT_SPI = 0
+.set WANT_TWI = 0
+.set WANT_USART0 = 0
+.set WANT_USART1 = 0
+.set WANT_CPU = 0
+.set WANT_BOOT_LOAD = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_EEPROM = 0
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_TIMER_COUNTER_2 = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_TIMER_COUNTER_3 = 0
+.set WANT_WATCHDOG = 0
+.set WANT_AD_CONVERTER = 0
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_CAN = 0
+.equ intvecsize = 2 ; please verify; flash size: 32768 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.org 2
+ rcall isr ; External Interrupt Request 0
+.org 4
+ rcall isr ; External Interrupt Request 1
+.org 6
+ rcall isr ; External Interrupt Request 2
+.org 8
+ rcall isr ; External Interrupt Request 3
+.org 10
+ rcall isr ; External Interrupt Request 4
+.org 12
+ rcall isr ; External Interrupt Request 5
+.org 14
+ rcall isr ; External Interrupt Request 6
+.org 16
+ rcall isr ; External Interrupt Request 7
+.org 18
+ rcall isr ; Timer/Counter2 Compare Match
+.org 20
+ rcall isr ; Timer/Counter2 Overflow
+.org 22
+ rcall isr ; Timer/Counter1 Capture Event
+.org 24
+ rcall isr ; Timer/Counter1 Compare Match A
+.org 26
+ rcall isr ; Timer/Counter Compare Match B
+.org 28
+ rcall isr ; Timer/Counter1 Compare Match C
+.org 30
+ rcall isr ; Timer/Counter1 Overflow
+.org 32
+ rcall isr ; Timer/Counter0 Compare Match
+.org 34
+ rcall isr ; Timer/Counter0 Overflow
+.org 36
+ rcall isr ; CAN Transfer Complete or Error
+.org 38
+ rcall isr ; CAN Timer Overrun
+.org 40
+ rcall isr ; SPI Serial Transfer Complete
+.org 42
+ rcall isr ; USART0, Rx Complete
+.org 44
+ rcall isr ; USART0 Data Register Empty
+.org 46
+ rcall isr ; USART0, Tx Complete
+.org 48
+ rcall isr ; Analog Comparator
+.org 50
+ rcall isr ; ADC Conversion Complete
+.org 52
+ rcall isr ; EEPROM Ready
+.org 54
+ rcall isr ; Timer/Counter3 Capture Event
+.org 56
+ rcall isr ; Timer/Counter3 Compare Match A
+.org 58
+ rcall isr ; Timer/Counter3 Compare Match B
+.org 60
+ rcall isr ; Timer/Counter3 Compare Match C
+.org 62
+ rcall isr ; Timer/Counter3 Overflow
+.org 64
+ rcall isr ; USART1, Rx Complete
+.org 66
+ rcall isr ; USART1, Data Register Empty
+.org 68
+ rcall isr ; USART1, Tx Complete
+.org 70
+ rcall isr ; 2-wire Serial Interface
+.org 72
+ rcall isr ; Store Program Memory Read
+.equ INTVECTORS = 37
+.nooverlap
+
+; compatability layer (maybe empty)
+.equ EEPE = EEWE
+.equ EEMPE = EEMWE
+
+; controller data area, environment query mcu-info
+mcu_info:
+mcu_ramsize:
+ .dw 2048
+mcu_eepromsize:
+ .dw 1024
+mcu_maxdp:
+ .dw 24576
+mcu_numints:
+ .dw 37
+mcu_name:
+ .dw 9
+ .db "AT90CAN32",0
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/at90can32/device.inc b/amforth-6.5/avr8/devices/at90can32/device.inc
new file mode 100644
index 0000000..4b27471
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90can32/device.inc
@@ -0,0 +1,1707 @@
+; Partname: AT90CAN32
+; generated automatically, no not edit
+
+.if WANT_PORTA == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Register
+VE_PORTA:
+ .dw $ff05
+ .db "PORTA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTA
+XT_PORTA:
+ .dw PFA_DOVARIABLE
+PFA_PORTA:
+ .dw 34
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Direction Register
+VE_DDRA:
+ .dw $ff04
+ .db "DDRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRA
+XT_DDRA:
+ .dw PFA_DOVARIABLE
+PFA_DDRA:
+ .dw 33
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Input Pins
+VE_PINA:
+ .dw $ff04
+ .db "PINA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINA
+XT_PINA:
+ .dw PFA_DOVARIABLE
+PFA_PINA:
+ .dw 32
+
+.endif
+.if WANT_PORTB == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw 37
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw 36
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw 35
+
+.endif
+.if WANT_PORTC == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Register
+VE_PORTC:
+ .dw $ff05
+ .db "PORTC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTC
+XT_PORTC:
+ .dw PFA_DOVARIABLE
+PFA_PORTC:
+ .dw 40
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Direction Register
+VE_DDRC:
+ .dw $ff04
+ .db "DDRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRC
+XT_DDRC:
+ .dw PFA_DOVARIABLE
+PFA_DDRC:
+ .dw 39
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Input Pins
+VE_PINC:
+ .dw $ff04
+ .db "PINC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINC
+XT_PINC:
+ .dw PFA_DOVARIABLE
+PFA_PINC:
+ .dw 38
+
+.endif
+.if WANT_PORTD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw 43
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw 42
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw 41
+
+.endif
+.if WANT_PORTE == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port E
+VE_PORTE:
+ .dw $ff05
+ .db "PORTE",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTE
+XT_PORTE:
+ .dw PFA_DOVARIABLE
+PFA_PORTE:
+ .dw 46
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port E
+VE_DDRE:
+ .dw $ff04
+ .db "DDRE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRE
+XT_DDRE:
+ .dw PFA_DOVARIABLE
+PFA_DDRE:
+ .dw 45
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port E
+VE_PINE:
+ .dw $ff04
+ .db "PINE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINE
+XT_PINE:
+ .dw PFA_DOVARIABLE
+PFA_PINE:
+ .dw 44
+
+.endif
+.if WANT_PORTF == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port F
+VE_PORTF:
+ .dw $ff05
+ .db "PORTF",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTF
+XT_PORTF:
+ .dw PFA_DOVARIABLE
+PFA_PORTF:
+ .dw 49
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port F
+VE_DDRF:
+ .dw $ff04
+ .db "DDRF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRF
+XT_DDRF:
+ .dw PFA_DOVARIABLE
+PFA_DDRF:
+ .dw 48
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port F
+VE_PINF:
+ .dw $ff04
+ .db "PINF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINF
+XT_PINF:
+ .dw PFA_DOVARIABLE
+PFA_PINF:
+ .dw 47
+
+.endif
+.if WANT_PORTG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port G
+VE_PORTG:
+ .dw $ff05
+ .db "PORTG",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTG
+XT_PORTG:
+ .dw PFA_DOVARIABLE
+PFA_PORTG:
+ .dw 52
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port G
+VE_DDRG:
+ .dw $ff04
+ .db "DDRG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRG
+XT_DDRG:
+ .dw PFA_DOVARIABLE
+PFA_DDRG:
+ .dw 51
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port G
+VE_PING:
+ .dw $ff04
+ .db "PING"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PING
+XT_PING:
+ .dw PFA_DOVARIABLE
+PFA_PING:
+ .dw 50
+
+.endif
+.if WANT_JTAG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; On-Chip Debug Related Register in I/O Memory
+VE_OCDR:
+ .dw $ff04
+ .db "OCDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCDR
+XT_OCDR:
+ .dw PFA_DOVARIABLE
+PFA_OCDR:
+ .dw 81
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw 85
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Status Register
+VE_MCUSR:
+ .dw $ff05
+ .db "MCUSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUSR
+XT_MCUSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUSR:
+ .dw 84
+
+.endif
+.if WANT_SPI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR:
+ .dw $ff04
+ .db "SPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR
+XT_SPCR:
+ .dw PFA_DOVARIABLE
+PFA_SPCR:
+ .dw 76
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR:
+ .dw $ff04
+ .db "SPSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR
+XT_SPSR:
+ .dw PFA_DOVARIABLE
+PFA_SPSR:
+ .dw 77
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR:
+ .dw $ff04
+ .db "SPDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR
+XT_SPDR:
+ .dw PFA_DOVARIABLE
+PFA_SPDR:
+ .dw 78
+
+.endif
+.if WANT_TWI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Bit Rate register
+VE_TWBR:
+ .dw $ff04
+ .db "TWBR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWBR
+XT_TWBR:
+ .dw PFA_DOVARIABLE
+PFA_TWBR:
+ .dw 184
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Control Register
+VE_TWCR:
+ .dw $ff04
+ .db "TWCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWCR
+XT_TWCR:
+ .dw PFA_DOVARIABLE
+PFA_TWCR:
+ .dw 188
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Status Register
+VE_TWSR:
+ .dw $ff04
+ .db "TWSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWSR
+XT_TWSR:
+ .dw PFA_DOVARIABLE
+PFA_TWSR:
+ .dw 185
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Data register
+VE_TWDR:
+ .dw $ff04
+ .db "TWDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWDR
+XT_TWDR:
+ .dw PFA_DOVARIABLE
+PFA_TWDR:
+ .dw 187
+; ( -- addr ) System Constant
+; R( -- )
+; TWI (Slave) Address register
+VE_TWAR:
+ .dw $ff04
+ .db "TWAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWAR
+XT_TWAR:
+ .dw PFA_DOVARIABLE
+PFA_TWAR:
+ .dw 186
+
+.endif
+.if WANT_USART0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR0:
+ .dw $ff04
+ .db "UDR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR0
+XT_UDR0:
+ .dw PFA_DOVARIABLE
+PFA_UDR0:
+ .dw 198
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR0A:
+ .dw $ff06
+ .db "UCSR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0A
+XT_UCSR0A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0A:
+ .dw 192
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR0B:
+ .dw $ff06
+ .db "UCSR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0B
+XT_UCSR0B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0B:
+ .dw 193
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR0C:
+ .dw $ff06
+ .db "UCSR0C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0C
+XT_UCSR0C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0C:
+ .dw 194
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register t Bytes
+VE_UBRR0:
+ .dw $ff05
+ .db "UBRR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR0
+XT_UBRR0:
+ .dw PFA_DOVARIABLE
+PFA_UBRR0:
+ .dw 196
+
+.endif
+.if WANT_USART1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR1:
+ .dw $ff04
+ .db "UDR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR1
+XT_UDR1:
+ .dw PFA_DOVARIABLE
+PFA_UDR1:
+ .dw 206
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR1A:
+ .dw $ff06
+ .db "UCSR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1A
+XT_UCSR1A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1A:
+ .dw 200
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR1B:
+ .dw $ff06
+ .db "UCSR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1B
+XT_UCSR1B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1B:
+ .dw 201
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR1C:
+ .dw $ff06
+ .db "UCSR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1C
+XT_UCSR1C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1C:
+ .dw 202
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register t Bytes
+VE_UBRR1:
+ .dw $ff05
+ .db "UBRR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR1
+XT_UBRR1:
+ .dw PFA_DOVARIABLE
+PFA_UBRR1:
+ .dw 204
+
+.endif
+.if WANT_CPU == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw 95
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer
+VE_SP:
+ .dw $ff02
+ .db "SP"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SP
+XT_SP:
+ .dw PFA_DOVARIABLE
+PFA_SP:
+ .dw 93
+; ( -- addr ) System Constant
+; R( -- )
+; External Memory Control Register A
+VE_XMCRA:
+ .dw $ff05
+ .db "XMCRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_XMCRA
+XT_XMCRA:
+ .dw PFA_DOVARIABLE
+PFA_XMCRA:
+ .dw 116
+; ( -- addr ) System Constant
+; R( -- )
+; External Memory Control Register B
+VE_XMCRB:
+ .dw $ff05
+ .db "XMCRB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_XMCRB
+XT_XMCRB:
+ .dw PFA_DOVARIABLE
+PFA_XMCRB:
+ .dw 117
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Calibration Value
+VE_OSCCAL:
+ .dw $ff06
+ .db "OSCCAL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSCCAL
+XT_OSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_OSCCAL:
+ .dw 102
+; ( -- addr ) System Constant
+; R( -- )
+; Clock Prescale Register
+VE_CLKPR:
+ .dw $ff05
+ .db "CLKPR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKPR
+XT_CLKPR:
+ .dw PFA_DOVARIABLE
+PFA_CLKPR:
+ .dw 97
+; ( -- addr ) System Constant
+; R( -- )
+; Sleep Mode Control Register
+VE_SMCR:
+ .dw $ff04
+ .db "SMCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SMCR
+XT_SMCR:
+ .dw PFA_DOVARIABLE
+PFA_SMCR:
+ .dw 83
+; ( -- addr ) System Constant
+; R( -- )
+; RAM Page Z Select Register - Not used.
+VE_RAMPZ:
+ .dw $ff05
+ .db "RAMPZ",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_RAMPZ
+XT_RAMPZ:
+ .dw PFA_DOVARIABLE
+PFA_RAMPZ:
+ .dw 91
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 2
+VE_GPIOR2:
+ .dw $ff06
+ .db "GPIOR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR2
+XT_GPIOR2:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR2:
+ .dw 75
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 1
+VE_GPIOR1:
+ .dw $ff06
+ .db "GPIOR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR1
+XT_GPIOR1:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR1:
+ .dw 74
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 0
+VE_GPIOR0:
+ .dw $ff06
+ .db "GPIOR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR0
+XT_GPIOR0:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR0:
+ .dw 62
+
+.endif
+.if WANT_BOOT_LOAD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control Register
+VE_SPMCSR:
+ .dw $ff06
+ .db "SPMCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCSR
+XT_SPMCSR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCSR:
+ .dw 87
+
+.endif
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register A
+VE_EICRA:
+ .dw $ff05
+ .db "EICRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRA
+XT_EICRA:
+ .dw PFA_DOVARIABLE
+PFA_EICRA:
+ .dw 105
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register B
+VE_EICRB:
+ .dw $ff05
+ .db "EICRB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRB
+XT_EICRB:
+ .dw PFA_DOVARIABLE
+PFA_EICRB:
+ .dw 106
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Mask Register
+VE_EIMSK:
+ .dw $ff05
+ .db "EIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIMSK
+XT_EIMSK:
+ .dw PFA_DOVARIABLE
+PFA_EIMSK:
+ .dw 61
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Flag Register
+VE_EIFR:
+ .dw $ff04
+ .db "EIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIFR
+XT_EIFR:
+ .dw PFA_DOVARIABLE
+PFA_EIFR:
+ .dw 60
+
+.endif
+.if WANT_EEPROM == 1
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Read/Write Access Bytes
+VE_EEAR:
+ .dw $ff04
+ .db "EEAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEAR
+XT_EEAR:
+ .dw PFA_DOVARIABLE
+PFA_EEAR:
+ .dw 65
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw 64
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw 63
+
+.endif
+.if WANT_TIMER_COUNTER_0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Control Register
+VE_TCCR0A:
+ .dw $ff06
+ .db "TCCR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0A
+XT_TCCR0A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0A:
+ .dw 68
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw 70
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0A:
+ .dw $ff05
+ .db "OCR0A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0A
+XT_OCR0A:
+ .dw PFA_DOVARIABLE
+PFA_OCR0A:
+ .dw 71
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Mask Register
+VE_TIMSK0:
+ .dw $ff06
+ .db "TIMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK0
+XT_TIMSK0:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK0:
+ .dw 110
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Flag register
+VE_TIFR0:
+ .dw $ff05
+ .db "TIFR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR0
+XT_TIFR0:
+ .dw PFA_DOVARIABLE
+PFA_TIFR0:
+ .dw 53
+; ( -- addr ) System Constant
+; R( -- )
+; General Timer/Control Register
+VE_GTCCR:
+ .dw $ff05
+ .db "GTCCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GTCCR
+XT_GTCCR:
+ .dw PFA_DOVARIABLE
+PFA_GTCCR:
+ .dw 67
+
+.endif
+.if WANT_TIMER_COUNTER_2 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register
+VE_TCCR2:
+ .dw $ff05
+ .db "TCCR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2
+XT_TCCR2:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2:
+ .dw 176
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2
+VE_TCNT2:
+ .dw $ff05
+ .db "TCNT2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT2
+XT_TCNT2:
+ .dw PFA_DOVARIABLE
+PFA_TCNT2:
+ .dw 178
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register
+VE_OCR2A:
+ .dw $ff05
+ .db "OCR2A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2A
+XT_OCR2A:
+ .dw PFA_DOVARIABLE
+PFA_OCR2A:
+ .dw 179
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Mask register
+VE_TIMSK2:
+ .dw $ff06
+ .db "TIMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK2
+XT_TIMSK2:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK2:
+ .dw 112
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Flag Register
+VE_TIFR2:
+ .dw $ff05
+ .db "TIFR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR2
+XT_TIFR2:
+ .dw PFA_DOVARIABLE
+PFA_TIFR2:
+ .dw 55
+; ( -- addr ) System Constant
+; R( -- )
+; Asynchronous Status Register
+VE_ASSR:
+ .dw $ff04
+ .db "ASSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ASSR
+XT_ASSR:
+ .dw PFA_DOVARIABLE
+PFA_ASSR:
+ .dw 182
+
+.endif
+.if WANT_TIMER_COUNTER_1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw 128
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw 129
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter 1 Control Register C
+VE_TCCR1C:
+ .dw $ff06
+ .db "TCCR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1C
+XT_TCCR1C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1C:
+ .dw 130
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Bytes
+VE_TCNT1:
+ .dw $ff05
+ .db "TCNT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1
+XT_TCNT1:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1:
+ .dw 132
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register Bytes
+VE_OCR1A:
+ .dw $ff05
+ .db "OCR1A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1A
+XT_OCR1A:
+ .dw PFA_DOVARIABLE
+PFA_OCR1A:
+ .dw 136
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register Bytes
+VE_OCR1B:
+ .dw $ff05
+ .db "OCR1B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1B
+XT_OCR1B:
+ .dw PFA_DOVARIABLE
+PFA_OCR1B:
+ .dw 138
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register Bytes
+VE_OCR1C:
+ .dw $ff05
+ .db "OCR1C",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1C
+XT_OCR1C:
+ .dw PFA_DOVARIABLE
+PFA_OCR1C:
+ .dw 140
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Bytes
+VE_ICR1:
+ .dw $ff04
+ .db "ICR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1
+XT_ICR1:
+ .dw PFA_DOVARIABLE
+PFA_ICR1:
+ .dw 134
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Mask Register
+VE_TIMSK1:
+ .dw $ff06
+ .db "TIMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK1
+XT_TIMSK1:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK1:
+ .dw 111
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Flag register
+VE_TIFR1:
+ .dw $ff05
+ .db "TIFR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR1
+XT_TIFR1:
+ .dw PFA_DOVARIABLE
+PFA_TIFR1:
+ .dw 54
+
+.endif
+.if WANT_TIMER_COUNTER_3 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Control Register A
+VE_TCCR3A:
+ .dw $ff06
+ .db "TCCR3A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR3A
+XT_TCCR3A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR3A:
+ .dw 144
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Control Register B
+VE_TCCR3B:
+ .dw $ff06
+ .db "TCCR3B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR3B
+XT_TCCR3B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR3B:
+ .dw 145
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter 3 Control Register C
+VE_TCCR3C:
+ .dw $ff06
+ .db "TCCR3C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR3C
+XT_TCCR3C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR3C:
+ .dw 146
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Bytes
+VE_TCNT3:
+ .dw $ff05
+ .db "TCNT3",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT3
+XT_TCNT3:
+ .dw PFA_DOVARIABLE
+PFA_TCNT3:
+ .dw 148
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Output Compare Register Bytes
+VE_OCR3A:
+ .dw $ff05
+ .db "OCR3A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR3A
+XT_OCR3A:
+ .dw PFA_DOVARIABLE
+PFA_OCR3A:
+ .dw 152
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Output Compare Register Bytes
+VE_OCR3B:
+ .dw $ff05
+ .db "OCR3B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR3B
+XT_OCR3B:
+ .dw PFA_DOVARIABLE
+PFA_OCR3B:
+ .dw 154
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Output Compare Register Bytes
+VE_OCR3C:
+ .dw $ff05
+ .db "OCR3C",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR3C
+XT_OCR3C:
+ .dw PFA_DOVARIABLE
+PFA_OCR3C:
+ .dw 156
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Input Capture Register Bytes
+VE_ICR3:
+ .dw $ff04
+ .db "ICR3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR3
+XT_ICR3:
+ .dw PFA_DOVARIABLE
+PFA_ICR3:
+ .dw 150
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Mask Register
+VE_TIMSK3:
+ .dw $ff06
+ .db "TIMSK3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK3
+XT_TIMSK3:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK3:
+ .dw 113
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Flag register
+VE_TIFR3:
+ .dw $ff05
+ .db "TIFR3",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR3
+XT_TIFR3:
+ .dw PFA_DOVARIABLE
+PFA_TIFR3:
+ .dw 56
+
+.endif
+.if WANT_WATCHDOG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCR:
+ .dw $ff05
+ .db "WDTCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCR
+XT_WDTCR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCR:
+ .dw 96
+
+.endif
+.if WANT_AD_CONVERTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC multiplexer Selection Register
+VE_ADMUX:
+ .dw $ff05
+ .db "ADMUX",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADMUX
+XT_ADMUX:
+ .dw PFA_DOVARIABLE
+PFA_ADMUX:
+ .dw 124
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register
+VE_ADCSRA:
+ .dw $ff06
+ .db "ADCSRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRA
+XT_ADCSRA:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRA:
+ .dw 122
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register Bytes
+VE_ADC:
+ .dw $ff03
+ .db "ADC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADC
+XT_ADC:
+ .dw PFA_DOVARIABLE
+PFA_ADC:
+ .dw 120
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Control and Status Register B
+VE_ADCSRB:
+ .dw $ff06
+ .db "ADCSRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRB
+XT_ADCSRB:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRB:
+ .dw 123
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 1
+VE_DIDR0:
+ .dw $ff05
+ .db "DIDR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR0
+XT_DIDR0:
+ .dw PFA_DOVARIABLE
+PFA_DIDR0:
+ .dw 126
+
+.endif
+.if WANT_ANALOG_COMPARATOR == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Control And Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw 80
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_DIDR1:
+ .dw $ff05
+ .db "DIDR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR1
+XT_DIDR1:
+ .dw PFA_DOVARIABLE
+PFA_DIDR1:
+ .dw 127
+
+.endif
+.if WANT_CAN == 1
+; ( -- addr ) System Constant
+; R( -- )
+; CAN General Control Register
+VE_CANGCON:
+ .dw $ff07
+ .db "CANGCON",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANGCON
+XT_CANGCON:
+ .dw PFA_DOVARIABLE
+PFA_CANGCON:
+ .dw 216
+; ( -- addr ) System Constant
+; R( -- )
+; CAN General Status Register
+VE_CANGSTA:
+ .dw $ff07
+ .db "CANGSTA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANGSTA
+XT_CANGSTA:
+ .dw PFA_DOVARIABLE
+PFA_CANGSTA:
+ .dw 217
+; ( -- addr ) System Constant
+; R( -- )
+; CAN General Interrupt Register
+VE_CANGIT:
+ .dw $ff06
+ .db "CANGIT"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANGIT
+XT_CANGIT:
+ .dw PFA_DOVARIABLE
+PFA_CANGIT:
+ .dw 218
+; ( -- addr ) System Constant
+; R( -- )
+; CAN General Interrupt Enable Register
+VE_CANGIE:
+ .dw $ff06
+ .db "CANGIE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANGIE
+XT_CANGIE:
+ .dw PFA_DOVARIABLE
+PFA_CANGIE:
+ .dw 219
+; ( -- addr ) System Constant
+; R( -- )
+; Enable MOb Register
+VE_CANEN2:
+ .dw $ff06
+ .db "CANEN2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANEN2
+XT_CANEN2:
+ .dw PFA_DOVARIABLE
+PFA_CANEN2:
+ .dw 220
+; ( -- addr ) System Constant
+; R( -- )
+; Enable MOb Register
+VE_CANEN1:
+ .dw $ff06
+ .db "CANEN1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANEN1
+XT_CANEN1:
+ .dw PFA_DOVARIABLE
+PFA_CANEN1:
+ .dw 221
+; ( -- addr ) System Constant
+; R( -- )
+; Enable Interrupt MOb Register
+VE_CANIE2:
+ .dw $ff06
+ .db "CANIE2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANIE2
+XT_CANIE2:
+ .dw PFA_DOVARIABLE
+PFA_CANIE2:
+ .dw 222
+; ( -- addr ) System Constant
+; R( -- )
+; Enable Interrupt MOb Register
+VE_CANIE1:
+ .dw $ff06
+ .db "CANIE1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANIE1
+XT_CANIE1:
+ .dw PFA_DOVARIABLE
+PFA_CANIE1:
+ .dw 223
+; ( -- addr ) System Constant
+; R( -- )
+; CAN Status Interrupt MOb Register
+VE_CANSIT2:
+ .dw $ff07
+ .db "CANSIT2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANSIT2
+XT_CANSIT2:
+ .dw PFA_DOVARIABLE
+PFA_CANSIT2:
+ .dw 224
+; ( -- addr ) System Constant
+; R( -- )
+; CAN Status Interrupt MOb Register
+VE_CANSIT1:
+ .dw $ff07
+ .db "CANSIT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANSIT1
+XT_CANSIT1:
+ .dw PFA_DOVARIABLE
+PFA_CANSIT1:
+ .dw 225
+; ( -- addr ) System Constant
+; R( -- )
+; Bit Timing Register 1
+VE_CANBT1:
+ .dw $ff06
+ .db "CANBT1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANBT1
+XT_CANBT1:
+ .dw PFA_DOVARIABLE
+PFA_CANBT1:
+ .dw 226
+; ( -- addr ) System Constant
+; R( -- )
+; Bit Timing Register 2
+VE_CANBT2:
+ .dw $ff06
+ .db "CANBT2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANBT2
+XT_CANBT2:
+ .dw PFA_DOVARIABLE
+PFA_CANBT2:
+ .dw 227
+; ( -- addr ) System Constant
+; R( -- )
+; Bit Timing Register 3
+VE_CANBT3:
+ .dw $ff06
+ .db "CANBT3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANBT3
+XT_CANBT3:
+ .dw PFA_DOVARIABLE
+PFA_CANBT3:
+ .dw 228
+; ( -- addr ) System Constant
+; R( -- )
+; Timer Control Register
+VE_CANTCON:
+ .dw $ff07
+ .db "CANTCON",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANTCON
+XT_CANTCON:
+ .dw PFA_DOVARIABLE
+PFA_CANTCON:
+ .dw 229
+; ( -- addr ) System Constant
+; R( -- )
+; Timer Register Low
+VE_CANTIML:
+ .dw $ff07
+ .db "CANTIML",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANTIML
+XT_CANTIML:
+ .dw PFA_DOVARIABLE
+PFA_CANTIML:
+ .dw 230
+; ( -- addr ) System Constant
+; R( -- )
+; Timer Register High
+VE_CANTIMH:
+ .dw $ff07
+ .db "CANTIMH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANTIMH
+XT_CANTIMH:
+ .dw PFA_DOVARIABLE
+PFA_CANTIMH:
+ .dw 231
+; ( -- addr ) System Constant
+; R( -- )
+; TTC Timer Register Low
+VE_CANTTCL:
+ .dw $ff07
+ .db "CANTTCL",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANTTCL
+XT_CANTTCL:
+ .dw PFA_DOVARIABLE
+PFA_CANTTCL:
+ .dw 232
+; ( -- addr ) System Constant
+; R( -- )
+; TTC Timer Register High
+VE_CANTTCH:
+ .dw $ff07
+ .db "CANTTCH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANTTCH
+XT_CANTTCH:
+ .dw PFA_DOVARIABLE
+PFA_CANTTCH:
+ .dw 233
+; ( -- addr ) System Constant
+; R( -- )
+; Transmit Error Counter Register
+VE_CANTEC:
+ .dw $ff06
+ .db "CANTEC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANTEC
+XT_CANTEC:
+ .dw PFA_DOVARIABLE
+PFA_CANTEC:
+ .dw 234
+; ( -- addr ) System Constant
+; R( -- )
+; Receive Error Counter Register
+VE_CANREC:
+ .dw $ff06
+ .db "CANREC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANREC
+XT_CANREC:
+ .dw PFA_DOVARIABLE
+PFA_CANREC:
+ .dw 235
+; ( -- addr ) System Constant
+; R( -- )
+; Highest Priority MOb Register
+VE_CANHPMOB:
+ .dw $ff08
+ .db "CANHPMOB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANHPMOB
+XT_CANHPMOB:
+ .dw PFA_DOVARIABLE
+PFA_CANHPMOB:
+ .dw 236
+; ( -- addr ) System Constant
+; R( -- )
+; Page MOb Register
+VE_CANPAGE:
+ .dw $ff07
+ .db "CANPAGE",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANPAGE
+XT_CANPAGE:
+ .dw PFA_DOVARIABLE
+PFA_CANPAGE:
+ .dw 237
+; ( -- addr ) System Constant
+; R( -- )
+; MOb Status Register
+VE_CANSTMOB:
+ .dw $ff08
+ .db "CANSTMOB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANSTMOB
+XT_CANSTMOB:
+ .dw PFA_DOVARIABLE
+PFA_CANSTMOB:
+ .dw 238
+; ( -- addr ) System Constant
+; R( -- )
+; MOb Control and DLC Register
+VE_CANCDMOB:
+ .dw $ff08
+ .db "CANCDMOB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANCDMOB
+XT_CANCDMOB:
+ .dw PFA_DOVARIABLE
+PFA_CANCDMOB:
+ .dw 239
+; ( -- addr ) System Constant
+; R( -- )
+; Identifier Tag Register 4
+VE_CANIDT4:
+ .dw $ff07
+ .db "CANIDT4",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANIDT4
+XT_CANIDT4:
+ .dw PFA_DOVARIABLE
+PFA_CANIDT4:
+ .dw 240
+; ( -- addr ) System Constant
+; R( -- )
+; Identifier Tag Register 3
+VE_CANIDT3:
+ .dw $ff07
+ .db "CANIDT3",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANIDT3
+XT_CANIDT3:
+ .dw PFA_DOVARIABLE
+PFA_CANIDT3:
+ .dw 241
+; ( -- addr ) System Constant
+; R( -- )
+; Identifier Tag Register 2
+VE_CANIDT2:
+ .dw $ff07
+ .db "CANIDT2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANIDT2
+XT_CANIDT2:
+ .dw PFA_DOVARIABLE
+PFA_CANIDT2:
+ .dw 242
+; ( -- addr ) System Constant
+; R( -- )
+; Identifier Tag Register 1
+VE_CANIDT1:
+ .dw $ff07
+ .db "CANIDT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANIDT1
+XT_CANIDT1:
+ .dw PFA_DOVARIABLE
+PFA_CANIDT1:
+ .dw 243
+; ( -- addr ) System Constant
+; R( -- )
+; Identifier Mask Register 4
+VE_CANIDM4:
+ .dw $ff07
+ .db "CANIDM4",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANIDM4
+XT_CANIDM4:
+ .dw PFA_DOVARIABLE
+PFA_CANIDM4:
+ .dw 244
+; ( -- addr ) System Constant
+; R( -- )
+; Identifier Mask Register 3
+VE_CANIDM3:
+ .dw $ff07
+ .db "CANIDM3",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANIDM3
+XT_CANIDM3:
+ .dw PFA_DOVARIABLE
+PFA_CANIDM3:
+ .dw 245
+; ( -- addr ) System Constant
+; R( -- )
+; Identifier Mask Register 2
+VE_CANIDM2:
+ .dw $ff07
+ .db "CANIDM2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANIDM2
+XT_CANIDM2:
+ .dw PFA_DOVARIABLE
+PFA_CANIDM2:
+ .dw 246
+; ( -- addr ) System Constant
+; R( -- )
+; Identifier Mask Register 1
+VE_CANIDM1:
+ .dw $ff07
+ .db "CANIDM1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANIDM1
+XT_CANIDM1:
+ .dw PFA_DOVARIABLE
+PFA_CANIDM1:
+ .dw 247
+; ( -- addr ) System Constant
+; R( -- )
+; Time Stamp Register Low
+VE_CANSTML:
+ .dw $ff07
+ .db "CANSTML",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANSTML
+XT_CANSTML:
+ .dw PFA_DOVARIABLE
+PFA_CANSTML:
+ .dw 248
+; ( -- addr ) System Constant
+; R( -- )
+; Time Stamp Register High
+VE_CANSTMH:
+ .dw $ff07
+ .db "CANSTMH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANSTMH
+XT_CANSTMH:
+ .dw PFA_DOVARIABLE
+PFA_CANSTMH:
+ .dw 249
+; ( -- addr ) System Constant
+; R( -- )
+; Message Data Register
+VE_CANMSG:
+ .dw $ff06
+ .db "CANMSG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANMSG
+XT_CANMSG:
+ .dw PFA_DOVARIABLE
+PFA_CANMSG:
+ .dw 250
+
+.endif
diff --git a/amforth-6.5/avr8/devices/at90can32/device.py b/amforth-6.5/avr8/devices/at90can32/device.py
new file mode 100644
index 0000000..b907435
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90can32/device.py
@@ -0,0 +1,507 @@
+# Generated Automatically
+
+# Partname AT90CAN32
+
+MCUREGS = {
+# Interrupt Vectors
+ 'INT0Addr' : '#2', # External Interrupt Request 0
+ 'INT1Addr' : '#4', # External Interrupt Request 1
+ 'INT2Addr' : '#6', # External Interrupt Request 2
+ 'INT3Addr' : '#8', # External Interrupt Request 3
+ 'INT4Addr' : '#10', # External Interrupt Request 4
+ 'INT5Addr' : '#12', # External Interrupt Request 5
+ 'INT6Addr' : '#14', # External Interrupt Request 6
+ 'INT7Addr' : '#16', # External Interrupt Request 7
+ 'TIMER2_COMPAddr' : '#18', # Timer/Counter2 Compare Match
+ 'TIMER2_OVFAddr' : '#20', # Timer/Counter2 Overflow
+ 'TIMER1_CAPTAddr' : '#22', # Timer/Counter1 Capture Event
+ 'TIMER1_COMPAAddr' : '#24', # Timer/Counter1 Compare Match A
+ 'TIMER1_COMPBAddr' : '#26', # Timer/Counter Compare Match B
+ 'TIMER1_COMPCAddr' : '#28', # Timer/Counter1 Compare Match C
+ 'TIMER1_OVFAddr' : '#30', # Timer/Counter1 Overflow
+ 'TIMER0_COMPAddr' : '#32', # Timer/Counter0 Compare Match
+ 'TIMER0_OVFAddr' : '#34', # Timer/Counter0 Overflow
+ 'CANITAddr' : '#36', # CAN Transfer Complete or Error
+ 'OVRITAddr' : '#38', # CAN Timer Overrun
+ 'SPI_STCAddr' : '#40', # SPI Serial Transfer Complete
+ 'USART0_RXAddr' : '#42', # USART0, Rx Complete
+ 'USART0_UDREAddr' : '#44', # USART0 Data Register Empty
+ 'USART0_TXAddr' : '#46', # USART0, Tx Complete
+ 'ANALOG_COMPAddr' : '#48', # Analog Comparator
+ 'ADCAddr' : '#50', # ADC Conversion Complete
+ 'EE_READYAddr' : '#52', # EEPROM Ready
+ 'TIMER3_CAPTAddr' : '#54', # Timer/Counter3 Capture Event
+ 'TIMER3_COMPAAddr' : '#56', # Timer/Counter3 Compare Match A
+ 'TIMER3_COMPBAddr' : '#58', # Timer/Counter3 Compare Match B
+ 'TIMER3_COMPCAddr' : '#60', # Timer/Counter3 Compare Match C
+ 'TIMER3_OVFAddr' : '#62', # Timer/Counter3 Overflow
+ 'USART1_RXAddr' : '#64', # USART1, Rx Complete
+ 'USART1_UDREAddr' : '#66', # USART1, Data Register Empty
+ 'USART1_TXAddr' : '#68', # USART1, Tx Complete
+ 'TWIAddr' : '#70', # 2-wire Serial Interface
+ 'SPM_READYAddr' : '#72', # Store Program Memory Read
+
+# Module PORTA
+ 'PORTA' : '$22', # Port A Data Register
+ 'DDRA' : '$21', # Port A Data Direction Register
+ 'PINA' : '$20', # Port A Input Pins
+
+# Module PORTB
+ 'PORTB' : '$25', # Port B Data Register
+ 'DDRB' : '$24', # Port B Data Direction Register
+ 'PINB' : '$23', # Port B Input Pins
+
+# Module PORTC
+ 'PORTC' : '$28', # Port C Data Register
+ 'DDRC' : '$27', # Port C Data Direction Register
+ 'PINC' : '$26', # Port C Input Pins
+
+# Module PORTD
+ 'PORTD' : '$2b', # Port D Data Register
+ 'DDRD' : '$2a', # Port D Data Direction Register
+ 'PIND' : '$29', # Port D Input Pins
+
+# Module PORTE
+ 'PORTE' : '$2e', # Data Register, Port E
+ 'DDRE' : '$2d', # Data Direction Register, Port
+ 'PINE' : '$2c', # Input Pins, Port E
+
+# Module PORTF
+ 'PORTF' : '$31', # Data Register, Port F
+ 'DDRF' : '$30', # Data Direction Register, Port
+ 'PINF' : '$2f', # Input Pins, Port F
+
+# Module PORTG
+ 'PORTG' : '$34', # Data Register, Port G
+ 'DDRG' : '$33', # Data Direction Register, Port
+ 'PING' : '$32', # Input Pins, Port G
+
+# Module JTAG
+ 'OCDR' : '$51', # On-Chip Debug Related Register
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_JTD': '$80', # JTAG Interface Disable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+
+# Module SPI
+ 'SPCR' : '$4c', # SPI Control Register
+ 'SPCR_SPIE': '$80', # SPI Interrupt Enable
+ 'SPCR_SPE': '$40', # SPI Enable
+ 'SPCR_DORD': '$20', # Data Order
+ 'SPCR_MSTR': '$10', # Master/Slave Select
+ 'SPCR_CPOL': '$8', # Clock polarity
+ 'SPCR_CPHA': '$4', # Clock Phase
+ 'SPCR_SPR': '$3', # SPI Clock Rate Selects
+ 'SPSR' : '$4d', # SPI Status Register
+ 'SPSR_SPIF': '$80', # SPI Interrupt Flag
+ 'SPSR_WCOL': '$40', # Write Collision Flag
+ 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
+ 'SPDR' : '$4e', # SPI Data Register
+
+# Module TWI
+ 'TWBR' : '$b8', # TWI Bit Rate register
+ 'TWCR' : '$bc', # TWI Control Register
+ 'TWCR_TWINT': '$80', # TWI Interrupt Flag
+ 'TWCR_TWEA': '$40', # TWI Enable Acknowledge Bit
+ 'TWCR_TWSTA': '$20', # TWI Start Condition Bit
+ 'TWCR_TWSTO': '$10', # TWI Stop Condition Bit
+ 'TWCR_TWWC': '$8', # TWI Write Collition Flag
+ 'TWCR_TWEN': '$4', # TWI Enable Bit
+ 'TWCR_TWIE': '$1', # TWI Interrupt Enable
+ 'TWSR' : '$b9', # TWI Status Register
+ 'TWSR_TWS': '$f8', # TWI Status
+ 'TWSR_TWPS': '$3', # TWI Prescaler
+ 'TWDR' : '$bb', # TWI Data register
+ 'TWAR' : '$ba', # TWI (Slave) Address register
+ 'TWAR_TWA': '$fe', # TWI (Slave) Address register B
+ 'TWAR_TWGCE': '$1', # TWI General Call Recognition E
+
+# Module USART0
+ 'UDR0' : '$c6', # USART I/O Data Register
+ 'UCSR0A' : '$c0', # USART Control and Status Regis
+ 'UCSR0A_RXC0': '$80', # USART Receive Complete
+ 'UCSR0A_TXC0': '$40', # USART Transmitt Complete
+ 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
+ 'UCSR0A_FE0': '$10', # Framing Error
+ 'UCSR0A_DOR0': '$8', # Data overRun
+ 'UCSR0A_UPE0': '$4', # Parity Error
+ 'UCSR0A_U2X0': '$2', # Double the USART transmission
+ 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
+ 'UCSR0B' : '$c1', # USART Control and Status Regis
+ 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
+ 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
+ 'UCSR0B_UDRIE0': '$20', # USART Data register Empty Inte
+ 'UCSR0B_RXEN0': '$10', # Receiver Enable
+ 'UCSR0B_TXEN0': '$8', # Transmitter Enable
+ 'UCSR0B_UCSZ02': '$4', # Character Size
+ 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
+ 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
+ 'UCSR0C' : '$c2', # USART Control and Status Regis
+ 'UCSR0C_UMSEL0': '$40', # USART Mode Select
+ 'UCSR0C_UPM0': '$30', # Parity Mode Bits
+ 'UCSR0C_USBS0': '$8', # Stop Bit Select
+ 'UCSR0C_UCSZ0': '$6', # Character Size
+ 'UCSR0C_UCPOL0': '$1', # Clock Polarity
+ 'UBRR0' : '$c4', # USART Baud Rate Register t Byt
+
+# Module USART1
+ 'UDR1' : '$ce', # USART I/O Data Register
+ 'UCSR1A' : '$c8', # USART Control and Status Regis
+ 'UCSR1A_RXC1': '$80', # USART Receive Complete
+ 'UCSR1A_TXC1': '$40', # USART Transmitt Complete
+ 'UCSR1A_UDRE1': '$20', # USART Data Register Empty
+ 'UCSR1A_FE1': '$10', # Framing Error
+ 'UCSR1A_DOR1': '$8', # Data overRun
+ 'UCSR1A_UPE1': '$4', # Parity Error
+ 'UCSR1A_U2X1': '$2', # Double the USART transmission
+ 'UCSR1A_MPCM1': '$1', # Multi-processor Communication
+ 'UCSR1B' : '$c9', # USART Control and Status Regis
+ 'UCSR1B_RXCIE1': '$80', # RX Complete Interrupt Enable
+ 'UCSR1B_TXCIE1': '$40', # TX Complete Interrupt Enable
+ 'UCSR1B_UDRIE1': '$20', # USART Data register Empty Inte
+ 'UCSR1B_RXEN1': '$10', # Receiver Enable
+ 'UCSR1B_TXEN1': '$8', # Transmitter Enable
+ 'UCSR1B_UCSZ12': '$4', # Character Size
+ 'UCSR1B_RXB81': '$2', # Receive Data Bit 8
+ 'UCSR1B_TXB81': '$1', # Transmit Data Bit 8
+ 'UCSR1C' : '$ca', # USART Control and Status Regis
+ 'UCSR1C_UMSEL1': '$40', # USART Mode Select
+ 'UCSR1C_UPM1': '$30', # Parity Mode Bits
+ 'UCSR1C_USBS1': '$8', # Stop Bit Select
+ 'UCSR1C_UCSZ1': '$6', # Character Size
+ 'UCSR1C_UCPOL1': '$1', # Clock Polarity
+ 'UBRR1' : '$cc', # USART Baud Rate Register t Byt
+
+# Module CPU
+ 'SREG' : '$5f', # Status Register
+ 'SREG_I': '$80', # Global Interrupt Enable
+ 'SREG_T': '$40', # Bit Copy Storage
+ 'SREG_H': '$20', # Half Carry Flag
+ 'SREG_S': '$10', # Sign Bit
+ 'SREG_V': '$8', # Two's Complement Overflow Flag
+ 'SREG_N': '$4', # Negative Flag
+ 'SREG_Z': '$2', # Zero Flag
+ 'SREG_C': '$1', # Carry Flag
+ 'SP' : '$5d', # Stack Pointer
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_PUD': '$10', # Pull-up disable
+ 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
+ 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+ 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
+ 'MCUSR_BORF': '$4', # Brown-out Reset Flag
+ 'MCUSR_EXTRF': '$2', # External Reset Flag
+ 'MCUSR_PORF': '$1', # Power-on reset flag
+ 'XMCRA' : '$74', # External Memory Control Regist
+ 'XMCRA_SRE': '$80', # External SRAM Enable
+ 'XMCRA_SRL': '$70', # Wait state page limit
+ 'XMCRA_SRW1': '$c', # Wait state select bit upper pa
+ 'XMCRA_SRW0': '$3', # Wait state select bit lower pa
+ 'XMCRB' : '$75', # External Memory Control Regist
+ 'XMCRB_XMBK': '$80', # External Memory Bus Keeper Ena
+ 'XMCRB_XMM': '$7', # External Memory High Mask
+ 'OSCCAL' : '$66', # Oscillator Calibration Value
+ 'CLKPR' : '$61', # Clock Prescale Register
+ 'CLKPR_CLKPCE': '$80', #
+ 'CLKPR_CLKPS': '$f', #
+ 'SMCR' : '$53', # Sleep Mode Control Register
+ 'SMCR_SM': '$e', # Sleep Mode Select bits
+ 'SMCR_SE': '$1', # Sleep Enable
+ 'RAMPZ' : '$5b', # RAM Page Z Select Register - N
+ 'RAMPZ_RAMPZ0': '$1', # RAM Page Z Select Register Bit
+ 'GPIOR2' : '$4b', # General Purpose IO Register 2
+ 'GPIOR2_GPIOR': '$ff', # General Purpose IO Register 2
+ 'GPIOR1' : '$4a', # General Purpose IO Register 1
+ 'GPIOR1_GPIOR': '$ff', # General Purpose IO Register 1
+ 'GPIOR0' : '$3e', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR07': '$80', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR06': '$40', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR05': '$20', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR04': '$10', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR03': '$8', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR02': '$4', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR01': '$2', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR00': '$1', # General Purpose IO Register 0
+
+# Module BOOT_LOAD
+ 'SPMCSR' : '$57', # Store Program Memory Control R
+ 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
+ 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
+ 'SPMCSR_RWWSRE': '$10', # Read While Write section read
+ 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
+ 'SPMCSR_PGWRT': '$4', # Page Write
+ 'SPMCSR_PGERS': '$2', # Page Erase
+ 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
+
+# Module EXTERNAL_INTERRUPT
+ 'EICRA' : '$69', # External Interrupt Control Reg
+ 'EICRA_ISC3': '$c0', # External Interrupt Sense Contr
+ 'EICRA_ISC2': '$30', # External Interrupt Sense Contr
+ 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
+ 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
+ 'EICRB' : '$6a', # External Interrupt Control Reg
+ 'EICRB_ISC7': '$c0', # External Interrupt 7-4 Sense C
+ 'EICRB_ISC6': '$30', # External Interrupt 7-4 Sense C
+ 'EICRB_ISC5': '$c', # External Interrupt 7-4 Sense C
+ 'EICRB_ISC4': '$3', # External Interrupt 7-4 Sense C
+ 'EIMSK' : '$3d', # External Interrupt Mask Regist
+ 'EIMSK_INT': '$ff', # External Interrupt Request 7 E
+ 'EIFR' : '$3c', # External Interrupt Flag Regist
+ 'EIFR_INTF': '$ff', # External Interrupt Flags
+
+# Module EEPROM
+ 'EEAR' : '$41', # EEPROM Read/Write Access Byte
+ 'EEDR' : '$40', # EEPROM Data Register
+ 'EECR' : '$3f', # EEPROM Control Register
+ 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
+ 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
+ 'EECR_EEWE': '$2', # EEPROM Write Enable
+ 'EECR_EERE': '$1', # EEPROM Read Enable
+
+# Module TIMER_COUNTER_0
+ 'TCCR0A' : '$44', # Timer/Counter0 Control Registe
+ 'TCCR0A_FOC0A': '$80', # Force Output Compare
+ 'TCCR0A_WGM00': '$40', # Waveform Generation Mode 0
+ 'TCCR0A_COM0A': '$30', # Compare Match Output Modes
+ 'TCCR0A_WGM01': '$8', # Waveform Generation Mode 1
+ 'TCCR0A_CS0': '$7', # Clock Selects
+ 'TCNT0' : '$46', # Timer/Counter0
+ 'OCR0A' : '$47', # Timer/Counter0 Output Compare
+ 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
+ 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
+ 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
+ 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
+ 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
+ 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Control Register
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSR310': '$1', # Prescaler Reset Timer/Counter1
+
+# Module TIMER_COUNTER_2
+ 'TCCR2' : '$b0', # Timer/Counter2 Control Registe
+ 'TCCR2_FOC2A': '$80', # Force Output Compare
+ 'TCCR2_WGM20': '$40', # Waveform Genration Mode
+ 'TCCR2_COM2A': '$30', # Compare Output Mode bits
+ 'TCCR2_WGM21': '$8', # Waveform Generation Mode
+ 'TCCR2_CS2': '$7', # Clock Select bits
+ 'TCNT2' : '$b2', # Timer/Counter2
+ 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
+ 'TIMSK2' : '$70', # Timer/Counter Interrupt Mask r
+ 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
+ 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
+ 'TIFR2' : '$37', # Timer/Counter Interrupt Flag R
+ 'TIFR2_OCF2A': '$2', # Output Compare Flag 2
+ 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_PSR2': '$2', # Prescaler Reset Timer/Counter2
+ 'ASSR' : '$b6', # Asynchronous Status Register
+ 'ASSR_EXCLK': '$10', # Enable External Clock Interrup
+ 'ASSR_AS2': '$8', # AS2: Asynchronous Timer/Counte
+ 'ASSR_TCN2UB': '$4', # TCN2UB: Timer/Counter2 Update
+ 'ASSR_OCR2UB': '$2', # Output Compare Register2 Updat
+ 'ASSR_TCR2UB': '$1', # TCR2UB: Timer/Counter Control
+
+# Module TIMER_COUNTER_1
+ 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
+ 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
+ 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
+ 'TCCR1A_COM1C': '$c', # Compare Output Mode 1C, bits
+ 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
+ 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
+ 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
+ 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
+ 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
+ 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
+ 'TCCR1C' : '$82', # Timer/Counter 1 Control Regist
+ 'TCCR1C_FOC1A': '$80', # Force Output Compare 1A
+ 'TCCR1C_FOC1B': '$40', # Force Output Compare 1B
+ 'TCCR1C_FOC1C': '$20', # Force Output Compare 1C
+ 'TCNT1' : '$84', # Timer/Counter1 Bytes
+ 'OCR1A' : '$88', # Timer/Counter1 Output Compare
+ 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
+ 'OCR1C' : '$8c', # Timer/Counter1 Output Compare
+ 'ICR1' : '$86', # Timer/Counter1 Input Capture R
+ 'TIMSK1' : '$6f', # Timer/Counter Interrupt Mask R
+ 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
+ 'TIMSK1_OCIE1C': '$8', # Timer/Counter1 Output CompareC
+ 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output CompareB
+ 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output CompareA
+ 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
+ 'TIFR1' : '$36', # Timer/Counter Interrupt Flag r
+ 'TIFR1_ICF1': '$20', # Input Capture Flag 1
+ 'TIFR1_OCF1C': '$8', # Output Compare Flag 1C
+ 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
+ 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
+ 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
+
+# Module TIMER_COUNTER_3
+ 'TCCR3A' : '$90', # Timer/Counter3 Control Registe
+ 'TCCR3A_COM3A': '$c0', # Compare Output Mode 3A, bits
+ 'TCCR3A_COM3B': '$30', # Compare Output Mode 3B, bits
+ 'TCCR3A_COM3C': '$c', # Compare Output Mode 3C, bits
+ 'TCCR3A_WGM3': '$3', # Waveform Generation Mode
+ 'TCCR3B' : '$91', # Timer/Counter3 Control Registe
+ 'TCCR3B_ICNC3': '$80', # Input Capture 3 Noise Canceler
+ 'TCCR3B_ICES3': '$40', # Input Capture 3 Edge Select
+ 'TCCR3B_WGM3': '$18', # Waveform Generation Mode
+ 'TCCR3B_CS3': '$7', # Prescaler source of Timer/Coun
+ 'TCCR3C' : '$92', # Timer/Counter 3 Control Regist
+ 'TCCR3C_FOC3A': '$80', # Force Output Compare 3A
+ 'TCCR3C_FOC3B': '$40', # Force Output Compare 3B
+ 'TCCR3C_FOC3C': '$20', # Force Output Compare 3C
+ 'TCNT3' : '$94', # Timer/Counter3 Bytes
+ 'OCR3A' : '$98', # Timer/Counter3 Output Compare
+ 'OCR3B' : '$9a', # Timer/Counter3 Output Compare
+ 'OCR3C' : '$9c', # Timer/Counter3 Output Compare
+ 'ICR3' : '$96', # Timer/Counter3 Input Capture R
+ 'TIMSK3' : '$71', # Timer/Counter Interrupt Mask R
+ 'TIMSK3_ICIE3': '$20', # Timer/Counter3 Input Capture I
+ 'TIMSK3_OCIE3C': '$8', # Timer/Counter3 Output CompareC
+ 'TIMSK3_OCIE3B': '$4', # Timer/Counter3 Output CompareB
+ 'TIMSK3_OCIE3A': '$2', # Timer/Counter3 Output CompareA
+ 'TIMSK3_TOIE3': '$1', # Timer/Counter3 Overflow Interr
+ 'TIFR3' : '$38', # Timer/Counter Interrupt Flag r
+ 'TIFR3_ICF3': '$20', # Input Capture Flag 3
+ 'TIFR3_OCF3C': '$8', # Output Compare Flag 3C
+ 'TIFR3_OCF3B': '$4', # Output Compare Flag 3B
+ 'TIFR3_OCF3A': '$2', # Output Compare Flag 3A
+ 'TIFR3_TOV3': '$1', # Timer/Counter3 Overflow Flag
+
+# Module WATCHDOG
+ 'WDTCR' : '$60', # Watchdog Timer Control Registe
+ 'WDTCR_WDCE': '$10', # Watchdog Change Enable
+ 'WDTCR_WDE': '$8', # Watch Dog Enable
+ 'WDTCR_WDP': '$7', # Watch Dog Timer Prescaler bits
+
+# Module AD_CONVERTER
+ 'ADMUX' : '$7c', # The ADC multiplexer Selection
+ 'ADMUX_REFS': '$c0', # Reference Selection Bits
+ 'ADMUX_ADLAR': '$20', # Left Adjust Result
+ 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
+ 'ADCSRA' : '$7a', # The ADC Control and Status reg
+ 'ADCSRA_ADEN': '$80', # ADC Enable
+ 'ADCSRA_ADSC': '$40', # ADC Start Conversion
+ 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
+ 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
+ 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
+ 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
+ 'ADC' : '$78', # ADC Data Register Bytes
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ADHSM': '$80', # ADC High Speed Mode
+ 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Sources
+ 'DIDR0' : '$7e', # Digital Input Disable Register
+ 'DIDR0_ADC7D': '$80', # ADC7 Digital input Disable
+ 'DIDR0_ADC6D': '$40', # ADC6 Digital input Disable
+ 'DIDR0_ADC5D': '$20', # ADC5 Digital input Disable
+ 'DIDR0_ADC4D': '$10', # ADC4 Digital input Disable
+ 'DIDR0_ADC3D': '$8', # ADC3 Digital input Disable
+ 'DIDR0_ADC2D': '$4', # ADC2 Digital input Disable
+ 'DIDR0_ADC1D': '$2', # ADC1 Digital input Disable
+ 'DIDR0_ADC0D': '$1', # ADC0 Digital input Disable
+
+# Module ANALOG_COMPARATOR
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
+ 'ACSR' : '$50', # Analog Comparator Control And
+ 'ACSR_ACD': '$80', # Analog Comparator Disable
+ 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
+ 'ACSR_ACO': '$20', # Analog Compare Output
+ 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
+ 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
+ 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
+ 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
+ 'DIDR1' : '$7f', #
+ 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
+ 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
+
+# Module CAN
+ 'CANGCON' : '$d8', # CAN General Control Register
+ 'CANGCON_ABRQ': '$80', # Abort Request
+ 'CANGCON_OVRQ': '$40', # Overload Frame Request
+ 'CANGCON_TTC': '$20', # Time Trigger Communication
+ 'CANGCON_SYNTTC': '$10', # Synchronization of TTC
+ 'CANGCON_LISTEN': '$8', # Listening Mode
+ 'CANGCON_TEST': '$4', # Test Mode
+ 'CANGCON_ENASTB': '$2', # Enable / Standby
+ 'CANGCON_SWRES': '$1', # Software Reset Request
+ 'CANGSTA' : '$d9', # CAN General Status Register
+ 'CANGSTA_OVRG': '$40', # Overload Frame Flag
+ 'CANGSTA_TXBSY': '$10', # Transmitter Busy
+ 'CANGSTA_RXBSY': '$8', # Receiver Busy
+ 'CANGSTA_ENFG': '$4', # Enable Flag
+ 'CANGSTA_BOFF': '$2', # Bus Off Mode
+ 'CANGSTA_ERRP': '$1', # Error Passive Mode
+ 'CANGIT' : '$da', # CAN General Interrupt Register
+ 'CANGIT_CANIT': '$80', # General Interrupt Flag
+ 'CANGIT_BOFFIT': '$40', # Bus Off Interrupt Flag
+ 'CANGIT_OVRTIM': '$20', # Overrun CAN Timer
+ 'CANGIT_BXOK': '$10', # Burst Receive Interrupt
+ 'CANGIT_SERG': '$8', # Stuff Error General
+ 'CANGIT_CERG': '$4', # CRC Error General
+ 'CANGIT_FERG': '$2', # Form Error General
+ 'CANGIT_AERG': '$1', # Ackknowledgement Error General
+ 'CANGIE' : '$db', # CAN General Interrupt Enable R
+ 'CANGIE_ENIT': '$80', # Enable all Interrupts
+ 'CANGIE_ENBOFF': '$40', # Enable Bus Off INterrupt
+ 'CANGIE_ENRX': '$20', # Enable Receive Interrupt
+ 'CANGIE_ENTX': '$10', # Enable Transmitt Interrupt
+ 'CANGIE_ENERR': '$8', # Enable MOb Error Interrupt
+ 'CANGIE_ENBX': '$4', # Enable Burst Receive Interrupt
+ 'CANGIE_ENERG': '$2', # Enable General Error Interrupt
+ 'CANGIE_ENOVRT': '$1', # Enable CAN Timer Overrun Inter
+ 'CANEN2' : '$dc', # Enable MOb Register
+ 'CANEN1' : '$dd', # Enable MOb Register
+ 'CANIE2' : '$de', # Enable Interrupt MOb Register
+ 'CANIE1' : '$df', # Enable Interrupt MOb Register
+ 'CANSIT2' : '$e0', # CAN Status Interrupt MOb Regis
+ 'CANSIT1' : '$e1', # CAN Status Interrupt MOb Regis
+ 'CANBT1' : '$e2', # Bit Timing Register 1
+ 'CANBT1_BRP': '$7e', # Baud Rate Prescaler bits
+ 'CANBT2' : '$e3', # Bit Timing Register 2
+ 'CANBT2_SJW': '$60', # Re-Sync Jump Width
+ 'CANBT2_PRS': '$e', # Propagation Time Segment
+ 'CANBT3' : '$e4', # Bit Timing Register 3
+ 'CANBT3_PHS2': '$70', # Phase Segments
+ 'CANBT3_PHS1': '$e', # Phase Segment 1
+ 'CANBT3_SMP': '$1', # Sample Type
+ 'CANTCON' : '$e5', # Timer Control Register
+ 'CANTIML' : '$e6', # Timer Register Low
+ 'CANTIMH' : '$e7', # Timer Register High
+ 'CANTTCL' : '$e8', # TTC Timer Register Low
+ 'CANTTCH' : '$e9', # TTC Timer Register High
+ 'CANTEC' : '$ea', # Transmit Error Counter Registe
+ 'CANREC' : '$eb', # Receive Error Counter Register
+ 'CANHPMOB' : '$ec', # Highest Priority MOb Register
+ 'CANPAGE' : '$ed', # Page MOb Register
+ 'CANPAGE_MOBNB': '$f0', # MOb Number Bits
+ 'CANPAGE_AINC': '$8', # MOb Data Buffer Auto Increment
+ 'CANPAGE_INDX': '$7', # Data Buffer Index Bits
+ 'CANSTMOB' : '$ee', # MOb Status Register
+ 'CANSTMOB_DLCW': '$80', # Data Length Code Warning
+ 'CANSTMOB_TXOK': '$40', # Transmit OK
+ 'CANSTMOB_RXOK': '$20', # Receive OK
+ 'CANSTMOB_BERR': '$10', # Bit Error
+ 'CANSTMOB_SERR': '$8', # Stuff Error
+ 'CANSTMOB_CERR': '$4', # CRC Error
+ 'CANSTMOB_FERR': '$2', # Form Error
+ 'CANSTMOB_AERR': '$1', # Ackknowledgement Error
+ 'CANCDMOB' : '$ef', # MOb Control and DLC Register
+ 'CANCDMOB_CONMOB': '$c0', # MOb Config Bits
+ 'CANCDMOB_RPLV': '$20', # Reply Valid
+ 'CANCDMOB_IDE': '$10', # Identifier Extension
+ 'CANCDMOB_DLC': '$f', # Data Length Code Bits
+ 'CANIDT4' : '$f0', # Identifier Tag Register 4
+ 'CANIDT3' : '$f1', # Identifier Tag Register 3
+ 'CANIDT2' : '$f2', # Identifier Tag Register 2
+ 'CANIDT1' : '$f3', # Identifier Tag Register 1
+ 'CANIDM4' : '$f4', # Identifier Mask Register 4
+ 'CANIDM3' : '$f5', # Identifier Mask Register 3
+ 'CANIDM2' : '$f6', # Identifier Mask Register 2
+ 'CANIDM1' : '$f7', # Identifier Mask Register 1
+ 'CANSTML' : '$f8', # Time Stamp Register Low
+ 'CANSTMH' : '$f9', # Time Stamp Register High
+ 'CANMSG' : '$fa', # Message Data Register
+
+ '__amforth_dummy':'0'
+}
diff --git a/amforth-6.5/avr8/devices/at90can32/words/no-jtag.asm b/amforth-6.5/avr8/devices/at90can32/words/no-jtag.asm
new file mode 100644
index 0000000..352a4bb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90can32/words/no-jtag.asm
@@ -0,0 +1,14 @@
+; ( -- )
+; ( -- )
+; MCU
+; disable jtag at runtime
+VE_NOJTAG:
+ .dw $FF05
+ .db "-jtag",0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOJTAG
+XT_NOJTAG:
+ .dw PFA_NOJTAG
+PFA_NOJTAG:
+
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/at90can32/words/no-wdt.asm b/amforth-6.5/avr8/devices/at90can32/words/no-wdt.asm
new file mode 100644
index 0000000..4a12261
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90can32/words/no-wdt.asm
@@ -0,0 +1,22 @@
+; ( -- )
+; MCU
+; disable watch dog timer at runtime
+VE_NOWDT:
+ .dw $ff04
+ .db "-wdt"
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOWDT
+XT_NOWDT:
+ .dw PFA_NOWDT
+PFA_NOWDT:
+
+; Reset WDT
+ wdr
+; Write logical one to WDTOE and WDE
+ in_ temp1, WDTCR
+ ori temp1, (1<<WDTOE)|(1<<WDE)
+ out WDTCR, temp1
+; Turn off WDT
+ ldi temp1, (0<<WDE)
+ out_ WDTCR, temp1
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/at90can32/words/sleep.asm b/amforth-6.5/avr8/devices/at90can32/words/sleep.asm
new file mode 100644
index 0000000..256249c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90can32/words/sleep.asm
@@ -0,0 +1,19 @@
+; ( mode -- )
+; MCU
+; put the controller into the specified sleep mode
+VE_SLEEP:
+ .dw $ff05
+ .db "sleep", 0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_SLEEP
+XT_SLEEP:
+ .dw PFA_SLEEP
+PFA_SLEEP:
+ andi tosl, 7 ; leave only legal mode bits
+ lsl tosl ; move to correct location (bits 3-1)
+ ori tosl, 1 ; set the SE bit
+ out_ SMCR, tosl ; set the sleep config
+ sleep ; nighty-night
+ out_ SMCR, zerol ; 0 protects against accidental sleeps
+ loadtos ; pop argument from stack
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/at90can64/at90can64.frt b/amforth-6.5/avr8/devices/at90can64/at90can64.frt
new file mode 100644
index 0000000..41db98b
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90can64/at90can64.frt
@@ -0,0 +1,465 @@
+\ Partname: AT90CAN64
+\ generated automatically
+
+\ PORTA
+&34 constant PORTA \ Port A Data Register
+&33 constant DDRA \ Port A Data Direction Register
+&32 constant PINA \ Port A Input Pins
+\ PORTB
+&37 constant PORTB \ Port B Data Register
+&36 constant DDRB \ Port B Data Direction Register
+&35 constant PINB \ Port B Input Pins
+\ PORTC
+&40 constant PORTC \ Port C Data Register
+&39 constant DDRC \ Port C Data Direction Register
+&38 constant PINC \ Port C Input Pins
+\ PORTD
+&43 constant PORTD \ Port D Data Register
+&42 constant DDRD \ Port D Data Direction Register
+&41 constant PIND \ Port D Input Pins
+\ PORTE
+&46 constant PORTE \ Data Register, Port E
+&45 constant DDRE \ Data Direction Register, Port E
+&44 constant PINE \ Input Pins, Port E
+\ PORTF
+&49 constant PORTF \ Data Register, Port F
+&48 constant DDRF \ Data Direction Register, Port F
+&47 constant PINF \ Input Pins, Port F
+\ JTAG
+&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
+&85 constant MCUCR \ MCU Control Register
+ $80 constant MCUCR_JTD \ JTAG Interface Disable
+&84 constant MCUSR \ MCU Status Register
+ $10 constant MCUSR_JTRF \ JTAG Reset Flag
+\ SPI
+&76 constant SPCR \ SPI Control Register
+ $80 constant SPCR_SPIE \ SPI Interrupt Enable
+ $40 constant SPCR_SPE \ SPI Enable
+ $20 constant SPCR_DORD \ Data Order
+ $10 constant SPCR_MSTR \ Master/Slave Select
+ $08 constant SPCR_CPOL \ Clock polarity
+ $04 constant SPCR_CPHA \ Clock Phase
+ $03 constant SPCR_SPR \ SPI Clock Rate Selects
+&77 constant SPSR \ SPI Status Register
+ $80 constant SPSR_SPIF \ SPI Interrupt Flag
+ $40 constant SPSR_WCOL \ Write Collision Flag
+ $01 constant SPSR_SPI2X \ Double SPI Speed Bit
+&78 constant SPDR \ SPI Data Register
+\ TWI
+&184 constant TWBR \ TWI Bit Rate register
+&188 constant TWCR \ TWI Control Register
+ $80 constant TWCR_TWINT \ TWI Interrupt Flag
+ $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
+ $20 constant TWCR_TWSTA \ TWI Start Condition Bit
+ $10 constant TWCR_TWSTO \ TWI Stop Condition Bit
+ $08 constant TWCR_TWWC \ TWI Write Collition Flag
+ $04 constant TWCR_TWEN \ TWI Enable Bit
+ $01 constant TWCR_TWIE \ TWI Interrupt Enable
+&185 constant TWSR \ TWI Status Register
+ $F8 constant TWSR_TWS \ TWI Status
+ $03 constant TWSR_TWPS \ TWI Prescaler
+&187 constant TWDR \ TWI Data register
+&186 constant TWAR \ TWI (Slave) Address register
+ $FE constant TWAR_TWA \ TWI (Slave) Address register Bits
+ $01 constant TWAR_TWGCE \ TWI General Call Recognition Enable Bit
+\ USART0
+&198 constant UDR0 \ USART I/O Data Register
+&192 constant UCSR0A \ USART Control and Status Register A
+ $80 constant UCSR0A_RXC0 \ USART Receive Complete
+ $40 constant UCSR0A_TXC0 \ USART Transmitt Complete
+ $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
+ $10 constant UCSR0A_FE0 \ Framing Error
+ $08 constant UCSR0A_DOR0 \ Data overRun
+ $04 constant UCSR0A_UPE0 \ Parity Error
+ $02 constant UCSR0A_U2X0 \ Double the USART transmission speed
+ $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
+&193 constant UCSR0B \ USART Control and Status Register B
+ $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
+ $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
+ $20 constant UCSR0B_UDRIE0 \ USART Data register Empty Interrupt Enable
+ $10 constant UCSR0B_RXEN0 \ Receiver Enable
+ $08 constant UCSR0B_TXEN0 \ Transmitter Enable
+ $04 constant UCSR0B_UCSZ02 \ Character Size
+ $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
+ $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
+&194 constant UCSR0C \ USART Control and Status Register C
+ $40 constant UCSR0C_UMSEL0 \ USART Mode Select
+ $30 constant UCSR0C_UPM0 \ Parity Mode Bits
+ $08 constant UCSR0C_USBS0 \ Stop Bit Select
+ $06 constant UCSR0C_UCSZ0 \ Character Size
+ $01 constant UCSR0C_UCPOL0 \ Clock Polarity
+&196 constant UBRR0 \ USART Baud Rate Register t Bytes
+\ USART1
+&206 constant UDR1 \ USART I/O Data Register
+&200 constant UCSR1A \ USART Control and Status Register A
+ $80 constant UCSR1A_RXC1 \ USART Receive Complete
+ $40 constant UCSR1A_TXC1 \ USART Transmitt Complete
+ $20 constant UCSR1A_UDRE1 \ USART Data Register Empty
+ $10 constant UCSR1A_FE1 \ Framing Error
+ $08 constant UCSR1A_DOR1 \ Data overRun
+ $04 constant UCSR1A_UPE1 \ Parity Error
+ $02 constant UCSR1A_U2X1 \ Double the USART transmission speed
+ $01 constant UCSR1A_MPCM1 \ Multi-processor Communication Mode
+&201 constant UCSR1B \ USART Control and Status Register B
+ $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable
+ $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable
+ $20 constant UCSR1B_UDRIE1 \ USART Data register Empty Interrupt Enable
+ $10 constant UCSR1B_RXEN1 \ Receiver Enable
+ $08 constant UCSR1B_TXEN1 \ Transmitter Enable
+ $04 constant UCSR1B_UCSZ12 \ Character Size
+ $02 constant UCSR1B_RXB81 \ Receive Data Bit 8
+ $01 constant UCSR1B_TXB81 \ Transmit Data Bit 8
+&202 constant UCSR1C \ USART Control and Status Register C
+ $40 constant UCSR1C_UMSEL1 \ USART Mode Select
+ $30 constant UCSR1C_UPM1 \ Parity Mode Bits
+ $08 constant UCSR1C_USBS1 \ Stop Bit Select
+ $06 constant UCSR1C_UCSZ1 \ Character Size
+ $01 constant UCSR1C_UCPOL1 \ Clock Polarity
+&204 constant UBRR1 \ USART Baud Rate Register t Bytes
+\ CPU
+&95 constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ $08 constant SREG_V \ Two's Complement Overflow Flag
+ $04 constant SREG_N \ Negative Flag
+ $02 constant SREG_Z \ Zero Flag
+ $01 constant SREG_C \ Carry Flag
+&93 constant SP \ Stack Pointer
+&116 constant XMCRA \ External Memory Control Register A
+ $80 constant XMCRA_SRE \ External SRAM Enable
+ $70 constant XMCRA_SRL \ Wait state page limit
+ $0C constant XMCRA_SRW1 \ Wait state select bit upper page
+ $03 constant XMCRA_SRW0 \ Wait state select bit lower page
+&117 constant XMCRB \ External Memory Control Register B
+ $80 constant XMCRB_XMBK \ External Memory Bus Keeper Enable
+ $07 constant XMCRB_XMM \ External Memory High Mask
+&102 constant OSCCAL \ Oscillator Calibration Value
+&97 constant CLKPR \ Clock Prescale Register
+ $80 constant CLKPR_CLKPCE \
+ $0F constant CLKPR_CLKPS \
+&83 constant SMCR \ Sleep Mode Control Register
+ $0E constant SMCR_SM \ Sleep Mode Select bits
+ $01 constant SMCR_SE \ Sleep Enable
+&91 constant RAMPZ \ RAM Page Z Select Register - Not used.
+ $01 constant RAMPZ_RAMPZ0 \ RAM Page Z Select Register Bit 0
+&75 constant GPIOR2 \ General Purpose IO Register 2
+ $FF constant GPIOR2_GPIOR \ General Purpose IO Register 2 bis
+&74 constant GPIOR1 \ General Purpose IO Register 1
+ $FF constant GPIOR1_GPIOR \ General Purpose IO Register 1 bis
+&62 constant GPIOR0 \ General Purpose IO Register 0
+ $80 constant GPIOR0_GPIOR07 \ General Purpose IO Register 0 bit 7
+ $40 constant GPIOR0_GPIOR06 \ General Purpose IO Register 0 bit 6
+ $20 constant GPIOR0_GPIOR05 \ General Purpose IO Register 0 bit 5
+ $10 constant GPIOR0_GPIOR04 \ General Purpose IO Register 0 bit 4
+ $08 constant GPIOR0_GPIOR03 \ General Purpose IO Register 0 bit 3
+ $04 constant GPIOR0_GPIOR02 \ General Purpose IO Register 0 bit 2
+ $02 constant GPIOR0_GPIOR01 \ General Purpose IO Register 0 bit 1
+ $01 constant GPIOR0_GPIOR00 \ General Purpose IO Register 0 bit 0
+\ BOOT_LOAD
+&87 constant SPMCSR \ Store Program Memory Control Register
+ $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
+ $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
+ $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
+ $04 constant SPMCSR_PGWRT \ Page Write
+ $02 constant SPMCSR_PGERS \ Page Erase
+ $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
+\ EXTERNAL_INTERRUPT
+&105 constant EICRA \ External Interrupt Control Register A
+ $C0 constant EICRA_ISC3 \ External Interrupt Sense Control Bit
+ $30 constant EICRA_ISC2 \ External Interrupt Sense Control Bit
+ $0C constant EICRA_ISC1 \ External Interrupt Sense Control Bit
+ $03 constant EICRA_ISC0 \ External Interrupt Sense Control Bit
+&106 constant EICRB \ External Interrupt Control Register B
+ $C0 constant EICRB_ISC7 \ External Interrupt 7-4 Sense Control Bit
+ $30 constant EICRB_ISC6 \ External Interrupt 7-4 Sense Control Bit
+ $0C constant EICRB_ISC5 \ External Interrupt 7-4 Sense Control Bit
+ $03 constant EICRB_ISC4 \ External Interrupt 7-4 Sense Control Bit
+&61 constant EIMSK \ External Interrupt Mask Register
+ $FF constant EIMSK_INT \ External Interrupt Request 7 Enable
+&60 constant EIFR \ External Interrupt Flag Register
+ $FF constant EIFR_INTF \ External Interrupt Flags
+\ EEPROM
+&65 constant EEAR \ EEPROM Read/Write Access Bytes - Only bit 10..8 are used in AT90CAN64 - Only bit 9..8 are used in AT90CAN32
+&64 constant EEDR \ EEPROM Data Register
+&63 constant EECR \ EEPROM Control Register
+ $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
+ $04 constant EECR_EEMWE \ EEPROM Master Write Enable
+ $02 constant EECR_EEWE \ EEPROM Write Enable
+ $01 constant EECR_EERE \ EEPROM Read Enable
+\ PORTG
+&52 constant PORTG \ Data Register, Port G
+&51 constant DDRG \ Data Direction Register, Port G
+&50 constant PING \ Input Pins, Port G
+\ TIMER_COUNTER_0
+&68 constant TCCR0A \ Timer/Counter0 Control Register
+ $80 constant TCCR0A_FOC0A \ Force Output Compare
+ $40 constant TCCR0A_WGM00 \ Waveform Generation Mode 0
+ $30 constant TCCR0A_COM0A \ Compare Match Output Modes
+ $08 constant TCCR0A_WGM01 \ Waveform Generation Mode 1
+ $07 constant TCCR0A_CS0 \ Clock Selects
+&70 constant TCNT0 \ Timer/Counter0
+&71 constant OCR0A \ Timer/Counter0 Output Compare Register
+&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
+ $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match Interrupt Enable
+ $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
+&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
+ $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0
+ $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
+&67 constant GTCCR \ General Timer/Control Register
+ $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
+ $01 constant GTCCR_PSR310 \ Prescaler Reset Timer/Counter1 and Timer/Counter0
+\ TIMER_COUNTER_1
+&128 constant TCCR1A \ Timer/Counter1 Control Register A
+ $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
+ $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
+ $0C constant TCCR1A_COM1C \ Compare Output Mode 1C, bits
+ $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
+&129 constant TCCR1B \ Timer/Counter1 Control Register B
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
+ $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
+&130 constant TCCR1C \ Timer/Counter 1 Control Register C
+ $80 constant TCCR1C_FOC1A \ Force Output Compare 1A
+ $40 constant TCCR1C_FOC1B \ Force Output Compare 1B
+ $20 constant TCCR1C_FOC1C \ Force Output Compare 1C
+&132 constant TCNT1 \ Timer/Counter1 Bytes
+&136 constant OCR1A \ Timer/Counter1 Output Compare Register Bytes
+&138 constant OCR1B \ Timer/Counter1 Output Compare Register Bytes
+&140 constant OCR1C \ Timer/Counter1 Output Compare Register Bytes
+&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
+&111 constant TIMSK1 \ Timer/Counter Interrupt Mask Register
+ $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
+ $08 constant TIMSK1_OCIE1C \ Timer/Counter1 Output CompareC Match Interrupt Enable
+ $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output CompareB Match Interrupt Enable
+ $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output CompareA Match Interrupt Enable
+ $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
+&54 constant TIFR1 \ Timer/Counter Interrupt Flag register
+ $20 constant TIFR1_ICF1 \ Input Capture Flag 1
+ $08 constant TIFR1_OCF1C \ Output Compare Flag 1C
+ $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
+ $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
+ $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
+\ TIMER_COUNTER_3
+&144 constant TCCR3A \ Timer/Counter3 Control Register A
+ $C0 constant TCCR3A_COM3A \ Compare Output Mode 3A, bits
+ $30 constant TCCR3A_COM3B \ Compare Output Mode 3B, bits
+ $0C constant TCCR3A_COM3C \ Compare Output Mode 3C, bits
+ $03 constant TCCR3A_WGM3 \ Waveform Generation Mode
+&145 constant TCCR3B \ Timer/Counter3 Control Register B
+ $80 constant TCCR3B_ICNC3 \ Input Capture 3 Noise Canceler
+ $40 constant TCCR3B_ICES3 \ Input Capture 3 Edge Select
+ $18 constant TCCR3B_WGM3 \ Waveform Generation Mode
+ $07 constant TCCR3B_CS3 \ Prescaler source of Timer/Counter 3
+&146 constant TCCR3C \ Timer/Counter 3 Control Register C
+ $80 constant TCCR3C_FOC3A \ Force Output Compare 3A
+ $40 constant TCCR3C_FOC3B \ Force Output Compare 3B
+ $20 constant TCCR3C_FOC3C \ Force Output Compare 3C
+&148 constant TCNT3 \ Timer/Counter3 Bytes
+&152 constant OCR3A \ Timer/Counter3 Output Compare Register Bytes
+&154 constant OCR3B \ Timer/Counter3 Output Compare Register Bytes
+&156 constant OCR3C \ Timer/Counter3 Output Compare Register Bytes
+&150 constant ICR3 \ Timer/Counter3 Input Capture Register Bytes
+&113 constant TIMSK3 \ Timer/Counter Interrupt Mask Register
+ $20 constant TIMSK3_ICIE3 \ Timer/Counter3 Input Capture Interrupt Enable
+ $08 constant TIMSK3_OCIE3C \ Timer/Counter3 Output CompareC Match Interrupt Enable
+ $04 constant TIMSK3_OCIE3B \ Timer/Counter3 Output CompareB Match Interrupt Enable
+ $02 constant TIMSK3_OCIE3A \ Timer/Counter3 Output CompareA Match Interrupt Enable
+ $01 constant TIMSK3_TOIE3 \ Timer/Counter3 Overflow Interrupt Enable
+&56 constant TIFR3 \ Timer/Counter Interrupt Flag register
+ $20 constant TIFR3_ICF3 \ Input Capture Flag 3
+ $08 constant TIFR3_OCF3C \ Output Compare Flag 3C
+ $04 constant TIFR3_OCF3B \ Output Compare Flag 3B
+ $02 constant TIFR3_OCF3A \ Output Compare Flag 3A
+ $01 constant TIFR3_TOV3 \ Timer/Counter3 Overflow Flag
+\ TIMER_COUNTER_2
+&176 constant TCCR2 \ Timer/Counter2 Control Register
+ $80 constant TCCR2_FOC2A \ Force Output Compare
+ $40 constant TCCR2_WGM20 \ Waveform Genration Mode
+ $30 constant TCCR2_COM2A \ Compare Output Mode bits
+ $08 constant TCCR2_WGM21 \ Waveform Generation Mode
+ $07 constant TCCR2_CS2 \ Clock Select bits
+&178 constant TCNT2 \ Timer/Counter2
+&179 constant OCR2A \ Timer/Counter2 Output Compare Register
+&112 constant TIMSK2 \ Timer/Counter Interrupt Mask register
+ $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match Interrupt Enable
+ $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
+&55 constant TIFR2 \ Timer/Counter Interrupt Flag Register
+ $02 constant TIFR2_OCF2A \ Output Compare Flag 2
+ $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
+&182 constant ASSR \ Asynchronous Status Register
+ $10 constant ASSR_EXCLK \ Enable External Clock Interrupt
+ $08 constant ASSR_AS2 \ AS2: Asynchronous Timer/Counter2
+ $04 constant ASSR_TCN2UB \ TCN2UB: Timer/Counter2 Update Busy
+ $02 constant ASSR_OCR2UB \ Output Compare Register2 Update Busy
+ $01 constant ASSR_TCR2UB \ TCR2UB: Timer/Counter Control Register2 Update Busy
+\ WATCHDOG
+&96 constant WDTCR \ Watchdog Timer Control Register
+ $10 constant WDTCR_WDCE \ Watchdog Change Enable
+ $08 constant WDTCR_WDE \ Watch Dog Enable
+ $07 constant WDTCR_WDP \ Watch Dog Timer Prescaler bits
+\ AD_CONVERTER
+&124 constant ADMUX \ The ADC multiplexer Selection Register
+ $C0 constant ADMUX_REFS \ Reference Selection Bits
+ $20 constant ADMUX_ADLAR \ Left Adjust Result
+ $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
+&122 constant ADCSRA \ The ADC Control and Status register
+ $80 constant ADCSRA_ADEN \ ADC Enable
+ $40 constant ADCSRA_ADSC \ ADC Start Conversion
+ $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
+ $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
+ $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
+ $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
+&120 constant ADC \ ADC Data Register Bytes
+&123 constant ADCSRB \ ADC Control and Status Register B
+ $80 constant ADCSRB_ADHSM \ ADC High Speed Mode
+ $07 constant ADCSRB_ADTS \ ADC Auto Trigger Sources
+&126 constant DIDR0 \ Digital Input Disable Register 1
+ $80 constant DIDR0_ADC7D \ ADC7 Digital input Disable
+ $40 constant DIDR0_ADC6D \ ADC6 Digital input Disable
+ $20 constant DIDR0_ADC5D \ ADC5 Digital input Disable
+ $10 constant DIDR0_ADC4D \ ADC4 Digital input Disable
+ $08 constant DIDR0_ADC3D \ ADC3 Digital input Disable
+ $04 constant DIDR0_ADC2D \ ADC2 Digital input Disable
+ $02 constant DIDR0_ADC1D \ ADC1 Digital input Disable
+ $01 constant DIDR0_ADC0D \ ADC0 Digital input Disable
+\ ANALOG_COMPARATOR
+&80 constant ACSR \ Analog Comparator Control And Status Register
+ $80 constant ACSR_ACD \ Analog Comparator Disable
+ $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
+ $20 constant ACSR_ACO \ Analog Compare Output
+ $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
+ $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
+ $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
+ $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
+&127 constant DIDR1 \
+ $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
+ $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
+\ CAN
+&216 constant CANGCON \ CAN General Control Register
+ $80 constant CANGCON_ABRQ \ Abort Request
+ $40 constant CANGCON_OVRQ \ Overload Frame Request
+ $20 constant CANGCON_TTC \ Time Trigger Communication
+ $10 constant CANGCON_SYNTTC \ Synchronization of TTC
+ $08 constant CANGCON_LISTEN \ Listening Mode
+ $04 constant CANGCON_TEST \ Test Mode
+ $02 constant CANGCON_ENASTB \ Enable / Standby
+ $01 constant CANGCON_SWRES \ Software Reset Request
+&217 constant CANGSTA \ CAN General Status Register
+ $40 constant CANGSTA_OVRG \ Overload Frame Flag
+ $10 constant CANGSTA_TXBSY \ Transmitter Busy
+ $08 constant CANGSTA_RXBSY \ Receiver Busy
+ $04 constant CANGSTA_ENFG \ Enable Flag
+ $02 constant CANGSTA_BOFF \ Bus Off Mode
+ $01 constant CANGSTA_ERRP \ Error Passive Mode
+&218 constant CANGIT \ CAN General Interrupt Register
+ $80 constant CANGIT_CANIT \ General Interrupt Flag
+ $40 constant CANGIT_BOFFIT \ Bus Off Interrupt Flag
+ $20 constant CANGIT_OVRTIM \ Overrun CAN Timer
+ $10 constant CANGIT_BXOK \ Burst Receive Interrupt
+ $08 constant CANGIT_SERG \ Stuff Error General
+ $04 constant CANGIT_CERG \ CRC Error General
+ $02 constant CANGIT_FERG \ Form Error General
+ $01 constant CANGIT_AERG \ Ackknowledgement Error General
+&219 constant CANGIE \ CAN General Interrupt Enable Register
+ $80 constant CANGIE_ENIT \ Enable all Interrupts
+ $40 constant CANGIE_ENBOFF \ Enable Bus Off INterrupt
+ $20 constant CANGIE_ENRX \ Enable Receive Interrupt
+ $10 constant CANGIE_ENTX \ Enable Transmitt Interrupt
+ $08 constant CANGIE_ENERR \ Enable MOb Error Interrupt
+ $04 constant CANGIE_ENBX \ Enable Burst Receive Interrupt
+ $02 constant CANGIE_ENERG \ Enable General Error Interrupt
+ $01 constant CANGIE_ENOVRT \ Enable CAN Timer Overrun Interrupt
+&220 constant CANEN2 \ Enable MOb Register
+&221 constant CANEN1 \ Enable MOb Register
+&222 constant CANIE2 \ Enable Interrupt MOb Register
+&223 constant CANIE1 \ Enable Interrupt MOb Register
+&224 constant CANSIT2 \ CAN Status Interrupt MOb Register
+&225 constant CANSIT1 \ CAN Status Interrupt MOb Register
+&226 constant CANBT1 \ Bit Timing Register 1
+ $7E constant CANBT1_BRP \ Baud Rate Prescaler bits
+&227 constant CANBT2 \ Bit Timing Register 2
+ $60 constant CANBT2_SJW \ Re-Sync Jump Width
+ $0E constant CANBT2_PRS \ Propagation Time Segment
+&228 constant CANBT3 \ Bit Timing Register 3
+ $70 constant CANBT3_PHS2 \ Phase Segments
+ $0E constant CANBT3_PHS1 \ Phase Segment 1
+ $01 constant CANBT3_SMP \ Sample Type
+&229 constant CANTCON \ Timer Control Register
+&230 constant CANTIML \ Timer Register Low
+&231 constant CANTIMH \ Timer Register High
+&232 constant CANTTCL \ TTC Timer Register Low
+&233 constant CANTTCH \ TTC Timer Register High
+&234 constant CANTEC \ Transmit Error Counter Register
+&235 constant CANREC \ Receive Error Counter Register
+&236 constant CANHPMOB \ Highest Priority MOb Register
+&237 constant CANPAGE \ Page MOb Register
+ $F0 constant CANPAGE_MOBNB \ MOb Number Bits
+ $08 constant CANPAGE_AINC \ MOb Data Buffer Auto Increment
+ $07 constant CANPAGE_INDX \ Data Buffer Index Bits
+&238 constant CANSTMOB \ MOb Status Register
+ $80 constant CANSTMOB_DLCW \ Data Length Code Warning
+ $40 constant CANSTMOB_TXOK \ Transmit OK
+ $20 constant CANSTMOB_RXOK \ Receive OK
+ $10 constant CANSTMOB_BERR \ Bit Error
+ $08 constant CANSTMOB_SERR \ Stuff Error
+ $04 constant CANSTMOB_CERR \ CRC Error
+ $02 constant CANSTMOB_FERR \ Form Error
+ $01 constant CANSTMOB_AERR \ Ackknowledgement Error
+&239 constant CANCDMOB \ MOb Control and DLC Register
+ $C0 constant CANCDMOB_CONMOB \ MOb Config Bits
+ $20 constant CANCDMOB_RPLV \ Reply Valid
+ $10 constant CANCDMOB_IDE \ Identifier Extension
+ $0F constant CANCDMOB_DLC \ Data Length Code Bits
+&240 constant CANIDT4 \ Identifier Tag Register 4
+&241 constant CANIDT3 \ Identifier Tag Register 3
+&242 constant CANIDT2 \ Identifier Tag Register 2
+&243 constant CANIDT1 \ Identifier Tag Register 1
+&244 constant CANIDM4 \ Identifier Mask Register 4
+&245 constant CANIDM3 \ Identifier Mask Register 3
+&246 constant CANIDM2 \ Identifier Mask Register 2
+&247 constant CANIDM1 \ Identifier Mask Register 1
+&248 constant CANSTML \ Time Stamp Register Low
+&249 constant CANSTMH \ Time Stamp Register High
+&250 constant CANMSG \ Message Data Register
+
+\ Interrupts
+&2 constant INT0Addr \ External Interrupt Request 0
+&4 constant INT1Addr \ External Interrupt Request 1
+&6 constant INT2Addr \ External Interrupt Request 2
+&8 constant INT3Addr \ External Interrupt Request 3
+&10 constant INT4Addr \ External Interrupt Request 4
+&12 constant INT5Addr \ External Interrupt Request 5
+&14 constant INT6Addr \ External Interrupt Request 6
+&16 constant INT7Addr \ External Interrupt Request 7
+&18 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
+&20 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
+&22 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+&24 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
+&26 constant TIMER1_COMPBAddr \ Timer/Counter Compare Match B
+&28 constant TIMER1_COMPCAddr \ Timer/Counter1 Compare Match C
+&30 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+&32 constant TIMER0_COMPAddr \ Timer/Counter0 Compare Match
+&34 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
+&36 constant CANITAddr \ CAN Transfer Complete or Error
+&38 constant OVRITAddr \ CAN Timer Overrun
+&40 constant SPI__STCAddr \ SPI Serial Transfer Complete
+&42 constant USART0__RXAddr \ USART0, Rx Complete
+&44 constant USART0__UDREAddr \ USART0 Data Register Empty
+&46 constant USART0__TXAddr \ USART0, Tx Complete
+&48 constant ANALOG_COMPAddr \ Analog Comparator
+&50 constant ADCAddr \ ADC Conversion Complete
+&52 constant EE_READYAddr \ EEPROM Ready
+&54 constant TIMER3_CAPTAddr \ Timer/Counter3 Capture Event
+&56 constant TIMER3_COMPAAddr \ Timer/Counter3 Compare Match A
+&58 constant TIMER3_COMPBAddr \ Timer/Counter3 Compare Match B
+&60 constant TIMER3_COMPCAddr \ Timer/Counter3 Compare Match C
+&62 constant TIMER3_OVFAddr \ Timer/Counter3 Overflow
+&64 constant USART1__RXAddr \ USART1, Rx Complete
+&66 constant USART1__UDREAddr \ USART1, Data Register Empty
+&68 constant USART1__TXAddr \ USART1, Tx Complete
+&70 constant TWIAddr \ 2-wire Serial Interface
+&72 constant SPM_READYAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/at90can64/device.asm b/amforth-6.5/avr8/devices/at90can64/device.asm
new file mode 100644
index 0000000..abcfaad
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90can64/device.asm
@@ -0,0 +1,139 @@
+; Partname: AT90CAN64
+; generated automatically, do not edit
+
+.nolist
+ .include "can64def.inc"
+.list
+
+.equ ramstart = 256
+.equ CELLSIZE = 2
+.macro readflashcell
+ lsl zl
+ rol zh
+ lpm @0, Z+
+ lpm @1, Z+
+.endmacro
+.macro writeflashcell
+ lsl zl
+ rol zh
+.endmacro
+.set WANT_PORTA = 0
+.set WANT_PORTB = 0
+.set WANT_PORTC = 0
+.set WANT_PORTD = 0
+.set WANT_PORTE = 0
+.set WANT_PORTF = 0
+.set WANT_JTAG = 0
+.set WANT_SPI = 0
+.set WANT_TWI = 0
+.set WANT_USART0 = 0
+.set WANT_USART1 = 0
+.set WANT_CPU = 0
+.set WANT_BOOT_LOAD = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_EEPROM = 0
+.set WANT_PORTG = 0
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_TIMER_COUNTER_3 = 0
+.set WANT_TIMER_COUNTER_2 = 0
+.set WANT_WATCHDOG = 0
+.set WANT_AD_CONVERTER = 0
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_CAN = 0
+.equ intvecsize = 2 ; please verify; flash size: 65536 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.org 2
+ rcall isr ; External Interrupt Request 0
+.org 4
+ rcall isr ; External Interrupt Request 1
+.org 6
+ rcall isr ; External Interrupt Request 2
+.org 8
+ rcall isr ; External Interrupt Request 3
+.org 10
+ rcall isr ; External Interrupt Request 4
+.org 12
+ rcall isr ; External Interrupt Request 5
+.org 14
+ rcall isr ; External Interrupt Request 6
+.org 16
+ rcall isr ; External Interrupt Request 7
+.org 18
+ rcall isr ; Timer/Counter2 Compare Match
+.org 20
+ rcall isr ; Timer/Counter2 Overflow
+.org 22
+ rcall isr ; Timer/Counter1 Capture Event
+.org 24
+ rcall isr ; Timer/Counter1 Compare Match A
+.org 26
+ rcall isr ; Timer/Counter Compare Match B
+.org 28
+ rcall isr ; Timer/Counter1 Compare Match C
+.org 30
+ rcall isr ; Timer/Counter1 Overflow
+.org 32
+ rcall isr ; Timer/Counter0 Compare Match
+.org 34
+ rcall isr ; Timer/Counter0 Overflow
+.org 36
+ rcall isr ; CAN Transfer Complete or Error
+.org 38
+ rcall isr ; CAN Timer Overrun
+.org 40
+ rcall isr ; SPI Serial Transfer Complete
+.org 42
+ rcall isr ; USART0, Rx Complete
+.org 44
+ rcall isr ; USART0 Data Register Empty
+.org 46
+ rcall isr ; USART0, Tx Complete
+.org 48
+ rcall isr ; Analog Comparator
+.org 50
+ rcall isr ; ADC Conversion Complete
+.org 52
+ rcall isr ; EEPROM Ready
+.org 54
+ rcall isr ; Timer/Counter3 Capture Event
+.org 56
+ rcall isr ; Timer/Counter3 Compare Match A
+.org 58
+ rcall isr ; Timer/Counter3 Compare Match B
+.org 60
+ rcall isr ; Timer/Counter3 Compare Match C
+.org 62
+ rcall isr ; Timer/Counter3 Overflow
+.org 64
+ rcall isr ; USART1, Rx Complete
+.org 66
+ rcall isr ; USART1, Data Register Empty
+.org 68
+ rcall isr ; USART1, Tx Complete
+.org 70
+ rcall isr ; 2-wire Serial Interface
+.org 72
+ rcall isr ; Store Program Memory Read
+.equ INTVECTORS = 37
+.nooverlap
+
+; compatability layer (maybe empty)
+.equ EEPE = EEWE
+.equ EEMPE = EEMWE
+
+; controller data area, environment query mcu-info
+mcu_info:
+mcu_ramsize:
+ .dw 4096
+mcu_eepromsize:
+ .dw 2048
+mcu_maxdp:
+ .dw 57344
+mcu_numints:
+ .dw 37
+mcu_name:
+ .dw 9
+ .db "AT90CAN64",0
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/at90can64/device.inc b/amforth-6.5/avr8/devices/at90can64/device.inc
new file mode 100644
index 0000000..24b3493
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90can64/device.inc
@@ -0,0 +1,1707 @@
+; Partname: AT90CAN64
+; generated automatically, no not edit
+
+.if WANT_PORTA == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Register
+VE_PORTA:
+ .dw $ff05
+ .db "PORTA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTA
+XT_PORTA:
+ .dw PFA_DOVARIABLE
+PFA_PORTA:
+ .dw 34
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Direction Register
+VE_DDRA:
+ .dw $ff04
+ .db "DDRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRA
+XT_DDRA:
+ .dw PFA_DOVARIABLE
+PFA_DDRA:
+ .dw 33
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Input Pins
+VE_PINA:
+ .dw $ff04
+ .db "PINA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINA
+XT_PINA:
+ .dw PFA_DOVARIABLE
+PFA_PINA:
+ .dw 32
+
+.endif
+.if WANT_PORTB == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw 37
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw 36
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw 35
+
+.endif
+.if WANT_PORTC == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Register
+VE_PORTC:
+ .dw $ff05
+ .db "PORTC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTC
+XT_PORTC:
+ .dw PFA_DOVARIABLE
+PFA_PORTC:
+ .dw 40
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Direction Register
+VE_DDRC:
+ .dw $ff04
+ .db "DDRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRC
+XT_DDRC:
+ .dw PFA_DOVARIABLE
+PFA_DDRC:
+ .dw 39
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Input Pins
+VE_PINC:
+ .dw $ff04
+ .db "PINC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINC
+XT_PINC:
+ .dw PFA_DOVARIABLE
+PFA_PINC:
+ .dw 38
+
+.endif
+.if WANT_PORTD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw 43
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw 42
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw 41
+
+.endif
+.if WANT_PORTE == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port E
+VE_PORTE:
+ .dw $ff05
+ .db "PORTE",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTE
+XT_PORTE:
+ .dw PFA_DOVARIABLE
+PFA_PORTE:
+ .dw 46
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port E
+VE_DDRE:
+ .dw $ff04
+ .db "DDRE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRE
+XT_DDRE:
+ .dw PFA_DOVARIABLE
+PFA_DDRE:
+ .dw 45
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port E
+VE_PINE:
+ .dw $ff04
+ .db "PINE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINE
+XT_PINE:
+ .dw PFA_DOVARIABLE
+PFA_PINE:
+ .dw 44
+
+.endif
+.if WANT_PORTF == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port F
+VE_PORTF:
+ .dw $ff05
+ .db "PORTF",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTF
+XT_PORTF:
+ .dw PFA_DOVARIABLE
+PFA_PORTF:
+ .dw 49
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port F
+VE_DDRF:
+ .dw $ff04
+ .db "DDRF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRF
+XT_DDRF:
+ .dw PFA_DOVARIABLE
+PFA_DDRF:
+ .dw 48
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port F
+VE_PINF:
+ .dw $ff04
+ .db "PINF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINF
+XT_PINF:
+ .dw PFA_DOVARIABLE
+PFA_PINF:
+ .dw 47
+
+.endif
+.if WANT_JTAG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; On-Chip Debug Related Register in I/O Memory
+VE_OCDR:
+ .dw $ff04
+ .db "OCDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCDR
+XT_OCDR:
+ .dw PFA_DOVARIABLE
+PFA_OCDR:
+ .dw 81
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw 85
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Status Register
+VE_MCUSR:
+ .dw $ff05
+ .db "MCUSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUSR
+XT_MCUSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUSR:
+ .dw 84
+
+.endif
+.if WANT_SPI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR:
+ .dw $ff04
+ .db "SPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR
+XT_SPCR:
+ .dw PFA_DOVARIABLE
+PFA_SPCR:
+ .dw 76
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR:
+ .dw $ff04
+ .db "SPSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR
+XT_SPSR:
+ .dw PFA_DOVARIABLE
+PFA_SPSR:
+ .dw 77
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR:
+ .dw $ff04
+ .db "SPDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR
+XT_SPDR:
+ .dw PFA_DOVARIABLE
+PFA_SPDR:
+ .dw 78
+
+.endif
+.if WANT_TWI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Bit Rate register
+VE_TWBR:
+ .dw $ff04
+ .db "TWBR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWBR
+XT_TWBR:
+ .dw PFA_DOVARIABLE
+PFA_TWBR:
+ .dw 184
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Control Register
+VE_TWCR:
+ .dw $ff04
+ .db "TWCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWCR
+XT_TWCR:
+ .dw PFA_DOVARIABLE
+PFA_TWCR:
+ .dw 188
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Status Register
+VE_TWSR:
+ .dw $ff04
+ .db "TWSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWSR
+XT_TWSR:
+ .dw PFA_DOVARIABLE
+PFA_TWSR:
+ .dw 185
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Data register
+VE_TWDR:
+ .dw $ff04
+ .db "TWDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWDR
+XT_TWDR:
+ .dw PFA_DOVARIABLE
+PFA_TWDR:
+ .dw 187
+; ( -- addr ) System Constant
+; R( -- )
+; TWI (Slave) Address register
+VE_TWAR:
+ .dw $ff04
+ .db "TWAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWAR
+XT_TWAR:
+ .dw PFA_DOVARIABLE
+PFA_TWAR:
+ .dw 186
+
+.endif
+.if WANT_USART0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR0:
+ .dw $ff04
+ .db "UDR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR0
+XT_UDR0:
+ .dw PFA_DOVARIABLE
+PFA_UDR0:
+ .dw 198
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR0A:
+ .dw $ff06
+ .db "UCSR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0A
+XT_UCSR0A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0A:
+ .dw 192
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR0B:
+ .dw $ff06
+ .db "UCSR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0B
+XT_UCSR0B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0B:
+ .dw 193
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR0C:
+ .dw $ff06
+ .db "UCSR0C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0C
+XT_UCSR0C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0C:
+ .dw 194
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register t Bytes
+VE_UBRR0:
+ .dw $ff05
+ .db "UBRR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR0
+XT_UBRR0:
+ .dw PFA_DOVARIABLE
+PFA_UBRR0:
+ .dw 196
+
+.endif
+.if WANT_USART1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR1:
+ .dw $ff04
+ .db "UDR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR1
+XT_UDR1:
+ .dw PFA_DOVARIABLE
+PFA_UDR1:
+ .dw 206
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR1A:
+ .dw $ff06
+ .db "UCSR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1A
+XT_UCSR1A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1A:
+ .dw 200
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR1B:
+ .dw $ff06
+ .db "UCSR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1B
+XT_UCSR1B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1B:
+ .dw 201
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR1C:
+ .dw $ff06
+ .db "UCSR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1C
+XT_UCSR1C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1C:
+ .dw 202
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register t Bytes
+VE_UBRR1:
+ .dw $ff05
+ .db "UBRR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR1
+XT_UBRR1:
+ .dw PFA_DOVARIABLE
+PFA_UBRR1:
+ .dw 204
+
+.endif
+.if WANT_CPU == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw 95
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer
+VE_SP:
+ .dw $ff02
+ .db "SP"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SP
+XT_SP:
+ .dw PFA_DOVARIABLE
+PFA_SP:
+ .dw 93
+; ( -- addr ) System Constant
+; R( -- )
+; External Memory Control Register A
+VE_XMCRA:
+ .dw $ff05
+ .db "XMCRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_XMCRA
+XT_XMCRA:
+ .dw PFA_DOVARIABLE
+PFA_XMCRA:
+ .dw 116
+; ( -- addr ) System Constant
+; R( -- )
+; External Memory Control Register B
+VE_XMCRB:
+ .dw $ff05
+ .db "XMCRB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_XMCRB
+XT_XMCRB:
+ .dw PFA_DOVARIABLE
+PFA_XMCRB:
+ .dw 117
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Calibration Value
+VE_OSCCAL:
+ .dw $ff06
+ .db "OSCCAL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSCCAL
+XT_OSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_OSCCAL:
+ .dw 102
+; ( -- addr ) System Constant
+; R( -- )
+; Clock Prescale Register
+VE_CLKPR:
+ .dw $ff05
+ .db "CLKPR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKPR
+XT_CLKPR:
+ .dw PFA_DOVARIABLE
+PFA_CLKPR:
+ .dw 97
+; ( -- addr ) System Constant
+; R( -- )
+; Sleep Mode Control Register
+VE_SMCR:
+ .dw $ff04
+ .db "SMCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SMCR
+XT_SMCR:
+ .dw PFA_DOVARIABLE
+PFA_SMCR:
+ .dw 83
+; ( -- addr ) System Constant
+; R( -- )
+; RAM Page Z Select Register - Not used.
+VE_RAMPZ:
+ .dw $ff05
+ .db "RAMPZ",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_RAMPZ
+XT_RAMPZ:
+ .dw PFA_DOVARIABLE
+PFA_RAMPZ:
+ .dw 91
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 2
+VE_GPIOR2:
+ .dw $ff06
+ .db "GPIOR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR2
+XT_GPIOR2:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR2:
+ .dw 75
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 1
+VE_GPIOR1:
+ .dw $ff06
+ .db "GPIOR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR1
+XT_GPIOR1:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR1:
+ .dw 74
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 0
+VE_GPIOR0:
+ .dw $ff06
+ .db "GPIOR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR0
+XT_GPIOR0:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR0:
+ .dw 62
+
+.endif
+.if WANT_BOOT_LOAD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control Register
+VE_SPMCSR:
+ .dw $ff06
+ .db "SPMCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCSR
+XT_SPMCSR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCSR:
+ .dw 87
+
+.endif
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register A
+VE_EICRA:
+ .dw $ff05
+ .db "EICRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRA
+XT_EICRA:
+ .dw PFA_DOVARIABLE
+PFA_EICRA:
+ .dw 105
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register B
+VE_EICRB:
+ .dw $ff05
+ .db "EICRB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRB
+XT_EICRB:
+ .dw PFA_DOVARIABLE
+PFA_EICRB:
+ .dw 106
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Mask Register
+VE_EIMSK:
+ .dw $ff05
+ .db "EIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIMSK
+XT_EIMSK:
+ .dw PFA_DOVARIABLE
+PFA_EIMSK:
+ .dw 61
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Flag Register
+VE_EIFR:
+ .dw $ff04
+ .db "EIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIFR
+XT_EIFR:
+ .dw PFA_DOVARIABLE
+PFA_EIFR:
+ .dw 60
+
+.endif
+.if WANT_EEPROM == 1
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Read/Write Access Bytes - Only bit 10..8 are used in AT90CAN64 - Only bit 9..8 are used in AT90CAN32
+VE_EEAR:
+ .dw $ff04
+ .db "EEAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEAR
+XT_EEAR:
+ .dw PFA_DOVARIABLE
+PFA_EEAR:
+ .dw 65
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw 64
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw 63
+
+.endif
+.if WANT_PORTG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port G
+VE_PORTG:
+ .dw $ff05
+ .db "PORTG",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTG
+XT_PORTG:
+ .dw PFA_DOVARIABLE
+PFA_PORTG:
+ .dw 52
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port G
+VE_DDRG:
+ .dw $ff04
+ .db "DDRG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRG
+XT_DDRG:
+ .dw PFA_DOVARIABLE
+PFA_DDRG:
+ .dw 51
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port G
+VE_PING:
+ .dw $ff04
+ .db "PING"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PING
+XT_PING:
+ .dw PFA_DOVARIABLE
+PFA_PING:
+ .dw 50
+
+.endif
+.if WANT_TIMER_COUNTER_0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Control Register
+VE_TCCR0A:
+ .dw $ff06
+ .db "TCCR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0A
+XT_TCCR0A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0A:
+ .dw 68
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw 70
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0A:
+ .dw $ff05
+ .db "OCR0A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0A
+XT_OCR0A:
+ .dw PFA_DOVARIABLE
+PFA_OCR0A:
+ .dw 71
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Mask Register
+VE_TIMSK0:
+ .dw $ff06
+ .db "TIMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK0
+XT_TIMSK0:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK0:
+ .dw 110
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Flag register
+VE_TIFR0:
+ .dw $ff05
+ .db "TIFR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR0
+XT_TIFR0:
+ .dw PFA_DOVARIABLE
+PFA_TIFR0:
+ .dw 53
+; ( -- addr ) System Constant
+; R( -- )
+; General Timer/Control Register
+VE_GTCCR:
+ .dw $ff05
+ .db "GTCCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GTCCR
+XT_GTCCR:
+ .dw PFA_DOVARIABLE
+PFA_GTCCR:
+ .dw 67
+
+.endif
+.if WANT_TIMER_COUNTER_1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw 128
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw 129
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter 1 Control Register C
+VE_TCCR1C:
+ .dw $ff06
+ .db "TCCR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1C
+XT_TCCR1C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1C:
+ .dw 130
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Bytes
+VE_TCNT1:
+ .dw $ff05
+ .db "TCNT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1
+XT_TCNT1:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1:
+ .dw 132
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register Bytes
+VE_OCR1A:
+ .dw $ff05
+ .db "OCR1A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1A
+XT_OCR1A:
+ .dw PFA_DOVARIABLE
+PFA_OCR1A:
+ .dw 136
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register Bytes
+VE_OCR1B:
+ .dw $ff05
+ .db "OCR1B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1B
+XT_OCR1B:
+ .dw PFA_DOVARIABLE
+PFA_OCR1B:
+ .dw 138
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register Bytes
+VE_OCR1C:
+ .dw $ff05
+ .db "OCR1C",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1C
+XT_OCR1C:
+ .dw PFA_DOVARIABLE
+PFA_OCR1C:
+ .dw 140
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Bytes
+VE_ICR1:
+ .dw $ff04
+ .db "ICR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1
+XT_ICR1:
+ .dw PFA_DOVARIABLE
+PFA_ICR1:
+ .dw 134
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Mask Register
+VE_TIMSK1:
+ .dw $ff06
+ .db "TIMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK1
+XT_TIMSK1:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK1:
+ .dw 111
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Flag register
+VE_TIFR1:
+ .dw $ff05
+ .db "TIFR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR1
+XT_TIFR1:
+ .dw PFA_DOVARIABLE
+PFA_TIFR1:
+ .dw 54
+
+.endif
+.if WANT_TIMER_COUNTER_3 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Control Register A
+VE_TCCR3A:
+ .dw $ff06
+ .db "TCCR3A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR3A
+XT_TCCR3A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR3A:
+ .dw 144
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Control Register B
+VE_TCCR3B:
+ .dw $ff06
+ .db "TCCR3B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR3B
+XT_TCCR3B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR3B:
+ .dw 145
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter 3 Control Register C
+VE_TCCR3C:
+ .dw $ff06
+ .db "TCCR3C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR3C
+XT_TCCR3C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR3C:
+ .dw 146
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Bytes
+VE_TCNT3:
+ .dw $ff05
+ .db "TCNT3",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT3
+XT_TCNT3:
+ .dw PFA_DOVARIABLE
+PFA_TCNT3:
+ .dw 148
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Output Compare Register Bytes
+VE_OCR3A:
+ .dw $ff05
+ .db "OCR3A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR3A
+XT_OCR3A:
+ .dw PFA_DOVARIABLE
+PFA_OCR3A:
+ .dw 152
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Output Compare Register Bytes
+VE_OCR3B:
+ .dw $ff05
+ .db "OCR3B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR3B
+XT_OCR3B:
+ .dw PFA_DOVARIABLE
+PFA_OCR3B:
+ .dw 154
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Output Compare Register Bytes
+VE_OCR3C:
+ .dw $ff05
+ .db "OCR3C",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR3C
+XT_OCR3C:
+ .dw PFA_DOVARIABLE
+PFA_OCR3C:
+ .dw 156
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Input Capture Register Bytes
+VE_ICR3:
+ .dw $ff04
+ .db "ICR3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR3
+XT_ICR3:
+ .dw PFA_DOVARIABLE
+PFA_ICR3:
+ .dw 150
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Mask Register
+VE_TIMSK3:
+ .dw $ff06
+ .db "TIMSK3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK3
+XT_TIMSK3:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK3:
+ .dw 113
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Flag register
+VE_TIFR3:
+ .dw $ff05
+ .db "TIFR3",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR3
+XT_TIFR3:
+ .dw PFA_DOVARIABLE
+PFA_TIFR3:
+ .dw 56
+
+.endif
+.if WANT_TIMER_COUNTER_2 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register
+VE_TCCR2:
+ .dw $ff05
+ .db "TCCR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2
+XT_TCCR2:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2:
+ .dw 176
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2
+VE_TCNT2:
+ .dw $ff05
+ .db "TCNT2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT2
+XT_TCNT2:
+ .dw PFA_DOVARIABLE
+PFA_TCNT2:
+ .dw 178
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register
+VE_OCR2A:
+ .dw $ff05
+ .db "OCR2A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2A
+XT_OCR2A:
+ .dw PFA_DOVARIABLE
+PFA_OCR2A:
+ .dw 179
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Mask register
+VE_TIMSK2:
+ .dw $ff06
+ .db "TIMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK2
+XT_TIMSK2:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK2:
+ .dw 112
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Flag Register
+VE_TIFR2:
+ .dw $ff05
+ .db "TIFR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR2
+XT_TIFR2:
+ .dw PFA_DOVARIABLE
+PFA_TIFR2:
+ .dw 55
+; ( -- addr ) System Constant
+; R( -- )
+; Asynchronous Status Register
+VE_ASSR:
+ .dw $ff04
+ .db "ASSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ASSR
+XT_ASSR:
+ .dw PFA_DOVARIABLE
+PFA_ASSR:
+ .dw 182
+
+.endif
+.if WANT_WATCHDOG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCR:
+ .dw $ff05
+ .db "WDTCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCR
+XT_WDTCR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCR:
+ .dw 96
+
+.endif
+.if WANT_AD_CONVERTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC multiplexer Selection Register
+VE_ADMUX:
+ .dw $ff05
+ .db "ADMUX",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADMUX
+XT_ADMUX:
+ .dw PFA_DOVARIABLE
+PFA_ADMUX:
+ .dw 124
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register
+VE_ADCSRA:
+ .dw $ff06
+ .db "ADCSRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRA
+XT_ADCSRA:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRA:
+ .dw 122
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register Bytes
+VE_ADC:
+ .dw $ff03
+ .db "ADC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADC
+XT_ADC:
+ .dw PFA_DOVARIABLE
+PFA_ADC:
+ .dw 120
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Control and Status Register B
+VE_ADCSRB:
+ .dw $ff06
+ .db "ADCSRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRB
+XT_ADCSRB:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRB:
+ .dw 123
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 1
+VE_DIDR0:
+ .dw $ff05
+ .db "DIDR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR0
+XT_DIDR0:
+ .dw PFA_DOVARIABLE
+PFA_DIDR0:
+ .dw 126
+
+.endif
+.if WANT_ANALOG_COMPARATOR == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Control And Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw 80
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_DIDR1:
+ .dw $ff05
+ .db "DIDR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR1
+XT_DIDR1:
+ .dw PFA_DOVARIABLE
+PFA_DIDR1:
+ .dw 127
+
+.endif
+.if WANT_CAN == 1
+; ( -- addr ) System Constant
+; R( -- )
+; CAN General Control Register
+VE_CANGCON:
+ .dw $ff07
+ .db "CANGCON",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANGCON
+XT_CANGCON:
+ .dw PFA_DOVARIABLE
+PFA_CANGCON:
+ .dw 216
+; ( -- addr ) System Constant
+; R( -- )
+; CAN General Status Register
+VE_CANGSTA:
+ .dw $ff07
+ .db "CANGSTA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANGSTA
+XT_CANGSTA:
+ .dw PFA_DOVARIABLE
+PFA_CANGSTA:
+ .dw 217
+; ( -- addr ) System Constant
+; R( -- )
+; CAN General Interrupt Register
+VE_CANGIT:
+ .dw $ff06
+ .db "CANGIT"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANGIT
+XT_CANGIT:
+ .dw PFA_DOVARIABLE
+PFA_CANGIT:
+ .dw 218
+; ( -- addr ) System Constant
+; R( -- )
+; CAN General Interrupt Enable Register
+VE_CANGIE:
+ .dw $ff06
+ .db "CANGIE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANGIE
+XT_CANGIE:
+ .dw PFA_DOVARIABLE
+PFA_CANGIE:
+ .dw 219
+; ( -- addr ) System Constant
+; R( -- )
+; Enable MOb Register
+VE_CANEN2:
+ .dw $ff06
+ .db "CANEN2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANEN2
+XT_CANEN2:
+ .dw PFA_DOVARIABLE
+PFA_CANEN2:
+ .dw 220
+; ( -- addr ) System Constant
+; R( -- )
+; Enable MOb Register
+VE_CANEN1:
+ .dw $ff06
+ .db "CANEN1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANEN1
+XT_CANEN1:
+ .dw PFA_DOVARIABLE
+PFA_CANEN1:
+ .dw 221
+; ( -- addr ) System Constant
+; R( -- )
+; Enable Interrupt MOb Register
+VE_CANIE2:
+ .dw $ff06
+ .db "CANIE2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANIE2
+XT_CANIE2:
+ .dw PFA_DOVARIABLE
+PFA_CANIE2:
+ .dw 222
+; ( -- addr ) System Constant
+; R( -- )
+; Enable Interrupt MOb Register
+VE_CANIE1:
+ .dw $ff06
+ .db "CANIE1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANIE1
+XT_CANIE1:
+ .dw PFA_DOVARIABLE
+PFA_CANIE1:
+ .dw 223
+; ( -- addr ) System Constant
+; R( -- )
+; CAN Status Interrupt MOb Register
+VE_CANSIT2:
+ .dw $ff07
+ .db "CANSIT2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANSIT2
+XT_CANSIT2:
+ .dw PFA_DOVARIABLE
+PFA_CANSIT2:
+ .dw 224
+; ( -- addr ) System Constant
+; R( -- )
+; CAN Status Interrupt MOb Register
+VE_CANSIT1:
+ .dw $ff07
+ .db "CANSIT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANSIT1
+XT_CANSIT1:
+ .dw PFA_DOVARIABLE
+PFA_CANSIT1:
+ .dw 225
+; ( -- addr ) System Constant
+; R( -- )
+; Bit Timing Register 1
+VE_CANBT1:
+ .dw $ff06
+ .db "CANBT1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANBT1
+XT_CANBT1:
+ .dw PFA_DOVARIABLE
+PFA_CANBT1:
+ .dw 226
+; ( -- addr ) System Constant
+; R( -- )
+; Bit Timing Register 2
+VE_CANBT2:
+ .dw $ff06
+ .db "CANBT2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANBT2
+XT_CANBT2:
+ .dw PFA_DOVARIABLE
+PFA_CANBT2:
+ .dw 227
+; ( -- addr ) System Constant
+; R( -- )
+; Bit Timing Register 3
+VE_CANBT3:
+ .dw $ff06
+ .db "CANBT3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANBT3
+XT_CANBT3:
+ .dw PFA_DOVARIABLE
+PFA_CANBT3:
+ .dw 228
+; ( -- addr ) System Constant
+; R( -- )
+; Timer Control Register
+VE_CANTCON:
+ .dw $ff07
+ .db "CANTCON",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANTCON
+XT_CANTCON:
+ .dw PFA_DOVARIABLE
+PFA_CANTCON:
+ .dw 229
+; ( -- addr ) System Constant
+; R( -- )
+; Timer Register Low
+VE_CANTIML:
+ .dw $ff07
+ .db "CANTIML",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANTIML
+XT_CANTIML:
+ .dw PFA_DOVARIABLE
+PFA_CANTIML:
+ .dw 230
+; ( -- addr ) System Constant
+; R( -- )
+; Timer Register High
+VE_CANTIMH:
+ .dw $ff07
+ .db "CANTIMH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANTIMH
+XT_CANTIMH:
+ .dw PFA_DOVARIABLE
+PFA_CANTIMH:
+ .dw 231
+; ( -- addr ) System Constant
+; R( -- )
+; TTC Timer Register Low
+VE_CANTTCL:
+ .dw $ff07
+ .db "CANTTCL",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANTTCL
+XT_CANTTCL:
+ .dw PFA_DOVARIABLE
+PFA_CANTTCL:
+ .dw 232
+; ( -- addr ) System Constant
+; R( -- )
+; TTC Timer Register High
+VE_CANTTCH:
+ .dw $ff07
+ .db "CANTTCH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANTTCH
+XT_CANTTCH:
+ .dw PFA_DOVARIABLE
+PFA_CANTTCH:
+ .dw 233
+; ( -- addr ) System Constant
+; R( -- )
+; Transmit Error Counter Register
+VE_CANTEC:
+ .dw $ff06
+ .db "CANTEC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANTEC
+XT_CANTEC:
+ .dw PFA_DOVARIABLE
+PFA_CANTEC:
+ .dw 234
+; ( -- addr ) System Constant
+; R( -- )
+; Receive Error Counter Register
+VE_CANREC:
+ .dw $ff06
+ .db "CANREC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANREC
+XT_CANREC:
+ .dw PFA_DOVARIABLE
+PFA_CANREC:
+ .dw 235
+; ( -- addr ) System Constant
+; R( -- )
+; Highest Priority MOb Register
+VE_CANHPMOB:
+ .dw $ff08
+ .db "CANHPMOB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANHPMOB
+XT_CANHPMOB:
+ .dw PFA_DOVARIABLE
+PFA_CANHPMOB:
+ .dw 236
+; ( -- addr ) System Constant
+; R( -- )
+; Page MOb Register
+VE_CANPAGE:
+ .dw $ff07
+ .db "CANPAGE",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANPAGE
+XT_CANPAGE:
+ .dw PFA_DOVARIABLE
+PFA_CANPAGE:
+ .dw 237
+; ( -- addr ) System Constant
+; R( -- )
+; MOb Status Register
+VE_CANSTMOB:
+ .dw $ff08
+ .db "CANSTMOB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANSTMOB
+XT_CANSTMOB:
+ .dw PFA_DOVARIABLE
+PFA_CANSTMOB:
+ .dw 238
+; ( -- addr ) System Constant
+; R( -- )
+; MOb Control and DLC Register
+VE_CANCDMOB:
+ .dw $ff08
+ .db "CANCDMOB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANCDMOB
+XT_CANCDMOB:
+ .dw PFA_DOVARIABLE
+PFA_CANCDMOB:
+ .dw 239
+; ( -- addr ) System Constant
+; R( -- )
+; Identifier Tag Register 4
+VE_CANIDT4:
+ .dw $ff07
+ .db "CANIDT4",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANIDT4
+XT_CANIDT4:
+ .dw PFA_DOVARIABLE
+PFA_CANIDT4:
+ .dw 240
+; ( -- addr ) System Constant
+; R( -- )
+; Identifier Tag Register 3
+VE_CANIDT3:
+ .dw $ff07
+ .db "CANIDT3",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANIDT3
+XT_CANIDT3:
+ .dw PFA_DOVARIABLE
+PFA_CANIDT3:
+ .dw 241
+; ( -- addr ) System Constant
+; R( -- )
+; Identifier Tag Register 2
+VE_CANIDT2:
+ .dw $ff07
+ .db "CANIDT2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANIDT2
+XT_CANIDT2:
+ .dw PFA_DOVARIABLE
+PFA_CANIDT2:
+ .dw 242
+; ( -- addr ) System Constant
+; R( -- )
+; Identifier Tag Register 1
+VE_CANIDT1:
+ .dw $ff07
+ .db "CANIDT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANIDT1
+XT_CANIDT1:
+ .dw PFA_DOVARIABLE
+PFA_CANIDT1:
+ .dw 243
+; ( -- addr ) System Constant
+; R( -- )
+; Identifier Mask Register 4
+VE_CANIDM4:
+ .dw $ff07
+ .db "CANIDM4",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANIDM4
+XT_CANIDM4:
+ .dw PFA_DOVARIABLE
+PFA_CANIDM4:
+ .dw 244
+; ( -- addr ) System Constant
+; R( -- )
+; Identifier Mask Register 3
+VE_CANIDM3:
+ .dw $ff07
+ .db "CANIDM3",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANIDM3
+XT_CANIDM3:
+ .dw PFA_DOVARIABLE
+PFA_CANIDM3:
+ .dw 245
+; ( -- addr ) System Constant
+; R( -- )
+; Identifier Mask Register 2
+VE_CANIDM2:
+ .dw $ff07
+ .db "CANIDM2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANIDM2
+XT_CANIDM2:
+ .dw PFA_DOVARIABLE
+PFA_CANIDM2:
+ .dw 246
+; ( -- addr ) System Constant
+; R( -- )
+; Identifier Mask Register 1
+VE_CANIDM1:
+ .dw $ff07
+ .db "CANIDM1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANIDM1
+XT_CANIDM1:
+ .dw PFA_DOVARIABLE
+PFA_CANIDM1:
+ .dw 247
+; ( -- addr ) System Constant
+; R( -- )
+; Time Stamp Register Low
+VE_CANSTML:
+ .dw $ff07
+ .db "CANSTML",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANSTML
+XT_CANSTML:
+ .dw PFA_DOVARIABLE
+PFA_CANSTML:
+ .dw 248
+; ( -- addr ) System Constant
+; R( -- )
+; Time Stamp Register High
+VE_CANSTMH:
+ .dw $ff07
+ .db "CANSTMH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANSTMH
+XT_CANSTMH:
+ .dw PFA_DOVARIABLE
+PFA_CANSTMH:
+ .dw 249
+; ( -- addr ) System Constant
+; R( -- )
+; Message Data Register
+VE_CANMSG:
+ .dw $ff06
+ .db "CANMSG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANMSG
+XT_CANMSG:
+ .dw PFA_DOVARIABLE
+PFA_CANMSG:
+ .dw 250
+
+.endif
diff --git a/amforth-6.5/avr8/devices/at90can64/device.py b/amforth-6.5/avr8/devices/at90can64/device.py
new file mode 100644
index 0000000..3de7034
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90can64/device.py
@@ -0,0 +1,507 @@
+# Generated Automatically
+
+# Partname AT90CAN64
+
+MCUREGS = {
+# Interrupt Vectors
+ 'INT0Addr' : '#2', # External Interrupt Request 0
+ 'INT1Addr' : '#4', # External Interrupt Request 1
+ 'INT2Addr' : '#6', # External Interrupt Request 2
+ 'INT3Addr' : '#8', # External Interrupt Request 3
+ 'INT4Addr' : '#10', # External Interrupt Request 4
+ 'INT5Addr' : '#12', # External Interrupt Request 5
+ 'INT6Addr' : '#14', # External Interrupt Request 6
+ 'INT7Addr' : '#16', # External Interrupt Request 7
+ 'TIMER2_COMPAddr' : '#18', # Timer/Counter2 Compare Match
+ 'TIMER2_OVFAddr' : '#20', # Timer/Counter2 Overflow
+ 'TIMER1_CAPTAddr' : '#22', # Timer/Counter1 Capture Event
+ 'TIMER1_COMPAAddr' : '#24', # Timer/Counter1 Compare Match A
+ 'TIMER1_COMPBAddr' : '#26', # Timer/Counter Compare Match B
+ 'TIMER1_COMPCAddr' : '#28', # Timer/Counter1 Compare Match C
+ 'TIMER1_OVFAddr' : '#30', # Timer/Counter1 Overflow
+ 'TIMER0_COMPAddr' : '#32', # Timer/Counter0 Compare Match
+ 'TIMER0_OVFAddr' : '#34', # Timer/Counter0 Overflow
+ 'CANITAddr' : '#36', # CAN Transfer Complete or Error
+ 'OVRITAddr' : '#38', # CAN Timer Overrun
+ 'SPI_STCAddr' : '#40', # SPI Serial Transfer Complete
+ 'USART0_RXAddr' : '#42', # USART0, Rx Complete
+ 'USART0_UDREAddr' : '#44', # USART0 Data Register Empty
+ 'USART0_TXAddr' : '#46', # USART0, Tx Complete
+ 'ANALOG_COMPAddr' : '#48', # Analog Comparator
+ 'ADCAddr' : '#50', # ADC Conversion Complete
+ 'EE_READYAddr' : '#52', # EEPROM Ready
+ 'TIMER3_CAPTAddr' : '#54', # Timer/Counter3 Capture Event
+ 'TIMER3_COMPAAddr' : '#56', # Timer/Counter3 Compare Match A
+ 'TIMER3_COMPBAddr' : '#58', # Timer/Counter3 Compare Match B
+ 'TIMER3_COMPCAddr' : '#60', # Timer/Counter3 Compare Match C
+ 'TIMER3_OVFAddr' : '#62', # Timer/Counter3 Overflow
+ 'USART1_RXAddr' : '#64', # USART1, Rx Complete
+ 'USART1_UDREAddr' : '#66', # USART1, Data Register Empty
+ 'USART1_TXAddr' : '#68', # USART1, Tx Complete
+ 'TWIAddr' : '#70', # 2-wire Serial Interface
+ 'SPM_READYAddr' : '#72', # Store Program Memory Read
+
+# Module PORTA
+ 'PORTA' : '$22', # Port A Data Register
+ 'DDRA' : '$21', # Port A Data Direction Register
+ 'PINA' : '$20', # Port A Input Pins
+
+# Module PORTB
+ 'PORTB' : '$25', # Port B Data Register
+ 'DDRB' : '$24', # Port B Data Direction Register
+ 'PINB' : '$23', # Port B Input Pins
+
+# Module PORTC
+ 'PORTC' : '$28', # Port C Data Register
+ 'DDRC' : '$27', # Port C Data Direction Register
+ 'PINC' : '$26', # Port C Input Pins
+
+# Module PORTD
+ 'PORTD' : '$2b', # Port D Data Register
+ 'DDRD' : '$2a', # Port D Data Direction Register
+ 'PIND' : '$29', # Port D Input Pins
+
+# Module PORTE
+ 'PORTE' : '$2e', # Data Register, Port E
+ 'DDRE' : '$2d', # Data Direction Register, Port
+ 'PINE' : '$2c', # Input Pins, Port E
+
+# Module PORTF
+ 'PORTF' : '$31', # Data Register, Port F
+ 'DDRF' : '$30', # Data Direction Register, Port
+ 'PINF' : '$2f', # Input Pins, Port F
+
+# Module JTAG
+ 'OCDR' : '$51', # On-Chip Debug Related Register
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_JTD': '$80', # JTAG Interface Disable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+
+# Module SPI
+ 'SPCR' : '$4c', # SPI Control Register
+ 'SPCR_SPIE': '$80', # SPI Interrupt Enable
+ 'SPCR_SPE': '$40', # SPI Enable
+ 'SPCR_DORD': '$20', # Data Order
+ 'SPCR_MSTR': '$10', # Master/Slave Select
+ 'SPCR_CPOL': '$8', # Clock polarity
+ 'SPCR_CPHA': '$4', # Clock Phase
+ 'SPCR_SPR': '$3', # SPI Clock Rate Selects
+ 'SPSR' : '$4d', # SPI Status Register
+ 'SPSR_SPIF': '$80', # SPI Interrupt Flag
+ 'SPSR_WCOL': '$40', # Write Collision Flag
+ 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
+ 'SPDR' : '$4e', # SPI Data Register
+
+# Module TWI
+ 'TWBR' : '$b8', # TWI Bit Rate register
+ 'TWCR' : '$bc', # TWI Control Register
+ 'TWCR_TWINT': '$80', # TWI Interrupt Flag
+ 'TWCR_TWEA': '$40', # TWI Enable Acknowledge Bit
+ 'TWCR_TWSTA': '$20', # TWI Start Condition Bit
+ 'TWCR_TWSTO': '$10', # TWI Stop Condition Bit
+ 'TWCR_TWWC': '$8', # TWI Write Collition Flag
+ 'TWCR_TWEN': '$4', # TWI Enable Bit
+ 'TWCR_TWIE': '$1', # TWI Interrupt Enable
+ 'TWSR' : '$b9', # TWI Status Register
+ 'TWSR_TWS': '$f8', # TWI Status
+ 'TWSR_TWPS': '$3', # TWI Prescaler
+ 'TWDR' : '$bb', # TWI Data register
+ 'TWAR' : '$ba', # TWI (Slave) Address register
+ 'TWAR_TWA': '$fe', # TWI (Slave) Address register B
+ 'TWAR_TWGCE': '$1', # TWI General Call Recognition E
+
+# Module USART0
+ 'UDR0' : '$c6', # USART I/O Data Register
+ 'UCSR0A' : '$c0', # USART Control and Status Regis
+ 'UCSR0A_RXC0': '$80', # USART Receive Complete
+ 'UCSR0A_TXC0': '$40', # USART Transmitt Complete
+ 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
+ 'UCSR0A_FE0': '$10', # Framing Error
+ 'UCSR0A_DOR0': '$8', # Data overRun
+ 'UCSR0A_UPE0': '$4', # Parity Error
+ 'UCSR0A_U2X0': '$2', # Double the USART transmission
+ 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
+ 'UCSR0B' : '$c1', # USART Control and Status Regis
+ 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
+ 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
+ 'UCSR0B_UDRIE0': '$20', # USART Data register Empty Inte
+ 'UCSR0B_RXEN0': '$10', # Receiver Enable
+ 'UCSR0B_TXEN0': '$8', # Transmitter Enable
+ 'UCSR0B_UCSZ02': '$4', # Character Size
+ 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
+ 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
+ 'UCSR0C' : '$c2', # USART Control and Status Regis
+ 'UCSR0C_UMSEL0': '$40', # USART Mode Select
+ 'UCSR0C_UPM0': '$30', # Parity Mode Bits
+ 'UCSR0C_USBS0': '$8', # Stop Bit Select
+ 'UCSR0C_UCSZ0': '$6', # Character Size
+ 'UCSR0C_UCPOL0': '$1', # Clock Polarity
+ 'UBRR0' : '$c4', # USART Baud Rate Register t Byt
+
+# Module USART1
+ 'UDR1' : '$ce', # USART I/O Data Register
+ 'UCSR1A' : '$c8', # USART Control and Status Regis
+ 'UCSR1A_RXC1': '$80', # USART Receive Complete
+ 'UCSR1A_TXC1': '$40', # USART Transmitt Complete
+ 'UCSR1A_UDRE1': '$20', # USART Data Register Empty
+ 'UCSR1A_FE1': '$10', # Framing Error
+ 'UCSR1A_DOR1': '$8', # Data overRun
+ 'UCSR1A_UPE1': '$4', # Parity Error
+ 'UCSR1A_U2X1': '$2', # Double the USART transmission
+ 'UCSR1A_MPCM1': '$1', # Multi-processor Communication
+ 'UCSR1B' : '$c9', # USART Control and Status Regis
+ 'UCSR1B_RXCIE1': '$80', # RX Complete Interrupt Enable
+ 'UCSR1B_TXCIE1': '$40', # TX Complete Interrupt Enable
+ 'UCSR1B_UDRIE1': '$20', # USART Data register Empty Inte
+ 'UCSR1B_RXEN1': '$10', # Receiver Enable
+ 'UCSR1B_TXEN1': '$8', # Transmitter Enable
+ 'UCSR1B_UCSZ12': '$4', # Character Size
+ 'UCSR1B_RXB81': '$2', # Receive Data Bit 8
+ 'UCSR1B_TXB81': '$1', # Transmit Data Bit 8
+ 'UCSR1C' : '$ca', # USART Control and Status Regis
+ 'UCSR1C_UMSEL1': '$40', # USART Mode Select
+ 'UCSR1C_UPM1': '$30', # Parity Mode Bits
+ 'UCSR1C_USBS1': '$8', # Stop Bit Select
+ 'UCSR1C_UCSZ1': '$6', # Character Size
+ 'UCSR1C_UCPOL1': '$1', # Clock Polarity
+ 'UBRR1' : '$cc', # USART Baud Rate Register t Byt
+
+# Module CPU
+ 'SREG' : '$5f', # Status Register
+ 'SREG_I': '$80', # Global Interrupt Enable
+ 'SREG_T': '$40', # Bit Copy Storage
+ 'SREG_H': '$20', # Half Carry Flag
+ 'SREG_S': '$10', # Sign Bit
+ 'SREG_V': '$8', # Two's Complement Overflow Flag
+ 'SREG_N': '$4', # Negative Flag
+ 'SREG_Z': '$2', # Zero Flag
+ 'SREG_C': '$1', # Carry Flag
+ 'SP' : '$5d', # Stack Pointer
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_PUD': '$10', # Pull-up disable
+ 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
+ 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+ 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
+ 'MCUSR_BORF': '$4', # Brown-out Reset Flag
+ 'MCUSR_EXTRF': '$2', # External Reset Flag
+ 'MCUSR_PORF': '$1', # Power-on reset flag
+ 'XMCRA' : '$74', # External Memory Control Regist
+ 'XMCRA_SRE': '$80', # External SRAM Enable
+ 'XMCRA_SRL': '$70', # Wait state page limit
+ 'XMCRA_SRW1': '$c', # Wait state select bit upper pa
+ 'XMCRA_SRW0': '$3', # Wait state select bit lower pa
+ 'XMCRB' : '$75', # External Memory Control Regist
+ 'XMCRB_XMBK': '$80', # External Memory Bus Keeper Ena
+ 'XMCRB_XMM': '$7', # External Memory High Mask
+ 'OSCCAL' : '$66', # Oscillator Calibration Value
+ 'CLKPR' : '$61', # Clock Prescale Register
+ 'CLKPR_CLKPCE': '$80', #
+ 'CLKPR_CLKPS': '$f', #
+ 'SMCR' : '$53', # Sleep Mode Control Register
+ 'SMCR_SM': '$e', # Sleep Mode Select bits
+ 'SMCR_SE': '$1', # Sleep Enable
+ 'RAMPZ' : '$5b', # RAM Page Z Select Register - N
+ 'RAMPZ_RAMPZ0': '$1', # RAM Page Z Select Register Bit
+ 'GPIOR2' : '$4b', # General Purpose IO Register 2
+ 'GPIOR2_GPIOR': '$ff', # General Purpose IO Register 2
+ 'GPIOR1' : '$4a', # General Purpose IO Register 1
+ 'GPIOR1_GPIOR': '$ff', # General Purpose IO Register 1
+ 'GPIOR0' : '$3e', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR07': '$80', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR06': '$40', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR05': '$20', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR04': '$10', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR03': '$8', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR02': '$4', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR01': '$2', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR00': '$1', # General Purpose IO Register 0
+
+# Module BOOT_LOAD
+ 'SPMCSR' : '$57', # Store Program Memory Control R
+ 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
+ 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
+ 'SPMCSR_RWWSRE': '$10', # Read While Write section read
+ 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
+ 'SPMCSR_PGWRT': '$4', # Page Write
+ 'SPMCSR_PGERS': '$2', # Page Erase
+ 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
+
+# Module EXTERNAL_INTERRUPT
+ 'EICRA' : '$69', # External Interrupt Control Reg
+ 'EICRA_ISC3': '$c0', # External Interrupt Sense Contr
+ 'EICRA_ISC2': '$30', # External Interrupt Sense Contr
+ 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
+ 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
+ 'EICRB' : '$6a', # External Interrupt Control Reg
+ 'EICRB_ISC7': '$c0', # External Interrupt 7-4 Sense C
+ 'EICRB_ISC6': '$30', # External Interrupt 7-4 Sense C
+ 'EICRB_ISC5': '$c', # External Interrupt 7-4 Sense C
+ 'EICRB_ISC4': '$3', # External Interrupt 7-4 Sense C
+ 'EIMSK' : '$3d', # External Interrupt Mask Regist
+ 'EIMSK_INT': '$ff', # External Interrupt Request 7 E
+ 'EIFR' : '$3c', # External Interrupt Flag Regist
+ 'EIFR_INTF': '$ff', # External Interrupt Flags
+
+# Module EEPROM
+ 'EEAR' : '$41', # EEPROM Read/Write Access Byte
+ 'EEDR' : '$40', # EEPROM Data Register
+ 'EECR' : '$3f', # EEPROM Control Register
+ 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
+ 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
+ 'EECR_EEWE': '$2', # EEPROM Write Enable
+ 'EECR_EERE': '$1', # EEPROM Read Enable
+
+# Module PORTG
+ 'PORTG' : '$34', # Data Register, Port G
+ 'DDRG' : '$33', # Data Direction Register, Port
+ 'PING' : '$32', # Input Pins, Port G
+
+# Module TIMER_COUNTER_0
+ 'TCCR0A' : '$44', # Timer/Counter0 Control Registe
+ 'TCCR0A_FOC0A': '$80', # Force Output Compare
+ 'TCCR0A_WGM00': '$40', # Waveform Generation Mode 0
+ 'TCCR0A_COM0A': '$30', # Compare Match Output Modes
+ 'TCCR0A_WGM01': '$8', # Waveform Generation Mode 1
+ 'TCCR0A_CS0': '$7', # Clock Selects
+ 'TCNT0' : '$46', # Timer/Counter0
+ 'OCR0A' : '$47', # Timer/Counter0 Output Compare
+ 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
+ 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
+ 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
+ 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
+ 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
+ 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Control Register
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSR310': '$1', # Prescaler Reset Timer/Counter1
+
+# Module TIMER_COUNTER_1
+ 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
+ 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
+ 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
+ 'TCCR1A_COM1C': '$c', # Compare Output Mode 1C, bits
+ 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
+ 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
+ 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
+ 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
+ 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
+ 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
+ 'TCCR1C' : '$82', # Timer/Counter 1 Control Regist
+ 'TCCR1C_FOC1A': '$80', # Force Output Compare 1A
+ 'TCCR1C_FOC1B': '$40', # Force Output Compare 1B
+ 'TCCR1C_FOC1C': '$20', # Force Output Compare 1C
+ 'TCNT1' : '$84', # Timer/Counter1 Bytes
+ 'OCR1A' : '$88', # Timer/Counter1 Output Compare
+ 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
+ 'OCR1C' : '$8c', # Timer/Counter1 Output Compare
+ 'ICR1' : '$86', # Timer/Counter1 Input Capture R
+ 'TIMSK1' : '$6f', # Timer/Counter Interrupt Mask R
+ 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
+ 'TIMSK1_OCIE1C': '$8', # Timer/Counter1 Output CompareC
+ 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output CompareB
+ 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output CompareA
+ 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
+ 'TIFR1' : '$36', # Timer/Counter Interrupt Flag r
+ 'TIFR1_ICF1': '$20', # Input Capture Flag 1
+ 'TIFR1_OCF1C': '$8', # Output Compare Flag 1C
+ 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
+ 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
+ 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
+
+# Module TIMER_COUNTER_3
+ 'TCCR3A' : '$90', # Timer/Counter3 Control Registe
+ 'TCCR3A_COM3A': '$c0', # Compare Output Mode 3A, bits
+ 'TCCR3A_COM3B': '$30', # Compare Output Mode 3B, bits
+ 'TCCR3A_COM3C': '$c', # Compare Output Mode 3C, bits
+ 'TCCR3A_WGM3': '$3', # Waveform Generation Mode
+ 'TCCR3B' : '$91', # Timer/Counter3 Control Registe
+ 'TCCR3B_ICNC3': '$80', # Input Capture 3 Noise Canceler
+ 'TCCR3B_ICES3': '$40', # Input Capture 3 Edge Select
+ 'TCCR3B_WGM3': '$18', # Waveform Generation Mode
+ 'TCCR3B_CS3': '$7', # Prescaler source of Timer/Coun
+ 'TCCR3C' : '$92', # Timer/Counter 3 Control Regist
+ 'TCCR3C_FOC3A': '$80', # Force Output Compare 3A
+ 'TCCR3C_FOC3B': '$40', # Force Output Compare 3B
+ 'TCCR3C_FOC3C': '$20', # Force Output Compare 3C
+ 'TCNT3' : '$94', # Timer/Counter3 Bytes
+ 'OCR3A' : '$98', # Timer/Counter3 Output Compare
+ 'OCR3B' : '$9a', # Timer/Counter3 Output Compare
+ 'OCR3C' : '$9c', # Timer/Counter3 Output Compare
+ 'ICR3' : '$96', # Timer/Counter3 Input Capture R
+ 'TIMSK3' : '$71', # Timer/Counter Interrupt Mask R
+ 'TIMSK3_ICIE3': '$20', # Timer/Counter3 Input Capture I
+ 'TIMSK3_OCIE3C': '$8', # Timer/Counter3 Output CompareC
+ 'TIMSK3_OCIE3B': '$4', # Timer/Counter3 Output CompareB
+ 'TIMSK3_OCIE3A': '$2', # Timer/Counter3 Output CompareA
+ 'TIMSK3_TOIE3': '$1', # Timer/Counter3 Overflow Interr
+ 'TIFR3' : '$38', # Timer/Counter Interrupt Flag r
+ 'TIFR3_ICF3': '$20', # Input Capture Flag 3
+ 'TIFR3_OCF3C': '$8', # Output Compare Flag 3C
+ 'TIFR3_OCF3B': '$4', # Output Compare Flag 3B
+ 'TIFR3_OCF3A': '$2', # Output Compare Flag 3A
+ 'TIFR3_TOV3': '$1', # Timer/Counter3 Overflow Flag
+
+# Module TIMER_COUNTER_2
+ 'TCCR2' : '$b0', # Timer/Counter2 Control Registe
+ 'TCCR2_FOC2A': '$80', # Force Output Compare
+ 'TCCR2_WGM20': '$40', # Waveform Genration Mode
+ 'TCCR2_COM2A': '$30', # Compare Output Mode bits
+ 'TCCR2_WGM21': '$8', # Waveform Generation Mode
+ 'TCCR2_CS2': '$7', # Clock Select bits
+ 'TCNT2' : '$b2', # Timer/Counter2
+ 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
+ 'TIMSK2' : '$70', # Timer/Counter Interrupt Mask r
+ 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
+ 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
+ 'TIFR2' : '$37', # Timer/Counter Interrupt Flag R
+ 'TIFR2_OCF2A': '$2', # Output Compare Flag 2
+ 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_PSR2': '$2', # Prescaler Reset Timer/Counter2
+ 'ASSR' : '$b6', # Asynchronous Status Register
+ 'ASSR_EXCLK': '$10', # Enable External Clock Interrup
+ 'ASSR_AS2': '$8', # AS2: Asynchronous Timer/Counte
+ 'ASSR_TCN2UB': '$4', # TCN2UB: Timer/Counter2 Update
+ 'ASSR_OCR2UB': '$2', # Output Compare Register2 Updat
+ 'ASSR_TCR2UB': '$1', # TCR2UB: Timer/Counter Control
+
+# Module WATCHDOG
+ 'WDTCR' : '$60', # Watchdog Timer Control Registe
+ 'WDTCR_WDCE': '$10', # Watchdog Change Enable
+ 'WDTCR_WDE': '$8', # Watch Dog Enable
+ 'WDTCR_WDP': '$7', # Watch Dog Timer Prescaler bits
+
+# Module AD_CONVERTER
+ 'ADMUX' : '$7c', # The ADC multiplexer Selection
+ 'ADMUX_REFS': '$c0', # Reference Selection Bits
+ 'ADMUX_ADLAR': '$20', # Left Adjust Result
+ 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
+ 'ADCSRA' : '$7a', # The ADC Control and Status reg
+ 'ADCSRA_ADEN': '$80', # ADC Enable
+ 'ADCSRA_ADSC': '$40', # ADC Start Conversion
+ 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
+ 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
+ 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
+ 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
+ 'ADC' : '$78', # ADC Data Register Bytes
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ADHSM': '$80', # ADC High Speed Mode
+ 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Sources
+ 'DIDR0' : '$7e', # Digital Input Disable Register
+ 'DIDR0_ADC7D': '$80', # ADC7 Digital input Disable
+ 'DIDR0_ADC6D': '$40', # ADC6 Digital input Disable
+ 'DIDR0_ADC5D': '$20', # ADC5 Digital input Disable
+ 'DIDR0_ADC4D': '$10', # ADC4 Digital input Disable
+ 'DIDR0_ADC3D': '$8', # ADC3 Digital input Disable
+ 'DIDR0_ADC2D': '$4', # ADC2 Digital input Disable
+ 'DIDR0_ADC1D': '$2', # ADC1 Digital input Disable
+ 'DIDR0_ADC0D': '$1', # ADC0 Digital input Disable
+
+# Module ANALOG_COMPARATOR
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
+ 'ACSR' : '$50', # Analog Comparator Control And
+ 'ACSR_ACD': '$80', # Analog Comparator Disable
+ 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
+ 'ACSR_ACO': '$20', # Analog Compare Output
+ 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
+ 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
+ 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
+ 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
+ 'DIDR1' : '$7f', #
+ 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
+ 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
+
+# Module CAN
+ 'CANGCON' : '$d8', # CAN General Control Register
+ 'CANGCON_ABRQ': '$80', # Abort Request
+ 'CANGCON_OVRQ': '$40', # Overload Frame Request
+ 'CANGCON_TTC': '$20', # Time Trigger Communication
+ 'CANGCON_SYNTTC': '$10', # Synchronization of TTC
+ 'CANGCON_LISTEN': '$8', # Listening Mode
+ 'CANGCON_TEST': '$4', # Test Mode
+ 'CANGCON_ENASTB': '$2', # Enable / Standby
+ 'CANGCON_SWRES': '$1', # Software Reset Request
+ 'CANGSTA' : '$d9', # CAN General Status Register
+ 'CANGSTA_OVRG': '$40', # Overload Frame Flag
+ 'CANGSTA_TXBSY': '$10', # Transmitter Busy
+ 'CANGSTA_RXBSY': '$8', # Receiver Busy
+ 'CANGSTA_ENFG': '$4', # Enable Flag
+ 'CANGSTA_BOFF': '$2', # Bus Off Mode
+ 'CANGSTA_ERRP': '$1', # Error Passive Mode
+ 'CANGIT' : '$da', # CAN General Interrupt Register
+ 'CANGIT_CANIT': '$80', # General Interrupt Flag
+ 'CANGIT_BOFFIT': '$40', # Bus Off Interrupt Flag
+ 'CANGIT_OVRTIM': '$20', # Overrun CAN Timer
+ 'CANGIT_BXOK': '$10', # Burst Receive Interrupt
+ 'CANGIT_SERG': '$8', # Stuff Error General
+ 'CANGIT_CERG': '$4', # CRC Error General
+ 'CANGIT_FERG': '$2', # Form Error General
+ 'CANGIT_AERG': '$1', # Ackknowledgement Error General
+ 'CANGIE' : '$db', # CAN General Interrupt Enable R
+ 'CANGIE_ENIT': '$80', # Enable all Interrupts
+ 'CANGIE_ENBOFF': '$40', # Enable Bus Off INterrupt
+ 'CANGIE_ENRX': '$20', # Enable Receive Interrupt
+ 'CANGIE_ENTX': '$10', # Enable Transmitt Interrupt
+ 'CANGIE_ENERR': '$8', # Enable MOb Error Interrupt
+ 'CANGIE_ENBX': '$4', # Enable Burst Receive Interrupt
+ 'CANGIE_ENERG': '$2', # Enable General Error Interrupt
+ 'CANGIE_ENOVRT': '$1', # Enable CAN Timer Overrun Inter
+ 'CANEN2' : '$dc', # Enable MOb Register
+ 'CANEN1' : '$dd', # Enable MOb Register
+ 'CANIE2' : '$de', # Enable Interrupt MOb Register
+ 'CANIE1' : '$df', # Enable Interrupt MOb Register
+ 'CANSIT2' : '$e0', # CAN Status Interrupt MOb Regis
+ 'CANSIT1' : '$e1', # CAN Status Interrupt MOb Regis
+ 'CANBT1' : '$e2', # Bit Timing Register 1
+ 'CANBT1_BRP': '$7e', # Baud Rate Prescaler bits
+ 'CANBT2' : '$e3', # Bit Timing Register 2
+ 'CANBT2_SJW': '$60', # Re-Sync Jump Width
+ 'CANBT2_PRS': '$e', # Propagation Time Segment
+ 'CANBT3' : '$e4', # Bit Timing Register 3
+ 'CANBT3_PHS2': '$70', # Phase Segments
+ 'CANBT3_PHS1': '$e', # Phase Segment 1
+ 'CANBT3_SMP': '$1', # Sample Type
+ 'CANTCON' : '$e5', # Timer Control Register
+ 'CANTIML' : '$e6', # Timer Register Low
+ 'CANTIMH' : '$e7', # Timer Register High
+ 'CANTTCL' : '$e8', # TTC Timer Register Low
+ 'CANTTCH' : '$e9', # TTC Timer Register High
+ 'CANTEC' : '$ea', # Transmit Error Counter Registe
+ 'CANREC' : '$eb', # Receive Error Counter Register
+ 'CANHPMOB' : '$ec', # Highest Priority MOb Register
+ 'CANPAGE' : '$ed', # Page MOb Register
+ 'CANPAGE_MOBNB': '$f0', # MOb Number Bits
+ 'CANPAGE_AINC': '$8', # MOb Data Buffer Auto Increment
+ 'CANPAGE_INDX': '$7', # Data Buffer Index Bits
+ 'CANSTMOB' : '$ee', # MOb Status Register
+ 'CANSTMOB_DLCW': '$80', # Data Length Code Warning
+ 'CANSTMOB_TXOK': '$40', # Transmit OK
+ 'CANSTMOB_RXOK': '$20', # Receive OK
+ 'CANSTMOB_BERR': '$10', # Bit Error
+ 'CANSTMOB_SERR': '$8', # Stuff Error
+ 'CANSTMOB_CERR': '$4', # CRC Error
+ 'CANSTMOB_FERR': '$2', # Form Error
+ 'CANSTMOB_AERR': '$1', # Ackknowledgement Error
+ 'CANCDMOB' : '$ef', # MOb Control and DLC Register
+ 'CANCDMOB_CONMOB': '$c0', # MOb Config Bits
+ 'CANCDMOB_RPLV': '$20', # Reply Valid
+ 'CANCDMOB_IDE': '$10', # Identifier Extension
+ 'CANCDMOB_DLC': '$f', # Data Length Code Bits
+ 'CANIDT4' : '$f0', # Identifier Tag Register 4
+ 'CANIDT3' : '$f1', # Identifier Tag Register 3
+ 'CANIDT2' : '$f2', # Identifier Tag Register 2
+ 'CANIDT1' : '$f3', # Identifier Tag Register 1
+ 'CANIDM4' : '$f4', # Identifier Mask Register 4
+ 'CANIDM3' : '$f5', # Identifier Mask Register 3
+ 'CANIDM2' : '$f6', # Identifier Mask Register 2
+ 'CANIDM1' : '$f7', # Identifier Mask Register 1
+ 'CANSTML' : '$f8', # Time Stamp Register Low
+ 'CANSTMH' : '$f9', # Time Stamp Register High
+ 'CANMSG' : '$fa', # Message Data Register
+
+ '__amforth_dummy':'0'
+}
diff --git a/amforth-6.5/avr8/devices/at90can64/words/no-jtag.asm b/amforth-6.5/avr8/devices/at90can64/words/no-jtag.asm
new file mode 100644
index 0000000..352a4bb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90can64/words/no-jtag.asm
@@ -0,0 +1,14 @@
+; ( -- )
+; ( -- )
+; MCU
+; disable jtag at runtime
+VE_NOJTAG:
+ .dw $FF05
+ .db "-jtag",0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOJTAG
+XT_NOJTAG:
+ .dw PFA_NOJTAG
+PFA_NOJTAG:
+
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/at90can64/words/no-wdt.asm b/amforth-6.5/avr8/devices/at90can64/words/no-wdt.asm
new file mode 100644
index 0000000..4a12261
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90can64/words/no-wdt.asm
@@ -0,0 +1,22 @@
+; ( -- )
+; MCU
+; disable watch dog timer at runtime
+VE_NOWDT:
+ .dw $ff04
+ .db "-wdt"
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOWDT
+XT_NOWDT:
+ .dw PFA_NOWDT
+PFA_NOWDT:
+
+; Reset WDT
+ wdr
+; Write logical one to WDTOE and WDE
+ in_ temp1, WDTCR
+ ori temp1, (1<<WDTOE)|(1<<WDE)
+ out WDTCR, temp1
+; Turn off WDT
+ ldi temp1, (0<<WDE)
+ out_ WDTCR, temp1
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/at90can64/words/sleep.asm b/amforth-6.5/avr8/devices/at90can64/words/sleep.asm
new file mode 100644
index 0000000..256249c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90can64/words/sleep.asm
@@ -0,0 +1,19 @@
+; ( mode -- )
+; MCU
+; put the controller into the specified sleep mode
+VE_SLEEP:
+ .dw $ff05
+ .db "sleep", 0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_SLEEP
+XT_SLEEP:
+ .dw PFA_SLEEP
+PFA_SLEEP:
+ andi tosl, 7 ; leave only legal mode bits
+ lsl tosl ; move to correct location (bits 3-1)
+ ori tosl, 1 ; set the SE bit
+ out_ SMCR, tosl ; set the sleep config
+ sleep ; nighty-night
+ out_ SMCR, zerol ; 0 protects against accidental sleeps
+ loadtos ; pop argument from stack
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/at90pwm1/at90pwm1.frt b/amforth-6.5/avr8/devices/at90pwm1/at90pwm1.frt
new file mode 100644
index 0000000..e17d4b8
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90pwm1/at90pwm1.frt
@@ -0,0 +1,381 @@
+\ Partname: AT90PWM1
+\ generated automatically
+
+\ PORTB
+&37 constant PORTB \ Port B Data Register
+&36 constant DDRB \ Port B Data Direction Register
+&35 constant PINB \ Port B Input Pins
+\ PORTD
+&43 constant PORTD \ Port D Data Register
+&42 constant DDRD \ Port D Data Direction Register
+&41 constant PIND \ Port D Input Pins
+\ BOOT_LOAD
+&87 constant SPMCSR \ Store Program Memory Control Register
+ $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
+ $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
+ $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
+ $04 constant SPMCSR_PGWRT \ Page Write
+ $02 constant SPMCSR_PGERS \ Page Erase
+ $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
+\ PSC0
+&222 constant PICR0 \ PSC 0 Input Capture Register
+&221 constant PFRC0B \ PSC 0 Input B Control
+ $80 constant PFRC0B_PCAE0B \ PSC 0 Capture Enable Input Part B
+ $40 constant PFRC0B_PISEL0B \ PSC 0 Input Select for Part B
+ $20 constant PFRC0B_PELEV0B \ PSC 0 Edge Level Selector on Input Part B
+ $10 constant PFRC0B_PFLTE0B \ PSC 0 Filter Enable on Input Part B
+ $0F constant PFRC0B_PRFM0B \ PSC 0 Retrigger and Fault Mode for Part B
+&220 constant PFRC0A \ PSC 0 Input A Control
+ $80 constant PFRC0A_PCAE0A \ PSC 0 Capture Enable Input Part A
+ $40 constant PFRC0A_PISEL0A \ PSC 0 Input Select for Part A
+ $20 constant PFRC0A_PELEV0A \ PSC 0 Edge Level Selector on Input Part A
+ $10 constant PFRC0A_PFLTE0A \ PSC 0 Filter Enable on Input Part A
+ $0F constant PFRC0A_PRFM0A \ PSC 0 Retrigger and Fault Mode for Part A
+&219 constant PCTL0 \ PSC 0 Control Register
+ $C0 constant PCTL0_PPRE0 \ PSC 0 Prescaler Selects
+ $20 constant PCTL0_PBFM0 \ PSC 0 Balance Flank Width Modulation
+ $10 constant PCTL0_PAOC0B \ PSC 0 Asynchronous Output Control B
+ $08 constant PCTL0_PAOC0A \ PSC 0 Asynchronous Output Control A
+ $04 constant PCTL0_PARUN0 \ PSC0 Auto Run
+ $02 constant PCTL0_PCCYC0 \ PSC0 Complete Cycle
+ $01 constant PCTL0_PRUN0 \ PSC 0 Run
+&218 constant PCNF0 \ PSC 0 Configuration Register
+ $80 constant PCNF0_PFIFTY0 \ PSC 0 Fifty
+ $40 constant PCNF0_PALOCK0 \ PSC 0 Autolock
+ $20 constant PCNF0_PLOCK0 \ PSC 0 Lock
+ $18 constant PCNF0_PMODE0 \ PSC 0 Mode
+ $04 constant PCNF0_POP0 \ PSC 0 Output Polarity
+ $02 constant PCNF0_PCLKSEL0 \ PSC 0 Input Clock Select
+&216 constant OCR0RB \ Output Compare RB Register
+&214 constant OCR0SB \ Output Compare SB Register
+&212 constant OCR0RA \ Output Compare RA Register
+&210 constant OCR0SA \ Output Compare SA Register
+&208 constant PSOC0 \ PSC0 Synchro and Output Configuration
+ $30 constant PSOC0_PSYNC0 \ Synchronization Out for ADC Selection
+ $04 constant PSOC0_POEN0B \ PSCOUT01 Output Enable
+ $01 constant PSOC0_POEN0A \ PSCOUT00 Output Enable
+&161 constant PIM0 \ PSC0 Interrupt Mask Register
+ $20 constant PIM0_PSEIE0 \ PSC 0 Synchro Error Interrupt Enable
+ $10 constant PIM0_PEVE0B \ External Event B Interrupt Enable
+ $08 constant PIM0_PEVE0A \ External Event A Interrupt Enable
+ $01 constant PIM0_PEOPE0 \ End of Cycle Interrupt Enable
+&160 constant PIFR0 \ PSC0 Interrupt Flag Register
+ $20 constant PIFR0_PSEI0 \ PSC 0 Synchro Error Interrupt
+ $10 constant PIFR0_PEV0B \ External Event B Interrupt
+ $08 constant PIFR0_PEV0A \ External Event A Interrupt
+ $06 constant PIFR0_PRN0 \ Ramp Number
+ $01 constant PIFR0_PEOP0 \ End of PSC0 Interrupt
+\ PSC2
+&254 constant PICR2 \ PSC 2 Input Capture Register
+&253 constant PFRC2B \ PSC 2 Input B Control
+ $80 constant PFRC2B_PCAE2B \ PSC 2 Capture Enable Input Part B
+ $40 constant PFRC2B_PISEL2B \ PSC 2 Input Select for Part B
+ $20 constant PFRC2B_PELEV2B \ PSC 2 Edge Level Selector on Input Part B
+ $10 constant PFRC2B_PFLTE2B \ PSC 2 Filter Enable on Input Part B
+ $0F constant PFRC2B_PRFM2B \ PSC 2 Retrigger and Fault Mode for Part B
+&252 constant PFRC2A \ PSC 2 Input B Control
+ $80 constant PFRC2A_PCAE2A \ PSC 2 Capture Enable Input Part A
+ $40 constant PFRC2A_PISEL2A \ PSC 2 Input Select for Part A
+ $20 constant PFRC2A_PELEV2A \ PSC 2 Edge Level Selector on Input Part A
+ $10 constant PFRC2A_PFLTE2A \ PSC 2 Filter Enable on Input Part A
+ $0F constant PFRC2A_PRFM2A \ PSC 2 Retrigger and Fault Mode for Part A
+&251 constant PCTL2 \ PSC 2 Control Register
+ $C0 constant PCTL2_PPRE2 \ PSC 2 Prescaler Selects
+ $20 constant PCTL2_PBFM2 \ Balance Flank Width Modulation
+ $10 constant PCTL2_PAOC2B \ PSC 2 Asynchronous Output Control B
+ $08 constant PCTL2_PAOC2A \ PSC 2 Asynchronous Output Control A
+ $04 constant PCTL2_PARUN2 \ PSC2 Auto Run
+ $02 constant PCTL2_PCCYC2 \ PSC2 Complete Cycle
+ $01 constant PCTL2_PRUN2 \ PSC 2 Run
+&250 constant PCNF2 \ PSC 2 Configuration Register
+ $80 constant PCNF2_PFIFTY2 \ PSC 2 Fifty
+ $40 constant PCNF2_PALOCK2 \ PSC 2 Autolock
+ $20 constant PCNF2_PLOCK2 \ PSC 2 Lock
+ $18 constant PCNF2_PMODE2 \ PSC 2 Mode
+ $04 constant PCNF2_POP2 \ PSC 2 Output Polarity
+ $02 constant PCNF2_PCLKSEL2 \ PSC 2 Input Clock Select
+ $01 constant PCNF2_POME2 \ PSC 2 Output Matrix Enable
+&248 constant OCR2RB \ Output Compare RB Register
+&246 constant OCR2SB \ Output Compare SB Register
+&244 constant OCR2RA \ Output Compare RA Register
+&242 constant OCR2SA \ Output Compare SA Register
+&241 constant POM2 \ PSC 2 Output Matrix
+ $F0 constant POM2_POMV2B \ Output Matrix Output B Ramps
+ $0F constant POM2_POMV2A \ Output Matrix Output A Ramps
+&240 constant PSOC2 \ PSC2 Synchro and Output Configuration
+ $C0 constant PSOC2_POS2 \ PSC 2 Output 23 Select
+ $30 constant PSOC2_PSYNC2_ \ Synchronization Out for ADC Selection
+ $08 constant PSOC2_POEN2D \ PSCOUT23 Output Enable
+ $04 constant PSOC2_POEN2B \ PSCOUT21 Output Enable
+ $02 constant PSOC2_POEN2C \ PSCOUT22 Output Enable
+ $01 constant PSOC2_POEN2A \ PSCOUT20 Output Enable
+&165 constant PIM2 \ PSC2 Interrupt Mask Register
+ $20 constant PIM2_PSEIE2 \ PSC 2 Synchro Error Interrupt Enable
+ $10 constant PIM2_PEVE2B \ External Event B Interrupt Enable
+ $08 constant PIM2_PEVE2A \ External Event A Interrupt Enable
+ $01 constant PIM2_PEOPE2 \ End of Cycle Interrupt Enable
+&164 constant PIFR2 \ PSC2 Interrupt Flag Register
+ $20 constant PIFR2_PSEI2 \ PSC 2 Synchro Error Interrupt
+ $10 constant PIFR2_PEV2B \ External Event B Interrupt
+ $08 constant PIFR2_PEV2A \ External Event A Interrupt
+ $06 constant PIFR2_PRN2 \ Ramp Number
+ $01 constant PIFR2_PEOP2 \ End of PSC2 Interrupt
+\ CPU
+&95 constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ $08 constant SREG_V \ Two's Complement Overflow Flag
+ $04 constant SREG_N \ Negative Flag
+ $02 constant SREG_Z \ Zero Flag
+ $01 constant SREG_C \ Carry Flag
+&93 constant SP \ Stack Pointer
+&85 constant MCUCR \ MCU Control Register
+ $80 constant MCUCR_SPIPS \ SPI Pin Select
+ $10 constant MCUCR_PUD \ Pull-up disable
+ $02 constant MCUCR_IVSEL \ Interrupt Vector Select
+ $01 constant MCUCR_IVCE \ Interrupt Vector Change Enable
+&84 constant MCUSR \ MCU Status Register
+ $08 constant MCUSR_WDRF \ Watchdog Reset Flag
+ $04 constant MCUSR_BORF \ Brown-out Reset Flag
+ $02 constant MCUSR_EXTRF \ External Reset Flag
+ $01 constant MCUSR_PORF \ Power-on reset flag
+&102 constant OSCCAL \ Oscillator Calibration Value
+&97 constant CLKPR \
+ $80 constant CLKPR_CLKPCE \
+ $0F constant CLKPR_CLKPS \
+&83 constant SMCR \ Sleep Mode Control Register
+ $0E constant SMCR_SM \ Sleep Mode Select bits
+ $01 constant SMCR_SE \ Sleep Enable
+&59 constant GPIOR3 \ General Purpose IO Register 3
+ $FF constant GPIOR3_GPIOR \ General Purpose IO Register 3 bis
+&58 constant GPIOR2 \ General Purpose IO Register 2
+ $FF constant GPIOR2_GPIOR \ General Purpose IO Register 2 bis
+&57 constant GPIOR1 \ General Purpose IO Register 1
+ $FF constant GPIOR1_GPIOR \ General Purpose IO Register 1 bis
+&62 constant GPIOR0 \ General Purpose IO Register 0
+ $80 constant GPIOR0_GPIOR07 \ General Purpose IO Register 0 bit 7
+ $40 constant GPIOR0_GPIOR06 \ General Purpose IO Register 0 bit 6
+ $20 constant GPIOR0_GPIOR05 \ General Purpose IO Register 0 bit 5
+ $10 constant GPIOR0_GPIOR04 \ General Purpose IO Register 0 bit 4
+ $08 constant GPIOR0_GPIOR03 \ General Purpose IO Register 0 bit 3
+ $04 constant GPIOR0_GPIOR02 \ General Purpose IO Register 0 bit 2
+ $02 constant GPIOR0_GPIOR01 \ General Purpose IO Register 0 bit 1
+ $01 constant GPIOR0_GPIOR00 \ General Purpose IO Register 0 bit 0
+&73 constant PLLCSR \ PLL Control And Status Register
+ $04 constant PLLCSR_PLLF \ PLL Factor
+ $02 constant PLLCSR_PLLE \ PLL Enable
+ $01 constant PLLCSR_PLOCK \ PLL Lock Detector
+&100 constant PRR \ Power Reduction Register
+ $E0 constant PRR_PRPSC \ Power Reduction PSC2
+ $10 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
+ $08 constant PRR_PRTIM0 \ Power Reduction Timer/Counter0
+ $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
+ $02 constant PRR_PRUSART0 \ Power Reduction USART
+ $01 constant PRR_PRADC \ Power Reduction ADC
+\ PORTE
+&46 constant PORTE \ Port E Data Register
+&45 constant DDRE \ Port E Data Direction Register
+&44 constant PINE \ Port E Input Pins
+\ TIMER_COUNTER_0
+&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
+ $04 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare Match B Interrupt Enable
+ $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match A Interrupt Enable
+ $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
+&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
+ $04 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare Flag 0B
+ $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0A
+ $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
+&68 constant TCCR0A \ Timer/Counter Control Register A
+ $C0 constant TCCR0A_COM0A \ Compare Output Mode, Phase Correct PWM Mode
+ $30 constant TCCR0A_COM0B \ Compare Output Mode, Fast PWm
+ $03 constant TCCR0A_WGM0 \ Waveform Generation Mode
+&69 constant TCCR0B \ Timer/Counter Control Register B
+ $80 constant TCCR0B_FOC0A \ Force Output Compare A
+ $40 constant TCCR0B_FOC0B \ Force Output Compare B
+ $08 constant TCCR0B_WGM02 \
+ $07 constant TCCR0B_CS0 \ Clock Select
+&70 constant TCNT0 \ Timer/Counter0
+&71 constant OCR0A \ Timer/Counter0 Output Compare Register
+&72 constant OCR0B \ Timer/Counter0 Output Compare Register
+&67 constant GTCCR \ General Timer/Counter Control Register
+ $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
+ $40 constant GTCCR_ICPSEL1 \ Timer1 Input Capture Selection Bit
+ $01 constant GTCCR_PSR10 \ Prescaler Reset Timer/Counter1 and Timer/Counter0
+\ TIMER_COUNTER_1
+&111 constant TIMSK1 \ Timer/Counter Interrupt Mask Register
+ $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
+ $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output CompareB Match Interrupt Enable
+ $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output CompareA Match Interrupt Enable
+ $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
+&54 constant TIFR1 \ Timer/Counter Interrupt Flag register
+ $20 constant TIFR1_ICF1 \ Input Capture Flag 1
+ $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
+ $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
+ $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
+&128 constant TCCR1A \ Timer/Counter1 Control Register A
+ $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
+ $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
+ $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
+&129 constant TCCR1B \ Timer/Counter1 Control Register B
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
+ $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
+&130 constant TCCR1C \ Timer/Counter1 Control Register C
+ $80 constant TCCR1C_FOC1A \
+ $40 constant TCCR1C_FOC1B \
+&132 constant TCNT1 \ Timer/Counter1 Bytes
+&136 constant OCR1A \ Timer/Counter1 Output Compare Register Bytes
+&138 constant OCR1B \ Timer/Counter1 Output Compare Register Bytes
+&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
+\ AD_CONVERTER
+&124 constant ADMUX \ The ADC multiplexer Selection Register
+ $C0 constant ADMUX_REFS \ Reference Selection Bits
+ $20 constant ADMUX_ADLAR \ Left Adjust Result
+ $0F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
+&122 constant ADCSRA \ The ADC Control and Status register
+ $80 constant ADCSRA_ADEN \ ADC Enable
+ $40 constant ADCSRA_ADSC \ ADC Start Conversion
+ $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
+ $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
+ $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
+ $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
+&120 constant ADC \ ADC Data Register Bytes
+&123 constant ADCSRB \ ADC Control and Status Register B
+&126 constant DIDR0 \ Digital Input Disable Register 0
+&127 constant DIDR1 \ Digital Input Disable Register 0
+ $20 constant DIDR1_ACMP0D \
+ $10 constant DIDR1_AMP0PD \
+ $08 constant DIDR1_AMP0ND \
+ $04 constant DIDR1_ADC10D \
+ $02 constant DIDR1_ADC9D \
+ $01 constant DIDR1_ADC8D \
+&118 constant AMP0CSR \
+ $80 constant AMP0CSR_AMP0EN \
+ $40 constant AMP0CSR_AMP0IS \
+ $30 constant AMP0CSR_AMP0G \
+ $03 constant AMP0CSR_AMP0TS \
+&119 constant AMP1CSR \
+ $80 constant AMP1CSR_AMP1EN \
+ $40 constant AMP1CSR_AMP1IS \
+ $30 constant AMP1CSR_AMP1G \
+ $03 constant AMP1CSR_AMP1TS \
+\ SPI
+&76 constant SPCR \ SPI Control Register
+ $80 constant SPCR_SPIE \ SPI Interrupt Enable
+ $40 constant SPCR_SPE \ SPI Enable
+ $20 constant SPCR_DORD \ Data Order
+ $10 constant SPCR_MSTR \ Master/Slave Select
+ $08 constant SPCR_CPOL \ Clock polarity
+ $04 constant SPCR_CPHA \ Clock Phase
+ $03 constant SPCR_SPR \ SPI Clock Rate Selects
+&77 constant SPSR \ SPI Status Register
+ $80 constant SPSR_SPIF \ SPI Interrupt Flag
+ $40 constant SPSR_WCOL \ Write Collision Flag
+ $01 constant SPSR_SPI2X \ Double SPI Speed Bit
+&78 constant SPDR \ SPI Data Register
+\ WATCHDOG
+&96 constant WDTCSR \ Watchdog Timer Control Register
+ $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Flag
+ $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Enable
+ $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
+ $10 constant WDTCSR_WDCE \ Watchdog Change Enable
+ $08 constant WDTCSR_WDE \ Watch Dog Enable
+\ EXTERNAL_INTERRUPT
+&105 constant EICRA \ External Interrupt Control Register A
+ $30 constant EICRA_ISC2 \ External Interrupt Sense Control Bit
+ $0C constant EICRA_ISC1 \ External Interrupt Sense Control Bit
+ $03 constant EICRA_ISC0 \ External Interrupt Sense Control Bit
+&61 constant EIMSK \ External Interrupt Mask Register
+ $07 constant EIMSK_INT \ External Interrupt Request 2 Enable
+&60 constant EIFR \ External Interrupt Flag Register
+ $07 constant EIFR_INTF \ External Interrupt Flags
+\ EEPROM
+&65 constant EEAR \ EEPROM Read/Write Access Bytes
+&64 constant EEDR \ EEPROM Data Register
+&63 constant EECR \ EEPROM Control Register
+ $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
+ $04 constant EECR_EEMWE \ EEPROM Master Write Enable
+ $02 constant EECR_EEWE \ EEPROM Write Enable
+ $01 constant EECR_EERE \ EEPROM Read Enable
+\ ANALOG_COMPARATOR
+&173 constant AC0CON \ Analog Comparator 0 Control Register
+ $80 constant AC0CON_AC0EN \ Analog Comparator 0 Enable Bit
+ $40 constant AC0CON_AC0IE \ Analog Comparator 0 Interrupt Enable Bit
+ $30 constant AC0CON_AC0IS \ Analog Comparator 0 Interrupt Select Bit
+ $07 constant AC0CON_AC0M \ Analog Comparator 0 Multiplexer Register
+&175 constant AC2CON \ Analog Comparator 2 Control Register
+ $80 constant AC2CON_AC2EN \ Analog Comparator 2 Enable Bit
+ $40 constant AC2CON_AC2IE \ Analog Comparator 2 Interrupt Enable Bit
+ $30 constant AC2CON_AC2IS \ Analog Comparator 2 Interrupt Select Bit
+ $07 constant AC2CON_AC2M \ Analog Comparator 2 Multiplexer Register
+&80 constant ACSR \ Analog Comparator Status Register
+ $80 constant ACSR_ACCKDIV \ Analog Comparator Clock Divider
+ $40 constant ACSR_AC2IF \ Analog Comparator 2 Interrupt Flag Bit
+ $20 constant ACSR_AC1IF \ Analog Comparator 1 Interrupt Flag Bit
+ $10 constant ACSR_AC0IF \ Analog Comparator 0 Interrupt Flag Bit
+ $04 constant ACSR_AC2O \ Analog Comparator 2 Output Bit
+ $02 constant ACSR_AC1O \ Analog Comparator 1 Output Bit
+ $01 constant ACSR_AC0O \ Analog Comparator 0 Output Bit
+\ PSC1
+&238 constant PICR1 \ PSC 1 Input Capture Register
+&237 constant PFRC1B \ PSC 1 Input B Control
+ $80 constant PFRC1B_PCAE1B \ PSC 1 Capture Enable Input Part B
+ $40 constant PFRC1B_PISEL1B \ PSC 1 Input Select for Part B
+ $20 constant PFRC1B_PELEV1B \ PSC 1 Edge Level Selector on Input Part B
+ $10 constant PFRC1B_PFLTE1B \ PSC 1 Filter Enable on Input Part B
+ $0F constant PFRC1B_PRFM1B \ PSC 1 Retrigger and Fault Mode for Part B
+&236 constant PFRC1A \ PSC 1 Input B Control
+ $80 constant PFRC1A_PCAE1A \ PSC 1 Capture Enable Input Part A
+ $40 constant PFRC1A_PISEL1A \ PSC 1 Input Select for Part A
+ $20 constant PFRC1A_PELEV1A \ PSC 1 Edge Level Selector on Input Part A
+ $10 constant PFRC1A_PFLTE1A \ PSC 1 Filter Enable on Input Part A
+ $0F constant PFRC1A_PRFM1A \ PSC 1 Retrigger and Fault Mode for Part A
+&235 constant PCTL1 \ PSC 1 Control Register
+ $C0 constant PCTL1_PPRE1 \ PSC 1 Prescaler Selects
+ $20 constant PCTL1_PBFM1 \ Balance Flank Width Modulation
+ $10 constant PCTL1_PAOC1B \ PSC 1 Asynchronous Output Control B
+ $08 constant PCTL1_PAOC1A \ PSC 1 Asynchronous Output Control A
+ $04 constant PCTL1_PARUN1 \ PSC1 Auto Run
+ $02 constant PCTL1_PCCYC1 \ PSC1 Complete Cycle
+ $01 constant PCTL1_PRUN1 \ PSC 1 Run
+&224 constant PSOC1 \ PSC1 Synchro and Output Configuration
+ $30 constant PSOC1_PSYNC1_ \ Synchronization Out for ADC Selection
+ $04 constant PSOC1_POEN1B \ PSCOUT11 Output Enable
+ $01 constant PSOC1_POEN1A \ PSCOUT10 Output Enable
+
+\ Interrupts
+&1 constant PSC2_CAPTAddr \ PSC2 Capture Event
+&2 constant PSC2_ECAddr \ PSC2 End Cycle
+&3 constant PSC1_CAPTAddr \ PSC1 Capture Event
+&4 constant PSC1_ECAddr \ PSC1 End Cycle
+&5 constant PSC0_CAPTAddr \ PSC0 Capture Event
+&6 constant PSC0_ECAddr \ PSC0 End Cycle
+&7 constant ANALOG_COMP_0Addr \ Analog Comparator 0
+&8 constant ANALOG_COMP_1Addr \ Analog Comparator 1
+&9 constant ANALOG_COMP_2Addr \ Analog Comparator 2
+&10 constant INT0Addr \ External Interrupt Request 0
+&11 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+&12 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
+&13 constant TIMER1_COMPBAddr \ Timer/Counter Compare Match B
+&14 constant RESERVED15Addr \
+&15 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+&16 constant TIMER0_COMP_AAddr \ Timer/Counter0 Compare Match A
+&17 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
+&18 constant ADCAddr \ ADC Conversion Complete
+&19 constant INT1Addr \ External Interrupt Request 1
+&20 constant SPI__STCAddr \ SPI Serial Transfer Complete
+&21 constant USART__RXAddr \ USART, Rx Complete
+&22 constant USART__UDREAddr \ USART Data Register Empty
+&23 constant USART__TXAddr \ USART, Tx Complete
+&24 constant INT2Addr \ External Interrupt Request 2
+&25 constant WDTAddr \ Watchdog Timeout Interrupt
+&26 constant EE_READYAddr \ EEPROM Ready
+&27 constant TIMER0_COMPBAddr \ Timer Counter 0 Compare Match B
+&28 constant INT3Addr \ External Interrupt Request 3
+&29 constant RESERVED30Addr \
+&30 constant RESERVED31Addr \
+&31 constant SPM_READYAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/at90pwm1/device.asm b/amforth-6.5/avr8/devices/at90pwm1/device.asm
new file mode 100644
index 0000000..af0c2c0
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90pwm1/device.asm
@@ -0,0 +1,121 @@
+; Partname: AT90PWM1
+; generated automatically, do not edit
+
+.nolist
+ .include "pwm1def.inc"
+.list
+
+.equ ramstart = 256
+.equ CELLSIZE = 2
+.macro readflashcell
+ lsl zl
+ rol zh
+ lpm @0, Z+
+ lpm @1, Z+
+.endmacro
+.macro writeflashcell
+ lsl zl
+ rol zh
+.endmacro
+.set WANT_PORTB = 0
+.set WANT_PORTD = 0
+.set WANT_BOOT_LOAD = 0
+.set WANT_PSC0 = 0
+.set WANT_PSC2 = 0
+.set WANT_CPU = 0
+.set WANT_PORTE = 0
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_AD_CONVERTER = 0
+.set WANT_SPI = 0
+.set WANT_WATCHDOG = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_EEPROM = 0
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_PSC1 = 0
+.equ intvecsize = 1 ; please verify; flash size: 8192 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.org 1
+ rcall isr ; PSC2 Capture Event
+.org 2
+ rcall isr ; PSC2 End Cycle
+.org 3
+ rcall isr ; PSC1 Capture Event
+.org 4
+ rcall isr ; PSC1 End Cycle
+.org 5
+ rcall isr ; PSC0 Capture Event
+.org 6
+ rcall isr ; PSC0 End Cycle
+.org 7
+ rcall isr ; Analog Comparator 0
+.org 8
+ rcall isr ; Analog Comparator 1
+.org 9
+ rcall isr ; Analog Comparator 2
+.org 10
+ rcall isr ; External Interrupt Request 0
+.org 11
+ rcall isr ; Timer/Counter1 Capture Event
+.org 12
+ rcall isr ; Timer/Counter1 Compare Match A
+.org 13
+ rcall isr ; Timer/Counter Compare Match B
+.org 14
+ rcall isr ;
+.org 15
+ rcall isr ; Timer/Counter1 Overflow
+.org 16
+ rcall isr ; Timer/Counter0 Compare Match A
+.org 17
+ rcall isr ; Timer/Counter0 Overflow
+.org 18
+ rcall isr ; ADC Conversion Complete
+.org 19
+ rcall isr ; External Interrupt Request 1
+.org 20
+ rcall isr ; SPI Serial Transfer Complete
+.org 21
+ rcall isr ; USART, Rx Complete
+.org 22
+ rcall isr ; USART Data Register Empty
+.org 23
+ rcall isr ; USART, Tx Complete
+.org 24
+ rcall isr ; External Interrupt Request 2
+.org 25
+ rcall isr ; Watchdog Timeout Interrupt
+.org 26
+ rcall isr ; EEPROM Ready
+.org 27
+ rcall isr ; Timer Counter 0 Compare Match B
+.org 28
+ rcall isr ; External Interrupt Request 3
+.org 29
+ rcall isr ;
+.org 30
+ rcall isr ;
+.org 31
+ rcall isr ; Store Program Memory Read
+.equ INTVECTORS = 32
+.nooverlap
+
+; compatability layer (maybe empty)
+.equ EEPE = EEWE
+.equ EEMPE = EEMWE
+
+; controller data area, environment query mcu-info
+mcu_info:
+mcu_ramsize:
+ .dw 512
+mcu_eepromsize:
+ .dw 512
+mcu_maxdp:
+ .dw 6144
+mcu_numints:
+ .dw 32
+mcu_name:
+ .dw 8
+ .db "AT90PWM1"
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/at90pwm1/device.inc b/amforth-6.5/avr8/devices/at90pwm1/device.inc
new file mode 100644
index 0000000..0b15f67
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90pwm1/device.inc
@@ -0,0 +1,1143 @@
+; Partname: AT90PWM1
+; generated automatically, no not edit
+
+.if WANT_PORTB == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw 37
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw 36
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw 35
+
+.endif
+.if WANT_PORTD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw 43
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw 42
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw 41
+
+.endif
+.if WANT_BOOT_LOAD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control Register
+VE_SPMCSR:
+ .dw $ff06
+ .db "SPMCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCSR
+XT_SPMCSR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCSR:
+ .dw 87
+
+.endif
+.if WANT_PSC0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 0 Input Capture Register
+VE_PICR0:
+ .dw $ff05
+ .db "PICR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PICR0
+XT_PICR0:
+ .dw PFA_DOVARIABLE
+PFA_PICR0:
+ .dw 222
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 0 Input B Control
+VE_PFRC0B:
+ .dw $ff06
+ .db "PFRC0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PFRC0B
+XT_PFRC0B:
+ .dw PFA_DOVARIABLE
+PFA_PFRC0B:
+ .dw 221
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 0 Input A Control
+VE_PFRC0A:
+ .dw $ff06
+ .db "PFRC0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PFRC0A
+XT_PFRC0A:
+ .dw PFA_DOVARIABLE
+PFA_PFRC0A:
+ .dw 220
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 0 Control Register
+VE_PCTL0:
+ .dw $ff05
+ .db "PCTL0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCTL0
+XT_PCTL0:
+ .dw PFA_DOVARIABLE
+PFA_PCTL0:
+ .dw 219
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 0 Configuration Register
+VE_PCNF0:
+ .dw $ff05
+ .db "PCNF0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCNF0
+XT_PCNF0:
+ .dw PFA_DOVARIABLE
+PFA_PCNF0:
+ .dw 218
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare RB Register
+VE_OCR0RB:
+ .dw $ff06
+ .db "OCR0RB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0RB
+XT_OCR0RB:
+ .dw PFA_DOVARIABLE
+PFA_OCR0RB:
+ .dw 216
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare SB Register
+VE_OCR0SB:
+ .dw $ff06
+ .db "OCR0SB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0SB
+XT_OCR0SB:
+ .dw PFA_DOVARIABLE
+PFA_OCR0SB:
+ .dw 214
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare RA Register
+VE_OCR0RA:
+ .dw $ff06
+ .db "OCR0RA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0RA
+XT_OCR0RA:
+ .dw PFA_DOVARIABLE
+PFA_OCR0RA:
+ .dw 212
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare SA Register
+VE_OCR0SA:
+ .dw $ff06
+ .db "OCR0SA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0SA
+XT_OCR0SA:
+ .dw PFA_DOVARIABLE
+PFA_OCR0SA:
+ .dw 210
+; ( -- addr ) System Constant
+; R( -- )
+; PSC0 Synchro and Output Configuration
+VE_PSOC0:
+ .dw $ff05
+ .db "PSOC0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PSOC0
+XT_PSOC0:
+ .dw PFA_DOVARIABLE
+PFA_PSOC0:
+ .dw 208
+; ( -- addr ) System Constant
+; R( -- )
+; PSC0 Interrupt Mask Register
+VE_PIM0:
+ .dw $ff04
+ .db "PIM0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIM0
+XT_PIM0:
+ .dw PFA_DOVARIABLE
+PFA_PIM0:
+ .dw 161
+; ( -- addr ) System Constant
+; R( -- )
+; PSC0 Interrupt Flag Register
+VE_PIFR0:
+ .dw $ff05
+ .db "PIFR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIFR0
+XT_PIFR0:
+ .dw PFA_DOVARIABLE
+PFA_PIFR0:
+ .dw 160
+
+.endif
+.if WANT_PSC2 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 2 Input Capture Register
+VE_PICR2:
+ .dw $ff05
+ .db "PICR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PICR2
+XT_PICR2:
+ .dw PFA_DOVARIABLE
+PFA_PICR2:
+ .dw 254
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 2 Input B Control
+VE_PFRC2B:
+ .dw $ff06
+ .db "PFRC2B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PFRC2B
+XT_PFRC2B:
+ .dw PFA_DOVARIABLE
+PFA_PFRC2B:
+ .dw 253
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 2 Input B Control
+VE_PFRC2A:
+ .dw $ff06
+ .db "PFRC2A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PFRC2A
+XT_PFRC2A:
+ .dw PFA_DOVARIABLE
+PFA_PFRC2A:
+ .dw 252
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 2 Control Register
+VE_PCTL2:
+ .dw $ff05
+ .db "PCTL2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCTL2
+XT_PCTL2:
+ .dw PFA_DOVARIABLE
+PFA_PCTL2:
+ .dw 251
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 2 Configuration Register
+VE_PCNF2:
+ .dw $ff05
+ .db "PCNF2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCNF2
+XT_PCNF2:
+ .dw PFA_DOVARIABLE
+PFA_PCNF2:
+ .dw 250
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare RB Register
+VE_OCR2RB:
+ .dw $ff06
+ .db "OCR2RB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2RB
+XT_OCR2RB:
+ .dw PFA_DOVARIABLE
+PFA_OCR2RB:
+ .dw 248
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare SB Register
+VE_OCR2SB:
+ .dw $ff06
+ .db "OCR2SB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2SB
+XT_OCR2SB:
+ .dw PFA_DOVARIABLE
+PFA_OCR2SB:
+ .dw 246
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare RA Register
+VE_OCR2RA:
+ .dw $ff06
+ .db "OCR2RA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2RA
+XT_OCR2RA:
+ .dw PFA_DOVARIABLE
+PFA_OCR2RA:
+ .dw 244
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare SA Register
+VE_OCR2SA:
+ .dw $ff06
+ .db "OCR2SA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2SA
+XT_OCR2SA:
+ .dw PFA_DOVARIABLE
+PFA_OCR2SA:
+ .dw 242
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 2 Output Matrix
+VE_POM2:
+ .dw $ff04
+ .db "POM2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_POM2
+XT_POM2:
+ .dw PFA_DOVARIABLE
+PFA_POM2:
+ .dw 241
+; ( -- addr ) System Constant
+; R( -- )
+; PSC2 Synchro and Output Configuration
+VE_PSOC2:
+ .dw $ff05
+ .db "PSOC2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PSOC2
+XT_PSOC2:
+ .dw PFA_DOVARIABLE
+PFA_PSOC2:
+ .dw 240
+; ( -- addr ) System Constant
+; R( -- )
+; PSC2 Interrupt Mask Register
+VE_PIM2:
+ .dw $ff04
+ .db "PIM2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIM2
+XT_PIM2:
+ .dw PFA_DOVARIABLE
+PFA_PIM2:
+ .dw 165
+; ( -- addr ) System Constant
+; R( -- )
+; PSC2 Interrupt Flag Register
+VE_PIFR2:
+ .dw $ff05
+ .db "PIFR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIFR2
+XT_PIFR2:
+ .dw PFA_DOVARIABLE
+PFA_PIFR2:
+ .dw 164
+
+.endif
+.if WANT_CPU == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw 95
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer
+VE_SP:
+ .dw $ff02
+ .db "SP"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SP
+XT_SP:
+ .dw PFA_DOVARIABLE
+PFA_SP:
+ .dw 93
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw 85
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Status Register
+VE_MCUSR:
+ .dw $ff05
+ .db "MCUSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUSR
+XT_MCUSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUSR:
+ .dw 84
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Calibration Value
+VE_OSCCAL:
+ .dw $ff06
+ .db "OSCCAL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSCCAL
+XT_OSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_OSCCAL:
+ .dw 102
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_CLKPR:
+ .dw $ff05
+ .db "CLKPR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKPR
+XT_CLKPR:
+ .dw PFA_DOVARIABLE
+PFA_CLKPR:
+ .dw 97
+; ( -- addr ) System Constant
+; R( -- )
+; Sleep Mode Control Register
+VE_SMCR:
+ .dw $ff04
+ .db "SMCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SMCR
+XT_SMCR:
+ .dw PFA_DOVARIABLE
+PFA_SMCR:
+ .dw 83
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 3
+VE_GPIOR3:
+ .dw $ff06
+ .db "GPIOR3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR3
+XT_GPIOR3:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR3:
+ .dw 59
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 2
+VE_GPIOR2:
+ .dw $ff06
+ .db "GPIOR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR2
+XT_GPIOR2:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR2:
+ .dw 58
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 1
+VE_GPIOR1:
+ .dw $ff06
+ .db "GPIOR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR1
+XT_GPIOR1:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR1:
+ .dw 57
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 0
+VE_GPIOR0:
+ .dw $ff06
+ .db "GPIOR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR0
+XT_GPIOR0:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR0:
+ .dw 62
+; ( -- addr ) System Constant
+; R( -- )
+; PLL Control And Status Register
+VE_PLLCSR:
+ .dw $ff06
+ .db "PLLCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PLLCSR
+XT_PLLCSR:
+ .dw PFA_DOVARIABLE
+PFA_PLLCSR:
+ .dw 73
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register
+VE_PRR:
+ .dw $ff03
+ .db "PRR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR
+XT_PRR:
+ .dw PFA_DOVARIABLE
+PFA_PRR:
+ .dw 100
+
+.endif
+.if WANT_PORTE == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port E Data Register
+VE_PORTE:
+ .dw $ff05
+ .db "PORTE",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTE
+XT_PORTE:
+ .dw PFA_DOVARIABLE
+PFA_PORTE:
+ .dw 46
+; ( -- addr ) System Constant
+; R( -- )
+; Port E Data Direction Register
+VE_DDRE:
+ .dw $ff04
+ .db "DDRE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRE
+XT_DDRE:
+ .dw PFA_DOVARIABLE
+PFA_DDRE:
+ .dw 45
+; ( -- addr ) System Constant
+; R( -- )
+; Port E Input Pins
+VE_PINE:
+ .dw $ff04
+ .db "PINE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINE
+XT_PINE:
+ .dw PFA_DOVARIABLE
+PFA_PINE:
+ .dw 44
+
+.endif
+.if WANT_TIMER_COUNTER_0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Mask Register
+VE_TIMSK0:
+ .dw $ff06
+ .db "TIMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK0
+XT_TIMSK0:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK0:
+ .dw 110
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Flag register
+VE_TIFR0:
+ .dw $ff05
+ .db "TIFR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR0
+XT_TIFR0:
+ .dw PFA_DOVARIABLE
+PFA_TIFR0:
+ .dw 53
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register A
+VE_TCCR0A:
+ .dw $ff06
+ .db "TCCR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0A
+XT_TCCR0A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0A:
+ .dw 68
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register B
+VE_TCCR0B:
+ .dw $ff06
+ .db "TCCR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0B
+XT_TCCR0B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0B:
+ .dw 69
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw 70
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0A:
+ .dw $ff05
+ .db "OCR0A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0A
+XT_OCR0A:
+ .dw PFA_DOVARIABLE
+PFA_OCR0A:
+ .dw 71
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0B:
+ .dw $ff05
+ .db "OCR0B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0B
+XT_OCR0B:
+ .dw PFA_DOVARIABLE
+PFA_OCR0B:
+ .dw 72
+; ( -- addr ) System Constant
+; R( -- )
+; General Timer/Counter Control Register
+VE_GTCCR:
+ .dw $ff05
+ .db "GTCCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GTCCR
+XT_GTCCR:
+ .dw PFA_DOVARIABLE
+PFA_GTCCR:
+ .dw 67
+
+.endif
+.if WANT_TIMER_COUNTER_1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Mask Register
+VE_TIMSK1:
+ .dw $ff06
+ .db "TIMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK1
+XT_TIMSK1:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK1:
+ .dw 111
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Flag register
+VE_TIFR1:
+ .dw $ff05
+ .db "TIFR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR1
+XT_TIFR1:
+ .dw PFA_DOVARIABLE
+PFA_TIFR1:
+ .dw 54
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw 128
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw 129
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register C
+VE_TCCR1C:
+ .dw $ff06
+ .db "TCCR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1C
+XT_TCCR1C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1C:
+ .dw 130
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Bytes
+VE_TCNT1:
+ .dw $ff05
+ .db "TCNT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1
+XT_TCNT1:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1:
+ .dw 132
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register Bytes
+VE_OCR1A:
+ .dw $ff05
+ .db "OCR1A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1A
+XT_OCR1A:
+ .dw PFA_DOVARIABLE
+PFA_OCR1A:
+ .dw 136
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register Bytes
+VE_OCR1B:
+ .dw $ff05
+ .db "OCR1B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1B
+XT_OCR1B:
+ .dw PFA_DOVARIABLE
+PFA_OCR1B:
+ .dw 138
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Bytes
+VE_ICR1:
+ .dw $ff04
+ .db "ICR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1
+XT_ICR1:
+ .dw PFA_DOVARIABLE
+PFA_ICR1:
+ .dw 134
+
+.endif
+.if WANT_AD_CONVERTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC multiplexer Selection Register
+VE_ADMUX:
+ .dw $ff05
+ .db "ADMUX",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADMUX
+XT_ADMUX:
+ .dw PFA_DOVARIABLE
+PFA_ADMUX:
+ .dw 124
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register
+VE_ADCSRA:
+ .dw $ff06
+ .db "ADCSRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRA
+XT_ADCSRA:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRA:
+ .dw 122
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register Bytes
+VE_ADC:
+ .dw $ff03
+ .db "ADC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADC
+XT_ADC:
+ .dw PFA_DOVARIABLE
+PFA_ADC:
+ .dw 120
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Control and Status Register B
+VE_ADCSRB:
+ .dw $ff06
+ .db "ADCSRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRB
+XT_ADCSRB:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRB:
+ .dw 123
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 0
+VE_DIDR0:
+ .dw $ff05
+ .db "DIDR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR0
+XT_DIDR0:
+ .dw PFA_DOVARIABLE
+PFA_DIDR0:
+ .dw 126
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 0
+VE_DIDR1:
+ .dw $ff05
+ .db "DIDR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR1
+XT_DIDR1:
+ .dw PFA_DOVARIABLE
+PFA_DIDR1:
+ .dw 127
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_AMP0CSR:
+ .dw $ff07
+ .db "AMP0CSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_AMP0CSR
+XT_AMP0CSR:
+ .dw PFA_DOVARIABLE
+PFA_AMP0CSR:
+ .dw 118
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_AMP1CSR:
+ .dw $ff07
+ .db "AMP1CSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_AMP1CSR
+XT_AMP1CSR:
+ .dw PFA_DOVARIABLE
+PFA_AMP1CSR:
+ .dw 119
+
+.endif
+.if WANT_SPI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR:
+ .dw $ff04
+ .db "SPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR
+XT_SPCR:
+ .dw PFA_DOVARIABLE
+PFA_SPCR:
+ .dw 76
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR:
+ .dw $ff04
+ .db "SPSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR
+XT_SPSR:
+ .dw PFA_DOVARIABLE
+PFA_SPSR:
+ .dw 77
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR:
+ .dw $ff04
+ .db "SPDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR
+XT_SPDR:
+ .dw PFA_DOVARIABLE
+PFA_SPDR:
+ .dw 78
+
+.endif
+.if WANT_WATCHDOG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCSR:
+ .dw $ff06
+ .db "WDTCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCSR
+XT_WDTCSR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCSR:
+ .dw 96
+
+.endif
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register A
+VE_EICRA:
+ .dw $ff05
+ .db "EICRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRA
+XT_EICRA:
+ .dw PFA_DOVARIABLE
+PFA_EICRA:
+ .dw 105
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Mask Register
+VE_EIMSK:
+ .dw $ff05
+ .db "EIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIMSK
+XT_EIMSK:
+ .dw PFA_DOVARIABLE
+PFA_EIMSK:
+ .dw 61
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Flag Register
+VE_EIFR:
+ .dw $ff04
+ .db "EIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIFR
+XT_EIFR:
+ .dw PFA_DOVARIABLE
+PFA_EIFR:
+ .dw 60
+
+.endif
+.if WANT_EEPROM == 1
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Read/Write Access Bytes
+VE_EEAR:
+ .dw $ff04
+ .db "EEAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEAR
+XT_EEAR:
+ .dw PFA_DOVARIABLE
+PFA_EEAR:
+ .dw 65
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw 64
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw 63
+
+.endif
+.if WANT_ANALOG_COMPARATOR == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator 0 Control Register
+VE_AC0CON:
+ .dw $ff06
+ .db "AC0CON"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_AC0CON
+XT_AC0CON:
+ .dw PFA_DOVARIABLE
+PFA_AC0CON:
+ .dw 173
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator 2 Control Register
+VE_AC2CON:
+ .dw $ff06
+ .db "AC2CON"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_AC2CON
+XT_AC2CON:
+ .dw PFA_DOVARIABLE
+PFA_AC2CON:
+ .dw 175
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw 80
+
+.endif
+.if WANT_PSC1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 1 Input Capture Register
+VE_PICR1:
+ .dw $ff05
+ .db "PICR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PICR1
+XT_PICR1:
+ .dw PFA_DOVARIABLE
+PFA_PICR1:
+ .dw 238
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 1 Input B Control
+VE_PFRC1B:
+ .dw $ff06
+ .db "PFRC1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PFRC1B
+XT_PFRC1B:
+ .dw PFA_DOVARIABLE
+PFA_PFRC1B:
+ .dw 237
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 1 Input B Control
+VE_PFRC1A:
+ .dw $ff06
+ .db "PFRC1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PFRC1A
+XT_PFRC1A:
+ .dw PFA_DOVARIABLE
+PFA_PFRC1A:
+ .dw 236
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 1 Control Register
+VE_PCTL1:
+ .dw $ff05
+ .db "PCTL1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCTL1
+XT_PCTL1:
+ .dw PFA_DOVARIABLE
+PFA_PCTL1:
+ .dw 235
+; ( -- addr ) System Constant
+; R( -- )
+; PSC1 Synchro and Output Configuration
+VE_PSOC1:
+ .dw $ff05
+ .db "PSOC1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PSOC1
+XT_PSOC1:
+ .dw PFA_DOVARIABLE
+PFA_PSOC1:
+ .dw 224
+
+.endif
diff --git a/amforth-6.5/avr8/devices/at90pwm1/device.py b/amforth-6.5/avr8/devices/at90pwm1/device.py
new file mode 100644
index 0000000..a9cd0bd
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90pwm1/device.py
@@ -0,0 +1,404 @@
+# Generated Automatically
+
+# Partname AT90PWM1
+
+MCUREGS = {
+# Interrupt Vectors
+ 'PSC2_CAPTAddr' : '#2', # PSC2 Capture Event
+ 'PSC2_ECAddr' : '#4', # PSC2 End Cycle
+ 'PSC1_CAPTAddr' : '#6', # PSC1 Capture Event
+ 'PSC1_ECAddr' : '#8', # PSC1 End Cycle
+ 'PSC0_CAPTAddr' : '#10', # PSC0 Capture Event
+ 'PSC0_ECAddr' : '#12', # PSC0 End Cycle
+ 'ANALOG_COMP_0Addr' : '#14', # Analog Comparator 0
+ 'ANALOG_COMP_1Addr' : '#16', # Analog Comparator 1
+ 'ANALOG_COMP_2Addr' : '#18', # Analog Comparator 2
+ 'INT0Addr' : '#20', # External Interrupt Request 0
+ 'TIMER1_CAPTAddr' : '#22', # Timer/Counter1 Capture Event
+ 'TIMER1_COMPAAddr' : '#24', # Timer/Counter1 Compare Match A
+ 'TIMER1_COMPBAddr' : '#26', # Timer/Counter Compare Match B
+ 'RESERVED15Addr' : '#28', #
+ 'TIMER1_OVFAddr' : '#30', # Timer/Counter1 Overflow
+ 'TIMER0_COMP_AAddr' : '#32', # Timer/Counter0 Compare Match A
+ 'TIMER0_OVFAddr' : '#34', # Timer/Counter0 Overflow
+ 'ADCAddr' : '#36', # ADC Conversion Complete
+ 'INT1Addr' : '#38', # External Interrupt Request 1
+ 'SPI_STCAddr' : '#40', # SPI Serial Transfer Complete
+ 'USART_RXAddr' : '#42', # USART, Rx Complete
+ 'USART_UDREAddr' : '#44', # USART Data Register Empty
+ 'USART_TXAddr' : '#46', # USART, Tx Complete
+ 'INT2Addr' : '#48', # External Interrupt Request 2
+ 'WDTAddr' : '#50', # Watchdog Timeout Interrupt
+ 'EE_READYAddr' : '#52', # EEPROM Ready
+ 'TIMER0_COMPBAddr' : '#54', # Timer Counter 0 Compare Match B
+ 'INT3Addr' : '#56', # External Interrupt Request 3
+ 'RESERVED30Addr' : '#58', #
+ 'RESERVED31Addr' : '#60', #
+ 'SPM_READYAddr' : '#62', # Store Program Memory Read
+
+# Module PORTB
+ 'PORTB' : '$25', # Port B Data Register
+ 'DDRB' : '$24', # Port B Data Direction Register
+ 'PINB' : '$23', # Port B Input Pins
+
+# Module PORTD
+ 'PORTD' : '$2b', # Port D Data Register
+ 'DDRD' : '$2a', # Port D Data Direction Register
+ 'PIND' : '$29', # Port D Input Pins
+
+# Module BOOT_LOAD
+ 'SPMCSR' : '$57', # Store Program Memory Control R
+ 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
+ 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
+ 'SPMCSR_RWWSRE': '$10', # Read While Write section read
+ 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
+ 'SPMCSR_PGWRT': '$4', # Page Write
+ 'SPMCSR_PGERS': '$2', # Page Erase
+ 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
+
+# Module PSC0
+ 'PICR0' : '$de', # PSC 0 Input Capture Register
+ 'PFRC0B' : '$dd', # PSC 0 Input B Control
+ 'PFRC0B_PCAE0B': '$80', # PSC 0 Capture Enable Input Par
+ 'PFRC0B_PISEL0B': '$40', # PSC 0 Input Select for Part B
+ 'PFRC0B_PELEV0B': '$20', # PSC 0 Edge Level Selector on I
+ 'PFRC0B_PFLTE0B': '$10', # PSC 0 Filter Enable on Input P
+ 'PFRC0B_PRFM0B': '$f', # PSC 0 Retrigger and Fault Mode
+ 'PFRC0A' : '$dc', # PSC 0 Input A Control
+ 'PFRC0A_PCAE0A': '$80', # PSC 0 Capture Enable Input Par
+ 'PFRC0A_PISEL0A': '$40', # PSC 0 Input Select for Part A
+ 'PFRC0A_PELEV0A': '$20', # PSC 0 Edge Level Selector on I
+ 'PFRC0A_PFLTE0A': '$10', # PSC 0 Filter Enable on Input P
+ 'PFRC0A_PRFM0A': '$f', # PSC 0 Retrigger and Fault Mode
+ 'PCTL0' : '$db', # PSC 0 Control Register
+ 'PCTL0_PPRE0': '$c0', # PSC 0 Prescaler Selects
+ 'PCTL0_PBFM0': '$20', # PSC 0 Balance Flank Width Modu
+ 'PCTL0_PAOC0B': '$10', # PSC 0 Asynchronous Output Cont
+ 'PCTL0_PAOC0A': '$8', # PSC 0 Asynchronous Output Cont
+ 'PCTL0_PARUN0': '$4', # PSC0 Auto Run
+ 'PCTL0_PCCYC0': '$2', # PSC0 Complete Cycle
+ 'PCTL0_PRUN0': '$1', # PSC 0 Run
+ 'PCNF0' : '$da', # PSC 0 Configuration Register
+ 'PCNF0_PFIFTY0': '$80', # PSC 0 Fifty
+ 'PCNF0_PALOCK0': '$40', # PSC 0 Autolock
+ 'PCNF0_PLOCK0': '$20', # PSC 0 Lock
+ 'PCNF0_PMODE0': '$18', # PSC 0 Mode
+ 'PCNF0_POP0': '$4', # PSC 0 Output Polarity
+ 'PCNF0_PCLKSEL0': '$2', # PSC 0 Input Clock Select
+ 'OCR0RB' : '$d8', # Output Compare RB Register
+ 'OCR0SB' : '$d6', # Output Compare SB Register
+ 'OCR0RA' : '$d4', # Output Compare RA Register
+ 'OCR0SA' : '$d2', # Output Compare SA Register
+ 'PSOC0' : '$d0', # PSC0 Synchro and Output Config
+ 'PSOC0_PSYNC0': '$30', # Synchronization Out for ADC Se
+ 'PSOC0_POEN0B': '$4', # PSCOUT01 Output Enable
+ 'PSOC0_POEN0A': '$1', # PSCOUT00 Output Enable
+ 'PIM0' : '$a1', # PSC0 Interrupt Mask Register
+ 'PIM0_PSEIE0': '$20', # PSC 0 Synchro Error Interrupt
+ 'PIM0_PEVE0B': '$10', # External Event B Interrupt Ena
+ 'PIM0_PEVE0A': '$8', # External Event A Interrupt Ena
+ 'PIM0_PEOPE0': '$1', # End of Cycle Interrupt Enable
+ 'PIFR0' : '$a0', # PSC0 Interrupt Flag Register
+ 'PIFR0_PSEI0': '$20', # PSC 0 Synchro Error Interrupt
+ 'PIFR0_PEV0B': '$10', # External Event B Interrupt
+ 'PIFR0_PEV0A': '$8', # External Event A Interrupt
+ 'PIFR0_PRN0': '$6', # Ramp Number
+ 'PIFR0_PEOP0': '$1', # End of PSC0 Interrupt
+
+# Module PSC2
+ 'PICR2' : '$fe', # PSC 2 Input Capture Register
+ 'PFRC2B' : '$fd', # PSC 2 Input B Control
+ 'PFRC2B_PCAE2B': '$80', # PSC 2 Capture Enable Input Par
+ 'PFRC2B_PISEL2B': '$40', # PSC 2 Input Select for Part B
+ 'PFRC2B_PELEV2B': '$20', # PSC 2 Edge Level Selector on I
+ 'PFRC2B_PFLTE2B': '$10', # PSC 2 Filter Enable on Input P
+ 'PFRC2B_PRFM2B': '$f', # PSC 2 Retrigger and Fault Mode
+ 'PFRC2A' : '$fc', # PSC 2 Input B Control
+ 'PFRC2A_PCAE2A': '$80', # PSC 2 Capture Enable Input Par
+ 'PFRC2A_PISEL2A': '$40', # PSC 2 Input Select for Part A
+ 'PFRC2A_PELEV2A': '$20', # PSC 2 Edge Level Selector on I
+ 'PFRC2A_PFLTE2A': '$10', # PSC 2 Filter Enable on Input P
+ 'PFRC2A_PRFM2A': '$f', # PSC 2 Retrigger and Fault Mode
+ 'PCTL2' : '$fb', # PSC 2 Control Register
+ 'PCTL2_PPRE2': '$c0', # PSC 2 Prescaler Selects
+ 'PCTL2_PBFM2': '$20', # Balance Flank Width Modulation
+ 'PCTL2_PAOC2B': '$10', # PSC 2 Asynchronous Output Cont
+ 'PCTL2_PAOC2A': '$8', # PSC 2 Asynchronous Output Cont
+ 'PCTL2_PARUN2': '$4', # PSC2 Auto Run
+ 'PCTL2_PCCYC2': '$2', # PSC2 Complete Cycle
+ 'PCTL2_PRUN2': '$1', # PSC 2 Run
+ 'PCNF2' : '$fa', # PSC 2 Configuration Register
+ 'PCNF2_PFIFTY2': '$80', # PSC 2 Fifty
+ 'PCNF2_PALOCK2': '$40', # PSC 2 Autolock
+ 'PCNF2_PLOCK2': '$20', # PSC 2 Lock
+ 'PCNF2_PMODE2': '$18', # PSC 2 Mode
+ 'PCNF2_POP2': '$4', # PSC 2 Output Polarity
+ 'PCNF2_PCLKSEL2': '$2', # PSC 2 Input Clock Select
+ 'PCNF2_POME2': '$1', # PSC 2 Output Matrix Enable
+ 'OCR2RB' : '$f8', # Output Compare RB Register
+ 'OCR2SB' : '$f6', # Output Compare SB Register
+ 'OCR2RA' : '$f4', # Output Compare RA Register
+ 'OCR2SA' : '$f2', # Output Compare SA Register
+ 'POM2' : '$f1', # PSC 2 Output Matrix
+ 'POM2_POMV2B': '$f0', # Output Matrix Output B Ramps
+ 'POM2_POMV2A': '$f', # Output Matrix Output A Ramps
+ 'PSOC2' : '$f0', # PSC2 Synchro and Output Config
+ 'PSOC2_POS2': '$c0', # PSC 2 Output 23 Select
+ 'PSOC2_PSYNC2_': '$30', # Synchronization Out for ADC Se
+ 'PSOC2_POEN2D': '$8', # PSCOUT23 Output Enable
+ 'PSOC2_POEN2B': '$4', # PSCOUT21 Output Enable
+ 'PSOC2_POEN2C': '$2', # PSCOUT22 Output Enable
+ 'PSOC2_POEN2A': '$1', # PSCOUT20 Output Enable
+ 'PIM2' : '$a5', # PSC2 Interrupt Mask Register
+ 'PIM2_PSEIE2': '$20', # PSC 2 Synchro Error Interrupt
+ 'PIM2_PEVE2B': '$10', # External Event B Interrupt Ena
+ 'PIM2_PEVE2A': '$8', # External Event A Interrupt Ena
+ 'PIM2_PEOPE2': '$1', # End of Cycle Interrupt Enable
+ 'PIFR2' : '$a4', # PSC2 Interrupt Flag Register
+ 'PIFR2_PSEI2': '$20', # PSC 2 Synchro Error Interrupt
+ 'PIFR2_PEV2B': '$10', # External Event B Interrupt
+ 'PIFR2_PEV2A': '$8', # External Event A Interrupt
+ 'PIFR2_PRN2': '$6', # Ramp Number
+ 'PIFR2_PEOP2': '$1', # End of PSC2 Interrupt
+
+# Module CPU
+ 'SREG' : '$5f', # Status Register
+ 'SREG_I': '$80', # Global Interrupt Enable
+ 'SREG_T': '$40', # Bit Copy Storage
+ 'SREG_H': '$20', # Half Carry Flag
+ 'SREG_S': '$10', # Sign Bit
+ 'SREG_V': '$8', # Two's Complement Overflow Flag
+ 'SREG_N': '$4', # Negative Flag
+ 'SREG_Z': '$2', # Zero Flag
+ 'SREG_C': '$1', # Carry Flag
+ 'SP' : '$5d', # Stack Pointer
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_SPIPS': '$80', # SPI Pin Select
+ 'MCUCR_PUD': '$10', # Pull-up disable
+ 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
+ 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
+ 'MCUSR_BORF': '$4', # Brown-out Reset Flag
+ 'MCUSR_EXTRF': '$2', # External Reset Flag
+ 'MCUSR_PORF': '$1', # Power-on reset flag
+ 'OSCCAL' : '$66', # Oscillator Calibration Value
+ 'CLKPR' : '$61', #
+ 'CLKPR_CLKPCE': '$80', #
+ 'CLKPR_CLKPS': '$f', #
+ 'SMCR' : '$53', # Sleep Mode Control Register
+ 'SMCR_SM': '$e', # Sleep Mode Select bits
+ 'SMCR_SE': '$1', # Sleep Enable
+ 'GPIOR3' : '$3b', # General Purpose IO Register 3
+ 'GPIOR3_GPIOR': '$ff', # General Purpose IO Register 3
+ 'GPIOR2' : '$3a', # General Purpose IO Register 2
+ 'GPIOR2_GPIOR': '$ff', # General Purpose IO Register 2
+ 'GPIOR1' : '$39', # General Purpose IO Register 1
+ 'GPIOR1_GPIOR': '$ff', # General Purpose IO Register 1
+ 'GPIOR0' : '$3e', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR07': '$80', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR06': '$40', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR05': '$20', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR04': '$10', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR03': '$8', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR02': '$4', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR01': '$2', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR00': '$1', # General Purpose IO Register 0
+ 'PLLCSR' : '$49', # PLL Control And Status Registe
+ 'PLLCSR_PLLF': '$4', # PLL Factor
+ 'PLLCSR_PLLE': '$2', # PLL Enable
+ 'PLLCSR_PLOCK': '$1', # PLL Lock Detector
+ 'PRR' : '$64', # Power Reduction Register
+ 'PRR_PRPSC': '$e0', # Power Reduction PSC2
+ 'PRR_PRTIM1': '$10', # Power Reduction Timer/Counter1
+ 'PRR_PRTIM0': '$8', # Power Reduction Timer/Counter0
+ 'PRR_PRSPI': '$4', # Power Reduction Serial Periphe
+ 'PRR_PRUSART0': '$2', # Power Reduction USART
+ 'PRR_PRADC': '$1', # Power Reduction ADC
+
+# Module PORTE
+ 'PORTE' : '$2e', # Port E Data Register
+ 'DDRE' : '$2d', # Port E Data Direction Register
+ 'PINE' : '$2c', # Port E Input Pins
+
+# Module TIMER_COUNTER_0
+ 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
+ 'TIMSK0_OCIE0B': '$4', # Timer/Counter0 Output Compare
+ 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
+ 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
+ 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
+ 'TIFR0_OCF0B': '$4', # Timer/Counter0 Output Compare
+ 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
+ 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
+ 'TCCR0A' : '$44', # Timer/Counter Control Registe
+ 'TCCR0A_COM0A': '$c0', # Compare Output Mode, Phase Cor
+ 'TCCR0A_COM0B': '$30', # Compare Output Mode, Fast PWm
+ 'TCCR0A_WGM0': '$3', # Waveform Generation Mode
+ 'TCCR0B' : '$45', # Timer/Counter Control Register
+ 'TCCR0B_FOC0A': '$80', # Force Output Compare A
+ 'TCCR0B_FOC0B': '$40', # Force Output Compare B
+ 'TCCR0B_WGM02': '$8', #
+ 'TCCR0B_CS0': '$7', # Clock Select
+ 'TCNT0' : '$46', # Timer/Counter0
+ 'OCR0A' : '$47', # Timer/Counter0 Output Compare
+ 'OCR0B' : '$48', # Timer/Counter0 Output Compare
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_ICPSEL1': '$40', # Timer1 Input Capture Selection
+ 'GTCCR_PSR10': '$1', # Prescaler Reset Timer/Counter1
+
+# Module TIMER_COUNTER_1
+ 'TIMSK1' : '$6f', # Timer/Counter Interrupt Mask R
+ 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
+ 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output CompareB
+ 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output CompareA
+ 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
+ 'TIFR1' : '$36', # Timer/Counter Interrupt Flag r
+ 'TIFR1_ICF1': '$20', # Input Capture Flag 1
+ 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
+ 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
+ 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
+ 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
+ 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
+ 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
+ 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
+ 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
+ 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
+ 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
+ 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
+ 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
+ 'TCCR1C' : '$82', # Timer/Counter1 Control Registe
+ 'TCCR1C_FOC1A': '$80', #
+ 'TCCR1C_FOC1B': '$40', #
+ 'TCNT1' : '$84', # Timer/Counter1 Bytes
+ 'OCR1A' : '$88', # Timer/Counter1 Output Compare
+ 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
+ 'ICR1' : '$86', # Timer/Counter1 Input Capture R
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSRSYNC': '$1', # Prescaler Reset Timer/Counter1
+
+# Module AD_CONVERTER
+ 'ADMUX' : '$7c', # The ADC multiplexer Selection
+ 'ADMUX_REFS': '$c0', # Reference Selection Bits
+ 'ADMUX_ADLAR': '$20', # Left Adjust Result
+ 'ADMUX_MUX': '$f', # Analog Channel and Gain Select
+ 'ADCSRA' : '$7a', # The ADC Control and Status reg
+ 'ADCSRA_ADEN': '$80', # ADC Enable
+ 'ADCSRA_ADSC': '$40', # ADC Start Conversion
+ 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
+ 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
+ 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
+ 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
+ 'ADC' : '$78', # ADC Data Register Bytes
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'DIDR0' : '$7e', # Digital Input Disable Register
+ 'DIDR1' : '$7f', # Digital Input Disable Register
+ 'DIDR1_ACMP0D': '$20', #
+ 'DIDR1_AMP0PD': '$10', #
+ 'DIDR1_AMP0ND': '$8', #
+ 'DIDR1_ADC10D': '$4', #
+ 'DIDR1_ADC9D': '$2', #
+ 'DIDR1_ADC8D': '$1', #
+ 'AMP0CSR' : '$76', #
+ 'AMP0CSR_AMP0EN': '$80', #
+ 'AMP0CSR_AMP0IS': '$40', #
+ 'AMP0CSR_AMP0G': '$30', #
+ 'AMP0CSR_AMP0TS': '$3', #
+ 'AMP1CSR' : '$77', #
+ 'AMP1CSR_AMP1EN': '$80', #
+ 'AMP1CSR_AMP1IS': '$40', #
+ 'AMP1CSR_AMP1G': '$30', #
+ 'AMP1CSR_AMP1TS': '$3', #
+
+# Module SPI
+ 'SPCR' : '$4c', # SPI Control Register
+ 'SPCR_SPIE': '$80', # SPI Interrupt Enable
+ 'SPCR_SPE': '$40', # SPI Enable
+ 'SPCR_DORD': '$20', # Data Order
+ 'SPCR_MSTR': '$10', # Master/Slave Select
+ 'SPCR_CPOL': '$8', # Clock polarity
+ 'SPCR_CPHA': '$4', # Clock Phase
+ 'SPCR_SPR': '$3', # SPI Clock Rate Selects
+ 'SPSR' : '$4d', # SPI Status Register
+ 'SPSR_SPIF': '$80', # SPI Interrupt Flag
+ 'SPSR_WCOL': '$40', # Write Collision Flag
+ 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
+ 'SPDR' : '$4e', # SPI Data Register
+
+# Module WATCHDOG
+ 'WDTCSR' : '$60', # Watchdog Timer Control Registe
+ 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
+ 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
+ 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
+ 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
+ 'WDTCSR_WDE': '$8', # Watch Dog Enable
+
+# Module EXTERNAL_INTERRUPT
+ 'EICRA' : '$69', # External Interrupt Control Reg
+ 'EICRA_ISC2': '$30', # External Interrupt Sense Contr
+ 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
+ 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
+ 'EIMSK' : '$3d', # External Interrupt Mask Regist
+ 'EIMSK_INT': '$7', # External Interrupt Request 2 E
+ 'EIFR' : '$3c', # External Interrupt Flag Regist
+ 'EIFR_INTF': '$7', # External Interrupt Flags
+
+# Module EEPROM
+ 'EEAR' : '$41', # EEPROM Read/Write Access Byte
+ 'EEDR' : '$40', # EEPROM Data Register
+ 'EECR' : '$3f', # EEPROM Control Register
+ 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
+ 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
+ 'EECR_EEWE': '$2', # EEPROM Write Enable
+ 'EECR_EERE': '$1', # EEPROM Read Enable
+
+# Module ANALOG_COMPARATOR
+ 'AC0CON' : '$ad', # Analog Comparator 0 Control Re
+ 'AC0CON_AC0EN': '$80', # Analog Comparator 0 Enable Bit
+ 'AC0CON_AC0IE': '$40', # Analog Comparator 0 Interrupt
+ 'AC0CON_AC0IS': '$30', # Analog Comparator 0 Interrupt
+ 'AC0CON_AC0M': '$7', # Analog Comparator 0 Multiplexe
+ 'AC2CON' : '$af', # Analog Comparator 2 Control Re
+ 'AC2CON_AC2EN': '$80', # Analog Comparator 2 Enable Bit
+ 'AC2CON_AC2IE': '$40', # Analog Comparator 2 Interrupt
+ 'AC2CON_AC2IS': '$30', # Analog Comparator 2 Interrupt
+ 'AC2CON_AC2M': '$7', # Analog Comparator 2 Multiplexe
+ 'ACSR' : '$50', # Analog Comparator Status Regis
+ 'ACSR_ACCKDIV': '$80', # Analog Comparator Clock Divide
+ 'ACSR_AC2IF': '$40', # Analog Comparator 2 Interrupt
+ 'ACSR_AC1IF': '$20', # Analog Comparator 1 Interrupt
+ 'ACSR_AC0IF': '$10', # Analog Comparator 0 Interrupt
+ 'ACSR_AC2O': '$4', # Analog Comparator 2 Output Bit
+ 'ACSR_AC1O': '$2', # Analog Comparator 1 Output Bit
+ 'ACSR_AC0O': '$1', # Analog Comparator 0 Output Bit
+
+# Module PSC1
+ 'PICR1' : '$ee', # PSC 1 Input Capture Register
+ 'PFRC1B' : '$ed', # PSC 1 Input B Control
+ 'PFRC1B_PCAE1B': '$80', # PSC 1 Capture Enable Input Par
+ 'PFRC1B_PISEL1B': '$40', # PSC 1 Input Select for Part B
+ 'PFRC1B_PELEV1B': '$20', # PSC 1 Edge Level Selector on I
+ 'PFRC1B_PFLTE1B': '$10', # PSC 1 Filter Enable on Input P
+ 'PFRC1B_PRFM1B': '$f', # PSC 1 Retrigger and Fault Mode
+ 'PFRC1A' : '$ec', # PSC 1 Input B Control
+ 'PFRC1A_PCAE1A': '$80', # PSC 1 Capture Enable Input Par
+ 'PFRC1A_PISEL1A': '$40', # PSC 1 Input Select for Part A
+ 'PFRC1A_PELEV1A': '$20', # PSC 1 Edge Level Selector on I
+ 'PFRC1A_PFLTE1A': '$10', # PSC 1 Filter Enable on Input P
+ 'PFRC1A_PRFM1A': '$f', # PSC 1 Retrigger and Fault Mode
+ 'PCTL1' : '$eb', # PSC 1 Control Register
+ 'PCTL1_PPRE1': '$c0', # PSC 1 Prescaler Selects
+ 'PCTL1_PBFM1': '$20', # Balance Flank Width Modulation
+ 'PCTL1_PAOC1B': '$10', # PSC 1 Asynchronous Output Cont
+ 'PCTL1_PAOC1A': '$8', # PSC 1 Asynchronous Output Cont
+ 'PCTL1_PARUN1': '$4', # PSC1 Auto Run
+ 'PCTL1_PCCYC1': '$2', # PSC1 Complete Cycle
+ 'PCTL1_PRUN1': '$1', # PSC 1 Run
+ 'PSOC1' : '$e0', # PSC1 Synchro and Output Config
+ 'PSOC1_PSYNC1_': '$30', # Synchronization Out for ADC Se
+ 'PSOC1_POEN1B': '$4', # PSCOUT11 Output Enable
+ 'PSOC1_POEN1A': '$1', # PSCOUT10 Output Enable
+
+ '__amforth_dummy':'0'
+}
diff --git a/amforth-6.5/avr8/devices/at90pwm1/words/no-jtag.asm b/amforth-6.5/avr8/devices/at90pwm1/words/no-jtag.asm
new file mode 100644
index 0000000..352a4bb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90pwm1/words/no-jtag.asm
@@ -0,0 +1,14 @@
+; ( -- )
+; ( -- )
+; MCU
+; disable jtag at runtime
+VE_NOJTAG:
+ .dw $FF05
+ .db "-jtag",0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOJTAG
+XT_NOJTAG:
+ .dw PFA_NOJTAG
+PFA_NOJTAG:
+
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/at90pwm1/words/no-wdt.asm b/amforth-6.5/avr8/devices/at90pwm1/words/no-wdt.asm
new file mode 100644
index 0000000..ff6ddd1
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90pwm1/words/no-wdt.asm
@@ -0,0 +1,34 @@
+; ( -- )
+; MCU
+; disable watch dog timer at runtime
+VE_NOWDT:
+ .dw $ff04
+ .db "-wdt"
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOWDT
+XT_NOWDT:
+ .dw PFA_NOWDT
+PFA_NOWDT:
+
+ in temp1,SREG
+ push temp1
+ ; Turn always off global interrupt.
+ cli
+ ; Reset Watchdog Timer
+ wdr
+ ; Clear WDRF in MCUSR
+ in temp1, MCUSR
+ andi temp1, (0xff & (0<<WDRF))
+ out MCUSR, temp1
+ ; Write logical one to WDCE and WDE
+ ; Keep old prescaler setting to prevent unintentional time-out
+ in_ temp1, WDTCSR
+ ori temp1, (1<<WDCE) | (1<<WDE)
+ out_ WDTCSR, temp1
+ ; Turn off WDT
+ ldi temp1, (0<<WDE)
+ out_ WDTCSR, temp1
+ ; restore status register
+ pop temp1
+ out SREG,temp1
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/at90pwm1/words/sleep.asm b/amforth-6.5/avr8/devices/at90pwm1/words/sleep.asm
new file mode 100644
index 0000000..256249c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90pwm1/words/sleep.asm
@@ -0,0 +1,19 @@
+; ( mode -- )
+; MCU
+; put the controller into the specified sleep mode
+VE_SLEEP:
+ .dw $ff05
+ .db "sleep", 0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_SLEEP
+XT_SLEEP:
+ .dw PFA_SLEEP
+PFA_SLEEP:
+ andi tosl, 7 ; leave only legal mode bits
+ lsl tosl ; move to correct location (bits 3-1)
+ ori tosl, 1 ; set the SE bit
+ out_ SMCR, tosl ; set the sleep config
+ sleep ; nighty-night
+ out_ SMCR, zerol ; 0 protects against accidental sleeps
+ loadtos ; pop argument from stack
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/at90pwm161/blocks/AD_CONVERTER.frt b/amforth-6.5/avr8/devices/at90pwm161/blocks/AD_CONVERTER.frt
new file mode 100644
index 0000000..9464801
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90pwm161/blocks/AD_CONVERTER.frt
@@ -0,0 +1,71 @@
+\ Generated automatically for at90pwm161
+\ #require bitnames.frt
+
+\ AD_CONVERTER
+$28 constant ADMUX \ The ADC multiplexer Selection
+ $c0 constant ADMUX_REFS \ Reference Selection Bits
+ 28 $c0 bitmask: ADMUX.REFS \ Reference Selection Bits
+ $20 constant ADMUX_ADLAR \ Left Adjust Result
+ 28 $20 bitmask: ADMUX.ADLAR \ Left Adjust Result
+ $f constant ADMUX_MUX \ Analog Channel and Gain Select
+ 28 $f bitmask: ADMUX.MUX \ Analog Channel and Gain Select
+$26 constant ADCSRA \ The ADC Control and Status reg
+ $80 constant ADCSRA_ADEN \ ADC Enable
+ 26 $80 bitmask: ADCSRA.ADEN \ ADC Enable
+ $40 constant ADCSRA_ADSC \ ADC Start Conversion
+ 26 $40 bitmask: ADCSRA.ADSC \ ADC Start Conversion
+ $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
+ 26 $20 bitmask: ADCSRA.ADATE \ ADC Auto Trigger Enable
+ $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
+ 26 $10 bitmask: ADCSRA.ADIF \ ADC Interrupt Flag
+ $8 constant ADCSRA_ADIE \ ADC Interrupt Enable
+ 26 $8 bitmask: ADCSRA.ADIE \ ADC Interrupt Enable
+ $7 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
+ 26 $7 bitmask: ADCSRA.ADPS \ ADC Prescaler Select Bits
+$4c constant ADC \ ADC Data Register Bytes
+$27 constant ADCSRB \ ADC Control and Status Registe
+ $80 constant ADCSRB_ADHSM \ ADC High Speed Mode
+ 27 $80 bitmask: ADCSRB.ADHSM \ ADC High Speed Mode
+ $40 constant ADCSRB_ADNCDIS \ ADC Noise Canceller Disable
+ 27 $40 bitmask: ADCSRB.ADNCDIS \ ADC Noise Canceller Disable
+ $10 constant ADCSRB_ADSSEN \ ADC Single Shot Enable on PSC'
+ 27 $10 bitmask: ADCSRB.ADSSEN \ ADC Single Shot Enable on PSC'
+ $f constant ADCSRB_ADTS \ ADC Auto Trigger Sources
+ 27 $f bitmask: ADCSRB.ADTS \ ADC Auto Trigger Sources
+$77 constant DIDR0 \ Digital Input Disable Register
+ $80 constant DIDR0_ADC7D \
+ 77 $80 bitmask: DIDR0.ADC7D \
+ $40 constant DIDR0_ADC6D \ ADC7 Digital input Disable
+ 77 $40 bitmask: DIDR0.ADC6D \ ADC7 Digital input Disable
+ $20 constant DIDR0_ADC5D \ ADC5 Digital input Disable
+ 77 $20 bitmask: DIDR0.ADC5D \ ADC5 Digital input Disable
+ $10 constant DIDR0_ADC4D \ ADC4 Digital input Disable
+ 77 $10 bitmask: DIDR0.ADC4D \ ADC4 Digital input Disable
+ $8 constant DIDR0_ADC3D \ ADC3 Digital input Disable
+ 77 $8 bitmask: DIDR0.ADC3D \ ADC3 Digital input Disable
+ $4 constant DIDR0_ADC2D \ ADC2 Digital input Disable
+ 77 $4 bitmask: DIDR0.ADC2D \ ADC2 Digital input Disable
+ $2 constant DIDR0_ADC1D \ ADC1 Digital input Disable
+ 77 $2 bitmask: DIDR0.ADC1D \ ADC1 Digital input Disable
+ $1 constant DIDR0_ADC0D \ ADC0 Digital input Disable
+ 77 $1 bitmask: DIDR0.ADC0D \ ADC0 Digital input Disable
+$78 constant DIDR1 \ Digital Input Disable Register
+ $8 constant DIDR1_ACMP1MD \
+ 78 $8 bitmask: DIDR1.ACMP1MD \
+ $4 constant DIDR1_AMP0POSD \
+ 78 $4 bitmask: DIDR1.AMP0POSD \
+ $2 constant DIDR1_ADC10D \
+ 78 $2 bitmask: DIDR1.ADC10D \
+ $1 constant DIDR1_ADC9D \
+ 78 $1 bitmask: DIDR1.ADC9D \
+$79 constant AMP0CSR \
+ $80 constant AMP0CSR_AMP0EN \
+ 79 $80 bitmask: AMP0CSR.AMP0EN \
+ $40 constant AMP0CSR_AMP0IS \
+ 79 $40 bitmask: AMP0CSR.AMP0IS \
+ $30 constant AMP0CSR_AMP0G \
+ 79 $30 bitmask: AMP0CSR.AMP0G \
+ $8 constant AMP0CSR_AMP0GS \
+ 79 $8 bitmask: AMP0CSR.AMP0GS \
+ $3 constant AMP0CSR_AMP0TS \
+ 79 $3 bitmask: AMP0CSR.AMP0TS \
diff --git a/amforth-6.5/avr8/devices/at90pwm161/blocks/ANALOG_COMPARATOR.frt b/amforth-6.5/avr8/devices/at90pwm161/blocks/ANALOG_COMPARATOR.frt
new file mode 100644
index 0000000..1db32bc
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90pwm161/blocks/ANALOG_COMPARATOR.frt
@@ -0,0 +1,69 @@
+\ Generated automatically for at90pwm161
+\ #require bitnames.frt
+
+\ ANALOG_COMPARATOR
+$7f constant AC3CON \ Analog Comparator3 Control Reg
+ $80 constant AC3CON_AC3EN \ Analog Comparator3 Enable Bit
+ 7f $80 bitmask: AC3CON.AC3EN \ Analog Comparator3 Enable Bit
+ $40 constant AC3CON_AC3IE \ Analog Comparator 3 Interrupt
+ 7f $40 bitmask: AC3CON.AC3IE \ Analog Comparator 3 Interrupt
+ $30 constant AC3CON_AC3IS \ Analog Comparator 3 Interrupt
+ 7f $30 bitmask: AC3CON.AC3IS \ Analog Comparator 3 Interrupt
+ $8 constant AC3CON_AC3OEA \ Analog Comparator 3 Alternate
+ 7f $8 bitmask: AC3CON.AC3OEA \ Analog Comparator 3 Alternate
+ $7 constant AC3CON_AC3M \ Analog Comparator 3 Multiplexe
+ 7f $7 bitmask: AC3CON.AC3M \ Analog Comparator 3 Multiplexe
+$7d constant AC1CON \ Analog Comparator 1 Control Re
+ $80 constant AC1CON_AC1EN \ Analog Comparator 1 Enable Bit
+ 7d $80 bitmask: AC1CON.AC1EN \ Analog Comparator 1 Enable Bit
+ $40 constant AC1CON_AC1IE \ Analog Comparator 1 Interrupt
+ 7d $40 bitmask: AC1CON.AC1IE \ Analog Comparator 1 Interrupt
+ $30 constant AC1CON_AC1IS \ Analog Comparator 1 Interrupt
+ 7d $30 bitmask: AC1CON.AC1IS \ Analog Comparator 1 Interrupt
+ $7 constant AC1CON_AC1M \ Analog Comparator 1 Multiplexe
+ 7d $7 bitmask: AC1CON.AC1M \ Analog Comparator 1 Multiplexe
+$7e constant AC2CON \ Analog Comparator 2 Control Re
+ $80 constant AC2CON_AC2EN \ Analog Comparator 2 Enable Bit
+ 7e $80 bitmask: AC2CON.AC2EN \ Analog Comparator 2 Enable Bit
+ $40 constant AC2CON_AC2IE \ Analog Comparator 2 Interrupt
+ 7e $40 bitmask: AC2CON.AC2IE \ Analog Comparator 2 Interrupt
+ $30 constant AC2CON_AC2IS \ Analog Comparator 2 Interrupt
+ 7e $30 bitmask: AC2CON.AC2IS \ Analog Comparator 2 Interrupt
+ $7 constant AC2CON_AC2M \ Analog Comparator 2 Multiplexe
+ 7e $7 bitmask: AC2CON.AC2M \ Analog Comparator 2 Multiplexe
+$20 constant ACSR \ Analog Comparator Status Regis
+ $80 constant ACSR_AC3IF \ Analog Comparator 3 Interrupt
+ 20 $80 bitmask: ACSR.AC3IF \ Analog Comparator 3 Interrupt
+ $40 constant ACSR_AC2IF \ Analog Comparator 2 Interrupt
+ 20 $40 bitmask: ACSR.AC2IF \ Analog Comparator 2 Interrupt
+ $20 constant ACSR_AC1IF \ Analog Comparator 1 Interrupt
+ 20 $20 bitmask: ACSR.AC1IF \ Analog Comparator 1 Interrupt
+ $8 constant ACSR_AC3O \ Analog Comparator 3 Output Bit
+ 20 $8 bitmask: ACSR.AC3O \ Analog Comparator 3 Output Bit
+ $4 constant ACSR_AC2O \ Analog Comparator 2 Output Bit
+ 20 $4 bitmask: ACSR.AC2O \ Analog Comparator 2 Output Bit
+ $2 constant ACSR_AC1O \ Analog Comparator 1 Output Bit
+ 20 $2 bitmask: ACSR.AC1O \ Analog Comparator 1 Output Bit
+$7c constant AC3ECON \
+ $20 constant AC3ECON_AC3OI \ Analog Comparator Ouput Invert
+ 7c $20 bitmask: AC3ECON.AC3OI \ Analog Comparator Ouput Invert
+ $10 constant AC3ECON_AC3OE \ Analog Comparator Ouput Enable
+ 7c $10 bitmask: AC3ECON.AC3OE \ Analog Comparator Ouput Enable
+ $7 constant AC3ECON_AC3H \ Analog Comparator Hysteresis S
+ 7c $7 bitmask: AC3ECON.AC3H \ Analog Comparator Hysteresis S
+$7b constant AC2ECON \
+ $20 constant AC2ECON_AC2OI \ Analog Comparator Ouput Invert
+ 7b $20 bitmask: AC2ECON.AC2OI \ Analog Comparator Ouput Invert
+ $10 constant AC2ECON_AC2OE \ Analog Comparator Ouput Enable
+ 7b $10 bitmask: AC2ECON.AC2OE \ Analog Comparator Ouput Enable
+ $7 constant AC2ECON_AC2H \ Analog Comparator Hysteresis S
+ 7b $7 bitmask: AC2ECON.AC2H \ Analog Comparator Hysteresis S
+$7a constant AC1ECON \
+ $20 constant AC1ECON_AC1OI \ Analog Comparator Ouput Invert
+ 7a $20 bitmask: AC1ECON.AC1OI \ Analog Comparator Ouput Invert
+ $10 constant AC1ECON_AC1OE \ Analog Comparator Ouput Enable
+ 7a $10 bitmask: AC1ECON.AC1OE \ Analog Comparator Ouput Enable
+ $8 constant AC1ECON_AC1ICE \ Analog Comparator Interrupt Ca
+ 7a $8 bitmask: AC1ECON.AC1ICE \ Analog Comparator Interrupt Ca
+ $7 constant AC1ECON_AC1H \ Analog Comparator Hysteresis S
+ 7a $7 bitmask: AC1ECON.AC1H \ Analog Comparator Hysteresis S
diff --git a/amforth-6.5/avr8/devices/at90pwm161/blocks/BOOT_LOAD.frt b/amforth-6.5/avr8/devices/at90pwm161/blocks/BOOT_LOAD.frt
new file mode 100644
index 0000000..37089a7
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90pwm161/blocks/BOOT_LOAD.frt
@@ -0,0 +1,21 @@
+\ Generated automatically for at90pwm161
+\ #require bitnames.frt
+
+\ BOOT_LOAD
+$57 constant SPMCSR \ Store Program Memory Control R
+ $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
+ 57 $80 bitmask: SPMCSR.SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
+ 57 $40 bitmask: SPMCSR.RWWSB \ Read While Write Section Busy
+ $20 constant SPMCSR_SIGRD \ Signature Row Read
+ 57 $20 bitmask: SPMCSR.SIGRD \ Signature Row Read
+ $10 constant SPMCSR_RWWSRE \ Read While Write section read
+ 57 $10 bitmask: SPMCSR.RWWSRE \ Read While Write section read
+ $8 constant SPMCSR_BLBSET \ Boot Lock Bit Set
+ 57 $8 bitmask: SPMCSR.BLBSET \ Boot Lock Bit Set
+ $4 constant SPMCSR_PGWRT \ Page Write
+ 57 $4 bitmask: SPMCSR.PGWRT \ Page Write
+ $2 constant SPMCSR_PGERS \ Page Erase
+ 57 $2 bitmask: SPMCSR.PGERS \ Page Erase
+ $1 constant SPMCSR_SPMEN \ Store Program Memory Enable
+ 57 $1 bitmask: SPMCSR.SPMEN \ Store Program Memory Enable
diff --git a/amforth-6.5/avr8/devices/at90pwm161/blocks/CPU.frt b/amforth-6.5/avr8/devices/at90pwm161/blocks/CPU.frt
new file mode 100644
index 0000000..37032ab
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90pwm161/blocks/CPU.frt
@@ -0,0 +1,114 @@
+\ Generated automatically for at90pwm161
+\ #require bitnames.frt
+
+\ CPU
+$5f constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ 5f $80 bitmask: SREG.I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ 5f $40 bitmask: SREG.T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ 5f $20 bitmask: SREG.H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ 5f $10 bitmask: SREG.S \ Sign Bit
+ $8 constant SREG_V \ Two's Complement Overflow Flag
+ 5f $8 bitmask: SREG.V \ Two's Complement Overflow Flag
+ $4 constant SREG_N \ Negative Flag
+ 5f $4 bitmask: SREG.N \ Negative Flag
+ $2 constant SREG_Z \ Zero Flag
+ 5f $2 bitmask: SREG.Z \ Zero Flag
+ $1 constant SREG_C \ Carry Flag
+ 5f $1 bitmask: SREG.C \ Carry Flag
+$5d constant SP \ Stack Pointer
+$55 constant MCUCR \ MCU Control Register
+ $10 constant MCUCR_PUD \ Pull-up disable
+ 55 $10 bitmask: MCUCR.PUD \ Pull-up disable
+ $8 constant MCUCR_RSTDIS \ Reset Pin Disable
+ 55 $8 bitmask: MCUCR.RSTDIS \ Reset Pin Disable
+ $4 constant MCUCR_CKRC81 \ Frequency Selection of the Cal
+ 55 $4 bitmask: MCUCR.CKRC81 \ Frequency Selection of the Cal
+ $2 constant MCUCR_IVSEL \ Interrupt Vector Select
+ 55 $2 bitmask: MCUCR.IVSEL \ Interrupt Vector Select
+ $1 constant MCUCR_IVCE \ Interrupt Vector Change Enable
+ 55 $1 bitmask: MCUCR.IVCE \ Interrupt Vector Change Enable
+$54 constant MCUSR \ MCU Status Register
+ $8 constant MCUSR_WDRF \ Watchdog Reset Flag
+ 54 $8 bitmask: MCUSR.WDRF \ Watchdog Reset Flag
+ $4 constant MCUSR_BORF \ Brown-out Reset Flag
+ 54 $4 bitmask: MCUSR.BORF \ Brown-out Reset Flag
+ $2 constant MCUSR_EXTRF \ External Reset Flag
+ 54 $2 bitmask: MCUSR.EXTRF \ External Reset Flag
+ $1 constant MCUSR_PORF \ Power-on reset flag
+ 54 $1 bitmask: MCUSR.PORF \ Power-on reset flag
+$88 constant OSCCAL \ Oscillator Calibration Value
+$83 constant CLKPR \
+ $80 constant CLKPR_CLKPCE \
+ 83 $80 bitmask: CLKPR.CLKPCE \
+ $f constant CLKPR_CLKPS \
+ 83 $f bitmask: CLKPR.CLKPS \
+$53 constant SMCR \ Sleep Mode Control Register
+ $e constant SMCR_SM \ Sleep Mode Select bits
+ 53 $e bitmask: SMCR.SM \ Sleep Mode Select bits
+ $1 constant SMCR_SE \ Sleep Enable
+ 53 $1 bitmask: SMCR.SE \ Sleep Enable
+$3b constant GPIOR2 \ General Purpose IO Register 2
+ $ff constant GPIOR2_GPIOR \ General Purpose IO Register 2
+ 3b $ff bitmask: GPIOR2.GPIOR \ General Purpose IO Register 2
+$3a constant GPIOR1 \ General Purpose IO Register 1
+ $ff constant GPIOR1_GPIOR \ General Purpose IO Register 1
+ 3a $ff bitmask: GPIOR1.GPIOR \ General Purpose IO Register 1
+$39 constant GPIOR0 \ General Purpose IO Register 0
+ $80 constant GPIOR0_GPIOR07 \ General Purpose IO Register 0
+ 39 $80 bitmask: GPIOR0.GPIOR07 \ General Purpose IO Register 0
+ $40 constant GPIOR0_GPIOR06 \ General Purpose IO Register 0
+ 39 $40 bitmask: GPIOR0.GPIOR06 \ General Purpose IO Register 0
+ $20 constant GPIOR0_GPIOR05 \ General Purpose IO Register 0
+ 39 $20 bitmask: GPIOR0.GPIOR05 \ General Purpose IO Register 0
+ $10 constant GPIOR0_GPIOR04 \ General Purpose IO Register 0
+ 39 $10 bitmask: GPIOR0.GPIOR04 \ General Purpose IO Register 0
+ $8 constant GPIOR0_GPIOR03 \ General Purpose IO Register 0
+ 39 $8 bitmask: GPIOR0.GPIOR03 \ General Purpose IO Register 0
+ $4 constant GPIOR0_GPIOR02 \ General Purpose IO Register 0
+ 39 $4 bitmask: GPIOR0.GPIOR02 \ General Purpose IO Register 0
+ $2 constant GPIOR0_GPIOR01 \ General Purpose IO Register 0
+ 39 $2 bitmask: GPIOR0.GPIOR01 \ General Purpose IO Register 0
+ $1 constant GPIOR0_GPIOR00 \ General Purpose IO Register 0
+ 39 $1 bitmask: GPIOR0.GPIOR00 \ General Purpose IO Register 0
+$87 constant PLLCSR \ PLL Control And Status Registe
+ $3c constant PLLCSR_PLLF \
+ 87 $3c bitmask: PLLCSR.PLLF \
+ $2 constant PLLCSR_PLLE \ PLL Enable
+ 87 $2 bitmask: PLLCSR.PLLE \ PLL Enable
+ $1 constant PLLCSR_PLOCK \ PLL Lock Detector
+ 87 $1 bitmask: PLLCSR.PLOCK \ PLL Lock Detector
+$86 constant PRR \ Power Reduction Register
+ $80 constant PRR_PRPSC2 \ Power Reduction PSC2
+ 86 $80 bitmask: PRR.PRPSC2 \ Power Reduction PSC2
+ $20 constant PRR_PRPSCR \ Power Reduction PSC0
+ 86 $20 bitmask: PRR.PRPSCR \ Power Reduction PSC0
+ $10 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
+ 86 $10 bitmask: PRR.PRTIM1 \ Power Reduction Timer/Counter1
+ $4 constant PRR_PRSPI \ Power Reduction Serial Periphe
+ 86 $4 bitmask: PRR.PRSPI \ Power Reduction Serial Periphe
+ $1 constant PRR_PRADC \ Power Reduction ADC
+ 86 $1 bitmask: PRR.PRADC \ Power Reduction ADC
+$84 constant CLKCSR \
+ $80 constant CLKCSR_CLKCCE \ Clock Control Change Enable
+ 84 $80 bitmask: CLKCSR.CLKCCE \ Clock Control Change Enable
+ $10 constant CLKCSR_CLKRDY \ Clock Ready Flag
+ 84 $10 bitmask: CLKCSR.CLKRDY \ Clock Ready Flag
+ $f constant CLKCSR_CLKC \ Clock Control
+ 84 $f bitmask: CLKCSR.CLKC \ Clock Control
+$85 constant CLKSELR \
+ $40 constant CLKSELR_COUT \ Clock OUT
+ 85 $40 bitmask: CLKSELR.COUT \ Clock OUT
+ $30 constant CLKSELR_CSUT \ Clock Start up Time
+ 85 $30 bitmask: CLKSELR.CSUT \ Clock Start up Time
+ $f constant CLKSELR_CKSEL \ Clock Source Select
+ 85 $f bitmask: CLKSELR.CKSEL \ Clock Source Select
+$81 constant BGCCR \ BandGap Current Calibration Re
+ $f constant BGCCR_BGCC \
+ 81 $f bitmask: BGCCR.BGCC \
+$80 constant BGCRR \ BandGap Resistor Calibration R
+ $f constant BGCRR_BGCR \
+ 80 $f bitmask: BGCRR.BGCR \
diff --git a/amforth-6.5/avr8/devices/at90pwm161/blocks/DA_CONVERTER.frt b/amforth-6.5/avr8/devices/at90pwm161/blocks/DA_CONVERTER.frt
new file mode 100644
index 0000000..9c36fb7
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90pwm161/blocks/DA_CONVERTER.frt
@@ -0,0 +1,19 @@
+\ Generated automatically for at90pwm161
+\ #require bitnames.frt
+
+\ DA_CONVERTER
+$59 constant DACH \ DAC Data Register High Byte
+ $ff constant DACH_DACH \ DAC Data Register High Byte Bi
+ 59 $ff bitmask: DACH.DACH \ DAC Data Register High Byte Bi
+$58 constant DACL \ DAC Data Register Low Byte
+ $ff constant DACL_DACL \ DAC Data Register Low Byte Bit
+ 58 $ff bitmask: DACL.DACL \ DAC Data Register Low Byte Bit
+$76 constant DACON \ DAC Control Register
+ $80 constant DACON_DAATE \ DAC Auto Trigger Enable Bit
+ 76 $80 bitmask: DACON.DAATE \ DAC Auto Trigger Enable Bit
+ $70 constant DACON_DATS \ DAC Trigger Selection Bits
+ 76 $70 bitmask: DACON.DATS \ DAC Trigger Selection Bits
+ $4 constant DACON_DALA \ DAC Left Adjust
+ 76 $4 bitmask: DACON.DALA \ DAC Left Adjust
+ $1 constant DACON_DAEN \ DAC Enable Bit
+ 76 $1 bitmask: DACON.DAEN \ DAC Enable Bit
diff --git a/amforth-6.5/avr8/devices/at90pwm161/blocks/EEPROM.frt b/amforth-6.5/avr8/devices/at90pwm161/blocks/EEPROM.frt
new file mode 100644
index 0000000..b30d081
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90pwm161/blocks/EEPROM.frt
@@ -0,0 +1,21 @@
+\ Generated automatically for at90pwm161
+\ #require bitnames.frt
+
+\ EEPROM
+$3e constant EEAR \ EEPROM Read/Write Access Byte
+$3d constant EEDR \ EEPROM Data Register
+$3c constant EECR \ EEPROM Control Register
+ $80 constant EECR_NVMBSY \ None Volatile Busy Memory Busy
+ 3c $80 bitmask: EECR.NVMBSY \ None Volatile Busy Memory Busy
+ $40 constant EECR_EEPAGE \ EEPROM Page Access
+ 3c $40 bitmask: EECR.EEPAGE \ EEPROM Page Access
+ $30 constant EECR_EEPM \ EEPROM Programming Mode
+ 3c $30 bitmask: EECR.EEPM \ EEPROM Programming Mode
+ $8 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
+ 3c $8 bitmask: EECR.EERIE \ EEPROM Ready Interrupt Enable
+ $4 constant EECR_EEMWE \ EEPROM Master Write Enable
+ 3c $4 bitmask: EECR.EEMWE \ EEPROM Master Write Enable
+ $2 constant EECR_EEWE \ EEPROM Write Enable
+ 3c $2 bitmask: EECR.EEWE \ EEPROM Write Enable
+ $1 constant EECR_EERE \ EEPROM Read Enable
+ 3c $1 bitmask: EECR.EERE \ EEPROM Read Enable
diff --git a/amforth-6.5/avr8/devices/at90pwm161/blocks/EXTERNAL_INTERRUPT.frt b/amforth-6.5/avr8/devices/at90pwm161/blocks/EXTERNAL_INTERRUPT.frt
new file mode 100644
index 0000000..6a0ecdc
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90pwm161/blocks/EXTERNAL_INTERRUPT.frt
@@ -0,0 +1,17 @@
+\ Generated automatically for at90pwm161
+\ #require bitnames.frt
+
+\ EXTERNAL_INTERRUPT
+$89 constant EICRA \ External Interrupt Control Reg
+ $30 constant EICRA_ISC2 \ External Interrupt Sense Contr
+ 89 $30 bitmask: EICRA.ISC2 \ External Interrupt Sense Contr
+ $c constant EICRA_ISC1 \ External Interrupt Sense Contr
+ 89 $c bitmask: EICRA.ISC1 \ External Interrupt Sense Contr
+ $3 constant EICRA_ISC0 \ External Interrupt Sense Contr
+ 89 $3 bitmask: EICRA.ISC0 \ External Interrupt Sense Contr
+$41 constant EIMSK \ External Interrupt Mask Regist
+ $7 constant EIMSK_INT \ External Interrupt Request 2 E
+ 41 $7 bitmask: EIMSK.INT \ External Interrupt Request 2 E
+$40 constant EIFR \ External Interrupt Flag Regist
+ $7 constant EIFR_INTF \ External Interrupt Flags
+ 40 $7 bitmask: EIFR.INTF \ External Interrupt Flags
diff --git a/amforth-6.5/avr8/devices/at90pwm161/blocks/PORTB.frt b/amforth-6.5/avr8/devices/at90pwm161/blocks/PORTB.frt
new file mode 100644
index 0000000..14612b5
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90pwm161/blocks/PORTB.frt
@@ -0,0 +1,7 @@
+\ Generated automatically for at90pwm161
+\ #require bitnames.frt
+
+\ PORTB
+$25 constant PORTB \ Port B Data Register
+$24 constant DDRB \ Port B Data Direction Register
+$23 constant PINB \ Port B Input Pins
diff --git a/amforth-6.5/avr8/devices/at90pwm161/blocks/PORTD.frt b/amforth-6.5/avr8/devices/at90pwm161/blocks/PORTD.frt
new file mode 100644
index 0000000..a45e474
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90pwm161/blocks/PORTD.frt
@@ -0,0 +1,7 @@
+\ Generated automatically for at90pwm161
+\ #require bitnames.frt
+
+\ PORTD
+$2b constant PORTD \ Port D Data Register
+$2a constant DDRD \ Port D Data Direction Register
+$29 constant PIND \ Port D Input Pins
diff --git a/amforth-6.5/avr8/devices/at90pwm161/blocks/PORTE.frt b/amforth-6.5/avr8/devices/at90pwm161/blocks/PORTE.frt
new file mode 100644
index 0000000..f774d19
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90pwm161/blocks/PORTE.frt
@@ -0,0 +1,7 @@
+\ Generated automatically for at90pwm161
+\ #require bitnames.frt
+
+\ PORTE
+$2e constant PORTE \ Port E Data Register
+$2d constant DDRE \ Port E Data Direction Register
+$2c constant PINE \ Port E Input Pins
diff --git a/amforth-6.5/avr8/devices/at90pwm161/blocks/PSC0.frt b/amforth-6.5/avr8/devices/at90pwm161/blocks/PSC0.frt
new file mode 100644
index 0000000..3774cfe
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90pwm161/blocks/PSC0.frt
@@ -0,0 +1,90 @@
+\ Generated automatically for at90pwm161
+\ #require bitnames.frt
+
+\ PSC0
+$68 constant PICR0 \ PSC 0 Input Capture Register
+$63 constant PFRC0B \ PSC 0 Input B Control
+ $80 constant PFRC0B_PCAE0B \ PSC 0 Capture Enable Input Par
+ 63 $80 bitmask: PFRC0B.PCAE0B \ PSC 0 Capture Enable Input Par
+ $40 constant PFRC0B_PISEL0B \ PSC 0 Input Select for Part B
+ 63 $40 bitmask: PFRC0B.PISEL0B \ PSC 0 Input Select for Part B
+ $20 constant PFRC0B_PELEV0B \ PSC 0 Edge Level Selector on I
+ 63 $20 bitmask: PFRC0B.PELEV0B \ PSC 0 Edge Level Selector on I
+ $10 constant PFRC0B_PFLTE0B \ PSC 0 Filter Enable on Input P
+ 63 $10 bitmask: PFRC0B.PFLTE0B \ PSC 0 Filter Enable on Input P
+ $f constant PFRC0B_PRFM0B \ PSC 0 Retrigger and Fault Mode
+ 63 $f bitmask: PFRC0B.PRFM0B \ PSC 0 Retrigger and Fault Mode
+$62 constant PFRC0A \ PSC 0 Input A Control
+ $80 constant PFRC0A_PCAE0A \ PSC 0 Capture Enable Input Par
+ 62 $80 bitmask: PFRC0A.PCAE0A \ PSC 0 Capture Enable Input Par
+ $40 constant PFRC0A_PISEL0A \ PSC 0 Input Select for Part A
+ 62 $40 bitmask: PFRC0A.PISEL0A \ PSC 0 Input Select for Part A
+ $20 constant PFRC0A_PELEV0A \ PSC 0 Edge Level Selector on I
+ 62 $20 bitmask: PFRC0A.PELEV0A \ PSC 0 Edge Level Selector on I
+ $10 constant PFRC0A_PFLTE0A \ PSC 0 Filter Enable on Input P
+ 62 $10 bitmask: PFRC0A.PFLTE0A \ PSC 0 Filter Enable on Input P
+ $f constant PFRC0A_PRFM0A \ PSC 0 Retrigger and Fault Mode
+ 62 $f bitmask: PFRC0A.PRFM0A \ PSC 0 Retrigger and Fault Mode
+$32 constant PCTL0 \ PSC 0 Control Register
+ $c0 constant PCTL0_PPRE0 \ PSC 0 Prescaler Selects
+ 32 $c0 bitmask: PCTL0.PPRE0 \ PSC 0 Prescaler Selects
+ $24 constant PCTL0_PBFM0 \ PSC 0 Balance Flank Width Modu
+ 32 $24 bitmask: PCTL0.PBFM0 \ PSC 0 Balance Flank Width Modu
+ $10 constant PCTL0_PAOC0B \ PSC 0 Asynchronous Output Cont
+ 32 $10 bitmask: PCTL0.PAOC0B \ PSC 0 Asynchronous Output Cont
+ $8 constant PCTL0_PAOC0A \ PSC 0 Asynchronous Output Cont
+ 32 $8 bitmask: PCTL0.PAOC0A \ PSC 0 Asynchronous Output Cont
+ $2 constant PCTL0_PCCYC0 \ PSC0 Complete Cycle
+ 32 $2 bitmask: PCTL0.PCCYC0 \ PSC0 Complete Cycle
+ $1 constant PCTL0_PRUN0 \ PSC 0 Run
+ 32 $1 bitmask: PCTL0.PRUN0 \ PSC 0 Run
+$31 constant PCNF0 \ PSC 0 Configuration Register
+ $80 constant PCNF0_PFIFTY0 \ PSC 0 Fifty
+ 31 $80 bitmask: PCNF0.PFIFTY0 \ PSC 0 Fifty
+ $40 constant PCNF0_PALOCK0 \ PSC 0 Autolock
+ 31 $40 bitmask: PCNF0.PALOCK0 \ PSC 0 Autolock
+ $20 constant PCNF0_PLOCK0 \ PSC 0 Lock
+ 31 $20 bitmask: PCNF0.PLOCK0 \ PSC 0 Lock
+ $18 constant PCNF0_PMODE0 \ PSC 0 Mode
+ 31 $18 bitmask: PCNF0.PMODE0 \ PSC 0 Mode
+ $4 constant PCNF0_POP0 \ PSC 0 Output Polarity
+ 31 $4 bitmask: PCNF0.POP0 \ PSC 0 Output Polarity
+ $2 constant PCNF0_PCLKSEL0 \ PSC 0 Input Clock Select
+ 31 $2 bitmask: PCNF0.PCLKSEL0 \ PSC 0 Input Clock Select
+$44 constant OCR0RB \ Output Compare RB Register
+$42 constant OCR0SB \ Output Compare SB Register
+$4a constant OCR0RA \ Output Compare RA Register
+$60 constant OCR0SA \ Output Compare SA Register
+$6a constant PSOC0 \ PSC0 Synchro and Output Config
+ $80 constant PSOC0_PISEL0A1 \ PSC Input Select
+ 6a $80 bitmask: PSOC0.PISEL0A1 \ PSC Input Select
+ $40 constant PSOC0_PISEL0B1 \ PSC Input Select
+ 6a $40 bitmask: PSOC0.PISEL0B1 \ PSC Input Select
+ $30 constant PSOC0_PSYNC0 \ Synchronisation out for ADC se
+ 6a $30 bitmask: PSOC0.PSYNC0 \ Synchronisation out for ADC se
+ $4 constant PSOC0_POEN0B \ PSCOUT01 Output Enable
+ 6a $4 bitmask: PSOC0.POEN0B \ PSCOUT01 Output Enable
+ $1 constant PSOC0_POEN0A \ PSCOUT00 Output Enable
+ 6a $1 bitmask: PSOC0.POEN0A \ PSCOUT00 Output Enable
+$2f constant PIM0 \ PSC0 Interrupt Mask Register
+ $10 constant PIM0_PEVE0B \ External Event B Interrupt Ena
+ 2f $10 bitmask: PIM0.PEVE0B \ External Event B Interrupt Ena
+ $8 constant PIM0_PEVE0A \ External Event A Interrupt Ena
+ 2f $8 bitmask: PIM0.PEVE0A \ External Event A Interrupt Ena
+ $2 constant PIM0_PEOEPE0 \ End of Enhanced Cycle Enable
+ 2f $2 bitmask: PIM0.PEOEPE0 \ End of Enhanced Cycle Enable
+ $1 constant PIM0_PEOPE0 \ End of Cycle Interrupt Enable
+ 2f $1 bitmask: PIM0.PEOPE0 \ End of Cycle Interrupt Enable
+$30 constant PIFR0 \ PSC0 Interrupt Flag Register
+ $80 constant PIFR0_POAC0B \ PSC 0 Output A Activity
+ 30 $80 bitmask: PIFR0.POAC0B \ PSC 0 Output A Activity
+ $40 constant PIFR0_POAC0A \ PSC 0 Output A Activity
+ 30 $40 bitmask: PIFR0.POAC0A \ PSC 0 Output A Activity
+ $10 constant PIFR0_PEV0B \ External Event B Interrupt
+ 30 $10 bitmask: PIFR0.PEV0B \ External Event B Interrupt
+ $8 constant PIFR0_PEV0A \ External Event A Interrupt
+ 30 $8 bitmask: PIFR0.PEV0A \ External Event A Interrupt
+ $6 constant PIFR0_PRN0 \ Ramp Number
+ 30 $6 bitmask: PIFR0.PRN0 \ Ramp Number
+ $1 constant PIFR0_PEOP0 \ End of PSC0 Interrupt
+ 30 $1 bitmask: PIFR0.PEOP0 \ End of PSC0 Interrupt
diff --git a/amforth-6.5/avr8/devices/at90pwm161/blocks/PSC2.frt b/amforth-6.5/avr8/devices/at90pwm161/blocks/PSC2.frt
new file mode 100644
index 0000000..68acc9f
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90pwm161/blocks/PSC2.frt
@@ -0,0 +1,126 @@
+\ Generated automatically for at90pwm161
+\ #require bitnames.frt
+
+\ PSC2
+$6d constant PICR2H \ PSC 2 Input Capture Register H
+ $80 constant PICR2H_PCST2 \ PSC 2 Capture Software Trigger
+ 6d $80 bitmask: PICR2H.PCST2 \ PSC 2 Capture Software Trigger
+ $c constant PICR2H_PICR21 \
+ 6d $c bitmask: PICR2H.PICR21 \
+ $3 constant PICR2H_PICR2 \
+ 6d $3 bitmask: PICR2H.PICR2 \
+$6c constant PICR2L \ PSC 2 Input Capture Register L
+$67 constant PFRC2B \ PSC 2 Input B Control
+ $80 constant PFRC2B_PCAE2B \ PSC 2 Capture Enable Input Par
+ 67 $80 bitmask: PFRC2B.PCAE2B \ PSC 2 Capture Enable Input Par
+ $40 constant PFRC2B_PISEL2B \ PSC 2 Input Select for Part B
+ 67 $40 bitmask: PFRC2B.PISEL2B \ PSC 2 Input Select for Part B
+ $20 constant PFRC2B_PELEV2B \ PSC 2 Edge Level Selector on I
+ 67 $20 bitmask: PFRC2B.PELEV2B \ PSC 2 Edge Level Selector on I
+ $10 constant PFRC2B_PFLTE2B \ PSC 2 Filter Enable on Input P
+ 67 $10 bitmask: PFRC2B.PFLTE2B \ PSC 2 Filter Enable on Input P
+ $f constant PFRC2B_PRFM2B \ PSC 2 Retrigger and Fault Mode
+ 67 $f bitmask: PFRC2B.PRFM2B \ PSC 2 Retrigger and Fault Mode
+$66 constant PFRC2A \ PSC 2 Input B Control
+ $80 constant PFRC2A_PCAE2A \ PSC 2 Capture Enable Input Par
+ 66 $80 bitmask: PFRC2A.PCAE2A \ PSC 2 Capture Enable Input Par
+ $40 constant PFRC2A_PISEL2A \ PSC 2 Input Select for Part A
+ 66 $40 bitmask: PFRC2A.PISEL2A \ PSC 2 Input Select for Part A
+ $20 constant PFRC2A_PELEV2A \ PSC 2 Edge Level Selector on I
+ 66 $20 bitmask: PFRC2A.PELEV2A \ PSC 2 Edge Level Selector on I
+ $10 constant PFRC2A_PFLTE2A \ PSC 2 Filter Enable on Input P
+ 66 $10 bitmask: PFRC2A.PFLTE2A \ PSC 2 Filter Enable on Input P
+ $f constant PFRC2A_PRFM2A \ PSC 2 Retrigger and Fault Mode
+ 66 $f bitmask: PFRC2A.PRFM2A \ PSC 2 Retrigger and Fault Mode
+$36 constant PCTL2 \ PSC 2 Control Register
+ $c0 constant PCTL2_PPRE2 \ PSC 2 Prescaler Selects
+ 36 $c0 bitmask: PCTL2.PPRE2 \ PSC 2 Prescaler Selects
+ $20 constant PCTL2_PBFM2 \ Balance Flank Width Modulation
+ 36 $20 bitmask: PCTL2.PBFM2 \ Balance Flank Width Modulation
+ $10 constant PCTL2_PAOC2B \ PSC 2 Asynchronous Output Cont
+ 36 $10 bitmask: PCTL2.PAOC2B \ PSC 2 Asynchronous Output Cont
+ $8 constant PCTL2_PAOC2A \ PSC 2 Asynchronous Output Cont
+ 36 $8 bitmask: PCTL2.PAOC2A \ PSC 2 Asynchronous Output Cont
+ $4 constant PCTL2_PARUN2 \ PSC2 Auto Run
+ 36 $4 bitmask: PCTL2.PARUN2 \ PSC2 Auto Run
+ $2 constant PCTL2_PCCYC2 \ PSC2 Complete Cycle
+ 36 $2 bitmask: PCTL2.PCCYC2 \ PSC2 Complete Cycle
+ $1 constant PCTL2_PRUN2 \ PSC 2 Run
+ 36 $1 bitmask: PCTL2.PRUN2 \ PSC 2 Run
+$35 constant PCNF2 \ PSC 2 Configuration Register
+ $80 constant PCNF2_PFIFTY2 \ PSC 2 Fifty
+ 35 $80 bitmask: PCNF2.PFIFTY2 \ PSC 2 Fifty
+ $40 constant PCNF2_PALOCK2 \ PSC 2 Autolock
+ 35 $40 bitmask: PCNF2.PALOCK2 \ PSC 2 Autolock
+ $20 constant PCNF2_PLOCK2 \ PSC 2 Lock
+ 35 $20 bitmask: PCNF2.PLOCK2 \ PSC 2 Lock
+ $18 constant PCNF2_PMODE2 \ PSC 2 Mode
+ 35 $18 bitmask: PCNF2.PMODE2 \ PSC 2 Mode
+ $4 constant PCNF2_POP2 \ PSC 2 Output Polarity
+ 35 $4 bitmask: PCNF2.POP2 \ PSC 2 Output Polarity
+ $2 constant PCNF2_PCLKSEL2 \ PSC 2 Input Clock Select
+ 35 $2 bitmask: PCNF2.PCLKSEL2 \ PSC 2 Input Clock Select
+ $1 constant PCNF2_POME2 \ PSC 2 Output Matrix Enable
+ 35 $1 bitmask: PCNF2.POME2 \ PSC 2 Output Matrix Enable
+$70 constant PCNFE2 \ PSC 2 Enhanced Configuration R
+ $e0 constant PCNFE2_PASDLK2 \
+ 70 $e0 bitmask: PCNFE2.PASDLK2 \
+ $10 constant PCNFE2_PBFM21 \
+ 70 $10 bitmask: PCNFE2.PBFM21 \
+ $8 constant PCNFE2_PELEV2A1 \
+ 70 $8 bitmask: PCNFE2.PELEV2A1 \
+ $4 constant PCNFE2_PELEV2B1 \
+ 70 $4 bitmask: PCNFE2.PELEV2B1 \
+ $2 constant PCNFE2_PISEL2A1 \
+ 70 $2 bitmask: PCNFE2.PISEL2A1 \
+ $1 constant PCNFE2_PISEL2B1 \
+ 70 $1 bitmask: PCNFE2.PISEL2B1 \
+$48 constant OCR2RB \ Output Compare RB Register
+$46 constant OCR2SB \ Output Compare SB Register
+$4e constant OCR2RA \ Output Compare RA Register
+$64 constant OCR2SA \ Output Compare SA Register
+$6f constant POM2 \ PSC 2 Output Matrix
+ $f0 constant POM2_POMV2B \ Output Matrix Output B Ramps
+ 6f $f0 bitmask: POM2.POMV2B \ Output Matrix Output B Ramps
+ $f constant POM2_POMV2A \ Output Matrix Output A Ramps
+ 6f $f bitmask: POM2.POMV2A \ Output Matrix Output A Ramps
+$6e constant PSOC2 \ PSC2 Synchro and Output Config
+ $c0 constant PSOC2_POS2 \ PSC 2 Output 23 Select
+ 6e $c0 bitmask: PSOC2.POS2 \ PSC 2 Output 23 Select
+ $30 constant PSOC2_PSYNC2 \ Synchronization Out for ADC Se
+ 6e $30 bitmask: PSOC2.PSYNC2 \ Synchronization Out for ADC Se
+ $8 constant PSOC2_POEN2D \ PSCOUT23 Output Enable
+ 6e $8 bitmask: PSOC2.POEN2D \ PSCOUT23 Output Enable
+ $4 constant PSOC2_POEN2B \ PSCOUT21 Output Enable
+ 6e $4 bitmask: PSOC2.POEN2B \ PSCOUT21 Output Enable
+ $2 constant PSOC2_POEN2C \ PSCOUT22 Output Enable
+ 6e $2 bitmask: PSOC2.POEN2C \ PSCOUT22 Output Enable
+ $1 constant PSOC2_POEN2A \ PSCOUT20 Output Enable
+ 6e $1 bitmask: PSOC2.POEN2A \ PSCOUT20 Output Enable
+$33 constant PIM2 \ PSC2 Interrupt Mask Register
+ $20 constant PIM2_PSEIE2 \ PSC 2 Synchro Error Interrupt
+ 33 $20 bitmask: PIM2.PSEIE2 \ PSC 2 Synchro Error Interrupt
+ $10 constant PIM2_PEVE2B \ External Event B Interrupt Ena
+ 33 $10 bitmask: PIM2.PEVE2B \ External Event B Interrupt Ena
+ $8 constant PIM2_PEVE2A \ External Event A Interrupt Ena
+ 33 $8 bitmask: PIM2.PEVE2A \ External Event A Interrupt Ena
+ $2 constant PIM2_PEOEPE2 \ End of Enhanced Cycle Interrup
+ 33 $2 bitmask: PIM2.PEOEPE2 \ End of Enhanced Cycle Interrup
+ $1 constant PIM2_PEOPE2 \ End of Cycle Interrupt Enable
+ 33 $1 bitmask: PIM2.PEOPE2 \ End of Cycle Interrupt Enable
+$34 constant PIFR2 \ PSC2 Interrupt Flag Register
+ $80 constant PIFR2_POAC2B \ PSC 2 Output A Activity
+ 34 $80 bitmask: PIFR2.POAC2B \ PSC 2 Output A Activity
+ $40 constant PIFR2_POAC2A \ PSC 2 Output A Activity
+ 34 $40 bitmask: PIFR2.POAC2A \ PSC 2 Output A Activity
+ $20 constant PIFR2_PSEI2 \ PSC 2 Synchro Error Interrupt
+ 34 $20 bitmask: PIFR2.PSEI2 \ PSC 2 Synchro Error Interrupt
+ $10 constant PIFR2_PEV2B \ External Event B Interrupt
+ 34 $10 bitmask: PIFR2.PEV2B \ External Event B Interrupt
+ $8 constant PIFR2_PEV2A \ External Event A Interrupt
+ 34 $8 bitmask: PIFR2.PEV2A \ External Event A Interrupt
+ $6 constant PIFR2_PRN2 \ Ramp Number
+ 34 $6 bitmask: PIFR2.PRN2 \ Ramp Number
+ $1 constant PIFR2_PEOP2 \ End of PSC2 Interrupt
+ 34 $1 bitmask: PIFR2.PEOP2 \ End of PSC2 Interrupt
+$71 constant PASDLY2 \ Analog Synchronization Delay R
diff --git a/amforth-6.5/avr8/devices/at90pwm161/blocks/SPI.frt b/amforth-6.5/avr8/devices/at90pwm161/blocks/SPI.frt
new file mode 100644
index 0000000..190bab5
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90pwm161/blocks/SPI.frt
@@ -0,0 +1,27 @@
+\ Generated automatically for at90pwm161
+\ #require bitnames.frt
+
+\ SPI
+$37 constant SPCR \ SPI Control Register
+ $80 constant SPCR_SPIE \ SPI Interrupt Enable
+ 37 $80 bitmask: SPCR.SPIE \ SPI Interrupt Enable
+ $40 constant SPCR_SPE \ SPI Enable
+ 37 $40 bitmask: SPCR.SPE \ SPI Enable
+ $20 constant SPCR_DORD \ Data Order
+ 37 $20 bitmask: SPCR.DORD \ Data Order
+ $10 constant SPCR_MSTR \ Master/Slave Select
+ 37 $10 bitmask: SPCR.MSTR \ Master/Slave Select
+ $8 constant SPCR_CPOL \ Clock polarity
+ 37 $8 bitmask: SPCR.CPOL \ Clock polarity
+ $4 constant SPCR_CPHA \ Clock Phase
+ 37 $4 bitmask: SPCR.CPHA \ Clock Phase
+ $3 constant SPCR_SPR \ SPI Clock Rate Selects
+ 37 $3 bitmask: SPCR.SPR \ SPI Clock Rate Selects
+$38 constant SPSR \ SPI Status Register
+ $80 constant SPSR_SPIF \ SPI Interrupt Flag
+ 38 $80 bitmask: SPSR.SPIF \ SPI Interrupt Flag
+ $40 constant SPSR_WCOL \ Write Collision Flag
+ 38 $40 bitmask: SPSR.WCOL \ Write Collision Flag
+ $1 constant SPSR_SPI2X \ Double SPI Speed Bit
+ 38 $1 bitmask: SPSR.SPI2X \ Double SPI Speed Bit
+$56 constant SPDR \ SPI Data Register
diff --git a/amforth-6.5/avr8/devices/at90pwm161/blocks/TIMER_COUNTER_1.frt b/amforth-6.5/avr8/devices/at90pwm161/blocks/TIMER_COUNTER_1.frt
new file mode 100644
index 0000000..3e17b16
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90pwm161/blocks/TIMER_COUNTER_1.frt
@@ -0,0 +1,25 @@
+\ Generated automatically for at90pwm161
+\ #require bitnames.frt
+
+\ TIMER_COUNTER_1
+$21 constant TIMSK1 \ Timer/Counter Interrupt Mask R
+ $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture I
+ 21 $20 bitmask: TIMSK1.ICIE1 \ Timer/Counter1 Input Capture I
+ $1 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interr
+ 21 $1 bitmask: TIMSK1.TOIE1 \ Timer/Counter1 Overflow Interr
+$22 constant TIFR1 \ Timer/Counter Interrupt Flag r
+ $20 constant TIFR1_ICF1 \ Input Capture Flag 1
+ 22 $20 bitmask: TIFR1.ICF1 \ Input Capture Flag 1
+ $1 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
+ 22 $1 bitmask: TIFR1.TOV1 \ Timer/Counter1 Overflow Flag
+$8a constant TCCR1B \ Timer/Counter1 Control Registe
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
+ 8a $80 bitmask: TCCR1B.ICNC1 \ Input Capture 1 Noise Canceler
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ 8a $40 bitmask: TCCR1B.ICES1 \ Input Capture 1 Edge Select
+ $10 constant TCCR1B_WGM13 \ Waveform Generation Mode
+ 8a $10 bitmask: TCCR1B.WGM13 \ Waveform Generation Mode
+ $7 constant TCCR1B_CS1 \ Prescaler source of Timer/Coun
+ 8a $7 bitmask: TCCR1B.CS1 \ Prescaler source of Timer/Coun
+$5a constant TCNT1 \ Timer/Counter1 Bytes
+$8c constant ICR1 \ Timer/Counter1 Input Capture R
diff --git a/amforth-6.5/avr8/devices/at90pwm161/blocks/WATCHDOG.frt b/amforth-6.5/avr8/devices/at90pwm161/blocks/WATCHDOG.frt
new file mode 100644
index 0000000..1772bac
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90pwm161/blocks/WATCHDOG.frt
@@ -0,0 +1,15 @@
+\ Generated automatically for at90pwm161
+\ #require bitnames.frt
+
+\ WATCHDOG
+$82 constant WDTCSR \ Watchdog Timer Control Registe
+ $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Fla
+ 82 $80 bitmask: WDTCSR.WDIF \ Watchdog Timeout Interrupt Fla
+ $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Ena
+ 82 $40 bitmask: WDTCSR.WDIE \ Watchdog Timeout Interrupt Ena
+ $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
+ 82 $27 bitmask: WDTCSR.WDP \ Watchdog Timer Prescaler Bits
+ $10 constant WDTCSR_WDCE \ Watchdog Change Enable
+ 82 $10 bitmask: WDTCSR.WDCE \ Watchdog Change Enable
+ $8 constant WDTCSR_WDE \ Watch Dog Enable
+ 82 $8 bitmask: WDTCSR.WDE \ Watch Dog Enable
diff --git a/amforth-6.5/avr8/devices/at90pwm161/device.asm b/amforth-6.5/avr8/devices/at90pwm161/device.asm
new file mode 100644
index 0000000..8bf16d2
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90pwm161/device.asm
@@ -0,0 +1,52 @@
+; Generated Automatically
+
+.nolist
+ include "pwm161def.inc"
+.list
+FLASHSTART = 0
+FLASHSIZE = 16384
+RAMEND = 1280
+IRAMSTART = 256
+IRAMSIZE = 1024
+EEPROMSIZE = 512
+; Interrupt Vectors
+.overlap
+.org 2
+ rcall isr ; PSC2 Capture Event
+.org 4
+ rcall isr ; PSC2 End Cycle
+.org 6
+ rcall isr ; PSC2 End Of Enhanced Cycle
+.org 8
+ rcall isr ; PSC0 Capture Event
+.org 10
+ rcall isr ; PSC0 End Cycle
+.org 12
+ rcall isr ; PSC0 End Of Enhanced Cycle
+.org 14
+ rcall isr ; Analog Comparator 1
+.org 16
+ rcall isr ; Analog Comparator 2
+.org 18
+ rcall isr ; Analog Comparator 3
+.org 20
+ rcall isr ; External Interrupt Request 0
+.org 22
+ rcall isr ; Timer/Counter1 Capture Event
+.org 24
+ rcall isr ; Timer/Counter1 Overflow
+.org 26
+ rcall isr ; ADC Conversion Complete
+.org 28
+ rcall isr ; External Interrupt Request 1
+.org 30
+ rcall isr ; SPI Serial Transfer Complet
+.org 32
+ rcall isr ; External Interrupt Request 2
+.org 34
+ rcall isr ; Watchdog Timeout Interrupt
+.org 36
+ rcall isr ; EEPROM Ready
+.org 38
+ rcall isr ; Store Program Memory Read
+.nooverlap
diff --git a/amforth-6.5/avr8/devices/at90pwm161/device.frt b/amforth-6.5/avr8/devices/at90pwm161/device.frt
new file mode 100644
index 0000000..00c4728
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90pwm161/device.frt
@@ -0,0 +1,613 @@
+\ Generated Automatically
+
+\ Interrupt Vectors
+#2 constant PSC2_CAPTAddr \ PSC2 Capture Event
+#4 constant PSC2_ECAddr \ PSC2 End Cycle
+#6 constant PSC2_EECAddr \ PSC2 End Of Enhanced Cycle
+#8 constant PSC0_CAPTAddr \ PSC0 Capture Event
+#10 constant PSC0_ECAddr \ PSC0 End Cycle
+#12 constant PSC0_EECAddr \ PSC0 End Of Enhanced Cycle
+#14 constant ANALOG_COMP_1Addr \ Analog Comparator 1
+#16 constant ANALOG_COMP_2Addr \ Analog Comparator 2
+#18 constant ANALOG_COMP_3Addr \ Analog Comparator 3
+#20 constant INT0Addr \ External Interrupt Request 0
+#22 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+#24 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+#26 constant ADCAddr \ ADC Conversion Complete
+#28 constant INT1Addr \ External Interrupt Request 1
+#30 constant SPI_STCAddr \ SPI Serial Transfer Complet
+#32 constant INT2Addr \ External Interrupt Request 2
+#34 constant WDTAddr \ Watchdog Timeout Interrupt
+#36 constant EE_READYAddr \ EEPROM Ready
+#38 constant SPM_READYAddr \ Store Program Memory Read
+\ PORTB
+$25 constant PORTB \ Port B Data Register
+$24 constant DDRB \ Port B Data Direction Register
+$23 constant PINB \ Port B Input Pins
+\ PORTD
+$2b constant PORTD \ Port D Data Register
+$2a constant DDRD \ Port D Data Direction Register
+$29 constant PIND \ Port D Input Pins
+\ DA_CONVERTER
+$59 constant DACH \ DAC Data Register High Byte
+ $ff constant DACH_DACH \ DAC Data Register High Byte Bi
+ 59 $ff bitmask: DACH.DACH \ DAC Data Register High Byte Bi
+$58 constant DACL \ DAC Data Register Low Byte
+ $ff constant DACL_DACL \ DAC Data Register Low Byte Bit
+ 58 $ff bitmask: DACL.DACL \ DAC Data Register Low Byte Bit
+$76 constant DACON \ DAC Control Register
+ $80 constant DACON_DAATE \ DAC Auto Trigger Enable Bit
+ 76 $80 bitmask: DACON.DAATE \ DAC Auto Trigger Enable Bit
+ $70 constant DACON_DATS \ DAC Trigger Selection Bits
+ 76 $70 bitmask: DACON.DATS \ DAC Trigger Selection Bits
+ $4 constant DACON_DALA \ DAC Left Adjust
+ 76 $4 bitmask: DACON.DALA \ DAC Left Adjust
+ $1 constant DACON_DAEN \ DAC Enable Bit
+ 76 $1 bitmask: DACON.DAEN \ DAC Enable Bit
+\ PORTE
+$2e constant PORTE \ Port E Data Register
+$2d constant DDRE \ Port E Data Direction Register
+$2c constant PINE \ Port E Input Pins
+\ SPI
+$37 constant SPCR \ SPI Control Register
+ $80 constant SPCR_SPIE \ SPI Interrupt Enable
+ 37 $80 bitmask: SPCR.SPIE \ SPI Interrupt Enable
+ $40 constant SPCR_SPE \ SPI Enable
+ 37 $40 bitmask: SPCR.SPE \ SPI Enable
+ $20 constant SPCR_DORD \ Data Order
+ 37 $20 bitmask: SPCR.DORD \ Data Order
+ $10 constant SPCR_MSTR \ Master/Slave Select
+ 37 $10 bitmask: SPCR.MSTR \ Master/Slave Select
+ $8 constant SPCR_CPOL \ Clock polarity
+ 37 $8 bitmask: SPCR.CPOL \ Clock polarity
+ $4 constant SPCR_CPHA \ Clock Phase
+ 37 $4 bitmask: SPCR.CPHA \ Clock Phase
+ $3 constant SPCR_SPR \ SPI Clock Rate Selects
+ 37 $3 bitmask: SPCR.SPR \ SPI Clock Rate Selects
+$38 constant SPSR \ SPI Status Register
+ $80 constant SPSR_SPIF \ SPI Interrupt Flag
+ 38 $80 bitmask: SPSR.SPIF \ SPI Interrupt Flag
+ $40 constant SPSR_WCOL \ Write Collision Flag
+ 38 $40 bitmask: SPSR.WCOL \ Write Collision Flag
+ $1 constant SPSR_SPI2X \ Double SPI Speed Bit
+ 38 $1 bitmask: SPSR.SPI2X \ Double SPI Speed Bit
+$56 constant SPDR \ SPI Data Register
+\ WATCHDOG
+$82 constant WDTCSR \ Watchdog Timer Control Registe
+ $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Fla
+ 82 $80 bitmask: WDTCSR.WDIF \ Watchdog Timeout Interrupt Fla
+ $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Ena
+ 82 $40 bitmask: WDTCSR.WDIE \ Watchdog Timeout Interrupt Ena
+ $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
+ 82 $27 bitmask: WDTCSR.WDP \ Watchdog Timer Prescaler Bits
+ $10 constant WDTCSR_WDCE \ Watchdog Change Enable
+ 82 $10 bitmask: WDTCSR.WDCE \ Watchdog Change Enable
+ $8 constant WDTCSR_WDE \ Watch Dog Enable
+ 82 $8 bitmask: WDTCSR.WDE \ Watch Dog Enable
+\ EXTERNAL_INTERRUPT
+$89 constant EICRA \ External Interrupt Control Reg
+ $30 constant EICRA_ISC2 \ External Interrupt Sense Contr
+ 89 $30 bitmask: EICRA.ISC2 \ External Interrupt Sense Contr
+ $c constant EICRA_ISC1 \ External Interrupt Sense Contr
+ 89 $c bitmask: EICRA.ISC1 \ External Interrupt Sense Contr
+ $3 constant EICRA_ISC0 \ External Interrupt Sense Contr
+ 89 $3 bitmask: EICRA.ISC0 \ External Interrupt Sense Contr
+$41 constant EIMSK \ External Interrupt Mask Regist
+ $7 constant EIMSK_INT \ External Interrupt Request 2 E
+ 41 $7 bitmask: EIMSK.INT \ External Interrupt Request 2 E
+$40 constant EIFR \ External Interrupt Flag Regist
+ $7 constant EIFR_INTF \ External Interrupt Flags
+ 40 $7 bitmask: EIFR.INTF \ External Interrupt Flags
+\ AD_CONVERTER
+$28 constant ADMUX \ The ADC multiplexer Selection
+ $c0 constant ADMUX_REFS \ Reference Selection Bits
+ 28 $c0 bitmask: ADMUX.REFS \ Reference Selection Bits
+ $20 constant ADMUX_ADLAR \ Left Adjust Result
+ 28 $20 bitmask: ADMUX.ADLAR \ Left Adjust Result
+ $f constant ADMUX_MUX \ Analog Channel and Gain Select
+ 28 $f bitmask: ADMUX.MUX \ Analog Channel and Gain Select
+$26 constant ADCSRA \ The ADC Control and Status reg
+ $80 constant ADCSRA_ADEN \ ADC Enable
+ 26 $80 bitmask: ADCSRA.ADEN \ ADC Enable
+ $40 constant ADCSRA_ADSC \ ADC Start Conversion
+ 26 $40 bitmask: ADCSRA.ADSC \ ADC Start Conversion
+ $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
+ 26 $20 bitmask: ADCSRA.ADATE \ ADC Auto Trigger Enable
+ $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
+ 26 $10 bitmask: ADCSRA.ADIF \ ADC Interrupt Flag
+ $8 constant ADCSRA_ADIE \ ADC Interrupt Enable
+ 26 $8 bitmask: ADCSRA.ADIE \ ADC Interrupt Enable
+ $7 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
+ 26 $7 bitmask: ADCSRA.ADPS \ ADC Prescaler Select Bits
+$4c constant ADC \ ADC Data Register Bytes
+$27 constant ADCSRB \ ADC Control and Status Registe
+ $80 constant ADCSRB_ADHSM \ ADC High Speed Mode
+ 27 $80 bitmask: ADCSRB.ADHSM \ ADC High Speed Mode
+ $40 constant ADCSRB_ADNCDIS \ ADC Noise Canceller Disable
+ 27 $40 bitmask: ADCSRB.ADNCDIS \ ADC Noise Canceller Disable
+ $10 constant ADCSRB_ADSSEN \ ADC Single Shot Enable on PSC'
+ 27 $10 bitmask: ADCSRB.ADSSEN \ ADC Single Shot Enable on PSC'
+ $f constant ADCSRB_ADTS \ ADC Auto Trigger Sources
+ 27 $f bitmask: ADCSRB.ADTS \ ADC Auto Trigger Sources
+$77 constant DIDR0 \ Digital Input Disable Register
+ $80 constant DIDR0_ADC7D \
+ 77 $80 bitmask: DIDR0.ADC7D \
+ $40 constant DIDR0_ADC6D \ ADC7 Digital input Disable
+ 77 $40 bitmask: DIDR0.ADC6D \ ADC7 Digital input Disable
+ $20 constant DIDR0_ADC5D \ ADC5 Digital input Disable
+ 77 $20 bitmask: DIDR0.ADC5D \ ADC5 Digital input Disable
+ $10 constant DIDR0_ADC4D \ ADC4 Digital input Disable
+ 77 $10 bitmask: DIDR0.ADC4D \ ADC4 Digital input Disable
+ $8 constant DIDR0_ADC3D \ ADC3 Digital input Disable
+ 77 $8 bitmask: DIDR0.ADC3D \ ADC3 Digital input Disable
+ $4 constant DIDR0_ADC2D \ ADC2 Digital input Disable
+ 77 $4 bitmask: DIDR0.ADC2D \ ADC2 Digital input Disable
+ $2 constant DIDR0_ADC1D \ ADC1 Digital input Disable
+ 77 $2 bitmask: DIDR0.ADC1D \ ADC1 Digital input Disable
+ $1 constant DIDR0_ADC0D \ ADC0 Digital input Disable
+ 77 $1 bitmask: DIDR0.ADC0D \ ADC0 Digital input Disable
+$78 constant DIDR1 \ Digital Input Disable Register
+ $8 constant DIDR1_ACMP1MD \
+ 78 $8 bitmask: DIDR1.ACMP1MD \
+ $4 constant DIDR1_AMP0POSD \
+ 78 $4 bitmask: DIDR1.AMP0POSD \
+ $2 constant DIDR1_ADC10D \
+ 78 $2 bitmask: DIDR1.ADC10D \
+ $1 constant DIDR1_ADC9D \
+ 78 $1 bitmask: DIDR1.ADC9D \
+$79 constant AMP0CSR \
+ $80 constant AMP0CSR_AMP0EN \
+ 79 $80 bitmask: AMP0CSR.AMP0EN \
+ $40 constant AMP0CSR_AMP0IS \
+ 79 $40 bitmask: AMP0CSR.AMP0IS \
+ $30 constant AMP0CSR_AMP0G \
+ 79 $30 bitmask: AMP0CSR.AMP0G \
+ $8 constant AMP0CSR_AMP0GS \
+ 79 $8 bitmask: AMP0CSR.AMP0GS \
+ $3 constant AMP0CSR_AMP0TS \
+ 79 $3 bitmask: AMP0CSR.AMP0TS \
+\ ANALOG_COMPARATOR
+$7f constant AC3CON \ Analog Comparator3 Control Reg
+ $80 constant AC3CON_AC3EN \ Analog Comparator3 Enable Bit
+ 7f $80 bitmask: AC3CON.AC3EN \ Analog Comparator3 Enable Bit
+ $40 constant AC3CON_AC3IE \ Analog Comparator 3 Interrupt
+ 7f $40 bitmask: AC3CON.AC3IE \ Analog Comparator 3 Interrupt
+ $30 constant AC3CON_AC3IS \ Analog Comparator 3 Interrupt
+ 7f $30 bitmask: AC3CON.AC3IS \ Analog Comparator 3 Interrupt
+ $8 constant AC3CON_AC3OEA \ Analog Comparator 3 Alternate
+ 7f $8 bitmask: AC3CON.AC3OEA \ Analog Comparator 3 Alternate
+ $7 constant AC3CON_AC3M \ Analog Comparator 3 Multiplexe
+ 7f $7 bitmask: AC3CON.AC3M \ Analog Comparator 3 Multiplexe
+$7d constant AC1CON \ Analog Comparator 1 Control Re
+ $80 constant AC1CON_AC1EN \ Analog Comparator 1 Enable Bit
+ 7d $80 bitmask: AC1CON.AC1EN \ Analog Comparator 1 Enable Bit
+ $40 constant AC1CON_AC1IE \ Analog Comparator 1 Interrupt
+ 7d $40 bitmask: AC1CON.AC1IE \ Analog Comparator 1 Interrupt
+ $30 constant AC1CON_AC1IS \ Analog Comparator 1 Interrupt
+ 7d $30 bitmask: AC1CON.AC1IS \ Analog Comparator 1 Interrupt
+ $7 constant AC1CON_AC1M \ Analog Comparator 1 Multiplexe
+ 7d $7 bitmask: AC1CON.AC1M \ Analog Comparator 1 Multiplexe
+$7e constant AC2CON \ Analog Comparator 2 Control Re
+ $80 constant AC2CON_AC2EN \ Analog Comparator 2 Enable Bit
+ 7e $80 bitmask: AC2CON.AC2EN \ Analog Comparator 2 Enable Bit
+ $40 constant AC2CON_AC2IE \ Analog Comparator 2 Interrupt
+ 7e $40 bitmask: AC2CON.AC2IE \ Analog Comparator 2 Interrupt
+ $30 constant AC2CON_AC2IS \ Analog Comparator 2 Interrupt
+ 7e $30 bitmask: AC2CON.AC2IS \ Analog Comparator 2 Interrupt
+ $7 constant AC2CON_AC2M \ Analog Comparator 2 Multiplexe
+ 7e $7 bitmask: AC2CON.AC2M \ Analog Comparator 2 Multiplexe
+$20 constant ACSR \ Analog Comparator Status Regis
+ $80 constant ACSR_AC3IF \ Analog Comparator 3 Interrupt
+ 20 $80 bitmask: ACSR.AC3IF \ Analog Comparator 3 Interrupt
+ $40 constant ACSR_AC2IF \ Analog Comparator 2 Interrupt
+ 20 $40 bitmask: ACSR.AC2IF \ Analog Comparator 2 Interrupt
+ $20 constant ACSR_AC1IF \ Analog Comparator 1 Interrupt
+ 20 $20 bitmask: ACSR.AC1IF \ Analog Comparator 1 Interrupt
+ $8 constant ACSR_AC3O \ Analog Comparator 3 Output Bit
+ 20 $8 bitmask: ACSR.AC3O \ Analog Comparator 3 Output Bit
+ $4 constant ACSR_AC2O \ Analog Comparator 2 Output Bit
+ 20 $4 bitmask: ACSR.AC2O \ Analog Comparator 2 Output Bit
+ $2 constant ACSR_AC1O \ Analog Comparator 1 Output Bit
+ 20 $2 bitmask: ACSR.AC1O \ Analog Comparator 1 Output Bit
+$7c constant AC3ECON \
+ $20 constant AC3ECON_AC3OI \ Analog Comparator Ouput Invert
+ 7c $20 bitmask: AC3ECON.AC3OI \ Analog Comparator Ouput Invert
+ $10 constant AC3ECON_AC3OE \ Analog Comparator Ouput Enable
+ 7c $10 bitmask: AC3ECON.AC3OE \ Analog Comparator Ouput Enable
+ $7 constant AC3ECON_AC3H \ Analog Comparator Hysteresis S
+ 7c $7 bitmask: AC3ECON.AC3H \ Analog Comparator Hysteresis S
+$7b constant AC2ECON \
+ $20 constant AC2ECON_AC2OI \ Analog Comparator Ouput Invert
+ 7b $20 bitmask: AC2ECON.AC2OI \ Analog Comparator Ouput Invert
+ $10 constant AC2ECON_AC2OE \ Analog Comparator Ouput Enable
+ 7b $10 bitmask: AC2ECON.AC2OE \ Analog Comparator Ouput Enable
+ $7 constant AC2ECON_AC2H \ Analog Comparator Hysteresis S
+ 7b $7 bitmask: AC2ECON.AC2H \ Analog Comparator Hysteresis S
+$7a constant AC1ECON \
+ $20 constant AC1ECON_AC1OI \ Analog Comparator Ouput Invert
+ 7a $20 bitmask: AC1ECON.AC1OI \ Analog Comparator Ouput Invert
+ $10 constant AC1ECON_AC1OE \ Analog Comparator Ouput Enable
+ 7a $10 bitmask: AC1ECON.AC1OE \ Analog Comparator Ouput Enable
+ $8 constant AC1ECON_AC1ICE \ Analog Comparator Interrupt Ca
+ 7a $8 bitmask: AC1ECON.AC1ICE \ Analog Comparator Interrupt Ca
+ $7 constant AC1ECON_AC1H \ Analog Comparator Hysteresis S
+ 7a $7 bitmask: AC1ECON.AC1H \ Analog Comparator Hysteresis S
+\ CPU
+$5f constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ 5f $80 bitmask: SREG.I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ 5f $40 bitmask: SREG.T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ 5f $20 bitmask: SREG.H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ 5f $10 bitmask: SREG.S \ Sign Bit
+ $8 constant SREG_V \ Two's Complement Overflow Flag
+ 5f $8 bitmask: SREG.V \ Two's Complement Overflow Flag
+ $4 constant SREG_N \ Negative Flag
+ 5f $4 bitmask: SREG.N \ Negative Flag
+ $2 constant SREG_Z \ Zero Flag
+ 5f $2 bitmask: SREG.Z \ Zero Flag
+ $1 constant SREG_C \ Carry Flag
+ 5f $1 bitmask: SREG.C \ Carry Flag
+$5d constant SP \ Stack Pointer
+$55 constant MCUCR \ MCU Control Register
+ $10 constant MCUCR_PUD \ Pull-up disable
+ 55 $10 bitmask: MCUCR.PUD \ Pull-up disable
+ $8 constant MCUCR_RSTDIS \ Reset Pin Disable
+ 55 $8 bitmask: MCUCR.RSTDIS \ Reset Pin Disable
+ $4 constant MCUCR_CKRC81 \ Frequency Selection of the Cal
+ 55 $4 bitmask: MCUCR.CKRC81 \ Frequency Selection of the Cal
+ $2 constant MCUCR_IVSEL \ Interrupt Vector Select
+ 55 $2 bitmask: MCUCR.IVSEL \ Interrupt Vector Select
+ $1 constant MCUCR_IVCE \ Interrupt Vector Change Enable
+ 55 $1 bitmask: MCUCR.IVCE \ Interrupt Vector Change Enable
+$54 constant MCUSR \ MCU Status Register
+ $8 constant MCUSR_WDRF \ Watchdog Reset Flag
+ 54 $8 bitmask: MCUSR.WDRF \ Watchdog Reset Flag
+ $4 constant MCUSR_BORF \ Brown-out Reset Flag
+ 54 $4 bitmask: MCUSR.BORF \ Brown-out Reset Flag
+ $2 constant MCUSR_EXTRF \ External Reset Flag
+ 54 $2 bitmask: MCUSR.EXTRF \ External Reset Flag
+ $1 constant MCUSR_PORF \ Power-on reset flag
+ 54 $1 bitmask: MCUSR.PORF \ Power-on reset flag
+$88 constant OSCCAL \ Oscillator Calibration Value
+$83 constant CLKPR \
+ $80 constant CLKPR_CLKPCE \
+ 83 $80 bitmask: CLKPR.CLKPCE \
+ $f constant CLKPR_CLKPS \
+ 83 $f bitmask: CLKPR.CLKPS \
+$53 constant SMCR \ Sleep Mode Control Register
+ $e constant SMCR_SM \ Sleep Mode Select bits
+ 53 $e bitmask: SMCR.SM \ Sleep Mode Select bits
+ $1 constant SMCR_SE \ Sleep Enable
+ 53 $1 bitmask: SMCR.SE \ Sleep Enable
+$3b constant GPIOR2 \ General Purpose IO Register 2
+ $ff constant GPIOR2_GPIOR \ General Purpose IO Register 2
+ 3b $ff bitmask: GPIOR2.GPIOR \ General Purpose IO Register 2
+$3a constant GPIOR1 \ General Purpose IO Register 1
+ $ff constant GPIOR1_GPIOR \ General Purpose IO Register 1
+ 3a $ff bitmask: GPIOR1.GPIOR \ General Purpose IO Register 1
+$39 constant GPIOR0 \ General Purpose IO Register 0
+ $80 constant GPIOR0_GPIOR07 \ General Purpose IO Register 0
+ 39 $80 bitmask: GPIOR0.GPIOR07 \ General Purpose IO Register 0
+ $40 constant GPIOR0_GPIOR06 \ General Purpose IO Register 0
+ 39 $40 bitmask: GPIOR0.GPIOR06 \ General Purpose IO Register 0
+ $20 constant GPIOR0_GPIOR05 \ General Purpose IO Register 0
+ 39 $20 bitmask: GPIOR0.GPIOR05 \ General Purpose IO Register 0
+ $10 constant GPIOR0_GPIOR04 \ General Purpose IO Register 0
+ 39 $10 bitmask: GPIOR0.GPIOR04 \ General Purpose IO Register 0
+ $8 constant GPIOR0_GPIOR03 \ General Purpose IO Register 0
+ 39 $8 bitmask: GPIOR0.GPIOR03 \ General Purpose IO Register 0
+ $4 constant GPIOR0_GPIOR02 \ General Purpose IO Register 0
+ 39 $4 bitmask: GPIOR0.GPIOR02 \ General Purpose IO Register 0
+ $2 constant GPIOR0_GPIOR01 \ General Purpose IO Register 0
+ 39 $2 bitmask: GPIOR0.GPIOR01 \ General Purpose IO Register 0
+ $1 constant GPIOR0_GPIOR00 \ General Purpose IO Register 0
+ 39 $1 bitmask: GPIOR0.GPIOR00 \ General Purpose IO Register 0
+$87 constant PLLCSR \ PLL Control And Status Registe
+ $3c constant PLLCSR_PLLF \
+ 87 $3c bitmask: PLLCSR.PLLF \
+ $2 constant PLLCSR_PLLE \ PLL Enable
+ 87 $2 bitmask: PLLCSR.PLLE \ PLL Enable
+ $1 constant PLLCSR_PLOCK \ PLL Lock Detector
+ 87 $1 bitmask: PLLCSR.PLOCK \ PLL Lock Detector
+$86 constant PRR \ Power Reduction Register
+ $80 constant PRR_PRPSC2 \ Power Reduction PSC2
+ 86 $80 bitmask: PRR.PRPSC2 \ Power Reduction PSC2
+ $20 constant PRR_PRPSCR \ Power Reduction PSC0
+ 86 $20 bitmask: PRR.PRPSCR \ Power Reduction PSC0
+ $10 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
+ 86 $10 bitmask: PRR.PRTIM1 \ Power Reduction Timer/Counter1
+ $4 constant PRR_PRSPI \ Power Reduction Serial Periphe
+ 86 $4 bitmask: PRR.PRSPI \ Power Reduction Serial Periphe
+ $1 constant PRR_PRADC \ Power Reduction ADC
+ 86 $1 bitmask: PRR.PRADC \ Power Reduction ADC
+$84 constant CLKCSR \
+ $80 constant CLKCSR_CLKCCE \ Clock Control Change Enable
+ 84 $80 bitmask: CLKCSR.CLKCCE \ Clock Control Change Enable
+ $10 constant CLKCSR_CLKRDY \ Clock Ready Flag
+ 84 $10 bitmask: CLKCSR.CLKRDY \ Clock Ready Flag
+ $f constant CLKCSR_CLKC \ Clock Control
+ 84 $f bitmask: CLKCSR.CLKC \ Clock Control
+$85 constant CLKSELR \
+ $40 constant CLKSELR_COUT \ Clock OUT
+ 85 $40 bitmask: CLKSELR.COUT \ Clock OUT
+ $30 constant CLKSELR_CSUT \ Clock Start up Time
+ 85 $30 bitmask: CLKSELR.CSUT \ Clock Start up Time
+ $f constant CLKSELR_CKSEL \ Clock Source Select
+ 85 $f bitmask: CLKSELR.CKSEL \ Clock Source Select
+$81 constant BGCCR \ BandGap Current Calibration Re
+ $f constant BGCCR_BGCC \
+ 81 $f bitmask: BGCCR.BGCC \
+$80 constant BGCRR \ BandGap Resistor Calibration R
+ $f constant BGCRR_BGCR \
+ 80 $f bitmask: BGCRR.BGCR \
+\ EEPROM
+$3e constant EEAR \ EEPROM Read/Write Access Byte
+$3d constant EEDR \ EEPROM Data Register
+$3c constant EECR \ EEPROM Control Register
+ $80 constant EECR_NVMBSY \ None Volatile Busy Memory Busy
+ 3c $80 bitmask: EECR.NVMBSY \ None Volatile Busy Memory Busy
+ $40 constant EECR_EEPAGE \ EEPROM Page Access
+ 3c $40 bitmask: EECR.EEPAGE \ EEPROM Page Access
+ $30 constant EECR_EEPM \ EEPROM Programming Mode
+ 3c $30 bitmask: EECR.EEPM \ EEPROM Programming Mode
+ $8 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
+ 3c $8 bitmask: EECR.EERIE \ EEPROM Ready Interrupt Enable
+ $4 constant EECR_EEMWE \ EEPROM Master Write Enable
+ 3c $4 bitmask: EECR.EEMWE \ EEPROM Master Write Enable
+ $2 constant EECR_EEWE \ EEPROM Write Enable
+ 3c $2 bitmask: EECR.EEWE \ EEPROM Write Enable
+ $1 constant EECR_EERE \ EEPROM Read Enable
+ 3c $1 bitmask: EECR.EERE \ EEPROM Read Enable
+\ PSC0
+$68 constant PICR0 \ PSC 0 Input Capture Register
+$63 constant PFRC0B \ PSC 0 Input B Control
+ $80 constant PFRC0B_PCAE0B \ PSC 0 Capture Enable Input Par
+ 63 $80 bitmask: PFRC0B.PCAE0B \ PSC 0 Capture Enable Input Par
+ $40 constant PFRC0B_PISEL0B \ PSC 0 Input Select for Part B
+ 63 $40 bitmask: PFRC0B.PISEL0B \ PSC 0 Input Select for Part B
+ $20 constant PFRC0B_PELEV0B \ PSC 0 Edge Level Selector on I
+ 63 $20 bitmask: PFRC0B.PELEV0B \ PSC 0 Edge Level Selector on I
+ $10 constant PFRC0B_PFLTE0B \ PSC 0 Filter Enable on Input P
+ 63 $10 bitmask: PFRC0B.PFLTE0B \ PSC 0 Filter Enable on Input P
+ $f constant PFRC0B_PRFM0B \ PSC 0 Retrigger and Fault Mode
+ 63 $f bitmask: PFRC0B.PRFM0B \ PSC 0 Retrigger and Fault Mode
+$62 constant PFRC0A \ PSC 0 Input A Control
+ $80 constant PFRC0A_PCAE0A \ PSC 0 Capture Enable Input Par
+ 62 $80 bitmask: PFRC0A.PCAE0A \ PSC 0 Capture Enable Input Par
+ $40 constant PFRC0A_PISEL0A \ PSC 0 Input Select for Part A
+ 62 $40 bitmask: PFRC0A.PISEL0A \ PSC 0 Input Select for Part A
+ $20 constant PFRC0A_PELEV0A \ PSC 0 Edge Level Selector on I
+ 62 $20 bitmask: PFRC0A.PELEV0A \ PSC 0 Edge Level Selector on I
+ $10 constant PFRC0A_PFLTE0A \ PSC 0 Filter Enable on Input P
+ 62 $10 bitmask: PFRC0A.PFLTE0A \ PSC 0 Filter Enable on Input P
+ $f constant PFRC0A_PRFM0A \ PSC 0 Retrigger and Fault Mode
+ 62 $f bitmask: PFRC0A.PRFM0A \ PSC 0 Retrigger and Fault Mode
+$32 constant PCTL0 \ PSC 0 Control Register
+ $c0 constant PCTL0_PPRE0 \ PSC 0 Prescaler Selects
+ 32 $c0 bitmask: PCTL0.PPRE0 \ PSC 0 Prescaler Selects
+ $24 constant PCTL0_PBFM0 \ PSC 0 Balance Flank Width Modu
+ 32 $24 bitmask: PCTL0.PBFM0 \ PSC 0 Balance Flank Width Modu
+ $10 constant PCTL0_PAOC0B \ PSC 0 Asynchronous Output Cont
+ 32 $10 bitmask: PCTL0.PAOC0B \ PSC 0 Asynchronous Output Cont
+ $8 constant PCTL0_PAOC0A \ PSC 0 Asynchronous Output Cont
+ 32 $8 bitmask: PCTL0.PAOC0A \ PSC 0 Asynchronous Output Cont
+ $2 constant PCTL0_PCCYC0 \ PSC0 Complete Cycle
+ 32 $2 bitmask: PCTL0.PCCYC0 \ PSC0 Complete Cycle
+ $1 constant PCTL0_PRUN0 \ PSC 0 Run
+ 32 $1 bitmask: PCTL0.PRUN0 \ PSC 0 Run
+$31 constant PCNF0 \ PSC 0 Configuration Register
+ $80 constant PCNF0_PFIFTY0 \ PSC 0 Fifty
+ 31 $80 bitmask: PCNF0.PFIFTY0 \ PSC 0 Fifty
+ $40 constant PCNF0_PALOCK0 \ PSC 0 Autolock
+ 31 $40 bitmask: PCNF0.PALOCK0 \ PSC 0 Autolock
+ $20 constant PCNF0_PLOCK0 \ PSC 0 Lock
+ 31 $20 bitmask: PCNF0.PLOCK0 \ PSC 0 Lock
+ $18 constant PCNF0_PMODE0 \ PSC 0 Mode
+ 31 $18 bitmask: PCNF0.PMODE0 \ PSC 0 Mode
+ $4 constant PCNF0_POP0 \ PSC 0 Output Polarity
+ 31 $4 bitmask: PCNF0.POP0 \ PSC 0 Output Polarity
+ $2 constant PCNF0_PCLKSEL0 \ PSC 0 Input Clock Select
+ 31 $2 bitmask: PCNF0.PCLKSEL0 \ PSC 0 Input Clock Select
+$44 constant OCR0RB \ Output Compare RB Register
+$42 constant OCR0SB \ Output Compare SB Register
+$4a constant OCR0RA \ Output Compare RA Register
+$60 constant OCR0SA \ Output Compare SA Register
+$6a constant PSOC0 \ PSC0 Synchro and Output Config
+ $80 constant PSOC0_PISEL0A1 \ PSC Input Select
+ 6a $80 bitmask: PSOC0.PISEL0A1 \ PSC Input Select
+ $40 constant PSOC0_PISEL0B1 \ PSC Input Select
+ 6a $40 bitmask: PSOC0.PISEL0B1 \ PSC Input Select
+ $30 constant PSOC0_PSYNC0 \ Synchronisation out for ADC se
+ 6a $30 bitmask: PSOC0.PSYNC0 \ Synchronisation out for ADC se
+ $4 constant PSOC0_POEN0B \ PSCOUT01 Output Enable
+ 6a $4 bitmask: PSOC0.POEN0B \ PSCOUT01 Output Enable
+ $1 constant PSOC0_POEN0A \ PSCOUT00 Output Enable
+ 6a $1 bitmask: PSOC0.POEN0A \ PSCOUT00 Output Enable
+$2f constant PIM0 \ PSC0 Interrupt Mask Register
+ $10 constant PIM0_PEVE0B \ External Event B Interrupt Ena
+ 2f $10 bitmask: PIM0.PEVE0B \ External Event B Interrupt Ena
+ $8 constant PIM0_PEVE0A \ External Event A Interrupt Ena
+ 2f $8 bitmask: PIM0.PEVE0A \ External Event A Interrupt Ena
+ $2 constant PIM0_PEOEPE0 \ End of Enhanced Cycle Enable
+ 2f $2 bitmask: PIM0.PEOEPE0 \ End of Enhanced Cycle Enable
+ $1 constant PIM0_PEOPE0 \ End of Cycle Interrupt Enable
+ 2f $1 bitmask: PIM0.PEOPE0 \ End of Cycle Interrupt Enable
+$30 constant PIFR0 \ PSC0 Interrupt Flag Register
+ $80 constant PIFR0_POAC0B \ PSC 0 Output A Activity
+ 30 $80 bitmask: PIFR0.POAC0B \ PSC 0 Output A Activity
+ $40 constant PIFR0_POAC0A \ PSC 0 Output A Activity
+ 30 $40 bitmask: PIFR0.POAC0A \ PSC 0 Output A Activity
+ $10 constant PIFR0_PEV0B \ External Event B Interrupt
+ 30 $10 bitmask: PIFR0.PEV0B \ External Event B Interrupt
+ $8 constant PIFR0_PEV0A \ External Event A Interrupt
+ 30 $8 bitmask: PIFR0.PEV0A \ External Event A Interrupt
+ $6 constant PIFR0_PRN0 \ Ramp Number
+ 30 $6 bitmask: PIFR0.PRN0 \ Ramp Number
+ $1 constant PIFR0_PEOP0 \ End of PSC0 Interrupt
+ 30 $1 bitmask: PIFR0.PEOP0 \ End of PSC0 Interrupt
+\ PSC2
+$6d constant PICR2H \ PSC 2 Input Capture Register H
+ $80 constant PICR2H_PCST2 \ PSC 2 Capture Software Trigger
+ 6d $80 bitmask: PICR2H.PCST2 \ PSC 2 Capture Software Trigger
+ $c constant PICR2H_PICR21 \
+ 6d $c bitmask: PICR2H.PICR21 \
+ $3 constant PICR2H_PICR2 \
+ 6d $3 bitmask: PICR2H.PICR2 \
+$6c constant PICR2L \ PSC 2 Input Capture Register L
+$67 constant PFRC2B \ PSC 2 Input B Control
+ $80 constant PFRC2B_PCAE2B \ PSC 2 Capture Enable Input Par
+ 67 $80 bitmask: PFRC2B.PCAE2B \ PSC 2 Capture Enable Input Par
+ $40 constant PFRC2B_PISEL2B \ PSC 2 Input Select for Part B
+ 67 $40 bitmask: PFRC2B.PISEL2B \ PSC 2 Input Select for Part B
+ $20 constant PFRC2B_PELEV2B \ PSC 2 Edge Level Selector on I
+ 67 $20 bitmask: PFRC2B.PELEV2B \ PSC 2 Edge Level Selector on I
+ $10 constant PFRC2B_PFLTE2B \ PSC 2 Filter Enable on Input P
+ 67 $10 bitmask: PFRC2B.PFLTE2B \ PSC 2 Filter Enable on Input P
+ $f constant PFRC2B_PRFM2B \ PSC 2 Retrigger and Fault Mode
+ 67 $f bitmask: PFRC2B.PRFM2B \ PSC 2 Retrigger and Fault Mode
+$66 constant PFRC2A \ PSC 2 Input B Control
+ $80 constant PFRC2A_PCAE2A \ PSC 2 Capture Enable Input Par
+ 66 $80 bitmask: PFRC2A.PCAE2A \ PSC 2 Capture Enable Input Par
+ $40 constant PFRC2A_PISEL2A \ PSC 2 Input Select for Part A
+ 66 $40 bitmask: PFRC2A.PISEL2A \ PSC 2 Input Select for Part A
+ $20 constant PFRC2A_PELEV2A \ PSC 2 Edge Level Selector on I
+ 66 $20 bitmask: PFRC2A.PELEV2A \ PSC 2 Edge Level Selector on I
+ $10 constant PFRC2A_PFLTE2A \ PSC 2 Filter Enable on Input P
+ 66 $10 bitmask: PFRC2A.PFLTE2A \ PSC 2 Filter Enable on Input P
+ $f constant PFRC2A_PRFM2A \ PSC 2 Retrigger and Fault Mode
+ 66 $f bitmask: PFRC2A.PRFM2A \ PSC 2 Retrigger and Fault Mode
+$36 constant PCTL2 \ PSC 2 Control Register
+ $c0 constant PCTL2_PPRE2 \ PSC 2 Prescaler Selects
+ 36 $c0 bitmask: PCTL2.PPRE2 \ PSC 2 Prescaler Selects
+ $20 constant PCTL2_PBFM2 \ Balance Flank Width Modulation
+ 36 $20 bitmask: PCTL2.PBFM2 \ Balance Flank Width Modulation
+ $10 constant PCTL2_PAOC2B \ PSC 2 Asynchronous Output Cont
+ 36 $10 bitmask: PCTL2.PAOC2B \ PSC 2 Asynchronous Output Cont
+ $8 constant PCTL2_PAOC2A \ PSC 2 Asynchronous Output Cont
+ 36 $8 bitmask: PCTL2.PAOC2A \ PSC 2 Asynchronous Output Cont
+ $4 constant PCTL2_PARUN2 \ PSC2 Auto Run
+ 36 $4 bitmask: PCTL2.PARUN2 \ PSC2 Auto Run
+ $2 constant PCTL2_PCCYC2 \ PSC2 Complete Cycle
+ 36 $2 bitmask: PCTL2.PCCYC2 \ PSC2 Complete Cycle
+ $1 constant PCTL2_PRUN2 \ PSC 2 Run
+ 36 $1 bitmask: PCTL2.PRUN2 \ PSC 2 Run
+$35 constant PCNF2 \ PSC 2 Configuration Register
+ $80 constant PCNF2_PFIFTY2 \ PSC 2 Fifty
+ 35 $80 bitmask: PCNF2.PFIFTY2 \ PSC 2 Fifty
+ $40 constant PCNF2_PALOCK2 \ PSC 2 Autolock
+ 35 $40 bitmask: PCNF2.PALOCK2 \ PSC 2 Autolock
+ $20 constant PCNF2_PLOCK2 \ PSC 2 Lock
+ 35 $20 bitmask: PCNF2.PLOCK2 \ PSC 2 Lock
+ $18 constant PCNF2_PMODE2 \ PSC 2 Mode
+ 35 $18 bitmask: PCNF2.PMODE2 \ PSC 2 Mode
+ $4 constant PCNF2_POP2 \ PSC 2 Output Polarity
+ 35 $4 bitmask: PCNF2.POP2 \ PSC 2 Output Polarity
+ $2 constant PCNF2_PCLKSEL2 \ PSC 2 Input Clock Select
+ 35 $2 bitmask: PCNF2.PCLKSEL2 \ PSC 2 Input Clock Select
+ $1 constant PCNF2_POME2 \ PSC 2 Output Matrix Enable
+ 35 $1 bitmask: PCNF2.POME2 \ PSC 2 Output Matrix Enable
+$70 constant PCNFE2 \ PSC 2 Enhanced Configuration R
+ $e0 constant PCNFE2_PASDLK2 \
+ 70 $e0 bitmask: PCNFE2.PASDLK2 \
+ $10 constant PCNFE2_PBFM21 \
+ 70 $10 bitmask: PCNFE2.PBFM21 \
+ $8 constant PCNFE2_PELEV2A1 \
+ 70 $8 bitmask: PCNFE2.PELEV2A1 \
+ $4 constant PCNFE2_PELEV2B1 \
+ 70 $4 bitmask: PCNFE2.PELEV2B1 \
+ $2 constant PCNFE2_PISEL2A1 \
+ 70 $2 bitmask: PCNFE2.PISEL2A1 \
+ $1 constant PCNFE2_PISEL2B1 \
+ 70 $1 bitmask: PCNFE2.PISEL2B1 \
+$48 constant OCR2RB \ Output Compare RB Register
+$46 constant OCR2SB \ Output Compare SB Register
+$4e constant OCR2RA \ Output Compare RA Register
+$64 constant OCR2SA \ Output Compare SA Register
+$6f constant POM2 \ PSC 2 Output Matrix
+ $f0 constant POM2_POMV2B \ Output Matrix Output B Ramps
+ 6f $f0 bitmask: POM2.POMV2B \ Output Matrix Output B Ramps
+ $f constant POM2_POMV2A \ Output Matrix Output A Ramps
+ 6f $f bitmask: POM2.POMV2A \ Output Matrix Output A Ramps
+$6e constant PSOC2 \ PSC2 Synchro and Output Config
+ $c0 constant PSOC2_POS2 \ PSC 2 Output 23 Select
+ 6e $c0 bitmask: PSOC2.POS2 \ PSC 2 Output 23 Select
+ $30 constant PSOC2_PSYNC2 \ Synchronization Out for ADC Se
+ 6e $30 bitmask: PSOC2.PSYNC2 \ Synchronization Out for ADC Se
+ $8 constant PSOC2_POEN2D \ PSCOUT23 Output Enable
+ 6e $8 bitmask: PSOC2.POEN2D \ PSCOUT23 Output Enable
+ $4 constant PSOC2_POEN2B \ PSCOUT21 Output Enable
+ 6e $4 bitmask: PSOC2.POEN2B \ PSCOUT21 Output Enable
+ $2 constant PSOC2_POEN2C \ PSCOUT22 Output Enable
+ 6e $2 bitmask: PSOC2.POEN2C \ PSCOUT22 Output Enable
+ $1 constant PSOC2_POEN2A \ PSCOUT20 Output Enable
+ 6e $1 bitmask: PSOC2.POEN2A \ PSCOUT20 Output Enable
+$33 constant PIM2 \ PSC2 Interrupt Mask Register
+ $20 constant PIM2_PSEIE2 \ PSC 2 Synchro Error Interrupt
+ 33 $20 bitmask: PIM2.PSEIE2 \ PSC 2 Synchro Error Interrupt
+ $10 constant PIM2_PEVE2B \ External Event B Interrupt Ena
+ 33 $10 bitmask: PIM2.PEVE2B \ External Event B Interrupt Ena
+ $8 constant PIM2_PEVE2A \ External Event A Interrupt Ena
+ 33 $8 bitmask: PIM2.PEVE2A \ External Event A Interrupt Ena
+ $2 constant PIM2_PEOEPE2 \ End of Enhanced Cycle Interrup
+ 33 $2 bitmask: PIM2.PEOEPE2 \ End of Enhanced Cycle Interrup
+ $1 constant PIM2_PEOPE2 \ End of Cycle Interrupt Enable
+ 33 $1 bitmask: PIM2.PEOPE2 \ End of Cycle Interrupt Enable
+$34 constant PIFR2 \ PSC2 Interrupt Flag Register
+ $80 constant PIFR2_POAC2B \ PSC 2 Output A Activity
+ 34 $80 bitmask: PIFR2.POAC2B \ PSC 2 Output A Activity
+ $40 constant PIFR2_POAC2A \ PSC 2 Output A Activity
+ 34 $40 bitmask: PIFR2.POAC2A \ PSC 2 Output A Activity
+ $20 constant PIFR2_PSEI2 \ PSC 2 Synchro Error Interrupt
+ 34 $20 bitmask: PIFR2.PSEI2 \ PSC 2 Synchro Error Interrupt
+ $10 constant PIFR2_PEV2B \ External Event B Interrupt
+ 34 $10 bitmask: PIFR2.PEV2B \ External Event B Interrupt
+ $8 constant PIFR2_PEV2A \ External Event A Interrupt
+ 34 $8 bitmask: PIFR2.PEV2A \ External Event A Interrupt
+ $6 constant PIFR2_PRN2 \ Ramp Number
+ 34 $6 bitmask: PIFR2.PRN2 \ Ramp Number
+ $1 constant PIFR2_PEOP2 \ End of PSC2 Interrupt
+ 34 $1 bitmask: PIFR2.PEOP2 \ End of PSC2 Interrupt
+$71 constant PASDLY2 \ Analog Synchronization Delay R
+\ TIMER_COUNTER_1
+$21 constant TIMSK1 \ Timer/Counter Interrupt Mask R
+ $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture I
+ 21 $20 bitmask: TIMSK1.ICIE1 \ Timer/Counter1 Input Capture I
+ $1 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interr
+ 21 $1 bitmask: TIMSK1.TOIE1 \ Timer/Counter1 Overflow Interr
+$22 constant TIFR1 \ Timer/Counter Interrupt Flag r
+ $20 constant TIFR1_ICF1 \ Input Capture Flag 1
+ 22 $20 bitmask: TIFR1.ICF1 \ Input Capture Flag 1
+ $1 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
+ 22 $1 bitmask: TIFR1.TOV1 \ Timer/Counter1 Overflow Flag
+$8a constant TCCR1B \ Timer/Counter1 Control Registe
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
+ 8a $80 bitmask: TCCR1B.ICNC1 \ Input Capture 1 Noise Canceler
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ 8a $40 bitmask: TCCR1B.ICES1 \ Input Capture 1 Edge Select
+ $10 constant TCCR1B_WGM13 \ Waveform Generation Mode
+ 8a $10 bitmask: TCCR1B.WGM13 \ Waveform Generation Mode
+ $7 constant TCCR1B_CS1 \ Prescaler source of Timer/Coun
+ 8a $7 bitmask: TCCR1B.CS1 \ Prescaler source of Timer/Coun
+$5a constant TCNT1 \ Timer/Counter1 Bytes
+$8c constant ICR1 \ Timer/Counter1 Input Capture R
+\ BOOT_LOAD
+$57 constant SPMCSR \ Store Program Memory Control R
+ $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
+ 57 $80 bitmask: SPMCSR.SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
+ 57 $40 bitmask: SPMCSR.RWWSB \ Read While Write Section Busy
+ $20 constant SPMCSR_SIGRD \ Signature Row Read
+ 57 $20 bitmask: SPMCSR.SIGRD \ Signature Row Read
+ $10 constant SPMCSR_RWWSRE \ Read While Write section read
+ 57 $10 bitmask: SPMCSR.RWWSRE \ Read While Write section read
+ $8 constant SPMCSR_BLBSET \ Boot Lock Bit Set
+ 57 $8 bitmask: SPMCSR.BLBSET \ Boot Lock Bit Set
+ $4 constant SPMCSR_PGWRT \ Page Write
+ 57 $4 bitmask: SPMCSR.PGWRT \ Page Write
+ $2 constant SPMCSR_PGERS \ Page Erase
+ 57 $2 bitmask: SPMCSR.PGERS \ Page Erase
+ $1 constant SPMCSR_SPMEN \ Store Program Memory Enable
+ 57 $1 bitmask: SPMCSR.SPMEN \ Store Program Memory Enable
diff --git a/amforth-6.5/avr8/devices/at90pwm161/device.py b/amforth-6.5/avr8/devices/at90pwm161/device.py
new file mode 100644
index 0000000..6a000b9
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90pwm161/device.py
@@ -0,0 +1,389 @@
+# Generated Automatically
+
+# Partname AT90PWM161
+
+MCUREGS = {
+# Interrupt Vectors
+ 'PSC2_CAPTAddr' : '#2', # PSC2 Capture Event
+ 'PSC2_ECAddr' : '#4', # PSC2 End Cycle
+ 'PSC2_EECAddr' : '#6', # PSC2 End Of Enhanced Cycle
+ 'PSC0_CAPTAddr' : '#8', # PSC0 Capture Event
+ 'PSC0_ECAddr' : '#10', # PSC0 End Cycle
+ 'PSC0_EECAddr' : '#12', # PSC0 End Of Enhanced Cycle
+ 'ANALOG_COMP_1Addr' : '#14', # Analog Comparator 1
+ 'ANALOG_COMP_2Addr' : '#16', # Analog Comparator 2
+ 'ANALOG_COMP_3Addr' : '#18', # Analog Comparator 3
+ 'INT0Addr' : '#20', # External Interrupt Request 0
+ 'TIMER1_CAPTAddr' : '#22', # Timer/Counter1 Capture Event
+ 'TIMER1_OVFAddr' : '#24', # Timer/Counter1 Overflow
+ 'ADCAddr' : '#26', # ADC Conversion Complete
+ 'INT1Addr' : '#28', # External Interrupt Request 1
+ 'SPI_STCAddr' : '#30', # SPI Serial Transfer Complet
+ 'INT2Addr' : '#32', # External Interrupt Request 2
+ 'WDTAddr' : '#34', # Watchdog Timeout Interrupt
+ 'EE_READYAddr' : '#36', # EEPROM Ready
+ 'SPM_READYAddr' : '#38', # Store Program Memory Read
+
+# Module PORTB
+ 'PORTB' : '$25', # Port B Data Register
+ 'DDRB' : '$24', # Port B Data Direction Register
+ 'PINB' : '$23', # Port B Input Pins
+
+# Module PORTD
+ 'PORTD' : '$2b', # Port D Data Register
+ 'DDRD' : '$2a', # Port D Data Direction Register
+ 'PIND' : '$29', # Port D Input Pins
+
+# Module DA_CONVERTER
+ 'DACH' : '$59', # DAC Data Register High Byte
+ 'DACH_DACH': '$ff', # DAC Data Register High Byte Bi
+ 'DACL' : '$58', # DAC Data Register Low Byte
+ 'DACL_DACL': '$ff', # DAC Data Register Low Byte Bit
+ 'DACON' : '$76', # DAC Control Register
+ 'DACON_DAATE': '$80', # DAC Auto Trigger Enable Bit
+ 'DACON_DATS': '$70', # DAC Trigger Selection Bits
+ 'DACON_DALA': '$4', # DAC Left Adjust
+ 'DACON_DAEN': '$1', # DAC Enable Bit
+
+# Module PORTE
+ 'PORTE' : '$2e', # Port E Data Register
+ 'DDRE' : '$2d', # Port E Data Direction Register
+ 'PINE' : '$2c', # Port E Input Pins
+
+# Module SPI
+ 'SPCR' : '$37', # SPI Control Register
+ 'SPCR_SPIE': '$80', # SPI Interrupt Enable
+ 'SPCR_SPE': '$40', # SPI Enable
+ 'SPCR_DORD': '$20', # Data Order
+ 'SPCR_MSTR': '$10', # Master/Slave Select
+ 'SPCR_CPOL': '$8', # Clock polarity
+ 'SPCR_CPHA': '$4', # Clock Phase
+ 'SPCR_SPR': '$3', # SPI Clock Rate Selects
+ 'SPSR' : '$38', # SPI Status Register
+ 'SPSR_SPIF': '$80', # SPI Interrupt Flag
+ 'SPSR_WCOL': '$40', # Write Collision Flag
+ 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
+ 'SPDR' : '$56', # SPI Data Register
+
+# Module WATCHDOG
+ 'WDTCSR' : '$82', # Watchdog Timer Control Registe
+ 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
+ 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
+ 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
+ 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
+ 'WDTCSR_WDE': '$8', # Watch Dog Enable
+
+# Module EXTERNAL_INTERRUPT
+ 'EICRA' : '$89', # External Interrupt Control Reg
+ 'EICRA_ISC2': '$30', # External Interrupt Sense Contr
+ 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
+ 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
+ 'EIMSK' : '$41', # External Interrupt Mask Regist
+ 'EIMSK_INT': '$7', # External Interrupt Request 2 E
+ 'EIFR' : '$40', # External Interrupt Flag Regist
+ 'EIFR_INTF': '$7', # External Interrupt Flags
+
+# Module AD_CONVERTER
+ 'ADMUX' : '$28', # The ADC multiplexer Selection
+ 'ADMUX_REFS': '$c0', # Reference Selection Bits
+ 'ADMUX_ADLAR': '$20', # Left Adjust Result
+ 'ADMUX_MUX': '$f', # Analog Channel and Gain Select
+ 'ADCSRA' : '$26', # The ADC Control and Status reg
+ 'ADCSRA_ADEN': '$80', # ADC Enable
+ 'ADCSRA_ADSC': '$40', # ADC Start Conversion
+ 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
+ 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
+ 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
+ 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
+ 'ADC' : '$4c', # ADC Data Register Bytes
+ 'ADCSRB' : '$27', # ADC Control and Status Registe
+ 'ADCSRB_ADHSM': '$80', # ADC High Speed Mode
+ 'ADCSRB_ADNCDIS': '$40', # ADC Noise Canceller Disable
+ 'ADCSRB_ADSSEN': '$10', # ADC Single Shot Enable on PSC'
+ 'ADCSRB_ADTS': '$f', # ADC Auto Trigger Sources
+ 'DIDR0' : '$77', # Digital Input Disable Register
+ 'DIDR0_ADC7D': '$80', #
+ 'DIDR0_ADC6D': '$40', # ADC7 Digital input Disable
+ 'DIDR0_ADC5D': '$20', # ADC5 Digital input Disable
+ 'DIDR0_ADC4D': '$10', # ADC4 Digital input Disable
+ 'DIDR0_ADC3D': '$8', # ADC3 Digital input Disable
+ 'DIDR0_ADC2D': '$4', # ADC2 Digital input Disable
+ 'DIDR0_ADC1D': '$2', # ADC1 Digital input Disable
+ 'DIDR0_ADC0D': '$1', # ADC0 Digital input Disable
+ 'DIDR1' : '$78', # Digital Input Disable Register
+ 'DIDR1_ACMP1MD': '$8', #
+ 'DIDR1_AMP0POSD': '$4', #
+ 'DIDR1_ADC10D': '$2', #
+ 'DIDR1_ADC9D': '$1', #
+ 'AMP0CSR' : '$79', #
+ 'AMP0CSR_AMP0EN': '$80', #
+ 'AMP0CSR_AMP0IS': '$40', #
+ 'AMP0CSR_AMP0G': '$30', #
+ 'AMP0CSR_AMP0GS': '$8', #
+ 'AMP0CSR_AMP0TS': '$3', #
+
+# Module ANALOG_COMPARATOR
+ 'AC3CON' : '$7f', # Analog Comparator3 Control Reg
+ 'AC3CON_AC3EN': '$80', # Analog Comparator3 Enable Bit
+ 'AC3CON_AC3IE': '$40', # Analog Comparator 3 Interrupt
+ 'AC3CON_AC3IS': '$30', # Analog Comparator 3 Interrupt
+ 'AC3CON_AC3OEA': '$8', # Analog Comparator 3 Alternate
+ 'AC3CON_AC3M': '$7', # Analog Comparator 3 Multiplexe
+ 'AC1CON' : '$7d', # Analog Comparator 1 Control Re
+ 'AC1CON_AC1EN': '$80', # Analog Comparator 1 Enable Bit
+ 'AC1CON_AC1IE': '$40', # Analog Comparator 1 Interrupt
+ 'AC1CON_AC1IS': '$30', # Analog Comparator 1 Interrupt
+ 'AC1CON_AC1M': '$7', # Analog Comparator 1 Multiplexe
+ 'AC2CON' : '$7e', # Analog Comparator 2 Control Re
+ 'AC2CON_AC2EN': '$80', # Analog Comparator 2 Enable Bit
+ 'AC2CON_AC2IE': '$40', # Analog Comparator 2 Interrupt
+ 'AC2CON_AC2IS': '$30', # Analog Comparator 2 Interrupt
+ 'AC2CON_AC2M': '$7', # Analog Comparator 2 Multiplexe
+ 'ACSR' : '$20', # Analog Comparator Status Regis
+ 'ACSR_AC3IF': '$80', # Analog Comparator 3 Interrupt
+ 'ACSR_AC2IF': '$40', # Analog Comparator 2 Interrupt
+ 'ACSR_AC1IF': '$20', # Analog Comparator 1 Interrupt
+ 'ACSR_AC3O': '$8', # Analog Comparator 3 Output Bit
+ 'ACSR_AC2O': '$4', # Analog Comparator 2 Output Bit
+ 'ACSR_AC1O': '$2', # Analog Comparator 1 Output Bit
+ 'AC3ECON' : '$7c', #
+ 'AC3ECON_AC3OI': '$20', # Analog Comparator Ouput Invert
+ 'AC3ECON_AC3OE': '$10', # Analog Comparator Ouput Enable
+ 'AC3ECON_AC3H': '$7', # Analog Comparator Hysteresis S
+ 'AC2ECON' : '$7b', #
+ 'AC2ECON_AC2OI': '$20', # Analog Comparator Ouput Invert
+ 'AC2ECON_AC2OE': '$10', # Analog Comparator Ouput Enable
+ 'AC2ECON_AC2H': '$7', # Analog Comparator Hysteresis S
+ 'AC1ECON' : '$7a', #
+ 'AC1ECON_AC1OI': '$20', # Analog Comparator Ouput Invert
+ 'AC1ECON_AC1OE': '$10', # Analog Comparator Ouput Enable
+ 'AC1ECON_AC1ICE': '$8', # Analog Comparator Interrupt Ca
+ 'AC1ECON_AC1H': '$7', # Analog Comparator Hysteresis S
+
+# Module CPU
+ 'SREG' : '$5f', # Status Register
+ 'SREG_I': '$80', # Global Interrupt Enable
+ 'SREG_T': '$40', # Bit Copy Storage
+ 'SREG_H': '$20', # Half Carry Flag
+ 'SREG_S': '$10', # Sign Bit
+ 'SREG_V': '$8', # Two's Complement Overflow Flag
+ 'SREG_N': '$4', # Negative Flag
+ 'SREG_Z': '$2', # Zero Flag
+ 'SREG_C': '$1', # Carry Flag
+ 'SP' : '$5d', # Stack Pointer
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_PUD': '$10', # Pull-up disable
+ 'MCUCR_RSTDIS': '$8', # Reset Pin Disable
+ 'MCUCR_CKRC81': '$4', # Frequency Selection of the Cal
+ 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
+ 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
+ 'MCUSR_BORF': '$4', # Brown-out Reset Flag
+ 'MCUSR_EXTRF': '$2', # External Reset Flag
+ 'MCUSR_PORF': '$1', # Power-on reset flag
+ 'OSCCAL' : '$88', # Oscillator Calibration Value
+ 'CLKPR' : '$83', #
+ 'CLKPR_CLKPCE': '$80', #
+ 'CLKPR_CLKPS': '$f', #
+ 'SMCR' : '$53', # Sleep Mode Control Register
+ 'SMCR_SM': '$e', # Sleep Mode Select bits
+ 'SMCR_SE': '$1', # Sleep Enable
+ 'GPIOR2' : '$3b', # General Purpose IO Register 2
+ 'GPIOR2_GPIOR': '$ff', # General Purpose IO Register 2
+ 'GPIOR1' : '$3a', # General Purpose IO Register 1
+ 'GPIOR1_GPIOR': '$ff', # General Purpose IO Register 1
+ 'GPIOR0' : '$39', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR07': '$80', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR06': '$40', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR05': '$20', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR04': '$10', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR03': '$8', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR02': '$4', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR01': '$2', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR00': '$1', # General Purpose IO Register 0
+ 'PLLCSR' : '$87', # PLL Control And Status Registe
+ 'PLLCSR_PLLF': '$3c', #
+ 'PLLCSR_PLLE': '$2', # PLL Enable
+ 'PLLCSR_PLOCK': '$1', # PLL Lock Detector
+ 'PRR' : '$86', # Power Reduction Register
+ 'PRR_PRPSC2': '$80', # Power Reduction PSC2
+ 'PRR_PRPSCR': '$20', # Power Reduction PSC0
+ 'PRR_PRTIM1': '$10', # Power Reduction Timer/Counter1
+ 'PRR_PRSPI': '$4', # Power Reduction Serial Periphe
+ 'PRR_PRADC': '$1', # Power Reduction ADC
+ 'CLKCSR' : '$84', #
+ 'CLKCSR_CLKCCE': '$80', # Clock Control Change Enable
+ 'CLKCSR_CLKRDY': '$10', # Clock Ready Flag
+ 'CLKCSR_CLKC': '$f', # Clock Control
+ 'CLKSELR' : '$85', #
+ 'CLKSELR_COUT': '$40', # Clock OUT
+ 'CLKSELR_CSUT': '$30', # Clock Start up Time
+ 'CLKSELR_CKSEL': '$f', # Clock Source Select
+ 'BGCCR' : '$81', # BandGap Current Calibration Re
+ 'BGCCR_BGCC': '$f', #
+ 'BGCRR' : '$80', # BandGap Resistor Calibration R
+ 'BGCRR_BGCR': '$f', #
+
+# Module EEPROM
+ 'EEAR' : '$3e', # EEPROM Read/Write Access Byte
+ 'EEDR' : '$3d', # EEPROM Data Register
+ 'EECR' : '$3c', # EEPROM Control Register
+ 'EECR_NVMBSY': '$80', # None Volatile Busy Memory Busy
+ 'EECR_EEPAGE': '$40', # EEPROM Page Access
+ 'EECR_EEPM': '$30', # EEPROM Programming Mode
+ 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
+ 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
+ 'EECR_EEWE': '$2', # EEPROM Write Enable
+ 'EECR_EERE': '$1', # EEPROM Read Enable
+
+# Module PSC0
+ 'PICR0' : '$68', # PSC 0 Input Capture Register
+ 'PFRC0B' : '$63', # PSC 0 Input B Control
+ 'PFRC0B_PCAE0B': '$80', # PSC 0 Capture Enable Input Par
+ 'PFRC0B_PISEL0B': '$40', # PSC 0 Input Select for Part B
+ 'PFRC0B_PELEV0B': '$20', # PSC 0 Edge Level Selector on I
+ 'PFRC0B_PFLTE0B': '$10', # PSC 0 Filter Enable on Input P
+ 'PFRC0B_PRFM0B': '$f', # PSC 0 Retrigger and Fault Mode
+ 'PFRC0A' : '$62', # PSC 0 Input A Control
+ 'PFRC0A_PCAE0A': '$80', # PSC 0 Capture Enable Input Par
+ 'PFRC0A_PISEL0A': '$40', # PSC 0 Input Select for Part A
+ 'PFRC0A_PELEV0A': '$20', # PSC 0 Edge Level Selector on I
+ 'PFRC0A_PFLTE0A': '$10', # PSC 0 Filter Enable on Input P
+ 'PFRC0A_PRFM0A': '$f', # PSC 0 Retrigger and Fault Mode
+ 'PCTL0' : '$32', # PSC 0 Control Register
+ 'PCTL0_PPRE0': '$c0', # PSC 0 Prescaler Selects
+ 'PCTL0_PBFM0': '$24', # PSC 0 Balance Flank Width Modu
+ 'PCTL0_PAOC0B': '$10', # PSC 0 Asynchronous Output Cont
+ 'PCTL0_PAOC0A': '$8', # PSC 0 Asynchronous Output Cont
+ 'PCTL0_PCCYC0': '$2', # PSC0 Complete Cycle
+ 'PCTL0_PRUN0': '$1', # PSC 0 Run
+ 'PCNF0' : '$31', # PSC 0 Configuration Register
+ 'PCNF0_PFIFTY0': '$80', # PSC 0 Fifty
+ 'PCNF0_PALOCK0': '$40', # PSC 0 Autolock
+ 'PCNF0_PLOCK0': '$20', # PSC 0 Lock
+ 'PCNF0_PMODE0': '$18', # PSC 0 Mode
+ 'PCNF0_POP0': '$4', # PSC 0 Output Polarity
+ 'PCNF0_PCLKSEL0': '$2', # PSC 0 Input Clock Select
+ 'OCR0RB' : '$44', # Output Compare RB Register
+ 'OCR0SB' : '$42', # Output Compare SB Register
+ 'OCR0RA' : '$4a', # Output Compare RA Register
+ 'OCR0SA' : '$60', # Output Compare SA Register
+ 'PSOC0' : '$6a', # PSC0 Synchro and Output Config
+ 'PSOC0_PISEL0A1': '$80', # PSC Input Select
+ 'PSOC0_PISEL0B1': '$40', # PSC Input Select
+ 'PSOC0_PSYNC0': '$30', # Synchronisation out for ADC se
+ 'PSOC0_POEN0B': '$4', # PSCOUT01 Output Enable
+ 'PSOC0_POEN0A': '$1', # PSCOUT00 Output Enable
+ 'PIM0' : '$2f', # PSC0 Interrupt Mask Register
+ 'PIM0_PEVE0B': '$10', # External Event B Interrupt Ena
+ 'PIM0_PEVE0A': '$8', # External Event A Interrupt Ena
+ 'PIM0_PEOEPE0': '$2', # End of Enhanced Cycle Enable
+ 'PIM0_PEOPE0': '$1', # End of Cycle Interrupt Enable
+ 'PIFR0' : '$30', # PSC0 Interrupt Flag Register
+ 'PIFR0_POAC0B': '$80', # PSC 0 Output A Activity
+ 'PIFR0_POAC0A': '$40', # PSC 0 Output A Activity
+ 'PIFR0_PEV0B': '$10', # External Event B Interrupt
+ 'PIFR0_PEV0A': '$8', # External Event A Interrupt
+ 'PIFR0_PRN0': '$6', # Ramp Number
+ 'PIFR0_PEOP0': '$1', # End of PSC0 Interrupt
+
+# Module PSC2
+ 'PICR2H' : '$6d', # PSC 2 Input Capture Register H
+ 'PICR2H_PCST2': '$80', # PSC 2 Capture Software Trigger
+ 'PICR2H_PICR21': '$c', #
+ 'PICR2H_PICR2': '$3', #
+ 'PICR2L' : '$6c', # PSC 2 Input Capture Register L
+ 'PFRC2B' : '$67', # PSC 2 Input B Control
+ 'PFRC2B_PCAE2B': '$80', # PSC 2 Capture Enable Input Par
+ 'PFRC2B_PISEL2B': '$40', # PSC 2 Input Select for Part B
+ 'PFRC2B_PELEV2B': '$20', # PSC 2 Edge Level Selector on I
+ 'PFRC2B_PFLTE2B': '$10', # PSC 2 Filter Enable on Input P
+ 'PFRC2B_PRFM2B': '$f', # PSC 2 Retrigger and Fault Mode
+ 'PFRC2A' : '$66', # PSC 2 Input B Control
+ 'PFRC2A_PCAE2A': '$80', # PSC 2 Capture Enable Input Par
+ 'PFRC2A_PISEL2A': '$40', # PSC 2 Input Select for Part A
+ 'PFRC2A_PELEV2A': '$20', # PSC 2 Edge Level Selector on I
+ 'PFRC2A_PFLTE2A': '$10', # PSC 2 Filter Enable on Input P
+ 'PFRC2A_PRFM2A': '$f', # PSC 2 Retrigger and Fault Mode
+ 'PCTL2' : '$36', # PSC 2 Control Register
+ 'PCTL2_PPRE2': '$c0', # PSC 2 Prescaler Selects
+ 'PCTL2_PBFM2': '$20', # Balance Flank Width Modulation
+ 'PCTL2_PAOC2B': '$10', # PSC 2 Asynchronous Output Cont
+ 'PCTL2_PAOC2A': '$8', # PSC 2 Asynchronous Output Cont
+ 'PCTL2_PARUN2': '$4', # PSC2 Auto Run
+ 'PCTL2_PCCYC2': '$2', # PSC2 Complete Cycle
+ 'PCTL2_PRUN2': '$1', # PSC 2 Run
+ 'PCNF2' : '$35', # PSC 2 Configuration Register
+ 'PCNF2_PFIFTY2': '$80', # PSC 2 Fifty
+ 'PCNF2_PALOCK2': '$40', # PSC 2 Autolock
+ 'PCNF2_PLOCK2': '$20', # PSC 2 Lock
+ 'PCNF2_PMODE2': '$18', # PSC 2 Mode
+ 'PCNF2_POP2': '$4', # PSC 2 Output Polarity
+ 'PCNF2_PCLKSEL2': '$2', # PSC 2 Input Clock Select
+ 'PCNF2_POME2': '$1', # PSC 2 Output Matrix Enable
+ 'PCNFE2' : '$70', # PSC 2 Enhanced Configuration R
+ 'PCNFE2_PASDLK2': '$e0', #
+ 'PCNFE2_PBFM21': '$10', #
+ 'PCNFE2_PELEV2A1': '$8', #
+ 'PCNFE2_PELEV2B1': '$4', #
+ 'PCNFE2_PISEL2A1': '$2', #
+ 'PCNFE2_PISEL2B1': '$1', #
+ 'OCR2RB' : '$48', # Output Compare RB Register
+ 'OCR2SB' : '$46', # Output Compare SB Register
+ 'OCR2RA' : '$4e', # Output Compare RA Register
+ 'OCR2SA' : '$64', # Output Compare SA Register
+ 'POM2' : '$6f', # PSC 2 Output Matrix
+ 'POM2_POMV2B': '$f0', # Output Matrix Output B Ramps
+ 'POM2_POMV2A': '$f', # Output Matrix Output A Ramps
+ 'PSOC2' : '$6e', # PSC2 Synchro and Output Config
+ 'PSOC2_POS2': '$c0', # PSC 2 Output 23 Select
+ 'PSOC2_PSYNC2': '$30', # Synchronization Out for ADC Se
+ 'PSOC2_POEN2D': '$8', # PSCOUT23 Output Enable
+ 'PSOC2_POEN2B': '$4', # PSCOUT21 Output Enable
+ 'PSOC2_POEN2C': '$2', # PSCOUT22 Output Enable
+ 'PSOC2_POEN2A': '$1', # PSCOUT20 Output Enable
+ 'PIM2' : '$33', # PSC2 Interrupt Mask Register
+ 'PIM2_PSEIE2': '$20', # PSC 2 Synchro Error Interrupt
+ 'PIM2_PEVE2B': '$10', # External Event B Interrupt Ena
+ 'PIM2_PEVE2A': '$8', # External Event A Interrupt Ena
+ 'PIM2_PEOEPE2': '$2', # End of Enhanced Cycle Interrup
+ 'PIM2_PEOPE2': '$1', # End of Cycle Interrupt Enable
+ 'PIFR2' : '$34', # PSC2 Interrupt Flag Register
+ 'PIFR2_POAC2B': '$80', # PSC 2 Output A Activity
+ 'PIFR2_POAC2A': '$40', # PSC 2 Output A Activity
+ 'PIFR2_PSEI2': '$20', # PSC 2 Synchro Error Interrupt
+ 'PIFR2_PEV2B': '$10', # External Event B Interrupt
+ 'PIFR2_PEV2A': '$8', # External Event A Interrupt
+ 'PIFR2_PRN2': '$6', # Ramp Number
+ 'PIFR2_PEOP2': '$1', # End of PSC2 Interrupt
+ 'PASDLY2' : '$71', # Analog Synchronization Delay R
+
+# Module TIMER_COUNTER_1
+ 'TIMSK1' : '$21', # Timer/Counter Interrupt Mask R
+ 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
+ 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
+ 'TIFR1' : '$22', # Timer/Counter Interrupt Flag r
+ 'TIFR1_ICF1': '$20', # Input Capture Flag 1
+ 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
+ 'TCCR1B' : '$8a', # Timer/Counter1 Control Registe
+ 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
+ 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
+ 'TCCR1B_WGM13': '$10', # Waveform Generation Mode
+ 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
+ 'TCNT1' : '$5a', # Timer/Counter1 Bytes
+ 'ICR1' : '$8c', # Timer/Counter1 Input Capture R
+
+# Module BOOT_LOAD
+ 'SPMCSR' : '$57', # Store Program Memory Control R
+ 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
+ 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
+ 'SPMCSR_SIGRD': '$20', # Signature Row Read
+ 'SPMCSR_RWWSRE': '$10', # Read While Write section read
+ 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
+ 'SPMCSR_PGWRT': '$4', # Page Write
+ 'SPMCSR_PGERS': '$2', # Page Erase
+ 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
+
+ '__amforth_dummy':'0'
+}
diff --git a/amforth-6.5/avr8/devices/at90pwm2/at90pwm2.frt b/amforth-6.5/avr8/devices/at90pwm2/at90pwm2.frt
new file mode 100644
index 0000000..828a39b
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90pwm2/at90pwm2.frt
@@ -0,0 +1,193 @@
+\ Partname: AT90PWM2
+\ Built using part description XML file version 168
+\ generated automatically
+
+hex
+
+\ AD_CONVERTER
+79 constant ADCH \ ADC Data Register High Byte
+78 constant ADCL \ ADC Data Register Low Byte
+7A constant ADCSRA \ The ADC Control and Status register
+7B constant ADCSRB \ ADC Control and Status Register B
+7C constant ADMUX \ The ADC multiplexer Selection Register
+76 constant AMP0CSR \
+77 constant AMP1CSR \
+7E constant DIDR0 \ Digital Input Disable Register 0
+7F constant DIDR1 \ Digital Input Disable Register 0
+
+\ ANALOG_COMPARATOR
+AD constant AC0CON \ Analog Comparator 0 Control Register
+AE constant AC1CON \ Analog Comparator 1 Control Register
+AF constant AC2CON \ Analog Comparator 2 Control Register
+50 constant ACSR \ Analog Comparator Status Register
+
+\ BOOT_LOAD
+57 constant SPMCSR \ Store Program Memory Control Register
+
+\ CPU
+61 constant CLKPR \
+3E constant GPIOR0 \ General Purpose IO Register 0
+39 constant GPIOR1 \ General Purpose IO Register 1
+3A constant GPIOR2 \ General Purpose IO Register 2
+3B constant GPIOR3 \ General Purpose IO Register 3
+55 constant MCUCR \ MCU Control Register
+54 constant MCUSR \ MCU Status Register
+66 constant OSCCAL \ Oscillator Calibration Value
+49 constant PLLCSR \ PLL Control And Status Register
+64 constant PRR \ Power Reduction Register
+53 constant SMCR \ Sleep Mode Control Register
+5E constant SPH \ Stack Pointer High
+5D constant SPL \ Stack Pointer Low
+5F constant SREG \ Status Register
+
+\ DA_CONVERTER
+AC constant DACH \ DAC Data Register High Byte
+AB constant DACL \ DAC Data Register Low Byte
+AA constant DACON \ DAC Control Register
+
+\ EEPROM
+42 constant EEARH \ EEPROM Read/Write Access High Byte
+41 constant EEARL \ EEPROM Read/Write Access Low Byte
+3F constant EECR \ EEPROM Control Register
+40 constant EEDR \ EEPROM Data Register
+
+\ EUSART
+C8 constant EUCSRA \ EUSART Control and Status Register A
+C9 constant EUCSRB \ EUSART Control Register B
+CA constant EUCSRC \ EUSART Status Register C
+CE constant EUDR \ EUSART I/O Data Register
+CD constant MUBRRH \ Manchester Receiver Baud Rate Register High Byte
+CC constant MUBRRL \ Manchester Receiver Baud Rate Register Low Byte
+
+\ EXTERNAL_INTERRUPT
+69 constant EICRA \ External Interrupt Control Register A
+3C constant EIFR \ External Interrupt Flag Register
+3D constant EIMSK \ External Interrupt Mask Register
+
+\ PORTB
+24 constant DDRB \ Port B Data Direction Register
+23 constant PINB \ Port B Input Pins
+25 constant PORTB \ Port B Data Register
+
+\ PORTD
+2A constant DDRD \ Port D Data Direction Register
+29 constant PIND \ Port D Input Pins
+2B constant PORTD \ Port D Data Register
+
+\ PORTE
+2D constant DDRE \ Port E Data Direction Register
+2C constant PINE \ Port E Input Pins
+2E constant PORTE \ Port E Data Register
+
+\ PSC0
+D5 constant OCR0RAH \ Output Compare RA Register High
+D4 constant OCR0RAL \ Output Compare RA Register Low
+D9 constant OCR0RBH \ Output Compare RB Register High
+D8 constant OCR0RBL \ Output Compare RB Register Low
+D3 constant OCR0SAH \ Output Compare SA Register High
+D2 constant OCR0SAL \ Output Compare SA Register Low
+D7 constant OCR0SBH \ Output Compare SB Register High
+D6 constant OCR0SBL \ Output Compare SB Register Low
+DA constant PCNF0 \ PSC 0 Configuration Register
+DB constant PCTL0 \ PSC 0 Control Register
+DC constant PFRC0A \ PSC 0 Input A Control
+DD constant PFRC0B \ PSC 0 Input B Control
+DF constant PICR0H \ PSC 0 Input Capture Register High
+DE constant PICR0L \ PSC 0 Input Capture Register Low
+A0 constant PIFR0 \ PSC0 Interrupt Flag Register
+A1 constant PIM0 \ PSC0 Interrupt Mask Register
+D0 constant PSOC0 \ PSC0 Synchro and Output Configuration
+
+\ PSC2
+F5 constant OCR2RAH \ Output Compare RA Register High
+F4 constant OCR2RAL \ Output Compare RA Register Low
+F9 constant OCR2RBH \ Output Compare RB Register High
+F8 constant OCR2RBL \ Output Compare RB Register Low
+F3 constant OCR2SAH \ Output Compare SA Register High
+F2 constant OCR2SAL \ Output Compare SA Register Low
+F7 constant OCR2SBH \ Output Compare SB Register High
+F6 constant OCR2SBL \ Output Compare SB Register Low
+FA constant PCNF2 \ PSC 2 Configuration Register
+FB constant PCTL2 \ PSC 2 Control Register
+FC constant PFRC2A \ PSC 2 Input B Control
+FD constant PFRC2B \ PSC 2 Input B Control
+FF constant PICR2H \ PSC 2 Input Capture Register High
+FE constant PICR2L \ PSC 2 Input Capture Register Low
+A4 constant PIFR2 \ PSC2 Interrupt Flag Register
+A5 constant PIM2 \ PSC2 Interrupt Mask Register
+F1 constant POM2 \ PSC 2 Output Matrix
+F0 constant PSOC2 \ PSC2 Synchro and Output Configuration
+
+\ SPI
+4C constant SPCR \ SPI Control Register
+4E constant SPDR \ SPI Data Register
+4D constant SPSR \ SPI Status Register
+
+\ TIMER_COUNTER_0
+43 constant GTCCR \ General Timer/Counter Control Register
+47 constant OCR0A \ Timer/Counter0 Output Compare Register
+48 constant OCR0B \ Timer/Counter0 Output Compare Register
+44 constant TCCR0A \ Timer/Counter Control Register A
+45 constant TCCR0B \ Timer/Counter Control Register B
+46 constant TCNT0 \ Timer/Counter0
+35 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
+6E constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
+
+\ TIMER_COUNTER_1
+87 constant ICR1H \ Timer/Counter1 Input Capture Register High Byte
+86 constant ICR1L \ Timer/Counter1 Input Capture Register Low Byte
+89 constant OCR1AH \ Timer/Counter1 Output Compare Register High Byte
+88 constant OCR1AL \ Timer/Counter1 Output Compare Register Low Byte
+8B constant OCR1BH \ Timer/Counter1 Output Compare Register High Byte
+8A constant OCR1BL \ Timer/Counter1 Output Compare Register Low Byte
+80 constant TCCR1A \ Timer/Counter1 Control Register A
+81 constant TCCR1B \ Timer/Counter1 Control Register B
+82 constant TCCR1C \ Timer/Counter1 Control Register C
+85 constant TCNT1H \ Timer/Counter1 High Byte
+84 constant TCNT1L \ Timer/Counter1 Low Byte
+36 constant TIFR1 \ Timer/Counter Interrupt Flag register
+6F constant TIMSK1 \ Timer/Counter Interrupt Mask Register
+
+\ USART
+C5 constant UBRRH \ USART Baud Rate Register High Byte
+C4 constant UBRRL \ USART Baud Rate Register Low Byte
+C0 constant UCSRA \ USART Control and Status register A
+C1 constant UCSRB \ USART Control an Status register B
+C2 constant UCSRC \ USART Control an Status register C
+C6 constant UDR \ USART I/O Data Register
+
+\ WATCHDOG
+60 constant WDTCSR \ Watchdog Timer Control Register
+
+\ Interrupts
+0001 constant PSC2_CAPTAddr \ PSC2 Capture Event
+0002 constant PSC2_ECAddr \ PSC2 End Cycle
+0003 constant PSC1_CAPTAddr \ PSC1 Capture Event
+0004 constant PSC1_ECAddr \ PSC1 End Cycle
+0005 constant PSC0_CAPTAddr \ PSC0 Capture Event
+0006 constant PSC0_ECAddr \ PSC0 End Cycle
+0007 constant ANALOG_COMP_0Addr \ Analog Comparator 0
+0008 constant ANALOG_COMP_1Addr \ Analog Comparator 1
+0009 constant ANALOG_COMP_2Addr \ Analog Comparator 2
+000A constant INT0Addr \ External Interrupt Request 0
+000B constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+000C constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
+000D constant TIMER1_COMPBAddr \ Timer/Counter Compare Match B
+000E constant RESERVED15Addr \
+000F constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+0010 constant TIMER0_COMP_AAddr \ Timer/Counter0 Compare Match A
+0011 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
+0012 constant ADCAddr \ ADC Conversion Complete
+0013 constant INT1Addr \ External Interrupt Request 1
+0014 constant SPI_STCAddr \ SPI Serial Transfer Complete
+0015 constant USART_RXAddr \ USART, Rx Complete
+0016 constant USART_UDREAddr \ USART Data Register Empty
+0017 constant USART_TXAddr \ USART, Tx Complete
+0018 constant INT2Addr \ External Interrupt Request 2
+0019 constant WDTAddr \ Watchdog Timeout Interrupt
+001A constant EE_READYAddr \ EEPROM Ready
+001B constant TIMER0_COMPBAddr \ Timer Counter 0 Compare Match B
+001C constant INT3Addr \ External Interrupt Request 3
+001D constant RESERVED30Addr \
+001E constant RESERVED31Addr \
+001F constant SPM_READYAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/at90pwm2/device.asm b/amforth-6.5/avr8/devices/at90pwm2/device.asm
new file mode 100644
index 0000000..71151f2
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90pwm2/device.asm
@@ -0,0 +1,137 @@
+; Partname: AT90PWM2
+; Built using part description XML file version 168
+; generated automatically, do not edit
+
+.nolist
+ .include "pwm2def.inc"
+.list
+
+.equ ramstart = $0100
+.equ CELLSIZE = 2
+.macro readflashcell
+ lsl zl
+ rol zh
+ lpm @0, Z+
+ lpm @1, Z+
+.endmacro
+.macro writeflashcell
+ lsl zl
+ rol zh
+.endmacro
+
+; the following definitions are shortcuts for the respective forth source segments if set to 1
+.set WANT_AD_CONVERTER = 0
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_BOOT_LOAD = 0
+.set WANT_CPU = 0
+.set WANT_DA_CONVERTER = 0
+.set WANT_EEPROM = 0
+.set WANT_EUSART = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_PORTB = 0
+.set WANT_PORTD = 0
+.set WANT_PORTE = 0
+.set WANT_PSC0 = 0
+.set WANT_PSC2 = 0
+.set WANT_SPI = 0
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_USART = 0
+.set WANT_WATCHDOG = 0
+
+
+.ifndef SPMEN
+ .equ SPMEN = SELFPRGEN
+.endif
+
+.ifndef SPMCSR
+ .equ SPMCSR = SPMCR
+.endif
+
+.ifndef EEPE
+ .equ EEPE = EEWE
+.endif
+
+.ifndef EEMPE
+ .equ EEMPE = EEMWE
+.endif
+.equ intvecsize = 1 ; please verify; flash size: 8192 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.equ INTVECTORS = 32
+.org $0001
+ rcall isr ; PSC2 Capture Event
+.org $0002
+ rcall isr ; PSC2 End Cycle
+.org $0003
+ rcall isr ; PSC1 Capture Event
+.org $0004
+ rcall isr ; PSC1 End Cycle
+.org $0005
+ rcall isr ; PSC0 Capture Event
+.org $0006
+ rcall isr ; PSC0 End Cycle
+.org $0007
+ rcall isr ; Analog Comparator 0
+.org $0008
+ rcall isr ; Analog Comparator 1
+.org $0009
+ rcall isr ; Analog Comparator 2
+.org $000A
+ rcall isr ; External Interrupt Request 0
+.org $000B
+ rcall isr ; Timer/Counter1 Capture Event
+.org $000C
+ rcall isr ; Timer/Counter1 Compare Match A
+.org $000D
+ rcall isr ; Timer/Counter Compare Match B
+.org $000E
+ rcall isr ;
+.org $000F
+ rcall isr ; Timer/Counter1 Overflow
+.org $0010
+ rcall isr ; Timer/Counter0 Compare Match A
+.org $0011
+ rcall isr ; Timer/Counter0 Overflow
+.org $0012
+ rcall isr ; ADC Conversion Complete
+.org $0013
+ rcall isr ; External Interrupt Request 1
+.org $0014
+ rcall isr ; SPI Serial Transfer Complete
+.org $0015
+ rcall isr ; USART, Rx Complete
+.org $0016
+ rcall isr ; USART Data Register Empty
+.org $0017
+ rcall isr ; USART, Tx Complete
+.org $0018
+ rcall isr ; External Interrupt Request 2
+.org $0019
+ rcall isr ; Watchdog Timeout Interrupt
+.org $001A
+ rcall isr ; EEPROM Ready
+.org $001B
+ rcall isr ; Timer Counter 0 Compare Match B
+.org $001C
+ rcall isr ; External Interrupt Request 3
+.org $001D
+ rcall isr ;
+.org $001E
+ rcall isr ;
+.org $001F
+ rcall isr ; Store Program Memory Read
+.nooverlap
+mcu_info:
+mcu_ramsize:
+ .dw 512
+mcu_eepromsize:
+ .dw 512
+mcu_maxdp:
+ .dw 3072 ; minimum of 0xC00 (from XML) and 0xffff
+mcu_numints:
+ .dw 32
+mcu_name:
+ .dw 8
+ .db "AT90PWM2"
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/at90pwm2/device.inc b/amforth-6.5/avr8/devices/at90pwm2/device.inc
new file mode 100644
index 0000000..8dd840b
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90pwm2/device.inc
@@ -0,0 +1,1539 @@
+; Partname: AT90PWM2
+; Built using part description XML file version 168
+; generated automatically, no not edit
+
+; ********
+.if WANT_AD_CONVERTER == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register High Byte
+VE_ADCH:
+ .dw $ff04
+ .db "ADCH"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCH
+XT_ADCH:
+ .dw PFA_DOVARIABLE
+PFA_ADCH:
+ .dw $79
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register Low Byte
+VE_ADCL:
+ .dw $ff04
+ .db "ADCL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCL
+XT_ADCL:
+ .dw PFA_DOVARIABLE
+PFA_ADCL:
+ .dw $78
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register
+VE_ADCSRA:
+ .dw $ff06
+ .db "ADCSRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRA
+XT_ADCSRA:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRA:
+ .dw $7A
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Control and Status Register B
+VE_ADCSRB:
+ .dw $ff06
+ .db "ADCSRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRB
+XT_ADCSRB:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRB:
+ .dw $7B
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC multiplexer Selection Register
+VE_ADMUX:
+ .dw $ff05
+ .db "ADMUX",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADMUX
+XT_ADMUX:
+ .dw PFA_DOVARIABLE
+PFA_ADMUX:
+ .dw $7C
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_AMP0CSR:
+ .dw $ff07
+ .db "AMP0CSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_AMP0CSR
+XT_AMP0CSR:
+ .dw PFA_DOVARIABLE
+PFA_AMP0CSR:
+ .dw $76
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_AMP1CSR:
+ .dw $ff07
+ .db "AMP1CSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_AMP1CSR
+XT_AMP1CSR:
+ .dw PFA_DOVARIABLE
+PFA_AMP1CSR:
+ .dw $77
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 0
+VE_DIDR0:
+ .dw $ff05
+ .db "DIDR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR0
+XT_DIDR0:
+ .dw PFA_DOVARIABLE
+PFA_DIDR0:
+ .dw $7E
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 0
+VE_DIDR1:
+ .dw $ff05
+ .db "DIDR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR1
+XT_DIDR1:
+ .dw PFA_DOVARIABLE
+PFA_DIDR1:
+ .dw $7F
+
+.endif
+
+; ********
+.if WANT_ANALOG_COMPARATOR == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator 0 Control Register
+VE_AC0CON:
+ .dw $ff06
+ .db "AC0CON"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_AC0CON
+XT_AC0CON:
+ .dw PFA_DOVARIABLE
+PFA_AC0CON:
+ .dw $AD
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator 1 Control Register
+VE_AC1CON:
+ .dw $ff06
+ .db "AC1CON"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_AC1CON
+XT_AC1CON:
+ .dw PFA_DOVARIABLE
+PFA_AC1CON:
+ .dw $AE
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator 2 Control Register
+VE_AC2CON:
+ .dw $ff06
+ .db "AC2CON"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_AC2CON
+XT_AC2CON:
+ .dw PFA_DOVARIABLE
+PFA_AC2CON:
+ .dw $AF
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw $50
+
+.endif
+
+; ********
+.if WANT_BOOT_LOAD == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control Register
+VE_SPMCSR:
+ .dw $ff06
+ .db "SPMCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCSR
+XT_SPMCSR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCSR:
+ .dw $57
+
+.endif
+
+; ********
+.if WANT_CPU == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_CLKPR:
+ .dw $ff05
+ .db "CLKPR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKPR
+XT_CLKPR:
+ .dw PFA_DOVARIABLE
+PFA_CLKPR:
+ .dw $61
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 0
+VE_GPIOR0:
+ .dw $ff06
+ .db "GPIOR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR0
+XT_GPIOR0:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR0:
+ .dw $3E
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 1
+VE_GPIOR1:
+ .dw $ff06
+ .db "GPIOR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR1
+XT_GPIOR1:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR1:
+ .dw $39
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 2
+VE_GPIOR2:
+ .dw $ff06
+ .db "GPIOR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR2
+XT_GPIOR2:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR2:
+ .dw $3A
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 3
+VE_GPIOR3:
+ .dw $ff06
+ .db "GPIOR3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR3
+XT_GPIOR3:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR3:
+ .dw $3B
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw $55
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Status Register
+VE_MCUSR:
+ .dw $ff05
+ .db "MCUSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUSR
+XT_MCUSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUSR:
+ .dw $54
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Calibration Value
+VE_OSCCAL:
+ .dw $ff06
+ .db "OSCCAL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSCCAL
+XT_OSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_OSCCAL:
+ .dw $66
+; ( -- addr ) System Constant
+; R( -- )
+; PLL Control And Status Register
+VE_PLLCSR:
+ .dw $ff06
+ .db "PLLCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PLLCSR
+XT_PLLCSR:
+ .dw PFA_DOVARIABLE
+PFA_PLLCSR:
+ .dw $49
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register
+VE_PRR:
+ .dw $ff03
+ .db "PRR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR
+XT_PRR:
+ .dw PFA_DOVARIABLE
+PFA_PRR:
+ .dw $64
+; ( -- addr ) System Constant
+; R( -- )
+; Sleep Mode Control Register
+VE_SMCR:
+ .dw $ff04
+ .db "SMCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SMCR
+XT_SMCR:
+ .dw PFA_DOVARIABLE
+PFA_SMCR:
+ .dw $53
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer High
+VE_SPH:
+ .dw $ff03
+ .db "SPH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPH
+XT_SPH:
+ .dw PFA_DOVARIABLE
+PFA_SPH:
+ .dw $5E
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer Low
+VE_SPL:
+ .dw $ff03
+ .db "SPL",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPL
+XT_SPL:
+ .dw PFA_DOVARIABLE
+PFA_SPL:
+ .dw $5D
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw $5F
+
+.endif
+
+; ********
+.if WANT_DA_CONVERTER == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; DAC Data Register High Byte
+VE_DACH:
+ .dw $ff04
+ .db "DACH"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DACH
+XT_DACH:
+ .dw PFA_DOVARIABLE
+PFA_DACH:
+ .dw $AC
+; ( -- addr ) System Constant
+; R( -- )
+; DAC Data Register Low Byte
+VE_DACL:
+ .dw $ff04
+ .db "DACL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DACL
+XT_DACL:
+ .dw PFA_DOVARIABLE
+PFA_DACL:
+ .dw $AB
+; ( -- addr ) System Constant
+; R( -- )
+; DAC Control Register
+VE_DACON:
+ .dw $ff05
+ .db "DACON",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DACON
+XT_DACON:
+ .dw PFA_DOVARIABLE
+PFA_DACON:
+ .dw $AA
+
+.endif
+
+; ********
+.if WANT_EEPROM == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Read/Write Access High Byte
+VE_EEARH:
+ .dw $ff05
+ .db "EEARH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEARH
+XT_EEARH:
+ .dw PFA_DOVARIABLE
+PFA_EEARH:
+ .dw $42
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Read/Write Access Low Byte
+VE_EEARL:
+ .dw $ff05
+ .db "EEARL",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEARL
+XT_EEARL:
+ .dw PFA_DOVARIABLE
+PFA_EEARL:
+ .dw $41
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw $3F
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw $40
+
+.endif
+
+; ********
+.if WANT_EUSART == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; EUSART Control and Status Register A
+VE_EUCSRA:
+ .dw $ff06
+ .db "EUCSRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EUCSRA
+XT_EUCSRA:
+ .dw PFA_DOVARIABLE
+PFA_EUCSRA:
+ .dw $C8
+; ( -- addr ) System Constant
+; R( -- )
+; EUSART Control Register B
+VE_EUCSRB:
+ .dw $ff06
+ .db "EUCSRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EUCSRB
+XT_EUCSRB:
+ .dw PFA_DOVARIABLE
+PFA_EUCSRB:
+ .dw $C9
+; ( -- addr ) System Constant
+; R( -- )
+; EUSART Status Register C
+VE_EUCSRC:
+ .dw $ff06
+ .db "EUCSRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EUCSRC
+XT_EUCSRC:
+ .dw PFA_DOVARIABLE
+PFA_EUCSRC:
+ .dw $CA
+; ( -- addr ) System Constant
+; R( -- )
+; EUSART I/O Data Register
+VE_EUDR:
+ .dw $ff04
+ .db "EUDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EUDR
+XT_EUDR:
+ .dw PFA_DOVARIABLE
+PFA_EUDR:
+ .dw $CE
+; ( -- addr ) System Constant
+; R( -- )
+; Manchester Receiver Baud Rate Register High Byte
+VE_MUBRRH:
+ .dw $ff06
+ .db "MUBRRH"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MUBRRH
+XT_MUBRRH:
+ .dw PFA_DOVARIABLE
+PFA_MUBRRH:
+ .dw $CD
+; ( -- addr ) System Constant
+; R( -- )
+; Manchester Receiver Baud Rate Register Low Byte
+VE_MUBRRL:
+ .dw $ff06
+ .db "MUBRRL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MUBRRL
+XT_MUBRRL:
+ .dw PFA_DOVARIABLE
+PFA_MUBRRL:
+ .dw $CC
+
+.endif
+
+; ********
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register A
+VE_EICRA:
+ .dw $ff05
+ .db "EICRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRA
+XT_EICRA:
+ .dw PFA_DOVARIABLE
+PFA_EICRA:
+ .dw $69
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Flag Register
+VE_EIFR:
+ .dw $ff04
+ .db "EIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIFR
+XT_EIFR:
+ .dw PFA_DOVARIABLE
+PFA_EIFR:
+ .dw $3C
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Mask Register
+VE_EIMSK:
+ .dw $ff05
+ .db "EIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIMSK
+XT_EIMSK:
+ .dw PFA_DOVARIABLE
+PFA_EIMSK:
+ .dw $3D
+
+.endif
+
+; ********
+.if WANT_PORTB == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw $24
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw $23
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw $25
+
+.endif
+
+; ********
+.if WANT_PORTD == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw $2A
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw $29
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw $2B
+
+.endif
+
+; ********
+.if WANT_PORTE == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Port E Data Direction Register
+VE_DDRE:
+ .dw $ff04
+ .db "DDRE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRE
+XT_DDRE:
+ .dw PFA_DOVARIABLE
+PFA_DDRE:
+ .dw $2D
+; ( -- addr ) System Constant
+; R( -- )
+; Port E Input Pins
+VE_PINE:
+ .dw $ff04
+ .db "PINE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINE
+XT_PINE:
+ .dw PFA_DOVARIABLE
+PFA_PINE:
+ .dw $2C
+; ( -- addr ) System Constant
+; R( -- )
+; Port E Data Register
+VE_PORTE:
+ .dw $ff05
+ .db "PORTE",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTE
+XT_PORTE:
+ .dw PFA_DOVARIABLE
+PFA_PORTE:
+ .dw $2E
+
+.endif
+
+; ********
+.if WANT_PSC0 == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare RA Register High
+VE_OCR0RAH:
+ .dw $ff07
+ .db "OCR0RAH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0RAH
+XT_OCR0RAH:
+ .dw PFA_DOVARIABLE
+PFA_OCR0RAH:
+ .dw $D5
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare RA Register Low
+VE_OCR0RAL:
+ .dw $ff07
+ .db "OCR0RAL",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0RAL
+XT_OCR0RAL:
+ .dw PFA_DOVARIABLE
+PFA_OCR0RAL:
+ .dw $D4
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare RB Register High
+VE_OCR0RBH:
+ .dw $ff07
+ .db "OCR0RBH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0RBH
+XT_OCR0RBH:
+ .dw PFA_DOVARIABLE
+PFA_OCR0RBH:
+ .dw $D9
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare RB Register Low
+VE_OCR0RBL:
+ .dw $ff07
+ .db "OCR0RBL",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0RBL
+XT_OCR0RBL:
+ .dw PFA_DOVARIABLE
+PFA_OCR0RBL:
+ .dw $D8
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare SA Register High
+VE_OCR0SAH:
+ .dw $ff07
+ .db "OCR0SAH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0SAH
+XT_OCR0SAH:
+ .dw PFA_DOVARIABLE
+PFA_OCR0SAH:
+ .dw $D3
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare SA Register Low
+VE_OCR0SAL:
+ .dw $ff07
+ .db "OCR0SAL",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0SAL
+XT_OCR0SAL:
+ .dw PFA_DOVARIABLE
+PFA_OCR0SAL:
+ .dw $D2
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare SB Register High
+VE_OCR0SBH:
+ .dw $ff07
+ .db "OCR0SBH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0SBH
+XT_OCR0SBH:
+ .dw PFA_DOVARIABLE
+PFA_OCR0SBH:
+ .dw $D7
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare SB Register Low
+VE_OCR0SBL:
+ .dw $ff07
+ .db "OCR0SBL",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0SBL
+XT_OCR0SBL:
+ .dw PFA_DOVARIABLE
+PFA_OCR0SBL:
+ .dw $D6
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 0 Configuration Register
+VE_PCNF0:
+ .dw $ff05
+ .db "PCNF0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCNF0
+XT_PCNF0:
+ .dw PFA_DOVARIABLE
+PFA_PCNF0:
+ .dw $DA
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 0 Control Register
+VE_PCTL0:
+ .dw $ff05
+ .db "PCTL0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCTL0
+XT_PCTL0:
+ .dw PFA_DOVARIABLE
+PFA_PCTL0:
+ .dw $DB
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 0 Input A Control
+VE_PFRC0A:
+ .dw $ff06
+ .db "PFRC0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PFRC0A
+XT_PFRC0A:
+ .dw PFA_DOVARIABLE
+PFA_PFRC0A:
+ .dw $DC
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 0 Input B Control
+VE_PFRC0B:
+ .dw $ff06
+ .db "PFRC0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PFRC0B
+XT_PFRC0B:
+ .dw PFA_DOVARIABLE
+PFA_PFRC0B:
+ .dw $DD
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 0 Input Capture Register High
+VE_PICR0H:
+ .dw $ff06
+ .db "PICR0H"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PICR0H
+XT_PICR0H:
+ .dw PFA_DOVARIABLE
+PFA_PICR0H:
+ .dw $DF
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 0 Input Capture Register Low
+VE_PICR0L:
+ .dw $ff06
+ .db "PICR0L"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PICR0L
+XT_PICR0L:
+ .dw PFA_DOVARIABLE
+PFA_PICR0L:
+ .dw $DE
+; ( -- addr ) System Constant
+; R( -- )
+; PSC0 Interrupt Flag Register
+VE_PIFR0:
+ .dw $ff05
+ .db "PIFR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIFR0
+XT_PIFR0:
+ .dw PFA_DOVARIABLE
+PFA_PIFR0:
+ .dw $A0
+; ( -- addr ) System Constant
+; R( -- )
+; PSC0 Interrupt Mask Register
+VE_PIM0:
+ .dw $ff04
+ .db "PIM0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIM0
+XT_PIM0:
+ .dw PFA_DOVARIABLE
+PFA_PIM0:
+ .dw $A1
+; ( -- addr ) System Constant
+; R( -- )
+; PSC0 Synchro and Output Configuration
+VE_PSOC0:
+ .dw $ff05
+ .db "PSOC0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PSOC0
+XT_PSOC0:
+ .dw PFA_DOVARIABLE
+PFA_PSOC0:
+ .dw $D0
+
+.endif
+
+; ********
+.if WANT_PSC2 == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare RA Register High
+VE_OCR2RAH:
+ .dw $ff07
+ .db "OCR2RAH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2RAH
+XT_OCR2RAH:
+ .dw PFA_DOVARIABLE
+PFA_OCR2RAH:
+ .dw $F5
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare RA Register Low
+VE_OCR2RAL:
+ .dw $ff07
+ .db "OCR2RAL",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2RAL
+XT_OCR2RAL:
+ .dw PFA_DOVARIABLE
+PFA_OCR2RAL:
+ .dw $F4
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare RB Register High
+VE_OCR2RBH:
+ .dw $ff07
+ .db "OCR2RBH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2RBH
+XT_OCR2RBH:
+ .dw PFA_DOVARIABLE
+PFA_OCR2RBH:
+ .dw $F9
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare RB Register Low
+VE_OCR2RBL:
+ .dw $ff07
+ .db "OCR2RBL",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2RBL
+XT_OCR2RBL:
+ .dw PFA_DOVARIABLE
+PFA_OCR2RBL:
+ .dw $F8
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare SA Register High
+VE_OCR2SAH:
+ .dw $ff07
+ .db "OCR2SAH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2SAH
+XT_OCR2SAH:
+ .dw PFA_DOVARIABLE
+PFA_OCR2SAH:
+ .dw $F3
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare SA Register Low
+VE_OCR2SAL:
+ .dw $ff07
+ .db "OCR2SAL",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2SAL
+XT_OCR2SAL:
+ .dw PFA_DOVARIABLE
+PFA_OCR2SAL:
+ .dw $F2
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare SB Register High
+VE_OCR2SBH:
+ .dw $ff07
+ .db "OCR2SBH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2SBH
+XT_OCR2SBH:
+ .dw PFA_DOVARIABLE
+PFA_OCR2SBH:
+ .dw $F7
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare SB Register Low
+VE_OCR2SBL:
+ .dw $ff07
+ .db "OCR2SBL",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2SBL
+XT_OCR2SBL:
+ .dw PFA_DOVARIABLE
+PFA_OCR2SBL:
+ .dw $F6
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 2 Configuration Register
+VE_PCNF2:
+ .dw $ff05
+ .db "PCNF2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCNF2
+XT_PCNF2:
+ .dw PFA_DOVARIABLE
+PFA_PCNF2:
+ .dw $FA
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 2 Control Register
+VE_PCTL2:
+ .dw $ff05
+ .db "PCTL2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCTL2
+XT_PCTL2:
+ .dw PFA_DOVARIABLE
+PFA_PCTL2:
+ .dw $FB
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 2 Input B Control
+VE_PFRC2A:
+ .dw $ff06
+ .db "PFRC2A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PFRC2A
+XT_PFRC2A:
+ .dw PFA_DOVARIABLE
+PFA_PFRC2A:
+ .dw $FC
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 2 Input B Control
+VE_PFRC2B:
+ .dw $ff06
+ .db "PFRC2B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PFRC2B
+XT_PFRC2B:
+ .dw PFA_DOVARIABLE
+PFA_PFRC2B:
+ .dw $FD
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 2 Input Capture Register High
+VE_PICR2H:
+ .dw $ff06
+ .db "PICR2H"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PICR2H
+XT_PICR2H:
+ .dw PFA_DOVARIABLE
+PFA_PICR2H:
+ .dw $FF
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 2 Input Capture Register Low
+VE_PICR2L:
+ .dw $ff06
+ .db "PICR2L"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PICR2L
+XT_PICR2L:
+ .dw PFA_DOVARIABLE
+PFA_PICR2L:
+ .dw $FE
+; ( -- addr ) System Constant
+; R( -- )
+; PSC2 Interrupt Flag Register
+VE_PIFR2:
+ .dw $ff05
+ .db "PIFR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIFR2
+XT_PIFR2:
+ .dw PFA_DOVARIABLE
+PFA_PIFR2:
+ .dw $A4
+; ( -- addr ) System Constant
+; R( -- )
+; PSC2 Interrupt Mask Register
+VE_PIM2:
+ .dw $ff04
+ .db "PIM2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIM2
+XT_PIM2:
+ .dw PFA_DOVARIABLE
+PFA_PIM2:
+ .dw $A5
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 2 Output Matrix
+VE_POM2:
+ .dw $ff04
+ .db "POM2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_POM2
+XT_POM2:
+ .dw PFA_DOVARIABLE
+PFA_POM2:
+ .dw $F1
+; ( -- addr ) System Constant
+; R( -- )
+; PSC2 Synchro and Output Configuration
+VE_PSOC2:
+ .dw $ff05
+ .db "PSOC2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PSOC2
+XT_PSOC2:
+ .dw PFA_DOVARIABLE
+PFA_PSOC2:
+ .dw $F0
+
+.endif
+
+; ********
+.if WANT_SPI == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR:
+ .dw $ff04
+ .db "SPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR
+XT_SPCR:
+ .dw PFA_DOVARIABLE
+PFA_SPCR:
+ .dw $4C
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR:
+ .dw $ff04
+ .db "SPDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR
+XT_SPDR:
+ .dw PFA_DOVARIABLE
+PFA_SPDR:
+ .dw $4E
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR:
+ .dw $ff04
+ .db "SPSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR
+XT_SPSR:
+ .dw PFA_DOVARIABLE
+PFA_SPSR:
+ .dw $4D
+
+.endif
+
+; ********
+.if WANT_TIMER_COUNTER_0 == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; General Timer/Counter Control Register
+VE_GTCCR:
+ .dw $ff05
+ .db "GTCCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GTCCR
+XT_GTCCR:
+ .dw PFA_DOVARIABLE
+PFA_GTCCR:
+ .dw $43
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0A:
+ .dw $ff05
+ .db "OCR0A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0A
+XT_OCR0A:
+ .dw PFA_DOVARIABLE
+PFA_OCR0A:
+ .dw $47
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0B:
+ .dw $ff05
+ .db "OCR0B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0B
+XT_OCR0B:
+ .dw PFA_DOVARIABLE
+PFA_OCR0B:
+ .dw $48
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register A
+VE_TCCR0A:
+ .dw $ff06
+ .db "TCCR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0A
+XT_TCCR0A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0A:
+ .dw $44
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register B
+VE_TCCR0B:
+ .dw $ff06
+ .db "TCCR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0B
+XT_TCCR0B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0B:
+ .dw $45
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw $46
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Flag register
+VE_TIFR0:
+ .dw $ff05
+ .db "TIFR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR0
+XT_TIFR0:
+ .dw PFA_DOVARIABLE
+PFA_TIFR0:
+ .dw $35
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Mask Register
+VE_TIMSK0:
+ .dw $ff06
+ .db "TIMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK0
+XT_TIMSK0:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK0:
+ .dw $6E
+
+.endif
+
+; ********
+.if WANT_TIMER_COUNTER_1 == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register High Byte
+VE_ICR1H:
+ .dw $ff05
+ .db "ICR1H",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1H
+XT_ICR1H:
+ .dw PFA_DOVARIABLE
+PFA_ICR1H:
+ .dw $87
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Low Byte
+VE_ICR1L:
+ .dw $ff05
+ .db "ICR1L",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1L
+XT_ICR1L:
+ .dw PFA_DOVARIABLE
+PFA_ICR1L:
+ .dw $86
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register High Byte
+VE_OCR1AH:
+ .dw $ff06
+ .db "OCR1AH"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1AH
+XT_OCR1AH:
+ .dw PFA_DOVARIABLE
+PFA_OCR1AH:
+ .dw $89
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register Low Byte
+VE_OCR1AL:
+ .dw $ff06
+ .db "OCR1AL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1AL
+XT_OCR1AL:
+ .dw PFA_DOVARIABLE
+PFA_OCR1AL:
+ .dw $88
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register High Byte
+VE_OCR1BH:
+ .dw $ff06
+ .db "OCR1BH"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1BH
+XT_OCR1BH:
+ .dw PFA_DOVARIABLE
+PFA_OCR1BH:
+ .dw $8B
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register Low Byte
+VE_OCR1BL:
+ .dw $ff06
+ .db "OCR1BL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1BL
+XT_OCR1BL:
+ .dw PFA_DOVARIABLE
+PFA_OCR1BL:
+ .dw $8A
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw $80
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw $81
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register C
+VE_TCCR1C:
+ .dw $ff06
+ .db "TCCR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1C
+XT_TCCR1C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1C:
+ .dw $82
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 High Byte
+VE_TCNT1H:
+ .dw $ff06
+ .db "TCNT1H"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1H
+XT_TCNT1H:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1H:
+ .dw $85
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Low Byte
+VE_TCNT1L:
+ .dw $ff06
+ .db "TCNT1L"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1L
+XT_TCNT1L:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1L:
+ .dw $84
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Flag register
+VE_TIFR1:
+ .dw $ff05
+ .db "TIFR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR1
+XT_TIFR1:
+ .dw PFA_DOVARIABLE
+PFA_TIFR1:
+ .dw $36
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Mask Register
+VE_TIMSK1:
+ .dw $ff06
+ .db "TIMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK1
+XT_TIMSK1:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK1:
+ .dw $6F
+
+.endif
+
+; ********
+.if WANT_USART == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register High Byte
+VE_UBRRH:
+ .dw $ff05
+ .db "UBRRH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRRH
+XT_UBRRH:
+ .dw PFA_DOVARIABLE
+PFA_UBRRH:
+ .dw $C5
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Low Byte
+VE_UBRRL:
+ .dw $ff05
+ .db "UBRRL",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRRL
+XT_UBRRL:
+ .dw PFA_DOVARIABLE
+PFA_UBRRL:
+ .dw $C4
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status register A
+VE_UCSRA:
+ .dw $ff05
+ .db "UCSRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSRA
+XT_UCSRA:
+ .dw PFA_DOVARIABLE
+PFA_UCSRA:
+ .dw $C0
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control an Status register B
+VE_UCSRB:
+ .dw $ff05
+ .db "UCSRB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSRB
+XT_UCSRB:
+ .dw PFA_DOVARIABLE
+PFA_UCSRB:
+ .dw $C1
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control an Status register C
+VE_UCSRC:
+ .dw $ff05
+ .db "UCSRC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSRC
+XT_UCSRC:
+ .dw PFA_DOVARIABLE
+PFA_UCSRC:
+ .dw $C2
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR:
+ .dw $ff03
+ .db "UDR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR
+XT_UDR:
+ .dw PFA_DOVARIABLE
+PFA_UDR:
+ .dw $C6
+
+.endif
+
+; ********
+.if WANT_WATCHDOG == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCSR:
+ .dw $ff06
+ .db "WDTCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCSR
+XT_WDTCSR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCSR:
+ .dw $60
+
+.endif
diff --git a/amforth-6.5/avr8/devices/at90pwm2/device.py b/amforth-6.5/avr8/devices/at90pwm2/device.py
new file mode 100644
index 0000000..48237b1
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90pwm2/device.py
@@ -0,0 +1,155 @@
+# Partname: AT90PWM2
+# Built using part description XML file version 168
+# generated automatically, do not edit
+MCUREGS = {
+ 'ADCH': '$79',
+ 'ADCL': '$78',
+ 'ADCSRA': '$7A',
+ 'ADCSRB': '$7B',
+ 'ADMUX': '$7C',
+ 'AMP0CSR': '$76',
+ 'AMP1CSR': '$77',
+ 'DIDR0': '$7E',
+ 'DIDR1': '$7F',
+ 'AC0CON': '$AD',
+ 'AC1CON': '$AE',
+ 'AC2CON': '$AF',
+ 'ACSR': '$50',
+ 'SPMCSR': '$57',
+ 'CLKPR': '$61',
+ 'GPIOR0': '$3E',
+ 'GPIOR1': '$39',
+ 'GPIOR2': '$3A',
+ 'GPIOR3': '$3B',
+ 'MCUCR': '$55',
+ 'MCUSR': '$54',
+ 'OSCCAL': '$66',
+ 'PLLCSR': '$49',
+ 'PRR': '$64',
+ 'SMCR': '$53',
+ 'SPH': '$5E',
+ 'SPL': '$5D',
+ 'SREG': '$5F',
+ 'DACH': '$AC',
+ 'DACL': '$AB',
+ 'DACON': '$AA',
+ 'EEARH': '$42',
+ 'EEARL': '$41',
+ 'EECR': '$3F',
+ 'EEDR': '$40',
+ 'EUCSRA': '$C8',
+ 'EUCSRB': '$C9',
+ 'EUCSRC': '$CA',
+ 'EUDR': '$CE',
+ 'MUBRRH': '$CD',
+ 'MUBRRL': '$CC',
+ 'EICRA': '$69',
+ 'EIFR': '$3C',
+ 'EIMSK': '$3D',
+ 'DDRB': '$24',
+ 'PINB': '$23',
+ 'PORTB': '$25',
+ 'DDRD': '$2A',
+ 'PIND': '$29',
+ 'PORTD': '$2B',
+ 'DDRE': '$2D',
+ 'PINE': '$2C',
+ 'PORTE': '$2E',
+ 'OCR0RAH': '$D5',
+ 'OCR0RAL': '$D4',
+ 'OCR0RBH': '$D9',
+ 'OCR0RBL': '$D8',
+ 'OCR0SAH': '$D3',
+ 'OCR0SAL': '$D2',
+ 'OCR0SBH': '$D7',
+ 'OCR0SBL': '$D6',
+ 'PCNF0': '$DA',
+ 'PCTL0': '$DB',
+ 'PFRC0A': '$DC',
+ 'PFRC0B': '$DD',
+ 'PICR0H': '$DF',
+ 'PICR0L': '$DE',
+ 'PIFR0': '$A0',
+ 'PIM0': '$A1',
+ 'PSOC0': '$D0',
+ 'OCR2RAH': '$F5',
+ 'OCR2RAL': '$F4',
+ 'OCR2RBH': '$F9',
+ 'OCR2RBL': '$F8',
+ 'OCR2SAH': '$F3',
+ 'OCR2SAL': '$F2',
+ 'OCR2SBH': '$F7',
+ 'OCR2SBL': '$F6',
+ 'PCNF2': '$FA',
+ 'PCTL2': '$FB',
+ 'PFRC2A': '$FC',
+ 'PFRC2B': '$FD',
+ 'PICR2H': '$FF',
+ 'PICR2L': '$FE',
+ 'PIFR2': '$A4',
+ 'PIM2': '$A5',
+ 'POM2': '$F1',
+ 'PSOC2': '$F0',
+ 'SPCR': '$4C',
+ 'SPDR': '$4E',
+ 'SPSR': '$4D',
+ 'GTCCR': '$43',
+ 'OCR0A': '$47',
+ 'OCR0B': '$48',
+ 'TCCR0A': '$44',
+ 'TCCR0B': '$45',
+ 'TCNT0': '$46',
+ 'TIFR0': '$35',
+ 'TIMSK0': '$6E',
+ 'ICR1H': '$87',
+ 'ICR1L': '$86',
+ 'OCR1AH': '$89',
+ 'OCR1AL': '$88',
+ 'OCR1BH': '$8B',
+ 'OCR1BL': '$8A',
+ 'TCCR1A': '$80',
+ 'TCCR1B': '$81',
+ 'TCCR1C': '$82',
+ 'TCNT1H': '$85',
+ 'TCNT1L': '$84',
+ 'TIFR1': '$36',
+ 'TIMSK1': '$6F',
+ 'UBRRH': '$C5',
+ 'UBRRL': '$C4',
+ 'UCSRA': '$C0',
+ 'UCSRB': '$C1',
+ 'UCSRC': '$C2',
+ 'UDR': '$C6',
+ 'WDTCSR': '$60',
+ 'PSC2_CAPTAddr': '$0001',
+ 'PSC2_ECAddr': '$0002',
+ 'PSC1_CAPTAddr': '$0003',
+ 'PSC1_ECAddr': '$0004',
+ 'PSC0_CAPTAddr': '$0005',
+ 'PSC0_ECAddr': '$0006',
+ 'ANALOG_COMP_0Addr': '$0007',
+ 'ANALOG_COMP_1Addr': '$0008',
+ 'ANALOG_COMP_2Addr': '$0009',
+ 'INT0Addr': '$000A',
+ 'TIMER1_CAPTAddr': '$000B',
+ 'TIMER1_COMPAAddr': '$000C',
+ 'TIMER1_COMPBAddr': '$000D',
+ 'RESERVED15Addr': '$000E',
+ 'TIMER1_OVFAddr': '$000F',
+ 'TIMER0_COMP_AAddr': '$0010',
+ 'TIMER0_OVFAddr': '$0011',
+ 'ADCAddr': '$0012',
+ 'INT1Addr': '$0013',
+ 'SPI_STCAddr': '$0014',
+ 'USART_RXAddr': '$0015',
+ 'USART_UDREAddr': '$0016',
+ 'USART_TXAddr': '$0017',
+ 'INT2Addr': '$0018',
+ 'WDTAddr': '$0019',
+ 'EE_READYAddr': '$001A',
+ 'TIMER0_COMPBAddr': '$001B',
+ 'INT3Addr': '$001C',
+ 'RESERVED30Addr': '$001D',
+ 'RESERVED31Addr': '$001E',
+ 'SPM_READYAddr': '$001F'
+} \ No newline at end of file
diff --git a/amforth-6.5/avr8/devices/at90pwm216/at90pwm216.frt b/amforth-6.5/avr8/devices/at90pwm216/at90pwm216.frt
new file mode 100644
index 0000000..cc489bc
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90pwm216/at90pwm216.frt
@@ -0,0 +1,423 @@
+\ Partname: AT90PWM216
+\ generated automatically
+
+\ PORTB
+&37 constant PORTB \ Port B Data Register
+&36 constant DDRB \ Port B Data Direction Register
+&35 constant PINB \ Port B Input Pins
+\ PORTD
+&43 constant PORTD \ Port D Data Register
+&42 constant DDRD \ Port D Data Direction Register
+&41 constant PIND \ Port D Input Pins
+\ BOOT_LOAD
+&87 constant SPMCSR \ Store Program Memory Control Register
+ $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
+ $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
+ $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
+ $04 constant SPMCSR_PGWRT \ Page Write
+ $02 constant SPMCSR_PGERS \ Page Erase
+ $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
+\ EUSART
+&206 constant EUDR \ EUSART I/O Data Register
+&200 constant EUCSRA \ EUSART Control and Status Register A
+ $F0 constant EUCSRA_UTxS \ EUSART Control and Status Register A Bits
+ $0F constant EUCSRA_URxS \ EUSART Control and Status Register A Bits
+&201 constant EUCSRB \ EUSART Control Register B
+ $10 constant EUCSRB_EUSART \ EUSART Enable Bit
+ $08 constant EUCSRB_EUSBS \ EUSBS Enable Bit
+ $02 constant EUCSRB_EMCH \ Manchester Mode Bit
+ $01 constant EUCSRB_BODR \ Order Bit
+&202 constant EUCSRC \ EUSART Status Register C
+ $08 constant EUCSRC_FEM \ Frame Error Manchester Bit
+ $04 constant EUCSRC_F1617 \ F1617 Bit
+ $03 constant EUCSRC_STP \ Stop Bits
+&205 constant MUBRRH \ Manchester Receiver Baud Rate Register High Byte
+ $FF constant MUBRRH_MUBRR \ Manchester Receiver Baud Rate Register Bits
+&204 constant MUBRRL \ Manchester Receiver Baud Rate Register Low Byte
+ $FF constant MUBRRL_MUBRR \ Manchester Receiver Baud Rate Register Bits
+\ ANALOG_COMPARATOR
+&173 constant AC0CON \ Analog Comparator 0 Control Register
+ $80 constant AC0CON_AC0EN \ Analog Comparator 0 Enable Bit
+ $40 constant AC0CON_AC0IE \ Analog Comparator 0 Interrupt Enable Bit
+ $30 constant AC0CON_AC0IS \ Analog Comparator 0 Interrupt Select Bit
+ $07 constant AC0CON_AC0M \ Analog Comparator 0 Multiplexer Register
+&174 constant AC1CON \ Analog Comparator 1 Control Register
+ $80 constant AC1CON_AC1EN \ Analog Comparator 1 Enable Bit
+ $40 constant AC1CON_AC1IE \ Analog Comparator 1 Interrupt Enable Bit
+ $30 constant AC1CON_AC1IS \ Analog Comparator 1 Interrupt Select Bit
+ $08 constant AC1CON_AC1ICE \ Analog Comparator 1 Interrupt Capture Enable Bit
+ $07 constant AC1CON_AC1M \ Analog Comparator 1 Multiplexer Register
+&175 constant AC2CON \ Analog Comparator 2 Control Register
+ $80 constant AC2CON_AC2EN \ Analog Comparator 2 Enable Bit
+ $40 constant AC2CON_AC2IE \ Analog Comparator 2 Interrupt Enable Bit
+ $30 constant AC2CON_AC2IS \ Analog Comparator 2 Interrupt Select Bit
+ $07 constant AC2CON_AC2M \ Analog Comparator 2 Multiplexer Register
+&80 constant ACSR \ Analog Comparator Status Register
+ $80 constant ACSR_ACCKDIV \ Analog Comparator Clock Divider
+ $40 constant ACSR_AC2IF \ Analog Comparator 2 Interrupt Flag Bit
+ $20 constant ACSR_AC1IF \ Analog Comparator 1 Interrupt Flag Bit
+ $10 constant ACSR_AC0IF \ Analog Comparator 0 Interrupt Flag Bit
+ $04 constant ACSR_AC2O \ Analog Comparator 2 Output Bit
+ $02 constant ACSR_AC1O \ Analog Comparator 1 Output Bit
+ $01 constant ACSR_AC0O \ Analog Comparator 0 Output Bit
+\ DA_CONVERTER
+&172 constant DACH \ DAC Data Register High Byte
+ $FF constant DACH_DACH \ DAC Data Register High Byte Bits
+&171 constant DACL \ DAC Data Register Low Byte
+ $FF constant DACL_DACL \ DAC Data Register Low Byte Bits
+&170 constant DACON \ DAC Control Register
+ $80 constant DACON_DAATE \ DAC Auto Trigger Enable Bit
+ $70 constant DACON_DATS \ DAC Trigger Selection Bits
+ $04 constant DACON_DALA \ DAC Left Adjust
+ $01 constant DACON_DAEN \ DAC Enable Bit
+\ CPU
+&95 constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ $08 constant SREG_V \ Two's Complement Overflow Flag
+ $04 constant SREG_N \ Negative Flag
+ $02 constant SREG_Z \ Zero Flag
+ $01 constant SREG_C \ Carry Flag
+&93 constant SP \ Stack Pointer
+&85 constant MCUCR \ MCU Control Register
+ $80 constant MCUCR_SPIPS \ SPI Pin Select
+ $10 constant MCUCR_PUD \ Pull-up disable
+ $02 constant MCUCR_IVSEL \ Interrupt Vector Select
+ $01 constant MCUCR_IVCE \ Interrupt Vector Change Enable
+&84 constant MCUSR \ MCU Status Register
+ $08 constant MCUSR_WDRF \ Watchdog Reset Flag
+ $04 constant MCUSR_BORF \ Brown-out Reset Flag
+ $02 constant MCUSR_EXTRF \ External Reset Flag
+ $01 constant MCUSR_PORF \ Power-on reset flag
+&102 constant OSCCAL \ Oscillator Calibration Value
+&97 constant CLKPR \
+ $80 constant CLKPR_CLKPCE \
+ $0F constant CLKPR_CLKPS \
+&83 constant SMCR \ Sleep Mode Control Register
+ $0E constant SMCR_SM \ Sleep Mode Select bits
+ $01 constant SMCR_SE \ Sleep Enable
+&59 constant GPIOR3 \ General Purpose IO Register 3
+ $FF constant GPIOR3_GPIOR \ General Purpose IO Register 3 bis
+&58 constant GPIOR2 \ General Purpose IO Register 2
+ $FF constant GPIOR2_GPIOR \ General Purpose IO Register 2 bis
+&57 constant GPIOR1 \ General Purpose IO Register 1
+ $FF constant GPIOR1_GPIOR \ General Purpose IO Register 1 bis
+&62 constant GPIOR0 \ General Purpose IO Register 0
+ $80 constant GPIOR0_GPIOR07 \ General Purpose IO Register 0 bit 7
+ $40 constant GPIOR0_GPIOR06 \ General Purpose IO Register 0 bit 6
+ $20 constant GPIOR0_GPIOR05 \ General Purpose IO Register 0 bit 5
+ $10 constant GPIOR0_GPIOR04 \ General Purpose IO Register 0 bit 4
+ $08 constant GPIOR0_GPIOR03 \ General Purpose IO Register 0 bit 3
+ $04 constant GPIOR0_GPIOR02 \ General Purpose IO Register 0 bit 2
+ $02 constant GPIOR0_GPIOR01 \ General Purpose IO Register 0 bit 1
+ $01 constant GPIOR0_GPIOR00 \ General Purpose IO Register 0 bit 0
+&73 constant PLLCSR \ PLL Control And Status Register
+ $04 constant PLLCSR_PLLF \ PLL Factor
+ $02 constant PLLCSR_PLLE \ PLL Enable
+ $01 constant PLLCSR_PLOCK \ PLL Lock Detector
+&100 constant PRR \ Power Reduction Register
+ $E0 constant PRR_PRPSC \ Power Reduction PSC2
+ $10 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
+ $08 constant PRR_PRTIM0 \ Power Reduction Timer/Counter0
+ $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
+ $02 constant PRR_PRUSART0 \ Power Reduction USART
+ $01 constant PRR_PRADC \ Power Reduction ADC
+\ PORTE
+&46 constant PORTE \ Port E Data Register
+&45 constant DDRE \ Port E Data Direction Register
+&44 constant PINE \ Port E Input Pins
+\ TIMER_COUNTER_0
+&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
+ $04 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare Match B Interrupt Enable
+ $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match A Interrupt Enable
+ $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
+&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
+ $04 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare Flag 0B
+ $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0A
+ $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
+&68 constant TCCR0A \ Timer/Counter Control Register A
+ $C0 constant TCCR0A_COM0A \ Compare Output Mode, Phase Correct PWM Mode
+ $30 constant TCCR0A_COM0B \ Compare Output Mode, Fast PWm
+ $03 constant TCCR0A_WGM0 \ Waveform Generation Mode
+&69 constant TCCR0B \ Timer/Counter Control Register B
+ $80 constant TCCR0B_FOC0A \ Force Output Compare A
+ $40 constant TCCR0B_FOC0B \ Force Output Compare B
+ $08 constant TCCR0B_WGM02 \
+ $07 constant TCCR0B_CS0 \ Clock Select
+&70 constant TCNT0 \ Timer/Counter0
+&71 constant OCR0A \ Timer/Counter0 Output Compare Register
+&72 constant OCR0B \ Timer/Counter0 Output Compare Register
+&67 constant GTCCR \ General Timer/Counter Control Register
+ $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
+ $40 constant GTCCR_ICPSEL1 \ Timer1 Input Capture Selection Bit
+ $01 constant GTCCR_PSR10 \ Prescaler Reset Timer/Counter1 and Timer/Counter0
+\ TIMER_COUNTER_1
+&111 constant TIMSK1 \ Timer/Counter Interrupt Mask Register
+ $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
+ $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output CompareB Match Interrupt Enable
+ $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output CompareA Match Interrupt Enable
+ $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
+&54 constant TIFR1 \ Timer/Counter Interrupt Flag register
+ $20 constant TIFR1_ICF1 \ Input Capture Flag 1
+ $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
+ $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
+ $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
+&128 constant TCCR1A \ Timer/Counter1 Control Register A
+ $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
+ $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
+ $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
+&129 constant TCCR1B \ Timer/Counter1 Control Register B
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
+ $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
+&130 constant TCCR1C \ Timer/Counter1 Control Register C
+ $80 constant TCCR1C_FOC1A \
+ $40 constant TCCR1C_FOC1B \
+&132 constant TCNT1 \ Timer/Counter1 Bytes
+&136 constant OCR1A \ Timer/Counter1 Output Compare Register Bytes
+&138 constant OCR1B \ Timer/Counter1 Output Compare Register Bytes
+&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
+\ AD_CONVERTER
+&124 constant ADMUX \ The ADC multiplexer Selection Register
+ $C0 constant ADMUX_REFS \ Reference Selection Bits
+ $20 constant ADMUX_ADLAR \ Left Adjust Result
+ $0F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
+&122 constant ADCSRA \ The ADC Control and Status register
+ $80 constant ADCSRA_ADEN \ ADC Enable
+ $40 constant ADCSRA_ADSC \ ADC Start Conversion
+ $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
+ $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
+ $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
+ $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
+&120 constant ADC \ ADC Data Register Bytes
+&123 constant ADCSRB \ ADC Control and Status Register B
+&126 constant DIDR0 \ Digital Input Disable Register 0
+&127 constant DIDR1 \ Digital Input Disable Register 0
+ $20 constant DIDR1_ACMP0D \
+ $10 constant DIDR1_AMP0PD \
+ $08 constant DIDR1_AMP0ND \
+ $04 constant DIDR1_ADC10D \
+ $02 constant DIDR1_ADC9D \
+ $01 constant DIDR1_ADC8D \
+&118 constant AMP0CSR \
+ $80 constant AMP0CSR_AMP0EN \
+ $40 constant AMP0CSR_AMP0IS \
+ $30 constant AMP0CSR_AMP0G \
+ $03 constant AMP0CSR_AMP0TS \
+&119 constant AMP1CSR \
+ $80 constant AMP1CSR_AMP1EN \
+ $40 constant AMP1CSR_AMP1IS \
+ $30 constant AMP1CSR_AMP1G \
+ $03 constant AMP1CSR_AMP1TS \
+\ USART
+&198 constant UDR \ USART I/O Data Register
+&192 constant UCSRA \ USART Control and Status register A
+ $80 constant UCSRA_RXC \ USART Receive Complete
+ $40 constant UCSRA_TXC \ USART Transmitt Complete
+ $20 constant UCSRA_UDRE \ USART Data Register Empty
+ $10 constant UCSRA_FE \ Framing Error
+ $08 constant UCSRA_DOR \ Data Overrun
+ $04 constant UCSRA_UPE \ USART Parity Error
+ $02 constant UCSRA_U2X \ Double USART Transmission Bit
+ $01 constant UCSRA_MPCM \ Multi-processor Communication Mode
+&193 constant UCSRB \ USART Control an Status register B
+ $80 constant UCSRB_RXCIE \ RX Complete Interrupt Enable
+ $40 constant UCSRB_TXCIE \ TX Complete Interrupt Enable
+ $20 constant UCSRB_UDRIE \ USART Data Register Empty Interrupt Enable
+ $10 constant UCSRB_RXEN \ Receiver Enable
+ $08 constant UCSRB_TXEN \ Transmitter Enable
+ $04 constant UCSRB_UCSZ2 \ Character Size
+ $02 constant UCSRB_RXB8 \ Receive Data Bit 8
+ $01 constant UCSRB_TXB8 \ Transmit Data Bit 8
+&194 constant UCSRC \ USART Control an Status register C
+ $40 constant UCSRC_UMSEL0 \ USART Mode Select
+ $30 constant UCSRC_UPM \ Parity Mode Bits
+ $08 constant UCSRC_USBS \ Stop Bit Select
+ $06 constant UCSRC_UCSZ \ Character Size Bits
+ $01 constant UCSRC_UCPOL \ Clock Polarity
+&197 constant UBRRH \ USART Baud Rate Register High Byte
+ $0F constant UBRRH_UBRR \ USART Baud Rate Register Bits
+&196 constant UBRRL \ USART Baud Rate Register Low Byte
+ $FF constant UBRRL_UBRR \ USART Baud Rate Register bits
+\ SPI
+&76 constant SPCR \ SPI Control Register
+ $80 constant SPCR_SPIE \ SPI Interrupt Enable
+ $40 constant SPCR_SPE \ SPI Enable
+ $20 constant SPCR_DORD \ Data Order
+ $10 constant SPCR_MSTR \ Master/Slave Select
+ $08 constant SPCR_CPOL \ Clock polarity
+ $04 constant SPCR_CPHA \ Clock Phase
+ $03 constant SPCR_SPR \ SPI Clock Rate Selects
+&77 constant SPSR \ SPI Status Register
+ $80 constant SPSR_SPIF \ SPI Interrupt Flag
+ $40 constant SPSR_WCOL \ Write Collision Flag
+ $01 constant SPSR_SPI2X \ Double SPI Speed Bit
+&78 constant SPDR \ SPI Data Register
+\ WATCHDOG
+&96 constant WDTCSR \ Watchdog Timer Control Register
+ $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Flag
+ $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Enable
+ $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
+ $10 constant WDTCSR_WDCE \ Watchdog Change Enable
+ $08 constant WDTCSR_WDE \ Watch Dog Enable
+\ EXTERNAL_INTERRUPT
+&105 constant EICRA \ External Interrupt Control Register A
+ $30 constant EICRA_ISC2 \ External Interrupt Sense Control Bit
+ $0C constant EICRA_ISC1 \ External Interrupt Sense Control Bit
+ $03 constant EICRA_ISC0 \ External Interrupt Sense Control Bit
+&61 constant EIMSK \ External Interrupt Mask Register
+ $07 constant EIMSK_INT \ External Interrupt Request 2 Enable
+&60 constant EIFR \ External Interrupt Flag Register
+ $07 constant EIFR_INTF \ External Interrupt Flags
+\ EEPROM
+&65 constant EEAR \ EEPROM Read/Write Access Bytes
+&64 constant EEDR \ EEPROM Data Register
+&63 constant EECR \ EEPROM Control Register
+ $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
+ $04 constant EECR_EEMWE \ EEPROM Master Write Enable
+ $02 constant EECR_EEWE \ EEPROM Write Enable
+ $01 constant EECR_EERE \ EEPROM Read Enable
+\ PSC0
+&222 constant PICR0 \ PSC 0 Input Capture Register
+&221 constant PFRC0B \ PSC 0 Input B Control
+ $80 constant PFRC0B_PCAE0B \ PSC 0 Capture Enable Input Part B
+ $40 constant PFRC0B_PISEL0B \ PSC 0 Input Select for Part B
+ $20 constant PFRC0B_PELEV0B \ PSC 0 Edge Level Selector on Input Part B
+ $10 constant PFRC0B_PFLTE0B \ PSC 0 Filter Enable on Input Part B
+ $0F constant PFRC0B_PRFM0B \ PSC 0 Retrigger and Fault Mode for Part B
+&220 constant PFRC0A \ PSC 0 Input A Control
+ $80 constant PFRC0A_PCAE0A \ PSC 0 Capture Enable Input Part A
+ $40 constant PFRC0A_PISEL0A \ PSC 0 Input Select for Part A
+ $20 constant PFRC0A_PELEV0A \ PSC 0 Edge Level Selector on Input Part A
+ $10 constant PFRC0A_PFLTE0A \ PSC 0 Filter Enable on Input Part A
+ $0F constant PFRC0A_PRFM0A \ PSC 0 Retrigger and Fault Mode for Part A
+&219 constant PCTL0 \ PSC 0 Control Register
+ $C0 constant PCTL0_PPRE0 \ PSC 0 Prescaler Selects
+ $20 constant PCTL0_PBFM0 \ PSC 0 Balance Flank Width Modulation
+ $10 constant PCTL0_PAOC0B \ PSC 0 Asynchronous Output Control B
+ $08 constant PCTL0_PAOC0A \ PSC 0 Asynchronous Output Control A
+ $04 constant PCTL0_PARUN0 \ PSC0 Auto Run
+ $02 constant PCTL0_PCCYC0 \ PSC0 Complete Cycle
+ $01 constant PCTL0_PRUN0 \ PSC 0 Run
+&218 constant PCNF0 \ PSC 0 Configuration Register
+ $80 constant PCNF0_PFIFTY0 \ PSC 0 Fifty
+ $40 constant PCNF0_PALOCK0 \ PSC 0 Autolock
+ $20 constant PCNF0_PLOCK0 \ PSC 0 Lock
+ $18 constant PCNF0_PMODE0 \ PSC 0 Mode
+ $04 constant PCNF0_POP0 \ PSC 0 Output Polarity
+ $02 constant PCNF0_PCLKSEL0 \ PSC 0 Input Clock Select
+&216 constant OCR0RB \ Output Compare RB Register
+&214 constant OCR0SB \ Output Compare SB Register
+&212 constant OCR0RA \ Output Compare RA Register
+&210 constant OCR0SA \ Output Compare SA Register
+&208 constant PSOC0 \ PSC0 Synchro and Output Configuration
+ $30 constant PSOC0_PSYNC0 \ Synchronization Out for ADC Selection
+ $04 constant PSOC0_POEN0B \ PSCOUT01 Output Enable
+ $01 constant PSOC0_POEN0A \ PSCOUT00 Output Enable
+&161 constant PIM0 \ PSC0 Interrupt Mask Register
+ $20 constant PIM0_PSEIE0 \ PSC 0 Synchro Error Interrupt Enable
+ $10 constant PIM0_PEVE0B \ External Event B Interrupt Enable
+ $08 constant PIM0_PEVE0A \ External Event A Interrupt Enable
+ $01 constant PIM0_PEOPE0 \ End of Cycle Interrupt Enable
+&160 constant PIFR0 \ PSC0 Interrupt Flag Register
+ $80 constant PIFR0_POAC0B \ PSC 0 Output A Activity
+ $40 constant PIFR0_POAC0A \ PSC 0 Output A Activity
+ $20 constant PIFR0_PSEI0 \ PSC 0 Synchro Error Interrupt
+ $10 constant PIFR0_PEV0B \ External Event B Interrupt
+ $08 constant PIFR0_PEV0A \ External Event A Interrupt
+ $06 constant PIFR0_PRN0 \ Ramp Number
+ $01 constant PIFR0_PEOP0 \ End of PSC0 Interrupt
+\ PSC2
+&254 constant PICR2 \ PSC 2 Input Capture Register
+&253 constant PFRC2B \ PSC 2 Input B Control
+ $80 constant PFRC2B_PCAE2B \ PSC 2 Capture Enable Input Part B
+ $40 constant PFRC2B_PISEL2B \ PSC 2 Input Select for Part B
+ $20 constant PFRC2B_PELEV2B \ PSC 2 Edge Level Selector on Input Part B
+ $10 constant PFRC2B_PFLTE2B \ PSC 2 Filter Enable on Input Part B
+ $0F constant PFRC2B_PRFM2B \ PSC 2 Retrigger and Fault Mode for Part B
+&252 constant PFRC2A \ PSC 2 Input B Control
+ $80 constant PFRC2A_PCAE2A \ PSC 2 Capture Enable Input Part A
+ $40 constant PFRC2A_PISEL2A \ PSC 2 Input Select for Part A
+ $20 constant PFRC2A_PELEV2A \ PSC 2 Edge Level Selector on Input Part A
+ $10 constant PFRC2A_PFLTE2A \ PSC 2 Filter Enable on Input Part A
+ $0F constant PFRC2A_PRFM2A \ PSC 2 Retrigger and Fault Mode for Part A
+&251 constant PCTL2 \ PSC 2 Control Register
+ $C0 constant PCTL2_PPRE2 \ PSC 2 Prescaler Selects
+ $20 constant PCTL2_PBFM2 \ Balance Flank Width Modulation
+ $10 constant PCTL2_PAOC2B \ PSC 2 Asynchronous Output Control B
+ $08 constant PCTL2_PAOC2A \ PSC 2 Asynchronous Output Control A
+ $04 constant PCTL2_PARUN2 \ PSC2 Auto Run
+ $02 constant PCTL2_PCCYC2 \ PSC2 Complete Cycle
+ $01 constant PCTL2_PRUN2 \ PSC 2 Run
+&250 constant PCNF2 \ PSC 2 Configuration Register
+ $80 constant PCNF2_PFIFTY2 \ PSC 2 Fifty
+ $40 constant PCNF2_PALOCK2 \ PSC 2 Autolock
+ $20 constant PCNF2_PLOCK2 \ PSC 2 Lock
+ $18 constant PCNF2_PMODE2 \ PSC 2 Mode
+ $04 constant PCNF2_POP2 \ PSC 2 Output Polarity
+ $02 constant PCNF2_PCLKSEL2 \ PSC 2 Input Clock Select
+ $01 constant PCNF2_POME2 \ PSC 2 Output Matrix Enable
+&248 constant OCR2RB \ Output Compare RB Register
+&246 constant OCR2SB \ Output Compare SB Register
+&244 constant OCR2RA \ Output Compare RA Register
+&242 constant OCR2SA \ Output Compare SA Register
+&241 constant POM2 \ PSC 2 Output Matrix
+ $F0 constant POM2_POMV2B \ Output Matrix Output B Ramps
+ $0F constant POM2_POMV2A \ Output Matrix Output A Ramps
+&240 constant PSOC2 \ PSC2 Synchro and Output Configuration
+ $C0 constant PSOC2_POS2 \ PSC 2 Output 23 Select
+ $30 constant PSOC2_PSYNC2_ \ Synchronization Out for ADC Selection
+ $08 constant PSOC2_POEN2D \ PSCOUT23 Output Enable
+ $04 constant PSOC2_POEN2B \ PSCOUT21 Output Enable
+ $02 constant PSOC2_POEN2C \ PSCOUT22 Output Enable
+ $01 constant PSOC2_POEN2A \ PSCOUT20 Output Enable
+&165 constant PIM2 \ PSC2 Interrupt Mask Register
+ $20 constant PIM2_PSEIE2 \ PSC 2 Synchro Error Interrupt Enable
+ $10 constant PIM2_PEVE2B \ External Event B Interrupt Enable
+ $08 constant PIM2_PEVE2A \ External Event A Interrupt Enable
+ $01 constant PIM2_PEOPE2 \ End of Cycle Interrupt Enable
+&164 constant PIFR2 \ PSC2 Interrupt Flag Register
+ $80 constant PIFR2_POAC2B \ PSC 2 Output A Activity
+ $40 constant PIFR2_POAC2A \ PSC 2 Output A Activity
+ $20 constant PIFR2_PSEI2 \ PSC 2 Synchro Error Interrupt
+ $10 constant PIFR2_PEV2B \ External Event B Interrupt
+ $08 constant PIFR2_PEV2A \ External Event A Interrupt
+ $06 constant PIFR2_PRN2 \ Ramp Number
+ $01 constant PIFR2_PEOP2 \ End of PSC2 Interrupt
+
+\ Interrupts
+&2 constant PSC2_CAPTAddr \ PSC2 Capture Event
+&4 constant PSC2_ECAddr \ PSC2 End Cycle
+&6 constant PSC1_CAPTAddr \ PSC1 Capture Event
+&8 constant PSC1_ECAddr \ PSC1 End Cycle
+&10 constant PSC0_CAPTAddr \ PSC0 Capture Event
+&12 constant PSC0_ECAddr \ PSC0 End Cycle
+&14 constant ANALOG_COMP_0Addr \ Analog Comparator 0
+&16 constant ANALOG_COMP_1Addr \ Analog Comparator 1
+&18 constant ANALOG_COMP_2Addr \ Analog Comparator 2
+&20 constant INT0Addr \ External Interrupt Request 0
+&22 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+&24 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
+&26 constant TIMER1_COMPBAddr \ Timer/Counter Compare Match B
+&28 constant RESERVED15Addr \
+&30 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+&32 constant TIMER0_COMP_AAddr \ Timer/Counter0 Compare Match A
+&34 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
+&36 constant ADCAddr \ ADC Conversion Complete
+&38 constant INT1Addr \ External Interrupt Request 1
+&40 constant SPI__STCAddr \ SPI Serial Transfer Complete
+&42 constant USART__RXAddr \ USART, Rx Complete
+&44 constant USART__UDREAddr \ USART Data Register Empty
+&46 constant USART__TXAddr \ USART, Tx Complete
+&48 constant INT2Addr \ External Interrupt Request 2
+&50 constant WDTAddr \ Watchdog Timeout Interrupt
+&52 constant EE_READYAddr \ EEPROM Ready
+&54 constant TIMER0_COMPBAddr \ Timer Counter 0 Compare Match B
+&56 constant INT3Addr \ External Interrupt Request 3
+&58 constant RESERVED30Addr \
+&60 constant RESERVED31Addr \
+&62 constant SPM_READYAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/at90pwm216/device.asm b/amforth-6.5/avr8/devices/at90pwm216/device.asm
new file mode 100644
index 0000000..01c61c6
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90pwm216/device.asm
@@ -0,0 +1,123 @@
+; Partname: AT90PWM216
+; generated automatically, do not edit
+
+.nolist
+ .include "pwm216def.inc"
+.list
+
+.equ ramstart = 256
+.equ CELLSIZE = 2
+.macro readflashcell
+ lsl zl
+ rol zh
+ lpm @0, Z+
+ lpm @1, Z+
+.endmacro
+.macro writeflashcell
+ lsl zl
+ rol zh
+.endmacro
+.set WANT_PORTB = 0
+.set WANT_PORTD = 0
+.set WANT_BOOT_LOAD = 0
+.set WANT_EUSART = 0
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_DA_CONVERTER = 0
+.set WANT_CPU = 0
+.set WANT_PORTE = 0
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_AD_CONVERTER = 0
+.set WANT_USART = 0
+.set WANT_SPI = 0
+.set WANT_WATCHDOG = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_EEPROM = 0
+.set WANT_PSC0 = 0
+.set WANT_PSC2 = 0
+.equ intvecsize = 2 ; please verify; flash size: 16384 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.org 2
+ rcall isr ; PSC2 Capture Event
+.org 4
+ rcall isr ; PSC2 End Cycle
+.org 6
+ rcall isr ; PSC1 Capture Event
+.org 8
+ rcall isr ; PSC1 End Cycle
+.org 10
+ rcall isr ; PSC0 Capture Event
+.org 12
+ rcall isr ; PSC0 End Cycle
+.org 14
+ rcall isr ; Analog Comparator 0
+.org 16
+ rcall isr ; Analog Comparator 1
+.org 18
+ rcall isr ; Analog Comparator 2
+.org 20
+ rcall isr ; External Interrupt Request 0
+.org 22
+ rcall isr ; Timer/Counter1 Capture Event
+.org 24
+ rcall isr ; Timer/Counter1 Compare Match A
+.org 26
+ rcall isr ; Timer/Counter Compare Match B
+.org 28
+ rcall isr ;
+.org 30
+ rcall isr ; Timer/Counter1 Overflow
+.org 32
+ rcall isr ; Timer/Counter0 Compare Match A
+.org 34
+ rcall isr ; Timer/Counter0 Overflow
+.org 36
+ rcall isr ; ADC Conversion Complete
+.org 38
+ rcall isr ; External Interrupt Request 1
+.org 40
+ rcall isr ; SPI Serial Transfer Complete
+.org 42
+ rcall isr ; USART, Rx Complete
+.org 44
+ rcall isr ; USART Data Register Empty
+.org 46
+ rcall isr ; USART, Tx Complete
+.org 48
+ rcall isr ; External Interrupt Request 2
+.org 50
+ rcall isr ; Watchdog Timeout Interrupt
+.org 52
+ rcall isr ; EEPROM Ready
+.org 54
+ rcall isr ; Timer Counter 0 Compare Match B
+.org 56
+ rcall isr ; External Interrupt Request 3
+.org 58
+ rcall isr ;
+.org 60
+ rcall isr ;
+.org 62
+ rcall isr ; Store Program Memory Read
+.equ INTVECTORS = 32
+.nooverlap
+
+; compatability layer (maybe empty)
+.equ EEPE = EEWE
+.equ EEMPE = EEMWE
+
+; controller data area, environment query mcu-info
+mcu_info:
+mcu_ramsize:
+ .dw 1024
+mcu_eepromsize:
+ .dw 512
+mcu_maxdp:
+ .dw 12288
+mcu_numints:
+ .dw 32
+mcu_name:
+ .dw 10
+ .db "AT90PWM216"
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/at90pwm216/device.inc b/amforth-6.5/avr8/devices/at90pwm216/device.inc
new file mode 100644
index 0000000..dd83403
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90pwm216/device.inc
@@ -0,0 +1,1281 @@
+; Partname: AT90PWM216
+; generated automatically, no not edit
+
+.if WANT_PORTB == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw 37
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw 36
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw 35
+
+.endif
+.if WANT_PORTD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw 43
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw 42
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw 41
+
+.endif
+.if WANT_BOOT_LOAD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control Register
+VE_SPMCSR:
+ .dw $ff06
+ .db "SPMCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCSR
+XT_SPMCSR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCSR:
+ .dw 87
+
+.endif
+.if WANT_EUSART == 1
+; ( -- addr ) System Constant
+; R( -- )
+; EUSART I/O Data Register
+VE_EUDR:
+ .dw $ff04
+ .db "EUDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EUDR
+XT_EUDR:
+ .dw PFA_DOVARIABLE
+PFA_EUDR:
+ .dw 206
+; ( -- addr ) System Constant
+; R( -- )
+; EUSART Control and Status Register A
+VE_EUCSRA:
+ .dw $ff06
+ .db "EUCSRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EUCSRA
+XT_EUCSRA:
+ .dw PFA_DOVARIABLE
+PFA_EUCSRA:
+ .dw 200
+; ( -- addr ) System Constant
+; R( -- )
+; EUSART Control Register B
+VE_EUCSRB:
+ .dw $ff06
+ .db "EUCSRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EUCSRB
+XT_EUCSRB:
+ .dw PFA_DOVARIABLE
+PFA_EUCSRB:
+ .dw 201
+; ( -- addr ) System Constant
+; R( -- )
+; EUSART Status Register C
+VE_EUCSRC:
+ .dw $ff06
+ .db "EUCSRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EUCSRC
+XT_EUCSRC:
+ .dw PFA_DOVARIABLE
+PFA_EUCSRC:
+ .dw 202
+; ( -- addr ) System Constant
+; R( -- )
+; Manchester Receiver Baud Rate Register High Byte
+VE_MUBRRH:
+ .dw $ff06
+ .db "MUBRRH"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MUBRRH
+XT_MUBRRH:
+ .dw PFA_DOVARIABLE
+PFA_MUBRRH:
+ .dw 205
+; ( -- addr ) System Constant
+; R( -- )
+; Manchester Receiver Baud Rate Register Low Byte
+VE_MUBRRL:
+ .dw $ff06
+ .db "MUBRRL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MUBRRL
+XT_MUBRRL:
+ .dw PFA_DOVARIABLE
+PFA_MUBRRL:
+ .dw 204
+
+.endif
+.if WANT_ANALOG_COMPARATOR == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator 0 Control Register
+VE_AC0CON:
+ .dw $ff06
+ .db "AC0CON"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_AC0CON
+XT_AC0CON:
+ .dw PFA_DOVARIABLE
+PFA_AC0CON:
+ .dw 173
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator 1 Control Register
+VE_AC1CON:
+ .dw $ff06
+ .db "AC1CON"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_AC1CON
+XT_AC1CON:
+ .dw PFA_DOVARIABLE
+PFA_AC1CON:
+ .dw 174
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator 2 Control Register
+VE_AC2CON:
+ .dw $ff06
+ .db "AC2CON"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_AC2CON
+XT_AC2CON:
+ .dw PFA_DOVARIABLE
+PFA_AC2CON:
+ .dw 175
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw 80
+
+.endif
+.if WANT_DA_CONVERTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; DAC Data Register High Byte
+VE_DACH:
+ .dw $ff04
+ .db "DACH"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DACH
+XT_DACH:
+ .dw PFA_DOVARIABLE
+PFA_DACH:
+ .dw 172
+; ( -- addr ) System Constant
+; R( -- )
+; DAC Data Register Low Byte
+VE_DACL:
+ .dw $ff04
+ .db "DACL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DACL
+XT_DACL:
+ .dw PFA_DOVARIABLE
+PFA_DACL:
+ .dw 171
+; ( -- addr ) System Constant
+; R( -- )
+; DAC Control Register
+VE_DACON:
+ .dw $ff05
+ .db "DACON",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DACON
+XT_DACON:
+ .dw PFA_DOVARIABLE
+PFA_DACON:
+ .dw 170
+
+.endif
+.if WANT_CPU == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw 95
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer
+VE_SP:
+ .dw $ff02
+ .db "SP"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SP
+XT_SP:
+ .dw PFA_DOVARIABLE
+PFA_SP:
+ .dw 93
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw 85
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Status Register
+VE_MCUSR:
+ .dw $ff05
+ .db "MCUSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUSR
+XT_MCUSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUSR:
+ .dw 84
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Calibration Value
+VE_OSCCAL:
+ .dw $ff06
+ .db "OSCCAL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSCCAL
+XT_OSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_OSCCAL:
+ .dw 102
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_CLKPR:
+ .dw $ff05
+ .db "CLKPR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKPR
+XT_CLKPR:
+ .dw PFA_DOVARIABLE
+PFA_CLKPR:
+ .dw 97
+; ( -- addr ) System Constant
+; R( -- )
+; Sleep Mode Control Register
+VE_SMCR:
+ .dw $ff04
+ .db "SMCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SMCR
+XT_SMCR:
+ .dw PFA_DOVARIABLE
+PFA_SMCR:
+ .dw 83
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 3
+VE_GPIOR3:
+ .dw $ff06
+ .db "GPIOR3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR3
+XT_GPIOR3:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR3:
+ .dw 59
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 2
+VE_GPIOR2:
+ .dw $ff06
+ .db "GPIOR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR2
+XT_GPIOR2:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR2:
+ .dw 58
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 1
+VE_GPIOR1:
+ .dw $ff06
+ .db "GPIOR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR1
+XT_GPIOR1:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR1:
+ .dw 57
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 0
+VE_GPIOR0:
+ .dw $ff06
+ .db "GPIOR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR0
+XT_GPIOR0:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR0:
+ .dw 62
+; ( -- addr ) System Constant
+; R( -- )
+; PLL Control And Status Register
+VE_PLLCSR:
+ .dw $ff06
+ .db "PLLCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PLLCSR
+XT_PLLCSR:
+ .dw PFA_DOVARIABLE
+PFA_PLLCSR:
+ .dw 73
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register
+VE_PRR:
+ .dw $ff03
+ .db "PRR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR
+XT_PRR:
+ .dw PFA_DOVARIABLE
+PFA_PRR:
+ .dw 100
+
+.endif
+.if WANT_PORTE == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port E Data Register
+VE_PORTE:
+ .dw $ff05
+ .db "PORTE",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTE
+XT_PORTE:
+ .dw PFA_DOVARIABLE
+PFA_PORTE:
+ .dw 46
+; ( -- addr ) System Constant
+; R( -- )
+; Port E Data Direction Register
+VE_DDRE:
+ .dw $ff04
+ .db "DDRE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRE
+XT_DDRE:
+ .dw PFA_DOVARIABLE
+PFA_DDRE:
+ .dw 45
+; ( -- addr ) System Constant
+; R( -- )
+; Port E Input Pins
+VE_PINE:
+ .dw $ff04
+ .db "PINE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINE
+XT_PINE:
+ .dw PFA_DOVARIABLE
+PFA_PINE:
+ .dw 44
+
+.endif
+.if WANT_TIMER_COUNTER_0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Mask Register
+VE_TIMSK0:
+ .dw $ff06
+ .db "TIMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK0
+XT_TIMSK0:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK0:
+ .dw 110
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Flag register
+VE_TIFR0:
+ .dw $ff05
+ .db "TIFR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR0
+XT_TIFR0:
+ .dw PFA_DOVARIABLE
+PFA_TIFR0:
+ .dw 53
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register A
+VE_TCCR0A:
+ .dw $ff06
+ .db "TCCR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0A
+XT_TCCR0A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0A:
+ .dw 68
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register B
+VE_TCCR0B:
+ .dw $ff06
+ .db "TCCR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0B
+XT_TCCR0B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0B:
+ .dw 69
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw 70
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0A:
+ .dw $ff05
+ .db "OCR0A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0A
+XT_OCR0A:
+ .dw PFA_DOVARIABLE
+PFA_OCR0A:
+ .dw 71
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0B:
+ .dw $ff05
+ .db "OCR0B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0B
+XT_OCR0B:
+ .dw PFA_DOVARIABLE
+PFA_OCR0B:
+ .dw 72
+; ( -- addr ) System Constant
+; R( -- )
+; General Timer/Counter Control Register
+VE_GTCCR:
+ .dw $ff05
+ .db "GTCCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GTCCR
+XT_GTCCR:
+ .dw PFA_DOVARIABLE
+PFA_GTCCR:
+ .dw 67
+
+.endif
+.if WANT_TIMER_COUNTER_1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Mask Register
+VE_TIMSK1:
+ .dw $ff06
+ .db "TIMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK1
+XT_TIMSK1:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK1:
+ .dw 111
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Flag register
+VE_TIFR1:
+ .dw $ff05
+ .db "TIFR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR1
+XT_TIFR1:
+ .dw PFA_DOVARIABLE
+PFA_TIFR1:
+ .dw 54
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw 128
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw 129
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register C
+VE_TCCR1C:
+ .dw $ff06
+ .db "TCCR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1C
+XT_TCCR1C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1C:
+ .dw 130
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Bytes
+VE_TCNT1:
+ .dw $ff05
+ .db "TCNT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1
+XT_TCNT1:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1:
+ .dw 132
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register Bytes
+VE_OCR1A:
+ .dw $ff05
+ .db "OCR1A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1A
+XT_OCR1A:
+ .dw PFA_DOVARIABLE
+PFA_OCR1A:
+ .dw 136
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register Bytes
+VE_OCR1B:
+ .dw $ff05
+ .db "OCR1B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1B
+XT_OCR1B:
+ .dw PFA_DOVARIABLE
+PFA_OCR1B:
+ .dw 138
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Bytes
+VE_ICR1:
+ .dw $ff04
+ .db "ICR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1
+XT_ICR1:
+ .dw PFA_DOVARIABLE
+PFA_ICR1:
+ .dw 134
+
+.endif
+.if WANT_AD_CONVERTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC multiplexer Selection Register
+VE_ADMUX:
+ .dw $ff05
+ .db "ADMUX",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADMUX
+XT_ADMUX:
+ .dw PFA_DOVARIABLE
+PFA_ADMUX:
+ .dw 124
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register
+VE_ADCSRA:
+ .dw $ff06
+ .db "ADCSRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRA
+XT_ADCSRA:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRA:
+ .dw 122
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register Bytes
+VE_ADC:
+ .dw $ff03
+ .db "ADC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADC
+XT_ADC:
+ .dw PFA_DOVARIABLE
+PFA_ADC:
+ .dw 120
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Control and Status Register B
+VE_ADCSRB:
+ .dw $ff06
+ .db "ADCSRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRB
+XT_ADCSRB:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRB:
+ .dw 123
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 0
+VE_DIDR0:
+ .dw $ff05
+ .db "DIDR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR0
+XT_DIDR0:
+ .dw PFA_DOVARIABLE
+PFA_DIDR0:
+ .dw 126
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 0
+VE_DIDR1:
+ .dw $ff05
+ .db "DIDR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR1
+XT_DIDR1:
+ .dw PFA_DOVARIABLE
+PFA_DIDR1:
+ .dw 127
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_AMP0CSR:
+ .dw $ff07
+ .db "AMP0CSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_AMP0CSR
+XT_AMP0CSR:
+ .dw PFA_DOVARIABLE
+PFA_AMP0CSR:
+ .dw 118
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_AMP1CSR:
+ .dw $ff07
+ .db "AMP1CSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_AMP1CSR
+XT_AMP1CSR:
+ .dw PFA_DOVARIABLE
+PFA_AMP1CSR:
+ .dw 119
+
+.endif
+.if WANT_USART == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR:
+ .dw $ff03
+ .db "UDR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR
+XT_UDR:
+ .dw PFA_DOVARIABLE
+PFA_UDR:
+ .dw 198
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status register A
+VE_UCSRA:
+ .dw $ff05
+ .db "UCSRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSRA
+XT_UCSRA:
+ .dw PFA_DOVARIABLE
+PFA_UCSRA:
+ .dw 192
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control an Status register B
+VE_UCSRB:
+ .dw $ff05
+ .db "UCSRB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSRB
+XT_UCSRB:
+ .dw PFA_DOVARIABLE
+PFA_UCSRB:
+ .dw 193
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control an Status register C
+VE_UCSRC:
+ .dw $ff05
+ .db "UCSRC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSRC
+XT_UCSRC:
+ .dw PFA_DOVARIABLE
+PFA_UCSRC:
+ .dw 194
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register High Byte
+VE_UBRRH:
+ .dw $ff05
+ .db "UBRRH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRRH
+XT_UBRRH:
+ .dw PFA_DOVARIABLE
+PFA_UBRRH:
+ .dw 197
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Low Byte
+VE_UBRRL:
+ .dw $ff05
+ .db "UBRRL",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRRL
+XT_UBRRL:
+ .dw PFA_DOVARIABLE
+PFA_UBRRL:
+ .dw 196
+
+.endif
+.if WANT_SPI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR:
+ .dw $ff04
+ .db "SPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR
+XT_SPCR:
+ .dw PFA_DOVARIABLE
+PFA_SPCR:
+ .dw 76
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR:
+ .dw $ff04
+ .db "SPSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR
+XT_SPSR:
+ .dw PFA_DOVARIABLE
+PFA_SPSR:
+ .dw 77
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR:
+ .dw $ff04
+ .db "SPDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR
+XT_SPDR:
+ .dw PFA_DOVARIABLE
+PFA_SPDR:
+ .dw 78
+
+.endif
+.if WANT_WATCHDOG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCSR:
+ .dw $ff06
+ .db "WDTCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCSR
+XT_WDTCSR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCSR:
+ .dw 96
+
+.endif
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register A
+VE_EICRA:
+ .dw $ff05
+ .db "EICRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRA
+XT_EICRA:
+ .dw PFA_DOVARIABLE
+PFA_EICRA:
+ .dw 105
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Mask Register
+VE_EIMSK:
+ .dw $ff05
+ .db "EIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIMSK
+XT_EIMSK:
+ .dw PFA_DOVARIABLE
+PFA_EIMSK:
+ .dw 61
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Flag Register
+VE_EIFR:
+ .dw $ff04
+ .db "EIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIFR
+XT_EIFR:
+ .dw PFA_DOVARIABLE
+PFA_EIFR:
+ .dw 60
+
+.endif
+.if WANT_EEPROM == 1
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Read/Write Access Bytes
+VE_EEAR:
+ .dw $ff04
+ .db "EEAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEAR
+XT_EEAR:
+ .dw PFA_DOVARIABLE
+PFA_EEAR:
+ .dw 65
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw 64
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw 63
+
+.endif
+.if WANT_PSC0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 0 Input Capture Register
+VE_PICR0:
+ .dw $ff05
+ .db "PICR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PICR0
+XT_PICR0:
+ .dw PFA_DOVARIABLE
+PFA_PICR0:
+ .dw 222
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 0 Input B Control
+VE_PFRC0B:
+ .dw $ff06
+ .db "PFRC0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PFRC0B
+XT_PFRC0B:
+ .dw PFA_DOVARIABLE
+PFA_PFRC0B:
+ .dw 221
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 0 Input A Control
+VE_PFRC0A:
+ .dw $ff06
+ .db "PFRC0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PFRC0A
+XT_PFRC0A:
+ .dw PFA_DOVARIABLE
+PFA_PFRC0A:
+ .dw 220
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 0 Control Register
+VE_PCTL0:
+ .dw $ff05
+ .db "PCTL0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCTL0
+XT_PCTL0:
+ .dw PFA_DOVARIABLE
+PFA_PCTL0:
+ .dw 219
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 0 Configuration Register
+VE_PCNF0:
+ .dw $ff05
+ .db "PCNF0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCNF0
+XT_PCNF0:
+ .dw PFA_DOVARIABLE
+PFA_PCNF0:
+ .dw 218
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare RB Register
+VE_OCR0RB:
+ .dw $ff06
+ .db "OCR0RB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0RB
+XT_OCR0RB:
+ .dw PFA_DOVARIABLE
+PFA_OCR0RB:
+ .dw 216
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare SB Register
+VE_OCR0SB:
+ .dw $ff06
+ .db "OCR0SB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0SB
+XT_OCR0SB:
+ .dw PFA_DOVARIABLE
+PFA_OCR0SB:
+ .dw 214
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare RA Register
+VE_OCR0RA:
+ .dw $ff06
+ .db "OCR0RA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0RA
+XT_OCR0RA:
+ .dw PFA_DOVARIABLE
+PFA_OCR0RA:
+ .dw 212
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare SA Register
+VE_OCR0SA:
+ .dw $ff06
+ .db "OCR0SA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0SA
+XT_OCR0SA:
+ .dw PFA_DOVARIABLE
+PFA_OCR0SA:
+ .dw 210
+; ( -- addr ) System Constant
+; R( -- )
+; PSC0 Synchro and Output Configuration
+VE_PSOC0:
+ .dw $ff05
+ .db "PSOC0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PSOC0
+XT_PSOC0:
+ .dw PFA_DOVARIABLE
+PFA_PSOC0:
+ .dw 208
+; ( -- addr ) System Constant
+; R( -- )
+; PSC0 Interrupt Mask Register
+VE_PIM0:
+ .dw $ff04
+ .db "PIM0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIM0
+XT_PIM0:
+ .dw PFA_DOVARIABLE
+PFA_PIM0:
+ .dw 161
+; ( -- addr ) System Constant
+; R( -- )
+; PSC0 Interrupt Flag Register
+VE_PIFR0:
+ .dw $ff05
+ .db "PIFR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIFR0
+XT_PIFR0:
+ .dw PFA_DOVARIABLE
+PFA_PIFR0:
+ .dw 160
+
+.endif
+.if WANT_PSC2 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 2 Input Capture Register
+VE_PICR2:
+ .dw $ff05
+ .db "PICR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PICR2
+XT_PICR2:
+ .dw PFA_DOVARIABLE
+PFA_PICR2:
+ .dw 254
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 2 Input B Control
+VE_PFRC2B:
+ .dw $ff06
+ .db "PFRC2B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PFRC2B
+XT_PFRC2B:
+ .dw PFA_DOVARIABLE
+PFA_PFRC2B:
+ .dw 253
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 2 Input B Control
+VE_PFRC2A:
+ .dw $ff06
+ .db "PFRC2A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PFRC2A
+XT_PFRC2A:
+ .dw PFA_DOVARIABLE
+PFA_PFRC2A:
+ .dw 252
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 2 Control Register
+VE_PCTL2:
+ .dw $ff05
+ .db "PCTL2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCTL2
+XT_PCTL2:
+ .dw PFA_DOVARIABLE
+PFA_PCTL2:
+ .dw 251
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 2 Configuration Register
+VE_PCNF2:
+ .dw $ff05
+ .db "PCNF2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCNF2
+XT_PCNF2:
+ .dw PFA_DOVARIABLE
+PFA_PCNF2:
+ .dw 250
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare RB Register
+VE_OCR2RB:
+ .dw $ff06
+ .db "OCR2RB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2RB
+XT_OCR2RB:
+ .dw PFA_DOVARIABLE
+PFA_OCR2RB:
+ .dw 248
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare SB Register
+VE_OCR2SB:
+ .dw $ff06
+ .db "OCR2SB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2SB
+XT_OCR2SB:
+ .dw PFA_DOVARIABLE
+PFA_OCR2SB:
+ .dw 246
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare RA Register
+VE_OCR2RA:
+ .dw $ff06
+ .db "OCR2RA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2RA
+XT_OCR2RA:
+ .dw PFA_DOVARIABLE
+PFA_OCR2RA:
+ .dw 244
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare SA Register
+VE_OCR2SA:
+ .dw $ff06
+ .db "OCR2SA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2SA
+XT_OCR2SA:
+ .dw PFA_DOVARIABLE
+PFA_OCR2SA:
+ .dw 242
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 2 Output Matrix
+VE_POM2:
+ .dw $ff04
+ .db "POM2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_POM2
+XT_POM2:
+ .dw PFA_DOVARIABLE
+PFA_POM2:
+ .dw 241
+; ( -- addr ) System Constant
+; R( -- )
+; PSC2 Synchro and Output Configuration
+VE_PSOC2:
+ .dw $ff05
+ .db "PSOC2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PSOC2
+XT_PSOC2:
+ .dw PFA_DOVARIABLE
+PFA_PSOC2:
+ .dw 240
+; ( -- addr ) System Constant
+; R( -- )
+; PSC2 Interrupt Mask Register
+VE_PIM2:
+ .dw $ff04
+ .db "PIM2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIM2
+XT_PIM2:
+ .dw PFA_DOVARIABLE
+PFA_PIM2:
+ .dw 165
+; ( -- addr ) System Constant
+; R( -- )
+; PSC2 Interrupt Flag Register
+VE_PIFR2:
+ .dw $ff05
+ .db "PIFR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIFR2
+XT_PIFR2:
+ .dw PFA_DOVARIABLE
+PFA_PIFR2:
+ .dw 164
+
+.endif
diff --git a/amforth-6.5/avr8/devices/at90pwm216/device.py b/amforth-6.5/avr8/devices/at90pwm216/device.py
new file mode 100644
index 0000000..af38406
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90pwm216/device.py
@@ -0,0 +1,448 @@
+# Generated Automatically
+
+# Partname AT90PWM216
+
+MCUREGS = {
+# Interrupt Vectors
+ 'PSC2_CAPTAddr' : '#2', # PSC2 Capture Event
+ 'PSC2_ECAddr' : '#4', # PSC2 End Cycle
+ 'PSC1_CAPTAddr' : '#6', # PSC1 Capture Event
+ 'PSC1_ECAddr' : '#8', # PSC1 End Cycle
+ 'PSC0_CAPTAddr' : '#10', # PSC0 Capture Event
+ 'PSC0_ECAddr' : '#12', # PSC0 End Cycle
+ 'ANALOG_COMP_0Addr' : '#14', # Analog Comparator 0
+ 'ANALOG_COMP_1Addr' : '#16', # Analog Comparator 1
+ 'ANALOG_COMP_2Addr' : '#18', # Analog Comparator 2
+ 'INT0Addr' : '#20', # External Interrupt Request 0
+ 'TIMER1_CAPTAddr' : '#22', # Timer/Counter1 Capture Event
+ 'TIMER1_COMPAAddr' : '#24', # Timer/Counter1 Compare Match A
+ 'TIMER1_COMPBAddr' : '#26', # Timer/Counter Compare Match B
+ 'RESERVED15Addr' : '#28', #
+ 'TIMER1_OVFAddr' : '#30', # Timer/Counter1 Overflow
+ 'TIMER0_COMP_AAddr' : '#32', # Timer/Counter0 Compare Match A
+ 'TIMER0_OVFAddr' : '#34', # Timer/Counter0 Overflow
+ 'ADCAddr' : '#36', # ADC Conversion Complete
+ 'INT1Addr' : '#38', # External Interrupt Request 1
+ 'SPI_STCAddr' : '#40', # SPI Serial Transfer Complete
+ 'USART_RXAddr' : '#42', # USART, Rx Complete
+ 'USART_UDREAddr' : '#44', # USART Data Register Empty
+ 'USART_TXAddr' : '#46', # USART, Tx Complete
+ 'INT2Addr' : '#48', # External Interrupt Request 2
+ 'WDTAddr' : '#50', # Watchdog Timeout Interrupt
+ 'EE_READYAddr' : '#52', # EEPROM Ready
+ 'TIMER0_COMPBAddr' : '#54', # Timer Counter 0 Compare Match B
+ 'INT3Addr' : '#56', # External Interrupt Request 3
+ 'RESERVED30Addr' : '#58', #
+ 'RESERVED31Addr' : '#60', #
+ 'SPM_READYAddr' : '#62', # Store Program Memory Read
+
+# Module PORTB
+ 'PORTB' : '$25', # Port B Data Register
+ 'DDRB' : '$24', # Port B Data Direction Register
+ 'PINB' : '$23', # Port B Input Pins
+
+# Module PORTD
+ 'PORTD' : '$2b', # Port D Data Register
+ 'DDRD' : '$2a', # Port D Data Direction Register
+ 'PIND' : '$29', # Port D Input Pins
+
+# Module BOOT_LOAD
+ 'SPMCSR' : '$57', # Store Program Memory Control R
+ 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
+ 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
+ 'SPMCSR_RWWSRE': '$10', # Read While Write section read
+ 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
+ 'SPMCSR_PGWRT': '$4', # Page Write
+ 'SPMCSR_PGERS': '$2', # Page Erase
+ 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
+
+# Module EUSART
+ 'EUDR' : '$ce', # EUSART I/O Data Register
+ 'EUCSRA' : '$c8', # EUSART Control and Status Regi
+ 'EUCSRA_UTxS': '$f0', # EUSART Control and Status Regi
+ 'EUCSRA_URxS': '$f', # EUSART Control and Status Regi
+ 'EUCSRB' : '$c9', # EUSART Control Register B
+ 'EUCSRB_EUSART': '$10', # EUSART Enable Bit
+ 'EUCSRB_EUSBS': '$8', # EUSBS Enable Bit
+ 'EUCSRB_EMCH': '$2', # Manchester Mode Bit
+ 'EUCSRB_BODR': '$1', # Order Bit
+ 'EUCSRC' : '$ca', # EUSART Status Register C
+ 'EUCSRC_FEM': '$8', # Frame Error Manchester Bit
+ 'EUCSRC_F1617': '$4', # F1617 Bit
+ 'EUCSRC_STP': '$3', # Stop Bits
+ 'MUBRRH' : '$cd', # Manchester Receiver Baud Rate
+ 'MUBRRH_MUBRR': '$ff', # Manchester Receiver Baud Rate
+ 'MUBRRL' : '$cc', # Manchester Receiver Baud Rate
+ 'MUBRRL_MUBRR': '$ff', # Manchester Receiver Baud Rate
+
+# Module ANALOG_COMPARATOR
+ 'AC0CON' : '$ad', # Analog Comparator 0 Control Re
+ 'AC0CON_AC0EN': '$80', # Analog Comparator 0 Enable Bit
+ 'AC0CON_AC0IE': '$40', # Analog Comparator 0 Interrupt
+ 'AC0CON_AC0IS': '$30', # Analog Comparator 0 Interrupt
+ 'AC0CON_AC0M': '$7', # Analog Comparator 0 Multiplexe
+ 'AC1CON' : '$ae', # Analog Comparator 1 Control Re
+ 'AC1CON_AC1EN': '$80', # Analog Comparator 1 Enable Bit
+ 'AC1CON_AC1IE': '$40', # Analog Comparator 1 Interrupt
+ 'AC1CON_AC1IS': '$30', # Analog Comparator 1 Interrupt
+ 'AC1CON_AC1ICE': '$8', # Analog Comparator 1 Interrupt
+ 'AC1CON_AC1M': '$7', # Analog Comparator 1 Multiplexe
+ 'AC2CON' : '$af', # Analog Comparator 2 Control Re
+ 'AC2CON_AC2EN': '$80', # Analog Comparator 2 Enable Bit
+ 'AC2CON_AC2IE': '$40', # Analog Comparator 2 Interrupt
+ 'AC2CON_AC2IS': '$30', # Analog Comparator 2 Interrupt
+ 'AC2CON_AC2M': '$7', # Analog Comparator 2 Multiplexe
+ 'ACSR' : '$50', # Analog Comparator Status Regis
+ 'ACSR_ACCKDIV': '$80', # Analog Comparator Clock Divide
+ 'ACSR_AC2IF': '$40', # Analog Comparator 2 Interrupt
+ 'ACSR_AC1IF': '$20', # Analog Comparator 1 Interrupt
+ 'ACSR_AC0IF': '$10', # Analog Comparator 0 Interrupt
+ 'ACSR_AC2O': '$4', # Analog Comparator 2 Output Bit
+ 'ACSR_AC1O': '$2', # Analog Comparator 1 Output Bit
+ 'ACSR_AC0O': '$1', # Analog Comparator 0 Output Bit
+
+# Module DA_CONVERTER
+ 'DACH' : '$ac', # DAC Data Register High Byte
+ 'DACH_DACH': '$ff', # DAC Data Register High Byte Bi
+ 'DACL' : '$ab', # DAC Data Register Low Byte
+ 'DACL_DACL': '$ff', # DAC Data Register Low Byte Bit
+ 'DACON' : '$aa', # DAC Control Register
+ 'DACON_DAATE': '$80', # DAC Auto Trigger Enable Bit
+ 'DACON_DATS': '$70', # DAC Trigger Selection Bits
+ 'DACON_DALA': '$4', # DAC Left Adjust
+ 'DACON_DAEN': '$1', # DAC Enable Bit
+
+# Module CPU
+ 'SREG' : '$5f', # Status Register
+ 'SREG_I': '$80', # Global Interrupt Enable
+ 'SREG_T': '$40', # Bit Copy Storage
+ 'SREG_H': '$20', # Half Carry Flag
+ 'SREG_S': '$10', # Sign Bit
+ 'SREG_V': '$8', # Two's Complement Overflow Flag
+ 'SREG_N': '$4', # Negative Flag
+ 'SREG_Z': '$2', # Zero Flag
+ 'SREG_C': '$1', # Carry Flag
+ 'SP' : '$5d', # Stack Pointer
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_SPIPS': '$80', # SPI Pin Select
+ 'MCUCR_PUD': '$10', # Pull-up disable
+ 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
+ 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
+ 'MCUSR_BORF': '$4', # Brown-out Reset Flag
+ 'MCUSR_EXTRF': '$2', # External Reset Flag
+ 'MCUSR_PORF': '$1', # Power-on reset flag
+ 'OSCCAL' : '$66', # Oscillator Calibration Value
+ 'CLKPR' : '$61', #
+ 'CLKPR_CLKPCE': '$80', #
+ 'CLKPR_CLKPS': '$f', #
+ 'SMCR' : '$53', # Sleep Mode Control Register
+ 'SMCR_SM': '$e', # Sleep Mode Select bits
+ 'SMCR_SE': '$1', # Sleep Enable
+ 'GPIOR3' : '$3b', # General Purpose IO Register 3
+ 'GPIOR3_GPIOR': '$ff', # General Purpose IO Register 3
+ 'GPIOR2' : '$3a', # General Purpose IO Register 2
+ 'GPIOR2_GPIOR': '$ff', # General Purpose IO Register 2
+ 'GPIOR1' : '$39', # General Purpose IO Register 1
+ 'GPIOR1_GPIOR': '$ff', # General Purpose IO Register 1
+ 'GPIOR0' : '$3e', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR07': '$80', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR06': '$40', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR05': '$20', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR04': '$10', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR03': '$8', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR02': '$4', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR01': '$2', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR00': '$1', # General Purpose IO Register 0
+ 'PLLCSR' : '$49', # PLL Control And Status Registe
+ 'PLLCSR_PLLF': '$4', # PLL Factor
+ 'PLLCSR_PLLE': '$2', # PLL Enable
+ 'PLLCSR_PLOCK': '$1', # PLL Lock Detector
+ 'PRR' : '$64', # Power Reduction Register
+ 'PRR_PRPSC': '$e0', # Power Reduction PSC2
+ 'PRR_PRTIM1': '$10', # Power Reduction Timer/Counter1
+ 'PRR_PRTIM0': '$8', # Power Reduction Timer/Counter0
+ 'PRR_PRSPI': '$4', # Power Reduction Serial Periphe
+ 'PRR_PRUSART0': '$2', # Power Reduction USART
+ 'PRR_PRADC': '$1', # Power Reduction ADC
+
+# Module PORTE
+ 'PORTE' : '$2e', # Port E Data Register
+ 'DDRE' : '$2d', # Port E Data Direction Register
+ 'PINE' : '$2c', # Port E Input Pins
+
+# Module TIMER_COUNTER_0
+ 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
+ 'TIMSK0_OCIE0B': '$4', # Timer/Counter0 Output Compare
+ 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
+ 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
+ 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
+ 'TIFR0_OCF0B': '$4', # Timer/Counter0 Output Compare
+ 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
+ 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
+ 'TCCR0A' : '$44', # Timer/Counter Control Registe
+ 'TCCR0A_COM0A': '$c0', # Compare Output Mode, Phase Cor
+ 'TCCR0A_COM0B': '$30', # Compare Output Mode, Fast PWm
+ 'TCCR0A_WGM0': '$3', # Waveform Generation Mode
+ 'TCCR0B' : '$45', # Timer/Counter Control Register
+ 'TCCR0B_FOC0A': '$80', # Force Output Compare A
+ 'TCCR0B_FOC0B': '$40', # Force Output Compare B
+ 'TCCR0B_WGM02': '$8', #
+ 'TCCR0B_CS0': '$7', # Clock Select
+ 'TCNT0' : '$46', # Timer/Counter0
+ 'OCR0A' : '$47', # Timer/Counter0 Output Compare
+ 'OCR0B' : '$48', # Timer/Counter0 Output Compare
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_ICPSEL1': '$40', # Timer1 Input Capture Selection
+ 'GTCCR_PSR10': '$1', # Prescaler Reset Timer/Counter1
+
+# Module TIMER_COUNTER_1
+ 'TIMSK1' : '$6f', # Timer/Counter Interrupt Mask R
+ 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
+ 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output CompareB
+ 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output CompareA
+ 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
+ 'TIFR1' : '$36', # Timer/Counter Interrupt Flag r
+ 'TIFR1_ICF1': '$20', # Input Capture Flag 1
+ 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
+ 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
+ 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
+ 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
+ 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
+ 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
+ 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
+ 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
+ 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
+ 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
+ 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
+ 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
+ 'TCCR1C' : '$82', # Timer/Counter1 Control Registe
+ 'TCCR1C_FOC1A': '$80', #
+ 'TCCR1C_FOC1B': '$40', #
+ 'TCNT1' : '$84', # Timer/Counter1 Bytes
+ 'OCR1A' : '$88', # Timer/Counter1 Output Compare
+ 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
+ 'ICR1' : '$86', # Timer/Counter1 Input Capture R
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSRSYNC': '$1', # Prescaler Reset Timer/Counter1
+
+# Module AD_CONVERTER
+ 'ADMUX' : '$7c', # The ADC multiplexer Selection
+ 'ADMUX_REFS': '$c0', # Reference Selection Bits
+ 'ADMUX_ADLAR': '$20', # Left Adjust Result
+ 'ADMUX_MUX': '$f', # Analog Channel and Gain Select
+ 'ADCSRA' : '$7a', # The ADC Control and Status reg
+ 'ADCSRA_ADEN': '$80', # ADC Enable
+ 'ADCSRA_ADSC': '$40', # ADC Start Conversion
+ 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
+ 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
+ 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
+ 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
+ 'ADC' : '$78', # ADC Data Register Bytes
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'DIDR0' : '$7e', # Digital Input Disable Register
+ 'DIDR1' : '$7f', # Digital Input Disable Register
+ 'DIDR1_ACMP0D': '$20', #
+ 'DIDR1_AMP0PD': '$10', #
+ 'DIDR1_AMP0ND': '$8', #
+ 'DIDR1_ADC10D': '$4', #
+ 'DIDR1_ADC9D': '$2', #
+ 'DIDR1_ADC8D': '$1', #
+ 'AMP0CSR' : '$76', #
+ 'AMP0CSR_AMP0EN': '$80', #
+ 'AMP0CSR_AMP0IS': '$40', #
+ 'AMP0CSR_AMP0G': '$30', #
+ 'AMP0CSR_AMP0TS': '$3', #
+ 'AMP1CSR' : '$77', #
+ 'AMP1CSR_AMP1EN': '$80', #
+ 'AMP1CSR_AMP1IS': '$40', #
+ 'AMP1CSR_AMP1G': '$30', #
+ 'AMP1CSR_AMP1TS': '$3', #
+
+# Module USART
+ 'UDR' : '$c6', # USART I/O Data Register
+ 'UCSRA' : '$c0', # USART Control and Status regis
+ 'UCSRA_RXC': '$80', # USART Receive Complete
+ 'UCSRA_TXC': '$40', # USART Transmitt Complete
+ 'UCSRA_UDRE': '$20', # USART Data Register Empty
+ 'UCSRA_FE': '$10', # Framing Error
+ 'UCSRA_DOR': '$8', # Data Overrun
+ 'UCSRA_UPE': '$4', # USART Parity Error
+ 'UCSRA_U2X': '$2', # Double USART Transmission Bit
+ 'UCSRA_MPCM': '$1', # Multi-processor Communication
+ 'UCSRB' : '$c1', # USART Control an Status regist
+ 'UCSRB_RXCIE': '$80', # RX Complete Interrupt Enable
+ 'UCSRB_TXCIE': '$40', # TX Complete Interrupt Enable
+ 'UCSRB_UDRIE': '$20', # USART Data Register Empty Inte
+ 'UCSRB_RXEN': '$10', # Receiver Enable
+ 'UCSRB_TXEN': '$8', # Transmitter Enable
+ 'UCSRB_UCSZ2': '$4', # Character Size
+ 'UCSRB_RXB8': '$2', # Receive Data Bit 8
+ 'UCSRB_TXB8': '$1', # Transmit Data Bit 8
+ 'UCSRC' : '$c2', # USART Control an Status regist
+ 'UCSRC_UMSEL0': '$40', # USART Mode Select
+ 'UCSRC_UPM': '$30', # Parity Mode Bits
+ 'UCSRC_USBS': '$8', # Stop Bit Select
+ 'UCSRC_UCSZ': '$6', # Character Size Bits
+ 'UCSRC_UCPOL': '$1', # Clock Polarity
+ 'UBRRH' : '$c5', # USART Baud Rate Register High
+ 'UBRRH_UBRR': '$f', # USART Baud Rate Register Bits
+ 'UBRRL' : '$c4', # USART Baud Rate Register Low B
+ 'UBRRL_UBRR': '$ff', # USART Baud Rate Register bits
+
+# Module SPI
+ 'SPCR' : '$4c', # SPI Control Register
+ 'SPCR_SPIE': '$80', # SPI Interrupt Enable
+ 'SPCR_SPE': '$40', # SPI Enable
+ 'SPCR_DORD': '$20', # Data Order
+ 'SPCR_MSTR': '$10', # Master/Slave Select
+ 'SPCR_CPOL': '$8', # Clock polarity
+ 'SPCR_CPHA': '$4', # Clock Phase
+ 'SPCR_SPR': '$3', # SPI Clock Rate Selects
+ 'SPSR' : '$4d', # SPI Status Register
+ 'SPSR_SPIF': '$80', # SPI Interrupt Flag
+ 'SPSR_WCOL': '$40', # Write Collision Flag
+ 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
+ 'SPDR' : '$4e', # SPI Data Register
+
+# Module WATCHDOG
+ 'WDTCSR' : '$60', # Watchdog Timer Control Registe
+ 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
+ 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
+ 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
+ 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
+ 'WDTCSR_WDE': '$8', # Watch Dog Enable
+
+# Module EXTERNAL_INTERRUPT
+ 'EICRA' : '$69', # External Interrupt Control Reg
+ 'EICRA_ISC2': '$30', # External Interrupt Sense Contr
+ 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
+ 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
+ 'EIMSK' : '$3d', # External Interrupt Mask Regist
+ 'EIMSK_INT': '$7', # External Interrupt Request 2 E
+ 'EIFR' : '$3c', # External Interrupt Flag Regist
+ 'EIFR_INTF': '$7', # External Interrupt Flags
+
+# Module EEPROM
+ 'EEAR' : '$41', # EEPROM Read/Write Access Byte
+ 'EEDR' : '$40', # EEPROM Data Register
+ 'EECR' : '$3f', # EEPROM Control Register
+ 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
+ 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
+ 'EECR_EEWE': '$2', # EEPROM Write Enable
+ 'EECR_EERE': '$1', # EEPROM Read Enable
+
+# Module PSC0
+ 'PICR0' : '$de', # PSC 0 Input Capture Register
+ 'PFRC0B' : '$dd', # PSC 0 Input B Control
+ 'PFRC0B_PCAE0B': '$80', # PSC 0 Capture Enable Input Par
+ 'PFRC0B_PISEL0B': '$40', # PSC 0 Input Select for Part B
+ 'PFRC0B_PELEV0B': '$20', # PSC 0 Edge Level Selector on I
+ 'PFRC0B_PFLTE0B': '$10', # PSC 0 Filter Enable on Input P
+ 'PFRC0B_PRFM0B': '$f', # PSC 0 Retrigger and Fault Mode
+ 'PFRC0A' : '$dc', # PSC 0 Input A Control
+ 'PFRC0A_PCAE0A': '$80', # PSC 0 Capture Enable Input Par
+ 'PFRC0A_PISEL0A': '$40', # PSC 0 Input Select for Part A
+ 'PFRC0A_PELEV0A': '$20', # PSC 0 Edge Level Selector on I
+ 'PFRC0A_PFLTE0A': '$10', # PSC 0 Filter Enable on Input P
+ 'PFRC0A_PRFM0A': '$f', # PSC 0 Retrigger and Fault Mode
+ 'PCTL0' : '$db', # PSC 0 Control Register
+ 'PCTL0_PPRE0': '$c0', # PSC 0 Prescaler Selects
+ 'PCTL0_PBFM0': '$20', # PSC 0 Balance Flank Width Modu
+ 'PCTL0_PAOC0B': '$10', # PSC 0 Asynchronous Output Cont
+ 'PCTL0_PAOC0A': '$8', # PSC 0 Asynchronous Output Cont
+ 'PCTL0_PARUN0': '$4', # PSC0 Auto Run
+ 'PCTL0_PCCYC0': '$2', # PSC0 Complete Cycle
+ 'PCTL0_PRUN0': '$1', # PSC 0 Run
+ 'PCNF0' : '$da', # PSC 0 Configuration Register
+ 'PCNF0_PFIFTY0': '$80', # PSC 0 Fifty
+ 'PCNF0_PALOCK0': '$40', # PSC 0 Autolock
+ 'PCNF0_PLOCK0': '$20', # PSC 0 Lock
+ 'PCNF0_PMODE0': '$18', # PSC 0 Mode
+ 'PCNF0_POP0': '$4', # PSC 0 Output Polarity
+ 'PCNF0_PCLKSEL0': '$2', # PSC 0 Input Clock Select
+ 'OCR0RB' : '$d8', # Output Compare RB Register
+ 'OCR0SB' : '$d6', # Output Compare SB Register
+ 'OCR0RA' : '$d4', # Output Compare RA Register
+ 'OCR0SA' : '$d2', # Output Compare SA Register
+ 'PSOC0' : '$d0', # PSC0 Synchro and Output Config
+ 'PSOC0_PSYNC0': '$30', # Synchronization Out for ADC Se
+ 'PSOC0_POEN0B': '$4', # PSCOUT01 Output Enable
+ 'PSOC0_POEN0A': '$1', # PSCOUT00 Output Enable
+ 'PIM0' : '$a1', # PSC0 Interrupt Mask Register
+ 'PIM0_PSEIE0': '$20', # PSC 0 Synchro Error Interrupt
+ 'PIM0_PEVE0B': '$10', # External Event B Interrupt Ena
+ 'PIM0_PEVE0A': '$8', # External Event A Interrupt Ena
+ 'PIM0_PEOPE0': '$1', # End of Cycle Interrupt Enable
+ 'PIFR0' : '$a0', # PSC0 Interrupt Flag Register
+ 'PIFR0_POAC0B': '$80', # PSC 0 Output A Activity
+ 'PIFR0_POAC0A': '$40', # PSC 0 Output A Activity
+ 'PIFR0_PSEI0': '$20', # PSC 0 Synchro Error Interrupt
+ 'PIFR0_PEV0B': '$10', # External Event B Interrupt
+ 'PIFR0_PEV0A': '$8', # External Event A Interrupt
+ 'PIFR0_PRN0': '$6', # Ramp Number
+ 'PIFR0_PEOP0': '$1', # End of PSC0 Interrupt
+
+# Module PSC2
+ 'PICR2' : '$fe', # PSC 2 Input Capture Register
+ 'PFRC2B' : '$fd', # PSC 2 Input B Control
+ 'PFRC2B_PCAE2B': '$80', # PSC 2 Capture Enable Input Par
+ 'PFRC2B_PISEL2B': '$40', # PSC 2 Input Select for Part B
+ 'PFRC2B_PELEV2B': '$20', # PSC 2 Edge Level Selector on I
+ 'PFRC2B_PFLTE2B': '$10', # PSC 2 Filter Enable on Input P
+ 'PFRC2B_PRFM2B': '$f', # PSC 2 Retrigger and Fault Mode
+ 'PFRC2A' : '$fc', # PSC 2 Input B Control
+ 'PFRC2A_PCAE2A': '$80', # PSC 2 Capture Enable Input Par
+ 'PFRC2A_PISEL2A': '$40', # PSC 2 Input Select for Part A
+ 'PFRC2A_PELEV2A': '$20', # PSC 2 Edge Level Selector on I
+ 'PFRC2A_PFLTE2A': '$10', # PSC 2 Filter Enable on Input P
+ 'PFRC2A_PRFM2A': '$f', # PSC 2 Retrigger and Fault Mode
+ 'PCTL2' : '$fb', # PSC 2 Control Register
+ 'PCTL2_PPRE2': '$c0', # PSC 2 Prescaler Selects
+ 'PCTL2_PBFM2': '$20', # Balance Flank Width Modulation
+ 'PCTL2_PAOC2B': '$10', # PSC 2 Asynchronous Output Cont
+ 'PCTL2_PAOC2A': '$8', # PSC 2 Asynchronous Output Cont
+ 'PCTL2_PARUN2': '$4', # PSC2 Auto Run
+ 'PCTL2_PCCYC2': '$2', # PSC2 Complete Cycle
+ 'PCTL2_PRUN2': '$1', # PSC 2 Run
+ 'PCNF2' : '$fa', # PSC 2 Configuration Register
+ 'PCNF2_PFIFTY2': '$80', # PSC 2 Fifty
+ 'PCNF2_PALOCK2': '$40', # PSC 2 Autolock
+ 'PCNF2_PLOCK2': '$20', # PSC 2 Lock
+ 'PCNF2_PMODE2': '$18', # PSC 2 Mode
+ 'PCNF2_POP2': '$4', # PSC 2 Output Polarity
+ 'PCNF2_PCLKSEL2': '$2', # PSC 2 Input Clock Select
+ 'PCNF2_POME2': '$1', # PSC 2 Output Matrix Enable
+ 'OCR2RB' : '$f8', # Output Compare RB Register
+ 'OCR2SB' : '$f6', # Output Compare SB Register
+ 'OCR2RA' : '$f4', # Output Compare RA Register
+ 'OCR2SA' : '$f2', # Output Compare SA Register
+ 'POM2' : '$f1', # PSC 2 Output Matrix
+ 'POM2_POMV2B': '$f0', # Output Matrix Output B Ramps
+ 'POM2_POMV2A': '$f', # Output Matrix Output A Ramps
+ 'PSOC2' : '$f0', # PSC2 Synchro and Output Config
+ 'PSOC2_POS2': '$c0', # PSC 2 Output 23 Select
+ 'PSOC2_PSYNC2_': '$30', # Synchronization Out for ADC Se
+ 'PSOC2_POEN2D': '$8', # PSCOUT23 Output Enable
+ 'PSOC2_POEN2B': '$4', # PSCOUT21 Output Enable
+ 'PSOC2_POEN2C': '$2', # PSCOUT22 Output Enable
+ 'PSOC2_POEN2A': '$1', # PSCOUT20 Output Enable
+ 'PIM2' : '$a5', # PSC2 Interrupt Mask Register
+ 'PIM2_PSEIE2': '$20', # PSC 2 Synchro Error Interrupt
+ 'PIM2_PEVE2B': '$10', # External Event B Interrupt Ena
+ 'PIM2_PEVE2A': '$8', # External Event A Interrupt Ena
+ 'PIM2_PEOPE2': '$1', # End of Cycle Interrupt Enable
+ 'PIFR2' : '$a4', # PSC2 Interrupt Flag Register
+ 'PIFR2_POAC2B': '$80', # PSC 2 Output A Activity
+ 'PIFR2_POAC2A': '$40', # PSC 2 Output A Activity
+ 'PIFR2_PSEI2': '$20', # PSC 2 Synchro Error Interrupt
+ 'PIFR2_PEV2B': '$10', # External Event B Interrupt
+ 'PIFR2_PEV2A': '$8', # External Event A Interrupt
+ 'PIFR2_PRN2': '$6', # Ramp Number
+ 'PIFR2_PEOP2': '$1', # End of PSC2 Interrupt
+
+ '__amforth_dummy':'0'
+}
diff --git a/amforth-6.5/avr8/devices/at90pwm216/words/no-jtag.asm b/amforth-6.5/avr8/devices/at90pwm216/words/no-jtag.asm
new file mode 100644
index 0000000..352a4bb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90pwm216/words/no-jtag.asm
@@ -0,0 +1,14 @@
+; ( -- )
+; ( -- )
+; MCU
+; disable jtag at runtime
+VE_NOJTAG:
+ .dw $FF05
+ .db "-jtag",0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOJTAG
+XT_NOJTAG:
+ .dw PFA_NOJTAG
+PFA_NOJTAG:
+
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/at90pwm216/words/no-wdt.asm b/amforth-6.5/avr8/devices/at90pwm216/words/no-wdt.asm
new file mode 100644
index 0000000..ff6ddd1
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90pwm216/words/no-wdt.asm
@@ -0,0 +1,34 @@
+; ( -- )
+; MCU
+; disable watch dog timer at runtime
+VE_NOWDT:
+ .dw $ff04
+ .db "-wdt"
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOWDT
+XT_NOWDT:
+ .dw PFA_NOWDT
+PFA_NOWDT:
+
+ in temp1,SREG
+ push temp1
+ ; Turn always off global interrupt.
+ cli
+ ; Reset Watchdog Timer
+ wdr
+ ; Clear WDRF in MCUSR
+ in temp1, MCUSR
+ andi temp1, (0xff & (0<<WDRF))
+ out MCUSR, temp1
+ ; Write logical one to WDCE and WDE
+ ; Keep old prescaler setting to prevent unintentional time-out
+ in_ temp1, WDTCSR
+ ori temp1, (1<<WDCE) | (1<<WDE)
+ out_ WDTCSR, temp1
+ ; Turn off WDT
+ ldi temp1, (0<<WDE)
+ out_ WDTCSR, temp1
+ ; restore status register
+ pop temp1
+ out SREG,temp1
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/at90pwm216/words/sleep.asm b/amforth-6.5/avr8/devices/at90pwm216/words/sleep.asm
new file mode 100644
index 0000000..256249c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90pwm216/words/sleep.asm
@@ -0,0 +1,19 @@
+; ( mode -- )
+; MCU
+; put the controller into the specified sleep mode
+VE_SLEEP:
+ .dw $ff05
+ .db "sleep", 0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_SLEEP
+XT_SLEEP:
+ .dw PFA_SLEEP
+PFA_SLEEP:
+ andi tosl, 7 ; leave only legal mode bits
+ lsl tosl ; move to correct location (bits 3-1)
+ ori tosl, 1 ; set the SE bit
+ out_ SMCR, tosl ; set the sleep config
+ sleep ; nighty-night
+ out_ SMCR, zerol ; 0 protects against accidental sleeps
+ loadtos ; pop argument from stack
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/at90pwm2b/at90pwm2b.frt b/amforth-6.5/avr8/devices/at90pwm2b/at90pwm2b.frt
new file mode 100644
index 0000000..30d6e54
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90pwm2b/at90pwm2b.frt
@@ -0,0 +1,423 @@
+\ Partname: AT90PWM2B
+\ generated automatically
+
+\ PORTB
+&37 constant PORTB \ Port B Data Register
+&36 constant DDRB \ Port B Data Direction Register
+&35 constant PINB \ Port B Input Pins
+\ PORTD
+&43 constant PORTD \ Port D Data Register
+&42 constant DDRD \ Port D Data Direction Register
+&41 constant PIND \ Port D Input Pins
+\ BOOT_LOAD
+&87 constant SPMCSR \ Store Program Memory Control Register
+ $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
+ $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
+ $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
+ $04 constant SPMCSR_PGWRT \ Page Write
+ $02 constant SPMCSR_PGERS \ Page Erase
+ $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
+\ EUSART
+&206 constant EUDR \ EUSART I/O Data Register
+&200 constant EUCSRA \ EUSART Control and Status Register A
+ $F0 constant EUCSRA_UTxS \ EUSART Control and Status Register A Bits
+ $0F constant EUCSRA_URxS \ EUSART Control and Status Register A Bits
+&201 constant EUCSRB \ EUSART Control Register B
+ $10 constant EUCSRB_EUSART \ EUSART Enable Bit
+ $08 constant EUCSRB_EUSBS \ EUSBS Enable Bit
+ $02 constant EUCSRB_EMCH \ Manchester Mode Bit
+ $01 constant EUCSRB_BODR \ Order Bit
+&202 constant EUCSRC \ EUSART Status Register C
+ $08 constant EUCSRC_FEM \ Frame Error Manchester Bit
+ $04 constant EUCSRC_F1617 \ F1617 Bit
+ $03 constant EUCSRC_STP \ Stop Bits
+&205 constant MUBRRH \ Manchester Receiver Baud Rate Register High Byte
+ $FF constant MUBRRH_MUBRR \ Manchester Receiver Baud Rate Register Bits
+&204 constant MUBRRL \ Manchester Receiver Baud Rate Register Low Byte
+ $FF constant MUBRRL_MUBRR \ Manchester Receiver Baud Rate Register Bits
+\ ANALOG_COMPARATOR
+&173 constant AC0CON \ Analog Comparator 0 Control Register
+ $80 constant AC0CON_AC0EN \ Analog Comparator 0 Enable Bit
+ $40 constant AC0CON_AC0IE \ Analog Comparator 0 Interrupt Enable Bit
+ $30 constant AC0CON_AC0IS \ Analog Comparator 0 Interrupt Select Bit
+ $07 constant AC0CON_AC0M \ Analog Comparator 0 Multiplexer Register
+&174 constant AC1CON \ Analog Comparator 1 Control Register
+ $80 constant AC1CON_AC1EN \ Analog Comparator 1 Enable Bit
+ $40 constant AC1CON_AC1IE \ Analog Comparator 1 Interrupt Enable Bit
+ $30 constant AC1CON_AC1IS \ Analog Comparator 1 Interrupt Select Bit
+ $08 constant AC1CON_AC1ICE \ Analog Comparator 1 Interrupt Capture Enable Bit
+ $07 constant AC1CON_AC1M \ Analog Comparator 1 Multiplexer Register
+&175 constant AC2CON \ Analog Comparator 2 Control Register
+ $80 constant AC2CON_AC2EN \ Analog Comparator 2 Enable Bit
+ $40 constant AC2CON_AC2IE \ Analog Comparator 2 Interrupt Enable Bit
+ $30 constant AC2CON_AC2IS \ Analog Comparator 2 Interrupt Select Bit
+ $07 constant AC2CON_AC2M \ Analog Comparator 2 Multiplexer Register
+&80 constant ACSR \ Analog Comparator Status Register
+ $80 constant ACSR_ACCKDIV \ Analog Comparator Clock Divider
+ $40 constant ACSR_AC2IF \ Analog Comparator 2 Interrupt Flag Bit
+ $20 constant ACSR_AC1IF \ Analog Comparator 1 Interrupt Flag Bit
+ $10 constant ACSR_AC0IF \ Analog Comparator 0 Interrupt Flag Bit
+ $04 constant ACSR_AC2O \ Analog Comparator 2 Output Bit
+ $02 constant ACSR_AC1O \ Analog Comparator 1 Output Bit
+ $01 constant ACSR_AC0O \ Analog Comparator 0 Output Bit
+\ DA_CONVERTER
+&172 constant DACH \ DAC Data Register High Byte
+ $FF constant DACH_DACH \ DAC Data Register High Byte Bits
+&171 constant DACL \ DAC Data Register Low Byte
+ $FF constant DACL_DACL \ DAC Data Register Low Byte Bits
+&170 constant DACON \ DAC Control Register
+ $80 constant DACON_DAATE \ DAC Auto Trigger Enable Bit
+ $70 constant DACON_DATS \ DAC Trigger Selection Bits
+ $04 constant DACON_DALA \ DAC Left Adjust
+ $01 constant DACON_DAEN \ DAC Enable Bit
+\ CPU
+&95 constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ $08 constant SREG_V \ Two's Complement Overflow Flag
+ $04 constant SREG_N \ Negative Flag
+ $02 constant SREG_Z \ Zero Flag
+ $01 constant SREG_C \ Carry Flag
+&93 constant SP \ Stack Pointer
+&85 constant MCUCR \ MCU Control Register
+ $80 constant MCUCR_SPIPS \ SPI Pin Select
+ $10 constant MCUCR_PUD \ Pull-up disable
+ $02 constant MCUCR_IVSEL \ Interrupt Vector Select
+ $01 constant MCUCR_IVCE \ Interrupt Vector Change Enable
+&84 constant MCUSR \ MCU Status Register
+ $08 constant MCUSR_WDRF \ Watchdog Reset Flag
+ $04 constant MCUSR_BORF \ Brown-out Reset Flag
+ $02 constant MCUSR_EXTRF \ External Reset Flag
+ $01 constant MCUSR_PORF \ Power-on reset flag
+&102 constant OSCCAL \ Oscillator Calibration Value
+&97 constant CLKPR \
+ $80 constant CLKPR_CLKPCE \
+ $0F constant CLKPR_CLKPS \
+&83 constant SMCR \ Sleep Mode Control Register
+ $0E constant SMCR_SM \ Sleep Mode Select bits
+ $01 constant SMCR_SE \ Sleep Enable
+&59 constant GPIOR3 \ General Purpose IO Register 3
+ $FF constant GPIOR3_GPIOR \ General Purpose IO Register 3 bis
+&58 constant GPIOR2 \ General Purpose IO Register 2
+ $FF constant GPIOR2_GPIOR \ General Purpose IO Register 2 bis
+&57 constant GPIOR1 \ General Purpose IO Register 1
+ $FF constant GPIOR1_GPIOR \ General Purpose IO Register 1 bis
+&62 constant GPIOR0 \ General Purpose IO Register 0
+ $80 constant GPIOR0_GPIOR07 \ General Purpose IO Register 0 bit 7
+ $40 constant GPIOR0_GPIOR06 \ General Purpose IO Register 0 bit 6
+ $20 constant GPIOR0_GPIOR05 \ General Purpose IO Register 0 bit 5
+ $10 constant GPIOR0_GPIOR04 \ General Purpose IO Register 0 bit 4
+ $08 constant GPIOR0_GPIOR03 \ General Purpose IO Register 0 bit 3
+ $04 constant GPIOR0_GPIOR02 \ General Purpose IO Register 0 bit 2
+ $02 constant GPIOR0_GPIOR01 \ General Purpose IO Register 0 bit 1
+ $01 constant GPIOR0_GPIOR00 \ General Purpose IO Register 0 bit 0
+&73 constant PLLCSR \ PLL Control And Status Register
+ $04 constant PLLCSR_PLLF \ PLL Factor
+ $02 constant PLLCSR_PLLE \ PLL Enable
+ $01 constant PLLCSR_PLOCK \ PLL Lock Detector
+&100 constant PRR \ Power Reduction Register
+ $E0 constant PRR_PRPSC \ Power Reduction PSC2
+ $10 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
+ $08 constant PRR_PRTIM0 \ Power Reduction Timer/Counter0
+ $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
+ $02 constant PRR_PRUSART0 \ Power Reduction USART
+ $01 constant PRR_PRADC \ Power Reduction ADC
+\ PORTE
+&46 constant PORTE \ Port E Data Register
+&45 constant DDRE \ Port E Data Direction Register
+&44 constant PINE \ Port E Input Pins
+\ TIMER_COUNTER_0
+&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
+ $04 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare Match B Interrupt Enable
+ $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match A Interrupt Enable
+ $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
+&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
+ $04 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare Flag 0B
+ $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0A
+ $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
+&68 constant TCCR0A \ Timer/Counter Control Register A
+ $C0 constant TCCR0A_COM0A \ Compare Output Mode, Phase Correct PWM Mode
+ $30 constant TCCR0A_COM0B \ Compare Output Mode, Fast PWm
+ $03 constant TCCR0A_WGM0 \ Waveform Generation Mode
+&69 constant TCCR0B \ Timer/Counter Control Register B
+ $80 constant TCCR0B_FOC0A \ Force Output Compare A
+ $40 constant TCCR0B_FOC0B \ Force Output Compare B
+ $08 constant TCCR0B_WGM02 \
+ $07 constant TCCR0B_CS0 \ Clock Select
+&70 constant TCNT0 \ Timer/Counter0
+&71 constant OCR0A \ Timer/Counter0 Output Compare Register
+&72 constant OCR0B \ Timer/Counter0 Output Compare Register
+&67 constant GTCCR \ General Timer/Counter Control Register
+ $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
+ $40 constant GTCCR_ICPSEL1 \ Timer1 Input Capture Selection Bit
+ $01 constant GTCCR_PSR10 \ Prescaler Reset Timer/Counter1 and Timer/Counter0
+\ TIMER_COUNTER_1
+&111 constant TIMSK1 \ Timer/Counter Interrupt Mask Register
+ $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
+ $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output CompareB Match Interrupt Enable
+ $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output CompareA Match Interrupt Enable
+ $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
+&54 constant TIFR1 \ Timer/Counter Interrupt Flag register
+ $20 constant TIFR1_ICF1 \ Input Capture Flag 1
+ $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
+ $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
+ $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
+&128 constant TCCR1A \ Timer/Counter1 Control Register A
+ $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
+ $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
+ $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
+&129 constant TCCR1B \ Timer/Counter1 Control Register B
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
+ $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
+&130 constant TCCR1C \ Timer/Counter1 Control Register C
+ $80 constant TCCR1C_FOC1A \
+ $40 constant TCCR1C_FOC1B \
+&132 constant TCNT1 \ Timer/Counter1 Bytes
+&136 constant OCR1A \ Timer/Counter1 Output Compare Register Bytes
+&138 constant OCR1B \ Timer/Counter1 Output Compare Register Bytes
+&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
+\ AD_CONVERTER
+&124 constant ADMUX \ The ADC multiplexer Selection Register
+ $C0 constant ADMUX_REFS \ Reference Selection Bits
+ $20 constant ADMUX_ADLAR \ Left Adjust Result
+ $0F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
+&122 constant ADCSRA \ The ADC Control and Status register
+ $80 constant ADCSRA_ADEN \ ADC Enable
+ $40 constant ADCSRA_ADSC \ ADC Start Conversion
+ $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
+ $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
+ $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
+ $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
+&120 constant ADC \ ADC Data Register Bytes
+&123 constant ADCSRB \ ADC Control and Status Register B
+&126 constant DIDR0 \ Digital Input Disable Register 0
+&127 constant DIDR1 \ Digital Input Disable Register 0
+ $20 constant DIDR1_ACMP0D \
+ $10 constant DIDR1_AMP0PD \
+ $08 constant DIDR1_AMP0ND \
+ $04 constant DIDR1_ADC10D \
+ $02 constant DIDR1_ADC9D \
+ $01 constant DIDR1_ADC8D \
+&118 constant AMP0CSR \
+ $80 constant AMP0CSR_AMP0EN \
+ $40 constant AMP0CSR_AMP0IS \
+ $30 constant AMP0CSR_AMP0G \
+ $03 constant AMP0CSR_AMP0TS \
+&119 constant AMP1CSR \
+ $80 constant AMP1CSR_AMP1EN \
+ $40 constant AMP1CSR_AMP1IS \
+ $30 constant AMP1CSR_AMP1G \
+ $03 constant AMP1CSR_AMP1TS \
+\ USART
+&198 constant UDR \ USART I/O Data Register
+&192 constant UCSRA \ USART Control and Status register A
+ $80 constant UCSRA_RXC \ USART Receive Complete
+ $40 constant UCSRA_TXC \ USART Transmitt Complete
+ $20 constant UCSRA_UDRE \ USART Data Register Empty
+ $10 constant UCSRA_FE \ Framing Error
+ $08 constant UCSRA_DOR \ Data Overrun
+ $04 constant UCSRA_UPE \ USART Parity Error
+ $02 constant UCSRA_U2X \ Double USART Transmission Bit
+ $01 constant UCSRA_MPCM \ Multi-processor Communication Mode
+&193 constant UCSRB \ USART Control an Status register B
+ $80 constant UCSRB_RXCIE \ RX Complete Interrupt Enable
+ $40 constant UCSRB_TXCIE \ TX Complete Interrupt Enable
+ $20 constant UCSRB_UDRIE \ USART Data Register Empty Interrupt Enable
+ $10 constant UCSRB_RXEN \ Receiver Enable
+ $08 constant UCSRB_TXEN \ Transmitter Enable
+ $04 constant UCSRB_UCSZ2 \ Character Size
+ $02 constant UCSRB_RXB8 \ Receive Data Bit 8
+ $01 constant UCSRB_TXB8 \ Transmit Data Bit 8
+&194 constant UCSRC \ USART Control an Status register C
+ $40 constant UCSRC_UMSEL0 \ USART Mode Select
+ $30 constant UCSRC_UPM \ Parity Mode Bits
+ $08 constant UCSRC_USBS \ Stop Bit Select
+ $06 constant UCSRC_UCSZ \ Character Size Bits
+ $01 constant UCSRC_UCPOL \ Clock Polarity
+&197 constant UBRRH \ USART Baud Rate Register High Byte
+ $0F constant UBRRH_UBRR \ USART Baud Rate Register Bits
+&196 constant UBRRL \ USART Baud Rate Register Low Byte
+ $FF constant UBRRL_UBRR \ USART Baud Rate Register bits
+\ SPI
+&76 constant SPCR \ SPI Control Register
+ $80 constant SPCR_SPIE \ SPI Interrupt Enable
+ $40 constant SPCR_SPE \ SPI Enable
+ $20 constant SPCR_DORD \ Data Order
+ $10 constant SPCR_MSTR \ Master/Slave Select
+ $08 constant SPCR_CPOL \ Clock polarity
+ $04 constant SPCR_CPHA \ Clock Phase
+ $03 constant SPCR_SPR \ SPI Clock Rate Selects
+&77 constant SPSR \ SPI Status Register
+ $80 constant SPSR_SPIF \ SPI Interrupt Flag
+ $40 constant SPSR_WCOL \ Write Collision Flag
+ $01 constant SPSR_SPI2X \ Double SPI Speed Bit
+&78 constant SPDR \ SPI Data Register
+\ WATCHDOG
+&96 constant WDTCSR \ Watchdog Timer Control Register
+ $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Flag
+ $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Enable
+ $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
+ $10 constant WDTCSR_WDCE \ Watchdog Change Enable
+ $08 constant WDTCSR_WDE \ Watch Dog Enable
+\ EXTERNAL_INTERRUPT
+&105 constant EICRA \ External Interrupt Control Register A
+ $30 constant EICRA_ISC2 \ External Interrupt Sense Control Bit
+ $0C constant EICRA_ISC1 \ External Interrupt Sense Control Bit
+ $03 constant EICRA_ISC0 \ External Interrupt Sense Control Bit
+&61 constant EIMSK \ External Interrupt Mask Register
+ $07 constant EIMSK_INT \ External Interrupt Request 2 Enable
+&60 constant EIFR \ External Interrupt Flag Register
+ $07 constant EIFR_INTF \ External Interrupt Flags
+\ EEPROM
+&65 constant EEAR \ EEPROM Read/Write Access Bytes
+&64 constant EEDR \ EEPROM Data Register
+&63 constant EECR \ EEPROM Control Register
+ $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
+ $04 constant EECR_EEMWE \ EEPROM Master Write Enable
+ $02 constant EECR_EEWE \ EEPROM Write Enable
+ $01 constant EECR_EERE \ EEPROM Read Enable
+\ PSC0
+&222 constant PICR0 \ PSC 0 Input Capture Register
+&221 constant PFRC0B \ PSC 0 Input B Control
+ $80 constant PFRC0B_PCAE0B \ PSC 0 Capture Enable Input Part B
+ $40 constant PFRC0B_PISEL0B \ PSC 0 Input Select for Part B
+ $20 constant PFRC0B_PELEV0B \ PSC 0 Edge Level Selector on Input Part B
+ $10 constant PFRC0B_PFLTE0B \ PSC 0 Filter Enable on Input Part B
+ $0F constant PFRC0B_PRFM0B \ PSC 0 Retrigger and Fault Mode for Part B
+&220 constant PFRC0A \ PSC 0 Input A Control
+ $80 constant PFRC0A_PCAE0A \ PSC 0 Capture Enable Input Part A
+ $40 constant PFRC0A_PISEL0A \ PSC 0 Input Select for Part A
+ $20 constant PFRC0A_PELEV0A \ PSC 0 Edge Level Selector on Input Part A
+ $10 constant PFRC0A_PFLTE0A \ PSC 0 Filter Enable on Input Part A
+ $0F constant PFRC0A_PRFM0A \ PSC 0 Retrigger and Fault Mode for Part A
+&219 constant PCTL0 \ PSC 0 Control Register
+ $C0 constant PCTL0_PPRE0 \ PSC 0 Prescaler Selects
+ $20 constant PCTL0_PBFM0 \ PSC 0 Balance Flank Width Modulation
+ $10 constant PCTL0_PAOC0B \ PSC 0 Asynchronous Output Control B
+ $08 constant PCTL0_PAOC0A \ PSC 0 Asynchronous Output Control A
+ $04 constant PCTL0_PARUN0 \ PSC0 Auto Run
+ $02 constant PCTL0_PCCYC0 \ PSC0 Complete Cycle
+ $01 constant PCTL0_PRUN0 \ PSC 0 Run
+&218 constant PCNF0 \ PSC 0 Configuration Register
+ $80 constant PCNF0_PFIFTY0 \ PSC 0 Fifty
+ $40 constant PCNF0_PALOCK0 \ PSC 0 Autolock
+ $20 constant PCNF0_PLOCK0 \ PSC 0 Lock
+ $18 constant PCNF0_PMODE0 \ PSC 0 Mode
+ $04 constant PCNF0_POP0 \ PSC 0 Output Polarity
+ $02 constant PCNF0_PCLKSEL0 \ PSC 0 Input Clock Select
+&216 constant OCR0RB \ Output Compare RB Register
+&214 constant OCR0SB \ Output Compare SB Register
+&212 constant OCR0RA \ Output Compare RA Register
+&210 constant OCR0SA \ Output Compare SA Register
+&208 constant PSOC0 \ PSC0 Synchro and Output Configuration
+ $30 constant PSOC0_PSYNC0 \ Synchronization Out for ADC Selection
+ $04 constant PSOC0_POEN0B \ PSCOUT01 Output Enable
+ $01 constant PSOC0_POEN0A \ PSCOUT00 Output Enable
+&161 constant PIM0 \ PSC0 Interrupt Mask Register
+ $20 constant PIM0_PSEIE0 \ PSC 0 Synchro Error Interrupt Enable
+ $10 constant PIM0_PEVE0B \ External Event B Interrupt Enable
+ $08 constant PIM0_PEVE0A \ External Event A Interrupt Enable
+ $01 constant PIM0_PEOPE0 \ End of Cycle Interrupt Enable
+&160 constant PIFR0 \ PSC0 Interrupt Flag Register
+ $80 constant PIFR0_POAC0B \ PSC 0 Output A Activity
+ $40 constant PIFR0_POAC0A \ PSC 0 Output A Activity
+ $20 constant PIFR0_PSEI0 \ PSC 0 Synchro Error Interrupt
+ $10 constant PIFR0_PEV0B \ External Event B Interrupt
+ $08 constant PIFR0_PEV0A \ External Event A Interrupt
+ $06 constant PIFR0_PRN0 \ Ramp Number
+ $01 constant PIFR0_PEOP0 \ End of PSC0 Interrupt
+\ PSC2
+&254 constant PICR2 \ PSC 2 Input Capture Register
+&253 constant PFRC2B \ PSC 2 Input B Control
+ $80 constant PFRC2B_PCAE2B \ PSC 2 Capture Enable Input Part B
+ $40 constant PFRC2B_PISEL2B \ PSC 2 Input Select for Part B
+ $20 constant PFRC2B_PELEV2B \ PSC 2 Edge Level Selector on Input Part B
+ $10 constant PFRC2B_PFLTE2B \ PSC 2 Filter Enable on Input Part B
+ $0F constant PFRC2B_PRFM2B \ PSC 2 Retrigger and Fault Mode for Part B
+&252 constant PFRC2A \ PSC 2 Input B Control
+ $80 constant PFRC2A_PCAE2A \ PSC 2 Capture Enable Input Part A
+ $40 constant PFRC2A_PISEL2A \ PSC 2 Input Select for Part A
+ $20 constant PFRC2A_PELEV2A \ PSC 2 Edge Level Selector on Input Part A
+ $10 constant PFRC2A_PFLTE2A \ PSC 2 Filter Enable on Input Part A
+ $0F constant PFRC2A_PRFM2A \ PSC 2 Retrigger and Fault Mode for Part A
+&251 constant PCTL2 \ PSC 2 Control Register
+ $C0 constant PCTL2_PPRE2 \ PSC 2 Prescaler Selects
+ $20 constant PCTL2_PBFM2 \ Balance Flank Width Modulation
+ $10 constant PCTL2_PAOC2B \ PSC 2 Asynchronous Output Control B
+ $08 constant PCTL2_PAOC2A \ PSC 2 Asynchronous Output Control A
+ $04 constant PCTL2_PARUN2 \ PSC2 Auto Run
+ $02 constant PCTL2_PCCYC2 \ PSC2 Complete Cycle
+ $01 constant PCTL2_PRUN2 \ PSC 2 Run
+&250 constant PCNF2 \ PSC 2 Configuration Register
+ $80 constant PCNF2_PFIFTY2 \ PSC 2 Fifty
+ $40 constant PCNF2_PALOCK2 \ PSC 2 Autolock
+ $20 constant PCNF2_PLOCK2 \ PSC 2 Lock
+ $18 constant PCNF2_PMODE2 \ PSC 2 Mode
+ $04 constant PCNF2_POP2 \ PSC 2 Output Polarity
+ $02 constant PCNF2_PCLKSEL2 \ PSC 2 Input Clock Select
+ $01 constant PCNF2_POME2 \ PSC 2 Output Matrix Enable
+&248 constant OCR2RB \ Output Compare RB Register
+&246 constant OCR2SB \ Output Compare SB Register
+&244 constant OCR2RA \ Output Compare RA Register
+&242 constant OCR2SA \ Output Compare SA Register
+&241 constant POM2 \ PSC 2 Output Matrix
+ $F0 constant POM2_POMV2B \ Output Matrix Output B Ramps
+ $0F constant POM2_POMV2A \ Output Matrix Output A Ramps
+&240 constant PSOC2 \ PSC2 Synchro and Output Configuration
+ $C0 constant PSOC2_POS2 \ PSC 2 Output 23 Select
+ $30 constant PSOC2_PSYNC2_ \ Synchronization Out for ADC Selection
+ $08 constant PSOC2_POEN2D \ PSCOUT23 Output Enable
+ $04 constant PSOC2_POEN2B \ PSCOUT21 Output Enable
+ $02 constant PSOC2_POEN2C \ PSCOUT22 Output Enable
+ $01 constant PSOC2_POEN2A \ PSCOUT20 Output Enable
+&165 constant PIM2 \ PSC2 Interrupt Mask Register
+ $20 constant PIM2_PSEIE2 \ PSC 2 Synchro Error Interrupt Enable
+ $10 constant PIM2_PEVE2B \ External Event B Interrupt Enable
+ $08 constant PIM2_PEVE2A \ External Event A Interrupt Enable
+ $01 constant PIM2_PEOPE2 \ End of Cycle Interrupt Enable
+&164 constant PIFR2 \ PSC2 Interrupt Flag Register
+ $80 constant PIFR2_POAC2B \ PSC 2 Output A Activity
+ $40 constant PIFR2_POAC2A \ PSC 2 Output A Activity
+ $20 constant PIFR2_PSEI2 \ PSC 2 Synchro Error Interrupt
+ $10 constant PIFR2_PEV2B \ External Event B Interrupt
+ $08 constant PIFR2_PEV2A \ External Event A Interrupt
+ $06 constant PIFR2_PRN2 \ Ramp Number
+ $01 constant PIFR2_PEOP2 \ End of PSC2 Interrupt
+
+\ Interrupts
+&1 constant PSC2_CAPTAddr \ PSC2 Capture Event
+&2 constant PSC2_ECAddr \ PSC2 End Cycle
+&3 constant PSC1_CAPTAddr \ PSC1 Capture Event
+&4 constant PSC1_ECAddr \ PSC1 End Cycle
+&5 constant PSC0_CAPTAddr \ PSC0 Capture Event
+&6 constant PSC0_ECAddr \ PSC0 End Cycle
+&7 constant ANALOG_COMP_0Addr \ Analog Comparator 0
+&8 constant ANALOG_COMP_1Addr \ Analog Comparator 1
+&9 constant ANALOG_COMP_2Addr \ Analog Comparator 2
+&10 constant INT0Addr \ External Interrupt Request 0
+&11 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+&12 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
+&13 constant TIMER1_COMPBAddr \ Timer/Counter Compare Match B
+&14 constant RESERVED15Addr \
+&15 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+&16 constant TIMER0_COMP_AAddr \ Timer/Counter0 Compare Match A
+&17 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
+&18 constant ADCAddr \ ADC Conversion Complete
+&19 constant INT1Addr \ External Interrupt Request 1
+&20 constant SPI__STCAddr \ SPI Serial Transfer Complete
+&21 constant USART__RXAddr \ USART, Rx Complete
+&22 constant USART__UDREAddr \ USART Data Register Empty
+&23 constant USART__TXAddr \ USART, Tx Complete
+&24 constant INT2Addr \ External Interrupt Request 2
+&25 constant WDTAddr \ Watchdog Timeout Interrupt
+&26 constant EE_READYAddr \ EEPROM Ready
+&27 constant TIMER0_COMPBAddr \ Timer Counter 0 Compare Match B
+&28 constant INT3Addr \ External Interrupt Request 3
+&29 constant RESERVED30Addr \
+&30 constant RESERVED31Addr \
+&31 constant SPM_READYAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/at90pwm2b/device.asm b/amforth-6.5/avr8/devices/at90pwm2b/device.asm
new file mode 100644
index 0000000..6656395
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90pwm2b/device.asm
@@ -0,0 +1,123 @@
+; Partname: AT90PWM2B
+; generated automatically, do not edit
+
+.nolist
+ .include "pwm2Bdef.inc"
+.list
+
+.equ ramstart = 256
+.equ CELLSIZE = 2
+.macro readflashcell
+ lsl zl
+ rol zh
+ lpm @0, Z+
+ lpm @1, Z+
+.endmacro
+.macro writeflashcell
+ lsl zl
+ rol zh
+.endmacro
+.set WANT_PORTB = 0
+.set WANT_PORTD = 0
+.set WANT_BOOT_LOAD = 0
+.set WANT_EUSART = 0
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_DA_CONVERTER = 0
+.set WANT_CPU = 0
+.set WANT_PORTE = 0
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_AD_CONVERTER = 0
+.set WANT_USART = 0
+.set WANT_SPI = 0
+.set WANT_WATCHDOG = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_EEPROM = 0
+.set WANT_PSC0 = 0
+.set WANT_PSC2 = 0
+.equ intvecsize = 1 ; please verify; flash size: 8192 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.org 1
+ rcall isr ; PSC2 Capture Event
+.org 2
+ rcall isr ; PSC2 End Cycle
+.org 3
+ rcall isr ; PSC1 Capture Event
+.org 4
+ rcall isr ; PSC1 End Cycle
+.org 5
+ rcall isr ; PSC0 Capture Event
+.org 6
+ rcall isr ; PSC0 End Cycle
+.org 7
+ rcall isr ; Analog Comparator 0
+.org 8
+ rcall isr ; Analog Comparator 1
+.org 9
+ rcall isr ; Analog Comparator 2
+.org 10
+ rcall isr ; External Interrupt Request 0
+.org 11
+ rcall isr ; Timer/Counter1 Capture Event
+.org 12
+ rcall isr ; Timer/Counter1 Compare Match A
+.org 13
+ rcall isr ; Timer/Counter Compare Match B
+.org 14
+ rcall isr ;
+.org 15
+ rcall isr ; Timer/Counter1 Overflow
+.org 16
+ rcall isr ; Timer/Counter0 Compare Match A
+.org 17
+ rcall isr ; Timer/Counter0 Overflow
+.org 18
+ rcall isr ; ADC Conversion Complete
+.org 19
+ rcall isr ; External Interrupt Request 1
+.org 20
+ rcall isr ; SPI Serial Transfer Complete
+.org 21
+ rcall isr ; USART, Rx Complete
+.org 22
+ rcall isr ; USART Data Register Empty
+.org 23
+ rcall isr ; USART, Tx Complete
+.org 24
+ rcall isr ; External Interrupt Request 2
+.org 25
+ rcall isr ; Watchdog Timeout Interrupt
+.org 26
+ rcall isr ; EEPROM Ready
+.org 27
+ rcall isr ; Timer Counter 0 Compare Match B
+.org 28
+ rcall isr ; External Interrupt Request 3
+.org 29
+ rcall isr ;
+.org 30
+ rcall isr ;
+.org 31
+ rcall isr ; Store Program Memory Read
+.equ INTVECTORS = 32
+.nooverlap
+
+; compatability layer (maybe empty)
+.equ EEPE = EEWE
+.equ EEMPE = EEMWE
+
+; controller data area, environment query mcu-info
+mcu_info:
+mcu_ramsize:
+ .dw 512
+mcu_eepromsize:
+ .dw 512
+mcu_maxdp:
+ .dw 6144
+mcu_numints:
+ .dw 32
+mcu_name:
+ .dw 9
+ .db "AT90PWM2B",0
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/at90pwm2b/device.inc b/amforth-6.5/avr8/devices/at90pwm2b/device.inc
new file mode 100644
index 0000000..3605e6b
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90pwm2b/device.inc
@@ -0,0 +1,1281 @@
+; Partname: AT90PWM2B
+; generated automatically, no not edit
+
+.if WANT_PORTB == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw 37
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw 36
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw 35
+
+.endif
+.if WANT_PORTD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw 43
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw 42
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw 41
+
+.endif
+.if WANT_BOOT_LOAD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control Register
+VE_SPMCSR:
+ .dw $ff06
+ .db "SPMCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCSR
+XT_SPMCSR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCSR:
+ .dw 87
+
+.endif
+.if WANT_EUSART == 1
+; ( -- addr ) System Constant
+; R( -- )
+; EUSART I/O Data Register
+VE_EUDR:
+ .dw $ff04
+ .db "EUDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EUDR
+XT_EUDR:
+ .dw PFA_DOVARIABLE
+PFA_EUDR:
+ .dw 206
+; ( -- addr ) System Constant
+; R( -- )
+; EUSART Control and Status Register A
+VE_EUCSRA:
+ .dw $ff06
+ .db "EUCSRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EUCSRA
+XT_EUCSRA:
+ .dw PFA_DOVARIABLE
+PFA_EUCSRA:
+ .dw 200
+; ( -- addr ) System Constant
+; R( -- )
+; EUSART Control Register B
+VE_EUCSRB:
+ .dw $ff06
+ .db "EUCSRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EUCSRB
+XT_EUCSRB:
+ .dw PFA_DOVARIABLE
+PFA_EUCSRB:
+ .dw 201
+; ( -- addr ) System Constant
+; R( -- )
+; EUSART Status Register C
+VE_EUCSRC:
+ .dw $ff06
+ .db "EUCSRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EUCSRC
+XT_EUCSRC:
+ .dw PFA_DOVARIABLE
+PFA_EUCSRC:
+ .dw 202
+; ( -- addr ) System Constant
+; R( -- )
+; Manchester Receiver Baud Rate Register High Byte
+VE_MUBRRH:
+ .dw $ff06
+ .db "MUBRRH"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MUBRRH
+XT_MUBRRH:
+ .dw PFA_DOVARIABLE
+PFA_MUBRRH:
+ .dw 205
+; ( -- addr ) System Constant
+; R( -- )
+; Manchester Receiver Baud Rate Register Low Byte
+VE_MUBRRL:
+ .dw $ff06
+ .db "MUBRRL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MUBRRL
+XT_MUBRRL:
+ .dw PFA_DOVARIABLE
+PFA_MUBRRL:
+ .dw 204
+
+.endif
+.if WANT_ANALOG_COMPARATOR == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator 0 Control Register
+VE_AC0CON:
+ .dw $ff06
+ .db "AC0CON"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_AC0CON
+XT_AC0CON:
+ .dw PFA_DOVARIABLE
+PFA_AC0CON:
+ .dw 173
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator 1 Control Register
+VE_AC1CON:
+ .dw $ff06
+ .db "AC1CON"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_AC1CON
+XT_AC1CON:
+ .dw PFA_DOVARIABLE
+PFA_AC1CON:
+ .dw 174
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator 2 Control Register
+VE_AC2CON:
+ .dw $ff06
+ .db "AC2CON"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_AC2CON
+XT_AC2CON:
+ .dw PFA_DOVARIABLE
+PFA_AC2CON:
+ .dw 175
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw 80
+
+.endif
+.if WANT_DA_CONVERTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; DAC Data Register High Byte
+VE_DACH:
+ .dw $ff04
+ .db "DACH"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DACH
+XT_DACH:
+ .dw PFA_DOVARIABLE
+PFA_DACH:
+ .dw 172
+; ( -- addr ) System Constant
+; R( -- )
+; DAC Data Register Low Byte
+VE_DACL:
+ .dw $ff04
+ .db "DACL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DACL
+XT_DACL:
+ .dw PFA_DOVARIABLE
+PFA_DACL:
+ .dw 171
+; ( -- addr ) System Constant
+; R( -- )
+; DAC Control Register
+VE_DACON:
+ .dw $ff05
+ .db "DACON",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DACON
+XT_DACON:
+ .dw PFA_DOVARIABLE
+PFA_DACON:
+ .dw 170
+
+.endif
+.if WANT_CPU == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw 95
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer
+VE_SP:
+ .dw $ff02
+ .db "SP"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SP
+XT_SP:
+ .dw PFA_DOVARIABLE
+PFA_SP:
+ .dw 93
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw 85
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Status Register
+VE_MCUSR:
+ .dw $ff05
+ .db "MCUSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUSR
+XT_MCUSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUSR:
+ .dw 84
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Calibration Value
+VE_OSCCAL:
+ .dw $ff06
+ .db "OSCCAL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSCCAL
+XT_OSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_OSCCAL:
+ .dw 102
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_CLKPR:
+ .dw $ff05
+ .db "CLKPR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKPR
+XT_CLKPR:
+ .dw PFA_DOVARIABLE
+PFA_CLKPR:
+ .dw 97
+; ( -- addr ) System Constant
+; R( -- )
+; Sleep Mode Control Register
+VE_SMCR:
+ .dw $ff04
+ .db "SMCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SMCR
+XT_SMCR:
+ .dw PFA_DOVARIABLE
+PFA_SMCR:
+ .dw 83
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 3
+VE_GPIOR3:
+ .dw $ff06
+ .db "GPIOR3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR3
+XT_GPIOR3:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR3:
+ .dw 59
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 2
+VE_GPIOR2:
+ .dw $ff06
+ .db "GPIOR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR2
+XT_GPIOR2:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR2:
+ .dw 58
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 1
+VE_GPIOR1:
+ .dw $ff06
+ .db "GPIOR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR1
+XT_GPIOR1:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR1:
+ .dw 57
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 0
+VE_GPIOR0:
+ .dw $ff06
+ .db "GPIOR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR0
+XT_GPIOR0:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR0:
+ .dw 62
+; ( -- addr ) System Constant
+; R( -- )
+; PLL Control And Status Register
+VE_PLLCSR:
+ .dw $ff06
+ .db "PLLCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PLLCSR
+XT_PLLCSR:
+ .dw PFA_DOVARIABLE
+PFA_PLLCSR:
+ .dw 73
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register
+VE_PRR:
+ .dw $ff03
+ .db "PRR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR
+XT_PRR:
+ .dw PFA_DOVARIABLE
+PFA_PRR:
+ .dw 100
+
+.endif
+.if WANT_PORTE == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port E Data Register
+VE_PORTE:
+ .dw $ff05
+ .db "PORTE",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTE
+XT_PORTE:
+ .dw PFA_DOVARIABLE
+PFA_PORTE:
+ .dw 46
+; ( -- addr ) System Constant
+; R( -- )
+; Port E Data Direction Register
+VE_DDRE:
+ .dw $ff04
+ .db "DDRE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRE
+XT_DDRE:
+ .dw PFA_DOVARIABLE
+PFA_DDRE:
+ .dw 45
+; ( -- addr ) System Constant
+; R( -- )
+; Port E Input Pins
+VE_PINE:
+ .dw $ff04
+ .db "PINE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINE
+XT_PINE:
+ .dw PFA_DOVARIABLE
+PFA_PINE:
+ .dw 44
+
+.endif
+.if WANT_TIMER_COUNTER_0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Mask Register
+VE_TIMSK0:
+ .dw $ff06
+ .db "TIMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK0
+XT_TIMSK0:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK0:
+ .dw 110
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Flag register
+VE_TIFR0:
+ .dw $ff05
+ .db "TIFR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR0
+XT_TIFR0:
+ .dw PFA_DOVARIABLE
+PFA_TIFR0:
+ .dw 53
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register A
+VE_TCCR0A:
+ .dw $ff06
+ .db "TCCR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0A
+XT_TCCR0A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0A:
+ .dw 68
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register B
+VE_TCCR0B:
+ .dw $ff06
+ .db "TCCR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0B
+XT_TCCR0B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0B:
+ .dw 69
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw 70
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0A:
+ .dw $ff05
+ .db "OCR0A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0A
+XT_OCR0A:
+ .dw PFA_DOVARIABLE
+PFA_OCR0A:
+ .dw 71
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0B:
+ .dw $ff05
+ .db "OCR0B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0B
+XT_OCR0B:
+ .dw PFA_DOVARIABLE
+PFA_OCR0B:
+ .dw 72
+; ( -- addr ) System Constant
+; R( -- )
+; General Timer/Counter Control Register
+VE_GTCCR:
+ .dw $ff05
+ .db "GTCCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GTCCR
+XT_GTCCR:
+ .dw PFA_DOVARIABLE
+PFA_GTCCR:
+ .dw 67
+
+.endif
+.if WANT_TIMER_COUNTER_1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Mask Register
+VE_TIMSK1:
+ .dw $ff06
+ .db "TIMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK1
+XT_TIMSK1:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK1:
+ .dw 111
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Flag register
+VE_TIFR1:
+ .dw $ff05
+ .db "TIFR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR1
+XT_TIFR1:
+ .dw PFA_DOVARIABLE
+PFA_TIFR1:
+ .dw 54
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw 128
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw 129
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register C
+VE_TCCR1C:
+ .dw $ff06
+ .db "TCCR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1C
+XT_TCCR1C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1C:
+ .dw 130
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Bytes
+VE_TCNT1:
+ .dw $ff05
+ .db "TCNT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1
+XT_TCNT1:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1:
+ .dw 132
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register Bytes
+VE_OCR1A:
+ .dw $ff05
+ .db "OCR1A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1A
+XT_OCR1A:
+ .dw PFA_DOVARIABLE
+PFA_OCR1A:
+ .dw 136
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register Bytes
+VE_OCR1B:
+ .dw $ff05
+ .db "OCR1B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1B
+XT_OCR1B:
+ .dw PFA_DOVARIABLE
+PFA_OCR1B:
+ .dw 138
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Bytes
+VE_ICR1:
+ .dw $ff04
+ .db "ICR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1
+XT_ICR1:
+ .dw PFA_DOVARIABLE
+PFA_ICR1:
+ .dw 134
+
+.endif
+.if WANT_AD_CONVERTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC multiplexer Selection Register
+VE_ADMUX:
+ .dw $ff05
+ .db "ADMUX",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADMUX
+XT_ADMUX:
+ .dw PFA_DOVARIABLE
+PFA_ADMUX:
+ .dw 124
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register
+VE_ADCSRA:
+ .dw $ff06
+ .db "ADCSRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRA
+XT_ADCSRA:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRA:
+ .dw 122
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register Bytes
+VE_ADC:
+ .dw $ff03
+ .db "ADC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADC
+XT_ADC:
+ .dw PFA_DOVARIABLE
+PFA_ADC:
+ .dw 120
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Control and Status Register B
+VE_ADCSRB:
+ .dw $ff06
+ .db "ADCSRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRB
+XT_ADCSRB:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRB:
+ .dw 123
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 0
+VE_DIDR0:
+ .dw $ff05
+ .db "DIDR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR0
+XT_DIDR0:
+ .dw PFA_DOVARIABLE
+PFA_DIDR0:
+ .dw 126
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 0
+VE_DIDR1:
+ .dw $ff05
+ .db "DIDR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR1
+XT_DIDR1:
+ .dw PFA_DOVARIABLE
+PFA_DIDR1:
+ .dw 127
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_AMP0CSR:
+ .dw $ff07
+ .db "AMP0CSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_AMP0CSR
+XT_AMP0CSR:
+ .dw PFA_DOVARIABLE
+PFA_AMP0CSR:
+ .dw 118
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_AMP1CSR:
+ .dw $ff07
+ .db "AMP1CSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_AMP1CSR
+XT_AMP1CSR:
+ .dw PFA_DOVARIABLE
+PFA_AMP1CSR:
+ .dw 119
+
+.endif
+.if WANT_USART == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR:
+ .dw $ff03
+ .db "UDR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR
+XT_UDR:
+ .dw PFA_DOVARIABLE
+PFA_UDR:
+ .dw 198
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status register A
+VE_UCSRA:
+ .dw $ff05
+ .db "UCSRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSRA
+XT_UCSRA:
+ .dw PFA_DOVARIABLE
+PFA_UCSRA:
+ .dw 192
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control an Status register B
+VE_UCSRB:
+ .dw $ff05
+ .db "UCSRB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSRB
+XT_UCSRB:
+ .dw PFA_DOVARIABLE
+PFA_UCSRB:
+ .dw 193
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control an Status register C
+VE_UCSRC:
+ .dw $ff05
+ .db "UCSRC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSRC
+XT_UCSRC:
+ .dw PFA_DOVARIABLE
+PFA_UCSRC:
+ .dw 194
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register High Byte
+VE_UBRRH:
+ .dw $ff05
+ .db "UBRRH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRRH
+XT_UBRRH:
+ .dw PFA_DOVARIABLE
+PFA_UBRRH:
+ .dw 197
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Low Byte
+VE_UBRRL:
+ .dw $ff05
+ .db "UBRRL",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRRL
+XT_UBRRL:
+ .dw PFA_DOVARIABLE
+PFA_UBRRL:
+ .dw 196
+
+.endif
+.if WANT_SPI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR:
+ .dw $ff04
+ .db "SPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR
+XT_SPCR:
+ .dw PFA_DOVARIABLE
+PFA_SPCR:
+ .dw 76
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR:
+ .dw $ff04
+ .db "SPSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR
+XT_SPSR:
+ .dw PFA_DOVARIABLE
+PFA_SPSR:
+ .dw 77
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR:
+ .dw $ff04
+ .db "SPDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR
+XT_SPDR:
+ .dw PFA_DOVARIABLE
+PFA_SPDR:
+ .dw 78
+
+.endif
+.if WANT_WATCHDOG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCSR:
+ .dw $ff06
+ .db "WDTCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCSR
+XT_WDTCSR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCSR:
+ .dw 96
+
+.endif
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register A
+VE_EICRA:
+ .dw $ff05
+ .db "EICRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRA
+XT_EICRA:
+ .dw PFA_DOVARIABLE
+PFA_EICRA:
+ .dw 105
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Mask Register
+VE_EIMSK:
+ .dw $ff05
+ .db "EIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIMSK
+XT_EIMSK:
+ .dw PFA_DOVARIABLE
+PFA_EIMSK:
+ .dw 61
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Flag Register
+VE_EIFR:
+ .dw $ff04
+ .db "EIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIFR
+XT_EIFR:
+ .dw PFA_DOVARIABLE
+PFA_EIFR:
+ .dw 60
+
+.endif
+.if WANT_EEPROM == 1
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Read/Write Access Bytes
+VE_EEAR:
+ .dw $ff04
+ .db "EEAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEAR
+XT_EEAR:
+ .dw PFA_DOVARIABLE
+PFA_EEAR:
+ .dw 65
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw 64
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw 63
+
+.endif
+.if WANT_PSC0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 0 Input Capture Register
+VE_PICR0:
+ .dw $ff05
+ .db "PICR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PICR0
+XT_PICR0:
+ .dw PFA_DOVARIABLE
+PFA_PICR0:
+ .dw 222
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 0 Input B Control
+VE_PFRC0B:
+ .dw $ff06
+ .db "PFRC0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PFRC0B
+XT_PFRC0B:
+ .dw PFA_DOVARIABLE
+PFA_PFRC0B:
+ .dw 221
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 0 Input A Control
+VE_PFRC0A:
+ .dw $ff06
+ .db "PFRC0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PFRC0A
+XT_PFRC0A:
+ .dw PFA_DOVARIABLE
+PFA_PFRC0A:
+ .dw 220
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 0 Control Register
+VE_PCTL0:
+ .dw $ff05
+ .db "PCTL0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCTL0
+XT_PCTL0:
+ .dw PFA_DOVARIABLE
+PFA_PCTL0:
+ .dw 219
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 0 Configuration Register
+VE_PCNF0:
+ .dw $ff05
+ .db "PCNF0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCNF0
+XT_PCNF0:
+ .dw PFA_DOVARIABLE
+PFA_PCNF0:
+ .dw 218
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare RB Register
+VE_OCR0RB:
+ .dw $ff06
+ .db "OCR0RB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0RB
+XT_OCR0RB:
+ .dw PFA_DOVARIABLE
+PFA_OCR0RB:
+ .dw 216
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare SB Register
+VE_OCR0SB:
+ .dw $ff06
+ .db "OCR0SB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0SB
+XT_OCR0SB:
+ .dw PFA_DOVARIABLE
+PFA_OCR0SB:
+ .dw 214
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare RA Register
+VE_OCR0RA:
+ .dw $ff06
+ .db "OCR0RA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0RA
+XT_OCR0RA:
+ .dw PFA_DOVARIABLE
+PFA_OCR0RA:
+ .dw 212
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare SA Register
+VE_OCR0SA:
+ .dw $ff06
+ .db "OCR0SA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0SA
+XT_OCR0SA:
+ .dw PFA_DOVARIABLE
+PFA_OCR0SA:
+ .dw 210
+; ( -- addr ) System Constant
+; R( -- )
+; PSC0 Synchro and Output Configuration
+VE_PSOC0:
+ .dw $ff05
+ .db "PSOC0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PSOC0
+XT_PSOC0:
+ .dw PFA_DOVARIABLE
+PFA_PSOC0:
+ .dw 208
+; ( -- addr ) System Constant
+; R( -- )
+; PSC0 Interrupt Mask Register
+VE_PIM0:
+ .dw $ff04
+ .db "PIM0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIM0
+XT_PIM0:
+ .dw PFA_DOVARIABLE
+PFA_PIM0:
+ .dw 161
+; ( -- addr ) System Constant
+; R( -- )
+; PSC0 Interrupt Flag Register
+VE_PIFR0:
+ .dw $ff05
+ .db "PIFR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIFR0
+XT_PIFR0:
+ .dw PFA_DOVARIABLE
+PFA_PIFR0:
+ .dw 160
+
+.endif
+.if WANT_PSC2 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 2 Input Capture Register
+VE_PICR2:
+ .dw $ff05
+ .db "PICR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PICR2
+XT_PICR2:
+ .dw PFA_DOVARIABLE
+PFA_PICR2:
+ .dw 254
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 2 Input B Control
+VE_PFRC2B:
+ .dw $ff06
+ .db "PFRC2B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PFRC2B
+XT_PFRC2B:
+ .dw PFA_DOVARIABLE
+PFA_PFRC2B:
+ .dw 253
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 2 Input B Control
+VE_PFRC2A:
+ .dw $ff06
+ .db "PFRC2A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PFRC2A
+XT_PFRC2A:
+ .dw PFA_DOVARIABLE
+PFA_PFRC2A:
+ .dw 252
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 2 Control Register
+VE_PCTL2:
+ .dw $ff05
+ .db "PCTL2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCTL2
+XT_PCTL2:
+ .dw PFA_DOVARIABLE
+PFA_PCTL2:
+ .dw 251
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 2 Configuration Register
+VE_PCNF2:
+ .dw $ff05
+ .db "PCNF2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCNF2
+XT_PCNF2:
+ .dw PFA_DOVARIABLE
+PFA_PCNF2:
+ .dw 250
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare RB Register
+VE_OCR2RB:
+ .dw $ff06
+ .db "OCR2RB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2RB
+XT_OCR2RB:
+ .dw PFA_DOVARIABLE
+PFA_OCR2RB:
+ .dw 248
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare SB Register
+VE_OCR2SB:
+ .dw $ff06
+ .db "OCR2SB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2SB
+XT_OCR2SB:
+ .dw PFA_DOVARIABLE
+PFA_OCR2SB:
+ .dw 246
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare RA Register
+VE_OCR2RA:
+ .dw $ff06
+ .db "OCR2RA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2RA
+XT_OCR2RA:
+ .dw PFA_DOVARIABLE
+PFA_OCR2RA:
+ .dw 244
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare SA Register
+VE_OCR2SA:
+ .dw $ff06
+ .db "OCR2SA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2SA
+XT_OCR2SA:
+ .dw PFA_DOVARIABLE
+PFA_OCR2SA:
+ .dw 242
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 2 Output Matrix
+VE_POM2:
+ .dw $ff04
+ .db "POM2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_POM2
+XT_POM2:
+ .dw PFA_DOVARIABLE
+PFA_POM2:
+ .dw 241
+; ( -- addr ) System Constant
+; R( -- )
+; PSC2 Synchro and Output Configuration
+VE_PSOC2:
+ .dw $ff05
+ .db "PSOC2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PSOC2
+XT_PSOC2:
+ .dw PFA_DOVARIABLE
+PFA_PSOC2:
+ .dw 240
+; ( -- addr ) System Constant
+; R( -- )
+; PSC2 Interrupt Mask Register
+VE_PIM2:
+ .dw $ff04
+ .db "PIM2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIM2
+XT_PIM2:
+ .dw PFA_DOVARIABLE
+PFA_PIM2:
+ .dw 165
+; ( -- addr ) System Constant
+; R( -- )
+; PSC2 Interrupt Flag Register
+VE_PIFR2:
+ .dw $ff05
+ .db "PIFR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIFR2
+XT_PIFR2:
+ .dw PFA_DOVARIABLE
+PFA_PIFR2:
+ .dw 164
+
+.endif
diff --git a/amforth-6.5/avr8/devices/at90pwm2b/device.py b/amforth-6.5/avr8/devices/at90pwm2b/device.py
new file mode 100644
index 0000000..4ef048e
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90pwm2b/device.py
@@ -0,0 +1,448 @@
+# Generated Automatically
+
+# Partname AT90PWM2B
+
+MCUREGS = {
+# Interrupt Vectors
+ 'PSC2_CAPTAddr' : '#2', # PSC2 Capture Event
+ 'PSC2_ECAddr' : '#4', # PSC2 End Cycle
+ 'PSC1_CAPTAddr' : '#6', # PSC1 Capture Event
+ 'PSC1_ECAddr' : '#8', # PSC1 End Cycle
+ 'PSC0_CAPTAddr' : '#10', # PSC0 Capture Event
+ 'PSC0_ECAddr' : '#12', # PSC0 End Cycle
+ 'ANALOG_COMP_0Addr' : '#14', # Analog Comparator 0
+ 'ANALOG_COMP_1Addr' : '#16', # Analog Comparator 1
+ 'ANALOG_COMP_2Addr' : '#18', # Analog Comparator 2
+ 'INT0Addr' : '#20', # External Interrupt Request 0
+ 'TIMER1_CAPTAddr' : '#22', # Timer/Counter1 Capture Event
+ 'TIMER1_COMPAAddr' : '#24', # Timer/Counter1 Compare Match A
+ 'TIMER1_COMPBAddr' : '#26', # Timer/Counter Compare Match B
+ 'RESERVED15Addr' : '#28', #
+ 'TIMER1_OVFAddr' : '#30', # Timer/Counter1 Overflow
+ 'TIMER0_COMP_AAddr' : '#32', # Timer/Counter0 Compare Match A
+ 'TIMER0_OVFAddr' : '#34', # Timer/Counter0 Overflow
+ 'ADCAddr' : '#36', # ADC Conversion Complete
+ 'INT1Addr' : '#38', # External Interrupt Request 1
+ 'SPI_STCAddr' : '#40', # SPI Serial Transfer Complete
+ 'USART_RXAddr' : '#42', # USART, Rx Complete
+ 'USART_UDREAddr' : '#44', # USART Data Register Empty
+ 'USART_TXAddr' : '#46', # USART, Tx Complete
+ 'INT2Addr' : '#48', # External Interrupt Request 2
+ 'WDTAddr' : '#50', # Watchdog Timeout Interrupt
+ 'EE_READYAddr' : '#52', # EEPROM Ready
+ 'TIMER0_COMPBAddr' : '#54', # Timer Counter 0 Compare Match B
+ 'INT3Addr' : '#56', # External Interrupt Request 3
+ 'RESERVED30Addr' : '#58', #
+ 'RESERVED31Addr' : '#60', #
+ 'SPM_READYAddr' : '#62', # Store Program Memory Read
+
+# Module PORTB
+ 'PORTB' : '$25', # Port B Data Register
+ 'DDRB' : '$24', # Port B Data Direction Register
+ 'PINB' : '$23', # Port B Input Pins
+
+# Module PORTD
+ 'PORTD' : '$2b', # Port D Data Register
+ 'DDRD' : '$2a', # Port D Data Direction Register
+ 'PIND' : '$29', # Port D Input Pins
+
+# Module BOOT_LOAD
+ 'SPMCSR' : '$57', # Store Program Memory Control R
+ 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
+ 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
+ 'SPMCSR_RWWSRE': '$10', # Read While Write section read
+ 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
+ 'SPMCSR_PGWRT': '$4', # Page Write
+ 'SPMCSR_PGERS': '$2', # Page Erase
+ 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
+
+# Module EUSART
+ 'EUDR' : '$ce', # EUSART I/O Data Register
+ 'EUCSRA' : '$c8', # EUSART Control and Status Regi
+ 'EUCSRA_UTxS': '$f0', # EUSART Control and Status Regi
+ 'EUCSRA_URxS': '$f', # EUSART Control and Status Regi
+ 'EUCSRB' : '$c9', # EUSART Control Register B
+ 'EUCSRB_EUSART': '$10', # EUSART Enable Bit
+ 'EUCSRB_EUSBS': '$8', # EUSBS Enable Bit
+ 'EUCSRB_EMCH': '$2', # Manchester Mode Bit
+ 'EUCSRB_BODR': '$1', # Order Bit
+ 'EUCSRC' : '$ca', # EUSART Status Register C
+ 'EUCSRC_FEM': '$8', # Frame Error Manchester Bit
+ 'EUCSRC_F1617': '$4', # F1617 Bit
+ 'EUCSRC_STP': '$3', # Stop Bits
+ 'MUBRRH' : '$cd', # Manchester Receiver Baud Rate
+ 'MUBRRH_MUBRR': '$ff', # Manchester Receiver Baud Rate
+ 'MUBRRL' : '$cc', # Manchester Receiver Baud Rate
+ 'MUBRRL_MUBRR': '$ff', # Manchester Receiver Baud Rate
+
+# Module ANALOG_COMPARATOR
+ 'AC0CON' : '$ad', # Analog Comparator 0 Control Re
+ 'AC0CON_AC0EN': '$80', # Analog Comparator 0 Enable Bit
+ 'AC0CON_AC0IE': '$40', # Analog Comparator 0 Interrupt
+ 'AC0CON_AC0IS': '$30', # Analog Comparator 0 Interrupt
+ 'AC0CON_AC0M': '$7', # Analog Comparator 0 Multiplexe
+ 'AC1CON' : '$ae', # Analog Comparator 1 Control Re
+ 'AC1CON_AC1EN': '$80', # Analog Comparator 1 Enable Bit
+ 'AC1CON_AC1IE': '$40', # Analog Comparator 1 Interrupt
+ 'AC1CON_AC1IS': '$30', # Analog Comparator 1 Interrupt
+ 'AC1CON_AC1ICE': '$8', # Analog Comparator 1 Interrupt
+ 'AC1CON_AC1M': '$7', # Analog Comparator 1 Multiplexe
+ 'AC2CON' : '$af', # Analog Comparator 2 Control Re
+ 'AC2CON_AC2EN': '$80', # Analog Comparator 2 Enable Bit
+ 'AC2CON_AC2IE': '$40', # Analog Comparator 2 Interrupt
+ 'AC2CON_AC2IS': '$30', # Analog Comparator 2 Interrupt
+ 'AC2CON_AC2M': '$7', # Analog Comparator 2 Multiplexe
+ 'ACSR' : '$50', # Analog Comparator Status Regis
+ 'ACSR_ACCKDIV': '$80', # Analog Comparator Clock Divide
+ 'ACSR_AC2IF': '$40', # Analog Comparator 2 Interrupt
+ 'ACSR_AC1IF': '$20', # Analog Comparator 1 Interrupt
+ 'ACSR_AC0IF': '$10', # Analog Comparator 0 Interrupt
+ 'ACSR_AC2O': '$4', # Analog Comparator 2 Output Bit
+ 'ACSR_AC1O': '$2', # Analog Comparator 1 Output Bit
+ 'ACSR_AC0O': '$1', # Analog Comparator 0 Output Bit
+
+# Module DA_CONVERTER
+ 'DACH' : '$ac', # DAC Data Register High Byte
+ 'DACH_DACH': '$ff', # DAC Data Register High Byte Bi
+ 'DACL' : '$ab', # DAC Data Register Low Byte
+ 'DACL_DACL': '$ff', # DAC Data Register Low Byte Bit
+ 'DACON' : '$aa', # DAC Control Register
+ 'DACON_DAATE': '$80', # DAC Auto Trigger Enable Bit
+ 'DACON_DATS': '$70', # DAC Trigger Selection Bits
+ 'DACON_DALA': '$4', # DAC Left Adjust
+ 'DACON_DAEN': '$1', # DAC Enable Bit
+
+# Module CPU
+ 'SREG' : '$5f', # Status Register
+ 'SREG_I': '$80', # Global Interrupt Enable
+ 'SREG_T': '$40', # Bit Copy Storage
+ 'SREG_H': '$20', # Half Carry Flag
+ 'SREG_S': '$10', # Sign Bit
+ 'SREG_V': '$8', # Two's Complement Overflow Flag
+ 'SREG_N': '$4', # Negative Flag
+ 'SREG_Z': '$2', # Zero Flag
+ 'SREG_C': '$1', # Carry Flag
+ 'SP' : '$5d', # Stack Pointer
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_SPIPS': '$80', # SPI Pin Select
+ 'MCUCR_PUD': '$10', # Pull-up disable
+ 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
+ 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
+ 'MCUSR_BORF': '$4', # Brown-out Reset Flag
+ 'MCUSR_EXTRF': '$2', # External Reset Flag
+ 'MCUSR_PORF': '$1', # Power-on reset flag
+ 'OSCCAL' : '$66', # Oscillator Calibration Value
+ 'CLKPR' : '$61', #
+ 'CLKPR_CLKPCE': '$80', #
+ 'CLKPR_CLKPS': '$f', #
+ 'SMCR' : '$53', # Sleep Mode Control Register
+ 'SMCR_SM': '$e', # Sleep Mode Select bits
+ 'SMCR_SE': '$1', # Sleep Enable
+ 'GPIOR3' : '$3b', # General Purpose IO Register 3
+ 'GPIOR3_GPIOR': '$ff', # General Purpose IO Register 3
+ 'GPIOR2' : '$3a', # General Purpose IO Register 2
+ 'GPIOR2_GPIOR': '$ff', # General Purpose IO Register 2
+ 'GPIOR1' : '$39', # General Purpose IO Register 1
+ 'GPIOR1_GPIOR': '$ff', # General Purpose IO Register 1
+ 'GPIOR0' : '$3e', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR07': '$80', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR06': '$40', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR05': '$20', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR04': '$10', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR03': '$8', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR02': '$4', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR01': '$2', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR00': '$1', # General Purpose IO Register 0
+ 'PLLCSR' : '$49', # PLL Control And Status Registe
+ 'PLLCSR_PLLF': '$4', # PLL Factor
+ 'PLLCSR_PLLE': '$2', # PLL Enable
+ 'PLLCSR_PLOCK': '$1', # PLL Lock Detector
+ 'PRR' : '$64', # Power Reduction Register
+ 'PRR_PRPSC': '$e0', # Power Reduction PSC2
+ 'PRR_PRTIM1': '$10', # Power Reduction Timer/Counter1
+ 'PRR_PRTIM0': '$8', # Power Reduction Timer/Counter0
+ 'PRR_PRSPI': '$4', # Power Reduction Serial Periphe
+ 'PRR_PRUSART0': '$2', # Power Reduction USART
+ 'PRR_PRADC': '$1', # Power Reduction ADC
+
+# Module PORTE
+ 'PORTE' : '$2e', # Port E Data Register
+ 'DDRE' : '$2d', # Port E Data Direction Register
+ 'PINE' : '$2c', # Port E Input Pins
+
+# Module TIMER_COUNTER_0
+ 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
+ 'TIMSK0_OCIE0B': '$4', # Timer/Counter0 Output Compare
+ 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
+ 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
+ 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
+ 'TIFR0_OCF0B': '$4', # Timer/Counter0 Output Compare
+ 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
+ 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
+ 'TCCR0A' : '$44', # Timer/Counter Control Registe
+ 'TCCR0A_COM0A': '$c0', # Compare Output Mode, Phase Cor
+ 'TCCR0A_COM0B': '$30', # Compare Output Mode, Fast PWm
+ 'TCCR0A_WGM0': '$3', # Waveform Generation Mode
+ 'TCCR0B' : '$45', # Timer/Counter Control Register
+ 'TCCR0B_FOC0A': '$80', # Force Output Compare A
+ 'TCCR0B_FOC0B': '$40', # Force Output Compare B
+ 'TCCR0B_WGM02': '$8', #
+ 'TCCR0B_CS0': '$7', # Clock Select
+ 'TCNT0' : '$46', # Timer/Counter0
+ 'OCR0A' : '$47', # Timer/Counter0 Output Compare
+ 'OCR0B' : '$48', # Timer/Counter0 Output Compare
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_ICPSEL1': '$40', # Timer1 Input Capture Selection
+ 'GTCCR_PSR10': '$1', # Prescaler Reset Timer/Counter1
+
+# Module TIMER_COUNTER_1
+ 'TIMSK1' : '$6f', # Timer/Counter Interrupt Mask R
+ 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
+ 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output CompareB
+ 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output CompareA
+ 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
+ 'TIFR1' : '$36', # Timer/Counter Interrupt Flag r
+ 'TIFR1_ICF1': '$20', # Input Capture Flag 1
+ 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
+ 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
+ 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
+ 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
+ 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
+ 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
+ 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
+ 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
+ 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
+ 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
+ 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
+ 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
+ 'TCCR1C' : '$82', # Timer/Counter1 Control Registe
+ 'TCCR1C_FOC1A': '$80', #
+ 'TCCR1C_FOC1B': '$40', #
+ 'TCNT1' : '$84', # Timer/Counter1 Bytes
+ 'OCR1A' : '$88', # Timer/Counter1 Output Compare
+ 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
+ 'ICR1' : '$86', # Timer/Counter1 Input Capture R
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSRSYNC': '$1', # Prescaler Reset Timer/Counter1
+
+# Module AD_CONVERTER
+ 'ADMUX' : '$7c', # The ADC multiplexer Selection
+ 'ADMUX_REFS': '$c0', # Reference Selection Bits
+ 'ADMUX_ADLAR': '$20', # Left Adjust Result
+ 'ADMUX_MUX': '$f', # Analog Channel and Gain Select
+ 'ADCSRA' : '$7a', # The ADC Control and Status reg
+ 'ADCSRA_ADEN': '$80', # ADC Enable
+ 'ADCSRA_ADSC': '$40', # ADC Start Conversion
+ 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
+ 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
+ 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
+ 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
+ 'ADC' : '$78', # ADC Data Register Bytes
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'DIDR0' : '$7e', # Digital Input Disable Register
+ 'DIDR1' : '$7f', # Digital Input Disable Register
+ 'DIDR1_ACMP0D': '$20', #
+ 'DIDR1_AMP0PD': '$10', #
+ 'DIDR1_AMP0ND': '$8', #
+ 'DIDR1_ADC10D': '$4', #
+ 'DIDR1_ADC9D': '$2', #
+ 'DIDR1_ADC8D': '$1', #
+ 'AMP0CSR' : '$76', #
+ 'AMP0CSR_AMP0EN': '$80', #
+ 'AMP0CSR_AMP0IS': '$40', #
+ 'AMP0CSR_AMP0G': '$30', #
+ 'AMP0CSR_AMP0TS': '$3', #
+ 'AMP1CSR' : '$77', #
+ 'AMP1CSR_AMP1EN': '$80', #
+ 'AMP1CSR_AMP1IS': '$40', #
+ 'AMP1CSR_AMP1G': '$30', #
+ 'AMP1CSR_AMP1TS': '$3', #
+
+# Module USART
+ 'UDR' : '$c6', # USART I/O Data Register
+ 'UCSRA' : '$c0', # USART Control and Status regis
+ 'UCSRA_RXC': '$80', # USART Receive Complete
+ 'UCSRA_TXC': '$40', # USART Transmitt Complete
+ 'UCSRA_UDRE': '$20', # USART Data Register Empty
+ 'UCSRA_FE': '$10', # Framing Error
+ 'UCSRA_DOR': '$8', # Data Overrun
+ 'UCSRA_UPE': '$4', # USART Parity Error
+ 'UCSRA_U2X': '$2', # Double USART Transmission Bit
+ 'UCSRA_MPCM': '$1', # Multi-processor Communication
+ 'UCSRB' : '$c1', # USART Control an Status regist
+ 'UCSRB_RXCIE': '$80', # RX Complete Interrupt Enable
+ 'UCSRB_TXCIE': '$40', # TX Complete Interrupt Enable
+ 'UCSRB_UDRIE': '$20', # USART Data Register Empty Inte
+ 'UCSRB_RXEN': '$10', # Receiver Enable
+ 'UCSRB_TXEN': '$8', # Transmitter Enable
+ 'UCSRB_UCSZ2': '$4', # Character Size
+ 'UCSRB_RXB8': '$2', # Receive Data Bit 8
+ 'UCSRB_TXB8': '$1', # Transmit Data Bit 8
+ 'UCSRC' : '$c2', # USART Control an Status regist
+ 'UCSRC_UMSEL0': '$40', # USART Mode Select
+ 'UCSRC_UPM': '$30', # Parity Mode Bits
+ 'UCSRC_USBS': '$8', # Stop Bit Select
+ 'UCSRC_UCSZ': '$6', # Character Size Bits
+ 'UCSRC_UCPOL': '$1', # Clock Polarity
+ 'UBRRH' : '$c5', # USART Baud Rate Register High
+ 'UBRRH_UBRR': '$f', # USART Baud Rate Register Bits
+ 'UBRRL' : '$c4', # USART Baud Rate Register Low B
+ 'UBRRL_UBRR': '$ff', # USART Baud Rate Register bits
+
+# Module SPI
+ 'SPCR' : '$4c', # SPI Control Register
+ 'SPCR_SPIE': '$80', # SPI Interrupt Enable
+ 'SPCR_SPE': '$40', # SPI Enable
+ 'SPCR_DORD': '$20', # Data Order
+ 'SPCR_MSTR': '$10', # Master/Slave Select
+ 'SPCR_CPOL': '$8', # Clock polarity
+ 'SPCR_CPHA': '$4', # Clock Phase
+ 'SPCR_SPR': '$3', # SPI Clock Rate Selects
+ 'SPSR' : '$4d', # SPI Status Register
+ 'SPSR_SPIF': '$80', # SPI Interrupt Flag
+ 'SPSR_WCOL': '$40', # Write Collision Flag
+ 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
+ 'SPDR' : '$4e', # SPI Data Register
+
+# Module WATCHDOG
+ 'WDTCSR' : '$60', # Watchdog Timer Control Registe
+ 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
+ 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
+ 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
+ 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
+ 'WDTCSR_WDE': '$8', # Watch Dog Enable
+
+# Module EXTERNAL_INTERRUPT
+ 'EICRA' : '$69', # External Interrupt Control Reg
+ 'EICRA_ISC2': '$30', # External Interrupt Sense Contr
+ 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
+ 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
+ 'EIMSK' : '$3d', # External Interrupt Mask Regist
+ 'EIMSK_INT': '$7', # External Interrupt Request 2 E
+ 'EIFR' : '$3c', # External Interrupt Flag Regist
+ 'EIFR_INTF': '$7', # External Interrupt Flags
+
+# Module EEPROM
+ 'EEAR' : '$41', # EEPROM Read/Write Access Byte
+ 'EEDR' : '$40', # EEPROM Data Register
+ 'EECR' : '$3f', # EEPROM Control Register
+ 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
+ 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
+ 'EECR_EEWE': '$2', # EEPROM Write Enable
+ 'EECR_EERE': '$1', # EEPROM Read Enable
+
+# Module PSC0
+ 'PICR0' : '$de', # PSC 0 Input Capture Register
+ 'PFRC0B' : '$dd', # PSC 0 Input B Control
+ 'PFRC0B_PCAE0B': '$80', # PSC 0 Capture Enable Input Par
+ 'PFRC0B_PISEL0B': '$40', # PSC 0 Input Select for Part B
+ 'PFRC0B_PELEV0B': '$20', # PSC 0 Edge Level Selector on I
+ 'PFRC0B_PFLTE0B': '$10', # PSC 0 Filter Enable on Input P
+ 'PFRC0B_PRFM0B': '$f', # PSC 0 Retrigger and Fault Mode
+ 'PFRC0A' : '$dc', # PSC 0 Input A Control
+ 'PFRC0A_PCAE0A': '$80', # PSC 0 Capture Enable Input Par
+ 'PFRC0A_PISEL0A': '$40', # PSC 0 Input Select for Part A
+ 'PFRC0A_PELEV0A': '$20', # PSC 0 Edge Level Selector on I
+ 'PFRC0A_PFLTE0A': '$10', # PSC 0 Filter Enable on Input P
+ 'PFRC0A_PRFM0A': '$f', # PSC 0 Retrigger and Fault Mode
+ 'PCTL0' : '$db', # PSC 0 Control Register
+ 'PCTL0_PPRE0': '$c0', # PSC 0 Prescaler Selects
+ 'PCTL0_PBFM0': '$20', # PSC 0 Balance Flank Width Modu
+ 'PCTL0_PAOC0B': '$10', # PSC 0 Asynchronous Output Cont
+ 'PCTL0_PAOC0A': '$8', # PSC 0 Asynchronous Output Cont
+ 'PCTL0_PARUN0': '$4', # PSC0 Auto Run
+ 'PCTL0_PCCYC0': '$2', # PSC0 Complete Cycle
+ 'PCTL0_PRUN0': '$1', # PSC 0 Run
+ 'PCNF0' : '$da', # PSC 0 Configuration Register
+ 'PCNF0_PFIFTY0': '$80', # PSC 0 Fifty
+ 'PCNF0_PALOCK0': '$40', # PSC 0 Autolock
+ 'PCNF0_PLOCK0': '$20', # PSC 0 Lock
+ 'PCNF0_PMODE0': '$18', # PSC 0 Mode
+ 'PCNF0_POP0': '$4', # PSC 0 Output Polarity
+ 'PCNF0_PCLKSEL0': '$2', # PSC 0 Input Clock Select
+ 'OCR0RB' : '$d8', # Output Compare RB Register
+ 'OCR0SB' : '$d6', # Output Compare SB Register
+ 'OCR0RA' : '$d4', # Output Compare RA Register
+ 'OCR0SA' : '$d2', # Output Compare SA Register
+ 'PSOC0' : '$d0', # PSC0 Synchro and Output Config
+ 'PSOC0_PSYNC0': '$30', # Synchronization Out for ADC Se
+ 'PSOC0_POEN0B': '$4', # PSCOUT01 Output Enable
+ 'PSOC0_POEN0A': '$1', # PSCOUT00 Output Enable
+ 'PIM0' : '$a1', # PSC0 Interrupt Mask Register
+ 'PIM0_PSEIE0': '$20', # PSC 0 Synchro Error Interrupt
+ 'PIM0_PEVE0B': '$10', # External Event B Interrupt Ena
+ 'PIM0_PEVE0A': '$8', # External Event A Interrupt Ena
+ 'PIM0_PEOPE0': '$1', # End of Cycle Interrupt Enable
+ 'PIFR0' : '$a0', # PSC0 Interrupt Flag Register
+ 'PIFR0_POAC0B': '$80', # PSC 0 Output A Activity
+ 'PIFR0_POAC0A': '$40', # PSC 0 Output A Activity
+ 'PIFR0_PSEI0': '$20', # PSC 0 Synchro Error Interrupt
+ 'PIFR0_PEV0B': '$10', # External Event B Interrupt
+ 'PIFR0_PEV0A': '$8', # External Event A Interrupt
+ 'PIFR0_PRN0': '$6', # Ramp Number
+ 'PIFR0_PEOP0': '$1', # End of PSC0 Interrupt
+
+# Module PSC2
+ 'PICR2' : '$fe', # PSC 2 Input Capture Register
+ 'PFRC2B' : '$fd', # PSC 2 Input B Control
+ 'PFRC2B_PCAE2B': '$80', # PSC 2 Capture Enable Input Par
+ 'PFRC2B_PISEL2B': '$40', # PSC 2 Input Select for Part B
+ 'PFRC2B_PELEV2B': '$20', # PSC 2 Edge Level Selector on I
+ 'PFRC2B_PFLTE2B': '$10', # PSC 2 Filter Enable on Input P
+ 'PFRC2B_PRFM2B': '$f', # PSC 2 Retrigger and Fault Mode
+ 'PFRC2A' : '$fc', # PSC 2 Input B Control
+ 'PFRC2A_PCAE2A': '$80', # PSC 2 Capture Enable Input Par
+ 'PFRC2A_PISEL2A': '$40', # PSC 2 Input Select for Part A
+ 'PFRC2A_PELEV2A': '$20', # PSC 2 Edge Level Selector on I
+ 'PFRC2A_PFLTE2A': '$10', # PSC 2 Filter Enable on Input P
+ 'PFRC2A_PRFM2A': '$f', # PSC 2 Retrigger and Fault Mode
+ 'PCTL2' : '$fb', # PSC 2 Control Register
+ 'PCTL2_PPRE2': '$c0', # PSC 2 Prescaler Selects
+ 'PCTL2_PBFM2': '$20', # Balance Flank Width Modulation
+ 'PCTL2_PAOC2B': '$10', # PSC 2 Asynchronous Output Cont
+ 'PCTL2_PAOC2A': '$8', # PSC 2 Asynchronous Output Cont
+ 'PCTL2_PARUN2': '$4', # PSC2 Auto Run
+ 'PCTL2_PCCYC2': '$2', # PSC2 Complete Cycle
+ 'PCTL2_PRUN2': '$1', # PSC 2 Run
+ 'PCNF2' : '$fa', # PSC 2 Configuration Register
+ 'PCNF2_PFIFTY2': '$80', # PSC 2 Fifty
+ 'PCNF2_PALOCK2': '$40', # PSC 2 Autolock
+ 'PCNF2_PLOCK2': '$20', # PSC 2 Lock
+ 'PCNF2_PMODE2': '$18', # PSC 2 Mode
+ 'PCNF2_POP2': '$4', # PSC 2 Output Polarity
+ 'PCNF2_PCLKSEL2': '$2', # PSC 2 Input Clock Select
+ 'PCNF2_POME2': '$1', # PSC 2 Output Matrix Enable
+ 'OCR2RB' : '$f8', # Output Compare RB Register
+ 'OCR2SB' : '$f6', # Output Compare SB Register
+ 'OCR2RA' : '$f4', # Output Compare RA Register
+ 'OCR2SA' : '$f2', # Output Compare SA Register
+ 'POM2' : '$f1', # PSC 2 Output Matrix
+ 'POM2_POMV2B': '$f0', # Output Matrix Output B Ramps
+ 'POM2_POMV2A': '$f', # Output Matrix Output A Ramps
+ 'PSOC2' : '$f0', # PSC2 Synchro and Output Config
+ 'PSOC2_POS2': '$c0', # PSC 2 Output 23 Select
+ 'PSOC2_PSYNC2_': '$30', # Synchronization Out for ADC Se
+ 'PSOC2_POEN2D': '$8', # PSCOUT23 Output Enable
+ 'PSOC2_POEN2B': '$4', # PSCOUT21 Output Enable
+ 'PSOC2_POEN2C': '$2', # PSCOUT22 Output Enable
+ 'PSOC2_POEN2A': '$1', # PSCOUT20 Output Enable
+ 'PIM2' : '$a5', # PSC2 Interrupt Mask Register
+ 'PIM2_PSEIE2': '$20', # PSC 2 Synchro Error Interrupt
+ 'PIM2_PEVE2B': '$10', # External Event B Interrupt Ena
+ 'PIM2_PEVE2A': '$8', # External Event A Interrupt Ena
+ 'PIM2_PEOPE2': '$1', # End of Cycle Interrupt Enable
+ 'PIFR2' : '$a4', # PSC2 Interrupt Flag Register
+ 'PIFR2_POAC2B': '$80', # PSC 2 Output A Activity
+ 'PIFR2_POAC2A': '$40', # PSC 2 Output A Activity
+ 'PIFR2_PSEI2': '$20', # PSC 2 Synchro Error Interrupt
+ 'PIFR2_PEV2B': '$10', # External Event B Interrupt
+ 'PIFR2_PEV2A': '$8', # External Event A Interrupt
+ 'PIFR2_PRN2': '$6', # Ramp Number
+ 'PIFR2_PEOP2': '$1', # End of PSC2 Interrupt
+
+ '__amforth_dummy':'0'
+}
diff --git a/amforth-6.5/avr8/devices/at90pwm2b/words/no-jtag.asm b/amforth-6.5/avr8/devices/at90pwm2b/words/no-jtag.asm
new file mode 100644
index 0000000..352a4bb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90pwm2b/words/no-jtag.asm
@@ -0,0 +1,14 @@
+; ( -- )
+; ( -- )
+; MCU
+; disable jtag at runtime
+VE_NOJTAG:
+ .dw $FF05
+ .db "-jtag",0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOJTAG
+XT_NOJTAG:
+ .dw PFA_NOJTAG
+PFA_NOJTAG:
+
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/at90pwm2b/words/no-wdt.asm b/amforth-6.5/avr8/devices/at90pwm2b/words/no-wdt.asm
new file mode 100644
index 0000000..ff6ddd1
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90pwm2b/words/no-wdt.asm
@@ -0,0 +1,34 @@
+; ( -- )
+; MCU
+; disable watch dog timer at runtime
+VE_NOWDT:
+ .dw $ff04
+ .db "-wdt"
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOWDT
+XT_NOWDT:
+ .dw PFA_NOWDT
+PFA_NOWDT:
+
+ in temp1,SREG
+ push temp1
+ ; Turn always off global interrupt.
+ cli
+ ; Reset Watchdog Timer
+ wdr
+ ; Clear WDRF in MCUSR
+ in temp1, MCUSR
+ andi temp1, (0xff & (0<<WDRF))
+ out MCUSR, temp1
+ ; Write logical one to WDCE and WDE
+ ; Keep old prescaler setting to prevent unintentional time-out
+ in_ temp1, WDTCSR
+ ori temp1, (1<<WDCE) | (1<<WDE)
+ out_ WDTCSR, temp1
+ ; Turn off WDT
+ ldi temp1, (0<<WDE)
+ out_ WDTCSR, temp1
+ ; restore status register
+ pop temp1
+ out SREG,temp1
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/at90pwm2b/words/sleep.asm b/amforth-6.5/avr8/devices/at90pwm2b/words/sleep.asm
new file mode 100644
index 0000000..256249c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90pwm2b/words/sleep.asm
@@ -0,0 +1,19 @@
+; ( mode -- )
+; MCU
+; put the controller into the specified sleep mode
+VE_SLEEP:
+ .dw $ff05
+ .db "sleep", 0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_SLEEP
+XT_SLEEP:
+ .dw PFA_SLEEP
+PFA_SLEEP:
+ andi tosl, 7 ; leave only legal mode bits
+ lsl tosl ; move to correct location (bits 3-1)
+ ori tosl, 1 ; set the SE bit
+ out_ SMCR, tosl ; set the sleep config
+ sleep ; nighty-night
+ out_ SMCR, zerol ; 0 protects against accidental sleeps
+ loadtos ; pop argument from stack
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/at90pwm3/at90pwm3.frt b/amforth-6.5/avr8/devices/at90pwm3/at90pwm3.frt
new file mode 100644
index 0000000..b143f5d
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90pwm3/at90pwm3.frt
@@ -0,0 +1,217 @@
+\ Partname: AT90PWM3
+\ Built using part description XML file version 179
+\ generated automatically
+
+hex
+
+\ AD_CONVERTER
+79 constant ADCH \ ADC Data Register High Byte
+78 constant ADCL \ ADC Data Register Low Byte
+7A constant ADCSRA \ The ADC Control and Status register
+7B constant ADCSRB \ ADC Control and Status Register B
+7C constant ADMUX \ The ADC multiplexer Selection Register
+76 constant AMP0CSR \
+77 constant AMP1CSR \
+7E constant DIDR0 \ Digital Input Disable Register 0
+7F constant DIDR1 \ Digital Input Disable Register 0
+
+\ ANALOG_COMPARATOR
+AD constant AC0CON \ Analog Comparator 0 Control Register
+AE constant AC1CON \ Analog Comparator 1 Control Register
+AF constant AC2CON \ Analog Comparator 2 Control Register
+50 constant ACSR \ Analog Comparator Status Register
+
+\ BOOT_LOAD
+57 constant SPMCSR \ Store Program Memory Control Register
+
+\ CPU
+61 constant CLKPR \
+3E constant GPIOR0 \ General Purpose IO Register 0
+39 constant GPIOR1 \ General Purpose IO Register 1
+3A constant GPIOR2 \ General Purpose IO Register 2
+3B constant GPIOR3 \ General Purpose IO Register 3
+55 constant MCUCR \ MCU Control Register
+54 constant MCUSR \ MCU Status Register
+66 constant OSCCAL \ Oscillator Calibration Value
+49 constant PLLCSR \ PLL Control And Status Register
+64 constant PRR \ Power Reduction Register
+53 constant SMCR \ Sleep Mode Control Register
+5E constant SPH \ Stack Pointer High
+5D constant SPL \ Stack Pointer Low
+5F constant SREG \ Status Register
+
+\ DA_CONVERTER
+AC constant DACH \ DAC Data Register High Byte
+AB constant DACL \ DAC Data Register Low Byte
+AA constant DACON \ DAC Control Register
+
+\ EEPROM
+42 constant EEARH \ EEPROM Read/Write Access High Byte
+41 constant EEARL \ EEPROM Read/Write Access Low Byte
+3F constant EECR \ EEPROM Control Register
+40 constant EEDR \ EEPROM Data Register
+
+\ EUSART
+C8 constant EUCSRA \ EUSART Control and Status Register A
+C9 constant EUCSRB \ EUSART Control Register B
+CA constant EUCSRC \ EUSART Status Register C
+CE constant EUDR \ EUSART I/O Data Register
+CD constant MUBRRH \ Manchester Receiver Baud Rate Register High Byte
+CC constant MUBRRL \ Manchester Receiver Baud Rate Register Low Byte
+
+\ EXTERNAL_INTERRUPT
+69 constant EICRA \ External Interrupt Control Register A
+3C constant EIFR \ External Interrupt Flag Register
+3D constant EIMSK \ External Interrupt Mask Register
+
+\ PORTB
+24 constant DDRB \ Port B Data Direction Register
+23 constant PINB \ Port B Input Pins
+25 constant PORTB \ Port B Data Register
+
+\ PORTC
+27 constant DDRC \ Port C Data Direction Register
+26 constant PINC \ Port C Input Pins
+28 constant PORTC \ Port C Data Register
+
+\ PORTD
+2A constant DDRD \ Port D Data Direction Register
+29 constant PIND \ Port D Input Pins
+2B constant PORTD \ Port D Data Register
+
+\ PORTE
+2D constant DDRE \ Port E Data Direction Register
+2C constant PINE \ Port E Input Pins
+2E constant PORTE \ Port E Data Register
+
+\ PSC0
+D5 constant OCR0RAH \ Output Compare RA Register High
+D4 constant OCR0RAL \ Output Compare RA Register Low
+D9 constant OCR0RBH \ Output Compare RB Register High
+D8 constant OCR0RBL \ Output Compare RB Register Low
+D3 constant OCR0SAH \ Output Compare SA Register High
+D2 constant OCR0SAL \ Output Compare SA Register Low
+D7 constant OCR0SBH \ Output Compare SB Register High
+D6 constant OCR0SBL \ Output Compare SB Register Low
+DA constant PCNF0 \ PSC 0 Configuration Register
+DB constant PCTL0 \ PSC 0 Control Register
+DC constant PFRC0A \ PSC 0 Input A Control
+DD constant PFRC0B \ PSC 0 Input B Control
+DF constant PICR0H \ PSC 0 Input Capture Register High
+DE constant PICR0L \ PSC 0 Input Capture Register Low
+A0 constant PIFR0 \ PSC0 Interrupt Flag Register
+A1 constant PIM0 \ PSC0 Interrupt Mask Register
+D0 constant PSOC0 \ PSC0 Synchro and Output Configuration
+
+\ PSC1
+E5 constant OCR1RAH \ Output Compare RA Register High
+E4 constant OCR1RAL \ Output Compare RA Register Low
+E9 constant OCR1RBH \ Output Compare RB Register High
+E8 constant OCR1RBL \ Output Compare RB Register Low
+E3 constant OCR1SAH \ Output Compare SA Register High
+E2 constant OCR1SAL \ Output Compare SA Register Low
+E7 constant OCR1SBH \ Output Compare SB Register High
+E6 constant OCR1SBL \ Output Compare SB Register Low
+EA constant PCNF1 \ PSC 1 Configuration Register
+EB constant PCTL1 \ PSC 1 Control Register
+EC constant PFRC1A \ PSC 1 Input B Control
+ED constant PFRC1B \ PSC 1 Input B Control
+EF constant PICR1H \ PSC 1 Input Capture Register High
+EE constant PICR1L \ PSC 1 Input Capture Register Low
+A2 constant PIFR1 \ PSC1 Interrupt Flag Register
+A3 constant PIM1 \ PSC1 Interrupt Mask Register
+E0 constant PSOC1 \ PSC1 Synchro and Output Configuration
+
+\ PSC2
+F5 constant OCR2RAH \ Output Compare RA Register High
+F4 constant OCR2RAL \ Output Compare RA Register Low
+F9 constant OCR2RBH \ Output Compare RB Register High
+F8 constant OCR2RBL \ Output Compare RB Register Low
+F3 constant OCR2SAH \ Output Compare SA Register High
+F2 constant OCR2SAL \ Output Compare SA Register Low
+F7 constant OCR2SBH \ Output Compare SB Register High
+F6 constant OCR2SBL \ Output Compare SB Register Low
+FA constant PCNF2 \ PSC 2 Configuration Register
+FB constant PCTL2 \ PSC 2 Control Register
+FC constant PFRC2A \ PSC 2 Input B Control
+FD constant PFRC2B \ PSC 2 Input B Control
+FF constant PICR2H \ PSC 2 Input Capture Register High
+FE constant PICR2L \ PSC 2 Input Capture Register Low
+A4 constant PIFR2 \ PSC2 Interrupt Flag Register
+A5 constant PIM2 \ PSC2 Interrupt Mask Register
+F1 constant POM2 \ PSC 2 Output Matrix
+F0 constant PSOC2 \ PSC2 Synchro and Output Configuration
+
+\ SPI
+4C constant SPCR \ SPI Control Register
+4E constant SPDR \ SPI Data Register
+4D constant SPSR \ SPI Status Register
+
+\ TIMER_COUNTER_0
+43 constant GTCCR \ General Timer/Counter Control Register
+47 constant OCR0A \ Timer/Counter0 Output Compare Register
+48 constant OCR0B \ Timer/Counter0 Output Compare Register
+44 constant TCCR0A \ Timer/Counter Control Register A
+45 constant TCCR0B \ Timer/Counter Control Register B
+46 constant TCNT0 \ Timer/Counter0
+35 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
+6E constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
+
+\ TIMER_COUNTER_1
+87 constant ICR1H \ Timer/Counter1 Input Capture Register High Byte
+86 constant ICR1L \ Timer/Counter1 Input Capture Register Low Byte
+89 constant OCR1AH \ Timer/Counter1 Output Compare Register High Byte
+88 constant OCR1AL \ Timer/Counter1 Output Compare Register Low Byte
+8B constant OCR1BH \ Timer/Counter1 Output Compare Register High Byte
+8A constant OCR1BL \ Timer/Counter1 Output Compare Register Low Byte
+80 constant TCCR1A \ Timer/Counter1 Control Register A
+81 constant TCCR1B \ Timer/Counter1 Control Register B
+82 constant TCCR1C \ Timer/Counter1 Control Register C
+85 constant TCNT1H \ Timer/Counter1 High Byte
+84 constant TCNT1L \ Timer/Counter1 Low Byte
+36 constant TIFR1 \ Timer/Counter Interrupt Flag register
+6F constant TIMSK1 \ Timer/Counter Interrupt Mask Register
+
+\ USART
+C5 constant UBRRH \ USART Baud Rate Register High Byte
+C4 constant UBRRL \ USART Baud Rate Register Low Byte
+C0 constant UCSRA \ USART Control and Status register A
+C1 constant UCSRB \ USART Control an Status register B
+C2 constant UCSRC \ USART Control an Status register C
+C6 constant UDR \ USART I/O Data Register
+
+\ WATCHDOG
+60 constant WDTCSR \ Watchdog Timer Control Register
+
+\ Interrupts
+0001 constant PSC2_CAPTAddr \ PSC2 Capture Event
+0002 constant PSC2_ECAddr \ PSC2 End Cycle
+0003 constant PSC1_CAPTAddr \ PSC1 Capture Event
+0004 constant PSC1_ECAddr \ PSC1 End Cycle
+0005 constant PSC0_CAPTAddr \ PSC0 Capture Event
+0006 constant PSC0_ECAddr \ PSC0 End Cycle
+0007 constant ANALOG_COMP_0Addr \ Analog Comparator 0
+0008 constant ANALOG_COMP_1Addr \ Analog Comparator 1
+0009 constant ANALOG_COMP_2Addr \ Analog Comparator 2
+000A constant INT0Addr \ External Interrupt Request 0
+000B constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+000C constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
+000D constant TIMER1_COMPBAddr \ Timer/Counter Compare Match B
+000E constant RESERVED15Addr \
+000F constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+0010 constant TIMER0_COMP_AAddr \ Timer/Counter0 Compare Match A
+0011 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
+0012 constant ADCAddr \ ADC Conversion Complete
+0013 constant INT1Addr \ External Interrupt Request 1
+0014 constant SPI_STCAddr \ SPI Serial Transfer Complete
+0015 constant USART_RXAddr \ USART, Rx Complete
+0016 constant USART_UDREAddr \ USART Data Register Empty
+0017 constant USART_TXAddr \ USART, Tx Complete
+0018 constant INT2Addr \ External Interrupt Request 2
+0019 constant WDTAddr \ Watchdog Timeout Interrupt
+001A constant EE_READYAddr \ EEPROM Ready
+001B constant TIMER0_COMPBAddr \ Timer Counter 0 Compare Match B
+001C constant INT3Addr \ External Interrupt Request 3
+001D constant RESERVED30Addr \
+001E constant RESERVED31Addr \
+001F constant SPM_READYAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/at90pwm3/device.asm b/amforth-6.5/avr8/devices/at90pwm3/device.asm
new file mode 100644
index 0000000..3386fce
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90pwm3/device.asm
@@ -0,0 +1,139 @@
+; Partname: AT90PWM3
+; Built using part description XML file version 179
+; generated automatically, do not edit
+
+.nolist
+ .include "pwm3def.inc"
+.list
+
+.equ ramstart = $0100
+.equ CELLSIZE = 2
+.macro readflashcell
+ lsl zl
+ rol zh
+ lpm @0, Z+
+ lpm @1, Z+
+.endmacro
+.macro writeflashcell
+ lsl zl
+ rol zh
+.endmacro
+
+; the following definitions are shortcuts for the respective forth source segments if set to 1
+.set WANT_AD_CONVERTER = 0
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_BOOT_LOAD = 0
+.set WANT_CPU = 0
+.set WANT_DA_CONVERTER = 0
+.set WANT_EEPROM = 0
+.set WANT_EUSART = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_PORTB = 0
+.set WANT_PORTC = 0
+.set WANT_PORTD = 0
+.set WANT_PORTE = 0
+.set WANT_PSC0 = 0
+.set WANT_PSC1 = 0
+.set WANT_PSC2 = 0
+.set WANT_SPI = 0
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_USART = 0
+.set WANT_WATCHDOG = 0
+
+
+.ifndef SPMEN
+ .equ SPMEN = SELFPRGEN
+.endif
+
+.ifndef SPMCSR
+ .equ SPMCSR = SPMCR
+.endif
+
+.ifndef EEPE
+ .equ EEPE = EEWE
+.endif
+
+.ifndef EEMPE
+ .equ EEMPE = EEMWE
+.endif
+.equ intvecsize = 1 ; please verify; flash size: 8192 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.equ INTVECTORS = 32
+.org $0001
+ rcall isr ; PSC2 Capture Event
+.org $0002
+ rcall isr ; PSC2 End Cycle
+.org $0003
+ rcall isr ; PSC1 Capture Event
+.org $0004
+ rcall isr ; PSC1 End Cycle
+.org $0005
+ rcall isr ; PSC0 Capture Event
+.org $0006
+ rcall isr ; PSC0 End Cycle
+.org $0007
+ rcall isr ; Analog Comparator 0
+.org $0008
+ rcall isr ; Analog Comparator 1
+.org $0009
+ rcall isr ; Analog Comparator 2
+.org $000A
+ rcall isr ; External Interrupt Request 0
+.org $000B
+ rcall isr ; Timer/Counter1 Capture Event
+.org $000C
+ rcall isr ; Timer/Counter1 Compare Match A
+.org $000D
+ rcall isr ; Timer/Counter Compare Match B
+.org $000E
+ rcall isr ;
+.org $000F
+ rcall isr ; Timer/Counter1 Overflow
+.org $0010
+ rcall isr ; Timer/Counter0 Compare Match A
+.org $0011
+ rcall isr ; Timer/Counter0 Overflow
+.org $0012
+ rcall isr ; ADC Conversion Complete
+.org $0013
+ rcall isr ; External Interrupt Request 1
+.org $0014
+ rcall isr ; SPI Serial Transfer Complete
+.org $0015
+ rcall isr ; USART, Rx Complete
+.org $0016
+ rcall isr ; USART Data Register Empty
+.org $0017
+ rcall isr ; USART, Tx Complete
+.org $0018
+ rcall isr ; External Interrupt Request 2
+.org $0019
+ rcall isr ; Watchdog Timeout Interrupt
+.org $001A
+ rcall isr ; EEPROM Ready
+.org $001B
+ rcall isr ; Timer Counter 0 Compare Match B
+.org $001C
+ rcall isr ; External Interrupt Request 3
+.org $001D
+ rcall isr ;
+.org $001E
+ rcall isr ;
+.org $001F
+ rcall isr ; Store Program Memory Read
+.nooverlap
+mcu_info:
+mcu_ramsize:
+ .dw 512
+mcu_eepromsize:
+ .dw 512
+mcu_maxdp:
+ .dw 3072 ; minimum of 0xC00 (from XML) and 0xffff
+mcu_numints:
+ .dw 32
+mcu_name:
+ .dw 8
+ .db "AT90PWM3"
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/at90pwm3/device.inc b/amforth-6.5/avr8/devices/at90pwm3/device.inc
new file mode 100644
index 0000000..6240e36
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90pwm3/device.inc
@@ -0,0 +1,1791 @@
+; Partname: AT90PWM3
+; Built using part description XML file version 179
+; generated automatically, no not edit
+
+; ********
+.if WANT_AD_CONVERTER == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register High Byte
+VE_ADCH:
+ .dw $ff04
+ .db "ADCH"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCH
+XT_ADCH:
+ .dw PFA_DOVARIABLE
+PFA_ADCH:
+ .dw $79
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register Low Byte
+VE_ADCL:
+ .dw $ff04
+ .db "ADCL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCL
+XT_ADCL:
+ .dw PFA_DOVARIABLE
+PFA_ADCL:
+ .dw $78
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register
+VE_ADCSRA:
+ .dw $ff06
+ .db "ADCSRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRA
+XT_ADCSRA:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRA:
+ .dw $7A
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Control and Status Register B
+VE_ADCSRB:
+ .dw $ff06
+ .db "ADCSRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRB
+XT_ADCSRB:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRB:
+ .dw $7B
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC multiplexer Selection Register
+VE_ADMUX:
+ .dw $ff05
+ .db "ADMUX",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADMUX
+XT_ADMUX:
+ .dw PFA_DOVARIABLE
+PFA_ADMUX:
+ .dw $7C
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_AMP0CSR:
+ .dw $ff07
+ .db "AMP0CSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_AMP0CSR
+XT_AMP0CSR:
+ .dw PFA_DOVARIABLE
+PFA_AMP0CSR:
+ .dw $76
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_AMP1CSR:
+ .dw $ff07
+ .db "AMP1CSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_AMP1CSR
+XT_AMP1CSR:
+ .dw PFA_DOVARIABLE
+PFA_AMP1CSR:
+ .dw $77
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 0
+VE_DIDR0:
+ .dw $ff05
+ .db "DIDR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR0
+XT_DIDR0:
+ .dw PFA_DOVARIABLE
+PFA_DIDR0:
+ .dw $7E
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 0
+VE_DIDR1:
+ .dw $ff05
+ .db "DIDR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR1
+XT_DIDR1:
+ .dw PFA_DOVARIABLE
+PFA_DIDR1:
+ .dw $7F
+
+.endif
+
+; ********
+.if WANT_ANALOG_COMPARATOR == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator 0 Control Register
+VE_AC0CON:
+ .dw $ff06
+ .db "AC0CON"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_AC0CON
+XT_AC0CON:
+ .dw PFA_DOVARIABLE
+PFA_AC0CON:
+ .dw $AD
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator 1 Control Register
+VE_AC1CON:
+ .dw $ff06
+ .db "AC1CON"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_AC1CON
+XT_AC1CON:
+ .dw PFA_DOVARIABLE
+PFA_AC1CON:
+ .dw $AE
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator 2 Control Register
+VE_AC2CON:
+ .dw $ff06
+ .db "AC2CON"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_AC2CON
+XT_AC2CON:
+ .dw PFA_DOVARIABLE
+PFA_AC2CON:
+ .dw $AF
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw $50
+
+.endif
+
+; ********
+.if WANT_BOOT_LOAD == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control Register
+VE_SPMCSR:
+ .dw $ff06
+ .db "SPMCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCSR
+XT_SPMCSR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCSR:
+ .dw $57
+
+.endif
+
+; ********
+.if WANT_CPU == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_CLKPR:
+ .dw $ff05
+ .db "CLKPR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKPR
+XT_CLKPR:
+ .dw PFA_DOVARIABLE
+PFA_CLKPR:
+ .dw $61
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 0
+VE_GPIOR0:
+ .dw $ff06
+ .db "GPIOR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR0
+XT_GPIOR0:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR0:
+ .dw $3E
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 1
+VE_GPIOR1:
+ .dw $ff06
+ .db "GPIOR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR1
+XT_GPIOR1:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR1:
+ .dw $39
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 2
+VE_GPIOR2:
+ .dw $ff06
+ .db "GPIOR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR2
+XT_GPIOR2:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR2:
+ .dw $3A
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 3
+VE_GPIOR3:
+ .dw $ff06
+ .db "GPIOR3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR3
+XT_GPIOR3:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR3:
+ .dw $3B
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw $55
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Status Register
+VE_MCUSR:
+ .dw $ff05
+ .db "MCUSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUSR
+XT_MCUSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUSR:
+ .dw $54
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Calibration Value
+VE_OSCCAL:
+ .dw $ff06
+ .db "OSCCAL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSCCAL
+XT_OSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_OSCCAL:
+ .dw $66
+; ( -- addr ) System Constant
+; R( -- )
+; PLL Control And Status Register
+VE_PLLCSR:
+ .dw $ff06
+ .db "PLLCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PLLCSR
+XT_PLLCSR:
+ .dw PFA_DOVARIABLE
+PFA_PLLCSR:
+ .dw $49
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register
+VE_PRR:
+ .dw $ff03
+ .db "PRR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR
+XT_PRR:
+ .dw PFA_DOVARIABLE
+PFA_PRR:
+ .dw $64
+; ( -- addr ) System Constant
+; R( -- )
+; Sleep Mode Control Register
+VE_SMCR:
+ .dw $ff04
+ .db "SMCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SMCR
+XT_SMCR:
+ .dw PFA_DOVARIABLE
+PFA_SMCR:
+ .dw $53
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer High
+VE_SPH:
+ .dw $ff03
+ .db "SPH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPH
+XT_SPH:
+ .dw PFA_DOVARIABLE
+PFA_SPH:
+ .dw $5E
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer Low
+VE_SPL:
+ .dw $ff03
+ .db "SPL",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPL
+XT_SPL:
+ .dw PFA_DOVARIABLE
+PFA_SPL:
+ .dw $5D
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw $5F
+
+.endif
+
+; ********
+.if WANT_DA_CONVERTER == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; DAC Data Register High Byte
+VE_DACH:
+ .dw $ff04
+ .db "DACH"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DACH
+XT_DACH:
+ .dw PFA_DOVARIABLE
+PFA_DACH:
+ .dw $AC
+; ( -- addr ) System Constant
+; R( -- )
+; DAC Data Register Low Byte
+VE_DACL:
+ .dw $ff04
+ .db "DACL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DACL
+XT_DACL:
+ .dw PFA_DOVARIABLE
+PFA_DACL:
+ .dw $AB
+; ( -- addr ) System Constant
+; R( -- )
+; DAC Control Register
+VE_DACON:
+ .dw $ff05
+ .db "DACON",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DACON
+XT_DACON:
+ .dw PFA_DOVARIABLE
+PFA_DACON:
+ .dw $AA
+
+.endif
+
+; ********
+.if WANT_EEPROM == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Read/Write Access High Byte
+VE_EEARH:
+ .dw $ff05
+ .db "EEARH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEARH
+XT_EEARH:
+ .dw PFA_DOVARIABLE
+PFA_EEARH:
+ .dw $42
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Read/Write Access Low Byte
+VE_EEARL:
+ .dw $ff05
+ .db "EEARL",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEARL
+XT_EEARL:
+ .dw PFA_DOVARIABLE
+PFA_EEARL:
+ .dw $41
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw $3F
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw $40
+
+.endif
+
+; ********
+.if WANT_EUSART == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; EUSART Control and Status Register A
+VE_EUCSRA:
+ .dw $ff06
+ .db "EUCSRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EUCSRA
+XT_EUCSRA:
+ .dw PFA_DOVARIABLE
+PFA_EUCSRA:
+ .dw $C8
+; ( -- addr ) System Constant
+; R( -- )
+; EUSART Control Register B
+VE_EUCSRB:
+ .dw $ff06
+ .db "EUCSRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EUCSRB
+XT_EUCSRB:
+ .dw PFA_DOVARIABLE
+PFA_EUCSRB:
+ .dw $C9
+; ( -- addr ) System Constant
+; R( -- )
+; EUSART Status Register C
+VE_EUCSRC:
+ .dw $ff06
+ .db "EUCSRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EUCSRC
+XT_EUCSRC:
+ .dw PFA_DOVARIABLE
+PFA_EUCSRC:
+ .dw $CA
+; ( -- addr ) System Constant
+; R( -- )
+; EUSART I/O Data Register
+VE_EUDR:
+ .dw $ff04
+ .db "EUDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EUDR
+XT_EUDR:
+ .dw PFA_DOVARIABLE
+PFA_EUDR:
+ .dw $CE
+; ( -- addr ) System Constant
+; R( -- )
+; Manchester Receiver Baud Rate Register High Byte
+VE_MUBRRH:
+ .dw $ff06
+ .db "MUBRRH"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MUBRRH
+XT_MUBRRH:
+ .dw PFA_DOVARIABLE
+PFA_MUBRRH:
+ .dw $CD
+; ( -- addr ) System Constant
+; R( -- )
+; Manchester Receiver Baud Rate Register Low Byte
+VE_MUBRRL:
+ .dw $ff06
+ .db "MUBRRL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MUBRRL
+XT_MUBRRL:
+ .dw PFA_DOVARIABLE
+PFA_MUBRRL:
+ .dw $CC
+
+.endif
+
+; ********
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register A
+VE_EICRA:
+ .dw $ff05
+ .db "EICRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRA
+XT_EICRA:
+ .dw PFA_DOVARIABLE
+PFA_EICRA:
+ .dw $69
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Flag Register
+VE_EIFR:
+ .dw $ff04
+ .db "EIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIFR
+XT_EIFR:
+ .dw PFA_DOVARIABLE
+PFA_EIFR:
+ .dw $3C
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Mask Register
+VE_EIMSK:
+ .dw $ff05
+ .db "EIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIMSK
+XT_EIMSK:
+ .dw PFA_DOVARIABLE
+PFA_EIMSK:
+ .dw $3D
+
+.endif
+
+; ********
+.if WANT_PORTB == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw $24
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw $23
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw $25
+
+.endif
+
+; ********
+.if WANT_PORTC == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Direction Register
+VE_DDRC:
+ .dw $ff04
+ .db "DDRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRC
+XT_DDRC:
+ .dw PFA_DOVARIABLE
+PFA_DDRC:
+ .dw $27
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Input Pins
+VE_PINC:
+ .dw $ff04
+ .db "PINC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINC
+XT_PINC:
+ .dw PFA_DOVARIABLE
+PFA_PINC:
+ .dw $26
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Register
+VE_PORTC:
+ .dw $ff05
+ .db "PORTC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTC
+XT_PORTC:
+ .dw PFA_DOVARIABLE
+PFA_PORTC:
+ .dw $28
+
+.endif
+
+; ********
+.if WANT_PORTD == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw $2A
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw $29
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw $2B
+
+.endif
+
+; ********
+.if WANT_PORTE == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Port E Data Direction Register
+VE_DDRE:
+ .dw $ff04
+ .db "DDRE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRE
+XT_DDRE:
+ .dw PFA_DOVARIABLE
+PFA_DDRE:
+ .dw $2D
+; ( -- addr ) System Constant
+; R( -- )
+; Port E Input Pins
+VE_PINE:
+ .dw $ff04
+ .db "PINE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINE
+XT_PINE:
+ .dw PFA_DOVARIABLE
+PFA_PINE:
+ .dw $2C
+; ( -- addr ) System Constant
+; R( -- )
+; Port E Data Register
+VE_PORTE:
+ .dw $ff05
+ .db "PORTE",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTE
+XT_PORTE:
+ .dw PFA_DOVARIABLE
+PFA_PORTE:
+ .dw $2E
+
+.endif
+
+; ********
+.if WANT_PSC0 == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare RA Register High
+VE_OCR0RAH:
+ .dw $ff07
+ .db "OCR0RAH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0RAH
+XT_OCR0RAH:
+ .dw PFA_DOVARIABLE
+PFA_OCR0RAH:
+ .dw $D5
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare RA Register Low
+VE_OCR0RAL:
+ .dw $ff07
+ .db "OCR0RAL",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0RAL
+XT_OCR0RAL:
+ .dw PFA_DOVARIABLE
+PFA_OCR0RAL:
+ .dw $D4
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare RB Register High
+VE_OCR0RBH:
+ .dw $ff07
+ .db "OCR0RBH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0RBH
+XT_OCR0RBH:
+ .dw PFA_DOVARIABLE
+PFA_OCR0RBH:
+ .dw $D9
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare RB Register Low
+VE_OCR0RBL:
+ .dw $ff07
+ .db "OCR0RBL",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0RBL
+XT_OCR0RBL:
+ .dw PFA_DOVARIABLE
+PFA_OCR0RBL:
+ .dw $D8
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare SA Register High
+VE_OCR0SAH:
+ .dw $ff07
+ .db "OCR0SAH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0SAH
+XT_OCR0SAH:
+ .dw PFA_DOVARIABLE
+PFA_OCR0SAH:
+ .dw $D3
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare SA Register Low
+VE_OCR0SAL:
+ .dw $ff07
+ .db "OCR0SAL",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0SAL
+XT_OCR0SAL:
+ .dw PFA_DOVARIABLE
+PFA_OCR0SAL:
+ .dw $D2
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare SB Register High
+VE_OCR0SBH:
+ .dw $ff07
+ .db "OCR0SBH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0SBH
+XT_OCR0SBH:
+ .dw PFA_DOVARIABLE
+PFA_OCR0SBH:
+ .dw $D7
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare SB Register Low
+VE_OCR0SBL:
+ .dw $ff07
+ .db "OCR0SBL",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0SBL
+XT_OCR0SBL:
+ .dw PFA_DOVARIABLE
+PFA_OCR0SBL:
+ .dw $D6
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 0 Configuration Register
+VE_PCNF0:
+ .dw $ff05
+ .db "PCNF0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCNF0
+XT_PCNF0:
+ .dw PFA_DOVARIABLE
+PFA_PCNF0:
+ .dw $DA
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 0 Control Register
+VE_PCTL0:
+ .dw $ff05
+ .db "PCTL0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCTL0
+XT_PCTL0:
+ .dw PFA_DOVARIABLE
+PFA_PCTL0:
+ .dw $DB
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 0 Input A Control
+VE_PFRC0A:
+ .dw $ff06
+ .db "PFRC0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PFRC0A
+XT_PFRC0A:
+ .dw PFA_DOVARIABLE
+PFA_PFRC0A:
+ .dw $DC
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 0 Input B Control
+VE_PFRC0B:
+ .dw $ff06
+ .db "PFRC0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PFRC0B
+XT_PFRC0B:
+ .dw PFA_DOVARIABLE
+PFA_PFRC0B:
+ .dw $DD
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 0 Input Capture Register High
+VE_PICR0H:
+ .dw $ff06
+ .db "PICR0H"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PICR0H
+XT_PICR0H:
+ .dw PFA_DOVARIABLE
+PFA_PICR0H:
+ .dw $DF
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 0 Input Capture Register Low
+VE_PICR0L:
+ .dw $ff06
+ .db "PICR0L"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PICR0L
+XT_PICR0L:
+ .dw PFA_DOVARIABLE
+PFA_PICR0L:
+ .dw $DE
+; ( -- addr ) System Constant
+; R( -- )
+; PSC0 Interrupt Flag Register
+VE_PIFR0:
+ .dw $ff05
+ .db "PIFR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIFR0
+XT_PIFR0:
+ .dw PFA_DOVARIABLE
+PFA_PIFR0:
+ .dw $A0
+; ( -- addr ) System Constant
+; R( -- )
+; PSC0 Interrupt Mask Register
+VE_PIM0:
+ .dw $ff04
+ .db "PIM0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIM0
+XT_PIM0:
+ .dw PFA_DOVARIABLE
+PFA_PIM0:
+ .dw $A1
+; ( -- addr ) System Constant
+; R( -- )
+; PSC0 Synchro and Output Configuration
+VE_PSOC0:
+ .dw $ff05
+ .db "PSOC0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PSOC0
+XT_PSOC0:
+ .dw PFA_DOVARIABLE
+PFA_PSOC0:
+ .dw $D0
+
+.endif
+
+; ********
+.if WANT_PSC1 == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare RA Register High
+VE_OCR1RAH:
+ .dw $ff07
+ .db "OCR1RAH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1RAH
+XT_OCR1RAH:
+ .dw PFA_DOVARIABLE
+PFA_OCR1RAH:
+ .dw $E5
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare RA Register Low
+VE_OCR1RAL:
+ .dw $ff07
+ .db "OCR1RAL",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1RAL
+XT_OCR1RAL:
+ .dw PFA_DOVARIABLE
+PFA_OCR1RAL:
+ .dw $E4
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare RB Register High
+VE_OCR1RBH:
+ .dw $ff07
+ .db "OCR1RBH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1RBH
+XT_OCR1RBH:
+ .dw PFA_DOVARIABLE
+PFA_OCR1RBH:
+ .dw $E9
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare RB Register Low
+VE_OCR1RBL:
+ .dw $ff07
+ .db "OCR1RBL",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1RBL
+XT_OCR1RBL:
+ .dw PFA_DOVARIABLE
+PFA_OCR1RBL:
+ .dw $E8
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare SA Register High
+VE_OCR1SAH:
+ .dw $ff07
+ .db "OCR1SAH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1SAH
+XT_OCR1SAH:
+ .dw PFA_DOVARIABLE
+PFA_OCR1SAH:
+ .dw $E3
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare SA Register Low
+VE_OCR1SAL:
+ .dw $ff07
+ .db "OCR1SAL",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1SAL
+XT_OCR1SAL:
+ .dw PFA_DOVARIABLE
+PFA_OCR1SAL:
+ .dw $E2
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare SB Register High
+VE_OCR1SBH:
+ .dw $ff07
+ .db "OCR1SBH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1SBH
+XT_OCR1SBH:
+ .dw PFA_DOVARIABLE
+PFA_OCR1SBH:
+ .dw $E7
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare SB Register Low
+VE_OCR1SBL:
+ .dw $ff07
+ .db "OCR1SBL",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1SBL
+XT_OCR1SBL:
+ .dw PFA_DOVARIABLE
+PFA_OCR1SBL:
+ .dw $E6
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 1 Configuration Register
+VE_PCNF1:
+ .dw $ff05
+ .db "PCNF1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCNF1
+XT_PCNF1:
+ .dw PFA_DOVARIABLE
+PFA_PCNF1:
+ .dw $EA
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 1 Control Register
+VE_PCTL1:
+ .dw $ff05
+ .db "PCTL1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCTL1
+XT_PCTL1:
+ .dw PFA_DOVARIABLE
+PFA_PCTL1:
+ .dw $EB
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 1 Input B Control
+VE_PFRC1A:
+ .dw $ff06
+ .db "PFRC1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PFRC1A
+XT_PFRC1A:
+ .dw PFA_DOVARIABLE
+PFA_PFRC1A:
+ .dw $EC
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 1 Input B Control
+VE_PFRC1B:
+ .dw $ff06
+ .db "PFRC1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PFRC1B
+XT_PFRC1B:
+ .dw PFA_DOVARIABLE
+PFA_PFRC1B:
+ .dw $ED
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 1 Input Capture Register High
+VE_PICR1H:
+ .dw $ff06
+ .db "PICR1H"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PICR1H
+XT_PICR1H:
+ .dw PFA_DOVARIABLE
+PFA_PICR1H:
+ .dw $EF
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 1 Input Capture Register Low
+VE_PICR1L:
+ .dw $ff06
+ .db "PICR1L"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PICR1L
+XT_PICR1L:
+ .dw PFA_DOVARIABLE
+PFA_PICR1L:
+ .dw $EE
+; ( -- addr ) System Constant
+; R( -- )
+; PSC1 Interrupt Flag Register
+VE_PIFR1:
+ .dw $ff05
+ .db "PIFR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIFR1
+XT_PIFR1:
+ .dw PFA_DOVARIABLE
+PFA_PIFR1:
+ .dw $A2
+; ( -- addr ) System Constant
+; R( -- )
+; PSC1 Interrupt Mask Register
+VE_PIM1:
+ .dw $ff04
+ .db "PIM1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIM1
+XT_PIM1:
+ .dw PFA_DOVARIABLE
+PFA_PIM1:
+ .dw $A3
+; ( -- addr ) System Constant
+; R( -- )
+; PSC1 Synchro and Output Configuration
+VE_PSOC1:
+ .dw $ff05
+ .db "PSOC1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PSOC1
+XT_PSOC1:
+ .dw PFA_DOVARIABLE
+PFA_PSOC1:
+ .dw $E0
+
+.endif
+
+; ********
+.if WANT_PSC2 == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare RA Register High
+VE_OCR2RAH:
+ .dw $ff07
+ .db "OCR2RAH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2RAH
+XT_OCR2RAH:
+ .dw PFA_DOVARIABLE
+PFA_OCR2RAH:
+ .dw $F5
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare RA Register Low
+VE_OCR2RAL:
+ .dw $ff07
+ .db "OCR2RAL",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2RAL
+XT_OCR2RAL:
+ .dw PFA_DOVARIABLE
+PFA_OCR2RAL:
+ .dw $F4
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare RB Register High
+VE_OCR2RBH:
+ .dw $ff07
+ .db "OCR2RBH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2RBH
+XT_OCR2RBH:
+ .dw PFA_DOVARIABLE
+PFA_OCR2RBH:
+ .dw $F9
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare RB Register Low
+VE_OCR2RBL:
+ .dw $ff07
+ .db "OCR2RBL",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2RBL
+XT_OCR2RBL:
+ .dw PFA_DOVARIABLE
+PFA_OCR2RBL:
+ .dw $F8
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare SA Register High
+VE_OCR2SAH:
+ .dw $ff07
+ .db "OCR2SAH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2SAH
+XT_OCR2SAH:
+ .dw PFA_DOVARIABLE
+PFA_OCR2SAH:
+ .dw $F3
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare SA Register Low
+VE_OCR2SAL:
+ .dw $ff07
+ .db "OCR2SAL",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2SAL
+XT_OCR2SAL:
+ .dw PFA_DOVARIABLE
+PFA_OCR2SAL:
+ .dw $F2
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare SB Register High
+VE_OCR2SBH:
+ .dw $ff07
+ .db "OCR2SBH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2SBH
+XT_OCR2SBH:
+ .dw PFA_DOVARIABLE
+PFA_OCR2SBH:
+ .dw $F7
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare SB Register Low
+VE_OCR2SBL:
+ .dw $ff07
+ .db "OCR2SBL",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2SBL
+XT_OCR2SBL:
+ .dw PFA_DOVARIABLE
+PFA_OCR2SBL:
+ .dw $F6
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 2 Configuration Register
+VE_PCNF2:
+ .dw $ff05
+ .db "PCNF2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCNF2
+XT_PCNF2:
+ .dw PFA_DOVARIABLE
+PFA_PCNF2:
+ .dw $FA
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 2 Control Register
+VE_PCTL2:
+ .dw $ff05
+ .db "PCTL2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCTL2
+XT_PCTL2:
+ .dw PFA_DOVARIABLE
+PFA_PCTL2:
+ .dw $FB
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 2 Input B Control
+VE_PFRC2A:
+ .dw $ff06
+ .db "PFRC2A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PFRC2A
+XT_PFRC2A:
+ .dw PFA_DOVARIABLE
+PFA_PFRC2A:
+ .dw $FC
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 2 Input B Control
+VE_PFRC2B:
+ .dw $ff06
+ .db "PFRC2B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PFRC2B
+XT_PFRC2B:
+ .dw PFA_DOVARIABLE
+PFA_PFRC2B:
+ .dw $FD
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 2 Input Capture Register High
+VE_PICR2H:
+ .dw $ff06
+ .db "PICR2H"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PICR2H
+XT_PICR2H:
+ .dw PFA_DOVARIABLE
+PFA_PICR2H:
+ .dw $FF
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 2 Input Capture Register Low
+VE_PICR2L:
+ .dw $ff06
+ .db "PICR2L"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PICR2L
+XT_PICR2L:
+ .dw PFA_DOVARIABLE
+PFA_PICR2L:
+ .dw $FE
+; ( -- addr ) System Constant
+; R( -- )
+; PSC2 Interrupt Flag Register
+VE_PIFR2:
+ .dw $ff05
+ .db "PIFR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIFR2
+XT_PIFR2:
+ .dw PFA_DOVARIABLE
+PFA_PIFR2:
+ .dw $A4
+; ( -- addr ) System Constant
+; R( -- )
+; PSC2 Interrupt Mask Register
+VE_PIM2:
+ .dw $ff04
+ .db "PIM2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIM2
+XT_PIM2:
+ .dw PFA_DOVARIABLE
+PFA_PIM2:
+ .dw $A5
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 2 Output Matrix
+VE_POM2:
+ .dw $ff04
+ .db "POM2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_POM2
+XT_POM2:
+ .dw PFA_DOVARIABLE
+PFA_POM2:
+ .dw $F1
+; ( -- addr ) System Constant
+; R( -- )
+; PSC2 Synchro and Output Configuration
+VE_PSOC2:
+ .dw $ff05
+ .db "PSOC2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PSOC2
+XT_PSOC2:
+ .dw PFA_DOVARIABLE
+PFA_PSOC2:
+ .dw $F0
+
+.endif
+
+; ********
+.if WANT_SPI == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR:
+ .dw $ff04
+ .db "SPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR
+XT_SPCR:
+ .dw PFA_DOVARIABLE
+PFA_SPCR:
+ .dw $4C
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR:
+ .dw $ff04
+ .db "SPDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR
+XT_SPDR:
+ .dw PFA_DOVARIABLE
+PFA_SPDR:
+ .dw $4E
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR:
+ .dw $ff04
+ .db "SPSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR
+XT_SPSR:
+ .dw PFA_DOVARIABLE
+PFA_SPSR:
+ .dw $4D
+
+.endif
+
+; ********
+.if WANT_TIMER_COUNTER_0 == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; General Timer/Counter Control Register
+VE_GTCCR:
+ .dw $ff05
+ .db "GTCCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GTCCR
+XT_GTCCR:
+ .dw PFA_DOVARIABLE
+PFA_GTCCR:
+ .dw $43
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0A:
+ .dw $ff05
+ .db "OCR0A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0A
+XT_OCR0A:
+ .dw PFA_DOVARIABLE
+PFA_OCR0A:
+ .dw $47
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0B:
+ .dw $ff05
+ .db "OCR0B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0B
+XT_OCR0B:
+ .dw PFA_DOVARIABLE
+PFA_OCR0B:
+ .dw $48
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register A
+VE_TCCR0A:
+ .dw $ff06
+ .db "TCCR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0A
+XT_TCCR0A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0A:
+ .dw $44
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register B
+VE_TCCR0B:
+ .dw $ff06
+ .db "TCCR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0B
+XT_TCCR0B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0B:
+ .dw $45
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw $46
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Flag register
+VE_TIFR0:
+ .dw $ff05
+ .db "TIFR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR0
+XT_TIFR0:
+ .dw PFA_DOVARIABLE
+PFA_TIFR0:
+ .dw $35
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Mask Register
+VE_TIMSK0:
+ .dw $ff06
+ .db "TIMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK0
+XT_TIMSK0:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK0:
+ .dw $6E
+
+.endif
+
+; ********
+.if WANT_TIMER_COUNTER_1 == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register High Byte
+VE_ICR1H:
+ .dw $ff05
+ .db "ICR1H",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1H
+XT_ICR1H:
+ .dw PFA_DOVARIABLE
+PFA_ICR1H:
+ .dw $87
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Low Byte
+VE_ICR1L:
+ .dw $ff05
+ .db "ICR1L",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1L
+XT_ICR1L:
+ .dw PFA_DOVARIABLE
+PFA_ICR1L:
+ .dw $86
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register High Byte
+VE_OCR1AH:
+ .dw $ff06
+ .db "OCR1AH"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1AH
+XT_OCR1AH:
+ .dw PFA_DOVARIABLE
+PFA_OCR1AH:
+ .dw $89
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register Low Byte
+VE_OCR1AL:
+ .dw $ff06
+ .db "OCR1AL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1AL
+XT_OCR1AL:
+ .dw PFA_DOVARIABLE
+PFA_OCR1AL:
+ .dw $88
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register High Byte
+VE_OCR1BH:
+ .dw $ff06
+ .db "OCR1BH"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1BH
+XT_OCR1BH:
+ .dw PFA_DOVARIABLE
+PFA_OCR1BH:
+ .dw $8B
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register Low Byte
+VE_OCR1BL:
+ .dw $ff06
+ .db "OCR1BL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1BL
+XT_OCR1BL:
+ .dw PFA_DOVARIABLE
+PFA_OCR1BL:
+ .dw $8A
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw $80
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw $81
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register C
+VE_TCCR1C:
+ .dw $ff06
+ .db "TCCR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1C
+XT_TCCR1C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1C:
+ .dw $82
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 High Byte
+VE_TCNT1H:
+ .dw $ff06
+ .db "TCNT1H"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1H
+XT_TCNT1H:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1H:
+ .dw $85
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Low Byte
+VE_TCNT1L:
+ .dw $ff06
+ .db "TCNT1L"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1L
+XT_TCNT1L:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1L:
+ .dw $84
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Flag register
+VE_TIFR1:
+ .dw $ff05
+ .db "TIFR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR1
+XT_TIFR1:
+ .dw PFA_DOVARIABLE
+PFA_TIFR1:
+ .dw $36
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Mask Register
+VE_TIMSK1:
+ .dw $ff06
+ .db "TIMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK1
+XT_TIMSK1:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK1:
+ .dw $6F
+
+.endif
+
+; ********
+.if WANT_USART == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register High Byte
+VE_UBRRH:
+ .dw $ff05
+ .db "UBRRH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRRH
+XT_UBRRH:
+ .dw PFA_DOVARIABLE
+PFA_UBRRH:
+ .dw $C5
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Low Byte
+VE_UBRRL:
+ .dw $ff05
+ .db "UBRRL",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRRL
+XT_UBRRL:
+ .dw PFA_DOVARIABLE
+PFA_UBRRL:
+ .dw $C4
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status register A
+VE_UCSRA:
+ .dw $ff05
+ .db "UCSRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSRA
+XT_UCSRA:
+ .dw PFA_DOVARIABLE
+PFA_UCSRA:
+ .dw $C0
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control an Status register B
+VE_UCSRB:
+ .dw $ff05
+ .db "UCSRB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSRB
+XT_UCSRB:
+ .dw PFA_DOVARIABLE
+PFA_UCSRB:
+ .dw $C1
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control an Status register C
+VE_UCSRC:
+ .dw $ff05
+ .db "UCSRC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSRC
+XT_UCSRC:
+ .dw PFA_DOVARIABLE
+PFA_UCSRC:
+ .dw $C2
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR:
+ .dw $ff03
+ .db "UDR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR
+XT_UDR:
+ .dw PFA_DOVARIABLE
+PFA_UDR:
+ .dw $C6
+
+.endif
+
+; ********
+.if WANT_WATCHDOG == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCSR:
+ .dw $ff06
+ .db "WDTCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCSR
+XT_WDTCSR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCSR:
+ .dw $60
+
+.endif
diff --git a/amforth-6.5/avr8/devices/at90pwm3/device.py b/amforth-6.5/avr8/devices/at90pwm3/device.py
new file mode 100644
index 0000000..c300eee
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90pwm3/device.py
@@ -0,0 +1,175 @@
+# Partname: AT90PWM3
+# Built using part description XML file version 179
+# generated automatically, do not edit
+MCUREGS = {
+ 'ADCH': '$79',
+ 'ADCL': '$78',
+ 'ADCSRA': '$7A',
+ 'ADCSRB': '$7B',
+ 'ADMUX': '$7C',
+ 'AMP0CSR': '$76',
+ 'AMP1CSR': '$77',
+ 'DIDR0': '$7E',
+ 'DIDR1': '$7F',
+ 'AC0CON': '$AD',
+ 'AC1CON': '$AE',
+ 'AC2CON': '$AF',
+ 'ACSR': '$50',
+ 'SPMCSR': '$57',
+ 'CLKPR': '$61',
+ 'GPIOR0': '$3E',
+ 'GPIOR1': '$39',
+ 'GPIOR2': '$3A',
+ 'GPIOR3': '$3B',
+ 'MCUCR': '$55',
+ 'MCUSR': '$54',
+ 'OSCCAL': '$66',
+ 'PLLCSR': '$49',
+ 'PRR': '$64',
+ 'SMCR': '$53',
+ 'SPH': '$5E',
+ 'SPL': '$5D',
+ 'SREG': '$5F',
+ 'DACH': '$AC',
+ 'DACL': '$AB',
+ 'DACON': '$AA',
+ 'EEARH': '$42',
+ 'EEARL': '$41',
+ 'EECR': '$3F',
+ 'EEDR': '$40',
+ 'EUCSRA': '$C8',
+ 'EUCSRB': '$C9',
+ 'EUCSRC': '$CA',
+ 'EUDR': '$CE',
+ 'MUBRRH': '$CD',
+ 'MUBRRL': '$CC',
+ 'EICRA': '$69',
+ 'EIFR': '$3C',
+ 'EIMSK': '$3D',
+ 'DDRB': '$24',
+ 'PINB': '$23',
+ 'PORTB': '$25',
+ 'DDRC': '$27',
+ 'PINC': '$26',
+ 'PORTC': '$28',
+ 'DDRD': '$2A',
+ 'PIND': '$29',
+ 'PORTD': '$2B',
+ 'DDRE': '$2D',
+ 'PINE': '$2C',
+ 'PORTE': '$2E',
+ 'OCR0RAH': '$D5',
+ 'OCR0RAL': '$D4',
+ 'OCR0RBH': '$D9',
+ 'OCR0RBL': '$D8',
+ 'OCR0SAH': '$D3',
+ 'OCR0SAL': '$D2',
+ 'OCR0SBH': '$D7',
+ 'OCR0SBL': '$D6',
+ 'PCNF0': '$DA',
+ 'PCTL0': '$DB',
+ 'PFRC0A': '$DC',
+ 'PFRC0B': '$DD',
+ 'PICR0H': '$DF',
+ 'PICR0L': '$DE',
+ 'PIFR0': '$A0',
+ 'PIM0': '$A1',
+ 'PSOC0': '$D0',
+ 'OCR1RAH': '$E5',
+ 'OCR1RAL': '$E4',
+ 'OCR1RBH': '$E9',
+ 'OCR1RBL': '$E8',
+ 'OCR1SAH': '$E3',
+ 'OCR1SAL': '$E2',
+ 'OCR1SBH': '$E7',
+ 'OCR1SBL': '$E6',
+ 'PCNF1': '$EA',
+ 'PCTL1': '$EB',
+ 'PFRC1A': '$EC',
+ 'PFRC1B': '$ED',
+ 'PICR1H': '$EF',
+ 'PICR1L': '$EE',
+ 'PIFR1': '$A2',
+ 'PIM1': '$A3',
+ 'PSOC1': '$E0',
+ 'OCR2RAH': '$F5',
+ 'OCR2RAL': '$F4',
+ 'OCR2RBH': '$F9',
+ 'OCR2RBL': '$F8',
+ 'OCR2SAH': '$F3',
+ 'OCR2SAL': '$F2',
+ 'OCR2SBH': '$F7',
+ 'OCR2SBL': '$F6',
+ 'PCNF2': '$FA',
+ 'PCTL2': '$FB',
+ 'PFRC2A': '$FC',
+ 'PFRC2B': '$FD',
+ 'PICR2H': '$FF',
+ 'PICR2L': '$FE',
+ 'PIFR2': '$A4',
+ 'PIM2': '$A5',
+ 'POM2': '$F1',
+ 'PSOC2': '$F0',
+ 'SPCR': '$4C',
+ 'SPDR': '$4E',
+ 'SPSR': '$4D',
+ 'GTCCR': '$43',
+ 'OCR0A': '$47',
+ 'OCR0B': '$48',
+ 'TCCR0A': '$44',
+ 'TCCR0B': '$45',
+ 'TCNT0': '$46',
+ 'TIFR0': '$35',
+ 'TIMSK0': '$6E',
+ 'ICR1H': '$87',
+ 'ICR1L': '$86',
+ 'OCR1AH': '$89',
+ 'OCR1AL': '$88',
+ 'OCR1BH': '$8B',
+ 'OCR1BL': '$8A',
+ 'TCCR1A': '$80',
+ 'TCCR1B': '$81',
+ 'TCCR1C': '$82',
+ 'TCNT1H': '$85',
+ 'TCNT1L': '$84',
+ 'TIFR1': '$36',
+ 'TIMSK1': '$6F',
+ 'UBRRH': '$C5',
+ 'UBRRL': '$C4',
+ 'UCSRA': '$C0',
+ 'UCSRB': '$C1',
+ 'UCSRC': '$C2',
+ 'UDR': '$C6',
+ 'WDTCSR': '$60',
+ 'PSC2_CAPTAddr': '$0001',
+ 'PSC2_ECAddr': '$0002',
+ 'PSC1_CAPTAddr': '$0003',
+ 'PSC1_ECAddr': '$0004',
+ 'PSC0_CAPTAddr': '$0005',
+ 'PSC0_ECAddr': '$0006',
+ 'ANALOG_COMP_0Addr': '$0007',
+ 'ANALOG_COMP_1Addr': '$0008',
+ 'ANALOG_COMP_2Addr': '$0009',
+ 'INT0Addr': '$000A',
+ 'TIMER1_CAPTAddr': '$000B',
+ 'TIMER1_COMPAAddr': '$000C',
+ 'TIMER1_COMPBAddr': '$000D',
+ 'RESERVED15Addr': '$000E',
+ 'TIMER1_OVFAddr': '$000F',
+ 'TIMER0_COMP_AAddr': '$0010',
+ 'TIMER0_OVFAddr': '$0011',
+ 'ADCAddr': '$0012',
+ 'INT1Addr': '$0013',
+ 'SPI_STCAddr': '$0014',
+ 'USART_RXAddr': '$0015',
+ 'USART_UDREAddr': '$0016',
+ 'USART_TXAddr': '$0017',
+ 'INT2Addr': '$0018',
+ 'WDTAddr': '$0019',
+ 'EE_READYAddr': '$001A',
+ 'TIMER0_COMPBAddr': '$001B',
+ 'INT3Addr': '$001C',
+ 'RESERVED30Addr': '$001D',
+ 'RESERVED31Addr': '$001E',
+ 'SPM_READYAddr': '$001F'
+} \ No newline at end of file
diff --git a/amforth-6.5/avr8/devices/at90pwm316/at90pwm316.frt b/amforth-6.5/avr8/devices/at90pwm316/at90pwm316.frt
new file mode 100644
index 0000000..b31592b
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90pwm316/at90pwm316.frt
@@ -0,0 +1,478 @@
+\ Partname: AT90PWM316
+\ generated automatically
+
+\ PORTB
+&37 constant PORTB \ Port B Data Register
+&36 constant DDRB \ Port B Data Direction Register
+&35 constant PINB \ Port B Input Pins
+\ PORTC
+&40 constant PORTC \ Port C Data Register
+&39 constant DDRC \ Port C Data Direction Register
+&38 constant PINC \ Port C Input Pins
+\ PORTD
+&43 constant PORTD \ Port D Data Register
+&42 constant DDRD \ Port D Data Direction Register
+&41 constant PIND \ Port D Input Pins
+\ BOOT_LOAD
+&87 constant SPMCSR \ Store Program Memory Control Register
+ $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
+ $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
+ $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
+ $04 constant SPMCSR_PGWRT \ Page Write
+ $02 constant SPMCSR_PGERS \ Page Erase
+ $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
+\ EUSART
+&206 constant EUDR \ EUSART I/O Data Register
+&200 constant EUCSRA \ EUSART Control and Status Register A
+ $F0 constant EUCSRA_UTxS \ EUSART Control and Status Register A Bits
+ $0F constant EUCSRA_URxS \ EUSART Control and Status Register A Bits
+&201 constant EUCSRB \ EUSART Control Register B
+ $10 constant EUCSRB_EUSART \ EUSART Enable Bit
+ $08 constant EUCSRB_EUSBS \ EUSBS Enable Bit
+ $02 constant EUCSRB_EMCH \ Manchester Mode Bit
+ $01 constant EUCSRB_BODR \ Order Bit
+&202 constant EUCSRC \ EUSART Status Register C
+ $08 constant EUCSRC_FEM \ Frame Error Manchester Bit
+ $04 constant EUCSRC_F1617 \ F1617 Bit
+ $03 constant EUCSRC_STP \ Stop Bits
+&205 constant MUBRRH \ Manchester Receiver Baud Rate Register High Byte
+ $FF constant MUBRRH_MUBRR \ Manchester Receiver Baud Rate Register Bits
+&204 constant MUBRRL \ Manchester Receiver Baud Rate Register Low Byte
+ $FF constant MUBRRL_MUBRR \ Manchester Receiver Baud Rate Register Bits
+\ ANALOG_COMPARATOR
+&173 constant AC0CON \ Analog Comparator 0 Control Register
+ $80 constant AC0CON_AC0EN \ Analog Comparator 0 Enable Bit
+ $40 constant AC0CON_AC0IE \ Analog Comparator 0 Interrupt Enable Bit
+ $30 constant AC0CON_AC0IS \ Analog Comparator 0 Interrupt Select Bit
+ $07 constant AC0CON_AC0M \ Analog Comparator 0 Multiplexer Register
+&174 constant AC1CON \ Analog Comparator 1 Control Register
+ $80 constant AC1CON_AC1EN \ Analog Comparator 1 Enable Bit
+ $40 constant AC1CON_AC1IE \ Analog Comparator 1 Interrupt Enable Bit
+ $30 constant AC1CON_AC1IS \ Analog Comparator 1 Interrupt Select Bit
+ $08 constant AC1CON_AC1ICE \ Analog Comparator 1 Interrupt Capture Enable Bit
+ $07 constant AC1CON_AC1M \ Analog Comparator 1 Multiplexer Register
+&175 constant AC2CON \ Analog Comparator 2 Control Register
+ $80 constant AC2CON_AC2EN \ Analog Comparator 2 Enable Bit
+ $40 constant AC2CON_AC2IE \ Analog Comparator 2 Interrupt Enable Bit
+ $30 constant AC2CON_AC2IS \ Analog Comparator 2 Interrupt Select Bit
+ $07 constant AC2CON_AC2M \ Analog Comparator 2 Multiplexer Register
+&80 constant ACSR \ Analog Comparator Status Register
+ $80 constant ACSR_ACCKDIV \ Analog Comparator Clock Divider
+ $40 constant ACSR_AC2IF \ Analog Comparator 2 Interrupt Flag Bit
+ $20 constant ACSR_AC1IF \ Analog Comparator 1 Interrupt Flag Bit
+ $10 constant ACSR_AC0IF \ Analog Comparator 0 Interrupt Flag Bit
+ $04 constant ACSR_AC2O \ Analog Comparator 2 Output Bit
+ $02 constant ACSR_AC1O \ Analog Comparator 1 Output Bit
+ $01 constant ACSR_AC0O \ Analog Comparator 0 Output Bit
+\ DA_CONVERTER
+&172 constant DACH \ DAC Data Register High Byte
+ $FF constant DACH_DACH \ DAC Data Register High Byte Bits
+&171 constant DACL \ DAC Data Register Low Byte
+ $FF constant DACL_DACL \ DAC Data Register Low Byte Bits
+&170 constant DACON \ DAC Control Register
+ $80 constant DACON_DAATE \ DAC Auto Trigger Enable Bit
+ $70 constant DACON_DATS \ DAC Trigger Selection Bits
+ $04 constant DACON_DALA \ DAC Left Adjust
+ $01 constant DACON_DAEN \ DAC Enable Bit
+\ CPU
+&95 constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ $08 constant SREG_V \ Two's Complement Overflow Flag
+ $04 constant SREG_N \ Negative Flag
+ $02 constant SREG_Z \ Zero Flag
+ $01 constant SREG_C \ Carry Flag
+&93 constant SP \ Stack Pointer
+&85 constant MCUCR \ MCU Control Register
+ $80 constant MCUCR_SPIPS \ SPI Pin Select
+ $10 constant MCUCR_PUD \ Pull-up disable
+ $02 constant MCUCR_IVSEL \ Interrupt Vector Select
+ $01 constant MCUCR_IVCE \ Interrupt Vector Change Enable
+&84 constant MCUSR \ MCU Status Register
+ $08 constant MCUSR_WDRF \ Watchdog Reset Flag
+ $04 constant MCUSR_BORF \ Brown-out Reset Flag
+ $02 constant MCUSR_EXTRF \ External Reset Flag
+ $01 constant MCUSR_PORF \ Power-on reset flag
+&102 constant OSCCAL \ Oscillator Calibration Value
+&97 constant CLKPR \
+ $80 constant CLKPR_CLKPCE \
+ $0F constant CLKPR_CLKPS \
+&83 constant SMCR \ Sleep Mode Control Register
+ $0E constant SMCR_SM \ Sleep Mode Select bits
+ $01 constant SMCR_SE \ Sleep Enable
+&59 constant GPIOR3 \ General Purpose IO Register 3
+ $FF constant GPIOR3_GPIOR \ General Purpose IO Register 3 bis
+&58 constant GPIOR2 \ General Purpose IO Register 2
+ $FF constant GPIOR2_GPIOR \ General Purpose IO Register 2 bis
+&57 constant GPIOR1 \ General Purpose IO Register 1
+ $FF constant GPIOR1_GPIOR \ General Purpose IO Register 1 bis
+&62 constant GPIOR0 \ General Purpose IO Register 0
+ $80 constant GPIOR0_GPIOR07 \ General Purpose IO Register 0 bit 7
+ $40 constant GPIOR0_GPIOR06 \ General Purpose IO Register 0 bit 6
+ $20 constant GPIOR0_GPIOR05 \ General Purpose IO Register 0 bit 5
+ $10 constant GPIOR0_GPIOR04 \ General Purpose IO Register 0 bit 4
+ $08 constant GPIOR0_GPIOR03 \ General Purpose IO Register 0 bit 3
+ $04 constant GPIOR0_GPIOR02 \ General Purpose IO Register 0 bit 2
+ $02 constant GPIOR0_GPIOR01 \ General Purpose IO Register 0 bit 1
+ $01 constant GPIOR0_GPIOR00 \ General Purpose IO Register 0 bit 0
+&73 constant PLLCSR \ PLL Control And Status Register
+ $04 constant PLLCSR_PLLF \ PLL Factor
+ $02 constant PLLCSR_PLLE \ PLL Enable
+ $01 constant PLLCSR_PLOCK \ PLL Lock Detector
+&100 constant PRR \ Power Reduction Register
+ $E0 constant PRR_PRPSC \ Power Reduction PSC2
+ $10 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
+ $08 constant PRR_PRTIM0 \ Power Reduction Timer/Counter0
+ $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
+ $02 constant PRR_PRUSART0 \ Power Reduction USART
+ $01 constant PRR_PRADC \ Power Reduction ADC
+\ PORTE
+&46 constant PORTE \ Port E Data Register
+&45 constant DDRE \ Port E Data Direction Register
+&44 constant PINE \ Port E Input Pins
+\ TIMER_COUNTER_0
+&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
+ $04 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare Match B Interrupt Enable
+ $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match A Interrupt Enable
+ $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
+&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
+ $04 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare Flag 0B
+ $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0A
+ $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
+&68 constant TCCR0A \ Timer/Counter Control Register A
+ $C0 constant TCCR0A_COM0A \ Compare Output Mode, Phase Correct PWM Mode
+ $30 constant TCCR0A_COM0B \ Compare Output Mode, Fast PWm
+ $03 constant TCCR0A_WGM0 \ Waveform Generation Mode
+&69 constant TCCR0B \ Timer/Counter Control Register B
+ $80 constant TCCR0B_FOC0A \ Force Output Compare A
+ $40 constant TCCR0B_FOC0B \ Force Output Compare B
+ $08 constant TCCR0B_WGM02 \
+ $07 constant TCCR0B_CS0 \ Clock Select
+&70 constant TCNT0 \ Timer/Counter0
+&71 constant OCR0A \ Timer/Counter0 Output Compare Register
+&72 constant OCR0B \ Timer/Counter0 Output Compare Register
+&67 constant GTCCR \ General Timer/Counter Control Register
+ $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
+ $40 constant GTCCR_ICPSEL1 \ Timer1 Input Capture Selection Bit
+ $01 constant GTCCR_PSR10 \ Prescaler Reset Timer/Counter1 and Timer/Counter0
+\ TIMER_COUNTER_1
+&111 constant TIMSK1 \ Timer/Counter Interrupt Mask Register
+ $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
+ $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output CompareB Match Interrupt Enable
+ $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output CompareA Match Interrupt Enable
+ $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
+&54 constant TIFR1 \ Timer/Counter Interrupt Flag register
+ $20 constant TIFR1_ICF1 \ Input Capture Flag 1
+ $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
+ $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
+ $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
+&128 constant TCCR1A \ Timer/Counter1 Control Register A
+ $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
+ $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
+ $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
+&129 constant TCCR1B \ Timer/Counter1 Control Register B
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
+ $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
+&130 constant TCCR1C \ Timer/Counter1 Control Register C
+ $80 constant TCCR1C_FOC1A \
+ $40 constant TCCR1C_FOC1B \
+&132 constant TCNT1 \ Timer/Counter1 Bytes
+&136 constant OCR1A \ Timer/Counter1 Output Compare Register Bytes
+&138 constant OCR1B \ Timer/Counter1 Output Compare Register Bytes
+&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
+\ AD_CONVERTER
+&124 constant ADMUX \ The ADC multiplexer Selection Register
+ $C0 constant ADMUX_REFS \ Reference Selection Bits
+ $20 constant ADMUX_ADLAR \ Left Adjust Result
+ $0F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
+&122 constant ADCSRA \ The ADC Control and Status register
+ $80 constant ADCSRA_ADEN \ ADC Enable
+ $40 constant ADCSRA_ADSC \ ADC Start Conversion
+ $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
+ $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
+ $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
+ $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
+&120 constant ADC \ ADC Data Register Bytes
+&123 constant ADCSRB \ ADC Control and Status Register B
+&126 constant DIDR0 \ Digital Input Disable Register 0
+&127 constant DIDR1 \ Digital Input Disable Register 0
+ $20 constant DIDR1_ACMP0D \
+ $10 constant DIDR1_AMP0PD \
+ $08 constant DIDR1_AMP0ND \
+ $04 constant DIDR1_ADC10D \
+ $02 constant DIDR1_ADC9D \
+ $01 constant DIDR1_ADC8D \
+&118 constant AMP0CSR \
+ $80 constant AMP0CSR_AMP0EN \
+ $40 constant AMP0CSR_AMP0IS \
+ $30 constant AMP0CSR_AMP0G \
+ $03 constant AMP0CSR_AMP0TS \
+&119 constant AMP1CSR \
+ $80 constant AMP1CSR_AMP1EN \
+ $40 constant AMP1CSR_AMP1IS \
+ $30 constant AMP1CSR_AMP1G \
+ $03 constant AMP1CSR_AMP1TS \
+\ USART
+&198 constant UDR \ USART I/O Data Register
+&192 constant UCSRA \ USART Control and Status register A
+ $80 constant UCSRA_RXC \ USART Receive Complete
+ $40 constant UCSRA_TXC \ USART Transmitt Complete
+ $20 constant UCSRA_UDRE \ USART Data Register Empty
+ $10 constant UCSRA_FE \ Framing Error
+ $08 constant UCSRA_DOR \ Data Overrun
+ $04 constant UCSRA_UPE \ USART Parity Error
+ $02 constant UCSRA_U2X \ Double USART Transmission Bit
+ $01 constant UCSRA_MPCM \ Multi-processor Communication Mode
+&193 constant UCSRB \ USART Control an Status register B
+ $80 constant UCSRB_RXCIE \ RX Complete Interrupt Enable
+ $40 constant UCSRB_TXCIE \ TX Complete Interrupt Enable
+ $20 constant UCSRB_UDRIE \ USART Data Register Empty Interrupt Enable
+ $10 constant UCSRB_RXEN \ Receiver Enable
+ $08 constant UCSRB_TXEN \ Transmitter Enable
+ $04 constant UCSRB_UCSZ2 \ Character Size
+ $02 constant UCSRB_RXB8 \ Receive Data Bit 8
+ $01 constant UCSRB_TXB8 \ Transmit Data Bit 8
+&194 constant UCSRC \ USART Control an Status register C
+ $40 constant UCSRC_UMSEL0 \ USART Mode Select
+ $30 constant UCSRC_UPM \ Parity Mode Bits
+ $08 constant UCSRC_USBS \ Stop Bit Select
+ $06 constant UCSRC_UCSZ \ Character Size Bits
+ $01 constant UCSRC_UCPOL \ Clock Polarity
+&197 constant UBRRH \ USART Baud Rate Register High Byte
+ $0F constant UBRRH_UBRR \ USART Baud Rate Register Bits
+&196 constant UBRRL \ USART Baud Rate Register Low Byte
+ $FF constant UBRRL_UBRR \ USART Baud Rate Register bits
+\ SPI
+&76 constant SPCR \ SPI Control Register
+ $80 constant SPCR_SPIE \ SPI Interrupt Enable
+ $40 constant SPCR_SPE \ SPI Enable
+ $20 constant SPCR_DORD \ Data Order
+ $10 constant SPCR_MSTR \ Master/Slave Select
+ $08 constant SPCR_CPOL \ Clock polarity
+ $04 constant SPCR_CPHA \ Clock Phase
+ $03 constant SPCR_SPR \ SPI Clock Rate Selects
+&77 constant SPSR \ SPI Status Register
+ $80 constant SPSR_SPIF \ SPI Interrupt Flag
+ $40 constant SPSR_WCOL \ Write Collision Flag
+ $01 constant SPSR_SPI2X \ Double SPI Speed Bit
+&78 constant SPDR \ SPI Data Register
+\ WATCHDOG
+&96 constant WDTCSR \ Watchdog Timer Control Register
+ $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Flag
+ $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Enable
+ $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
+ $10 constant WDTCSR_WDCE \ Watchdog Change Enable
+ $08 constant WDTCSR_WDE \ Watch Dog Enable
+\ EXTERNAL_INTERRUPT
+&105 constant EICRA \ External Interrupt Control Register A
+ $C0 constant EICRA_ISC3 \ External Interrupt Sense Control Bit
+ $30 constant EICRA_ISC2 \ External Interrupt Sense Control Bit
+ $0C constant EICRA_ISC1 \ External Interrupt Sense Control Bit
+ $03 constant EICRA_ISC0 \ External Interrupt Sense Control Bit
+&61 constant EIMSK \ External Interrupt Mask Register
+ $0F constant EIMSK_INT \ External Interrupt Request 3 Enable
+&60 constant EIFR \ External Interrupt Flag Register
+ $0F constant EIFR_INTF \ External Interrupt Flags
+\ EEPROM
+&65 constant EEAR \ EEPROM Read/Write Access Bytes
+&64 constant EEDR \ EEPROM Data Register
+&63 constant EECR \ EEPROM Control Register
+ $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
+ $04 constant EECR_EEMWE \ EEPROM Master Write Enable
+ $02 constant EECR_EEWE \ EEPROM Write Enable
+ $01 constant EECR_EERE \ EEPROM Read Enable
+\ PSC0
+&222 constant PICR0 \ PSC 0 Input Capture Register
+&221 constant PFRC0B \ PSC 0 Input B Control
+ $80 constant PFRC0B_PCAE0B \ PSC 0 Capture Enable Input Part B
+ $40 constant PFRC0B_PISEL0B \ PSC 0 Input Select for Part B
+ $20 constant PFRC0B_PELEV0B \ PSC 0 Edge Level Selector on Input Part B
+ $10 constant PFRC0B_PFLTE0B \ PSC 0 Filter Enable on Input Part B
+ $0F constant PFRC0B_PRFM0B \ PSC 0 Retrigger and Fault Mode for Part B
+&220 constant PFRC0A \ PSC 0 Input A Control
+ $80 constant PFRC0A_PCAE0A \ PSC 0 Capture Enable Input Part A
+ $40 constant PFRC0A_PISEL0A \ PSC 0 Input Select for Part A
+ $20 constant PFRC0A_PELEV0A \ PSC 0 Edge Level Selector on Input Part A
+ $10 constant PFRC0A_PFLTE0A \ PSC 0 Filter Enable on Input Part A
+ $0F constant PFRC0A_PRFM0A \ PSC 0 Retrigger and Fault Mode for Part A
+&219 constant PCTL0 \ PSC 0 Control Register
+ $C0 constant PCTL0_PPRE0 \ PSC 0 Prescaler Selects
+ $20 constant PCTL0_PBFM0 \ PSC 0 Balance Flank Width Modulation
+ $10 constant PCTL0_PAOC0B \ PSC 0 Asynchronous Output Control B
+ $08 constant PCTL0_PAOC0A \ PSC 0 Asynchronous Output Control A
+ $04 constant PCTL0_PARUN0 \ PSC0 Auto Run
+ $02 constant PCTL0_PCCYC0 \ PSC0 Complete Cycle
+ $01 constant PCTL0_PRUN0 \ PSC 0 Run
+&218 constant PCNF0 \ PSC 0 Configuration Register
+ $80 constant PCNF0_PFIFTY0 \ PSC 0 Fifty
+ $40 constant PCNF0_PALOCK0 \ PSC 0 Autolock
+ $20 constant PCNF0_PLOCK0 \ PSC 0 Lock
+ $18 constant PCNF0_PMODE0 \ PSC 0 Mode
+ $04 constant PCNF0_POP0 \ PSC 0 Output Polarity
+ $02 constant PCNF0_PCLKSEL0 \ PSC 0 Input Clock Select
+&216 constant OCR0RB \ Output Compare RB Register
+&214 constant OCR0SB \ Output Compare SB Register
+&212 constant OCR0RA \ Output Compare RA Register
+&210 constant OCR0SA \ Output Compare SA Register
+&208 constant PSOC0 \ PSC0 Synchro and Output Configuration
+ $30 constant PSOC0_PSYNC0 \ Synchronization Out for ADC Selection
+ $04 constant PSOC0_POEN0B \ PSCOUT01 Output Enable
+ $01 constant PSOC0_POEN0A \ PSCOUT00 Output Enable
+&161 constant PIM0 \ PSC0 Interrupt Mask Register
+ $20 constant PIM0_PSEIE0 \ PSC 0 Synchro Error Interrupt Enable
+ $10 constant PIM0_PEVE0B \ External Event B Interrupt Enable
+ $08 constant PIM0_PEVE0A \ External Event A Interrupt Enable
+ $01 constant PIM0_PEOPE0 \ End of Cycle Interrupt Enable
+&160 constant PIFR0 \ PSC0 Interrupt Flag Register
+ $80 constant PIFR0_POAC0B \ PSC 0 Output A Activity
+ $40 constant PIFR0_POAC0A \ PSC 0 Output A Activity
+ $20 constant PIFR0_PSEI0 \ PSC 0 Synchro Error Interrupt
+ $10 constant PIFR0_PEV0B \ External Event B Interrupt
+ $08 constant PIFR0_PEV0A \ External Event A Interrupt
+ $06 constant PIFR0_PRN0 \ Ramp Number
+ $01 constant PIFR0_PEOP0 \ End of PSC0 Interrupt
+\ PSC1
+&238 constant PICR1 \ PSC 1 Input Capture Register
+&237 constant PFRC1B \ PSC 1 Input B Control
+ $80 constant PFRC1B_PCAE1B \ PSC 1 Capture Enable Input Part B
+ $40 constant PFRC1B_PISEL1B \ PSC 1 Input Select for Part B
+ $20 constant PFRC1B_PELEV1B \ PSC 1 Edge Level Selector on Input Part B
+ $10 constant PFRC1B_PFLTE1B \ PSC 1 Filter Enable on Input Part B
+ $0F constant PFRC1B_PRFM1B \ PSC 1 Retrigger and Fault Mode for Part B
+&236 constant PFRC1A \ PSC 1 Input B Control
+ $80 constant PFRC1A_PCAE1A \ PSC 1 Capture Enable Input Part A
+ $40 constant PFRC1A_PISEL1A \ PSC 1 Input Select for Part A
+ $20 constant PFRC1A_PELEV1A \ PSC 1 Edge Level Selector on Input Part A
+ $10 constant PFRC1A_PFLTE1A \ PSC 1 Filter Enable on Input Part A
+ $0F constant PFRC1A_PRFM1A \ PSC 1 Retrigger and Fault Mode for Part A
+&235 constant PCTL1 \ PSC 1 Control Register
+ $C0 constant PCTL1_PPRE1 \ PSC 1 Prescaler Selects
+ $20 constant PCTL1_PBFM1 \ Balance Flank Width Modulation
+ $10 constant PCTL1_PAOC1B \ PSC 1 Asynchronous Output Control B
+ $08 constant PCTL1_PAOC1A \ PSC 1 Asynchronous Output Control A
+ $04 constant PCTL1_PARUN1 \ PSC1 Auto Run
+ $02 constant PCTL1_PCCYC1 \ PSC1 Complete Cycle
+ $01 constant PCTL1_PRUN1 \ PSC 1 Run
+&234 constant PCNF1 \ PSC 1 Configuration Register
+ $80 constant PCNF1_PFIFTY1 \ PSC 1 Fifty
+ $40 constant PCNF1_PALOCK1 \ PSC 1 Autolock
+ $20 constant PCNF1_PLOCK1 \ PSC 1 Lock
+ $18 constant PCNF1_PMODE1 \ PSC 1 Mode
+ $04 constant PCNF1_POP1 \ PSC 1 Output Polarity
+ $02 constant PCNF1_PCLKSEL1 \ PSC 1 Input Clock Select
+&232 constant OCR1RB \ Output Compare RB Register
+&230 constant OCR1SB \ Output Compare SB Register
+&228 constant OCR1RA \ Output Compare RA Register
+&226 constant OCR1SA \ Output Compare SA Register
+&224 constant PSOC1 \ PSC1 Synchro and Output Configuration
+ $30 constant PSOC1_PSYNC1_ \ Synchronization Out for ADC Selection
+ $04 constant PSOC1_POEN1B \ PSCOUT11 Output Enable
+ $01 constant PSOC1_POEN1A \ PSCOUT10 Output Enable
+&163 constant PIM1 \ PSC1 Interrupt Mask Register
+ $20 constant PIM1_PSEIE1 \ PSC 1 Synchro Error Interrupt Enable
+ $10 constant PIM1_PEVE1B \ External Event B Interrupt Enable
+ $08 constant PIM1_PEVE1A \ External Event A Interrupt Enable
+ $01 constant PIM1_PEOPE1 \ End of Cycle Interrupt Enable
+&162 constant PIFR1 \ PSC1 Interrupt Flag Register
+ $80 constant PIFR1_POAC1B \ PSC 1 Output B Activity
+ $40 constant PIFR1_POAC1A \ PSC 1 Output A Activity
+ $20 constant PIFR1_PSEI1 \ PSC 1 Synchro Error Interrupt
+ $10 constant PIFR1_PEV1B \ External Event B Interrupt
+ $08 constant PIFR1_PEV1A \ External Event A Interrupt
+ $06 constant PIFR1_PRN1 \ Ramp Number
+ $01 constant PIFR1_PEOP1 \ End of PSC1 Interrupt
+\ PSC2
+&254 constant PICR2 \ PSC 2 Input Capture Register
+&253 constant PFRC2B \ PSC 2 Input B Control
+ $80 constant PFRC2B_PCAE2B \ PSC 2 Capture Enable Input Part B
+ $40 constant PFRC2B_PISEL2B \ PSC 2 Input Select for Part B
+ $20 constant PFRC2B_PELEV2B \ PSC 2 Edge Level Selector on Input Part B
+ $10 constant PFRC2B_PFLTE2B \ PSC 2 Filter Enable on Input Part B
+ $0F constant PFRC2B_PRFM2B \ PSC 2 Retrigger and Fault Mode for Part B
+&252 constant PFRC2A \ PSC 2 Input B Control
+ $80 constant PFRC2A_PCAE2A \ PSC 2 Capture Enable Input Part A
+ $40 constant PFRC2A_PISEL2A \ PSC 2 Input Select for Part A
+ $20 constant PFRC2A_PELEV2A \ PSC 2 Edge Level Selector on Input Part A
+ $10 constant PFRC2A_PFLTE2A \ PSC 2 Filter Enable on Input Part A
+ $0F constant PFRC2A_PRFM2A \ PSC 2 Retrigger and Fault Mode for Part A
+&251 constant PCTL2 \ PSC 2 Control Register
+ $C0 constant PCTL2_PPRE2 \ PSC 2 Prescaler Selects
+ $20 constant PCTL2_PBFM2 \ Balance Flank Width Modulation
+ $10 constant PCTL2_PAOC2B \ PSC 2 Asynchronous Output Control B
+ $08 constant PCTL2_PAOC2A \ PSC 2 Asynchronous Output Control A
+ $04 constant PCTL2_PARUN2 \ PSC2 Auto Run
+ $02 constant PCTL2_PCCYC2 \ PSC2 Complete Cycle
+ $01 constant PCTL2_PRUN2 \ PSC 2 Run
+&250 constant PCNF2 \ PSC 2 Configuration Register
+ $80 constant PCNF2_PFIFTY2 \ PSC 2 Fifty
+ $40 constant PCNF2_PALOCK2 \ PSC 2 Autolock
+ $20 constant PCNF2_PLOCK2 \ PSC 2 Lock
+ $18 constant PCNF2_PMODE2 \ PSC 2 Mode
+ $04 constant PCNF2_POP2 \ PSC 2 Output Polarity
+ $02 constant PCNF2_PCLKSEL2 \ PSC 2 Input Clock Select
+ $01 constant PCNF2_POME2 \ PSC 2 Output Matrix Enable
+&248 constant OCR2RB \ Output Compare RB Register
+&246 constant OCR2SB \ Output Compare SB Register
+&244 constant OCR2RA \ Output Compare RA Register
+&242 constant OCR2SA \ Output Compare SA Register
+&241 constant POM2 \ PSC 2 Output Matrix
+ $F0 constant POM2_POMV2B \ Output Matrix Output B Ramps
+ $0F constant POM2_POMV2A \ Output Matrix Output A Ramps
+&240 constant PSOC2 \ PSC2 Synchro and Output Configuration
+ $C0 constant PSOC2_POS2 \ PSC 2 Output 23 Select
+ $30 constant PSOC2_PSYNC2_ \ Synchronization Out for ADC Selection
+ $08 constant PSOC2_POEN2D \ PSCOUT23 Output Enable
+ $04 constant PSOC2_POEN2B \ PSCOUT21 Output Enable
+ $02 constant PSOC2_POEN2C \ PSCOUT22 Output Enable
+ $01 constant PSOC2_POEN2A \ PSCOUT20 Output Enable
+&165 constant PIM2 \ PSC2 Interrupt Mask Register
+ $20 constant PIM2_PSEIE2 \ PSC 2 Synchro Error Interrupt Enable
+ $10 constant PIM2_PEVE2B \ External Event B Interrupt Enable
+ $08 constant PIM2_PEVE2A \ External Event A Interrupt Enable
+ $01 constant PIM2_PEOPE2 \ End of Cycle Interrupt Enable
+&164 constant PIFR2 \ PSC2 Interrupt Flag Register
+ $80 constant PIFR2_POAC2B \ PSC 2 Output A Activity
+ $40 constant PIFR2_POAC2A \ PSC 2 Output A Activity
+ $20 constant PIFR2_PSEI2 \ PSC 2 Synchro Error Interrupt
+ $10 constant PIFR2_PEV2B \ External Event B Interrupt
+ $08 constant PIFR2_PEV2A \ External Event A Interrupt
+ $06 constant PIFR2_PRN2 \ Ramp Number
+ $01 constant PIFR2_PEOP2 \ End of PSC2 Interrupt
+
+\ Interrupts
+&2 constant PSC2_CAPTAddr \ PSC2 Capture Event
+&4 constant PSC2_ECAddr \ PSC2 End Cycle
+&6 constant PSC1_CAPTAddr \ PSC1 Capture Event
+&8 constant PSC1_ECAddr \ PSC1 End Cycle
+&10 constant PSC0_CAPTAddr \ PSC0 Capture Event
+&12 constant PSC0_ECAddr \ PSC0 End Cycle
+&14 constant ANALOG_COMP_0Addr \ Analog Comparator 0
+&16 constant ANALOG_COMP_1Addr \ Analog Comparator 1
+&18 constant ANALOG_COMP_2Addr \ Analog Comparator 2
+&20 constant INT0Addr \ External Interrupt Request 0
+&22 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+&24 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
+&26 constant TIMER1_COMPBAddr \ Timer/Counter Compare Match B
+&28 constant RESERVED15Addr \
+&30 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+&32 constant TIMER0_COMP_AAddr \ Timer/Counter0 Compare Match A
+&34 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
+&36 constant ADCAddr \ ADC Conversion Complete
+&38 constant INT1Addr \ External Interrupt Request 1
+&40 constant SPI__STCAddr \ SPI Serial Transfer Complete
+&42 constant USART__RXAddr \ USART, Rx Complete
+&44 constant USART__UDREAddr \ USART Data Register Empty
+&46 constant USART__TXAddr \ USART, Tx Complete
+&48 constant INT2Addr \ External Interrupt Request 2
+&50 constant WDTAddr \ Watchdog Timeout Interrupt
+&52 constant EE_READYAddr \ EEPROM Ready
+&54 constant TIMER0_COMPBAddr \ Timer Counter 0 Compare Match B
+&56 constant INT3Addr \ External Interrupt Request 3
+&58 constant RESERVED30Addr \
+&60 constant RESERVED31Addr \
+&62 constant SPM_READYAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/at90pwm316/device.asm b/amforth-6.5/avr8/devices/at90pwm316/device.asm
new file mode 100644
index 0000000..c36c5ad
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90pwm316/device.asm
@@ -0,0 +1,125 @@
+; Partname: AT90PWM316
+; generated automatically, do not edit
+
+.nolist
+ .include "pwm316def.inc"
+.list
+
+.equ ramstart = 256
+.equ CELLSIZE = 2
+.macro readflashcell
+ lsl zl
+ rol zh
+ lpm @0, Z+
+ lpm @1, Z+
+.endmacro
+.macro writeflashcell
+ lsl zl
+ rol zh
+.endmacro
+.set WANT_PORTB = 0
+.set WANT_PORTC = 0
+.set WANT_PORTD = 0
+.set WANT_BOOT_LOAD = 0
+.set WANT_EUSART = 0
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_DA_CONVERTER = 0
+.set WANT_CPU = 0
+.set WANT_PORTE = 0
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_AD_CONVERTER = 0
+.set WANT_USART = 0
+.set WANT_SPI = 0
+.set WANT_WATCHDOG = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_EEPROM = 0
+.set WANT_PSC0 = 0
+.set WANT_PSC1 = 0
+.set WANT_PSC2 = 0
+.equ intvecsize = 2 ; please verify; flash size: 16384 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.org 2
+ rcall isr ; PSC2 Capture Event
+.org 4
+ rcall isr ; PSC2 End Cycle
+.org 6
+ rcall isr ; PSC1 Capture Event
+.org 8
+ rcall isr ; PSC1 End Cycle
+.org 10
+ rcall isr ; PSC0 Capture Event
+.org 12
+ rcall isr ; PSC0 End Cycle
+.org 14
+ rcall isr ; Analog Comparator 0
+.org 16
+ rcall isr ; Analog Comparator 1
+.org 18
+ rcall isr ; Analog Comparator 2
+.org 20
+ rcall isr ; External Interrupt Request 0
+.org 22
+ rcall isr ; Timer/Counter1 Capture Event
+.org 24
+ rcall isr ; Timer/Counter1 Compare Match A
+.org 26
+ rcall isr ; Timer/Counter Compare Match B
+.org 28
+ rcall isr ;
+.org 30
+ rcall isr ; Timer/Counter1 Overflow
+.org 32
+ rcall isr ; Timer/Counter0 Compare Match A
+.org 34
+ rcall isr ; Timer/Counter0 Overflow
+.org 36
+ rcall isr ; ADC Conversion Complete
+.org 38
+ rcall isr ; External Interrupt Request 1
+.org 40
+ rcall isr ; SPI Serial Transfer Complete
+.org 42
+ rcall isr ; USART, Rx Complete
+.org 44
+ rcall isr ; USART Data Register Empty
+.org 46
+ rcall isr ; USART, Tx Complete
+.org 48
+ rcall isr ; External Interrupt Request 2
+.org 50
+ rcall isr ; Watchdog Timeout Interrupt
+.org 52
+ rcall isr ; EEPROM Ready
+.org 54
+ rcall isr ; Timer Counter 0 Compare Match B
+.org 56
+ rcall isr ; External Interrupt Request 3
+.org 58
+ rcall isr ;
+.org 60
+ rcall isr ;
+.org 62
+ rcall isr ; Store Program Memory Read
+.equ INTVECTORS = 32
+.nooverlap
+
+; compatability layer (maybe empty)
+.equ EEPE = EEWE
+.equ EEMPE = EEMWE
+
+; controller data area, environment query mcu-info
+mcu_info:
+mcu_ramsize:
+ .dw 1024
+mcu_eepromsize:
+ .dw 512
+mcu_maxdp:
+ .dw 12288
+mcu_numints:
+ .dw 32
+mcu_name:
+ .dw 10
+ .db "AT90PWM316"
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/at90pwm316/device.inc b/amforth-6.5/avr8/devices/at90pwm316/device.inc
new file mode 100644
index 0000000..b85c36d
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90pwm316/device.inc
@@ -0,0 +1,1467 @@
+; Partname: AT90PWM316
+; generated automatically, no not edit
+
+.if WANT_PORTB == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw 37
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw 36
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw 35
+
+.endif
+.if WANT_PORTC == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Register
+VE_PORTC:
+ .dw $ff05
+ .db "PORTC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTC
+XT_PORTC:
+ .dw PFA_DOVARIABLE
+PFA_PORTC:
+ .dw 40
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Direction Register
+VE_DDRC:
+ .dw $ff04
+ .db "DDRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRC
+XT_DDRC:
+ .dw PFA_DOVARIABLE
+PFA_DDRC:
+ .dw 39
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Input Pins
+VE_PINC:
+ .dw $ff04
+ .db "PINC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINC
+XT_PINC:
+ .dw PFA_DOVARIABLE
+PFA_PINC:
+ .dw 38
+
+.endif
+.if WANT_PORTD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw 43
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw 42
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw 41
+
+.endif
+.if WANT_BOOT_LOAD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control Register
+VE_SPMCSR:
+ .dw $ff06
+ .db "SPMCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCSR
+XT_SPMCSR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCSR:
+ .dw 87
+
+.endif
+.if WANT_EUSART == 1
+; ( -- addr ) System Constant
+; R( -- )
+; EUSART I/O Data Register
+VE_EUDR:
+ .dw $ff04
+ .db "EUDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EUDR
+XT_EUDR:
+ .dw PFA_DOVARIABLE
+PFA_EUDR:
+ .dw 206
+; ( -- addr ) System Constant
+; R( -- )
+; EUSART Control and Status Register A
+VE_EUCSRA:
+ .dw $ff06
+ .db "EUCSRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EUCSRA
+XT_EUCSRA:
+ .dw PFA_DOVARIABLE
+PFA_EUCSRA:
+ .dw 200
+; ( -- addr ) System Constant
+; R( -- )
+; EUSART Control Register B
+VE_EUCSRB:
+ .dw $ff06
+ .db "EUCSRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EUCSRB
+XT_EUCSRB:
+ .dw PFA_DOVARIABLE
+PFA_EUCSRB:
+ .dw 201
+; ( -- addr ) System Constant
+; R( -- )
+; EUSART Status Register C
+VE_EUCSRC:
+ .dw $ff06
+ .db "EUCSRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EUCSRC
+XT_EUCSRC:
+ .dw PFA_DOVARIABLE
+PFA_EUCSRC:
+ .dw 202
+; ( -- addr ) System Constant
+; R( -- )
+; Manchester Receiver Baud Rate Register High Byte
+VE_MUBRRH:
+ .dw $ff06
+ .db "MUBRRH"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MUBRRH
+XT_MUBRRH:
+ .dw PFA_DOVARIABLE
+PFA_MUBRRH:
+ .dw 205
+; ( -- addr ) System Constant
+; R( -- )
+; Manchester Receiver Baud Rate Register Low Byte
+VE_MUBRRL:
+ .dw $ff06
+ .db "MUBRRL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MUBRRL
+XT_MUBRRL:
+ .dw PFA_DOVARIABLE
+PFA_MUBRRL:
+ .dw 204
+
+.endif
+.if WANT_ANALOG_COMPARATOR == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator 0 Control Register
+VE_AC0CON:
+ .dw $ff06
+ .db "AC0CON"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_AC0CON
+XT_AC0CON:
+ .dw PFA_DOVARIABLE
+PFA_AC0CON:
+ .dw 173
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator 1 Control Register
+VE_AC1CON:
+ .dw $ff06
+ .db "AC1CON"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_AC1CON
+XT_AC1CON:
+ .dw PFA_DOVARIABLE
+PFA_AC1CON:
+ .dw 174
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator 2 Control Register
+VE_AC2CON:
+ .dw $ff06
+ .db "AC2CON"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_AC2CON
+XT_AC2CON:
+ .dw PFA_DOVARIABLE
+PFA_AC2CON:
+ .dw 175
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw 80
+
+.endif
+.if WANT_DA_CONVERTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; DAC Data Register High Byte
+VE_DACH:
+ .dw $ff04
+ .db "DACH"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DACH
+XT_DACH:
+ .dw PFA_DOVARIABLE
+PFA_DACH:
+ .dw 172
+; ( -- addr ) System Constant
+; R( -- )
+; DAC Data Register Low Byte
+VE_DACL:
+ .dw $ff04
+ .db "DACL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DACL
+XT_DACL:
+ .dw PFA_DOVARIABLE
+PFA_DACL:
+ .dw 171
+; ( -- addr ) System Constant
+; R( -- )
+; DAC Control Register
+VE_DACON:
+ .dw $ff05
+ .db "DACON",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DACON
+XT_DACON:
+ .dw PFA_DOVARIABLE
+PFA_DACON:
+ .dw 170
+
+.endif
+.if WANT_CPU == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw 95
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer
+VE_SP:
+ .dw $ff02
+ .db "SP"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SP
+XT_SP:
+ .dw PFA_DOVARIABLE
+PFA_SP:
+ .dw 93
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw 85
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Status Register
+VE_MCUSR:
+ .dw $ff05
+ .db "MCUSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUSR
+XT_MCUSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUSR:
+ .dw 84
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Calibration Value
+VE_OSCCAL:
+ .dw $ff06
+ .db "OSCCAL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSCCAL
+XT_OSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_OSCCAL:
+ .dw 102
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_CLKPR:
+ .dw $ff05
+ .db "CLKPR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKPR
+XT_CLKPR:
+ .dw PFA_DOVARIABLE
+PFA_CLKPR:
+ .dw 97
+; ( -- addr ) System Constant
+; R( -- )
+; Sleep Mode Control Register
+VE_SMCR:
+ .dw $ff04
+ .db "SMCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SMCR
+XT_SMCR:
+ .dw PFA_DOVARIABLE
+PFA_SMCR:
+ .dw 83
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 3
+VE_GPIOR3:
+ .dw $ff06
+ .db "GPIOR3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR3
+XT_GPIOR3:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR3:
+ .dw 59
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 2
+VE_GPIOR2:
+ .dw $ff06
+ .db "GPIOR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR2
+XT_GPIOR2:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR2:
+ .dw 58
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 1
+VE_GPIOR1:
+ .dw $ff06
+ .db "GPIOR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR1
+XT_GPIOR1:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR1:
+ .dw 57
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 0
+VE_GPIOR0:
+ .dw $ff06
+ .db "GPIOR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR0
+XT_GPIOR0:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR0:
+ .dw 62
+; ( -- addr ) System Constant
+; R( -- )
+; PLL Control And Status Register
+VE_PLLCSR:
+ .dw $ff06
+ .db "PLLCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PLLCSR
+XT_PLLCSR:
+ .dw PFA_DOVARIABLE
+PFA_PLLCSR:
+ .dw 73
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register
+VE_PRR:
+ .dw $ff03
+ .db "PRR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR
+XT_PRR:
+ .dw PFA_DOVARIABLE
+PFA_PRR:
+ .dw 100
+
+.endif
+.if WANT_PORTE == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port E Data Register
+VE_PORTE:
+ .dw $ff05
+ .db "PORTE",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTE
+XT_PORTE:
+ .dw PFA_DOVARIABLE
+PFA_PORTE:
+ .dw 46
+; ( -- addr ) System Constant
+; R( -- )
+; Port E Data Direction Register
+VE_DDRE:
+ .dw $ff04
+ .db "DDRE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRE
+XT_DDRE:
+ .dw PFA_DOVARIABLE
+PFA_DDRE:
+ .dw 45
+; ( -- addr ) System Constant
+; R( -- )
+; Port E Input Pins
+VE_PINE:
+ .dw $ff04
+ .db "PINE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINE
+XT_PINE:
+ .dw PFA_DOVARIABLE
+PFA_PINE:
+ .dw 44
+
+.endif
+.if WANT_TIMER_COUNTER_0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Mask Register
+VE_TIMSK0:
+ .dw $ff06
+ .db "TIMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK0
+XT_TIMSK0:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK0:
+ .dw 110
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Flag register
+VE_TIFR0:
+ .dw $ff05
+ .db "TIFR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR0
+XT_TIFR0:
+ .dw PFA_DOVARIABLE
+PFA_TIFR0:
+ .dw 53
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register A
+VE_TCCR0A:
+ .dw $ff06
+ .db "TCCR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0A
+XT_TCCR0A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0A:
+ .dw 68
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register B
+VE_TCCR0B:
+ .dw $ff06
+ .db "TCCR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0B
+XT_TCCR0B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0B:
+ .dw 69
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw 70
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0A:
+ .dw $ff05
+ .db "OCR0A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0A
+XT_OCR0A:
+ .dw PFA_DOVARIABLE
+PFA_OCR0A:
+ .dw 71
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0B:
+ .dw $ff05
+ .db "OCR0B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0B
+XT_OCR0B:
+ .dw PFA_DOVARIABLE
+PFA_OCR0B:
+ .dw 72
+; ( -- addr ) System Constant
+; R( -- )
+; General Timer/Counter Control Register
+VE_GTCCR:
+ .dw $ff05
+ .db "GTCCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GTCCR
+XT_GTCCR:
+ .dw PFA_DOVARIABLE
+PFA_GTCCR:
+ .dw 67
+
+.endif
+.if WANT_TIMER_COUNTER_1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Mask Register
+VE_TIMSK1:
+ .dw $ff06
+ .db "TIMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK1
+XT_TIMSK1:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK1:
+ .dw 111
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Flag register
+VE_TIFR1:
+ .dw $ff05
+ .db "TIFR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR1
+XT_TIFR1:
+ .dw PFA_DOVARIABLE
+PFA_TIFR1:
+ .dw 54
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw 128
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw 129
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register C
+VE_TCCR1C:
+ .dw $ff06
+ .db "TCCR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1C
+XT_TCCR1C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1C:
+ .dw 130
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Bytes
+VE_TCNT1:
+ .dw $ff05
+ .db "TCNT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1
+XT_TCNT1:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1:
+ .dw 132
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register Bytes
+VE_OCR1A:
+ .dw $ff05
+ .db "OCR1A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1A
+XT_OCR1A:
+ .dw PFA_DOVARIABLE
+PFA_OCR1A:
+ .dw 136
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register Bytes
+VE_OCR1B:
+ .dw $ff05
+ .db "OCR1B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1B
+XT_OCR1B:
+ .dw PFA_DOVARIABLE
+PFA_OCR1B:
+ .dw 138
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Bytes
+VE_ICR1:
+ .dw $ff04
+ .db "ICR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1
+XT_ICR1:
+ .dw PFA_DOVARIABLE
+PFA_ICR1:
+ .dw 134
+
+.endif
+.if WANT_AD_CONVERTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC multiplexer Selection Register
+VE_ADMUX:
+ .dw $ff05
+ .db "ADMUX",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADMUX
+XT_ADMUX:
+ .dw PFA_DOVARIABLE
+PFA_ADMUX:
+ .dw 124
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register
+VE_ADCSRA:
+ .dw $ff06
+ .db "ADCSRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRA
+XT_ADCSRA:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRA:
+ .dw 122
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register Bytes
+VE_ADC:
+ .dw $ff03
+ .db "ADC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADC
+XT_ADC:
+ .dw PFA_DOVARIABLE
+PFA_ADC:
+ .dw 120
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Control and Status Register B
+VE_ADCSRB:
+ .dw $ff06
+ .db "ADCSRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRB
+XT_ADCSRB:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRB:
+ .dw 123
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 0
+VE_DIDR0:
+ .dw $ff05
+ .db "DIDR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR0
+XT_DIDR0:
+ .dw PFA_DOVARIABLE
+PFA_DIDR0:
+ .dw 126
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 0
+VE_DIDR1:
+ .dw $ff05
+ .db "DIDR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR1
+XT_DIDR1:
+ .dw PFA_DOVARIABLE
+PFA_DIDR1:
+ .dw 127
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_AMP0CSR:
+ .dw $ff07
+ .db "AMP0CSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_AMP0CSR
+XT_AMP0CSR:
+ .dw PFA_DOVARIABLE
+PFA_AMP0CSR:
+ .dw 118
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_AMP1CSR:
+ .dw $ff07
+ .db "AMP1CSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_AMP1CSR
+XT_AMP1CSR:
+ .dw PFA_DOVARIABLE
+PFA_AMP1CSR:
+ .dw 119
+
+.endif
+.if WANT_USART == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR:
+ .dw $ff03
+ .db "UDR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR
+XT_UDR:
+ .dw PFA_DOVARIABLE
+PFA_UDR:
+ .dw 198
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status register A
+VE_UCSRA:
+ .dw $ff05
+ .db "UCSRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSRA
+XT_UCSRA:
+ .dw PFA_DOVARIABLE
+PFA_UCSRA:
+ .dw 192
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control an Status register B
+VE_UCSRB:
+ .dw $ff05
+ .db "UCSRB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSRB
+XT_UCSRB:
+ .dw PFA_DOVARIABLE
+PFA_UCSRB:
+ .dw 193
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control an Status register C
+VE_UCSRC:
+ .dw $ff05
+ .db "UCSRC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSRC
+XT_UCSRC:
+ .dw PFA_DOVARIABLE
+PFA_UCSRC:
+ .dw 194
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register High Byte
+VE_UBRRH:
+ .dw $ff05
+ .db "UBRRH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRRH
+XT_UBRRH:
+ .dw PFA_DOVARIABLE
+PFA_UBRRH:
+ .dw 197
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Low Byte
+VE_UBRRL:
+ .dw $ff05
+ .db "UBRRL",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRRL
+XT_UBRRL:
+ .dw PFA_DOVARIABLE
+PFA_UBRRL:
+ .dw 196
+
+.endif
+.if WANT_SPI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR:
+ .dw $ff04
+ .db "SPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR
+XT_SPCR:
+ .dw PFA_DOVARIABLE
+PFA_SPCR:
+ .dw 76
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR:
+ .dw $ff04
+ .db "SPSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR
+XT_SPSR:
+ .dw PFA_DOVARIABLE
+PFA_SPSR:
+ .dw 77
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR:
+ .dw $ff04
+ .db "SPDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR
+XT_SPDR:
+ .dw PFA_DOVARIABLE
+PFA_SPDR:
+ .dw 78
+
+.endif
+.if WANT_WATCHDOG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCSR:
+ .dw $ff06
+ .db "WDTCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCSR
+XT_WDTCSR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCSR:
+ .dw 96
+
+.endif
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register A
+VE_EICRA:
+ .dw $ff05
+ .db "EICRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRA
+XT_EICRA:
+ .dw PFA_DOVARIABLE
+PFA_EICRA:
+ .dw 105
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Mask Register
+VE_EIMSK:
+ .dw $ff05
+ .db "EIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIMSK
+XT_EIMSK:
+ .dw PFA_DOVARIABLE
+PFA_EIMSK:
+ .dw 61
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Flag Register
+VE_EIFR:
+ .dw $ff04
+ .db "EIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIFR
+XT_EIFR:
+ .dw PFA_DOVARIABLE
+PFA_EIFR:
+ .dw 60
+
+.endif
+.if WANT_EEPROM == 1
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Read/Write Access Bytes
+VE_EEAR:
+ .dw $ff04
+ .db "EEAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEAR
+XT_EEAR:
+ .dw PFA_DOVARIABLE
+PFA_EEAR:
+ .dw 65
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw 64
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw 63
+
+.endif
+.if WANT_PSC0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 0 Input Capture Register
+VE_PICR0:
+ .dw $ff05
+ .db "PICR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PICR0
+XT_PICR0:
+ .dw PFA_DOVARIABLE
+PFA_PICR0:
+ .dw 222
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 0 Input B Control
+VE_PFRC0B:
+ .dw $ff06
+ .db "PFRC0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PFRC0B
+XT_PFRC0B:
+ .dw PFA_DOVARIABLE
+PFA_PFRC0B:
+ .dw 221
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 0 Input A Control
+VE_PFRC0A:
+ .dw $ff06
+ .db "PFRC0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PFRC0A
+XT_PFRC0A:
+ .dw PFA_DOVARIABLE
+PFA_PFRC0A:
+ .dw 220
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 0 Control Register
+VE_PCTL0:
+ .dw $ff05
+ .db "PCTL0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCTL0
+XT_PCTL0:
+ .dw PFA_DOVARIABLE
+PFA_PCTL0:
+ .dw 219
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 0 Configuration Register
+VE_PCNF0:
+ .dw $ff05
+ .db "PCNF0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCNF0
+XT_PCNF0:
+ .dw PFA_DOVARIABLE
+PFA_PCNF0:
+ .dw 218
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare RB Register
+VE_OCR0RB:
+ .dw $ff06
+ .db "OCR0RB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0RB
+XT_OCR0RB:
+ .dw PFA_DOVARIABLE
+PFA_OCR0RB:
+ .dw 216
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare SB Register
+VE_OCR0SB:
+ .dw $ff06
+ .db "OCR0SB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0SB
+XT_OCR0SB:
+ .dw PFA_DOVARIABLE
+PFA_OCR0SB:
+ .dw 214
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare RA Register
+VE_OCR0RA:
+ .dw $ff06
+ .db "OCR0RA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0RA
+XT_OCR0RA:
+ .dw PFA_DOVARIABLE
+PFA_OCR0RA:
+ .dw 212
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare SA Register
+VE_OCR0SA:
+ .dw $ff06
+ .db "OCR0SA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0SA
+XT_OCR0SA:
+ .dw PFA_DOVARIABLE
+PFA_OCR0SA:
+ .dw 210
+; ( -- addr ) System Constant
+; R( -- )
+; PSC0 Synchro and Output Configuration
+VE_PSOC0:
+ .dw $ff05
+ .db "PSOC0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PSOC0
+XT_PSOC0:
+ .dw PFA_DOVARIABLE
+PFA_PSOC0:
+ .dw 208
+; ( -- addr ) System Constant
+; R( -- )
+; PSC0 Interrupt Mask Register
+VE_PIM0:
+ .dw $ff04
+ .db "PIM0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIM0
+XT_PIM0:
+ .dw PFA_DOVARIABLE
+PFA_PIM0:
+ .dw 161
+; ( -- addr ) System Constant
+; R( -- )
+; PSC0 Interrupt Flag Register
+VE_PIFR0:
+ .dw $ff05
+ .db "PIFR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIFR0
+XT_PIFR0:
+ .dw PFA_DOVARIABLE
+PFA_PIFR0:
+ .dw 160
+
+.endif
+.if WANT_PSC1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 1 Input Capture Register
+VE_PICR1:
+ .dw $ff05
+ .db "PICR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PICR1
+XT_PICR1:
+ .dw PFA_DOVARIABLE
+PFA_PICR1:
+ .dw 238
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 1 Input B Control
+VE_PFRC1B:
+ .dw $ff06
+ .db "PFRC1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PFRC1B
+XT_PFRC1B:
+ .dw PFA_DOVARIABLE
+PFA_PFRC1B:
+ .dw 237
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 1 Input B Control
+VE_PFRC1A:
+ .dw $ff06
+ .db "PFRC1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PFRC1A
+XT_PFRC1A:
+ .dw PFA_DOVARIABLE
+PFA_PFRC1A:
+ .dw 236
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 1 Control Register
+VE_PCTL1:
+ .dw $ff05
+ .db "PCTL1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCTL1
+XT_PCTL1:
+ .dw PFA_DOVARIABLE
+PFA_PCTL1:
+ .dw 235
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 1 Configuration Register
+VE_PCNF1:
+ .dw $ff05
+ .db "PCNF1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCNF1
+XT_PCNF1:
+ .dw PFA_DOVARIABLE
+PFA_PCNF1:
+ .dw 234
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare RB Register
+VE_OCR1RB:
+ .dw $ff06
+ .db "OCR1RB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1RB
+XT_OCR1RB:
+ .dw PFA_DOVARIABLE
+PFA_OCR1RB:
+ .dw 232
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare SB Register
+VE_OCR1SB:
+ .dw $ff06
+ .db "OCR1SB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1SB
+XT_OCR1SB:
+ .dw PFA_DOVARIABLE
+PFA_OCR1SB:
+ .dw 230
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare RA Register
+VE_OCR1RA:
+ .dw $ff06
+ .db "OCR1RA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1RA
+XT_OCR1RA:
+ .dw PFA_DOVARIABLE
+PFA_OCR1RA:
+ .dw 228
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare SA Register
+VE_OCR1SA:
+ .dw $ff06
+ .db "OCR1SA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1SA
+XT_OCR1SA:
+ .dw PFA_DOVARIABLE
+PFA_OCR1SA:
+ .dw 226
+; ( -- addr ) System Constant
+; R( -- )
+; PSC1 Synchro and Output Configuration
+VE_PSOC1:
+ .dw $ff05
+ .db "PSOC1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PSOC1
+XT_PSOC1:
+ .dw PFA_DOVARIABLE
+PFA_PSOC1:
+ .dw 224
+; ( -- addr ) System Constant
+; R( -- )
+; PSC1 Interrupt Mask Register
+VE_PIM1:
+ .dw $ff04
+ .db "PIM1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIM1
+XT_PIM1:
+ .dw PFA_DOVARIABLE
+PFA_PIM1:
+ .dw 163
+; ( -- addr ) System Constant
+; R( -- )
+; PSC1 Interrupt Flag Register
+VE_PIFR1:
+ .dw $ff05
+ .db "PIFR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIFR1
+XT_PIFR1:
+ .dw PFA_DOVARIABLE
+PFA_PIFR1:
+ .dw 162
+
+.endif
+.if WANT_PSC2 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 2 Input Capture Register
+VE_PICR2:
+ .dw $ff05
+ .db "PICR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PICR2
+XT_PICR2:
+ .dw PFA_DOVARIABLE
+PFA_PICR2:
+ .dw 254
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 2 Input B Control
+VE_PFRC2B:
+ .dw $ff06
+ .db "PFRC2B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PFRC2B
+XT_PFRC2B:
+ .dw PFA_DOVARIABLE
+PFA_PFRC2B:
+ .dw 253
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 2 Input B Control
+VE_PFRC2A:
+ .dw $ff06
+ .db "PFRC2A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PFRC2A
+XT_PFRC2A:
+ .dw PFA_DOVARIABLE
+PFA_PFRC2A:
+ .dw 252
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 2 Control Register
+VE_PCTL2:
+ .dw $ff05
+ .db "PCTL2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCTL2
+XT_PCTL2:
+ .dw PFA_DOVARIABLE
+PFA_PCTL2:
+ .dw 251
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 2 Configuration Register
+VE_PCNF2:
+ .dw $ff05
+ .db "PCNF2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCNF2
+XT_PCNF2:
+ .dw PFA_DOVARIABLE
+PFA_PCNF2:
+ .dw 250
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare RB Register
+VE_OCR2RB:
+ .dw $ff06
+ .db "OCR2RB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2RB
+XT_OCR2RB:
+ .dw PFA_DOVARIABLE
+PFA_OCR2RB:
+ .dw 248
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare SB Register
+VE_OCR2SB:
+ .dw $ff06
+ .db "OCR2SB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2SB
+XT_OCR2SB:
+ .dw PFA_DOVARIABLE
+PFA_OCR2SB:
+ .dw 246
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare RA Register
+VE_OCR2RA:
+ .dw $ff06
+ .db "OCR2RA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2RA
+XT_OCR2RA:
+ .dw PFA_DOVARIABLE
+PFA_OCR2RA:
+ .dw 244
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare SA Register
+VE_OCR2SA:
+ .dw $ff06
+ .db "OCR2SA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2SA
+XT_OCR2SA:
+ .dw PFA_DOVARIABLE
+PFA_OCR2SA:
+ .dw 242
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 2 Output Matrix
+VE_POM2:
+ .dw $ff04
+ .db "POM2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_POM2
+XT_POM2:
+ .dw PFA_DOVARIABLE
+PFA_POM2:
+ .dw 241
+; ( -- addr ) System Constant
+; R( -- )
+; PSC2 Synchro and Output Configuration
+VE_PSOC2:
+ .dw $ff05
+ .db "PSOC2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PSOC2
+XT_PSOC2:
+ .dw PFA_DOVARIABLE
+PFA_PSOC2:
+ .dw 240
+; ( -- addr ) System Constant
+; R( -- )
+; PSC2 Interrupt Mask Register
+VE_PIM2:
+ .dw $ff04
+ .db "PIM2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIM2
+XT_PIM2:
+ .dw PFA_DOVARIABLE
+PFA_PIM2:
+ .dw 165
+; ( -- addr ) System Constant
+; R( -- )
+; PSC2 Interrupt Flag Register
+VE_PIFR2:
+ .dw $ff05
+ .db "PIFR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIFR2
+XT_PIFR2:
+ .dw PFA_DOVARIABLE
+PFA_PIFR2:
+ .dw 164
+
+.endif
diff --git a/amforth-6.5/avr8/devices/at90pwm316/device.py b/amforth-6.5/avr8/devices/at90pwm316/device.py
new file mode 100644
index 0000000..233602f
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90pwm316/device.py
@@ -0,0 +1,505 @@
+# Generated Automatically
+
+# Partname AT90PWM316
+
+MCUREGS = {
+# Interrupt Vectors
+ 'PSC2_CAPTAddr' : '#2', # PSC2 Capture Event
+ 'PSC2_ECAddr' : '#4', # PSC2 End Cycle
+ 'PSC1_CAPTAddr' : '#6', # PSC1 Capture Event
+ 'PSC1_ECAddr' : '#8', # PSC1 End Cycle
+ 'PSC0_CAPTAddr' : '#10', # PSC0 Capture Event
+ 'PSC0_ECAddr' : '#12', # PSC0 End Cycle
+ 'ANALOG_COMP_0Addr' : '#14', # Analog Comparator 0
+ 'ANALOG_COMP_1Addr' : '#16', # Analog Comparator 1
+ 'ANALOG_COMP_2Addr' : '#18', # Analog Comparator 2
+ 'INT0Addr' : '#20', # External Interrupt Request 0
+ 'TIMER1_CAPTAddr' : '#22', # Timer/Counter1 Capture Event
+ 'TIMER1_COMPAAddr' : '#24', # Timer/Counter1 Compare Match A
+ 'TIMER1_COMPBAddr' : '#26', # Timer/Counter Compare Match B
+ 'RESERVED15Addr' : '#28', #
+ 'TIMER1_OVFAddr' : '#30', # Timer/Counter1 Overflow
+ 'TIMER0_COMP_AAddr' : '#32', # Timer/Counter0 Compare Match A
+ 'TIMER0_OVFAddr' : '#34', # Timer/Counter0 Overflow
+ 'ADCAddr' : '#36', # ADC Conversion Complete
+ 'INT1Addr' : '#38', # External Interrupt Request 1
+ 'SPI_STCAddr' : '#40', # SPI Serial Transfer Complete
+ 'USART_RXAddr' : '#42', # USART, Rx Complete
+ 'USART_UDREAddr' : '#44', # USART Data Register Empty
+ 'USART_TXAddr' : '#46', # USART, Tx Complete
+ 'INT2Addr' : '#48', # External Interrupt Request 2
+ 'WDTAddr' : '#50', # Watchdog Timeout Interrupt
+ 'EE_READYAddr' : '#52', # EEPROM Ready
+ 'TIMER0_COMPBAddr' : '#54', # Timer Counter 0 Compare Match B
+ 'INT3Addr' : '#56', # External Interrupt Request 3
+ 'RESERVED30Addr' : '#58', #
+ 'RESERVED31Addr' : '#60', #
+ 'SPM_READYAddr' : '#62', # Store Program Memory Read
+
+# Module PORTB
+ 'PORTB' : '$25', # Port B Data Register
+ 'DDRB' : '$24', # Port B Data Direction Register
+ 'PINB' : '$23', # Port B Input Pins
+
+# Module PORTC
+ 'PORTC' : '$28', # Port C Data Register
+ 'DDRC' : '$27', # Port C Data Direction Register
+ 'PINC' : '$26', # Port C Input Pins
+
+# Module PORTD
+ 'PORTD' : '$2b', # Port D Data Register
+ 'DDRD' : '$2a', # Port D Data Direction Register
+ 'PIND' : '$29', # Port D Input Pins
+
+# Module BOOT_LOAD
+ 'SPMCSR' : '$57', # Store Program Memory Control R
+ 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
+ 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
+ 'SPMCSR_RWWSRE': '$10', # Read While Write section read
+ 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
+ 'SPMCSR_PGWRT': '$4', # Page Write
+ 'SPMCSR_PGERS': '$2', # Page Erase
+ 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
+
+# Module EUSART
+ 'EUDR' : '$ce', # EUSART I/O Data Register
+ 'EUCSRA' : '$c8', # EUSART Control and Status Regi
+ 'EUCSRA_UTxS': '$f0', # EUSART Control and Status Regi
+ 'EUCSRA_URxS': '$f', # EUSART Control and Status Regi
+ 'EUCSRB' : '$c9', # EUSART Control Register B
+ 'EUCSRB_EUSART': '$10', # EUSART Enable Bit
+ 'EUCSRB_EUSBS': '$8', # EUSBS Enable Bit
+ 'EUCSRB_EMCH': '$2', # Manchester Mode Bit
+ 'EUCSRB_BODR': '$1', # Order Bit
+ 'EUCSRC' : '$ca', # EUSART Status Register C
+ 'EUCSRC_FEM': '$8', # Frame Error Manchester Bit
+ 'EUCSRC_F1617': '$4', # F1617 Bit
+ 'EUCSRC_STP': '$3', # Stop Bits
+ 'MUBRRH' : '$cd', # Manchester Receiver Baud Rate
+ 'MUBRRH_MUBRR': '$ff', # Manchester Receiver Baud Rate
+ 'MUBRRL' : '$cc', # Manchester Receiver Baud Rate
+ 'MUBRRL_MUBRR': '$ff', # Manchester Receiver Baud Rate
+
+# Module ANALOG_COMPARATOR
+ 'AC0CON' : '$ad', # Analog Comparator 0 Control Re
+ 'AC0CON_AC0EN': '$80', # Analog Comparator 0 Enable Bit
+ 'AC0CON_AC0IE': '$40', # Analog Comparator 0 Interrupt
+ 'AC0CON_AC0IS': '$30', # Analog Comparator 0 Interrupt
+ 'AC0CON_AC0M': '$7', # Analog Comparator 0 Multiplexe
+ 'AC1CON' : '$ae', # Analog Comparator 1 Control Re
+ 'AC1CON_AC1EN': '$80', # Analog Comparator 1 Enable Bit
+ 'AC1CON_AC1IE': '$40', # Analog Comparator 1 Interrupt
+ 'AC1CON_AC1IS': '$30', # Analog Comparator 1 Interrupt
+ 'AC1CON_AC1ICE': '$8', # Analog Comparator 1 Interrupt
+ 'AC1CON_AC1M': '$7', # Analog Comparator 1 Multiplexe
+ 'AC2CON' : '$af', # Analog Comparator 2 Control Re
+ 'AC2CON_AC2EN': '$80', # Analog Comparator 2 Enable Bit
+ 'AC2CON_AC2IE': '$40', # Analog Comparator 2 Interrupt
+ 'AC2CON_AC2IS': '$30', # Analog Comparator 2 Interrupt
+ 'AC2CON_AC2M': '$7', # Analog Comparator 2 Multiplexe
+ 'ACSR' : '$50', # Analog Comparator Status Regis
+ 'ACSR_ACCKDIV': '$80', # Analog Comparator Clock Divide
+ 'ACSR_AC2IF': '$40', # Analog Comparator 2 Interrupt
+ 'ACSR_AC1IF': '$20', # Analog Comparator 1 Interrupt
+ 'ACSR_AC0IF': '$10', # Analog Comparator 0 Interrupt
+ 'ACSR_AC2O': '$4', # Analog Comparator 2 Output Bit
+ 'ACSR_AC1O': '$2', # Analog Comparator 1 Output Bit
+ 'ACSR_AC0O': '$1', # Analog Comparator 0 Output Bit
+
+# Module DA_CONVERTER
+ 'DACH' : '$ac', # DAC Data Register High Byte
+ 'DACH_DACH': '$ff', # DAC Data Register High Byte Bi
+ 'DACL' : '$ab', # DAC Data Register Low Byte
+ 'DACL_DACL': '$ff', # DAC Data Register Low Byte Bit
+ 'DACON' : '$aa', # DAC Control Register
+ 'DACON_DAATE': '$80', # DAC Auto Trigger Enable Bit
+ 'DACON_DATS': '$70', # DAC Trigger Selection Bits
+ 'DACON_DALA': '$4', # DAC Left Adjust
+ 'DACON_DAEN': '$1', # DAC Enable Bit
+
+# Module CPU
+ 'SREG' : '$5f', # Status Register
+ 'SREG_I': '$80', # Global Interrupt Enable
+ 'SREG_T': '$40', # Bit Copy Storage
+ 'SREG_H': '$20', # Half Carry Flag
+ 'SREG_S': '$10', # Sign Bit
+ 'SREG_V': '$8', # Two's Complement Overflow Flag
+ 'SREG_N': '$4', # Negative Flag
+ 'SREG_Z': '$2', # Zero Flag
+ 'SREG_C': '$1', # Carry Flag
+ 'SP' : '$5d', # Stack Pointer
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_SPIPS': '$80', # SPI Pin Select
+ 'MCUCR_PUD': '$10', # Pull-up disable
+ 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
+ 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
+ 'MCUSR_BORF': '$4', # Brown-out Reset Flag
+ 'MCUSR_EXTRF': '$2', # External Reset Flag
+ 'MCUSR_PORF': '$1', # Power-on reset flag
+ 'OSCCAL' : '$66', # Oscillator Calibration Value
+ 'CLKPR' : '$61', #
+ 'CLKPR_CLKPCE': '$80', #
+ 'CLKPR_CLKPS': '$f', #
+ 'SMCR' : '$53', # Sleep Mode Control Register
+ 'SMCR_SM': '$e', # Sleep Mode Select bits
+ 'SMCR_SE': '$1', # Sleep Enable
+ 'GPIOR3' : '$3b', # General Purpose IO Register 3
+ 'GPIOR3_GPIOR': '$ff', # General Purpose IO Register 3
+ 'GPIOR2' : '$3a', # General Purpose IO Register 2
+ 'GPIOR2_GPIOR': '$ff', # General Purpose IO Register 2
+ 'GPIOR1' : '$39', # General Purpose IO Register 1
+ 'GPIOR1_GPIOR': '$ff', # General Purpose IO Register 1
+ 'GPIOR0' : '$3e', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR07': '$80', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR06': '$40', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR05': '$20', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR04': '$10', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR03': '$8', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR02': '$4', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR01': '$2', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR00': '$1', # General Purpose IO Register 0
+ 'PLLCSR' : '$49', # PLL Control And Status Registe
+ 'PLLCSR_PLLF': '$4', # PLL Factor
+ 'PLLCSR_PLLE': '$2', # PLL Enable
+ 'PLLCSR_PLOCK': '$1', # PLL Lock Detector
+ 'PRR' : '$64', # Power Reduction Register
+ 'PRR_PRPSC': '$e0', # Power Reduction PSC2
+ 'PRR_PRTIM1': '$10', # Power Reduction Timer/Counter1
+ 'PRR_PRTIM0': '$8', # Power Reduction Timer/Counter0
+ 'PRR_PRSPI': '$4', # Power Reduction Serial Periphe
+ 'PRR_PRUSART0': '$2', # Power Reduction USART
+ 'PRR_PRADC': '$1', # Power Reduction ADC
+
+# Module PORTE
+ 'PORTE' : '$2e', # Port E Data Register
+ 'DDRE' : '$2d', # Port E Data Direction Register
+ 'PINE' : '$2c', # Port E Input Pins
+
+# Module TIMER_COUNTER_0
+ 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
+ 'TIMSK0_OCIE0B': '$4', # Timer/Counter0 Output Compare
+ 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
+ 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
+ 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
+ 'TIFR0_OCF0B': '$4', # Timer/Counter0 Output Compare
+ 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
+ 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
+ 'TCCR0A' : '$44', # Timer/Counter Control Registe
+ 'TCCR0A_COM0A': '$c0', # Compare Output Mode, Phase Cor
+ 'TCCR0A_COM0B': '$30', # Compare Output Mode, Fast PWm
+ 'TCCR0A_WGM0': '$3', # Waveform Generation Mode
+ 'TCCR0B' : '$45', # Timer/Counter Control Register
+ 'TCCR0B_FOC0A': '$80', # Force Output Compare A
+ 'TCCR0B_FOC0B': '$40', # Force Output Compare B
+ 'TCCR0B_WGM02': '$8', #
+ 'TCCR0B_CS0': '$7', # Clock Select
+ 'TCNT0' : '$46', # Timer/Counter0
+ 'OCR0A' : '$47', # Timer/Counter0 Output Compare
+ 'OCR0B' : '$48', # Timer/Counter0 Output Compare
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_ICPSEL1': '$40', # Timer1 Input Capture Selection
+ 'GTCCR_PSR10': '$1', # Prescaler Reset Timer/Counter1
+
+# Module TIMER_COUNTER_1
+ 'TIMSK1' : '$6f', # Timer/Counter Interrupt Mask R
+ 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
+ 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output CompareB
+ 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output CompareA
+ 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
+ 'TIFR1' : '$36', # Timer/Counter Interrupt Flag r
+ 'TIFR1_ICF1': '$20', # Input Capture Flag 1
+ 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
+ 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
+ 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
+ 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
+ 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
+ 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
+ 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
+ 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
+ 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
+ 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
+ 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
+ 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
+ 'TCCR1C' : '$82', # Timer/Counter1 Control Registe
+ 'TCCR1C_FOC1A': '$80', #
+ 'TCCR1C_FOC1B': '$40', #
+ 'TCNT1' : '$84', # Timer/Counter1 Bytes
+ 'OCR1A' : '$88', # Timer/Counter1 Output Compare
+ 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
+ 'ICR1' : '$86', # Timer/Counter1 Input Capture R
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSRSYNC': '$1', # Prescaler Reset Timer/Counter1
+
+# Module AD_CONVERTER
+ 'ADMUX' : '$7c', # The ADC multiplexer Selection
+ 'ADMUX_REFS': '$c0', # Reference Selection Bits
+ 'ADMUX_ADLAR': '$20', # Left Adjust Result
+ 'ADMUX_MUX': '$f', # Analog Channel and Gain Select
+ 'ADCSRA' : '$7a', # The ADC Control and Status reg
+ 'ADCSRA_ADEN': '$80', # ADC Enable
+ 'ADCSRA_ADSC': '$40', # ADC Start Conversion
+ 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
+ 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
+ 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
+ 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
+ 'ADC' : '$78', # ADC Data Register Bytes
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'DIDR0' : '$7e', # Digital Input Disable Register
+ 'DIDR1' : '$7f', # Digital Input Disable Register
+ 'DIDR1_ACMP0D': '$20', #
+ 'DIDR1_AMP0PD': '$10', #
+ 'DIDR1_AMP0ND': '$8', #
+ 'DIDR1_ADC10D': '$4', #
+ 'DIDR1_ADC9D': '$2', #
+ 'DIDR1_ADC8D': '$1', #
+ 'AMP0CSR' : '$76', #
+ 'AMP0CSR_AMP0EN': '$80', #
+ 'AMP0CSR_AMP0IS': '$40', #
+ 'AMP0CSR_AMP0G': '$30', #
+ 'AMP0CSR_AMP0TS': '$3', #
+ 'AMP1CSR' : '$77', #
+ 'AMP1CSR_AMP1EN': '$80', #
+ 'AMP1CSR_AMP1IS': '$40', #
+ 'AMP1CSR_AMP1G': '$30', #
+ 'AMP1CSR_AMP1TS': '$3', #
+
+# Module USART
+ 'UDR' : '$c6', # USART I/O Data Register
+ 'UCSRA' : '$c0', # USART Control and Status regis
+ 'UCSRA_RXC': '$80', # USART Receive Complete
+ 'UCSRA_TXC': '$40', # USART Transmitt Complete
+ 'UCSRA_UDRE': '$20', # USART Data Register Empty
+ 'UCSRA_FE': '$10', # Framing Error
+ 'UCSRA_DOR': '$8', # Data Overrun
+ 'UCSRA_UPE': '$4', # USART Parity Error
+ 'UCSRA_U2X': '$2', # Double USART Transmission Bit
+ 'UCSRA_MPCM': '$1', # Multi-processor Communication
+ 'UCSRB' : '$c1', # USART Control an Status regist
+ 'UCSRB_RXCIE': '$80', # RX Complete Interrupt Enable
+ 'UCSRB_TXCIE': '$40', # TX Complete Interrupt Enable
+ 'UCSRB_UDRIE': '$20', # USART Data Register Empty Inte
+ 'UCSRB_RXEN': '$10', # Receiver Enable
+ 'UCSRB_TXEN': '$8', # Transmitter Enable
+ 'UCSRB_UCSZ2': '$4', # Character Size
+ 'UCSRB_RXB8': '$2', # Receive Data Bit 8
+ 'UCSRB_TXB8': '$1', # Transmit Data Bit 8
+ 'UCSRC' : '$c2', # USART Control an Status regist
+ 'UCSRC_UMSEL0': '$40', # USART Mode Select
+ 'UCSRC_UPM': '$30', # Parity Mode Bits
+ 'UCSRC_USBS': '$8', # Stop Bit Select
+ 'UCSRC_UCSZ': '$6', # Character Size Bits
+ 'UCSRC_UCPOL': '$1', # Clock Polarity
+ 'UBRRH' : '$c5', # USART Baud Rate Register High
+ 'UBRRH_UBRR': '$f', # USART Baud Rate Register Bits
+ 'UBRRL' : '$c4', # USART Baud Rate Register Low B
+ 'UBRRL_UBRR': '$ff', # USART Baud Rate Register bits
+
+# Module SPI
+ 'SPCR' : '$4c', # SPI Control Register
+ 'SPCR_SPIE': '$80', # SPI Interrupt Enable
+ 'SPCR_SPE': '$40', # SPI Enable
+ 'SPCR_DORD': '$20', # Data Order
+ 'SPCR_MSTR': '$10', # Master/Slave Select
+ 'SPCR_CPOL': '$8', # Clock polarity
+ 'SPCR_CPHA': '$4', # Clock Phase
+ 'SPCR_SPR': '$3', # SPI Clock Rate Selects
+ 'SPSR' : '$4d', # SPI Status Register
+ 'SPSR_SPIF': '$80', # SPI Interrupt Flag
+ 'SPSR_WCOL': '$40', # Write Collision Flag
+ 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
+ 'SPDR' : '$4e', # SPI Data Register
+
+# Module WATCHDOG
+ 'WDTCSR' : '$60', # Watchdog Timer Control Registe
+ 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
+ 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
+ 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
+ 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
+ 'WDTCSR_WDE': '$8', # Watch Dog Enable
+
+# Module EXTERNAL_INTERRUPT
+ 'EICRA' : '$69', # External Interrupt Control Reg
+ 'EICRA_ISC3': '$c0', # External Interrupt Sense Contr
+ 'EICRA_ISC2': '$30', # External Interrupt Sense Contr
+ 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
+ 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
+ 'EIMSK' : '$3d', # External Interrupt Mask Regist
+ 'EIMSK_INT': '$f', # External Interrupt Request 3 E
+ 'EIFR' : '$3c', # External Interrupt Flag Regist
+ 'EIFR_INTF': '$f', # External Interrupt Flags
+
+# Module EEPROM
+ 'EEAR' : '$41', # EEPROM Read/Write Access Byte
+ 'EEDR' : '$40', # EEPROM Data Register
+ 'EECR' : '$3f', # EEPROM Control Register
+ 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
+ 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
+ 'EECR_EEWE': '$2', # EEPROM Write Enable
+ 'EECR_EERE': '$1', # EEPROM Read Enable
+
+# Module PSC0
+ 'PICR0' : '$de', # PSC 0 Input Capture Register
+ 'PFRC0B' : '$dd', # PSC 0 Input B Control
+ 'PFRC0B_PCAE0B': '$80', # PSC 0 Capture Enable Input Par
+ 'PFRC0B_PISEL0B': '$40', # PSC 0 Input Select for Part B
+ 'PFRC0B_PELEV0B': '$20', # PSC 0 Edge Level Selector on I
+ 'PFRC0B_PFLTE0B': '$10', # PSC 0 Filter Enable on Input P
+ 'PFRC0B_PRFM0B': '$f', # PSC 0 Retrigger and Fault Mode
+ 'PFRC0A' : '$dc', # PSC 0 Input A Control
+ 'PFRC0A_PCAE0A': '$80', # PSC 0 Capture Enable Input Par
+ 'PFRC0A_PISEL0A': '$40', # PSC 0 Input Select for Part A
+ 'PFRC0A_PELEV0A': '$20', # PSC 0 Edge Level Selector on I
+ 'PFRC0A_PFLTE0A': '$10', # PSC 0 Filter Enable on Input P
+ 'PFRC0A_PRFM0A': '$f', # PSC 0 Retrigger and Fault Mode
+ 'PCTL0' : '$db', # PSC 0 Control Register
+ 'PCTL0_PPRE0': '$c0', # PSC 0 Prescaler Selects
+ 'PCTL0_PBFM0': '$20', # PSC 0 Balance Flank Width Modu
+ 'PCTL0_PAOC0B': '$10', # PSC 0 Asynchronous Output Cont
+ 'PCTL0_PAOC0A': '$8', # PSC 0 Asynchronous Output Cont
+ 'PCTL0_PARUN0': '$4', # PSC0 Auto Run
+ 'PCTL0_PCCYC0': '$2', # PSC0 Complete Cycle
+ 'PCTL0_PRUN0': '$1', # PSC 0 Run
+ 'PCNF0' : '$da', # PSC 0 Configuration Register
+ 'PCNF0_PFIFTY0': '$80', # PSC 0 Fifty
+ 'PCNF0_PALOCK0': '$40', # PSC 0 Autolock
+ 'PCNF0_PLOCK0': '$20', # PSC 0 Lock
+ 'PCNF0_PMODE0': '$18', # PSC 0 Mode
+ 'PCNF0_POP0': '$4', # PSC 0 Output Polarity
+ 'PCNF0_PCLKSEL0': '$2', # PSC 0 Input Clock Select
+ 'OCR0RB' : '$d8', # Output Compare RB Register
+ 'OCR0SB' : '$d6', # Output Compare SB Register
+ 'OCR0RA' : '$d4', # Output Compare RA Register
+ 'OCR0SA' : '$d2', # Output Compare SA Register
+ 'PSOC0' : '$d0', # PSC0 Synchro and Output Config
+ 'PSOC0_PSYNC0': '$30', # Synchronization Out for ADC Se
+ 'PSOC0_POEN0B': '$4', # PSCOUT01 Output Enable
+ 'PSOC0_POEN0A': '$1', # PSCOUT00 Output Enable
+ 'PIM0' : '$a1', # PSC0 Interrupt Mask Register
+ 'PIM0_PSEIE0': '$20', # PSC 0 Synchro Error Interrupt
+ 'PIM0_PEVE0B': '$10', # External Event B Interrupt Ena
+ 'PIM0_PEVE0A': '$8', # External Event A Interrupt Ena
+ 'PIM0_PEOPE0': '$1', # End of Cycle Interrupt Enable
+ 'PIFR0' : '$a0', # PSC0 Interrupt Flag Register
+ 'PIFR0_POAC0B': '$80', # PSC 0 Output A Activity
+ 'PIFR0_POAC0A': '$40', # PSC 0 Output A Activity
+ 'PIFR0_PSEI0': '$20', # PSC 0 Synchro Error Interrupt
+ 'PIFR0_PEV0B': '$10', # External Event B Interrupt
+ 'PIFR0_PEV0A': '$8', # External Event A Interrupt
+ 'PIFR0_PRN0': '$6', # Ramp Number
+ 'PIFR0_PEOP0': '$1', # End of PSC0 Interrupt
+
+# Module PSC1
+ 'PICR1' : '$ee', # PSC 1 Input Capture Register
+ 'PFRC1B' : '$ed', # PSC 1 Input B Control
+ 'PFRC1B_PCAE1B': '$80', # PSC 1 Capture Enable Input Par
+ 'PFRC1B_PISEL1B': '$40', # PSC 1 Input Select for Part B
+ 'PFRC1B_PELEV1B': '$20', # PSC 1 Edge Level Selector on I
+ 'PFRC1B_PFLTE1B': '$10', # PSC 1 Filter Enable on Input P
+ 'PFRC1B_PRFM1B': '$f', # PSC 1 Retrigger and Fault Mode
+ 'PFRC1A' : '$ec', # PSC 1 Input B Control
+ 'PFRC1A_PCAE1A': '$80', # PSC 1 Capture Enable Input Par
+ 'PFRC1A_PISEL1A': '$40', # PSC 1 Input Select for Part A
+ 'PFRC1A_PELEV1A': '$20', # PSC 1 Edge Level Selector on I
+ 'PFRC1A_PFLTE1A': '$10', # PSC 1 Filter Enable on Input P
+ 'PFRC1A_PRFM1A': '$f', # PSC 1 Retrigger and Fault Mode
+ 'PCTL1' : '$eb', # PSC 1 Control Register
+ 'PCTL1_PPRE1': '$c0', # PSC 1 Prescaler Selects
+ 'PCTL1_PBFM1': '$20', # Balance Flank Width Modulation
+ 'PCTL1_PAOC1B': '$10', # PSC 1 Asynchronous Output Cont
+ 'PCTL1_PAOC1A': '$8', # PSC 1 Asynchronous Output Cont
+ 'PCTL1_PARUN1': '$4', # PSC1 Auto Run
+ 'PCTL1_PCCYC1': '$2', # PSC1 Complete Cycle
+ 'PCTL1_PRUN1': '$1', # PSC 1 Run
+ 'PCNF1' : '$ea', # PSC 1 Configuration Register
+ 'PCNF1_PFIFTY1': '$80', # PSC 1 Fifty
+ 'PCNF1_PALOCK1': '$40', # PSC 1 Autolock
+ 'PCNF1_PLOCK1': '$20', # PSC 1 Lock
+ 'PCNF1_PMODE1': '$18', # PSC 1 Mode
+ 'PCNF1_POP1': '$4', # PSC 1 Output Polarity
+ 'PCNF1_PCLKSEL1': '$2', # PSC 1 Input Clock Select
+ 'OCR1RB' : '$e8', # Output Compare RB Register
+ 'OCR1SB' : '$e6', # Output Compare SB Register
+ 'OCR1RA' : '$e4', # Output Compare RA Register
+ 'OCR1SA' : '$e2', # Output Compare SA Register
+ 'PSOC1' : '$e0', # PSC1 Synchro and Output Config
+ 'PSOC1_PSYNC1_': '$30', # Synchronization Out for ADC Se
+ 'PSOC1_POEN1B': '$4', # PSCOUT11 Output Enable
+ 'PSOC1_POEN1A': '$1', # PSCOUT10 Output Enable
+ 'PIM1' : '$a3', # PSC1 Interrupt Mask Register
+ 'PIM1_PSEIE1': '$20', # PSC 1 Synchro Error Interrupt
+ 'PIM1_PEVE1B': '$10', # External Event B Interrupt Ena
+ 'PIM1_PEVE1A': '$8', # External Event A Interrupt Ena
+ 'PIM1_PEOPE1': '$1', # End of Cycle Interrupt Enable
+ 'PIFR1' : '$a2', # PSC1 Interrupt Flag Register
+ 'PIFR1_POAC1B': '$80', # PSC 1 Output B Activity
+ 'PIFR1_POAC1A': '$40', # PSC 1 Output A Activity
+ 'PIFR1_PSEI1': '$20', # PSC 1 Synchro Error Interrupt
+ 'PIFR1_PEV1B': '$10', # External Event B Interrupt
+ 'PIFR1_PEV1A': '$8', # External Event A Interrupt
+ 'PIFR1_PRN1': '$6', # Ramp Number
+ 'PIFR1_PEOP1': '$1', # End of PSC1 Interrupt
+
+# Module PSC2
+ 'PICR2' : '$fe', # PSC 2 Input Capture Register
+ 'PFRC2B' : '$fd', # PSC 2 Input B Control
+ 'PFRC2B_PCAE2B': '$80', # PSC 2 Capture Enable Input Par
+ 'PFRC2B_PISEL2B': '$40', # PSC 2 Input Select for Part B
+ 'PFRC2B_PELEV2B': '$20', # PSC 2 Edge Level Selector on I
+ 'PFRC2B_PFLTE2B': '$10', # PSC 2 Filter Enable on Input P
+ 'PFRC2B_PRFM2B': '$f', # PSC 2 Retrigger and Fault Mode
+ 'PFRC2A' : '$fc', # PSC 2 Input B Control
+ 'PFRC2A_PCAE2A': '$80', # PSC 2 Capture Enable Input Par
+ 'PFRC2A_PISEL2A': '$40', # PSC 2 Input Select for Part A
+ 'PFRC2A_PELEV2A': '$20', # PSC 2 Edge Level Selector on I
+ 'PFRC2A_PFLTE2A': '$10', # PSC 2 Filter Enable on Input P
+ 'PFRC2A_PRFM2A': '$f', # PSC 2 Retrigger and Fault Mode
+ 'PCTL2' : '$fb', # PSC 2 Control Register
+ 'PCTL2_PPRE2': '$c0', # PSC 2 Prescaler Selects
+ 'PCTL2_PBFM2': '$20', # Balance Flank Width Modulation
+ 'PCTL2_PAOC2B': '$10', # PSC 2 Asynchronous Output Cont
+ 'PCTL2_PAOC2A': '$8', # PSC 2 Asynchronous Output Cont
+ 'PCTL2_PARUN2': '$4', # PSC2 Auto Run
+ 'PCTL2_PCCYC2': '$2', # PSC2 Complete Cycle
+ 'PCTL2_PRUN2': '$1', # PSC 2 Run
+ 'PCNF2' : '$fa', # PSC 2 Configuration Register
+ 'PCNF2_PFIFTY2': '$80', # PSC 2 Fifty
+ 'PCNF2_PALOCK2': '$40', # PSC 2 Autolock
+ 'PCNF2_PLOCK2': '$20', # PSC 2 Lock
+ 'PCNF2_PMODE2': '$18', # PSC 2 Mode
+ 'PCNF2_POP2': '$4', # PSC 2 Output Polarity
+ 'PCNF2_PCLKSEL2': '$2', # PSC 2 Input Clock Select
+ 'PCNF2_POME2': '$1', # PSC 2 Output Matrix Enable
+ 'OCR2RB' : '$f8', # Output Compare RB Register
+ 'OCR2SB' : '$f6', # Output Compare SB Register
+ 'OCR2RA' : '$f4', # Output Compare RA Register
+ 'OCR2SA' : '$f2', # Output Compare SA Register
+ 'POM2' : '$f1', # PSC 2 Output Matrix
+ 'POM2_POMV2B': '$f0', # Output Matrix Output B Ramps
+ 'POM2_POMV2A': '$f', # Output Matrix Output A Ramps
+ 'PSOC2' : '$f0', # PSC2 Synchro and Output Config
+ 'PSOC2_POS2': '$c0', # PSC 2 Output 23 Select
+ 'PSOC2_PSYNC2_': '$30', # Synchronization Out for ADC Se
+ 'PSOC2_POEN2D': '$8', # PSCOUT23 Output Enable
+ 'PSOC2_POEN2B': '$4', # PSCOUT21 Output Enable
+ 'PSOC2_POEN2C': '$2', # PSCOUT22 Output Enable
+ 'PSOC2_POEN2A': '$1', # PSCOUT20 Output Enable
+ 'PIM2' : '$a5', # PSC2 Interrupt Mask Register
+ 'PIM2_PSEIE2': '$20', # PSC 2 Synchro Error Interrupt
+ 'PIM2_PEVE2B': '$10', # External Event B Interrupt Ena
+ 'PIM2_PEVE2A': '$8', # External Event A Interrupt Ena
+ 'PIM2_PEOPE2': '$1', # End of Cycle Interrupt Enable
+ 'PIFR2' : '$a4', # PSC2 Interrupt Flag Register
+ 'PIFR2_POAC2B': '$80', # PSC 2 Output A Activity
+ 'PIFR2_POAC2A': '$40', # PSC 2 Output A Activity
+ 'PIFR2_PSEI2': '$20', # PSC 2 Synchro Error Interrupt
+ 'PIFR2_PEV2B': '$10', # External Event B Interrupt
+ 'PIFR2_PEV2A': '$8', # External Event A Interrupt
+ 'PIFR2_PRN2': '$6', # Ramp Number
+ 'PIFR2_PEOP2': '$1', # End of PSC2 Interrupt
+
+ '__amforth_dummy':'0'
+}
diff --git a/amforth-6.5/avr8/devices/at90pwm316/words/no-jtag.asm b/amforth-6.5/avr8/devices/at90pwm316/words/no-jtag.asm
new file mode 100644
index 0000000..352a4bb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90pwm316/words/no-jtag.asm
@@ -0,0 +1,14 @@
+; ( -- )
+; ( -- )
+; MCU
+; disable jtag at runtime
+VE_NOJTAG:
+ .dw $FF05
+ .db "-jtag",0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOJTAG
+XT_NOJTAG:
+ .dw PFA_NOJTAG
+PFA_NOJTAG:
+
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/at90pwm316/words/no-wdt.asm b/amforth-6.5/avr8/devices/at90pwm316/words/no-wdt.asm
new file mode 100644
index 0000000..ff6ddd1
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90pwm316/words/no-wdt.asm
@@ -0,0 +1,34 @@
+; ( -- )
+; MCU
+; disable watch dog timer at runtime
+VE_NOWDT:
+ .dw $ff04
+ .db "-wdt"
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOWDT
+XT_NOWDT:
+ .dw PFA_NOWDT
+PFA_NOWDT:
+
+ in temp1,SREG
+ push temp1
+ ; Turn always off global interrupt.
+ cli
+ ; Reset Watchdog Timer
+ wdr
+ ; Clear WDRF in MCUSR
+ in temp1, MCUSR
+ andi temp1, (0xff & (0<<WDRF))
+ out MCUSR, temp1
+ ; Write logical one to WDCE and WDE
+ ; Keep old prescaler setting to prevent unintentional time-out
+ in_ temp1, WDTCSR
+ ori temp1, (1<<WDCE) | (1<<WDE)
+ out_ WDTCSR, temp1
+ ; Turn off WDT
+ ldi temp1, (0<<WDE)
+ out_ WDTCSR, temp1
+ ; restore status register
+ pop temp1
+ out SREG,temp1
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/at90pwm316/words/sleep.asm b/amforth-6.5/avr8/devices/at90pwm316/words/sleep.asm
new file mode 100644
index 0000000..256249c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90pwm316/words/sleep.asm
@@ -0,0 +1,19 @@
+; ( mode -- )
+; MCU
+; put the controller into the specified sleep mode
+VE_SLEEP:
+ .dw $ff05
+ .db "sleep", 0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_SLEEP
+XT_SLEEP:
+ .dw PFA_SLEEP
+PFA_SLEEP:
+ andi tosl, 7 ; leave only legal mode bits
+ lsl tosl ; move to correct location (bits 3-1)
+ ori tosl, 1 ; set the SE bit
+ out_ SMCR, tosl ; set the sleep config
+ sleep ; nighty-night
+ out_ SMCR, zerol ; 0 protects against accidental sleeps
+ loadtos ; pop argument from stack
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/at90pwm3b/at90pwm3b.frt b/amforth-6.5/avr8/devices/at90pwm3b/at90pwm3b.frt
new file mode 100644
index 0000000..94c96ac
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90pwm3b/at90pwm3b.frt
@@ -0,0 +1,478 @@
+\ Partname: AT90PWM3B
+\ generated automatically
+
+\ PORTB
+&37 constant PORTB \ Port B Data Register
+&36 constant DDRB \ Port B Data Direction Register
+&35 constant PINB \ Port B Input Pins
+\ PORTC
+&40 constant PORTC \ Port C Data Register
+&39 constant DDRC \ Port C Data Direction Register
+&38 constant PINC \ Port C Input Pins
+\ PORTD
+&43 constant PORTD \ Port D Data Register
+&42 constant DDRD \ Port D Data Direction Register
+&41 constant PIND \ Port D Input Pins
+\ BOOT_LOAD
+&87 constant SPMCSR \ Store Program Memory Control Register
+ $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
+ $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
+ $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
+ $04 constant SPMCSR_PGWRT \ Page Write
+ $02 constant SPMCSR_PGERS \ Page Erase
+ $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
+\ EUSART
+&206 constant EUDR \ EUSART I/O Data Register
+&200 constant EUCSRA \ EUSART Control and Status Register A
+ $F0 constant EUCSRA_UTxS \ EUSART Control and Status Register A Bits
+ $0F constant EUCSRA_URxS \ EUSART Control and Status Register A Bits
+&201 constant EUCSRB \ EUSART Control Register B
+ $10 constant EUCSRB_EUSART \ EUSART Enable Bit
+ $08 constant EUCSRB_EUSBS \ EUSBS Enable Bit
+ $02 constant EUCSRB_EMCH \ Manchester Mode Bit
+ $01 constant EUCSRB_BODR \ Order Bit
+&202 constant EUCSRC \ EUSART Status Register C
+ $08 constant EUCSRC_FEM \ Frame Error Manchester Bit
+ $04 constant EUCSRC_F1617 \ F1617 Bit
+ $03 constant EUCSRC_STP \ Stop Bits
+&205 constant MUBRRH \ Manchester Receiver Baud Rate Register High Byte
+ $FF constant MUBRRH_MUBRR \ Manchester Receiver Baud Rate Register Bits
+&204 constant MUBRRL \ Manchester Receiver Baud Rate Register Low Byte
+ $FF constant MUBRRL_MUBRR \ Manchester Receiver Baud Rate Register Bits
+\ ANALOG_COMPARATOR
+&173 constant AC0CON \ Analog Comparator 0 Control Register
+ $80 constant AC0CON_AC0EN \ Analog Comparator 0 Enable Bit
+ $40 constant AC0CON_AC0IE \ Analog Comparator 0 Interrupt Enable Bit
+ $30 constant AC0CON_AC0IS \ Analog Comparator 0 Interrupt Select Bit
+ $07 constant AC0CON_AC0M \ Analog Comparator 0 Multiplexer Register
+&174 constant AC1CON \ Analog Comparator 1 Control Register
+ $80 constant AC1CON_AC1EN \ Analog Comparator 1 Enable Bit
+ $40 constant AC1CON_AC1IE \ Analog Comparator 1 Interrupt Enable Bit
+ $30 constant AC1CON_AC1IS \ Analog Comparator 1 Interrupt Select Bit
+ $08 constant AC1CON_AC1ICE \ Analog Comparator 1 Interrupt Capture Enable Bit
+ $07 constant AC1CON_AC1M \ Analog Comparator 1 Multiplexer Register
+&175 constant AC2CON \ Analog Comparator 2 Control Register
+ $80 constant AC2CON_AC2EN \ Analog Comparator 2 Enable Bit
+ $40 constant AC2CON_AC2IE \ Analog Comparator 2 Interrupt Enable Bit
+ $30 constant AC2CON_AC2IS \ Analog Comparator 2 Interrupt Select Bit
+ $07 constant AC2CON_AC2M \ Analog Comparator 2 Multiplexer Register
+&80 constant ACSR \ Analog Comparator Status Register
+ $80 constant ACSR_ACCKDIV \ Analog Comparator Clock Divider
+ $40 constant ACSR_AC2IF \ Analog Comparator 2 Interrupt Flag Bit
+ $20 constant ACSR_AC1IF \ Analog Comparator 1 Interrupt Flag Bit
+ $10 constant ACSR_AC0IF \ Analog Comparator 0 Interrupt Flag Bit
+ $04 constant ACSR_AC2O \ Analog Comparator 2 Output Bit
+ $02 constant ACSR_AC1O \ Analog Comparator 1 Output Bit
+ $01 constant ACSR_AC0O \ Analog Comparator 0 Output Bit
+\ DA_CONVERTER
+&172 constant DACH \ DAC Data Register High Byte
+ $FF constant DACH_DACH \ DAC Data Register High Byte Bits
+&171 constant DACL \ DAC Data Register Low Byte
+ $FF constant DACL_DACL \ DAC Data Register Low Byte Bits
+&170 constant DACON \ DAC Control Register
+ $80 constant DACON_DAATE \ DAC Auto Trigger Enable Bit
+ $70 constant DACON_DATS \ DAC Trigger Selection Bits
+ $04 constant DACON_DALA \ DAC Left Adjust
+ $01 constant DACON_DAEN \ DAC Enable Bit
+\ CPU
+&95 constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ $08 constant SREG_V \ Two's Complement Overflow Flag
+ $04 constant SREG_N \ Negative Flag
+ $02 constant SREG_Z \ Zero Flag
+ $01 constant SREG_C \ Carry Flag
+&93 constant SP \ Stack Pointer
+&85 constant MCUCR \ MCU Control Register
+ $80 constant MCUCR_SPIPS \ SPI Pin Select
+ $10 constant MCUCR_PUD \ Pull-up disable
+ $02 constant MCUCR_IVSEL \ Interrupt Vector Select
+ $01 constant MCUCR_IVCE \ Interrupt Vector Change Enable
+&84 constant MCUSR \ MCU Status Register
+ $08 constant MCUSR_WDRF \ Watchdog Reset Flag
+ $04 constant MCUSR_BORF \ Brown-out Reset Flag
+ $02 constant MCUSR_EXTRF \ External Reset Flag
+ $01 constant MCUSR_PORF \ Power-on reset flag
+&102 constant OSCCAL \ Oscillator Calibration Value
+&97 constant CLKPR \
+ $80 constant CLKPR_CLKPCE \
+ $0F constant CLKPR_CLKPS \
+&83 constant SMCR \ Sleep Mode Control Register
+ $0E constant SMCR_SM \ Sleep Mode Select bits
+ $01 constant SMCR_SE \ Sleep Enable
+&59 constant GPIOR3 \ General Purpose IO Register 3
+ $FF constant GPIOR3_GPIOR \ General Purpose IO Register 3 bis
+&58 constant GPIOR2 \ General Purpose IO Register 2
+ $FF constant GPIOR2_GPIOR \ General Purpose IO Register 2 bis
+&57 constant GPIOR1 \ General Purpose IO Register 1
+ $FF constant GPIOR1_GPIOR \ General Purpose IO Register 1 bis
+&62 constant GPIOR0 \ General Purpose IO Register 0
+ $80 constant GPIOR0_GPIOR07 \ General Purpose IO Register 0 bit 7
+ $40 constant GPIOR0_GPIOR06 \ General Purpose IO Register 0 bit 6
+ $20 constant GPIOR0_GPIOR05 \ General Purpose IO Register 0 bit 5
+ $10 constant GPIOR0_GPIOR04 \ General Purpose IO Register 0 bit 4
+ $08 constant GPIOR0_GPIOR03 \ General Purpose IO Register 0 bit 3
+ $04 constant GPIOR0_GPIOR02 \ General Purpose IO Register 0 bit 2
+ $02 constant GPIOR0_GPIOR01 \ General Purpose IO Register 0 bit 1
+ $01 constant GPIOR0_GPIOR00 \ General Purpose IO Register 0 bit 0
+&73 constant PLLCSR \ PLL Control And Status Register
+ $04 constant PLLCSR_PLLF \ PLL Factor
+ $02 constant PLLCSR_PLLE \ PLL Enable
+ $01 constant PLLCSR_PLOCK \ PLL Lock Detector
+&100 constant PRR \ Power Reduction Register
+ $E0 constant PRR_PRPSC \ Power Reduction PSC2
+ $10 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
+ $08 constant PRR_PRTIM0 \ Power Reduction Timer/Counter0
+ $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
+ $02 constant PRR_PRUSART0 \ Power Reduction USART
+ $01 constant PRR_PRADC \ Power Reduction ADC
+\ PORTE
+&46 constant PORTE \ Port E Data Register
+&45 constant DDRE \ Port E Data Direction Register
+&44 constant PINE \ Port E Input Pins
+\ TIMER_COUNTER_0
+&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
+ $04 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare Match B Interrupt Enable
+ $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match A Interrupt Enable
+ $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
+&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
+ $04 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare Flag 0B
+ $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0A
+ $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
+&68 constant TCCR0A \ Timer/Counter Control Register A
+ $C0 constant TCCR0A_COM0A \ Compare Output Mode, Phase Correct PWM Mode
+ $30 constant TCCR0A_COM0B \ Compare Output Mode, Fast PWm
+ $03 constant TCCR0A_WGM0 \ Waveform Generation Mode
+&69 constant TCCR0B \ Timer/Counter Control Register B
+ $80 constant TCCR0B_FOC0A \ Force Output Compare A
+ $40 constant TCCR0B_FOC0B \ Force Output Compare B
+ $08 constant TCCR0B_WGM02 \
+ $07 constant TCCR0B_CS0 \ Clock Select
+&70 constant TCNT0 \ Timer/Counter0
+&71 constant OCR0A \ Timer/Counter0 Output Compare Register
+&72 constant OCR0B \ Timer/Counter0 Output Compare Register
+&67 constant GTCCR \ General Timer/Counter Control Register
+ $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
+ $40 constant GTCCR_ICPSEL1 \ Timer1 Input Capture Selection Bit
+ $01 constant GTCCR_PSR10 \ Prescaler Reset Timer/Counter1 and Timer/Counter0
+\ TIMER_COUNTER_1
+&111 constant TIMSK1 \ Timer/Counter Interrupt Mask Register
+ $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
+ $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output CompareB Match Interrupt Enable
+ $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output CompareA Match Interrupt Enable
+ $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
+&54 constant TIFR1 \ Timer/Counter Interrupt Flag register
+ $20 constant TIFR1_ICF1 \ Input Capture Flag 1
+ $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
+ $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
+ $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
+&128 constant TCCR1A \ Timer/Counter1 Control Register A
+ $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
+ $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
+ $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
+&129 constant TCCR1B \ Timer/Counter1 Control Register B
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
+ $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
+&130 constant TCCR1C \ Timer/Counter1 Control Register C
+ $80 constant TCCR1C_FOC1A \
+ $40 constant TCCR1C_FOC1B \
+&132 constant TCNT1 \ Timer/Counter1 Bytes
+&136 constant OCR1A \ Timer/Counter1 Output Compare Register Bytes
+&138 constant OCR1B \ Timer/Counter1 Output Compare Register Bytes
+&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
+\ AD_CONVERTER
+&124 constant ADMUX \ The ADC multiplexer Selection Register
+ $C0 constant ADMUX_REFS \ Reference Selection Bits
+ $20 constant ADMUX_ADLAR \ Left Adjust Result
+ $0F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
+&122 constant ADCSRA \ The ADC Control and Status register
+ $80 constant ADCSRA_ADEN \ ADC Enable
+ $40 constant ADCSRA_ADSC \ ADC Start Conversion
+ $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
+ $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
+ $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
+ $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
+&120 constant ADC \ ADC Data Register Bytes
+&123 constant ADCSRB \ ADC Control and Status Register B
+&126 constant DIDR0 \ Digital Input Disable Register 0
+&127 constant DIDR1 \ Digital Input Disable Register 0
+ $20 constant DIDR1_ACMP0D \
+ $10 constant DIDR1_AMP0PD \
+ $08 constant DIDR1_AMP0ND \
+ $04 constant DIDR1_ADC10D \
+ $02 constant DIDR1_ADC9D \
+ $01 constant DIDR1_ADC8D \
+&118 constant AMP0CSR \
+ $80 constant AMP0CSR_AMP0EN \
+ $40 constant AMP0CSR_AMP0IS \
+ $30 constant AMP0CSR_AMP0G \
+ $03 constant AMP0CSR_AMP0TS \
+&119 constant AMP1CSR \
+ $80 constant AMP1CSR_AMP1EN \
+ $40 constant AMP1CSR_AMP1IS \
+ $30 constant AMP1CSR_AMP1G \
+ $03 constant AMP1CSR_AMP1TS \
+\ USART
+&198 constant UDR \ USART I/O Data Register
+&192 constant UCSRA \ USART Control and Status register A
+ $80 constant UCSRA_RXC \ USART Receive Complete
+ $40 constant UCSRA_TXC \ USART Transmitt Complete
+ $20 constant UCSRA_UDRE \ USART Data Register Empty
+ $10 constant UCSRA_FE \ Framing Error
+ $08 constant UCSRA_DOR \ Data Overrun
+ $04 constant UCSRA_UPE \ USART Parity Error
+ $02 constant UCSRA_U2X \ Double USART Transmission Bit
+ $01 constant UCSRA_MPCM \ Multi-processor Communication Mode
+&193 constant UCSRB \ USART Control an Status register B
+ $80 constant UCSRB_RXCIE \ RX Complete Interrupt Enable
+ $40 constant UCSRB_TXCIE \ TX Complete Interrupt Enable
+ $20 constant UCSRB_UDRIE \ USART Data Register Empty Interrupt Enable
+ $10 constant UCSRB_RXEN \ Receiver Enable
+ $08 constant UCSRB_TXEN \ Transmitter Enable
+ $04 constant UCSRB_UCSZ2 \ Character Size
+ $02 constant UCSRB_RXB8 \ Receive Data Bit 8
+ $01 constant UCSRB_TXB8 \ Transmit Data Bit 8
+&194 constant UCSRC \ USART Control an Status register C
+ $40 constant UCSRC_UMSEL0 \ USART Mode Select
+ $30 constant UCSRC_UPM \ Parity Mode Bits
+ $08 constant UCSRC_USBS \ Stop Bit Select
+ $06 constant UCSRC_UCSZ \ Character Size Bits
+ $01 constant UCSRC_UCPOL \ Clock Polarity
+&197 constant UBRRH \ USART Baud Rate Register High Byte
+ $0F constant UBRRH_UBRR \ USART Baud Rate Register Bits
+&196 constant UBRRL \ USART Baud Rate Register Low Byte
+ $FF constant UBRRL_UBRR \ USART Baud Rate Register bits
+\ SPI
+&76 constant SPCR \ SPI Control Register
+ $80 constant SPCR_SPIE \ SPI Interrupt Enable
+ $40 constant SPCR_SPE \ SPI Enable
+ $20 constant SPCR_DORD \ Data Order
+ $10 constant SPCR_MSTR \ Master/Slave Select
+ $08 constant SPCR_CPOL \ Clock polarity
+ $04 constant SPCR_CPHA \ Clock Phase
+ $03 constant SPCR_SPR \ SPI Clock Rate Selects
+&77 constant SPSR \ SPI Status Register
+ $80 constant SPSR_SPIF \ SPI Interrupt Flag
+ $40 constant SPSR_WCOL \ Write Collision Flag
+ $01 constant SPSR_SPI2X \ Double SPI Speed Bit
+&78 constant SPDR \ SPI Data Register
+\ WATCHDOG
+&96 constant WDTCSR \ Watchdog Timer Control Register
+ $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Flag
+ $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Enable
+ $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
+ $10 constant WDTCSR_WDCE \ Watchdog Change Enable
+ $08 constant WDTCSR_WDE \ Watch Dog Enable
+\ EXTERNAL_INTERRUPT
+&105 constant EICRA \ External Interrupt Control Register A
+ $C0 constant EICRA_ISC3 \ External Interrupt Sense Control Bit
+ $30 constant EICRA_ISC2 \ External Interrupt Sense Control Bit
+ $0C constant EICRA_ISC1 \ External Interrupt Sense Control Bit
+ $03 constant EICRA_ISC0 \ External Interrupt Sense Control Bit
+&61 constant EIMSK \ External Interrupt Mask Register
+ $0F constant EIMSK_INT \ External Interrupt Request 3 Enable
+&60 constant EIFR \ External Interrupt Flag Register
+ $0F constant EIFR_INTF \ External Interrupt Flags
+\ EEPROM
+&65 constant EEAR \ EEPROM Read/Write Access Bytes
+&64 constant EEDR \ EEPROM Data Register
+&63 constant EECR \ EEPROM Control Register
+ $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
+ $04 constant EECR_EEMWE \ EEPROM Master Write Enable
+ $02 constant EECR_EEWE \ EEPROM Write Enable
+ $01 constant EECR_EERE \ EEPROM Read Enable
+\ PSC0
+&222 constant PICR0 \ PSC 0 Input Capture Register
+&221 constant PFRC0B \ PSC 0 Input B Control
+ $80 constant PFRC0B_PCAE0B \ PSC 0 Capture Enable Input Part B
+ $40 constant PFRC0B_PISEL0B \ PSC 0 Input Select for Part B
+ $20 constant PFRC0B_PELEV0B \ PSC 0 Edge Level Selector on Input Part B
+ $10 constant PFRC0B_PFLTE0B \ PSC 0 Filter Enable on Input Part B
+ $0F constant PFRC0B_PRFM0B \ PSC 0 Retrigger and Fault Mode for Part B
+&220 constant PFRC0A \ PSC 0 Input A Control
+ $80 constant PFRC0A_PCAE0A \ PSC 0 Capture Enable Input Part A
+ $40 constant PFRC0A_PISEL0A \ PSC 0 Input Select for Part A
+ $20 constant PFRC0A_PELEV0A \ PSC 0 Edge Level Selector on Input Part A
+ $10 constant PFRC0A_PFLTE0A \ PSC 0 Filter Enable on Input Part A
+ $0F constant PFRC0A_PRFM0A \ PSC 0 Retrigger and Fault Mode for Part A
+&219 constant PCTL0 \ PSC 0 Control Register
+ $C0 constant PCTL0_PPRE0 \ PSC 0 Prescaler Selects
+ $20 constant PCTL0_PBFM0 \ PSC 0 Balance Flank Width Modulation
+ $10 constant PCTL0_PAOC0B \ PSC 0 Asynchronous Output Control B
+ $08 constant PCTL0_PAOC0A \ PSC 0 Asynchronous Output Control A
+ $04 constant PCTL0_PARUN0 \ PSC0 Auto Run
+ $02 constant PCTL0_PCCYC0 \ PSC0 Complete Cycle
+ $01 constant PCTL0_PRUN0 \ PSC 0 Run
+&218 constant PCNF0 \ PSC 0 Configuration Register
+ $80 constant PCNF0_PFIFTY0 \ PSC 0 Fifty
+ $40 constant PCNF0_PALOCK0 \ PSC 0 Autolock
+ $20 constant PCNF0_PLOCK0 \ PSC 0 Lock
+ $18 constant PCNF0_PMODE0 \ PSC 0 Mode
+ $04 constant PCNF0_POP0 \ PSC 0 Output Polarity
+ $02 constant PCNF0_PCLKSEL0 \ PSC 0 Input Clock Select
+&216 constant OCR0RB \ Output Compare RB Register
+&214 constant OCR0SB \ Output Compare SB Register
+&212 constant OCR0RA \ Output Compare RA Register
+&210 constant OCR0SA \ Output Compare SA Register
+&208 constant PSOC0 \ PSC0 Synchro and Output Configuration
+ $30 constant PSOC0_PSYNC0 \ Synchronization Out for ADC Selection
+ $04 constant PSOC0_POEN0B \ PSCOUT01 Output Enable
+ $01 constant PSOC0_POEN0A \ PSCOUT00 Output Enable
+&161 constant PIM0 \ PSC0 Interrupt Mask Register
+ $20 constant PIM0_PSEIE0 \ PSC 0 Synchro Error Interrupt Enable
+ $10 constant PIM0_PEVE0B \ External Event B Interrupt Enable
+ $08 constant PIM0_PEVE0A \ External Event A Interrupt Enable
+ $01 constant PIM0_PEOPE0 \ End of Cycle Interrupt Enable
+&160 constant PIFR0 \ PSC0 Interrupt Flag Register
+ $80 constant PIFR0_POAC0B \ PSC 0 Output A Activity
+ $40 constant PIFR0_POAC0A \ PSC 0 Output A Activity
+ $20 constant PIFR0_PSEI0 \ PSC 0 Synchro Error Interrupt
+ $10 constant PIFR0_PEV0B \ External Event B Interrupt
+ $08 constant PIFR0_PEV0A \ External Event A Interrupt
+ $06 constant PIFR0_PRN0 \ Ramp Number
+ $01 constant PIFR0_PEOP0 \ End of PSC0 Interrupt
+\ PSC1
+&238 constant PICR1 \ PSC 1 Input Capture Register
+&237 constant PFRC1B \ PSC 1 Input B Control
+ $80 constant PFRC1B_PCAE1B \ PSC 1 Capture Enable Input Part B
+ $40 constant PFRC1B_PISEL1B \ PSC 1 Input Select for Part B
+ $20 constant PFRC1B_PELEV1B \ PSC 1 Edge Level Selector on Input Part B
+ $10 constant PFRC1B_PFLTE1B \ PSC 1 Filter Enable on Input Part B
+ $0F constant PFRC1B_PRFM1B \ PSC 1 Retrigger and Fault Mode for Part B
+&236 constant PFRC1A \ PSC 1 Input B Control
+ $80 constant PFRC1A_PCAE1A \ PSC 1 Capture Enable Input Part A
+ $40 constant PFRC1A_PISEL1A \ PSC 1 Input Select for Part A
+ $20 constant PFRC1A_PELEV1A \ PSC 1 Edge Level Selector on Input Part A
+ $10 constant PFRC1A_PFLTE1A \ PSC 1 Filter Enable on Input Part A
+ $0F constant PFRC1A_PRFM1A \ PSC 1 Retrigger and Fault Mode for Part A
+&235 constant PCTL1 \ PSC 1 Control Register
+ $C0 constant PCTL1_PPRE1 \ PSC 1 Prescaler Selects
+ $20 constant PCTL1_PBFM1 \ Balance Flank Width Modulation
+ $10 constant PCTL1_PAOC1B \ PSC 1 Asynchronous Output Control B
+ $08 constant PCTL1_PAOC1A \ PSC 1 Asynchronous Output Control A
+ $04 constant PCTL1_PARUN1 \ PSC1 Auto Run
+ $02 constant PCTL1_PCCYC1 \ PSC1 Complete Cycle
+ $01 constant PCTL1_PRUN1 \ PSC 1 Run
+&234 constant PCNF1 \ PSC 1 Configuration Register
+ $80 constant PCNF1_PFIFTY1 \ PSC 1 Fifty
+ $40 constant PCNF1_PALOCK1 \ PSC 1 Autolock
+ $20 constant PCNF1_PLOCK1 \ PSC 1 Lock
+ $18 constant PCNF1_PMODE1 \ PSC 1 Mode
+ $04 constant PCNF1_POP1 \ PSC 1 Output Polarity
+ $02 constant PCNF1_PCLKSEL1 \ PSC 1 Input Clock Select
+&232 constant OCR1RB \ Output Compare RB Register
+&230 constant OCR1SB \ Output Compare SB Register
+&228 constant OCR1RA \ Output Compare RA Register
+&226 constant OCR1SA \ Output Compare SA Register
+&224 constant PSOC1 \ PSC1 Synchro and Output Configuration
+ $30 constant PSOC1_PSYNC1_ \ Synchronization Out for ADC Selection
+ $04 constant PSOC1_POEN1B \ PSCOUT11 Output Enable
+ $01 constant PSOC1_POEN1A \ PSCOUT10 Output Enable
+&163 constant PIM1 \ PSC1 Interrupt Mask Register
+ $20 constant PIM1_PSEIE1 \ PSC 1 Synchro Error Interrupt Enable
+ $10 constant PIM1_PEVE1B \ External Event B Interrupt Enable
+ $08 constant PIM1_PEVE1A \ External Event A Interrupt Enable
+ $01 constant PIM1_PEOPE1 \ End of Cycle Interrupt Enable
+&162 constant PIFR1 \ PSC1 Interrupt Flag Register
+ $80 constant PIFR1_POAC1B \ PSC 1 Output B Activity
+ $40 constant PIFR1_POAC1A \ PSC 1 Output A Activity
+ $20 constant PIFR1_PSEI1 \ PSC 1 Synchro Error Interrupt
+ $10 constant PIFR1_PEV1B \ External Event B Interrupt
+ $08 constant PIFR1_PEV1A \ External Event A Interrupt
+ $06 constant PIFR1_PRN1 \ Ramp Number
+ $01 constant PIFR1_PEOP1 \ End of PSC1 Interrupt
+\ PSC2
+&254 constant PICR2 \ PSC 2 Input Capture Register
+&253 constant PFRC2B \ PSC 2 Input B Control
+ $80 constant PFRC2B_PCAE2B \ PSC 2 Capture Enable Input Part B
+ $40 constant PFRC2B_PISEL2B \ PSC 2 Input Select for Part B
+ $20 constant PFRC2B_PELEV2B \ PSC 2 Edge Level Selector on Input Part B
+ $10 constant PFRC2B_PFLTE2B \ PSC 2 Filter Enable on Input Part B
+ $0F constant PFRC2B_PRFM2B \ PSC 2 Retrigger and Fault Mode for Part B
+&252 constant PFRC2A \ PSC 2 Input B Control
+ $80 constant PFRC2A_PCAE2A \ PSC 2 Capture Enable Input Part A
+ $40 constant PFRC2A_PISEL2A \ PSC 2 Input Select for Part A
+ $20 constant PFRC2A_PELEV2A \ PSC 2 Edge Level Selector on Input Part A
+ $10 constant PFRC2A_PFLTE2A \ PSC 2 Filter Enable on Input Part A
+ $0F constant PFRC2A_PRFM2A \ PSC 2 Retrigger and Fault Mode for Part A
+&251 constant PCTL2 \ PSC 2 Control Register
+ $C0 constant PCTL2_PPRE2 \ PSC 2 Prescaler Selects
+ $20 constant PCTL2_PBFM2 \ Balance Flank Width Modulation
+ $10 constant PCTL2_PAOC2B \ PSC 2 Asynchronous Output Control B
+ $08 constant PCTL2_PAOC2A \ PSC 2 Asynchronous Output Control A
+ $04 constant PCTL2_PARUN2 \ PSC2 Auto Run
+ $02 constant PCTL2_PCCYC2 \ PSC2 Complete Cycle
+ $01 constant PCTL2_PRUN2 \ PSC 2 Run
+&250 constant PCNF2 \ PSC 2 Configuration Register
+ $80 constant PCNF2_PFIFTY2 \ PSC 2 Fifty
+ $40 constant PCNF2_PALOCK2 \ PSC 2 Autolock
+ $20 constant PCNF2_PLOCK2 \ PSC 2 Lock
+ $18 constant PCNF2_PMODE2 \ PSC 2 Mode
+ $04 constant PCNF2_POP2 \ PSC 2 Output Polarity
+ $02 constant PCNF2_PCLKSEL2 \ PSC 2 Input Clock Select
+ $01 constant PCNF2_POME2 \ PSC 2 Output Matrix Enable
+&248 constant OCR2RB \ Output Compare RB Register
+&246 constant OCR2SB \ Output Compare SB Register
+&244 constant OCR2RA \ Output Compare RA Register
+&242 constant OCR2SA \ Output Compare SA Register
+&241 constant POM2 \ PSC 2 Output Matrix
+ $F0 constant POM2_POMV2B \ Output Matrix Output B Ramps
+ $0F constant POM2_POMV2A \ Output Matrix Output A Ramps
+&240 constant PSOC2 \ PSC2 Synchro and Output Configuration
+ $C0 constant PSOC2_POS2 \ PSC 2 Output 23 Select
+ $30 constant PSOC2_PSYNC2_ \ Synchronization Out for ADC Selection
+ $08 constant PSOC2_POEN2D \ PSCOUT23 Output Enable
+ $04 constant PSOC2_POEN2B \ PSCOUT21 Output Enable
+ $02 constant PSOC2_POEN2C \ PSCOUT22 Output Enable
+ $01 constant PSOC2_POEN2A \ PSCOUT20 Output Enable
+&165 constant PIM2 \ PSC2 Interrupt Mask Register
+ $20 constant PIM2_PSEIE2 \ PSC 2 Synchro Error Interrupt Enable
+ $10 constant PIM2_PEVE2B \ External Event B Interrupt Enable
+ $08 constant PIM2_PEVE2A \ External Event A Interrupt Enable
+ $01 constant PIM2_PEOPE2 \ End of Cycle Interrupt Enable
+&164 constant PIFR2 \ PSC2 Interrupt Flag Register
+ $80 constant PIFR2_POAC2B \ PSC 2 Output A Activity
+ $40 constant PIFR2_POAC2A \ PSC 2 Output A Activity
+ $20 constant PIFR2_PSEI2 \ PSC 2 Synchro Error Interrupt
+ $10 constant PIFR2_PEV2B \ External Event B Interrupt
+ $08 constant PIFR2_PEV2A \ External Event A Interrupt
+ $06 constant PIFR2_PRN2 \ Ramp Number
+ $01 constant PIFR2_PEOP2 \ End of PSC2 Interrupt
+
+\ Interrupts
+&1 constant PSC2_CAPTAddr \ PSC2 Capture Event
+&2 constant PSC2_ECAddr \ PSC2 End Cycle
+&3 constant PSC1_CAPTAddr \ PSC1 Capture Event
+&4 constant PSC1_ECAddr \ PSC1 End Cycle
+&5 constant PSC0_CAPTAddr \ PSC0 Capture Event
+&6 constant PSC0_ECAddr \ PSC0 End Cycle
+&7 constant ANALOG_COMP_0Addr \ Analog Comparator 0
+&8 constant ANALOG_COMP_1Addr \ Analog Comparator 1
+&9 constant ANALOG_COMP_2Addr \ Analog Comparator 2
+&10 constant INT0Addr \ External Interrupt Request 0
+&11 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+&12 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
+&13 constant TIMER1_COMPBAddr \ Timer/Counter Compare Match B
+&14 constant RESERVED15Addr \
+&15 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+&16 constant TIMER0_COMP_AAddr \ Timer/Counter0 Compare Match A
+&17 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
+&18 constant ADCAddr \ ADC Conversion Complete
+&19 constant INT1Addr \ External Interrupt Request 1
+&20 constant SPI__STCAddr \ SPI Serial Transfer Complete
+&21 constant USART__RXAddr \ USART, Rx Complete
+&22 constant USART__UDREAddr \ USART Data Register Empty
+&23 constant USART__TXAddr \ USART, Tx Complete
+&24 constant INT2Addr \ External Interrupt Request 2
+&25 constant WDTAddr \ Watchdog Timeout Interrupt
+&26 constant EE_READYAddr \ EEPROM Ready
+&27 constant TIMER0_COMPBAddr \ Timer Counter 0 Compare Match B
+&28 constant INT3Addr \ External Interrupt Request 3
+&29 constant RESERVED30Addr \
+&30 constant RESERVED31Addr \
+&31 constant SPM_READYAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/at90pwm3b/device.asm b/amforth-6.5/avr8/devices/at90pwm3b/device.asm
new file mode 100644
index 0000000..e3fafb9
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90pwm3b/device.asm
@@ -0,0 +1,125 @@
+; Partname: AT90PWM3B
+; generated automatically, do not edit
+
+.nolist
+ .include "pwm3Bdef.inc"
+.list
+
+.equ ramstart = 256
+.equ CELLSIZE = 2
+.macro readflashcell
+ lsl zl
+ rol zh
+ lpm @0, Z+
+ lpm @1, Z+
+.endmacro
+.macro writeflashcell
+ lsl zl
+ rol zh
+.endmacro
+.set WANT_PORTB = 0
+.set WANT_PORTC = 0
+.set WANT_PORTD = 0
+.set WANT_BOOT_LOAD = 0
+.set WANT_EUSART = 0
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_DA_CONVERTER = 0
+.set WANT_CPU = 0
+.set WANT_PORTE = 0
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_AD_CONVERTER = 0
+.set WANT_USART = 0
+.set WANT_SPI = 0
+.set WANT_WATCHDOG = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_EEPROM = 0
+.set WANT_PSC0 = 0
+.set WANT_PSC1 = 0
+.set WANT_PSC2 = 0
+.equ intvecsize = 1 ; please verify; flash size: 8192 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.org 1
+ rcall isr ; PSC2 Capture Event
+.org 2
+ rcall isr ; PSC2 End Cycle
+.org 3
+ rcall isr ; PSC1 Capture Event
+.org 4
+ rcall isr ; PSC1 End Cycle
+.org 5
+ rcall isr ; PSC0 Capture Event
+.org 6
+ rcall isr ; PSC0 End Cycle
+.org 7
+ rcall isr ; Analog Comparator 0
+.org 8
+ rcall isr ; Analog Comparator 1
+.org 9
+ rcall isr ; Analog Comparator 2
+.org 10
+ rcall isr ; External Interrupt Request 0
+.org 11
+ rcall isr ; Timer/Counter1 Capture Event
+.org 12
+ rcall isr ; Timer/Counter1 Compare Match A
+.org 13
+ rcall isr ; Timer/Counter Compare Match B
+.org 14
+ rcall isr ;
+.org 15
+ rcall isr ; Timer/Counter1 Overflow
+.org 16
+ rcall isr ; Timer/Counter0 Compare Match A
+.org 17
+ rcall isr ; Timer/Counter0 Overflow
+.org 18
+ rcall isr ; ADC Conversion Complete
+.org 19
+ rcall isr ; External Interrupt Request 1
+.org 20
+ rcall isr ; SPI Serial Transfer Complete
+.org 21
+ rcall isr ; USART, Rx Complete
+.org 22
+ rcall isr ; USART Data Register Empty
+.org 23
+ rcall isr ; USART, Tx Complete
+.org 24
+ rcall isr ; External Interrupt Request 2
+.org 25
+ rcall isr ; Watchdog Timeout Interrupt
+.org 26
+ rcall isr ; EEPROM Ready
+.org 27
+ rcall isr ; Timer Counter 0 Compare Match B
+.org 28
+ rcall isr ; External Interrupt Request 3
+.org 29
+ rcall isr ;
+.org 30
+ rcall isr ;
+.org 31
+ rcall isr ; Store Program Memory Read
+.equ INTVECTORS = 32
+.nooverlap
+
+; compatability layer (maybe empty)
+.equ EEPE = EEWE
+.equ EEMPE = EEMWE
+
+; controller data area, environment query mcu-info
+mcu_info:
+mcu_ramsize:
+ .dw 512
+mcu_eepromsize:
+ .dw 512
+mcu_maxdp:
+ .dw 6144
+mcu_numints:
+ .dw 32
+mcu_name:
+ .dw 9
+ .db "AT90PWM3B",0
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/at90pwm3b/device.inc b/amforth-6.5/avr8/devices/at90pwm3b/device.inc
new file mode 100644
index 0000000..8b83af9
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90pwm3b/device.inc
@@ -0,0 +1,1467 @@
+; Partname: AT90PWM3B
+; generated automatically, no not edit
+
+.if WANT_PORTB == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw 37
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw 36
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw 35
+
+.endif
+.if WANT_PORTC == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Register
+VE_PORTC:
+ .dw $ff05
+ .db "PORTC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTC
+XT_PORTC:
+ .dw PFA_DOVARIABLE
+PFA_PORTC:
+ .dw 40
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Direction Register
+VE_DDRC:
+ .dw $ff04
+ .db "DDRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRC
+XT_DDRC:
+ .dw PFA_DOVARIABLE
+PFA_DDRC:
+ .dw 39
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Input Pins
+VE_PINC:
+ .dw $ff04
+ .db "PINC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINC
+XT_PINC:
+ .dw PFA_DOVARIABLE
+PFA_PINC:
+ .dw 38
+
+.endif
+.if WANT_PORTD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw 43
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw 42
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw 41
+
+.endif
+.if WANT_BOOT_LOAD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control Register
+VE_SPMCSR:
+ .dw $ff06
+ .db "SPMCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCSR
+XT_SPMCSR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCSR:
+ .dw 87
+
+.endif
+.if WANT_EUSART == 1
+; ( -- addr ) System Constant
+; R( -- )
+; EUSART I/O Data Register
+VE_EUDR:
+ .dw $ff04
+ .db "EUDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EUDR
+XT_EUDR:
+ .dw PFA_DOVARIABLE
+PFA_EUDR:
+ .dw 206
+; ( -- addr ) System Constant
+; R( -- )
+; EUSART Control and Status Register A
+VE_EUCSRA:
+ .dw $ff06
+ .db "EUCSRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EUCSRA
+XT_EUCSRA:
+ .dw PFA_DOVARIABLE
+PFA_EUCSRA:
+ .dw 200
+; ( -- addr ) System Constant
+; R( -- )
+; EUSART Control Register B
+VE_EUCSRB:
+ .dw $ff06
+ .db "EUCSRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EUCSRB
+XT_EUCSRB:
+ .dw PFA_DOVARIABLE
+PFA_EUCSRB:
+ .dw 201
+; ( -- addr ) System Constant
+; R( -- )
+; EUSART Status Register C
+VE_EUCSRC:
+ .dw $ff06
+ .db "EUCSRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EUCSRC
+XT_EUCSRC:
+ .dw PFA_DOVARIABLE
+PFA_EUCSRC:
+ .dw 202
+; ( -- addr ) System Constant
+; R( -- )
+; Manchester Receiver Baud Rate Register High Byte
+VE_MUBRRH:
+ .dw $ff06
+ .db "MUBRRH"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MUBRRH
+XT_MUBRRH:
+ .dw PFA_DOVARIABLE
+PFA_MUBRRH:
+ .dw 205
+; ( -- addr ) System Constant
+; R( -- )
+; Manchester Receiver Baud Rate Register Low Byte
+VE_MUBRRL:
+ .dw $ff06
+ .db "MUBRRL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MUBRRL
+XT_MUBRRL:
+ .dw PFA_DOVARIABLE
+PFA_MUBRRL:
+ .dw 204
+
+.endif
+.if WANT_ANALOG_COMPARATOR == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator 0 Control Register
+VE_AC0CON:
+ .dw $ff06
+ .db "AC0CON"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_AC0CON
+XT_AC0CON:
+ .dw PFA_DOVARIABLE
+PFA_AC0CON:
+ .dw 173
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator 1 Control Register
+VE_AC1CON:
+ .dw $ff06
+ .db "AC1CON"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_AC1CON
+XT_AC1CON:
+ .dw PFA_DOVARIABLE
+PFA_AC1CON:
+ .dw 174
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator 2 Control Register
+VE_AC2CON:
+ .dw $ff06
+ .db "AC2CON"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_AC2CON
+XT_AC2CON:
+ .dw PFA_DOVARIABLE
+PFA_AC2CON:
+ .dw 175
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw 80
+
+.endif
+.if WANT_DA_CONVERTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; DAC Data Register High Byte
+VE_DACH:
+ .dw $ff04
+ .db "DACH"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DACH
+XT_DACH:
+ .dw PFA_DOVARIABLE
+PFA_DACH:
+ .dw 172
+; ( -- addr ) System Constant
+; R( -- )
+; DAC Data Register Low Byte
+VE_DACL:
+ .dw $ff04
+ .db "DACL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DACL
+XT_DACL:
+ .dw PFA_DOVARIABLE
+PFA_DACL:
+ .dw 171
+; ( -- addr ) System Constant
+; R( -- )
+; DAC Control Register
+VE_DACON:
+ .dw $ff05
+ .db "DACON",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DACON
+XT_DACON:
+ .dw PFA_DOVARIABLE
+PFA_DACON:
+ .dw 170
+
+.endif
+.if WANT_CPU == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw 95
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer
+VE_SP:
+ .dw $ff02
+ .db "SP"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SP
+XT_SP:
+ .dw PFA_DOVARIABLE
+PFA_SP:
+ .dw 93
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw 85
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Status Register
+VE_MCUSR:
+ .dw $ff05
+ .db "MCUSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUSR
+XT_MCUSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUSR:
+ .dw 84
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Calibration Value
+VE_OSCCAL:
+ .dw $ff06
+ .db "OSCCAL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSCCAL
+XT_OSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_OSCCAL:
+ .dw 102
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_CLKPR:
+ .dw $ff05
+ .db "CLKPR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKPR
+XT_CLKPR:
+ .dw PFA_DOVARIABLE
+PFA_CLKPR:
+ .dw 97
+; ( -- addr ) System Constant
+; R( -- )
+; Sleep Mode Control Register
+VE_SMCR:
+ .dw $ff04
+ .db "SMCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SMCR
+XT_SMCR:
+ .dw PFA_DOVARIABLE
+PFA_SMCR:
+ .dw 83
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 3
+VE_GPIOR3:
+ .dw $ff06
+ .db "GPIOR3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR3
+XT_GPIOR3:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR3:
+ .dw 59
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 2
+VE_GPIOR2:
+ .dw $ff06
+ .db "GPIOR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR2
+XT_GPIOR2:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR2:
+ .dw 58
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 1
+VE_GPIOR1:
+ .dw $ff06
+ .db "GPIOR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR1
+XT_GPIOR1:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR1:
+ .dw 57
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 0
+VE_GPIOR0:
+ .dw $ff06
+ .db "GPIOR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR0
+XT_GPIOR0:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR0:
+ .dw 62
+; ( -- addr ) System Constant
+; R( -- )
+; PLL Control And Status Register
+VE_PLLCSR:
+ .dw $ff06
+ .db "PLLCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PLLCSR
+XT_PLLCSR:
+ .dw PFA_DOVARIABLE
+PFA_PLLCSR:
+ .dw 73
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register
+VE_PRR:
+ .dw $ff03
+ .db "PRR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR
+XT_PRR:
+ .dw PFA_DOVARIABLE
+PFA_PRR:
+ .dw 100
+
+.endif
+.if WANT_PORTE == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port E Data Register
+VE_PORTE:
+ .dw $ff05
+ .db "PORTE",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTE
+XT_PORTE:
+ .dw PFA_DOVARIABLE
+PFA_PORTE:
+ .dw 46
+; ( -- addr ) System Constant
+; R( -- )
+; Port E Data Direction Register
+VE_DDRE:
+ .dw $ff04
+ .db "DDRE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRE
+XT_DDRE:
+ .dw PFA_DOVARIABLE
+PFA_DDRE:
+ .dw 45
+; ( -- addr ) System Constant
+; R( -- )
+; Port E Input Pins
+VE_PINE:
+ .dw $ff04
+ .db "PINE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINE
+XT_PINE:
+ .dw PFA_DOVARIABLE
+PFA_PINE:
+ .dw 44
+
+.endif
+.if WANT_TIMER_COUNTER_0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Mask Register
+VE_TIMSK0:
+ .dw $ff06
+ .db "TIMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK0
+XT_TIMSK0:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK0:
+ .dw 110
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Flag register
+VE_TIFR0:
+ .dw $ff05
+ .db "TIFR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR0
+XT_TIFR0:
+ .dw PFA_DOVARIABLE
+PFA_TIFR0:
+ .dw 53
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register A
+VE_TCCR0A:
+ .dw $ff06
+ .db "TCCR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0A
+XT_TCCR0A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0A:
+ .dw 68
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register B
+VE_TCCR0B:
+ .dw $ff06
+ .db "TCCR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0B
+XT_TCCR0B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0B:
+ .dw 69
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw 70
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0A:
+ .dw $ff05
+ .db "OCR0A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0A
+XT_OCR0A:
+ .dw PFA_DOVARIABLE
+PFA_OCR0A:
+ .dw 71
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0B:
+ .dw $ff05
+ .db "OCR0B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0B
+XT_OCR0B:
+ .dw PFA_DOVARIABLE
+PFA_OCR0B:
+ .dw 72
+; ( -- addr ) System Constant
+; R( -- )
+; General Timer/Counter Control Register
+VE_GTCCR:
+ .dw $ff05
+ .db "GTCCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GTCCR
+XT_GTCCR:
+ .dw PFA_DOVARIABLE
+PFA_GTCCR:
+ .dw 67
+
+.endif
+.if WANT_TIMER_COUNTER_1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Mask Register
+VE_TIMSK1:
+ .dw $ff06
+ .db "TIMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK1
+XT_TIMSK1:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK1:
+ .dw 111
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Flag register
+VE_TIFR1:
+ .dw $ff05
+ .db "TIFR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR1
+XT_TIFR1:
+ .dw PFA_DOVARIABLE
+PFA_TIFR1:
+ .dw 54
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw 128
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw 129
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register C
+VE_TCCR1C:
+ .dw $ff06
+ .db "TCCR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1C
+XT_TCCR1C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1C:
+ .dw 130
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Bytes
+VE_TCNT1:
+ .dw $ff05
+ .db "TCNT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1
+XT_TCNT1:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1:
+ .dw 132
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register Bytes
+VE_OCR1A:
+ .dw $ff05
+ .db "OCR1A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1A
+XT_OCR1A:
+ .dw PFA_DOVARIABLE
+PFA_OCR1A:
+ .dw 136
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register Bytes
+VE_OCR1B:
+ .dw $ff05
+ .db "OCR1B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1B
+XT_OCR1B:
+ .dw PFA_DOVARIABLE
+PFA_OCR1B:
+ .dw 138
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Bytes
+VE_ICR1:
+ .dw $ff04
+ .db "ICR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1
+XT_ICR1:
+ .dw PFA_DOVARIABLE
+PFA_ICR1:
+ .dw 134
+
+.endif
+.if WANT_AD_CONVERTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC multiplexer Selection Register
+VE_ADMUX:
+ .dw $ff05
+ .db "ADMUX",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADMUX
+XT_ADMUX:
+ .dw PFA_DOVARIABLE
+PFA_ADMUX:
+ .dw 124
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register
+VE_ADCSRA:
+ .dw $ff06
+ .db "ADCSRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRA
+XT_ADCSRA:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRA:
+ .dw 122
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register Bytes
+VE_ADC:
+ .dw $ff03
+ .db "ADC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADC
+XT_ADC:
+ .dw PFA_DOVARIABLE
+PFA_ADC:
+ .dw 120
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Control and Status Register B
+VE_ADCSRB:
+ .dw $ff06
+ .db "ADCSRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRB
+XT_ADCSRB:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRB:
+ .dw 123
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 0
+VE_DIDR0:
+ .dw $ff05
+ .db "DIDR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR0
+XT_DIDR0:
+ .dw PFA_DOVARIABLE
+PFA_DIDR0:
+ .dw 126
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 0
+VE_DIDR1:
+ .dw $ff05
+ .db "DIDR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR1
+XT_DIDR1:
+ .dw PFA_DOVARIABLE
+PFA_DIDR1:
+ .dw 127
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_AMP0CSR:
+ .dw $ff07
+ .db "AMP0CSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_AMP0CSR
+XT_AMP0CSR:
+ .dw PFA_DOVARIABLE
+PFA_AMP0CSR:
+ .dw 118
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_AMP1CSR:
+ .dw $ff07
+ .db "AMP1CSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_AMP1CSR
+XT_AMP1CSR:
+ .dw PFA_DOVARIABLE
+PFA_AMP1CSR:
+ .dw 119
+
+.endif
+.if WANT_USART == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR:
+ .dw $ff03
+ .db "UDR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR
+XT_UDR:
+ .dw PFA_DOVARIABLE
+PFA_UDR:
+ .dw 198
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status register A
+VE_UCSRA:
+ .dw $ff05
+ .db "UCSRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSRA
+XT_UCSRA:
+ .dw PFA_DOVARIABLE
+PFA_UCSRA:
+ .dw 192
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control an Status register B
+VE_UCSRB:
+ .dw $ff05
+ .db "UCSRB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSRB
+XT_UCSRB:
+ .dw PFA_DOVARIABLE
+PFA_UCSRB:
+ .dw 193
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control an Status register C
+VE_UCSRC:
+ .dw $ff05
+ .db "UCSRC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSRC
+XT_UCSRC:
+ .dw PFA_DOVARIABLE
+PFA_UCSRC:
+ .dw 194
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register High Byte
+VE_UBRRH:
+ .dw $ff05
+ .db "UBRRH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRRH
+XT_UBRRH:
+ .dw PFA_DOVARIABLE
+PFA_UBRRH:
+ .dw 197
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Low Byte
+VE_UBRRL:
+ .dw $ff05
+ .db "UBRRL",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRRL
+XT_UBRRL:
+ .dw PFA_DOVARIABLE
+PFA_UBRRL:
+ .dw 196
+
+.endif
+.if WANT_SPI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR:
+ .dw $ff04
+ .db "SPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR
+XT_SPCR:
+ .dw PFA_DOVARIABLE
+PFA_SPCR:
+ .dw 76
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR:
+ .dw $ff04
+ .db "SPSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR
+XT_SPSR:
+ .dw PFA_DOVARIABLE
+PFA_SPSR:
+ .dw 77
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR:
+ .dw $ff04
+ .db "SPDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR
+XT_SPDR:
+ .dw PFA_DOVARIABLE
+PFA_SPDR:
+ .dw 78
+
+.endif
+.if WANT_WATCHDOG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCSR:
+ .dw $ff06
+ .db "WDTCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCSR
+XT_WDTCSR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCSR:
+ .dw 96
+
+.endif
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register A
+VE_EICRA:
+ .dw $ff05
+ .db "EICRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRA
+XT_EICRA:
+ .dw PFA_DOVARIABLE
+PFA_EICRA:
+ .dw 105
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Mask Register
+VE_EIMSK:
+ .dw $ff05
+ .db "EIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIMSK
+XT_EIMSK:
+ .dw PFA_DOVARIABLE
+PFA_EIMSK:
+ .dw 61
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Flag Register
+VE_EIFR:
+ .dw $ff04
+ .db "EIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIFR
+XT_EIFR:
+ .dw PFA_DOVARIABLE
+PFA_EIFR:
+ .dw 60
+
+.endif
+.if WANT_EEPROM == 1
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Read/Write Access Bytes
+VE_EEAR:
+ .dw $ff04
+ .db "EEAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEAR
+XT_EEAR:
+ .dw PFA_DOVARIABLE
+PFA_EEAR:
+ .dw 65
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw 64
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw 63
+
+.endif
+.if WANT_PSC0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 0 Input Capture Register
+VE_PICR0:
+ .dw $ff05
+ .db "PICR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PICR0
+XT_PICR0:
+ .dw PFA_DOVARIABLE
+PFA_PICR0:
+ .dw 222
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 0 Input B Control
+VE_PFRC0B:
+ .dw $ff06
+ .db "PFRC0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PFRC0B
+XT_PFRC0B:
+ .dw PFA_DOVARIABLE
+PFA_PFRC0B:
+ .dw 221
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 0 Input A Control
+VE_PFRC0A:
+ .dw $ff06
+ .db "PFRC0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PFRC0A
+XT_PFRC0A:
+ .dw PFA_DOVARIABLE
+PFA_PFRC0A:
+ .dw 220
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 0 Control Register
+VE_PCTL0:
+ .dw $ff05
+ .db "PCTL0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCTL0
+XT_PCTL0:
+ .dw PFA_DOVARIABLE
+PFA_PCTL0:
+ .dw 219
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 0 Configuration Register
+VE_PCNF0:
+ .dw $ff05
+ .db "PCNF0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCNF0
+XT_PCNF0:
+ .dw PFA_DOVARIABLE
+PFA_PCNF0:
+ .dw 218
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare RB Register
+VE_OCR0RB:
+ .dw $ff06
+ .db "OCR0RB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0RB
+XT_OCR0RB:
+ .dw PFA_DOVARIABLE
+PFA_OCR0RB:
+ .dw 216
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare SB Register
+VE_OCR0SB:
+ .dw $ff06
+ .db "OCR0SB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0SB
+XT_OCR0SB:
+ .dw PFA_DOVARIABLE
+PFA_OCR0SB:
+ .dw 214
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare RA Register
+VE_OCR0RA:
+ .dw $ff06
+ .db "OCR0RA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0RA
+XT_OCR0RA:
+ .dw PFA_DOVARIABLE
+PFA_OCR0RA:
+ .dw 212
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare SA Register
+VE_OCR0SA:
+ .dw $ff06
+ .db "OCR0SA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0SA
+XT_OCR0SA:
+ .dw PFA_DOVARIABLE
+PFA_OCR0SA:
+ .dw 210
+; ( -- addr ) System Constant
+; R( -- )
+; PSC0 Synchro and Output Configuration
+VE_PSOC0:
+ .dw $ff05
+ .db "PSOC0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PSOC0
+XT_PSOC0:
+ .dw PFA_DOVARIABLE
+PFA_PSOC0:
+ .dw 208
+; ( -- addr ) System Constant
+; R( -- )
+; PSC0 Interrupt Mask Register
+VE_PIM0:
+ .dw $ff04
+ .db "PIM0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIM0
+XT_PIM0:
+ .dw PFA_DOVARIABLE
+PFA_PIM0:
+ .dw 161
+; ( -- addr ) System Constant
+; R( -- )
+; PSC0 Interrupt Flag Register
+VE_PIFR0:
+ .dw $ff05
+ .db "PIFR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIFR0
+XT_PIFR0:
+ .dw PFA_DOVARIABLE
+PFA_PIFR0:
+ .dw 160
+
+.endif
+.if WANT_PSC1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 1 Input Capture Register
+VE_PICR1:
+ .dw $ff05
+ .db "PICR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PICR1
+XT_PICR1:
+ .dw PFA_DOVARIABLE
+PFA_PICR1:
+ .dw 238
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 1 Input B Control
+VE_PFRC1B:
+ .dw $ff06
+ .db "PFRC1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PFRC1B
+XT_PFRC1B:
+ .dw PFA_DOVARIABLE
+PFA_PFRC1B:
+ .dw 237
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 1 Input B Control
+VE_PFRC1A:
+ .dw $ff06
+ .db "PFRC1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PFRC1A
+XT_PFRC1A:
+ .dw PFA_DOVARIABLE
+PFA_PFRC1A:
+ .dw 236
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 1 Control Register
+VE_PCTL1:
+ .dw $ff05
+ .db "PCTL1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCTL1
+XT_PCTL1:
+ .dw PFA_DOVARIABLE
+PFA_PCTL1:
+ .dw 235
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 1 Configuration Register
+VE_PCNF1:
+ .dw $ff05
+ .db "PCNF1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCNF1
+XT_PCNF1:
+ .dw PFA_DOVARIABLE
+PFA_PCNF1:
+ .dw 234
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare RB Register
+VE_OCR1RB:
+ .dw $ff06
+ .db "OCR1RB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1RB
+XT_OCR1RB:
+ .dw PFA_DOVARIABLE
+PFA_OCR1RB:
+ .dw 232
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare SB Register
+VE_OCR1SB:
+ .dw $ff06
+ .db "OCR1SB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1SB
+XT_OCR1SB:
+ .dw PFA_DOVARIABLE
+PFA_OCR1SB:
+ .dw 230
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare RA Register
+VE_OCR1RA:
+ .dw $ff06
+ .db "OCR1RA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1RA
+XT_OCR1RA:
+ .dw PFA_DOVARIABLE
+PFA_OCR1RA:
+ .dw 228
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare SA Register
+VE_OCR1SA:
+ .dw $ff06
+ .db "OCR1SA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1SA
+XT_OCR1SA:
+ .dw PFA_DOVARIABLE
+PFA_OCR1SA:
+ .dw 226
+; ( -- addr ) System Constant
+; R( -- )
+; PSC1 Synchro and Output Configuration
+VE_PSOC1:
+ .dw $ff05
+ .db "PSOC1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PSOC1
+XT_PSOC1:
+ .dw PFA_DOVARIABLE
+PFA_PSOC1:
+ .dw 224
+; ( -- addr ) System Constant
+; R( -- )
+; PSC1 Interrupt Mask Register
+VE_PIM1:
+ .dw $ff04
+ .db "PIM1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIM1
+XT_PIM1:
+ .dw PFA_DOVARIABLE
+PFA_PIM1:
+ .dw 163
+; ( -- addr ) System Constant
+; R( -- )
+; PSC1 Interrupt Flag Register
+VE_PIFR1:
+ .dw $ff05
+ .db "PIFR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIFR1
+XT_PIFR1:
+ .dw PFA_DOVARIABLE
+PFA_PIFR1:
+ .dw 162
+
+.endif
+.if WANT_PSC2 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 2 Input Capture Register
+VE_PICR2:
+ .dw $ff05
+ .db "PICR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PICR2
+XT_PICR2:
+ .dw PFA_DOVARIABLE
+PFA_PICR2:
+ .dw 254
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 2 Input B Control
+VE_PFRC2B:
+ .dw $ff06
+ .db "PFRC2B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PFRC2B
+XT_PFRC2B:
+ .dw PFA_DOVARIABLE
+PFA_PFRC2B:
+ .dw 253
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 2 Input B Control
+VE_PFRC2A:
+ .dw $ff06
+ .db "PFRC2A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PFRC2A
+XT_PFRC2A:
+ .dw PFA_DOVARIABLE
+PFA_PFRC2A:
+ .dw 252
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 2 Control Register
+VE_PCTL2:
+ .dw $ff05
+ .db "PCTL2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCTL2
+XT_PCTL2:
+ .dw PFA_DOVARIABLE
+PFA_PCTL2:
+ .dw 251
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 2 Configuration Register
+VE_PCNF2:
+ .dw $ff05
+ .db "PCNF2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCNF2
+XT_PCNF2:
+ .dw PFA_DOVARIABLE
+PFA_PCNF2:
+ .dw 250
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare RB Register
+VE_OCR2RB:
+ .dw $ff06
+ .db "OCR2RB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2RB
+XT_OCR2RB:
+ .dw PFA_DOVARIABLE
+PFA_OCR2RB:
+ .dw 248
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare SB Register
+VE_OCR2SB:
+ .dw $ff06
+ .db "OCR2SB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2SB
+XT_OCR2SB:
+ .dw PFA_DOVARIABLE
+PFA_OCR2SB:
+ .dw 246
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare RA Register
+VE_OCR2RA:
+ .dw $ff06
+ .db "OCR2RA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2RA
+XT_OCR2RA:
+ .dw PFA_DOVARIABLE
+PFA_OCR2RA:
+ .dw 244
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare SA Register
+VE_OCR2SA:
+ .dw $ff06
+ .db "OCR2SA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2SA
+XT_OCR2SA:
+ .dw PFA_DOVARIABLE
+PFA_OCR2SA:
+ .dw 242
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 2 Output Matrix
+VE_POM2:
+ .dw $ff04
+ .db "POM2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_POM2
+XT_POM2:
+ .dw PFA_DOVARIABLE
+PFA_POM2:
+ .dw 241
+; ( -- addr ) System Constant
+; R( -- )
+; PSC2 Synchro and Output Configuration
+VE_PSOC2:
+ .dw $ff05
+ .db "PSOC2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PSOC2
+XT_PSOC2:
+ .dw PFA_DOVARIABLE
+PFA_PSOC2:
+ .dw 240
+; ( -- addr ) System Constant
+; R( -- )
+; PSC2 Interrupt Mask Register
+VE_PIM2:
+ .dw $ff04
+ .db "PIM2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIM2
+XT_PIM2:
+ .dw PFA_DOVARIABLE
+PFA_PIM2:
+ .dw 165
+; ( -- addr ) System Constant
+; R( -- )
+; PSC2 Interrupt Flag Register
+VE_PIFR2:
+ .dw $ff05
+ .db "PIFR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIFR2
+XT_PIFR2:
+ .dw PFA_DOVARIABLE
+PFA_PIFR2:
+ .dw 164
+
+.endif
diff --git a/amforth-6.5/avr8/devices/at90pwm3b/device.py b/amforth-6.5/avr8/devices/at90pwm3b/device.py
new file mode 100644
index 0000000..a547e53
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90pwm3b/device.py
@@ -0,0 +1,505 @@
+# Generated Automatically
+
+# Partname AT90PWM3B
+
+MCUREGS = {
+# Interrupt Vectors
+ 'PSC2_CAPTAddr' : '#2', # PSC2 Capture Event
+ 'PSC2_ECAddr' : '#4', # PSC2 End Cycle
+ 'PSC1_CAPTAddr' : '#6', # PSC1 Capture Event
+ 'PSC1_ECAddr' : '#8', # PSC1 End Cycle
+ 'PSC0_CAPTAddr' : '#10', # PSC0 Capture Event
+ 'PSC0_ECAddr' : '#12', # PSC0 End Cycle
+ 'ANALOG_COMP_0Addr' : '#14', # Analog Comparator 0
+ 'ANALOG_COMP_1Addr' : '#16', # Analog Comparator 1
+ 'ANALOG_COMP_2Addr' : '#18', # Analog Comparator 2
+ 'INT0Addr' : '#20', # External Interrupt Request 0
+ 'TIMER1_CAPTAddr' : '#22', # Timer/Counter1 Capture Event
+ 'TIMER1_COMPAAddr' : '#24', # Timer/Counter1 Compare Match A
+ 'TIMER1_COMPBAddr' : '#26', # Timer/Counter Compare Match B
+ 'RESERVED15Addr' : '#28', #
+ 'TIMER1_OVFAddr' : '#30', # Timer/Counter1 Overflow
+ 'TIMER0_COMP_AAddr' : '#32', # Timer/Counter0 Compare Match A
+ 'TIMER0_OVFAddr' : '#34', # Timer/Counter0 Overflow
+ 'ADCAddr' : '#36', # ADC Conversion Complete
+ 'INT1Addr' : '#38', # External Interrupt Request 1
+ 'SPI_STCAddr' : '#40', # SPI Serial Transfer Complete
+ 'USART_RXAddr' : '#42', # USART, Rx Complete
+ 'USART_UDREAddr' : '#44', # USART Data Register Empty
+ 'USART_TXAddr' : '#46', # USART, Tx Complete
+ 'INT2Addr' : '#48', # External Interrupt Request 2
+ 'WDTAddr' : '#50', # Watchdog Timeout Interrupt
+ 'EE_READYAddr' : '#52', # EEPROM Ready
+ 'TIMER0_COMPBAddr' : '#54', # Timer Counter 0 Compare Match B
+ 'INT3Addr' : '#56', # External Interrupt Request 3
+ 'RESERVED30Addr' : '#58', #
+ 'RESERVED31Addr' : '#60', #
+ 'SPM_READYAddr' : '#62', # Store Program Memory Read
+
+# Module PORTB
+ 'PORTB' : '$25', # Port B Data Register
+ 'DDRB' : '$24', # Port B Data Direction Register
+ 'PINB' : '$23', # Port B Input Pins
+
+# Module PORTC
+ 'PORTC' : '$28', # Port C Data Register
+ 'DDRC' : '$27', # Port C Data Direction Register
+ 'PINC' : '$26', # Port C Input Pins
+
+# Module PORTD
+ 'PORTD' : '$2b', # Port D Data Register
+ 'DDRD' : '$2a', # Port D Data Direction Register
+ 'PIND' : '$29', # Port D Input Pins
+
+# Module BOOT_LOAD
+ 'SPMCSR' : '$57', # Store Program Memory Control R
+ 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
+ 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
+ 'SPMCSR_RWWSRE': '$10', # Read While Write section read
+ 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
+ 'SPMCSR_PGWRT': '$4', # Page Write
+ 'SPMCSR_PGERS': '$2', # Page Erase
+ 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
+
+# Module EUSART
+ 'EUDR' : '$ce', # EUSART I/O Data Register
+ 'EUCSRA' : '$c8', # EUSART Control and Status Regi
+ 'EUCSRA_UTxS': '$f0', # EUSART Control and Status Regi
+ 'EUCSRA_URxS': '$f', # EUSART Control and Status Regi
+ 'EUCSRB' : '$c9', # EUSART Control Register B
+ 'EUCSRB_EUSART': '$10', # EUSART Enable Bit
+ 'EUCSRB_EUSBS': '$8', # EUSBS Enable Bit
+ 'EUCSRB_EMCH': '$2', # Manchester Mode Bit
+ 'EUCSRB_BODR': '$1', # Order Bit
+ 'EUCSRC' : '$ca', # EUSART Status Register C
+ 'EUCSRC_FEM': '$8', # Frame Error Manchester Bit
+ 'EUCSRC_F1617': '$4', # F1617 Bit
+ 'EUCSRC_STP': '$3', # Stop Bits
+ 'MUBRRH' : '$cd', # Manchester Receiver Baud Rate
+ 'MUBRRH_MUBRR': '$ff', # Manchester Receiver Baud Rate
+ 'MUBRRL' : '$cc', # Manchester Receiver Baud Rate
+ 'MUBRRL_MUBRR': '$ff', # Manchester Receiver Baud Rate
+
+# Module ANALOG_COMPARATOR
+ 'AC0CON' : '$ad', # Analog Comparator 0 Control Re
+ 'AC0CON_AC0EN': '$80', # Analog Comparator 0 Enable Bit
+ 'AC0CON_AC0IE': '$40', # Analog Comparator 0 Interrupt
+ 'AC0CON_AC0IS': '$30', # Analog Comparator 0 Interrupt
+ 'AC0CON_AC0M': '$7', # Analog Comparator 0 Multiplexe
+ 'AC1CON' : '$ae', # Analog Comparator 1 Control Re
+ 'AC1CON_AC1EN': '$80', # Analog Comparator 1 Enable Bit
+ 'AC1CON_AC1IE': '$40', # Analog Comparator 1 Interrupt
+ 'AC1CON_AC1IS': '$30', # Analog Comparator 1 Interrupt
+ 'AC1CON_AC1ICE': '$8', # Analog Comparator 1 Interrupt
+ 'AC1CON_AC1M': '$7', # Analog Comparator 1 Multiplexe
+ 'AC2CON' : '$af', # Analog Comparator 2 Control Re
+ 'AC2CON_AC2EN': '$80', # Analog Comparator 2 Enable Bit
+ 'AC2CON_AC2IE': '$40', # Analog Comparator 2 Interrupt
+ 'AC2CON_AC2IS': '$30', # Analog Comparator 2 Interrupt
+ 'AC2CON_AC2M': '$7', # Analog Comparator 2 Multiplexe
+ 'ACSR' : '$50', # Analog Comparator Status Regis
+ 'ACSR_ACCKDIV': '$80', # Analog Comparator Clock Divide
+ 'ACSR_AC2IF': '$40', # Analog Comparator 2 Interrupt
+ 'ACSR_AC1IF': '$20', # Analog Comparator 1 Interrupt
+ 'ACSR_AC0IF': '$10', # Analog Comparator 0 Interrupt
+ 'ACSR_AC2O': '$4', # Analog Comparator 2 Output Bit
+ 'ACSR_AC1O': '$2', # Analog Comparator 1 Output Bit
+ 'ACSR_AC0O': '$1', # Analog Comparator 0 Output Bit
+
+# Module DA_CONVERTER
+ 'DACH' : '$ac', # DAC Data Register High Byte
+ 'DACH_DACH': '$ff', # DAC Data Register High Byte Bi
+ 'DACL' : '$ab', # DAC Data Register Low Byte
+ 'DACL_DACL': '$ff', # DAC Data Register Low Byte Bit
+ 'DACON' : '$aa', # DAC Control Register
+ 'DACON_DAATE': '$80', # DAC Auto Trigger Enable Bit
+ 'DACON_DATS': '$70', # DAC Trigger Selection Bits
+ 'DACON_DALA': '$4', # DAC Left Adjust
+ 'DACON_DAEN': '$1', # DAC Enable Bit
+
+# Module CPU
+ 'SREG' : '$5f', # Status Register
+ 'SREG_I': '$80', # Global Interrupt Enable
+ 'SREG_T': '$40', # Bit Copy Storage
+ 'SREG_H': '$20', # Half Carry Flag
+ 'SREG_S': '$10', # Sign Bit
+ 'SREG_V': '$8', # Two's Complement Overflow Flag
+ 'SREG_N': '$4', # Negative Flag
+ 'SREG_Z': '$2', # Zero Flag
+ 'SREG_C': '$1', # Carry Flag
+ 'SP' : '$5d', # Stack Pointer
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_SPIPS': '$80', # SPI Pin Select
+ 'MCUCR_PUD': '$10', # Pull-up disable
+ 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
+ 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
+ 'MCUSR_BORF': '$4', # Brown-out Reset Flag
+ 'MCUSR_EXTRF': '$2', # External Reset Flag
+ 'MCUSR_PORF': '$1', # Power-on reset flag
+ 'OSCCAL' : '$66', # Oscillator Calibration Value
+ 'CLKPR' : '$61', #
+ 'CLKPR_CLKPCE': '$80', #
+ 'CLKPR_CLKPS': '$f', #
+ 'SMCR' : '$53', # Sleep Mode Control Register
+ 'SMCR_SM': '$e', # Sleep Mode Select bits
+ 'SMCR_SE': '$1', # Sleep Enable
+ 'GPIOR3' : '$3b', # General Purpose IO Register 3
+ 'GPIOR3_GPIOR': '$ff', # General Purpose IO Register 3
+ 'GPIOR2' : '$3a', # General Purpose IO Register 2
+ 'GPIOR2_GPIOR': '$ff', # General Purpose IO Register 2
+ 'GPIOR1' : '$39', # General Purpose IO Register 1
+ 'GPIOR1_GPIOR': '$ff', # General Purpose IO Register 1
+ 'GPIOR0' : '$3e', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR07': '$80', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR06': '$40', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR05': '$20', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR04': '$10', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR03': '$8', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR02': '$4', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR01': '$2', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR00': '$1', # General Purpose IO Register 0
+ 'PLLCSR' : '$49', # PLL Control And Status Registe
+ 'PLLCSR_PLLF': '$4', # PLL Factor
+ 'PLLCSR_PLLE': '$2', # PLL Enable
+ 'PLLCSR_PLOCK': '$1', # PLL Lock Detector
+ 'PRR' : '$64', # Power Reduction Register
+ 'PRR_PRPSC': '$e0', # Power Reduction PSC2
+ 'PRR_PRTIM1': '$10', # Power Reduction Timer/Counter1
+ 'PRR_PRTIM0': '$8', # Power Reduction Timer/Counter0
+ 'PRR_PRSPI': '$4', # Power Reduction Serial Periphe
+ 'PRR_PRUSART0': '$2', # Power Reduction USART
+ 'PRR_PRADC': '$1', # Power Reduction ADC
+
+# Module PORTE
+ 'PORTE' : '$2e', # Port E Data Register
+ 'DDRE' : '$2d', # Port E Data Direction Register
+ 'PINE' : '$2c', # Port E Input Pins
+
+# Module TIMER_COUNTER_0
+ 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
+ 'TIMSK0_OCIE0B': '$4', # Timer/Counter0 Output Compare
+ 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
+ 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
+ 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
+ 'TIFR0_OCF0B': '$4', # Timer/Counter0 Output Compare
+ 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
+ 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
+ 'TCCR0A' : '$44', # Timer/Counter Control Registe
+ 'TCCR0A_COM0A': '$c0', # Compare Output Mode, Phase Cor
+ 'TCCR0A_COM0B': '$30', # Compare Output Mode, Fast PWm
+ 'TCCR0A_WGM0': '$3', # Waveform Generation Mode
+ 'TCCR0B' : '$45', # Timer/Counter Control Register
+ 'TCCR0B_FOC0A': '$80', # Force Output Compare A
+ 'TCCR0B_FOC0B': '$40', # Force Output Compare B
+ 'TCCR0B_WGM02': '$8', #
+ 'TCCR0B_CS0': '$7', # Clock Select
+ 'TCNT0' : '$46', # Timer/Counter0
+ 'OCR0A' : '$47', # Timer/Counter0 Output Compare
+ 'OCR0B' : '$48', # Timer/Counter0 Output Compare
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_ICPSEL1': '$40', # Timer1 Input Capture Selection
+ 'GTCCR_PSR10': '$1', # Prescaler Reset Timer/Counter1
+
+# Module TIMER_COUNTER_1
+ 'TIMSK1' : '$6f', # Timer/Counter Interrupt Mask R
+ 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
+ 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output CompareB
+ 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output CompareA
+ 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
+ 'TIFR1' : '$36', # Timer/Counter Interrupt Flag r
+ 'TIFR1_ICF1': '$20', # Input Capture Flag 1
+ 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
+ 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
+ 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
+ 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
+ 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
+ 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
+ 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
+ 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
+ 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
+ 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
+ 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
+ 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
+ 'TCCR1C' : '$82', # Timer/Counter1 Control Registe
+ 'TCCR1C_FOC1A': '$80', #
+ 'TCCR1C_FOC1B': '$40', #
+ 'TCNT1' : '$84', # Timer/Counter1 Bytes
+ 'OCR1A' : '$88', # Timer/Counter1 Output Compare
+ 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
+ 'ICR1' : '$86', # Timer/Counter1 Input Capture R
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSRSYNC': '$1', # Prescaler Reset Timer/Counter1
+
+# Module AD_CONVERTER
+ 'ADMUX' : '$7c', # The ADC multiplexer Selection
+ 'ADMUX_REFS': '$c0', # Reference Selection Bits
+ 'ADMUX_ADLAR': '$20', # Left Adjust Result
+ 'ADMUX_MUX': '$f', # Analog Channel and Gain Select
+ 'ADCSRA' : '$7a', # The ADC Control and Status reg
+ 'ADCSRA_ADEN': '$80', # ADC Enable
+ 'ADCSRA_ADSC': '$40', # ADC Start Conversion
+ 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
+ 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
+ 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
+ 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
+ 'ADC' : '$78', # ADC Data Register Bytes
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'DIDR0' : '$7e', # Digital Input Disable Register
+ 'DIDR1' : '$7f', # Digital Input Disable Register
+ 'DIDR1_ACMP0D': '$20', #
+ 'DIDR1_AMP0PD': '$10', #
+ 'DIDR1_AMP0ND': '$8', #
+ 'DIDR1_ADC10D': '$4', #
+ 'DIDR1_ADC9D': '$2', #
+ 'DIDR1_ADC8D': '$1', #
+ 'AMP0CSR' : '$76', #
+ 'AMP0CSR_AMP0EN': '$80', #
+ 'AMP0CSR_AMP0IS': '$40', #
+ 'AMP0CSR_AMP0G': '$30', #
+ 'AMP0CSR_AMP0TS': '$3', #
+ 'AMP1CSR' : '$77', #
+ 'AMP1CSR_AMP1EN': '$80', #
+ 'AMP1CSR_AMP1IS': '$40', #
+ 'AMP1CSR_AMP1G': '$30', #
+ 'AMP1CSR_AMP1TS': '$3', #
+
+# Module USART
+ 'UDR' : '$c6', # USART I/O Data Register
+ 'UCSRA' : '$c0', # USART Control and Status regis
+ 'UCSRA_RXC': '$80', # USART Receive Complete
+ 'UCSRA_TXC': '$40', # USART Transmitt Complete
+ 'UCSRA_UDRE': '$20', # USART Data Register Empty
+ 'UCSRA_FE': '$10', # Framing Error
+ 'UCSRA_DOR': '$8', # Data Overrun
+ 'UCSRA_UPE': '$4', # USART Parity Error
+ 'UCSRA_U2X': '$2', # Double USART Transmission Bit
+ 'UCSRA_MPCM': '$1', # Multi-processor Communication
+ 'UCSRB' : '$c1', # USART Control an Status regist
+ 'UCSRB_RXCIE': '$80', # RX Complete Interrupt Enable
+ 'UCSRB_TXCIE': '$40', # TX Complete Interrupt Enable
+ 'UCSRB_UDRIE': '$20', # USART Data Register Empty Inte
+ 'UCSRB_RXEN': '$10', # Receiver Enable
+ 'UCSRB_TXEN': '$8', # Transmitter Enable
+ 'UCSRB_UCSZ2': '$4', # Character Size
+ 'UCSRB_RXB8': '$2', # Receive Data Bit 8
+ 'UCSRB_TXB8': '$1', # Transmit Data Bit 8
+ 'UCSRC' : '$c2', # USART Control an Status regist
+ 'UCSRC_UMSEL0': '$40', # USART Mode Select
+ 'UCSRC_UPM': '$30', # Parity Mode Bits
+ 'UCSRC_USBS': '$8', # Stop Bit Select
+ 'UCSRC_UCSZ': '$6', # Character Size Bits
+ 'UCSRC_UCPOL': '$1', # Clock Polarity
+ 'UBRRH' : '$c5', # USART Baud Rate Register High
+ 'UBRRH_UBRR': '$f', # USART Baud Rate Register Bits
+ 'UBRRL' : '$c4', # USART Baud Rate Register Low B
+ 'UBRRL_UBRR': '$ff', # USART Baud Rate Register bits
+
+# Module SPI
+ 'SPCR' : '$4c', # SPI Control Register
+ 'SPCR_SPIE': '$80', # SPI Interrupt Enable
+ 'SPCR_SPE': '$40', # SPI Enable
+ 'SPCR_DORD': '$20', # Data Order
+ 'SPCR_MSTR': '$10', # Master/Slave Select
+ 'SPCR_CPOL': '$8', # Clock polarity
+ 'SPCR_CPHA': '$4', # Clock Phase
+ 'SPCR_SPR': '$3', # SPI Clock Rate Selects
+ 'SPSR' : '$4d', # SPI Status Register
+ 'SPSR_SPIF': '$80', # SPI Interrupt Flag
+ 'SPSR_WCOL': '$40', # Write Collision Flag
+ 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
+ 'SPDR' : '$4e', # SPI Data Register
+
+# Module WATCHDOG
+ 'WDTCSR' : '$60', # Watchdog Timer Control Registe
+ 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
+ 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
+ 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
+ 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
+ 'WDTCSR_WDE': '$8', # Watch Dog Enable
+
+# Module EXTERNAL_INTERRUPT
+ 'EICRA' : '$69', # External Interrupt Control Reg
+ 'EICRA_ISC3': '$c0', # External Interrupt Sense Contr
+ 'EICRA_ISC2': '$30', # External Interrupt Sense Contr
+ 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
+ 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
+ 'EIMSK' : '$3d', # External Interrupt Mask Regist
+ 'EIMSK_INT': '$f', # External Interrupt Request 3 E
+ 'EIFR' : '$3c', # External Interrupt Flag Regist
+ 'EIFR_INTF': '$f', # External Interrupt Flags
+
+# Module EEPROM
+ 'EEAR' : '$41', # EEPROM Read/Write Access Byte
+ 'EEDR' : '$40', # EEPROM Data Register
+ 'EECR' : '$3f', # EEPROM Control Register
+ 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
+ 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
+ 'EECR_EEWE': '$2', # EEPROM Write Enable
+ 'EECR_EERE': '$1', # EEPROM Read Enable
+
+# Module PSC0
+ 'PICR0' : '$de', # PSC 0 Input Capture Register
+ 'PFRC0B' : '$dd', # PSC 0 Input B Control
+ 'PFRC0B_PCAE0B': '$80', # PSC 0 Capture Enable Input Par
+ 'PFRC0B_PISEL0B': '$40', # PSC 0 Input Select for Part B
+ 'PFRC0B_PELEV0B': '$20', # PSC 0 Edge Level Selector on I
+ 'PFRC0B_PFLTE0B': '$10', # PSC 0 Filter Enable on Input P
+ 'PFRC0B_PRFM0B': '$f', # PSC 0 Retrigger and Fault Mode
+ 'PFRC0A' : '$dc', # PSC 0 Input A Control
+ 'PFRC0A_PCAE0A': '$80', # PSC 0 Capture Enable Input Par
+ 'PFRC0A_PISEL0A': '$40', # PSC 0 Input Select for Part A
+ 'PFRC0A_PELEV0A': '$20', # PSC 0 Edge Level Selector on I
+ 'PFRC0A_PFLTE0A': '$10', # PSC 0 Filter Enable on Input P
+ 'PFRC0A_PRFM0A': '$f', # PSC 0 Retrigger and Fault Mode
+ 'PCTL0' : '$db', # PSC 0 Control Register
+ 'PCTL0_PPRE0': '$c0', # PSC 0 Prescaler Selects
+ 'PCTL0_PBFM0': '$20', # PSC 0 Balance Flank Width Modu
+ 'PCTL0_PAOC0B': '$10', # PSC 0 Asynchronous Output Cont
+ 'PCTL0_PAOC0A': '$8', # PSC 0 Asynchronous Output Cont
+ 'PCTL0_PARUN0': '$4', # PSC0 Auto Run
+ 'PCTL0_PCCYC0': '$2', # PSC0 Complete Cycle
+ 'PCTL0_PRUN0': '$1', # PSC 0 Run
+ 'PCNF0' : '$da', # PSC 0 Configuration Register
+ 'PCNF0_PFIFTY0': '$80', # PSC 0 Fifty
+ 'PCNF0_PALOCK0': '$40', # PSC 0 Autolock
+ 'PCNF0_PLOCK0': '$20', # PSC 0 Lock
+ 'PCNF0_PMODE0': '$18', # PSC 0 Mode
+ 'PCNF0_POP0': '$4', # PSC 0 Output Polarity
+ 'PCNF0_PCLKSEL0': '$2', # PSC 0 Input Clock Select
+ 'OCR0RB' : '$d8', # Output Compare RB Register
+ 'OCR0SB' : '$d6', # Output Compare SB Register
+ 'OCR0RA' : '$d4', # Output Compare RA Register
+ 'OCR0SA' : '$d2', # Output Compare SA Register
+ 'PSOC0' : '$d0', # PSC0 Synchro and Output Config
+ 'PSOC0_PSYNC0': '$30', # Synchronization Out for ADC Se
+ 'PSOC0_POEN0B': '$4', # PSCOUT01 Output Enable
+ 'PSOC0_POEN0A': '$1', # PSCOUT00 Output Enable
+ 'PIM0' : '$a1', # PSC0 Interrupt Mask Register
+ 'PIM0_PSEIE0': '$20', # PSC 0 Synchro Error Interrupt
+ 'PIM0_PEVE0B': '$10', # External Event B Interrupt Ena
+ 'PIM0_PEVE0A': '$8', # External Event A Interrupt Ena
+ 'PIM0_PEOPE0': '$1', # End of Cycle Interrupt Enable
+ 'PIFR0' : '$a0', # PSC0 Interrupt Flag Register
+ 'PIFR0_POAC0B': '$80', # PSC 0 Output A Activity
+ 'PIFR0_POAC0A': '$40', # PSC 0 Output A Activity
+ 'PIFR0_PSEI0': '$20', # PSC 0 Synchro Error Interrupt
+ 'PIFR0_PEV0B': '$10', # External Event B Interrupt
+ 'PIFR0_PEV0A': '$8', # External Event A Interrupt
+ 'PIFR0_PRN0': '$6', # Ramp Number
+ 'PIFR0_PEOP0': '$1', # End of PSC0 Interrupt
+
+# Module PSC1
+ 'PICR1' : '$ee', # PSC 1 Input Capture Register
+ 'PFRC1B' : '$ed', # PSC 1 Input B Control
+ 'PFRC1B_PCAE1B': '$80', # PSC 1 Capture Enable Input Par
+ 'PFRC1B_PISEL1B': '$40', # PSC 1 Input Select for Part B
+ 'PFRC1B_PELEV1B': '$20', # PSC 1 Edge Level Selector on I
+ 'PFRC1B_PFLTE1B': '$10', # PSC 1 Filter Enable on Input P
+ 'PFRC1B_PRFM1B': '$f', # PSC 1 Retrigger and Fault Mode
+ 'PFRC1A' : '$ec', # PSC 1 Input B Control
+ 'PFRC1A_PCAE1A': '$80', # PSC 1 Capture Enable Input Par
+ 'PFRC1A_PISEL1A': '$40', # PSC 1 Input Select for Part A
+ 'PFRC1A_PELEV1A': '$20', # PSC 1 Edge Level Selector on I
+ 'PFRC1A_PFLTE1A': '$10', # PSC 1 Filter Enable on Input P
+ 'PFRC1A_PRFM1A': '$f', # PSC 1 Retrigger and Fault Mode
+ 'PCTL1' : '$eb', # PSC 1 Control Register
+ 'PCTL1_PPRE1': '$c0', # PSC 1 Prescaler Selects
+ 'PCTL1_PBFM1': '$20', # Balance Flank Width Modulation
+ 'PCTL1_PAOC1B': '$10', # PSC 1 Asynchronous Output Cont
+ 'PCTL1_PAOC1A': '$8', # PSC 1 Asynchronous Output Cont
+ 'PCTL1_PARUN1': '$4', # PSC1 Auto Run
+ 'PCTL1_PCCYC1': '$2', # PSC1 Complete Cycle
+ 'PCTL1_PRUN1': '$1', # PSC 1 Run
+ 'PCNF1' : '$ea', # PSC 1 Configuration Register
+ 'PCNF1_PFIFTY1': '$80', # PSC 1 Fifty
+ 'PCNF1_PALOCK1': '$40', # PSC 1 Autolock
+ 'PCNF1_PLOCK1': '$20', # PSC 1 Lock
+ 'PCNF1_PMODE1': '$18', # PSC 1 Mode
+ 'PCNF1_POP1': '$4', # PSC 1 Output Polarity
+ 'PCNF1_PCLKSEL1': '$2', # PSC 1 Input Clock Select
+ 'OCR1RB' : '$e8', # Output Compare RB Register
+ 'OCR1SB' : '$e6', # Output Compare SB Register
+ 'OCR1RA' : '$e4', # Output Compare RA Register
+ 'OCR1SA' : '$e2', # Output Compare SA Register
+ 'PSOC1' : '$e0', # PSC1 Synchro and Output Config
+ 'PSOC1_PSYNC1_': '$30', # Synchronization Out for ADC Se
+ 'PSOC1_POEN1B': '$4', # PSCOUT11 Output Enable
+ 'PSOC1_POEN1A': '$1', # PSCOUT10 Output Enable
+ 'PIM1' : '$a3', # PSC1 Interrupt Mask Register
+ 'PIM1_PSEIE1': '$20', # PSC 1 Synchro Error Interrupt
+ 'PIM1_PEVE1B': '$10', # External Event B Interrupt Ena
+ 'PIM1_PEVE1A': '$8', # External Event A Interrupt Ena
+ 'PIM1_PEOPE1': '$1', # End of Cycle Interrupt Enable
+ 'PIFR1' : '$a2', # PSC1 Interrupt Flag Register
+ 'PIFR1_POAC1B': '$80', # PSC 1 Output B Activity
+ 'PIFR1_POAC1A': '$40', # PSC 1 Output A Activity
+ 'PIFR1_PSEI1': '$20', # PSC 1 Synchro Error Interrupt
+ 'PIFR1_PEV1B': '$10', # External Event B Interrupt
+ 'PIFR1_PEV1A': '$8', # External Event A Interrupt
+ 'PIFR1_PRN1': '$6', # Ramp Number
+ 'PIFR1_PEOP1': '$1', # End of PSC1 Interrupt
+
+# Module PSC2
+ 'PICR2' : '$fe', # PSC 2 Input Capture Register
+ 'PFRC2B' : '$fd', # PSC 2 Input B Control
+ 'PFRC2B_PCAE2B': '$80', # PSC 2 Capture Enable Input Par
+ 'PFRC2B_PISEL2B': '$40', # PSC 2 Input Select for Part B
+ 'PFRC2B_PELEV2B': '$20', # PSC 2 Edge Level Selector on I
+ 'PFRC2B_PFLTE2B': '$10', # PSC 2 Filter Enable on Input P
+ 'PFRC2B_PRFM2B': '$f', # PSC 2 Retrigger and Fault Mode
+ 'PFRC2A' : '$fc', # PSC 2 Input B Control
+ 'PFRC2A_PCAE2A': '$80', # PSC 2 Capture Enable Input Par
+ 'PFRC2A_PISEL2A': '$40', # PSC 2 Input Select for Part A
+ 'PFRC2A_PELEV2A': '$20', # PSC 2 Edge Level Selector on I
+ 'PFRC2A_PFLTE2A': '$10', # PSC 2 Filter Enable on Input P
+ 'PFRC2A_PRFM2A': '$f', # PSC 2 Retrigger and Fault Mode
+ 'PCTL2' : '$fb', # PSC 2 Control Register
+ 'PCTL2_PPRE2': '$c0', # PSC 2 Prescaler Selects
+ 'PCTL2_PBFM2': '$20', # Balance Flank Width Modulation
+ 'PCTL2_PAOC2B': '$10', # PSC 2 Asynchronous Output Cont
+ 'PCTL2_PAOC2A': '$8', # PSC 2 Asynchronous Output Cont
+ 'PCTL2_PARUN2': '$4', # PSC2 Auto Run
+ 'PCTL2_PCCYC2': '$2', # PSC2 Complete Cycle
+ 'PCTL2_PRUN2': '$1', # PSC 2 Run
+ 'PCNF2' : '$fa', # PSC 2 Configuration Register
+ 'PCNF2_PFIFTY2': '$80', # PSC 2 Fifty
+ 'PCNF2_PALOCK2': '$40', # PSC 2 Autolock
+ 'PCNF2_PLOCK2': '$20', # PSC 2 Lock
+ 'PCNF2_PMODE2': '$18', # PSC 2 Mode
+ 'PCNF2_POP2': '$4', # PSC 2 Output Polarity
+ 'PCNF2_PCLKSEL2': '$2', # PSC 2 Input Clock Select
+ 'PCNF2_POME2': '$1', # PSC 2 Output Matrix Enable
+ 'OCR2RB' : '$f8', # Output Compare RB Register
+ 'OCR2SB' : '$f6', # Output Compare SB Register
+ 'OCR2RA' : '$f4', # Output Compare RA Register
+ 'OCR2SA' : '$f2', # Output Compare SA Register
+ 'POM2' : '$f1', # PSC 2 Output Matrix
+ 'POM2_POMV2B': '$f0', # Output Matrix Output B Ramps
+ 'POM2_POMV2A': '$f', # Output Matrix Output A Ramps
+ 'PSOC2' : '$f0', # PSC2 Synchro and Output Config
+ 'PSOC2_POS2': '$c0', # PSC 2 Output 23 Select
+ 'PSOC2_PSYNC2_': '$30', # Synchronization Out for ADC Se
+ 'PSOC2_POEN2D': '$8', # PSCOUT23 Output Enable
+ 'PSOC2_POEN2B': '$4', # PSCOUT21 Output Enable
+ 'PSOC2_POEN2C': '$2', # PSCOUT22 Output Enable
+ 'PSOC2_POEN2A': '$1', # PSCOUT20 Output Enable
+ 'PIM2' : '$a5', # PSC2 Interrupt Mask Register
+ 'PIM2_PSEIE2': '$20', # PSC 2 Synchro Error Interrupt
+ 'PIM2_PEVE2B': '$10', # External Event B Interrupt Ena
+ 'PIM2_PEVE2A': '$8', # External Event A Interrupt Ena
+ 'PIM2_PEOPE2': '$1', # End of Cycle Interrupt Enable
+ 'PIFR2' : '$a4', # PSC2 Interrupt Flag Register
+ 'PIFR2_POAC2B': '$80', # PSC 2 Output A Activity
+ 'PIFR2_POAC2A': '$40', # PSC 2 Output A Activity
+ 'PIFR2_PSEI2': '$20', # PSC 2 Synchro Error Interrupt
+ 'PIFR2_PEV2B': '$10', # External Event B Interrupt
+ 'PIFR2_PEV2A': '$8', # External Event A Interrupt
+ 'PIFR2_PRN2': '$6', # Ramp Number
+ 'PIFR2_PEOP2': '$1', # End of PSC2 Interrupt
+
+ '__amforth_dummy':'0'
+}
diff --git a/amforth-6.5/avr8/devices/at90pwm3b/words/no-jtag.asm b/amforth-6.5/avr8/devices/at90pwm3b/words/no-jtag.asm
new file mode 100644
index 0000000..352a4bb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90pwm3b/words/no-jtag.asm
@@ -0,0 +1,14 @@
+; ( -- )
+; ( -- )
+; MCU
+; disable jtag at runtime
+VE_NOJTAG:
+ .dw $FF05
+ .db "-jtag",0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOJTAG
+XT_NOJTAG:
+ .dw PFA_NOJTAG
+PFA_NOJTAG:
+
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/at90pwm3b/words/no-wdt.asm b/amforth-6.5/avr8/devices/at90pwm3b/words/no-wdt.asm
new file mode 100644
index 0000000..ff6ddd1
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90pwm3b/words/no-wdt.asm
@@ -0,0 +1,34 @@
+; ( -- )
+; MCU
+; disable watch dog timer at runtime
+VE_NOWDT:
+ .dw $ff04
+ .db "-wdt"
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOWDT
+XT_NOWDT:
+ .dw PFA_NOWDT
+PFA_NOWDT:
+
+ in temp1,SREG
+ push temp1
+ ; Turn always off global interrupt.
+ cli
+ ; Reset Watchdog Timer
+ wdr
+ ; Clear WDRF in MCUSR
+ in temp1, MCUSR
+ andi temp1, (0xff & (0<<WDRF))
+ out MCUSR, temp1
+ ; Write logical one to WDCE and WDE
+ ; Keep old prescaler setting to prevent unintentional time-out
+ in_ temp1, WDTCSR
+ ori temp1, (1<<WDCE) | (1<<WDE)
+ out_ WDTCSR, temp1
+ ; Turn off WDT
+ ldi temp1, (0<<WDE)
+ out_ WDTCSR, temp1
+ ; restore status register
+ pop temp1
+ out SREG,temp1
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/at90pwm3b/words/sleep.asm b/amforth-6.5/avr8/devices/at90pwm3b/words/sleep.asm
new file mode 100644
index 0000000..256249c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90pwm3b/words/sleep.asm
@@ -0,0 +1,19 @@
+; ( mode -- )
+; MCU
+; put the controller into the specified sleep mode
+VE_SLEEP:
+ .dw $ff05
+ .db "sleep", 0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_SLEEP
+XT_SLEEP:
+ .dw PFA_SLEEP
+PFA_SLEEP:
+ andi tosl, 7 ; leave only legal mode bits
+ lsl tosl ; move to correct location (bits 3-1)
+ ori tosl, 1 ; set the SE bit
+ out_ SMCR, tosl ; set the sleep config
+ sleep ; nighty-night
+ out_ SMCR, zerol ; 0 protects against accidental sleeps
+ loadtos ; pop argument from stack
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/at90pwm81/at90pwm81.frt b/amforth-6.5/avr8/devices/at90pwm81/at90pwm81.frt
new file mode 100644
index 0000000..a25970a
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90pwm81/at90pwm81.frt
@@ -0,0 +1,370 @@
+\ Partname: AT90PWM81
+\ generated automatically
+
+\ PORTB
+&37 constant PORTB \ Port B Data Register
+&36 constant DDRB \ Port B Data Direction Register
+&35 constant PINB \ Port B Input Pins
+\ PORTD
+&43 constant PORTD \ Port D Data Register
+&42 constant DDRD \ Port D Data Direction Register
+&41 constant PIND \ Port D Input Pins
+\ DA_CONVERTER
+&89 constant DACH \ DAC Data Register High Byte
+ $FF constant DACH_DACH \ DAC Data Register High Byte Bits
+&88 constant DACL \ DAC Data Register Low Byte
+ $FF constant DACL_DACL \ DAC Data Register Low Byte Bits
+&118 constant DACON \ DAC Control Register
+ $80 constant DACON_DAATE \ DAC Auto Trigger Enable Bit
+ $70 constant DACON_DATS \ DAC Trigger Selection Bits
+ $04 constant DACON_DALA \ DAC Left Adjust
+ $01 constant DACON_DAEN \ DAC Enable Bit
+\ PORTE
+&46 constant PORTE \ Port E Data Register
+&45 constant DDRE \ Port E Data Direction Register
+&44 constant PINE \ Port E Input Pins
+\ SPI
+&55 constant SPCR \ SPI Control Register
+ $80 constant SPCR_SPIE \ SPI Interrupt Enable
+ $40 constant SPCR_SPE \ SPI Enable
+ $20 constant SPCR_DORD \ Data Order
+ $10 constant SPCR_MSTR \ Master/Slave Select
+ $08 constant SPCR_CPOL \ Clock polarity
+ $04 constant SPCR_CPHA \ Clock Phase
+ $03 constant SPCR_SPR \ SPI Clock Rate Selects
+&56 constant SPSR \ SPI Status Register
+ $80 constant SPSR_SPIF \ SPI Interrupt Flag
+ $40 constant SPSR_WCOL \ Write Collision Flag
+ $01 constant SPSR_SPI2X \ Double SPI Speed Bit
+&86 constant SPDR \ SPI Data Register
+\ WATCHDOG
+&130 constant WDTCSR \ Watchdog Timer Control Register
+ $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Flag
+ $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Enable
+ $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
+ $10 constant WDTCSR_WDCE \ Watchdog Change Enable
+ $08 constant WDTCSR_WDE \ Watch Dog Enable
+\ EXTERNAL_INTERRUPT
+&137 constant EICRA \ External Interrupt Control Register A
+ $30 constant EICRA_ISC2 \ External Interrupt Sense Control Bit
+ $0C constant EICRA_ISC1 \ External Interrupt Sense Control Bit
+ $03 constant EICRA_ISC0 \ External Interrupt Sense Control Bit
+&65 constant EIMSK \ External Interrupt Mask Register
+ $07 constant EIMSK_INT \ External Interrupt Request 2 Enable
+&64 constant EIFR \ External Interrupt Flag Register
+ $07 constant EIFR_INTF \ External Interrupt Flags
+\ AD_CONVERTER
+&40 constant ADMUX \ The ADC multiplexer Selection Register
+ $C0 constant ADMUX_REFS \ Reference Selection Bits
+ $20 constant ADMUX_ADLAR \ Left Adjust Result
+ $0F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
+&38 constant ADCSRA \ The ADC Control and Status register
+ $80 constant ADCSRA_ADEN \ ADC Enable
+ $40 constant ADCSRA_ADSC \ ADC Start Conversion
+ $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
+ $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
+ $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
+ $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
+&76 constant ADC \ ADC Data Register Bytes
+&39 constant ADCSRB \ ADC Control and Status Register B
+ $80 constant ADCSRB_ADHSM \ ADC High Speed Mode
+ $40 constant ADCSRB_ADNCDIS \ ADC Noise Canceller Disable
+ $10 constant ADCSRB_ADSSEN \ ADC Single Shot Enable on PSC's Synchronisation Signals
+ $0F constant ADCSRB_ADTS \ ADC Auto Trigger Sources
+&119 constant DIDR0 \ Digital Input Disable Register 0
+ $80 constant DIDR0_ADC7D \
+ $40 constant DIDR0_ADC6D \ ADC7 Digital input Disable
+ $20 constant DIDR0_ADC5D \ ADC5 Digital input Disable
+ $10 constant DIDR0_ADC4D \ ADC4 Digital input Disable
+ $08 constant DIDR0_ADC3D \ ADC3 Digital input Disable
+ $04 constant DIDR0_ADC2D \ ADC2 Digital input Disable
+ $02 constant DIDR0_ADC1D \ ADC1 Digital input Disable
+ $01 constant DIDR0_ADC0D \ ADC0 Digital input Disable
+&120 constant DIDR1 \ Digital Input Disable Register 0
+ $08 constant DIDR1_ACMP1MD \
+ $04 constant DIDR1_AMP0POSD \
+ $02 constant DIDR1_ADC10D \
+ $01 constant DIDR1_ADC9D \
+&121 constant AMP0CSR \
+ $80 constant AMP0CSR_AMP0EN \
+ $40 constant AMP0CSR_AMP0IS \
+ $30 constant AMP0CSR_AMP0G \
+ $08 constant AMP0CSR_AMP0GS \
+ $03 constant AMP0CSR_AMP0TS \
+\ ANALOG_COMPARATOR
+&127 constant AC3CON \ Analog Comparator3 Control Register
+ $80 constant AC3CON_AC3EN \ Analog Comparator3 Enable Bit
+ $40 constant AC3CON_AC3IE \ Analog Comparator 3 Interrupt Enable Bit
+ $30 constant AC3CON_AC3IS \ Analog Comparator 3 Interrupt Select Bit
+ $08 constant AC3CON_AC3OEA \ Analog Comparator 3 Alternate Output Enable
+ $07 constant AC3CON_AC3M \ Analog Comparator 3 Multiplexer Register
+&125 constant AC1CON \ Analog Comparator 1 Control Register
+ $80 constant AC1CON_AC1EN \ Analog Comparator 1 Enable Bit
+ $40 constant AC1CON_AC1IE \ Analog Comparator 1 Interrupt Enable Bit
+ $30 constant AC1CON_AC1IS \ Analog Comparator 1 Interrupt Select Bit
+ $07 constant AC1CON_AC1M \ Analog Comparator 1 Multiplexer Register
+&126 constant AC2CON \ Analog Comparator 2 Control Register
+ $80 constant AC2CON_AC2EN \ Analog Comparator 2 Enable Bit
+ $40 constant AC2CON_AC2IE \ Analog Comparator 2 Interrupt Enable Bit
+ $30 constant AC2CON_AC2IS \ Analog Comparator 2 Interrupt Select Bit
+ $07 constant AC2CON_AC2M \ Analog Comparator 2 Multiplexer Register
+&32 constant ACSR \ Analog Comparator Status Register
+ $80 constant ACSR_AC3IF \ Analog Comparator 3 Interrupt Flag Bit
+ $40 constant ACSR_AC2IF \ Analog Comparator 2 Interrupt Flag Bit
+ $20 constant ACSR_AC1IF \ Analog Comparator 1 Interrupt Flag Bit
+ $08 constant ACSR_AC3O \ Analog Comparator 3 Output Bit
+ $04 constant ACSR_AC2O \ Analog Comparator 2 Output Bit
+ $02 constant ACSR_AC1O \ Analog Comparator 1 Output Bit
+&124 constant AC3ECON \
+ $20 constant AC3ECON_AC3OI \ Analog Comparator Ouput Invert
+ $10 constant AC3ECON_AC3OE \ Analog Comparator Ouput Enable
+ $07 constant AC3ECON_AC3H \ Analog Comparator Hysteresis Select
+&123 constant AC2ECON \
+ $20 constant AC2ECON_AC2OI \ Analog Comparator Ouput Invert
+ $10 constant AC2ECON_AC2OE \ Analog Comparator Ouput Enable
+ $07 constant AC2ECON_AC2H \ Analog Comparator Hysteresis Select
+&122 constant AC1ECON \
+ $20 constant AC1ECON_AC1OI \ Analog Comparator Ouput Invert
+ $10 constant AC1ECON_AC1OE \ Analog Comparator Ouput Enable
+ $08 constant AC1ECON_AC1ICE \ Analog Comparator Interrupt Capture Enable
+ $07 constant AC1ECON_AC1H \ Analog Comparator Hysteresis Select
+\ CPU
+&95 constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ $08 constant SREG_V \ Two's Complement Overflow Flag
+ $04 constant SREG_N \ Negative Flag
+ $02 constant SREG_Z \ Zero Flag
+ $01 constant SREG_C \ Carry Flag
+&93 constant SP \ Stack Pointer
+&85 constant MCUCR \ MCU Control Register
+ $10 constant MCUCR_PUD \ Pull-up disable
+ $08 constant MCUCR_RSTDIS \ Reset Pin Disable
+ $04 constant MCUCR_CKRC81 \ Frequency Selection of the Calibrated RC Oscillator
+ $02 constant MCUCR_IVSEL \ Interrupt Vector Select
+ $01 constant MCUCR_IVCE \ Interrupt Vector Change Enable
+&84 constant MCUSR \ MCU Status Register
+ $08 constant MCUSR_WDRF \ Watchdog Reset Flag
+ $04 constant MCUSR_BORF \ Brown-out Reset Flag
+ $02 constant MCUSR_EXTRF \ External Reset Flag
+ $01 constant MCUSR_PORF \ Power-on reset flag
+&136 constant OSCCAL \ Oscillator Calibration Value
+&131 constant CLKPR \
+ $80 constant CLKPR_CLKPCE \
+ $0F constant CLKPR_CLKPS \
+&83 constant SMCR \ Sleep Mode Control Register
+ $0E constant SMCR_SM \ Sleep Mode Select bits
+ $01 constant SMCR_SE \ Sleep Enable
+&59 constant GPIOR2 \ General Purpose IO Register 2
+ $FF constant GPIOR2_GPIOR \ General Purpose IO Register 2 bis
+&58 constant GPIOR1 \ General Purpose IO Register 1
+ $FF constant GPIOR1_GPIOR \ General Purpose IO Register 1 bis
+&57 constant GPIOR0 \ General Purpose IO Register 0
+ $80 constant GPIOR0_GPIOR07 \ General Purpose IO Register 0 bit 7
+ $40 constant GPIOR0_GPIOR06 \ General Purpose IO Register 0 bit 6
+ $20 constant GPIOR0_GPIOR05 \ General Purpose IO Register 0 bit 5
+ $10 constant GPIOR0_GPIOR04 \ General Purpose IO Register 0 bit 4
+ $08 constant GPIOR0_GPIOR03 \ General Purpose IO Register 0 bit 3
+ $04 constant GPIOR0_GPIOR02 \ General Purpose IO Register 0 bit 2
+ $02 constant GPIOR0_GPIOR01 \ General Purpose IO Register 0 bit 1
+ $01 constant GPIOR0_GPIOR00 \ General Purpose IO Register 0 bit 0
+&135 constant PLLCSR \ PLL Control And Status Register
+ $3C constant PLLCSR_PLLF \
+ $02 constant PLLCSR_PLLE \ PLL Enable
+ $01 constant PLLCSR_PLOCK \ PLL Lock Detector
+&134 constant PRR \ Power Reduction Register
+ $80 constant PRR_PRPSC2 \ Power Reduction PSC2
+ $20 constant PRR_PRPSCR \ Power Reduction PSC0
+ $10 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
+ $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
+ $01 constant PRR_PRADC \ Power Reduction ADC
+&132 constant CLKCSR \
+ $80 constant CLKCSR_CLKCCE \ Clock Control Change Enable
+ $10 constant CLKCSR_CLKRDY \ Clock Ready Flag
+ $0F constant CLKCSR_CLKC \ Clock Control
+&133 constant CLKSELR \
+ $40 constant CLKSELR_COUT \ Clock OUT
+ $30 constant CLKSELR_CSUT \ Clock Start up Time
+ $0F constant CLKSELR_CKSEL \ Clock Source Select
+&129 constant BGCCR \ BandGap Current Calibration Register
+ $0F constant BGCCR_BGCC \
+&128 constant BGCRR \ BandGap Resistor Calibration Register
+ $0F constant BGCRR_BGCR \
+\ EEPROM
+&62 constant EEAR \ EEPROM Read/Write Access Bytes
+&61 constant EEDR \ EEPROM Data Register
+&60 constant EECR \ EEPROM Control Register
+ $80 constant EECR_NVMBSY \ None Volatile Busy Memory Busy
+ $40 constant EECR_EEPAGE \ EEPROM Page Access
+ $30 constant EECR_EEPM \ EEPROM Programming Mode
+ $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
+ $04 constant EECR_EEMWE \ EEPROM Master Write Enable
+ $02 constant EECR_EEWE \ EEPROM Write Enable
+ $01 constant EECR_EERE \ EEPROM Read Enable
+\ PSC0
+&104 constant PICR0 \ PSC 0 Input Capture Register
+&99 constant PFRC0B \ PSC 0 Input B Control
+ $80 constant PFRC0B_PCAE0B \ PSC 0 Capture Enable Input Part B
+ $40 constant PFRC0B_PISEL0B \ PSC 0 Input Select for Part B
+ $20 constant PFRC0B_PELEV0B \ PSC 0 Edge Level Selector on Input Part B
+ $10 constant PFRC0B_PFLTE0B \ PSC 0 Filter Enable on Input Part B
+ $0F constant PFRC0B_PRFM0B \ PSC 0 Retrigger and Fault Mode for Part B
+&98 constant PFRC0A \ PSC 0 Input A Control
+ $80 constant PFRC0A_PCAE0A \ PSC 0 Capture Enable Input Part A
+ $40 constant PFRC0A_PISEL0A \ PSC 0 Input Select for Part A
+ $20 constant PFRC0A_PELEV0A \ PSC 0 Edge Level Selector on Input Part A
+ $10 constant PFRC0A_PFLTE0A \ PSC 0 Filter Enable on Input Part A
+ $0F constant PFRC0A_PRFM0A \ PSC 0 Retrigger and Fault Mode for Part A
+&50 constant PCTL0 \ PSC 0 Control Register
+ $C0 constant PCTL0_PPRE0 \ PSC 0 Prescaler Selects
+ $24 constant PCTL0_PBFM0 \ PSC 0 Balance Flank Width Modulation
+ $10 constant PCTL0_PAOC0B \ PSC 0 Asynchronous Output Control B
+ $08 constant PCTL0_PAOC0A \ PSC 0 Asynchronous Output Control A
+ $02 constant PCTL0_PCCYC0 \ PSC0 Complete Cycle
+ $01 constant PCTL0_PRUN0 \ PSC 0 Run
+&49 constant PCNF0 \ PSC 0 Configuration Register
+ $80 constant PCNF0_PFIFTY0 \ PSC 0 Fifty
+ $40 constant PCNF0_PALOCK0 \ PSC 0 Autolock
+ $20 constant PCNF0_PLOCK0 \ PSC 0 Lock
+ $18 constant PCNF0_PMODE0 \ PSC 0 Mode
+ $04 constant PCNF0_POP0 \ PSC 0 Output Polarity
+ $02 constant PCNF0_PCLKSEL0 \ PSC 0 Input Clock Select
+&68 constant OCR0RB \ Output Compare RB Register
+&66 constant OCR0SB \ Output Compare SB Register
+&74 constant OCR0RA \ Output Compare RA Register
+&96 constant OCR0SA \ Output Compare SA Register
+&106 constant PSOC0 \ PSC0 Synchro and Output Configuration
+ $80 constant PSOC0_PISEL0A1 \ PSC Input Select
+ $40 constant PSOC0_PISEL0B1 \ PSC Input Select
+ $30 constant PSOC0_PSYNC0 \ Synchronisation out for ADC selection
+ $04 constant PSOC0_POEN0B \ PSCOUT01 Output Enable
+ $01 constant PSOC0_POEN0A \ PSCOUT00 Output Enable
+&47 constant PIM0 \ PSC0 Interrupt Mask Register
+ $10 constant PIM0_PEVE0B \ External Event B Interrupt Enable
+ $08 constant PIM0_PEVE0A \ External Event A Interrupt Enable
+ $02 constant PIM0_PEOEPE0 \ End of Enhanced Cycle Enable
+ $01 constant PIM0_PEOPE0 \ End of Cycle Interrupt Enable
+&48 constant PIFR0 \ PSC0 Interrupt Flag Register
+ $80 constant PIFR0_POAC0B \ PSC 0 Output A Activity
+ $40 constant PIFR0_POAC0A \ PSC 0 Output A Activity
+ $10 constant PIFR0_PEV0B \ External Event B Interrupt
+ $08 constant PIFR0_PEV0A \ External Event A Interrupt
+ $06 constant PIFR0_PRN0 \ Ramp Number
+ $01 constant PIFR0_PEOP0 \ End of PSC0 Interrupt
+\ PSC2
+&109 constant PICR2H \ PSC 2 Input Capture Register High
+ $80 constant PICR2H_PCST2 \ PSC 2 Capture Software Trigger Bit
+ $0C constant PICR2H_PICR21 \
+ $03 constant PICR2H_PICR2 \
+&108 constant PICR2L \ PSC 2 Input Capture Register Low
+&103 constant PFRC2B \ PSC 2 Input B Control
+ $80 constant PFRC2B_PCAE2B \ PSC 2 Capture Enable Input Part B
+ $40 constant PFRC2B_PISEL2B \ PSC 2 Input Select for Part B
+ $20 constant PFRC2B_PELEV2B \ PSC 2 Edge Level Selector on Input Part B
+ $10 constant PFRC2B_PFLTE2B \ PSC 2 Filter Enable on Input Part B
+ $0F constant PFRC2B_PRFM2B \ PSC 2 Retrigger and Fault Mode for Part B
+&102 constant PFRC2A \ PSC 2 Input B Control
+ $80 constant PFRC2A_PCAE2A \ PSC 2 Capture Enable Input Part A
+ $40 constant PFRC2A_PISEL2A \ PSC 2 Input Select for Part A
+ $20 constant PFRC2A_PELEV2A \ PSC 2 Edge Level Selector on Input Part A
+ $10 constant PFRC2A_PFLTE2A \ PSC 2 Filter Enable on Input Part A
+ $0F constant PFRC2A_PRFM2A \ PSC 2 Retrigger and Fault Mode for Part A
+&54 constant PCTL2 \ PSC 2 Control Register
+ $C0 constant PCTL2_PPRE2 \ PSC 2 Prescaler Selects
+ $20 constant PCTL2_PBFM2 \ Balance Flank Width Modulation
+ $10 constant PCTL2_PAOC2B \ PSC 2 Asynchronous Output Control B
+ $08 constant PCTL2_PAOC2A \ PSC 2 Asynchronous Output Control A
+ $04 constant PCTL2_PARUN2 \ PSC2 Auto Run
+ $02 constant PCTL2_PCCYC2 \ PSC2 Complete Cycle
+ $01 constant PCTL2_PRUN2 \ PSC 2 Run
+&53 constant PCNF2 \ PSC 2 Configuration Register
+ $80 constant PCNF2_PFIFTY2 \ PSC 2 Fifty
+ $40 constant PCNF2_PALOCK2 \ PSC 2 Autolock
+ $20 constant PCNF2_PLOCK2 \ PSC 2 Lock
+ $18 constant PCNF2_PMODE2 \ PSC 2 Mode
+ $04 constant PCNF2_POP2 \ PSC 2 Output Polarity
+ $02 constant PCNF2_PCLKSEL2 \ PSC 2 Input Clock Select
+ $01 constant PCNF2_POME2 \ PSC 2 Output Matrix Enable
+&112 constant PCNFE2 \ PSC 2 Enhanced Configuration Register
+ $E0 constant PCNFE2_PASDLK2 \
+ $10 constant PCNFE2_PBFM21 \
+ $08 constant PCNFE2_PELEV2A1 \
+ $04 constant PCNFE2_PELEV2B1 \
+ $02 constant PCNFE2_PISEL2A1 \
+ $01 constant PCNFE2_PISEL2B1 \
+&72 constant OCR2RB \ Output Compare RB Register
+&70 constant OCR2SB \ Output Compare SB Register
+&78 constant OCR2RA \ Output Compare RA Register
+&100 constant OCR2SA \ Output Compare SA Register
+&111 constant POM2 \ PSC 2 Output Matrix
+ $F0 constant POM2_POMV2B \ Output Matrix Output B Ramps
+ $0F constant POM2_POMV2A \ Output Matrix Output A Ramps
+&110 constant PSOC2 \ PSC2 Synchro and Output Configuration
+ $C0 constant PSOC2_POS2 \ PSC 2 Output 23 Select
+ $30 constant PSOC2_PSYNC2 \ Synchronization Out for ADC Selection
+ $08 constant PSOC2_POEN2D \ PSCOUT23 Output Enable
+ $04 constant PSOC2_POEN2B \ PSCOUT21 Output Enable
+ $02 constant PSOC2_POEN2C \ PSCOUT22 Output Enable
+ $01 constant PSOC2_POEN2A \ PSCOUT20 Output Enable
+&51 constant PIM2 \ PSC2 Interrupt Mask Register
+ $20 constant PIM2_PSEIE2 \ PSC 2 Synchro Error Interrupt Enable
+ $10 constant PIM2_PEVE2B \ External Event B Interrupt Enable
+ $08 constant PIM2_PEVE2A \ External Event A Interrupt Enable
+ $02 constant PIM2_PEOEPE2 \ End of Enhanced Cycle Interrupt Enable
+ $01 constant PIM2_PEOPE2 \ End of Cycle Interrupt Enable
+&52 constant PIFR2 \ PSC2 Interrupt Flag Register
+ $80 constant PIFR2_POAC2B \ PSC 2 Output A Activity
+ $40 constant PIFR2_POAC2A \ PSC 2 Output A Activity
+ $20 constant PIFR2_PSEI2 \ PSC 2 Synchro Error Interrupt
+ $10 constant PIFR2_PEV2B \ External Event B Interrupt
+ $08 constant PIFR2_PEV2A \ External Event A Interrupt
+ $06 constant PIFR2_PRN2 \ Ramp Number
+ $01 constant PIFR2_PEOP2 \ End of PSC2 Interrupt
+&113 constant PASDLY2 \ Analog Synchronization Delay Register
+\ TIMER_COUNTER_1
+&33 constant TIMSK1 \ Timer/Counter Interrupt Mask Register
+ $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
+ $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
+&34 constant TIFR1 \ Timer/Counter Interrupt Flag register
+ $20 constant TIFR1_ICF1 \ Input Capture Flag 1
+ $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
+&138 constant TCCR1B \ Timer/Counter1 Control Register B
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ $10 constant TCCR1B_WGM13 \ Waveform Generation Mode
+ $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
+&90 constant TCNT1 \ Timer/Counter1 Bytes
+&140 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
+\ BOOT_LOAD
+&87 constant SPMCSR \ Store Program Memory Control Register
+ $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
+ $20 constant SPMCSR_SIGRD \ Signature Row Read
+ $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
+ $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
+ $04 constant SPMCSR_PGWRT \ Page Write
+ $02 constant SPMCSR_PGERS \ Page Erase
+ $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
+
+\ Interrupts
+&1 constant PSC2_CAPTAddr \ PSC2 Capture Event
+&2 constant PSC2_ECAddr \ PSC2 End Cycle
+&3 constant PSC2_EECAddr \ PSC2 End Of Enhanced Cycle
+&4 constant PSC0_CAPTAddr \ PSC0 Capture Event
+&5 constant PSC0_ECAddr \ PSC0 End Cycle
+&6 constant PSC0_EECAddr \ PSC0 End Of Enhanced Cycle
+&7 constant ANALOG_COMP_1Addr \ Analog Comparator 1
+&8 constant ANALOG_COMP_2Addr \ Analog Comparator 2
+&9 constant ANALOG_COMP_3Addr \ Analog Comparator 3
+&10 constant INT0Addr \ External Interrupt Request 0
+&11 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+&12 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+&13 constant ADCAddr \ ADC Conversion Complete
+&14 constant INT1Addr \ External Interrupt Request 1
+&15 constant SPI__STCAddr \ SPI Serial Transfer Complet
+&16 constant INT2Addr \ External Interrupt Request 2
+&17 constant WDTAddr \ Watchdog Timeout Interrupt
+&18 constant EE_READYAddr \ EEPROM Ready
+&19 constant SPM_READYAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/at90pwm81/device.asm b/amforth-6.5/avr8/devices/at90pwm81/device.asm
new file mode 100644
index 0000000..b836c8e
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90pwm81/device.asm
@@ -0,0 +1,96 @@
+; Partname: AT90PWM81
+; generated automatically, do not edit
+
+.nolist
+ .include "pwm81def.inc"
+.list
+
+.equ ramstart = 256
+.equ CELLSIZE = 2
+.macro readflashcell
+ lsl zl
+ rol zh
+ lpm @0, Z+
+ lpm @1, Z+
+.endmacro
+.macro writeflashcell
+ lsl zl
+ rol zh
+.endmacro
+.set WANT_PORTB = 0
+.set WANT_PORTD = 0
+.set WANT_DA_CONVERTER = 0
+.set WANT_PORTE = 0
+.set WANT_SPI = 0
+.set WANT_WATCHDOG = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_AD_CONVERTER = 0
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_CPU = 0
+.set WANT_EEPROM = 0
+.set WANT_PSC0 = 0
+.set WANT_PSC2 = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_BOOT_LOAD = 0
+.equ intvecsize = 1 ; please verify; flash size: 8192 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.org 1
+ rcall isr ; PSC2 Capture Event
+.org 2
+ rcall isr ; PSC2 End Cycle
+.org 3
+ rcall isr ; PSC2 End Of Enhanced Cycle
+.org 4
+ rcall isr ; PSC0 Capture Event
+.org 5
+ rcall isr ; PSC0 End Cycle
+.org 6
+ rcall isr ; PSC0 End Of Enhanced Cycle
+.org 7
+ rcall isr ; Analog Comparator 1
+.org 8
+ rcall isr ; Analog Comparator 2
+.org 9
+ rcall isr ; Analog Comparator 3
+.org 10
+ rcall isr ; External Interrupt Request 0
+.org 11
+ rcall isr ; Timer/Counter1 Capture Event
+.org 12
+ rcall isr ; Timer/Counter1 Overflow
+.org 13
+ rcall isr ; ADC Conversion Complete
+.org 14
+ rcall isr ; External Interrupt Request 1
+.org 15
+ rcall isr ; SPI Serial Transfer Complet
+.org 16
+ rcall isr ; External Interrupt Request 2
+.org 17
+ rcall isr ; Watchdog Timeout Interrupt
+.org 18
+ rcall isr ; EEPROM Ready
+.org 19
+ rcall isr ; Store Program Memory Read
+.equ INTVECTORS = 20
+.nooverlap
+
+; compatability layer (maybe empty)
+.equ EEPE = EEWE
+.equ EEMPE = EEMWE
+
+; controller data area, environment query mcu-info
+mcu_info:
+mcu_ramsize:
+ .dw 256
+mcu_eepromsize:
+ .dw 512
+mcu_maxdp:
+ .dw 6144
+mcu_numints:
+ .dw 20
+mcu_name:
+ .dw 9
+ .db "AT90PWM81",0
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/at90pwm81/device.inc b/amforth-6.5/avr8/devices/at90pwm81/device.inc
new file mode 100644
index 0000000..64c1370
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90pwm81/device.inc
@@ -0,0 +1,1080 @@
+; Partname: AT90PWM81
+; generated automatically, no not edit
+
+.if WANT_PORTB == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw 37
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw 36
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw 35
+
+.endif
+.if WANT_PORTD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw 43
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw 42
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw 41
+
+.endif
+.if WANT_DA_CONVERTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; DAC Data Register High Byte
+VE_DACH:
+ .dw $ff04
+ .db "DACH"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DACH
+XT_DACH:
+ .dw PFA_DOVARIABLE
+PFA_DACH:
+ .dw 89
+; ( -- addr ) System Constant
+; R( -- )
+; DAC Data Register Low Byte
+VE_DACL:
+ .dw $ff04
+ .db "DACL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DACL
+XT_DACL:
+ .dw PFA_DOVARIABLE
+PFA_DACL:
+ .dw 88
+; ( -- addr ) System Constant
+; R( -- )
+; DAC Control Register
+VE_DACON:
+ .dw $ff05
+ .db "DACON",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DACON
+XT_DACON:
+ .dw PFA_DOVARIABLE
+PFA_DACON:
+ .dw 118
+
+.endif
+.if WANT_PORTE == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port E Data Register
+VE_PORTE:
+ .dw $ff05
+ .db "PORTE",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTE
+XT_PORTE:
+ .dw PFA_DOVARIABLE
+PFA_PORTE:
+ .dw 46
+; ( -- addr ) System Constant
+; R( -- )
+; Port E Data Direction Register
+VE_DDRE:
+ .dw $ff04
+ .db "DDRE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRE
+XT_DDRE:
+ .dw PFA_DOVARIABLE
+PFA_DDRE:
+ .dw 45
+; ( -- addr ) System Constant
+; R( -- )
+; Port E Input Pins
+VE_PINE:
+ .dw $ff04
+ .db "PINE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINE
+XT_PINE:
+ .dw PFA_DOVARIABLE
+PFA_PINE:
+ .dw 44
+
+.endif
+.if WANT_SPI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR:
+ .dw $ff04
+ .db "SPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR
+XT_SPCR:
+ .dw PFA_DOVARIABLE
+PFA_SPCR:
+ .dw 55
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR:
+ .dw $ff04
+ .db "SPSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR
+XT_SPSR:
+ .dw PFA_DOVARIABLE
+PFA_SPSR:
+ .dw 56
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR:
+ .dw $ff04
+ .db "SPDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR
+XT_SPDR:
+ .dw PFA_DOVARIABLE
+PFA_SPDR:
+ .dw 86
+
+.endif
+.if WANT_WATCHDOG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCSR:
+ .dw $ff06
+ .db "WDTCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCSR
+XT_WDTCSR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCSR:
+ .dw 130
+
+.endif
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register A
+VE_EICRA:
+ .dw $ff05
+ .db "EICRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRA
+XT_EICRA:
+ .dw PFA_DOVARIABLE
+PFA_EICRA:
+ .dw 137
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Mask Register
+VE_EIMSK:
+ .dw $ff05
+ .db "EIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIMSK
+XT_EIMSK:
+ .dw PFA_DOVARIABLE
+PFA_EIMSK:
+ .dw 65
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Flag Register
+VE_EIFR:
+ .dw $ff04
+ .db "EIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIFR
+XT_EIFR:
+ .dw PFA_DOVARIABLE
+PFA_EIFR:
+ .dw 64
+
+.endif
+.if WANT_AD_CONVERTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC multiplexer Selection Register
+VE_ADMUX:
+ .dw $ff05
+ .db "ADMUX",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADMUX
+XT_ADMUX:
+ .dw PFA_DOVARIABLE
+PFA_ADMUX:
+ .dw 40
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register
+VE_ADCSRA:
+ .dw $ff06
+ .db "ADCSRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRA
+XT_ADCSRA:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRA:
+ .dw 38
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register Bytes
+VE_ADC:
+ .dw $ff03
+ .db "ADC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADC
+XT_ADC:
+ .dw PFA_DOVARIABLE
+PFA_ADC:
+ .dw 76
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Control and Status Register B
+VE_ADCSRB:
+ .dw $ff06
+ .db "ADCSRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRB
+XT_ADCSRB:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRB:
+ .dw 39
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 0
+VE_DIDR0:
+ .dw $ff05
+ .db "DIDR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR0
+XT_DIDR0:
+ .dw PFA_DOVARIABLE
+PFA_DIDR0:
+ .dw 119
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 0
+VE_DIDR1:
+ .dw $ff05
+ .db "DIDR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR1
+XT_DIDR1:
+ .dw PFA_DOVARIABLE
+PFA_DIDR1:
+ .dw 120
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_AMP0CSR:
+ .dw $ff07
+ .db "AMP0CSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_AMP0CSR
+XT_AMP0CSR:
+ .dw PFA_DOVARIABLE
+PFA_AMP0CSR:
+ .dw 121
+
+.endif
+.if WANT_ANALOG_COMPARATOR == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator3 Control Register
+VE_AC3CON:
+ .dw $ff06
+ .db "AC3CON"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_AC3CON
+XT_AC3CON:
+ .dw PFA_DOVARIABLE
+PFA_AC3CON:
+ .dw 127
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator 1 Control Register
+VE_AC1CON:
+ .dw $ff06
+ .db "AC1CON"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_AC1CON
+XT_AC1CON:
+ .dw PFA_DOVARIABLE
+PFA_AC1CON:
+ .dw 125
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator 2 Control Register
+VE_AC2CON:
+ .dw $ff06
+ .db "AC2CON"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_AC2CON
+XT_AC2CON:
+ .dw PFA_DOVARIABLE
+PFA_AC2CON:
+ .dw 126
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw 32
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_AC3ECON:
+ .dw $ff07
+ .db "AC3ECON",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_AC3ECON
+XT_AC3ECON:
+ .dw PFA_DOVARIABLE
+PFA_AC3ECON:
+ .dw 124
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_AC2ECON:
+ .dw $ff07
+ .db "AC2ECON",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_AC2ECON
+XT_AC2ECON:
+ .dw PFA_DOVARIABLE
+PFA_AC2ECON:
+ .dw 123
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_AC1ECON:
+ .dw $ff07
+ .db "AC1ECON",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_AC1ECON
+XT_AC1ECON:
+ .dw PFA_DOVARIABLE
+PFA_AC1ECON:
+ .dw 122
+
+.endif
+.if WANT_CPU == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw 95
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer
+VE_SP:
+ .dw $ff02
+ .db "SP"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SP
+XT_SP:
+ .dw PFA_DOVARIABLE
+PFA_SP:
+ .dw 93
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw 85
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Status Register
+VE_MCUSR:
+ .dw $ff05
+ .db "MCUSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUSR
+XT_MCUSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUSR:
+ .dw 84
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Calibration Value
+VE_OSCCAL:
+ .dw $ff06
+ .db "OSCCAL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSCCAL
+XT_OSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_OSCCAL:
+ .dw 136
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_CLKPR:
+ .dw $ff05
+ .db "CLKPR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKPR
+XT_CLKPR:
+ .dw PFA_DOVARIABLE
+PFA_CLKPR:
+ .dw 131
+; ( -- addr ) System Constant
+; R( -- )
+; Sleep Mode Control Register
+VE_SMCR:
+ .dw $ff04
+ .db "SMCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SMCR
+XT_SMCR:
+ .dw PFA_DOVARIABLE
+PFA_SMCR:
+ .dw 83
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 2
+VE_GPIOR2:
+ .dw $ff06
+ .db "GPIOR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR2
+XT_GPIOR2:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR2:
+ .dw 59
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 1
+VE_GPIOR1:
+ .dw $ff06
+ .db "GPIOR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR1
+XT_GPIOR1:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR1:
+ .dw 58
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 0
+VE_GPIOR0:
+ .dw $ff06
+ .db "GPIOR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR0
+XT_GPIOR0:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR0:
+ .dw 57
+; ( -- addr ) System Constant
+; R( -- )
+; PLL Control And Status Register
+VE_PLLCSR:
+ .dw $ff06
+ .db "PLLCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PLLCSR
+XT_PLLCSR:
+ .dw PFA_DOVARIABLE
+PFA_PLLCSR:
+ .dw 135
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register
+VE_PRR:
+ .dw $ff03
+ .db "PRR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR
+XT_PRR:
+ .dw PFA_DOVARIABLE
+PFA_PRR:
+ .dw 134
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_CLKCSR:
+ .dw $ff06
+ .db "CLKCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKCSR
+XT_CLKCSR:
+ .dw PFA_DOVARIABLE
+PFA_CLKCSR:
+ .dw 132
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_CLKSELR:
+ .dw $ff07
+ .db "CLKSELR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKSELR
+XT_CLKSELR:
+ .dw PFA_DOVARIABLE
+PFA_CLKSELR:
+ .dw 133
+; ( -- addr ) System Constant
+; R( -- )
+; BandGap Current Calibration Register
+VE_BGCCR:
+ .dw $ff05
+ .db "BGCCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_BGCCR
+XT_BGCCR:
+ .dw PFA_DOVARIABLE
+PFA_BGCCR:
+ .dw 129
+; ( -- addr ) System Constant
+; R( -- )
+; BandGap Resistor Calibration Register
+VE_BGCRR:
+ .dw $ff05
+ .db "BGCRR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_BGCRR
+XT_BGCRR:
+ .dw PFA_DOVARIABLE
+PFA_BGCRR:
+ .dw 128
+
+.endif
+.if WANT_EEPROM == 1
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Read/Write Access Bytes
+VE_EEAR:
+ .dw $ff04
+ .db "EEAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEAR
+XT_EEAR:
+ .dw PFA_DOVARIABLE
+PFA_EEAR:
+ .dw 62
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw 61
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw 60
+
+.endif
+.if WANT_PSC0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 0 Input Capture Register
+VE_PICR0:
+ .dw $ff05
+ .db "PICR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PICR0
+XT_PICR0:
+ .dw PFA_DOVARIABLE
+PFA_PICR0:
+ .dw 104
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 0 Input B Control
+VE_PFRC0B:
+ .dw $ff06
+ .db "PFRC0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PFRC0B
+XT_PFRC0B:
+ .dw PFA_DOVARIABLE
+PFA_PFRC0B:
+ .dw 99
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 0 Input A Control
+VE_PFRC0A:
+ .dw $ff06
+ .db "PFRC0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PFRC0A
+XT_PFRC0A:
+ .dw PFA_DOVARIABLE
+PFA_PFRC0A:
+ .dw 98
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 0 Control Register
+VE_PCTL0:
+ .dw $ff05
+ .db "PCTL0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCTL0
+XT_PCTL0:
+ .dw PFA_DOVARIABLE
+PFA_PCTL0:
+ .dw 50
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 0 Configuration Register
+VE_PCNF0:
+ .dw $ff05
+ .db "PCNF0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCNF0
+XT_PCNF0:
+ .dw PFA_DOVARIABLE
+PFA_PCNF0:
+ .dw 49
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare RB Register
+VE_OCR0RB:
+ .dw $ff06
+ .db "OCR0RB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0RB
+XT_OCR0RB:
+ .dw PFA_DOVARIABLE
+PFA_OCR0RB:
+ .dw 68
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare SB Register
+VE_OCR0SB:
+ .dw $ff06
+ .db "OCR0SB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0SB
+XT_OCR0SB:
+ .dw PFA_DOVARIABLE
+PFA_OCR0SB:
+ .dw 66
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare RA Register
+VE_OCR0RA:
+ .dw $ff06
+ .db "OCR0RA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0RA
+XT_OCR0RA:
+ .dw PFA_DOVARIABLE
+PFA_OCR0RA:
+ .dw 74
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare SA Register
+VE_OCR0SA:
+ .dw $ff06
+ .db "OCR0SA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0SA
+XT_OCR0SA:
+ .dw PFA_DOVARIABLE
+PFA_OCR0SA:
+ .dw 96
+; ( -- addr ) System Constant
+; R( -- )
+; PSC0 Synchro and Output Configuration
+VE_PSOC0:
+ .dw $ff05
+ .db "PSOC0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PSOC0
+XT_PSOC0:
+ .dw PFA_DOVARIABLE
+PFA_PSOC0:
+ .dw 106
+; ( -- addr ) System Constant
+; R( -- )
+; PSC0 Interrupt Mask Register
+VE_PIM0:
+ .dw $ff04
+ .db "PIM0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIM0
+XT_PIM0:
+ .dw PFA_DOVARIABLE
+PFA_PIM0:
+ .dw 47
+; ( -- addr ) System Constant
+; R( -- )
+; PSC0 Interrupt Flag Register
+VE_PIFR0:
+ .dw $ff05
+ .db "PIFR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIFR0
+XT_PIFR0:
+ .dw PFA_DOVARIABLE
+PFA_PIFR0:
+ .dw 48
+
+.endif
+.if WANT_PSC2 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 2 Input Capture Register High
+VE_PICR2H:
+ .dw $ff06
+ .db "PICR2H"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PICR2H
+XT_PICR2H:
+ .dw PFA_DOVARIABLE
+PFA_PICR2H:
+ .dw 109
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 2 Input Capture Register Low
+VE_PICR2L:
+ .dw $ff06
+ .db "PICR2L"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PICR2L
+XT_PICR2L:
+ .dw PFA_DOVARIABLE
+PFA_PICR2L:
+ .dw 108
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 2 Input B Control
+VE_PFRC2B:
+ .dw $ff06
+ .db "PFRC2B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PFRC2B
+XT_PFRC2B:
+ .dw PFA_DOVARIABLE
+PFA_PFRC2B:
+ .dw 103
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 2 Input B Control
+VE_PFRC2A:
+ .dw $ff06
+ .db "PFRC2A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PFRC2A
+XT_PFRC2A:
+ .dw PFA_DOVARIABLE
+PFA_PFRC2A:
+ .dw 102
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 2 Control Register
+VE_PCTL2:
+ .dw $ff05
+ .db "PCTL2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCTL2
+XT_PCTL2:
+ .dw PFA_DOVARIABLE
+PFA_PCTL2:
+ .dw 54
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 2 Configuration Register
+VE_PCNF2:
+ .dw $ff05
+ .db "PCNF2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCNF2
+XT_PCNF2:
+ .dw PFA_DOVARIABLE
+PFA_PCNF2:
+ .dw 53
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 2 Enhanced Configuration Register
+VE_PCNFE2:
+ .dw $ff06
+ .db "PCNFE2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCNFE2
+XT_PCNFE2:
+ .dw PFA_DOVARIABLE
+PFA_PCNFE2:
+ .dw 112
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare RB Register
+VE_OCR2RB:
+ .dw $ff06
+ .db "OCR2RB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2RB
+XT_OCR2RB:
+ .dw PFA_DOVARIABLE
+PFA_OCR2RB:
+ .dw 72
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare SB Register
+VE_OCR2SB:
+ .dw $ff06
+ .db "OCR2SB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2SB
+XT_OCR2SB:
+ .dw PFA_DOVARIABLE
+PFA_OCR2SB:
+ .dw 70
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare RA Register
+VE_OCR2RA:
+ .dw $ff06
+ .db "OCR2RA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2RA
+XT_OCR2RA:
+ .dw PFA_DOVARIABLE
+PFA_OCR2RA:
+ .dw 78
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare SA Register
+VE_OCR2SA:
+ .dw $ff06
+ .db "OCR2SA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2SA
+XT_OCR2SA:
+ .dw PFA_DOVARIABLE
+PFA_OCR2SA:
+ .dw 100
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 2 Output Matrix
+VE_POM2:
+ .dw $ff04
+ .db "POM2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_POM2
+XT_POM2:
+ .dw PFA_DOVARIABLE
+PFA_POM2:
+ .dw 111
+; ( -- addr ) System Constant
+; R( -- )
+; PSC2 Synchro and Output Configuration
+VE_PSOC2:
+ .dw $ff05
+ .db "PSOC2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PSOC2
+XT_PSOC2:
+ .dw PFA_DOVARIABLE
+PFA_PSOC2:
+ .dw 110
+; ( -- addr ) System Constant
+; R( -- )
+; PSC2 Interrupt Mask Register
+VE_PIM2:
+ .dw $ff04
+ .db "PIM2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIM2
+XT_PIM2:
+ .dw PFA_DOVARIABLE
+PFA_PIM2:
+ .dw 51
+; ( -- addr ) System Constant
+; R( -- )
+; PSC2 Interrupt Flag Register
+VE_PIFR2:
+ .dw $ff05
+ .db "PIFR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIFR2
+XT_PIFR2:
+ .dw PFA_DOVARIABLE
+PFA_PIFR2:
+ .dw 52
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Synchronization Delay Register
+VE_PASDLY2:
+ .dw $ff07
+ .db "PASDLY2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PASDLY2
+XT_PASDLY2:
+ .dw PFA_DOVARIABLE
+PFA_PASDLY2:
+ .dw 113
+
+.endif
+.if WANT_TIMER_COUNTER_1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Mask Register
+VE_TIMSK1:
+ .dw $ff06
+ .db "TIMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK1
+XT_TIMSK1:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK1:
+ .dw 33
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Flag register
+VE_TIFR1:
+ .dw $ff05
+ .db "TIFR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR1
+XT_TIFR1:
+ .dw PFA_DOVARIABLE
+PFA_TIFR1:
+ .dw 34
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw 138
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Bytes
+VE_TCNT1:
+ .dw $ff05
+ .db "TCNT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1
+XT_TCNT1:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1:
+ .dw 90
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Bytes
+VE_ICR1:
+ .dw $ff04
+ .db "ICR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1
+XT_ICR1:
+ .dw PFA_DOVARIABLE
+PFA_ICR1:
+ .dw 140
+
+.endif
+.if WANT_BOOT_LOAD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control Register
+VE_SPMCSR:
+ .dw $ff06
+ .db "SPMCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCSR
+XT_SPMCSR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCSR:
+ .dw 87
+
+.endif
diff --git a/amforth-6.5/avr8/devices/at90pwm81/device.py b/amforth-6.5/avr8/devices/at90pwm81/device.py
new file mode 100644
index 0000000..853ac3a
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90pwm81/device.py
@@ -0,0 +1,389 @@
+# Generated Automatically
+
+# Partname AT90PWM81
+
+MCUREGS = {
+# Interrupt Vectors
+ 'PSC2_CAPTAddr' : '#2', # PSC2 Capture Event
+ 'PSC2_ECAddr' : '#4', # PSC2 End Cycle
+ 'PSC2_EECAddr' : '#6', # PSC2 End Of Enhanced Cycle
+ 'PSC0_CAPTAddr' : '#8', # PSC0 Capture Event
+ 'PSC0_ECAddr' : '#10', # PSC0 End Cycle
+ 'PSC0_EECAddr' : '#12', # PSC0 End Of Enhanced Cycle
+ 'ANALOG_COMP_1Addr' : '#14', # Analog Comparator 1
+ 'ANALOG_COMP_2Addr' : '#16', # Analog Comparator 2
+ 'ANALOG_COMP_3Addr' : '#18', # Analog Comparator 3
+ 'INT0Addr' : '#20', # External Interrupt Request 0
+ 'TIMER1_CAPTAddr' : '#22', # Timer/Counter1 Capture Event
+ 'TIMER1_OVFAddr' : '#24', # Timer/Counter1 Overflow
+ 'ADCAddr' : '#26', # ADC Conversion Complete
+ 'INT1Addr' : '#28', # External Interrupt Request 1
+ 'SPI_STCAddr' : '#30', # SPI Serial Transfer Complet
+ 'INT2Addr' : '#32', # External Interrupt Request 2
+ 'WDTAddr' : '#34', # Watchdog Timeout Interrupt
+ 'EE_READYAddr' : '#36', # EEPROM Ready
+ 'SPM_READYAddr' : '#38', # Store Program Memory Read
+
+# Module PORTB
+ 'PORTB' : '$25', # Port B Data Register
+ 'DDRB' : '$24', # Port B Data Direction Register
+ 'PINB' : '$23', # Port B Input Pins
+
+# Module PORTD
+ 'PORTD' : '$2b', # Port D Data Register
+ 'DDRD' : '$2a', # Port D Data Direction Register
+ 'PIND' : '$29', # Port D Input Pins
+
+# Module DA_CONVERTER
+ 'DACH' : '$59', # DAC Data Register High Byte
+ 'DACH_DACH': '$ff', # DAC Data Register High Byte Bi
+ 'DACL' : '$58', # DAC Data Register Low Byte
+ 'DACL_DACL': '$ff', # DAC Data Register Low Byte Bit
+ 'DACON' : '$76', # DAC Control Register
+ 'DACON_DAATE': '$80', # DAC Auto Trigger Enable Bit
+ 'DACON_DATS': '$70', # DAC Trigger Selection Bits
+ 'DACON_DALA': '$4', # DAC Left Adjust
+ 'DACON_DAEN': '$1', # DAC Enable Bit
+
+# Module PORTE
+ 'PORTE' : '$2e', # Port E Data Register
+ 'DDRE' : '$2d', # Port E Data Direction Register
+ 'PINE' : '$2c', # Port E Input Pins
+
+# Module SPI
+ 'SPCR' : '$37', # SPI Control Register
+ 'SPCR_SPIE': '$80', # SPI Interrupt Enable
+ 'SPCR_SPE': '$40', # SPI Enable
+ 'SPCR_DORD': '$20', # Data Order
+ 'SPCR_MSTR': '$10', # Master/Slave Select
+ 'SPCR_CPOL': '$8', # Clock polarity
+ 'SPCR_CPHA': '$4', # Clock Phase
+ 'SPCR_SPR': '$3', # SPI Clock Rate Selects
+ 'SPSR' : '$38', # SPI Status Register
+ 'SPSR_SPIF': '$80', # SPI Interrupt Flag
+ 'SPSR_WCOL': '$40', # Write Collision Flag
+ 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
+ 'SPDR' : '$56', # SPI Data Register
+
+# Module WATCHDOG
+ 'WDTCSR' : '$82', # Watchdog Timer Control Registe
+ 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
+ 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
+ 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
+ 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
+ 'WDTCSR_WDE': '$8', # Watch Dog Enable
+
+# Module EXTERNAL_INTERRUPT
+ 'EICRA' : '$89', # External Interrupt Control Reg
+ 'EICRA_ISC2': '$30', # External Interrupt Sense Contr
+ 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
+ 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
+ 'EIMSK' : '$41', # External Interrupt Mask Regist
+ 'EIMSK_INT': '$7', # External Interrupt Request 2 E
+ 'EIFR' : '$40', # External Interrupt Flag Regist
+ 'EIFR_INTF': '$7', # External Interrupt Flags
+
+# Module AD_CONVERTER
+ 'ADMUX' : '$28', # The ADC multiplexer Selection
+ 'ADMUX_REFS': '$c0', # Reference Selection Bits
+ 'ADMUX_ADLAR': '$20', # Left Adjust Result
+ 'ADMUX_MUX': '$f', # Analog Channel and Gain Select
+ 'ADCSRA' : '$26', # The ADC Control and Status reg
+ 'ADCSRA_ADEN': '$80', # ADC Enable
+ 'ADCSRA_ADSC': '$40', # ADC Start Conversion
+ 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
+ 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
+ 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
+ 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
+ 'ADC' : '$4c', # ADC Data Register Bytes
+ 'ADCSRB' : '$27', # ADC Control and Status Registe
+ 'ADCSRB_ADHSM': '$80', # ADC High Speed Mode
+ 'ADCSRB_ADNCDIS': '$40', # ADC Noise Canceller Disable
+ 'ADCSRB_ADSSEN': '$10', # ADC Single Shot Enable on PSC'
+ 'ADCSRB_ADTS': '$f', # ADC Auto Trigger Sources
+ 'DIDR0' : '$77', # Digital Input Disable Register
+ 'DIDR0_ADC7D': '$80', #
+ 'DIDR0_ADC6D': '$40', # ADC7 Digital input Disable
+ 'DIDR0_ADC5D': '$20', # ADC5 Digital input Disable
+ 'DIDR0_ADC4D': '$10', # ADC4 Digital input Disable
+ 'DIDR0_ADC3D': '$8', # ADC3 Digital input Disable
+ 'DIDR0_ADC2D': '$4', # ADC2 Digital input Disable
+ 'DIDR0_ADC1D': '$2', # ADC1 Digital input Disable
+ 'DIDR0_ADC0D': '$1', # ADC0 Digital input Disable
+ 'DIDR1' : '$78', # Digital Input Disable Register
+ 'DIDR1_ACMP1MD': '$8', #
+ 'DIDR1_AMP0POSD': '$4', #
+ 'DIDR1_ADC10D': '$2', #
+ 'DIDR1_ADC9D': '$1', #
+ 'AMP0CSR' : '$79', #
+ 'AMP0CSR_AMP0EN': '$80', #
+ 'AMP0CSR_AMP0IS': '$40', #
+ 'AMP0CSR_AMP0G': '$30', #
+ 'AMP0CSR_AMP0GS': '$8', #
+ 'AMP0CSR_AMP0TS': '$3', #
+
+# Module ANALOG_COMPARATOR
+ 'AC3CON' : '$7f', # Analog Comparator3 Control Reg
+ 'AC3CON_AC3EN': '$80', # Analog Comparator3 Enable Bit
+ 'AC3CON_AC3IE': '$40', # Analog Comparator 3 Interrupt
+ 'AC3CON_AC3IS': '$30', # Analog Comparator 3 Interrupt
+ 'AC3CON_AC3OEA': '$8', # Analog Comparator 3 Alternate
+ 'AC3CON_AC3M': '$7', # Analog Comparator 3 Multiplexe
+ 'AC1CON' : '$7d', # Analog Comparator 1 Control Re
+ 'AC1CON_AC1EN': '$80', # Analog Comparator 1 Enable Bit
+ 'AC1CON_AC1IE': '$40', # Analog Comparator 1 Interrupt
+ 'AC1CON_AC1IS': '$30', # Analog Comparator 1 Interrupt
+ 'AC1CON_AC1M': '$7', # Analog Comparator 1 Multiplexe
+ 'AC2CON' : '$7e', # Analog Comparator 2 Control Re
+ 'AC2CON_AC2EN': '$80', # Analog Comparator 2 Enable Bit
+ 'AC2CON_AC2IE': '$40', # Analog Comparator 2 Interrupt
+ 'AC2CON_AC2IS': '$30', # Analog Comparator 2 Interrupt
+ 'AC2CON_AC2M': '$7', # Analog Comparator 2 Multiplexe
+ 'ACSR' : '$20', # Analog Comparator Status Regis
+ 'ACSR_AC3IF': '$80', # Analog Comparator 3 Interrupt
+ 'ACSR_AC2IF': '$40', # Analog Comparator 2 Interrupt
+ 'ACSR_AC1IF': '$20', # Analog Comparator 1 Interrupt
+ 'ACSR_AC3O': '$8', # Analog Comparator 3 Output Bit
+ 'ACSR_AC2O': '$4', # Analog Comparator 2 Output Bit
+ 'ACSR_AC1O': '$2', # Analog Comparator 1 Output Bit
+ 'AC3ECON' : '$7c', #
+ 'AC3ECON_AC3OI': '$20', # Analog Comparator Ouput Invert
+ 'AC3ECON_AC3OE': '$10', # Analog Comparator Ouput Enable
+ 'AC3ECON_AC3H': '$7', # Analog Comparator Hysteresis S
+ 'AC2ECON' : '$7b', #
+ 'AC2ECON_AC2OI': '$20', # Analog Comparator Ouput Invert
+ 'AC2ECON_AC2OE': '$10', # Analog Comparator Ouput Enable
+ 'AC2ECON_AC2H': '$7', # Analog Comparator Hysteresis S
+ 'AC1ECON' : '$7a', #
+ 'AC1ECON_AC1OI': '$20', # Analog Comparator Ouput Invert
+ 'AC1ECON_AC1OE': '$10', # Analog Comparator Ouput Enable
+ 'AC1ECON_AC1ICE': '$8', # Analog Comparator Interrupt Ca
+ 'AC1ECON_AC1H': '$7', # Analog Comparator Hysteresis S
+
+# Module CPU
+ 'SREG' : '$5f', # Status Register
+ 'SREG_I': '$80', # Global Interrupt Enable
+ 'SREG_T': '$40', # Bit Copy Storage
+ 'SREG_H': '$20', # Half Carry Flag
+ 'SREG_S': '$10', # Sign Bit
+ 'SREG_V': '$8', # Two's Complement Overflow Flag
+ 'SREG_N': '$4', # Negative Flag
+ 'SREG_Z': '$2', # Zero Flag
+ 'SREG_C': '$1', # Carry Flag
+ 'SP' : '$5d', # Stack Pointer
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_PUD': '$10', # Pull-up disable
+ 'MCUCR_RSTDIS': '$8', # Reset Pin Disable
+ 'MCUCR_CKRC81': '$4', # Frequency Selection of the Cal
+ 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
+ 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
+ 'MCUSR_BORF': '$4', # Brown-out Reset Flag
+ 'MCUSR_EXTRF': '$2', # External Reset Flag
+ 'MCUSR_PORF': '$1', # Power-on reset flag
+ 'OSCCAL' : '$88', # Oscillator Calibration Value
+ 'CLKPR' : '$83', #
+ 'CLKPR_CLKPCE': '$80', #
+ 'CLKPR_CLKPS': '$f', #
+ 'SMCR' : '$53', # Sleep Mode Control Register
+ 'SMCR_SM': '$e', # Sleep Mode Select bits
+ 'SMCR_SE': '$1', # Sleep Enable
+ 'GPIOR2' : '$3b', # General Purpose IO Register 2
+ 'GPIOR2_GPIOR': '$ff', # General Purpose IO Register 2
+ 'GPIOR1' : '$3a', # General Purpose IO Register 1
+ 'GPIOR1_GPIOR': '$ff', # General Purpose IO Register 1
+ 'GPIOR0' : '$39', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR07': '$80', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR06': '$40', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR05': '$20', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR04': '$10', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR03': '$8', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR02': '$4', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR01': '$2', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR00': '$1', # General Purpose IO Register 0
+ 'PLLCSR' : '$87', # PLL Control And Status Registe
+ 'PLLCSR_PLLF': '$3c', #
+ 'PLLCSR_PLLE': '$2', # PLL Enable
+ 'PLLCSR_PLOCK': '$1', # PLL Lock Detector
+ 'PRR' : '$86', # Power Reduction Register
+ 'PRR_PRPSC2': '$80', # Power Reduction PSC2
+ 'PRR_PRPSCR': '$20', # Power Reduction PSC0
+ 'PRR_PRTIM1': '$10', # Power Reduction Timer/Counter1
+ 'PRR_PRSPI': '$4', # Power Reduction Serial Periphe
+ 'PRR_PRADC': '$1', # Power Reduction ADC
+ 'CLKCSR' : '$84', #
+ 'CLKCSR_CLKCCE': '$80', # Clock Control Change Enable
+ 'CLKCSR_CLKRDY': '$10', # Clock Ready Flag
+ 'CLKCSR_CLKC': '$f', # Clock Control
+ 'CLKSELR' : '$85', #
+ 'CLKSELR_COUT': '$40', # Clock OUT
+ 'CLKSELR_CSUT': '$30', # Clock Start up Time
+ 'CLKSELR_CKSEL': '$f', # Clock Source Select
+ 'BGCCR' : '$81', # BandGap Current Calibration Re
+ 'BGCCR_BGCC': '$f', #
+ 'BGCRR' : '$80', # BandGap Resistor Calibration R
+ 'BGCRR_BGCR': '$f', #
+
+# Module EEPROM
+ 'EEAR' : '$3e', # EEPROM Read/Write Access Byte
+ 'EEDR' : '$3d', # EEPROM Data Register
+ 'EECR' : '$3c', # EEPROM Control Register
+ 'EECR_NVMBSY': '$80', # None Volatile Busy Memory Busy
+ 'EECR_EEPAGE': '$40', # EEPROM Page Access
+ 'EECR_EEPM': '$30', # EEPROM Programming Mode
+ 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
+ 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
+ 'EECR_EEWE': '$2', # EEPROM Write Enable
+ 'EECR_EERE': '$1', # EEPROM Read Enable
+
+# Module PSC0
+ 'PICR0' : '$68', # PSC 0 Input Capture Register
+ 'PFRC0B' : '$63', # PSC 0 Input B Control
+ 'PFRC0B_PCAE0B': '$80', # PSC 0 Capture Enable Input Par
+ 'PFRC0B_PISEL0B': '$40', # PSC 0 Input Select for Part B
+ 'PFRC0B_PELEV0B': '$20', # PSC 0 Edge Level Selector on I
+ 'PFRC0B_PFLTE0B': '$10', # PSC 0 Filter Enable on Input P
+ 'PFRC0B_PRFM0B': '$f', # PSC 0 Retrigger and Fault Mode
+ 'PFRC0A' : '$62', # PSC 0 Input A Control
+ 'PFRC0A_PCAE0A': '$80', # PSC 0 Capture Enable Input Par
+ 'PFRC0A_PISEL0A': '$40', # PSC 0 Input Select for Part A
+ 'PFRC0A_PELEV0A': '$20', # PSC 0 Edge Level Selector on I
+ 'PFRC0A_PFLTE0A': '$10', # PSC 0 Filter Enable on Input P
+ 'PFRC0A_PRFM0A': '$f', # PSC 0 Retrigger and Fault Mode
+ 'PCTL0' : '$32', # PSC 0 Control Register
+ 'PCTL0_PPRE0': '$c0', # PSC 0 Prescaler Selects
+ 'PCTL0_PBFM0': '$24', # PSC 0 Balance Flank Width Modu
+ 'PCTL0_PAOC0B': '$10', # PSC 0 Asynchronous Output Cont
+ 'PCTL0_PAOC0A': '$8', # PSC 0 Asynchronous Output Cont
+ 'PCTL0_PCCYC0': '$2', # PSC0 Complete Cycle
+ 'PCTL0_PRUN0': '$1', # PSC 0 Run
+ 'PCNF0' : '$31', # PSC 0 Configuration Register
+ 'PCNF0_PFIFTY0': '$80', # PSC 0 Fifty
+ 'PCNF0_PALOCK0': '$40', # PSC 0 Autolock
+ 'PCNF0_PLOCK0': '$20', # PSC 0 Lock
+ 'PCNF0_PMODE0': '$18', # PSC 0 Mode
+ 'PCNF0_POP0': '$4', # PSC 0 Output Polarity
+ 'PCNF0_PCLKSEL0': '$2', # PSC 0 Input Clock Select
+ 'OCR0RB' : '$44', # Output Compare RB Register
+ 'OCR0SB' : '$42', # Output Compare SB Register
+ 'OCR0RA' : '$4a', # Output Compare RA Register
+ 'OCR0SA' : '$60', # Output Compare SA Register
+ 'PSOC0' : '$6a', # PSC0 Synchro and Output Config
+ 'PSOC0_PISEL0A1': '$80', # PSC Input Select
+ 'PSOC0_PISEL0B1': '$40', # PSC Input Select
+ 'PSOC0_PSYNC0': '$30', # Synchronisation out for ADC se
+ 'PSOC0_POEN0B': '$4', # PSCOUT01 Output Enable
+ 'PSOC0_POEN0A': '$1', # PSCOUT00 Output Enable
+ 'PIM0' : '$2f', # PSC0 Interrupt Mask Register
+ 'PIM0_PEVE0B': '$10', # External Event B Interrupt Ena
+ 'PIM0_PEVE0A': '$8', # External Event A Interrupt Ena
+ 'PIM0_PEOEPE0': '$2', # End of Enhanced Cycle Enable
+ 'PIM0_PEOPE0': '$1', # End of Cycle Interrupt Enable
+ 'PIFR0' : '$30', # PSC0 Interrupt Flag Register
+ 'PIFR0_POAC0B': '$80', # PSC 0 Output A Activity
+ 'PIFR0_POAC0A': '$40', # PSC 0 Output A Activity
+ 'PIFR0_PEV0B': '$10', # External Event B Interrupt
+ 'PIFR0_PEV0A': '$8', # External Event A Interrupt
+ 'PIFR0_PRN0': '$6', # Ramp Number
+ 'PIFR0_PEOP0': '$1', # End of PSC0 Interrupt
+
+# Module PSC2
+ 'PICR2H' : '$6d', # PSC 2 Input Capture Register H
+ 'PICR2H_PCST2': '$80', # PSC 2 Capture Software Trigger
+ 'PICR2H_PICR21': '$c', #
+ 'PICR2H_PICR2': '$3', #
+ 'PICR2L' : '$6c', # PSC 2 Input Capture Register L
+ 'PFRC2B' : '$67', # PSC 2 Input B Control
+ 'PFRC2B_PCAE2B': '$80', # PSC 2 Capture Enable Input Par
+ 'PFRC2B_PISEL2B': '$40', # PSC 2 Input Select for Part B
+ 'PFRC2B_PELEV2B': '$20', # PSC 2 Edge Level Selector on I
+ 'PFRC2B_PFLTE2B': '$10', # PSC 2 Filter Enable on Input P
+ 'PFRC2B_PRFM2B': '$f', # PSC 2 Retrigger and Fault Mode
+ 'PFRC2A' : '$66', # PSC 2 Input B Control
+ 'PFRC2A_PCAE2A': '$80', # PSC 2 Capture Enable Input Par
+ 'PFRC2A_PISEL2A': '$40', # PSC 2 Input Select for Part A
+ 'PFRC2A_PELEV2A': '$20', # PSC 2 Edge Level Selector on I
+ 'PFRC2A_PFLTE2A': '$10', # PSC 2 Filter Enable on Input P
+ 'PFRC2A_PRFM2A': '$f', # PSC 2 Retrigger and Fault Mode
+ 'PCTL2' : '$36', # PSC 2 Control Register
+ 'PCTL2_PPRE2': '$c0', # PSC 2 Prescaler Selects
+ 'PCTL2_PBFM2': '$20', # Balance Flank Width Modulation
+ 'PCTL2_PAOC2B': '$10', # PSC 2 Asynchronous Output Cont
+ 'PCTL2_PAOC2A': '$8', # PSC 2 Asynchronous Output Cont
+ 'PCTL2_PARUN2': '$4', # PSC2 Auto Run
+ 'PCTL2_PCCYC2': '$2', # PSC2 Complete Cycle
+ 'PCTL2_PRUN2': '$1', # PSC 2 Run
+ 'PCNF2' : '$35', # PSC 2 Configuration Register
+ 'PCNF2_PFIFTY2': '$80', # PSC 2 Fifty
+ 'PCNF2_PALOCK2': '$40', # PSC 2 Autolock
+ 'PCNF2_PLOCK2': '$20', # PSC 2 Lock
+ 'PCNF2_PMODE2': '$18', # PSC 2 Mode
+ 'PCNF2_POP2': '$4', # PSC 2 Output Polarity
+ 'PCNF2_PCLKSEL2': '$2', # PSC 2 Input Clock Select
+ 'PCNF2_POME2': '$1', # PSC 2 Output Matrix Enable
+ 'PCNFE2' : '$70', # PSC 2 Enhanced Configuration R
+ 'PCNFE2_PASDLK2': '$e0', #
+ 'PCNFE2_PBFM21': '$10', #
+ 'PCNFE2_PELEV2A1': '$8', #
+ 'PCNFE2_PELEV2B1': '$4', #
+ 'PCNFE2_PISEL2A1': '$2', #
+ 'PCNFE2_PISEL2B1': '$1', #
+ 'OCR2RB' : '$48', # Output Compare RB Register
+ 'OCR2SB' : '$46', # Output Compare SB Register
+ 'OCR2RA' : '$4e', # Output Compare RA Register
+ 'OCR2SA' : '$64', # Output Compare SA Register
+ 'POM2' : '$6f', # PSC 2 Output Matrix
+ 'POM2_POMV2B': '$f0', # Output Matrix Output B Ramps
+ 'POM2_POMV2A': '$f', # Output Matrix Output A Ramps
+ 'PSOC2' : '$6e', # PSC2 Synchro and Output Config
+ 'PSOC2_POS2': '$c0', # PSC 2 Output 23 Select
+ 'PSOC2_PSYNC2': '$30', # Synchronization Out for ADC Se
+ 'PSOC2_POEN2D': '$8', # PSCOUT23 Output Enable
+ 'PSOC2_POEN2B': '$4', # PSCOUT21 Output Enable
+ 'PSOC2_POEN2C': '$2', # PSCOUT22 Output Enable
+ 'PSOC2_POEN2A': '$1', # PSCOUT20 Output Enable
+ 'PIM2' : '$33', # PSC2 Interrupt Mask Register
+ 'PIM2_PSEIE2': '$20', # PSC 2 Synchro Error Interrupt
+ 'PIM2_PEVE2B': '$10', # External Event B Interrupt Ena
+ 'PIM2_PEVE2A': '$8', # External Event A Interrupt Ena
+ 'PIM2_PEOEPE2': '$2', # End of Enhanced Cycle Interrup
+ 'PIM2_PEOPE2': '$1', # End of Cycle Interrupt Enable
+ 'PIFR2' : '$34', # PSC2 Interrupt Flag Register
+ 'PIFR2_POAC2B': '$80', # PSC 2 Output A Activity
+ 'PIFR2_POAC2A': '$40', # PSC 2 Output A Activity
+ 'PIFR2_PSEI2': '$20', # PSC 2 Synchro Error Interrupt
+ 'PIFR2_PEV2B': '$10', # External Event B Interrupt
+ 'PIFR2_PEV2A': '$8', # External Event A Interrupt
+ 'PIFR2_PRN2': '$6', # Ramp Number
+ 'PIFR2_PEOP2': '$1', # End of PSC2 Interrupt
+ 'PASDLY2' : '$71', # Analog Synchronization Delay R
+
+# Module TIMER_COUNTER_1
+ 'TIMSK1' : '$21', # Timer/Counter Interrupt Mask R
+ 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
+ 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
+ 'TIFR1' : '$22', # Timer/Counter Interrupt Flag r
+ 'TIFR1_ICF1': '$20', # Input Capture Flag 1
+ 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
+ 'TCCR1B' : '$8a', # Timer/Counter1 Control Registe
+ 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
+ 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
+ 'TCCR1B_WGM13': '$10', # Waveform Generation Mode
+ 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
+ 'TCNT1' : '$5a', # Timer/Counter1 Bytes
+ 'ICR1' : '$8c', # Timer/Counter1 Input Capture R
+
+# Module BOOT_LOAD
+ 'SPMCSR' : '$57', # Store Program Memory Control R
+ 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
+ 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
+ 'SPMCSR_SIGRD': '$20', # Signature Row Read
+ 'SPMCSR_RWWSRE': '$10', # Read While Write section read
+ 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
+ 'SPMCSR_PGWRT': '$4', # Page Write
+ 'SPMCSR_PGERS': '$2', # Page Erase
+ 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
+
+ '__amforth_dummy':'0'
+}
diff --git a/amforth-6.5/avr8/devices/at90pwm81/words/no-jtag.asm b/amforth-6.5/avr8/devices/at90pwm81/words/no-jtag.asm
new file mode 100644
index 0000000..352a4bb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90pwm81/words/no-jtag.asm
@@ -0,0 +1,14 @@
+; ( -- )
+; ( -- )
+; MCU
+; disable jtag at runtime
+VE_NOJTAG:
+ .dw $FF05
+ .db "-jtag",0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOJTAG
+XT_NOJTAG:
+ .dw PFA_NOJTAG
+PFA_NOJTAG:
+
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/at90pwm81/words/no-wdt.asm b/amforth-6.5/avr8/devices/at90pwm81/words/no-wdt.asm
new file mode 100644
index 0000000..ff6ddd1
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90pwm81/words/no-wdt.asm
@@ -0,0 +1,34 @@
+; ( -- )
+; MCU
+; disable watch dog timer at runtime
+VE_NOWDT:
+ .dw $ff04
+ .db "-wdt"
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOWDT
+XT_NOWDT:
+ .dw PFA_NOWDT
+PFA_NOWDT:
+
+ in temp1,SREG
+ push temp1
+ ; Turn always off global interrupt.
+ cli
+ ; Reset Watchdog Timer
+ wdr
+ ; Clear WDRF in MCUSR
+ in temp1, MCUSR
+ andi temp1, (0xff & (0<<WDRF))
+ out MCUSR, temp1
+ ; Write logical one to WDCE and WDE
+ ; Keep old prescaler setting to prevent unintentional time-out
+ in_ temp1, WDTCSR
+ ori temp1, (1<<WDCE) | (1<<WDE)
+ out_ WDTCSR, temp1
+ ; Turn off WDT
+ ldi temp1, (0<<WDE)
+ out_ WDTCSR, temp1
+ ; restore status register
+ pop temp1
+ out SREG,temp1
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/at90pwm81/words/sleep.asm b/amforth-6.5/avr8/devices/at90pwm81/words/sleep.asm
new file mode 100644
index 0000000..256249c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90pwm81/words/sleep.asm
@@ -0,0 +1,19 @@
+; ( mode -- )
+; MCU
+; put the controller into the specified sleep mode
+VE_SLEEP:
+ .dw $ff05
+ .db "sleep", 0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_SLEEP
+XT_SLEEP:
+ .dw PFA_SLEEP
+PFA_SLEEP:
+ andi tosl, 7 ; leave only legal mode bits
+ lsl tosl ; move to correct location (bits 3-1)
+ ori tosl, 1 ; set the SE bit
+ out_ SMCR, tosl ; set the sleep config
+ sleep ; nighty-night
+ out_ SMCR, zerol ; 0 protects against accidental sleeps
+ loadtos ; pop argument from stack
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/at90usb1286/at90usb1286.frt b/amforth-6.5/avr8/devices/at90usb1286/at90usb1286.frt
new file mode 100644
index 0000000..850e5e7
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90usb1286/at90usb1286.frt
@@ -0,0 +1,486 @@
+\ Partname: AT90USB1286
+\ generated automatically
+
+\ WATCHDOG
+&96 constant WDTCSR \ Watchdog Timer Control Register
+ $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Flag
+ $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Enable
+ $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
+ $10 constant WDTCSR_WDCE \ Watchdog Change Enable
+ $08 constant WDTCSR_WDE \ Watch Dog Enable
+\ PORTA
+&34 constant PORTA \ Port A Data Register
+&33 constant DDRA \ Port A Data Direction Register
+&32 constant PINA \ Port A Input Pins
+\ PORTB
+&37 constant PORTB \ Port B Data Register
+&36 constant DDRB \ Port B Data Direction Register
+&35 constant PINB \ Port B Input Pins
+\ PORTC
+&40 constant PORTC \ Port C Data Register
+&39 constant DDRC \ Port C Data Direction Register
+&38 constant PINC \ Port C Input Pins
+\ PORTD
+&43 constant PORTD \ Port D Data Register
+&42 constant DDRD \ Port D Data Direction Register
+&41 constant PIND \ Port D Input Pins
+\ PORTE
+&46 constant PORTE \ Data Register, Port E
+&45 constant DDRE \ Data Direction Register, Port E
+&44 constant PINE \ Input Pins, Port E
+\ PORTF
+&49 constant PORTF \ Data Register, Port F
+&48 constant DDRF \ Data Direction Register, Port F
+&47 constant PINF \ Input Pins, Port F
+\ CPU
+&95 constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ $08 constant SREG_V \ Two's Complement Overflow Flag
+ $04 constant SREG_N \ Negative Flag
+ $02 constant SREG_Z \ Zero Flag
+ $01 constant SREG_C \ Carry Flag
+&93 constant SP \ Stack Pointer
+&85 constant MCUCR \ MCU Control Register
+ $80 constant MCUCR_JTD \ JTAG Interface Disable
+ $10 constant MCUCR_PUD \ Pull-up disable
+ $02 constant MCUCR_IVSEL \ Interrupt Vector Select
+ $01 constant MCUCR_IVCE \ Interrupt Vector Change Enable
+&84 constant MCUSR \ MCU Status Register
+ $10 constant MCUSR_JTRF \ JTAG Reset Flag
+ $08 constant MCUSR_WDRF \ Watchdog Reset Flag
+ $04 constant MCUSR_BORF \ Brown-out Reset Flag
+ $02 constant MCUSR_EXTRF \ External Reset Flag
+ $01 constant MCUSR_PORF \ Power-on reset flag
+&116 constant XMCRA \ External Memory Control Register A
+ $80 constant XMCRA_SRE \ External SRAM Enable
+ $70 constant XMCRA_SRL \ Wait state page limit
+ $0C constant XMCRA_SRW1 \ Wait state select bit upper page
+ $03 constant XMCRA_SRW0 \ Wait state select bit lower page
+&117 constant XMCRB \ External Memory Control Register B
+ $80 constant XMCRB_XMBK \ External Memory Bus Keeper Enable
+ $07 constant XMCRB_XMM \ External Memory High Mask
+&102 constant OSCCAL \ Oscillator Calibration Value
+&97 constant CLKPR \
+ $80 constant CLKPR_CLKPCE \
+ $0F constant CLKPR_CLKPS \
+&83 constant SMCR \ Sleep Mode Control Register
+ $0E constant SMCR_SM \ Sleep Mode Select bits
+ $01 constant SMCR_SE \ Sleep Enable
+&92 constant EIND \ Extended Indirect Register
+&91 constant RAMPZ \ RAM Page Z Select Register
+&75 constant GPIOR2 \ General Purpose IO Register 2
+ $FF constant GPIOR2_GPIOR \ General Purpose IO Register 2 bis
+&74 constant GPIOR1 \ General Purpose IO Register 1
+ $FF constant GPIOR1_GPIOR \ General Purpose IO Register 1 bis
+&62 constant GPIOR0 \ General Purpose IO Register 0
+ $80 constant GPIOR0_GPIOR07 \ General Purpose IO Register 0 bit 7
+ $40 constant GPIOR0_GPIOR06 \ General Purpose IO Register 0 bit 6
+ $20 constant GPIOR0_GPIOR05 \ General Purpose IO Register 0 bit 5
+ $10 constant GPIOR0_GPIOR04 \ General Purpose IO Register 0 bit 4
+ $08 constant GPIOR0_GPIOR03 \ General Purpose IO Register 0 bit 3
+ $04 constant GPIOR0_GPIOR02 \ General Purpose IO Register 0 bit 2
+ $02 constant GPIOR0_GPIOR01 \ General Purpose IO Register 0 bit 1
+ $01 constant GPIOR0_GPIOR00 \ General Purpose IO Register 0 bit 0
+&101 constant PRR1 \ Power Reduction Register1
+ $80 constant PRR1_PRUSB \ Power Reduction USB
+ $08 constant PRR1_PRTIM3 \ Power Reduction Timer/Counter3
+ $01 constant PRR1_PRUSART1 \ Power Reduction USART1
+&100 constant PRR0 \ Power Reduction Register0
+ $80 constant PRR0_PRTWI \ Power Reduction TWI
+ $40 constant PRR0_PRTIM2 \ Power Reduction Timer/Counter2
+ $20 constant PRR0_PRTIM0 \ Power Reduction Timer/Counter0
+ $08 constant PRR0_PRTIM1 \ Power Reduction Timer/Counter1
+ $04 constant PRR0_PRSPI \ Power Reduction Serial Peripheral Interface
+ $01 constant PRR0_PRADC \ Power Reduction ADC
+\ TWI
+&189 constant TWAMR \ TWI (Slave) Address Mask Register
+ $FE constant TWAMR_TWAM \
+&184 constant TWBR \ TWI Bit Rate register
+&188 constant TWCR \ TWI Control Register
+ $80 constant TWCR_TWINT \ TWI Interrupt Flag
+ $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
+ $20 constant TWCR_TWSTA \ TWI Start Condition Bit
+ $10 constant TWCR_TWSTO \ TWI Stop Condition Bit
+ $08 constant TWCR_TWWC \ TWI Write Collition Flag
+ $04 constant TWCR_TWEN \ TWI Enable Bit
+ $01 constant TWCR_TWIE \ TWI Interrupt Enable
+&185 constant TWSR \ TWI Status Register
+ $F8 constant TWSR_TWS \ TWI Status
+ $03 constant TWSR_TWPS \ TWI Prescaler
+&187 constant TWDR \ TWI Data register
+&186 constant TWAR \ TWI (Slave) Address register
+ $FE constant TWAR_TWA \ TWI (Slave) Address register Bits
+ $01 constant TWAR_TWGCE \ TWI General Call Recognition Enable Bit
+\ SPI
+&76 constant SPCR \ SPI Control Register
+ $80 constant SPCR_SPIE \ SPI Interrupt Enable
+ $40 constant SPCR_SPE \ SPI Enable
+ $20 constant SPCR_DORD \ Data Order
+ $10 constant SPCR_MSTR \ Master/Slave Select
+ $08 constant SPCR_CPOL \ Clock polarity
+ $04 constant SPCR_CPHA \ Clock Phase
+ $03 constant SPCR_SPR \ SPI Clock Rate Selects
+&77 constant SPSR \ SPI Status Register
+ $80 constant SPSR_SPIF \ SPI Interrupt Flag
+ $40 constant SPSR_WCOL \ Write Collision Flag
+ $01 constant SPSR_SPI2X \ Double SPI Speed Bit
+&78 constant SPDR \ SPI Data Register
+\ USART1
+&206 constant UDR1 \ USART I/O Data Register
+&200 constant UCSR1A \ USART Control and Status Register A
+ $80 constant UCSR1A_RXC1 \ USART Receive Complete
+ $40 constant UCSR1A_TXC1 \ USART Transmitt Complete
+ $20 constant UCSR1A_UDRE1 \ USART Data Register Empty
+ $10 constant UCSR1A_FE1 \ Framing Error
+ $08 constant UCSR1A_DOR1 \ Data overRun
+ $04 constant UCSR1A_UPE1 \ Parity Error
+ $02 constant UCSR1A_U2X1 \ Double the USART transmission speed
+ $01 constant UCSR1A_MPCM1 \ Multi-processor Communication Mode
+&201 constant UCSR1B \ USART Control and Status Register B
+ $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable
+ $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable
+ $20 constant UCSR1B_UDRIE1 \ USART Data register Empty Interrupt Enable
+ $10 constant UCSR1B_RXEN1 \ Receiver Enable
+ $08 constant UCSR1B_TXEN1 \ Transmitter Enable
+ $04 constant UCSR1B_UCSZ12 \ Character Size
+ $02 constant UCSR1B_RXB81 \ Receive Data Bit 8
+ $01 constant UCSR1B_TXB81 \ Transmit Data Bit 8
+&202 constant UCSR1C \ USART Control and Status Register C
+ $C0 constant UCSR1C_UMSEL1 \ USART Mode Select
+ $30 constant UCSR1C_UPM1 \ Parity Mode Bits
+ $08 constant UCSR1C_USBS1 \ Stop Bit Select
+ $06 constant UCSR1C_UCSZ1 \ Character Size
+ $01 constant UCSR1C_UCPOL1 \ Clock Polarity
+&204 constant UBRR1 \ USART Baud Rate Register Bytes
+\ USB_DEVICE
+&244 constant UEINT \
+&243 constant UEBCHX \
+&242 constant UEBCLX \
+&241 constant UEDATX \
+&240 constant UEIENX \
+ $80 constant UEIENX_FLERRE \
+ $40 constant UEIENX_NAKINE \
+ $10 constant UEIENX_NAKOUTE \
+ $08 constant UEIENX_RXSTPE \
+ $04 constant UEIENX_RXOUTE \
+ $02 constant UEIENX_STALLEDE \
+ $01 constant UEIENX_TXINE \
+&239 constant UESTA1X \
+ $04 constant UESTA1X_CTRLDIR \
+ $03 constant UESTA1X_CURRBK \
+&238 constant UESTA0X \
+ $80 constant UESTA0X_CFGOK \
+ $40 constant UESTA0X_OVERFI \
+ $20 constant UESTA0X_UNDERFI \
+ $0C constant UESTA0X_DTSEQ \
+ $03 constant UESTA0X_NBUSYBK \
+&237 constant UECFG1X \
+ $70 constant UECFG1X_EPSIZE \
+ $0C constant UECFG1X_EPBK \
+ $02 constant UECFG1X_ALLOC \
+&236 constant UECFG0X \
+ $C0 constant UECFG0X_EPTYPE \
+ $01 constant UECFG0X_EPDIR \
+&235 constant UECONX \
+ $20 constant UECONX_STALLRQ \
+ $10 constant UECONX_STALLRQC \
+ $08 constant UECONX_RSTDT \
+ $01 constant UECONX_EPEN \
+&234 constant UERST \
+ $7F constant UERST_EPRST \
+&233 constant UENUM \
+&232 constant UEINTX \
+ $80 constant UEINTX_FIFOCON \
+ $40 constant UEINTX_NAKINI \
+ $20 constant UEINTX_RWAL \
+ $10 constant UEINTX_NAKOUTI \
+ $08 constant UEINTX_RXSTPI \
+ $04 constant UEINTX_RXOUTI \
+ $02 constant UEINTX_STALLEDI \
+ $01 constant UEINTX_TXINI \
+&230 constant UDMFN \
+ $10 constant UDMFN_FNCERR \
+&228 constant UDFNUM \
+&227 constant UDADDR \
+ $80 constant UDADDR_ADDEN \
+ $7F constant UDADDR_UADD \
+&226 constant UDIEN \
+ $40 constant UDIEN_UPRSME \
+ $20 constant UDIEN_EORSME \
+ $10 constant UDIEN_WAKEUPE \
+ $08 constant UDIEN_EORSTE \
+ $04 constant UDIEN_SOFE \
+ $01 constant UDIEN_SUSPE \
+&225 constant UDINT \
+ $40 constant UDINT_UPRSMI \
+ $20 constant UDINT_EORSMI \
+ $10 constant UDINT_WAKEUPI \
+ $08 constant UDINT_EORSTI \
+ $04 constant UDINT_SOFI \
+ $01 constant UDINT_SUSPI \
+&224 constant UDCON \
+ $04 constant UDCON_LSM \
+ $02 constant UDCON_RMWKUP \
+ $01 constant UDCON_DETACH \
+\ BOOT_LOAD
+&87 constant SPMCSR \ Store Program Memory Control Register
+ $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
+ $20 constant SPMCSR_SIGRD \ Signature Row Read
+ $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
+ $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
+ $04 constant SPMCSR_PGWRT \ Page Write
+ $02 constant SPMCSR_PGERS \ Page Erase
+ $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
+\ EEPROM
+&65 constant EEAR \ EEPROM Address Register Low Bytes
+&64 constant EEDR \ EEPROM Data Register
+&63 constant EECR \ EEPROM Control Register
+ $30 constant EECR_EEPM \ EEPROM Programming Mode Bits
+ $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
+ $04 constant EECR_EEMPE \ EEPROM Master Write Enable
+ $02 constant EECR_EEPE \ EEPROM Write Enable
+ $01 constant EECR_EERE \ EEPROM Read Enable
+\ TIMER_COUNTER_0
+&72 constant OCR0B \ Timer/Counter0 Output Compare Register
+&71 constant OCR0A \ Timer/Counter0 Output Compare Register
+&70 constant TCNT0 \ Timer/Counter0
+&69 constant TCCR0B \ Timer/Counter Control Register B
+ $80 constant TCCR0B_FOC0A \ Force Output Compare A
+ $40 constant TCCR0B_FOC0B \ Force Output Compare B
+ $08 constant TCCR0B_WGM02 \
+ $07 constant TCCR0B_CS0 \ Clock Select
+&68 constant TCCR0A \ Timer/Counter Control Register A
+ $C0 constant TCCR0A_COM0A \ Compare Output Mode, Phase Correct PWM Mode
+ $30 constant TCCR0A_COM0B \ Compare Output Mode, Fast PWm
+ $03 constant TCCR0A_WGM0 \ Waveform Generation Mode
+&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
+ $04 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare Match B Interrupt Enable
+ $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match A Interrupt Enable
+ $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
+&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
+ $04 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare Flag 0B
+ $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0A
+ $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
+&67 constant GTCCR \ General Timer/Counter Control Register
+ $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
+ $01 constant GTCCR_PSRSYNC \ Prescaler Reset Timer/Counter1 and Timer/Counter0
+\ TIMER_COUNTER_2
+&112 constant TIMSK2 \ Timer/Counter Interrupt Mask register
+ $04 constant TIMSK2_OCIE2B \ Timer/Counter2 Output Compare Match B Interrupt Enable
+ $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match A Interrupt Enable
+ $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
+&55 constant TIFR2 \ Timer/Counter Interrupt Flag Register
+ $04 constant TIFR2_OCF2B \ Output Compare Flag 2B
+ $02 constant TIFR2_OCF2A \ Output Compare Flag 2A
+ $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
+&176 constant TCCR2A \ Timer/Counter2 Control Register A
+ $C0 constant TCCR2A_COM2A \ Compare Output Mode bits
+ $30 constant TCCR2A_COM2B \ Compare Output Mode bits
+ $03 constant TCCR2A_WGM2 \ Waveform Genration Mode
+&177 constant TCCR2B \ Timer/Counter2 Control Register B
+ $80 constant TCCR2B_FOC2A \ Force Output Compare A
+ $40 constant TCCR2B_FOC2B \ Force Output Compare B
+ $08 constant TCCR2B_WGM22 \ Waveform Generation Mode
+ $07 constant TCCR2B_CS2 \ Clock Select bits
+&178 constant TCNT2 \ Timer/Counter2
+&180 constant OCR2B \ Timer/Counter2 Output Compare Register B
+&179 constant OCR2A \ Timer/Counter2 Output Compare Register A
+&182 constant ASSR \ Asynchronous Status Register
+ $40 constant ASSR_EXCLK \ Enable External Clock Input
+ $20 constant ASSR_AS2 \ Asynchronous Timer/Counter2
+ $10 constant ASSR_TCN2UB \ Timer/Counter2 Update Busy
+ $08 constant ASSR_OCR2AUB \ Output Compare Register2 Update Busy
+ $04 constant ASSR_OCR2BUB \ Output Compare Register 2 Update Busy
+ $02 constant ASSR_TCR2AUB \ Timer/Counter Control Register2 Update Busy
+ $01 constant ASSR_TCR2BUB \ Timer/Counter Control Register2 Update Busy
+\ TIMER_COUNTER_3
+&144 constant TCCR3A \ Timer/Counter3 Control Register A
+ $C0 constant TCCR3A_COM3A \ Compare Output Mode 1A, bits
+ $30 constant TCCR3A_COM3B \ Compare Output Mode 3B, bits
+ $0C constant TCCR3A_COM3C \ Compare Output Mode 3C, bits
+ $03 constant TCCR3A_WGM3 \ Waveform Generation Mode
+&145 constant TCCR3B \ Timer/Counter3 Control Register B
+ $80 constant TCCR3B_ICNC3 \ Input Capture 3 Noise Canceler
+ $40 constant TCCR3B_ICES3 \ Input Capture 3 Edge Select
+ $18 constant TCCR3B_WGM3 \ Waveform Generation Mode
+ $07 constant TCCR3B_CS3 \ Prescaler source of Timer/Counter 3
+&146 constant TCCR3C \ Timer/Counter 3 Control Register C
+ $80 constant TCCR3C_FOC3A \ Force Output Compare 3A
+ $40 constant TCCR3C_FOC3B \ Force Output Compare 3B
+ $20 constant TCCR3C_FOC3C \ Force Output Compare 3C
+&148 constant TCNT3 \ Timer/Counter3 Bytes
+&152 constant OCR3A \ Timer/Counter3 Output Compare Register A Bytes
+&154 constant OCR3B \ Timer/Counter3 Output Compare Register B Bytes
+&156 constant OCR3C \ Timer/Counter3 Output Compare Register B Bytes
+&150 constant ICR3 \ Timer/Counter3 Input Capture Register Bytes
+&113 constant TIMSK3 \ Timer/Counter3 Interrupt Mask Register
+ $20 constant TIMSK3_ICIE3 \ Timer/Counter3 Input Capture Interrupt Enable
+ $08 constant TIMSK3_OCIE3C \ Timer/Counter3 Output Compare C Match Interrupt Enable
+ $04 constant TIMSK3_OCIE3B \ Timer/Counter3 Output Compare B Match Interrupt Enable
+ $02 constant TIMSK3_OCIE3A \ Timer/Counter3 Output Compare A Match Interrupt Enable
+ $01 constant TIMSK3_TOIE3 \ Timer/Counter3 Overflow Interrupt Enable
+&56 constant TIFR3 \ Timer/Counter3 Interrupt Flag register
+ $20 constant TIFR3_ICF3 \ Input Capture Flag 3
+ $08 constant TIFR3_OCF3C \ Output Compare Flag 3C
+ $04 constant TIFR3_OCF3B \ Output Compare Flag 3B
+ $02 constant TIFR3_OCF3A \ Output Compare Flag 3A
+ $01 constant TIFR3_TOV3 \ Timer/Counter3 Overflow Flag
+\ TIMER_COUNTER_1
+&128 constant TCCR1A \ Timer/Counter1 Control Register A
+ $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
+ $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
+ $0C constant TCCR1A_COM1C \ Compare Output Mode 1C, bits
+ $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
+&129 constant TCCR1B \ Timer/Counter1 Control Register B
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
+ $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
+&130 constant TCCR1C \ Timer/Counter 1 Control Register C
+ $80 constant TCCR1C_FOC1A \ Force Output Compare 1A
+ $40 constant TCCR1C_FOC1B \ Force Output Compare 1B
+ $20 constant TCCR1C_FOC1C \ Force Output Compare 1C
+&132 constant TCNT1 \ Timer/Counter1 Bytes
+&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
+&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
+&140 constant OCR1C \ Timer/Counter1 Output Compare Register C Bytes
+&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
+&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
+ $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
+ $08 constant TIMSK1_OCIE1C \ Timer/Counter1 Output Compare C Match Interrupt Enable
+ $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
+ $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
+ $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
+&54 constant TIFR1 \ Timer/Counter1 Interrupt Flag register
+ $20 constant TIFR1_ICF1 \ Input Capture Flag 1
+ $08 constant TIFR1_OCF1C \ Output Compare Flag 1C
+ $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
+ $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
+ $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
+\ JTAG
+&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
+\ EXTERNAL_INTERRUPT
+&105 constant EICRA \ External Interrupt Control Register A
+ $C0 constant EICRA_ISC3 \ External Interrupt Sense Control Bit
+ $30 constant EICRA_ISC2 \ External Interrupt Sense Control Bit
+ $0C constant EICRA_ISC1 \ External Interrupt Sense Control Bit
+ $03 constant EICRA_ISC0 \ External Interrupt Sense Control Bit
+&106 constant EICRB \ External Interrupt Control Register B
+ $C0 constant EICRB_ISC7 \ External Interrupt 7-4 Sense Control Bit
+ $30 constant EICRB_ISC6 \ External Interrupt 7-4 Sense Control Bit
+ $0C constant EICRB_ISC5 \ External Interrupt 7-4 Sense Control Bit
+ $03 constant EICRB_ISC4 \ External Interrupt 7-4 Sense Control Bit
+&61 constant EIMSK \ External Interrupt Mask Register
+ $FF constant EIMSK_INT \ External Interrupt Request 7 Enable
+&60 constant EIFR \ External Interrupt Flag Register
+ $FF constant EIFR_INTF \ External Interrupt Flags
+&107 constant PCMSK0 \ Pin Change Mask Register 0
+&59 constant PCIFR \ Pin Change Interrupt Flag Register
+ $01 constant PCIFR_PCIF0 \ Pin Change Interrupt Flag 0
+&104 constant PCICR \ Pin Change Interrupt Control Register
+ $01 constant PCICR_PCIE0 \ Pin Change Interrupt Enable 0
+\ AD_CONVERTER
+&124 constant ADMUX \ The ADC multiplexer Selection Register
+ $C0 constant ADMUX_REFS \ Reference Selection Bits
+ $20 constant ADMUX_ADLAR \ Left Adjust Result
+ $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
+&122 constant ADCSRA \ The ADC Control and Status register
+ $80 constant ADCSRA_ADEN \ ADC Enable
+ $40 constant ADCSRA_ADSC \ ADC Start Conversion
+ $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
+ $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
+ $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
+ $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
+&120 constant ADC \ ADC Data Register Bytes
+&123 constant ADCSRB \ ADC Control and Status Register B
+ $80 constant ADCSRB_ADHSM \ ADC High Speed Mode
+ $07 constant ADCSRB_ADTS \ ADC Auto Trigger Sources
+&126 constant DIDR0 \ Digital Input Disable Register 1
+ $80 constant DIDR0_ADC7D \ ADC7 Digital input Disable
+ $40 constant DIDR0_ADC6D \ ADC6 Digital input Disable
+ $20 constant DIDR0_ADC5D \ ADC5 Digital input Disable
+ $10 constant DIDR0_ADC4D \ ADC4 Digital input Disable
+ $08 constant DIDR0_ADC3D \ ADC3 Digital input Disable
+ $04 constant DIDR0_ADC2D \ ADC2 Digital input Disable
+ $02 constant DIDR0_ADC1D \ ADC1 Digital input Disable
+ $01 constant DIDR0_ADC0D \ ADC0 Digital input Disable
+\ ANALOG_COMPARATOR
+&80 constant ACSR \ Analog Comparator Control And Status Register
+ $80 constant ACSR_ACD \ Analog Comparator Disable
+ $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
+ $20 constant ACSR_ACO \ Analog Compare Output
+ $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
+ $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
+ $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
+ $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
+&127 constant DIDR1 \
+ $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
+ $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
+\ PLL
+&73 constant PLLCSR \ PLL Status and Control register
+ $1C constant PLLCSR_PLLP \ PLL prescaler Bits
+ $02 constant PLLCSR_PLLE \ PLL Enable Bit
+ $01 constant PLLCSR_PLOCK \ PLL Lock Status Bit
+\ USB_GLOBAL
+&218 constant USBINT \
+ $02 constant USBINT_IDTI \
+ $01 constant USBINT_VBUSTI \
+&217 constant USBSTA \
+ $08 constant USBSTA_SPEED \
+ $02 constant USBSTA_ID \
+ $01 constant USBSTA_VBUS \
+&216 constant USBCON \ USB General Control Register
+ $80 constant USBCON_USBE \
+ $40 constant USBCON_HOST \
+ $20 constant USBCON_FRZCLK \
+ $10 constant USBCON_OTGPADE \
+ $02 constant USBCON_IDTE \
+ $01 constant USBCON_VBUSTE \
+&215 constant UHWCON \ USB Hardware Configuration Register
+ $80 constant UHWCON_UIMOD \
+ $40 constant UHWCON_UIDE \
+ $10 constant UHWCON_UVCONE \
+ $01 constant UHWCON_UVREGE \
+
+\ Interrupts
+&2 constant INT0Addr \ External Interrupt Request 0
+&4 constant INT1Addr \ External Interrupt Request 1
+&6 constant INT2Addr \ External Interrupt Request 2
+&8 constant INT3Addr \ External Interrupt Request 3
+&10 constant INT4Addr \ External Interrupt Request 4
+&12 constant INT5Addr \ External Interrupt Request 5
+&14 constant INT6Addr \ External Interrupt Request 6
+&16 constant INT7Addr \ External Interrupt Request 7
+&18 constant PCINT0Addr \ Pin Change Interrupt Request 0
+&20 constant USB_GENAddr \ USB General Interrupt Request
+&22 constant USB_COMAddr \ USB Endpoint/Pipe Interrupt Communication Reque
+&24 constant WDTAddr \ Watchdog Time-out Interrupt
+&26 constant TIMER2_COMPAAddr \ Timer/Counter2 Compare Match A
+&28 constant TIMER2_COMPBAddr \ Timer/Counter2 Compare Match B
+&30 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
+&32 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+&34 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
+&36 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
+&38 constant TIMER1_COMPCAddr \ Timer/Counter1 Compare Match C
+&40 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+&42 constant TIMER0_COMPAAddr \ Timer/Counter0 Compare Match A
+&44 constant TIMER0_COMPBAddr \ Timer/Counter0 Compare Match B
+&46 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
+&48 constant SPI__STCAddr \ SPI Serial Transfer Complete
+&50 constant USART1__RXAddr \ USART1, Rx Complete
+&52 constant USART1__UDREAddr \ USART1 Data register Empty
+&54 constant USART1__TXAddr \ USART1, Tx Complete
+&56 constant ANALOG_COMPAddr \ Analog Comparator
+&58 constant ADCAddr \ ADC Conversion Complete
+&60 constant EE_READYAddr \ EEPROM Ready
+&62 constant TIMER3_CAPTAddr \ Timer/Counter3 Capture Event
+&64 constant TIMER3_COMPAAddr \ Timer/Counter3 Compare Match A
+&66 constant TIMER3_COMPBAddr \ Timer/Counter3 Compare Match B
+&68 constant TIMER3_COMPCAddr \ Timer/Counter3 Compare Match C
+&70 constant TIMER3_OVFAddr \ Timer/Counter3 Overflow
+&72 constant TWIAddr \ 2-wire Serial Interface
+&74 constant SPM_READYAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/at90usb1286/device.asm b/amforth-6.5/avr8/devices/at90usb1286/device.asm
new file mode 100644
index 0000000..74159f0
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90usb1286/device.asm
@@ -0,0 +1,145 @@
+; Partname: AT90USB1286
+; generated automatically, do not edit
+
+.nolist
+ .include "usb1286def.inc"
+.list
+
+.equ ramstart = 256
+.equ CELLSIZE = 2
+.macro readflashcell
+ clr temp7
+ lsl zl
+ rol zh
+ rol temp7
+ out_ RAMPZ, temp7
+ elpm @0, Z+
+ elpm @1, Z+
+.endmacro
+.macro writeflashcell
+ clr temp7
+ lsl zl
+ rol zh
+ rol temp7
+ out_ RAMPZ, temp7
+.endmacro
+.set WANT_WATCHDOG = 0
+.set WANT_PORTA = 0
+.set WANT_PORTB = 0
+.set WANT_PORTC = 0
+.set WANT_PORTD = 0
+.set WANT_PORTE = 0
+.set WANT_PORTF = 0
+.set WANT_CPU = 0
+.set WANT_TWI = 0
+.set WANT_SPI = 0
+.set WANT_USART1 = 0
+.set WANT_USB_DEVICE = 0
+.set WANT_BOOT_LOAD = 0
+.set WANT_EEPROM = 0
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_TIMER_COUNTER_2 = 0
+.set WANT_TIMER_COUNTER_3 = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_JTAG = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_AD_CONVERTER = 0
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_PLL = 0
+.set WANT_USB_GLOBAL = 0
+.equ intvecsize = 2 ; please verify; flash size: 131072 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.org 2
+ rcall isr ; External Interrupt Request 0
+.org 4
+ rcall isr ; External Interrupt Request 1
+.org 6
+ rcall isr ; External Interrupt Request 2
+.org 8
+ rcall isr ; External Interrupt Request 3
+.org 10
+ rcall isr ; External Interrupt Request 4
+.org 12
+ rcall isr ; External Interrupt Request 5
+.org 14
+ rcall isr ; External Interrupt Request 6
+.org 16
+ rcall isr ; External Interrupt Request 7
+.org 18
+ rcall isr ; Pin Change Interrupt Request 0
+.org 20
+ rcall isr ; USB General Interrupt Request
+.org 22
+ rcall isr ; USB Endpoint/Pipe Interrupt Communication Request
+.org 24
+ rcall isr ; Watchdog Time-out Interrupt
+.org 26
+ rcall isr ; Timer/Counter2 Compare Match A
+.org 28
+ rcall isr ; Timer/Counter2 Compare Match B
+.org 30
+ rcall isr ; Timer/Counter2 Overflow
+.org 32
+ rcall isr ; Timer/Counter1 Capture Event
+.org 34
+ rcall isr ; Timer/Counter1 Compare Match A
+.org 36
+ rcall isr ; Timer/Counter1 Compare Match B
+.org 38
+ rcall isr ; Timer/Counter1 Compare Match C
+.org 40
+ rcall isr ; Timer/Counter1 Overflow
+.org 42
+ rcall isr ; Timer/Counter0 Compare Match A
+.org 44
+ rcall isr ; Timer/Counter0 Compare Match B
+.org 46
+ rcall isr ; Timer/Counter0 Overflow
+.org 48
+ rcall isr ; SPI Serial Transfer Complete
+.org 50
+ rcall isr ; USART1, Rx Complete
+.org 52
+ rcall isr ; USART1 Data register Empty
+.org 54
+ rcall isr ; USART1, Tx Complete
+.org 56
+ rcall isr ; Analog Comparator
+.org 58
+ rcall isr ; ADC Conversion Complete
+.org 60
+ rcall isr ; EEPROM Ready
+.org 62
+ rcall isr ; Timer/Counter3 Capture Event
+.org 64
+ rcall isr ; Timer/Counter3 Compare Match A
+.org 66
+ rcall isr ; Timer/Counter3 Compare Match B
+.org 68
+ rcall isr ; Timer/Counter3 Compare Match C
+.org 70
+ rcall isr ; Timer/Counter3 Overflow
+.org 72
+ rcall isr ; 2-wire Serial Interface
+.org 74
+ rcall isr ; Store Program Memory Read
+.equ INTVECTORS = 38
+.nooverlap
+
+; compatability layer (maybe empty)
+
+; controller data area, environment query mcu-info
+mcu_info:
+mcu_ramsize:
+ .dw 8192
+mcu_eepromsize:
+ .dw 4096
+mcu_maxdp:
+ .dw 65535
+mcu_numints:
+ .dw 38
+mcu_name:
+ .dw 11
+ .db "AT90USB1286",0
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/at90usb1286/device.inc b/amforth-6.5/avr8/devices/at90usb1286/device.inc
new file mode 100644
index 0000000..dd2e63c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90usb1286/device.inc
@@ -0,0 +1,1611 @@
+; Partname: AT90USB1286
+; generated automatically, no not edit
+
+.if WANT_WATCHDOG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCSR:
+ .dw $ff06
+ .db "WDTCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCSR
+XT_WDTCSR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCSR:
+ .dw 96
+
+.endif
+.if WANT_PORTA == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Register
+VE_PORTA:
+ .dw $ff05
+ .db "PORTA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTA
+XT_PORTA:
+ .dw PFA_DOVARIABLE
+PFA_PORTA:
+ .dw 34
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Direction Register
+VE_DDRA:
+ .dw $ff04
+ .db "DDRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRA
+XT_DDRA:
+ .dw PFA_DOVARIABLE
+PFA_DDRA:
+ .dw 33
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Input Pins
+VE_PINA:
+ .dw $ff04
+ .db "PINA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINA
+XT_PINA:
+ .dw PFA_DOVARIABLE
+PFA_PINA:
+ .dw 32
+
+.endif
+.if WANT_PORTB == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw 37
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw 36
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw 35
+
+.endif
+.if WANT_PORTC == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Register
+VE_PORTC:
+ .dw $ff05
+ .db "PORTC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTC
+XT_PORTC:
+ .dw PFA_DOVARIABLE
+PFA_PORTC:
+ .dw 40
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Direction Register
+VE_DDRC:
+ .dw $ff04
+ .db "DDRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRC
+XT_DDRC:
+ .dw PFA_DOVARIABLE
+PFA_DDRC:
+ .dw 39
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Input Pins
+VE_PINC:
+ .dw $ff04
+ .db "PINC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINC
+XT_PINC:
+ .dw PFA_DOVARIABLE
+PFA_PINC:
+ .dw 38
+
+.endif
+.if WANT_PORTD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw 43
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw 42
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw 41
+
+.endif
+.if WANT_PORTE == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port E
+VE_PORTE:
+ .dw $ff05
+ .db "PORTE",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTE
+XT_PORTE:
+ .dw PFA_DOVARIABLE
+PFA_PORTE:
+ .dw 46
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port E
+VE_DDRE:
+ .dw $ff04
+ .db "DDRE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRE
+XT_DDRE:
+ .dw PFA_DOVARIABLE
+PFA_DDRE:
+ .dw 45
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port E
+VE_PINE:
+ .dw $ff04
+ .db "PINE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINE
+XT_PINE:
+ .dw PFA_DOVARIABLE
+PFA_PINE:
+ .dw 44
+
+.endif
+.if WANT_PORTF == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port F
+VE_PORTF:
+ .dw $ff05
+ .db "PORTF",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTF
+XT_PORTF:
+ .dw PFA_DOVARIABLE
+PFA_PORTF:
+ .dw 49
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port F
+VE_DDRF:
+ .dw $ff04
+ .db "DDRF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRF
+XT_DDRF:
+ .dw PFA_DOVARIABLE
+PFA_DDRF:
+ .dw 48
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port F
+VE_PINF:
+ .dw $ff04
+ .db "PINF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINF
+XT_PINF:
+ .dw PFA_DOVARIABLE
+PFA_PINF:
+ .dw 47
+
+.endif
+.if WANT_CPU == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw 95
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer
+VE_SP:
+ .dw $ff02
+ .db "SP"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SP
+XT_SP:
+ .dw PFA_DOVARIABLE
+PFA_SP:
+ .dw 93
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw 85
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Status Register
+VE_MCUSR:
+ .dw $ff05
+ .db "MCUSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUSR
+XT_MCUSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUSR:
+ .dw 84
+; ( -- addr ) System Constant
+; R( -- )
+; External Memory Control Register A
+VE_XMCRA:
+ .dw $ff05
+ .db "XMCRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_XMCRA
+XT_XMCRA:
+ .dw PFA_DOVARIABLE
+PFA_XMCRA:
+ .dw 116
+; ( -- addr ) System Constant
+; R( -- )
+; External Memory Control Register B
+VE_XMCRB:
+ .dw $ff05
+ .db "XMCRB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_XMCRB
+XT_XMCRB:
+ .dw PFA_DOVARIABLE
+PFA_XMCRB:
+ .dw 117
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Calibration Value
+VE_OSCCAL:
+ .dw $ff06
+ .db "OSCCAL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSCCAL
+XT_OSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_OSCCAL:
+ .dw 102
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_CLKPR:
+ .dw $ff05
+ .db "CLKPR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKPR
+XT_CLKPR:
+ .dw PFA_DOVARIABLE
+PFA_CLKPR:
+ .dw 97
+; ( -- addr ) System Constant
+; R( -- )
+; Sleep Mode Control Register
+VE_SMCR:
+ .dw $ff04
+ .db "SMCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SMCR
+XT_SMCR:
+ .dw PFA_DOVARIABLE
+PFA_SMCR:
+ .dw 83
+; ( -- addr ) System Constant
+; R( -- )
+; Extended Indirect Register
+VE_EIND:
+ .dw $ff04
+ .db "EIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIND
+XT_EIND:
+ .dw PFA_DOVARIABLE
+PFA_EIND:
+ .dw 92
+; ( -- addr ) System Constant
+; R( -- )
+; RAM Page Z Select Register
+VE_RAMPZ:
+ .dw $ff05
+ .db "RAMPZ",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_RAMPZ
+XT_RAMPZ:
+ .dw PFA_DOVARIABLE
+PFA_RAMPZ:
+ .dw 91
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 2
+VE_GPIOR2:
+ .dw $ff06
+ .db "GPIOR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR2
+XT_GPIOR2:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR2:
+ .dw 75
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 1
+VE_GPIOR1:
+ .dw $ff06
+ .db "GPIOR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR1
+XT_GPIOR1:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR1:
+ .dw 74
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 0
+VE_GPIOR0:
+ .dw $ff06
+ .db "GPIOR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR0
+XT_GPIOR0:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR0:
+ .dw 62
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register1
+VE_PRR1:
+ .dw $ff04
+ .db "PRR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR1
+XT_PRR1:
+ .dw PFA_DOVARIABLE
+PFA_PRR1:
+ .dw 101
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register0
+VE_PRR0:
+ .dw $ff04
+ .db "PRR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR0
+XT_PRR0:
+ .dw PFA_DOVARIABLE
+PFA_PRR0:
+ .dw 100
+
+.endif
+.if WANT_TWI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; TWI (Slave) Address Mask Register
+VE_TWAMR:
+ .dw $ff05
+ .db "TWAMR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWAMR
+XT_TWAMR:
+ .dw PFA_DOVARIABLE
+PFA_TWAMR:
+ .dw 189
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Bit Rate register
+VE_TWBR:
+ .dw $ff04
+ .db "TWBR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWBR
+XT_TWBR:
+ .dw PFA_DOVARIABLE
+PFA_TWBR:
+ .dw 184
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Control Register
+VE_TWCR:
+ .dw $ff04
+ .db "TWCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWCR
+XT_TWCR:
+ .dw PFA_DOVARIABLE
+PFA_TWCR:
+ .dw 188
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Status Register
+VE_TWSR:
+ .dw $ff04
+ .db "TWSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWSR
+XT_TWSR:
+ .dw PFA_DOVARIABLE
+PFA_TWSR:
+ .dw 185
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Data register
+VE_TWDR:
+ .dw $ff04
+ .db "TWDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWDR
+XT_TWDR:
+ .dw PFA_DOVARIABLE
+PFA_TWDR:
+ .dw 187
+; ( -- addr ) System Constant
+; R( -- )
+; TWI (Slave) Address register
+VE_TWAR:
+ .dw $ff04
+ .db "TWAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWAR
+XT_TWAR:
+ .dw PFA_DOVARIABLE
+PFA_TWAR:
+ .dw 186
+
+.endif
+.if WANT_SPI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR:
+ .dw $ff04
+ .db "SPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR
+XT_SPCR:
+ .dw PFA_DOVARIABLE
+PFA_SPCR:
+ .dw 76
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR:
+ .dw $ff04
+ .db "SPSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR
+XT_SPSR:
+ .dw PFA_DOVARIABLE
+PFA_SPSR:
+ .dw 77
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR:
+ .dw $ff04
+ .db "SPDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR
+XT_SPDR:
+ .dw PFA_DOVARIABLE
+PFA_SPDR:
+ .dw 78
+
+.endif
+.if WANT_USART1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR1:
+ .dw $ff04
+ .db "UDR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR1
+XT_UDR1:
+ .dw PFA_DOVARIABLE
+PFA_UDR1:
+ .dw 206
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR1A:
+ .dw $ff06
+ .db "UCSR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1A
+XT_UCSR1A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1A:
+ .dw 200
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR1B:
+ .dw $ff06
+ .db "UCSR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1B
+XT_UCSR1B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1B:
+ .dw 201
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR1C:
+ .dw $ff06
+ .db "UCSR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1C
+XT_UCSR1C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1C:
+ .dw 202
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Bytes
+VE_UBRR1:
+ .dw $ff05
+ .db "UBRR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR1
+XT_UBRR1:
+ .dw PFA_DOVARIABLE
+PFA_UBRR1:
+ .dw 204
+
+.endif
+.if WANT_USB_DEVICE == 1
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UEINT:
+ .dw $ff05
+ .db "UEINT",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UEINT
+XT_UEINT:
+ .dw PFA_DOVARIABLE
+PFA_UEINT:
+ .dw 244
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UEBCHX:
+ .dw $ff06
+ .db "UEBCHX"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UEBCHX
+XT_UEBCHX:
+ .dw PFA_DOVARIABLE
+PFA_UEBCHX:
+ .dw 243
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UEBCLX:
+ .dw $ff06
+ .db "UEBCLX"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UEBCLX
+XT_UEBCLX:
+ .dw PFA_DOVARIABLE
+PFA_UEBCLX:
+ .dw 242
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UEDATX:
+ .dw $ff06
+ .db "UEDATX"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UEDATX
+XT_UEDATX:
+ .dw PFA_DOVARIABLE
+PFA_UEDATX:
+ .dw 241
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UEIENX:
+ .dw $ff06
+ .db "UEIENX"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UEIENX
+XT_UEIENX:
+ .dw PFA_DOVARIABLE
+PFA_UEIENX:
+ .dw 240
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UESTA1X:
+ .dw $ff07
+ .db "UESTA1X",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UESTA1X
+XT_UESTA1X:
+ .dw PFA_DOVARIABLE
+PFA_UESTA1X:
+ .dw 239
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UESTA0X:
+ .dw $ff07
+ .db "UESTA0X",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UESTA0X
+XT_UESTA0X:
+ .dw PFA_DOVARIABLE
+PFA_UESTA0X:
+ .dw 238
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UECFG1X:
+ .dw $ff07
+ .db "UECFG1X",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UECFG1X
+XT_UECFG1X:
+ .dw PFA_DOVARIABLE
+PFA_UECFG1X:
+ .dw 237
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UECFG0X:
+ .dw $ff07
+ .db "UECFG0X",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UECFG0X
+XT_UECFG0X:
+ .dw PFA_DOVARIABLE
+PFA_UECFG0X:
+ .dw 236
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UECONX:
+ .dw $ff06
+ .db "UECONX"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UECONX
+XT_UECONX:
+ .dw PFA_DOVARIABLE
+PFA_UECONX:
+ .dw 235
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UERST:
+ .dw $ff05
+ .db "UERST",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UERST
+XT_UERST:
+ .dw PFA_DOVARIABLE
+PFA_UERST:
+ .dw 234
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UENUM:
+ .dw $ff05
+ .db "UENUM",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UENUM
+XT_UENUM:
+ .dw PFA_DOVARIABLE
+PFA_UENUM:
+ .dw 233
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UEINTX:
+ .dw $ff06
+ .db "UEINTX"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UEINTX
+XT_UEINTX:
+ .dw PFA_DOVARIABLE
+PFA_UEINTX:
+ .dw 232
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UDMFN:
+ .dw $ff05
+ .db "UDMFN",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDMFN
+XT_UDMFN:
+ .dw PFA_DOVARIABLE
+PFA_UDMFN:
+ .dw 230
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UDFNUM:
+ .dw $ff06
+ .db "UDFNUM"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDFNUM
+XT_UDFNUM:
+ .dw PFA_DOVARIABLE
+PFA_UDFNUM:
+ .dw 228
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UDADDR:
+ .dw $ff06
+ .db "UDADDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDADDR
+XT_UDADDR:
+ .dw PFA_DOVARIABLE
+PFA_UDADDR:
+ .dw 227
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UDIEN:
+ .dw $ff05
+ .db "UDIEN",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDIEN
+XT_UDIEN:
+ .dw PFA_DOVARIABLE
+PFA_UDIEN:
+ .dw 226
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UDINT:
+ .dw $ff05
+ .db "UDINT",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDINT
+XT_UDINT:
+ .dw PFA_DOVARIABLE
+PFA_UDINT:
+ .dw 225
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UDCON:
+ .dw $ff05
+ .db "UDCON",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDCON
+XT_UDCON:
+ .dw PFA_DOVARIABLE
+PFA_UDCON:
+ .dw 224
+
+.endif
+.if WANT_BOOT_LOAD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control Register
+VE_SPMCSR:
+ .dw $ff06
+ .db "SPMCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCSR
+XT_SPMCSR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCSR:
+ .dw 87
+
+.endif
+.if WANT_EEPROM == 1
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Address Register Low Bytes
+VE_EEAR:
+ .dw $ff04
+ .db "EEAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEAR
+XT_EEAR:
+ .dw PFA_DOVARIABLE
+PFA_EEAR:
+ .dw 65
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw 64
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw 63
+
+.endif
+.if WANT_TIMER_COUNTER_0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0B:
+ .dw $ff05
+ .db "OCR0B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0B
+XT_OCR0B:
+ .dw PFA_DOVARIABLE
+PFA_OCR0B:
+ .dw 72
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0A:
+ .dw $ff05
+ .db "OCR0A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0A
+XT_OCR0A:
+ .dw PFA_DOVARIABLE
+PFA_OCR0A:
+ .dw 71
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw 70
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register B
+VE_TCCR0B:
+ .dw $ff06
+ .db "TCCR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0B
+XT_TCCR0B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0B:
+ .dw 69
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register A
+VE_TCCR0A:
+ .dw $ff06
+ .db "TCCR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0A
+XT_TCCR0A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0A:
+ .dw 68
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Mask Register
+VE_TIMSK0:
+ .dw $ff06
+ .db "TIMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK0
+XT_TIMSK0:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK0:
+ .dw 110
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Flag register
+VE_TIFR0:
+ .dw $ff05
+ .db "TIFR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR0
+XT_TIFR0:
+ .dw PFA_DOVARIABLE
+PFA_TIFR0:
+ .dw 53
+; ( -- addr ) System Constant
+; R( -- )
+; General Timer/Counter Control Register
+VE_GTCCR:
+ .dw $ff05
+ .db "GTCCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GTCCR
+XT_GTCCR:
+ .dw PFA_DOVARIABLE
+PFA_GTCCR:
+ .dw 67
+
+.endif
+.if WANT_TIMER_COUNTER_2 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Mask register
+VE_TIMSK2:
+ .dw $ff06
+ .db "TIMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK2
+XT_TIMSK2:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK2:
+ .dw 112
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Flag Register
+VE_TIFR2:
+ .dw $ff05
+ .db "TIFR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR2
+XT_TIFR2:
+ .dw PFA_DOVARIABLE
+PFA_TIFR2:
+ .dw 55
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register A
+VE_TCCR2A:
+ .dw $ff06
+ .db "TCCR2A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2A
+XT_TCCR2A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2A:
+ .dw 176
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register B
+VE_TCCR2B:
+ .dw $ff06
+ .db "TCCR2B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2B
+XT_TCCR2B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2B:
+ .dw 177
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2
+VE_TCNT2:
+ .dw $ff05
+ .db "TCNT2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT2
+XT_TCNT2:
+ .dw PFA_DOVARIABLE
+PFA_TCNT2:
+ .dw 178
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register B
+VE_OCR2B:
+ .dw $ff05
+ .db "OCR2B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2B
+XT_OCR2B:
+ .dw PFA_DOVARIABLE
+PFA_OCR2B:
+ .dw 180
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register A
+VE_OCR2A:
+ .dw $ff05
+ .db "OCR2A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2A
+XT_OCR2A:
+ .dw PFA_DOVARIABLE
+PFA_OCR2A:
+ .dw 179
+; ( -- addr ) System Constant
+; R( -- )
+; Asynchronous Status Register
+VE_ASSR:
+ .dw $ff04
+ .db "ASSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ASSR
+XT_ASSR:
+ .dw PFA_DOVARIABLE
+PFA_ASSR:
+ .dw 182
+
+.endif
+.if WANT_TIMER_COUNTER_3 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Control Register A
+VE_TCCR3A:
+ .dw $ff06
+ .db "TCCR3A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR3A
+XT_TCCR3A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR3A:
+ .dw 144
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Control Register B
+VE_TCCR3B:
+ .dw $ff06
+ .db "TCCR3B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR3B
+XT_TCCR3B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR3B:
+ .dw 145
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter 3 Control Register C
+VE_TCCR3C:
+ .dw $ff06
+ .db "TCCR3C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR3C
+XT_TCCR3C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR3C:
+ .dw 146
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Bytes
+VE_TCNT3:
+ .dw $ff05
+ .db "TCNT3",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT3
+XT_TCNT3:
+ .dw PFA_DOVARIABLE
+PFA_TCNT3:
+ .dw 148
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Output Compare Register A Bytes
+VE_OCR3A:
+ .dw $ff05
+ .db "OCR3A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR3A
+XT_OCR3A:
+ .dw PFA_DOVARIABLE
+PFA_OCR3A:
+ .dw 152
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Output Compare Register B Bytes
+VE_OCR3B:
+ .dw $ff05
+ .db "OCR3B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR3B
+XT_OCR3B:
+ .dw PFA_DOVARIABLE
+PFA_OCR3B:
+ .dw 154
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Output Compare Register B Bytes
+VE_OCR3C:
+ .dw $ff05
+ .db "OCR3C",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR3C
+XT_OCR3C:
+ .dw PFA_DOVARIABLE
+PFA_OCR3C:
+ .dw 156
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Input Capture Register Bytes
+VE_ICR3:
+ .dw $ff04
+ .db "ICR3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR3
+XT_ICR3:
+ .dw PFA_DOVARIABLE
+PFA_ICR3:
+ .dw 150
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Interrupt Mask Register
+VE_TIMSK3:
+ .dw $ff06
+ .db "TIMSK3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK3
+XT_TIMSK3:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK3:
+ .dw 113
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Interrupt Flag register
+VE_TIFR3:
+ .dw $ff05
+ .db "TIFR3",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR3
+XT_TIFR3:
+ .dw PFA_DOVARIABLE
+PFA_TIFR3:
+ .dw 56
+
+.endif
+.if WANT_TIMER_COUNTER_1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw 128
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw 129
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter 1 Control Register C
+VE_TCCR1C:
+ .dw $ff06
+ .db "TCCR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1C
+XT_TCCR1C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1C:
+ .dw 130
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Bytes
+VE_TCNT1:
+ .dw $ff05
+ .db "TCNT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1
+XT_TCNT1:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1:
+ .dw 132
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register A Bytes
+VE_OCR1A:
+ .dw $ff05
+ .db "OCR1A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1A
+XT_OCR1A:
+ .dw PFA_DOVARIABLE
+PFA_OCR1A:
+ .dw 136
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register B Bytes
+VE_OCR1B:
+ .dw $ff05
+ .db "OCR1B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1B
+XT_OCR1B:
+ .dw PFA_DOVARIABLE
+PFA_OCR1B:
+ .dw 138
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register C Bytes
+VE_OCR1C:
+ .dw $ff05
+ .db "OCR1C",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1C
+XT_OCR1C:
+ .dw PFA_DOVARIABLE
+PFA_OCR1C:
+ .dw 140
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Bytes
+VE_ICR1:
+ .dw $ff04
+ .db "ICR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1
+XT_ICR1:
+ .dw PFA_DOVARIABLE
+PFA_ICR1:
+ .dw 134
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Mask Register
+VE_TIMSK1:
+ .dw $ff06
+ .db "TIMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK1
+XT_TIMSK1:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK1:
+ .dw 111
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Flag register
+VE_TIFR1:
+ .dw $ff05
+ .db "TIFR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR1
+XT_TIFR1:
+ .dw PFA_DOVARIABLE
+PFA_TIFR1:
+ .dw 54
+
+.endif
+.if WANT_JTAG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; On-Chip Debug Related Register in I/O Memory
+VE_OCDR:
+ .dw $ff04
+ .db "OCDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCDR
+XT_OCDR:
+ .dw PFA_DOVARIABLE
+PFA_OCDR:
+ .dw 81
+
+.endif
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register A
+VE_EICRA:
+ .dw $ff05
+ .db "EICRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRA
+XT_EICRA:
+ .dw PFA_DOVARIABLE
+PFA_EICRA:
+ .dw 105
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register B
+VE_EICRB:
+ .dw $ff05
+ .db "EICRB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRB
+XT_EICRB:
+ .dw PFA_DOVARIABLE
+PFA_EICRB:
+ .dw 106
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Mask Register
+VE_EIMSK:
+ .dw $ff05
+ .db "EIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIMSK
+XT_EIMSK:
+ .dw PFA_DOVARIABLE
+PFA_EIMSK:
+ .dw 61
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Flag Register
+VE_EIFR:
+ .dw $ff04
+ .db "EIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIFR
+XT_EIFR:
+ .dw PFA_DOVARIABLE
+PFA_EIFR:
+ .dw 60
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 0
+VE_PCMSK0:
+ .dw $ff06
+ .db "PCMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK0
+XT_PCMSK0:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK0:
+ .dw 107
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Interrupt Flag Register
+VE_PCIFR:
+ .dw $ff05
+ .db "PCIFR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCIFR
+XT_PCIFR:
+ .dw PFA_DOVARIABLE
+PFA_PCIFR:
+ .dw 59
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Interrupt Control Register
+VE_PCICR:
+ .dw $ff05
+ .db "PCICR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCICR
+XT_PCICR:
+ .dw PFA_DOVARIABLE
+PFA_PCICR:
+ .dw 104
+
+.endif
+.if WANT_AD_CONVERTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC multiplexer Selection Register
+VE_ADMUX:
+ .dw $ff05
+ .db "ADMUX",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADMUX
+XT_ADMUX:
+ .dw PFA_DOVARIABLE
+PFA_ADMUX:
+ .dw 124
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register
+VE_ADCSRA:
+ .dw $ff06
+ .db "ADCSRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRA
+XT_ADCSRA:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRA:
+ .dw 122
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register Bytes
+VE_ADC:
+ .dw $ff03
+ .db "ADC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADC
+XT_ADC:
+ .dw PFA_DOVARIABLE
+PFA_ADC:
+ .dw 120
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Control and Status Register B
+VE_ADCSRB:
+ .dw $ff06
+ .db "ADCSRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRB
+XT_ADCSRB:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRB:
+ .dw 123
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 1
+VE_DIDR0:
+ .dw $ff05
+ .db "DIDR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR0
+XT_DIDR0:
+ .dw PFA_DOVARIABLE
+PFA_DIDR0:
+ .dw 126
+
+.endif
+.if WANT_ANALOG_COMPARATOR == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Control And Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw 80
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_DIDR1:
+ .dw $ff05
+ .db "DIDR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR1
+XT_DIDR1:
+ .dw PFA_DOVARIABLE
+PFA_DIDR1:
+ .dw 127
+
+.endif
+.if WANT_PLL == 1
+; ( -- addr ) System Constant
+; R( -- )
+; PLL Status and Control register
+VE_PLLCSR:
+ .dw $ff06
+ .db "PLLCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PLLCSR
+XT_PLLCSR:
+ .dw PFA_DOVARIABLE
+PFA_PLLCSR:
+ .dw 73
+
+.endif
+.if WANT_USB_GLOBAL == 1
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_USBINT:
+ .dw $ff06
+ .db "USBINT"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USBINT
+XT_USBINT:
+ .dw PFA_DOVARIABLE
+PFA_USBINT:
+ .dw 218
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_USBSTA:
+ .dw $ff06
+ .db "USBSTA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USBSTA
+XT_USBSTA:
+ .dw PFA_DOVARIABLE
+PFA_USBSTA:
+ .dw 217
+; ( -- addr ) System Constant
+; R( -- )
+; USB General Control Register
+VE_USBCON:
+ .dw $ff06
+ .db "USBCON"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USBCON
+XT_USBCON:
+ .dw PFA_DOVARIABLE
+PFA_USBCON:
+ .dw 216
+; ( -- addr ) System Constant
+; R( -- )
+; USB Hardware Configuration Register
+VE_UHWCON:
+ .dw $ff06
+ .db "UHWCON"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UHWCON
+XT_UHWCON:
+ .dw PFA_DOVARIABLE
+PFA_UHWCON:
+ .dw 215
+
+.endif
diff --git a/amforth-6.5/avr8/devices/at90usb1286/device.py b/amforth-6.5/avr8/devices/at90usb1286/device.py
new file mode 100644
index 0000000..48ce421
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90usb1286/device.py
@@ -0,0 +1,523 @@
+# Generated Automatically
+
+# Partname AT90USB1286
+
+MCUREGS = {
+# Interrupt Vectors
+ 'INT0Addr' : '#2', # External Interrupt Request 0
+ 'INT1Addr' : '#4', # External Interrupt Request 1
+ 'INT2Addr' : '#6', # External Interrupt Request 2
+ 'INT3Addr' : '#8', # External Interrupt Request 3
+ 'INT4Addr' : '#10', # External Interrupt Request 4
+ 'INT5Addr' : '#12', # External Interrupt Request 5
+ 'INT6Addr' : '#14', # External Interrupt Request 6
+ 'INT7Addr' : '#16', # External Interrupt Request 7
+ 'PCINT0Addr' : '#18', # Pin Change Interrupt Request 0
+ 'USB_GENAddr' : '#20', # USB General Interrupt Request
+ 'USB_COMAddr' : '#22', # USB Endpoint/Pipe Interrupt Communication Request
+ 'WDTAddr' : '#24', # Watchdog Time-out Interrupt
+ 'TIMER2_COMPAAddr' : '#26', # Timer/Counter2 Compare Match A
+ 'TIMER2_COMPBAddr' : '#28', # Timer/Counter2 Compare Match B
+ 'TIMER2_OVFAddr' : '#30', # Timer/Counter2 Overflow
+ 'TIMER1_CAPTAddr' : '#32', # Timer/Counter1 Capture Event
+ 'TIMER1_COMPAAddr' : '#34', # Timer/Counter1 Compare Match A
+ 'TIMER1_COMPBAddr' : '#36', # Timer/Counter1 Compare Match B
+ 'TIMER1_COMPCAddr' : '#38', # Timer/Counter1 Compare Match C
+ 'TIMER1_OVFAddr' : '#40', # Timer/Counter1 Overflow
+ 'TIMER0_COMPAAddr' : '#42', # Timer/Counter0 Compare Match A
+ 'TIMER0_COMPBAddr' : '#44', # Timer/Counter0 Compare Match B
+ 'TIMER0_OVFAddr' : '#46', # Timer/Counter0 Overflow
+ 'SPI_STCAddr' : '#48', # SPI Serial Transfer Complete
+ 'USART1_RXAddr' : '#50', # USART1, Rx Complete
+ 'USART1_UDREAddr' : '#52', # USART1 Data register Empty
+ 'USART1_TXAddr' : '#54', # USART1, Tx Complete
+ 'ANALOG_COMPAddr' : '#56', # Analog Comparator
+ 'ADCAddr' : '#58', # ADC Conversion Complete
+ 'EE_READYAddr' : '#60', # EEPROM Ready
+ 'TIMER3_CAPTAddr' : '#62', # Timer/Counter3 Capture Event
+ 'TIMER3_COMPAAddr' : '#64', # Timer/Counter3 Compare Match A
+ 'TIMER3_COMPBAddr' : '#66', # Timer/Counter3 Compare Match B
+ 'TIMER3_COMPCAddr' : '#68', # Timer/Counter3 Compare Match C
+ 'TIMER3_OVFAddr' : '#70', # Timer/Counter3 Overflow
+ 'TWIAddr' : '#72', # 2-wire Serial Interface
+ 'SPM_READYAddr' : '#74', # Store Program Memory Read
+
+# Module WATCHDOG
+ 'WDTCSR' : '$60', # Watchdog Timer Control Registe
+ 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
+ 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
+ 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
+ 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
+ 'WDTCSR_WDE': '$8', # Watch Dog Enable
+
+# Module PORTA
+ 'PORTA' : '$22', # Port A Data Register
+ 'DDRA' : '$21', # Port A Data Direction Register
+ 'PINA' : '$20', # Port A Input Pins
+
+# Module PORTB
+ 'PORTB' : '$25', # Port B Data Register
+ 'DDRB' : '$24', # Port B Data Direction Register
+ 'PINB' : '$23', # Port B Input Pins
+
+# Module PORTC
+ 'PORTC' : '$28', # Port C Data Register
+ 'DDRC' : '$27', # Port C Data Direction Register
+ 'PINC' : '$26', # Port C Input Pins
+
+# Module PORTD
+ 'PORTD' : '$2b', # Port D Data Register
+ 'DDRD' : '$2a', # Port D Data Direction Register
+ 'PIND' : '$29', # Port D Input Pins
+
+# Module PORTE
+ 'PORTE' : '$2e', # Data Register, Port E
+ 'DDRE' : '$2d', # Data Direction Register, Port
+ 'PINE' : '$2c', # Input Pins, Port E
+
+# Module PORTF
+ 'PORTF' : '$31', # Data Register, Port F
+ 'DDRF' : '$30', # Data Direction Register, Port
+ 'PINF' : '$2f', # Input Pins, Port F
+
+# Module CPU
+ 'SREG' : '$5f', # Status Register
+ 'SREG_I': '$80', # Global Interrupt Enable
+ 'SREG_T': '$40', # Bit Copy Storage
+ 'SREG_H': '$20', # Half Carry Flag
+ 'SREG_S': '$10', # Sign Bit
+ 'SREG_V': '$8', # Two's Complement Overflow Flag
+ 'SREG_N': '$4', # Negative Flag
+ 'SREG_Z': '$2', # Zero Flag
+ 'SREG_C': '$1', # Carry Flag
+ 'SP' : '$5d', # Stack Pointer
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_JTD': '$80', # JTAG Interface Disable
+ 'MCUCR_PUD': '$10', # Pull-up disable
+ 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
+ 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+ 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
+ 'MCUSR_BORF': '$4', # Brown-out Reset Flag
+ 'MCUSR_EXTRF': '$2', # External Reset Flag
+ 'MCUSR_PORF': '$1', # Power-on reset flag
+ 'XMCRA' : '$74', # External Memory Control Regist
+ 'XMCRA_SRE': '$80', # External SRAM Enable
+ 'XMCRA_SRL': '$70', # Wait state page limit
+ 'XMCRA_SRW1': '$c', # Wait state select bit upper pa
+ 'XMCRA_SRW0': '$3', # Wait state select bit lower pa
+ 'XMCRB' : '$75', # External Memory Control Regist
+ 'XMCRB_XMBK': '$80', # External Memory Bus Keeper Ena
+ 'XMCRB_XMM': '$7', # External Memory High Mask
+ 'OSCCAL' : '$66', # Oscillator Calibration Value
+ 'CLKPR' : '$61', #
+ 'CLKPR_CLKPCE': '$80', #
+ 'CLKPR_CLKPS': '$f', #
+ 'SMCR' : '$53', # Sleep Mode Control Register
+ 'SMCR_SM': '$e', # Sleep Mode Select bits
+ 'SMCR_SE': '$1', # Sleep Enable
+ 'EIND' : '$5c', # Extended Indirect Register
+ 'RAMPZ' : '$5b', # RAM Page Z Select Register
+ 'GPIOR2' : '$4b', # General Purpose IO Register 2
+ 'GPIOR2_GPIOR': '$ff', # General Purpose IO Register 2
+ 'GPIOR1' : '$4a', # General Purpose IO Register 1
+ 'GPIOR1_GPIOR': '$ff', # General Purpose IO Register 1
+ 'GPIOR0' : '$3e', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR07': '$80', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR06': '$40', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR05': '$20', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR04': '$10', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR03': '$8', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR02': '$4', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR01': '$2', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR00': '$1', # General Purpose IO Register 0
+ 'PRR1' : '$65', # Power Reduction Register1
+ 'PRR1_PRUSB': '$80', # Power Reduction USB
+ 'PRR1_PRTIM3': '$8', # Power Reduction Timer/Counter3
+ 'PRR1_PRUSART1': '$1', # Power Reduction USART1
+ 'PRR0' : '$64', # Power Reduction Register0
+ 'PRR0_PRTWI': '$80', # Power Reduction TWI
+ 'PRR0_PRTIM2': '$40', # Power Reduction Timer/Counter2
+ 'PRR0_PRTIM0': '$20', # Power Reduction Timer/Counter0
+ 'PRR0_PRTIM1': '$8', # Power Reduction Timer/Counter1
+ 'PRR0_PRSPI': '$4', # Power Reduction Serial Periphe
+ 'PRR0_PRADC': '$1', # Power Reduction ADC
+
+# Module TWI
+ 'TWAMR' : '$bd', # TWI (Slave) Address Mask Regis
+ 'TWAMR_TWAM': '$fe', #
+ 'TWBR' : '$b8', # TWI Bit Rate register
+ 'TWCR' : '$bc', # TWI Control Register
+ 'TWCR_TWINT': '$80', # TWI Interrupt Flag
+ 'TWCR_TWEA': '$40', # TWI Enable Acknowledge Bit
+ 'TWCR_TWSTA': '$20', # TWI Start Condition Bit
+ 'TWCR_TWSTO': '$10', # TWI Stop Condition Bit
+ 'TWCR_TWWC': '$8', # TWI Write Collition Flag
+ 'TWCR_TWEN': '$4', # TWI Enable Bit
+ 'TWCR_TWIE': '$1', # TWI Interrupt Enable
+ 'TWSR' : '$b9', # TWI Status Register
+ 'TWSR_TWS': '$f8', # TWI Status
+ 'TWSR_TWPS': '$3', # TWI Prescaler
+ 'TWDR' : '$bb', # TWI Data register
+ 'TWAR' : '$ba', # TWI (Slave) Address register
+ 'TWAR_TWA': '$fe', # TWI (Slave) Address register B
+ 'TWAR_TWGCE': '$1', # TWI General Call Recognition E
+
+# Module SPI
+ 'SPCR' : '$4c', # SPI Control Register
+ 'SPCR_SPIE': '$80', # SPI Interrupt Enable
+ 'SPCR_SPE': '$40', # SPI Enable
+ 'SPCR_DORD': '$20', # Data Order
+ 'SPCR_MSTR': '$10', # Master/Slave Select
+ 'SPCR_CPOL': '$8', # Clock polarity
+ 'SPCR_CPHA': '$4', # Clock Phase
+ 'SPCR_SPR': '$3', # SPI Clock Rate Selects
+ 'SPSR' : '$4d', # SPI Status Register
+ 'SPSR_SPIF': '$80', # SPI Interrupt Flag
+ 'SPSR_WCOL': '$40', # Write Collision Flag
+ 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
+ 'SPDR' : '$4e', # SPI Data Register
+
+# Module USART1
+ 'UDR1' : '$ce', # USART I/O Data Register
+ 'UCSR1A' : '$c8', # USART Control and Status Regis
+ 'UCSR1A_RXC1': '$80', # USART Receive Complete
+ 'UCSR1A_TXC1': '$40', # USART Transmitt Complete
+ 'UCSR1A_UDRE1': '$20', # USART Data Register Empty
+ 'UCSR1A_FE1': '$10', # Framing Error
+ 'UCSR1A_DOR1': '$8', # Data overRun
+ 'UCSR1A_UPE1': '$4', # Parity Error
+ 'UCSR1A_U2X1': '$2', # Double the USART transmission
+ 'UCSR1A_MPCM1': '$1', # Multi-processor Communication
+ 'UCSR1B' : '$c9', # USART Control and Status Regis
+ 'UCSR1B_RXCIE1': '$80', # RX Complete Interrupt Enable
+ 'UCSR1B_TXCIE1': '$40', # TX Complete Interrupt Enable
+ 'UCSR1B_UDRIE1': '$20', # USART Data register Empty Inte
+ 'UCSR1B_RXEN1': '$10', # Receiver Enable
+ 'UCSR1B_TXEN1': '$8', # Transmitter Enable
+ 'UCSR1B_UCSZ12': '$4', # Character Size
+ 'UCSR1B_RXB81': '$2', # Receive Data Bit 8
+ 'UCSR1B_TXB81': '$1', # Transmit Data Bit 8
+ 'UCSR1C' : '$ca', # USART Control and Status Regis
+ 'UCSR1C_UMSEL1': '$c0', # USART Mode Select
+ 'UCSR1C_UPM1': '$30', # Parity Mode Bits
+ 'UCSR1C_USBS1': '$8', # Stop Bit Select
+ 'UCSR1C_UCSZ1': '$6', # Character Size
+ 'UCSR1C_UCPOL1': '$1', # Clock Polarity
+ 'UBRR1' : '$cc', # USART Baud Rate Register Byte
+
+# Module USB_DEVICE
+ 'UEINT' : '$f4', #
+ 'UEBCHX' : '$f3', #
+ 'UEBCLX' : '$f2', #
+ 'UEDATX' : '$f1', #
+ 'UEIENX' : '$f0', #
+ 'UEIENX_FLERRE': '$80', #
+ 'UEIENX_NAKINE': '$40', #
+ 'UEIENX_NAKOUTE': '$10', #
+ 'UEIENX_RXSTPE': '$8', #
+ 'UEIENX_RXOUTE': '$4', #
+ 'UEIENX_STALLEDE': '$2', #
+ 'UEIENX_TXINE': '$1', #
+ 'UESTA1X' : '$ef', #
+ 'UESTA1X_CTRLDIR': '$4', #
+ 'UESTA1X_CURRBK': '$3', #
+ 'UESTA0X' : '$ee', #
+ 'UESTA0X_CFGOK': '$80', #
+ 'UESTA0X_OVERFI': '$40', #
+ 'UESTA0X_UNDERFI': '$20', #
+ 'UESTA0X_DTSEQ': '$c', #
+ 'UESTA0X_NBUSYBK': '$3', #
+ 'UECFG1X' : '$ed', #
+ 'UECFG1X_EPSIZE': '$70', #
+ 'UECFG1X_EPBK': '$c', #
+ 'UECFG1X_ALLOC': '$2', #
+ 'UECFG0X' : '$ec', #
+ 'UECFG0X_EPTYPE': '$c0', #
+ 'UECFG0X_EPDIR': '$1', #
+ 'UECONX' : '$eb', #
+ 'UECONX_STALLRQ': '$20', #
+ 'UECONX_STALLRQC': '$10', #
+ 'UECONX_RSTDT': '$8', #
+ 'UECONX_EPEN': '$1', #
+ 'UERST' : '$ea', #
+ 'UERST_EPRST': '$7f', #
+ 'UENUM' : '$e9', #
+ 'UEINTX' : '$e8', #
+ 'UEINTX_FIFOCON': '$80', #
+ 'UEINTX_NAKINI': '$40', #
+ 'UEINTX_RWAL': '$20', #
+ 'UEINTX_NAKOUTI': '$10', #
+ 'UEINTX_RXSTPI': '$8', #
+ 'UEINTX_RXOUTI': '$4', #
+ 'UEINTX_STALLEDI': '$2', #
+ 'UEINTX_TXINI': '$1', #
+ 'UDMFN' : '$e6', #
+ 'UDMFN_FNCERR': '$10', #
+ 'UDFNUM' : '$e4', #
+ 'UDADDR' : '$e3', #
+ 'UDADDR_ADDEN': '$80', #
+ 'UDADDR_UADD': '$7f', #
+ 'UDIEN' : '$e2', #
+ 'UDIEN_UPRSME': '$40', #
+ 'UDIEN_EORSME': '$20', #
+ 'UDIEN_WAKEUPE': '$10', #
+ 'UDIEN_EORSTE': '$8', #
+ 'UDIEN_SOFE': '$4', #
+ 'UDIEN_SUSPE': '$1', #
+ 'UDINT' : '$e1', #
+ 'UDINT_UPRSMI': '$40', #
+ 'UDINT_EORSMI': '$20', #
+ 'UDINT_WAKEUPI': '$10', #
+ 'UDINT_EORSTI': '$8', #
+ 'UDINT_SOFI': '$4', #
+ 'UDINT_SUSPI': '$1', #
+ 'UDCON' : '$e0', #
+ 'UDCON_LSM': '$4', #
+ 'UDCON_RMWKUP': '$2', #
+ 'UDCON_DETACH': '$1', #
+
+# Module BOOT_LOAD
+ 'SPMCSR' : '$57', # Store Program Memory Control R
+ 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
+ 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
+ 'SPMCSR_SIGRD': '$20', # Signature Row Read
+ 'SPMCSR_RWWSRE': '$10', # Read While Write section read
+ 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
+ 'SPMCSR_PGWRT': '$4', # Page Write
+ 'SPMCSR_PGERS': '$2', # Page Erase
+ 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
+
+# Module EEPROM
+ 'EEAR' : '$41', # EEPROM Address Register Low By
+ 'EEDR' : '$40', # EEPROM Data Register
+ 'EECR' : '$3f', # EEPROM Control Register
+ 'EECR_EEPM': '$30', # EEPROM Programming Mode Bits
+ 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
+ 'EECR_EEMPE': '$4', # EEPROM Master Write Enable
+ 'EECR_EEPE': '$2', # EEPROM Write Enable
+ 'EECR_EERE': '$1', # EEPROM Read Enable
+
+# Module TIMER_COUNTER_0
+ 'OCR0B' : '$48', # Timer/Counter0 Output Compare
+ 'OCR0A' : '$47', # Timer/Counter0 Output Compare
+ 'TCNT0' : '$46', # Timer/Counter0
+ 'TCCR0B' : '$45', # Timer/Counter Control Register
+ 'TCCR0B_FOC0A': '$80', # Force Output Compare A
+ 'TCCR0B_FOC0B': '$40', # Force Output Compare B
+ 'TCCR0B_WGM02': '$8', #
+ 'TCCR0B_CS0': '$7', # Clock Select
+ 'TCCR0A' : '$44', # Timer/Counter Control Registe
+ 'TCCR0A_COM0A': '$c0', # Compare Output Mode, Phase Cor
+ 'TCCR0A_COM0B': '$30', # Compare Output Mode, Fast PWm
+ 'TCCR0A_WGM0': '$3', # Waveform Generation Mode
+ 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
+ 'TIMSK0_OCIE0B': '$4', # Timer/Counter0 Output Compare
+ 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
+ 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
+ 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
+ 'TIFR0_OCF0B': '$4', # Timer/Counter0 Output Compare
+ 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
+ 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSRSYNC': '$1', # Prescaler Reset Timer/Counter1
+
+# Module TIMER_COUNTER_2
+ 'TIMSK2' : '$70', # Timer/Counter Interrupt Mask r
+ 'TIMSK2_OCIE2B': '$4', # Timer/Counter2 Output Compare
+ 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
+ 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
+ 'TIFR2' : '$37', # Timer/Counter Interrupt Flag R
+ 'TIFR2_OCF2B': '$4', # Output Compare Flag 2B
+ 'TIFR2_OCF2A': '$2', # Output Compare Flag 2A
+ 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
+ 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
+ 'TCCR2A_COM2A': '$c0', # Compare Output Mode bits
+ 'TCCR2A_COM2B': '$30', # Compare Output Mode bits
+ 'TCCR2A_WGM2': '$3', # Waveform Genration Mode
+ 'TCCR2B' : '$b1', # Timer/Counter2 Control Registe
+ 'TCCR2B_FOC2A': '$80', # Force Output Compare A
+ 'TCCR2B_FOC2B': '$40', # Force Output Compare B
+ 'TCCR2B_WGM22': '$8', # Waveform Generation Mode
+ 'TCCR2B_CS2': '$7', # Clock Select bits
+ 'TCNT2' : '$b2', # Timer/Counter2
+ 'OCR2B' : '$b4', # Timer/Counter2 Output Compare
+ 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
+ 'ASSR' : '$b6', # Asynchronous Status Register
+ 'ASSR_EXCLK': '$40', # Enable External Clock Input
+ 'ASSR_AS2': '$20', # Asynchronous Timer/Counter2
+ 'ASSR_TCN2UB': '$10', # Timer/Counter2 Update Busy
+ 'ASSR_OCR2AUB': '$8', # Output Compare Register2 Updat
+ 'ASSR_OCR2BUB': '$4', # Output Compare Register 2 Upda
+ 'ASSR_TCR2AUB': '$2', # Timer/Counter Control Register
+ 'ASSR_TCR2BUB': '$1', # Timer/Counter Control Register
+ 'GTCCR' : '$43', # General Timer Counter Control
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSRASY': '$2', # Prescaler Reset Timer/Counter2
+
+# Module TIMER_COUNTER_3
+ 'TCCR3A' : '$90', # Timer/Counter3 Control Registe
+ 'TCCR3A_COM3A': '$c0', # Compare Output Mode 1A, bits
+ 'TCCR3A_COM3B': '$30', # Compare Output Mode 3B, bits
+ 'TCCR3A_COM3C': '$c', # Compare Output Mode 3C, bits
+ 'TCCR3A_WGM3': '$3', # Waveform Generation Mode
+ 'TCCR3B' : '$91', # Timer/Counter3 Control Registe
+ 'TCCR3B_ICNC3': '$80', # Input Capture 3 Noise Canceler
+ 'TCCR3B_ICES3': '$40', # Input Capture 3 Edge Select
+ 'TCCR3B_WGM3': '$18', # Waveform Generation Mode
+ 'TCCR3B_CS3': '$7', # Prescaler source of Timer/Coun
+ 'TCCR3C' : '$92', # Timer/Counter 3 Control Regist
+ 'TCCR3C_FOC3A': '$80', # Force Output Compare 3A
+ 'TCCR3C_FOC3B': '$40', # Force Output Compare 3B
+ 'TCCR3C_FOC3C': '$20', # Force Output Compare 3C
+ 'TCNT3' : '$94', # Timer/Counter3 Bytes
+ 'OCR3A' : '$98', # Timer/Counter3 Output Compare
+ 'OCR3B' : '$9a', # Timer/Counter3 Output Compare
+ 'OCR3C' : '$9c', # Timer/Counter3 Output Compare
+ 'ICR3' : '$96', # Timer/Counter3 Input Capture R
+ 'TIMSK3' : '$71', # Timer/Counter3 Interrupt Mask
+ 'TIMSK3_ICIE3': '$20', # Timer/Counter3 Input Capture I
+ 'TIMSK3_OCIE3C': '$8', # Timer/Counter3 Output Compare
+ 'TIMSK3_OCIE3B': '$4', # Timer/Counter3 Output Compare
+ 'TIMSK3_OCIE3A': '$2', # Timer/Counter3 Output Compare
+ 'TIMSK3_TOIE3': '$1', # Timer/Counter3 Overflow Interr
+ 'TIFR3' : '$38', # Timer/Counter3 Interrupt Flag
+ 'TIFR3_ICF3': '$20', # Input Capture Flag 3
+ 'TIFR3_OCF3C': '$8', # Output Compare Flag 3C
+ 'TIFR3_OCF3B': '$4', # Output Compare Flag 3B
+ 'TIFR3_OCF3A': '$2', # Output Compare Flag 3A
+ 'TIFR3_TOV3': '$1', # Timer/Counter3 Overflow Flag
+
+# Module TIMER_COUNTER_1
+ 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
+ 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
+ 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
+ 'TCCR1A_COM1C': '$c', # Compare Output Mode 1C, bits
+ 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
+ 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
+ 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
+ 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
+ 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
+ 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
+ 'TCCR1C' : '$82', # Timer/Counter 1 Control Regist
+ 'TCCR1C_FOC1A': '$80', # Force Output Compare 1A
+ 'TCCR1C_FOC1B': '$40', # Force Output Compare 1B
+ 'TCCR1C_FOC1C': '$20', # Force Output Compare 1C
+ 'TCNT1' : '$84', # Timer/Counter1 Bytes
+ 'OCR1A' : '$88', # Timer/Counter1 Output Compare
+ 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
+ 'OCR1C' : '$8c', # Timer/Counter1 Output Compare
+ 'ICR1' : '$86', # Timer/Counter1 Input Capture R
+ 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
+ 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
+ 'TIMSK1_OCIE1C': '$8', # Timer/Counter1 Output Compare
+ 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
+ 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
+ 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
+ 'TIFR1' : '$36', # Timer/Counter1 Interrupt Flag
+ 'TIFR1_ICF1': '$20', # Input Capture Flag 1
+ 'TIFR1_OCF1C': '$8', # Output Compare Flag 1C
+ 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
+ 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
+ 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
+
+# Module JTAG
+ 'OCDR' : '$51', # On-Chip Debug Related Register
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_JTD': '$80', # JTAG Interface Disable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+
+# Module EXTERNAL_INTERRUPT
+ 'EICRA' : '$69', # External Interrupt Control Reg
+ 'EICRA_ISC3': '$c0', # External Interrupt Sense Contr
+ 'EICRA_ISC2': '$30', # External Interrupt Sense Contr
+ 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
+ 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
+ 'EICRB' : '$6a', # External Interrupt Control Reg
+ 'EICRB_ISC7': '$c0', # External Interrupt 7-4 Sense C
+ 'EICRB_ISC6': '$30', # External Interrupt 7-4 Sense C
+ 'EICRB_ISC5': '$c', # External Interrupt 7-4 Sense C
+ 'EICRB_ISC4': '$3', # External Interrupt 7-4 Sense C
+ 'EIMSK' : '$3d', # External Interrupt Mask Regist
+ 'EIMSK_INT': '$ff', # External Interrupt Request 7 E
+ 'EIFR' : '$3c', # External Interrupt Flag Regist
+ 'EIFR_INTF': '$ff', # External Interrupt Flags
+ 'PCMSK0' : '$6b', # Pin Change Mask Register 0
+ 'PCIFR' : '$3b', # Pin Change Interrupt Flag Regi
+ 'PCIFR_PCIF0': '$1', # Pin Change Interrupt Flag 0
+ 'PCICR' : '$68', # Pin Change Interrupt Control R
+ 'PCICR_PCIE0': '$1', # Pin Change Interrupt Enable 0
+
+# Module AD_CONVERTER
+ 'ADMUX' : '$7c', # The ADC multiplexer Selection
+ 'ADMUX_REFS': '$c0', # Reference Selection Bits
+ 'ADMUX_ADLAR': '$20', # Left Adjust Result
+ 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
+ 'ADCSRA' : '$7a', # The ADC Control and Status reg
+ 'ADCSRA_ADEN': '$80', # ADC Enable
+ 'ADCSRA_ADSC': '$40', # ADC Start Conversion
+ 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
+ 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
+ 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
+ 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
+ 'ADC' : '$78', # ADC Data Register Bytes
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ADHSM': '$80', # ADC High Speed Mode
+ 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Sources
+ 'DIDR0' : '$7e', # Digital Input Disable Register
+ 'DIDR0_ADC7D': '$80', # ADC7 Digital input Disable
+ 'DIDR0_ADC6D': '$40', # ADC6 Digital input Disable
+ 'DIDR0_ADC5D': '$20', # ADC5 Digital input Disable
+ 'DIDR0_ADC4D': '$10', # ADC4 Digital input Disable
+ 'DIDR0_ADC3D': '$8', # ADC3 Digital input Disable
+ 'DIDR0_ADC2D': '$4', # ADC2 Digital input Disable
+ 'DIDR0_ADC1D': '$2', # ADC1 Digital input Disable
+ 'DIDR0_ADC0D': '$1', # ADC0 Digital input Disable
+
+# Module ANALOG_COMPARATOR
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
+ 'ACSR' : '$50', # Analog Comparator Control And
+ 'ACSR_ACD': '$80', # Analog Comparator Disable
+ 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
+ 'ACSR_ACO': '$20', # Analog Compare Output
+ 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
+ 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
+ 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
+ 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
+ 'DIDR1' : '$7f', #
+ 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
+ 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
+
+# Module PLL
+ 'PLLCSR' : '$49', # PLL Status and Control registe
+ 'PLLCSR_PLLP': '$1c', # PLL prescaler Bits
+ 'PLLCSR_PLLE': '$2', # PLL Enable Bit
+ 'PLLCSR_PLOCK': '$1', # PLL Lock Status Bit
+
+# Module USB_GLOBAL
+ 'USBINT' : '$da', #
+ 'USBINT_IDTI': '$2', #
+ 'USBINT_VBUSTI': '$1', #
+ 'USBSTA' : '$d9', #
+ 'USBSTA_SPEED': '$8', #
+ 'USBSTA_ID': '$2', #
+ 'USBSTA_VBUS': '$1', #
+ 'USBCON' : '$d8', # USB General Control Register
+ 'USBCON_USBE': '$80', #
+ 'USBCON_HOST': '$40', #
+ 'USBCON_FRZCLK': '$20', #
+ 'USBCON_OTGPADE': '$10', #
+ 'USBCON_IDTE': '$2', #
+ 'USBCON_VBUSTE': '$1', #
+ 'UHWCON' : '$d7', # USB Hardware Configuration Reg
+ 'UHWCON_UIMOD': '$80', #
+ 'UHWCON_UIDE': '$40', #
+ 'UHWCON_UVCONE': '$10', #
+ 'UHWCON_UVREGE': '$1', #
+
+ '__amforth_dummy':'0'
+}
diff --git a/amforth-6.5/avr8/devices/at90usb1286/words/no-jtag.asm b/amforth-6.5/avr8/devices/at90usb1286/words/no-jtag.asm
new file mode 100644
index 0000000..352a4bb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90usb1286/words/no-jtag.asm
@@ -0,0 +1,14 @@
+; ( -- )
+; ( -- )
+; MCU
+; disable jtag at runtime
+VE_NOJTAG:
+ .dw $FF05
+ .db "-jtag",0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOJTAG
+XT_NOJTAG:
+ .dw PFA_NOJTAG
+PFA_NOJTAG:
+
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/at90usb1286/words/no-wdt.asm b/amforth-6.5/avr8/devices/at90usb1286/words/no-wdt.asm
new file mode 100644
index 0000000..ff6ddd1
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90usb1286/words/no-wdt.asm
@@ -0,0 +1,34 @@
+; ( -- )
+; MCU
+; disable watch dog timer at runtime
+VE_NOWDT:
+ .dw $ff04
+ .db "-wdt"
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOWDT
+XT_NOWDT:
+ .dw PFA_NOWDT
+PFA_NOWDT:
+
+ in temp1,SREG
+ push temp1
+ ; Turn always off global interrupt.
+ cli
+ ; Reset Watchdog Timer
+ wdr
+ ; Clear WDRF in MCUSR
+ in temp1, MCUSR
+ andi temp1, (0xff & (0<<WDRF))
+ out MCUSR, temp1
+ ; Write logical one to WDCE and WDE
+ ; Keep old prescaler setting to prevent unintentional time-out
+ in_ temp1, WDTCSR
+ ori temp1, (1<<WDCE) | (1<<WDE)
+ out_ WDTCSR, temp1
+ ; Turn off WDT
+ ldi temp1, (0<<WDE)
+ out_ WDTCSR, temp1
+ ; restore status register
+ pop temp1
+ out SREG,temp1
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/at90usb1286/words/sleep.asm b/amforth-6.5/avr8/devices/at90usb1286/words/sleep.asm
new file mode 100644
index 0000000..256249c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90usb1286/words/sleep.asm
@@ -0,0 +1,19 @@
+; ( mode -- )
+; MCU
+; put the controller into the specified sleep mode
+VE_SLEEP:
+ .dw $ff05
+ .db "sleep", 0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_SLEEP
+XT_SLEEP:
+ .dw PFA_SLEEP
+PFA_SLEEP:
+ andi tosl, 7 ; leave only legal mode bits
+ lsl tosl ; move to correct location (bits 3-1)
+ ori tosl, 1 ; set the SE bit
+ out_ SMCR, tosl ; set the sleep config
+ sleep ; nighty-night
+ out_ SMCR, zerol ; 0 protects against accidental sleeps
+ loadtos ; pop argument from stack
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/at90usb1287/at90usb1287.frt b/amforth-6.5/avr8/devices/at90usb1287/at90usb1287.frt
new file mode 100644
index 0000000..5cf3ed4
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90usb1287/at90usb1287.frt
@@ -0,0 +1,587 @@
+\ Partname: AT90USB1287
+\ generated automatically
+
+\ WATCHDOG
+&96 constant WDTCSR \ Watchdog Timer Control Register
+ $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Flag
+ $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Enable
+ $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
+ $10 constant WDTCSR_WDCE \ Watchdog Change Enable
+ $08 constant WDTCSR_WDE \ Watch Dog Enable
+\ PORTA
+&34 constant PORTA \ Port A Data Register
+&33 constant DDRA \ Port A Data Direction Register
+&32 constant PINA \ Port A Input Pins
+\ PORTB
+&37 constant PORTB \ Port B Data Register
+&36 constant DDRB \ Port B Data Direction Register
+&35 constant PINB \ Port B Input Pins
+\ PORTC
+&40 constant PORTC \ Port C Data Register
+&39 constant DDRC \ Port C Data Direction Register
+&38 constant PINC \ Port C Input Pins
+\ PORTD
+&43 constant PORTD \ Port D Data Register
+&42 constant DDRD \ Port D Data Direction Register
+&41 constant PIND \ Port D Input Pins
+\ PORTE
+&46 constant PORTE \ Data Register, Port E
+&45 constant DDRE \ Data Direction Register, Port E
+&44 constant PINE \ Input Pins, Port E
+\ PORTF
+&49 constant PORTF \ Data Register, Port F
+&48 constant DDRF \ Data Direction Register, Port F
+&47 constant PINF \ Input Pins, Port F
+\ CPU
+&95 constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ $08 constant SREG_V \ Two's Complement Overflow Flag
+ $04 constant SREG_N \ Negative Flag
+ $02 constant SREG_Z \ Zero Flag
+ $01 constant SREG_C \ Carry Flag
+&93 constant SP \ Stack Pointer
+&85 constant MCUCR \ MCU Control Register
+ $80 constant MCUCR_JTD \ JTAG Interface Disable
+ $10 constant MCUCR_PUD \ Pull-up disable
+ $02 constant MCUCR_IVSEL \ Interrupt Vector Select
+ $01 constant MCUCR_IVCE \ Interrupt Vector Change Enable
+&84 constant MCUSR \ MCU Status Register
+ $10 constant MCUSR_JTRF \ JTAG Reset Flag
+ $08 constant MCUSR_WDRF \ Watchdog Reset Flag
+ $04 constant MCUSR_BORF \ Brown-out Reset Flag
+ $02 constant MCUSR_EXTRF \ External Reset Flag
+ $01 constant MCUSR_PORF \ Power-on reset flag
+&116 constant XMCRA \ External Memory Control Register A
+ $80 constant XMCRA_SRE \ External SRAM Enable
+ $70 constant XMCRA_SRL \ Wait state page limit
+ $0C constant XMCRA_SRW1 \ Wait state select bit upper page
+ $03 constant XMCRA_SRW0 \ Wait state select bit lower page
+&117 constant XMCRB \ External Memory Control Register B
+ $80 constant XMCRB_XMBK \ External Memory Bus Keeper Enable
+ $07 constant XMCRB_XMM \ External Memory High Mask
+&102 constant OSCCAL \ Oscillator Calibration Value
+&97 constant CLKPR \
+ $80 constant CLKPR_CLKPCE \
+ $0F constant CLKPR_CLKPS \
+&83 constant SMCR \ Sleep Mode Control Register
+ $0E constant SMCR_SM \ Sleep Mode Select bits
+ $01 constant SMCR_SE \ Sleep Enable
+&92 constant EIND \ Extended Indirect Register
+&91 constant RAMPZ \ RAM Page Z Select Register
+&75 constant GPIOR2 \ General Purpose IO Register 2
+ $FF constant GPIOR2_GPIOR \ General Purpose IO Register 2 bis
+&74 constant GPIOR1 \ General Purpose IO Register 1
+ $FF constant GPIOR1_GPIOR \ General Purpose IO Register 1 bis
+&62 constant GPIOR0 \ General Purpose IO Register 0
+ $80 constant GPIOR0_GPIOR07 \ General Purpose IO Register 0 bit 7
+ $40 constant GPIOR0_GPIOR06 \ General Purpose IO Register 0 bit 6
+ $20 constant GPIOR0_GPIOR05 \ General Purpose IO Register 0 bit 5
+ $10 constant GPIOR0_GPIOR04 \ General Purpose IO Register 0 bit 4
+ $08 constant GPIOR0_GPIOR03 \ General Purpose IO Register 0 bit 3
+ $04 constant GPIOR0_GPIOR02 \ General Purpose IO Register 0 bit 2
+ $02 constant GPIOR0_GPIOR01 \ General Purpose IO Register 0 bit 1
+ $01 constant GPIOR0_GPIOR00 \ General Purpose IO Register 0 bit 0
+&101 constant PRR1 \ Power Reduction Register1
+ $80 constant PRR1_PRUSB \ Power Reduction USB
+ $08 constant PRR1_PRTIM3 \ Power Reduction Timer/Counter3
+ $01 constant PRR1_PRUSART1 \ Power Reduction USART1
+&100 constant PRR0 \ Power Reduction Register0
+ $80 constant PRR0_PRTWI \ Power Reduction TWI
+ $40 constant PRR0_PRTIM2 \ Power Reduction Timer/Counter2
+ $20 constant PRR0_PRTIM0 \ Power Reduction Timer/Counter0
+ $08 constant PRR0_PRTIM1 \ Power Reduction Timer/Counter1
+ $04 constant PRR0_PRSPI \ Power Reduction Serial Peripheral Interface
+ $01 constant PRR0_PRADC \ Power Reduction ADC
+\ TWI
+&189 constant TWAMR \ TWI (Slave) Address Mask Register
+ $FE constant TWAMR_TWAM \
+&184 constant TWBR \ TWI Bit Rate register
+&188 constant TWCR \ TWI Control Register
+ $80 constant TWCR_TWINT \ TWI Interrupt Flag
+ $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
+ $20 constant TWCR_TWSTA \ TWI Start Condition Bit
+ $10 constant TWCR_TWSTO \ TWI Stop Condition Bit
+ $08 constant TWCR_TWWC \ TWI Write Collition Flag
+ $04 constant TWCR_TWEN \ TWI Enable Bit
+ $01 constant TWCR_TWIE \ TWI Interrupt Enable
+&185 constant TWSR \ TWI Status Register
+ $F8 constant TWSR_TWS \ TWI Status
+ $03 constant TWSR_TWPS \ TWI Prescaler
+&187 constant TWDR \ TWI Data register
+&186 constant TWAR \ TWI (Slave) Address register
+ $FE constant TWAR_TWA \ TWI (Slave) Address register Bits
+ $01 constant TWAR_TWGCE \ TWI General Call Recognition Enable Bit
+\ SPI
+&76 constant SPCR \ SPI Control Register
+ $80 constant SPCR_SPIE \ SPI Interrupt Enable
+ $40 constant SPCR_SPE \ SPI Enable
+ $20 constant SPCR_DORD \ Data Order
+ $10 constant SPCR_MSTR \ Master/Slave Select
+ $08 constant SPCR_CPOL \ Clock polarity
+ $04 constant SPCR_CPHA \ Clock Phase
+ $03 constant SPCR_SPR \ SPI Clock Rate Selects
+&77 constant SPSR \ SPI Status Register
+ $80 constant SPSR_SPIF \ SPI Interrupt Flag
+ $40 constant SPSR_WCOL \ Write Collision Flag
+ $01 constant SPSR_SPI2X \ Double SPI Speed Bit
+&78 constant SPDR \ SPI Data Register
+\ USART1
+&206 constant UDR1 \ USART I/O Data Register
+&200 constant UCSR1A \ USART Control and Status Register A
+ $80 constant UCSR1A_RXC1 \ USART Receive Complete
+ $40 constant UCSR1A_TXC1 \ USART Transmitt Complete
+ $20 constant UCSR1A_UDRE1 \ USART Data Register Empty
+ $10 constant UCSR1A_FE1 \ Framing Error
+ $08 constant UCSR1A_DOR1 \ Data overRun
+ $04 constant UCSR1A_UPE1 \ Parity Error
+ $02 constant UCSR1A_U2X1 \ Double the USART transmission speed
+ $01 constant UCSR1A_MPCM1 \ Multi-processor Communication Mode
+&201 constant UCSR1B \ USART Control and Status Register B
+ $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable
+ $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable
+ $20 constant UCSR1B_UDRIE1 \ USART Data register Empty Interrupt Enable
+ $10 constant UCSR1B_RXEN1 \ Receiver Enable
+ $08 constant UCSR1B_TXEN1 \ Transmitter Enable
+ $04 constant UCSR1B_UCSZ12 \ Character Size
+ $02 constant UCSR1B_RXB81 \ Receive Data Bit 8
+ $01 constant UCSR1B_TXB81 \ Transmit Data Bit 8
+&202 constant UCSR1C \ USART Control and Status Register C
+ $C0 constant UCSR1C_UMSEL1 \ USART Mode Select
+ $30 constant UCSR1C_UPM1 \ Parity Mode Bits
+ $08 constant UCSR1C_USBS1 \ Stop Bit Select
+ $06 constant UCSR1C_UCSZ1 \ Character Size
+ $01 constant UCSR1C_UCPOL1 \ Clock Polarity
+&204 constant UBRR1 \ USART Baud Rate Register Bytes
+\ USB_DEVICE
+&244 constant UEINT \
+&243 constant UEBCHX \
+&242 constant UEBCLX \
+&241 constant UEDATX \
+&240 constant UEIENX \
+ $80 constant UEIENX_FLERRE \
+ $40 constant UEIENX_NAKINE \
+ $10 constant UEIENX_NAKOUTE \
+ $08 constant UEIENX_RXSTPE \
+ $04 constant UEIENX_RXOUTE \
+ $02 constant UEIENX_STALLEDE \
+ $01 constant UEIENX_TXINE \
+&239 constant UESTA1X \
+ $04 constant UESTA1X_CTRLDIR \
+ $03 constant UESTA1X_CURRBK \
+&238 constant UESTA0X \
+ $80 constant UESTA0X_CFGOK \
+ $40 constant UESTA0X_OVERFI \
+ $20 constant UESTA0X_UNDERFI \
+ $0C constant UESTA0X_DTSEQ \
+ $03 constant UESTA0X_NBUSYBK \
+&237 constant UECFG1X \
+ $70 constant UECFG1X_EPSIZE \
+ $0C constant UECFG1X_EPBK \
+ $02 constant UECFG1X_ALLOC \
+&236 constant UECFG0X \
+ $C0 constant UECFG0X_EPTYPE \
+ $01 constant UECFG0X_EPDIR \
+&235 constant UECONX \
+ $20 constant UECONX_STALLRQ \
+ $10 constant UECONX_STALLRQC \
+ $08 constant UECONX_RSTDT \
+ $01 constant UECONX_EPEN \
+&234 constant UERST \
+ $7F constant UERST_EPRST \
+&233 constant UENUM \
+&232 constant UEINTX \
+ $80 constant UEINTX_FIFOCON \
+ $40 constant UEINTX_NAKINI \
+ $20 constant UEINTX_RWAL \
+ $10 constant UEINTX_NAKOUTI \
+ $08 constant UEINTX_RXSTPI \
+ $04 constant UEINTX_RXOUTI \
+ $02 constant UEINTX_STALLEDI \
+ $01 constant UEINTX_TXINI \
+&230 constant UDMFN \
+ $10 constant UDMFN_FNCERR \
+&228 constant UDFNUM \
+&227 constant UDADDR \
+ $80 constant UDADDR_ADDEN \
+ $7F constant UDADDR_UADD \
+&226 constant UDIEN \
+ $40 constant UDIEN_UPRSME \
+ $20 constant UDIEN_EORSME \
+ $10 constant UDIEN_WAKEUPE \
+ $08 constant UDIEN_EORSTE \
+ $04 constant UDIEN_SOFE \
+ $01 constant UDIEN_SUSPE \
+&225 constant UDINT \
+ $40 constant UDINT_UPRSMI \
+ $20 constant UDINT_EORSMI \
+ $10 constant UDINT_WAKEUPI \
+ $08 constant UDINT_EORSTI \
+ $04 constant UDINT_SOFI \
+ $01 constant UDINT_SUSPI \
+&224 constant UDCON \
+ $04 constant UDCON_LSM \
+ $02 constant UDCON_RMWKUP \
+ $01 constant UDCON_DETACH \
+\ USB_GLOBAL
+&223 constant OTGINT \
+ $20 constant OTGINT_STOI \
+ $10 constant OTGINT_HNPERRI \
+ $08 constant OTGINT_ROLEEXI \
+ $04 constant OTGINT_BCERRI \
+ $02 constant OTGINT_VBERRI \
+ $01 constant OTGINT_SRPI \
+&222 constant OTGIEN \
+ $20 constant OTGIEN_STOE \
+ $10 constant OTGIEN_HNPERRE \
+ $08 constant OTGIEN_ROLEEXE \
+ $04 constant OTGIEN_BCERRE \
+ $02 constant OTGIEN_VBERRE \
+ $01 constant OTGIEN_SRPE \
+&221 constant OTGCON \
+ $20 constant OTGCON_HNPREQ \
+ $10 constant OTGCON_SRPREQ \
+ $08 constant OTGCON_SRPSEL \
+ $04 constant OTGCON_VBUSHWC \
+ $02 constant OTGCON_VBUSREQ \
+ $01 constant OTGCON_VBUSRQC \
+&249 constant OTGTCON \
+ $80 constant OTGTCON_OTGTCON_7 \
+ $60 constant OTGTCON_PAGE \
+ $07 constant OTGTCON_VALUE_2 \
+&218 constant USBINT \
+ $02 constant USBINT_IDTI \
+ $01 constant USBINT_VBUSTI \
+&217 constant USBSTA \
+ $08 constant USBSTA_SPEED \
+ $02 constant USBSTA_ID \
+ $01 constant USBSTA_VBUS \
+&216 constant USBCON \ USB General Control Register
+ $80 constant USBCON_USBE \
+ $40 constant USBCON_HOST \
+ $20 constant USBCON_FRZCLK \
+ $10 constant USBCON_OTGPADE \
+ $02 constant USBCON_IDTE \
+ $01 constant USBCON_VBUSTE \
+&215 constant UHWCON \ USB Hardware Configuration Register
+ $80 constant UHWCON_UIMOD \
+ $40 constant UHWCON_UIDE \
+ $10 constant UHWCON_UVCONE \
+ $01 constant UHWCON_UVREGE \
+\ USB_HOST
+&245 constant UPERRX \
+ $60 constant UPERRX_COUNTER \
+ $10 constant UPERRX_CRC16 \
+ $08 constant UPERRX_TIMEOUT \
+ $04 constant UPERRX_PID \
+ $02 constant UPERRX_DATAPID \
+ $01 constant UPERRX_DATATGL \
+&248 constant UPINT \
+&247 constant UPBCHX \
+&246 constant UPBCLX \
+&175 constant UPDATX \
+&174 constant UPIENX \
+ $80 constant UPIENX_FLERRE \
+ $40 constant UPIENX_NAKEDE \
+ $10 constant UPIENX_PERRE \
+ $08 constant UPIENX_TXSTPE \
+ $04 constant UPIENX_TXOUTE \
+ $02 constant UPIENX_RXSTALLE \
+ $01 constant UPIENX_RXINE \
+&173 constant UPCFG2X \
+&172 constant UPSTAX \
+ $80 constant UPSTAX_CFGOK \
+ $40 constant UPSTAX_OVERFI \
+ $20 constant UPSTAX_UNDERFI \
+ $0C constant UPSTAX_DTSEQ \
+ $03 constant UPSTAX_NBUSYK \
+&171 constant UPCFG1X \
+ $70 constant UPCFG1X_PSIZE \
+ $0C constant UPCFG1X_PBK \
+ $02 constant UPCFG1X_ALLOC \
+&170 constant UPCFG0X \
+ $C0 constant UPCFG0X_PTYPE \
+ $30 constant UPCFG0X_PTOKEN \
+ $0F constant UPCFG0X_PEPNUM \
+&169 constant UPCONX \
+ $40 constant UPCONX_PFREEZE \
+ $20 constant UPCONX_INMODE \
+ $08 constant UPCONX_RSTDT \
+ $01 constant UPCONX_PEN \
+&168 constant UPRST \
+ $7F constant UPRST_PRST \
+&167 constant UPNUM \
+&166 constant UPINTX \
+ $80 constant UPINTX_FIFOCON \
+ $40 constant UPINTX_NAKEDI \
+ $20 constant UPINTX_RWAL \
+ $10 constant UPINTX_PERRI \
+ $08 constant UPINTX_TXSTPI \
+ $04 constant UPINTX_TXOUTI \
+ $02 constant UPINTX_RXSTALLI \
+ $01 constant UPINTX_RXINI \
+&165 constant UPINRQX \
+&164 constant UHFLEN \
+&162 constant UHFNUM \
+&161 constant UHADDR \
+&160 constant UHIEN \
+ $40 constant UHIEN_HWUPE \
+ $20 constant UHIEN_HSOFE \
+ $10 constant UHIEN_RXRSME \
+ $08 constant UHIEN_RSMEDE \
+ $04 constant UHIEN_RSTE \
+ $02 constant UHIEN_DDISCE \
+ $01 constant UHIEN_DCONNE \
+&159 constant UHINT \
+ $40 constant UHINT_UHUPI \
+ $20 constant UHINT_HSOFI \
+ $10 constant UHINT_RXRSMI \
+ $08 constant UHINT_RSMEDI \
+ $04 constant UHINT_RSTI \
+ $02 constant UHINT_DDISCI \
+ $01 constant UHINT_DCONNI \
+&158 constant UHCON \
+ $04 constant UHCON_RESUME \
+ $02 constant UHCON_RESET \
+ $01 constant UHCON_SOFEN \
+\ BOOT_LOAD
+&87 constant SPMCSR \ Store Program Memory Control Register
+ $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
+ $20 constant SPMCSR_SIGRD \ Signature Row Read
+ $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
+ $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
+ $04 constant SPMCSR_PGWRT \ Page Write
+ $02 constant SPMCSR_PGERS \ Page Erase
+ $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
+\ EEPROM
+&65 constant EEAR \ EEPROM Address Register Low Bytes
+&64 constant EEDR \ EEPROM Data Register
+&63 constant EECR \ EEPROM Control Register
+ $30 constant EECR_EEPM \ EEPROM Programming Mode Bits
+ $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
+ $04 constant EECR_EEMPE \ EEPROM Master Write Enable
+ $02 constant EECR_EEPE \ EEPROM Write Enable
+ $01 constant EECR_EERE \ EEPROM Read Enable
+\ TIMER_COUNTER_0
+&72 constant OCR0B \ Timer/Counter0 Output Compare Register
+&71 constant OCR0A \ Timer/Counter0 Output Compare Register
+&70 constant TCNT0 \ Timer/Counter0
+&69 constant TCCR0B \ Timer/Counter Control Register B
+ $80 constant TCCR0B_FOC0A \ Force Output Compare A
+ $40 constant TCCR0B_FOC0B \ Force Output Compare B
+ $08 constant TCCR0B_WGM02 \
+ $07 constant TCCR0B_CS0 \ Clock Select
+&68 constant TCCR0A \ Timer/Counter Control Register A
+ $C0 constant TCCR0A_COM0A \ Compare Output Mode, Phase Correct PWM Mode
+ $30 constant TCCR0A_COM0B \ Compare Output Mode, Fast PWm
+ $03 constant TCCR0A_WGM0 \ Waveform Generation Mode
+&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
+ $04 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare Match B Interrupt Enable
+ $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match A Interrupt Enable
+ $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
+&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
+ $04 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare Flag 0B
+ $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0A
+ $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
+&67 constant GTCCR \ General Timer/Counter Control Register
+ $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
+ $01 constant GTCCR_PSRSYNC \ Prescaler Reset Timer/Counter1 and Timer/Counter0
+\ TIMER_COUNTER_2
+&112 constant TIMSK2 \ Timer/Counter Interrupt Mask register
+ $04 constant TIMSK2_OCIE2B \ Timer/Counter2 Output Compare Match B Interrupt Enable
+ $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match A Interrupt Enable
+ $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
+&55 constant TIFR2 \ Timer/Counter Interrupt Flag Register
+ $04 constant TIFR2_OCF2B \ Output Compare Flag 2B
+ $02 constant TIFR2_OCF2A \ Output Compare Flag 2A
+ $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
+&176 constant TCCR2A \ Timer/Counter2 Control Register A
+ $C0 constant TCCR2A_COM2A \ Compare Output Mode bits
+ $30 constant TCCR2A_COM2B \ Compare Output Mode bits
+ $03 constant TCCR2A_WGM2 \ Waveform Genration Mode
+&177 constant TCCR2B \ Timer/Counter2 Control Register B
+ $80 constant TCCR2B_FOC2A \ Force Output Compare A
+ $40 constant TCCR2B_FOC2B \ Force Output Compare B
+ $08 constant TCCR2B_WGM22 \ Waveform Generation Mode
+ $07 constant TCCR2B_CS2 \ Clock Select bits
+&178 constant TCNT2 \ Timer/Counter2
+&180 constant OCR2B \ Timer/Counter2 Output Compare Register B
+&179 constant OCR2A \ Timer/Counter2 Output Compare Register A
+&182 constant ASSR \ Asynchronous Status Register
+ $40 constant ASSR_EXCLK \ Enable External Clock Input
+ $20 constant ASSR_AS2 \ Asynchronous Timer/Counter2
+ $10 constant ASSR_TCN2UB \ Timer/Counter2 Update Busy
+ $08 constant ASSR_OCR2AUB \ Output Compare Register2 Update Busy
+ $04 constant ASSR_OCR2BUB \ Output Compare Register 2 Update Busy
+ $02 constant ASSR_TCR2AUB \ Timer/Counter Control Register2 Update Busy
+ $01 constant ASSR_TCR2BUB \ Timer/Counter Control Register2 Update Busy
+\ TIMER_COUNTER_3
+&144 constant TCCR3A \ Timer/Counter3 Control Register A
+ $C0 constant TCCR3A_COM3A \ Compare Output Mode 1A, bits
+ $30 constant TCCR3A_COM3B \ Compare Output Mode 3B, bits
+ $0C constant TCCR3A_COM3C \ Compare Output Mode 3C, bits
+ $03 constant TCCR3A_WGM3 \ Waveform Generation Mode
+&145 constant TCCR3B \ Timer/Counter3 Control Register B
+ $80 constant TCCR3B_ICNC3 \ Input Capture 3 Noise Canceler
+ $40 constant TCCR3B_ICES3 \ Input Capture 3 Edge Select
+ $18 constant TCCR3B_WGM3 \ Waveform Generation Mode
+ $07 constant TCCR3B_CS3 \ Prescaler source of Timer/Counter 3
+&146 constant TCCR3C \ Timer/Counter 3 Control Register C
+ $80 constant TCCR3C_FOC3A \ Force Output Compare 3A
+ $40 constant TCCR3C_FOC3B \ Force Output Compare 3B
+ $20 constant TCCR3C_FOC3C \ Force Output Compare 3C
+&148 constant TCNT3 \ Timer/Counter3 Bytes
+&152 constant OCR3A \ Timer/Counter3 Output Compare Register A Bytes
+&154 constant OCR3B \ Timer/Counter3 Output Compare Register B Bytes
+&156 constant OCR3C \ Timer/Counter3 Output Compare Register B Bytes
+&150 constant ICR3 \ Timer/Counter3 Input Capture Register Bytes
+&113 constant TIMSK3 \ Timer/Counter3 Interrupt Mask Register
+ $20 constant TIMSK3_ICIE3 \ Timer/Counter3 Input Capture Interrupt Enable
+ $08 constant TIMSK3_OCIE3C \ Timer/Counter3 Output Compare C Match Interrupt Enable
+ $04 constant TIMSK3_OCIE3B \ Timer/Counter3 Output Compare B Match Interrupt Enable
+ $02 constant TIMSK3_OCIE3A \ Timer/Counter3 Output Compare A Match Interrupt Enable
+ $01 constant TIMSK3_TOIE3 \ Timer/Counter3 Overflow Interrupt Enable
+&56 constant TIFR3 \ Timer/Counter3 Interrupt Flag register
+ $20 constant TIFR3_ICF3 \ Input Capture Flag 3
+ $08 constant TIFR3_OCF3C \ Output Compare Flag 3C
+ $04 constant TIFR3_OCF3B \ Output Compare Flag 3B
+ $02 constant TIFR3_OCF3A \ Output Compare Flag 3A
+ $01 constant TIFR3_TOV3 \ Timer/Counter3 Overflow Flag
+\ TIMER_COUNTER_1
+&128 constant TCCR1A \ Timer/Counter1 Control Register A
+ $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
+ $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
+ $0C constant TCCR1A_COM1C \ Compare Output Mode 1C, bits
+ $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
+&129 constant TCCR1B \ Timer/Counter1 Control Register B
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
+ $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
+&130 constant TCCR1C \ Timer/Counter 1 Control Register C
+ $80 constant TCCR1C_FOC1A \ Force Output Compare 1A
+ $40 constant TCCR1C_FOC1B \ Force Output Compare 1B
+ $20 constant TCCR1C_FOC1C \ Force Output Compare 1C
+&132 constant TCNT1 \ Timer/Counter1 Bytes
+&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
+&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
+&140 constant OCR1C \ Timer/Counter1 Output Compare Register C Bytes
+&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
+&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
+ $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
+ $08 constant TIMSK1_OCIE1C \ Timer/Counter1 Output Compare C Match Interrupt Enable
+ $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
+ $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
+ $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
+&54 constant TIFR1 \ Timer/Counter1 Interrupt Flag register
+ $20 constant TIFR1_ICF1 \ Input Capture Flag 1
+ $08 constant TIFR1_OCF1C \ Output Compare Flag 1C
+ $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
+ $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
+ $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
+\ JTAG
+&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
+\ EXTERNAL_INTERRUPT
+&105 constant EICRA \ External Interrupt Control Register A
+ $C0 constant EICRA_ISC3 \ External Interrupt Sense Control Bit
+ $30 constant EICRA_ISC2 \ External Interrupt Sense Control Bit
+ $0C constant EICRA_ISC1 \ External Interrupt Sense Control Bit
+ $03 constant EICRA_ISC0 \ External Interrupt Sense Control Bit
+&106 constant EICRB \ External Interrupt Control Register B
+ $C0 constant EICRB_ISC7 \ External Interrupt 7-4 Sense Control Bit
+ $30 constant EICRB_ISC6 \ External Interrupt 7-4 Sense Control Bit
+ $0C constant EICRB_ISC5 \ External Interrupt 7-4 Sense Control Bit
+ $03 constant EICRB_ISC4 \ External Interrupt 7-4 Sense Control Bit
+&61 constant EIMSK \ External Interrupt Mask Register
+ $FF constant EIMSK_INT \ External Interrupt Request 7 Enable
+&60 constant EIFR \ External Interrupt Flag Register
+ $FF constant EIFR_INTF \ External Interrupt Flags
+&107 constant PCMSK0 \ Pin Change Mask Register 0
+&59 constant PCIFR \ Pin Change Interrupt Flag Register
+ $01 constant PCIFR_PCIF0 \ Pin Change Interrupt Flag 0
+&104 constant PCICR \ Pin Change Interrupt Control Register
+ $01 constant PCICR_PCIE0 \ Pin Change Interrupt Enable 0
+\ AD_CONVERTER
+&124 constant ADMUX \ The ADC multiplexer Selection Register
+ $C0 constant ADMUX_REFS \ Reference Selection Bits
+ $20 constant ADMUX_ADLAR \ Left Adjust Result
+ $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
+&122 constant ADCSRA \ The ADC Control and Status register
+ $80 constant ADCSRA_ADEN \ ADC Enable
+ $40 constant ADCSRA_ADSC \ ADC Start Conversion
+ $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
+ $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
+ $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
+ $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
+&120 constant ADC \ ADC Data Register Bytes
+&123 constant ADCSRB \ ADC Control and Status Register B
+ $80 constant ADCSRB_ADHSM \ ADC High Speed Mode
+ $07 constant ADCSRB_ADTS \ ADC Auto Trigger Sources
+&126 constant DIDR0 \ Digital Input Disable Register 1
+ $80 constant DIDR0_ADC7D \ ADC7 Digital input Disable
+ $40 constant DIDR0_ADC6D \ ADC6 Digital input Disable
+ $20 constant DIDR0_ADC5D \ ADC5 Digital input Disable
+ $10 constant DIDR0_ADC4D \ ADC4 Digital input Disable
+ $08 constant DIDR0_ADC3D \ ADC3 Digital input Disable
+ $04 constant DIDR0_ADC2D \ ADC2 Digital input Disable
+ $02 constant DIDR0_ADC1D \ ADC1 Digital input Disable
+ $01 constant DIDR0_ADC0D \ ADC0 Digital input Disable
+\ ANALOG_COMPARATOR
+&80 constant ACSR \ Analog Comparator Control And Status Register
+ $80 constant ACSR_ACD \ Analog Comparator Disable
+ $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
+ $20 constant ACSR_ACO \ Analog Compare Output
+ $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
+ $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
+ $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
+ $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
+&127 constant DIDR1 \
+ $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
+ $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
+\ PLL
+&73 constant PLLCSR \ PLL Status and Control register
+ $1C constant PLLCSR_PLLP \ PLL prescaler Bits
+ $02 constant PLLCSR_PLLE \ PLL Enable Bit
+ $01 constant PLLCSR_PLOCK \ PLL Lock Status Bit
+
+\ Interrupts
+&2 constant INT0Addr \ External Interrupt Request 0
+&4 constant INT1Addr \ External Interrupt Request 1
+&6 constant INT2Addr \ External Interrupt Request 2
+&8 constant INT3Addr \ External Interrupt Request 3
+&10 constant INT4Addr \ External Interrupt Request 4
+&12 constant INT5Addr \ External Interrupt Request 5
+&14 constant INT6Addr \ External Interrupt Request 6
+&16 constant INT7Addr \ External Interrupt Request 7
+&18 constant PCINT0Addr \ Pin Change Interrupt Request 0
+&20 constant USB_GENAddr \ USB General Interrupt Request
+&22 constant USB_COMAddr \ USB Endpoint/Pipe Interrupt Communication Reque
+&24 constant WDTAddr \ Watchdog Time-out Interrupt
+&26 constant TIMER2_COMPAAddr \ Timer/Counter2 Compare Match A
+&28 constant TIMER2_COMPBAddr \ Timer/Counter2 Compare Match B
+&30 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
+&32 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+&34 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
+&36 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
+&38 constant TIMER1_COMPCAddr \ Timer/Counter1 Compare Match C
+&40 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+&42 constant TIMER0_COMPAAddr \ Timer/Counter0 Compare Match A
+&44 constant TIMER0_COMPBAddr \ Timer/Counter0 Compare Match B
+&46 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
+&48 constant SPI__STCAddr \ SPI Serial Transfer Complete
+&50 constant USART1__RXAddr \ USART1, Rx Complete
+&52 constant USART1__UDREAddr \ USART1 Data register Empty
+&54 constant USART1__TXAddr \ USART1, Tx Complete
+&56 constant ANALOG_COMPAddr \ Analog Comparator
+&58 constant ADCAddr \ ADC Conversion Complete
+&60 constant EE_READYAddr \ EEPROM Ready
+&62 constant TIMER3_CAPTAddr \ Timer/Counter3 Capture Event
+&64 constant TIMER3_COMPAAddr \ Timer/Counter3 Compare Match A
+&66 constant TIMER3_COMPBAddr \ Timer/Counter3 Compare Match B
+&68 constant TIMER3_COMPCAddr \ Timer/Counter3 Compare Match C
+&70 constant TIMER3_OVFAddr \ Timer/Counter3 Overflow
+&72 constant TWIAddr \ 2-wire Serial Interface
+&74 constant SPM_READYAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/at90usb1287/device.asm b/amforth-6.5/avr8/devices/at90usb1287/device.asm
new file mode 100644
index 0000000..496a474
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90usb1287/device.asm
@@ -0,0 +1,146 @@
+; Partname: AT90USB1287
+; generated automatically, do not edit
+
+.nolist
+ .include "usb1287def.inc"
+.list
+
+.equ ramstart = 256
+.equ CELLSIZE = 2
+.macro readflashcell
+ clr temp7
+ lsl zl
+ rol zh
+ rol temp7
+ out_ RAMPZ, temp7
+ elpm @0, Z+
+ elpm @1, Z+
+.endmacro
+.macro writeflashcell
+ clr temp7
+ lsl zl
+ rol zh
+ rol temp7
+ out_ RAMPZ, temp7
+.endmacro
+.set WANT_WATCHDOG = 0
+.set WANT_PORTA = 0
+.set WANT_PORTB = 0
+.set WANT_PORTC = 0
+.set WANT_PORTD = 0
+.set WANT_PORTE = 0
+.set WANT_PORTF = 0
+.set WANT_CPU = 0
+.set WANT_TWI = 0
+.set WANT_SPI = 0
+.set WANT_USART1 = 0
+.set WANT_USB_DEVICE = 0
+.set WANT_USB_GLOBAL = 0
+.set WANT_USB_HOST = 0
+.set WANT_BOOT_LOAD = 0
+.set WANT_EEPROM = 0
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_TIMER_COUNTER_2 = 0
+.set WANT_TIMER_COUNTER_3 = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_JTAG = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_AD_CONVERTER = 0
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_PLL = 0
+.equ intvecsize = 2 ; please verify; flash size: 131072 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.org 2
+ rcall isr ; External Interrupt Request 0
+.org 4
+ rcall isr ; External Interrupt Request 1
+.org 6
+ rcall isr ; External Interrupt Request 2
+.org 8
+ rcall isr ; External Interrupt Request 3
+.org 10
+ rcall isr ; External Interrupt Request 4
+.org 12
+ rcall isr ; External Interrupt Request 5
+.org 14
+ rcall isr ; External Interrupt Request 6
+.org 16
+ rcall isr ; External Interrupt Request 7
+.org 18
+ rcall isr ; Pin Change Interrupt Request 0
+.org 20
+ rcall isr ; USB General Interrupt Request
+.org 22
+ rcall isr ; USB Endpoint/Pipe Interrupt Communication Request
+.org 24
+ rcall isr ; Watchdog Time-out Interrupt
+.org 26
+ rcall isr ; Timer/Counter2 Compare Match A
+.org 28
+ rcall isr ; Timer/Counter2 Compare Match B
+.org 30
+ rcall isr ; Timer/Counter2 Overflow
+.org 32
+ rcall isr ; Timer/Counter1 Capture Event
+.org 34
+ rcall isr ; Timer/Counter1 Compare Match A
+.org 36
+ rcall isr ; Timer/Counter1 Compare Match B
+.org 38
+ rcall isr ; Timer/Counter1 Compare Match C
+.org 40
+ rcall isr ; Timer/Counter1 Overflow
+.org 42
+ rcall isr ; Timer/Counter0 Compare Match A
+.org 44
+ rcall isr ; Timer/Counter0 Compare Match B
+.org 46
+ rcall isr ; Timer/Counter0 Overflow
+.org 48
+ rcall isr ; SPI Serial Transfer Complete
+.org 50
+ rcall isr ; USART1, Rx Complete
+.org 52
+ rcall isr ; USART1 Data register Empty
+.org 54
+ rcall isr ; USART1, Tx Complete
+.org 56
+ rcall isr ; Analog Comparator
+.org 58
+ rcall isr ; ADC Conversion Complete
+.org 60
+ rcall isr ; EEPROM Ready
+.org 62
+ rcall isr ; Timer/Counter3 Capture Event
+.org 64
+ rcall isr ; Timer/Counter3 Compare Match A
+.org 66
+ rcall isr ; Timer/Counter3 Compare Match B
+.org 68
+ rcall isr ; Timer/Counter3 Compare Match C
+.org 70
+ rcall isr ; Timer/Counter3 Overflow
+.org 72
+ rcall isr ; 2-wire Serial Interface
+.org 74
+ rcall isr ; Store Program Memory Read
+.equ INTVECTORS = 38
+.nooverlap
+
+; compatability layer (maybe empty)
+
+; controller data area, environment query mcu-info
+mcu_info:
+mcu_ramsize:
+ .dw 8192
+mcu_eepromsize:
+ .dw 4096
+mcu_maxdp:
+ .dw 65535
+mcu_numints:
+ .dw 38
+mcu_name:
+ .dw 11
+ .db "AT90USB1287",0
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/at90usb1287/device.inc b/amforth-6.5/avr8/devices/at90usb1287/device.inc
new file mode 100644
index 0000000..7772255
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90usb1287/device.inc
@@ -0,0 +1,1914 @@
+; Partname: AT90USB1287
+; generated automatically, no not edit
+
+.if WANT_WATCHDOG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCSR:
+ .dw $ff06
+ .db "WDTCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCSR
+XT_WDTCSR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCSR:
+ .dw 96
+
+.endif
+.if WANT_PORTA == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Register
+VE_PORTA:
+ .dw $ff05
+ .db "PORTA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTA
+XT_PORTA:
+ .dw PFA_DOVARIABLE
+PFA_PORTA:
+ .dw 34
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Direction Register
+VE_DDRA:
+ .dw $ff04
+ .db "DDRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRA
+XT_DDRA:
+ .dw PFA_DOVARIABLE
+PFA_DDRA:
+ .dw 33
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Input Pins
+VE_PINA:
+ .dw $ff04
+ .db "PINA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINA
+XT_PINA:
+ .dw PFA_DOVARIABLE
+PFA_PINA:
+ .dw 32
+
+.endif
+.if WANT_PORTB == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw 37
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw 36
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw 35
+
+.endif
+.if WANT_PORTC == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Register
+VE_PORTC:
+ .dw $ff05
+ .db "PORTC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTC
+XT_PORTC:
+ .dw PFA_DOVARIABLE
+PFA_PORTC:
+ .dw 40
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Direction Register
+VE_DDRC:
+ .dw $ff04
+ .db "DDRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRC
+XT_DDRC:
+ .dw PFA_DOVARIABLE
+PFA_DDRC:
+ .dw 39
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Input Pins
+VE_PINC:
+ .dw $ff04
+ .db "PINC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINC
+XT_PINC:
+ .dw PFA_DOVARIABLE
+PFA_PINC:
+ .dw 38
+
+.endif
+.if WANT_PORTD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw 43
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw 42
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw 41
+
+.endif
+.if WANT_PORTE == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port E
+VE_PORTE:
+ .dw $ff05
+ .db "PORTE",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTE
+XT_PORTE:
+ .dw PFA_DOVARIABLE
+PFA_PORTE:
+ .dw 46
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port E
+VE_DDRE:
+ .dw $ff04
+ .db "DDRE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRE
+XT_DDRE:
+ .dw PFA_DOVARIABLE
+PFA_DDRE:
+ .dw 45
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port E
+VE_PINE:
+ .dw $ff04
+ .db "PINE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINE
+XT_PINE:
+ .dw PFA_DOVARIABLE
+PFA_PINE:
+ .dw 44
+
+.endif
+.if WANT_PORTF == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port F
+VE_PORTF:
+ .dw $ff05
+ .db "PORTF",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTF
+XT_PORTF:
+ .dw PFA_DOVARIABLE
+PFA_PORTF:
+ .dw 49
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port F
+VE_DDRF:
+ .dw $ff04
+ .db "DDRF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRF
+XT_DDRF:
+ .dw PFA_DOVARIABLE
+PFA_DDRF:
+ .dw 48
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port F
+VE_PINF:
+ .dw $ff04
+ .db "PINF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINF
+XT_PINF:
+ .dw PFA_DOVARIABLE
+PFA_PINF:
+ .dw 47
+
+.endif
+.if WANT_CPU == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw 95
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer
+VE_SP:
+ .dw $ff02
+ .db "SP"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SP
+XT_SP:
+ .dw PFA_DOVARIABLE
+PFA_SP:
+ .dw 93
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw 85
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Status Register
+VE_MCUSR:
+ .dw $ff05
+ .db "MCUSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUSR
+XT_MCUSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUSR:
+ .dw 84
+; ( -- addr ) System Constant
+; R( -- )
+; External Memory Control Register A
+VE_XMCRA:
+ .dw $ff05
+ .db "XMCRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_XMCRA
+XT_XMCRA:
+ .dw PFA_DOVARIABLE
+PFA_XMCRA:
+ .dw 116
+; ( -- addr ) System Constant
+; R( -- )
+; External Memory Control Register B
+VE_XMCRB:
+ .dw $ff05
+ .db "XMCRB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_XMCRB
+XT_XMCRB:
+ .dw PFA_DOVARIABLE
+PFA_XMCRB:
+ .dw 117
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Calibration Value
+VE_OSCCAL:
+ .dw $ff06
+ .db "OSCCAL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSCCAL
+XT_OSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_OSCCAL:
+ .dw 102
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_CLKPR:
+ .dw $ff05
+ .db "CLKPR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKPR
+XT_CLKPR:
+ .dw PFA_DOVARIABLE
+PFA_CLKPR:
+ .dw 97
+; ( -- addr ) System Constant
+; R( -- )
+; Sleep Mode Control Register
+VE_SMCR:
+ .dw $ff04
+ .db "SMCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SMCR
+XT_SMCR:
+ .dw PFA_DOVARIABLE
+PFA_SMCR:
+ .dw 83
+; ( -- addr ) System Constant
+; R( -- )
+; Extended Indirect Register
+VE_EIND:
+ .dw $ff04
+ .db "EIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIND
+XT_EIND:
+ .dw PFA_DOVARIABLE
+PFA_EIND:
+ .dw 92
+; ( -- addr ) System Constant
+; R( -- )
+; RAM Page Z Select Register
+VE_RAMPZ:
+ .dw $ff05
+ .db "RAMPZ",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_RAMPZ
+XT_RAMPZ:
+ .dw PFA_DOVARIABLE
+PFA_RAMPZ:
+ .dw 91
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 2
+VE_GPIOR2:
+ .dw $ff06
+ .db "GPIOR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR2
+XT_GPIOR2:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR2:
+ .dw 75
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 1
+VE_GPIOR1:
+ .dw $ff06
+ .db "GPIOR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR1
+XT_GPIOR1:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR1:
+ .dw 74
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 0
+VE_GPIOR0:
+ .dw $ff06
+ .db "GPIOR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR0
+XT_GPIOR0:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR0:
+ .dw 62
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register1
+VE_PRR1:
+ .dw $ff04
+ .db "PRR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR1
+XT_PRR1:
+ .dw PFA_DOVARIABLE
+PFA_PRR1:
+ .dw 101
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register0
+VE_PRR0:
+ .dw $ff04
+ .db "PRR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR0
+XT_PRR0:
+ .dw PFA_DOVARIABLE
+PFA_PRR0:
+ .dw 100
+
+.endif
+.if WANT_TWI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; TWI (Slave) Address Mask Register
+VE_TWAMR:
+ .dw $ff05
+ .db "TWAMR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWAMR
+XT_TWAMR:
+ .dw PFA_DOVARIABLE
+PFA_TWAMR:
+ .dw 189
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Bit Rate register
+VE_TWBR:
+ .dw $ff04
+ .db "TWBR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWBR
+XT_TWBR:
+ .dw PFA_DOVARIABLE
+PFA_TWBR:
+ .dw 184
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Control Register
+VE_TWCR:
+ .dw $ff04
+ .db "TWCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWCR
+XT_TWCR:
+ .dw PFA_DOVARIABLE
+PFA_TWCR:
+ .dw 188
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Status Register
+VE_TWSR:
+ .dw $ff04
+ .db "TWSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWSR
+XT_TWSR:
+ .dw PFA_DOVARIABLE
+PFA_TWSR:
+ .dw 185
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Data register
+VE_TWDR:
+ .dw $ff04
+ .db "TWDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWDR
+XT_TWDR:
+ .dw PFA_DOVARIABLE
+PFA_TWDR:
+ .dw 187
+; ( -- addr ) System Constant
+; R( -- )
+; TWI (Slave) Address register
+VE_TWAR:
+ .dw $ff04
+ .db "TWAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWAR
+XT_TWAR:
+ .dw PFA_DOVARIABLE
+PFA_TWAR:
+ .dw 186
+
+.endif
+.if WANT_SPI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR:
+ .dw $ff04
+ .db "SPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR
+XT_SPCR:
+ .dw PFA_DOVARIABLE
+PFA_SPCR:
+ .dw 76
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR:
+ .dw $ff04
+ .db "SPSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR
+XT_SPSR:
+ .dw PFA_DOVARIABLE
+PFA_SPSR:
+ .dw 77
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR:
+ .dw $ff04
+ .db "SPDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR
+XT_SPDR:
+ .dw PFA_DOVARIABLE
+PFA_SPDR:
+ .dw 78
+
+.endif
+.if WANT_USART1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR1:
+ .dw $ff04
+ .db "UDR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR1
+XT_UDR1:
+ .dw PFA_DOVARIABLE
+PFA_UDR1:
+ .dw 206
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR1A:
+ .dw $ff06
+ .db "UCSR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1A
+XT_UCSR1A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1A:
+ .dw 200
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR1B:
+ .dw $ff06
+ .db "UCSR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1B
+XT_UCSR1B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1B:
+ .dw 201
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR1C:
+ .dw $ff06
+ .db "UCSR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1C
+XT_UCSR1C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1C:
+ .dw 202
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Bytes
+VE_UBRR1:
+ .dw $ff05
+ .db "UBRR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR1
+XT_UBRR1:
+ .dw PFA_DOVARIABLE
+PFA_UBRR1:
+ .dw 204
+
+.endif
+.if WANT_USB_DEVICE == 1
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UEINT:
+ .dw $ff05
+ .db "UEINT",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UEINT
+XT_UEINT:
+ .dw PFA_DOVARIABLE
+PFA_UEINT:
+ .dw 244
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UEBCHX:
+ .dw $ff06
+ .db "UEBCHX"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UEBCHX
+XT_UEBCHX:
+ .dw PFA_DOVARIABLE
+PFA_UEBCHX:
+ .dw 243
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UEBCLX:
+ .dw $ff06
+ .db "UEBCLX"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UEBCLX
+XT_UEBCLX:
+ .dw PFA_DOVARIABLE
+PFA_UEBCLX:
+ .dw 242
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UEDATX:
+ .dw $ff06
+ .db "UEDATX"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UEDATX
+XT_UEDATX:
+ .dw PFA_DOVARIABLE
+PFA_UEDATX:
+ .dw 241
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UEIENX:
+ .dw $ff06
+ .db "UEIENX"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UEIENX
+XT_UEIENX:
+ .dw PFA_DOVARIABLE
+PFA_UEIENX:
+ .dw 240
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UESTA1X:
+ .dw $ff07
+ .db "UESTA1X",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UESTA1X
+XT_UESTA1X:
+ .dw PFA_DOVARIABLE
+PFA_UESTA1X:
+ .dw 239
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UESTA0X:
+ .dw $ff07
+ .db "UESTA0X",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UESTA0X
+XT_UESTA0X:
+ .dw PFA_DOVARIABLE
+PFA_UESTA0X:
+ .dw 238
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UECFG1X:
+ .dw $ff07
+ .db "UECFG1X",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UECFG1X
+XT_UECFG1X:
+ .dw PFA_DOVARIABLE
+PFA_UECFG1X:
+ .dw 237
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UECFG0X:
+ .dw $ff07
+ .db "UECFG0X",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UECFG0X
+XT_UECFG0X:
+ .dw PFA_DOVARIABLE
+PFA_UECFG0X:
+ .dw 236
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UECONX:
+ .dw $ff06
+ .db "UECONX"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UECONX
+XT_UECONX:
+ .dw PFA_DOVARIABLE
+PFA_UECONX:
+ .dw 235
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UERST:
+ .dw $ff05
+ .db "UERST",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UERST
+XT_UERST:
+ .dw PFA_DOVARIABLE
+PFA_UERST:
+ .dw 234
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UENUM:
+ .dw $ff05
+ .db "UENUM",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UENUM
+XT_UENUM:
+ .dw PFA_DOVARIABLE
+PFA_UENUM:
+ .dw 233
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UEINTX:
+ .dw $ff06
+ .db "UEINTX"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UEINTX
+XT_UEINTX:
+ .dw PFA_DOVARIABLE
+PFA_UEINTX:
+ .dw 232
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UDMFN:
+ .dw $ff05
+ .db "UDMFN",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDMFN
+XT_UDMFN:
+ .dw PFA_DOVARIABLE
+PFA_UDMFN:
+ .dw 230
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UDFNUM:
+ .dw $ff06
+ .db "UDFNUM"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDFNUM
+XT_UDFNUM:
+ .dw PFA_DOVARIABLE
+PFA_UDFNUM:
+ .dw 228
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UDADDR:
+ .dw $ff06
+ .db "UDADDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDADDR
+XT_UDADDR:
+ .dw PFA_DOVARIABLE
+PFA_UDADDR:
+ .dw 227
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UDIEN:
+ .dw $ff05
+ .db "UDIEN",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDIEN
+XT_UDIEN:
+ .dw PFA_DOVARIABLE
+PFA_UDIEN:
+ .dw 226
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UDINT:
+ .dw $ff05
+ .db "UDINT",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDINT
+XT_UDINT:
+ .dw PFA_DOVARIABLE
+PFA_UDINT:
+ .dw 225
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UDCON:
+ .dw $ff05
+ .db "UDCON",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDCON
+XT_UDCON:
+ .dw PFA_DOVARIABLE
+PFA_UDCON:
+ .dw 224
+
+.endif
+.if WANT_USB_GLOBAL == 1
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_OTGINT:
+ .dw $ff06
+ .db "OTGINT"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OTGINT
+XT_OTGINT:
+ .dw PFA_DOVARIABLE
+PFA_OTGINT:
+ .dw 223
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_OTGIEN:
+ .dw $ff06
+ .db "OTGIEN"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OTGIEN
+XT_OTGIEN:
+ .dw PFA_DOVARIABLE
+PFA_OTGIEN:
+ .dw 222
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_OTGCON:
+ .dw $ff06
+ .db "OTGCON"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OTGCON
+XT_OTGCON:
+ .dw PFA_DOVARIABLE
+PFA_OTGCON:
+ .dw 221
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_OTGTCON:
+ .dw $ff07
+ .db "OTGTCON",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OTGTCON
+XT_OTGTCON:
+ .dw PFA_DOVARIABLE
+PFA_OTGTCON:
+ .dw 249
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_USBINT:
+ .dw $ff06
+ .db "USBINT"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USBINT
+XT_USBINT:
+ .dw PFA_DOVARIABLE
+PFA_USBINT:
+ .dw 218
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_USBSTA:
+ .dw $ff06
+ .db "USBSTA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USBSTA
+XT_USBSTA:
+ .dw PFA_DOVARIABLE
+PFA_USBSTA:
+ .dw 217
+; ( -- addr ) System Constant
+; R( -- )
+; USB General Control Register
+VE_USBCON:
+ .dw $ff06
+ .db "USBCON"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USBCON
+XT_USBCON:
+ .dw PFA_DOVARIABLE
+PFA_USBCON:
+ .dw 216
+; ( -- addr ) System Constant
+; R( -- )
+; USB Hardware Configuration Register
+VE_UHWCON:
+ .dw $ff06
+ .db "UHWCON"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UHWCON
+XT_UHWCON:
+ .dw PFA_DOVARIABLE
+PFA_UHWCON:
+ .dw 215
+
+.endif
+.if WANT_USB_HOST == 1
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UPERRX:
+ .dw $ff06
+ .db "UPERRX"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UPERRX
+XT_UPERRX:
+ .dw PFA_DOVARIABLE
+PFA_UPERRX:
+ .dw 245
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UPINT:
+ .dw $ff05
+ .db "UPINT",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UPINT
+XT_UPINT:
+ .dw PFA_DOVARIABLE
+PFA_UPINT:
+ .dw 248
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UPBCHX:
+ .dw $ff06
+ .db "UPBCHX"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UPBCHX
+XT_UPBCHX:
+ .dw PFA_DOVARIABLE
+PFA_UPBCHX:
+ .dw 247
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UPBCLX:
+ .dw $ff06
+ .db "UPBCLX"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UPBCLX
+XT_UPBCLX:
+ .dw PFA_DOVARIABLE
+PFA_UPBCLX:
+ .dw 246
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UPDATX:
+ .dw $ff06
+ .db "UPDATX"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UPDATX
+XT_UPDATX:
+ .dw PFA_DOVARIABLE
+PFA_UPDATX:
+ .dw 175
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UPIENX:
+ .dw $ff06
+ .db "UPIENX"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UPIENX
+XT_UPIENX:
+ .dw PFA_DOVARIABLE
+PFA_UPIENX:
+ .dw 174
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UPCFG2X:
+ .dw $ff07
+ .db "UPCFG2X",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UPCFG2X
+XT_UPCFG2X:
+ .dw PFA_DOVARIABLE
+PFA_UPCFG2X:
+ .dw 173
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UPSTAX:
+ .dw $ff06
+ .db "UPSTAX"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UPSTAX
+XT_UPSTAX:
+ .dw PFA_DOVARIABLE
+PFA_UPSTAX:
+ .dw 172
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UPCFG1X:
+ .dw $ff07
+ .db "UPCFG1X",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UPCFG1X
+XT_UPCFG1X:
+ .dw PFA_DOVARIABLE
+PFA_UPCFG1X:
+ .dw 171
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UPCFG0X:
+ .dw $ff07
+ .db "UPCFG0X",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UPCFG0X
+XT_UPCFG0X:
+ .dw PFA_DOVARIABLE
+PFA_UPCFG0X:
+ .dw 170
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UPCONX:
+ .dw $ff06
+ .db "UPCONX"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UPCONX
+XT_UPCONX:
+ .dw PFA_DOVARIABLE
+PFA_UPCONX:
+ .dw 169
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UPRST:
+ .dw $ff05
+ .db "UPRST",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UPRST
+XT_UPRST:
+ .dw PFA_DOVARIABLE
+PFA_UPRST:
+ .dw 168
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UPNUM:
+ .dw $ff05
+ .db "UPNUM",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UPNUM
+XT_UPNUM:
+ .dw PFA_DOVARIABLE
+PFA_UPNUM:
+ .dw 167
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UPINTX:
+ .dw $ff06
+ .db "UPINTX"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UPINTX
+XT_UPINTX:
+ .dw PFA_DOVARIABLE
+PFA_UPINTX:
+ .dw 166
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UPINRQX:
+ .dw $ff07
+ .db "UPINRQX",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UPINRQX
+XT_UPINRQX:
+ .dw PFA_DOVARIABLE
+PFA_UPINRQX:
+ .dw 165
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UHFLEN:
+ .dw $ff06
+ .db "UHFLEN"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UHFLEN
+XT_UHFLEN:
+ .dw PFA_DOVARIABLE
+PFA_UHFLEN:
+ .dw 164
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UHFNUM:
+ .dw $ff06
+ .db "UHFNUM"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UHFNUM
+XT_UHFNUM:
+ .dw PFA_DOVARIABLE
+PFA_UHFNUM:
+ .dw 162
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UHADDR:
+ .dw $ff06
+ .db "UHADDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UHADDR
+XT_UHADDR:
+ .dw PFA_DOVARIABLE
+PFA_UHADDR:
+ .dw 161
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UHIEN:
+ .dw $ff05
+ .db "UHIEN",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UHIEN
+XT_UHIEN:
+ .dw PFA_DOVARIABLE
+PFA_UHIEN:
+ .dw 160
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UHINT:
+ .dw $ff05
+ .db "UHINT",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UHINT
+XT_UHINT:
+ .dw PFA_DOVARIABLE
+PFA_UHINT:
+ .dw 159
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UHCON:
+ .dw $ff05
+ .db "UHCON",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UHCON
+XT_UHCON:
+ .dw PFA_DOVARIABLE
+PFA_UHCON:
+ .dw 158
+
+.endif
+.if WANT_BOOT_LOAD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control Register
+VE_SPMCSR:
+ .dw $ff06
+ .db "SPMCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCSR
+XT_SPMCSR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCSR:
+ .dw 87
+
+.endif
+.if WANT_EEPROM == 1
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Address Register Low Bytes
+VE_EEAR:
+ .dw $ff04
+ .db "EEAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEAR
+XT_EEAR:
+ .dw PFA_DOVARIABLE
+PFA_EEAR:
+ .dw 65
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw 64
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw 63
+
+.endif
+.if WANT_TIMER_COUNTER_0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0B:
+ .dw $ff05
+ .db "OCR0B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0B
+XT_OCR0B:
+ .dw PFA_DOVARIABLE
+PFA_OCR0B:
+ .dw 72
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0A:
+ .dw $ff05
+ .db "OCR0A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0A
+XT_OCR0A:
+ .dw PFA_DOVARIABLE
+PFA_OCR0A:
+ .dw 71
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw 70
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register B
+VE_TCCR0B:
+ .dw $ff06
+ .db "TCCR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0B
+XT_TCCR0B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0B:
+ .dw 69
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register A
+VE_TCCR0A:
+ .dw $ff06
+ .db "TCCR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0A
+XT_TCCR0A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0A:
+ .dw 68
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Mask Register
+VE_TIMSK0:
+ .dw $ff06
+ .db "TIMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK0
+XT_TIMSK0:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK0:
+ .dw 110
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Flag register
+VE_TIFR0:
+ .dw $ff05
+ .db "TIFR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR0
+XT_TIFR0:
+ .dw PFA_DOVARIABLE
+PFA_TIFR0:
+ .dw 53
+; ( -- addr ) System Constant
+; R( -- )
+; General Timer/Counter Control Register
+VE_GTCCR:
+ .dw $ff05
+ .db "GTCCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GTCCR
+XT_GTCCR:
+ .dw PFA_DOVARIABLE
+PFA_GTCCR:
+ .dw 67
+
+.endif
+.if WANT_TIMER_COUNTER_2 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Mask register
+VE_TIMSK2:
+ .dw $ff06
+ .db "TIMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK2
+XT_TIMSK2:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK2:
+ .dw 112
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Flag Register
+VE_TIFR2:
+ .dw $ff05
+ .db "TIFR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR2
+XT_TIFR2:
+ .dw PFA_DOVARIABLE
+PFA_TIFR2:
+ .dw 55
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register A
+VE_TCCR2A:
+ .dw $ff06
+ .db "TCCR2A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2A
+XT_TCCR2A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2A:
+ .dw 176
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register B
+VE_TCCR2B:
+ .dw $ff06
+ .db "TCCR2B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2B
+XT_TCCR2B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2B:
+ .dw 177
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2
+VE_TCNT2:
+ .dw $ff05
+ .db "TCNT2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT2
+XT_TCNT2:
+ .dw PFA_DOVARIABLE
+PFA_TCNT2:
+ .dw 178
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register B
+VE_OCR2B:
+ .dw $ff05
+ .db "OCR2B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2B
+XT_OCR2B:
+ .dw PFA_DOVARIABLE
+PFA_OCR2B:
+ .dw 180
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register A
+VE_OCR2A:
+ .dw $ff05
+ .db "OCR2A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2A
+XT_OCR2A:
+ .dw PFA_DOVARIABLE
+PFA_OCR2A:
+ .dw 179
+; ( -- addr ) System Constant
+; R( -- )
+; Asynchronous Status Register
+VE_ASSR:
+ .dw $ff04
+ .db "ASSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ASSR
+XT_ASSR:
+ .dw PFA_DOVARIABLE
+PFA_ASSR:
+ .dw 182
+
+.endif
+.if WANT_TIMER_COUNTER_3 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Control Register A
+VE_TCCR3A:
+ .dw $ff06
+ .db "TCCR3A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR3A
+XT_TCCR3A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR3A:
+ .dw 144
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Control Register B
+VE_TCCR3B:
+ .dw $ff06
+ .db "TCCR3B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR3B
+XT_TCCR3B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR3B:
+ .dw 145
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter 3 Control Register C
+VE_TCCR3C:
+ .dw $ff06
+ .db "TCCR3C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR3C
+XT_TCCR3C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR3C:
+ .dw 146
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Bytes
+VE_TCNT3:
+ .dw $ff05
+ .db "TCNT3",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT3
+XT_TCNT3:
+ .dw PFA_DOVARIABLE
+PFA_TCNT3:
+ .dw 148
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Output Compare Register A Bytes
+VE_OCR3A:
+ .dw $ff05
+ .db "OCR3A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR3A
+XT_OCR3A:
+ .dw PFA_DOVARIABLE
+PFA_OCR3A:
+ .dw 152
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Output Compare Register B Bytes
+VE_OCR3B:
+ .dw $ff05
+ .db "OCR3B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR3B
+XT_OCR3B:
+ .dw PFA_DOVARIABLE
+PFA_OCR3B:
+ .dw 154
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Output Compare Register B Bytes
+VE_OCR3C:
+ .dw $ff05
+ .db "OCR3C",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR3C
+XT_OCR3C:
+ .dw PFA_DOVARIABLE
+PFA_OCR3C:
+ .dw 156
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Input Capture Register Bytes
+VE_ICR3:
+ .dw $ff04
+ .db "ICR3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR3
+XT_ICR3:
+ .dw PFA_DOVARIABLE
+PFA_ICR3:
+ .dw 150
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Interrupt Mask Register
+VE_TIMSK3:
+ .dw $ff06
+ .db "TIMSK3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK3
+XT_TIMSK3:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK3:
+ .dw 113
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Interrupt Flag register
+VE_TIFR3:
+ .dw $ff05
+ .db "TIFR3",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR3
+XT_TIFR3:
+ .dw PFA_DOVARIABLE
+PFA_TIFR3:
+ .dw 56
+
+.endif
+.if WANT_TIMER_COUNTER_1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw 128
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw 129
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter 1 Control Register C
+VE_TCCR1C:
+ .dw $ff06
+ .db "TCCR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1C
+XT_TCCR1C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1C:
+ .dw 130
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Bytes
+VE_TCNT1:
+ .dw $ff05
+ .db "TCNT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1
+XT_TCNT1:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1:
+ .dw 132
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register A Bytes
+VE_OCR1A:
+ .dw $ff05
+ .db "OCR1A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1A
+XT_OCR1A:
+ .dw PFA_DOVARIABLE
+PFA_OCR1A:
+ .dw 136
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register B Bytes
+VE_OCR1B:
+ .dw $ff05
+ .db "OCR1B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1B
+XT_OCR1B:
+ .dw PFA_DOVARIABLE
+PFA_OCR1B:
+ .dw 138
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register C Bytes
+VE_OCR1C:
+ .dw $ff05
+ .db "OCR1C",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1C
+XT_OCR1C:
+ .dw PFA_DOVARIABLE
+PFA_OCR1C:
+ .dw 140
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Bytes
+VE_ICR1:
+ .dw $ff04
+ .db "ICR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1
+XT_ICR1:
+ .dw PFA_DOVARIABLE
+PFA_ICR1:
+ .dw 134
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Mask Register
+VE_TIMSK1:
+ .dw $ff06
+ .db "TIMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK1
+XT_TIMSK1:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK1:
+ .dw 111
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Flag register
+VE_TIFR1:
+ .dw $ff05
+ .db "TIFR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR1
+XT_TIFR1:
+ .dw PFA_DOVARIABLE
+PFA_TIFR1:
+ .dw 54
+
+.endif
+.if WANT_JTAG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; On-Chip Debug Related Register in I/O Memory
+VE_OCDR:
+ .dw $ff04
+ .db "OCDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCDR
+XT_OCDR:
+ .dw PFA_DOVARIABLE
+PFA_OCDR:
+ .dw 81
+
+.endif
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register A
+VE_EICRA:
+ .dw $ff05
+ .db "EICRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRA
+XT_EICRA:
+ .dw PFA_DOVARIABLE
+PFA_EICRA:
+ .dw 105
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register B
+VE_EICRB:
+ .dw $ff05
+ .db "EICRB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRB
+XT_EICRB:
+ .dw PFA_DOVARIABLE
+PFA_EICRB:
+ .dw 106
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Mask Register
+VE_EIMSK:
+ .dw $ff05
+ .db "EIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIMSK
+XT_EIMSK:
+ .dw PFA_DOVARIABLE
+PFA_EIMSK:
+ .dw 61
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Flag Register
+VE_EIFR:
+ .dw $ff04
+ .db "EIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIFR
+XT_EIFR:
+ .dw PFA_DOVARIABLE
+PFA_EIFR:
+ .dw 60
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 0
+VE_PCMSK0:
+ .dw $ff06
+ .db "PCMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK0
+XT_PCMSK0:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK0:
+ .dw 107
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Interrupt Flag Register
+VE_PCIFR:
+ .dw $ff05
+ .db "PCIFR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCIFR
+XT_PCIFR:
+ .dw PFA_DOVARIABLE
+PFA_PCIFR:
+ .dw 59
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Interrupt Control Register
+VE_PCICR:
+ .dw $ff05
+ .db "PCICR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCICR
+XT_PCICR:
+ .dw PFA_DOVARIABLE
+PFA_PCICR:
+ .dw 104
+
+.endif
+.if WANT_AD_CONVERTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC multiplexer Selection Register
+VE_ADMUX:
+ .dw $ff05
+ .db "ADMUX",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADMUX
+XT_ADMUX:
+ .dw PFA_DOVARIABLE
+PFA_ADMUX:
+ .dw 124
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register
+VE_ADCSRA:
+ .dw $ff06
+ .db "ADCSRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRA
+XT_ADCSRA:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRA:
+ .dw 122
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register Bytes
+VE_ADC:
+ .dw $ff03
+ .db "ADC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADC
+XT_ADC:
+ .dw PFA_DOVARIABLE
+PFA_ADC:
+ .dw 120
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Control and Status Register B
+VE_ADCSRB:
+ .dw $ff06
+ .db "ADCSRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRB
+XT_ADCSRB:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRB:
+ .dw 123
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 1
+VE_DIDR0:
+ .dw $ff05
+ .db "DIDR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR0
+XT_DIDR0:
+ .dw PFA_DOVARIABLE
+PFA_DIDR0:
+ .dw 126
+
+.endif
+.if WANT_ANALOG_COMPARATOR == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Control And Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw 80
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_DIDR1:
+ .dw $ff05
+ .db "DIDR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR1
+XT_DIDR1:
+ .dw PFA_DOVARIABLE
+PFA_DIDR1:
+ .dw 127
+
+.endif
+.if WANT_PLL == 1
+; ( -- addr ) System Constant
+; R( -- )
+; PLL Status and Control register
+VE_PLLCSR:
+ .dw $ff06
+ .db "PLLCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PLLCSR
+XT_PLLCSR:
+ .dw PFA_DOVARIABLE
+PFA_PLLCSR:
+ .dw 73
+
+.endif
diff --git a/amforth-6.5/avr8/devices/at90usb1287/device.py b/amforth-6.5/avr8/devices/at90usb1287/device.py
new file mode 100644
index 0000000..bae6439
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90usb1287/device.py
@@ -0,0 +1,625 @@
+# Generated Automatically
+
+# Partname AT90USB1287
+
+MCUREGS = {
+# Interrupt Vectors
+ 'INT0Addr' : '#2', # External Interrupt Request 0
+ 'INT1Addr' : '#4', # External Interrupt Request 1
+ 'INT2Addr' : '#6', # External Interrupt Request 2
+ 'INT3Addr' : '#8', # External Interrupt Request 3
+ 'INT4Addr' : '#10', # External Interrupt Request 4
+ 'INT5Addr' : '#12', # External Interrupt Request 5
+ 'INT6Addr' : '#14', # External Interrupt Request 6
+ 'INT7Addr' : '#16', # External Interrupt Request 7
+ 'PCINT0Addr' : '#18', # Pin Change Interrupt Request 0
+ 'USB_GENAddr' : '#20', # USB General Interrupt Request
+ 'USB_COMAddr' : '#22', # USB Endpoint/Pipe Interrupt Communication Request
+ 'WDTAddr' : '#24', # Watchdog Time-out Interrupt
+ 'TIMER2_COMPAAddr' : '#26', # Timer/Counter2 Compare Match A
+ 'TIMER2_COMPBAddr' : '#28', # Timer/Counter2 Compare Match B
+ 'TIMER2_OVFAddr' : '#30', # Timer/Counter2 Overflow
+ 'TIMER1_CAPTAddr' : '#32', # Timer/Counter1 Capture Event
+ 'TIMER1_COMPAAddr' : '#34', # Timer/Counter1 Compare Match A
+ 'TIMER1_COMPBAddr' : '#36', # Timer/Counter1 Compare Match B
+ 'TIMER1_COMPCAddr' : '#38', # Timer/Counter1 Compare Match C
+ 'TIMER1_OVFAddr' : '#40', # Timer/Counter1 Overflow
+ 'TIMER0_COMPAAddr' : '#42', # Timer/Counter0 Compare Match A
+ 'TIMER0_COMPBAddr' : '#44', # Timer/Counter0 Compare Match B
+ 'TIMER0_OVFAddr' : '#46', # Timer/Counter0 Overflow
+ 'SPI_STCAddr' : '#48', # SPI Serial Transfer Complete
+ 'USART1_RXAddr' : '#50', # USART1, Rx Complete
+ 'USART1_UDREAddr' : '#52', # USART1 Data register Empty
+ 'USART1_TXAddr' : '#54', # USART1, Tx Complete
+ 'ANALOG_COMPAddr' : '#56', # Analog Comparator
+ 'ADCAddr' : '#58', # ADC Conversion Complete
+ 'EE_READYAddr' : '#60', # EEPROM Ready
+ 'TIMER3_CAPTAddr' : '#62', # Timer/Counter3 Capture Event
+ 'TIMER3_COMPAAddr' : '#64', # Timer/Counter3 Compare Match A
+ 'TIMER3_COMPBAddr' : '#66', # Timer/Counter3 Compare Match B
+ 'TIMER3_COMPCAddr' : '#68', # Timer/Counter3 Compare Match C
+ 'TIMER3_OVFAddr' : '#70', # Timer/Counter3 Overflow
+ 'TWIAddr' : '#72', # 2-wire Serial Interface
+ 'SPM_READYAddr' : '#74', # Store Program Memory Read
+
+# Module WATCHDOG
+ 'WDTCSR' : '$60', # Watchdog Timer Control Registe
+ 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
+ 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
+ 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
+ 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
+ 'WDTCSR_WDE': '$8', # Watch Dog Enable
+
+# Module PORTA
+ 'PORTA' : '$22', # Port A Data Register
+ 'DDRA' : '$21', # Port A Data Direction Register
+ 'PINA' : '$20', # Port A Input Pins
+
+# Module PORTB
+ 'PORTB' : '$25', # Port B Data Register
+ 'DDRB' : '$24', # Port B Data Direction Register
+ 'PINB' : '$23', # Port B Input Pins
+
+# Module PORTC
+ 'PORTC' : '$28', # Port C Data Register
+ 'DDRC' : '$27', # Port C Data Direction Register
+ 'PINC' : '$26', # Port C Input Pins
+
+# Module PORTD
+ 'PORTD' : '$2b', # Port D Data Register
+ 'DDRD' : '$2a', # Port D Data Direction Register
+ 'PIND' : '$29', # Port D Input Pins
+
+# Module PORTE
+ 'PORTE' : '$2e', # Data Register, Port E
+ 'DDRE' : '$2d', # Data Direction Register, Port
+ 'PINE' : '$2c', # Input Pins, Port E
+
+# Module PORTF
+ 'PORTF' : '$31', # Data Register, Port F
+ 'DDRF' : '$30', # Data Direction Register, Port
+ 'PINF' : '$2f', # Input Pins, Port F
+
+# Module CPU
+ 'SREG' : '$5f', # Status Register
+ 'SREG_I': '$80', # Global Interrupt Enable
+ 'SREG_T': '$40', # Bit Copy Storage
+ 'SREG_H': '$20', # Half Carry Flag
+ 'SREG_S': '$10', # Sign Bit
+ 'SREG_V': '$8', # Two's Complement Overflow Flag
+ 'SREG_N': '$4', # Negative Flag
+ 'SREG_Z': '$2', # Zero Flag
+ 'SREG_C': '$1', # Carry Flag
+ 'SP' : '$5d', # Stack Pointer
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_JTD': '$80', # JTAG Interface Disable
+ 'MCUCR_PUD': '$10', # Pull-up disable
+ 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
+ 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+ 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
+ 'MCUSR_BORF': '$4', # Brown-out Reset Flag
+ 'MCUSR_EXTRF': '$2', # External Reset Flag
+ 'MCUSR_PORF': '$1', # Power-on reset flag
+ 'XMCRA' : '$74', # External Memory Control Regist
+ 'XMCRA_SRE': '$80', # External SRAM Enable
+ 'XMCRA_SRL': '$70', # Wait state page limit
+ 'XMCRA_SRW1': '$c', # Wait state select bit upper pa
+ 'XMCRA_SRW0': '$3', # Wait state select bit lower pa
+ 'XMCRB' : '$75', # External Memory Control Regist
+ 'XMCRB_XMBK': '$80', # External Memory Bus Keeper Ena
+ 'XMCRB_XMM': '$7', # External Memory High Mask
+ 'OSCCAL' : '$66', # Oscillator Calibration Value
+ 'CLKPR' : '$61', #
+ 'CLKPR_CLKPCE': '$80', #
+ 'CLKPR_CLKPS': '$f', #
+ 'SMCR' : '$53', # Sleep Mode Control Register
+ 'SMCR_SM': '$e', # Sleep Mode Select bits
+ 'SMCR_SE': '$1', # Sleep Enable
+ 'EIND' : '$5c', # Extended Indirect Register
+ 'RAMPZ' : '$5b', # RAM Page Z Select Register
+ 'GPIOR2' : '$4b', # General Purpose IO Register 2
+ 'GPIOR2_GPIOR': '$ff', # General Purpose IO Register 2
+ 'GPIOR1' : '$4a', # General Purpose IO Register 1
+ 'GPIOR1_GPIOR': '$ff', # General Purpose IO Register 1
+ 'GPIOR0' : '$3e', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR07': '$80', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR06': '$40', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR05': '$20', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR04': '$10', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR03': '$8', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR02': '$4', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR01': '$2', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR00': '$1', # General Purpose IO Register 0
+ 'PRR1' : '$65', # Power Reduction Register1
+ 'PRR1_PRUSB': '$80', # Power Reduction USB
+ 'PRR1_PRTIM3': '$8', # Power Reduction Timer/Counter3
+ 'PRR1_PRUSART1': '$1', # Power Reduction USART1
+ 'PRR0' : '$64', # Power Reduction Register0
+ 'PRR0_PRTWI': '$80', # Power Reduction TWI
+ 'PRR0_PRTIM2': '$40', # Power Reduction Timer/Counter2
+ 'PRR0_PRTIM0': '$20', # Power Reduction Timer/Counter0
+ 'PRR0_PRTIM1': '$8', # Power Reduction Timer/Counter1
+ 'PRR0_PRSPI': '$4', # Power Reduction Serial Periphe
+ 'PRR0_PRADC': '$1', # Power Reduction ADC
+
+# Module TWI
+ 'TWAMR' : '$bd', # TWI (Slave) Address Mask Regis
+ 'TWAMR_TWAM': '$fe', #
+ 'TWBR' : '$b8', # TWI Bit Rate register
+ 'TWCR' : '$bc', # TWI Control Register
+ 'TWCR_TWINT': '$80', # TWI Interrupt Flag
+ 'TWCR_TWEA': '$40', # TWI Enable Acknowledge Bit
+ 'TWCR_TWSTA': '$20', # TWI Start Condition Bit
+ 'TWCR_TWSTO': '$10', # TWI Stop Condition Bit
+ 'TWCR_TWWC': '$8', # TWI Write Collition Flag
+ 'TWCR_TWEN': '$4', # TWI Enable Bit
+ 'TWCR_TWIE': '$1', # TWI Interrupt Enable
+ 'TWSR' : '$b9', # TWI Status Register
+ 'TWSR_TWS': '$f8', # TWI Status
+ 'TWSR_TWPS': '$3', # TWI Prescaler
+ 'TWDR' : '$bb', # TWI Data register
+ 'TWAR' : '$ba', # TWI (Slave) Address register
+ 'TWAR_TWA': '$fe', # TWI (Slave) Address register B
+ 'TWAR_TWGCE': '$1', # TWI General Call Recognition E
+
+# Module SPI
+ 'SPCR' : '$4c', # SPI Control Register
+ 'SPCR_SPIE': '$80', # SPI Interrupt Enable
+ 'SPCR_SPE': '$40', # SPI Enable
+ 'SPCR_DORD': '$20', # Data Order
+ 'SPCR_MSTR': '$10', # Master/Slave Select
+ 'SPCR_CPOL': '$8', # Clock polarity
+ 'SPCR_CPHA': '$4', # Clock Phase
+ 'SPCR_SPR': '$3', # SPI Clock Rate Selects
+ 'SPSR' : '$4d', # SPI Status Register
+ 'SPSR_SPIF': '$80', # SPI Interrupt Flag
+ 'SPSR_WCOL': '$40', # Write Collision Flag
+ 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
+ 'SPDR' : '$4e', # SPI Data Register
+
+# Module USART1
+ 'UDR1' : '$ce', # USART I/O Data Register
+ 'UCSR1A' : '$c8', # USART Control and Status Regis
+ 'UCSR1A_RXC1': '$80', # USART Receive Complete
+ 'UCSR1A_TXC1': '$40', # USART Transmitt Complete
+ 'UCSR1A_UDRE1': '$20', # USART Data Register Empty
+ 'UCSR1A_FE1': '$10', # Framing Error
+ 'UCSR1A_DOR1': '$8', # Data overRun
+ 'UCSR1A_UPE1': '$4', # Parity Error
+ 'UCSR1A_U2X1': '$2', # Double the USART transmission
+ 'UCSR1A_MPCM1': '$1', # Multi-processor Communication
+ 'UCSR1B' : '$c9', # USART Control and Status Regis
+ 'UCSR1B_RXCIE1': '$80', # RX Complete Interrupt Enable
+ 'UCSR1B_TXCIE1': '$40', # TX Complete Interrupt Enable
+ 'UCSR1B_UDRIE1': '$20', # USART Data register Empty Inte
+ 'UCSR1B_RXEN1': '$10', # Receiver Enable
+ 'UCSR1B_TXEN1': '$8', # Transmitter Enable
+ 'UCSR1B_UCSZ12': '$4', # Character Size
+ 'UCSR1B_RXB81': '$2', # Receive Data Bit 8
+ 'UCSR1B_TXB81': '$1', # Transmit Data Bit 8
+ 'UCSR1C' : '$ca', # USART Control and Status Regis
+ 'UCSR1C_UMSEL1': '$c0', # USART Mode Select
+ 'UCSR1C_UPM1': '$30', # Parity Mode Bits
+ 'UCSR1C_USBS1': '$8', # Stop Bit Select
+ 'UCSR1C_UCSZ1': '$6', # Character Size
+ 'UCSR1C_UCPOL1': '$1', # Clock Polarity
+ 'UBRR1' : '$cc', # USART Baud Rate Register Byte
+
+# Module USB_DEVICE
+ 'UEINT' : '$f4', #
+ 'UEBCHX' : '$f3', #
+ 'UEBCLX' : '$f2', #
+ 'UEDATX' : '$f1', #
+ 'UEIENX' : '$f0', #
+ 'UEIENX_FLERRE': '$80', #
+ 'UEIENX_NAKINE': '$40', #
+ 'UEIENX_NAKOUTE': '$10', #
+ 'UEIENX_RXSTPE': '$8', #
+ 'UEIENX_RXOUTE': '$4', #
+ 'UEIENX_STALLEDE': '$2', #
+ 'UEIENX_TXINE': '$1', #
+ 'UESTA1X' : '$ef', #
+ 'UESTA1X_CTRLDIR': '$4', #
+ 'UESTA1X_CURRBK': '$3', #
+ 'UESTA0X' : '$ee', #
+ 'UESTA0X_CFGOK': '$80', #
+ 'UESTA0X_OVERFI': '$40', #
+ 'UESTA0X_UNDERFI': '$20', #
+ 'UESTA0X_DTSEQ': '$c', #
+ 'UESTA0X_NBUSYBK': '$3', #
+ 'UECFG1X' : '$ed', #
+ 'UECFG1X_EPSIZE': '$70', #
+ 'UECFG1X_EPBK': '$c', #
+ 'UECFG1X_ALLOC': '$2', #
+ 'UECFG0X' : '$ec', #
+ 'UECFG0X_EPTYPE': '$c0', #
+ 'UECFG0X_EPDIR': '$1', #
+ 'UECONX' : '$eb', #
+ 'UECONX_STALLRQ': '$20', #
+ 'UECONX_STALLRQC': '$10', #
+ 'UECONX_RSTDT': '$8', #
+ 'UECONX_EPEN': '$1', #
+ 'UERST' : '$ea', #
+ 'UERST_EPRST': '$7f', #
+ 'UENUM' : '$e9', #
+ 'UEINTX' : '$e8', #
+ 'UEINTX_FIFOCON': '$80', #
+ 'UEINTX_NAKINI': '$40', #
+ 'UEINTX_RWAL': '$20', #
+ 'UEINTX_NAKOUTI': '$10', #
+ 'UEINTX_RXSTPI': '$8', #
+ 'UEINTX_RXOUTI': '$4', #
+ 'UEINTX_STALLEDI': '$2', #
+ 'UEINTX_TXINI': '$1', #
+ 'UDMFN' : '$e6', #
+ 'UDMFN_FNCERR': '$10', #
+ 'UDFNUM' : '$e4', #
+ 'UDADDR' : '$e3', #
+ 'UDADDR_ADDEN': '$80', #
+ 'UDADDR_UADD': '$7f', #
+ 'UDIEN' : '$e2', #
+ 'UDIEN_UPRSME': '$40', #
+ 'UDIEN_EORSME': '$20', #
+ 'UDIEN_WAKEUPE': '$10', #
+ 'UDIEN_EORSTE': '$8', #
+ 'UDIEN_SOFE': '$4', #
+ 'UDIEN_SUSPE': '$1', #
+ 'UDINT' : '$e1', #
+ 'UDINT_UPRSMI': '$40', #
+ 'UDINT_EORSMI': '$20', #
+ 'UDINT_WAKEUPI': '$10', #
+ 'UDINT_EORSTI': '$8', #
+ 'UDINT_SOFI': '$4', #
+ 'UDINT_SUSPI': '$1', #
+ 'UDCON' : '$e0', #
+ 'UDCON_LSM': '$4', #
+ 'UDCON_RMWKUP': '$2', #
+ 'UDCON_DETACH': '$1', #
+
+# Module USB_GLOBAL
+ 'OTGINT' : '$df', #
+ 'OTGINT_STOI': '$20', #
+ 'OTGINT_HNPERRI': '$10', #
+ 'OTGINT_ROLEEXI': '$8', #
+ 'OTGINT_BCERRI': '$4', #
+ 'OTGINT_VBERRI': '$2', #
+ 'OTGINT_SRPI': '$1', #
+ 'OTGIEN' : '$de', #
+ 'OTGIEN_STOE': '$20', #
+ 'OTGIEN_HNPERRE': '$10', #
+ 'OTGIEN_ROLEEXE': '$8', #
+ 'OTGIEN_BCERRE': '$4', #
+ 'OTGIEN_VBERRE': '$2', #
+ 'OTGIEN_SRPE': '$1', #
+ 'OTGCON' : '$dd', #
+ 'OTGCON_HNPREQ': '$20', #
+ 'OTGCON_SRPREQ': '$10', #
+ 'OTGCON_SRPSEL': '$8', #
+ 'OTGCON_VBUSHWC': '$4', #
+ 'OTGCON_VBUSREQ': '$2', #
+ 'OTGCON_VBUSRQC': '$1', #
+ 'OTGTCON' : '$f9', #
+ 'OTGTCON_OTGTCON_7': '$80', #
+ 'OTGTCON_PAGE': '$60', #
+ 'OTGTCON_VALUE_2': '$7', #
+ 'USBINT' : '$da', #
+ 'USBINT_IDTI': '$2', #
+ 'USBINT_VBUSTI': '$1', #
+ 'USBSTA' : '$d9', #
+ 'USBSTA_SPEED': '$8', #
+ 'USBSTA_ID': '$2', #
+ 'USBSTA_VBUS': '$1', #
+ 'USBCON' : '$d8', # USB General Control Register
+ 'USBCON_USBE': '$80', #
+ 'USBCON_HOST': '$40', #
+ 'USBCON_FRZCLK': '$20', #
+ 'USBCON_OTGPADE': '$10', #
+ 'USBCON_IDTE': '$2', #
+ 'USBCON_VBUSTE': '$1', #
+ 'UHWCON' : '$d7', # USB Hardware Configuration Reg
+ 'UHWCON_UIMOD': '$80', #
+ 'UHWCON_UIDE': '$40', #
+ 'UHWCON_UVCONE': '$10', #
+ 'UHWCON_UVREGE': '$1', #
+
+# Module USB_HOST
+ 'UPERRX' : '$f5', #
+ 'UPERRX_COUNTER': '$60', #
+ 'UPERRX_CRC16': '$10', #
+ 'UPERRX_TIMEOUT': '$8', #
+ 'UPERRX_PID': '$4', #
+ 'UPERRX_DATAPID': '$2', #
+ 'UPERRX_DATATGL': '$1', #
+ 'UPINT' : '$f8', #
+ 'UPBCHX' : '$f7', #
+ 'UPBCLX' : '$f6', #
+ 'UPDATX' : '$af', #
+ 'UPIENX' : '$ae', #
+ 'UPIENX_FLERRE': '$80', #
+ 'UPIENX_NAKEDE': '$40', #
+ 'UPIENX_PERRE': '$10', #
+ 'UPIENX_TXSTPE': '$8', #
+ 'UPIENX_TXOUTE': '$4', #
+ 'UPIENX_RXSTALLE': '$2', #
+ 'UPIENX_RXINE': '$1', #
+ 'UPCFG2X' : '$ad', #
+ 'UPSTAX' : '$ac', #
+ 'UPSTAX_CFGOK': '$80', #
+ 'UPSTAX_OVERFI': '$40', #
+ 'UPSTAX_UNDERFI': '$20', #
+ 'UPSTAX_DTSEQ': '$c', #
+ 'UPSTAX_NBUSYK': '$3', #
+ 'UPCFG1X' : '$ab', #
+ 'UPCFG1X_PSIZE': '$70', #
+ 'UPCFG1X_PBK': '$c', #
+ 'UPCFG1X_ALLOC': '$2', #
+ 'UPCFG0X' : '$aa', #
+ 'UPCFG0X_PTYPE': '$c0', #
+ 'UPCFG0X_PTOKEN': '$30', #
+ 'UPCFG0X_PEPNUM': '$f', #
+ 'UPCONX' : '$a9', #
+ 'UPCONX_PFREEZE': '$40', #
+ 'UPCONX_INMODE': '$20', #
+ 'UPCONX_RSTDT': '$8', #
+ 'UPCONX_PEN': '$1', #
+ 'UPRST' : '$a8', #
+ 'UPRST_PRST': '$7f', #
+ 'UPNUM' : '$a7', #
+ 'UPINTX' : '$a6', #
+ 'UPINTX_FIFOCON': '$80', #
+ 'UPINTX_NAKEDI': '$40', #
+ 'UPINTX_RWAL': '$20', #
+ 'UPINTX_PERRI': '$10', #
+ 'UPINTX_TXSTPI': '$8', #
+ 'UPINTX_TXOUTI': '$4', #
+ 'UPINTX_RXSTALLI': '$2', #
+ 'UPINTX_RXINI': '$1', #
+ 'UPINRQX' : '$a5', #
+ 'UHFLEN' : '$a4', #
+ 'UHFNUM' : '$a2', #
+ 'UHADDR' : '$a1', #
+ 'UHIEN' : '$a0', #
+ 'UHIEN_HWUPE': '$40', #
+ 'UHIEN_HSOFE': '$20', #
+ 'UHIEN_RXRSME': '$10', #
+ 'UHIEN_RSMEDE': '$8', #
+ 'UHIEN_RSTE': '$4', #
+ 'UHIEN_DDISCE': '$2', #
+ 'UHIEN_DCONNE': '$1', #
+ 'UHINT' : '$9f', #
+ 'UHINT_UHUPI': '$40', #
+ 'UHINT_HSOFI': '$20', #
+ 'UHINT_RXRSMI': '$10', #
+ 'UHINT_RSMEDI': '$8', #
+ 'UHINT_RSTI': '$4', #
+ 'UHINT_DDISCI': '$2', #
+ 'UHINT_DCONNI': '$1', #
+ 'UHCON' : '$9e', #
+ 'UHCON_RESUME': '$4', #
+ 'UHCON_RESET': '$2', #
+ 'UHCON_SOFEN': '$1', #
+
+# Module BOOT_LOAD
+ 'SPMCSR' : '$57', # Store Program Memory Control R
+ 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
+ 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
+ 'SPMCSR_SIGRD': '$20', # Signature Row Read
+ 'SPMCSR_RWWSRE': '$10', # Read While Write section read
+ 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
+ 'SPMCSR_PGWRT': '$4', # Page Write
+ 'SPMCSR_PGERS': '$2', # Page Erase
+ 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
+
+# Module EEPROM
+ 'EEAR' : '$41', # EEPROM Address Register Low By
+ 'EEDR' : '$40', # EEPROM Data Register
+ 'EECR' : '$3f', # EEPROM Control Register
+ 'EECR_EEPM': '$30', # EEPROM Programming Mode Bits
+ 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
+ 'EECR_EEMPE': '$4', # EEPROM Master Write Enable
+ 'EECR_EEPE': '$2', # EEPROM Write Enable
+ 'EECR_EERE': '$1', # EEPROM Read Enable
+
+# Module TIMER_COUNTER_0
+ 'OCR0B' : '$48', # Timer/Counter0 Output Compare
+ 'OCR0A' : '$47', # Timer/Counter0 Output Compare
+ 'TCNT0' : '$46', # Timer/Counter0
+ 'TCCR0B' : '$45', # Timer/Counter Control Register
+ 'TCCR0B_FOC0A': '$80', # Force Output Compare A
+ 'TCCR0B_FOC0B': '$40', # Force Output Compare B
+ 'TCCR0B_WGM02': '$8', #
+ 'TCCR0B_CS0': '$7', # Clock Select
+ 'TCCR0A' : '$44', # Timer/Counter Control Registe
+ 'TCCR0A_COM0A': '$c0', # Compare Output Mode, Phase Cor
+ 'TCCR0A_COM0B': '$30', # Compare Output Mode, Fast PWm
+ 'TCCR0A_WGM0': '$3', # Waveform Generation Mode
+ 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
+ 'TIMSK0_OCIE0B': '$4', # Timer/Counter0 Output Compare
+ 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
+ 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
+ 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
+ 'TIFR0_OCF0B': '$4', # Timer/Counter0 Output Compare
+ 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
+ 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSRSYNC': '$1', # Prescaler Reset Timer/Counter1
+
+# Module TIMER_COUNTER_2
+ 'TIMSK2' : '$70', # Timer/Counter Interrupt Mask r
+ 'TIMSK2_OCIE2B': '$4', # Timer/Counter2 Output Compare
+ 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
+ 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
+ 'TIFR2' : '$37', # Timer/Counter Interrupt Flag R
+ 'TIFR2_OCF2B': '$4', # Output Compare Flag 2B
+ 'TIFR2_OCF2A': '$2', # Output Compare Flag 2A
+ 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
+ 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
+ 'TCCR2A_COM2A': '$c0', # Compare Output Mode bits
+ 'TCCR2A_COM2B': '$30', # Compare Output Mode bits
+ 'TCCR2A_WGM2': '$3', # Waveform Genration Mode
+ 'TCCR2B' : '$b1', # Timer/Counter2 Control Registe
+ 'TCCR2B_FOC2A': '$80', # Force Output Compare A
+ 'TCCR2B_FOC2B': '$40', # Force Output Compare B
+ 'TCCR2B_WGM22': '$8', # Waveform Generation Mode
+ 'TCCR2B_CS2': '$7', # Clock Select bits
+ 'TCNT2' : '$b2', # Timer/Counter2
+ 'OCR2B' : '$b4', # Timer/Counter2 Output Compare
+ 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
+ 'ASSR' : '$b6', # Asynchronous Status Register
+ 'ASSR_EXCLK': '$40', # Enable External Clock Input
+ 'ASSR_AS2': '$20', # Asynchronous Timer/Counter2
+ 'ASSR_TCN2UB': '$10', # Timer/Counter2 Update Busy
+ 'ASSR_OCR2AUB': '$8', # Output Compare Register2 Updat
+ 'ASSR_OCR2BUB': '$4', # Output Compare Register 2 Upda
+ 'ASSR_TCR2AUB': '$2', # Timer/Counter Control Register
+ 'ASSR_TCR2BUB': '$1', # Timer/Counter Control Register
+ 'GTCCR' : '$43', # General Timer Counter Control
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSRASY': '$2', # Prescaler Reset Timer/Counter2
+
+# Module TIMER_COUNTER_3
+ 'TCCR3A' : '$90', # Timer/Counter3 Control Registe
+ 'TCCR3A_COM3A': '$c0', # Compare Output Mode 1A, bits
+ 'TCCR3A_COM3B': '$30', # Compare Output Mode 3B, bits
+ 'TCCR3A_COM3C': '$c', # Compare Output Mode 3C, bits
+ 'TCCR3A_WGM3': '$3', # Waveform Generation Mode
+ 'TCCR3B' : '$91', # Timer/Counter3 Control Registe
+ 'TCCR3B_ICNC3': '$80', # Input Capture 3 Noise Canceler
+ 'TCCR3B_ICES3': '$40', # Input Capture 3 Edge Select
+ 'TCCR3B_WGM3': '$18', # Waveform Generation Mode
+ 'TCCR3B_CS3': '$7', # Prescaler source of Timer/Coun
+ 'TCCR3C' : '$92', # Timer/Counter 3 Control Regist
+ 'TCCR3C_FOC3A': '$80', # Force Output Compare 3A
+ 'TCCR3C_FOC3B': '$40', # Force Output Compare 3B
+ 'TCCR3C_FOC3C': '$20', # Force Output Compare 3C
+ 'TCNT3' : '$94', # Timer/Counter3 Bytes
+ 'OCR3A' : '$98', # Timer/Counter3 Output Compare
+ 'OCR3B' : '$9a', # Timer/Counter3 Output Compare
+ 'OCR3C' : '$9c', # Timer/Counter3 Output Compare
+ 'ICR3' : '$96', # Timer/Counter3 Input Capture R
+ 'TIMSK3' : '$71', # Timer/Counter3 Interrupt Mask
+ 'TIMSK3_ICIE3': '$20', # Timer/Counter3 Input Capture I
+ 'TIMSK3_OCIE3C': '$8', # Timer/Counter3 Output Compare
+ 'TIMSK3_OCIE3B': '$4', # Timer/Counter3 Output Compare
+ 'TIMSK3_OCIE3A': '$2', # Timer/Counter3 Output Compare
+ 'TIMSK3_TOIE3': '$1', # Timer/Counter3 Overflow Interr
+ 'TIFR3' : '$38', # Timer/Counter3 Interrupt Flag
+ 'TIFR3_ICF3': '$20', # Input Capture Flag 3
+ 'TIFR3_OCF3C': '$8', # Output Compare Flag 3C
+ 'TIFR3_OCF3B': '$4', # Output Compare Flag 3B
+ 'TIFR3_OCF3A': '$2', # Output Compare Flag 3A
+ 'TIFR3_TOV3': '$1', # Timer/Counter3 Overflow Flag
+
+# Module TIMER_COUNTER_1
+ 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
+ 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
+ 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
+ 'TCCR1A_COM1C': '$c', # Compare Output Mode 1C, bits
+ 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
+ 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
+ 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
+ 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
+ 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
+ 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
+ 'TCCR1C' : '$82', # Timer/Counter 1 Control Regist
+ 'TCCR1C_FOC1A': '$80', # Force Output Compare 1A
+ 'TCCR1C_FOC1B': '$40', # Force Output Compare 1B
+ 'TCCR1C_FOC1C': '$20', # Force Output Compare 1C
+ 'TCNT1' : '$84', # Timer/Counter1 Bytes
+ 'OCR1A' : '$88', # Timer/Counter1 Output Compare
+ 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
+ 'OCR1C' : '$8c', # Timer/Counter1 Output Compare
+ 'ICR1' : '$86', # Timer/Counter1 Input Capture R
+ 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
+ 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
+ 'TIMSK1_OCIE1C': '$8', # Timer/Counter1 Output Compare
+ 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
+ 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
+ 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
+ 'TIFR1' : '$36', # Timer/Counter1 Interrupt Flag
+ 'TIFR1_ICF1': '$20', # Input Capture Flag 1
+ 'TIFR1_OCF1C': '$8', # Output Compare Flag 1C
+ 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
+ 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
+ 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
+
+# Module JTAG
+ 'OCDR' : '$51', # On-Chip Debug Related Register
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_JTD': '$80', # JTAG Interface Disable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+
+# Module EXTERNAL_INTERRUPT
+ 'EICRA' : '$69', # External Interrupt Control Reg
+ 'EICRA_ISC3': '$c0', # External Interrupt Sense Contr
+ 'EICRA_ISC2': '$30', # External Interrupt Sense Contr
+ 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
+ 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
+ 'EICRB' : '$6a', # External Interrupt Control Reg
+ 'EICRB_ISC7': '$c0', # External Interrupt 7-4 Sense C
+ 'EICRB_ISC6': '$30', # External Interrupt 7-4 Sense C
+ 'EICRB_ISC5': '$c', # External Interrupt 7-4 Sense C
+ 'EICRB_ISC4': '$3', # External Interrupt 7-4 Sense C
+ 'EIMSK' : '$3d', # External Interrupt Mask Regist
+ 'EIMSK_INT': '$ff', # External Interrupt Request 7 E
+ 'EIFR' : '$3c', # External Interrupt Flag Regist
+ 'EIFR_INTF': '$ff', # External Interrupt Flags
+ 'PCMSK0' : '$6b', # Pin Change Mask Register 0
+ 'PCIFR' : '$3b', # Pin Change Interrupt Flag Regi
+ 'PCIFR_PCIF0': '$1', # Pin Change Interrupt Flag 0
+ 'PCICR' : '$68', # Pin Change Interrupt Control R
+ 'PCICR_PCIE0': '$1', # Pin Change Interrupt Enable 0
+
+# Module AD_CONVERTER
+ 'ADMUX' : '$7c', # The ADC multiplexer Selection
+ 'ADMUX_REFS': '$c0', # Reference Selection Bits
+ 'ADMUX_ADLAR': '$20', # Left Adjust Result
+ 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
+ 'ADCSRA' : '$7a', # The ADC Control and Status reg
+ 'ADCSRA_ADEN': '$80', # ADC Enable
+ 'ADCSRA_ADSC': '$40', # ADC Start Conversion
+ 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
+ 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
+ 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
+ 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
+ 'ADC' : '$78', # ADC Data Register Bytes
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ADHSM': '$80', # ADC High Speed Mode
+ 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Sources
+ 'DIDR0' : '$7e', # Digital Input Disable Register
+ 'DIDR0_ADC7D': '$80', # ADC7 Digital input Disable
+ 'DIDR0_ADC6D': '$40', # ADC6 Digital input Disable
+ 'DIDR0_ADC5D': '$20', # ADC5 Digital input Disable
+ 'DIDR0_ADC4D': '$10', # ADC4 Digital input Disable
+ 'DIDR0_ADC3D': '$8', # ADC3 Digital input Disable
+ 'DIDR0_ADC2D': '$4', # ADC2 Digital input Disable
+ 'DIDR0_ADC1D': '$2', # ADC1 Digital input Disable
+ 'DIDR0_ADC0D': '$1', # ADC0 Digital input Disable
+
+# Module ANALOG_COMPARATOR
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
+ 'ACSR' : '$50', # Analog Comparator Control And
+ 'ACSR_ACD': '$80', # Analog Comparator Disable
+ 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
+ 'ACSR_ACO': '$20', # Analog Compare Output
+ 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
+ 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
+ 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
+ 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
+ 'DIDR1' : '$7f', #
+ 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
+ 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
+
+# Module PLL
+ 'PLLCSR' : '$49', # PLL Status and Control registe
+ 'PLLCSR_PLLP': '$1c', # PLL prescaler Bits
+ 'PLLCSR_PLLE': '$2', # PLL Enable Bit
+ 'PLLCSR_PLOCK': '$1', # PLL Lock Status Bit
+
+ '__amforth_dummy':'0'
+}
diff --git a/amforth-6.5/avr8/devices/at90usb1287/words/no-jtag.asm b/amforth-6.5/avr8/devices/at90usb1287/words/no-jtag.asm
new file mode 100644
index 0000000..352a4bb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90usb1287/words/no-jtag.asm
@@ -0,0 +1,14 @@
+; ( -- )
+; ( -- )
+; MCU
+; disable jtag at runtime
+VE_NOJTAG:
+ .dw $FF05
+ .db "-jtag",0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOJTAG
+XT_NOJTAG:
+ .dw PFA_NOJTAG
+PFA_NOJTAG:
+
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/at90usb1287/words/no-wdt.asm b/amforth-6.5/avr8/devices/at90usb1287/words/no-wdt.asm
new file mode 100644
index 0000000..ff6ddd1
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90usb1287/words/no-wdt.asm
@@ -0,0 +1,34 @@
+; ( -- )
+; MCU
+; disable watch dog timer at runtime
+VE_NOWDT:
+ .dw $ff04
+ .db "-wdt"
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOWDT
+XT_NOWDT:
+ .dw PFA_NOWDT
+PFA_NOWDT:
+
+ in temp1,SREG
+ push temp1
+ ; Turn always off global interrupt.
+ cli
+ ; Reset Watchdog Timer
+ wdr
+ ; Clear WDRF in MCUSR
+ in temp1, MCUSR
+ andi temp1, (0xff & (0<<WDRF))
+ out MCUSR, temp1
+ ; Write logical one to WDCE and WDE
+ ; Keep old prescaler setting to prevent unintentional time-out
+ in_ temp1, WDTCSR
+ ori temp1, (1<<WDCE) | (1<<WDE)
+ out_ WDTCSR, temp1
+ ; Turn off WDT
+ ldi temp1, (0<<WDE)
+ out_ WDTCSR, temp1
+ ; restore status register
+ pop temp1
+ out SREG,temp1
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/at90usb1287/words/sleep.asm b/amforth-6.5/avr8/devices/at90usb1287/words/sleep.asm
new file mode 100644
index 0000000..256249c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90usb1287/words/sleep.asm
@@ -0,0 +1,19 @@
+; ( mode -- )
+; MCU
+; put the controller into the specified sleep mode
+VE_SLEEP:
+ .dw $ff05
+ .db "sleep", 0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_SLEEP
+XT_SLEEP:
+ .dw PFA_SLEEP
+PFA_SLEEP:
+ andi tosl, 7 ; leave only legal mode bits
+ lsl tosl ; move to correct location (bits 3-1)
+ ori tosl, 1 ; set the SE bit
+ out_ SMCR, tosl ; set the sleep config
+ sleep ; nighty-night
+ out_ SMCR, zerol ; 0 protects against accidental sleeps
+ loadtos ; pop argument from stack
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/at90usb162/at90usb162.frt b/amforth-6.5/avr8/devices/at90usb162/at90usb162.frt
new file mode 100644
index 0000000..a17ffca
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90usb162/at90usb162.frt
@@ -0,0 +1,367 @@
+\ Partname: AT90USB162
+\ generated automatically
+
+\ PORTB
+&37 constant PORTB \ Port B Data Register
+&36 constant DDRB \ Port B Data Direction Register
+&35 constant PINB \ Port B Input Pins
+\ PORTD
+&43 constant PORTD \ Port D Data Register
+&42 constant DDRD \ Port D Data Direction Register
+&41 constant PIND \ Port D Input Pins
+\ SPI
+&76 constant SPCR \ SPI Control Register
+ $80 constant SPCR_SPIE \ SPI Interrupt Enable
+ $40 constant SPCR_SPE \ SPI Enable
+ $20 constant SPCR_DORD \ Data Order
+ $10 constant SPCR_MSTR \ Master/Slave Select
+ $08 constant SPCR_CPOL \ Clock polarity
+ $04 constant SPCR_CPHA \ Clock Phase
+ $03 constant SPCR_SPR \ SPI Clock Rate Selects
+&77 constant SPSR \ SPI Status Register
+ $80 constant SPSR_SPIF \ SPI Interrupt Flag
+ $40 constant SPSR_WCOL \ Write Collision Flag
+ $01 constant SPSR_SPI2X \ Double SPI Speed Bit
+&78 constant SPDR \ SPI Data Register
+\ BOOT_LOAD
+&87 constant SPMCSR \ Store Program Memory Control Register
+ $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
+ $20 constant SPMCSR_SIGRD \ Signature Row Read
+ $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
+ $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
+ $04 constant SPMCSR_PGWRT \ Page Write
+ $02 constant SPMCSR_PGERS \ Page Erase
+ $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
+\ EEPROM
+&65 constant EEAR \ EEPROM Address Register Low Bytes
+&64 constant EEDR \ EEPROM Data Register
+&63 constant EECR \ EEPROM Control Register
+ $30 constant EECR_EEPM \ EEPROM Programming Mode Bits
+ $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
+ $04 constant EECR_EEMPE \ EEPROM Master Write Enable
+ $02 constant EECR_EEPE \ EEPROM Write Enable
+ $01 constant EECR_EERE \ EEPROM Read Enable
+\ TIMER_COUNTER_0
+&72 constant OCR0B \ Timer/Counter0 Output Compare Register
+&71 constant OCR0A \ Timer/Counter0 Output Compare Register
+&70 constant TCNT0 \ Timer/Counter0
+&69 constant TCCR0B \ Timer/Counter Control Register B
+ $80 constant TCCR0B_FOC0A \ Force Output Compare A
+ $40 constant TCCR0B_FOC0B \ Force Output Compare B
+ $08 constant TCCR0B_WGM02 \
+ $07 constant TCCR0B_CS0 \ Clock Select
+&68 constant TCCR0A \ Timer/Counter Control Register A
+ $C0 constant TCCR0A_COM0A \ Compare Output Mode, Phase Correct PWM Mode
+ $30 constant TCCR0A_COM0B \ Compare Output Mode, Fast PWm
+ $03 constant TCCR0A_WGM0 \ Waveform Generation Mode
+&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
+ $04 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare Match B Interrupt Enable
+ $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match A Interrupt Enable
+ $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
+&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
+ $04 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare Flag 0B
+ $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0A
+ $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
+&67 constant GTCCR \ General Timer/Counter Control Register
+ $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
+ $01 constant GTCCR_PSRSYNC \ Prescaler Reset Timer/Counter1 and Timer/Counter0
+\ TIMER_COUNTER_1
+&128 constant TCCR1A \ Timer/Counter1 Control Register A
+ $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
+ $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
+ $0C constant TCCR1A_COM1C \ Compare Output Mode 1C, bits
+ $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
+&129 constant TCCR1B \ Timer/Counter1 Control Register B
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
+ $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
+&130 constant TCCR1C \ Timer/Counter 1 Control Register C
+ $80 constant TCCR1C_FOC1A \ Force Output Compare 1A
+ $40 constant TCCR1C_FOC1B \ Force Output Compare 1B
+ $20 constant TCCR1C_FOC1C \ Force Output Compare 1C
+&132 constant TCNT1 \ Timer/Counter1 Bytes
+&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
+&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
+&140 constant OCR1C \ Timer/Counter1 Output Compare Register C Bytes
+&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
+&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
+ $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
+ $08 constant TIMSK1_OCIE1C \ Timer/Counter1 Output Compare C Match Interrupt Enable
+ $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
+ $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
+ $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
+&54 constant TIFR1 \ Timer/Counter1 Interrupt Flag register
+ $20 constant TIFR1_ICF1 \ Input Capture Flag 1
+ $08 constant TIFR1_OCF1C \ Output Compare Flag 1C
+ $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
+ $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
+ $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
+\ PLL
+&73 constant PLLCSR \ PLL Status and Control register
+ $1C constant PLLCSR_PLLP \ PLL prescaler Bits
+ $02 constant PLLCSR_PLLE \ PLL Enable Bit
+ $01 constant PLLCSR_PLOCK \ PLL Lock Status Bit
+\ USB_DEVICE
+&244 constant UEINT \
+&242 constant UEBCLX \
+&241 constant UEDATX \
+&240 constant UEIENX \
+ $80 constant UEIENX_FLERRE \
+ $40 constant UEIENX_NAKINE \
+ $10 constant UEIENX_NAKOUTE \
+ $08 constant UEIENX_RXSTPE \
+ $04 constant UEIENX_RXOUTE \
+ $02 constant UEIENX_STALLEDE \
+ $01 constant UEIENX_TXINE \
+&239 constant UESTA1X \
+ $04 constant UESTA1X_CTRLDIR \
+ $03 constant UESTA1X_CURRBK \
+&238 constant UESTA0X \
+ $80 constant UESTA0X_CFGOK \
+ $40 constant UESTA0X_OVERFI \
+ $20 constant UESTA0X_UNDERFI \
+ $0C constant UESTA0X_DTSEQ \
+ $03 constant UESTA0X_NBUSYBK \
+&237 constant UECFG1X \
+ $70 constant UECFG1X_EPSIZE \
+ $0C constant UECFG1X_EPBK \
+ $02 constant UECFG1X_ALLOC \
+&236 constant UECFG0X \
+ $C0 constant UECFG0X_EPTYPE \
+ $01 constant UECFG0X_EPDIR \
+&235 constant UECONX \
+ $20 constant UECONX_STALLRQ \
+ $10 constant UECONX_STALLRQC \
+ $08 constant UECONX_RSTDT \
+ $01 constant UECONX_EPEN \
+&234 constant UERST \
+ $1F constant UERST_EPRST \
+&233 constant UENUM \
+&232 constant UEINTX \
+ $80 constant UEINTX_FIFOCON \
+ $40 constant UEINTX_NAKINI \
+ $20 constant UEINTX_RWAL \
+ $10 constant UEINTX_NAKOUTI \
+ $08 constant UEINTX_RXSTPI \
+ $04 constant UEINTX_RXOUTI \
+ $02 constant UEINTX_STALLEDI \
+ $01 constant UEINTX_TXINI \
+&230 constant UDMFN \
+ $10 constant UDMFN_FNCERR \
+&228 constant UDFNUM \
+&227 constant UDADDR \
+ $80 constant UDADDR_ADDEN \
+ $7F constant UDADDR_UADD \
+&226 constant UDIEN \
+ $40 constant UDIEN_UPRSME \
+ $20 constant UDIEN_EORSME \
+ $10 constant UDIEN_WAKEUPE \
+ $08 constant UDIEN_EORSTE \
+ $04 constant UDIEN_SOFE \
+ $01 constant UDIEN_SUSPE \
+&225 constant UDINT \
+ $40 constant UDINT_UPRSMI \
+ $20 constant UDINT_EORSMI \
+ $10 constant UDINT_WAKEUPI \
+ $08 constant UDINT_EORSTI \
+ $04 constant UDINT_SOFI \
+ $01 constant UDINT_SUSPI \
+&224 constant UDCON \
+ $04 constant UDCON_RSTCPU \
+ $02 constant UDCON_RMWKUP \
+ $01 constant UDCON_DETACH \
+&216 constant USBCON \ USB General Control Register
+ $80 constant USBCON_USBE \
+ $20 constant USBCON_FRZCLK \
+&99 constant REGCR \ Regulator Control Register
+ $01 constant REGCR_REGDIS \
+\ PS2
+&251 constant UPOE \
+ $C0 constant UPOE_UPWE \
+ $30 constant UPOE_UPDRV \
+ $08 constant UPOE_SCKI \
+ $04 constant UPOE_DATAI \
+ $02 constant UPOE_DPI \
+ $01 constant UPOE_DMI \
+&250 constant PS2CON \ PS2 Pad Enable register
+ $01 constant PS2CON_PS2EN \ Enable
+\ CPU
+&95 constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ $08 constant SREG_V \ Two's Complement Overflow Flag
+ $04 constant SREG_N \ Negative Flag
+ $02 constant SREG_Z \ Zero Flag
+ $01 constant SREG_C \ Carry Flag
+&93 constant SP \ Stack Pointer
+&85 constant MCUCR \ MCU Control Register
+ $10 constant MCUCR_PUD \ Pull-up disable
+ $02 constant MCUCR_IVSEL \ Interrupt Vector Select
+ $01 constant MCUCR_IVCE \ Interrupt Vector Change Enable
+&84 constant MCUSR \ MCU Status Register
+ $20 constant MCUSR_USBRF \ USB reset flag
+ $08 constant MCUSR_WDRF \ Watchdog Reset Flag
+ $04 constant MCUSR_BORF \ Brown-out Reset Flag
+ $02 constant MCUSR_EXTRF \ External Reset Flag
+ $01 constant MCUSR_PORF \ Power-on reset flag
+&102 constant OSCCAL \ Oscillator Calibration Value
+&97 constant CLKPR \
+ $80 constant CLKPR_CLKPCE \
+ $0F constant CLKPR_CLKPS \
+&83 constant SMCR \ Sleep Mode Control Register
+ $0E constant SMCR_SM \ Sleep Mode Select bits
+ $01 constant SMCR_SE \ Sleep Enable
+&92 constant EIND \ Extended Indirect Register
+&75 constant GPIOR2 \ General Purpose IO Register 2
+ $FF constant GPIOR2_GPIOR \ General Purpose IO Register 2 bis
+&74 constant GPIOR1 \ General Purpose IO Register 1
+ $FF constant GPIOR1_GPIOR \ General Purpose IO Register 1 bis
+&62 constant GPIOR0 \ General Purpose IO Register 0
+ $80 constant GPIOR0_GPIOR07 \ General Purpose IO Register 0 bit 7
+ $40 constant GPIOR0_GPIOR06 \ General Purpose IO Register 0 bit 6
+ $20 constant GPIOR0_GPIOR05 \ General Purpose IO Register 0 bit 5
+ $10 constant GPIOR0_GPIOR04 \ General Purpose IO Register 0 bit 4
+ $08 constant GPIOR0_GPIOR03 \ General Purpose IO Register 0 bit 3
+ $04 constant GPIOR0_GPIOR02 \ General Purpose IO Register 0 bit 2
+ $02 constant GPIOR0_GPIOR01 \ General Purpose IO Register 0 bit 1
+ $01 constant GPIOR0_GPIOR00 \ General Purpose IO Register 0 bit 0
+&101 constant PRR1 \ Power Reduction Register1
+ $80 constant PRR1_PRUSB \ Power Reduction USB
+ $01 constant PRR1_PRUSART1 \ Power Reduction USART1
+&100 constant PRR0 \ Power Reduction Register0
+ $20 constant PRR0_PRTIM0 \ Power Reduction Timer/Counter0
+ $08 constant PRR0_PRTIM1 \ Power Reduction Timer/Counter1
+ $04 constant PRR0_PRSPI \ Power Reduction Serial Peripheral Interface
+&210 constant CLKSTA \
+ $02 constant CLKSTA_RCON \
+ $01 constant CLKSTA_EXTON \
+&209 constant CLKSEL1 \
+ $F0 constant CLKSEL1_RCCKSEL \
+ $0F constant CLKSEL1_EXCKSEL \
+&208 constant CLKSEL0 \
+ $C0 constant CLKSEL0_RCSUT \
+ $30 constant CLKSEL0_EXSUT \
+ $08 constant CLKSEL0_RCE \
+ $04 constant CLKSEL0_EXTE \
+ $01 constant CLKSEL0_CLKS \
+&81 constant DWDR \ debugWire communication register
+\ EXTERNAL_INTERRUPT
+&105 constant EICRA \ External Interrupt Control Register A
+ $C0 constant EICRA_ISC3 \ External Interrupt Sense Control Bit
+ $30 constant EICRA_ISC2 \ External Interrupt Sense Control Bit
+ $0C constant EICRA_ISC1 \ External Interrupt Sense Control Bit
+ $03 constant EICRA_ISC0 \ External Interrupt Sense Control Bit
+&106 constant EICRB \ External Interrupt Control Register B
+ $C0 constant EICRB_ISC7 \ External Interrupt 7-4 Sense Control Bit
+ $30 constant EICRB_ISC6 \ External Interrupt 7-4 Sense Control Bit
+ $0C constant EICRB_ISC5 \ External Interrupt 7-4 Sense Control Bit
+ $03 constant EICRB_ISC4 \ External Interrupt 7-4 Sense Control Bit
+&61 constant EIMSK \ External Interrupt Mask Register
+ $FF constant EIMSK_INT \ External Interrupt Request 7 Enable
+&60 constant EIFR \ External Interrupt Flag Register
+ $FF constant EIFR_INTF \ External Interrupt Flags
+&107 constant PCMSK0 \ Pin Change Mask Register 0
+ $FF constant PCMSK0_PCINT \ Pin Change Enable Masks
+&108 constant PCMSK1 \ Pin Change Mask Register 1
+ $1F constant PCMSK1_PCINT \
+&59 constant PCIFR \ Pin Change Interrupt Flag Register
+ $03 constant PCIFR_PCIF \ Pin Change Interrupt Flags
+&104 constant PCICR \ Pin Change Interrupt Control Register
+ $03 constant PCICR_PCIE \ Pin Change Interrupt Enables
+\ USART1
+&206 constant UDR1 \ USART I/O Data Register
+&200 constant UCSR1A \ USART Control and Status Register A
+ $80 constant UCSR1A_RXC1 \ USART Receive Complete
+ $40 constant UCSR1A_TXC1 \ USART Transmitt Complete
+ $20 constant UCSR1A_UDRE1 \ USART Data Register Empty
+ $10 constant UCSR1A_FE1 \ Framing Error
+ $08 constant UCSR1A_DOR1 \ Data overRun
+ $04 constant UCSR1A_UPE1 \ Parity Error
+ $02 constant UCSR1A_U2X1 \ Double the USART transmission speed
+ $01 constant UCSR1A_MPCM1 \ Multi-processor Communication Mode
+&201 constant UCSR1B \ USART Control and Status Register B
+ $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable
+ $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable
+ $20 constant UCSR1B_UDRIE1 \ USART Data register Empty Interrupt Enable
+ $10 constant UCSR1B_RXEN1 \ Receiver Enable
+ $08 constant UCSR1B_TXEN1 \ Transmitter Enable
+ $04 constant UCSR1B_UCSZ12 \ Character Size
+ $02 constant UCSR1B_RXB81 \ Receive Data Bit 8
+ $01 constant UCSR1B_TXB81 \ Transmit Data Bit 8
+&202 constant UCSR1C \ USART Control and Status Register C
+ $C0 constant UCSR1C_UMSEL1 \ USART Mode Select
+ $30 constant UCSR1C_UPM1 \ Parity Mode Bits
+ $08 constant UCSR1C_USBS1 \ Stop Bit Select
+ $06 constant UCSR1C_UCSZ1 \ Character Size
+ $01 constant UCSR1C_UCPOL1 \ Clock Polarity
+&203 constant UCSR1D \ USART Control and Status Register D
+ $02 constant UCSR1D_CTSEN \ CTS Enable
+ $01 constant UCSR1D_RTSEN \ RTS Enable
+&204 constant UBRR1 \ USART Baud Rate Register Bytes
+\ WATCHDOG
+&96 constant WDTCSR \ Watchdog Timer Control Register
+ $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Flag
+ $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Enable
+ $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
+ $10 constant WDTCSR_WDCE \ Watchdog Change Enable
+ $08 constant WDTCSR_WDE \ Watch Dog Enable
+&98 constant WDTCKD \ Watchdog Timer Clock Divider
+ $08 constant WDTCKD_WDEWIF \ Watchdog Early Warning Interrupt Flag
+ $04 constant WDTCKD_WDEWIE \ Watchdog Early Warning Interrupt Enable
+ $03 constant WDTCKD_WCLKD \ Watchdog Timer Clock Dividers
+\ ANALOG_COMPARATOR
+&80 constant ACSR \ Analog Comparator Control And Status Register
+ $80 constant ACSR_ACD \ Analog Comparator Disable
+ $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
+ $20 constant ACSR_ACO \ Analog Compare Output
+ $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
+ $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
+ $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
+ $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
+&127 constant DIDR1 \
+ $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
+ $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
+\ PORTC
+&40 constant PORTC \ Port C Data Register
+ $F0 constant PORTC_PORTC \ Port C Data Register bits
+ $07 constant PORTC_PORTC \ Port C Data Register bits
+&39 constant DDRC \ Port C Data Direction Register
+ $F0 constant DDRC_DDC \ Port C Data Direction Register bits
+ $07 constant DDRC_DDC \ Port C Data Direction Register bits
+&38 constant PINC \ Port C Input Pins
+ $F0 constant PINC_PINC \ Port C Input Pins bits
+ $07 constant PINC_PINC \ Port C Input Pins bits
+
+\ Interrupts
+&2 constant INT0Addr \ External Interrupt Request 0
+&4 constant INT1Addr \ External Interrupt Request 1
+&6 constant INT2Addr \ External Interrupt Request 2
+&8 constant INT3Addr \ External Interrupt Request 3
+&10 constant INT4Addr \ External Interrupt Request 4
+&12 constant INT5Addr \ External Interrupt Request 5
+&14 constant INT6Addr \ External Interrupt Request 6
+&16 constant INT7Addr \ External Interrupt Request 7
+&18 constant PCINT0Addr \ Pin Change Interrupt Request 0
+&20 constant PCINT1Addr \ Pin Change Interrupt Request 1
+&22 constant USB_GENAddr \ USB General Interrupt Request
+&24 constant USB_COMAddr \ USB Endpoint/Pipe Interrupt Communication Reque
+&26 constant WDTAddr \ Watchdog Time-out Interrupt
+&28 constant TIMER1_CAPTAddr \ Timer/Counter2 Capture Event
+&30 constant TIMER1_COMPAAddr \ Timer/Counter2 Compare Match B
+&32 constant TIMER1_COMPBAddr \ Timer/Counter2 Compare Match B
+&34 constant TIMER1_COMPCAddr \ Timer/Counter2 Compare Match C
+&36 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+&38 constant TIMER0_COMPAAddr \ Timer/Counter0 Compare Match A
+&40 constant TIMER0_COMPBAddr \ Timer/Counter0 Compare Match B
+&42 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
+&44 constant SPI__STCAddr \ SPI Serial Transfer Complete
+&46 constant USART1__RXAddr \ USART1, Rx Complete
+&48 constant USART1__UDREAddr \ USART1 Data register Empty
+&50 constant USART1__TXAddr \ USART1, Tx Complete
+&52 constant ANALOG_COMPAddr \ Analog Comparator
+&54 constant EE_READYAddr \ EEPROM Ready
+&56 constant SPM_READYAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/at90usb162/device.asm b/amforth-6.5/avr8/devices/at90usb162/device.asm
new file mode 100644
index 0000000..2cb7d4b
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90usb162/device.asm
@@ -0,0 +1,113 @@
+; Partname: AT90USB162
+; generated automatically, do not edit
+
+.nolist
+ .include "usb162def.inc"
+.list
+
+.equ ramstart = 256
+.equ CELLSIZE = 2
+.macro readflashcell
+ lsl zl
+ rol zh
+ lpm @0, Z+
+ lpm @1, Z+
+.endmacro
+.macro writeflashcell
+ lsl zl
+ rol zh
+.endmacro
+.set WANT_PORTB = 0
+.set WANT_PORTD = 0
+.set WANT_SPI = 0
+.set WANT_BOOT_LOAD = 0
+.set WANT_EEPROM = 0
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_PLL = 0
+.set WANT_USB_DEVICE = 0
+.set WANT_PS2 = 0
+.set WANT_CPU = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_USART1 = 0
+.set WANT_WATCHDOG = 0
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_PORTC = 0
+.equ intvecsize = 2 ; please verify; flash size: 16384 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.org 2
+ rcall isr ; External Interrupt Request 0
+.org 4
+ rcall isr ; External Interrupt Request 1
+.org 6
+ rcall isr ; External Interrupt Request 2
+.org 8
+ rcall isr ; External Interrupt Request 3
+.org 10
+ rcall isr ; External Interrupt Request 4
+.org 12
+ rcall isr ; External Interrupt Request 5
+.org 14
+ rcall isr ; External Interrupt Request 6
+.org 16
+ rcall isr ; External Interrupt Request 7
+.org 18
+ rcall isr ; Pin Change Interrupt Request 0
+.org 20
+ rcall isr ; Pin Change Interrupt Request 1
+.org 22
+ rcall isr ; USB General Interrupt Request
+.org 24
+ rcall isr ; USB Endpoint/Pipe Interrupt Communication Request
+.org 26
+ rcall isr ; Watchdog Time-out Interrupt
+.org 28
+ rcall isr ; Timer/Counter2 Capture Event
+.org 30
+ rcall isr ; Timer/Counter2 Compare Match B
+.org 32
+ rcall isr ; Timer/Counter2 Compare Match B
+.org 34
+ rcall isr ; Timer/Counter2 Compare Match C
+.org 36
+ rcall isr ; Timer/Counter1 Overflow
+.org 38
+ rcall isr ; Timer/Counter0 Compare Match A
+.org 40
+ rcall isr ; Timer/Counter0 Compare Match B
+.org 42
+ rcall isr ; Timer/Counter0 Overflow
+.org 44
+ rcall isr ; SPI Serial Transfer Complete
+.org 46
+ rcall isr ; USART1, Rx Complete
+.org 48
+ rcall isr ; USART1 Data register Empty
+.org 50
+ rcall isr ; USART1, Tx Complete
+.org 52
+ rcall isr ; Analog Comparator
+.org 54
+ rcall isr ; EEPROM Ready
+.org 56
+ rcall isr ; Store Program Memory Read
+.equ INTVECTORS = 29
+.nooverlap
+
+; compatability layer (maybe empty)
+
+; controller data area, environment query mcu-info
+mcu_info:
+mcu_ramsize:
+ .dw 512
+mcu_eepromsize:
+ .dw 512
+mcu_maxdp:
+ .dw 12288
+mcu_numints:
+ .dw 29
+mcu_name:
+ .dw 10
+ .db "AT90USB162"
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/at90usb162/device.inc b/amforth-6.5/avr8/devices/at90usb162/device.inc
new file mode 100644
index 0000000..97b1bc3
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90usb162/device.inc
@@ -0,0 +1,1155 @@
+; Partname: AT90USB162
+; generated automatically, no not edit
+
+.if WANT_PORTB == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw 37
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw 36
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw 35
+
+.endif
+.if WANT_PORTD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw 43
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw 42
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw 41
+
+.endif
+.if WANT_SPI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR:
+ .dw $ff04
+ .db "SPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR
+XT_SPCR:
+ .dw PFA_DOVARIABLE
+PFA_SPCR:
+ .dw 76
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR:
+ .dw $ff04
+ .db "SPSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR
+XT_SPSR:
+ .dw PFA_DOVARIABLE
+PFA_SPSR:
+ .dw 77
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR:
+ .dw $ff04
+ .db "SPDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR
+XT_SPDR:
+ .dw PFA_DOVARIABLE
+PFA_SPDR:
+ .dw 78
+
+.endif
+.if WANT_BOOT_LOAD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control Register
+VE_SPMCSR:
+ .dw $ff06
+ .db "SPMCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCSR
+XT_SPMCSR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCSR:
+ .dw 87
+
+.endif
+.if WANT_EEPROM == 1
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Address Register Low Bytes
+VE_EEAR:
+ .dw $ff04
+ .db "EEAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEAR
+XT_EEAR:
+ .dw PFA_DOVARIABLE
+PFA_EEAR:
+ .dw 65
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw 64
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw 63
+
+.endif
+.if WANT_TIMER_COUNTER_0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0B:
+ .dw $ff05
+ .db "OCR0B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0B
+XT_OCR0B:
+ .dw PFA_DOVARIABLE
+PFA_OCR0B:
+ .dw 72
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0A:
+ .dw $ff05
+ .db "OCR0A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0A
+XT_OCR0A:
+ .dw PFA_DOVARIABLE
+PFA_OCR0A:
+ .dw 71
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw 70
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register B
+VE_TCCR0B:
+ .dw $ff06
+ .db "TCCR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0B
+XT_TCCR0B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0B:
+ .dw 69
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register A
+VE_TCCR0A:
+ .dw $ff06
+ .db "TCCR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0A
+XT_TCCR0A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0A:
+ .dw 68
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Mask Register
+VE_TIMSK0:
+ .dw $ff06
+ .db "TIMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK0
+XT_TIMSK0:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK0:
+ .dw 110
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Flag register
+VE_TIFR0:
+ .dw $ff05
+ .db "TIFR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR0
+XT_TIFR0:
+ .dw PFA_DOVARIABLE
+PFA_TIFR0:
+ .dw 53
+; ( -- addr ) System Constant
+; R( -- )
+; General Timer/Counter Control Register
+VE_GTCCR:
+ .dw $ff05
+ .db "GTCCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GTCCR
+XT_GTCCR:
+ .dw PFA_DOVARIABLE
+PFA_GTCCR:
+ .dw 67
+
+.endif
+.if WANT_TIMER_COUNTER_1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw 128
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw 129
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter 1 Control Register C
+VE_TCCR1C:
+ .dw $ff06
+ .db "TCCR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1C
+XT_TCCR1C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1C:
+ .dw 130
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Bytes
+VE_TCNT1:
+ .dw $ff05
+ .db "TCNT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1
+XT_TCNT1:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1:
+ .dw 132
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register A Bytes
+VE_OCR1A:
+ .dw $ff05
+ .db "OCR1A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1A
+XT_OCR1A:
+ .dw PFA_DOVARIABLE
+PFA_OCR1A:
+ .dw 136
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register B Bytes
+VE_OCR1B:
+ .dw $ff05
+ .db "OCR1B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1B
+XT_OCR1B:
+ .dw PFA_DOVARIABLE
+PFA_OCR1B:
+ .dw 138
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register C Bytes
+VE_OCR1C:
+ .dw $ff05
+ .db "OCR1C",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1C
+XT_OCR1C:
+ .dw PFA_DOVARIABLE
+PFA_OCR1C:
+ .dw 140
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Bytes
+VE_ICR1:
+ .dw $ff04
+ .db "ICR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1
+XT_ICR1:
+ .dw PFA_DOVARIABLE
+PFA_ICR1:
+ .dw 134
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Mask Register
+VE_TIMSK1:
+ .dw $ff06
+ .db "TIMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK1
+XT_TIMSK1:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK1:
+ .dw 111
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Flag register
+VE_TIFR1:
+ .dw $ff05
+ .db "TIFR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR1
+XT_TIFR1:
+ .dw PFA_DOVARIABLE
+PFA_TIFR1:
+ .dw 54
+
+.endif
+.if WANT_PLL == 1
+; ( -- addr ) System Constant
+; R( -- )
+; PLL Status and Control register
+VE_PLLCSR:
+ .dw $ff06
+ .db "PLLCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PLLCSR
+XT_PLLCSR:
+ .dw PFA_DOVARIABLE
+PFA_PLLCSR:
+ .dw 73
+
+.endif
+.if WANT_USB_DEVICE == 1
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UEINT:
+ .dw $ff05
+ .db "UEINT",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UEINT
+XT_UEINT:
+ .dw PFA_DOVARIABLE
+PFA_UEINT:
+ .dw 244
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UEBCLX:
+ .dw $ff06
+ .db "UEBCLX"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UEBCLX
+XT_UEBCLX:
+ .dw PFA_DOVARIABLE
+PFA_UEBCLX:
+ .dw 242
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UEDATX:
+ .dw $ff06
+ .db "UEDATX"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UEDATX
+XT_UEDATX:
+ .dw PFA_DOVARIABLE
+PFA_UEDATX:
+ .dw 241
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UEIENX:
+ .dw $ff06
+ .db "UEIENX"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UEIENX
+XT_UEIENX:
+ .dw PFA_DOVARIABLE
+PFA_UEIENX:
+ .dw 240
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UESTA1X:
+ .dw $ff07
+ .db "UESTA1X",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UESTA1X
+XT_UESTA1X:
+ .dw PFA_DOVARIABLE
+PFA_UESTA1X:
+ .dw 239
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UESTA0X:
+ .dw $ff07
+ .db "UESTA0X",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UESTA0X
+XT_UESTA0X:
+ .dw PFA_DOVARIABLE
+PFA_UESTA0X:
+ .dw 238
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UECFG1X:
+ .dw $ff07
+ .db "UECFG1X",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UECFG1X
+XT_UECFG1X:
+ .dw PFA_DOVARIABLE
+PFA_UECFG1X:
+ .dw 237
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UECFG0X:
+ .dw $ff07
+ .db "UECFG0X",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UECFG0X
+XT_UECFG0X:
+ .dw PFA_DOVARIABLE
+PFA_UECFG0X:
+ .dw 236
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UECONX:
+ .dw $ff06
+ .db "UECONX"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UECONX
+XT_UECONX:
+ .dw PFA_DOVARIABLE
+PFA_UECONX:
+ .dw 235
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UERST:
+ .dw $ff05
+ .db "UERST",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UERST
+XT_UERST:
+ .dw PFA_DOVARIABLE
+PFA_UERST:
+ .dw 234
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UENUM:
+ .dw $ff05
+ .db "UENUM",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UENUM
+XT_UENUM:
+ .dw PFA_DOVARIABLE
+PFA_UENUM:
+ .dw 233
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UEINTX:
+ .dw $ff06
+ .db "UEINTX"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UEINTX
+XT_UEINTX:
+ .dw PFA_DOVARIABLE
+PFA_UEINTX:
+ .dw 232
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UDMFN:
+ .dw $ff05
+ .db "UDMFN",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDMFN
+XT_UDMFN:
+ .dw PFA_DOVARIABLE
+PFA_UDMFN:
+ .dw 230
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UDFNUM:
+ .dw $ff06
+ .db "UDFNUM"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDFNUM
+XT_UDFNUM:
+ .dw PFA_DOVARIABLE
+PFA_UDFNUM:
+ .dw 228
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UDADDR:
+ .dw $ff06
+ .db "UDADDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDADDR
+XT_UDADDR:
+ .dw PFA_DOVARIABLE
+PFA_UDADDR:
+ .dw 227
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UDIEN:
+ .dw $ff05
+ .db "UDIEN",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDIEN
+XT_UDIEN:
+ .dw PFA_DOVARIABLE
+PFA_UDIEN:
+ .dw 226
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UDINT:
+ .dw $ff05
+ .db "UDINT",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDINT
+XT_UDINT:
+ .dw PFA_DOVARIABLE
+PFA_UDINT:
+ .dw 225
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UDCON:
+ .dw $ff05
+ .db "UDCON",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDCON
+XT_UDCON:
+ .dw PFA_DOVARIABLE
+PFA_UDCON:
+ .dw 224
+; ( -- addr ) System Constant
+; R( -- )
+; USB General Control Register
+VE_USBCON:
+ .dw $ff06
+ .db "USBCON"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USBCON
+XT_USBCON:
+ .dw PFA_DOVARIABLE
+PFA_USBCON:
+ .dw 216
+; ( -- addr ) System Constant
+; R( -- )
+; Regulator Control Register
+VE_REGCR:
+ .dw $ff05
+ .db "REGCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_REGCR
+XT_REGCR:
+ .dw PFA_DOVARIABLE
+PFA_REGCR:
+ .dw 99
+
+.endif
+.if WANT_PS2 == 1
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UPOE:
+ .dw $ff04
+ .db "UPOE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UPOE
+XT_UPOE:
+ .dw PFA_DOVARIABLE
+PFA_UPOE:
+ .dw 251
+; ( -- addr ) System Constant
+; R( -- )
+; PS2 Pad Enable register
+VE_PS2CON:
+ .dw $ff06
+ .db "PS2CON"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PS2CON
+XT_PS2CON:
+ .dw PFA_DOVARIABLE
+PFA_PS2CON:
+ .dw 250
+
+.endif
+.if WANT_CPU == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw 95
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer
+VE_SP:
+ .dw $ff02
+ .db "SP"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SP
+XT_SP:
+ .dw PFA_DOVARIABLE
+PFA_SP:
+ .dw 93
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw 85
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Status Register
+VE_MCUSR:
+ .dw $ff05
+ .db "MCUSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUSR
+XT_MCUSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUSR:
+ .dw 84
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Calibration Value
+VE_OSCCAL:
+ .dw $ff06
+ .db "OSCCAL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSCCAL
+XT_OSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_OSCCAL:
+ .dw 102
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_CLKPR:
+ .dw $ff05
+ .db "CLKPR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKPR
+XT_CLKPR:
+ .dw PFA_DOVARIABLE
+PFA_CLKPR:
+ .dw 97
+; ( -- addr ) System Constant
+; R( -- )
+; Sleep Mode Control Register
+VE_SMCR:
+ .dw $ff04
+ .db "SMCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SMCR
+XT_SMCR:
+ .dw PFA_DOVARIABLE
+PFA_SMCR:
+ .dw 83
+; ( -- addr ) System Constant
+; R( -- )
+; Extended Indirect Register
+VE_EIND:
+ .dw $ff04
+ .db "EIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIND
+XT_EIND:
+ .dw PFA_DOVARIABLE
+PFA_EIND:
+ .dw 92
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 2
+VE_GPIOR2:
+ .dw $ff06
+ .db "GPIOR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR2
+XT_GPIOR2:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR2:
+ .dw 75
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 1
+VE_GPIOR1:
+ .dw $ff06
+ .db "GPIOR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR1
+XT_GPIOR1:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR1:
+ .dw 74
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 0
+VE_GPIOR0:
+ .dw $ff06
+ .db "GPIOR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR0
+XT_GPIOR0:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR0:
+ .dw 62
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register1
+VE_PRR1:
+ .dw $ff04
+ .db "PRR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR1
+XT_PRR1:
+ .dw PFA_DOVARIABLE
+PFA_PRR1:
+ .dw 101
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register0
+VE_PRR0:
+ .dw $ff04
+ .db "PRR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR0
+XT_PRR0:
+ .dw PFA_DOVARIABLE
+PFA_PRR0:
+ .dw 100
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_CLKSTA:
+ .dw $ff06
+ .db "CLKSTA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKSTA
+XT_CLKSTA:
+ .dw PFA_DOVARIABLE
+PFA_CLKSTA:
+ .dw 210
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_CLKSEL1:
+ .dw $ff07
+ .db "CLKSEL1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKSEL1
+XT_CLKSEL1:
+ .dw PFA_DOVARIABLE
+PFA_CLKSEL1:
+ .dw 209
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_CLKSEL0:
+ .dw $ff07
+ .db "CLKSEL0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKSEL0
+XT_CLKSEL0:
+ .dw PFA_DOVARIABLE
+PFA_CLKSEL0:
+ .dw 208
+; ( -- addr ) System Constant
+; R( -- )
+; debugWire communication register
+VE_DWDR:
+ .dw $ff04
+ .db "DWDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DWDR
+XT_DWDR:
+ .dw PFA_DOVARIABLE
+PFA_DWDR:
+ .dw 81
+
+.endif
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register A
+VE_EICRA:
+ .dw $ff05
+ .db "EICRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRA
+XT_EICRA:
+ .dw PFA_DOVARIABLE
+PFA_EICRA:
+ .dw 105
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register B
+VE_EICRB:
+ .dw $ff05
+ .db "EICRB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRB
+XT_EICRB:
+ .dw PFA_DOVARIABLE
+PFA_EICRB:
+ .dw 106
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Mask Register
+VE_EIMSK:
+ .dw $ff05
+ .db "EIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIMSK
+XT_EIMSK:
+ .dw PFA_DOVARIABLE
+PFA_EIMSK:
+ .dw 61
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Flag Register
+VE_EIFR:
+ .dw $ff04
+ .db "EIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIFR
+XT_EIFR:
+ .dw PFA_DOVARIABLE
+PFA_EIFR:
+ .dw 60
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 0
+VE_PCMSK0:
+ .dw $ff06
+ .db "PCMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK0
+XT_PCMSK0:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK0:
+ .dw 107
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 1
+VE_PCMSK1:
+ .dw $ff06
+ .db "PCMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK1
+XT_PCMSK1:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK1:
+ .dw 108
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Interrupt Flag Register
+VE_PCIFR:
+ .dw $ff05
+ .db "PCIFR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCIFR
+XT_PCIFR:
+ .dw PFA_DOVARIABLE
+PFA_PCIFR:
+ .dw 59
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Interrupt Control Register
+VE_PCICR:
+ .dw $ff05
+ .db "PCICR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCICR
+XT_PCICR:
+ .dw PFA_DOVARIABLE
+PFA_PCICR:
+ .dw 104
+
+.endif
+.if WANT_USART1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR1:
+ .dw $ff04
+ .db "UDR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR1
+XT_UDR1:
+ .dw PFA_DOVARIABLE
+PFA_UDR1:
+ .dw 206
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR1A:
+ .dw $ff06
+ .db "UCSR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1A
+XT_UCSR1A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1A:
+ .dw 200
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR1B:
+ .dw $ff06
+ .db "UCSR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1B
+XT_UCSR1B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1B:
+ .dw 201
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR1C:
+ .dw $ff06
+ .db "UCSR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1C
+XT_UCSR1C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1C:
+ .dw 202
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register D
+VE_UCSR1D:
+ .dw $ff06
+ .db "UCSR1D"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1D
+XT_UCSR1D:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1D:
+ .dw 203
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Bytes
+VE_UBRR1:
+ .dw $ff05
+ .db "UBRR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR1
+XT_UBRR1:
+ .dw PFA_DOVARIABLE
+PFA_UBRR1:
+ .dw 204
+
+.endif
+.if WANT_WATCHDOG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCSR:
+ .dw $ff06
+ .db "WDTCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCSR
+XT_WDTCSR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCSR:
+ .dw 96
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Clock Divider
+VE_WDTCKD:
+ .dw $ff06
+ .db "WDTCKD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCKD
+XT_WDTCKD:
+ .dw PFA_DOVARIABLE
+PFA_WDTCKD:
+ .dw 98
+
+.endif
+.if WANT_ANALOG_COMPARATOR == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Control And Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw 80
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_DIDR1:
+ .dw $ff05
+ .db "DIDR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR1
+XT_DIDR1:
+ .dw PFA_DOVARIABLE
+PFA_DIDR1:
+ .dw 127
+
+.endif
+.if WANT_PORTC == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Register
+VE_PORTC:
+ .dw $ff05
+ .db "PORTC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTC
+XT_PORTC:
+ .dw PFA_DOVARIABLE
+PFA_PORTC:
+ .dw 40
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Direction Register
+VE_DDRC:
+ .dw $ff04
+ .db "DDRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRC
+XT_DDRC:
+ .dw PFA_DOVARIABLE
+PFA_DDRC:
+ .dw 39
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Input Pins
+VE_PINC:
+ .dw $ff04
+ .db "PINC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINC
+XT_PINC:
+ .dw PFA_DOVARIABLE
+PFA_PINC:
+ .dw 38
+
+.endif
diff --git a/amforth-6.5/avr8/devices/at90usb162/device.py b/amforth-6.5/avr8/devices/at90usb162/device.py
new file mode 100644
index 0000000..5787585
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90usb162/device.py
@@ -0,0 +1,387 @@
+# Generated Automatically
+
+# Partname AT90USB162
+
+MCUREGS = {
+# Interrupt Vectors
+ 'INT0Addr' : '#2', # External Interrupt Request 0
+ 'INT1Addr' : '#4', # External Interrupt Request 1
+ 'INT2Addr' : '#6', # External Interrupt Request 2
+ 'INT3Addr' : '#8', # External Interrupt Request 3
+ 'INT4Addr' : '#10', # External Interrupt Request 4
+ 'INT5Addr' : '#12', # External Interrupt Request 5
+ 'INT6Addr' : '#14', # External Interrupt Request 6
+ 'INT7Addr' : '#16', # External Interrupt Request 7
+ 'PCINT0Addr' : '#18', # Pin Change Interrupt Request 0
+ 'PCINT1Addr' : '#20', # Pin Change Interrupt Request 1
+ 'USB_GENAddr' : '#22', # USB General Interrupt Request
+ 'USB_COMAddr' : '#24', # USB Endpoint/Pipe Interrupt Communication Request
+ 'WDTAddr' : '#26', # Watchdog Time-out Interrupt
+ 'TIMER1_CAPTAddr' : '#28', # Timer/Counter2 Capture Event
+ 'TIMER1_COMPAAddr' : '#30', # Timer/Counter2 Compare Match B
+ 'TIMER1_COMPBAddr' : '#32', # Timer/Counter2 Compare Match B
+ 'TIMER1_COMPCAddr' : '#34', # Timer/Counter2 Compare Match C
+ 'TIMER1_OVFAddr' : '#36', # Timer/Counter1 Overflow
+ 'TIMER0_COMPAAddr' : '#38', # Timer/Counter0 Compare Match A
+ 'TIMER0_COMPBAddr' : '#40', # Timer/Counter0 Compare Match B
+ 'TIMER0_OVFAddr' : '#42', # Timer/Counter0 Overflow
+ 'SPI_STCAddr' : '#44', # SPI Serial Transfer Complete
+ 'USART1_RXAddr' : '#46', # USART1, Rx Complete
+ 'USART1_UDREAddr' : '#48', # USART1 Data register Empty
+ 'USART1_TXAddr' : '#50', # USART1, Tx Complete
+ 'ANALOG_COMPAddr' : '#52', # Analog Comparator
+ 'EE_READYAddr' : '#54', # EEPROM Ready
+ 'SPM_READYAddr' : '#56', # Store Program Memory Read
+
+# Module PORTB
+ 'PORTB' : '$25', # Port B Data Register
+ 'DDRB' : '$24', # Port B Data Direction Register
+ 'PINB' : '$23', # Port B Input Pins
+
+# Module PORTD
+ 'PORTD' : '$2b', # Port D Data Register
+ 'DDRD' : '$2a', # Port D Data Direction Register
+ 'PIND' : '$29', # Port D Input Pins
+
+# Module SPI
+ 'SPCR' : '$4c', # SPI Control Register
+ 'SPCR_SPIE': '$80', # SPI Interrupt Enable
+ 'SPCR_SPE': '$40', # SPI Enable
+ 'SPCR_DORD': '$20', # Data Order
+ 'SPCR_MSTR': '$10', # Master/Slave Select
+ 'SPCR_CPOL': '$8', # Clock polarity
+ 'SPCR_CPHA': '$4', # Clock Phase
+ 'SPCR_SPR': '$3', # SPI Clock Rate Selects
+ 'SPSR' : '$4d', # SPI Status Register
+ 'SPSR_SPIF': '$80', # SPI Interrupt Flag
+ 'SPSR_WCOL': '$40', # Write Collision Flag
+ 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
+ 'SPDR' : '$4e', # SPI Data Register
+
+# Module BOOT_LOAD
+ 'SPMCSR' : '$57', # Store Program Memory Control R
+ 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
+ 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
+ 'SPMCSR_SIGRD': '$20', # Signature Row Read
+ 'SPMCSR_RWWSRE': '$10', # Read While Write section read
+ 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
+ 'SPMCSR_PGWRT': '$4', # Page Write
+ 'SPMCSR_PGERS': '$2', # Page Erase
+ 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
+
+# Module EEPROM
+ 'EEAR' : '$41', # EEPROM Address Register Low By
+ 'EEDR' : '$40', # EEPROM Data Register
+ 'EECR' : '$3f', # EEPROM Control Register
+ 'EECR_EEPM': '$30', # EEPROM Programming Mode Bits
+ 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
+ 'EECR_EEMPE': '$4', # EEPROM Master Write Enable
+ 'EECR_EEPE': '$2', # EEPROM Write Enable
+ 'EECR_EERE': '$1', # EEPROM Read Enable
+
+# Module TIMER_COUNTER_0
+ 'OCR0B' : '$48', # Timer/Counter0 Output Compare
+ 'OCR0A' : '$47', # Timer/Counter0 Output Compare
+ 'TCNT0' : '$46', # Timer/Counter0
+ 'TCCR0B' : '$45', # Timer/Counter Control Register
+ 'TCCR0B_FOC0A': '$80', # Force Output Compare A
+ 'TCCR0B_FOC0B': '$40', # Force Output Compare B
+ 'TCCR0B_WGM02': '$8', #
+ 'TCCR0B_CS0': '$7', # Clock Select
+ 'TCCR0A' : '$44', # Timer/Counter Control Registe
+ 'TCCR0A_COM0A': '$c0', # Compare Output Mode, Phase Cor
+ 'TCCR0A_COM0B': '$30', # Compare Output Mode, Fast PWm
+ 'TCCR0A_WGM0': '$3', # Waveform Generation Mode
+ 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
+ 'TIMSK0_OCIE0B': '$4', # Timer/Counter0 Output Compare
+ 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
+ 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
+ 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
+ 'TIFR0_OCF0B': '$4', # Timer/Counter0 Output Compare
+ 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
+ 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSRSYNC': '$1', # Prescaler Reset Timer/Counter1
+
+# Module TIMER_COUNTER_1
+ 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
+ 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
+ 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
+ 'TCCR1A_COM1C': '$c', # Compare Output Mode 1C, bits
+ 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
+ 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
+ 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
+ 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
+ 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
+ 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
+ 'TCCR1C' : '$82', # Timer/Counter 1 Control Regist
+ 'TCCR1C_FOC1A': '$80', # Force Output Compare 1A
+ 'TCCR1C_FOC1B': '$40', # Force Output Compare 1B
+ 'TCCR1C_FOC1C': '$20', # Force Output Compare 1C
+ 'TCNT1' : '$84', # Timer/Counter1 Bytes
+ 'OCR1A' : '$88', # Timer/Counter1 Output Compare
+ 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
+ 'OCR1C' : '$8c', # Timer/Counter1 Output Compare
+ 'ICR1' : '$86', # Timer/Counter1 Input Capture R
+ 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
+ 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
+ 'TIMSK1_OCIE1C': '$8', # Timer/Counter1 Output Compare
+ 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
+ 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
+ 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
+ 'TIFR1' : '$36', # Timer/Counter1 Interrupt Flag
+ 'TIFR1_ICF1': '$20', # Input Capture Flag 1
+ 'TIFR1_OCF1C': '$8', # Output Compare Flag 1C
+ 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
+ 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
+ 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
+
+# Module PLL
+ 'PLLCSR' : '$49', # PLL Status and Control registe
+ 'PLLCSR_PLLP': '$1c', # PLL prescaler Bits
+ 'PLLCSR_PLLE': '$2', # PLL Enable Bit
+ 'PLLCSR_PLOCK': '$1', # PLL Lock Status Bit
+
+# Module USB_DEVICE
+ 'UEINT' : '$f4', #
+ 'UEBCLX' : '$f2', #
+ 'UEDATX' : '$f1', #
+ 'UEIENX' : '$f0', #
+ 'UEIENX_FLERRE': '$80', #
+ 'UEIENX_NAKINE': '$40', #
+ 'UEIENX_NAKOUTE': '$10', #
+ 'UEIENX_RXSTPE': '$8', #
+ 'UEIENX_RXOUTE': '$4', #
+ 'UEIENX_STALLEDE': '$2', #
+ 'UEIENX_TXINE': '$1', #
+ 'UESTA1X' : '$ef', #
+ 'UESTA1X_CTRLDIR': '$4', #
+ 'UESTA1X_CURRBK': '$3', #
+ 'UESTA0X' : '$ee', #
+ 'UESTA0X_CFGOK': '$80', #
+ 'UESTA0X_OVERFI': '$40', #
+ 'UESTA0X_UNDERFI': '$20', #
+ 'UESTA0X_DTSEQ': '$c', #
+ 'UESTA0X_NBUSYBK': '$3', #
+ 'UECFG1X' : '$ed', #
+ 'UECFG1X_EPSIZE': '$70', #
+ 'UECFG1X_EPBK': '$c', #
+ 'UECFG1X_ALLOC': '$2', #
+ 'UECFG0X' : '$ec', #
+ 'UECFG0X_EPTYPE': '$c0', #
+ 'UECFG0X_EPDIR': '$1', #
+ 'UECONX' : '$eb', #
+ 'UECONX_STALLRQ': '$20', #
+ 'UECONX_STALLRQC': '$10', #
+ 'UECONX_RSTDT': '$8', #
+ 'UECONX_EPEN': '$1', #
+ 'UERST' : '$ea', #
+ 'UERST_EPRST': '$1f', #
+ 'UENUM' : '$e9', #
+ 'UEINTX' : '$e8', #
+ 'UEINTX_FIFOCON': '$80', #
+ 'UEINTX_NAKINI': '$40', #
+ 'UEINTX_RWAL': '$20', #
+ 'UEINTX_NAKOUTI': '$10', #
+ 'UEINTX_RXSTPI': '$8', #
+ 'UEINTX_RXOUTI': '$4', #
+ 'UEINTX_STALLEDI': '$2', #
+ 'UEINTX_TXINI': '$1', #
+ 'UDMFN' : '$e6', #
+ 'UDMFN_FNCERR': '$10', #
+ 'UDFNUM' : '$e4', #
+ 'UDADDR' : '$e3', #
+ 'UDADDR_ADDEN': '$80', #
+ 'UDADDR_UADD': '$7f', #
+ 'UDIEN' : '$e2', #
+ 'UDIEN_UPRSME': '$40', #
+ 'UDIEN_EORSME': '$20', #
+ 'UDIEN_WAKEUPE': '$10', #
+ 'UDIEN_EORSTE': '$8', #
+ 'UDIEN_SOFE': '$4', #
+ 'UDIEN_SUSPE': '$1', #
+ 'UDINT' : '$e1', #
+ 'UDINT_UPRSMI': '$40', #
+ 'UDINT_EORSMI': '$20', #
+ 'UDINT_WAKEUPI': '$10', #
+ 'UDINT_EORSTI': '$8', #
+ 'UDINT_SOFI': '$4', #
+ 'UDINT_SUSPI': '$1', #
+ 'UDCON' : '$e0', #
+ 'UDCON_RSTCPU': '$4', #
+ 'UDCON_RMWKUP': '$2', #
+ 'UDCON_DETACH': '$1', #
+ 'USBCON' : '$d8', # USB General Control Register
+ 'USBCON_USBE': '$80', #
+ 'USBCON_FRZCLK': '$20', #
+ 'REGCR' : '$63', # Regulator Control Register
+ 'REGCR_REGDIS': '$1', #
+
+# Module PS2
+ 'UPOE' : '$fb', #
+ 'UPOE_UPWE': '$c0', #
+ 'UPOE_UPDRV': '$30', #
+ 'UPOE_SCKI': '$8', #
+ 'UPOE_DATAI': '$4', #
+ 'UPOE_DPI': '$2', #
+ 'UPOE_DMI': '$1', #
+ 'PS2CON' : '$fa', # PS2 Pad Enable register
+ 'PS2CON_PS2EN': '$1', # Enable
+
+# Module CPU
+ 'SREG' : '$5f', # Status Register
+ 'SREG_I': '$80', # Global Interrupt Enable
+ 'SREG_T': '$40', # Bit Copy Storage
+ 'SREG_H': '$20', # Half Carry Flag
+ 'SREG_S': '$10', # Sign Bit
+ 'SREG_V': '$8', # Two's Complement Overflow Flag
+ 'SREG_N': '$4', # Negative Flag
+ 'SREG_Z': '$2', # Zero Flag
+ 'SREG_C': '$1', # Carry Flag
+ 'SP' : '$5d', # Stack Pointer
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_PUD': '$10', # Pull-up disable
+ 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
+ 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_USBRF': '$20', # USB reset flag
+ 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
+ 'MCUSR_BORF': '$4', # Brown-out Reset Flag
+ 'MCUSR_EXTRF': '$2', # External Reset Flag
+ 'MCUSR_PORF': '$1', # Power-on reset flag
+ 'OSCCAL' : '$66', # Oscillator Calibration Value
+ 'CLKPR' : '$61', #
+ 'CLKPR_CLKPCE': '$80', #
+ 'CLKPR_CLKPS': '$f', #
+ 'SMCR' : '$53', # Sleep Mode Control Register
+ 'SMCR_SM': '$e', # Sleep Mode Select bits
+ 'SMCR_SE': '$1', # Sleep Enable
+ 'EIND' : '$5c', # Extended Indirect Register
+ 'GPIOR2' : '$4b', # General Purpose IO Register 2
+ 'GPIOR2_GPIOR': '$ff', # General Purpose IO Register 2
+ 'GPIOR1' : '$4a', # General Purpose IO Register 1
+ 'GPIOR1_GPIOR': '$ff', # General Purpose IO Register 1
+ 'GPIOR0' : '$3e', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR07': '$80', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR06': '$40', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR05': '$20', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR04': '$10', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR03': '$8', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR02': '$4', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR01': '$2', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR00': '$1', # General Purpose IO Register 0
+ 'PRR1' : '$65', # Power Reduction Register1
+ 'PRR1_PRUSB': '$80', # Power Reduction USB
+ 'PRR1_PRUSART1': '$1', # Power Reduction USART1
+ 'PRR0' : '$64', # Power Reduction Register0
+ 'PRR0_PRTIM0': '$20', # Power Reduction Timer/Counter0
+ 'PRR0_PRTIM1': '$8', # Power Reduction Timer/Counter1
+ 'PRR0_PRSPI': '$4', # Power Reduction Serial Periphe
+ 'CLKSTA' : '$d2', #
+ 'CLKSTA_RCON': '$2', #
+ 'CLKSTA_EXTON': '$1', #
+ 'CLKSEL1' : '$d1', #
+ 'CLKSEL1_RCCKSEL': '$f0', #
+ 'CLKSEL1_EXCKSEL': '$f', #
+ 'CLKSEL0' : '$d0', #
+ 'CLKSEL0_RCSUT': '$c0', #
+ 'CLKSEL0_EXSUT': '$30', #
+ 'CLKSEL0_RCE': '$8', #
+ 'CLKSEL0_EXTE': '$4', #
+ 'CLKSEL0_CLKS': '$1', #
+ 'DWDR' : '$51', # debugWire communication regist
+
+# Module EXTERNAL_INTERRUPT
+ 'EICRA' : '$69', # External Interrupt Control Reg
+ 'EICRA_ISC3': '$c0', # External Interrupt Sense Contr
+ 'EICRA_ISC2': '$30', # External Interrupt Sense Contr
+ 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
+ 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
+ 'EICRB' : '$6a', # External Interrupt Control Reg
+ 'EICRB_ISC7': '$c0', # External Interrupt 7-4 Sense C
+ 'EICRB_ISC6': '$30', # External Interrupt 7-4 Sense C
+ 'EICRB_ISC5': '$c', # External Interrupt 7-4 Sense C
+ 'EICRB_ISC4': '$3', # External Interrupt 7-4 Sense C
+ 'EIMSK' : '$3d', # External Interrupt Mask Regist
+ 'EIMSK_INT': '$ff', # External Interrupt Request 7 E
+ 'EIFR' : '$3c', # External Interrupt Flag Regist
+ 'EIFR_INTF': '$ff', # External Interrupt Flags
+ 'PCMSK0' : '$6b', # Pin Change Mask Register 0
+ 'PCMSK0_PCINT': '$ff', # Pin Change Enable Masks
+ 'PCMSK1' : '$6c', # Pin Change Mask Register 1
+ 'PCMSK1_PCINT': '$1f', #
+ 'PCIFR' : '$3b', # Pin Change Interrupt Flag Regi
+ 'PCIFR_PCIF': '$3', # Pin Change Interrupt Flags
+ 'PCICR' : '$68', # Pin Change Interrupt Control R
+ 'PCICR_PCIE': '$3', # Pin Change Interrupt Enables
+
+# Module USART1
+ 'UDR1' : '$ce', # USART I/O Data Register
+ 'UCSR1A' : '$c8', # USART Control and Status Regis
+ 'UCSR1A_RXC1': '$80', # USART Receive Complete
+ 'UCSR1A_TXC1': '$40', # USART Transmitt Complete
+ 'UCSR1A_UDRE1': '$20', # USART Data Register Empty
+ 'UCSR1A_FE1': '$10', # Framing Error
+ 'UCSR1A_DOR1': '$8', # Data overRun
+ 'UCSR1A_UPE1': '$4', # Parity Error
+ 'UCSR1A_U2X1': '$2', # Double the USART transmission
+ 'UCSR1A_MPCM1': '$1', # Multi-processor Communication
+ 'UCSR1B' : '$c9', # USART Control and Status Regis
+ 'UCSR1B_RXCIE1': '$80', # RX Complete Interrupt Enable
+ 'UCSR1B_TXCIE1': '$40', # TX Complete Interrupt Enable
+ 'UCSR1B_UDRIE1': '$20', # USART Data register Empty Inte
+ 'UCSR1B_RXEN1': '$10', # Receiver Enable
+ 'UCSR1B_TXEN1': '$8', # Transmitter Enable
+ 'UCSR1B_UCSZ12': '$4', # Character Size
+ 'UCSR1B_RXB81': '$2', # Receive Data Bit 8
+ 'UCSR1B_TXB81': '$1', # Transmit Data Bit 8
+ 'UCSR1C' : '$ca', # USART Control and Status Regis
+ 'UCSR1C_UMSEL1': '$c0', # USART Mode Select
+ 'UCSR1C_UPM1': '$30', # Parity Mode Bits
+ 'UCSR1C_USBS1': '$8', # Stop Bit Select
+ 'UCSR1C_UCSZ1': '$6', # Character Size
+ 'UCSR1C_UCPOL1': '$1', # Clock Polarity
+ 'UCSR1D' : '$cb', # USART Control and Status Regis
+ 'UCSR1D_CTSEN': '$2', # CTS Enable
+ 'UCSR1D_RTSEN': '$1', # RTS Enable
+ 'UBRR1' : '$cc', # USART Baud Rate Register Byte
+
+# Module WATCHDOG
+ 'WDTCSR' : '$60', # Watchdog Timer Control Registe
+ 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
+ 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
+ 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
+ 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
+ 'WDTCSR_WDE': '$8', # Watch Dog Enable
+ 'WDTCKD' : '$62', # Watchdog Timer Clock Divider
+ 'WDTCKD_WDEWIF': '$8', # Watchdog Early Warning Interru
+ 'WDTCKD_WDEWIE': '$4', # Watchdog Early Warning Interru
+ 'WDTCKD_WCLKD': '$3', # Watchdog Timer Clock Dividers
+
+# Module ANALOG_COMPARATOR
+ 'ACSR' : '$50', # Analog Comparator Control And
+ 'ACSR_ACD': '$80', # Analog Comparator Disable
+ 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
+ 'ACSR_ACO': '$20', # Analog Compare Output
+ 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
+ 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
+ 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
+ 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
+ 'DIDR1' : '$7f', #
+ 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
+ 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
+
+# Module PORTC
+ 'PORTC' : '$28', # Port C Data Register
+ 'PORTC_PORTC': '$f0', # Port C Data Register bits
+ 'PORTC_PORTC': '$7', # Port C Data Register bits
+ 'DDRC' : '$27', # Port C Data Direction Register
+ 'DDRC_DDC': '$f0', # Port C Data Direction Register
+ 'DDRC_DDC': '$7', # Port C Data Direction Register
+ 'PINC' : '$26', # Port C Input Pins
+ 'PINC_PINC': '$f0', # Port C Input Pins bits
+ 'PINC_PINC': '$7', # Port C Input Pins bits
+
+ '__amforth_dummy':'0'
+}
diff --git a/amforth-6.5/avr8/devices/at90usb162/words/no-jtag.asm b/amforth-6.5/avr8/devices/at90usb162/words/no-jtag.asm
new file mode 100644
index 0000000..352a4bb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90usb162/words/no-jtag.asm
@@ -0,0 +1,14 @@
+; ( -- )
+; ( -- )
+; MCU
+; disable jtag at runtime
+VE_NOJTAG:
+ .dw $FF05
+ .db "-jtag",0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOJTAG
+XT_NOJTAG:
+ .dw PFA_NOJTAG
+PFA_NOJTAG:
+
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/at90usb162/words/no-wdt.asm b/amforth-6.5/avr8/devices/at90usb162/words/no-wdt.asm
new file mode 100644
index 0000000..ff6ddd1
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90usb162/words/no-wdt.asm
@@ -0,0 +1,34 @@
+; ( -- )
+; MCU
+; disable watch dog timer at runtime
+VE_NOWDT:
+ .dw $ff04
+ .db "-wdt"
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOWDT
+XT_NOWDT:
+ .dw PFA_NOWDT
+PFA_NOWDT:
+
+ in temp1,SREG
+ push temp1
+ ; Turn always off global interrupt.
+ cli
+ ; Reset Watchdog Timer
+ wdr
+ ; Clear WDRF in MCUSR
+ in temp1, MCUSR
+ andi temp1, (0xff & (0<<WDRF))
+ out MCUSR, temp1
+ ; Write logical one to WDCE and WDE
+ ; Keep old prescaler setting to prevent unintentional time-out
+ in_ temp1, WDTCSR
+ ori temp1, (1<<WDCE) | (1<<WDE)
+ out_ WDTCSR, temp1
+ ; Turn off WDT
+ ldi temp1, (0<<WDE)
+ out_ WDTCSR, temp1
+ ; restore status register
+ pop temp1
+ out SREG,temp1
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/at90usb162/words/sleep.asm b/amforth-6.5/avr8/devices/at90usb162/words/sleep.asm
new file mode 100644
index 0000000..256249c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90usb162/words/sleep.asm
@@ -0,0 +1,19 @@
+; ( mode -- )
+; MCU
+; put the controller into the specified sleep mode
+VE_SLEEP:
+ .dw $ff05
+ .db "sleep", 0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_SLEEP
+XT_SLEEP:
+ .dw PFA_SLEEP
+PFA_SLEEP:
+ andi tosl, 7 ; leave only legal mode bits
+ lsl tosl ; move to correct location (bits 3-1)
+ ori tosl, 1 ; set the SE bit
+ out_ SMCR, tosl ; set the sleep config
+ sleep ; nighty-night
+ out_ SMCR, zerol ; 0 protects against accidental sleeps
+ loadtos ; pop argument from stack
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/at90usb646/at90usb646.frt b/amforth-6.5/avr8/devices/at90usb646/at90usb646.frt
new file mode 100644
index 0000000..0f1b47c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90usb646/at90usb646.frt
@@ -0,0 +1,587 @@
+\ Partname: AT90USB646
+\ generated automatically
+
+\ WATCHDOG
+&96 constant WDTCSR \ Watchdog Timer Control Register
+ $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Flag
+ $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Enable
+ $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
+ $10 constant WDTCSR_WDCE \ Watchdog Change Enable
+ $08 constant WDTCSR_WDE \ Watch Dog Enable
+\ PORTA
+&34 constant PORTA \ Port A Data Register
+&33 constant DDRA \ Port A Data Direction Register
+&32 constant PINA \ Port A Input Pins
+\ PORTB
+&37 constant PORTB \ Port B Data Register
+&36 constant DDRB \ Port B Data Direction Register
+&35 constant PINB \ Port B Input Pins
+\ PORTC
+&40 constant PORTC \ Port C Data Register
+&39 constant DDRC \ Port C Data Direction Register
+&38 constant PINC \ Port C Input Pins
+\ PORTD
+&43 constant PORTD \ Port D Data Register
+&42 constant DDRD \ Port D Data Direction Register
+&41 constant PIND \ Port D Input Pins
+\ PORTE
+&46 constant PORTE \ Data Register, Port E
+&45 constant DDRE \ Data Direction Register, Port E
+&44 constant PINE \ Input Pins, Port E
+\ PORTF
+&49 constant PORTF \ Data Register, Port F
+&48 constant DDRF \ Data Direction Register, Port F
+&47 constant PINF \ Input Pins, Port F
+\ CPU
+&95 constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ $08 constant SREG_V \ Two's Complement Overflow Flag
+ $04 constant SREG_N \ Negative Flag
+ $02 constant SREG_Z \ Zero Flag
+ $01 constant SREG_C \ Carry Flag
+&93 constant SP \ Stack Pointer
+&85 constant MCUCR \ MCU Control Register
+ $80 constant MCUCR_JTD \ JTAG Interface Disable
+ $10 constant MCUCR_PUD \ Pull-up disable
+ $02 constant MCUCR_IVSEL \ Interrupt Vector Select
+ $01 constant MCUCR_IVCE \ Interrupt Vector Change Enable
+&84 constant MCUSR \ MCU Status Register
+ $10 constant MCUSR_JTRF \ JTAG Reset Flag
+ $08 constant MCUSR_WDRF \ Watchdog Reset Flag
+ $04 constant MCUSR_BORF \ Brown-out Reset Flag
+ $02 constant MCUSR_EXTRF \ External Reset Flag
+ $01 constant MCUSR_PORF \ Power-on reset flag
+&116 constant XMCRA \ External Memory Control Register A
+ $80 constant XMCRA_SRE \ External SRAM Enable
+ $70 constant XMCRA_SRL \ Wait state page limit
+ $0C constant XMCRA_SRW1 \ Wait state select bit upper page
+ $03 constant XMCRA_SRW0 \ Wait state select bit lower page
+&117 constant XMCRB \ External Memory Control Register B
+ $80 constant XMCRB_XMBK \ External Memory Bus Keeper Enable
+ $07 constant XMCRB_XMM \ External Memory High Mask
+&102 constant OSCCAL \ Oscillator Calibration Value
+&97 constant CLKPR \
+ $80 constant CLKPR_CLKPCE \
+ $0F constant CLKPR_CLKPS \
+&83 constant SMCR \ Sleep Mode Control Register
+ $0E constant SMCR_SM \ Sleep Mode Select bits
+ $01 constant SMCR_SE \ Sleep Enable
+&92 constant EIND \ Extended Indirect Register
+&91 constant RAMPZ \ RAM Page Z Select Register
+&75 constant GPIOR2 \ General Purpose IO Register 2
+ $FF constant GPIOR2_GPIOR \ General Purpose IO Register 2 bis
+&74 constant GPIOR1 \ General Purpose IO Register 1
+ $FF constant GPIOR1_GPIOR \ General Purpose IO Register 1 bis
+&62 constant GPIOR0 \ General Purpose IO Register 0
+ $80 constant GPIOR0_GPIOR07 \ General Purpose IO Register 0 bit 7
+ $40 constant GPIOR0_GPIOR06 \ General Purpose IO Register 0 bit 6
+ $20 constant GPIOR0_GPIOR05 \ General Purpose IO Register 0 bit 5
+ $10 constant GPIOR0_GPIOR04 \ General Purpose IO Register 0 bit 4
+ $08 constant GPIOR0_GPIOR03 \ General Purpose IO Register 0 bit 3
+ $04 constant GPIOR0_GPIOR02 \ General Purpose IO Register 0 bit 2
+ $02 constant GPIOR0_GPIOR01 \ General Purpose IO Register 0 bit 1
+ $01 constant GPIOR0_GPIOR00 \ General Purpose IO Register 0 bit 0
+&101 constant PRR1 \ Power Reduction Register1
+ $80 constant PRR1_PRUSB \ Power Reduction USB
+ $08 constant PRR1_PRTIM3 \ Power Reduction Timer/Counter3
+ $01 constant PRR1_PRUSART1 \ Power Reduction USART1
+&100 constant PRR0 \ Power Reduction Register0
+ $80 constant PRR0_PRTWI \ Power Reduction TWI
+ $40 constant PRR0_PRTIM2 \ Power Reduction Timer/Counter2
+ $20 constant PRR0_PRTIM0 \ Power Reduction Timer/Counter0
+ $08 constant PRR0_PRTIM1 \ Power Reduction Timer/Counter1
+ $04 constant PRR0_PRSPI \ Power Reduction Serial Peripheral Interface
+ $01 constant PRR0_PRADC \ Power Reduction ADC
+\ TWI
+&189 constant TWAMR \ TWI (Slave) Address Mask Register
+ $FE constant TWAMR_TWAM \
+&184 constant TWBR \ TWI Bit Rate register
+&188 constant TWCR \ TWI Control Register
+ $80 constant TWCR_TWINT \ TWI Interrupt Flag
+ $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
+ $20 constant TWCR_TWSTA \ TWI Start Condition Bit
+ $10 constant TWCR_TWSTO \ TWI Stop Condition Bit
+ $08 constant TWCR_TWWC \ TWI Write Collition Flag
+ $04 constant TWCR_TWEN \ TWI Enable Bit
+ $01 constant TWCR_TWIE \ TWI Interrupt Enable
+&185 constant TWSR \ TWI Status Register
+ $F8 constant TWSR_TWS \ TWI Status
+ $03 constant TWSR_TWPS \ TWI Prescaler
+&187 constant TWDR \ TWI Data register
+&186 constant TWAR \ TWI (Slave) Address register
+ $FE constant TWAR_TWA \ TWI (Slave) Address register Bits
+ $01 constant TWAR_TWGCE \ TWI General Call Recognition Enable Bit
+\ SPI
+&76 constant SPCR \ SPI Control Register
+ $80 constant SPCR_SPIE \ SPI Interrupt Enable
+ $40 constant SPCR_SPE \ SPI Enable
+ $20 constant SPCR_DORD \ Data Order
+ $10 constant SPCR_MSTR \ Master/Slave Select
+ $08 constant SPCR_CPOL \ Clock polarity
+ $04 constant SPCR_CPHA \ Clock Phase
+ $03 constant SPCR_SPR \ SPI Clock Rate Selects
+&77 constant SPSR \ SPI Status Register
+ $80 constant SPSR_SPIF \ SPI Interrupt Flag
+ $40 constant SPSR_WCOL \ Write Collision Flag
+ $01 constant SPSR_SPI2X \ Double SPI Speed Bit
+&78 constant SPDR \ SPI Data Register
+\ USART1
+&206 constant UDR1 \ USART I/O Data Register
+&200 constant UCSR1A \ USART Control and Status Register A
+ $80 constant UCSR1A_RXC1 \ USART Receive Complete
+ $40 constant UCSR1A_TXC1 \ USART Transmitt Complete
+ $20 constant UCSR1A_UDRE1 \ USART Data Register Empty
+ $10 constant UCSR1A_FE1 \ Framing Error
+ $08 constant UCSR1A_DOR1 \ Data overRun
+ $04 constant UCSR1A_UPE1 \ Parity Error
+ $02 constant UCSR1A_U2X1 \ Double the USART transmission speed
+ $01 constant UCSR1A_MPCM1 \ Multi-processor Communication Mode
+&201 constant UCSR1B \ USART Control and Status Register B
+ $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable
+ $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable
+ $20 constant UCSR1B_UDRIE1 \ USART Data register Empty Interrupt Enable
+ $10 constant UCSR1B_RXEN1 \ Receiver Enable
+ $08 constant UCSR1B_TXEN1 \ Transmitter Enable
+ $04 constant UCSR1B_UCSZ12 \ Character Size
+ $02 constant UCSR1B_RXB81 \ Receive Data Bit 8
+ $01 constant UCSR1B_TXB81 \ Transmit Data Bit 8
+&202 constant UCSR1C \ USART Control and Status Register C
+ $C0 constant UCSR1C_UMSEL1 \ USART Mode Select
+ $30 constant UCSR1C_UPM1 \ Parity Mode Bits
+ $08 constant UCSR1C_USBS1 \ Stop Bit Select
+ $06 constant UCSR1C_UCSZ1 \ Character Size
+ $01 constant UCSR1C_UCPOL1 \ Clock Polarity
+&204 constant UBRR1 \ USART Baud Rate Register Bytes
+\ USB_DEVICE
+&244 constant UEINT \
+&243 constant UEBCHX \
+&242 constant UEBCLX \
+&241 constant UEDATX \
+&240 constant UEIENX \
+ $80 constant UEIENX_FLERRE \
+ $40 constant UEIENX_NAKINE \
+ $10 constant UEIENX_NAKOUTE \
+ $08 constant UEIENX_RXSTPE \
+ $04 constant UEIENX_RXOUTE \
+ $02 constant UEIENX_STALLEDE \
+ $01 constant UEIENX_TXINE \
+&239 constant UESTA1X \
+ $04 constant UESTA1X_CTRLDIR \
+ $03 constant UESTA1X_CURRBK \
+&238 constant UESTA0X \
+ $80 constant UESTA0X_CFGOK \
+ $40 constant UESTA0X_OVERFI \
+ $20 constant UESTA0X_UNDERFI \
+ $0C constant UESTA0X_DTSEQ \
+ $03 constant UESTA0X_NBUSYBK \
+&237 constant UECFG1X \
+ $70 constant UECFG1X_EPSIZE \
+ $0C constant UECFG1X_EPBK \
+ $02 constant UECFG1X_ALLOC \
+&236 constant UECFG0X \
+ $C0 constant UECFG0X_EPTYPE \
+ $01 constant UECFG0X_EPDIR \
+&235 constant UECONX \
+ $20 constant UECONX_STALLRQ \
+ $10 constant UECONX_STALLRQC \
+ $08 constant UECONX_RSTDT \
+ $01 constant UECONX_EPEN \
+&234 constant UERST \
+ $7F constant UERST_EPRST \
+&233 constant UENUM \
+&232 constant UEINTX \
+ $80 constant UEINTX_FIFOCON \
+ $40 constant UEINTX_NAKINI \
+ $20 constant UEINTX_RWAL \
+ $10 constant UEINTX_NAKOUTI \
+ $08 constant UEINTX_RXSTPI \
+ $04 constant UEINTX_RXOUTI \
+ $02 constant UEINTX_STALLEDI \
+ $01 constant UEINTX_TXINI \
+&230 constant UDMFN \
+ $10 constant UDMFN_FNCERR \
+&228 constant UDFNUM \
+&227 constant UDADDR \
+ $80 constant UDADDR_ADDEN \
+ $7F constant UDADDR_UADD \
+&226 constant UDIEN \
+ $40 constant UDIEN_UPRSME \
+ $20 constant UDIEN_EORSME \
+ $10 constant UDIEN_WAKEUPE \
+ $08 constant UDIEN_EORSTE \
+ $04 constant UDIEN_SOFE \
+ $01 constant UDIEN_SUSPE \
+&225 constant UDINT \
+ $40 constant UDINT_UPRSMI \
+ $20 constant UDINT_EORSMI \
+ $10 constant UDINT_WAKEUPI \
+ $08 constant UDINT_EORSTI \
+ $04 constant UDINT_SOFI \
+ $01 constant UDINT_SUSPI \
+&224 constant UDCON \
+ $04 constant UDCON_LSM \
+ $02 constant UDCON_RMWKUP \
+ $01 constant UDCON_DETACH \
+\ USB_GLOBAL
+&223 constant OTGINT \
+ $20 constant OTGINT_STOI \
+ $10 constant OTGINT_HNPERRI \
+ $08 constant OTGINT_ROLEEXI \
+ $04 constant OTGINT_BCERRI \
+ $02 constant OTGINT_VBERRI \
+ $01 constant OTGINT_SRPI \
+&222 constant OTGIEN \
+ $20 constant OTGIEN_STOE \
+ $10 constant OTGIEN_HNPERRE \
+ $08 constant OTGIEN_ROLEEXE \
+ $04 constant OTGIEN_BCERRE \
+ $02 constant OTGIEN_VBERRE \
+ $01 constant OTGIEN_SRPE \
+&221 constant OTGCON \
+ $20 constant OTGCON_HNPREQ \
+ $10 constant OTGCON_SRPREQ \
+ $08 constant OTGCON_SRPSEL \
+ $04 constant OTGCON_VBUSHWC \
+ $02 constant OTGCON_VBUSREQ \
+ $01 constant OTGCON_VBUSRQC \
+&249 constant OTGTCON \
+ $80 constant OTGTCON_OTGTCON_7 \
+ $60 constant OTGTCON_PAGE \
+ $07 constant OTGTCON_VALUE_2 \
+&218 constant USBINT \
+ $02 constant USBINT_IDTI \
+ $01 constant USBINT_VBUSTI \
+&217 constant USBSTA \
+ $08 constant USBSTA_SPEED \
+ $02 constant USBSTA_ID \
+ $01 constant USBSTA_VBUS \
+&216 constant USBCON \ USB General Control Register
+ $80 constant USBCON_USBE \
+ $40 constant USBCON_HOST \
+ $20 constant USBCON_FRZCLK \
+ $10 constant USBCON_OTGPADE \
+ $02 constant USBCON_IDTE \
+ $01 constant USBCON_VBUSTE \
+&215 constant UHWCON \ USB Hardware Configuration Register
+ $80 constant UHWCON_UIMOD \
+ $40 constant UHWCON_UIDE \
+ $10 constant UHWCON_UVCONE \
+ $01 constant UHWCON_UVREGE \
+\ USB_HOST
+&245 constant UPERRX \
+ $60 constant UPERRX_COUNTER \
+ $10 constant UPERRX_CRC16 \
+ $08 constant UPERRX_TIMEOUT \
+ $04 constant UPERRX_PID \
+ $02 constant UPERRX_DATAPID \
+ $01 constant UPERRX_DATATGL \
+&248 constant UPINT \
+&247 constant UPBCHX \
+&246 constant UPBCLX \
+&175 constant UPDATX \
+&174 constant UPIENX \
+ $80 constant UPIENX_FLERRE \
+ $40 constant UPIENX_NAKEDE \
+ $10 constant UPIENX_PERRE \
+ $08 constant UPIENX_TXSTPE \
+ $04 constant UPIENX_TXOUTE \
+ $02 constant UPIENX_RXSTALLE \
+ $01 constant UPIENX_RXINE \
+&173 constant UPCFG2X \
+&172 constant UPSTAX \
+ $80 constant UPSTAX_CFGOK \
+ $40 constant UPSTAX_OVERFI \
+ $20 constant UPSTAX_UNDERFI \
+ $0C constant UPSTAX_DTSEQ \
+ $03 constant UPSTAX_NBUSYK \
+&171 constant UPCFG1X \
+ $70 constant UPCFG1X_PSIZE \
+ $0C constant UPCFG1X_PBK \
+ $02 constant UPCFG1X_ALLOC \
+&170 constant UPCFG0X \
+ $C0 constant UPCFG0X_PTYPE \
+ $30 constant UPCFG0X_PTOKEN \
+ $0F constant UPCFG0X_PEPNUM \
+&169 constant UPCONX \
+ $40 constant UPCONX_PFREEZE \
+ $20 constant UPCONX_INMODE \
+ $08 constant UPCONX_RSTDT \
+ $01 constant UPCONX_PEN \
+&168 constant UPRST \
+ $7F constant UPRST_PRST \
+&167 constant UPNUM \
+&166 constant UPINTX \
+ $80 constant UPINTX_FIFOCON \
+ $40 constant UPINTX_NAKEDI \
+ $20 constant UPINTX_RWAL \
+ $10 constant UPINTX_PERRI \
+ $08 constant UPINTX_TXSTPI \
+ $04 constant UPINTX_TXOUTI \
+ $02 constant UPINTX_RXSTALLI \
+ $01 constant UPINTX_RXINI \
+&165 constant UPINRQX \
+&164 constant UHFLEN \
+&162 constant UHFNUM \
+&161 constant UHADDR \
+&160 constant UHIEN \
+ $40 constant UHIEN_HWUPE \
+ $20 constant UHIEN_HSOFE \
+ $10 constant UHIEN_RXRSME \
+ $08 constant UHIEN_RSMEDE \
+ $04 constant UHIEN_RSTE \
+ $02 constant UHIEN_DDISCE \
+ $01 constant UHIEN_DCONNE \
+&159 constant UHINT \
+ $40 constant UHINT_UHUPI \
+ $20 constant UHINT_HSOFI \
+ $10 constant UHINT_RXRSMI \
+ $08 constant UHINT_RSMEDI \
+ $04 constant UHINT_RSTI \
+ $02 constant UHINT_DDISCI \
+ $01 constant UHINT_DCONNI \
+&158 constant UHCON \
+ $04 constant UHCON_RESUME \
+ $02 constant UHCON_RESET \
+ $01 constant UHCON_SOFEN \
+\ BOOT_LOAD
+&87 constant SPMCSR \ Store Program Memory Control Register
+ $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
+ $20 constant SPMCSR_SIGRD \ Signature Row Read
+ $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
+ $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
+ $04 constant SPMCSR_PGWRT \ Page Write
+ $02 constant SPMCSR_PGERS \ Page Erase
+ $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
+\ EEPROM
+&65 constant EEAR \ EEPROM Address Register Low Bytes
+&64 constant EEDR \ EEPROM Data Register
+&63 constant EECR \ EEPROM Control Register
+ $30 constant EECR_EEPM \ EEPROM Programming Mode Bits
+ $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
+ $04 constant EECR_EEMPE \ EEPROM Master Write Enable
+ $02 constant EECR_EEPE \ EEPROM Write Enable
+ $01 constant EECR_EERE \ EEPROM Read Enable
+\ TIMER_COUNTER_0
+&72 constant OCR0B \ Timer/Counter0 Output Compare Register
+&71 constant OCR0A \ Timer/Counter0 Output Compare Register
+&70 constant TCNT0 \ Timer/Counter0
+&69 constant TCCR0B \ Timer/Counter Control Register B
+ $80 constant TCCR0B_FOC0A \ Force Output Compare A
+ $40 constant TCCR0B_FOC0B \ Force Output Compare B
+ $08 constant TCCR0B_WGM02 \
+ $07 constant TCCR0B_CS0 \ Clock Select
+&68 constant TCCR0A \ Timer/Counter Control Register A
+ $C0 constant TCCR0A_COM0A \ Compare Output Mode, Phase Correct PWM Mode
+ $30 constant TCCR0A_COM0B \ Compare Output Mode, Fast PWm
+ $03 constant TCCR0A_WGM0 \ Waveform Generation Mode
+&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
+ $04 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare Match B Interrupt Enable
+ $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match A Interrupt Enable
+ $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
+&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
+ $04 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare Flag 0B
+ $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0A
+ $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
+&67 constant GTCCR \ General Timer/Counter Control Register
+ $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
+ $01 constant GTCCR_PSRSYNC \ Prescaler Reset Timer/Counter1 and Timer/Counter0
+\ TIMER_COUNTER_2
+&112 constant TIMSK2 \ Timer/Counter Interrupt Mask register
+ $04 constant TIMSK2_OCIE2B \ Timer/Counter2 Output Compare Match B Interrupt Enable
+ $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match A Interrupt Enable
+ $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
+&55 constant TIFR2 \ Timer/Counter Interrupt Flag Register
+ $04 constant TIFR2_OCF2B \ Output Compare Flag 2B
+ $02 constant TIFR2_OCF2A \ Output Compare Flag 2A
+ $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
+&176 constant TCCR2A \ Timer/Counter2 Control Register A
+ $C0 constant TCCR2A_COM2A \ Compare Output Mode bits
+ $30 constant TCCR2A_COM2B \ Compare Output Mode bits
+ $03 constant TCCR2A_WGM2 \ Waveform Genration Mode
+&177 constant TCCR2B \ Timer/Counter2 Control Register B
+ $80 constant TCCR2B_FOC2A \ Force Output Compare A
+ $40 constant TCCR2B_FOC2B \ Force Output Compare B
+ $08 constant TCCR2B_WGM22 \ Waveform Generation Mode
+ $07 constant TCCR2B_CS2 \ Clock Select bits
+&178 constant TCNT2 \ Timer/Counter2
+&180 constant OCR2B \ Timer/Counter2 Output Compare Register B
+&179 constant OCR2A \ Timer/Counter2 Output Compare Register A
+&182 constant ASSR \ Asynchronous Status Register
+ $40 constant ASSR_EXCLK \ Enable External Clock Input
+ $20 constant ASSR_AS2 \ Asynchronous Timer/Counter2
+ $10 constant ASSR_TCN2UB \ Timer/Counter2 Update Busy
+ $08 constant ASSR_OCR2AUB \ Output Compare Register2 Update Busy
+ $04 constant ASSR_OCR2BUB \ Output Compare Register 2 Update Busy
+ $02 constant ASSR_TCR2AUB \ Timer/Counter Control Register2 Update Busy
+ $01 constant ASSR_TCR2BUB \ Timer/Counter Control Register2 Update Busy
+\ TIMER_COUNTER_3
+&144 constant TCCR3A \ Timer/Counter3 Control Register A
+ $C0 constant TCCR3A_COM3A \ Compare Output Mode 1A, bits
+ $30 constant TCCR3A_COM3B \ Compare Output Mode 3B, bits
+ $0C constant TCCR3A_COM3C \ Compare Output Mode 3C, bits
+ $03 constant TCCR3A_WGM3 \ Waveform Generation Mode
+&145 constant TCCR3B \ Timer/Counter3 Control Register B
+ $80 constant TCCR3B_ICNC3 \ Input Capture 3 Noise Canceler
+ $40 constant TCCR3B_ICES3 \ Input Capture 3 Edge Select
+ $18 constant TCCR3B_WGM3 \ Waveform Generation Mode
+ $07 constant TCCR3B_CS3 \ Prescaler source of Timer/Counter 3
+&146 constant TCCR3C \ Timer/Counter 3 Control Register C
+ $80 constant TCCR3C_FOC3A \ Force Output Compare 3A
+ $40 constant TCCR3C_FOC3B \ Force Output Compare 3B
+ $20 constant TCCR3C_FOC3C \ Force Output Compare 3C
+&148 constant TCNT3 \ Timer/Counter3 Bytes
+&152 constant OCR3A \ Timer/Counter3 Output Compare Register A Bytes
+&154 constant OCR3B \ Timer/Counter3 Output Compare Register B Bytes
+&156 constant OCR3C \ Timer/Counter3 Output Compare Register B Bytes
+&150 constant ICR3 \ Timer/Counter3 Input Capture Register Bytes
+&113 constant TIMSK3 \ Timer/Counter3 Interrupt Mask Register
+ $20 constant TIMSK3_ICIE3 \ Timer/Counter3 Input Capture Interrupt Enable
+ $08 constant TIMSK3_OCIE3C \ Timer/Counter3 Output Compare C Match Interrupt Enable
+ $04 constant TIMSK3_OCIE3B \ Timer/Counter3 Output Compare B Match Interrupt Enable
+ $02 constant TIMSK3_OCIE3A \ Timer/Counter3 Output Compare A Match Interrupt Enable
+ $01 constant TIMSK3_TOIE3 \ Timer/Counter3 Overflow Interrupt Enable
+&56 constant TIFR3 \ Timer/Counter3 Interrupt Flag register
+ $20 constant TIFR3_ICF3 \ Input Capture Flag 3
+ $08 constant TIFR3_OCF3C \ Output Compare Flag 3C
+ $04 constant TIFR3_OCF3B \ Output Compare Flag 3B
+ $02 constant TIFR3_OCF3A \ Output Compare Flag 3A
+ $01 constant TIFR3_TOV3 \ Timer/Counter3 Overflow Flag
+\ TIMER_COUNTER_1
+&128 constant TCCR1A \ Timer/Counter1 Control Register A
+ $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
+ $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
+ $0C constant TCCR1A_COM1C \ Compare Output Mode 1C, bits
+ $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
+&129 constant TCCR1B \ Timer/Counter1 Control Register B
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
+ $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
+&130 constant TCCR1C \ Timer/Counter 1 Control Register C
+ $80 constant TCCR1C_FOC1A \ Force Output Compare 1A
+ $40 constant TCCR1C_FOC1B \ Force Output Compare 1B
+ $20 constant TCCR1C_FOC1C \ Force Output Compare 1C
+&132 constant TCNT1 \ Timer/Counter1 Bytes
+&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
+&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
+&140 constant OCR1C \ Timer/Counter1 Output Compare Register C Bytes
+&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
+&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
+ $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
+ $08 constant TIMSK1_OCIE1C \ Timer/Counter1 Output Compare C Match Interrupt Enable
+ $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
+ $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
+ $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
+&54 constant TIFR1 \ Timer/Counter1 Interrupt Flag register
+ $20 constant TIFR1_ICF1 \ Input Capture Flag 1
+ $08 constant TIFR1_OCF1C \ Output Compare Flag 1C
+ $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
+ $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
+ $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
+\ JTAG
+&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
+\ EXTERNAL_INTERRUPT
+&105 constant EICRA \ External Interrupt Control Register A
+ $C0 constant EICRA_ISC3 \ External Interrupt Sense Control Bit
+ $30 constant EICRA_ISC2 \ External Interrupt Sense Control Bit
+ $0C constant EICRA_ISC1 \ External Interrupt Sense Control Bit
+ $03 constant EICRA_ISC0 \ External Interrupt Sense Control Bit
+&106 constant EICRB \ External Interrupt Control Register B
+ $C0 constant EICRB_ISC7 \ External Interrupt 7-4 Sense Control Bit
+ $30 constant EICRB_ISC6 \ External Interrupt 7-4 Sense Control Bit
+ $0C constant EICRB_ISC5 \ External Interrupt 7-4 Sense Control Bit
+ $03 constant EICRB_ISC4 \ External Interrupt 7-4 Sense Control Bit
+&61 constant EIMSK \ External Interrupt Mask Register
+ $FF constant EIMSK_INT \ External Interrupt Request 7 Enable
+&60 constant EIFR \ External Interrupt Flag Register
+ $FF constant EIFR_INTF \ External Interrupt Flags
+&107 constant PCMSK0 \ Pin Change Mask Register 0
+&59 constant PCIFR \ Pin Change Interrupt Flag Register
+ $01 constant PCIFR_PCIF0 \ Pin Change Interrupt Flag 0
+&104 constant PCICR \ Pin Change Interrupt Control Register
+ $01 constant PCICR_PCIE0 \ Pin Change Interrupt Enable 0
+\ AD_CONVERTER
+&124 constant ADMUX \ The ADC multiplexer Selection Register
+ $C0 constant ADMUX_REFS \ Reference Selection Bits
+ $20 constant ADMUX_ADLAR \ Left Adjust Result
+ $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
+&122 constant ADCSRA \ The ADC Control and Status register
+ $80 constant ADCSRA_ADEN \ ADC Enable
+ $40 constant ADCSRA_ADSC \ ADC Start Conversion
+ $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
+ $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
+ $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
+ $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
+&120 constant ADC \ ADC Data Register Bytes
+&123 constant ADCSRB \ ADC Control and Status Register B
+ $80 constant ADCSRB_ADHSM \ ADC High Speed Mode
+ $07 constant ADCSRB_ADTS \ ADC Auto Trigger Sources
+&126 constant DIDR0 \ Digital Input Disable Register 1
+ $80 constant DIDR0_ADC7D \ ADC7 Digital input Disable
+ $40 constant DIDR0_ADC6D \ ADC6 Digital input Disable
+ $20 constant DIDR0_ADC5D \ ADC5 Digital input Disable
+ $10 constant DIDR0_ADC4D \ ADC4 Digital input Disable
+ $08 constant DIDR0_ADC3D \ ADC3 Digital input Disable
+ $04 constant DIDR0_ADC2D \ ADC2 Digital input Disable
+ $02 constant DIDR0_ADC1D \ ADC1 Digital input Disable
+ $01 constant DIDR0_ADC0D \ ADC0 Digital input Disable
+\ ANALOG_COMPARATOR
+&80 constant ACSR \ Analog Comparator Control And Status Register
+ $80 constant ACSR_ACD \ Analog Comparator Disable
+ $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
+ $20 constant ACSR_ACO \ Analog Compare Output
+ $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
+ $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
+ $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
+ $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
+&127 constant DIDR1 \
+ $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
+ $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
+\ PLL
+&73 constant PLLCSR \ PLL Status and Control register
+ $1C constant PLLCSR_PLLP \ PLL prescaler Bits
+ $02 constant PLLCSR_PLLE \ PLL Enable Bit
+ $01 constant PLLCSR_PLOCK \ PLL Lock Status Bit
+
+\ Interrupts
+&2 constant INT0Addr \ External Interrupt Request 0
+&4 constant INT1Addr \ External Interrupt Request 1
+&6 constant INT2Addr \ External Interrupt Request 2
+&8 constant INT3Addr \ External Interrupt Request 3
+&10 constant INT4Addr \ External Interrupt Request 4
+&12 constant INT5Addr \ External Interrupt Request 5
+&14 constant INT6Addr \ External Interrupt Request 6
+&16 constant INT7Addr \ External Interrupt Request 7
+&18 constant PCINT0Addr \ Pin Change Interrupt Request 0
+&20 constant USB_GENAddr \ USB General Interrupt Request
+&22 constant USB_COMAddr \ USB Endpoint/Pipe Interrupt Communication Reque
+&24 constant WDTAddr \ Watchdog Time-out Interrupt
+&26 constant TIMER2_COMPAAddr \ Timer/Counter2 Compare Match A
+&28 constant TIMER2_COMPBAddr \ Timer/Counter2 Compare Match B
+&30 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
+&32 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+&34 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
+&36 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
+&38 constant TIMER1_COMPCAddr \ Timer/Counter1 Compare Match C
+&40 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+&42 constant TIMER0_COMPAAddr \ Timer/Counter0 Compare Match A
+&44 constant TIMER0_COMPBAddr \ Timer/Counter0 Compare Match B
+&46 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
+&48 constant SPI__STCAddr \ SPI Serial Transfer Complete
+&50 constant USART1__RXAddr \ USART1, Rx Complete
+&52 constant USART1__UDREAddr \ USART1 Data register Empty
+&54 constant USART1__TXAddr \ USART1, Tx Complete
+&56 constant ANALOG_COMPAddr \ Analog Comparator
+&58 constant ADCAddr \ ADC Conversion Complete
+&60 constant EE_READYAddr \ EEPROM Ready
+&62 constant TIMER3_CAPTAddr \ Timer/Counter3 Capture Event
+&64 constant TIMER3_COMPAAddr \ Timer/Counter3 Compare Match A
+&66 constant TIMER3_COMPBAddr \ Timer/Counter3 Compare Match B
+&68 constant TIMER3_COMPCAddr \ Timer/Counter3 Compare Match C
+&70 constant TIMER3_OVFAddr \ Timer/Counter3 Overflow
+&72 constant TWIAddr \ 2-wire Serial Interface
+&74 constant SPM_READYAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/at90usb646/device.asm b/amforth-6.5/avr8/devices/at90usb646/device.asm
new file mode 100644
index 0000000..f088ca3
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90usb646/device.asm
@@ -0,0 +1,140 @@
+; Partname: AT90USB646
+; generated automatically, do not edit
+
+.nolist
+ .include "usb646def.inc"
+.list
+
+.equ ramstart = 256
+.equ CELLSIZE = 2
+.macro readflashcell
+ lsl zl
+ rol zh
+ lpm @0, Z+
+ lpm @1, Z+
+.endmacro
+.macro writeflashcell
+ lsl zl
+ rol zh
+.endmacro
+.set WANT_WATCHDOG = 0
+.set WANT_PORTA = 0
+.set WANT_PORTB = 0
+.set WANT_PORTC = 0
+.set WANT_PORTD = 0
+.set WANT_PORTE = 0
+.set WANT_PORTF = 0
+.set WANT_CPU = 0
+.set WANT_TWI = 0
+.set WANT_SPI = 0
+.set WANT_USART1 = 0
+.set WANT_USB_DEVICE = 0
+.set WANT_USB_GLOBAL = 0
+.set WANT_USB_HOST = 0
+.set WANT_BOOT_LOAD = 0
+.set WANT_EEPROM = 0
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_TIMER_COUNTER_2 = 0
+.set WANT_TIMER_COUNTER_3 = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_JTAG = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_AD_CONVERTER = 0
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_PLL = 0
+.equ intvecsize = 2 ; please verify; flash size: 65536 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.org 2
+ rcall isr ; External Interrupt Request 0
+.org 4
+ rcall isr ; External Interrupt Request 1
+.org 6
+ rcall isr ; External Interrupt Request 2
+.org 8
+ rcall isr ; External Interrupt Request 3
+.org 10
+ rcall isr ; External Interrupt Request 4
+.org 12
+ rcall isr ; External Interrupt Request 5
+.org 14
+ rcall isr ; External Interrupt Request 6
+.org 16
+ rcall isr ; External Interrupt Request 7
+.org 18
+ rcall isr ; Pin Change Interrupt Request 0
+.org 20
+ rcall isr ; USB General Interrupt Request
+.org 22
+ rcall isr ; USB Endpoint/Pipe Interrupt Communication Request
+.org 24
+ rcall isr ; Watchdog Time-out Interrupt
+.org 26
+ rcall isr ; Timer/Counter2 Compare Match A
+.org 28
+ rcall isr ; Timer/Counter2 Compare Match B
+.org 30
+ rcall isr ; Timer/Counter2 Overflow
+.org 32
+ rcall isr ; Timer/Counter1 Capture Event
+.org 34
+ rcall isr ; Timer/Counter1 Compare Match A
+.org 36
+ rcall isr ; Timer/Counter1 Compare Match B
+.org 38
+ rcall isr ; Timer/Counter1 Compare Match C
+.org 40
+ rcall isr ; Timer/Counter1 Overflow
+.org 42
+ rcall isr ; Timer/Counter0 Compare Match A
+.org 44
+ rcall isr ; Timer/Counter0 Compare Match B
+.org 46
+ rcall isr ; Timer/Counter0 Overflow
+.org 48
+ rcall isr ; SPI Serial Transfer Complete
+.org 50
+ rcall isr ; USART1, Rx Complete
+.org 52
+ rcall isr ; USART1 Data register Empty
+.org 54
+ rcall isr ; USART1, Tx Complete
+.org 56
+ rcall isr ; Analog Comparator
+.org 58
+ rcall isr ; ADC Conversion Complete
+.org 60
+ rcall isr ; EEPROM Ready
+.org 62
+ rcall isr ; Timer/Counter3 Capture Event
+.org 64
+ rcall isr ; Timer/Counter3 Compare Match A
+.org 66
+ rcall isr ; Timer/Counter3 Compare Match B
+.org 68
+ rcall isr ; Timer/Counter3 Compare Match C
+.org 70
+ rcall isr ; Timer/Counter3 Overflow
+.org 72
+ rcall isr ; 2-wire Serial Interface
+.org 74
+ rcall isr ; Store Program Memory Read
+.equ INTVECTORS = 38
+.nooverlap
+
+; compatability layer (maybe empty)
+
+; controller data area, environment query mcu-info
+mcu_info:
+mcu_ramsize:
+ .dw 4096
+mcu_eepromsize:
+ .dw 2048
+mcu_maxdp:
+ .dw 57344
+mcu_numints:
+ .dw 38
+mcu_name:
+ .dw 10
+ .db "AT90USB646"
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/at90usb646/device.inc b/amforth-6.5/avr8/devices/at90usb646/device.inc
new file mode 100644
index 0000000..7a90f23
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90usb646/device.inc
@@ -0,0 +1,1914 @@
+; Partname: AT90USB646
+; generated automatically, no not edit
+
+.if WANT_WATCHDOG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCSR:
+ .dw $ff06
+ .db "WDTCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCSR
+XT_WDTCSR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCSR:
+ .dw 96
+
+.endif
+.if WANT_PORTA == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Register
+VE_PORTA:
+ .dw $ff05
+ .db "PORTA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTA
+XT_PORTA:
+ .dw PFA_DOVARIABLE
+PFA_PORTA:
+ .dw 34
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Direction Register
+VE_DDRA:
+ .dw $ff04
+ .db "DDRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRA
+XT_DDRA:
+ .dw PFA_DOVARIABLE
+PFA_DDRA:
+ .dw 33
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Input Pins
+VE_PINA:
+ .dw $ff04
+ .db "PINA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINA
+XT_PINA:
+ .dw PFA_DOVARIABLE
+PFA_PINA:
+ .dw 32
+
+.endif
+.if WANT_PORTB == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw 37
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw 36
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw 35
+
+.endif
+.if WANT_PORTC == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Register
+VE_PORTC:
+ .dw $ff05
+ .db "PORTC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTC
+XT_PORTC:
+ .dw PFA_DOVARIABLE
+PFA_PORTC:
+ .dw 40
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Direction Register
+VE_DDRC:
+ .dw $ff04
+ .db "DDRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRC
+XT_DDRC:
+ .dw PFA_DOVARIABLE
+PFA_DDRC:
+ .dw 39
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Input Pins
+VE_PINC:
+ .dw $ff04
+ .db "PINC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINC
+XT_PINC:
+ .dw PFA_DOVARIABLE
+PFA_PINC:
+ .dw 38
+
+.endif
+.if WANT_PORTD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw 43
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw 42
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw 41
+
+.endif
+.if WANT_PORTE == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port E
+VE_PORTE:
+ .dw $ff05
+ .db "PORTE",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTE
+XT_PORTE:
+ .dw PFA_DOVARIABLE
+PFA_PORTE:
+ .dw 46
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port E
+VE_DDRE:
+ .dw $ff04
+ .db "DDRE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRE
+XT_DDRE:
+ .dw PFA_DOVARIABLE
+PFA_DDRE:
+ .dw 45
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port E
+VE_PINE:
+ .dw $ff04
+ .db "PINE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINE
+XT_PINE:
+ .dw PFA_DOVARIABLE
+PFA_PINE:
+ .dw 44
+
+.endif
+.if WANT_PORTF == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port F
+VE_PORTF:
+ .dw $ff05
+ .db "PORTF",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTF
+XT_PORTF:
+ .dw PFA_DOVARIABLE
+PFA_PORTF:
+ .dw 49
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port F
+VE_DDRF:
+ .dw $ff04
+ .db "DDRF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRF
+XT_DDRF:
+ .dw PFA_DOVARIABLE
+PFA_DDRF:
+ .dw 48
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port F
+VE_PINF:
+ .dw $ff04
+ .db "PINF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINF
+XT_PINF:
+ .dw PFA_DOVARIABLE
+PFA_PINF:
+ .dw 47
+
+.endif
+.if WANT_CPU == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw 95
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer
+VE_SP:
+ .dw $ff02
+ .db "SP"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SP
+XT_SP:
+ .dw PFA_DOVARIABLE
+PFA_SP:
+ .dw 93
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw 85
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Status Register
+VE_MCUSR:
+ .dw $ff05
+ .db "MCUSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUSR
+XT_MCUSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUSR:
+ .dw 84
+; ( -- addr ) System Constant
+; R( -- )
+; External Memory Control Register A
+VE_XMCRA:
+ .dw $ff05
+ .db "XMCRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_XMCRA
+XT_XMCRA:
+ .dw PFA_DOVARIABLE
+PFA_XMCRA:
+ .dw 116
+; ( -- addr ) System Constant
+; R( -- )
+; External Memory Control Register B
+VE_XMCRB:
+ .dw $ff05
+ .db "XMCRB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_XMCRB
+XT_XMCRB:
+ .dw PFA_DOVARIABLE
+PFA_XMCRB:
+ .dw 117
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Calibration Value
+VE_OSCCAL:
+ .dw $ff06
+ .db "OSCCAL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSCCAL
+XT_OSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_OSCCAL:
+ .dw 102
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_CLKPR:
+ .dw $ff05
+ .db "CLKPR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKPR
+XT_CLKPR:
+ .dw PFA_DOVARIABLE
+PFA_CLKPR:
+ .dw 97
+; ( -- addr ) System Constant
+; R( -- )
+; Sleep Mode Control Register
+VE_SMCR:
+ .dw $ff04
+ .db "SMCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SMCR
+XT_SMCR:
+ .dw PFA_DOVARIABLE
+PFA_SMCR:
+ .dw 83
+; ( -- addr ) System Constant
+; R( -- )
+; Extended Indirect Register
+VE_EIND:
+ .dw $ff04
+ .db "EIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIND
+XT_EIND:
+ .dw PFA_DOVARIABLE
+PFA_EIND:
+ .dw 92
+; ( -- addr ) System Constant
+; R( -- )
+; RAM Page Z Select Register
+VE_RAMPZ:
+ .dw $ff05
+ .db "RAMPZ",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_RAMPZ
+XT_RAMPZ:
+ .dw PFA_DOVARIABLE
+PFA_RAMPZ:
+ .dw 91
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 2
+VE_GPIOR2:
+ .dw $ff06
+ .db "GPIOR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR2
+XT_GPIOR2:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR2:
+ .dw 75
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 1
+VE_GPIOR1:
+ .dw $ff06
+ .db "GPIOR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR1
+XT_GPIOR1:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR1:
+ .dw 74
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 0
+VE_GPIOR0:
+ .dw $ff06
+ .db "GPIOR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR0
+XT_GPIOR0:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR0:
+ .dw 62
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register1
+VE_PRR1:
+ .dw $ff04
+ .db "PRR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR1
+XT_PRR1:
+ .dw PFA_DOVARIABLE
+PFA_PRR1:
+ .dw 101
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register0
+VE_PRR0:
+ .dw $ff04
+ .db "PRR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR0
+XT_PRR0:
+ .dw PFA_DOVARIABLE
+PFA_PRR0:
+ .dw 100
+
+.endif
+.if WANT_TWI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; TWI (Slave) Address Mask Register
+VE_TWAMR:
+ .dw $ff05
+ .db "TWAMR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWAMR
+XT_TWAMR:
+ .dw PFA_DOVARIABLE
+PFA_TWAMR:
+ .dw 189
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Bit Rate register
+VE_TWBR:
+ .dw $ff04
+ .db "TWBR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWBR
+XT_TWBR:
+ .dw PFA_DOVARIABLE
+PFA_TWBR:
+ .dw 184
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Control Register
+VE_TWCR:
+ .dw $ff04
+ .db "TWCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWCR
+XT_TWCR:
+ .dw PFA_DOVARIABLE
+PFA_TWCR:
+ .dw 188
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Status Register
+VE_TWSR:
+ .dw $ff04
+ .db "TWSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWSR
+XT_TWSR:
+ .dw PFA_DOVARIABLE
+PFA_TWSR:
+ .dw 185
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Data register
+VE_TWDR:
+ .dw $ff04
+ .db "TWDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWDR
+XT_TWDR:
+ .dw PFA_DOVARIABLE
+PFA_TWDR:
+ .dw 187
+; ( -- addr ) System Constant
+; R( -- )
+; TWI (Slave) Address register
+VE_TWAR:
+ .dw $ff04
+ .db "TWAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWAR
+XT_TWAR:
+ .dw PFA_DOVARIABLE
+PFA_TWAR:
+ .dw 186
+
+.endif
+.if WANT_SPI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR:
+ .dw $ff04
+ .db "SPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR
+XT_SPCR:
+ .dw PFA_DOVARIABLE
+PFA_SPCR:
+ .dw 76
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR:
+ .dw $ff04
+ .db "SPSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR
+XT_SPSR:
+ .dw PFA_DOVARIABLE
+PFA_SPSR:
+ .dw 77
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR:
+ .dw $ff04
+ .db "SPDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR
+XT_SPDR:
+ .dw PFA_DOVARIABLE
+PFA_SPDR:
+ .dw 78
+
+.endif
+.if WANT_USART1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR1:
+ .dw $ff04
+ .db "UDR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR1
+XT_UDR1:
+ .dw PFA_DOVARIABLE
+PFA_UDR1:
+ .dw 206
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR1A:
+ .dw $ff06
+ .db "UCSR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1A
+XT_UCSR1A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1A:
+ .dw 200
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR1B:
+ .dw $ff06
+ .db "UCSR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1B
+XT_UCSR1B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1B:
+ .dw 201
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR1C:
+ .dw $ff06
+ .db "UCSR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1C
+XT_UCSR1C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1C:
+ .dw 202
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Bytes
+VE_UBRR1:
+ .dw $ff05
+ .db "UBRR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR1
+XT_UBRR1:
+ .dw PFA_DOVARIABLE
+PFA_UBRR1:
+ .dw 204
+
+.endif
+.if WANT_USB_DEVICE == 1
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UEINT:
+ .dw $ff05
+ .db "UEINT",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UEINT
+XT_UEINT:
+ .dw PFA_DOVARIABLE
+PFA_UEINT:
+ .dw 244
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UEBCHX:
+ .dw $ff06
+ .db "UEBCHX"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UEBCHX
+XT_UEBCHX:
+ .dw PFA_DOVARIABLE
+PFA_UEBCHX:
+ .dw 243
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UEBCLX:
+ .dw $ff06
+ .db "UEBCLX"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UEBCLX
+XT_UEBCLX:
+ .dw PFA_DOVARIABLE
+PFA_UEBCLX:
+ .dw 242
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UEDATX:
+ .dw $ff06
+ .db "UEDATX"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UEDATX
+XT_UEDATX:
+ .dw PFA_DOVARIABLE
+PFA_UEDATX:
+ .dw 241
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UEIENX:
+ .dw $ff06
+ .db "UEIENX"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UEIENX
+XT_UEIENX:
+ .dw PFA_DOVARIABLE
+PFA_UEIENX:
+ .dw 240
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UESTA1X:
+ .dw $ff07
+ .db "UESTA1X",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UESTA1X
+XT_UESTA1X:
+ .dw PFA_DOVARIABLE
+PFA_UESTA1X:
+ .dw 239
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UESTA0X:
+ .dw $ff07
+ .db "UESTA0X",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UESTA0X
+XT_UESTA0X:
+ .dw PFA_DOVARIABLE
+PFA_UESTA0X:
+ .dw 238
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UECFG1X:
+ .dw $ff07
+ .db "UECFG1X",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UECFG1X
+XT_UECFG1X:
+ .dw PFA_DOVARIABLE
+PFA_UECFG1X:
+ .dw 237
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UECFG0X:
+ .dw $ff07
+ .db "UECFG0X",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UECFG0X
+XT_UECFG0X:
+ .dw PFA_DOVARIABLE
+PFA_UECFG0X:
+ .dw 236
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UECONX:
+ .dw $ff06
+ .db "UECONX"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UECONX
+XT_UECONX:
+ .dw PFA_DOVARIABLE
+PFA_UECONX:
+ .dw 235
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UERST:
+ .dw $ff05
+ .db "UERST",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UERST
+XT_UERST:
+ .dw PFA_DOVARIABLE
+PFA_UERST:
+ .dw 234
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UENUM:
+ .dw $ff05
+ .db "UENUM",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UENUM
+XT_UENUM:
+ .dw PFA_DOVARIABLE
+PFA_UENUM:
+ .dw 233
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UEINTX:
+ .dw $ff06
+ .db "UEINTX"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UEINTX
+XT_UEINTX:
+ .dw PFA_DOVARIABLE
+PFA_UEINTX:
+ .dw 232
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UDMFN:
+ .dw $ff05
+ .db "UDMFN",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDMFN
+XT_UDMFN:
+ .dw PFA_DOVARIABLE
+PFA_UDMFN:
+ .dw 230
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UDFNUM:
+ .dw $ff06
+ .db "UDFNUM"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDFNUM
+XT_UDFNUM:
+ .dw PFA_DOVARIABLE
+PFA_UDFNUM:
+ .dw 228
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UDADDR:
+ .dw $ff06
+ .db "UDADDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDADDR
+XT_UDADDR:
+ .dw PFA_DOVARIABLE
+PFA_UDADDR:
+ .dw 227
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UDIEN:
+ .dw $ff05
+ .db "UDIEN",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDIEN
+XT_UDIEN:
+ .dw PFA_DOVARIABLE
+PFA_UDIEN:
+ .dw 226
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UDINT:
+ .dw $ff05
+ .db "UDINT",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDINT
+XT_UDINT:
+ .dw PFA_DOVARIABLE
+PFA_UDINT:
+ .dw 225
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UDCON:
+ .dw $ff05
+ .db "UDCON",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDCON
+XT_UDCON:
+ .dw PFA_DOVARIABLE
+PFA_UDCON:
+ .dw 224
+
+.endif
+.if WANT_USB_GLOBAL == 1
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_OTGINT:
+ .dw $ff06
+ .db "OTGINT"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OTGINT
+XT_OTGINT:
+ .dw PFA_DOVARIABLE
+PFA_OTGINT:
+ .dw 223
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_OTGIEN:
+ .dw $ff06
+ .db "OTGIEN"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OTGIEN
+XT_OTGIEN:
+ .dw PFA_DOVARIABLE
+PFA_OTGIEN:
+ .dw 222
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_OTGCON:
+ .dw $ff06
+ .db "OTGCON"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OTGCON
+XT_OTGCON:
+ .dw PFA_DOVARIABLE
+PFA_OTGCON:
+ .dw 221
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_OTGTCON:
+ .dw $ff07
+ .db "OTGTCON",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OTGTCON
+XT_OTGTCON:
+ .dw PFA_DOVARIABLE
+PFA_OTGTCON:
+ .dw 249
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_USBINT:
+ .dw $ff06
+ .db "USBINT"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USBINT
+XT_USBINT:
+ .dw PFA_DOVARIABLE
+PFA_USBINT:
+ .dw 218
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_USBSTA:
+ .dw $ff06
+ .db "USBSTA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USBSTA
+XT_USBSTA:
+ .dw PFA_DOVARIABLE
+PFA_USBSTA:
+ .dw 217
+; ( -- addr ) System Constant
+; R( -- )
+; USB General Control Register
+VE_USBCON:
+ .dw $ff06
+ .db "USBCON"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USBCON
+XT_USBCON:
+ .dw PFA_DOVARIABLE
+PFA_USBCON:
+ .dw 216
+; ( -- addr ) System Constant
+; R( -- )
+; USB Hardware Configuration Register
+VE_UHWCON:
+ .dw $ff06
+ .db "UHWCON"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UHWCON
+XT_UHWCON:
+ .dw PFA_DOVARIABLE
+PFA_UHWCON:
+ .dw 215
+
+.endif
+.if WANT_USB_HOST == 1
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UPERRX:
+ .dw $ff06
+ .db "UPERRX"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UPERRX
+XT_UPERRX:
+ .dw PFA_DOVARIABLE
+PFA_UPERRX:
+ .dw 245
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UPINT:
+ .dw $ff05
+ .db "UPINT",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UPINT
+XT_UPINT:
+ .dw PFA_DOVARIABLE
+PFA_UPINT:
+ .dw 248
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UPBCHX:
+ .dw $ff06
+ .db "UPBCHX"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UPBCHX
+XT_UPBCHX:
+ .dw PFA_DOVARIABLE
+PFA_UPBCHX:
+ .dw 247
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UPBCLX:
+ .dw $ff06
+ .db "UPBCLX"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UPBCLX
+XT_UPBCLX:
+ .dw PFA_DOVARIABLE
+PFA_UPBCLX:
+ .dw 246
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UPDATX:
+ .dw $ff06
+ .db "UPDATX"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UPDATX
+XT_UPDATX:
+ .dw PFA_DOVARIABLE
+PFA_UPDATX:
+ .dw 175
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UPIENX:
+ .dw $ff06
+ .db "UPIENX"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UPIENX
+XT_UPIENX:
+ .dw PFA_DOVARIABLE
+PFA_UPIENX:
+ .dw 174
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UPCFG2X:
+ .dw $ff07
+ .db "UPCFG2X",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UPCFG2X
+XT_UPCFG2X:
+ .dw PFA_DOVARIABLE
+PFA_UPCFG2X:
+ .dw 173
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UPSTAX:
+ .dw $ff06
+ .db "UPSTAX"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UPSTAX
+XT_UPSTAX:
+ .dw PFA_DOVARIABLE
+PFA_UPSTAX:
+ .dw 172
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UPCFG1X:
+ .dw $ff07
+ .db "UPCFG1X",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UPCFG1X
+XT_UPCFG1X:
+ .dw PFA_DOVARIABLE
+PFA_UPCFG1X:
+ .dw 171
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UPCFG0X:
+ .dw $ff07
+ .db "UPCFG0X",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UPCFG0X
+XT_UPCFG0X:
+ .dw PFA_DOVARIABLE
+PFA_UPCFG0X:
+ .dw 170
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UPCONX:
+ .dw $ff06
+ .db "UPCONX"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UPCONX
+XT_UPCONX:
+ .dw PFA_DOVARIABLE
+PFA_UPCONX:
+ .dw 169
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UPRST:
+ .dw $ff05
+ .db "UPRST",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UPRST
+XT_UPRST:
+ .dw PFA_DOVARIABLE
+PFA_UPRST:
+ .dw 168
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UPNUM:
+ .dw $ff05
+ .db "UPNUM",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UPNUM
+XT_UPNUM:
+ .dw PFA_DOVARIABLE
+PFA_UPNUM:
+ .dw 167
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UPINTX:
+ .dw $ff06
+ .db "UPINTX"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UPINTX
+XT_UPINTX:
+ .dw PFA_DOVARIABLE
+PFA_UPINTX:
+ .dw 166
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UPINRQX:
+ .dw $ff07
+ .db "UPINRQX",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UPINRQX
+XT_UPINRQX:
+ .dw PFA_DOVARIABLE
+PFA_UPINRQX:
+ .dw 165
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UHFLEN:
+ .dw $ff06
+ .db "UHFLEN"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UHFLEN
+XT_UHFLEN:
+ .dw PFA_DOVARIABLE
+PFA_UHFLEN:
+ .dw 164
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UHFNUM:
+ .dw $ff06
+ .db "UHFNUM"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UHFNUM
+XT_UHFNUM:
+ .dw PFA_DOVARIABLE
+PFA_UHFNUM:
+ .dw 162
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UHADDR:
+ .dw $ff06
+ .db "UHADDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UHADDR
+XT_UHADDR:
+ .dw PFA_DOVARIABLE
+PFA_UHADDR:
+ .dw 161
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UHIEN:
+ .dw $ff05
+ .db "UHIEN",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UHIEN
+XT_UHIEN:
+ .dw PFA_DOVARIABLE
+PFA_UHIEN:
+ .dw 160
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UHINT:
+ .dw $ff05
+ .db "UHINT",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UHINT
+XT_UHINT:
+ .dw PFA_DOVARIABLE
+PFA_UHINT:
+ .dw 159
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UHCON:
+ .dw $ff05
+ .db "UHCON",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UHCON
+XT_UHCON:
+ .dw PFA_DOVARIABLE
+PFA_UHCON:
+ .dw 158
+
+.endif
+.if WANT_BOOT_LOAD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control Register
+VE_SPMCSR:
+ .dw $ff06
+ .db "SPMCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCSR
+XT_SPMCSR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCSR:
+ .dw 87
+
+.endif
+.if WANT_EEPROM == 1
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Address Register Low Bytes
+VE_EEAR:
+ .dw $ff04
+ .db "EEAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEAR
+XT_EEAR:
+ .dw PFA_DOVARIABLE
+PFA_EEAR:
+ .dw 65
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw 64
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw 63
+
+.endif
+.if WANT_TIMER_COUNTER_0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0B:
+ .dw $ff05
+ .db "OCR0B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0B
+XT_OCR0B:
+ .dw PFA_DOVARIABLE
+PFA_OCR0B:
+ .dw 72
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0A:
+ .dw $ff05
+ .db "OCR0A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0A
+XT_OCR0A:
+ .dw PFA_DOVARIABLE
+PFA_OCR0A:
+ .dw 71
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw 70
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register B
+VE_TCCR0B:
+ .dw $ff06
+ .db "TCCR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0B
+XT_TCCR0B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0B:
+ .dw 69
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register A
+VE_TCCR0A:
+ .dw $ff06
+ .db "TCCR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0A
+XT_TCCR0A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0A:
+ .dw 68
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Mask Register
+VE_TIMSK0:
+ .dw $ff06
+ .db "TIMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK0
+XT_TIMSK0:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK0:
+ .dw 110
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Flag register
+VE_TIFR0:
+ .dw $ff05
+ .db "TIFR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR0
+XT_TIFR0:
+ .dw PFA_DOVARIABLE
+PFA_TIFR0:
+ .dw 53
+; ( -- addr ) System Constant
+; R( -- )
+; General Timer/Counter Control Register
+VE_GTCCR:
+ .dw $ff05
+ .db "GTCCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GTCCR
+XT_GTCCR:
+ .dw PFA_DOVARIABLE
+PFA_GTCCR:
+ .dw 67
+
+.endif
+.if WANT_TIMER_COUNTER_2 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Mask register
+VE_TIMSK2:
+ .dw $ff06
+ .db "TIMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK2
+XT_TIMSK2:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK2:
+ .dw 112
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Flag Register
+VE_TIFR2:
+ .dw $ff05
+ .db "TIFR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR2
+XT_TIFR2:
+ .dw PFA_DOVARIABLE
+PFA_TIFR2:
+ .dw 55
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register A
+VE_TCCR2A:
+ .dw $ff06
+ .db "TCCR2A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2A
+XT_TCCR2A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2A:
+ .dw 176
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register B
+VE_TCCR2B:
+ .dw $ff06
+ .db "TCCR2B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2B
+XT_TCCR2B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2B:
+ .dw 177
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2
+VE_TCNT2:
+ .dw $ff05
+ .db "TCNT2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT2
+XT_TCNT2:
+ .dw PFA_DOVARIABLE
+PFA_TCNT2:
+ .dw 178
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register B
+VE_OCR2B:
+ .dw $ff05
+ .db "OCR2B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2B
+XT_OCR2B:
+ .dw PFA_DOVARIABLE
+PFA_OCR2B:
+ .dw 180
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register A
+VE_OCR2A:
+ .dw $ff05
+ .db "OCR2A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2A
+XT_OCR2A:
+ .dw PFA_DOVARIABLE
+PFA_OCR2A:
+ .dw 179
+; ( -- addr ) System Constant
+; R( -- )
+; Asynchronous Status Register
+VE_ASSR:
+ .dw $ff04
+ .db "ASSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ASSR
+XT_ASSR:
+ .dw PFA_DOVARIABLE
+PFA_ASSR:
+ .dw 182
+
+.endif
+.if WANT_TIMER_COUNTER_3 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Control Register A
+VE_TCCR3A:
+ .dw $ff06
+ .db "TCCR3A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR3A
+XT_TCCR3A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR3A:
+ .dw 144
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Control Register B
+VE_TCCR3B:
+ .dw $ff06
+ .db "TCCR3B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR3B
+XT_TCCR3B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR3B:
+ .dw 145
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter 3 Control Register C
+VE_TCCR3C:
+ .dw $ff06
+ .db "TCCR3C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR3C
+XT_TCCR3C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR3C:
+ .dw 146
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Bytes
+VE_TCNT3:
+ .dw $ff05
+ .db "TCNT3",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT3
+XT_TCNT3:
+ .dw PFA_DOVARIABLE
+PFA_TCNT3:
+ .dw 148
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Output Compare Register A Bytes
+VE_OCR3A:
+ .dw $ff05
+ .db "OCR3A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR3A
+XT_OCR3A:
+ .dw PFA_DOVARIABLE
+PFA_OCR3A:
+ .dw 152
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Output Compare Register B Bytes
+VE_OCR3B:
+ .dw $ff05
+ .db "OCR3B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR3B
+XT_OCR3B:
+ .dw PFA_DOVARIABLE
+PFA_OCR3B:
+ .dw 154
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Output Compare Register B Bytes
+VE_OCR3C:
+ .dw $ff05
+ .db "OCR3C",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR3C
+XT_OCR3C:
+ .dw PFA_DOVARIABLE
+PFA_OCR3C:
+ .dw 156
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Input Capture Register Bytes
+VE_ICR3:
+ .dw $ff04
+ .db "ICR3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR3
+XT_ICR3:
+ .dw PFA_DOVARIABLE
+PFA_ICR3:
+ .dw 150
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Interrupt Mask Register
+VE_TIMSK3:
+ .dw $ff06
+ .db "TIMSK3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK3
+XT_TIMSK3:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK3:
+ .dw 113
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Interrupt Flag register
+VE_TIFR3:
+ .dw $ff05
+ .db "TIFR3",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR3
+XT_TIFR3:
+ .dw PFA_DOVARIABLE
+PFA_TIFR3:
+ .dw 56
+
+.endif
+.if WANT_TIMER_COUNTER_1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw 128
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw 129
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter 1 Control Register C
+VE_TCCR1C:
+ .dw $ff06
+ .db "TCCR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1C
+XT_TCCR1C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1C:
+ .dw 130
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Bytes
+VE_TCNT1:
+ .dw $ff05
+ .db "TCNT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1
+XT_TCNT1:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1:
+ .dw 132
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register A Bytes
+VE_OCR1A:
+ .dw $ff05
+ .db "OCR1A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1A
+XT_OCR1A:
+ .dw PFA_DOVARIABLE
+PFA_OCR1A:
+ .dw 136
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register B Bytes
+VE_OCR1B:
+ .dw $ff05
+ .db "OCR1B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1B
+XT_OCR1B:
+ .dw PFA_DOVARIABLE
+PFA_OCR1B:
+ .dw 138
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register C Bytes
+VE_OCR1C:
+ .dw $ff05
+ .db "OCR1C",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1C
+XT_OCR1C:
+ .dw PFA_DOVARIABLE
+PFA_OCR1C:
+ .dw 140
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Bytes
+VE_ICR1:
+ .dw $ff04
+ .db "ICR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1
+XT_ICR1:
+ .dw PFA_DOVARIABLE
+PFA_ICR1:
+ .dw 134
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Mask Register
+VE_TIMSK1:
+ .dw $ff06
+ .db "TIMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK1
+XT_TIMSK1:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK1:
+ .dw 111
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Flag register
+VE_TIFR1:
+ .dw $ff05
+ .db "TIFR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR1
+XT_TIFR1:
+ .dw PFA_DOVARIABLE
+PFA_TIFR1:
+ .dw 54
+
+.endif
+.if WANT_JTAG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; On-Chip Debug Related Register in I/O Memory
+VE_OCDR:
+ .dw $ff04
+ .db "OCDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCDR
+XT_OCDR:
+ .dw PFA_DOVARIABLE
+PFA_OCDR:
+ .dw 81
+
+.endif
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register A
+VE_EICRA:
+ .dw $ff05
+ .db "EICRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRA
+XT_EICRA:
+ .dw PFA_DOVARIABLE
+PFA_EICRA:
+ .dw 105
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register B
+VE_EICRB:
+ .dw $ff05
+ .db "EICRB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRB
+XT_EICRB:
+ .dw PFA_DOVARIABLE
+PFA_EICRB:
+ .dw 106
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Mask Register
+VE_EIMSK:
+ .dw $ff05
+ .db "EIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIMSK
+XT_EIMSK:
+ .dw PFA_DOVARIABLE
+PFA_EIMSK:
+ .dw 61
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Flag Register
+VE_EIFR:
+ .dw $ff04
+ .db "EIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIFR
+XT_EIFR:
+ .dw PFA_DOVARIABLE
+PFA_EIFR:
+ .dw 60
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 0
+VE_PCMSK0:
+ .dw $ff06
+ .db "PCMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK0
+XT_PCMSK0:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK0:
+ .dw 107
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Interrupt Flag Register
+VE_PCIFR:
+ .dw $ff05
+ .db "PCIFR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCIFR
+XT_PCIFR:
+ .dw PFA_DOVARIABLE
+PFA_PCIFR:
+ .dw 59
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Interrupt Control Register
+VE_PCICR:
+ .dw $ff05
+ .db "PCICR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCICR
+XT_PCICR:
+ .dw PFA_DOVARIABLE
+PFA_PCICR:
+ .dw 104
+
+.endif
+.if WANT_AD_CONVERTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC multiplexer Selection Register
+VE_ADMUX:
+ .dw $ff05
+ .db "ADMUX",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADMUX
+XT_ADMUX:
+ .dw PFA_DOVARIABLE
+PFA_ADMUX:
+ .dw 124
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register
+VE_ADCSRA:
+ .dw $ff06
+ .db "ADCSRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRA
+XT_ADCSRA:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRA:
+ .dw 122
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register Bytes
+VE_ADC:
+ .dw $ff03
+ .db "ADC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADC
+XT_ADC:
+ .dw PFA_DOVARIABLE
+PFA_ADC:
+ .dw 120
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Control and Status Register B
+VE_ADCSRB:
+ .dw $ff06
+ .db "ADCSRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRB
+XT_ADCSRB:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRB:
+ .dw 123
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 1
+VE_DIDR0:
+ .dw $ff05
+ .db "DIDR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR0
+XT_DIDR0:
+ .dw PFA_DOVARIABLE
+PFA_DIDR0:
+ .dw 126
+
+.endif
+.if WANT_ANALOG_COMPARATOR == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Control And Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw 80
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_DIDR1:
+ .dw $ff05
+ .db "DIDR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR1
+XT_DIDR1:
+ .dw PFA_DOVARIABLE
+PFA_DIDR1:
+ .dw 127
+
+.endif
+.if WANT_PLL == 1
+; ( -- addr ) System Constant
+; R( -- )
+; PLL Status and Control register
+VE_PLLCSR:
+ .dw $ff06
+ .db "PLLCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PLLCSR
+XT_PLLCSR:
+ .dw PFA_DOVARIABLE
+PFA_PLLCSR:
+ .dw 73
+
+.endif
diff --git a/amforth-6.5/avr8/devices/at90usb646/device.py b/amforth-6.5/avr8/devices/at90usb646/device.py
new file mode 100644
index 0000000..94d5083
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90usb646/device.py
@@ -0,0 +1,625 @@
+# Generated Automatically
+
+# Partname AT90USB646
+
+MCUREGS = {
+# Interrupt Vectors
+ 'INT0Addr' : '#2', # External Interrupt Request 0
+ 'INT1Addr' : '#4', # External Interrupt Request 1
+ 'INT2Addr' : '#6', # External Interrupt Request 2
+ 'INT3Addr' : '#8', # External Interrupt Request 3
+ 'INT4Addr' : '#10', # External Interrupt Request 4
+ 'INT5Addr' : '#12', # External Interrupt Request 5
+ 'INT6Addr' : '#14', # External Interrupt Request 6
+ 'INT7Addr' : '#16', # External Interrupt Request 7
+ 'PCINT0Addr' : '#18', # Pin Change Interrupt Request 0
+ 'USB_GENAddr' : '#20', # USB General Interrupt Request
+ 'USB_COMAddr' : '#22', # USB Endpoint/Pipe Interrupt Communication Request
+ 'WDTAddr' : '#24', # Watchdog Time-out Interrupt
+ 'TIMER2_COMPAAddr' : '#26', # Timer/Counter2 Compare Match A
+ 'TIMER2_COMPBAddr' : '#28', # Timer/Counter2 Compare Match B
+ 'TIMER2_OVFAddr' : '#30', # Timer/Counter2 Overflow
+ 'TIMER1_CAPTAddr' : '#32', # Timer/Counter1 Capture Event
+ 'TIMER1_COMPAAddr' : '#34', # Timer/Counter1 Compare Match A
+ 'TIMER1_COMPBAddr' : '#36', # Timer/Counter1 Compare Match B
+ 'TIMER1_COMPCAddr' : '#38', # Timer/Counter1 Compare Match C
+ 'TIMER1_OVFAddr' : '#40', # Timer/Counter1 Overflow
+ 'TIMER0_COMPAAddr' : '#42', # Timer/Counter0 Compare Match A
+ 'TIMER0_COMPBAddr' : '#44', # Timer/Counter0 Compare Match B
+ 'TIMER0_OVFAddr' : '#46', # Timer/Counter0 Overflow
+ 'SPI_STCAddr' : '#48', # SPI Serial Transfer Complete
+ 'USART1_RXAddr' : '#50', # USART1, Rx Complete
+ 'USART1_UDREAddr' : '#52', # USART1 Data register Empty
+ 'USART1_TXAddr' : '#54', # USART1, Tx Complete
+ 'ANALOG_COMPAddr' : '#56', # Analog Comparator
+ 'ADCAddr' : '#58', # ADC Conversion Complete
+ 'EE_READYAddr' : '#60', # EEPROM Ready
+ 'TIMER3_CAPTAddr' : '#62', # Timer/Counter3 Capture Event
+ 'TIMER3_COMPAAddr' : '#64', # Timer/Counter3 Compare Match A
+ 'TIMER3_COMPBAddr' : '#66', # Timer/Counter3 Compare Match B
+ 'TIMER3_COMPCAddr' : '#68', # Timer/Counter3 Compare Match C
+ 'TIMER3_OVFAddr' : '#70', # Timer/Counter3 Overflow
+ 'TWIAddr' : '#72', # 2-wire Serial Interface
+ 'SPM_READYAddr' : '#74', # Store Program Memory Read
+
+# Module WATCHDOG
+ 'WDTCSR' : '$60', # Watchdog Timer Control Registe
+ 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
+ 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
+ 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
+ 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
+ 'WDTCSR_WDE': '$8', # Watch Dog Enable
+
+# Module PORTA
+ 'PORTA' : '$22', # Port A Data Register
+ 'DDRA' : '$21', # Port A Data Direction Register
+ 'PINA' : '$20', # Port A Input Pins
+
+# Module PORTB
+ 'PORTB' : '$25', # Port B Data Register
+ 'DDRB' : '$24', # Port B Data Direction Register
+ 'PINB' : '$23', # Port B Input Pins
+
+# Module PORTC
+ 'PORTC' : '$28', # Port C Data Register
+ 'DDRC' : '$27', # Port C Data Direction Register
+ 'PINC' : '$26', # Port C Input Pins
+
+# Module PORTD
+ 'PORTD' : '$2b', # Port D Data Register
+ 'DDRD' : '$2a', # Port D Data Direction Register
+ 'PIND' : '$29', # Port D Input Pins
+
+# Module PORTE
+ 'PORTE' : '$2e', # Data Register, Port E
+ 'DDRE' : '$2d', # Data Direction Register, Port
+ 'PINE' : '$2c', # Input Pins, Port E
+
+# Module PORTF
+ 'PORTF' : '$31', # Data Register, Port F
+ 'DDRF' : '$30', # Data Direction Register, Port
+ 'PINF' : '$2f', # Input Pins, Port F
+
+# Module CPU
+ 'SREG' : '$5f', # Status Register
+ 'SREG_I': '$80', # Global Interrupt Enable
+ 'SREG_T': '$40', # Bit Copy Storage
+ 'SREG_H': '$20', # Half Carry Flag
+ 'SREG_S': '$10', # Sign Bit
+ 'SREG_V': '$8', # Two's Complement Overflow Flag
+ 'SREG_N': '$4', # Negative Flag
+ 'SREG_Z': '$2', # Zero Flag
+ 'SREG_C': '$1', # Carry Flag
+ 'SP' : '$5d', # Stack Pointer
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_JTD': '$80', # JTAG Interface Disable
+ 'MCUCR_PUD': '$10', # Pull-up disable
+ 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
+ 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+ 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
+ 'MCUSR_BORF': '$4', # Brown-out Reset Flag
+ 'MCUSR_EXTRF': '$2', # External Reset Flag
+ 'MCUSR_PORF': '$1', # Power-on reset flag
+ 'XMCRA' : '$74', # External Memory Control Regist
+ 'XMCRA_SRE': '$80', # External SRAM Enable
+ 'XMCRA_SRL': '$70', # Wait state page limit
+ 'XMCRA_SRW1': '$c', # Wait state select bit upper pa
+ 'XMCRA_SRW0': '$3', # Wait state select bit lower pa
+ 'XMCRB' : '$75', # External Memory Control Regist
+ 'XMCRB_XMBK': '$80', # External Memory Bus Keeper Ena
+ 'XMCRB_XMM': '$7', # External Memory High Mask
+ 'OSCCAL' : '$66', # Oscillator Calibration Value
+ 'CLKPR' : '$61', #
+ 'CLKPR_CLKPCE': '$80', #
+ 'CLKPR_CLKPS': '$f', #
+ 'SMCR' : '$53', # Sleep Mode Control Register
+ 'SMCR_SM': '$e', # Sleep Mode Select bits
+ 'SMCR_SE': '$1', # Sleep Enable
+ 'EIND' : '$5c', # Extended Indirect Register
+ 'RAMPZ' : '$5b', # RAM Page Z Select Register
+ 'GPIOR2' : '$4b', # General Purpose IO Register 2
+ 'GPIOR2_GPIOR': '$ff', # General Purpose IO Register 2
+ 'GPIOR1' : '$4a', # General Purpose IO Register 1
+ 'GPIOR1_GPIOR': '$ff', # General Purpose IO Register 1
+ 'GPIOR0' : '$3e', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR07': '$80', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR06': '$40', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR05': '$20', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR04': '$10', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR03': '$8', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR02': '$4', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR01': '$2', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR00': '$1', # General Purpose IO Register 0
+ 'PRR1' : '$65', # Power Reduction Register1
+ 'PRR1_PRUSB': '$80', # Power Reduction USB
+ 'PRR1_PRTIM3': '$8', # Power Reduction Timer/Counter3
+ 'PRR1_PRUSART1': '$1', # Power Reduction USART1
+ 'PRR0' : '$64', # Power Reduction Register0
+ 'PRR0_PRTWI': '$80', # Power Reduction TWI
+ 'PRR0_PRTIM2': '$40', # Power Reduction Timer/Counter2
+ 'PRR0_PRTIM0': '$20', # Power Reduction Timer/Counter0
+ 'PRR0_PRTIM1': '$8', # Power Reduction Timer/Counter1
+ 'PRR0_PRSPI': '$4', # Power Reduction Serial Periphe
+ 'PRR0_PRADC': '$1', # Power Reduction ADC
+
+# Module TWI
+ 'TWAMR' : '$bd', # TWI (Slave) Address Mask Regis
+ 'TWAMR_TWAM': '$fe', #
+ 'TWBR' : '$b8', # TWI Bit Rate register
+ 'TWCR' : '$bc', # TWI Control Register
+ 'TWCR_TWINT': '$80', # TWI Interrupt Flag
+ 'TWCR_TWEA': '$40', # TWI Enable Acknowledge Bit
+ 'TWCR_TWSTA': '$20', # TWI Start Condition Bit
+ 'TWCR_TWSTO': '$10', # TWI Stop Condition Bit
+ 'TWCR_TWWC': '$8', # TWI Write Collition Flag
+ 'TWCR_TWEN': '$4', # TWI Enable Bit
+ 'TWCR_TWIE': '$1', # TWI Interrupt Enable
+ 'TWSR' : '$b9', # TWI Status Register
+ 'TWSR_TWS': '$f8', # TWI Status
+ 'TWSR_TWPS': '$3', # TWI Prescaler
+ 'TWDR' : '$bb', # TWI Data register
+ 'TWAR' : '$ba', # TWI (Slave) Address register
+ 'TWAR_TWA': '$fe', # TWI (Slave) Address register B
+ 'TWAR_TWGCE': '$1', # TWI General Call Recognition E
+
+# Module SPI
+ 'SPCR' : '$4c', # SPI Control Register
+ 'SPCR_SPIE': '$80', # SPI Interrupt Enable
+ 'SPCR_SPE': '$40', # SPI Enable
+ 'SPCR_DORD': '$20', # Data Order
+ 'SPCR_MSTR': '$10', # Master/Slave Select
+ 'SPCR_CPOL': '$8', # Clock polarity
+ 'SPCR_CPHA': '$4', # Clock Phase
+ 'SPCR_SPR': '$3', # SPI Clock Rate Selects
+ 'SPSR' : '$4d', # SPI Status Register
+ 'SPSR_SPIF': '$80', # SPI Interrupt Flag
+ 'SPSR_WCOL': '$40', # Write Collision Flag
+ 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
+ 'SPDR' : '$4e', # SPI Data Register
+
+# Module USART1
+ 'UDR1' : '$ce', # USART I/O Data Register
+ 'UCSR1A' : '$c8', # USART Control and Status Regis
+ 'UCSR1A_RXC1': '$80', # USART Receive Complete
+ 'UCSR1A_TXC1': '$40', # USART Transmitt Complete
+ 'UCSR1A_UDRE1': '$20', # USART Data Register Empty
+ 'UCSR1A_FE1': '$10', # Framing Error
+ 'UCSR1A_DOR1': '$8', # Data overRun
+ 'UCSR1A_UPE1': '$4', # Parity Error
+ 'UCSR1A_U2X1': '$2', # Double the USART transmission
+ 'UCSR1A_MPCM1': '$1', # Multi-processor Communication
+ 'UCSR1B' : '$c9', # USART Control and Status Regis
+ 'UCSR1B_RXCIE1': '$80', # RX Complete Interrupt Enable
+ 'UCSR1B_TXCIE1': '$40', # TX Complete Interrupt Enable
+ 'UCSR1B_UDRIE1': '$20', # USART Data register Empty Inte
+ 'UCSR1B_RXEN1': '$10', # Receiver Enable
+ 'UCSR1B_TXEN1': '$8', # Transmitter Enable
+ 'UCSR1B_UCSZ12': '$4', # Character Size
+ 'UCSR1B_RXB81': '$2', # Receive Data Bit 8
+ 'UCSR1B_TXB81': '$1', # Transmit Data Bit 8
+ 'UCSR1C' : '$ca', # USART Control and Status Regis
+ 'UCSR1C_UMSEL1': '$c0', # USART Mode Select
+ 'UCSR1C_UPM1': '$30', # Parity Mode Bits
+ 'UCSR1C_USBS1': '$8', # Stop Bit Select
+ 'UCSR1C_UCSZ1': '$6', # Character Size
+ 'UCSR1C_UCPOL1': '$1', # Clock Polarity
+ 'UBRR1' : '$cc', # USART Baud Rate Register Byte
+
+# Module USB_DEVICE
+ 'UEINT' : '$f4', #
+ 'UEBCHX' : '$f3', #
+ 'UEBCLX' : '$f2', #
+ 'UEDATX' : '$f1', #
+ 'UEIENX' : '$f0', #
+ 'UEIENX_FLERRE': '$80', #
+ 'UEIENX_NAKINE': '$40', #
+ 'UEIENX_NAKOUTE': '$10', #
+ 'UEIENX_RXSTPE': '$8', #
+ 'UEIENX_RXOUTE': '$4', #
+ 'UEIENX_STALLEDE': '$2', #
+ 'UEIENX_TXINE': '$1', #
+ 'UESTA1X' : '$ef', #
+ 'UESTA1X_CTRLDIR': '$4', #
+ 'UESTA1X_CURRBK': '$3', #
+ 'UESTA0X' : '$ee', #
+ 'UESTA0X_CFGOK': '$80', #
+ 'UESTA0X_OVERFI': '$40', #
+ 'UESTA0X_UNDERFI': '$20', #
+ 'UESTA0X_DTSEQ': '$c', #
+ 'UESTA0X_NBUSYBK': '$3', #
+ 'UECFG1X' : '$ed', #
+ 'UECFG1X_EPSIZE': '$70', #
+ 'UECFG1X_EPBK': '$c', #
+ 'UECFG1X_ALLOC': '$2', #
+ 'UECFG0X' : '$ec', #
+ 'UECFG0X_EPTYPE': '$c0', #
+ 'UECFG0X_EPDIR': '$1', #
+ 'UECONX' : '$eb', #
+ 'UECONX_STALLRQ': '$20', #
+ 'UECONX_STALLRQC': '$10', #
+ 'UECONX_RSTDT': '$8', #
+ 'UECONX_EPEN': '$1', #
+ 'UERST' : '$ea', #
+ 'UERST_EPRST': '$7f', #
+ 'UENUM' : '$e9', #
+ 'UEINTX' : '$e8', #
+ 'UEINTX_FIFOCON': '$80', #
+ 'UEINTX_NAKINI': '$40', #
+ 'UEINTX_RWAL': '$20', #
+ 'UEINTX_NAKOUTI': '$10', #
+ 'UEINTX_RXSTPI': '$8', #
+ 'UEINTX_RXOUTI': '$4', #
+ 'UEINTX_STALLEDI': '$2', #
+ 'UEINTX_TXINI': '$1', #
+ 'UDMFN' : '$e6', #
+ 'UDMFN_FNCERR': '$10', #
+ 'UDFNUM' : '$e4', #
+ 'UDADDR' : '$e3', #
+ 'UDADDR_ADDEN': '$80', #
+ 'UDADDR_UADD': '$7f', #
+ 'UDIEN' : '$e2', #
+ 'UDIEN_UPRSME': '$40', #
+ 'UDIEN_EORSME': '$20', #
+ 'UDIEN_WAKEUPE': '$10', #
+ 'UDIEN_EORSTE': '$8', #
+ 'UDIEN_SOFE': '$4', #
+ 'UDIEN_SUSPE': '$1', #
+ 'UDINT' : '$e1', #
+ 'UDINT_UPRSMI': '$40', #
+ 'UDINT_EORSMI': '$20', #
+ 'UDINT_WAKEUPI': '$10', #
+ 'UDINT_EORSTI': '$8', #
+ 'UDINT_SOFI': '$4', #
+ 'UDINT_SUSPI': '$1', #
+ 'UDCON' : '$e0', #
+ 'UDCON_LSM': '$4', #
+ 'UDCON_RMWKUP': '$2', #
+ 'UDCON_DETACH': '$1', #
+
+# Module USB_GLOBAL
+ 'OTGINT' : '$df', #
+ 'OTGINT_STOI': '$20', #
+ 'OTGINT_HNPERRI': '$10', #
+ 'OTGINT_ROLEEXI': '$8', #
+ 'OTGINT_BCERRI': '$4', #
+ 'OTGINT_VBERRI': '$2', #
+ 'OTGINT_SRPI': '$1', #
+ 'OTGIEN' : '$de', #
+ 'OTGIEN_STOE': '$20', #
+ 'OTGIEN_HNPERRE': '$10', #
+ 'OTGIEN_ROLEEXE': '$8', #
+ 'OTGIEN_BCERRE': '$4', #
+ 'OTGIEN_VBERRE': '$2', #
+ 'OTGIEN_SRPE': '$1', #
+ 'OTGCON' : '$dd', #
+ 'OTGCON_HNPREQ': '$20', #
+ 'OTGCON_SRPREQ': '$10', #
+ 'OTGCON_SRPSEL': '$8', #
+ 'OTGCON_VBUSHWC': '$4', #
+ 'OTGCON_VBUSREQ': '$2', #
+ 'OTGCON_VBUSRQC': '$1', #
+ 'OTGTCON' : '$f9', #
+ 'OTGTCON_OTGTCON_7': '$80', #
+ 'OTGTCON_PAGE': '$60', #
+ 'OTGTCON_VALUE_2': '$7', #
+ 'USBINT' : '$da', #
+ 'USBINT_IDTI': '$2', #
+ 'USBINT_VBUSTI': '$1', #
+ 'USBSTA' : '$d9', #
+ 'USBSTA_SPEED': '$8', #
+ 'USBSTA_ID': '$2', #
+ 'USBSTA_VBUS': '$1', #
+ 'USBCON' : '$d8', # USB General Control Register
+ 'USBCON_USBE': '$80', #
+ 'USBCON_HOST': '$40', #
+ 'USBCON_FRZCLK': '$20', #
+ 'USBCON_OTGPADE': '$10', #
+ 'USBCON_IDTE': '$2', #
+ 'USBCON_VBUSTE': '$1', #
+ 'UHWCON' : '$d7', # USB Hardware Configuration Reg
+ 'UHWCON_UIMOD': '$80', #
+ 'UHWCON_UIDE': '$40', #
+ 'UHWCON_UVCONE': '$10', #
+ 'UHWCON_UVREGE': '$1', #
+
+# Module USB_HOST
+ 'UPERRX' : '$f5', #
+ 'UPERRX_COUNTER': '$60', #
+ 'UPERRX_CRC16': '$10', #
+ 'UPERRX_TIMEOUT': '$8', #
+ 'UPERRX_PID': '$4', #
+ 'UPERRX_DATAPID': '$2', #
+ 'UPERRX_DATATGL': '$1', #
+ 'UPINT' : '$f8', #
+ 'UPBCHX' : '$f7', #
+ 'UPBCLX' : '$f6', #
+ 'UPDATX' : '$af', #
+ 'UPIENX' : '$ae', #
+ 'UPIENX_FLERRE': '$80', #
+ 'UPIENX_NAKEDE': '$40', #
+ 'UPIENX_PERRE': '$10', #
+ 'UPIENX_TXSTPE': '$8', #
+ 'UPIENX_TXOUTE': '$4', #
+ 'UPIENX_RXSTALLE': '$2', #
+ 'UPIENX_RXINE': '$1', #
+ 'UPCFG2X' : '$ad', #
+ 'UPSTAX' : '$ac', #
+ 'UPSTAX_CFGOK': '$80', #
+ 'UPSTAX_OVERFI': '$40', #
+ 'UPSTAX_UNDERFI': '$20', #
+ 'UPSTAX_DTSEQ': '$c', #
+ 'UPSTAX_NBUSYK': '$3', #
+ 'UPCFG1X' : '$ab', #
+ 'UPCFG1X_PSIZE': '$70', #
+ 'UPCFG1X_PBK': '$c', #
+ 'UPCFG1X_ALLOC': '$2', #
+ 'UPCFG0X' : '$aa', #
+ 'UPCFG0X_PTYPE': '$c0', #
+ 'UPCFG0X_PTOKEN': '$30', #
+ 'UPCFG0X_PEPNUM': '$f', #
+ 'UPCONX' : '$a9', #
+ 'UPCONX_PFREEZE': '$40', #
+ 'UPCONX_INMODE': '$20', #
+ 'UPCONX_RSTDT': '$8', #
+ 'UPCONX_PEN': '$1', #
+ 'UPRST' : '$a8', #
+ 'UPRST_PRST': '$7f', #
+ 'UPNUM' : '$a7', #
+ 'UPINTX' : '$a6', #
+ 'UPINTX_FIFOCON': '$80', #
+ 'UPINTX_NAKEDI': '$40', #
+ 'UPINTX_RWAL': '$20', #
+ 'UPINTX_PERRI': '$10', #
+ 'UPINTX_TXSTPI': '$8', #
+ 'UPINTX_TXOUTI': '$4', #
+ 'UPINTX_RXSTALLI': '$2', #
+ 'UPINTX_RXINI': '$1', #
+ 'UPINRQX' : '$a5', #
+ 'UHFLEN' : '$a4', #
+ 'UHFNUM' : '$a2', #
+ 'UHADDR' : '$a1', #
+ 'UHIEN' : '$a0', #
+ 'UHIEN_HWUPE': '$40', #
+ 'UHIEN_HSOFE': '$20', #
+ 'UHIEN_RXRSME': '$10', #
+ 'UHIEN_RSMEDE': '$8', #
+ 'UHIEN_RSTE': '$4', #
+ 'UHIEN_DDISCE': '$2', #
+ 'UHIEN_DCONNE': '$1', #
+ 'UHINT' : '$9f', #
+ 'UHINT_UHUPI': '$40', #
+ 'UHINT_HSOFI': '$20', #
+ 'UHINT_RXRSMI': '$10', #
+ 'UHINT_RSMEDI': '$8', #
+ 'UHINT_RSTI': '$4', #
+ 'UHINT_DDISCI': '$2', #
+ 'UHINT_DCONNI': '$1', #
+ 'UHCON' : '$9e', #
+ 'UHCON_RESUME': '$4', #
+ 'UHCON_RESET': '$2', #
+ 'UHCON_SOFEN': '$1', #
+
+# Module BOOT_LOAD
+ 'SPMCSR' : '$57', # Store Program Memory Control R
+ 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
+ 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
+ 'SPMCSR_SIGRD': '$20', # Signature Row Read
+ 'SPMCSR_RWWSRE': '$10', # Read While Write section read
+ 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
+ 'SPMCSR_PGWRT': '$4', # Page Write
+ 'SPMCSR_PGERS': '$2', # Page Erase
+ 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
+
+# Module EEPROM
+ 'EEAR' : '$41', # EEPROM Address Register Low By
+ 'EEDR' : '$40', # EEPROM Data Register
+ 'EECR' : '$3f', # EEPROM Control Register
+ 'EECR_EEPM': '$30', # EEPROM Programming Mode Bits
+ 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
+ 'EECR_EEMPE': '$4', # EEPROM Master Write Enable
+ 'EECR_EEPE': '$2', # EEPROM Write Enable
+ 'EECR_EERE': '$1', # EEPROM Read Enable
+
+# Module TIMER_COUNTER_0
+ 'OCR0B' : '$48', # Timer/Counter0 Output Compare
+ 'OCR0A' : '$47', # Timer/Counter0 Output Compare
+ 'TCNT0' : '$46', # Timer/Counter0
+ 'TCCR0B' : '$45', # Timer/Counter Control Register
+ 'TCCR0B_FOC0A': '$80', # Force Output Compare A
+ 'TCCR0B_FOC0B': '$40', # Force Output Compare B
+ 'TCCR0B_WGM02': '$8', #
+ 'TCCR0B_CS0': '$7', # Clock Select
+ 'TCCR0A' : '$44', # Timer/Counter Control Registe
+ 'TCCR0A_COM0A': '$c0', # Compare Output Mode, Phase Cor
+ 'TCCR0A_COM0B': '$30', # Compare Output Mode, Fast PWm
+ 'TCCR0A_WGM0': '$3', # Waveform Generation Mode
+ 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
+ 'TIMSK0_OCIE0B': '$4', # Timer/Counter0 Output Compare
+ 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
+ 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
+ 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
+ 'TIFR0_OCF0B': '$4', # Timer/Counter0 Output Compare
+ 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
+ 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSRSYNC': '$1', # Prescaler Reset Timer/Counter1
+
+# Module TIMER_COUNTER_2
+ 'TIMSK2' : '$70', # Timer/Counter Interrupt Mask r
+ 'TIMSK2_OCIE2B': '$4', # Timer/Counter2 Output Compare
+ 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
+ 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
+ 'TIFR2' : '$37', # Timer/Counter Interrupt Flag R
+ 'TIFR2_OCF2B': '$4', # Output Compare Flag 2B
+ 'TIFR2_OCF2A': '$2', # Output Compare Flag 2A
+ 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
+ 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
+ 'TCCR2A_COM2A': '$c0', # Compare Output Mode bits
+ 'TCCR2A_COM2B': '$30', # Compare Output Mode bits
+ 'TCCR2A_WGM2': '$3', # Waveform Genration Mode
+ 'TCCR2B' : '$b1', # Timer/Counter2 Control Registe
+ 'TCCR2B_FOC2A': '$80', # Force Output Compare A
+ 'TCCR2B_FOC2B': '$40', # Force Output Compare B
+ 'TCCR2B_WGM22': '$8', # Waveform Generation Mode
+ 'TCCR2B_CS2': '$7', # Clock Select bits
+ 'TCNT2' : '$b2', # Timer/Counter2
+ 'OCR2B' : '$b4', # Timer/Counter2 Output Compare
+ 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
+ 'ASSR' : '$b6', # Asynchronous Status Register
+ 'ASSR_EXCLK': '$40', # Enable External Clock Input
+ 'ASSR_AS2': '$20', # Asynchronous Timer/Counter2
+ 'ASSR_TCN2UB': '$10', # Timer/Counter2 Update Busy
+ 'ASSR_OCR2AUB': '$8', # Output Compare Register2 Updat
+ 'ASSR_OCR2BUB': '$4', # Output Compare Register 2 Upda
+ 'ASSR_TCR2AUB': '$2', # Timer/Counter Control Register
+ 'ASSR_TCR2BUB': '$1', # Timer/Counter Control Register
+ 'GTCCR' : '$43', # General Timer Counter Control
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSRASY': '$2', # Prescaler Reset Timer/Counter2
+
+# Module TIMER_COUNTER_3
+ 'TCCR3A' : '$90', # Timer/Counter3 Control Registe
+ 'TCCR3A_COM3A': '$c0', # Compare Output Mode 1A, bits
+ 'TCCR3A_COM3B': '$30', # Compare Output Mode 3B, bits
+ 'TCCR3A_COM3C': '$c', # Compare Output Mode 3C, bits
+ 'TCCR3A_WGM3': '$3', # Waveform Generation Mode
+ 'TCCR3B' : '$91', # Timer/Counter3 Control Registe
+ 'TCCR3B_ICNC3': '$80', # Input Capture 3 Noise Canceler
+ 'TCCR3B_ICES3': '$40', # Input Capture 3 Edge Select
+ 'TCCR3B_WGM3': '$18', # Waveform Generation Mode
+ 'TCCR3B_CS3': '$7', # Prescaler source of Timer/Coun
+ 'TCCR3C' : '$92', # Timer/Counter 3 Control Regist
+ 'TCCR3C_FOC3A': '$80', # Force Output Compare 3A
+ 'TCCR3C_FOC3B': '$40', # Force Output Compare 3B
+ 'TCCR3C_FOC3C': '$20', # Force Output Compare 3C
+ 'TCNT3' : '$94', # Timer/Counter3 Bytes
+ 'OCR3A' : '$98', # Timer/Counter3 Output Compare
+ 'OCR3B' : '$9a', # Timer/Counter3 Output Compare
+ 'OCR3C' : '$9c', # Timer/Counter3 Output Compare
+ 'ICR3' : '$96', # Timer/Counter3 Input Capture R
+ 'TIMSK3' : '$71', # Timer/Counter3 Interrupt Mask
+ 'TIMSK3_ICIE3': '$20', # Timer/Counter3 Input Capture I
+ 'TIMSK3_OCIE3C': '$8', # Timer/Counter3 Output Compare
+ 'TIMSK3_OCIE3B': '$4', # Timer/Counter3 Output Compare
+ 'TIMSK3_OCIE3A': '$2', # Timer/Counter3 Output Compare
+ 'TIMSK3_TOIE3': '$1', # Timer/Counter3 Overflow Interr
+ 'TIFR3' : '$38', # Timer/Counter3 Interrupt Flag
+ 'TIFR3_ICF3': '$20', # Input Capture Flag 3
+ 'TIFR3_OCF3C': '$8', # Output Compare Flag 3C
+ 'TIFR3_OCF3B': '$4', # Output Compare Flag 3B
+ 'TIFR3_OCF3A': '$2', # Output Compare Flag 3A
+ 'TIFR3_TOV3': '$1', # Timer/Counter3 Overflow Flag
+
+# Module TIMER_COUNTER_1
+ 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
+ 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
+ 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
+ 'TCCR1A_COM1C': '$c', # Compare Output Mode 1C, bits
+ 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
+ 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
+ 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
+ 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
+ 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
+ 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
+ 'TCCR1C' : '$82', # Timer/Counter 1 Control Regist
+ 'TCCR1C_FOC1A': '$80', # Force Output Compare 1A
+ 'TCCR1C_FOC1B': '$40', # Force Output Compare 1B
+ 'TCCR1C_FOC1C': '$20', # Force Output Compare 1C
+ 'TCNT1' : '$84', # Timer/Counter1 Bytes
+ 'OCR1A' : '$88', # Timer/Counter1 Output Compare
+ 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
+ 'OCR1C' : '$8c', # Timer/Counter1 Output Compare
+ 'ICR1' : '$86', # Timer/Counter1 Input Capture R
+ 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
+ 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
+ 'TIMSK1_OCIE1C': '$8', # Timer/Counter1 Output Compare
+ 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
+ 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
+ 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
+ 'TIFR1' : '$36', # Timer/Counter1 Interrupt Flag
+ 'TIFR1_ICF1': '$20', # Input Capture Flag 1
+ 'TIFR1_OCF1C': '$8', # Output Compare Flag 1C
+ 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
+ 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
+ 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
+
+# Module JTAG
+ 'OCDR' : '$51', # On-Chip Debug Related Register
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_JTD': '$80', # JTAG Interface Disable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+
+# Module EXTERNAL_INTERRUPT
+ 'EICRA' : '$69', # External Interrupt Control Reg
+ 'EICRA_ISC3': '$c0', # External Interrupt Sense Contr
+ 'EICRA_ISC2': '$30', # External Interrupt Sense Contr
+ 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
+ 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
+ 'EICRB' : '$6a', # External Interrupt Control Reg
+ 'EICRB_ISC7': '$c0', # External Interrupt 7-4 Sense C
+ 'EICRB_ISC6': '$30', # External Interrupt 7-4 Sense C
+ 'EICRB_ISC5': '$c', # External Interrupt 7-4 Sense C
+ 'EICRB_ISC4': '$3', # External Interrupt 7-4 Sense C
+ 'EIMSK' : '$3d', # External Interrupt Mask Regist
+ 'EIMSK_INT': '$ff', # External Interrupt Request 7 E
+ 'EIFR' : '$3c', # External Interrupt Flag Regist
+ 'EIFR_INTF': '$ff', # External Interrupt Flags
+ 'PCMSK0' : '$6b', # Pin Change Mask Register 0
+ 'PCIFR' : '$3b', # Pin Change Interrupt Flag Regi
+ 'PCIFR_PCIF0': '$1', # Pin Change Interrupt Flag 0
+ 'PCICR' : '$68', # Pin Change Interrupt Control R
+ 'PCICR_PCIE0': '$1', # Pin Change Interrupt Enable 0
+
+# Module AD_CONVERTER
+ 'ADMUX' : '$7c', # The ADC multiplexer Selection
+ 'ADMUX_REFS': '$c0', # Reference Selection Bits
+ 'ADMUX_ADLAR': '$20', # Left Adjust Result
+ 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
+ 'ADCSRA' : '$7a', # The ADC Control and Status reg
+ 'ADCSRA_ADEN': '$80', # ADC Enable
+ 'ADCSRA_ADSC': '$40', # ADC Start Conversion
+ 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
+ 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
+ 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
+ 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
+ 'ADC' : '$78', # ADC Data Register Bytes
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ADHSM': '$80', # ADC High Speed Mode
+ 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Sources
+ 'DIDR0' : '$7e', # Digital Input Disable Register
+ 'DIDR0_ADC7D': '$80', # ADC7 Digital input Disable
+ 'DIDR0_ADC6D': '$40', # ADC6 Digital input Disable
+ 'DIDR0_ADC5D': '$20', # ADC5 Digital input Disable
+ 'DIDR0_ADC4D': '$10', # ADC4 Digital input Disable
+ 'DIDR0_ADC3D': '$8', # ADC3 Digital input Disable
+ 'DIDR0_ADC2D': '$4', # ADC2 Digital input Disable
+ 'DIDR0_ADC1D': '$2', # ADC1 Digital input Disable
+ 'DIDR0_ADC0D': '$1', # ADC0 Digital input Disable
+
+# Module ANALOG_COMPARATOR
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
+ 'ACSR' : '$50', # Analog Comparator Control And
+ 'ACSR_ACD': '$80', # Analog Comparator Disable
+ 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
+ 'ACSR_ACO': '$20', # Analog Compare Output
+ 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
+ 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
+ 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
+ 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
+ 'DIDR1' : '$7f', #
+ 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
+ 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
+
+# Module PLL
+ 'PLLCSR' : '$49', # PLL Status and Control registe
+ 'PLLCSR_PLLP': '$1c', # PLL prescaler Bits
+ 'PLLCSR_PLLE': '$2', # PLL Enable Bit
+ 'PLLCSR_PLOCK': '$1', # PLL Lock Status Bit
+
+ '__amforth_dummy':'0'
+}
diff --git a/amforth-6.5/avr8/devices/at90usb646/words/no-jtag.asm b/amforth-6.5/avr8/devices/at90usb646/words/no-jtag.asm
new file mode 100644
index 0000000..352a4bb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90usb646/words/no-jtag.asm
@@ -0,0 +1,14 @@
+; ( -- )
+; ( -- )
+; MCU
+; disable jtag at runtime
+VE_NOJTAG:
+ .dw $FF05
+ .db "-jtag",0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOJTAG
+XT_NOJTAG:
+ .dw PFA_NOJTAG
+PFA_NOJTAG:
+
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/at90usb646/words/no-wdt.asm b/amforth-6.5/avr8/devices/at90usb646/words/no-wdt.asm
new file mode 100644
index 0000000..ff6ddd1
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90usb646/words/no-wdt.asm
@@ -0,0 +1,34 @@
+; ( -- )
+; MCU
+; disable watch dog timer at runtime
+VE_NOWDT:
+ .dw $ff04
+ .db "-wdt"
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOWDT
+XT_NOWDT:
+ .dw PFA_NOWDT
+PFA_NOWDT:
+
+ in temp1,SREG
+ push temp1
+ ; Turn always off global interrupt.
+ cli
+ ; Reset Watchdog Timer
+ wdr
+ ; Clear WDRF in MCUSR
+ in temp1, MCUSR
+ andi temp1, (0xff & (0<<WDRF))
+ out MCUSR, temp1
+ ; Write logical one to WDCE and WDE
+ ; Keep old prescaler setting to prevent unintentional time-out
+ in_ temp1, WDTCSR
+ ori temp1, (1<<WDCE) | (1<<WDE)
+ out_ WDTCSR, temp1
+ ; Turn off WDT
+ ldi temp1, (0<<WDE)
+ out_ WDTCSR, temp1
+ ; restore status register
+ pop temp1
+ out SREG,temp1
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/at90usb646/words/sleep.asm b/amforth-6.5/avr8/devices/at90usb646/words/sleep.asm
new file mode 100644
index 0000000..256249c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90usb646/words/sleep.asm
@@ -0,0 +1,19 @@
+; ( mode -- )
+; MCU
+; put the controller into the specified sleep mode
+VE_SLEEP:
+ .dw $ff05
+ .db "sleep", 0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_SLEEP
+XT_SLEEP:
+ .dw PFA_SLEEP
+PFA_SLEEP:
+ andi tosl, 7 ; leave only legal mode bits
+ lsl tosl ; move to correct location (bits 3-1)
+ ori tosl, 1 ; set the SE bit
+ out_ SMCR, tosl ; set the sleep config
+ sleep ; nighty-night
+ out_ SMCR, zerol ; 0 protects against accidental sleeps
+ loadtos ; pop argument from stack
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/at90usb647/at90usb647.frt b/amforth-6.5/avr8/devices/at90usb647/at90usb647.frt
new file mode 100644
index 0000000..4c7bc8e
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90usb647/at90usb647.frt
@@ -0,0 +1,587 @@
+\ Partname: AT90USB647
+\ generated automatically
+
+\ WATCHDOG
+&96 constant WDTCSR \ Watchdog Timer Control Register
+ $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Flag
+ $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Enable
+ $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
+ $10 constant WDTCSR_WDCE \ Watchdog Change Enable
+ $08 constant WDTCSR_WDE \ Watch Dog Enable
+\ PORTA
+&34 constant PORTA \ Port A Data Register
+&33 constant DDRA \ Port A Data Direction Register
+&32 constant PINA \ Port A Input Pins
+\ PORTB
+&37 constant PORTB \ Port B Data Register
+&36 constant DDRB \ Port B Data Direction Register
+&35 constant PINB \ Port B Input Pins
+\ PORTC
+&40 constant PORTC \ Port C Data Register
+&39 constant DDRC \ Port C Data Direction Register
+&38 constant PINC \ Port C Input Pins
+\ PORTD
+&43 constant PORTD \ Port D Data Register
+&42 constant DDRD \ Port D Data Direction Register
+&41 constant PIND \ Port D Input Pins
+\ PORTE
+&46 constant PORTE \ Data Register, Port E
+&45 constant DDRE \ Data Direction Register, Port E
+&44 constant PINE \ Input Pins, Port E
+\ PORTF
+&49 constant PORTF \ Data Register, Port F
+&48 constant DDRF \ Data Direction Register, Port F
+&47 constant PINF \ Input Pins, Port F
+\ CPU
+&95 constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ $08 constant SREG_V \ Two's Complement Overflow Flag
+ $04 constant SREG_N \ Negative Flag
+ $02 constant SREG_Z \ Zero Flag
+ $01 constant SREG_C \ Carry Flag
+&93 constant SP \ Stack Pointer
+&85 constant MCUCR \ MCU Control Register
+ $80 constant MCUCR_JTD \ JTAG Interface Disable
+ $10 constant MCUCR_PUD \ Pull-up disable
+ $02 constant MCUCR_IVSEL \ Interrupt Vector Select
+ $01 constant MCUCR_IVCE \ Interrupt Vector Change Enable
+&84 constant MCUSR \ MCU Status Register
+ $10 constant MCUSR_JTRF \ JTAG Reset Flag
+ $08 constant MCUSR_WDRF \ Watchdog Reset Flag
+ $04 constant MCUSR_BORF \ Brown-out Reset Flag
+ $02 constant MCUSR_EXTRF \ External Reset Flag
+ $01 constant MCUSR_PORF \ Power-on reset flag
+&116 constant XMCRA \ External Memory Control Register A
+ $80 constant XMCRA_SRE \ External SRAM Enable
+ $70 constant XMCRA_SRL \ Wait state page limit
+ $0C constant XMCRA_SRW1 \ Wait state select bit upper page
+ $03 constant XMCRA_SRW0 \ Wait state select bit lower page
+&117 constant XMCRB \ External Memory Control Register B
+ $80 constant XMCRB_XMBK \ External Memory Bus Keeper Enable
+ $07 constant XMCRB_XMM \ External Memory High Mask
+&102 constant OSCCAL \ Oscillator Calibration Value
+&97 constant CLKPR \
+ $80 constant CLKPR_CLKPCE \
+ $0F constant CLKPR_CLKPS \
+&83 constant SMCR \ Sleep Mode Control Register
+ $0E constant SMCR_SM \ Sleep Mode Select bits
+ $01 constant SMCR_SE \ Sleep Enable
+&92 constant EIND \ Extended Indirect Register
+&91 constant RAMPZ \ RAM Page Z Select Register
+&75 constant GPIOR2 \ General Purpose IO Register 2
+ $FF constant GPIOR2_GPIOR \ General Purpose IO Register 2 bis
+&74 constant GPIOR1 \ General Purpose IO Register 1
+ $FF constant GPIOR1_GPIOR \ General Purpose IO Register 1 bis
+&62 constant GPIOR0 \ General Purpose IO Register 0
+ $80 constant GPIOR0_GPIOR07 \ General Purpose IO Register 0 bit 7
+ $40 constant GPIOR0_GPIOR06 \ General Purpose IO Register 0 bit 6
+ $20 constant GPIOR0_GPIOR05 \ General Purpose IO Register 0 bit 5
+ $10 constant GPIOR0_GPIOR04 \ General Purpose IO Register 0 bit 4
+ $08 constant GPIOR0_GPIOR03 \ General Purpose IO Register 0 bit 3
+ $04 constant GPIOR0_GPIOR02 \ General Purpose IO Register 0 bit 2
+ $02 constant GPIOR0_GPIOR01 \ General Purpose IO Register 0 bit 1
+ $01 constant GPIOR0_GPIOR00 \ General Purpose IO Register 0 bit 0
+&101 constant PRR1 \ Power Reduction Register1
+ $80 constant PRR1_PRUSB \ Power Reduction USB
+ $08 constant PRR1_PRTIM3 \ Power Reduction Timer/Counter3
+ $01 constant PRR1_PRUSART1 \ Power Reduction USART1
+&100 constant PRR0 \ Power Reduction Register0
+ $80 constant PRR0_PRTWI \ Power Reduction TWI
+ $40 constant PRR0_PRTIM2 \ Power Reduction Timer/Counter2
+ $20 constant PRR0_PRTIM0 \ Power Reduction Timer/Counter0
+ $08 constant PRR0_PRTIM1 \ Power Reduction Timer/Counter1
+ $04 constant PRR0_PRSPI \ Power Reduction Serial Peripheral Interface
+ $01 constant PRR0_PRADC \ Power Reduction ADC
+\ TWI
+&189 constant TWAMR \ TWI (Slave) Address Mask Register
+ $FE constant TWAMR_TWAM \
+&184 constant TWBR \ TWI Bit Rate register
+&188 constant TWCR \ TWI Control Register
+ $80 constant TWCR_TWINT \ TWI Interrupt Flag
+ $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
+ $20 constant TWCR_TWSTA \ TWI Start Condition Bit
+ $10 constant TWCR_TWSTO \ TWI Stop Condition Bit
+ $08 constant TWCR_TWWC \ TWI Write Collition Flag
+ $04 constant TWCR_TWEN \ TWI Enable Bit
+ $01 constant TWCR_TWIE \ TWI Interrupt Enable
+&185 constant TWSR \ TWI Status Register
+ $F8 constant TWSR_TWS \ TWI Status
+ $03 constant TWSR_TWPS \ TWI Prescaler
+&187 constant TWDR \ TWI Data register
+&186 constant TWAR \ TWI (Slave) Address register
+ $FE constant TWAR_TWA \ TWI (Slave) Address register Bits
+ $01 constant TWAR_TWGCE \ TWI General Call Recognition Enable Bit
+\ SPI
+&76 constant SPCR \ SPI Control Register
+ $80 constant SPCR_SPIE \ SPI Interrupt Enable
+ $40 constant SPCR_SPE \ SPI Enable
+ $20 constant SPCR_DORD \ Data Order
+ $10 constant SPCR_MSTR \ Master/Slave Select
+ $08 constant SPCR_CPOL \ Clock polarity
+ $04 constant SPCR_CPHA \ Clock Phase
+ $03 constant SPCR_SPR \ SPI Clock Rate Selects
+&77 constant SPSR \ SPI Status Register
+ $80 constant SPSR_SPIF \ SPI Interrupt Flag
+ $40 constant SPSR_WCOL \ Write Collision Flag
+ $01 constant SPSR_SPI2X \ Double SPI Speed Bit
+&78 constant SPDR \ SPI Data Register
+\ USART1
+&206 constant UDR1 \ USART I/O Data Register
+&200 constant UCSR1A \ USART Control and Status Register A
+ $80 constant UCSR1A_RXC1 \ USART Receive Complete
+ $40 constant UCSR1A_TXC1 \ USART Transmitt Complete
+ $20 constant UCSR1A_UDRE1 \ USART Data Register Empty
+ $10 constant UCSR1A_FE1 \ Framing Error
+ $08 constant UCSR1A_DOR1 \ Data overRun
+ $04 constant UCSR1A_UPE1 \ Parity Error
+ $02 constant UCSR1A_U2X1 \ Double the USART transmission speed
+ $01 constant UCSR1A_MPCM1 \ Multi-processor Communication Mode
+&201 constant UCSR1B \ USART Control and Status Register B
+ $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable
+ $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable
+ $20 constant UCSR1B_UDRIE1 \ USART Data register Empty Interrupt Enable
+ $10 constant UCSR1B_RXEN1 \ Receiver Enable
+ $08 constant UCSR1B_TXEN1 \ Transmitter Enable
+ $04 constant UCSR1B_UCSZ12 \ Character Size
+ $02 constant UCSR1B_RXB81 \ Receive Data Bit 8
+ $01 constant UCSR1B_TXB81 \ Transmit Data Bit 8
+&202 constant UCSR1C \ USART Control and Status Register C
+ $C0 constant UCSR1C_UMSEL1 \ USART Mode Select
+ $30 constant UCSR1C_UPM1 \ Parity Mode Bits
+ $08 constant UCSR1C_USBS1 \ Stop Bit Select
+ $06 constant UCSR1C_UCSZ1 \ Character Size
+ $01 constant UCSR1C_UCPOL1 \ Clock Polarity
+&204 constant UBRR1 \ USART Baud Rate Register Bytes
+\ USB_DEVICE
+&244 constant UEINT \
+&243 constant UEBCHX \
+&242 constant UEBCLX \
+&241 constant UEDATX \
+&240 constant UEIENX \
+ $80 constant UEIENX_FLERRE \
+ $40 constant UEIENX_NAKINE \
+ $10 constant UEIENX_NAKOUTE \
+ $08 constant UEIENX_RXSTPE \
+ $04 constant UEIENX_RXOUTE \
+ $02 constant UEIENX_STALLEDE \
+ $01 constant UEIENX_TXINE \
+&239 constant UESTA1X \
+ $04 constant UESTA1X_CTRLDIR \
+ $03 constant UESTA1X_CURRBK \
+&238 constant UESTA0X \
+ $80 constant UESTA0X_CFGOK \
+ $40 constant UESTA0X_OVERFI \
+ $20 constant UESTA0X_UNDERFI \
+ $0C constant UESTA0X_DTSEQ \
+ $03 constant UESTA0X_NBUSYBK \
+&237 constant UECFG1X \
+ $70 constant UECFG1X_EPSIZE \
+ $0C constant UECFG1X_EPBK \
+ $02 constant UECFG1X_ALLOC \
+&236 constant UECFG0X \
+ $C0 constant UECFG0X_EPTYPE \
+ $01 constant UECFG0X_EPDIR \
+&235 constant UECONX \
+ $20 constant UECONX_STALLRQ \
+ $10 constant UECONX_STALLRQC \
+ $08 constant UECONX_RSTDT \
+ $01 constant UECONX_EPEN \
+&234 constant UERST \
+ $7F constant UERST_EPRST \
+&233 constant UENUM \
+&232 constant UEINTX \
+ $80 constant UEINTX_FIFOCON \
+ $40 constant UEINTX_NAKINI \
+ $20 constant UEINTX_RWAL \
+ $10 constant UEINTX_NAKOUTI \
+ $08 constant UEINTX_RXSTPI \
+ $04 constant UEINTX_RXOUTI \
+ $02 constant UEINTX_STALLEDI \
+ $01 constant UEINTX_TXINI \
+&230 constant UDMFN \
+ $10 constant UDMFN_FNCERR \
+&228 constant UDFNUM \
+&227 constant UDADDR \
+ $80 constant UDADDR_ADDEN \
+ $7F constant UDADDR_UADD \
+&226 constant UDIEN \
+ $40 constant UDIEN_UPRSME \
+ $20 constant UDIEN_EORSME \
+ $10 constant UDIEN_WAKEUPE \
+ $08 constant UDIEN_EORSTE \
+ $04 constant UDIEN_SOFE \
+ $01 constant UDIEN_SUSPE \
+&225 constant UDINT \
+ $40 constant UDINT_UPRSMI \
+ $20 constant UDINT_EORSMI \
+ $10 constant UDINT_WAKEUPI \
+ $08 constant UDINT_EORSTI \
+ $04 constant UDINT_SOFI \
+ $01 constant UDINT_SUSPI \
+&224 constant UDCON \
+ $04 constant UDCON_LSM \
+ $02 constant UDCON_RMWKUP \
+ $01 constant UDCON_DETACH \
+\ USB_GLOBAL
+&223 constant OTGINT \
+ $20 constant OTGINT_STOI \
+ $10 constant OTGINT_HNPERRI \
+ $08 constant OTGINT_ROLEEXI \
+ $04 constant OTGINT_BCERRI \
+ $02 constant OTGINT_VBERRI \
+ $01 constant OTGINT_SRPI \
+&222 constant OTGIEN \
+ $20 constant OTGIEN_STOE \
+ $10 constant OTGIEN_HNPERRE \
+ $08 constant OTGIEN_ROLEEXE \
+ $04 constant OTGIEN_BCERRE \
+ $02 constant OTGIEN_VBERRE \
+ $01 constant OTGIEN_SRPE \
+&221 constant OTGCON \
+ $20 constant OTGCON_HNPREQ \
+ $10 constant OTGCON_SRPREQ \
+ $08 constant OTGCON_SRPSEL \
+ $04 constant OTGCON_VBUSHWC \
+ $02 constant OTGCON_VBUSREQ \
+ $01 constant OTGCON_VBUSRQC \
+&249 constant OTGTCON \
+ $80 constant OTGTCON_OTGTCON_7 \
+ $60 constant OTGTCON_PAGE \
+ $07 constant OTGTCON_VALUE_2 \
+&218 constant USBINT \
+ $02 constant USBINT_IDTI \
+ $01 constant USBINT_VBUSTI \
+&217 constant USBSTA \
+ $08 constant USBSTA_SPEED \
+ $02 constant USBSTA_ID \
+ $01 constant USBSTA_VBUS \
+&216 constant USBCON \ USB General Control Register
+ $80 constant USBCON_USBE \
+ $40 constant USBCON_HOST \
+ $20 constant USBCON_FRZCLK \
+ $10 constant USBCON_OTGPADE \
+ $02 constant USBCON_IDTE \
+ $01 constant USBCON_VBUSTE \
+&215 constant UHWCON \ USB Hardware Configuration Register
+ $80 constant UHWCON_UIMOD \
+ $40 constant UHWCON_UIDE \
+ $10 constant UHWCON_UVCONE \
+ $01 constant UHWCON_UVREGE \
+\ USB_HOST
+&245 constant UPERRX \
+ $60 constant UPERRX_COUNTER \
+ $10 constant UPERRX_CRC16 \
+ $08 constant UPERRX_TIMEOUT \
+ $04 constant UPERRX_PID \
+ $02 constant UPERRX_DATAPID \
+ $01 constant UPERRX_DATATGL \
+&248 constant UPINT \
+&247 constant UPBCHX \
+&246 constant UPBCLX \
+&175 constant UPDATX \
+&174 constant UPIENX \
+ $80 constant UPIENX_FLERRE \
+ $40 constant UPIENX_NAKEDE \
+ $10 constant UPIENX_PERRE \
+ $08 constant UPIENX_TXSTPE \
+ $04 constant UPIENX_TXOUTE \
+ $02 constant UPIENX_RXSTALLE \
+ $01 constant UPIENX_RXINE \
+&173 constant UPCFG2X \
+&172 constant UPSTAX \
+ $80 constant UPSTAX_CFGOK \
+ $40 constant UPSTAX_OVERFI \
+ $20 constant UPSTAX_UNDERFI \
+ $0C constant UPSTAX_DTSEQ \
+ $03 constant UPSTAX_NBUSYK \
+&171 constant UPCFG1X \
+ $70 constant UPCFG1X_PSIZE \
+ $0C constant UPCFG1X_PBK \
+ $02 constant UPCFG1X_ALLOC \
+&170 constant UPCFG0X \
+ $C0 constant UPCFG0X_PTYPE \
+ $30 constant UPCFG0X_PTOKEN \
+ $0F constant UPCFG0X_PEPNUM \
+&169 constant UPCONX \
+ $40 constant UPCONX_PFREEZE \
+ $20 constant UPCONX_INMODE \
+ $08 constant UPCONX_RSTDT \
+ $01 constant UPCONX_PEN \
+&168 constant UPRST \
+ $7F constant UPRST_PRST \
+&167 constant UPNUM \
+&166 constant UPINTX \
+ $80 constant UPINTX_FIFOCON \
+ $40 constant UPINTX_NAKEDI \
+ $20 constant UPINTX_RWAL \
+ $10 constant UPINTX_PERRI \
+ $08 constant UPINTX_TXSTPI \
+ $04 constant UPINTX_TXOUTI \
+ $02 constant UPINTX_RXSTALLI \
+ $01 constant UPINTX_RXINI \
+&165 constant UPINRQX \
+&164 constant UHFLEN \
+&162 constant UHFNUM \
+&161 constant UHADDR \
+&160 constant UHIEN \
+ $40 constant UHIEN_HWUPE \
+ $20 constant UHIEN_HSOFE \
+ $10 constant UHIEN_RXRSME \
+ $08 constant UHIEN_RSMEDE \
+ $04 constant UHIEN_RSTE \
+ $02 constant UHIEN_DDISCE \
+ $01 constant UHIEN_DCONNE \
+&159 constant UHINT \
+ $40 constant UHINT_UHUPI \
+ $20 constant UHINT_HSOFI \
+ $10 constant UHINT_RXRSMI \
+ $08 constant UHINT_RSMEDI \
+ $04 constant UHINT_RSTI \
+ $02 constant UHINT_DDISCI \
+ $01 constant UHINT_DCONNI \
+&158 constant UHCON \
+ $04 constant UHCON_RESUME \
+ $02 constant UHCON_RESET \
+ $01 constant UHCON_SOFEN \
+\ BOOT_LOAD
+&87 constant SPMCSR \ Store Program Memory Control Register
+ $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
+ $20 constant SPMCSR_SIGRD \ Signature Row Read
+ $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
+ $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
+ $04 constant SPMCSR_PGWRT \ Page Write
+ $02 constant SPMCSR_PGERS \ Page Erase
+ $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
+\ EEPROM
+&65 constant EEAR \ EEPROM Address Register Low Bytes
+&64 constant EEDR \ EEPROM Data Register
+&63 constant EECR \ EEPROM Control Register
+ $30 constant EECR_EEPM \ EEPROM Programming Mode Bits
+ $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
+ $04 constant EECR_EEMPE \ EEPROM Master Write Enable
+ $02 constant EECR_EEPE \ EEPROM Write Enable
+ $01 constant EECR_EERE \ EEPROM Read Enable
+\ TIMER_COUNTER_0
+&72 constant OCR0B \ Timer/Counter0 Output Compare Register
+&71 constant OCR0A \ Timer/Counter0 Output Compare Register
+&70 constant TCNT0 \ Timer/Counter0
+&69 constant TCCR0B \ Timer/Counter Control Register B
+ $80 constant TCCR0B_FOC0A \ Force Output Compare A
+ $40 constant TCCR0B_FOC0B \ Force Output Compare B
+ $08 constant TCCR0B_WGM02 \
+ $07 constant TCCR0B_CS0 \ Clock Select
+&68 constant TCCR0A \ Timer/Counter Control Register A
+ $C0 constant TCCR0A_COM0A \ Compare Output Mode, Phase Correct PWM Mode
+ $30 constant TCCR0A_COM0B \ Compare Output Mode, Fast PWm
+ $03 constant TCCR0A_WGM0 \ Waveform Generation Mode
+&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
+ $04 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare Match B Interrupt Enable
+ $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match A Interrupt Enable
+ $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
+&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
+ $04 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare Flag 0B
+ $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0A
+ $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
+&67 constant GTCCR \ General Timer/Counter Control Register
+ $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
+ $01 constant GTCCR_PSRSYNC \ Prescaler Reset Timer/Counter1 and Timer/Counter0
+\ TIMER_COUNTER_2
+&112 constant TIMSK2 \ Timer/Counter Interrupt Mask register
+ $04 constant TIMSK2_OCIE2B \ Timer/Counter2 Output Compare Match B Interrupt Enable
+ $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match A Interrupt Enable
+ $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
+&55 constant TIFR2 \ Timer/Counter Interrupt Flag Register
+ $04 constant TIFR2_OCF2B \ Output Compare Flag 2B
+ $02 constant TIFR2_OCF2A \ Output Compare Flag 2A
+ $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
+&176 constant TCCR2A \ Timer/Counter2 Control Register A
+ $C0 constant TCCR2A_COM2A \ Compare Output Mode bits
+ $30 constant TCCR2A_COM2B \ Compare Output Mode bits
+ $03 constant TCCR2A_WGM2 \ Waveform Genration Mode
+&177 constant TCCR2B \ Timer/Counter2 Control Register B
+ $80 constant TCCR2B_FOC2A \ Force Output Compare A
+ $40 constant TCCR2B_FOC2B \ Force Output Compare B
+ $08 constant TCCR2B_WGM22 \ Waveform Generation Mode
+ $07 constant TCCR2B_CS2 \ Clock Select bits
+&178 constant TCNT2 \ Timer/Counter2
+&180 constant OCR2B \ Timer/Counter2 Output Compare Register B
+&179 constant OCR2A \ Timer/Counter2 Output Compare Register A
+&182 constant ASSR \ Asynchronous Status Register
+ $40 constant ASSR_EXCLK \ Enable External Clock Input
+ $20 constant ASSR_AS2 \ Asynchronous Timer/Counter2
+ $10 constant ASSR_TCN2UB \ Timer/Counter2 Update Busy
+ $08 constant ASSR_OCR2AUB \ Output Compare Register2 Update Busy
+ $04 constant ASSR_OCR2BUB \ Output Compare Register 2 Update Busy
+ $02 constant ASSR_TCR2AUB \ Timer/Counter Control Register2 Update Busy
+ $01 constant ASSR_TCR2BUB \ Timer/Counter Control Register2 Update Busy
+\ TIMER_COUNTER_3
+&144 constant TCCR3A \ Timer/Counter3 Control Register A
+ $C0 constant TCCR3A_COM3A \ Compare Output Mode 1A, bits
+ $30 constant TCCR3A_COM3B \ Compare Output Mode 3B, bits
+ $0C constant TCCR3A_COM3C \ Compare Output Mode 3C, bits
+ $03 constant TCCR3A_WGM3 \ Waveform Generation Mode
+&145 constant TCCR3B \ Timer/Counter3 Control Register B
+ $80 constant TCCR3B_ICNC3 \ Input Capture 3 Noise Canceler
+ $40 constant TCCR3B_ICES3 \ Input Capture 3 Edge Select
+ $18 constant TCCR3B_WGM3 \ Waveform Generation Mode
+ $07 constant TCCR3B_CS3 \ Prescaler source of Timer/Counter 3
+&146 constant TCCR3C \ Timer/Counter 3 Control Register C
+ $80 constant TCCR3C_FOC3A \ Force Output Compare 3A
+ $40 constant TCCR3C_FOC3B \ Force Output Compare 3B
+ $20 constant TCCR3C_FOC3C \ Force Output Compare 3C
+&148 constant TCNT3 \ Timer/Counter3 Bytes
+&152 constant OCR3A \ Timer/Counter3 Output Compare Register A Bytes
+&154 constant OCR3B \ Timer/Counter3 Output Compare Register B Bytes
+&156 constant OCR3C \ Timer/Counter3 Output Compare Register B Bytes
+&150 constant ICR3 \ Timer/Counter3 Input Capture Register Bytes
+&113 constant TIMSK3 \ Timer/Counter3 Interrupt Mask Register
+ $20 constant TIMSK3_ICIE3 \ Timer/Counter3 Input Capture Interrupt Enable
+ $08 constant TIMSK3_OCIE3C \ Timer/Counter3 Output Compare C Match Interrupt Enable
+ $04 constant TIMSK3_OCIE3B \ Timer/Counter3 Output Compare B Match Interrupt Enable
+ $02 constant TIMSK3_OCIE3A \ Timer/Counter3 Output Compare A Match Interrupt Enable
+ $01 constant TIMSK3_TOIE3 \ Timer/Counter3 Overflow Interrupt Enable
+&56 constant TIFR3 \ Timer/Counter3 Interrupt Flag register
+ $20 constant TIFR3_ICF3 \ Input Capture Flag 3
+ $08 constant TIFR3_OCF3C \ Output Compare Flag 3C
+ $04 constant TIFR3_OCF3B \ Output Compare Flag 3B
+ $02 constant TIFR3_OCF3A \ Output Compare Flag 3A
+ $01 constant TIFR3_TOV3 \ Timer/Counter3 Overflow Flag
+\ TIMER_COUNTER_1
+&128 constant TCCR1A \ Timer/Counter1 Control Register A
+ $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
+ $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
+ $0C constant TCCR1A_COM1C \ Compare Output Mode 1C, bits
+ $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
+&129 constant TCCR1B \ Timer/Counter1 Control Register B
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
+ $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
+&130 constant TCCR1C \ Timer/Counter 1 Control Register C
+ $80 constant TCCR1C_FOC1A \ Force Output Compare 1A
+ $40 constant TCCR1C_FOC1B \ Force Output Compare 1B
+ $20 constant TCCR1C_FOC1C \ Force Output Compare 1C
+&132 constant TCNT1 \ Timer/Counter1 Bytes
+&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
+&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
+&140 constant OCR1C \ Timer/Counter1 Output Compare Register C Bytes
+&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
+&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
+ $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
+ $08 constant TIMSK1_OCIE1C \ Timer/Counter1 Output Compare C Match Interrupt Enable
+ $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
+ $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
+ $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
+&54 constant TIFR1 \ Timer/Counter1 Interrupt Flag register
+ $20 constant TIFR1_ICF1 \ Input Capture Flag 1
+ $08 constant TIFR1_OCF1C \ Output Compare Flag 1C
+ $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
+ $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
+ $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
+\ JTAG
+&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
+\ EXTERNAL_INTERRUPT
+&105 constant EICRA \ External Interrupt Control Register A
+ $C0 constant EICRA_ISC3 \ External Interrupt Sense Control Bit
+ $30 constant EICRA_ISC2 \ External Interrupt Sense Control Bit
+ $0C constant EICRA_ISC1 \ External Interrupt Sense Control Bit
+ $03 constant EICRA_ISC0 \ External Interrupt Sense Control Bit
+&106 constant EICRB \ External Interrupt Control Register B
+ $C0 constant EICRB_ISC7 \ External Interrupt 7-4 Sense Control Bit
+ $30 constant EICRB_ISC6 \ External Interrupt 7-4 Sense Control Bit
+ $0C constant EICRB_ISC5 \ External Interrupt 7-4 Sense Control Bit
+ $03 constant EICRB_ISC4 \ External Interrupt 7-4 Sense Control Bit
+&61 constant EIMSK \ External Interrupt Mask Register
+ $FF constant EIMSK_INT \ External Interrupt Request 7 Enable
+&60 constant EIFR \ External Interrupt Flag Register
+ $FF constant EIFR_INTF \ External Interrupt Flags
+&107 constant PCMSK0 \ Pin Change Mask Register 0
+&59 constant PCIFR \ Pin Change Interrupt Flag Register
+ $01 constant PCIFR_PCIF0 \ Pin Change Interrupt Flag 0
+&104 constant PCICR \ Pin Change Interrupt Control Register
+ $01 constant PCICR_PCIE0 \ Pin Change Interrupt Enable 0
+\ AD_CONVERTER
+&124 constant ADMUX \ The ADC multiplexer Selection Register
+ $C0 constant ADMUX_REFS \ Reference Selection Bits
+ $20 constant ADMUX_ADLAR \ Left Adjust Result
+ $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
+&122 constant ADCSRA \ The ADC Control and Status register
+ $80 constant ADCSRA_ADEN \ ADC Enable
+ $40 constant ADCSRA_ADSC \ ADC Start Conversion
+ $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
+ $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
+ $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
+ $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
+&120 constant ADC \ ADC Data Register Bytes
+&123 constant ADCSRB \ ADC Control and Status Register B
+ $80 constant ADCSRB_ADHSM \ ADC High Speed Mode
+ $07 constant ADCSRB_ADTS \ ADC Auto Trigger Sources
+&126 constant DIDR0 \ Digital Input Disable Register 1
+ $80 constant DIDR0_ADC7D \ ADC7 Digital input Disable
+ $40 constant DIDR0_ADC6D \ ADC6 Digital input Disable
+ $20 constant DIDR0_ADC5D \ ADC5 Digital input Disable
+ $10 constant DIDR0_ADC4D \ ADC4 Digital input Disable
+ $08 constant DIDR0_ADC3D \ ADC3 Digital input Disable
+ $04 constant DIDR0_ADC2D \ ADC2 Digital input Disable
+ $02 constant DIDR0_ADC1D \ ADC1 Digital input Disable
+ $01 constant DIDR0_ADC0D \ ADC0 Digital input Disable
+\ ANALOG_COMPARATOR
+&80 constant ACSR \ Analog Comparator Control And Status Register
+ $80 constant ACSR_ACD \ Analog Comparator Disable
+ $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
+ $20 constant ACSR_ACO \ Analog Compare Output
+ $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
+ $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
+ $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
+ $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
+&127 constant DIDR1 \
+ $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
+ $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
+\ PLL
+&73 constant PLLCSR \ PLL Status and Control register
+ $1C constant PLLCSR_PLLP \ PLL prescaler Bits
+ $02 constant PLLCSR_PLLE \ PLL Enable Bit
+ $01 constant PLLCSR_PLOCK \ PLL Lock Status Bit
+
+\ Interrupts
+&2 constant INT0Addr \ External Interrupt Request 0
+&4 constant INT1Addr \ External Interrupt Request 1
+&6 constant INT2Addr \ External Interrupt Request 2
+&8 constant INT3Addr \ External Interrupt Request 3
+&10 constant INT4Addr \ External Interrupt Request 4
+&12 constant INT5Addr \ External Interrupt Request 5
+&14 constant INT6Addr \ External Interrupt Request 6
+&16 constant INT7Addr \ External Interrupt Request 7
+&18 constant PCINT0Addr \ Pin Change Interrupt Request 0
+&20 constant USB_GENAddr \ USB General Interrupt Request
+&22 constant USB_COMAddr \ USB Endpoint/Pipe Interrupt Communication Reque
+&24 constant WDTAddr \ Watchdog Time-out Interrupt
+&26 constant TIMER2_COMPAAddr \ Timer/Counter2 Compare Match A
+&28 constant TIMER2_COMPBAddr \ Timer/Counter2 Compare Match B
+&30 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
+&32 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+&34 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
+&36 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
+&38 constant TIMER1_COMPCAddr \ Timer/Counter1 Compare Match C
+&40 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+&42 constant TIMER0_COMPAAddr \ Timer/Counter0 Compare Match A
+&44 constant TIMER0_COMPBAddr \ Timer/Counter0 Compare Match B
+&46 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
+&48 constant SPI__STCAddr \ SPI Serial Transfer Complete
+&50 constant USART1__RXAddr \ USART1, Rx Complete
+&52 constant USART1__UDREAddr \ USART1 Data register Empty
+&54 constant USART1__TXAddr \ USART1, Tx Complete
+&56 constant ANALOG_COMPAddr \ Analog Comparator
+&58 constant ADCAddr \ ADC Conversion Complete
+&60 constant EE_READYAddr \ EEPROM Ready
+&62 constant TIMER3_CAPTAddr \ Timer/Counter3 Capture Event
+&64 constant TIMER3_COMPAAddr \ Timer/Counter3 Compare Match A
+&66 constant TIMER3_COMPBAddr \ Timer/Counter3 Compare Match B
+&68 constant TIMER3_COMPCAddr \ Timer/Counter3 Compare Match C
+&70 constant TIMER3_OVFAddr \ Timer/Counter3 Overflow
+&72 constant TWIAddr \ 2-wire Serial Interface
+&74 constant SPM_READYAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/at90usb647/device.asm b/amforth-6.5/avr8/devices/at90usb647/device.asm
new file mode 100644
index 0000000..12cadca
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90usb647/device.asm
@@ -0,0 +1,140 @@
+; Partname: AT90USB647
+; generated automatically, do not edit
+
+.nolist
+ .include "usb647def.inc"
+.list
+
+.equ ramstart = 256
+.equ CELLSIZE = 2
+.macro readflashcell
+ lsl zl
+ rol zh
+ lpm @0, Z+
+ lpm @1, Z+
+.endmacro
+.macro writeflashcell
+ lsl zl
+ rol zh
+.endmacro
+.set WANT_WATCHDOG = 0
+.set WANT_PORTA = 0
+.set WANT_PORTB = 0
+.set WANT_PORTC = 0
+.set WANT_PORTD = 0
+.set WANT_PORTE = 0
+.set WANT_PORTF = 0
+.set WANT_CPU = 0
+.set WANT_TWI = 0
+.set WANT_SPI = 0
+.set WANT_USART1 = 0
+.set WANT_USB_DEVICE = 0
+.set WANT_USB_GLOBAL = 0
+.set WANT_USB_HOST = 0
+.set WANT_BOOT_LOAD = 0
+.set WANT_EEPROM = 0
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_TIMER_COUNTER_2 = 0
+.set WANT_TIMER_COUNTER_3 = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_JTAG = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_AD_CONVERTER = 0
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_PLL = 0
+.equ intvecsize = 2 ; please verify; flash size: 65536 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.org 2
+ rcall isr ; External Interrupt Request 0
+.org 4
+ rcall isr ; External Interrupt Request 1
+.org 6
+ rcall isr ; External Interrupt Request 2
+.org 8
+ rcall isr ; External Interrupt Request 3
+.org 10
+ rcall isr ; External Interrupt Request 4
+.org 12
+ rcall isr ; External Interrupt Request 5
+.org 14
+ rcall isr ; External Interrupt Request 6
+.org 16
+ rcall isr ; External Interrupt Request 7
+.org 18
+ rcall isr ; Pin Change Interrupt Request 0
+.org 20
+ rcall isr ; USB General Interrupt Request
+.org 22
+ rcall isr ; USB Endpoint/Pipe Interrupt Communication Request
+.org 24
+ rcall isr ; Watchdog Time-out Interrupt
+.org 26
+ rcall isr ; Timer/Counter2 Compare Match A
+.org 28
+ rcall isr ; Timer/Counter2 Compare Match B
+.org 30
+ rcall isr ; Timer/Counter2 Overflow
+.org 32
+ rcall isr ; Timer/Counter1 Capture Event
+.org 34
+ rcall isr ; Timer/Counter1 Compare Match A
+.org 36
+ rcall isr ; Timer/Counter1 Compare Match B
+.org 38
+ rcall isr ; Timer/Counter1 Compare Match C
+.org 40
+ rcall isr ; Timer/Counter1 Overflow
+.org 42
+ rcall isr ; Timer/Counter0 Compare Match A
+.org 44
+ rcall isr ; Timer/Counter0 Compare Match B
+.org 46
+ rcall isr ; Timer/Counter0 Overflow
+.org 48
+ rcall isr ; SPI Serial Transfer Complete
+.org 50
+ rcall isr ; USART1, Rx Complete
+.org 52
+ rcall isr ; USART1 Data register Empty
+.org 54
+ rcall isr ; USART1, Tx Complete
+.org 56
+ rcall isr ; Analog Comparator
+.org 58
+ rcall isr ; ADC Conversion Complete
+.org 60
+ rcall isr ; EEPROM Ready
+.org 62
+ rcall isr ; Timer/Counter3 Capture Event
+.org 64
+ rcall isr ; Timer/Counter3 Compare Match A
+.org 66
+ rcall isr ; Timer/Counter3 Compare Match B
+.org 68
+ rcall isr ; Timer/Counter3 Compare Match C
+.org 70
+ rcall isr ; Timer/Counter3 Overflow
+.org 72
+ rcall isr ; 2-wire Serial Interface
+.org 74
+ rcall isr ; Store Program Memory Read
+.equ INTVECTORS = 38
+.nooverlap
+
+; compatability layer (maybe empty)
+
+; controller data area, environment query mcu-info
+mcu_info:
+mcu_ramsize:
+ .dw 4096
+mcu_eepromsize:
+ .dw 2048
+mcu_maxdp:
+ .dw 57344
+mcu_numints:
+ .dw 38
+mcu_name:
+ .dw 10
+ .db "AT90USB647"
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/at90usb647/device.inc b/amforth-6.5/avr8/devices/at90usb647/device.inc
new file mode 100644
index 0000000..b6d73ec
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90usb647/device.inc
@@ -0,0 +1,1914 @@
+; Partname: AT90USB647
+; generated automatically, no not edit
+
+.if WANT_WATCHDOG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCSR:
+ .dw $ff06
+ .db "WDTCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCSR
+XT_WDTCSR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCSR:
+ .dw 96
+
+.endif
+.if WANT_PORTA == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Register
+VE_PORTA:
+ .dw $ff05
+ .db "PORTA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTA
+XT_PORTA:
+ .dw PFA_DOVARIABLE
+PFA_PORTA:
+ .dw 34
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Direction Register
+VE_DDRA:
+ .dw $ff04
+ .db "DDRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRA
+XT_DDRA:
+ .dw PFA_DOVARIABLE
+PFA_DDRA:
+ .dw 33
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Input Pins
+VE_PINA:
+ .dw $ff04
+ .db "PINA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINA
+XT_PINA:
+ .dw PFA_DOVARIABLE
+PFA_PINA:
+ .dw 32
+
+.endif
+.if WANT_PORTB == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw 37
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw 36
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw 35
+
+.endif
+.if WANT_PORTC == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Register
+VE_PORTC:
+ .dw $ff05
+ .db "PORTC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTC
+XT_PORTC:
+ .dw PFA_DOVARIABLE
+PFA_PORTC:
+ .dw 40
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Direction Register
+VE_DDRC:
+ .dw $ff04
+ .db "DDRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRC
+XT_DDRC:
+ .dw PFA_DOVARIABLE
+PFA_DDRC:
+ .dw 39
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Input Pins
+VE_PINC:
+ .dw $ff04
+ .db "PINC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINC
+XT_PINC:
+ .dw PFA_DOVARIABLE
+PFA_PINC:
+ .dw 38
+
+.endif
+.if WANT_PORTD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw 43
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw 42
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw 41
+
+.endif
+.if WANT_PORTE == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port E
+VE_PORTE:
+ .dw $ff05
+ .db "PORTE",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTE
+XT_PORTE:
+ .dw PFA_DOVARIABLE
+PFA_PORTE:
+ .dw 46
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port E
+VE_DDRE:
+ .dw $ff04
+ .db "DDRE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRE
+XT_DDRE:
+ .dw PFA_DOVARIABLE
+PFA_DDRE:
+ .dw 45
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port E
+VE_PINE:
+ .dw $ff04
+ .db "PINE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINE
+XT_PINE:
+ .dw PFA_DOVARIABLE
+PFA_PINE:
+ .dw 44
+
+.endif
+.if WANT_PORTF == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port F
+VE_PORTF:
+ .dw $ff05
+ .db "PORTF",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTF
+XT_PORTF:
+ .dw PFA_DOVARIABLE
+PFA_PORTF:
+ .dw 49
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port F
+VE_DDRF:
+ .dw $ff04
+ .db "DDRF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRF
+XT_DDRF:
+ .dw PFA_DOVARIABLE
+PFA_DDRF:
+ .dw 48
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port F
+VE_PINF:
+ .dw $ff04
+ .db "PINF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINF
+XT_PINF:
+ .dw PFA_DOVARIABLE
+PFA_PINF:
+ .dw 47
+
+.endif
+.if WANT_CPU == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw 95
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer
+VE_SP:
+ .dw $ff02
+ .db "SP"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SP
+XT_SP:
+ .dw PFA_DOVARIABLE
+PFA_SP:
+ .dw 93
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw 85
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Status Register
+VE_MCUSR:
+ .dw $ff05
+ .db "MCUSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUSR
+XT_MCUSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUSR:
+ .dw 84
+; ( -- addr ) System Constant
+; R( -- )
+; External Memory Control Register A
+VE_XMCRA:
+ .dw $ff05
+ .db "XMCRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_XMCRA
+XT_XMCRA:
+ .dw PFA_DOVARIABLE
+PFA_XMCRA:
+ .dw 116
+; ( -- addr ) System Constant
+; R( -- )
+; External Memory Control Register B
+VE_XMCRB:
+ .dw $ff05
+ .db "XMCRB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_XMCRB
+XT_XMCRB:
+ .dw PFA_DOVARIABLE
+PFA_XMCRB:
+ .dw 117
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Calibration Value
+VE_OSCCAL:
+ .dw $ff06
+ .db "OSCCAL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSCCAL
+XT_OSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_OSCCAL:
+ .dw 102
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_CLKPR:
+ .dw $ff05
+ .db "CLKPR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKPR
+XT_CLKPR:
+ .dw PFA_DOVARIABLE
+PFA_CLKPR:
+ .dw 97
+; ( -- addr ) System Constant
+; R( -- )
+; Sleep Mode Control Register
+VE_SMCR:
+ .dw $ff04
+ .db "SMCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SMCR
+XT_SMCR:
+ .dw PFA_DOVARIABLE
+PFA_SMCR:
+ .dw 83
+; ( -- addr ) System Constant
+; R( -- )
+; Extended Indirect Register
+VE_EIND:
+ .dw $ff04
+ .db "EIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIND
+XT_EIND:
+ .dw PFA_DOVARIABLE
+PFA_EIND:
+ .dw 92
+; ( -- addr ) System Constant
+; R( -- )
+; RAM Page Z Select Register
+VE_RAMPZ:
+ .dw $ff05
+ .db "RAMPZ",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_RAMPZ
+XT_RAMPZ:
+ .dw PFA_DOVARIABLE
+PFA_RAMPZ:
+ .dw 91
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 2
+VE_GPIOR2:
+ .dw $ff06
+ .db "GPIOR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR2
+XT_GPIOR2:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR2:
+ .dw 75
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 1
+VE_GPIOR1:
+ .dw $ff06
+ .db "GPIOR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR1
+XT_GPIOR1:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR1:
+ .dw 74
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 0
+VE_GPIOR0:
+ .dw $ff06
+ .db "GPIOR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR0
+XT_GPIOR0:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR0:
+ .dw 62
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register1
+VE_PRR1:
+ .dw $ff04
+ .db "PRR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR1
+XT_PRR1:
+ .dw PFA_DOVARIABLE
+PFA_PRR1:
+ .dw 101
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register0
+VE_PRR0:
+ .dw $ff04
+ .db "PRR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR0
+XT_PRR0:
+ .dw PFA_DOVARIABLE
+PFA_PRR0:
+ .dw 100
+
+.endif
+.if WANT_TWI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; TWI (Slave) Address Mask Register
+VE_TWAMR:
+ .dw $ff05
+ .db "TWAMR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWAMR
+XT_TWAMR:
+ .dw PFA_DOVARIABLE
+PFA_TWAMR:
+ .dw 189
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Bit Rate register
+VE_TWBR:
+ .dw $ff04
+ .db "TWBR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWBR
+XT_TWBR:
+ .dw PFA_DOVARIABLE
+PFA_TWBR:
+ .dw 184
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Control Register
+VE_TWCR:
+ .dw $ff04
+ .db "TWCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWCR
+XT_TWCR:
+ .dw PFA_DOVARIABLE
+PFA_TWCR:
+ .dw 188
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Status Register
+VE_TWSR:
+ .dw $ff04
+ .db "TWSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWSR
+XT_TWSR:
+ .dw PFA_DOVARIABLE
+PFA_TWSR:
+ .dw 185
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Data register
+VE_TWDR:
+ .dw $ff04
+ .db "TWDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWDR
+XT_TWDR:
+ .dw PFA_DOVARIABLE
+PFA_TWDR:
+ .dw 187
+; ( -- addr ) System Constant
+; R( -- )
+; TWI (Slave) Address register
+VE_TWAR:
+ .dw $ff04
+ .db "TWAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWAR
+XT_TWAR:
+ .dw PFA_DOVARIABLE
+PFA_TWAR:
+ .dw 186
+
+.endif
+.if WANT_SPI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR:
+ .dw $ff04
+ .db "SPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR
+XT_SPCR:
+ .dw PFA_DOVARIABLE
+PFA_SPCR:
+ .dw 76
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR:
+ .dw $ff04
+ .db "SPSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR
+XT_SPSR:
+ .dw PFA_DOVARIABLE
+PFA_SPSR:
+ .dw 77
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR:
+ .dw $ff04
+ .db "SPDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR
+XT_SPDR:
+ .dw PFA_DOVARIABLE
+PFA_SPDR:
+ .dw 78
+
+.endif
+.if WANT_USART1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR1:
+ .dw $ff04
+ .db "UDR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR1
+XT_UDR1:
+ .dw PFA_DOVARIABLE
+PFA_UDR1:
+ .dw 206
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR1A:
+ .dw $ff06
+ .db "UCSR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1A
+XT_UCSR1A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1A:
+ .dw 200
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR1B:
+ .dw $ff06
+ .db "UCSR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1B
+XT_UCSR1B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1B:
+ .dw 201
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR1C:
+ .dw $ff06
+ .db "UCSR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1C
+XT_UCSR1C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1C:
+ .dw 202
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Bytes
+VE_UBRR1:
+ .dw $ff05
+ .db "UBRR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR1
+XT_UBRR1:
+ .dw PFA_DOVARIABLE
+PFA_UBRR1:
+ .dw 204
+
+.endif
+.if WANT_USB_DEVICE == 1
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UEINT:
+ .dw $ff05
+ .db "UEINT",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UEINT
+XT_UEINT:
+ .dw PFA_DOVARIABLE
+PFA_UEINT:
+ .dw 244
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UEBCHX:
+ .dw $ff06
+ .db "UEBCHX"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UEBCHX
+XT_UEBCHX:
+ .dw PFA_DOVARIABLE
+PFA_UEBCHX:
+ .dw 243
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UEBCLX:
+ .dw $ff06
+ .db "UEBCLX"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UEBCLX
+XT_UEBCLX:
+ .dw PFA_DOVARIABLE
+PFA_UEBCLX:
+ .dw 242
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UEDATX:
+ .dw $ff06
+ .db "UEDATX"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UEDATX
+XT_UEDATX:
+ .dw PFA_DOVARIABLE
+PFA_UEDATX:
+ .dw 241
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UEIENX:
+ .dw $ff06
+ .db "UEIENX"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UEIENX
+XT_UEIENX:
+ .dw PFA_DOVARIABLE
+PFA_UEIENX:
+ .dw 240
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UESTA1X:
+ .dw $ff07
+ .db "UESTA1X",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UESTA1X
+XT_UESTA1X:
+ .dw PFA_DOVARIABLE
+PFA_UESTA1X:
+ .dw 239
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UESTA0X:
+ .dw $ff07
+ .db "UESTA0X",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UESTA0X
+XT_UESTA0X:
+ .dw PFA_DOVARIABLE
+PFA_UESTA0X:
+ .dw 238
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UECFG1X:
+ .dw $ff07
+ .db "UECFG1X",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UECFG1X
+XT_UECFG1X:
+ .dw PFA_DOVARIABLE
+PFA_UECFG1X:
+ .dw 237
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UECFG0X:
+ .dw $ff07
+ .db "UECFG0X",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UECFG0X
+XT_UECFG0X:
+ .dw PFA_DOVARIABLE
+PFA_UECFG0X:
+ .dw 236
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UECONX:
+ .dw $ff06
+ .db "UECONX"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UECONX
+XT_UECONX:
+ .dw PFA_DOVARIABLE
+PFA_UECONX:
+ .dw 235
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UERST:
+ .dw $ff05
+ .db "UERST",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UERST
+XT_UERST:
+ .dw PFA_DOVARIABLE
+PFA_UERST:
+ .dw 234
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UENUM:
+ .dw $ff05
+ .db "UENUM",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UENUM
+XT_UENUM:
+ .dw PFA_DOVARIABLE
+PFA_UENUM:
+ .dw 233
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UEINTX:
+ .dw $ff06
+ .db "UEINTX"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UEINTX
+XT_UEINTX:
+ .dw PFA_DOVARIABLE
+PFA_UEINTX:
+ .dw 232
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UDMFN:
+ .dw $ff05
+ .db "UDMFN",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDMFN
+XT_UDMFN:
+ .dw PFA_DOVARIABLE
+PFA_UDMFN:
+ .dw 230
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UDFNUM:
+ .dw $ff06
+ .db "UDFNUM"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDFNUM
+XT_UDFNUM:
+ .dw PFA_DOVARIABLE
+PFA_UDFNUM:
+ .dw 228
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UDADDR:
+ .dw $ff06
+ .db "UDADDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDADDR
+XT_UDADDR:
+ .dw PFA_DOVARIABLE
+PFA_UDADDR:
+ .dw 227
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UDIEN:
+ .dw $ff05
+ .db "UDIEN",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDIEN
+XT_UDIEN:
+ .dw PFA_DOVARIABLE
+PFA_UDIEN:
+ .dw 226
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UDINT:
+ .dw $ff05
+ .db "UDINT",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDINT
+XT_UDINT:
+ .dw PFA_DOVARIABLE
+PFA_UDINT:
+ .dw 225
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UDCON:
+ .dw $ff05
+ .db "UDCON",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDCON
+XT_UDCON:
+ .dw PFA_DOVARIABLE
+PFA_UDCON:
+ .dw 224
+
+.endif
+.if WANT_USB_GLOBAL == 1
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_OTGINT:
+ .dw $ff06
+ .db "OTGINT"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OTGINT
+XT_OTGINT:
+ .dw PFA_DOVARIABLE
+PFA_OTGINT:
+ .dw 223
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_OTGIEN:
+ .dw $ff06
+ .db "OTGIEN"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OTGIEN
+XT_OTGIEN:
+ .dw PFA_DOVARIABLE
+PFA_OTGIEN:
+ .dw 222
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_OTGCON:
+ .dw $ff06
+ .db "OTGCON"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OTGCON
+XT_OTGCON:
+ .dw PFA_DOVARIABLE
+PFA_OTGCON:
+ .dw 221
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_OTGTCON:
+ .dw $ff07
+ .db "OTGTCON",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OTGTCON
+XT_OTGTCON:
+ .dw PFA_DOVARIABLE
+PFA_OTGTCON:
+ .dw 249
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_USBINT:
+ .dw $ff06
+ .db "USBINT"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USBINT
+XT_USBINT:
+ .dw PFA_DOVARIABLE
+PFA_USBINT:
+ .dw 218
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_USBSTA:
+ .dw $ff06
+ .db "USBSTA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USBSTA
+XT_USBSTA:
+ .dw PFA_DOVARIABLE
+PFA_USBSTA:
+ .dw 217
+; ( -- addr ) System Constant
+; R( -- )
+; USB General Control Register
+VE_USBCON:
+ .dw $ff06
+ .db "USBCON"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USBCON
+XT_USBCON:
+ .dw PFA_DOVARIABLE
+PFA_USBCON:
+ .dw 216
+; ( -- addr ) System Constant
+; R( -- )
+; USB Hardware Configuration Register
+VE_UHWCON:
+ .dw $ff06
+ .db "UHWCON"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UHWCON
+XT_UHWCON:
+ .dw PFA_DOVARIABLE
+PFA_UHWCON:
+ .dw 215
+
+.endif
+.if WANT_USB_HOST == 1
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UPERRX:
+ .dw $ff06
+ .db "UPERRX"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UPERRX
+XT_UPERRX:
+ .dw PFA_DOVARIABLE
+PFA_UPERRX:
+ .dw 245
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UPINT:
+ .dw $ff05
+ .db "UPINT",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UPINT
+XT_UPINT:
+ .dw PFA_DOVARIABLE
+PFA_UPINT:
+ .dw 248
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UPBCHX:
+ .dw $ff06
+ .db "UPBCHX"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UPBCHX
+XT_UPBCHX:
+ .dw PFA_DOVARIABLE
+PFA_UPBCHX:
+ .dw 247
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UPBCLX:
+ .dw $ff06
+ .db "UPBCLX"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UPBCLX
+XT_UPBCLX:
+ .dw PFA_DOVARIABLE
+PFA_UPBCLX:
+ .dw 246
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UPDATX:
+ .dw $ff06
+ .db "UPDATX"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UPDATX
+XT_UPDATX:
+ .dw PFA_DOVARIABLE
+PFA_UPDATX:
+ .dw 175
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UPIENX:
+ .dw $ff06
+ .db "UPIENX"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UPIENX
+XT_UPIENX:
+ .dw PFA_DOVARIABLE
+PFA_UPIENX:
+ .dw 174
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UPCFG2X:
+ .dw $ff07
+ .db "UPCFG2X",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UPCFG2X
+XT_UPCFG2X:
+ .dw PFA_DOVARIABLE
+PFA_UPCFG2X:
+ .dw 173
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UPSTAX:
+ .dw $ff06
+ .db "UPSTAX"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UPSTAX
+XT_UPSTAX:
+ .dw PFA_DOVARIABLE
+PFA_UPSTAX:
+ .dw 172
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UPCFG1X:
+ .dw $ff07
+ .db "UPCFG1X",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UPCFG1X
+XT_UPCFG1X:
+ .dw PFA_DOVARIABLE
+PFA_UPCFG1X:
+ .dw 171
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UPCFG0X:
+ .dw $ff07
+ .db "UPCFG0X",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UPCFG0X
+XT_UPCFG0X:
+ .dw PFA_DOVARIABLE
+PFA_UPCFG0X:
+ .dw 170
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UPCONX:
+ .dw $ff06
+ .db "UPCONX"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UPCONX
+XT_UPCONX:
+ .dw PFA_DOVARIABLE
+PFA_UPCONX:
+ .dw 169
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UPRST:
+ .dw $ff05
+ .db "UPRST",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UPRST
+XT_UPRST:
+ .dw PFA_DOVARIABLE
+PFA_UPRST:
+ .dw 168
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UPNUM:
+ .dw $ff05
+ .db "UPNUM",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UPNUM
+XT_UPNUM:
+ .dw PFA_DOVARIABLE
+PFA_UPNUM:
+ .dw 167
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UPINTX:
+ .dw $ff06
+ .db "UPINTX"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UPINTX
+XT_UPINTX:
+ .dw PFA_DOVARIABLE
+PFA_UPINTX:
+ .dw 166
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UPINRQX:
+ .dw $ff07
+ .db "UPINRQX",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UPINRQX
+XT_UPINRQX:
+ .dw PFA_DOVARIABLE
+PFA_UPINRQX:
+ .dw 165
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UHFLEN:
+ .dw $ff06
+ .db "UHFLEN"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UHFLEN
+XT_UHFLEN:
+ .dw PFA_DOVARIABLE
+PFA_UHFLEN:
+ .dw 164
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UHFNUM:
+ .dw $ff06
+ .db "UHFNUM"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UHFNUM
+XT_UHFNUM:
+ .dw PFA_DOVARIABLE
+PFA_UHFNUM:
+ .dw 162
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UHADDR:
+ .dw $ff06
+ .db "UHADDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UHADDR
+XT_UHADDR:
+ .dw PFA_DOVARIABLE
+PFA_UHADDR:
+ .dw 161
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UHIEN:
+ .dw $ff05
+ .db "UHIEN",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UHIEN
+XT_UHIEN:
+ .dw PFA_DOVARIABLE
+PFA_UHIEN:
+ .dw 160
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UHINT:
+ .dw $ff05
+ .db "UHINT",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UHINT
+XT_UHINT:
+ .dw PFA_DOVARIABLE
+PFA_UHINT:
+ .dw 159
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UHCON:
+ .dw $ff05
+ .db "UHCON",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UHCON
+XT_UHCON:
+ .dw PFA_DOVARIABLE
+PFA_UHCON:
+ .dw 158
+
+.endif
+.if WANT_BOOT_LOAD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control Register
+VE_SPMCSR:
+ .dw $ff06
+ .db "SPMCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCSR
+XT_SPMCSR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCSR:
+ .dw 87
+
+.endif
+.if WANT_EEPROM == 1
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Address Register Low Bytes
+VE_EEAR:
+ .dw $ff04
+ .db "EEAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEAR
+XT_EEAR:
+ .dw PFA_DOVARIABLE
+PFA_EEAR:
+ .dw 65
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw 64
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw 63
+
+.endif
+.if WANT_TIMER_COUNTER_0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0B:
+ .dw $ff05
+ .db "OCR0B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0B
+XT_OCR0B:
+ .dw PFA_DOVARIABLE
+PFA_OCR0B:
+ .dw 72
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0A:
+ .dw $ff05
+ .db "OCR0A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0A
+XT_OCR0A:
+ .dw PFA_DOVARIABLE
+PFA_OCR0A:
+ .dw 71
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw 70
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register B
+VE_TCCR0B:
+ .dw $ff06
+ .db "TCCR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0B
+XT_TCCR0B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0B:
+ .dw 69
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register A
+VE_TCCR0A:
+ .dw $ff06
+ .db "TCCR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0A
+XT_TCCR0A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0A:
+ .dw 68
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Mask Register
+VE_TIMSK0:
+ .dw $ff06
+ .db "TIMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK0
+XT_TIMSK0:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK0:
+ .dw 110
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Flag register
+VE_TIFR0:
+ .dw $ff05
+ .db "TIFR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR0
+XT_TIFR0:
+ .dw PFA_DOVARIABLE
+PFA_TIFR0:
+ .dw 53
+; ( -- addr ) System Constant
+; R( -- )
+; General Timer/Counter Control Register
+VE_GTCCR:
+ .dw $ff05
+ .db "GTCCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GTCCR
+XT_GTCCR:
+ .dw PFA_DOVARIABLE
+PFA_GTCCR:
+ .dw 67
+
+.endif
+.if WANT_TIMER_COUNTER_2 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Mask register
+VE_TIMSK2:
+ .dw $ff06
+ .db "TIMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK2
+XT_TIMSK2:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK2:
+ .dw 112
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Flag Register
+VE_TIFR2:
+ .dw $ff05
+ .db "TIFR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR2
+XT_TIFR2:
+ .dw PFA_DOVARIABLE
+PFA_TIFR2:
+ .dw 55
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register A
+VE_TCCR2A:
+ .dw $ff06
+ .db "TCCR2A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2A
+XT_TCCR2A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2A:
+ .dw 176
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register B
+VE_TCCR2B:
+ .dw $ff06
+ .db "TCCR2B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2B
+XT_TCCR2B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2B:
+ .dw 177
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2
+VE_TCNT2:
+ .dw $ff05
+ .db "TCNT2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT2
+XT_TCNT2:
+ .dw PFA_DOVARIABLE
+PFA_TCNT2:
+ .dw 178
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register B
+VE_OCR2B:
+ .dw $ff05
+ .db "OCR2B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2B
+XT_OCR2B:
+ .dw PFA_DOVARIABLE
+PFA_OCR2B:
+ .dw 180
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register A
+VE_OCR2A:
+ .dw $ff05
+ .db "OCR2A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2A
+XT_OCR2A:
+ .dw PFA_DOVARIABLE
+PFA_OCR2A:
+ .dw 179
+; ( -- addr ) System Constant
+; R( -- )
+; Asynchronous Status Register
+VE_ASSR:
+ .dw $ff04
+ .db "ASSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ASSR
+XT_ASSR:
+ .dw PFA_DOVARIABLE
+PFA_ASSR:
+ .dw 182
+
+.endif
+.if WANT_TIMER_COUNTER_3 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Control Register A
+VE_TCCR3A:
+ .dw $ff06
+ .db "TCCR3A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR3A
+XT_TCCR3A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR3A:
+ .dw 144
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Control Register B
+VE_TCCR3B:
+ .dw $ff06
+ .db "TCCR3B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR3B
+XT_TCCR3B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR3B:
+ .dw 145
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter 3 Control Register C
+VE_TCCR3C:
+ .dw $ff06
+ .db "TCCR3C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR3C
+XT_TCCR3C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR3C:
+ .dw 146
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Bytes
+VE_TCNT3:
+ .dw $ff05
+ .db "TCNT3",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT3
+XT_TCNT3:
+ .dw PFA_DOVARIABLE
+PFA_TCNT3:
+ .dw 148
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Output Compare Register A Bytes
+VE_OCR3A:
+ .dw $ff05
+ .db "OCR3A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR3A
+XT_OCR3A:
+ .dw PFA_DOVARIABLE
+PFA_OCR3A:
+ .dw 152
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Output Compare Register B Bytes
+VE_OCR3B:
+ .dw $ff05
+ .db "OCR3B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR3B
+XT_OCR3B:
+ .dw PFA_DOVARIABLE
+PFA_OCR3B:
+ .dw 154
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Output Compare Register B Bytes
+VE_OCR3C:
+ .dw $ff05
+ .db "OCR3C",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR3C
+XT_OCR3C:
+ .dw PFA_DOVARIABLE
+PFA_OCR3C:
+ .dw 156
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Input Capture Register Bytes
+VE_ICR3:
+ .dw $ff04
+ .db "ICR3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR3
+XT_ICR3:
+ .dw PFA_DOVARIABLE
+PFA_ICR3:
+ .dw 150
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Interrupt Mask Register
+VE_TIMSK3:
+ .dw $ff06
+ .db "TIMSK3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK3
+XT_TIMSK3:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK3:
+ .dw 113
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Interrupt Flag register
+VE_TIFR3:
+ .dw $ff05
+ .db "TIFR3",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR3
+XT_TIFR3:
+ .dw PFA_DOVARIABLE
+PFA_TIFR3:
+ .dw 56
+
+.endif
+.if WANT_TIMER_COUNTER_1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw 128
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw 129
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter 1 Control Register C
+VE_TCCR1C:
+ .dw $ff06
+ .db "TCCR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1C
+XT_TCCR1C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1C:
+ .dw 130
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Bytes
+VE_TCNT1:
+ .dw $ff05
+ .db "TCNT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1
+XT_TCNT1:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1:
+ .dw 132
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register A Bytes
+VE_OCR1A:
+ .dw $ff05
+ .db "OCR1A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1A
+XT_OCR1A:
+ .dw PFA_DOVARIABLE
+PFA_OCR1A:
+ .dw 136
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register B Bytes
+VE_OCR1B:
+ .dw $ff05
+ .db "OCR1B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1B
+XT_OCR1B:
+ .dw PFA_DOVARIABLE
+PFA_OCR1B:
+ .dw 138
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register C Bytes
+VE_OCR1C:
+ .dw $ff05
+ .db "OCR1C",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1C
+XT_OCR1C:
+ .dw PFA_DOVARIABLE
+PFA_OCR1C:
+ .dw 140
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Bytes
+VE_ICR1:
+ .dw $ff04
+ .db "ICR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1
+XT_ICR1:
+ .dw PFA_DOVARIABLE
+PFA_ICR1:
+ .dw 134
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Mask Register
+VE_TIMSK1:
+ .dw $ff06
+ .db "TIMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK1
+XT_TIMSK1:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK1:
+ .dw 111
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Flag register
+VE_TIFR1:
+ .dw $ff05
+ .db "TIFR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR1
+XT_TIFR1:
+ .dw PFA_DOVARIABLE
+PFA_TIFR1:
+ .dw 54
+
+.endif
+.if WANT_JTAG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; On-Chip Debug Related Register in I/O Memory
+VE_OCDR:
+ .dw $ff04
+ .db "OCDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCDR
+XT_OCDR:
+ .dw PFA_DOVARIABLE
+PFA_OCDR:
+ .dw 81
+
+.endif
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register A
+VE_EICRA:
+ .dw $ff05
+ .db "EICRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRA
+XT_EICRA:
+ .dw PFA_DOVARIABLE
+PFA_EICRA:
+ .dw 105
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register B
+VE_EICRB:
+ .dw $ff05
+ .db "EICRB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRB
+XT_EICRB:
+ .dw PFA_DOVARIABLE
+PFA_EICRB:
+ .dw 106
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Mask Register
+VE_EIMSK:
+ .dw $ff05
+ .db "EIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIMSK
+XT_EIMSK:
+ .dw PFA_DOVARIABLE
+PFA_EIMSK:
+ .dw 61
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Flag Register
+VE_EIFR:
+ .dw $ff04
+ .db "EIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIFR
+XT_EIFR:
+ .dw PFA_DOVARIABLE
+PFA_EIFR:
+ .dw 60
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 0
+VE_PCMSK0:
+ .dw $ff06
+ .db "PCMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK0
+XT_PCMSK0:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK0:
+ .dw 107
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Interrupt Flag Register
+VE_PCIFR:
+ .dw $ff05
+ .db "PCIFR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCIFR
+XT_PCIFR:
+ .dw PFA_DOVARIABLE
+PFA_PCIFR:
+ .dw 59
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Interrupt Control Register
+VE_PCICR:
+ .dw $ff05
+ .db "PCICR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCICR
+XT_PCICR:
+ .dw PFA_DOVARIABLE
+PFA_PCICR:
+ .dw 104
+
+.endif
+.if WANT_AD_CONVERTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC multiplexer Selection Register
+VE_ADMUX:
+ .dw $ff05
+ .db "ADMUX",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADMUX
+XT_ADMUX:
+ .dw PFA_DOVARIABLE
+PFA_ADMUX:
+ .dw 124
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register
+VE_ADCSRA:
+ .dw $ff06
+ .db "ADCSRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRA
+XT_ADCSRA:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRA:
+ .dw 122
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register Bytes
+VE_ADC:
+ .dw $ff03
+ .db "ADC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADC
+XT_ADC:
+ .dw PFA_DOVARIABLE
+PFA_ADC:
+ .dw 120
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Control and Status Register B
+VE_ADCSRB:
+ .dw $ff06
+ .db "ADCSRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRB
+XT_ADCSRB:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRB:
+ .dw 123
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 1
+VE_DIDR0:
+ .dw $ff05
+ .db "DIDR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR0
+XT_DIDR0:
+ .dw PFA_DOVARIABLE
+PFA_DIDR0:
+ .dw 126
+
+.endif
+.if WANT_ANALOG_COMPARATOR == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Control And Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw 80
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_DIDR1:
+ .dw $ff05
+ .db "DIDR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR1
+XT_DIDR1:
+ .dw PFA_DOVARIABLE
+PFA_DIDR1:
+ .dw 127
+
+.endif
+.if WANT_PLL == 1
+; ( -- addr ) System Constant
+; R( -- )
+; PLL Status and Control register
+VE_PLLCSR:
+ .dw $ff06
+ .db "PLLCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PLLCSR
+XT_PLLCSR:
+ .dw PFA_DOVARIABLE
+PFA_PLLCSR:
+ .dw 73
+
+.endif
diff --git a/amforth-6.5/avr8/devices/at90usb647/device.py b/amforth-6.5/avr8/devices/at90usb647/device.py
new file mode 100644
index 0000000..485b265
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90usb647/device.py
@@ -0,0 +1,625 @@
+# Generated Automatically
+
+# Partname AT90USB647
+
+MCUREGS = {
+# Interrupt Vectors
+ 'INT0Addr' : '#2', # External Interrupt Request 0
+ 'INT1Addr' : '#4', # External Interrupt Request 1
+ 'INT2Addr' : '#6', # External Interrupt Request 2
+ 'INT3Addr' : '#8', # External Interrupt Request 3
+ 'INT4Addr' : '#10', # External Interrupt Request 4
+ 'INT5Addr' : '#12', # External Interrupt Request 5
+ 'INT6Addr' : '#14', # External Interrupt Request 6
+ 'INT7Addr' : '#16', # External Interrupt Request 7
+ 'PCINT0Addr' : '#18', # Pin Change Interrupt Request 0
+ 'USB_GENAddr' : '#20', # USB General Interrupt Request
+ 'USB_COMAddr' : '#22', # USB Endpoint/Pipe Interrupt Communication Request
+ 'WDTAddr' : '#24', # Watchdog Time-out Interrupt
+ 'TIMER2_COMPAAddr' : '#26', # Timer/Counter2 Compare Match A
+ 'TIMER2_COMPBAddr' : '#28', # Timer/Counter2 Compare Match B
+ 'TIMER2_OVFAddr' : '#30', # Timer/Counter2 Overflow
+ 'TIMER1_CAPTAddr' : '#32', # Timer/Counter1 Capture Event
+ 'TIMER1_COMPAAddr' : '#34', # Timer/Counter1 Compare Match A
+ 'TIMER1_COMPBAddr' : '#36', # Timer/Counter1 Compare Match B
+ 'TIMER1_COMPCAddr' : '#38', # Timer/Counter1 Compare Match C
+ 'TIMER1_OVFAddr' : '#40', # Timer/Counter1 Overflow
+ 'TIMER0_COMPAAddr' : '#42', # Timer/Counter0 Compare Match A
+ 'TIMER0_COMPBAddr' : '#44', # Timer/Counter0 Compare Match B
+ 'TIMER0_OVFAddr' : '#46', # Timer/Counter0 Overflow
+ 'SPI_STCAddr' : '#48', # SPI Serial Transfer Complete
+ 'USART1_RXAddr' : '#50', # USART1, Rx Complete
+ 'USART1_UDREAddr' : '#52', # USART1 Data register Empty
+ 'USART1_TXAddr' : '#54', # USART1, Tx Complete
+ 'ANALOG_COMPAddr' : '#56', # Analog Comparator
+ 'ADCAddr' : '#58', # ADC Conversion Complete
+ 'EE_READYAddr' : '#60', # EEPROM Ready
+ 'TIMER3_CAPTAddr' : '#62', # Timer/Counter3 Capture Event
+ 'TIMER3_COMPAAddr' : '#64', # Timer/Counter3 Compare Match A
+ 'TIMER3_COMPBAddr' : '#66', # Timer/Counter3 Compare Match B
+ 'TIMER3_COMPCAddr' : '#68', # Timer/Counter3 Compare Match C
+ 'TIMER3_OVFAddr' : '#70', # Timer/Counter3 Overflow
+ 'TWIAddr' : '#72', # 2-wire Serial Interface
+ 'SPM_READYAddr' : '#74', # Store Program Memory Read
+
+# Module WATCHDOG
+ 'WDTCSR' : '$60', # Watchdog Timer Control Registe
+ 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
+ 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
+ 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
+ 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
+ 'WDTCSR_WDE': '$8', # Watch Dog Enable
+
+# Module PORTA
+ 'PORTA' : '$22', # Port A Data Register
+ 'DDRA' : '$21', # Port A Data Direction Register
+ 'PINA' : '$20', # Port A Input Pins
+
+# Module PORTB
+ 'PORTB' : '$25', # Port B Data Register
+ 'DDRB' : '$24', # Port B Data Direction Register
+ 'PINB' : '$23', # Port B Input Pins
+
+# Module PORTC
+ 'PORTC' : '$28', # Port C Data Register
+ 'DDRC' : '$27', # Port C Data Direction Register
+ 'PINC' : '$26', # Port C Input Pins
+
+# Module PORTD
+ 'PORTD' : '$2b', # Port D Data Register
+ 'DDRD' : '$2a', # Port D Data Direction Register
+ 'PIND' : '$29', # Port D Input Pins
+
+# Module PORTE
+ 'PORTE' : '$2e', # Data Register, Port E
+ 'DDRE' : '$2d', # Data Direction Register, Port
+ 'PINE' : '$2c', # Input Pins, Port E
+
+# Module PORTF
+ 'PORTF' : '$31', # Data Register, Port F
+ 'DDRF' : '$30', # Data Direction Register, Port
+ 'PINF' : '$2f', # Input Pins, Port F
+
+# Module CPU
+ 'SREG' : '$5f', # Status Register
+ 'SREG_I': '$80', # Global Interrupt Enable
+ 'SREG_T': '$40', # Bit Copy Storage
+ 'SREG_H': '$20', # Half Carry Flag
+ 'SREG_S': '$10', # Sign Bit
+ 'SREG_V': '$8', # Two's Complement Overflow Flag
+ 'SREG_N': '$4', # Negative Flag
+ 'SREG_Z': '$2', # Zero Flag
+ 'SREG_C': '$1', # Carry Flag
+ 'SP' : '$5d', # Stack Pointer
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_JTD': '$80', # JTAG Interface Disable
+ 'MCUCR_PUD': '$10', # Pull-up disable
+ 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
+ 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+ 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
+ 'MCUSR_BORF': '$4', # Brown-out Reset Flag
+ 'MCUSR_EXTRF': '$2', # External Reset Flag
+ 'MCUSR_PORF': '$1', # Power-on reset flag
+ 'XMCRA' : '$74', # External Memory Control Regist
+ 'XMCRA_SRE': '$80', # External SRAM Enable
+ 'XMCRA_SRL': '$70', # Wait state page limit
+ 'XMCRA_SRW1': '$c', # Wait state select bit upper pa
+ 'XMCRA_SRW0': '$3', # Wait state select bit lower pa
+ 'XMCRB' : '$75', # External Memory Control Regist
+ 'XMCRB_XMBK': '$80', # External Memory Bus Keeper Ena
+ 'XMCRB_XMM': '$7', # External Memory High Mask
+ 'OSCCAL' : '$66', # Oscillator Calibration Value
+ 'CLKPR' : '$61', #
+ 'CLKPR_CLKPCE': '$80', #
+ 'CLKPR_CLKPS': '$f', #
+ 'SMCR' : '$53', # Sleep Mode Control Register
+ 'SMCR_SM': '$e', # Sleep Mode Select bits
+ 'SMCR_SE': '$1', # Sleep Enable
+ 'EIND' : '$5c', # Extended Indirect Register
+ 'RAMPZ' : '$5b', # RAM Page Z Select Register
+ 'GPIOR2' : '$4b', # General Purpose IO Register 2
+ 'GPIOR2_GPIOR': '$ff', # General Purpose IO Register 2
+ 'GPIOR1' : '$4a', # General Purpose IO Register 1
+ 'GPIOR1_GPIOR': '$ff', # General Purpose IO Register 1
+ 'GPIOR0' : '$3e', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR07': '$80', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR06': '$40', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR05': '$20', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR04': '$10', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR03': '$8', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR02': '$4', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR01': '$2', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR00': '$1', # General Purpose IO Register 0
+ 'PRR1' : '$65', # Power Reduction Register1
+ 'PRR1_PRUSB': '$80', # Power Reduction USB
+ 'PRR1_PRTIM3': '$8', # Power Reduction Timer/Counter3
+ 'PRR1_PRUSART1': '$1', # Power Reduction USART1
+ 'PRR0' : '$64', # Power Reduction Register0
+ 'PRR0_PRTWI': '$80', # Power Reduction TWI
+ 'PRR0_PRTIM2': '$40', # Power Reduction Timer/Counter2
+ 'PRR0_PRTIM0': '$20', # Power Reduction Timer/Counter0
+ 'PRR0_PRTIM1': '$8', # Power Reduction Timer/Counter1
+ 'PRR0_PRSPI': '$4', # Power Reduction Serial Periphe
+ 'PRR0_PRADC': '$1', # Power Reduction ADC
+
+# Module TWI
+ 'TWAMR' : '$bd', # TWI (Slave) Address Mask Regis
+ 'TWAMR_TWAM': '$fe', #
+ 'TWBR' : '$b8', # TWI Bit Rate register
+ 'TWCR' : '$bc', # TWI Control Register
+ 'TWCR_TWINT': '$80', # TWI Interrupt Flag
+ 'TWCR_TWEA': '$40', # TWI Enable Acknowledge Bit
+ 'TWCR_TWSTA': '$20', # TWI Start Condition Bit
+ 'TWCR_TWSTO': '$10', # TWI Stop Condition Bit
+ 'TWCR_TWWC': '$8', # TWI Write Collition Flag
+ 'TWCR_TWEN': '$4', # TWI Enable Bit
+ 'TWCR_TWIE': '$1', # TWI Interrupt Enable
+ 'TWSR' : '$b9', # TWI Status Register
+ 'TWSR_TWS': '$f8', # TWI Status
+ 'TWSR_TWPS': '$3', # TWI Prescaler
+ 'TWDR' : '$bb', # TWI Data register
+ 'TWAR' : '$ba', # TWI (Slave) Address register
+ 'TWAR_TWA': '$fe', # TWI (Slave) Address register B
+ 'TWAR_TWGCE': '$1', # TWI General Call Recognition E
+
+# Module SPI
+ 'SPCR' : '$4c', # SPI Control Register
+ 'SPCR_SPIE': '$80', # SPI Interrupt Enable
+ 'SPCR_SPE': '$40', # SPI Enable
+ 'SPCR_DORD': '$20', # Data Order
+ 'SPCR_MSTR': '$10', # Master/Slave Select
+ 'SPCR_CPOL': '$8', # Clock polarity
+ 'SPCR_CPHA': '$4', # Clock Phase
+ 'SPCR_SPR': '$3', # SPI Clock Rate Selects
+ 'SPSR' : '$4d', # SPI Status Register
+ 'SPSR_SPIF': '$80', # SPI Interrupt Flag
+ 'SPSR_WCOL': '$40', # Write Collision Flag
+ 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
+ 'SPDR' : '$4e', # SPI Data Register
+
+# Module USART1
+ 'UDR1' : '$ce', # USART I/O Data Register
+ 'UCSR1A' : '$c8', # USART Control and Status Regis
+ 'UCSR1A_RXC1': '$80', # USART Receive Complete
+ 'UCSR1A_TXC1': '$40', # USART Transmitt Complete
+ 'UCSR1A_UDRE1': '$20', # USART Data Register Empty
+ 'UCSR1A_FE1': '$10', # Framing Error
+ 'UCSR1A_DOR1': '$8', # Data overRun
+ 'UCSR1A_UPE1': '$4', # Parity Error
+ 'UCSR1A_U2X1': '$2', # Double the USART transmission
+ 'UCSR1A_MPCM1': '$1', # Multi-processor Communication
+ 'UCSR1B' : '$c9', # USART Control and Status Regis
+ 'UCSR1B_RXCIE1': '$80', # RX Complete Interrupt Enable
+ 'UCSR1B_TXCIE1': '$40', # TX Complete Interrupt Enable
+ 'UCSR1B_UDRIE1': '$20', # USART Data register Empty Inte
+ 'UCSR1B_RXEN1': '$10', # Receiver Enable
+ 'UCSR1B_TXEN1': '$8', # Transmitter Enable
+ 'UCSR1B_UCSZ12': '$4', # Character Size
+ 'UCSR1B_RXB81': '$2', # Receive Data Bit 8
+ 'UCSR1B_TXB81': '$1', # Transmit Data Bit 8
+ 'UCSR1C' : '$ca', # USART Control and Status Regis
+ 'UCSR1C_UMSEL1': '$c0', # USART Mode Select
+ 'UCSR1C_UPM1': '$30', # Parity Mode Bits
+ 'UCSR1C_USBS1': '$8', # Stop Bit Select
+ 'UCSR1C_UCSZ1': '$6', # Character Size
+ 'UCSR1C_UCPOL1': '$1', # Clock Polarity
+ 'UBRR1' : '$cc', # USART Baud Rate Register Byte
+
+# Module USB_DEVICE
+ 'UEINT' : '$f4', #
+ 'UEBCHX' : '$f3', #
+ 'UEBCLX' : '$f2', #
+ 'UEDATX' : '$f1', #
+ 'UEIENX' : '$f0', #
+ 'UEIENX_FLERRE': '$80', #
+ 'UEIENX_NAKINE': '$40', #
+ 'UEIENX_NAKOUTE': '$10', #
+ 'UEIENX_RXSTPE': '$8', #
+ 'UEIENX_RXOUTE': '$4', #
+ 'UEIENX_STALLEDE': '$2', #
+ 'UEIENX_TXINE': '$1', #
+ 'UESTA1X' : '$ef', #
+ 'UESTA1X_CTRLDIR': '$4', #
+ 'UESTA1X_CURRBK': '$3', #
+ 'UESTA0X' : '$ee', #
+ 'UESTA0X_CFGOK': '$80', #
+ 'UESTA0X_OVERFI': '$40', #
+ 'UESTA0X_UNDERFI': '$20', #
+ 'UESTA0X_DTSEQ': '$c', #
+ 'UESTA0X_NBUSYBK': '$3', #
+ 'UECFG1X' : '$ed', #
+ 'UECFG1X_EPSIZE': '$70', #
+ 'UECFG1X_EPBK': '$c', #
+ 'UECFG1X_ALLOC': '$2', #
+ 'UECFG0X' : '$ec', #
+ 'UECFG0X_EPTYPE': '$c0', #
+ 'UECFG0X_EPDIR': '$1', #
+ 'UECONX' : '$eb', #
+ 'UECONX_STALLRQ': '$20', #
+ 'UECONX_STALLRQC': '$10', #
+ 'UECONX_RSTDT': '$8', #
+ 'UECONX_EPEN': '$1', #
+ 'UERST' : '$ea', #
+ 'UERST_EPRST': '$7f', #
+ 'UENUM' : '$e9', #
+ 'UEINTX' : '$e8', #
+ 'UEINTX_FIFOCON': '$80', #
+ 'UEINTX_NAKINI': '$40', #
+ 'UEINTX_RWAL': '$20', #
+ 'UEINTX_NAKOUTI': '$10', #
+ 'UEINTX_RXSTPI': '$8', #
+ 'UEINTX_RXOUTI': '$4', #
+ 'UEINTX_STALLEDI': '$2', #
+ 'UEINTX_TXINI': '$1', #
+ 'UDMFN' : '$e6', #
+ 'UDMFN_FNCERR': '$10', #
+ 'UDFNUM' : '$e4', #
+ 'UDADDR' : '$e3', #
+ 'UDADDR_ADDEN': '$80', #
+ 'UDADDR_UADD': '$7f', #
+ 'UDIEN' : '$e2', #
+ 'UDIEN_UPRSME': '$40', #
+ 'UDIEN_EORSME': '$20', #
+ 'UDIEN_WAKEUPE': '$10', #
+ 'UDIEN_EORSTE': '$8', #
+ 'UDIEN_SOFE': '$4', #
+ 'UDIEN_SUSPE': '$1', #
+ 'UDINT' : '$e1', #
+ 'UDINT_UPRSMI': '$40', #
+ 'UDINT_EORSMI': '$20', #
+ 'UDINT_WAKEUPI': '$10', #
+ 'UDINT_EORSTI': '$8', #
+ 'UDINT_SOFI': '$4', #
+ 'UDINT_SUSPI': '$1', #
+ 'UDCON' : '$e0', #
+ 'UDCON_LSM': '$4', #
+ 'UDCON_RMWKUP': '$2', #
+ 'UDCON_DETACH': '$1', #
+
+# Module USB_GLOBAL
+ 'OTGINT' : '$df', #
+ 'OTGINT_STOI': '$20', #
+ 'OTGINT_HNPERRI': '$10', #
+ 'OTGINT_ROLEEXI': '$8', #
+ 'OTGINT_BCERRI': '$4', #
+ 'OTGINT_VBERRI': '$2', #
+ 'OTGINT_SRPI': '$1', #
+ 'OTGIEN' : '$de', #
+ 'OTGIEN_STOE': '$20', #
+ 'OTGIEN_HNPERRE': '$10', #
+ 'OTGIEN_ROLEEXE': '$8', #
+ 'OTGIEN_BCERRE': '$4', #
+ 'OTGIEN_VBERRE': '$2', #
+ 'OTGIEN_SRPE': '$1', #
+ 'OTGCON' : '$dd', #
+ 'OTGCON_HNPREQ': '$20', #
+ 'OTGCON_SRPREQ': '$10', #
+ 'OTGCON_SRPSEL': '$8', #
+ 'OTGCON_VBUSHWC': '$4', #
+ 'OTGCON_VBUSREQ': '$2', #
+ 'OTGCON_VBUSRQC': '$1', #
+ 'OTGTCON' : '$f9', #
+ 'OTGTCON_OTGTCON_7': '$80', #
+ 'OTGTCON_PAGE': '$60', #
+ 'OTGTCON_VALUE_2': '$7', #
+ 'USBINT' : '$da', #
+ 'USBINT_IDTI': '$2', #
+ 'USBINT_VBUSTI': '$1', #
+ 'USBSTA' : '$d9', #
+ 'USBSTA_SPEED': '$8', #
+ 'USBSTA_ID': '$2', #
+ 'USBSTA_VBUS': '$1', #
+ 'USBCON' : '$d8', # USB General Control Register
+ 'USBCON_USBE': '$80', #
+ 'USBCON_HOST': '$40', #
+ 'USBCON_FRZCLK': '$20', #
+ 'USBCON_OTGPADE': '$10', #
+ 'USBCON_IDTE': '$2', #
+ 'USBCON_VBUSTE': '$1', #
+ 'UHWCON' : '$d7', # USB Hardware Configuration Reg
+ 'UHWCON_UIMOD': '$80', #
+ 'UHWCON_UIDE': '$40', #
+ 'UHWCON_UVCONE': '$10', #
+ 'UHWCON_UVREGE': '$1', #
+
+# Module USB_HOST
+ 'UPERRX' : '$f5', #
+ 'UPERRX_COUNTER': '$60', #
+ 'UPERRX_CRC16': '$10', #
+ 'UPERRX_TIMEOUT': '$8', #
+ 'UPERRX_PID': '$4', #
+ 'UPERRX_DATAPID': '$2', #
+ 'UPERRX_DATATGL': '$1', #
+ 'UPINT' : '$f8', #
+ 'UPBCHX' : '$f7', #
+ 'UPBCLX' : '$f6', #
+ 'UPDATX' : '$af', #
+ 'UPIENX' : '$ae', #
+ 'UPIENX_FLERRE': '$80', #
+ 'UPIENX_NAKEDE': '$40', #
+ 'UPIENX_PERRE': '$10', #
+ 'UPIENX_TXSTPE': '$8', #
+ 'UPIENX_TXOUTE': '$4', #
+ 'UPIENX_RXSTALLE': '$2', #
+ 'UPIENX_RXINE': '$1', #
+ 'UPCFG2X' : '$ad', #
+ 'UPSTAX' : '$ac', #
+ 'UPSTAX_CFGOK': '$80', #
+ 'UPSTAX_OVERFI': '$40', #
+ 'UPSTAX_UNDERFI': '$20', #
+ 'UPSTAX_DTSEQ': '$c', #
+ 'UPSTAX_NBUSYK': '$3', #
+ 'UPCFG1X' : '$ab', #
+ 'UPCFG1X_PSIZE': '$70', #
+ 'UPCFG1X_PBK': '$c', #
+ 'UPCFG1X_ALLOC': '$2', #
+ 'UPCFG0X' : '$aa', #
+ 'UPCFG0X_PTYPE': '$c0', #
+ 'UPCFG0X_PTOKEN': '$30', #
+ 'UPCFG0X_PEPNUM': '$f', #
+ 'UPCONX' : '$a9', #
+ 'UPCONX_PFREEZE': '$40', #
+ 'UPCONX_INMODE': '$20', #
+ 'UPCONX_RSTDT': '$8', #
+ 'UPCONX_PEN': '$1', #
+ 'UPRST' : '$a8', #
+ 'UPRST_PRST': '$7f', #
+ 'UPNUM' : '$a7', #
+ 'UPINTX' : '$a6', #
+ 'UPINTX_FIFOCON': '$80', #
+ 'UPINTX_NAKEDI': '$40', #
+ 'UPINTX_RWAL': '$20', #
+ 'UPINTX_PERRI': '$10', #
+ 'UPINTX_TXSTPI': '$8', #
+ 'UPINTX_TXOUTI': '$4', #
+ 'UPINTX_RXSTALLI': '$2', #
+ 'UPINTX_RXINI': '$1', #
+ 'UPINRQX' : '$a5', #
+ 'UHFLEN' : '$a4', #
+ 'UHFNUM' : '$a2', #
+ 'UHADDR' : '$a1', #
+ 'UHIEN' : '$a0', #
+ 'UHIEN_HWUPE': '$40', #
+ 'UHIEN_HSOFE': '$20', #
+ 'UHIEN_RXRSME': '$10', #
+ 'UHIEN_RSMEDE': '$8', #
+ 'UHIEN_RSTE': '$4', #
+ 'UHIEN_DDISCE': '$2', #
+ 'UHIEN_DCONNE': '$1', #
+ 'UHINT' : '$9f', #
+ 'UHINT_UHUPI': '$40', #
+ 'UHINT_HSOFI': '$20', #
+ 'UHINT_RXRSMI': '$10', #
+ 'UHINT_RSMEDI': '$8', #
+ 'UHINT_RSTI': '$4', #
+ 'UHINT_DDISCI': '$2', #
+ 'UHINT_DCONNI': '$1', #
+ 'UHCON' : '$9e', #
+ 'UHCON_RESUME': '$4', #
+ 'UHCON_RESET': '$2', #
+ 'UHCON_SOFEN': '$1', #
+
+# Module BOOT_LOAD
+ 'SPMCSR' : '$57', # Store Program Memory Control R
+ 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
+ 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
+ 'SPMCSR_SIGRD': '$20', # Signature Row Read
+ 'SPMCSR_RWWSRE': '$10', # Read While Write section read
+ 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
+ 'SPMCSR_PGWRT': '$4', # Page Write
+ 'SPMCSR_PGERS': '$2', # Page Erase
+ 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
+
+# Module EEPROM
+ 'EEAR' : '$41', # EEPROM Address Register Low By
+ 'EEDR' : '$40', # EEPROM Data Register
+ 'EECR' : '$3f', # EEPROM Control Register
+ 'EECR_EEPM': '$30', # EEPROM Programming Mode Bits
+ 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
+ 'EECR_EEMPE': '$4', # EEPROM Master Write Enable
+ 'EECR_EEPE': '$2', # EEPROM Write Enable
+ 'EECR_EERE': '$1', # EEPROM Read Enable
+
+# Module TIMER_COUNTER_0
+ 'OCR0B' : '$48', # Timer/Counter0 Output Compare
+ 'OCR0A' : '$47', # Timer/Counter0 Output Compare
+ 'TCNT0' : '$46', # Timer/Counter0
+ 'TCCR0B' : '$45', # Timer/Counter Control Register
+ 'TCCR0B_FOC0A': '$80', # Force Output Compare A
+ 'TCCR0B_FOC0B': '$40', # Force Output Compare B
+ 'TCCR0B_WGM02': '$8', #
+ 'TCCR0B_CS0': '$7', # Clock Select
+ 'TCCR0A' : '$44', # Timer/Counter Control Registe
+ 'TCCR0A_COM0A': '$c0', # Compare Output Mode, Phase Cor
+ 'TCCR0A_COM0B': '$30', # Compare Output Mode, Fast PWm
+ 'TCCR0A_WGM0': '$3', # Waveform Generation Mode
+ 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
+ 'TIMSK0_OCIE0B': '$4', # Timer/Counter0 Output Compare
+ 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
+ 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
+ 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
+ 'TIFR0_OCF0B': '$4', # Timer/Counter0 Output Compare
+ 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
+ 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSRSYNC': '$1', # Prescaler Reset Timer/Counter1
+
+# Module TIMER_COUNTER_2
+ 'TIMSK2' : '$70', # Timer/Counter Interrupt Mask r
+ 'TIMSK2_OCIE2B': '$4', # Timer/Counter2 Output Compare
+ 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
+ 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
+ 'TIFR2' : '$37', # Timer/Counter Interrupt Flag R
+ 'TIFR2_OCF2B': '$4', # Output Compare Flag 2B
+ 'TIFR2_OCF2A': '$2', # Output Compare Flag 2A
+ 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
+ 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
+ 'TCCR2A_COM2A': '$c0', # Compare Output Mode bits
+ 'TCCR2A_COM2B': '$30', # Compare Output Mode bits
+ 'TCCR2A_WGM2': '$3', # Waveform Genration Mode
+ 'TCCR2B' : '$b1', # Timer/Counter2 Control Registe
+ 'TCCR2B_FOC2A': '$80', # Force Output Compare A
+ 'TCCR2B_FOC2B': '$40', # Force Output Compare B
+ 'TCCR2B_WGM22': '$8', # Waveform Generation Mode
+ 'TCCR2B_CS2': '$7', # Clock Select bits
+ 'TCNT2' : '$b2', # Timer/Counter2
+ 'OCR2B' : '$b4', # Timer/Counter2 Output Compare
+ 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
+ 'ASSR' : '$b6', # Asynchronous Status Register
+ 'ASSR_EXCLK': '$40', # Enable External Clock Input
+ 'ASSR_AS2': '$20', # Asynchronous Timer/Counter2
+ 'ASSR_TCN2UB': '$10', # Timer/Counter2 Update Busy
+ 'ASSR_OCR2AUB': '$8', # Output Compare Register2 Updat
+ 'ASSR_OCR2BUB': '$4', # Output Compare Register 2 Upda
+ 'ASSR_TCR2AUB': '$2', # Timer/Counter Control Register
+ 'ASSR_TCR2BUB': '$1', # Timer/Counter Control Register
+ 'GTCCR' : '$43', # General Timer Counter Control
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSRASY': '$2', # Prescaler Reset Timer/Counter2
+
+# Module TIMER_COUNTER_3
+ 'TCCR3A' : '$90', # Timer/Counter3 Control Registe
+ 'TCCR3A_COM3A': '$c0', # Compare Output Mode 1A, bits
+ 'TCCR3A_COM3B': '$30', # Compare Output Mode 3B, bits
+ 'TCCR3A_COM3C': '$c', # Compare Output Mode 3C, bits
+ 'TCCR3A_WGM3': '$3', # Waveform Generation Mode
+ 'TCCR3B' : '$91', # Timer/Counter3 Control Registe
+ 'TCCR3B_ICNC3': '$80', # Input Capture 3 Noise Canceler
+ 'TCCR3B_ICES3': '$40', # Input Capture 3 Edge Select
+ 'TCCR3B_WGM3': '$18', # Waveform Generation Mode
+ 'TCCR3B_CS3': '$7', # Prescaler source of Timer/Coun
+ 'TCCR3C' : '$92', # Timer/Counter 3 Control Regist
+ 'TCCR3C_FOC3A': '$80', # Force Output Compare 3A
+ 'TCCR3C_FOC3B': '$40', # Force Output Compare 3B
+ 'TCCR3C_FOC3C': '$20', # Force Output Compare 3C
+ 'TCNT3' : '$94', # Timer/Counter3 Bytes
+ 'OCR3A' : '$98', # Timer/Counter3 Output Compare
+ 'OCR3B' : '$9a', # Timer/Counter3 Output Compare
+ 'OCR3C' : '$9c', # Timer/Counter3 Output Compare
+ 'ICR3' : '$96', # Timer/Counter3 Input Capture R
+ 'TIMSK3' : '$71', # Timer/Counter3 Interrupt Mask
+ 'TIMSK3_ICIE3': '$20', # Timer/Counter3 Input Capture I
+ 'TIMSK3_OCIE3C': '$8', # Timer/Counter3 Output Compare
+ 'TIMSK3_OCIE3B': '$4', # Timer/Counter3 Output Compare
+ 'TIMSK3_OCIE3A': '$2', # Timer/Counter3 Output Compare
+ 'TIMSK3_TOIE3': '$1', # Timer/Counter3 Overflow Interr
+ 'TIFR3' : '$38', # Timer/Counter3 Interrupt Flag
+ 'TIFR3_ICF3': '$20', # Input Capture Flag 3
+ 'TIFR3_OCF3C': '$8', # Output Compare Flag 3C
+ 'TIFR3_OCF3B': '$4', # Output Compare Flag 3B
+ 'TIFR3_OCF3A': '$2', # Output Compare Flag 3A
+ 'TIFR3_TOV3': '$1', # Timer/Counter3 Overflow Flag
+
+# Module TIMER_COUNTER_1
+ 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
+ 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
+ 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
+ 'TCCR1A_COM1C': '$c', # Compare Output Mode 1C, bits
+ 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
+ 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
+ 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
+ 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
+ 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
+ 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
+ 'TCCR1C' : '$82', # Timer/Counter 1 Control Regist
+ 'TCCR1C_FOC1A': '$80', # Force Output Compare 1A
+ 'TCCR1C_FOC1B': '$40', # Force Output Compare 1B
+ 'TCCR1C_FOC1C': '$20', # Force Output Compare 1C
+ 'TCNT1' : '$84', # Timer/Counter1 Bytes
+ 'OCR1A' : '$88', # Timer/Counter1 Output Compare
+ 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
+ 'OCR1C' : '$8c', # Timer/Counter1 Output Compare
+ 'ICR1' : '$86', # Timer/Counter1 Input Capture R
+ 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
+ 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
+ 'TIMSK1_OCIE1C': '$8', # Timer/Counter1 Output Compare
+ 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
+ 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
+ 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
+ 'TIFR1' : '$36', # Timer/Counter1 Interrupt Flag
+ 'TIFR1_ICF1': '$20', # Input Capture Flag 1
+ 'TIFR1_OCF1C': '$8', # Output Compare Flag 1C
+ 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
+ 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
+ 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
+
+# Module JTAG
+ 'OCDR' : '$51', # On-Chip Debug Related Register
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_JTD': '$80', # JTAG Interface Disable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+
+# Module EXTERNAL_INTERRUPT
+ 'EICRA' : '$69', # External Interrupt Control Reg
+ 'EICRA_ISC3': '$c0', # External Interrupt Sense Contr
+ 'EICRA_ISC2': '$30', # External Interrupt Sense Contr
+ 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
+ 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
+ 'EICRB' : '$6a', # External Interrupt Control Reg
+ 'EICRB_ISC7': '$c0', # External Interrupt 7-4 Sense C
+ 'EICRB_ISC6': '$30', # External Interrupt 7-4 Sense C
+ 'EICRB_ISC5': '$c', # External Interrupt 7-4 Sense C
+ 'EICRB_ISC4': '$3', # External Interrupt 7-4 Sense C
+ 'EIMSK' : '$3d', # External Interrupt Mask Regist
+ 'EIMSK_INT': '$ff', # External Interrupt Request 7 E
+ 'EIFR' : '$3c', # External Interrupt Flag Regist
+ 'EIFR_INTF': '$ff', # External Interrupt Flags
+ 'PCMSK0' : '$6b', # Pin Change Mask Register 0
+ 'PCIFR' : '$3b', # Pin Change Interrupt Flag Regi
+ 'PCIFR_PCIF0': '$1', # Pin Change Interrupt Flag 0
+ 'PCICR' : '$68', # Pin Change Interrupt Control R
+ 'PCICR_PCIE0': '$1', # Pin Change Interrupt Enable 0
+
+# Module AD_CONVERTER
+ 'ADMUX' : '$7c', # The ADC multiplexer Selection
+ 'ADMUX_REFS': '$c0', # Reference Selection Bits
+ 'ADMUX_ADLAR': '$20', # Left Adjust Result
+ 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
+ 'ADCSRA' : '$7a', # The ADC Control and Status reg
+ 'ADCSRA_ADEN': '$80', # ADC Enable
+ 'ADCSRA_ADSC': '$40', # ADC Start Conversion
+ 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
+ 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
+ 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
+ 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
+ 'ADC' : '$78', # ADC Data Register Bytes
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ADHSM': '$80', # ADC High Speed Mode
+ 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Sources
+ 'DIDR0' : '$7e', # Digital Input Disable Register
+ 'DIDR0_ADC7D': '$80', # ADC7 Digital input Disable
+ 'DIDR0_ADC6D': '$40', # ADC6 Digital input Disable
+ 'DIDR0_ADC5D': '$20', # ADC5 Digital input Disable
+ 'DIDR0_ADC4D': '$10', # ADC4 Digital input Disable
+ 'DIDR0_ADC3D': '$8', # ADC3 Digital input Disable
+ 'DIDR0_ADC2D': '$4', # ADC2 Digital input Disable
+ 'DIDR0_ADC1D': '$2', # ADC1 Digital input Disable
+ 'DIDR0_ADC0D': '$1', # ADC0 Digital input Disable
+
+# Module ANALOG_COMPARATOR
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
+ 'ACSR' : '$50', # Analog Comparator Control And
+ 'ACSR_ACD': '$80', # Analog Comparator Disable
+ 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
+ 'ACSR_ACO': '$20', # Analog Compare Output
+ 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
+ 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
+ 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
+ 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
+ 'DIDR1' : '$7f', #
+ 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
+ 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
+
+# Module PLL
+ 'PLLCSR' : '$49', # PLL Status and Control registe
+ 'PLLCSR_PLLP': '$1c', # PLL prescaler Bits
+ 'PLLCSR_PLLE': '$2', # PLL Enable Bit
+ 'PLLCSR_PLOCK': '$1', # PLL Lock Status Bit
+
+ '__amforth_dummy':'0'
+}
diff --git a/amforth-6.5/avr8/devices/at90usb647/words/no-jtag.asm b/amforth-6.5/avr8/devices/at90usb647/words/no-jtag.asm
new file mode 100644
index 0000000..352a4bb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90usb647/words/no-jtag.asm
@@ -0,0 +1,14 @@
+; ( -- )
+; ( -- )
+; MCU
+; disable jtag at runtime
+VE_NOJTAG:
+ .dw $FF05
+ .db "-jtag",0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOJTAG
+XT_NOJTAG:
+ .dw PFA_NOJTAG
+PFA_NOJTAG:
+
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/at90usb647/words/no-wdt.asm b/amforth-6.5/avr8/devices/at90usb647/words/no-wdt.asm
new file mode 100644
index 0000000..ff6ddd1
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90usb647/words/no-wdt.asm
@@ -0,0 +1,34 @@
+; ( -- )
+; MCU
+; disable watch dog timer at runtime
+VE_NOWDT:
+ .dw $ff04
+ .db "-wdt"
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOWDT
+XT_NOWDT:
+ .dw PFA_NOWDT
+PFA_NOWDT:
+
+ in temp1,SREG
+ push temp1
+ ; Turn always off global interrupt.
+ cli
+ ; Reset Watchdog Timer
+ wdr
+ ; Clear WDRF in MCUSR
+ in temp1, MCUSR
+ andi temp1, (0xff & (0<<WDRF))
+ out MCUSR, temp1
+ ; Write logical one to WDCE and WDE
+ ; Keep old prescaler setting to prevent unintentional time-out
+ in_ temp1, WDTCSR
+ ori temp1, (1<<WDCE) | (1<<WDE)
+ out_ WDTCSR, temp1
+ ; Turn off WDT
+ ldi temp1, (0<<WDE)
+ out_ WDTCSR, temp1
+ ; restore status register
+ pop temp1
+ out SREG,temp1
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/at90usb647/words/sleep.asm b/amforth-6.5/avr8/devices/at90usb647/words/sleep.asm
new file mode 100644
index 0000000..256249c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90usb647/words/sleep.asm
@@ -0,0 +1,19 @@
+; ( mode -- )
+; MCU
+; put the controller into the specified sleep mode
+VE_SLEEP:
+ .dw $ff05
+ .db "sleep", 0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_SLEEP
+XT_SLEEP:
+ .dw PFA_SLEEP
+PFA_SLEEP:
+ andi tosl, 7 ; leave only legal mode bits
+ lsl tosl ; move to correct location (bits 3-1)
+ ori tosl, 1 ; set the SE bit
+ out_ SMCR, tosl ; set the sleep config
+ sleep ; nighty-night
+ out_ SMCR, zerol ; 0 protects against accidental sleeps
+ loadtos ; pop argument from stack
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/at90usb82/at90usb82.frt b/amforth-6.5/avr8/devices/at90usb82/at90usb82.frt
new file mode 100644
index 0000000..26ab16b
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90usb82/at90usb82.frt
@@ -0,0 +1,367 @@
+\ Partname: AT90USB82
+\ generated automatically
+
+\ PORTB
+&37 constant PORTB \ Port B Data Register
+&36 constant DDRB \ Port B Data Direction Register
+&35 constant PINB \ Port B Input Pins
+\ PORTD
+&43 constant PORTD \ Port D Data Register
+&42 constant DDRD \ Port D Data Direction Register
+&41 constant PIND \ Port D Input Pins
+\ SPI
+&76 constant SPCR \ SPI Control Register
+ $80 constant SPCR_SPIE \ SPI Interrupt Enable
+ $40 constant SPCR_SPE \ SPI Enable
+ $20 constant SPCR_DORD \ Data Order
+ $10 constant SPCR_MSTR \ Master/Slave Select
+ $08 constant SPCR_CPOL \ Clock polarity
+ $04 constant SPCR_CPHA \ Clock Phase
+ $03 constant SPCR_SPR \ SPI Clock Rate Selects
+&77 constant SPSR \ SPI Status Register
+ $80 constant SPSR_SPIF \ SPI Interrupt Flag
+ $40 constant SPSR_WCOL \ Write Collision Flag
+ $01 constant SPSR_SPI2X \ Double SPI Speed Bit
+&78 constant SPDR \ SPI Data Register
+\ BOOT_LOAD
+&87 constant SPMCSR \ Store Program Memory Control Register
+ $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
+ $20 constant SPMCSR_SIGRD \ Signature Row Read
+ $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
+ $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
+ $04 constant SPMCSR_PGWRT \ Page Write
+ $02 constant SPMCSR_PGERS \ Page Erase
+ $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
+\ EEPROM
+&65 constant EEAR \ EEPROM Address Register Low Bytes
+&64 constant EEDR \ EEPROM Data Register
+&63 constant EECR \ EEPROM Control Register
+ $30 constant EECR_EEPM \ EEPROM Programming Mode Bits
+ $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
+ $04 constant EECR_EEMPE \ EEPROM Master Write Enable
+ $02 constant EECR_EEPE \ EEPROM Write Enable
+ $01 constant EECR_EERE \ EEPROM Read Enable
+\ TIMER_COUNTER_0
+&72 constant OCR0B \ Timer/Counter0 Output Compare Register
+&71 constant OCR0A \ Timer/Counter0 Output Compare Register
+&70 constant TCNT0 \ Timer/Counter0
+&69 constant TCCR0B \ Timer/Counter Control Register B
+ $80 constant TCCR0B_FOC0A \ Force Output Compare A
+ $40 constant TCCR0B_FOC0B \ Force Output Compare B
+ $08 constant TCCR0B_WGM02 \
+ $07 constant TCCR0B_CS0 \ Clock Select
+&68 constant TCCR0A \ Timer/Counter Control Register A
+ $C0 constant TCCR0A_COM0A \ Compare Output Mode, Phase Correct PWM Mode
+ $30 constant TCCR0A_COM0B \ Compare Output Mode, Fast PWm
+ $03 constant TCCR0A_WGM0 \ Waveform Generation Mode
+&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
+ $04 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare Match B Interrupt Enable
+ $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match A Interrupt Enable
+ $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
+&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
+ $04 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare Flag 0B
+ $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0A
+ $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
+&67 constant GTCCR \ General Timer/Counter Control Register
+ $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
+ $01 constant GTCCR_PSRSYNC \ Prescaler Reset Timer/Counter1 and Timer/Counter0
+\ TIMER_COUNTER_1
+&128 constant TCCR1A \ Timer/Counter1 Control Register A
+ $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
+ $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
+ $0C constant TCCR1A_COM1C \ Compare Output Mode 1C, bits
+ $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
+&129 constant TCCR1B \ Timer/Counter1 Control Register B
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
+ $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
+&130 constant TCCR1C \ Timer/Counter 1 Control Register C
+ $80 constant TCCR1C_FOC1A \ Force Output Compare 1A
+ $40 constant TCCR1C_FOC1B \ Force Output Compare 1B
+ $20 constant TCCR1C_FOC1C \ Force Output Compare 1C
+&132 constant TCNT1 \ Timer/Counter1 Bytes
+&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
+&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
+&140 constant OCR1C \ Timer/Counter1 Output Compare Register C Bytes
+&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
+&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
+ $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
+ $08 constant TIMSK1_OCIE1C \ Timer/Counter1 Output Compare C Match Interrupt Enable
+ $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
+ $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
+ $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
+&54 constant TIFR1 \ Timer/Counter1 Interrupt Flag register
+ $20 constant TIFR1_ICF1 \ Input Capture Flag 1
+ $08 constant TIFR1_OCF1C \ Output Compare Flag 1C
+ $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
+ $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
+ $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
+\ PLL
+&73 constant PLLCSR \ PLL Status and Control register
+ $1C constant PLLCSR_PLLP \ PLL prescaler Bits
+ $02 constant PLLCSR_PLLE \ PLL Enable Bit
+ $01 constant PLLCSR_PLOCK \ PLL Lock Status Bit
+\ USB_DEVICE
+&244 constant UEINT \
+&242 constant UEBCLX \
+&241 constant UEDATX \
+&240 constant UEIENX \
+ $80 constant UEIENX_FLERRE \
+ $40 constant UEIENX_NAKINE \
+ $10 constant UEIENX_NAKOUTE \
+ $08 constant UEIENX_RXSTPE \
+ $04 constant UEIENX_RXOUTE \
+ $02 constant UEIENX_STALLEDE \
+ $01 constant UEIENX_TXINE \
+&239 constant UESTA1X \
+ $04 constant UESTA1X_CTRLDIR \
+ $03 constant UESTA1X_CURRBK \
+&238 constant UESTA0X \
+ $80 constant UESTA0X_CFGOK \
+ $40 constant UESTA0X_OVERFI \
+ $20 constant UESTA0X_UNDERFI \
+ $0C constant UESTA0X_DTSEQ \
+ $03 constant UESTA0X_NBUSYBK \
+&237 constant UECFG1X \
+ $70 constant UECFG1X_EPSIZE \
+ $0C constant UECFG1X_EPBK \
+ $02 constant UECFG1X_ALLOC \
+&236 constant UECFG0X \
+ $C0 constant UECFG0X_EPTYPE \
+ $01 constant UECFG0X_EPDIR \
+&235 constant UECONX \
+ $20 constant UECONX_STALLRQ \
+ $10 constant UECONX_STALLRQC \
+ $08 constant UECONX_RSTDT \
+ $01 constant UECONX_EPEN \
+&234 constant UERST \
+ $1F constant UERST_EPRST \
+&233 constant UENUM \
+&232 constant UEINTX \
+ $80 constant UEINTX_FIFOCON \
+ $40 constant UEINTX_NAKINI \
+ $20 constant UEINTX_RWAL \
+ $10 constant UEINTX_NAKOUTI \
+ $08 constant UEINTX_RXSTPI \
+ $04 constant UEINTX_RXOUTI \
+ $02 constant UEINTX_STALLEDI \
+ $01 constant UEINTX_TXINI \
+&230 constant UDMFN \
+ $10 constant UDMFN_FNCERR \
+&228 constant UDFNUM \
+&227 constant UDADDR \
+ $80 constant UDADDR_ADDEN \
+ $7F constant UDADDR_UADD \
+&226 constant UDIEN \
+ $40 constant UDIEN_UPRSME \
+ $20 constant UDIEN_EORSME \
+ $10 constant UDIEN_WAKEUPE \
+ $08 constant UDIEN_EORSTE \
+ $04 constant UDIEN_SOFE \
+ $01 constant UDIEN_SUSPE \
+&225 constant UDINT \
+ $40 constant UDINT_UPRSMI \
+ $20 constant UDINT_EORSMI \
+ $10 constant UDINT_WAKEUPI \
+ $08 constant UDINT_EORSTI \
+ $04 constant UDINT_SOFI \
+ $01 constant UDINT_SUSPI \
+&224 constant UDCON \
+ $04 constant UDCON_RSTCPU \
+ $02 constant UDCON_RMWKUP \
+ $01 constant UDCON_DETACH \
+&216 constant USBCON \ USB General Control Register
+ $80 constant USBCON_USBE \
+ $20 constant USBCON_FRZCLK \
+&99 constant REGCR \ Regulator Control Register
+ $01 constant REGCR_REGDIS \
+\ PS2
+&251 constant UPOE \
+ $C0 constant UPOE_UPWE \
+ $30 constant UPOE_UPDRV \
+ $08 constant UPOE_SCKI \
+ $04 constant UPOE_DATAI \
+ $02 constant UPOE_DPI \
+ $01 constant UPOE_DMI \
+&250 constant PS2CON \ PS2 Pad Enable register
+ $01 constant PS2CON_PS2EN \ Enable
+\ CPU
+&95 constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ $08 constant SREG_V \ Two's Complement Overflow Flag
+ $04 constant SREG_N \ Negative Flag
+ $02 constant SREG_Z \ Zero Flag
+ $01 constant SREG_C \ Carry Flag
+&93 constant SP \ Stack Pointer
+&85 constant MCUCR \ MCU Control Register
+ $10 constant MCUCR_PUD \ Pull-up disable
+ $02 constant MCUCR_IVSEL \ Interrupt Vector Select
+ $01 constant MCUCR_IVCE \ Interrupt Vector Change Enable
+&84 constant MCUSR \ MCU Status Register
+ $20 constant MCUSR_USBRF \ USB reset flag
+ $08 constant MCUSR_WDRF \ Watchdog Reset Flag
+ $04 constant MCUSR_BORF \ Brown-out Reset Flag
+ $02 constant MCUSR_EXTRF \ External Reset Flag
+ $01 constant MCUSR_PORF \ Power-on reset flag
+&102 constant OSCCAL \ Oscillator Calibration Value
+&97 constant CLKPR \
+ $80 constant CLKPR_CLKPCE \
+ $0F constant CLKPR_CLKPS \
+&83 constant SMCR \ Sleep Mode Control Register
+ $0E constant SMCR_SM \ Sleep Mode Select bits
+ $01 constant SMCR_SE \ Sleep Enable
+&92 constant EIND \ Extended Indirect Register
+&75 constant GPIOR2 \ General Purpose IO Register 2
+ $FF constant GPIOR2_GPIOR \ General Purpose IO Register 2 bis
+&74 constant GPIOR1 \ General Purpose IO Register 1
+ $FF constant GPIOR1_GPIOR \ General Purpose IO Register 1 bis
+&62 constant GPIOR0 \ General Purpose IO Register 0
+ $80 constant GPIOR0_GPIOR07 \ General Purpose IO Register 0 bit 7
+ $40 constant GPIOR0_GPIOR06 \ General Purpose IO Register 0 bit 6
+ $20 constant GPIOR0_GPIOR05 \ General Purpose IO Register 0 bit 5
+ $10 constant GPIOR0_GPIOR04 \ General Purpose IO Register 0 bit 4
+ $08 constant GPIOR0_GPIOR03 \ General Purpose IO Register 0 bit 3
+ $04 constant GPIOR0_GPIOR02 \ General Purpose IO Register 0 bit 2
+ $02 constant GPIOR0_GPIOR01 \ General Purpose IO Register 0 bit 1
+ $01 constant GPIOR0_GPIOR00 \ General Purpose IO Register 0 bit 0
+&101 constant PRR1 \ Power Reduction Register1
+ $80 constant PRR1_PRUSB \ Power Reduction USB
+ $01 constant PRR1_PRUSART1 \ Power Reduction USART1
+&100 constant PRR0 \ Power Reduction Register0
+ $20 constant PRR0_PRTIM0 \ Power Reduction Timer/Counter0
+ $08 constant PRR0_PRTIM1 \ Power Reduction Timer/Counter1
+ $04 constant PRR0_PRSPI \ Power Reduction Serial Peripheral Interface
+&210 constant CLKSTA \
+ $02 constant CLKSTA_RCON \
+ $01 constant CLKSTA_EXTON \
+&209 constant CLKSEL1 \
+ $F0 constant CLKSEL1_RCCKSEL \
+ $0F constant CLKSEL1_EXCKSEL \
+&208 constant CLKSEL0 \
+ $C0 constant CLKSEL0_RCSUT \
+ $30 constant CLKSEL0_EXSUT \
+ $08 constant CLKSEL0_RCE \
+ $04 constant CLKSEL0_EXTE \
+ $01 constant CLKSEL0_CLKS \
+&81 constant DWDR \ debugWire communication register
+\ EXTERNAL_INTERRUPT
+&105 constant EICRA \ External Interrupt Control Register A
+ $C0 constant EICRA_ISC3 \ External Interrupt Sense Control Bit
+ $30 constant EICRA_ISC2 \ External Interrupt Sense Control Bit
+ $0C constant EICRA_ISC1 \ External Interrupt Sense Control Bit
+ $03 constant EICRA_ISC0 \ External Interrupt Sense Control Bit
+&106 constant EICRB \ External Interrupt Control Register B
+ $C0 constant EICRB_ISC7 \ External Interrupt 7-4 Sense Control Bit
+ $30 constant EICRB_ISC6 \ External Interrupt 7-4 Sense Control Bit
+ $0C constant EICRB_ISC5 \ External Interrupt 7-4 Sense Control Bit
+ $03 constant EICRB_ISC4 \ External Interrupt 7-4 Sense Control Bit
+&61 constant EIMSK \ External Interrupt Mask Register
+ $FF constant EIMSK_INT \ External Interrupt Request 7 Enable
+&60 constant EIFR \ External Interrupt Flag Register
+ $FF constant EIFR_INTF \ External Interrupt Flags
+&107 constant PCMSK0 \ Pin Change Mask Register 0
+ $FF constant PCMSK0_PCINT \ Pin Change Enable Masks
+&108 constant PCMSK1 \ Pin Change Mask Register 1
+ $1F constant PCMSK1_PCINT \
+&59 constant PCIFR \ Pin Change Interrupt Flag Register
+ $03 constant PCIFR_PCIF \ Pin Change Interrupt Flags
+&104 constant PCICR \ Pin Change Interrupt Control Register
+ $03 constant PCICR_PCIE \ Pin Change Interrupt Enables
+\ USART1
+&206 constant UDR1 \ USART I/O Data Register
+&200 constant UCSR1A \ USART Control and Status Register A
+ $80 constant UCSR1A_RXC1 \ USART Receive Complete
+ $40 constant UCSR1A_TXC1 \ USART Transmitt Complete
+ $20 constant UCSR1A_UDRE1 \ USART Data Register Empty
+ $10 constant UCSR1A_FE1 \ Framing Error
+ $08 constant UCSR1A_DOR1 \ Data overRun
+ $04 constant UCSR1A_UPE1 \ Parity Error
+ $02 constant UCSR1A_U2X1 \ Double the USART transmission speed
+ $01 constant UCSR1A_MPCM1 \ Multi-processor Communication Mode
+&201 constant UCSR1B \ USART Control and Status Register B
+ $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable
+ $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable
+ $20 constant UCSR1B_UDRIE1 \ USART Data register Empty Interrupt Enable
+ $10 constant UCSR1B_RXEN1 \ Receiver Enable
+ $08 constant UCSR1B_TXEN1 \ Transmitter Enable
+ $04 constant UCSR1B_UCSZ12 \ Character Size
+ $02 constant UCSR1B_RXB81 \ Receive Data Bit 8
+ $01 constant UCSR1B_TXB81 \ Transmit Data Bit 8
+&202 constant UCSR1C \ USART Control and Status Register C
+ $C0 constant UCSR1C_UMSEL1 \ USART Mode Select
+ $30 constant UCSR1C_UPM1 \ Parity Mode Bits
+ $08 constant UCSR1C_USBS1 \ Stop Bit Select
+ $06 constant UCSR1C_UCSZ1 \ Character Size
+ $01 constant UCSR1C_UCPOL1 \ Clock Polarity
+&203 constant UCSR1D \ USART Control and Status Register D
+ $02 constant UCSR1D_CTSEN \ CTS Enable
+ $01 constant UCSR1D_RTSEN \ RTS Enable
+&204 constant UBRR1 \ USART Baud Rate Register Bytes
+\ WATCHDOG
+&96 constant WDTCSR \ Watchdog Timer Control Register
+ $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Flag
+ $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Enable
+ $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
+ $10 constant WDTCSR_WDCE \ Watchdog Change Enable
+ $08 constant WDTCSR_WDE \ Watch Dog Enable
+&98 constant WDTCKD \ Watchdog Timer Clock Divider
+ $08 constant WDTCKD_WDEWIF \ Watchdog Early Warning Interrupt Flag
+ $04 constant WDTCKD_WDEWIE \ Watchdog Early Warning Interrupt Enable
+ $03 constant WDTCKD_WCLKD \ Watchdog Timer Clock Dividers
+\ ANALOG_COMPARATOR
+&80 constant ACSR \ Analog Comparator Control And Status Register
+ $80 constant ACSR_ACD \ Analog Comparator Disable
+ $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
+ $20 constant ACSR_ACO \ Analog Compare Output
+ $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
+ $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
+ $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
+ $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
+&127 constant DIDR1 \
+ $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
+ $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
+\ PORTC
+&40 constant PORTC \ Port C Data Register
+ $F0 constant PORTC_PORTC \ Port C Data Register bits
+ $07 constant PORTC_PORTC \ Port C Data Register bits
+&39 constant DDRC \ Port C Data Direction Register
+ $F0 constant DDRC_DDC \ Port C Data Direction Register bits
+ $07 constant DDRC_DDC \ Port C Data Direction Register bits
+&38 constant PINC \ Port C Input Pins
+ $F0 constant PINC_PINC \ Port C Input Pins bits
+ $07 constant PINC_PINC \ Port C Input Pins bits
+
+\ Interrupts
+&2 constant INT0Addr \ External Interrupt Request 0
+&4 constant INT1Addr \ External Interrupt Request 1
+&6 constant INT2Addr \ External Interrupt Request 2
+&8 constant INT3Addr \ External Interrupt Request 3
+&10 constant INT4Addr \ External Interrupt Request 4
+&12 constant INT5Addr \ External Interrupt Request 5
+&14 constant INT6Addr \ External Interrupt Request 6
+&16 constant INT7Addr \ External Interrupt Request 7
+&18 constant PCINT0Addr \ Pin Change Interrupt Request 0
+&20 constant PCINT1Addr \ Pin Change Interrupt Request 1
+&22 constant USB_GENAddr \ USB General Interrupt Request
+&24 constant USB_COMAddr \ USB Endpoint/Pipe Interrupt Communication Reque
+&26 constant WDTAddr \ Watchdog Time-out Interrupt
+&28 constant TIMER1_CAPTAddr \ Timer/Counter2 Capture Event
+&30 constant TIMER1_COMPAAddr \ Timer/Counter2 Compare Match B
+&32 constant TIMER1_COMPBAddr \ Timer/Counter2 Compare Match B
+&34 constant TIMER1_COMPCAddr \ Timer/Counter2 Compare Match C
+&36 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+&38 constant TIMER0_COMPAAddr \ Timer/Counter0 Compare Match A
+&40 constant TIMER0_COMPBAddr \ Timer/Counter0 Compare Match B
+&42 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
+&44 constant SPI__STCAddr \ SPI Serial Transfer Complete
+&46 constant USART1__RXAddr \ USART1, Rx Complete
+&48 constant USART1__UDREAddr \ USART1 Data register Empty
+&50 constant USART1__TXAddr \ USART1, Tx Complete
+&52 constant ANALOG_COMPAddr \ Analog Comparator
+&54 constant EE_READYAddr \ EEPROM Ready
+&56 constant SPM_READYAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/at90usb82/device.asm b/amforth-6.5/avr8/devices/at90usb82/device.asm
new file mode 100644
index 0000000..9432dca
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90usb82/device.asm
@@ -0,0 +1,113 @@
+; Partname: AT90USB82
+; generated automatically, do not edit
+
+.nolist
+ .include "usb82def.inc"
+.list
+
+.equ ramstart = 256
+.equ CELLSIZE = 2
+.macro readflashcell
+ lsl zl
+ rol zh
+ lpm @0, Z+
+ lpm @1, Z+
+.endmacro
+.macro writeflashcell
+ lsl zl
+ rol zh
+.endmacro
+.set WANT_PORTB = 0
+.set WANT_PORTD = 0
+.set WANT_SPI = 0
+.set WANT_BOOT_LOAD = 0
+.set WANT_EEPROM = 0
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_PLL = 0
+.set WANT_USB_DEVICE = 0
+.set WANT_PS2 = 0
+.set WANT_CPU = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_USART1 = 0
+.set WANT_WATCHDOG = 0
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_PORTC = 0
+.equ intvecsize = 1 ; please verify; flash size: 8192 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.org 2
+ rcall isr ; External Interrupt Request 0
+.org 4
+ rcall isr ; External Interrupt Request 1
+.org 6
+ rcall isr ; External Interrupt Request 2
+.org 8
+ rcall isr ; External Interrupt Request 3
+.org 10
+ rcall isr ; External Interrupt Request 4
+.org 12
+ rcall isr ; External Interrupt Request 5
+.org 14
+ rcall isr ; External Interrupt Request 6
+.org 16
+ rcall isr ; External Interrupt Request 7
+.org 18
+ rcall isr ; Pin Change Interrupt Request 0
+.org 20
+ rcall isr ; Pin Change Interrupt Request 1
+.org 22
+ rcall isr ; USB General Interrupt Request
+.org 24
+ rcall isr ; USB Endpoint/Pipe Interrupt Communication Request
+.org 26
+ rcall isr ; Watchdog Time-out Interrupt
+.org 28
+ rcall isr ; Timer/Counter2 Capture Event
+.org 30
+ rcall isr ; Timer/Counter2 Compare Match B
+.org 32
+ rcall isr ; Timer/Counter2 Compare Match B
+.org 34
+ rcall isr ; Timer/Counter2 Compare Match C
+.org 36
+ rcall isr ; Timer/Counter1 Overflow
+.org 38
+ rcall isr ; Timer/Counter0 Compare Match A
+.org 40
+ rcall isr ; Timer/Counter0 Compare Match B
+.org 42
+ rcall isr ; Timer/Counter0 Overflow
+.org 44
+ rcall isr ; SPI Serial Transfer Complete
+.org 46
+ rcall isr ; USART1, Rx Complete
+.org 48
+ rcall isr ; USART1 Data register Empty
+.org 50
+ rcall isr ; USART1, Tx Complete
+.org 52
+ rcall isr ; Analog Comparator
+.org 54
+ rcall isr ; EEPROM Ready
+.org 56
+ rcall isr ; Store Program Memory Read
+.equ INTVECTORS = 29
+.nooverlap
+
+; compatability layer (maybe empty)
+
+; controller data area, environment query mcu-info
+mcu_info:
+mcu_ramsize:
+ .dw 512
+mcu_eepromsize:
+ .dw 512
+mcu_maxdp:
+ .dw 4096
+mcu_numints:
+ .dw 29
+mcu_name:
+ .dw 9
+ .db "AT90USB82",0
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/at90usb82/device.inc b/amforth-6.5/avr8/devices/at90usb82/device.inc
new file mode 100644
index 0000000..7ca46fb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90usb82/device.inc
@@ -0,0 +1,1155 @@
+; Partname: AT90USB82
+; generated automatically, no not edit
+
+.if WANT_PORTB == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw 37
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw 36
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw 35
+
+.endif
+.if WANT_PORTD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw 43
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw 42
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw 41
+
+.endif
+.if WANT_SPI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR:
+ .dw $ff04
+ .db "SPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR
+XT_SPCR:
+ .dw PFA_DOVARIABLE
+PFA_SPCR:
+ .dw 76
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR:
+ .dw $ff04
+ .db "SPSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR
+XT_SPSR:
+ .dw PFA_DOVARIABLE
+PFA_SPSR:
+ .dw 77
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR:
+ .dw $ff04
+ .db "SPDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR
+XT_SPDR:
+ .dw PFA_DOVARIABLE
+PFA_SPDR:
+ .dw 78
+
+.endif
+.if WANT_BOOT_LOAD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control Register
+VE_SPMCSR:
+ .dw $ff06
+ .db "SPMCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCSR
+XT_SPMCSR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCSR:
+ .dw 87
+
+.endif
+.if WANT_EEPROM == 1
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Address Register Low Bytes
+VE_EEAR:
+ .dw $ff04
+ .db "EEAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEAR
+XT_EEAR:
+ .dw PFA_DOVARIABLE
+PFA_EEAR:
+ .dw 65
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw 64
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw 63
+
+.endif
+.if WANT_TIMER_COUNTER_0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0B:
+ .dw $ff05
+ .db "OCR0B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0B
+XT_OCR0B:
+ .dw PFA_DOVARIABLE
+PFA_OCR0B:
+ .dw 72
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0A:
+ .dw $ff05
+ .db "OCR0A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0A
+XT_OCR0A:
+ .dw PFA_DOVARIABLE
+PFA_OCR0A:
+ .dw 71
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw 70
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register B
+VE_TCCR0B:
+ .dw $ff06
+ .db "TCCR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0B
+XT_TCCR0B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0B:
+ .dw 69
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register A
+VE_TCCR0A:
+ .dw $ff06
+ .db "TCCR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0A
+XT_TCCR0A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0A:
+ .dw 68
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Mask Register
+VE_TIMSK0:
+ .dw $ff06
+ .db "TIMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK0
+XT_TIMSK0:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK0:
+ .dw 110
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Flag register
+VE_TIFR0:
+ .dw $ff05
+ .db "TIFR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR0
+XT_TIFR0:
+ .dw PFA_DOVARIABLE
+PFA_TIFR0:
+ .dw 53
+; ( -- addr ) System Constant
+; R( -- )
+; General Timer/Counter Control Register
+VE_GTCCR:
+ .dw $ff05
+ .db "GTCCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GTCCR
+XT_GTCCR:
+ .dw PFA_DOVARIABLE
+PFA_GTCCR:
+ .dw 67
+
+.endif
+.if WANT_TIMER_COUNTER_1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw 128
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw 129
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter 1 Control Register C
+VE_TCCR1C:
+ .dw $ff06
+ .db "TCCR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1C
+XT_TCCR1C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1C:
+ .dw 130
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Bytes
+VE_TCNT1:
+ .dw $ff05
+ .db "TCNT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1
+XT_TCNT1:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1:
+ .dw 132
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register A Bytes
+VE_OCR1A:
+ .dw $ff05
+ .db "OCR1A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1A
+XT_OCR1A:
+ .dw PFA_DOVARIABLE
+PFA_OCR1A:
+ .dw 136
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register B Bytes
+VE_OCR1B:
+ .dw $ff05
+ .db "OCR1B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1B
+XT_OCR1B:
+ .dw PFA_DOVARIABLE
+PFA_OCR1B:
+ .dw 138
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register C Bytes
+VE_OCR1C:
+ .dw $ff05
+ .db "OCR1C",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1C
+XT_OCR1C:
+ .dw PFA_DOVARIABLE
+PFA_OCR1C:
+ .dw 140
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Bytes
+VE_ICR1:
+ .dw $ff04
+ .db "ICR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1
+XT_ICR1:
+ .dw PFA_DOVARIABLE
+PFA_ICR1:
+ .dw 134
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Mask Register
+VE_TIMSK1:
+ .dw $ff06
+ .db "TIMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK1
+XT_TIMSK1:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK1:
+ .dw 111
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Flag register
+VE_TIFR1:
+ .dw $ff05
+ .db "TIFR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR1
+XT_TIFR1:
+ .dw PFA_DOVARIABLE
+PFA_TIFR1:
+ .dw 54
+
+.endif
+.if WANT_PLL == 1
+; ( -- addr ) System Constant
+; R( -- )
+; PLL Status and Control register
+VE_PLLCSR:
+ .dw $ff06
+ .db "PLLCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PLLCSR
+XT_PLLCSR:
+ .dw PFA_DOVARIABLE
+PFA_PLLCSR:
+ .dw 73
+
+.endif
+.if WANT_USB_DEVICE == 1
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UEINT:
+ .dw $ff05
+ .db "UEINT",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UEINT
+XT_UEINT:
+ .dw PFA_DOVARIABLE
+PFA_UEINT:
+ .dw 244
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UEBCLX:
+ .dw $ff06
+ .db "UEBCLX"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UEBCLX
+XT_UEBCLX:
+ .dw PFA_DOVARIABLE
+PFA_UEBCLX:
+ .dw 242
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UEDATX:
+ .dw $ff06
+ .db "UEDATX"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UEDATX
+XT_UEDATX:
+ .dw PFA_DOVARIABLE
+PFA_UEDATX:
+ .dw 241
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UEIENX:
+ .dw $ff06
+ .db "UEIENX"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UEIENX
+XT_UEIENX:
+ .dw PFA_DOVARIABLE
+PFA_UEIENX:
+ .dw 240
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UESTA1X:
+ .dw $ff07
+ .db "UESTA1X",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UESTA1X
+XT_UESTA1X:
+ .dw PFA_DOVARIABLE
+PFA_UESTA1X:
+ .dw 239
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UESTA0X:
+ .dw $ff07
+ .db "UESTA0X",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UESTA0X
+XT_UESTA0X:
+ .dw PFA_DOVARIABLE
+PFA_UESTA0X:
+ .dw 238
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UECFG1X:
+ .dw $ff07
+ .db "UECFG1X",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UECFG1X
+XT_UECFG1X:
+ .dw PFA_DOVARIABLE
+PFA_UECFG1X:
+ .dw 237
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UECFG0X:
+ .dw $ff07
+ .db "UECFG0X",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UECFG0X
+XT_UECFG0X:
+ .dw PFA_DOVARIABLE
+PFA_UECFG0X:
+ .dw 236
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UECONX:
+ .dw $ff06
+ .db "UECONX"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UECONX
+XT_UECONX:
+ .dw PFA_DOVARIABLE
+PFA_UECONX:
+ .dw 235
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UERST:
+ .dw $ff05
+ .db "UERST",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UERST
+XT_UERST:
+ .dw PFA_DOVARIABLE
+PFA_UERST:
+ .dw 234
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UENUM:
+ .dw $ff05
+ .db "UENUM",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UENUM
+XT_UENUM:
+ .dw PFA_DOVARIABLE
+PFA_UENUM:
+ .dw 233
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UEINTX:
+ .dw $ff06
+ .db "UEINTX"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UEINTX
+XT_UEINTX:
+ .dw PFA_DOVARIABLE
+PFA_UEINTX:
+ .dw 232
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UDMFN:
+ .dw $ff05
+ .db "UDMFN",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDMFN
+XT_UDMFN:
+ .dw PFA_DOVARIABLE
+PFA_UDMFN:
+ .dw 230
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UDFNUM:
+ .dw $ff06
+ .db "UDFNUM"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDFNUM
+XT_UDFNUM:
+ .dw PFA_DOVARIABLE
+PFA_UDFNUM:
+ .dw 228
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UDADDR:
+ .dw $ff06
+ .db "UDADDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDADDR
+XT_UDADDR:
+ .dw PFA_DOVARIABLE
+PFA_UDADDR:
+ .dw 227
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UDIEN:
+ .dw $ff05
+ .db "UDIEN",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDIEN
+XT_UDIEN:
+ .dw PFA_DOVARIABLE
+PFA_UDIEN:
+ .dw 226
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UDINT:
+ .dw $ff05
+ .db "UDINT",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDINT
+XT_UDINT:
+ .dw PFA_DOVARIABLE
+PFA_UDINT:
+ .dw 225
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UDCON:
+ .dw $ff05
+ .db "UDCON",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDCON
+XT_UDCON:
+ .dw PFA_DOVARIABLE
+PFA_UDCON:
+ .dw 224
+; ( -- addr ) System Constant
+; R( -- )
+; USB General Control Register
+VE_USBCON:
+ .dw $ff06
+ .db "USBCON"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USBCON
+XT_USBCON:
+ .dw PFA_DOVARIABLE
+PFA_USBCON:
+ .dw 216
+; ( -- addr ) System Constant
+; R( -- )
+; Regulator Control Register
+VE_REGCR:
+ .dw $ff05
+ .db "REGCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_REGCR
+XT_REGCR:
+ .dw PFA_DOVARIABLE
+PFA_REGCR:
+ .dw 99
+
+.endif
+.if WANT_PS2 == 1
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UPOE:
+ .dw $ff04
+ .db "UPOE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UPOE
+XT_UPOE:
+ .dw PFA_DOVARIABLE
+PFA_UPOE:
+ .dw 251
+; ( -- addr ) System Constant
+; R( -- )
+; PS2 Pad Enable register
+VE_PS2CON:
+ .dw $ff06
+ .db "PS2CON"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PS2CON
+XT_PS2CON:
+ .dw PFA_DOVARIABLE
+PFA_PS2CON:
+ .dw 250
+
+.endif
+.if WANT_CPU == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw 95
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer
+VE_SP:
+ .dw $ff02
+ .db "SP"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SP
+XT_SP:
+ .dw PFA_DOVARIABLE
+PFA_SP:
+ .dw 93
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw 85
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Status Register
+VE_MCUSR:
+ .dw $ff05
+ .db "MCUSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUSR
+XT_MCUSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUSR:
+ .dw 84
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Calibration Value
+VE_OSCCAL:
+ .dw $ff06
+ .db "OSCCAL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSCCAL
+XT_OSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_OSCCAL:
+ .dw 102
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_CLKPR:
+ .dw $ff05
+ .db "CLKPR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKPR
+XT_CLKPR:
+ .dw PFA_DOVARIABLE
+PFA_CLKPR:
+ .dw 97
+; ( -- addr ) System Constant
+; R( -- )
+; Sleep Mode Control Register
+VE_SMCR:
+ .dw $ff04
+ .db "SMCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SMCR
+XT_SMCR:
+ .dw PFA_DOVARIABLE
+PFA_SMCR:
+ .dw 83
+; ( -- addr ) System Constant
+; R( -- )
+; Extended Indirect Register
+VE_EIND:
+ .dw $ff04
+ .db "EIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIND
+XT_EIND:
+ .dw PFA_DOVARIABLE
+PFA_EIND:
+ .dw 92
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 2
+VE_GPIOR2:
+ .dw $ff06
+ .db "GPIOR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR2
+XT_GPIOR2:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR2:
+ .dw 75
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 1
+VE_GPIOR1:
+ .dw $ff06
+ .db "GPIOR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR1
+XT_GPIOR1:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR1:
+ .dw 74
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 0
+VE_GPIOR0:
+ .dw $ff06
+ .db "GPIOR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR0
+XT_GPIOR0:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR0:
+ .dw 62
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register1
+VE_PRR1:
+ .dw $ff04
+ .db "PRR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR1
+XT_PRR1:
+ .dw PFA_DOVARIABLE
+PFA_PRR1:
+ .dw 101
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register0
+VE_PRR0:
+ .dw $ff04
+ .db "PRR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR0
+XT_PRR0:
+ .dw PFA_DOVARIABLE
+PFA_PRR0:
+ .dw 100
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_CLKSTA:
+ .dw $ff06
+ .db "CLKSTA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKSTA
+XT_CLKSTA:
+ .dw PFA_DOVARIABLE
+PFA_CLKSTA:
+ .dw 210
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_CLKSEL1:
+ .dw $ff07
+ .db "CLKSEL1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKSEL1
+XT_CLKSEL1:
+ .dw PFA_DOVARIABLE
+PFA_CLKSEL1:
+ .dw 209
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_CLKSEL0:
+ .dw $ff07
+ .db "CLKSEL0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKSEL0
+XT_CLKSEL0:
+ .dw PFA_DOVARIABLE
+PFA_CLKSEL0:
+ .dw 208
+; ( -- addr ) System Constant
+; R( -- )
+; debugWire communication register
+VE_DWDR:
+ .dw $ff04
+ .db "DWDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DWDR
+XT_DWDR:
+ .dw PFA_DOVARIABLE
+PFA_DWDR:
+ .dw 81
+
+.endif
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register A
+VE_EICRA:
+ .dw $ff05
+ .db "EICRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRA
+XT_EICRA:
+ .dw PFA_DOVARIABLE
+PFA_EICRA:
+ .dw 105
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register B
+VE_EICRB:
+ .dw $ff05
+ .db "EICRB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRB
+XT_EICRB:
+ .dw PFA_DOVARIABLE
+PFA_EICRB:
+ .dw 106
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Mask Register
+VE_EIMSK:
+ .dw $ff05
+ .db "EIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIMSK
+XT_EIMSK:
+ .dw PFA_DOVARIABLE
+PFA_EIMSK:
+ .dw 61
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Flag Register
+VE_EIFR:
+ .dw $ff04
+ .db "EIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIFR
+XT_EIFR:
+ .dw PFA_DOVARIABLE
+PFA_EIFR:
+ .dw 60
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 0
+VE_PCMSK0:
+ .dw $ff06
+ .db "PCMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK0
+XT_PCMSK0:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK0:
+ .dw 107
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 1
+VE_PCMSK1:
+ .dw $ff06
+ .db "PCMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK1
+XT_PCMSK1:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK1:
+ .dw 108
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Interrupt Flag Register
+VE_PCIFR:
+ .dw $ff05
+ .db "PCIFR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCIFR
+XT_PCIFR:
+ .dw PFA_DOVARIABLE
+PFA_PCIFR:
+ .dw 59
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Interrupt Control Register
+VE_PCICR:
+ .dw $ff05
+ .db "PCICR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCICR
+XT_PCICR:
+ .dw PFA_DOVARIABLE
+PFA_PCICR:
+ .dw 104
+
+.endif
+.if WANT_USART1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR1:
+ .dw $ff04
+ .db "UDR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR1
+XT_UDR1:
+ .dw PFA_DOVARIABLE
+PFA_UDR1:
+ .dw 206
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR1A:
+ .dw $ff06
+ .db "UCSR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1A
+XT_UCSR1A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1A:
+ .dw 200
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR1B:
+ .dw $ff06
+ .db "UCSR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1B
+XT_UCSR1B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1B:
+ .dw 201
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR1C:
+ .dw $ff06
+ .db "UCSR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1C
+XT_UCSR1C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1C:
+ .dw 202
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register D
+VE_UCSR1D:
+ .dw $ff06
+ .db "UCSR1D"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1D
+XT_UCSR1D:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1D:
+ .dw 203
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Bytes
+VE_UBRR1:
+ .dw $ff05
+ .db "UBRR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR1
+XT_UBRR1:
+ .dw PFA_DOVARIABLE
+PFA_UBRR1:
+ .dw 204
+
+.endif
+.if WANT_WATCHDOG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCSR:
+ .dw $ff06
+ .db "WDTCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCSR
+XT_WDTCSR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCSR:
+ .dw 96
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Clock Divider
+VE_WDTCKD:
+ .dw $ff06
+ .db "WDTCKD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCKD
+XT_WDTCKD:
+ .dw PFA_DOVARIABLE
+PFA_WDTCKD:
+ .dw 98
+
+.endif
+.if WANT_ANALOG_COMPARATOR == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Control And Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw 80
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_DIDR1:
+ .dw $ff05
+ .db "DIDR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR1
+XT_DIDR1:
+ .dw PFA_DOVARIABLE
+PFA_DIDR1:
+ .dw 127
+
+.endif
+.if WANT_PORTC == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Register
+VE_PORTC:
+ .dw $ff05
+ .db "PORTC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTC
+XT_PORTC:
+ .dw PFA_DOVARIABLE
+PFA_PORTC:
+ .dw 40
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Direction Register
+VE_DDRC:
+ .dw $ff04
+ .db "DDRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRC
+XT_DDRC:
+ .dw PFA_DOVARIABLE
+PFA_DDRC:
+ .dw 39
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Input Pins
+VE_PINC:
+ .dw $ff04
+ .db "PINC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINC
+XT_PINC:
+ .dw PFA_DOVARIABLE
+PFA_PINC:
+ .dw 38
+
+.endif
diff --git a/amforth-6.5/avr8/devices/at90usb82/device.py b/amforth-6.5/avr8/devices/at90usb82/device.py
new file mode 100644
index 0000000..2a45f1d
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90usb82/device.py
@@ -0,0 +1,387 @@
+# Generated Automatically
+
+# Partname AT90USB82
+
+MCUREGS = {
+# Interrupt Vectors
+ 'INT0Addr' : '#4', # External Interrupt Request 0
+ 'INT1Addr' : '#8', # External Interrupt Request 1
+ 'INT2Addr' : '#12', # External Interrupt Request 2
+ 'INT3Addr' : '#16', # External Interrupt Request 3
+ 'INT4Addr' : '#20', # External Interrupt Request 4
+ 'INT5Addr' : '#24', # External Interrupt Request 5
+ 'INT6Addr' : '#28', # External Interrupt Request 6
+ 'INT7Addr' : '#32', # External Interrupt Request 7
+ 'PCINT0Addr' : '#36', # Pin Change Interrupt Request 0
+ 'PCINT1Addr' : '#40', # Pin Change Interrupt Request 1
+ 'USB_GENAddr' : '#44', # USB General Interrupt Request
+ 'USB_COMAddr' : '#48', # USB Endpoint/Pipe Interrupt Communication Request
+ 'WDTAddr' : '#52', # Watchdog Time-out Interrupt
+ 'TIMER1_CAPTAddr' : '#56', # Timer/Counter2 Capture Event
+ 'TIMER1_COMPAAddr' : '#60', # Timer/Counter2 Compare Match B
+ 'TIMER1_COMPBAddr' : '#64', # Timer/Counter2 Compare Match B
+ 'TIMER1_COMPCAddr' : '#68', # Timer/Counter2 Compare Match C
+ 'TIMER1_OVFAddr' : '#72', # Timer/Counter1 Overflow
+ 'TIMER0_COMPAAddr' : '#76', # Timer/Counter0 Compare Match A
+ 'TIMER0_COMPBAddr' : '#80', # Timer/Counter0 Compare Match B
+ 'TIMER0_OVFAddr' : '#84', # Timer/Counter0 Overflow
+ 'SPI_STCAddr' : '#88', # SPI Serial Transfer Complete
+ 'USART1_RXAddr' : '#92', # USART1, Rx Complete
+ 'USART1_UDREAddr' : '#96', # USART1 Data register Empty
+ 'USART1_TXAddr' : '#100', # USART1, Tx Complete
+ 'ANALOG_COMPAddr' : '#104', # Analog Comparator
+ 'EE_READYAddr' : '#108', # EEPROM Ready
+ 'SPM_READYAddr' : '#112', # Store Program Memory Read
+
+# Module PORTB
+ 'PORTB' : '$25', # Port B Data Register
+ 'DDRB' : '$24', # Port B Data Direction Register
+ 'PINB' : '$23', # Port B Input Pins
+
+# Module PORTD
+ 'PORTD' : '$2b', # Port D Data Register
+ 'DDRD' : '$2a', # Port D Data Direction Register
+ 'PIND' : '$29', # Port D Input Pins
+
+# Module SPI
+ 'SPCR' : '$4c', # SPI Control Register
+ 'SPCR_SPIE': '$80', # SPI Interrupt Enable
+ 'SPCR_SPE': '$40', # SPI Enable
+ 'SPCR_DORD': '$20', # Data Order
+ 'SPCR_MSTR': '$10', # Master/Slave Select
+ 'SPCR_CPOL': '$8', # Clock polarity
+ 'SPCR_CPHA': '$4', # Clock Phase
+ 'SPCR_SPR': '$3', # SPI Clock Rate Selects
+ 'SPSR' : '$4d', # SPI Status Register
+ 'SPSR_SPIF': '$80', # SPI Interrupt Flag
+ 'SPSR_WCOL': '$40', # Write Collision Flag
+ 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
+ 'SPDR' : '$4e', # SPI Data Register
+
+# Module BOOT_LOAD
+ 'SPMCSR' : '$57', # Store Program Memory Control R
+ 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
+ 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
+ 'SPMCSR_SIGRD': '$20', # Signature Row Read
+ 'SPMCSR_RWWSRE': '$10', # Read While Write section read
+ 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
+ 'SPMCSR_PGWRT': '$4', # Page Write
+ 'SPMCSR_PGERS': '$2', # Page Erase
+ 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
+
+# Module EEPROM
+ 'EEAR' : '$41', # EEPROM Address Register Low By
+ 'EEDR' : '$40', # EEPROM Data Register
+ 'EECR' : '$3f', # EEPROM Control Register
+ 'EECR_EEPM': '$30', # EEPROM Programming Mode Bits
+ 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
+ 'EECR_EEMPE': '$4', # EEPROM Master Write Enable
+ 'EECR_EEPE': '$2', # EEPROM Write Enable
+ 'EECR_EERE': '$1', # EEPROM Read Enable
+
+# Module TIMER_COUNTER_0
+ 'OCR0B' : '$48', # Timer/Counter0 Output Compare
+ 'OCR0A' : '$47', # Timer/Counter0 Output Compare
+ 'TCNT0' : '$46', # Timer/Counter0
+ 'TCCR0B' : '$45', # Timer/Counter Control Register
+ 'TCCR0B_FOC0A': '$80', # Force Output Compare A
+ 'TCCR0B_FOC0B': '$40', # Force Output Compare B
+ 'TCCR0B_WGM02': '$8', #
+ 'TCCR0B_CS0': '$7', # Clock Select
+ 'TCCR0A' : '$44', # Timer/Counter Control Registe
+ 'TCCR0A_COM0A': '$c0', # Compare Output Mode, Phase Cor
+ 'TCCR0A_COM0B': '$30', # Compare Output Mode, Fast PWm
+ 'TCCR0A_WGM0': '$3', # Waveform Generation Mode
+ 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
+ 'TIMSK0_OCIE0B': '$4', # Timer/Counter0 Output Compare
+ 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
+ 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
+ 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
+ 'TIFR0_OCF0B': '$4', # Timer/Counter0 Output Compare
+ 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
+ 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSRSYNC': '$1', # Prescaler Reset Timer/Counter1
+
+# Module TIMER_COUNTER_1
+ 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
+ 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
+ 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
+ 'TCCR1A_COM1C': '$c', # Compare Output Mode 1C, bits
+ 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
+ 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
+ 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
+ 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
+ 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
+ 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
+ 'TCCR1C' : '$82', # Timer/Counter 1 Control Regist
+ 'TCCR1C_FOC1A': '$80', # Force Output Compare 1A
+ 'TCCR1C_FOC1B': '$40', # Force Output Compare 1B
+ 'TCCR1C_FOC1C': '$20', # Force Output Compare 1C
+ 'TCNT1' : '$84', # Timer/Counter1 Bytes
+ 'OCR1A' : '$88', # Timer/Counter1 Output Compare
+ 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
+ 'OCR1C' : '$8c', # Timer/Counter1 Output Compare
+ 'ICR1' : '$86', # Timer/Counter1 Input Capture R
+ 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
+ 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
+ 'TIMSK1_OCIE1C': '$8', # Timer/Counter1 Output Compare
+ 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
+ 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
+ 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
+ 'TIFR1' : '$36', # Timer/Counter1 Interrupt Flag
+ 'TIFR1_ICF1': '$20', # Input Capture Flag 1
+ 'TIFR1_OCF1C': '$8', # Output Compare Flag 1C
+ 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
+ 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
+ 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
+
+# Module PLL
+ 'PLLCSR' : '$49', # PLL Status and Control registe
+ 'PLLCSR_PLLP': '$1c', # PLL prescaler Bits
+ 'PLLCSR_PLLE': '$2', # PLL Enable Bit
+ 'PLLCSR_PLOCK': '$1', # PLL Lock Status Bit
+
+# Module USB_DEVICE
+ 'UEINT' : '$f4', #
+ 'UEBCLX' : '$f2', #
+ 'UEDATX' : '$f1', #
+ 'UEIENX' : '$f0', #
+ 'UEIENX_FLERRE': '$80', #
+ 'UEIENX_NAKINE': '$40', #
+ 'UEIENX_NAKOUTE': '$10', #
+ 'UEIENX_RXSTPE': '$8', #
+ 'UEIENX_RXOUTE': '$4', #
+ 'UEIENX_STALLEDE': '$2', #
+ 'UEIENX_TXINE': '$1', #
+ 'UESTA1X' : '$ef', #
+ 'UESTA1X_CTRLDIR': '$4', #
+ 'UESTA1X_CURRBK': '$3', #
+ 'UESTA0X' : '$ee', #
+ 'UESTA0X_CFGOK': '$80', #
+ 'UESTA0X_OVERFI': '$40', #
+ 'UESTA0X_UNDERFI': '$20', #
+ 'UESTA0X_DTSEQ': '$c', #
+ 'UESTA0X_NBUSYBK': '$3', #
+ 'UECFG1X' : '$ed', #
+ 'UECFG1X_EPSIZE': '$70', #
+ 'UECFG1X_EPBK': '$c', #
+ 'UECFG1X_ALLOC': '$2', #
+ 'UECFG0X' : '$ec', #
+ 'UECFG0X_EPTYPE': '$c0', #
+ 'UECFG0X_EPDIR': '$1', #
+ 'UECONX' : '$eb', #
+ 'UECONX_STALLRQ': '$20', #
+ 'UECONX_STALLRQC': '$10', #
+ 'UECONX_RSTDT': '$8', #
+ 'UECONX_EPEN': '$1', #
+ 'UERST' : '$ea', #
+ 'UERST_EPRST': '$1f', #
+ 'UENUM' : '$e9', #
+ 'UEINTX' : '$e8', #
+ 'UEINTX_FIFOCON': '$80', #
+ 'UEINTX_NAKINI': '$40', #
+ 'UEINTX_RWAL': '$20', #
+ 'UEINTX_NAKOUTI': '$10', #
+ 'UEINTX_RXSTPI': '$8', #
+ 'UEINTX_RXOUTI': '$4', #
+ 'UEINTX_STALLEDI': '$2', #
+ 'UEINTX_TXINI': '$1', #
+ 'UDMFN' : '$e6', #
+ 'UDMFN_FNCERR': '$10', #
+ 'UDFNUM' : '$e4', #
+ 'UDADDR' : '$e3', #
+ 'UDADDR_ADDEN': '$80', #
+ 'UDADDR_UADD': '$7f', #
+ 'UDIEN' : '$e2', #
+ 'UDIEN_UPRSME': '$40', #
+ 'UDIEN_EORSME': '$20', #
+ 'UDIEN_WAKEUPE': '$10', #
+ 'UDIEN_EORSTE': '$8', #
+ 'UDIEN_SOFE': '$4', #
+ 'UDIEN_SUSPE': '$1', #
+ 'UDINT' : '$e1', #
+ 'UDINT_UPRSMI': '$40', #
+ 'UDINT_EORSMI': '$20', #
+ 'UDINT_WAKEUPI': '$10', #
+ 'UDINT_EORSTI': '$8', #
+ 'UDINT_SOFI': '$4', #
+ 'UDINT_SUSPI': '$1', #
+ 'UDCON' : '$e0', #
+ 'UDCON_RSTCPU': '$4', #
+ 'UDCON_RMWKUP': '$2', #
+ 'UDCON_DETACH': '$1', #
+ 'USBCON' : '$d8', # USB General Control Register
+ 'USBCON_USBE': '$80', #
+ 'USBCON_FRZCLK': '$20', #
+ 'REGCR' : '$63', # Regulator Control Register
+ 'REGCR_REGDIS': '$1', #
+
+# Module PS2
+ 'UPOE' : '$fb', #
+ 'UPOE_UPWE': '$c0', #
+ 'UPOE_UPDRV': '$30', #
+ 'UPOE_SCKI': '$8', #
+ 'UPOE_DATAI': '$4', #
+ 'UPOE_DPI': '$2', #
+ 'UPOE_DMI': '$1', #
+ 'PS2CON' : '$fa', # PS2 Pad Enable register
+ 'PS2CON_PS2EN': '$1', # Enable
+
+# Module CPU
+ 'SREG' : '$5f', # Status Register
+ 'SREG_I': '$80', # Global Interrupt Enable
+ 'SREG_T': '$40', # Bit Copy Storage
+ 'SREG_H': '$20', # Half Carry Flag
+ 'SREG_S': '$10', # Sign Bit
+ 'SREG_V': '$8', # Two's Complement Overflow Flag
+ 'SREG_N': '$4', # Negative Flag
+ 'SREG_Z': '$2', # Zero Flag
+ 'SREG_C': '$1', # Carry Flag
+ 'SP' : '$5d', # Stack Pointer
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_PUD': '$10', # Pull-up disable
+ 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
+ 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_USBRF': '$20', # USB reset flag
+ 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
+ 'MCUSR_BORF': '$4', # Brown-out Reset Flag
+ 'MCUSR_EXTRF': '$2', # External Reset Flag
+ 'MCUSR_PORF': '$1', # Power-on reset flag
+ 'OSCCAL' : '$66', # Oscillator Calibration Value
+ 'CLKPR' : '$61', #
+ 'CLKPR_CLKPCE': '$80', #
+ 'CLKPR_CLKPS': '$f', #
+ 'SMCR' : '$53', # Sleep Mode Control Register
+ 'SMCR_SM': '$e', # Sleep Mode Select bits
+ 'SMCR_SE': '$1', # Sleep Enable
+ 'EIND' : '$5c', # Extended Indirect Register
+ 'GPIOR2' : '$4b', # General Purpose IO Register 2
+ 'GPIOR2_GPIOR': '$ff', # General Purpose IO Register 2
+ 'GPIOR1' : '$4a', # General Purpose IO Register 1
+ 'GPIOR1_GPIOR': '$ff', # General Purpose IO Register 1
+ 'GPIOR0' : '$3e', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR07': '$80', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR06': '$40', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR05': '$20', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR04': '$10', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR03': '$8', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR02': '$4', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR01': '$2', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR00': '$1', # General Purpose IO Register 0
+ 'PRR1' : '$65', # Power Reduction Register1
+ 'PRR1_PRUSB': '$80', # Power Reduction USB
+ 'PRR1_PRUSART1': '$1', # Power Reduction USART1
+ 'PRR0' : '$64', # Power Reduction Register0
+ 'PRR0_PRTIM0': '$20', # Power Reduction Timer/Counter0
+ 'PRR0_PRTIM1': '$8', # Power Reduction Timer/Counter1
+ 'PRR0_PRSPI': '$4', # Power Reduction Serial Periphe
+ 'CLKSTA' : '$d2', #
+ 'CLKSTA_RCON': '$2', #
+ 'CLKSTA_EXTON': '$1', #
+ 'CLKSEL1' : '$d1', #
+ 'CLKSEL1_RCCKSEL': '$f0', #
+ 'CLKSEL1_EXCKSEL': '$f', #
+ 'CLKSEL0' : '$d0', #
+ 'CLKSEL0_RCSUT': '$c0', #
+ 'CLKSEL0_EXSUT': '$30', #
+ 'CLKSEL0_RCE': '$8', #
+ 'CLKSEL0_EXTE': '$4', #
+ 'CLKSEL0_CLKS': '$1', #
+ 'DWDR' : '$51', # debugWire communication regist
+
+# Module EXTERNAL_INTERRUPT
+ 'EICRA' : '$69', # External Interrupt Control Reg
+ 'EICRA_ISC3': '$c0', # External Interrupt Sense Contr
+ 'EICRA_ISC2': '$30', # External Interrupt Sense Contr
+ 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
+ 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
+ 'EICRB' : '$6a', # External Interrupt Control Reg
+ 'EICRB_ISC7': '$c0', # External Interrupt 7-4 Sense C
+ 'EICRB_ISC6': '$30', # External Interrupt 7-4 Sense C
+ 'EICRB_ISC5': '$c', # External Interrupt 7-4 Sense C
+ 'EICRB_ISC4': '$3', # External Interrupt 7-4 Sense C
+ 'EIMSK' : '$3d', # External Interrupt Mask Regist
+ 'EIMSK_INT': '$ff', # External Interrupt Request 7 E
+ 'EIFR' : '$3c', # External Interrupt Flag Regist
+ 'EIFR_INTF': '$ff', # External Interrupt Flags
+ 'PCMSK0' : '$6b', # Pin Change Mask Register 0
+ 'PCMSK0_PCINT': '$ff', # Pin Change Enable Masks
+ 'PCMSK1' : '$6c', # Pin Change Mask Register 1
+ 'PCMSK1_PCINT': '$1f', #
+ 'PCIFR' : '$3b', # Pin Change Interrupt Flag Regi
+ 'PCIFR_PCIF': '$3', # Pin Change Interrupt Flags
+ 'PCICR' : '$68', # Pin Change Interrupt Control R
+ 'PCICR_PCIE': '$3', # Pin Change Interrupt Enables
+
+# Module USART1
+ 'UDR1' : '$ce', # USART I/O Data Register
+ 'UCSR1A' : '$c8', # USART Control and Status Regis
+ 'UCSR1A_RXC1': '$80', # USART Receive Complete
+ 'UCSR1A_TXC1': '$40', # USART Transmitt Complete
+ 'UCSR1A_UDRE1': '$20', # USART Data Register Empty
+ 'UCSR1A_FE1': '$10', # Framing Error
+ 'UCSR1A_DOR1': '$8', # Data overRun
+ 'UCSR1A_UPE1': '$4', # Parity Error
+ 'UCSR1A_U2X1': '$2', # Double the USART transmission
+ 'UCSR1A_MPCM1': '$1', # Multi-processor Communication
+ 'UCSR1B' : '$c9', # USART Control and Status Regis
+ 'UCSR1B_RXCIE1': '$80', # RX Complete Interrupt Enable
+ 'UCSR1B_TXCIE1': '$40', # TX Complete Interrupt Enable
+ 'UCSR1B_UDRIE1': '$20', # USART Data register Empty Inte
+ 'UCSR1B_RXEN1': '$10', # Receiver Enable
+ 'UCSR1B_TXEN1': '$8', # Transmitter Enable
+ 'UCSR1B_UCSZ12': '$4', # Character Size
+ 'UCSR1B_RXB81': '$2', # Receive Data Bit 8
+ 'UCSR1B_TXB81': '$1', # Transmit Data Bit 8
+ 'UCSR1C' : '$ca', # USART Control and Status Regis
+ 'UCSR1C_UMSEL1': '$c0', # USART Mode Select
+ 'UCSR1C_UPM1': '$30', # Parity Mode Bits
+ 'UCSR1C_USBS1': '$8', # Stop Bit Select
+ 'UCSR1C_UCSZ1': '$6', # Character Size
+ 'UCSR1C_UCPOL1': '$1', # Clock Polarity
+ 'UCSR1D' : '$cb', # USART Control and Status Regis
+ 'UCSR1D_CTSEN': '$2', # CTS Enable
+ 'UCSR1D_RTSEN': '$1', # RTS Enable
+ 'UBRR1' : '$cc', # USART Baud Rate Register Byte
+
+# Module WATCHDOG
+ 'WDTCSR' : '$60', # Watchdog Timer Control Registe
+ 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
+ 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
+ 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
+ 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
+ 'WDTCSR_WDE': '$8', # Watch Dog Enable
+ 'WDTCKD' : '$62', # Watchdog Timer Clock Divider
+ 'WDTCKD_WDEWIF': '$8', # Watchdog Early Warning Interru
+ 'WDTCKD_WDEWIE': '$4', # Watchdog Early Warning Interru
+ 'WDTCKD_WCLKD': '$3', # Watchdog Timer Clock Dividers
+
+# Module ANALOG_COMPARATOR
+ 'ACSR' : '$50', # Analog Comparator Control And
+ 'ACSR_ACD': '$80', # Analog Comparator Disable
+ 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
+ 'ACSR_ACO': '$20', # Analog Compare Output
+ 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
+ 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
+ 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
+ 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
+ 'DIDR1' : '$7f', #
+ 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
+ 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
+
+# Module PORTC
+ 'PORTC' : '$28', # Port C Data Register
+ 'PORTC_PORTC': '$f0', # Port C Data Register bits
+ 'PORTC_PORTC': '$7', # Port C Data Register bits
+ 'DDRC' : '$27', # Port C Data Direction Register
+ 'DDRC_DDC': '$f0', # Port C Data Direction Register
+ 'DDRC_DDC': '$7', # Port C Data Direction Register
+ 'PINC' : '$26', # Port C Input Pins
+ 'PINC_PINC': '$f0', # Port C Input Pins bits
+ 'PINC_PINC': '$7', # Port C Input Pins bits
+
+ '__amforth_dummy':'0'
+}
diff --git a/amforth-6.5/avr8/devices/at90usb82/words/no-jtag.asm b/amforth-6.5/avr8/devices/at90usb82/words/no-jtag.asm
new file mode 100644
index 0000000..352a4bb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90usb82/words/no-jtag.asm
@@ -0,0 +1,14 @@
+; ( -- )
+; ( -- )
+; MCU
+; disable jtag at runtime
+VE_NOJTAG:
+ .dw $FF05
+ .db "-jtag",0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOJTAG
+XT_NOJTAG:
+ .dw PFA_NOJTAG
+PFA_NOJTAG:
+
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/at90usb82/words/no-wdt.asm b/amforth-6.5/avr8/devices/at90usb82/words/no-wdt.asm
new file mode 100644
index 0000000..ff6ddd1
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90usb82/words/no-wdt.asm
@@ -0,0 +1,34 @@
+; ( -- )
+; MCU
+; disable watch dog timer at runtime
+VE_NOWDT:
+ .dw $ff04
+ .db "-wdt"
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOWDT
+XT_NOWDT:
+ .dw PFA_NOWDT
+PFA_NOWDT:
+
+ in temp1,SREG
+ push temp1
+ ; Turn always off global interrupt.
+ cli
+ ; Reset Watchdog Timer
+ wdr
+ ; Clear WDRF in MCUSR
+ in temp1, MCUSR
+ andi temp1, (0xff & (0<<WDRF))
+ out MCUSR, temp1
+ ; Write logical one to WDCE and WDE
+ ; Keep old prescaler setting to prevent unintentional time-out
+ in_ temp1, WDTCSR
+ ori temp1, (1<<WDCE) | (1<<WDE)
+ out_ WDTCSR, temp1
+ ; Turn off WDT
+ ldi temp1, (0<<WDE)
+ out_ WDTCSR, temp1
+ ; restore status register
+ pop temp1
+ out SREG,temp1
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/at90usb82/words/sleep.asm b/amforth-6.5/avr8/devices/at90usb82/words/sleep.asm
new file mode 100644
index 0000000..256249c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90usb82/words/sleep.asm
@@ -0,0 +1,19 @@
+; ( mode -- )
+; MCU
+; put the controller into the specified sleep mode
+VE_SLEEP:
+ .dw $ff05
+ .db "sleep", 0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_SLEEP
+XT_SLEEP:
+ .dw PFA_SLEEP
+PFA_SLEEP:
+ andi tosl, 7 ; leave only legal mode bits
+ lsl tosl ; move to correct location (bits 3-1)
+ ori tosl, 1 ; set the SE bit
+ out_ SMCR, tosl ; set the sleep config
+ sleep ; nighty-night
+ out_ SMCR, zerol ; 0 protects against accidental sleeps
+ loadtos ; pop argument from stack
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega103/atmega103.frt b/amforth-6.5/avr8/devices/atmega103/atmega103.frt
new file mode 100644
index 0000000..6130f93
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega103/atmega103.frt
@@ -0,0 +1,124 @@
+\ Partname: ATmega103
+\ Built using part description XML file version 236
+\ generated automatically
+
+hex
+
+\ AD_CONVERTER
+25 constant ADCH \ ADC Data Register High Byte
+24 constant ADCL \ ADC Data Register Low Byte
+26 constant ADCSR \ The ADC Control and Status register
+27 constant ADMUX \ The ADC multiplexer Selection Register
+
+\ ANALOG_COMPARATOR
+28 constant ACSR \ Analog Comparator Control And Status Register
+
+\ CPU
+55 constant MCUCR \ MCU Control Register
+54 constant MCUSR \ MCU Status Register
+5B constant RAMPZ \ RAM Page Z Select Register
+5E constant SPH \ Stack Pointer High
+5D constant SPL \ Stack Pointer Low
+5F constant SREG \ Status Register
+5C constant XDIV \ XTAL Divide Control Register
+
+\ EEPROM
+3F constant EEARH \ EEPROM Read/Write Access High Byte
+3E constant EEARL \ EEPROM Read/Write Access Low Byte
+3C constant EECR \ EEPROM Control Register
+3D constant EEDR \ EEPROM Data Register
+
+\ EXTERNAL_INTERRUPT
+5A constant EICR \ External Interrupt Control Register B
+58 constant EIFR \ External Interrupt Flag Register
+59 constant EIMSK \ External Interrupt Mask Register
+
+\ PORTA
+3A constant DDRA \ Port A Data Direction Register
+39 constant PINA \ Port A Input Pins
+3B constant PORTA \ Port A Data Register
+
+\ PORTB
+37 constant DDRB \ Port B Data Direction Register
+36 constant PINB \ Port B Input Pins
+38 constant PORTB \ Port B Data Register
+
+\ PORTC
+35 constant PORTC \ Port C Data Register
+
+\ PORTD
+31 constant DDRD \ Port D Data Direction Register
+30 constant PIND \ Port D Input Pins
+32 constant PORTD \ Port D Data Register
+
+\ PORTE
+22 constant DDRE \ Data Direction Register, Port E
+21 constant PINE \ Input Pins, Port E
+23 constant PORTE \ Data Register, Port E
+
+\ PORTF
+20 constant PINF \ Input Pins, Port F
+
+\ SPI
+2D constant SPCR \ SPI Control Register
+2F constant SPDR \ SPI Data Register
+2E constant SPSR \ SPI Status Register
+
+\ TIMER_COUNTER_0
+50 constant ASSR \ Asynchronus Status Register
+51 constant OCR0 \ Output Compare Register
+53 constant TCCR0 \ Timer/Counter Control Register
+52 constant TCNT0 \ Timer/Counter Register
+56 constant TIFR \ Timer/Counter Interrupt Flag register
+57 constant TIMSK \ Timer/Counter Interrupt Mask Register
+
+\ TIMER_COUNTER_1
+47 constant ICR1H \ Timer/Counter1 Input Capture Register High Byte
+46 constant ICR1L \ Timer/Counter1 Input Capture Register Low Byte
+4B constant OCR1AH \ Timer/Counter1 Output Compare Register High Byte
+4A constant OCR1AL \ Timer/Counter1 Output Compare Register Low Byte
+49 constant OCR1BH \ Timer/Counter1 Output Compare Register High Byte
+48 constant OCR1BL \ Timer/Counter1 Output Compare Register Low Byte
+4F constant TCCR1A \ Timer/Counter1 Control Register A
+4E constant TCCR1B \ Timer/Counter1 Control Register B
+4D constant TCNT1H \ Timer/Counter1 High Byte
+4C constant TCNT1L \ Timer/Counter1 Low Byte
+
+\ TIMER_COUNTER_2
+43 constant OCR2 \ Timer/Counter2 Output Compare Register
+45 constant TCCR2 \ Timer/Counter2 Control Register
+44 constant TCNT2 \ Timer/Counter2
+
+\ UART
+29 constant UBRR \ UART BAUD Rate Register
+2A constant UCR \ UART Control Register
+2C constant UDR \ UART I/O Data Register
+2B constant USR \ UART Status Register
+
+\ WATCHDOG
+41 constant WDTCR \ Watchdog Timer Control Register
+
+\ Interrupts
+002 constant INT0Addr \ External Interrupt 0
+004 constant INT1Addr \ External Interrupt 1
+006 constant INT2Addr \ External Interrupt 2
+008 constant INT3Addr \ External Interrupt 3
+00A constant INT4Addr \ External Interrupt 4
+00C constant INT5Addr \ External Interrupt 5
+00E constant INT6Addr \ External Interrupt 6
+010 constant INT7Addr \ External Interrupt 7
+012 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
+014 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
+016 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+018 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
+01A constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
+01C constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+01E constant TIMER0_COMPAddr \ Timer/Counter0 Compare Match
+020 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
+022 constant SPISTCAddr \ SPI Serial Transfer Complete
+024 constant UARTRXAddr \ UART, Rx Complete
+026 constant UARTUDREAddr \ UART Data Register Empty
+028 constant UARTTXAddr \ UART, Tx Complete
+02A constant ADCAddr \ ADC Conversion Complete
+02C constant EE_READYAddr \ EEPROM Ready
+02E constant ANALOG_COMPAddr \ Analog Comparator
diff --git a/amforth-6.5/avr8/devices/atmega103/device.asm b/amforth-6.5/avr8/devices/atmega103/device.asm
new file mode 100644
index 0000000..efcb78f
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega103/device.asm
@@ -0,0 +1,126 @@
+; Partname: ATmega103
+; Built using part description XML file version 236
+; generated automatically, do not edit
+
+.nolist
+ .include "m103def.inc"
+.list
+
+.equ ramstart = $60
+.equ CELLSIZE = 2
+.macro readflashcell
+ clr temp7
+ lsl zl
+ rol zh
+ rol temp7
+ out_ RAMPZ, temp7
+ elpm @0, Z+
+ elpm @1, Z+
+.endmacro
+.macro writeflashcell
+ clr temp7
+ lsl zl
+ rol zh
+ rol temp7
+ out_ RAMPZ, temp7
+.endmacro
+
+; the following definitions are shortcuts for the respective forth source segments if set to 1
+.set WANT_AD_CONVERTER = 0
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_CPU = 0
+.set WANT_EEPROM = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_PORTA = 0
+.set WANT_PORTB = 0
+.set WANT_PORTC = 0
+.set WANT_PORTD = 0
+.set WANT_PORTE = 0
+.set WANT_PORTF = 0
+.set WANT_SPI = 0
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_TIMER_COUNTER_2 = 0
+.set WANT_UART = 0
+.set WANT_WATCHDOG = 0
+
+
+.ifndef SPMEN
+ .equ SPMEN = SELFPRGEN
+.endif
+
+.ifndef SPMCSR
+ .equ SPMCSR = SPMCR
+.endif
+
+.ifndef EEPE
+ .equ EEPE = EEWE
+.endif
+
+.ifndef EEMPE
+ .equ EEMPE = EEMWE
+.endif
+.equ intvecsize = 2 ; please verify; flash size: 131072 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.equ INTVECTORS = 24
+.org $002
+ rcall isr ; External Interrupt 0
+.org $004
+ rcall isr ; External Interrupt 1
+.org $006
+ rcall isr ; External Interrupt 2
+.org $008
+ rcall isr ; External Interrupt 3
+.org $00A
+ rcall isr ; External Interrupt 4
+.org $00C
+ rcall isr ; External Interrupt 5
+.org $00E
+ rcall isr ; External Interrupt 6
+.org $010
+ rcall isr ; External Interrupt 7
+.org $012
+ rcall isr ; Timer/Counter2 Compare Match
+.org $014
+ rcall isr ; Timer/Counter2 Overflow
+.org $016
+ rcall isr ; Timer/Counter1 Capture Event
+.org $018
+ rcall isr ; Timer/Counter1 Compare Match A
+.org $01A
+ rcall isr ; Timer/Counter1 Compare Match B
+.org $01C
+ rcall isr ; Timer/Counter1 Overflow
+.org $01E
+ rcall isr ; Timer/Counter0 Compare Match
+.org $020
+ rcall isr ; Timer/Counter0 Overflow
+.org $022
+ rcall isr ; SPI Serial Transfer Complete
+.org $024
+ rcall isr ; UART, Rx Complete
+.org $026
+ rcall isr ; UART Data Register Empty
+.org $028
+ rcall isr ; UART, Tx Complete
+.org $02A
+ rcall isr ; ADC Conversion Complete
+.org $02C
+ rcall isr ; EEPROM Ready
+.org $02E
+ rcall isr ; Analog Comparator
+.nooverlap
+mcu_info:
+mcu_ramsize:
+ .dw 4000
+mcu_eepromsize:
+ .dw 4096
+mcu_maxdp:
+ .dw 0 ; minimum of (from XML) and 0xffff
+mcu_numints:
+ .dw 24
+mcu_name:
+ .dw 9
+ .db "ATmega103",0
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega103/device.inc b/amforth-6.5/avr8/devices/atmega103/device.inc
new file mode 100644
index 0000000..f52a85e
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega103/device.inc
@@ -0,0 +1,825 @@
+; Partname: ATmega103
+; Built using part description XML file version 236
+; generated automatically, no not edit
+
+; ********
+.if WANT_AD_CONVERTER == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register High Byte
+VE_ADCH:
+ .dw $ff04
+ .db "ADCH"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCH
+XT_ADCH:
+ .dw PFA_DOVARIABLE
+PFA_ADCH:
+ .dw $25
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register Low Byte
+VE_ADCL:
+ .dw $ff04
+ .db "ADCL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCL
+XT_ADCL:
+ .dw PFA_DOVARIABLE
+PFA_ADCL:
+ .dw $24
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register
+VE_ADCSR:
+ .dw $ff05
+ .db "ADCSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSR
+XT_ADCSR:
+ .dw PFA_DOVARIABLE
+PFA_ADCSR:
+ .dw $26
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC multiplexer Selection Register
+VE_ADMUX:
+ .dw $ff05
+ .db "ADMUX",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADMUX
+XT_ADMUX:
+ .dw PFA_DOVARIABLE
+PFA_ADMUX:
+ .dw $27
+
+.endif
+
+; ********
+.if WANT_ANALOG_COMPARATOR == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Control And Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw $28
+
+.endif
+
+; ********
+.if WANT_CPU == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw $55
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Status Register
+VE_MCUSR:
+ .dw $ff05
+ .db "MCUSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUSR
+XT_MCUSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUSR:
+ .dw $54
+; ( -- addr ) System Constant
+; R( -- )
+; RAM Page Z Select Register
+VE_RAMPZ:
+ .dw $ff05
+ .db "RAMPZ",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_RAMPZ
+XT_RAMPZ:
+ .dw PFA_DOVARIABLE
+PFA_RAMPZ:
+ .dw $5B
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer High
+VE_SPH:
+ .dw $ff03
+ .db "SPH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPH
+XT_SPH:
+ .dw PFA_DOVARIABLE
+PFA_SPH:
+ .dw $5E
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer Low
+VE_SPL:
+ .dw $ff03
+ .db "SPL",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPL
+XT_SPL:
+ .dw PFA_DOVARIABLE
+PFA_SPL:
+ .dw $5D
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw $5F
+; ( -- addr ) System Constant
+; R( -- )
+; XTAL Divide Control Register
+VE_XDIV:
+ .dw $ff04
+ .db "XDIV"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_XDIV
+XT_XDIV:
+ .dw PFA_DOVARIABLE
+PFA_XDIV:
+ .dw $5C
+
+.endif
+
+; ********
+.if WANT_EEPROM == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Read/Write Access High Byte
+VE_EEARH:
+ .dw $ff05
+ .db "EEARH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEARH
+XT_EEARH:
+ .dw PFA_DOVARIABLE
+PFA_EEARH:
+ .dw $3F
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Read/Write Access Low Byte
+VE_EEARL:
+ .dw $ff05
+ .db "EEARL",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEARL
+XT_EEARL:
+ .dw PFA_DOVARIABLE
+PFA_EEARL:
+ .dw $3E
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw $3C
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw $3D
+
+.endif
+
+; ********
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register B
+VE_EICR:
+ .dw $ff04
+ .db "EICR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICR
+XT_EICR:
+ .dw PFA_DOVARIABLE
+PFA_EICR:
+ .dw $5A
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Flag Register
+VE_EIFR:
+ .dw $ff04
+ .db "EIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIFR
+XT_EIFR:
+ .dw PFA_DOVARIABLE
+PFA_EIFR:
+ .dw $58
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Mask Register
+VE_EIMSK:
+ .dw $ff05
+ .db "EIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIMSK
+XT_EIMSK:
+ .dw PFA_DOVARIABLE
+PFA_EIMSK:
+ .dw $59
+
+.endif
+
+; ********
+.if WANT_PORTA == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Direction Register
+VE_DDRA:
+ .dw $ff04
+ .db "DDRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRA
+XT_DDRA:
+ .dw PFA_DOVARIABLE
+PFA_DDRA:
+ .dw $3A
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Input Pins
+VE_PINA:
+ .dw $ff04
+ .db "PINA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINA
+XT_PINA:
+ .dw PFA_DOVARIABLE
+PFA_PINA:
+ .dw $39
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Register
+VE_PORTA:
+ .dw $ff05
+ .db "PORTA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTA
+XT_PORTA:
+ .dw PFA_DOVARIABLE
+PFA_PORTA:
+ .dw $3B
+
+.endif
+
+; ********
+.if WANT_PORTB == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw $37
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw $36
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw $38
+
+.endif
+
+; ********
+.if WANT_PORTC == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Register
+VE_PORTC:
+ .dw $ff05
+ .db "PORTC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTC
+XT_PORTC:
+ .dw PFA_DOVARIABLE
+PFA_PORTC:
+ .dw $35
+
+.endif
+
+; ********
+.if WANT_PORTD == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw $31
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw $30
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw $32
+
+.endif
+
+; ********
+.if WANT_PORTE == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port E
+VE_DDRE:
+ .dw $ff04
+ .db "DDRE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRE
+XT_DDRE:
+ .dw PFA_DOVARIABLE
+PFA_DDRE:
+ .dw $22
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port E
+VE_PINE:
+ .dw $ff04
+ .db "PINE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINE
+XT_PINE:
+ .dw PFA_DOVARIABLE
+PFA_PINE:
+ .dw $21
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port E
+VE_PORTE:
+ .dw $ff05
+ .db "PORTE",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTE
+XT_PORTE:
+ .dw PFA_DOVARIABLE
+PFA_PORTE:
+ .dw $23
+
+.endif
+
+; ********
+.if WANT_PORTF == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port F
+VE_PINF:
+ .dw $ff04
+ .db "PINF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINF
+XT_PINF:
+ .dw PFA_DOVARIABLE
+PFA_PINF:
+ .dw $20
+
+.endif
+
+; ********
+.if WANT_SPI == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR:
+ .dw $ff04
+ .db "SPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR
+XT_SPCR:
+ .dw PFA_DOVARIABLE
+PFA_SPCR:
+ .dw $2D
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR:
+ .dw $ff04
+ .db "SPDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR
+XT_SPDR:
+ .dw PFA_DOVARIABLE
+PFA_SPDR:
+ .dw $2F
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR:
+ .dw $ff04
+ .db "SPSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR
+XT_SPSR:
+ .dw PFA_DOVARIABLE
+PFA_SPSR:
+ .dw $2E
+
+.endif
+
+; ********
+.if WANT_TIMER_COUNTER_0 == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Asynchronus Status Register
+VE_ASSR:
+ .dw $ff04
+ .db "ASSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ASSR
+XT_ASSR:
+ .dw PFA_DOVARIABLE
+PFA_ASSR:
+ .dw $50
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare Register
+VE_OCR0:
+ .dw $ff04
+ .db "OCR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0
+XT_OCR0:
+ .dw PFA_DOVARIABLE
+PFA_OCR0:
+ .dw $51
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register
+VE_TCCR0:
+ .dw $ff05
+ .db "TCCR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0
+XT_TCCR0:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0:
+ .dw $53
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Register
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw $52
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Flag register
+VE_TIFR:
+ .dw $ff04
+ .db "TIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR
+XT_TIFR:
+ .dw PFA_DOVARIABLE
+PFA_TIFR:
+ .dw $56
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Mask Register
+VE_TIMSK:
+ .dw $ff05
+ .db "TIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK
+XT_TIMSK:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK:
+ .dw $57
+
+.endif
+
+; ********
+.if WANT_TIMER_COUNTER_1 == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register High Byte
+VE_ICR1H:
+ .dw $ff05
+ .db "ICR1H",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1H
+XT_ICR1H:
+ .dw PFA_DOVARIABLE
+PFA_ICR1H:
+ .dw $47
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Low Byte
+VE_ICR1L:
+ .dw $ff05
+ .db "ICR1L",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1L
+XT_ICR1L:
+ .dw PFA_DOVARIABLE
+PFA_ICR1L:
+ .dw $46
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register High Byte
+VE_OCR1AH:
+ .dw $ff06
+ .db "OCR1AH"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1AH
+XT_OCR1AH:
+ .dw PFA_DOVARIABLE
+PFA_OCR1AH:
+ .dw $4B
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register Low Byte
+VE_OCR1AL:
+ .dw $ff06
+ .db "OCR1AL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1AL
+XT_OCR1AL:
+ .dw PFA_DOVARIABLE
+PFA_OCR1AL:
+ .dw $4A
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register High Byte
+VE_OCR1BH:
+ .dw $ff06
+ .db "OCR1BH"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1BH
+XT_OCR1BH:
+ .dw PFA_DOVARIABLE
+PFA_OCR1BH:
+ .dw $49
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register Low Byte
+VE_OCR1BL:
+ .dw $ff06
+ .db "OCR1BL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1BL
+XT_OCR1BL:
+ .dw PFA_DOVARIABLE
+PFA_OCR1BL:
+ .dw $48
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw $4F
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw $4E
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 High Byte
+VE_TCNT1H:
+ .dw $ff06
+ .db "TCNT1H"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1H
+XT_TCNT1H:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1H:
+ .dw $4D
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Low Byte
+VE_TCNT1L:
+ .dw $ff06
+ .db "TCNT1L"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1L
+XT_TCNT1L:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1L:
+ .dw $4C
+
+.endif
+
+; ********
+.if WANT_TIMER_COUNTER_2 == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register
+VE_OCR2:
+ .dw $ff04
+ .db "OCR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2
+XT_OCR2:
+ .dw PFA_DOVARIABLE
+PFA_OCR2:
+ .dw $43
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register
+VE_TCCR2:
+ .dw $ff05
+ .db "TCCR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2
+XT_TCCR2:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2:
+ .dw $45
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2
+VE_TCNT2:
+ .dw $ff05
+ .db "TCNT2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT2
+XT_TCNT2:
+ .dw PFA_DOVARIABLE
+PFA_TCNT2:
+ .dw $44
+
+.endif
+
+; ********
+.if WANT_UART == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; UART BAUD Rate Register
+VE_UBRR:
+ .dw $ff04
+ .db "UBRR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR
+XT_UBRR:
+ .dw PFA_DOVARIABLE
+PFA_UBRR:
+ .dw $29
+; ( -- addr ) System Constant
+; R( -- )
+; UART Control Register
+VE_UCR:
+ .dw $ff03
+ .db "UCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCR
+XT_UCR:
+ .dw PFA_DOVARIABLE
+PFA_UCR:
+ .dw $2A
+; ( -- addr ) System Constant
+; R( -- )
+; UART I/O Data Register
+VE_UDR:
+ .dw $ff03
+ .db "UDR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR
+XT_UDR:
+ .dw PFA_DOVARIABLE
+PFA_UDR:
+ .dw $2C
+; ( -- addr ) System Constant
+; R( -- )
+; UART Status Register
+VE_USR:
+ .dw $ff03
+ .db "USR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USR
+XT_USR:
+ .dw PFA_DOVARIABLE
+PFA_USR:
+ .dw $2B
+
+.endif
+
+; ********
+.if WANT_WATCHDOG == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCR:
+ .dw $ff05
+ .db "WDTCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCR
+XT_WDTCR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCR:
+ .dw $41
+
+.endif
diff --git a/amforth-6.5/avr8/devices/atmega103/device.py b/amforth-6.5/avr8/devices/atmega103/device.py
new file mode 100644
index 0000000..fcd3341
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega103/device.py
@@ -0,0 +1,88 @@
+# Partname: ATmega103
+# Built using part description XML file version 236
+# generated automatically, do not edit
+MCUREGS = {
+ 'ADCH': '$25',
+ 'ADCL': '$24',
+ 'ADCSR': '$26',
+ 'ADMUX': '$27',
+ 'ACSR': '$28',
+ 'MCUCR': '$55',
+ 'MCUSR': '$54',
+ 'RAMPZ': '$5B',
+ 'SPH': '$5E',
+ 'SPL': '$5D',
+ 'SREG': '$5F',
+ 'XDIV': '$5C',
+ 'EEARH': '$3F',
+ 'EEARL': '$3E',
+ 'EECR': '$3C',
+ 'EEDR': '$3D',
+ 'EICR': '$5A',
+ 'EIFR': '$58',
+ 'EIMSK': '$59',
+ 'DDRA': '$3A',
+ 'PINA': '$39',
+ 'PORTA': '$3B',
+ 'DDRB': '$37',
+ 'PINB': '$36',
+ 'PORTB': '$38',
+ 'PORTC': '$35',
+ 'DDRD': '$31',
+ 'PIND': '$30',
+ 'PORTD': '$32',
+ 'DDRE': '$22',
+ 'PINE': '$21',
+ 'PORTE': '$23',
+ 'PINF': '$20',
+ 'SPCR': '$2D',
+ 'SPDR': '$2F',
+ 'SPSR': '$2E',
+ 'ASSR': '$50',
+ 'OCR0': '$51',
+ 'TCCR0': '$53',
+ 'TCNT0': '$52',
+ 'TIFR': '$56',
+ 'TIMSK': '$57',
+ 'ICR1H': '$47',
+ 'ICR1L': '$46',
+ 'OCR1AH': '$4B',
+ 'OCR1AL': '$4A',
+ 'OCR1BH': '$49',
+ 'OCR1BL': '$48',
+ 'TCCR1A': '$4F',
+ 'TCCR1B': '$4E',
+ 'TCNT1H': '$4D',
+ 'TCNT1L': '$4C',
+ 'OCR2': '$43',
+ 'TCCR2': '$45',
+ 'TCNT2': '$44',
+ 'UBRR': '$29',
+ 'UCR': '$2A',
+ 'UDR': '$2C',
+ 'USR': '$2B',
+ 'WDTCR': '$41',
+ 'INT0Addr': '$002',
+ 'INT1Addr': '$004',
+ 'INT2Addr': '$006',
+ 'INT3Addr': '$008',
+ 'INT4Addr': '$00A',
+ 'INT5Addr': '$00C',
+ 'INT6Addr': '$00E',
+ 'INT7Addr': '$010',
+ 'TIMER2_COMPAddr': '$012',
+ 'TIMER2_OVFAddr': '$014',
+ 'TIMER1_CAPTAddr': '$016',
+ 'TIMER1_COMPAAddr': '$018',
+ 'TIMER1_COMPBAddr': '$01A',
+ 'TIMER1_OVFAddr': '$01C',
+ 'TIMER0_COMPAddr': '$01E',
+ 'TIMER0_OVFAddr': '$020',
+ 'SPISTCAddr': '$022',
+ 'UARTRXAddr': '$024',
+ 'UARTUDREAddr': '$026',
+ 'UARTTXAddr': '$028',
+ 'ADCAddr': '$02A',
+ 'EE_READYAddr': '$02C',
+ 'ANALOG_COMPAddr': '$02E'
+} \ No newline at end of file
diff --git a/amforth-6.5/avr8/devices/atmega128/atmega128.frt b/amforth-6.5/avr8/devices/atmega128/atmega128.frt
new file mode 100644
index 0000000..7441912
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega128/atmega128.frt
@@ -0,0 +1,329 @@
+\ Partname: ATmega128
+\ generated automatically
+
+\ ANALOG_COMPARATOR
+&64 constant SFIOR \ Special Function IO Register
+ $08 constant SFIOR_ACME \ Analog Comparator Multiplexer Enable
+&40 constant ACSR \ Analog Comparator Control And Status Register
+ $80 constant ACSR_ACD \ Analog Comparator Disable
+ $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
+ $20 constant ACSR_ACO \ Analog Compare Output
+ $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
+ $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
+ $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
+ $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
+\ SPI
+&47 constant SPDR \ SPI Data Register
+&46 constant SPSR \ SPI Status Register
+ $80 constant SPSR_SPIF \ SPI Interrupt Flag
+ $40 constant SPSR_WCOL \ Write Collision Flag
+ $01 constant SPSR_SPI2X \ Double SPI Speed Bit
+&45 constant SPCR \ SPI Control Register
+ $80 constant SPCR_SPIE \ SPI Interrupt Enable
+ $40 constant SPCR_SPE \ SPI Enable
+ $20 constant SPCR_DORD \ Data Order
+ $10 constant SPCR_MSTR \ Master/Slave Select
+ $08 constant SPCR_CPOL \ Clock polarity
+ $04 constant SPCR_CPHA \ Clock Phase
+ $03 constant SPCR_SPR \ SPI Clock Rate Selects
+\ TWI
+&112 constant TWBR \ TWI Bit Rate register
+&116 constant TWCR \ TWI Control Register
+ $80 constant TWCR_TWINT \ TWI Interrupt Flag
+ $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
+ $20 constant TWCR_TWSTA \ TWI Start Condition Bit
+ $10 constant TWCR_TWSTO \ TWI Stop Condition Bit
+ $08 constant TWCR_TWWC \ TWI Write Collition Flag
+ $04 constant TWCR_TWEN \ TWI Enable Bit
+ $01 constant TWCR_TWIE \ TWI Interrupt Enable
+&113 constant TWSR \ TWI Status Register
+ $F8 constant TWSR_TWS \ TWI Status
+ $03 constant TWSR_TWPS \ TWI Prescaler
+&115 constant TWDR \ TWI Data register
+&114 constant TWAR \ TWI (Slave) Address register
+ $FE constant TWAR_TWA \ TWI (Slave) Address register Bits
+ $01 constant TWAR_TWGCE \ TWI General Call Recognition Enable Bit
+\ USART0
+&44 constant UDR0 \ USART I/O Data Register
+&43 constant UCSR0A \ USART Control and Status Register A
+ $80 constant UCSR0A_RXC0 \ USART Receive Complete
+ $40 constant UCSR0A_TXC0 \ USART Transmitt Complete
+ $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
+ $10 constant UCSR0A_FE0 \ Framing Error
+ $08 constant UCSR0A_DOR0 \ Data overRun
+ $04 constant UCSR0A_UPE0 \ Parity Error
+ $02 constant UCSR0A_U2X0 \ Double the USART transmission speed
+ $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
+&42 constant UCSR0B \ USART Control and Status Register B
+ $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
+ $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
+ $20 constant UCSR0B_UDRIE0 \ USART Data register Empty Interrupt Enable
+ $10 constant UCSR0B_RXEN0 \ Receiver Enable
+ $08 constant UCSR0B_TXEN0 \ Transmitter Enable
+ $04 constant UCSR0B_UCSZ02 \ Character Size
+ $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
+ $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
+&149 constant UCSR0C \ USART Control and Status Register C
+ $40 constant UCSR0C_UMSEL0 \ USART Mode Select
+ $30 constant UCSR0C_UPM0 \ Parity Mode Bits
+ $08 constant UCSR0C_USBS0 \ Stop Bit Select
+ $06 constant UCSR0C_UCSZ0 \ Character Size
+ $01 constant UCSR0C_UCPOL0 \ Clock Polarity
+&144 constant UBRR0H \ USART Baud Rate Register Hight Byte
+&41 constant UBRR0L \ USART Baud Rate Register Low Byte
+\ USART1
+&156 constant UDR1 \ USART I/O Data Register
+&155 constant UCSR1A \ USART Control and Status Register A
+ $80 constant UCSR1A_RXC1 \ USART Receive Complete
+ $40 constant UCSR1A_TXC1 \ USART Transmitt Complete
+ $20 constant UCSR1A_UDRE1 \ USART Data Register Empty
+ $10 constant UCSR1A_FE1 \ Framing Error
+ $08 constant UCSR1A_DOR1 \ Data overRun
+ $04 constant UCSR1A_UPE1 \ Parity Error
+ $02 constant UCSR1A_U2X1 \ Double the USART transmission speed
+ $01 constant UCSR1A_MPCM1 \ Multi-processor Communication Mode
+&154 constant UCSR1B \ USART Control and Status Register B
+ $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable
+ $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable
+ $20 constant UCSR1B_UDRIE1 \ USART Data register Empty Interrupt Enable
+ $10 constant UCSR1B_RXEN1 \ Receiver Enable
+ $08 constant UCSR1B_TXEN1 \ Transmitter Enable
+ $04 constant UCSR1B_UCSZ12 \ Character Size
+ $02 constant UCSR1B_RXB81 \ Receive Data Bit 8
+ $01 constant UCSR1B_TXB81 \ Transmit Data Bit 8
+&157 constant UCSR1C \ USART Control and Status Register C
+ $40 constant UCSR1C_UMSEL1 \ USART Mode Select
+ $30 constant UCSR1C_UPM1 \ Parity Mode Bits
+ $08 constant UCSR1C_USBS1 \ Stop Bit Select
+ $06 constant UCSR1C_UCSZ1 \ Character Size
+ $01 constant UCSR1C_UCPOL1 \ Clock Polarity
+&152 constant UBRR1H \ USART Baud Rate Register Hight Byte
+&153 constant UBRR1L \ USART Baud Rate Register Low Byte
+\ CPU
+&95 constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ $08 constant SREG_V \ Two's Complement Overflow Flag
+ $04 constant SREG_N \ Negative Flag
+ $02 constant SREG_Z \ Zero Flag
+ $01 constant SREG_C \ Carry Flag
+&93 constant SP \ Stack Pointer
+&85 constant MCUCR \ MCU Control Register
+ $80 constant MCUCR_SRE \ External SRAM Enable
+ $40 constant MCUCR_SRW10 \ External SRAM Wait State Select
+ $20 constant MCUCR_SE \ Sleep Enable
+ $18 constant MCUCR_SM \ Sleep Mode Select
+ $04 constant MCUCR_SM2 \ Sleep Mode Select
+ $02 constant MCUCR_IVSEL \ Interrupt Vector Select
+ $01 constant MCUCR_IVCE \ Interrupt Vector Change Enable
+&84 constant MCUCSR \ MCU Control And Status Register
+ $80 constant MCUCSR_JTD \ JTAG Interface Disable
+ $10 constant MCUCSR_JTRF \ JTAG Reset Flag
+ $08 constant MCUCSR_WDRF \ Watchdog Reset Flag
+ $04 constant MCUCSR_BORF \ Brown-out Reset Flag
+ $02 constant MCUCSR_EXTRF \ External Reset Flag
+ $01 constant MCUCSR_PORF \ Power-on reset flag
+&109 constant XMCRA \ External Memory Control Register A
+ $70 constant XMCRA_SRL \ Wait state page limit
+ $0C constant XMCRA_SRW0 \ Wait state select bit lower page
+ $02 constant XMCRA_SRW11 \ Wait state select bit upper page
+&108 constant XMCRB \ External Memory Control Register B
+ $80 constant XMCRB_XMBK \ External Memory Bus Keeper Enable
+ $07 constant XMCRB_XMM \ External Memory High Mask
+&111 constant OSCCAL \ Oscillator Calibration Value
+&92 constant XDIV \ XTAL Divide Control Register
+&91 constant RAMPZ \ RAM Page Z Select Register
+ $01 constant RAMPZ_RAMPZ0 \ RAM Page Z Select Register Bit 0
+\ BOOT_LOAD
+&104 constant SPMCSR \ Store Program Memory Control Register
+ $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
+ $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
+ $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
+ $04 constant SPMCSR_PGWRT \ Page Write
+ $02 constant SPMCSR_PGERS \ Page Erase
+ $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
+\ JTAG
+&66 constant OCDR \ On-Chip Debug Related Register in I/O Memory
+ $FF constant OCDR_OCDR \ On-Chip Debug Register Bits
+\ MISC
+\ EXTERNAL_INTERRUPT
+&106 constant EICRA \ External Interrupt Control Register A
+ $C0 constant EICRA_ISC3 \ External Interrupt Sense Control Bit
+ $30 constant EICRA_ISC2 \ External Interrupt Sense Control Bit
+ $0C constant EICRA_ISC1 \ External Interrupt Sense Control Bit
+ $03 constant EICRA_ISC0 \ External Interrupt Sense Control Bit
+&90 constant EICRB \ External Interrupt Control Register B
+ $C0 constant EICRB_ISC7 \ External Interrupt 7-4 Sense Control Bit
+ $30 constant EICRB_ISC6 \ External Interrupt 7-4 Sense Control Bit
+ $0C constant EICRB_ISC5 \ External Interrupt 7-4 Sense Control Bit
+ $03 constant EICRB_ISC4 \ External Interrupt 7-4 Sense Control Bit
+&89 constant EIMSK \ External Interrupt Mask Register
+ $FF constant EIMSK_INT \ External Interrupt Request 7 Enable
+&88 constant EIFR \ External Interrupt Flag Register
+ $FF constant EIFR_INTF \ External Interrupt Flags
+\ EEPROM
+&62 constant EEAR \ EEPROM Read/Write Access Bytes
+&61 constant EEDR \ EEPROM Data Register
+&60 constant EECR \ EEPROM Control Register
+ $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
+ $04 constant EECR_EEMWE \ EEPROM Master Write Enable
+ $02 constant EECR_EEWE \ EEPROM Write Enable
+ $01 constant EECR_EERE \ EEPROM Read Enable
+\ PORTA
+&59 constant PORTA \ Port A Data Register
+&58 constant DDRA \ Port A Data Direction Register
+&57 constant PINA \ Port A Input Pins
+\ PORTB
+&56 constant PORTB \ Port B Data Register
+&55 constant DDRB \ Port B Data Direction Register
+&54 constant PINB \ Port B Input Pins
+\ PORTC
+&53 constant PORTC \ Port C Data Register
+&52 constant DDRC \ Port C Data Direction Register
+&51 constant PINC \ Port C Input Pins
+\ PORTD
+&50 constant PORTD \ Port D Data Register
+&49 constant DDRD \ Port D Data Direction Register
+&48 constant PIND \ Port D Input Pins
+\ PORTE
+&35 constant PORTE \ Data Register, Port E
+&34 constant DDRE \ Data Direction Register, Port E
+&33 constant PINE \ Input Pins, Port E
+\ PORTF
+&98 constant PORTF \ Data Register, Port F
+&97 constant DDRF \ Data Direction Register, Port F
+&32 constant PINF \ Input Pins, Port F
+\ PORTG
+&101 constant PORTG \ Data Register, Port G
+&100 constant DDRG \ Data Direction Register, Port G
+&99 constant PING \ Input Pins, Port G
+\ TIMER_COUNTER_0
+&83 constant TCCR0 \ Timer/Counter Control Register
+ $80 constant TCCR0_FOC0 \ Force Output Compare
+ $40 constant TCCR0_WGM00 \ Waveform Generation Mode 0
+ $30 constant TCCR0_COM0 \ Compare Match Output Modes
+ $08 constant TCCR0_WGM01 \ Waveform Generation Mode 1
+ $07 constant TCCR0_CS0 \ Clock Selects
+&82 constant TCNT0 \ Timer/Counter Register
+&81 constant OCR0 \ Output Compare Register
+&80 constant ASSR \ Asynchronus Status Register
+ $08 constant ASSR_AS0 \ Asynchronus Timer/Counter 0
+ $04 constant ASSR_TCN0UB \ Timer/Counter0 Update Busy
+ $02 constant ASSR_OCR0UB \ Output Compare register 0 Busy
+ $01 constant ASSR_TCR0UB \ Timer/Counter Control Register 0 Update Busy
+&87 constant TIMSK \ Timer/Counter Interrupt Mask Register
+ $02 constant TIMSK_OCIE0 \ Timer/Counter0 Output Compare Match Interrupt register
+ $01 constant TIMSK_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
+&86 constant TIFR \ Timer/Counter Interrupt Flag register
+ $02 constant TIFR_OCF0 \ Output Compare Flag 0
+ $01 constant TIFR_TOV0 \ Timer/Counter0 Overflow Flag
+\ TIMER_COUNTER_1
+&125 constant ETIMSK \ Extended Timer/Counter Interrupt Mask Register
+ $01 constant ETIMSK_OCIE1C \ Timer/Counter 1, Output Compare Match C Interrupt Enable
+&124 constant ETIFR \ Extended Timer/Counter Interrupt Flag register
+ $01 constant ETIFR_OCF1C \ Timer/Counter 1, Output Compare C Match Flag
+&79 constant TCCR1A \ Timer/Counter1 Control Register A
+ $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
+ $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
+ $0C constant TCCR1A_COM1C \ Compare Output Mode 1C, bits
+ $03 constant TCCR1A_WGM1 \ Waveform Generation Mode Bits
+&78 constant TCCR1B \ Timer/Counter1 Control Register B
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
+ $07 constant TCCR1B_CS1 \ Clock Select1 bits
+&122 constant TCCR1C \ Timer/Counter1 Control Register C
+ $80 constant TCCR1C_FOC1A \ Force Output Compare for channel A
+ $40 constant TCCR1C_FOC1B \ Force Output Compare for channel B
+ $20 constant TCCR1C_FOC1C \ Force Output Compare for channel C
+&76 constant TCNT1 \ Timer/Counter1 Bytes
+&74 constant OCR1A \ Timer/Counter1 Output Compare Register Bytes
+&72 constant OCR1B \ Timer/Counter1 Output Compare Register Bytes
+&120 constant OCR1C \ Timer/Counter1 Output Compare Register Bytes
+&70 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
+\ TIMER_COUNTER_2
+&69 constant TCCR2 \ Timer/Counter Control Register
+ $80 constant TCCR2_FOC2 \ Force Output Compare
+ $40 constant TCCR2_WGM20 \ Wafeform Generation Mode
+ $30 constant TCCR2_COM2 \ Compare Match Output Mode
+ $08 constant TCCR2_WGM21 \ Waveform Generation Mode
+ $07 constant TCCR2_CS2 \ Clock Select
+&68 constant TCNT2 \ Timer/Counter Register
+&67 constant OCR2 \ Output Compare Register
+\ TIMER_COUNTER_3
+&139 constant TCCR3A \ Timer/Counter3 Control Register A
+ $C0 constant TCCR3A_COM3A \ Compare Output Mode 3A, bits
+ $30 constant TCCR3A_COM3B \ Compare Output Mode 3B, bits
+ $0C constant TCCR3A_COM3C \ Compare Output Mode 3C, bits
+ $03 constant TCCR3A_WGM3 \ Waveform Generation Mode Bits
+&138 constant TCCR3B \ Timer/Counter3 Control Register B
+ $80 constant TCCR3B_ICNC3 \ Input Capture 3 Noise Canceler
+ $40 constant TCCR3B_ICES3 \ Input Capture 3 Edge Select
+ $18 constant TCCR3B_WGM3 \ Waveform Generation Mode
+ $07 constant TCCR3B_CS3 \ Clock Select3 bits
+&140 constant TCCR3C \ Timer/Counter3 Control Register C
+ $80 constant TCCR3C_FOC3A \ Force Output Compare for channel A
+ $40 constant TCCR3C_FOC3B \ Force Output Compare for channel B
+ $20 constant TCCR3C_FOC3C \ Force Output Compare for channel C
+&136 constant TCNT3 \ Timer/Counter3 Bytes
+&134 constant OCR3A \ Timer/Counter3 Output Compare Register A Bytes
+&132 constant OCR3B \ Timer/Counter3 Output Compare Register B Bytes
+&130 constant OCR3C \ Timer/Counter3 Output compare Register C Bytes
+&128 constant ICR3 \ Timer/Counter3 Input Capture Register Bytes
+\ WATCHDOG
+&65 constant WDTCR \ Watchdog Timer Control Register
+ $10 constant WDTCR_WDCE \ Watchdog Change Enable
+ $08 constant WDTCR_WDE \ Watch Dog Enable
+ $07 constant WDTCR_WDP \ Watch Dog Timer Prescaler bits
+\ AD_CONVERTER
+&39 constant ADMUX \ The ADC multiplexer Selection Register
+ $C0 constant ADMUX_REFS \ Reference Selection Bits
+ $20 constant ADMUX_ADLAR \ Left Adjust Result
+ $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
+&38 constant ADCSRA \ The ADC Control and Status register
+ $80 constant ADCSRA_ADEN \ ADC Enable
+ $40 constant ADCSRA_ADSC \ ADC Start Conversion
+ $20 constant ADCSRA_ADFR \ ADC Free Running Select
+ $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
+ $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
+ $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
+&36 constant ADC \ ADC Data Register Bytes
+
+\ Interrupts
+&2 constant INT0Addr \ External Interrupt Request 0
+&4 constant INT1Addr \ External Interrupt Request 1
+&6 constant INT2Addr \ External Interrupt Request 2
+&8 constant INT3Addr \ External Interrupt Request 3
+&10 constant INT4Addr \ External Interrupt Request 4
+&12 constant INT5Addr \ External Interrupt Request 5
+&14 constant INT6Addr \ External Interrupt Request 6
+&16 constant INT7Addr \ External Interrupt Request 7
+&18 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
+&20 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
+&22 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+&24 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
+&26 constant TIMER1_COMPBAddr \ Timer/Counter Compare Match B
+&28 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+&30 constant TIMER0_COMPAddr \ Timer/Counter0 Compare Match
+&32 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
+&34 constant SPI__STCAddr \ SPI Serial Transfer Complete
+&36 constant USART0__RXAddr \ USART0, Rx Complete
+&38 constant USART0__UDREAddr \ USART0 Data Register Empty
+&40 constant USART0__TXAddr \ USART0, Tx Complete
+&42 constant ADCAddr \ ADC Conversion Complete
+&44 constant EE_READYAddr \ EEPROM Ready
+&46 constant ANALOG_COMPAddr \ Analog Comparator
+&48 constant TIMER1_COMPCAddr \ Timer/Counter1 Compare Match C
+&50 constant TIMER3_CAPTAddr \ Timer/Counter3 Capture Event
+&52 constant TIMER3_COMPAAddr \ Timer/Counter3 Compare Match A
+&54 constant TIMER3_COMPBAddr \ Timer/Counter3 Compare Match B
+&56 constant TIMER3_COMPCAddr \ Timer/Counter3 Compare Match C
+&58 constant TIMER3_OVFAddr \ Timer/Counter3 Overflow
+&60 constant USART1__RXAddr \ USART1, Rx Complete
+&62 constant USART1__UDREAddr \ USART1, Data Register Empty
+&64 constant USART1__TXAddr \ USART1, Tx Complete
+&66 constant TWIAddr \ 2-wire Serial Interface
+&68 constant SPM_READYAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/atmega128/device.asm b/amforth-6.5/avr8/devices/atmega128/device.asm
new file mode 100644
index 0000000..2466ed0
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega128/device.asm
@@ -0,0 +1,141 @@
+; Partname: ATmega128
+; generated automatically, do not edit
+
+.nolist
+ .include "m128def.inc"
+.list
+
+.equ ramstart = 256
+.equ CELLSIZE = 2
+.macro readflashcell
+ clr temp7
+ lsl zl
+ rol zh
+ rol temp7
+ out_ RAMPZ, temp7
+ elpm @0, Z+
+ elpm @1, Z+
+.endmacro
+.macro writeflashcell
+ clr temp7
+ lsl zl
+ rol zh
+ rol temp7
+ out_ RAMPZ, temp7
+.endmacro
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_SPI = 0
+.set WANT_TWI = 0
+.set WANT_USART0 = 0
+.set WANT_USART1 = 0
+.set WANT_CPU = 0
+.set WANT_BOOT_LOAD = 0
+.set WANT_JTAG = 0
+.set WANT_MISC = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_EEPROM = 0
+.set WANT_PORTA = 0
+.set WANT_PORTB = 0
+.set WANT_PORTC = 0
+.set WANT_PORTD = 0
+.set WANT_PORTE = 0
+.set WANT_PORTF = 0
+.set WANT_PORTG = 0
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_TIMER_COUNTER_2 = 0
+.set WANT_TIMER_COUNTER_3 = 0
+.set WANT_WATCHDOG = 0
+.set WANT_AD_CONVERTER = 0
+.equ intvecsize = 2 ; please verify; flash size: 131072 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.org 2
+ rcall isr ; External Interrupt Request 0
+.org 4
+ rcall isr ; External Interrupt Request 1
+.org 6
+ rcall isr ; External Interrupt Request 2
+.org 8
+ rcall isr ; External Interrupt Request 3
+.org 10
+ rcall isr ; External Interrupt Request 4
+.org 12
+ rcall isr ; External Interrupt Request 5
+.org 14
+ rcall isr ; External Interrupt Request 6
+.org 16
+ rcall isr ; External Interrupt Request 7
+.org 18
+ rcall isr ; Timer/Counter2 Compare Match
+.org 20
+ rcall isr ; Timer/Counter2 Overflow
+.org 22
+ rcall isr ; Timer/Counter1 Capture Event
+.org 24
+ rcall isr ; Timer/Counter1 Compare Match A
+.org 26
+ rcall isr ; Timer/Counter Compare Match B
+.org 28
+ rcall isr ; Timer/Counter1 Overflow
+.org 30
+ rcall isr ; Timer/Counter0 Compare Match
+.org 32
+ rcall isr ; Timer/Counter0 Overflow
+.org 34
+ rcall isr ; SPI Serial Transfer Complete
+.org 36
+ rcall isr ; USART0, Rx Complete
+.org 38
+ rcall isr ; USART0 Data Register Empty
+.org 40
+ rcall isr ; USART0, Tx Complete
+.org 42
+ rcall isr ; ADC Conversion Complete
+.org 44
+ rcall isr ; EEPROM Ready
+.org 46
+ rcall isr ; Analog Comparator
+.org 48
+ rcall isr ; Timer/Counter1 Compare Match C
+.org 50
+ rcall isr ; Timer/Counter3 Capture Event
+.org 52
+ rcall isr ; Timer/Counter3 Compare Match A
+.org 54
+ rcall isr ; Timer/Counter3 Compare Match B
+.org 56
+ rcall isr ; Timer/Counter3 Compare Match C
+.org 58
+ rcall isr ; Timer/Counter3 Overflow
+.org 60
+ rcall isr ; USART1, Rx Complete
+.org 62
+ rcall isr ; USART1, Data Register Empty
+.org 64
+ rcall isr ; USART1, Tx Complete
+.org 66
+ rcall isr ; 2-wire Serial Interface
+.org 68
+ rcall isr ; Store Program Memory Read
+.equ INTVECTORS = 35
+.nooverlap
+
+; compatability layer (maybe empty)
+.equ EEPE = EEWE
+.equ EEMPE = EEMWE
+
+; controller data area, environment query mcu-info
+mcu_info:
+mcu_ramsize:
+ .dw 4096
+mcu_eepromsize:
+ .dw 4096
+mcu_maxdp:
+ .dw 65535
+mcu_numints:
+ .dw 35
+mcu_name:
+ .dw 9
+ .db "ATmega128",0
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega128/device.inc b/amforth-6.5/avr8/devices/atmega128/device.inc
new file mode 100644
index 0000000..e6ee249
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega128/device.inc
@@ -0,0 +1,1179 @@
+; Partname: ATmega128
+; generated automatically, no not edit
+
+.if WANT_ANALOG_COMPARATOR == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Special Function IO Register
+VE_SFIOR:
+ .dw $ff05
+ .db "SFIOR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SFIOR
+XT_SFIOR:
+ .dw PFA_DOVARIABLE
+PFA_SFIOR:
+ .dw 64
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Control And Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw 40
+
+.endif
+.if WANT_SPI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR:
+ .dw $ff04
+ .db "SPDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR
+XT_SPDR:
+ .dw PFA_DOVARIABLE
+PFA_SPDR:
+ .dw 47
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR:
+ .dw $ff04
+ .db "SPSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR
+XT_SPSR:
+ .dw PFA_DOVARIABLE
+PFA_SPSR:
+ .dw 46
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR:
+ .dw $ff04
+ .db "SPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR
+XT_SPCR:
+ .dw PFA_DOVARIABLE
+PFA_SPCR:
+ .dw 45
+
+.endif
+.if WANT_TWI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Bit Rate register
+VE_TWBR:
+ .dw $ff04
+ .db "TWBR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWBR
+XT_TWBR:
+ .dw PFA_DOVARIABLE
+PFA_TWBR:
+ .dw 112
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Control Register
+VE_TWCR:
+ .dw $ff04
+ .db "TWCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWCR
+XT_TWCR:
+ .dw PFA_DOVARIABLE
+PFA_TWCR:
+ .dw 116
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Status Register
+VE_TWSR:
+ .dw $ff04
+ .db "TWSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWSR
+XT_TWSR:
+ .dw PFA_DOVARIABLE
+PFA_TWSR:
+ .dw 113
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Data register
+VE_TWDR:
+ .dw $ff04
+ .db "TWDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWDR
+XT_TWDR:
+ .dw PFA_DOVARIABLE
+PFA_TWDR:
+ .dw 115
+; ( -- addr ) System Constant
+; R( -- )
+; TWI (Slave) Address register
+VE_TWAR:
+ .dw $ff04
+ .db "TWAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWAR
+XT_TWAR:
+ .dw PFA_DOVARIABLE
+PFA_TWAR:
+ .dw 114
+
+.endif
+.if WANT_USART0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR0:
+ .dw $ff04
+ .db "UDR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR0
+XT_UDR0:
+ .dw PFA_DOVARIABLE
+PFA_UDR0:
+ .dw 44
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR0A:
+ .dw $ff06
+ .db "UCSR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0A
+XT_UCSR0A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0A:
+ .dw 43
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR0B:
+ .dw $ff06
+ .db "UCSR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0B
+XT_UCSR0B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0B:
+ .dw 42
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR0C:
+ .dw $ff06
+ .db "UCSR0C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0C
+XT_UCSR0C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0C:
+ .dw 149
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Hight Byte
+VE_UBRR0H:
+ .dw $ff06
+ .db "UBRR0H"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR0H
+XT_UBRR0H:
+ .dw PFA_DOVARIABLE
+PFA_UBRR0H:
+ .dw 144
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Low Byte
+VE_UBRR0L:
+ .dw $ff06
+ .db "UBRR0L"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR0L
+XT_UBRR0L:
+ .dw PFA_DOVARIABLE
+PFA_UBRR0L:
+ .dw 41
+
+.endif
+.if WANT_USART1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR1:
+ .dw $ff04
+ .db "UDR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR1
+XT_UDR1:
+ .dw PFA_DOVARIABLE
+PFA_UDR1:
+ .dw 156
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR1A:
+ .dw $ff06
+ .db "UCSR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1A
+XT_UCSR1A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1A:
+ .dw 155
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR1B:
+ .dw $ff06
+ .db "UCSR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1B
+XT_UCSR1B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1B:
+ .dw 154
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR1C:
+ .dw $ff06
+ .db "UCSR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1C
+XT_UCSR1C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1C:
+ .dw 157
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Hight Byte
+VE_UBRR1H:
+ .dw $ff06
+ .db "UBRR1H"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR1H
+XT_UBRR1H:
+ .dw PFA_DOVARIABLE
+PFA_UBRR1H:
+ .dw 152
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Low Byte
+VE_UBRR1L:
+ .dw $ff06
+ .db "UBRR1L"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR1L
+XT_UBRR1L:
+ .dw PFA_DOVARIABLE
+PFA_UBRR1L:
+ .dw 153
+
+.endif
+.if WANT_CPU == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw 95
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer
+VE_SP:
+ .dw $ff02
+ .db "SP"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SP
+XT_SP:
+ .dw PFA_DOVARIABLE
+PFA_SP:
+ .dw 93
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw 85
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control And Status Register
+VE_MCUCSR:
+ .dw $ff06
+ .db "MCUCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCSR
+XT_MCUCSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCSR:
+ .dw 84
+; ( -- addr ) System Constant
+; R( -- )
+; External Memory Control Register A
+VE_XMCRA:
+ .dw $ff05
+ .db "XMCRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_XMCRA
+XT_XMCRA:
+ .dw PFA_DOVARIABLE
+PFA_XMCRA:
+ .dw 109
+; ( -- addr ) System Constant
+; R( -- )
+; External Memory Control Register B
+VE_XMCRB:
+ .dw $ff05
+ .db "XMCRB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_XMCRB
+XT_XMCRB:
+ .dw PFA_DOVARIABLE
+PFA_XMCRB:
+ .dw 108
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Calibration Value
+VE_OSCCAL:
+ .dw $ff06
+ .db "OSCCAL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSCCAL
+XT_OSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_OSCCAL:
+ .dw 111
+; ( -- addr ) System Constant
+; R( -- )
+; XTAL Divide Control Register
+VE_XDIV:
+ .dw $ff04
+ .db "XDIV"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_XDIV
+XT_XDIV:
+ .dw PFA_DOVARIABLE
+PFA_XDIV:
+ .dw 92
+; ( -- addr ) System Constant
+; R( -- )
+; RAM Page Z Select Register
+VE_RAMPZ:
+ .dw $ff05
+ .db "RAMPZ",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_RAMPZ
+XT_RAMPZ:
+ .dw PFA_DOVARIABLE
+PFA_RAMPZ:
+ .dw 91
+
+.endif
+.if WANT_BOOT_LOAD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control Register
+VE_SPMCSR:
+ .dw $ff06
+ .db "SPMCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCSR
+XT_SPMCSR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCSR:
+ .dw 104
+
+.endif
+.if WANT_JTAG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; On-Chip Debug Related Register in I/O Memory
+VE_OCDR:
+ .dw $ff04
+ .db "OCDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCDR
+XT_OCDR:
+ .dw PFA_DOVARIABLE
+PFA_OCDR:
+ .dw 66
+
+.endif
+.if WANT_MISC == 1
+
+.endif
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register A
+VE_EICRA:
+ .dw $ff05
+ .db "EICRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRA
+XT_EICRA:
+ .dw PFA_DOVARIABLE
+PFA_EICRA:
+ .dw 106
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register B
+VE_EICRB:
+ .dw $ff05
+ .db "EICRB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRB
+XT_EICRB:
+ .dw PFA_DOVARIABLE
+PFA_EICRB:
+ .dw 90
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Mask Register
+VE_EIMSK:
+ .dw $ff05
+ .db "EIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIMSK
+XT_EIMSK:
+ .dw PFA_DOVARIABLE
+PFA_EIMSK:
+ .dw 89
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Flag Register
+VE_EIFR:
+ .dw $ff04
+ .db "EIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIFR
+XT_EIFR:
+ .dw PFA_DOVARIABLE
+PFA_EIFR:
+ .dw 88
+
+.endif
+.if WANT_EEPROM == 1
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Read/Write Access Bytes
+VE_EEAR:
+ .dw $ff04
+ .db "EEAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEAR
+XT_EEAR:
+ .dw PFA_DOVARIABLE
+PFA_EEAR:
+ .dw 62
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw 61
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw 60
+
+.endif
+.if WANT_PORTA == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Register
+VE_PORTA:
+ .dw $ff05
+ .db "PORTA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTA
+XT_PORTA:
+ .dw PFA_DOVARIABLE
+PFA_PORTA:
+ .dw 59
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Direction Register
+VE_DDRA:
+ .dw $ff04
+ .db "DDRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRA
+XT_DDRA:
+ .dw PFA_DOVARIABLE
+PFA_DDRA:
+ .dw 58
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Input Pins
+VE_PINA:
+ .dw $ff04
+ .db "PINA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINA
+XT_PINA:
+ .dw PFA_DOVARIABLE
+PFA_PINA:
+ .dw 57
+
+.endif
+.if WANT_PORTB == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw 56
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw 55
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw 54
+
+.endif
+.if WANT_PORTC == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Register
+VE_PORTC:
+ .dw $ff05
+ .db "PORTC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTC
+XT_PORTC:
+ .dw PFA_DOVARIABLE
+PFA_PORTC:
+ .dw 53
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Direction Register
+VE_DDRC:
+ .dw $ff04
+ .db "DDRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRC
+XT_DDRC:
+ .dw PFA_DOVARIABLE
+PFA_DDRC:
+ .dw 52
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Input Pins
+VE_PINC:
+ .dw $ff04
+ .db "PINC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINC
+XT_PINC:
+ .dw PFA_DOVARIABLE
+PFA_PINC:
+ .dw 51
+
+.endif
+.if WANT_PORTD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw 50
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw 49
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw 48
+
+.endif
+.if WANT_PORTE == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port E
+VE_PORTE:
+ .dw $ff05
+ .db "PORTE",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTE
+XT_PORTE:
+ .dw PFA_DOVARIABLE
+PFA_PORTE:
+ .dw 35
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port E
+VE_DDRE:
+ .dw $ff04
+ .db "DDRE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRE
+XT_DDRE:
+ .dw PFA_DOVARIABLE
+PFA_DDRE:
+ .dw 34
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port E
+VE_PINE:
+ .dw $ff04
+ .db "PINE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINE
+XT_PINE:
+ .dw PFA_DOVARIABLE
+PFA_PINE:
+ .dw 33
+
+.endif
+.if WANT_PORTF == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port F
+VE_PORTF:
+ .dw $ff05
+ .db "PORTF",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTF
+XT_PORTF:
+ .dw PFA_DOVARIABLE
+PFA_PORTF:
+ .dw 98
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port F
+VE_DDRF:
+ .dw $ff04
+ .db "DDRF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRF
+XT_DDRF:
+ .dw PFA_DOVARIABLE
+PFA_DDRF:
+ .dw 97
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port F
+VE_PINF:
+ .dw $ff04
+ .db "PINF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINF
+XT_PINF:
+ .dw PFA_DOVARIABLE
+PFA_PINF:
+ .dw 32
+
+.endif
+.if WANT_PORTG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port G
+VE_PORTG:
+ .dw $ff05
+ .db "PORTG",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTG
+XT_PORTG:
+ .dw PFA_DOVARIABLE
+PFA_PORTG:
+ .dw 101
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port G
+VE_DDRG:
+ .dw $ff04
+ .db "DDRG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRG
+XT_DDRG:
+ .dw PFA_DOVARIABLE
+PFA_DDRG:
+ .dw 100
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port G
+VE_PING:
+ .dw $ff04
+ .db "PING"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PING
+XT_PING:
+ .dw PFA_DOVARIABLE
+PFA_PING:
+ .dw 99
+
+.endif
+.if WANT_TIMER_COUNTER_0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register
+VE_TCCR0:
+ .dw $ff05
+ .db "TCCR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0
+XT_TCCR0:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0:
+ .dw 83
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Register
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw 82
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare Register
+VE_OCR0:
+ .dw $ff04
+ .db "OCR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0
+XT_OCR0:
+ .dw PFA_DOVARIABLE
+PFA_OCR0:
+ .dw 81
+; ( -- addr ) System Constant
+; R( -- )
+; Asynchronus Status Register
+VE_ASSR:
+ .dw $ff04
+ .db "ASSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ASSR
+XT_ASSR:
+ .dw PFA_DOVARIABLE
+PFA_ASSR:
+ .dw 80
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Mask Register
+VE_TIMSK:
+ .dw $ff05
+ .db "TIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK
+XT_TIMSK:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK:
+ .dw 87
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Flag register
+VE_TIFR:
+ .dw $ff04
+ .db "TIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR
+XT_TIFR:
+ .dw PFA_DOVARIABLE
+PFA_TIFR:
+ .dw 86
+
+.endif
+.if WANT_TIMER_COUNTER_1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Extended Timer/Counter Interrupt Mask Register
+VE_ETIMSK:
+ .dw $ff06
+ .db "ETIMSK"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ETIMSK
+XT_ETIMSK:
+ .dw PFA_DOVARIABLE
+PFA_ETIMSK:
+ .dw 125
+; ( -- addr ) System Constant
+; R( -- )
+; Extended Timer/Counter Interrupt Flag register
+VE_ETIFR:
+ .dw $ff05
+ .db "ETIFR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ETIFR
+XT_ETIFR:
+ .dw PFA_DOVARIABLE
+PFA_ETIFR:
+ .dw 124
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw 79
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw 78
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register C
+VE_TCCR1C:
+ .dw $ff06
+ .db "TCCR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1C
+XT_TCCR1C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1C:
+ .dw 122
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Bytes
+VE_TCNT1:
+ .dw $ff05
+ .db "TCNT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1
+XT_TCNT1:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1:
+ .dw 76
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register Bytes
+VE_OCR1A:
+ .dw $ff05
+ .db "OCR1A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1A
+XT_OCR1A:
+ .dw PFA_DOVARIABLE
+PFA_OCR1A:
+ .dw 74
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register Bytes
+VE_OCR1B:
+ .dw $ff05
+ .db "OCR1B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1B
+XT_OCR1B:
+ .dw PFA_DOVARIABLE
+PFA_OCR1B:
+ .dw 72
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register Bytes
+VE_OCR1C:
+ .dw $ff05
+ .db "OCR1C",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1C
+XT_OCR1C:
+ .dw PFA_DOVARIABLE
+PFA_OCR1C:
+ .dw 120
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Bytes
+VE_ICR1:
+ .dw $ff04
+ .db "ICR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1
+XT_ICR1:
+ .dw PFA_DOVARIABLE
+PFA_ICR1:
+ .dw 70
+
+.endif
+.if WANT_TIMER_COUNTER_2 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register
+VE_TCCR2:
+ .dw $ff05
+ .db "TCCR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2
+XT_TCCR2:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2:
+ .dw 69
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Register
+VE_TCNT2:
+ .dw $ff05
+ .db "TCNT2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT2
+XT_TCNT2:
+ .dw PFA_DOVARIABLE
+PFA_TCNT2:
+ .dw 68
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare Register
+VE_OCR2:
+ .dw $ff04
+ .db "OCR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2
+XT_OCR2:
+ .dw PFA_DOVARIABLE
+PFA_OCR2:
+ .dw 67
+
+.endif
+.if WANT_TIMER_COUNTER_3 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Control Register A
+VE_TCCR3A:
+ .dw $ff06
+ .db "TCCR3A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR3A
+XT_TCCR3A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR3A:
+ .dw 139
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Control Register B
+VE_TCCR3B:
+ .dw $ff06
+ .db "TCCR3B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR3B
+XT_TCCR3B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR3B:
+ .dw 138
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Control Register C
+VE_TCCR3C:
+ .dw $ff06
+ .db "TCCR3C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR3C
+XT_TCCR3C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR3C:
+ .dw 140
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Bytes
+VE_TCNT3:
+ .dw $ff05
+ .db "TCNT3",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT3
+XT_TCNT3:
+ .dw PFA_DOVARIABLE
+PFA_TCNT3:
+ .dw 136
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Output Compare Register A Bytes
+VE_OCR3A:
+ .dw $ff05
+ .db "OCR3A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR3A
+XT_OCR3A:
+ .dw PFA_DOVARIABLE
+PFA_OCR3A:
+ .dw 134
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Output Compare Register B Bytes
+VE_OCR3B:
+ .dw $ff05
+ .db "OCR3B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR3B
+XT_OCR3B:
+ .dw PFA_DOVARIABLE
+PFA_OCR3B:
+ .dw 132
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Output compare Register C Bytes
+VE_OCR3C:
+ .dw $ff05
+ .db "OCR3C",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR3C
+XT_OCR3C:
+ .dw PFA_DOVARIABLE
+PFA_OCR3C:
+ .dw 130
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Input Capture Register Bytes
+VE_ICR3:
+ .dw $ff04
+ .db "ICR3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR3
+XT_ICR3:
+ .dw PFA_DOVARIABLE
+PFA_ICR3:
+ .dw 128
+
+.endif
+.if WANT_WATCHDOG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCR:
+ .dw $ff05
+ .db "WDTCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCR
+XT_WDTCR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCR:
+ .dw 65
+
+.endif
+.if WANT_AD_CONVERTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC multiplexer Selection Register
+VE_ADMUX:
+ .dw $ff05
+ .db "ADMUX",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADMUX
+XT_ADMUX:
+ .dw PFA_DOVARIABLE
+PFA_ADMUX:
+ .dw 39
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register
+VE_ADCSRA:
+ .dw $ff06
+ .db "ADCSRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRA
+XT_ADCSRA:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRA:
+ .dw 38
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register Bytes
+VE_ADC:
+ .dw $ff03
+ .db "ADC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADC
+XT_ADC:
+ .dw PFA_DOVARIABLE
+PFA_ADC:
+ .dw 36
+
+.endif
diff --git a/amforth-6.5/avr8/devices/atmega128/device.py b/amforth-6.5/avr8/devices/atmega128/device.py
new file mode 100644
index 0000000..fbb8cb1
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega128/device.py
@@ -0,0 +1,403 @@
+# Generated Automatically
+
+# Partname ATmega128
+
+MCUREGS = {
+# Interrupt Vectors
+ 'INT0Addr' : '#2', # External Interrupt Request 0
+ 'INT1Addr' : '#4', # External Interrupt Request 1
+ 'INT2Addr' : '#6', # External Interrupt Request 2
+ 'INT3Addr' : '#8', # External Interrupt Request 3
+ 'INT4Addr' : '#10', # External Interrupt Request 4
+ 'INT5Addr' : '#12', # External Interrupt Request 5
+ 'INT6Addr' : '#14', # External Interrupt Request 6
+ 'INT7Addr' : '#16', # External Interrupt Request 7
+ 'TIMER2_COMPAddr' : '#18', # Timer/Counter2 Compare Match
+ 'TIMER2_OVFAddr' : '#20', # Timer/Counter2 Overflow
+ 'TIMER1_CAPTAddr' : '#22', # Timer/Counter1 Capture Event
+ 'TIMER1_COMPAAddr' : '#24', # Timer/Counter1 Compare Match A
+ 'TIMER1_COMPBAddr' : '#26', # Timer/Counter Compare Match B
+ 'TIMER1_OVFAddr' : '#28', # Timer/Counter1 Overflow
+ 'TIMER0_COMPAddr' : '#30', # Timer/Counter0 Compare Match
+ 'TIMER0_OVFAddr' : '#32', # Timer/Counter0 Overflow
+ 'SPI_STCAddr' : '#34', # SPI Serial Transfer Complete
+ 'USART0_RXAddr' : '#36', # USART0, Rx Complete
+ 'USART0_UDREAddr' : '#38', # USART0 Data Register Empty
+ 'USART0_TXAddr' : '#40', # USART0, Tx Complete
+ 'ADCAddr' : '#42', # ADC Conversion Complete
+ 'EE_READYAddr' : '#44', # EEPROM Ready
+ 'ANALOG_COMPAddr' : '#46', # Analog Comparator
+ 'TIMER1_COMPCAddr' : '#48', # Timer/Counter1 Compare Match C
+ 'TIMER3_CAPTAddr' : '#50', # Timer/Counter3 Capture Event
+ 'TIMER3_COMPAAddr' : '#52', # Timer/Counter3 Compare Match A
+ 'TIMER3_COMPBAddr' : '#54', # Timer/Counter3 Compare Match B
+ 'TIMER3_COMPCAddr' : '#56', # Timer/Counter3 Compare Match C
+ 'TIMER3_OVFAddr' : '#58', # Timer/Counter3 Overflow
+ 'USART1_RXAddr' : '#60', # USART1, Rx Complete
+ 'USART1_UDREAddr' : '#62', # USART1, Data Register Empty
+ 'USART1_TXAddr' : '#64', # USART1, Tx Complete
+ 'TWIAddr' : '#66', # 2-wire Serial Interface
+ 'SPM_READYAddr' : '#68', # Store Program Memory Read
+
+# Module ANALOG_COMPARATOR
+ 'SFIOR' : '$40', # Special Function IO Register
+ 'SFIOR_ACME': '$8', # Analog Comparator Multiplexer
+ 'ACSR' : '$28', # Analog Comparator Control And
+ 'ACSR_ACD': '$80', # Analog Comparator Disable
+ 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
+ 'ACSR_ACO': '$20', # Analog Compare Output
+ 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
+ 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
+ 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
+ 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
+
+# Module SPI
+ 'SPDR' : '$2f', # SPI Data Register
+ 'SPSR' : '$2e', # SPI Status Register
+ 'SPSR_SPIF': '$80', # SPI Interrupt Flag
+ 'SPSR_WCOL': '$40', # Write Collision Flag
+ 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
+ 'SPCR' : '$2d', # SPI Control Register
+ 'SPCR_SPIE': '$80', # SPI Interrupt Enable
+ 'SPCR_SPE': '$40', # SPI Enable
+ 'SPCR_DORD': '$20', # Data Order
+ 'SPCR_MSTR': '$10', # Master/Slave Select
+ 'SPCR_CPOL': '$8', # Clock polarity
+ 'SPCR_CPHA': '$4', # Clock Phase
+ 'SPCR_SPR': '$3', # SPI Clock Rate Selects
+
+# Module TWI
+ 'TWBR' : '$70', # TWI Bit Rate register
+ 'TWCR' : '$74', # TWI Control Register
+ 'TWCR_TWINT': '$80', # TWI Interrupt Flag
+ 'TWCR_TWEA': '$40', # TWI Enable Acknowledge Bit
+ 'TWCR_TWSTA': '$20', # TWI Start Condition Bit
+ 'TWCR_TWSTO': '$10', # TWI Stop Condition Bit
+ 'TWCR_TWWC': '$8', # TWI Write Collition Flag
+ 'TWCR_TWEN': '$4', # TWI Enable Bit
+ 'TWCR_TWIE': '$1', # TWI Interrupt Enable
+ 'TWSR' : '$71', # TWI Status Register
+ 'TWSR_TWS': '$f8', # TWI Status
+ 'TWSR_TWPS': '$3', # TWI Prescaler
+ 'TWDR' : '$73', # TWI Data register
+ 'TWAR' : '$72', # TWI (Slave) Address register
+ 'TWAR_TWA': '$fe', # TWI (Slave) Address register B
+ 'TWAR_TWGCE': '$1', # TWI General Call Recognition E
+
+# Module USART0
+ 'UDR0' : '$2c', # USART I/O Data Register
+ 'UCSR0A' : '$2b', # USART Control and Status Regis
+ 'UCSR0A_RXC0': '$80', # USART Receive Complete
+ 'UCSR0A_TXC0': '$40', # USART Transmitt Complete
+ 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
+ 'UCSR0A_FE0': '$10', # Framing Error
+ 'UCSR0A_DOR0': '$8', # Data overRun
+ 'UCSR0A_UPE0': '$4', # Parity Error
+ 'UCSR0A_U2X0': '$2', # Double the USART transmission
+ 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
+ 'UCSR0B' : '$2a', # USART Control and Status Regis
+ 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
+ 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
+ 'UCSR0B_UDRIE0': '$20', # USART Data register Empty Inte
+ 'UCSR0B_RXEN0': '$10', # Receiver Enable
+ 'UCSR0B_TXEN0': '$8', # Transmitter Enable
+ 'UCSR0B_UCSZ02': '$4', # Character Size
+ 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
+ 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
+ 'UCSR0C' : '$95', # USART Control and Status Regis
+ 'UCSR0C_UMSEL0': '$40', # USART Mode Select
+ 'UCSR0C_UPM0': '$30', # Parity Mode Bits
+ 'UCSR0C_USBS0': '$8', # Stop Bit Select
+ 'UCSR0C_UCSZ0': '$6', # Character Size
+ 'UCSR0C_UCPOL0': '$1', # Clock Polarity
+ 'UBRR0H' : '$90', # USART Baud Rate Register Hight
+ 'UBRR0L' : '$29', # USART Baud Rate Register Low B
+
+# Module USART1
+ 'UDR1' : '$9c', # USART I/O Data Register
+ 'UCSR1A' : '$9b', # USART Control and Status Regis
+ 'UCSR1A_RXC1': '$80', # USART Receive Complete
+ 'UCSR1A_TXC1': '$40', # USART Transmitt Complete
+ 'UCSR1A_UDRE1': '$20', # USART Data Register Empty
+ 'UCSR1A_FE1': '$10', # Framing Error
+ 'UCSR1A_DOR1': '$8', # Data overRun
+ 'UCSR1A_UPE1': '$4', # Parity Error
+ 'UCSR1A_U2X1': '$2', # Double the USART transmission
+ 'UCSR1A_MPCM1': '$1', # Multi-processor Communication
+ 'UCSR1B' : '$9a', # USART Control and Status Regis
+ 'UCSR1B_RXCIE1': '$80', # RX Complete Interrupt Enable
+ 'UCSR1B_TXCIE1': '$40', # TX Complete Interrupt Enable
+ 'UCSR1B_UDRIE1': '$20', # USART Data register Empty Inte
+ 'UCSR1B_RXEN1': '$10', # Receiver Enable
+ 'UCSR1B_TXEN1': '$8', # Transmitter Enable
+ 'UCSR1B_UCSZ12': '$4', # Character Size
+ 'UCSR1B_RXB81': '$2', # Receive Data Bit 8
+ 'UCSR1B_TXB81': '$1', # Transmit Data Bit 8
+ 'UCSR1C' : '$9d', # USART Control and Status Regis
+ 'UCSR1C_UMSEL1': '$40', # USART Mode Select
+ 'UCSR1C_UPM1': '$30', # Parity Mode Bits
+ 'UCSR1C_USBS1': '$8', # Stop Bit Select
+ 'UCSR1C_UCSZ1': '$6', # Character Size
+ 'UCSR1C_UCPOL1': '$1', # Clock Polarity
+ 'UBRR1H' : '$98', # USART Baud Rate Register Hight
+ 'UBRR1L' : '$99', # USART Baud Rate Register Low B
+
+# Module CPU
+ 'SREG' : '$5f', # Status Register
+ 'SREG_I': '$80', # Global Interrupt Enable
+ 'SREG_T': '$40', # Bit Copy Storage
+ 'SREG_H': '$20', # Half Carry Flag
+ 'SREG_S': '$10', # Sign Bit
+ 'SREG_V': '$8', # Two's Complement Overflow Flag
+ 'SREG_N': '$4', # Negative Flag
+ 'SREG_Z': '$2', # Zero Flag
+ 'SREG_C': '$1', # Carry Flag
+ 'SP' : '$5d', # Stack Pointer
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_SRE': '$80', # External SRAM Enable
+ 'MCUCR_SRW10': '$40', # External SRAM Wait State Selec
+ 'MCUCR_SE': '$20', # Sleep Enable
+ 'MCUCR_SM': '$18', # Sleep Mode Select
+ 'MCUCR_SM2': '$4', # Sleep Mode Select
+ 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
+ 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
+ 'MCUCSR' : '$54', # MCU Control And Status Registe
+ 'MCUCSR_JTD': '$80', # JTAG Interface Disable
+ 'MCUCSR_JTRF': '$10', # JTAG Reset Flag
+ 'MCUCSR_WDRF': '$8', # Watchdog Reset Flag
+ 'MCUCSR_BORF': '$4', # Brown-out Reset Flag
+ 'MCUCSR_EXTRF': '$2', # External Reset Flag
+ 'MCUCSR_PORF': '$1', # Power-on reset flag
+ 'XMCRA' : '$6d', # External Memory Control Regist
+ 'XMCRA_SRL': '$70', # Wait state page limit
+ 'XMCRA_SRW0': '$c', # Wait state select bit lower pa
+ 'XMCRA_SRW11': '$2', # Wait state select bit upper pa
+ 'XMCRB' : '$6c', # External Memory Control Regist
+ 'XMCRB_XMBK': '$80', # External Memory Bus Keeper Ena
+ 'XMCRB_XMM': '$7', # External Memory High Mask
+ 'OSCCAL' : '$6f', # Oscillator Calibration Value
+ 'XDIV' : '$5c', # XTAL Divide Control Register
+ 'RAMPZ' : '$5b', # RAM Page Z Select Register
+ 'RAMPZ_RAMPZ0': '$1', # RAM Page Z Select Register Bit
+
+# Module BOOT_LOAD
+ 'SPMCSR' : '$68', # Store Program Memory Control R
+ 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
+ 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
+ 'SPMCSR_RWWSRE': '$10', # Read While Write section read
+ 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
+ 'SPMCSR_PGWRT': '$4', # Page Write
+ 'SPMCSR_PGERS': '$2', # Page Erase
+ 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
+
+# Module JTAG
+ 'OCDR' : '$42', # On-Chip Debug Related Register
+ 'OCDR_OCDR': '$ff', # On-Chip Debug Register Bits
+ 'MCUCSR' : '$54', # MCU Control And Status Registe
+ 'MCUCSR_JTD': '$80', # JTAG Interface Disable
+ 'MCUCSR_JTRF': '$10', # JTAG Reset Flag
+
+# Module MISC
+ 'SFIOR' : '$40', # Special Function IO Register
+ 'SFIOR_TSM': '$80', # Timer/Counter Synchronization
+ 'SFIOR_ACME': '$8', # Analog Comparator Multiplexer
+ 'SFIOR_PUD': '$4', # Pull Up Disable
+ 'SFIOR_PSR0': '$2', # Prescaler Reset Timer/Counter0
+ 'SFIOR_PSR321': '$1', # Prescaler Reset Timer/Counter3
+
+# Module EXTERNAL_INTERRUPT
+ 'EICRA' : '$6a', # External Interrupt Control Reg
+ 'EICRA_ISC3': '$c0', # External Interrupt Sense Contr
+ 'EICRA_ISC2': '$30', # External Interrupt Sense Contr
+ 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
+ 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
+ 'EICRB' : '$5a', # External Interrupt Control Reg
+ 'EICRB_ISC7': '$c0', # External Interrupt 7-4 Sense C
+ 'EICRB_ISC6': '$30', # External Interrupt 7-4 Sense C
+ 'EICRB_ISC5': '$c', # External Interrupt 7-4 Sense C
+ 'EICRB_ISC4': '$3', # External Interrupt 7-4 Sense C
+ 'EIMSK' : '$59', # External Interrupt Mask Regist
+ 'EIMSK_INT': '$ff', # External Interrupt Request 7 E
+ 'EIFR' : '$58', # External Interrupt Flag Regist
+ 'EIFR_INTF': '$ff', # External Interrupt Flags
+
+# Module EEPROM
+ 'EEAR' : '$3e', # EEPROM Read/Write Access Byte
+ 'EEDR' : '$3d', # EEPROM Data Register
+ 'EECR' : '$3c', # EEPROM Control Register
+ 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
+ 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
+ 'EECR_EEWE': '$2', # EEPROM Write Enable
+ 'EECR_EERE': '$1', # EEPROM Read Enable
+
+# Module PORTA
+ 'PORTA' : '$3b', # Port A Data Register
+ 'DDRA' : '$3a', # Port A Data Direction Register
+ 'PINA' : '$39', # Port A Input Pins
+
+# Module PORTB
+ 'PORTB' : '$38', # Port B Data Register
+ 'DDRB' : '$37', # Port B Data Direction Register
+ 'PINB' : '$36', # Port B Input Pins
+
+# Module PORTC
+ 'PORTC' : '$35', # Port C Data Register
+ 'DDRC' : '$34', # Port C Data Direction Register
+ 'PINC' : '$33', # Port C Input Pins
+
+# Module PORTD
+ 'PORTD' : '$32', # Port D Data Register
+ 'DDRD' : '$31', # Port D Data Direction Register
+ 'PIND' : '$30', # Port D Input Pins
+
+# Module PORTE
+ 'PORTE' : '$23', # Data Register, Port E
+ 'DDRE' : '$22', # Data Direction Register, Port
+ 'PINE' : '$21', # Input Pins, Port E
+
+# Module PORTF
+ 'PORTF' : '$62', # Data Register, Port F
+ 'DDRF' : '$61', # Data Direction Register, Port
+ 'PINF' : '$20', # Input Pins, Port F
+
+# Module PORTG
+ 'PORTG' : '$65', # Data Register, Port G
+ 'DDRG' : '$64', # Data Direction Register, Port
+ 'PING' : '$63', # Input Pins, Port G
+
+# Module TIMER_COUNTER_0
+ 'TCCR0' : '$53', # Timer/Counter Control Register
+ 'TCCR0_FOC0': '$80', # Force Output Compare
+ 'TCCR0_WGM00': '$40', # Waveform Generation Mode 0
+ 'TCCR0_COM0': '$30', # Compare Match Output Modes
+ 'TCCR0_WGM01': '$8', # Waveform Generation Mode 1
+ 'TCCR0_CS0': '$7', # Clock Selects
+ 'TCNT0' : '$52', # Timer/Counter Register
+ 'OCR0' : '$51', # Output Compare Register
+ 'ASSR' : '$50', # Asynchronus Status Register
+ 'ASSR_AS0': '$8', # Asynchronus Timer/Counter 0
+ 'ASSR_TCN0UB': '$4', # Timer/Counter0 Update Busy
+ 'ASSR_OCR0UB': '$2', # Output Compare register 0 Busy
+ 'ASSR_TCR0UB': '$1', # Timer/Counter Control Register
+ 'TIMSK' : '$57', # Timer/Counter Interrupt Mask R
+ 'TIMSK_OCIE0': '$2', # Timer/Counter0 Output Compare
+ 'TIMSK_TOIE0': '$1', # Timer/Counter0 Overflow Interr
+ 'TIFR' : '$56', # Timer/Counter Interrupt Flag r
+ 'TIFR_OCF0': '$2', # Output Compare Flag 0
+ 'TIFR_TOV0': '$1', # Timer/Counter0 Overflow Flag
+ 'SFIOR' : '$40', # Special Function IO Register
+ 'SFIOR_TSM': '$80', # Timer/Counter Synchronization
+ 'SFIOR_PSR0': '$2', # Prescaler Reset Timer/Counter0
+
+# Module TIMER_COUNTER_1
+ 'TIMSK' : '$57', # Timer/Counter Interrupt Mask R
+ 'TIMSK_TICIE1': '$20', # Timer/Counter1 Input Capture I
+ 'TIMSK_OCIE1A': '$10', # Timer/Counter1 Output CompareA
+ 'TIMSK_OCIE1B': '$8', # Timer/Counter1 Output CompareB
+ 'TIMSK_TOIE1': '$4', # Timer/Counter1 Overflow Interr
+ 'ETIMSK' : '$7d', # Extended Timer/Counter Interru
+ 'ETIMSK_OCIE1C': '$1', # Timer/Counter 1, Output Compar
+ 'TIFR' : '$56', # Timer/Counter Interrupt Flag r
+ 'TIFR_ICF1': '$20', # Input Capture Flag 1
+ 'TIFR_OCF1A': '$10', # Output Compare Flag 1A
+ 'TIFR_OCF1B': '$8', # Output Compare Flag 1B
+ 'TIFR_TOV1': '$4', # Timer/Counter1 Overflow Flag
+ 'ETIFR' : '$7c', # Extended Timer/Counter Interru
+ 'ETIFR_OCF1C': '$1', # Timer/Counter 1, Output Compar
+ 'SFIOR' : '$40', # Special Function IO Register
+ 'SFIOR_TSM': '$80', # Timer/Counter Synchronization
+ 'SFIOR_PSR321': '$1', # Prescaler Reset, T/C3, T/C2, T
+ 'TCCR1A' : '$4f', # Timer/Counter1 Control Registe
+ 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
+ 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
+ 'TCCR1A_COM1C': '$c', # Compare Output Mode 1C, bits
+ 'TCCR1A_WGM1': '$3', # Waveform Generation Mode Bits
+ 'TCCR1B' : '$4e', # Timer/Counter1 Control Registe
+ 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
+ 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
+ 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
+ 'TCCR1B_CS1': '$7', # Clock Select1 bits
+ 'TCCR1C' : '$7a', # Timer/Counter1 Control Registe
+ 'TCCR1C_FOC1A': '$80', # Force Output Compare for chann
+ 'TCCR1C_FOC1B': '$40', # Force Output Compare for chann
+ 'TCCR1C_FOC1C': '$20', # Force Output Compare for chann
+ 'TCNT1' : '$4c', # Timer/Counter1 Bytes
+ 'OCR1A' : '$4a', # Timer/Counter1 Output Compare
+ 'OCR1B' : '$48', # Timer/Counter1 Output Compare
+ 'OCR1C' : '$78', # Timer/Counter1 Output Compare
+ 'ICR1' : '$46', # Timer/Counter1 Input Capture R
+
+# Module TIMER_COUNTER_2
+ 'TCCR2' : '$45', # Timer/Counter Control Register
+ 'TCCR2_FOC2': '$80', # Force Output Compare
+ 'TCCR2_WGM20': '$40', # Wafeform Generation Mode
+ 'TCCR2_COM2': '$30', # Compare Match Output Mode
+ 'TCCR2_WGM21': '$8', # Waveform Generation Mode
+ 'TCCR2_CS2': '$7', # Clock Select
+ 'TCNT2' : '$44', # Timer/Counter Register
+ 'OCR2' : '$43', # Output Compare Register
+ 'TIFR' : '$56', # Timer/Counter Interrupt Flag R
+ 'TIFR_OCF2': '$80', # Output Compare Flag 2
+ 'TIFR_TOV2': '$40', # Timer/Counter2 Overflow Flag
+ 'TIMSK' : '$57', #
+ 'TIMSK_OCIE2': '$80', #
+ 'TIMSK_TOIE2': '$40', #
+
+# Module TIMER_COUNTER_3
+ 'ETIMSK' : '$7d', # Extended Timer/Counter Interru
+ 'ETIMSK_TICIE3': '$20', # Timer/Counter3 Input Capture I
+ 'ETIMSK_OCIE3A': '$10', # Timer/Counter3 Output CompareA
+ 'ETIMSK_OCIE3B': '$8', # Timer/Counter3 Output CompareB
+ 'ETIMSK_TOIE3': '$4', # Timer/Counter3 Overflow Interr
+ 'ETIMSK_OCIE3C': '$2', # Timer/Counter3, Output Compare
+ 'ETIFR' : '$7c', # Extended Timer/Counter Interru
+ 'ETIFR_ICF3': '$20', # Input Capture Flag 1
+ 'ETIFR_OCF3A': '$10', # Output Compare Flag 1A
+ 'ETIFR_OCF3B': '$8', # Output Compare Flag 1B
+ 'ETIFR_TOV3': '$4', # Timer/Counter3 Overflow Flag
+ 'ETIFR_OCF3C': '$2', # Timer/Counter3 Output Compare
+ 'SFIOR' : '$40', # Special Function IO Register
+ 'SFIOR_TSM': '$80', # Timer/Counter Synchronization
+ 'SFIOR_PSR321': '$1', # Prescaler Reset, T/C3, T/C2, T
+ 'TCCR3A' : '$8b', # Timer/Counter3 Control Registe
+ 'TCCR3A_COM3A': '$c0', # Compare Output Mode 3A, bits
+ 'TCCR3A_COM3B': '$30', # Compare Output Mode 3B, bits
+ 'TCCR3A_COM3C': '$c', # Compare Output Mode 3C, bits
+ 'TCCR3A_WGM3': '$3', # Waveform Generation Mode Bits
+ 'TCCR3B' : '$8a', # Timer/Counter3 Control Registe
+ 'TCCR3B_ICNC3': '$80', # Input Capture 3 Noise Cancele
+ 'TCCR3B_ICES3': '$40', # Input Capture 3 Edge Select
+ 'TCCR3B_WGM3': '$18', # Waveform Generation Mode
+ 'TCCR3B_CS3': '$7', # Clock Select3 bits
+ 'TCCR3C' : '$8c', # Timer/Counter3 Control Registe
+ 'TCCR3C_FOC3A': '$80', # Force Output Compare for chann
+ 'TCCR3C_FOC3B': '$40', # Force Output Compare for chann
+ 'TCCR3C_FOC3C': '$20', # Force Output Compare for chann
+ 'TCNT3' : '$88', # Timer/Counter3 Bytes
+ 'OCR3A' : '$86', # Timer/Counter3 Output Compare
+ 'OCR3B' : '$84', # Timer/Counter3 Output Compare
+ 'OCR3C' : '$82', # Timer/Counter3 Output compare
+ 'ICR3' : '$80', # Timer/Counter3 Input Capture R
+
+# Module WATCHDOG
+ 'WDTCR' : '$41', # Watchdog Timer Control Registe
+ 'WDTCR_WDCE': '$10', # Watchdog Change Enable
+ 'WDTCR_WDE': '$8', # Watch Dog Enable
+ 'WDTCR_WDP': '$7', # Watch Dog Timer Prescaler bits
+
+# Module AD_CONVERTER
+ 'ADMUX' : '$27', # The ADC multiplexer Selection
+ 'ADMUX_REFS': '$c0', # Reference Selection Bits
+ 'ADMUX_ADLAR': '$20', # Left Adjust Result
+ 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
+ 'ADCSRA' : '$26', # The ADC Control and Status reg
+ 'ADCSRA_ADEN': '$80', # ADC Enable
+ 'ADCSRA_ADSC': '$40', # ADC Start Conversion
+ 'ADCSRA_ADFR': '$20', # ADC Free Running Select
+ 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
+ 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
+ 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
+ 'ADC' : '$24', # ADC Data Register Bytes
+
+ '__amforth_dummy':'0'
+}
diff --git a/amforth-6.5/avr8/devices/atmega128/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega128/words/no-jtag.asm
new file mode 100644
index 0000000..352a4bb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega128/words/no-jtag.asm
@@ -0,0 +1,14 @@
+; ( -- )
+; ( -- )
+; MCU
+; disable jtag at runtime
+VE_NOJTAG:
+ .dw $FF05
+ .db "-jtag",0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOJTAG
+XT_NOJTAG:
+ .dw PFA_NOJTAG
+PFA_NOJTAG:
+
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega128/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega128/words/no-wdt.asm
new file mode 100644
index 0000000..4a12261
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega128/words/no-wdt.asm
@@ -0,0 +1,22 @@
+; ( -- )
+; MCU
+; disable watch dog timer at runtime
+VE_NOWDT:
+ .dw $ff04
+ .db "-wdt"
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOWDT
+XT_NOWDT:
+ .dw PFA_NOWDT
+PFA_NOWDT:
+
+; Reset WDT
+ wdr
+; Write logical one to WDTOE and WDE
+ in_ temp1, WDTCR
+ ori temp1, (1<<WDTOE)|(1<<WDE)
+ out WDTCR, temp1
+; Turn off WDT
+ ldi temp1, (0<<WDE)
+ out_ WDTCR, temp1
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega128/words/sleep.asm b/amforth-6.5/avr8/devices/atmega128/words/sleep.asm
new file mode 100644
index 0000000..778fa32
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega128/words/sleep.asm
@@ -0,0 +1,24 @@
+; ( mode -- )
+; MCU
+; put the controller into the specified sleep mode
+VE_SLEEP:
+ .dw $ff05
+ .db "sleep", 0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_SLEEP
+XT_SLEEP:
+ .dw PFA_SLEEP
+PFA_SLEEP:
+ andi tosl, 7 ; leave only legal mode bits
+ swap tosl ; move to correct location (bits 6-4, atmega32)
+ ori tosl, $80 ; set the SE bit (atmega32: bit 7, not bit 0)
+ out_ MCUCR, tosl ; set the sleep config (atmega32: MCUCR not SMCR)
+ sleep ; nighty-night
+;; the 4 lower bits of MCUCR should not be touched
+ in_ tosl, MCUCR
+ andi tosl, $0F
+ out_ MCUCR, tosl
+ ;clr tosl ; need to clean up the SMCR reg before we leave
+ ;out SMCR, tosl ; 0 protects against accidental sleeps
+ loadtos ; pop argument from stack
+ jmp DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega1280/atmega1280.frt b/amforth-6.5/avr8/devices/atmega1280/atmega1280.frt
new file mode 100644
index 0000000..6fef8ef
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega1280/atmega1280.frt
@@ -0,0 +1,580 @@
+\ Partname: ATmega1280
+\ generated automatically
+
+\ ANALOG_COMPARATOR
+&123 constant ADCSRB \ ADC Control and Status Register B
+ $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer Enable
+&80 constant ACSR \ Analog Comparator Control And Status Register
+ $80 constant ACSR_ACD \ Analog Comparator Disable
+ $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
+ $20 constant ACSR_ACO \ Analog Compare Output
+ $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
+ $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
+ $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
+ $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
+&127 constant DIDR1 \ Digital Input Disable Register 1
+ $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
+ $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
+\ USART0
+&198 constant UDR0 \ USART I/O Data Register
+&192 constant UCSR0A \ USART Control and Status Register A
+ $80 constant UCSR0A_RXC0 \ USART Receive Complete
+ $40 constant UCSR0A_TXC0 \ USART Transmitt Complete
+ $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
+ $10 constant UCSR0A_FE0 \ Framing Error
+ $08 constant UCSR0A_DOR0 \ Data overRun
+ $04 constant UCSR0A_UPE0 \ Parity Error
+ $02 constant UCSR0A_U2X0 \ Double the USART transmission speed
+ $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
+&193 constant UCSR0B \ USART Control and Status Register B
+ $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
+ $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
+ $20 constant UCSR0B_UDRIE0 \ USART Data register Empty Interrupt Enable
+ $10 constant UCSR0B_RXEN0 \ Receiver Enable
+ $08 constant UCSR0B_TXEN0 \ Transmitter Enable
+ $04 constant UCSR0B_UCSZ02 \ Character Size
+ $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
+ $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
+&194 constant UCSR0C \ USART Control and Status Register C
+ $C0 constant UCSR0C_UMSEL0 \ USART Mode Select
+ $30 constant UCSR0C_UPM0 \ Parity Mode Bits
+ $08 constant UCSR0C_USBS0 \ Stop Bit Select
+ $06 constant UCSR0C_UCSZ0 \ Character Size
+ $01 constant UCSR0C_UCPOL0 \ Clock Polarity
+&196 constant UBRR0 \ USART Baud Rate Register Bytes
+\ TWI
+&189 constant TWAMR \ TWI (Slave) Address Mask Register
+ $FE constant TWAMR_TWAM \
+&184 constant TWBR \ TWI Bit Rate register
+&188 constant TWCR \ TWI Control Register
+ $80 constant TWCR_TWINT \ TWI Interrupt Flag
+ $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
+ $20 constant TWCR_TWSTA \ TWI Start Condition Bit
+ $10 constant TWCR_TWSTO \ TWI Stop Condition Bit
+ $08 constant TWCR_TWWC \ TWI Write Collition Flag
+ $04 constant TWCR_TWEN \ TWI Enable Bit
+ $01 constant TWCR_TWIE \ TWI Interrupt Enable
+&185 constant TWSR \ TWI Status Register
+ $F8 constant TWSR_TWS \ TWI Status
+ $03 constant TWSR_TWPS \ TWI Prescaler
+&187 constant TWDR \ TWI Data register
+&186 constant TWAR \ TWI (Slave) Address register
+ $FE constant TWAR_TWA \ TWI (Slave) Address register Bits
+ $01 constant TWAR_TWGCE \ TWI General Call Recognition Enable Bit
+\ SPI
+&76 constant SPCR \ SPI Control Register
+ $80 constant SPCR_SPIE \ SPI Interrupt Enable
+ $40 constant SPCR_SPE \ SPI Enable
+ $20 constant SPCR_DORD \ Data Order
+ $10 constant SPCR_MSTR \ Master/Slave Select
+ $08 constant SPCR_CPOL \ Clock polarity
+ $04 constant SPCR_CPHA \ Clock Phase
+ $03 constant SPCR_SPR \ SPI Clock Rate Selects
+&77 constant SPSR \ SPI Status Register
+ $80 constant SPSR_SPIF \ SPI Interrupt Flag
+ $40 constant SPSR_WCOL \ Write Collision Flag
+ $01 constant SPSR_SPI2X \ Double SPI Speed Bit
+&78 constant SPDR \ SPI Data Register
+\ PORTA
+&34 constant PORTA \ Port A Data Register
+&33 constant DDRA \ Port A Data Direction Register
+&32 constant PINA \ Port A Input Pins
+\ PORTB
+&37 constant PORTB \ Port B Data Register
+&36 constant DDRB \ Port B Data Direction Register
+&35 constant PINB \ Port B Input Pins
+\ PORTC
+&40 constant PORTC \ Port C Data Register
+&39 constant DDRC \ Port C Data Direction Register
+&38 constant PINC \ Port C Input Pins
+\ PORTD
+&43 constant PORTD \ Port D Data Register
+&42 constant DDRD \ Port D Data Direction Register
+&41 constant PIND \ Port D Input Pins
+\ PORTE
+&46 constant PORTE \ Data Register, Port E
+&45 constant DDRE \ Data Direction Register, Port E
+&44 constant PINE \ Input Pins, Port E
+\ PORTF
+&49 constant PORTF \ Data Register, Port F
+&48 constant DDRF \ Data Direction Register, Port F
+&47 constant PINF \ Input Pins, Port F
+\ PORTG
+&52 constant PORTG \ Data Register, Port G
+&51 constant DDRG \ Data Direction Register, Port G
+&50 constant PING \ Input Pins, Port G
+\ PORTH
+&258 constant PORTH \ PORT H Data Register
+&257 constant DDRH \ PORT H Data Direction Register
+&256 constant PINH \ PORT H Input Pins
+\ PORTJ
+&261 constant PORTJ \ PORT J Data Register
+&260 constant DDRJ \ PORT J Data Direction Register
+&259 constant PINJ \ PORT J Input Pins
+\ PORTK
+&264 constant PORTK \ PORT K Data Register
+&263 constant DDRK \ PORT K Data Direction Register
+&262 constant PINK \ PORT K Input Pins
+\ PORTL
+&267 constant PORTL \ PORT L Data Register
+&266 constant DDRL \ PORT L Data Direction Register
+&265 constant PINL \ PORT L Input Pins
+\ TIMER_COUNTER_0
+&72 constant OCR0B \ Timer/Counter0 Output Compare Register
+&71 constant OCR0A \ Timer/Counter0 Output Compare Register
+&70 constant TCNT0 \ Timer/Counter0
+&69 constant TCCR0B \ Timer/Counter Control Register B
+ $80 constant TCCR0B_FOC0A \ Force Output Compare A
+ $40 constant TCCR0B_FOC0B \ Force Output Compare B
+ $08 constant TCCR0B_WGM02 \
+ $07 constant TCCR0B_CS0 \ Clock Select
+&68 constant TCCR0A \ Timer/Counter Control Register A
+ $C0 constant TCCR0A_COM0A \ Compare Output Mode, Phase Correct PWM Mode
+ $30 constant TCCR0A_COM0B \ Compare Output Mode, Fast PWm
+ $03 constant TCCR0A_WGM0 \ Waveform Generation Mode
+&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
+ $04 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare Match B Interrupt Enable
+ $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match A Interrupt Enable
+ $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
+&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
+ $04 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare Flag 0B
+ $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0A
+ $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
+&67 constant GTCCR \ General Timer/Counter Control Register
+ $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
+ $01 constant GTCCR_PSRSYNC \ Prescaler Reset Timer/Counter1 and Timer/Counter0
+\ TIMER_COUNTER_2
+&112 constant TIMSK2 \ Timer/Counter Interrupt Mask register
+ $04 constant TIMSK2_OCIE2B \ Timer/Counter2 Output Compare Match B Interrupt Enable
+ $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match A Interrupt Enable
+ $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
+&55 constant TIFR2 \ Timer/Counter Interrupt Flag Register
+ $04 constant TIFR2_OCF2B \ Output Compare Flag 2B
+ $02 constant TIFR2_OCF2A \ Output Compare Flag 2A
+ $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
+&176 constant TCCR2A \ Timer/Counter2 Control Register A
+ $C0 constant TCCR2A_COM2A \ Compare Output Mode bits
+ $30 constant TCCR2A_COM2B \ Compare Output Mode bits
+ $03 constant TCCR2A_WGM2 \ Waveform Genration Mode
+&177 constant TCCR2B \ Timer/Counter2 Control Register B
+ $80 constant TCCR2B_FOC2A \ Force Output Compare A
+ $40 constant TCCR2B_FOC2B \ Force Output Compare B
+ $08 constant TCCR2B_WGM22 \ Waveform Generation Mode
+ $07 constant TCCR2B_CS2 \ Clock Select bits
+&178 constant TCNT2 \ Timer/Counter2
+&180 constant OCR2B \ Timer/Counter2 Output Compare Register B
+&179 constant OCR2A \ Timer/Counter2 Output Compare Register A
+&182 constant ASSR \ Asynchronous Status Register
+ $40 constant ASSR_EXCLK \ Enable External Clock Input
+ $20 constant ASSR_AS2 \ Asynchronous Timer/Counter2
+ $10 constant ASSR_TCN2UB \ Timer/Counter2 Update Busy
+ $08 constant ASSR_OCR2AUB \ Output Compare Register2 Update Busy
+ $04 constant ASSR_OCR2BUB \ Output Compare Register 2 Update Busy
+ $02 constant ASSR_TCR2AUB \ Timer/Counter Control Register2 Update Busy
+ $01 constant ASSR_TCR2BUB \ Timer/Counter Control Register2 Update Busy
+\ WATCHDOG
+&96 constant WDTCSR \ Watchdog Timer Control Register
+ $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Flag
+ $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Enable
+ $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
+ $10 constant WDTCSR_WDCE \ Watchdog Change Enable
+ $08 constant WDTCSR_WDE \ Watch Dog Enable
+\ USART1
+&206 constant UDR1 \ USART I/O Data Register
+&200 constant UCSR1A \ USART Control and Status Register A
+ $80 constant UCSR1A_RXC1 \ USART Receive Complete
+ $40 constant UCSR1A_TXC1 \ USART Transmitt Complete
+ $20 constant UCSR1A_UDRE1 \ USART Data Register Empty
+ $10 constant UCSR1A_FE1 \ Framing Error
+ $08 constant UCSR1A_DOR1 \ Data overRun
+ $04 constant UCSR1A_UPE1 \ Parity Error
+ $02 constant UCSR1A_U2X1 \ Double the USART transmission speed
+ $01 constant UCSR1A_MPCM1 \ Multi-processor Communication Mode
+&201 constant UCSR1B \ USART Control and Status Register B
+ $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable
+ $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable
+ $20 constant UCSR1B_UDRIE1 \ USART Data register Empty Interrupt Enable
+ $10 constant UCSR1B_RXEN1 \ Receiver Enable
+ $08 constant UCSR1B_TXEN1 \ Transmitter Enable
+ $04 constant UCSR1B_UCSZ12 \ Character Size
+ $02 constant UCSR1B_RXB81 \ Receive Data Bit 8
+ $01 constant UCSR1B_TXB81 \ Transmit Data Bit 8
+&202 constant UCSR1C \ USART Control and Status Register C
+ $C0 constant UCSR1C_UMSEL1 \ USART Mode Select
+ $30 constant UCSR1C_UPM1 \ Parity Mode Bits
+ $08 constant UCSR1C_USBS1 \ Stop Bit Select
+ $06 constant UCSR1C_UCSZ1 \ Character Size
+ $01 constant UCSR1C_UCPOL1 \ Clock Polarity
+&204 constant UBRR1 \ USART Baud Rate Register Bytes
+\ EEPROM
+&65 constant EEAR \ EEPROM Address Register Low Bytes
+&64 constant EEDR \ EEPROM Data Register
+&63 constant EECR \ EEPROM Control Register
+ $30 constant EECR_EEPM \ EEPROM Programming Mode Bits
+ $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
+ $04 constant EECR_EEMPE \ EEPROM Master Write Enable
+ $02 constant EECR_EEPE \ EEPROM Write Enable
+ $01 constant EECR_EERE \ EEPROM Read Enable
+\ TIMER_COUNTER_5
+&288 constant TCCR5A \ Timer/Counter5 Control Register A
+ $C0 constant TCCR5A_COM5A \ Compare Output Mode 1A, bits
+ $30 constant TCCR5A_COM5B \ Compare Output Mode 5B, bits
+ $0C constant TCCR5A_COM5C \ Compare Output Mode 5C, bits
+ $03 constant TCCR5A_WGM5 \ Waveform Generation Mode
+&289 constant TCCR5B \ Timer/Counter5 Control Register B
+ $80 constant TCCR5B_ICNC5 \ Input Capture 5 Noise Canceler
+ $40 constant TCCR5B_ICES5 \ Input Capture 5 Edge Select
+ $18 constant TCCR5B_WGM5 \ Waveform Generation Mode
+ $07 constant TCCR5B_CS5 \ Prescaler source of Timer/Counter 5
+&290 constant TCCR5C \ Timer/Counter 5 Control Register C
+ $80 constant TCCR5C_FOC5A \ Force Output Compare 5A
+ $40 constant TCCR5C_FOC5B \ Force Output Compare 5B
+ $20 constant TCCR5C_FOC5C \ Force Output Compare 5C
+&292 constant TCNT5 \ Timer/Counter5 Bytes
+&296 constant OCR5A \ Timer/Counter5 Output Compare Register A Bytes
+&298 constant OCR5B \ Timer/Counter5 Output Compare Register B Bytes
+&300 constant OCR5C \ Timer/Counter5 Output Compare Register B Bytes
+&294 constant ICR5 \ Timer/Counter5 Input Capture Register Bytes
+&115 constant TIMSK5 \ Timer/Counter5 Interrupt Mask Register
+ $20 constant TIMSK5_ICIE5 \ Timer/Counter5 Input Capture Interrupt Enable
+ $08 constant TIMSK5_OCIE5C \ Timer/Counter5 Output Compare C Match Interrupt Enable
+ $04 constant TIMSK5_OCIE5B \ Timer/Counter5 Output Compare B Match Interrupt Enable
+ $02 constant TIMSK5_OCIE5A \ Timer/Counter5 Output Compare A Match Interrupt Enable
+ $01 constant TIMSK5_TOIE5 \ Timer/Counter5 Overflow Interrupt Enable
+&58 constant TIFR5 \ Timer/Counter5 Interrupt Flag register
+ $20 constant TIFR5_ICF5 \ Input Capture Flag 5
+ $08 constant TIFR5_OCF5C \ Output Compare Flag 5C
+ $04 constant TIFR5_OCF5B \ Output Compare Flag 5B
+ $02 constant TIFR5_OCF5A \ Output Compare Flag 5A
+ $01 constant TIFR5_TOV5 \ Timer/Counter5 Overflow Flag
+\ TIMER_COUNTER_4
+&160 constant TCCR4A \ Timer/Counter4 Control Register A
+ $C0 constant TCCR4A_COM4A \ Compare Output Mode 1A, bits
+ $30 constant TCCR4A_COM4B \ Compare Output Mode 4B, bits
+ $0C constant TCCR4A_COM4C \ Compare Output Mode 4C, bits
+ $03 constant TCCR4A_WGM4 \ Waveform Generation Mode
+&161 constant TCCR4B \ Timer/Counter4 Control Register B
+ $80 constant TCCR4B_ICNC4 \ Input Capture 4 Noise Canceler
+ $40 constant TCCR4B_ICES4 \ Input Capture 4 Edge Select
+ $18 constant TCCR4B_WGM4 \ Waveform Generation Mode
+ $07 constant TCCR4B_CS4 \ Prescaler source of Timer/Counter 4
+&162 constant TCCR4C \ Timer/Counter 4 Control Register C
+ $80 constant TCCR4C_FOC4A \ Force Output Compare 4A
+ $40 constant TCCR4C_FOC4B \ Force Output Compare 4B
+ $20 constant TCCR4C_FOC4C \ Force Output Compare 4C
+&164 constant TCNT4 \ Timer/Counter4 Bytes
+&168 constant OCR4A \ Timer/Counter4 Output Compare Register A Bytes
+&170 constant OCR4B \ Timer/Counter4 Output Compare Register B Bytes
+&172 constant OCR4C \ Timer/Counter4 Output Compare Register B Bytes
+&166 constant ICR4 \ Timer/Counter4 Input Capture Register Bytes
+&114 constant TIMSK4 \ Timer/Counter4 Interrupt Mask Register
+ $20 constant TIMSK4_ICIE4 \ Timer/Counter4 Input Capture Interrupt Enable
+ $08 constant TIMSK4_OCIE4C \ Timer/Counter4 Output Compare C Match Interrupt Enable
+ $04 constant TIMSK4_OCIE4B \ Timer/Counter4 Output Compare B Match Interrupt Enable
+ $02 constant TIMSK4_OCIE4A \ Timer/Counter4 Output Compare A Match Interrupt Enable
+ $01 constant TIMSK4_TOIE4 \ Timer/Counter4 Overflow Interrupt Enable
+&57 constant TIFR4 \ Timer/Counter4 Interrupt Flag register
+ $20 constant TIFR4_ICF4 \ Input Capture Flag 4
+ $08 constant TIFR4_OCF4C \ Output Compare Flag 4C
+ $04 constant TIFR4_OCF4B \ Output Compare Flag 4B
+ $02 constant TIFR4_OCF4A \ Output Compare Flag 4A
+ $01 constant TIFR4_TOV4 \ Timer/Counter4 Overflow Flag
+\ TIMER_COUNTER_3
+&144 constant TCCR3A \ Timer/Counter3 Control Register A
+ $C0 constant TCCR3A_COM3A \ Compare Output Mode 1A, bits
+ $30 constant TCCR3A_COM3B \ Compare Output Mode 3B, bits
+ $0C constant TCCR3A_COM3C \ Compare Output Mode 3C, bits
+ $03 constant TCCR3A_WGM3 \ Waveform Generation Mode
+&145 constant TCCR3B \ Timer/Counter3 Control Register B
+ $80 constant TCCR3B_ICNC3 \ Input Capture 3 Noise Canceler
+ $40 constant TCCR3B_ICES3 \ Input Capture 3 Edge Select
+ $18 constant TCCR3B_WGM3 \ Waveform Generation Mode
+ $07 constant TCCR3B_CS3 \ Prescaler source of Timer/Counter 3
+&146 constant TCCR3C \ Timer/Counter 3 Control Register C
+ $80 constant TCCR3C_FOC3A \ Force Output Compare 3A
+ $40 constant TCCR3C_FOC3B \ Force Output Compare 3B
+ $20 constant TCCR3C_FOC3C \ Force Output Compare 3C
+&148 constant TCNT3 \ Timer/Counter3 Bytes
+&152 constant OCR3A \ Timer/Counter3 Output Compare Register A Bytes
+&154 constant OCR3B \ Timer/Counter3 Output Compare Register B Bytes
+&156 constant OCR3C \ Timer/Counter3 Output Compare Register B Bytes
+&150 constant ICR3 \ Timer/Counter3 Input Capture Register Bytes
+&113 constant TIMSK3 \ Timer/Counter3 Interrupt Mask Register
+ $20 constant TIMSK3_ICIE3 \ Timer/Counter3 Input Capture Interrupt Enable
+ $08 constant TIMSK3_OCIE3C \ Timer/Counter3 Output Compare C Match Interrupt Enable
+ $04 constant TIMSK3_OCIE3B \ Timer/Counter3 Output Compare B Match Interrupt Enable
+ $02 constant TIMSK3_OCIE3A \ Timer/Counter3 Output Compare A Match Interrupt Enable
+ $01 constant TIMSK3_TOIE3 \ Timer/Counter3 Overflow Interrupt Enable
+&56 constant TIFR3 \ Timer/Counter3 Interrupt Flag register
+ $20 constant TIFR3_ICF3 \ Input Capture Flag 3
+ $08 constant TIFR3_OCF3C \ Output Compare Flag 3C
+ $04 constant TIFR3_OCF3B \ Output Compare Flag 3B
+ $02 constant TIFR3_OCF3A \ Output Compare Flag 3A
+ $01 constant TIFR3_TOV3 \ Timer/Counter3 Overflow Flag
+\ TIMER_COUNTER_1
+&128 constant TCCR1A \ Timer/Counter1 Control Register A
+ $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
+ $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
+ $0C constant TCCR1A_COM1C \ Compare Output Mode 1C, bits
+ $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
+&129 constant TCCR1B \ Timer/Counter1 Control Register B
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
+ $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
+&130 constant TCCR1C \ Timer/Counter 1 Control Register C
+ $80 constant TCCR1C_FOC1A \ Force Output Compare 1A
+ $40 constant TCCR1C_FOC1B \ Force Output Compare 1B
+ $20 constant TCCR1C_FOC1C \ Force Output Compare 1C
+&132 constant TCNT1 \ Timer/Counter1 Bytes
+&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
+&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
+&140 constant OCR1C \ Timer/Counter1 Output Compare Register C Bytes
+&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
+&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
+ $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
+ $08 constant TIMSK1_OCIE1C \ Timer/Counter1 Output Compare C Match Interrupt Enable
+ $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
+ $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
+ $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
+&54 constant TIFR1 \ Timer/Counter1 Interrupt Flag register
+ $20 constant TIFR1_ICF1 \ Input Capture Flag 1
+ $08 constant TIFR1_OCF1C \ Output Compare Flag 1C
+ $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
+ $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
+ $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
+\ JTAG
+&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
+&85 constant MCUCR \ MCU Control Register
+ $80 constant MCUCR_JTD \ JTAG Interface Disable
+&84 constant MCUSR \ MCU Status Register
+ $10 constant MCUSR_JTRF \ JTAG Reset Flag
+\ EXTERNAL_INTERRUPT
+&105 constant EICRA \ External Interrupt Control Register A
+ $C0 constant EICRA_ISC3 \ External Interrupt Sense Control Bit
+ $30 constant EICRA_ISC2 \ External Interrupt Sense Control Bit
+ $0C constant EICRA_ISC1 \ External Interrupt Sense Control Bit
+ $03 constant EICRA_ISC0 \ External Interrupt Sense Control Bit
+&106 constant EICRB \ External Interrupt Control Register B
+ $C0 constant EICRB_ISC7 \ External Interrupt 7-4 Sense Control Bit
+ $30 constant EICRB_ISC6 \ External Interrupt 7-4 Sense Control Bit
+ $0C constant EICRB_ISC5 \ External Interrupt 7-4 Sense Control Bit
+ $03 constant EICRB_ISC4 \ External Interrupt 7-4 Sense Control Bit
+&61 constant EIMSK \ External Interrupt Mask Register
+ $FF constant EIMSK_INT \ External Interrupt Request 7 Enable
+&60 constant EIFR \ External Interrupt Flag Register
+ $FF constant EIFR_INTF \ External Interrupt Flags
+&109 constant PCMSK2 \ Pin Change Mask Register 2
+&108 constant PCMSK1 \ Pin Change Mask Register 1
+&107 constant PCMSK0 \ Pin Change Mask Register 0
+&59 constant PCIFR \ Pin Change Interrupt Flag Register
+ $07 constant PCIFR_PCIF \ Pin Change Interrupt Flags
+&104 constant PCICR \ Pin Change Interrupt Control Register
+ $07 constant PCICR_PCIE \ Pin Change Interrupt Enables
+\ CPU
+&95 constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ $08 constant SREG_V \ Two's Complement Overflow Flag
+ $04 constant SREG_N \ Negative Flag
+ $02 constant SREG_Z \ Zero Flag
+ $01 constant SREG_C \ Carry Flag
+&93 constant SP \ Stack Pointer
+&116 constant XMCRA \ External Memory Control Register A
+ $80 constant XMCRA_SRE \ External SRAM Enable
+ $70 constant XMCRA_SRL \ Wait state page limit
+ $0C constant XMCRA_SRW1 \ Wait state select bit upper page
+ $03 constant XMCRA_SRW0 \ Wait state select bit lower page
+&117 constant XMCRB \ External Memory Control Register B
+ $80 constant XMCRB_XMBK \ External Memory Bus Keeper Enable
+ $07 constant XMCRB_XMM \ External Memory High Mask
+&102 constant OSCCAL \ Oscillator Calibration Value
+&97 constant CLKPR \
+ $80 constant CLKPR_CLKPCE \
+ $0F constant CLKPR_CLKPS \
+&83 constant SMCR \ Sleep Mode Control Register
+ $0E constant SMCR_SM \ Sleep Mode Select bits
+ $01 constant SMCR_SE \ Sleep Enable
+&92 constant EIND \ Extended Indirect Register
+&91 constant RAMPZ \ RAM Page Z Select Register
+&75 constant GPIOR2 \ General Purpose IO Register 2
+ $FF constant GPIOR2_GPIOR \ General Purpose IO Register 2 bis
+&74 constant GPIOR1 \ General Purpose IO Register 1
+ $FF constant GPIOR1_GPIOR \ General Purpose IO Register 1 bis
+&62 constant GPIOR0 \ General Purpose IO Register 0
+ $80 constant GPIOR0_GPIOR07 \ General Purpose IO Register 0 bit 7
+ $40 constant GPIOR0_GPIOR06 \ General Purpose IO Register 0 bit 6
+ $20 constant GPIOR0_GPIOR05 \ General Purpose IO Register 0 bit 5
+ $10 constant GPIOR0_GPIOR04 \ General Purpose IO Register 0 bit 4
+ $08 constant GPIOR0_GPIOR03 \ General Purpose IO Register 0 bit 3
+ $04 constant GPIOR0_GPIOR02 \ General Purpose IO Register 0 bit 2
+ $02 constant GPIOR0_GPIOR01 \ General Purpose IO Register 0 bit 1
+ $01 constant GPIOR0_GPIOR00 \ General Purpose IO Register 0 bit 0
+&101 constant PRR1 \ Power Reduction Register1
+ $20 constant PRR1_PRTIM5 \ Power Reduction Timer/Counter5
+ $10 constant PRR1_PRTIM4 \ Power Reduction Timer/Counter4
+ $08 constant PRR1_PRTIM3 \ Power Reduction Timer/Counter3
+ $07 constant PRR1_PRUSART \ Power Reduction USART3
+&100 constant PRR0 \ Power Reduction Register0
+ $80 constant PRR0_PRTWI \ Power Reduction TWI
+ $40 constant PRR0_PRTIM2 \ Power Reduction Timer/Counter2
+ $20 constant PRR0_PRTIM0 \ Power Reduction Timer/Counter0
+ $08 constant PRR0_PRTIM1 \ Power Reduction Timer/Counter1
+ $04 constant PRR0_PRSPI \ Power Reduction Serial Peripheral Interface
+ $02 constant PRR0_PRUSART0 \ Power Reduction USART
+ $01 constant PRR0_PRADC \ Power Reduction ADC
+\ AD_CONVERTER
+&124 constant ADMUX \ The ADC multiplexer Selection Register
+ $C0 constant ADMUX_REFS \ Reference Selection Bits
+ $20 constant ADMUX_ADLAR \ Left Adjust Result
+ $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
+&120 constant ADC \ ADC Data Register Bytes
+&122 constant ADCSRA \ The ADC Control and Status register A
+ $80 constant ADCSRA_ADEN \ ADC Enable
+ $40 constant ADCSRA_ADSC \ ADC Start Conversion
+ $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
+ $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
+ $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
+ $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
+&125 constant DIDR2 \ Digital Input Disable Register
+ $80 constant DIDR2_ADC15D \
+ $40 constant DIDR2_ADC14D \
+ $20 constant DIDR2_ADC13D \
+ $10 constant DIDR2_ADC12D \
+ $08 constant DIDR2_ADC11D \
+ $04 constant DIDR2_ADC10D \
+ $02 constant DIDR2_ADC9D \
+ $01 constant DIDR2_ADC8D \
+&126 constant DIDR0 \ Digital Input Disable Register
+ $80 constant DIDR0_ADC7D \
+ $40 constant DIDR0_ADC6D \
+ $20 constant DIDR0_ADC5D \
+ $10 constant DIDR0_ADC4D \
+ $08 constant DIDR0_ADC3D \
+ $04 constant DIDR0_ADC2D \
+ $02 constant DIDR0_ADC1D \
+ $01 constant DIDR0_ADC0D \
+\ BOOT_LOAD
+&87 constant SPMCSR \ Store Program Memory Control Register
+ $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
+ $20 constant SPMCSR_SIGRD \ Signature Row Read
+ $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
+ $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
+ $04 constant SPMCSR_PGWRT \ Page Write
+ $02 constant SPMCSR_PGERS \ Page Erase
+ $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
+\ USART2
+&214 constant UDR2 \ USART I/O Data Register
+&208 constant UCSR2A \ USART Control and Status Register A
+ $80 constant UCSR2A_RXC2 \ USART Receive Complete
+ $40 constant UCSR2A_TXC2 \ USART Transmitt Complete
+ $20 constant UCSR2A_UDRE2 \ USART Data Register Empty
+ $10 constant UCSR2A_FE2 \ Framing Error
+ $08 constant UCSR2A_DOR2 \ Data overRun
+ $04 constant UCSR2A_UPE2 \ Parity Error
+ $02 constant UCSR2A_U2X2 \ Double the USART transmission speed
+ $01 constant UCSR2A_MPCM2 \ Multi-processor Communication Mode
+&209 constant UCSR2B \ USART Control and Status Register B
+ $80 constant UCSR2B_RXCIE2 \ RX Complete Interrupt Enable
+ $40 constant UCSR2B_TXCIE2 \ TX Complete Interrupt Enable
+ $20 constant UCSR2B_UDRIE2 \ USART Data register Empty Interrupt Enable
+ $10 constant UCSR2B_RXEN2 \ Receiver Enable
+ $08 constant UCSR2B_TXEN2 \ Transmitter Enable
+ $04 constant UCSR2B_UCSZ22 \ Character Size
+ $02 constant UCSR2B_RXB82 \ Receive Data Bit 8
+ $01 constant UCSR2B_TXB82 \ Transmit Data Bit 8
+&210 constant UCSR2C \ USART Control and Status Register C
+ $C0 constant UCSR2C_UMSEL2 \ USART Mode Select
+ $30 constant UCSR2C_UPM2 \ Parity Mode Bits
+ $08 constant UCSR2C_USBS2 \ Stop Bit Select
+ $06 constant UCSR2C_UCSZ2 \ Character Size
+ $01 constant UCSR2C_UCPOL2 \ Clock Polarity
+&212 constant UBRR2 \ USART Baud Rate Register Bytes
+\ USART3
+&310 constant UDR3 \ USART I/O Data Register
+&304 constant UCSR3A \ USART Control and Status Register A
+ $80 constant UCSR3A_RXC3 \ USART Receive Complete
+ $40 constant UCSR3A_TXC3 \ USART Transmitt Complete
+ $20 constant UCSR3A_UDRE3 \ USART Data Register Empty
+ $10 constant UCSR3A_FE3 \ Framing Error
+ $08 constant UCSR3A_DOR3 \ Data overRun
+ $04 constant UCSR3A_UPE3 \ Parity Error
+ $02 constant UCSR3A_U2X3 \ Double the USART transmission speed
+ $01 constant UCSR3A_MPCM3 \ Multi-processor Communication Mode
+&305 constant UCSR3B \ USART Control and Status Register B
+ $80 constant UCSR3B_RXCIE3 \ RX Complete Interrupt Enable
+ $40 constant UCSR3B_TXCIE3 \ TX Complete Interrupt Enable
+ $20 constant UCSR3B_UDRIE3 \ USART Data register Empty Interrupt Enable
+ $10 constant UCSR3B_RXEN3 \ Receiver Enable
+ $08 constant UCSR3B_TXEN3 \ Transmitter Enable
+ $04 constant UCSR3B_UCSZ32 \ Character Size
+ $02 constant UCSR3B_RXB83 \ Receive Data Bit 8
+ $01 constant UCSR3B_TXB83 \ Transmit Data Bit 8
+&306 constant UCSR3C \ USART Control and Status Register C
+ $C0 constant UCSR3C_UMSEL3 \ USART Mode Select
+ $30 constant UCSR3C_UPM3 \ Parity Mode Bits
+ $08 constant UCSR3C_USBS3 \ Stop Bit Select
+ $06 constant UCSR3C_UCSZ3 \ Character Size
+ $01 constant UCSR3C_UCPOL3 \ Clock Polarity
+&308 constant UBRR3 \ USART Baud Rate Register Bytes
+
+\ Interrupts
+&2 constant INT0Addr \ External Interrupt Request 0
+&4 constant INT1Addr \ External Interrupt Request 1
+&6 constant INT2Addr \ External Interrupt Request 2
+&8 constant INT3Addr \ External Interrupt Request 3
+&10 constant INT4Addr \ External Interrupt Request 4
+&12 constant INT5Addr \ External Interrupt Request 5
+&14 constant INT6Addr \ External Interrupt Request 6
+&16 constant INT7Addr \ External Interrupt Request 7
+&18 constant PCINT0Addr \ Pin Change Interrupt Request 0
+&20 constant PCINT1Addr \ Pin Change Interrupt Request 1
+&22 constant PCINT2Addr \ Pin Change Interrupt Request 2
+&24 constant WDTAddr \ Watchdog Time-out Interrupt
+&26 constant TIMER2_COMPAAddr \ Timer/Counter2 Compare Match A
+&28 constant TIMER2_COMPBAddr \ Timer/Counter2 Compare Match B
+&30 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
+&32 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+&34 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
+&36 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
+&38 constant TIMER1_COMPCAddr \ Timer/Counter1 Compare Match C
+&40 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+&42 constant TIMER0_COMPAAddr \ Timer/Counter0 Compare Match A
+&44 constant TIMER0_COMPBAddr \ Timer/Counter0 Compare Match B
+&46 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
+&48 constant SPI__STCAddr \ SPI Serial Transfer Complete
+&50 constant USART0__RXAddr \ USART0, Rx Complete
+&52 constant USART0__UDREAddr \ USART0 Data register Empty
+&54 constant USART0__TXAddr \ USART0, Tx Complete
+&56 constant ANALOG_COMPAddr \ Analog Comparator
+&58 constant ADCAddr \ ADC Conversion Complete
+&60 constant EE_READYAddr \ EEPROM Ready
+&62 constant TIMER3_CAPTAddr \ Timer/Counter3 Capture Event
+&64 constant TIMER3_COMPAAddr \ Timer/Counter3 Compare Match A
+&66 constant TIMER3_COMPBAddr \ Timer/Counter3 Compare Match B
+&68 constant TIMER3_COMPCAddr \ Timer/Counter3 Compare Match C
+&70 constant TIMER3_OVFAddr \ Timer/Counter3 Overflow
+&72 constant USART1__RXAddr \ USART1, Rx Complete
+&74 constant USART1__UDREAddr \ USART1 Data register Empty
+&76 constant USART1__TXAddr \ USART1, Tx Complete
+&78 constant TWIAddr \ 2-wire Serial Interface
+&80 constant SPM_READYAddr \ Store Program Memory Read
+&82 constant TIMER4_CAPTAddr \ Timer/Counter4 Capture Event
+&84 constant TIMER4_COMPAAddr \ Timer/Counter4 Compare Match A
+&86 constant TIMER4_COMPBAddr \ Timer/Counter4 Compare Match B
+&88 constant TIMER4_COMPCAddr \ Timer/Counter4 Compare Match C
+&90 constant TIMER4_OVFAddr \ Timer/Counter4 Overflow
+&92 constant TIMER5_CAPTAddr \ Timer/Counter5 Capture Event
+&94 constant TIMER5_COMPAAddr \ Timer/Counter5 Compare Match A
+&96 constant TIMER5_COMPBAddr \ Timer/Counter5 Compare Match B
+&98 constant TIMER5_COMPCAddr \ Timer/Counter5 Compare Match C
+&100 constant TIMER5_OVFAddr \ Timer/Counter5 Overflow
+&102 constant USART2__RXAddr \ USART2, Rx Complete
+&104 constant USART2__UDREAddr \ USART2 Data register Empty
+&106 constant USART2__TXAddr \ USART2, Tx Complete
+&108 constant USART3__RXAddr \ USART3, Rx Complete
+&110 constant USART3__UDREAddr \ USART3 Data register Empty
+&112 constant USART3__TXAddr \ USART3, Tx Complete
diff --git a/amforth-6.5/avr8/devices/atmega1280/device.asm b/amforth-6.5/avr8/devices/atmega1280/device.asm
new file mode 100644
index 0000000..c30b89b
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega1280/device.asm
@@ -0,0 +1,190 @@
+; Partname: ATmega1280
+; generated automatically, do not edit
+
+.nolist
+ .include "m1280def.inc"
+.list
+
+.equ ramstart = 512
+.equ CELLSIZE = 2
+.macro readflashcell
+ clr temp7
+ lsl zl
+ rol zh
+ rol temp7
+ out_ RAMPZ, temp7
+ elpm @0, Z+
+ elpm @1, Z+
+.endmacro
+.macro writeflashcell
+ clr temp7
+ lsl zl
+ rol zh
+ rol temp7
+ out_ RAMPZ, temp7
+.endmacro
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_USART0 = 0
+.set WANT_TWI = 0
+.set WANT_SPI = 0
+.set WANT_PORTA = 0
+.set WANT_PORTB = 0
+.set WANT_PORTC = 0
+.set WANT_PORTD = 0
+.set WANT_PORTE = 0
+.set WANT_PORTF = 0
+.set WANT_PORTG = 0
+.set WANT_PORTH = 0
+.set WANT_PORTJ = 0
+.set WANT_PORTK = 0
+.set WANT_PORTL = 0
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_TIMER_COUNTER_2 = 0
+.set WANT_WATCHDOG = 0
+.set WANT_USART1 = 0
+.set WANT_EEPROM = 0
+.set WANT_TIMER_COUNTER_5 = 0
+.set WANT_TIMER_COUNTER_4 = 0
+.set WANT_TIMER_COUNTER_3 = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_JTAG = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_CPU = 0
+.set WANT_AD_CONVERTER = 0
+.set WANT_BOOT_LOAD = 0
+.set WANT_USART2 = 0
+.set WANT_USART3 = 0
+.equ intvecsize = 2 ; please verify; flash size: 131072 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.org 2
+ rcall isr ; External Interrupt Request 0
+.org 4
+ rcall isr ; External Interrupt Request 1
+.org 6
+ rcall isr ; External Interrupt Request 2
+.org 8
+ rcall isr ; External Interrupt Request 3
+.org 10
+ rcall isr ; External Interrupt Request 4
+.org 12
+ rcall isr ; External Interrupt Request 5
+.org 14
+ rcall isr ; External Interrupt Request 6
+.org 16
+ rcall isr ; External Interrupt Request 7
+.org 18
+ rcall isr ; Pin Change Interrupt Request 0
+.org 20
+ rcall isr ; Pin Change Interrupt Request 1
+.org 22
+ rcall isr ; Pin Change Interrupt Request 2
+.org 24
+ rcall isr ; Watchdog Time-out Interrupt
+.org 26
+ rcall isr ; Timer/Counter2 Compare Match A
+.org 28
+ rcall isr ; Timer/Counter2 Compare Match B
+.org 30
+ rcall isr ; Timer/Counter2 Overflow
+.org 32
+ rcall isr ; Timer/Counter1 Capture Event
+.org 34
+ rcall isr ; Timer/Counter1 Compare Match A
+.org 36
+ rcall isr ; Timer/Counter1 Compare Match B
+.org 38
+ rcall isr ; Timer/Counter1 Compare Match C
+.org 40
+ rcall isr ; Timer/Counter1 Overflow
+.org 42
+ rcall isr ; Timer/Counter0 Compare Match A
+.org 44
+ rcall isr ; Timer/Counter0 Compare Match B
+.org 46
+ rcall isr ; Timer/Counter0 Overflow
+.org 48
+ rcall isr ; SPI Serial Transfer Complete
+.org 50
+ rcall isr ; USART0, Rx Complete
+.org 52
+ rcall isr ; USART0 Data register Empty
+.org 54
+ rcall isr ; USART0, Tx Complete
+.org 56
+ rcall isr ; Analog Comparator
+.org 58
+ rcall isr ; ADC Conversion Complete
+.org 60
+ rcall isr ; EEPROM Ready
+.org 62
+ rcall isr ; Timer/Counter3 Capture Event
+.org 64
+ rcall isr ; Timer/Counter3 Compare Match A
+.org 66
+ rcall isr ; Timer/Counter3 Compare Match B
+.org 68
+ rcall isr ; Timer/Counter3 Compare Match C
+.org 70
+ rcall isr ; Timer/Counter3 Overflow
+.org 72
+ rcall isr ; USART1, Rx Complete
+.org 74
+ rcall isr ; USART1 Data register Empty
+.org 76
+ rcall isr ; USART1, Tx Complete
+.org 78
+ rcall isr ; 2-wire Serial Interface
+.org 80
+ rcall isr ; Store Program Memory Read
+.org 82
+ rcall isr ; Timer/Counter4 Capture Event
+.org 84
+ rcall isr ; Timer/Counter4 Compare Match A
+.org 86
+ rcall isr ; Timer/Counter4 Compare Match B
+.org 88
+ rcall isr ; Timer/Counter4 Compare Match C
+.org 90
+ rcall isr ; Timer/Counter4 Overflow
+.org 92
+ rcall isr ; Timer/Counter5 Capture Event
+.org 94
+ rcall isr ; Timer/Counter5 Compare Match A
+.org 96
+ rcall isr ; Timer/Counter5 Compare Match B
+.org 98
+ rcall isr ; Timer/Counter5 Compare Match C
+.org 100
+ rcall isr ; Timer/Counter5 Overflow
+.org 102
+ rcall isr ; USART2, Rx Complete
+.org 104
+ rcall isr ; USART2 Data register Empty
+.org 106
+ rcall isr ; USART2, Tx Complete
+.org 108
+ rcall isr ; USART3, Rx Complete
+.org 110
+ rcall isr ; USART3 Data register Empty
+.org 112
+ rcall isr ; USART3, Tx Complete
+.equ INTVECTORS = 57
+.nooverlap
+
+; compatability layer (maybe empty)
+
+; controller data area, environment query mcu-info
+mcu_info:
+mcu_ramsize:
+ .dw 8192
+mcu_eepromsize:
+ .dw 4096
+mcu_maxdp:
+ .dw 65535
+mcu_numints:
+ .dw 57
+mcu_name:
+ .dw 10
+ .db "ATmega1280"
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega1280/device.inc b/amforth-6.5/avr8/devices/atmega1280/device.inc
new file mode 100644
index 0000000..48553d2
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega1280/device.inc
@@ -0,0 +1,1980 @@
+; Partname: ATmega1280
+; generated automatically, no not edit
+
+.if WANT_ANALOG_COMPARATOR == 1
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Control and Status Register B
+VE_ADCSRB:
+ .dw $ff06
+ .db "ADCSRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRB
+XT_ADCSRB:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRB:
+ .dw 123
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Control And Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw 80
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 1
+VE_DIDR1:
+ .dw $ff05
+ .db "DIDR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR1
+XT_DIDR1:
+ .dw PFA_DOVARIABLE
+PFA_DIDR1:
+ .dw 127
+
+.endif
+.if WANT_USART0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR0:
+ .dw $ff04
+ .db "UDR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR0
+XT_UDR0:
+ .dw PFA_DOVARIABLE
+PFA_UDR0:
+ .dw 198
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR0A:
+ .dw $ff06
+ .db "UCSR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0A
+XT_UCSR0A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0A:
+ .dw 192
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR0B:
+ .dw $ff06
+ .db "UCSR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0B
+XT_UCSR0B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0B:
+ .dw 193
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR0C:
+ .dw $ff06
+ .db "UCSR0C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0C
+XT_UCSR0C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0C:
+ .dw 194
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Bytes
+VE_UBRR0:
+ .dw $ff05
+ .db "UBRR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR0
+XT_UBRR0:
+ .dw PFA_DOVARIABLE
+PFA_UBRR0:
+ .dw 196
+
+.endif
+.if WANT_TWI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; TWI (Slave) Address Mask Register
+VE_TWAMR:
+ .dw $ff05
+ .db "TWAMR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWAMR
+XT_TWAMR:
+ .dw PFA_DOVARIABLE
+PFA_TWAMR:
+ .dw 189
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Bit Rate register
+VE_TWBR:
+ .dw $ff04
+ .db "TWBR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWBR
+XT_TWBR:
+ .dw PFA_DOVARIABLE
+PFA_TWBR:
+ .dw 184
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Control Register
+VE_TWCR:
+ .dw $ff04
+ .db "TWCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWCR
+XT_TWCR:
+ .dw PFA_DOVARIABLE
+PFA_TWCR:
+ .dw 188
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Status Register
+VE_TWSR:
+ .dw $ff04
+ .db "TWSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWSR
+XT_TWSR:
+ .dw PFA_DOVARIABLE
+PFA_TWSR:
+ .dw 185
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Data register
+VE_TWDR:
+ .dw $ff04
+ .db "TWDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWDR
+XT_TWDR:
+ .dw PFA_DOVARIABLE
+PFA_TWDR:
+ .dw 187
+; ( -- addr ) System Constant
+; R( -- )
+; TWI (Slave) Address register
+VE_TWAR:
+ .dw $ff04
+ .db "TWAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWAR
+XT_TWAR:
+ .dw PFA_DOVARIABLE
+PFA_TWAR:
+ .dw 186
+
+.endif
+.if WANT_SPI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR:
+ .dw $ff04
+ .db "SPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR
+XT_SPCR:
+ .dw PFA_DOVARIABLE
+PFA_SPCR:
+ .dw 76
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR:
+ .dw $ff04
+ .db "SPSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR
+XT_SPSR:
+ .dw PFA_DOVARIABLE
+PFA_SPSR:
+ .dw 77
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR:
+ .dw $ff04
+ .db "SPDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR
+XT_SPDR:
+ .dw PFA_DOVARIABLE
+PFA_SPDR:
+ .dw 78
+
+.endif
+.if WANT_PORTA == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Register
+VE_PORTA:
+ .dw $ff05
+ .db "PORTA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTA
+XT_PORTA:
+ .dw PFA_DOVARIABLE
+PFA_PORTA:
+ .dw 34
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Direction Register
+VE_DDRA:
+ .dw $ff04
+ .db "DDRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRA
+XT_DDRA:
+ .dw PFA_DOVARIABLE
+PFA_DDRA:
+ .dw 33
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Input Pins
+VE_PINA:
+ .dw $ff04
+ .db "PINA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINA
+XT_PINA:
+ .dw PFA_DOVARIABLE
+PFA_PINA:
+ .dw 32
+
+.endif
+.if WANT_PORTB == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw 37
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw 36
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw 35
+
+.endif
+.if WANT_PORTC == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Register
+VE_PORTC:
+ .dw $ff05
+ .db "PORTC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTC
+XT_PORTC:
+ .dw PFA_DOVARIABLE
+PFA_PORTC:
+ .dw 40
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Direction Register
+VE_DDRC:
+ .dw $ff04
+ .db "DDRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRC
+XT_DDRC:
+ .dw PFA_DOVARIABLE
+PFA_DDRC:
+ .dw 39
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Input Pins
+VE_PINC:
+ .dw $ff04
+ .db "PINC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINC
+XT_PINC:
+ .dw PFA_DOVARIABLE
+PFA_PINC:
+ .dw 38
+
+.endif
+.if WANT_PORTD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw 43
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw 42
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw 41
+
+.endif
+.if WANT_PORTE == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port E
+VE_PORTE:
+ .dw $ff05
+ .db "PORTE",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTE
+XT_PORTE:
+ .dw PFA_DOVARIABLE
+PFA_PORTE:
+ .dw 46
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port E
+VE_DDRE:
+ .dw $ff04
+ .db "DDRE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRE
+XT_DDRE:
+ .dw PFA_DOVARIABLE
+PFA_DDRE:
+ .dw 45
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port E
+VE_PINE:
+ .dw $ff04
+ .db "PINE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINE
+XT_PINE:
+ .dw PFA_DOVARIABLE
+PFA_PINE:
+ .dw 44
+
+.endif
+.if WANT_PORTF == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port F
+VE_PORTF:
+ .dw $ff05
+ .db "PORTF",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTF
+XT_PORTF:
+ .dw PFA_DOVARIABLE
+PFA_PORTF:
+ .dw 49
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port F
+VE_DDRF:
+ .dw $ff04
+ .db "DDRF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRF
+XT_DDRF:
+ .dw PFA_DOVARIABLE
+PFA_DDRF:
+ .dw 48
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port F
+VE_PINF:
+ .dw $ff04
+ .db "PINF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINF
+XT_PINF:
+ .dw PFA_DOVARIABLE
+PFA_PINF:
+ .dw 47
+
+.endif
+.if WANT_PORTG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port G
+VE_PORTG:
+ .dw $ff05
+ .db "PORTG",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTG
+XT_PORTG:
+ .dw PFA_DOVARIABLE
+PFA_PORTG:
+ .dw 52
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port G
+VE_DDRG:
+ .dw $ff04
+ .db "DDRG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRG
+XT_DDRG:
+ .dw PFA_DOVARIABLE
+PFA_DDRG:
+ .dw 51
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port G
+VE_PING:
+ .dw $ff04
+ .db "PING"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PING
+XT_PING:
+ .dw PFA_DOVARIABLE
+PFA_PING:
+ .dw 50
+
+.endif
+.if WANT_PORTH == 1
+; ( -- addr ) System Constant
+; R( -- )
+; PORT H Data Register
+VE_PORTH:
+ .dw $ff05
+ .db "PORTH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTH
+XT_PORTH:
+ .dw PFA_DOVARIABLE
+PFA_PORTH:
+ .dw 258
+; ( -- addr ) System Constant
+; R( -- )
+; PORT H Data Direction Register
+VE_DDRH:
+ .dw $ff04
+ .db "DDRH"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRH
+XT_DDRH:
+ .dw PFA_DOVARIABLE
+PFA_DDRH:
+ .dw 257
+; ( -- addr ) System Constant
+; R( -- )
+; PORT H Input Pins
+VE_PINH:
+ .dw $ff04
+ .db "PINH"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINH
+XT_PINH:
+ .dw PFA_DOVARIABLE
+PFA_PINH:
+ .dw 256
+
+.endif
+.if WANT_PORTJ == 1
+; ( -- addr ) System Constant
+; R( -- )
+; PORT J Data Register
+VE_PORTJ:
+ .dw $ff05
+ .db "PORTJ",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTJ
+XT_PORTJ:
+ .dw PFA_DOVARIABLE
+PFA_PORTJ:
+ .dw 261
+; ( -- addr ) System Constant
+; R( -- )
+; PORT J Data Direction Register
+VE_DDRJ:
+ .dw $ff04
+ .db "DDRJ"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRJ
+XT_DDRJ:
+ .dw PFA_DOVARIABLE
+PFA_DDRJ:
+ .dw 260
+; ( -- addr ) System Constant
+; R( -- )
+; PORT J Input Pins
+VE_PINJ:
+ .dw $ff04
+ .db "PINJ"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINJ
+XT_PINJ:
+ .dw PFA_DOVARIABLE
+PFA_PINJ:
+ .dw 259
+
+.endif
+.if WANT_PORTK == 1
+; ( -- addr ) System Constant
+; R( -- )
+; PORT K Data Register
+VE_PORTK:
+ .dw $ff05
+ .db "PORTK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTK
+XT_PORTK:
+ .dw PFA_DOVARIABLE
+PFA_PORTK:
+ .dw 264
+; ( -- addr ) System Constant
+; R( -- )
+; PORT K Data Direction Register
+VE_DDRK:
+ .dw $ff04
+ .db "DDRK"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRK
+XT_DDRK:
+ .dw PFA_DOVARIABLE
+PFA_DDRK:
+ .dw 263
+; ( -- addr ) System Constant
+; R( -- )
+; PORT K Input Pins
+VE_PINK:
+ .dw $ff04
+ .db "PINK"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINK
+XT_PINK:
+ .dw PFA_DOVARIABLE
+PFA_PINK:
+ .dw 262
+
+.endif
+.if WANT_PORTL == 1
+; ( -- addr ) System Constant
+; R( -- )
+; PORT L Data Register
+VE_PORTL:
+ .dw $ff05
+ .db "PORTL",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTL
+XT_PORTL:
+ .dw PFA_DOVARIABLE
+PFA_PORTL:
+ .dw 267
+; ( -- addr ) System Constant
+; R( -- )
+; PORT L Data Direction Register
+VE_DDRL:
+ .dw $ff04
+ .db "DDRL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRL
+XT_DDRL:
+ .dw PFA_DOVARIABLE
+PFA_DDRL:
+ .dw 266
+; ( -- addr ) System Constant
+; R( -- )
+; PORT L Input Pins
+VE_PINL:
+ .dw $ff04
+ .db "PINL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINL
+XT_PINL:
+ .dw PFA_DOVARIABLE
+PFA_PINL:
+ .dw 265
+
+.endif
+.if WANT_TIMER_COUNTER_0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0B:
+ .dw $ff05
+ .db "OCR0B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0B
+XT_OCR0B:
+ .dw PFA_DOVARIABLE
+PFA_OCR0B:
+ .dw 72
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0A:
+ .dw $ff05
+ .db "OCR0A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0A
+XT_OCR0A:
+ .dw PFA_DOVARIABLE
+PFA_OCR0A:
+ .dw 71
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw 70
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register B
+VE_TCCR0B:
+ .dw $ff06
+ .db "TCCR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0B
+XT_TCCR0B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0B:
+ .dw 69
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register A
+VE_TCCR0A:
+ .dw $ff06
+ .db "TCCR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0A
+XT_TCCR0A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0A:
+ .dw 68
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Mask Register
+VE_TIMSK0:
+ .dw $ff06
+ .db "TIMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK0
+XT_TIMSK0:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK0:
+ .dw 110
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Flag register
+VE_TIFR0:
+ .dw $ff05
+ .db "TIFR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR0
+XT_TIFR0:
+ .dw PFA_DOVARIABLE
+PFA_TIFR0:
+ .dw 53
+; ( -- addr ) System Constant
+; R( -- )
+; General Timer/Counter Control Register
+VE_GTCCR:
+ .dw $ff05
+ .db "GTCCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GTCCR
+XT_GTCCR:
+ .dw PFA_DOVARIABLE
+PFA_GTCCR:
+ .dw 67
+
+.endif
+.if WANT_TIMER_COUNTER_2 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Mask register
+VE_TIMSK2:
+ .dw $ff06
+ .db "TIMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK2
+XT_TIMSK2:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK2:
+ .dw 112
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Flag Register
+VE_TIFR2:
+ .dw $ff05
+ .db "TIFR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR2
+XT_TIFR2:
+ .dw PFA_DOVARIABLE
+PFA_TIFR2:
+ .dw 55
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register A
+VE_TCCR2A:
+ .dw $ff06
+ .db "TCCR2A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2A
+XT_TCCR2A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2A:
+ .dw 176
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register B
+VE_TCCR2B:
+ .dw $ff06
+ .db "TCCR2B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2B
+XT_TCCR2B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2B:
+ .dw 177
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2
+VE_TCNT2:
+ .dw $ff05
+ .db "TCNT2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT2
+XT_TCNT2:
+ .dw PFA_DOVARIABLE
+PFA_TCNT2:
+ .dw 178
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register B
+VE_OCR2B:
+ .dw $ff05
+ .db "OCR2B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2B
+XT_OCR2B:
+ .dw PFA_DOVARIABLE
+PFA_OCR2B:
+ .dw 180
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register A
+VE_OCR2A:
+ .dw $ff05
+ .db "OCR2A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2A
+XT_OCR2A:
+ .dw PFA_DOVARIABLE
+PFA_OCR2A:
+ .dw 179
+; ( -- addr ) System Constant
+; R( -- )
+; Asynchronous Status Register
+VE_ASSR:
+ .dw $ff04
+ .db "ASSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ASSR
+XT_ASSR:
+ .dw PFA_DOVARIABLE
+PFA_ASSR:
+ .dw 182
+
+.endif
+.if WANT_WATCHDOG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCSR:
+ .dw $ff06
+ .db "WDTCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCSR
+XT_WDTCSR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCSR:
+ .dw 96
+
+.endif
+.if WANT_USART1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR1:
+ .dw $ff04
+ .db "UDR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR1
+XT_UDR1:
+ .dw PFA_DOVARIABLE
+PFA_UDR1:
+ .dw 206
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR1A:
+ .dw $ff06
+ .db "UCSR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1A
+XT_UCSR1A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1A:
+ .dw 200
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR1B:
+ .dw $ff06
+ .db "UCSR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1B
+XT_UCSR1B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1B:
+ .dw 201
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR1C:
+ .dw $ff06
+ .db "UCSR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1C
+XT_UCSR1C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1C:
+ .dw 202
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Bytes
+VE_UBRR1:
+ .dw $ff05
+ .db "UBRR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR1
+XT_UBRR1:
+ .dw PFA_DOVARIABLE
+PFA_UBRR1:
+ .dw 204
+
+.endif
+.if WANT_EEPROM == 1
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Address Register Low Bytes
+VE_EEAR:
+ .dw $ff04
+ .db "EEAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEAR
+XT_EEAR:
+ .dw PFA_DOVARIABLE
+PFA_EEAR:
+ .dw 65
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw 64
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw 63
+
+.endif
+.if WANT_TIMER_COUNTER_5 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter5 Control Register A
+VE_TCCR5A:
+ .dw $ff06
+ .db "TCCR5A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR5A
+XT_TCCR5A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR5A:
+ .dw 288
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter5 Control Register B
+VE_TCCR5B:
+ .dw $ff06
+ .db "TCCR5B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR5B
+XT_TCCR5B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR5B:
+ .dw 289
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter 5 Control Register C
+VE_TCCR5C:
+ .dw $ff06
+ .db "TCCR5C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR5C
+XT_TCCR5C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR5C:
+ .dw 290
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter5 Bytes
+VE_TCNT5:
+ .dw $ff05
+ .db "TCNT5",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT5
+XT_TCNT5:
+ .dw PFA_DOVARIABLE
+PFA_TCNT5:
+ .dw 292
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter5 Output Compare Register A Bytes
+VE_OCR5A:
+ .dw $ff05
+ .db "OCR5A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR5A
+XT_OCR5A:
+ .dw PFA_DOVARIABLE
+PFA_OCR5A:
+ .dw 296
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter5 Output Compare Register B Bytes
+VE_OCR5B:
+ .dw $ff05
+ .db "OCR5B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR5B
+XT_OCR5B:
+ .dw PFA_DOVARIABLE
+PFA_OCR5B:
+ .dw 298
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter5 Output Compare Register B Bytes
+VE_OCR5C:
+ .dw $ff05
+ .db "OCR5C",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR5C
+XT_OCR5C:
+ .dw PFA_DOVARIABLE
+PFA_OCR5C:
+ .dw 300
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter5 Input Capture Register Bytes
+VE_ICR5:
+ .dw $ff04
+ .db "ICR5"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR5
+XT_ICR5:
+ .dw PFA_DOVARIABLE
+PFA_ICR5:
+ .dw 294
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter5 Interrupt Mask Register
+VE_TIMSK5:
+ .dw $ff06
+ .db "TIMSK5"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK5
+XT_TIMSK5:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK5:
+ .dw 115
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter5 Interrupt Flag register
+VE_TIFR5:
+ .dw $ff05
+ .db "TIFR5",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR5
+XT_TIFR5:
+ .dw PFA_DOVARIABLE
+PFA_TIFR5:
+ .dw 58
+
+.endif
+.if WANT_TIMER_COUNTER_4 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter4 Control Register A
+VE_TCCR4A:
+ .dw $ff06
+ .db "TCCR4A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR4A
+XT_TCCR4A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR4A:
+ .dw 160
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter4 Control Register B
+VE_TCCR4B:
+ .dw $ff06
+ .db "TCCR4B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR4B
+XT_TCCR4B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR4B:
+ .dw 161
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter 4 Control Register C
+VE_TCCR4C:
+ .dw $ff06
+ .db "TCCR4C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR4C
+XT_TCCR4C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR4C:
+ .dw 162
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter4 Bytes
+VE_TCNT4:
+ .dw $ff05
+ .db "TCNT4",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT4
+XT_TCNT4:
+ .dw PFA_DOVARIABLE
+PFA_TCNT4:
+ .dw 164
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter4 Output Compare Register A Bytes
+VE_OCR4A:
+ .dw $ff05
+ .db "OCR4A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR4A
+XT_OCR4A:
+ .dw PFA_DOVARIABLE
+PFA_OCR4A:
+ .dw 168
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter4 Output Compare Register B Bytes
+VE_OCR4B:
+ .dw $ff05
+ .db "OCR4B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR4B
+XT_OCR4B:
+ .dw PFA_DOVARIABLE
+PFA_OCR4B:
+ .dw 170
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter4 Output Compare Register B Bytes
+VE_OCR4C:
+ .dw $ff05
+ .db "OCR4C",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR4C
+XT_OCR4C:
+ .dw PFA_DOVARIABLE
+PFA_OCR4C:
+ .dw 172
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter4 Input Capture Register Bytes
+VE_ICR4:
+ .dw $ff04
+ .db "ICR4"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR4
+XT_ICR4:
+ .dw PFA_DOVARIABLE
+PFA_ICR4:
+ .dw 166
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter4 Interrupt Mask Register
+VE_TIMSK4:
+ .dw $ff06
+ .db "TIMSK4"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK4
+XT_TIMSK4:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK4:
+ .dw 114
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter4 Interrupt Flag register
+VE_TIFR4:
+ .dw $ff05
+ .db "TIFR4",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR4
+XT_TIFR4:
+ .dw PFA_DOVARIABLE
+PFA_TIFR4:
+ .dw 57
+
+.endif
+.if WANT_TIMER_COUNTER_3 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Control Register A
+VE_TCCR3A:
+ .dw $ff06
+ .db "TCCR3A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR3A
+XT_TCCR3A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR3A:
+ .dw 144
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Control Register B
+VE_TCCR3B:
+ .dw $ff06
+ .db "TCCR3B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR3B
+XT_TCCR3B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR3B:
+ .dw 145
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter 3 Control Register C
+VE_TCCR3C:
+ .dw $ff06
+ .db "TCCR3C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR3C
+XT_TCCR3C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR3C:
+ .dw 146
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Bytes
+VE_TCNT3:
+ .dw $ff05
+ .db "TCNT3",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT3
+XT_TCNT3:
+ .dw PFA_DOVARIABLE
+PFA_TCNT3:
+ .dw 148
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Output Compare Register A Bytes
+VE_OCR3A:
+ .dw $ff05
+ .db "OCR3A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR3A
+XT_OCR3A:
+ .dw PFA_DOVARIABLE
+PFA_OCR3A:
+ .dw 152
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Output Compare Register B Bytes
+VE_OCR3B:
+ .dw $ff05
+ .db "OCR3B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR3B
+XT_OCR3B:
+ .dw PFA_DOVARIABLE
+PFA_OCR3B:
+ .dw 154
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Output Compare Register B Bytes
+VE_OCR3C:
+ .dw $ff05
+ .db "OCR3C",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR3C
+XT_OCR3C:
+ .dw PFA_DOVARIABLE
+PFA_OCR3C:
+ .dw 156
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Input Capture Register Bytes
+VE_ICR3:
+ .dw $ff04
+ .db "ICR3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR3
+XT_ICR3:
+ .dw PFA_DOVARIABLE
+PFA_ICR3:
+ .dw 150
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Interrupt Mask Register
+VE_TIMSK3:
+ .dw $ff06
+ .db "TIMSK3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK3
+XT_TIMSK3:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK3:
+ .dw 113
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Interrupt Flag register
+VE_TIFR3:
+ .dw $ff05
+ .db "TIFR3",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR3
+XT_TIFR3:
+ .dw PFA_DOVARIABLE
+PFA_TIFR3:
+ .dw 56
+
+.endif
+.if WANT_TIMER_COUNTER_1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw 128
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw 129
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter 1 Control Register C
+VE_TCCR1C:
+ .dw $ff06
+ .db "TCCR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1C
+XT_TCCR1C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1C:
+ .dw 130
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Bytes
+VE_TCNT1:
+ .dw $ff05
+ .db "TCNT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1
+XT_TCNT1:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1:
+ .dw 132
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register A Bytes
+VE_OCR1A:
+ .dw $ff05
+ .db "OCR1A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1A
+XT_OCR1A:
+ .dw PFA_DOVARIABLE
+PFA_OCR1A:
+ .dw 136
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register B Bytes
+VE_OCR1B:
+ .dw $ff05
+ .db "OCR1B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1B
+XT_OCR1B:
+ .dw PFA_DOVARIABLE
+PFA_OCR1B:
+ .dw 138
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register C Bytes
+VE_OCR1C:
+ .dw $ff05
+ .db "OCR1C",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1C
+XT_OCR1C:
+ .dw PFA_DOVARIABLE
+PFA_OCR1C:
+ .dw 140
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Bytes
+VE_ICR1:
+ .dw $ff04
+ .db "ICR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1
+XT_ICR1:
+ .dw PFA_DOVARIABLE
+PFA_ICR1:
+ .dw 134
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Mask Register
+VE_TIMSK1:
+ .dw $ff06
+ .db "TIMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK1
+XT_TIMSK1:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK1:
+ .dw 111
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Flag register
+VE_TIFR1:
+ .dw $ff05
+ .db "TIFR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR1
+XT_TIFR1:
+ .dw PFA_DOVARIABLE
+PFA_TIFR1:
+ .dw 54
+
+.endif
+.if WANT_JTAG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; On-Chip Debug Related Register in I/O Memory
+VE_OCDR:
+ .dw $ff04
+ .db "OCDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCDR
+XT_OCDR:
+ .dw PFA_DOVARIABLE
+PFA_OCDR:
+ .dw 81
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw 85
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Status Register
+VE_MCUSR:
+ .dw $ff05
+ .db "MCUSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUSR
+XT_MCUSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUSR:
+ .dw 84
+
+.endif
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register A
+VE_EICRA:
+ .dw $ff05
+ .db "EICRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRA
+XT_EICRA:
+ .dw PFA_DOVARIABLE
+PFA_EICRA:
+ .dw 105
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register B
+VE_EICRB:
+ .dw $ff05
+ .db "EICRB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRB
+XT_EICRB:
+ .dw PFA_DOVARIABLE
+PFA_EICRB:
+ .dw 106
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Mask Register
+VE_EIMSK:
+ .dw $ff05
+ .db "EIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIMSK
+XT_EIMSK:
+ .dw PFA_DOVARIABLE
+PFA_EIMSK:
+ .dw 61
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Flag Register
+VE_EIFR:
+ .dw $ff04
+ .db "EIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIFR
+XT_EIFR:
+ .dw PFA_DOVARIABLE
+PFA_EIFR:
+ .dw 60
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 2
+VE_PCMSK2:
+ .dw $ff06
+ .db "PCMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK2
+XT_PCMSK2:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK2:
+ .dw 109
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 1
+VE_PCMSK1:
+ .dw $ff06
+ .db "PCMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK1
+XT_PCMSK1:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK1:
+ .dw 108
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 0
+VE_PCMSK0:
+ .dw $ff06
+ .db "PCMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK0
+XT_PCMSK0:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK0:
+ .dw 107
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Interrupt Flag Register
+VE_PCIFR:
+ .dw $ff05
+ .db "PCIFR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCIFR
+XT_PCIFR:
+ .dw PFA_DOVARIABLE
+PFA_PCIFR:
+ .dw 59
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Interrupt Control Register
+VE_PCICR:
+ .dw $ff05
+ .db "PCICR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCICR
+XT_PCICR:
+ .dw PFA_DOVARIABLE
+PFA_PCICR:
+ .dw 104
+
+.endif
+.if WANT_CPU == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw 95
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer
+VE_SP:
+ .dw $ff02
+ .db "SP"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SP
+XT_SP:
+ .dw PFA_DOVARIABLE
+PFA_SP:
+ .dw 93
+; ( -- addr ) System Constant
+; R( -- )
+; External Memory Control Register A
+VE_XMCRA:
+ .dw $ff05
+ .db "XMCRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_XMCRA
+XT_XMCRA:
+ .dw PFA_DOVARIABLE
+PFA_XMCRA:
+ .dw 116
+; ( -- addr ) System Constant
+; R( -- )
+; External Memory Control Register B
+VE_XMCRB:
+ .dw $ff05
+ .db "XMCRB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_XMCRB
+XT_XMCRB:
+ .dw PFA_DOVARIABLE
+PFA_XMCRB:
+ .dw 117
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Calibration Value
+VE_OSCCAL:
+ .dw $ff06
+ .db "OSCCAL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSCCAL
+XT_OSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_OSCCAL:
+ .dw 102
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_CLKPR:
+ .dw $ff05
+ .db "CLKPR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKPR
+XT_CLKPR:
+ .dw PFA_DOVARIABLE
+PFA_CLKPR:
+ .dw 97
+; ( -- addr ) System Constant
+; R( -- )
+; Sleep Mode Control Register
+VE_SMCR:
+ .dw $ff04
+ .db "SMCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SMCR
+XT_SMCR:
+ .dw PFA_DOVARIABLE
+PFA_SMCR:
+ .dw 83
+; ( -- addr ) System Constant
+; R( -- )
+; Extended Indirect Register
+VE_EIND:
+ .dw $ff04
+ .db "EIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIND
+XT_EIND:
+ .dw PFA_DOVARIABLE
+PFA_EIND:
+ .dw 92
+; ( -- addr ) System Constant
+; R( -- )
+; RAM Page Z Select Register
+VE_RAMPZ:
+ .dw $ff05
+ .db "RAMPZ",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_RAMPZ
+XT_RAMPZ:
+ .dw PFA_DOVARIABLE
+PFA_RAMPZ:
+ .dw 91
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 2
+VE_GPIOR2:
+ .dw $ff06
+ .db "GPIOR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR2
+XT_GPIOR2:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR2:
+ .dw 75
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 1
+VE_GPIOR1:
+ .dw $ff06
+ .db "GPIOR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR1
+XT_GPIOR1:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR1:
+ .dw 74
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 0
+VE_GPIOR0:
+ .dw $ff06
+ .db "GPIOR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR0
+XT_GPIOR0:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR0:
+ .dw 62
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register1
+VE_PRR1:
+ .dw $ff04
+ .db "PRR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR1
+XT_PRR1:
+ .dw PFA_DOVARIABLE
+PFA_PRR1:
+ .dw 101
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register0
+VE_PRR0:
+ .dw $ff04
+ .db "PRR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR0
+XT_PRR0:
+ .dw PFA_DOVARIABLE
+PFA_PRR0:
+ .dw 100
+
+.endif
+.if WANT_AD_CONVERTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC multiplexer Selection Register
+VE_ADMUX:
+ .dw $ff05
+ .db "ADMUX",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADMUX
+XT_ADMUX:
+ .dw PFA_DOVARIABLE
+PFA_ADMUX:
+ .dw 124
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register Bytes
+VE_ADC:
+ .dw $ff03
+ .db "ADC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADC
+XT_ADC:
+ .dw PFA_DOVARIABLE
+PFA_ADC:
+ .dw 120
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register A
+VE_ADCSRA:
+ .dw $ff06
+ .db "ADCSRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRA
+XT_ADCSRA:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRA:
+ .dw 122
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register
+VE_DIDR2:
+ .dw $ff05
+ .db "DIDR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR2
+XT_DIDR2:
+ .dw PFA_DOVARIABLE
+PFA_DIDR2:
+ .dw 125
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register
+VE_DIDR0:
+ .dw $ff05
+ .db "DIDR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR0
+XT_DIDR0:
+ .dw PFA_DOVARIABLE
+PFA_DIDR0:
+ .dw 126
+
+.endif
+.if WANT_BOOT_LOAD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control Register
+VE_SPMCSR:
+ .dw $ff06
+ .db "SPMCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCSR
+XT_SPMCSR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCSR:
+ .dw 87
+
+.endif
+.if WANT_USART2 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR2:
+ .dw $ff04
+ .db "UDR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR2
+XT_UDR2:
+ .dw PFA_DOVARIABLE
+PFA_UDR2:
+ .dw 214
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR2A:
+ .dw $ff06
+ .db "UCSR2A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR2A
+XT_UCSR2A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR2A:
+ .dw 208
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR2B:
+ .dw $ff06
+ .db "UCSR2B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR2B
+XT_UCSR2B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR2B:
+ .dw 209
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR2C:
+ .dw $ff06
+ .db "UCSR2C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR2C
+XT_UCSR2C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR2C:
+ .dw 210
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Bytes
+VE_UBRR2:
+ .dw $ff05
+ .db "UBRR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR2
+XT_UBRR2:
+ .dw PFA_DOVARIABLE
+PFA_UBRR2:
+ .dw 212
+
+.endif
+.if WANT_USART3 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR3:
+ .dw $ff04
+ .db "UDR3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR3
+XT_UDR3:
+ .dw PFA_DOVARIABLE
+PFA_UDR3:
+ .dw 310
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR3A:
+ .dw $ff06
+ .db "UCSR3A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR3A
+XT_UCSR3A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR3A:
+ .dw 304
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR3B:
+ .dw $ff06
+ .db "UCSR3B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR3B
+XT_UCSR3B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR3B:
+ .dw 305
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR3C:
+ .dw $ff06
+ .db "UCSR3C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR3C
+XT_UCSR3C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR3C:
+ .dw 306
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Bytes
+VE_UBRR3:
+ .dw $ff05
+ .db "UBRR3",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR3
+XT_UBRR3:
+ .dw PFA_DOVARIABLE
+PFA_UBRR3:
+ .dw 308
+
+.endif
diff --git a/amforth-6.5/avr8/devices/atmega1280/device.py b/amforth-6.5/avr8/devices/atmega1280/device.py
new file mode 100644
index 0000000..8750d77
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega1280/device.py
@@ -0,0 +1,633 @@
+# Generated Automatically
+
+# Partname ATmega1280
+
+MCUREGS = {
+# Interrupt Vectors
+ 'INT0Addr' : '#2', # External Interrupt Request 0
+ 'INT1Addr' : '#4', # External Interrupt Request 1
+ 'INT2Addr' : '#6', # External Interrupt Request 2
+ 'INT3Addr' : '#8', # External Interrupt Request 3
+ 'INT4Addr' : '#10', # External Interrupt Request 4
+ 'INT5Addr' : '#12', # External Interrupt Request 5
+ 'INT6Addr' : '#14', # External Interrupt Request 6
+ 'INT7Addr' : '#16', # External Interrupt Request 7
+ 'PCINT0Addr' : '#18', # Pin Change Interrupt Request 0
+ 'PCINT1Addr' : '#20', # Pin Change Interrupt Request 1
+ 'PCINT2Addr' : '#22', # Pin Change Interrupt Request 2
+ 'WDTAddr' : '#24', # Watchdog Time-out Interrupt
+ 'TIMER2_COMPAAddr' : '#26', # Timer/Counter2 Compare Match A
+ 'TIMER2_COMPBAddr' : '#28', # Timer/Counter2 Compare Match B
+ 'TIMER2_OVFAddr' : '#30', # Timer/Counter2 Overflow
+ 'TIMER1_CAPTAddr' : '#32', # Timer/Counter1 Capture Event
+ 'TIMER1_COMPAAddr' : '#34', # Timer/Counter1 Compare Match A
+ 'TIMER1_COMPBAddr' : '#36', # Timer/Counter1 Compare Match B
+ 'TIMER1_COMPCAddr' : '#38', # Timer/Counter1 Compare Match C
+ 'TIMER1_OVFAddr' : '#40', # Timer/Counter1 Overflow
+ 'TIMER0_COMPAAddr' : '#42', # Timer/Counter0 Compare Match A
+ 'TIMER0_COMPBAddr' : '#44', # Timer/Counter0 Compare Match B
+ 'TIMER0_OVFAddr' : '#46', # Timer/Counter0 Overflow
+ 'SPI_STCAddr' : '#48', # SPI Serial Transfer Complete
+ 'USART0_RXAddr' : '#50', # USART0, Rx Complete
+ 'USART0_UDREAddr' : '#52', # USART0 Data register Empty
+ 'USART0_TXAddr' : '#54', # USART0, Tx Complete
+ 'ANALOG_COMPAddr' : '#56', # Analog Comparator
+ 'ADCAddr' : '#58', # ADC Conversion Complete
+ 'EE_READYAddr' : '#60', # EEPROM Ready
+ 'TIMER3_CAPTAddr' : '#62', # Timer/Counter3 Capture Event
+ 'TIMER3_COMPAAddr' : '#64', # Timer/Counter3 Compare Match A
+ 'TIMER3_COMPBAddr' : '#66', # Timer/Counter3 Compare Match B
+ 'TIMER3_COMPCAddr' : '#68', # Timer/Counter3 Compare Match C
+ 'TIMER3_OVFAddr' : '#70', # Timer/Counter3 Overflow
+ 'USART1_RXAddr' : '#72', # USART1, Rx Complete
+ 'USART1_UDREAddr' : '#74', # USART1 Data register Empty
+ 'USART1_TXAddr' : '#76', # USART1, Tx Complete
+ 'TWIAddr' : '#78', # 2-wire Serial Interface
+ 'SPM_READYAddr' : '#80', # Store Program Memory Read
+ 'TIMER4_CAPTAddr' : '#82', # Timer/Counter4 Capture Event
+ 'TIMER4_COMPAAddr' : '#84', # Timer/Counter4 Compare Match A
+ 'TIMER4_COMPBAddr' : '#86', # Timer/Counter4 Compare Match B
+ 'TIMER4_COMPCAddr' : '#88', # Timer/Counter4 Compare Match C
+ 'TIMER4_OVFAddr' : '#90', # Timer/Counter4 Overflow
+ 'TIMER5_CAPTAddr' : '#92', # Timer/Counter5 Capture Event
+ 'TIMER5_COMPAAddr' : '#94', # Timer/Counter5 Compare Match A
+ 'TIMER5_COMPBAddr' : '#96', # Timer/Counter5 Compare Match B
+ 'TIMER5_COMPCAddr' : '#98', # Timer/Counter5 Compare Match C
+ 'TIMER5_OVFAddr' : '#100', # Timer/Counter5 Overflow
+ 'USART2_RXAddr' : '#102', # USART2, Rx Complete
+ 'USART2_UDREAddr' : '#104', # USART2 Data register Empty
+ 'USART2_TXAddr' : '#106', # USART2, Tx Complete
+ 'USART3_RXAddr' : '#108', # USART3, Rx Complete
+ 'USART3_UDREAddr' : '#110', # USART3 Data register Empty
+ 'USART3_TXAddr' : '#112', # USART3, Tx Complete
+
+# Module ANALOG_COMPARATOR
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
+ 'ACSR' : '$50', # Analog Comparator Control And
+ 'ACSR_ACD': '$80', # Analog Comparator Disable
+ 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
+ 'ACSR_ACO': '$20', # Analog Compare Output
+ 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
+ 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
+ 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
+ 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
+ 'DIDR1' : '$7f', # Digital Input Disable Register
+ 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
+ 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
+
+# Module USART0
+ 'UDR0' : '$c6', # USART I/O Data Register
+ 'UCSR0A' : '$c0', # USART Control and Status Regis
+ 'UCSR0A_RXC0': '$80', # USART Receive Complete
+ 'UCSR0A_TXC0': '$40', # USART Transmitt Complete
+ 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
+ 'UCSR0A_FE0': '$10', # Framing Error
+ 'UCSR0A_DOR0': '$8', # Data overRun
+ 'UCSR0A_UPE0': '$4', # Parity Error
+ 'UCSR0A_U2X0': '$2', # Double the USART transmission
+ 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
+ 'UCSR0B' : '$c1', # USART Control and Status Regis
+ 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
+ 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
+ 'UCSR0B_UDRIE0': '$20', # USART Data register Empty Inte
+ 'UCSR0B_RXEN0': '$10', # Receiver Enable
+ 'UCSR0B_TXEN0': '$8', # Transmitter Enable
+ 'UCSR0B_UCSZ02': '$4', # Character Size
+ 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
+ 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
+ 'UCSR0C' : '$c2', # USART Control and Status Regis
+ 'UCSR0C_UMSEL0': '$c0', # USART Mode Select
+ 'UCSR0C_UPM0': '$30', # Parity Mode Bits
+ 'UCSR0C_USBS0': '$8', # Stop Bit Select
+ 'UCSR0C_UCSZ0': '$6', # Character Size
+ 'UCSR0C_UCPOL0': '$1', # Clock Polarity
+ 'UBRR0' : '$c4', # USART Baud Rate Register Byte
+
+# Module TWI
+ 'TWAMR' : '$bd', # TWI (Slave) Address Mask Regis
+ 'TWAMR_TWAM': '$fe', #
+ 'TWBR' : '$b8', # TWI Bit Rate register
+ 'TWCR' : '$bc', # TWI Control Register
+ 'TWCR_TWINT': '$80', # TWI Interrupt Flag
+ 'TWCR_TWEA': '$40', # TWI Enable Acknowledge Bit
+ 'TWCR_TWSTA': '$20', # TWI Start Condition Bit
+ 'TWCR_TWSTO': '$10', # TWI Stop Condition Bit
+ 'TWCR_TWWC': '$8', # TWI Write Collition Flag
+ 'TWCR_TWEN': '$4', # TWI Enable Bit
+ 'TWCR_TWIE': '$1', # TWI Interrupt Enable
+ 'TWSR' : '$b9', # TWI Status Register
+ 'TWSR_TWS': '$f8', # TWI Status
+ 'TWSR_TWPS': '$3', # TWI Prescaler
+ 'TWDR' : '$bb', # TWI Data register
+ 'TWAR' : '$ba', # TWI (Slave) Address register
+ 'TWAR_TWA': '$fe', # TWI (Slave) Address register B
+ 'TWAR_TWGCE': '$1', # TWI General Call Recognition E
+
+# Module SPI
+ 'SPCR' : '$4c', # SPI Control Register
+ 'SPCR_SPIE': '$80', # SPI Interrupt Enable
+ 'SPCR_SPE': '$40', # SPI Enable
+ 'SPCR_DORD': '$20', # Data Order
+ 'SPCR_MSTR': '$10', # Master/Slave Select
+ 'SPCR_CPOL': '$8', # Clock polarity
+ 'SPCR_CPHA': '$4', # Clock Phase
+ 'SPCR_SPR': '$3', # SPI Clock Rate Selects
+ 'SPSR' : '$4d', # SPI Status Register
+ 'SPSR_SPIF': '$80', # SPI Interrupt Flag
+ 'SPSR_WCOL': '$40', # Write Collision Flag
+ 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
+ 'SPDR' : '$4e', # SPI Data Register
+
+# Module PORTA
+ 'PORTA' : '$22', # Port A Data Register
+ 'DDRA' : '$21', # Port A Data Direction Register
+ 'PINA' : '$20', # Port A Input Pins
+
+# Module PORTB
+ 'PORTB' : '$25', # Port B Data Register
+ 'DDRB' : '$24', # Port B Data Direction Register
+ 'PINB' : '$23', # Port B Input Pins
+
+# Module PORTC
+ 'PORTC' : '$28', # Port C Data Register
+ 'DDRC' : '$27', # Port C Data Direction Register
+ 'PINC' : '$26', # Port C Input Pins
+
+# Module PORTD
+ 'PORTD' : '$2b', # Port D Data Register
+ 'DDRD' : '$2a', # Port D Data Direction Register
+ 'PIND' : '$29', # Port D Input Pins
+
+# Module PORTE
+ 'PORTE' : '$2e', # Data Register, Port E
+ 'DDRE' : '$2d', # Data Direction Register, Port
+ 'PINE' : '$2c', # Input Pins, Port E
+
+# Module PORTF
+ 'PORTF' : '$31', # Data Register, Port F
+ 'DDRF' : '$30', # Data Direction Register, Port
+ 'PINF' : '$2f', # Input Pins, Port F
+
+# Module PORTG
+ 'PORTG' : '$34', # Data Register, Port G
+ 'DDRG' : '$33', # Data Direction Register, Port
+ 'PING' : '$32', # Input Pins, Port G
+
+# Module PORTH
+ 'PORTH' : '$102', # PORT H Data Register
+ 'DDRH' : '$101', # PORT H Data Direction Register
+ 'PINH' : '$100', # PORT H Input Pins
+
+# Module PORTJ
+ 'PORTJ' : '$105', # PORT J Data Register
+ 'DDRJ' : '$104', # PORT J Data Direction Register
+ 'PINJ' : '$103', # PORT J Input Pins
+
+# Module PORTK
+ 'PORTK' : '$108', # PORT K Data Register
+ 'DDRK' : '$107', # PORT K Data Direction Register
+ 'PINK' : '$106', # PORT K Input Pins
+
+# Module PORTL
+ 'PORTL' : '$10b', # PORT L Data Register
+ 'DDRL' : '$10a', # PORT L Data Direction Register
+ 'PINL' : '$109', # PORT L Input Pins
+
+# Module TIMER_COUNTER_0
+ 'OCR0B' : '$48', # Timer/Counter0 Output Compare
+ 'OCR0A' : '$47', # Timer/Counter0 Output Compare
+ 'TCNT0' : '$46', # Timer/Counter0
+ 'TCCR0B' : '$45', # Timer/Counter Control Register
+ 'TCCR0B_FOC0A': '$80', # Force Output Compare A
+ 'TCCR0B_FOC0B': '$40', # Force Output Compare B
+ 'TCCR0B_WGM02': '$8', #
+ 'TCCR0B_CS0': '$7', # Clock Select
+ 'TCCR0A' : '$44', # Timer/Counter Control Registe
+ 'TCCR0A_COM0A': '$c0', # Compare Output Mode, Phase Cor
+ 'TCCR0A_COM0B': '$30', # Compare Output Mode, Fast PWm
+ 'TCCR0A_WGM0': '$3', # Waveform Generation Mode
+ 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
+ 'TIMSK0_OCIE0B': '$4', # Timer/Counter0 Output Compare
+ 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
+ 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
+ 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
+ 'TIFR0_OCF0B': '$4', # Timer/Counter0 Output Compare
+ 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
+ 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSRSYNC': '$1', # Prescaler Reset Timer/Counter1
+
+# Module TIMER_COUNTER_2
+ 'TIMSK2' : '$70', # Timer/Counter Interrupt Mask r
+ 'TIMSK2_OCIE2B': '$4', # Timer/Counter2 Output Compare
+ 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
+ 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
+ 'TIFR2' : '$37', # Timer/Counter Interrupt Flag R
+ 'TIFR2_OCF2B': '$4', # Output Compare Flag 2B
+ 'TIFR2_OCF2A': '$2', # Output Compare Flag 2A
+ 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
+ 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
+ 'TCCR2A_COM2A': '$c0', # Compare Output Mode bits
+ 'TCCR2A_COM2B': '$30', # Compare Output Mode bits
+ 'TCCR2A_WGM2': '$3', # Waveform Genration Mode
+ 'TCCR2B' : '$b1', # Timer/Counter2 Control Registe
+ 'TCCR2B_FOC2A': '$80', # Force Output Compare A
+ 'TCCR2B_FOC2B': '$40', # Force Output Compare B
+ 'TCCR2B_WGM22': '$8', # Waveform Generation Mode
+ 'TCCR2B_CS2': '$7', # Clock Select bits
+ 'TCNT2' : '$b2', # Timer/Counter2
+ 'OCR2B' : '$b4', # Timer/Counter2 Output Compare
+ 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
+ 'ASSR' : '$b6', # Asynchronous Status Register
+ 'ASSR_EXCLK': '$40', # Enable External Clock Input
+ 'ASSR_AS2': '$20', # Asynchronous Timer/Counter2
+ 'ASSR_TCN2UB': '$10', # Timer/Counter2 Update Busy
+ 'ASSR_OCR2AUB': '$8', # Output Compare Register2 Updat
+ 'ASSR_OCR2BUB': '$4', # Output Compare Register 2 Upda
+ 'ASSR_TCR2AUB': '$2', # Timer/Counter Control Register
+ 'ASSR_TCR2BUB': '$1', # Timer/Counter Control Register
+ 'GTCCR' : '$43', # General Timer Counter Control
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSRASY': '$2', # Prescaler Reset Timer/Counter2
+
+# Module WATCHDOG
+ 'WDTCSR' : '$60', # Watchdog Timer Control Registe
+ 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
+ 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
+ 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
+ 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
+ 'WDTCSR_WDE': '$8', # Watch Dog Enable
+
+# Module USART1
+ 'UDR1' : '$ce', # USART I/O Data Register
+ 'UCSR1A' : '$c8', # USART Control and Status Regis
+ 'UCSR1A_RXC1': '$80', # USART Receive Complete
+ 'UCSR1A_TXC1': '$40', # USART Transmitt Complete
+ 'UCSR1A_UDRE1': '$20', # USART Data Register Empty
+ 'UCSR1A_FE1': '$10', # Framing Error
+ 'UCSR1A_DOR1': '$8', # Data overRun
+ 'UCSR1A_UPE1': '$4', # Parity Error
+ 'UCSR1A_U2X1': '$2', # Double the USART transmission
+ 'UCSR1A_MPCM1': '$1', # Multi-processor Communication
+ 'UCSR1B' : '$c9', # USART Control and Status Regis
+ 'UCSR1B_RXCIE1': '$80', # RX Complete Interrupt Enable
+ 'UCSR1B_TXCIE1': '$40', # TX Complete Interrupt Enable
+ 'UCSR1B_UDRIE1': '$20', # USART Data register Empty Inte
+ 'UCSR1B_RXEN1': '$10', # Receiver Enable
+ 'UCSR1B_TXEN1': '$8', # Transmitter Enable
+ 'UCSR1B_UCSZ12': '$4', # Character Size
+ 'UCSR1B_RXB81': '$2', # Receive Data Bit 8
+ 'UCSR1B_TXB81': '$1', # Transmit Data Bit 8
+ 'UCSR1C' : '$ca', # USART Control and Status Regis
+ 'UCSR1C_UMSEL1': '$c0', # USART Mode Select
+ 'UCSR1C_UPM1': '$30', # Parity Mode Bits
+ 'UCSR1C_USBS1': '$8', # Stop Bit Select
+ 'UCSR1C_UCSZ1': '$6', # Character Size
+ 'UCSR1C_UCPOL1': '$1', # Clock Polarity
+ 'UBRR1' : '$cc', # USART Baud Rate Register Byte
+
+# Module EEPROM
+ 'EEAR' : '$41', # EEPROM Address Register Low By
+ 'EEDR' : '$40', # EEPROM Data Register
+ 'EECR' : '$3f', # EEPROM Control Register
+ 'EECR_EEPM': '$30', # EEPROM Programming Mode Bits
+ 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
+ 'EECR_EEMPE': '$4', # EEPROM Master Write Enable
+ 'EECR_EEPE': '$2', # EEPROM Write Enable
+ 'EECR_EERE': '$1', # EEPROM Read Enable
+
+# Module TIMER_COUNTER_5
+ 'TCCR5A' : '$120', # Timer/Counter5 Control Registe
+ 'TCCR5A_COM5A': '$c0', # Compare Output Mode 1A, bits
+ 'TCCR5A_COM5B': '$30', # Compare Output Mode 5B, bits
+ 'TCCR5A_COM5C': '$c', # Compare Output Mode 5C, bits
+ 'TCCR5A_WGM5': '$3', # Waveform Generation Mode
+ 'TCCR5B' : '$121', # Timer/Counter5 Control Registe
+ 'TCCR5B_ICNC5': '$80', # Input Capture 5 Noise Canceler
+ 'TCCR5B_ICES5': '$40', # Input Capture 5 Edge Select
+ 'TCCR5B_WGM5': '$18', # Waveform Generation Mode
+ 'TCCR5B_CS5': '$7', # Prescaler source of Timer/Coun
+ 'TCCR5C' : '$122', # Timer/Counter 5 Control Regist
+ 'TCCR5C_FOC5A': '$80', # Force Output Compare 5A
+ 'TCCR5C_FOC5B': '$40', # Force Output Compare 5B
+ 'TCCR5C_FOC5C': '$20', # Force Output Compare 5C
+ 'TCNT5' : '$124', # Timer/Counter5 Bytes
+ 'OCR5A' : '$128', # Timer/Counter5 Output Compare
+ 'OCR5B' : '$12a', # Timer/Counter5 Output Compare
+ 'OCR5C' : '$12c', # Timer/Counter5 Output Compare
+ 'ICR5' : '$126', # Timer/Counter5 Input Capture R
+ 'TIMSK5' : '$73', # Timer/Counter5 Interrupt Mask
+ 'TIMSK5_ICIE5': '$20', # Timer/Counter5 Input Capture I
+ 'TIMSK5_OCIE5C': '$8', # Timer/Counter5 Output Compare
+ 'TIMSK5_OCIE5B': '$4', # Timer/Counter5 Output Compare
+ 'TIMSK5_OCIE5A': '$2', # Timer/Counter5 Output Compare
+ 'TIMSK5_TOIE5': '$1', # Timer/Counter5 Overflow Interr
+ 'TIFR5' : '$3a', # Timer/Counter5 Interrupt Flag
+ 'TIFR5_ICF5': '$20', # Input Capture Flag 5
+ 'TIFR5_OCF5C': '$8', # Output Compare Flag 5C
+ 'TIFR5_OCF5B': '$4', # Output Compare Flag 5B
+ 'TIFR5_OCF5A': '$2', # Output Compare Flag 5A
+ 'TIFR5_TOV5': '$1', # Timer/Counter5 Overflow Flag
+
+# Module TIMER_COUNTER_4
+ 'TCCR4A' : '$a0', # Timer/Counter4 Control Registe
+ 'TCCR4A_COM4A': '$c0', # Compare Output Mode 1A, bits
+ 'TCCR4A_COM4B': '$30', # Compare Output Mode 4B, bits
+ 'TCCR4A_COM4C': '$c', # Compare Output Mode 4C, bits
+ 'TCCR4A_WGM4': '$3', # Waveform Generation Mode
+ 'TCCR4B' : '$a1', # Timer/Counter4 Control Registe
+ 'TCCR4B_ICNC4': '$80', # Input Capture 4 Noise Canceler
+ 'TCCR4B_ICES4': '$40', # Input Capture 4 Edge Select
+ 'TCCR4B_WGM4': '$18', # Waveform Generation Mode
+ 'TCCR4B_CS4': '$7', # Prescaler source of Timer/Coun
+ 'TCCR4C' : '$a2', # Timer/Counter 4 Control Regist
+ 'TCCR4C_FOC4A': '$80', # Force Output Compare 4A
+ 'TCCR4C_FOC4B': '$40', # Force Output Compare 4B
+ 'TCCR4C_FOC4C': '$20', # Force Output Compare 4C
+ 'TCNT4' : '$a4', # Timer/Counter4 Bytes
+ 'OCR4A' : '$a8', # Timer/Counter4 Output Compare
+ 'OCR4B' : '$aa', # Timer/Counter4 Output Compare
+ 'OCR4C' : '$ac', # Timer/Counter4 Output Compare
+ 'ICR4' : '$a6', # Timer/Counter4 Input Capture R
+ 'TIMSK4' : '$72', # Timer/Counter4 Interrupt Mask
+ 'TIMSK4_ICIE4': '$20', # Timer/Counter4 Input Capture I
+ 'TIMSK4_OCIE4C': '$8', # Timer/Counter4 Output Compare
+ 'TIMSK4_OCIE4B': '$4', # Timer/Counter4 Output Compare
+ 'TIMSK4_OCIE4A': '$2', # Timer/Counter4 Output Compare
+ 'TIMSK4_TOIE4': '$1', # Timer/Counter4 Overflow Interr
+ 'TIFR4' : '$39', # Timer/Counter4 Interrupt Flag
+ 'TIFR4_ICF4': '$20', # Input Capture Flag 4
+ 'TIFR4_OCF4C': '$8', # Output Compare Flag 4C
+ 'TIFR4_OCF4B': '$4', # Output Compare Flag 4B
+ 'TIFR4_OCF4A': '$2', # Output Compare Flag 4A
+ 'TIFR4_TOV4': '$1', # Timer/Counter4 Overflow Flag
+
+# Module TIMER_COUNTER_3
+ 'TCCR3A' : '$90', # Timer/Counter3 Control Registe
+ 'TCCR3A_COM3A': '$c0', # Compare Output Mode 1A, bits
+ 'TCCR3A_COM3B': '$30', # Compare Output Mode 3B, bits
+ 'TCCR3A_COM3C': '$c', # Compare Output Mode 3C, bits
+ 'TCCR3A_WGM3': '$3', # Waveform Generation Mode
+ 'TCCR3B' : '$91', # Timer/Counter3 Control Registe
+ 'TCCR3B_ICNC3': '$80', # Input Capture 3 Noise Canceler
+ 'TCCR3B_ICES3': '$40', # Input Capture 3 Edge Select
+ 'TCCR3B_WGM3': '$18', # Waveform Generation Mode
+ 'TCCR3B_CS3': '$7', # Prescaler source of Timer/Coun
+ 'TCCR3C' : '$92', # Timer/Counter 3 Control Regist
+ 'TCCR3C_FOC3A': '$80', # Force Output Compare 3A
+ 'TCCR3C_FOC3B': '$40', # Force Output Compare 3B
+ 'TCCR3C_FOC3C': '$20', # Force Output Compare 3C
+ 'TCNT3' : '$94', # Timer/Counter3 Bytes
+ 'OCR3A' : '$98', # Timer/Counter3 Output Compare
+ 'OCR3B' : '$9a', # Timer/Counter3 Output Compare
+ 'OCR3C' : '$9c', # Timer/Counter3 Output Compare
+ 'ICR3' : '$96', # Timer/Counter3 Input Capture R
+ 'TIMSK3' : '$71', # Timer/Counter3 Interrupt Mask
+ 'TIMSK3_ICIE3': '$20', # Timer/Counter3 Input Capture I
+ 'TIMSK3_OCIE3C': '$8', # Timer/Counter3 Output Compare
+ 'TIMSK3_OCIE3B': '$4', # Timer/Counter3 Output Compare
+ 'TIMSK3_OCIE3A': '$2', # Timer/Counter3 Output Compare
+ 'TIMSK3_TOIE3': '$1', # Timer/Counter3 Overflow Interr
+ 'TIFR3' : '$38', # Timer/Counter3 Interrupt Flag
+ 'TIFR3_ICF3': '$20', # Input Capture Flag 3
+ 'TIFR3_OCF3C': '$8', # Output Compare Flag 3C
+ 'TIFR3_OCF3B': '$4', # Output Compare Flag 3B
+ 'TIFR3_OCF3A': '$2', # Output Compare Flag 3A
+ 'TIFR3_TOV3': '$1', # Timer/Counter3 Overflow Flag
+
+# Module TIMER_COUNTER_1
+ 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
+ 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
+ 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
+ 'TCCR1A_COM1C': '$c', # Compare Output Mode 1C, bits
+ 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
+ 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
+ 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
+ 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
+ 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
+ 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
+ 'TCCR1C' : '$82', # Timer/Counter 1 Control Regist
+ 'TCCR1C_FOC1A': '$80', # Force Output Compare 1A
+ 'TCCR1C_FOC1B': '$40', # Force Output Compare 1B
+ 'TCCR1C_FOC1C': '$20', # Force Output Compare 1C
+ 'TCNT1' : '$84', # Timer/Counter1 Bytes
+ 'OCR1A' : '$88', # Timer/Counter1 Output Compare
+ 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
+ 'OCR1C' : '$8c', # Timer/Counter1 Output Compare
+ 'ICR1' : '$86', # Timer/Counter1 Input Capture R
+ 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
+ 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
+ 'TIMSK1_OCIE1C': '$8', # Timer/Counter1 Output Compare
+ 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
+ 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
+ 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
+ 'TIFR1' : '$36', # Timer/Counter1 Interrupt Flag
+ 'TIFR1_ICF1': '$20', # Input Capture Flag 1
+ 'TIFR1_OCF1C': '$8', # Output Compare Flag 1C
+ 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
+ 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
+ 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
+
+# Module JTAG
+ 'OCDR' : '$51', # On-Chip Debug Related Register
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_JTD': '$80', # JTAG Interface Disable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+
+# Module EXTERNAL_INTERRUPT
+ 'EICRA' : '$69', # External Interrupt Control Reg
+ 'EICRA_ISC3': '$c0', # External Interrupt Sense Contr
+ 'EICRA_ISC2': '$30', # External Interrupt Sense Contr
+ 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
+ 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
+ 'EICRB' : '$6a', # External Interrupt Control Reg
+ 'EICRB_ISC7': '$c0', # External Interrupt 7-4 Sense C
+ 'EICRB_ISC6': '$30', # External Interrupt 7-4 Sense C
+ 'EICRB_ISC5': '$c', # External Interrupt 7-4 Sense C
+ 'EICRB_ISC4': '$3', # External Interrupt 7-4 Sense C
+ 'EIMSK' : '$3d', # External Interrupt Mask Regist
+ 'EIMSK_INT': '$ff', # External Interrupt Request 7 E
+ 'EIFR' : '$3c', # External Interrupt Flag Regist
+ 'EIFR_INTF': '$ff', # External Interrupt Flags
+ 'PCMSK2' : '$6d', # Pin Change Mask Register 2
+ 'PCMSK1' : '$6c', # Pin Change Mask Register 1
+ 'PCMSK0' : '$6b', # Pin Change Mask Register 0
+ 'PCIFR' : '$3b', # Pin Change Interrupt Flag Regi
+ 'PCIFR_PCIF': '$7', # Pin Change Interrupt Flags
+ 'PCICR' : '$68', # Pin Change Interrupt Control R
+ 'PCICR_PCIE': '$7', # Pin Change Interrupt Enables
+
+# Module CPU
+ 'SREG' : '$5f', # Status Register
+ 'SREG_I': '$80', # Global Interrupt Enable
+ 'SREG_T': '$40', # Bit Copy Storage
+ 'SREG_H': '$20', # Half Carry Flag
+ 'SREG_S': '$10', # Sign Bit
+ 'SREG_V': '$8', # Two's Complement Overflow Flag
+ 'SREG_N': '$4', # Negative Flag
+ 'SREG_Z': '$2', # Zero Flag
+ 'SREG_C': '$1', # Carry Flag
+ 'SP' : '$5d', # Stack Pointer
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_JTD': '$80', # JTAG Interface Disable
+ 'MCUCR_PUD': '$10', # Pull-up disable
+ 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
+ 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+ 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
+ 'MCUSR_BORF': '$4', # Brown-out Reset Flag
+ 'MCUSR_EXTRF': '$2', # External Reset Flag
+ 'MCUSR_PORF': '$1', # Power-on reset flag
+ 'XMCRA' : '$74', # External Memory Control Regist
+ 'XMCRA_SRE': '$80', # External SRAM Enable
+ 'XMCRA_SRL': '$70', # Wait state page limit
+ 'XMCRA_SRW1': '$c', # Wait state select bit upper pa
+ 'XMCRA_SRW0': '$3', # Wait state select bit lower pa
+ 'XMCRB' : '$75', # External Memory Control Regist
+ 'XMCRB_XMBK': '$80', # External Memory Bus Keeper Ena
+ 'XMCRB_XMM': '$7', # External Memory High Mask
+ 'OSCCAL' : '$66', # Oscillator Calibration Value
+ 'CLKPR' : '$61', #
+ 'CLKPR_CLKPCE': '$80', #
+ 'CLKPR_CLKPS': '$f', #
+ 'SMCR' : '$53', # Sleep Mode Control Register
+ 'SMCR_SM': '$e', # Sleep Mode Select bits
+ 'SMCR_SE': '$1', # Sleep Enable
+ 'EIND' : '$5c', # Extended Indirect Register
+ 'RAMPZ' : '$5b', # RAM Page Z Select Register
+ 'GPIOR2' : '$4b', # General Purpose IO Register 2
+ 'GPIOR2_GPIOR': '$ff', # General Purpose IO Register 2
+ 'GPIOR1' : '$4a', # General Purpose IO Register 1
+ 'GPIOR1_GPIOR': '$ff', # General Purpose IO Register 1
+ 'GPIOR0' : '$3e', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR07': '$80', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR06': '$40', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR05': '$20', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR04': '$10', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR03': '$8', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR02': '$4', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR01': '$2', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR00': '$1', # General Purpose IO Register 0
+ 'PRR1' : '$65', # Power Reduction Register1
+ 'PRR1_PRTIM5': '$20', # Power Reduction Timer/Counter5
+ 'PRR1_PRTIM4': '$10', # Power Reduction Timer/Counter4
+ 'PRR1_PRTIM3': '$8', # Power Reduction Timer/Counter3
+ 'PRR1_PRUSART': '$7', # Power Reduction USART3
+ 'PRR0' : '$64', # Power Reduction Register0
+ 'PRR0_PRTWI': '$80', # Power Reduction TWI
+ 'PRR0_PRTIM2': '$40', # Power Reduction Timer/Counter2
+ 'PRR0_PRTIM0': '$20', # Power Reduction Timer/Counter0
+ 'PRR0_PRTIM1': '$8', # Power Reduction Timer/Counter1
+ 'PRR0_PRSPI': '$4', # Power Reduction Serial Periphe
+ 'PRR0_PRUSART0': '$2', # Power Reduction USART
+ 'PRR0_PRADC': '$1', # Power Reduction ADC
+
+# Module AD_CONVERTER
+ 'ADMUX' : '$7c', # The ADC multiplexer Selection
+ 'ADMUX_REFS': '$c0', # Reference Selection Bits
+ 'ADMUX_ADLAR': '$20', # Left Adjust Result
+ 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
+ 'ADC' : '$78', # ADC Data Register Bytes
+ 'ADCSRA' : '$7a', # The ADC Control and Status reg
+ 'ADCSRA_ADEN': '$80', # ADC Enable
+ 'ADCSRA_ADSC': '$40', # ADC Start Conversion
+ 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
+ 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
+ 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
+ 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
+ 'ADCSRB' : '$7b', # The ADC Control and Status reg
+ 'ADCSRB_ACME': '$40', #
+ 'ADCSRB_MUX5': '$8', # Analog Channel and Gain Select
+ 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Source bits
+ 'DIDR2' : '$7d', # Digital Input Disable Register
+ 'DIDR2_ADC15D': '$80', #
+ 'DIDR2_ADC14D': '$40', #
+ 'DIDR2_ADC13D': '$20', #
+ 'DIDR2_ADC12D': '$10', #
+ 'DIDR2_ADC11D': '$8', #
+ 'DIDR2_ADC10D': '$4', #
+ 'DIDR2_ADC9D': '$2', #
+ 'DIDR2_ADC8D': '$1', #
+ 'DIDR0' : '$7e', # Digital Input Disable Register
+ 'DIDR0_ADC7D': '$80', #
+ 'DIDR0_ADC6D': '$40', #
+ 'DIDR0_ADC5D': '$20', #
+ 'DIDR0_ADC4D': '$10', #
+ 'DIDR0_ADC3D': '$8', #
+ 'DIDR0_ADC2D': '$4', #
+ 'DIDR0_ADC1D': '$2', #
+ 'DIDR0_ADC0D': '$1', #
+
+# Module BOOT_LOAD
+ 'SPMCSR' : '$57', # Store Program Memory Control R
+ 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
+ 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
+ 'SPMCSR_SIGRD': '$20', # Signature Row Read
+ 'SPMCSR_RWWSRE': '$10', # Read While Write section read
+ 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
+ 'SPMCSR_PGWRT': '$4', # Page Write
+ 'SPMCSR_PGERS': '$2', # Page Erase
+ 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
+
+# Module USART2
+ 'UDR2' : '$d6', # USART I/O Data Register
+ 'UCSR2A' : '$d0', # USART Control and Status Regis
+ 'UCSR2A_RXC2': '$80', # USART Receive Complete
+ 'UCSR2A_TXC2': '$40', # USART Transmitt Complete
+ 'UCSR2A_UDRE2': '$20', # USART Data Register Empty
+ 'UCSR2A_FE2': '$10', # Framing Error
+ 'UCSR2A_DOR2': '$8', # Data overRun
+ 'UCSR2A_UPE2': '$4', # Parity Error
+ 'UCSR2A_U2X2': '$2', # Double the USART transmission
+ 'UCSR2A_MPCM2': '$1', # Multi-processor Communication
+ 'UCSR2B' : '$d1', # USART Control and Status Regis
+ 'UCSR2B_RXCIE2': '$80', # RX Complete Interrupt Enable
+ 'UCSR2B_TXCIE2': '$40', # TX Complete Interrupt Enable
+ 'UCSR2B_UDRIE2': '$20', # USART Data register Empty Inte
+ 'UCSR2B_RXEN2': '$10', # Receiver Enable
+ 'UCSR2B_TXEN2': '$8', # Transmitter Enable
+ 'UCSR2B_UCSZ22': '$4', # Character Size
+ 'UCSR2B_RXB82': '$2', # Receive Data Bit 8
+ 'UCSR2B_TXB82': '$1', # Transmit Data Bit 8
+ 'UCSR2C' : '$d2', # USART Control and Status Regis
+ 'UCSR2C_UMSEL2': '$c0', # USART Mode Select
+ 'UCSR2C_UPM2': '$30', # Parity Mode Bits
+ 'UCSR2C_USBS2': '$8', # Stop Bit Select
+ 'UCSR2C_UCSZ2': '$6', # Character Size
+ 'UCSR2C_UCPOL2': '$1', # Clock Polarity
+ 'UBRR2' : '$d4', # USART Baud Rate Register Byte
+
+# Module USART3
+ 'UDR3' : '$136', # USART I/O Data Register
+ 'UCSR3A' : '$130', # USART Control and Status Regis
+ 'UCSR3A_RXC3': '$80', # USART Receive Complete
+ 'UCSR3A_TXC3': '$40', # USART Transmitt Complete
+ 'UCSR3A_UDRE3': '$20', # USART Data Register Empty
+ 'UCSR3A_FE3': '$10', # Framing Error
+ 'UCSR3A_DOR3': '$8', # Data overRun
+ 'UCSR3A_UPE3': '$4', # Parity Error
+ 'UCSR3A_U2X3': '$2', # Double the USART transmission
+ 'UCSR3A_MPCM3': '$1', # Multi-processor Communication
+ 'UCSR3B' : '$131', # USART Control and Status Regis
+ 'UCSR3B_RXCIE3': '$80', # RX Complete Interrupt Enable
+ 'UCSR3B_TXCIE3': '$40', # TX Complete Interrupt Enable
+ 'UCSR3B_UDRIE3': '$20', # USART Data register Empty Inte
+ 'UCSR3B_RXEN3': '$10', # Receiver Enable
+ 'UCSR3B_TXEN3': '$8', # Transmitter Enable
+ 'UCSR3B_UCSZ32': '$4', # Character Size
+ 'UCSR3B_RXB83': '$2', # Receive Data Bit 8
+ 'UCSR3B_TXB83': '$1', # Transmit Data Bit 8
+ 'UCSR3C' : '$132', # USART Control and Status Regis
+ 'UCSR3C_UMSEL3': '$c0', # USART Mode Select
+ 'UCSR3C_UPM3': '$30', # Parity Mode Bits
+ 'UCSR3C_USBS3': '$8', # Stop Bit Select
+ 'UCSR3C_UCSZ3': '$6', # Character Size
+ 'UCSR3C_UCPOL3': '$1', # Clock Polarity
+ 'UBRR3' : '$134', # USART Baud Rate Register Byte
+
+ '__amforth_dummy':'0'
+}
diff --git a/amforth-6.5/avr8/devices/atmega1280/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega1280/words/no-jtag.asm
new file mode 100644
index 0000000..352a4bb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega1280/words/no-jtag.asm
@@ -0,0 +1,14 @@
+; ( -- )
+; ( -- )
+; MCU
+; disable jtag at runtime
+VE_NOJTAG:
+ .dw $FF05
+ .db "-jtag",0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOJTAG
+XT_NOJTAG:
+ .dw PFA_NOJTAG
+PFA_NOJTAG:
+
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega1280/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega1280/words/no-wdt.asm
new file mode 100644
index 0000000..ff6ddd1
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega1280/words/no-wdt.asm
@@ -0,0 +1,34 @@
+; ( -- )
+; MCU
+; disable watch dog timer at runtime
+VE_NOWDT:
+ .dw $ff04
+ .db "-wdt"
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOWDT
+XT_NOWDT:
+ .dw PFA_NOWDT
+PFA_NOWDT:
+
+ in temp1,SREG
+ push temp1
+ ; Turn always off global interrupt.
+ cli
+ ; Reset Watchdog Timer
+ wdr
+ ; Clear WDRF in MCUSR
+ in temp1, MCUSR
+ andi temp1, (0xff & (0<<WDRF))
+ out MCUSR, temp1
+ ; Write logical one to WDCE and WDE
+ ; Keep old prescaler setting to prevent unintentional time-out
+ in_ temp1, WDTCSR
+ ori temp1, (1<<WDCE) | (1<<WDE)
+ out_ WDTCSR, temp1
+ ; Turn off WDT
+ ldi temp1, (0<<WDE)
+ out_ WDTCSR, temp1
+ ; restore status register
+ pop temp1
+ out SREG,temp1
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega1280/words/sleep.asm b/amforth-6.5/avr8/devices/atmega1280/words/sleep.asm
new file mode 100644
index 0000000..256249c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega1280/words/sleep.asm
@@ -0,0 +1,19 @@
+; ( mode -- )
+; MCU
+; put the controller into the specified sleep mode
+VE_SLEEP:
+ .dw $ff05
+ .db "sleep", 0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_SLEEP
+XT_SLEEP:
+ .dw PFA_SLEEP
+PFA_SLEEP:
+ andi tosl, 7 ; leave only legal mode bits
+ lsl tosl ; move to correct location (bits 3-1)
+ ori tosl, 1 ; set the SE bit
+ out_ SMCR, tosl ; set the sleep config
+ sleep ; nighty-night
+ out_ SMCR, zerol ; 0 protects against accidental sleeps
+ loadtos ; pop argument from stack
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega1281/atmega1281.frt b/amforth-6.5/avr8/devices/atmega1281/atmega1281.frt
new file mode 100644
index 0000000..2c2516b
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega1281/atmega1281.frt
@@ -0,0 +1,509 @@
+\ Partname: ATmega1281
+\ generated automatically
+
+\ ANALOG_COMPARATOR
+&123 constant ADCSRB \ ADC Control and Status Register B
+ $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer Enable
+&80 constant ACSR \ Analog Comparator Control And Status Register
+ $80 constant ACSR_ACD \ Analog Comparator Disable
+ $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
+ $20 constant ACSR_ACO \ Analog Compare Output
+ $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
+ $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
+ $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
+ $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
+&127 constant DIDR1 \ Digital Input Disable Register 1
+ $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
+ $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
+\ USART0
+&198 constant UDR0 \ USART I/O Data Register
+&192 constant UCSR0A \ USART Control and Status Register A
+ $80 constant UCSR0A_RXC0 \ USART Receive Complete
+ $40 constant UCSR0A_TXC0 \ USART Transmitt Complete
+ $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
+ $10 constant UCSR0A_FE0 \ Framing Error
+ $08 constant UCSR0A_DOR0 \ Data overRun
+ $04 constant UCSR0A_UPE0 \ Parity Error
+ $02 constant UCSR0A_U2X0 \ Double the USART transmission speed
+ $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
+&193 constant UCSR0B \ USART Control and Status Register B
+ $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
+ $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
+ $20 constant UCSR0B_UDRIE0 \ USART Data register Empty Interrupt Enable
+ $10 constant UCSR0B_RXEN0 \ Receiver Enable
+ $08 constant UCSR0B_TXEN0 \ Transmitter Enable
+ $04 constant UCSR0B_UCSZ02 \ Character Size
+ $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
+ $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
+&194 constant UCSR0C \ USART Control and Status Register C
+ $C0 constant UCSR0C_UMSEL0 \ USART Mode Select
+ $30 constant UCSR0C_UPM0 \ Parity Mode Bits
+ $08 constant UCSR0C_USBS0 \ Stop Bit Select
+ $06 constant UCSR0C_UCSZ0 \ Character Size
+ $01 constant UCSR0C_UCPOL0 \ Clock Polarity
+&196 constant UBRR0 \ USART Baud Rate Register Bytes
+\ USART1
+&206 constant UDR1 \ USART I/O Data Register
+&200 constant UCSR1A \ USART Control and Status Register A
+ $80 constant UCSR1A_RXC1 \ USART Receive Complete
+ $40 constant UCSR1A_TXC1 \ USART Transmitt Complete
+ $20 constant UCSR1A_UDRE1 \ USART Data Register Empty
+ $10 constant UCSR1A_FE1 \ Framing Error
+ $08 constant UCSR1A_DOR1 \ Data overRun
+ $04 constant UCSR1A_UPE1 \ Parity Error
+ $02 constant UCSR1A_U2X1 \ Double the USART transmission speed
+ $01 constant UCSR1A_MPCM1 \ Multi-processor Communication Mode
+&201 constant UCSR1B \ USART Control and Status Register B
+ $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable
+ $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable
+ $20 constant UCSR1B_UDRIE1 \ USART Data register Empty Interrupt Enable
+ $10 constant UCSR1B_RXEN1 \ Receiver Enable
+ $08 constant UCSR1B_TXEN1 \ Transmitter Enable
+ $04 constant UCSR1B_UCSZ12 \ Character Size
+ $02 constant UCSR1B_RXB81 \ Receive Data Bit 8
+ $01 constant UCSR1B_TXB81 \ Transmit Data Bit 8
+&202 constant UCSR1C \ USART Control and Status Register C
+ $C0 constant UCSR1C_UMSEL1 \ USART Mode Select
+ $30 constant UCSR1C_UPM1 \ Parity Mode Bits
+ $08 constant UCSR1C_USBS1 \ Stop Bit Select
+ $06 constant UCSR1C_UCSZ1 \ Character Size
+ $01 constant UCSR1C_UCPOL1 \ Clock Polarity
+&204 constant UBRR1 \ USART Baud Rate Register Bytes
+\ TWI
+&189 constant TWAMR \ TWI (Slave) Address Mask Register
+ $FE constant TWAMR_TWAM \
+&184 constant TWBR \ TWI Bit Rate register
+&188 constant TWCR \ TWI Control Register
+ $80 constant TWCR_TWINT \ TWI Interrupt Flag
+ $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
+ $20 constant TWCR_TWSTA \ TWI Start Condition Bit
+ $10 constant TWCR_TWSTO \ TWI Stop Condition Bit
+ $08 constant TWCR_TWWC \ TWI Write Collition Flag
+ $04 constant TWCR_TWEN \ TWI Enable Bit
+ $01 constant TWCR_TWIE \ TWI Interrupt Enable
+&185 constant TWSR \ TWI Status Register
+ $F8 constant TWSR_TWS \ TWI Status
+ $03 constant TWSR_TWPS \ TWI Prescaler
+&187 constant TWDR \ TWI Data register
+&186 constant TWAR \ TWI (Slave) Address register
+ $FE constant TWAR_TWA \ TWI (Slave) Address register Bits
+ $01 constant TWAR_TWGCE \ TWI General Call Recognition Enable Bit
+\ SPI
+&76 constant SPCR \ SPI Control Register
+ $80 constant SPCR_SPIE \ SPI Interrupt Enable
+ $40 constant SPCR_SPE \ SPI Enable
+ $20 constant SPCR_DORD \ Data Order
+ $10 constant SPCR_MSTR \ Master/Slave Select
+ $08 constant SPCR_CPOL \ Clock polarity
+ $04 constant SPCR_CPHA \ Clock Phase
+ $03 constant SPCR_SPR \ SPI Clock Rate Selects
+&77 constant SPSR \ SPI Status Register
+ $80 constant SPSR_SPIF \ SPI Interrupt Flag
+ $40 constant SPSR_WCOL \ Write Collision Flag
+ $01 constant SPSR_SPI2X \ Double SPI Speed Bit
+&78 constant SPDR \ SPI Data Register
+\ PORTA
+&34 constant PORTA \ Port A Data Register
+&33 constant DDRA \ Port A Data Direction Register
+&32 constant PINA \ Port A Input Pins
+\ PORTB
+&37 constant PORTB \ Port B Data Register
+&36 constant DDRB \ Port B Data Direction Register
+&35 constant PINB \ Port B Input Pins
+\ PORTC
+&40 constant PORTC \ Port C Data Register
+&39 constant DDRC \ Port C Data Direction Register
+&38 constant PINC \ Port C Input Pins
+\ PORTD
+&43 constant PORTD \ Port D Data Register
+&42 constant DDRD \ Port D Data Direction Register
+&41 constant PIND \ Port D Input Pins
+\ PORTE
+&46 constant PORTE \ Data Register, Port E
+&45 constant DDRE \ Data Direction Register, Port E
+&44 constant PINE \ Input Pins, Port E
+\ PORTF
+&49 constant PORTF \ Data Register, Port F
+&48 constant DDRF \ Data Direction Register, Port F
+&47 constant PINF \ Input Pins, Port F
+\ PORTG
+&52 constant PORTG \ Data Register, Port G
+&51 constant DDRG \ Data Direction Register, Port G
+&50 constant PING \ Input Pins, Port G
+\ TIMER_COUNTER_0
+&72 constant OCR0B \ Timer/Counter0 Output Compare Register
+&71 constant OCR0A \ Timer/Counter0 Output Compare Register
+&70 constant TCNT0 \ Timer/Counter0
+&69 constant TCCR0B \ Timer/Counter Control Register B
+ $80 constant TCCR0B_FOC0A \ Force Output Compare A
+ $40 constant TCCR0B_FOC0B \ Force Output Compare B
+ $08 constant TCCR0B_WGM02 \
+ $07 constant TCCR0B_CS0 \ Clock Select
+&68 constant TCCR0A \ Timer/Counter Control Register A
+ $C0 constant TCCR0A_COM0A \ Compare Output Mode, Phase Correct PWM Mode
+ $30 constant TCCR0A_COM0B \ Compare Output Mode, Fast PWm
+ $03 constant TCCR0A_WGM0 \ Waveform Generation Mode
+&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
+ $04 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare Match B Interrupt Enable
+ $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match A Interrupt Enable
+ $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
+&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
+ $04 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare Flag 0B
+ $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0A
+ $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
+&67 constant GTCCR \ General Timer/Counter Control Register
+ $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
+ $01 constant GTCCR_PSRSYNC \ Prescaler Reset Timer/Counter1 and Timer/Counter0
+\ TIMER_COUNTER_2
+&112 constant TIMSK2 \ Timer/Counter Interrupt Mask register
+ $04 constant TIMSK2_OCIE2B \ Timer/Counter2 Output Compare Match B Interrupt Enable
+ $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match A Interrupt Enable
+ $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
+&55 constant TIFR2 \ Timer/Counter Interrupt Flag Register
+ $04 constant TIFR2_OCF2B \ Output Compare Flag 2B
+ $02 constant TIFR2_OCF2A \ Output Compare Flag 2A
+ $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
+&176 constant TCCR2A \ Timer/Counter2 Control Register A
+ $C0 constant TCCR2A_COM2A \ Compare Output Mode bits
+ $30 constant TCCR2A_COM2B \ Compare Output Mode bits
+ $03 constant TCCR2A_WGM2 \ Waveform Genration Mode
+&177 constant TCCR2B \ Timer/Counter2 Control Register B
+ $80 constant TCCR2B_FOC2A \ Force Output Compare A
+ $40 constant TCCR2B_FOC2B \ Force Output Compare B
+ $08 constant TCCR2B_WGM22 \ Waveform Generation Mode
+ $07 constant TCCR2B_CS2 \ Clock Select bits
+&178 constant TCNT2 \ Timer/Counter2
+&180 constant OCR2B \ Timer/Counter2 Output Compare Register B
+&179 constant OCR2A \ Timer/Counter2 Output Compare Register A
+&182 constant ASSR \ Asynchronous Status Register
+ $40 constant ASSR_EXCLK \ Enable External Clock Input
+ $20 constant ASSR_AS2 \ Asynchronous Timer/Counter2
+ $10 constant ASSR_TCN2UB \ Timer/Counter2 Update Busy
+ $08 constant ASSR_OCR2AUB \ Output Compare Register2 Update Busy
+ $04 constant ASSR_OCR2BUB \ Output Compare Register 2 Update Busy
+ $02 constant ASSR_TCR2AUB \ Timer/Counter Control Register2 Update Busy
+ $01 constant ASSR_TCR2BUB \ Timer/Counter Control Register2 Update Busy
+\ WATCHDOG
+&96 constant WDTCSR \ Watchdog Timer Control Register
+ $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Flag
+ $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Enable
+ $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
+ $10 constant WDTCSR_WDCE \ Watchdog Change Enable
+ $08 constant WDTCSR_WDE \ Watch Dog Enable
+\ TIMER_COUNTER_5
+&288 constant TCCR5A \ Timer/Counter5 Control Register A
+ $C0 constant TCCR5A_COM5A \ Compare Output Mode 1A, bits
+ $30 constant TCCR5A_COM5B \ Compare Output Mode 5B, bits
+ $0C constant TCCR5A_COM5C \ Compare Output Mode 5C, bits
+ $03 constant TCCR5A_WGM5 \ Waveform Generation Mode
+&289 constant TCCR5B \ Timer/Counter5 Control Register B
+ $80 constant TCCR5B_ICNC5 \ Input Capture 5 Noise Canceler
+ $40 constant TCCR5B_ICES5 \ Input Capture 5 Edge Select
+ $18 constant TCCR5B_WGM5 \ Waveform Generation Mode
+ $07 constant TCCR5B_CS5 \ Prescaler source of Timer/Counter 5
+&290 constant TCCR5C \ Timer/Counter 5 Control Register C
+ $80 constant TCCR5C_FOC5A \ Force Output Compare 5A
+ $40 constant TCCR5C_FOC5B \ Force Output Compare 5B
+ $20 constant TCCR5C_FOC5C \ Force Output Compare 5C
+&292 constant TCNT5 \ Timer/Counter5 Bytes
+&296 constant OCR5A \ Timer/Counter5 Output Compare Register A Bytes
+&298 constant OCR5B \ Timer/Counter5 Output Compare Register B Bytes
+&300 constant OCR5C \ Timer/Counter5 Output Compare Register B Bytes
+&294 constant ICR5 \ Timer/Counter5 Input Capture Register Bytes
+&115 constant TIMSK5 \ Timer/Counter5 Interrupt Mask Register
+ $20 constant TIMSK5_ICIE5 \ Timer/Counter5 Input Capture Interrupt Enable
+ $08 constant TIMSK5_OCIE5C \ Timer/Counter5 Output Compare C Match Interrupt Enable
+ $04 constant TIMSK5_OCIE5B \ Timer/Counter5 Output Compare B Match Interrupt Enable
+ $02 constant TIMSK5_OCIE5A \ Timer/Counter5 Output Compare A Match Interrupt Enable
+ $01 constant TIMSK5_TOIE5 \ Timer/Counter5 Overflow Interrupt Enable
+&58 constant TIFR5 \ Timer/Counter5 Interrupt Flag register
+ $20 constant TIFR5_ICF5 \ Input Capture Flag 5
+ $08 constant TIFR5_OCF5C \ Output Compare Flag 5C
+ $04 constant TIFR5_OCF5B \ Output Compare Flag 5B
+ $02 constant TIFR5_OCF5A \ Output Compare Flag 5A
+ $01 constant TIFR5_TOV5 \ Timer/Counter5 Overflow Flag
+\ TIMER_COUNTER_4
+&160 constant TCCR4A \ Timer/Counter4 Control Register A
+ $C0 constant TCCR4A_COM4A \ Compare Output Mode 1A, bits
+ $30 constant TCCR4A_COM4B \ Compare Output Mode 4B, bits
+ $0C constant TCCR4A_COM4C \ Compare Output Mode 4C, bits
+ $03 constant TCCR4A_WGM4 \ Waveform Generation Mode
+&161 constant TCCR4B \ Timer/Counter4 Control Register B
+ $80 constant TCCR4B_ICNC4 \ Input Capture 4 Noise Canceler
+ $40 constant TCCR4B_ICES4 \ Input Capture 4 Edge Select
+ $18 constant TCCR4B_WGM4 \ Waveform Generation Mode
+ $07 constant TCCR4B_CS4 \ Prescaler source of Timer/Counter 4
+&162 constant TCCR4C \ Timer/Counter 4 Control Register C
+ $80 constant TCCR4C_FOC4A \ Force Output Compare 4A
+ $40 constant TCCR4C_FOC4B \ Force Output Compare 4B
+ $20 constant TCCR4C_FOC4C \ Force Output Compare 4C
+&164 constant TCNT4 \ Timer/Counter4 Bytes
+&168 constant OCR4A \ Timer/Counter4 Output Compare Register A Bytes
+&170 constant OCR4B \ Timer/Counter4 Output Compare Register B Bytes
+&172 constant OCR4C \ Timer/Counter4 Output Compare Register B Bytes
+&166 constant ICR4 \ Timer/Counter4 Input Capture Register Bytes
+&114 constant TIMSK4 \ Timer/Counter4 Interrupt Mask Register
+ $20 constant TIMSK4_ICIE4 \ Timer/Counter4 Input Capture Interrupt Enable
+ $08 constant TIMSK4_OCIE4C \ Timer/Counter4 Output Compare C Match Interrupt Enable
+ $04 constant TIMSK4_OCIE4B \ Timer/Counter4 Output Compare B Match Interrupt Enable
+ $02 constant TIMSK4_OCIE4A \ Timer/Counter4 Output Compare A Match Interrupt Enable
+ $01 constant TIMSK4_TOIE4 \ Timer/Counter4 Overflow Interrupt Enable
+&57 constant TIFR4 \ Timer/Counter4 Interrupt Flag register
+ $20 constant TIFR4_ICF4 \ Input Capture Flag 4
+ $08 constant TIFR4_OCF4C \ Output Compare Flag 4C
+ $04 constant TIFR4_OCF4B \ Output Compare Flag 4B
+ $02 constant TIFR4_OCF4A \ Output Compare Flag 4A
+ $01 constant TIFR4_TOV4 \ Timer/Counter4 Overflow Flag
+\ TIMER_COUNTER_3
+&144 constant TCCR3A \ Timer/Counter3 Control Register A
+ $C0 constant TCCR3A_COM3A \ Compare Output Mode 1A, bits
+ $30 constant TCCR3A_COM3B \ Compare Output Mode 3B, bits
+ $0C constant TCCR3A_COM3C \ Compare Output Mode 3C, bits
+ $03 constant TCCR3A_WGM3 \ Waveform Generation Mode
+&145 constant TCCR3B \ Timer/Counter3 Control Register B
+ $80 constant TCCR3B_ICNC3 \ Input Capture 3 Noise Canceler
+ $40 constant TCCR3B_ICES3 \ Input Capture 3 Edge Select
+ $18 constant TCCR3B_WGM3 \ Waveform Generation Mode
+ $07 constant TCCR3B_CS3 \ Prescaler source of Timer/Counter 3
+&146 constant TCCR3C \ Timer/Counter 3 Control Register C
+ $80 constant TCCR3C_FOC3A \ Force Output Compare 3A
+ $40 constant TCCR3C_FOC3B \ Force Output Compare 3B
+ $20 constant TCCR3C_FOC3C \ Force Output Compare 3C
+&148 constant TCNT3 \ Timer/Counter3 Bytes
+&152 constant OCR3A \ Timer/Counter3 Output Compare Register A Bytes
+&154 constant OCR3B \ Timer/Counter3 Output Compare Register B Bytes
+&156 constant OCR3C \ Timer/Counter3 Output Compare Register B Bytes
+&150 constant ICR3 \ Timer/Counter3 Input Capture Register Bytes
+&113 constant TIMSK3 \ Timer/Counter3 Interrupt Mask Register
+ $20 constant TIMSK3_ICIE3 \ Timer/Counter3 Input Capture Interrupt Enable
+ $08 constant TIMSK3_OCIE3C \ Timer/Counter3 Output Compare C Match Interrupt Enable
+ $04 constant TIMSK3_OCIE3B \ Timer/Counter3 Output Compare B Match Interrupt Enable
+ $02 constant TIMSK3_OCIE3A \ Timer/Counter3 Output Compare A Match Interrupt Enable
+ $01 constant TIMSK3_TOIE3 \ Timer/Counter3 Overflow Interrupt Enable
+&56 constant TIFR3 \ Timer/Counter3 Interrupt Flag register
+ $20 constant TIFR3_ICF3 \ Input Capture Flag 3
+ $08 constant TIFR3_OCF3C \ Output Compare Flag 3C
+ $04 constant TIFR3_OCF3B \ Output Compare Flag 3B
+ $02 constant TIFR3_OCF3A \ Output Compare Flag 3A
+ $01 constant TIFR3_TOV3 \ Timer/Counter3 Overflow Flag
+\ TIMER_COUNTER_1
+&128 constant TCCR1A \ Timer/Counter1 Control Register A
+ $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
+ $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
+ $0C constant TCCR1A_COM1C \ Compare Output Mode 1C, bits
+ $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
+&129 constant TCCR1B \ Timer/Counter1 Control Register B
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
+ $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
+&130 constant TCCR1C \ Timer/Counter 1 Control Register C
+ $80 constant TCCR1C_FOC1A \ Force Output Compare 1A
+ $40 constant TCCR1C_FOC1B \ Force Output Compare 1B
+ $20 constant TCCR1C_FOC1C \ Force Output Compare 1C
+&132 constant TCNT1 \ Timer/Counter1 Bytes
+&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
+&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
+&140 constant OCR1C \ Timer/Counter1 Output Compare Register C Bytes
+&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
+&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
+ $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
+ $08 constant TIMSK1_OCIE1C \ Timer/Counter1 Output Compare C Match Interrupt Enable
+ $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
+ $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
+ $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
+&54 constant TIFR1 \ Timer/Counter1 Interrupt Flag register
+ $20 constant TIFR1_ICF1 \ Input Capture Flag 1
+ $08 constant TIFR1_OCF1C \ Output Compare Flag 1C
+ $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
+ $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
+ $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
+\ EEPROM
+&65 constant EEAR \ EEPROM Address Register Low Bytes
+&64 constant EEDR \ EEPROM Data Register
+&63 constant EECR \ EEPROM Control Register
+ $30 constant EECR_EEPM \ EEPROM Programming Mode Bits
+ $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
+ $04 constant EECR_EEMPE \ EEPROM Master Write Enable
+ $02 constant EECR_EEPE \ EEPROM Write Enable
+ $01 constant EECR_EERE \ EEPROM Read Enable
+\ JTAG
+&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
+&85 constant MCUCR \ MCU Control Register
+ $80 constant MCUCR_JTD \ JTAG Interface Disable
+&84 constant MCUSR \ MCU Status Register
+ $10 constant MCUSR_JTRF \ JTAG Reset Flag
+\ EXTERNAL_INTERRUPT
+&105 constant EICRA \ External Interrupt Control Register A
+ $C0 constant EICRA_ISC3 \ External Interrupt Sense Control Bit
+ $30 constant EICRA_ISC2 \ External Interrupt Sense Control Bit
+ $0C constant EICRA_ISC1 \ External Interrupt Sense Control Bit
+ $03 constant EICRA_ISC0 \ External Interrupt Sense Control Bit
+&106 constant EICRB \ External Interrupt Control Register B
+ $C0 constant EICRB_ISC7 \ External Interrupt 7-4 Sense Control Bit
+ $30 constant EICRB_ISC6 \ External Interrupt 7-4 Sense Control Bit
+ $0C constant EICRB_ISC5 \ External Interrupt 7-4 Sense Control Bit
+ $03 constant EICRB_ISC4 \ External Interrupt 7-4 Sense Control Bit
+&61 constant EIMSK \ External Interrupt Mask Register
+ $FF constant EIMSK_INT \ External Interrupt Request 7 Enable
+&60 constant EIFR \ External Interrupt Flag Register
+ $FF constant EIFR_INTF \ External Interrupt Flags
+&109 constant PCMSK2 \ Pin Change Mask Register 2
+&108 constant PCMSK1 \ Pin Change Mask Register 1
+&107 constant PCMSK0 \ Pin Change Mask Register 0
+&59 constant PCIFR \ Pin Change Interrupt Flag Register
+ $07 constant PCIFR_PCIF \ Pin Change Interrupt Flags
+&104 constant PCICR \ Pin Change Interrupt Control Register
+ $07 constant PCICR_PCIE \ Pin Change Interrupt Enables
+\ AD_CONVERTER
+&124 constant ADMUX \ The ADC multiplexer Selection Register
+ $C0 constant ADMUX_REFS \ Reference Selection Bits
+ $20 constant ADMUX_ADLAR \ Left Adjust Result
+ $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
+&120 constant ADC \ ADC Data Register Bytes
+&122 constant ADCSRA \ The ADC Control and Status register A
+ $80 constant ADCSRA_ADEN \ ADC Enable
+ $40 constant ADCSRA_ADSC \ ADC Start Conversion
+ $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
+ $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
+ $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
+ $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
+&125 constant DIDR2 \ Digital Input Disable Register
+ $80 constant DIDR2_ADC15D \
+ $40 constant DIDR2_ADC14D \
+ $20 constant DIDR2_ADC13D \
+ $10 constant DIDR2_ADC12D \
+ $08 constant DIDR2_ADC11D \
+ $04 constant DIDR2_ADC10D \
+ $02 constant DIDR2_ADC9D \
+ $01 constant DIDR2_ADC8D \
+&126 constant DIDR0 \ Digital Input Disable Register
+ $80 constant DIDR0_ADC7D \
+ $40 constant DIDR0_ADC6D \
+ $20 constant DIDR0_ADC5D \
+ $10 constant DIDR0_ADC4D \
+ $08 constant DIDR0_ADC3D \
+ $04 constant DIDR0_ADC2D \
+ $02 constant DIDR0_ADC1D \
+ $01 constant DIDR0_ADC0D \
+\ BOOT_LOAD
+&87 constant SPMCSR \ Store Program Memory Control Register
+ $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
+ $20 constant SPMCSR_SIGRD \ Signature Row Read
+ $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
+ $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
+ $04 constant SPMCSR_PGWRT \ Page Write
+ $02 constant SPMCSR_PGERS \ Page Erase
+ $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
+\ CPU
+&95 constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ $08 constant SREG_V \ Two's Complement Overflow Flag
+ $04 constant SREG_N \ Negative Flag
+ $02 constant SREG_Z \ Zero Flag
+ $01 constant SREG_C \ Carry Flag
+&93 constant SP \ Stack Pointer
+&116 constant XMCRA \ External Memory Control Register A
+ $80 constant XMCRA_SRE \ External SRAM Enable
+ $70 constant XMCRA_SRL \ Wait state page limit
+ $0C constant XMCRA_SRW1 \ Wait state select bit upper page
+ $03 constant XMCRA_SRW0 \ Wait state select bit lower page
+&117 constant XMCRB \ External Memory Control Register B
+ $80 constant XMCRB_XMBK \ External Memory Bus Keeper Enable
+ $07 constant XMCRB_XMM \ External Memory High Mask
+&102 constant OSCCAL \ Oscillator Calibration Value
+&97 constant CLKPR \
+ $80 constant CLKPR_CLKPCE \
+ $0F constant CLKPR_CLKPS \
+&83 constant SMCR \ Sleep Mode Control Register
+ $0E constant SMCR_SM \ Sleep Mode Select bits
+ $01 constant SMCR_SE \ Sleep Enable
+&91 constant RAMPZ \ RAM Page Z Select Register
+&75 constant GPIOR2 \ General Purpose IO Register 2
+ $FF constant GPIOR2_GPIOR \ General Purpose IO Register 2 bis
+&74 constant GPIOR1 \ General Purpose IO Register 1
+ $FF constant GPIOR1_GPIOR \ General Purpose IO Register 1 bis
+&62 constant GPIOR0 \ General Purpose IO Register 0
+ $80 constant GPIOR0_GPIOR07 \ General Purpose IO Register 0 bit 7
+ $40 constant GPIOR0_GPIOR06 \ General Purpose IO Register 0 bit 6
+ $20 constant GPIOR0_GPIOR05 \ General Purpose IO Register 0 bit 5
+ $10 constant GPIOR0_GPIOR04 \ General Purpose IO Register 0 bit 4
+ $08 constant GPIOR0_GPIOR03 \ General Purpose IO Register 0 bit 3
+ $04 constant GPIOR0_GPIOR02 \ General Purpose IO Register 0 bit 2
+ $02 constant GPIOR0_GPIOR01 \ General Purpose IO Register 0 bit 1
+ $01 constant GPIOR0_GPIOR00 \ General Purpose IO Register 0 bit 0
+&101 constant PRR1 \ Power Reduction Register1
+ $20 constant PRR1_PRTIM5 \ Power Reduction Timer/Counter5
+ $10 constant PRR1_PRTIM4 \ Power Reduction Timer/Counter4
+ $08 constant PRR1_PRTIM3 \ Power Reduction Timer/Counter3
+ $07 constant PRR1_PRUSART \ Power Reduction USART3
+&100 constant PRR0 \ Power Reduction Register0
+ $80 constant PRR0_PRTWI \ Power Reduction TWI
+ $40 constant PRR0_PRTIM2 \ Power Reduction Timer/Counter2
+ $20 constant PRR0_PRTIM0 \ Power Reduction Timer/Counter0
+ $08 constant PRR0_PRTIM1 \ Power Reduction Timer/Counter1
+ $04 constant PRR0_PRSPI \ Power Reduction Serial Peripheral Interface
+ $02 constant PRR0_PRUSART0 \ Power Reduction USART
+ $01 constant PRR0_PRADC \ Power Reduction ADC
+
+\ Interrupts
+&2 constant INT0Addr \ External Interrupt Request 0
+&4 constant INT1Addr \ External Interrupt Request 1
+&6 constant INT2Addr \ External Interrupt Request 2
+&8 constant INT3Addr \ External Interrupt Request 3
+&10 constant INT4Addr \ External Interrupt Request 4
+&12 constant INT5Addr \ External Interrupt Request 5
+&14 constant INT6Addr \ External Interrupt Request 6
+&16 constant INT7Addr \ External Interrupt Request 7
+&18 constant PCINT0Addr \ Pin Change Interrupt Request 0
+&20 constant PCINT1Addr \ Pin Change Interrupt Request 1
+&22 constant PCINT2Addr \ Pin Change Interrupt Request 2
+&24 constant WDTAddr \ Watchdog Time-out Interrupt
+&26 constant TIMER2_COMPAAddr \ Timer/Counter2 Compare Match A
+&28 constant TIMER2_COMPBAddr \ Timer/Counter2 Compare Match B
+&30 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
+&32 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+&34 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
+&36 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
+&38 constant TIMER1_COMPCAddr \ Timer/Counter1 Compare Match C
+&40 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+&42 constant TIMER0_COMPAAddr \ Timer/Counter0 Compare Match A
+&44 constant TIMER0_COMPBAddr \ Timer/Counter0 Compare Match B
+&46 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
+&48 constant SPI__STCAddr \ SPI Serial Transfer Complete
+&50 constant USART0__RXAddr \ USART0, Rx Complete
+&52 constant USART0__UDREAddr \ USART0 Data register Empty
+&54 constant USART0__TXAddr \ USART0, Tx Complete
+&56 constant ANALOG_COMPAddr \ Analog Comparator
+&58 constant ADCAddr \ ADC Conversion Complete
+&60 constant EE_READYAddr \ EEPROM Ready
+&62 constant TIMER3_CAPTAddr \ Timer/Counter3 Capture Event
+&64 constant TIMER3_COMPAAddr \ Timer/Counter3 Compare Match A
+&66 constant TIMER3_COMPBAddr \ Timer/Counter3 Compare Match B
+&68 constant TIMER3_COMPCAddr \ Timer/Counter3 Compare Match C
+&70 constant TIMER3_OVFAddr \ Timer/Counter3 Overflow
+&72 constant USART1__RXAddr \ USART1, Rx Complete
+&74 constant USART1__UDREAddr \ USART1 Data register Empty
+&76 constant USART1__TXAddr \ USART1, Tx Complete
+&78 constant TWIAddr \ 2-wire Serial Interface
+&80 constant SPM_READYAddr \ Store Program Memory Read
+&82 constant TIMER4_CAPTAddr \ Timer/Counter4 Capture Event
+&84 constant TIMER4_COMPAAddr \ Timer/Counter4 Compare Match A
+&86 constant TIMER4_COMPBAddr \ Timer/Counter4 Compare Match B
+&88 constant TIMER4_COMPCAddr \ Timer/Counter4 Compare Match C
+&90 constant TIMER4_OVFAddr \ Timer/Counter4 Overflow
+&92 constant TIMER5_CAPTAddr \ Timer/Counter5 Capture Event
+&94 constant TIMER5_COMPAAddr \ Timer/Counter5 Compare Match A
+&96 constant TIMER5_COMPBAddr \ Timer/Counter5 Compare Match B
+&98 constant TIMER5_COMPCAddr \ Timer/Counter5 Compare Match C
+&100 constant TIMER5_OVFAddr \ Timer/Counter5 Overflow
+&102 constant USART2__RXAddr \ USART2, Rx Complete
+&104 constant USART2__UDREAddr \ USART2 Data register Empty
+&106 constant USART2__TXAddr \ USART2, Tx Complete
+&108 constant USART3__RXAddr \ USART3, Rx Complete
+&110 constant USART3__UDREAddr \ USART3 Data register Empty
+&112 constant USART3__TXAddr \ USART3, Tx Complete
diff --git a/amforth-6.5/avr8/devices/atmega1281/device.asm b/amforth-6.5/avr8/devices/atmega1281/device.asm
new file mode 100644
index 0000000..cc65436
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega1281/device.asm
@@ -0,0 +1,184 @@
+; Partname: ATmega1281
+; generated automatically, do not edit
+
+.nolist
+ .include "m1281def.inc"
+.list
+
+.equ ramstart = 512
+.equ CELLSIZE = 2
+.macro readflashcell
+ clr temp7
+ lsl zl
+ rol zh
+ rol temp7
+ out_ RAMPZ, temp7
+ elpm @0, Z+
+ elpm @1, Z+
+.endmacro
+.macro writeflashcell
+ clr temp7
+ lsl zl
+ rol zh
+ rol temp7
+ out_ RAMPZ, temp7
+.endmacro
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_USART0 = 0
+.set WANT_USART1 = 0
+.set WANT_TWI = 0
+.set WANT_SPI = 0
+.set WANT_PORTA = 0
+.set WANT_PORTB = 0
+.set WANT_PORTC = 0
+.set WANT_PORTD = 0
+.set WANT_PORTE = 0
+.set WANT_PORTF = 0
+.set WANT_PORTG = 0
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_TIMER_COUNTER_2 = 0
+.set WANT_WATCHDOG = 0
+.set WANT_TIMER_COUNTER_5 = 0
+.set WANT_TIMER_COUNTER_4 = 0
+.set WANT_TIMER_COUNTER_3 = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_EEPROM = 0
+.set WANT_JTAG = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_AD_CONVERTER = 0
+.set WANT_BOOT_LOAD = 0
+.set WANT_CPU = 0
+.equ intvecsize = 2 ; please verify; flash size: 131072 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.org 2
+ rcall isr ; External Interrupt Request 0
+.org 4
+ rcall isr ; External Interrupt Request 1
+.org 6
+ rcall isr ; External Interrupt Request 2
+.org 8
+ rcall isr ; External Interrupt Request 3
+.org 10
+ rcall isr ; External Interrupt Request 4
+.org 12
+ rcall isr ; External Interrupt Request 5
+.org 14
+ rcall isr ; External Interrupt Request 6
+.org 16
+ rcall isr ; External Interrupt Request 7
+.org 18
+ rcall isr ; Pin Change Interrupt Request 0
+.org 20
+ rcall isr ; Pin Change Interrupt Request 1
+.org 22
+ rcall isr ; Pin Change Interrupt Request 2
+.org 24
+ rcall isr ; Watchdog Time-out Interrupt
+.org 26
+ rcall isr ; Timer/Counter2 Compare Match A
+.org 28
+ rcall isr ; Timer/Counter2 Compare Match B
+.org 30
+ rcall isr ; Timer/Counter2 Overflow
+.org 32
+ rcall isr ; Timer/Counter1 Capture Event
+.org 34
+ rcall isr ; Timer/Counter1 Compare Match A
+.org 36
+ rcall isr ; Timer/Counter1 Compare Match B
+.org 38
+ rcall isr ; Timer/Counter1 Compare Match C
+.org 40
+ rcall isr ; Timer/Counter1 Overflow
+.org 42
+ rcall isr ; Timer/Counter0 Compare Match A
+.org 44
+ rcall isr ; Timer/Counter0 Compare Match B
+.org 46
+ rcall isr ; Timer/Counter0 Overflow
+.org 48
+ rcall isr ; SPI Serial Transfer Complete
+.org 50
+ rcall isr ; USART0, Rx Complete
+.org 52
+ rcall isr ; USART0 Data register Empty
+.org 54
+ rcall isr ; USART0, Tx Complete
+.org 56
+ rcall isr ; Analog Comparator
+.org 58
+ rcall isr ; ADC Conversion Complete
+.org 60
+ rcall isr ; EEPROM Ready
+.org 62
+ rcall isr ; Timer/Counter3 Capture Event
+.org 64
+ rcall isr ; Timer/Counter3 Compare Match A
+.org 66
+ rcall isr ; Timer/Counter3 Compare Match B
+.org 68
+ rcall isr ; Timer/Counter3 Compare Match C
+.org 70
+ rcall isr ; Timer/Counter3 Overflow
+.org 72
+ rcall isr ; USART1, Rx Complete
+.org 74
+ rcall isr ; USART1 Data register Empty
+.org 76
+ rcall isr ; USART1, Tx Complete
+.org 78
+ rcall isr ; 2-wire Serial Interface
+.org 80
+ rcall isr ; Store Program Memory Read
+.org 82
+ rcall isr ; Timer/Counter4 Capture Event
+.org 84
+ rcall isr ; Timer/Counter4 Compare Match A
+.org 86
+ rcall isr ; Timer/Counter4 Compare Match B
+.org 88
+ rcall isr ; Timer/Counter4 Compare Match C
+.org 90
+ rcall isr ; Timer/Counter4 Overflow
+.org 92
+ rcall isr ; Timer/Counter5 Capture Event
+.org 94
+ rcall isr ; Timer/Counter5 Compare Match A
+.org 96
+ rcall isr ; Timer/Counter5 Compare Match B
+.org 98
+ rcall isr ; Timer/Counter5 Compare Match C
+.org 100
+ rcall isr ; Timer/Counter5 Overflow
+.org 102
+ rcall isr ; USART2, Rx Complete
+.org 104
+ rcall isr ; USART2 Data register Empty
+.org 106
+ rcall isr ; USART2, Tx Complete
+.org 108
+ rcall isr ; USART3, Rx Complete
+.org 110
+ rcall isr ; USART3 Data register Empty
+.org 112
+ rcall isr ; USART3, Tx Complete
+.equ INTVECTORS = 57
+.nooverlap
+
+; compatability layer (maybe empty)
+
+; controller data area, environment query mcu-info
+mcu_info:
+mcu_ramsize:
+ .dw 8192
+mcu_eepromsize:
+ .dw 4096
+mcu_maxdp:
+ .dw 65535
+mcu_numints:
+ .dw 57
+mcu_name:
+ .dw 10
+ .db "ATmega1281"
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega1281/device.inc b/amforth-6.5/avr8/devices/atmega1281/device.inc
new file mode 100644
index 0000000..f9f4a06
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega1281/device.inc
@@ -0,0 +1,1686 @@
+; Partname: ATmega1281
+; generated automatically, no not edit
+
+.if WANT_ANALOG_COMPARATOR == 1
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Control and Status Register B
+VE_ADCSRB:
+ .dw $ff06
+ .db "ADCSRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRB
+XT_ADCSRB:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRB:
+ .dw 123
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Control And Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw 80
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 1
+VE_DIDR1:
+ .dw $ff05
+ .db "DIDR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR1
+XT_DIDR1:
+ .dw PFA_DOVARIABLE
+PFA_DIDR1:
+ .dw 127
+
+.endif
+.if WANT_USART0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR0:
+ .dw $ff04
+ .db "UDR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR0
+XT_UDR0:
+ .dw PFA_DOVARIABLE
+PFA_UDR0:
+ .dw 198
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR0A:
+ .dw $ff06
+ .db "UCSR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0A
+XT_UCSR0A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0A:
+ .dw 192
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR0B:
+ .dw $ff06
+ .db "UCSR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0B
+XT_UCSR0B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0B:
+ .dw 193
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR0C:
+ .dw $ff06
+ .db "UCSR0C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0C
+XT_UCSR0C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0C:
+ .dw 194
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Bytes
+VE_UBRR0:
+ .dw $ff05
+ .db "UBRR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR0
+XT_UBRR0:
+ .dw PFA_DOVARIABLE
+PFA_UBRR0:
+ .dw 196
+
+.endif
+.if WANT_USART1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR1:
+ .dw $ff04
+ .db "UDR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR1
+XT_UDR1:
+ .dw PFA_DOVARIABLE
+PFA_UDR1:
+ .dw 206
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR1A:
+ .dw $ff06
+ .db "UCSR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1A
+XT_UCSR1A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1A:
+ .dw 200
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR1B:
+ .dw $ff06
+ .db "UCSR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1B
+XT_UCSR1B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1B:
+ .dw 201
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR1C:
+ .dw $ff06
+ .db "UCSR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1C
+XT_UCSR1C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1C:
+ .dw 202
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Bytes
+VE_UBRR1:
+ .dw $ff05
+ .db "UBRR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR1
+XT_UBRR1:
+ .dw PFA_DOVARIABLE
+PFA_UBRR1:
+ .dw 204
+
+.endif
+.if WANT_TWI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; TWI (Slave) Address Mask Register
+VE_TWAMR:
+ .dw $ff05
+ .db "TWAMR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWAMR
+XT_TWAMR:
+ .dw PFA_DOVARIABLE
+PFA_TWAMR:
+ .dw 189
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Bit Rate register
+VE_TWBR:
+ .dw $ff04
+ .db "TWBR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWBR
+XT_TWBR:
+ .dw PFA_DOVARIABLE
+PFA_TWBR:
+ .dw 184
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Control Register
+VE_TWCR:
+ .dw $ff04
+ .db "TWCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWCR
+XT_TWCR:
+ .dw PFA_DOVARIABLE
+PFA_TWCR:
+ .dw 188
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Status Register
+VE_TWSR:
+ .dw $ff04
+ .db "TWSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWSR
+XT_TWSR:
+ .dw PFA_DOVARIABLE
+PFA_TWSR:
+ .dw 185
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Data register
+VE_TWDR:
+ .dw $ff04
+ .db "TWDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWDR
+XT_TWDR:
+ .dw PFA_DOVARIABLE
+PFA_TWDR:
+ .dw 187
+; ( -- addr ) System Constant
+; R( -- )
+; TWI (Slave) Address register
+VE_TWAR:
+ .dw $ff04
+ .db "TWAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWAR
+XT_TWAR:
+ .dw PFA_DOVARIABLE
+PFA_TWAR:
+ .dw 186
+
+.endif
+.if WANT_SPI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR:
+ .dw $ff04
+ .db "SPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR
+XT_SPCR:
+ .dw PFA_DOVARIABLE
+PFA_SPCR:
+ .dw 76
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR:
+ .dw $ff04
+ .db "SPSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR
+XT_SPSR:
+ .dw PFA_DOVARIABLE
+PFA_SPSR:
+ .dw 77
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR:
+ .dw $ff04
+ .db "SPDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR
+XT_SPDR:
+ .dw PFA_DOVARIABLE
+PFA_SPDR:
+ .dw 78
+
+.endif
+.if WANT_PORTA == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Register
+VE_PORTA:
+ .dw $ff05
+ .db "PORTA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTA
+XT_PORTA:
+ .dw PFA_DOVARIABLE
+PFA_PORTA:
+ .dw 34
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Direction Register
+VE_DDRA:
+ .dw $ff04
+ .db "DDRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRA
+XT_DDRA:
+ .dw PFA_DOVARIABLE
+PFA_DDRA:
+ .dw 33
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Input Pins
+VE_PINA:
+ .dw $ff04
+ .db "PINA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINA
+XT_PINA:
+ .dw PFA_DOVARIABLE
+PFA_PINA:
+ .dw 32
+
+.endif
+.if WANT_PORTB == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw 37
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw 36
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw 35
+
+.endif
+.if WANT_PORTC == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Register
+VE_PORTC:
+ .dw $ff05
+ .db "PORTC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTC
+XT_PORTC:
+ .dw PFA_DOVARIABLE
+PFA_PORTC:
+ .dw 40
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Direction Register
+VE_DDRC:
+ .dw $ff04
+ .db "DDRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRC
+XT_DDRC:
+ .dw PFA_DOVARIABLE
+PFA_DDRC:
+ .dw 39
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Input Pins
+VE_PINC:
+ .dw $ff04
+ .db "PINC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINC
+XT_PINC:
+ .dw PFA_DOVARIABLE
+PFA_PINC:
+ .dw 38
+
+.endif
+.if WANT_PORTD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw 43
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw 42
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw 41
+
+.endif
+.if WANT_PORTE == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port E
+VE_PORTE:
+ .dw $ff05
+ .db "PORTE",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTE
+XT_PORTE:
+ .dw PFA_DOVARIABLE
+PFA_PORTE:
+ .dw 46
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port E
+VE_DDRE:
+ .dw $ff04
+ .db "DDRE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRE
+XT_DDRE:
+ .dw PFA_DOVARIABLE
+PFA_DDRE:
+ .dw 45
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port E
+VE_PINE:
+ .dw $ff04
+ .db "PINE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINE
+XT_PINE:
+ .dw PFA_DOVARIABLE
+PFA_PINE:
+ .dw 44
+
+.endif
+.if WANT_PORTF == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port F
+VE_PORTF:
+ .dw $ff05
+ .db "PORTF",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTF
+XT_PORTF:
+ .dw PFA_DOVARIABLE
+PFA_PORTF:
+ .dw 49
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port F
+VE_DDRF:
+ .dw $ff04
+ .db "DDRF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRF
+XT_DDRF:
+ .dw PFA_DOVARIABLE
+PFA_DDRF:
+ .dw 48
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port F
+VE_PINF:
+ .dw $ff04
+ .db "PINF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINF
+XT_PINF:
+ .dw PFA_DOVARIABLE
+PFA_PINF:
+ .dw 47
+
+.endif
+.if WANT_PORTG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port G
+VE_PORTG:
+ .dw $ff05
+ .db "PORTG",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTG
+XT_PORTG:
+ .dw PFA_DOVARIABLE
+PFA_PORTG:
+ .dw 52
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port G
+VE_DDRG:
+ .dw $ff04
+ .db "DDRG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRG
+XT_DDRG:
+ .dw PFA_DOVARIABLE
+PFA_DDRG:
+ .dw 51
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port G
+VE_PING:
+ .dw $ff04
+ .db "PING"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PING
+XT_PING:
+ .dw PFA_DOVARIABLE
+PFA_PING:
+ .dw 50
+
+.endif
+.if WANT_TIMER_COUNTER_0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0B:
+ .dw $ff05
+ .db "OCR0B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0B
+XT_OCR0B:
+ .dw PFA_DOVARIABLE
+PFA_OCR0B:
+ .dw 72
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0A:
+ .dw $ff05
+ .db "OCR0A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0A
+XT_OCR0A:
+ .dw PFA_DOVARIABLE
+PFA_OCR0A:
+ .dw 71
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw 70
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register B
+VE_TCCR0B:
+ .dw $ff06
+ .db "TCCR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0B
+XT_TCCR0B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0B:
+ .dw 69
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register A
+VE_TCCR0A:
+ .dw $ff06
+ .db "TCCR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0A
+XT_TCCR0A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0A:
+ .dw 68
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Mask Register
+VE_TIMSK0:
+ .dw $ff06
+ .db "TIMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK0
+XT_TIMSK0:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK0:
+ .dw 110
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Flag register
+VE_TIFR0:
+ .dw $ff05
+ .db "TIFR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR0
+XT_TIFR0:
+ .dw PFA_DOVARIABLE
+PFA_TIFR0:
+ .dw 53
+; ( -- addr ) System Constant
+; R( -- )
+; General Timer/Counter Control Register
+VE_GTCCR:
+ .dw $ff05
+ .db "GTCCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GTCCR
+XT_GTCCR:
+ .dw PFA_DOVARIABLE
+PFA_GTCCR:
+ .dw 67
+
+.endif
+.if WANT_TIMER_COUNTER_2 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Mask register
+VE_TIMSK2:
+ .dw $ff06
+ .db "TIMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK2
+XT_TIMSK2:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK2:
+ .dw 112
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Flag Register
+VE_TIFR2:
+ .dw $ff05
+ .db "TIFR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR2
+XT_TIFR2:
+ .dw PFA_DOVARIABLE
+PFA_TIFR2:
+ .dw 55
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register A
+VE_TCCR2A:
+ .dw $ff06
+ .db "TCCR2A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2A
+XT_TCCR2A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2A:
+ .dw 176
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register B
+VE_TCCR2B:
+ .dw $ff06
+ .db "TCCR2B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2B
+XT_TCCR2B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2B:
+ .dw 177
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2
+VE_TCNT2:
+ .dw $ff05
+ .db "TCNT2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT2
+XT_TCNT2:
+ .dw PFA_DOVARIABLE
+PFA_TCNT2:
+ .dw 178
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register B
+VE_OCR2B:
+ .dw $ff05
+ .db "OCR2B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2B
+XT_OCR2B:
+ .dw PFA_DOVARIABLE
+PFA_OCR2B:
+ .dw 180
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register A
+VE_OCR2A:
+ .dw $ff05
+ .db "OCR2A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2A
+XT_OCR2A:
+ .dw PFA_DOVARIABLE
+PFA_OCR2A:
+ .dw 179
+; ( -- addr ) System Constant
+; R( -- )
+; Asynchronous Status Register
+VE_ASSR:
+ .dw $ff04
+ .db "ASSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ASSR
+XT_ASSR:
+ .dw PFA_DOVARIABLE
+PFA_ASSR:
+ .dw 182
+
+.endif
+.if WANT_WATCHDOG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCSR:
+ .dw $ff06
+ .db "WDTCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCSR
+XT_WDTCSR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCSR:
+ .dw 96
+
+.endif
+.if WANT_TIMER_COUNTER_5 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter5 Control Register A
+VE_TCCR5A:
+ .dw $ff06
+ .db "TCCR5A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR5A
+XT_TCCR5A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR5A:
+ .dw 288
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter5 Control Register B
+VE_TCCR5B:
+ .dw $ff06
+ .db "TCCR5B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR5B
+XT_TCCR5B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR5B:
+ .dw 289
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter 5 Control Register C
+VE_TCCR5C:
+ .dw $ff06
+ .db "TCCR5C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR5C
+XT_TCCR5C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR5C:
+ .dw 290
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter5 Bytes
+VE_TCNT5:
+ .dw $ff05
+ .db "TCNT5",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT5
+XT_TCNT5:
+ .dw PFA_DOVARIABLE
+PFA_TCNT5:
+ .dw 292
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter5 Output Compare Register A Bytes
+VE_OCR5A:
+ .dw $ff05
+ .db "OCR5A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR5A
+XT_OCR5A:
+ .dw PFA_DOVARIABLE
+PFA_OCR5A:
+ .dw 296
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter5 Output Compare Register B Bytes
+VE_OCR5B:
+ .dw $ff05
+ .db "OCR5B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR5B
+XT_OCR5B:
+ .dw PFA_DOVARIABLE
+PFA_OCR5B:
+ .dw 298
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter5 Output Compare Register B Bytes
+VE_OCR5C:
+ .dw $ff05
+ .db "OCR5C",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR5C
+XT_OCR5C:
+ .dw PFA_DOVARIABLE
+PFA_OCR5C:
+ .dw 300
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter5 Input Capture Register Bytes
+VE_ICR5:
+ .dw $ff04
+ .db "ICR5"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR5
+XT_ICR5:
+ .dw PFA_DOVARIABLE
+PFA_ICR5:
+ .dw 294
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter5 Interrupt Mask Register
+VE_TIMSK5:
+ .dw $ff06
+ .db "TIMSK5"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK5
+XT_TIMSK5:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK5:
+ .dw 115
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter5 Interrupt Flag register
+VE_TIFR5:
+ .dw $ff05
+ .db "TIFR5",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR5
+XT_TIFR5:
+ .dw PFA_DOVARIABLE
+PFA_TIFR5:
+ .dw 58
+
+.endif
+.if WANT_TIMER_COUNTER_4 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter4 Control Register A
+VE_TCCR4A:
+ .dw $ff06
+ .db "TCCR4A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR4A
+XT_TCCR4A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR4A:
+ .dw 160
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter4 Control Register B
+VE_TCCR4B:
+ .dw $ff06
+ .db "TCCR4B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR4B
+XT_TCCR4B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR4B:
+ .dw 161
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter 4 Control Register C
+VE_TCCR4C:
+ .dw $ff06
+ .db "TCCR4C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR4C
+XT_TCCR4C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR4C:
+ .dw 162
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter4 Bytes
+VE_TCNT4:
+ .dw $ff05
+ .db "TCNT4",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT4
+XT_TCNT4:
+ .dw PFA_DOVARIABLE
+PFA_TCNT4:
+ .dw 164
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter4 Output Compare Register A Bytes
+VE_OCR4A:
+ .dw $ff05
+ .db "OCR4A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR4A
+XT_OCR4A:
+ .dw PFA_DOVARIABLE
+PFA_OCR4A:
+ .dw 168
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter4 Output Compare Register B Bytes
+VE_OCR4B:
+ .dw $ff05
+ .db "OCR4B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR4B
+XT_OCR4B:
+ .dw PFA_DOVARIABLE
+PFA_OCR4B:
+ .dw 170
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter4 Output Compare Register B Bytes
+VE_OCR4C:
+ .dw $ff05
+ .db "OCR4C",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR4C
+XT_OCR4C:
+ .dw PFA_DOVARIABLE
+PFA_OCR4C:
+ .dw 172
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter4 Input Capture Register Bytes
+VE_ICR4:
+ .dw $ff04
+ .db "ICR4"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR4
+XT_ICR4:
+ .dw PFA_DOVARIABLE
+PFA_ICR4:
+ .dw 166
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter4 Interrupt Mask Register
+VE_TIMSK4:
+ .dw $ff06
+ .db "TIMSK4"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK4
+XT_TIMSK4:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK4:
+ .dw 114
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter4 Interrupt Flag register
+VE_TIFR4:
+ .dw $ff05
+ .db "TIFR4",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR4
+XT_TIFR4:
+ .dw PFA_DOVARIABLE
+PFA_TIFR4:
+ .dw 57
+
+.endif
+.if WANT_TIMER_COUNTER_3 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Control Register A
+VE_TCCR3A:
+ .dw $ff06
+ .db "TCCR3A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR3A
+XT_TCCR3A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR3A:
+ .dw 144
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Control Register B
+VE_TCCR3B:
+ .dw $ff06
+ .db "TCCR3B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR3B
+XT_TCCR3B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR3B:
+ .dw 145
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter 3 Control Register C
+VE_TCCR3C:
+ .dw $ff06
+ .db "TCCR3C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR3C
+XT_TCCR3C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR3C:
+ .dw 146
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Bytes
+VE_TCNT3:
+ .dw $ff05
+ .db "TCNT3",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT3
+XT_TCNT3:
+ .dw PFA_DOVARIABLE
+PFA_TCNT3:
+ .dw 148
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Output Compare Register A Bytes
+VE_OCR3A:
+ .dw $ff05
+ .db "OCR3A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR3A
+XT_OCR3A:
+ .dw PFA_DOVARIABLE
+PFA_OCR3A:
+ .dw 152
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Output Compare Register B Bytes
+VE_OCR3B:
+ .dw $ff05
+ .db "OCR3B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR3B
+XT_OCR3B:
+ .dw PFA_DOVARIABLE
+PFA_OCR3B:
+ .dw 154
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Output Compare Register B Bytes
+VE_OCR3C:
+ .dw $ff05
+ .db "OCR3C",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR3C
+XT_OCR3C:
+ .dw PFA_DOVARIABLE
+PFA_OCR3C:
+ .dw 156
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Input Capture Register Bytes
+VE_ICR3:
+ .dw $ff04
+ .db "ICR3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR3
+XT_ICR3:
+ .dw PFA_DOVARIABLE
+PFA_ICR3:
+ .dw 150
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Interrupt Mask Register
+VE_TIMSK3:
+ .dw $ff06
+ .db "TIMSK3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK3
+XT_TIMSK3:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK3:
+ .dw 113
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Interrupt Flag register
+VE_TIFR3:
+ .dw $ff05
+ .db "TIFR3",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR3
+XT_TIFR3:
+ .dw PFA_DOVARIABLE
+PFA_TIFR3:
+ .dw 56
+
+.endif
+.if WANT_TIMER_COUNTER_1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw 128
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw 129
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter 1 Control Register C
+VE_TCCR1C:
+ .dw $ff06
+ .db "TCCR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1C
+XT_TCCR1C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1C:
+ .dw 130
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Bytes
+VE_TCNT1:
+ .dw $ff05
+ .db "TCNT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1
+XT_TCNT1:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1:
+ .dw 132
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register A Bytes
+VE_OCR1A:
+ .dw $ff05
+ .db "OCR1A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1A
+XT_OCR1A:
+ .dw PFA_DOVARIABLE
+PFA_OCR1A:
+ .dw 136
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register B Bytes
+VE_OCR1B:
+ .dw $ff05
+ .db "OCR1B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1B
+XT_OCR1B:
+ .dw PFA_DOVARIABLE
+PFA_OCR1B:
+ .dw 138
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register C Bytes
+VE_OCR1C:
+ .dw $ff05
+ .db "OCR1C",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1C
+XT_OCR1C:
+ .dw PFA_DOVARIABLE
+PFA_OCR1C:
+ .dw 140
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Bytes
+VE_ICR1:
+ .dw $ff04
+ .db "ICR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1
+XT_ICR1:
+ .dw PFA_DOVARIABLE
+PFA_ICR1:
+ .dw 134
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Mask Register
+VE_TIMSK1:
+ .dw $ff06
+ .db "TIMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK1
+XT_TIMSK1:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK1:
+ .dw 111
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Flag register
+VE_TIFR1:
+ .dw $ff05
+ .db "TIFR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR1
+XT_TIFR1:
+ .dw PFA_DOVARIABLE
+PFA_TIFR1:
+ .dw 54
+
+.endif
+.if WANT_EEPROM == 1
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Address Register Low Bytes
+VE_EEAR:
+ .dw $ff04
+ .db "EEAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEAR
+XT_EEAR:
+ .dw PFA_DOVARIABLE
+PFA_EEAR:
+ .dw 65
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw 64
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw 63
+
+.endif
+.if WANT_JTAG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; On-Chip Debug Related Register in I/O Memory
+VE_OCDR:
+ .dw $ff04
+ .db "OCDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCDR
+XT_OCDR:
+ .dw PFA_DOVARIABLE
+PFA_OCDR:
+ .dw 81
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw 85
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Status Register
+VE_MCUSR:
+ .dw $ff05
+ .db "MCUSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUSR
+XT_MCUSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUSR:
+ .dw 84
+
+.endif
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register A
+VE_EICRA:
+ .dw $ff05
+ .db "EICRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRA
+XT_EICRA:
+ .dw PFA_DOVARIABLE
+PFA_EICRA:
+ .dw 105
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register B
+VE_EICRB:
+ .dw $ff05
+ .db "EICRB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRB
+XT_EICRB:
+ .dw PFA_DOVARIABLE
+PFA_EICRB:
+ .dw 106
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Mask Register
+VE_EIMSK:
+ .dw $ff05
+ .db "EIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIMSK
+XT_EIMSK:
+ .dw PFA_DOVARIABLE
+PFA_EIMSK:
+ .dw 61
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Flag Register
+VE_EIFR:
+ .dw $ff04
+ .db "EIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIFR
+XT_EIFR:
+ .dw PFA_DOVARIABLE
+PFA_EIFR:
+ .dw 60
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 2
+VE_PCMSK2:
+ .dw $ff06
+ .db "PCMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK2
+XT_PCMSK2:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK2:
+ .dw 109
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 1
+VE_PCMSK1:
+ .dw $ff06
+ .db "PCMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK1
+XT_PCMSK1:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK1:
+ .dw 108
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 0
+VE_PCMSK0:
+ .dw $ff06
+ .db "PCMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK0
+XT_PCMSK0:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK0:
+ .dw 107
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Interrupt Flag Register
+VE_PCIFR:
+ .dw $ff05
+ .db "PCIFR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCIFR
+XT_PCIFR:
+ .dw PFA_DOVARIABLE
+PFA_PCIFR:
+ .dw 59
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Interrupt Control Register
+VE_PCICR:
+ .dw $ff05
+ .db "PCICR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCICR
+XT_PCICR:
+ .dw PFA_DOVARIABLE
+PFA_PCICR:
+ .dw 104
+
+.endif
+.if WANT_AD_CONVERTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC multiplexer Selection Register
+VE_ADMUX:
+ .dw $ff05
+ .db "ADMUX",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADMUX
+XT_ADMUX:
+ .dw PFA_DOVARIABLE
+PFA_ADMUX:
+ .dw 124
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register Bytes
+VE_ADC:
+ .dw $ff03
+ .db "ADC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADC
+XT_ADC:
+ .dw PFA_DOVARIABLE
+PFA_ADC:
+ .dw 120
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register A
+VE_ADCSRA:
+ .dw $ff06
+ .db "ADCSRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRA
+XT_ADCSRA:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRA:
+ .dw 122
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register
+VE_DIDR2:
+ .dw $ff05
+ .db "DIDR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR2
+XT_DIDR2:
+ .dw PFA_DOVARIABLE
+PFA_DIDR2:
+ .dw 125
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register
+VE_DIDR0:
+ .dw $ff05
+ .db "DIDR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR0
+XT_DIDR0:
+ .dw PFA_DOVARIABLE
+PFA_DIDR0:
+ .dw 126
+
+.endif
+.if WANT_BOOT_LOAD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control Register
+VE_SPMCSR:
+ .dw $ff06
+ .db "SPMCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCSR
+XT_SPMCSR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCSR:
+ .dw 87
+
+.endif
+.if WANT_CPU == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw 95
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer
+VE_SP:
+ .dw $ff02
+ .db "SP"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SP
+XT_SP:
+ .dw PFA_DOVARIABLE
+PFA_SP:
+ .dw 93
+; ( -- addr ) System Constant
+; R( -- )
+; External Memory Control Register A
+VE_XMCRA:
+ .dw $ff05
+ .db "XMCRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_XMCRA
+XT_XMCRA:
+ .dw PFA_DOVARIABLE
+PFA_XMCRA:
+ .dw 116
+; ( -- addr ) System Constant
+; R( -- )
+; External Memory Control Register B
+VE_XMCRB:
+ .dw $ff05
+ .db "XMCRB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_XMCRB
+XT_XMCRB:
+ .dw PFA_DOVARIABLE
+PFA_XMCRB:
+ .dw 117
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Calibration Value
+VE_OSCCAL:
+ .dw $ff06
+ .db "OSCCAL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSCCAL
+XT_OSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_OSCCAL:
+ .dw 102
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_CLKPR:
+ .dw $ff05
+ .db "CLKPR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKPR
+XT_CLKPR:
+ .dw PFA_DOVARIABLE
+PFA_CLKPR:
+ .dw 97
+; ( -- addr ) System Constant
+; R( -- )
+; Sleep Mode Control Register
+VE_SMCR:
+ .dw $ff04
+ .db "SMCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SMCR
+XT_SMCR:
+ .dw PFA_DOVARIABLE
+PFA_SMCR:
+ .dw 83
+; ( -- addr ) System Constant
+; R( -- )
+; RAM Page Z Select Register
+VE_RAMPZ:
+ .dw $ff05
+ .db "RAMPZ",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_RAMPZ
+XT_RAMPZ:
+ .dw PFA_DOVARIABLE
+PFA_RAMPZ:
+ .dw 91
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 2
+VE_GPIOR2:
+ .dw $ff06
+ .db "GPIOR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR2
+XT_GPIOR2:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR2:
+ .dw 75
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 1
+VE_GPIOR1:
+ .dw $ff06
+ .db "GPIOR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR1
+XT_GPIOR1:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR1:
+ .dw 74
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 0
+VE_GPIOR0:
+ .dw $ff06
+ .db "GPIOR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR0
+XT_GPIOR0:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR0:
+ .dw 62
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register1
+VE_PRR1:
+ .dw $ff04
+ .db "PRR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR1
+XT_PRR1:
+ .dw PFA_DOVARIABLE
+PFA_PRR1:
+ .dw 101
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register0
+VE_PRR0:
+ .dw $ff04
+ .db "PRR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR0
+XT_PRR0:
+ .dw PFA_DOVARIABLE
+PFA_PRR0:
+ .dw 100
+
+.endif
diff --git a/amforth-6.5/avr8/devices/atmega1281/device.py b/amforth-6.5/avr8/devices/atmega1281/device.py
new file mode 100644
index 0000000..8f3d69e
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega1281/device.py
@@ -0,0 +1,556 @@
+# Generated Automatically
+
+# Partname ATmega1281
+
+MCUREGS = {
+# Interrupt Vectors
+ 'INT0Addr' : '#2', # External Interrupt Request 0
+ 'INT1Addr' : '#4', # External Interrupt Request 1
+ 'INT2Addr' : '#6', # External Interrupt Request 2
+ 'INT3Addr' : '#8', # External Interrupt Request 3
+ 'INT4Addr' : '#10', # External Interrupt Request 4
+ 'INT5Addr' : '#12', # External Interrupt Request 5
+ 'INT6Addr' : '#14', # External Interrupt Request 6
+ 'INT7Addr' : '#16', # External Interrupt Request 7
+ 'PCINT0Addr' : '#18', # Pin Change Interrupt Request 0
+ 'PCINT1Addr' : '#20', # Pin Change Interrupt Request 1
+ 'PCINT2Addr' : '#22', # Pin Change Interrupt Request 2
+ 'WDTAddr' : '#24', # Watchdog Time-out Interrupt
+ 'TIMER2_COMPAAddr' : '#26', # Timer/Counter2 Compare Match A
+ 'TIMER2_COMPBAddr' : '#28', # Timer/Counter2 Compare Match B
+ 'TIMER2_OVFAddr' : '#30', # Timer/Counter2 Overflow
+ 'TIMER1_CAPTAddr' : '#32', # Timer/Counter1 Capture Event
+ 'TIMER1_COMPAAddr' : '#34', # Timer/Counter1 Compare Match A
+ 'TIMER1_COMPBAddr' : '#36', # Timer/Counter1 Compare Match B
+ 'TIMER1_COMPCAddr' : '#38', # Timer/Counter1 Compare Match C
+ 'TIMER1_OVFAddr' : '#40', # Timer/Counter1 Overflow
+ 'TIMER0_COMPAAddr' : '#42', # Timer/Counter0 Compare Match A
+ 'TIMER0_COMPBAddr' : '#44', # Timer/Counter0 Compare Match B
+ 'TIMER0_OVFAddr' : '#46', # Timer/Counter0 Overflow
+ 'SPI_STCAddr' : '#48', # SPI Serial Transfer Complete
+ 'USART0_RXAddr' : '#50', # USART0, Rx Complete
+ 'USART0_UDREAddr' : '#52', # USART0 Data register Empty
+ 'USART0_TXAddr' : '#54', # USART0, Tx Complete
+ 'ANALOG_COMPAddr' : '#56', # Analog Comparator
+ 'ADCAddr' : '#58', # ADC Conversion Complete
+ 'EE_READYAddr' : '#60', # EEPROM Ready
+ 'TIMER3_CAPTAddr' : '#62', # Timer/Counter3 Capture Event
+ 'TIMER3_COMPAAddr' : '#64', # Timer/Counter3 Compare Match A
+ 'TIMER3_COMPBAddr' : '#66', # Timer/Counter3 Compare Match B
+ 'TIMER3_COMPCAddr' : '#68', # Timer/Counter3 Compare Match C
+ 'TIMER3_OVFAddr' : '#70', # Timer/Counter3 Overflow
+ 'USART1_RXAddr' : '#72', # USART1, Rx Complete
+ 'USART1_UDREAddr' : '#74', # USART1 Data register Empty
+ 'USART1_TXAddr' : '#76', # USART1, Tx Complete
+ 'TWIAddr' : '#78', # 2-wire Serial Interface
+ 'SPM_READYAddr' : '#80', # Store Program Memory Read
+ 'TIMER4_CAPTAddr' : '#82', # Timer/Counter4 Capture Event
+ 'TIMER4_COMPAAddr' : '#84', # Timer/Counter4 Compare Match A
+ 'TIMER4_COMPBAddr' : '#86', # Timer/Counter4 Compare Match B
+ 'TIMER4_COMPCAddr' : '#88', # Timer/Counter4 Compare Match C
+ 'TIMER4_OVFAddr' : '#90', # Timer/Counter4 Overflow
+ 'TIMER5_CAPTAddr' : '#92', # Timer/Counter5 Capture Event
+ 'TIMER5_COMPAAddr' : '#94', # Timer/Counter5 Compare Match A
+ 'TIMER5_COMPBAddr' : '#96', # Timer/Counter5 Compare Match B
+ 'TIMER5_COMPCAddr' : '#98', # Timer/Counter5 Compare Match C
+ 'TIMER5_OVFAddr' : '#100', # Timer/Counter5 Overflow
+ 'USART2_RXAddr' : '#102', # USART2, Rx Complete
+ 'USART2_UDREAddr' : '#104', # USART2 Data register Empty
+ 'USART2_TXAddr' : '#106', # USART2, Tx Complete
+ 'USART3_RXAddr' : '#108', # USART3, Rx Complete
+ 'USART3_UDREAddr' : '#110', # USART3 Data register Empty
+ 'USART3_TXAddr' : '#112', # USART3, Tx Complete
+
+# Module ANALOG_COMPARATOR
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
+ 'ACSR' : '$50', # Analog Comparator Control And
+ 'ACSR_ACD': '$80', # Analog Comparator Disable
+ 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
+ 'ACSR_ACO': '$20', # Analog Compare Output
+ 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
+ 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
+ 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
+ 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
+ 'DIDR1' : '$7f', # Digital Input Disable Register
+ 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
+ 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
+
+# Module USART0
+ 'UDR0' : '$c6', # USART I/O Data Register
+ 'UCSR0A' : '$c0', # USART Control and Status Regis
+ 'UCSR0A_RXC0': '$80', # USART Receive Complete
+ 'UCSR0A_TXC0': '$40', # USART Transmitt Complete
+ 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
+ 'UCSR0A_FE0': '$10', # Framing Error
+ 'UCSR0A_DOR0': '$8', # Data overRun
+ 'UCSR0A_UPE0': '$4', # Parity Error
+ 'UCSR0A_U2X0': '$2', # Double the USART transmission
+ 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
+ 'UCSR0B' : '$c1', # USART Control and Status Regis
+ 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
+ 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
+ 'UCSR0B_UDRIE0': '$20', # USART Data register Empty Inte
+ 'UCSR0B_RXEN0': '$10', # Receiver Enable
+ 'UCSR0B_TXEN0': '$8', # Transmitter Enable
+ 'UCSR0B_UCSZ02': '$4', # Character Size
+ 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
+ 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
+ 'UCSR0C' : '$c2', # USART Control and Status Regis
+ 'UCSR0C_UMSEL0': '$c0', # USART Mode Select
+ 'UCSR0C_UPM0': '$30', # Parity Mode Bits
+ 'UCSR0C_USBS0': '$8', # Stop Bit Select
+ 'UCSR0C_UCSZ0': '$6', # Character Size
+ 'UCSR0C_UCPOL0': '$1', # Clock Polarity
+ 'UBRR0' : '$c4', # USART Baud Rate Register Byte
+
+# Module USART1
+ 'UDR1' : '$ce', # USART I/O Data Register
+ 'UCSR1A' : '$c8', # USART Control and Status Regis
+ 'UCSR1A_RXC1': '$80', # USART Receive Complete
+ 'UCSR1A_TXC1': '$40', # USART Transmitt Complete
+ 'UCSR1A_UDRE1': '$20', # USART Data Register Empty
+ 'UCSR1A_FE1': '$10', # Framing Error
+ 'UCSR1A_DOR1': '$8', # Data overRun
+ 'UCSR1A_UPE1': '$4', # Parity Error
+ 'UCSR1A_U2X1': '$2', # Double the USART transmission
+ 'UCSR1A_MPCM1': '$1', # Multi-processor Communication
+ 'UCSR1B' : '$c9', # USART Control and Status Regis
+ 'UCSR1B_RXCIE1': '$80', # RX Complete Interrupt Enable
+ 'UCSR1B_TXCIE1': '$40', # TX Complete Interrupt Enable
+ 'UCSR1B_UDRIE1': '$20', # USART Data register Empty Inte
+ 'UCSR1B_RXEN1': '$10', # Receiver Enable
+ 'UCSR1B_TXEN1': '$8', # Transmitter Enable
+ 'UCSR1B_UCSZ12': '$4', # Character Size
+ 'UCSR1B_RXB81': '$2', # Receive Data Bit 8
+ 'UCSR1B_TXB81': '$1', # Transmit Data Bit 8
+ 'UCSR1C' : '$ca', # USART Control and Status Regis
+ 'UCSR1C_UMSEL1': '$c0', # USART Mode Select
+ 'UCSR1C_UPM1': '$30', # Parity Mode Bits
+ 'UCSR1C_USBS1': '$8', # Stop Bit Select
+ 'UCSR1C_UCSZ1': '$6', # Character Size
+ 'UCSR1C_UCPOL1': '$1', # Clock Polarity
+ 'UBRR1' : '$cc', # USART Baud Rate Register Byte
+
+# Module TWI
+ 'TWAMR' : '$bd', # TWI (Slave) Address Mask Regis
+ 'TWAMR_TWAM': '$fe', #
+ 'TWBR' : '$b8', # TWI Bit Rate register
+ 'TWCR' : '$bc', # TWI Control Register
+ 'TWCR_TWINT': '$80', # TWI Interrupt Flag
+ 'TWCR_TWEA': '$40', # TWI Enable Acknowledge Bit
+ 'TWCR_TWSTA': '$20', # TWI Start Condition Bit
+ 'TWCR_TWSTO': '$10', # TWI Stop Condition Bit
+ 'TWCR_TWWC': '$8', # TWI Write Collition Flag
+ 'TWCR_TWEN': '$4', # TWI Enable Bit
+ 'TWCR_TWIE': '$1', # TWI Interrupt Enable
+ 'TWSR' : '$b9', # TWI Status Register
+ 'TWSR_TWS': '$f8', # TWI Status
+ 'TWSR_TWPS': '$3', # TWI Prescaler
+ 'TWDR' : '$bb', # TWI Data register
+ 'TWAR' : '$ba', # TWI (Slave) Address register
+ 'TWAR_TWA': '$fe', # TWI (Slave) Address register B
+ 'TWAR_TWGCE': '$1', # TWI General Call Recognition E
+
+# Module SPI
+ 'SPCR' : '$4c', # SPI Control Register
+ 'SPCR_SPIE': '$80', # SPI Interrupt Enable
+ 'SPCR_SPE': '$40', # SPI Enable
+ 'SPCR_DORD': '$20', # Data Order
+ 'SPCR_MSTR': '$10', # Master/Slave Select
+ 'SPCR_CPOL': '$8', # Clock polarity
+ 'SPCR_CPHA': '$4', # Clock Phase
+ 'SPCR_SPR': '$3', # SPI Clock Rate Selects
+ 'SPSR' : '$4d', # SPI Status Register
+ 'SPSR_SPIF': '$80', # SPI Interrupt Flag
+ 'SPSR_WCOL': '$40', # Write Collision Flag
+ 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
+ 'SPDR' : '$4e', # SPI Data Register
+
+# Module PORTA
+ 'PORTA' : '$22', # Port A Data Register
+ 'DDRA' : '$21', # Port A Data Direction Register
+ 'PINA' : '$20', # Port A Input Pins
+
+# Module PORTB
+ 'PORTB' : '$25', # Port B Data Register
+ 'DDRB' : '$24', # Port B Data Direction Register
+ 'PINB' : '$23', # Port B Input Pins
+
+# Module PORTC
+ 'PORTC' : '$28', # Port C Data Register
+ 'DDRC' : '$27', # Port C Data Direction Register
+ 'PINC' : '$26', # Port C Input Pins
+
+# Module PORTD
+ 'PORTD' : '$2b', # Port D Data Register
+ 'DDRD' : '$2a', # Port D Data Direction Register
+ 'PIND' : '$29', # Port D Input Pins
+
+# Module PORTE
+ 'PORTE' : '$2e', # Data Register, Port E
+ 'DDRE' : '$2d', # Data Direction Register, Port
+ 'PINE' : '$2c', # Input Pins, Port E
+
+# Module PORTF
+ 'PORTF' : '$31', # Data Register, Port F
+ 'DDRF' : '$30', # Data Direction Register, Port
+ 'PINF' : '$2f', # Input Pins, Port F
+
+# Module PORTG
+ 'PORTG' : '$34', # Data Register, Port G
+ 'DDRG' : '$33', # Data Direction Register, Port
+ 'PING' : '$32', # Input Pins, Port G
+
+# Module TIMER_COUNTER_0
+ 'OCR0B' : '$48', # Timer/Counter0 Output Compare
+ 'OCR0A' : '$47', # Timer/Counter0 Output Compare
+ 'TCNT0' : '$46', # Timer/Counter0
+ 'TCCR0B' : '$45', # Timer/Counter Control Register
+ 'TCCR0B_FOC0A': '$80', # Force Output Compare A
+ 'TCCR0B_FOC0B': '$40', # Force Output Compare B
+ 'TCCR0B_WGM02': '$8', #
+ 'TCCR0B_CS0': '$7', # Clock Select
+ 'TCCR0A' : '$44', # Timer/Counter Control Registe
+ 'TCCR0A_COM0A': '$c0', # Compare Output Mode, Phase Cor
+ 'TCCR0A_COM0B': '$30', # Compare Output Mode, Fast PWm
+ 'TCCR0A_WGM0': '$3', # Waveform Generation Mode
+ 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
+ 'TIMSK0_OCIE0B': '$4', # Timer/Counter0 Output Compare
+ 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
+ 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
+ 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
+ 'TIFR0_OCF0B': '$4', # Timer/Counter0 Output Compare
+ 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
+ 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSRSYNC': '$1', # Prescaler Reset Timer/Counter1
+
+# Module TIMER_COUNTER_2
+ 'TIMSK2' : '$70', # Timer/Counter Interrupt Mask r
+ 'TIMSK2_OCIE2B': '$4', # Timer/Counter2 Output Compare
+ 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
+ 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
+ 'TIFR2' : '$37', # Timer/Counter Interrupt Flag R
+ 'TIFR2_OCF2B': '$4', # Output Compare Flag 2B
+ 'TIFR2_OCF2A': '$2', # Output Compare Flag 2A
+ 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
+ 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
+ 'TCCR2A_COM2A': '$c0', # Compare Output Mode bits
+ 'TCCR2A_COM2B': '$30', # Compare Output Mode bits
+ 'TCCR2A_WGM2': '$3', # Waveform Genration Mode
+ 'TCCR2B' : '$b1', # Timer/Counter2 Control Registe
+ 'TCCR2B_FOC2A': '$80', # Force Output Compare A
+ 'TCCR2B_FOC2B': '$40', # Force Output Compare B
+ 'TCCR2B_WGM22': '$8', # Waveform Generation Mode
+ 'TCCR2B_CS2': '$7', # Clock Select bits
+ 'TCNT2' : '$b2', # Timer/Counter2
+ 'OCR2B' : '$b4', # Timer/Counter2 Output Compare
+ 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
+ 'ASSR' : '$b6', # Asynchronous Status Register
+ 'ASSR_EXCLK': '$40', # Enable External Clock Input
+ 'ASSR_AS2': '$20', # Asynchronous Timer/Counter2
+ 'ASSR_TCN2UB': '$10', # Timer/Counter2 Update Busy
+ 'ASSR_OCR2AUB': '$8', # Output Compare Register2 Updat
+ 'ASSR_OCR2BUB': '$4', # Output Compare Register 2 Upda
+ 'ASSR_TCR2AUB': '$2', # Timer/Counter Control Register
+ 'ASSR_TCR2BUB': '$1', # Timer/Counter Control Register
+ 'GTCCR' : '$43', # General Timer Counter Control
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSRASY': '$2', # Prescaler Reset Timer/Counter2
+
+# Module WATCHDOG
+ 'WDTCSR' : '$60', # Watchdog Timer Control Registe
+ 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
+ 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
+ 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
+ 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
+ 'WDTCSR_WDE': '$8', # Watch Dog Enable
+
+# Module TIMER_COUNTER_5
+ 'TCCR5A' : '$120', # Timer/Counter5 Control Registe
+ 'TCCR5A_COM5A': '$c0', # Compare Output Mode 1A, bits
+ 'TCCR5A_COM5B': '$30', # Compare Output Mode 5B, bits
+ 'TCCR5A_COM5C': '$c', # Compare Output Mode 5C, bits
+ 'TCCR5A_WGM5': '$3', # Waveform Generation Mode
+ 'TCCR5B' : '$121', # Timer/Counter5 Control Registe
+ 'TCCR5B_ICNC5': '$80', # Input Capture 5 Noise Canceler
+ 'TCCR5B_ICES5': '$40', # Input Capture 5 Edge Select
+ 'TCCR5B_WGM5': '$18', # Waveform Generation Mode
+ 'TCCR5B_CS5': '$7', # Prescaler source of Timer/Coun
+ 'TCCR5C' : '$122', # Timer/Counter 5 Control Regist
+ 'TCCR5C_FOC5A': '$80', # Force Output Compare 5A
+ 'TCCR5C_FOC5B': '$40', # Force Output Compare 5B
+ 'TCCR5C_FOC5C': '$20', # Force Output Compare 5C
+ 'TCNT5' : '$124', # Timer/Counter5 Bytes
+ 'OCR5A' : '$128', # Timer/Counter5 Output Compare
+ 'OCR5B' : '$12a', # Timer/Counter5 Output Compare
+ 'OCR5C' : '$12c', # Timer/Counter5 Output Compare
+ 'ICR5' : '$126', # Timer/Counter5 Input Capture R
+ 'TIMSK5' : '$73', # Timer/Counter5 Interrupt Mask
+ 'TIMSK5_ICIE5': '$20', # Timer/Counter5 Input Capture I
+ 'TIMSK5_OCIE5C': '$8', # Timer/Counter5 Output Compare
+ 'TIMSK5_OCIE5B': '$4', # Timer/Counter5 Output Compare
+ 'TIMSK5_OCIE5A': '$2', # Timer/Counter5 Output Compare
+ 'TIMSK5_TOIE5': '$1', # Timer/Counter5 Overflow Interr
+ 'TIFR5' : '$3a', # Timer/Counter5 Interrupt Flag
+ 'TIFR5_ICF5': '$20', # Input Capture Flag 5
+ 'TIFR5_OCF5C': '$8', # Output Compare Flag 5C
+ 'TIFR5_OCF5B': '$4', # Output Compare Flag 5B
+ 'TIFR5_OCF5A': '$2', # Output Compare Flag 5A
+ 'TIFR5_TOV5': '$1', # Timer/Counter5 Overflow Flag
+
+# Module TIMER_COUNTER_4
+ 'TCCR4A' : '$a0', # Timer/Counter4 Control Registe
+ 'TCCR4A_COM4A': '$c0', # Compare Output Mode 1A, bits
+ 'TCCR4A_COM4B': '$30', # Compare Output Mode 4B, bits
+ 'TCCR4A_COM4C': '$c', # Compare Output Mode 4C, bits
+ 'TCCR4A_WGM4': '$3', # Waveform Generation Mode
+ 'TCCR4B' : '$a1', # Timer/Counter4 Control Registe
+ 'TCCR4B_ICNC4': '$80', # Input Capture 4 Noise Canceler
+ 'TCCR4B_ICES4': '$40', # Input Capture 4 Edge Select
+ 'TCCR4B_WGM4': '$18', # Waveform Generation Mode
+ 'TCCR4B_CS4': '$7', # Prescaler source of Timer/Coun
+ 'TCCR4C' : '$a2', # Timer/Counter 4 Control Regist
+ 'TCCR4C_FOC4A': '$80', # Force Output Compare 4A
+ 'TCCR4C_FOC4B': '$40', # Force Output Compare 4B
+ 'TCCR4C_FOC4C': '$20', # Force Output Compare 4C
+ 'TCNT4' : '$a4', # Timer/Counter4 Bytes
+ 'OCR4A' : '$a8', # Timer/Counter4 Output Compare
+ 'OCR4B' : '$aa', # Timer/Counter4 Output Compare
+ 'OCR4C' : '$ac', # Timer/Counter4 Output Compare
+ 'ICR4' : '$a6', # Timer/Counter4 Input Capture R
+ 'TIMSK4' : '$72', # Timer/Counter4 Interrupt Mask
+ 'TIMSK4_ICIE4': '$20', # Timer/Counter4 Input Capture I
+ 'TIMSK4_OCIE4C': '$8', # Timer/Counter4 Output Compare
+ 'TIMSK4_OCIE4B': '$4', # Timer/Counter4 Output Compare
+ 'TIMSK4_OCIE4A': '$2', # Timer/Counter4 Output Compare
+ 'TIMSK4_TOIE4': '$1', # Timer/Counter4 Overflow Interr
+ 'TIFR4' : '$39', # Timer/Counter4 Interrupt Flag
+ 'TIFR4_ICF4': '$20', # Input Capture Flag 4
+ 'TIFR4_OCF4C': '$8', # Output Compare Flag 4C
+ 'TIFR4_OCF4B': '$4', # Output Compare Flag 4B
+ 'TIFR4_OCF4A': '$2', # Output Compare Flag 4A
+ 'TIFR4_TOV4': '$1', # Timer/Counter4 Overflow Flag
+
+# Module TIMER_COUNTER_3
+ 'TCCR3A' : '$90', # Timer/Counter3 Control Registe
+ 'TCCR3A_COM3A': '$c0', # Compare Output Mode 1A, bits
+ 'TCCR3A_COM3B': '$30', # Compare Output Mode 3B, bits
+ 'TCCR3A_COM3C': '$c', # Compare Output Mode 3C, bits
+ 'TCCR3A_WGM3': '$3', # Waveform Generation Mode
+ 'TCCR3B' : '$91', # Timer/Counter3 Control Registe
+ 'TCCR3B_ICNC3': '$80', # Input Capture 3 Noise Canceler
+ 'TCCR3B_ICES3': '$40', # Input Capture 3 Edge Select
+ 'TCCR3B_WGM3': '$18', # Waveform Generation Mode
+ 'TCCR3B_CS3': '$7', # Prescaler source of Timer/Coun
+ 'TCCR3C' : '$92', # Timer/Counter 3 Control Regist
+ 'TCCR3C_FOC3A': '$80', # Force Output Compare 3A
+ 'TCCR3C_FOC3B': '$40', # Force Output Compare 3B
+ 'TCCR3C_FOC3C': '$20', # Force Output Compare 3C
+ 'TCNT3' : '$94', # Timer/Counter3 Bytes
+ 'OCR3A' : '$98', # Timer/Counter3 Output Compare
+ 'OCR3B' : '$9a', # Timer/Counter3 Output Compare
+ 'OCR3C' : '$9c', # Timer/Counter3 Output Compare
+ 'ICR3' : '$96', # Timer/Counter3 Input Capture R
+ 'TIMSK3' : '$71', # Timer/Counter3 Interrupt Mask
+ 'TIMSK3_ICIE3': '$20', # Timer/Counter3 Input Capture I
+ 'TIMSK3_OCIE3C': '$8', # Timer/Counter3 Output Compare
+ 'TIMSK3_OCIE3B': '$4', # Timer/Counter3 Output Compare
+ 'TIMSK3_OCIE3A': '$2', # Timer/Counter3 Output Compare
+ 'TIMSK3_TOIE3': '$1', # Timer/Counter3 Overflow Interr
+ 'TIFR3' : '$38', # Timer/Counter3 Interrupt Flag
+ 'TIFR3_ICF3': '$20', # Input Capture Flag 3
+ 'TIFR3_OCF3C': '$8', # Output Compare Flag 3C
+ 'TIFR3_OCF3B': '$4', # Output Compare Flag 3B
+ 'TIFR3_OCF3A': '$2', # Output Compare Flag 3A
+ 'TIFR3_TOV3': '$1', # Timer/Counter3 Overflow Flag
+
+# Module TIMER_COUNTER_1
+ 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
+ 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
+ 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
+ 'TCCR1A_COM1C': '$c', # Compare Output Mode 1C, bits
+ 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
+ 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
+ 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
+ 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
+ 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
+ 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
+ 'TCCR1C' : '$82', # Timer/Counter 1 Control Regist
+ 'TCCR1C_FOC1A': '$80', # Force Output Compare 1A
+ 'TCCR1C_FOC1B': '$40', # Force Output Compare 1B
+ 'TCCR1C_FOC1C': '$20', # Force Output Compare 1C
+ 'TCNT1' : '$84', # Timer/Counter1 Bytes
+ 'OCR1A' : '$88', # Timer/Counter1 Output Compare
+ 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
+ 'OCR1C' : '$8c', # Timer/Counter1 Output Compare
+ 'ICR1' : '$86', # Timer/Counter1 Input Capture R
+ 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
+ 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
+ 'TIMSK1_OCIE1C': '$8', # Timer/Counter1 Output Compare
+ 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
+ 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
+ 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
+ 'TIFR1' : '$36', # Timer/Counter1 Interrupt Flag
+ 'TIFR1_ICF1': '$20', # Input Capture Flag 1
+ 'TIFR1_OCF1C': '$8', # Output Compare Flag 1C
+ 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
+ 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
+ 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
+
+# Module EEPROM
+ 'EEAR' : '$41', # EEPROM Address Register Low By
+ 'EEDR' : '$40', # EEPROM Data Register
+ 'EECR' : '$3f', # EEPROM Control Register
+ 'EECR_EEPM': '$30', # EEPROM Programming Mode Bits
+ 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
+ 'EECR_EEMPE': '$4', # EEPROM Master Write Enable
+ 'EECR_EEPE': '$2', # EEPROM Write Enable
+ 'EECR_EERE': '$1', # EEPROM Read Enable
+
+# Module JTAG
+ 'OCDR' : '$51', # On-Chip Debug Related Register
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_JTD': '$80', # JTAG Interface Disable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+
+# Module EXTERNAL_INTERRUPT
+ 'EICRA' : '$69', # External Interrupt Control Reg
+ 'EICRA_ISC3': '$c0', # External Interrupt Sense Contr
+ 'EICRA_ISC2': '$30', # External Interrupt Sense Contr
+ 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
+ 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
+ 'EICRB' : '$6a', # External Interrupt Control Reg
+ 'EICRB_ISC7': '$c0', # External Interrupt 7-4 Sense C
+ 'EICRB_ISC6': '$30', # External Interrupt 7-4 Sense C
+ 'EICRB_ISC5': '$c', # External Interrupt 7-4 Sense C
+ 'EICRB_ISC4': '$3', # External Interrupt 7-4 Sense C
+ 'EIMSK' : '$3d', # External Interrupt Mask Regist
+ 'EIMSK_INT': '$ff', # External Interrupt Request 7 E
+ 'EIFR' : '$3c', # External Interrupt Flag Regist
+ 'EIFR_INTF': '$ff', # External Interrupt Flags
+ 'PCMSK2' : '$6d', # Pin Change Mask Register 2
+ 'PCMSK1' : '$6c', # Pin Change Mask Register 1
+ 'PCMSK0' : '$6b', # Pin Change Mask Register 0
+ 'PCIFR' : '$3b', # Pin Change Interrupt Flag Regi
+ 'PCIFR_PCIF': '$7', # Pin Change Interrupt Flags
+ 'PCICR' : '$68', # Pin Change Interrupt Control R
+ 'PCICR_PCIE': '$7', # Pin Change Interrupt Enables
+
+# Module AD_CONVERTER
+ 'ADMUX' : '$7c', # The ADC multiplexer Selection
+ 'ADMUX_REFS': '$c0', # Reference Selection Bits
+ 'ADMUX_ADLAR': '$20', # Left Adjust Result
+ 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
+ 'ADC' : '$78', # ADC Data Register Bytes
+ 'ADCSRA' : '$7a', # The ADC Control and Status reg
+ 'ADCSRA_ADEN': '$80', # ADC Enable
+ 'ADCSRA_ADSC': '$40', # ADC Start Conversion
+ 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
+ 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
+ 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
+ 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
+ 'ADCSRB' : '$7b', # The ADC Control and Status reg
+ 'ADCSRB_ACME': '$40', #
+ 'ADCSRB_MUX5': '$8', # Analog Channel and Gain Select
+ 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Source bits
+ 'DIDR2' : '$7d', # Digital Input Disable Register
+ 'DIDR2_ADC15D': '$80', #
+ 'DIDR2_ADC14D': '$40', #
+ 'DIDR2_ADC13D': '$20', #
+ 'DIDR2_ADC12D': '$10', #
+ 'DIDR2_ADC11D': '$8', #
+ 'DIDR2_ADC10D': '$4', #
+ 'DIDR2_ADC9D': '$2', #
+ 'DIDR2_ADC8D': '$1', #
+ 'DIDR0' : '$7e', # Digital Input Disable Register
+ 'DIDR0_ADC7D': '$80', #
+ 'DIDR0_ADC6D': '$40', #
+ 'DIDR0_ADC5D': '$20', #
+ 'DIDR0_ADC4D': '$10', #
+ 'DIDR0_ADC3D': '$8', #
+ 'DIDR0_ADC2D': '$4', #
+ 'DIDR0_ADC1D': '$2', #
+ 'DIDR0_ADC0D': '$1', #
+
+# Module BOOT_LOAD
+ 'SPMCSR' : '$57', # Store Program Memory Control R
+ 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
+ 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
+ 'SPMCSR_SIGRD': '$20', # Signature Row Read
+ 'SPMCSR_RWWSRE': '$10', # Read While Write section read
+ 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
+ 'SPMCSR_PGWRT': '$4', # Page Write
+ 'SPMCSR_PGERS': '$2', # Page Erase
+ 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
+
+# Module CPU
+ 'SREG' : '$5f', # Status Register
+ 'SREG_I': '$80', # Global Interrupt Enable
+ 'SREG_T': '$40', # Bit Copy Storage
+ 'SREG_H': '$20', # Half Carry Flag
+ 'SREG_S': '$10', # Sign Bit
+ 'SREG_V': '$8', # Two's Complement Overflow Flag
+ 'SREG_N': '$4', # Negative Flag
+ 'SREG_Z': '$2', # Zero Flag
+ 'SREG_C': '$1', # Carry Flag
+ 'SP' : '$5d', # Stack Pointer
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_JTD': '$80', # JTAG Interface Disable
+ 'MCUCR_PUD': '$10', # Pull-up disable
+ 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
+ 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+ 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
+ 'MCUSR_BORF': '$4', # Brown-out Reset Flag
+ 'MCUSR_EXTRF': '$2', # External Reset Flag
+ 'MCUSR_PORF': '$1', # Power-on reset flag
+ 'XMCRA' : '$74', # External Memory Control Regist
+ 'XMCRA_SRE': '$80', # External SRAM Enable
+ 'XMCRA_SRL': '$70', # Wait state page limit
+ 'XMCRA_SRW1': '$c', # Wait state select bit upper pa
+ 'XMCRA_SRW0': '$3', # Wait state select bit lower pa
+ 'XMCRB' : '$75', # External Memory Control Regist
+ 'XMCRB_XMBK': '$80', # External Memory Bus Keeper Ena
+ 'XMCRB_XMM': '$7', # External Memory High Mask
+ 'OSCCAL' : '$66', # Oscillator Calibration Value
+ 'CLKPR' : '$61', #
+ 'CLKPR_CLKPCE': '$80', #
+ 'CLKPR_CLKPS': '$f', #
+ 'SMCR' : '$53', # Sleep Mode Control Register
+ 'SMCR_SM': '$e', # Sleep Mode Select bits
+ 'SMCR_SE': '$1', # Sleep Enable
+ 'RAMPZ' : '$5b', # RAM Page Z Select Register
+ 'GPIOR2' : '$4b', # General Purpose IO Register 2
+ 'GPIOR2_GPIOR': '$ff', # General Purpose IO Register 2
+ 'GPIOR1' : '$4a', # General Purpose IO Register 1
+ 'GPIOR1_GPIOR': '$ff', # General Purpose IO Register 1
+ 'GPIOR0' : '$3e', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR07': '$80', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR06': '$40', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR05': '$20', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR04': '$10', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR03': '$8', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR02': '$4', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR01': '$2', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR00': '$1', # General Purpose IO Register 0
+ 'PRR1' : '$65', # Power Reduction Register1
+ 'PRR1_PRTIM5': '$20', # Power Reduction Timer/Counter5
+ 'PRR1_PRTIM4': '$10', # Power Reduction Timer/Counter4
+ 'PRR1_PRTIM3': '$8', # Power Reduction Timer/Counter3
+ 'PRR1_PRUSART': '$7', # Power Reduction USART3
+ 'PRR0' : '$64', # Power Reduction Register0
+ 'PRR0_PRTWI': '$80', # Power Reduction TWI
+ 'PRR0_PRTIM2': '$40', # Power Reduction Timer/Counter2
+ 'PRR0_PRTIM0': '$20', # Power Reduction Timer/Counter0
+ 'PRR0_PRTIM1': '$8', # Power Reduction Timer/Counter1
+ 'PRR0_PRSPI': '$4', # Power Reduction Serial Periphe
+ 'PRR0_PRUSART0': '$2', # Power Reduction USART
+ 'PRR0_PRADC': '$1', # Power Reduction ADC
+
+ '__amforth_dummy':'0'
+}
diff --git a/amforth-6.5/avr8/devices/atmega1281/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega1281/words/no-jtag.asm
new file mode 100644
index 0000000..352a4bb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega1281/words/no-jtag.asm
@@ -0,0 +1,14 @@
+; ( -- )
+; ( -- )
+; MCU
+; disable jtag at runtime
+VE_NOJTAG:
+ .dw $FF05
+ .db "-jtag",0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOJTAG
+XT_NOJTAG:
+ .dw PFA_NOJTAG
+PFA_NOJTAG:
+
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega1281/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega1281/words/no-wdt.asm
new file mode 100644
index 0000000..ff6ddd1
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega1281/words/no-wdt.asm
@@ -0,0 +1,34 @@
+; ( -- )
+; MCU
+; disable watch dog timer at runtime
+VE_NOWDT:
+ .dw $ff04
+ .db "-wdt"
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOWDT
+XT_NOWDT:
+ .dw PFA_NOWDT
+PFA_NOWDT:
+
+ in temp1,SREG
+ push temp1
+ ; Turn always off global interrupt.
+ cli
+ ; Reset Watchdog Timer
+ wdr
+ ; Clear WDRF in MCUSR
+ in temp1, MCUSR
+ andi temp1, (0xff & (0<<WDRF))
+ out MCUSR, temp1
+ ; Write logical one to WDCE and WDE
+ ; Keep old prescaler setting to prevent unintentional time-out
+ in_ temp1, WDTCSR
+ ori temp1, (1<<WDCE) | (1<<WDE)
+ out_ WDTCSR, temp1
+ ; Turn off WDT
+ ldi temp1, (0<<WDE)
+ out_ WDTCSR, temp1
+ ; restore status register
+ pop temp1
+ out SREG,temp1
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega1281/words/sleep.asm b/amforth-6.5/avr8/devices/atmega1281/words/sleep.asm
new file mode 100644
index 0000000..256249c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega1281/words/sleep.asm
@@ -0,0 +1,19 @@
+; ( mode -- )
+; MCU
+; put the controller into the specified sleep mode
+VE_SLEEP:
+ .dw $ff05
+ .db "sleep", 0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_SLEEP
+XT_SLEEP:
+ .dw PFA_SLEEP
+PFA_SLEEP:
+ andi tosl, 7 ; leave only legal mode bits
+ lsl tosl ; move to correct location (bits 3-1)
+ ori tosl, 1 ; set the SE bit
+ out_ SMCR, tosl ; set the sleep config
+ sleep ; nighty-night
+ out_ SMCR, zerol ; 0 protects against accidental sleeps
+ loadtos ; pop argument from stack
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega1284/atmega1284.frt b/amforth-6.5/avr8/devices/atmega1284/atmega1284.frt
new file mode 100644
index 0000000..6b3a352
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega1284/atmega1284.frt
@@ -0,0 +1,380 @@
+\ Partname: ATmega1284
+\ generated automatically
+
+\ ANALOG_COMPARATOR
+&123 constant ADCSRB \ ADC Control and Status Register B
+ $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer Enable
+&80 constant ACSR \ Analog Comparator Control And Status Register
+ $80 constant ACSR_ACD \ Analog Comparator Disable
+ $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
+ $20 constant ACSR_ACO \ Analog Compare Output
+ $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
+ $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
+ $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
+ $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
+&127 constant DIDR1 \ Digital Input Disable Register 1
+ $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
+ $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
+\ USART0
+&198 constant UDR0 \ USART I/O Data Register
+&192 constant UCSR0A \ USART Control and Status Register A
+ $80 constant UCSR0A_RXC0 \ USART Receive Complete
+ $40 constant UCSR0A_TXC0 \ USART Transmitt Complete
+ $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
+ $10 constant UCSR0A_FE0 \ Framing Error
+ $08 constant UCSR0A_DOR0 \ Data overRun
+ $04 constant UCSR0A_UPE0 \ Parity Error
+ $02 constant UCSR0A_U2X0 \ Double the USART transmission speed
+ $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
+&193 constant UCSR0B \ USART Control and Status Register B
+ $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
+ $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
+ $20 constant UCSR0B_UDRIE0 \ USART Data register Empty Interrupt Enable
+ $10 constant UCSR0B_RXEN0 \ Receiver Enable
+ $08 constant UCSR0B_TXEN0 \ Transmitter Enable
+ $04 constant UCSR0B_UCSZ02 \ Character Size
+ $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
+ $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
+&194 constant UCSR0C \ USART Control and Status Register C
+ $C0 constant UCSR0C_UMSEL0 \ USART Mode Select
+ $30 constant UCSR0C_UPM0 \ Parity Mode Bits
+ $08 constant UCSR0C_USBS0 \ Stop Bit Select
+ $06 constant UCSR0C_UCSZ0 \ Character Size
+ $01 constant UCSR0C_UCPOL0 \ Clock Polarity
+&196 constant UBRR0 \ USART Baud Rate Register Bytes
+\ PORTA
+&34 constant PORTA \ Port A Data Register
+&33 constant DDRA \ Port A Data Direction Register
+&32 constant PINA \ Port A Input Pins
+\ PORTB
+&37 constant PORTB \ Port B Data Register
+&36 constant DDRB \ Port B Data Direction Register
+&35 constant PINB \ Port B Input Pins
+\ PORTC
+&40 constant PORTC \ Port C Data Register
+&39 constant DDRC \ Port C Data Direction Register
+&38 constant PINC \ Port C Input Pins
+\ PORTD
+&43 constant PORTD \ Port D Data Register
+&42 constant DDRD \ Port D Data Direction Register
+&41 constant PIND \ Port D Input Pins
+\ TIMER_COUNTER_0
+&72 constant OCR0B \ Timer/Counter0 Output Compare Register
+&71 constant OCR0A \ Timer/Counter0 Output Compare Register
+&70 constant TCNT0 \ Timer/Counter0
+&69 constant TCCR0B \ Timer/Counter Control Register B
+ $80 constant TCCR0B_FOC0A \ Force Output Compare A
+ $40 constant TCCR0B_FOC0B \ Force Output Compare B
+ $08 constant TCCR0B_WGM02 \
+ $07 constant TCCR0B_CS0 \ Clock Select
+&68 constant TCCR0A \ Timer/Counter Control Register A
+ $C0 constant TCCR0A_COM0A \ Compare Output Mode, Phase Correct PWM Mode
+ $30 constant TCCR0A_COM0B \ Compare Output Mode, Fast PWm
+ $03 constant TCCR0A_WGM0 \ Waveform Generation Mode
+&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
+ $04 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare Match B Interrupt Enable
+ $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match A Interrupt Enable
+ $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
+&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
+ $04 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare Flag 0B
+ $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0A
+ $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
+&67 constant GTCCR \ General Timer/Counter Control Register
+ $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
+ $01 constant GTCCR_PSRSYNC \ Prescaler Reset Timer/Counter1 and Timer/Counter0
+\ TIMER_COUNTER_1
+&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
+ $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
+ $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
+ $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
+ $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
+&54 constant TIFR1 \ Timer/Counter Interrupt Flag register
+ $20 constant TIFR1_ICF1 \ Timer/Counter1 Input Capture Flag
+ $04 constant TIFR1_OCF1B \ Timer/Counter1 Output Compare B Match Flag
+ $02 constant TIFR1_OCF1A \ Timer/Counter1 Output Compare A Match Flag
+ $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
+&128 constant TCCR1A \ Timer/Counter1 Control Register A
+ $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
+ $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
+ $03 constant TCCR1A_WGM1 \ Pulse Width Modulator Select Bits
+&129 constant TCCR1B \ Timer/Counter1 Control Register B
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ $18 constant TCCR1B_WGM1 \ Waveform Generation Mode Bits
+ $07 constant TCCR1B_CS1 \ Clock Select1 bits
+&130 constant TCCR1C \ Timer/Counter1 Control Register C
+ $80 constant TCCR1C_FOC1A \ Force Output Compare for Channel A
+ $40 constant TCCR1C_FOC1B \ Force Output Compare for Channel B
+&132 constant TCNT1 \ Timer/Counter1 Bytes
+&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
+&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
+&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
+\ TIMER_COUNTER_2
+&112 constant TIMSK2 \ Timer/Counter Interrupt Mask register
+ $04 constant TIMSK2_OCIE2B \ Timer/Counter2 Output Compare Match B Interrupt Enable
+ $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match A Interrupt Enable
+ $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
+&55 constant TIFR2 \ Timer/Counter Interrupt Flag Register
+ $04 constant TIFR2_OCF2B \ Output Compare Flag 2B
+ $02 constant TIFR2_OCF2A \ Output Compare Flag 2A
+ $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
+&176 constant TCCR2A \ Timer/Counter2 Control Register A
+ $C0 constant TCCR2A_COM2A \ Compare Output Mode bits
+ $30 constant TCCR2A_COM2B \ Compare Output Mode bits
+ $03 constant TCCR2A_WGM2 \ Waveform Genration Mode
+&177 constant TCCR2B \ Timer/Counter2 Control Register B
+ $80 constant TCCR2B_FOC2A \ Force Output Compare A
+ $40 constant TCCR2B_FOC2B \ Force Output Compare B
+ $08 constant TCCR2B_WGM22 \ Waveform Generation Mode
+ $07 constant TCCR2B_CS2 \ Clock Select bits
+&178 constant TCNT2 \ Timer/Counter2
+&180 constant OCR2B \ Timer/Counter2 Output Compare Register B
+&179 constant OCR2A \ Timer/Counter2 Output Compare Register A
+&182 constant ASSR \ Asynchronous Status Register
+ $40 constant ASSR_EXCLK \ Enable External Clock Input
+ $20 constant ASSR_AS2 \ Asynchronous Timer/Counter2
+ $10 constant ASSR_TCN2UB \ Timer/Counter2 Update Busy
+ $08 constant ASSR_OCR2AUB \ Output Compare Register2 Update Busy
+ $04 constant ASSR_OCR2BUB \ Output Compare Register 2 Update Busy
+ $02 constant ASSR_TCR2AUB \ Timer/Counter Control Register2 Update Busy
+ $01 constant ASSR_TCR2BUB \ Timer/Counter Control Register2 Update Busy
+\ TIMER_COUNTER_3
+&113 constant TIMSK3 \ Timer/Counter3 Interrupt Mask Register
+ $20 constant TIMSK3_ICIE3 \ Timer/Counter3 Input Capture Interrupt Enable
+ $04 constant TIMSK3_OCIE3B \ Timer/Counter3 Output Compare B Match Interrupt Enable
+ $02 constant TIMSK3_OCIE3A \ Timer/Counter3 Output Compare A Match Interrupt Enable
+ $01 constant TIMSK3_TOIE3 \ Timer/Counter3 Overflow Interrupt Enable
+&56 constant TIFR3 \ Timer/Counter Interrupt Flag register
+ $20 constant TIFR3_ICF3 \ Timer/Counter3 Input Capture Flag
+ $04 constant TIFR3_OCF3B \ Timer/Counter3 Output Compare B Match Flag
+ $02 constant TIFR3_OCF3A \ Timer/Counter3 Output Compare A Match Flag
+ $01 constant TIFR3_TOV3 \ Timer/Counter3 Overflow Flag
+&144 constant TCCR3A \ Timer/Counter3 Control Register A
+ $C0 constant TCCR3A_COM3A \ Compare Output Mode 3A, bits
+ $30 constant TCCR3A_COM3B \ Compare Output Mode 3B, bits
+ $03 constant TCCR3A_WGM3 \ Pulse Width Modulator Select Bits
+&145 constant TCCR3B \ Timer/Counter3 Control Register B
+ $80 constant TCCR3B_ICNC3 \ Input Capture 3 Noise Canceler
+ $40 constant TCCR3B_ICES3 \ Input Capture 3 Edge Select
+ $18 constant TCCR3B_WGM3 \ Waveform Generation Mode Bits
+ $07 constant TCCR3B_CS3 \ Clock Select3 bits
+&146 constant TCCR3C \ Timer/Counter3 Control Register C
+ $80 constant TCCR3C_FOC3A \ Force Output Compare for Channel A
+ $40 constant TCCR3C_FOC3B \ Force Output Compare for Channel B
+&148 constant TCNT3 \ Timer/Counter3 Bytes
+&152 constant OCR3A \ Timer/Counter3 Output Compare Register A Bytes
+&154 constant OCR3B \ Timer/Counter3 Output Compare Register B Bytes
+&150 constant ICR3 \ Timer/Counter3 Input Capture Register Bytes
+\ BOOT_LOAD
+&87 constant SPMCSR \ Store Program Memory Control Register
+ $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
+ $20 constant SPMCSR_SIGRD \ Signature Row Read
+ $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
+ $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
+ $04 constant SPMCSR_PGWRT \ Page Write
+ $02 constant SPMCSR_PGERS \ Page Erase
+ $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
+\ EXTERNAL_INTERRUPT
+&105 constant EICRA \ External Interrupt Control Register A
+ $30 constant EICRA_ISC2 \ External Interrupt Sense Control Bit
+ $0C constant EICRA_ISC1 \ External Interrupt Sense Control Bit
+ $03 constant EICRA_ISC0 \ External Interrupt Sense Control Bit
+&61 constant EIMSK \ External Interrupt Mask Register
+ $07 constant EIMSK_INT \ External Interrupt Request 2 Enable
+&60 constant EIFR \ External Interrupt Flag Register
+ $07 constant EIFR_INTF \ External Interrupt Flags
+&115 constant PCMSK3 \ Pin Change Mask Register 3
+ $FF constant PCMSK3_PCINT \ Pin Change Enable Masks
+&109 constant PCMSK2 \ Pin Change Mask Register 2
+ $FF constant PCMSK2_PCINT \ Pin Change Enable Masks
+&108 constant PCMSK1 \ Pin Change Mask Register 1
+ $FF constant PCMSK1_PCINT \ Pin Change Enable Masks
+&107 constant PCMSK0 \ Pin Change Mask Register 0
+ $FF constant PCMSK0_PCINT \ Pin Change Enable Masks
+&59 constant PCIFR \ Pin Change Interrupt Flag Register
+ $0F constant PCIFR_PCIF \ Pin Change Interrupt Flags
+&104 constant PCICR \ Pin Change Interrupt Control Register
+ $0F constant PCICR_PCIE \ Pin Change Interrupt Enables
+\ AD_CONVERTER
+&124 constant ADMUX \ The ADC multiplexer Selection Register
+ $C0 constant ADMUX_REFS \ Reference Selection Bits
+ $20 constant ADMUX_ADLAR \ Left Adjust Result
+ $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
+&120 constant ADC \ ADC Data Register Bytes
+&122 constant ADCSRA \ The ADC Control and Status register A
+ $80 constant ADCSRA_ADEN \ ADC Enable
+ $40 constant ADCSRA_ADSC \ ADC Start Conversion
+ $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
+ $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
+ $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
+ $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
+&126 constant DIDR0 \ Digital Input Disable Register
+ $80 constant DIDR0_ADC7D \
+ $40 constant DIDR0_ADC6D \
+ $20 constant DIDR0_ADC5D \
+ $10 constant DIDR0_ADC4D \
+ $08 constant DIDR0_ADC3D \
+ $04 constant DIDR0_ADC2D \
+ $02 constant DIDR0_ADC1D \
+ $01 constant DIDR0_ADC0D \
+\ JTAG
+&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
+&85 constant MCUCR \ MCU Control Register
+ $80 constant MCUCR_JTD \ JTAG Interface Disable
+&84 constant MCUSR \ MCU Status Register
+ $10 constant MCUSR_JTRF \ JTAG Reset Flag
+\ EEPROM
+&65 constant EEAR \ EEPROM Address Register Low Bytes
+&64 constant EEDR \ EEPROM Data Register
+&63 constant EECR \ EEPROM Control Register
+ $30 constant EECR_EEPM \ EEPROM Programming Mode Bits
+ $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
+ $04 constant EECR_EEMPE \ EEPROM Master Write Enable
+ $02 constant EECR_EEPE \ EEPROM Write Enable
+ $01 constant EECR_EERE \ EEPROM Read Enable
+\ TWI
+&189 constant TWAMR \ TWI (Slave) Address Mask Register
+ $FE constant TWAMR_TWAM \
+&184 constant TWBR \ TWI Bit Rate register
+&188 constant TWCR \ TWI Control Register
+ $80 constant TWCR_TWINT \ TWI Interrupt Flag
+ $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
+ $20 constant TWCR_TWSTA \ TWI Start Condition Bit
+ $10 constant TWCR_TWSTO \ TWI Stop Condition Bit
+ $08 constant TWCR_TWWC \ TWI Write Collition Flag
+ $04 constant TWCR_TWEN \ TWI Enable Bit
+ $01 constant TWCR_TWIE \ TWI Interrupt Enable
+&185 constant TWSR \ TWI Status Register
+ $F8 constant TWSR_TWS \ TWI Status
+ $03 constant TWSR_TWPS \ TWI Prescaler
+&187 constant TWDR \ TWI Data register
+&186 constant TWAR \ TWI (Slave) Address register
+ $FE constant TWAR_TWA \ TWI (Slave) Address register Bits
+ $01 constant TWAR_TWGCE \ TWI General Call Recognition Enable Bit
+\ USART1
+&206 constant UDR1 \ USART I/O Data Register
+&200 constant UCSR1A \ USART Control and Status Register A
+ $80 constant UCSR1A_RXC1 \ USART Receive Complete
+ $40 constant UCSR1A_TXC1 \ USART Transmitt Complete
+ $20 constant UCSR1A_UDRE1 \ USART Data Register Empty
+ $10 constant UCSR1A_FE1 \ Framing Error
+ $08 constant UCSR1A_DOR1 \ Data overRun
+ $04 constant UCSR1A_UPE1 \ Parity Error
+ $02 constant UCSR1A_U2X1 \ Double the USART transmission speed
+ $01 constant UCSR1A_MPCM1 \ Multi-processor Communication Mode
+&201 constant UCSR1B \ USART Control and Status Register B
+ $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable
+ $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable
+ $20 constant UCSR1B_UDRIE1 \ USART Data register Empty Interrupt Enable
+ $10 constant UCSR1B_RXEN1 \ Receiver Enable
+ $08 constant UCSR1B_TXEN1 \ Transmitter Enable
+ $04 constant UCSR1B_UCSZ12 \ Character Size
+ $02 constant UCSR1B_RXB81 \ Receive Data Bit 8
+ $01 constant UCSR1B_TXB81 \ Transmit Data Bit 8
+&202 constant UCSR1C \ USART Control and Status Register C
+ $C0 constant UCSR1C_UMSEL1 \ USART Mode Select
+ $30 constant UCSR1C_UPM1 \ Parity Mode Bits
+ $08 constant UCSR1C_USBS1 \ Stop Bit Select
+ $06 constant UCSR1C_UCSZ1 \ Character Size
+ $01 constant UCSR1C_UCPOL1 \ Clock Polarity
+&204 constant UBRR1 \ USART Baud Rate Register Bytes
+\ SPI
+&78 constant SPDR \ SPI Data Register
+&77 constant SPSR \ SPI Status Register
+ $80 constant SPSR_SPIF \ SPI Interrupt Flag
+ $40 constant SPSR_WCOL \ Write Collision Flag
+ $01 constant SPSR_SPI2X \ Double SPI Speed Bit
+&76 constant SPCR \ SPI Control Register
+ $80 constant SPCR_SPIE \ SPI Interrupt Enable
+ $40 constant SPCR_SPE \ SPI Enable
+ $20 constant SPCR_DORD \ Data Order
+ $10 constant SPCR_MSTR \ Master/Slave Select
+ $08 constant SPCR_CPOL \ Clock polarity
+ $04 constant SPCR_CPHA \ Clock Phase
+ $03 constant SPCR_SPR \ SPI Clock Rate Selects
+\ WATCHDOG
+&96 constant WDTCSR \ Watchdog Timer Control Register
+ $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Flag
+ $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Enable
+ $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
+ $10 constant WDTCSR_WDCE \ Watchdog Change Enable
+ $08 constant WDTCSR_WDE \ Watch Dog Enable
+\ CPU
+&95 constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ $08 constant SREG_V \ Two's Complement Overflow Flag
+ $04 constant SREG_N \ Negative Flag
+ $02 constant SREG_Z \ Zero Flag
+ $01 constant SREG_C \ Carry Flag
+&93 constant SP \ Stack Pointer
+&102 constant OSCCAL \ Oscillator Calibration Value
+&97 constant CLKPR \
+ $80 constant CLKPR_CLKPCE \
+ $0F constant CLKPR_CLKPS \
+&83 constant SMCR \ Sleep Mode Control Register
+ $0E constant SMCR_SM \ Sleep Mode Select bits
+ $01 constant SMCR_SE \ Sleep Enable
+&91 constant RAMPZ \ RAM Page Z Select Register
+&75 constant GPIOR2 \ General Purpose IO Register 2
+ $FF constant GPIOR2_GPIOR \ General Purpose IO Register 2 bis
+&74 constant GPIOR1 \ General Purpose IO Register 1
+ $FF constant GPIOR1_GPIOR \ General Purpose IO Register 1 bis
+&62 constant GPIOR0 \ General Purpose IO Register 0
+ $80 constant GPIOR0_GPIOR07 \ General Purpose IO Register 0 bit 7
+ $40 constant GPIOR0_GPIOR06 \ General Purpose IO Register 0 bit 6
+ $20 constant GPIOR0_GPIOR05 \ General Purpose IO Register 0 bit 5
+ $10 constant GPIOR0_GPIOR04 \ General Purpose IO Register 0 bit 4
+ $08 constant GPIOR0_GPIOR03 \ General Purpose IO Register 0 bit 3
+ $04 constant GPIOR0_GPIOR02 \ General Purpose IO Register 0 bit 2
+ $02 constant GPIOR0_GPIOR01 \ General Purpose IO Register 0 bit 1
+ $01 constant GPIOR0_GPIOR00 \ General Purpose IO Register 0 bit 0
+&100 constant PRR0 \ Power Reduction Register0
+ $80 constant PRR0_PRTWI \ Power Reduction TWI
+ $40 constant PRR0_PRTIM2 \ Power Reduction Timer/Counter2
+ $20 constant PRR0_PRTIM0 \ Power Reduction Timer/Counter0
+ $12 constant PRR0_PRUSART \ Power Reduction USARTs
+ $08 constant PRR0_PRTIM1 \ Power Reduction Timer/Counter1
+ $04 constant PRR0_PRSPI \ Power Reduction Serial Peripheral Interface
+ $01 constant PRR0_PRADC \ Power Reduction ADC
+&101 constant PRR1 \ Power Reduction Register1
+ $01 constant PRR1_PRTIM3 \ Power Reduction Timer/Counter3
+
+\ Interrupts
+&2 constant INT0Addr \ External Interrupt Request 0
+&4 constant INT1Addr \ External Interrupt Request 1
+&6 constant INT2Addr \ External Interrupt Request 2
+&8 constant PCINT0Addr \ Pin Change Interrupt Request 0
+&10 constant PCINT1Addr \ Pin Change Interrupt Request 1
+&12 constant PCINT2Addr \ Pin Change Interrupt Request 2
+&14 constant PCINT3Addr \ Pin Change Interrupt Request 3
+&16 constant WDTAddr \ Watchdog Time-out Interrupt
+&18 constant TIMER2_COMPAAddr \ Timer/Counter2 Compare Match A
+&20 constant TIMER2_COMPBAddr \ Timer/Counter2 Compare Match B
+&22 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
+&24 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+&26 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
+&28 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
+&30 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+&32 constant TIMER0_COMPAAddr \ Timer/Counter0 Compare Match A
+&34 constant TIMER0_COMPBAddr \ Timer/Counter0 Compare Match B
+&36 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
+&38 constant SPI__STCAddr \ SPI Serial Transfer Complete
+&40 constant USART0__RXAddr \ USART0, Rx Complete
+&42 constant USART0__UDREAddr \ USART0 Data register Empty
+&44 constant USART0__TXAddr \ USART0, Tx Complete
+&46 constant ANALOG_COMPAddr \ Analog Comparator
+&48 constant ADCAddr \ ADC Conversion Complete
+&50 constant EE_READYAddr \ EEPROM Ready
+&52 constant TWIAddr \ 2-wire Serial Interface
+&54 constant SPM_READYAddr \ Store Program Memory Read
+&56 constant USART1_RXAddr \ USART1 RX complete
+&58 constant USART1_UDREAddr \ USART1 Data Register Empty
+&60 constant USART1_TXAddr \ USART1 TX complete
+&62 constant TIMER3_CAPTAddr \ Timer/Counter3 Capture Event
+&64 constant TIMER3_COMPAAddr \ Timer/Counter3 Compare Match A
+&66 constant TIMER3_COMPBAddr \ Timer/Counter3 Compare Match B
+&68 constant TIMER3_OVFAddr \ Timer/Counter3 Overflow
diff --git a/amforth-6.5/avr8/devices/atmega1284/device.asm b/amforth-6.5/avr8/devices/atmega1284/device.asm
new file mode 100644
index 0000000..6d89a60
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega1284/device.asm
@@ -0,0 +1,135 @@
+; Partname: ATmega1284
+; generated automatically, do not edit
+
+.nolist
+ .include "m1284def.inc"
+.list
+
+.equ ramstart = 256
+.equ CELLSIZE = 2
+.macro readflashcell
+ clr temp7
+ lsl zl
+ rol zh
+ rol temp7
+ out_ RAMPZ, temp7
+ elpm @0, Z+
+ elpm @1, Z+
+.endmacro
+.macro writeflashcell
+ clr temp7
+ lsl zl
+ rol zh
+ rol temp7
+ out_ RAMPZ, temp7
+.endmacro
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_USART0 = 0
+.set WANT_PORTA = 0
+.set WANT_PORTB = 0
+.set WANT_PORTC = 0
+.set WANT_PORTD = 0
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_TIMER_COUNTER_2 = 0
+.set WANT_TIMER_COUNTER_3 = 0
+.set WANT_BOOT_LOAD = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_AD_CONVERTER = 0
+.set WANT_JTAG = 0
+.set WANT_EEPROM = 0
+.set WANT_TWI = 0
+.set WANT_USART1 = 0
+.set WANT_SPI = 0
+.set WANT_WATCHDOG = 0
+.set WANT_CPU = 0
+.equ intvecsize = 2 ; please verify; flash size: 131072 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.org 2
+ rcall isr ; External Interrupt Request 0
+.org 4
+ rcall isr ; External Interrupt Request 1
+.org 6
+ rcall isr ; External Interrupt Request 2
+.org 8
+ rcall isr ; Pin Change Interrupt Request 0
+.org 10
+ rcall isr ; Pin Change Interrupt Request 1
+.org 12
+ rcall isr ; Pin Change Interrupt Request 2
+.org 14
+ rcall isr ; Pin Change Interrupt Request 3
+.org 16
+ rcall isr ; Watchdog Time-out Interrupt
+.org 18
+ rcall isr ; Timer/Counter2 Compare Match A
+.org 20
+ rcall isr ; Timer/Counter2 Compare Match B
+.org 22
+ rcall isr ; Timer/Counter2 Overflow
+.org 24
+ rcall isr ; Timer/Counter1 Capture Event
+.org 26
+ rcall isr ; Timer/Counter1 Compare Match A
+.org 28
+ rcall isr ; Timer/Counter1 Compare Match B
+.org 30
+ rcall isr ; Timer/Counter1 Overflow
+.org 32
+ rcall isr ; Timer/Counter0 Compare Match A
+.org 34
+ rcall isr ; Timer/Counter0 Compare Match B
+.org 36
+ rcall isr ; Timer/Counter0 Overflow
+.org 38
+ rcall isr ; SPI Serial Transfer Complete
+.org 40
+ rcall isr ; USART0, Rx Complete
+.org 42
+ rcall isr ; USART0 Data register Empty
+.org 44
+ rcall isr ; USART0, Tx Complete
+.org 46
+ rcall isr ; Analog Comparator
+.org 48
+ rcall isr ; ADC Conversion Complete
+.org 50
+ rcall isr ; EEPROM Ready
+.org 52
+ rcall isr ; 2-wire Serial Interface
+.org 54
+ rcall isr ; Store Program Memory Read
+.org 56
+ rcall isr ; USART1 RX complete
+.org 58
+ rcall isr ; USART1 Data Register Empty
+.org 60
+ rcall isr ; USART1 TX complete
+.org 62
+ rcall isr ; Timer/Counter3 Capture Event
+.org 64
+ rcall isr ; Timer/Counter3 Compare Match A
+.org 66
+ rcall isr ; Timer/Counter3 Compare Match B
+.org 68
+ rcall isr ; Timer/Counter3 Overflow
+.equ INTVECTORS = 35
+.nooverlap
+
+; compatability layer (maybe empty)
+
+; controller data area, environment query mcu-info
+mcu_info:
+mcu_ramsize:
+ .dw 16384
+mcu_eepromsize:
+ .dw 4096
+mcu_maxdp:
+ .dw 65535
+mcu_numints:
+ .dw 35
+mcu_name:
+ .dw 10
+ .db "ATmega1284"
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega1284/device.inc b/amforth-6.5/avr8/devices/atmega1284/device.inc
new file mode 100644
index 0000000..0242304
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega1284/device.inc
@@ -0,0 +1,1263 @@
+; Partname: ATmega1284
+; generated automatically, no not edit
+
+.if WANT_ANALOG_COMPARATOR == 1
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Control and Status Register B
+VE_ADCSRB:
+ .dw $ff06
+ .db "ADCSRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRB
+XT_ADCSRB:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRB:
+ .dw 123
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Control And Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw 80
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 1
+VE_DIDR1:
+ .dw $ff05
+ .db "DIDR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR1
+XT_DIDR1:
+ .dw PFA_DOVARIABLE
+PFA_DIDR1:
+ .dw 127
+
+.endif
+.if WANT_USART0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR0:
+ .dw $ff04
+ .db "UDR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR0
+XT_UDR0:
+ .dw PFA_DOVARIABLE
+PFA_UDR0:
+ .dw 198
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR0A:
+ .dw $ff06
+ .db "UCSR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0A
+XT_UCSR0A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0A:
+ .dw 192
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR0B:
+ .dw $ff06
+ .db "UCSR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0B
+XT_UCSR0B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0B:
+ .dw 193
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR0C:
+ .dw $ff06
+ .db "UCSR0C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0C
+XT_UCSR0C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0C:
+ .dw 194
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Bytes
+VE_UBRR0:
+ .dw $ff05
+ .db "UBRR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR0
+XT_UBRR0:
+ .dw PFA_DOVARIABLE
+PFA_UBRR0:
+ .dw 196
+
+.endif
+.if WANT_PORTA == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Register
+VE_PORTA:
+ .dw $ff05
+ .db "PORTA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTA
+XT_PORTA:
+ .dw PFA_DOVARIABLE
+PFA_PORTA:
+ .dw 34
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Direction Register
+VE_DDRA:
+ .dw $ff04
+ .db "DDRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRA
+XT_DDRA:
+ .dw PFA_DOVARIABLE
+PFA_DDRA:
+ .dw 33
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Input Pins
+VE_PINA:
+ .dw $ff04
+ .db "PINA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINA
+XT_PINA:
+ .dw PFA_DOVARIABLE
+PFA_PINA:
+ .dw 32
+
+.endif
+.if WANT_PORTB == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw 37
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw 36
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw 35
+
+.endif
+.if WANT_PORTC == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Register
+VE_PORTC:
+ .dw $ff05
+ .db "PORTC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTC
+XT_PORTC:
+ .dw PFA_DOVARIABLE
+PFA_PORTC:
+ .dw 40
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Direction Register
+VE_DDRC:
+ .dw $ff04
+ .db "DDRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRC
+XT_DDRC:
+ .dw PFA_DOVARIABLE
+PFA_DDRC:
+ .dw 39
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Input Pins
+VE_PINC:
+ .dw $ff04
+ .db "PINC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINC
+XT_PINC:
+ .dw PFA_DOVARIABLE
+PFA_PINC:
+ .dw 38
+
+.endif
+.if WANT_PORTD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw 43
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw 42
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw 41
+
+.endif
+.if WANT_TIMER_COUNTER_0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0B:
+ .dw $ff05
+ .db "OCR0B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0B
+XT_OCR0B:
+ .dw PFA_DOVARIABLE
+PFA_OCR0B:
+ .dw 72
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0A:
+ .dw $ff05
+ .db "OCR0A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0A
+XT_OCR0A:
+ .dw PFA_DOVARIABLE
+PFA_OCR0A:
+ .dw 71
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw 70
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register B
+VE_TCCR0B:
+ .dw $ff06
+ .db "TCCR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0B
+XT_TCCR0B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0B:
+ .dw 69
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register A
+VE_TCCR0A:
+ .dw $ff06
+ .db "TCCR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0A
+XT_TCCR0A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0A:
+ .dw 68
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Mask Register
+VE_TIMSK0:
+ .dw $ff06
+ .db "TIMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK0
+XT_TIMSK0:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK0:
+ .dw 110
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Flag register
+VE_TIFR0:
+ .dw $ff05
+ .db "TIFR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR0
+XT_TIFR0:
+ .dw PFA_DOVARIABLE
+PFA_TIFR0:
+ .dw 53
+; ( -- addr ) System Constant
+; R( -- )
+; General Timer/Counter Control Register
+VE_GTCCR:
+ .dw $ff05
+ .db "GTCCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GTCCR
+XT_GTCCR:
+ .dw PFA_DOVARIABLE
+PFA_GTCCR:
+ .dw 67
+
+.endif
+.if WANT_TIMER_COUNTER_1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Mask Register
+VE_TIMSK1:
+ .dw $ff06
+ .db "TIMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK1
+XT_TIMSK1:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK1:
+ .dw 111
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Flag register
+VE_TIFR1:
+ .dw $ff05
+ .db "TIFR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR1
+XT_TIFR1:
+ .dw PFA_DOVARIABLE
+PFA_TIFR1:
+ .dw 54
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw 128
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw 129
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register C
+VE_TCCR1C:
+ .dw $ff06
+ .db "TCCR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1C
+XT_TCCR1C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1C:
+ .dw 130
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Bytes
+VE_TCNT1:
+ .dw $ff05
+ .db "TCNT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1
+XT_TCNT1:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1:
+ .dw 132
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register A Bytes
+VE_OCR1A:
+ .dw $ff05
+ .db "OCR1A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1A
+XT_OCR1A:
+ .dw PFA_DOVARIABLE
+PFA_OCR1A:
+ .dw 136
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register B Bytes
+VE_OCR1B:
+ .dw $ff05
+ .db "OCR1B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1B
+XT_OCR1B:
+ .dw PFA_DOVARIABLE
+PFA_OCR1B:
+ .dw 138
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Bytes
+VE_ICR1:
+ .dw $ff04
+ .db "ICR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1
+XT_ICR1:
+ .dw PFA_DOVARIABLE
+PFA_ICR1:
+ .dw 134
+
+.endif
+.if WANT_TIMER_COUNTER_2 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Mask register
+VE_TIMSK2:
+ .dw $ff06
+ .db "TIMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK2
+XT_TIMSK2:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK2:
+ .dw 112
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Flag Register
+VE_TIFR2:
+ .dw $ff05
+ .db "TIFR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR2
+XT_TIFR2:
+ .dw PFA_DOVARIABLE
+PFA_TIFR2:
+ .dw 55
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register A
+VE_TCCR2A:
+ .dw $ff06
+ .db "TCCR2A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2A
+XT_TCCR2A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2A:
+ .dw 176
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register B
+VE_TCCR2B:
+ .dw $ff06
+ .db "TCCR2B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2B
+XT_TCCR2B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2B:
+ .dw 177
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2
+VE_TCNT2:
+ .dw $ff05
+ .db "TCNT2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT2
+XT_TCNT2:
+ .dw PFA_DOVARIABLE
+PFA_TCNT2:
+ .dw 178
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register B
+VE_OCR2B:
+ .dw $ff05
+ .db "OCR2B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2B
+XT_OCR2B:
+ .dw PFA_DOVARIABLE
+PFA_OCR2B:
+ .dw 180
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register A
+VE_OCR2A:
+ .dw $ff05
+ .db "OCR2A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2A
+XT_OCR2A:
+ .dw PFA_DOVARIABLE
+PFA_OCR2A:
+ .dw 179
+; ( -- addr ) System Constant
+; R( -- )
+; Asynchronous Status Register
+VE_ASSR:
+ .dw $ff04
+ .db "ASSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ASSR
+XT_ASSR:
+ .dw PFA_DOVARIABLE
+PFA_ASSR:
+ .dw 182
+
+.endif
+.if WANT_TIMER_COUNTER_3 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Interrupt Mask Register
+VE_TIMSK3:
+ .dw $ff06
+ .db "TIMSK3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK3
+XT_TIMSK3:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK3:
+ .dw 113
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Flag register
+VE_TIFR3:
+ .dw $ff05
+ .db "TIFR3",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR3
+XT_TIFR3:
+ .dw PFA_DOVARIABLE
+PFA_TIFR3:
+ .dw 56
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Control Register A
+VE_TCCR3A:
+ .dw $ff06
+ .db "TCCR3A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR3A
+XT_TCCR3A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR3A:
+ .dw 144
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Control Register B
+VE_TCCR3B:
+ .dw $ff06
+ .db "TCCR3B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR3B
+XT_TCCR3B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR3B:
+ .dw 145
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Control Register C
+VE_TCCR3C:
+ .dw $ff06
+ .db "TCCR3C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR3C
+XT_TCCR3C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR3C:
+ .dw 146
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Bytes
+VE_TCNT3:
+ .dw $ff05
+ .db "TCNT3",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT3
+XT_TCNT3:
+ .dw PFA_DOVARIABLE
+PFA_TCNT3:
+ .dw 148
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Output Compare Register A Bytes
+VE_OCR3A:
+ .dw $ff05
+ .db "OCR3A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR3A
+XT_OCR3A:
+ .dw PFA_DOVARIABLE
+PFA_OCR3A:
+ .dw 152
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Output Compare Register B Bytes
+VE_OCR3B:
+ .dw $ff05
+ .db "OCR3B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR3B
+XT_OCR3B:
+ .dw PFA_DOVARIABLE
+PFA_OCR3B:
+ .dw 154
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Input Capture Register Bytes
+VE_ICR3:
+ .dw $ff04
+ .db "ICR3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR3
+XT_ICR3:
+ .dw PFA_DOVARIABLE
+PFA_ICR3:
+ .dw 150
+
+.endif
+.if WANT_BOOT_LOAD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control Register
+VE_SPMCSR:
+ .dw $ff06
+ .db "SPMCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCSR
+XT_SPMCSR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCSR:
+ .dw 87
+
+.endif
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register A
+VE_EICRA:
+ .dw $ff05
+ .db "EICRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRA
+XT_EICRA:
+ .dw PFA_DOVARIABLE
+PFA_EICRA:
+ .dw 105
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Mask Register
+VE_EIMSK:
+ .dw $ff05
+ .db "EIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIMSK
+XT_EIMSK:
+ .dw PFA_DOVARIABLE
+PFA_EIMSK:
+ .dw 61
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Flag Register
+VE_EIFR:
+ .dw $ff04
+ .db "EIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIFR
+XT_EIFR:
+ .dw PFA_DOVARIABLE
+PFA_EIFR:
+ .dw 60
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 3
+VE_PCMSK3:
+ .dw $ff06
+ .db "PCMSK3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK3
+XT_PCMSK3:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK3:
+ .dw 115
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 2
+VE_PCMSK2:
+ .dw $ff06
+ .db "PCMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK2
+XT_PCMSK2:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK2:
+ .dw 109
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 1
+VE_PCMSK1:
+ .dw $ff06
+ .db "PCMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK1
+XT_PCMSK1:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK1:
+ .dw 108
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 0
+VE_PCMSK0:
+ .dw $ff06
+ .db "PCMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK0
+XT_PCMSK0:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK0:
+ .dw 107
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Interrupt Flag Register
+VE_PCIFR:
+ .dw $ff05
+ .db "PCIFR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCIFR
+XT_PCIFR:
+ .dw PFA_DOVARIABLE
+PFA_PCIFR:
+ .dw 59
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Interrupt Control Register
+VE_PCICR:
+ .dw $ff05
+ .db "PCICR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCICR
+XT_PCICR:
+ .dw PFA_DOVARIABLE
+PFA_PCICR:
+ .dw 104
+
+.endif
+.if WANT_AD_CONVERTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC multiplexer Selection Register
+VE_ADMUX:
+ .dw $ff05
+ .db "ADMUX",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADMUX
+XT_ADMUX:
+ .dw PFA_DOVARIABLE
+PFA_ADMUX:
+ .dw 124
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register Bytes
+VE_ADC:
+ .dw $ff03
+ .db "ADC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADC
+XT_ADC:
+ .dw PFA_DOVARIABLE
+PFA_ADC:
+ .dw 120
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register A
+VE_ADCSRA:
+ .dw $ff06
+ .db "ADCSRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRA
+XT_ADCSRA:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRA:
+ .dw 122
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register
+VE_DIDR0:
+ .dw $ff05
+ .db "DIDR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR0
+XT_DIDR0:
+ .dw PFA_DOVARIABLE
+PFA_DIDR0:
+ .dw 126
+
+.endif
+.if WANT_JTAG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; On-Chip Debug Related Register in I/O Memory
+VE_OCDR:
+ .dw $ff04
+ .db "OCDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCDR
+XT_OCDR:
+ .dw PFA_DOVARIABLE
+PFA_OCDR:
+ .dw 81
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw 85
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Status Register
+VE_MCUSR:
+ .dw $ff05
+ .db "MCUSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUSR
+XT_MCUSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUSR:
+ .dw 84
+
+.endif
+.if WANT_EEPROM == 1
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Address Register Low Bytes
+VE_EEAR:
+ .dw $ff04
+ .db "EEAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEAR
+XT_EEAR:
+ .dw PFA_DOVARIABLE
+PFA_EEAR:
+ .dw 65
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw 64
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw 63
+
+.endif
+.if WANT_TWI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; TWI (Slave) Address Mask Register
+VE_TWAMR:
+ .dw $ff05
+ .db "TWAMR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWAMR
+XT_TWAMR:
+ .dw PFA_DOVARIABLE
+PFA_TWAMR:
+ .dw 189
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Bit Rate register
+VE_TWBR:
+ .dw $ff04
+ .db "TWBR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWBR
+XT_TWBR:
+ .dw PFA_DOVARIABLE
+PFA_TWBR:
+ .dw 184
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Control Register
+VE_TWCR:
+ .dw $ff04
+ .db "TWCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWCR
+XT_TWCR:
+ .dw PFA_DOVARIABLE
+PFA_TWCR:
+ .dw 188
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Status Register
+VE_TWSR:
+ .dw $ff04
+ .db "TWSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWSR
+XT_TWSR:
+ .dw PFA_DOVARIABLE
+PFA_TWSR:
+ .dw 185
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Data register
+VE_TWDR:
+ .dw $ff04
+ .db "TWDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWDR
+XT_TWDR:
+ .dw PFA_DOVARIABLE
+PFA_TWDR:
+ .dw 187
+; ( -- addr ) System Constant
+; R( -- )
+; TWI (Slave) Address register
+VE_TWAR:
+ .dw $ff04
+ .db "TWAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWAR
+XT_TWAR:
+ .dw PFA_DOVARIABLE
+PFA_TWAR:
+ .dw 186
+
+.endif
+.if WANT_USART1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR1:
+ .dw $ff04
+ .db "UDR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR1
+XT_UDR1:
+ .dw PFA_DOVARIABLE
+PFA_UDR1:
+ .dw 206
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR1A:
+ .dw $ff06
+ .db "UCSR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1A
+XT_UCSR1A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1A:
+ .dw 200
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR1B:
+ .dw $ff06
+ .db "UCSR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1B
+XT_UCSR1B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1B:
+ .dw 201
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR1C:
+ .dw $ff06
+ .db "UCSR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1C
+XT_UCSR1C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1C:
+ .dw 202
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Bytes
+VE_UBRR1:
+ .dw $ff05
+ .db "UBRR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR1
+XT_UBRR1:
+ .dw PFA_DOVARIABLE
+PFA_UBRR1:
+ .dw 204
+
+.endif
+.if WANT_SPI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR:
+ .dw $ff04
+ .db "SPDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR
+XT_SPDR:
+ .dw PFA_DOVARIABLE
+PFA_SPDR:
+ .dw 78
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR:
+ .dw $ff04
+ .db "SPSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR
+XT_SPSR:
+ .dw PFA_DOVARIABLE
+PFA_SPSR:
+ .dw 77
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR:
+ .dw $ff04
+ .db "SPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR
+XT_SPCR:
+ .dw PFA_DOVARIABLE
+PFA_SPCR:
+ .dw 76
+
+.endif
+.if WANT_WATCHDOG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCSR:
+ .dw $ff06
+ .db "WDTCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCSR
+XT_WDTCSR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCSR:
+ .dw 96
+
+.endif
+.if WANT_CPU == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw 95
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer
+VE_SP:
+ .dw $ff02
+ .db "SP"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SP
+XT_SP:
+ .dw PFA_DOVARIABLE
+PFA_SP:
+ .dw 93
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Calibration Value
+VE_OSCCAL:
+ .dw $ff06
+ .db "OSCCAL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSCCAL
+XT_OSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_OSCCAL:
+ .dw 102
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_CLKPR:
+ .dw $ff05
+ .db "CLKPR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKPR
+XT_CLKPR:
+ .dw PFA_DOVARIABLE
+PFA_CLKPR:
+ .dw 97
+; ( -- addr ) System Constant
+; R( -- )
+; Sleep Mode Control Register
+VE_SMCR:
+ .dw $ff04
+ .db "SMCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SMCR
+XT_SMCR:
+ .dw PFA_DOVARIABLE
+PFA_SMCR:
+ .dw 83
+; ( -- addr ) System Constant
+; R( -- )
+; RAM Page Z Select Register
+VE_RAMPZ:
+ .dw $ff05
+ .db "RAMPZ",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_RAMPZ
+XT_RAMPZ:
+ .dw PFA_DOVARIABLE
+PFA_RAMPZ:
+ .dw 91
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 2
+VE_GPIOR2:
+ .dw $ff06
+ .db "GPIOR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR2
+XT_GPIOR2:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR2:
+ .dw 75
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 1
+VE_GPIOR1:
+ .dw $ff06
+ .db "GPIOR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR1
+XT_GPIOR1:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR1:
+ .dw 74
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 0
+VE_GPIOR0:
+ .dw $ff06
+ .db "GPIOR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR0
+XT_GPIOR0:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR0:
+ .dw 62
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register0
+VE_PRR0:
+ .dw $ff04
+ .db "PRR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR0
+XT_PRR0:
+ .dw PFA_DOVARIABLE
+PFA_PRR0:
+ .dw 100
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register1
+VE_PRR1:
+ .dw $ff04
+ .db "PRR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR1
+XT_PRR1:
+ .dw PFA_DOVARIABLE
+PFA_PRR1:
+ .dw 101
+
+.endif
diff --git a/amforth-6.5/avr8/devices/atmega1284/device.py b/amforth-6.5/avr8/devices/atmega1284/device.py
new file mode 100644
index 0000000..0b316cb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega1284/device.py
@@ -0,0 +1,421 @@
+# Generated Automatically
+
+# Partname ATmega1284
+
+MCUREGS = {
+# Interrupt Vectors
+ 'INT0Addr' : '#2', # External Interrupt Request 0
+ 'INT1Addr' : '#4', # External Interrupt Request 1
+ 'INT2Addr' : '#6', # External Interrupt Request 2
+ 'PCINT0Addr' : '#8', # Pin Change Interrupt Request 0
+ 'PCINT1Addr' : '#10', # Pin Change Interrupt Request 1
+ 'PCINT2Addr' : '#12', # Pin Change Interrupt Request 2
+ 'PCINT3Addr' : '#14', # Pin Change Interrupt Request 3
+ 'WDTAddr' : '#16', # Watchdog Time-out Interrupt
+ 'TIMER2_COMPAAddr' : '#18', # Timer/Counter2 Compare Match A
+ 'TIMER2_COMPBAddr' : '#20', # Timer/Counter2 Compare Match B
+ 'TIMER2_OVFAddr' : '#22', # Timer/Counter2 Overflow
+ 'TIMER1_CAPTAddr' : '#24', # Timer/Counter1 Capture Event
+ 'TIMER1_COMPAAddr' : '#26', # Timer/Counter1 Compare Match A
+ 'TIMER1_COMPBAddr' : '#28', # Timer/Counter1 Compare Match B
+ 'TIMER1_OVFAddr' : '#30', # Timer/Counter1 Overflow
+ 'TIMER0_COMPAAddr' : '#32', # Timer/Counter0 Compare Match A
+ 'TIMER0_COMPBAddr' : '#34', # Timer/Counter0 Compare Match B
+ 'TIMER0_OVFAddr' : '#36', # Timer/Counter0 Overflow
+ 'SPI_STCAddr' : '#38', # SPI Serial Transfer Complete
+ 'USART0_RXAddr' : '#40', # USART0, Rx Complete
+ 'USART0_UDREAddr' : '#42', # USART0 Data register Empty
+ 'USART0_TXAddr' : '#44', # USART0, Tx Complete
+ 'ANALOG_COMPAddr' : '#46', # Analog Comparator
+ 'ADCAddr' : '#48', # ADC Conversion Complete
+ 'EE_READYAddr' : '#50', # EEPROM Ready
+ 'TWIAddr' : '#52', # 2-wire Serial Interface
+ 'SPM_READYAddr' : '#54', # Store Program Memory Read
+ 'USART1_RXAddr' : '#56', # USART1 RX complete
+ 'USART1_UDREAddr' : '#58', # USART1 Data Register Empty
+ 'USART1_TXAddr' : '#60', # USART1 TX complete
+ 'TIMER3_CAPTAddr' : '#62', # Timer/Counter3 Capture Event
+ 'TIMER3_COMPAAddr' : '#64', # Timer/Counter3 Compare Match A
+ 'TIMER3_COMPBAddr' : '#66', # Timer/Counter3 Compare Match B
+ 'TIMER3_OVFAddr' : '#68', # Timer/Counter3 Overflow
+
+# Module ANALOG_COMPARATOR
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
+ 'ACSR' : '$50', # Analog Comparator Control And
+ 'ACSR_ACD': '$80', # Analog Comparator Disable
+ 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
+ 'ACSR_ACO': '$20', # Analog Compare Output
+ 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
+ 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
+ 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
+ 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
+ 'DIDR1' : '$7f', # Digital Input Disable Register
+ 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
+ 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
+
+# Module USART0
+ 'UDR0' : '$c6', # USART I/O Data Register
+ 'UCSR0A' : '$c0', # USART Control and Status Regis
+ 'UCSR0A_RXC0': '$80', # USART Receive Complete
+ 'UCSR0A_TXC0': '$40', # USART Transmitt Complete
+ 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
+ 'UCSR0A_FE0': '$10', # Framing Error
+ 'UCSR0A_DOR0': '$8', # Data overRun
+ 'UCSR0A_UPE0': '$4', # Parity Error
+ 'UCSR0A_U2X0': '$2', # Double the USART transmission
+ 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
+ 'UCSR0B' : '$c1', # USART Control and Status Regis
+ 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
+ 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
+ 'UCSR0B_UDRIE0': '$20', # USART Data register Empty Inte
+ 'UCSR0B_RXEN0': '$10', # Receiver Enable
+ 'UCSR0B_TXEN0': '$8', # Transmitter Enable
+ 'UCSR0B_UCSZ02': '$4', # Character Size
+ 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
+ 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
+ 'UCSR0C' : '$c2', # USART Control and Status Regis
+ 'UCSR0C_UMSEL0': '$c0', # USART Mode Select
+ 'UCSR0C_UPM0': '$30', # Parity Mode Bits
+ 'UCSR0C_USBS0': '$8', # Stop Bit Select
+ 'UCSR0C_UCSZ0': '$6', # Character Size
+ 'UCSR0C_UCPOL0': '$1', # Clock Polarity
+ 'UBRR0' : '$c4', # USART Baud Rate Register Byte
+
+# Module PORTA
+ 'PORTA' : '$22', # Port A Data Register
+ 'DDRA' : '$21', # Port A Data Direction Register
+ 'PINA' : '$20', # Port A Input Pins
+
+# Module PORTB
+ 'PORTB' : '$25', # Port B Data Register
+ 'DDRB' : '$24', # Port B Data Direction Register
+ 'PINB' : '$23', # Port B Input Pins
+
+# Module PORTC
+ 'PORTC' : '$28', # Port C Data Register
+ 'DDRC' : '$27', # Port C Data Direction Register
+ 'PINC' : '$26', # Port C Input Pins
+
+# Module PORTD
+ 'PORTD' : '$2b', # Port D Data Register
+ 'DDRD' : '$2a', # Port D Data Direction Register
+ 'PIND' : '$29', # Port D Input Pins
+
+# Module TIMER_COUNTER_0
+ 'OCR0B' : '$48', # Timer/Counter0 Output Compare
+ 'OCR0A' : '$47', # Timer/Counter0 Output Compare
+ 'TCNT0' : '$46', # Timer/Counter0
+ 'TCCR0B' : '$45', # Timer/Counter Control Register
+ 'TCCR0B_FOC0A': '$80', # Force Output Compare A
+ 'TCCR0B_FOC0B': '$40', # Force Output Compare B
+ 'TCCR0B_WGM02': '$8', #
+ 'TCCR0B_CS0': '$7', # Clock Select
+ 'TCCR0A' : '$44', # Timer/Counter Control Registe
+ 'TCCR0A_COM0A': '$c0', # Compare Output Mode, Phase Cor
+ 'TCCR0A_COM0B': '$30', # Compare Output Mode, Fast PWm
+ 'TCCR0A_WGM0': '$3', # Waveform Generation Mode
+ 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
+ 'TIMSK0_OCIE0B': '$4', # Timer/Counter0 Output Compare
+ 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
+ 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
+ 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
+ 'TIFR0_OCF0B': '$4', # Timer/Counter0 Output Compare
+ 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
+ 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSRSYNC': '$1', # Prescaler Reset Timer/Counter1
+
+# Module TIMER_COUNTER_1
+ 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
+ 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
+ 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
+ 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
+ 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
+ 'TIFR1' : '$36', # Timer/Counter Interrupt Flag r
+ 'TIFR1_ICF1': '$20', # Timer/Counter1 Input Capture F
+ 'TIFR1_OCF1B': '$4', # Timer/Counter1 Output Compare
+ 'TIFR1_OCF1A': '$2', # Timer/Counter1 Output Compare
+ 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
+ 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
+ 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
+ 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
+ 'TCCR1A_WGM1': '$3', # Pulse Width Modulator Select B
+ 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
+ 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
+ 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
+ 'TCCR1B_WGM1': '$18', # Waveform Generation Mode Bits
+ 'TCCR1B_CS1': '$7', # Clock Select1 bits
+ 'TCCR1C' : '$82', # Timer/Counter1 Control Registe
+ 'TCCR1C_FOC1A': '$80', # Force Output Compare for Chann
+ 'TCCR1C_FOC1B': '$40', # Force Output Compare for Chann
+ 'TCNT1' : '$84', # Timer/Counter1 Bytes
+ 'OCR1A' : '$88', # Timer/Counter1 Output Compare
+ 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
+ 'ICR1' : '$86', # Timer/Counter1 Input Capture R
+
+# Module TIMER_COUNTER_2
+ 'TIMSK2' : '$70', # Timer/Counter Interrupt Mask r
+ 'TIMSK2_OCIE2B': '$4', # Timer/Counter2 Output Compare
+ 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
+ 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
+ 'TIFR2' : '$37', # Timer/Counter Interrupt Flag R
+ 'TIFR2_OCF2B': '$4', # Output Compare Flag 2B
+ 'TIFR2_OCF2A': '$2', # Output Compare Flag 2A
+ 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
+ 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
+ 'TCCR2A_COM2A': '$c0', # Compare Output Mode bits
+ 'TCCR2A_COM2B': '$30', # Compare Output Mode bits
+ 'TCCR2A_WGM2': '$3', # Waveform Genration Mode
+ 'TCCR2B' : '$b1', # Timer/Counter2 Control Registe
+ 'TCCR2B_FOC2A': '$80', # Force Output Compare A
+ 'TCCR2B_FOC2B': '$40', # Force Output Compare B
+ 'TCCR2B_WGM22': '$8', # Waveform Generation Mode
+ 'TCCR2B_CS2': '$7', # Clock Select bits
+ 'TCNT2' : '$b2', # Timer/Counter2
+ 'OCR2B' : '$b4', # Timer/Counter2 Output Compare
+ 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
+ 'ASSR' : '$b6', # Asynchronous Status Register
+ 'ASSR_EXCLK': '$40', # Enable External Clock Input
+ 'ASSR_AS2': '$20', # Asynchronous Timer/Counter2
+ 'ASSR_TCN2UB': '$10', # Timer/Counter2 Update Busy
+ 'ASSR_OCR2AUB': '$8', # Output Compare Register2 Updat
+ 'ASSR_OCR2BUB': '$4', # Output Compare Register 2 Upda
+ 'ASSR_TCR2AUB': '$2', # Timer/Counter Control Register
+ 'ASSR_TCR2BUB': '$1', # Timer/Counter Control Register
+ 'GTCCR' : '$43', # General Timer Counter Control
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSRASY': '$2', # Prescaler Reset Timer/Counter2
+
+# Module TIMER_COUNTER_3
+ 'TIMSK3' : '$71', # Timer/Counter3 Interrupt Mask
+ 'TIMSK3_ICIE3': '$20', # Timer/Counter3 Input Capture I
+ 'TIMSK3_OCIE3B': '$4', # Timer/Counter3 Output Compare
+ 'TIMSK3_OCIE3A': '$2', # Timer/Counter3 Output Compare
+ 'TIMSK3_TOIE3': '$1', # Timer/Counter3 Overflow Interr
+ 'TIFR3' : '$38', # Timer/Counter Interrupt Flag r
+ 'TIFR3_ICF3': '$20', # Timer/Counter3 Input Capture F
+ 'TIFR3_OCF3B': '$4', # Timer/Counter3 Output Compare
+ 'TIFR3_OCF3A': '$2', # Timer/Counter3 Output Compare
+ 'TIFR3_TOV3': '$1', # Timer/Counter3 Overflow Flag
+ 'TCCR3A' : '$90', # Timer/Counter3 Control Registe
+ 'TCCR3A_COM3A': '$c0', # Compare Output Mode 3A, bits
+ 'TCCR3A_COM3B': '$30', # Compare Output Mode 3B, bits
+ 'TCCR3A_WGM3': '$3', # Pulse Width Modulator Select B
+ 'TCCR3B' : '$91', # Timer/Counter3 Control Registe
+ 'TCCR3B_ICNC3': '$80', # Input Capture 3 Noise Canceler
+ 'TCCR3B_ICES3': '$40', # Input Capture 3 Edge Select
+ 'TCCR3B_WGM3': '$18', # Waveform Generation Mode Bits
+ 'TCCR3B_CS3': '$7', # Clock Select3 bits
+ 'TCCR3C' : '$92', # Timer/Counter3 Control Registe
+ 'TCCR3C_FOC3A': '$80', # Force Output Compare for Chann
+ 'TCCR3C_FOC3B': '$40', # Force Output Compare for Chann
+ 'TCNT3' : '$94', # Timer/Counter3 Bytes
+ 'OCR3A' : '$98', # Timer/Counter3 Output Compare
+ 'OCR3B' : '$9a', # Timer/Counter3 Output Compare
+ 'ICR3' : '$96', # Timer/Counter3 Input Capture R
+
+# Module BOOT_LOAD
+ 'SPMCSR' : '$57', # Store Program Memory Control R
+ 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
+ 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
+ 'SPMCSR_SIGRD': '$20', # Signature Row Read
+ 'SPMCSR_RWWSRE': '$10', # Read While Write section read
+ 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
+ 'SPMCSR_PGWRT': '$4', # Page Write
+ 'SPMCSR_PGERS': '$2', # Page Erase
+ 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
+
+# Module EXTERNAL_INTERRUPT
+ 'EICRA' : '$69', # External Interrupt Control Reg
+ 'EICRA_ISC2': '$30', # External Interrupt Sense Contr
+ 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
+ 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
+ 'EIMSK' : '$3d', # External Interrupt Mask Regist
+ 'EIMSK_INT': '$7', # External Interrupt Request 2 E
+ 'EIFR' : '$3c', # External Interrupt Flag Regist
+ 'EIFR_INTF': '$7', # External Interrupt Flags
+ 'PCMSK3' : '$73', # Pin Change Mask Register 3
+ 'PCMSK3_PCINT': '$ff', # Pin Change Enable Masks
+ 'PCMSK2' : '$6d', # Pin Change Mask Register 2
+ 'PCMSK2_PCINT': '$ff', # Pin Change Enable Masks
+ 'PCMSK1' : '$6c', # Pin Change Mask Register 1
+ 'PCMSK1_PCINT': '$ff', # Pin Change Enable Masks
+ 'PCMSK0' : '$6b', # Pin Change Mask Register 0
+ 'PCMSK0_PCINT': '$ff', # Pin Change Enable Masks
+ 'PCIFR' : '$3b', # Pin Change Interrupt Flag Regi
+ 'PCIFR_PCIF': '$f', # Pin Change Interrupt Flags
+ 'PCICR' : '$68', # Pin Change Interrupt Control R
+ 'PCICR_PCIE': '$f', # Pin Change Interrupt Enables
+
+# Module AD_CONVERTER
+ 'ADMUX' : '$7c', # The ADC multiplexer Selection
+ 'ADMUX_REFS': '$c0', # Reference Selection Bits
+ 'ADMUX_ADLAR': '$20', # Left Adjust Result
+ 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
+ 'ADC' : '$78', # ADC Data Register Bytes
+ 'ADCSRA' : '$7a', # The ADC Control and Status reg
+ 'ADCSRA_ADEN': '$80', # ADC Enable
+ 'ADCSRA_ADSC': '$40', # ADC Start Conversion
+ 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
+ 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
+ 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
+ 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
+ 'ADCSRB' : '$7b', # The ADC Control and Status reg
+ 'ADCSRB_ACME': '$40', #
+ 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Source bits
+ 'DIDR0' : '$7e', # Digital Input Disable Register
+ 'DIDR0_ADC7D': '$80', #
+ 'DIDR0_ADC6D': '$40', #
+ 'DIDR0_ADC5D': '$20', #
+ 'DIDR0_ADC4D': '$10', #
+ 'DIDR0_ADC3D': '$8', #
+ 'DIDR0_ADC2D': '$4', #
+ 'DIDR0_ADC1D': '$2', #
+ 'DIDR0_ADC0D': '$1', #
+
+# Module JTAG
+ 'OCDR' : '$51', # On-Chip Debug Related Register
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_JTD': '$80', # JTAG Interface Disable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+
+# Module EEPROM
+ 'EEAR' : '$41', # EEPROM Address Register Low By
+ 'EEDR' : '$40', # EEPROM Data Register
+ 'EECR' : '$3f', # EEPROM Control Register
+ 'EECR_EEPM': '$30', # EEPROM Programming Mode Bits
+ 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
+ 'EECR_EEMPE': '$4', # EEPROM Master Write Enable
+ 'EECR_EEPE': '$2', # EEPROM Write Enable
+ 'EECR_EERE': '$1', # EEPROM Read Enable
+
+# Module TWI
+ 'TWAMR' : '$bd', # TWI (Slave) Address Mask Regis
+ 'TWAMR_TWAM': '$fe', #
+ 'TWBR' : '$b8', # TWI Bit Rate register
+ 'TWCR' : '$bc', # TWI Control Register
+ 'TWCR_TWINT': '$80', # TWI Interrupt Flag
+ 'TWCR_TWEA': '$40', # TWI Enable Acknowledge Bit
+ 'TWCR_TWSTA': '$20', # TWI Start Condition Bit
+ 'TWCR_TWSTO': '$10', # TWI Stop Condition Bit
+ 'TWCR_TWWC': '$8', # TWI Write Collition Flag
+ 'TWCR_TWEN': '$4', # TWI Enable Bit
+ 'TWCR_TWIE': '$1', # TWI Interrupt Enable
+ 'TWSR' : '$b9', # TWI Status Register
+ 'TWSR_TWS': '$f8', # TWI Status
+ 'TWSR_TWPS': '$3', # TWI Prescaler
+ 'TWDR' : '$bb', # TWI Data register
+ 'TWAR' : '$ba', # TWI (Slave) Address register
+ 'TWAR_TWA': '$fe', # TWI (Slave) Address register B
+ 'TWAR_TWGCE': '$1', # TWI General Call Recognition E
+
+# Module USART1
+ 'UDR1' : '$ce', # USART I/O Data Register
+ 'UCSR1A' : '$c8', # USART Control and Status Regis
+ 'UCSR1A_RXC1': '$80', # USART Receive Complete
+ 'UCSR1A_TXC1': '$40', # USART Transmitt Complete
+ 'UCSR1A_UDRE1': '$20', # USART Data Register Empty
+ 'UCSR1A_FE1': '$10', # Framing Error
+ 'UCSR1A_DOR1': '$8', # Data overRun
+ 'UCSR1A_UPE1': '$4', # Parity Error
+ 'UCSR1A_U2X1': '$2', # Double the USART transmission
+ 'UCSR1A_MPCM1': '$1', # Multi-processor Communication
+ 'UCSR1B' : '$c9', # USART Control and Status Regis
+ 'UCSR1B_RXCIE1': '$80', # RX Complete Interrupt Enable
+ 'UCSR1B_TXCIE1': '$40', # TX Complete Interrupt Enable
+ 'UCSR1B_UDRIE1': '$20', # USART Data register Empty Inte
+ 'UCSR1B_RXEN1': '$10', # Receiver Enable
+ 'UCSR1B_TXEN1': '$8', # Transmitter Enable
+ 'UCSR1B_UCSZ12': '$4', # Character Size
+ 'UCSR1B_RXB81': '$2', # Receive Data Bit 8
+ 'UCSR1B_TXB81': '$1', # Transmit Data Bit 8
+ 'UCSR1C' : '$ca', # USART Control and Status Regis
+ 'UCSR1C_UMSEL1': '$c0', # USART Mode Select
+ 'UCSR1C_UPM1': '$30', # Parity Mode Bits
+ 'UCSR1C_USBS1': '$8', # Stop Bit Select
+ 'UCSR1C_UCSZ1': '$6', # Character Size
+ 'UCSR1C_UCPOL1': '$1', # Clock Polarity
+ 'UBRR1' : '$cc', # USART Baud Rate Register Byte
+
+# Module SPI
+ 'SPDR' : '$4e', # SPI Data Register
+ 'SPSR' : '$4d', # SPI Status Register
+ 'SPSR_SPIF': '$80', # SPI Interrupt Flag
+ 'SPSR_WCOL': '$40', # Write Collision Flag
+ 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
+ 'SPCR' : '$4c', # SPI Control Register
+ 'SPCR_SPIE': '$80', # SPI Interrupt Enable
+ 'SPCR_SPE': '$40', # SPI Enable
+ 'SPCR_DORD': '$20', # Data Order
+ 'SPCR_MSTR': '$10', # Master/Slave Select
+ 'SPCR_CPOL': '$8', # Clock polarity
+ 'SPCR_CPHA': '$4', # Clock Phase
+ 'SPCR_SPR': '$3', # SPI Clock Rate Selects
+
+# Module WATCHDOG
+ 'WDTCSR' : '$60', # Watchdog Timer Control Registe
+ 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
+ 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
+ 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
+ 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
+ 'WDTCSR_WDE': '$8', # Watch Dog Enable
+
+# Module CPU
+ 'SREG' : '$5f', # Status Register
+ 'SREG_I': '$80', # Global Interrupt Enable
+ 'SREG_T': '$40', # Bit Copy Storage
+ 'SREG_H': '$20', # Half Carry Flag
+ 'SREG_S': '$10', # Sign Bit
+ 'SREG_V': '$8', # Two's Complement Overflow Flag
+ 'SREG_N': '$4', # Negative Flag
+ 'SREG_Z': '$2', # Zero Flag
+ 'SREG_C': '$1', # Carry Flag
+ 'SP' : '$5d', # Stack Pointer
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_JTD': '$80', # JTAG Interface Disable
+ 'MCUCR_PUD': '$10', # Pull-up disable
+ 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
+ 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+ 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
+ 'MCUSR_BORF': '$4', # Brown-out Reset Flag
+ 'MCUSR_EXTRF': '$2', # External Reset Flag
+ 'MCUSR_PORF': '$1', # Power-on reset flag
+ 'OSCCAL' : '$66', # Oscillator Calibration Value
+ 'CLKPR' : '$61', #
+ 'CLKPR_CLKPCE': '$80', #
+ 'CLKPR_CLKPS': '$f', #
+ 'SMCR' : '$53', # Sleep Mode Control Register
+ 'SMCR_SM': '$e', # Sleep Mode Select bits
+ 'SMCR_SE': '$1', # Sleep Enable
+ 'RAMPZ' : '$5b', # RAM Page Z Select Register
+ 'GPIOR2' : '$4b', # General Purpose IO Register 2
+ 'GPIOR2_GPIOR': '$ff', # General Purpose IO Register 2
+ 'GPIOR1' : '$4a', # General Purpose IO Register 1
+ 'GPIOR1_GPIOR': '$ff', # General Purpose IO Register 1
+ 'GPIOR0' : '$3e', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR07': '$80', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR06': '$40', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR05': '$20', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR04': '$10', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR03': '$8', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR02': '$4', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR01': '$2', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR00': '$1', # General Purpose IO Register 0
+ 'PRR0' : '$64', # Power Reduction Register0
+ 'PRR0_PRTWI': '$80', # Power Reduction TWI
+ 'PRR0_PRTIM2': '$40', # Power Reduction Timer/Counter2
+ 'PRR0_PRTIM0': '$20', # Power Reduction Timer/Counter0
+ 'PRR0_PRUSART': '$12', # Power Reduction USARTs
+ 'PRR0_PRTIM1': '$8', # Power Reduction Timer/Counter1
+ 'PRR0_PRSPI': '$4', # Power Reduction Serial Periphe
+ 'PRR0_PRADC': '$1', # Power Reduction ADC
+ 'PRR1' : '$65', # Power Reduction Register1
+ 'PRR1_PRTIM3': '$1', # Power Reduction Timer/Counter3
+
+ '__amforth_dummy':'0'
+}
diff --git a/amforth-6.5/avr8/devices/atmega1284/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega1284/words/no-jtag.asm
new file mode 100644
index 0000000..352a4bb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega1284/words/no-jtag.asm
@@ -0,0 +1,14 @@
+; ( -- )
+; ( -- )
+; MCU
+; disable jtag at runtime
+VE_NOJTAG:
+ .dw $FF05
+ .db "-jtag",0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOJTAG
+XT_NOJTAG:
+ .dw PFA_NOJTAG
+PFA_NOJTAG:
+
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega1284/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega1284/words/no-wdt.asm
new file mode 100644
index 0000000..ff6ddd1
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega1284/words/no-wdt.asm
@@ -0,0 +1,34 @@
+; ( -- )
+; MCU
+; disable watch dog timer at runtime
+VE_NOWDT:
+ .dw $ff04
+ .db "-wdt"
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOWDT
+XT_NOWDT:
+ .dw PFA_NOWDT
+PFA_NOWDT:
+
+ in temp1,SREG
+ push temp1
+ ; Turn always off global interrupt.
+ cli
+ ; Reset Watchdog Timer
+ wdr
+ ; Clear WDRF in MCUSR
+ in temp1, MCUSR
+ andi temp1, (0xff & (0<<WDRF))
+ out MCUSR, temp1
+ ; Write logical one to WDCE and WDE
+ ; Keep old prescaler setting to prevent unintentional time-out
+ in_ temp1, WDTCSR
+ ori temp1, (1<<WDCE) | (1<<WDE)
+ out_ WDTCSR, temp1
+ ; Turn off WDT
+ ldi temp1, (0<<WDE)
+ out_ WDTCSR, temp1
+ ; restore status register
+ pop temp1
+ out SREG,temp1
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega1284/words/sleep.asm b/amforth-6.5/avr8/devices/atmega1284/words/sleep.asm
new file mode 100644
index 0000000..256249c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega1284/words/sleep.asm
@@ -0,0 +1,19 @@
+; ( mode -- )
+; MCU
+; put the controller into the specified sleep mode
+VE_SLEEP:
+ .dw $ff05
+ .db "sleep", 0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_SLEEP
+XT_SLEEP:
+ .dw PFA_SLEEP
+PFA_SLEEP:
+ andi tosl, 7 ; leave only legal mode bits
+ lsl tosl ; move to correct location (bits 3-1)
+ ori tosl, 1 ; set the SE bit
+ out_ SMCR, tosl ; set the sleep config
+ sleep ; nighty-night
+ out_ SMCR, zerol ; 0 protects against accidental sleeps
+ loadtos ; pop argument from stack
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega1284p/atmega1284p.frt b/amforth-6.5/avr8/devices/atmega1284p/atmega1284p.frt
new file mode 100644
index 0000000..2419609
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega1284p/atmega1284p.frt
@@ -0,0 +1,380 @@
+\ Partname: ATmega1284P
+\ generated automatically
+
+\ ANALOG_COMPARATOR
+&123 constant ADCSRB \ ADC Control and Status Register B
+ $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer Enable
+&80 constant ACSR \ Analog Comparator Control And Status Register
+ $80 constant ACSR_ACD \ Analog Comparator Disable
+ $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
+ $20 constant ACSR_ACO \ Analog Compare Output
+ $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
+ $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
+ $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
+ $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
+&127 constant DIDR1 \ Digital Input Disable Register 1
+ $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
+ $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
+\ USART0
+&198 constant UDR0 \ USART I/O Data Register
+&192 constant UCSR0A \ USART Control and Status Register A
+ $80 constant UCSR0A_RXC0 \ USART Receive Complete
+ $40 constant UCSR0A_TXC0 \ USART Transmitt Complete
+ $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
+ $10 constant UCSR0A_FE0 \ Framing Error
+ $08 constant UCSR0A_DOR0 \ Data overRun
+ $04 constant UCSR0A_UPE0 \ Parity Error
+ $02 constant UCSR0A_U2X0 \ Double the USART transmission speed
+ $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
+&193 constant UCSR0B \ USART Control and Status Register B
+ $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
+ $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
+ $20 constant UCSR0B_UDRIE0 \ USART Data register Empty Interrupt Enable
+ $10 constant UCSR0B_RXEN0 \ Receiver Enable
+ $08 constant UCSR0B_TXEN0 \ Transmitter Enable
+ $04 constant UCSR0B_UCSZ02 \ Character Size
+ $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
+ $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
+&194 constant UCSR0C \ USART Control and Status Register C
+ $C0 constant UCSR0C_UMSEL0 \ USART Mode Select
+ $30 constant UCSR0C_UPM0 \ Parity Mode Bits
+ $08 constant UCSR0C_USBS0 \ Stop Bit Select
+ $06 constant UCSR0C_UCSZ0 \ Character Size
+ $01 constant UCSR0C_UCPOL0 \ Clock Polarity
+&196 constant UBRR0 \ USART Baud Rate Register Bytes
+\ PORTA
+&34 constant PORTA \ Port A Data Register
+&33 constant DDRA \ Port A Data Direction Register
+&32 constant PINA \ Port A Input Pins
+\ PORTB
+&37 constant PORTB \ Port B Data Register
+&36 constant DDRB \ Port B Data Direction Register
+&35 constant PINB \ Port B Input Pins
+\ PORTC
+&40 constant PORTC \ Port C Data Register
+&39 constant DDRC \ Port C Data Direction Register
+&38 constant PINC \ Port C Input Pins
+\ PORTD
+&43 constant PORTD \ Port D Data Register
+&42 constant DDRD \ Port D Data Direction Register
+&41 constant PIND \ Port D Input Pins
+\ TIMER_COUNTER_0
+&72 constant OCR0B \ Timer/Counter0 Output Compare Register
+&71 constant OCR0A \ Timer/Counter0 Output Compare Register
+&70 constant TCNT0 \ Timer/Counter0
+&69 constant TCCR0B \ Timer/Counter Control Register B
+ $80 constant TCCR0B_FOC0A \ Force Output Compare A
+ $40 constant TCCR0B_FOC0B \ Force Output Compare B
+ $08 constant TCCR0B_WGM02 \
+ $07 constant TCCR0B_CS0 \ Clock Select
+&68 constant TCCR0A \ Timer/Counter Control Register A
+ $C0 constant TCCR0A_COM0A \ Compare Output Mode, Phase Correct PWM Mode
+ $30 constant TCCR0A_COM0B \ Compare Output Mode, Fast PWm
+ $03 constant TCCR0A_WGM0 \ Waveform Generation Mode
+&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
+ $04 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare Match B Interrupt Enable
+ $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match A Interrupt Enable
+ $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
+&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
+ $04 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare Flag 0B
+ $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0A
+ $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
+&67 constant GTCCR \ General Timer/Counter Control Register
+ $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
+ $01 constant GTCCR_PSRSYNC \ Prescaler Reset Timer/Counter1 and Timer/Counter0
+\ TIMER_COUNTER_1
+&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
+ $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
+ $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
+ $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
+ $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
+&54 constant TIFR1 \ Timer/Counter Interrupt Flag register
+ $20 constant TIFR1_ICF1 \ Timer/Counter1 Input Capture Flag
+ $04 constant TIFR1_OCF1B \ Timer/Counter1 Output Compare B Match Flag
+ $02 constant TIFR1_OCF1A \ Timer/Counter1 Output Compare A Match Flag
+ $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
+&128 constant TCCR1A \ Timer/Counter1 Control Register A
+ $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
+ $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
+ $03 constant TCCR1A_WGM1 \ Pulse Width Modulator Select Bits
+&129 constant TCCR1B \ Timer/Counter1 Control Register B
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ $18 constant TCCR1B_WGM1 \ Waveform Generation Mode Bits
+ $07 constant TCCR1B_CS1 \ Clock Select1 bits
+&130 constant TCCR1C \ Timer/Counter1 Control Register C
+ $80 constant TCCR1C_FOC1A \ Force Output Compare for Channel A
+ $40 constant TCCR1C_FOC1B \ Force Output Compare for Channel B
+&132 constant TCNT1 \ Timer/Counter1 Bytes
+&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
+&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
+&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
+\ TIMER_COUNTER_2
+&112 constant TIMSK2 \ Timer/Counter Interrupt Mask register
+ $04 constant TIMSK2_OCIE2B \ Timer/Counter2 Output Compare Match B Interrupt Enable
+ $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match A Interrupt Enable
+ $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
+&55 constant TIFR2 \ Timer/Counter Interrupt Flag Register
+ $04 constant TIFR2_OCF2B \ Output Compare Flag 2B
+ $02 constant TIFR2_OCF2A \ Output Compare Flag 2A
+ $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
+&176 constant TCCR2A \ Timer/Counter2 Control Register A
+ $C0 constant TCCR2A_COM2A \ Compare Output Mode bits
+ $30 constant TCCR2A_COM2B \ Compare Output Mode bits
+ $03 constant TCCR2A_WGM2 \ Waveform Genration Mode
+&177 constant TCCR2B \ Timer/Counter2 Control Register B
+ $80 constant TCCR2B_FOC2A \ Force Output Compare A
+ $40 constant TCCR2B_FOC2B \ Force Output Compare B
+ $08 constant TCCR2B_WGM22 \ Waveform Generation Mode
+ $07 constant TCCR2B_CS2 \ Clock Select bits
+&178 constant TCNT2 \ Timer/Counter2
+&180 constant OCR2B \ Timer/Counter2 Output Compare Register B
+&179 constant OCR2A \ Timer/Counter2 Output Compare Register A
+&182 constant ASSR \ Asynchronous Status Register
+ $40 constant ASSR_EXCLK \ Enable External Clock Input
+ $20 constant ASSR_AS2 \ Asynchronous Timer/Counter2
+ $10 constant ASSR_TCN2UB \ Timer/Counter2 Update Busy
+ $08 constant ASSR_OCR2AUB \ Output Compare Register2 Update Busy
+ $04 constant ASSR_OCR2BUB \ Output Compare Register 2 Update Busy
+ $02 constant ASSR_TCR2AUB \ Timer/Counter Control Register2 Update Busy
+ $01 constant ASSR_TCR2BUB \ Timer/Counter Control Register2 Update Busy
+\ TIMER_COUNTER_3
+&113 constant TIMSK3 \ Timer/Counter3 Interrupt Mask Register
+ $20 constant TIMSK3_ICIE3 \ Timer/Counter3 Input Capture Interrupt Enable
+ $04 constant TIMSK3_OCIE3B \ Timer/Counter3 Output Compare B Match Interrupt Enable
+ $02 constant TIMSK3_OCIE3A \ Timer/Counter3 Output Compare A Match Interrupt Enable
+ $01 constant TIMSK3_TOIE3 \ Timer/Counter3 Overflow Interrupt Enable
+&56 constant TIFR3 \ Timer/Counter Interrupt Flag register
+ $20 constant TIFR3_ICF3 \ Timer/Counter3 Input Capture Flag
+ $04 constant TIFR3_OCF3B \ Timer/Counter3 Output Compare B Match Flag
+ $02 constant TIFR3_OCF3A \ Timer/Counter3 Output Compare A Match Flag
+ $01 constant TIFR3_TOV3 \ Timer/Counter3 Overflow Flag
+&144 constant TCCR3A \ Timer/Counter3 Control Register A
+ $C0 constant TCCR3A_COM3A \ Compare Output Mode 3A, bits
+ $30 constant TCCR3A_COM3B \ Compare Output Mode 3B, bits
+ $03 constant TCCR3A_WGM3 \ Pulse Width Modulator Select Bits
+&145 constant TCCR3B \ Timer/Counter3 Control Register B
+ $80 constant TCCR3B_ICNC3 \ Input Capture 3 Noise Canceler
+ $40 constant TCCR3B_ICES3 \ Input Capture 3 Edge Select
+ $18 constant TCCR3B_WGM3 \ Waveform Generation Mode Bits
+ $07 constant TCCR3B_CS3 \ Clock Select3 bits
+&146 constant TCCR3C \ Timer/Counter3 Control Register C
+ $80 constant TCCR3C_FOC3A \ Force Output Compare for Channel A
+ $40 constant TCCR3C_FOC3B \ Force Output Compare for Channel B
+&148 constant TCNT3 \ Timer/Counter3 Bytes
+&152 constant OCR3A \ Timer/Counter3 Output Compare Register A Bytes
+&154 constant OCR3B \ Timer/Counter3 Output Compare Register B Bytes
+&150 constant ICR3 \ Timer/Counter3 Input Capture Register Bytes
+\ BOOT_LOAD
+&87 constant SPMCSR \ Store Program Memory Control Register
+ $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
+ $20 constant SPMCSR_SIGRD \ Signature Row Read
+ $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
+ $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
+ $04 constant SPMCSR_PGWRT \ Page Write
+ $02 constant SPMCSR_PGERS \ Page Erase
+ $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
+\ EXTERNAL_INTERRUPT
+&105 constant EICRA \ External Interrupt Control Register A
+ $30 constant EICRA_ISC2 \ External Interrupt Sense Control Bit
+ $0C constant EICRA_ISC1 \ External Interrupt Sense Control Bit
+ $03 constant EICRA_ISC0 \ External Interrupt Sense Control Bit
+&61 constant EIMSK \ External Interrupt Mask Register
+ $07 constant EIMSK_INT \ External Interrupt Request 2 Enable
+&60 constant EIFR \ External Interrupt Flag Register
+ $07 constant EIFR_INTF \ External Interrupt Flags
+&115 constant PCMSK3 \ Pin Change Mask Register 3
+ $FF constant PCMSK3_PCINT \ Pin Change Enable Masks
+&109 constant PCMSK2 \ Pin Change Mask Register 2
+ $FF constant PCMSK2_PCINT \ Pin Change Enable Masks
+&108 constant PCMSK1 \ Pin Change Mask Register 1
+ $FF constant PCMSK1_PCINT \ Pin Change Enable Masks
+&107 constant PCMSK0 \ Pin Change Mask Register 0
+ $FF constant PCMSK0_PCINT \ Pin Change Enable Masks
+&59 constant PCIFR \ Pin Change Interrupt Flag Register
+ $0F constant PCIFR_PCIF \ Pin Change Interrupt Flags
+&104 constant PCICR \ Pin Change Interrupt Control Register
+ $0F constant PCICR_PCIE \ Pin Change Interrupt Enables
+\ AD_CONVERTER
+&124 constant ADMUX \ The ADC multiplexer Selection Register
+ $C0 constant ADMUX_REFS \ Reference Selection Bits
+ $20 constant ADMUX_ADLAR \ Left Adjust Result
+ $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
+&120 constant ADC \ ADC Data Register Bytes
+&122 constant ADCSRA \ The ADC Control and Status register A
+ $80 constant ADCSRA_ADEN \ ADC Enable
+ $40 constant ADCSRA_ADSC \ ADC Start Conversion
+ $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
+ $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
+ $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
+ $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
+&126 constant DIDR0 \ Digital Input Disable Register
+ $80 constant DIDR0_ADC7D \
+ $40 constant DIDR0_ADC6D \
+ $20 constant DIDR0_ADC5D \
+ $10 constant DIDR0_ADC4D \
+ $08 constant DIDR0_ADC3D \
+ $04 constant DIDR0_ADC2D \
+ $02 constant DIDR0_ADC1D \
+ $01 constant DIDR0_ADC0D \
+\ JTAG
+&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
+&85 constant MCUCR \ MCU Control Register
+ $80 constant MCUCR_JTD \ JTAG Interface Disable
+&84 constant MCUSR \ MCU Status Register
+ $10 constant MCUSR_JTRF \ JTAG Reset Flag
+\ EEPROM
+&65 constant EEAR \ EEPROM Address Register Low Bytes
+&64 constant EEDR \ EEPROM Data Register
+&63 constant EECR \ EEPROM Control Register
+ $30 constant EECR_EEPM \ EEPROM Programming Mode Bits
+ $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
+ $04 constant EECR_EEMPE \ EEPROM Master Write Enable
+ $02 constant EECR_EEPE \ EEPROM Write Enable
+ $01 constant EECR_EERE \ EEPROM Read Enable
+\ TWI
+&189 constant TWAMR \ TWI (Slave) Address Mask Register
+ $FE constant TWAMR_TWAM \
+&184 constant TWBR \ TWI Bit Rate register
+&188 constant TWCR \ TWI Control Register
+ $80 constant TWCR_TWINT \ TWI Interrupt Flag
+ $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
+ $20 constant TWCR_TWSTA \ TWI Start Condition Bit
+ $10 constant TWCR_TWSTO \ TWI Stop Condition Bit
+ $08 constant TWCR_TWWC \ TWI Write Collition Flag
+ $04 constant TWCR_TWEN \ TWI Enable Bit
+ $01 constant TWCR_TWIE \ TWI Interrupt Enable
+&185 constant TWSR \ TWI Status Register
+ $F8 constant TWSR_TWS \ TWI Status
+ $03 constant TWSR_TWPS \ TWI Prescaler
+&187 constant TWDR \ TWI Data register
+&186 constant TWAR \ TWI (Slave) Address register
+ $FE constant TWAR_TWA \ TWI (Slave) Address register Bits
+ $01 constant TWAR_TWGCE \ TWI General Call Recognition Enable Bit
+\ USART1
+&206 constant UDR1 \ USART I/O Data Register
+&200 constant UCSR1A \ USART Control and Status Register A
+ $80 constant UCSR1A_RXC1 \ USART Receive Complete
+ $40 constant UCSR1A_TXC1 \ USART Transmitt Complete
+ $20 constant UCSR1A_UDRE1 \ USART Data Register Empty
+ $10 constant UCSR1A_FE1 \ Framing Error
+ $08 constant UCSR1A_DOR1 \ Data overRun
+ $04 constant UCSR1A_UPE1 \ Parity Error
+ $02 constant UCSR1A_U2X1 \ Double the USART transmission speed
+ $01 constant UCSR1A_MPCM1 \ Multi-processor Communication Mode
+&201 constant UCSR1B \ USART Control and Status Register B
+ $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable
+ $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable
+ $20 constant UCSR1B_UDRIE1 \ USART Data register Empty Interrupt Enable
+ $10 constant UCSR1B_RXEN1 \ Receiver Enable
+ $08 constant UCSR1B_TXEN1 \ Transmitter Enable
+ $04 constant UCSR1B_UCSZ12 \ Character Size
+ $02 constant UCSR1B_RXB81 \ Receive Data Bit 8
+ $01 constant UCSR1B_TXB81 \ Transmit Data Bit 8
+&202 constant UCSR1C \ USART Control and Status Register C
+ $C0 constant UCSR1C_UMSEL1 \ USART Mode Select
+ $30 constant UCSR1C_UPM1 \ Parity Mode Bits
+ $08 constant UCSR1C_USBS1 \ Stop Bit Select
+ $06 constant UCSR1C_UCSZ1 \ Character Size
+ $01 constant UCSR1C_UCPOL1 \ Clock Polarity
+&204 constant UBRR1 \ USART Baud Rate Register Bytes
+\ SPI
+&78 constant SPDR \ SPI Data Register
+&77 constant SPSR \ SPI Status Register
+ $80 constant SPSR_SPIF \ SPI Interrupt Flag
+ $40 constant SPSR_WCOL \ Write Collision Flag
+ $01 constant SPSR_SPI2X \ Double SPI Speed Bit
+&76 constant SPCR \ SPI Control Register
+ $80 constant SPCR_SPIE \ SPI Interrupt Enable
+ $40 constant SPCR_SPE \ SPI Enable
+ $20 constant SPCR_DORD \ Data Order
+ $10 constant SPCR_MSTR \ Master/Slave Select
+ $08 constant SPCR_CPOL \ Clock polarity
+ $04 constant SPCR_CPHA \ Clock Phase
+ $03 constant SPCR_SPR \ SPI Clock Rate Selects
+\ WATCHDOG
+&96 constant WDTCSR \ Watchdog Timer Control Register
+ $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Flag
+ $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Enable
+ $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
+ $10 constant WDTCSR_WDCE \ Watchdog Change Enable
+ $08 constant WDTCSR_WDE \ Watch Dog Enable
+\ CPU
+&95 constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ $08 constant SREG_V \ Two's Complement Overflow Flag
+ $04 constant SREG_N \ Negative Flag
+ $02 constant SREG_Z \ Zero Flag
+ $01 constant SREG_C \ Carry Flag
+&93 constant SP \ Stack Pointer
+&102 constant OSCCAL \ Oscillator Calibration Value
+&97 constant CLKPR \
+ $80 constant CLKPR_CLKPCE \
+ $0F constant CLKPR_CLKPS \
+&83 constant SMCR \ Sleep Mode Control Register
+ $0E constant SMCR_SM \ Sleep Mode Select bits
+ $01 constant SMCR_SE \ Sleep Enable
+&91 constant RAMPZ \ RAM Page Z Select Register
+&75 constant GPIOR2 \ General Purpose IO Register 2
+ $FF constant GPIOR2_GPIOR \ General Purpose IO Register 2 bis
+&74 constant GPIOR1 \ General Purpose IO Register 1
+ $FF constant GPIOR1_GPIOR \ General Purpose IO Register 1 bis
+&62 constant GPIOR0 \ General Purpose IO Register 0
+ $80 constant GPIOR0_GPIOR07 \ General Purpose IO Register 0 bit 7
+ $40 constant GPIOR0_GPIOR06 \ General Purpose IO Register 0 bit 6
+ $20 constant GPIOR0_GPIOR05 \ General Purpose IO Register 0 bit 5
+ $10 constant GPIOR0_GPIOR04 \ General Purpose IO Register 0 bit 4
+ $08 constant GPIOR0_GPIOR03 \ General Purpose IO Register 0 bit 3
+ $04 constant GPIOR0_GPIOR02 \ General Purpose IO Register 0 bit 2
+ $02 constant GPIOR0_GPIOR01 \ General Purpose IO Register 0 bit 1
+ $01 constant GPIOR0_GPIOR00 \ General Purpose IO Register 0 bit 0
+&100 constant PRR0 \ Power Reduction Register0
+ $80 constant PRR0_PRTWI \ Power Reduction TWI
+ $40 constant PRR0_PRTIM2 \ Power Reduction Timer/Counter2
+ $20 constant PRR0_PRTIM0 \ Power Reduction Timer/Counter0
+ $12 constant PRR0_PRUSART \ Power Reduction USARTs
+ $08 constant PRR0_PRTIM1 \ Power Reduction Timer/Counter1
+ $04 constant PRR0_PRSPI \ Power Reduction Serial Peripheral Interface
+ $01 constant PRR0_PRADC \ Power Reduction ADC
+&101 constant PRR1 \ Power Reduction Register1
+ $01 constant PRR1_PRTIM3 \ Power Reduction Timer/Counter3
+
+\ Interrupts
+&2 constant INT0Addr \ External Interrupt Request 0
+&4 constant INT1Addr \ External Interrupt Request 1
+&6 constant INT2Addr \ External Interrupt Request 2
+&8 constant PCINT0Addr \ Pin Change Interrupt Request 0
+&10 constant PCINT1Addr \ Pin Change Interrupt Request 1
+&12 constant PCINT2Addr \ Pin Change Interrupt Request 2
+&14 constant PCINT3Addr \ Pin Change Interrupt Request 3
+&16 constant WDTAddr \ Watchdog Time-out Interrupt
+&18 constant TIMER2_COMPAAddr \ Timer/Counter2 Compare Match A
+&20 constant TIMER2_COMPBAddr \ Timer/Counter2 Compare Match B
+&22 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
+&24 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+&26 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
+&28 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
+&30 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+&32 constant TIMER0_COMPAAddr \ Timer/Counter0 Compare Match A
+&34 constant TIMER0_COMPBAddr \ Timer/Counter0 Compare Match B
+&36 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
+&38 constant SPI__STCAddr \ SPI Serial Transfer Complete
+&40 constant USART0__RXAddr \ USART0, Rx Complete
+&42 constant USART0__UDREAddr \ USART0 Data register Empty
+&44 constant USART0__TXAddr \ USART0, Tx Complete
+&46 constant ANALOG_COMPAddr \ Analog Comparator
+&48 constant ADCAddr \ ADC Conversion Complete
+&50 constant EE_READYAddr \ EEPROM Ready
+&52 constant TWIAddr \ 2-wire Serial Interface
+&54 constant SPM_READYAddr \ Store Program Memory Read
+&56 constant USART1_RXAddr \ USART1 RX complete
+&58 constant USART1_UDREAddr \ USART1 Data Register Empty
+&60 constant USART1_TXAddr \ USART1 TX complete
+&62 constant TIMER3_CAPTAddr \ Timer/Counter3 Capture Event
+&64 constant TIMER3_COMPAAddr \ Timer/Counter3 Compare Match A
+&66 constant TIMER3_COMPBAddr \ Timer/Counter3 Compare Match B
+&68 constant TIMER3_OVFAddr \ Timer/Counter3 Overflow
diff --git a/amforth-6.5/avr8/devices/atmega1284p/device.asm b/amforth-6.5/avr8/devices/atmega1284p/device.asm
new file mode 100644
index 0000000..e8d1391
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega1284p/device.asm
@@ -0,0 +1,135 @@
+; Partname: ATmega1284P
+; generated automatically, do not edit
+
+.nolist
+ .include "m1284Pdef.inc"
+.list
+
+.equ ramstart = 256
+.equ CELLSIZE = 2
+.macro readflashcell
+ clr temp7
+ lsl zl
+ rol zh
+ rol temp7
+ out_ RAMPZ, temp7
+ elpm @0, Z+
+ elpm @1, Z+
+.endmacro
+.macro writeflashcell
+ clr temp7
+ lsl zl
+ rol zh
+ rol temp7
+ out_ RAMPZ, temp7
+.endmacro
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_USART0 = 0
+.set WANT_PORTA = 0
+.set WANT_PORTB = 0
+.set WANT_PORTC = 0
+.set WANT_PORTD = 0
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_TIMER_COUNTER_2 = 0
+.set WANT_TIMER_COUNTER_3 = 0
+.set WANT_BOOT_LOAD = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_AD_CONVERTER = 0
+.set WANT_JTAG = 0
+.set WANT_EEPROM = 0
+.set WANT_TWI = 0
+.set WANT_USART1 = 0
+.set WANT_SPI = 0
+.set WANT_WATCHDOG = 0
+.set WANT_CPU = 0
+.equ intvecsize = 2 ; please verify; flash size: 131072 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.org 2
+ rcall isr ; External Interrupt Request 0
+.org 4
+ rcall isr ; External Interrupt Request 1
+.org 6
+ rcall isr ; External Interrupt Request 2
+.org 8
+ rcall isr ; Pin Change Interrupt Request 0
+.org 10
+ rcall isr ; Pin Change Interrupt Request 1
+.org 12
+ rcall isr ; Pin Change Interrupt Request 2
+.org 14
+ rcall isr ; Pin Change Interrupt Request 3
+.org 16
+ rcall isr ; Watchdog Time-out Interrupt
+.org 18
+ rcall isr ; Timer/Counter2 Compare Match A
+.org 20
+ rcall isr ; Timer/Counter2 Compare Match B
+.org 22
+ rcall isr ; Timer/Counter2 Overflow
+.org 24
+ rcall isr ; Timer/Counter1 Capture Event
+.org 26
+ rcall isr ; Timer/Counter1 Compare Match A
+.org 28
+ rcall isr ; Timer/Counter1 Compare Match B
+.org 30
+ rcall isr ; Timer/Counter1 Overflow
+.org 32
+ rcall isr ; Timer/Counter0 Compare Match A
+.org 34
+ rcall isr ; Timer/Counter0 Compare Match B
+.org 36
+ rcall isr ; Timer/Counter0 Overflow
+.org 38
+ rcall isr ; SPI Serial Transfer Complete
+.org 40
+ rcall isr ; USART0, Rx Complete
+.org 42
+ rcall isr ; USART0 Data register Empty
+.org 44
+ rcall isr ; USART0, Tx Complete
+.org 46
+ rcall isr ; Analog Comparator
+.org 48
+ rcall isr ; ADC Conversion Complete
+.org 50
+ rcall isr ; EEPROM Ready
+.org 52
+ rcall isr ; 2-wire Serial Interface
+.org 54
+ rcall isr ; Store Program Memory Read
+.org 56
+ rcall isr ; USART1 RX complete
+.org 58
+ rcall isr ; USART1 Data Register Empty
+.org 60
+ rcall isr ; USART1 TX complete
+.org 62
+ rcall isr ; Timer/Counter3 Capture Event
+.org 64
+ rcall isr ; Timer/Counter3 Compare Match A
+.org 66
+ rcall isr ; Timer/Counter3 Compare Match B
+.org 68
+ rcall isr ; Timer/Counter3 Overflow
+.equ INTVECTORS = 35
+.nooverlap
+
+; compatability layer (maybe empty)
+
+; controller data area, environment query mcu-info
+mcu_info:
+mcu_ramsize:
+ .dw 16384
+mcu_eepromsize:
+ .dw 4096
+mcu_maxdp:
+ .dw 65535
+mcu_numints:
+ .dw 35
+mcu_name:
+ .dw 11
+ .db "ATmega1284P",0
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega1284p/device.inc b/amforth-6.5/avr8/devices/atmega1284p/device.inc
new file mode 100644
index 0000000..718a658
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega1284p/device.inc
@@ -0,0 +1,1263 @@
+; Partname: ATmega1284P
+; generated automatically, no not edit
+
+.if WANT_ANALOG_COMPARATOR == 1
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Control and Status Register B
+VE_ADCSRB:
+ .dw $ff06
+ .db "ADCSRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRB
+XT_ADCSRB:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRB:
+ .dw 123
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Control And Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw 80
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 1
+VE_DIDR1:
+ .dw $ff05
+ .db "DIDR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR1
+XT_DIDR1:
+ .dw PFA_DOVARIABLE
+PFA_DIDR1:
+ .dw 127
+
+.endif
+.if WANT_USART0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR0:
+ .dw $ff04
+ .db "UDR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR0
+XT_UDR0:
+ .dw PFA_DOVARIABLE
+PFA_UDR0:
+ .dw 198
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR0A:
+ .dw $ff06
+ .db "UCSR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0A
+XT_UCSR0A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0A:
+ .dw 192
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR0B:
+ .dw $ff06
+ .db "UCSR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0B
+XT_UCSR0B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0B:
+ .dw 193
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR0C:
+ .dw $ff06
+ .db "UCSR0C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0C
+XT_UCSR0C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0C:
+ .dw 194
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Bytes
+VE_UBRR0:
+ .dw $ff05
+ .db "UBRR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR0
+XT_UBRR0:
+ .dw PFA_DOVARIABLE
+PFA_UBRR0:
+ .dw 196
+
+.endif
+.if WANT_PORTA == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Register
+VE_PORTA:
+ .dw $ff05
+ .db "PORTA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTA
+XT_PORTA:
+ .dw PFA_DOVARIABLE
+PFA_PORTA:
+ .dw 34
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Direction Register
+VE_DDRA:
+ .dw $ff04
+ .db "DDRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRA
+XT_DDRA:
+ .dw PFA_DOVARIABLE
+PFA_DDRA:
+ .dw 33
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Input Pins
+VE_PINA:
+ .dw $ff04
+ .db "PINA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINA
+XT_PINA:
+ .dw PFA_DOVARIABLE
+PFA_PINA:
+ .dw 32
+
+.endif
+.if WANT_PORTB == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw 37
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw 36
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw 35
+
+.endif
+.if WANT_PORTC == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Register
+VE_PORTC:
+ .dw $ff05
+ .db "PORTC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTC
+XT_PORTC:
+ .dw PFA_DOVARIABLE
+PFA_PORTC:
+ .dw 40
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Direction Register
+VE_DDRC:
+ .dw $ff04
+ .db "DDRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRC
+XT_DDRC:
+ .dw PFA_DOVARIABLE
+PFA_DDRC:
+ .dw 39
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Input Pins
+VE_PINC:
+ .dw $ff04
+ .db "PINC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINC
+XT_PINC:
+ .dw PFA_DOVARIABLE
+PFA_PINC:
+ .dw 38
+
+.endif
+.if WANT_PORTD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw 43
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw 42
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw 41
+
+.endif
+.if WANT_TIMER_COUNTER_0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0B:
+ .dw $ff05
+ .db "OCR0B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0B
+XT_OCR0B:
+ .dw PFA_DOVARIABLE
+PFA_OCR0B:
+ .dw 72
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0A:
+ .dw $ff05
+ .db "OCR0A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0A
+XT_OCR0A:
+ .dw PFA_DOVARIABLE
+PFA_OCR0A:
+ .dw 71
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw 70
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register B
+VE_TCCR0B:
+ .dw $ff06
+ .db "TCCR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0B
+XT_TCCR0B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0B:
+ .dw 69
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register A
+VE_TCCR0A:
+ .dw $ff06
+ .db "TCCR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0A
+XT_TCCR0A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0A:
+ .dw 68
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Mask Register
+VE_TIMSK0:
+ .dw $ff06
+ .db "TIMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK0
+XT_TIMSK0:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK0:
+ .dw 110
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Flag register
+VE_TIFR0:
+ .dw $ff05
+ .db "TIFR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR0
+XT_TIFR0:
+ .dw PFA_DOVARIABLE
+PFA_TIFR0:
+ .dw 53
+; ( -- addr ) System Constant
+; R( -- )
+; General Timer/Counter Control Register
+VE_GTCCR:
+ .dw $ff05
+ .db "GTCCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GTCCR
+XT_GTCCR:
+ .dw PFA_DOVARIABLE
+PFA_GTCCR:
+ .dw 67
+
+.endif
+.if WANT_TIMER_COUNTER_1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Mask Register
+VE_TIMSK1:
+ .dw $ff06
+ .db "TIMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK1
+XT_TIMSK1:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK1:
+ .dw 111
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Flag register
+VE_TIFR1:
+ .dw $ff05
+ .db "TIFR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR1
+XT_TIFR1:
+ .dw PFA_DOVARIABLE
+PFA_TIFR1:
+ .dw 54
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw 128
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw 129
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register C
+VE_TCCR1C:
+ .dw $ff06
+ .db "TCCR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1C
+XT_TCCR1C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1C:
+ .dw 130
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Bytes
+VE_TCNT1:
+ .dw $ff05
+ .db "TCNT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1
+XT_TCNT1:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1:
+ .dw 132
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register A Bytes
+VE_OCR1A:
+ .dw $ff05
+ .db "OCR1A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1A
+XT_OCR1A:
+ .dw PFA_DOVARIABLE
+PFA_OCR1A:
+ .dw 136
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register B Bytes
+VE_OCR1B:
+ .dw $ff05
+ .db "OCR1B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1B
+XT_OCR1B:
+ .dw PFA_DOVARIABLE
+PFA_OCR1B:
+ .dw 138
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Bytes
+VE_ICR1:
+ .dw $ff04
+ .db "ICR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1
+XT_ICR1:
+ .dw PFA_DOVARIABLE
+PFA_ICR1:
+ .dw 134
+
+.endif
+.if WANT_TIMER_COUNTER_2 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Mask register
+VE_TIMSK2:
+ .dw $ff06
+ .db "TIMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK2
+XT_TIMSK2:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK2:
+ .dw 112
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Flag Register
+VE_TIFR2:
+ .dw $ff05
+ .db "TIFR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR2
+XT_TIFR2:
+ .dw PFA_DOVARIABLE
+PFA_TIFR2:
+ .dw 55
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register A
+VE_TCCR2A:
+ .dw $ff06
+ .db "TCCR2A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2A
+XT_TCCR2A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2A:
+ .dw 176
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register B
+VE_TCCR2B:
+ .dw $ff06
+ .db "TCCR2B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2B
+XT_TCCR2B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2B:
+ .dw 177
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2
+VE_TCNT2:
+ .dw $ff05
+ .db "TCNT2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT2
+XT_TCNT2:
+ .dw PFA_DOVARIABLE
+PFA_TCNT2:
+ .dw 178
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register B
+VE_OCR2B:
+ .dw $ff05
+ .db "OCR2B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2B
+XT_OCR2B:
+ .dw PFA_DOVARIABLE
+PFA_OCR2B:
+ .dw 180
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register A
+VE_OCR2A:
+ .dw $ff05
+ .db "OCR2A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2A
+XT_OCR2A:
+ .dw PFA_DOVARIABLE
+PFA_OCR2A:
+ .dw 179
+; ( -- addr ) System Constant
+; R( -- )
+; Asynchronous Status Register
+VE_ASSR:
+ .dw $ff04
+ .db "ASSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ASSR
+XT_ASSR:
+ .dw PFA_DOVARIABLE
+PFA_ASSR:
+ .dw 182
+
+.endif
+.if WANT_TIMER_COUNTER_3 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Interrupt Mask Register
+VE_TIMSK3:
+ .dw $ff06
+ .db "TIMSK3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK3
+XT_TIMSK3:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK3:
+ .dw 113
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Flag register
+VE_TIFR3:
+ .dw $ff05
+ .db "TIFR3",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR3
+XT_TIFR3:
+ .dw PFA_DOVARIABLE
+PFA_TIFR3:
+ .dw 56
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Control Register A
+VE_TCCR3A:
+ .dw $ff06
+ .db "TCCR3A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR3A
+XT_TCCR3A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR3A:
+ .dw 144
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Control Register B
+VE_TCCR3B:
+ .dw $ff06
+ .db "TCCR3B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR3B
+XT_TCCR3B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR3B:
+ .dw 145
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Control Register C
+VE_TCCR3C:
+ .dw $ff06
+ .db "TCCR3C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR3C
+XT_TCCR3C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR3C:
+ .dw 146
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Bytes
+VE_TCNT3:
+ .dw $ff05
+ .db "TCNT3",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT3
+XT_TCNT3:
+ .dw PFA_DOVARIABLE
+PFA_TCNT3:
+ .dw 148
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Output Compare Register A Bytes
+VE_OCR3A:
+ .dw $ff05
+ .db "OCR3A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR3A
+XT_OCR3A:
+ .dw PFA_DOVARIABLE
+PFA_OCR3A:
+ .dw 152
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Output Compare Register B Bytes
+VE_OCR3B:
+ .dw $ff05
+ .db "OCR3B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR3B
+XT_OCR3B:
+ .dw PFA_DOVARIABLE
+PFA_OCR3B:
+ .dw 154
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Input Capture Register Bytes
+VE_ICR3:
+ .dw $ff04
+ .db "ICR3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR3
+XT_ICR3:
+ .dw PFA_DOVARIABLE
+PFA_ICR3:
+ .dw 150
+
+.endif
+.if WANT_BOOT_LOAD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control Register
+VE_SPMCSR:
+ .dw $ff06
+ .db "SPMCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCSR
+XT_SPMCSR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCSR:
+ .dw 87
+
+.endif
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register A
+VE_EICRA:
+ .dw $ff05
+ .db "EICRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRA
+XT_EICRA:
+ .dw PFA_DOVARIABLE
+PFA_EICRA:
+ .dw 105
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Mask Register
+VE_EIMSK:
+ .dw $ff05
+ .db "EIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIMSK
+XT_EIMSK:
+ .dw PFA_DOVARIABLE
+PFA_EIMSK:
+ .dw 61
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Flag Register
+VE_EIFR:
+ .dw $ff04
+ .db "EIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIFR
+XT_EIFR:
+ .dw PFA_DOVARIABLE
+PFA_EIFR:
+ .dw 60
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 3
+VE_PCMSK3:
+ .dw $ff06
+ .db "PCMSK3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK3
+XT_PCMSK3:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK3:
+ .dw 115
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 2
+VE_PCMSK2:
+ .dw $ff06
+ .db "PCMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK2
+XT_PCMSK2:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK2:
+ .dw 109
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 1
+VE_PCMSK1:
+ .dw $ff06
+ .db "PCMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK1
+XT_PCMSK1:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK1:
+ .dw 108
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 0
+VE_PCMSK0:
+ .dw $ff06
+ .db "PCMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK0
+XT_PCMSK0:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK0:
+ .dw 107
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Interrupt Flag Register
+VE_PCIFR:
+ .dw $ff05
+ .db "PCIFR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCIFR
+XT_PCIFR:
+ .dw PFA_DOVARIABLE
+PFA_PCIFR:
+ .dw 59
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Interrupt Control Register
+VE_PCICR:
+ .dw $ff05
+ .db "PCICR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCICR
+XT_PCICR:
+ .dw PFA_DOVARIABLE
+PFA_PCICR:
+ .dw 104
+
+.endif
+.if WANT_AD_CONVERTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC multiplexer Selection Register
+VE_ADMUX:
+ .dw $ff05
+ .db "ADMUX",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADMUX
+XT_ADMUX:
+ .dw PFA_DOVARIABLE
+PFA_ADMUX:
+ .dw 124
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register Bytes
+VE_ADC:
+ .dw $ff03
+ .db "ADC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADC
+XT_ADC:
+ .dw PFA_DOVARIABLE
+PFA_ADC:
+ .dw 120
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register A
+VE_ADCSRA:
+ .dw $ff06
+ .db "ADCSRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRA
+XT_ADCSRA:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRA:
+ .dw 122
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register
+VE_DIDR0:
+ .dw $ff05
+ .db "DIDR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR0
+XT_DIDR0:
+ .dw PFA_DOVARIABLE
+PFA_DIDR0:
+ .dw 126
+
+.endif
+.if WANT_JTAG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; On-Chip Debug Related Register in I/O Memory
+VE_OCDR:
+ .dw $ff04
+ .db "OCDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCDR
+XT_OCDR:
+ .dw PFA_DOVARIABLE
+PFA_OCDR:
+ .dw 81
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw 85
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Status Register
+VE_MCUSR:
+ .dw $ff05
+ .db "MCUSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUSR
+XT_MCUSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUSR:
+ .dw 84
+
+.endif
+.if WANT_EEPROM == 1
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Address Register Low Bytes
+VE_EEAR:
+ .dw $ff04
+ .db "EEAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEAR
+XT_EEAR:
+ .dw PFA_DOVARIABLE
+PFA_EEAR:
+ .dw 65
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw 64
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw 63
+
+.endif
+.if WANT_TWI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; TWI (Slave) Address Mask Register
+VE_TWAMR:
+ .dw $ff05
+ .db "TWAMR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWAMR
+XT_TWAMR:
+ .dw PFA_DOVARIABLE
+PFA_TWAMR:
+ .dw 189
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Bit Rate register
+VE_TWBR:
+ .dw $ff04
+ .db "TWBR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWBR
+XT_TWBR:
+ .dw PFA_DOVARIABLE
+PFA_TWBR:
+ .dw 184
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Control Register
+VE_TWCR:
+ .dw $ff04
+ .db "TWCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWCR
+XT_TWCR:
+ .dw PFA_DOVARIABLE
+PFA_TWCR:
+ .dw 188
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Status Register
+VE_TWSR:
+ .dw $ff04
+ .db "TWSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWSR
+XT_TWSR:
+ .dw PFA_DOVARIABLE
+PFA_TWSR:
+ .dw 185
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Data register
+VE_TWDR:
+ .dw $ff04
+ .db "TWDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWDR
+XT_TWDR:
+ .dw PFA_DOVARIABLE
+PFA_TWDR:
+ .dw 187
+; ( -- addr ) System Constant
+; R( -- )
+; TWI (Slave) Address register
+VE_TWAR:
+ .dw $ff04
+ .db "TWAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWAR
+XT_TWAR:
+ .dw PFA_DOVARIABLE
+PFA_TWAR:
+ .dw 186
+
+.endif
+.if WANT_USART1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR1:
+ .dw $ff04
+ .db "UDR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR1
+XT_UDR1:
+ .dw PFA_DOVARIABLE
+PFA_UDR1:
+ .dw 206
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR1A:
+ .dw $ff06
+ .db "UCSR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1A
+XT_UCSR1A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1A:
+ .dw 200
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR1B:
+ .dw $ff06
+ .db "UCSR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1B
+XT_UCSR1B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1B:
+ .dw 201
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR1C:
+ .dw $ff06
+ .db "UCSR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1C
+XT_UCSR1C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1C:
+ .dw 202
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Bytes
+VE_UBRR1:
+ .dw $ff05
+ .db "UBRR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR1
+XT_UBRR1:
+ .dw PFA_DOVARIABLE
+PFA_UBRR1:
+ .dw 204
+
+.endif
+.if WANT_SPI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR:
+ .dw $ff04
+ .db "SPDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR
+XT_SPDR:
+ .dw PFA_DOVARIABLE
+PFA_SPDR:
+ .dw 78
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR:
+ .dw $ff04
+ .db "SPSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR
+XT_SPSR:
+ .dw PFA_DOVARIABLE
+PFA_SPSR:
+ .dw 77
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR:
+ .dw $ff04
+ .db "SPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR
+XT_SPCR:
+ .dw PFA_DOVARIABLE
+PFA_SPCR:
+ .dw 76
+
+.endif
+.if WANT_WATCHDOG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCSR:
+ .dw $ff06
+ .db "WDTCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCSR
+XT_WDTCSR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCSR:
+ .dw 96
+
+.endif
+.if WANT_CPU == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw 95
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer
+VE_SP:
+ .dw $ff02
+ .db "SP"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SP
+XT_SP:
+ .dw PFA_DOVARIABLE
+PFA_SP:
+ .dw 93
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Calibration Value
+VE_OSCCAL:
+ .dw $ff06
+ .db "OSCCAL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSCCAL
+XT_OSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_OSCCAL:
+ .dw 102
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_CLKPR:
+ .dw $ff05
+ .db "CLKPR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKPR
+XT_CLKPR:
+ .dw PFA_DOVARIABLE
+PFA_CLKPR:
+ .dw 97
+; ( -- addr ) System Constant
+; R( -- )
+; Sleep Mode Control Register
+VE_SMCR:
+ .dw $ff04
+ .db "SMCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SMCR
+XT_SMCR:
+ .dw PFA_DOVARIABLE
+PFA_SMCR:
+ .dw 83
+; ( -- addr ) System Constant
+; R( -- )
+; RAM Page Z Select Register
+VE_RAMPZ:
+ .dw $ff05
+ .db "RAMPZ",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_RAMPZ
+XT_RAMPZ:
+ .dw PFA_DOVARIABLE
+PFA_RAMPZ:
+ .dw 91
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 2
+VE_GPIOR2:
+ .dw $ff06
+ .db "GPIOR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR2
+XT_GPIOR2:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR2:
+ .dw 75
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 1
+VE_GPIOR1:
+ .dw $ff06
+ .db "GPIOR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR1
+XT_GPIOR1:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR1:
+ .dw 74
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 0
+VE_GPIOR0:
+ .dw $ff06
+ .db "GPIOR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR0
+XT_GPIOR0:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR0:
+ .dw 62
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register0
+VE_PRR0:
+ .dw $ff04
+ .db "PRR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR0
+XT_PRR0:
+ .dw PFA_DOVARIABLE
+PFA_PRR0:
+ .dw 100
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register1
+VE_PRR1:
+ .dw $ff04
+ .db "PRR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR1
+XT_PRR1:
+ .dw PFA_DOVARIABLE
+PFA_PRR1:
+ .dw 101
+
+.endif
diff --git a/amforth-6.5/avr8/devices/atmega1284p/device.py b/amforth-6.5/avr8/devices/atmega1284p/device.py
new file mode 100644
index 0000000..73725c6
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega1284p/device.py
@@ -0,0 +1,423 @@
+# Generated Automatically
+
+# Partname ATmega1284P
+
+MCUREGS = {
+# Interrupt Vectors
+ 'INT0Addr' : '#2', # External Interrupt Request 0
+ 'INT1Addr' : '#4', # External Interrupt Request 1
+ 'INT2Addr' : '#6', # External Interrupt Request 2
+ 'PCINT0Addr' : '#8', # Pin Change Interrupt Request 0
+ 'PCINT1Addr' : '#10', # Pin Change Interrupt Request 1
+ 'PCINT2Addr' : '#12', # Pin Change Interrupt Request 2
+ 'PCINT3Addr' : '#14', # Pin Change Interrupt Request 3
+ 'WDTAddr' : '#16', # Watchdog Time-out Interrupt
+ 'TIMER2_COMPAAddr' : '#18', # Timer/Counter2 Compare Match A
+ 'TIMER2_COMPBAddr' : '#20', # Timer/Counter2 Compare Match B
+ 'TIMER2_OVFAddr' : '#22', # Timer/Counter2 Overflow
+ 'TIMER1_CAPTAddr' : '#24', # Timer/Counter1 Capture Event
+ 'TIMER1_COMPAAddr' : '#26', # Timer/Counter1 Compare Match A
+ 'TIMER1_COMPBAddr' : '#28', # Timer/Counter1 Compare Match B
+ 'TIMER1_OVFAddr' : '#30', # Timer/Counter1 Overflow
+ 'TIMER0_COMPAAddr' : '#32', # Timer/Counter0 Compare Match A
+ 'TIMER0_COMPBAddr' : '#34', # Timer/Counter0 Compare Match B
+ 'TIMER0_OVFAddr' : '#36', # Timer/Counter0 Overflow
+ 'SPI_STCAddr' : '#38', # SPI Serial Transfer Complete
+ 'USART0_RXAddr' : '#40', # USART0, Rx Complete
+ 'USART0_UDREAddr' : '#42', # USART0 Data register Empty
+ 'USART0_TXAddr' : '#44', # USART0, Tx Complete
+ 'ANALOG_COMPAddr' : '#46', # Analog Comparator
+ 'ADCAddr' : '#48', # ADC Conversion Complete
+ 'EE_READYAddr' : '#50', # EEPROM Ready
+ 'TWIAddr' : '#52', # 2-wire Serial Interface
+ 'SPM_READYAddr' : '#54', # Store Program Memory Read
+ 'USART1_RXAddr' : '#56', # USART1 RX complete
+ 'USART1_UDREAddr' : '#58', # USART1 Data Register Empty
+ 'USART1_TXAddr' : '#60', # USART1 TX complete
+ 'TIMER3_CAPTAddr' : '#62', # Timer/Counter3 Capture Event
+ 'TIMER3_COMPAAddr' : '#64', # Timer/Counter3 Compare Match A
+ 'TIMER3_COMPBAddr' : '#66', # Timer/Counter3 Compare Match B
+ 'TIMER3_OVFAddr' : '#68', # Timer/Counter3 Overflow
+
+# Module ANALOG_COMPARATOR
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
+ 'ACSR' : '$50', # Analog Comparator Control And
+ 'ACSR_ACD': '$80', # Analog Comparator Disable
+ 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
+ 'ACSR_ACO': '$20', # Analog Compare Output
+ 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
+ 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
+ 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
+ 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
+ 'DIDR1' : '$7f', # Digital Input Disable Register
+ 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
+ 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
+
+# Module USART0
+ 'UDR0' : '$c6', # USART I/O Data Register
+ 'UCSR0A' : '$c0', # USART Control and Status Regis
+ 'UCSR0A_RXC0': '$80', # USART Receive Complete
+ 'UCSR0A_TXC0': '$40', # USART Transmitt Complete
+ 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
+ 'UCSR0A_FE0': '$10', # Framing Error
+ 'UCSR0A_DOR0': '$8', # Data overRun
+ 'UCSR0A_UPE0': '$4', # Parity Error
+ 'UCSR0A_U2X0': '$2', # Double the USART transmission
+ 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
+ 'UCSR0B' : '$c1', # USART Control and Status Regis
+ 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
+ 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
+ 'UCSR0B_UDRIE0': '$20', # USART Data register Empty Inte
+ 'UCSR0B_RXEN0': '$10', # Receiver Enable
+ 'UCSR0B_TXEN0': '$8', # Transmitter Enable
+ 'UCSR0B_UCSZ02': '$4', # Character Size
+ 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
+ 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
+ 'UCSR0C' : '$c2', # USART Control and Status Regis
+ 'UCSR0C_UMSEL0': '$c0', # USART Mode Select
+ 'UCSR0C_UPM0': '$30', # Parity Mode Bits
+ 'UCSR0C_USBS0': '$8', # Stop Bit Select
+ 'UCSR0C_UCSZ0': '$6', # Character Size
+ 'UCSR0C_UCPOL0': '$1', # Clock Polarity
+ 'UBRR0' : '$c4', # USART Baud Rate Register Byte
+
+# Module PORTA
+ 'PORTA' : '$22', # Port A Data Register
+ 'DDRA' : '$21', # Port A Data Direction Register
+ 'PINA' : '$20', # Port A Input Pins
+
+# Module PORTB
+ 'PORTB' : '$25', # Port B Data Register
+ 'DDRB' : '$24', # Port B Data Direction Register
+ 'PINB' : '$23', # Port B Input Pins
+
+# Module PORTC
+ 'PORTC' : '$28', # Port C Data Register
+ 'DDRC' : '$27', # Port C Data Direction Register
+ 'PINC' : '$26', # Port C Input Pins
+
+# Module PORTD
+ 'PORTD' : '$2b', # Port D Data Register
+ 'DDRD' : '$2a', # Port D Data Direction Register
+ 'PIND' : '$29', # Port D Input Pins
+
+# Module TIMER_COUNTER_0
+ 'OCR0B' : '$48', # Timer/Counter0 Output Compare
+ 'OCR0A' : '$47', # Timer/Counter0 Output Compare
+ 'TCNT0' : '$46', # Timer/Counter0
+ 'TCCR0B' : '$45', # Timer/Counter Control Register
+ 'TCCR0B_FOC0A': '$80', # Force Output Compare A
+ 'TCCR0B_FOC0B': '$40', # Force Output Compare B
+ 'TCCR0B_WGM02': '$8', #
+ 'TCCR0B_CS0': '$7', # Clock Select
+ 'TCCR0A' : '$44', # Timer/Counter Control Registe
+ 'TCCR0A_COM0A': '$c0', # Compare Output Mode, Phase Cor
+ 'TCCR0A_COM0B': '$30', # Compare Output Mode, Fast PWm
+ 'TCCR0A_WGM0': '$3', # Waveform Generation Mode
+ 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
+ 'TIMSK0_OCIE0B': '$4', # Timer/Counter0 Output Compare
+ 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
+ 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
+ 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
+ 'TIFR0_OCF0B': '$4', # Timer/Counter0 Output Compare
+ 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
+ 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSRSYNC': '$1', # Prescaler Reset Timer/Counter1
+
+# Module TIMER_COUNTER_1
+ 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
+ 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
+ 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
+ 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
+ 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
+ 'TIFR1' : '$36', # Timer/Counter Interrupt Flag r
+ 'TIFR1_ICF1': '$20', # Timer/Counter1 Input Capture F
+ 'TIFR1_OCF1B': '$4', # Timer/Counter1 Output Compare
+ 'TIFR1_OCF1A': '$2', # Timer/Counter1 Output Compare
+ 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
+ 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
+ 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
+ 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
+ 'TCCR1A_WGM1': '$3', # Pulse Width Modulator Select B
+ 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
+ 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
+ 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
+ 'TCCR1B_WGM1': '$18', # Waveform Generation Mode Bits
+ 'TCCR1B_CS1': '$7', # Clock Select1 bits
+ 'TCCR1C' : '$82', # Timer/Counter1 Control Registe
+ 'TCCR1C_FOC1A': '$80', # Force Output Compare for Chann
+ 'TCCR1C_FOC1B': '$40', # Force Output Compare for Chann
+ 'TCNT1' : '$84', # Timer/Counter1 Bytes
+ 'OCR1A' : '$88', # Timer/Counter1 Output Compare
+ 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
+ 'ICR1' : '$86', # Timer/Counter1 Input Capture R
+
+# Module TIMER_COUNTER_2
+ 'TIMSK2' : '$70', # Timer/Counter Interrupt Mask r
+ 'TIMSK2_OCIE2B': '$4', # Timer/Counter2 Output Compare
+ 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
+ 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
+ 'TIFR2' : '$37', # Timer/Counter Interrupt Flag R
+ 'TIFR2_OCF2B': '$4', # Output Compare Flag 2B
+ 'TIFR2_OCF2A': '$2', # Output Compare Flag 2A
+ 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
+ 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
+ 'TCCR2A_COM2A': '$c0', # Compare Output Mode bits
+ 'TCCR2A_COM2B': '$30', # Compare Output Mode bits
+ 'TCCR2A_WGM2': '$3', # Waveform Genration Mode
+ 'TCCR2B' : '$b1', # Timer/Counter2 Control Registe
+ 'TCCR2B_FOC2A': '$80', # Force Output Compare A
+ 'TCCR2B_FOC2B': '$40', # Force Output Compare B
+ 'TCCR2B_WGM22': '$8', # Waveform Generation Mode
+ 'TCCR2B_CS2': '$7', # Clock Select bits
+ 'TCNT2' : '$b2', # Timer/Counter2
+ 'OCR2B' : '$b4', # Timer/Counter2 Output Compare
+ 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
+ 'ASSR' : '$b6', # Asynchronous Status Register
+ 'ASSR_EXCLK': '$40', # Enable External Clock Input
+ 'ASSR_AS2': '$20', # Asynchronous Timer/Counter2
+ 'ASSR_TCN2UB': '$10', # Timer/Counter2 Update Busy
+ 'ASSR_OCR2AUB': '$8', # Output Compare Register2 Updat
+ 'ASSR_OCR2BUB': '$4', # Output Compare Register 2 Upda
+ 'ASSR_TCR2AUB': '$2', # Timer/Counter Control Register
+ 'ASSR_TCR2BUB': '$1', # Timer/Counter Control Register
+ 'GTCCR' : '$43', # General Timer Counter Control
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSRASY': '$2', # Prescaler Reset Timer/Counter2
+
+# Module TIMER_COUNTER_3
+ 'TIMSK3' : '$71', # Timer/Counter3 Interrupt Mask
+ 'TIMSK3_ICIE3': '$20', # Timer/Counter3 Input Capture I
+ 'TIMSK3_OCIE3B': '$4', # Timer/Counter3 Output Compare
+ 'TIMSK3_OCIE3A': '$2', # Timer/Counter3 Output Compare
+ 'TIMSK3_TOIE3': '$1', # Timer/Counter3 Overflow Interr
+ 'TIFR3' : '$38', # Timer/Counter Interrupt Flag r
+ 'TIFR3_ICF3': '$20', # Timer/Counter3 Input Capture F
+ 'TIFR3_OCF3B': '$4', # Timer/Counter3 Output Compare
+ 'TIFR3_OCF3A': '$2', # Timer/Counter3 Output Compare
+ 'TIFR3_TOV3': '$1', # Timer/Counter3 Overflow Flag
+ 'TCCR3A' : '$90', # Timer/Counter3 Control Registe
+ 'TCCR3A_COM3A': '$c0', # Compare Output Mode 3A, bits
+ 'TCCR3A_COM3B': '$30', # Compare Output Mode 3B, bits
+ 'TCCR3A_WGM3': '$3', # Pulse Width Modulator Select B
+ 'TCCR3B' : '$91', # Timer/Counter3 Control Registe
+ 'TCCR3B_ICNC3': '$80', # Input Capture 3 Noise Canceler
+ 'TCCR3B_ICES3': '$40', # Input Capture 3 Edge Select
+ 'TCCR3B_WGM3': '$18', # Waveform Generation Mode Bits
+ 'TCCR3B_CS3': '$7', # Clock Select3 bits
+ 'TCCR3C' : '$92', # Timer/Counter3 Control Registe
+ 'TCCR3C_FOC3A': '$80', # Force Output Compare for Chann
+ 'TCCR3C_FOC3B': '$40', # Force Output Compare for Chann
+ 'TCNT3' : '$94', # Timer/Counter3 Bytes
+ 'OCR3A' : '$98', # Timer/Counter3 Output Compare
+ 'OCR3B' : '$9a', # Timer/Counter3 Output Compare
+ 'ICR3' : '$96', # Timer/Counter3 Input Capture R
+
+# Module BOOT_LOAD
+ 'SPMCSR' : '$57', # Store Program Memory Control R
+ 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
+ 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
+ 'SPMCSR_SIGRD': '$20', # Signature Row Read
+ 'SPMCSR_RWWSRE': '$10', # Read While Write section read
+ 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
+ 'SPMCSR_PGWRT': '$4', # Page Write
+ 'SPMCSR_PGERS': '$2', # Page Erase
+ 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
+
+# Module EXTERNAL_INTERRUPT
+ 'EICRA' : '$69', # External Interrupt Control Reg
+ 'EICRA_ISC2': '$30', # External Interrupt Sense Contr
+ 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
+ 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
+ 'EIMSK' : '$3d', # External Interrupt Mask Regist
+ 'EIMSK_INT': '$7', # External Interrupt Request 2 E
+ 'EIFR' : '$3c', # External Interrupt Flag Regist
+ 'EIFR_INTF': '$7', # External Interrupt Flags
+ 'PCMSK3' : '$73', # Pin Change Mask Register 3
+ 'PCMSK3_PCINT': '$ff', # Pin Change Enable Masks
+ 'PCMSK2' : '$6d', # Pin Change Mask Register 2
+ 'PCMSK2_PCINT': '$ff', # Pin Change Enable Masks
+ 'PCMSK1' : '$6c', # Pin Change Mask Register 1
+ 'PCMSK1_PCINT': '$ff', # Pin Change Enable Masks
+ 'PCMSK0' : '$6b', # Pin Change Mask Register 0
+ 'PCMSK0_PCINT': '$ff', # Pin Change Enable Masks
+ 'PCIFR' : '$3b', # Pin Change Interrupt Flag Regi
+ 'PCIFR_PCIF': '$f', # Pin Change Interrupt Flags
+ 'PCICR' : '$68', # Pin Change Interrupt Control R
+ 'PCICR_PCIE': '$f', # Pin Change Interrupt Enables
+
+# Module AD_CONVERTER
+ 'ADMUX' : '$7c', # The ADC multiplexer Selection
+ 'ADMUX_REFS': '$c0', # Reference Selection Bits
+ 'ADMUX_ADLAR': '$20', # Left Adjust Result
+ 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
+ 'ADC' : '$78', # ADC Data Register Bytes
+ 'ADCSRA' : '$7a', # The ADC Control and Status reg
+ 'ADCSRA_ADEN': '$80', # ADC Enable
+ 'ADCSRA_ADSC': '$40', # ADC Start Conversion
+ 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
+ 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
+ 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
+ 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
+ 'ADCSRB' : '$7b', # The ADC Control and Status reg
+ 'ADCSRB_ACME': '$40', #
+ 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Source bits
+ 'DIDR0' : '$7e', # Digital Input Disable Register
+ 'DIDR0_ADC7D': '$80', #
+ 'DIDR0_ADC6D': '$40', #
+ 'DIDR0_ADC5D': '$20', #
+ 'DIDR0_ADC4D': '$10', #
+ 'DIDR0_ADC3D': '$8', #
+ 'DIDR0_ADC2D': '$4', #
+ 'DIDR0_ADC1D': '$2', #
+ 'DIDR0_ADC0D': '$1', #
+
+# Module JTAG
+ 'OCDR' : '$51', # On-Chip Debug Related Register
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_JTD': '$80', # JTAG Interface Disable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+
+# Module EEPROM
+ 'EEAR' : '$41', # EEPROM Address Register Low By
+ 'EEDR' : '$40', # EEPROM Data Register
+ 'EECR' : '$3f', # EEPROM Control Register
+ 'EECR_EEPM': '$30', # EEPROM Programming Mode Bits
+ 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
+ 'EECR_EEMPE': '$4', # EEPROM Master Write Enable
+ 'EECR_EEPE': '$2', # EEPROM Write Enable
+ 'EECR_EERE': '$1', # EEPROM Read Enable
+
+# Module TWI
+ 'TWAMR' : '$bd', # TWI (Slave) Address Mask Regis
+ 'TWAMR_TWAM': '$fe', #
+ 'TWBR' : '$b8', # TWI Bit Rate register
+ 'TWCR' : '$bc', # TWI Control Register
+ 'TWCR_TWINT': '$80', # TWI Interrupt Flag
+ 'TWCR_TWEA': '$40', # TWI Enable Acknowledge Bit
+ 'TWCR_TWSTA': '$20', # TWI Start Condition Bit
+ 'TWCR_TWSTO': '$10', # TWI Stop Condition Bit
+ 'TWCR_TWWC': '$8', # TWI Write Collition Flag
+ 'TWCR_TWEN': '$4', # TWI Enable Bit
+ 'TWCR_TWIE': '$1', # TWI Interrupt Enable
+ 'TWSR' : '$b9', # TWI Status Register
+ 'TWSR_TWS': '$f8', # TWI Status
+ 'TWSR_TWPS': '$3', # TWI Prescaler
+ 'TWDR' : '$bb', # TWI Data register
+ 'TWAR' : '$ba', # TWI (Slave) Address register
+ 'TWAR_TWA': '$fe', # TWI (Slave) Address register B
+ 'TWAR_TWGCE': '$1', # TWI General Call Recognition E
+
+# Module USART1
+ 'UDR1' : '$ce', # USART I/O Data Register
+ 'UCSR1A' : '$c8', # USART Control and Status Regis
+ 'UCSR1A_RXC1': '$80', # USART Receive Complete
+ 'UCSR1A_TXC1': '$40', # USART Transmitt Complete
+ 'UCSR1A_UDRE1': '$20', # USART Data Register Empty
+ 'UCSR1A_FE1': '$10', # Framing Error
+ 'UCSR1A_DOR1': '$8', # Data overRun
+ 'UCSR1A_UPE1': '$4', # Parity Error
+ 'UCSR1A_U2X1': '$2', # Double the USART transmission
+ 'UCSR1A_MPCM1': '$1', # Multi-processor Communication
+ 'UCSR1B' : '$c9', # USART Control and Status Regis
+ 'UCSR1B_RXCIE1': '$80', # RX Complete Interrupt Enable
+ 'UCSR1B_TXCIE1': '$40', # TX Complete Interrupt Enable
+ 'UCSR1B_UDRIE1': '$20', # USART Data register Empty Inte
+ 'UCSR1B_RXEN1': '$10', # Receiver Enable
+ 'UCSR1B_TXEN1': '$8', # Transmitter Enable
+ 'UCSR1B_UCSZ12': '$4', # Character Size
+ 'UCSR1B_RXB81': '$2', # Receive Data Bit 8
+ 'UCSR1B_TXB81': '$1', # Transmit Data Bit 8
+ 'UCSR1C' : '$ca', # USART Control and Status Regis
+ 'UCSR1C_UMSEL1': '$c0', # USART Mode Select
+ 'UCSR1C_UPM1': '$30', # Parity Mode Bits
+ 'UCSR1C_USBS1': '$8', # Stop Bit Select
+ 'UCSR1C_UCSZ1': '$6', # Character Size
+ 'UCSR1C_UCPOL1': '$1', # Clock Polarity
+ 'UBRR1' : '$cc', # USART Baud Rate Register Byte
+
+# Module SPI
+ 'SPDR' : '$4e', # SPI Data Register
+ 'SPSR' : '$4d', # SPI Status Register
+ 'SPSR_SPIF': '$80', # SPI Interrupt Flag
+ 'SPSR_WCOL': '$40', # Write Collision Flag
+ 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
+ 'SPCR' : '$4c', # SPI Control Register
+ 'SPCR_SPIE': '$80', # SPI Interrupt Enable
+ 'SPCR_SPE': '$40', # SPI Enable
+ 'SPCR_DORD': '$20', # Data Order
+ 'SPCR_MSTR': '$10', # Master/Slave Select
+ 'SPCR_CPOL': '$8', # Clock polarity
+ 'SPCR_CPHA': '$4', # Clock Phase
+ 'SPCR_SPR': '$3', # SPI Clock Rate Selects
+
+# Module WATCHDOG
+ 'WDTCSR' : '$60', # Watchdog Timer Control Registe
+ 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
+ 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
+ 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
+ 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
+ 'WDTCSR_WDE': '$8', # Watch Dog Enable
+
+# Module CPU
+ 'SREG' : '$5f', # Status Register
+ 'SREG_I': '$80', # Global Interrupt Enable
+ 'SREG_T': '$40', # Bit Copy Storage
+ 'SREG_H': '$20', # Half Carry Flag
+ 'SREG_S': '$10', # Sign Bit
+ 'SREG_V': '$8', # Two's Complement Overflow Flag
+ 'SREG_N': '$4', # Negative Flag
+ 'SREG_Z': '$2', # Zero Flag
+ 'SREG_C': '$1', # Carry Flag
+ 'SP' : '$5d', # Stack Pointer
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_JTD': '$80', # JTAG Interface Disable
+ 'MCUCR_BODS': '$40', # BOD Power Down in Sleep
+ 'MCUCR_BODSE': '$20', # BOD Power Down in Sleep Enable
+ 'MCUCR_PUD': '$10', # Pull-up disable
+ 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
+ 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+ 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
+ 'MCUSR_BORF': '$4', # Brown-out Reset Flag
+ 'MCUSR_EXTRF': '$2', # External Reset Flag
+ 'MCUSR_PORF': '$1', # Power-on reset flag
+ 'OSCCAL' : '$66', # Oscillator Calibration Value
+ 'CLKPR' : '$61', #
+ 'CLKPR_CLKPCE': '$80', #
+ 'CLKPR_CLKPS': '$f', #
+ 'SMCR' : '$53', # Sleep Mode Control Register
+ 'SMCR_SM': '$e', # Sleep Mode Select bits
+ 'SMCR_SE': '$1', # Sleep Enable
+ 'RAMPZ' : '$5b', # RAM Page Z Select Register
+ 'GPIOR2' : '$4b', # General Purpose IO Register 2
+ 'GPIOR2_GPIOR': '$ff', # General Purpose IO Register 2
+ 'GPIOR1' : '$4a', # General Purpose IO Register 1
+ 'GPIOR1_GPIOR': '$ff', # General Purpose IO Register 1
+ 'GPIOR0' : '$3e', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR07': '$80', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR06': '$40', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR05': '$20', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR04': '$10', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR03': '$8', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR02': '$4', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR01': '$2', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR00': '$1', # General Purpose IO Register 0
+ 'PRR0' : '$64', # Power Reduction Register0
+ 'PRR0_PRTWI': '$80', # Power Reduction TWI
+ 'PRR0_PRTIM2': '$40', # Power Reduction Timer/Counter2
+ 'PRR0_PRTIM0': '$20', # Power Reduction Timer/Counter0
+ 'PRR0_PRUSART': '$12', # Power Reduction USARTs
+ 'PRR0_PRTIM1': '$8', # Power Reduction Timer/Counter1
+ 'PRR0_PRSPI': '$4', # Power Reduction Serial Periphe
+ 'PRR0_PRADC': '$1', # Power Reduction ADC
+ 'PRR1' : '$65', # Power Reduction Register1
+ 'PRR1_PRTIM3': '$1', # Power Reduction Timer/Counter3
+
+ '__amforth_dummy':'0'
+}
diff --git a/amforth-6.5/avr8/devices/atmega1284p/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega1284p/words/no-jtag.asm
new file mode 100644
index 0000000..352a4bb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega1284p/words/no-jtag.asm
@@ -0,0 +1,14 @@
+; ( -- )
+; ( -- )
+; MCU
+; disable jtag at runtime
+VE_NOJTAG:
+ .dw $FF05
+ .db "-jtag",0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOJTAG
+XT_NOJTAG:
+ .dw PFA_NOJTAG
+PFA_NOJTAG:
+
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega1284p/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega1284p/words/no-wdt.asm
new file mode 100644
index 0000000..ff6ddd1
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega1284p/words/no-wdt.asm
@@ -0,0 +1,34 @@
+; ( -- )
+; MCU
+; disable watch dog timer at runtime
+VE_NOWDT:
+ .dw $ff04
+ .db "-wdt"
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOWDT
+XT_NOWDT:
+ .dw PFA_NOWDT
+PFA_NOWDT:
+
+ in temp1,SREG
+ push temp1
+ ; Turn always off global interrupt.
+ cli
+ ; Reset Watchdog Timer
+ wdr
+ ; Clear WDRF in MCUSR
+ in temp1, MCUSR
+ andi temp1, (0xff & (0<<WDRF))
+ out MCUSR, temp1
+ ; Write logical one to WDCE and WDE
+ ; Keep old prescaler setting to prevent unintentional time-out
+ in_ temp1, WDTCSR
+ ori temp1, (1<<WDCE) | (1<<WDE)
+ out_ WDTCSR, temp1
+ ; Turn off WDT
+ ldi temp1, (0<<WDE)
+ out_ WDTCSR, temp1
+ ; restore status register
+ pop temp1
+ out SREG,temp1
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega1284p/words/sleep.asm b/amforth-6.5/avr8/devices/atmega1284p/words/sleep.asm
new file mode 100644
index 0000000..256249c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega1284p/words/sleep.asm
@@ -0,0 +1,19 @@
+; ( mode -- )
+; MCU
+; put the controller into the specified sleep mode
+VE_SLEEP:
+ .dw $ff05
+ .db "sleep", 0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_SLEEP
+XT_SLEEP:
+ .dw PFA_SLEEP
+PFA_SLEEP:
+ andi tosl, 7 ; leave only legal mode bits
+ lsl tosl ; move to correct location (bits 3-1)
+ ori tosl, 1 ; set the SE bit
+ out_ SMCR, tosl ; set the sleep config
+ sleep ; nighty-night
+ out_ SMCR, zerol ; 0 protects against accidental sleeps
+ loadtos ; pop argument from stack
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/AD_CONVERTER.frt b/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/AD_CONVERTER.frt
new file mode 100644
index 0000000..5920fc8
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/AD_CONVERTER.frt
@@ -0,0 +1,79 @@
+\ Generated automatically for atmega1284rfr2
+\ #require bitnames.frt
+
+\ AD_CONVERTER
+$7c constant ADMUX \ The ADC Multiplexer Selection
+ $c0 constant ADMUX_REFS \ Reference Selection Bits
+ 7c $c0 bitmask: ADMUX.REFS \ Reference Selection Bits
+ $20 constant ADMUX_ADLAR \ ADC Left Adjust Result
+ 7c $20 bitmask: ADMUX.ADLAR \ ADC Left Adjust Result
+ $1f constant ADMUX_MUX \ Analog Channel and Gain Select
+ 7c $1f bitmask: ADMUX.MUX \ Analog Channel and Gain Select
+$78 constant ADC \ ADC Data Register Bytes
+$7a constant ADCSRA \ The ADC Control and Status Reg
+ $80 constant ADCSRA_ADEN \ ADC Enable
+ 7a $80 bitmask: ADCSRA.ADEN \ ADC Enable
+ $40 constant ADCSRA_ADSC \ ADC Start Conversion
+ 7a $40 bitmask: ADCSRA.ADSC \ ADC Start Conversion
+ $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
+ 7a $20 bitmask: ADCSRA.ADATE \ ADC Auto Trigger Enable
+ $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
+ 7a $10 bitmask: ADCSRA.ADIF \ ADC Interrupt Flag
+ $8 constant ADCSRA_ADIE \ ADC Interrupt Enable
+ 7a $8 bitmask: ADCSRA.ADIE \ ADC Interrupt Enable
+ $7 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
+ 7a $7 bitmask: ADCSRA.ADPS \ ADC Prescaler Select Bits
+$7b constant ADCSRB \ The ADC Control and Status Reg
+ $80 constant ADCSRB_AVDDOK \ AVDD Supply Voltage OK
+ 7b $80 bitmask: ADCSRB.AVDDOK \ AVDD Supply Voltage OK
+ $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer
+ 7b $40 bitmask: ADCSRB.ACME \ Analog Comparator Multiplexer
+ $20 constant ADCSRB_REFOK \ Reference Voltage OK
+ 7b $20 bitmask: ADCSRB.REFOK \ Reference Voltage OK
+ $10 constant ADCSRB_ACCH \ Analog Channel Change
+ 7b $10 bitmask: ADCSRB.ACCH \ Analog Channel Change
+ $8 constant ADCSRB_MUX5 \ Analog Channel and Gain Select
+ 7b $8 bitmask: ADCSRB.MUX5 \ Analog Channel and Gain Select
+ $7 constant ADCSRB_ADTS \ ADC Auto Trigger Source
+ 7b $7 bitmask: ADCSRB.ADTS \ ADC Auto Trigger Source
+$77 constant ADCSRC \ The ADC Control and Status Reg
+ $c0 constant ADCSRC_ADTHT \ ADC Track-and-Hold Time
+ 77 $c0 bitmask: ADCSRC.ADTHT \ ADC Track-and-Hold Time
+ $20 constant ADCSRC_Res0 \ Reserved
+ 77 $20 bitmask: ADCSRC.Res0 \ Reserved
+ $1f constant ADCSRC_ADSUT \ ADC Start-up Time
+ 77 $1f bitmask: ADCSRC.ADSUT \ ADC Start-up Time
+$7d constant DIDR2 \ Digital Input Disable Register
+ $80 constant DIDR2_ADC15D \ Reserved Bits
+ 7d $80 bitmask: DIDR2.ADC15D \ Reserved Bits
+ $40 constant DIDR2_ADC14D \ Reserved Bits
+ 7d $40 bitmask: DIDR2.ADC14D \ Reserved Bits
+ $20 constant DIDR2_ADC13D \ Reserved Bits
+ 7d $20 bitmask: DIDR2.ADC13D \ Reserved Bits
+ $10 constant DIDR2_ADC12D \ Reserved Bits
+ 7d $10 bitmask: DIDR2.ADC12D \ Reserved Bits
+ $8 constant DIDR2_ADC11D \ Reserved Bits
+ 7d $8 bitmask: DIDR2.ADC11D \ Reserved Bits
+ $4 constant DIDR2_ADC10D \ Reserved Bits
+ 7d $4 bitmask: DIDR2.ADC10D \ Reserved Bits
+ $2 constant DIDR2_ADC9D \ Reserved Bits
+ 7d $2 bitmask: DIDR2.ADC9D \ Reserved Bits
+ $1 constant DIDR2_ADC8D \ Reserved Bits
+ 7d $1 bitmask: DIDR2.ADC8D \ Reserved Bits
+$7e constant DIDR0 \ Digital Input Disable Register
+ $80 constant DIDR0_ADC7D \ Disable ADC7:0 Digital Input
+ 7e $80 bitmask: DIDR0.ADC7D \ Disable ADC7:0 Digital Input
+ $40 constant DIDR0_ADC6D \ Disable ADC7:0 Digital Input
+ 7e $40 bitmask: DIDR0.ADC6D \ Disable ADC7:0 Digital Input
+ $20 constant DIDR0_ADC5D \ Disable ADC7:0 Digital Input
+ 7e $20 bitmask: DIDR0.ADC5D \ Disable ADC7:0 Digital Input
+ $10 constant DIDR0_ADC4D \ Disable ADC7:0 Digital Input
+ 7e $10 bitmask: DIDR0.ADC4D \ Disable ADC7:0 Digital Input
+ $8 constant DIDR0_ADC3D \ Disable ADC7:0 Digital Input
+ 7e $8 bitmask: DIDR0.ADC3D \ Disable ADC7:0 Digital Input
+ $4 constant DIDR0_ADC2D \ Disable ADC7:0 Digital Input
+ 7e $4 bitmask: DIDR0.ADC2D \ Disable ADC7:0 Digital Input
+ $2 constant DIDR0_ADC1D \ Disable ADC7:0 Digital Input
+ 7e $2 bitmask: DIDR0.ADC1D \ Disable ADC7:0 Digital Input
+ $1 constant DIDR0_ADC0D \ Disable ADC7:0 Digital Input
+ 7e $1 bitmask: DIDR0.ADC0D \ Disable ADC7:0 Digital Input
diff --git a/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/ANALOG_COMPARATOR.frt b/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/ANALOG_COMPARATOR.frt
new file mode 100644
index 0000000..0479c7f
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/ANALOG_COMPARATOR.frt
@@ -0,0 +1,27 @@
+\ Generated automatically for atmega1284rfr2
+\ #require bitnames.frt
+
+\ ANALOG_COMPARATOR
+$7b constant ADCSRB \ ADC Control and Status Registe
+ $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer
+ 7b $40 bitmask: ADCSRB.ACME \ Analog Comparator Multiplexer
+$50 constant ACSR \ Analog Comparator Control And
+ $80 constant ACSR_ACD \ Analog Comparator Disable
+ 50 $80 bitmask: ACSR.ACD \ Analog Comparator Disable
+ $40 constant ACSR_ACBG \ Analog Comparator Bandgap Sele
+ 50 $40 bitmask: ACSR.ACBG \ Analog Comparator Bandgap Sele
+ $20 constant ACSR_ACO \ Analog Compare Output
+ 50 $20 bitmask: ACSR.ACO \ Analog Compare Output
+ $10 constant ACSR_ACI \ Analog Comparator Interrupt Fl
+ 50 $10 bitmask: ACSR.ACI \ Analog Comparator Interrupt Fl
+ $8 constant ACSR_ACIE \ Analog Comparator Interrupt En
+ 50 $8 bitmask: ACSR.ACIE \ Analog Comparator Interrupt En
+ $4 constant ACSR_ACIC \ Analog Comparator Input Captur
+ 50 $4 bitmask: ACSR.ACIC \ Analog Comparator Input Captur
+ $3 constant ACSR_ACIS \ Analog Comparator Interrupt Mo
+ 50 $3 bitmask: ACSR.ACIS \ Analog Comparator Interrupt Mo
+$7f constant DIDR1 \ Digital Input Disable Register
+ $2 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
+ 7f $2 bitmask: DIDR1.AIN1D \ AIN1 Digital Input Disable
+ $1 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
+ 7f $1 bitmask: DIDR1.AIN0D \ AIN0 Digital Input Disable
diff --git a/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/BOOT_LOAD.frt b/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/BOOT_LOAD.frt
new file mode 100644
index 0000000..8d5a583
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/BOOT_LOAD.frt
@@ -0,0 +1,21 @@
+\ Generated automatically for atmega1284rfr2
+\ #require bitnames.frt
+
+\ BOOT_LOAD
+$57 constant SPMCSR \ Store Program Memory Control R
+ $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
+ 57 $80 bitmask: SPMCSR.SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
+ 57 $40 bitmask: SPMCSR.RWWSB \ Read While Write Section Busy
+ $20 constant SPMCSR_SIGRD \ Signature Row Read
+ 57 $20 bitmask: SPMCSR.SIGRD \ Signature Row Read
+ $10 constant SPMCSR_RWWSRE \ Read While Write Section Read
+ 57 $10 bitmask: SPMCSR.RWWSRE \ Read While Write Section Read
+ $8 constant SPMCSR_BLBSET \ Boot Lock Bit Set
+ 57 $8 bitmask: SPMCSR.BLBSET \ Boot Lock Bit Set
+ $4 constant SPMCSR_PGWRT \ Page Write
+ 57 $4 bitmask: SPMCSR.PGWRT \ Page Write
+ $2 constant SPMCSR_PGERS \ Page Erase
+ 57 $2 bitmask: SPMCSR.PGERS \ Page Erase
+ $1 constant SPMCSR_SPMEN \ Store Program Memory Enable
+ 57 $1 bitmask: SPMCSR.SPMEN \ Store Program Memory Enable
diff --git a/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/CPU.frt b/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/CPU.frt
new file mode 100644
index 0000000..ba7a278
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/CPU.frt
@@ -0,0 +1,128 @@
+\ Generated automatically for atmega1284rfr2
+\ #require bitnames.frt
+
+\ CPU
+$5f constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ 5f $80 bitmask: SREG.I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ 5f $40 bitmask: SREG.T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ 5f $20 bitmask: SREG.H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ 5f $10 bitmask: SREG.S \ Sign Bit
+ $8 constant SREG_V \ Two's Complement Overflow Flag
+ 5f $8 bitmask: SREG.V \ Two's Complement Overflow Flag
+ $4 constant SREG_N \ Negative Flag
+ 5f $4 bitmask: SREG.N \ Negative Flag
+ $2 constant SREG_Z \ Zero Flag
+ 5f $2 bitmask: SREG.Z \ Zero Flag
+ $1 constant SREG_C \ Carry Flag
+ 5f $1 bitmask: SREG.C \ Carry Flag
+$5d constant SP \ Stack Pointer
+$55 constant MCUCR \ MCU Control Register
+ $80 constant MCUCR_JTD \ JTAG Interface Disable
+ 55 $80 bitmask: MCUCR.JTD \ JTAG Interface Disable
+ $60 constant MCUCR_Res \ Reserved
+ 55 $60 bitmask: MCUCR.Res \ Reserved
+ $10 constant MCUCR_PUD \ Pull-up Disable
+ 55 $10 bitmask: MCUCR.PUD \ Pull-up Disable
+ $c constant MCUCR_Res \ Reserved
+ 55 $c bitmask: MCUCR.Res \ Reserved
+ $2 constant MCUCR_IVSEL \ Interrupt Vector Select
+ 55 $2 bitmask: MCUCR.IVSEL \ Interrupt Vector Select
+ $1 constant MCUCR_IVCE \ Interrupt Vector Change Enable
+ 55 $1 bitmask: MCUCR.IVCE \ Interrupt Vector Change Enable
+$54 constant MCUSR \ MCU Status Register
+ $e0 constant MCUSR_Res \ Reserved
+ 54 $e0 bitmask: MCUSR.Res \ Reserved
+ $10 constant MCUSR_JTRF \ JTAG Reset Flag
+ 54 $10 bitmask: MCUSR.JTRF \ JTAG Reset Flag
+ $8 constant MCUSR_WDRF \ Watchdog Reset Flag
+ 54 $8 bitmask: MCUSR.WDRF \ Watchdog Reset Flag
+ $4 constant MCUSR_BORF \ Brown-out Reset Flag
+ 54 $4 bitmask: MCUSR.BORF \ Brown-out Reset Flag
+ $2 constant MCUSR_EXTRF \ External Reset Flag
+ 54 $2 bitmask: MCUSR.EXTRF \ External Reset Flag
+ $1 constant MCUSR_PORF \ Power-on Reset Flag
+ 54 $1 bitmask: MCUSR.PORF \ Power-on Reset Flag
+$66 constant OSCCAL \ Oscillator Calibration Value
+ $ff constant OSCCAL_CAL \ Oscillator Calibration Tuning
+ 66 $ff bitmask: OSCCAL.CAL \ Oscillator Calibration Tuning
+$61 constant CLKPR \ Clock Prescale Register
+ $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable
+ 61 $80 bitmask: CLKPR.CLKPCE \ Clock Prescaler Change Enable
+ $70 constant CLKPR_Res \ Reserved
+ 61 $70 bitmask: CLKPR.Res \ Reserved
+ $f constant CLKPR_CLKPS \ Clock Prescaler Select Bits
+ 61 $f bitmask: CLKPR.CLKPS \ Clock Prescaler Select Bits
+$53 constant SMCR \ Sleep Mode Control Register
+ $f0 constant SMCR_Res \ Reserved
+ 53 $f0 bitmask: SMCR.Res \ Reserved
+ $e constant SMCR_SM \ Sleep Mode Select bits
+ 53 $e bitmask: SMCR.SM \ Sleep Mode Select bits
+ $1 constant SMCR_SE \ Sleep Enable
+ 53 $1 bitmask: SMCR.SE \ Sleep Enable
+$5b constant RAMPZ \ Extended Z-pointer Register fo
+ $fe constant RAMPZ_Res \ Reserved
+ 5b $fe bitmask: RAMPZ.Res \ Reserved
+ $1 constant RAMPZ_RAMPZ0 \ Extended Z-Pointer Value
+ 5b $1 bitmask: RAMPZ.RAMPZ0 \ Extended Z-Pointer Value
+$4b constant GPIOR2 \ General Purpose I/O Register 2
+ $ff constant GPIOR2_GPIOR \ General Purpose I/O Register 2
+ 4b $ff bitmask: GPIOR2.GPIOR \ General Purpose I/O Register 2
+$4a constant GPIOR1 \ General Purpose IO Register 1
+ $ff constant GPIOR1_GPIOR \ General Purpose I/O Register 1
+ 4a $ff bitmask: GPIOR1.GPIOR \ General Purpose I/O Register 1
+$3e constant GPIOR0 \ General Purpose IO Register 0
+ $80 constant GPIOR0_GPIOR07 \ General Purpose I/O Register 0
+ 3e $80 bitmask: GPIOR0.GPIOR07 \ General Purpose I/O Register 0
+ $40 constant GPIOR0_GPIOR06 \ General Purpose I/O Register 0
+ 3e $40 bitmask: GPIOR0.GPIOR06 \ General Purpose I/O Register 0
+ $20 constant GPIOR0_GPIOR05 \ General Purpose I/O Register 0
+ 3e $20 bitmask: GPIOR0.GPIOR05 \ General Purpose I/O Register 0
+ $10 constant GPIOR0_GPIOR04 \ General Purpose I/O Register 0
+ 3e $10 bitmask: GPIOR0.GPIOR04 \ General Purpose I/O Register 0
+ $8 constant GPIOR0_GPIOR03 \ General Purpose I/O Register 0
+ 3e $8 bitmask: GPIOR0.GPIOR03 \ General Purpose I/O Register 0
+ $4 constant GPIOR0_GPIOR02 \ General Purpose I/O Register 0
+ 3e $4 bitmask: GPIOR0.GPIOR02 \ General Purpose I/O Register 0
+ $2 constant GPIOR0_GPIOR01 \ General Purpose I/O Register 0
+ 3e $2 bitmask: GPIOR0.GPIOR01 \ General Purpose I/O Register 0
+ $1 constant GPIOR0_GPIOR00 \ General Purpose I/O Register 0
+ 3e $1 bitmask: GPIOR0.GPIOR00 \ General Purpose I/O Register 0
+$63 constant PRR2 \ Power Reduction Register 2
+ $f0 constant PRR2_Res \ Reserved Bit
+ 63 $f0 bitmask: PRR2.Res \ Reserved Bit
+ $f constant PRR2_PRRAM \ Power Reduction SRAMs
+ 63 $f bitmask: PRR2.PRRAM \ Power Reduction SRAMs
+$65 constant PRR1 \ Power Reduction Register 1
+ $80 constant PRR1_Res \ Reserved Bit
+ 65 $80 bitmask: PRR1.Res \ Reserved Bit
+ $40 constant PRR1_PRTRX24 \ Power Reduction Transceiver
+ 65 $40 bitmask: PRR1.PRTRX24 \ Power Reduction Transceiver
+ $20 constant PRR1_PRTIM5 \ Power Reduction Timer/Counter5
+ 65 $20 bitmask: PRR1.PRTIM5 \ Power Reduction Timer/Counter5
+ $10 constant PRR1_PRTIM4 \ Power Reduction Timer/Counter4
+ 65 $10 bitmask: PRR1.PRTIM4 \ Power Reduction Timer/Counter4
+ $8 constant PRR1_PRTIM3 \ Power Reduction Timer/Counter3
+ 65 $8 bitmask: PRR1.PRTIM3 \ Power Reduction Timer/Counter3
+ $1 constant PRR1_PRUSART1 \ Power Reduction USART1
+ 65 $1 bitmask: PRR1.PRUSART1 \ Power Reduction USART1
+$64 constant PRR0 \ Power Reduction Register0
+ $80 constant PRR0_PRTWI \ Power Reduction TWI
+ 64 $80 bitmask: PRR0.PRTWI \ Power Reduction TWI
+ $40 constant PRR0_PRTIM2 \ Power Reduction Timer/Counter2
+ 64 $40 bitmask: PRR0.PRTIM2 \ Power Reduction Timer/Counter2
+ $20 constant PRR0_PRTIM0 \ Power Reduction Timer/Counter0
+ 64 $20 bitmask: PRR0.PRTIM0 \ Power Reduction Timer/Counter0
+ $10 constant PRR0_PRPGA \ Power Reduction PGA
+ 64 $10 bitmask: PRR0.PRPGA \ Power Reduction PGA
+ $8 constant PRR0_PRTIM1 \ Power Reduction Timer/Counter1
+ 64 $8 bitmask: PRR0.PRTIM1 \ Power Reduction Timer/Counter1
+ $4 constant PRR0_PRSPI \ Power Reduction Serial Periphe
+ 64 $4 bitmask: PRR0.PRSPI \ Power Reduction Serial Periphe
+ $2 constant PRR0_PRUSART0 \ Power Reduction USART
+ 64 $2 bitmask: PRR0.PRUSART0 \ Power Reduction USART
+ $1 constant PRR0_PRADC \ Power Reduction ADC
+ 64 $1 bitmask: PRR0.PRADC \ Power Reduction ADC
diff --git a/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/EEPROM.frt b/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/EEPROM.frt
new file mode 100644
index 0000000..50cdbc0
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/EEPROM.frt
@@ -0,0 +1,19 @@
+\ Generated automatically for atmega1284rfr2
+\ #require bitnames.frt
+
+\ EEPROM
+$41 constant EEAR \ EEPROM Address Register Bytes
+$40 constant EEDR \ EEPROM Data Register
+$3f constant EECR \ EEPROM Control Register
+ $c0 constant EECR_Res \ Reserved
+ 3f $c0 bitmask: EECR.Res \ Reserved
+ $30 constant EECR_EEPM \ EEPROM Programming Mode
+ 3f $30 bitmask: EECR.EEPM \ EEPROM Programming Mode
+ $8 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
+ 3f $8 bitmask: EECR.EERIE \ EEPROM Ready Interrupt Enable
+ $4 constant EECR_EEMPE \ EEPROM Master Write Enable
+ 3f $4 bitmask: EECR.EEMPE \ EEPROM Master Write Enable
+ $2 constant EECR_EEPE \ EEPROM Programming Enable
+ 3f $2 bitmask: EECR.EEPE \ EEPROM Programming Enable
+ $1 constant EECR_EERE \ EEPROM Read Enable
+ 3f $1 bitmask: EECR.EERE \ EEPROM Read Enable
diff --git a/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/EXTERNAL_INTERRUPT.frt b/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/EXTERNAL_INTERRUPT.frt
new file mode 100644
index 0000000..2db4353
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/EXTERNAL_INTERRUPT.frt
@@ -0,0 +1,45 @@
+\ Generated automatically for atmega1284rfr2
+\ #require bitnames.frt
+
+\ EXTERNAL_INTERRUPT
+$69 constant EICRA \ External Interrupt Control Reg
+ $c0 constant EICRA_ISC3 \ External Interrupt 3 Sense Con
+ 69 $c0 bitmask: EICRA.ISC3 \ External Interrupt 3 Sense Con
+ $30 constant EICRA_ISC2 \ External Interrupt 2 Sense Con
+ 69 $30 bitmask: EICRA.ISC2 \ External Interrupt 2 Sense Con
+ $c constant EICRA_ISC1 \ External Interrupt 1 Sense Con
+ 69 $c bitmask: EICRA.ISC1 \ External Interrupt 1 Sense Con
+ $3 constant EICRA_ISC0 \ External Interrupt 0 Sense Con
+ 69 $3 bitmask: EICRA.ISC0 \ External Interrupt 0 Sense Con
+$6a constant EICRB \ External Interrupt Control Reg
+ $c0 constant EICRB_ISC7 \ External Interrupt 7 Sense Con
+ 6a $c0 bitmask: EICRB.ISC7 \ External Interrupt 7 Sense Con
+ $30 constant EICRB_ISC6 \ External Interrupt 6 Sense Con
+ 6a $30 bitmask: EICRB.ISC6 \ External Interrupt 6 Sense Con
+ $c constant EICRB_ISC5 \ External Interrupt 5 Sense Con
+ 6a $c bitmask: EICRB.ISC5 \ External Interrupt 5 Sense Con
+ $3 constant EICRB_ISC4 \ External Interrupt 4 Sense Con
+ 6a $3 bitmask: EICRB.ISC4 \ External Interrupt 4 Sense Con
+$3d constant EIMSK \ External Interrupt Mask Regist
+ $ff constant EIMSK_INT \ External Interrupt Request Ena
+ 3d $ff bitmask: EIMSK.INT \ External Interrupt Request Ena
+$3c constant EIFR \ External Interrupt Flag Regist
+ $ff constant EIFR_INTF \ External Interrupt Flag
+ 3c $ff bitmask: EIFR.INTF \ External Interrupt Flag
+$6d constant PCMSK2 \ Pin Change Mask Register 2
+ $ff constant PCMSK2_PCINT \ Pin Change Enable Mask
+ 6d $ff bitmask: PCMSK2.PCINT \ Pin Change Enable Mask
+$6c constant PCMSK1 \ Pin Change Mask Register 1
+ $ff constant PCMSK1_PCINT \ Pin Change Enable Mask
+ 6c $ff bitmask: PCMSK1.PCINT \ Pin Change Enable Mask
+$6b constant PCMSK0 \ Pin Change Mask Register 0
+$3b constant PCIFR \ Pin Change Interrupt Flag Regi
+ $f8 constant PCIFR_Res \ Reserved Bit
+ 3b $f8 bitmask: PCIFR.Res \ Reserved Bit
+ $7 constant PCIFR_PCIF \ Pin Change Interrupt Flags
+ 3b $7 bitmask: PCIFR.PCIF \ Pin Change Interrupt Flags
+$68 constant PCICR \ Pin Change Interrupt Control R
+ $f8 constant PCICR_Res \ Reserved Bit
+ 68 $f8 bitmask: PCICR.Res \ Reserved Bit
+ $7 constant PCICR_PCIE \ Pin Change Interrupt Enables
+ 68 $7 bitmask: PCICR.PCIE \ Pin Change Interrupt Enables
diff --git a/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/FLASH.frt b/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/FLASH.frt
new file mode 100644
index 0000000..de5d33e
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/FLASH.frt
@@ -0,0 +1,16 @@
+\ Generated automatically for atmega1284rfr2
+\ #require bitnames.frt
+
+\ FLASH
+$75 constant NEMCR \ Flash Extended-Mode Control-Re
+ $40 constant NEMCR_ENEAM \ Enable Extended Address Mode f
+ 75 $40 bitmask: NEMCR.ENEAM \ Enable Extended Address Mode f
+ $30 constant NEMCR_AEAM \ Address for Extended Address M
+ 75 $30 bitmask: NEMCR.AEAM \ Address for Extended Address M
+$67 constant BGCR \ Reference Voltage Calibration
+ $80 constant BGCR_Res \ Reserved Bit
+ 67 $80 bitmask: BGCR.Res \ Reserved Bit
+ $78 constant BGCR_BGCAL_FINE \ Fine Calibration Bits
+ 67 $78 bitmask: BGCR.BGCAL_FINE \ Fine Calibration Bits
+ $7 constant BGCR_BGCAL \ Coarse Calibration Bits
+ 67 $7 bitmask: BGCR.BGCAL \ Coarse Calibration Bits
diff --git a/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/JTAG.frt b/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/JTAG.frt
new file mode 100644
index 0000000..52b3f90
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/JTAG.frt
@@ -0,0 +1,13 @@
+\ Generated automatically for atmega1284rfr2
+\ #require bitnames.frt
+
+\ JTAG
+$51 constant OCDR \ On-Chip Debug Register
+ $ff constant OCDR_OCDR \ On-Chip Debug Register Data
+ 51 $ff bitmask: OCDR.OCDR \ On-Chip Debug Register Data
+$55 constant MCUCR \ MCU Control Register
+ $80 constant MCUCR_JTD \ JTAG Interface Disable
+ 55 $80 bitmask: MCUCR.JTD \ JTAG Interface Disable
+$54 constant MCUSR \ MCU Status Register
+ $10 constant MCUSR_JTRF \ JTAG Reset Flag
+ 54 $10 bitmask: MCUSR.JTRF \ JTAG Reset Flag
diff --git a/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/PORTA.frt b/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/PORTA.frt
new file mode 100644
index 0000000..e369e36
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/PORTA.frt
@@ -0,0 +1,7 @@
+\ Generated automatically for atmega1284rfr2
+\ #require bitnames.frt
+
+\ PORTA
+$22 constant PORTA \ Port A Data Register
+$21 constant DDRA \ Port A Data Direction Register
+$20 constant PINA \ Port A Input Pins Address
diff --git a/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/PORTB.frt b/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/PORTB.frt
new file mode 100644
index 0000000..1dd5691
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/PORTB.frt
@@ -0,0 +1,7 @@
+\ Generated automatically for atmega1284rfr2
+\ #require bitnames.frt
+
+\ PORTB
+$25 constant PORTB \ Port B Data Register
+$24 constant DDRB \ Port B Data Direction Register
+$23 constant PINB \ Port B Input Pins Address
diff --git a/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/PORTC.frt b/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/PORTC.frt
new file mode 100644
index 0000000..f3b7289
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/PORTC.frt
@@ -0,0 +1,7 @@
+\ Generated automatically for atmega1284rfr2
+\ #require bitnames.frt
+
+\ PORTC
+$28 constant PORTC \ Port C Data Register
+$27 constant DDRC \ Port C Data Direction Register
+$26 constant PINC \ Port C Input Pins Address
diff --git a/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/PORTD.frt b/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/PORTD.frt
new file mode 100644
index 0000000..50a7df1
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/PORTD.frt
@@ -0,0 +1,7 @@
+\ Generated automatically for atmega1284rfr2
+\ #require bitnames.frt
+
+\ PORTD
+$2b constant PORTD \ Port D Data Register
+$2a constant DDRD \ Port D Data Direction Register
+$29 constant PIND \ Port D Input Pins Address
diff --git a/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/PORTE.frt b/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/PORTE.frt
new file mode 100644
index 0000000..acc7ee9
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/PORTE.frt
@@ -0,0 +1,7 @@
+\ Generated automatically for atmega1284rfr2
+\ #require bitnames.frt
+
+\ PORTE
+$2e constant PORTE \ Port E Data Register
+$2d constant DDRE \ Port E Data Direction Register
+$2c constant PINE \ Port E Input Pins Address
diff --git a/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/PORTF.frt b/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/PORTF.frt
new file mode 100644
index 0000000..a7a1d12
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/PORTF.frt
@@ -0,0 +1,7 @@
+\ Generated automatically for atmega1284rfr2
+\ #require bitnames.frt
+
+\ PORTF
+$31 constant PORTF \ Port F Data Register
+$30 constant DDRF \ Port F Data Direction Register
+$2f constant PINF \ Port F Input Pins Address
diff --git a/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/PORTG.frt b/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/PORTG.frt
new file mode 100644
index 0000000..7b07cf8
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/PORTG.frt
@@ -0,0 +1,7 @@
+\ Generated automatically for atmega1284rfr2
+\ #require bitnames.frt
+
+\ PORTG
+$34 constant PORTG \ Port G Data Register
+$33 constant DDRG \ Port G Data Direction Register
+$32 constant PING \ Port G Input Pins Address
diff --git a/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/PWRCTRL.frt b/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/PWRCTRL.frt
new file mode 100644
index 0000000..1a76e14
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/PWRCTRL.frt
@@ -0,0 +1,81 @@
+\ Generated automatically for atmega1284rfr2
+\ #require bitnames.frt
+
+\ PWRCTRL
+$139 constant TRXPR \ Transceiver Pin Register
+ $f0 constant TRXPR_Res \ Reserved
+ 139 $f0 bitmask: TRXPR.Res \ Reserved
+ $2 constant TRXPR_SLPTR \ Multi-purpose Transceiver Cont
+ 139 $2 bitmask: TRXPR.SLPTR \ Multi-purpose Transceiver Cont
+ $1 constant TRXPR_TRXRST \ Force Transceiver Reset
+ 139 $1 bitmask: TRXPR.TRXRST \ Force Transceiver Reset
+$135 constant DRTRAM0 \ Data Retention Configuration R
+ $c0 constant DRTRAM0_Res \ Reserved
+ 135 $c0 bitmask: DRTRAM0.Res \ Reserved
+ $20 constant DRTRAM0_DRTSWOK \ DRT Switch OK
+ 135 $20 bitmask: DRTRAM0.DRTSWOK \ DRT Switch OK
+ $10 constant DRTRAM0_ENDRT \ Enable SRAM Data Retention
+ 135 $10 bitmask: DRTRAM0.ENDRT \ Enable SRAM Data Retention
+$134 constant DRTRAM1 \ Data Retention Configuration R
+ $c0 constant DRTRAM1_Res \ Reserved
+ 134 $c0 bitmask: DRTRAM1.Res \ Reserved
+ $20 constant DRTRAM1_DRTSWOK \ DRT Switch OK
+ 134 $20 bitmask: DRTRAM1.DRTSWOK \ DRT Switch OK
+ $10 constant DRTRAM1_ENDRT \ Enable SRAM Data Retention
+ 134 $10 bitmask: DRTRAM1.ENDRT \ Enable SRAM Data Retention
+$133 constant DRTRAM2 \ Data Retention Configuration R
+ $40 constant DRTRAM2_Res \ Reserved Bit
+ 133 $40 bitmask: DRTRAM2.Res \ Reserved Bit
+ $20 constant DRTRAM2_DRTSWOK \ DRT Switch OK
+ 133 $20 bitmask: DRTRAM2.DRTSWOK \ DRT Switch OK
+ $10 constant DRTRAM2_ENDRT \ Enable SRAM Data Retention
+ 133 $10 bitmask: DRTRAM2.ENDRT \ Enable SRAM Data Retention
+$132 constant DRTRAM3 \ Data Retention Configuration R
+ $c0 constant DRTRAM3_Res \ Reserved
+ 132 $c0 bitmask: DRTRAM3.Res \ Reserved
+ $20 constant DRTRAM3_DRTSWOK \ DRT Switch OK
+ 132 $20 bitmask: DRTRAM3.DRTSWOK \ DRT Switch OK
+ $10 constant DRTRAM3_ENDRT \ Enable SRAM Data Retention
+ 132 $10 bitmask: DRTRAM3.ENDRT \ Enable SRAM Data Retention
+$130 constant LLDRL \ Low Leakage Voltage Regulator
+ $f0 constant LLDRL_Res \ Reserved
+ 130 $f0 bitmask: LLDRL.Res \ Reserved
+ $f constant LLDRL_LLDRL \ Low-Byte Data Register Bits
+ 130 $f bitmask: LLDRL.LLDRL \ Low-Byte Data Register Bits
+$131 constant LLDRH \ Low Leakage Voltage Regulator
+ $e0 constant LLDRH_Res \ Reserved
+ 131 $e0 bitmask: LLDRH.Res \ Reserved
+ $1f constant LLDRH_LLDRH \ High-Byte Data Register Bits
+ 131 $1f bitmask: LLDRH.LLDRH \ High-Byte Data Register Bits
+$12f constant LLCR \ Low Leakage Voltage Regulator
+ $c0 constant LLCR_Res \ Reserved Bit
+ 12f $c0 bitmask: LLCR.Res \ Reserved Bit
+ $20 constant LLCR_LLDONE \ Calibration Done
+ 12f $20 bitmask: LLCR.LLDONE \ Calibration Done
+ $10 constant LLCR_LLCOMP \ Comparator Output
+ 12f $10 bitmask: LLCR.LLCOMP \ Comparator Output
+ $8 constant LLCR_LLCAL \ Calibration Active
+ 12f $8 bitmask: LLCR.LLCAL \ Calibration Active
+ $4 constant LLCR_LLTCO \ Temperature Coefficient of Cur
+ 12f $4 bitmask: LLCR.LLTCO \ Temperature Coefficient of Cur
+ $2 constant LLCR_LLSHORT \ Short Lower Calibration Circui
+ 12f $2 bitmask: LLCR.LLSHORT \ Short Lower Calibration Circui
+ $1 constant LLCR_LLENCAL \ Enable Automatic Calibration
+ 12f $1 bitmask: LLCR.LLENCAL \ Enable Automatic Calibration
+$136 constant DPDS0 \ Port Driver Strength Register
+ $c0 constant DPDS0_PFDRV \ Driver Strength Port F
+ 136 $c0 bitmask: DPDS0.PFDRV \ Driver Strength Port F
+ $30 constant DPDS0_PEDRV \ Driver Strength Port E
+ 136 $30 bitmask: DPDS0.PEDRV \ Driver Strength Port E
+ $c constant DPDS0_PDDRV \ Driver Strength Port D
+ 136 $c bitmask: DPDS0.PDDRV \ Driver Strength Port D
+ $3 constant DPDS0_PBDRV \ Driver Strength Port B
+ 136 $3 bitmask: DPDS0.PBDRV \ Driver Strength Port B
+$137 constant DPDS1 \ Port Driver Strength Register
+ $fc constant DPDS1_Res \ Reserved
+ 137 $fc bitmask: DPDS1.Res \ Reserved
+ $3 constant DPDS1_PGDRV \ Driver Strength Port G
+ 137 $3 bitmask: DPDS1.PGDRV \ Driver Strength Port G
+$55 constant MCUCR \ MCU Control Register
+ $10 constant MCUCR_PUD \ Pull-up Disable
+ 55 $10 bitmask: MCUCR.PUD \ Pull-up Disable
diff --git a/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/SPI.frt b/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/SPI.frt
new file mode 100644
index 0000000..e4945a3
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/SPI.frt
@@ -0,0 +1,29 @@
+\ Generated automatically for atmega1284rfr2
+\ #require bitnames.frt
+
+\ SPI
+$4c constant SPCR \ SPI Control Register
+ $80 constant SPCR_SPIE \ SPI Interrupt Enable
+ 4c $80 bitmask: SPCR.SPIE \ SPI Interrupt Enable
+ $40 constant SPCR_SPE \ SPI Enable
+ 4c $40 bitmask: SPCR.SPE \ SPI Enable
+ $20 constant SPCR_DORD \ Data Order
+ 4c $20 bitmask: SPCR.DORD \ Data Order
+ $10 constant SPCR_MSTR \ Master/Slave Select
+ 4c $10 bitmask: SPCR.MSTR \ Master/Slave Select
+ $8 constant SPCR_CPOL \ Clock polarity
+ 4c $8 bitmask: SPCR.CPOL \ Clock polarity
+ $4 constant SPCR_CPHA \ Clock Phase
+ 4c $4 bitmask: SPCR.CPHA \ Clock Phase
+ $3 constant SPCR_SPR \ SPI Clock Rate Select 1 and 0
+ 4c $3 bitmask: SPCR.SPR \ SPI Clock Rate Select 1 and 0
+$4d constant SPSR \ SPI Status Register
+ $80 constant SPSR_SPIF \ SPI Interrupt Flag
+ 4d $80 bitmask: SPSR.SPIF \ SPI Interrupt Flag
+ $40 constant SPSR_WCOL \ Write Collision Flag
+ 4d $40 bitmask: SPSR.WCOL \ Write Collision Flag
+ $3e constant SPSR_Res \ Reserved
+ 4d $3e bitmask: SPSR.Res \ Reserved
+ $1 constant SPSR_SPI2X \ Double SPI Speed Bit
+ 4d $1 bitmask: SPSR.SPI2X \ Double SPI Speed Bit
+$4e constant SPDR \ SPI Data Register
diff --git a/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/SYMCNT.frt b/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/SYMCNT.frt
new file mode 100644
index 0000000..fe7500d
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/SYMCNT.frt
@@ -0,0 +1,156 @@
+\ Generated automatically for atmega1284rfr2
+\ #require bitnames.frt
+
+\ SYMCNT
+$fc constant SCTSTRHH \ Symbol Counter Transmit Frame
+ $ff constant SCTSTRHH_SCTSTRHH \ Symbol Counter Transmit Frame
+ fc $ff bitmask: SCTSTRHH.SCTSTRHH \ Symbol Counter Transmit Frame
+$fb constant SCTSTRHL \ Symbol Counter Transmit Frame
+ $ff constant SCTSTRHL_SCTSTRHL \ Symbol Counter Transmit Frame
+ fb $ff bitmask: SCTSTRHL.SCTSTRHL \ Symbol Counter Transmit Frame
+$fa constant SCTSTRLH \ Symbol Counter Transmit Frame
+ $ff constant SCTSTRLH_SCTSTRLH \ Symbol Counter Transmit Frame
+ fa $ff bitmask: SCTSTRLH.SCTSTRLH \ Symbol Counter Transmit Frame
+$f9 constant SCTSTRLL \ Symbol Counter Transmit Frame
+ $ff constant SCTSTRLL_SCTSTRLL \ Symbol Counter Transmit Frame
+ f9 $ff bitmask: SCTSTRLL.SCTSTRLL \ Symbol Counter Transmit Frame
+$f8 constant SCOCR1HH \ Symbol Counter Output Compare
+ $ff constant SCOCR1HH_SCOCR1HH \ Symbol Counter Output Compare
+ f8 $ff bitmask: SCOCR1HH.SCOCR1HH \ Symbol Counter Output Compare
+$f7 constant SCOCR1HL \ Symbol Counter Output Compare
+ $ff constant SCOCR1HL_SCOCR1HL \ Symbol Counter Output Compare
+ f7 $ff bitmask: SCOCR1HL.SCOCR1HL \ Symbol Counter Output Compare
+$f6 constant SCOCR1LH \ Symbol Counter Output Compare
+ $ff constant SCOCR1LH_SCOCR1LH \ Symbol Counter Output Compare
+ f6 $ff bitmask: SCOCR1LH.SCOCR1LH \ Symbol Counter Output Compare
+$f5 constant SCOCR1LL \ Symbol Counter Output Compare
+ $ff constant SCOCR1LL_SCOCR1LL \ Symbol Counter Output Compare
+ f5 $ff bitmask: SCOCR1LL.SCOCR1LL \ Symbol Counter Output Compare
+$f4 constant SCOCR2HH \ Symbol Counter Output Compare
+ $ff constant SCOCR2HH_SCOCR2HH \ Symbol Counter Output Compare
+ f4 $ff bitmask: SCOCR2HH.SCOCR2HH \ Symbol Counter Output Compare
+$f3 constant SCOCR2HL \ Symbol Counter Output Compare
+ $ff constant SCOCR2HL_SCOCR2HL \ Symbol Counter Output Compare
+ f3 $ff bitmask: SCOCR2HL.SCOCR2HL \ Symbol Counter Output Compare
+$f2 constant SCOCR2LH \ Symbol Counter Output Compare
+ $ff constant SCOCR2LH_SCOCR2LH \ Symbol Counter Output Compare
+ f2 $ff bitmask: SCOCR2LH.SCOCR2LH \ Symbol Counter Output Compare
+$f1 constant SCOCR2LL \ Symbol Counter Output Compare
+ $ff constant SCOCR2LL_SCOCR2LL \ Symbol Counter Output Compare
+ f1 $ff bitmask: SCOCR2LL.SCOCR2LL \ Symbol Counter Output Compare
+$f0 constant SCOCR3HH \ Symbol Counter Output Compare
+ $ff constant SCOCR3HH_SCOCR3HH \ Symbol Counter Output Compare
+ f0 $ff bitmask: SCOCR3HH.SCOCR3HH \ Symbol Counter Output Compare
+$ef constant SCOCR3HL \ Symbol Counter Output Compare
+ $ff constant SCOCR3HL_SCOCR3HL \ Symbol Counter Output Compare
+ ef $ff bitmask: SCOCR3HL.SCOCR3HL \ Symbol Counter Output Compare
+$ee constant SCOCR3LH \ Symbol Counter Output Compare
+ $ff constant SCOCR3LH_SCOCR3LH \ Symbol Counter Output Compare
+ ee $ff bitmask: SCOCR3LH.SCOCR3LH \ Symbol Counter Output Compare
+$ed constant SCOCR3LL \ Symbol Counter Output Compare
+ $ff constant SCOCR3LL_SCOCR3LL \ Symbol Counter Output Compare
+ ed $ff bitmask: SCOCR3LL.SCOCR3LL \ Symbol Counter Output Compare
+$ec constant SCTSRHH \ Symbol Counter Frame Timestamp
+ $ff constant SCTSRHH_SCTSRHH \ Symbol Counter Frame Timestamp
+ ec $ff bitmask: SCTSRHH.SCTSRHH \ Symbol Counter Frame Timestamp
+$eb constant SCTSRHL \ Symbol Counter Frame Timestamp
+ $ff constant SCTSRHL_SCTSRHL \ Symbol Counter Frame Timestamp
+ eb $ff bitmask: SCTSRHL.SCTSRHL \ Symbol Counter Frame Timestamp
+$ea constant SCTSRLH \ Symbol Counter Frame Timestamp
+ $ff constant SCTSRLH_SCTSRLH \ Symbol Counter Frame Timestamp
+ ea $ff bitmask: SCTSRLH.SCTSRLH \ Symbol Counter Frame Timestamp
+$e9 constant SCTSRLL \ Symbol Counter Frame Timestamp
+ $ff constant SCTSRLL_SCTSRLL \ Symbol Counter Frame Timestamp
+ e9 $ff bitmask: SCTSRLL.SCTSRLL \ Symbol Counter Frame Timestamp
+$e8 constant SCBTSRHH \ Symbol Counter Beacon Timestam
+ $ff constant SCBTSRHH_SCBTSRHH \ Symbol Counter Beacon Timestam
+ e8 $ff bitmask: SCBTSRHH.SCBTSRHH \ Symbol Counter Beacon Timestam
+$e7 constant SCBTSRHL \ Symbol Counter Beacon Timestam
+ $ff constant SCBTSRHL_SCBTSRHL \ Symbol Counter Beacon Timestam
+ e7 $ff bitmask: SCBTSRHL.SCBTSRHL \ Symbol Counter Beacon Timestam
+$e6 constant SCBTSRLH \ Symbol Counter Beacon Timestam
+ $ff constant SCBTSRLH_SCBTSRLH \ Symbol Counter Beacon Timestam
+ e6 $ff bitmask: SCBTSRLH.SCBTSRLH \ Symbol Counter Beacon Timestam
+$e5 constant SCBTSRLL \ Symbol Counter Beacon Timestam
+ $ff constant SCBTSRLL_SCBTSRLL \ Symbol Counter Beacon Timestam
+ e5 $ff bitmask: SCBTSRLL.SCBTSRLL \ Symbol Counter Beacon Timestam
+$e4 constant SCCNTHH \ Symbol Counter Register HH-Byt
+ $ff constant SCCNTHH_SCCNTHH \ Symbol Counter Register HH-Byt
+ e4 $ff bitmask: SCCNTHH.SCCNTHH \ Symbol Counter Register HH-Byt
+$e3 constant SCCNTHL \ Symbol Counter Register HL-Byt
+ $ff constant SCCNTHL_SCCNTHL \ Symbol Counter Register HL-Byt
+ e3 $ff bitmask: SCCNTHL.SCCNTHL \ Symbol Counter Register HL-Byt
+$e2 constant SCCNTLH \ Symbol Counter Register LH-Byt
+ $ff constant SCCNTLH_SCCNTLH \ Symbol Counter Register LH-Byt
+ e2 $ff bitmask: SCCNTLH.SCCNTLH \ Symbol Counter Register LH-Byt
+$e1 constant SCCNTLL \ Symbol Counter Register LL-Byt
+ $ff constant SCCNTLL_SCCNTLL \ Symbol Counter Register LL-Byt
+ e1 $ff bitmask: SCCNTLL.SCCNTLL \ Symbol Counter Register LL-Byt
+$e0 constant SCIRQS \ Symbol Counter Interrupt Statu
+ $e0 constant SCIRQS_Res \ Reserved Bit
+ e0 $e0 bitmask: SCIRQS.Res \ Reserved Bit
+ $10 constant SCIRQS_IRQSBO \ Backoff Slot Counter IRQ
+ e0 $10 bitmask: SCIRQS.IRQSBO \ Backoff Slot Counter IRQ
+ $8 constant SCIRQS_IRQSOF \ Symbol Counter Overflow IRQ
+ e0 $8 bitmask: SCIRQS.IRQSOF \ Symbol Counter Overflow IRQ
+ $7 constant SCIRQS_IRQSCP \ Compare Unit 3 Compare Match I
+ e0 $7 bitmask: SCIRQS.IRQSCP \ Compare Unit 3 Compare Match I
+$df constant SCIRQM \ Symbol Counter Interrupt Mask
+ $e0 constant SCIRQM_Res \ Reserved Bit
+ df $e0 bitmask: SCIRQM.Res \ Reserved Bit
+ $10 constant SCIRQM_IRQMBO \ Backoff Slot Counter IRQ enabl
+ df $10 bitmask: SCIRQM.IRQMBO \ Backoff Slot Counter IRQ enabl
+ $8 constant SCIRQM_IRQMOF \ Symbol Counter Overflow IRQ en
+ df $8 bitmask: SCIRQM.IRQMOF \ Symbol Counter Overflow IRQ en
+ $7 constant SCIRQM_IRQMCP \ Symbol Counter Compare Match 3
+ df $7 bitmask: SCIRQM.IRQMCP \ Symbol Counter Compare Match 3
+$de constant SCSR \ Symbol Counter Status Register
+ $fe constant SCSR_Res \ Reserved Bit
+ de $fe bitmask: SCSR.Res \ Reserved Bit
+ $1 constant SCSR_SCBSY \ Symbol Counter busy
+ de $1 bitmask: SCSR.SCBSY \ Symbol Counter busy
+$dd constant SCCR1 \ Symbol Counter Control Registe
+ $c0 constant SCCR1_Res \ Reserved Bit
+ dd $c0 bitmask: SCCR1.Res \ Reserved Bit
+ $20 constant SCCR1_SCBTSM \ Symbol Counter Beacon Timestam
+ dd $20 bitmask: SCCR1.SCBTSM \ Symbol Counter Beacon Timestam
+ $1c constant SCCR1_SCCKDIV \ Clock divider for synchronous
+ dd $1c bitmask: SCCR1.SCCKDIV \ Clock divider for synchronous
+ $2 constant SCCR1_SCEECLK \ Enable External Clock Source o
+ dd $2 bitmask: SCCR1.SCEECLK \ Enable External Clock Source o
+ $1 constant SCCR1_SCENBO \ Backoff Slot Counter enable
+ dd $1 bitmask: SCCR1.SCENBO \ Backoff Slot Counter enable
+$dc constant SCCR0 \ Symbol Counter Control Registe
+ $80 constant SCCR0_SCRES \ Symbol Counter Synchronization
+ dc $80 bitmask: SCCR0.SCRES \ Symbol Counter Synchronization
+ $40 constant SCCR0_SCMBTS \ Manual Beacon Timestamp
+ dc $40 bitmask: SCCR0.SCMBTS \ Manual Beacon Timestamp
+ $20 constant SCCR0_SCEN \ Symbol Counter enable
+ dc $20 bitmask: SCCR0.SCEN \ Symbol Counter enable
+ $10 constant SCCR0_SCCKSEL \ Symbol Counter Clock Source se
+ dc $10 bitmask: SCCR0.SCCKSEL \ Symbol Counter Clock Source se
+ $8 constant SCCR0_SCTSE \ Symbol Counter Automatic Times
+ dc $8 bitmask: SCCR0.SCTSE \ Symbol Counter Automatic Times
+ $7 constant SCCR0_SCCMP \ Symbol Counter Compare Unit 3
+ dc $7 bitmask: SCCR0.SCCMP \ Symbol Counter Compare Unit 3
+$db constant SCCSR \ Symbol Counter Compare Source
+ $c0 constant SCCSR_Res \ Reserved Bit
+ db $c0 bitmask: SCCSR.Res \ Reserved Bit
+ $30 constant SCCSR_SCCS3 \ Symbol Counter Compare Source
+ db $30 bitmask: SCCSR.SCCS3 \ Symbol Counter Compare Source
+ $c constant SCCSR_SCCS2 \ Symbol Counter Compare Source
+ db $c bitmask: SCCSR.SCCS2 \ Symbol Counter Compare Source
+ $3 constant SCCSR_SCCS1 \ Symbol Counter Compare Source
+ db $3 bitmask: SCCSR.SCCS1 \ Symbol Counter Compare Source
+$da constant SCRSTRHH \ Symbol Counter Received Frame
+ $ff constant SCRSTRHH_SCRSTRHH \ Symbol Counter Received Frame
+ da $ff bitmask: SCRSTRHH.SCRSTRHH \ Symbol Counter Received Frame
+$d9 constant SCRSTRHL \ Symbol Counter Received Frame
+ $ff constant SCRSTRHL_SCRSTRHL \ Symbol Counter Received Frame
+ d9 $ff bitmask: SCRSTRHL.SCRSTRHL \ Symbol Counter Received Frame
+$d8 constant SCRSTRLH \ Symbol Counter Received Frame
+ $ff constant SCRSTRLH_SCRSTRLH \ Symbol Counter Received Frame
+ d8 $ff bitmask: SCRSTRLH.SCRSTRLH \ Symbol Counter Received Frame
+$d7 constant SCRSTRLL \ Symbol Counter Received Frame
+ $ff constant SCRSTRLL_SCRSTRLL \ Symbol Counter Received Frame
+ d7 $ff bitmask: SCRSTRLL.SCRSTRLL \ Symbol Counter Received Frame
diff --git a/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/TIMER_COUNTER_0.frt b/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/TIMER_COUNTER_0.frt
new file mode 100644
index 0000000..c3d1a1f
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/TIMER_COUNTER_0.frt
@@ -0,0 +1,54 @@
+\ Generated automatically for atmega1284rfr2
+\ #require bitnames.frt
+
+\ TIMER_COUNTER_0
+$48 constant OCR0B \ Timer/Counter0 Output Compare
+$47 constant OCR0A \ Timer/Counter0 Output Compare
+$46 constant TCNT0 \ Timer/Counter0 Register
+$45 constant TCCR0B \ Timer/Counter0 Control Registe
+ $80 constant TCCR0B_FOC0A \ Force Output Compare A
+ 45 $80 bitmask: TCCR0B.FOC0A \ Force Output Compare A
+ $40 constant TCCR0B_FOC0B \ Force Output Compare B
+ 45 $40 bitmask: TCCR0B.FOC0B \ Force Output Compare B
+ $30 constant TCCR0B_Res \ Reserved Bit
+ 45 $30 bitmask: TCCR0B.Res \ Reserved Bit
+ $8 constant TCCR0B_WGM02 \
+ 45 $8 bitmask: TCCR0B.WGM02 \
+ $7 constant TCCR0B_CS0 \ Clock Select
+ 45 $7 bitmask: TCCR0B.CS0 \ Clock Select
+$44 constant TCCR0A \ Timer/Counter0 Control Registe
+ $c0 constant TCCR0A_COM0A \ Compare Match Output A Mode
+ 44 $c0 bitmask: TCCR0A.COM0A \ Compare Match Output A Mode
+ $30 constant TCCR0A_COM0B \ Compare Match Output B Mode
+ 44 $30 bitmask: TCCR0A.COM0B \ Compare Match Output B Mode
+ $c constant TCCR0A_Res \ Reserved Bit
+ 44 $c bitmask: TCCR0A.Res \ Reserved Bit
+ $3 constant TCCR0A_WGM0 \ Waveform Generation Mode
+ 44 $3 bitmask: TCCR0A.WGM0 \ Waveform Generation Mode
+$6e constant TIMSK0 \ Timer/Counter0 Interrupt Mask
+ $f8 constant TIMSK0_Res \ Reserved
+ 6e $f8 bitmask: TIMSK0.Res \ Reserved
+ $4 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare
+ 6e $4 bitmask: TIMSK0.OCIE0B \ Timer/Counter0 Output Compare
+ $2 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare
+ 6e $2 bitmask: TIMSK0.OCIE0A \ Timer/Counter0 Output Compare
+ $1 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interr
+ 6e $1 bitmask: TIMSK0.TOIE0 \ Timer/Counter0 Overflow Interr
+$35 constant TIFR0 \ Timer/Counter0 Interrupt Flag
+ $f8 constant TIFR0_Res \ Reserved
+ 35 $f8 bitmask: TIFR0.Res \ Reserved
+ $4 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare
+ 35 $4 bitmask: TIFR0.OCF0B \ Timer/Counter0 Output Compare
+ $2 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare
+ 35 $2 bitmask: TIFR0.OCF0A \ Timer/Counter0 Output Compare
+ $1 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
+ 35 $1 bitmask: TIFR0.TOV0 \ Timer/Counter0 Overflow Flag
+$43 constant GTCCR \ General Timer/Counter Control
+ $80 constant GTCCR_TSM \ Timer/Counter Synchronization
+ 43 $80 bitmask: GTCCR.TSM \ Timer/Counter Synchronization
+ $7c constant GTCCR_Res \ Reserved
+ 43 $7c bitmask: GTCCR.Res \ Reserved
+ $2 constant GTCCR_PSRASY \ Prescaler Reset Timer/Counter2
+ 43 $2 bitmask: GTCCR.PSRASY \ Prescaler Reset Timer/Counter2
+ $1 constant GTCCR_PSRSYNC \ Prescaler Reset for Synchronou
+ 43 $1 bitmask: GTCCR.PSRSYNC \ Prescaler Reset for Synchronou
diff --git a/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/TIMER_COUNTER_1.frt b/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/TIMER_COUNTER_1.frt
new file mode 100644
index 0000000..1f9a23d
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/TIMER_COUNTER_1.frt
@@ -0,0 +1,68 @@
+\ Generated automatically for atmega1284rfr2
+\ #require bitnames.frt
+
+\ TIMER_COUNTER_1
+$80 constant TCCR1A \ Timer/Counter1 Control Registe
+ $c0 constant TCCR1A_COM1A \ Compare Output Mode for Channe
+ 80 $c0 bitmask: TCCR1A.COM1A \ Compare Output Mode for Channe
+ $30 constant TCCR1A_COM1B \ Compare Output Mode for Channe
+ 80 $30 bitmask: TCCR1A.COM1B \ Compare Output Mode for Channe
+ $c constant TCCR1A_COM1C \ Compare Output Mode for Channe
+ 80 $c bitmask: TCCR1A.COM1C \ Compare Output Mode for Channe
+ $3 constant TCCR1A_WGM1 \ Waveform Generation Mode
+ 80 $3 bitmask: TCCR1A.WGM1 \ Waveform Generation Mode
+$81 constant TCCR1B \ Timer/Counter1 Control Registe
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Cancelle
+ 81 $80 bitmask: TCCR1B.ICNC1 \ Input Capture 1 Noise Cancelle
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ 81 $40 bitmask: TCCR1B.ICES1 \ Input Capture 1 Edge Select
+ $20 constant TCCR1B_Res \ Reserved Bit
+ 81 $20 bitmask: TCCR1B.Res \ Reserved Bit
+ $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
+ 81 $18 bitmask: TCCR1B.WGM1 \ Waveform Generation Mode
+ $7 constant TCCR1B_CS1 \ Clock Select
+ 81 $7 bitmask: TCCR1B.CS1 \ Clock Select
+$82 constant TCCR1C \ Timer/Counter1 Control Registe
+ $80 constant TCCR1C_FOC1A \ Force Output Compare for Chann
+ 82 $80 bitmask: TCCR1C.FOC1A \ Force Output Compare for Chann
+ $40 constant TCCR1C_FOC1B \ Force Output Compare for Chann
+ 82 $40 bitmask: TCCR1C.FOC1B \ Force Output Compare for Chann
+ $20 constant TCCR1C_FOC1C \ Force Output Compare for Chann
+ 82 $20 bitmask: TCCR1C.FOC1C \ Force Output Compare for Chann
+ $1f constant TCCR1C_Res \ Reserved
+ 82 $1f bitmask: TCCR1C.Res \ Reserved
+$84 constant TCNT1 \ Timer/Counter1 Bytes
+$88 constant OCR1A \ Timer/Counter1 Output Compare
+$8a constant OCR1B \ Timer/Counter1 Output Compare
+$8c constant OCR1C \ Timer/Counter1 Output Compare
+$86 constant ICR1 \ Timer/Counter1 Input Capture R
+$6f constant TIMSK1 \ Timer/Counter1 Interrupt Mask
+ $c0 constant TIMSK1_Res \ Reserved Bit
+ 6f $c0 bitmask: TIMSK1.Res \ Reserved Bit
+ $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture I
+ 6f $20 bitmask: TIMSK1.ICIE1 \ Timer/Counter1 Input Capture I
+ $10 constant TIMSK1_Res \ Reserved Bit
+ 6f $10 bitmask: TIMSK1.Res \ Reserved Bit
+ $8 constant TIMSK1_OCIE1C \ Timer/Counter1 Output Compare
+ 6f $8 bitmask: TIMSK1.OCIE1C \ Timer/Counter1 Output Compare
+ $4 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare
+ 6f $4 bitmask: TIMSK1.OCIE1B \ Timer/Counter1 Output Compare
+ $2 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare
+ 6f $2 bitmask: TIMSK1.OCIE1A \ Timer/Counter1 Output Compare
+ $1 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interr
+ 6f $1 bitmask: TIMSK1.TOIE1 \ Timer/Counter1 Overflow Interr
+$36 constant TIFR1 \ Timer/Counter1 Interrupt Flag
+ $c0 constant TIFR1_Res \ Reserved Bit
+ 36 $c0 bitmask: TIFR1.Res \ Reserved Bit
+ $20 constant TIFR1_ICF1 \ Timer/Counter1 Input Capture F
+ 36 $20 bitmask: TIFR1.ICF1 \ Timer/Counter1 Input Capture F
+ $10 constant TIFR1_Res \ Reserved Bit
+ 36 $10 bitmask: TIFR1.Res \ Reserved Bit
+ $8 constant TIFR1_OCF1C \ Timer/Counter1 Output Compare
+ 36 $8 bitmask: TIFR1.OCF1C \ Timer/Counter1 Output Compare
+ $4 constant TIFR1_OCF1B \ Timer/Counter1 Output Compare
+ 36 $4 bitmask: TIFR1.OCF1B \ Timer/Counter1 Output Compare
+ $2 constant TIFR1_OCF1A \ Timer/Counter1 Output Compare
+ 36 $2 bitmask: TIFR1.OCF1A \ Timer/Counter1 Output Compare
+ $1 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
+ 36 $1 bitmask: TIFR1.TOV1 \ Timer/Counter1 Overflow Flag
diff --git a/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/TIMER_COUNTER_2.frt b/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/TIMER_COUNTER_2.frt
new file mode 100644
index 0000000..785cfdd
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/TIMER_COUNTER_2.frt
@@ -0,0 +1,67 @@
+\ Generated automatically for atmega1284rfr2
+\ #require bitnames.frt
+
+\ TIMER_COUNTER_2
+$70 constant TIMSK2 \ Timer/Counter Interrupt Mask r
+ $f8 constant TIMSK2_Res \ Reserved Bit
+ 70 $f8 bitmask: TIMSK2.Res \ Reserved Bit
+ $4 constant TIMSK2_OCIE2B \ Timer/Counter2 Output Compare
+ 70 $4 bitmask: TIMSK2.OCIE2B \ Timer/Counter2 Output Compare
+ $2 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare
+ 70 $2 bitmask: TIMSK2.OCIE2A \ Timer/Counter2 Output Compare
+ $1 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interr
+ 70 $1 bitmask: TIMSK2.TOIE2 \ Timer/Counter2 Overflow Interr
+$37 constant TIFR2 \ Timer/Counter Interrupt Flag R
+ $f8 constant TIFR2_Res \ Reserved Bit
+ 37 $f8 bitmask: TIFR2.Res \ Reserved Bit
+ $4 constant TIFR2_OCF2B \ Output Compare Flag 2 B
+ 37 $4 bitmask: TIFR2.OCF2B \ Output Compare Flag 2 B
+ $2 constant TIFR2_OCF2A \ Output Compare Flag 2 A
+ 37 $2 bitmask: TIFR2.OCF2A \ Output Compare Flag 2 A
+ $1 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
+ 37 $1 bitmask: TIFR2.TOV2 \ Timer/Counter2 Overflow Flag
+$b0 constant TCCR2A \ Timer/Counter2 Control Registe
+ $c0 constant TCCR2A_COM2A \ Compare Match Output A Mode
+ b0 $c0 bitmask: TCCR2A.COM2A \ Compare Match Output A Mode
+ $30 constant TCCR2A_COM2B \ Compare Match Output B Mode
+ b0 $30 bitmask: TCCR2A.COM2B \ Compare Match Output B Mode
+ $c constant TCCR2A_Res \ Reserved
+ b0 $c bitmask: TCCR2A.Res \ Reserved
+ $3 constant TCCR2A_WGM2 \ Waveform Generation Mode
+ b0 $3 bitmask: TCCR2A.WGM2 \ Waveform Generation Mode
+$b1 constant TCCR2B \ Timer/Counter2 Control Registe
+ $80 constant TCCR2B_FOC2A \ Force Output Compare A
+ b1 $80 bitmask: TCCR2B.FOC2A \ Force Output Compare A
+ $40 constant TCCR2B_FOC2B \ Force Output Compare B
+ b1 $40 bitmask: TCCR2B.FOC2B \ Force Output Compare B
+ $30 constant TCCR2B_Res \ Reserved
+ b1 $30 bitmask: TCCR2B.Res \ Reserved
+ $8 constant TCCR2B_WGM22 \ Waveform Generation Mode
+ b1 $8 bitmask: TCCR2B.WGM22 \ Waveform Generation Mode
+ $7 constant TCCR2B_CS2 \ Clock Select
+ b1 $7 bitmask: TCCR2B.CS2 \ Clock Select
+$b2 constant TCNT2 \ Timer/Counter2
+$b4 constant OCR2B \ Timer/Counter2 Output Compare
+$b3 constant OCR2A \ Timer/Counter2 Output Compare
+$b6 constant ASSR \ Asynchronous Status Register
+ $80 constant ASSR_EXCLKAMR \ Enable External Clock Input fo
+ b6 $80 bitmask: ASSR.EXCLKAMR \ Enable External Clock Input fo
+ $40 constant ASSR_EXCLK \ Enable External Clock Input
+ b6 $40 bitmask: ASSR.EXCLK \ Enable External Clock Input
+ $20 constant ASSR_AS2 \ Timer/Counter2 Asynchronous Mo
+ b6 $20 bitmask: ASSR.AS2 \ Timer/Counter2 Asynchronous Mo
+ $10 constant ASSR_TCN2UB \ Timer/Counter2 Update Busy
+ b6 $10 bitmask: ASSR.TCN2UB \ Timer/Counter2 Update Busy
+ $8 constant ASSR_OCR2AUB \ Timer/Counter2 Output Compare
+ b6 $8 bitmask: ASSR.OCR2AUB \ Timer/Counter2 Output Compare
+ $4 constant ASSR_OCR2BUB \ Timer/Counter2 Output Compare
+ b6 $4 bitmask: ASSR.OCR2BUB \ Timer/Counter2 Output Compare
+ $2 constant ASSR_TCR2AUB \ Timer/Counter2 Control Registe
+ b6 $2 bitmask: ASSR.TCR2AUB \ Timer/Counter2 Control Registe
+ $1 constant ASSR_TCR2BUB \ Timer/Counter2 Control Registe
+ b6 $1 bitmask: ASSR.TCR2BUB \ Timer/Counter2 Control Registe
+$43 constant GTCCR \ General Timer Counter Control
+ $80 constant GTCCR_TSM \ Timer/Counter Synchronization
+ 43 $80 bitmask: GTCCR.TSM \ Timer/Counter Synchronization
+ $2 constant GTCCR_PSRASY \ Prescaler Reset Timer/Counter2
+ 43 $2 bitmask: GTCCR.PSRASY \ Prescaler Reset Timer/Counter2
diff --git a/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/TIMER_COUNTER_3.frt b/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/TIMER_COUNTER_3.frt
new file mode 100644
index 0000000..3a545ee
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/TIMER_COUNTER_3.frt
@@ -0,0 +1,68 @@
+\ Generated automatically for atmega1284rfr2
+\ #require bitnames.frt
+
+\ TIMER_COUNTER_3
+$90 constant TCCR3A \ Timer/Counter3 Control Registe
+ $c0 constant TCCR3A_COM3A \ Compare Output Mode for Channe
+ 90 $c0 bitmask: TCCR3A.COM3A \ Compare Output Mode for Channe
+ $30 constant TCCR3A_COM3B \ Compare Output Mode for Channe
+ 90 $30 bitmask: TCCR3A.COM3B \ Compare Output Mode for Channe
+ $c constant TCCR3A_COM3C \ Compare Output Mode for Channe
+ 90 $c bitmask: TCCR3A.COM3C \ Compare Output Mode for Channe
+ $3 constant TCCR3A_WGM3 \ Waveform Generation Mode
+ 90 $3 bitmask: TCCR3A.WGM3 \ Waveform Generation Mode
+$91 constant TCCR3B \ Timer/Counter3 Control Registe
+ $80 constant TCCR3B_ICNC3 \ Input Capture 3 Noise Cancelle
+ 91 $80 bitmask: TCCR3B.ICNC3 \ Input Capture 3 Noise Cancelle
+ $40 constant TCCR3B_ICES3 \ Input Capture 3 Edge Select
+ 91 $40 bitmask: TCCR3B.ICES3 \ Input Capture 3 Edge Select
+ $20 constant TCCR3B_Res \ Reserved Bit
+ 91 $20 bitmask: TCCR3B.Res \ Reserved Bit
+ $18 constant TCCR3B_WGM3 \ Waveform Generation Mode
+ 91 $18 bitmask: TCCR3B.WGM3 \ Waveform Generation Mode
+ $7 constant TCCR3B_CS3 \ Clock Select
+ 91 $7 bitmask: TCCR3B.CS3 \ Clock Select
+$92 constant TCCR3C \ Timer/Counter3 Control Registe
+ $80 constant TCCR3C_FOC3A \ Force Output Compare for Chann
+ 92 $80 bitmask: TCCR3C.FOC3A \ Force Output Compare for Chann
+ $40 constant TCCR3C_FOC3B \ Force Output Compare for Chann
+ 92 $40 bitmask: TCCR3C.FOC3B \ Force Output Compare for Chann
+ $20 constant TCCR3C_FOC3C \ Force Output Compare for Chann
+ 92 $20 bitmask: TCCR3C.FOC3C \ Force Output Compare for Chann
+ $1f constant TCCR3C_Res \ Reserved
+ 92 $1f bitmask: TCCR3C.Res \ Reserved
+$94 constant TCNT3 \ Timer/Counter3 Bytes
+$98 constant OCR3A \ Timer/Counter3 Output Compare
+$9a constant OCR3B \ Timer/Counter3 Output Compare
+$9c constant OCR3C \ Timer/Counter3 Output Compare
+$96 constant ICR3 \ Timer/Counter3 Input Capture R
+$71 constant TIMSK3 \ Timer/Counter3 Interrupt Mask
+ $c0 constant TIMSK3_Res \ Reserved Bit
+ 71 $c0 bitmask: TIMSK3.Res \ Reserved Bit
+ $20 constant TIMSK3_ICIE3 \ Timer/Counter3 Input Capture I
+ 71 $20 bitmask: TIMSK3.ICIE3 \ Timer/Counter3 Input Capture I
+ $10 constant TIMSK3_Res \ Reserved Bit
+ 71 $10 bitmask: TIMSK3.Res \ Reserved Bit
+ $8 constant TIMSK3_OCIE3C \ Timer/Counter3 Output Compare
+ 71 $8 bitmask: TIMSK3.OCIE3C \ Timer/Counter3 Output Compare
+ $4 constant TIMSK3_OCIE3B \ Timer/Counter3 Output Compare
+ 71 $4 bitmask: TIMSK3.OCIE3B \ Timer/Counter3 Output Compare
+ $2 constant TIMSK3_OCIE3A \ Timer/Counter3 Output Compare
+ 71 $2 bitmask: TIMSK3.OCIE3A \ Timer/Counter3 Output Compare
+ $1 constant TIMSK3_TOIE3 \ Timer/Counter3 Overflow Interr
+ 71 $1 bitmask: TIMSK3.TOIE3 \ Timer/Counter3 Overflow Interr
+$38 constant TIFR3 \ Timer/Counter3 Interrupt Flag
+ $c0 constant TIFR3_Res \ Reserved Bit
+ 38 $c0 bitmask: TIFR3.Res \ Reserved Bit
+ $20 constant TIFR3_ICF3 \ Timer/Counter3 Input Capture F
+ 38 $20 bitmask: TIFR3.ICF3 \ Timer/Counter3 Input Capture F
+ $10 constant TIFR3_Res \ Reserved Bit
+ 38 $10 bitmask: TIFR3.Res \ Reserved Bit
+ $8 constant TIFR3_OCF3C \ Timer/Counter3 Output Compare
+ 38 $8 bitmask: TIFR3.OCF3C \ Timer/Counter3 Output Compare
+ $4 constant TIFR3_OCF3B \ Timer/Counter3 Output Compare
+ 38 $4 bitmask: TIFR3.OCF3B \ Timer/Counter3 Output Compare
+ $2 constant TIFR3_OCF3A \ Timer/Counter3 Output Compare
+ 38 $2 bitmask: TIFR3.OCF3A \ Timer/Counter3 Output Compare
+ $1 constant TIFR3_TOV3 \ Timer/Counter3 Overflow Flag
+ 38 $1 bitmask: TIFR3.TOV3 \ Timer/Counter3 Overflow Flag
diff --git a/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/TIMER_COUNTER_4.frt b/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/TIMER_COUNTER_4.frt
new file mode 100644
index 0000000..0ccc3bd
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/TIMER_COUNTER_4.frt
@@ -0,0 +1,68 @@
+\ Generated automatically for atmega1284rfr2
+\ #require bitnames.frt
+
+\ TIMER_COUNTER_4
+$a0 constant TCCR4A \ Timer/Counter4 Control Registe
+ $c0 constant TCCR4A_COM4A \ Compare Output Mode for Channe
+ a0 $c0 bitmask: TCCR4A.COM4A \ Compare Output Mode for Channe
+ $30 constant TCCR4A_COM4B \ Compare Output Mode for Channe
+ a0 $30 bitmask: TCCR4A.COM4B \ Compare Output Mode for Channe
+ $c constant TCCR4A_COM4C \ Compare Output Mode for Channe
+ a0 $c bitmask: TCCR4A.COM4C \ Compare Output Mode for Channe
+ $3 constant TCCR4A_WGM4 \ Waveform Generation Mode
+ a0 $3 bitmask: TCCR4A.WGM4 \ Waveform Generation Mode
+$a1 constant TCCR4B \ Timer/Counter4 Control Registe
+ $80 constant TCCR4B_ICNC4 \ Input Capture 4 Noise Cancelle
+ a1 $80 bitmask: TCCR4B.ICNC4 \ Input Capture 4 Noise Cancelle
+ $40 constant TCCR4B_ICES4 \ Input Capture 4 Edge Select
+ a1 $40 bitmask: TCCR4B.ICES4 \ Input Capture 4 Edge Select
+ $20 constant TCCR4B_Res \ Reserved Bit
+ a1 $20 bitmask: TCCR4B.Res \ Reserved Bit
+ $18 constant TCCR4B_WGM4 \ Waveform Generation Mode
+ a1 $18 bitmask: TCCR4B.WGM4 \ Waveform Generation Mode
+ $7 constant TCCR4B_CS4 \ Clock Select
+ a1 $7 bitmask: TCCR4B.CS4 \ Clock Select
+$a2 constant TCCR4C \ Timer/Counter4 Control Registe
+ $80 constant TCCR4C_FOC4A \ Force Output Compare for Chann
+ a2 $80 bitmask: TCCR4C.FOC4A \ Force Output Compare for Chann
+ $40 constant TCCR4C_FOC4B \ Force Output Compare for Chann
+ a2 $40 bitmask: TCCR4C.FOC4B \ Force Output Compare for Chann
+ $20 constant TCCR4C_FOC4C \ Force Output Compare for Chann
+ a2 $20 bitmask: TCCR4C.FOC4C \ Force Output Compare for Chann
+ $1f constant TCCR4C_Res \ Reserved
+ a2 $1f bitmask: TCCR4C.Res \ Reserved
+$a4 constant TCNT4 \ Timer/Counter4 Bytes
+$a8 constant OCR4A \ Timer/Counter4 Output Compare
+$aa constant OCR4B \ Timer/Counter4 Output Compare
+$ac constant OCR4C \ Timer/Counter4 Output Compare
+$a6 constant ICR4 \ Timer/Counter4 Input Capture R
+$72 constant TIMSK4 \ Timer/Counter4 Interrupt Mask
+ $c0 constant TIMSK4_Res \ Reserved Bit
+ 72 $c0 bitmask: TIMSK4.Res \ Reserved Bit
+ $20 constant TIMSK4_ICIE4 \ Timer/Counter4 Input Capture I
+ 72 $20 bitmask: TIMSK4.ICIE4 \ Timer/Counter4 Input Capture I
+ $10 constant TIMSK4_Res \ Reserved Bit
+ 72 $10 bitmask: TIMSK4.Res \ Reserved Bit
+ $8 constant TIMSK4_OCIE4C \ Timer/Counter4 Output Compare
+ 72 $8 bitmask: TIMSK4.OCIE4C \ Timer/Counter4 Output Compare
+ $4 constant TIMSK4_OCIE4B \ Timer/Counter4 Output Compare
+ 72 $4 bitmask: TIMSK4.OCIE4B \ Timer/Counter4 Output Compare
+ $2 constant TIMSK4_OCIE4A \ Timer/Counter4 Output Compare
+ 72 $2 bitmask: TIMSK4.OCIE4A \ Timer/Counter4 Output Compare
+ $1 constant TIMSK4_TOIE4 \ Timer/Counter4 Overflow Interr
+ 72 $1 bitmask: TIMSK4.TOIE4 \ Timer/Counter4 Overflow Interr
+$39 constant TIFR4 \ Timer/Counter4 Interrupt Flag
+ $c0 constant TIFR4_Res \ Reserved Bit
+ 39 $c0 bitmask: TIFR4.Res \ Reserved Bit
+ $20 constant TIFR4_ICF4 \ Timer/Counter4 Input Capture F
+ 39 $20 bitmask: TIFR4.ICF4 \ Timer/Counter4 Input Capture F
+ $10 constant TIFR4_Res \ Reserved Bit
+ 39 $10 bitmask: TIFR4.Res \ Reserved Bit
+ $8 constant TIFR4_OCF4C \ Timer/Counter4 Output Compare
+ 39 $8 bitmask: TIFR4.OCF4C \ Timer/Counter4 Output Compare
+ $4 constant TIFR4_OCF4B \ Timer/Counter4 Output Compare
+ 39 $4 bitmask: TIFR4.OCF4B \ Timer/Counter4 Output Compare
+ $2 constant TIFR4_OCF4A \ Timer/Counter4 Output Compare
+ 39 $2 bitmask: TIFR4.OCF4A \ Timer/Counter4 Output Compare
+ $1 constant TIFR4_TOV4 \ Timer/Counter4 Overflow Flag
+ 39 $1 bitmask: TIFR4.TOV4 \ Timer/Counter4 Overflow Flag
diff --git a/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/TIMER_COUNTER_5.frt b/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/TIMER_COUNTER_5.frt
new file mode 100644
index 0000000..b3b9e55
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/TIMER_COUNTER_5.frt
@@ -0,0 +1,68 @@
+\ Generated automatically for atmega1284rfr2
+\ #require bitnames.frt
+
+\ TIMER_COUNTER_5
+$120 constant TCCR5A \ Timer/Counter5 Control Registe
+ $c0 constant TCCR5A_COM5A \ Compare Output Mode for Channe
+ 120 $c0 bitmask: TCCR5A.COM5A \ Compare Output Mode for Channe
+ $30 constant TCCR5A_COM5B \ Compare Output Mode for Channe
+ 120 $30 bitmask: TCCR5A.COM5B \ Compare Output Mode for Channe
+ $c constant TCCR5A_COM5C \ Compare Output Mode for Channe
+ 120 $c bitmask: TCCR5A.COM5C \ Compare Output Mode for Channe
+ $3 constant TCCR5A_WGM5 \ Waveform Generation Mode
+ 120 $3 bitmask: TCCR5A.WGM5 \ Waveform Generation Mode
+$121 constant TCCR5B \ Timer/Counter5 Control Registe
+ $80 constant TCCR5B_ICNC5 \ Input Capture 5 Noise Cancelle
+ 121 $80 bitmask: TCCR5B.ICNC5 \ Input Capture 5 Noise Cancelle
+ $40 constant TCCR5B_ICES5 \ Input Capture 5 Edge Select
+ 121 $40 bitmask: TCCR5B.ICES5 \ Input Capture 5 Edge Select
+ $20 constant TCCR5B_Res \ Reserved Bit
+ 121 $20 bitmask: TCCR5B.Res \ Reserved Bit
+ $18 constant TCCR5B_WGM5 \ Waveform Generation Mode
+ 121 $18 bitmask: TCCR5B.WGM5 \ Waveform Generation Mode
+ $7 constant TCCR5B_CS5 \ Clock Select
+ 121 $7 bitmask: TCCR5B.CS5 \ Clock Select
+$122 constant TCCR5C \ Timer/Counter5 Control Registe
+ $80 constant TCCR5C_FOC5A \ Force Output Compare for Chann
+ 122 $80 bitmask: TCCR5C.FOC5A \ Force Output Compare for Chann
+ $40 constant TCCR5C_FOC5B \ Force Output Compare for Chann
+ 122 $40 bitmask: TCCR5C.FOC5B \ Force Output Compare for Chann
+ $20 constant TCCR5C_FOC5C \ Force Output Compare for Chann
+ 122 $20 bitmask: TCCR5C.FOC5C \ Force Output Compare for Chann
+ $1f constant TCCR5C_Res \ Reserved
+ 122 $1f bitmask: TCCR5C.Res \ Reserved
+$124 constant TCNT5 \ Timer/Counter5 Bytes
+$128 constant OCR5A \ Timer/Counter5 Output Compare
+$12a constant OCR5B \ Timer/Counter5 Output Compare
+$12c constant OCR5C \ Timer/Counter5 Output Compare
+$126 constant ICR5 \ Timer/Counter5 Input Capture R
+$73 constant TIMSK5 \ Timer/Counter5 Interrupt Mask
+ $c0 constant TIMSK5_Res \ Reserved Bit
+ 73 $c0 bitmask: TIMSK5.Res \ Reserved Bit
+ $20 constant TIMSK5_ICIE5 \ Timer/Counter5 Input Capture I
+ 73 $20 bitmask: TIMSK5.ICIE5 \ Timer/Counter5 Input Capture I
+ $10 constant TIMSK5_Res \ Reserved Bit
+ 73 $10 bitmask: TIMSK5.Res \ Reserved Bit
+ $8 constant TIMSK5_OCIE5C \ Timer/Counter5 Output Compare
+ 73 $8 bitmask: TIMSK5.OCIE5C \ Timer/Counter5 Output Compare
+ $4 constant TIMSK5_OCIE5B \ Timer/Counter5 Output Compare
+ 73 $4 bitmask: TIMSK5.OCIE5B \ Timer/Counter5 Output Compare
+ $2 constant TIMSK5_OCIE5A \ Timer/Counter5 Output Compare
+ 73 $2 bitmask: TIMSK5.OCIE5A \ Timer/Counter5 Output Compare
+ $1 constant TIMSK5_TOIE5 \ Timer/Counter5 Overflow Interr
+ 73 $1 bitmask: TIMSK5.TOIE5 \ Timer/Counter5 Overflow Interr
+$3a constant TIFR5 \ Timer/Counter5 Interrupt Flag
+ $c0 constant TIFR5_Res \ Reserved Bit
+ 3a $c0 bitmask: TIFR5.Res \ Reserved Bit
+ $20 constant TIFR5_ICF5 \ Timer/Counter5 Input Capture F
+ 3a $20 bitmask: TIFR5.ICF5 \ Timer/Counter5 Input Capture F
+ $10 constant TIFR5_Res \ Reserved Bit
+ 3a $10 bitmask: TIFR5.Res \ Reserved Bit
+ $8 constant TIFR5_OCF5C \ Timer/Counter5 Output Compare
+ 3a $8 bitmask: TIFR5.OCF5C \ Timer/Counter5 Output Compare
+ $4 constant TIFR5_OCF5B \ Timer/Counter5 Output Compare
+ 3a $4 bitmask: TIFR5.OCF5B \ Timer/Counter5 Output Compare
+ $2 constant TIFR5_OCF5A \ Timer/Counter5 Output Compare
+ 3a $2 bitmask: TIFR5.OCF5A \ Timer/Counter5 Output Compare
+ $1 constant TIFR5_TOV5 \ Timer/Counter5 Overflow Flag
+ 3a $1 bitmask: TIFR5.TOV5 \ Timer/Counter5 Overflow Flag
diff --git a/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/TRX24.frt b/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/TRX24.frt
new file mode 100644
index 0000000..12d310a
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/TRX24.frt
@@ -0,0 +1,495 @@
+\ Generated automatically for atmega1284rfr2
+\ #require bitnames.frt
+
+\ TRX24
+$138 constant PARCR \ Power Amplifier Ramp up/down C
+ $e0 constant PARCR_PALTD \ ext. PA Ramp Down Lead Time
+ 138 $e0 bitmask: PARCR.PALTD \ ext. PA Ramp Down Lead Time
+ $1c constant PARCR_PALTU \ ext. PA Ramp Up Lead Time
+ 138 $1c bitmask: PARCR.PALTU \ ext. PA Ramp Up Lead Time
+ $2 constant PARCR_PARDFI \ Power Amplifier Ramp Down Freq
+ 138 $2 bitmask: PARCR.PARDFI \ Power Amplifier Ramp Down Freq
+ $1 constant PARCR_PARUFI \ Power Amplifier Ramp Up Freque
+ 138 $1 bitmask: PARCR.PARUFI \ Power Amplifier Ramp Up Freque
+$10e constant MAFSA0L \ Transceiver MAC Short Address
+ $ff constant MAFSA0L_MAFSA0L \ MAC Short Address low Byte for
+ 10e $ff bitmask: MAFSA0L.MAFSA0L \ MAC Short Address low Byte for
+$10f constant MAFSA0H \ Transceiver MAC Short Address
+ $ff constant MAFSA0H_MAFSA0H \ MAC Short Address high Byte fo
+ 10f $ff bitmask: MAFSA0H.MAFSA0H \ MAC Short Address high Byte fo
+$110 constant MAFPA0L \ Transceiver Personal Area Netw
+ $ff constant MAFPA0L_MAFPA0L \ MAC Personal Area Network ID l
+ 110 $ff bitmask: MAFPA0L.MAFPA0L \ MAC Personal Area Network ID l
+$111 constant MAFPA0H \ Transceiver Personal Area Netw
+ $ff constant MAFPA0H_MAFPA0H \ MAC Personal Area Network ID h
+ 111 $ff bitmask: MAFPA0H.MAFPA0H \ MAC Personal Area Network ID h
+$112 constant MAFSA1L \ Transceiver MAC Short Address
+ $ff constant MAFSA1L_MAFSA1L \ MAC Short Address low Byte for
+ 112 $ff bitmask: MAFSA1L.MAFSA1L \ MAC Short Address low Byte for
+$113 constant MAFSA1H \ Transceiver MAC Short Address
+ $ff constant MAFSA1H_MAFSA1H \ MAC Short Address high Byte fo
+ 113 $ff bitmask: MAFSA1H.MAFSA1H \ MAC Short Address high Byte fo
+$114 constant MAFPA1L \ Transceiver Personal Area Netw
+ $ff constant MAFPA1L_MAFPA1L \ MAC Personal Area Network ID l
+ 114 $ff bitmask: MAFPA1L.MAFPA1L \ MAC Personal Area Network ID l
+$115 constant MAFPA1H \ Transceiver Personal Area Netw
+ $ff constant MAFPA1H_MAFPA1H \ MAC Personal Area Network ID h
+ 115 $ff bitmask: MAFPA1H.MAFPA1H \ MAC Personal Area Network ID h
+$116 constant MAFSA2L \ Transceiver MAC Short Address
+ $ff constant MAFSA2L_MAFSA2L \ MAC Short Address low Byte for
+ 116 $ff bitmask: MAFSA2L.MAFSA2L \ MAC Short Address low Byte for
+$117 constant MAFSA2H \ Transceiver MAC Short Address
+ $ff constant MAFSA2H_MAFSA2H \ MAC Short Address high Byte fo
+ 117 $ff bitmask: MAFSA2H.MAFSA2H \ MAC Short Address high Byte fo
+$118 constant MAFPA2L \ Transceiver Personal Area Netw
+ $ff constant MAFPA2L_MAFPA2L \ MAC Personal Area Network ID l
+ 118 $ff bitmask: MAFPA2L.MAFPA2L \ MAC Personal Area Network ID l
+$119 constant MAFPA2H \ Transceiver Personal Area Netw
+ $ff constant MAFPA2H_MAFPA2H \ MAC Personal Area Network ID h
+ 119 $ff bitmask: MAFPA2H.MAFPA2H \ MAC Personal Area Network ID h
+$11a constant MAFSA3L \ Transceiver MAC Short Address
+ $ff constant MAFSA3L_MAFSA3L \ MAC Short Address low Byte for
+ 11a $ff bitmask: MAFSA3L.MAFSA3L \ MAC Short Address low Byte for
+$11b constant MAFSA3H \ Transceiver MAC Short Address
+ $ff constant MAFSA3H_MAFSA3H \ MAC Short Address high Byte fo
+ 11b $ff bitmask: MAFSA3H.MAFSA3H \ MAC Short Address high Byte fo
+$11c constant MAFPA3L \ Transceiver Personal Area Netw
+ $ff constant MAFPA3L_MAFPA3L \ MAC Personal Area Network ID l
+ 11c $ff bitmask: MAFPA3L.MAFPA3L \ MAC Personal Area Network ID l
+$11d constant MAFPA3H \ Transceiver Personal Area Netw
+ $ff constant MAFPA3H_MAFPA3H \ MAC Personal Area Network ID h
+ 11d $ff bitmask: MAFPA3H.MAFPA3H \ MAC Personal Area Network ID h
+$10c constant MAFCR0 \ Multiple Address Filter Config
+ $f0 constant MAFCR0_Res \ Reserved Bit
+ 10c $f0 bitmask: MAFCR0.Res \ Reserved Bit
+ $8 constant MAFCR0_MAF3EN \ Multiple Address Filter 3 Enab
+ 10c $8 bitmask: MAFCR0.MAF3EN \ Multiple Address Filter 3 Enab
+ $4 constant MAFCR0_MAF2EN \ Multiple Address Filter 2 Enab
+ 10c $4 bitmask: MAFCR0.MAF2EN \ Multiple Address Filter 2 Enab
+ $2 constant MAFCR0_MAF1EN \ Multiple Address Filter 1 Enab
+ 10c $2 bitmask: MAFCR0.MAF1EN \ Multiple Address Filter 1 Enab
+ $1 constant MAFCR0_MAF0EN \ Multiple Address Filter 0 Enab
+ 10c $1 bitmask: MAFCR0.MAF0EN \ Multiple Address Filter 0 Enab
+$10d constant MAFCR1 \ Multiple Address Filter Config
+ $80 constant MAFCR1_AACK_3_SET_PD \ Set Data Pending bit for addre
+ 10d $80 bitmask: MAFCR1.AACK_3_SET_PD \ Set Data Pending bit for addre
+ $40 constant MAFCR1_AACK_3_I_AM_COORD \ Enable PAN Coordinator mode fo
+ 10d $40 bitmask: MAFCR1.AACK_3_I_AM_COORD \ Enable PAN Coordinator mode fo
+ $20 constant MAFCR1_AACK_2_SET_PD \ Set Data Pending bit for addre
+ 10d $20 bitmask: MAFCR1.AACK_2_SET_PD \ Set Data Pending bit for addre
+ $10 constant MAFCR1_AACK_2_I_AM_COORD \ Enable PAN Coordinator mode fo
+ 10d $10 bitmask: MAFCR1.AACK_2_I_AM_COORD \ Enable PAN Coordinator mode fo
+ $8 constant MAFCR1_AACK_1_SET_PD \ Set Data Pending bit for addre
+ 10d $8 bitmask: MAFCR1.AACK_1_SET_PD \ Set Data Pending bit for addre
+ $4 constant MAFCR1_AACK_1_I_AM_COORD \ Enable PAN Coordinator mode fo
+ 10d $4 bitmask: MAFCR1.AACK_1_I_AM_COORD \ Enable PAN Coordinator mode fo
+ $2 constant MAFCR1_AACK_0_SET_PD \ Set Data Pending bit for addre
+ 10d $2 bitmask: MAFCR1.AACK_0_SET_PD \ Set Data Pending bit for addre
+ $1 constant MAFCR1_AACK_0_I_AM_COORD \ Enable PAN Coordinator mode fo
+ 10d $1 bitmask: MAFCR1.AACK_0_I_AM_COORD \ Enable PAN Coordinator mode fo
+$13c constant AES_CTRL \ AES Control Register
+ $80 constant AES_CTRL_AES_REQUEST \ Request AES Operation.
+ 13c $80 bitmask: AES_CTRL.AES_REQUEST \ Request AES Operation.
+ $40 constant AES_CTRL_Res \ Reserved Bit
+ 13c $40 bitmask: AES_CTRL.Res \ Reserved Bit
+ $20 constant AES_CTRL_AES_MODE \ Set AES Operation Mode
+ 13c $20 bitmask: AES_CTRL.AES_MODE \ Set AES Operation Mode
+ $10 constant AES_CTRL_Res \ Reserved Bit
+ 13c $10 bitmask: AES_CTRL.Res \ Reserved Bit
+ $8 constant AES_CTRL_AES_DIR \ Set AES Operation Direction
+ 13c $8 bitmask: AES_CTRL.AES_DIR \ Set AES Operation Direction
+ $4 constant AES_CTRL_AES_IM \ AES Interrupt Enable
+ 13c $4 bitmask: AES_CTRL.AES_IM \ AES Interrupt Enable
+ $3 constant AES_CTRL_Res \ Reserved Bit
+ 13c $3 bitmask: AES_CTRL.Res \ Reserved Bit
+$13d constant AES_STATUS \ AES Status Register
+ $80 constant AES_STATUS_AES_ER \ AES Operation Finished with Er
+ 13d $80 bitmask: AES_STATUS.AES_ER \ AES Operation Finished with Er
+ $7e constant AES_STATUS_Res \ Reserved
+ 13d $7e bitmask: AES_STATUS.Res \ Reserved
+ $1 constant AES_STATUS_AES_DONE \ AES Operation Finished with Su
+ 13d $1 bitmask: AES_STATUS.AES_DONE \ AES Operation Finished with Su
+$13e constant AES_STATE \ AES Plain and Cipher Text Buff
+ $ff constant AES_STATE_AES_STATE \ AES Plain and Cipher Text Buff
+ 13e $ff bitmask: AES_STATE.AES_STATE \ AES Plain and Cipher Text Buff
+$13f constant AES_KEY \ AES Encryption and Decryption
+ $ff constant AES_KEY_AES_KEY \ AES Encryption/Decryption Key
+ 13f $ff bitmask: AES_KEY.AES_KEY \ AES Encryption/Decryption Key
+$141 constant TRX_STATUS \ Transceiver Status Register
+ $80 constant TRX_STATUS_CCA_DONE \ CCA Algorithm Status
+ 141 $80 bitmask: TRX_STATUS.CCA_DONE \ CCA Algorithm Status
+ $40 constant TRX_STATUS_CCA_STATUS \ CCA Status Result
+ 141 $40 bitmask: TRX_STATUS.CCA_STATUS \ CCA Status Result
+ $20 constant TRX_STATUS_TST_STATUS \ Test mode status
+ 141 $20 bitmask: TRX_STATUS.TST_STATUS \ Test mode status
+ $1f constant TRX_STATUS_TRX_STATUS \ Transceiver Main Status
+ 141 $1f bitmask: TRX_STATUS.TRX_STATUS \ Transceiver Main Status
+$142 constant TRX_STATE \ Transceiver State Control Regi
+ $e0 constant TRX_STATE_TRAC_STATUS \ Transaction Status
+ 142 $e0 bitmask: TRX_STATE.TRAC_STATUS \ Transaction Status
+ $1f constant TRX_STATE_TRX_CMD \ State Control Command
+ 142 $1f bitmask: TRX_STATE.TRX_CMD \ State Control Command
+$143 constant TRX_CTRL_0 \ Reserved
+ $80 constant TRX_CTRL_0_Res7 \ Reserved
+ 143 $80 bitmask: TRX_CTRL_0.Res7 \ Reserved
+ $40 constant TRX_CTRL_0_PMU_EN \ Enable Phase Measurement Unit
+ 143 $40 bitmask: TRX_CTRL_0.PMU_EN \ Enable Phase Measurement Unit
+ $20 constant TRX_CTRL_0_PMU_START \ Start of Phase Measurement Uni
+ 143 $20 bitmask: TRX_CTRL_0.PMU_START \ Start of Phase Measurement Uni
+ $10 constant TRX_CTRL_0_PMU_IF_INV \ PMU IF Inverse
+ 143 $10 bitmask: TRX_CTRL_0.PMU_IF_INV \ PMU IF Inverse
+ $f constant TRX_CTRL_0_Res \ Reserved
+ 143 $f bitmask: TRX_CTRL_0.Res \ Reserved
+$144 constant TRX_CTRL_1 \ Transceiver Control Register 1
+ $80 constant TRX_CTRL_1_PA_EXT_EN \ External PA support enable
+ 144 $80 bitmask: TRX_CTRL_1.PA_EXT_EN \ External PA support enable
+ $40 constant TRX_CTRL_1_IRQ_2_EXT_EN \ Connect Frame Start IRQ to TC1
+ 144 $40 bitmask: TRX_CTRL_1.IRQ_2_EXT_EN \ Connect Frame Start IRQ to TC1
+ $20 constant TRX_CTRL_1_TX_AUTO_CRC_ON \ Enable Automatic CRC Calculati
+ 144 $20 bitmask: TRX_CTRL_1.TX_AUTO_CRC_ON \ Enable Automatic CRC Calculati
+ $10 constant TRX_CTRL_1_PLL_TX_FLT \ Enable PLL TX filter
+ 144 $10 bitmask: TRX_CTRL_1.PLL_TX_FLT \ Enable PLL TX filter
+ $f constant TRX_CTRL_1_Res \ Reserved
+ 144 $f bitmask: TRX_CTRL_1.Res \ Reserved
+$145 constant PHY_TX_PWR \ Transceiver Transmit Power Con
+ $f0 constant PHY_TX_PWR_Res \ Reserved
+ 145 $f0 bitmask: PHY_TX_PWR.Res \ Reserved
+ $f constant PHY_TX_PWR_TX_PWR \ Transmit Power Setting
+ 145 $f bitmask: PHY_TX_PWR.TX_PWR \ Transmit Power Setting
+$146 constant PHY_RSSI \ Receiver Signal Strength Indic
+ $80 constant PHY_RSSI_RX_CRC_VALID \ Received Frame CRC Status
+ 146 $80 bitmask: PHY_RSSI.RX_CRC_VALID \ Received Frame CRC Status
+ $60 constant PHY_RSSI_RND_VALUE \ Random Value
+ 146 $60 bitmask: PHY_RSSI.RND_VALUE \ Random Value
+ $1f constant PHY_RSSI_RSSI \ Receiver Signal Strength Indic
+ 146 $1f bitmask: PHY_RSSI.RSSI \ Receiver Signal Strength Indic
+$147 constant PHY_ED_LEVEL \ Transceiver Energy Detection L
+ $ff constant PHY_ED_LEVEL_ED_LEVEL \ Energy Detection Level
+ 147 $ff bitmask: PHY_ED_LEVEL.ED_LEVEL \ Energy Detection Level
+$148 constant PHY_CC_CCA \ Transceiver Clear Channel Asse
+ $80 constant PHY_CC_CCA_CCA_REQUEST \ Manual CCA Measurement Request
+ 148 $80 bitmask: PHY_CC_CCA.CCA_REQUEST \ Manual CCA Measurement Request
+ $60 constant PHY_CC_CCA_CCA_MODE \ Select CCA Measurement Mode
+ 148 $60 bitmask: PHY_CC_CCA.CCA_MODE \ Select CCA Measurement Mode
+ $1f constant PHY_CC_CCA_CHANNEL \ RX/TX Channel Selection
+ 148 $1f bitmask: PHY_CC_CCA.CHANNEL \ RX/TX Channel Selection
+$149 constant CCA_THRES \ Transceiver CCA Threshold Sett
+ $f0 constant CCA_THRES_CCA_CS_THRES \ CS Threshold Level for CCA Mea
+ 149 $f0 bitmask: CCA_THRES.CCA_CS_THRES \ CS Threshold Level for CCA Mea
+ $f constant CCA_THRES_CCA_ED_THRES \ ED Threshold Level for CCA Mea
+ 149 $f bitmask: CCA_THRES.CCA_ED_THRES \ ED Threshold Level for CCA Mea
+$14a constant RX_CTRL \ Transceiver Receive Control Re
+ $f constant RX_CTRL_PDT_THRES \ Receiver Sensitivity Control
+ 14a $f bitmask: RX_CTRL.PDT_THRES \ Receiver Sensitivity Control
+$14b constant SFD_VALUE \ Start of Frame Delimiter Value
+ $ff constant SFD_VALUE_SFD_VALUE \ Start of Frame Delimiter Value
+ 14b $ff bitmask: SFD_VALUE.SFD_VALUE \ Start of Frame Delimiter Value
+$14c constant TRX_CTRL_2 \ Transceiver Control Register 2
+ $80 constant TRX_CTRL_2_RX_SAFE_MODE \ RX Safe Mode
+ 14c $80 bitmask: TRX_CTRL_2.RX_SAFE_MODE \ RX Safe Mode
+ $7c constant TRX_CTRL_2_Res \ Reserved
+ 14c $7c bitmask: TRX_CTRL_2.Res \ Reserved
+ $3 constant TRX_CTRL_2_OQPSK_DATA_RATE \ Data Rate Selection
+ 14c $3 bitmask: TRX_CTRL_2.OQPSK_DATA_RATE \ Data Rate Selection
+$14d constant ANT_DIV \ Antenna Diversity Control Regi
+ $80 constant ANT_DIV_ANT_SEL \ Antenna Diversity Antenna Stat
+ 14d $80 bitmask: ANT_DIV.ANT_SEL \ Antenna Diversity Antenna Stat
+ $70 constant ANT_DIV_Res \ Reserved
+ 14d $70 bitmask: ANT_DIV.Res \ Reserved
+ $8 constant ANT_DIV_ANT_DIV_EN \ Enable Antenna Diversity
+ 14d $8 bitmask: ANT_DIV.ANT_DIV_EN \ Enable Antenna Diversity
+ $4 constant ANT_DIV_ANT_EXT_SW_EN \ Enable External Antenna Switch
+ 14d $4 bitmask: ANT_DIV.ANT_EXT_SW_EN \ Enable External Antenna Switch
+ $3 constant ANT_DIV_ANT_CTRL \ Static Antenna Diversity Switc
+ 14d $3 bitmask: ANT_DIV.ANT_CTRL \ Static Antenna Diversity Switc
+$14e constant IRQ_MASK \ Transceiver Interrupt Enable R
+ $80 constant IRQ_MASK_AWAKE_EN \ Awake Interrupt Enable
+ 14e $80 bitmask: IRQ_MASK.AWAKE_EN \ Awake Interrupt Enable
+ $40 constant IRQ_MASK_TX_END_EN \ TX_END Interrupt Enable
+ 14e $40 bitmask: IRQ_MASK.TX_END_EN \ TX_END Interrupt Enable
+ $20 constant IRQ_MASK_AMI_EN \ Address Match Interrupt Enable
+ 14e $20 bitmask: IRQ_MASK.AMI_EN \ Address Match Interrupt Enable
+ $10 constant IRQ_MASK_CCA_ED_DONE_EN \ End of ED Measurement Interrup
+ 14e $10 bitmask: IRQ_MASK.CCA_ED_DONE_EN \ End of ED Measurement Interrup
+ $8 constant IRQ_MASK_RX_END_EN \ RX_END Interrupt Enable
+ 14e $8 bitmask: IRQ_MASK.RX_END_EN \ RX_END Interrupt Enable
+ $4 constant IRQ_MASK_RX_START_EN \ RX_START Interrupt Enable
+ 14e $4 bitmask: IRQ_MASK.RX_START_EN \ RX_START Interrupt Enable
+ $2 constant IRQ_MASK_PLL_UNLOCK_EN \ PLL Unlock Interrupt Enable
+ 14e $2 bitmask: IRQ_MASK.PLL_UNLOCK_EN \ PLL Unlock Interrupt Enable
+ $1 constant IRQ_MASK_PLL_LOCK_EN \ PLL Lock Interrupt Enable
+ 14e $1 bitmask: IRQ_MASK.PLL_LOCK_EN \ PLL Lock Interrupt Enable
+$14f constant IRQ_STATUS \ Transceiver Interrupt Status R
+ $80 constant IRQ_STATUS_AWAKE \ Awake Interrupt Status
+ 14f $80 bitmask: IRQ_STATUS.AWAKE \ Awake Interrupt Status
+ $40 constant IRQ_STATUS_TX_END \ TX_END Interrupt Status
+ 14f $40 bitmask: IRQ_STATUS.TX_END \ TX_END Interrupt Status
+ $20 constant IRQ_STATUS_AMI \ Address Match Interrupt Status
+ 14f $20 bitmask: IRQ_STATUS.AMI \ Address Match Interrupt Status
+ $10 constant IRQ_STATUS_CCA_ED_DONE \ End of ED Measurement Interrup
+ 14f $10 bitmask: IRQ_STATUS.CCA_ED_DONE \ End of ED Measurement Interrup
+ $8 constant IRQ_STATUS_RX_END \ RX_END Interrupt Status
+ 14f $8 bitmask: IRQ_STATUS.RX_END \ RX_END Interrupt Status
+ $4 constant IRQ_STATUS_RX_START \ RX_START Interrupt Status
+ 14f $4 bitmask: IRQ_STATUS.RX_START \ RX_START Interrupt Status
+ $2 constant IRQ_STATUS_PLL_UNLOCK \ PLL Unlock Interrupt Status
+ 14f $2 bitmask: IRQ_STATUS.PLL_UNLOCK \ PLL Unlock Interrupt Status
+ $1 constant IRQ_STATUS_PLL_LOCK \ PLL Lock Interrupt Status
+ 14f $1 bitmask: IRQ_STATUS.PLL_LOCK \ PLL Lock Interrupt Status
+$be constant IRQ_MASK1 \ Transceiver Interrupt Enable R
+ $e0 constant IRQ_MASK1_Res \ Reserved Bit
+ be $e0 bitmask: IRQ_MASK1.Res \ Reserved Bit
+ $10 constant IRQ_MASK1_MAF_3_AMI_EN \ Address Match Interrupt enable
+ be $10 bitmask: IRQ_MASK1.MAF_3_AMI_EN \ Address Match Interrupt enable
+ $8 constant IRQ_MASK1_MAF_2_AMI_EN \ Address Match Interrupt enable
+ be $8 bitmask: IRQ_MASK1.MAF_2_AMI_EN \ Address Match Interrupt enable
+ $4 constant IRQ_MASK1_MAF_1_AMI_EN \ Address Match Interrupt enable
+ be $4 bitmask: IRQ_MASK1.MAF_1_AMI_EN \ Address Match Interrupt enable
+ $2 constant IRQ_MASK1_MAF_0_AMI_EN \ Address Match Interrupt enable
+ be $2 bitmask: IRQ_MASK1.MAF_0_AMI_EN \ Address Match Interrupt enable
+ $1 constant IRQ_MASK1_TX_START_EN \ Transmit Start Interrupt enabl
+ be $1 bitmask: IRQ_MASK1.TX_START_EN \ Transmit Start Interrupt enabl
+$bf constant IRQ_STATUS1 \ Transceiver Interrupt Status R
+ $e0 constant IRQ_STATUS1_Res \ Reserved Bit
+ bf $e0 bitmask: IRQ_STATUS1.Res \ Reserved Bit
+ $10 constant IRQ_STATUS1_MAF_3_AMI \ Address Match Interrupt Status
+ bf $10 bitmask: IRQ_STATUS1.MAF_3_AMI \ Address Match Interrupt Status
+ $8 constant IRQ_STATUS1_MAF_2_AMI \ Address Match Interrupt Status
+ bf $8 bitmask: IRQ_STATUS1.MAF_2_AMI \ Address Match Interrupt Status
+ $4 constant IRQ_STATUS1_MAF_1_AMI \ Address Match Interrupt Status
+ bf $4 bitmask: IRQ_STATUS1.MAF_1_AMI \ Address Match Interrupt Status
+ $2 constant IRQ_STATUS1_MAF_0_AMI \ Address Match Interrupt Status
+ bf $2 bitmask: IRQ_STATUS1.MAF_0_AMI \ Address Match Interrupt Status
+ $1 constant IRQ_STATUS1_TX_START \ Transmit Start Interrupt Statu
+ bf $1 bitmask: IRQ_STATUS1.TX_START \ Transmit Start Interrupt Statu
+$150 constant VREG_CTRL \ Voltage Regulator Control and
+ $80 constant VREG_CTRL_AVREG_EXT \ Use External AVDD Regulator
+ 150 $80 bitmask: VREG_CTRL.AVREG_EXT \ Use External AVDD Regulator
+ $40 constant VREG_CTRL_AVDD_OK \ AVDD Supply Voltage Valid
+ 150 $40 bitmask: VREG_CTRL.AVDD_OK \ AVDD Supply Voltage Valid
+ $8 constant VREG_CTRL_DVREG_EXT \ Use External DVDD Regulator
+ 150 $8 bitmask: VREG_CTRL.DVREG_EXT \ Use External DVDD Regulator
+ $4 constant VREG_CTRL_DVDD_OK \ DVDD Supply Voltage Valid
+ 150 $4 bitmask: VREG_CTRL.DVDD_OK \ DVDD Supply Voltage Valid
+$151 constant BATMON \ Battery Monitor Control and St
+ $80 constant BATMON_BAT_LOW \ Battery Monitor Interrupt Stat
+ 151 $80 bitmask: BATMON.BAT_LOW \ Battery Monitor Interrupt Stat
+ $40 constant BATMON_BAT_LOW_EN \ Battery Monitor Interrupt Enab
+ 151 $40 bitmask: BATMON.BAT_LOW_EN \ Battery Monitor Interrupt Enab
+ $20 constant BATMON_BATMON_OK \ Battery Monitor Status
+ 151 $20 bitmask: BATMON.BATMON_OK \ Battery Monitor Status
+ $10 constant BATMON_BATMON_HR \ Battery Monitor Voltage Range
+ 151 $10 bitmask: BATMON.BATMON_HR \ Battery Monitor Voltage Range
+ $f constant BATMON_BATMON_VTH \ Battery Monitor Threshold Volt
+ 151 $f bitmask: BATMON.BATMON_VTH \ Battery Monitor Threshold Volt
+$152 constant XOSC_CTRL \ Crystal Oscillator Control Reg
+ $f0 constant XOSC_CTRL_XTAL_MODE \ Crystal Oscillator Operating M
+ 152 $f0 bitmask: XOSC_CTRL.XTAL_MODE \ Crystal Oscillator Operating M
+ $f constant XOSC_CTRL_XTAL_TRIM \ Crystal Oscillator Load Capaci
+ 152 $f bitmask: XOSC_CTRL.XTAL_TRIM \ Crystal Oscillator Load Capaci
+$153 constant CC_CTRL_0 \ Channel Control Register 0
+ $ff constant CC_CTRL_0_CC_NUMBER \ Channel Number
+ 153 $ff bitmask: CC_CTRL_0.CC_NUMBER \ Channel Number
+$154 constant CC_CTRL_1 \ Channel Control Register 1
+ $f constant CC_CTRL_1_CC_BAND \ Channel Band
+ 154 $f bitmask: CC_CTRL_1.CC_BAND \ Channel Band
+$155 constant RX_SYN \ Transceiver Receiver Sensitivi
+ $80 constant RX_SYN_RX_PDT_DIS \ Prevent Frame Reception
+ 155 $80 bitmask: RX_SYN.RX_PDT_DIS \ Prevent Frame Reception
+ $40 constant RX_SYN_RX_OVERRIDE \ Receiver Override Function
+ 155 $40 bitmask: RX_SYN.RX_OVERRIDE \ Receiver Override Function
+ $30 constant RX_SYN_Res \ Reserved
+ 155 $30 bitmask: RX_SYN.Res \ Reserved
+ $f constant RX_SYN_RX_PDT_LEVEL \ Reduce Receiver Sensitivity
+ 155 $f bitmask: RX_SYN.RX_PDT_LEVEL \ Reduce Receiver Sensitivity
+$156 constant TRX_RPC \ Transceiver Reduced Power Cons
+ $c0 constant TRX_RPC_RX_RPC_CTRL \ Smart Receiving Mode Timing
+ 156 $c0 bitmask: TRX_RPC.RX_RPC_CTRL \ Smart Receiving Mode Timing
+ $20 constant TRX_RPC_RX_RPC_EN \ Reciver Smart Receiving Mode E
+ 156 $20 bitmask: TRX_RPC.RX_RPC_EN \ Reciver Smart Receiving Mode E
+ $10 constant TRX_RPC_PDT_RPC_EN \ Smart Receiving Mode Reduced S
+ 156 $10 bitmask: TRX_RPC.PDT_RPC_EN \ Smart Receiving Mode Reduced S
+ $8 constant TRX_RPC_PLL_RPC_EN \ PLL Smart Receiving Mode Enabl
+ 156 $8 bitmask: TRX_RPC.PLL_RPC_EN \ PLL Smart Receiving Mode Enabl
+ $4 constant TRX_RPC_Res0 \ Reserved
+ 156 $4 bitmask: TRX_RPC.Res0 \ Reserved
+ $2 constant TRX_RPC_IPAN_RPC_EN \ Smart Receiving Mode IPAN Hand
+ 156 $2 bitmask: TRX_RPC.IPAN_RPC_EN \ Smart Receiving Mode IPAN Hand
+ $1 constant TRX_RPC_XAH_RPC_EN \ Smart Receiving in Extended Op
+ 156 $1 bitmask: TRX_RPC.XAH_RPC_EN \ Smart Receiving in Extended Op
+$157 constant XAH_CTRL_1 \ Transceiver Acknowledgment Fra
+ $c0 constant XAH_CTRL_1_Res \ Reserved Bit
+ 157 $c0 bitmask: XAH_CTRL_1.Res \ Reserved Bit
+ $20 constant XAH_CTRL_1_AACK_FLTR_RES_FT \ Filter Reserved Frames
+ 157 $20 bitmask: XAH_CTRL_1.AACK_FLTR_RES_FT \ Filter Reserved Frames
+ $10 constant XAH_CTRL_1_AACK_UPLD_RES_FT \ Process Reserved Frames
+ 157 $10 bitmask: XAH_CTRL_1.AACK_UPLD_RES_FT \ Process Reserved Frames
+ $8 constant XAH_CTRL_1_Res \ Reserved Bit
+ 157 $8 bitmask: XAH_CTRL_1.Res \ Reserved Bit
+ $4 constant XAH_CTRL_1_AACK_ACK_TIME \ Reduce Acknowledgment Time
+ 157 $4 bitmask: XAH_CTRL_1.AACK_ACK_TIME \ Reduce Acknowledgment Time
+ $2 constant XAH_CTRL_1_AACK_PROM_MODE \ Enable Promiscuous Mode
+ 157 $2 bitmask: XAH_CTRL_1.AACK_PROM_MODE \ Enable Promiscuous Mode
+ $1 constant XAH_CTRL_1_Res \ Reserved Bit
+ 157 $1 bitmask: XAH_CTRL_1.Res \ Reserved Bit
+$158 constant FTN_CTRL \ Transceiver Filter Tuning Cont
+ $80 constant FTN_CTRL_FTN_START \ Start Calibration Loop of Filt
+ 158 $80 bitmask: FTN_CTRL.FTN_START \ Start Calibration Loop of Filt
+$15a constant PLL_CF \ Transceiver Center Frequency C
+ $80 constant PLL_CF_PLL_CF_START \ Start Center Frequency Calibra
+ 15a $80 bitmask: PLL_CF.PLL_CF_START \ Start Center Frequency Calibra
+$15b constant PLL_DCU \ Transceiver Delay Cell Calibra
+ $80 constant PLL_DCU_PLL_DCU_START \ Start Delay Cell Calibration
+ 15b $80 bitmask: PLL_DCU.PLL_DCU_START \ Start Delay Cell Calibration
+$15c constant PART_NUM \ Device Identification Register
+ $ff constant PART_NUM_PART_NUM \ Part Number
+ 15c $ff bitmask: PART_NUM.PART_NUM \ Part Number
+$15d constant VERSION_NUM \ Device Identification Register
+ $ff constant VERSION_NUM_VERSION_NUM \ Version Number
+ 15d $ff bitmask: VERSION_NUM.VERSION_NUM \ Version Number
+$15e constant MAN_ID_0 \ Device Identification Register
+ $80 constant MAN_ID_0_MAN_ID_07 \ Manufacturer ID (Low Byte)
+ 15e $80 bitmask: MAN_ID_0.MAN_ID_07 \ Manufacturer ID (Low Byte)
+ $40 constant MAN_ID_0_MAN_ID_06 \ Manufacturer ID (Low Byte)
+ 15e $40 bitmask: MAN_ID_0.MAN_ID_06 \ Manufacturer ID (Low Byte)
+ $20 constant MAN_ID_0_MAN_ID_05 \ Manufacturer ID (Low Byte)
+ 15e $20 bitmask: MAN_ID_0.MAN_ID_05 \ Manufacturer ID (Low Byte)
+ $10 constant MAN_ID_0_MAN_ID_04 \ Manufacturer ID (Low Byte)
+ 15e $10 bitmask: MAN_ID_0.MAN_ID_04 \ Manufacturer ID (Low Byte)
+ $8 constant MAN_ID_0_MAN_ID_03 \ Manufacturer ID (Low Byte)
+ 15e $8 bitmask: MAN_ID_0.MAN_ID_03 \ Manufacturer ID (Low Byte)
+ $4 constant MAN_ID_0_MAN_ID_02 \ Manufacturer ID (Low Byte)
+ 15e $4 bitmask: MAN_ID_0.MAN_ID_02 \ Manufacturer ID (Low Byte)
+ $2 constant MAN_ID_0_MAN_ID_01 \ Manufacturer ID (Low Byte)
+ 15e $2 bitmask: MAN_ID_0.MAN_ID_01 \ Manufacturer ID (Low Byte)
+ $1 constant MAN_ID_0_MAN_ID_00 \ Manufacturer ID (Low Byte)
+ 15e $1 bitmask: MAN_ID_0.MAN_ID_00 \ Manufacturer ID (Low Byte)
+$15f constant MAN_ID_1 \ Device Identification Register
+ $ff constant MAN_ID_1_MAN_ID_ \ Manufacturer ID (High Byte)
+ 15f $ff bitmask: MAN_ID_1.MAN_ID_ \ Manufacturer ID (High Byte)
+$160 constant SHORT_ADDR_0 \ Transceiver MAC Short Address
+ $80 constant SHORT_ADDR_0_SHORT_ADDR_07 \ MAC Short Address
+ 160 $80 bitmask: SHORT_ADDR_0.SHORT_ADDR_07 \ MAC Short Address
+ $40 constant SHORT_ADDR_0_SHORT_ADDR_06 \ MAC Short Address
+ 160 $40 bitmask: SHORT_ADDR_0.SHORT_ADDR_06 \ MAC Short Address
+ $20 constant SHORT_ADDR_0_SHORT_ADDR_05 \ MAC Short Address
+ 160 $20 bitmask: SHORT_ADDR_0.SHORT_ADDR_05 \ MAC Short Address
+ $10 constant SHORT_ADDR_0_SHORT_ADDR_04 \ MAC Short Address
+ 160 $10 bitmask: SHORT_ADDR_0.SHORT_ADDR_04 \ MAC Short Address
+ $8 constant SHORT_ADDR_0_SHORT_ADDR_03 \ MAC Short Address
+ 160 $8 bitmask: SHORT_ADDR_0.SHORT_ADDR_03 \ MAC Short Address
+ $4 constant SHORT_ADDR_0_SHORT_ADDR_02 \ MAC Short Address
+ 160 $4 bitmask: SHORT_ADDR_0.SHORT_ADDR_02 \ MAC Short Address
+ $2 constant SHORT_ADDR_0_SHORT_ADDR_01 \ MAC Short Address
+ 160 $2 bitmask: SHORT_ADDR_0.SHORT_ADDR_01 \ MAC Short Address
+ $1 constant SHORT_ADDR_0_SHORT_ADDR_00 \ MAC Short Address
+ 160 $1 bitmask: SHORT_ADDR_0.SHORT_ADDR_00 \ MAC Short Address
+$161 constant SHORT_ADDR_1 \ Transceiver MAC Short Address
+ $ff constant SHORT_ADDR_1_SHORT_ADDR_ \ MAC Short Address
+ 161 $ff bitmask: SHORT_ADDR_1.SHORT_ADDR_ \ MAC Short Address
+$162 constant PAN_ID_0 \ Transceiver Personal Area Netw
+ $80 constant PAN_ID_0_PAN_ID_07 \ MAC Personal Area Network ID
+ 162 $80 bitmask: PAN_ID_0.PAN_ID_07 \ MAC Personal Area Network ID
+ $40 constant PAN_ID_0_PAN_ID_06 \ MAC Personal Area Network ID
+ 162 $40 bitmask: PAN_ID_0.PAN_ID_06 \ MAC Personal Area Network ID
+ $20 constant PAN_ID_0_PAN_ID_05 \ MAC Personal Area Network ID
+ 162 $20 bitmask: PAN_ID_0.PAN_ID_05 \ MAC Personal Area Network ID
+ $10 constant PAN_ID_0_PAN_ID_04 \ MAC Personal Area Network ID
+ 162 $10 bitmask: PAN_ID_0.PAN_ID_04 \ MAC Personal Area Network ID
+ $8 constant PAN_ID_0_PAN_ID_03 \ MAC Personal Area Network ID
+ 162 $8 bitmask: PAN_ID_0.PAN_ID_03 \ MAC Personal Area Network ID
+ $4 constant PAN_ID_0_PAN_ID_02 \ MAC Personal Area Network ID
+ 162 $4 bitmask: PAN_ID_0.PAN_ID_02 \ MAC Personal Area Network ID
+ $2 constant PAN_ID_0_PAN_ID_01 \ MAC Personal Area Network ID
+ 162 $2 bitmask: PAN_ID_0.PAN_ID_01 \ MAC Personal Area Network ID
+ $1 constant PAN_ID_0_PAN_ID_00 \ MAC Personal Area Network ID
+ 162 $1 bitmask: PAN_ID_0.PAN_ID_00 \ MAC Personal Area Network ID
+$163 constant PAN_ID_1 \ Transceiver Personal Area Netw
+ $ff constant PAN_ID_1_PAN_ID_ \ MAC Personal Area Network ID
+ 163 $ff bitmask: PAN_ID_1.PAN_ID_ \ MAC Personal Area Network ID
+$164 constant IEEE_ADDR_0 \ Transceiver MAC IEEE Address R
+ $80 constant IEEE_ADDR_0_IEEE_ADDR_07 \ MAC IEEE Address
+ 164 $80 bitmask: IEEE_ADDR_0.IEEE_ADDR_07 \ MAC IEEE Address
+ $40 constant IEEE_ADDR_0_IEEE_ADDR_06 \ MAC IEEE Address
+ 164 $40 bitmask: IEEE_ADDR_0.IEEE_ADDR_06 \ MAC IEEE Address
+ $20 constant IEEE_ADDR_0_IEEE_ADDR_05 \ MAC IEEE Address
+ 164 $20 bitmask: IEEE_ADDR_0.IEEE_ADDR_05 \ MAC IEEE Address
+ $10 constant IEEE_ADDR_0_IEEE_ADDR_04 \ MAC IEEE Address
+ 164 $10 bitmask: IEEE_ADDR_0.IEEE_ADDR_04 \ MAC IEEE Address
+ $8 constant IEEE_ADDR_0_IEEE_ADDR_03 \ MAC IEEE Address
+ 164 $8 bitmask: IEEE_ADDR_0.IEEE_ADDR_03 \ MAC IEEE Address
+ $4 constant IEEE_ADDR_0_IEEE_ADDR_02 \ MAC IEEE Address
+ 164 $4 bitmask: IEEE_ADDR_0.IEEE_ADDR_02 \ MAC IEEE Address
+ $2 constant IEEE_ADDR_0_IEEE_ADDR_01 \ MAC IEEE Address
+ 164 $2 bitmask: IEEE_ADDR_0.IEEE_ADDR_01 \ MAC IEEE Address
+ $1 constant IEEE_ADDR_0_IEEE_ADDR_00 \ MAC IEEE Address
+ 164 $1 bitmask: IEEE_ADDR_0.IEEE_ADDR_00 \ MAC IEEE Address
+$165 constant IEEE_ADDR_1 \ Transceiver MAC IEEE Address R
+ $ff constant IEEE_ADDR_1_IEEE_ADDR_ \ MAC IEEE Address
+ 165 $ff bitmask: IEEE_ADDR_1.IEEE_ADDR_ \ MAC IEEE Address
+$166 constant IEEE_ADDR_2 \ Transceiver MAC IEEE Address R
+ $ff constant IEEE_ADDR_2_IEEE_ADDR_ \ MAC IEEE Address
+ 166 $ff bitmask: IEEE_ADDR_2.IEEE_ADDR_ \ MAC IEEE Address
+$167 constant IEEE_ADDR_3 \ Transceiver MAC IEEE Address R
+ $ff constant IEEE_ADDR_3_IEEE_ADDR_ \ MAC IEEE Address
+ 167 $ff bitmask: IEEE_ADDR_3.IEEE_ADDR_ \ MAC IEEE Address
+$168 constant IEEE_ADDR_4 \ Transceiver MAC IEEE Address R
+ $ff constant IEEE_ADDR_4_IEEE_ADDR_ \ MAC IEEE Address
+ 168 $ff bitmask: IEEE_ADDR_4.IEEE_ADDR_ \ MAC IEEE Address
+$169 constant IEEE_ADDR_5 \ Transceiver MAC IEEE Address R
+ $ff constant IEEE_ADDR_5_IEEE_ADDR_ \ MAC IEEE Address
+ 169 $ff bitmask: IEEE_ADDR_5.IEEE_ADDR_ \ MAC IEEE Address
+$16a constant IEEE_ADDR_6 \ Transceiver MAC IEEE Address R
+ $ff constant IEEE_ADDR_6_IEEE_ADDR_ \ MAC IEEE Address
+ 16a $ff bitmask: IEEE_ADDR_6.IEEE_ADDR_ \ MAC IEEE Address
+$16b constant IEEE_ADDR_7 \ Transceiver MAC IEEE Address R
+ $ff constant IEEE_ADDR_7_IEEE_ADDR_ \ MAC IEEE Address
+ 16b $ff bitmask: IEEE_ADDR_7.IEEE_ADDR_ \ MAC IEEE Address
+$16c constant XAH_CTRL_0 \ Transceiver Extended Operating
+ $f0 constant XAH_CTRL_0_MAX_FRAME_RETRIES \ Maximum Number of Frame Re-tra
+ 16c $f0 bitmask: XAH_CTRL_0.MAX_FRAME_RETRIES \ Maximum Number of Frame Re-tra
+ $e constant XAH_CTRL_0_MAX_CSMA_RETRIES \ Maximum Number of CSMA-CA Proc
+ 16c $e bitmask: XAH_CTRL_0.MAX_CSMA_RETRIES \ Maximum Number of CSMA-CA Proc
+ $1 constant XAH_CTRL_0_SLOTTED_OPERATION \ Set Slotted Acknowledgment
+ 16c $1 bitmask: XAH_CTRL_0.SLOTTED_OPERATION \ Set Slotted Acknowledgment
+$16d constant CSMA_SEED_0 \ Transceiver CSMA-CA Random Num
+ $80 constant CSMA_SEED_0_CSMA_SEED_07 \ Seed Value for CSMA Random Num
+ 16d $80 bitmask: CSMA_SEED_0.CSMA_SEED_07 \ Seed Value for CSMA Random Num
+ $40 constant CSMA_SEED_0_CSMA_SEED_06 \ Seed Value for CSMA Random Num
+ 16d $40 bitmask: CSMA_SEED_0.CSMA_SEED_06 \ Seed Value for CSMA Random Num
+ $20 constant CSMA_SEED_0_CSMA_SEED_05 \ Seed Value for CSMA Random Num
+ 16d $20 bitmask: CSMA_SEED_0.CSMA_SEED_05 \ Seed Value for CSMA Random Num
+ $10 constant CSMA_SEED_0_CSMA_SEED_04 \ Seed Value for CSMA Random Num
+ 16d $10 bitmask: CSMA_SEED_0.CSMA_SEED_04 \ Seed Value for CSMA Random Num
+ $8 constant CSMA_SEED_0_CSMA_SEED_03 \ Seed Value for CSMA Random Num
+ 16d $8 bitmask: CSMA_SEED_0.CSMA_SEED_03 \ Seed Value for CSMA Random Num
+ $4 constant CSMA_SEED_0_CSMA_SEED_02 \ Seed Value for CSMA Random Num
+ 16d $4 bitmask: CSMA_SEED_0.CSMA_SEED_02 \ Seed Value for CSMA Random Num
+ $2 constant CSMA_SEED_0_CSMA_SEED_01 \ Seed Value for CSMA Random Num
+ 16d $2 bitmask: CSMA_SEED_0.CSMA_SEED_01 \ Seed Value for CSMA Random Num
+ $1 constant CSMA_SEED_0_CSMA_SEED_00 \ Seed Value for CSMA Random Num
+ 16d $1 bitmask: CSMA_SEED_0.CSMA_SEED_00 \ Seed Value for CSMA Random Num
+$16e constant CSMA_SEED_1 \ Transceiver Acknowledgment Fra
+ $c0 constant CSMA_SEED_1_AACK_FVN_MODE \ Acknowledgment Frame Filter Mo
+ 16e $c0 bitmask: CSMA_SEED_1.AACK_FVN_MODE \ Acknowledgment Frame Filter Mo
+ $20 constant CSMA_SEED_1_AACK_SET_PD \ Set Frame Pending Sub-field
+ 16e $20 bitmask: CSMA_SEED_1.AACK_SET_PD \ Set Frame Pending Sub-field
+ $10 constant CSMA_SEED_1_AACK_DIS_ACK \ Disable Acknowledgment Frame T
+ 16e $10 bitmask: CSMA_SEED_1.AACK_DIS_ACK \ Disable Acknowledgment Frame T
+ $8 constant CSMA_SEED_1_AACK_I_AM_COORD \ Set Personal Area Network Coor
+ 16e $8 bitmask: CSMA_SEED_1.AACK_I_AM_COORD \ Set Personal Area Network Coor
+ $7 constant CSMA_SEED_1_CSMA_SEED_1 \ Seed Value for CSMA Random Num
+ 16e $7 bitmask: CSMA_SEED_1.CSMA_SEED_1 \ Seed Value for CSMA Random Num
+$16f constant CSMA_BE \ Transceiver CSMA-CA Back-off E
+ $f0 constant CSMA_BE_MAX_BE \ Maximum Back-off Exponent
+ 16f $f0 bitmask: CSMA_BE.MAX_BE \ Maximum Back-off Exponent
+ $f constant CSMA_BE_MIN_BE \ Minimum Back-off Exponent
+ 16f $f bitmask: CSMA_BE.MIN_BE \ Minimum Back-off Exponent
+$176 constant TST_CTRL_DIGI \ Transceiver Digital Test Contr
+ $f constant TST_CTRL_DIGI_TST_CTRL_DIG \ Digital Test Controller Regist
+ 176 $f bitmask: TST_CTRL_DIGI.TST_CTRL_DIG \ Digital Test Controller Regist
+$17b constant TST_RX_LENGTH \ Transceiver Received Frame Len
+ $ff constant TST_RX_LENGTH_RX_LENGTH \ Received Frame Length
+ 17b $ff bitmask: TST_RX_LENGTH.RX_LENGTH \ Received Frame Length
+$180 constant TRXFBST \ Start of frame buffer
+$1ff constant TRXFBEND \ End of frame buffer
diff --git a/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/TWI.frt b/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/TWI.frt
new file mode 100644
index 0000000..bb68925
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/TWI.frt
@@ -0,0 +1,40 @@
+\ Generated automatically for atmega1284rfr2
+\ #require bitnames.frt
+
+\ TWI
+$bd constant TWAMR \ TWI (Slave) Address Mask Regis
+ $fe constant TWAMR_TWAM \ TWI Address Mask
+ bd $fe bitmask: TWAMR.TWAM \ TWI Address Mask
+ $1 constant TWAMR_Res \ Reserved Bit
+ bd $1 bitmask: TWAMR.Res \ Reserved Bit
+$b8 constant TWBR \ TWI Bit Rate Register
+$bc constant TWCR \ TWI Control Register
+ $80 constant TWCR_TWINT \ TWI Interrupt Flag
+ bc $80 bitmask: TWCR.TWINT \ TWI Interrupt Flag
+ $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
+ bc $40 bitmask: TWCR.TWEA \ TWI Enable Acknowledge Bit
+ $20 constant TWCR_TWSTA \ TWI START Condition Bit
+ bc $20 bitmask: TWCR.TWSTA \ TWI START Condition Bit
+ $10 constant TWCR_TWSTO \ TWI STOP Condition Bit
+ bc $10 bitmask: TWCR.TWSTO \ TWI STOP Condition Bit
+ $8 constant TWCR_TWWC \ TWI Write Collision Flag
+ bc $8 bitmask: TWCR.TWWC \ TWI Write Collision Flag
+ $4 constant TWCR_TWEN \ TWI Enable Bit
+ bc $4 bitmask: TWCR.TWEN \ TWI Enable Bit
+ $2 constant TWCR_Res \ Reserved Bit
+ bc $2 bitmask: TWCR.Res \ Reserved Bit
+ $1 constant TWCR_TWIE \ TWI Interrupt Enable
+ bc $1 bitmask: TWCR.TWIE \ TWI Interrupt Enable
+$b9 constant TWSR \ TWI Status Register
+ $f8 constant TWSR_TWS \ TWI Status
+ b9 $f8 bitmask: TWSR.TWS \ TWI Status
+ $4 constant TWSR_Res \ Reserved Bit
+ b9 $4 bitmask: TWSR.Res \ Reserved Bit
+ $3 constant TWSR_TWPS \ TWI Prescaler Bits
+ b9 $3 bitmask: TWSR.TWPS \ TWI Prescaler Bits
+$bb constant TWDR \ TWI Data Register
+$ba constant TWAR \ TWI (Slave) Address Register
+ $fe constant TWAR_TWA \ TWI (Slave) Address
+ ba $fe bitmask: TWAR.TWA \ TWI (Slave) Address
+ $1 constant TWAR_TWGCE \ TWI General Call Recognition E
+ ba $1 bitmask: TWAR.TWGCE \ TWI General Call Recognition E
diff --git a/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/USART0.frt b/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/USART0.frt
new file mode 100644
index 0000000..7532d38
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/USART0.frt
@@ -0,0 +1,51 @@
+\ Generated automatically for atmega1284rfr2
+\ #require bitnames.frt
+
+\ USART0
+$c6 constant UDR0 \ USART0 I/O Data Register
+$c0 constant UCSR0A \ USART0 Control and Status Regi
+ $80 constant UCSR0A_RXC0 \ USART Receive Complete
+ c0 $80 bitmask: UCSR0A.RXC0 \ USART Receive Complete
+ $40 constant UCSR0A_TXC0 \ USART Transmit Complete
+ c0 $40 bitmask: UCSR0A.TXC0 \ USART Transmit Complete
+ $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
+ c0 $20 bitmask: UCSR0A.UDRE0 \ USART Data Register Empty
+ $10 constant UCSR0A_FE0 \ Frame Error
+ c0 $10 bitmask: UCSR0A.FE0 \ Frame Error
+ $8 constant UCSR0A_DOR0 \ Data OverRun
+ c0 $8 bitmask: UCSR0A.DOR0 \ Data OverRun
+ $4 constant UCSR0A_UPE0 \ USART Parity Error
+ c0 $4 bitmask: UCSR0A.UPE0 \ USART Parity Error
+ $2 constant UCSR0A_U2X0 \ Double the USART Transmission
+ c0 $2 bitmask: UCSR0A.U2X0 \ Double the USART Transmission
+ $1 constant UCSR0A_MPCM0 \ Multi-processor Communication
+ c0 $1 bitmask: UCSR0A.MPCM0 \ Multi-processor Communication
+$c1 constant UCSR0B \ USART0 Control and Status Regi
+ $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
+ c1 $80 bitmask: UCSR0B.RXCIE0 \ RX Complete Interrupt Enable
+ $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
+ c1 $40 bitmask: UCSR0B.TXCIE0 \ TX Complete Interrupt Enable
+ $20 constant UCSR0B_UDRIE0 \ USART Data Register Empty Inte
+ c1 $20 bitmask: UCSR0B.UDRIE0 \ USART Data Register Empty Inte
+ $10 constant UCSR0B_RXEN0 \ Receiver Enable
+ c1 $10 bitmask: UCSR0B.RXEN0 \ Receiver Enable
+ $8 constant UCSR0B_TXEN0 \ Transmitter Enable
+ c1 $8 bitmask: UCSR0B.TXEN0 \ Transmitter Enable
+ $4 constant UCSR0B_UCSZ02 \ Character Size
+ c1 $4 bitmask: UCSR0B.UCSZ02 \ Character Size
+ $2 constant UCSR0B_RXB80 \ Receive Data Bit 8
+ c1 $2 bitmask: UCSR0B.RXB80 \ Receive Data Bit 8
+ $1 constant UCSR0B_TXB80 \ Transmit Data Bit 8
+ c1 $1 bitmask: UCSR0B.TXB80 \ Transmit Data Bit 8
+$c2 constant UCSR0C \ USART0 Control and Status Regi
+ $c0 constant UCSR0C_UMSEL0 \ USART Mode Select
+ c2 $c0 bitmask: UCSR0C.UMSEL0 \ USART Mode Select
+ $30 constant UCSR0C_UPM0 \ Parity Mode
+ c2 $30 bitmask: UCSR0C.UPM0 \ Parity Mode
+ $8 constant UCSR0C_USBS0 \ Stop Bit Select
+ c2 $8 bitmask: UCSR0C.USBS0 \ Stop Bit Select
+ $6 constant UCSR0C_UCSZ0 \ Character Size
+ c2 $6 bitmask: UCSR0C.UCSZ0 \ Character Size
+ $1 constant UCSR0C_UCPOL0 \ Clock Polarity
+ c2 $1 bitmask: UCSR0C.UCPOL0 \ Clock Polarity
+$c4 constant UBRR0 \ USART0 Baud Rate Register Byt
diff --git a/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/USART0_SPI.frt b/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/USART0_SPI.frt
new file mode 100644
index 0000000..cde1b1b
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/USART0_SPI.frt
@@ -0,0 +1,29 @@
+\ Generated automatically for atmega1284rfr2
+\ #require bitnames.frt
+
+\ USART0_SPI
+$c0 constant UCSR0A \ USART0 MSPIM Control and Statu
+ $80 constant UCSR0A_RXC0 \ USART Receive Complete
+ c0 $80 bitmask: UCSR0A.RXC0 \ USART Receive Complete
+ $40 constant UCSR0A_TXC0 \ USART Transmit Complete
+ c0 $40 bitmask: UCSR0A.TXC0 \ USART Transmit Complete
+ $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
+ c0 $20 bitmask: UCSR0A.UDRE0 \ USART Data Register Empty
+$c1 constant UCSR0B \ USART0 MSPIM Control and Statu
+ $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
+ c1 $80 bitmask: UCSR0B.RXCIE0 \ RX Complete Interrupt Enable
+ $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
+ c1 $40 bitmask: UCSR0B.TXCIE0 \ TX Complete Interrupt Enable
+ $20 constant UCSR0B_UDRIE0 \ USART Data Register Empty Inte
+ c1 $20 bitmask: UCSR0B.UDRIE0 \ USART Data Register Empty Inte
+ $10 constant UCSR0B_RXEN0 \ Receiver Enable
+ c1 $10 bitmask: UCSR0B.RXEN0 \ Receiver Enable
+ $8 constant UCSR0B_TXEN0 \ Transmitter Enable
+ c1 $8 bitmask: UCSR0B.TXEN0 \ Transmitter Enable
+$c2 constant UCSR0C \ USART0 MSPIM Control and Statu
+ $4 constant UCSR0C_UDORD0 \ Data Order
+ c2 $4 bitmask: UCSR0C.UDORD0 \ Data Order
+ $2 constant UCSR0C_UCPHA0 \ Clock Phase
+ c2 $2 bitmask: UCSR0C.UCPHA0 \ Clock Phase
+ $1 constant UCSR0C_UCPOL0 \ Clock Polarity
+ c2 $1 bitmask: UCSR0C.UCPOL0 \ Clock Polarity
diff --git a/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/USART1.frt b/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/USART1.frt
new file mode 100644
index 0000000..9656f84
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/USART1.frt
@@ -0,0 +1,51 @@
+\ Generated automatically for atmega1284rfr2
+\ #require bitnames.frt
+
+\ USART1
+$ce constant UDR1 \ USART1 I/O Data Register
+$c8 constant UCSR1A \ USART1 Control and Status Regi
+ $80 constant UCSR1A_RXC1 \ USART Receive Complete
+ c8 $80 bitmask: UCSR1A.RXC1 \ USART Receive Complete
+ $40 constant UCSR1A_TXC1 \ USART Transmit Complete
+ c8 $40 bitmask: UCSR1A.TXC1 \ USART Transmit Complete
+ $20 constant UCSR1A_UDRE1 \ USART Data Register Empty
+ c8 $20 bitmask: UCSR1A.UDRE1 \ USART Data Register Empty
+ $10 constant UCSR1A_FE1 \ Frame Error
+ c8 $10 bitmask: UCSR1A.FE1 \ Frame Error
+ $8 constant UCSR1A_DOR1 \ Data OverRun
+ c8 $8 bitmask: UCSR1A.DOR1 \ Data OverRun
+ $4 constant UCSR1A_UPE1 \ USART Parity Error
+ c8 $4 bitmask: UCSR1A.UPE1 \ USART Parity Error
+ $2 constant UCSR1A_U2X1 \ Double the USART Transmission
+ c8 $2 bitmask: UCSR1A.U2X1 \ Double the USART Transmission
+ $1 constant UCSR1A_MPCM1 \ Multi-processor Communication
+ c8 $1 bitmask: UCSR1A.MPCM1 \ Multi-processor Communication
+$c9 constant UCSR1B \ USART1 Control and Status Regi
+ $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable
+ c9 $80 bitmask: UCSR1B.RXCIE1 \ RX Complete Interrupt Enable
+ $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable
+ c9 $40 bitmask: UCSR1B.TXCIE1 \ TX Complete Interrupt Enable
+ $20 constant UCSR1B_UDRIE1 \ USART Data Register Empty Inte
+ c9 $20 bitmask: UCSR1B.UDRIE1 \ USART Data Register Empty Inte
+ $10 constant UCSR1B_RXEN1 \ Receiver Enable
+ c9 $10 bitmask: UCSR1B.RXEN1 \ Receiver Enable
+ $8 constant UCSR1B_TXEN1 \ Transmitter Enable
+ c9 $8 bitmask: UCSR1B.TXEN1 \ Transmitter Enable
+ $4 constant UCSR1B_UCSZ12 \ Character Size
+ c9 $4 bitmask: UCSR1B.UCSZ12 \ Character Size
+ $2 constant UCSR1B_RXB81 \ Receive Data Bit 8
+ c9 $2 bitmask: UCSR1B.RXB81 \ Receive Data Bit 8
+ $1 constant UCSR1B_TXB81 \ Transmit Data Bit 8
+ c9 $1 bitmask: UCSR1B.TXB81 \ Transmit Data Bit 8
+$ca constant UCSR1C \ USART1 Control and Status Regi
+ $c0 constant UCSR1C_UMSEL1 \ USART Mode Select
+ ca $c0 bitmask: UCSR1C.UMSEL1 \ USART Mode Select
+ $30 constant UCSR1C_UPM1 \ Parity Mode
+ ca $30 bitmask: UCSR1C.UPM1 \ Parity Mode
+ $8 constant UCSR1C_USBS1 \ Stop Bit Select
+ ca $8 bitmask: UCSR1C.USBS1 \ Stop Bit Select
+ $6 constant UCSR1C_UCSZ1 \ Character Size
+ ca $6 bitmask: UCSR1C.UCSZ1 \ Character Size
+ $1 constant UCSR1C_UCPOL1 \ Clock Polarity
+ ca $1 bitmask: UCSR1C.UCPOL1 \ Clock Polarity
+$cc constant UBRR1 \ USART1 Baud Rate Register Byt
diff --git a/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/USART1_SPI.frt b/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/USART1_SPI.frt
new file mode 100644
index 0000000..701f21f
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/USART1_SPI.frt
@@ -0,0 +1,29 @@
+\ Generated automatically for atmega1284rfr2
+\ #require bitnames.frt
+
+\ USART1_SPI
+$c8 constant UCSR1A \ USART1 MSPIM Control and Statu
+ $80 constant UCSR1A_RXC1 \ USART Receive Complete
+ c8 $80 bitmask: UCSR1A.RXC1 \ USART Receive Complete
+ $40 constant UCSR1A_TXC1 \ USART Transmit Complete
+ c8 $40 bitmask: UCSR1A.TXC1 \ USART Transmit Complete
+ $20 constant UCSR1A_UDRE1 \ USART Data Register Empty
+ c8 $20 bitmask: UCSR1A.UDRE1 \ USART Data Register Empty
+$c9 constant UCSR1B \ USART1 MSPIM Control and Statu
+ $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable
+ c9 $80 bitmask: UCSR1B.RXCIE1 \ RX Complete Interrupt Enable
+ $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable
+ c9 $40 bitmask: UCSR1B.TXCIE1 \ TX Complete Interrupt Enable
+ $20 constant UCSR1B_UDRIE1 \ USART Data Register Empty Inte
+ c9 $20 bitmask: UCSR1B.UDRIE1 \ USART Data Register Empty Inte
+ $10 constant UCSR1B_RXEN1 \ Receiver Enable
+ c9 $10 bitmask: UCSR1B.RXEN1 \ Receiver Enable
+ $8 constant UCSR1B_TXEN1 \ Transmitter Enable
+ c9 $8 bitmask: UCSR1B.TXEN1 \ Transmitter Enable
+$ca constant UCSR1C \ USART1 MSPIM Control and Statu
+ $4 constant UCSR1C_UDORD1 \ Data Order
+ ca $4 bitmask: UCSR1C.UDORD1 \ Data Order
+ $2 constant UCSR1C_UCPHA1 \ Clock Phase
+ ca $2 bitmask: UCSR1C.UCPHA1 \ Clock Phase
+ $1 constant UCSR1C_UCPOL1 \ Clock Polarity
+ ca $1 bitmask: UCSR1C.UCPOL1 \ Clock Polarity
diff --git a/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/WATCHDOG.frt b/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/WATCHDOG.frt
new file mode 100644
index 0000000..ae1c311
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega1284rfr2/blocks/WATCHDOG.frt
@@ -0,0 +1,15 @@
+\ Generated automatically for atmega1284rfr2
+\ #require bitnames.frt
+
+\ WATCHDOG
+$60 constant WDTCSR \ Watchdog Timer Control Registe
+ $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Fla
+ 60 $80 bitmask: WDTCSR.WDIF \ Watchdog Timeout Interrupt Fla
+ $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Ena
+ 60 $40 bitmask: WDTCSR.WDIE \ Watchdog Timeout Interrupt Ena
+ $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
+ 60 $27 bitmask: WDTCSR.WDP \ Watchdog Timer Prescaler Bits
+ $10 constant WDTCSR_WDCE \ Watchdog Change Enable
+ 60 $10 bitmask: WDTCSR.WDCE \ Watchdog Change Enable
+ $8 constant WDTCSR_WDE \ Watch Dog Enable
+ 60 $8 bitmask: WDTCSR.WDE \ Watch Dog Enable
diff --git a/amforth-6.5/avr8/devices/atmega1284rfr2/device.asm b/amforth-6.5/avr8/devices/atmega1284rfr2/device.asm
new file mode 100644
index 0000000..49846c0
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega1284rfr2/device.asm
@@ -0,0 +1,166 @@
+; Generated Automatically
+
+.nolist
+ include "m1284RFR2def.inc"
+.list
+FLASHSTART = 0
+FLASHSIZE = 131072
+RAMEND = 16896
+IRAMSTART = 512
+IRAMSIZE = 16384
+EEPROMSIZE = 4096
+; Interrupt Vectors
+.overlap
+.org 2
+ rcall isr ; External Interrupt Request 0
+.org 4
+ rcall isr ; External Interrupt Request 1
+.org 6
+ rcall isr ; External Interrupt Request 2
+.org 8
+ rcall isr ; External Interrupt Request 3
+.org 10
+ rcall isr ; External Interrupt Request 4
+.org 12
+ rcall isr ; External Interrupt Request 5
+.org 14
+ rcall isr ; External Interrupt Request 6
+.org 16
+ rcall isr ; External Interrupt Request 7
+.org 18
+ rcall isr ; Pin Change Interrupt Request 0
+.org 20
+ rcall isr ; Pin Change Interrupt Request 1
+.org 22
+ rcall isr ; Pin Change Interrupt Request 2
+.org 24
+ rcall isr ; Watchdog Time-out Interrupt
+.org 26
+ rcall isr ; Timer/Counter2 Compare Match A
+.org 28
+ rcall isr ; Timer/Counter2 Compare Match B
+.org 30
+ rcall isr ; Timer/Counter2 Overflow
+.org 32
+ rcall isr ; Timer/Counter1 Capture Event
+.org 34
+ rcall isr ; Timer/Counter1 Compare Match A
+.org 36
+ rcall isr ; Timer/Counter1 Compare Match B
+.org 38
+ rcall isr ; Timer/Counter1 Compare Match C
+.org 40
+ rcall isr ; Timer/Counter1 Overflow
+.org 42
+ rcall isr ; Timer/Counter0 Compare Match A
+.org 44
+ rcall isr ; Timer/Counter0 Compare Match B
+.org 46
+ rcall isr ; Timer/Counter0 Overflow
+.org 48
+ rcall isr ; SPI Serial Transfer Complete
+.org 50
+ rcall isr ; USART0, Rx Complete
+.org 52
+ rcall isr ; USART0 Data register Empty
+.org 54
+ rcall isr ; USART0, Tx Complete
+.org 56
+ rcall isr ; Analog Comparator
+.org 58
+ rcall isr ; ADC Conversion Complete
+.org 60
+ rcall isr ; EEPROM Ready
+.org 62
+ rcall isr ; Timer/Counter3 Capture Event
+.org 64
+ rcall isr ; Timer/Counter3 Compare Match A
+.org 66
+ rcall isr ; Timer/Counter3 Compare Match B
+.org 68
+ rcall isr ; Timer/Counter3 Compare Match C
+.org 70
+ rcall isr ; Timer/Counter3 Overflow
+.org 72
+ rcall isr ; USART1, Rx Complete
+.org 74
+ rcall isr ; USART1 Data register Empty
+.org 76
+ rcall isr ; USART1, Tx Complete
+.org 78
+ rcall isr ; 2-wire Serial Interface
+.org 80
+ rcall isr ; Store Program Memory Read
+.org 82
+ rcall isr ; Timer/Counter4 Capture Event
+.org 84
+ rcall isr ; Timer/Counter4 Compare Match A
+.org 86
+ rcall isr ; Timer/Counter4 Compare Match B
+.org 88
+ rcall isr ; Timer/Counter4 Compare Match C
+.org 90
+ rcall isr ; Timer/Counter4 Overflow
+.org 92
+ rcall isr ; Timer/Counter5 Capture Event
+.org 94
+ rcall isr ; Timer/Counter5 Compare Match A
+.org 96
+ rcall isr ; Timer/Counter5 Compare Match B
+.org 98
+ rcall isr ; Timer/Counter5 Compare Match C
+.org 100
+ rcall isr ; Timer/Counter5 Overflow
+.org 102
+ rcall isr ; USART2, Rx Complete
+.org 104
+ rcall isr ; USART2 Data register Empty
+.org 106
+ rcall isr ; USART2, Tx Complete
+.org 108
+ rcall isr ; USART3, Rx Complete
+.org 110
+ rcall isr ; USART3 Data register Empty
+.org 112
+ rcall isr ; USART3, Tx Complete
+.org 114
+ rcall isr ; TRX24 - PLL lock interrupt
+.org 116
+ rcall isr ; TRX24 - PLL unlock interrupt
+.org 118
+ rcall isr ; TRX24 - Receive start interrupt
+.org 120
+ rcall isr ; TRX24 - RX_END interrupt
+.org 122
+ rcall isr ; TRX24 - CCA/ED done interrupt
+.org 124
+ rcall isr ; TRX24 - XAH - AMI
+.org 126
+ rcall isr ; TRX24 - TX_END interrupt
+.org 128
+ rcall isr ; TRX24 AWAKE - tranceiver is reaching state TRX_OFF
+.org 130
+ rcall isr ; Symbol counter - compare match 1 interrupt
+.org 132
+ rcall isr ; Symbol counter - compare match 2 interrupt
+.org 134
+ rcall isr ; Symbol counter - compare match 3 interrupt
+.org 136
+ rcall isr ; Symbol counter - overflow interrupt
+.org 138
+ rcall isr ; Symbol counter - backoff interrupt
+.org 140
+ rcall isr ; AES engine ready interrupt
+.org 142
+ rcall isr ; Battery monitor indicates supply voltage below threshold
+.org 144
+ rcall isr ; TRX24 TX start interrupt
+.org 146
+ rcall isr ; Address match interrupt of address filter 0
+.org 148
+ rcall isr ; Address match interrupt of address filter 1
+.org 150
+ rcall isr ; Address match interrupt of address filter 2
+.org 152
+ rcall isr ; Address match interrupt of address filter 3
+.nooverlap
diff --git a/amforth-6.5/avr8/devices/atmega1284rfr2/device.frt b/amforth-6.5/avr8/devices/atmega1284rfr2/device.frt
new file mode 100644
index 0000000..a844898
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega1284rfr2/device.frt
@@ -0,0 +1,1752 @@
+\ Generated Automatically
+
+\ Interrupt Vectors
+#2 constant INT0Addr \ External Interrupt Request 0
+#4 constant INT1Addr \ External Interrupt Request 1
+#6 constant INT2Addr \ External Interrupt Request 2
+#8 constant INT3Addr \ External Interrupt Request 3
+#10 constant INT4Addr \ External Interrupt Request 4
+#12 constant INT5Addr \ External Interrupt Request 5
+#14 constant INT6Addr \ External Interrupt Request 6
+#16 constant INT7Addr \ External Interrupt Request 7
+#18 constant PCINT0Addr \ Pin Change Interrupt Request 0
+#20 constant PCINT1Addr \ Pin Change Interrupt Request 1
+#22 constant PCINT2Addr \ Pin Change Interrupt Request 2
+#24 constant WDTAddr \ Watchdog Time-out Interrupt
+#26 constant TIMER2_COMPAAddr \ Timer/Counter2 Compare Match A
+#28 constant TIMER2_COMPBAddr \ Timer/Counter2 Compare Match B
+#30 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
+#32 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+#34 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
+#36 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
+#38 constant TIMER1_COMPCAddr \ Timer/Counter1 Compare Match C
+#40 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+#42 constant TIMER0_COMPAAddr \ Timer/Counter0 Compare Match A
+#44 constant TIMER0_COMPBAddr \ Timer/Counter0 Compare Match B
+#46 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
+#48 constant SPI_STCAddr \ SPI Serial Transfer Complete
+#50 constant USART0_RXAddr \ USART0, Rx Complete
+#52 constant USART0_UDREAddr \ USART0 Data register Empty
+#54 constant USART0_TXAddr \ USART0, Tx Complete
+#56 constant ANALOG_COMPAddr \ Analog Comparator
+#58 constant ADCAddr \ ADC Conversion Complete
+#60 constant EE_READYAddr \ EEPROM Ready
+#62 constant TIMER3_CAPTAddr \ Timer/Counter3 Capture Event
+#64 constant TIMER3_COMPAAddr \ Timer/Counter3 Compare Match A
+#66 constant TIMER3_COMPBAddr \ Timer/Counter3 Compare Match B
+#68 constant TIMER3_COMPCAddr \ Timer/Counter3 Compare Match C
+#70 constant TIMER3_OVFAddr \ Timer/Counter3 Overflow
+#72 constant USART1_RXAddr \ USART1, Rx Complete
+#74 constant USART1_UDREAddr \ USART1 Data register Empty
+#76 constant USART1_TXAddr \ USART1, Tx Complete
+#78 constant TWIAddr \ 2-wire Serial Interface
+#80 constant SPM_READYAddr \ Store Program Memory Read
+#82 constant TIMER4_CAPTAddr \ Timer/Counter4 Capture Event
+#84 constant TIMER4_COMPAAddr \ Timer/Counter4 Compare Match A
+#86 constant TIMER4_COMPBAddr \ Timer/Counter4 Compare Match B
+#88 constant TIMER4_COMPCAddr \ Timer/Counter4 Compare Match C
+#90 constant TIMER4_OVFAddr \ Timer/Counter4 Overflow
+#92 constant TIMER5_CAPTAddr \ Timer/Counter5 Capture Event
+#94 constant TIMER5_COMPAAddr \ Timer/Counter5 Compare Match A
+#96 constant TIMER5_COMPBAddr \ Timer/Counter5 Compare Match B
+#98 constant TIMER5_COMPCAddr \ Timer/Counter5 Compare Match C
+#100 constant TIMER5_OVFAddr \ Timer/Counter5 Overflow
+#102 constant USART2_RXAddr \ USART2, Rx Complete
+#104 constant USART2_UDREAddr \ USART2 Data register Empty
+#106 constant USART2_TXAddr \ USART2, Tx Complete
+#108 constant USART3_RXAddr \ USART3, Rx Complete
+#110 constant USART3_UDREAddr \ USART3 Data register Empty
+#112 constant USART3_TXAddr \ USART3, Tx Complete
+#114 constant TRX24_PLL_LOCKAddr \ TRX24 - PLL lock interrupt
+#116 constant TRX24_PLL_UNLOCKAddr \ TRX24 - PLL unlock interrupt
+#118 constant TRX24_RX_STARTAddr \ TRX24 - Receive start interrupt
+#120 constant TRX24_RX_ENDAddr \ TRX24 - RX_END interrupt
+#122 constant TRX24_CCA_ED_DONEAddr \ TRX24 - CCA/ED done interrupt
+#124 constant TRX24_XAH_AMIAddr \ TRX24 - XAH - AMI
+#126 constant TRX24_TX_ENDAddr \ TRX24 - TX_END interrupt
+#128 constant TRX24_AWAKEAddr \ TRX24 AWAKE - tranceiver is reaching state TRX_OFF
+#130 constant SCNT_CMP1Addr \ Symbol counter - compare match 1 interrupt
+#132 constant SCNT_CMP2Addr \ Symbol counter - compare match 2 interrupt
+#134 constant SCNT_CMP3Addr \ Symbol counter - compare match 3 interrupt
+#136 constant SCNT_OVFLAddr \ Symbol counter - overflow interrupt
+#138 constant SCNT_BACKOFFAddr \ Symbol counter - backoff interrupt
+#140 constant AES_READYAddr \ AES engine ready interrupt
+#142 constant BAT_LOWAddr \ Battery monitor indicates supply voltage below threshold
+#144 constant TRX24_TX_STARTAddr \ TRX24 TX start interrupt
+#146 constant TRX24_AMI0Addr \ Address match interrupt of address filter 0
+#148 constant TRX24_AMI1Addr \ Address match interrupt of address filter 1
+#150 constant TRX24_AMI2Addr \ Address match interrupt of address filter 2
+#152 constant TRX24_AMI3Addr \ Address match interrupt of address filter 3
+\ ANALOG_COMPARATOR
+$7b constant ADCSRB \ ADC Control and Status Registe
+ $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer
+ 7b $40 bitmask: ADCSRB.ACME \ Analog Comparator Multiplexer
+$50 constant ACSR \ Analog Comparator Control And
+ $80 constant ACSR_ACD \ Analog Comparator Disable
+ 50 $80 bitmask: ACSR.ACD \ Analog Comparator Disable
+ $40 constant ACSR_ACBG \ Analog Comparator Bandgap Sele
+ 50 $40 bitmask: ACSR.ACBG \ Analog Comparator Bandgap Sele
+ $20 constant ACSR_ACO \ Analog Compare Output
+ 50 $20 bitmask: ACSR.ACO \ Analog Compare Output
+ $10 constant ACSR_ACI \ Analog Comparator Interrupt Fl
+ 50 $10 bitmask: ACSR.ACI \ Analog Comparator Interrupt Fl
+ $8 constant ACSR_ACIE \ Analog Comparator Interrupt En
+ 50 $8 bitmask: ACSR.ACIE \ Analog Comparator Interrupt En
+ $4 constant ACSR_ACIC \ Analog Comparator Input Captur
+ 50 $4 bitmask: ACSR.ACIC \ Analog Comparator Input Captur
+ $3 constant ACSR_ACIS \ Analog Comparator Interrupt Mo
+ 50 $3 bitmask: ACSR.ACIS \ Analog Comparator Interrupt Mo
+$7f constant DIDR1 \ Digital Input Disable Register
+ $2 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
+ 7f $2 bitmask: DIDR1.AIN1D \ AIN1 Digital Input Disable
+ $1 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
+ 7f $1 bitmask: DIDR1.AIN0D \ AIN0 Digital Input Disable
+\ USART0
+$c6 constant UDR0 \ USART0 I/O Data Register
+$c0 constant UCSR0A \ USART0 Control and Status Regi
+ $80 constant UCSR0A_RXC0 \ USART Receive Complete
+ c0 $80 bitmask: UCSR0A.RXC0 \ USART Receive Complete
+ $40 constant UCSR0A_TXC0 \ USART Transmit Complete
+ c0 $40 bitmask: UCSR0A.TXC0 \ USART Transmit Complete
+ $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
+ c0 $20 bitmask: UCSR0A.UDRE0 \ USART Data Register Empty
+ $10 constant UCSR0A_FE0 \ Frame Error
+ c0 $10 bitmask: UCSR0A.FE0 \ Frame Error
+ $8 constant UCSR0A_DOR0 \ Data OverRun
+ c0 $8 bitmask: UCSR0A.DOR0 \ Data OverRun
+ $4 constant UCSR0A_UPE0 \ USART Parity Error
+ c0 $4 bitmask: UCSR0A.UPE0 \ USART Parity Error
+ $2 constant UCSR0A_U2X0 \ Double the USART Transmission
+ c0 $2 bitmask: UCSR0A.U2X0 \ Double the USART Transmission
+ $1 constant UCSR0A_MPCM0 \ Multi-processor Communication
+ c0 $1 bitmask: UCSR0A.MPCM0 \ Multi-processor Communication
+$c1 constant UCSR0B \ USART0 Control and Status Regi
+ $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
+ c1 $80 bitmask: UCSR0B.RXCIE0 \ RX Complete Interrupt Enable
+ $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
+ c1 $40 bitmask: UCSR0B.TXCIE0 \ TX Complete Interrupt Enable
+ $20 constant UCSR0B_UDRIE0 \ USART Data Register Empty Inte
+ c1 $20 bitmask: UCSR0B.UDRIE0 \ USART Data Register Empty Inte
+ $10 constant UCSR0B_RXEN0 \ Receiver Enable
+ c1 $10 bitmask: UCSR0B.RXEN0 \ Receiver Enable
+ $8 constant UCSR0B_TXEN0 \ Transmitter Enable
+ c1 $8 bitmask: UCSR0B.TXEN0 \ Transmitter Enable
+ $4 constant UCSR0B_UCSZ02 \ Character Size
+ c1 $4 bitmask: UCSR0B.UCSZ02 \ Character Size
+ $2 constant UCSR0B_RXB80 \ Receive Data Bit 8
+ c1 $2 bitmask: UCSR0B.RXB80 \ Receive Data Bit 8
+ $1 constant UCSR0B_TXB80 \ Transmit Data Bit 8
+ c1 $1 bitmask: UCSR0B.TXB80 \ Transmit Data Bit 8
+$c2 constant UCSR0C \ USART0 Control and Status Regi
+ $c0 constant UCSR0C_UMSEL0 \ USART Mode Select
+ c2 $c0 bitmask: UCSR0C.UMSEL0 \ USART Mode Select
+ $30 constant UCSR0C_UPM0 \ Parity Mode
+ c2 $30 bitmask: UCSR0C.UPM0 \ Parity Mode
+ $8 constant UCSR0C_USBS0 \ Stop Bit Select
+ c2 $8 bitmask: UCSR0C.USBS0 \ Stop Bit Select
+ $6 constant UCSR0C_UCSZ0 \ Character Size
+ c2 $6 bitmask: UCSR0C.UCSZ0 \ Character Size
+ $1 constant UCSR0C_UCPOL0 \ Clock Polarity
+ c2 $1 bitmask: UCSR0C.UCPOL0 \ Clock Polarity
+$c4 constant UBRR0 \ USART0 Baud Rate Register Byt
+\ USART1
+$ce constant UDR1 \ USART1 I/O Data Register
+$c8 constant UCSR1A \ USART1 Control and Status Regi
+ $80 constant UCSR1A_RXC1 \ USART Receive Complete
+ c8 $80 bitmask: UCSR1A.RXC1 \ USART Receive Complete
+ $40 constant UCSR1A_TXC1 \ USART Transmit Complete
+ c8 $40 bitmask: UCSR1A.TXC1 \ USART Transmit Complete
+ $20 constant UCSR1A_UDRE1 \ USART Data Register Empty
+ c8 $20 bitmask: UCSR1A.UDRE1 \ USART Data Register Empty
+ $10 constant UCSR1A_FE1 \ Frame Error
+ c8 $10 bitmask: UCSR1A.FE1 \ Frame Error
+ $8 constant UCSR1A_DOR1 \ Data OverRun
+ c8 $8 bitmask: UCSR1A.DOR1 \ Data OverRun
+ $4 constant UCSR1A_UPE1 \ USART Parity Error
+ c8 $4 bitmask: UCSR1A.UPE1 \ USART Parity Error
+ $2 constant UCSR1A_U2X1 \ Double the USART Transmission
+ c8 $2 bitmask: UCSR1A.U2X1 \ Double the USART Transmission
+ $1 constant UCSR1A_MPCM1 \ Multi-processor Communication
+ c8 $1 bitmask: UCSR1A.MPCM1 \ Multi-processor Communication
+$c9 constant UCSR1B \ USART1 Control and Status Regi
+ $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable
+ c9 $80 bitmask: UCSR1B.RXCIE1 \ RX Complete Interrupt Enable
+ $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable
+ c9 $40 bitmask: UCSR1B.TXCIE1 \ TX Complete Interrupt Enable
+ $20 constant UCSR1B_UDRIE1 \ USART Data Register Empty Inte
+ c9 $20 bitmask: UCSR1B.UDRIE1 \ USART Data Register Empty Inte
+ $10 constant UCSR1B_RXEN1 \ Receiver Enable
+ c9 $10 bitmask: UCSR1B.RXEN1 \ Receiver Enable
+ $8 constant UCSR1B_TXEN1 \ Transmitter Enable
+ c9 $8 bitmask: UCSR1B.TXEN1 \ Transmitter Enable
+ $4 constant UCSR1B_UCSZ12 \ Character Size
+ c9 $4 bitmask: UCSR1B.UCSZ12 \ Character Size
+ $2 constant UCSR1B_RXB81 \ Receive Data Bit 8
+ c9 $2 bitmask: UCSR1B.RXB81 \ Receive Data Bit 8
+ $1 constant UCSR1B_TXB81 \ Transmit Data Bit 8
+ c9 $1 bitmask: UCSR1B.TXB81 \ Transmit Data Bit 8
+$ca constant UCSR1C \ USART1 Control and Status Regi
+ $c0 constant UCSR1C_UMSEL1 \ USART Mode Select
+ ca $c0 bitmask: UCSR1C.UMSEL1 \ USART Mode Select
+ $30 constant UCSR1C_UPM1 \ Parity Mode
+ ca $30 bitmask: UCSR1C.UPM1 \ Parity Mode
+ $8 constant UCSR1C_USBS1 \ Stop Bit Select
+ ca $8 bitmask: UCSR1C.USBS1 \ Stop Bit Select
+ $6 constant UCSR1C_UCSZ1 \ Character Size
+ ca $6 bitmask: UCSR1C.UCSZ1 \ Character Size
+ $1 constant UCSR1C_UCPOL1 \ Clock Polarity
+ ca $1 bitmask: UCSR1C.UCPOL1 \ Clock Polarity
+$cc constant UBRR1 \ USART1 Baud Rate Register Byt
+\ TWI
+$bd constant TWAMR \ TWI (Slave) Address Mask Regis
+ $fe constant TWAMR_TWAM \ TWI Address Mask
+ bd $fe bitmask: TWAMR.TWAM \ TWI Address Mask
+ $1 constant TWAMR_Res \ Reserved Bit
+ bd $1 bitmask: TWAMR.Res \ Reserved Bit
+$b8 constant TWBR \ TWI Bit Rate Register
+$bc constant TWCR \ TWI Control Register
+ $80 constant TWCR_TWINT \ TWI Interrupt Flag
+ bc $80 bitmask: TWCR.TWINT \ TWI Interrupt Flag
+ $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
+ bc $40 bitmask: TWCR.TWEA \ TWI Enable Acknowledge Bit
+ $20 constant TWCR_TWSTA \ TWI START Condition Bit
+ bc $20 bitmask: TWCR.TWSTA \ TWI START Condition Bit
+ $10 constant TWCR_TWSTO \ TWI STOP Condition Bit
+ bc $10 bitmask: TWCR.TWSTO \ TWI STOP Condition Bit
+ $8 constant TWCR_TWWC \ TWI Write Collision Flag
+ bc $8 bitmask: TWCR.TWWC \ TWI Write Collision Flag
+ $4 constant TWCR_TWEN \ TWI Enable Bit
+ bc $4 bitmask: TWCR.TWEN \ TWI Enable Bit
+ $2 constant TWCR_Res \ Reserved Bit
+ bc $2 bitmask: TWCR.Res \ Reserved Bit
+ $1 constant TWCR_TWIE \ TWI Interrupt Enable
+ bc $1 bitmask: TWCR.TWIE \ TWI Interrupt Enable
+$b9 constant TWSR \ TWI Status Register
+ $f8 constant TWSR_TWS \ TWI Status
+ b9 $f8 bitmask: TWSR.TWS \ TWI Status
+ $4 constant TWSR_Res \ Reserved Bit
+ b9 $4 bitmask: TWSR.Res \ Reserved Bit
+ $3 constant TWSR_TWPS \ TWI Prescaler Bits
+ b9 $3 bitmask: TWSR.TWPS \ TWI Prescaler Bits
+$bb constant TWDR \ TWI Data Register
+$ba constant TWAR \ TWI (Slave) Address Register
+ $fe constant TWAR_TWA \ TWI (Slave) Address
+ ba $fe bitmask: TWAR.TWA \ TWI (Slave) Address
+ $1 constant TWAR_TWGCE \ TWI General Call Recognition E
+ ba $1 bitmask: TWAR.TWGCE \ TWI General Call Recognition E
+\ SPI
+$4c constant SPCR \ SPI Control Register
+ $80 constant SPCR_SPIE \ SPI Interrupt Enable
+ 4c $80 bitmask: SPCR.SPIE \ SPI Interrupt Enable
+ $40 constant SPCR_SPE \ SPI Enable
+ 4c $40 bitmask: SPCR.SPE \ SPI Enable
+ $20 constant SPCR_DORD \ Data Order
+ 4c $20 bitmask: SPCR.DORD \ Data Order
+ $10 constant SPCR_MSTR \ Master/Slave Select
+ 4c $10 bitmask: SPCR.MSTR \ Master/Slave Select
+ $8 constant SPCR_CPOL \ Clock polarity
+ 4c $8 bitmask: SPCR.CPOL \ Clock polarity
+ $4 constant SPCR_CPHA \ Clock Phase
+ 4c $4 bitmask: SPCR.CPHA \ Clock Phase
+ $3 constant SPCR_SPR \ SPI Clock Rate Select 1 and 0
+ 4c $3 bitmask: SPCR.SPR \ SPI Clock Rate Select 1 and 0
+$4d constant SPSR \ SPI Status Register
+ $80 constant SPSR_SPIF \ SPI Interrupt Flag
+ 4d $80 bitmask: SPSR.SPIF \ SPI Interrupt Flag
+ $40 constant SPSR_WCOL \ Write Collision Flag
+ 4d $40 bitmask: SPSR.WCOL \ Write Collision Flag
+ $3e constant SPSR_Res \ Reserved
+ 4d $3e bitmask: SPSR.Res \ Reserved
+ $1 constant SPSR_SPI2X \ Double SPI Speed Bit
+ 4d $1 bitmask: SPSR.SPI2X \ Double SPI Speed Bit
+$4e constant SPDR \ SPI Data Register
+\ PORTA
+$22 constant PORTA \ Port A Data Register
+$21 constant DDRA \ Port A Data Direction Register
+$20 constant PINA \ Port A Input Pins Address
+\ PORTB
+$25 constant PORTB \ Port B Data Register
+$24 constant DDRB \ Port B Data Direction Register
+$23 constant PINB \ Port B Input Pins Address
+\ PORTC
+$28 constant PORTC \ Port C Data Register
+$27 constant DDRC \ Port C Data Direction Register
+$26 constant PINC \ Port C Input Pins Address
+\ PORTD
+$2b constant PORTD \ Port D Data Register
+$2a constant DDRD \ Port D Data Direction Register
+$29 constant PIND \ Port D Input Pins Address
+\ PORTE
+$2e constant PORTE \ Port E Data Register
+$2d constant DDRE \ Port E Data Direction Register
+$2c constant PINE \ Port E Input Pins Address
+\ PORTF
+$31 constant PORTF \ Port F Data Register
+$30 constant DDRF \ Port F Data Direction Register
+$2f constant PINF \ Port F Input Pins Address
+\ PORTG
+$34 constant PORTG \ Port G Data Register
+$33 constant DDRG \ Port G Data Direction Register
+$32 constant PING \ Port G Input Pins Address
+\ TIMER_COUNTER_0
+$48 constant OCR0B \ Timer/Counter0 Output Compare
+$47 constant OCR0A \ Timer/Counter0 Output Compare
+$46 constant TCNT0 \ Timer/Counter0 Register
+$45 constant TCCR0B \ Timer/Counter0 Control Registe
+ $80 constant TCCR0B_FOC0A \ Force Output Compare A
+ 45 $80 bitmask: TCCR0B.FOC0A \ Force Output Compare A
+ $40 constant TCCR0B_FOC0B \ Force Output Compare B
+ 45 $40 bitmask: TCCR0B.FOC0B \ Force Output Compare B
+ $30 constant TCCR0B_Res \ Reserved Bit
+ 45 $30 bitmask: TCCR0B.Res \ Reserved Bit
+ $8 constant TCCR0B_WGM02 \
+ 45 $8 bitmask: TCCR0B.WGM02 \
+ $7 constant TCCR0B_CS0 \ Clock Select
+ 45 $7 bitmask: TCCR0B.CS0 \ Clock Select
+$44 constant TCCR0A \ Timer/Counter0 Control Registe
+ $c0 constant TCCR0A_COM0A \ Compare Match Output A Mode
+ 44 $c0 bitmask: TCCR0A.COM0A \ Compare Match Output A Mode
+ $30 constant TCCR0A_COM0B \ Compare Match Output B Mode
+ 44 $30 bitmask: TCCR0A.COM0B \ Compare Match Output B Mode
+ $c constant TCCR0A_Res \ Reserved Bit
+ 44 $c bitmask: TCCR0A.Res \ Reserved Bit
+ $3 constant TCCR0A_WGM0 \ Waveform Generation Mode
+ 44 $3 bitmask: TCCR0A.WGM0 \ Waveform Generation Mode
+$6e constant TIMSK0 \ Timer/Counter0 Interrupt Mask
+ $f8 constant TIMSK0_Res \ Reserved
+ 6e $f8 bitmask: TIMSK0.Res \ Reserved
+ $4 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare
+ 6e $4 bitmask: TIMSK0.OCIE0B \ Timer/Counter0 Output Compare
+ $2 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare
+ 6e $2 bitmask: TIMSK0.OCIE0A \ Timer/Counter0 Output Compare
+ $1 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interr
+ 6e $1 bitmask: TIMSK0.TOIE0 \ Timer/Counter0 Overflow Interr
+$35 constant TIFR0 \ Timer/Counter0 Interrupt Flag
+ $f8 constant TIFR0_Res \ Reserved
+ 35 $f8 bitmask: TIFR0.Res \ Reserved
+ $4 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare
+ 35 $4 bitmask: TIFR0.OCF0B \ Timer/Counter0 Output Compare
+ $2 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare
+ 35 $2 bitmask: TIFR0.OCF0A \ Timer/Counter0 Output Compare
+ $1 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
+ 35 $1 bitmask: TIFR0.TOV0 \ Timer/Counter0 Overflow Flag
+$43 constant GTCCR \ General Timer/Counter Control
+ $80 constant GTCCR_TSM \ Timer/Counter Synchronization
+ 43 $80 bitmask: GTCCR.TSM \ Timer/Counter Synchronization
+ $7c constant GTCCR_Res \ Reserved
+ 43 $7c bitmask: GTCCR.Res \ Reserved
+ $2 constant GTCCR_PSRASY \ Prescaler Reset Timer/Counter2
+ 43 $2 bitmask: GTCCR.PSRASY \ Prescaler Reset Timer/Counter2
+ $1 constant GTCCR_PSRSYNC \ Prescaler Reset for Synchronou
+ 43 $1 bitmask: GTCCR.PSRSYNC \ Prescaler Reset for Synchronou
+\ TIMER_COUNTER_2
+$70 constant TIMSK2 \ Timer/Counter Interrupt Mask r
+ $f8 constant TIMSK2_Res \ Reserved Bit
+ 70 $f8 bitmask: TIMSK2.Res \ Reserved Bit
+ $4 constant TIMSK2_OCIE2B \ Timer/Counter2 Output Compare
+ 70 $4 bitmask: TIMSK2.OCIE2B \ Timer/Counter2 Output Compare
+ $2 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare
+ 70 $2 bitmask: TIMSK2.OCIE2A \ Timer/Counter2 Output Compare
+ $1 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interr
+ 70 $1 bitmask: TIMSK2.TOIE2 \ Timer/Counter2 Overflow Interr
+$37 constant TIFR2 \ Timer/Counter Interrupt Flag R
+ $f8 constant TIFR2_Res \ Reserved Bit
+ 37 $f8 bitmask: TIFR2.Res \ Reserved Bit
+ $4 constant TIFR2_OCF2B \ Output Compare Flag 2 B
+ 37 $4 bitmask: TIFR2.OCF2B \ Output Compare Flag 2 B
+ $2 constant TIFR2_OCF2A \ Output Compare Flag 2 A
+ 37 $2 bitmask: TIFR2.OCF2A \ Output Compare Flag 2 A
+ $1 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
+ 37 $1 bitmask: TIFR2.TOV2 \ Timer/Counter2 Overflow Flag
+$b0 constant TCCR2A \ Timer/Counter2 Control Registe
+ $c0 constant TCCR2A_COM2A \ Compare Match Output A Mode
+ b0 $c0 bitmask: TCCR2A.COM2A \ Compare Match Output A Mode
+ $30 constant TCCR2A_COM2B \ Compare Match Output B Mode
+ b0 $30 bitmask: TCCR2A.COM2B \ Compare Match Output B Mode
+ $c constant TCCR2A_Res \ Reserved
+ b0 $c bitmask: TCCR2A.Res \ Reserved
+ $3 constant TCCR2A_WGM2 \ Waveform Generation Mode
+ b0 $3 bitmask: TCCR2A.WGM2 \ Waveform Generation Mode
+$b1 constant TCCR2B \ Timer/Counter2 Control Registe
+ $80 constant TCCR2B_FOC2A \ Force Output Compare A
+ b1 $80 bitmask: TCCR2B.FOC2A \ Force Output Compare A
+ $40 constant TCCR2B_FOC2B \ Force Output Compare B
+ b1 $40 bitmask: TCCR2B.FOC2B \ Force Output Compare B
+ $30 constant TCCR2B_Res \ Reserved
+ b1 $30 bitmask: TCCR2B.Res \ Reserved
+ $8 constant TCCR2B_WGM22 \ Waveform Generation Mode
+ b1 $8 bitmask: TCCR2B.WGM22 \ Waveform Generation Mode
+ $7 constant TCCR2B_CS2 \ Clock Select
+ b1 $7 bitmask: TCCR2B.CS2 \ Clock Select
+$b2 constant TCNT2 \ Timer/Counter2
+$b4 constant OCR2B \ Timer/Counter2 Output Compare
+$b3 constant OCR2A \ Timer/Counter2 Output Compare
+$b6 constant ASSR \ Asynchronous Status Register
+ $80 constant ASSR_EXCLKAMR \ Enable External Clock Input fo
+ b6 $80 bitmask: ASSR.EXCLKAMR \ Enable External Clock Input fo
+ $40 constant ASSR_EXCLK \ Enable External Clock Input
+ b6 $40 bitmask: ASSR.EXCLK \ Enable External Clock Input
+ $20 constant ASSR_AS2 \ Timer/Counter2 Asynchronous Mo
+ b6 $20 bitmask: ASSR.AS2 \ Timer/Counter2 Asynchronous Mo
+ $10 constant ASSR_TCN2UB \ Timer/Counter2 Update Busy
+ b6 $10 bitmask: ASSR.TCN2UB \ Timer/Counter2 Update Busy
+ $8 constant ASSR_OCR2AUB \ Timer/Counter2 Output Compare
+ b6 $8 bitmask: ASSR.OCR2AUB \ Timer/Counter2 Output Compare
+ $4 constant ASSR_OCR2BUB \ Timer/Counter2 Output Compare
+ b6 $4 bitmask: ASSR.OCR2BUB \ Timer/Counter2 Output Compare
+ $2 constant ASSR_TCR2AUB \ Timer/Counter2 Control Registe
+ b6 $2 bitmask: ASSR.TCR2AUB \ Timer/Counter2 Control Registe
+ $1 constant ASSR_TCR2BUB \ Timer/Counter2 Control Registe
+ b6 $1 bitmask: ASSR.TCR2BUB \ Timer/Counter2 Control Registe
+$43 constant GTCCR \ General Timer Counter Control
+ $80 constant GTCCR_TSM \ Timer/Counter Synchronization
+ 43 $80 bitmask: GTCCR.TSM \ Timer/Counter Synchronization
+ $2 constant GTCCR_PSRASY \ Prescaler Reset Timer/Counter2
+ 43 $2 bitmask: GTCCR.PSRASY \ Prescaler Reset Timer/Counter2
+\ WATCHDOG
+$60 constant WDTCSR \ Watchdog Timer Control Registe
+ $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Fla
+ 60 $80 bitmask: WDTCSR.WDIF \ Watchdog Timeout Interrupt Fla
+ $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Ena
+ 60 $40 bitmask: WDTCSR.WDIE \ Watchdog Timeout Interrupt Ena
+ $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
+ 60 $27 bitmask: WDTCSR.WDP \ Watchdog Timer Prescaler Bits
+ $10 constant WDTCSR_WDCE \ Watchdog Change Enable
+ 60 $10 bitmask: WDTCSR.WDCE \ Watchdog Change Enable
+ $8 constant WDTCSR_WDE \ Watch Dog Enable
+ 60 $8 bitmask: WDTCSR.WDE \ Watch Dog Enable
+\ TIMER_COUNTER_5
+$120 constant TCCR5A \ Timer/Counter5 Control Registe
+ $c0 constant TCCR5A_COM5A \ Compare Output Mode for Channe
+ 120 $c0 bitmask: TCCR5A.COM5A \ Compare Output Mode for Channe
+ $30 constant TCCR5A_COM5B \ Compare Output Mode for Channe
+ 120 $30 bitmask: TCCR5A.COM5B \ Compare Output Mode for Channe
+ $c constant TCCR5A_COM5C \ Compare Output Mode for Channe
+ 120 $c bitmask: TCCR5A.COM5C \ Compare Output Mode for Channe
+ $3 constant TCCR5A_WGM5 \ Waveform Generation Mode
+ 120 $3 bitmask: TCCR5A.WGM5 \ Waveform Generation Mode
+$121 constant TCCR5B \ Timer/Counter5 Control Registe
+ $80 constant TCCR5B_ICNC5 \ Input Capture 5 Noise Cancelle
+ 121 $80 bitmask: TCCR5B.ICNC5 \ Input Capture 5 Noise Cancelle
+ $40 constant TCCR5B_ICES5 \ Input Capture 5 Edge Select
+ 121 $40 bitmask: TCCR5B.ICES5 \ Input Capture 5 Edge Select
+ $20 constant TCCR5B_Res \ Reserved Bit
+ 121 $20 bitmask: TCCR5B.Res \ Reserved Bit
+ $18 constant TCCR5B_WGM5 \ Waveform Generation Mode
+ 121 $18 bitmask: TCCR5B.WGM5 \ Waveform Generation Mode
+ $7 constant TCCR5B_CS5 \ Clock Select
+ 121 $7 bitmask: TCCR5B.CS5 \ Clock Select
+$122 constant TCCR5C \ Timer/Counter5 Control Registe
+ $80 constant TCCR5C_FOC5A \ Force Output Compare for Chann
+ 122 $80 bitmask: TCCR5C.FOC5A \ Force Output Compare for Chann
+ $40 constant TCCR5C_FOC5B \ Force Output Compare for Chann
+ 122 $40 bitmask: TCCR5C.FOC5B \ Force Output Compare for Chann
+ $20 constant TCCR5C_FOC5C \ Force Output Compare for Chann
+ 122 $20 bitmask: TCCR5C.FOC5C \ Force Output Compare for Chann
+ $1f constant TCCR5C_Res \ Reserved
+ 122 $1f bitmask: TCCR5C.Res \ Reserved
+$124 constant TCNT5 \ Timer/Counter5 Bytes
+$128 constant OCR5A \ Timer/Counter5 Output Compare
+$12a constant OCR5B \ Timer/Counter5 Output Compare
+$12c constant OCR5C \ Timer/Counter5 Output Compare
+$126 constant ICR5 \ Timer/Counter5 Input Capture R
+$73 constant TIMSK5 \ Timer/Counter5 Interrupt Mask
+ $c0 constant TIMSK5_Res \ Reserved Bit
+ 73 $c0 bitmask: TIMSK5.Res \ Reserved Bit
+ $20 constant TIMSK5_ICIE5 \ Timer/Counter5 Input Capture I
+ 73 $20 bitmask: TIMSK5.ICIE5 \ Timer/Counter5 Input Capture I
+ $10 constant TIMSK5_Res \ Reserved Bit
+ 73 $10 bitmask: TIMSK5.Res \ Reserved Bit
+ $8 constant TIMSK5_OCIE5C \ Timer/Counter5 Output Compare
+ 73 $8 bitmask: TIMSK5.OCIE5C \ Timer/Counter5 Output Compare
+ $4 constant TIMSK5_OCIE5B \ Timer/Counter5 Output Compare
+ 73 $4 bitmask: TIMSK5.OCIE5B \ Timer/Counter5 Output Compare
+ $2 constant TIMSK5_OCIE5A \ Timer/Counter5 Output Compare
+ 73 $2 bitmask: TIMSK5.OCIE5A \ Timer/Counter5 Output Compare
+ $1 constant TIMSK5_TOIE5 \ Timer/Counter5 Overflow Interr
+ 73 $1 bitmask: TIMSK5.TOIE5 \ Timer/Counter5 Overflow Interr
+$3a constant TIFR5 \ Timer/Counter5 Interrupt Flag
+ $c0 constant TIFR5_Res \ Reserved Bit
+ 3a $c0 bitmask: TIFR5.Res \ Reserved Bit
+ $20 constant TIFR5_ICF5 \ Timer/Counter5 Input Capture F
+ 3a $20 bitmask: TIFR5.ICF5 \ Timer/Counter5 Input Capture F
+ $10 constant TIFR5_Res \ Reserved Bit
+ 3a $10 bitmask: TIFR5.Res \ Reserved Bit
+ $8 constant TIFR5_OCF5C \ Timer/Counter5 Output Compare
+ 3a $8 bitmask: TIFR5.OCF5C \ Timer/Counter5 Output Compare
+ $4 constant TIFR5_OCF5B \ Timer/Counter5 Output Compare
+ 3a $4 bitmask: TIFR5.OCF5B \ Timer/Counter5 Output Compare
+ $2 constant TIFR5_OCF5A \ Timer/Counter5 Output Compare
+ 3a $2 bitmask: TIFR5.OCF5A \ Timer/Counter5 Output Compare
+ $1 constant TIFR5_TOV5 \ Timer/Counter5 Overflow Flag
+ 3a $1 bitmask: TIFR5.TOV5 \ Timer/Counter5 Overflow Flag
+\ TIMER_COUNTER_4
+$a0 constant TCCR4A \ Timer/Counter4 Control Registe
+ $c0 constant TCCR4A_COM4A \ Compare Output Mode for Channe
+ a0 $c0 bitmask: TCCR4A.COM4A \ Compare Output Mode for Channe
+ $30 constant TCCR4A_COM4B \ Compare Output Mode for Channe
+ a0 $30 bitmask: TCCR4A.COM4B \ Compare Output Mode for Channe
+ $c constant TCCR4A_COM4C \ Compare Output Mode for Channe
+ a0 $c bitmask: TCCR4A.COM4C \ Compare Output Mode for Channe
+ $3 constant TCCR4A_WGM4 \ Waveform Generation Mode
+ a0 $3 bitmask: TCCR4A.WGM4 \ Waveform Generation Mode
+$a1 constant TCCR4B \ Timer/Counter4 Control Registe
+ $80 constant TCCR4B_ICNC4 \ Input Capture 4 Noise Cancelle
+ a1 $80 bitmask: TCCR4B.ICNC4 \ Input Capture 4 Noise Cancelle
+ $40 constant TCCR4B_ICES4 \ Input Capture 4 Edge Select
+ a1 $40 bitmask: TCCR4B.ICES4 \ Input Capture 4 Edge Select
+ $20 constant TCCR4B_Res \ Reserved Bit
+ a1 $20 bitmask: TCCR4B.Res \ Reserved Bit
+ $18 constant TCCR4B_WGM4 \ Waveform Generation Mode
+ a1 $18 bitmask: TCCR4B.WGM4 \ Waveform Generation Mode
+ $7 constant TCCR4B_CS4 \ Clock Select
+ a1 $7 bitmask: TCCR4B.CS4 \ Clock Select
+$a2 constant TCCR4C \ Timer/Counter4 Control Registe
+ $80 constant TCCR4C_FOC4A \ Force Output Compare for Chann
+ a2 $80 bitmask: TCCR4C.FOC4A \ Force Output Compare for Chann
+ $40 constant TCCR4C_FOC4B \ Force Output Compare for Chann
+ a2 $40 bitmask: TCCR4C.FOC4B \ Force Output Compare for Chann
+ $20 constant TCCR4C_FOC4C \ Force Output Compare for Chann
+ a2 $20 bitmask: TCCR4C.FOC4C \ Force Output Compare for Chann
+ $1f constant TCCR4C_Res \ Reserved
+ a2 $1f bitmask: TCCR4C.Res \ Reserved
+$a4 constant TCNT4 \ Timer/Counter4 Bytes
+$a8 constant OCR4A \ Timer/Counter4 Output Compare
+$aa constant OCR4B \ Timer/Counter4 Output Compare
+$ac constant OCR4C \ Timer/Counter4 Output Compare
+$a6 constant ICR4 \ Timer/Counter4 Input Capture R
+$72 constant TIMSK4 \ Timer/Counter4 Interrupt Mask
+ $c0 constant TIMSK4_Res \ Reserved Bit
+ 72 $c0 bitmask: TIMSK4.Res \ Reserved Bit
+ $20 constant TIMSK4_ICIE4 \ Timer/Counter4 Input Capture I
+ 72 $20 bitmask: TIMSK4.ICIE4 \ Timer/Counter4 Input Capture I
+ $10 constant TIMSK4_Res \ Reserved Bit
+ 72 $10 bitmask: TIMSK4.Res \ Reserved Bit
+ $8 constant TIMSK4_OCIE4C \ Timer/Counter4 Output Compare
+ 72 $8 bitmask: TIMSK4.OCIE4C \ Timer/Counter4 Output Compare
+ $4 constant TIMSK4_OCIE4B \ Timer/Counter4 Output Compare
+ 72 $4 bitmask: TIMSK4.OCIE4B \ Timer/Counter4 Output Compare
+ $2 constant TIMSK4_OCIE4A \ Timer/Counter4 Output Compare
+ 72 $2 bitmask: TIMSK4.OCIE4A \ Timer/Counter4 Output Compare
+ $1 constant TIMSK4_TOIE4 \ Timer/Counter4 Overflow Interr
+ 72 $1 bitmask: TIMSK4.TOIE4 \ Timer/Counter4 Overflow Interr
+$39 constant TIFR4 \ Timer/Counter4 Interrupt Flag
+ $c0 constant TIFR4_Res \ Reserved Bit
+ 39 $c0 bitmask: TIFR4.Res \ Reserved Bit
+ $20 constant TIFR4_ICF4 \ Timer/Counter4 Input Capture F
+ 39 $20 bitmask: TIFR4.ICF4 \ Timer/Counter4 Input Capture F
+ $10 constant TIFR4_Res \ Reserved Bit
+ 39 $10 bitmask: TIFR4.Res \ Reserved Bit
+ $8 constant TIFR4_OCF4C \ Timer/Counter4 Output Compare
+ 39 $8 bitmask: TIFR4.OCF4C \ Timer/Counter4 Output Compare
+ $4 constant TIFR4_OCF4B \ Timer/Counter4 Output Compare
+ 39 $4 bitmask: TIFR4.OCF4B \ Timer/Counter4 Output Compare
+ $2 constant TIFR4_OCF4A \ Timer/Counter4 Output Compare
+ 39 $2 bitmask: TIFR4.OCF4A \ Timer/Counter4 Output Compare
+ $1 constant TIFR4_TOV4 \ Timer/Counter4 Overflow Flag
+ 39 $1 bitmask: TIFR4.TOV4 \ Timer/Counter4 Overflow Flag
+\ TIMER_COUNTER_3
+$90 constant TCCR3A \ Timer/Counter3 Control Registe
+ $c0 constant TCCR3A_COM3A \ Compare Output Mode for Channe
+ 90 $c0 bitmask: TCCR3A.COM3A \ Compare Output Mode for Channe
+ $30 constant TCCR3A_COM3B \ Compare Output Mode for Channe
+ 90 $30 bitmask: TCCR3A.COM3B \ Compare Output Mode for Channe
+ $c constant TCCR3A_COM3C \ Compare Output Mode for Channe
+ 90 $c bitmask: TCCR3A.COM3C \ Compare Output Mode for Channe
+ $3 constant TCCR3A_WGM3 \ Waveform Generation Mode
+ 90 $3 bitmask: TCCR3A.WGM3 \ Waveform Generation Mode
+$91 constant TCCR3B \ Timer/Counter3 Control Registe
+ $80 constant TCCR3B_ICNC3 \ Input Capture 3 Noise Cancelle
+ 91 $80 bitmask: TCCR3B.ICNC3 \ Input Capture 3 Noise Cancelle
+ $40 constant TCCR3B_ICES3 \ Input Capture 3 Edge Select
+ 91 $40 bitmask: TCCR3B.ICES3 \ Input Capture 3 Edge Select
+ $20 constant TCCR3B_Res \ Reserved Bit
+ 91 $20 bitmask: TCCR3B.Res \ Reserved Bit
+ $18 constant TCCR3B_WGM3 \ Waveform Generation Mode
+ 91 $18 bitmask: TCCR3B.WGM3 \ Waveform Generation Mode
+ $7 constant TCCR3B_CS3 \ Clock Select
+ 91 $7 bitmask: TCCR3B.CS3 \ Clock Select
+$92 constant TCCR3C \ Timer/Counter3 Control Registe
+ $80 constant TCCR3C_FOC3A \ Force Output Compare for Chann
+ 92 $80 bitmask: TCCR3C.FOC3A \ Force Output Compare for Chann
+ $40 constant TCCR3C_FOC3B \ Force Output Compare for Chann
+ 92 $40 bitmask: TCCR3C.FOC3B \ Force Output Compare for Chann
+ $20 constant TCCR3C_FOC3C \ Force Output Compare for Chann
+ 92 $20 bitmask: TCCR3C.FOC3C \ Force Output Compare for Chann
+ $1f constant TCCR3C_Res \ Reserved
+ 92 $1f bitmask: TCCR3C.Res \ Reserved
+$94 constant TCNT3 \ Timer/Counter3 Bytes
+$98 constant OCR3A \ Timer/Counter3 Output Compare
+$9a constant OCR3B \ Timer/Counter3 Output Compare
+$9c constant OCR3C \ Timer/Counter3 Output Compare
+$96 constant ICR3 \ Timer/Counter3 Input Capture R
+$71 constant TIMSK3 \ Timer/Counter3 Interrupt Mask
+ $c0 constant TIMSK3_Res \ Reserved Bit
+ 71 $c0 bitmask: TIMSK3.Res \ Reserved Bit
+ $20 constant TIMSK3_ICIE3 \ Timer/Counter3 Input Capture I
+ 71 $20 bitmask: TIMSK3.ICIE3 \ Timer/Counter3 Input Capture I
+ $10 constant TIMSK3_Res \ Reserved Bit
+ 71 $10 bitmask: TIMSK3.Res \ Reserved Bit
+ $8 constant TIMSK3_OCIE3C \ Timer/Counter3 Output Compare
+ 71 $8 bitmask: TIMSK3.OCIE3C \ Timer/Counter3 Output Compare
+ $4 constant TIMSK3_OCIE3B \ Timer/Counter3 Output Compare
+ 71 $4 bitmask: TIMSK3.OCIE3B \ Timer/Counter3 Output Compare
+ $2 constant TIMSK3_OCIE3A \ Timer/Counter3 Output Compare
+ 71 $2 bitmask: TIMSK3.OCIE3A \ Timer/Counter3 Output Compare
+ $1 constant TIMSK3_TOIE3 \ Timer/Counter3 Overflow Interr
+ 71 $1 bitmask: TIMSK3.TOIE3 \ Timer/Counter3 Overflow Interr
+$38 constant TIFR3 \ Timer/Counter3 Interrupt Flag
+ $c0 constant TIFR3_Res \ Reserved Bit
+ 38 $c0 bitmask: TIFR3.Res \ Reserved Bit
+ $20 constant TIFR3_ICF3 \ Timer/Counter3 Input Capture F
+ 38 $20 bitmask: TIFR3.ICF3 \ Timer/Counter3 Input Capture F
+ $10 constant TIFR3_Res \ Reserved Bit
+ 38 $10 bitmask: TIFR3.Res \ Reserved Bit
+ $8 constant TIFR3_OCF3C \ Timer/Counter3 Output Compare
+ 38 $8 bitmask: TIFR3.OCF3C \ Timer/Counter3 Output Compare
+ $4 constant TIFR3_OCF3B \ Timer/Counter3 Output Compare
+ 38 $4 bitmask: TIFR3.OCF3B \ Timer/Counter3 Output Compare
+ $2 constant TIFR3_OCF3A \ Timer/Counter3 Output Compare
+ 38 $2 bitmask: TIFR3.OCF3A \ Timer/Counter3 Output Compare
+ $1 constant TIFR3_TOV3 \ Timer/Counter3 Overflow Flag
+ 38 $1 bitmask: TIFR3.TOV3 \ Timer/Counter3 Overflow Flag
+\ TIMER_COUNTER_1
+$80 constant TCCR1A \ Timer/Counter1 Control Registe
+ $c0 constant TCCR1A_COM1A \ Compare Output Mode for Channe
+ 80 $c0 bitmask: TCCR1A.COM1A \ Compare Output Mode for Channe
+ $30 constant TCCR1A_COM1B \ Compare Output Mode for Channe
+ 80 $30 bitmask: TCCR1A.COM1B \ Compare Output Mode for Channe
+ $c constant TCCR1A_COM1C \ Compare Output Mode for Channe
+ 80 $c bitmask: TCCR1A.COM1C \ Compare Output Mode for Channe
+ $3 constant TCCR1A_WGM1 \ Waveform Generation Mode
+ 80 $3 bitmask: TCCR1A.WGM1 \ Waveform Generation Mode
+$81 constant TCCR1B \ Timer/Counter1 Control Registe
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Cancelle
+ 81 $80 bitmask: TCCR1B.ICNC1 \ Input Capture 1 Noise Cancelle
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ 81 $40 bitmask: TCCR1B.ICES1 \ Input Capture 1 Edge Select
+ $20 constant TCCR1B_Res \ Reserved Bit
+ 81 $20 bitmask: TCCR1B.Res \ Reserved Bit
+ $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
+ 81 $18 bitmask: TCCR1B.WGM1 \ Waveform Generation Mode
+ $7 constant TCCR1B_CS1 \ Clock Select
+ 81 $7 bitmask: TCCR1B.CS1 \ Clock Select
+$82 constant TCCR1C \ Timer/Counter1 Control Registe
+ $80 constant TCCR1C_FOC1A \ Force Output Compare for Chann
+ 82 $80 bitmask: TCCR1C.FOC1A \ Force Output Compare for Chann
+ $40 constant TCCR1C_FOC1B \ Force Output Compare for Chann
+ 82 $40 bitmask: TCCR1C.FOC1B \ Force Output Compare for Chann
+ $20 constant TCCR1C_FOC1C \ Force Output Compare for Chann
+ 82 $20 bitmask: TCCR1C.FOC1C \ Force Output Compare for Chann
+ $1f constant TCCR1C_Res \ Reserved
+ 82 $1f bitmask: TCCR1C.Res \ Reserved
+$84 constant TCNT1 \ Timer/Counter1 Bytes
+$88 constant OCR1A \ Timer/Counter1 Output Compare
+$8a constant OCR1B \ Timer/Counter1 Output Compare
+$8c constant OCR1C \ Timer/Counter1 Output Compare
+$86 constant ICR1 \ Timer/Counter1 Input Capture R
+$6f constant TIMSK1 \ Timer/Counter1 Interrupt Mask
+ $c0 constant TIMSK1_Res \ Reserved Bit
+ 6f $c0 bitmask: TIMSK1.Res \ Reserved Bit
+ $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture I
+ 6f $20 bitmask: TIMSK1.ICIE1 \ Timer/Counter1 Input Capture I
+ $10 constant TIMSK1_Res \ Reserved Bit
+ 6f $10 bitmask: TIMSK1.Res \ Reserved Bit
+ $8 constant TIMSK1_OCIE1C \ Timer/Counter1 Output Compare
+ 6f $8 bitmask: TIMSK1.OCIE1C \ Timer/Counter1 Output Compare
+ $4 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare
+ 6f $4 bitmask: TIMSK1.OCIE1B \ Timer/Counter1 Output Compare
+ $2 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare
+ 6f $2 bitmask: TIMSK1.OCIE1A \ Timer/Counter1 Output Compare
+ $1 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interr
+ 6f $1 bitmask: TIMSK1.TOIE1 \ Timer/Counter1 Overflow Interr
+$36 constant TIFR1 \ Timer/Counter1 Interrupt Flag
+ $c0 constant TIFR1_Res \ Reserved Bit
+ 36 $c0 bitmask: TIFR1.Res \ Reserved Bit
+ $20 constant TIFR1_ICF1 \ Timer/Counter1 Input Capture F
+ 36 $20 bitmask: TIFR1.ICF1 \ Timer/Counter1 Input Capture F
+ $10 constant TIFR1_Res \ Reserved Bit
+ 36 $10 bitmask: TIFR1.Res \ Reserved Bit
+ $8 constant TIFR1_OCF1C \ Timer/Counter1 Output Compare
+ 36 $8 bitmask: TIFR1.OCF1C \ Timer/Counter1 Output Compare
+ $4 constant TIFR1_OCF1B \ Timer/Counter1 Output Compare
+ 36 $4 bitmask: TIFR1.OCF1B \ Timer/Counter1 Output Compare
+ $2 constant TIFR1_OCF1A \ Timer/Counter1 Output Compare
+ 36 $2 bitmask: TIFR1.OCF1A \ Timer/Counter1 Output Compare
+ $1 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
+ 36 $1 bitmask: TIFR1.TOV1 \ Timer/Counter1 Overflow Flag
+\ TRX24
+$138 constant PARCR \ Power Amplifier Ramp up/down C
+ $e0 constant PARCR_PALTD \ ext. PA Ramp Down Lead Time
+ 138 $e0 bitmask: PARCR.PALTD \ ext. PA Ramp Down Lead Time
+ $1c constant PARCR_PALTU \ ext. PA Ramp Up Lead Time
+ 138 $1c bitmask: PARCR.PALTU \ ext. PA Ramp Up Lead Time
+ $2 constant PARCR_PARDFI \ Power Amplifier Ramp Down Freq
+ 138 $2 bitmask: PARCR.PARDFI \ Power Amplifier Ramp Down Freq
+ $1 constant PARCR_PARUFI \ Power Amplifier Ramp Up Freque
+ 138 $1 bitmask: PARCR.PARUFI \ Power Amplifier Ramp Up Freque
+$10e constant MAFSA0L \ Transceiver MAC Short Address
+ $ff constant MAFSA0L_MAFSA0L \ MAC Short Address low Byte for
+ 10e $ff bitmask: MAFSA0L.MAFSA0L \ MAC Short Address low Byte for
+$10f constant MAFSA0H \ Transceiver MAC Short Address
+ $ff constant MAFSA0H_MAFSA0H \ MAC Short Address high Byte fo
+ 10f $ff bitmask: MAFSA0H.MAFSA0H \ MAC Short Address high Byte fo
+$110 constant MAFPA0L \ Transceiver Personal Area Netw
+ $ff constant MAFPA0L_MAFPA0L \ MAC Personal Area Network ID l
+ 110 $ff bitmask: MAFPA0L.MAFPA0L \ MAC Personal Area Network ID l
+$111 constant MAFPA0H \ Transceiver Personal Area Netw
+ $ff constant MAFPA0H_MAFPA0H \ MAC Personal Area Network ID h
+ 111 $ff bitmask: MAFPA0H.MAFPA0H \ MAC Personal Area Network ID h
+$112 constant MAFSA1L \ Transceiver MAC Short Address
+ $ff constant MAFSA1L_MAFSA1L \ MAC Short Address low Byte for
+ 112 $ff bitmask: MAFSA1L.MAFSA1L \ MAC Short Address low Byte for
+$113 constant MAFSA1H \ Transceiver MAC Short Address
+ $ff constant MAFSA1H_MAFSA1H \ MAC Short Address high Byte fo
+ 113 $ff bitmask: MAFSA1H.MAFSA1H \ MAC Short Address high Byte fo
+$114 constant MAFPA1L \ Transceiver Personal Area Netw
+ $ff constant MAFPA1L_MAFPA1L \ MAC Personal Area Network ID l
+ 114 $ff bitmask: MAFPA1L.MAFPA1L \ MAC Personal Area Network ID l
+$115 constant MAFPA1H \ Transceiver Personal Area Netw
+ $ff constant MAFPA1H_MAFPA1H \ MAC Personal Area Network ID h
+ 115 $ff bitmask: MAFPA1H.MAFPA1H \ MAC Personal Area Network ID h
+$116 constant MAFSA2L \ Transceiver MAC Short Address
+ $ff constant MAFSA2L_MAFSA2L \ MAC Short Address low Byte for
+ 116 $ff bitmask: MAFSA2L.MAFSA2L \ MAC Short Address low Byte for
+$117 constant MAFSA2H \ Transceiver MAC Short Address
+ $ff constant MAFSA2H_MAFSA2H \ MAC Short Address high Byte fo
+ 117 $ff bitmask: MAFSA2H.MAFSA2H \ MAC Short Address high Byte fo
+$118 constant MAFPA2L \ Transceiver Personal Area Netw
+ $ff constant MAFPA2L_MAFPA2L \ MAC Personal Area Network ID l
+ 118 $ff bitmask: MAFPA2L.MAFPA2L \ MAC Personal Area Network ID l
+$119 constant MAFPA2H \ Transceiver Personal Area Netw
+ $ff constant MAFPA2H_MAFPA2H \ MAC Personal Area Network ID h
+ 119 $ff bitmask: MAFPA2H.MAFPA2H \ MAC Personal Area Network ID h
+$11a constant MAFSA3L \ Transceiver MAC Short Address
+ $ff constant MAFSA3L_MAFSA3L \ MAC Short Address low Byte for
+ 11a $ff bitmask: MAFSA3L.MAFSA3L \ MAC Short Address low Byte for
+$11b constant MAFSA3H \ Transceiver MAC Short Address
+ $ff constant MAFSA3H_MAFSA3H \ MAC Short Address high Byte fo
+ 11b $ff bitmask: MAFSA3H.MAFSA3H \ MAC Short Address high Byte fo
+$11c constant MAFPA3L \ Transceiver Personal Area Netw
+ $ff constant MAFPA3L_MAFPA3L \ MAC Personal Area Network ID l
+ 11c $ff bitmask: MAFPA3L.MAFPA3L \ MAC Personal Area Network ID l
+$11d constant MAFPA3H \ Transceiver Personal Area Netw
+ $ff constant MAFPA3H_MAFPA3H \ MAC Personal Area Network ID h
+ 11d $ff bitmask: MAFPA3H.MAFPA3H \ MAC Personal Area Network ID h
+$10c constant MAFCR0 \ Multiple Address Filter Config
+ $f0 constant MAFCR0_Res \ Reserved Bit
+ 10c $f0 bitmask: MAFCR0.Res \ Reserved Bit
+ $8 constant MAFCR0_MAF3EN \ Multiple Address Filter 3 Enab
+ 10c $8 bitmask: MAFCR0.MAF3EN \ Multiple Address Filter 3 Enab
+ $4 constant MAFCR0_MAF2EN \ Multiple Address Filter 2 Enab
+ 10c $4 bitmask: MAFCR0.MAF2EN \ Multiple Address Filter 2 Enab
+ $2 constant MAFCR0_MAF1EN \ Multiple Address Filter 1 Enab
+ 10c $2 bitmask: MAFCR0.MAF1EN \ Multiple Address Filter 1 Enab
+ $1 constant MAFCR0_MAF0EN \ Multiple Address Filter 0 Enab
+ 10c $1 bitmask: MAFCR0.MAF0EN \ Multiple Address Filter 0 Enab
+$10d constant MAFCR1 \ Multiple Address Filter Config
+ $80 constant MAFCR1_AACK_3_SET_PD \ Set Data Pending bit for addre
+ 10d $80 bitmask: MAFCR1.AACK_3_SET_PD \ Set Data Pending bit for addre
+ $40 constant MAFCR1_AACK_3_I_AM_COORD \ Enable PAN Coordinator mode fo
+ 10d $40 bitmask: MAFCR1.AACK_3_I_AM_COORD \ Enable PAN Coordinator mode fo
+ $20 constant MAFCR1_AACK_2_SET_PD \ Set Data Pending bit for addre
+ 10d $20 bitmask: MAFCR1.AACK_2_SET_PD \ Set Data Pending bit for addre
+ $10 constant MAFCR1_AACK_2_I_AM_COORD \ Enable PAN Coordinator mode fo
+ 10d $10 bitmask: MAFCR1.AACK_2_I_AM_COORD \ Enable PAN Coordinator mode fo
+ $8 constant MAFCR1_AACK_1_SET_PD \ Set Data Pending bit for addre
+ 10d $8 bitmask: MAFCR1.AACK_1_SET_PD \ Set Data Pending bit for addre
+ $4 constant MAFCR1_AACK_1_I_AM_COORD \ Enable PAN Coordinator mode fo
+ 10d $4 bitmask: MAFCR1.AACK_1_I_AM_COORD \ Enable PAN Coordinator mode fo
+ $2 constant MAFCR1_AACK_0_SET_PD \ Set Data Pending bit for addre
+ 10d $2 bitmask: MAFCR1.AACK_0_SET_PD \ Set Data Pending bit for addre
+ $1 constant MAFCR1_AACK_0_I_AM_COORD \ Enable PAN Coordinator mode fo
+ 10d $1 bitmask: MAFCR1.AACK_0_I_AM_COORD \ Enable PAN Coordinator mode fo
+$13c constant AES_CTRL \ AES Control Register
+ $80 constant AES_CTRL_AES_REQUEST \ Request AES Operation.
+ 13c $80 bitmask: AES_CTRL.AES_REQUEST \ Request AES Operation.
+ $40 constant AES_CTRL_Res \ Reserved Bit
+ 13c $40 bitmask: AES_CTRL.Res \ Reserved Bit
+ $20 constant AES_CTRL_AES_MODE \ Set AES Operation Mode
+ 13c $20 bitmask: AES_CTRL.AES_MODE \ Set AES Operation Mode
+ $10 constant AES_CTRL_Res \ Reserved Bit
+ 13c $10 bitmask: AES_CTRL.Res \ Reserved Bit
+ $8 constant AES_CTRL_AES_DIR \ Set AES Operation Direction
+ 13c $8 bitmask: AES_CTRL.AES_DIR \ Set AES Operation Direction
+ $4 constant AES_CTRL_AES_IM \ AES Interrupt Enable
+ 13c $4 bitmask: AES_CTRL.AES_IM \ AES Interrupt Enable
+ $3 constant AES_CTRL_Res \ Reserved Bit
+ 13c $3 bitmask: AES_CTRL.Res \ Reserved Bit
+$13d constant AES_STATUS \ AES Status Register
+ $80 constant AES_STATUS_AES_ER \ AES Operation Finished with Er
+ 13d $80 bitmask: AES_STATUS.AES_ER \ AES Operation Finished with Er
+ $7e constant AES_STATUS_Res \ Reserved
+ 13d $7e bitmask: AES_STATUS.Res \ Reserved
+ $1 constant AES_STATUS_AES_DONE \ AES Operation Finished with Su
+ 13d $1 bitmask: AES_STATUS.AES_DONE \ AES Operation Finished with Su
+$13e constant AES_STATE \ AES Plain and Cipher Text Buff
+ $ff constant AES_STATE_AES_STATE \ AES Plain and Cipher Text Buff
+ 13e $ff bitmask: AES_STATE.AES_STATE \ AES Plain and Cipher Text Buff
+$13f constant AES_KEY \ AES Encryption and Decryption
+ $ff constant AES_KEY_AES_KEY \ AES Encryption/Decryption Key
+ 13f $ff bitmask: AES_KEY.AES_KEY \ AES Encryption/Decryption Key
+$141 constant TRX_STATUS \ Transceiver Status Register
+ $80 constant TRX_STATUS_CCA_DONE \ CCA Algorithm Status
+ 141 $80 bitmask: TRX_STATUS.CCA_DONE \ CCA Algorithm Status
+ $40 constant TRX_STATUS_CCA_STATUS \ CCA Status Result
+ 141 $40 bitmask: TRX_STATUS.CCA_STATUS \ CCA Status Result
+ $20 constant TRX_STATUS_TST_STATUS \ Test mode status
+ 141 $20 bitmask: TRX_STATUS.TST_STATUS \ Test mode status
+ $1f constant TRX_STATUS_TRX_STATUS \ Transceiver Main Status
+ 141 $1f bitmask: TRX_STATUS.TRX_STATUS \ Transceiver Main Status
+$142 constant TRX_STATE \ Transceiver State Control Regi
+ $e0 constant TRX_STATE_TRAC_STATUS \ Transaction Status
+ 142 $e0 bitmask: TRX_STATE.TRAC_STATUS \ Transaction Status
+ $1f constant TRX_STATE_TRX_CMD \ State Control Command
+ 142 $1f bitmask: TRX_STATE.TRX_CMD \ State Control Command
+$143 constant TRX_CTRL_0 \ Reserved
+ $80 constant TRX_CTRL_0_Res7 \ Reserved
+ 143 $80 bitmask: TRX_CTRL_0.Res7 \ Reserved
+ $40 constant TRX_CTRL_0_PMU_EN \ Enable Phase Measurement Unit
+ 143 $40 bitmask: TRX_CTRL_0.PMU_EN \ Enable Phase Measurement Unit
+ $20 constant TRX_CTRL_0_PMU_START \ Start of Phase Measurement Uni
+ 143 $20 bitmask: TRX_CTRL_0.PMU_START \ Start of Phase Measurement Uni
+ $10 constant TRX_CTRL_0_PMU_IF_INV \ PMU IF Inverse
+ 143 $10 bitmask: TRX_CTRL_0.PMU_IF_INV \ PMU IF Inverse
+ $f constant TRX_CTRL_0_Res \ Reserved
+ 143 $f bitmask: TRX_CTRL_0.Res \ Reserved
+$144 constant TRX_CTRL_1 \ Transceiver Control Register 1
+ $80 constant TRX_CTRL_1_PA_EXT_EN \ External PA support enable
+ 144 $80 bitmask: TRX_CTRL_1.PA_EXT_EN \ External PA support enable
+ $40 constant TRX_CTRL_1_IRQ_2_EXT_EN \ Connect Frame Start IRQ to TC1
+ 144 $40 bitmask: TRX_CTRL_1.IRQ_2_EXT_EN \ Connect Frame Start IRQ to TC1
+ $20 constant TRX_CTRL_1_TX_AUTO_CRC_ON \ Enable Automatic CRC Calculati
+ 144 $20 bitmask: TRX_CTRL_1.TX_AUTO_CRC_ON \ Enable Automatic CRC Calculati
+ $10 constant TRX_CTRL_1_PLL_TX_FLT \ Enable PLL TX filter
+ 144 $10 bitmask: TRX_CTRL_1.PLL_TX_FLT \ Enable PLL TX filter
+ $f constant TRX_CTRL_1_Res \ Reserved
+ 144 $f bitmask: TRX_CTRL_1.Res \ Reserved
+$145 constant PHY_TX_PWR \ Transceiver Transmit Power Con
+ $f0 constant PHY_TX_PWR_Res \ Reserved
+ 145 $f0 bitmask: PHY_TX_PWR.Res \ Reserved
+ $f constant PHY_TX_PWR_TX_PWR \ Transmit Power Setting
+ 145 $f bitmask: PHY_TX_PWR.TX_PWR \ Transmit Power Setting
+$146 constant PHY_RSSI \ Receiver Signal Strength Indic
+ $80 constant PHY_RSSI_RX_CRC_VALID \ Received Frame CRC Status
+ 146 $80 bitmask: PHY_RSSI.RX_CRC_VALID \ Received Frame CRC Status
+ $60 constant PHY_RSSI_RND_VALUE \ Random Value
+ 146 $60 bitmask: PHY_RSSI.RND_VALUE \ Random Value
+ $1f constant PHY_RSSI_RSSI \ Receiver Signal Strength Indic
+ 146 $1f bitmask: PHY_RSSI.RSSI \ Receiver Signal Strength Indic
+$147 constant PHY_ED_LEVEL \ Transceiver Energy Detection L
+ $ff constant PHY_ED_LEVEL_ED_LEVEL \ Energy Detection Level
+ 147 $ff bitmask: PHY_ED_LEVEL.ED_LEVEL \ Energy Detection Level
+$148 constant PHY_CC_CCA \ Transceiver Clear Channel Asse
+ $80 constant PHY_CC_CCA_CCA_REQUEST \ Manual CCA Measurement Request
+ 148 $80 bitmask: PHY_CC_CCA.CCA_REQUEST \ Manual CCA Measurement Request
+ $60 constant PHY_CC_CCA_CCA_MODE \ Select CCA Measurement Mode
+ 148 $60 bitmask: PHY_CC_CCA.CCA_MODE \ Select CCA Measurement Mode
+ $1f constant PHY_CC_CCA_CHANNEL \ RX/TX Channel Selection
+ 148 $1f bitmask: PHY_CC_CCA.CHANNEL \ RX/TX Channel Selection
+$149 constant CCA_THRES \ Transceiver CCA Threshold Sett
+ $f0 constant CCA_THRES_CCA_CS_THRES \ CS Threshold Level for CCA Mea
+ 149 $f0 bitmask: CCA_THRES.CCA_CS_THRES \ CS Threshold Level for CCA Mea
+ $f constant CCA_THRES_CCA_ED_THRES \ ED Threshold Level for CCA Mea
+ 149 $f bitmask: CCA_THRES.CCA_ED_THRES \ ED Threshold Level for CCA Mea
+$14a constant RX_CTRL \ Transceiver Receive Control Re
+ $f constant RX_CTRL_PDT_THRES \ Receiver Sensitivity Control
+ 14a $f bitmask: RX_CTRL.PDT_THRES \ Receiver Sensitivity Control
+$14b constant SFD_VALUE \ Start of Frame Delimiter Value
+ $ff constant SFD_VALUE_SFD_VALUE \ Start of Frame Delimiter Value
+ 14b $ff bitmask: SFD_VALUE.SFD_VALUE \ Start of Frame Delimiter Value
+$14c constant TRX_CTRL_2 \ Transceiver Control Register 2
+ $80 constant TRX_CTRL_2_RX_SAFE_MODE \ RX Safe Mode
+ 14c $80 bitmask: TRX_CTRL_2.RX_SAFE_MODE \ RX Safe Mode
+ $7c constant TRX_CTRL_2_Res \ Reserved
+ 14c $7c bitmask: TRX_CTRL_2.Res \ Reserved
+ $3 constant TRX_CTRL_2_OQPSK_DATA_RATE \ Data Rate Selection
+ 14c $3 bitmask: TRX_CTRL_2.OQPSK_DATA_RATE \ Data Rate Selection
+$14d constant ANT_DIV \ Antenna Diversity Control Regi
+ $80 constant ANT_DIV_ANT_SEL \ Antenna Diversity Antenna Stat
+ 14d $80 bitmask: ANT_DIV.ANT_SEL \ Antenna Diversity Antenna Stat
+ $70 constant ANT_DIV_Res \ Reserved
+ 14d $70 bitmask: ANT_DIV.Res \ Reserved
+ $8 constant ANT_DIV_ANT_DIV_EN \ Enable Antenna Diversity
+ 14d $8 bitmask: ANT_DIV.ANT_DIV_EN \ Enable Antenna Diversity
+ $4 constant ANT_DIV_ANT_EXT_SW_EN \ Enable External Antenna Switch
+ 14d $4 bitmask: ANT_DIV.ANT_EXT_SW_EN \ Enable External Antenna Switch
+ $3 constant ANT_DIV_ANT_CTRL \ Static Antenna Diversity Switc
+ 14d $3 bitmask: ANT_DIV.ANT_CTRL \ Static Antenna Diversity Switc
+$14e constant IRQ_MASK \ Transceiver Interrupt Enable R
+ $80 constant IRQ_MASK_AWAKE_EN \ Awake Interrupt Enable
+ 14e $80 bitmask: IRQ_MASK.AWAKE_EN \ Awake Interrupt Enable
+ $40 constant IRQ_MASK_TX_END_EN \ TX_END Interrupt Enable
+ 14e $40 bitmask: IRQ_MASK.TX_END_EN \ TX_END Interrupt Enable
+ $20 constant IRQ_MASK_AMI_EN \ Address Match Interrupt Enable
+ 14e $20 bitmask: IRQ_MASK.AMI_EN \ Address Match Interrupt Enable
+ $10 constant IRQ_MASK_CCA_ED_DONE_EN \ End of ED Measurement Interrup
+ 14e $10 bitmask: IRQ_MASK.CCA_ED_DONE_EN \ End of ED Measurement Interrup
+ $8 constant IRQ_MASK_RX_END_EN \ RX_END Interrupt Enable
+ 14e $8 bitmask: IRQ_MASK.RX_END_EN \ RX_END Interrupt Enable
+ $4 constant IRQ_MASK_RX_START_EN \ RX_START Interrupt Enable
+ 14e $4 bitmask: IRQ_MASK.RX_START_EN \ RX_START Interrupt Enable
+ $2 constant IRQ_MASK_PLL_UNLOCK_EN \ PLL Unlock Interrupt Enable
+ 14e $2 bitmask: IRQ_MASK.PLL_UNLOCK_EN \ PLL Unlock Interrupt Enable
+ $1 constant IRQ_MASK_PLL_LOCK_EN \ PLL Lock Interrupt Enable
+ 14e $1 bitmask: IRQ_MASK.PLL_LOCK_EN \ PLL Lock Interrupt Enable
+$14f constant IRQ_STATUS \ Transceiver Interrupt Status R
+ $80 constant IRQ_STATUS_AWAKE \ Awake Interrupt Status
+ 14f $80 bitmask: IRQ_STATUS.AWAKE \ Awake Interrupt Status
+ $40 constant IRQ_STATUS_TX_END \ TX_END Interrupt Status
+ 14f $40 bitmask: IRQ_STATUS.TX_END \ TX_END Interrupt Status
+ $20 constant IRQ_STATUS_AMI \ Address Match Interrupt Status
+ 14f $20 bitmask: IRQ_STATUS.AMI \ Address Match Interrupt Status
+ $10 constant IRQ_STATUS_CCA_ED_DONE \ End of ED Measurement Interrup
+ 14f $10 bitmask: IRQ_STATUS.CCA_ED_DONE \ End of ED Measurement Interrup
+ $8 constant IRQ_STATUS_RX_END \ RX_END Interrupt Status
+ 14f $8 bitmask: IRQ_STATUS.RX_END \ RX_END Interrupt Status
+ $4 constant IRQ_STATUS_RX_START \ RX_START Interrupt Status
+ 14f $4 bitmask: IRQ_STATUS.RX_START \ RX_START Interrupt Status
+ $2 constant IRQ_STATUS_PLL_UNLOCK \ PLL Unlock Interrupt Status
+ 14f $2 bitmask: IRQ_STATUS.PLL_UNLOCK \ PLL Unlock Interrupt Status
+ $1 constant IRQ_STATUS_PLL_LOCK \ PLL Lock Interrupt Status
+ 14f $1 bitmask: IRQ_STATUS.PLL_LOCK \ PLL Lock Interrupt Status
+$be constant IRQ_MASK1 \ Transceiver Interrupt Enable R
+ $e0 constant IRQ_MASK1_Res \ Reserved Bit
+ be $e0 bitmask: IRQ_MASK1.Res \ Reserved Bit
+ $10 constant IRQ_MASK1_MAF_3_AMI_EN \ Address Match Interrupt enable
+ be $10 bitmask: IRQ_MASK1.MAF_3_AMI_EN \ Address Match Interrupt enable
+ $8 constant IRQ_MASK1_MAF_2_AMI_EN \ Address Match Interrupt enable
+ be $8 bitmask: IRQ_MASK1.MAF_2_AMI_EN \ Address Match Interrupt enable
+ $4 constant IRQ_MASK1_MAF_1_AMI_EN \ Address Match Interrupt enable
+ be $4 bitmask: IRQ_MASK1.MAF_1_AMI_EN \ Address Match Interrupt enable
+ $2 constant IRQ_MASK1_MAF_0_AMI_EN \ Address Match Interrupt enable
+ be $2 bitmask: IRQ_MASK1.MAF_0_AMI_EN \ Address Match Interrupt enable
+ $1 constant IRQ_MASK1_TX_START_EN \ Transmit Start Interrupt enabl
+ be $1 bitmask: IRQ_MASK1.TX_START_EN \ Transmit Start Interrupt enabl
+$bf constant IRQ_STATUS1 \ Transceiver Interrupt Status R
+ $e0 constant IRQ_STATUS1_Res \ Reserved Bit
+ bf $e0 bitmask: IRQ_STATUS1.Res \ Reserved Bit
+ $10 constant IRQ_STATUS1_MAF_3_AMI \ Address Match Interrupt Status
+ bf $10 bitmask: IRQ_STATUS1.MAF_3_AMI \ Address Match Interrupt Status
+ $8 constant IRQ_STATUS1_MAF_2_AMI \ Address Match Interrupt Status
+ bf $8 bitmask: IRQ_STATUS1.MAF_2_AMI \ Address Match Interrupt Status
+ $4 constant IRQ_STATUS1_MAF_1_AMI \ Address Match Interrupt Status
+ bf $4 bitmask: IRQ_STATUS1.MAF_1_AMI \ Address Match Interrupt Status
+ $2 constant IRQ_STATUS1_MAF_0_AMI \ Address Match Interrupt Status
+ bf $2 bitmask: IRQ_STATUS1.MAF_0_AMI \ Address Match Interrupt Status
+ $1 constant IRQ_STATUS1_TX_START \ Transmit Start Interrupt Statu
+ bf $1 bitmask: IRQ_STATUS1.TX_START \ Transmit Start Interrupt Statu
+$150 constant VREG_CTRL \ Voltage Regulator Control and
+ $80 constant VREG_CTRL_AVREG_EXT \ Use External AVDD Regulator
+ 150 $80 bitmask: VREG_CTRL.AVREG_EXT \ Use External AVDD Regulator
+ $40 constant VREG_CTRL_AVDD_OK \ AVDD Supply Voltage Valid
+ 150 $40 bitmask: VREG_CTRL.AVDD_OK \ AVDD Supply Voltage Valid
+ $8 constant VREG_CTRL_DVREG_EXT \ Use External DVDD Regulator
+ 150 $8 bitmask: VREG_CTRL.DVREG_EXT \ Use External DVDD Regulator
+ $4 constant VREG_CTRL_DVDD_OK \ DVDD Supply Voltage Valid
+ 150 $4 bitmask: VREG_CTRL.DVDD_OK \ DVDD Supply Voltage Valid
+$151 constant BATMON \ Battery Monitor Control and St
+ $80 constant BATMON_BAT_LOW \ Battery Monitor Interrupt Stat
+ 151 $80 bitmask: BATMON.BAT_LOW \ Battery Monitor Interrupt Stat
+ $40 constant BATMON_BAT_LOW_EN \ Battery Monitor Interrupt Enab
+ 151 $40 bitmask: BATMON.BAT_LOW_EN \ Battery Monitor Interrupt Enab
+ $20 constant BATMON_BATMON_OK \ Battery Monitor Status
+ 151 $20 bitmask: BATMON.BATMON_OK \ Battery Monitor Status
+ $10 constant BATMON_BATMON_HR \ Battery Monitor Voltage Range
+ 151 $10 bitmask: BATMON.BATMON_HR \ Battery Monitor Voltage Range
+ $f constant BATMON_BATMON_VTH \ Battery Monitor Threshold Volt
+ 151 $f bitmask: BATMON.BATMON_VTH \ Battery Monitor Threshold Volt
+$152 constant XOSC_CTRL \ Crystal Oscillator Control Reg
+ $f0 constant XOSC_CTRL_XTAL_MODE \ Crystal Oscillator Operating M
+ 152 $f0 bitmask: XOSC_CTRL.XTAL_MODE \ Crystal Oscillator Operating M
+ $f constant XOSC_CTRL_XTAL_TRIM \ Crystal Oscillator Load Capaci
+ 152 $f bitmask: XOSC_CTRL.XTAL_TRIM \ Crystal Oscillator Load Capaci
+$153 constant CC_CTRL_0 \ Channel Control Register 0
+ $ff constant CC_CTRL_0_CC_NUMBER \ Channel Number
+ 153 $ff bitmask: CC_CTRL_0.CC_NUMBER \ Channel Number
+$154 constant CC_CTRL_1 \ Channel Control Register 1
+ $f constant CC_CTRL_1_CC_BAND \ Channel Band
+ 154 $f bitmask: CC_CTRL_1.CC_BAND \ Channel Band
+$155 constant RX_SYN \ Transceiver Receiver Sensitivi
+ $80 constant RX_SYN_RX_PDT_DIS \ Prevent Frame Reception
+ 155 $80 bitmask: RX_SYN.RX_PDT_DIS \ Prevent Frame Reception
+ $40 constant RX_SYN_RX_OVERRIDE \ Receiver Override Function
+ 155 $40 bitmask: RX_SYN.RX_OVERRIDE \ Receiver Override Function
+ $30 constant RX_SYN_Res \ Reserved
+ 155 $30 bitmask: RX_SYN.Res \ Reserved
+ $f constant RX_SYN_RX_PDT_LEVEL \ Reduce Receiver Sensitivity
+ 155 $f bitmask: RX_SYN.RX_PDT_LEVEL \ Reduce Receiver Sensitivity
+$156 constant TRX_RPC \ Transceiver Reduced Power Cons
+ $c0 constant TRX_RPC_RX_RPC_CTRL \ Smart Receiving Mode Timing
+ 156 $c0 bitmask: TRX_RPC.RX_RPC_CTRL \ Smart Receiving Mode Timing
+ $20 constant TRX_RPC_RX_RPC_EN \ Reciver Smart Receiving Mode E
+ 156 $20 bitmask: TRX_RPC.RX_RPC_EN \ Reciver Smart Receiving Mode E
+ $10 constant TRX_RPC_PDT_RPC_EN \ Smart Receiving Mode Reduced S
+ 156 $10 bitmask: TRX_RPC.PDT_RPC_EN \ Smart Receiving Mode Reduced S
+ $8 constant TRX_RPC_PLL_RPC_EN \ PLL Smart Receiving Mode Enabl
+ 156 $8 bitmask: TRX_RPC.PLL_RPC_EN \ PLL Smart Receiving Mode Enabl
+ $4 constant TRX_RPC_Res0 \ Reserved
+ 156 $4 bitmask: TRX_RPC.Res0 \ Reserved
+ $2 constant TRX_RPC_IPAN_RPC_EN \ Smart Receiving Mode IPAN Hand
+ 156 $2 bitmask: TRX_RPC.IPAN_RPC_EN \ Smart Receiving Mode IPAN Hand
+ $1 constant TRX_RPC_XAH_RPC_EN \ Smart Receiving in Extended Op
+ 156 $1 bitmask: TRX_RPC.XAH_RPC_EN \ Smart Receiving in Extended Op
+$157 constant XAH_CTRL_1 \ Transceiver Acknowledgment Fra
+ $c0 constant XAH_CTRL_1_Res \ Reserved Bit
+ 157 $c0 bitmask: XAH_CTRL_1.Res \ Reserved Bit
+ $20 constant XAH_CTRL_1_AACK_FLTR_RES_FT \ Filter Reserved Frames
+ 157 $20 bitmask: XAH_CTRL_1.AACK_FLTR_RES_FT \ Filter Reserved Frames
+ $10 constant XAH_CTRL_1_AACK_UPLD_RES_FT \ Process Reserved Frames
+ 157 $10 bitmask: XAH_CTRL_1.AACK_UPLD_RES_FT \ Process Reserved Frames
+ $8 constant XAH_CTRL_1_Res \ Reserved Bit
+ 157 $8 bitmask: XAH_CTRL_1.Res \ Reserved Bit
+ $4 constant XAH_CTRL_1_AACK_ACK_TIME \ Reduce Acknowledgment Time
+ 157 $4 bitmask: XAH_CTRL_1.AACK_ACK_TIME \ Reduce Acknowledgment Time
+ $2 constant XAH_CTRL_1_AACK_PROM_MODE \ Enable Promiscuous Mode
+ 157 $2 bitmask: XAH_CTRL_1.AACK_PROM_MODE \ Enable Promiscuous Mode
+ $1 constant XAH_CTRL_1_Res \ Reserved Bit
+ 157 $1 bitmask: XAH_CTRL_1.Res \ Reserved Bit
+$158 constant FTN_CTRL \ Transceiver Filter Tuning Cont
+ $80 constant FTN_CTRL_FTN_START \ Start Calibration Loop of Filt
+ 158 $80 bitmask: FTN_CTRL.FTN_START \ Start Calibration Loop of Filt
+$15a constant PLL_CF \ Transceiver Center Frequency C
+ $80 constant PLL_CF_PLL_CF_START \ Start Center Frequency Calibra
+ 15a $80 bitmask: PLL_CF.PLL_CF_START \ Start Center Frequency Calibra
+$15b constant PLL_DCU \ Transceiver Delay Cell Calibra
+ $80 constant PLL_DCU_PLL_DCU_START \ Start Delay Cell Calibration
+ 15b $80 bitmask: PLL_DCU.PLL_DCU_START \ Start Delay Cell Calibration
+$15c constant PART_NUM \ Device Identification Register
+ $ff constant PART_NUM_PART_NUM \ Part Number
+ 15c $ff bitmask: PART_NUM.PART_NUM \ Part Number
+$15d constant VERSION_NUM \ Device Identification Register
+ $ff constant VERSION_NUM_VERSION_NUM \ Version Number
+ 15d $ff bitmask: VERSION_NUM.VERSION_NUM \ Version Number
+$15e constant MAN_ID_0 \ Device Identification Register
+ $80 constant MAN_ID_0_MAN_ID_07 \ Manufacturer ID (Low Byte)
+ 15e $80 bitmask: MAN_ID_0.MAN_ID_07 \ Manufacturer ID (Low Byte)
+ $40 constant MAN_ID_0_MAN_ID_06 \ Manufacturer ID (Low Byte)
+ 15e $40 bitmask: MAN_ID_0.MAN_ID_06 \ Manufacturer ID (Low Byte)
+ $20 constant MAN_ID_0_MAN_ID_05 \ Manufacturer ID (Low Byte)
+ 15e $20 bitmask: MAN_ID_0.MAN_ID_05 \ Manufacturer ID (Low Byte)
+ $10 constant MAN_ID_0_MAN_ID_04 \ Manufacturer ID (Low Byte)
+ 15e $10 bitmask: MAN_ID_0.MAN_ID_04 \ Manufacturer ID (Low Byte)
+ $8 constant MAN_ID_0_MAN_ID_03 \ Manufacturer ID (Low Byte)
+ 15e $8 bitmask: MAN_ID_0.MAN_ID_03 \ Manufacturer ID (Low Byte)
+ $4 constant MAN_ID_0_MAN_ID_02 \ Manufacturer ID (Low Byte)
+ 15e $4 bitmask: MAN_ID_0.MAN_ID_02 \ Manufacturer ID (Low Byte)
+ $2 constant MAN_ID_0_MAN_ID_01 \ Manufacturer ID (Low Byte)
+ 15e $2 bitmask: MAN_ID_0.MAN_ID_01 \ Manufacturer ID (Low Byte)
+ $1 constant MAN_ID_0_MAN_ID_00 \ Manufacturer ID (Low Byte)
+ 15e $1 bitmask: MAN_ID_0.MAN_ID_00 \ Manufacturer ID (Low Byte)
+$15f constant MAN_ID_1 \ Device Identification Register
+ $ff constant MAN_ID_1_MAN_ID_ \ Manufacturer ID (High Byte)
+ 15f $ff bitmask: MAN_ID_1.MAN_ID_ \ Manufacturer ID (High Byte)
+$160 constant SHORT_ADDR_0 \ Transceiver MAC Short Address
+ $80 constant SHORT_ADDR_0_SHORT_ADDR_07 \ MAC Short Address
+ 160 $80 bitmask: SHORT_ADDR_0.SHORT_ADDR_07 \ MAC Short Address
+ $40 constant SHORT_ADDR_0_SHORT_ADDR_06 \ MAC Short Address
+ 160 $40 bitmask: SHORT_ADDR_0.SHORT_ADDR_06 \ MAC Short Address
+ $20 constant SHORT_ADDR_0_SHORT_ADDR_05 \ MAC Short Address
+ 160 $20 bitmask: SHORT_ADDR_0.SHORT_ADDR_05 \ MAC Short Address
+ $10 constant SHORT_ADDR_0_SHORT_ADDR_04 \ MAC Short Address
+ 160 $10 bitmask: SHORT_ADDR_0.SHORT_ADDR_04 \ MAC Short Address
+ $8 constant SHORT_ADDR_0_SHORT_ADDR_03 \ MAC Short Address
+ 160 $8 bitmask: SHORT_ADDR_0.SHORT_ADDR_03 \ MAC Short Address
+ $4 constant SHORT_ADDR_0_SHORT_ADDR_02 \ MAC Short Address
+ 160 $4 bitmask: SHORT_ADDR_0.SHORT_ADDR_02 \ MAC Short Address
+ $2 constant SHORT_ADDR_0_SHORT_ADDR_01 \ MAC Short Address
+ 160 $2 bitmask: SHORT_ADDR_0.SHORT_ADDR_01 \ MAC Short Address
+ $1 constant SHORT_ADDR_0_SHORT_ADDR_00 \ MAC Short Address
+ 160 $1 bitmask: SHORT_ADDR_0.SHORT_ADDR_00 \ MAC Short Address
+$161 constant SHORT_ADDR_1 \ Transceiver MAC Short Address
+ $ff constant SHORT_ADDR_1_SHORT_ADDR_ \ MAC Short Address
+ 161 $ff bitmask: SHORT_ADDR_1.SHORT_ADDR_ \ MAC Short Address
+$162 constant PAN_ID_0 \ Transceiver Personal Area Netw
+ $80 constant PAN_ID_0_PAN_ID_07 \ MAC Personal Area Network ID
+ 162 $80 bitmask: PAN_ID_0.PAN_ID_07 \ MAC Personal Area Network ID
+ $40 constant PAN_ID_0_PAN_ID_06 \ MAC Personal Area Network ID
+ 162 $40 bitmask: PAN_ID_0.PAN_ID_06 \ MAC Personal Area Network ID
+ $20 constant PAN_ID_0_PAN_ID_05 \ MAC Personal Area Network ID
+ 162 $20 bitmask: PAN_ID_0.PAN_ID_05 \ MAC Personal Area Network ID
+ $10 constant PAN_ID_0_PAN_ID_04 \ MAC Personal Area Network ID
+ 162 $10 bitmask: PAN_ID_0.PAN_ID_04 \ MAC Personal Area Network ID
+ $8 constant PAN_ID_0_PAN_ID_03 \ MAC Personal Area Network ID
+ 162 $8 bitmask: PAN_ID_0.PAN_ID_03 \ MAC Personal Area Network ID
+ $4 constant PAN_ID_0_PAN_ID_02 \ MAC Personal Area Network ID
+ 162 $4 bitmask: PAN_ID_0.PAN_ID_02 \ MAC Personal Area Network ID
+ $2 constant PAN_ID_0_PAN_ID_01 \ MAC Personal Area Network ID
+ 162 $2 bitmask: PAN_ID_0.PAN_ID_01 \ MAC Personal Area Network ID
+ $1 constant PAN_ID_0_PAN_ID_00 \ MAC Personal Area Network ID
+ 162 $1 bitmask: PAN_ID_0.PAN_ID_00 \ MAC Personal Area Network ID
+$163 constant PAN_ID_1 \ Transceiver Personal Area Netw
+ $ff constant PAN_ID_1_PAN_ID_ \ MAC Personal Area Network ID
+ 163 $ff bitmask: PAN_ID_1.PAN_ID_ \ MAC Personal Area Network ID
+$164 constant IEEE_ADDR_0 \ Transceiver MAC IEEE Address R
+ $80 constant IEEE_ADDR_0_IEEE_ADDR_07 \ MAC IEEE Address
+ 164 $80 bitmask: IEEE_ADDR_0.IEEE_ADDR_07 \ MAC IEEE Address
+ $40 constant IEEE_ADDR_0_IEEE_ADDR_06 \ MAC IEEE Address
+ 164 $40 bitmask: IEEE_ADDR_0.IEEE_ADDR_06 \ MAC IEEE Address
+ $20 constant IEEE_ADDR_0_IEEE_ADDR_05 \ MAC IEEE Address
+ 164 $20 bitmask: IEEE_ADDR_0.IEEE_ADDR_05 \ MAC IEEE Address
+ $10 constant IEEE_ADDR_0_IEEE_ADDR_04 \ MAC IEEE Address
+ 164 $10 bitmask: IEEE_ADDR_0.IEEE_ADDR_04 \ MAC IEEE Address
+ $8 constant IEEE_ADDR_0_IEEE_ADDR_03 \ MAC IEEE Address
+ 164 $8 bitmask: IEEE_ADDR_0.IEEE_ADDR_03 \ MAC IEEE Address
+ $4 constant IEEE_ADDR_0_IEEE_ADDR_02 \ MAC IEEE Address
+ 164 $4 bitmask: IEEE_ADDR_0.IEEE_ADDR_02 \ MAC IEEE Address
+ $2 constant IEEE_ADDR_0_IEEE_ADDR_01 \ MAC IEEE Address
+ 164 $2 bitmask: IEEE_ADDR_0.IEEE_ADDR_01 \ MAC IEEE Address
+ $1 constant IEEE_ADDR_0_IEEE_ADDR_00 \ MAC IEEE Address
+ 164 $1 bitmask: IEEE_ADDR_0.IEEE_ADDR_00 \ MAC IEEE Address
+$165 constant IEEE_ADDR_1 \ Transceiver MAC IEEE Address R
+ $ff constant IEEE_ADDR_1_IEEE_ADDR_ \ MAC IEEE Address
+ 165 $ff bitmask: IEEE_ADDR_1.IEEE_ADDR_ \ MAC IEEE Address
+$166 constant IEEE_ADDR_2 \ Transceiver MAC IEEE Address R
+ $ff constant IEEE_ADDR_2_IEEE_ADDR_ \ MAC IEEE Address
+ 166 $ff bitmask: IEEE_ADDR_2.IEEE_ADDR_ \ MAC IEEE Address
+$167 constant IEEE_ADDR_3 \ Transceiver MAC IEEE Address R
+ $ff constant IEEE_ADDR_3_IEEE_ADDR_ \ MAC IEEE Address
+ 167 $ff bitmask: IEEE_ADDR_3.IEEE_ADDR_ \ MAC IEEE Address
+$168 constant IEEE_ADDR_4 \ Transceiver MAC IEEE Address R
+ $ff constant IEEE_ADDR_4_IEEE_ADDR_ \ MAC IEEE Address
+ 168 $ff bitmask: IEEE_ADDR_4.IEEE_ADDR_ \ MAC IEEE Address
+$169 constant IEEE_ADDR_5 \ Transceiver MAC IEEE Address R
+ $ff constant IEEE_ADDR_5_IEEE_ADDR_ \ MAC IEEE Address
+ 169 $ff bitmask: IEEE_ADDR_5.IEEE_ADDR_ \ MAC IEEE Address
+$16a constant IEEE_ADDR_6 \ Transceiver MAC IEEE Address R
+ $ff constant IEEE_ADDR_6_IEEE_ADDR_ \ MAC IEEE Address
+ 16a $ff bitmask: IEEE_ADDR_6.IEEE_ADDR_ \ MAC IEEE Address
+$16b constant IEEE_ADDR_7 \ Transceiver MAC IEEE Address R
+ $ff constant IEEE_ADDR_7_IEEE_ADDR_ \ MAC IEEE Address
+ 16b $ff bitmask: IEEE_ADDR_7.IEEE_ADDR_ \ MAC IEEE Address
+$16c constant XAH_CTRL_0 \ Transceiver Extended Operating
+ $f0 constant XAH_CTRL_0_MAX_FRAME_RETRIES \ Maximum Number of Frame Re-tra
+ 16c $f0 bitmask: XAH_CTRL_0.MAX_FRAME_RETRIES \ Maximum Number of Frame Re-tra
+ $e constant XAH_CTRL_0_MAX_CSMA_RETRIES \ Maximum Number of CSMA-CA Proc
+ 16c $e bitmask: XAH_CTRL_0.MAX_CSMA_RETRIES \ Maximum Number of CSMA-CA Proc
+ $1 constant XAH_CTRL_0_SLOTTED_OPERATION \ Set Slotted Acknowledgment
+ 16c $1 bitmask: XAH_CTRL_0.SLOTTED_OPERATION \ Set Slotted Acknowledgment
+$16d constant CSMA_SEED_0 \ Transceiver CSMA-CA Random Num
+ $80 constant CSMA_SEED_0_CSMA_SEED_07 \ Seed Value for CSMA Random Num
+ 16d $80 bitmask: CSMA_SEED_0.CSMA_SEED_07 \ Seed Value for CSMA Random Num
+ $40 constant CSMA_SEED_0_CSMA_SEED_06 \ Seed Value for CSMA Random Num
+ 16d $40 bitmask: CSMA_SEED_0.CSMA_SEED_06 \ Seed Value for CSMA Random Num
+ $20 constant CSMA_SEED_0_CSMA_SEED_05 \ Seed Value for CSMA Random Num
+ 16d $20 bitmask: CSMA_SEED_0.CSMA_SEED_05 \ Seed Value for CSMA Random Num
+ $10 constant CSMA_SEED_0_CSMA_SEED_04 \ Seed Value for CSMA Random Num
+ 16d $10 bitmask: CSMA_SEED_0.CSMA_SEED_04 \ Seed Value for CSMA Random Num
+ $8 constant CSMA_SEED_0_CSMA_SEED_03 \ Seed Value for CSMA Random Num
+ 16d $8 bitmask: CSMA_SEED_0.CSMA_SEED_03 \ Seed Value for CSMA Random Num
+ $4 constant CSMA_SEED_0_CSMA_SEED_02 \ Seed Value for CSMA Random Num
+ 16d $4 bitmask: CSMA_SEED_0.CSMA_SEED_02 \ Seed Value for CSMA Random Num
+ $2 constant CSMA_SEED_0_CSMA_SEED_01 \ Seed Value for CSMA Random Num
+ 16d $2 bitmask: CSMA_SEED_0.CSMA_SEED_01 \ Seed Value for CSMA Random Num
+ $1 constant CSMA_SEED_0_CSMA_SEED_00 \ Seed Value for CSMA Random Num
+ 16d $1 bitmask: CSMA_SEED_0.CSMA_SEED_00 \ Seed Value for CSMA Random Num
+$16e constant CSMA_SEED_1 \ Transceiver Acknowledgment Fra
+ $c0 constant CSMA_SEED_1_AACK_FVN_MODE \ Acknowledgment Frame Filter Mo
+ 16e $c0 bitmask: CSMA_SEED_1.AACK_FVN_MODE \ Acknowledgment Frame Filter Mo
+ $20 constant CSMA_SEED_1_AACK_SET_PD \ Set Frame Pending Sub-field
+ 16e $20 bitmask: CSMA_SEED_1.AACK_SET_PD \ Set Frame Pending Sub-field
+ $10 constant CSMA_SEED_1_AACK_DIS_ACK \ Disable Acknowledgment Frame T
+ 16e $10 bitmask: CSMA_SEED_1.AACK_DIS_ACK \ Disable Acknowledgment Frame T
+ $8 constant CSMA_SEED_1_AACK_I_AM_COORD \ Set Personal Area Network Coor
+ 16e $8 bitmask: CSMA_SEED_1.AACK_I_AM_COORD \ Set Personal Area Network Coor
+ $7 constant CSMA_SEED_1_CSMA_SEED_1 \ Seed Value for CSMA Random Num
+ 16e $7 bitmask: CSMA_SEED_1.CSMA_SEED_1 \ Seed Value for CSMA Random Num
+$16f constant CSMA_BE \ Transceiver CSMA-CA Back-off E
+ $f0 constant CSMA_BE_MAX_BE \ Maximum Back-off Exponent
+ 16f $f0 bitmask: CSMA_BE.MAX_BE \ Maximum Back-off Exponent
+ $f constant CSMA_BE_MIN_BE \ Minimum Back-off Exponent
+ 16f $f bitmask: CSMA_BE.MIN_BE \ Minimum Back-off Exponent
+$176 constant TST_CTRL_DIGI \ Transceiver Digital Test Contr
+ $f constant TST_CTRL_DIGI_TST_CTRL_DIG \ Digital Test Controller Regist
+ 176 $f bitmask: TST_CTRL_DIGI.TST_CTRL_DIG \ Digital Test Controller Regist
+$17b constant TST_RX_LENGTH \ Transceiver Received Frame Len
+ $ff constant TST_RX_LENGTH_RX_LENGTH \ Received Frame Length
+ 17b $ff bitmask: TST_RX_LENGTH.RX_LENGTH \ Received Frame Length
+$180 constant TRXFBST \ Start of frame buffer
+$1ff constant TRXFBEND \ End of frame buffer
+\ SYMCNT
+$fc constant SCTSTRHH \ Symbol Counter Transmit Frame
+ $ff constant SCTSTRHH_SCTSTRHH \ Symbol Counter Transmit Frame
+ fc $ff bitmask: SCTSTRHH.SCTSTRHH \ Symbol Counter Transmit Frame
+$fb constant SCTSTRHL \ Symbol Counter Transmit Frame
+ $ff constant SCTSTRHL_SCTSTRHL \ Symbol Counter Transmit Frame
+ fb $ff bitmask: SCTSTRHL.SCTSTRHL \ Symbol Counter Transmit Frame
+$fa constant SCTSTRLH \ Symbol Counter Transmit Frame
+ $ff constant SCTSTRLH_SCTSTRLH \ Symbol Counter Transmit Frame
+ fa $ff bitmask: SCTSTRLH.SCTSTRLH \ Symbol Counter Transmit Frame
+$f9 constant SCTSTRLL \ Symbol Counter Transmit Frame
+ $ff constant SCTSTRLL_SCTSTRLL \ Symbol Counter Transmit Frame
+ f9 $ff bitmask: SCTSTRLL.SCTSTRLL \ Symbol Counter Transmit Frame
+$f8 constant SCOCR1HH \ Symbol Counter Output Compare
+ $ff constant SCOCR1HH_SCOCR1HH \ Symbol Counter Output Compare
+ f8 $ff bitmask: SCOCR1HH.SCOCR1HH \ Symbol Counter Output Compare
+$f7 constant SCOCR1HL \ Symbol Counter Output Compare
+ $ff constant SCOCR1HL_SCOCR1HL \ Symbol Counter Output Compare
+ f7 $ff bitmask: SCOCR1HL.SCOCR1HL \ Symbol Counter Output Compare
+$f6 constant SCOCR1LH \ Symbol Counter Output Compare
+ $ff constant SCOCR1LH_SCOCR1LH \ Symbol Counter Output Compare
+ f6 $ff bitmask: SCOCR1LH.SCOCR1LH \ Symbol Counter Output Compare
+$f5 constant SCOCR1LL \ Symbol Counter Output Compare
+ $ff constant SCOCR1LL_SCOCR1LL \ Symbol Counter Output Compare
+ f5 $ff bitmask: SCOCR1LL.SCOCR1LL \ Symbol Counter Output Compare
+$f4 constant SCOCR2HH \ Symbol Counter Output Compare
+ $ff constant SCOCR2HH_SCOCR2HH \ Symbol Counter Output Compare
+ f4 $ff bitmask: SCOCR2HH.SCOCR2HH \ Symbol Counter Output Compare
+$f3 constant SCOCR2HL \ Symbol Counter Output Compare
+ $ff constant SCOCR2HL_SCOCR2HL \ Symbol Counter Output Compare
+ f3 $ff bitmask: SCOCR2HL.SCOCR2HL \ Symbol Counter Output Compare
+$f2 constant SCOCR2LH \ Symbol Counter Output Compare
+ $ff constant SCOCR2LH_SCOCR2LH \ Symbol Counter Output Compare
+ f2 $ff bitmask: SCOCR2LH.SCOCR2LH \ Symbol Counter Output Compare
+$f1 constant SCOCR2LL \ Symbol Counter Output Compare
+ $ff constant SCOCR2LL_SCOCR2LL \ Symbol Counter Output Compare
+ f1 $ff bitmask: SCOCR2LL.SCOCR2LL \ Symbol Counter Output Compare
+$f0 constant SCOCR3HH \ Symbol Counter Output Compare
+ $ff constant SCOCR3HH_SCOCR3HH \ Symbol Counter Output Compare
+ f0 $ff bitmask: SCOCR3HH.SCOCR3HH \ Symbol Counter Output Compare
+$ef constant SCOCR3HL \ Symbol Counter Output Compare
+ $ff constant SCOCR3HL_SCOCR3HL \ Symbol Counter Output Compare
+ ef $ff bitmask: SCOCR3HL.SCOCR3HL \ Symbol Counter Output Compare
+$ee constant SCOCR3LH \ Symbol Counter Output Compare
+ $ff constant SCOCR3LH_SCOCR3LH \ Symbol Counter Output Compare
+ ee $ff bitmask: SCOCR3LH.SCOCR3LH \ Symbol Counter Output Compare
+$ed constant SCOCR3LL \ Symbol Counter Output Compare
+ $ff constant SCOCR3LL_SCOCR3LL \ Symbol Counter Output Compare
+ ed $ff bitmask: SCOCR3LL.SCOCR3LL \ Symbol Counter Output Compare
+$ec constant SCTSRHH \ Symbol Counter Frame Timestamp
+ $ff constant SCTSRHH_SCTSRHH \ Symbol Counter Frame Timestamp
+ ec $ff bitmask: SCTSRHH.SCTSRHH \ Symbol Counter Frame Timestamp
+$eb constant SCTSRHL \ Symbol Counter Frame Timestamp
+ $ff constant SCTSRHL_SCTSRHL \ Symbol Counter Frame Timestamp
+ eb $ff bitmask: SCTSRHL.SCTSRHL \ Symbol Counter Frame Timestamp
+$ea constant SCTSRLH \ Symbol Counter Frame Timestamp
+ $ff constant SCTSRLH_SCTSRLH \ Symbol Counter Frame Timestamp
+ ea $ff bitmask: SCTSRLH.SCTSRLH \ Symbol Counter Frame Timestamp
+$e9 constant SCTSRLL \ Symbol Counter Frame Timestamp
+ $ff constant SCTSRLL_SCTSRLL \ Symbol Counter Frame Timestamp
+ e9 $ff bitmask: SCTSRLL.SCTSRLL \ Symbol Counter Frame Timestamp
+$e8 constant SCBTSRHH \ Symbol Counter Beacon Timestam
+ $ff constant SCBTSRHH_SCBTSRHH \ Symbol Counter Beacon Timestam
+ e8 $ff bitmask: SCBTSRHH.SCBTSRHH \ Symbol Counter Beacon Timestam
+$e7 constant SCBTSRHL \ Symbol Counter Beacon Timestam
+ $ff constant SCBTSRHL_SCBTSRHL \ Symbol Counter Beacon Timestam
+ e7 $ff bitmask: SCBTSRHL.SCBTSRHL \ Symbol Counter Beacon Timestam
+$e6 constant SCBTSRLH \ Symbol Counter Beacon Timestam
+ $ff constant SCBTSRLH_SCBTSRLH \ Symbol Counter Beacon Timestam
+ e6 $ff bitmask: SCBTSRLH.SCBTSRLH \ Symbol Counter Beacon Timestam
+$e5 constant SCBTSRLL \ Symbol Counter Beacon Timestam
+ $ff constant SCBTSRLL_SCBTSRLL \ Symbol Counter Beacon Timestam
+ e5 $ff bitmask: SCBTSRLL.SCBTSRLL \ Symbol Counter Beacon Timestam
+$e4 constant SCCNTHH \ Symbol Counter Register HH-Byt
+ $ff constant SCCNTHH_SCCNTHH \ Symbol Counter Register HH-Byt
+ e4 $ff bitmask: SCCNTHH.SCCNTHH \ Symbol Counter Register HH-Byt
+$e3 constant SCCNTHL \ Symbol Counter Register HL-Byt
+ $ff constant SCCNTHL_SCCNTHL \ Symbol Counter Register HL-Byt
+ e3 $ff bitmask: SCCNTHL.SCCNTHL \ Symbol Counter Register HL-Byt
+$e2 constant SCCNTLH \ Symbol Counter Register LH-Byt
+ $ff constant SCCNTLH_SCCNTLH \ Symbol Counter Register LH-Byt
+ e2 $ff bitmask: SCCNTLH.SCCNTLH \ Symbol Counter Register LH-Byt
+$e1 constant SCCNTLL \ Symbol Counter Register LL-Byt
+ $ff constant SCCNTLL_SCCNTLL \ Symbol Counter Register LL-Byt
+ e1 $ff bitmask: SCCNTLL.SCCNTLL \ Symbol Counter Register LL-Byt
+$e0 constant SCIRQS \ Symbol Counter Interrupt Statu
+ $e0 constant SCIRQS_Res \ Reserved Bit
+ e0 $e0 bitmask: SCIRQS.Res \ Reserved Bit
+ $10 constant SCIRQS_IRQSBO \ Backoff Slot Counter IRQ
+ e0 $10 bitmask: SCIRQS.IRQSBO \ Backoff Slot Counter IRQ
+ $8 constant SCIRQS_IRQSOF \ Symbol Counter Overflow IRQ
+ e0 $8 bitmask: SCIRQS.IRQSOF \ Symbol Counter Overflow IRQ
+ $7 constant SCIRQS_IRQSCP \ Compare Unit 3 Compare Match I
+ e0 $7 bitmask: SCIRQS.IRQSCP \ Compare Unit 3 Compare Match I
+$df constant SCIRQM \ Symbol Counter Interrupt Mask
+ $e0 constant SCIRQM_Res \ Reserved Bit
+ df $e0 bitmask: SCIRQM.Res \ Reserved Bit
+ $10 constant SCIRQM_IRQMBO \ Backoff Slot Counter IRQ enabl
+ df $10 bitmask: SCIRQM.IRQMBO \ Backoff Slot Counter IRQ enabl
+ $8 constant SCIRQM_IRQMOF \ Symbol Counter Overflow IRQ en
+ df $8 bitmask: SCIRQM.IRQMOF \ Symbol Counter Overflow IRQ en
+ $7 constant SCIRQM_IRQMCP \ Symbol Counter Compare Match 3
+ df $7 bitmask: SCIRQM.IRQMCP \ Symbol Counter Compare Match 3
+$de constant SCSR \ Symbol Counter Status Register
+ $fe constant SCSR_Res \ Reserved Bit
+ de $fe bitmask: SCSR.Res \ Reserved Bit
+ $1 constant SCSR_SCBSY \ Symbol Counter busy
+ de $1 bitmask: SCSR.SCBSY \ Symbol Counter busy
+$dd constant SCCR1 \ Symbol Counter Control Registe
+ $c0 constant SCCR1_Res \ Reserved Bit
+ dd $c0 bitmask: SCCR1.Res \ Reserved Bit
+ $20 constant SCCR1_SCBTSM \ Symbol Counter Beacon Timestam
+ dd $20 bitmask: SCCR1.SCBTSM \ Symbol Counter Beacon Timestam
+ $1c constant SCCR1_SCCKDIV \ Clock divider for synchronous
+ dd $1c bitmask: SCCR1.SCCKDIV \ Clock divider for synchronous
+ $2 constant SCCR1_SCEECLK \ Enable External Clock Source o
+ dd $2 bitmask: SCCR1.SCEECLK \ Enable External Clock Source o
+ $1 constant SCCR1_SCENBO \ Backoff Slot Counter enable
+ dd $1 bitmask: SCCR1.SCENBO \ Backoff Slot Counter enable
+$dc constant SCCR0 \ Symbol Counter Control Registe
+ $80 constant SCCR0_SCRES \ Symbol Counter Synchronization
+ dc $80 bitmask: SCCR0.SCRES \ Symbol Counter Synchronization
+ $40 constant SCCR0_SCMBTS \ Manual Beacon Timestamp
+ dc $40 bitmask: SCCR0.SCMBTS \ Manual Beacon Timestamp
+ $20 constant SCCR0_SCEN \ Symbol Counter enable
+ dc $20 bitmask: SCCR0.SCEN \ Symbol Counter enable
+ $10 constant SCCR0_SCCKSEL \ Symbol Counter Clock Source se
+ dc $10 bitmask: SCCR0.SCCKSEL \ Symbol Counter Clock Source se
+ $8 constant SCCR0_SCTSE \ Symbol Counter Automatic Times
+ dc $8 bitmask: SCCR0.SCTSE \ Symbol Counter Automatic Times
+ $7 constant SCCR0_SCCMP \ Symbol Counter Compare Unit 3
+ dc $7 bitmask: SCCR0.SCCMP \ Symbol Counter Compare Unit 3
+$db constant SCCSR \ Symbol Counter Compare Source
+ $c0 constant SCCSR_Res \ Reserved Bit
+ db $c0 bitmask: SCCSR.Res \ Reserved Bit
+ $30 constant SCCSR_SCCS3 \ Symbol Counter Compare Source
+ db $30 bitmask: SCCSR.SCCS3 \ Symbol Counter Compare Source
+ $c constant SCCSR_SCCS2 \ Symbol Counter Compare Source
+ db $c bitmask: SCCSR.SCCS2 \ Symbol Counter Compare Source
+ $3 constant SCCSR_SCCS1 \ Symbol Counter Compare Source
+ db $3 bitmask: SCCSR.SCCS1 \ Symbol Counter Compare Source
+$da constant SCRSTRHH \ Symbol Counter Received Frame
+ $ff constant SCRSTRHH_SCRSTRHH \ Symbol Counter Received Frame
+ da $ff bitmask: SCRSTRHH.SCRSTRHH \ Symbol Counter Received Frame
+$d9 constant SCRSTRHL \ Symbol Counter Received Frame
+ $ff constant SCRSTRHL_SCRSTRHL \ Symbol Counter Received Frame
+ d9 $ff bitmask: SCRSTRHL.SCRSTRHL \ Symbol Counter Received Frame
+$d8 constant SCRSTRLH \ Symbol Counter Received Frame
+ $ff constant SCRSTRLH_SCRSTRLH \ Symbol Counter Received Frame
+ d8 $ff bitmask: SCRSTRLH.SCRSTRLH \ Symbol Counter Received Frame
+$d7 constant SCRSTRLL \ Symbol Counter Received Frame
+ $ff constant SCRSTRLL_SCRSTRLL \ Symbol Counter Received Frame
+ d7 $ff bitmask: SCRSTRLL.SCRSTRLL \ Symbol Counter Received Frame
+\ EEPROM
+$41 constant EEAR \ EEPROM Address Register Bytes
+$40 constant EEDR \ EEPROM Data Register
+$3f constant EECR \ EEPROM Control Register
+ $c0 constant EECR_Res \ Reserved
+ 3f $c0 bitmask: EECR.Res \ Reserved
+ $30 constant EECR_EEPM \ EEPROM Programming Mode
+ 3f $30 bitmask: EECR.EEPM \ EEPROM Programming Mode
+ $8 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
+ 3f $8 bitmask: EECR.EERIE \ EEPROM Ready Interrupt Enable
+ $4 constant EECR_EEMPE \ EEPROM Master Write Enable
+ 3f $4 bitmask: EECR.EEMPE \ EEPROM Master Write Enable
+ $2 constant EECR_EEPE \ EEPROM Programming Enable
+ 3f $2 bitmask: EECR.EEPE \ EEPROM Programming Enable
+ $1 constant EECR_EERE \ EEPROM Read Enable
+ 3f $1 bitmask: EECR.EERE \ EEPROM Read Enable
+\ JTAG
+$51 constant OCDR \ On-Chip Debug Register
+ $ff constant OCDR_OCDR \ On-Chip Debug Register Data
+ 51 $ff bitmask: OCDR.OCDR \ On-Chip Debug Register Data
+$55 constant MCUCR \ MCU Control Register
+ $80 constant MCUCR_JTD \ JTAG Interface Disable
+ 55 $80 bitmask: MCUCR.JTD \ JTAG Interface Disable
+$54 constant MCUSR \ MCU Status Register
+ $10 constant MCUSR_JTRF \ JTAG Reset Flag
+ 54 $10 bitmask: MCUSR.JTRF \ JTAG Reset Flag
+\ EXTERNAL_INTERRUPT
+$69 constant EICRA \ External Interrupt Control Reg
+ $c0 constant EICRA_ISC3 \ External Interrupt 3 Sense Con
+ 69 $c0 bitmask: EICRA.ISC3 \ External Interrupt 3 Sense Con
+ $30 constant EICRA_ISC2 \ External Interrupt 2 Sense Con
+ 69 $30 bitmask: EICRA.ISC2 \ External Interrupt 2 Sense Con
+ $c constant EICRA_ISC1 \ External Interrupt 1 Sense Con
+ 69 $c bitmask: EICRA.ISC1 \ External Interrupt 1 Sense Con
+ $3 constant EICRA_ISC0 \ External Interrupt 0 Sense Con
+ 69 $3 bitmask: EICRA.ISC0 \ External Interrupt 0 Sense Con
+$6a constant EICRB \ External Interrupt Control Reg
+ $c0 constant EICRB_ISC7 \ External Interrupt 7 Sense Con
+ 6a $c0 bitmask: EICRB.ISC7 \ External Interrupt 7 Sense Con
+ $30 constant EICRB_ISC6 \ External Interrupt 6 Sense Con
+ 6a $30 bitmask: EICRB.ISC6 \ External Interrupt 6 Sense Con
+ $c constant EICRB_ISC5 \ External Interrupt 5 Sense Con
+ 6a $c bitmask: EICRB.ISC5 \ External Interrupt 5 Sense Con
+ $3 constant EICRB_ISC4 \ External Interrupt 4 Sense Con
+ 6a $3 bitmask: EICRB.ISC4 \ External Interrupt 4 Sense Con
+$3d constant EIMSK \ External Interrupt Mask Regist
+ $ff constant EIMSK_INT \ External Interrupt Request Ena
+ 3d $ff bitmask: EIMSK.INT \ External Interrupt Request Ena
+$3c constant EIFR \ External Interrupt Flag Regist
+ $ff constant EIFR_INTF \ External Interrupt Flag
+ 3c $ff bitmask: EIFR.INTF \ External Interrupt Flag
+$6d constant PCMSK2 \ Pin Change Mask Register 2
+ $ff constant PCMSK2_PCINT \ Pin Change Enable Mask
+ 6d $ff bitmask: PCMSK2.PCINT \ Pin Change Enable Mask
+$6c constant PCMSK1 \ Pin Change Mask Register 1
+ $ff constant PCMSK1_PCINT \ Pin Change Enable Mask
+ 6c $ff bitmask: PCMSK1.PCINT \ Pin Change Enable Mask
+$6b constant PCMSK0 \ Pin Change Mask Register 0
+$3b constant PCIFR \ Pin Change Interrupt Flag Regi
+ $f8 constant PCIFR_Res \ Reserved Bit
+ 3b $f8 bitmask: PCIFR.Res \ Reserved Bit
+ $7 constant PCIFR_PCIF \ Pin Change Interrupt Flags
+ 3b $7 bitmask: PCIFR.PCIF \ Pin Change Interrupt Flags
+$68 constant PCICR \ Pin Change Interrupt Control R
+ $f8 constant PCICR_Res \ Reserved Bit
+ 68 $f8 bitmask: PCICR.Res \ Reserved Bit
+ $7 constant PCICR_PCIE \ Pin Change Interrupt Enables
+ 68 $7 bitmask: PCICR.PCIE \ Pin Change Interrupt Enables
+\ AD_CONVERTER
+$7c constant ADMUX \ The ADC Multiplexer Selection
+ $c0 constant ADMUX_REFS \ Reference Selection Bits
+ 7c $c0 bitmask: ADMUX.REFS \ Reference Selection Bits
+ $20 constant ADMUX_ADLAR \ ADC Left Adjust Result
+ 7c $20 bitmask: ADMUX.ADLAR \ ADC Left Adjust Result
+ $1f constant ADMUX_MUX \ Analog Channel and Gain Select
+ 7c $1f bitmask: ADMUX.MUX \ Analog Channel and Gain Select
+$78 constant ADC \ ADC Data Register Bytes
+$7a constant ADCSRA \ The ADC Control and Status Reg
+ $80 constant ADCSRA_ADEN \ ADC Enable
+ 7a $80 bitmask: ADCSRA.ADEN \ ADC Enable
+ $40 constant ADCSRA_ADSC \ ADC Start Conversion
+ 7a $40 bitmask: ADCSRA.ADSC \ ADC Start Conversion
+ $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
+ 7a $20 bitmask: ADCSRA.ADATE \ ADC Auto Trigger Enable
+ $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
+ 7a $10 bitmask: ADCSRA.ADIF \ ADC Interrupt Flag
+ $8 constant ADCSRA_ADIE \ ADC Interrupt Enable
+ 7a $8 bitmask: ADCSRA.ADIE \ ADC Interrupt Enable
+ $7 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
+ 7a $7 bitmask: ADCSRA.ADPS \ ADC Prescaler Select Bits
+$7b constant ADCSRB \ The ADC Control and Status Reg
+ $80 constant ADCSRB_AVDDOK \ AVDD Supply Voltage OK
+ 7b $80 bitmask: ADCSRB.AVDDOK \ AVDD Supply Voltage OK
+ $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer
+ 7b $40 bitmask: ADCSRB.ACME \ Analog Comparator Multiplexer
+ $20 constant ADCSRB_REFOK \ Reference Voltage OK
+ 7b $20 bitmask: ADCSRB.REFOK \ Reference Voltage OK
+ $10 constant ADCSRB_ACCH \ Analog Channel Change
+ 7b $10 bitmask: ADCSRB.ACCH \ Analog Channel Change
+ $8 constant ADCSRB_MUX5 \ Analog Channel and Gain Select
+ 7b $8 bitmask: ADCSRB.MUX5 \ Analog Channel and Gain Select
+ $7 constant ADCSRB_ADTS \ ADC Auto Trigger Source
+ 7b $7 bitmask: ADCSRB.ADTS \ ADC Auto Trigger Source
+$77 constant ADCSRC \ The ADC Control and Status Reg
+ $c0 constant ADCSRC_ADTHT \ ADC Track-and-Hold Time
+ 77 $c0 bitmask: ADCSRC.ADTHT \ ADC Track-and-Hold Time
+ $20 constant ADCSRC_Res0 \ Reserved
+ 77 $20 bitmask: ADCSRC.Res0 \ Reserved
+ $1f constant ADCSRC_ADSUT \ ADC Start-up Time
+ 77 $1f bitmask: ADCSRC.ADSUT \ ADC Start-up Time
+$7d constant DIDR2 \ Digital Input Disable Register
+ $80 constant DIDR2_ADC15D \ Reserved Bits
+ 7d $80 bitmask: DIDR2.ADC15D \ Reserved Bits
+ $40 constant DIDR2_ADC14D \ Reserved Bits
+ 7d $40 bitmask: DIDR2.ADC14D \ Reserved Bits
+ $20 constant DIDR2_ADC13D \ Reserved Bits
+ 7d $20 bitmask: DIDR2.ADC13D \ Reserved Bits
+ $10 constant DIDR2_ADC12D \ Reserved Bits
+ 7d $10 bitmask: DIDR2.ADC12D \ Reserved Bits
+ $8 constant DIDR2_ADC11D \ Reserved Bits
+ 7d $8 bitmask: DIDR2.ADC11D \ Reserved Bits
+ $4 constant DIDR2_ADC10D \ Reserved Bits
+ 7d $4 bitmask: DIDR2.ADC10D \ Reserved Bits
+ $2 constant DIDR2_ADC9D \ Reserved Bits
+ 7d $2 bitmask: DIDR2.ADC9D \ Reserved Bits
+ $1 constant DIDR2_ADC8D \ Reserved Bits
+ 7d $1 bitmask: DIDR2.ADC8D \ Reserved Bits
+$7e constant DIDR0 \ Digital Input Disable Register
+ $80 constant DIDR0_ADC7D \ Disable ADC7:0 Digital Input
+ 7e $80 bitmask: DIDR0.ADC7D \ Disable ADC7:0 Digital Input
+ $40 constant DIDR0_ADC6D \ Disable ADC7:0 Digital Input
+ 7e $40 bitmask: DIDR0.ADC6D \ Disable ADC7:0 Digital Input
+ $20 constant DIDR0_ADC5D \ Disable ADC7:0 Digital Input
+ 7e $20 bitmask: DIDR0.ADC5D \ Disable ADC7:0 Digital Input
+ $10 constant DIDR0_ADC4D \ Disable ADC7:0 Digital Input
+ 7e $10 bitmask: DIDR0.ADC4D \ Disable ADC7:0 Digital Input
+ $8 constant DIDR0_ADC3D \ Disable ADC7:0 Digital Input
+ 7e $8 bitmask: DIDR0.ADC3D \ Disable ADC7:0 Digital Input
+ $4 constant DIDR0_ADC2D \ Disable ADC7:0 Digital Input
+ 7e $4 bitmask: DIDR0.ADC2D \ Disable ADC7:0 Digital Input
+ $2 constant DIDR0_ADC1D \ Disable ADC7:0 Digital Input
+ 7e $2 bitmask: DIDR0.ADC1D \ Disable ADC7:0 Digital Input
+ $1 constant DIDR0_ADC0D \ Disable ADC7:0 Digital Input
+ 7e $1 bitmask: DIDR0.ADC0D \ Disable ADC7:0 Digital Input
+\ BOOT_LOAD
+$57 constant SPMCSR \ Store Program Memory Control R
+ $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
+ 57 $80 bitmask: SPMCSR.SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
+ 57 $40 bitmask: SPMCSR.RWWSB \ Read While Write Section Busy
+ $20 constant SPMCSR_SIGRD \ Signature Row Read
+ 57 $20 bitmask: SPMCSR.SIGRD \ Signature Row Read
+ $10 constant SPMCSR_RWWSRE \ Read While Write Section Read
+ 57 $10 bitmask: SPMCSR.RWWSRE \ Read While Write Section Read
+ $8 constant SPMCSR_BLBSET \ Boot Lock Bit Set
+ 57 $8 bitmask: SPMCSR.BLBSET \ Boot Lock Bit Set
+ $4 constant SPMCSR_PGWRT \ Page Write
+ 57 $4 bitmask: SPMCSR.PGWRT \ Page Write
+ $2 constant SPMCSR_PGERS \ Page Erase
+ 57 $2 bitmask: SPMCSR.PGERS \ Page Erase
+ $1 constant SPMCSR_SPMEN \ Store Program Memory Enable
+ 57 $1 bitmask: SPMCSR.SPMEN \ Store Program Memory Enable
+\ CPU
+$5f constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ 5f $80 bitmask: SREG.I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ 5f $40 bitmask: SREG.T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ 5f $20 bitmask: SREG.H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ 5f $10 bitmask: SREG.S \ Sign Bit
+ $8 constant SREG_V \ Two's Complement Overflow Flag
+ 5f $8 bitmask: SREG.V \ Two's Complement Overflow Flag
+ $4 constant SREG_N \ Negative Flag
+ 5f $4 bitmask: SREG.N \ Negative Flag
+ $2 constant SREG_Z \ Zero Flag
+ 5f $2 bitmask: SREG.Z \ Zero Flag
+ $1 constant SREG_C \ Carry Flag
+ 5f $1 bitmask: SREG.C \ Carry Flag
+$5d constant SP \ Stack Pointer
+$55 constant MCUCR \ MCU Control Register
+ $80 constant MCUCR_JTD \ JTAG Interface Disable
+ 55 $80 bitmask: MCUCR.JTD \ JTAG Interface Disable
+ $60 constant MCUCR_Res \ Reserved
+ 55 $60 bitmask: MCUCR.Res \ Reserved
+ $10 constant MCUCR_PUD \ Pull-up Disable
+ 55 $10 bitmask: MCUCR.PUD \ Pull-up Disable
+ $c constant MCUCR_Res \ Reserved
+ 55 $c bitmask: MCUCR.Res \ Reserved
+ $2 constant MCUCR_IVSEL \ Interrupt Vector Select
+ 55 $2 bitmask: MCUCR.IVSEL \ Interrupt Vector Select
+ $1 constant MCUCR_IVCE \ Interrupt Vector Change Enable
+ 55 $1 bitmask: MCUCR.IVCE \ Interrupt Vector Change Enable
+$54 constant MCUSR \ MCU Status Register
+ $e0 constant MCUSR_Res \ Reserved
+ 54 $e0 bitmask: MCUSR.Res \ Reserved
+ $10 constant MCUSR_JTRF \ JTAG Reset Flag
+ 54 $10 bitmask: MCUSR.JTRF \ JTAG Reset Flag
+ $8 constant MCUSR_WDRF \ Watchdog Reset Flag
+ 54 $8 bitmask: MCUSR.WDRF \ Watchdog Reset Flag
+ $4 constant MCUSR_BORF \ Brown-out Reset Flag
+ 54 $4 bitmask: MCUSR.BORF \ Brown-out Reset Flag
+ $2 constant MCUSR_EXTRF \ External Reset Flag
+ 54 $2 bitmask: MCUSR.EXTRF \ External Reset Flag
+ $1 constant MCUSR_PORF \ Power-on Reset Flag
+ 54 $1 bitmask: MCUSR.PORF \ Power-on Reset Flag
+$66 constant OSCCAL \ Oscillator Calibration Value
+ $ff constant OSCCAL_CAL \ Oscillator Calibration Tuning
+ 66 $ff bitmask: OSCCAL.CAL \ Oscillator Calibration Tuning
+$61 constant CLKPR \ Clock Prescale Register
+ $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable
+ 61 $80 bitmask: CLKPR.CLKPCE \ Clock Prescaler Change Enable
+ $70 constant CLKPR_Res \ Reserved
+ 61 $70 bitmask: CLKPR.Res \ Reserved
+ $f constant CLKPR_CLKPS \ Clock Prescaler Select Bits
+ 61 $f bitmask: CLKPR.CLKPS \ Clock Prescaler Select Bits
+$53 constant SMCR \ Sleep Mode Control Register
+ $f0 constant SMCR_Res \ Reserved
+ 53 $f0 bitmask: SMCR.Res \ Reserved
+ $e constant SMCR_SM \ Sleep Mode Select bits
+ 53 $e bitmask: SMCR.SM \ Sleep Mode Select bits
+ $1 constant SMCR_SE \ Sleep Enable
+ 53 $1 bitmask: SMCR.SE \ Sleep Enable
+$5b constant RAMPZ \ Extended Z-pointer Register fo
+ $fe constant RAMPZ_Res \ Reserved
+ 5b $fe bitmask: RAMPZ.Res \ Reserved
+ $1 constant RAMPZ_RAMPZ0 \ Extended Z-Pointer Value
+ 5b $1 bitmask: RAMPZ.RAMPZ0 \ Extended Z-Pointer Value
+$4b constant GPIOR2 \ General Purpose I/O Register 2
+ $ff constant GPIOR2_GPIOR \ General Purpose I/O Register 2
+ 4b $ff bitmask: GPIOR2.GPIOR \ General Purpose I/O Register 2
+$4a constant GPIOR1 \ General Purpose IO Register 1
+ $ff constant GPIOR1_GPIOR \ General Purpose I/O Register 1
+ 4a $ff bitmask: GPIOR1.GPIOR \ General Purpose I/O Register 1
+$3e constant GPIOR0 \ General Purpose IO Register 0
+ $80 constant GPIOR0_GPIOR07 \ General Purpose I/O Register 0
+ 3e $80 bitmask: GPIOR0.GPIOR07 \ General Purpose I/O Register 0
+ $40 constant GPIOR0_GPIOR06 \ General Purpose I/O Register 0
+ 3e $40 bitmask: GPIOR0.GPIOR06 \ General Purpose I/O Register 0
+ $20 constant GPIOR0_GPIOR05 \ General Purpose I/O Register 0
+ 3e $20 bitmask: GPIOR0.GPIOR05 \ General Purpose I/O Register 0
+ $10 constant GPIOR0_GPIOR04 \ General Purpose I/O Register 0
+ 3e $10 bitmask: GPIOR0.GPIOR04 \ General Purpose I/O Register 0
+ $8 constant GPIOR0_GPIOR03 \ General Purpose I/O Register 0
+ 3e $8 bitmask: GPIOR0.GPIOR03 \ General Purpose I/O Register 0
+ $4 constant GPIOR0_GPIOR02 \ General Purpose I/O Register 0
+ 3e $4 bitmask: GPIOR0.GPIOR02 \ General Purpose I/O Register 0
+ $2 constant GPIOR0_GPIOR01 \ General Purpose I/O Register 0
+ 3e $2 bitmask: GPIOR0.GPIOR01 \ General Purpose I/O Register 0
+ $1 constant GPIOR0_GPIOR00 \ General Purpose I/O Register 0
+ 3e $1 bitmask: GPIOR0.GPIOR00 \ General Purpose I/O Register 0
+$63 constant PRR2 \ Power Reduction Register 2
+ $f0 constant PRR2_Res \ Reserved Bit
+ 63 $f0 bitmask: PRR2.Res \ Reserved Bit
+ $f constant PRR2_PRRAM \ Power Reduction SRAMs
+ 63 $f bitmask: PRR2.PRRAM \ Power Reduction SRAMs
+$65 constant PRR1 \ Power Reduction Register 1
+ $80 constant PRR1_Res \ Reserved Bit
+ 65 $80 bitmask: PRR1.Res \ Reserved Bit
+ $40 constant PRR1_PRTRX24 \ Power Reduction Transceiver
+ 65 $40 bitmask: PRR1.PRTRX24 \ Power Reduction Transceiver
+ $20 constant PRR1_PRTIM5 \ Power Reduction Timer/Counter5
+ 65 $20 bitmask: PRR1.PRTIM5 \ Power Reduction Timer/Counter5
+ $10 constant PRR1_PRTIM4 \ Power Reduction Timer/Counter4
+ 65 $10 bitmask: PRR1.PRTIM4 \ Power Reduction Timer/Counter4
+ $8 constant PRR1_PRTIM3 \ Power Reduction Timer/Counter3
+ 65 $8 bitmask: PRR1.PRTIM3 \ Power Reduction Timer/Counter3
+ $1 constant PRR1_PRUSART1 \ Power Reduction USART1
+ 65 $1 bitmask: PRR1.PRUSART1 \ Power Reduction USART1
+$64 constant PRR0 \ Power Reduction Register0
+ $80 constant PRR0_PRTWI \ Power Reduction TWI
+ 64 $80 bitmask: PRR0.PRTWI \ Power Reduction TWI
+ $40 constant PRR0_PRTIM2 \ Power Reduction Timer/Counter2
+ 64 $40 bitmask: PRR0.PRTIM2 \ Power Reduction Timer/Counter2
+ $20 constant PRR0_PRTIM0 \ Power Reduction Timer/Counter0
+ 64 $20 bitmask: PRR0.PRTIM0 \ Power Reduction Timer/Counter0
+ $10 constant PRR0_PRPGA \ Power Reduction PGA
+ 64 $10 bitmask: PRR0.PRPGA \ Power Reduction PGA
+ $8 constant PRR0_PRTIM1 \ Power Reduction Timer/Counter1
+ 64 $8 bitmask: PRR0.PRTIM1 \ Power Reduction Timer/Counter1
+ $4 constant PRR0_PRSPI \ Power Reduction Serial Periphe
+ 64 $4 bitmask: PRR0.PRSPI \ Power Reduction Serial Periphe
+ $2 constant PRR0_PRUSART0 \ Power Reduction USART
+ 64 $2 bitmask: PRR0.PRUSART0 \ Power Reduction USART
+ $1 constant PRR0_PRADC \ Power Reduction ADC
+ 64 $1 bitmask: PRR0.PRADC \ Power Reduction ADC
+\ FLASH
+$75 constant NEMCR \ Flash Extended-Mode Control-Re
+ $40 constant NEMCR_ENEAM \ Enable Extended Address Mode f
+ 75 $40 bitmask: NEMCR.ENEAM \ Enable Extended Address Mode f
+ $30 constant NEMCR_AEAM \ Address for Extended Address M
+ 75 $30 bitmask: NEMCR.AEAM \ Address for Extended Address M
+$67 constant BGCR \ Reference Voltage Calibration
+ $80 constant BGCR_Res \ Reserved Bit
+ 67 $80 bitmask: BGCR.Res \ Reserved Bit
+ $78 constant BGCR_BGCAL_FINE \ Fine Calibration Bits
+ 67 $78 bitmask: BGCR.BGCAL_FINE \ Fine Calibration Bits
+ $7 constant BGCR_BGCAL \ Coarse Calibration Bits
+ 67 $7 bitmask: BGCR.BGCAL \ Coarse Calibration Bits
+\ PWRCTRL
+$139 constant TRXPR \ Transceiver Pin Register
+ $f0 constant TRXPR_Res \ Reserved
+ 139 $f0 bitmask: TRXPR.Res \ Reserved
+ $2 constant TRXPR_SLPTR \ Multi-purpose Transceiver Cont
+ 139 $2 bitmask: TRXPR.SLPTR \ Multi-purpose Transceiver Cont
+ $1 constant TRXPR_TRXRST \ Force Transceiver Reset
+ 139 $1 bitmask: TRXPR.TRXRST \ Force Transceiver Reset
+$135 constant DRTRAM0 \ Data Retention Configuration R
+ $c0 constant DRTRAM0_Res \ Reserved
+ 135 $c0 bitmask: DRTRAM0.Res \ Reserved
+ $20 constant DRTRAM0_DRTSWOK \ DRT Switch OK
+ 135 $20 bitmask: DRTRAM0.DRTSWOK \ DRT Switch OK
+ $10 constant DRTRAM0_ENDRT \ Enable SRAM Data Retention
+ 135 $10 bitmask: DRTRAM0.ENDRT \ Enable SRAM Data Retention
+$134 constant DRTRAM1 \ Data Retention Configuration R
+ $c0 constant DRTRAM1_Res \ Reserved
+ 134 $c0 bitmask: DRTRAM1.Res \ Reserved
+ $20 constant DRTRAM1_DRTSWOK \ DRT Switch OK
+ 134 $20 bitmask: DRTRAM1.DRTSWOK \ DRT Switch OK
+ $10 constant DRTRAM1_ENDRT \ Enable SRAM Data Retention
+ 134 $10 bitmask: DRTRAM1.ENDRT \ Enable SRAM Data Retention
+$133 constant DRTRAM2 \ Data Retention Configuration R
+ $40 constant DRTRAM2_Res \ Reserved Bit
+ 133 $40 bitmask: DRTRAM2.Res \ Reserved Bit
+ $20 constant DRTRAM2_DRTSWOK \ DRT Switch OK
+ 133 $20 bitmask: DRTRAM2.DRTSWOK \ DRT Switch OK
+ $10 constant DRTRAM2_ENDRT \ Enable SRAM Data Retention
+ 133 $10 bitmask: DRTRAM2.ENDRT \ Enable SRAM Data Retention
+$132 constant DRTRAM3 \ Data Retention Configuration R
+ $c0 constant DRTRAM3_Res \ Reserved
+ 132 $c0 bitmask: DRTRAM3.Res \ Reserved
+ $20 constant DRTRAM3_DRTSWOK \ DRT Switch OK
+ 132 $20 bitmask: DRTRAM3.DRTSWOK \ DRT Switch OK
+ $10 constant DRTRAM3_ENDRT \ Enable SRAM Data Retention
+ 132 $10 bitmask: DRTRAM3.ENDRT \ Enable SRAM Data Retention
+$130 constant LLDRL \ Low Leakage Voltage Regulator
+ $f0 constant LLDRL_Res \ Reserved
+ 130 $f0 bitmask: LLDRL.Res \ Reserved
+ $f constant LLDRL_LLDRL \ Low-Byte Data Register Bits
+ 130 $f bitmask: LLDRL.LLDRL \ Low-Byte Data Register Bits
+$131 constant LLDRH \ Low Leakage Voltage Regulator
+ $e0 constant LLDRH_Res \ Reserved
+ 131 $e0 bitmask: LLDRH.Res \ Reserved
+ $1f constant LLDRH_LLDRH \ High-Byte Data Register Bits
+ 131 $1f bitmask: LLDRH.LLDRH \ High-Byte Data Register Bits
+$12f constant LLCR \ Low Leakage Voltage Regulator
+ $c0 constant LLCR_Res \ Reserved Bit
+ 12f $c0 bitmask: LLCR.Res \ Reserved Bit
+ $20 constant LLCR_LLDONE \ Calibration Done
+ 12f $20 bitmask: LLCR.LLDONE \ Calibration Done
+ $10 constant LLCR_LLCOMP \ Comparator Output
+ 12f $10 bitmask: LLCR.LLCOMP \ Comparator Output
+ $8 constant LLCR_LLCAL \ Calibration Active
+ 12f $8 bitmask: LLCR.LLCAL \ Calibration Active
+ $4 constant LLCR_LLTCO \ Temperature Coefficient of Cur
+ 12f $4 bitmask: LLCR.LLTCO \ Temperature Coefficient of Cur
+ $2 constant LLCR_LLSHORT \ Short Lower Calibration Circui
+ 12f $2 bitmask: LLCR.LLSHORT \ Short Lower Calibration Circui
+ $1 constant LLCR_LLENCAL \ Enable Automatic Calibration
+ 12f $1 bitmask: LLCR.LLENCAL \ Enable Automatic Calibration
+$136 constant DPDS0 \ Port Driver Strength Register
+ $c0 constant DPDS0_PFDRV \ Driver Strength Port F
+ 136 $c0 bitmask: DPDS0.PFDRV \ Driver Strength Port F
+ $30 constant DPDS0_PEDRV \ Driver Strength Port E
+ 136 $30 bitmask: DPDS0.PEDRV \ Driver Strength Port E
+ $c constant DPDS0_PDDRV \ Driver Strength Port D
+ 136 $c bitmask: DPDS0.PDDRV \ Driver Strength Port D
+ $3 constant DPDS0_PBDRV \ Driver Strength Port B
+ 136 $3 bitmask: DPDS0.PBDRV \ Driver Strength Port B
+$137 constant DPDS1 \ Port Driver Strength Register
+ $fc constant DPDS1_Res \ Reserved
+ 137 $fc bitmask: DPDS1.Res \ Reserved
+ $3 constant DPDS1_PGDRV \ Driver Strength Port G
+ 137 $3 bitmask: DPDS1.PGDRV \ Driver Strength Port G
+$55 constant MCUCR \ MCU Control Register
+ $10 constant MCUCR_PUD \ Pull-up Disable
+ 55 $10 bitmask: MCUCR.PUD \ Pull-up Disable
+\ USART0_SPI
+$c0 constant UCSR0A \ USART0 MSPIM Control and Statu
+ $80 constant UCSR0A_RXC0 \ USART Receive Complete
+ c0 $80 bitmask: UCSR0A.RXC0 \ USART Receive Complete
+ $40 constant UCSR0A_TXC0 \ USART Transmit Complete
+ c0 $40 bitmask: UCSR0A.TXC0 \ USART Transmit Complete
+ $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
+ c0 $20 bitmask: UCSR0A.UDRE0 \ USART Data Register Empty
+$c1 constant UCSR0B \ USART0 MSPIM Control and Statu
+ $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
+ c1 $80 bitmask: UCSR0B.RXCIE0 \ RX Complete Interrupt Enable
+ $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
+ c1 $40 bitmask: UCSR0B.TXCIE0 \ TX Complete Interrupt Enable
+ $20 constant UCSR0B_UDRIE0 \ USART Data Register Empty Inte
+ c1 $20 bitmask: UCSR0B.UDRIE0 \ USART Data Register Empty Inte
+ $10 constant UCSR0B_RXEN0 \ Receiver Enable
+ c1 $10 bitmask: UCSR0B.RXEN0 \ Receiver Enable
+ $8 constant UCSR0B_TXEN0 \ Transmitter Enable
+ c1 $8 bitmask: UCSR0B.TXEN0 \ Transmitter Enable
+$c2 constant UCSR0C \ USART0 MSPIM Control and Statu
+ $4 constant UCSR0C_UDORD0 \ Data Order
+ c2 $4 bitmask: UCSR0C.UDORD0 \ Data Order
+ $2 constant UCSR0C_UCPHA0 \ Clock Phase
+ c2 $2 bitmask: UCSR0C.UCPHA0 \ Clock Phase
+ $1 constant UCSR0C_UCPOL0 \ Clock Polarity
+ c2 $1 bitmask: UCSR0C.UCPOL0 \ Clock Polarity
+\ USART1_SPI
+$c8 constant UCSR1A \ USART1 MSPIM Control and Statu
+ $80 constant UCSR1A_RXC1 \ USART Receive Complete
+ c8 $80 bitmask: UCSR1A.RXC1 \ USART Receive Complete
+ $40 constant UCSR1A_TXC1 \ USART Transmit Complete
+ c8 $40 bitmask: UCSR1A.TXC1 \ USART Transmit Complete
+ $20 constant UCSR1A_UDRE1 \ USART Data Register Empty
+ c8 $20 bitmask: UCSR1A.UDRE1 \ USART Data Register Empty
+$c9 constant UCSR1B \ USART1 MSPIM Control and Statu
+ $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable
+ c9 $80 bitmask: UCSR1B.RXCIE1 \ RX Complete Interrupt Enable
+ $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable
+ c9 $40 bitmask: UCSR1B.TXCIE1 \ TX Complete Interrupt Enable
+ $20 constant UCSR1B_UDRIE1 \ USART Data Register Empty Inte
+ c9 $20 bitmask: UCSR1B.UDRIE1 \ USART Data Register Empty Inte
+ $10 constant UCSR1B_RXEN1 \ Receiver Enable
+ c9 $10 bitmask: UCSR1B.RXEN1 \ Receiver Enable
+ $8 constant UCSR1B_TXEN1 \ Transmitter Enable
+ c9 $8 bitmask: UCSR1B.TXEN1 \ Transmitter Enable
+$ca constant UCSR1C \ USART1 MSPIM Control and Statu
+ $4 constant UCSR1C_UDORD1 \ Data Order
+ ca $4 bitmask: UCSR1C.UDORD1 \ Data Order
+ $2 constant UCSR1C_UCPHA1 \ Clock Phase
+ ca $2 bitmask: UCSR1C.UCPHA1 \ Clock Phase
+ $1 constant UCSR1C_UCPOL1 \ Clock Polarity
+ ca $1 bitmask: UCSR1C.UCPOL1 \ Clock Polarity
diff --git a/amforth-6.5/avr8/devices/atmega1284rfr2/device.py b/amforth-6.5/avr8/devices/atmega1284rfr2/device.py
new file mode 100644
index 0000000..fbea858
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega1284rfr2/device.py
@@ -0,0 +1,1103 @@
+# Generated Automatically
+
+# Partname ATmega1284RFR2
+
+MCUREGS = {
+# Interrupt Vectors
+ 'INT0Addr' : '#2', # External Interrupt Request 0
+ 'INT1Addr' : '#4', # External Interrupt Request 1
+ 'INT2Addr' : '#6', # External Interrupt Request 2
+ 'INT3Addr' : '#8', # External Interrupt Request 3
+ 'INT4Addr' : '#10', # External Interrupt Request 4
+ 'INT5Addr' : '#12', # External Interrupt Request 5
+ 'INT6Addr' : '#14', # External Interrupt Request 6
+ 'INT7Addr' : '#16', # External Interrupt Request 7
+ 'PCINT0Addr' : '#18', # Pin Change Interrupt Request 0
+ 'PCINT1Addr' : '#20', # Pin Change Interrupt Request 1
+ 'PCINT2Addr' : '#22', # Pin Change Interrupt Request 2
+ 'WDTAddr' : '#24', # Watchdog Time-out Interrupt
+ 'TIMER2_COMPAAddr' : '#26', # Timer/Counter2 Compare Match A
+ 'TIMER2_COMPBAddr' : '#28', # Timer/Counter2 Compare Match B
+ 'TIMER2_OVFAddr' : '#30', # Timer/Counter2 Overflow
+ 'TIMER1_CAPTAddr' : '#32', # Timer/Counter1 Capture Event
+ 'TIMER1_COMPAAddr' : '#34', # Timer/Counter1 Compare Match A
+ 'TIMER1_COMPBAddr' : '#36', # Timer/Counter1 Compare Match B
+ 'TIMER1_COMPCAddr' : '#38', # Timer/Counter1 Compare Match C
+ 'TIMER1_OVFAddr' : '#40', # Timer/Counter1 Overflow
+ 'TIMER0_COMPAAddr' : '#42', # Timer/Counter0 Compare Match A
+ 'TIMER0_COMPBAddr' : '#44', # Timer/Counter0 Compare Match B
+ 'TIMER0_OVFAddr' : '#46', # Timer/Counter0 Overflow
+ 'SPI_STCAddr' : '#48', # SPI Serial Transfer Complete
+ 'USART0_RXAddr' : '#50', # USART0, Rx Complete
+ 'USART0_UDREAddr' : '#52', # USART0 Data register Empty
+ 'USART0_TXAddr' : '#54', # USART0, Tx Complete
+ 'ANALOG_COMPAddr' : '#56', # Analog Comparator
+ 'ADCAddr' : '#58', # ADC Conversion Complete
+ 'EE_READYAddr' : '#60', # EEPROM Ready
+ 'TIMER3_CAPTAddr' : '#62', # Timer/Counter3 Capture Event
+ 'TIMER3_COMPAAddr' : '#64', # Timer/Counter3 Compare Match A
+ 'TIMER3_COMPBAddr' : '#66', # Timer/Counter3 Compare Match B
+ 'TIMER3_COMPCAddr' : '#68', # Timer/Counter3 Compare Match C
+ 'TIMER3_OVFAddr' : '#70', # Timer/Counter3 Overflow
+ 'USART1_RXAddr' : '#72', # USART1, Rx Complete
+ 'USART1_UDREAddr' : '#74', # USART1 Data register Empty
+ 'USART1_TXAddr' : '#76', # USART1, Tx Complete
+ 'TWIAddr' : '#78', # 2-wire Serial Interface
+ 'SPM_READYAddr' : '#80', # Store Program Memory Read
+ 'TIMER4_CAPTAddr' : '#82', # Timer/Counter4 Capture Event
+ 'TIMER4_COMPAAddr' : '#84', # Timer/Counter4 Compare Match A
+ 'TIMER4_COMPBAddr' : '#86', # Timer/Counter4 Compare Match B
+ 'TIMER4_COMPCAddr' : '#88', # Timer/Counter4 Compare Match C
+ 'TIMER4_OVFAddr' : '#90', # Timer/Counter4 Overflow
+ 'TIMER5_CAPTAddr' : '#92', # Timer/Counter5 Capture Event
+ 'TIMER5_COMPAAddr' : '#94', # Timer/Counter5 Compare Match A
+ 'TIMER5_COMPBAddr' : '#96', # Timer/Counter5 Compare Match B
+ 'TIMER5_COMPCAddr' : '#98', # Timer/Counter5 Compare Match C
+ 'TIMER5_OVFAddr' : '#100', # Timer/Counter5 Overflow
+ 'USART2_RXAddr' : '#102', # USART2, Rx Complete
+ 'USART2_UDREAddr' : '#104', # USART2 Data register Empty
+ 'USART2_TXAddr' : '#106', # USART2, Tx Complete
+ 'USART3_RXAddr' : '#108', # USART3, Rx Complete
+ 'USART3_UDREAddr' : '#110', # USART3 Data register Empty
+ 'USART3_TXAddr' : '#112', # USART3, Tx Complete
+ 'TRX24_PLL_LOCKAddr' : '#114', # TRX24 - PLL lock interrupt
+ 'TRX24_PLL_UNLOCKAddr' : '#116', # TRX24 - PLL unlock interrupt
+ 'TRX24_RX_STARTAddr' : '#118', # TRX24 - Receive start interrupt
+ 'TRX24_RX_ENDAddr' : '#120', # TRX24 - RX_END interrupt
+ 'TRX24_CCA_ED_DONEAddr' : '#122', # TRX24 - CCA/ED done interrupt
+ 'TRX24_XAH_AMIAddr' : '#124', # TRX24 - XAH - AMI
+ 'TRX24_TX_ENDAddr' : '#126', # TRX24 - TX_END interrupt
+ 'TRX24_AWAKEAddr' : '#128', # TRX24 AWAKE - tranceiver is reaching state TRX_OFF
+ 'SCNT_CMP1Addr' : '#130', # Symbol counter - compare match 1 interrupt
+ 'SCNT_CMP2Addr' : '#132', # Symbol counter - compare match 2 interrupt
+ 'SCNT_CMP3Addr' : '#134', # Symbol counter - compare match 3 interrupt
+ 'SCNT_OVFLAddr' : '#136', # Symbol counter - overflow interrupt
+ 'SCNT_BACKOFFAddr' : '#138', # Symbol counter - backoff interrupt
+ 'AES_READYAddr' : '#140', # AES engine ready interrupt
+ 'BAT_LOWAddr' : '#142', # Battery monitor indicates supply voltage below threshold
+ 'TRX24_TX_STARTAddr' : '#144', # TRX24 TX start interrupt
+ 'TRX24_AMI0Addr' : '#146', # Address match interrupt of address filter 0
+ 'TRX24_AMI1Addr' : '#148', # Address match interrupt of address filter 1
+ 'TRX24_AMI2Addr' : '#150', # Address match interrupt of address filter 2
+ 'TRX24_AMI3Addr' : '#152', # Address match interrupt of address filter 3
+
+# Module ANALOG_COMPARATOR
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
+ 'ACSR' : '$50', # Analog Comparator Control And
+ 'ACSR_ACD': '$80', # Analog Comparator Disable
+ 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
+ 'ACSR_ACO': '$20', # Analog Compare Output
+ 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
+ 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
+ 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
+ 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
+ 'DIDR1' : '$7f', # Digital Input Disable Register
+ 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
+ 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
+
+# Module USART0
+ 'UDR0' : '$c6', # USART0 I/O Data Register
+ 'UCSR0A' : '$c0', # USART0 Control and Status Regi
+ 'UCSR0A_RXC0': '$80', # USART Receive Complete
+ 'UCSR0A_TXC0': '$40', # USART Transmit Complete
+ 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
+ 'UCSR0A_FE0': '$10', # Frame Error
+ 'UCSR0A_DOR0': '$8', # Data OverRun
+ 'UCSR0A_UPE0': '$4', # USART Parity Error
+ 'UCSR0A_U2X0': '$2', # Double the USART Transmission
+ 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
+ 'UCSR0B' : '$c1', # USART0 Control and Status Regi
+ 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
+ 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
+ 'UCSR0B_UDRIE0': '$20', # USART Data Register Empty Inte
+ 'UCSR0B_RXEN0': '$10', # Receiver Enable
+ 'UCSR0B_TXEN0': '$8', # Transmitter Enable
+ 'UCSR0B_UCSZ02': '$4', # Character Size
+ 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
+ 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
+ 'UCSR0C' : '$c2', # USART0 Control and Status Regi
+ 'UCSR0C_UMSEL0': '$c0', # USART Mode Select
+ 'UCSR0C_UPM0': '$30', # Parity Mode
+ 'UCSR0C_USBS0': '$8', # Stop Bit Select
+ 'UCSR0C_UCSZ0': '$6', # Character Size
+ 'UCSR0C_UCPOL0': '$1', # Clock Polarity
+ 'UBRR0' : '$c4', # USART0 Baud Rate Register Byt
+
+# Module USART1
+ 'UDR1' : '$ce', # USART1 I/O Data Register
+ 'UCSR1A' : '$c8', # USART1 Control and Status Regi
+ 'UCSR1A_RXC1': '$80', # USART Receive Complete
+ 'UCSR1A_TXC1': '$40', # USART Transmit Complete
+ 'UCSR1A_UDRE1': '$20', # USART Data Register Empty
+ 'UCSR1A_FE1': '$10', # Frame Error
+ 'UCSR1A_DOR1': '$8', # Data OverRun
+ 'UCSR1A_UPE1': '$4', # USART Parity Error
+ 'UCSR1A_U2X1': '$2', # Double the USART Transmission
+ 'UCSR1A_MPCM1': '$1', # Multi-processor Communication
+ 'UCSR1B' : '$c9', # USART1 Control and Status Regi
+ 'UCSR1B_RXCIE1': '$80', # RX Complete Interrupt Enable
+ 'UCSR1B_TXCIE1': '$40', # TX Complete Interrupt Enable
+ 'UCSR1B_UDRIE1': '$20', # USART Data Register Empty Inte
+ 'UCSR1B_RXEN1': '$10', # Receiver Enable
+ 'UCSR1B_TXEN1': '$8', # Transmitter Enable
+ 'UCSR1B_UCSZ12': '$4', # Character Size
+ 'UCSR1B_RXB81': '$2', # Receive Data Bit 8
+ 'UCSR1B_TXB81': '$1', # Transmit Data Bit 8
+ 'UCSR1C' : '$ca', # USART1 Control and Status Regi
+ 'UCSR1C_UMSEL1': '$c0', # USART Mode Select
+ 'UCSR1C_UPM1': '$30', # Parity Mode
+ 'UCSR1C_USBS1': '$8', # Stop Bit Select
+ 'UCSR1C_UCSZ1': '$6', # Character Size
+ 'UCSR1C_UCPOL1': '$1', # Clock Polarity
+ 'UBRR1' : '$cc', # USART1 Baud Rate Register Byt
+
+# Module TWI
+ 'TWAMR' : '$bd', # TWI (Slave) Address Mask Regis
+ 'TWAMR_TWAM': '$fe', # TWI Address Mask
+ 'TWAMR_Res': '$1', # Reserved Bit
+ 'TWBR' : '$b8', # TWI Bit Rate Register
+ 'TWCR' : '$bc', # TWI Control Register
+ 'TWCR_TWINT': '$80', # TWI Interrupt Flag
+ 'TWCR_TWEA': '$40', # TWI Enable Acknowledge Bit
+ 'TWCR_TWSTA': '$20', # TWI START Condition Bit
+ 'TWCR_TWSTO': '$10', # TWI STOP Condition Bit
+ 'TWCR_TWWC': '$8', # TWI Write Collision Flag
+ 'TWCR_TWEN': '$4', # TWI Enable Bit
+ 'TWCR_Res': '$2', # Reserved Bit
+ 'TWCR_TWIE': '$1', # TWI Interrupt Enable
+ 'TWSR' : '$b9', # TWI Status Register
+ 'TWSR_TWS': '$f8', # TWI Status
+ 'TWSR_Res': '$4', # Reserved Bit
+ 'TWSR_TWPS': '$3', # TWI Prescaler Bits
+ 'TWDR' : '$bb', # TWI Data Register
+ 'TWAR' : '$ba', # TWI (Slave) Address Register
+ 'TWAR_TWA': '$fe', # TWI (Slave) Address
+ 'TWAR_TWGCE': '$1', # TWI General Call Recognition E
+
+# Module SPI
+ 'SPCR' : '$4c', # SPI Control Register
+ 'SPCR_SPIE': '$80', # SPI Interrupt Enable
+ 'SPCR_SPE': '$40', # SPI Enable
+ 'SPCR_DORD': '$20', # Data Order
+ 'SPCR_MSTR': '$10', # Master/Slave Select
+ 'SPCR_CPOL': '$8', # Clock polarity
+ 'SPCR_CPHA': '$4', # Clock Phase
+ 'SPCR_SPR': '$3', # SPI Clock Rate Select 1 and 0
+ 'SPSR' : '$4d', # SPI Status Register
+ 'SPSR_SPIF': '$80', # SPI Interrupt Flag
+ 'SPSR_WCOL': '$40', # Write Collision Flag
+ 'SPSR_Res': '$3e', # Reserved
+ 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
+ 'SPDR' : '$4e', # SPI Data Register
+
+# Module PORTA
+ 'PORTA' : '$22', # Port A Data Register
+ 'DDRA' : '$21', # Port A Data Direction Register
+ 'PINA' : '$20', # Port A Input Pins Address
+
+# Module PORTB
+ 'PORTB' : '$25', # Port B Data Register
+ 'DDRB' : '$24', # Port B Data Direction Register
+ 'PINB' : '$23', # Port B Input Pins Address
+
+# Module PORTC
+ 'PORTC' : '$28', # Port C Data Register
+ 'DDRC' : '$27', # Port C Data Direction Register
+ 'PINC' : '$26', # Port C Input Pins Address
+
+# Module PORTD
+ 'PORTD' : '$2b', # Port D Data Register
+ 'DDRD' : '$2a', # Port D Data Direction Register
+ 'PIND' : '$29', # Port D Input Pins Address
+
+# Module PORTE
+ 'PORTE' : '$2e', # Port E Data Register
+ 'DDRE' : '$2d', # Port E Data Direction Register
+ 'PINE' : '$2c', # Port E Input Pins Address
+
+# Module PORTF
+ 'PORTF' : '$31', # Port F Data Register
+ 'DDRF' : '$30', # Port F Data Direction Register
+ 'PINF' : '$2f', # Port F Input Pins Address
+
+# Module PORTG
+ 'PORTG' : '$34', # Port G Data Register
+ 'DDRG' : '$33', # Port G Data Direction Register
+ 'PING' : '$32', # Port G Input Pins Address
+
+# Module TIMER_COUNTER_0
+ 'OCR0B' : '$48', # Timer/Counter0 Output Compare
+ 'OCR0A' : '$47', # Timer/Counter0 Output Compare
+ 'TCNT0' : '$46', # Timer/Counter0 Register
+ 'TCCR0B' : '$45', # Timer/Counter0 Control Registe
+ 'TCCR0B_FOC0A': '$80', # Force Output Compare A
+ 'TCCR0B_FOC0B': '$40', # Force Output Compare B
+ 'TCCR0B_Res': '$30', # Reserved Bit
+ 'TCCR0B_WGM02': '$8', #
+ 'TCCR0B_CS0': '$7', # Clock Select
+ 'TCCR0A' : '$44', # Timer/Counter0 Control Registe
+ 'TCCR0A_COM0A': '$c0', # Compare Match Output A Mode
+ 'TCCR0A_COM0B': '$30', # Compare Match Output B Mode
+ 'TCCR0A_Res': '$c', # Reserved Bit
+ 'TCCR0A_WGM0': '$3', # Waveform Generation Mode
+ 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
+ 'TIMSK0_Res': '$f8', # Reserved
+ 'TIMSK0_OCIE0B': '$4', # Timer/Counter0 Output Compare
+ 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
+ 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
+ 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
+ 'TIFR0_Res': '$f8', # Reserved
+ 'TIFR0_OCF0B': '$4', # Timer/Counter0 Output Compare
+ 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
+ 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_Res': '$7c', # Reserved
+ 'GTCCR_PSRASY': '$2', # Prescaler Reset Timer/Counter2
+ 'GTCCR_PSRSYNC': '$1', # Prescaler Reset for Synchronou
+
+# Module TIMER_COUNTER_2
+ 'TIMSK2' : '$70', # Timer/Counter Interrupt Mask r
+ 'TIMSK2_Res': '$f8', # Reserved Bit
+ 'TIMSK2_OCIE2B': '$4', # Timer/Counter2 Output Compare
+ 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
+ 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
+ 'TIFR2' : '$37', # Timer/Counter Interrupt Flag R
+ 'TIFR2_Res': '$f8', # Reserved Bit
+ 'TIFR2_OCF2B': '$4', # Output Compare Flag 2 B
+ 'TIFR2_OCF2A': '$2', # Output Compare Flag 2 A
+ 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
+ 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
+ 'TCCR2A_COM2A': '$c0', # Compare Match Output A Mode
+ 'TCCR2A_COM2B': '$30', # Compare Match Output B Mode
+ 'TCCR2A_Res': '$c', # Reserved
+ 'TCCR2A_WGM2': '$3', # Waveform Generation Mode
+ 'TCCR2B' : '$b1', # Timer/Counter2 Control Registe
+ 'TCCR2B_FOC2A': '$80', # Force Output Compare A
+ 'TCCR2B_FOC2B': '$40', # Force Output Compare B
+ 'TCCR2B_Res': '$30', # Reserved
+ 'TCCR2B_WGM22': '$8', # Waveform Generation Mode
+ 'TCCR2B_CS2': '$7', # Clock Select
+ 'TCNT2' : '$b2', # Timer/Counter2
+ 'OCR2B' : '$b4', # Timer/Counter2 Output Compare
+ 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
+ 'ASSR' : '$b6', # Asynchronous Status Register
+ 'ASSR_EXCLKAMR': '$80', # Enable External Clock Input fo
+ 'ASSR_EXCLK': '$40', # Enable External Clock Input
+ 'ASSR_AS2': '$20', # Timer/Counter2 Asynchronous Mo
+ 'ASSR_TCN2UB': '$10', # Timer/Counter2 Update Busy
+ 'ASSR_OCR2AUB': '$8', # Timer/Counter2 Output Compare
+ 'ASSR_OCR2BUB': '$4', # Timer/Counter2 Output Compare
+ 'ASSR_TCR2AUB': '$2', # Timer/Counter2 Control Registe
+ 'ASSR_TCR2BUB': '$1', # Timer/Counter2 Control Registe
+ 'GTCCR' : '$43', # General Timer Counter Control
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSRASY': '$2', # Prescaler Reset Timer/Counter2
+
+# Module WATCHDOG
+ 'WDTCSR' : '$60', # Watchdog Timer Control Registe
+ 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
+ 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
+ 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
+ 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
+ 'WDTCSR_WDE': '$8', # Watch Dog Enable
+
+# Module TIMER_COUNTER_5
+ 'TCCR5A' : '$120', # Timer/Counter5 Control Registe
+ 'TCCR5A_COM5A': '$c0', # Compare Output Mode for Channe
+ 'TCCR5A_COM5B': '$30', # Compare Output Mode for Channe
+ 'TCCR5A_COM5C': '$c', # Compare Output Mode for Channe
+ 'TCCR5A_WGM5': '$3', # Waveform Generation Mode
+ 'TCCR5B' : '$121', # Timer/Counter5 Control Registe
+ 'TCCR5B_ICNC5': '$80', # Input Capture 5 Noise Cancelle
+ 'TCCR5B_ICES5': '$40', # Input Capture 5 Edge Select
+ 'TCCR5B_Res': '$20', # Reserved Bit
+ 'TCCR5B_WGM5': '$18', # Waveform Generation Mode
+ 'TCCR5B_CS5': '$7', # Clock Select
+ 'TCCR5C' : '$122', # Timer/Counter5 Control Registe
+ 'TCCR5C_FOC5A': '$80', # Force Output Compare for Chann
+ 'TCCR5C_FOC5B': '$40', # Force Output Compare for Chann
+ 'TCCR5C_FOC5C': '$20', # Force Output Compare for Chann
+ 'TCCR5C_Res': '$1f', # Reserved
+ 'TCNT5' : '$124', # Timer/Counter5 Bytes
+ 'OCR5A' : '$128', # Timer/Counter5 Output Compare
+ 'OCR5B' : '$12a', # Timer/Counter5 Output Compare
+ 'OCR5C' : '$12c', # Timer/Counter5 Output Compare
+ 'ICR5' : '$126', # Timer/Counter5 Input Capture R
+ 'TIMSK5' : '$73', # Timer/Counter5 Interrupt Mask
+ 'TIMSK5_Res': '$c0', # Reserved Bit
+ 'TIMSK5_ICIE5': '$20', # Timer/Counter5 Input Capture I
+ 'TIMSK5_Res': '$10', # Reserved Bit
+ 'TIMSK5_OCIE5C': '$8', # Timer/Counter5 Output Compare
+ 'TIMSK5_OCIE5B': '$4', # Timer/Counter5 Output Compare
+ 'TIMSK5_OCIE5A': '$2', # Timer/Counter5 Output Compare
+ 'TIMSK5_TOIE5': '$1', # Timer/Counter5 Overflow Interr
+ 'TIFR5' : '$3a', # Timer/Counter5 Interrupt Flag
+ 'TIFR5_Res': '$c0', # Reserved Bit
+ 'TIFR5_ICF5': '$20', # Timer/Counter5 Input Capture F
+ 'TIFR5_Res': '$10', # Reserved Bit
+ 'TIFR5_OCF5C': '$8', # Timer/Counter5 Output Compare
+ 'TIFR5_OCF5B': '$4', # Timer/Counter5 Output Compare
+ 'TIFR5_OCF5A': '$2', # Timer/Counter5 Output Compare
+ 'TIFR5_TOV5': '$1', # Timer/Counter5 Overflow Flag
+
+# Module TIMER_COUNTER_4
+ 'TCCR4A' : '$a0', # Timer/Counter4 Control Registe
+ 'TCCR4A_COM4A': '$c0', # Compare Output Mode for Channe
+ 'TCCR4A_COM4B': '$30', # Compare Output Mode for Channe
+ 'TCCR4A_COM4C': '$c', # Compare Output Mode for Channe
+ 'TCCR4A_WGM4': '$3', # Waveform Generation Mode
+ 'TCCR4B' : '$a1', # Timer/Counter4 Control Registe
+ 'TCCR4B_ICNC4': '$80', # Input Capture 4 Noise Cancelle
+ 'TCCR4B_ICES4': '$40', # Input Capture 4 Edge Select
+ 'TCCR4B_Res': '$20', # Reserved Bit
+ 'TCCR4B_WGM4': '$18', # Waveform Generation Mode
+ 'TCCR4B_CS4': '$7', # Clock Select
+ 'TCCR4C' : '$a2', # Timer/Counter4 Control Registe
+ 'TCCR4C_FOC4A': '$80', # Force Output Compare for Chann
+ 'TCCR4C_FOC4B': '$40', # Force Output Compare for Chann
+ 'TCCR4C_FOC4C': '$20', # Force Output Compare for Chann
+ 'TCCR4C_Res': '$1f', # Reserved
+ 'TCNT4' : '$a4', # Timer/Counter4 Bytes
+ 'OCR4A' : '$a8', # Timer/Counter4 Output Compare
+ 'OCR4B' : '$aa', # Timer/Counter4 Output Compare
+ 'OCR4C' : '$ac', # Timer/Counter4 Output Compare
+ 'ICR4' : '$a6', # Timer/Counter4 Input Capture R
+ 'TIMSK4' : '$72', # Timer/Counter4 Interrupt Mask
+ 'TIMSK4_Res': '$c0', # Reserved Bit
+ 'TIMSK4_ICIE4': '$20', # Timer/Counter4 Input Capture I
+ 'TIMSK4_Res': '$10', # Reserved Bit
+ 'TIMSK4_OCIE4C': '$8', # Timer/Counter4 Output Compare
+ 'TIMSK4_OCIE4B': '$4', # Timer/Counter4 Output Compare
+ 'TIMSK4_OCIE4A': '$2', # Timer/Counter4 Output Compare
+ 'TIMSK4_TOIE4': '$1', # Timer/Counter4 Overflow Interr
+ 'TIFR4' : '$39', # Timer/Counter4 Interrupt Flag
+ 'TIFR4_Res': '$c0', # Reserved Bit
+ 'TIFR4_ICF4': '$20', # Timer/Counter4 Input Capture F
+ 'TIFR4_Res': '$10', # Reserved Bit
+ 'TIFR4_OCF4C': '$8', # Timer/Counter4 Output Compare
+ 'TIFR4_OCF4B': '$4', # Timer/Counter4 Output Compare
+ 'TIFR4_OCF4A': '$2', # Timer/Counter4 Output Compare
+ 'TIFR4_TOV4': '$1', # Timer/Counter4 Overflow Flag
+
+# Module TIMER_COUNTER_3
+ 'TCCR3A' : '$90', # Timer/Counter3 Control Registe
+ 'TCCR3A_COM3A': '$c0', # Compare Output Mode for Channe
+ 'TCCR3A_COM3B': '$30', # Compare Output Mode for Channe
+ 'TCCR3A_COM3C': '$c', # Compare Output Mode for Channe
+ 'TCCR3A_WGM3': '$3', # Waveform Generation Mode
+ 'TCCR3B' : '$91', # Timer/Counter3 Control Registe
+ 'TCCR3B_ICNC3': '$80', # Input Capture 3 Noise Cancelle
+ 'TCCR3B_ICES3': '$40', # Input Capture 3 Edge Select
+ 'TCCR3B_Res': '$20', # Reserved Bit
+ 'TCCR3B_WGM3': '$18', # Waveform Generation Mode
+ 'TCCR3B_CS3': '$7', # Clock Select
+ 'TCCR3C' : '$92', # Timer/Counter3 Control Registe
+ 'TCCR3C_FOC3A': '$80', # Force Output Compare for Chann
+ 'TCCR3C_FOC3B': '$40', # Force Output Compare for Chann
+ 'TCCR3C_FOC3C': '$20', # Force Output Compare for Chann
+ 'TCCR3C_Res': '$1f', # Reserved
+ 'TCNT3' : '$94', # Timer/Counter3 Bytes
+ 'OCR3A' : '$98', # Timer/Counter3 Output Compare
+ 'OCR3B' : '$9a', # Timer/Counter3 Output Compare
+ 'OCR3C' : '$9c', # Timer/Counter3 Output Compare
+ 'ICR3' : '$96', # Timer/Counter3 Input Capture R
+ 'TIMSK3' : '$71', # Timer/Counter3 Interrupt Mask
+ 'TIMSK3_Res': '$c0', # Reserved Bit
+ 'TIMSK3_ICIE3': '$20', # Timer/Counter3 Input Capture I
+ 'TIMSK3_Res': '$10', # Reserved Bit
+ 'TIMSK3_OCIE3C': '$8', # Timer/Counter3 Output Compare
+ 'TIMSK3_OCIE3B': '$4', # Timer/Counter3 Output Compare
+ 'TIMSK3_OCIE3A': '$2', # Timer/Counter3 Output Compare
+ 'TIMSK3_TOIE3': '$1', # Timer/Counter3 Overflow Interr
+ 'TIFR3' : '$38', # Timer/Counter3 Interrupt Flag
+ 'TIFR3_Res': '$c0', # Reserved Bit
+ 'TIFR3_ICF3': '$20', # Timer/Counter3 Input Capture F
+ 'TIFR3_Res': '$10', # Reserved Bit
+ 'TIFR3_OCF3C': '$8', # Timer/Counter3 Output Compare
+ 'TIFR3_OCF3B': '$4', # Timer/Counter3 Output Compare
+ 'TIFR3_OCF3A': '$2', # Timer/Counter3 Output Compare
+ 'TIFR3_TOV3': '$1', # Timer/Counter3 Overflow Flag
+
+# Module TIMER_COUNTER_1
+ 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
+ 'TCCR1A_COM1A': '$c0', # Compare Output Mode for Channe
+ 'TCCR1A_COM1B': '$30', # Compare Output Mode for Channe
+ 'TCCR1A_COM1C': '$c', # Compare Output Mode for Channe
+ 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
+ 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
+ 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Cancelle
+ 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
+ 'TCCR1B_Res': '$20', # Reserved Bit
+ 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
+ 'TCCR1B_CS1': '$7', # Clock Select
+ 'TCCR1C' : '$82', # Timer/Counter1 Control Registe
+ 'TCCR1C_FOC1A': '$80', # Force Output Compare for Chann
+ 'TCCR1C_FOC1B': '$40', # Force Output Compare for Chann
+ 'TCCR1C_FOC1C': '$20', # Force Output Compare for Chann
+ 'TCCR1C_Res': '$1f', # Reserved
+ 'TCNT1' : '$84', # Timer/Counter1 Bytes
+ 'OCR1A' : '$88', # Timer/Counter1 Output Compare
+ 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
+ 'OCR1C' : '$8c', # Timer/Counter1 Output Compare
+ 'ICR1' : '$86', # Timer/Counter1 Input Capture R
+ 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
+ 'TIMSK1_Res': '$c0', # Reserved Bit
+ 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
+ 'TIMSK1_Res': '$10', # Reserved Bit
+ 'TIMSK1_OCIE1C': '$8', # Timer/Counter1 Output Compare
+ 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
+ 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
+ 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
+ 'TIFR1' : '$36', # Timer/Counter1 Interrupt Flag
+ 'TIFR1_Res': '$c0', # Reserved Bit
+ 'TIFR1_ICF1': '$20', # Timer/Counter1 Input Capture F
+ 'TIFR1_Res': '$10', # Reserved Bit
+ 'TIFR1_OCF1C': '$8', # Timer/Counter1 Output Compare
+ 'TIFR1_OCF1B': '$4', # Timer/Counter1 Output Compare
+ 'TIFR1_OCF1A': '$2', # Timer/Counter1 Output Compare
+ 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
+
+# Module TRX24
+ 'PARCR' : '$138', # Power Amplifier Ramp up/down C
+ 'PARCR_PALTD': '$e0', # ext. PA Ramp Down Lead Time
+ 'PARCR_PALTU': '$1c', # ext. PA Ramp Up Lead Time
+ 'PARCR_PARDFI': '$2', # Power Amplifier Ramp Down Freq
+ 'PARCR_PARUFI': '$1', # Power Amplifier Ramp Up Freque
+ 'MAFSA0L' : '$10e', # Transceiver MAC Short Address
+ 'MAFSA0L_MAFSA0L': '$ff', # MAC Short Address low Byte for
+ 'MAFSA0H' : '$10f', # Transceiver MAC Short Address
+ 'MAFSA0H_MAFSA0H': '$ff', # MAC Short Address high Byte fo
+ 'MAFPA0L' : '$110', # Transceiver Personal Area Netw
+ 'MAFPA0L_MAFPA0L': '$ff', # MAC Personal Area Network ID l
+ 'MAFPA0H' : '$111', # Transceiver Personal Area Netw
+ 'MAFPA0H_MAFPA0H': '$ff', # MAC Personal Area Network ID h
+ 'MAFSA1L' : '$112', # Transceiver MAC Short Address
+ 'MAFSA1L_MAFSA1L': '$ff', # MAC Short Address low Byte for
+ 'MAFSA1H' : '$113', # Transceiver MAC Short Address
+ 'MAFSA1H_MAFSA1H': '$ff', # MAC Short Address high Byte fo
+ 'MAFPA1L' : '$114', # Transceiver Personal Area Netw
+ 'MAFPA1L_MAFPA1L': '$ff', # MAC Personal Area Network ID l
+ 'MAFPA1H' : '$115', # Transceiver Personal Area Netw
+ 'MAFPA1H_MAFPA1H': '$ff', # MAC Personal Area Network ID h
+ 'MAFSA2L' : '$116', # Transceiver MAC Short Address
+ 'MAFSA2L_MAFSA2L': '$ff', # MAC Short Address low Byte for
+ 'MAFSA2H' : '$117', # Transceiver MAC Short Address
+ 'MAFSA2H_MAFSA2H': '$ff', # MAC Short Address high Byte fo
+ 'MAFPA2L' : '$118', # Transceiver Personal Area Netw
+ 'MAFPA2L_MAFPA2L': '$ff', # MAC Personal Area Network ID l
+ 'MAFPA2H' : '$119', # Transceiver Personal Area Netw
+ 'MAFPA2H_MAFPA2H': '$ff', # MAC Personal Area Network ID h
+ 'MAFSA3L' : '$11a', # Transceiver MAC Short Address
+ 'MAFSA3L_MAFSA3L': '$ff', # MAC Short Address low Byte for
+ 'MAFSA3H' : '$11b', # Transceiver MAC Short Address
+ 'MAFSA3H_MAFSA3H': '$ff', # MAC Short Address high Byte fo
+ 'MAFPA3L' : '$11c', # Transceiver Personal Area Netw
+ 'MAFPA3L_MAFPA3L': '$ff', # MAC Personal Area Network ID l
+ 'MAFPA3H' : '$11d', # Transceiver Personal Area Netw
+ 'MAFPA3H_MAFPA3H': '$ff', # MAC Personal Area Network ID h
+ 'MAFCR0' : '$10c', # Multiple Address Filter Config
+ 'MAFCR0_Res': '$f0', # Reserved Bit
+ 'MAFCR0_MAF3EN': '$8', # Multiple Address Filter 3 Enab
+ 'MAFCR0_MAF2EN': '$4', # Multiple Address Filter 2 Enab
+ 'MAFCR0_MAF1EN': '$2', # Multiple Address Filter 1 Enab
+ 'MAFCR0_MAF0EN': '$1', # Multiple Address Filter 0 Enab
+ 'MAFCR1' : '$10d', # Multiple Address Filter Config
+ 'MAFCR1_AACK_3_SET_PD': '$80', # Set Data Pending bit for addre
+ 'MAFCR1_AACK_3_I_AM_COORD': '$40', # Enable PAN Coordinator mode fo
+ 'MAFCR1_AACK_2_SET_PD': '$20', # Set Data Pending bit for addre
+ 'MAFCR1_AACK_2_I_AM_COORD': '$10', # Enable PAN Coordinator mode fo
+ 'MAFCR1_AACK_1_SET_PD': '$8', # Set Data Pending bit for addre
+ 'MAFCR1_AACK_1_I_AM_COORD': '$4', # Enable PAN Coordinator mode fo
+ 'MAFCR1_AACK_0_SET_PD': '$2', # Set Data Pending bit for addre
+ 'MAFCR1_AACK_0_I_AM_COORD': '$1', # Enable PAN Coordinator mode fo
+ 'AES_CTRL' : '$13c', # AES Control Register
+ 'AES_CTRL_AES_REQUEST': '$80', # Request AES Operation.
+ 'AES_CTRL_Res': '$40', # Reserved Bit
+ 'AES_CTRL_AES_MODE': '$20', # Set AES Operation Mode
+ 'AES_CTRL_Res': '$10', # Reserved Bit
+ 'AES_CTRL_AES_DIR': '$8', # Set AES Operation Direction
+ 'AES_CTRL_AES_IM': '$4', # AES Interrupt Enable
+ 'AES_CTRL_Res': '$3', # Reserved Bit
+ 'AES_STATUS' : '$13d', # AES Status Register
+ 'AES_STATUS_AES_ER': '$80', # AES Operation Finished with Er
+ 'AES_STATUS_Res': '$7e', # Reserved
+ 'AES_STATUS_AES_DONE': '$1', # AES Operation Finished with Su
+ 'AES_STATE' : '$13e', # AES Plain and Cipher Text Buff
+ 'AES_STATE_AES_STATE': '$ff', # AES Plain and Cipher Text Buff
+ 'AES_KEY' : '$13f', # AES Encryption and Decryption
+ 'AES_KEY_AES_KEY': '$ff', # AES Encryption/Decryption Key
+ 'TRX_STATUS' : '$141', # Transceiver Status Register
+ 'TRX_STATUS_CCA_DONE': '$80', # CCA Algorithm Status
+ 'TRX_STATUS_CCA_STATUS': '$40', # CCA Status Result
+ 'TRX_STATUS_TST_STATUS': '$20', # Test mode status
+ 'TRX_STATUS_TRX_STATUS': '$1f', # Transceiver Main Status
+ 'TRX_STATE' : '$142', # Transceiver State Control Regi
+ 'TRX_STATE_TRAC_STATUS': '$e0', # Transaction Status
+ 'TRX_STATE_TRX_CMD': '$1f', # State Control Command
+ 'TRX_CTRL_0' : '$143', # Reserved
+ 'TRX_CTRL_0_Res7': '$80', # Reserved
+ 'TRX_CTRL_0_PMU_EN': '$40', # Enable Phase Measurement Unit
+ 'TRX_CTRL_0_PMU_START': '$20', # Start of Phase Measurement Uni
+ 'TRX_CTRL_0_PMU_IF_INV': '$10', # PMU IF Inverse
+ 'TRX_CTRL_0_Res': '$f', # Reserved
+ 'TRX_CTRL_1' : '$144', # Transceiver Control Register 1
+ 'TRX_CTRL_1_PA_EXT_EN': '$80', # External PA support enable
+ 'TRX_CTRL_1_IRQ_2_EXT_EN': '$40', # Connect Frame Start IRQ to TC1
+ 'TRX_CTRL_1_TX_AUTO_CRC_ON': '$20', # Enable Automatic CRC Calculati
+ 'TRX_CTRL_1_PLL_TX_FLT': '$10', # Enable PLL TX filter
+ 'TRX_CTRL_1_Res': '$f', # Reserved
+ 'PHY_TX_PWR' : '$145', # Transceiver Transmit Power Con
+ 'PHY_TX_PWR_Res': '$f0', # Reserved
+ 'PHY_TX_PWR_TX_PWR': '$f', # Transmit Power Setting
+ 'PHY_RSSI' : '$146', # Receiver Signal Strength Indic
+ 'PHY_RSSI_RX_CRC_VALID': '$80', # Received Frame CRC Status
+ 'PHY_RSSI_RND_VALUE': '$60', # Random Value
+ 'PHY_RSSI_RSSI': '$1f', # Receiver Signal Strength Indic
+ 'PHY_ED_LEVEL' : '$147', # Transceiver Energy Detection L
+ 'PHY_ED_LEVEL_ED_LEVEL': '$ff', # Energy Detection Level
+ 'PHY_CC_CCA' : '$148', # Transceiver Clear Channel Asse
+ 'PHY_CC_CCA_CCA_REQUEST': '$80', # Manual CCA Measurement Request
+ 'PHY_CC_CCA_CCA_MODE': '$60', # Select CCA Measurement Mode
+ 'PHY_CC_CCA_CHANNEL': '$1f', # RX/TX Channel Selection
+ 'CCA_THRES' : '$149', # Transceiver CCA Threshold Sett
+ 'CCA_THRES_CCA_CS_THRES': '$f0', # CS Threshold Level for CCA Mea
+ 'CCA_THRES_CCA_ED_THRES': '$f', # ED Threshold Level for CCA Mea
+ 'RX_CTRL' : '$14a', # Transceiver Receive Control Re
+ 'RX_CTRL_PDT_THRES': '$f', # Receiver Sensitivity Control
+ 'SFD_VALUE' : '$14b', # Start of Frame Delimiter Value
+ 'SFD_VALUE_SFD_VALUE': '$ff', # Start of Frame Delimiter Value
+ 'TRX_CTRL_2' : '$14c', # Transceiver Control Register 2
+ 'TRX_CTRL_2_RX_SAFE_MODE': '$80', # RX Safe Mode
+ 'TRX_CTRL_2_Res': '$7c', # Reserved
+ 'TRX_CTRL_2_OQPSK_DATA_RATE': '$3', # Data Rate Selection
+ 'ANT_DIV' : '$14d', # Antenna Diversity Control Regi
+ 'ANT_DIV_ANT_SEL': '$80', # Antenna Diversity Antenna Stat
+ 'ANT_DIV_Res': '$70', # Reserved
+ 'ANT_DIV_ANT_DIV_EN': '$8', # Enable Antenna Diversity
+ 'ANT_DIV_ANT_EXT_SW_EN': '$4', # Enable External Antenna Switch
+ 'ANT_DIV_ANT_CTRL': '$3', # Static Antenna Diversity Switc
+ 'IRQ_MASK' : '$14e', # Transceiver Interrupt Enable R
+ 'IRQ_MASK_AWAKE_EN': '$80', # Awake Interrupt Enable
+ 'IRQ_MASK_TX_END_EN': '$40', # TX_END Interrupt Enable
+ 'IRQ_MASK_AMI_EN': '$20', # Address Match Interrupt Enable
+ 'IRQ_MASK_CCA_ED_DONE_EN': '$10', # End of ED Measurement Interrup
+ 'IRQ_MASK_RX_END_EN': '$8', # RX_END Interrupt Enable
+ 'IRQ_MASK_RX_START_EN': '$4', # RX_START Interrupt Enable
+ 'IRQ_MASK_PLL_UNLOCK_EN': '$2', # PLL Unlock Interrupt Enable
+ 'IRQ_MASK_PLL_LOCK_EN': '$1', # PLL Lock Interrupt Enable
+ 'IRQ_STATUS' : '$14f', # Transceiver Interrupt Status R
+ 'IRQ_STATUS_AWAKE': '$80', # Awake Interrupt Status
+ 'IRQ_STATUS_TX_END': '$40', # TX_END Interrupt Status
+ 'IRQ_STATUS_AMI': '$20', # Address Match Interrupt Status
+ 'IRQ_STATUS_CCA_ED_DONE': '$10', # End of ED Measurement Interrup
+ 'IRQ_STATUS_RX_END': '$8', # RX_END Interrupt Status
+ 'IRQ_STATUS_RX_START': '$4', # RX_START Interrupt Status
+ 'IRQ_STATUS_PLL_UNLOCK': '$2', # PLL Unlock Interrupt Status
+ 'IRQ_STATUS_PLL_LOCK': '$1', # PLL Lock Interrupt Status
+ 'IRQ_MASK1' : '$be', # Transceiver Interrupt Enable R
+ 'IRQ_MASK1_Res': '$e0', # Reserved Bit
+ 'IRQ_MASK1_MAF_3_AMI_EN': '$10', # Address Match Interrupt enable
+ 'IRQ_MASK1_MAF_2_AMI_EN': '$8', # Address Match Interrupt enable
+ 'IRQ_MASK1_MAF_1_AMI_EN': '$4', # Address Match Interrupt enable
+ 'IRQ_MASK1_MAF_0_AMI_EN': '$2', # Address Match Interrupt enable
+ 'IRQ_MASK1_TX_START_EN': '$1', # Transmit Start Interrupt enabl
+ 'IRQ_STATUS1' : '$bf', # Transceiver Interrupt Status R
+ 'IRQ_STATUS1_Res': '$e0', # Reserved Bit
+ 'IRQ_STATUS1_MAF_3_AMI': '$10', # Address Match Interrupt Status
+ 'IRQ_STATUS1_MAF_2_AMI': '$8', # Address Match Interrupt Status
+ 'IRQ_STATUS1_MAF_1_AMI': '$4', # Address Match Interrupt Status
+ 'IRQ_STATUS1_MAF_0_AMI': '$2', # Address Match Interrupt Status
+ 'IRQ_STATUS1_TX_START': '$1', # Transmit Start Interrupt Statu
+ 'VREG_CTRL' : '$150', # Voltage Regulator Control and
+ 'VREG_CTRL_AVREG_EXT': '$80', # Use External AVDD Regulator
+ 'VREG_CTRL_AVDD_OK': '$40', # AVDD Supply Voltage Valid
+ 'VREG_CTRL_DVREG_EXT': '$8', # Use External DVDD Regulator
+ 'VREG_CTRL_DVDD_OK': '$4', # DVDD Supply Voltage Valid
+ 'BATMON' : '$151', # Battery Monitor Control and St
+ 'BATMON_BAT_LOW': '$80', # Battery Monitor Interrupt Stat
+ 'BATMON_BAT_LOW_EN': '$40', # Battery Monitor Interrupt Enab
+ 'BATMON_BATMON_OK': '$20', # Battery Monitor Status
+ 'BATMON_BATMON_HR': '$10', # Battery Monitor Voltage Range
+ 'BATMON_BATMON_VTH': '$f', # Battery Monitor Threshold Volt
+ 'XOSC_CTRL' : '$152', # Crystal Oscillator Control Reg
+ 'XOSC_CTRL_XTAL_MODE': '$f0', # Crystal Oscillator Operating M
+ 'XOSC_CTRL_XTAL_TRIM': '$f', # Crystal Oscillator Load Capaci
+ 'CC_CTRL_0' : '$153', # Channel Control Register 0
+ 'CC_CTRL_0_CC_NUMBER': '$ff', # Channel Number
+ 'CC_CTRL_1' : '$154', # Channel Control Register 1
+ 'CC_CTRL_1_CC_BAND': '$f', # Channel Band
+ 'RX_SYN' : '$155', # Transceiver Receiver Sensitivi
+ 'RX_SYN_RX_PDT_DIS': '$80', # Prevent Frame Reception
+ 'RX_SYN_RX_OVERRIDE': '$40', # Receiver Override Function
+ 'RX_SYN_Res': '$30', # Reserved
+ 'RX_SYN_RX_PDT_LEVEL': '$f', # Reduce Receiver Sensitivity
+ 'TRX_RPC' : '$156', # Transceiver Reduced Power Cons
+ 'TRX_RPC_RX_RPC_CTRL': '$c0', # Smart Receiving Mode Timing
+ 'TRX_RPC_RX_RPC_EN': '$20', # Reciver Smart Receiving Mode E
+ 'TRX_RPC_PDT_RPC_EN': '$10', # Smart Receiving Mode Reduced S
+ 'TRX_RPC_PLL_RPC_EN': '$8', # PLL Smart Receiving Mode Enabl
+ 'TRX_RPC_Res0': '$4', # Reserved
+ 'TRX_RPC_IPAN_RPC_EN': '$2', # Smart Receiving Mode IPAN Hand
+ 'TRX_RPC_XAH_RPC_EN': '$1', # Smart Receiving in Extended Op
+ 'XAH_CTRL_1' : '$157', # Transceiver Acknowledgment Fra
+ 'XAH_CTRL_1_Res': '$c0', # Reserved Bit
+ 'XAH_CTRL_1_AACK_FLTR_RES_FT': '$20', # Filter Reserved Frames
+ 'XAH_CTRL_1_AACK_UPLD_RES_FT': '$10', # Process Reserved Frames
+ 'XAH_CTRL_1_Res': '$8', # Reserved Bit
+ 'XAH_CTRL_1_AACK_ACK_TIME': '$4', # Reduce Acknowledgment Time
+ 'XAH_CTRL_1_AACK_PROM_MODE': '$2', # Enable Promiscuous Mode
+ 'XAH_CTRL_1_Res': '$1', # Reserved Bit
+ 'FTN_CTRL' : '$158', # Transceiver Filter Tuning Cont
+ 'FTN_CTRL_FTN_START': '$80', # Start Calibration Loop of Filt
+ 'PLL_CF' : '$15a', # Transceiver Center Frequency C
+ 'PLL_CF_PLL_CF_START': '$80', # Start Center Frequency Calibra
+ 'PLL_DCU' : '$15b', # Transceiver Delay Cell Calibra
+ 'PLL_DCU_PLL_DCU_START': '$80', # Start Delay Cell Calibration
+ 'PART_NUM' : '$15c', # Device Identification Register
+ 'PART_NUM_PART_NUM': '$ff', # Part Number
+ 'VERSION_NUM' : '$15d', # Device Identification Register
+ 'VERSION_NUM_VERSION_NUM': '$ff', # Version Number
+ 'MAN_ID_0' : '$15e', # Device Identification Register
+ 'MAN_ID_0_MAN_ID_07': '$80', # Manufacturer ID (Low Byte)
+ 'MAN_ID_0_MAN_ID_06': '$40', # Manufacturer ID (Low Byte)
+ 'MAN_ID_0_MAN_ID_05': '$20', # Manufacturer ID (Low Byte)
+ 'MAN_ID_0_MAN_ID_04': '$10', # Manufacturer ID (Low Byte)
+ 'MAN_ID_0_MAN_ID_03': '$8', # Manufacturer ID (Low Byte)
+ 'MAN_ID_0_MAN_ID_02': '$4', # Manufacturer ID (Low Byte)
+ 'MAN_ID_0_MAN_ID_01': '$2', # Manufacturer ID (Low Byte)
+ 'MAN_ID_0_MAN_ID_00': '$1', # Manufacturer ID (Low Byte)
+ 'MAN_ID_1' : '$15f', # Device Identification Register
+ 'MAN_ID_1_MAN_ID_': '$ff', # Manufacturer ID (High Byte)
+ 'SHORT_ADDR_0' : '$160', # Transceiver MAC Short Address
+ 'SHORT_ADDR_0_SHORT_ADDR_07': '$80', # MAC Short Address
+ 'SHORT_ADDR_0_SHORT_ADDR_06': '$40', # MAC Short Address
+ 'SHORT_ADDR_0_SHORT_ADDR_05': '$20', # MAC Short Address
+ 'SHORT_ADDR_0_SHORT_ADDR_04': '$10', # MAC Short Address
+ 'SHORT_ADDR_0_SHORT_ADDR_03': '$8', # MAC Short Address
+ 'SHORT_ADDR_0_SHORT_ADDR_02': '$4', # MAC Short Address
+ 'SHORT_ADDR_0_SHORT_ADDR_01': '$2', # MAC Short Address
+ 'SHORT_ADDR_0_SHORT_ADDR_00': '$1', # MAC Short Address
+ 'SHORT_ADDR_1' : '$161', # Transceiver MAC Short Address
+ 'SHORT_ADDR_1_SHORT_ADDR_': '$ff', # MAC Short Address
+ 'PAN_ID_0' : '$162', # Transceiver Personal Area Netw
+ 'PAN_ID_0_PAN_ID_07': '$80', # MAC Personal Area Network ID
+ 'PAN_ID_0_PAN_ID_06': '$40', # MAC Personal Area Network ID
+ 'PAN_ID_0_PAN_ID_05': '$20', # MAC Personal Area Network ID
+ 'PAN_ID_0_PAN_ID_04': '$10', # MAC Personal Area Network ID
+ 'PAN_ID_0_PAN_ID_03': '$8', # MAC Personal Area Network ID
+ 'PAN_ID_0_PAN_ID_02': '$4', # MAC Personal Area Network ID
+ 'PAN_ID_0_PAN_ID_01': '$2', # MAC Personal Area Network ID
+ 'PAN_ID_0_PAN_ID_00': '$1', # MAC Personal Area Network ID
+ 'PAN_ID_1' : '$163', # Transceiver Personal Area Netw
+ 'PAN_ID_1_PAN_ID_': '$ff', # MAC Personal Area Network ID
+ 'IEEE_ADDR_0' : '$164', # Transceiver MAC IEEE Address R
+ 'IEEE_ADDR_0_IEEE_ADDR_07': '$80', # MAC IEEE Address
+ 'IEEE_ADDR_0_IEEE_ADDR_06': '$40', # MAC IEEE Address
+ 'IEEE_ADDR_0_IEEE_ADDR_05': '$20', # MAC IEEE Address
+ 'IEEE_ADDR_0_IEEE_ADDR_04': '$10', # MAC IEEE Address
+ 'IEEE_ADDR_0_IEEE_ADDR_03': '$8', # MAC IEEE Address
+ 'IEEE_ADDR_0_IEEE_ADDR_02': '$4', # MAC IEEE Address
+ 'IEEE_ADDR_0_IEEE_ADDR_01': '$2', # MAC IEEE Address
+ 'IEEE_ADDR_0_IEEE_ADDR_00': '$1', # MAC IEEE Address
+ 'IEEE_ADDR_1' : '$165', # Transceiver MAC IEEE Address R
+ 'IEEE_ADDR_1_IEEE_ADDR_': '$ff', # MAC IEEE Address
+ 'IEEE_ADDR_2' : '$166', # Transceiver MAC IEEE Address R
+ 'IEEE_ADDR_2_IEEE_ADDR_': '$ff', # MAC IEEE Address
+ 'IEEE_ADDR_3' : '$167', # Transceiver MAC IEEE Address R
+ 'IEEE_ADDR_3_IEEE_ADDR_': '$ff', # MAC IEEE Address
+ 'IEEE_ADDR_4' : '$168', # Transceiver MAC IEEE Address R
+ 'IEEE_ADDR_4_IEEE_ADDR_': '$ff', # MAC IEEE Address
+ 'IEEE_ADDR_5' : '$169', # Transceiver MAC IEEE Address R
+ 'IEEE_ADDR_5_IEEE_ADDR_': '$ff', # MAC IEEE Address
+ 'IEEE_ADDR_6' : '$16a', # Transceiver MAC IEEE Address R
+ 'IEEE_ADDR_6_IEEE_ADDR_': '$ff', # MAC IEEE Address
+ 'IEEE_ADDR_7' : '$16b', # Transceiver MAC IEEE Address R
+ 'IEEE_ADDR_7_IEEE_ADDR_': '$ff', # MAC IEEE Address
+ 'XAH_CTRL_0' : '$16c', # Transceiver Extended Operating
+ 'XAH_CTRL_0_MAX_FRAME_RETRIES': '$f0', # Maximum Number of Frame Re-tra
+ 'XAH_CTRL_0_MAX_CSMA_RETRIES': '$e', # Maximum Number of CSMA-CA Proc
+ 'XAH_CTRL_0_SLOTTED_OPERATION': '$1', # Set Slotted Acknowledgment
+ 'CSMA_SEED_0' : '$16d', # Transceiver CSMA-CA Random Num
+ 'CSMA_SEED_0_CSMA_SEED_07': '$80', # Seed Value for CSMA Random Num
+ 'CSMA_SEED_0_CSMA_SEED_06': '$40', # Seed Value for CSMA Random Num
+ 'CSMA_SEED_0_CSMA_SEED_05': '$20', # Seed Value for CSMA Random Num
+ 'CSMA_SEED_0_CSMA_SEED_04': '$10', # Seed Value for CSMA Random Num
+ 'CSMA_SEED_0_CSMA_SEED_03': '$8', # Seed Value for CSMA Random Num
+ 'CSMA_SEED_0_CSMA_SEED_02': '$4', # Seed Value for CSMA Random Num
+ 'CSMA_SEED_0_CSMA_SEED_01': '$2', # Seed Value for CSMA Random Num
+ 'CSMA_SEED_0_CSMA_SEED_00': '$1', # Seed Value for CSMA Random Num
+ 'CSMA_SEED_1' : '$16e', # Transceiver Acknowledgment Fra
+ 'CSMA_SEED_1_AACK_FVN_MODE': '$c0', # Acknowledgment Frame Filter Mo
+ 'CSMA_SEED_1_AACK_SET_PD': '$20', # Set Frame Pending Sub-field
+ 'CSMA_SEED_1_AACK_DIS_ACK': '$10', # Disable Acknowledgment Frame T
+ 'CSMA_SEED_1_AACK_I_AM_COORD': '$8', # Set Personal Area Network Coor
+ 'CSMA_SEED_1_CSMA_SEED_1': '$7', # Seed Value for CSMA Random Num
+ 'CSMA_BE' : '$16f', # Transceiver CSMA-CA Back-off E
+ 'CSMA_BE_MAX_BE': '$f0', # Maximum Back-off Exponent
+ 'CSMA_BE_MIN_BE': '$f', # Minimum Back-off Exponent
+ 'TST_CTRL_DIGI' : '$176', # Transceiver Digital Test Contr
+ 'TST_CTRL_DIGI_TST_CTRL_DIG': '$f', # Digital Test Controller Regist
+ 'TST_RX_LENGTH' : '$17b', # Transceiver Received Frame Len
+ 'TST_RX_LENGTH_RX_LENGTH': '$ff', # Received Frame Length
+ 'TRXFBST' : '$180', # Start of frame buffer
+ 'TRXFBEND' : '$1ff', # End of frame buffer
+
+# Module SYMCNT
+ 'SCTSTRHH' : '$fc', # Symbol Counter Transmit Frame
+ 'SCTSTRHH_SCTSTRHH': '$ff', # Symbol Counter Transmit Frame
+ 'SCTSTRHL' : '$fb', # Symbol Counter Transmit Frame
+ 'SCTSTRHL_SCTSTRHL': '$ff', # Symbol Counter Transmit Frame
+ 'SCTSTRLH' : '$fa', # Symbol Counter Transmit Frame
+ 'SCTSTRLH_SCTSTRLH': '$ff', # Symbol Counter Transmit Frame
+ 'SCTSTRLL' : '$f9', # Symbol Counter Transmit Frame
+ 'SCTSTRLL_SCTSTRLL': '$ff', # Symbol Counter Transmit Frame
+ 'SCOCR1HH' : '$f8', # Symbol Counter Output Compare
+ 'SCOCR1HH_SCOCR1HH': '$ff', # Symbol Counter Output Compare
+ 'SCOCR1HL' : '$f7', # Symbol Counter Output Compare
+ 'SCOCR1HL_SCOCR1HL': '$ff', # Symbol Counter Output Compare
+ 'SCOCR1LH' : '$f6', # Symbol Counter Output Compare
+ 'SCOCR1LH_SCOCR1LH': '$ff', # Symbol Counter Output Compare
+ 'SCOCR1LL' : '$f5', # Symbol Counter Output Compare
+ 'SCOCR1LL_SCOCR1LL': '$ff', # Symbol Counter Output Compare
+ 'SCOCR2HH' : '$f4', # Symbol Counter Output Compare
+ 'SCOCR2HH_SCOCR2HH': '$ff', # Symbol Counter Output Compare
+ 'SCOCR2HL' : '$f3', # Symbol Counter Output Compare
+ 'SCOCR2HL_SCOCR2HL': '$ff', # Symbol Counter Output Compare
+ 'SCOCR2LH' : '$f2', # Symbol Counter Output Compare
+ 'SCOCR2LH_SCOCR2LH': '$ff', # Symbol Counter Output Compare
+ 'SCOCR2LL' : '$f1', # Symbol Counter Output Compare
+ 'SCOCR2LL_SCOCR2LL': '$ff', # Symbol Counter Output Compare
+ 'SCOCR3HH' : '$f0', # Symbol Counter Output Compare
+ 'SCOCR3HH_SCOCR3HH': '$ff', # Symbol Counter Output Compare
+ 'SCOCR3HL' : '$ef', # Symbol Counter Output Compare
+ 'SCOCR3HL_SCOCR3HL': '$ff', # Symbol Counter Output Compare
+ 'SCOCR3LH' : '$ee', # Symbol Counter Output Compare
+ 'SCOCR3LH_SCOCR3LH': '$ff', # Symbol Counter Output Compare
+ 'SCOCR3LL' : '$ed', # Symbol Counter Output Compare
+ 'SCOCR3LL_SCOCR3LL': '$ff', # Symbol Counter Output Compare
+ 'SCTSRHH' : '$ec', # Symbol Counter Frame Timestamp
+ 'SCTSRHH_SCTSRHH': '$ff', # Symbol Counter Frame Timestamp
+ 'SCTSRHL' : '$eb', # Symbol Counter Frame Timestamp
+ 'SCTSRHL_SCTSRHL': '$ff', # Symbol Counter Frame Timestamp
+ 'SCTSRLH' : '$ea', # Symbol Counter Frame Timestamp
+ 'SCTSRLH_SCTSRLH': '$ff', # Symbol Counter Frame Timestamp
+ 'SCTSRLL' : '$e9', # Symbol Counter Frame Timestamp
+ 'SCTSRLL_SCTSRLL': '$ff', # Symbol Counter Frame Timestamp
+ 'SCBTSRHH' : '$e8', # Symbol Counter Beacon Timestam
+ 'SCBTSRHH_SCBTSRHH': '$ff', # Symbol Counter Beacon Timestam
+ 'SCBTSRHL' : '$e7', # Symbol Counter Beacon Timestam
+ 'SCBTSRHL_SCBTSRHL': '$ff', # Symbol Counter Beacon Timestam
+ 'SCBTSRLH' : '$e6', # Symbol Counter Beacon Timestam
+ 'SCBTSRLH_SCBTSRLH': '$ff', # Symbol Counter Beacon Timestam
+ 'SCBTSRLL' : '$e5', # Symbol Counter Beacon Timestam
+ 'SCBTSRLL_SCBTSRLL': '$ff', # Symbol Counter Beacon Timestam
+ 'SCCNTHH' : '$e4', # Symbol Counter Register HH-Byt
+ 'SCCNTHH_SCCNTHH': '$ff', # Symbol Counter Register HH-Byt
+ 'SCCNTHL' : '$e3', # Symbol Counter Register HL-Byt
+ 'SCCNTHL_SCCNTHL': '$ff', # Symbol Counter Register HL-Byt
+ 'SCCNTLH' : '$e2', # Symbol Counter Register LH-Byt
+ 'SCCNTLH_SCCNTLH': '$ff', # Symbol Counter Register LH-Byt
+ 'SCCNTLL' : '$e1', # Symbol Counter Register LL-Byt
+ 'SCCNTLL_SCCNTLL': '$ff', # Symbol Counter Register LL-Byt
+ 'SCIRQS' : '$e0', # Symbol Counter Interrupt Statu
+ 'SCIRQS_Res': '$e0', # Reserved Bit
+ 'SCIRQS_IRQSBO': '$10', # Backoff Slot Counter IRQ
+ 'SCIRQS_IRQSOF': '$8', # Symbol Counter Overflow IRQ
+ 'SCIRQS_IRQSCP': '$7', # Compare Unit 3 Compare Match I
+ 'SCIRQM' : '$df', # Symbol Counter Interrupt Mask
+ 'SCIRQM_Res': '$e0', # Reserved Bit
+ 'SCIRQM_IRQMBO': '$10', # Backoff Slot Counter IRQ enabl
+ 'SCIRQM_IRQMOF': '$8', # Symbol Counter Overflow IRQ en
+ 'SCIRQM_IRQMCP': '$7', # Symbol Counter Compare Match 3
+ 'SCSR' : '$de', # Symbol Counter Status Register
+ 'SCSR_Res': '$fe', # Reserved Bit
+ 'SCSR_SCBSY': '$1', # Symbol Counter busy
+ 'SCCR1' : '$dd', # Symbol Counter Control Registe
+ 'SCCR1_Res': '$c0', # Reserved Bit
+ 'SCCR1_SCBTSM': '$20', # Symbol Counter Beacon Timestam
+ 'SCCR1_SCCKDIV': '$1c', # Clock divider for synchronous
+ 'SCCR1_SCEECLK': '$2', # Enable External Clock Source o
+ 'SCCR1_SCENBO': '$1', # Backoff Slot Counter enable
+ 'SCCR0' : '$dc', # Symbol Counter Control Registe
+ 'SCCR0_SCRES': '$80', # Symbol Counter Synchronization
+ 'SCCR0_SCMBTS': '$40', # Manual Beacon Timestamp
+ 'SCCR0_SCEN': '$20', # Symbol Counter enable
+ 'SCCR0_SCCKSEL': '$10', # Symbol Counter Clock Source se
+ 'SCCR0_SCTSE': '$8', # Symbol Counter Automatic Times
+ 'SCCR0_SCCMP': '$7', # Symbol Counter Compare Unit 3
+ 'SCCSR' : '$db', # Symbol Counter Compare Source
+ 'SCCSR_Res': '$c0', # Reserved Bit
+ 'SCCSR_SCCS3': '$30', # Symbol Counter Compare Source
+ 'SCCSR_SCCS2': '$c', # Symbol Counter Compare Source
+ 'SCCSR_SCCS1': '$3', # Symbol Counter Compare Source
+ 'SCRSTRHH' : '$da', # Symbol Counter Received Frame
+ 'SCRSTRHH_SCRSTRHH': '$ff', # Symbol Counter Received Frame
+ 'SCRSTRHL' : '$d9', # Symbol Counter Received Frame
+ 'SCRSTRHL_SCRSTRHL': '$ff', # Symbol Counter Received Frame
+ 'SCRSTRLH' : '$d8', # Symbol Counter Received Frame
+ 'SCRSTRLH_SCRSTRLH': '$ff', # Symbol Counter Received Frame
+ 'SCRSTRLL' : '$d7', # Symbol Counter Received Frame
+ 'SCRSTRLL_SCRSTRLL': '$ff', # Symbol Counter Received Frame
+
+# Module EEPROM
+ 'EEAR' : '$41', # EEPROM Address Register Bytes
+ 'EEDR' : '$40', # EEPROM Data Register
+ 'EECR' : '$3f', # EEPROM Control Register
+ 'EECR_Res': '$c0', # Reserved
+ 'EECR_EEPM': '$30', # EEPROM Programming Mode
+ 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
+ 'EECR_EEMPE': '$4', # EEPROM Master Write Enable
+ 'EECR_EEPE': '$2', # EEPROM Programming Enable
+ 'EECR_EERE': '$1', # EEPROM Read Enable
+
+# Module JTAG
+ 'OCDR' : '$51', # On-Chip Debug Register
+ 'OCDR_OCDR': '$ff', # On-Chip Debug Register Data
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_JTD': '$80', # JTAG Interface Disable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+
+# Module EXTERNAL_INTERRUPT
+ 'EICRA' : '$69', # External Interrupt Control Reg
+ 'EICRA_ISC3': '$c0', # External Interrupt 3 Sense Con
+ 'EICRA_ISC2': '$30', # External Interrupt 2 Sense Con
+ 'EICRA_ISC1': '$c', # External Interrupt 1 Sense Con
+ 'EICRA_ISC0': '$3', # External Interrupt 0 Sense Con
+ 'EICRB' : '$6a', # External Interrupt Control Reg
+ 'EICRB_ISC7': '$c0', # External Interrupt 7 Sense Con
+ 'EICRB_ISC6': '$30', # External Interrupt 6 Sense Con
+ 'EICRB_ISC5': '$c', # External Interrupt 5 Sense Con
+ 'EICRB_ISC4': '$3', # External Interrupt 4 Sense Con
+ 'EIMSK' : '$3d', # External Interrupt Mask Regist
+ 'EIMSK_INT': '$ff', # External Interrupt Request Ena
+ 'EIFR' : '$3c', # External Interrupt Flag Regist
+ 'EIFR_INTF': '$ff', # External Interrupt Flag
+ 'PCMSK2' : '$6d', # Pin Change Mask Register 2
+ 'PCMSK2_PCINT': '$ff', # Pin Change Enable Mask
+ 'PCMSK1' : '$6c', # Pin Change Mask Register 1
+ 'PCMSK1_PCINT': '$ff', # Pin Change Enable Mask
+ 'PCMSK0' : '$6b', # Pin Change Mask Register 0
+ 'PCIFR' : '$3b', # Pin Change Interrupt Flag Regi
+ 'PCIFR_Res': '$f8', # Reserved Bit
+ 'PCIFR_PCIF': '$7', # Pin Change Interrupt Flags
+ 'PCICR' : '$68', # Pin Change Interrupt Control R
+ 'PCICR_Res': '$f8', # Reserved Bit
+ 'PCICR_PCIE': '$7', # Pin Change Interrupt Enables
+
+# Module AD_CONVERTER
+ 'ADMUX' : '$7c', # The ADC Multiplexer Selection
+ 'ADMUX_REFS': '$c0', # Reference Selection Bits
+ 'ADMUX_ADLAR': '$20', # ADC Left Adjust Result
+ 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
+ 'ADC' : '$78', # ADC Data Register Bytes
+ 'ADCSRA' : '$7a', # The ADC Control and Status Reg
+ 'ADCSRA_ADEN': '$80', # ADC Enable
+ 'ADCSRA_ADSC': '$40', # ADC Start Conversion
+ 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
+ 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
+ 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
+ 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
+ 'ADCSRB' : '$7b', # The ADC Control and Status Reg
+ 'ADCSRB_AVDDOK': '$80', # AVDD Supply Voltage OK
+ 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
+ 'ADCSRB_REFOK': '$20', # Reference Voltage OK
+ 'ADCSRB_ACCH': '$10', # Analog Channel Change
+ 'ADCSRB_MUX5': '$8', # Analog Channel and Gain Select
+ 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Source
+ 'ADCSRC' : '$77', # The ADC Control and Status Reg
+ 'ADCSRC_ADTHT': '$c0', # ADC Track-and-Hold Time
+ 'ADCSRC_Res0': '$20', # Reserved
+ 'ADCSRC_ADSUT': '$1f', # ADC Start-up Time
+ 'DIDR2' : '$7d', # Digital Input Disable Register
+ 'DIDR2_ADC15D': '$80', # Reserved Bits
+ 'DIDR2_ADC14D': '$40', # Reserved Bits
+ 'DIDR2_ADC13D': '$20', # Reserved Bits
+ 'DIDR2_ADC12D': '$10', # Reserved Bits
+ 'DIDR2_ADC11D': '$8', # Reserved Bits
+ 'DIDR2_ADC10D': '$4', # Reserved Bits
+ 'DIDR2_ADC9D': '$2', # Reserved Bits
+ 'DIDR2_ADC8D': '$1', # Reserved Bits
+ 'DIDR0' : '$7e', # Digital Input Disable Register
+ 'DIDR0_ADC7D': '$80', # Disable ADC7:0 Digital Input
+ 'DIDR0_ADC6D': '$40', # Disable ADC7:0 Digital Input
+ 'DIDR0_ADC5D': '$20', # Disable ADC7:0 Digital Input
+ 'DIDR0_ADC4D': '$10', # Disable ADC7:0 Digital Input
+ 'DIDR0_ADC3D': '$8', # Disable ADC7:0 Digital Input
+ 'DIDR0_ADC2D': '$4', # Disable ADC7:0 Digital Input
+ 'DIDR0_ADC1D': '$2', # Disable ADC7:0 Digital Input
+ 'DIDR0_ADC0D': '$1', # Disable ADC7:0 Digital Input
+
+# Module BOOT_LOAD
+ 'SPMCSR' : '$57', # Store Program Memory Control R
+ 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
+ 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
+ 'SPMCSR_SIGRD': '$20', # Signature Row Read
+ 'SPMCSR_RWWSRE': '$10', # Read While Write Section Read
+ 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
+ 'SPMCSR_PGWRT': '$4', # Page Write
+ 'SPMCSR_PGERS': '$2', # Page Erase
+ 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
+
+# Module CPU
+ 'SREG' : '$5f', # Status Register
+ 'SREG_I': '$80', # Global Interrupt Enable
+ 'SREG_T': '$40', # Bit Copy Storage
+ 'SREG_H': '$20', # Half Carry Flag
+ 'SREG_S': '$10', # Sign Bit
+ 'SREG_V': '$8', # Two's Complement Overflow Flag
+ 'SREG_N': '$4', # Negative Flag
+ 'SREG_Z': '$2', # Zero Flag
+ 'SREG_C': '$1', # Carry Flag
+ 'SP' : '$5d', # Stack Pointer
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_JTD': '$80', # JTAG Interface Disable
+ 'MCUCR_Res': '$60', # Reserved
+ 'MCUCR_PUD': '$10', # Pull-up Disable
+ 'MCUCR_Res': '$c', # Reserved
+ 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
+ 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_Res': '$e0', # Reserved
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+ 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
+ 'MCUSR_BORF': '$4', # Brown-out Reset Flag
+ 'MCUSR_EXTRF': '$2', # External Reset Flag
+ 'MCUSR_PORF': '$1', # Power-on Reset Flag
+ 'OSCCAL' : '$66', # Oscillator Calibration Value
+ 'OSCCAL_CAL': '$ff', # Oscillator Calibration Tuning
+ 'CLKPR' : '$61', # Clock Prescale Register
+ 'CLKPR_CLKPCE': '$80', # Clock Prescaler Change Enable
+ 'CLKPR_Res': '$70', # Reserved
+ 'CLKPR_CLKPS': '$f', # Clock Prescaler Select Bits
+ 'SMCR' : '$53', # Sleep Mode Control Register
+ 'SMCR_Res': '$f0', # Reserved
+ 'SMCR_SM': '$e', # Sleep Mode Select bits
+ 'SMCR_SE': '$1', # Sleep Enable
+ 'RAMPZ' : '$5b', # Extended Z-pointer Register fo
+ 'RAMPZ_Res': '$fe', # Reserved
+ 'RAMPZ_RAMPZ0': '$1', # Extended Z-Pointer Value
+ 'GPIOR2' : '$4b', # General Purpose I/O Register 2
+ 'GPIOR2_GPIOR': '$ff', # General Purpose I/O Register 2
+ 'GPIOR1' : '$4a', # General Purpose IO Register 1
+ 'GPIOR1_GPIOR': '$ff', # General Purpose I/O Register 1
+ 'GPIOR0' : '$3e', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR07': '$80', # General Purpose I/O Register 0
+ 'GPIOR0_GPIOR06': '$40', # General Purpose I/O Register 0
+ 'GPIOR0_GPIOR05': '$20', # General Purpose I/O Register 0
+ 'GPIOR0_GPIOR04': '$10', # General Purpose I/O Register 0
+ 'GPIOR0_GPIOR03': '$8', # General Purpose I/O Register 0
+ 'GPIOR0_GPIOR02': '$4', # General Purpose I/O Register 0
+ 'GPIOR0_GPIOR01': '$2', # General Purpose I/O Register 0
+ 'GPIOR0_GPIOR00': '$1', # General Purpose I/O Register 0
+ 'PRR2' : '$63', # Power Reduction Register 2
+ 'PRR2_Res': '$f0', # Reserved Bit
+ 'PRR2_PRRAM': '$f', # Power Reduction SRAMs
+ 'PRR1' : '$65', # Power Reduction Register 1
+ 'PRR1_Res': '$80', # Reserved Bit
+ 'PRR1_PRTRX24': '$40', # Power Reduction Transceiver
+ 'PRR1_PRTIM5': '$20', # Power Reduction Timer/Counter5
+ 'PRR1_PRTIM4': '$10', # Power Reduction Timer/Counter4
+ 'PRR1_PRTIM3': '$8', # Power Reduction Timer/Counter3
+ 'PRR1_PRUSART1': '$1', # Power Reduction USART1
+ 'PRR0' : '$64', # Power Reduction Register0
+ 'PRR0_PRTWI': '$80', # Power Reduction TWI
+ 'PRR0_PRTIM2': '$40', # Power Reduction Timer/Counter2
+ 'PRR0_PRTIM0': '$20', # Power Reduction Timer/Counter0
+ 'PRR0_PRPGA': '$10', # Power Reduction PGA
+ 'PRR0_PRTIM1': '$8', # Power Reduction Timer/Counter1
+ 'PRR0_PRSPI': '$4', # Power Reduction Serial Periphe
+ 'PRR0_PRUSART0': '$2', # Power Reduction USART
+ 'PRR0_PRADC': '$1', # Power Reduction ADC
+
+# Module FLASH
+ 'NEMCR' : '$75', # Flash Extended-Mode Control-Re
+ 'NEMCR_ENEAM': '$40', # Enable Extended Address Mode f
+ 'NEMCR_AEAM': '$30', # Address for Extended Address M
+ 'BGCR' : '$67', # Reference Voltage Calibration
+ 'BGCR_Res': '$80', # Reserved Bit
+ 'BGCR_BGCAL_FINE': '$78', # Fine Calibration Bits
+ 'BGCR_BGCAL': '$7', # Coarse Calibration Bits
+
+# Module PWRCTRL
+ 'TRXPR' : '$139', # Transceiver Pin Register
+ 'TRXPR_Res': '$f0', # Reserved
+ 'TRXPR_SLPTR': '$2', # Multi-purpose Transceiver Cont
+ 'TRXPR_TRXRST': '$1', # Force Transceiver Reset
+ 'DRTRAM0' : '$135', # Data Retention Configuration R
+ 'DRTRAM0_Res': '$c0', # Reserved
+ 'DRTRAM0_DRTSWOK': '$20', # DRT Switch OK
+ 'DRTRAM0_ENDRT': '$10', # Enable SRAM Data Retention
+ 'DRTRAM1' : '$134', # Data Retention Configuration R
+ 'DRTRAM1_Res': '$c0', # Reserved
+ 'DRTRAM1_DRTSWOK': '$20', # DRT Switch OK
+ 'DRTRAM1_ENDRT': '$10', # Enable SRAM Data Retention
+ 'DRTRAM2' : '$133', # Data Retention Configuration R
+ 'DRTRAM2_Res': '$40', # Reserved Bit
+ 'DRTRAM2_DRTSWOK': '$20', # DRT Switch OK
+ 'DRTRAM2_ENDRT': '$10', # Enable SRAM Data Retention
+ 'DRTRAM3' : '$132', # Data Retention Configuration R
+ 'DRTRAM3_Res': '$c0', # Reserved
+ 'DRTRAM3_DRTSWOK': '$20', # DRT Switch OK
+ 'DRTRAM3_ENDRT': '$10', # Enable SRAM Data Retention
+ 'LLDRL' : '$130', # Low Leakage Voltage Regulator
+ 'LLDRL_Res': '$f0', # Reserved
+ 'LLDRL_LLDRL': '$f', # Low-Byte Data Register Bits
+ 'LLDRH' : '$131', # Low Leakage Voltage Regulator
+ 'LLDRH_Res': '$e0', # Reserved
+ 'LLDRH_LLDRH': '$1f', # High-Byte Data Register Bits
+ 'LLCR' : '$12f', # Low Leakage Voltage Regulator
+ 'LLCR_Res': '$c0', # Reserved Bit
+ 'LLCR_LLDONE': '$20', # Calibration Done
+ 'LLCR_LLCOMP': '$10', # Comparator Output
+ 'LLCR_LLCAL': '$8', # Calibration Active
+ 'LLCR_LLTCO': '$4', # Temperature Coefficient of Cur
+ 'LLCR_LLSHORT': '$2', # Short Lower Calibration Circui
+ 'LLCR_LLENCAL': '$1', # Enable Automatic Calibration
+ 'DPDS0' : '$136', # Port Driver Strength Register
+ 'DPDS0_PFDRV': '$c0', # Driver Strength Port F
+ 'DPDS0_PEDRV': '$30', # Driver Strength Port E
+ 'DPDS0_PDDRV': '$c', # Driver Strength Port D
+ 'DPDS0_PBDRV': '$3', # Driver Strength Port B
+ 'DPDS1' : '$137', # Port Driver Strength Register
+ 'DPDS1_Res': '$fc', # Reserved
+ 'DPDS1_PGDRV': '$3', # Driver Strength Port G
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_PUD': '$10', # Pull-up Disable
+
+# Module USART0_SPI
+ 'UCSR0A' : '$c0', # USART0 MSPIM Control and Statu
+ 'UCSR0A_RXC0': '$80', # USART Receive Complete
+ 'UCSR0A_TXC0': '$40', # USART Transmit Complete
+ 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
+ 'UCSR0B' : '$c1', # USART0 MSPIM Control and Statu
+ 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
+ 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
+ 'UCSR0B_UDRIE0': '$20', # USART Data Register Empty Inte
+ 'UCSR0B_RXEN0': '$10', # Receiver Enable
+ 'UCSR0B_TXEN0': '$8', # Transmitter Enable
+ 'UCSR0C' : '$c2', # USART0 MSPIM Control and Statu
+ 'UCSR0C_UDORD0': '$4', # Data Order
+ 'UCSR0C_UCPHA0': '$2', # Clock Phase
+ 'UCSR0C_UCPOL0': '$1', # Clock Polarity
+
+# Module USART1_SPI
+ 'UCSR1A' : '$c8', # USART1 MSPIM Control and Statu
+ 'UCSR1A_RXC1': '$80', # USART Receive Complete
+ 'UCSR1A_TXC1': '$40', # USART Transmit Complete
+ 'UCSR1A_UDRE1': '$20', # USART Data Register Empty
+ 'UCSR1B' : '$c9', # USART1 MSPIM Control and Statu
+ 'UCSR1B_RXCIE1': '$80', # RX Complete Interrupt Enable
+ 'UCSR1B_TXCIE1': '$40', # TX Complete Interrupt Enable
+ 'UCSR1B_UDRIE1': '$20', # USART Data Register Empty Inte
+ 'UCSR1B_RXEN1': '$10', # Receiver Enable
+ 'UCSR1B_TXEN1': '$8', # Transmitter Enable
+ 'UCSR1C' : '$ca', # USART1 MSPIM Control and Statu
+ 'UCSR1C_UDORD1': '$4', # Data Order
+ 'UCSR1C_UCPHA1': '$2', # Clock Phase
+ 'UCSR1C_UCPOL1': '$1', # Clock Polarity
+
+ '__amforth_dummy':'0'
+}
diff --git a/amforth-6.5/avr8/devices/atmega128a/atmega128a.frt b/amforth-6.5/avr8/devices/atmega128a/atmega128a.frt
new file mode 100644
index 0000000..83b4185
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega128a/atmega128a.frt
@@ -0,0 +1,329 @@
+\ Partname: ATmega128A
+\ generated automatically
+
+\ ANALOG_COMPARATOR
+&64 constant SFIOR \ Special Function IO Register
+ $08 constant SFIOR_ACME \ Analog Comparator Multiplexer Enable
+&40 constant ACSR \ Analog Comparator Control And Status Register
+ $80 constant ACSR_ACD \ Analog Comparator Disable
+ $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
+ $20 constant ACSR_ACO \ Analog Compare Output
+ $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
+ $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
+ $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
+ $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
+\ SPI
+&47 constant SPDR \ SPI Data Register
+&46 constant SPSR \ SPI Status Register
+ $80 constant SPSR_SPIF \ SPI Interrupt Flag
+ $40 constant SPSR_WCOL \ Write Collision Flag
+ $01 constant SPSR_SPI2X \ Double SPI Speed Bit
+&45 constant SPCR \ SPI Control Register
+ $80 constant SPCR_SPIE \ SPI Interrupt Enable
+ $40 constant SPCR_SPE \ SPI Enable
+ $20 constant SPCR_DORD \ Data Order
+ $10 constant SPCR_MSTR \ Master/Slave Select
+ $08 constant SPCR_CPOL \ Clock polarity
+ $04 constant SPCR_CPHA \ Clock Phase
+ $03 constant SPCR_SPR \ SPI Clock Rate Selects
+\ TWI
+&112 constant TWBR \ TWI Bit Rate register
+&116 constant TWCR \ TWI Control Register
+ $80 constant TWCR_TWINT \ TWI Interrupt Flag
+ $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
+ $20 constant TWCR_TWSTA \ TWI Start Condition Bit
+ $10 constant TWCR_TWSTO \ TWI Stop Condition Bit
+ $08 constant TWCR_TWWC \ TWI Write Collition Flag
+ $04 constant TWCR_TWEN \ TWI Enable Bit
+ $01 constant TWCR_TWIE \ TWI Interrupt Enable
+&113 constant TWSR \ TWI Status Register
+ $F8 constant TWSR_TWS \ TWI Status
+ $03 constant TWSR_TWPS \ TWI Prescaler
+&115 constant TWDR \ TWI Data register
+&114 constant TWAR \ TWI (Slave) Address register
+ $FE constant TWAR_TWA \ TWI (Slave) Address register Bits
+ $01 constant TWAR_TWGCE \ TWI General Call Recognition Enable Bit
+\ USART0
+&44 constant UDR0 \ USART I/O Data Register
+&43 constant UCSR0A \ USART Control and Status Register A
+ $80 constant UCSR0A_RXC0 \ USART Receive Complete
+ $40 constant UCSR0A_TXC0 \ USART Transmitt Complete
+ $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
+ $10 constant UCSR0A_FE0 \ Framing Error
+ $08 constant UCSR0A_DOR0 \ Data overRun
+ $04 constant UCSR0A_UPE0 \ Parity Error
+ $02 constant UCSR0A_U2X0 \ Double the USART transmission speed
+ $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
+&42 constant UCSR0B \ USART Control and Status Register B
+ $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
+ $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
+ $20 constant UCSR0B_UDRIE0 \ USART Data register Empty Interrupt Enable
+ $10 constant UCSR0B_RXEN0 \ Receiver Enable
+ $08 constant UCSR0B_TXEN0 \ Transmitter Enable
+ $04 constant UCSR0B_UCSZ02 \ Character Size
+ $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
+ $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
+&149 constant UCSR0C \ USART Control and Status Register C
+ $40 constant UCSR0C_UMSEL0 \ USART Mode Select
+ $30 constant UCSR0C_UPM0 \ Parity Mode Bits
+ $08 constant UCSR0C_USBS0 \ Stop Bit Select
+ $06 constant UCSR0C_UCSZ0 \ Character Size
+ $01 constant UCSR0C_UCPOL0 \ Clock Polarity
+&144 constant UBRR0H \ USART Baud Rate Register Hight Byte
+&41 constant UBRR0L \ USART Baud Rate Register Low Byte
+\ USART1
+&156 constant UDR1 \ USART I/O Data Register
+&155 constant UCSR1A \ USART Control and Status Register A
+ $80 constant UCSR1A_RXC1 \ USART Receive Complete
+ $40 constant UCSR1A_TXC1 \ USART Transmitt Complete
+ $20 constant UCSR1A_UDRE1 \ USART Data Register Empty
+ $10 constant UCSR1A_FE1 \ Framing Error
+ $08 constant UCSR1A_DOR1 \ Data overRun
+ $04 constant UCSR1A_UPE1 \ Parity Error
+ $02 constant UCSR1A_U2X1 \ Double the USART transmission speed
+ $01 constant UCSR1A_MPCM1 \ Multi-processor Communication Mode
+&154 constant UCSR1B \ USART Control and Status Register B
+ $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable
+ $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable
+ $20 constant UCSR1B_UDRIE1 \ USART Data register Empty Interrupt Enable
+ $10 constant UCSR1B_RXEN1 \ Receiver Enable
+ $08 constant UCSR1B_TXEN1 \ Transmitter Enable
+ $04 constant UCSR1B_UCSZ12 \ Character Size
+ $02 constant UCSR1B_RXB81 \ Receive Data Bit 8
+ $01 constant UCSR1B_TXB81 \ Transmit Data Bit 8
+&157 constant UCSR1C \ USART Control and Status Register C
+ $40 constant UCSR1C_UMSEL1 \ USART Mode Select
+ $30 constant UCSR1C_UPM1 \ Parity Mode Bits
+ $08 constant UCSR1C_USBS1 \ Stop Bit Select
+ $06 constant UCSR1C_UCSZ1 \ Character Size
+ $01 constant UCSR1C_UCPOL1 \ Clock Polarity
+&152 constant UBRR1H \ USART Baud Rate Register Hight Byte
+&153 constant UBRR1L \ USART Baud Rate Register Low Byte
+\ CPU
+&95 constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ $08 constant SREG_V \ Two's Complement Overflow Flag
+ $04 constant SREG_N \ Negative Flag
+ $02 constant SREG_Z \ Zero Flag
+ $01 constant SREG_C \ Carry Flag
+&93 constant SP \ Stack Pointer
+&85 constant MCUCR \ MCU Control Register
+ $80 constant MCUCR_SRE \ External SRAM Enable
+ $40 constant MCUCR_SRW10 \ External SRAM Wait State Select
+ $20 constant MCUCR_SE \ Sleep Enable
+ $18 constant MCUCR_SM \ Sleep Mode Select
+ $04 constant MCUCR_SM2 \ Sleep Mode Select
+ $02 constant MCUCR_IVSEL \ Interrupt Vector Select
+ $01 constant MCUCR_IVCE \ Interrupt Vector Change Enable
+&84 constant MCUCSR \ MCU Control And Status Register
+ $80 constant MCUCSR_JTD \ JTAG Interface Disable
+ $10 constant MCUCSR_JTRF \ JTAG Reset Flag
+ $08 constant MCUCSR_WDRF \ Watchdog Reset Flag
+ $04 constant MCUCSR_BORF \ Brown-out Reset Flag
+ $02 constant MCUCSR_EXTRF \ External Reset Flag
+ $01 constant MCUCSR_PORF \ Power-on reset flag
+&109 constant XMCRA \ External Memory Control Register A
+ $70 constant XMCRA_SRL \ Wait state page limit
+ $0C constant XMCRA_SRW0 \ Wait state select bit lower page
+ $02 constant XMCRA_SRW11 \ Wait state select bit upper page
+&108 constant XMCRB \ External Memory Control Register B
+ $80 constant XMCRB_XMBK \ External Memory Bus Keeper Enable
+ $07 constant XMCRB_XMM \ External Memory High Mask
+&111 constant OSCCAL \ Oscillator Calibration Value
+&92 constant XDIV \ XTAL Divide Control Register
+&91 constant RAMPZ \ RAM Page Z Select Register
+ $01 constant RAMPZ_RAMPZ0 \ RAM Page Z Select Register Bit 0
+\ BOOT_LOAD
+&104 constant SPMCSR \ Store Program Memory Control Register
+ $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
+ $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
+ $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
+ $04 constant SPMCSR_PGWRT \ Page Write
+ $02 constant SPMCSR_PGERS \ Page Erase
+ $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
+\ JTAG
+&66 constant OCDR \ On-Chip Debug Related Register in I/O Memory
+ $FF constant OCDR_OCDR \ On-Chip Debug Register Bits
+\ MISC
+\ EXTERNAL_INTERRUPT
+&106 constant EICRA \ External Interrupt Control Register A
+ $C0 constant EICRA_ISC3 \ External Interrupt Sense Control Bit
+ $30 constant EICRA_ISC2 \ External Interrupt Sense Control Bit
+ $0C constant EICRA_ISC1 \ External Interrupt Sense Control Bit
+ $03 constant EICRA_ISC0 \ External Interrupt Sense Control Bit
+&90 constant EICRB \ External Interrupt Control Register B
+ $C0 constant EICRB_ISC7 \ External Interrupt 7-4 Sense Control Bit
+ $30 constant EICRB_ISC6 \ External Interrupt 7-4 Sense Control Bit
+ $0C constant EICRB_ISC5 \ External Interrupt 7-4 Sense Control Bit
+ $03 constant EICRB_ISC4 \ External Interrupt 7-4 Sense Control Bit
+&89 constant EIMSK \ External Interrupt Mask Register
+ $FF constant EIMSK_INT \ External Interrupt Request 7 Enable
+&88 constant EIFR \ External Interrupt Flag Register
+ $FF constant EIFR_INTF \ External Interrupt Flags
+\ EEPROM
+&62 constant EEAR \ EEPROM Read/Write Access Bytes
+&61 constant EEDR \ EEPROM Data Register
+&60 constant EECR \ EEPROM Control Register
+ $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
+ $04 constant EECR_EEMWE \ EEPROM Master Write Enable
+ $02 constant EECR_EEWE \ EEPROM Write Enable
+ $01 constant EECR_EERE \ EEPROM Read Enable
+\ PORTA
+&59 constant PORTA \ Port A Data Register
+&58 constant DDRA \ Port A Data Direction Register
+&57 constant PINA \ Port A Input Pins
+\ PORTB
+&56 constant PORTB \ Port B Data Register
+&55 constant DDRB \ Port B Data Direction Register
+&54 constant PINB \ Port B Input Pins
+\ PORTC
+&53 constant PORTC \ Port C Data Register
+&52 constant DDRC \ Port C Data Direction Register
+&51 constant PINC \ Port C Input Pins
+\ PORTD
+&50 constant PORTD \ Port D Data Register
+&49 constant DDRD \ Port D Data Direction Register
+&48 constant PIND \ Port D Input Pins
+\ PORTE
+&35 constant PORTE \ Data Register, Port E
+&34 constant DDRE \ Data Direction Register, Port E
+&33 constant PINE \ Input Pins, Port E
+\ PORTF
+&98 constant PORTF \ Data Register, Port F
+&97 constant DDRF \ Data Direction Register, Port F
+&32 constant PINF \ Input Pins, Port F
+\ PORTG
+&101 constant PORTG \ Data Register, Port G
+&100 constant DDRG \ Data Direction Register, Port G
+&99 constant PING \ Input Pins, Port G
+\ TIMER_COUNTER_0
+&83 constant TCCR0 \ Timer/Counter Control Register
+ $80 constant TCCR0_FOC0 \ Force Output Compare
+ $40 constant TCCR0_WGM00 \ Waveform Generation Mode 0
+ $30 constant TCCR0_COM0 \ Compare Match Output Modes
+ $08 constant TCCR0_WGM01 \ Waveform Generation Mode 1
+ $07 constant TCCR0_CS0 \ Clock Selects
+&82 constant TCNT0 \ Timer/Counter Register
+&81 constant OCR0 \ Output Compare Register
+&80 constant ASSR \ Asynchronus Status Register
+ $08 constant ASSR_AS0 \ Asynchronus Timer/Counter 0
+ $04 constant ASSR_TCN0UB \ Timer/Counter0 Update Busy
+ $02 constant ASSR_OCR0UB \ Output Compare register 0 Busy
+ $01 constant ASSR_TCR0UB \ Timer/Counter Control Register 0 Update Busy
+&87 constant TIMSK \ Timer/Counter Interrupt Mask Register
+ $02 constant TIMSK_OCIE0 \ Timer/Counter0 Output Compare Match Interrupt register
+ $01 constant TIMSK_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
+&86 constant TIFR \ Timer/Counter Interrupt Flag register
+ $02 constant TIFR_OCF0 \ Output Compare Flag 0
+ $01 constant TIFR_TOV0 \ Timer/Counter0 Overflow Flag
+\ TIMER_COUNTER_1
+&125 constant ETIMSK \ Extended Timer/Counter Interrupt Mask Register
+ $01 constant ETIMSK_OCIE1C \ Timer/Counter 1, Output Compare Match C Interrupt Enable
+&124 constant ETIFR \ Extended Timer/Counter Interrupt Flag register
+ $01 constant ETIFR_OCF1C \ Timer/Counter 1, Output Compare C Match Flag
+&79 constant TCCR1A \ Timer/Counter1 Control Register A
+ $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
+ $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
+ $0C constant TCCR1A_COM1C \ Compare Output Mode 1C, bits
+ $03 constant TCCR1A_WGM1 \ Waveform Generation Mode Bits
+&78 constant TCCR1B \ Timer/Counter1 Control Register B
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
+ $07 constant TCCR1B_CS1 \ Clock Select1 bits
+&122 constant TCCR1C \ Timer/Counter1 Control Register C
+ $80 constant TCCR1C_FOC1A \ Force Output Compare for channel A
+ $40 constant TCCR1C_FOC1B \ Force Output Compare for channel B
+ $20 constant TCCR1C_FOC1C \ Force Output Compare for channel C
+&76 constant TCNT1 \ Timer/Counter1 Bytes
+&74 constant OCR1A \ Timer/Counter1 Output Compare Register Bytes
+&72 constant OCR1B \ Timer/Counter1 Output Compare Register Bytes
+&120 constant OCR1C \ Timer/Counter1 Output Compare Register Bytes
+&70 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
+\ TIMER_COUNTER_2
+&69 constant TCCR2 \ Timer/Counter Control Register
+ $80 constant TCCR2_FOC2 \ Force Output Compare
+ $40 constant TCCR2_WGM20 \ Wafeform Generation Mode
+ $30 constant TCCR2_COM2 \ Compare Match Output Mode
+ $08 constant TCCR2_WGM21 \ Waveform Generation Mode
+ $07 constant TCCR2_CS2 \ Clock Select
+&68 constant TCNT2 \ Timer/Counter Register
+&67 constant OCR2 \ Output Compare Register
+\ TIMER_COUNTER_3
+&139 constant TCCR3A \ Timer/Counter3 Control Register A
+ $C0 constant TCCR3A_COM3A \ Compare Output Mode 3A, bits
+ $30 constant TCCR3A_COM3B \ Compare Output Mode 3B, bits
+ $0C constant TCCR3A_COM3C \ Compare Output Mode 3C, bits
+ $03 constant TCCR3A_WGM3 \ Waveform Generation Mode Bits
+&138 constant TCCR3B \ Timer/Counter3 Control Register B
+ $80 constant TCCR3B_ICNC3 \ Input Capture 3 Noise Canceler
+ $40 constant TCCR3B_ICES3 \ Input Capture 3 Edge Select
+ $18 constant TCCR3B_WGM3 \ Waveform Generation Mode
+ $07 constant TCCR3B_CS3 \ Clock Select3 bits
+&140 constant TCCR3C \ Timer/Counter3 Control Register C
+ $80 constant TCCR3C_FOC3A \ Force Output Compare for channel A
+ $40 constant TCCR3C_FOC3B \ Force Output Compare for channel B
+ $20 constant TCCR3C_FOC3C \ Force Output Compare for channel C
+&136 constant TCNT3 \ Timer/Counter3 Bytes
+&134 constant OCR3A \ Timer/Counter3 Output Compare Register A Bytes
+&132 constant OCR3B \ Timer/Counter3 Output Compare Register B Bytes
+&130 constant OCR3C \ Timer/Counter3 Output compare Register C Bytes
+&128 constant ICR3 \ Timer/Counter3 Input Capture Register Bytes
+\ WATCHDOG
+&65 constant WDTCR \ Watchdog Timer Control Register
+ $10 constant WDTCR_WDCE \ Watchdog Change Enable
+ $08 constant WDTCR_WDE \ Watch Dog Enable
+ $07 constant WDTCR_WDP \ Watch Dog Timer Prescaler bits
+\ AD_CONVERTER
+&39 constant ADMUX \ The ADC multiplexer Selection Register
+ $C0 constant ADMUX_REFS \ Reference Selection Bits
+ $20 constant ADMUX_ADLAR \ Left Adjust Result
+ $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
+&38 constant ADCSRA \ The ADC Control and Status register
+ $80 constant ADCSRA_ADEN \ ADC Enable
+ $40 constant ADCSRA_ADSC \ ADC Start Conversion
+ $20 constant ADCSRA_ADFR \ ADC Free Running Select
+ $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
+ $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
+ $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
+&36 constant ADC \ ADC Data Register Bytes
+
+\ Interrupts
+&2 constant INT0Addr \ External Interrupt Request 0
+&4 constant INT1Addr \ External Interrupt Request 1
+&6 constant INT2Addr \ External Interrupt Request 2
+&8 constant INT3Addr \ External Interrupt Request 3
+&10 constant INT4Addr \ External Interrupt Request 4
+&12 constant INT5Addr \ External Interrupt Request 5
+&14 constant INT6Addr \ External Interrupt Request 6
+&16 constant INT7Addr \ External Interrupt Request 7
+&18 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
+&20 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
+&22 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+&24 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
+&26 constant TIMER1_COMPBAddr \ Timer/Counter Compare Match B
+&28 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+&30 constant TIMER0_COMPAddr \ Timer/Counter0 Compare Match
+&32 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
+&34 constant SPI__STCAddr \ SPI Serial Transfer Complete
+&36 constant USART0__RXAddr \ USART0, Rx Complete
+&38 constant USART0__UDREAddr \ USART0 Data Register Empty
+&40 constant USART0__TXAddr \ USART0, Tx Complete
+&42 constant ADCAddr \ ADC Conversion Complete
+&44 constant EE_READYAddr \ EEPROM Ready
+&46 constant ANALOG_COMPAddr \ Analog Comparator
+&48 constant TIMER1_COMPCAddr \ Timer/Counter1 Compare Match C
+&50 constant TIMER3_CAPTAddr \ Timer/Counter3 Capture Event
+&52 constant TIMER3_COMPAAddr \ Timer/Counter3 Compare Match A
+&54 constant TIMER3_COMPBAddr \ Timer/Counter3 Compare Match B
+&56 constant TIMER3_COMPCAddr \ Timer/Counter3 Compare Match C
+&58 constant TIMER3_OVFAddr \ Timer/Counter3 Overflow
+&60 constant USART1__RXAddr \ USART1, Rx Complete
+&62 constant USART1__UDREAddr \ USART1, Data Register Empty
+&64 constant USART1__TXAddr \ USART1, Tx Complete
+&66 constant TWIAddr \ 2-wire Serial Interface
+&68 constant SPM_READYAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/atmega128a/device.asm b/amforth-6.5/avr8/devices/atmega128a/device.asm
new file mode 100644
index 0000000..a0f8692
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega128a/device.asm
@@ -0,0 +1,141 @@
+; Partname: ATmega128A
+; generated automatically, do not edit
+
+.nolist
+ .include "m128Adef.inc"
+.list
+
+.equ ramstart = 256
+.equ CELLSIZE = 2
+.macro readflashcell
+ clr temp7
+ lsl zl
+ rol zh
+ rol temp7
+ out_ RAMPZ, temp7
+ elpm @0, Z+
+ elpm @1, Z+
+.endmacro
+.macro writeflashcell
+ clr temp7
+ lsl zl
+ rol zh
+ rol temp7
+ out_ RAMPZ, temp7
+.endmacro
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_SPI = 0
+.set WANT_TWI = 0
+.set WANT_USART0 = 0
+.set WANT_USART1 = 0
+.set WANT_CPU = 0
+.set WANT_BOOT_LOAD = 0
+.set WANT_JTAG = 0
+.set WANT_MISC = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_EEPROM = 0
+.set WANT_PORTA = 0
+.set WANT_PORTB = 0
+.set WANT_PORTC = 0
+.set WANT_PORTD = 0
+.set WANT_PORTE = 0
+.set WANT_PORTF = 0
+.set WANT_PORTG = 0
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_TIMER_COUNTER_2 = 0
+.set WANT_TIMER_COUNTER_3 = 0
+.set WANT_WATCHDOG = 0
+.set WANT_AD_CONVERTER = 0
+.equ intvecsize = 2 ; please verify; flash size: 131072 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.org 2
+ rcall isr ; External Interrupt Request 0
+.org 4
+ rcall isr ; External Interrupt Request 1
+.org 6
+ rcall isr ; External Interrupt Request 2
+.org 8
+ rcall isr ; External Interrupt Request 3
+.org 10
+ rcall isr ; External Interrupt Request 4
+.org 12
+ rcall isr ; External Interrupt Request 5
+.org 14
+ rcall isr ; External Interrupt Request 6
+.org 16
+ rcall isr ; External Interrupt Request 7
+.org 18
+ rcall isr ; Timer/Counter2 Compare Match
+.org 20
+ rcall isr ; Timer/Counter2 Overflow
+.org 22
+ rcall isr ; Timer/Counter1 Capture Event
+.org 24
+ rcall isr ; Timer/Counter1 Compare Match A
+.org 26
+ rcall isr ; Timer/Counter Compare Match B
+.org 28
+ rcall isr ; Timer/Counter1 Overflow
+.org 30
+ rcall isr ; Timer/Counter0 Compare Match
+.org 32
+ rcall isr ; Timer/Counter0 Overflow
+.org 34
+ rcall isr ; SPI Serial Transfer Complete
+.org 36
+ rcall isr ; USART0, Rx Complete
+.org 38
+ rcall isr ; USART0 Data Register Empty
+.org 40
+ rcall isr ; USART0, Tx Complete
+.org 42
+ rcall isr ; ADC Conversion Complete
+.org 44
+ rcall isr ; EEPROM Ready
+.org 46
+ rcall isr ; Analog Comparator
+.org 48
+ rcall isr ; Timer/Counter1 Compare Match C
+.org 50
+ rcall isr ; Timer/Counter3 Capture Event
+.org 52
+ rcall isr ; Timer/Counter3 Compare Match A
+.org 54
+ rcall isr ; Timer/Counter3 Compare Match B
+.org 56
+ rcall isr ; Timer/Counter3 Compare Match C
+.org 58
+ rcall isr ; Timer/Counter3 Overflow
+.org 60
+ rcall isr ; USART1, Rx Complete
+.org 62
+ rcall isr ; USART1, Data Register Empty
+.org 64
+ rcall isr ; USART1, Tx Complete
+.org 66
+ rcall isr ; 2-wire Serial Interface
+.org 68
+ rcall isr ; Store Program Memory Read
+.equ INTVECTORS = 35
+.nooverlap
+
+; compatability layer (maybe empty)
+.equ EEPE = EEWE
+.equ EEMPE = EEMWE
+
+; controller data area, environment query mcu-info
+mcu_info:
+mcu_ramsize:
+ .dw 4096
+mcu_eepromsize:
+ .dw 4096
+mcu_maxdp:
+ .dw 65535
+mcu_numints:
+ .dw 35
+mcu_name:
+ .dw 10
+ .db "ATmega128A"
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega128a/device.inc b/amforth-6.5/avr8/devices/atmega128a/device.inc
new file mode 100644
index 0000000..3252433
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega128a/device.inc
@@ -0,0 +1,1179 @@
+; Partname: ATmega128A
+; generated automatically, no not edit
+
+.if WANT_ANALOG_COMPARATOR == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Special Function IO Register
+VE_SFIOR:
+ .dw $ff05
+ .db "SFIOR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SFIOR
+XT_SFIOR:
+ .dw PFA_DOVARIABLE
+PFA_SFIOR:
+ .dw 64
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Control And Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw 40
+
+.endif
+.if WANT_SPI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR:
+ .dw $ff04
+ .db "SPDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR
+XT_SPDR:
+ .dw PFA_DOVARIABLE
+PFA_SPDR:
+ .dw 47
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR:
+ .dw $ff04
+ .db "SPSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR
+XT_SPSR:
+ .dw PFA_DOVARIABLE
+PFA_SPSR:
+ .dw 46
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR:
+ .dw $ff04
+ .db "SPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR
+XT_SPCR:
+ .dw PFA_DOVARIABLE
+PFA_SPCR:
+ .dw 45
+
+.endif
+.if WANT_TWI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Bit Rate register
+VE_TWBR:
+ .dw $ff04
+ .db "TWBR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWBR
+XT_TWBR:
+ .dw PFA_DOVARIABLE
+PFA_TWBR:
+ .dw 112
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Control Register
+VE_TWCR:
+ .dw $ff04
+ .db "TWCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWCR
+XT_TWCR:
+ .dw PFA_DOVARIABLE
+PFA_TWCR:
+ .dw 116
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Status Register
+VE_TWSR:
+ .dw $ff04
+ .db "TWSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWSR
+XT_TWSR:
+ .dw PFA_DOVARIABLE
+PFA_TWSR:
+ .dw 113
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Data register
+VE_TWDR:
+ .dw $ff04
+ .db "TWDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWDR
+XT_TWDR:
+ .dw PFA_DOVARIABLE
+PFA_TWDR:
+ .dw 115
+; ( -- addr ) System Constant
+; R( -- )
+; TWI (Slave) Address register
+VE_TWAR:
+ .dw $ff04
+ .db "TWAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWAR
+XT_TWAR:
+ .dw PFA_DOVARIABLE
+PFA_TWAR:
+ .dw 114
+
+.endif
+.if WANT_USART0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR0:
+ .dw $ff04
+ .db "UDR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR0
+XT_UDR0:
+ .dw PFA_DOVARIABLE
+PFA_UDR0:
+ .dw 44
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR0A:
+ .dw $ff06
+ .db "UCSR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0A
+XT_UCSR0A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0A:
+ .dw 43
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR0B:
+ .dw $ff06
+ .db "UCSR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0B
+XT_UCSR0B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0B:
+ .dw 42
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR0C:
+ .dw $ff06
+ .db "UCSR0C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0C
+XT_UCSR0C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0C:
+ .dw 149
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Hight Byte
+VE_UBRR0H:
+ .dw $ff06
+ .db "UBRR0H"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR0H
+XT_UBRR0H:
+ .dw PFA_DOVARIABLE
+PFA_UBRR0H:
+ .dw 144
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Low Byte
+VE_UBRR0L:
+ .dw $ff06
+ .db "UBRR0L"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR0L
+XT_UBRR0L:
+ .dw PFA_DOVARIABLE
+PFA_UBRR0L:
+ .dw 41
+
+.endif
+.if WANT_USART1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR1:
+ .dw $ff04
+ .db "UDR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR1
+XT_UDR1:
+ .dw PFA_DOVARIABLE
+PFA_UDR1:
+ .dw 156
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR1A:
+ .dw $ff06
+ .db "UCSR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1A
+XT_UCSR1A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1A:
+ .dw 155
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR1B:
+ .dw $ff06
+ .db "UCSR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1B
+XT_UCSR1B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1B:
+ .dw 154
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR1C:
+ .dw $ff06
+ .db "UCSR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1C
+XT_UCSR1C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1C:
+ .dw 157
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Hight Byte
+VE_UBRR1H:
+ .dw $ff06
+ .db "UBRR1H"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR1H
+XT_UBRR1H:
+ .dw PFA_DOVARIABLE
+PFA_UBRR1H:
+ .dw 152
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Low Byte
+VE_UBRR1L:
+ .dw $ff06
+ .db "UBRR1L"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR1L
+XT_UBRR1L:
+ .dw PFA_DOVARIABLE
+PFA_UBRR1L:
+ .dw 153
+
+.endif
+.if WANT_CPU == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw 95
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer
+VE_SP:
+ .dw $ff02
+ .db "SP"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SP
+XT_SP:
+ .dw PFA_DOVARIABLE
+PFA_SP:
+ .dw 93
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw 85
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control And Status Register
+VE_MCUCSR:
+ .dw $ff06
+ .db "MCUCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCSR
+XT_MCUCSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCSR:
+ .dw 84
+; ( -- addr ) System Constant
+; R( -- )
+; External Memory Control Register A
+VE_XMCRA:
+ .dw $ff05
+ .db "XMCRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_XMCRA
+XT_XMCRA:
+ .dw PFA_DOVARIABLE
+PFA_XMCRA:
+ .dw 109
+; ( -- addr ) System Constant
+; R( -- )
+; External Memory Control Register B
+VE_XMCRB:
+ .dw $ff05
+ .db "XMCRB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_XMCRB
+XT_XMCRB:
+ .dw PFA_DOVARIABLE
+PFA_XMCRB:
+ .dw 108
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Calibration Value
+VE_OSCCAL:
+ .dw $ff06
+ .db "OSCCAL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSCCAL
+XT_OSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_OSCCAL:
+ .dw 111
+; ( -- addr ) System Constant
+; R( -- )
+; XTAL Divide Control Register
+VE_XDIV:
+ .dw $ff04
+ .db "XDIV"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_XDIV
+XT_XDIV:
+ .dw PFA_DOVARIABLE
+PFA_XDIV:
+ .dw 92
+; ( -- addr ) System Constant
+; R( -- )
+; RAM Page Z Select Register
+VE_RAMPZ:
+ .dw $ff05
+ .db "RAMPZ",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_RAMPZ
+XT_RAMPZ:
+ .dw PFA_DOVARIABLE
+PFA_RAMPZ:
+ .dw 91
+
+.endif
+.if WANT_BOOT_LOAD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control Register
+VE_SPMCSR:
+ .dw $ff06
+ .db "SPMCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCSR
+XT_SPMCSR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCSR:
+ .dw 104
+
+.endif
+.if WANT_JTAG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; On-Chip Debug Related Register in I/O Memory
+VE_OCDR:
+ .dw $ff04
+ .db "OCDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCDR
+XT_OCDR:
+ .dw PFA_DOVARIABLE
+PFA_OCDR:
+ .dw 66
+
+.endif
+.if WANT_MISC == 1
+
+.endif
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register A
+VE_EICRA:
+ .dw $ff05
+ .db "EICRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRA
+XT_EICRA:
+ .dw PFA_DOVARIABLE
+PFA_EICRA:
+ .dw 106
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register B
+VE_EICRB:
+ .dw $ff05
+ .db "EICRB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRB
+XT_EICRB:
+ .dw PFA_DOVARIABLE
+PFA_EICRB:
+ .dw 90
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Mask Register
+VE_EIMSK:
+ .dw $ff05
+ .db "EIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIMSK
+XT_EIMSK:
+ .dw PFA_DOVARIABLE
+PFA_EIMSK:
+ .dw 89
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Flag Register
+VE_EIFR:
+ .dw $ff04
+ .db "EIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIFR
+XT_EIFR:
+ .dw PFA_DOVARIABLE
+PFA_EIFR:
+ .dw 88
+
+.endif
+.if WANT_EEPROM == 1
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Read/Write Access Bytes
+VE_EEAR:
+ .dw $ff04
+ .db "EEAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEAR
+XT_EEAR:
+ .dw PFA_DOVARIABLE
+PFA_EEAR:
+ .dw 62
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw 61
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw 60
+
+.endif
+.if WANT_PORTA == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Register
+VE_PORTA:
+ .dw $ff05
+ .db "PORTA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTA
+XT_PORTA:
+ .dw PFA_DOVARIABLE
+PFA_PORTA:
+ .dw 59
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Direction Register
+VE_DDRA:
+ .dw $ff04
+ .db "DDRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRA
+XT_DDRA:
+ .dw PFA_DOVARIABLE
+PFA_DDRA:
+ .dw 58
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Input Pins
+VE_PINA:
+ .dw $ff04
+ .db "PINA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINA
+XT_PINA:
+ .dw PFA_DOVARIABLE
+PFA_PINA:
+ .dw 57
+
+.endif
+.if WANT_PORTB == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw 56
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw 55
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw 54
+
+.endif
+.if WANT_PORTC == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Register
+VE_PORTC:
+ .dw $ff05
+ .db "PORTC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTC
+XT_PORTC:
+ .dw PFA_DOVARIABLE
+PFA_PORTC:
+ .dw 53
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Direction Register
+VE_DDRC:
+ .dw $ff04
+ .db "DDRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRC
+XT_DDRC:
+ .dw PFA_DOVARIABLE
+PFA_DDRC:
+ .dw 52
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Input Pins
+VE_PINC:
+ .dw $ff04
+ .db "PINC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINC
+XT_PINC:
+ .dw PFA_DOVARIABLE
+PFA_PINC:
+ .dw 51
+
+.endif
+.if WANT_PORTD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw 50
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw 49
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw 48
+
+.endif
+.if WANT_PORTE == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port E
+VE_PORTE:
+ .dw $ff05
+ .db "PORTE",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTE
+XT_PORTE:
+ .dw PFA_DOVARIABLE
+PFA_PORTE:
+ .dw 35
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port E
+VE_DDRE:
+ .dw $ff04
+ .db "DDRE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRE
+XT_DDRE:
+ .dw PFA_DOVARIABLE
+PFA_DDRE:
+ .dw 34
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port E
+VE_PINE:
+ .dw $ff04
+ .db "PINE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINE
+XT_PINE:
+ .dw PFA_DOVARIABLE
+PFA_PINE:
+ .dw 33
+
+.endif
+.if WANT_PORTF == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port F
+VE_PORTF:
+ .dw $ff05
+ .db "PORTF",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTF
+XT_PORTF:
+ .dw PFA_DOVARIABLE
+PFA_PORTF:
+ .dw 98
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port F
+VE_DDRF:
+ .dw $ff04
+ .db "DDRF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRF
+XT_DDRF:
+ .dw PFA_DOVARIABLE
+PFA_DDRF:
+ .dw 97
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port F
+VE_PINF:
+ .dw $ff04
+ .db "PINF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINF
+XT_PINF:
+ .dw PFA_DOVARIABLE
+PFA_PINF:
+ .dw 32
+
+.endif
+.if WANT_PORTG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port G
+VE_PORTG:
+ .dw $ff05
+ .db "PORTG",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTG
+XT_PORTG:
+ .dw PFA_DOVARIABLE
+PFA_PORTG:
+ .dw 101
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port G
+VE_DDRG:
+ .dw $ff04
+ .db "DDRG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRG
+XT_DDRG:
+ .dw PFA_DOVARIABLE
+PFA_DDRG:
+ .dw 100
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port G
+VE_PING:
+ .dw $ff04
+ .db "PING"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PING
+XT_PING:
+ .dw PFA_DOVARIABLE
+PFA_PING:
+ .dw 99
+
+.endif
+.if WANT_TIMER_COUNTER_0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register
+VE_TCCR0:
+ .dw $ff05
+ .db "TCCR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0
+XT_TCCR0:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0:
+ .dw 83
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Register
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw 82
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare Register
+VE_OCR0:
+ .dw $ff04
+ .db "OCR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0
+XT_OCR0:
+ .dw PFA_DOVARIABLE
+PFA_OCR0:
+ .dw 81
+; ( -- addr ) System Constant
+; R( -- )
+; Asynchronus Status Register
+VE_ASSR:
+ .dw $ff04
+ .db "ASSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ASSR
+XT_ASSR:
+ .dw PFA_DOVARIABLE
+PFA_ASSR:
+ .dw 80
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Mask Register
+VE_TIMSK:
+ .dw $ff05
+ .db "TIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK
+XT_TIMSK:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK:
+ .dw 87
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Flag register
+VE_TIFR:
+ .dw $ff04
+ .db "TIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR
+XT_TIFR:
+ .dw PFA_DOVARIABLE
+PFA_TIFR:
+ .dw 86
+
+.endif
+.if WANT_TIMER_COUNTER_1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Extended Timer/Counter Interrupt Mask Register
+VE_ETIMSK:
+ .dw $ff06
+ .db "ETIMSK"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ETIMSK
+XT_ETIMSK:
+ .dw PFA_DOVARIABLE
+PFA_ETIMSK:
+ .dw 125
+; ( -- addr ) System Constant
+; R( -- )
+; Extended Timer/Counter Interrupt Flag register
+VE_ETIFR:
+ .dw $ff05
+ .db "ETIFR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ETIFR
+XT_ETIFR:
+ .dw PFA_DOVARIABLE
+PFA_ETIFR:
+ .dw 124
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw 79
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw 78
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register C
+VE_TCCR1C:
+ .dw $ff06
+ .db "TCCR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1C
+XT_TCCR1C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1C:
+ .dw 122
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Bytes
+VE_TCNT1:
+ .dw $ff05
+ .db "TCNT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1
+XT_TCNT1:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1:
+ .dw 76
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register Bytes
+VE_OCR1A:
+ .dw $ff05
+ .db "OCR1A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1A
+XT_OCR1A:
+ .dw PFA_DOVARIABLE
+PFA_OCR1A:
+ .dw 74
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register Bytes
+VE_OCR1B:
+ .dw $ff05
+ .db "OCR1B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1B
+XT_OCR1B:
+ .dw PFA_DOVARIABLE
+PFA_OCR1B:
+ .dw 72
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register Bytes
+VE_OCR1C:
+ .dw $ff05
+ .db "OCR1C",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1C
+XT_OCR1C:
+ .dw PFA_DOVARIABLE
+PFA_OCR1C:
+ .dw 120
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Bytes
+VE_ICR1:
+ .dw $ff04
+ .db "ICR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1
+XT_ICR1:
+ .dw PFA_DOVARIABLE
+PFA_ICR1:
+ .dw 70
+
+.endif
+.if WANT_TIMER_COUNTER_2 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register
+VE_TCCR2:
+ .dw $ff05
+ .db "TCCR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2
+XT_TCCR2:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2:
+ .dw 69
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Register
+VE_TCNT2:
+ .dw $ff05
+ .db "TCNT2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT2
+XT_TCNT2:
+ .dw PFA_DOVARIABLE
+PFA_TCNT2:
+ .dw 68
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare Register
+VE_OCR2:
+ .dw $ff04
+ .db "OCR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2
+XT_OCR2:
+ .dw PFA_DOVARIABLE
+PFA_OCR2:
+ .dw 67
+
+.endif
+.if WANT_TIMER_COUNTER_3 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Control Register A
+VE_TCCR3A:
+ .dw $ff06
+ .db "TCCR3A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR3A
+XT_TCCR3A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR3A:
+ .dw 139
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Control Register B
+VE_TCCR3B:
+ .dw $ff06
+ .db "TCCR3B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR3B
+XT_TCCR3B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR3B:
+ .dw 138
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Control Register C
+VE_TCCR3C:
+ .dw $ff06
+ .db "TCCR3C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR3C
+XT_TCCR3C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR3C:
+ .dw 140
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Bytes
+VE_TCNT3:
+ .dw $ff05
+ .db "TCNT3",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT3
+XT_TCNT3:
+ .dw PFA_DOVARIABLE
+PFA_TCNT3:
+ .dw 136
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Output Compare Register A Bytes
+VE_OCR3A:
+ .dw $ff05
+ .db "OCR3A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR3A
+XT_OCR3A:
+ .dw PFA_DOVARIABLE
+PFA_OCR3A:
+ .dw 134
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Output Compare Register B Bytes
+VE_OCR3B:
+ .dw $ff05
+ .db "OCR3B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR3B
+XT_OCR3B:
+ .dw PFA_DOVARIABLE
+PFA_OCR3B:
+ .dw 132
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Output compare Register C Bytes
+VE_OCR3C:
+ .dw $ff05
+ .db "OCR3C",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR3C
+XT_OCR3C:
+ .dw PFA_DOVARIABLE
+PFA_OCR3C:
+ .dw 130
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Input Capture Register Bytes
+VE_ICR3:
+ .dw $ff04
+ .db "ICR3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR3
+XT_ICR3:
+ .dw PFA_DOVARIABLE
+PFA_ICR3:
+ .dw 128
+
+.endif
+.if WANT_WATCHDOG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCR:
+ .dw $ff05
+ .db "WDTCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCR
+XT_WDTCR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCR:
+ .dw 65
+
+.endif
+.if WANT_AD_CONVERTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC multiplexer Selection Register
+VE_ADMUX:
+ .dw $ff05
+ .db "ADMUX",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADMUX
+XT_ADMUX:
+ .dw PFA_DOVARIABLE
+PFA_ADMUX:
+ .dw 39
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register
+VE_ADCSRA:
+ .dw $ff06
+ .db "ADCSRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRA
+XT_ADCSRA:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRA:
+ .dw 38
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register Bytes
+VE_ADC:
+ .dw $ff03
+ .db "ADC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADC
+XT_ADC:
+ .dw PFA_DOVARIABLE
+PFA_ADC:
+ .dw 36
+
+.endif
diff --git a/amforth-6.5/avr8/devices/atmega128a/device.py b/amforth-6.5/avr8/devices/atmega128a/device.py
new file mode 100644
index 0000000..ee2580a
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega128a/device.py
@@ -0,0 +1,403 @@
+# Generated Automatically
+
+# Partname ATmega128A
+
+MCUREGS = {
+# Interrupt Vectors
+ 'INT0Addr' : '#2', # External Interrupt Request 0
+ 'INT1Addr' : '#4', # External Interrupt Request 1
+ 'INT2Addr' : '#6', # External Interrupt Request 2
+ 'INT3Addr' : '#8', # External Interrupt Request 3
+ 'INT4Addr' : '#10', # External Interrupt Request 4
+ 'INT5Addr' : '#12', # External Interrupt Request 5
+ 'INT6Addr' : '#14', # External Interrupt Request 6
+ 'INT7Addr' : '#16', # External Interrupt Request 7
+ 'TIMER2_COMPAddr' : '#18', # Timer/Counter2 Compare Match
+ 'TIMER2_OVFAddr' : '#20', # Timer/Counter2 Overflow
+ 'TIMER1_CAPTAddr' : '#22', # Timer/Counter1 Capture Event
+ 'TIMER1_COMPAAddr' : '#24', # Timer/Counter1 Compare Match A
+ 'TIMER1_COMPBAddr' : '#26', # Timer/Counter Compare Match B
+ 'TIMER1_OVFAddr' : '#28', # Timer/Counter1 Overflow
+ 'TIMER0_COMPAddr' : '#30', # Timer/Counter0 Compare Match
+ 'TIMER0_OVFAddr' : '#32', # Timer/Counter0 Overflow
+ 'SPI_STCAddr' : '#34', # SPI Serial Transfer Complete
+ 'USART0_RXAddr' : '#36', # USART0, Rx Complete
+ 'USART0_UDREAddr' : '#38', # USART0 Data Register Empty
+ 'USART0_TXAddr' : '#40', # USART0, Tx Complete
+ 'ADCAddr' : '#42', # ADC Conversion Complete
+ 'EE_READYAddr' : '#44', # EEPROM Ready
+ 'ANALOG_COMPAddr' : '#46', # Analog Comparator
+ 'TIMER1_COMPCAddr' : '#48', # Timer/Counter1 Compare Match C
+ 'TIMER3_CAPTAddr' : '#50', # Timer/Counter3 Capture Event
+ 'TIMER3_COMPAAddr' : '#52', # Timer/Counter3 Compare Match A
+ 'TIMER3_COMPBAddr' : '#54', # Timer/Counter3 Compare Match B
+ 'TIMER3_COMPCAddr' : '#56', # Timer/Counter3 Compare Match C
+ 'TIMER3_OVFAddr' : '#58', # Timer/Counter3 Overflow
+ 'USART1_RXAddr' : '#60', # USART1, Rx Complete
+ 'USART1_UDREAddr' : '#62', # USART1, Data Register Empty
+ 'USART1_TXAddr' : '#64', # USART1, Tx Complete
+ 'TWIAddr' : '#66', # 2-wire Serial Interface
+ 'SPM_READYAddr' : '#68', # Store Program Memory Read
+
+# Module ANALOG_COMPARATOR
+ 'SFIOR' : '$40', # Special Function IO Register
+ 'SFIOR_ACME': '$8', # Analog Comparator Multiplexer
+ 'ACSR' : '$28', # Analog Comparator Control And
+ 'ACSR_ACD': '$80', # Analog Comparator Disable
+ 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
+ 'ACSR_ACO': '$20', # Analog Compare Output
+ 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
+ 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
+ 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
+ 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
+
+# Module SPI
+ 'SPDR' : '$2f', # SPI Data Register
+ 'SPSR' : '$2e', # SPI Status Register
+ 'SPSR_SPIF': '$80', # SPI Interrupt Flag
+ 'SPSR_WCOL': '$40', # Write Collision Flag
+ 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
+ 'SPCR' : '$2d', # SPI Control Register
+ 'SPCR_SPIE': '$80', # SPI Interrupt Enable
+ 'SPCR_SPE': '$40', # SPI Enable
+ 'SPCR_DORD': '$20', # Data Order
+ 'SPCR_MSTR': '$10', # Master/Slave Select
+ 'SPCR_CPOL': '$8', # Clock polarity
+ 'SPCR_CPHA': '$4', # Clock Phase
+ 'SPCR_SPR': '$3', # SPI Clock Rate Selects
+
+# Module TWI
+ 'TWBR' : '$70', # TWI Bit Rate register
+ 'TWCR' : '$74', # TWI Control Register
+ 'TWCR_TWINT': '$80', # TWI Interrupt Flag
+ 'TWCR_TWEA': '$40', # TWI Enable Acknowledge Bit
+ 'TWCR_TWSTA': '$20', # TWI Start Condition Bit
+ 'TWCR_TWSTO': '$10', # TWI Stop Condition Bit
+ 'TWCR_TWWC': '$8', # TWI Write Collition Flag
+ 'TWCR_TWEN': '$4', # TWI Enable Bit
+ 'TWCR_TWIE': '$1', # TWI Interrupt Enable
+ 'TWSR' : '$71', # TWI Status Register
+ 'TWSR_TWS': '$f8', # TWI Status
+ 'TWSR_TWPS': '$3', # TWI Prescaler
+ 'TWDR' : '$73', # TWI Data register
+ 'TWAR' : '$72', # TWI (Slave) Address register
+ 'TWAR_TWA': '$fe', # TWI (Slave) Address register B
+ 'TWAR_TWGCE': '$1', # TWI General Call Recognition E
+
+# Module USART0
+ 'UDR0' : '$2c', # USART I/O Data Register
+ 'UCSR0A' : '$2b', # USART Control and Status Regis
+ 'UCSR0A_RXC0': '$80', # USART Receive Complete
+ 'UCSR0A_TXC0': '$40', # USART Transmitt Complete
+ 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
+ 'UCSR0A_FE0': '$10', # Framing Error
+ 'UCSR0A_DOR0': '$8', # Data overRun
+ 'UCSR0A_UPE0': '$4', # Parity Error
+ 'UCSR0A_U2X0': '$2', # Double the USART transmission
+ 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
+ 'UCSR0B' : '$2a', # USART Control and Status Regis
+ 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
+ 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
+ 'UCSR0B_UDRIE0': '$20', # USART Data register Empty Inte
+ 'UCSR0B_RXEN0': '$10', # Receiver Enable
+ 'UCSR0B_TXEN0': '$8', # Transmitter Enable
+ 'UCSR0B_UCSZ02': '$4', # Character Size
+ 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
+ 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
+ 'UCSR0C' : '$95', # USART Control and Status Regis
+ 'UCSR0C_UMSEL0': '$40', # USART Mode Select
+ 'UCSR0C_UPM0': '$30', # Parity Mode Bits
+ 'UCSR0C_USBS0': '$8', # Stop Bit Select
+ 'UCSR0C_UCSZ0': '$6', # Character Size
+ 'UCSR0C_UCPOL0': '$1', # Clock Polarity
+ 'UBRR0H' : '$90', # USART Baud Rate Register Hight
+ 'UBRR0L' : '$29', # USART Baud Rate Register Low B
+
+# Module USART1
+ 'UDR1' : '$9c', # USART I/O Data Register
+ 'UCSR1A' : '$9b', # USART Control and Status Regis
+ 'UCSR1A_RXC1': '$80', # USART Receive Complete
+ 'UCSR1A_TXC1': '$40', # USART Transmitt Complete
+ 'UCSR1A_UDRE1': '$20', # USART Data Register Empty
+ 'UCSR1A_FE1': '$10', # Framing Error
+ 'UCSR1A_DOR1': '$8', # Data overRun
+ 'UCSR1A_UPE1': '$4', # Parity Error
+ 'UCSR1A_U2X1': '$2', # Double the USART transmission
+ 'UCSR1A_MPCM1': '$1', # Multi-processor Communication
+ 'UCSR1B' : '$9a', # USART Control and Status Regis
+ 'UCSR1B_RXCIE1': '$80', # RX Complete Interrupt Enable
+ 'UCSR1B_TXCIE1': '$40', # TX Complete Interrupt Enable
+ 'UCSR1B_UDRIE1': '$20', # USART Data register Empty Inte
+ 'UCSR1B_RXEN1': '$10', # Receiver Enable
+ 'UCSR1B_TXEN1': '$8', # Transmitter Enable
+ 'UCSR1B_UCSZ12': '$4', # Character Size
+ 'UCSR1B_RXB81': '$2', # Receive Data Bit 8
+ 'UCSR1B_TXB81': '$1', # Transmit Data Bit 8
+ 'UCSR1C' : '$9d', # USART Control and Status Regis
+ 'UCSR1C_UMSEL1': '$40', # USART Mode Select
+ 'UCSR1C_UPM1': '$30', # Parity Mode Bits
+ 'UCSR1C_USBS1': '$8', # Stop Bit Select
+ 'UCSR1C_UCSZ1': '$6', # Character Size
+ 'UCSR1C_UCPOL1': '$1', # Clock Polarity
+ 'UBRR1H' : '$98', # USART Baud Rate Register Hight
+ 'UBRR1L' : '$99', # USART Baud Rate Register Low B
+
+# Module CPU
+ 'SREG' : '$5f', # Status Register
+ 'SREG_I': '$80', # Global Interrupt Enable
+ 'SREG_T': '$40', # Bit Copy Storage
+ 'SREG_H': '$20', # Half Carry Flag
+ 'SREG_S': '$10', # Sign Bit
+ 'SREG_V': '$8', # Two's Complement Overflow Flag
+ 'SREG_N': '$4', # Negative Flag
+ 'SREG_Z': '$2', # Zero Flag
+ 'SREG_C': '$1', # Carry Flag
+ 'SP' : '$5d', # Stack Pointer
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_SRE': '$80', # External SRAM Enable
+ 'MCUCR_SRW10': '$40', # External SRAM Wait State Selec
+ 'MCUCR_SE': '$20', # Sleep Enable
+ 'MCUCR_SM': '$18', # Sleep Mode Select
+ 'MCUCR_SM2': '$4', # Sleep Mode Select
+ 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
+ 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
+ 'MCUCSR' : '$54', # MCU Control And Status Registe
+ 'MCUCSR_JTD': '$80', # JTAG Interface Disable
+ 'MCUCSR_JTRF': '$10', # JTAG Reset Flag
+ 'MCUCSR_WDRF': '$8', # Watchdog Reset Flag
+ 'MCUCSR_BORF': '$4', # Brown-out Reset Flag
+ 'MCUCSR_EXTRF': '$2', # External Reset Flag
+ 'MCUCSR_PORF': '$1', # Power-on reset flag
+ 'XMCRA' : '$6d', # External Memory Control Regist
+ 'XMCRA_SRL': '$70', # Wait state page limit
+ 'XMCRA_SRW0': '$c', # Wait state select bit lower pa
+ 'XMCRA_SRW11': '$2', # Wait state select bit upper pa
+ 'XMCRB' : '$6c', # External Memory Control Regist
+ 'XMCRB_XMBK': '$80', # External Memory Bus Keeper Ena
+ 'XMCRB_XMM': '$7', # External Memory High Mask
+ 'OSCCAL' : '$6f', # Oscillator Calibration Value
+ 'XDIV' : '$5c', # XTAL Divide Control Register
+ 'RAMPZ' : '$5b', # RAM Page Z Select Register
+ 'RAMPZ_RAMPZ0': '$1', # RAM Page Z Select Register Bit
+
+# Module BOOT_LOAD
+ 'SPMCSR' : '$68', # Store Program Memory Control R
+ 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
+ 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
+ 'SPMCSR_RWWSRE': '$10', # Read While Write section read
+ 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
+ 'SPMCSR_PGWRT': '$4', # Page Write
+ 'SPMCSR_PGERS': '$2', # Page Erase
+ 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
+
+# Module JTAG
+ 'OCDR' : '$42', # On-Chip Debug Related Register
+ 'OCDR_OCDR': '$ff', # On-Chip Debug Register Bits
+ 'MCUCSR' : '$54', # MCU Control And Status Registe
+ 'MCUCSR_JTD': '$80', # JTAG Interface Disable
+ 'MCUCSR_JTRF': '$10', # JTAG Reset Flag
+
+# Module MISC
+ 'SFIOR' : '$40', # Special Function IO Register
+ 'SFIOR_TSM': '$80', # Timer/Counter Synchronization
+ 'SFIOR_ACME': '$8', # Analog Comparator Multiplexer
+ 'SFIOR_PUD': '$4', # Pull Up Disable
+ 'SFIOR_PSR0': '$2', # Prescaler Reset Timer/Counter0
+ 'SFIOR_PSR321': '$1', # Prescaler Reset Timer/Counter3
+
+# Module EXTERNAL_INTERRUPT
+ 'EICRA' : '$6a', # External Interrupt Control Reg
+ 'EICRA_ISC3': '$c0', # External Interrupt Sense Contr
+ 'EICRA_ISC2': '$30', # External Interrupt Sense Contr
+ 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
+ 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
+ 'EICRB' : '$5a', # External Interrupt Control Reg
+ 'EICRB_ISC7': '$c0', # External Interrupt 7-4 Sense C
+ 'EICRB_ISC6': '$30', # External Interrupt 7-4 Sense C
+ 'EICRB_ISC5': '$c', # External Interrupt 7-4 Sense C
+ 'EICRB_ISC4': '$3', # External Interrupt 7-4 Sense C
+ 'EIMSK' : '$59', # External Interrupt Mask Regist
+ 'EIMSK_INT': '$ff', # External Interrupt Request 7 E
+ 'EIFR' : '$58', # External Interrupt Flag Regist
+ 'EIFR_INTF': '$ff', # External Interrupt Flags
+
+# Module EEPROM
+ 'EEAR' : '$3e', # EEPROM Read/Write Access Byte
+ 'EEDR' : '$3d', # EEPROM Data Register
+ 'EECR' : '$3c', # EEPROM Control Register
+ 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
+ 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
+ 'EECR_EEWE': '$2', # EEPROM Write Enable
+ 'EECR_EERE': '$1', # EEPROM Read Enable
+
+# Module PORTA
+ 'PORTA' : '$3b', # Port A Data Register
+ 'DDRA' : '$3a', # Port A Data Direction Register
+ 'PINA' : '$39', # Port A Input Pins
+
+# Module PORTB
+ 'PORTB' : '$38', # Port B Data Register
+ 'DDRB' : '$37', # Port B Data Direction Register
+ 'PINB' : '$36', # Port B Input Pins
+
+# Module PORTC
+ 'PORTC' : '$35', # Port C Data Register
+ 'DDRC' : '$34', # Port C Data Direction Register
+ 'PINC' : '$33', # Port C Input Pins
+
+# Module PORTD
+ 'PORTD' : '$32', # Port D Data Register
+ 'DDRD' : '$31', # Port D Data Direction Register
+ 'PIND' : '$30', # Port D Input Pins
+
+# Module PORTE
+ 'PORTE' : '$23', # Data Register, Port E
+ 'DDRE' : '$22', # Data Direction Register, Port
+ 'PINE' : '$21', # Input Pins, Port E
+
+# Module PORTF
+ 'PORTF' : '$62', # Data Register, Port F
+ 'DDRF' : '$61', # Data Direction Register, Port
+ 'PINF' : '$20', # Input Pins, Port F
+
+# Module PORTG
+ 'PORTG' : '$65', # Data Register, Port G
+ 'DDRG' : '$64', # Data Direction Register, Port
+ 'PING' : '$63', # Input Pins, Port G
+
+# Module TIMER_COUNTER_0
+ 'TCCR0' : '$53', # Timer/Counter Control Register
+ 'TCCR0_FOC0': '$80', # Force Output Compare
+ 'TCCR0_WGM00': '$40', # Waveform Generation Mode 0
+ 'TCCR0_COM0': '$30', # Compare Match Output Modes
+ 'TCCR0_WGM01': '$8', # Waveform Generation Mode 1
+ 'TCCR0_CS0': '$7', # Clock Selects
+ 'TCNT0' : '$52', # Timer/Counter Register
+ 'OCR0' : '$51', # Output Compare Register
+ 'ASSR' : '$50', # Asynchronus Status Register
+ 'ASSR_AS0': '$8', # Asynchronus Timer/Counter 0
+ 'ASSR_TCN0UB': '$4', # Timer/Counter0 Update Busy
+ 'ASSR_OCR0UB': '$2', # Output Compare register 0 Busy
+ 'ASSR_TCR0UB': '$1', # Timer/Counter Control Register
+ 'TIMSK' : '$57', # Timer/Counter Interrupt Mask R
+ 'TIMSK_OCIE0': '$2', # Timer/Counter0 Output Compare
+ 'TIMSK_TOIE0': '$1', # Timer/Counter0 Overflow Interr
+ 'TIFR' : '$56', # Timer/Counter Interrupt Flag r
+ 'TIFR_OCF0': '$2', # Output Compare Flag 0
+ 'TIFR_TOV0': '$1', # Timer/Counter0 Overflow Flag
+ 'SFIOR' : '$40', # Special Function IO Register
+ 'SFIOR_TSM': '$80', # Timer/Counter Synchronization
+ 'SFIOR_PSR0': '$2', # Prescaler Reset Timer/Counter0
+
+# Module TIMER_COUNTER_1
+ 'TIMSK' : '$57', # Timer/Counter Interrupt Mask R
+ 'TIMSK_TICIE1': '$20', # Timer/Counter1 Input Capture I
+ 'TIMSK_OCIE1A': '$10', # Timer/Counter1 Output CompareA
+ 'TIMSK_OCIE1B': '$8', # Timer/Counter1 Output CompareB
+ 'TIMSK_TOIE1': '$4', # Timer/Counter1 Overflow Interr
+ 'ETIMSK' : '$7d', # Extended Timer/Counter Interru
+ 'ETIMSK_OCIE1C': '$1', # Timer/Counter 1, Output Compar
+ 'TIFR' : '$56', # Timer/Counter Interrupt Flag r
+ 'TIFR_ICF1': '$20', # Input Capture Flag 1
+ 'TIFR_OCF1A': '$10', # Output Compare Flag 1A
+ 'TIFR_OCF1B': '$8', # Output Compare Flag 1B
+ 'TIFR_TOV1': '$4', # Timer/Counter1 Overflow Flag
+ 'ETIFR' : '$7c', # Extended Timer/Counter Interru
+ 'ETIFR_OCF1C': '$1', # Timer/Counter 1, Output Compar
+ 'SFIOR' : '$40', # Special Function IO Register
+ 'SFIOR_TSM': '$80', # Timer/Counter Synchronization
+ 'SFIOR_PSR321': '$1', # Prescaler Reset, T/C3, T/C2, T
+ 'TCCR1A' : '$4f', # Timer/Counter1 Control Registe
+ 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
+ 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
+ 'TCCR1A_COM1C': '$c', # Compare Output Mode 1C, bits
+ 'TCCR1A_WGM1': '$3', # Waveform Generation Mode Bits
+ 'TCCR1B' : '$4e', # Timer/Counter1 Control Registe
+ 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
+ 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
+ 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
+ 'TCCR1B_CS1': '$7', # Clock Select1 bits
+ 'TCCR1C' : '$7a', # Timer/Counter1 Control Registe
+ 'TCCR1C_FOC1A': '$80', # Force Output Compare for chann
+ 'TCCR1C_FOC1B': '$40', # Force Output Compare for chann
+ 'TCCR1C_FOC1C': '$20', # Force Output Compare for chann
+ 'TCNT1' : '$4c', # Timer/Counter1 Bytes
+ 'OCR1A' : '$4a', # Timer/Counter1 Output Compare
+ 'OCR1B' : '$48', # Timer/Counter1 Output Compare
+ 'OCR1C' : '$78', # Timer/Counter1 Output Compare
+ 'ICR1' : '$46', # Timer/Counter1 Input Capture R
+
+# Module TIMER_COUNTER_2
+ 'TCCR2' : '$45', # Timer/Counter Control Register
+ 'TCCR2_FOC2': '$80', # Force Output Compare
+ 'TCCR2_WGM20': '$40', # Wafeform Generation Mode
+ 'TCCR2_COM2': '$30', # Compare Match Output Mode
+ 'TCCR2_WGM21': '$8', # Waveform Generation Mode
+ 'TCCR2_CS2': '$7', # Clock Select
+ 'TCNT2' : '$44', # Timer/Counter Register
+ 'OCR2' : '$43', # Output Compare Register
+ 'TIFR' : '$56', # Timer/Counter Interrupt Flag R
+ 'TIFR_OCF2': '$80', # Output Compare Flag 2
+ 'TIFR_TOV2': '$40', # Timer/Counter2 Overflow Flag
+ 'TIMSK' : '$57', #
+ 'TIMSK_OCIE2': '$80', #
+ 'TIMSK_TOIE2': '$40', #
+
+# Module TIMER_COUNTER_3
+ 'ETIMSK' : '$7d', # Extended Timer/Counter Interru
+ 'ETIMSK_TICIE3': '$20', # Timer/Counter3 Input Capture I
+ 'ETIMSK_OCIE3A': '$10', # Timer/Counter3 Output CompareA
+ 'ETIMSK_OCIE3B': '$8', # Timer/Counter3 Output CompareB
+ 'ETIMSK_TOIE3': '$4', # Timer/Counter3 Overflow Interr
+ 'ETIMSK_OCIE3C': '$2', # Timer/Counter3, Output Compare
+ 'ETIFR' : '$7c', # Extended Timer/Counter Interru
+ 'ETIFR_ICF3': '$20', # Input Capture Flag 1
+ 'ETIFR_OCF3A': '$10', # Output Compare Flag 1A
+ 'ETIFR_OCF3B': '$8', # Output Compare Flag 1B
+ 'ETIFR_TOV3': '$4', # Timer/Counter3 Overflow Flag
+ 'ETIFR_OCF3C': '$2', # Timer/Counter3 Output Compare
+ 'SFIOR' : '$40', # Special Function IO Register
+ 'SFIOR_TSM': '$80', # Timer/Counter Synchronization
+ 'SFIOR_PSR321': '$1', # Prescaler Reset, T/C3, T/C2, T
+ 'TCCR3A' : '$8b', # Timer/Counter3 Control Registe
+ 'TCCR3A_COM3A': '$c0', # Compare Output Mode 3A, bits
+ 'TCCR3A_COM3B': '$30', # Compare Output Mode 3B, bits
+ 'TCCR3A_COM3C': '$c', # Compare Output Mode 3C, bits
+ 'TCCR3A_WGM3': '$3', # Waveform Generation Mode Bits
+ 'TCCR3B' : '$8a', # Timer/Counter3 Control Registe
+ 'TCCR3B_ICNC3': '$80', # Input Capture 3 Noise Cancele
+ 'TCCR3B_ICES3': '$40', # Input Capture 3 Edge Select
+ 'TCCR3B_WGM3': '$18', # Waveform Generation Mode
+ 'TCCR3B_CS3': '$7', # Clock Select3 bits
+ 'TCCR3C' : '$8c', # Timer/Counter3 Control Registe
+ 'TCCR3C_FOC3A': '$80', # Force Output Compare for chann
+ 'TCCR3C_FOC3B': '$40', # Force Output Compare for chann
+ 'TCCR3C_FOC3C': '$20', # Force Output Compare for chann
+ 'TCNT3' : '$88', # Timer/Counter3 Bytes
+ 'OCR3A' : '$86', # Timer/Counter3 Output Compare
+ 'OCR3B' : '$84', # Timer/Counter3 Output Compare
+ 'OCR3C' : '$82', # Timer/Counter3 Output compare
+ 'ICR3' : '$80', # Timer/Counter3 Input Capture R
+
+# Module WATCHDOG
+ 'WDTCR' : '$41', # Watchdog Timer Control Registe
+ 'WDTCR_WDCE': '$10', # Watchdog Change Enable
+ 'WDTCR_WDE': '$8', # Watch Dog Enable
+ 'WDTCR_WDP': '$7', # Watch Dog Timer Prescaler bits
+
+# Module AD_CONVERTER
+ 'ADMUX' : '$27', # The ADC multiplexer Selection
+ 'ADMUX_REFS': '$c0', # Reference Selection Bits
+ 'ADMUX_ADLAR': '$20', # Left Adjust Result
+ 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
+ 'ADCSRA' : '$26', # The ADC Control and Status reg
+ 'ADCSRA_ADEN': '$80', # ADC Enable
+ 'ADCSRA_ADSC': '$40', # ADC Start Conversion
+ 'ADCSRA_ADFR': '$20', # ADC Free Running Select
+ 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
+ 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
+ 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
+ 'ADC' : '$24', # ADC Data Register Bytes
+
+ '__amforth_dummy':'0'
+}
diff --git a/amforth-6.5/avr8/devices/atmega128a/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega128a/words/no-jtag.asm
new file mode 100644
index 0000000..352a4bb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega128a/words/no-jtag.asm
@@ -0,0 +1,14 @@
+; ( -- )
+; ( -- )
+; MCU
+; disable jtag at runtime
+VE_NOJTAG:
+ .dw $FF05
+ .db "-jtag",0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOJTAG
+XT_NOJTAG:
+ .dw PFA_NOJTAG
+PFA_NOJTAG:
+
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega128a/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega128a/words/no-wdt.asm
new file mode 100644
index 0000000..4a12261
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega128a/words/no-wdt.asm
@@ -0,0 +1,22 @@
+; ( -- )
+; MCU
+; disable watch dog timer at runtime
+VE_NOWDT:
+ .dw $ff04
+ .db "-wdt"
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOWDT
+XT_NOWDT:
+ .dw PFA_NOWDT
+PFA_NOWDT:
+
+; Reset WDT
+ wdr
+; Write logical one to WDTOE and WDE
+ in_ temp1, WDTCR
+ ori temp1, (1<<WDTOE)|(1<<WDE)
+ out WDTCR, temp1
+; Turn off WDT
+ ldi temp1, (0<<WDE)
+ out_ WDTCR, temp1
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega128a/words/sleep.asm b/amforth-6.5/avr8/devices/atmega128a/words/sleep.asm
new file mode 100644
index 0000000..778fa32
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega128a/words/sleep.asm
@@ -0,0 +1,24 @@
+; ( mode -- )
+; MCU
+; put the controller into the specified sleep mode
+VE_SLEEP:
+ .dw $ff05
+ .db "sleep", 0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_SLEEP
+XT_SLEEP:
+ .dw PFA_SLEEP
+PFA_SLEEP:
+ andi tosl, 7 ; leave only legal mode bits
+ swap tosl ; move to correct location (bits 6-4, atmega32)
+ ori tosl, $80 ; set the SE bit (atmega32: bit 7, not bit 0)
+ out_ MCUCR, tosl ; set the sleep config (atmega32: MCUCR not SMCR)
+ sleep ; nighty-night
+;; the 4 lower bits of MCUCR should not be touched
+ in_ tosl, MCUCR
+ andi tosl, $0F
+ out_ MCUCR, tosl
+ ;clr tosl ; need to clean up the SMCR reg before we leave
+ ;out SMCR, tosl ; 0 protects against accidental sleeps
+ loadtos ; pop argument from stack
+ jmp DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega128rfa1/atmega128rfa1.frt b/amforth-6.5/avr8/devices/atmega128rfa1/atmega128rfa1.frt
new file mode 100644
index 0000000..317ebd2
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega128rfa1/atmega128rfa1.frt
@@ -0,0 +1,902 @@
+\ Partname: ATmega128RFA1
+\ generated automatically
+
+\ ANALOG_COMPARATOR
+&123 constant ADCSRB \ ADC Control and Status Register B
+ $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer Enable
+&80 constant ACSR \ Analog Comparator Control And Status Register
+ $80 constant ACSR_ACD \ Analog Comparator Disable
+ $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
+ $20 constant ACSR_ACO \ Analog Compare Output
+ $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
+ $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
+ $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
+ $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select
+&127 constant DIDR1 \ Digital Input Disable Register 1
+ $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
+ $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
+\ USART0
+&198 constant UDR0 \ USART0 I/O Data Register
+&192 constant UCSR0A \ USART0 Control and Status Register A
+ $80 constant UCSR0A_RXC0 \ USART Receive Complete
+ $40 constant UCSR0A_TXC0 \ USART Transmit Complete
+ $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
+ $10 constant UCSR0A_FE0 \ Frame Error
+ $08 constant UCSR0A_DOR0 \ Data OverRun
+ $04 constant UCSR0A_UPE0 \ USART Parity Error
+ $02 constant UCSR0A_U2X0 \ Double the USART Transmission Speed
+ $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
+&193 constant UCSR0B \ USART0 Control and Status Register B
+ $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
+ $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
+ $20 constant UCSR0B_UDRIE0 \ USART Data Register Empty Interrupt Enable
+ $10 constant UCSR0B_RXEN0 \ Receiver Enable
+ $08 constant UCSR0B_TXEN0 \ Transmitter Enable
+ $04 constant UCSR0B_UCSZ02 \ Character Size
+ $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
+ $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
+&194 constant UCSR0C \ USART0 Control and Status Register C
+ $C0 constant UCSR0C_UMSEL0 \ USART Mode Select
+ $30 constant UCSR0C_UPM0 \ Parity Mode
+ $08 constant UCSR0C_USBS0 \ Stop Bit Select
+ $06 constant UCSR0C_UCSZ0 \ Character Size
+ $01 constant UCSR0C_UCPOL0 \ Clock Polarity
+&196 constant UBRR0 \ USART0 Baud Rate Register Bytes
+\ USART1
+&206 constant UDR1 \ USART1 I/O Data Register
+&200 constant UCSR1A \ USART1 Control and Status Register A
+ $80 constant UCSR1A_RXC1 \ USART Receive Complete
+ $40 constant UCSR1A_TXC1 \ USART Transmit Complete
+ $20 constant UCSR1A_UDRE1 \ USART Data Register Empty
+ $10 constant UCSR1A_FE1 \ Frame Error
+ $08 constant UCSR1A_DOR1 \ Data OverRun
+ $04 constant UCSR1A_UPE1 \ USART Parity Error
+ $02 constant UCSR1A_U2X1 \ Double the USART Transmission Speed
+ $01 constant UCSR1A_MPCM1 \ Multi-processor Communication Mode
+&201 constant UCSR1B \ USART1 Control and Status Register B
+ $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable
+ $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable
+ $20 constant UCSR1B_UDRIE1 \ USART Data Register Empty Interrupt Enable
+ $10 constant UCSR1B_RXEN1 \ Receiver Enable
+ $08 constant UCSR1B_TXEN1 \ Transmitter Enable
+ $04 constant UCSR1B_UCSZ12 \ Character Size
+ $02 constant UCSR1B_RXB81 \ Receive Data Bit 8
+ $01 constant UCSR1B_TXB81 \ Transmit Data Bit 8
+&202 constant UCSR1C \ USART1 Control and Status Register C
+ $C0 constant UCSR1C_UMSEL1 \ USART Mode Select
+ $30 constant UCSR1C_UPM1 \ Parity Mode
+ $08 constant UCSR1C_USBS1 \ Stop Bit Select
+ $06 constant UCSR1C_UCSZ1 \ Character Size
+ $01 constant UCSR1C_UCPOL1 \ Clock Polarity
+&204 constant UBRR1 \ USART1 Baud Rate Register Bytes
+\ TWI
+&189 constant TWAMR \ TWI (Slave) Address Mask Register
+ $FE constant TWAMR_TWAM \ TWI Address Mask
+ $01 constant TWAMR_Res \ Reserved Bit
+&184 constant TWBR \ TWI Bit Rate Register
+&188 constant TWCR \ TWI Control Register
+ $80 constant TWCR_TWINT \ TWI Interrupt Flag
+ $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
+ $20 constant TWCR_TWSTA \ TWI START Condition Bit
+ $10 constant TWCR_TWSTO \ TWI STOP Condition Bit
+ $08 constant TWCR_TWWC \ TWI Write Collision Flag
+ $04 constant TWCR_TWEN \ TWI Enable Bit
+ $02 constant TWCR_Res \ Reserved Bit
+ $01 constant TWCR_TWIE \ TWI Interrupt Enable
+&185 constant TWSR \ TWI Status Register
+ $F8 constant TWSR_TWS \ TWI Status
+ $04 constant TWSR_Res \ Reserved Bit
+ $03 constant TWSR_TWPS \ TWI Prescaler Bits
+&187 constant TWDR \ TWI Data Register
+&186 constant TWAR \ TWI (Slave) Address Register
+ $FE constant TWAR_TWA \ TWI (Slave) Address
+ $01 constant TWAR_TWGCE \ TWI General Call Recognition Enable Bit
+\ SPI
+&76 constant SPCR \ SPI Control Register
+ $80 constant SPCR_SPIE \ SPI Interrupt Enable
+ $40 constant SPCR_SPE \ SPI Enable
+ $20 constant SPCR_DORD \ Data Order
+ $10 constant SPCR_MSTR \ Master/Slave Select
+ $08 constant SPCR_CPOL \ Clock polarity
+ $04 constant SPCR_CPHA \ Clock Phase
+ $03 constant SPCR_SPR \ SPI Clock Rate Select 1 and 0
+&77 constant SPSR \ SPI Status Register
+ $80 constant SPSR_SPIF \ SPI Interrupt Flag
+ $40 constant SPSR_WCOL \ Write Collision Flag
+ $3E constant SPSR_Res \ Reserved
+ $01 constant SPSR_SPI2X \ Double SPI Speed Bit
+&78 constant SPDR \ SPI Data Register
+\ PORTA
+&34 constant PORTA \ Port A Data Register
+&33 constant DDRA \ Port A Data Direction Register
+&32 constant PINA \ Port A Input Pins Address
+\ PORTB
+&37 constant PORTB \ Port B Data Register
+&36 constant DDRB \ Port B Data Direction Register
+&35 constant PINB \ Port B Input Pins Address
+\ PORTC
+&40 constant PORTC \ Port C Data Register
+&39 constant DDRC \ Port C Data Direction Register
+&38 constant PINC \ Port C Input Pins Address
+\ PORTD
+&43 constant PORTD \ Port D Data Register
+&42 constant DDRD \ Port D Data Direction Register
+&41 constant PIND \ Port D Input Pins Address
+\ PORTE
+&46 constant PORTE \ Port E Data Register
+&45 constant DDRE \ Port E Data Direction Register
+&44 constant PINE \ Port E Input Pins Address
+\ PORTF
+&49 constant PORTF \ Port F Data Register
+&48 constant DDRF \ Port F Data Direction Register
+&47 constant PINF \ Port F Input Pins Address
+\ PORTG
+&52 constant PORTG \ Port G Data Register
+&51 constant DDRG \ Port G Data Direction Register
+&50 constant PING \ Port G Input Pins Address
+\ TIMER_COUNTER_0
+&72 constant OCR0B \ Timer/Counter0 Output Compare Register B
+&71 constant OCR0A \ Timer/Counter0 Output Compare Register
+&70 constant TCNT0 \ Timer/Counter0 Register
+&69 constant TCCR0B \ Timer/Counter0 Control Register B
+ $80 constant TCCR0B_FOC0A \ Force Output Compare A
+ $40 constant TCCR0B_FOC0B \ Force Output Compare B
+ $30 constant TCCR0B_Res \ Reserved Bit
+ $08 constant TCCR0B_WGM02 \
+ $07 constant TCCR0B_CS0 \ Clock Select
+&68 constant TCCR0A \ Timer/Counter0 Control Register A
+ $C0 constant TCCR0A_COM0A \ Compare Match Output A Mode
+ $30 constant TCCR0A_COM0B \ Compare Match Output B Mode
+ $0C constant TCCR0A_Res \ Reserved Bit
+ $03 constant TCCR0A_WGM0 \ Waveform Generation Mode
+&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
+ $F8 constant TIMSK0_Res \ Reserved
+ $04 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare Match B Interrupt Enable
+ $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match A Interrupt Enable
+ $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
+&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag Register
+ $F8 constant TIFR0_Res \ Reserved
+ $04 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare B Match Flag
+ $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare A Match Flag
+ $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
+&67 constant GTCCR \ General Timer/Counter Control Register
+ $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
+ $7C constant GTCCR_Res \ Reserved
+ $02 constant GTCCR_PSRASY \ Prescaler Reset Timer/Counter2
+ $01 constant GTCCR_PSRSYNC \ Prescaler Reset for Synchronous Timer/Counters
+\ TIMER_COUNTER_2
+&112 constant TIMSK2 \ Timer/Counter Interrupt Mask register
+ $F8 constant TIMSK2_Res \ Reserved Bit
+ $04 constant TIMSK2_OCIE2B \ Timer/Counter2 Output Compare Match B Interrupt Enable
+ $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match A Interrupt Enable
+ $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
+&55 constant TIFR2 \ Timer/Counter Interrupt Flag Register
+ $F8 constant TIFR2_Res \ Reserved Bit
+ $04 constant TIFR2_OCF2B \ Output Compare Flag 2 B
+ $02 constant TIFR2_OCF2A \ Output Compare Flag 2 A
+ $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
+&176 constant TCCR2A \ Timer/Counter2 Control Register A
+ $C0 constant TCCR2A_COM2A \ Compare Match Output A Mode
+ $30 constant TCCR2A_COM2B \ Compare Match Output B Mode
+ $0C constant TCCR2A_Res \ Reserved
+ $03 constant TCCR2A_WGM2 \ Waveform Generation Mode
+&177 constant TCCR2B \ Timer/Counter2 Control Register B
+ $80 constant TCCR2B_FOC2A \ Force Output Compare A
+ $40 constant TCCR2B_FOC2B \ Force Output Compare B
+ $30 constant TCCR2B_Res \ Reserved
+ $08 constant TCCR2B_WGM22 \ Waveform Generation Mode
+ $07 constant TCCR2B_CS2 \ Clock Select
+&178 constant TCNT2 \ Timer/Counter2
+&180 constant OCR2B \ Timer/Counter2 Output Compare Register B
+&179 constant OCR2A \ Timer/Counter2 Output Compare Register A
+&182 constant ASSR \ Asynchronous Status Register
+ $80 constant ASSR_EXCLKAMR \ Enable External Clock Input for AMR
+ $40 constant ASSR_EXCLK \ Enable External Clock Input
+ $20 constant ASSR_AS2 \ Timer/Counter2 Asynchronous Mode
+ $10 constant ASSR_TCN2UB \ Timer/Counter2 Update Busy
+ $08 constant ASSR_OCR2AUB \ Timer/Counter2 Output Compare Register A Update Busy
+ $04 constant ASSR_OCR2BUB \ Timer/Counter2 Output Compare Register B Update Busy
+ $02 constant ASSR_TCR2AUB \ Timer/Counter2 Control Register A Update Busy
+ $01 constant ASSR_TCR2BUB \ Timer/Counter2 Control Register B Update Busy
+\ WATCHDOG
+&96 constant WDTCSR \ Watchdog Timer Control Register
+ $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Flag
+ $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Enable
+ $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
+ $10 constant WDTCSR_WDCE \ Watchdog Change Enable
+ $08 constant WDTCSR_WDE \ Watch Dog Enable
+\ TIMER_COUNTER_5
+&288 constant TCCR5A \ Timer/Counter5 Control Register A
+ $C0 constant TCCR5A_COM5A \ Compare Output Mode for Channel A
+ $30 constant TCCR5A_COM5B \ Compare Output Mode for Channel B
+ $0C constant TCCR5A_COM5C \ Compare Output Mode for Channel C
+ $03 constant TCCR5A_WGM5 \ Waveform Generation Mode
+&289 constant TCCR5B \ Timer/Counter5 Control Register B
+ $80 constant TCCR5B_ICNC5 \ Input Capture 5 Noise Canceller
+ $40 constant TCCR5B_ICES5 \ Input Capture 5 Edge Select
+ $20 constant TCCR5B_Res \ Reserved Bit
+ $18 constant TCCR5B_WGM5 \ Waveform Generation Mode
+ $07 constant TCCR5B_CS5 \ Clock Select
+&290 constant TCCR5C \ Timer/Counter5 Control Register C
+ $80 constant TCCR5C_FOC5A \ Force Output Compare for Channel A
+ $40 constant TCCR5C_FOC5B \ Force Output Compare for Channel B
+ $20 constant TCCR5C_FOC5C \ Force Output Compare for Channel C
+ $1F constant TCCR5C_Res \ Reserved
+&292 constant TCNT5 \ Timer/Counter5 Bytes
+&296 constant OCR5A \ Timer/Counter5 Output Compare Register A Bytes
+&298 constant OCR5B \ Timer/Counter5 Output Compare Register B Bytes
+&300 constant OCR5C \ Timer/Counter5 Output Compare Register C Bytes
+&294 constant ICR5 \ Timer/Counter5 Input Capture Register Bytes
+&115 constant TIMSK5 \ Timer/Counter5 Interrupt Mask Register
+ $C0 constant TIMSK5_Res \ Reserved Bit
+ $20 constant TIMSK5_ICIE5 \ Timer/Counter5 Input Capture Interrupt Enable
+ $10 constant TIMSK5_Res \ Reserved Bit
+ $08 constant TIMSK5_OCIE5C \ Timer/Counter5 Output Compare C Match Interrupt Enable
+ $04 constant TIMSK5_OCIE5B \ Timer/Counter5 Output Compare B Match Interrupt Enable
+ $02 constant TIMSK5_OCIE5A \ Timer/Counter5 Output Compare A Match Interrupt Enable
+ $01 constant TIMSK5_TOIE5 \ Timer/Counter5 Overflow Interrupt Enable
+&58 constant TIFR5 \ Timer/Counter5 Interrupt Flag Register
+ $C0 constant TIFR5_Res \ Reserved Bit
+ $20 constant TIFR5_ICF5 \ Timer/Counter5 Input Capture Flag
+ $10 constant TIFR5_Res \ Reserved Bit
+ $08 constant TIFR5_OCF5C \ Timer/Counter5 Output Compare C Match Flag
+ $04 constant TIFR5_OCF5B \ Timer/Counter5 Output Compare B Match Flag
+ $02 constant TIFR5_OCF5A \ Timer/Counter5 Output Compare A Match Flag
+ $01 constant TIFR5_TOV5 \ Timer/Counter5 Overflow Flag
+\ TIMER_COUNTER_4
+&160 constant TCCR4A \ Timer/Counter4 Control Register A
+ $C0 constant TCCR4A_COM4A \ Compare Output Mode for Channel A
+ $30 constant TCCR4A_COM4B \ Compare Output Mode for Channel B
+ $0C constant TCCR4A_COM4C \ Compare Output Mode for Channel C
+ $03 constant TCCR4A_WGM4 \ Waveform Generation Mode
+&161 constant TCCR4B \ Timer/Counter4 Control Register B
+ $80 constant TCCR4B_ICNC4 \ Input Capture 4 Noise Canceller
+ $40 constant TCCR4B_ICES4 \ Input Capture 4 Edge Select
+ $20 constant TCCR4B_Res \ Reserved Bit
+ $18 constant TCCR4B_WGM4 \ Waveform Generation Mode
+ $07 constant TCCR4B_CS4 \ Clock Select
+&162 constant TCCR4C \ Timer/Counter4 Control Register C
+ $80 constant TCCR4C_FOC4A \ Force Output Compare for Channel A
+ $40 constant TCCR4C_FOC4B \ Force Output Compare for Channel B
+ $20 constant TCCR4C_FOC4C \ Force Output Compare for Channel C
+ $1F constant TCCR4C_Res \ Reserved
+&164 constant TCNT4 \ Timer/Counter4 Bytes
+&168 constant OCR4A \ Timer/Counter4 Output Compare Register A Bytes
+&170 constant OCR4B \ Timer/Counter4 Output Compare Register B Bytes
+&172 constant OCR4C \ Timer/Counter4 Output Compare Register C Bytes
+&166 constant ICR4 \ Timer/Counter4 Input Capture Register Bytes
+&114 constant TIMSK4 \ Timer/Counter4 Interrupt Mask Register
+ $C0 constant TIMSK4_Res \ Reserved Bit
+ $20 constant TIMSK4_ICIE4 \ Timer/Counter4 Input Capture Interrupt Enable
+ $10 constant TIMSK4_Res \ Reserved Bit
+ $08 constant TIMSK4_OCIE4C \ Timer/Counter4 Output Compare C Match Interrupt Enable
+ $04 constant TIMSK4_OCIE4B \ Timer/Counter4 Output Compare B Match Interrupt Enable
+ $02 constant TIMSK4_OCIE4A \ Timer/Counter4 Output Compare A Match Interrupt Enable
+ $01 constant TIMSK4_TOIE4 \ Timer/Counter4 Overflow Interrupt Enable
+&57 constant TIFR4 \ Timer/Counter4 Interrupt Flag Register
+ $C0 constant TIFR4_Res \ Reserved Bit
+ $20 constant TIFR4_ICF4 \ Timer/Counter4 Input Capture Flag
+ $10 constant TIFR4_Res \ Reserved Bit
+ $08 constant TIFR4_OCF4C \ Timer/Counter4 Output Compare C Match Flag
+ $04 constant TIFR4_OCF4B \ Timer/Counter4 Output Compare B Match Flag
+ $02 constant TIFR4_OCF4A \ Timer/Counter4 Output Compare A Match Flag
+ $01 constant TIFR4_TOV4 \ Timer/Counter4 Overflow Flag
+\ TIMER_COUNTER_3
+&144 constant TCCR3A \ Timer/Counter3 Control Register A
+ $C0 constant TCCR3A_COM3A \ Compare Output Mode for Channel A
+ $30 constant TCCR3A_COM3B \ Compare Output Mode for Channel B
+ $0C constant TCCR3A_COM3C \ Compare Output Mode for Channel C
+ $03 constant TCCR3A_WGM3 \ Waveform Generation Mode
+&145 constant TCCR3B \ Timer/Counter3 Control Register B
+ $80 constant TCCR3B_ICNC3 \ Input Capture 3 Noise Canceller
+ $40 constant TCCR3B_ICES3 \ Input Capture 3 Edge Select
+ $20 constant TCCR3B_Res \ Reserved Bit
+ $18 constant TCCR3B_WGM3 \ Waveform Generation Mode
+ $07 constant TCCR3B_CS3 \ Clock Select
+&146 constant TCCR3C \ Timer/Counter3 Control Register C
+ $80 constant TCCR3C_FOC3A \ Force Output Compare for Channel A
+ $40 constant TCCR3C_FOC3B \ Force Output Compare for Channel B
+ $20 constant TCCR3C_FOC3C \ Force Output Compare for Channel C
+ $1F constant TCCR3C_Res \ Reserved
+&148 constant TCNT3 \ Timer/Counter3 Bytes
+&152 constant OCR3A \ Timer/Counter3 Output Compare Register A Bytes
+&154 constant OCR3B \ Timer/Counter3 Output Compare Register B Bytes
+&156 constant OCR3C \ Timer/Counter3 Output Compare Register C Bytes
+&150 constant ICR3 \ Timer/Counter3 Input Capture Register Bytes
+&113 constant TIMSK3 \ Timer/Counter3 Interrupt Mask Register
+ $C0 constant TIMSK3_Res \ Reserved Bit
+ $20 constant TIMSK3_ICIE3 \ Timer/Counter3 Input Capture Interrupt Enable
+ $10 constant TIMSK3_Res \ Reserved Bit
+ $08 constant TIMSK3_OCIE3C \ Timer/Counter3 Output Compare C Match Interrupt Enable
+ $04 constant TIMSK3_OCIE3B \ Timer/Counter3 Output Compare B Match Interrupt Enable
+ $02 constant TIMSK3_OCIE3A \ Timer/Counter3 Output Compare A Match Interrupt Enable
+ $01 constant TIMSK3_TOIE3 \ Timer/Counter3 Overflow Interrupt Enable
+&56 constant TIFR3 \ Timer/Counter3 Interrupt Flag Register
+ $C0 constant TIFR3_Res \ Reserved Bit
+ $20 constant TIFR3_ICF3 \ Timer/Counter3 Input Capture Flag
+ $10 constant TIFR3_Res \ Reserved Bit
+ $08 constant TIFR3_OCF3C \ Timer/Counter3 Output Compare C Match Flag
+ $04 constant TIFR3_OCF3B \ Timer/Counter3 Output Compare B Match Flag
+ $02 constant TIFR3_OCF3A \ Timer/Counter3 Output Compare A Match Flag
+ $01 constant TIFR3_TOV3 \ Timer/Counter3 Overflow Flag
+\ TIMER_COUNTER_1
+&128 constant TCCR1A \ Timer/Counter1 Control Register A
+ $C0 constant TCCR1A_COM1A \ Compare Output Mode for Channel A
+ $30 constant TCCR1A_COM1B \ Compare Output Mode for Channel B
+ $0C constant TCCR1A_COM1C \ Compare Output Mode for Channel C
+ $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
+&129 constant TCCR1B \ Timer/Counter1 Control Register B
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceller
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ $20 constant TCCR1B_Res \ Reserved Bit
+ $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
+ $07 constant TCCR1B_CS1 \ Clock Select
+&130 constant TCCR1C \ Timer/Counter1 Control Register C
+ $80 constant TCCR1C_FOC1A \ Force Output Compare for Channel A
+ $40 constant TCCR1C_FOC1B \ Force Output Compare for Channel B
+ $20 constant TCCR1C_FOC1C \ Force Output Compare for Channel C
+ $1F constant TCCR1C_Res \ Reserved
+&132 constant TCNT1 \ Timer/Counter1 Bytes
+&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
+&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
+&140 constant OCR1C \ Timer/Counter1 Output Compare Register C Bytes
+&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
+&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
+ $C0 constant TIMSK1_Res \ Reserved Bit
+ $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
+ $10 constant TIMSK1_Res \ Reserved Bit
+ $08 constant TIMSK1_OCIE1C \ Timer/Counter1 Output Compare C Match Interrupt Enable
+ $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
+ $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
+ $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
+&54 constant TIFR1 \ Timer/Counter1 Interrupt Flag Register
+ $C0 constant TIFR1_Res \ Reserved Bit
+ $20 constant TIFR1_ICF1 \ Timer/Counter1 Input Capture Flag
+ $10 constant TIFR1_Res \ Reserved Bit
+ $08 constant TIFR1_OCF1C \ Timer/Counter1 Output Compare C Match Flag
+ $04 constant TIFR1_OCF1B \ Timer/Counter1 Output Compare B Match Flag
+ $02 constant TIFR1_OCF1A \ Timer/Counter1 Output Compare A Match Flag
+ $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
+\ TRX24
+&316 constant AES_CTRL \ AES Control Register
+ $80 constant AES_CTRL_AES_REQUEST \ Request AES Operation.
+ $40 constant AES_CTRL_Res \ Reserved Bit
+ $20 constant AES_CTRL_AES_MODE \ Set AES Operation Mode
+ $10 constant AES_CTRL_Res \ Reserved Bit
+ $08 constant AES_CTRL_AES_DIR \ Set AES Operation Direction
+ $04 constant AES_CTRL_AES_IM \ AES Interrupt Enable
+ $03 constant AES_CTRL_Res \ Reserved Bit
+&317 constant AES_STATUS \ AES Status Register
+ $80 constant AES_STATUS_AES_ER \ AES Operation Finished with Error
+ $7E constant AES_STATUS_Res \ Reserved
+ $01 constant AES_STATUS_AES_DONE \ AES Operation Finished with Success
+&318 constant AES_STATE \ AES Plain and Cipher Text Buffer Register
+ $FF constant AES_STATE_AES_STATE \ AES Plain and Cipher Text Buffer
+&319 constant AES_KEY \ AES Encryption and Decryption Key Buffer Register
+ $FF constant AES_KEY_AES_KEY \ AES Encryption/Decryption Key Buffer
+&321 constant TRX_STATUS \ Transceiver Status Register
+ $80 constant TRX_STATUS_CCA_DONE \ CCA Algorithm Status
+ $40 constant TRX_STATUS_CCA_STATUS \ CCA Status Result
+ $20 constant TRX_STATUS_TST_STATUS \ Test mode status
+ $1F constant TRX_STATUS_TRX_STATUS \ Transceiver Main Status
+&322 constant TRX_STATE \ Transceiver State Control Register
+ $E0 constant TRX_STATE_TRAC_STATUS \ Transaction Status
+ $1F constant TRX_STATE_TRX_CMD \ State Control Command
+&323 constant TRX_CTRL_0 \ Reserved
+ $FF constant TRX_CTRL_0_Res \ Reserved
+&324 constant TRX_CTRL_1 \ Transceiver Control Register 1
+ $80 constant TRX_CTRL_1_PA_EXT_EN \ External PA support enable
+ $40 constant TRX_CTRL_1_IRQ_2_EXT_EN \ Connect Frame Start IRQ to TC1
+ $20 constant TRX_CTRL_1_TX_AUTO_CRC_ON \ Enable Automatic CRC Calculation
+ $1F constant TRX_CTRL_1_Res \ Reserved
+&325 constant PHY_TX_PWR \ Transceiver Transmit Power Control Register
+ $C0 constant PHY_TX_PWR_PA_BUF_LT \ Power Amplifier Buffer Lead Time
+ $30 constant PHY_TX_PWR_PA_LT \ Power Amplifier Lead Time
+ $0F constant PHY_TX_PWR_TX_PWR \ Transmit Power Setting
+&326 constant PHY_RSSI \ Receiver Signal Strength Indicator Register
+ $80 constant PHY_RSSI_RX_CRC_VALID \ Received Frame CRC Status
+ $60 constant PHY_RSSI_RND_VALUE \ Random Value
+ $1F constant PHY_RSSI_RSSI \ Receiver Signal Strength Indicator
+&327 constant PHY_ED_LEVEL \ Transceiver Energy Detection Level Register
+ $FF constant PHY_ED_LEVEL_ED_LEVEL \ Energy Detection Level
+&328 constant PHY_CC_CCA \ Transceiver Clear Channel Assessment (CCA) Control Register
+ $80 constant PHY_CC_CCA_CCA_REQUEST \ Manual CCA Measurement Request
+ $60 constant PHY_CC_CCA_CCA_MODE \ Select CCA Measurement Mode
+ $1F constant PHY_CC_CCA_CHANNEL \ RX/TX Channel Selection
+&329 constant CCA_THRES \ Transceiver CCA Threshold Setting Register
+ $F0 constant CCA_THRES_CCA_CS_THRES \ CS Threshold Level for CCA Measurement
+ $0F constant CCA_THRES_CCA_ED_THRES \ ED Threshold Level for CCA Measurement
+&330 constant RX_CTRL \ Transceiver Receive Control Register
+ $0F constant RX_CTRL_PDT_THRES \ Receiver Sensitivity Control
+&331 constant SFD_VALUE \ Start of Frame Delimiter Value Register
+ $FF constant SFD_VALUE_SFD_VALUE \ Start of Frame Delimiter Value
+&332 constant TRX_CTRL_2 \ Transceiver Control Register 2
+ $80 constant TRX_CTRL_2_RX_SAFE_MODE \ RX Safe Mode
+ $7C constant TRX_CTRL_2_Res \ Reserved
+ $03 constant TRX_CTRL_2_OQPSK_DATA_RATE \ Data Rate Selection
+&333 constant ANT_DIV \ Antenna Diversity Control Register
+ $80 constant ANT_DIV_ANT_SEL \ Antenna Diversity Antenna Status
+ $70 constant ANT_DIV_Res \ Reserved
+ $08 constant ANT_DIV_ANT_DIV_EN \ Enable Antenna Diversity
+ $04 constant ANT_DIV_ANT_EXT_SW_EN \ Enable External Antenna Switch Control
+ $03 constant ANT_DIV_ANT_CTRL \ Static Antenna Diversity Switch Control
+&334 constant IRQ_MASK \ Transceiver Interrupt Enable Register
+ $80 constant IRQ_MASK_AWAKE_EN \ Awake Interrupt Enable
+ $40 constant IRQ_MASK_TX_END_EN \ TX_END Interrupt Enable
+ $20 constant IRQ_MASK_AMI_EN \ Address Match Interrupt Enable
+ $10 constant IRQ_MASK_CCA_ED_DONE_EN \ End of ED Measurement Interrupt Enable
+ $08 constant IRQ_MASK_RX_END_EN \ RX_END Interrupt Enable
+ $04 constant IRQ_MASK_RX_START_EN \ RX_START Interrupt Enable
+ $02 constant IRQ_MASK_PLL_UNLOCK_EN \ PLL Unlock Interrupt Enable
+ $01 constant IRQ_MASK_PLL_LOCK_EN \ PLL Lock Interrupt Enable
+&335 constant IRQ_STATUS \ Transceiver Interrupt Status Register
+ $80 constant IRQ_STATUS_AWAKE \ Awake Interrupt Status
+ $40 constant IRQ_STATUS_TX_END \ TX_END Interrupt Status
+ $20 constant IRQ_STATUS_AMI \ Address Match Interrupt Status
+ $10 constant IRQ_STATUS_CCA_ED_DONE \ End of ED Measurement Interrupt Status
+ $08 constant IRQ_STATUS_RX_END \ RX_END Interrupt Status
+ $04 constant IRQ_STATUS_RX_START \ RX_START Interrupt Status
+ $02 constant IRQ_STATUS_PLL_UNLOCK \ PLL Unlock Interrupt Status
+ $01 constant IRQ_STATUS_PLL_LOCK \ PLL Lock Interrupt Status
+&336 constant VREG_CTRL \ Voltage Regulator Control and Status Register
+ $80 constant VREG_CTRL_AVREG_EXT \ Use External AVDD Regulator
+ $40 constant VREG_CTRL_AVDD_OK \ AVDD Supply Voltage Valid
+ $08 constant VREG_CTRL_DVREG_EXT \ Use External DVDD Regulator
+ $04 constant VREG_CTRL_DVDD_OK \ DVDD Supply Voltage Valid
+&337 constant BATMON \ Battery Monitor Control and Status Register
+ $80 constant BATMON_BAT_LOW \ Battery Monitor Interrupt Status
+ $40 constant BATMON_BAT_LOW_EN \ Battery Monitor Interrupt Enable
+ $20 constant BATMON_BATMON_OK \ Battery Monitor Status
+ $10 constant BATMON_BATMON_HR \ Battery Monitor Voltage Range
+ $0F constant BATMON_BATMON_VTH \ Battery Monitor Threshold Voltage
+&338 constant XOSC_CTRL \ Crystal Oscillator Control Register
+ $F0 constant XOSC_CTRL_XTAL_MODE \ Crystal Oscillator Operating Mode
+ $0F constant XOSC_CTRL_XTAL_TRIM \ Crystal Oscillator Load Capacitance Trimming
+&341 constant RX_SYN \ Transceiver Receiver Sensitivity Control Register
+ $80 constant RX_SYN_RX_PDT_DIS \ Prevent Frame Reception
+ $70 constant RX_SYN_Res \ Reserved
+ $0F constant RX_SYN_RX_PDT_LEVEL \ Reduce Receiver Sensitivity
+&343 constant XAH_CTRL_1 \ Transceiver Acknowledgment Frame Control Register 1
+ $C0 constant XAH_CTRL_1_Res \ Reserved Bit
+ $20 constant XAH_CTRL_1_AACK_FLTR_RES_FT \ Filter Reserved Frames
+ $10 constant XAH_CTRL_1_AACK_UPLD_RES_FT \ Process Reserved Frames
+ $08 constant XAH_CTRL_1_Res \ Reserved Bit
+ $04 constant XAH_CTRL_1_AACK_ACK_TIME \ Reduce Acknowledgment Time
+ $02 constant XAH_CTRL_1_AACK_PROM_MODE \ Enable Promiscuous Mode
+ $01 constant XAH_CTRL_1_Res \ Reserved Bit
+&344 constant FTN_CTRL \ Transceiver Filter Tuning Control Register
+ $80 constant FTN_CTRL_FTN_START \ Start Calibration Loop of Filter Tuning Network
+&346 constant PLL_CF \ Transceiver Center Frequency Calibration Control Register
+ $80 constant PLL_CF_PLL_CF_START \ Start Center Frequency Calibration
+&347 constant PLL_DCU \ Transceiver Delay Cell Calibration Control Register
+ $80 constant PLL_DCU_PLL_DCU_START \ Start Delay Cell Calibration
+&348 constant PART_NUM \ Device Identification Register (Part Number)
+ $FF constant PART_NUM_PART_NUM \ Part Number
+&349 constant VERSION_NUM \ Device Identification Register (Version Number)
+ $FF constant VERSION_NUM_VERSION_NUM \ Version Number
+&350 constant MAN_ID_0 \ Device Identification Register (Manufacture ID Low Byte)
+ $80 constant MAN_ID_0_MAN_ID_07 \ Manufacturer ID (Low Byte)
+ $40 constant MAN_ID_0_MAN_ID_06 \ Manufacturer ID (Low Byte)
+ $20 constant MAN_ID_0_MAN_ID_05 \ Manufacturer ID (Low Byte)
+ $10 constant MAN_ID_0_MAN_ID_04 \ Manufacturer ID (Low Byte)
+ $08 constant MAN_ID_0_MAN_ID_03 \ Manufacturer ID (Low Byte)
+ $04 constant MAN_ID_0_MAN_ID_02 \ Manufacturer ID (Low Byte)
+ $02 constant MAN_ID_0_MAN_ID_01 \ Manufacturer ID (Low Byte)
+ $01 constant MAN_ID_0_MAN_ID_00 \ Manufacturer ID (Low Byte)
+&351 constant MAN_ID_1 \ Device Identification Register (Manufacture ID High Byte)
+ $FF constant MAN_ID_1_MAN_ID_ \ Manufacturer ID (High Byte)
+&352 constant SHORT_ADDR_0 \ Transceiver MAC Short Address Register (Low Byte)
+ $80 constant SHORT_ADDR_0_SHORT_ADDR_07 \ MAC Short Address
+ $40 constant SHORT_ADDR_0_SHORT_ADDR_06 \ MAC Short Address
+ $20 constant SHORT_ADDR_0_SHORT_ADDR_05 \ MAC Short Address
+ $10 constant SHORT_ADDR_0_SHORT_ADDR_04 \ MAC Short Address
+ $08 constant SHORT_ADDR_0_SHORT_ADDR_03 \ MAC Short Address
+ $04 constant SHORT_ADDR_0_SHORT_ADDR_02 \ MAC Short Address
+ $02 constant SHORT_ADDR_0_SHORT_ADDR_01 \ MAC Short Address
+ $01 constant SHORT_ADDR_0_SHORT_ADDR_00 \ MAC Short Address
+&353 constant SHORT_ADDR_1 \ Transceiver MAC Short Address Register (High Byte)
+ $FF constant SHORT_ADDR_1_SHORT_ADDR_ \ MAC Short Address
+&354 constant PAN_ID_0 \ Transceiver Personal Area Network ID Register (Low Byte)
+ $80 constant PAN_ID_0_PAN_ID_07 \ MAC Personal Area Network ID
+ $40 constant PAN_ID_0_PAN_ID_06 \ MAC Personal Area Network ID
+ $20 constant PAN_ID_0_PAN_ID_05 \ MAC Personal Area Network ID
+ $10 constant PAN_ID_0_PAN_ID_04 \ MAC Personal Area Network ID
+ $08 constant PAN_ID_0_PAN_ID_03 \ MAC Personal Area Network ID
+ $04 constant PAN_ID_0_PAN_ID_02 \ MAC Personal Area Network ID
+ $02 constant PAN_ID_0_PAN_ID_01 \ MAC Personal Area Network ID
+ $01 constant PAN_ID_0_PAN_ID_00 \ MAC Personal Area Network ID
+&355 constant PAN_ID_1 \ Transceiver Personal Area Network ID Register (High Byte)
+ $FF constant PAN_ID_1_PAN_ID_ \ MAC Personal Area Network ID
+&356 constant IEEE_ADDR_0 \ Transceiver MAC IEEE Address Register 0
+ $80 constant IEEE_ADDR_0_IEEE_ADDR_07 \ MAC IEEE Address
+ $40 constant IEEE_ADDR_0_IEEE_ADDR_06 \ MAC IEEE Address
+ $20 constant IEEE_ADDR_0_IEEE_ADDR_05 \ MAC IEEE Address
+ $10 constant IEEE_ADDR_0_IEEE_ADDR_04 \ MAC IEEE Address
+ $08 constant IEEE_ADDR_0_IEEE_ADDR_03 \ MAC IEEE Address
+ $04 constant IEEE_ADDR_0_IEEE_ADDR_02 \ MAC IEEE Address
+ $02 constant IEEE_ADDR_0_IEEE_ADDR_01 \ MAC IEEE Address
+ $01 constant IEEE_ADDR_0_IEEE_ADDR_00 \ MAC IEEE Address
+&357 constant IEEE_ADDR_1 \ Transceiver MAC IEEE Address Register 1
+ $FF constant IEEE_ADDR_1_IEEE_ADDR_ \ MAC IEEE Address
+&358 constant IEEE_ADDR_2 \ Transceiver MAC IEEE Address Register 2
+ $FF constant IEEE_ADDR_2_IEEE_ADDR_ \ MAC IEEE Address
+&359 constant IEEE_ADDR_3 \ Transceiver MAC IEEE Address Register 3
+ $FF constant IEEE_ADDR_3_IEEE_ADDR_ \ MAC IEEE Address
+&360 constant IEEE_ADDR_4 \ Transceiver MAC IEEE Address Register 4
+ $FF constant IEEE_ADDR_4_IEEE_ADDR_ \ MAC IEEE Address
+&361 constant IEEE_ADDR_5 \ Transceiver MAC IEEE Address Register 5
+ $FF constant IEEE_ADDR_5_IEEE_ADDR_ \ MAC IEEE Address
+&362 constant IEEE_ADDR_6 \ Transceiver MAC IEEE Address Register 6
+ $FF constant IEEE_ADDR_6_IEEE_ADDR_ \ MAC IEEE Address
+&363 constant IEEE_ADDR_7 \ Transceiver MAC IEEE Address Register 7
+ $FF constant IEEE_ADDR_7_IEEE_ADDR_ \ MAC IEEE Address
+&364 constant XAH_CTRL_0 \ Transceiver Extended Operating Mode Control Register
+ $F0 constant XAH_CTRL_0_MAX_FRAME_RETRIES \ Maximum Number of Frame Re-transmission Attempts
+ $0E constant XAH_CTRL_0_MAX_CSMA_RETRIES \ Maximum Number of CSMA-CA Procedure Repetition Attempts
+ $01 constant XAH_CTRL_0_SLOTTED_OPERATION \ Set Slotted Acknowledgment
+&365 constant CSMA_SEED_0 \ Transceiver CSMA-CA Random Number Generator Seed Register
+ $80 constant CSMA_SEED_0_CSMA_SEED_07 \ Seed Value for CSMA Random Number Generator
+ $40 constant CSMA_SEED_0_CSMA_SEED_06 \ Seed Value for CSMA Random Number Generator
+ $20 constant CSMA_SEED_0_CSMA_SEED_05 \ Seed Value for CSMA Random Number Generator
+ $10 constant CSMA_SEED_0_CSMA_SEED_04 \ Seed Value for CSMA Random Number Generator
+ $08 constant CSMA_SEED_0_CSMA_SEED_03 \ Seed Value for CSMA Random Number Generator
+ $04 constant CSMA_SEED_0_CSMA_SEED_02 \ Seed Value for CSMA Random Number Generator
+ $02 constant CSMA_SEED_0_CSMA_SEED_01 \ Seed Value for CSMA Random Number Generator
+ $01 constant CSMA_SEED_0_CSMA_SEED_00 \ Seed Value for CSMA Random Number Generator
+&366 constant CSMA_SEED_1 \ Transceiver Acknowledgment Frame Control Register 2
+ $C0 constant CSMA_SEED_1_AACK_FVN_MODE \ Acknowledgment Frame Filter Mode
+ $20 constant CSMA_SEED_1_AACK_SET_PD \ Set Frame Pending Sub-field
+ $10 constant CSMA_SEED_1_AACK_DIS_ACK \ Disable Acknowledgment Frame Transmission
+ $08 constant CSMA_SEED_1_AACK_I_AM_COORD \ Set Personal Area Network Coordinator
+ $07 constant CSMA_SEED_1_CSMA_SEED_1 \ Seed Value for CSMA Random Number Generator
+&367 constant CSMA_BE \ Transceiver CSMA-CA Back-off Exponent Control Register
+ $F0 constant CSMA_BE_MAX_BE \ Maximum Back-off Exponent
+ $0F constant CSMA_BE_MIN_BE \ Minimum Back-off Exponent
+&374 constant TST_CTRL_DIGI \ Transceiver Digital Test Control Register
+ $0F constant TST_CTRL_DIGI_TST_CTRL_DIG \ Digital Test Controller Register
+&379 constant TST_RX_LENGTH \ Transceiver Received Frame Length Register
+ $FF constant TST_RX_LENGTH_RX_LENGTH \ Received Frame Length
+&384 constant TRXFBST \ Start of frame buffer
+&511 constant TRXFBEND \ End of frame buffer
+\ SYMCNT
+&248 constant SCOCR1HH \ Symbol Counter Output Compare Register 1 HH-Byte
+ $FF constant SCOCR1HH_SCOCR1HH \ Symbol Counter Output Compare Register 1 HH-Byte
+&247 constant SCOCR1HL \ Symbol Counter Output Compare Register 1 HL-Byte
+ $FF constant SCOCR1HL_SCOCR1HL \ Symbol Counter Output Compare Register 1 HL-Byte
+&246 constant SCOCR1LH \ Symbol Counter Output Compare Register 1 LH-Byte
+ $FF constant SCOCR1LH_SCOCR1LH \ Symbol Counter Output Compare Register 1 LH-Byte
+&245 constant SCOCR1LL \ Symbol Counter Output Compare Register 1 LL-Byte
+ $FF constant SCOCR1LL_SCOCR1LL \ Symbol Counter Output Compare Register 1 LL-Byte
+&244 constant SCOCR2HH \ Symbol Counter Output Compare Register 2 HH-Byte
+ $FF constant SCOCR2HH_SCOCR2HH \ Symbol Counter Output Compare Register 2 HH-Byte
+&243 constant SCOCR2HL \ Symbol Counter Output Compare Register 2 HL-Byte
+ $FF constant SCOCR2HL_SCOCR2HL \ Symbol Counter Output Compare Register 2 HL-Byte
+&242 constant SCOCR2LH \ Symbol Counter Output Compare Register 2 LH-Byte
+ $FF constant SCOCR2LH_SCOCR2LH \ Symbol Counter Output Compare Register 2 LH-Byte
+&241 constant SCOCR2LL \ Symbol Counter Output Compare Register 2 LL-Byte
+ $FF constant SCOCR2LL_SCOCR2LL \ Symbol Counter Output Compare Register 2 LL-Byte
+&240 constant SCOCR3HH \ Symbol Counter Output Compare Register 3 HH-Byte
+ $FF constant SCOCR3HH_SCOCR3HH \ Symbol Counter Output Compare Register 3 HH-Byte
+&239 constant SCOCR3HL \ Symbol Counter Output Compare Register 3 HL-Byte
+ $FF constant SCOCR3HL_SCOCR3HL \ Symbol Counter Output Compare Register 3 HL-Byte
+&238 constant SCOCR3LH \ Symbol Counter Output Compare Register 3 LH-Byte
+ $FF constant SCOCR3LH_SCOCR3LH \ Symbol Counter Output Compare Register 3 LH-Byte
+&237 constant SCOCR3LL \ Symbol Counter Output Compare Register 3 LL-Byte
+ $FF constant SCOCR3LL_SCOCR3LL \ Symbol Counter Output Compare Register 3 LL-Byte
+&236 constant SCTSRHH \ Symbol Counter Frame Timestamp Register HH-Byte
+ $FF constant SCTSRHH_SCTSRHH \ Symbol Counter Frame Timestamp Register HH-Byte
+&235 constant SCTSRHL \ Symbol Counter Frame Timestamp Register HL-Byte
+ $FF constant SCTSRHL_SCTSRHL \ Symbol Counter Frame Timestamp Register HL-Byte
+&234 constant SCTSRLH \ Symbol Counter Frame Timestamp Register LH-Byte
+ $FF constant SCTSRLH_SCTSRLH \ Symbol Counter Frame Timestamp Register LH-Byte
+&233 constant SCTSRLL \ Symbol Counter Frame Timestamp Register LL-Byte
+ $FF constant SCTSRLL_SCTSRLL \ Symbol Counter Frame Timestamp Register LL-Byte
+&232 constant SCBTSRHH \ Symbol Counter Beacon Timestamp Register HH-Byte
+ $FF constant SCBTSRHH_SCBTSRHH \ Symbol Counter Beacon Timestamp Register HH-Byte
+&231 constant SCBTSRHL \ Symbol Counter Beacon Timestamp Register HL-Byte
+ $FF constant SCBTSRHL_SCBTSRHL \ Symbol Counter Beacon Timestamp Register HL-Byte
+&230 constant SCBTSRLH \ Symbol Counter Beacon Timestamp Register LH-Byte
+ $FF constant SCBTSRLH_SCBTSRLH \ Symbol Counter Beacon Timestamp Register LH-Byte
+&229 constant SCBTSRLL \ Symbol Counter Beacon Timestamp Register LL-Byte
+ $FF constant SCBTSRLL_SCBTSRLL \ Symbol Counter Beacon Timestamp Register LL-Byte
+&228 constant SCCNTHH \ Symbol Counter Register HH-Byte
+ $FF constant SCCNTHH_SCCNTHH \ Symbol Counter Register HH-Byte
+&227 constant SCCNTHL \ Symbol Counter Register HL-Byte
+ $FF constant SCCNTHL_SCCNTHL \ Symbol Counter Register HL-Byte
+&226 constant SCCNTLH \ Symbol Counter Register LH-Byte
+ $FF constant SCCNTLH_SCCNTLH \ Symbol Counter Register LH-Byte
+&225 constant SCCNTLL \ Symbol Counter Register LL-Byte
+ $FF constant SCCNTLL_SCCNTLL \ Symbol Counter Register LL-Byte
+&224 constant SCIRQS \ Symbol Counter Interrupt Status Register
+ $E0 constant SCIRQS_Res \ Reserved Bit
+ $10 constant SCIRQS_IRQSBO \ Backoff Slot Counter IRQ
+ $08 constant SCIRQS_IRQSOF \ Symbol Counter Overflow IRQ
+ $07 constant SCIRQS_IRQSCP \ Compare Unit 3 Compare Match IRQ
+&223 constant SCIRQM \ Symbol Counter Interrupt Mask Register
+ $E0 constant SCIRQM_Res \ Reserved Bit
+ $10 constant SCIRQM_IRQMBO \ Backoff Slot Counter IRQ enable
+ $08 constant SCIRQM_IRQMOF \ Symbol Counter Overflow IRQ enable
+ $07 constant SCIRQM_IRQMCP \ Symbol Counter Compare Match 3 IRQ enable
+&222 constant SCSR \ Symbol Counter Status Register
+ $FE constant SCSR_Res \ Reserved Bit
+ $01 constant SCSR_SCBSY \ Symbol Counter busy
+&221 constant SCCR1 \ Symbol Counter Control Register 1
+ $FE constant SCCR1_Res \ Reserved Bit
+ $01 constant SCCR1_SCENBO \ Backoff Slot Counter enable
+&220 constant SCCR0 \ Symbol Counter Control Register 0
+ $80 constant SCCR0_SCRES \ Symbol Counter Synchronization
+ $40 constant SCCR0_SCMBTS \ Manual Beacon Timestamp
+ $20 constant SCCR0_SCEN \ Symbol Counter enable
+ $10 constant SCCR0_SCCKSEL \ Symbol Counter Clock Source select
+ $08 constant SCCR0_SCTSE \ Symbol Counter Automatic Timestamping enable
+ $07 constant SCCR0_SCCMP \ Symbol Counter Compare Unit 3 Mode select
+\ EEPROM
+&65 constant EEAR \ EEPROM Address Register Bytes
+&64 constant EEDR \ EEPROM Data Register
+&63 constant EECR \ EEPROM Control Register
+ $C0 constant EECR_Res \ Reserved
+ $30 constant EECR_EEPM \ EEPROM Programming Mode
+ $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
+ $04 constant EECR_EEMPE \ EEPROM Master Write Enable
+ $02 constant EECR_EEPE \ EEPROM Programming Enable
+ $01 constant EECR_EERE \ EEPROM Read Enable
+\ JTAG
+&81 constant OCDR \ On-Chip Debug Register
+ $FF constant OCDR_OCDR \ On-Chip Debug Register Data
+&85 constant MCUCR \ MCU Control Register
+ $80 constant MCUCR_JTD \ JTAG Interface Disable
+&84 constant MCUSR \ MCU Status Register
+ $10 constant MCUSR_JTRF \ JTAG Reset Flag
+\ EXTERNAL_INTERRUPT
+&105 constant EICRA \ External Interrupt Control Register A
+ $C0 constant EICRA_ISC3 \ External Interrupt 3 Sense Control Bit
+ $30 constant EICRA_ISC2 \ External Interrupt 2 Sense Control Bit
+ $0C constant EICRA_ISC1 \ External Interrupt 1 Sense Control Bit
+ $03 constant EICRA_ISC0 \ External Interrupt 0 Sense Control Bit
+&106 constant EICRB \ External Interrupt Control Register B
+ $C0 constant EICRB_ISC7 \ External Interrupt 7 Sense Control Bit
+ $30 constant EICRB_ISC6 \ External Interrupt 6 Sense Control Bit
+ $0C constant EICRB_ISC5 \ External Interrupt 5 Sense Control Bit
+ $03 constant EICRB_ISC4 \ External Interrupt 4 Sense Control Bit
+&61 constant EIMSK \ External Interrupt Mask Register
+ $FF constant EIMSK_INT \ External Interrupt Request Enable
+&60 constant EIFR \ External Interrupt Flag Register
+ $FF constant EIFR_INTF \ External Interrupt Flag
+&109 constant PCMSK2 \ Pin Change Mask Register 2
+ $FF constant PCMSK2_PCINT \ Pin Change Enable Mask
+&108 constant PCMSK1 \ Pin Change Mask Register 1
+ $FF constant PCMSK1_PCINT \ Pin Change Enable Mask
+&107 constant PCMSK0 \ Pin Change Mask Register 0
+&59 constant PCIFR \ Pin Change Interrupt Flag Register
+ $F8 constant PCIFR_Res \ Reserved Bit
+ $07 constant PCIFR_PCIF \ Pin Change Interrupt Flags
+&104 constant PCICR \ Pin Change Interrupt Control Register
+ $F8 constant PCICR_Res \ Reserved Bit
+ $07 constant PCICR_PCIE \ Pin Change Interrupt Enables
+\ AD_CONVERTER
+&124 constant ADMUX \ The ADC Multiplexer Selection Register
+ $C0 constant ADMUX_REFS \ Reference Selection Bits
+ $20 constant ADMUX_ADLAR \ ADC Left Adjust Result
+ $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
+&120 constant ADC \ ADC Data Register Bytes
+&122 constant ADCSRA \ The ADC Control and Status Register A
+ $80 constant ADCSRA_ADEN \ ADC Enable
+ $40 constant ADCSRA_ADSC \ ADC Start Conversion
+ $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
+ $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
+ $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
+ $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
+&119 constant ADCSRC \ The ADC Control and Status Register C
+ $C0 constant ADCSRC_ADTHT \ ADC Track-and-Hold Time
+ $20 constant ADCSRC_Res0 \ Reserved
+ $1F constant ADCSRC_ADSUT \ ADC Start-up Time
+&125 constant DIDR2 \ Digital Input Disable Register 2
+ $80 constant DIDR2_ADC15D \ Reserved Bits
+ $40 constant DIDR2_ADC14D \ Reserved Bits
+ $20 constant DIDR2_ADC13D \ Reserved Bits
+ $10 constant DIDR2_ADC12D \ Reserved Bits
+ $08 constant DIDR2_ADC11D \ Reserved Bits
+ $04 constant DIDR2_ADC10D \ Reserved Bits
+ $02 constant DIDR2_ADC9D \ Reserved Bits
+ $01 constant DIDR2_ADC8D \ Reserved Bits
+&126 constant DIDR0 \ Digital Input Disable Register 0
+ $80 constant DIDR0_ADC7D \ Disable ADC7:0 Digital Input
+ $40 constant DIDR0_ADC6D \ Disable ADC7:0 Digital Input
+ $20 constant DIDR0_ADC5D \ Disable ADC7:0 Digital Input
+ $10 constant DIDR0_ADC4D \ Disable ADC7:0 Digital Input
+ $08 constant DIDR0_ADC3D \ Disable ADC7:0 Digital Input
+ $04 constant DIDR0_ADC2D \ Disable ADC7:0 Digital Input
+ $02 constant DIDR0_ADC1D \ Disable ADC7:0 Digital Input
+ $01 constant DIDR0_ADC0D \ Disable ADC7:0 Digital Input
+\ BOOT_LOAD
+&87 constant SPMCSR \ Store Program Memory Control Register
+ $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
+ $20 constant SPMCSR_SIGRD \ Signature Row Read
+ $10 constant SPMCSR_RWWSRE \ Read While Write Section Read Enable
+ $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
+ $04 constant SPMCSR_PGWRT \ Page Write
+ $02 constant SPMCSR_PGERS \ Page Erase
+ $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
+\ CPU
+&95 constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ $08 constant SREG_V \ Two's Complement Overflow Flag
+ $04 constant SREG_N \ Negative Flag
+ $02 constant SREG_Z \ Zero Flag
+ $01 constant SREG_C \ Carry Flag
+&93 constant SP \ Stack Pointer
+&102 constant OSCCAL \ Oscillator Calibration Value
+ $FF constant OSCCAL_CAL \ Oscillator Calibration Tuning Value
+&97 constant CLKPR \ Clock Prescale Register
+ $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable
+ $70 constant CLKPR_Res \ Reserved
+ $0F constant CLKPR_CLKPS \ Clock Prescaler Select Bits
+&83 constant SMCR \ Sleep Mode Control Register
+ $F0 constant SMCR_Res \ Reserved
+ $0E constant SMCR_SM \ Sleep Mode Select bits
+ $01 constant SMCR_SE \ Sleep Enable
+&91 constant RAMPZ \ Extended Z-pointer Register for ELPM/SPM
+ $FC constant RAMPZ_Res \ Reserved
+ $03 constant RAMPZ_RAMPZ \ Extended Z-Pointer Value
+&75 constant GPIOR2 \ General Purpose I/O Register 2
+ $FF constant GPIOR2_GPIOR \ General Purpose I/O Register 2 Value
+&74 constant GPIOR1 \ General Purpose IO Register 1
+ $FF constant GPIOR1_GPIOR \ General Purpose I/O Register 1 Value
+&62 constant GPIOR0 \ General Purpose IO Register 0
+ $80 constant GPIOR0_GPIOR07 \ General Purpose I/O Register 0 Value
+ $40 constant GPIOR0_GPIOR06 \ General Purpose I/O Register 0 Value
+ $20 constant GPIOR0_GPIOR05 \ General Purpose I/O Register 0 Value
+ $10 constant GPIOR0_GPIOR04 \ General Purpose I/O Register 0 Value
+ $08 constant GPIOR0_GPIOR03 \ General Purpose I/O Register 0 Value
+ $04 constant GPIOR0_GPIOR02 \ General Purpose I/O Register 0 Value
+ $02 constant GPIOR0_GPIOR01 \ General Purpose I/O Register 0 Value
+ $01 constant GPIOR0_GPIOR00 \ General Purpose I/O Register 0 Value
+&99 constant PRR2 \ Power Reduction Register 2
+ $F0 constant PRR2_Res \ Reserved Bit
+ $0F constant PRR2_PRRAM \ Power Reduction SRAMs
+&101 constant PRR1 \ Power Reduction Register 1
+ $80 constant PRR1_Res \ Reserved Bit
+ $40 constant PRR1_PRTRX24 \ Power Reduction Transceiver
+ $20 constant PRR1_PRTIM5 \ Power Reduction Timer/Counter5
+ $10 constant PRR1_PRTIM4 \ Power Reduction Timer/Counter4
+ $08 constant PRR1_PRTIM3 \ Power Reduction Timer/Counter3
+ $07 constant PRR1_PRUSART \ Reserved
+&100 constant PRR0 \ Power Reduction Register0
+ $80 constant PRR0_PRTWI \ Power Reduction TWI
+ $40 constant PRR0_PRTIM2 \ Power Reduction Timer/Counter2
+ $20 constant PRR0_PRTIM0 \ Power Reduction Timer/Counter0
+ $10 constant PRR0_PRPGA \ Power Reduction PGA
+ $08 constant PRR0_PRTIM1 \ Power Reduction Timer/Counter1
+ $04 constant PRR0_PRSPI \ Power Reduction Serial Peripheral Interface
+ $02 constant PRR0_PRUSART0 \ Power Reduction USART
+ $01 constant PRR0_PRADC \ Power Reduction ADC
+\ FLASH
+&117 constant NEMCR \ Flash Extended-Mode Control-Register
+ $40 constant NEMCR_ENEAM \ Enable Extended Address Mode for Extra Rows
+ $30 constant NEMCR_AEAM \ Address for Extended Address Mode of Extra Rows
+&103 constant BGCR \ Reference Voltage Calibration Register
+ $80 constant BGCR_Res \ Reserved Bit
+ $78 constant BGCR_BGCAL_FINE \ Fine Calibration Bits
+ $07 constant BGCR_BGCAL \ Coarse Calibration Bits
+\ PWRCTRL
+&313 constant TRXPR \ Transceiver Pin Register
+ $F0 constant TRXPR_Res \ Reserved
+ $02 constant TRXPR_SLPTR \ Multi-purpose Transceiver Control Bit
+ $01 constant TRXPR_TRXRST \ Force Transceiver Reset
+&309 constant DRTRAM0 \ Data Retention Configuration Register of SRAM 0
+ $C0 constant DRTRAM0_Res \ Reserved
+ $20 constant DRTRAM0_DRTSWOK \ DRT Switch OK
+ $10 constant DRTRAM0_ENDRT \ Enable SRAM Data Retention
+&308 constant DRTRAM1 \ Data Retention Configuration Register of SRAM 1
+ $C0 constant DRTRAM1_Res \ Reserved
+ $20 constant DRTRAM1_DRTSWOK \ DRT Switch OK
+ $10 constant DRTRAM1_ENDRT \ Enable SRAM Data Retention
+&307 constant DRTRAM2 \ Data Retention Configuration Register of SRAM 2
+ $40 constant DRTRAM2_Res \ Reserved Bit
+ $20 constant DRTRAM2_DRTSWOK \ DRT Switch OK
+ $10 constant DRTRAM2_ENDRT \ Enable SRAM Data Retention
+&306 constant DRTRAM3 \ Data Retention Configuration Register of SRAM 3
+ $C0 constant DRTRAM3_Res \ Reserved
+ $20 constant DRTRAM3_DRTSWOK \ DRT Switch OK
+ $10 constant DRTRAM3_ENDRT \ Enable SRAM Data Retention
+&304 constant LLDRL \ Low Leakage Voltage Regulator Data Register (Low-Byte)
+ $F0 constant LLDRL_Res \ Reserved
+ $0F constant LLDRL_LLDRL \ Low-Byte Data Register Bits
+&305 constant LLDRH \ Low Leakage Voltage Regulator Data Register (High-Byte)
+ $E0 constant LLDRH_Res \ Reserved
+ $1F constant LLDRH_LLDRH \ High-Byte Data Register Bits
+&303 constant LLCR \ Low Leakage Voltage Regulator Control Register
+ $C0 constant LLCR_Res \ Reserved Bit
+ $20 constant LLCR_LLDONE \ Calibration Done
+ $10 constant LLCR_LLCOMP \ Comparator Output
+ $08 constant LLCR_LLCAL \ Calibration Active
+ $04 constant LLCR_LLTCO \ Temperature Coefficient of Current Source
+ $02 constant LLCR_LLSHORT \ Short Lower Calibration Circuit
+ $01 constant LLCR_LLENCAL \ Enable Automatic Calibration
+&310 constant DPDS0 \ Port Driver Strength Register 0
+ $C0 constant DPDS0_PFDRV \ Driver Strength Port F
+ $30 constant DPDS0_PEDRV \ Driver Strength Port E
+ $0C constant DPDS0_PDDRV \ Driver Strength Port D
+ $03 constant DPDS0_PBDRV \ Driver Strength Port B
+&311 constant DPDS1 \ Port Driver Strength Register 1
+ $FC constant DPDS1_Res \ Reserved
+ $03 constant DPDS1_PGDRV \ Driver Strength Port G
+\ USART0_SPI
+\ USART1_SPI
+
+\ Interrupts
+&2 constant INT0Addr \ External Interrupt Request 0
+&4 constant INT1Addr \ External Interrupt Request 1
+&6 constant INT2Addr \ External Interrupt Request 2
+&8 constant INT3Addr \ External Interrupt Request 3
+&10 constant INT4Addr \ External Interrupt Request 4
+&12 constant INT5Addr \ External Interrupt Request 5
+&14 constant INT6Addr \ External Interrupt Request 6
+&16 constant INT7Addr \ External Interrupt Request 7
+&18 constant PCINT0Addr \ Pin Change Interrupt Request 0
+&20 constant PCINT1Addr \ Pin Change Interrupt Request 1
+&22 constant PCINT2Addr \ Pin Change Interrupt Request 2
+&24 constant WDTAddr \ Watchdog Time-out Interrupt
+&26 constant TIMER2_COMPAAddr \ Timer/Counter2 Compare Match A
+&28 constant TIMER2_COMPBAddr \ Timer/Counter2 Compare Match B
+&30 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
+&32 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+&34 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
+&36 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
+&38 constant TIMER1_COMPCAddr \ Timer/Counter1 Compare Match C
+&40 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+&42 constant TIMER0_COMPAAddr \ Timer/Counter0 Compare Match A
+&44 constant TIMER0_COMPBAddr \ Timer/Counter0 Compare Match B
+&46 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
+&48 constant SPI_STCAddr \ SPI Serial Transfer Complete
+&50 constant USART0_RXAddr \ USART0, Rx Complete
+&52 constant USART0_UDREAddr \ USART0 Data register Empty
+&54 constant USART0_TXAddr \ USART0, Tx Complete
+&56 constant ANALOG_COMPAddr \ Analog Comparator
+&58 constant ADCAddr \ ADC Conversion Complete
+&60 constant EE_READYAddr \ EEPROM Ready
+&62 constant TIMER3_CAPTAddr \ Timer/Counter3 Capture Event
+&64 constant TIMER3_COMPAAddr \ Timer/Counter3 Compare Match A
+&66 constant TIMER3_COMPBAddr \ Timer/Counter3 Compare Match B
+&68 constant TIMER3_COMPCAddr \ Timer/Counter3 Compare Match C
+&70 constant TIMER3_OVFAddr \ Timer/Counter3 Overflow
+&72 constant USART1_RXAddr \ USART1, Rx Complete
+&74 constant USART1_UDREAddr \ USART1 Data register Empty
+&76 constant USART1_TXAddr \ USART1, Tx Complete
+&78 constant TWIAddr \ 2-wire Serial Interface
+&80 constant SPM_READYAddr \ Store Program Memory Read
+&82 constant TIMER4_CAPTAddr \ Timer/Counter4 Capture Event
+&84 constant TIMER4_COMPAAddr \ Timer/Counter4 Compare Match A
+&86 constant TIMER4_COMPBAddr \ Timer/Counter4 Compare Match B
+&88 constant TIMER4_COMPCAddr \ Timer/Counter4 Compare Match C
+&90 constant TIMER4_OVFAddr \ Timer/Counter4 Overflow
+&92 constant TIMER5_CAPTAddr \ Timer/Counter5 Capture Event
+&94 constant TIMER5_COMPAAddr \ Timer/Counter5 Compare Match A
+&96 constant TIMER5_COMPBAddr \ Timer/Counter5 Compare Match B
+&98 constant TIMER5_COMPCAddr \ Timer/Counter5 Compare Match C
+&100 constant TIMER5_OVFAddr \ Timer/Counter5 Overflow
+&102 constant USART2_RXAddr \ USART2, Rx Complete
+&104 constant USART2_UDREAddr \ USART2 Data register Empty
+&106 constant USART2_TXAddr \ USART2, Tx Complete
+&108 constant USART3_RXAddr \ USART3, Rx Complete
+&110 constant USART3_UDREAddr \ USART3 Data register Empty
+&112 constant USART3_TXAddr \ USART3, Tx Complete
+&114 constant TRX24_PLL_LOCKAddr \ TRX24 - PLL lock interrupt
+&116 constant TRX24_PLL_UNLOCKAddr \ TRX24 - PLL unlock interrupt
+&118 constant TRX24_RX_STARTAddr \ TRX24 - Receive start interrupt
+&120 constant TRX24_RX_ENDAddr \ TRX24 - RX_END interrupt
+&122 constant TRX24_CCA_ED_DONEAddr \ TRX24 - CCA/ED done interrupt
+&124 constant TRX24_XAH_AMIAddr \ TRX24 - XAH - AMI
+&126 constant TRX24_TX_ENDAddr \ TRX24 - TX_END interrupt
+&128 constant TRX24_AWAKEAddr \ TRX24 AWAKE - tranceiver is reaching state
+&130 constant SCNT_CMP1Addr \ Symbol counter - compare match 1 interrupt
+&132 constant SCNT_CMP2Addr \ Symbol counter - compare match 2 interrupt
+&134 constant SCNT_CMP3Addr \ Symbol counter - compare match 3 interrupt
+&136 constant SCNT_OVFLAddr \ Symbol counter - overflow interrupt
+&138 constant SCNT_BACKOFFAddr \ Symbol counter - backoff interrupt
+&140 constant AES_READYAddr \ AES engine ready interrupt
+&142 constant BAT_LOWAddr \ Battery monitor indicates supply voltage below
diff --git a/amforth-6.5/avr8/devices/atmega128rfa1/device.asm b/amforth-6.5/avr8/devices/atmega128rfa1/device.asm
new file mode 100644
index 0000000..e81539e
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega128rfa1/device.asm
@@ -0,0 +1,220 @@
+; Partname: ATmega128RFA1
+; generated automatically, do not edit
+
+.nolist
+ .include "m128RFA1def.inc"
+.list
+
+.equ ramstart = 512
+.equ CELLSIZE = 2
+.macro readflashcell
+ clr temp7
+ lsl zl
+ rol zh
+ rol temp7
+ out_ RAMPZ, temp7
+ elpm @0, Z+
+ elpm @1, Z+
+.endmacro
+.macro writeflashcell
+ clr temp7
+ lsl zl
+ rol zh
+ rol temp7
+ out_ RAMPZ, temp7
+.endmacro
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_USART0 = 0
+.set WANT_USART1 = 0
+.set WANT_TWI = 0
+.set WANT_SPI = 0
+.set WANT_PORTA = 0
+.set WANT_PORTB = 0
+.set WANT_PORTC = 0
+.set WANT_PORTD = 0
+.set WANT_PORTE = 0
+.set WANT_PORTF = 0
+.set WANT_PORTG = 0
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_TIMER_COUNTER_2 = 0
+.set WANT_WATCHDOG = 0
+.set WANT_TIMER_COUNTER_5 = 0
+.set WANT_TIMER_COUNTER_4 = 0
+.set WANT_TIMER_COUNTER_3 = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_TRX24 = 0
+.set WANT_SYMCNT = 0
+.set WANT_EEPROM = 0
+.set WANT_JTAG = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_AD_CONVERTER = 0
+.set WANT_BOOT_LOAD = 0
+.set WANT_CPU = 0
+.set WANT_FLASH = 0
+.set WANT_PWRCTRL = 0
+.set WANT_USART0_SPI = 0
+.set WANT_USART1_SPI = 0
+.equ intvecsize = 2 ; please verify; flash size: 131072 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.org 2
+ rcall isr ; External Interrupt Request 0
+.org 4
+ rcall isr ; External Interrupt Request 1
+.org 6
+ rcall isr ; External Interrupt Request 2
+.org 8
+ rcall isr ; External Interrupt Request 3
+.org 10
+ rcall isr ; External Interrupt Request 4
+.org 12
+ rcall isr ; External Interrupt Request 5
+.org 14
+ rcall isr ; External Interrupt Request 6
+.org 16
+ rcall isr ; External Interrupt Request 7
+.org 18
+ rcall isr ; Pin Change Interrupt Request 0
+.org 20
+ rcall isr ; Pin Change Interrupt Request 1
+.org 22
+ rcall isr ; Pin Change Interrupt Request 2
+.org 24
+ rcall isr ; Watchdog Time-out Interrupt
+.org 26
+ rcall isr ; Timer/Counter2 Compare Match A
+.org 28
+ rcall isr ; Timer/Counter2 Compare Match B
+.org 30
+ rcall isr ; Timer/Counter2 Overflow
+.org 32
+ rcall isr ; Timer/Counter1 Capture Event
+.org 34
+ rcall isr ; Timer/Counter1 Compare Match A
+.org 36
+ rcall isr ; Timer/Counter1 Compare Match B
+.org 38
+ rcall isr ; Timer/Counter1 Compare Match C
+.org 40
+ rcall isr ; Timer/Counter1 Overflow
+.org 42
+ rcall isr ; Timer/Counter0 Compare Match A
+.org 44
+ rcall isr ; Timer/Counter0 Compare Match B
+.org 46
+ rcall isr ; Timer/Counter0 Overflow
+.org 48
+ rcall isr ; SPI Serial Transfer Complete
+.org 50
+ rcall isr ; USART0, Rx Complete
+.org 52
+ rcall isr ; USART0 Data register Empty
+.org 54
+ rcall isr ; USART0, Tx Complete
+.org 56
+ rcall isr ; Analog Comparator
+.org 58
+ rcall isr ; ADC Conversion Complete
+.org 60
+ rcall isr ; EEPROM Ready
+.org 62
+ rcall isr ; Timer/Counter3 Capture Event
+.org 64
+ rcall isr ; Timer/Counter3 Compare Match A
+.org 66
+ rcall isr ; Timer/Counter3 Compare Match B
+.org 68
+ rcall isr ; Timer/Counter3 Compare Match C
+.org 70
+ rcall isr ; Timer/Counter3 Overflow
+.org 72
+ rcall isr ; USART1, Rx Complete
+.org 74
+ rcall isr ; USART1 Data register Empty
+.org 76
+ rcall isr ; USART1, Tx Complete
+.org 78
+ rcall isr ; 2-wire Serial Interface
+.org 80
+ rcall isr ; Store Program Memory Read
+.org 82
+ rcall isr ; Timer/Counter4 Capture Event
+.org 84
+ rcall isr ; Timer/Counter4 Compare Match A
+.org 86
+ rcall isr ; Timer/Counter4 Compare Match B
+.org 88
+ rcall isr ; Timer/Counter4 Compare Match C
+.org 90
+ rcall isr ; Timer/Counter4 Overflow
+.org 92
+ rcall isr ; Timer/Counter5 Capture Event
+.org 94
+ rcall isr ; Timer/Counter5 Compare Match A
+.org 96
+ rcall isr ; Timer/Counter5 Compare Match B
+.org 98
+ rcall isr ; Timer/Counter5 Compare Match C
+.org 100
+ rcall isr ; Timer/Counter5 Overflow
+.org 102
+ rcall isr ; USART2, Rx Complete
+.org 104
+ rcall isr ; USART2 Data register Empty
+.org 106
+ rcall isr ; USART2, Tx Complete
+.org 108
+ rcall isr ; USART3, Rx Complete
+.org 110
+ rcall isr ; USART3 Data register Empty
+.org 112
+ rcall isr ; USART3, Tx Complete
+.org 114
+ rcall isr ; TRX24 - PLL lock interrupt
+.org 116
+ rcall isr ; TRX24 - PLL unlock interrupt
+.org 118
+ rcall isr ; TRX24 - Receive start interrupt
+.org 120
+ rcall isr ; TRX24 - RX_END interrupt
+.org 122
+ rcall isr ; TRX24 - CCA/ED done interrupt
+.org 124
+ rcall isr ; TRX24 - XAH - AMI
+.org 126
+ rcall isr ; TRX24 - TX_END interrupt
+.org 128
+ rcall isr ; TRX24 AWAKE - tranceiver is reaching state TRX_OFF
+.org 130
+ rcall isr ; Symbol counter - compare match 1 interrupt
+.org 132
+ rcall isr ; Symbol counter - compare match 2 interrupt
+.org 134
+ rcall isr ; Symbol counter - compare match 3 interrupt
+.org 136
+ rcall isr ; Symbol counter - overflow interrupt
+.org 138
+ rcall isr ; Symbol counter - backoff interrupt
+.org 140
+ rcall isr ; AES engine ready interrupt
+.org 142
+ rcall isr ; Battery monitor indicates supply voltage below threshold
+.equ INTVECTORS = 72
+.nooverlap
+
+; compatability layer (maybe empty)
+
+; controller data area, environment query mcu-info
+mcu_info:
+mcu_ramsize:
+ .dw 16384
+mcu_eepromsize:
+ .dw 4096
+mcu_maxdp:
+ .dw 65535
+mcu_numints:
+ .dw 72
+mcu_name:
+ .dw 13
+ .db "ATmega128RFA1",0
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega128rfa1/device.inc b/amforth-6.5/avr8/devices/atmega128rfa1/device.inc
new file mode 100644
index 0000000..503bb63
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega128rfa1/device.inc
@@ -0,0 +1,2808 @@
+; Partname: ATmega128RFA1
+; generated automatically, no not edit
+
+.if WANT_ANALOG_COMPARATOR == 1
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Control and Status Register B
+VE_ADCSRB:
+ .dw $ff06
+ .db "ADCSRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRB
+XT_ADCSRB:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRB:
+ .dw 123
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Control And Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw 80
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 1
+VE_DIDR1:
+ .dw $ff05
+ .db "DIDR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR1
+XT_DIDR1:
+ .dw PFA_DOVARIABLE
+PFA_DIDR1:
+ .dw 127
+
+.endif
+.if WANT_USART0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART0 I/O Data Register
+VE_UDR0:
+ .dw $ff04
+ .db "UDR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR0
+XT_UDR0:
+ .dw PFA_DOVARIABLE
+PFA_UDR0:
+ .dw 198
+; ( -- addr ) System Constant
+; R( -- )
+; USART0 Control and Status Register A
+VE_UCSR0A:
+ .dw $ff06
+ .db "UCSR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0A
+XT_UCSR0A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0A:
+ .dw 192
+; ( -- addr ) System Constant
+; R( -- )
+; USART0 Control and Status Register B
+VE_UCSR0B:
+ .dw $ff06
+ .db "UCSR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0B
+XT_UCSR0B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0B:
+ .dw 193
+; ( -- addr ) System Constant
+; R( -- )
+; USART0 Control and Status Register C
+VE_UCSR0C:
+ .dw $ff06
+ .db "UCSR0C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0C
+XT_UCSR0C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0C:
+ .dw 194
+; ( -- addr ) System Constant
+; R( -- )
+; USART0 Baud Rate Register Bytes
+VE_UBRR0:
+ .dw $ff05
+ .db "UBRR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR0
+XT_UBRR0:
+ .dw PFA_DOVARIABLE
+PFA_UBRR0:
+ .dw 196
+
+.endif
+.if WANT_USART1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART1 I/O Data Register
+VE_UDR1:
+ .dw $ff04
+ .db "UDR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR1
+XT_UDR1:
+ .dw PFA_DOVARIABLE
+PFA_UDR1:
+ .dw 206
+; ( -- addr ) System Constant
+; R( -- )
+; USART1 Control and Status Register A
+VE_UCSR1A:
+ .dw $ff06
+ .db "UCSR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1A
+XT_UCSR1A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1A:
+ .dw 200
+; ( -- addr ) System Constant
+; R( -- )
+; USART1 Control and Status Register B
+VE_UCSR1B:
+ .dw $ff06
+ .db "UCSR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1B
+XT_UCSR1B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1B:
+ .dw 201
+; ( -- addr ) System Constant
+; R( -- )
+; USART1 Control and Status Register C
+VE_UCSR1C:
+ .dw $ff06
+ .db "UCSR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1C
+XT_UCSR1C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1C:
+ .dw 202
+; ( -- addr ) System Constant
+; R( -- )
+; USART1 Baud Rate Register Bytes
+VE_UBRR1:
+ .dw $ff05
+ .db "UBRR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR1
+XT_UBRR1:
+ .dw PFA_DOVARIABLE
+PFA_UBRR1:
+ .dw 204
+
+.endif
+.if WANT_TWI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; TWI (Slave) Address Mask Register
+VE_TWAMR:
+ .dw $ff05
+ .db "TWAMR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWAMR
+XT_TWAMR:
+ .dw PFA_DOVARIABLE
+PFA_TWAMR:
+ .dw 189
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Bit Rate Register
+VE_TWBR:
+ .dw $ff04
+ .db "TWBR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWBR
+XT_TWBR:
+ .dw PFA_DOVARIABLE
+PFA_TWBR:
+ .dw 184
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Control Register
+VE_TWCR:
+ .dw $ff04
+ .db "TWCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWCR
+XT_TWCR:
+ .dw PFA_DOVARIABLE
+PFA_TWCR:
+ .dw 188
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Status Register
+VE_TWSR:
+ .dw $ff04
+ .db "TWSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWSR
+XT_TWSR:
+ .dw PFA_DOVARIABLE
+PFA_TWSR:
+ .dw 185
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Data Register
+VE_TWDR:
+ .dw $ff04
+ .db "TWDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWDR
+XT_TWDR:
+ .dw PFA_DOVARIABLE
+PFA_TWDR:
+ .dw 187
+; ( -- addr ) System Constant
+; R( -- )
+; TWI (Slave) Address Register
+VE_TWAR:
+ .dw $ff04
+ .db "TWAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWAR
+XT_TWAR:
+ .dw PFA_DOVARIABLE
+PFA_TWAR:
+ .dw 186
+
+.endif
+.if WANT_SPI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR:
+ .dw $ff04
+ .db "SPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR
+XT_SPCR:
+ .dw PFA_DOVARIABLE
+PFA_SPCR:
+ .dw 76
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR:
+ .dw $ff04
+ .db "SPSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR
+XT_SPSR:
+ .dw PFA_DOVARIABLE
+PFA_SPSR:
+ .dw 77
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR:
+ .dw $ff04
+ .db "SPDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR
+XT_SPDR:
+ .dw PFA_DOVARIABLE
+PFA_SPDR:
+ .dw 78
+
+.endif
+.if WANT_PORTA == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Register
+VE_PORTA:
+ .dw $ff05
+ .db "PORTA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTA
+XT_PORTA:
+ .dw PFA_DOVARIABLE
+PFA_PORTA:
+ .dw 34
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Direction Register
+VE_DDRA:
+ .dw $ff04
+ .db "DDRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRA
+XT_DDRA:
+ .dw PFA_DOVARIABLE
+PFA_DDRA:
+ .dw 33
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Input Pins Address
+VE_PINA:
+ .dw $ff04
+ .db "PINA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINA
+XT_PINA:
+ .dw PFA_DOVARIABLE
+PFA_PINA:
+ .dw 32
+
+.endif
+.if WANT_PORTB == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw 37
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw 36
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins Address
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw 35
+
+.endif
+.if WANT_PORTC == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Register
+VE_PORTC:
+ .dw $ff05
+ .db "PORTC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTC
+XT_PORTC:
+ .dw PFA_DOVARIABLE
+PFA_PORTC:
+ .dw 40
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Direction Register
+VE_DDRC:
+ .dw $ff04
+ .db "DDRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRC
+XT_DDRC:
+ .dw PFA_DOVARIABLE
+PFA_DDRC:
+ .dw 39
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Input Pins Address
+VE_PINC:
+ .dw $ff04
+ .db "PINC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINC
+XT_PINC:
+ .dw PFA_DOVARIABLE
+PFA_PINC:
+ .dw 38
+
+.endif
+.if WANT_PORTD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw 43
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw 42
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins Address
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw 41
+
+.endif
+.if WANT_PORTE == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port E Data Register
+VE_PORTE:
+ .dw $ff05
+ .db "PORTE",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTE
+XT_PORTE:
+ .dw PFA_DOVARIABLE
+PFA_PORTE:
+ .dw 46
+; ( -- addr ) System Constant
+; R( -- )
+; Port E Data Direction Register
+VE_DDRE:
+ .dw $ff04
+ .db "DDRE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRE
+XT_DDRE:
+ .dw PFA_DOVARIABLE
+PFA_DDRE:
+ .dw 45
+; ( -- addr ) System Constant
+; R( -- )
+; Port E Input Pins Address
+VE_PINE:
+ .dw $ff04
+ .db "PINE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINE
+XT_PINE:
+ .dw PFA_DOVARIABLE
+PFA_PINE:
+ .dw 44
+
+.endif
+.if WANT_PORTF == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port F Data Register
+VE_PORTF:
+ .dw $ff05
+ .db "PORTF",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTF
+XT_PORTF:
+ .dw PFA_DOVARIABLE
+PFA_PORTF:
+ .dw 49
+; ( -- addr ) System Constant
+; R( -- )
+; Port F Data Direction Register
+VE_DDRF:
+ .dw $ff04
+ .db "DDRF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRF
+XT_DDRF:
+ .dw PFA_DOVARIABLE
+PFA_DDRF:
+ .dw 48
+; ( -- addr ) System Constant
+; R( -- )
+; Port F Input Pins Address
+VE_PINF:
+ .dw $ff04
+ .db "PINF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINF
+XT_PINF:
+ .dw PFA_DOVARIABLE
+PFA_PINF:
+ .dw 47
+
+.endif
+.if WANT_PORTG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Data Register
+VE_PORTG:
+ .dw $ff05
+ .db "PORTG",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTG
+XT_PORTG:
+ .dw PFA_DOVARIABLE
+PFA_PORTG:
+ .dw 52
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Data Direction Register
+VE_DDRG:
+ .dw $ff04
+ .db "DDRG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRG
+XT_DDRG:
+ .dw PFA_DOVARIABLE
+PFA_DDRG:
+ .dw 51
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Input Pins Address
+VE_PING:
+ .dw $ff04
+ .db "PING"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PING
+XT_PING:
+ .dw PFA_DOVARIABLE
+PFA_PING:
+ .dw 50
+
+.endif
+.if WANT_TIMER_COUNTER_0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register B
+VE_OCR0B:
+ .dw $ff05
+ .db "OCR0B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0B
+XT_OCR0B:
+ .dw PFA_DOVARIABLE
+PFA_OCR0B:
+ .dw 72
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0A:
+ .dw $ff05
+ .db "OCR0A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0A
+XT_OCR0A:
+ .dw PFA_DOVARIABLE
+PFA_OCR0A:
+ .dw 71
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Register
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw 70
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Control Register B
+VE_TCCR0B:
+ .dw $ff06
+ .db "TCCR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0B
+XT_TCCR0B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0B:
+ .dw 69
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Control Register A
+VE_TCCR0A:
+ .dw $ff06
+ .db "TCCR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0A
+XT_TCCR0A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0A:
+ .dw 68
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Mask Register
+VE_TIMSK0:
+ .dw $ff06
+ .db "TIMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK0
+XT_TIMSK0:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK0:
+ .dw 110
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Flag Register
+VE_TIFR0:
+ .dw $ff05
+ .db "TIFR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR0
+XT_TIFR0:
+ .dw PFA_DOVARIABLE
+PFA_TIFR0:
+ .dw 53
+; ( -- addr ) System Constant
+; R( -- )
+; General Timer/Counter Control Register
+VE_GTCCR:
+ .dw $ff05
+ .db "GTCCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GTCCR
+XT_GTCCR:
+ .dw PFA_DOVARIABLE
+PFA_GTCCR:
+ .dw 67
+
+.endif
+.if WANT_TIMER_COUNTER_2 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Mask register
+VE_TIMSK2:
+ .dw $ff06
+ .db "TIMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK2
+XT_TIMSK2:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK2:
+ .dw 112
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Flag Register
+VE_TIFR2:
+ .dw $ff05
+ .db "TIFR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR2
+XT_TIFR2:
+ .dw PFA_DOVARIABLE
+PFA_TIFR2:
+ .dw 55
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register A
+VE_TCCR2A:
+ .dw $ff06
+ .db "TCCR2A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2A
+XT_TCCR2A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2A:
+ .dw 176
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register B
+VE_TCCR2B:
+ .dw $ff06
+ .db "TCCR2B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2B
+XT_TCCR2B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2B:
+ .dw 177
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2
+VE_TCNT2:
+ .dw $ff05
+ .db "TCNT2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT2
+XT_TCNT2:
+ .dw PFA_DOVARIABLE
+PFA_TCNT2:
+ .dw 178
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register B
+VE_OCR2B:
+ .dw $ff05
+ .db "OCR2B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2B
+XT_OCR2B:
+ .dw PFA_DOVARIABLE
+PFA_OCR2B:
+ .dw 180
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register A
+VE_OCR2A:
+ .dw $ff05
+ .db "OCR2A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2A
+XT_OCR2A:
+ .dw PFA_DOVARIABLE
+PFA_OCR2A:
+ .dw 179
+; ( -- addr ) System Constant
+; R( -- )
+; Asynchronous Status Register
+VE_ASSR:
+ .dw $ff04
+ .db "ASSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ASSR
+XT_ASSR:
+ .dw PFA_DOVARIABLE
+PFA_ASSR:
+ .dw 182
+
+.endif
+.if WANT_WATCHDOG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCSR:
+ .dw $ff06
+ .db "WDTCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCSR
+XT_WDTCSR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCSR:
+ .dw 96
+
+.endif
+.if WANT_TIMER_COUNTER_5 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter5 Control Register A
+VE_TCCR5A:
+ .dw $ff06
+ .db "TCCR5A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR5A
+XT_TCCR5A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR5A:
+ .dw 288
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter5 Control Register B
+VE_TCCR5B:
+ .dw $ff06
+ .db "TCCR5B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR5B
+XT_TCCR5B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR5B:
+ .dw 289
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter5 Control Register C
+VE_TCCR5C:
+ .dw $ff06
+ .db "TCCR5C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR5C
+XT_TCCR5C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR5C:
+ .dw 290
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter5 Bytes
+VE_TCNT5:
+ .dw $ff05
+ .db "TCNT5",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT5
+XT_TCNT5:
+ .dw PFA_DOVARIABLE
+PFA_TCNT5:
+ .dw 292
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter5 Output Compare Register A Bytes
+VE_OCR5A:
+ .dw $ff05
+ .db "OCR5A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR5A
+XT_OCR5A:
+ .dw PFA_DOVARIABLE
+PFA_OCR5A:
+ .dw 296
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter5 Output Compare Register B Bytes
+VE_OCR5B:
+ .dw $ff05
+ .db "OCR5B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR5B
+XT_OCR5B:
+ .dw PFA_DOVARIABLE
+PFA_OCR5B:
+ .dw 298
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter5 Output Compare Register C Bytes
+VE_OCR5C:
+ .dw $ff05
+ .db "OCR5C",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR5C
+XT_OCR5C:
+ .dw PFA_DOVARIABLE
+PFA_OCR5C:
+ .dw 300
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter5 Input Capture Register Bytes
+VE_ICR5:
+ .dw $ff04
+ .db "ICR5"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR5
+XT_ICR5:
+ .dw PFA_DOVARIABLE
+PFA_ICR5:
+ .dw 294
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter5 Interrupt Mask Register
+VE_TIMSK5:
+ .dw $ff06
+ .db "TIMSK5"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK5
+XT_TIMSK5:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK5:
+ .dw 115
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter5 Interrupt Flag Register
+VE_TIFR5:
+ .dw $ff05
+ .db "TIFR5",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR5
+XT_TIFR5:
+ .dw PFA_DOVARIABLE
+PFA_TIFR5:
+ .dw 58
+
+.endif
+.if WANT_TIMER_COUNTER_4 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter4 Control Register A
+VE_TCCR4A:
+ .dw $ff06
+ .db "TCCR4A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR4A
+XT_TCCR4A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR4A:
+ .dw 160
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter4 Control Register B
+VE_TCCR4B:
+ .dw $ff06
+ .db "TCCR4B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR4B
+XT_TCCR4B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR4B:
+ .dw 161
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter4 Control Register C
+VE_TCCR4C:
+ .dw $ff06
+ .db "TCCR4C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR4C
+XT_TCCR4C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR4C:
+ .dw 162
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter4 Bytes
+VE_TCNT4:
+ .dw $ff05
+ .db "TCNT4",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT4
+XT_TCNT4:
+ .dw PFA_DOVARIABLE
+PFA_TCNT4:
+ .dw 164
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter4 Output Compare Register A Bytes
+VE_OCR4A:
+ .dw $ff05
+ .db "OCR4A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR4A
+XT_OCR4A:
+ .dw PFA_DOVARIABLE
+PFA_OCR4A:
+ .dw 168
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter4 Output Compare Register B Bytes
+VE_OCR4B:
+ .dw $ff05
+ .db "OCR4B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR4B
+XT_OCR4B:
+ .dw PFA_DOVARIABLE
+PFA_OCR4B:
+ .dw 170
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter4 Output Compare Register C Bytes
+VE_OCR4C:
+ .dw $ff05
+ .db "OCR4C",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR4C
+XT_OCR4C:
+ .dw PFA_DOVARIABLE
+PFA_OCR4C:
+ .dw 172
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter4 Input Capture Register Bytes
+VE_ICR4:
+ .dw $ff04
+ .db "ICR4"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR4
+XT_ICR4:
+ .dw PFA_DOVARIABLE
+PFA_ICR4:
+ .dw 166
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter4 Interrupt Mask Register
+VE_TIMSK4:
+ .dw $ff06
+ .db "TIMSK4"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK4
+XT_TIMSK4:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK4:
+ .dw 114
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter4 Interrupt Flag Register
+VE_TIFR4:
+ .dw $ff05
+ .db "TIFR4",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR4
+XT_TIFR4:
+ .dw PFA_DOVARIABLE
+PFA_TIFR4:
+ .dw 57
+
+.endif
+.if WANT_TIMER_COUNTER_3 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Control Register A
+VE_TCCR3A:
+ .dw $ff06
+ .db "TCCR3A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR3A
+XT_TCCR3A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR3A:
+ .dw 144
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Control Register B
+VE_TCCR3B:
+ .dw $ff06
+ .db "TCCR3B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR3B
+XT_TCCR3B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR3B:
+ .dw 145
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Control Register C
+VE_TCCR3C:
+ .dw $ff06
+ .db "TCCR3C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR3C
+XT_TCCR3C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR3C:
+ .dw 146
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Bytes
+VE_TCNT3:
+ .dw $ff05
+ .db "TCNT3",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT3
+XT_TCNT3:
+ .dw PFA_DOVARIABLE
+PFA_TCNT3:
+ .dw 148
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Output Compare Register A Bytes
+VE_OCR3A:
+ .dw $ff05
+ .db "OCR3A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR3A
+XT_OCR3A:
+ .dw PFA_DOVARIABLE
+PFA_OCR3A:
+ .dw 152
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Output Compare Register B Bytes
+VE_OCR3B:
+ .dw $ff05
+ .db "OCR3B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR3B
+XT_OCR3B:
+ .dw PFA_DOVARIABLE
+PFA_OCR3B:
+ .dw 154
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Output Compare Register C Bytes
+VE_OCR3C:
+ .dw $ff05
+ .db "OCR3C",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR3C
+XT_OCR3C:
+ .dw PFA_DOVARIABLE
+PFA_OCR3C:
+ .dw 156
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Input Capture Register Bytes
+VE_ICR3:
+ .dw $ff04
+ .db "ICR3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR3
+XT_ICR3:
+ .dw PFA_DOVARIABLE
+PFA_ICR3:
+ .dw 150
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Interrupt Mask Register
+VE_TIMSK3:
+ .dw $ff06
+ .db "TIMSK3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK3
+XT_TIMSK3:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK3:
+ .dw 113
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Interrupt Flag Register
+VE_TIFR3:
+ .dw $ff05
+ .db "TIFR3",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR3
+XT_TIFR3:
+ .dw PFA_DOVARIABLE
+PFA_TIFR3:
+ .dw 56
+
+.endif
+.if WANT_TIMER_COUNTER_1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw 128
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw 129
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register C
+VE_TCCR1C:
+ .dw $ff06
+ .db "TCCR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1C
+XT_TCCR1C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1C:
+ .dw 130
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Bytes
+VE_TCNT1:
+ .dw $ff05
+ .db "TCNT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1
+XT_TCNT1:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1:
+ .dw 132
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register A Bytes
+VE_OCR1A:
+ .dw $ff05
+ .db "OCR1A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1A
+XT_OCR1A:
+ .dw PFA_DOVARIABLE
+PFA_OCR1A:
+ .dw 136
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register B Bytes
+VE_OCR1B:
+ .dw $ff05
+ .db "OCR1B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1B
+XT_OCR1B:
+ .dw PFA_DOVARIABLE
+PFA_OCR1B:
+ .dw 138
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register C Bytes
+VE_OCR1C:
+ .dw $ff05
+ .db "OCR1C",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1C
+XT_OCR1C:
+ .dw PFA_DOVARIABLE
+PFA_OCR1C:
+ .dw 140
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Bytes
+VE_ICR1:
+ .dw $ff04
+ .db "ICR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1
+XT_ICR1:
+ .dw PFA_DOVARIABLE
+PFA_ICR1:
+ .dw 134
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Mask Register
+VE_TIMSK1:
+ .dw $ff06
+ .db "TIMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK1
+XT_TIMSK1:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK1:
+ .dw 111
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Flag Register
+VE_TIFR1:
+ .dw $ff05
+ .db "TIFR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR1
+XT_TIFR1:
+ .dw PFA_DOVARIABLE
+PFA_TIFR1:
+ .dw 54
+
+.endif
+.if WANT_TRX24 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; AES Control Register
+VE_AES_CTRL:
+ .dw $ff08
+ .db "AES_CTRL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_AES_CTRL
+XT_AES_CTRL:
+ .dw PFA_DOVARIABLE
+PFA_AES_CTRL:
+ .dw 316
+; ( -- addr ) System Constant
+; R( -- )
+; AES Status Register
+VE_AES_STATUS:
+ .dw $ff10
+ .db "AES_STATUS"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_AES_STATUS
+XT_AES_STATUS:
+ .dw PFA_DOVARIABLE
+PFA_AES_STATUS:
+ .dw 317
+; ( -- addr ) System Constant
+; R( -- )
+; AES Plain and Cipher Text Buffer Register
+VE_AES_STATE:
+ .dw $ff09
+ .db "AES_STATE",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_AES_STATE
+XT_AES_STATE:
+ .dw PFA_DOVARIABLE
+PFA_AES_STATE:
+ .dw 318
+; ( -- addr ) System Constant
+; R( -- )
+; AES Encryption and Decryption Key Buffer Register
+VE_AES_KEY:
+ .dw $ff07
+ .db "AES_KEY",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_AES_KEY
+XT_AES_KEY:
+ .dw PFA_DOVARIABLE
+PFA_AES_KEY:
+ .dw 319
+; ( -- addr ) System Constant
+; R( -- )
+; Transceiver Status Register
+VE_TRX_STATUS:
+ .dw $ff10
+ .db "TRX_STATUS"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TRX_STATUS
+XT_TRX_STATUS:
+ .dw PFA_DOVARIABLE
+PFA_TRX_STATUS:
+ .dw 321
+; ( -- addr ) System Constant
+; R( -- )
+; Transceiver State Control Register
+VE_TRX_STATE:
+ .dw $ff09
+ .db "TRX_STATE",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TRX_STATE
+XT_TRX_STATE:
+ .dw PFA_DOVARIABLE
+PFA_TRX_STATE:
+ .dw 322
+; ( -- addr ) System Constant
+; R( -- )
+; Reserved
+VE_TRX_CTRL_0:
+ .dw $ff10
+ .db "TRX_CTRL_0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TRX_CTRL_0
+XT_TRX_CTRL_0:
+ .dw PFA_DOVARIABLE
+PFA_TRX_CTRL_0:
+ .dw 323
+; ( -- addr ) System Constant
+; R( -- )
+; Transceiver Control Register 1
+VE_TRX_CTRL_1:
+ .dw $ff10
+ .db "TRX_CTRL_1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TRX_CTRL_1
+XT_TRX_CTRL_1:
+ .dw PFA_DOVARIABLE
+PFA_TRX_CTRL_1:
+ .dw 324
+; ( -- addr ) System Constant
+; R( -- )
+; Transceiver Transmit Power Control Register
+VE_PHY_TX_PWR:
+ .dw $ff10
+ .db "PHY_TX_PWR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PHY_TX_PWR
+XT_PHY_TX_PWR:
+ .dw PFA_DOVARIABLE
+PFA_PHY_TX_PWR:
+ .dw 325
+; ( -- addr ) System Constant
+; R( -- )
+; Receiver Signal Strength Indicator Register
+VE_PHY_RSSI:
+ .dw $ff08
+ .db "PHY_RSSI"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PHY_RSSI
+XT_PHY_RSSI:
+ .dw PFA_DOVARIABLE
+PFA_PHY_RSSI:
+ .dw 326
+; ( -- addr ) System Constant
+; R( -- )
+; Transceiver Energy Detection Level Register
+VE_PHY_ED_LEVEL:
+ .dw $ff12
+ .db "PHY_ED_LEVEL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PHY_ED_LEVEL
+XT_PHY_ED_LEVEL:
+ .dw PFA_DOVARIABLE
+PFA_PHY_ED_LEVEL:
+ .dw 327
+; ( -- addr ) System Constant
+; R( -- )
+; Transceiver Clear Channel Assessment (CCA) Control Register
+VE_PHY_CC_CCA:
+ .dw $ff10
+ .db "PHY_CC_CCA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PHY_CC_CCA
+XT_PHY_CC_CCA:
+ .dw PFA_DOVARIABLE
+PFA_PHY_CC_CCA:
+ .dw 328
+; ( -- addr ) System Constant
+; R( -- )
+; Transceiver CCA Threshold Setting Register
+VE_CCA_THRES:
+ .dw $ff09
+ .db "CCA_THRES",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CCA_THRES
+XT_CCA_THRES:
+ .dw PFA_DOVARIABLE
+PFA_CCA_THRES:
+ .dw 329
+; ( -- addr ) System Constant
+; R( -- )
+; Transceiver Receive Control Register
+VE_RX_CTRL:
+ .dw $ff07
+ .db "RX_CTRL",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_RX_CTRL
+XT_RX_CTRL:
+ .dw PFA_DOVARIABLE
+PFA_RX_CTRL:
+ .dw 330
+; ( -- addr ) System Constant
+; R( -- )
+; Start of Frame Delimiter Value Register
+VE_SFD_VALUE:
+ .dw $ff09
+ .db "SFD_VALUE",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SFD_VALUE
+XT_SFD_VALUE:
+ .dw PFA_DOVARIABLE
+PFA_SFD_VALUE:
+ .dw 331
+; ( -- addr ) System Constant
+; R( -- )
+; Transceiver Control Register 2
+VE_TRX_CTRL_2:
+ .dw $ff10
+ .db "TRX_CTRL_2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TRX_CTRL_2
+XT_TRX_CTRL_2:
+ .dw PFA_DOVARIABLE
+PFA_TRX_CTRL_2:
+ .dw 332
+; ( -- addr ) System Constant
+; R( -- )
+; Antenna Diversity Control Register
+VE_ANT_DIV:
+ .dw $ff07
+ .db "ANT_DIV",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ANT_DIV
+XT_ANT_DIV:
+ .dw PFA_DOVARIABLE
+PFA_ANT_DIV:
+ .dw 333
+; ( -- addr ) System Constant
+; R( -- )
+; Transceiver Interrupt Enable Register
+VE_IRQ_MASK:
+ .dw $ff08
+ .db "IRQ_MASK"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_IRQ_MASK
+XT_IRQ_MASK:
+ .dw PFA_DOVARIABLE
+PFA_IRQ_MASK:
+ .dw 334
+; ( -- addr ) System Constant
+; R( -- )
+; Transceiver Interrupt Status Register
+VE_IRQ_STATUS:
+ .dw $ff10
+ .db "IRQ_STATUS"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_IRQ_STATUS
+XT_IRQ_STATUS:
+ .dw PFA_DOVARIABLE
+PFA_IRQ_STATUS:
+ .dw 335
+; ( -- addr ) System Constant
+; R( -- )
+; Voltage Regulator Control and Status Register
+VE_VREG_CTRL:
+ .dw $ff09
+ .db "VREG_CTRL",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_VREG_CTRL
+XT_VREG_CTRL:
+ .dw PFA_DOVARIABLE
+PFA_VREG_CTRL:
+ .dw 336
+; ( -- addr ) System Constant
+; R( -- )
+; Battery Monitor Control and Status Register
+VE_BATMON:
+ .dw $ff06
+ .db "BATMON"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_BATMON
+XT_BATMON:
+ .dw PFA_DOVARIABLE
+PFA_BATMON:
+ .dw 337
+; ( -- addr ) System Constant
+; R( -- )
+; Crystal Oscillator Control Register
+VE_XOSC_CTRL:
+ .dw $ff09
+ .db "XOSC_CTRL",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_XOSC_CTRL
+XT_XOSC_CTRL:
+ .dw PFA_DOVARIABLE
+PFA_XOSC_CTRL:
+ .dw 338
+; ( -- addr ) System Constant
+; R( -- )
+; Transceiver Receiver Sensitivity Control Register
+VE_RX_SYN:
+ .dw $ff06
+ .db "RX_SYN"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_RX_SYN
+XT_RX_SYN:
+ .dw PFA_DOVARIABLE
+PFA_RX_SYN:
+ .dw 341
+; ( -- addr ) System Constant
+; R( -- )
+; Transceiver Acknowledgment Frame Control Register 1
+VE_XAH_CTRL_1:
+ .dw $ff10
+ .db "XAH_CTRL_1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_XAH_CTRL_1
+XT_XAH_CTRL_1:
+ .dw PFA_DOVARIABLE
+PFA_XAH_CTRL_1:
+ .dw 343
+; ( -- addr ) System Constant
+; R( -- )
+; Transceiver Filter Tuning Control Register
+VE_FTN_CTRL:
+ .dw $ff08
+ .db "FTN_CTRL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_FTN_CTRL
+XT_FTN_CTRL:
+ .dw PFA_DOVARIABLE
+PFA_FTN_CTRL:
+ .dw 344
+; ( -- addr ) System Constant
+; R( -- )
+; Transceiver Center Frequency Calibration Control Register
+VE_PLL_CF:
+ .dw $ff06
+ .db "PLL_CF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PLL_CF
+XT_PLL_CF:
+ .dw PFA_DOVARIABLE
+PFA_PLL_CF:
+ .dw 346
+; ( -- addr ) System Constant
+; R( -- )
+; Transceiver Delay Cell Calibration Control Register
+VE_PLL_DCU:
+ .dw $ff07
+ .db "PLL_DCU",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PLL_DCU
+XT_PLL_DCU:
+ .dw PFA_DOVARIABLE
+PFA_PLL_DCU:
+ .dw 347
+; ( -- addr ) System Constant
+; R( -- )
+; Device Identification Register (Part Number)
+VE_PART_NUM:
+ .dw $ff08
+ .db "PART_NUM"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PART_NUM
+XT_PART_NUM:
+ .dw PFA_DOVARIABLE
+PFA_PART_NUM:
+ .dw 348
+; ( -- addr ) System Constant
+; R( -- )
+; Device Identification Register (Version Number)
+VE_VERSION_NUM:
+ .dw $ff11
+ .db "VERSION_NUM",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_VERSION_NUM
+XT_VERSION_NUM:
+ .dw PFA_DOVARIABLE
+PFA_VERSION_NUM:
+ .dw 349
+; ( -- addr ) System Constant
+; R( -- )
+; Device Identification Register (Manufacture ID Low Byte)
+VE_MAN_ID_0:
+ .dw $ff08
+ .db "MAN_ID_0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MAN_ID_0
+XT_MAN_ID_0:
+ .dw PFA_DOVARIABLE
+PFA_MAN_ID_0:
+ .dw 350
+; ( -- addr ) System Constant
+; R( -- )
+; Device Identification Register (Manufacture ID High Byte)
+VE_MAN_ID_1:
+ .dw $ff08
+ .db "MAN_ID_1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MAN_ID_1
+XT_MAN_ID_1:
+ .dw PFA_DOVARIABLE
+PFA_MAN_ID_1:
+ .dw 351
+; ( -- addr ) System Constant
+; R( -- )
+; Transceiver MAC Short Address Register (Low Byte)
+VE_SHORT_ADDR_0:
+ .dw $ff12
+ .db "SHORT_ADDR_0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SHORT_ADDR_0
+XT_SHORT_ADDR_0:
+ .dw PFA_DOVARIABLE
+PFA_SHORT_ADDR_0:
+ .dw 352
+; ( -- addr ) System Constant
+; R( -- )
+; Transceiver MAC Short Address Register (High Byte)
+VE_SHORT_ADDR_1:
+ .dw $ff12
+ .db "SHORT_ADDR_1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SHORT_ADDR_1
+XT_SHORT_ADDR_1:
+ .dw PFA_DOVARIABLE
+PFA_SHORT_ADDR_1:
+ .dw 353
+; ( -- addr ) System Constant
+; R( -- )
+; Transceiver Personal Area Network ID Register (Low Byte)
+VE_PAN_ID_0:
+ .dw $ff08
+ .db "PAN_ID_0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PAN_ID_0
+XT_PAN_ID_0:
+ .dw PFA_DOVARIABLE
+PFA_PAN_ID_0:
+ .dw 354
+; ( -- addr ) System Constant
+; R( -- )
+; Transceiver Personal Area Network ID Register (High Byte)
+VE_PAN_ID_1:
+ .dw $ff08
+ .db "PAN_ID_1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PAN_ID_1
+XT_PAN_ID_1:
+ .dw PFA_DOVARIABLE
+PFA_PAN_ID_1:
+ .dw 355
+; ( -- addr ) System Constant
+; R( -- )
+; Transceiver MAC IEEE Address Register 0
+VE_IEEE_ADDR_0:
+ .dw $ff11
+ .db "IEEE_ADDR_0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_IEEE_ADDR_0
+XT_IEEE_ADDR_0:
+ .dw PFA_DOVARIABLE
+PFA_IEEE_ADDR_0:
+ .dw 356
+; ( -- addr ) System Constant
+; R( -- )
+; Transceiver MAC IEEE Address Register 1
+VE_IEEE_ADDR_1:
+ .dw $ff11
+ .db "IEEE_ADDR_1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_IEEE_ADDR_1
+XT_IEEE_ADDR_1:
+ .dw PFA_DOVARIABLE
+PFA_IEEE_ADDR_1:
+ .dw 357
+; ( -- addr ) System Constant
+; R( -- )
+; Transceiver MAC IEEE Address Register 2
+VE_IEEE_ADDR_2:
+ .dw $ff11
+ .db "IEEE_ADDR_2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_IEEE_ADDR_2
+XT_IEEE_ADDR_2:
+ .dw PFA_DOVARIABLE
+PFA_IEEE_ADDR_2:
+ .dw 358
+; ( -- addr ) System Constant
+; R( -- )
+; Transceiver MAC IEEE Address Register 3
+VE_IEEE_ADDR_3:
+ .dw $ff11
+ .db "IEEE_ADDR_3",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_IEEE_ADDR_3
+XT_IEEE_ADDR_3:
+ .dw PFA_DOVARIABLE
+PFA_IEEE_ADDR_3:
+ .dw 359
+; ( -- addr ) System Constant
+; R( -- )
+; Transceiver MAC IEEE Address Register 4
+VE_IEEE_ADDR_4:
+ .dw $ff11
+ .db "IEEE_ADDR_4",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_IEEE_ADDR_4
+XT_IEEE_ADDR_4:
+ .dw PFA_DOVARIABLE
+PFA_IEEE_ADDR_4:
+ .dw 360
+; ( -- addr ) System Constant
+; R( -- )
+; Transceiver MAC IEEE Address Register 5
+VE_IEEE_ADDR_5:
+ .dw $ff11
+ .db "IEEE_ADDR_5",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_IEEE_ADDR_5
+XT_IEEE_ADDR_5:
+ .dw PFA_DOVARIABLE
+PFA_IEEE_ADDR_5:
+ .dw 361
+; ( -- addr ) System Constant
+; R( -- )
+; Transceiver MAC IEEE Address Register 6
+VE_IEEE_ADDR_6:
+ .dw $ff11
+ .db "IEEE_ADDR_6",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_IEEE_ADDR_6
+XT_IEEE_ADDR_6:
+ .dw PFA_DOVARIABLE
+PFA_IEEE_ADDR_6:
+ .dw 362
+; ( -- addr ) System Constant
+; R( -- )
+; Transceiver MAC IEEE Address Register 7
+VE_IEEE_ADDR_7:
+ .dw $ff11
+ .db "IEEE_ADDR_7",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_IEEE_ADDR_7
+XT_IEEE_ADDR_7:
+ .dw PFA_DOVARIABLE
+PFA_IEEE_ADDR_7:
+ .dw 363
+; ( -- addr ) System Constant
+; R( -- )
+; Transceiver Extended Operating Mode Control Register
+VE_XAH_CTRL_0:
+ .dw $ff10
+ .db "XAH_CTRL_0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_XAH_CTRL_0
+XT_XAH_CTRL_0:
+ .dw PFA_DOVARIABLE
+PFA_XAH_CTRL_0:
+ .dw 364
+; ( -- addr ) System Constant
+; R( -- )
+; Transceiver CSMA-CA Random Number Generator Seed Register
+VE_CSMA_SEED_0:
+ .dw $ff11
+ .db "CSMA_SEED_0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CSMA_SEED_0
+XT_CSMA_SEED_0:
+ .dw PFA_DOVARIABLE
+PFA_CSMA_SEED_0:
+ .dw 365
+; ( -- addr ) System Constant
+; R( -- )
+; Transceiver Acknowledgment Frame Control Register 2
+VE_CSMA_SEED_1:
+ .dw $ff11
+ .db "CSMA_SEED_1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CSMA_SEED_1
+XT_CSMA_SEED_1:
+ .dw PFA_DOVARIABLE
+PFA_CSMA_SEED_1:
+ .dw 366
+; ( -- addr ) System Constant
+; R( -- )
+; Transceiver CSMA-CA Back-off Exponent Control Register
+VE_CSMA_BE:
+ .dw $ff07
+ .db "CSMA_BE",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CSMA_BE
+XT_CSMA_BE:
+ .dw PFA_DOVARIABLE
+PFA_CSMA_BE:
+ .dw 367
+; ( -- addr ) System Constant
+; R( -- )
+; Transceiver Digital Test Control Register
+VE_TST_CTRL_DIGI:
+ .dw $ff13
+ .db "TST_CTRL_DIGI",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TST_CTRL_DIGI
+XT_TST_CTRL_DIGI:
+ .dw PFA_DOVARIABLE
+PFA_TST_CTRL_DIGI:
+ .dw 374
+; ( -- addr ) System Constant
+; R( -- )
+; Transceiver Received Frame Length Register
+VE_TST_RX_LENGTH:
+ .dw $ff13
+ .db "TST_RX_LENGTH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TST_RX_LENGTH
+XT_TST_RX_LENGTH:
+ .dw PFA_DOVARIABLE
+PFA_TST_RX_LENGTH:
+ .dw 379
+; ( -- addr ) System Constant
+; R( -- )
+; Start of frame buffer
+VE_TRXFBST:
+ .dw $ff07
+ .db "TRXFBST",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TRXFBST
+XT_TRXFBST:
+ .dw PFA_DOVARIABLE
+PFA_TRXFBST:
+ .dw 384
+; ( -- addr ) System Constant
+; R( -- )
+; End of frame buffer
+VE_TRXFBEND:
+ .dw $ff08
+ .db "TRXFBEND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TRXFBEND
+XT_TRXFBEND:
+ .dw PFA_DOVARIABLE
+PFA_TRXFBEND:
+ .dw 511
+
+.endif
+.if WANT_SYMCNT == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Symbol Counter Output Compare Register 1 HH-Byte
+VE_SCOCR1HH:
+ .dw $ff08
+ .db "SCOCR1HH"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SCOCR1HH
+XT_SCOCR1HH:
+ .dw PFA_DOVARIABLE
+PFA_SCOCR1HH:
+ .dw 248
+; ( -- addr ) System Constant
+; R( -- )
+; Symbol Counter Output Compare Register 1 HL-Byte
+VE_SCOCR1HL:
+ .dw $ff08
+ .db "SCOCR1HL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SCOCR1HL
+XT_SCOCR1HL:
+ .dw PFA_DOVARIABLE
+PFA_SCOCR1HL:
+ .dw 247
+; ( -- addr ) System Constant
+; R( -- )
+; Symbol Counter Output Compare Register 1 LH-Byte
+VE_SCOCR1LH:
+ .dw $ff08
+ .db "SCOCR1LH"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SCOCR1LH
+XT_SCOCR1LH:
+ .dw PFA_DOVARIABLE
+PFA_SCOCR1LH:
+ .dw 246
+; ( -- addr ) System Constant
+; R( -- )
+; Symbol Counter Output Compare Register 1 LL-Byte
+VE_SCOCR1LL:
+ .dw $ff08
+ .db "SCOCR1LL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SCOCR1LL
+XT_SCOCR1LL:
+ .dw PFA_DOVARIABLE
+PFA_SCOCR1LL:
+ .dw 245
+; ( -- addr ) System Constant
+; R( -- )
+; Symbol Counter Output Compare Register 2 HH-Byte
+VE_SCOCR2HH:
+ .dw $ff08
+ .db "SCOCR2HH"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SCOCR2HH
+XT_SCOCR2HH:
+ .dw PFA_DOVARIABLE
+PFA_SCOCR2HH:
+ .dw 244
+; ( -- addr ) System Constant
+; R( -- )
+; Symbol Counter Output Compare Register 2 HL-Byte
+VE_SCOCR2HL:
+ .dw $ff08
+ .db "SCOCR2HL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SCOCR2HL
+XT_SCOCR2HL:
+ .dw PFA_DOVARIABLE
+PFA_SCOCR2HL:
+ .dw 243
+; ( -- addr ) System Constant
+; R( -- )
+; Symbol Counter Output Compare Register 2 LH-Byte
+VE_SCOCR2LH:
+ .dw $ff08
+ .db "SCOCR2LH"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SCOCR2LH
+XT_SCOCR2LH:
+ .dw PFA_DOVARIABLE
+PFA_SCOCR2LH:
+ .dw 242
+; ( -- addr ) System Constant
+; R( -- )
+; Symbol Counter Output Compare Register 2 LL-Byte
+VE_SCOCR2LL:
+ .dw $ff08
+ .db "SCOCR2LL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SCOCR2LL
+XT_SCOCR2LL:
+ .dw PFA_DOVARIABLE
+PFA_SCOCR2LL:
+ .dw 241
+; ( -- addr ) System Constant
+; R( -- )
+; Symbol Counter Output Compare Register 3 HH-Byte
+VE_SCOCR3HH:
+ .dw $ff08
+ .db "SCOCR3HH"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SCOCR3HH
+XT_SCOCR3HH:
+ .dw PFA_DOVARIABLE
+PFA_SCOCR3HH:
+ .dw 240
+; ( -- addr ) System Constant
+; R( -- )
+; Symbol Counter Output Compare Register 3 HL-Byte
+VE_SCOCR3HL:
+ .dw $ff08
+ .db "SCOCR3HL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SCOCR3HL
+XT_SCOCR3HL:
+ .dw PFA_DOVARIABLE
+PFA_SCOCR3HL:
+ .dw 239
+; ( -- addr ) System Constant
+; R( -- )
+; Symbol Counter Output Compare Register 3 LH-Byte
+VE_SCOCR3LH:
+ .dw $ff08
+ .db "SCOCR3LH"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SCOCR3LH
+XT_SCOCR3LH:
+ .dw PFA_DOVARIABLE
+PFA_SCOCR3LH:
+ .dw 238
+; ( -- addr ) System Constant
+; R( -- )
+; Symbol Counter Output Compare Register 3 LL-Byte
+VE_SCOCR3LL:
+ .dw $ff08
+ .db "SCOCR3LL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SCOCR3LL
+XT_SCOCR3LL:
+ .dw PFA_DOVARIABLE
+PFA_SCOCR3LL:
+ .dw 237
+; ( -- addr ) System Constant
+; R( -- )
+; Symbol Counter Frame Timestamp Register HH-Byte
+VE_SCTSRHH:
+ .dw $ff07
+ .db "SCTSRHH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SCTSRHH
+XT_SCTSRHH:
+ .dw PFA_DOVARIABLE
+PFA_SCTSRHH:
+ .dw 236
+; ( -- addr ) System Constant
+; R( -- )
+; Symbol Counter Frame Timestamp Register HL-Byte
+VE_SCTSRHL:
+ .dw $ff07
+ .db "SCTSRHL",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SCTSRHL
+XT_SCTSRHL:
+ .dw PFA_DOVARIABLE
+PFA_SCTSRHL:
+ .dw 235
+; ( -- addr ) System Constant
+; R( -- )
+; Symbol Counter Frame Timestamp Register LH-Byte
+VE_SCTSRLH:
+ .dw $ff07
+ .db "SCTSRLH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SCTSRLH
+XT_SCTSRLH:
+ .dw PFA_DOVARIABLE
+PFA_SCTSRLH:
+ .dw 234
+; ( -- addr ) System Constant
+; R( -- )
+; Symbol Counter Frame Timestamp Register LL-Byte
+VE_SCTSRLL:
+ .dw $ff07
+ .db "SCTSRLL",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SCTSRLL
+XT_SCTSRLL:
+ .dw PFA_DOVARIABLE
+PFA_SCTSRLL:
+ .dw 233
+; ( -- addr ) System Constant
+; R( -- )
+; Symbol Counter Beacon Timestamp Register HH-Byte
+VE_SCBTSRHH:
+ .dw $ff08
+ .db "SCBTSRHH"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SCBTSRHH
+XT_SCBTSRHH:
+ .dw PFA_DOVARIABLE
+PFA_SCBTSRHH:
+ .dw 232
+; ( -- addr ) System Constant
+; R( -- )
+; Symbol Counter Beacon Timestamp Register HL-Byte
+VE_SCBTSRHL:
+ .dw $ff08
+ .db "SCBTSRHL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SCBTSRHL
+XT_SCBTSRHL:
+ .dw PFA_DOVARIABLE
+PFA_SCBTSRHL:
+ .dw 231
+; ( -- addr ) System Constant
+; R( -- )
+; Symbol Counter Beacon Timestamp Register LH-Byte
+VE_SCBTSRLH:
+ .dw $ff08
+ .db "SCBTSRLH"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SCBTSRLH
+XT_SCBTSRLH:
+ .dw PFA_DOVARIABLE
+PFA_SCBTSRLH:
+ .dw 230
+; ( -- addr ) System Constant
+; R( -- )
+; Symbol Counter Beacon Timestamp Register LL-Byte
+VE_SCBTSRLL:
+ .dw $ff08
+ .db "SCBTSRLL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SCBTSRLL
+XT_SCBTSRLL:
+ .dw PFA_DOVARIABLE
+PFA_SCBTSRLL:
+ .dw 229
+; ( -- addr ) System Constant
+; R( -- )
+; Symbol Counter Register HH-Byte
+VE_SCCNTHH:
+ .dw $ff07
+ .db "SCCNTHH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SCCNTHH
+XT_SCCNTHH:
+ .dw PFA_DOVARIABLE
+PFA_SCCNTHH:
+ .dw 228
+; ( -- addr ) System Constant
+; R( -- )
+; Symbol Counter Register HL-Byte
+VE_SCCNTHL:
+ .dw $ff07
+ .db "SCCNTHL",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SCCNTHL
+XT_SCCNTHL:
+ .dw PFA_DOVARIABLE
+PFA_SCCNTHL:
+ .dw 227
+; ( -- addr ) System Constant
+; R( -- )
+; Symbol Counter Register LH-Byte
+VE_SCCNTLH:
+ .dw $ff07
+ .db "SCCNTLH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SCCNTLH
+XT_SCCNTLH:
+ .dw PFA_DOVARIABLE
+PFA_SCCNTLH:
+ .dw 226
+; ( -- addr ) System Constant
+; R( -- )
+; Symbol Counter Register LL-Byte
+VE_SCCNTLL:
+ .dw $ff07
+ .db "SCCNTLL",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SCCNTLL
+XT_SCCNTLL:
+ .dw PFA_DOVARIABLE
+PFA_SCCNTLL:
+ .dw 225
+; ( -- addr ) System Constant
+; R( -- )
+; Symbol Counter Interrupt Status Register
+VE_SCIRQS:
+ .dw $ff06
+ .db "SCIRQS"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SCIRQS
+XT_SCIRQS:
+ .dw PFA_DOVARIABLE
+PFA_SCIRQS:
+ .dw 224
+; ( -- addr ) System Constant
+; R( -- )
+; Symbol Counter Interrupt Mask Register
+VE_SCIRQM:
+ .dw $ff06
+ .db "SCIRQM"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SCIRQM
+XT_SCIRQM:
+ .dw PFA_DOVARIABLE
+PFA_SCIRQM:
+ .dw 223
+; ( -- addr ) System Constant
+; R( -- )
+; Symbol Counter Status Register
+VE_SCSR:
+ .dw $ff04
+ .db "SCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SCSR
+XT_SCSR:
+ .dw PFA_DOVARIABLE
+PFA_SCSR:
+ .dw 222
+; ( -- addr ) System Constant
+; R( -- )
+; Symbol Counter Control Register 1
+VE_SCCR1:
+ .dw $ff05
+ .db "SCCR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SCCR1
+XT_SCCR1:
+ .dw PFA_DOVARIABLE
+PFA_SCCR1:
+ .dw 221
+; ( -- addr ) System Constant
+; R( -- )
+; Symbol Counter Control Register 0
+VE_SCCR0:
+ .dw $ff05
+ .db "SCCR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SCCR0
+XT_SCCR0:
+ .dw PFA_DOVARIABLE
+PFA_SCCR0:
+ .dw 220
+
+.endif
+.if WANT_EEPROM == 1
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Address Register Bytes
+VE_EEAR:
+ .dw $ff04
+ .db "EEAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEAR
+XT_EEAR:
+ .dw PFA_DOVARIABLE
+PFA_EEAR:
+ .dw 65
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw 64
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw 63
+
+.endif
+.if WANT_JTAG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; On-Chip Debug Register
+VE_OCDR:
+ .dw $ff04
+ .db "OCDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCDR
+XT_OCDR:
+ .dw PFA_DOVARIABLE
+PFA_OCDR:
+ .dw 81
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw 85
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Status Register
+VE_MCUSR:
+ .dw $ff05
+ .db "MCUSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUSR
+XT_MCUSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUSR:
+ .dw 84
+
+.endif
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register A
+VE_EICRA:
+ .dw $ff05
+ .db "EICRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRA
+XT_EICRA:
+ .dw PFA_DOVARIABLE
+PFA_EICRA:
+ .dw 105
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register B
+VE_EICRB:
+ .dw $ff05
+ .db "EICRB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRB
+XT_EICRB:
+ .dw PFA_DOVARIABLE
+PFA_EICRB:
+ .dw 106
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Mask Register
+VE_EIMSK:
+ .dw $ff05
+ .db "EIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIMSK
+XT_EIMSK:
+ .dw PFA_DOVARIABLE
+PFA_EIMSK:
+ .dw 61
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Flag Register
+VE_EIFR:
+ .dw $ff04
+ .db "EIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIFR
+XT_EIFR:
+ .dw PFA_DOVARIABLE
+PFA_EIFR:
+ .dw 60
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 2
+VE_PCMSK2:
+ .dw $ff06
+ .db "PCMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK2
+XT_PCMSK2:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK2:
+ .dw 109
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 1
+VE_PCMSK1:
+ .dw $ff06
+ .db "PCMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK1
+XT_PCMSK1:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK1:
+ .dw 108
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 0
+VE_PCMSK0:
+ .dw $ff06
+ .db "PCMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK0
+XT_PCMSK0:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK0:
+ .dw 107
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Interrupt Flag Register
+VE_PCIFR:
+ .dw $ff05
+ .db "PCIFR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCIFR
+XT_PCIFR:
+ .dw PFA_DOVARIABLE
+PFA_PCIFR:
+ .dw 59
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Interrupt Control Register
+VE_PCICR:
+ .dw $ff05
+ .db "PCICR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCICR
+XT_PCICR:
+ .dw PFA_DOVARIABLE
+PFA_PCICR:
+ .dw 104
+
+.endif
+.if WANT_AD_CONVERTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Multiplexer Selection Register
+VE_ADMUX:
+ .dw $ff05
+ .db "ADMUX",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADMUX
+XT_ADMUX:
+ .dw PFA_DOVARIABLE
+PFA_ADMUX:
+ .dw 124
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register Bytes
+VE_ADC:
+ .dw $ff03
+ .db "ADC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADC
+XT_ADC:
+ .dw PFA_DOVARIABLE
+PFA_ADC:
+ .dw 120
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status Register A
+VE_ADCSRA:
+ .dw $ff06
+ .db "ADCSRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRA
+XT_ADCSRA:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRA:
+ .dw 122
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status Register C
+VE_ADCSRC:
+ .dw $ff06
+ .db "ADCSRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRC
+XT_ADCSRC:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRC:
+ .dw 119
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 2
+VE_DIDR2:
+ .dw $ff05
+ .db "DIDR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR2
+XT_DIDR2:
+ .dw PFA_DOVARIABLE
+PFA_DIDR2:
+ .dw 125
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 0
+VE_DIDR0:
+ .dw $ff05
+ .db "DIDR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR0
+XT_DIDR0:
+ .dw PFA_DOVARIABLE
+PFA_DIDR0:
+ .dw 126
+
+.endif
+.if WANT_BOOT_LOAD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control Register
+VE_SPMCSR:
+ .dw $ff06
+ .db "SPMCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCSR
+XT_SPMCSR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCSR:
+ .dw 87
+
+.endif
+.if WANT_CPU == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw 95
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer
+VE_SP:
+ .dw $ff02
+ .db "SP"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SP
+XT_SP:
+ .dw PFA_DOVARIABLE
+PFA_SP:
+ .dw 93
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Calibration Value
+VE_OSCCAL:
+ .dw $ff06
+ .db "OSCCAL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSCCAL
+XT_OSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_OSCCAL:
+ .dw 102
+; ( -- addr ) System Constant
+; R( -- )
+; Clock Prescale Register
+VE_CLKPR:
+ .dw $ff05
+ .db "CLKPR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKPR
+XT_CLKPR:
+ .dw PFA_DOVARIABLE
+PFA_CLKPR:
+ .dw 97
+; ( -- addr ) System Constant
+; R( -- )
+; Sleep Mode Control Register
+VE_SMCR:
+ .dw $ff04
+ .db "SMCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SMCR
+XT_SMCR:
+ .dw PFA_DOVARIABLE
+PFA_SMCR:
+ .dw 83
+; ( -- addr ) System Constant
+; R( -- )
+; Extended Z-pointer Register for ELPM/SPM
+VE_RAMPZ:
+ .dw $ff05
+ .db "RAMPZ",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_RAMPZ
+XT_RAMPZ:
+ .dw PFA_DOVARIABLE
+PFA_RAMPZ:
+ .dw 91
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose I/O Register 2
+VE_GPIOR2:
+ .dw $ff06
+ .db "GPIOR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR2
+XT_GPIOR2:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR2:
+ .dw 75
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 1
+VE_GPIOR1:
+ .dw $ff06
+ .db "GPIOR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR1
+XT_GPIOR1:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR1:
+ .dw 74
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 0
+VE_GPIOR0:
+ .dw $ff06
+ .db "GPIOR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR0
+XT_GPIOR0:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR0:
+ .dw 62
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register 2
+VE_PRR2:
+ .dw $ff04
+ .db "PRR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR2
+XT_PRR2:
+ .dw PFA_DOVARIABLE
+PFA_PRR2:
+ .dw 99
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register 1
+VE_PRR1:
+ .dw $ff04
+ .db "PRR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR1
+XT_PRR1:
+ .dw PFA_DOVARIABLE
+PFA_PRR1:
+ .dw 101
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register0
+VE_PRR0:
+ .dw $ff04
+ .db "PRR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR0
+XT_PRR0:
+ .dw PFA_DOVARIABLE
+PFA_PRR0:
+ .dw 100
+
+.endif
+.if WANT_FLASH == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Flash Extended-Mode Control-Register
+VE_NEMCR:
+ .dw $ff05
+ .db "NEMCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_NEMCR
+XT_NEMCR:
+ .dw PFA_DOVARIABLE
+PFA_NEMCR:
+ .dw 117
+; ( -- addr ) System Constant
+; R( -- )
+; Reference Voltage Calibration Register
+VE_BGCR:
+ .dw $ff04
+ .db "BGCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_BGCR
+XT_BGCR:
+ .dw PFA_DOVARIABLE
+PFA_BGCR:
+ .dw 103
+
+.endif
+.if WANT_PWRCTRL == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Transceiver Pin Register
+VE_TRXPR:
+ .dw $ff05
+ .db "TRXPR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TRXPR
+XT_TRXPR:
+ .dw PFA_DOVARIABLE
+PFA_TRXPR:
+ .dw 313
+; ( -- addr ) System Constant
+; R( -- )
+; Data Retention Configuration Register of SRAM 0
+VE_DRTRAM0:
+ .dw $ff07
+ .db "DRTRAM0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DRTRAM0
+XT_DRTRAM0:
+ .dw PFA_DOVARIABLE
+PFA_DRTRAM0:
+ .dw 309
+; ( -- addr ) System Constant
+; R( -- )
+; Data Retention Configuration Register of SRAM 1
+VE_DRTRAM1:
+ .dw $ff07
+ .db "DRTRAM1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DRTRAM1
+XT_DRTRAM1:
+ .dw PFA_DOVARIABLE
+PFA_DRTRAM1:
+ .dw 308
+; ( -- addr ) System Constant
+; R( -- )
+; Data Retention Configuration Register of SRAM 2
+VE_DRTRAM2:
+ .dw $ff07
+ .db "DRTRAM2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DRTRAM2
+XT_DRTRAM2:
+ .dw PFA_DOVARIABLE
+PFA_DRTRAM2:
+ .dw 307
+; ( -- addr ) System Constant
+; R( -- )
+; Data Retention Configuration Register of SRAM 3
+VE_DRTRAM3:
+ .dw $ff07
+ .db "DRTRAM3",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DRTRAM3
+XT_DRTRAM3:
+ .dw PFA_DOVARIABLE
+PFA_DRTRAM3:
+ .dw 306
+; ( -- addr ) System Constant
+; R( -- )
+; Low Leakage Voltage Regulator Data Register (Low-Byte)
+VE_LLDRL:
+ .dw $ff05
+ .db "LLDRL",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LLDRL
+XT_LLDRL:
+ .dw PFA_DOVARIABLE
+PFA_LLDRL:
+ .dw 304
+; ( -- addr ) System Constant
+; R( -- )
+; Low Leakage Voltage Regulator Data Register (High-Byte)
+VE_LLDRH:
+ .dw $ff05
+ .db "LLDRH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LLDRH
+XT_LLDRH:
+ .dw PFA_DOVARIABLE
+PFA_LLDRH:
+ .dw 305
+; ( -- addr ) System Constant
+; R( -- )
+; Low Leakage Voltage Regulator Control Register
+VE_LLCR:
+ .dw $ff04
+ .db "LLCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LLCR
+XT_LLCR:
+ .dw PFA_DOVARIABLE
+PFA_LLCR:
+ .dw 303
+; ( -- addr ) System Constant
+; R( -- )
+; Port Driver Strength Register 0
+VE_DPDS0:
+ .dw $ff05
+ .db "DPDS0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DPDS0
+XT_DPDS0:
+ .dw PFA_DOVARIABLE
+PFA_DPDS0:
+ .dw 310
+; ( -- addr ) System Constant
+; R( -- )
+; Port Driver Strength Register 1
+VE_DPDS1:
+ .dw $ff05
+ .db "DPDS1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DPDS1
+XT_DPDS1:
+ .dw PFA_DOVARIABLE
+PFA_DPDS1:
+ .dw 311
+
+.endif
+.if WANT_USART0_SPI == 1
+
+.endif
+.if WANT_USART1_SPI == 1
+
+.endif
diff --git a/amforth-6.5/avr8/devices/atmega128rfa1/device.py b/amforth-6.5/avr8/devices/atmega128rfa1/device.py
new file mode 100644
index 0000000..3e24dfa
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega128rfa1/device.py
@@ -0,0 +1,991 @@
+# Generated Automatically
+
+# Partname ATmega128RFA1
+
+MCUREGS = {
+# Interrupt Vectors
+ 'INT0Addr' : '#2', # External Interrupt Request 0
+ 'INT1Addr' : '#4', # External Interrupt Request 1
+ 'INT2Addr' : '#6', # External Interrupt Request 2
+ 'INT3Addr' : '#8', # External Interrupt Request 3
+ 'INT4Addr' : '#10', # External Interrupt Request 4
+ 'INT5Addr' : '#12', # External Interrupt Request 5
+ 'INT6Addr' : '#14', # External Interrupt Request 6
+ 'INT7Addr' : '#16', # External Interrupt Request 7
+ 'PCINT0Addr' : '#18', # Pin Change Interrupt Request 0
+ 'PCINT1Addr' : '#20', # Pin Change Interrupt Request 1
+ 'PCINT2Addr' : '#22', # Pin Change Interrupt Request 2
+ 'WDTAddr' : '#24', # Watchdog Time-out Interrupt
+ 'TIMER2_COMPAAddr' : '#26', # Timer/Counter2 Compare Match A
+ 'TIMER2_COMPBAddr' : '#28', # Timer/Counter2 Compare Match B
+ 'TIMER2_OVFAddr' : '#30', # Timer/Counter2 Overflow
+ 'TIMER1_CAPTAddr' : '#32', # Timer/Counter1 Capture Event
+ 'TIMER1_COMPAAddr' : '#34', # Timer/Counter1 Compare Match A
+ 'TIMER1_COMPBAddr' : '#36', # Timer/Counter1 Compare Match B
+ 'TIMER1_COMPCAddr' : '#38', # Timer/Counter1 Compare Match C
+ 'TIMER1_OVFAddr' : '#40', # Timer/Counter1 Overflow
+ 'TIMER0_COMPAAddr' : '#42', # Timer/Counter0 Compare Match A
+ 'TIMER0_COMPBAddr' : '#44', # Timer/Counter0 Compare Match B
+ 'TIMER0_OVFAddr' : '#46', # Timer/Counter0 Overflow
+ 'SPI_STCAddr' : '#48', # SPI Serial Transfer Complete
+ 'USART0_RXAddr' : '#50', # USART0, Rx Complete
+ 'USART0_UDREAddr' : '#52', # USART0 Data register Empty
+ 'USART0_TXAddr' : '#54', # USART0, Tx Complete
+ 'ANALOG_COMPAddr' : '#56', # Analog Comparator
+ 'ADCAddr' : '#58', # ADC Conversion Complete
+ 'EE_READYAddr' : '#60', # EEPROM Ready
+ 'TIMER3_CAPTAddr' : '#62', # Timer/Counter3 Capture Event
+ 'TIMER3_COMPAAddr' : '#64', # Timer/Counter3 Compare Match A
+ 'TIMER3_COMPBAddr' : '#66', # Timer/Counter3 Compare Match B
+ 'TIMER3_COMPCAddr' : '#68', # Timer/Counter3 Compare Match C
+ 'TIMER3_OVFAddr' : '#70', # Timer/Counter3 Overflow
+ 'USART1_RXAddr' : '#72', # USART1, Rx Complete
+ 'USART1_UDREAddr' : '#74', # USART1 Data register Empty
+ 'USART1_TXAddr' : '#76', # USART1, Tx Complete
+ 'TWIAddr' : '#78', # 2-wire Serial Interface
+ 'SPM_READYAddr' : '#80', # Store Program Memory Read
+ 'TIMER4_CAPTAddr' : '#82', # Timer/Counter4 Capture Event
+ 'TIMER4_COMPAAddr' : '#84', # Timer/Counter4 Compare Match A
+ 'TIMER4_COMPBAddr' : '#86', # Timer/Counter4 Compare Match B
+ 'TIMER4_COMPCAddr' : '#88', # Timer/Counter4 Compare Match C
+ 'TIMER4_OVFAddr' : '#90', # Timer/Counter4 Overflow
+ 'TIMER5_CAPTAddr' : '#92', # Timer/Counter5 Capture Event
+ 'TIMER5_COMPAAddr' : '#94', # Timer/Counter5 Compare Match A
+ 'TIMER5_COMPBAddr' : '#96', # Timer/Counter5 Compare Match B
+ 'TIMER5_COMPCAddr' : '#98', # Timer/Counter5 Compare Match C
+ 'TIMER5_OVFAddr' : '#100', # Timer/Counter5 Overflow
+ 'USART2_RXAddr' : '#102', # USART2, Rx Complete
+ 'USART2_UDREAddr' : '#104', # USART2 Data register Empty
+ 'USART2_TXAddr' : '#106', # USART2, Tx Complete
+ 'USART3_RXAddr' : '#108', # USART3, Rx Complete
+ 'USART3_UDREAddr' : '#110', # USART3 Data register Empty
+ 'USART3_TXAddr' : '#112', # USART3, Tx Complete
+ 'TRX24_PLL_LOCKAddr' : '#114', # TRX24 - PLL lock interrupt
+ 'TRX24_PLL_UNLOCKAddr' : '#116', # TRX24 - PLL unlock interrupt
+ 'TRX24_RX_STARTAddr' : '#118', # TRX24 - Receive start interrupt
+ 'TRX24_RX_ENDAddr' : '#120', # TRX24 - RX_END interrupt
+ 'TRX24_CCA_ED_DONEAddr' : '#122', # TRX24 - CCA/ED done interrupt
+ 'TRX24_XAH_AMIAddr' : '#124', # TRX24 - XAH - AMI
+ 'TRX24_TX_ENDAddr' : '#126', # TRX24 - TX_END interrupt
+ 'TRX24_AWAKEAddr' : '#128', # TRX24 AWAKE - tranceiver is reaching state TRX_OFF
+ 'SCNT_CMP1Addr' : '#130', # Symbol counter - compare match 1 interrupt
+ 'SCNT_CMP2Addr' : '#132', # Symbol counter - compare match 2 interrupt
+ 'SCNT_CMP3Addr' : '#134', # Symbol counter - compare match 3 interrupt
+ 'SCNT_OVFLAddr' : '#136', # Symbol counter - overflow interrupt
+ 'SCNT_BACKOFFAddr' : '#138', # Symbol counter - backoff interrupt
+ 'AES_READYAddr' : '#140', # AES engine ready interrupt
+ 'BAT_LOWAddr' : '#142', # Battery monitor indicates supply voltage below threshold
+
+# Module ANALOG_COMPARATOR
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
+ 'ACSR' : '$50', # Analog Comparator Control And
+ 'ACSR_ACD': '$80', # Analog Comparator Disable
+ 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
+ 'ACSR_ACO': '$20', # Analog Compare Output
+ 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
+ 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
+ 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
+ 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
+ 'DIDR1' : '$7f', # Digital Input Disable Register
+ 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
+ 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
+
+# Module USART0
+ 'UDR0' : '$c6', # USART0 I/O Data Register
+ 'UCSR0A' : '$c0', # USART0 Control and Status Regi
+ 'UCSR0A_RXC0': '$80', # USART Receive Complete
+ 'UCSR0A_TXC0': '$40', # USART Transmit Complete
+ 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
+ 'UCSR0A_FE0': '$10', # Frame Error
+ 'UCSR0A_DOR0': '$8', # Data OverRun
+ 'UCSR0A_UPE0': '$4', # USART Parity Error
+ 'UCSR0A_U2X0': '$2', # Double the USART Transmission
+ 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
+ 'UCSR0B' : '$c1', # USART0 Control and Status Regi
+ 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
+ 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
+ 'UCSR0B_UDRIE0': '$20', # USART Data Register Empty Inte
+ 'UCSR0B_RXEN0': '$10', # Receiver Enable
+ 'UCSR0B_TXEN0': '$8', # Transmitter Enable
+ 'UCSR0B_UCSZ02': '$4', # Character Size
+ 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
+ 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
+ 'UCSR0C' : '$c2', # USART0 Control and Status Regi
+ 'UCSR0C_UMSEL0': '$c0', # USART Mode Select
+ 'UCSR0C_UPM0': '$30', # Parity Mode
+ 'UCSR0C_USBS0': '$8', # Stop Bit Select
+ 'UCSR0C_UCSZ0': '$6', # Character Size
+ 'UCSR0C_UCPOL0': '$1', # Clock Polarity
+ 'UBRR0' : '$c4', # USART0 Baud Rate Register Byt
+
+# Module USART1
+ 'UDR1' : '$ce', # USART1 I/O Data Register
+ 'UCSR1A' : '$c8', # USART1 Control and Status Regi
+ 'UCSR1A_RXC1': '$80', # USART Receive Complete
+ 'UCSR1A_TXC1': '$40', # USART Transmit Complete
+ 'UCSR1A_UDRE1': '$20', # USART Data Register Empty
+ 'UCSR1A_FE1': '$10', # Frame Error
+ 'UCSR1A_DOR1': '$8', # Data OverRun
+ 'UCSR1A_UPE1': '$4', # USART Parity Error
+ 'UCSR1A_U2X1': '$2', # Double the USART Transmission
+ 'UCSR1A_MPCM1': '$1', # Multi-processor Communication
+ 'UCSR1B' : '$c9', # USART1 Control and Status Regi
+ 'UCSR1B_RXCIE1': '$80', # RX Complete Interrupt Enable
+ 'UCSR1B_TXCIE1': '$40', # TX Complete Interrupt Enable
+ 'UCSR1B_UDRIE1': '$20', # USART Data Register Empty Inte
+ 'UCSR1B_RXEN1': '$10', # Receiver Enable
+ 'UCSR1B_TXEN1': '$8', # Transmitter Enable
+ 'UCSR1B_UCSZ12': '$4', # Character Size
+ 'UCSR1B_RXB81': '$2', # Receive Data Bit 8
+ 'UCSR1B_TXB81': '$1', # Transmit Data Bit 8
+ 'UCSR1C' : '$ca', # USART1 Control and Status Regi
+ 'UCSR1C_UMSEL1': '$c0', # USART Mode Select
+ 'UCSR1C_UPM1': '$30', # Parity Mode
+ 'UCSR1C_USBS1': '$8', # Stop Bit Select
+ 'UCSR1C_UCSZ1': '$6', # Character Size
+ 'UCSR1C_UCPOL1': '$1', # Clock Polarity
+ 'UBRR1' : '$cc', # USART1 Baud Rate Register Byt
+
+# Module TWI
+ 'TWAMR' : '$bd', # TWI (Slave) Address Mask Regis
+ 'TWAMR_TWAM': '$fe', # TWI Address Mask
+ 'TWAMR_Res': '$1', # Reserved Bit
+ 'TWBR' : '$b8', # TWI Bit Rate Register
+ 'TWCR' : '$bc', # TWI Control Register
+ 'TWCR_TWINT': '$80', # TWI Interrupt Flag
+ 'TWCR_TWEA': '$40', # TWI Enable Acknowledge Bit
+ 'TWCR_TWSTA': '$20', # TWI START Condition Bit
+ 'TWCR_TWSTO': '$10', # TWI STOP Condition Bit
+ 'TWCR_TWWC': '$8', # TWI Write Collision Flag
+ 'TWCR_TWEN': '$4', # TWI Enable Bit
+ 'TWCR_Res': '$2', # Reserved Bit
+ 'TWCR_TWIE': '$1', # TWI Interrupt Enable
+ 'TWSR' : '$b9', # TWI Status Register
+ 'TWSR_TWS': '$f8', # TWI Status
+ 'TWSR_Res': '$4', # Reserved Bit
+ 'TWSR_TWPS': '$3', # TWI Prescaler Bits
+ 'TWDR' : '$bb', # TWI Data Register
+ 'TWAR' : '$ba', # TWI (Slave) Address Register
+ 'TWAR_TWA': '$fe', # TWI (Slave) Address
+ 'TWAR_TWGCE': '$1', # TWI General Call Recognition E
+
+# Module SPI
+ 'SPCR' : '$4c', # SPI Control Register
+ 'SPCR_SPIE': '$80', # SPI Interrupt Enable
+ 'SPCR_SPE': '$40', # SPI Enable
+ 'SPCR_DORD': '$20', # Data Order
+ 'SPCR_MSTR': '$10', # Master/Slave Select
+ 'SPCR_CPOL': '$8', # Clock polarity
+ 'SPCR_CPHA': '$4', # Clock Phase
+ 'SPCR_SPR': '$3', # SPI Clock Rate Select 1 and 0
+ 'SPSR' : '$4d', # SPI Status Register
+ 'SPSR_SPIF': '$80', # SPI Interrupt Flag
+ 'SPSR_WCOL': '$40', # Write Collision Flag
+ 'SPSR_Res': '$3e', # Reserved
+ 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
+ 'SPDR' : '$4e', # SPI Data Register
+
+# Module PORTA
+ 'PORTA' : '$22', # Port A Data Register
+ 'DDRA' : '$21', # Port A Data Direction Register
+ 'PINA' : '$20', # Port A Input Pins Address
+
+# Module PORTB
+ 'PORTB' : '$25', # Port B Data Register
+ 'DDRB' : '$24', # Port B Data Direction Register
+ 'PINB' : '$23', # Port B Input Pins Address
+
+# Module PORTC
+ 'PORTC' : '$28', # Port C Data Register
+ 'DDRC' : '$27', # Port C Data Direction Register
+ 'PINC' : '$26', # Port C Input Pins Address
+
+# Module PORTD
+ 'PORTD' : '$2b', # Port D Data Register
+ 'DDRD' : '$2a', # Port D Data Direction Register
+ 'PIND' : '$29', # Port D Input Pins Address
+
+# Module PORTE
+ 'PORTE' : '$2e', # Port E Data Register
+ 'DDRE' : '$2d', # Port E Data Direction Register
+ 'PINE' : '$2c', # Port E Input Pins Address
+
+# Module PORTF
+ 'PORTF' : '$31', # Port F Data Register
+ 'DDRF' : '$30', # Port F Data Direction Register
+ 'PINF' : '$2f', # Port F Input Pins Address
+
+# Module PORTG
+ 'PORTG' : '$34', # Port G Data Register
+ 'DDRG' : '$33', # Port G Data Direction Register
+ 'PING' : '$32', # Port G Input Pins Address
+
+# Module TIMER_COUNTER_0
+ 'OCR0B' : '$48', # Timer/Counter0 Output Compare
+ 'OCR0A' : '$47', # Timer/Counter0 Output Compare
+ 'TCNT0' : '$46', # Timer/Counter0 Register
+ 'TCCR0B' : '$45', # Timer/Counter0 Control Registe
+ 'TCCR0B_FOC0A': '$80', # Force Output Compare A
+ 'TCCR0B_FOC0B': '$40', # Force Output Compare B
+ 'TCCR0B_Res': '$30', # Reserved Bit
+ 'TCCR0B_WGM02': '$8', #
+ 'TCCR0B_CS0': '$7', # Clock Select
+ 'TCCR0A' : '$44', # Timer/Counter0 Control Registe
+ 'TCCR0A_COM0A': '$c0', # Compare Match Output A Mode
+ 'TCCR0A_COM0B': '$30', # Compare Match Output B Mode
+ 'TCCR0A_Res': '$c', # Reserved Bit
+ 'TCCR0A_WGM0': '$3', # Waveform Generation Mode
+ 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
+ 'TIMSK0_Res': '$f8', # Reserved
+ 'TIMSK0_OCIE0B': '$4', # Timer/Counter0 Output Compare
+ 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
+ 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
+ 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
+ 'TIFR0_Res': '$f8', # Reserved
+ 'TIFR0_OCF0B': '$4', # Timer/Counter0 Output Compare
+ 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
+ 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_Res': '$7c', # Reserved
+ 'GTCCR_PSRASY': '$2', # Prescaler Reset Timer/Counter2
+ 'GTCCR_PSRSYNC': '$1', # Prescaler Reset for Synchronou
+
+# Module TIMER_COUNTER_2
+ 'TIMSK2' : '$70', # Timer/Counter Interrupt Mask r
+ 'TIMSK2_Res': '$f8', # Reserved Bit
+ 'TIMSK2_OCIE2B': '$4', # Timer/Counter2 Output Compare
+ 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
+ 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
+ 'TIFR2' : '$37', # Timer/Counter Interrupt Flag R
+ 'TIFR2_Res': '$f8', # Reserved Bit
+ 'TIFR2_OCF2B': '$4', # Output Compare Flag 2 B
+ 'TIFR2_OCF2A': '$2', # Output Compare Flag 2 A
+ 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
+ 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
+ 'TCCR2A_COM2A': '$c0', # Compare Match Output A Mode
+ 'TCCR2A_COM2B': '$30', # Compare Match Output B Mode
+ 'TCCR2A_Res': '$c', # Reserved
+ 'TCCR2A_WGM2': '$3', # Waveform Generation Mode
+ 'TCCR2B' : '$b1', # Timer/Counter2 Control Registe
+ 'TCCR2B_FOC2A': '$80', # Force Output Compare A
+ 'TCCR2B_FOC2B': '$40', # Force Output Compare B
+ 'TCCR2B_Res': '$30', # Reserved
+ 'TCCR2B_WGM22': '$8', # Waveform Generation Mode
+ 'TCCR2B_CS2': '$7', # Clock Select
+ 'TCNT2' : '$b2', # Timer/Counter2
+ 'OCR2B' : '$b4', # Timer/Counter2 Output Compare
+ 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
+ 'ASSR' : '$b6', # Asynchronous Status Register
+ 'ASSR_EXCLKAMR': '$80', # Enable External Clock Input fo
+ 'ASSR_EXCLK': '$40', # Enable External Clock Input
+ 'ASSR_AS2': '$20', # Timer/Counter2 Asynchronous Mo
+ 'ASSR_TCN2UB': '$10', # Timer/Counter2 Update Busy
+ 'ASSR_OCR2AUB': '$8', # Timer/Counter2 Output Compare
+ 'ASSR_OCR2BUB': '$4', # Timer/Counter2 Output Compare
+ 'ASSR_TCR2AUB': '$2', # Timer/Counter2 Control Registe
+ 'ASSR_TCR2BUB': '$1', # Timer/Counter2 Control Registe
+ 'GTCCR' : '$43', # General Timer Counter Control
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSRASY': '$2', # Prescaler Reset Timer/Counter2
+
+# Module WATCHDOG
+ 'WDTCSR' : '$60', # Watchdog Timer Control Registe
+ 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
+ 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
+ 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
+ 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
+ 'WDTCSR_WDE': '$8', # Watch Dog Enable
+
+# Module TIMER_COUNTER_5
+ 'TCCR5A' : '$120', # Timer/Counter5 Control Registe
+ 'TCCR5A_COM5A': '$c0', # Compare Output Mode for Channe
+ 'TCCR5A_COM5B': '$30', # Compare Output Mode for Channe
+ 'TCCR5A_COM5C': '$c', # Compare Output Mode for Channe
+ 'TCCR5A_WGM5': '$3', # Waveform Generation Mode
+ 'TCCR5B' : '$121', # Timer/Counter5 Control Registe
+ 'TCCR5B_ICNC5': '$80', # Input Capture 5 Noise Cancelle
+ 'TCCR5B_ICES5': '$40', # Input Capture 5 Edge Select
+ 'TCCR5B_Res': '$20', # Reserved Bit
+ 'TCCR5B_WGM5': '$18', # Waveform Generation Mode
+ 'TCCR5B_CS5': '$7', # Clock Select
+ 'TCCR5C' : '$122', # Timer/Counter5 Control Registe
+ 'TCCR5C_FOC5A': '$80', # Force Output Compare for Chann
+ 'TCCR5C_FOC5B': '$40', # Force Output Compare for Chann
+ 'TCCR5C_FOC5C': '$20', # Force Output Compare for Chann
+ 'TCCR5C_Res': '$1f', # Reserved
+ 'TCNT5' : '$124', # Timer/Counter5 Bytes
+ 'OCR5A' : '$128', # Timer/Counter5 Output Compare
+ 'OCR5B' : '$12a', # Timer/Counter5 Output Compare
+ 'OCR5C' : '$12c', # Timer/Counter5 Output Compare
+ 'ICR5' : '$126', # Timer/Counter5 Input Capture R
+ 'TIMSK5' : '$73', # Timer/Counter5 Interrupt Mask
+ 'TIMSK5_Res': '$c0', # Reserved Bit
+ 'TIMSK5_ICIE5': '$20', # Timer/Counter5 Input Capture I
+ 'TIMSK5_Res': '$10', # Reserved Bit
+ 'TIMSK5_OCIE5C': '$8', # Timer/Counter5 Output Compare
+ 'TIMSK5_OCIE5B': '$4', # Timer/Counter5 Output Compare
+ 'TIMSK5_OCIE5A': '$2', # Timer/Counter5 Output Compare
+ 'TIMSK5_TOIE5': '$1', # Timer/Counter5 Overflow Interr
+ 'TIFR5' : '$3a', # Timer/Counter5 Interrupt Flag
+ 'TIFR5_Res': '$c0', # Reserved Bit
+ 'TIFR5_ICF5': '$20', # Timer/Counter5 Input Capture F
+ 'TIFR5_Res': '$10', # Reserved Bit
+ 'TIFR5_OCF5C': '$8', # Timer/Counter5 Output Compare
+ 'TIFR5_OCF5B': '$4', # Timer/Counter5 Output Compare
+ 'TIFR5_OCF5A': '$2', # Timer/Counter5 Output Compare
+ 'TIFR5_TOV5': '$1', # Timer/Counter5 Overflow Flag
+
+# Module TIMER_COUNTER_4
+ 'TCCR4A' : '$a0', # Timer/Counter4 Control Registe
+ 'TCCR4A_COM4A': '$c0', # Compare Output Mode for Channe
+ 'TCCR4A_COM4B': '$30', # Compare Output Mode for Channe
+ 'TCCR4A_COM4C': '$c', # Compare Output Mode for Channe
+ 'TCCR4A_WGM4': '$3', # Waveform Generation Mode
+ 'TCCR4B' : '$a1', # Timer/Counter4 Control Registe
+ 'TCCR4B_ICNC4': '$80', # Input Capture 4 Noise Cancelle
+ 'TCCR4B_ICES4': '$40', # Input Capture 4 Edge Select
+ 'TCCR4B_Res': '$20', # Reserved Bit
+ 'TCCR4B_WGM4': '$18', # Waveform Generation Mode
+ 'TCCR4B_CS4': '$7', # Clock Select
+ 'TCCR4C' : '$a2', # Timer/Counter4 Control Registe
+ 'TCCR4C_FOC4A': '$80', # Force Output Compare for Chann
+ 'TCCR4C_FOC4B': '$40', # Force Output Compare for Chann
+ 'TCCR4C_FOC4C': '$20', # Force Output Compare for Chann
+ 'TCCR4C_Res': '$1f', # Reserved
+ 'TCNT4' : '$a4', # Timer/Counter4 Bytes
+ 'OCR4A' : '$a8', # Timer/Counter4 Output Compare
+ 'OCR4B' : '$aa', # Timer/Counter4 Output Compare
+ 'OCR4C' : '$ac', # Timer/Counter4 Output Compare
+ 'ICR4' : '$a6', # Timer/Counter4 Input Capture R
+ 'TIMSK4' : '$72', # Timer/Counter4 Interrupt Mask
+ 'TIMSK4_Res': '$c0', # Reserved Bit
+ 'TIMSK4_ICIE4': '$20', # Timer/Counter4 Input Capture I
+ 'TIMSK4_Res': '$10', # Reserved Bit
+ 'TIMSK4_OCIE4C': '$8', # Timer/Counter4 Output Compare
+ 'TIMSK4_OCIE4B': '$4', # Timer/Counter4 Output Compare
+ 'TIMSK4_OCIE4A': '$2', # Timer/Counter4 Output Compare
+ 'TIMSK4_TOIE4': '$1', # Timer/Counter4 Overflow Interr
+ 'TIFR4' : '$39', # Timer/Counter4 Interrupt Flag
+ 'TIFR4_Res': '$c0', # Reserved Bit
+ 'TIFR4_ICF4': '$20', # Timer/Counter4 Input Capture F
+ 'TIFR4_Res': '$10', # Reserved Bit
+ 'TIFR4_OCF4C': '$8', # Timer/Counter4 Output Compare
+ 'TIFR4_OCF4B': '$4', # Timer/Counter4 Output Compare
+ 'TIFR4_OCF4A': '$2', # Timer/Counter4 Output Compare
+ 'TIFR4_TOV4': '$1', # Timer/Counter4 Overflow Flag
+
+# Module TIMER_COUNTER_3
+ 'TCCR3A' : '$90', # Timer/Counter3 Control Registe
+ 'TCCR3A_COM3A': '$c0', # Compare Output Mode for Channe
+ 'TCCR3A_COM3B': '$30', # Compare Output Mode for Channe
+ 'TCCR3A_COM3C': '$c', # Compare Output Mode for Channe
+ 'TCCR3A_WGM3': '$3', # Waveform Generation Mode
+ 'TCCR3B' : '$91', # Timer/Counter3 Control Registe
+ 'TCCR3B_ICNC3': '$80', # Input Capture 3 Noise Cancelle
+ 'TCCR3B_ICES3': '$40', # Input Capture 3 Edge Select
+ 'TCCR3B_Res': '$20', # Reserved Bit
+ 'TCCR3B_WGM3': '$18', # Waveform Generation Mode
+ 'TCCR3B_CS3': '$7', # Clock Select
+ 'TCCR3C' : '$92', # Timer/Counter3 Control Registe
+ 'TCCR3C_FOC3A': '$80', # Force Output Compare for Chann
+ 'TCCR3C_FOC3B': '$40', # Force Output Compare for Chann
+ 'TCCR3C_FOC3C': '$20', # Force Output Compare for Chann
+ 'TCCR3C_Res': '$1f', # Reserved
+ 'TCNT3' : '$94', # Timer/Counter3 Bytes
+ 'OCR3A' : '$98', # Timer/Counter3 Output Compare
+ 'OCR3B' : '$9a', # Timer/Counter3 Output Compare
+ 'OCR3C' : '$9c', # Timer/Counter3 Output Compare
+ 'ICR3' : '$96', # Timer/Counter3 Input Capture R
+ 'TIMSK3' : '$71', # Timer/Counter3 Interrupt Mask
+ 'TIMSK3_Res': '$c0', # Reserved Bit
+ 'TIMSK3_ICIE3': '$20', # Timer/Counter3 Input Capture I
+ 'TIMSK3_Res': '$10', # Reserved Bit
+ 'TIMSK3_OCIE3C': '$8', # Timer/Counter3 Output Compare
+ 'TIMSK3_OCIE3B': '$4', # Timer/Counter3 Output Compare
+ 'TIMSK3_OCIE3A': '$2', # Timer/Counter3 Output Compare
+ 'TIMSK3_TOIE3': '$1', # Timer/Counter3 Overflow Interr
+ 'TIFR3' : '$38', # Timer/Counter3 Interrupt Flag
+ 'TIFR3_Res': '$c0', # Reserved Bit
+ 'TIFR3_ICF3': '$20', # Timer/Counter3 Input Capture F
+ 'TIFR3_Res': '$10', # Reserved Bit
+ 'TIFR3_OCF3C': '$8', # Timer/Counter3 Output Compare
+ 'TIFR3_OCF3B': '$4', # Timer/Counter3 Output Compare
+ 'TIFR3_OCF3A': '$2', # Timer/Counter3 Output Compare
+ 'TIFR3_TOV3': '$1', # Timer/Counter3 Overflow Flag
+
+# Module TIMER_COUNTER_1
+ 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
+ 'TCCR1A_COM1A': '$c0', # Compare Output Mode for Channe
+ 'TCCR1A_COM1B': '$30', # Compare Output Mode for Channe
+ 'TCCR1A_COM1C': '$c', # Compare Output Mode for Channe
+ 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
+ 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
+ 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Cancelle
+ 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
+ 'TCCR1B_Res': '$20', # Reserved Bit
+ 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
+ 'TCCR1B_CS1': '$7', # Clock Select
+ 'TCCR1C' : '$82', # Timer/Counter1 Control Registe
+ 'TCCR1C_FOC1A': '$80', # Force Output Compare for Chann
+ 'TCCR1C_FOC1B': '$40', # Force Output Compare for Chann
+ 'TCCR1C_FOC1C': '$20', # Force Output Compare for Chann
+ 'TCCR1C_Res': '$1f', # Reserved
+ 'TCNT1' : '$84', # Timer/Counter1 Bytes
+ 'OCR1A' : '$88', # Timer/Counter1 Output Compare
+ 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
+ 'OCR1C' : '$8c', # Timer/Counter1 Output Compare
+ 'ICR1' : '$86', # Timer/Counter1 Input Capture R
+ 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
+ 'TIMSK1_Res': '$c0', # Reserved Bit
+ 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
+ 'TIMSK1_Res': '$10', # Reserved Bit
+ 'TIMSK1_OCIE1C': '$8', # Timer/Counter1 Output Compare
+ 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
+ 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
+ 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
+ 'TIFR1' : '$36', # Timer/Counter1 Interrupt Flag
+ 'TIFR1_Res': '$c0', # Reserved Bit
+ 'TIFR1_ICF1': '$20', # Timer/Counter1 Input Capture F
+ 'TIFR1_Res': '$10', # Reserved Bit
+ 'TIFR1_OCF1C': '$8', # Timer/Counter1 Output Compare
+ 'TIFR1_OCF1B': '$4', # Timer/Counter1 Output Compare
+ 'TIFR1_OCF1A': '$2', # Timer/Counter1 Output Compare
+ 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
+
+# Module TRX24
+ 'AES_CTRL' : '$13c', # AES Control Register
+ 'AES_CTRL_AES_REQUEST': '$80', # Request AES Operation.
+ 'AES_CTRL_Res': '$40', # Reserved Bit
+ 'AES_CTRL_AES_MODE': '$20', # Set AES Operation Mode
+ 'AES_CTRL_Res': '$10', # Reserved Bit
+ 'AES_CTRL_AES_DIR': '$8', # Set AES Operation Direction
+ 'AES_CTRL_AES_IM': '$4', # AES Interrupt Enable
+ 'AES_CTRL_Res': '$3', # Reserved Bit
+ 'AES_STATUS' : '$13d', # AES Status Register
+ 'AES_STATUS_AES_ER': '$80', # AES Operation Finished with Er
+ 'AES_STATUS_Res': '$7e', # Reserved
+ 'AES_STATUS_AES_DONE': '$1', # AES Operation Finished with Su
+ 'AES_STATE' : '$13e', # AES Plain and Cipher Text Buff
+ 'AES_STATE_AES_STATE': '$ff', # AES Plain and Cipher Text Buff
+ 'AES_KEY' : '$13f', # AES Encryption and Decryption
+ 'AES_KEY_AES_KEY': '$ff', # AES Encryption/Decryption Key
+ 'TRX_STATUS' : '$141', # Transceiver Status Register
+ 'TRX_STATUS_CCA_DONE': '$80', # CCA Algorithm Status
+ 'TRX_STATUS_CCA_STATUS': '$40', # CCA Status Result
+ 'TRX_STATUS_TST_STATUS': '$20', # Test mode status
+ 'TRX_STATUS_TRX_STATUS': '$1f', # Transceiver Main Status
+ 'TRX_STATE' : '$142', # Transceiver State Control Regi
+ 'TRX_STATE_TRAC_STATUS': '$e0', # Transaction Status
+ 'TRX_STATE_TRX_CMD': '$1f', # State Control Command
+ 'TRX_CTRL_0' : '$143', # Reserved
+ 'TRX_CTRL_0_Res': '$ff', # Reserved
+ 'TRX_CTRL_1' : '$144', # Transceiver Control Register 1
+ 'TRX_CTRL_1_PA_EXT_EN': '$80', # External PA support enable
+ 'TRX_CTRL_1_IRQ_2_EXT_EN': '$40', # Connect Frame Start IRQ to TC1
+ 'TRX_CTRL_1_TX_AUTO_CRC_ON': '$20', # Enable Automatic CRC Calculati
+ 'TRX_CTRL_1_Res': '$1f', # Reserved
+ 'PHY_TX_PWR' : '$145', # Transceiver Transmit Power Con
+ 'PHY_TX_PWR_PA_BUF_LT': '$c0', # Power Amplifier Buffer Lead Ti
+ 'PHY_TX_PWR_PA_LT': '$30', # Power Amplifier Lead Time
+ 'PHY_TX_PWR_TX_PWR': '$f', # Transmit Power Setting
+ 'PHY_RSSI' : '$146', # Receiver Signal Strength Indic
+ 'PHY_RSSI_RX_CRC_VALID': '$80', # Received Frame CRC Status
+ 'PHY_RSSI_RND_VALUE': '$60', # Random Value
+ 'PHY_RSSI_RSSI': '$1f', # Receiver Signal Strength Indic
+ 'PHY_ED_LEVEL' : '$147', # Transceiver Energy Detection L
+ 'PHY_ED_LEVEL_ED_LEVEL': '$ff', # Energy Detection Level
+ 'PHY_CC_CCA' : '$148', # Transceiver Clear Channel Asse
+ 'PHY_CC_CCA_CCA_REQUEST': '$80', # Manual CCA Measurement Request
+ 'PHY_CC_CCA_CCA_MODE': '$60', # Select CCA Measurement Mode
+ 'PHY_CC_CCA_CHANNEL': '$1f', # RX/TX Channel Selection
+ 'CCA_THRES' : '$149', # Transceiver CCA Threshold Sett
+ 'CCA_THRES_CCA_CS_THRES': '$f0', # CS Threshold Level for CCA Mea
+ 'CCA_THRES_CCA_ED_THRES': '$f', # ED Threshold Level for CCA Mea
+ 'RX_CTRL' : '$14a', # Transceiver Receive Control Re
+ 'RX_CTRL_PDT_THRES': '$f', # Receiver Sensitivity Control
+ 'SFD_VALUE' : '$14b', # Start of Frame Delimiter Value
+ 'SFD_VALUE_SFD_VALUE': '$ff', # Start of Frame Delimiter Value
+ 'TRX_CTRL_2' : '$14c', # Transceiver Control Register 2
+ 'TRX_CTRL_2_RX_SAFE_MODE': '$80', # RX Safe Mode
+ 'TRX_CTRL_2_Res': '$7c', # Reserved
+ 'TRX_CTRL_2_OQPSK_DATA_RATE': '$3', # Data Rate Selection
+ 'ANT_DIV' : '$14d', # Antenna Diversity Control Regi
+ 'ANT_DIV_ANT_SEL': '$80', # Antenna Diversity Antenna Stat
+ 'ANT_DIV_Res': '$70', # Reserved
+ 'ANT_DIV_ANT_DIV_EN': '$8', # Enable Antenna Diversity
+ 'ANT_DIV_ANT_EXT_SW_EN': '$4', # Enable External Antenna Switch
+ 'ANT_DIV_ANT_CTRL': '$3', # Static Antenna Diversity Switc
+ 'IRQ_MASK' : '$14e', # Transceiver Interrupt Enable R
+ 'IRQ_MASK_AWAKE_EN': '$80', # Awake Interrupt Enable
+ 'IRQ_MASK_TX_END_EN': '$40', # TX_END Interrupt Enable
+ 'IRQ_MASK_AMI_EN': '$20', # Address Match Interrupt Enable
+ 'IRQ_MASK_CCA_ED_DONE_EN': '$10', # End of ED Measurement Interrup
+ 'IRQ_MASK_RX_END_EN': '$8', # RX_END Interrupt Enable
+ 'IRQ_MASK_RX_START_EN': '$4', # RX_START Interrupt Enable
+ 'IRQ_MASK_PLL_UNLOCK_EN': '$2', # PLL Unlock Interrupt Enable
+ 'IRQ_MASK_PLL_LOCK_EN': '$1', # PLL Lock Interrupt Enable
+ 'IRQ_STATUS' : '$14f', # Transceiver Interrupt Status R
+ 'IRQ_STATUS_AWAKE': '$80', # Awake Interrupt Status
+ 'IRQ_STATUS_TX_END': '$40', # TX_END Interrupt Status
+ 'IRQ_STATUS_AMI': '$20', # Address Match Interrupt Status
+ 'IRQ_STATUS_CCA_ED_DONE': '$10', # End of ED Measurement Interrup
+ 'IRQ_STATUS_RX_END': '$8', # RX_END Interrupt Status
+ 'IRQ_STATUS_RX_START': '$4', # RX_START Interrupt Status
+ 'IRQ_STATUS_PLL_UNLOCK': '$2', # PLL Unlock Interrupt Status
+ 'IRQ_STATUS_PLL_LOCK': '$1', # PLL Lock Interrupt Status
+ 'VREG_CTRL' : '$150', # Voltage Regulator Control and
+ 'VREG_CTRL_AVREG_EXT': '$80', # Use External AVDD Regulator
+ 'VREG_CTRL_AVDD_OK': '$40', # AVDD Supply Voltage Valid
+ 'VREG_CTRL_DVREG_EXT': '$8', # Use External DVDD Regulator
+ 'VREG_CTRL_DVDD_OK': '$4', # DVDD Supply Voltage Valid
+ 'BATMON' : '$151', # Battery Monitor Control and St
+ 'BATMON_BAT_LOW': '$80', # Battery Monitor Interrupt Stat
+ 'BATMON_BAT_LOW_EN': '$40', # Battery Monitor Interrupt Enab
+ 'BATMON_BATMON_OK': '$20', # Battery Monitor Status
+ 'BATMON_BATMON_HR': '$10', # Battery Monitor Voltage Range
+ 'BATMON_BATMON_VTH': '$f', # Battery Monitor Threshold Volt
+ 'XOSC_CTRL' : '$152', # Crystal Oscillator Control Reg
+ 'XOSC_CTRL_XTAL_MODE': '$f0', # Crystal Oscillator Operating M
+ 'XOSC_CTRL_XTAL_TRIM': '$f', # Crystal Oscillator Load Capaci
+ 'RX_SYN' : '$155', # Transceiver Receiver Sensitivi
+ 'RX_SYN_RX_PDT_DIS': '$80', # Prevent Frame Reception
+ 'RX_SYN_Res': '$70', # Reserved
+ 'RX_SYN_RX_PDT_LEVEL': '$f', # Reduce Receiver Sensitivity
+ 'XAH_CTRL_1' : '$157', # Transceiver Acknowledgment Fra
+ 'XAH_CTRL_1_Res': '$c0', # Reserved Bit
+ 'XAH_CTRL_1_AACK_FLTR_RES_FT': '$20', # Filter Reserved Frames
+ 'XAH_CTRL_1_AACK_UPLD_RES_FT': '$10', # Process Reserved Frames
+ 'XAH_CTRL_1_Res': '$8', # Reserved Bit
+ 'XAH_CTRL_1_AACK_ACK_TIME': '$4', # Reduce Acknowledgment Time
+ 'XAH_CTRL_1_AACK_PROM_MODE': '$2', # Enable Promiscuous Mode
+ 'XAH_CTRL_1_Res': '$1', # Reserved Bit
+ 'FTN_CTRL' : '$158', # Transceiver Filter Tuning Cont
+ 'FTN_CTRL_FTN_START': '$80', # Start Calibration Loop of Filt
+ 'PLL_CF' : '$15a', # Transceiver Center Frequency C
+ 'PLL_CF_PLL_CF_START': '$80', # Start Center Frequency Calibra
+ 'PLL_DCU' : '$15b', # Transceiver Delay Cell Calibra
+ 'PLL_DCU_PLL_DCU_START': '$80', # Start Delay Cell Calibration
+ 'PART_NUM' : '$15c', # Device Identification Register
+ 'PART_NUM_PART_NUM': '$ff', # Part Number
+ 'VERSION_NUM' : '$15d', # Device Identification Register
+ 'VERSION_NUM_VERSION_NUM': '$ff', # Version Number
+ 'MAN_ID_0' : '$15e', # Device Identification Register
+ 'MAN_ID_0_MAN_ID_07': '$80', # Manufacturer ID (Low Byte)
+ 'MAN_ID_0_MAN_ID_06': '$40', # Manufacturer ID (Low Byte)
+ 'MAN_ID_0_MAN_ID_05': '$20', # Manufacturer ID (Low Byte)
+ 'MAN_ID_0_MAN_ID_04': '$10', # Manufacturer ID (Low Byte)
+ 'MAN_ID_0_MAN_ID_03': '$8', # Manufacturer ID (Low Byte)
+ 'MAN_ID_0_MAN_ID_02': '$4', # Manufacturer ID (Low Byte)
+ 'MAN_ID_0_MAN_ID_01': '$2', # Manufacturer ID (Low Byte)
+ 'MAN_ID_0_MAN_ID_00': '$1', # Manufacturer ID (Low Byte)
+ 'MAN_ID_1' : '$15f', # Device Identification Register
+ 'MAN_ID_1_MAN_ID_': '$ff', # Manufacturer ID (High Byte)
+ 'SHORT_ADDR_0' : '$160', # Transceiver MAC Short Address
+ 'SHORT_ADDR_0_SHORT_ADDR_07': '$80', # MAC Short Address
+ 'SHORT_ADDR_0_SHORT_ADDR_06': '$40', # MAC Short Address
+ 'SHORT_ADDR_0_SHORT_ADDR_05': '$20', # MAC Short Address
+ 'SHORT_ADDR_0_SHORT_ADDR_04': '$10', # MAC Short Address
+ 'SHORT_ADDR_0_SHORT_ADDR_03': '$8', # MAC Short Address
+ 'SHORT_ADDR_0_SHORT_ADDR_02': '$4', # MAC Short Address
+ 'SHORT_ADDR_0_SHORT_ADDR_01': '$2', # MAC Short Address
+ 'SHORT_ADDR_0_SHORT_ADDR_00': '$1', # MAC Short Address
+ 'SHORT_ADDR_1' : '$161', # Transceiver MAC Short Address
+ 'SHORT_ADDR_1_SHORT_ADDR_': '$ff', # MAC Short Address
+ 'PAN_ID_0' : '$162', # Transceiver Personal Area Netw
+ 'PAN_ID_0_PAN_ID_07': '$80', # MAC Personal Area Network ID
+ 'PAN_ID_0_PAN_ID_06': '$40', # MAC Personal Area Network ID
+ 'PAN_ID_0_PAN_ID_05': '$20', # MAC Personal Area Network ID
+ 'PAN_ID_0_PAN_ID_04': '$10', # MAC Personal Area Network ID
+ 'PAN_ID_0_PAN_ID_03': '$8', # MAC Personal Area Network ID
+ 'PAN_ID_0_PAN_ID_02': '$4', # MAC Personal Area Network ID
+ 'PAN_ID_0_PAN_ID_01': '$2', # MAC Personal Area Network ID
+ 'PAN_ID_0_PAN_ID_00': '$1', # MAC Personal Area Network ID
+ 'PAN_ID_1' : '$163', # Transceiver Personal Area Netw
+ 'PAN_ID_1_PAN_ID_': '$ff', # MAC Personal Area Network ID
+ 'IEEE_ADDR_0' : '$164', # Transceiver MAC IEEE Address R
+ 'IEEE_ADDR_0_IEEE_ADDR_07': '$80', # MAC IEEE Address
+ 'IEEE_ADDR_0_IEEE_ADDR_06': '$40', # MAC IEEE Address
+ 'IEEE_ADDR_0_IEEE_ADDR_05': '$20', # MAC IEEE Address
+ 'IEEE_ADDR_0_IEEE_ADDR_04': '$10', # MAC IEEE Address
+ 'IEEE_ADDR_0_IEEE_ADDR_03': '$8', # MAC IEEE Address
+ 'IEEE_ADDR_0_IEEE_ADDR_02': '$4', # MAC IEEE Address
+ 'IEEE_ADDR_0_IEEE_ADDR_01': '$2', # MAC IEEE Address
+ 'IEEE_ADDR_0_IEEE_ADDR_00': '$1', # MAC IEEE Address
+ 'IEEE_ADDR_1' : '$165', # Transceiver MAC IEEE Address R
+ 'IEEE_ADDR_1_IEEE_ADDR_': '$ff', # MAC IEEE Address
+ 'IEEE_ADDR_2' : '$166', # Transceiver MAC IEEE Address R
+ 'IEEE_ADDR_2_IEEE_ADDR_': '$ff', # MAC IEEE Address
+ 'IEEE_ADDR_3' : '$167', # Transceiver MAC IEEE Address R
+ 'IEEE_ADDR_3_IEEE_ADDR_': '$ff', # MAC IEEE Address
+ 'IEEE_ADDR_4' : '$168', # Transceiver MAC IEEE Address R
+ 'IEEE_ADDR_4_IEEE_ADDR_': '$ff', # MAC IEEE Address
+ 'IEEE_ADDR_5' : '$169', # Transceiver MAC IEEE Address R
+ 'IEEE_ADDR_5_IEEE_ADDR_': '$ff', # MAC IEEE Address
+ 'IEEE_ADDR_6' : '$16a', # Transceiver MAC IEEE Address R
+ 'IEEE_ADDR_6_IEEE_ADDR_': '$ff', # MAC IEEE Address
+ 'IEEE_ADDR_7' : '$16b', # Transceiver MAC IEEE Address R
+ 'IEEE_ADDR_7_IEEE_ADDR_': '$ff', # MAC IEEE Address
+ 'XAH_CTRL_0' : '$16c', # Transceiver Extended Operating
+ 'XAH_CTRL_0_MAX_FRAME_RETRIES': '$f0', # Maximum Number of Frame Re-tra
+ 'XAH_CTRL_0_MAX_CSMA_RETRIES': '$e', # Maximum Number of CSMA-CA Proc
+ 'XAH_CTRL_0_SLOTTED_OPERATION': '$1', # Set Slotted Acknowledgment
+ 'CSMA_SEED_0' : '$16d', # Transceiver CSMA-CA Random Num
+ 'CSMA_SEED_0_CSMA_SEED_07': '$80', # Seed Value for CSMA Random Num
+ 'CSMA_SEED_0_CSMA_SEED_06': '$40', # Seed Value for CSMA Random Num
+ 'CSMA_SEED_0_CSMA_SEED_05': '$20', # Seed Value for CSMA Random Num
+ 'CSMA_SEED_0_CSMA_SEED_04': '$10', # Seed Value for CSMA Random Num
+ 'CSMA_SEED_0_CSMA_SEED_03': '$8', # Seed Value for CSMA Random Num
+ 'CSMA_SEED_0_CSMA_SEED_02': '$4', # Seed Value for CSMA Random Num
+ 'CSMA_SEED_0_CSMA_SEED_01': '$2', # Seed Value for CSMA Random Num
+ 'CSMA_SEED_0_CSMA_SEED_00': '$1', # Seed Value for CSMA Random Num
+ 'CSMA_SEED_1' : '$16e', # Transceiver Acknowledgment Fra
+ 'CSMA_SEED_1_AACK_FVN_MODE': '$c0', # Acknowledgment Frame Filter Mo
+ 'CSMA_SEED_1_AACK_SET_PD': '$20', # Set Frame Pending Sub-field
+ 'CSMA_SEED_1_AACK_DIS_ACK': '$10', # Disable Acknowledgment Frame T
+ 'CSMA_SEED_1_AACK_I_AM_COORD': '$8', # Set Personal Area Network Coor
+ 'CSMA_SEED_1_CSMA_SEED_1': '$7', # Seed Value for CSMA Random Num
+ 'CSMA_BE' : '$16f', # Transceiver CSMA-CA Back-off E
+ 'CSMA_BE_MAX_BE': '$f0', # Maximum Back-off Exponent
+ 'CSMA_BE_MIN_BE': '$f', # Minimum Back-off Exponent
+ 'TST_CTRL_DIGI' : '$176', # Transceiver Digital Test Contr
+ 'TST_CTRL_DIGI_TST_CTRL_DIG': '$f', # Digital Test Controller Regist
+ 'TST_RX_LENGTH' : '$17b', # Transceiver Received Frame Len
+ 'TST_RX_LENGTH_RX_LENGTH': '$ff', # Received Frame Length
+ 'TRXFBST' : '$180', # Start of frame buffer
+ 'TRXFBEND' : '$1ff', # End of frame buffer
+
+# Module SYMCNT
+ 'SCOCR1HH' : '$f8', # Symbol Counter Output Compare
+ 'SCOCR1HH_SCOCR1HH': '$ff', # Symbol Counter Output Compare
+ 'SCOCR1HL' : '$f7', # Symbol Counter Output Compare
+ 'SCOCR1HL_SCOCR1HL': '$ff', # Symbol Counter Output Compare
+ 'SCOCR1LH' : '$f6', # Symbol Counter Output Compare
+ 'SCOCR1LH_SCOCR1LH': '$ff', # Symbol Counter Output Compare
+ 'SCOCR1LL' : '$f5', # Symbol Counter Output Compare
+ 'SCOCR1LL_SCOCR1LL': '$ff', # Symbol Counter Output Compare
+ 'SCOCR2HH' : '$f4', # Symbol Counter Output Compare
+ 'SCOCR2HH_SCOCR2HH': '$ff', # Symbol Counter Output Compare
+ 'SCOCR2HL' : '$f3', # Symbol Counter Output Compare
+ 'SCOCR2HL_SCOCR2HL': '$ff', # Symbol Counter Output Compare
+ 'SCOCR2LH' : '$f2', # Symbol Counter Output Compare
+ 'SCOCR2LH_SCOCR2LH': '$ff', # Symbol Counter Output Compare
+ 'SCOCR2LL' : '$f1', # Symbol Counter Output Compare
+ 'SCOCR2LL_SCOCR2LL': '$ff', # Symbol Counter Output Compare
+ 'SCOCR3HH' : '$f0', # Symbol Counter Output Compare
+ 'SCOCR3HH_SCOCR3HH': '$ff', # Symbol Counter Output Compare
+ 'SCOCR3HL' : '$ef', # Symbol Counter Output Compare
+ 'SCOCR3HL_SCOCR3HL': '$ff', # Symbol Counter Output Compare
+ 'SCOCR3LH' : '$ee', # Symbol Counter Output Compare
+ 'SCOCR3LH_SCOCR3LH': '$ff', # Symbol Counter Output Compare
+ 'SCOCR3LL' : '$ed', # Symbol Counter Output Compare
+ 'SCOCR3LL_SCOCR3LL': '$ff', # Symbol Counter Output Compare
+ 'SCTSRHH' : '$ec', # Symbol Counter Frame Timestamp
+ 'SCTSRHH_SCTSRHH': '$ff', # Symbol Counter Frame Timestamp
+ 'SCTSRHL' : '$eb', # Symbol Counter Frame Timestamp
+ 'SCTSRHL_SCTSRHL': '$ff', # Symbol Counter Frame Timestamp
+ 'SCTSRLH' : '$ea', # Symbol Counter Frame Timestamp
+ 'SCTSRLH_SCTSRLH': '$ff', # Symbol Counter Frame Timestamp
+ 'SCTSRLL' : '$e9', # Symbol Counter Frame Timestamp
+ 'SCTSRLL_SCTSRLL': '$ff', # Symbol Counter Frame Timestamp
+ 'SCBTSRHH' : '$e8', # Symbol Counter Beacon Timestam
+ 'SCBTSRHH_SCBTSRHH': '$ff', # Symbol Counter Beacon Timestam
+ 'SCBTSRHL' : '$e7', # Symbol Counter Beacon Timestam
+ 'SCBTSRHL_SCBTSRHL': '$ff', # Symbol Counter Beacon Timestam
+ 'SCBTSRLH' : '$e6', # Symbol Counter Beacon Timestam
+ 'SCBTSRLH_SCBTSRLH': '$ff', # Symbol Counter Beacon Timestam
+ 'SCBTSRLL' : '$e5', # Symbol Counter Beacon Timestam
+ 'SCBTSRLL_SCBTSRLL': '$ff', # Symbol Counter Beacon Timestam
+ 'SCCNTHH' : '$e4', # Symbol Counter Register HH-Byt
+ 'SCCNTHH_SCCNTHH': '$ff', # Symbol Counter Register HH-Byt
+ 'SCCNTHL' : '$e3', # Symbol Counter Register HL-Byt
+ 'SCCNTHL_SCCNTHL': '$ff', # Symbol Counter Register HL-Byt
+ 'SCCNTLH' : '$e2', # Symbol Counter Register LH-Byt
+ 'SCCNTLH_SCCNTLH': '$ff', # Symbol Counter Register LH-Byt
+ 'SCCNTLL' : '$e1', # Symbol Counter Register LL-Byt
+ 'SCCNTLL_SCCNTLL': '$ff', # Symbol Counter Register LL-Byt
+ 'SCIRQS' : '$e0', # Symbol Counter Interrupt Statu
+ 'SCIRQS_Res': '$e0', # Reserved Bit
+ 'SCIRQS_IRQSBO': '$10', # Backoff Slot Counter IRQ
+ 'SCIRQS_IRQSOF': '$8', # Symbol Counter Overflow IRQ
+ 'SCIRQS_IRQSCP': '$7', # Compare Unit 3 Compare Match I
+ 'SCIRQM' : '$df', # Symbol Counter Interrupt Mask
+ 'SCIRQM_Res': '$e0', # Reserved Bit
+ 'SCIRQM_IRQMBO': '$10', # Backoff Slot Counter IRQ enabl
+ 'SCIRQM_IRQMOF': '$8', # Symbol Counter Overflow IRQ en
+ 'SCIRQM_IRQMCP': '$7', # Symbol Counter Compare Match 3
+ 'SCSR' : '$de', # Symbol Counter Status Register
+ 'SCSR_Res': '$fe', # Reserved Bit
+ 'SCSR_SCBSY': '$1', # Symbol Counter busy
+ 'SCCR1' : '$dd', # Symbol Counter Control Registe
+ 'SCCR1_Res': '$fe', # Reserved Bit
+ 'SCCR1_SCENBO': '$1', # Backoff Slot Counter enable
+ 'SCCR0' : '$dc', # Symbol Counter Control Registe
+ 'SCCR0_SCRES': '$80', # Symbol Counter Synchronization
+ 'SCCR0_SCMBTS': '$40', # Manual Beacon Timestamp
+ 'SCCR0_SCEN': '$20', # Symbol Counter enable
+ 'SCCR0_SCCKSEL': '$10', # Symbol Counter Clock Source se
+ 'SCCR0_SCTSE': '$8', # Symbol Counter Automatic Times
+ 'SCCR0_SCCMP': '$7', # Symbol Counter Compare Unit 3
+
+# Module EEPROM
+ 'EEAR' : '$41', # EEPROM Address Register Bytes
+ 'EEDR' : '$40', # EEPROM Data Register
+ 'EECR' : '$3f', # EEPROM Control Register
+ 'EECR_Res': '$c0', # Reserved
+ 'EECR_EEPM': '$30', # EEPROM Programming Mode
+ 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
+ 'EECR_EEMPE': '$4', # EEPROM Master Write Enable
+ 'EECR_EEPE': '$2', # EEPROM Programming Enable
+ 'EECR_EERE': '$1', # EEPROM Read Enable
+
+# Module JTAG
+ 'OCDR' : '$51', # On-Chip Debug Register
+ 'OCDR_OCDR': '$ff', # On-Chip Debug Register Data
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_JTD': '$80', # JTAG Interface Disable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+
+# Module EXTERNAL_INTERRUPT
+ 'EICRA' : '$69', # External Interrupt Control Reg
+ 'EICRA_ISC3': '$c0', # External Interrupt 3 Sense Con
+ 'EICRA_ISC2': '$30', # External Interrupt 2 Sense Con
+ 'EICRA_ISC1': '$c', # External Interrupt 1 Sense Con
+ 'EICRA_ISC0': '$3', # External Interrupt 0 Sense Con
+ 'EICRB' : '$6a', # External Interrupt Control Reg
+ 'EICRB_ISC7': '$c0', # External Interrupt 7 Sense Con
+ 'EICRB_ISC6': '$30', # External Interrupt 6 Sense Con
+ 'EICRB_ISC5': '$c', # External Interrupt 5 Sense Con
+ 'EICRB_ISC4': '$3', # External Interrupt 4 Sense Con
+ 'EIMSK' : '$3d', # External Interrupt Mask Regist
+ 'EIMSK_INT': '$ff', # External Interrupt Request Ena
+ 'EIFR' : '$3c', # External Interrupt Flag Regist
+ 'EIFR_INTF': '$ff', # External Interrupt Flag
+ 'PCMSK2' : '$6d', # Pin Change Mask Register 2
+ 'PCMSK2_PCINT': '$ff', # Pin Change Enable Mask
+ 'PCMSK1' : '$6c', # Pin Change Mask Register 1
+ 'PCMSK1_PCINT': '$ff', # Pin Change Enable Mask
+ 'PCMSK0' : '$6b', # Pin Change Mask Register 0
+ 'PCIFR' : '$3b', # Pin Change Interrupt Flag Regi
+ 'PCIFR_Res': '$f8', # Reserved Bit
+ 'PCIFR_PCIF': '$7', # Pin Change Interrupt Flags
+ 'PCICR' : '$68', # Pin Change Interrupt Control R
+ 'PCICR_Res': '$f8', # Reserved Bit
+ 'PCICR_PCIE': '$7', # Pin Change Interrupt Enables
+
+# Module AD_CONVERTER
+ 'ADMUX' : '$7c', # The ADC Multiplexer Selection
+ 'ADMUX_REFS': '$c0', # Reference Selection Bits
+ 'ADMUX_ADLAR': '$20', # ADC Left Adjust Result
+ 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
+ 'ADC' : '$78', # ADC Data Register Bytes
+ 'ADCSRA' : '$7a', # The ADC Control and Status Reg
+ 'ADCSRA_ADEN': '$80', # ADC Enable
+ 'ADCSRA_ADSC': '$40', # ADC Start Conversion
+ 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
+ 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
+ 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
+ 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
+ 'ADCSRB' : '$7b', # The ADC Control and Status Reg
+ 'ADCSRB_AVDDOK': '$80', # AVDD Supply Voltage OK
+ 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
+ 'ADCSRB_REFOK': '$20', # Reference Voltage OK
+ 'ADCSRB_ACCH': '$10', # Analog Channel Change
+ 'ADCSRB_MUX5': '$8', # Analog Channel and Gain Select
+ 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Source
+ 'ADCSRC' : '$77', # The ADC Control and Status Reg
+ 'ADCSRC_ADTHT': '$c0', # ADC Track-and-Hold Time
+ 'ADCSRC_Res0': '$20', # Reserved
+ 'ADCSRC_ADSUT': '$1f', # ADC Start-up Time
+ 'DIDR2' : '$7d', # Digital Input Disable Register
+ 'DIDR2_ADC15D': '$80', # Reserved Bits
+ 'DIDR2_ADC14D': '$40', # Reserved Bits
+ 'DIDR2_ADC13D': '$20', # Reserved Bits
+ 'DIDR2_ADC12D': '$10', # Reserved Bits
+ 'DIDR2_ADC11D': '$8', # Reserved Bits
+ 'DIDR2_ADC10D': '$4', # Reserved Bits
+ 'DIDR2_ADC9D': '$2', # Reserved Bits
+ 'DIDR2_ADC8D': '$1', # Reserved Bits
+ 'DIDR0' : '$7e', # Digital Input Disable Register
+ 'DIDR0_ADC7D': '$80', # Disable ADC7:0 Digital Input
+ 'DIDR0_ADC6D': '$40', # Disable ADC7:0 Digital Input
+ 'DIDR0_ADC5D': '$20', # Disable ADC7:0 Digital Input
+ 'DIDR0_ADC4D': '$10', # Disable ADC7:0 Digital Input
+ 'DIDR0_ADC3D': '$8', # Disable ADC7:0 Digital Input
+ 'DIDR0_ADC2D': '$4', # Disable ADC7:0 Digital Input
+ 'DIDR0_ADC1D': '$2', # Disable ADC7:0 Digital Input
+ 'DIDR0_ADC0D': '$1', # Disable ADC7:0 Digital Input
+
+# Module BOOT_LOAD
+ 'SPMCSR' : '$57', # Store Program Memory Control R
+ 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
+ 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
+ 'SPMCSR_SIGRD': '$20', # Signature Row Read
+ 'SPMCSR_RWWSRE': '$10', # Read While Write Section Read
+ 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
+ 'SPMCSR_PGWRT': '$4', # Page Write
+ 'SPMCSR_PGERS': '$2', # Page Erase
+ 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
+
+# Module CPU
+ 'SREG' : '$5f', # Status Register
+ 'SREG_I': '$80', # Global Interrupt Enable
+ 'SREG_T': '$40', # Bit Copy Storage
+ 'SREG_H': '$20', # Half Carry Flag
+ 'SREG_S': '$10', # Sign Bit
+ 'SREG_V': '$8', # Two's Complement Overflow Flag
+ 'SREG_N': '$4', # Negative Flag
+ 'SREG_Z': '$2', # Zero Flag
+ 'SREG_C': '$1', # Carry Flag
+ 'SP' : '$5d', # Stack Pointer
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_JTD': '$80', # JTAG Interface Disable
+ 'MCUCR_Res': '$60', # Reserved
+ 'MCUCR_PUD': '$10', # Pull-up Disable
+ 'MCUCR_Res': '$c', # Reserved
+ 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
+ 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_Res': '$e0', # Reserved
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+ 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
+ 'MCUSR_BORF': '$4', # Brown-out Reset Flag
+ 'MCUSR_EXTRF': '$2', # External Reset Flag
+ 'MCUSR_PORF': '$1', # Power-on Reset Flag
+ 'OSCCAL' : '$66', # Oscillator Calibration Value
+ 'OSCCAL_CAL': '$ff', # Oscillator Calibration Tuning
+ 'CLKPR' : '$61', # Clock Prescale Register
+ 'CLKPR_CLKPCE': '$80', # Clock Prescaler Change Enable
+ 'CLKPR_Res': '$70', # Reserved
+ 'CLKPR_CLKPS': '$f', # Clock Prescaler Select Bits
+ 'SMCR' : '$53', # Sleep Mode Control Register
+ 'SMCR_Res': '$f0', # Reserved
+ 'SMCR_SM': '$e', # Sleep Mode Select bits
+ 'SMCR_SE': '$1', # Sleep Enable
+ 'RAMPZ' : '$5b', # Extended Z-pointer Register fo
+ 'RAMPZ_Res': '$fc', # Reserved
+ 'RAMPZ_RAMPZ': '$3', # Extended Z-Pointer Value
+ 'GPIOR2' : '$4b', # General Purpose I/O Register 2
+ 'GPIOR2_GPIOR': '$ff', # General Purpose I/O Register 2
+ 'GPIOR1' : '$4a', # General Purpose IO Register 1
+ 'GPIOR1_GPIOR': '$ff', # General Purpose I/O Register 1
+ 'GPIOR0' : '$3e', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR07': '$80', # General Purpose I/O Register 0
+ 'GPIOR0_GPIOR06': '$40', # General Purpose I/O Register 0
+ 'GPIOR0_GPIOR05': '$20', # General Purpose I/O Register 0
+ 'GPIOR0_GPIOR04': '$10', # General Purpose I/O Register 0
+ 'GPIOR0_GPIOR03': '$8', # General Purpose I/O Register 0
+ 'GPIOR0_GPIOR02': '$4', # General Purpose I/O Register 0
+ 'GPIOR0_GPIOR01': '$2', # General Purpose I/O Register 0
+ 'GPIOR0_GPIOR00': '$1', # General Purpose I/O Register 0
+ 'PRR2' : '$63', # Power Reduction Register 2
+ 'PRR2_Res': '$f0', # Reserved Bit
+ 'PRR2_PRRAM': '$f', # Power Reduction SRAMs
+ 'PRR1' : '$65', # Power Reduction Register 1
+ 'PRR1_Res': '$80', # Reserved Bit
+ 'PRR1_PRTRX24': '$40', # Power Reduction Transceiver
+ 'PRR1_PRTIM5': '$20', # Power Reduction Timer/Counter5
+ 'PRR1_PRTIM4': '$10', # Power Reduction Timer/Counter4
+ 'PRR1_PRTIM3': '$8', # Power Reduction Timer/Counter3
+ 'PRR1_PRUSART': '$7', # Reserved
+ 'PRR0' : '$64', # Power Reduction Register0
+ 'PRR0_PRTWI': '$80', # Power Reduction TWI
+ 'PRR0_PRTIM2': '$40', # Power Reduction Timer/Counter2
+ 'PRR0_PRTIM0': '$20', # Power Reduction Timer/Counter0
+ 'PRR0_PRPGA': '$10', # Power Reduction PGA
+ 'PRR0_PRTIM1': '$8', # Power Reduction Timer/Counter1
+ 'PRR0_PRSPI': '$4', # Power Reduction Serial Periphe
+ 'PRR0_PRUSART0': '$2', # Power Reduction USART
+ 'PRR0_PRADC': '$1', # Power Reduction ADC
+
+# Module FLASH
+ 'NEMCR' : '$75', # Flash Extended-Mode Control-Re
+ 'NEMCR_ENEAM': '$40', # Enable Extended Address Mode f
+ 'NEMCR_AEAM': '$30', # Address for Extended Address M
+ 'BGCR' : '$67', # Reference Voltage Calibration
+ 'BGCR_Res': '$80', # Reserved Bit
+ 'BGCR_BGCAL_FINE': '$78', # Fine Calibration Bits
+ 'BGCR_BGCAL': '$7', # Coarse Calibration Bits
+
+# Module PWRCTRL
+ 'TRXPR' : '$139', # Transceiver Pin Register
+ 'TRXPR_Res': '$f0', # Reserved
+ 'TRXPR_SLPTR': '$2', # Multi-purpose Transceiver Cont
+ 'TRXPR_TRXRST': '$1', # Force Transceiver Reset
+ 'DRTRAM0' : '$135', # Data Retention Configuration R
+ 'DRTRAM0_Res': '$c0', # Reserved
+ 'DRTRAM0_DRTSWOK': '$20', # DRT Switch OK
+ 'DRTRAM0_ENDRT': '$10', # Enable SRAM Data Retention
+ 'DRTRAM1' : '$134', # Data Retention Configuration R
+ 'DRTRAM1_Res': '$c0', # Reserved
+ 'DRTRAM1_DRTSWOK': '$20', # DRT Switch OK
+ 'DRTRAM1_ENDRT': '$10', # Enable SRAM Data Retention
+ 'DRTRAM2' : '$133', # Data Retention Configuration R
+ 'DRTRAM2_Res': '$40', # Reserved Bit
+ 'DRTRAM2_DRTSWOK': '$20', # DRT Switch OK
+ 'DRTRAM2_ENDRT': '$10', # Enable SRAM Data Retention
+ 'DRTRAM3' : '$132', # Data Retention Configuration R
+ 'DRTRAM3_Res': '$c0', # Reserved
+ 'DRTRAM3_DRTSWOK': '$20', # DRT Switch OK
+ 'DRTRAM3_ENDRT': '$10', # Enable SRAM Data Retention
+ 'LLDRL' : '$130', # Low Leakage Voltage Regulator
+ 'LLDRL_Res': '$f0', # Reserved
+ 'LLDRL_LLDRL': '$f', # Low-Byte Data Register Bits
+ 'LLDRH' : '$131', # Low Leakage Voltage Regulator
+ 'LLDRH_Res': '$e0', # Reserved
+ 'LLDRH_LLDRH': '$1f', # High-Byte Data Register Bits
+ 'LLCR' : '$12f', # Low Leakage Voltage Regulator
+ 'LLCR_Res': '$c0', # Reserved Bit
+ 'LLCR_LLDONE': '$20', # Calibration Done
+ 'LLCR_LLCOMP': '$10', # Comparator Output
+ 'LLCR_LLCAL': '$8', # Calibration Active
+ 'LLCR_LLTCO': '$4', # Temperature Coefficient of Cur
+ 'LLCR_LLSHORT': '$2', # Short Lower Calibration Circui
+ 'LLCR_LLENCAL': '$1', # Enable Automatic Calibration
+ 'DPDS0' : '$136', # Port Driver Strength Register
+ 'DPDS0_PFDRV': '$c0', # Driver Strength Port F
+ 'DPDS0_PEDRV': '$30', # Driver Strength Port E
+ 'DPDS0_PDDRV': '$c', # Driver Strength Port D
+ 'DPDS0_PBDRV': '$3', # Driver Strength Port B
+ 'DPDS1' : '$137', # Port Driver Strength Register
+ 'DPDS1_Res': '$fc', # Reserved
+ 'DPDS1_PGDRV': '$3', # Driver Strength Port G
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_PUD': '$10', # Pull-up Disable
+
+# Module USART0_SPI
+ 'UCSR0A' : '$c0', # USART0 MSPIM Control and Statu
+ 'UCSR0A_RXC0': '$80', # USART Receive Complete
+ 'UCSR0A_TXC0': '$40', # USART Transmit Complete
+ 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
+ 'UCSR0B' : '$c1', # USART0 MSPIM Control and Statu
+ 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
+ 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
+ 'UCSR0B_UDRIE0': '$20', # USART Data Register Empty Inte
+ 'UCSR0B_RXEN0': '$10', # Receiver Enable
+ 'UCSR0B_TXEN0': '$8', # Transmitter Enable
+ 'UCSR0C' : '$c2', # USART0 MSPIM Control and Statu
+ 'UCSR0C_UDORD0': '$4', # Data Order
+ 'UCSR0C_UCPHA0': '$2', # Clock Phase
+ 'UCSR0C_UCPOL0': '$1', # Clock Polarity
+
+# Module USART1_SPI
+ 'UCSR1A' : '$c8', # USART1 MSPIM Control and Statu
+ 'UCSR1A_RXC1': '$80', # USART Receive Complete
+ 'UCSR1A_TXC1': '$40', # USART Transmit Complete
+ 'UCSR1A_UDRE1': '$20', # USART Data Register Empty
+ 'UCSR1B' : '$c9', # USART1 MSPIM Control and Statu
+ 'UCSR1B_RXCIE1': '$80', # RX Complete Interrupt Enable
+ 'UCSR1B_TXCIE1': '$40', # TX Complete Interrupt Enable
+ 'UCSR1B_UDRIE1': '$20', # USART Data Register Empty Inte
+ 'UCSR1B_RXEN1': '$10', # Receiver Enable
+ 'UCSR1B_TXEN1': '$8', # Transmitter Enable
+ 'UCSR1C' : '$ca', # USART1 MSPIM Control and Statu
+ 'UCSR1C_UDORD1': '$4', # Data Order
+ 'UCSR1C_UCPHA1': '$2', # Clock Phase
+ 'UCSR1C_UCPOL1': '$1', # Clock Polarity
+
+ '__amforth_dummy':'0'
+}
diff --git a/amforth-6.5/avr8/devices/atmega128rfa1/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega128rfa1/words/no-jtag.asm
new file mode 100644
index 0000000..352a4bb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega128rfa1/words/no-jtag.asm
@@ -0,0 +1,14 @@
+; ( -- )
+; ( -- )
+; MCU
+; disable jtag at runtime
+VE_NOJTAG:
+ .dw $FF05
+ .db "-jtag",0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOJTAG
+XT_NOJTAG:
+ .dw PFA_NOJTAG
+PFA_NOJTAG:
+
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega128rfa1/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega128rfa1/words/no-wdt.asm
new file mode 100644
index 0000000..ff6ddd1
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega128rfa1/words/no-wdt.asm
@@ -0,0 +1,34 @@
+; ( -- )
+; MCU
+; disable watch dog timer at runtime
+VE_NOWDT:
+ .dw $ff04
+ .db "-wdt"
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOWDT
+XT_NOWDT:
+ .dw PFA_NOWDT
+PFA_NOWDT:
+
+ in temp1,SREG
+ push temp1
+ ; Turn always off global interrupt.
+ cli
+ ; Reset Watchdog Timer
+ wdr
+ ; Clear WDRF in MCUSR
+ in temp1, MCUSR
+ andi temp1, (0xff & (0<<WDRF))
+ out MCUSR, temp1
+ ; Write logical one to WDCE and WDE
+ ; Keep old prescaler setting to prevent unintentional time-out
+ in_ temp1, WDTCSR
+ ori temp1, (1<<WDCE) | (1<<WDE)
+ out_ WDTCSR, temp1
+ ; Turn off WDT
+ ldi temp1, (0<<WDE)
+ out_ WDTCSR, temp1
+ ; restore status register
+ pop temp1
+ out SREG,temp1
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega128rfa1/words/sleep.asm b/amforth-6.5/avr8/devices/atmega128rfa1/words/sleep.asm
new file mode 100644
index 0000000..256249c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega128rfa1/words/sleep.asm
@@ -0,0 +1,19 @@
+; ( mode -- )
+; MCU
+; put the controller into the specified sleep mode
+VE_SLEEP:
+ .dw $ff05
+ .db "sleep", 0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_SLEEP
+XT_SLEEP:
+ .dw PFA_SLEEP
+PFA_SLEEP:
+ andi tosl, 7 ; leave only legal mode bits
+ lsl tosl ; move to correct location (bits 3-1)
+ ori tosl, 1 ; set the SE bit
+ out_ SMCR, tosl ; set the sleep config
+ sleep ; nighty-night
+ out_ SMCR, zerol ; 0 protects against accidental sleeps
+ loadtos ; pop argument from stack
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega128rfr2/blocks/AD_CONVERTER.frt b/amforth-6.5/avr8/devices/atmega128rfr2/blocks/AD_CONVERTER.frt
new file mode 100644
index 0000000..89b8933
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega128rfr2/blocks/AD_CONVERTER.frt
@@ -0,0 +1,79 @@
+\ Generated automatically for atmega128rfr2
+\ #require bitnames.frt
+
+\ AD_CONVERTER
+$7c constant ADMUX \ The ADC Multiplexer Selection
+ $c0 constant ADMUX_REFS \ Reference Selection Bits
+ 7c $c0 bitmask: ADMUX.REFS \ Reference Selection Bits
+ $20 constant ADMUX_ADLAR \ ADC Left Adjust Result
+ 7c $20 bitmask: ADMUX.ADLAR \ ADC Left Adjust Result
+ $1f constant ADMUX_MUX \ Analog Channel and Gain Select
+ 7c $1f bitmask: ADMUX.MUX \ Analog Channel and Gain Select
+$78 constant ADC \ ADC Data Register Bytes
+$7a constant ADCSRA \ The ADC Control and Status Reg
+ $80 constant ADCSRA_ADEN \ ADC Enable
+ 7a $80 bitmask: ADCSRA.ADEN \ ADC Enable
+ $40 constant ADCSRA_ADSC \ ADC Start Conversion
+ 7a $40 bitmask: ADCSRA.ADSC \ ADC Start Conversion
+ $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
+ 7a $20 bitmask: ADCSRA.ADATE \ ADC Auto Trigger Enable
+ $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
+ 7a $10 bitmask: ADCSRA.ADIF \ ADC Interrupt Flag
+ $8 constant ADCSRA_ADIE \ ADC Interrupt Enable
+ 7a $8 bitmask: ADCSRA.ADIE \ ADC Interrupt Enable
+ $7 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
+ 7a $7 bitmask: ADCSRA.ADPS \ ADC Prescaler Select Bits
+$7b constant ADCSRB \ The ADC Control and Status Reg
+ $80 constant ADCSRB_AVDDOK \ AVDD Supply Voltage OK
+ 7b $80 bitmask: ADCSRB.AVDDOK \ AVDD Supply Voltage OK
+ $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer
+ 7b $40 bitmask: ADCSRB.ACME \ Analog Comparator Multiplexer
+ $20 constant ADCSRB_REFOK \ Reference Voltage OK
+ 7b $20 bitmask: ADCSRB.REFOK \ Reference Voltage OK
+ $10 constant ADCSRB_ACCH \ Analog Channel Change
+ 7b $10 bitmask: ADCSRB.ACCH \ Analog Channel Change
+ $8 constant ADCSRB_MUX5 \ Analog Channel and Gain Select
+ 7b $8 bitmask: ADCSRB.MUX5 \ Analog Channel and Gain Select
+ $7 constant ADCSRB_ADTS \ ADC Auto Trigger Source
+ 7b $7 bitmask: ADCSRB.ADTS \ ADC Auto Trigger Source
+$77 constant ADCSRC \ The ADC Control and Status Reg
+ $c0 constant ADCSRC_ADTHT \ ADC Track-and-Hold Time
+ 77 $c0 bitmask: ADCSRC.ADTHT \ ADC Track-and-Hold Time
+ $20 constant ADCSRC_Res0 \ Reserved
+ 77 $20 bitmask: ADCSRC.Res0 \ Reserved
+ $1f constant ADCSRC_ADSUT \ ADC Start-up Time
+ 77 $1f bitmask: ADCSRC.ADSUT \ ADC Start-up Time
+$7d constant DIDR2 \ Digital Input Disable Register
+ $80 constant DIDR2_ADC15D \ Reserved Bits
+ 7d $80 bitmask: DIDR2.ADC15D \ Reserved Bits
+ $40 constant DIDR2_ADC14D \ Reserved Bits
+ 7d $40 bitmask: DIDR2.ADC14D \ Reserved Bits
+ $20 constant DIDR2_ADC13D \ Reserved Bits
+ 7d $20 bitmask: DIDR2.ADC13D \ Reserved Bits
+ $10 constant DIDR2_ADC12D \ Reserved Bits
+ 7d $10 bitmask: DIDR2.ADC12D \ Reserved Bits
+ $8 constant DIDR2_ADC11D \ Reserved Bits
+ 7d $8 bitmask: DIDR2.ADC11D \ Reserved Bits
+ $4 constant DIDR2_ADC10D \ Reserved Bits
+ 7d $4 bitmask: DIDR2.ADC10D \ Reserved Bits
+ $2 constant DIDR2_ADC9D \ Reserved Bits
+ 7d $2 bitmask: DIDR2.ADC9D \ Reserved Bits
+ $1 constant DIDR2_ADC8D \ Reserved Bits
+ 7d $1 bitmask: DIDR2.ADC8D \ Reserved Bits
+$7e constant DIDR0 \ Digital Input Disable Register
+ $80 constant DIDR0_ADC7D \ Disable ADC7:0 Digital Input
+ 7e $80 bitmask: DIDR0.ADC7D \ Disable ADC7:0 Digital Input
+ $40 constant DIDR0_ADC6D \ Disable ADC7:0 Digital Input
+ 7e $40 bitmask: DIDR0.ADC6D \ Disable ADC7:0 Digital Input
+ $20 constant DIDR0_ADC5D \ Disable ADC7:0 Digital Input
+ 7e $20 bitmask: DIDR0.ADC5D \ Disable ADC7:0 Digital Input
+ $10 constant DIDR0_ADC4D \ Disable ADC7:0 Digital Input
+ 7e $10 bitmask: DIDR0.ADC4D \ Disable ADC7:0 Digital Input
+ $8 constant DIDR0_ADC3D \ Disable ADC7:0 Digital Input
+ 7e $8 bitmask: DIDR0.ADC3D \ Disable ADC7:0 Digital Input
+ $4 constant DIDR0_ADC2D \ Disable ADC7:0 Digital Input
+ 7e $4 bitmask: DIDR0.ADC2D \ Disable ADC7:0 Digital Input
+ $2 constant DIDR0_ADC1D \ Disable ADC7:0 Digital Input
+ 7e $2 bitmask: DIDR0.ADC1D \ Disable ADC7:0 Digital Input
+ $1 constant DIDR0_ADC0D \ Disable ADC7:0 Digital Input
+ 7e $1 bitmask: DIDR0.ADC0D \ Disable ADC7:0 Digital Input
diff --git a/amforth-6.5/avr8/devices/atmega128rfr2/blocks/ANALOG_COMPARATOR.frt b/amforth-6.5/avr8/devices/atmega128rfr2/blocks/ANALOG_COMPARATOR.frt
new file mode 100644
index 0000000..d93c680
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega128rfr2/blocks/ANALOG_COMPARATOR.frt
@@ -0,0 +1,27 @@
+\ Generated automatically for atmega128rfr2
+\ #require bitnames.frt
+
+\ ANALOG_COMPARATOR
+$7b constant ADCSRB \ ADC Control and Status Registe
+ $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer
+ 7b $40 bitmask: ADCSRB.ACME \ Analog Comparator Multiplexer
+$50 constant ACSR \ Analog Comparator Control And
+ $80 constant ACSR_ACD \ Analog Comparator Disable
+ 50 $80 bitmask: ACSR.ACD \ Analog Comparator Disable
+ $40 constant ACSR_ACBG \ Analog Comparator Bandgap Sele
+ 50 $40 bitmask: ACSR.ACBG \ Analog Comparator Bandgap Sele
+ $20 constant ACSR_ACO \ Analog Compare Output
+ 50 $20 bitmask: ACSR.ACO \ Analog Compare Output
+ $10 constant ACSR_ACI \ Analog Comparator Interrupt Fl
+ 50 $10 bitmask: ACSR.ACI \ Analog Comparator Interrupt Fl
+ $8 constant ACSR_ACIE \ Analog Comparator Interrupt En
+ 50 $8 bitmask: ACSR.ACIE \ Analog Comparator Interrupt En
+ $4 constant ACSR_ACIC \ Analog Comparator Input Captur
+ 50 $4 bitmask: ACSR.ACIC \ Analog Comparator Input Captur
+ $3 constant ACSR_ACIS \ Analog Comparator Interrupt Mo
+ 50 $3 bitmask: ACSR.ACIS \ Analog Comparator Interrupt Mo
+$7f constant DIDR1 \ Digital Input Disable Register
+ $2 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
+ 7f $2 bitmask: DIDR1.AIN1D \ AIN1 Digital Input Disable
+ $1 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
+ 7f $1 bitmask: DIDR1.AIN0D \ AIN0 Digital Input Disable
diff --git a/amforth-6.5/avr8/devices/atmega128rfr2/blocks/BOOT_LOAD.frt b/amforth-6.5/avr8/devices/atmega128rfr2/blocks/BOOT_LOAD.frt
new file mode 100644
index 0000000..20127b2
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega128rfr2/blocks/BOOT_LOAD.frt
@@ -0,0 +1,21 @@
+\ Generated automatically for atmega128rfr2
+\ #require bitnames.frt
+
+\ BOOT_LOAD
+$57 constant SPMCSR \ Store Program Memory Control R
+ $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
+ 57 $80 bitmask: SPMCSR.SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
+ 57 $40 bitmask: SPMCSR.RWWSB \ Read While Write Section Busy
+ $20 constant SPMCSR_SIGRD \ Signature Row Read
+ 57 $20 bitmask: SPMCSR.SIGRD \ Signature Row Read
+ $10 constant SPMCSR_RWWSRE \ Read While Write Section Read
+ 57 $10 bitmask: SPMCSR.RWWSRE \ Read While Write Section Read
+ $8 constant SPMCSR_BLBSET \ Boot Lock Bit Set
+ 57 $8 bitmask: SPMCSR.BLBSET \ Boot Lock Bit Set
+ $4 constant SPMCSR_PGWRT \ Page Write
+ 57 $4 bitmask: SPMCSR.PGWRT \ Page Write
+ $2 constant SPMCSR_PGERS \ Page Erase
+ 57 $2 bitmask: SPMCSR.PGERS \ Page Erase
+ $1 constant SPMCSR_SPMEN \ Store Program Memory Enable
+ 57 $1 bitmask: SPMCSR.SPMEN \ Store Program Memory Enable
diff --git a/amforth-6.5/avr8/devices/atmega128rfr2/blocks/CPU.frt b/amforth-6.5/avr8/devices/atmega128rfr2/blocks/CPU.frt
new file mode 100644
index 0000000..311193c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega128rfr2/blocks/CPU.frt
@@ -0,0 +1,128 @@
+\ Generated automatically for atmega128rfr2
+\ #require bitnames.frt
+
+\ CPU
+$5f constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ 5f $80 bitmask: SREG.I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ 5f $40 bitmask: SREG.T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ 5f $20 bitmask: SREG.H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ 5f $10 bitmask: SREG.S \ Sign Bit
+ $8 constant SREG_V \ Two's Complement Overflow Flag
+ 5f $8 bitmask: SREG.V \ Two's Complement Overflow Flag
+ $4 constant SREG_N \ Negative Flag
+ 5f $4 bitmask: SREG.N \ Negative Flag
+ $2 constant SREG_Z \ Zero Flag
+ 5f $2 bitmask: SREG.Z \ Zero Flag
+ $1 constant SREG_C \ Carry Flag
+ 5f $1 bitmask: SREG.C \ Carry Flag
+$5d constant SP \ Stack Pointer
+$55 constant MCUCR \ MCU Control Register
+ $80 constant MCUCR_JTD \ JTAG Interface Disable
+ 55 $80 bitmask: MCUCR.JTD \ JTAG Interface Disable
+ $60 constant MCUCR_Res \ Reserved
+ 55 $60 bitmask: MCUCR.Res \ Reserved
+ $10 constant MCUCR_PUD \ Pull-up Disable
+ 55 $10 bitmask: MCUCR.PUD \ Pull-up Disable
+ $c constant MCUCR_Res \ Reserved
+ 55 $c bitmask: MCUCR.Res \ Reserved
+ $2 constant MCUCR_IVSEL \ Interrupt Vector Select
+ 55 $2 bitmask: MCUCR.IVSEL \ Interrupt Vector Select
+ $1 constant MCUCR_IVCE \ Interrupt Vector Change Enable
+ 55 $1 bitmask: MCUCR.IVCE \ Interrupt Vector Change Enable
+$54 constant MCUSR \ MCU Status Register
+ $e0 constant MCUSR_Res \ Reserved
+ 54 $e0 bitmask: MCUSR.Res \ Reserved
+ $10 constant MCUSR_JTRF \ JTAG Reset Flag
+ 54 $10 bitmask: MCUSR.JTRF \ JTAG Reset Flag
+ $8 constant MCUSR_WDRF \ Watchdog Reset Flag
+ 54 $8 bitmask: MCUSR.WDRF \ Watchdog Reset Flag
+ $4 constant MCUSR_BORF \ Brown-out Reset Flag
+ 54 $4 bitmask: MCUSR.BORF \ Brown-out Reset Flag
+ $2 constant MCUSR_EXTRF \ External Reset Flag
+ 54 $2 bitmask: MCUSR.EXTRF \ External Reset Flag
+ $1 constant MCUSR_PORF \ Power-on Reset Flag
+ 54 $1 bitmask: MCUSR.PORF \ Power-on Reset Flag
+$66 constant OSCCAL \ Oscillator Calibration Value
+ $ff constant OSCCAL_CAL \ Oscillator Calibration Tuning
+ 66 $ff bitmask: OSCCAL.CAL \ Oscillator Calibration Tuning
+$61 constant CLKPR \ Clock Prescale Register
+ $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable
+ 61 $80 bitmask: CLKPR.CLKPCE \ Clock Prescaler Change Enable
+ $70 constant CLKPR_Res \ Reserved
+ 61 $70 bitmask: CLKPR.Res \ Reserved
+ $f constant CLKPR_CLKPS \ Clock Prescaler Select Bits
+ 61 $f bitmask: CLKPR.CLKPS \ Clock Prescaler Select Bits
+$53 constant SMCR \ Sleep Mode Control Register
+ $f0 constant SMCR_Res \ Reserved
+ 53 $f0 bitmask: SMCR.Res \ Reserved
+ $e constant SMCR_SM \ Sleep Mode Select bits
+ 53 $e bitmask: SMCR.SM \ Sleep Mode Select bits
+ $1 constant SMCR_SE \ Sleep Enable
+ 53 $1 bitmask: SMCR.SE \ Sleep Enable
+$5b constant RAMPZ \ Extended Z-pointer Register fo
+ $fe constant RAMPZ_Res \ Reserved
+ 5b $fe bitmask: RAMPZ.Res \ Reserved
+ $1 constant RAMPZ_RAMPZ0 \ Extended Z-Pointer Value
+ 5b $1 bitmask: RAMPZ.RAMPZ0 \ Extended Z-Pointer Value
+$4b constant GPIOR2 \ General Purpose I/O Register 2
+ $ff constant GPIOR2_GPIOR \ General Purpose I/O Register 2
+ 4b $ff bitmask: GPIOR2.GPIOR \ General Purpose I/O Register 2
+$4a constant GPIOR1 \ General Purpose IO Register 1
+ $ff constant GPIOR1_GPIOR \ General Purpose I/O Register 1
+ 4a $ff bitmask: GPIOR1.GPIOR \ General Purpose I/O Register 1
+$3e constant GPIOR0 \ General Purpose IO Register 0
+ $80 constant GPIOR0_GPIOR07 \ General Purpose I/O Register 0
+ 3e $80 bitmask: GPIOR0.GPIOR07 \ General Purpose I/O Register 0
+ $40 constant GPIOR0_GPIOR06 \ General Purpose I/O Register 0
+ 3e $40 bitmask: GPIOR0.GPIOR06 \ General Purpose I/O Register 0
+ $20 constant GPIOR0_GPIOR05 \ General Purpose I/O Register 0
+ 3e $20 bitmask: GPIOR0.GPIOR05 \ General Purpose I/O Register 0
+ $10 constant GPIOR0_GPIOR04 \ General Purpose I/O Register 0
+ 3e $10 bitmask: GPIOR0.GPIOR04 \ General Purpose I/O Register 0
+ $8 constant GPIOR0_GPIOR03 \ General Purpose I/O Register 0
+ 3e $8 bitmask: GPIOR0.GPIOR03 \ General Purpose I/O Register 0
+ $4 constant GPIOR0_GPIOR02 \ General Purpose I/O Register 0
+ 3e $4 bitmask: GPIOR0.GPIOR02 \ General Purpose I/O Register 0
+ $2 constant GPIOR0_GPIOR01 \ General Purpose I/O Register 0
+ 3e $2 bitmask: GPIOR0.GPIOR01 \ General Purpose I/O Register 0
+ $1 constant GPIOR0_GPIOR00 \ General Purpose I/O Register 0
+ 3e $1 bitmask: GPIOR0.GPIOR00 \ General Purpose I/O Register 0
+$63 constant PRR2 \ Power Reduction Register 2
+ $f0 constant PRR2_Res \ Reserved Bit
+ 63 $f0 bitmask: PRR2.Res \ Reserved Bit
+ $f constant PRR2_PRRAM \ Power Reduction SRAMs
+ 63 $f bitmask: PRR2.PRRAM \ Power Reduction SRAMs
+$65 constant PRR1 \ Power Reduction Register 1
+ $80 constant PRR1_Res \ Reserved Bit
+ 65 $80 bitmask: PRR1.Res \ Reserved Bit
+ $40 constant PRR1_PRTRX24 \ Power Reduction Transceiver
+ 65 $40 bitmask: PRR1.PRTRX24 \ Power Reduction Transceiver
+ $20 constant PRR1_PRTIM5 \ Power Reduction Timer/Counter5
+ 65 $20 bitmask: PRR1.PRTIM5 \ Power Reduction Timer/Counter5
+ $10 constant PRR1_PRTIM4 \ Power Reduction Timer/Counter4
+ 65 $10 bitmask: PRR1.PRTIM4 \ Power Reduction Timer/Counter4
+ $8 constant PRR1_PRTIM3 \ Power Reduction Timer/Counter3
+ 65 $8 bitmask: PRR1.PRTIM3 \ Power Reduction Timer/Counter3
+ $1 constant PRR1_PRUSART1 \ Power Reduction USART1
+ 65 $1 bitmask: PRR1.PRUSART1 \ Power Reduction USART1
+$64 constant PRR0 \ Power Reduction Register0
+ $80 constant PRR0_PRTWI \ Power Reduction TWI
+ 64 $80 bitmask: PRR0.PRTWI \ Power Reduction TWI
+ $40 constant PRR0_PRTIM2 \ Power Reduction Timer/Counter2
+ 64 $40 bitmask: PRR0.PRTIM2 \ Power Reduction Timer/Counter2
+ $20 constant PRR0_PRTIM0 \ Power Reduction Timer/Counter0
+ 64 $20 bitmask: PRR0.PRTIM0 \ Power Reduction Timer/Counter0
+ $10 constant PRR0_PRPGA \ Power Reduction PGA
+ 64 $10 bitmask: PRR0.PRPGA \ Power Reduction PGA
+ $8 constant PRR0_PRTIM1 \ Power Reduction Timer/Counter1
+ 64 $8 bitmask: PRR0.PRTIM1 \ Power Reduction Timer/Counter1
+ $4 constant PRR0_PRSPI \ Power Reduction Serial Periphe
+ 64 $4 bitmask: PRR0.PRSPI \ Power Reduction Serial Periphe
+ $2 constant PRR0_PRUSART0 \ Power Reduction USART
+ 64 $2 bitmask: PRR0.PRUSART0 \ Power Reduction USART
+ $1 constant PRR0_PRADC \ Power Reduction ADC
+ 64 $1 bitmask: PRR0.PRADC \ Power Reduction ADC
diff --git a/amforth-6.5/avr8/devices/atmega128rfr2/blocks/EEPROM.frt b/amforth-6.5/avr8/devices/atmega128rfr2/blocks/EEPROM.frt
new file mode 100644
index 0000000..b2d892c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega128rfr2/blocks/EEPROM.frt
@@ -0,0 +1,19 @@
+\ Generated automatically for atmega128rfr2
+\ #require bitnames.frt
+
+\ EEPROM
+$41 constant EEAR \ EEPROM Address Register Bytes
+$40 constant EEDR \ EEPROM Data Register
+$3f constant EECR \ EEPROM Control Register
+ $c0 constant EECR_Res \ Reserved
+ 3f $c0 bitmask: EECR.Res \ Reserved
+ $30 constant EECR_EEPM \ EEPROM Programming Mode
+ 3f $30 bitmask: EECR.EEPM \ EEPROM Programming Mode
+ $8 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
+ 3f $8 bitmask: EECR.EERIE \ EEPROM Ready Interrupt Enable
+ $4 constant EECR_EEMPE \ EEPROM Master Write Enable
+ 3f $4 bitmask: EECR.EEMPE \ EEPROM Master Write Enable
+ $2 constant EECR_EEPE \ EEPROM Programming Enable
+ 3f $2 bitmask: EECR.EEPE \ EEPROM Programming Enable
+ $1 constant EECR_EERE \ EEPROM Read Enable
+ 3f $1 bitmask: EECR.EERE \ EEPROM Read Enable
diff --git a/amforth-6.5/avr8/devices/atmega128rfr2/blocks/EXTERNAL_INTERRUPT.frt b/amforth-6.5/avr8/devices/atmega128rfr2/blocks/EXTERNAL_INTERRUPT.frt
new file mode 100644
index 0000000..0bda9c6
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega128rfr2/blocks/EXTERNAL_INTERRUPT.frt
@@ -0,0 +1,45 @@
+\ Generated automatically for atmega128rfr2
+\ #require bitnames.frt
+
+\ EXTERNAL_INTERRUPT
+$69 constant EICRA \ External Interrupt Control Reg
+ $c0 constant EICRA_ISC3 \ External Interrupt 3 Sense Con
+ 69 $c0 bitmask: EICRA.ISC3 \ External Interrupt 3 Sense Con
+ $30 constant EICRA_ISC2 \ External Interrupt 2 Sense Con
+ 69 $30 bitmask: EICRA.ISC2 \ External Interrupt 2 Sense Con
+ $c constant EICRA_ISC1 \ External Interrupt 1 Sense Con
+ 69 $c bitmask: EICRA.ISC1 \ External Interrupt 1 Sense Con
+ $3 constant EICRA_ISC0 \ External Interrupt 0 Sense Con
+ 69 $3 bitmask: EICRA.ISC0 \ External Interrupt 0 Sense Con
+$6a constant EICRB \ External Interrupt Control Reg
+ $c0 constant EICRB_ISC7 \ External Interrupt 7 Sense Con
+ 6a $c0 bitmask: EICRB.ISC7 \ External Interrupt 7 Sense Con
+ $30 constant EICRB_ISC6 \ External Interrupt 6 Sense Con
+ 6a $30 bitmask: EICRB.ISC6 \ External Interrupt 6 Sense Con
+ $c constant EICRB_ISC5 \ External Interrupt 5 Sense Con
+ 6a $c bitmask: EICRB.ISC5 \ External Interrupt 5 Sense Con
+ $3 constant EICRB_ISC4 \ External Interrupt 4 Sense Con
+ 6a $3 bitmask: EICRB.ISC4 \ External Interrupt 4 Sense Con
+$3d constant EIMSK \ External Interrupt Mask Regist
+ $ff constant EIMSK_INT \ External Interrupt Request Ena
+ 3d $ff bitmask: EIMSK.INT \ External Interrupt Request Ena
+$3c constant EIFR \ External Interrupt Flag Regist
+ $ff constant EIFR_INTF \ External Interrupt Flag
+ 3c $ff bitmask: EIFR.INTF \ External Interrupt Flag
+$6d constant PCMSK2 \ Pin Change Mask Register 2
+ $ff constant PCMSK2_PCINT \ Pin Change Enable Mask
+ 6d $ff bitmask: PCMSK2.PCINT \ Pin Change Enable Mask
+$6c constant PCMSK1 \ Pin Change Mask Register 1
+ $ff constant PCMSK1_PCINT \ Pin Change Enable Mask
+ 6c $ff bitmask: PCMSK1.PCINT \ Pin Change Enable Mask
+$6b constant PCMSK0 \ Pin Change Mask Register 0
+$3b constant PCIFR \ Pin Change Interrupt Flag Regi
+ $f8 constant PCIFR_Res \ Reserved Bit
+ 3b $f8 bitmask: PCIFR.Res \ Reserved Bit
+ $7 constant PCIFR_PCIF \ Pin Change Interrupt Flags
+ 3b $7 bitmask: PCIFR.PCIF \ Pin Change Interrupt Flags
+$68 constant PCICR \ Pin Change Interrupt Control R
+ $f8 constant PCICR_Res \ Reserved Bit
+ 68 $f8 bitmask: PCICR.Res \ Reserved Bit
+ $7 constant PCICR_PCIE \ Pin Change Interrupt Enables
+ 68 $7 bitmask: PCICR.PCIE \ Pin Change Interrupt Enables
diff --git a/amforth-6.5/avr8/devices/atmega128rfr2/blocks/FLASH.frt b/amforth-6.5/avr8/devices/atmega128rfr2/blocks/FLASH.frt
new file mode 100644
index 0000000..0b34424
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega128rfr2/blocks/FLASH.frt
@@ -0,0 +1,16 @@
+\ Generated automatically for atmega128rfr2
+\ #require bitnames.frt
+
+\ FLASH
+$75 constant NEMCR \ Flash Extended-Mode Control-Re
+ $40 constant NEMCR_ENEAM \ Enable Extended Address Mode f
+ 75 $40 bitmask: NEMCR.ENEAM \ Enable Extended Address Mode f
+ $30 constant NEMCR_AEAM \ Address for Extended Address M
+ 75 $30 bitmask: NEMCR.AEAM \ Address for Extended Address M
+$67 constant BGCR \ Reference Voltage Calibration
+ $80 constant BGCR_Res \ Reserved Bit
+ 67 $80 bitmask: BGCR.Res \ Reserved Bit
+ $78 constant BGCR_BGCAL_FINE \ Fine Calibration Bits
+ 67 $78 bitmask: BGCR.BGCAL_FINE \ Fine Calibration Bits
+ $7 constant BGCR_BGCAL \ Coarse Calibration Bits
+ 67 $7 bitmask: BGCR.BGCAL \ Coarse Calibration Bits
diff --git a/amforth-6.5/avr8/devices/atmega128rfr2/blocks/JTAG.frt b/amforth-6.5/avr8/devices/atmega128rfr2/blocks/JTAG.frt
new file mode 100644
index 0000000..8179040
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega128rfr2/blocks/JTAG.frt
@@ -0,0 +1,13 @@
+\ Generated automatically for atmega128rfr2
+\ #require bitnames.frt
+
+\ JTAG
+$51 constant OCDR \ On-Chip Debug Register
+ $ff constant OCDR_OCDR \ On-Chip Debug Register Data
+ 51 $ff bitmask: OCDR.OCDR \ On-Chip Debug Register Data
+$55 constant MCUCR \ MCU Control Register
+ $80 constant MCUCR_JTD \ JTAG Interface Disable
+ 55 $80 bitmask: MCUCR.JTD \ JTAG Interface Disable
+$54 constant MCUSR \ MCU Status Register
+ $10 constant MCUSR_JTRF \ JTAG Reset Flag
+ 54 $10 bitmask: MCUSR.JTRF \ JTAG Reset Flag
diff --git a/amforth-6.5/avr8/devices/atmega128rfr2/blocks/PORTA.frt b/amforth-6.5/avr8/devices/atmega128rfr2/blocks/PORTA.frt
new file mode 100644
index 0000000..65e46f6
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega128rfr2/blocks/PORTA.frt
@@ -0,0 +1,7 @@
+\ Generated automatically for atmega128rfr2
+\ #require bitnames.frt
+
+\ PORTA
+$22 constant PORTA \ Port A Data Register
+$21 constant DDRA \ Port A Data Direction Register
+$20 constant PINA \ Port A Input Pins Address
diff --git a/amforth-6.5/avr8/devices/atmega128rfr2/blocks/PORTB.frt b/amforth-6.5/avr8/devices/atmega128rfr2/blocks/PORTB.frt
new file mode 100644
index 0000000..b001eab
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega128rfr2/blocks/PORTB.frt
@@ -0,0 +1,7 @@
+\ Generated automatically for atmega128rfr2
+\ #require bitnames.frt
+
+\ PORTB
+$25 constant PORTB \ Port B Data Register
+$24 constant DDRB \ Port B Data Direction Register
+$23 constant PINB \ Port B Input Pins Address
diff --git a/amforth-6.5/avr8/devices/atmega128rfr2/blocks/PORTC.frt b/amforth-6.5/avr8/devices/atmega128rfr2/blocks/PORTC.frt
new file mode 100644
index 0000000..7205bbc
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega128rfr2/blocks/PORTC.frt
@@ -0,0 +1,7 @@
+\ Generated automatically for atmega128rfr2
+\ #require bitnames.frt
+
+\ PORTC
+$28 constant PORTC \ Port C Data Register
+$27 constant DDRC \ Port C Data Direction Register
+$26 constant PINC \ Port C Input Pins Address
diff --git a/amforth-6.5/avr8/devices/atmega128rfr2/blocks/PORTD.frt b/amforth-6.5/avr8/devices/atmega128rfr2/blocks/PORTD.frt
new file mode 100644
index 0000000..075c075
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega128rfr2/blocks/PORTD.frt
@@ -0,0 +1,7 @@
+\ Generated automatically for atmega128rfr2
+\ #require bitnames.frt
+
+\ PORTD
+$2b constant PORTD \ Port D Data Register
+$2a constant DDRD \ Port D Data Direction Register
+$29 constant PIND \ Port D Input Pins Address
diff --git a/amforth-6.5/avr8/devices/atmega128rfr2/blocks/PORTE.frt b/amforth-6.5/avr8/devices/atmega128rfr2/blocks/PORTE.frt
new file mode 100644
index 0000000..f1aee5d
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega128rfr2/blocks/PORTE.frt
@@ -0,0 +1,7 @@
+\ Generated automatically for atmega128rfr2
+\ #require bitnames.frt
+
+\ PORTE
+$2e constant PORTE \ Port E Data Register
+$2d constant DDRE \ Port E Data Direction Register
+$2c constant PINE \ Port E Input Pins Address
diff --git a/amforth-6.5/avr8/devices/atmega128rfr2/blocks/PORTF.frt b/amforth-6.5/avr8/devices/atmega128rfr2/blocks/PORTF.frt
new file mode 100644
index 0000000..d153c62
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega128rfr2/blocks/PORTF.frt
@@ -0,0 +1,7 @@
+\ Generated automatically for atmega128rfr2
+\ #require bitnames.frt
+
+\ PORTF
+$31 constant PORTF \ Port F Data Register
+$30 constant DDRF \ Port F Data Direction Register
+$2f constant PINF \ Port F Input Pins Address
diff --git a/amforth-6.5/avr8/devices/atmega128rfr2/blocks/PORTG.frt b/amforth-6.5/avr8/devices/atmega128rfr2/blocks/PORTG.frt
new file mode 100644
index 0000000..9f0cbf5
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega128rfr2/blocks/PORTG.frt
@@ -0,0 +1,7 @@
+\ Generated automatically for atmega128rfr2
+\ #require bitnames.frt
+
+\ PORTG
+$34 constant PORTG \ Port G Data Register
+$33 constant DDRG \ Port G Data Direction Register
+$32 constant PING \ Port G Input Pins Address
diff --git a/amforth-6.5/avr8/devices/atmega128rfr2/blocks/PWRCTRL.frt b/amforth-6.5/avr8/devices/atmega128rfr2/blocks/PWRCTRL.frt
new file mode 100644
index 0000000..ab5d139
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega128rfr2/blocks/PWRCTRL.frt
@@ -0,0 +1,81 @@
+\ Generated automatically for atmega128rfr2
+\ #require bitnames.frt
+
+\ PWRCTRL
+$139 constant TRXPR \ Transceiver Pin Register
+ $f0 constant TRXPR_Res \ Reserved
+ 139 $f0 bitmask: TRXPR.Res \ Reserved
+ $2 constant TRXPR_SLPTR \ Multi-purpose Transceiver Cont
+ 139 $2 bitmask: TRXPR.SLPTR \ Multi-purpose Transceiver Cont
+ $1 constant TRXPR_TRXRST \ Force Transceiver Reset
+ 139 $1 bitmask: TRXPR.TRXRST \ Force Transceiver Reset
+$135 constant DRTRAM0 \ Data Retention Configuration R
+ $c0 constant DRTRAM0_Res \ Reserved
+ 135 $c0 bitmask: DRTRAM0.Res \ Reserved
+ $20 constant DRTRAM0_DRTSWOK \ DRT Switch OK
+ 135 $20 bitmask: DRTRAM0.DRTSWOK \ DRT Switch OK
+ $10 constant DRTRAM0_ENDRT \ Enable SRAM Data Retention
+ 135 $10 bitmask: DRTRAM0.ENDRT \ Enable SRAM Data Retention
+$134 constant DRTRAM1 \ Data Retention Configuration R
+ $c0 constant DRTRAM1_Res \ Reserved
+ 134 $c0 bitmask: DRTRAM1.Res \ Reserved
+ $20 constant DRTRAM1_DRTSWOK \ DRT Switch OK
+ 134 $20 bitmask: DRTRAM1.DRTSWOK \ DRT Switch OK
+ $10 constant DRTRAM1_ENDRT \ Enable SRAM Data Retention
+ 134 $10 bitmask: DRTRAM1.ENDRT \ Enable SRAM Data Retention
+$133 constant DRTRAM2 \ Data Retention Configuration R
+ $40 constant DRTRAM2_Res \ Reserved Bit
+ 133 $40 bitmask: DRTRAM2.Res \ Reserved Bit
+ $20 constant DRTRAM2_DRTSWOK \ DRT Switch OK
+ 133 $20 bitmask: DRTRAM2.DRTSWOK \ DRT Switch OK
+ $10 constant DRTRAM2_ENDRT \ Enable SRAM Data Retention
+ 133 $10 bitmask: DRTRAM2.ENDRT \ Enable SRAM Data Retention
+$132 constant DRTRAM3 \ Data Retention Configuration R
+ $c0 constant DRTRAM3_Res \ Reserved
+ 132 $c0 bitmask: DRTRAM3.Res \ Reserved
+ $20 constant DRTRAM3_DRTSWOK \ DRT Switch OK
+ 132 $20 bitmask: DRTRAM3.DRTSWOK \ DRT Switch OK
+ $10 constant DRTRAM3_ENDRT \ Enable SRAM Data Retention
+ 132 $10 bitmask: DRTRAM3.ENDRT \ Enable SRAM Data Retention
+$130 constant LLDRL \ Low Leakage Voltage Regulator
+ $f0 constant LLDRL_Res \ Reserved
+ 130 $f0 bitmask: LLDRL.Res \ Reserved
+ $f constant LLDRL_LLDRL \ Low-Byte Data Register Bits
+ 130 $f bitmask: LLDRL.LLDRL \ Low-Byte Data Register Bits
+$131 constant LLDRH \ Low Leakage Voltage Regulator
+ $e0 constant LLDRH_Res \ Reserved
+ 131 $e0 bitmask: LLDRH.Res \ Reserved
+ $1f constant LLDRH_LLDRH \ High-Byte Data Register Bits
+ 131 $1f bitmask: LLDRH.LLDRH \ High-Byte Data Register Bits
+$12f constant LLCR \ Low Leakage Voltage Regulator
+ $c0 constant LLCR_Res \ Reserved Bit
+ 12f $c0 bitmask: LLCR.Res \ Reserved Bit
+ $20 constant LLCR_LLDONE \ Calibration Done
+ 12f $20 bitmask: LLCR.LLDONE \ Calibration Done
+ $10 constant LLCR_LLCOMP \ Comparator Output
+ 12f $10 bitmask: LLCR.LLCOMP \ Comparator Output
+ $8 constant LLCR_LLCAL \ Calibration Active
+ 12f $8 bitmask: LLCR.LLCAL \ Calibration Active
+ $4 constant LLCR_LLTCO \ Temperature Coefficient of Cur
+ 12f $4 bitmask: LLCR.LLTCO \ Temperature Coefficient of Cur
+ $2 constant LLCR_LLSHORT \ Short Lower Calibration Circui
+ 12f $2 bitmask: LLCR.LLSHORT \ Short Lower Calibration Circui
+ $1 constant LLCR_LLENCAL \ Enable Automatic Calibration
+ 12f $1 bitmask: LLCR.LLENCAL \ Enable Automatic Calibration
+$136 constant DPDS0 \ Port Driver Strength Register
+ $c0 constant DPDS0_PFDRV \ Driver Strength Port F
+ 136 $c0 bitmask: DPDS0.PFDRV \ Driver Strength Port F
+ $30 constant DPDS0_PEDRV \ Driver Strength Port E
+ 136 $30 bitmask: DPDS0.PEDRV \ Driver Strength Port E
+ $c constant DPDS0_PDDRV \ Driver Strength Port D
+ 136 $c bitmask: DPDS0.PDDRV \ Driver Strength Port D
+ $3 constant DPDS0_PBDRV \ Driver Strength Port B
+ 136 $3 bitmask: DPDS0.PBDRV \ Driver Strength Port B
+$137 constant DPDS1 \ Port Driver Strength Register
+ $fc constant DPDS1_Res \ Reserved
+ 137 $fc bitmask: DPDS1.Res \ Reserved
+ $3 constant DPDS1_PGDRV \ Driver Strength Port G
+ 137 $3 bitmask: DPDS1.PGDRV \ Driver Strength Port G
+$55 constant MCUCR \ MCU Control Register
+ $10 constant MCUCR_PUD \ Pull-up Disable
+ 55 $10 bitmask: MCUCR.PUD \ Pull-up Disable
diff --git a/amforth-6.5/avr8/devices/atmega128rfr2/blocks/SPI.frt b/amforth-6.5/avr8/devices/atmega128rfr2/blocks/SPI.frt
new file mode 100644
index 0000000..5380282
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega128rfr2/blocks/SPI.frt
@@ -0,0 +1,29 @@
+\ Generated automatically for atmega128rfr2
+\ #require bitnames.frt
+
+\ SPI
+$4c constant SPCR \ SPI Control Register
+ $80 constant SPCR_SPIE \ SPI Interrupt Enable
+ 4c $80 bitmask: SPCR.SPIE \ SPI Interrupt Enable
+ $40 constant SPCR_SPE \ SPI Enable
+ 4c $40 bitmask: SPCR.SPE \ SPI Enable
+ $20 constant SPCR_DORD \ Data Order
+ 4c $20 bitmask: SPCR.DORD \ Data Order
+ $10 constant SPCR_MSTR \ Master/Slave Select
+ 4c $10 bitmask: SPCR.MSTR \ Master/Slave Select
+ $8 constant SPCR_CPOL \ Clock polarity
+ 4c $8 bitmask: SPCR.CPOL \ Clock polarity
+ $4 constant SPCR_CPHA \ Clock Phase
+ 4c $4 bitmask: SPCR.CPHA \ Clock Phase
+ $3 constant SPCR_SPR \ SPI Clock Rate Select 1 and 0
+ 4c $3 bitmask: SPCR.SPR \ SPI Clock Rate Select 1 and 0
+$4d constant SPSR \ SPI Status Register
+ $80 constant SPSR_SPIF \ SPI Interrupt Flag
+ 4d $80 bitmask: SPSR.SPIF \ SPI Interrupt Flag
+ $40 constant SPSR_WCOL \ Write Collision Flag
+ 4d $40 bitmask: SPSR.WCOL \ Write Collision Flag
+ $3e constant SPSR_Res \ Reserved
+ 4d $3e bitmask: SPSR.Res \ Reserved
+ $1 constant SPSR_SPI2X \ Double SPI Speed Bit
+ 4d $1 bitmask: SPSR.SPI2X \ Double SPI Speed Bit
+$4e constant SPDR \ SPI Data Register
diff --git a/amforth-6.5/avr8/devices/atmega128rfr2/blocks/SYMCNT.frt b/amforth-6.5/avr8/devices/atmega128rfr2/blocks/SYMCNT.frt
new file mode 100644
index 0000000..3f52468
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega128rfr2/blocks/SYMCNT.frt
@@ -0,0 +1,156 @@
+\ Generated automatically for atmega128rfr2
+\ #require bitnames.frt
+
+\ SYMCNT
+$fc constant SCTSTRHH \ Symbol Counter Transmit Frame
+ $ff constant SCTSTRHH_SCTSTRHH \ Symbol Counter Transmit Frame
+ fc $ff bitmask: SCTSTRHH.SCTSTRHH \ Symbol Counter Transmit Frame
+$fb constant SCTSTRHL \ Symbol Counter Transmit Frame
+ $ff constant SCTSTRHL_SCTSTRHL \ Symbol Counter Transmit Frame
+ fb $ff bitmask: SCTSTRHL.SCTSTRHL \ Symbol Counter Transmit Frame
+$fa constant SCTSTRLH \ Symbol Counter Transmit Frame
+ $ff constant SCTSTRLH_SCTSTRLH \ Symbol Counter Transmit Frame
+ fa $ff bitmask: SCTSTRLH.SCTSTRLH \ Symbol Counter Transmit Frame
+$f9 constant SCTSTRLL \ Symbol Counter Transmit Frame
+ $ff constant SCTSTRLL_SCTSTRLL \ Symbol Counter Transmit Frame
+ f9 $ff bitmask: SCTSTRLL.SCTSTRLL \ Symbol Counter Transmit Frame
+$f8 constant SCOCR1HH \ Symbol Counter Output Compare
+ $ff constant SCOCR1HH_SCOCR1HH \ Symbol Counter Output Compare
+ f8 $ff bitmask: SCOCR1HH.SCOCR1HH \ Symbol Counter Output Compare
+$f7 constant SCOCR1HL \ Symbol Counter Output Compare
+ $ff constant SCOCR1HL_SCOCR1HL \ Symbol Counter Output Compare
+ f7 $ff bitmask: SCOCR1HL.SCOCR1HL \ Symbol Counter Output Compare
+$f6 constant SCOCR1LH \ Symbol Counter Output Compare
+ $ff constant SCOCR1LH_SCOCR1LH \ Symbol Counter Output Compare
+ f6 $ff bitmask: SCOCR1LH.SCOCR1LH \ Symbol Counter Output Compare
+$f5 constant SCOCR1LL \ Symbol Counter Output Compare
+ $ff constant SCOCR1LL_SCOCR1LL \ Symbol Counter Output Compare
+ f5 $ff bitmask: SCOCR1LL.SCOCR1LL \ Symbol Counter Output Compare
+$f4 constant SCOCR2HH \ Symbol Counter Output Compare
+ $ff constant SCOCR2HH_SCOCR2HH \ Symbol Counter Output Compare
+ f4 $ff bitmask: SCOCR2HH.SCOCR2HH \ Symbol Counter Output Compare
+$f3 constant SCOCR2HL \ Symbol Counter Output Compare
+ $ff constant SCOCR2HL_SCOCR2HL \ Symbol Counter Output Compare
+ f3 $ff bitmask: SCOCR2HL.SCOCR2HL \ Symbol Counter Output Compare
+$f2 constant SCOCR2LH \ Symbol Counter Output Compare
+ $ff constant SCOCR2LH_SCOCR2LH \ Symbol Counter Output Compare
+ f2 $ff bitmask: SCOCR2LH.SCOCR2LH \ Symbol Counter Output Compare
+$f1 constant SCOCR2LL \ Symbol Counter Output Compare
+ $ff constant SCOCR2LL_SCOCR2LL \ Symbol Counter Output Compare
+ f1 $ff bitmask: SCOCR2LL.SCOCR2LL \ Symbol Counter Output Compare
+$f0 constant SCOCR3HH \ Symbol Counter Output Compare
+ $ff constant SCOCR3HH_SCOCR3HH \ Symbol Counter Output Compare
+ f0 $ff bitmask: SCOCR3HH.SCOCR3HH \ Symbol Counter Output Compare
+$ef constant SCOCR3HL \ Symbol Counter Output Compare
+ $ff constant SCOCR3HL_SCOCR3HL \ Symbol Counter Output Compare
+ ef $ff bitmask: SCOCR3HL.SCOCR3HL \ Symbol Counter Output Compare
+$ee constant SCOCR3LH \ Symbol Counter Output Compare
+ $ff constant SCOCR3LH_SCOCR3LH \ Symbol Counter Output Compare
+ ee $ff bitmask: SCOCR3LH.SCOCR3LH \ Symbol Counter Output Compare
+$ed constant SCOCR3LL \ Symbol Counter Output Compare
+ $ff constant SCOCR3LL_SCOCR3LL \ Symbol Counter Output Compare
+ ed $ff bitmask: SCOCR3LL.SCOCR3LL \ Symbol Counter Output Compare
+$ec constant SCTSRHH \ Symbol Counter Frame Timestamp
+ $ff constant SCTSRHH_SCTSRHH \ Symbol Counter Frame Timestamp
+ ec $ff bitmask: SCTSRHH.SCTSRHH \ Symbol Counter Frame Timestamp
+$eb constant SCTSRHL \ Symbol Counter Frame Timestamp
+ $ff constant SCTSRHL_SCTSRHL \ Symbol Counter Frame Timestamp
+ eb $ff bitmask: SCTSRHL.SCTSRHL \ Symbol Counter Frame Timestamp
+$ea constant SCTSRLH \ Symbol Counter Frame Timestamp
+ $ff constant SCTSRLH_SCTSRLH \ Symbol Counter Frame Timestamp
+ ea $ff bitmask: SCTSRLH.SCTSRLH \ Symbol Counter Frame Timestamp
+$e9 constant SCTSRLL \ Symbol Counter Frame Timestamp
+ $ff constant SCTSRLL_SCTSRLL \ Symbol Counter Frame Timestamp
+ e9 $ff bitmask: SCTSRLL.SCTSRLL \ Symbol Counter Frame Timestamp
+$e8 constant SCBTSRHH \ Symbol Counter Beacon Timestam
+ $ff constant SCBTSRHH_SCBTSRHH \ Symbol Counter Beacon Timestam
+ e8 $ff bitmask: SCBTSRHH.SCBTSRHH \ Symbol Counter Beacon Timestam
+$e7 constant SCBTSRHL \ Symbol Counter Beacon Timestam
+ $ff constant SCBTSRHL_SCBTSRHL \ Symbol Counter Beacon Timestam
+ e7 $ff bitmask: SCBTSRHL.SCBTSRHL \ Symbol Counter Beacon Timestam
+$e6 constant SCBTSRLH \ Symbol Counter Beacon Timestam
+ $ff constant SCBTSRLH_SCBTSRLH \ Symbol Counter Beacon Timestam
+ e6 $ff bitmask: SCBTSRLH.SCBTSRLH \ Symbol Counter Beacon Timestam
+$e5 constant SCBTSRLL \ Symbol Counter Beacon Timestam
+ $ff constant SCBTSRLL_SCBTSRLL \ Symbol Counter Beacon Timestam
+ e5 $ff bitmask: SCBTSRLL.SCBTSRLL \ Symbol Counter Beacon Timestam
+$e4 constant SCCNTHH \ Symbol Counter Register HH-Byt
+ $ff constant SCCNTHH_SCCNTHH \ Symbol Counter Register HH-Byt
+ e4 $ff bitmask: SCCNTHH.SCCNTHH \ Symbol Counter Register HH-Byt
+$e3 constant SCCNTHL \ Symbol Counter Register HL-Byt
+ $ff constant SCCNTHL_SCCNTHL \ Symbol Counter Register HL-Byt
+ e3 $ff bitmask: SCCNTHL.SCCNTHL \ Symbol Counter Register HL-Byt
+$e2 constant SCCNTLH \ Symbol Counter Register LH-Byt
+ $ff constant SCCNTLH_SCCNTLH \ Symbol Counter Register LH-Byt
+ e2 $ff bitmask: SCCNTLH.SCCNTLH \ Symbol Counter Register LH-Byt
+$e1 constant SCCNTLL \ Symbol Counter Register LL-Byt
+ $ff constant SCCNTLL_SCCNTLL \ Symbol Counter Register LL-Byt
+ e1 $ff bitmask: SCCNTLL.SCCNTLL \ Symbol Counter Register LL-Byt
+$e0 constant SCIRQS \ Symbol Counter Interrupt Statu
+ $e0 constant SCIRQS_Res \ Reserved Bit
+ e0 $e0 bitmask: SCIRQS.Res \ Reserved Bit
+ $10 constant SCIRQS_IRQSBO \ Backoff Slot Counter IRQ
+ e0 $10 bitmask: SCIRQS.IRQSBO \ Backoff Slot Counter IRQ
+ $8 constant SCIRQS_IRQSOF \ Symbol Counter Overflow IRQ
+ e0 $8 bitmask: SCIRQS.IRQSOF \ Symbol Counter Overflow IRQ
+ $7 constant SCIRQS_IRQSCP \ Compare Unit 3 Compare Match I
+ e0 $7 bitmask: SCIRQS.IRQSCP \ Compare Unit 3 Compare Match I
+$df constant SCIRQM \ Symbol Counter Interrupt Mask
+ $e0 constant SCIRQM_Res \ Reserved Bit
+ df $e0 bitmask: SCIRQM.Res \ Reserved Bit
+ $10 constant SCIRQM_IRQMBO \ Backoff Slot Counter IRQ enabl
+ df $10 bitmask: SCIRQM.IRQMBO \ Backoff Slot Counter IRQ enabl
+ $8 constant SCIRQM_IRQMOF \ Symbol Counter Overflow IRQ en
+ df $8 bitmask: SCIRQM.IRQMOF \ Symbol Counter Overflow IRQ en
+ $7 constant SCIRQM_IRQMCP \ Symbol Counter Compare Match 3
+ df $7 bitmask: SCIRQM.IRQMCP \ Symbol Counter Compare Match 3
+$de constant SCSR \ Symbol Counter Status Register
+ $fe constant SCSR_Res \ Reserved Bit
+ de $fe bitmask: SCSR.Res \ Reserved Bit
+ $1 constant SCSR_SCBSY \ Symbol Counter busy
+ de $1 bitmask: SCSR.SCBSY \ Symbol Counter busy
+$dd constant SCCR1 \ Symbol Counter Control Registe
+ $c0 constant SCCR1_Res \ Reserved Bit
+ dd $c0 bitmask: SCCR1.Res \ Reserved Bit
+ $20 constant SCCR1_SCBTSM \ Symbol Counter Beacon Timestam
+ dd $20 bitmask: SCCR1.SCBTSM \ Symbol Counter Beacon Timestam
+ $1c constant SCCR1_SCCKDIV \ Clock divider for synchronous
+ dd $1c bitmask: SCCR1.SCCKDIV \ Clock divider for synchronous
+ $2 constant SCCR1_SCEECLK \ Enable External Clock Source o
+ dd $2 bitmask: SCCR1.SCEECLK \ Enable External Clock Source o
+ $1 constant SCCR1_SCENBO \ Backoff Slot Counter enable
+ dd $1 bitmask: SCCR1.SCENBO \ Backoff Slot Counter enable
+$dc constant SCCR0 \ Symbol Counter Control Registe
+ $80 constant SCCR0_SCRES \ Symbol Counter Synchronization
+ dc $80 bitmask: SCCR0.SCRES \ Symbol Counter Synchronization
+ $40 constant SCCR0_SCMBTS \ Manual Beacon Timestamp
+ dc $40 bitmask: SCCR0.SCMBTS \ Manual Beacon Timestamp
+ $20 constant SCCR0_SCEN \ Symbol Counter enable
+ dc $20 bitmask: SCCR0.SCEN \ Symbol Counter enable
+ $10 constant SCCR0_SCCKSEL \ Symbol Counter Clock Source se
+ dc $10 bitmask: SCCR0.SCCKSEL \ Symbol Counter Clock Source se
+ $8 constant SCCR0_SCTSE \ Symbol Counter Automatic Times
+ dc $8 bitmask: SCCR0.SCTSE \ Symbol Counter Automatic Times
+ $7 constant SCCR0_SCCMP \ Symbol Counter Compare Unit 3
+ dc $7 bitmask: SCCR0.SCCMP \ Symbol Counter Compare Unit 3
+$db constant SCCSR \ Symbol Counter Compare Source
+ $c0 constant SCCSR_Res \ Reserved Bit
+ db $c0 bitmask: SCCSR.Res \ Reserved Bit
+ $30 constant SCCSR_SCCS3 \ Symbol Counter Compare Source
+ db $30 bitmask: SCCSR.SCCS3 \ Symbol Counter Compare Source
+ $c constant SCCSR_SCCS2 \ Symbol Counter Compare Source
+ db $c bitmask: SCCSR.SCCS2 \ Symbol Counter Compare Source
+ $3 constant SCCSR_SCCS1 \ Symbol Counter Compare Source
+ db $3 bitmask: SCCSR.SCCS1 \ Symbol Counter Compare Source
+$da constant SCRSTRHH \ Symbol Counter Received Frame
+ $ff constant SCRSTRHH_SCRSTRHH \ Symbol Counter Received Frame
+ da $ff bitmask: SCRSTRHH.SCRSTRHH \ Symbol Counter Received Frame
+$d9 constant SCRSTRHL \ Symbol Counter Received Frame
+ $ff constant SCRSTRHL_SCRSTRHL \ Symbol Counter Received Frame
+ d9 $ff bitmask: SCRSTRHL.SCRSTRHL \ Symbol Counter Received Frame
+$d8 constant SCRSTRLH \ Symbol Counter Received Frame
+ $ff constant SCRSTRLH_SCRSTRLH \ Symbol Counter Received Frame
+ d8 $ff bitmask: SCRSTRLH.SCRSTRLH \ Symbol Counter Received Frame
+$d7 constant SCRSTRLL \ Symbol Counter Received Frame
+ $ff constant SCRSTRLL_SCRSTRLL \ Symbol Counter Received Frame
+ d7 $ff bitmask: SCRSTRLL.SCRSTRLL \ Symbol Counter Received Frame
diff --git a/amforth-6.5/avr8/devices/atmega128rfr2/blocks/TIMER_COUNTER_0.frt b/amforth-6.5/avr8/devices/atmega128rfr2/blocks/TIMER_COUNTER_0.frt
new file mode 100644
index 0000000..2cc8dd3
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega128rfr2/blocks/TIMER_COUNTER_0.frt
@@ -0,0 +1,54 @@
+\ Generated automatically for atmega128rfr2
+\ #require bitnames.frt
+
+\ TIMER_COUNTER_0
+$48 constant OCR0B \ Timer/Counter0 Output Compare
+$47 constant OCR0A \ Timer/Counter0 Output Compare
+$46 constant TCNT0 \ Timer/Counter0 Register
+$45 constant TCCR0B \ Timer/Counter0 Control Registe
+ $80 constant TCCR0B_FOC0A \ Force Output Compare A
+ 45 $80 bitmask: TCCR0B.FOC0A \ Force Output Compare A
+ $40 constant TCCR0B_FOC0B \ Force Output Compare B
+ 45 $40 bitmask: TCCR0B.FOC0B \ Force Output Compare B
+ $30 constant TCCR0B_Res \ Reserved Bit
+ 45 $30 bitmask: TCCR0B.Res \ Reserved Bit
+ $8 constant TCCR0B_WGM02 \
+ 45 $8 bitmask: TCCR0B.WGM02 \
+ $7 constant TCCR0B_CS0 \ Clock Select
+ 45 $7 bitmask: TCCR0B.CS0 \ Clock Select
+$44 constant TCCR0A \ Timer/Counter0 Control Registe
+ $c0 constant TCCR0A_COM0A \ Compare Match Output A Mode
+ 44 $c0 bitmask: TCCR0A.COM0A \ Compare Match Output A Mode
+ $30 constant TCCR0A_COM0B \ Compare Match Output B Mode
+ 44 $30 bitmask: TCCR0A.COM0B \ Compare Match Output B Mode
+ $c constant TCCR0A_Res \ Reserved Bit
+ 44 $c bitmask: TCCR0A.Res \ Reserved Bit
+ $3 constant TCCR0A_WGM0 \ Waveform Generation Mode
+ 44 $3 bitmask: TCCR0A.WGM0 \ Waveform Generation Mode
+$6e constant TIMSK0 \ Timer/Counter0 Interrupt Mask
+ $f8 constant TIMSK0_Res \ Reserved
+ 6e $f8 bitmask: TIMSK0.Res \ Reserved
+ $4 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare
+ 6e $4 bitmask: TIMSK0.OCIE0B \ Timer/Counter0 Output Compare
+ $2 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare
+ 6e $2 bitmask: TIMSK0.OCIE0A \ Timer/Counter0 Output Compare
+ $1 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interr
+ 6e $1 bitmask: TIMSK0.TOIE0 \ Timer/Counter0 Overflow Interr
+$35 constant TIFR0 \ Timer/Counter0 Interrupt Flag
+ $f8 constant TIFR0_Res \ Reserved
+ 35 $f8 bitmask: TIFR0.Res \ Reserved
+ $4 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare
+ 35 $4 bitmask: TIFR0.OCF0B \ Timer/Counter0 Output Compare
+ $2 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare
+ 35 $2 bitmask: TIFR0.OCF0A \ Timer/Counter0 Output Compare
+ $1 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
+ 35 $1 bitmask: TIFR0.TOV0 \ Timer/Counter0 Overflow Flag
+$43 constant GTCCR \ General Timer/Counter Control
+ $80 constant GTCCR_TSM \ Timer/Counter Synchronization
+ 43 $80 bitmask: GTCCR.TSM \ Timer/Counter Synchronization
+ $7c constant GTCCR_Res \ Reserved
+ 43 $7c bitmask: GTCCR.Res \ Reserved
+ $2 constant GTCCR_PSRASY \ Prescaler Reset Timer/Counter2
+ 43 $2 bitmask: GTCCR.PSRASY \ Prescaler Reset Timer/Counter2
+ $1 constant GTCCR_PSRSYNC \ Prescaler Reset for Synchronou
+ 43 $1 bitmask: GTCCR.PSRSYNC \ Prescaler Reset for Synchronou
diff --git a/amforth-6.5/avr8/devices/atmega128rfr2/blocks/TIMER_COUNTER_1.frt b/amforth-6.5/avr8/devices/atmega128rfr2/blocks/TIMER_COUNTER_1.frt
new file mode 100644
index 0000000..1b4a1ea
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega128rfr2/blocks/TIMER_COUNTER_1.frt
@@ -0,0 +1,68 @@
+\ Generated automatically for atmega128rfr2
+\ #require bitnames.frt
+
+\ TIMER_COUNTER_1
+$80 constant TCCR1A \ Timer/Counter1 Control Registe
+ $c0 constant TCCR1A_COM1A \ Compare Output Mode for Channe
+ 80 $c0 bitmask: TCCR1A.COM1A \ Compare Output Mode for Channe
+ $30 constant TCCR1A_COM1B \ Compare Output Mode for Channe
+ 80 $30 bitmask: TCCR1A.COM1B \ Compare Output Mode for Channe
+ $c constant TCCR1A_COM1C \ Compare Output Mode for Channe
+ 80 $c bitmask: TCCR1A.COM1C \ Compare Output Mode for Channe
+ $3 constant TCCR1A_WGM1 \ Waveform Generation Mode
+ 80 $3 bitmask: TCCR1A.WGM1 \ Waveform Generation Mode
+$81 constant TCCR1B \ Timer/Counter1 Control Registe
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Cancelle
+ 81 $80 bitmask: TCCR1B.ICNC1 \ Input Capture 1 Noise Cancelle
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ 81 $40 bitmask: TCCR1B.ICES1 \ Input Capture 1 Edge Select
+ $20 constant TCCR1B_Res \ Reserved Bit
+ 81 $20 bitmask: TCCR1B.Res \ Reserved Bit
+ $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
+ 81 $18 bitmask: TCCR1B.WGM1 \ Waveform Generation Mode
+ $7 constant TCCR1B_CS1 \ Clock Select
+ 81 $7 bitmask: TCCR1B.CS1 \ Clock Select
+$82 constant TCCR1C \ Timer/Counter1 Control Registe
+ $80 constant TCCR1C_FOC1A \ Force Output Compare for Chann
+ 82 $80 bitmask: TCCR1C.FOC1A \ Force Output Compare for Chann
+ $40 constant TCCR1C_FOC1B \ Force Output Compare for Chann
+ 82 $40 bitmask: TCCR1C.FOC1B \ Force Output Compare for Chann
+ $20 constant TCCR1C_FOC1C \ Force Output Compare for Chann
+ 82 $20 bitmask: TCCR1C.FOC1C \ Force Output Compare for Chann
+ $1f constant TCCR1C_Res \ Reserved
+ 82 $1f bitmask: TCCR1C.Res \ Reserved
+$84 constant TCNT1 \ Timer/Counter1 Bytes
+$88 constant OCR1A \ Timer/Counter1 Output Compare
+$8a constant OCR1B \ Timer/Counter1 Output Compare
+$8c constant OCR1C \ Timer/Counter1 Output Compare
+$86 constant ICR1 \ Timer/Counter1 Input Capture R
+$6f constant TIMSK1 \ Timer/Counter1 Interrupt Mask
+ $c0 constant TIMSK1_Res \ Reserved Bit
+ 6f $c0 bitmask: TIMSK1.Res \ Reserved Bit
+ $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture I
+ 6f $20 bitmask: TIMSK1.ICIE1 \ Timer/Counter1 Input Capture I
+ $10 constant TIMSK1_Res \ Reserved Bit
+ 6f $10 bitmask: TIMSK1.Res \ Reserved Bit
+ $8 constant TIMSK1_OCIE1C \ Timer/Counter1 Output Compare
+ 6f $8 bitmask: TIMSK1.OCIE1C \ Timer/Counter1 Output Compare
+ $4 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare
+ 6f $4 bitmask: TIMSK1.OCIE1B \ Timer/Counter1 Output Compare
+ $2 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare
+ 6f $2 bitmask: TIMSK1.OCIE1A \ Timer/Counter1 Output Compare
+ $1 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interr
+ 6f $1 bitmask: TIMSK1.TOIE1 \ Timer/Counter1 Overflow Interr
+$36 constant TIFR1 \ Timer/Counter1 Interrupt Flag
+ $c0 constant TIFR1_Res \ Reserved Bit
+ 36 $c0 bitmask: TIFR1.Res \ Reserved Bit
+ $20 constant TIFR1_ICF1 \ Timer/Counter1 Input Capture F
+ 36 $20 bitmask: TIFR1.ICF1 \ Timer/Counter1 Input Capture F
+ $10 constant TIFR1_Res \ Reserved Bit
+ 36 $10 bitmask: TIFR1.Res \ Reserved Bit
+ $8 constant TIFR1_OCF1C \ Timer/Counter1 Output Compare
+ 36 $8 bitmask: TIFR1.OCF1C \ Timer/Counter1 Output Compare
+ $4 constant TIFR1_OCF1B \ Timer/Counter1 Output Compare
+ 36 $4 bitmask: TIFR1.OCF1B \ Timer/Counter1 Output Compare
+ $2 constant TIFR1_OCF1A \ Timer/Counter1 Output Compare
+ 36 $2 bitmask: TIFR1.OCF1A \ Timer/Counter1 Output Compare
+ $1 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
+ 36 $1 bitmask: TIFR1.TOV1 \ Timer/Counter1 Overflow Flag
diff --git a/amforth-6.5/avr8/devices/atmega128rfr2/blocks/TIMER_COUNTER_2.frt b/amforth-6.5/avr8/devices/atmega128rfr2/blocks/TIMER_COUNTER_2.frt
new file mode 100644
index 0000000..c694b06
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega128rfr2/blocks/TIMER_COUNTER_2.frt
@@ -0,0 +1,67 @@
+\ Generated automatically for atmega128rfr2
+\ #require bitnames.frt
+
+\ TIMER_COUNTER_2
+$70 constant TIMSK2 \ Timer/Counter Interrupt Mask r
+ $f8 constant TIMSK2_Res \ Reserved Bit
+ 70 $f8 bitmask: TIMSK2.Res \ Reserved Bit
+ $4 constant TIMSK2_OCIE2B \ Timer/Counter2 Output Compare
+ 70 $4 bitmask: TIMSK2.OCIE2B \ Timer/Counter2 Output Compare
+ $2 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare
+ 70 $2 bitmask: TIMSK2.OCIE2A \ Timer/Counter2 Output Compare
+ $1 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interr
+ 70 $1 bitmask: TIMSK2.TOIE2 \ Timer/Counter2 Overflow Interr
+$37 constant TIFR2 \ Timer/Counter Interrupt Flag R
+ $f8 constant TIFR2_Res \ Reserved Bit
+ 37 $f8 bitmask: TIFR2.Res \ Reserved Bit
+ $4 constant TIFR2_OCF2B \ Output Compare Flag 2 B
+ 37 $4 bitmask: TIFR2.OCF2B \ Output Compare Flag 2 B
+ $2 constant TIFR2_OCF2A \ Output Compare Flag 2 A
+ 37 $2 bitmask: TIFR2.OCF2A \ Output Compare Flag 2 A
+ $1 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
+ 37 $1 bitmask: TIFR2.TOV2 \ Timer/Counter2 Overflow Flag
+$b0 constant TCCR2A \ Timer/Counter2 Control Registe
+ $c0 constant TCCR2A_COM2A \ Compare Match Output A Mode
+ b0 $c0 bitmask: TCCR2A.COM2A \ Compare Match Output A Mode
+ $30 constant TCCR2A_COM2B \ Compare Match Output B Mode
+ b0 $30 bitmask: TCCR2A.COM2B \ Compare Match Output B Mode
+ $c constant TCCR2A_Res \ Reserved
+ b0 $c bitmask: TCCR2A.Res \ Reserved
+ $3 constant TCCR2A_WGM2 \ Waveform Generation Mode
+ b0 $3 bitmask: TCCR2A.WGM2 \ Waveform Generation Mode
+$b1 constant TCCR2B \ Timer/Counter2 Control Registe
+ $80 constant TCCR2B_FOC2A \ Force Output Compare A
+ b1 $80 bitmask: TCCR2B.FOC2A \ Force Output Compare A
+ $40 constant TCCR2B_FOC2B \ Force Output Compare B
+ b1 $40 bitmask: TCCR2B.FOC2B \ Force Output Compare B
+ $30 constant TCCR2B_Res \ Reserved
+ b1 $30 bitmask: TCCR2B.Res \ Reserved
+ $8 constant TCCR2B_WGM22 \ Waveform Generation Mode
+ b1 $8 bitmask: TCCR2B.WGM22 \ Waveform Generation Mode
+ $7 constant TCCR2B_CS2 \ Clock Select
+ b1 $7 bitmask: TCCR2B.CS2 \ Clock Select
+$b2 constant TCNT2 \ Timer/Counter2
+$b4 constant OCR2B \ Timer/Counter2 Output Compare
+$b3 constant OCR2A \ Timer/Counter2 Output Compare
+$b6 constant ASSR \ Asynchronous Status Register
+ $80 constant ASSR_EXCLKAMR \ Enable External Clock Input fo
+ b6 $80 bitmask: ASSR.EXCLKAMR \ Enable External Clock Input fo
+ $40 constant ASSR_EXCLK \ Enable External Clock Input
+ b6 $40 bitmask: ASSR.EXCLK \ Enable External Clock Input
+ $20 constant ASSR_AS2 \ Timer/Counter2 Asynchronous Mo
+ b6 $20 bitmask: ASSR.AS2 \ Timer/Counter2 Asynchronous Mo
+ $10 constant ASSR_TCN2UB \ Timer/Counter2 Update Busy
+ b6 $10 bitmask: ASSR.TCN2UB \ Timer/Counter2 Update Busy
+ $8 constant ASSR_OCR2AUB \ Timer/Counter2 Output Compare
+ b6 $8 bitmask: ASSR.OCR2AUB \ Timer/Counter2 Output Compare
+ $4 constant ASSR_OCR2BUB \ Timer/Counter2 Output Compare
+ b6 $4 bitmask: ASSR.OCR2BUB \ Timer/Counter2 Output Compare
+ $2 constant ASSR_TCR2AUB \ Timer/Counter2 Control Registe
+ b6 $2 bitmask: ASSR.TCR2AUB \ Timer/Counter2 Control Registe
+ $1 constant ASSR_TCR2BUB \ Timer/Counter2 Control Registe
+ b6 $1 bitmask: ASSR.TCR2BUB \ Timer/Counter2 Control Registe
+$43 constant GTCCR \ General Timer Counter Control
+ $80 constant GTCCR_TSM \ Timer/Counter Synchronization
+ 43 $80 bitmask: GTCCR.TSM \ Timer/Counter Synchronization
+ $2 constant GTCCR_PSRASY \ Prescaler Reset Timer/Counter2
+ 43 $2 bitmask: GTCCR.PSRASY \ Prescaler Reset Timer/Counter2
diff --git a/amforth-6.5/avr8/devices/atmega128rfr2/blocks/TIMER_COUNTER_3.frt b/amforth-6.5/avr8/devices/atmega128rfr2/blocks/TIMER_COUNTER_3.frt
new file mode 100644
index 0000000..52e7b4c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega128rfr2/blocks/TIMER_COUNTER_3.frt
@@ -0,0 +1,68 @@
+\ Generated automatically for atmega128rfr2
+\ #require bitnames.frt
+
+\ TIMER_COUNTER_3
+$90 constant TCCR3A \ Timer/Counter3 Control Registe
+ $c0 constant TCCR3A_COM3A \ Compare Output Mode for Channe
+ 90 $c0 bitmask: TCCR3A.COM3A \ Compare Output Mode for Channe
+ $30 constant TCCR3A_COM3B \ Compare Output Mode for Channe
+ 90 $30 bitmask: TCCR3A.COM3B \ Compare Output Mode for Channe
+ $c constant TCCR3A_COM3C \ Compare Output Mode for Channe
+ 90 $c bitmask: TCCR3A.COM3C \ Compare Output Mode for Channe
+ $3 constant TCCR3A_WGM3 \ Waveform Generation Mode
+ 90 $3 bitmask: TCCR3A.WGM3 \ Waveform Generation Mode
+$91 constant TCCR3B \ Timer/Counter3 Control Registe
+ $80 constant TCCR3B_ICNC3 \ Input Capture 3 Noise Cancelle
+ 91 $80 bitmask: TCCR3B.ICNC3 \ Input Capture 3 Noise Cancelle
+ $40 constant TCCR3B_ICES3 \ Input Capture 3 Edge Select
+ 91 $40 bitmask: TCCR3B.ICES3 \ Input Capture 3 Edge Select
+ $20 constant TCCR3B_Res \ Reserved Bit
+ 91 $20 bitmask: TCCR3B.Res \ Reserved Bit
+ $18 constant TCCR3B_WGM3 \ Waveform Generation Mode
+ 91 $18 bitmask: TCCR3B.WGM3 \ Waveform Generation Mode
+ $7 constant TCCR3B_CS3 \ Clock Select
+ 91 $7 bitmask: TCCR3B.CS3 \ Clock Select
+$92 constant TCCR3C \ Timer/Counter3 Control Registe
+ $80 constant TCCR3C_FOC3A \ Force Output Compare for Chann
+ 92 $80 bitmask: TCCR3C.FOC3A \ Force Output Compare for Chann
+ $40 constant TCCR3C_FOC3B \ Force Output Compare for Chann
+ 92 $40 bitmask: TCCR3C.FOC3B \ Force Output Compare for Chann
+ $20 constant TCCR3C_FOC3C \ Force Output Compare for Chann
+ 92 $20 bitmask: TCCR3C.FOC3C \ Force Output Compare for Chann
+ $1f constant TCCR3C_Res \ Reserved
+ 92 $1f bitmask: TCCR3C.Res \ Reserved
+$94 constant TCNT3 \ Timer/Counter3 Bytes
+$98 constant OCR3A \ Timer/Counter3 Output Compare
+$9a constant OCR3B \ Timer/Counter3 Output Compare
+$9c constant OCR3C \ Timer/Counter3 Output Compare
+$96 constant ICR3 \ Timer/Counter3 Input Capture R
+$71 constant TIMSK3 \ Timer/Counter3 Interrupt Mask
+ $c0 constant TIMSK3_Res \ Reserved Bit
+ 71 $c0 bitmask: TIMSK3.Res \ Reserved Bit
+ $20 constant TIMSK3_ICIE3 \ Timer/Counter3 Input Capture I
+ 71 $20 bitmask: TIMSK3.ICIE3 \ Timer/Counter3 Input Capture I
+ $10 constant TIMSK3_Res \ Reserved Bit
+ 71 $10 bitmask: TIMSK3.Res \ Reserved Bit
+ $8 constant TIMSK3_OCIE3C \ Timer/Counter3 Output Compare
+ 71 $8 bitmask: TIMSK3.OCIE3C \ Timer/Counter3 Output Compare
+ $4 constant TIMSK3_OCIE3B \ Timer/Counter3 Output Compare
+ 71 $4 bitmask: TIMSK3.OCIE3B \ Timer/Counter3 Output Compare
+ $2 constant TIMSK3_OCIE3A \ Timer/Counter3 Output Compare
+ 71 $2 bitmask: TIMSK3.OCIE3A \ Timer/Counter3 Output Compare
+ $1 constant TIMSK3_TOIE3 \ Timer/Counter3 Overflow Interr
+ 71 $1 bitmask: TIMSK3.TOIE3 \ Timer/Counter3 Overflow Interr
+$38 constant TIFR3 \ Timer/Counter3 Interrupt Flag
+ $c0 constant TIFR3_Res \ Reserved Bit
+ 38 $c0 bitmask: TIFR3.Res \ Reserved Bit
+ $20 constant TIFR3_ICF3 \ Timer/Counter3 Input Capture F
+ 38 $20 bitmask: TIFR3.ICF3 \ Timer/Counter3 Input Capture F
+ $10 constant TIFR3_Res \ Reserved Bit
+ 38 $10 bitmask: TIFR3.Res \ Reserved Bit
+ $8 constant TIFR3_OCF3C \ Timer/Counter3 Output Compare
+ 38 $8 bitmask: TIFR3.OCF3C \ Timer/Counter3 Output Compare
+ $4 constant TIFR3_OCF3B \ Timer/Counter3 Output Compare
+ 38 $4 bitmask: TIFR3.OCF3B \ Timer/Counter3 Output Compare
+ $2 constant TIFR3_OCF3A \ Timer/Counter3 Output Compare
+ 38 $2 bitmask: TIFR3.OCF3A \ Timer/Counter3 Output Compare
+ $1 constant TIFR3_TOV3 \ Timer/Counter3 Overflow Flag
+ 38 $1 bitmask: TIFR3.TOV3 \ Timer/Counter3 Overflow Flag
diff --git a/amforth-6.5/avr8/devices/atmega128rfr2/blocks/TIMER_COUNTER_4.frt b/amforth-6.5/avr8/devices/atmega128rfr2/blocks/TIMER_COUNTER_4.frt
new file mode 100644
index 0000000..ffd3366
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega128rfr2/blocks/TIMER_COUNTER_4.frt
@@ -0,0 +1,68 @@
+\ Generated automatically for atmega128rfr2
+\ #require bitnames.frt
+
+\ TIMER_COUNTER_4
+$a0 constant TCCR4A \ Timer/Counter4 Control Registe
+ $c0 constant TCCR4A_COM4A \ Compare Output Mode for Channe
+ a0 $c0 bitmask: TCCR4A.COM4A \ Compare Output Mode for Channe
+ $30 constant TCCR4A_COM4B \ Compare Output Mode for Channe
+ a0 $30 bitmask: TCCR4A.COM4B \ Compare Output Mode for Channe
+ $c constant TCCR4A_COM4C \ Compare Output Mode for Channe
+ a0 $c bitmask: TCCR4A.COM4C \ Compare Output Mode for Channe
+ $3 constant TCCR4A_WGM4 \ Waveform Generation Mode
+ a0 $3 bitmask: TCCR4A.WGM4 \ Waveform Generation Mode
+$a1 constant TCCR4B \ Timer/Counter4 Control Registe
+ $80 constant TCCR4B_ICNC4 \ Input Capture 4 Noise Cancelle
+ a1 $80 bitmask: TCCR4B.ICNC4 \ Input Capture 4 Noise Cancelle
+ $40 constant TCCR4B_ICES4 \ Input Capture 4 Edge Select
+ a1 $40 bitmask: TCCR4B.ICES4 \ Input Capture 4 Edge Select
+ $20 constant TCCR4B_Res \ Reserved Bit
+ a1 $20 bitmask: TCCR4B.Res \ Reserved Bit
+ $18 constant TCCR4B_WGM4 \ Waveform Generation Mode
+ a1 $18 bitmask: TCCR4B.WGM4 \ Waveform Generation Mode
+ $7 constant TCCR4B_CS4 \ Clock Select
+ a1 $7 bitmask: TCCR4B.CS4 \ Clock Select
+$a2 constant TCCR4C \ Timer/Counter4 Control Registe
+ $80 constant TCCR4C_FOC4A \ Force Output Compare for Chann
+ a2 $80 bitmask: TCCR4C.FOC4A \ Force Output Compare for Chann
+ $40 constant TCCR4C_FOC4B \ Force Output Compare for Chann
+ a2 $40 bitmask: TCCR4C.FOC4B \ Force Output Compare for Chann
+ $20 constant TCCR4C_FOC4C \ Force Output Compare for Chann
+ a2 $20 bitmask: TCCR4C.FOC4C \ Force Output Compare for Chann
+ $1f constant TCCR4C_Res \ Reserved
+ a2 $1f bitmask: TCCR4C.Res \ Reserved
+$a4 constant TCNT4 \ Timer/Counter4 Bytes
+$a8 constant OCR4A \ Timer/Counter4 Output Compare
+$aa constant OCR4B \ Timer/Counter4 Output Compare
+$ac constant OCR4C \ Timer/Counter4 Output Compare
+$a6 constant ICR4 \ Timer/Counter4 Input Capture R
+$72 constant TIMSK4 \ Timer/Counter4 Interrupt Mask
+ $c0 constant TIMSK4_Res \ Reserved Bit
+ 72 $c0 bitmask: TIMSK4.Res \ Reserved Bit
+ $20 constant TIMSK4_ICIE4 \ Timer/Counter4 Input Capture I
+ 72 $20 bitmask: TIMSK4.ICIE4 \ Timer/Counter4 Input Capture I
+ $10 constant TIMSK4_Res \ Reserved Bit
+ 72 $10 bitmask: TIMSK4.Res \ Reserved Bit
+ $8 constant TIMSK4_OCIE4C \ Timer/Counter4 Output Compare
+ 72 $8 bitmask: TIMSK4.OCIE4C \ Timer/Counter4 Output Compare
+ $4 constant TIMSK4_OCIE4B \ Timer/Counter4 Output Compare
+ 72 $4 bitmask: TIMSK4.OCIE4B \ Timer/Counter4 Output Compare
+ $2 constant TIMSK4_OCIE4A \ Timer/Counter4 Output Compare
+ 72 $2 bitmask: TIMSK4.OCIE4A \ Timer/Counter4 Output Compare
+ $1 constant TIMSK4_TOIE4 \ Timer/Counter4 Overflow Interr
+ 72 $1 bitmask: TIMSK4.TOIE4 \ Timer/Counter4 Overflow Interr
+$39 constant TIFR4 \ Timer/Counter4 Interrupt Flag
+ $c0 constant TIFR4_Res \ Reserved Bit
+ 39 $c0 bitmask: TIFR4.Res \ Reserved Bit
+ $20 constant TIFR4_ICF4 \ Timer/Counter4 Input Capture F
+ 39 $20 bitmask: TIFR4.ICF4 \ Timer/Counter4 Input Capture F
+ $10 constant TIFR4_Res \ Reserved Bit
+ 39 $10 bitmask: TIFR4.Res \ Reserved Bit
+ $8 constant TIFR4_OCF4C \ Timer/Counter4 Output Compare
+ 39 $8 bitmask: TIFR4.OCF4C \ Timer/Counter4 Output Compare
+ $4 constant TIFR4_OCF4B \ Timer/Counter4 Output Compare
+ 39 $4 bitmask: TIFR4.OCF4B \ Timer/Counter4 Output Compare
+ $2 constant TIFR4_OCF4A \ Timer/Counter4 Output Compare
+ 39 $2 bitmask: TIFR4.OCF4A \ Timer/Counter4 Output Compare
+ $1 constant TIFR4_TOV4 \ Timer/Counter4 Overflow Flag
+ 39 $1 bitmask: TIFR4.TOV4 \ Timer/Counter4 Overflow Flag
diff --git a/amforth-6.5/avr8/devices/atmega128rfr2/blocks/TIMER_COUNTER_5.frt b/amforth-6.5/avr8/devices/atmega128rfr2/blocks/TIMER_COUNTER_5.frt
new file mode 100644
index 0000000..93077e5
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega128rfr2/blocks/TIMER_COUNTER_5.frt
@@ -0,0 +1,68 @@
+\ Generated automatically for atmega128rfr2
+\ #require bitnames.frt
+
+\ TIMER_COUNTER_5
+$120 constant TCCR5A \ Timer/Counter5 Control Registe
+ $c0 constant TCCR5A_COM5A \ Compare Output Mode for Channe
+ 120 $c0 bitmask: TCCR5A.COM5A \ Compare Output Mode for Channe
+ $30 constant TCCR5A_COM5B \ Compare Output Mode for Channe
+ 120 $30 bitmask: TCCR5A.COM5B \ Compare Output Mode for Channe
+ $c constant TCCR5A_COM5C \ Compare Output Mode for Channe
+ 120 $c bitmask: TCCR5A.COM5C \ Compare Output Mode for Channe
+ $3 constant TCCR5A_WGM5 \ Waveform Generation Mode
+ 120 $3 bitmask: TCCR5A.WGM5 \ Waveform Generation Mode
+$121 constant TCCR5B \ Timer/Counter5 Control Registe
+ $80 constant TCCR5B_ICNC5 \ Input Capture 5 Noise Cancelle
+ 121 $80 bitmask: TCCR5B.ICNC5 \ Input Capture 5 Noise Cancelle
+ $40 constant TCCR5B_ICES5 \ Input Capture 5 Edge Select
+ 121 $40 bitmask: TCCR5B.ICES5 \ Input Capture 5 Edge Select
+ $20 constant TCCR5B_Res \ Reserved Bit
+ 121 $20 bitmask: TCCR5B.Res \ Reserved Bit
+ $18 constant TCCR5B_WGM5 \ Waveform Generation Mode
+ 121 $18 bitmask: TCCR5B.WGM5 \ Waveform Generation Mode
+ $7 constant TCCR5B_CS5 \ Clock Select
+ 121 $7 bitmask: TCCR5B.CS5 \ Clock Select
+$122 constant TCCR5C \ Timer/Counter5 Control Registe
+ $80 constant TCCR5C_FOC5A \ Force Output Compare for Chann
+ 122 $80 bitmask: TCCR5C.FOC5A \ Force Output Compare for Chann
+ $40 constant TCCR5C_FOC5B \ Force Output Compare for Chann
+ 122 $40 bitmask: TCCR5C.FOC5B \ Force Output Compare for Chann
+ $20 constant TCCR5C_FOC5C \ Force Output Compare for Chann
+ 122 $20 bitmask: TCCR5C.FOC5C \ Force Output Compare for Chann
+ $1f constant TCCR5C_Res \ Reserved
+ 122 $1f bitmask: TCCR5C.Res \ Reserved
+$124 constant TCNT5 \ Timer/Counter5 Bytes
+$128 constant OCR5A \ Timer/Counter5 Output Compare
+$12a constant OCR5B \ Timer/Counter5 Output Compare
+$12c constant OCR5C \ Timer/Counter5 Output Compare
+$126 constant ICR5 \ Timer/Counter5 Input Capture R
+$73 constant TIMSK5 \ Timer/Counter5 Interrupt Mask
+ $c0 constant TIMSK5_Res \ Reserved Bit
+ 73 $c0 bitmask: TIMSK5.Res \ Reserved Bit
+ $20 constant TIMSK5_ICIE5 \ Timer/Counter5 Input Capture I
+ 73 $20 bitmask: TIMSK5.ICIE5 \ Timer/Counter5 Input Capture I
+ $10 constant TIMSK5_Res \ Reserved Bit
+ 73 $10 bitmask: TIMSK5.Res \ Reserved Bit
+ $8 constant TIMSK5_OCIE5C \ Timer/Counter5 Output Compare
+ 73 $8 bitmask: TIMSK5.OCIE5C \ Timer/Counter5 Output Compare
+ $4 constant TIMSK5_OCIE5B \ Timer/Counter5 Output Compare
+ 73 $4 bitmask: TIMSK5.OCIE5B \ Timer/Counter5 Output Compare
+ $2 constant TIMSK5_OCIE5A \ Timer/Counter5 Output Compare
+ 73 $2 bitmask: TIMSK5.OCIE5A \ Timer/Counter5 Output Compare
+ $1 constant TIMSK5_TOIE5 \ Timer/Counter5 Overflow Interr
+ 73 $1 bitmask: TIMSK5.TOIE5 \ Timer/Counter5 Overflow Interr
+$3a constant TIFR5 \ Timer/Counter5 Interrupt Flag
+ $c0 constant TIFR5_Res \ Reserved Bit
+ 3a $c0 bitmask: TIFR5.Res \ Reserved Bit
+ $20 constant TIFR5_ICF5 \ Timer/Counter5 Input Capture F
+ 3a $20 bitmask: TIFR5.ICF5 \ Timer/Counter5 Input Capture F
+ $10 constant TIFR5_Res \ Reserved Bit
+ 3a $10 bitmask: TIFR5.Res \ Reserved Bit
+ $8 constant TIFR5_OCF5C \ Timer/Counter5 Output Compare
+ 3a $8 bitmask: TIFR5.OCF5C \ Timer/Counter5 Output Compare
+ $4 constant TIFR5_OCF5B \ Timer/Counter5 Output Compare
+ 3a $4 bitmask: TIFR5.OCF5B \ Timer/Counter5 Output Compare
+ $2 constant TIFR5_OCF5A \ Timer/Counter5 Output Compare
+ 3a $2 bitmask: TIFR5.OCF5A \ Timer/Counter5 Output Compare
+ $1 constant TIFR5_TOV5 \ Timer/Counter5 Overflow Flag
+ 3a $1 bitmask: TIFR5.TOV5 \ Timer/Counter5 Overflow Flag
diff --git a/amforth-6.5/avr8/devices/atmega128rfr2/blocks/TRX24.frt b/amforth-6.5/avr8/devices/atmega128rfr2/blocks/TRX24.frt
new file mode 100644
index 0000000..820424b
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega128rfr2/blocks/TRX24.frt
@@ -0,0 +1,495 @@
+\ Generated automatically for atmega128rfr2
+\ #require bitnames.frt
+
+\ TRX24
+$138 constant PARCR \ Power Amplifier Ramp up/down C
+ $e0 constant PARCR_PALTD \ ext. PA Ramp Down Lead Time
+ 138 $e0 bitmask: PARCR.PALTD \ ext. PA Ramp Down Lead Time
+ $1c constant PARCR_PALTU \ ext. PA Ramp Up Lead Time
+ 138 $1c bitmask: PARCR.PALTU \ ext. PA Ramp Up Lead Time
+ $2 constant PARCR_PARDFI \ Power Amplifier Ramp Down Freq
+ 138 $2 bitmask: PARCR.PARDFI \ Power Amplifier Ramp Down Freq
+ $1 constant PARCR_PARUFI \ Power Amplifier Ramp Up Freque
+ 138 $1 bitmask: PARCR.PARUFI \ Power Amplifier Ramp Up Freque
+$10e constant MAFSA0L \ Transceiver MAC Short Address
+ $ff constant MAFSA0L_MAFSA0L \ MAC Short Address low Byte for
+ 10e $ff bitmask: MAFSA0L.MAFSA0L \ MAC Short Address low Byte for
+$10f constant MAFSA0H \ Transceiver MAC Short Address
+ $ff constant MAFSA0H_MAFSA0H \ MAC Short Address high Byte fo
+ 10f $ff bitmask: MAFSA0H.MAFSA0H \ MAC Short Address high Byte fo
+$110 constant MAFPA0L \ Transceiver Personal Area Netw
+ $ff constant MAFPA0L_MAFPA0L \ MAC Personal Area Network ID l
+ 110 $ff bitmask: MAFPA0L.MAFPA0L \ MAC Personal Area Network ID l
+$111 constant MAFPA0H \ Transceiver Personal Area Netw
+ $ff constant MAFPA0H_MAFPA0H \ MAC Personal Area Network ID h
+ 111 $ff bitmask: MAFPA0H.MAFPA0H \ MAC Personal Area Network ID h
+$112 constant MAFSA1L \ Transceiver MAC Short Address
+ $ff constant MAFSA1L_MAFSA1L \ MAC Short Address low Byte for
+ 112 $ff bitmask: MAFSA1L.MAFSA1L \ MAC Short Address low Byte for
+$113 constant MAFSA1H \ Transceiver MAC Short Address
+ $ff constant MAFSA1H_MAFSA1H \ MAC Short Address high Byte fo
+ 113 $ff bitmask: MAFSA1H.MAFSA1H \ MAC Short Address high Byte fo
+$114 constant MAFPA1L \ Transceiver Personal Area Netw
+ $ff constant MAFPA1L_MAFPA1L \ MAC Personal Area Network ID l
+ 114 $ff bitmask: MAFPA1L.MAFPA1L \ MAC Personal Area Network ID l
+$115 constant MAFPA1H \ Transceiver Personal Area Netw
+ $ff constant MAFPA1H_MAFPA1H \ MAC Personal Area Network ID h
+ 115 $ff bitmask: MAFPA1H.MAFPA1H \ MAC Personal Area Network ID h
+$116 constant MAFSA2L \ Transceiver MAC Short Address
+ $ff constant MAFSA2L_MAFSA2L \ MAC Short Address low Byte for
+ 116 $ff bitmask: MAFSA2L.MAFSA2L \ MAC Short Address low Byte for
+$117 constant MAFSA2H \ Transceiver MAC Short Address
+ $ff constant MAFSA2H_MAFSA2H \ MAC Short Address high Byte fo
+ 117 $ff bitmask: MAFSA2H.MAFSA2H \ MAC Short Address high Byte fo
+$118 constant MAFPA2L \ Transceiver Personal Area Netw
+ $ff constant MAFPA2L_MAFPA2L \ MAC Personal Area Network ID l
+ 118 $ff bitmask: MAFPA2L.MAFPA2L \ MAC Personal Area Network ID l
+$119 constant MAFPA2H \ Transceiver Personal Area Netw
+ $ff constant MAFPA2H_MAFPA2H \ MAC Personal Area Network ID h
+ 119 $ff bitmask: MAFPA2H.MAFPA2H \ MAC Personal Area Network ID h
+$11a constant MAFSA3L \ Transceiver MAC Short Address
+ $ff constant MAFSA3L_MAFSA3L \ MAC Short Address low Byte for
+ 11a $ff bitmask: MAFSA3L.MAFSA3L \ MAC Short Address low Byte for
+$11b constant MAFSA3H \ Transceiver MAC Short Address
+ $ff constant MAFSA3H_MAFSA3H \ MAC Short Address high Byte fo
+ 11b $ff bitmask: MAFSA3H.MAFSA3H \ MAC Short Address high Byte fo
+$11c constant MAFPA3L \ Transceiver Personal Area Netw
+ $ff constant MAFPA3L_MAFPA3L \ MAC Personal Area Network ID l
+ 11c $ff bitmask: MAFPA3L.MAFPA3L \ MAC Personal Area Network ID l
+$11d constant MAFPA3H \ Transceiver Personal Area Netw
+ $ff constant MAFPA3H_MAFPA3H \ MAC Personal Area Network ID h
+ 11d $ff bitmask: MAFPA3H.MAFPA3H \ MAC Personal Area Network ID h
+$10c constant MAFCR0 \ Multiple Address Filter Config
+ $f0 constant MAFCR0_Res \ Reserved Bit
+ 10c $f0 bitmask: MAFCR0.Res \ Reserved Bit
+ $8 constant MAFCR0_MAF3EN \ Multiple Address Filter 3 Enab
+ 10c $8 bitmask: MAFCR0.MAF3EN \ Multiple Address Filter 3 Enab
+ $4 constant MAFCR0_MAF2EN \ Multiple Address Filter 2 Enab
+ 10c $4 bitmask: MAFCR0.MAF2EN \ Multiple Address Filter 2 Enab
+ $2 constant MAFCR0_MAF1EN \ Multiple Address Filter 1 Enab
+ 10c $2 bitmask: MAFCR0.MAF1EN \ Multiple Address Filter 1 Enab
+ $1 constant MAFCR0_MAF0EN \ Multiple Address Filter 0 Enab
+ 10c $1 bitmask: MAFCR0.MAF0EN \ Multiple Address Filter 0 Enab
+$10d constant MAFCR1 \ Multiple Address Filter Config
+ $80 constant MAFCR1_AACK_3_SET_PD \ Set Data Pending bit for addre
+ 10d $80 bitmask: MAFCR1.AACK_3_SET_PD \ Set Data Pending bit for addre
+ $40 constant MAFCR1_AACK_3_I_AM_COORD \ Enable PAN Coordinator mode fo
+ 10d $40 bitmask: MAFCR1.AACK_3_I_AM_COORD \ Enable PAN Coordinator mode fo
+ $20 constant MAFCR1_AACK_2_SET_PD \ Set Data Pending bit for addre
+ 10d $20 bitmask: MAFCR1.AACK_2_SET_PD \ Set Data Pending bit for addre
+ $10 constant MAFCR1_AACK_2_I_AM_COORD \ Enable PAN Coordinator mode fo
+ 10d $10 bitmask: MAFCR1.AACK_2_I_AM_COORD \ Enable PAN Coordinator mode fo
+ $8 constant MAFCR1_AACK_1_SET_PD \ Set Data Pending bit for addre
+ 10d $8 bitmask: MAFCR1.AACK_1_SET_PD \ Set Data Pending bit for addre
+ $4 constant MAFCR1_AACK_1_I_AM_COORD \ Enable PAN Coordinator mode fo
+ 10d $4 bitmask: MAFCR1.AACK_1_I_AM_COORD \ Enable PAN Coordinator mode fo
+ $2 constant MAFCR1_AACK_0_SET_PD \ Set Data Pending bit for addre
+ 10d $2 bitmask: MAFCR1.AACK_0_SET_PD \ Set Data Pending bit for addre
+ $1 constant MAFCR1_AACK_0_I_AM_COORD \ Enable PAN Coordinator mode fo
+ 10d $1 bitmask: MAFCR1.AACK_0_I_AM_COORD \ Enable PAN Coordinator mode fo
+$13c constant AES_CTRL \ AES Control Register
+ $80 constant AES_CTRL_AES_REQUEST \ Request AES Operation.
+ 13c $80 bitmask: AES_CTRL.AES_REQUEST \ Request AES Operation.
+ $40 constant AES_CTRL_Res \ Reserved Bit
+ 13c $40 bitmask: AES_CTRL.Res \ Reserved Bit
+ $20 constant AES_CTRL_AES_MODE \ Set AES Operation Mode
+ 13c $20 bitmask: AES_CTRL.AES_MODE \ Set AES Operation Mode
+ $10 constant AES_CTRL_Res \ Reserved Bit
+ 13c $10 bitmask: AES_CTRL.Res \ Reserved Bit
+ $8 constant AES_CTRL_AES_DIR \ Set AES Operation Direction
+ 13c $8 bitmask: AES_CTRL.AES_DIR \ Set AES Operation Direction
+ $4 constant AES_CTRL_AES_IM \ AES Interrupt Enable
+ 13c $4 bitmask: AES_CTRL.AES_IM \ AES Interrupt Enable
+ $3 constant AES_CTRL_Res \ Reserved Bit
+ 13c $3 bitmask: AES_CTRL.Res \ Reserved Bit
+$13d constant AES_STATUS \ AES Status Register
+ $80 constant AES_STATUS_AES_ER \ AES Operation Finished with Er
+ 13d $80 bitmask: AES_STATUS.AES_ER \ AES Operation Finished with Er
+ $7e constant AES_STATUS_Res \ Reserved
+ 13d $7e bitmask: AES_STATUS.Res \ Reserved
+ $1 constant AES_STATUS_AES_DONE \ AES Operation Finished with Su
+ 13d $1 bitmask: AES_STATUS.AES_DONE \ AES Operation Finished with Su
+$13e constant AES_STATE \ AES Plain and Cipher Text Buff
+ $ff constant AES_STATE_AES_STATE \ AES Plain and Cipher Text Buff
+ 13e $ff bitmask: AES_STATE.AES_STATE \ AES Plain and Cipher Text Buff
+$13f constant AES_KEY \ AES Encryption and Decryption
+ $ff constant AES_KEY_AES_KEY \ AES Encryption/Decryption Key
+ 13f $ff bitmask: AES_KEY.AES_KEY \ AES Encryption/Decryption Key
+$141 constant TRX_STATUS \ Transceiver Status Register
+ $80 constant TRX_STATUS_CCA_DONE \ CCA Algorithm Status
+ 141 $80 bitmask: TRX_STATUS.CCA_DONE \ CCA Algorithm Status
+ $40 constant TRX_STATUS_CCA_STATUS \ CCA Status Result
+ 141 $40 bitmask: TRX_STATUS.CCA_STATUS \ CCA Status Result
+ $20 constant TRX_STATUS_TST_STATUS \ Test mode status
+ 141 $20 bitmask: TRX_STATUS.TST_STATUS \ Test mode status
+ $1f constant TRX_STATUS_TRX_STATUS \ Transceiver Main Status
+ 141 $1f bitmask: TRX_STATUS.TRX_STATUS \ Transceiver Main Status
+$142 constant TRX_STATE \ Transceiver State Control Regi
+ $e0 constant TRX_STATE_TRAC_STATUS \ Transaction Status
+ 142 $e0 bitmask: TRX_STATE.TRAC_STATUS \ Transaction Status
+ $1f constant TRX_STATE_TRX_CMD \ State Control Command
+ 142 $1f bitmask: TRX_STATE.TRX_CMD \ State Control Command
+$143 constant TRX_CTRL_0 \ Reserved
+ $80 constant TRX_CTRL_0_Res7 \ Reserved
+ 143 $80 bitmask: TRX_CTRL_0.Res7 \ Reserved
+ $40 constant TRX_CTRL_0_PMU_EN \ Enable Phase Measurement Unit
+ 143 $40 bitmask: TRX_CTRL_0.PMU_EN \ Enable Phase Measurement Unit
+ $20 constant TRX_CTRL_0_PMU_START \ Start of Phase Measurement Uni
+ 143 $20 bitmask: TRX_CTRL_0.PMU_START \ Start of Phase Measurement Uni
+ $10 constant TRX_CTRL_0_PMU_IF_INV \ PMU IF Inverse
+ 143 $10 bitmask: TRX_CTRL_0.PMU_IF_INV \ PMU IF Inverse
+ $f constant TRX_CTRL_0_Res \ Reserved
+ 143 $f bitmask: TRX_CTRL_0.Res \ Reserved
+$144 constant TRX_CTRL_1 \ Transceiver Control Register 1
+ $80 constant TRX_CTRL_1_PA_EXT_EN \ External PA support enable
+ 144 $80 bitmask: TRX_CTRL_1.PA_EXT_EN \ External PA support enable
+ $40 constant TRX_CTRL_1_IRQ_2_EXT_EN \ Connect Frame Start IRQ to TC1
+ 144 $40 bitmask: TRX_CTRL_1.IRQ_2_EXT_EN \ Connect Frame Start IRQ to TC1
+ $20 constant TRX_CTRL_1_TX_AUTO_CRC_ON \ Enable Automatic CRC Calculati
+ 144 $20 bitmask: TRX_CTRL_1.TX_AUTO_CRC_ON \ Enable Automatic CRC Calculati
+ $10 constant TRX_CTRL_1_PLL_TX_FLT \ Enable PLL TX filter
+ 144 $10 bitmask: TRX_CTRL_1.PLL_TX_FLT \ Enable PLL TX filter
+ $f constant TRX_CTRL_1_Res \ Reserved
+ 144 $f bitmask: TRX_CTRL_1.Res \ Reserved
+$145 constant PHY_TX_PWR \ Transceiver Transmit Power Con
+ $f0 constant PHY_TX_PWR_Res \ Reserved
+ 145 $f0 bitmask: PHY_TX_PWR.Res \ Reserved
+ $f constant PHY_TX_PWR_TX_PWR \ Transmit Power Setting
+ 145 $f bitmask: PHY_TX_PWR.TX_PWR \ Transmit Power Setting
+$146 constant PHY_RSSI \ Receiver Signal Strength Indic
+ $80 constant PHY_RSSI_RX_CRC_VALID \ Received Frame CRC Status
+ 146 $80 bitmask: PHY_RSSI.RX_CRC_VALID \ Received Frame CRC Status
+ $60 constant PHY_RSSI_RND_VALUE \ Random Value
+ 146 $60 bitmask: PHY_RSSI.RND_VALUE \ Random Value
+ $1f constant PHY_RSSI_RSSI \ Receiver Signal Strength Indic
+ 146 $1f bitmask: PHY_RSSI.RSSI \ Receiver Signal Strength Indic
+$147 constant PHY_ED_LEVEL \ Transceiver Energy Detection L
+ $ff constant PHY_ED_LEVEL_ED_LEVEL \ Energy Detection Level
+ 147 $ff bitmask: PHY_ED_LEVEL.ED_LEVEL \ Energy Detection Level
+$148 constant PHY_CC_CCA \ Transceiver Clear Channel Asse
+ $80 constant PHY_CC_CCA_CCA_REQUEST \ Manual CCA Measurement Request
+ 148 $80 bitmask: PHY_CC_CCA.CCA_REQUEST \ Manual CCA Measurement Request
+ $60 constant PHY_CC_CCA_CCA_MODE \ Select CCA Measurement Mode
+ 148 $60 bitmask: PHY_CC_CCA.CCA_MODE \ Select CCA Measurement Mode
+ $1f constant PHY_CC_CCA_CHANNEL \ RX/TX Channel Selection
+ 148 $1f bitmask: PHY_CC_CCA.CHANNEL \ RX/TX Channel Selection
+$149 constant CCA_THRES \ Transceiver CCA Threshold Sett
+ $f0 constant CCA_THRES_CCA_CS_THRES \ CS Threshold Level for CCA Mea
+ 149 $f0 bitmask: CCA_THRES.CCA_CS_THRES \ CS Threshold Level for CCA Mea
+ $f constant CCA_THRES_CCA_ED_THRES \ ED Threshold Level for CCA Mea
+ 149 $f bitmask: CCA_THRES.CCA_ED_THRES \ ED Threshold Level for CCA Mea
+$14a constant RX_CTRL \ Transceiver Receive Control Re
+ $f constant RX_CTRL_PDT_THRES \ Receiver Sensitivity Control
+ 14a $f bitmask: RX_CTRL.PDT_THRES \ Receiver Sensitivity Control
+$14b constant SFD_VALUE \ Start of Frame Delimiter Value
+ $ff constant SFD_VALUE_SFD_VALUE \ Start of Frame Delimiter Value
+ 14b $ff bitmask: SFD_VALUE.SFD_VALUE \ Start of Frame Delimiter Value
+$14c constant TRX_CTRL_2 \ Transceiver Control Register 2
+ $80 constant TRX_CTRL_2_RX_SAFE_MODE \ RX Safe Mode
+ 14c $80 bitmask: TRX_CTRL_2.RX_SAFE_MODE \ RX Safe Mode
+ $7c constant TRX_CTRL_2_Res \ Reserved
+ 14c $7c bitmask: TRX_CTRL_2.Res \ Reserved
+ $3 constant TRX_CTRL_2_OQPSK_DATA_RATE \ Data Rate Selection
+ 14c $3 bitmask: TRX_CTRL_2.OQPSK_DATA_RATE \ Data Rate Selection
+$14d constant ANT_DIV \ Antenna Diversity Control Regi
+ $80 constant ANT_DIV_ANT_SEL \ Antenna Diversity Antenna Stat
+ 14d $80 bitmask: ANT_DIV.ANT_SEL \ Antenna Diversity Antenna Stat
+ $70 constant ANT_DIV_Res \ Reserved
+ 14d $70 bitmask: ANT_DIV.Res \ Reserved
+ $8 constant ANT_DIV_ANT_DIV_EN \ Enable Antenna Diversity
+ 14d $8 bitmask: ANT_DIV.ANT_DIV_EN \ Enable Antenna Diversity
+ $4 constant ANT_DIV_ANT_EXT_SW_EN \ Enable External Antenna Switch
+ 14d $4 bitmask: ANT_DIV.ANT_EXT_SW_EN \ Enable External Antenna Switch
+ $3 constant ANT_DIV_ANT_CTRL \ Static Antenna Diversity Switc
+ 14d $3 bitmask: ANT_DIV.ANT_CTRL \ Static Antenna Diversity Switc
+$14e constant IRQ_MASK \ Transceiver Interrupt Enable R
+ $80 constant IRQ_MASK_AWAKE_EN \ Awake Interrupt Enable
+ 14e $80 bitmask: IRQ_MASK.AWAKE_EN \ Awake Interrupt Enable
+ $40 constant IRQ_MASK_TX_END_EN \ TX_END Interrupt Enable
+ 14e $40 bitmask: IRQ_MASK.TX_END_EN \ TX_END Interrupt Enable
+ $20 constant IRQ_MASK_AMI_EN \ Address Match Interrupt Enable
+ 14e $20 bitmask: IRQ_MASK.AMI_EN \ Address Match Interrupt Enable
+ $10 constant IRQ_MASK_CCA_ED_DONE_EN \ End of ED Measurement Interrup
+ 14e $10 bitmask: IRQ_MASK.CCA_ED_DONE_EN \ End of ED Measurement Interrup
+ $8 constant IRQ_MASK_RX_END_EN \ RX_END Interrupt Enable
+ 14e $8 bitmask: IRQ_MASK.RX_END_EN \ RX_END Interrupt Enable
+ $4 constant IRQ_MASK_RX_START_EN \ RX_START Interrupt Enable
+ 14e $4 bitmask: IRQ_MASK.RX_START_EN \ RX_START Interrupt Enable
+ $2 constant IRQ_MASK_PLL_UNLOCK_EN \ PLL Unlock Interrupt Enable
+ 14e $2 bitmask: IRQ_MASK.PLL_UNLOCK_EN \ PLL Unlock Interrupt Enable
+ $1 constant IRQ_MASK_PLL_LOCK_EN \ PLL Lock Interrupt Enable
+ 14e $1 bitmask: IRQ_MASK.PLL_LOCK_EN \ PLL Lock Interrupt Enable
+$14f constant IRQ_STATUS \ Transceiver Interrupt Status R
+ $80 constant IRQ_STATUS_AWAKE \ Awake Interrupt Status
+ 14f $80 bitmask: IRQ_STATUS.AWAKE \ Awake Interrupt Status
+ $40 constant IRQ_STATUS_TX_END \ TX_END Interrupt Status
+ 14f $40 bitmask: IRQ_STATUS.TX_END \ TX_END Interrupt Status
+ $20 constant IRQ_STATUS_AMI \ Address Match Interrupt Status
+ 14f $20 bitmask: IRQ_STATUS.AMI \ Address Match Interrupt Status
+ $10 constant IRQ_STATUS_CCA_ED_DONE \ End of ED Measurement Interrup
+ 14f $10 bitmask: IRQ_STATUS.CCA_ED_DONE \ End of ED Measurement Interrup
+ $8 constant IRQ_STATUS_RX_END \ RX_END Interrupt Status
+ 14f $8 bitmask: IRQ_STATUS.RX_END \ RX_END Interrupt Status
+ $4 constant IRQ_STATUS_RX_START \ RX_START Interrupt Status
+ 14f $4 bitmask: IRQ_STATUS.RX_START \ RX_START Interrupt Status
+ $2 constant IRQ_STATUS_PLL_UNLOCK \ PLL Unlock Interrupt Status
+ 14f $2 bitmask: IRQ_STATUS.PLL_UNLOCK \ PLL Unlock Interrupt Status
+ $1 constant IRQ_STATUS_PLL_LOCK \ PLL Lock Interrupt Status
+ 14f $1 bitmask: IRQ_STATUS.PLL_LOCK \ PLL Lock Interrupt Status
+$be constant IRQ_MASK1 \ Transceiver Interrupt Enable R
+ $e0 constant IRQ_MASK1_Res \ Reserved Bit
+ be $e0 bitmask: IRQ_MASK1.Res \ Reserved Bit
+ $10 constant IRQ_MASK1_MAF_3_AMI_EN \ Address Match Interrupt enable
+ be $10 bitmask: IRQ_MASK1.MAF_3_AMI_EN \ Address Match Interrupt enable
+ $8 constant IRQ_MASK1_MAF_2_AMI_EN \ Address Match Interrupt enable
+ be $8 bitmask: IRQ_MASK1.MAF_2_AMI_EN \ Address Match Interrupt enable
+ $4 constant IRQ_MASK1_MAF_1_AMI_EN \ Address Match Interrupt enable
+ be $4 bitmask: IRQ_MASK1.MAF_1_AMI_EN \ Address Match Interrupt enable
+ $2 constant IRQ_MASK1_MAF_0_AMI_EN \ Address Match Interrupt enable
+ be $2 bitmask: IRQ_MASK1.MAF_0_AMI_EN \ Address Match Interrupt enable
+ $1 constant IRQ_MASK1_TX_START_EN \ Transmit Start Interrupt enabl
+ be $1 bitmask: IRQ_MASK1.TX_START_EN \ Transmit Start Interrupt enabl
+$bf constant IRQ_STATUS1 \ Transceiver Interrupt Status R
+ $e0 constant IRQ_STATUS1_Res \ Reserved Bit
+ bf $e0 bitmask: IRQ_STATUS1.Res \ Reserved Bit
+ $10 constant IRQ_STATUS1_MAF_3_AMI \ Address Match Interrupt Status
+ bf $10 bitmask: IRQ_STATUS1.MAF_3_AMI \ Address Match Interrupt Status
+ $8 constant IRQ_STATUS1_MAF_2_AMI \ Address Match Interrupt Status
+ bf $8 bitmask: IRQ_STATUS1.MAF_2_AMI \ Address Match Interrupt Status
+ $4 constant IRQ_STATUS1_MAF_1_AMI \ Address Match Interrupt Status
+ bf $4 bitmask: IRQ_STATUS1.MAF_1_AMI \ Address Match Interrupt Status
+ $2 constant IRQ_STATUS1_MAF_0_AMI \ Address Match Interrupt Status
+ bf $2 bitmask: IRQ_STATUS1.MAF_0_AMI \ Address Match Interrupt Status
+ $1 constant IRQ_STATUS1_TX_START \ Transmit Start Interrupt Statu
+ bf $1 bitmask: IRQ_STATUS1.TX_START \ Transmit Start Interrupt Statu
+$150 constant VREG_CTRL \ Voltage Regulator Control and
+ $80 constant VREG_CTRL_AVREG_EXT \ Use External AVDD Regulator
+ 150 $80 bitmask: VREG_CTRL.AVREG_EXT \ Use External AVDD Regulator
+ $40 constant VREG_CTRL_AVDD_OK \ AVDD Supply Voltage Valid
+ 150 $40 bitmask: VREG_CTRL.AVDD_OK \ AVDD Supply Voltage Valid
+ $8 constant VREG_CTRL_DVREG_EXT \ Use External DVDD Regulator
+ 150 $8 bitmask: VREG_CTRL.DVREG_EXT \ Use External DVDD Regulator
+ $4 constant VREG_CTRL_DVDD_OK \ DVDD Supply Voltage Valid
+ 150 $4 bitmask: VREG_CTRL.DVDD_OK \ DVDD Supply Voltage Valid
+$151 constant BATMON \ Battery Monitor Control and St
+ $80 constant BATMON_BAT_LOW \ Battery Monitor Interrupt Stat
+ 151 $80 bitmask: BATMON.BAT_LOW \ Battery Monitor Interrupt Stat
+ $40 constant BATMON_BAT_LOW_EN \ Battery Monitor Interrupt Enab
+ 151 $40 bitmask: BATMON.BAT_LOW_EN \ Battery Monitor Interrupt Enab
+ $20 constant BATMON_BATMON_OK \ Battery Monitor Status
+ 151 $20 bitmask: BATMON.BATMON_OK \ Battery Monitor Status
+ $10 constant BATMON_BATMON_HR \ Battery Monitor Voltage Range
+ 151 $10 bitmask: BATMON.BATMON_HR \ Battery Monitor Voltage Range
+ $f constant BATMON_BATMON_VTH \ Battery Monitor Threshold Volt
+ 151 $f bitmask: BATMON.BATMON_VTH \ Battery Monitor Threshold Volt
+$152 constant XOSC_CTRL \ Crystal Oscillator Control Reg
+ $f0 constant XOSC_CTRL_XTAL_MODE \ Crystal Oscillator Operating M
+ 152 $f0 bitmask: XOSC_CTRL.XTAL_MODE \ Crystal Oscillator Operating M
+ $f constant XOSC_CTRL_XTAL_TRIM \ Crystal Oscillator Load Capaci
+ 152 $f bitmask: XOSC_CTRL.XTAL_TRIM \ Crystal Oscillator Load Capaci
+$153 constant CC_CTRL_0 \ Channel Control Register 0
+ $ff constant CC_CTRL_0_CC_NUMBER \ Channel Number
+ 153 $ff bitmask: CC_CTRL_0.CC_NUMBER \ Channel Number
+$154 constant CC_CTRL_1 \ Channel Control Register 1
+ $f constant CC_CTRL_1_CC_BAND \ Channel Band
+ 154 $f bitmask: CC_CTRL_1.CC_BAND \ Channel Band
+$155 constant RX_SYN \ Transceiver Receiver Sensitivi
+ $80 constant RX_SYN_RX_PDT_DIS \ Prevent Frame Reception
+ 155 $80 bitmask: RX_SYN.RX_PDT_DIS \ Prevent Frame Reception
+ $40 constant RX_SYN_RX_OVERRIDE \ Receiver Override Function
+ 155 $40 bitmask: RX_SYN.RX_OVERRIDE \ Receiver Override Function
+ $30 constant RX_SYN_Res \ Reserved
+ 155 $30 bitmask: RX_SYN.Res \ Reserved
+ $f constant RX_SYN_RX_PDT_LEVEL \ Reduce Receiver Sensitivity
+ 155 $f bitmask: RX_SYN.RX_PDT_LEVEL \ Reduce Receiver Sensitivity
+$156 constant TRX_RPC \ Transceiver Reduced Power Cons
+ $c0 constant TRX_RPC_RX_RPC_CTRL \ Smart Receiving Mode Timing
+ 156 $c0 bitmask: TRX_RPC.RX_RPC_CTRL \ Smart Receiving Mode Timing
+ $20 constant TRX_RPC_RX_RPC_EN \ Reciver Smart Receiving Mode E
+ 156 $20 bitmask: TRX_RPC.RX_RPC_EN \ Reciver Smart Receiving Mode E
+ $10 constant TRX_RPC_PDT_RPC_EN \ Smart Receiving Mode Reduced S
+ 156 $10 bitmask: TRX_RPC.PDT_RPC_EN \ Smart Receiving Mode Reduced S
+ $8 constant TRX_RPC_PLL_RPC_EN \ PLL Smart Receiving Mode Enabl
+ 156 $8 bitmask: TRX_RPC.PLL_RPC_EN \ PLL Smart Receiving Mode Enabl
+ $4 constant TRX_RPC_Res0 \ Reserved
+ 156 $4 bitmask: TRX_RPC.Res0 \ Reserved
+ $2 constant TRX_RPC_IPAN_RPC_EN \ Smart Receiving Mode IPAN Hand
+ 156 $2 bitmask: TRX_RPC.IPAN_RPC_EN \ Smart Receiving Mode IPAN Hand
+ $1 constant TRX_RPC_XAH_RPC_EN \ Smart Receiving in Extended Op
+ 156 $1 bitmask: TRX_RPC.XAH_RPC_EN \ Smart Receiving in Extended Op
+$157 constant XAH_CTRL_1 \ Transceiver Acknowledgment Fra
+ $c0 constant XAH_CTRL_1_Res \ Reserved Bit
+ 157 $c0 bitmask: XAH_CTRL_1.Res \ Reserved Bit
+ $20 constant XAH_CTRL_1_AACK_FLTR_RES_FT \ Filter Reserved Frames
+ 157 $20 bitmask: XAH_CTRL_1.AACK_FLTR_RES_FT \ Filter Reserved Frames
+ $10 constant XAH_CTRL_1_AACK_UPLD_RES_FT \ Process Reserved Frames
+ 157 $10 bitmask: XAH_CTRL_1.AACK_UPLD_RES_FT \ Process Reserved Frames
+ $8 constant XAH_CTRL_1_Res \ Reserved Bit
+ 157 $8 bitmask: XAH_CTRL_1.Res \ Reserved Bit
+ $4 constant XAH_CTRL_1_AACK_ACK_TIME \ Reduce Acknowledgment Time
+ 157 $4 bitmask: XAH_CTRL_1.AACK_ACK_TIME \ Reduce Acknowledgment Time
+ $2 constant XAH_CTRL_1_AACK_PROM_MODE \ Enable Promiscuous Mode
+ 157 $2 bitmask: XAH_CTRL_1.AACK_PROM_MODE \ Enable Promiscuous Mode
+ $1 constant XAH_CTRL_1_Res \ Reserved Bit
+ 157 $1 bitmask: XAH_CTRL_1.Res \ Reserved Bit
+$158 constant FTN_CTRL \ Transceiver Filter Tuning Cont
+ $80 constant FTN_CTRL_FTN_START \ Start Calibration Loop of Filt
+ 158 $80 bitmask: FTN_CTRL.FTN_START \ Start Calibration Loop of Filt
+$15a constant PLL_CF \ Transceiver Center Frequency C
+ $80 constant PLL_CF_PLL_CF_START \ Start Center Frequency Calibra
+ 15a $80 bitmask: PLL_CF.PLL_CF_START \ Start Center Frequency Calibra
+$15b constant PLL_DCU \ Transceiver Delay Cell Calibra
+ $80 constant PLL_DCU_PLL_DCU_START \ Start Delay Cell Calibration
+ 15b $80 bitmask: PLL_DCU.PLL_DCU_START \ Start Delay Cell Calibration
+$15c constant PART_NUM \ Device Identification Register
+ $ff constant PART_NUM_PART_NUM \ Part Number
+ 15c $ff bitmask: PART_NUM.PART_NUM \ Part Number
+$15d constant VERSION_NUM \ Device Identification Register
+ $ff constant VERSION_NUM_VERSION_NUM \ Version Number
+ 15d $ff bitmask: VERSION_NUM.VERSION_NUM \ Version Number
+$15e constant MAN_ID_0 \ Device Identification Register
+ $80 constant MAN_ID_0_MAN_ID_07 \ Manufacturer ID (Low Byte)
+ 15e $80 bitmask: MAN_ID_0.MAN_ID_07 \ Manufacturer ID (Low Byte)
+ $40 constant MAN_ID_0_MAN_ID_06 \ Manufacturer ID (Low Byte)
+ 15e $40 bitmask: MAN_ID_0.MAN_ID_06 \ Manufacturer ID (Low Byte)
+ $20 constant MAN_ID_0_MAN_ID_05 \ Manufacturer ID (Low Byte)
+ 15e $20 bitmask: MAN_ID_0.MAN_ID_05 \ Manufacturer ID (Low Byte)
+ $10 constant MAN_ID_0_MAN_ID_04 \ Manufacturer ID (Low Byte)
+ 15e $10 bitmask: MAN_ID_0.MAN_ID_04 \ Manufacturer ID (Low Byte)
+ $8 constant MAN_ID_0_MAN_ID_03 \ Manufacturer ID (Low Byte)
+ 15e $8 bitmask: MAN_ID_0.MAN_ID_03 \ Manufacturer ID (Low Byte)
+ $4 constant MAN_ID_0_MAN_ID_02 \ Manufacturer ID (Low Byte)
+ 15e $4 bitmask: MAN_ID_0.MAN_ID_02 \ Manufacturer ID (Low Byte)
+ $2 constant MAN_ID_0_MAN_ID_01 \ Manufacturer ID (Low Byte)
+ 15e $2 bitmask: MAN_ID_0.MAN_ID_01 \ Manufacturer ID (Low Byte)
+ $1 constant MAN_ID_0_MAN_ID_00 \ Manufacturer ID (Low Byte)
+ 15e $1 bitmask: MAN_ID_0.MAN_ID_00 \ Manufacturer ID (Low Byte)
+$15f constant MAN_ID_1 \ Device Identification Register
+ $ff constant MAN_ID_1_MAN_ID_ \ Manufacturer ID (High Byte)
+ 15f $ff bitmask: MAN_ID_1.MAN_ID_ \ Manufacturer ID (High Byte)
+$160 constant SHORT_ADDR_0 \ Transceiver MAC Short Address
+ $80 constant SHORT_ADDR_0_SHORT_ADDR_07 \ MAC Short Address
+ 160 $80 bitmask: SHORT_ADDR_0.SHORT_ADDR_07 \ MAC Short Address
+ $40 constant SHORT_ADDR_0_SHORT_ADDR_06 \ MAC Short Address
+ 160 $40 bitmask: SHORT_ADDR_0.SHORT_ADDR_06 \ MAC Short Address
+ $20 constant SHORT_ADDR_0_SHORT_ADDR_05 \ MAC Short Address
+ 160 $20 bitmask: SHORT_ADDR_0.SHORT_ADDR_05 \ MAC Short Address
+ $10 constant SHORT_ADDR_0_SHORT_ADDR_04 \ MAC Short Address
+ 160 $10 bitmask: SHORT_ADDR_0.SHORT_ADDR_04 \ MAC Short Address
+ $8 constant SHORT_ADDR_0_SHORT_ADDR_03 \ MAC Short Address
+ 160 $8 bitmask: SHORT_ADDR_0.SHORT_ADDR_03 \ MAC Short Address
+ $4 constant SHORT_ADDR_0_SHORT_ADDR_02 \ MAC Short Address
+ 160 $4 bitmask: SHORT_ADDR_0.SHORT_ADDR_02 \ MAC Short Address
+ $2 constant SHORT_ADDR_0_SHORT_ADDR_01 \ MAC Short Address
+ 160 $2 bitmask: SHORT_ADDR_0.SHORT_ADDR_01 \ MAC Short Address
+ $1 constant SHORT_ADDR_0_SHORT_ADDR_00 \ MAC Short Address
+ 160 $1 bitmask: SHORT_ADDR_0.SHORT_ADDR_00 \ MAC Short Address
+$161 constant SHORT_ADDR_1 \ Transceiver MAC Short Address
+ $ff constant SHORT_ADDR_1_SHORT_ADDR_ \ MAC Short Address
+ 161 $ff bitmask: SHORT_ADDR_1.SHORT_ADDR_ \ MAC Short Address
+$162 constant PAN_ID_0 \ Transceiver Personal Area Netw
+ $80 constant PAN_ID_0_PAN_ID_07 \ MAC Personal Area Network ID
+ 162 $80 bitmask: PAN_ID_0.PAN_ID_07 \ MAC Personal Area Network ID
+ $40 constant PAN_ID_0_PAN_ID_06 \ MAC Personal Area Network ID
+ 162 $40 bitmask: PAN_ID_0.PAN_ID_06 \ MAC Personal Area Network ID
+ $20 constant PAN_ID_0_PAN_ID_05 \ MAC Personal Area Network ID
+ 162 $20 bitmask: PAN_ID_0.PAN_ID_05 \ MAC Personal Area Network ID
+ $10 constant PAN_ID_0_PAN_ID_04 \ MAC Personal Area Network ID
+ 162 $10 bitmask: PAN_ID_0.PAN_ID_04 \ MAC Personal Area Network ID
+ $8 constant PAN_ID_0_PAN_ID_03 \ MAC Personal Area Network ID
+ 162 $8 bitmask: PAN_ID_0.PAN_ID_03 \ MAC Personal Area Network ID
+ $4 constant PAN_ID_0_PAN_ID_02 \ MAC Personal Area Network ID
+ 162 $4 bitmask: PAN_ID_0.PAN_ID_02 \ MAC Personal Area Network ID
+ $2 constant PAN_ID_0_PAN_ID_01 \ MAC Personal Area Network ID
+ 162 $2 bitmask: PAN_ID_0.PAN_ID_01 \ MAC Personal Area Network ID
+ $1 constant PAN_ID_0_PAN_ID_00 \ MAC Personal Area Network ID
+ 162 $1 bitmask: PAN_ID_0.PAN_ID_00 \ MAC Personal Area Network ID
+$163 constant PAN_ID_1 \ Transceiver Personal Area Netw
+ $ff constant PAN_ID_1_PAN_ID_ \ MAC Personal Area Network ID
+ 163 $ff bitmask: PAN_ID_1.PAN_ID_ \ MAC Personal Area Network ID
+$164 constant IEEE_ADDR_0 \ Transceiver MAC IEEE Address R
+ $80 constant IEEE_ADDR_0_IEEE_ADDR_07 \ MAC IEEE Address
+ 164 $80 bitmask: IEEE_ADDR_0.IEEE_ADDR_07 \ MAC IEEE Address
+ $40 constant IEEE_ADDR_0_IEEE_ADDR_06 \ MAC IEEE Address
+ 164 $40 bitmask: IEEE_ADDR_0.IEEE_ADDR_06 \ MAC IEEE Address
+ $20 constant IEEE_ADDR_0_IEEE_ADDR_05 \ MAC IEEE Address
+ 164 $20 bitmask: IEEE_ADDR_0.IEEE_ADDR_05 \ MAC IEEE Address
+ $10 constant IEEE_ADDR_0_IEEE_ADDR_04 \ MAC IEEE Address
+ 164 $10 bitmask: IEEE_ADDR_0.IEEE_ADDR_04 \ MAC IEEE Address
+ $8 constant IEEE_ADDR_0_IEEE_ADDR_03 \ MAC IEEE Address
+ 164 $8 bitmask: IEEE_ADDR_0.IEEE_ADDR_03 \ MAC IEEE Address
+ $4 constant IEEE_ADDR_0_IEEE_ADDR_02 \ MAC IEEE Address
+ 164 $4 bitmask: IEEE_ADDR_0.IEEE_ADDR_02 \ MAC IEEE Address
+ $2 constant IEEE_ADDR_0_IEEE_ADDR_01 \ MAC IEEE Address
+ 164 $2 bitmask: IEEE_ADDR_0.IEEE_ADDR_01 \ MAC IEEE Address
+ $1 constant IEEE_ADDR_0_IEEE_ADDR_00 \ MAC IEEE Address
+ 164 $1 bitmask: IEEE_ADDR_0.IEEE_ADDR_00 \ MAC IEEE Address
+$165 constant IEEE_ADDR_1 \ Transceiver MAC IEEE Address R
+ $ff constant IEEE_ADDR_1_IEEE_ADDR_ \ MAC IEEE Address
+ 165 $ff bitmask: IEEE_ADDR_1.IEEE_ADDR_ \ MAC IEEE Address
+$166 constant IEEE_ADDR_2 \ Transceiver MAC IEEE Address R
+ $ff constant IEEE_ADDR_2_IEEE_ADDR_ \ MAC IEEE Address
+ 166 $ff bitmask: IEEE_ADDR_2.IEEE_ADDR_ \ MAC IEEE Address
+$167 constant IEEE_ADDR_3 \ Transceiver MAC IEEE Address R
+ $ff constant IEEE_ADDR_3_IEEE_ADDR_ \ MAC IEEE Address
+ 167 $ff bitmask: IEEE_ADDR_3.IEEE_ADDR_ \ MAC IEEE Address
+$168 constant IEEE_ADDR_4 \ Transceiver MAC IEEE Address R
+ $ff constant IEEE_ADDR_4_IEEE_ADDR_ \ MAC IEEE Address
+ 168 $ff bitmask: IEEE_ADDR_4.IEEE_ADDR_ \ MAC IEEE Address
+$169 constant IEEE_ADDR_5 \ Transceiver MAC IEEE Address R
+ $ff constant IEEE_ADDR_5_IEEE_ADDR_ \ MAC IEEE Address
+ 169 $ff bitmask: IEEE_ADDR_5.IEEE_ADDR_ \ MAC IEEE Address
+$16a constant IEEE_ADDR_6 \ Transceiver MAC IEEE Address R
+ $ff constant IEEE_ADDR_6_IEEE_ADDR_ \ MAC IEEE Address
+ 16a $ff bitmask: IEEE_ADDR_6.IEEE_ADDR_ \ MAC IEEE Address
+$16b constant IEEE_ADDR_7 \ Transceiver MAC IEEE Address R
+ $ff constant IEEE_ADDR_7_IEEE_ADDR_ \ MAC IEEE Address
+ 16b $ff bitmask: IEEE_ADDR_7.IEEE_ADDR_ \ MAC IEEE Address
+$16c constant XAH_CTRL_0 \ Transceiver Extended Operating
+ $f0 constant XAH_CTRL_0_MAX_FRAME_RETRIES \ Maximum Number of Frame Re-tra
+ 16c $f0 bitmask: XAH_CTRL_0.MAX_FRAME_RETRIES \ Maximum Number of Frame Re-tra
+ $e constant XAH_CTRL_0_MAX_CSMA_RETRIES \ Maximum Number of CSMA-CA Proc
+ 16c $e bitmask: XAH_CTRL_0.MAX_CSMA_RETRIES \ Maximum Number of CSMA-CA Proc
+ $1 constant XAH_CTRL_0_SLOTTED_OPERATION \ Set Slotted Acknowledgment
+ 16c $1 bitmask: XAH_CTRL_0.SLOTTED_OPERATION \ Set Slotted Acknowledgment
+$16d constant CSMA_SEED_0 \ Transceiver CSMA-CA Random Num
+ $80 constant CSMA_SEED_0_CSMA_SEED_07 \ Seed Value for CSMA Random Num
+ 16d $80 bitmask: CSMA_SEED_0.CSMA_SEED_07 \ Seed Value for CSMA Random Num
+ $40 constant CSMA_SEED_0_CSMA_SEED_06 \ Seed Value for CSMA Random Num
+ 16d $40 bitmask: CSMA_SEED_0.CSMA_SEED_06 \ Seed Value for CSMA Random Num
+ $20 constant CSMA_SEED_0_CSMA_SEED_05 \ Seed Value for CSMA Random Num
+ 16d $20 bitmask: CSMA_SEED_0.CSMA_SEED_05 \ Seed Value for CSMA Random Num
+ $10 constant CSMA_SEED_0_CSMA_SEED_04 \ Seed Value for CSMA Random Num
+ 16d $10 bitmask: CSMA_SEED_0.CSMA_SEED_04 \ Seed Value for CSMA Random Num
+ $8 constant CSMA_SEED_0_CSMA_SEED_03 \ Seed Value for CSMA Random Num
+ 16d $8 bitmask: CSMA_SEED_0.CSMA_SEED_03 \ Seed Value for CSMA Random Num
+ $4 constant CSMA_SEED_0_CSMA_SEED_02 \ Seed Value for CSMA Random Num
+ 16d $4 bitmask: CSMA_SEED_0.CSMA_SEED_02 \ Seed Value for CSMA Random Num
+ $2 constant CSMA_SEED_0_CSMA_SEED_01 \ Seed Value for CSMA Random Num
+ 16d $2 bitmask: CSMA_SEED_0.CSMA_SEED_01 \ Seed Value for CSMA Random Num
+ $1 constant CSMA_SEED_0_CSMA_SEED_00 \ Seed Value for CSMA Random Num
+ 16d $1 bitmask: CSMA_SEED_0.CSMA_SEED_00 \ Seed Value for CSMA Random Num
+$16e constant CSMA_SEED_1 \ Transceiver Acknowledgment Fra
+ $c0 constant CSMA_SEED_1_AACK_FVN_MODE \ Acknowledgment Frame Filter Mo
+ 16e $c0 bitmask: CSMA_SEED_1.AACK_FVN_MODE \ Acknowledgment Frame Filter Mo
+ $20 constant CSMA_SEED_1_AACK_SET_PD \ Set Frame Pending Sub-field
+ 16e $20 bitmask: CSMA_SEED_1.AACK_SET_PD \ Set Frame Pending Sub-field
+ $10 constant CSMA_SEED_1_AACK_DIS_ACK \ Disable Acknowledgment Frame T
+ 16e $10 bitmask: CSMA_SEED_1.AACK_DIS_ACK \ Disable Acknowledgment Frame T
+ $8 constant CSMA_SEED_1_AACK_I_AM_COORD \ Set Personal Area Network Coor
+ 16e $8 bitmask: CSMA_SEED_1.AACK_I_AM_COORD \ Set Personal Area Network Coor
+ $7 constant CSMA_SEED_1_CSMA_SEED_1 \ Seed Value for CSMA Random Num
+ 16e $7 bitmask: CSMA_SEED_1.CSMA_SEED_1 \ Seed Value for CSMA Random Num
+$16f constant CSMA_BE \ Transceiver CSMA-CA Back-off E
+ $f0 constant CSMA_BE_MAX_BE \ Maximum Back-off Exponent
+ 16f $f0 bitmask: CSMA_BE.MAX_BE \ Maximum Back-off Exponent
+ $f constant CSMA_BE_MIN_BE \ Minimum Back-off Exponent
+ 16f $f bitmask: CSMA_BE.MIN_BE \ Minimum Back-off Exponent
+$176 constant TST_CTRL_DIGI \ Transceiver Digital Test Contr
+ $f constant TST_CTRL_DIGI_TST_CTRL_DIG \ Digital Test Controller Regist
+ 176 $f bitmask: TST_CTRL_DIGI.TST_CTRL_DIG \ Digital Test Controller Regist
+$17b constant TST_RX_LENGTH \ Transceiver Received Frame Len
+ $ff constant TST_RX_LENGTH_RX_LENGTH \ Received Frame Length
+ 17b $ff bitmask: TST_RX_LENGTH.RX_LENGTH \ Received Frame Length
+$180 constant TRXFBST \ Start of frame buffer
+$1ff constant TRXFBEND \ End of frame buffer
diff --git a/amforth-6.5/avr8/devices/atmega128rfr2/blocks/TWI.frt b/amforth-6.5/avr8/devices/atmega128rfr2/blocks/TWI.frt
new file mode 100644
index 0000000..e4d558c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega128rfr2/blocks/TWI.frt
@@ -0,0 +1,40 @@
+\ Generated automatically for atmega128rfr2
+\ #require bitnames.frt
+
+\ TWI
+$bd constant TWAMR \ TWI (Slave) Address Mask Regis
+ $fe constant TWAMR_TWAM \ TWI Address Mask
+ bd $fe bitmask: TWAMR.TWAM \ TWI Address Mask
+ $1 constant TWAMR_Res \ Reserved Bit
+ bd $1 bitmask: TWAMR.Res \ Reserved Bit
+$b8 constant TWBR \ TWI Bit Rate Register
+$bc constant TWCR \ TWI Control Register
+ $80 constant TWCR_TWINT \ TWI Interrupt Flag
+ bc $80 bitmask: TWCR.TWINT \ TWI Interrupt Flag
+ $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
+ bc $40 bitmask: TWCR.TWEA \ TWI Enable Acknowledge Bit
+ $20 constant TWCR_TWSTA \ TWI START Condition Bit
+ bc $20 bitmask: TWCR.TWSTA \ TWI START Condition Bit
+ $10 constant TWCR_TWSTO \ TWI STOP Condition Bit
+ bc $10 bitmask: TWCR.TWSTO \ TWI STOP Condition Bit
+ $8 constant TWCR_TWWC \ TWI Write Collision Flag
+ bc $8 bitmask: TWCR.TWWC \ TWI Write Collision Flag
+ $4 constant TWCR_TWEN \ TWI Enable Bit
+ bc $4 bitmask: TWCR.TWEN \ TWI Enable Bit
+ $2 constant TWCR_Res \ Reserved Bit
+ bc $2 bitmask: TWCR.Res \ Reserved Bit
+ $1 constant TWCR_TWIE \ TWI Interrupt Enable
+ bc $1 bitmask: TWCR.TWIE \ TWI Interrupt Enable
+$b9 constant TWSR \ TWI Status Register
+ $f8 constant TWSR_TWS \ TWI Status
+ b9 $f8 bitmask: TWSR.TWS \ TWI Status
+ $4 constant TWSR_Res \ Reserved Bit
+ b9 $4 bitmask: TWSR.Res \ Reserved Bit
+ $3 constant TWSR_TWPS \ TWI Prescaler Bits
+ b9 $3 bitmask: TWSR.TWPS \ TWI Prescaler Bits
+$bb constant TWDR \ TWI Data Register
+$ba constant TWAR \ TWI (Slave) Address Register
+ $fe constant TWAR_TWA \ TWI (Slave) Address
+ ba $fe bitmask: TWAR.TWA \ TWI (Slave) Address
+ $1 constant TWAR_TWGCE \ TWI General Call Recognition E
+ ba $1 bitmask: TWAR.TWGCE \ TWI General Call Recognition E
diff --git a/amforth-6.5/avr8/devices/atmega128rfr2/blocks/USART0.frt b/amforth-6.5/avr8/devices/atmega128rfr2/blocks/USART0.frt
new file mode 100644
index 0000000..46bedc3
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega128rfr2/blocks/USART0.frt
@@ -0,0 +1,51 @@
+\ Generated automatically for atmega128rfr2
+\ #require bitnames.frt
+
+\ USART0
+$c6 constant UDR0 \ USART0 I/O Data Register
+$c0 constant UCSR0A \ USART0 Control and Status Regi
+ $80 constant UCSR0A_RXC0 \ USART Receive Complete
+ c0 $80 bitmask: UCSR0A.RXC0 \ USART Receive Complete
+ $40 constant UCSR0A_TXC0 \ USART Transmit Complete
+ c0 $40 bitmask: UCSR0A.TXC0 \ USART Transmit Complete
+ $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
+ c0 $20 bitmask: UCSR0A.UDRE0 \ USART Data Register Empty
+ $10 constant UCSR0A_FE0 \ Frame Error
+ c0 $10 bitmask: UCSR0A.FE0 \ Frame Error
+ $8 constant UCSR0A_DOR0 \ Data OverRun
+ c0 $8 bitmask: UCSR0A.DOR0 \ Data OverRun
+ $4 constant UCSR0A_UPE0 \ USART Parity Error
+ c0 $4 bitmask: UCSR0A.UPE0 \ USART Parity Error
+ $2 constant UCSR0A_U2X0 \ Double the USART Transmission
+ c0 $2 bitmask: UCSR0A.U2X0 \ Double the USART Transmission
+ $1 constant UCSR0A_MPCM0 \ Multi-processor Communication
+ c0 $1 bitmask: UCSR0A.MPCM0 \ Multi-processor Communication
+$c1 constant UCSR0B \ USART0 Control and Status Regi
+ $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
+ c1 $80 bitmask: UCSR0B.RXCIE0 \ RX Complete Interrupt Enable
+ $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
+ c1 $40 bitmask: UCSR0B.TXCIE0 \ TX Complete Interrupt Enable
+ $20 constant UCSR0B_UDRIE0 \ USART Data Register Empty Inte
+ c1 $20 bitmask: UCSR0B.UDRIE0 \ USART Data Register Empty Inte
+ $10 constant UCSR0B_RXEN0 \ Receiver Enable
+ c1 $10 bitmask: UCSR0B.RXEN0 \ Receiver Enable
+ $8 constant UCSR0B_TXEN0 \ Transmitter Enable
+ c1 $8 bitmask: UCSR0B.TXEN0 \ Transmitter Enable
+ $4 constant UCSR0B_UCSZ02 \ Character Size
+ c1 $4 bitmask: UCSR0B.UCSZ02 \ Character Size
+ $2 constant UCSR0B_RXB80 \ Receive Data Bit 8
+ c1 $2 bitmask: UCSR0B.RXB80 \ Receive Data Bit 8
+ $1 constant UCSR0B_TXB80 \ Transmit Data Bit 8
+ c1 $1 bitmask: UCSR0B.TXB80 \ Transmit Data Bit 8
+$c2 constant UCSR0C \ USART0 Control and Status Regi
+ $c0 constant UCSR0C_UMSEL0 \ USART Mode Select
+ c2 $c0 bitmask: UCSR0C.UMSEL0 \ USART Mode Select
+ $30 constant UCSR0C_UPM0 \ Parity Mode
+ c2 $30 bitmask: UCSR0C.UPM0 \ Parity Mode
+ $8 constant UCSR0C_USBS0 \ Stop Bit Select
+ c2 $8 bitmask: UCSR0C.USBS0 \ Stop Bit Select
+ $6 constant UCSR0C_UCSZ0 \ Character Size
+ c2 $6 bitmask: UCSR0C.UCSZ0 \ Character Size
+ $1 constant UCSR0C_UCPOL0 \ Clock Polarity
+ c2 $1 bitmask: UCSR0C.UCPOL0 \ Clock Polarity
+$c4 constant UBRR0 \ USART0 Baud Rate Register Byt
diff --git a/amforth-6.5/avr8/devices/atmega128rfr2/blocks/USART0_SPI.frt b/amforth-6.5/avr8/devices/atmega128rfr2/blocks/USART0_SPI.frt
new file mode 100644
index 0000000..f5992b7
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega128rfr2/blocks/USART0_SPI.frt
@@ -0,0 +1,29 @@
+\ Generated automatically for atmega128rfr2
+\ #require bitnames.frt
+
+\ USART0_SPI
+$c0 constant UCSR0A \ USART0 MSPIM Control and Statu
+ $80 constant UCSR0A_RXC0 \ USART Receive Complete
+ c0 $80 bitmask: UCSR0A.RXC0 \ USART Receive Complete
+ $40 constant UCSR0A_TXC0 \ USART Transmit Complete
+ c0 $40 bitmask: UCSR0A.TXC0 \ USART Transmit Complete
+ $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
+ c0 $20 bitmask: UCSR0A.UDRE0 \ USART Data Register Empty
+$c1 constant UCSR0B \ USART0 MSPIM Control and Statu
+ $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
+ c1 $80 bitmask: UCSR0B.RXCIE0 \ RX Complete Interrupt Enable
+ $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
+ c1 $40 bitmask: UCSR0B.TXCIE0 \ TX Complete Interrupt Enable
+ $20 constant UCSR0B_UDRIE0 \ USART Data Register Empty Inte
+ c1 $20 bitmask: UCSR0B.UDRIE0 \ USART Data Register Empty Inte
+ $10 constant UCSR0B_RXEN0 \ Receiver Enable
+ c1 $10 bitmask: UCSR0B.RXEN0 \ Receiver Enable
+ $8 constant UCSR0B_TXEN0 \ Transmitter Enable
+ c1 $8 bitmask: UCSR0B.TXEN0 \ Transmitter Enable
+$c2 constant UCSR0C \ USART0 MSPIM Control and Statu
+ $4 constant UCSR0C_UDORD0 \ Data Order
+ c2 $4 bitmask: UCSR0C.UDORD0 \ Data Order
+ $2 constant UCSR0C_UCPHA0 \ Clock Phase
+ c2 $2 bitmask: UCSR0C.UCPHA0 \ Clock Phase
+ $1 constant UCSR0C_UCPOL0 \ Clock Polarity
+ c2 $1 bitmask: UCSR0C.UCPOL0 \ Clock Polarity
diff --git a/amforth-6.5/avr8/devices/atmega128rfr2/blocks/USART1.frt b/amforth-6.5/avr8/devices/atmega128rfr2/blocks/USART1.frt
new file mode 100644
index 0000000..d884da0
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega128rfr2/blocks/USART1.frt
@@ -0,0 +1,51 @@
+\ Generated automatically for atmega128rfr2
+\ #require bitnames.frt
+
+\ USART1
+$ce constant UDR1 \ USART1 I/O Data Register
+$c8 constant UCSR1A \ USART1 Control and Status Regi
+ $80 constant UCSR1A_RXC1 \ USART Receive Complete
+ c8 $80 bitmask: UCSR1A.RXC1 \ USART Receive Complete
+ $40 constant UCSR1A_TXC1 \ USART Transmit Complete
+ c8 $40 bitmask: UCSR1A.TXC1 \ USART Transmit Complete
+ $20 constant UCSR1A_UDRE1 \ USART Data Register Empty
+ c8 $20 bitmask: UCSR1A.UDRE1 \ USART Data Register Empty
+ $10 constant UCSR1A_FE1 \ Frame Error
+ c8 $10 bitmask: UCSR1A.FE1 \ Frame Error
+ $8 constant UCSR1A_DOR1 \ Data OverRun
+ c8 $8 bitmask: UCSR1A.DOR1 \ Data OverRun
+ $4 constant UCSR1A_UPE1 \ USART Parity Error
+ c8 $4 bitmask: UCSR1A.UPE1 \ USART Parity Error
+ $2 constant UCSR1A_U2X1 \ Double the USART Transmission
+ c8 $2 bitmask: UCSR1A.U2X1 \ Double the USART Transmission
+ $1 constant UCSR1A_MPCM1 \ Multi-processor Communication
+ c8 $1 bitmask: UCSR1A.MPCM1 \ Multi-processor Communication
+$c9 constant UCSR1B \ USART1 Control and Status Regi
+ $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable
+ c9 $80 bitmask: UCSR1B.RXCIE1 \ RX Complete Interrupt Enable
+ $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable
+ c9 $40 bitmask: UCSR1B.TXCIE1 \ TX Complete Interrupt Enable
+ $20 constant UCSR1B_UDRIE1 \ USART Data Register Empty Inte
+ c9 $20 bitmask: UCSR1B.UDRIE1 \ USART Data Register Empty Inte
+ $10 constant UCSR1B_RXEN1 \ Receiver Enable
+ c9 $10 bitmask: UCSR1B.RXEN1 \ Receiver Enable
+ $8 constant UCSR1B_TXEN1 \ Transmitter Enable
+ c9 $8 bitmask: UCSR1B.TXEN1 \ Transmitter Enable
+ $4 constant UCSR1B_UCSZ12 \ Character Size
+ c9 $4 bitmask: UCSR1B.UCSZ12 \ Character Size
+ $2 constant UCSR1B_RXB81 \ Receive Data Bit 8
+ c9 $2 bitmask: UCSR1B.RXB81 \ Receive Data Bit 8
+ $1 constant UCSR1B_TXB81 \ Transmit Data Bit 8
+ c9 $1 bitmask: UCSR1B.TXB81 \ Transmit Data Bit 8
+$ca constant UCSR1C \ USART1 Control and Status Regi
+ $c0 constant UCSR1C_UMSEL1 \ USART Mode Select
+ ca $c0 bitmask: UCSR1C.UMSEL1 \ USART Mode Select
+ $30 constant UCSR1C_UPM1 \ Parity Mode
+ ca $30 bitmask: UCSR1C.UPM1 \ Parity Mode
+ $8 constant UCSR1C_USBS1 \ Stop Bit Select
+ ca $8 bitmask: UCSR1C.USBS1 \ Stop Bit Select
+ $6 constant UCSR1C_UCSZ1 \ Character Size
+ ca $6 bitmask: UCSR1C.UCSZ1 \ Character Size
+ $1 constant UCSR1C_UCPOL1 \ Clock Polarity
+ ca $1 bitmask: UCSR1C.UCPOL1 \ Clock Polarity
+$cc constant UBRR1 \ USART1 Baud Rate Register Byt
diff --git a/amforth-6.5/avr8/devices/atmega128rfr2/blocks/USART1_SPI.frt b/amforth-6.5/avr8/devices/atmega128rfr2/blocks/USART1_SPI.frt
new file mode 100644
index 0000000..29dbd95
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega128rfr2/blocks/USART1_SPI.frt
@@ -0,0 +1,29 @@
+\ Generated automatically for atmega128rfr2
+\ #require bitnames.frt
+
+\ USART1_SPI
+$c8 constant UCSR1A \ USART1 MSPIM Control and Statu
+ $80 constant UCSR1A_RXC1 \ USART Receive Complete
+ c8 $80 bitmask: UCSR1A.RXC1 \ USART Receive Complete
+ $40 constant UCSR1A_TXC1 \ USART Transmit Complete
+ c8 $40 bitmask: UCSR1A.TXC1 \ USART Transmit Complete
+ $20 constant UCSR1A_UDRE1 \ USART Data Register Empty
+ c8 $20 bitmask: UCSR1A.UDRE1 \ USART Data Register Empty
+$c9 constant UCSR1B \ USART1 MSPIM Control and Statu
+ $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable
+ c9 $80 bitmask: UCSR1B.RXCIE1 \ RX Complete Interrupt Enable
+ $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable
+ c9 $40 bitmask: UCSR1B.TXCIE1 \ TX Complete Interrupt Enable
+ $20 constant UCSR1B_UDRIE1 \ USART Data Register Empty Inte
+ c9 $20 bitmask: UCSR1B.UDRIE1 \ USART Data Register Empty Inte
+ $10 constant UCSR1B_RXEN1 \ Receiver Enable
+ c9 $10 bitmask: UCSR1B.RXEN1 \ Receiver Enable
+ $8 constant UCSR1B_TXEN1 \ Transmitter Enable
+ c9 $8 bitmask: UCSR1B.TXEN1 \ Transmitter Enable
+$ca constant UCSR1C \ USART1 MSPIM Control and Statu
+ $4 constant UCSR1C_UDORD1 \ Data Order
+ ca $4 bitmask: UCSR1C.UDORD1 \ Data Order
+ $2 constant UCSR1C_UCPHA1 \ Clock Phase
+ ca $2 bitmask: UCSR1C.UCPHA1 \ Clock Phase
+ $1 constant UCSR1C_UCPOL1 \ Clock Polarity
+ ca $1 bitmask: UCSR1C.UCPOL1 \ Clock Polarity
diff --git a/amforth-6.5/avr8/devices/atmega128rfr2/blocks/WATCHDOG.frt b/amforth-6.5/avr8/devices/atmega128rfr2/blocks/WATCHDOG.frt
new file mode 100644
index 0000000..7cc4b2a
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega128rfr2/blocks/WATCHDOG.frt
@@ -0,0 +1,15 @@
+\ Generated automatically for atmega128rfr2
+\ #require bitnames.frt
+
+\ WATCHDOG
+$60 constant WDTCSR \ Watchdog Timer Control Registe
+ $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Fla
+ 60 $80 bitmask: WDTCSR.WDIF \ Watchdog Timeout Interrupt Fla
+ $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Ena
+ 60 $40 bitmask: WDTCSR.WDIE \ Watchdog Timeout Interrupt Ena
+ $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
+ 60 $27 bitmask: WDTCSR.WDP \ Watchdog Timer Prescaler Bits
+ $10 constant WDTCSR_WDCE \ Watchdog Change Enable
+ 60 $10 bitmask: WDTCSR.WDCE \ Watchdog Change Enable
+ $8 constant WDTCSR_WDE \ Watch Dog Enable
+ 60 $8 bitmask: WDTCSR.WDE \ Watch Dog Enable
diff --git a/amforth-6.5/avr8/devices/atmega128rfr2/device.asm b/amforth-6.5/avr8/devices/atmega128rfr2/device.asm
new file mode 100644
index 0000000..2b8ddbb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega128rfr2/device.asm
@@ -0,0 +1,166 @@
+; Generated Automatically
+
+.nolist
+ include "m128RFR2def.inc"
+.list
+FLASHSTART = 0
+FLASHSIZE = 131072
+RAMEND = 16896
+IRAMSTART = 512
+IRAMSIZE = 16384
+EEPROMSIZE = 4096
+; Interrupt Vectors
+.overlap
+.org 2
+ rcall isr ; External Interrupt Request 0
+.org 4
+ rcall isr ; External Interrupt Request 1
+.org 6
+ rcall isr ; External Interrupt Request 2
+.org 8
+ rcall isr ; External Interrupt Request 3
+.org 10
+ rcall isr ; External Interrupt Request 4
+.org 12
+ rcall isr ; External Interrupt Request 5
+.org 14
+ rcall isr ; External Interrupt Request 6
+.org 16
+ rcall isr ; External Interrupt Request 7
+.org 18
+ rcall isr ; Pin Change Interrupt Request 0
+.org 20
+ rcall isr ; Pin Change Interrupt Request 1
+.org 22
+ rcall isr ; Pin Change Interrupt Request 2
+.org 24
+ rcall isr ; Watchdog Time-out Interrupt
+.org 26
+ rcall isr ; Timer/Counter2 Compare Match A
+.org 28
+ rcall isr ; Timer/Counter2 Compare Match B
+.org 30
+ rcall isr ; Timer/Counter2 Overflow
+.org 32
+ rcall isr ; Timer/Counter1 Capture Event
+.org 34
+ rcall isr ; Timer/Counter1 Compare Match A
+.org 36
+ rcall isr ; Timer/Counter1 Compare Match B
+.org 38
+ rcall isr ; Timer/Counter1 Compare Match C
+.org 40
+ rcall isr ; Timer/Counter1 Overflow
+.org 42
+ rcall isr ; Timer/Counter0 Compare Match A
+.org 44
+ rcall isr ; Timer/Counter0 Compare Match B
+.org 46
+ rcall isr ; Timer/Counter0 Overflow
+.org 48
+ rcall isr ; SPI Serial Transfer Complete
+.org 50
+ rcall isr ; USART0, Rx Complete
+.org 52
+ rcall isr ; USART0 Data register Empty
+.org 54
+ rcall isr ; USART0, Tx Complete
+.org 56
+ rcall isr ; Analog Comparator
+.org 58
+ rcall isr ; ADC Conversion Complete
+.org 60
+ rcall isr ; EEPROM Ready
+.org 62
+ rcall isr ; Timer/Counter3 Capture Event
+.org 64
+ rcall isr ; Timer/Counter3 Compare Match A
+.org 66
+ rcall isr ; Timer/Counter3 Compare Match B
+.org 68
+ rcall isr ; Timer/Counter3 Compare Match C
+.org 70
+ rcall isr ; Timer/Counter3 Overflow
+.org 72
+ rcall isr ; USART1, Rx Complete
+.org 74
+ rcall isr ; USART1 Data register Empty
+.org 76
+ rcall isr ; USART1, Tx Complete
+.org 78
+ rcall isr ; 2-wire Serial Interface
+.org 80
+ rcall isr ; Store Program Memory Read
+.org 82
+ rcall isr ; Timer/Counter4 Capture Event
+.org 84
+ rcall isr ; Timer/Counter4 Compare Match A
+.org 86
+ rcall isr ; Timer/Counter4 Compare Match B
+.org 88
+ rcall isr ; Timer/Counter4 Compare Match C
+.org 90
+ rcall isr ; Timer/Counter4 Overflow
+.org 92
+ rcall isr ; Timer/Counter5 Capture Event
+.org 94
+ rcall isr ; Timer/Counter5 Compare Match A
+.org 96
+ rcall isr ; Timer/Counter5 Compare Match B
+.org 98
+ rcall isr ; Timer/Counter5 Compare Match C
+.org 100
+ rcall isr ; Timer/Counter5 Overflow
+.org 102
+ rcall isr ; USART2, Rx Complete
+.org 104
+ rcall isr ; USART2 Data register Empty
+.org 106
+ rcall isr ; USART2, Tx Complete
+.org 108
+ rcall isr ; USART3, Rx Complete
+.org 110
+ rcall isr ; USART3 Data register Empty
+.org 112
+ rcall isr ; USART3, Tx Complete
+.org 114
+ rcall isr ; TRX24 - PLL lock interrupt
+.org 116
+ rcall isr ; TRX24 - PLL unlock interrupt
+.org 118
+ rcall isr ; TRX24 - Receive start interrupt
+.org 120
+ rcall isr ; TRX24 - RX_END interrupt
+.org 122
+ rcall isr ; TRX24 - CCA/ED done interrupt
+.org 124
+ rcall isr ; TRX24 - XAH - AMI
+.org 126
+ rcall isr ; TRX24 - TX_END interrupt
+.org 128
+ rcall isr ; TRX24 AWAKE - tranceiver is reaching state TRX_OFF
+.org 130
+ rcall isr ; Symbol counter - compare match 1 interrupt
+.org 132
+ rcall isr ; Symbol counter - compare match 2 interrupt
+.org 134
+ rcall isr ; Symbol counter - compare match 3 interrupt
+.org 136
+ rcall isr ; Symbol counter - overflow interrupt
+.org 138
+ rcall isr ; Symbol counter - backoff interrupt
+.org 140
+ rcall isr ; AES engine ready interrupt
+.org 142
+ rcall isr ; Battery monitor indicates supply voltage below threshold
+.org 144
+ rcall isr ; TRX24 TX start interrupt
+.org 146
+ rcall isr ; Address match interrupt of address filter 0
+.org 148
+ rcall isr ; Address match interrupt of address filter 1
+.org 150
+ rcall isr ; Address match interrupt of address filter 2
+.org 152
+ rcall isr ; Address match interrupt of address filter 3
+.nooverlap
diff --git a/amforth-6.5/avr8/devices/atmega128rfr2/device.frt b/amforth-6.5/avr8/devices/atmega128rfr2/device.frt
new file mode 100644
index 0000000..a844898
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega128rfr2/device.frt
@@ -0,0 +1,1752 @@
+\ Generated Automatically
+
+\ Interrupt Vectors
+#2 constant INT0Addr \ External Interrupt Request 0
+#4 constant INT1Addr \ External Interrupt Request 1
+#6 constant INT2Addr \ External Interrupt Request 2
+#8 constant INT3Addr \ External Interrupt Request 3
+#10 constant INT4Addr \ External Interrupt Request 4
+#12 constant INT5Addr \ External Interrupt Request 5
+#14 constant INT6Addr \ External Interrupt Request 6
+#16 constant INT7Addr \ External Interrupt Request 7
+#18 constant PCINT0Addr \ Pin Change Interrupt Request 0
+#20 constant PCINT1Addr \ Pin Change Interrupt Request 1
+#22 constant PCINT2Addr \ Pin Change Interrupt Request 2
+#24 constant WDTAddr \ Watchdog Time-out Interrupt
+#26 constant TIMER2_COMPAAddr \ Timer/Counter2 Compare Match A
+#28 constant TIMER2_COMPBAddr \ Timer/Counter2 Compare Match B
+#30 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
+#32 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+#34 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
+#36 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
+#38 constant TIMER1_COMPCAddr \ Timer/Counter1 Compare Match C
+#40 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+#42 constant TIMER0_COMPAAddr \ Timer/Counter0 Compare Match A
+#44 constant TIMER0_COMPBAddr \ Timer/Counter0 Compare Match B
+#46 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
+#48 constant SPI_STCAddr \ SPI Serial Transfer Complete
+#50 constant USART0_RXAddr \ USART0, Rx Complete
+#52 constant USART0_UDREAddr \ USART0 Data register Empty
+#54 constant USART0_TXAddr \ USART0, Tx Complete
+#56 constant ANALOG_COMPAddr \ Analog Comparator
+#58 constant ADCAddr \ ADC Conversion Complete
+#60 constant EE_READYAddr \ EEPROM Ready
+#62 constant TIMER3_CAPTAddr \ Timer/Counter3 Capture Event
+#64 constant TIMER3_COMPAAddr \ Timer/Counter3 Compare Match A
+#66 constant TIMER3_COMPBAddr \ Timer/Counter3 Compare Match B
+#68 constant TIMER3_COMPCAddr \ Timer/Counter3 Compare Match C
+#70 constant TIMER3_OVFAddr \ Timer/Counter3 Overflow
+#72 constant USART1_RXAddr \ USART1, Rx Complete
+#74 constant USART1_UDREAddr \ USART1 Data register Empty
+#76 constant USART1_TXAddr \ USART1, Tx Complete
+#78 constant TWIAddr \ 2-wire Serial Interface
+#80 constant SPM_READYAddr \ Store Program Memory Read
+#82 constant TIMER4_CAPTAddr \ Timer/Counter4 Capture Event
+#84 constant TIMER4_COMPAAddr \ Timer/Counter4 Compare Match A
+#86 constant TIMER4_COMPBAddr \ Timer/Counter4 Compare Match B
+#88 constant TIMER4_COMPCAddr \ Timer/Counter4 Compare Match C
+#90 constant TIMER4_OVFAddr \ Timer/Counter4 Overflow
+#92 constant TIMER5_CAPTAddr \ Timer/Counter5 Capture Event
+#94 constant TIMER5_COMPAAddr \ Timer/Counter5 Compare Match A
+#96 constant TIMER5_COMPBAddr \ Timer/Counter5 Compare Match B
+#98 constant TIMER5_COMPCAddr \ Timer/Counter5 Compare Match C
+#100 constant TIMER5_OVFAddr \ Timer/Counter5 Overflow
+#102 constant USART2_RXAddr \ USART2, Rx Complete
+#104 constant USART2_UDREAddr \ USART2 Data register Empty
+#106 constant USART2_TXAddr \ USART2, Tx Complete
+#108 constant USART3_RXAddr \ USART3, Rx Complete
+#110 constant USART3_UDREAddr \ USART3 Data register Empty
+#112 constant USART3_TXAddr \ USART3, Tx Complete
+#114 constant TRX24_PLL_LOCKAddr \ TRX24 - PLL lock interrupt
+#116 constant TRX24_PLL_UNLOCKAddr \ TRX24 - PLL unlock interrupt
+#118 constant TRX24_RX_STARTAddr \ TRX24 - Receive start interrupt
+#120 constant TRX24_RX_ENDAddr \ TRX24 - RX_END interrupt
+#122 constant TRX24_CCA_ED_DONEAddr \ TRX24 - CCA/ED done interrupt
+#124 constant TRX24_XAH_AMIAddr \ TRX24 - XAH - AMI
+#126 constant TRX24_TX_ENDAddr \ TRX24 - TX_END interrupt
+#128 constant TRX24_AWAKEAddr \ TRX24 AWAKE - tranceiver is reaching state TRX_OFF
+#130 constant SCNT_CMP1Addr \ Symbol counter - compare match 1 interrupt
+#132 constant SCNT_CMP2Addr \ Symbol counter - compare match 2 interrupt
+#134 constant SCNT_CMP3Addr \ Symbol counter - compare match 3 interrupt
+#136 constant SCNT_OVFLAddr \ Symbol counter - overflow interrupt
+#138 constant SCNT_BACKOFFAddr \ Symbol counter - backoff interrupt
+#140 constant AES_READYAddr \ AES engine ready interrupt
+#142 constant BAT_LOWAddr \ Battery monitor indicates supply voltage below threshold
+#144 constant TRX24_TX_STARTAddr \ TRX24 TX start interrupt
+#146 constant TRX24_AMI0Addr \ Address match interrupt of address filter 0
+#148 constant TRX24_AMI1Addr \ Address match interrupt of address filter 1
+#150 constant TRX24_AMI2Addr \ Address match interrupt of address filter 2
+#152 constant TRX24_AMI3Addr \ Address match interrupt of address filter 3
+\ ANALOG_COMPARATOR
+$7b constant ADCSRB \ ADC Control and Status Registe
+ $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer
+ 7b $40 bitmask: ADCSRB.ACME \ Analog Comparator Multiplexer
+$50 constant ACSR \ Analog Comparator Control And
+ $80 constant ACSR_ACD \ Analog Comparator Disable
+ 50 $80 bitmask: ACSR.ACD \ Analog Comparator Disable
+ $40 constant ACSR_ACBG \ Analog Comparator Bandgap Sele
+ 50 $40 bitmask: ACSR.ACBG \ Analog Comparator Bandgap Sele
+ $20 constant ACSR_ACO \ Analog Compare Output
+ 50 $20 bitmask: ACSR.ACO \ Analog Compare Output
+ $10 constant ACSR_ACI \ Analog Comparator Interrupt Fl
+ 50 $10 bitmask: ACSR.ACI \ Analog Comparator Interrupt Fl
+ $8 constant ACSR_ACIE \ Analog Comparator Interrupt En
+ 50 $8 bitmask: ACSR.ACIE \ Analog Comparator Interrupt En
+ $4 constant ACSR_ACIC \ Analog Comparator Input Captur
+ 50 $4 bitmask: ACSR.ACIC \ Analog Comparator Input Captur
+ $3 constant ACSR_ACIS \ Analog Comparator Interrupt Mo
+ 50 $3 bitmask: ACSR.ACIS \ Analog Comparator Interrupt Mo
+$7f constant DIDR1 \ Digital Input Disable Register
+ $2 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
+ 7f $2 bitmask: DIDR1.AIN1D \ AIN1 Digital Input Disable
+ $1 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
+ 7f $1 bitmask: DIDR1.AIN0D \ AIN0 Digital Input Disable
+\ USART0
+$c6 constant UDR0 \ USART0 I/O Data Register
+$c0 constant UCSR0A \ USART0 Control and Status Regi
+ $80 constant UCSR0A_RXC0 \ USART Receive Complete
+ c0 $80 bitmask: UCSR0A.RXC0 \ USART Receive Complete
+ $40 constant UCSR0A_TXC0 \ USART Transmit Complete
+ c0 $40 bitmask: UCSR0A.TXC0 \ USART Transmit Complete
+ $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
+ c0 $20 bitmask: UCSR0A.UDRE0 \ USART Data Register Empty
+ $10 constant UCSR0A_FE0 \ Frame Error
+ c0 $10 bitmask: UCSR0A.FE0 \ Frame Error
+ $8 constant UCSR0A_DOR0 \ Data OverRun
+ c0 $8 bitmask: UCSR0A.DOR0 \ Data OverRun
+ $4 constant UCSR0A_UPE0 \ USART Parity Error
+ c0 $4 bitmask: UCSR0A.UPE0 \ USART Parity Error
+ $2 constant UCSR0A_U2X0 \ Double the USART Transmission
+ c0 $2 bitmask: UCSR0A.U2X0 \ Double the USART Transmission
+ $1 constant UCSR0A_MPCM0 \ Multi-processor Communication
+ c0 $1 bitmask: UCSR0A.MPCM0 \ Multi-processor Communication
+$c1 constant UCSR0B \ USART0 Control and Status Regi
+ $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
+ c1 $80 bitmask: UCSR0B.RXCIE0 \ RX Complete Interrupt Enable
+ $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
+ c1 $40 bitmask: UCSR0B.TXCIE0 \ TX Complete Interrupt Enable
+ $20 constant UCSR0B_UDRIE0 \ USART Data Register Empty Inte
+ c1 $20 bitmask: UCSR0B.UDRIE0 \ USART Data Register Empty Inte
+ $10 constant UCSR0B_RXEN0 \ Receiver Enable
+ c1 $10 bitmask: UCSR0B.RXEN0 \ Receiver Enable
+ $8 constant UCSR0B_TXEN0 \ Transmitter Enable
+ c1 $8 bitmask: UCSR0B.TXEN0 \ Transmitter Enable
+ $4 constant UCSR0B_UCSZ02 \ Character Size
+ c1 $4 bitmask: UCSR0B.UCSZ02 \ Character Size
+ $2 constant UCSR0B_RXB80 \ Receive Data Bit 8
+ c1 $2 bitmask: UCSR0B.RXB80 \ Receive Data Bit 8
+ $1 constant UCSR0B_TXB80 \ Transmit Data Bit 8
+ c1 $1 bitmask: UCSR0B.TXB80 \ Transmit Data Bit 8
+$c2 constant UCSR0C \ USART0 Control and Status Regi
+ $c0 constant UCSR0C_UMSEL0 \ USART Mode Select
+ c2 $c0 bitmask: UCSR0C.UMSEL0 \ USART Mode Select
+ $30 constant UCSR0C_UPM0 \ Parity Mode
+ c2 $30 bitmask: UCSR0C.UPM0 \ Parity Mode
+ $8 constant UCSR0C_USBS0 \ Stop Bit Select
+ c2 $8 bitmask: UCSR0C.USBS0 \ Stop Bit Select
+ $6 constant UCSR0C_UCSZ0 \ Character Size
+ c2 $6 bitmask: UCSR0C.UCSZ0 \ Character Size
+ $1 constant UCSR0C_UCPOL0 \ Clock Polarity
+ c2 $1 bitmask: UCSR0C.UCPOL0 \ Clock Polarity
+$c4 constant UBRR0 \ USART0 Baud Rate Register Byt
+\ USART1
+$ce constant UDR1 \ USART1 I/O Data Register
+$c8 constant UCSR1A \ USART1 Control and Status Regi
+ $80 constant UCSR1A_RXC1 \ USART Receive Complete
+ c8 $80 bitmask: UCSR1A.RXC1 \ USART Receive Complete
+ $40 constant UCSR1A_TXC1 \ USART Transmit Complete
+ c8 $40 bitmask: UCSR1A.TXC1 \ USART Transmit Complete
+ $20 constant UCSR1A_UDRE1 \ USART Data Register Empty
+ c8 $20 bitmask: UCSR1A.UDRE1 \ USART Data Register Empty
+ $10 constant UCSR1A_FE1 \ Frame Error
+ c8 $10 bitmask: UCSR1A.FE1 \ Frame Error
+ $8 constant UCSR1A_DOR1 \ Data OverRun
+ c8 $8 bitmask: UCSR1A.DOR1 \ Data OverRun
+ $4 constant UCSR1A_UPE1 \ USART Parity Error
+ c8 $4 bitmask: UCSR1A.UPE1 \ USART Parity Error
+ $2 constant UCSR1A_U2X1 \ Double the USART Transmission
+ c8 $2 bitmask: UCSR1A.U2X1 \ Double the USART Transmission
+ $1 constant UCSR1A_MPCM1 \ Multi-processor Communication
+ c8 $1 bitmask: UCSR1A.MPCM1 \ Multi-processor Communication
+$c9 constant UCSR1B \ USART1 Control and Status Regi
+ $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable
+ c9 $80 bitmask: UCSR1B.RXCIE1 \ RX Complete Interrupt Enable
+ $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable
+ c9 $40 bitmask: UCSR1B.TXCIE1 \ TX Complete Interrupt Enable
+ $20 constant UCSR1B_UDRIE1 \ USART Data Register Empty Inte
+ c9 $20 bitmask: UCSR1B.UDRIE1 \ USART Data Register Empty Inte
+ $10 constant UCSR1B_RXEN1 \ Receiver Enable
+ c9 $10 bitmask: UCSR1B.RXEN1 \ Receiver Enable
+ $8 constant UCSR1B_TXEN1 \ Transmitter Enable
+ c9 $8 bitmask: UCSR1B.TXEN1 \ Transmitter Enable
+ $4 constant UCSR1B_UCSZ12 \ Character Size
+ c9 $4 bitmask: UCSR1B.UCSZ12 \ Character Size
+ $2 constant UCSR1B_RXB81 \ Receive Data Bit 8
+ c9 $2 bitmask: UCSR1B.RXB81 \ Receive Data Bit 8
+ $1 constant UCSR1B_TXB81 \ Transmit Data Bit 8
+ c9 $1 bitmask: UCSR1B.TXB81 \ Transmit Data Bit 8
+$ca constant UCSR1C \ USART1 Control and Status Regi
+ $c0 constant UCSR1C_UMSEL1 \ USART Mode Select
+ ca $c0 bitmask: UCSR1C.UMSEL1 \ USART Mode Select
+ $30 constant UCSR1C_UPM1 \ Parity Mode
+ ca $30 bitmask: UCSR1C.UPM1 \ Parity Mode
+ $8 constant UCSR1C_USBS1 \ Stop Bit Select
+ ca $8 bitmask: UCSR1C.USBS1 \ Stop Bit Select
+ $6 constant UCSR1C_UCSZ1 \ Character Size
+ ca $6 bitmask: UCSR1C.UCSZ1 \ Character Size
+ $1 constant UCSR1C_UCPOL1 \ Clock Polarity
+ ca $1 bitmask: UCSR1C.UCPOL1 \ Clock Polarity
+$cc constant UBRR1 \ USART1 Baud Rate Register Byt
+\ TWI
+$bd constant TWAMR \ TWI (Slave) Address Mask Regis
+ $fe constant TWAMR_TWAM \ TWI Address Mask
+ bd $fe bitmask: TWAMR.TWAM \ TWI Address Mask
+ $1 constant TWAMR_Res \ Reserved Bit
+ bd $1 bitmask: TWAMR.Res \ Reserved Bit
+$b8 constant TWBR \ TWI Bit Rate Register
+$bc constant TWCR \ TWI Control Register
+ $80 constant TWCR_TWINT \ TWI Interrupt Flag
+ bc $80 bitmask: TWCR.TWINT \ TWI Interrupt Flag
+ $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
+ bc $40 bitmask: TWCR.TWEA \ TWI Enable Acknowledge Bit
+ $20 constant TWCR_TWSTA \ TWI START Condition Bit
+ bc $20 bitmask: TWCR.TWSTA \ TWI START Condition Bit
+ $10 constant TWCR_TWSTO \ TWI STOP Condition Bit
+ bc $10 bitmask: TWCR.TWSTO \ TWI STOP Condition Bit
+ $8 constant TWCR_TWWC \ TWI Write Collision Flag
+ bc $8 bitmask: TWCR.TWWC \ TWI Write Collision Flag
+ $4 constant TWCR_TWEN \ TWI Enable Bit
+ bc $4 bitmask: TWCR.TWEN \ TWI Enable Bit
+ $2 constant TWCR_Res \ Reserved Bit
+ bc $2 bitmask: TWCR.Res \ Reserved Bit
+ $1 constant TWCR_TWIE \ TWI Interrupt Enable
+ bc $1 bitmask: TWCR.TWIE \ TWI Interrupt Enable
+$b9 constant TWSR \ TWI Status Register
+ $f8 constant TWSR_TWS \ TWI Status
+ b9 $f8 bitmask: TWSR.TWS \ TWI Status
+ $4 constant TWSR_Res \ Reserved Bit
+ b9 $4 bitmask: TWSR.Res \ Reserved Bit
+ $3 constant TWSR_TWPS \ TWI Prescaler Bits
+ b9 $3 bitmask: TWSR.TWPS \ TWI Prescaler Bits
+$bb constant TWDR \ TWI Data Register
+$ba constant TWAR \ TWI (Slave) Address Register
+ $fe constant TWAR_TWA \ TWI (Slave) Address
+ ba $fe bitmask: TWAR.TWA \ TWI (Slave) Address
+ $1 constant TWAR_TWGCE \ TWI General Call Recognition E
+ ba $1 bitmask: TWAR.TWGCE \ TWI General Call Recognition E
+\ SPI
+$4c constant SPCR \ SPI Control Register
+ $80 constant SPCR_SPIE \ SPI Interrupt Enable
+ 4c $80 bitmask: SPCR.SPIE \ SPI Interrupt Enable
+ $40 constant SPCR_SPE \ SPI Enable
+ 4c $40 bitmask: SPCR.SPE \ SPI Enable
+ $20 constant SPCR_DORD \ Data Order
+ 4c $20 bitmask: SPCR.DORD \ Data Order
+ $10 constant SPCR_MSTR \ Master/Slave Select
+ 4c $10 bitmask: SPCR.MSTR \ Master/Slave Select
+ $8 constant SPCR_CPOL \ Clock polarity
+ 4c $8 bitmask: SPCR.CPOL \ Clock polarity
+ $4 constant SPCR_CPHA \ Clock Phase
+ 4c $4 bitmask: SPCR.CPHA \ Clock Phase
+ $3 constant SPCR_SPR \ SPI Clock Rate Select 1 and 0
+ 4c $3 bitmask: SPCR.SPR \ SPI Clock Rate Select 1 and 0
+$4d constant SPSR \ SPI Status Register
+ $80 constant SPSR_SPIF \ SPI Interrupt Flag
+ 4d $80 bitmask: SPSR.SPIF \ SPI Interrupt Flag
+ $40 constant SPSR_WCOL \ Write Collision Flag
+ 4d $40 bitmask: SPSR.WCOL \ Write Collision Flag
+ $3e constant SPSR_Res \ Reserved
+ 4d $3e bitmask: SPSR.Res \ Reserved
+ $1 constant SPSR_SPI2X \ Double SPI Speed Bit
+ 4d $1 bitmask: SPSR.SPI2X \ Double SPI Speed Bit
+$4e constant SPDR \ SPI Data Register
+\ PORTA
+$22 constant PORTA \ Port A Data Register
+$21 constant DDRA \ Port A Data Direction Register
+$20 constant PINA \ Port A Input Pins Address
+\ PORTB
+$25 constant PORTB \ Port B Data Register
+$24 constant DDRB \ Port B Data Direction Register
+$23 constant PINB \ Port B Input Pins Address
+\ PORTC
+$28 constant PORTC \ Port C Data Register
+$27 constant DDRC \ Port C Data Direction Register
+$26 constant PINC \ Port C Input Pins Address
+\ PORTD
+$2b constant PORTD \ Port D Data Register
+$2a constant DDRD \ Port D Data Direction Register
+$29 constant PIND \ Port D Input Pins Address
+\ PORTE
+$2e constant PORTE \ Port E Data Register
+$2d constant DDRE \ Port E Data Direction Register
+$2c constant PINE \ Port E Input Pins Address
+\ PORTF
+$31 constant PORTF \ Port F Data Register
+$30 constant DDRF \ Port F Data Direction Register
+$2f constant PINF \ Port F Input Pins Address
+\ PORTG
+$34 constant PORTG \ Port G Data Register
+$33 constant DDRG \ Port G Data Direction Register
+$32 constant PING \ Port G Input Pins Address
+\ TIMER_COUNTER_0
+$48 constant OCR0B \ Timer/Counter0 Output Compare
+$47 constant OCR0A \ Timer/Counter0 Output Compare
+$46 constant TCNT0 \ Timer/Counter0 Register
+$45 constant TCCR0B \ Timer/Counter0 Control Registe
+ $80 constant TCCR0B_FOC0A \ Force Output Compare A
+ 45 $80 bitmask: TCCR0B.FOC0A \ Force Output Compare A
+ $40 constant TCCR0B_FOC0B \ Force Output Compare B
+ 45 $40 bitmask: TCCR0B.FOC0B \ Force Output Compare B
+ $30 constant TCCR0B_Res \ Reserved Bit
+ 45 $30 bitmask: TCCR0B.Res \ Reserved Bit
+ $8 constant TCCR0B_WGM02 \
+ 45 $8 bitmask: TCCR0B.WGM02 \
+ $7 constant TCCR0B_CS0 \ Clock Select
+ 45 $7 bitmask: TCCR0B.CS0 \ Clock Select
+$44 constant TCCR0A \ Timer/Counter0 Control Registe
+ $c0 constant TCCR0A_COM0A \ Compare Match Output A Mode
+ 44 $c0 bitmask: TCCR0A.COM0A \ Compare Match Output A Mode
+ $30 constant TCCR0A_COM0B \ Compare Match Output B Mode
+ 44 $30 bitmask: TCCR0A.COM0B \ Compare Match Output B Mode
+ $c constant TCCR0A_Res \ Reserved Bit
+ 44 $c bitmask: TCCR0A.Res \ Reserved Bit
+ $3 constant TCCR0A_WGM0 \ Waveform Generation Mode
+ 44 $3 bitmask: TCCR0A.WGM0 \ Waveform Generation Mode
+$6e constant TIMSK0 \ Timer/Counter0 Interrupt Mask
+ $f8 constant TIMSK0_Res \ Reserved
+ 6e $f8 bitmask: TIMSK0.Res \ Reserved
+ $4 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare
+ 6e $4 bitmask: TIMSK0.OCIE0B \ Timer/Counter0 Output Compare
+ $2 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare
+ 6e $2 bitmask: TIMSK0.OCIE0A \ Timer/Counter0 Output Compare
+ $1 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interr
+ 6e $1 bitmask: TIMSK0.TOIE0 \ Timer/Counter0 Overflow Interr
+$35 constant TIFR0 \ Timer/Counter0 Interrupt Flag
+ $f8 constant TIFR0_Res \ Reserved
+ 35 $f8 bitmask: TIFR0.Res \ Reserved
+ $4 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare
+ 35 $4 bitmask: TIFR0.OCF0B \ Timer/Counter0 Output Compare
+ $2 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare
+ 35 $2 bitmask: TIFR0.OCF0A \ Timer/Counter0 Output Compare
+ $1 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
+ 35 $1 bitmask: TIFR0.TOV0 \ Timer/Counter0 Overflow Flag
+$43 constant GTCCR \ General Timer/Counter Control
+ $80 constant GTCCR_TSM \ Timer/Counter Synchronization
+ 43 $80 bitmask: GTCCR.TSM \ Timer/Counter Synchronization
+ $7c constant GTCCR_Res \ Reserved
+ 43 $7c bitmask: GTCCR.Res \ Reserved
+ $2 constant GTCCR_PSRASY \ Prescaler Reset Timer/Counter2
+ 43 $2 bitmask: GTCCR.PSRASY \ Prescaler Reset Timer/Counter2
+ $1 constant GTCCR_PSRSYNC \ Prescaler Reset for Synchronou
+ 43 $1 bitmask: GTCCR.PSRSYNC \ Prescaler Reset for Synchronou
+\ TIMER_COUNTER_2
+$70 constant TIMSK2 \ Timer/Counter Interrupt Mask r
+ $f8 constant TIMSK2_Res \ Reserved Bit
+ 70 $f8 bitmask: TIMSK2.Res \ Reserved Bit
+ $4 constant TIMSK2_OCIE2B \ Timer/Counter2 Output Compare
+ 70 $4 bitmask: TIMSK2.OCIE2B \ Timer/Counter2 Output Compare
+ $2 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare
+ 70 $2 bitmask: TIMSK2.OCIE2A \ Timer/Counter2 Output Compare
+ $1 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interr
+ 70 $1 bitmask: TIMSK2.TOIE2 \ Timer/Counter2 Overflow Interr
+$37 constant TIFR2 \ Timer/Counter Interrupt Flag R
+ $f8 constant TIFR2_Res \ Reserved Bit
+ 37 $f8 bitmask: TIFR2.Res \ Reserved Bit
+ $4 constant TIFR2_OCF2B \ Output Compare Flag 2 B
+ 37 $4 bitmask: TIFR2.OCF2B \ Output Compare Flag 2 B
+ $2 constant TIFR2_OCF2A \ Output Compare Flag 2 A
+ 37 $2 bitmask: TIFR2.OCF2A \ Output Compare Flag 2 A
+ $1 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
+ 37 $1 bitmask: TIFR2.TOV2 \ Timer/Counter2 Overflow Flag
+$b0 constant TCCR2A \ Timer/Counter2 Control Registe
+ $c0 constant TCCR2A_COM2A \ Compare Match Output A Mode
+ b0 $c0 bitmask: TCCR2A.COM2A \ Compare Match Output A Mode
+ $30 constant TCCR2A_COM2B \ Compare Match Output B Mode
+ b0 $30 bitmask: TCCR2A.COM2B \ Compare Match Output B Mode
+ $c constant TCCR2A_Res \ Reserved
+ b0 $c bitmask: TCCR2A.Res \ Reserved
+ $3 constant TCCR2A_WGM2 \ Waveform Generation Mode
+ b0 $3 bitmask: TCCR2A.WGM2 \ Waveform Generation Mode
+$b1 constant TCCR2B \ Timer/Counter2 Control Registe
+ $80 constant TCCR2B_FOC2A \ Force Output Compare A
+ b1 $80 bitmask: TCCR2B.FOC2A \ Force Output Compare A
+ $40 constant TCCR2B_FOC2B \ Force Output Compare B
+ b1 $40 bitmask: TCCR2B.FOC2B \ Force Output Compare B
+ $30 constant TCCR2B_Res \ Reserved
+ b1 $30 bitmask: TCCR2B.Res \ Reserved
+ $8 constant TCCR2B_WGM22 \ Waveform Generation Mode
+ b1 $8 bitmask: TCCR2B.WGM22 \ Waveform Generation Mode
+ $7 constant TCCR2B_CS2 \ Clock Select
+ b1 $7 bitmask: TCCR2B.CS2 \ Clock Select
+$b2 constant TCNT2 \ Timer/Counter2
+$b4 constant OCR2B \ Timer/Counter2 Output Compare
+$b3 constant OCR2A \ Timer/Counter2 Output Compare
+$b6 constant ASSR \ Asynchronous Status Register
+ $80 constant ASSR_EXCLKAMR \ Enable External Clock Input fo
+ b6 $80 bitmask: ASSR.EXCLKAMR \ Enable External Clock Input fo
+ $40 constant ASSR_EXCLK \ Enable External Clock Input
+ b6 $40 bitmask: ASSR.EXCLK \ Enable External Clock Input
+ $20 constant ASSR_AS2 \ Timer/Counter2 Asynchronous Mo
+ b6 $20 bitmask: ASSR.AS2 \ Timer/Counter2 Asynchronous Mo
+ $10 constant ASSR_TCN2UB \ Timer/Counter2 Update Busy
+ b6 $10 bitmask: ASSR.TCN2UB \ Timer/Counter2 Update Busy
+ $8 constant ASSR_OCR2AUB \ Timer/Counter2 Output Compare
+ b6 $8 bitmask: ASSR.OCR2AUB \ Timer/Counter2 Output Compare
+ $4 constant ASSR_OCR2BUB \ Timer/Counter2 Output Compare
+ b6 $4 bitmask: ASSR.OCR2BUB \ Timer/Counter2 Output Compare
+ $2 constant ASSR_TCR2AUB \ Timer/Counter2 Control Registe
+ b6 $2 bitmask: ASSR.TCR2AUB \ Timer/Counter2 Control Registe
+ $1 constant ASSR_TCR2BUB \ Timer/Counter2 Control Registe
+ b6 $1 bitmask: ASSR.TCR2BUB \ Timer/Counter2 Control Registe
+$43 constant GTCCR \ General Timer Counter Control
+ $80 constant GTCCR_TSM \ Timer/Counter Synchronization
+ 43 $80 bitmask: GTCCR.TSM \ Timer/Counter Synchronization
+ $2 constant GTCCR_PSRASY \ Prescaler Reset Timer/Counter2
+ 43 $2 bitmask: GTCCR.PSRASY \ Prescaler Reset Timer/Counter2
+\ WATCHDOG
+$60 constant WDTCSR \ Watchdog Timer Control Registe
+ $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Fla
+ 60 $80 bitmask: WDTCSR.WDIF \ Watchdog Timeout Interrupt Fla
+ $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Ena
+ 60 $40 bitmask: WDTCSR.WDIE \ Watchdog Timeout Interrupt Ena
+ $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
+ 60 $27 bitmask: WDTCSR.WDP \ Watchdog Timer Prescaler Bits
+ $10 constant WDTCSR_WDCE \ Watchdog Change Enable
+ 60 $10 bitmask: WDTCSR.WDCE \ Watchdog Change Enable
+ $8 constant WDTCSR_WDE \ Watch Dog Enable
+ 60 $8 bitmask: WDTCSR.WDE \ Watch Dog Enable
+\ TIMER_COUNTER_5
+$120 constant TCCR5A \ Timer/Counter5 Control Registe
+ $c0 constant TCCR5A_COM5A \ Compare Output Mode for Channe
+ 120 $c0 bitmask: TCCR5A.COM5A \ Compare Output Mode for Channe
+ $30 constant TCCR5A_COM5B \ Compare Output Mode for Channe
+ 120 $30 bitmask: TCCR5A.COM5B \ Compare Output Mode for Channe
+ $c constant TCCR5A_COM5C \ Compare Output Mode for Channe
+ 120 $c bitmask: TCCR5A.COM5C \ Compare Output Mode for Channe
+ $3 constant TCCR5A_WGM5 \ Waveform Generation Mode
+ 120 $3 bitmask: TCCR5A.WGM5 \ Waveform Generation Mode
+$121 constant TCCR5B \ Timer/Counter5 Control Registe
+ $80 constant TCCR5B_ICNC5 \ Input Capture 5 Noise Cancelle
+ 121 $80 bitmask: TCCR5B.ICNC5 \ Input Capture 5 Noise Cancelle
+ $40 constant TCCR5B_ICES5 \ Input Capture 5 Edge Select
+ 121 $40 bitmask: TCCR5B.ICES5 \ Input Capture 5 Edge Select
+ $20 constant TCCR5B_Res \ Reserved Bit
+ 121 $20 bitmask: TCCR5B.Res \ Reserved Bit
+ $18 constant TCCR5B_WGM5 \ Waveform Generation Mode
+ 121 $18 bitmask: TCCR5B.WGM5 \ Waveform Generation Mode
+ $7 constant TCCR5B_CS5 \ Clock Select
+ 121 $7 bitmask: TCCR5B.CS5 \ Clock Select
+$122 constant TCCR5C \ Timer/Counter5 Control Registe
+ $80 constant TCCR5C_FOC5A \ Force Output Compare for Chann
+ 122 $80 bitmask: TCCR5C.FOC5A \ Force Output Compare for Chann
+ $40 constant TCCR5C_FOC5B \ Force Output Compare for Chann
+ 122 $40 bitmask: TCCR5C.FOC5B \ Force Output Compare for Chann
+ $20 constant TCCR5C_FOC5C \ Force Output Compare for Chann
+ 122 $20 bitmask: TCCR5C.FOC5C \ Force Output Compare for Chann
+ $1f constant TCCR5C_Res \ Reserved
+ 122 $1f bitmask: TCCR5C.Res \ Reserved
+$124 constant TCNT5 \ Timer/Counter5 Bytes
+$128 constant OCR5A \ Timer/Counter5 Output Compare
+$12a constant OCR5B \ Timer/Counter5 Output Compare
+$12c constant OCR5C \ Timer/Counter5 Output Compare
+$126 constant ICR5 \ Timer/Counter5 Input Capture R
+$73 constant TIMSK5 \ Timer/Counter5 Interrupt Mask
+ $c0 constant TIMSK5_Res \ Reserved Bit
+ 73 $c0 bitmask: TIMSK5.Res \ Reserved Bit
+ $20 constant TIMSK5_ICIE5 \ Timer/Counter5 Input Capture I
+ 73 $20 bitmask: TIMSK5.ICIE5 \ Timer/Counter5 Input Capture I
+ $10 constant TIMSK5_Res \ Reserved Bit
+ 73 $10 bitmask: TIMSK5.Res \ Reserved Bit
+ $8 constant TIMSK5_OCIE5C \ Timer/Counter5 Output Compare
+ 73 $8 bitmask: TIMSK5.OCIE5C \ Timer/Counter5 Output Compare
+ $4 constant TIMSK5_OCIE5B \ Timer/Counter5 Output Compare
+ 73 $4 bitmask: TIMSK5.OCIE5B \ Timer/Counter5 Output Compare
+ $2 constant TIMSK5_OCIE5A \ Timer/Counter5 Output Compare
+ 73 $2 bitmask: TIMSK5.OCIE5A \ Timer/Counter5 Output Compare
+ $1 constant TIMSK5_TOIE5 \ Timer/Counter5 Overflow Interr
+ 73 $1 bitmask: TIMSK5.TOIE5 \ Timer/Counter5 Overflow Interr
+$3a constant TIFR5 \ Timer/Counter5 Interrupt Flag
+ $c0 constant TIFR5_Res \ Reserved Bit
+ 3a $c0 bitmask: TIFR5.Res \ Reserved Bit
+ $20 constant TIFR5_ICF5 \ Timer/Counter5 Input Capture F
+ 3a $20 bitmask: TIFR5.ICF5 \ Timer/Counter5 Input Capture F
+ $10 constant TIFR5_Res \ Reserved Bit
+ 3a $10 bitmask: TIFR5.Res \ Reserved Bit
+ $8 constant TIFR5_OCF5C \ Timer/Counter5 Output Compare
+ 3a $8 bitmask: TIFR5.OCF5C \ Timer/Counter5 Output Compare
+ $4 constant TIFR5_OCF5B \ Timer/Counter5 Output Compare
+ 3a $4 bitmask: TIFR5.OCF5B \ Timer/Counter5 Output Compare
+ $2 constant TIFR5_OCF5A \ Timer/Counter5 Output Compare
+ 3a $2 bitmask: TIFR5.OCF5A \ Timer/Counter5 Output Compare
+ $1 constant TIFR5_TOV5 \ Timer/Counter5 Overflow Flag
+ 3a $1 bitmask: TIFR5.TOV5 \ Timer/Counter5 Overflow Flag
+\ TIMER_COUNTER_4
+$a0 constant TCCR4A \ Timer/Counter4 Control Registe
+ $c0 constant TCCR4A_COM4A \ Compare Output Mode for Channe
+ a0 $c0 bitmask: TCCR4A.COM4A \ Compare Output Mode for Channe
+ $30 constant TCCR4A_COM4B \ Compare Output Mode for Channe
+ a0 $30 bitmask: TCCR4A.COM4B \ Compare Output Mode for Channe
+ $c constant TCCR4A_COM4C \ Compare Output Mode for Channe
+ a0 $c bitmask: TCCR4A.COM4C \ Compare Output Mode for Channe
+ $3 constant TCCR4A_WGM4 \ Waveform Generation Mode
+ a0 $3 bitmask: TCCR4A.WGM4 \ Waveform Generation Mode
+$a1 constant TCCR4B \ Timer/Counter4 Control Registe
+ $80 constant TCCR4B_ICNC4 \ Input Capture 4 Noise Cancelle
+ a1 $80 bitmask: TCCR4B.ICNC4 \ Input Capture 4 Noise Cancelle
+ $40 constant TCCR4B_ICES4 \ Input Capture 4 Edge Select
+ a1 $40 bitmask: TCCR4B.ICES4 \ Input Capture 4 Edge Select
+ $20 constant TCCR4B_Res \ Reserved Bit
+ a1 $20 bitmask: TCCR4B.Res \ Reserved Bit
+ $18 constant TCCR4B_WGM4 \ Waveform Generation Mode
+ a1 $18 bitmask: TCCR4B.WGM4 \ Waveform Generation Mode
+ $7 constant TCCR4B_CS4 \ Clock Select
+ a1 $7 bitmask: TCCR4B.CS4 \ Clock Select
+$a2 constant TCCR4C \ Timer/Counter4 Control Registe
+ $80 constant TCCR4C_FOC4A \ Force Output Compare for Chann
+ a2 $80 bitmask: TCCR4C.FOC4A \ Force Output Compare for Chann
+ $40 constant TCCR4C_FOC4B \ Force Output Compare for Chann
+ a2 $40 bitmask: TCCR4C.FOC4B \ Force Output Compare for Chann
+ $20 constant TCCR4C_FOC4C \ Force Output Compare for Chann
+ a2 $20 bitmask: TCCR4C.FOC4C \ Force Output Compare for Chann
+ $1f constant TCCR4C_Res \ Reserved
+ a2 $1f bitmask: TCCR4C.Res \ Reserved
+$a4 constant TCNT4 \ Timer/Counter4 Bytes
+$a8 constant OCR4A \ Timer/Counter4 Output Compare
+$aa constant OCR4B \ Timer/Counter4 Output Compare
+$ac constant OCR4C \ Timer/Counter4 Output Compare
+$a6 constant ICR4 \ Timer/Counter4 Input Capture R
+$72 constant TIMSK4 \ Timer/Counter4 Interrupt Mask
+ $c0 constant TIMSK4_Res \ Reserved Bit
+ 72 $c0 bitmask: TIMSK4.Res \ Reserved Bit
+ $20 constant TIMSK4_ICIE4 \ Timer/Counter4 Input Capture I
+ 72 $20 bitmask: TIMSK4.ICIE4 \ Timer/Counter4 Input Capture I
+ $10 constant TIMSK4_Res \ Reserved Bit
+ 72 $10 bitmask: TIMSK4.Res \ Reserved Bit
+ $8 constant TIMSK4_OCIE4C \ Timer/Counter4 Output Compare
+ 72 $8 bitmask: TIMSK4.OCIE4C \ Timer/Counter4 Output Compare
+ $4 constant TIMSK4_OCIE4B \ Timer/Counter4 Output Compare
+ 72 $4 bitmask: TIMSK4.OCIE4B \ Timer/Counter4 Output Compare
+ $2 constant TIMSK4_OCIE4A \ Timer/Counter4 Output Compare
+ 72 $2 bitmask: TIMSK4.OCIE4A \ Timer/Counter4 Output Compare
+ $1 constant TIMSK4_TOIE4 \ Timer/Counter4 Overflow Interr
+ 72 $1 bitmask: TIMSK4.TOIE4 \ Timer/Counter4 Overflow Interr
+$39 constant TIFR4 \ Timer/Counter4 Interrupt Flag
+ $c0 constant TIFR4_Res \ Reserved Bit
+ 39 $c0 bitmask: TIFR4.Res \ Reserved Bit
+ $20 constant TIFR4_ICF4 \ Timer/Counter4 Input Capture F
+ 39 $20 bitmask: TIFR4.ICF4 \ Timer/Counter4 Input Capture F
+ $10 constant TIFR4_Res \ Reserved Bit
+ 39 $10 bitmask: TIFR4.Res \ Reserved Bit
+ $8 constant TIFR4_OCF4C \ Timer/Counter4 Output Compare
+ 39 $8 bitmask: TIFR4.OCF4C \ Timer/Counter4 Output Compare
+ $4 constant TIFR4_OCF4B \ Timer/Counter4 Output Compare
+ 39 $4 bitmask: TIFR4.OCF4B \ Timer/Counter4 Output Compare
+ $2 constant TIFR4_OCF4A \ Timer/Counter4 Output Compare
+ 39 $2 bitmask: TIFR4.OCF4A \ Timer/Counter4 Output Compare
+ $1 constant TIFR4_TOV4 \ Timer/Counter4 Overflow Flag
+ 39 $1 bitmask: TIFR4.TOV4 \ Timer/Counter4 Overflow Flag
+\ TIMER_COUNTER_3
+$90 constant TCCR3A \ Timer/Counter3 Control Registe
+ $c0 constant TCCR3A_COM3A \ Compare Output Mode for Channe
+ 90 $c0 bitmask: TCCR3A.COM3A \ Compare Output Mode for Channe
+ $30 constant TCCR3A_COM3B \ Compare Output Mode for Channe
+ 90 $30 bitmask: TCCR3A.COM3B \ Compare Output Mode for Channe
+ $c constant TCCR3A_COM3C \ Compare Output Mode for Channe
+ 90 $c bitmask: TCCR3A.COM3C \ Compare Output Mode for Channe
+ $3 constant TCCR3A_WGM3 \ Waveform Generation Mode
+ 90 $3 bitmask: TCCR3A.WGM3 \ Waveform Generation Mode
+$91 constant TCCR3B \ Timer/Counter3 Control Registe
+ $80 constant TCCR3B_ICNC3 \ Input Capture 3 Noise Cancelle
+ 91 $80 bitmask: TCCR3B.ICNC3 \ Input Capture 3 Noise Cancelle
+ $40 constant TCCR3B_ICES3 \ Input Capture 3 Edge Select
+ 91 $40 bitmask: TCCR3B.ICES3 \ Input Capture 3 Edge Select
+ $20 constant TCCR3B_Res \ Reserved Bit
+ 91 $20 bitmask: TCCR3B.Res \ Reserved Bit
+ $18 constant TCCR3B_WGM3 \ Waveform Generation Mode
+ 91 $18 bitmask: TCCR3B.WGM3 \ Waveform Generation Mode
+ $7 constant TCCR3B_CS3 \ Clock Select
+ 91 $7 bitmask: TCCR3B.CS3 \ Clock Select
+$92 constant TCCR3C \ Timer/Counter3 Control Registe
+ $80 constant TCCR3C_FOC3A \ Force Output Compare for Chann
+ 92 $80 bitmask: TCCR3C.FOC3A \ Force Output Compare for Chann
+ $40 constant TCCR3C_FOC3B \ Force Output Compare for Chann
+ 92 $40 bitmask: TCCR3C.FOC3B \ Force Output Compare for Chann
+ $20 constant TCCR3C_FOC3C \ Force Output Compare for Chann
+ 92 $20 bitmask: TCCR3C.FOC3C \ Force Output Compare for Chann
+ $1f constant TCCR3C_Res \ Reserved
+ 92 $1f bitmask: TCCR3C.Res \ Reserved
+$94 constant TCNT3 \ Timer/Counter3 Bytes
+$98 constant OCR3A \ Timer/Counter3 Output Compare
+$9a constant OCR3B \ Timer/Counter3 Output Compare
+$9c constant OCR3C \ Timer/Counter3 Output Compare
+$96 constant ICR3 \ Timer/Counter3 Input Capture R
+$71 constant TIMSK3 \ Timer/Counter3 Interrupt Mask
+ $c0 constant TIMSK3_Res \ Reserved Bit
+ 71 $c0 bitmask: TIMSK3.Res \ Reserved Bit
+ $20 constant TIMSK3_ICIE3 \ Timer/Counter3 Input Capture I
+ 71 $20 bitmask: TIMSK3.ICIE3 \ Timer/Counter3 Input Capture I
+ $10 constant TIMSK3_Res \ Reserved Bit
+ 71 $10 bitmask: TIMSK3.Res \ Reserved Bit
+ $8 constant TIMSK3_OCIE3C \ Timer/Counter3 Output Compare
+ 71 $8 bitmask: TIMSK3.OCIE3C \ Timer/Counter3 Output Compare
+ $4 constant TIMSK3_OCIE3B \ Timer/Counter3 Output Compare
+ 71 $4 bitmask: TIMSK3.OCIE3B \ Timer/Counter3 Output Compare
+ $2 constant TIMSK3_OCIE3A \ Timer/Counter3 Output Compare
+ 71 $2 bitmask: TIMSK3.OCIE3A \ Timer/Counter3 Output Compare
+ $1 constant TIMSK3_TOIE3 \ Timer/Counter3 Overflow Interr
+ 71 $1 bitmask: TIMSK3.TOIE3 \ Timer/Counter3 Overflow Interr
+$38 constant TIFR3 \ Timer/Counter3 Interrupt Flag
+ $c0 constant TIFR3_Res \ Reserved Bit
+ 38 $c0 bitmask: TIFR3.Res \ Reserved Bit
+ $20 constant TIFR3_ICF3 \ Timer/Counter3 Input Capture F
+ 38 $20 bitmask: TIFR3.ICF3 \ Timer/Counter3 Input Capture F
+ $10 constant TIFR3_Res \ Reserved Bit
+ 38 $10 bitmask: TIFR3.Res \ Reserved Bit
+ $8 constant TIFR3_OCF3C \ Timer/Counter3 Output Compare
+ 38 $8 bitmask: TIFR3.OCF3C \ Timer/Counter3 Output Compare
+ $4 constant TIFR3_OCF3B \ Timer/Counter3 Output Compare
+ 38 $4 bitmask: TIFR3.OCF3B \ Timer/Counter3 Output Compare
+ $2 constant TIFR3_OCF3A \ Timer/Counter3 Output Compare
+ 38 $2 bitmask: TIFR3.OCF3A \ Timer/Counter3 Output Compare
+ $1 constant TIFR3_TOV3 \ Timer/Counter3 Overflow Flag
+ 38 $1 bitmask: TIFR3.TOV3 \ Timer/Counter3 Overflow Flag
+\ TIMER_COUNTER_1
+$80 constant TCCR1A \ Timer/Counter1 Control Registe
+ $c0 constant TCCR1A_COM1A \ Compare Output Mode for Channe
+ 80 $c0 bitmask: TCCR1A.COM1A \ Compare Output Mode for Channe
+ $30 constant TCCR1A_COM1B \ Compare Output Mode for Channe
+ 80 $30 bitmask: TCCR1A.COM1B \ Compare Output Mode for Channe
+ $c constant TCCR1A_COM1C \ Compare Output Mode for Channe
+ 80 $c bitmask: TCCR1A.COM1C \ Compare Output Mode for Channe
+ $3 constant TCCR1A_WGM1 \ Waveform Generation Mode
+ 80 $3 bitmask: TCCR1A.WGM1 \ Waveform Generation Mode
+$81 constant TCCR1B \ Timer/Counter1 Control Registe
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Cancelle
+ 81 $80 bitmask: TCCR1B.ICNC1 \ Input Capture 1 Noise Cancelle
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ 81 $40 bitmask: TCCR1B.ICES1 \ Input Capture 1 Edge Select
+ $20 constant TCCR1B_Res \ Reserved Bit
+ 81 $20 bitmask: TCCR1B.Res \ Reserved Bit
+ $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
+ 81 $18 bitmask: TCCR1B.WGM1 \ Waveform Generation Mode
+ $7 constant TCCR1B_CS1 \ Clock Select
+ 81 $7 bitmask: TCCR1B.CS1 \ Clock Select
+$82 constant TCCR1C \ Timer/Counter1 Control Registe
+ $80 constant TCCR1C_FOC1A \ Force Output Compare for Chann
+ 82 $80 bitmask: TCCR1C.FOC1A \ Force Output Compare for Chann
+ $40 constant TCCR1C_FOC1B \ Force Output Compare for Chann
+ 82 $40 bitmask: TCCR1C.FOC1B \ Force Output Compare for Chann
+ $20 constant TCCR1C_FOC1C \ Force Output Compare for Chann
+ 82 $20 bitmask: TCCR1C.FOC1C \ Force Output Compare for Chann
+ $1f constant TCCR1C_Res \ Reserved
+ 82 $1f bitmask: TCCR1C.Res \ Reserved
+$84 constant TCNT1 \ Timer/Counter1 Bytes
+$88 constant OCR1A \ Timer/Counter1 Output Compare
+$8a constant OCR1B \ Timer/Counter1 Output Compare
+$8c constant OCR1C \ Timer/Counter1 Output Compare
+$86 constant ICR1 \ Timer/Counter1 Input Capture R
+$6f constant TIMSK1 \ Timer/Counter1 Interrupt Mask
+ $c0 constant TIMSK1_Res \ Reserved Bit
+ 6f $c0 bitmask: TIMSK1.Res \ Reserved Bit
+ $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture I
+ 6f $20 bitmask: TIMSK1.ICIE1 \ Timer/Counter1 Input Capture I
+ $10 constant TIMSK1_Res \ Reserved Bit
+ 6f $10 bitmask: TIMSK1.Res \ Reserved Bit
+ $8 constant TIMSK1_OCIE1C \ Timer/Counter1 Output Compare
+ 6f $8 bitmask: TIMSK1.OCIE1C \ Timer/Counter1 Output Compare
+ $4 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare
+ 6f $4 bitmask: TIMSK1.OCIE1B \ Timer/Counter1 Output Compare
+ $2 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare
+ 6f $2 bitmask: TIMSK1.OCIE1A \ Timer/Counter1 Output Compare
+ $1 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interr
+ 6f $1 bitmask: TIMSK1.TOIE1 \ Timer/Counter1 Overflow Interr
+$36 constant TIFR1 \ Timer/Counter1 Interrupt Flag
+ $c0 constant TIFR1_Res \ Reserved Bit
+ 36 $c0 bitmask: TIFR1.Res \ Reserved Bit
+ $20 constant TIFR1_ICF1 \ Timer/Counter1 Input Capture F
+ 36 $20 bitmask: TIFR1.ICF1 \ Timer/Counter1 Input Capture F
+ $10 constant TIFR1_Res \ Reserved Bit
+ 36 $10 bitmask: TIFR1.Res \ Reserved Bit
+ $8 constant TIFR1_OCF1C \ Timer/Counter1 Output Compare
+ 36 $8 bitmask: TIFR1.OCF1C \ Timer/Counter1 Output Compare
+ $4 constant TIFR1_OCF1B \ Timer/Counter1 Output Compare
+ 36 $4 bitmask: TIFR1.OCF1B \ Timer/Counter1 Output Compare
+ $2 constant TIFR1_OCF1A \ Timer/Counter1 Output Compare
+ 36 $2 bitmask: TIFR1.OCF1A \ Timer/Counter1 Output Compare
+ $1 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
+ 36 $1 bitmask: TIFR1.TOV1 \ Timer/Counter1 Overflow Flag
+\ TRX24
+$138 constant PARCR \ Power Amplifier Ramp up/down C
+ $e0 constant PARCR_PALTD \ ext. PA Ramp Down Lead Time
+ 138 $e0 bitmask: PARCR.PALTD \ ext. PA Ramp Down Lead Time
+ $1c constant PARCR_PALTU \ ext. PA Ramp Up Lead Time
+ 138 $1c bitmask: PARCR.PALTU \ ext. PA Ramp Up Lead Time
+ $2 constant PARCR_PARDFI \ Power Amplifier Ramp Down Freq
+ 138 $2 bitmask: PARCR.PARDFI \ Power Amplifier Ramp Down Freq
+ $1 constant PARCR_PARUFI \ Power Amplifier Ramp Up Freque
+ 138 $1 bitmask: PARCR.PARUFI \ Power Amplifier Ramp Up Freque
+$10e constant MAFSA0L \ Transceiver MAC Short Address
+ $ff constant MAFSA0L_MAFSA0L \ MAC Short Address low Byte for
+ 10e $ff bitmask: MAFSA0L.MAFSA0L \ MAC Short Address low Byte for
+$10f constant MAFSA0H \ Transceiver MAC Short Address
+ $ff constant MAFSA0H_MAFSA0H \ MAC Short Address high Byte fo
+ 10f $ff bitmask: MAFSA0H.MAFSA0H \ MAC Short Address high Byte fo
+$110 constant MAFPA0L \ Transceiver Personal Area Netw
+ $ff constant MAFPA0L_MAFPA0L \ MAC Personal Area Network ID l
+ 110 $ff bitmask: MAFPA0L.MAFPA0L \ MAC Personal Area Network ID l
+$111 constant MAFPA0H \ Transceiver Personal Area Netw
+ $ff constant MAFPA0H_MAFPA0H \ MAC Personal Area Network ID h
+ 111 $ff bitmask: MAFPA0H.MAFPA0H \ MAC Personal Area Network ID h
+$112 constant MAFSA1L \ Transceiver MAC Short Address
+ $ff constant MAFSA1L_MAFSA1L \ MAC Short Address low Byte for
+ 112 $ff bitmask: MAFSA1L.MAFSA1L \ MAC Short Address low Byte for
+$113 constant MAFSA1H \ Transceiver MAC Short Address
+ $ff constant MAFSA1H_MAFSA1H \ MAC Short Address high Byte fo
+ 113 $ff bitmask: MAFSA1H.MAFSA1H \ MAC Short Address high Byte fo
+$114 constant MAFPA1L \ Transceiver Personal Area Netw
+ $ff constant MAFPA1L_MAFPA1L \ MAC Personal Area Network ID l
+ 114 $ff bitmask: MAFPA1L.MAFPA1L \ MAC Personal Area Network ID l
+$115 constant MAFPA1H \ Transceiver Personal Area Netw
+ $ff constant MAFPA1H_MAFPA1H \ MAC Personal Area Network ID h
+ 115 $ff bitmask: MAFPA1H.MAFPA1H \ MAC Personal Area Network ID h
+$116 constant MAFSA2L \ Transceiver MAC Short Address
+ $ff constant MAFSA2L_MAFSA2L \ MAC Short Address low Byte for
+ 116 $ff bitmask: MAFSA2L.MAFSA2L \ MAC Short Address low Byte for
+$117 constant MAFSA2H \ Transceiver MAC Short Address
+ $ff constant MAFSA2H_MAFSA2H \ MAC Short Address high Byte fo
+ 117 $ff bitmask: MAFSA2H.MAFSA2H \ MAC Short Address high Byte fo
+$118 constant MAFPA2L \ Transceiver Personal Area Netw
+ $ff constant MAFPA2L_MAFPA2L \ MAC Personal Area Network ID l
+ 118 $ff bitmask: MAFPA2L.MAFPA2L \ MAC Personal Area Network ID l
+$119 constant MAFPA2H \ Transceiver Personal Area Netw
+ $ff constant MAFPA2H_MAFPA2H \ MAC Personal Area Network ID h
+ 119 $ff bitmask: MAFPA2H.MAFPA2H \ MAC Personal Area Network ID h
+$11a constant MAFSA3L \ Transceiver MAC Short Address
+ $ff constant MAFSA3L_MAFSA3L \ MAC Short Address low Byte for
+ 11a $ff bitmask: MAFSA3L.MAFSA3L \ MAC Short Address low Byte for
+$11b constant MAFSA3H \ Transceiver MAC Short Address
+ $ff constant MAFSA3H_MAFSA3H \ MAC Short Address high Byte fo
+ 11b $ff bitmask: MAFSA3H.MAFSA3H \ MAC Short Address high Byte fo
+$11c constant MAFPA3L \ Transceiver Personal Area Netw
+ $ff constant MAFPA3L_MAFPA3L \ MAC Personal Area Network ID l
+ 11c $ff bitmask: MAFPA3L.MAFPA3L \ MAC Personal Area Network ID l
+$11d constant MAFPA3H \ Transceiver Personal Area Netw
+ $ff constant MAFPA3H_MAFPA3H \ MAC Personal Area Network ID h
+ 11d $ff bitmask: MAFPA3H.MAFPA3H \ MAC Personal Area Network ID h
+$10c constant MAFCR0 \ Multiple Address Filter Config
+ $f0 constant MAFCR0_Res \ Reserved Bit
+ 10c $f0 bitmask: MAFCR0.Res \ Reserved Bit
+ $8 constant MAFCR0_MAF3EN \ Multiple Address Filter 3 Enab
+ 10c $8 bitmask: MAFCR0.MAF3EN \ Multiple Address Filter 3 Enab
+ $4 constant MAFCR0_MAF2EN \ Multiple Address Filter 2 Enab
+ 10c $4 bitmask: MAFCR0.MAF2EN \ Multiple Address Filter 2 Enab
+ $2 constant MAFCR0_MAF1EN \ Multiple Address Filter 1 Enab
+ 10c $2 bitmask: MAFCR0.MAF1EN \ Multiple Address Filter 1 Enab
+ $1 constant MAFCR0_MAF0EN \ Multiple Address Filter 0 Enab
+ 10c $1 bitmask: MAFCR0.MAF0EN \ Multiple Address Filter 0 Enab
+$10d constant MAFCR1 \ Multiple Address Filter Config
+ $80 constant MAFCR1_AACK_3_SET_PD \ Set Data Pending bit for addre
+ 10d $80 bitmask: MAFCR1.AACK_3_SET_PD \ Set Data Pending bit for addre
+ $40 constant MAFCR1_AACK_3_I_AM_COORD \ Enable PAN Coordinator mode fo
+ 10d $40 bitmask: MAFCR1.AACK_3_I_AM_COORD \ Enable PAN Coordinator mode fo
+ $20 constant MAFCR1_AACK_2_SET_PD \ Set Data Pending bit for addre
+ 10d $20 bitmask: MAFCR1.AACK_2_SET_PD \ Set Data Pending bit for addre
+ $10 constant MAFCR1_AACK_2_I_AM_COORD \ Enable PAN Coordinator mode fo
+ 10d $10 bitmask: MAFCR1.AACK_2_I_AM_COORD \ Enable PAN Coordinator mode fo
+ $8 constant MAFCR1_AACK_1_SET_PD \ Set Data Pending bit for addre
+ 10d $8 bitmask: MAFCR1.AACK_1_SET_PD \ Set Data Pending bit for addre
+ $4 constant MAFCR1_AACK_1_I_AM_COORD \ Enable PAN Coordinator mode fo
+ 10d $4 bitmask: MAFCR1.AACK_1_I_AM_COORD \ Enable PAN Coordinator mode fo
+ $2 constant MAFCR1_AACK_0_SET_PD \ Set Data Pending bit for addre
+ 10d $2 bitmask: MAFCR1.AACK_0_SET_PD \ Set Data Pending bit for addre
+ $1 constant MAFCR1_AACK_0_I_AM_COORD \ Enable PAN Coordinator mode fo
+ 10d $1 bitmask: MAFCR1.AACK_0_I_AM_COORD \ Enable PAN Coordinator mode fo
+$13c constant AES_CTRL \ AES Control Register
+ $80 constant AES_CTRL_AES_REQUEST \ Request AES Operation.
+ 13c $80 bitmask: AES_CTRL.AES_REQUEST \ Request AES Operation.
+ $40 constant AES_CTRL_Res \ Reserved Bit
+ 13c $40 bitmask: AES_CTRL.Res \ Reserved Bit
+ $20 constant AES_CTRL_AES_MODE \ Set AES Operation Mode
+ 13c $20 bitmask: AES_CTRL.AES_MODE \ Set AES Operation Mode
+ $10 constant AES_CTRL_Res \ Reserved Bit
+ 13c $10 bitmask: AES_CTRL.Res \ Reserved Bit
+ $8 constant AES_CTRL_AES_DIR \ Set AES Operation Direction
+ 13c $8 bitmask: AES_CTRL.AES_DIR \ Set AES Operation Direction
+ $4 constant AES_CTRL_AES_IM \ AES Interrupt Enable
+ 13c $4 bitmask: AES_CTRL.AES_IM \ AES Interrupt Enable
+ $3 constant AES_CTRL_Res \ Reserved Bit
+ 13c $3 bitmask: AES_CTRL.Res \ Reserved Bit
+$13d constant AES_STATUS \ AES Status Register
+ $80 constant AES_STATUS_AES_ER \ AES Operation Finished with Er
+ 13d $80 bitmask: AES_STATUS.AES_ER \ AES Operation Finished with Er
+ $7e constant AES_STATUS_Res \ Reserved
+ 13d $7e bitmask: AES_STATUS.Res \ Reserved
+ $1 constant AES_STATUS_AES_DONE \ AES Operation Finished with Su
+ 13d $1 bitmask: AES_STATUS.AES_DONE \ AES Operation Finished with Su
+$13e constant AES_STATE \ AES Plain and Cipher Text Buff
+ $ff constant AES_STATE_AES_STATE \ AES Plain and Cipher Text Buff
+ 13e $ff bitmask: AES_STATE.AES_STATE \ AES Plain and Cipher Text Buff
+$13f constant AES_KEY \ AES Encryption and Decryption
+ $ff constant AES_KEY_AES_KEY \ AES Encryption/Decryption Key
+ 13f $ff bitmask: AES_KEY.AES_KEY \ AES Encryption/Decryption Key
+$141 constant TRX_STATUS \ Transceiver Status Register
+ $80 constant TRX_STATUS_CCA_DONE \ CCA Algorithm Status
+ 141 $80 bitmask: TRX_STATUS.CCA_DONE \ CCA Algorithm Status
+ $40 constant TRX_STATUS_CCA_STATUS \ CCA Status Result
+ 141 $40 bitmask: TRX_STATUS.CCA_STATUS \ CCA Status Result
+ $20 constant TRX_STATUS_TST_STATUS \ Test mode status
+ 141 $20 bitmask: TRX_STATUS.TST_STATUS \ Test mode status
+ $1f constant TRX_STATUS_TRX_STATUS \ Transceiver Main Status
+ 141 $1f bitmask: TRX_STATUS.TRX_STATUS \ Transceiver Main Status
+$142 constant TRX_STATE \ Transceiver State Control Regi
+ $e0 constant TRX_STATE_TRAC_STATUS \ Transaction Status
+ 142 $e0 bitmask: TRX_STATE.TRAC_STATUS \ Transaction Status
+ $1f constant TRX_STATE_TRX_CMD \ State Control Command
+ 142 $1f bitmask: TRX_STATE.TRX_CMD \ State Control Command
+$143 constant TRX_CTRL_0 \ Reserved
+ $80 constant TRX_CTRL_0_Res7 \ Reserved
+ 143 $80 bitmask: TRX_CTRL_0.Res7 \ Reserved
+ $40 constant TRX_CTRL_0_PMU_EN \ Enable Phase Measurement Unit
+ 143 $40 bitmask: TRX_CTRL_0.PMU_EN \ Enable Phase Measurement Unit
+ $20 constant TRX_CTRL_0_PMU_START \ Start of Phase Measurement Uni
+ 143 $20 bitmask: TRX_CTRL_0.PMU_START \ Start of Phase Measurement Uni
+ $10 constant TRX_CTRL_0_PMU_IF_INV \ PMU IF Inverse
+ 143 $10 bitmask: TRX_CTRL_0.PMU_IF_INV \ PMU IF Inverse
+ $f constant TRX_CTRL_0_Res \ Reserved
+ 143 $f bitmask: TRX_CTRL_0.Res \ Reserved
+$144 constant TRX_CTRL_1 \ Transceiver Control Register 1
+ $80 constant TRX_CTRL_1_PA_EXT_EN \ External PA support enable
+ 144 $80 bitmask: TRX_CTRL_1.PA_EXT_EN \ External PA support enable
+ $40 constant TRX_CTRL_1_IRQ_2_EXT_EN \ Connect Frame Start IRQ to TC1
+ 144 $40 bitmask: TRX_CTRL_1.IRQ_2_EXT_EN \ Connect Frame Start IRQ to TC1
+ $20 constant TRX_CTRL_1_TX_AUTO_CRC_ON \ Enable Automatic CRC Calculati
+ 144 $20 bitmask: TRX_CTRL_1.TX_AUTO_CRC_ON \ Enable Automatic CRC Calculati
+ $10 constant TRX_CTRL_1_PLL_TX_FLT \ Enable PLL TX filter
+ 144 $10 bitmask: TRX_CTRL_1.PLL_TX_FLT \ Enable PLL TX filter
+ $f constant TRX_CTRL_1_Res \ Reserved
+ 144 $f bitmask: TRX_CTRL_1.Res \ Reserved
+$145 constant PHY_TX_PWR \ Transceiver Transmit Power Con
+ $f0 constant PHY_TX_PWR_Res \ Reserved
+ 145 $f0 bitmask: PHY_TX_PWR.Res \ Reserved
+ $f constant PHY_TX_PWR_TX_PWR \ Transmit Power Setting
+ 145 $f bitmask: PHY_TX_PWR.TX_PWR \ Transmit Power Setting
+$146 constant PHY_RSSI \ Receiver Signal Strength Indic
+ $80 constant PHY_RSSI_RX_CRC_VALID \ Received Frame CRC Status
+ 146 $80 bitmask: PHY_RSSI.RX_CRC_VALID \ Received Frame CRC Status
+ $60 constant PHY_RSSI_RND_VALUE \ Random Value
+ 146 $60 bitmask: PHY_RSSI.RND_VALUE \ Random Value
+ $1f constant PHY_RSSI_RSSI \ Receiver Signal Strength Indic
+ 146 $1f bitmask: PHY_RSSI.RSSI \ Receiver Signal Strength Indic
+$147 constant PHY_ED_LEVEL \ Transceiver Energy Detection L
+ $ff constant PHY_ED_LEVEL_ED_LEVEL \ Energy Detection Level
+ 147 $ff bitmask: PHY_ED_LEVEL.ED_LEVEL \ Energy Detection Level
+$148 constant PHY_CC_CCA \ Transceiver Clear Channel Asse
+ $80 constant PHY_CC_CCA_CCA_REQUEST \ Manual CCA Measurement Request
+ 148 $80 bitmask: PHY_CC_CCA.CCA_REQUEST \ Manual CCA Measurement Request
+ $60 constant PHY_CC_CCA_CCA_MODE \ Select CCA Measurement Mode
+ 148 $60 bitmask: PHY_CC_CCA.CCA_MODE \ Select CCA Measurement Mode
+ $1f constant PHY_CC_CCA_CHANNEL \ RX/TX Channel Selection
+ 148 $1f bitmask: PHY_CC_CCA.CHANNEL \ RX/TX Channel Selection
+$149 constant CCA_THRES \ Transceiver CCA Threshold Sett
+ $f0 constant CCA_THRES_CCA_CS_THRES \ CS Threshold Level for CCA Mea
+ 149 $f0 bitmask: CCA_THRES.CCA_CS_THRES \ CS Threshold Level for CCA Mea
+ $f constant CCA_THRES_CCA_ED_THRES \ ED Threshold Level for CCA Mea
+ 149 $f bitmask: CCA_THRES.CCA_ED_THRES \ ED Threshold Level for CCA Mea
+$14a constant RX_CTRL \ Transceiver Receive Control Re
+ $f constant RX_CTRL_PDT_THRES \ Receiver Sensitivity Control
+ 14a $f bitmask: RX_CTRL.PDT_THRES \ Receiver Sensitivity Control
+$14b constant SFD_VALUE \ Start of Frame Delimiter Value
+ $ff constant SFD_VALUE_SFD_VALUE \ Start of Frame Delimiter Value
+ 14b $ff bitmask: SFD_VALUE.SFD_VALUE \ Start of Frame Delimiter Value
+$14c constant TRX_CTRL_2 \ Transceiver Control Register 2
+ $80 constant TRX_CTRL_2_RX_SAFE_MODE \ RX Safe Mode
+ 14c $80 bitmask: TRX_CTRL_2.RX_SAFE_MODE \ RX Safe Mode
+ $7c constant TRX_CTRL_2_Res \ Reserved
+ 14c $7c bitmask: TRX_CTRL_2.Res \ Reserved
+ $3 constant TRX_CTRL_2_OQPSK_DATA_RATE \ Data Rate Selection
+ 14c $3 bitmask: TRX_CTRL_2.OQPSK_DATA_RATE \ Data Rate Selection
+$14d constant ANT_DIV \ Antenna Diversity Control Regi
+ $80 constant ANT_DIV_ANT_SEL \ Antenna Diversity Antenna Stat
+ 14d $80 bitmask: ANT_DIV.ANT_SEL \ Antenna Diversity Antenna Stat
+ $70 constant ANT_DIV_Res \ Reserved
+ 14d $70 bitmask: ANT_DIV.Res \ Reserved
+ $8 constant ANT_DIV_ANT_DIV_EN \ Enable Antenna Diversity
+ 14d $8 bitmask: ANT_DIV.ANT_DIV_EN \ Enable Antenna Diversity
+ $4 constant ANT_DIV_ANT_EXT_SW_EN \ Enable External Antenna Switch
+ 14d $4 bitmask: ANT_DIV.ANT_EXT_SW_EN \ Enable External Antenna Switch
+ $3 constant ANT_DIV_ANT_CTRL \ Static Antenna Diversity Switc
+ 14d $3 bitmask: ANT_DIV.ANT_CTRL \ Static Antenna Diversity Switc
+$14e constant IRQ_MASK \ Transceiver Interrupt Enable R
+ $80 constant IRQ_MASK_AWAKE_EN \ Awake Interrupt Enable
+ 14e $80 bitmask: IRQ_MASK.AWAKE_EN \ Awake Interrupt Enable
+ $40 constant IRQ_MASK_TX_END_EN \ TX_END Interrupt Enable
+ 14e $40 bitmask: IRQ_MASK.TX_END_EN \ TX_END Interrupt Enable
+ $20 constant IRQ_MASK_AMI_EN \ Address Match Interrupt Enable
+ 14e $20 bitmask: IRQ_MASK.AMI_EN \ Address Match Interrupt Enable
+ $10 constant IRQ_MASK_CCA_ED_DONE_EN \ End of ED Measurement Interrup
+ 14e $10 bitmask: IRQ_MASK.CCA_ED_DONE_EN \ End of ED Measurement Interrup
+ $8 constant IRQ_MASK_RX_END_EN \ RX_END Interrupt Enable
+ 14e $8 bitmask: IRQ_MASK.RX_END_EN \ RX_END Interrupt Enable
+ $4 constant IRQ_MASK_RX_START_EN \ RX_START Interrupt Enable
+ 14e $4 bitmask: IRQ_MASK.RX_START_EN \ RX_START Interrupt Enable
+ $2 constant IRQ_MASK_PLL_UNLOCK_EN \ PLL Unlock Interrupt Enable
+ 14e $2 bitmask: IRQ_MASK.PLL_UNLOCK_EN \ PLL Unlock Interrupt Enable
+ $1 constant IRQ_MASK_PLL_LOCK_EN \ PLL Lock Interrupt Enable
+ 14e $1 bitmask: IRQ_MASK.PLL_LOCK_EN \ PLL Lock Interrupt Enable
+$14f constant IRQ_STATUS \ Transceiver Interrupt Status R
+ $80 constant IRQ_STATUS_AWAKE \ Awake Interrupt Status
+ 14f $80 bitmask: IRQ_STATUS.AWAKE \ Awake Interrupt Status
+ $40 constant IRQ_STATUS_TX_END \ TX_END Interrupt Status
+ 14f $40 bitmask: IRQ_STATUS.TX_END \ TX_END Interrupt Status
+ $20 constant IRQ_STATUS_AMI \ Address Match Interrupt Status
+ 14f $20 bitmask: IRQ_STATUS.AMI \ Address Match Interrupt Status
+ $10 constant IRQ_STATUS_CCA_ED_DONE \ End of ED Measurement Interrup
+ 14f $10 bitmask: IRQ_STATUS.CCA_ED_DONE \ End of ED Measurement Interrup
+ $8 constant IRQ_STATUS_RX_END \ RX_END Interrupt Status
+ 14f $8 bitmask: IRQ_STATUS.RX_END \ RX_END Interrupt Status
+ $4 constant IRQ_STATUS_RX_START \ RX_START Interrupt Status
+ 14f $4 bitmask: IRQ_STATUS.RX_START \ RX_START Interrupt Status
+ $2 constant IRQ_STATUS_PLL_UNLOCK \ PLL Unlock Interrupt Status
+ 14f $2 bitmask: IRQ_STATUS.PLL_UNLOCK \ PLL Unlock Interrupt Status
+ $1 constant IRQ_STATUS_PLL_LOCK \ PLL Lock Interrupt Status
+ 14f $1 bitmask: IRQ_STATUS.PLL_LOCK \ PLL Lock Interrupt Status
+$be constant IRQ_MASK1 \ Transceiver Interrupt Enable R
+ $e0 constant IRQ_MASK1_Res \ Reserved Bit
+ be $e0 bitmask: IRQ_MASK1.Res \ Reserved Bit
+ $10 constant IRQ_MASK1_MAF_3_AMI_EN \ Address Match Interrupt enable
+ be $10 bitmask: IRQ_MASK1.MAF_3_AMI_EN \ Address Match Interrupt enable
+ $8 constant IRQ_MASK1_MAF_2_AMI_EN \ Address Match Interrupt enable
+ be $8 bitmask: IRQ_MASK1.MAF_2_AMI_EN \ Address Match Interrupt enable
+ $4 constant IRQ_MASK1_MAF_1_AMI_EN \ Address Match Interrupt enable
+ be $4 bitmask: IRQ_MASK1.MAF_1_AMI_EN \ Address Match Interrupt enable
+ $2 constant IRQ_MASK1_MAF_0_AMI_EN \ Address Match Interrupt enable
+ be $2 bitmask: IRQ_MASK1.MAF_0_AMI_EN \ Address Match Interrupt enable
+ $1 constant IRQ_MASK1_TX_START_EN \ Transmit Start Interrupt enabl
+ be $1 bitmask: IRQ_MASK1.TX_START_EN \ Transmit Start Interrupt enabl
+$bf constant IRQ_STATUS1 \ Transceiver Interrupt Status R
+ $e0 constant IRQ_STATUS1_Res \ Reserved Bit
+ bf $e0 bitmask: IRQ_STATUS1.Res \ Reserved Bit
+ $10 constant IRQ_STATUS1_MAF_3_AMI \ Address Match Interrupt Status
+ bf $10 bitmask: IRQ_STATUS1.MAF_3_AMI \ Address Match Interrupt Status
+ $8 constant IRQ_STATUS1_MAF_2_AMI \ Address Match Interrupt Status
+ bf $8 bitmask: IRQ_STATUS1.MAF_2_AMI \ Address Match Interrupt Status
+ $4 constant IRQ_STATUS1_MAF_1_AMI \ Address Match Interrupt Status
+ bf $4 bitmask: IRQ_STATUS1.MAF_1_AMI \ Address Match Interrupt Status
+ $2 constant IRQ_STATUS1_MAF_0_AMI \ Address Match Interrupt Status
+ bf $2 bitmask: IRQ_STATUS1.MAF_0_AMI \ Address Match Interrupt Status
+ $1 constant IRQ_STATUS1_TX_START \ Transmit Start Interrupt Statu
+ bf $1 bitmask: IRQ_STATUS1.TX_START \ Transmit Start Interrupt Statu
+$150 constant VREG_CTRL \ Voltage Regulator Control and
+ $80 constant VREG_CTRL_AVREG_EXT \ Use External AVDD Regulator
+ 150 $80 bitmask: VREG_CTRL.AVREG_EXT \ Use External AVDD Regulator
+ $40 constant VREG_CTRL_AVDD_OK \ AVDD Supply Voltage Valid
+ 150 $40 bitmask: VREG_CTRL.AVDD_OK \ AVDD Supply Voltage Valid
+ $8 constant VREG_CTRL_DVREG_EXT \ Use External DVDD Regulator
+ 150 $8 bitmask: VREG_CTRL.DVREG_EXT \ Use External DVDD Regulator
+ $4 constant VREG_CTRL_DVDD_OK \ DVDD Supply Voltage Valid
+ 150 $4 bitmask: VREG_CTRL.DVDD_OK \ DVDD Supply Voltage Valid
+$151 constant BATMON \ Battery Monitor Control and St
+ $80 constant BATMON_BAT_LOW \ Battery Monitor Interrupt Stat
+ 151 $80 bitmask: BATMON.BAT_LOW \ Battery Monitor Interrupt Stat
+ $40 constant BATMON_BAT_LOW_EN \ Battery Monitor Interrupt Enab
+ 151 $40 bitmask: BATMON.BAT_LOW_EN \ Battery Monitor Interrupt Enab
+ $20 constant BATMON_BATMON_OK \ Battery Monitor Status
+ 151 $20 bitmask: BATMON.BATMON_OK \ Battery Monitor Status
+ $10 constant BATMON_BATMON_HR \ Battery Monitor Voltage Range
+ 151 $10 bitmask: BATMON.BATMON_HR \ Battery Monitor Voltage Range
+ $f constant BATMON_BATMON_VTH \ Battery Monitor Threshold Volt
+ 151 $f bitmask: BATMON.BATMON_VTH \ Battery Monitor Threshold Volt
+$152 constant XOSC_CTRL \ Crystal Oscillator Control Reg
+ $f0 constant XOSC_CTRL_XTAL_MODE \ Crystal Oscillator Operating M
+ 152 $f0 bitmask: XOSC_CTRL.XTAL_MODE \ Crystal Oscillator Operating M
+ $f constant XOSC_CTRL_XTAL_TRIM \ Crystal Oscillator Load Capaci
+ 152 $f bitmask: XOSC_CTRL.XTAL_TRIM \ Crystal Oscillator Load Capaci
+$153 constant CC_CTRL_0 \ Channel Control Register 0
+ $ff constant CC_CTRL_0_CC_NUMBER \ Channel Number
+ 153 $ff bitmask: CC_CTRL_0.CC_NUMBER \ Channel Number
+$154 constant CC_CTRL_1 \ Channel Control Register 1
+ $f constant CC_CTRL_1_CC_BAND \ Channel Band
+ 154 $f bitmask: CC_CTRL_1.CC_BAND \ Channel Band
+$155 constant RX_SYN \ Transceiver Receiver Sensitivi
+ $80 constant RX_SYN_RX_PDT_DIS \ Prevent Frame Reception
+ 155 $80 bitmask: RX_SYN.RX_PDT_DIS \ Prevent Frame Reception
+ $40 constant RX_SYN_RX_OVERRIDE \ Receiver Override Function
+ 155 $40 bitmask: RX_SYN.RX_OVERRIDE \ Receiver Override Function
+ $30 constant RX_SYN_Res \ Reserved
+ 155 $30 bitmask: RX_SYN.Res \ Reserved
+ $f constant RX_SYN_RX_PDT_LEVEL \ Reduce Receiver Sensitivity
+ 155 $f bitmask: RX_SYN.RX_PDT_LEVEL \ Reduce Receiver Sensitivity
+$156 constant TRX_RPC \ Transceiver Reduced Power Cons
+ $c0 constant TRX_RPC_RX_RPC_CTRL \ Smart Receiving Mode Timing
+ 156 $c0 bitmask: TRX_RPC.RX_RPC_CTRL \ Smart Receiving Mode Timing
+ $20 constant TRX_RPC_RX_RPC_EN \ Reciver Smart Receiving Mode E
+ 156 $20 bitmask: TRX_RPC.RX_RPC_EN \ Reciver Smart Receiving Mode E
+ $10 constant TRX_RPC_PDT_RPC_EN \ Smart Receiving Mode Reduced S
+ 156 $10 bitmask: TRX_RPC.PDT_RPC_EN \ Smart Receiving Mode Reduced S
+ $8 constant TRX_RPC_PLL_RPC_EN \ PLL Smart Receiving Mode Enabl
+ 156 $8 bitmask: TRX_RPC.PLL_RPC_EN \ PLL Smart Receiving Mode Enabl
+ $4 constant TRX_RPC_Res0 \ Reserved
+ 156 $4 bitmask: TRX_RPC.Res0 \ Reserved
+ $2 constant TRX_RPC_IPAN_RPC_EN \ Smart Receiving Mode IPAN Hand
+ 156 $2 bitmask: TRX_RPC.IPAN_RPC_EN \ Smart Receiving Mode IPAN Hand
+ $1 constant TRX_RPC_XAH_RPC_EN \ Smart Receiving in Extended Op
+ 156 $1 bitmask: TRX_RPC.XAH_RPC_EN \ Smart Receiving in Extended Op
+$157 constant XAH_CTRL_1 \ Transceiver Acknowledgment Fra
+ $c0 constant XAH_CTRL_1_Res \ Reserved Bit
+ 157 $c0 bitmask: XAH_CTRL_1.Res \ Reserved Bit
+ $20 constant XAH_CTRL_1_AACK_FLTR_RES_FT \ Filter Reserved Frames
+ 157 $20 bitmask: XAH_CTRL_1.AACK_FLTR_RES_FT \ Filter Reserved Frames
+ $10 constant XAH_CTRL_1_AACK_UPLD_RES_FT \ Process Reserved Frames
+ 157 $10 bitmask: XAH_CTRL_1.AACK_UPLD_RES_FT \ Process Reserved Frames
+ $8 constant XAH_CTRL_1_Res \ Reserved Bit
+ 157 $8 bitmask: XAH_CTRL_1.Res \ Reserved Bit
+ $4 constant XAH_CTRL_1_AACK_ACK_TIME \ Reduce Acknowledgment Time
+ 157 $4 bitmask: XAH_CTRL_1.AACK_ACK_TIME \ Reduce Acknowledgment Time
+ $2 constant XAH_CTRL_1_AACK_PROM_MODE \ Enable Promiscuous Mode
+ 157 $2 bitmask: XAH_CTRL_1.AACK_PROM_MODE \ Enable Promiscuous Mode
+ $1 constant XAH_CTRL_1_Res \ Reserved Bit
+ 157 $1 bitmask: XAH_CTRL_1.Res \ Reserved Bit
+$158 constant FTN_CTRL \ Transceiver Filter Tuning Cont
+ $80 constant FTN_CTRL_FTN_START \ Start Calibration Loop of Filt
+ 158 $80 bitmask: FTN_CTRL.FTN_START \ Start Calibration Loop of Filt
+$15a constant PLL_CF \ Transceiver Center Frequency C
+ $80 constant PLL_CF_PLL_CF_START \ Start Center Frequency Calibra
+ 15a $80 bitmask: PLL_CF.PLL_CF_START \ Start Center Frequency Calibra
+$15b constant PLL_DCU \ Transceiver Delay Cell Calibra
+ $80 constant PLL_DCU_PLL_DCU_START \ Start Delay Cell Calibration
+ 15b $80 bitmask: PLL_DCU.PLL_DCU_START \ Start Delay Cell Calibration
+$15c constant PART_NUM \ Device Identification Register
+ $ff constant PART_NUM_PART_NUM \ Part Number
+ 15c $ff bitmask: PART_NUM.PART_NUM \ Part Number
+$15d constant VERSION_NUM \ Device Identification Register
+ $ff constant VERSION_NUM_VERSION_NUM \ Version Number
+ 15d $ff bitmask: VERSION_NUM.VERSION_NUM \ Version Number
+$15e constant MAN_ID_0 \ Device Identification Register
+ $80 constant MAN_ID_0_MAN_ID_07 \ Manufacturer ID (Low Byte)
+ 15e $80 bitmask: MAN_ID_0.MAN_ID_07 \ Manufacturer ID (Low Byte)
+ $40 constant MAN_ID_0_MAN_ID_06 \ Manufacturer ID (Low Byte)
+ 15e $40 bitmask: MAN_ID_0.MAN_ID_06 \ Manufacturer ID (Low Byte)
+ $20 constant MAN_ID_0_MAN_ID_05 \ Manufacturer ID (Low Byte)
+ 15e $20 bitmask: MAN_ID_0.MAN_ID_05 \ Manufacturer ID (Low Byte)
+ $10 constant MAN_ID_0_MAN_ID_04 \ Manufacturer ID (Low Byte)
+ 15e $10 bitmask: MAN_ID_0.MAN_ID_04 \ Manufacturer ID (Low Byte)
+ $8 constant MAN_ID_0_MAN_ID_03 \ Manufacturer ID (Low Byte)
+ 15e $8 bitmask: MAN_ID_0.MAN_ID_03 \ Manufacturer ID (Low Byte)
+ $4 constant MAN_ID_0_MAN_ID_02 \ Manufacturer ID (Low Byte)
+ 15e $4 bitmask: MAN_ID_0.MAN_ID_02 \ Manufacturer ID (Low Byte)
+ $2 constant MAN_ID_0_MAN_ID_01 \ Manufacturer ID (Low Byte)
+ 15e $2 bitmask: MAN_ID_0.MAN_ID_01 \ Manufacturer ID (Low Byte)
+ $1 constant MAN_ID_0_MAN_ID_00 \ Manufacturer ID (Low Byte)
+ 15e $1 bitmask: MAN_ID_0.MAN_ID_00 \ Manufacturer ID (Low Byte)
+$15f constant MAN_ID_1 \ Device Identification Register
+ $ff constant MAN_ID_1_MAN_ID_ \ Manufacturer ID (High Byte)
+ 15f $ff bitmask: MAN_ID_1.MAN_ID_ \ Manufacturer ID (High Byte)
+$160 constant SHORT_ADDR_0 \ Transceiver MAC Short Address
+ $80 constant SHORT_ADDR_0_SHORT_ADDR_07 \ MAC Short Address
+ 160 $80 bitmask: SHORT_ADDR_0.SHORT_ADDR_07 \ MAC Short Address
+ $40 constant SHORT_ADDR_0_SHORT_ADDR_06 \ MAC Short Address
+ 160 $40 bitmask: SHORT_ADDR_0.SHORT_ADDR_06 \ MAC Short Address
+ $20 constant SHORT_ADDR_0_SHORT_ADDR_05 \ MAC Short Address
+ 160 $20 bitmask: SHORT_ADDR_0.SHORT_ADDR_05 \ MAC Short Address
+ $10 constant SHORT_ADDR_0_SHORT_ADDR_04 \ MAC Short Address
+ 160 $10 bitmask: SHORT_ADDR_0.SHORT_ADDR_04 \ MAC Short Address
+ $8 constant SHORT_ADDR_0_SHORT_ADDR_03 \ MAC Short Address
+ 160 $8 bitmask: SHORT_ADDR_0.SHORT_ADDR_03 \ MAC Short Address
+ $4 constant SHORT_ADDR_0_SHORT_ADDR_02 \ MAC Short Address
+ 160 $4 bitmask: SHORT_ADDR_0.SHORT_ADDR_02 \ MAC Short Address
+ $2 constant SHORT_ADDR_0_SHORT_ADDR_01 \ MAC Short Address
+ 160 $2 bitmask: SHORT_ADDR_0.SHORT_ADDR_01 \ MAC Short Address
+ $1 constant SHORT_ADDR_0_SHORT_ADDR_00 \ MAC Short Address
+ 160 $1 bitmask: SHORT_ADDR_0.SHORT_ADDR_00 \ MAC Short Address
+$161 constant SHORT_ADDR_1 \ Transceiver MAC Short Address
+ $ff constant SHORT_ADDR_1_SHORT_ADDR_ \ MAC Short Address
+ 161 $ff bitmask: SHORT_ADDR_1.SHORT_ADDR_ \ MAC Short Address
+$162 constant PAN_ID_0 \ Transceiver Personal Area Netw
+ $80 constant PAN_ID_0_PAN_ID_07 \ MAC Personal Area Network ID
+ 162 $80 bitmask: PAN_ID_0.PAN_ID_07 \ MAC Personal Area Network ID
+ $40 constant PAN_ID_0_PAN_ID_06 \ MAC Personal Area Network ID
+ 162 $40 bitmask: PAN_ID_0.PAN_ID_06 \ MAC Personal Area Network ID
+ $20 constant PAN_ID_0_PAN_ID_05 \ MAC Personal Area Network ID
+ 162 $20 bitmask: PAN_ID_0.PAN_ID_05 \ MAC Personal Area Network ID
+ $10 constant PAN_ID_0_PAN_ID_04 \ MAC Personal Area Network ID
+ 162 $10 bitmask: PAN_ID_0.PAN_ID_04 \ MAC Personal Area Network ID
+ $8 constant PAN_ID_0_PAN_ID_03 \ MAC Personal Area Network ID
+ 162 $8 bitmask: PAN_ID_0.PAN_ID_03 \ MAC Personal Area Network ID
+ $4 constant PAN_ID_0_PAN_ID_02 \ MAC Personal Area Network ID
+ 162 $4 bitmask: PAN_ID_0.PAN_ID_02 \ MAC Personal Area Network ID
+ $2 constant PAN_ID_0_PAN_ID_01 \ MAC Personal Area Network ID
+ 162 $2 bitmask: PAN_ID_0.PAN_ID_01 \ MAC Personal Area Network ID
+ $1 constant PAN_ID_0_PAN_ID_00 \ MAC Personal Area Network ID
+ 162 $1 bitmask: PAN_ID_0.PAN_ID_00 \ MAC Personal Area Network ID
+$163 constant PAN_ID_1 \ Transceiver Personal Area Netw
+ $ff constant PAN_ID_1_PAN_ID_ \ MAC Personal Area Network ID
+ 163 $ff bitmask: PAN_ID_1.PAN_ID_ \ MAC Personal Area Network ID
+$164 constant IEEE_ADDR_0 \ Transceiver MAC IEEE Address R
+ $80 constant IEEE_ADDR_0_IEEE_ADDR_07 \ MAC IEEE Address
+ 164 $80 bitmask: IEEE_ADDR_0.IEEE_ADDR_07 \ MAC IEEE Address
+ $40 constant IEEE_ADDR_0_IEEE_ADDR_06 \ MAC IEEE Address
+ 164 $40 bitmask: IEEE_ADDR_0.IEEE_ADDR_06 \ MAC IEEE Address
+ $20 constant IEEE_ADDR_0_IEEE_ADDR_05 \ MAC IEEE Address
+ 164 $20 bitmask: IEEE_ADDR_0.IEEE_ADDR_05 \ MAC IEEE Address
+ $10 constant IEEE_ADDR_0_IEEE_ADDR_04 \ MAC IEEE Address
+ 164 $10 bitmask: IEEE_ADDR_0.IEEE_ADDR_04 \ MAC IEEE Address
+ $8 constant IEEE_ADDR_0_IEEE_ADDR_03 \ MAC IEEE Address
+ 164 $8 bitmask: IEEE_ADDR_0.IEEE_ADDR_03 \ MAC IEEE Address
+ $4 constant IEEE_ADDR_0_IEEE_ADDR_02 \ MAC IEEE Address
+ 164 $4 bitmask: IEEE_ADDR_0.IEEE_ADDR_02 \ MAC IEEE Address
+ $2 constant IEEE_ADDR_0_IEEE_ADDR_01 \ MAC IEEE Address
+ 164 $2 bitmask: IEEE_ADDR_0.IEEE_ADDR_01 \ MAC IEEE Address
+ $1 constant IEEE_ADDR_0_IEEE_ADDR_00 \ MAC IEEE Address
+ 164 $1 bitmask: IEEE_ADDR_0.IEEE_ADDR_00 \ MAC IEEE Address
+$165 constant IEEE_ADDR_1 \ Transceiver MAC IEEE Address R
+ $ff constant IEEE_ADDR_1_IEEE_ADDR_ \ MAC IEEE Address
+ 165 $ff bitmask: IEEE_ADDR_1.IEEE_ADDR_ \ MAC IEEE Address
+$166 constant IEEE_ADDR_2 \ Transceiver MAC IEEE Address R
+ $ff constant IEEE_ADDR_2_IEEE_ADDR_ \ MAC IEEE Address
+ 166 $ff bitmask: IEEE_ADDR_2.IEEE_ADDR_ \ MAC IEEE Address
+$167 constant IEEE_ADDR_3 \ Transceiver MAC IEEE Address R
+ $ff constant IEEE_ADDR_3_IEEE_ADDR_ \ MAC IEEE Address
+ 167 $ff bitmask: IEEE_ADDR_3.IEEE_ADDR_ \ MAC IEEE Address
+$168 constant IEEE_ADDR_4 \ Transceiver MAC IEEE Address R
+ $ff constant IEEE_ADDR_4_IEEE_ADDR_ \ MAC IEEE Address
+ 168 $ff bitmask: IEEE_ADDR_4.IEEE_ADDR_ \ MAC IEEE Address
+$169 constant IEEE_ADDR_5 \ Transceiver MAC IEEE Address R
+ $ff constant IEEE_ADDR_5_IEEE_ADDR_ \ MAC IEEE Address
+ 169 $ff bitmask: IEEE_ADDR_5.IEEE_ADDR_ \ MAC IEEE Address
+$16a constant IEEE_ADDR_6 \ Transceiver MAC IEEE Address R
+ $ff constant IEEE_ADDR_6_IEEE_ADDR_ \ MAC IEEE Address
+ 16a $ff bitmask: IEEE_ADDR_6.IEEE_ADDR_ \ MAC IEEE Address
+$16b constant IEEE_ADDR_7 \ Transceiver MAC IEEE Address R
+ $ff constant IEEE_ADDR_7_IEEE_ADDR_ \ MAC IEEE Address
+ 16b $ff bitmask: IEEE_ADDR_7.IEEE_ADDR_ \ MAC IEEE Address
+$16c constant XAH_CTRL_0 \ Transceiver Extended Operating
+ $f0 constant XAH_CTRL_0_MAX_FRAME_RETRIES \ Maximum Number of Frame Re-tra
+ 16c $f0 bitmask: XAH_CTRL_0.MAX_FRAME_RETRIES \ Maximum Number of Frame Re-tra
+ $e constant XAH_CTRL_0_MAX_CSMA_RETRIES \ Maximum Number of CSMA-CA Proc
+ 16c $e bitmask: XAH_CTRL_0.MAX_CSMA_RETRIES \ Maximum Number of CSMA-CA Proc
+ $1 constant XAH_CTRL_0_SLOTTED_OPERATION \ Set Slotted Acknowledgment
+ 16c $1 bitmask: XAH_CTRL_0.SLOTTED_OPERATION \ Set Slotted Acknowledgment
+$16d constant CSMA_SEED_0 \ Transceiver CSMA-CA Random Num
+ $80 constant CSMA_SEED_0_CSMA_SEED_07 \ Seed Value for CSMA Random Num
+ 16d $80 bitmask: CSMA_SEED_0.CSMA_SEED_07 \ Seed Value for CSMA Random Num
+ $40 constant CSMA_SEED_0_CSMA_SEED_06 \ Seed Value for CSMA Random Num
+ 16d $40 bitmask: CSMA_SEED_0.CSMA_SEED_06 \ Seed Value for CSMA Random Num
+ $20 constant CSMA_SEED_0_CSMA_SEED_05 \ Seed Value for CSMA Random Num
+ 16d $20 bitmask: CSMA_SEED_0.CSMA_SEED_05 \ Seed Value for CSMA Random Num
+ $10 constant CSMA_SEED_0_CSMA_SEED_04 \ Seed Value for CSMA Random Num
+ 16d $10 bitmask: CSMA_SEED_0.CSMA_SEED_04 \ Seed Value for CSMA Random Num
+ $8 constant CSMA_SEED_0_CSMA_SEED_03 \ Seed Value for CSMA Random Num
+ 16d $8 bitmask: CSMA_SEED_0.CSMA_SEED_03 \ Seed Value for CSMA Random Num
+ $4 constant CSMA_SEED_0_CSMA_SEED_02 \ Seed Value for CSMA Random Num
+ 16d $4 bitmask: CSMA_SEED_0.CSMA_SEED_02 \ Seed Value for CSMA Random Num
+ $2 constant CSMA_SEED_0_CSMA_SEED_01 \ Seed Value for CSMA Random Num
+ 16d $2 bitmask: CSMA_SEED_0.CSMA_SEED_01 \ Seed Value for CSMA Random Num
+ $1 constant CSMA_SEED_0_CSMA_SEED_00 \ Seed Value for CSMA Random Num
+ 16d $1 bitmask: CSMA_SEED_0.CSMA_SEED_00 \ Seed Value for CSMA Random Num
+$16e constant CSMA_SEED_1 \ Transceiver Acknowledgment Fra
+ $c0 constant CSMA_SEED_1_AACK_FVN_MODE \ Acknowledgment Frame Filter Mo
+ 16e $c0 bitmask: CSMA_SEED_1.AACK_FVN_MODE \ Acknowledgment Frame Filter Mo
+ $20 constant CSMA_SEED_1_AACK_SET_PD \ Set Frame Pending Sub-field
+ 16e $20 bitmask: CSMA_SEED_1.AACK_SET_PD \ Set Frame Pending Sub-field
+ $10 constant CSMA_SEED_1_AACK_DIS_ACK \ Disable Acknowledgment Frame T
+ 16e $10 bitmask: CSMA_SEED_1.AACK_DIS_ACK \ Disable Acknowledgment Frame T
+ $8 constant CSMA_SEED_1_AACK_I_AM_COORD \ Set Personal Area Network Coor
+ 16e $8 bitmask: CSMA_SEED_1.AACK_I_AM_COORD \ Set Personal Area Network Coor
+ $7 constant CSMA_SEED_1_CSMA_SEED_1 \ Seed Value for CSMA Random Num
+ 16e $7 bitmask: CSMA_SEED_1.CSMA_SEED_1 \ Seed Value for CSMA Random Num
+$16f constant CSMA_BE \ Transceiver CSMA-CA Back-off E
+ $f0 constant CSMA_BE_MAX_BE \ Maximum Back-off Exponent
+ 16f $f0 bitmask: CSMA_BE.MAX_BE \ Maximum Back-off Exponent
+ $f constant CSMA_BE_MIN_BE \ Minimum Back-off Exponent
+ 16f $f bitmask: CSMA_BE.MIN_BE \ Minimum Back-off Exponent
+$176 constant TST_CTRL_DIGI \ Transceiver Digital Test Contr
+ $f constant TST_CTRL_DIGI_TST_CTRL_DIG \ Digital Test Controller Regist
+ 176 $f bitmask: TST_CTRL_DIGI.TST_CTRL_DIG \ Digital Test Controller Regist
+$17b constant TST_RX_LENGTH \ Transceiver Received Frame Len
+ $ff constant TST_RX_LENGTH_RX_LENGTH \ Received Frame Length
+ 17b $ff bitmask: TST_RX_LENGTH.RX_LENGTH \ Received Frame Length
+$180 constant TRXFBST \ Start of frame buffer
+$1ff constant TRXFBEND \ End of frame buffer
+\ SYMCNT
+$fc constant SCTSTRHH \ Symbol Counter Transmit Frame
+ $ff constant SCTSTRHH_SCTSTRHH \ Symbol Counter Transmit Frame
+ fc $ff bitmask: SCTSTRHH.SCTSTRHH \ Symbol Counter Transmit Frame
+$fb constant SCTSTRHL \ Symbol Counter Transmit Frame
+ $ff constant SCTSTRHL_SCTSTRHL \ Symbol Counter Transmit Frame
+ fb $ff bitmask: SCTSTRHL.SCTSTRHL \ Symbol Counter Transmit Frame
+$fa constant SCTSTRLH \ Symbol Counter Transmit Frame
+ $ff constant SCTSTRLH_SCTSTRLH \ Symbol Counter Transmit Frame
+ fa $ff bitmask: SCTSTRLH.SCTSTRLH \ Symbol Counter Transmit Frame
+$f9 constant SCTSTRLL \ Symbol Counter Transmit Frame
+ $ff constant SCTSTRLL_SCTSTRLL \ Symbol Counter Transmit Frame
+ f9 $ff bitmask: SCTSTRLL.SCTSTRLL \ Symbol Counter Transmit Frame
+$f8 constant SCOCR1HH \ Symbol Counter Output Compare
+ $ff constant SCOCR1HH_SCOCR1HH \ Symbol Counter Output Compare
+ f8 $ff bitmask: SCOCR1HH.SCOCR1HH \ Symbol Counter Output Compare
+$f7 constant SCOCR1HL \ Symbol Counter Output Compare
+ $ff constant SCOCR1HL_SCOCR1HL \ Symbol Counter Output Compare
+ f7 $ff bitmask: SCOCR1HL.SCOCR1HL \ Symbol Counter Output Compare
+$f6 constant SCOCR1LH \ Symbol Counter Output Compare
+ $ff constant SCOCR1LH_SCOCR1LH \ Symbol Counter Output Compare
+ f6 $ff bitmask: SCOCR1LH.SCOCR1LH \ Symbol Counter Output Compare
+$f5 constant SCOCR1LL \ Symbol Counter Output Compare
+ $ff constant SCOCR1LL_SCOCR1LL \ Symbol Counter Output Compare
+ f5 $ff bitmask: SCOCR1LL.SCOCR1LL \ Symbol Counter Output Compare
+$f4 constant SCOCR2HH \ Symbol Counter Output Compare
+ $ff constant SCOCR2HH_SCOCR2HH \ Symbol Counter Output Compare
+ f4 $ff bitmask: SCOCR2HH.SCOCR2HH \ Symbol Counter Output Compare
+$f3 constant SCOCR2HL \ Symbol Counter Output Compare
+ $ff constant SCOCR2HL_SCOCR2HL \ Symbol Counter Output Compare
+ f3 $ff bitmask: SCOCR2HL.SCOCR2HL \ Symbol Counter Output Compare
+$f2 constant SCOCR2LH \ Symbol Counter Output Compare
+ $ff constant SCOCR2LH_SCOCR2LH \ Symbol Counter Output Compare
+ f2 $ff bitmask: SCOCR2LH.SCOCR2LH \ Symbol Counter Output Compare
+$f1 constant SCOCR2LL \ Symbol Counter Output Compare
+ $ff constant SCOCR2LL_SCOCR2LL \ Symbol Counter Output Compare
+ f1 $ff bitmask: SCOCR2LL.SCOCR2LL \ Symbol Counter Output Compare
+$f0 constant SCOCR3HH \ Symbol Counter Output Compare
+ $ff constant SCOCR3HH_SCOCR3HH \ Symbol Counter Output Compare
+ f0 $ff bitmask: SCOCR3HH.SCOCR3HH \ Symbol Counter Output Compare
+$ef constant SCOCR3HL \ Symbol Counter Output Compare
+ $ff constant SCOCR3HL_SCOCR3HL \ Symbol Counter Output Compare
+ ef $ff bitmask: SCOCR3HL.SCOCR3HL \ Symbol Counter Output Compare
+$ee constant SCOCR3LH \ Symbol Counter Output Compare
+ $ff constant SCOCR3LH_SCOCR3LH \ Symbol Counter Output Compare
+ ee $ff bitmask: SCOCR3LH.SCOCR3LH \ Symbol Counter Output Compare
+$ed constant SCOCR3LL \ Symbol Counter Output Compare
+ $ff constant SCOCR3LL_SCOCR3LL \ Symbol Counter Output Compare
+ ed $ff bitmask: SCOCR3LL.SCOCR3LL \ Symbol Counter Output Compare
+$ec constant SCTSRHH \ Symbol Counter Frame Timestamp
+ $ff constant SCTSRHH_SCTSRHH \ Symbol Counter Frame Timestamp
+ ec $ff bitmask: SCTSRHH.SCTSRHH \ Symbol Counter Frame Timestamp
+$eb constant SCTSRHL \ Symbol Counter Frame Timestamp
+ $ff constant SCTSRHL_SCTSRHL \ Symbol Counter Frame Timestamp
+ eb $ff bitmask: SCTSRHL.SCTSRHL \ Symbol Counter Frame Timestamp
+$ea constant SCTSRLH \ Symbol Counter Frame Timestamp
+ $ff constant SCTSRLH_SCTSRLH \ Symbol Counter Frame Timestamp
+ ea $ff bitmask: SCTSRLH.SCTSRLH \ Symbol Counter Frame Timestamp
+$e9 constant SCTSRLL \ Symbol Counter Frame Timestamp
+ $ff constant SCTSRLL_SCTSRLL \ Symbol Counter Frame Timestamp
+ e9 $ff bitmask: SCTSRLL.SCTSRLL \ Symbol Counter Frame Timestamp
+$e8 constant SCBTSRHH \ Symbol Counter Beacon Timestam
+ $ff constant SCBTSRHH_SCBTSRHH \ Symbol Counter Beacon Timestam
+ e8 $ff bitmask: SCBTSRHH.SCBTSRHH \ Symbol Counter Beacon Timestam
+$e7 constant SCBTSRHL \ Symbol Counter Beacon Timestam
+ $ff constant SCBTSRHL_SCBTSRHL \ Symbol Counter Beacon Timestam
+ e7 $ff bitmask: SCBTSRHL.SCBTSRHL \ Symbol Counter Beacon Timestam
+$e6 constant SCBTSRLH \ Symbol Counter Beacon Timestam
+ $ff constant SCBTSRLH_SCBTSRLH \ Symbol Counter Beacon Timestam
+ e6 $ff bitmask: SCBTSRLH.SCBTSRLH \ Symbol Counter Beacon Timestam
+$e5 constant SCBTSRLL \ Symbol Counter Beacon Timestam
+ $ff constant SCBTSRLL_SCBTSRLL \ Symbol Counter Beacon Timestam
+ e5 $ff bitmask: SCBTSRLL.SCBTSRLL \ Symbol Counter Beacon Timestam
+$e4 constant SCCNTHH \ Symbol Counter Register HH-Byt
+ $ff constant SCCNTHH_SCCNTHH \ Symbol Counter Register HH-Byt
+ e4 $ff bitmask: SCCNTHH.SCCNTHH \ Symbol Counter Register HH-Byt
+$e3 constant SCCNTHL \ Symbol Counter Register HL-Byt
+ $ff constant SCCNTHL_SCCNTHL \ Symbol Counter Register HL-Byt
+ e3 $ff bitmask: SCCNTHL.SCCNTHL \ Symbol Counter Register HL-Byt
+$e2 constant SCCNTLH \ Symbol Counter Register LH-Byt
+ $ff constant SCCNTLH_SCCNTLH \ Symbol Counter Register LH-Byt
+ e2 $ff bitmask: SCCNTLH.SCCNTLH \ Symbol Counter Register LH-Byt
+$e1 constant SCCNTLL \ Symbol Counter Register LL-Byt
+ $ff constant SCCNTLL_SCCNTLL \ Symbol Counter Register LL-Byt
+ e1 $ff bitmask: SCCNTLL.SCCNTLL \ Symbol Counter Register LL-Byt
+$e0 constant SCIRQS \ Symbol Counter Interrupt Statu
+ $e0 constant SCIRQS_Res \ Reserved Bit
+ e0 $e0 bitmask: SCIRQS.Res \ Reserved Bit
+ $10 constant SCIRQS_IRQSBO \ Backoff Slot Counter IRQ
+ e0 $10 bitmask: SCIRQS.IRQSBO \ Backoff Slot Counter IRQ
+ $8 constant SCIRQS_IRQSOF \ Symbol Counter Overflow IRQ
+ e0 $8 bitmask: SCIRQS.IRQSOF \ Symbol Counter Overflow IRQ
+ $7 constant SCIRQS_IRQSCP \ Compare Unit 3 Compare Match I
+ e0 $7 bitmask: SCIRQS.IRQSCP \ Compare Unit 3 Compare Match I
+$df constant SCIRQM \ Symbol Counter Interrupt Mask
+ $e0 constant SCIRQM_Res \ Reserved Bit
+ df $e0 bitmask: SCIRQM.Res \ Reserved Bit
+ $10 constant SCIRQM_IRQMBO \ Backoff Slot Counter IRQ enabl
+ df $10 bitmask: SCIRQM.IRQMBO \ Backoff Slot Counter IRQ enabl
+ $8 constant SCIRQM_IRQMOF \ Symbol Counter Overflow IRQ en
+ df $8 bitmask: SCIRQM.IRQMOF \ Symbol Counter Overflow IRQ en
+ $7 constant SCIRQM_IRQMCP \ Symbol Counter Compare Match 3
+ df $7 bitmask: SCIRQM.IRQMCP \ Symbol Counter Compare Match 3
+$de constant SCSR \ Symbol Counter Status Register
+ $fe constant SCSR_Res \ Reserved Bit
+ de $fe bitmask: SCSR.Res \ Reserved Bit
+ $1 constant SCSR_SCBSY \ Symbol Counter busy
+ de $1 bitmask: SCSR.SCBSY \ Symbol Counter busy
+$dd constant SCCR1 \ Symbol Counter Control Registe
+ $c0 constant SCCR1_Res \ Reserved Bit
+ dd $c0 bitmask: SCCR1.Res \ Reserved Bit
+ $20 constant SCCR1_SCBTSM \ Symbol Counter Beacon Timestam
+ dd $20 bitmask: SCCR1.SCBTSM \ Symbol Counter Beacon Timestam
+ $1c constant SCCR1_SCCKDIV \ Clock divider for synchronous
+ dd $1c bitmask: SCCR1.SCCKDIV \ Clock divider for synchronous
+ $2 constant SCCR1_SCEECLK \ Enable External Clock Source o
+ dd $2 bitmask: SCCR1.SCEECLK \ Enable External Clock Source o
+ $1 constant SCCR1_SCENBO \ Backoff Slot Counter enable
+ dd $1 bitmask: SCCR1.SCENBO \ Backoff Slot Counter enable
+$dc constant SCCR0 \ Symbol Counter Control Registe
+ $80 constant SCCR0_SCRES \ Symbol Counter Synchronization
+ dc $80 bitmask: SCCR0.SCRES \ Symbol Counter Synchronization
+ $40 constant SCCR0_SCMBTS \ Manual Beacon Timestamp
+ dc $40 bitmask: SCCR0.SCMBTS \ Manual Beacon Timestamp
+ $20 constant SCCR0_SCEN \ Symbol Counter enable
+ dc $20 bitmask: SCCR0.SCEN \ Symbol Counter enable
+ $10 constant SCCR0_SCCKSEL \ Symbol Counter Clock Source se
+ dc $10 bitmask: SCCR0.SCCKSEL \ Symbol Counter Clock Source se
+ $8 constant SCCR0_SCTSE \ Symbol Counter Automatic Times
+ dc $8 bitmask: SCCR0.SCTSE \ Symbol Counter Automatic Times
+ $7 constant SCCR0_SCCMP \ Symbol Counter Compare Unit 3
+ dc $7 bitmask: SCCR0.SCCMP \ Symbol Counter Compare Unit 3
+$db constant SCCSR \ Symbol Counter Compare Source
+ $c0 constant SCCSR_Res \ Reserved Bit
+ db $c0 bitmask: SCCSR.Res \ Reserved Bit
+ $30 constant SCCSR_SCCS3 \ Symbol Counter Compare Source
+ db $30 bitmask: SCCSR.SCCS3 \ Symbol Counter Compare Source
+ $c constant SCCSR_SCCS2 \ Symbol Counter Compare Source
+ db $c bitmask: SCCSR.SCCS2 \ Symbol Counter Compare Source
+ $3 constant SCCSR_SCCS1 \ Symbol Counter Compare Source
+ db $3 bitmask: SCCSR.SCCS1 \ Symbol Counter Compare Source
+$da constant SCRSTRHH \ Symbol Counter Received Frame
+ $ff constant SCRSTRHH_SCRSTRHH \ Symbol Counter Received Frame
+ da $ff bitmask: SCRSTRHH.SCRSTRHH \ Symbol Counter Received Frame
+$d9 constant SCRSTRHL \ Symbol Counter Received Frame
+ $ff constant SCRSTRHL_SCRSTRHL \ Symbol Counter Received Frame
+ d9 $ff bitmask: SCRSTRHL.SCRSTRHL \ Symbol Counter Received Frame
+$d8 constant SCRSTRLH \ Symbol Counter Received Frame
+ $ff constant SCRSTRLH_SCRSTRLH \ Symbol Counter Received Frame
+ d8 $ff bitmask: SCRSTRLH.SCRSTRLH \ Symbol Counter Received Frame
+$d7 constant SCRSTRLL \ Symbol Counter Received Frame
+ $ff constant SCRSTRLL_SCRSTRLL \ Symbol Counter Received Frame
+ d7 $ff bitmask: SCRSTRLL.SCRSTRLL \ Symbol Counter Received Frame
+\ EEPROM
+$41 constant EEAR \ EEPROM Address Register Bytes
+$40 constant EEDR \ EEPROM Data Register
+$3f constant EECR \ EEPROM Control Register
+ $c0 constant EECR_Res \ Reserved
+ 3f $c0 bitmask: EECR.Res \ Reserved
+ $30 constant EECR_EEPM \ EEPROM Programming Mode
+ 3f $30 bitmask: EECR.EEPM \ EEPROM Programming Mode
+ $8 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
+ 3f $8 bitmask: EECR.EERIE \ EEPROM Ready Interrupt Enable
+ $4 constant EECR_EEMPE \ EEPROM Master Write Enable
+ 3f $4 bitmask: EECR.EEMPE \ EEPROM Master Write Enable
+ $2 constant EECR_EEPE \ EEPROM Programming Enable
+ 3f $2 bitmask: EECR.EEPE \ EEPROM Programming Enable
+ $1 constant EECR_EERE \ EEPROM Read Enable
+ 3f $1 bitmask: EECR.EERE \ EEPROM Read Enable
+\ JTAG
+$51 constant OCDR \ On-Chip Debug Register
+ $ff constant OCDR_OCDR \ On-Chip Debug Register Data
+ 51 $ff bitmask: OCDR.OCDR \ On-Chip Debug Register Data
+$55 constant MCUCR \ MCU Control Register
+ $80 constant MCUCR_JTD \ JTAG Interface Disable
+ 55 $80 bitmask: MCUCR.JTD \ JTAG Interface Disable
+$54 constant MCUSR \ MCU Status Register
+ $10 constant MCUSR_JTRF \ JTAG Reset Flag
+ 54 $10 bitmask: MCUSR.JTRF \ JTAG Reset Flag
+\ EXTERNAL_INTERRUPT
+$69 constant EICRA \ External Interrupt Control Reg
+ $c0 constant EICRA_ISC3 \ External Interrupt 3 Sense Con
+ 69 $c0 bitmask: EICRA.ISC3 \ External Interrupt 3 Sense Con
+ $30 constant EICRA_ISC2 \ External Interrupt 2 Sense Con
+ 69 $30 bitmask: EICRA.ISC2 \ External Interrupt 2 Sense Con
+ $c constant EICRA_ISC1 \ External Interrupt 1 Sense Con
+ 69 $c bitmask: EICRA.ISC1 \ External Interrupt 1 Sense Con
+ $3 constant EICRA_ISC0 \ External Interrupt 0 Sense Con
+ 69 $3 bitmask: EICRA.ISC0 \ External Interrupt 0 Sense Con
+$6a constant EICRB \ External Interrupt Control Reg
+ $c0 constant EICRB_ISC7 \ External Interrupt 7 Sense Con
+ 6a $c0 bitmask: EICRB.ISC7 \ External Interrupt 7 Sense Con
+ $30 constant EICRB_ISC6 \ External Interrupt 6 Sense Con
+ 6a $30 bitmask: EICRB.ISC6 \ External Interrupt 6 Sense Con
+ $c constant EICRB_ISC5 \ External Interrupt 5 Sense Con
+ 6a $c bitmask: EICRB.ISC5 \ External Interrupt 5 Sense Con
+ $3 constant EICRB_ISC4 \ External Interrupt 4 Sense Con
+ 6a $3 bitmask: EICRB.ISC4 \ External Interrupt 4 Sense Con
+$3d constant EIMSK \ External Interrupt Mask Regist
+ $ff constant EIMSK_INT \ External Interrupt Request Ena
+ 3d $ff bitmask: EIMSK.INT \ External Interrupt Request Ena
+$3c constant EIFR \ External Interrupt Flag Regist
+ $ff constant EIFR_INTF \ External Interrupt Flag
+ 3c $ff bitmask: EIFR.INTF \ External Interrupt Flag
+$6d constant PCMSK2 \ Pin Change Mask Register 2
+ $ff constant PCMSK2_PCINT \ Pin Change Enable Mask
+ 6d $ff bitmask: PCMSK2.PCINT \ Pin Change Enable Mask
+$6c constant PCMSK1 \ Pin Change Mask Register 1
+ $ff constant PCMSK1_PCINT \ Pin Change Enable Mask
+ 6c $ff bitmask: PCMSK1.PCINT \ Pin Change Enable Mask
+$6b constant PCMSK0 \ Pin Change Mask Register 0
+$3b constant PCIFR \ Pin Change Interrupt Flag Regi
+ $f8 constant PCIFR_Res \ Reserved Bit
+ 3b $f8 bitmask: PCIFR.Res \ Reserved Bit
+ $7 constant PCIFR_PCIF \ Pin Change Interrupt Flags
+ 3b $7 bitmask: PCIFR.PCIF \ Pin Change Interrupt Flags
+$68 constant PCICR \ Pin Change Interrupt Control R
+ $f8 constant PCICR_Res \ Reserved Bit
+ 68 $f8 bitmask: PCICR.Res \ Reserved Bit
+ $7 constant PCICR_PCIE \ Pin Change Interrupt Enables
+ 68 $7 bitmask: PCICR.PCIE \ Pin Change Interrupt Enables
+\ AD_CONVERTER
+$7c constant ADMUX \ The ADC Multiplexer Selection
+ $c0 constant ADMUX_REFS \ Reference Selection Bits
+ 7c $c0 bitmask: ADMUX.REFS \ Reference Selection Bits
+ $20 constant ADMUX_ADLAR \ ADC Left Adjust Result
+ 7c $20 bitmask: ADMUX.ADLAR \ ADC Left Adjust Result
+ $1f constant ADMUX_MUX \ Analog Channel and Gain Select
+ 7c $1f bitmask: ADMUX.MUX \ Analog Channel and Gain Select
+$78 constant ADC \ ADC Data Register Bytes
+$7a constant ADCSRA \ The ADC Control and Status Reg
+ $80 constant ADCSRA_ADEN \ ADC Enable
+ 7a $80 bitmask: ADCSRA.ADEN \ ADC Enable
+ $40 constant ADCSRA_ADSC \ ADC Start Conversion
+ 7a $40 bitmask: ADCSRA.ADSC \ ADC Start Conversion
+ $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
+ 7a $20 bitmask: ADCSRA.ADATE \ ADC Auto Trigger Enable
+ $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
+ 7a $10 bitmask: ADCSRA.ADIF \ ADC Interrupt Flag
+ $8 constant ADCSRA_ADIE \ ADC Interrupt Enable
+ 7a $8 bitmask: ADCSRA.ADIE \ ADC Interrupt Enable
+ $7 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
+ 7a $7 bitmask: ADCSRA.ADPS \ ADC Prescaler Select Bits
+$7b constant ADCSRB \ The ADC Control and Status Reg
+ $80 constant ADCSRB_AVDDOK \ AVDD Supply Voltage OK
+ 7b $80 bitmask: ADCSRB.AVDDOK \ AVDD Supply Voltage OK
+ $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer
+ 7b $40 bitmask: ADCSRB.ACME \ Analog Comparator Multiplexer
+ $20 constant ADCSRB_REFOK \ Reference Voltage OK
+ 7b $20 bitmask: ADCSRB.REFOK \ Reference Voltage OK
+ $10 constant ADCSRB_ACCH \ Analog Channel Change
+ 7b $10 bitmask: ADCSRB.ACCH \ Analog Channel Change
+ $8 constant ADCSRB_MUX5 \ Analog Channel and Gain Select
+ 7b $8 bitmask: ADCSRB.MUX5 \ Analog Channel and Gain Select
+ $7 constant ADCSRB_ADTS \ ADC Auto Trigger Source
+ 7b $7 bitmask: ADCSRB.ADTS \ ADC Auto Trigger Source
+$77 constant ADCSRC \ The ADC Control and Status Reg
+ $c0 constant ADCSRC_ADTHT \ ADC Track-and-Hold Time
+ 77 $c0 bitmask: ADCSRC.ADTHT \ ADC Track-and-Hold Time
+ $20 constant ADCSRC_Res0 \ Reserved
+ 77 $20 bitmask: ADCSRC.Res0 \ Reserved
+ $1f constant ADCSRC_ADSUT \ ADC Start-up Time
+ 77 $1f bitmask: ADCSRC.ADSUT \ ADC Start-up Time
+$7d constant DIDR2 \ Digital Input Disable Register
+ $80 constant DIDR2_ADC15D \ Reserved Bits
+ 7d $80 bitmask: DIDR2.ADC15D \ Reserved Bits
+ $40 constant DIDR2_ADC14D \ Reserved Bits
+ 7d $40 bitmask: DIDR2.ADC14D \ Reserved Bits
+ $20 constant DIDR2_ADC13D \ Reserved Bits
+ 7d $20 bitmask: DIDR2.ADC13D \ Reserved Bits
+ $10 constant DIDR2_ADC12D \ Reserved Bits
+ 7d $10 bitmask: DIDR2.ADC12D \ Reserved Bits
+ $8 constant DIDR2_ADC11D \ Reserved Bits
+ 7d $8 bitmask: DIDR2.ADC11D \ Reserved Bits
+ $4 constant DIDR2_ADC10D \ Reserved Bits
+ 7d $4 bitmask: DIDR2.ADC10D \ Reserved Bits
+ $2 constant DIDR2_ADC9D \ Reserved Bits
+ 7d $2 bitmask: DIDR2.ADC9D \ Reserved Bits
+ $1 constant DIDR2_ADC8D \ Reserved Bits
+ 7d $1 bitmask: DIDR2.ADC8D \ Reserved Bits
+$7e constant DIDR0 \ Digital Input Disable Register
+ $80 constant DIDR0_ADC7D \ Disable ADC7:0 Digital Input
+ 7e $80 bitmask: DIDR0.ADC7D \ Disable ADC7:0 Digital Input
+ $40 constant DIDR0_ADC6D \ Disable ADC7:0 Digital Input
+ 7e $40 bitmask: DIDR0.ADC6D \ Disable ADC7:0 Digital Input
+ $20 constant DIDR0_ADC5D \ Disable ADC7:0 Digital Input
+ 7e $20 bitmask: DIDR0.ADC5D \ Disable ADC7:0 Digital Input
+ $10 constant DIDR0_ADC4D \ Disable ADC7:0 Digital Input
+ 7e $10 bitmask: DIDR0.ADC4D \ Disable ADC7:0 Digital Input
+ $8 constant DIDR0_ADC3D \ Disable ADC7:0 Digital Input
+ 7e $8 bitmask: DIDR0.ADC3D \ Disable ADC7:0 Digital Input
+ $4 constant DIDR0_ADC2D \ Disable ADC7:0 Digital Input
+ 7e $4 bitmask: DIDR0.ADC2D \ Disable ADC7:0 Digital Input
+ $2 constant DIDR0_ADC1D \ Disable ADC7:0 Digital Input
+ 7e $2 bitmask: DIDR0.ADC1D \ Disable ADC7:0 Digital Input
+ $1 constant DIDR0_ADC0D \ Disable ADC7:0 Digital Input
+ 7e $1 bitmask: DIDR0.ADC0D \ Disable ADC7:0 Digital Input
+\ BOOT_LOAD
+$57 constant SPMCSR \ Store Program Memory Control R
+ $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
+ 57 $80 bitmask: SPMCSR.SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
+ 57 $40 bitmask: SPMCSR.RWWSB \ Read While Write Section Busy
+ $20 constant SPMCSR_SIGRD \ Signature Row Read
+ 57 $20 bitmask: SPMCSR.SIGRD \ Signature Row Read
+ $10 constant SPMCSR_RWWSRE \ Read While Write Section Read
+ 57 $10 bitmask: SPMCSR.RWWSRE \ Read While Write Section Read
+ $8 constant SPMCSR_BLBSET \ Boot Lock Bit Set
+ 57 $8 bitmask: SPMCSR.BLBSET \ Boot Lock Bit Set
+ $4 constant SPMCSR_PGWRT \ Page Write
+ 57 $4 bitmask: SPMCSR.PGWRT \ Page Write
+ $2 constant SPMCSR_PGERS \ Page Erase
+ 57 $2 bitmask: SPMCSR.PGERS \ Page Erase
+ $1 constant SPMCSR_SPMEN \ Store Program Memory Enable
+ 57 $1 bitmask: SPMCSR.SPMEN \ Store Program Memory Enable
+\ CPU
+$5f constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ 5f $80 bitmask: SREG.I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ 5f $40 bitmask: SREG.T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ 5f $20 bitmask: SREG.H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ 5f $10 bitmask: SREG.S \ Sign Bit
+ $8 constant SREG_V \ Two's Complement Overflow Flag
+ 5f $8 bitmask: SREG.V \ Two's Complement Overflow Flag
+ $4 constant SREG_N \ Negative Flag
+ 5f $4 bitmask: SREG.N \ Negative Flag
+ $2 constant SREG_Z \ Zero Flag
+ 5f $2 bitmask: SREG.Z \ Zero Flag
+ $1 constant SREG_C \ Carry Flag
+ 5f $1 bitmask: SREG.C \ Carry Flag
+$5d constant SP \ Stack Pointer
+$55 constant MCUCR \ MCU Control Register
+ $80 constant MCUCR_JTD \ JTAG Interface Disable
+ 55 $80 bitmask: MCUCR.JTD \ JTAG Interface Disable
+ $60 constant MCUCR_Res \ Reserved
+ 55 $60 bitmask: MCUCR.Res \ Reserved
+ $10 constant MCUCR_PUD \ Pull-up Disable
+ 55 $10 bitmask: MCUCR.PUD \ Pull-up Disable
+ $c constant MCUCR_Res \ Reserved
+ 55 $c bitmask: MCUCR.Res \ Reserved
+ $2 constant MCUCR_IVSEL \ Interrupt Vector Select
+ 55 $2 bitmask: MCUCR.IVSEL \ Interrupt Vector Select
+ $1 constant MCUCR_IVCE \ Interrupt Vector Change Enable
+ 55 $1 bitmask: MCUCR.IVCE \ Interrupt Vector Change Enable
+$54 constant MCUSR \ MCU Status Register
+ $e0 constant MCUSR_Res \ Reserved
+ 54 $e0 bitmask: MCUSR.Res \ Reserved
+ $10 constant MCUSR_JTRF \ JTAG Reset Flag
+ 54 $10 bitmask: MCUSR.JTRF \ JTAG Reset Flag
+ $8 constant MCUSR_WDRF \ Watchdog Reset Flag
+ 54 $8 bitmask: MCUSR.WDRF \ Watchdog Reset Flag
+ $4 constant MCUSR_BORF \ Brown-out Reset Flag
+ 54 $4 bitmask: MCUSR.BORF \ Brown-out Reset Flag
+ $2 constant MCUSR_EXTRF \ External Reset Flag
+ 54 $2 bitmask: MCUSR.EXTRF \ External Reset Flag
+ $1 constant MCUSR_PORF \ Power-on Reset Flag
+ 54 $1 bitmask: MCUSR.PORF \ Power-on Reset Flag
+$66 constant OSCCAL \ Oscillator Calibration Value
+ $ff constant OSCCAL_CAL \ Oscillator Calibration Tuning
+ 66 $ff bitmask: OSCCAL.CAL \ Oscillator Calibration Tuning
+$61 constant CLKPR \ Clock Prescale Register
+ $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable
+ 61 $80 bitmask: CLKPR.CLKPCE \ Clock Prescaler Change Enable
+ $70 constant CLKPR_Res \ Reserved
+ 61 $70 bitmask: CLKPR.Res \ Reserved
+ $f constant CLKPR_CLKPS \ Clock Prescaler Select Bits
+ 61 $f bitmask: CLKPR.CLKPS \ Clock Prescaler Select Bits
+$53 constant SMCR \ Sleep Mode Control Register
+ $f0 constant SMCR_Res \ Reserved
+ 53 $f0 bitmask: SMCR.Res \ Reserved
+ $e constant SMCR_SM \ Sleep Mode Select bits
+ 53 $e bitmask: SMCR.SM \ Sleep Mode Select bits
+ $1 constant SMCR_SE \ Sleep Enable
+ 53 $1 bitmask: SMCR.SE \ Sleep Enable
+$5b constant RAMPZ \ Extended Z-pointer Register fo
+ $fe constant RAMPZ_Res \ Reserved
+ 5b $fe bitmask: RAMPZ.Res \ Reserved
+ $1 constant RAMPZ_RAMPZ0 \ Extended Z-Pointer Value
+ 5b $1 bitmask: RAMPZ.RAMPZ0 \ Extended Z-Pointer Value
+$4b constant GPIOR2 \ General Purpose I/O Register 2
+ $ff constant GPIOR2_GPIOR \ General Purpose I/O Register 2
+ 4b $ff bitmask: GPIOR2.GPIOR \ General Purpose I/O Register 2
+$4a constant GPIOR1 \ General Purpose IO Register 1
+ $ff constant GPIOR1_GPIOR \ General Purpose I/O Register 1
+ 4a $ff bitmask: GPIOR1.GPIOR \ General Purpose I/O Register 1
+$3e constant GPIOR0 \ General Purpose IO Register 0
+ $80 constant GPIOR0_GPIOR07 \ General Purpose I/O Register 0
+ 3e $80 bitmask: GPIOR0.GPIOR07 \ General Purpose I/O Register 0
+ $40 constant GPIOR0_GPIOR06 \ General Purpose I/O Register 0
+ 3e $40 bitmask: GPIOR0.GPIOR06 \ General Purpose I/O Register 0
+ $20 constant GPIOR0_GPIOR05 \ General Purpose I/O Register 0
+ 3e $20 bitmask: GPIOR0.GPIOR05 \ General Purpose I/O Register 0
+ $10 constant GPIOR0_GPIOR04 \ General Purpose I/O Register 0
+ 3e $10 bitmask: GPIOR0.GPIOR04 \ General Purpose I/O Register 0
+ $8 constant GPIOR0_GPIOR03 \ General Purpose I/O Register 0
+ 3e $8 bitmask: GPIOR0.GPIOR03 \ General Purpose I/O Register 0
+ $4 constant GPIOR0_GPIOR02 \ General Purpose I/O Register 0
+ 3e $4 bitmask: GPIOR0.GPIOR02 \ General Purpose I/O Register 0
+ $2 constant GPIOR0_GPIOR01 \ General Purpose I/O Register 0
+ 3e $2 bitmask: GPIOR0.GPIOR01 \ General Purpose I/O Register 0
+ $1 constant GPIOR0_GPIOR00 \ General Purpose I/O Register 0
+ 3e $1 bitmask: GPIOR0.GPIOR00 \ General Purpose I/O Register 0
+$63 constant PRR2 \ Power Reduction Register 2
+ $f0 constant PRR2_Res \ Reserved Bit
+ 63 $f0 bitmask: PRR2.Res \ Reserved Bit
+ $f constant PRR2_PRRAM \ Power Reduction SRAMs
+ 63 $f bitmask: PRR2.PRRAM \ Power Reduction SRAMs
+$65 constant PRR1 \ Power Reduction Register 1
+ $80 constant PRR1_Res \ Reserved Bit
+ 65 $80 bitmask: PRR1.Res \ Reserved Bit
+ $40 constant PRR1_PRTRX24 \ Power Reduction Transceiver
+ 65 $40 bitmask: PRR1.PRTRX24 \ Power Reduction Transceiver
+ $20 constant PRR1_PRTIM5 \ Power Reduction Timer/Counter5
+ 65 $20 bitmask: PRR1.PRTIM5 \ Power Reduction Timer/Counter5
+ $10 constant PRR1_PRTIM4 \ Power Reduction Timer/Counter4
+ 65 $10 bitmask: PRR1.PRTIM4 \ Power Reduction Timer/Counter4
+ $8 constant PRR1_PRTIM3 \ Power Reduction Timer/Counter3
+ 65 $8 bitmask: PRR1.PRTIM3 \ Power Reduction Timer/Counter3
+ $1 constant PRR1_PRUSART1 \ Power Reduction USART1
+ 65 $1 bitmask: PRR1.PRUSART1 \ Power Reduction USART1
+$64 constant PRR0 \ Power Reduction Register0
+ $80 constant PRR0_PRTWI \ Power Reduction TWI
+ 64 $80 bitmask: PRR0.PRTWI \ Power Reduction TWI
+ $40 constant PRR0_PRTIM2 \ Power Reduction Timer/Counter2
+ 64 $40 bitmask: PRR0.PRTIM2 \ Power Reduction Timer/Counter2
+ $20 constant PRR0_PRTIM0 \ Power Reduction Timer/Counter0
+ 64 $20 bitmask: PRR0.PRTIM0 \ Power Reduction Timer/Counter0
+ $10 constant PRR0_PRPGA \ Power Reduction PGA
+ 64 $10 bitmask: PRR0.PRPGA \ Power Reduction PGA
+ $8 constant PRR0_PRTIM1 \ Power Reduction Timer/Counter1
+ 64 $8 bitmask: PRR0.PRTIM1 \ Power Reduction Timer/Counter1
+ $4 constant PRR0_PRSPI \ Power Reduction Serial Periphe
+ 64 $4 bitmask: PRR0.PRSPI \ Power Reduction Serial Periphe
+ $2 constant PRR0_PRUSART0 \ Power Reduction USART
+ 64 $2 bitmask: PRR0.PRUSART0 \ Power Reduction USART
+ $1 constant PRR0_PRADC \ Power Reduction ADC
+ 64 $1 bitmask: PRR0.PRADC \ Power Reduction ADC
+\ FLASH
+$75 constant NEMCR \ Flash Extended-Mode Control-Re
+ $40 constant NEMCR_ENEAM \ Enable Extended Address Mode f
+ 75 $40 bitmask: NEMCR.ENEAM \ Enable Extended Address Mode f
+ $30 constant NEMCR_AEAM \ Address for Extended Address M
+ 75 $30 bitmask: NEMCR.AEAM \ Address for Extended Address M
+$67 constant BGCR \ Reference Voltage Calibration
+ $80 constant BGCR_Res \ Reserved Bit
+ 67 $80 bitmask: BGCR.Res \ Reserved Bit
+ $78 constant BGCR_BGCAL_FINE \ Fine Calibration Bits
+ 67 $78 bitmask: BGCR.BGCAL_FINE \ Fine Calibration Bits
+ $7 constant BGCR_BGCAL \ Coarse Calibration Bits
+ 67 $7 bitmask: BGCR.BGCAL \ Coarse Calibration Bits
+\ PWRCTRL
+$139 constant TRXPR \ Transceiver Pin Register
+ $f0 constant TRXPR_Res \ Reserved
+ 139 $f0 bitmask: TRXPR.Res \ Reserved
+ $2 constant TRXPR_SLPTR \ Multi-purpose Transceiver Cont
+ 139 $2 bitmask: TRXPR.SLPTR \ Multi-purpose Transceiver Cont
+ $1 constant TRXPR_TRXRST \ Force Transceiver Reset
+ 139 $1 bitmask: TRXPR.TRXRST \ Force Transceiver Reset
+$135 constant DRTRAM0 \ Data Retention Configuration R
+ $c0 constant DRTRAM0_Res \ Reserved
+ 135 $c0 bitmask: DRTRAM0.Res \ Reserved
+ $20 constant DRTRAM0_DRTSWOK \ DRT Switch OK
+ 135 $20 bitmask: DRTRAM0.DRTSWOK \ DRT Switch OK
+ $10 constant DRTRAM0_ENDRT \ Enable SRAM Data Retention
+ 135 $10 bitmask: DRTRAM0.ENDRT \ Enable SRAM Data Retention
+$134 constant DRTRAM1 \ Data Retention Configuration R
+ $c0 constant DRTRAM1_Res \ Reserved
+ 134 $c0 bitmask: DRTRAM1.Res \ Reserved
+ $20 constant DRTRAM1_DRTSWOK \ DRT Switch OK
+ 134 $20 bitmask: DRTRAM1.DRTSWOK \ DRT Switch OK
+ $10 constant DRTRAM1_ENDRT \ Enable SRAM Data Retention
+ 134 $10 bitmask: DRTRAM1.ENDRT \ Enable SRAM Data Retention
+$133 constant DRTRAM2 \ Data Retention Configuration R
+ $40 constant DRTRAM2_Res \ Reserved Bit
+ 133 $40 bitmask: DRTRAM2.Res \ Reserved Bit
+ $20 constant DRTRAM2_DRTSWOK \ DRT Switch OK
+ 133 $20 bitmask: DRTRAM2.DRTSWOK \ DRT Switch OK
+ $10 constant DRTRAM2_ENDRT \ Enable SRAM Data Retention
+ 133 $10 bitmask: DRTRAM2.ENDRT \ Enable SRAM Data Retention
+$132 constant DRTRAM3 \ Data Retention Configuration R
+ $c0 constant DRTRAM3_Res \ Reserved
+ 132 $c0 bitmask: DRTRAM3.Res \ Reserved
+ $20 constant DRTRAM3_DRTSWOK \ DRT Switch OK
+ 132 $20 bitmask: DRTRAM3.DRTSWOK \ DRT Switch OK
+ $10 constant DRTRAM3_ENDRT \ Enable SRAM Data Retention
+ 132 $10 bitmask: DRTRAM3.ENDRT \ Enable SRAM Data Retention
+$130 constant LLDRL \ Low Leakage Voltage Regulator
+ $f0 constant LLDRL_Res \ Reserved
+ 130 $f0 bitmask: LLDRL.Res \ Reserved
+ $f constant LLDRL_LLDRL \ Low-Byte Data Register Bits
+ 130 $f bitmask: LLDRL.LLDRL \ Low-Byte Data Register Bits
+$131 constant LLDRH \ Low Leakage Voltage Regulator
+ $e0 constant LLDRH_Res \ Reserved
+ 131 $e0 bitmask: LLDRH.Res \ Reserved
+ $1f constant LLDRH_LLDRH \ High-Byte Data Register Bits
+ 131 $1f bitmask: LLDRH.LLDRH \ High-Byte Data Register Bits
+$12f constant LLCR \ Low Leakage Voltage Regulator
+ $c0 constant LLCR_Res \ Reserved Bit
+ 12f $c0 bitmask: LLCR.Res \ Reserved Bit
+ $20 constant LLCR_LLDONE \ Calibration Done
+ 12f $20 bitmask: LLCR.LLDONE \ Calibration Done
+ $10 constant LLCR_LLCOMP \ Comparator Output
+ 12f $10 bitmask: LLCR.LLCOMP \ Comparator Output
+ $8 constant LLCR_LLCAL \ Calibration Active
+ 12f $8 bitmask: LLCR.LLCAL \ Calibration Active
+ $4 constant LLCR_LLTCO \ Temperature Coefficient of Cur
+ 12f $4 bitmask: LLCR.LLTCO \ Temperature Coefficient of Cur
+ $2 constant LLCR_LLSHORT \ Short Lower Calibration Circui
+ 12f $2 bitmask: LLCR.LLSHORT \ Short Lower Calibration Circui
+ $1 constant LLCR_LLENCAL \ Enable Automatic Calibration
+ 12f $1 bitmask: LLCR.LLENCAL \ Enable Automatic Calibration
+$136 constant DPDS0 \ Port Driver Strength Register
+ $c0 constant DPDS0_PFDRV \ Driver Strength Port F
+ 136 $c0 bitmask: DPDS0.PFDRV \ Driver Strength Port F
+ $30 constant DPDS0_PEDRV \ Driver Strength Port E
+ 136 $30 bitmask: DPDS0.PEDRV \ Driver Strength Port E
+ $c constant DPDS0_PDDRV \ Driver Strength Port D
+ 136 $c bitmask: DPDS0.PDDRV \ Driver Strength Port D
+ $3 constant DPDS0_PBDRV \ Driver Strength Port B
+ 136 $3 bitmask: DPDS0.PBDRV \ Driver Strength Port B
+$137 constant DPDS1 \ Port Driver Strength Register
+ $fc constant DPDS1_Res \ Reserved
+ 137 $fc bitmask: DPDS1.Res \ Reserved
+ $3 constant DPDS1_PGDRV \ Driver Strength Port G
+ 137 $3 bitmask: DPDS1.PGDRV \ Driver Strength Port G
+$55 constant MCUCR \ MCU Control Register
+ $10 constant MCUCR_PUD \ Pull-up Disable
+ 55 $10 bitmask: MCUCR.PUD \ Pull-up Disable
+\ USART0_SPI
+$c0 constant UCSR0A \ USART0 MSPIM Control and Statu
+ $80 constant UCSR0A_RXC0 \ USART Receive Complete
+ c0 $80 bitmask: UCSR0A.RXC0 \ USART Receive Complete
+ $40 constant UCSR0A_TXC0 \ USART Transmit Complete
+ c0 $40 bitmask: UCSR0A.TXC0 \ USART Transmit Complete
+ $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
+ c0 $20 bitmask: UCSR0A.UDRE0 \ USART Data Register Empty
+$c1 constant UCSR0B \ USART0 MSPIM Control and Statu
+ $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
+ c1 $80 bitmask: UCSR0B.RXCIE0 \ RX Complete Interrupt Enable
+ $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
+ c1 $40 bitmask: UCSR0B.TXCIE0 \ TX Complete Interrupt Enable
+ $20 constant UCSR0B_UDRIE0 \ USART Data Register Empty Inte
+ c1 $20 bitmask: UCSR0B.UDRIE0 \ USART Data Register Empty Inte
+ $10 constant UCSR0B_RXEN0 \ Receiver Enable
+ c1 $10 bitmask: UCSR0B.RXEN0 \ Receiver Enable
+ $8 constant UCSR0B_TXEN0 \ Transmitter Enable
+ c1 $8 bitmask: UCSR0B.TXEN0 \ Transmitter Enable
+$c2 constant UCSR0C \ USART0 MSPIM Control and Statu
+ $4 constant UCSR0C_UDORD0 \ Data Order
+ c2 $4 bitmask: UCSR0C.UDORD0 \ Data Order
+ $2 constant UCSR0C_UCPHA0 \ Clock Phase
+ c2 $2 bitmask: UCSR0C.UCPHA0 \ Clock Phase
+ $1 constant UCSR0C_UCPOL0 \ Clock Polarity
+ c2 $1 bitmask: UCSR0C.UCPOL0 \ Clock Polarity
+\ USART1_SPI
+$c8 constant UCSR1A \ USART1 MSPIM Control and Statu
+ $80 constant UCSR1A_RXC1 \ USART Receive Complete
+ c8 $80 bitmask: UCSR1A.RXC1 \ USART Receive Complete
+ $40 constant UCSR1A_TXC1 \ USART Transmit Complete
+ c8 $40 bitmask: UCSR1A.TXC1 \ USART Transmit Complete
+ $20 constant UCSR1A_UDRE1 \ USART Data Register Empty
+ c8 $20 bitmask: UCSR1A.UDRE1 \ USART Data Register Empty
+$c9 constant UCSR1B \ USART1 MSPIM Control and Statu
+ $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable
+ c9 $80 bitmask: UCSR1B.RXCIE1 \ RX Complete Interrupt Enable
+ $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable
+ c9 $40 bitmask: UCSR1B.TXCIE1 \ TX Complete Interrupt Enable
+ $20 constant UCSR1B_UDRIE1 \ USART Data Register Empty Inte
+ c9 $20 bitmask: UCSR1B.UDRIE1 \ USART Data Register Empty Inte
+ $10 constant UCSR1B_RXEN1 \ Receiver Enable
+ c9 $10 bitmask: UCSR1B.RXEN1 \ Receiver Enable
+ $8 constant UCSR1B_TXEN1 \ Transmitter Enable
+ c9 $8 bitmask: UCSR1B.TXEN1 \ Transmitter Enable
+$ca constant UCSR1C \ USART1 MSPIM Control and Statu
+ $4 constant UCSR1C_UDORD1 \ Data Order
+ ca $4 bitmask: UCSR1C.UDORD1 \ Data Order
+ $2 constant UCSR1C_UCPHA1 \ Clock Phase
+ ca $2 bitmask: UCSR1C.UCPHA1 \ Clock Phase
+ $1 constant UCSR1C_UCPOL1 \ Clock Polarity
+ ca $1 bitmask: UCSR1C.UCPOL1 \ Clock Polarity
diff --git a/amforth-6.5/avr8/devices/atmega128rfr2/device.py b/amforth-6.5/avr8/devices/atmega128rfr2/device.py
new file mode 100644
index 0000000..3d65d6c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega128rfr2/device.py
@@ -0,0 +1,1103 @@
+# Generated Automatically
+
+# Partname ATmega128RFR2
+
+MCUREGS = {
+# Interrupt Vectors
+ 'INT0Addr' : '#2', # External Interrupt Request 0
+ 'INT1Addr' : '#4', # External Interrupt Request 1
+ 'INT2Addr' : '#6', # External Interrupt Request 2
+ 'INT3Addr' : '#8', # External Interrupt Request 3
+ 'INT4Addr' : '#10', # External Interrupt Request 4
+ 'INT5Addr' : '#12', # External Interrupt Request 5
+ 'INT6Addr' : '#14', # External Interrupt Request 6
+ 'INT7Addr' : '#16', # External Interrupt Request 7
+ 'PCINT0Addr' : '#18', # Pin Change Interrupt Request 0
+ 'PCINT1Addr' : '#20', # Pin Change Interrupt Request 1
+ 'PCINT2Addr' : '#22', # Pin Change Interrupt Request 2
+ 'WDTAddr' : '#24', # Watchdog Time-out Interrupt
+ 'TIMER2_COMPAAddr' : '#26', # Timer/Counter2 Compare Match A
+ 'TIMER2_COMPBAddr' : '#28', # Timer/Counter2 Compare Match B
+ 'TIMER2_OVFAddr' : '#30', # Timer/Counter2 Overflow
+ 'TIMER1_CAPTAddr' : '#32', # Timer/Counter1 Capture Event
+ 'TIMER1_COMPAAddr' : '#34', # Timer/Counter1 Compare Match A
+ 'TIMER1_COMPBAddr' : '#36', # Timer/Counter1 Compare Match B
+ 'TIMER1_COMPCAddr' : '#38', # Timer/Counter1 Compare Match C
+ 'TIMER1_OVFAddr' : '#40', # Timer/Counter1 Overflow
+ 'TIMER0_COMPAAddr' : '#42', # Timer/Counter0 Compare Match A
+ 'TIMER0_COMPBAddr' : '#44', # Timer/Counter0 Compare Match B
+ 'TIMER0_OVFAddr' : '#46', # Timer/Counter0 Overflow
+ 'SPI_STCAddr' : '#48', # SPI Serial Transfer Complete
+ 'USART0_RXAddr' : '#50', # USART0, Rx Complete
+ 'USART0_UDREAddr' : '#52', # USART0 Data register Empty
+ 'USART0_TXAddr' : '#54', # USART0, Tx Complete
+ 'ANALOG_COMPAddr' : '#56', # Analog Comparator
+ 'ADCAddr' : '#58', # ADC Conversion Complete
+ 'EE_READYAddr' : '#60', # EEPROM Ready
+ 'TIMER3_CAPTAddr' : '#62', # Timer/Counter3 Capture Event
+ 'TIMER3_COMPAAddr' : '#64', # Timer/Counter3 Compare Match A
+ 'TIMER3_COMPBAddr' : '#66', # Timer/Counter3 Compare Match B
+ 'TIMER3_COMPCAddr' : '#68', # Timer/Counter3 Compare Match C
+ 'TIMER3_OVFAddr' : '#70', # Timer/Counter3 Overflow
+ 'USART1_RXAddr' : '#72', # USART1, Rx Complete
+ 'USART1_UDREAddr' : '#74', # USART1 Data register Empty
+ 'USART1_TXAddr' : '#76', # USART1, Tx Complete
+ 'TWIAddr' : '#78', # 2-wire Serial Interface
+ 'SPM_READYAddr' : '#80', # Store Program Memory Read
+ 'TIMER4_CAPTAddr' : '#82', # Timer/Counter4 Capture Event
+ 'TIMER4_COMPAAddr' : '#84', # Timer/Counter4 Compare Match A
+ 'TIMER4_COMPBAddr' : '#86', # Timer/Counter4 Compare Match B
+ 'TIMER4_COMPCAddr' : '#88', # Timer/Counter4 Compare Match C
+ 'TIMER4_OVFAddr' : '#90', # Timer/Counter4 Overflow
+ 'TIMER5_CAPTAddr' : '#92', # Timer/Counter5 Capture Event
+ 'TIMER5_COMPAAddr' : '#94', # Timer/Counter5 Compare Match A
+ 'TIMER5_COMPBAddr' : '#96', # Timer/Counter5 Compare Match B
+ 'TIMER5_COMPCAddr' : '#98', # Timer/Counter5 Compare Match C
+ 'TIMER5_OVFAddr' : '#100', # Timer/Counter5 Overflow
+ 'USART2_RXAddr' : '#102', # USART2, Rx Complete
+ 'USART2_UDREAddr' : '#104', # USART2 Data register Empty
+ 'USART2_TXAddr' : '#106', # USART2, Tx Complete
+ 'USART3_RXAddr' : '#108', # USART3, Rx Complete
+ 'USART3_UDREAddr' : '#110', # USART3 Data register Empty
+ 'USART3_TXAddr' : '#112', # USART3, Tx Complete
+ 'TRX24_PLL_LOCKAddr' : '#114', # TRX24 - PLL lock interrupt
+ 'TRX24_PLL_UNLOCKAddr' : '#116', # TRX24 - PLL unlock interrupt
+ 'TRX24_RX_STARTAddr' : '#118', # TRX24 - Receive start interrupt
+ 'TRX24_RX_ENDAddr' : '#120', # TRX24 - RX_END interrupt
+ 'TRX24_CCA_ED_DONEAddr' : '#122', # TRX24 - CCA/ED done interrupt
+ 'TRX24_XAH_AMIAddr' : '#124', # TRX24 - XAH - AMI
+ 'TRX24_TX_ENDAddr' : '#126', # TRX24 - TX_END interrupt
+ 'TRX24_AWAKEAddr' : '#128', # TRX24 AWAKE - tranceiver is reaching state TRX_OFF
+ 'SCNT_CMP1Addr' : '#130', # Symbol counter - compare match 1 interrupt
+ 'SCNT_CMP2Addr' : '#132', # Symbol counter - compare match 2 interrupt
+ 'SCNT_CMP3Addr' : '#134', # Symbol counter - compare match 3 interrupt
+ 'SCNT_OVFLAddr' : '#136', # Symbol counter - overflow interrupt
+ 'SCNT_BACKOFFAddr' : '#138', # Symbol counter - backoff interrupt
+ 'AES_READYAddr' : '#140', # AES engine ready interrupt
+ 'BAT_LOWAddr' : '#142', # Battery monitor indicates supply voltage below threshold
+ 'TRX24_TX_STARTAddr' : '#144', # TRX24 TX start interrupt
+ 'TRX24_AMI0Addr' : '#146', # Address match interrupt of address filter 0
+ 'TRX24_AMI1Addr' : '#148', # Address match interrupt of address filter 1
+ 'TRX24_AMI2Addr' : '#150', # Address match interrupt of address filter 2
+ 'TRX24_AMI3Addr' : '#152', # Address match interrupt of address filter 3
+
+# Module ANALOG_COMPARATOR
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
+ 'ACSR' : '$50', # Analog Comparator Control And
+ 'ACSR_ACD': '$80', # Analog Comparator Disable
+ 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
+ 'ACSR_ACO': '$20', # Analog Compare Output
+ 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
+ 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
+ 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
+ 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
+ 'DIDR1' : '$7f', # Digital Input Disable Register
+ 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
+ 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
+
+# Module USART0
+ 'UDR0' : '$c6', # USART0 I/O Data Register
+ 'UCSR0A' : '$c0', # USART0 Control and Status Regi
+ 'UCSR0A_RXC0': '$80', # USART Receive Complete
+ 'UCSR0A_TXC0': '$40', # USART Transmit Complete
+ 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
+ 'UCSR0A_FE0': '$10', # Frame Error
+ 'UCSR0A_DOR0': '$8', # Data OverRun
+ 'UCSR0A_UPE0': '$4', # USART Parity Error
+ 'UCSR0A_U2X0': '$2', # Double the USART Transmission
+ 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
+ 'UCSR0B' : '$c1', # USART0 Control and Status Regi
+ 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
+ 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
+ 'UCSR0B_UDRIE0': '$20', # USART Data Register Empty Inte
+ 'UCSR0B_RXEN0': '$10', # Receiver Enable
+ 'UCSR0B_TXEN0': '$8', # Transmitter Enable
+ 'UCSR0B_UCSZ02': '$4', # Character Size
+ 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
+ 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
+ 'UCSR0C' : '$c2', # USART0 Control and Status Regi
+ 'UCSR0C_UMSEL0': '$c0', # USART Mode Select
+ 'UCSR0C_UPM0': '$30', # Parity Mode
+ 'UCSR0C_USBS0': '$8', # Stop Bit Select
+ 'UCSR0C_UCSZ0': '$6', # Character Size
+ 'UCSR0C_UCPOL0': '$1', # Clock Polarity
+ 'UBRR0' : '$c4', # USART0 Baud Rate Register Byt
+
+# Module USART1
+ 'UDR1' : '$ce', # USART1 I/O Data Register
+ 'UCSR1A' : '$c8', # USART1 Control and Status Regi
+ 'UCSR1A_RXC1': '$80', # USART Receive Complete
+ 'UCSR1A_TXC1': '$40', # USART Transmit Complete
+ 'UCSR1A_UDRE1': '$20', # USART Data Register Empty
+ 'UCSR1A_FE1': '$10', # Frame Error
+ 'UCSR1A_DOR1': '$8', # Data OverRun
+ 'UCSR1A_UPE1': '$4', # USART Parity Error
+ 'UCSR1A_U2X1': '$2', # Double the USART Transmission
+ 'UCSR1A_MPCM1': '$1', # Multi-processor Communication
+ 'UCSR1B' : '$c9', # USART1 Control and Status Regi
+ 'UCSR1B_RXCIE1': '$80', # RX Complete Interrupt Enable
+ 'UCSR1B_TXCIE1': '$40', # TX Complete Interrupt Enable
+ 'UCSR1B_UDRIE1': '$20', # USART Data Register Empty Inte
+ 'UCSR1B_RXEN1': '$10', # Receiver Enable
+ 'UCSR1B_TXEN1': '$8', # Transmitter Enable
+ 'UCSR1B_UCSZ12': '$4', # Character Size
+ 'UCSR1B_RXB81': '$2', # Receive Data Bit 8
+ 'UCSR1B_TXB81': '$1', # Transmit Data Bit 8
+ 'UCSR1C' : '$ca', # USART1 Control and Status Regi
+ 'UCSR1C_UMSEL1': '$c0', # USART Mode Select
+ 'UCSR1C_UPM1': '$30', # Parity Mode
+ 'UCSR1C_USBS1': '$8', # Stop Bit Select
+ 'UCSR1C_UCSZ1': '$6', # Character Size
+ 'UCSR1C_UCPOL1': '$1', # Clock Polarity
+ 'UBRR1' : '$cc', # USART1 Baud Rate Register Byt
+
+# Module TWI
+ 'TWAMR' : '$bd', # TWI (Slave) Address Mask Regis
+ 'TWAMR_TWAM': '$fe', # TWI Address Mask
+ 'TWAMR_Res': '$1', # Reserved Bit
+ 'TWBR' : '$b8', # TWI Bit Rate Register
+ 'TWCR' : '$bc', # TWI Control Register
+ 'TWCR_TWINT': '$80', # TWI Interrupt Flag
+ 'TWCR_TWEA': '$40', # TWI Enable Acknowledge Bit
+ 'TWCR_TWSTA': '$20', # TWI START Condition Bit
+ 'TWCR_TWSTO': '$10', # TWI STOP Condition Bit
+ 'TWCR_TWWC': '$8', # TWI Write Collision Flag
+ 'TWCR_TWEN': '$4', # TWI Enable Bit
+ 'TWCR_Res': '$2', # Reserved Bit
+ 'TWCR_TWIE': '$1', # TWI Interrupt Enable
+ 'TWSR' : '$b9', # TWI Status Register
+ 'TWSR_TWS': '$f8', # TWI Status
+ 'TWSR_Res': '$4', # Reserved Bit
+ 'TWSR_TWPS': '$3', # TWI Prescaler Bits
+ 'TWDR' : '$bb', # TWI Data Register
+ 'TWAR' : '$ba', # TWI (Slave) Address Register
+ 'TWAR_TWA': '$fe', # TWI (Slave) Address
+ 'TWAR_TWGCE': '$1', # TWI General Call Recognition E
+
+# Module SPI
+ 'SPCR' : '$4c', # SPI Control Register
+ 'SPCR_SPIE': '$80', # SPI Interrupt Enable
+ 'SPCR_SPE': '$40', # SPI Enable
+ 'SPCR_DORD': '$20', # Data Order
+ 'SPCR_MSTR': '$10', # Master/Slave Select
+ 'SPCR_CPOL': '$8', # Clock polarity
+ 'SPCR_CPHA': '$4', # Clock Phase
+ 'SPCR_SPR': '$3', # SPI Clock Rate Select 1 and 0
+ 'SPSR' : '$4d', # SPI Status Register
+ 'SPSR_SPIF': '$80', # SPI Interrupt Flag
+ 'SPSR_WCOL': '$40', # Write Collision Flag
+ 'SPSR_Res': '$3e', # Reserved
+ 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
+ 'SPDR' : '$4e', # SPI Data Register
+
+# Module PORTA
+ 'PORTA' : '$22', # Port A Data Register
+ 'DDRA' : '$21', # Port A Data Direction Register
+ 'PINA' : '$20', # Port A Input Pins Address
+
+# Module PORTB
+ 'PORTB' : '$25', # Port B Data Register
+ 'DDRB' : '$24', # Port B Data Direction Register
+ 'PINB' : '$23', # Port B Input Pins Address
+
+# Module PORTC
+ 'PORTC' : '$28', # Port C Data Register
+ 'DDRC' : '$27', # Port C Data Direction Register
+ 'PINC' : '$26', # Port C Input Pins Address
+
+# Module PORTD
+ 'PORTD' : '$2b', # Port D Data Register
+ 'DDRD' : '$2a', # Port D Data Direction Register
+ 'PIND' : '$29', # Port D Input Pins Address
+
+# Module PORTE
+ 'PORTE' : '$2e', # Port E Data Register
+ 'DDRE' : '$2d', # Port E Data Direction Register
+ 'PINE' : '$2c', # Port E Input Pins Address
+
+# Module PORTF
+ 'PORTF' : '$31', # Port F Data Register
+ 'DDRF' : '$30', # Port F Data Direction Register
+ 'PINF' : '$2f', # Port F Input Pins Address
+
+# Module PORTG
+ 'PORTG' : '$34', # Port G Data Register
+ 'DDRG' : '$33', # Port G Data Direction Register
+ 'PING' : '$32', # Port G Input Pins Address
+
+# Module TIMER_COUNTER_0
+ 'OCR0B' : '$48', # Timer/Counter0 Output Compare
+ 'OCR0A' : '$47', # Timer/Counter0 Output Compare
+ 'TCNT0' : '$46', # Timer/Counter0 Register
+ 'TCCR0B' : '$45', # Timer/Counter0 Control Registe
+ 'TCCR0B_FOC0A': '$80', # Force Output Compare A
+ 'TCCR0B_FOC0B': '$40', # Force Output Compare B
+ 'TCCR0B_Res': '$30', # Reserved Bit
+ 'TCCR0B_WGM02': '$8', #
+ 'TCCR0B_CS0': '$7', # Clock Select
+ 'TCCR0A' : '$44', # Timer/Counter0 Control Registe
+ 'TCCR0A_COM0A': '$c0', # Compare Match Output A Mode
+ 'TCCR0A_COM0B': '$30', # Compare Match Output B Mode
+ 'TCCR0A_Res': '$c', # Reserved Bit
+ 'TCCR0A_WGM0': '$3', # Waveform Generation Mode
+ 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
+ 'TIMSK0_Res': '$f8', # Reserved
+ 'TIMSK0_OCIE0B': '$4', # Timer/Counter0 Output Compare
+ 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
+ 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
+ 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
+ 'TIFR0_Res': '$f8', # Reserved
+ 'TIFR0_OCF0B': '$4', # Timer/Counter0 Output Compare
+ 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
+ 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_Res': '$7c', # Reserved
+ 'GTCCR_PSRASY': '$2', # Prescaler Reset Timer/Counter2
+ 'GTCCR_PSRSYNC': '$1', # Prescaler Reset for Synchronou
+
+# Module TIMER_COUNTER_2
+ 'TIMSK2' : '$70', # Timer/Counter Interrupt Mask r
+ 'TIMSK2_Res': '$f8', # Reserved Bit
+ 'TIMSK2_OCIE2B': '$4', # Timer/Counter2 Output Compare
+ 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
+ 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
+ 'TIFR2' : '$37', # Timer/Counter Interrupt Flag R
+ 'TIFR2_Res': '$f8', # Reserved Bit
+ 'TIFR2_OCF2B': '$4', # Output Compare Flag 2 B
+ 'TIFR2_OCF2A': '$2', # Output Compare Flag 2 A
+ 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
+ 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
+ 'TCCR2A_COM2A': '$c0', # Compare Match Output A Mode
+ 'TCCR2A_COM2B': '$30', # Compare Match Output B Mode
+ 'TCCR2A_Res': '$c', # Reserved
+ 'TCCR2A_WGM2': '$3', # Waveform Generation Mode
+ 'TCCR2B' : '$b1', # Timer/Counter2 Control Registe
+ 'TCCR2B_FOC2A': '$80', # Force Output Compare A
+ 'TCCR2B_FOC2B': '$40', # Force Output Compare B
+ 'TCCR2B_Res': '$30', # Reserved
+ 'TCCR2B_WGM22': '$8', # Waveform Generation Mode
+ 'TCCR2B_CS2': '$7', # Clock Select
+ 'TCNT2' : '$b2', # Timer/Counter2
+ 'OCR2B' : '$b4', # Timer/Counter2 Output Compare
+ 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
+ 'ASSR' : '$b6', # Asynchronous Status Register
+ 'ASSR_EXCLKAMR': '$80', # Enable External Clock Input fo
+ 'ASSR_EXCLK': '$40', # Enable External Clock Input
+ 'ASSR_AS2': '$20', # Timer/Counter2 Asynchronous Mo
+ 'ASSR_TCN2UB': '$10', # Timer/Counter2 Update Busy
+ 'ASSR_OCR2AUB': '$8', # Timer/Counter2 Output Compare
+ 'ASSR_OCR2BUB': '$4', # Timer/Counter2 Output Compare
+ 'ASSR_TCR2AUB': '$2', # Timer/Counter2 Control Registe
+ 'ASSR_TCR2BUB': '$1', # Timer/Counter2 Control Registe
+ 'GTCCR' : '$43', # General Timer Counter Control
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSRASY': '$2', # Prescaler Reset Timer/Counter2
+
+# Module WATCHDOG
+ 'WDTCSR' : '$60', # Watchdog Timer Control Registe
+ 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
+ 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
+ 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
+ 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
+ 'WDTCSR_WDE': '$8', # Watch Dog Enable
+
+# Module TIMER_COUNTER_5
+ 'TCCR5A' : '$120', # Timer/Counter5 Control Registe
+ 'TCCR5A_COM5A': '$c0', # Compare Output Mode for Channe
+ 'TCCR5A_COM5B': '$30', # Compare Output Mode for Channe
+ 'TCCR5A_COM5C': '$c', # Compare Output Mode for Channe
+ 'TCCR5A_WGM5': '$3', # Waveform Generation Mode
+ 'TCCR5B' : '$121', # Timer/Counter5 Control Registe
+ 'TCCR5B_ICNC5': '$80', # Input Capture 5 Noise Cancelle
+ 'TCCR5B_ICES5': '$40', # Input Capture 5 Edge Select
+ 'TCCR5B_Res': '$20', # Reserved Bit
+ 'TCCR5B_WGM5': '$18', # Waveform Generation Mode
+ 'TCCR5B_CS5': '$7', # Clock Select
+ 'TCCR5C' : '$122', # Timer/Counter5 Control Registe
+ 'TCCR5C_FOC5A': '$80', # Force Output Compare for Chann
+ 'TCCR5C_FOC5B': '$40', # Force Output Compare for Chann
+ 'TCCR5C_FOC5C': '$20', # Force Output Compare for Chann
+ 'TCCR5C_Res': '$1f', # Reserved
+ 'TCNT5' : '$124', # Timer/Counter5 Bytes
+ 'OCR5A' : '$128', # Timer/Counter5 Output Compare
+ 'OCR5B' : '$12a', # Timer/Counter5 Output Compare
+ 'OCR5C' : '$12c', # Timer/Counter5 Output Compare
+ 'ICR5' : '$126', # Timer/Counter5 Input Capture R
+ 'TIMSK5' : '$73', # Timer/Counter5 Interrupt Mask
+ 'TIMSK5_Res': '$c0', # Reserved Bit
+ 'TIMSK5_ICIE5': '$20', # Timer/Counter5 Input Capture I
+ 'TIMSK5_Res': '$10', # Reserved Bit
+ 'TIMSK5_OCIE5C': '$8', # Timer/Counter5 Output Compare
+ 'TIMSK5_OCIE5B': '$4', # Timer/Counter5 Output Compare
+ 'TIMSK5_OCIE5A': '$2', # Timer/Counter5 Output Compare
+ 'TIMSK5_TOIE5': '$1', # Timer/Counter5 Overflow Interr
+ 'TIFR5' : '$3a', # Timer/Counter5 Interrupt Flag
+ 'TIFR5_Res': '$c0', # Reserved Bit
+ 'TIFR5_ICF5': '$20', # Timer/Counter5 Input Capture F
+ 'TIFR5_Res': '$10', # Reserved Bit
+ 'TIFR5_OCF5C': '$8', # Timer/Counter5 Output Compare
+ 'TIFR5_OCF5B': '$4', # Timer/Counter5 Output Compare
+ 'TIFR5_OCF5A': '$2', # Timer/Counter5 Output Compare
+ 'TIFR5_TOV5': '$1', # Timer/Counter5 Overflow Flag
+
+# Module TIMER_COUNTER_4
+ 'TCCR4A' : '$a0', # Timer/Counter4 Control Registe
+ 'TCCR4A_COM4A': '$c0', # Compare Output Mode for Channe
+ 'TCCR4A_COM4B': '$30', # Compare Output Mode for Channe
+ 'TCCR4A_COM4C': '$c', # Compare Output Mode for Channe
+ 'TCCR4A_WGM4': '$3', # Waveform Generation Mode
+ 'TCCR4B' : '$a1', # Timer/Counter4 Control Registe
+ 'TCCR4B_ICNC4': '$80', # Input Capture 4 Noise Cancelle
+ 'TCCR4B_ICES4': '$40', # Input Capture 4 Edge Select
+ 'TCCR4B_Res': '$20', # Reserved Bit
+ 'TCCR4B_WGM4': '$18', # Waveform Generation Mode
+ 'TCCR4B_CS4': '$7', # Clock Select
+ 'TCCR4C' : '$a2', # Timer/Counter4 Control Registe
+ 'TCCR4C_FOC4A': '$80', # Force Output Compare for Chann
+ 'TCCR4C_FOC4B': '$40', # Force Output Compare for Chann
+ 'TCCR4C_FOC4C': '$20', # Force Output Compare for Chann
+ 'TCCR4C_Res': '$1f', # Reserved
+ 'TCNT4' : '$a4', # Timer/Counter4 Bytes
+ 'OCR4A' : '$a8', # Timer/Counter4 Output Compare
+ 'OCR4B' : '$aa', # Timer/Counter4 Output Compare
+ 'OCR4C' : '$ac', # Timer/Counter4 Output Compare
+ 'ICR4' : '$a6', # Timer/Counter4 Input Capture R
+ 'TIMSK4' : '$72', # Timer/Counter4 Interrupt Mask
+ 'TIMSK4_Res': '$c0', # Reserved Bit
+ 'TIMSK4_ICIE4': '$20', # Timer/Counter4 Input Capture I
+ 'TIMSK4_Res': '$10', # Reserved Bit
+ 'TIMSK4_OCIE4C': '$8', # Timer/Counter4 Output Compare
+ 'TIMSK4_OCIE4B': '$4', # Timer/Counter4 Output Compare
+ 'TIMSK4_OCIE4A': '$2', # Timer/Counter4 Output Compare
+ 'TIMSK4_TOIE4': '$1', # Timer/Counter4 Overflow Interr
+ 'TIFR4' : '$39', # Timer/Counter4 Interrupt Flag
+ 'TIFR4_Res': '$c0', # Reserved Bit
+ 'TIFR4_ICF4': '$20', # Timer/Counter4 Input Capture F
+ 'TIFR4_Res': '$10', # Reserved Bit
+ 'TIFR4_OCF4C': '$8', # Timer/Counter4 Output Compare
+ 'TIFR4_OCF4B': '$4', # Timer/Counter4 Output Compare
+ 'TIFR4_OCF4A': '$2', # Timer/Counter4 Output Compare
+ 'TIFR4_TOV4': '$1', # Timer/Counter4 Overflow Flag
+
+# Module TIMER_COUNTER_3
+ 'TCCR3A' : '$90', # Timer/Counter3 Control Registe
+ 'TCCR3A_COM3A': '$c0', # Compare Output Mode for Channe
+ 'TCCR3A_COM3B': '$30', # Compare Output Mode for Channe
+ 'TCCR3A_COM3C': '$c', # Compare Output Mode for Channe
+ 'TCCR3A_WGM3': '$3', # Waveform Generation Mode
+ 'TCCR3B' : '$91', # Timer/Counter3 Control Registe
+ 'TCCR3B_ICNC3': '$80', # Input Capture 3 Noise Cancelle
+ 'TCCR3B_ICES3': '$40', # Input Capture 3 Edge Select
+ 'TCCR3B_Res': '$20', # Reserved Bit
+ 'TCCR3B_WGM3': '$18', # Waveform Generation Mode
+ 'TCCR3B_CS3': '$7', # Clock Select
+ 'TCCR3C' : '$92', # Timer/Counter3 Control Registe
+ 'TCCR3C_FOC3A': '$80', # Force Output Compare for Chann
+ 'TCCR3C_FOC3B': '$40', # Force Output Compare for Chann
+ 'TCCR3C_FOC3C': '$20', # Force Output Compare for Chann
+ 'TCCR3C_Res': '$1f', # Reserved
+ 'TCNT3' : '$94', # Timer/Counter3 Bytes
+ 'OCR3A' : '$98', # Timer/Counter3 Output Compare
+ 'OCR3B' : '$9a', # Timer/Counter3 Output Compare
+ 'OCR3C' : '$9c', # Timer/Counter3 Output Compare
+ 'ICR3' : '$96', # Timer/Counter3 Input Capture R
+ 'TIMSK3' : '$71', # Timer/Counter3 Interrupt Mask
+ 'TIMSK3_Res': '$c0', # Reserved Bit
+ 'TIMSK3_ICIE3': '$20', # Timer/Counter3 Input Capture I
+ 'TIMSK3_Res': '$10', # Reserved Bit
+ 'TIMSK3_OCIE3C': '$8', # Timer/Counter3 Output Compare
+ 'TIMSK3_OCIE3B': '$4', # Timer/Counter3 Output Compare
+ 'TIMSK3_OCIE3A': '$2', # Timer/Counter3 Output Compare
+ 'TIMSK3_TOIE3': '$1', # Timer/Counter3 Overflow Interr
+ 'TIFR3' : '$38', # Timer/Counter3 Interrupt Flag
+ 'TIFR3_Res': '$c0', # Reserved Bit
+ 'TIFR3_ICF3': '$20', # Timer/Counter3 Input Capture F
+ 'TIFR3_Res': '$10', # Reserved Bit
+ 'TIFR3_OCF3C': '$8', # Timer/Counter3 Output Compare
+ 'TIFR3_OCF3B': '$4', # Timer/Counter3 Output Compare
+ 'TIFR3_OCF3A': '$2', # Timer/Counter3 Output Compare
+ 'TIFR3_TOV3': '$1', # Timer/Counter3 Overflow Flag
+
+# Module TIMER_COUNTER_1
+ 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
+ 'TCCR1A_COM1A': '$c0', # Compare Output Mode for Channe
+ 'TCCR1A_COM1B': '$30', # Compare Output Mode for Channe
+ 'TCCR1A_COM1C': '$c', # Compare Output Mode for Channe
+ 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
+ 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
+ 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Cancelle
+ 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
+ 'TCCR1B_Res': '$20', # Reserved Bit
+ 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
+ 'TCCR1B_CS1': '$7', # Clock Select
+ 'TCCR1C' : '$82', # Timer/Counter1 Control Registe
+ 'TCCR1C_FOC1A': '$80', # Force Output Compare for Chann
+ 'TCCR1C_FOC1B': '$40', # Force Output Compare for Chann
+ 'TCCR1C_FOC1C': '$20', # Force Output Compare for Chann
+ 'TCCR1C_Res': '$1f', # Reserved
+ 'TCNT1' : '$84', # Timer/Counter1 Bytes
+ 'OCR1A' : '$88', # Timer/Counter1 Output Compare
+ 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
+ 'OCR1C' : '$8c', # Timer/Counter1 Output Compare
+ 'ICR1' : '$86', # Timer/Counter1 Input Capture R
+ 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
+ 'TIMSK1_Res': '$c0', # Reserved Bit
+ 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
+ 'TIMSK1_Res': '$10', # Reserved Bit
+ 'TIMSK1_OCIE1C': '$8', # Timer/Counter1 Output Compare
+ 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
+ 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
+ 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
+ 'TIFR1' : '$36', # Timer/Counter1 Interrupt Flag
+ 'TIFR1_Res': '$c0', # Reserved Bit
+ 'TIFR1_ICF1': '$20', # Timer/Counter1 Input Capture F
+ 'TIFR1_Res': '$10', # Reserved Bit
+ 'TIFR1_OCF1C': '$8', # Timer/Counter1 Output Compare
+ 'TIFR1_OCF1B': '$4', # Timer/Counter1 Output Compare
+ 'TIFR1_OCF1A': '$2', # Timer/Counter1 Output Compare
+ 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
+
+# Module TRX24
+ 'PARCR' : '$138', # Power Amplifier Ramp up/down C
+ 'PARCR_PALTD': '$e0', # ext. PA Ramp Down Lead Time
+ 'PARCR_PALTU': '$1c', # ext. PA Ramp Up Lead Time
+ 'PARCR_PARDFI': '$2', # Power Amplifier Ramp Down Freq
+ 'PARCR_PARUFI': '$1', # Power Amplifier Ramp Up Freque
+ 'MAFSA0L' : '$10e', # Transceiver MAC Short Address
+ 'MAFSA0L_MAFSA0L': '$ff', # MAC Short Address low Byte for
+ 'MAFSA0H' : '$10f', # Transceiver MAC Short Address
+ 'MAFSA0H_MAFSA0H': '$ff', # MAC Short Address high Byte fo
+ 'MAFPA0L' : '$110', # Transceiver Personal Area Netw
+ 'MAFPA0L_MAFPA0L': '$ff', # MAC Personal Area Network ID l
+ 'MAFPA0H' : '$111', # Transceiver Personal Area Netw
+ 'MAFPA0H_MAFPA0H': '$ff', # MAC Personal Area Network ID h
+ 'MAFSA1L' : '$112', # Transceiver MAC Short Address
+ 'MAFSA1L_MAFSA1L': '$ff', # MAC Short Address low Byte for
+ 'MAFSA1H' : '$113', # Transceiver MAC Short Address
+ 'MAFSA1H_MAFSA1H': '$ff', # MAC Short Address high Byte fo
+ 'MAFPA1L' : '$114', # Transceiver Personal Area Netw
+ 'MAFPA1L_MAFPA1L': '$ff', # MAC Personal Area Network ID l
+ 'MAFPA1H' : '$115', # Transceiver Personal Area Netw
+ 'MAFPA1H_MAFPA1H': '$ff', # MAC Personal Area Network ID h
+ 'MAFSA2L' : '$116', # Transceiver MAC Short Address
+ 'MAFSA2L_MAFSA2L': '$ff', # MAC Short Address low Byte for
+ 'MAFSA2H' : '$117', # Transceiver MAC Short Address
+ 'MAFSA2H_MAFSA2H': '$ff', # MAC Short Address high Byte fo
+ 'MAFPA2L' : '$118', # Transceiver Personal Area Netw
+ 'MAFPA2L_MAFPA2L': '$ff', # MAC Personal Area Network ID l
+ 'MAFPA2H' : '$119', # Transceiver Personal Area Netw
+ 'MAFPA2H_MAFPA2H': '$ff', # MAC Personal Area Network ID h
+ 'MAFSA3L' : '$11a', # Transceiver MAC Short Address
+ 'MAFSA3L_MAFSA3L': '$ff', # MAC Short Address low Byte for
+ 'MAFSA3H' : '$11b', # Transceiver MAC Short Address
+ 'MAFSA3H_MAFSA3H': '$ff', # MAC Short Address high Byte fo
+ 'MAFPA3L' : '$11c', # Transceiver Personal Area Netw
+ 'MAFPA3L_MAFPA3L': '$ff', # MAC Personal Area Network ID l
+ 'MAFPA3H' : '$11d', # Transceiver Personal Area Netw
+ 'MAFPA3H_MAFPA3H': '$ff', # MAC Personal Area Network ID h
+ 'MAFCR0' : '$10c', # Multiple Address Filter Config
+ 'MAFCR0_Res': '$f0', # Reserved Bit
+ 'MAFCR0_MAF3EN': '$8', # Multiple Address Filter 3 Enab
+ 'MAFCR0_MAF2EN': '$4', # Multiple Address Filter 2 Enab
+ 'MAFCR0_MAF1EN': '$2', # Multiple Address Filter 1 Enab
+ 'MAFCR0_MAF0EN': '$1', # Multiple Address Filter 0 Enab
+ 'MAFCR1' : '$10d', # Multiple Address Filter Config
+ 'MAFCR1_AACK_3_SET_PD': '$80', # Set Data Pending bit for addre
+ 'MAFCR1_AACK_3_I_AM_COORD': '$40', # Enable PAN Coordinator mode fo
+ 'MAFCR1_AACK_2_SET_PD': '$20', # Set Data Pending bit for addre
+ 'MAFCR1_AACK_2_I_AM_COORD': '$10', # Enable PAN Coordinator mode fo
+ 'MAFCR1_AACK_1_SET_PD': '$8', # Set Data Pending bit for addre
+ 'MAFCR1_AACK_1_I_AM_COORD': '$4', # Enable PAN Coordinator mode fo
+ 'MAFCR1_AACK_0_SET_PD': '$2', # Set Data Pending bit for addre
+ 'MAFCR1_AACK_0_I_AM_COORD': '$1', # Enable PAN Coordinator mode fo
+ 'AES_CTRL' : '$13c', # AES Control Register
+ 'AES_CTRL_AES_REQUEST': '$80', # Request AES Operation.
+ 'AES_CTRL_Res': '$40', # Reserved Bit
+ 'AES_CTRL_AES_MODE': '$20', # Set AES Operation Mode
+ 'AES_CTRL_Res': '$10', # Reserved Bit
+ 'AES_CTRL_AES_DIR': '$8', # Set AES Operation Direction
+ 'AES_CTRL_AES_IM': '$4', # AES Interrupt Enable
+ 'AES_CTRL_Res': '$3', # Reserved Bit
+ 'AES_STATUS' : '$13d', # AES Status Register
+ 'AES_STATUS_AES_ER': '$80', # AES Operation Finished with Er
+ 'AES_STATUS_Res': '$7e', # Reserved
+ 'AES_STATUS_AES_DONE': '$1', # AES Operation Finished with Su
+ 'AES_STATE' : '$13e', # AES Plain and Cipher Text Buff
+ 'AES_STATE_AES_STATE': '$ff', # AES Plain and Cipher Text Buff
+ 'AES_KEY' : '$13f', # AES Encryption and Decryption
+ 'AES_KEY_AES_KEY': '$ff', # AES Encryption/Decryption Key
+ 'TRX_STATUS' : '$141', # Transceiver Status Register
+ 'TRX_STATUS_CCA_DONE': '$80', # CCA Algorithm Status
+ 'TRX_STATUS_CCA_STATUS': '$40', # CCA Status Result
+ 'TRX_STATUS_TST_STATUS': '$20', # Test mode status
+ 'TRX_STATUS_TRX_STATUS': '$1f', # Transceiver Main Status
+ 'TRX_STATE' : '$142', # Transceiver State Control Regi
+ 'TRX_STATE_TRAC_STATUS': '$e0', # Transaction Status
+ 'TRX_STATE_TRX_CMD': '$1f', # State Control Command
+ 'TRX_CTRL_0' : '$143', # Reserved
+ 'TRX_CTRL_0_Res7': '$80', # Reserved
+ 'TRX_CTRL_0_PMU_EN': '$40', # Enable Phase Measurement Unit
+ 'TRX_CTRL_0_PMU_START': '$20', # Start of Phase Measurement Uni
+ 'TRX_CTRL_0_PMU_IF_INV': '$10', # PMU IF Inverse
+ 'TRX_CTRL_0_Res': '$f', # Reserved
+ 'TRX_CTRL_1' : '$144', # Transceiver Control Register 1
+ 'TRX_CTRL_1_PA_EXT_EN': '$80', # External PA support enable
+ 'TRX_CTRL_1_IRQ_2_EXT_EN': '$40', # Connect Frame Start IRQ to TC1
+ 'TRX_CTRL_1_TX_AUTO_CRC_ON': '$20', # Enable Automatic CRC Calculati
+ 'TRX_CTRL_1_PLL_TX_FLT': '$10', # Enable PLL TX filter
+ 'TRX_CTRL_1_Res': '$f', # Reserved
+ 'PHY_TX_PWR' : '$145', # Transceiver Transmit Power Con
+ 'PHY_TX_PWR_Res': '$f0', # Reserved
+ 'PHY_TX_PWR_TX_PWR': '$f', # Transmit Power Setting
+ 'PHY_RSSI' : '$146', # Receiver Signal Strength Indic
+ 'PHY_RSSI_RX_CRC_VALID': '$80', # Received Frame CRC Status
+ 'PHY_RSSI_RND_VALUE': '$60', # Random Value
+ 'PHY_RSSI_RSSI': '$1f', # Receiver Signal Strength Indic
+ 'PHY_ED_LEVEL' : '$147', # Transceiver Energy Detection L
+ 'PHY_ED_LEVEL_ED_LEVEL': '$ff', # Energy Detection Level
+ 'PHY_CC_CCA' : '$148', # Transceiver Clear Channel Asse
+ 'PHY_CC_CCA_CCA_REQUEST': '$80', # Manual CCA Measurement Request
+ 'PHY_CC_CCA_CCA_MODE': '$60', # Select CCA Measurement Mode
+ 'PHY_CC_CCA_CHANNEL': '$1f', # RX/TX Channel Selection
+ 'CCA_THRES' : '$149', # Transceiver CCA Threshold Sett
+ 'CCA_THRES_CCA_CS_THRES': '$f0', # CS Threshold Level for CCA Mea
+ 'CCA_THRES_CCA_ED_THRES': '$f', # ED Threshold Level for CCA Mea
+ 'RX_CTRL' : '$14a', # Transceiver Receive Control Re
+ 'RX_CTRL_PDT_THRES': '$f', # Receiver Sensitivity Control
+ 'SFD_VALUE' : '$14b', # Start of Frame Delimiter Value
+ 'SFD_VALUE_SFD_VALUE': '$ff', # Start of Frame Delimiter Value
+ 'TRX_CTRL_2' : '$14c', # Transceiver Control Register 2
+ 'TRX_CTRL_2_RX_SAFE_MODE': '$80', # RX Safe Mode
+ 'TRX_CTRL_2_Res': '$7c', # Reserved
+ 'TRX_CTRL_2_OQPSK_DATA_RATE': '$3', # Data Rate Selection
+ 'ANT_DIV' : '$14d', # Antenna Diversity Control Regi
+ 'ANT_DIV_ANT_SEL': '$80', # Antenna Diversity Antenna Stat
+ 'ANT_DIV_Res': '$70', # Reserved
+ 'ANT_DIV_ANT_DIV_EN': '$8', # Enable Antenna Diversity
+ 'ANT_DIV_ANT_EXT_SW_EN': '$4', # Enable External Antenna Switch
+ 'ANT_DIV_ANT_CTRL': '$3', # Static Antenna Diversity Switc
+ 'IRQ_MASK' : '$14e', # Transceiver Interrupt Enable R
+ 'IRQ_MASK_AWAKE_EN': '$80', # Awake Interrupt Enable
+ 'IRQ_MASK_TX_END_EN': '$40', # TX_END Interrupt Enable
+ 'IRQ_MASK_AMI_EN': '$20', # Address Match Interrupt Enable
+ 'IRQ_MASK_CCA_ED_DONE_EN': '$10', # End of ED Measurement Interrup
+ 'IRQ_MASK_RX_END_EN': '$8', # RX_END Interrupt Enable
+ 'IRQ_MASK_RX_START_EN': '$4', # RX_START Interrupt Enable
+ 'IRQ_MASK_PLL_UNLOCK_EN': '$2', # PLL Unlock Interrupt Enable
+ 'IRQ_MASK_PLL_LOCK_EN': '$1', # PLL Lock Interrupt Enable
+ 'IRQ_STATUS' : '$14f', # Transceiver Interrupt Status R
+ 'IRQ_STATUS_AWAKE': '$80', # Awake Interrupt Status
+ 'IRQ_STATUS_TX_END': '$40', # TX_END Interrupt Status
+ 'IRQ_STATUS_AMI': '$20', # Address Match Interrupt Status
+ 'IRQ_STATUS_CCA_ED_DONE': '$10', # End of ED Measurement Interrup
+ 'IRQ_STATUS_RX_END': '$8', # RX_END Interrupt Status
+ 'IRQ_STATUS_RX_START': '$4', # RX_START Interrupt Status
+ 'IRQ_STATUS_PLL_UNLOCK': '$2', # PLL Unlock Interrupt Status
+ 'IRQ_STATUS_PLL_LOCK': '$1', # PLL Lock Interrupt Status
+ 'IRQ_MASK1' : '$be', # Transceiver Interrupt Enable R
+ 'IRQ_MASK1_Res': '$e0', # Reserved Bit
+ 'IRQ_MASK1_MAF_3_AMI_EN': '$10', # Address Match Interrupt enable
+ 'IRQ_MASK1_MAF_2_AMI_EN': '$8', # Address Match Interrupt enable
+ 'IRQ_MASK1_MAF_1_AMI_EN': '$4', # Address Match Interrupt enable
+ 'IRQ_MASK1_MAF_0_AMI_EN': '$2', # Address Match Interrupt enable
+ 'IRQ_MASK1_TX_START_EN': '$1', # Transmit Start Interrupt enabl
+ 'IRQ_STATUS1' : '$bf', # Transceiver Interrupt Status R
+ 'IRQ_STATUS1_Res': '$e0', # Reserved Bit
+ 'IRQ_STATUS1_MAF_3_AMI': '$10', # Address Match Interrupt Status
+ 'IRQ_STATUS1_MAF_2_AMI': '$8', # Address Match Interrupt Status
+ 'IRQ_STATUS1_MAF_1_AMI': '$4', # Address Match Interrupt Status
+ 'IRQ_STATUS1_MAF_0_AMI': '$2', # Address Match Interrupt Status
+ 'IRQ_STATUS1_TX_START': '$1', # Transmit Start Interrupt Statu
+ 'VREG_CTRL' : '$150', # Voltage Regulator Control and
+ 'VREG_CTRL_AVREG_EXT': '$80', # Use External AVDD Regulator
+ 'VREG_CTRL_AVDD_OK': '$40', # AVDD Supply Voltage Valid
+ 'VREG_CTRL_DVREG_EXT': '$8', # Use External DVDD Regulator
+ 'VREG_CTRL_DVDD_OK': '$4', # DVDD Supply Voltage Valid
+ 'BATMON' : '$151', # Battery Monitor Control and St
+ 'BATMON_BAT_LOW': '$80', # Battery Monitor Interrupt Stat
+ 'BATMON_BAT_LOW_EN': '$40', # Battery Monitor Interrupt Enab
+ 'BATMON_BATMON_OK': '$20', # Battery Monitor Status
+ 'BATMON_BATMON_HR': '$10', # Battery Monitor Voltage Range
+ 'BATMON_BATMON_VTH': '$f', # Battery Monitor Threshold Volt
+ 'XOSC_CTRL' : '$152', # Crystal Oscillator Control Reg
+ 'XOSC_CTRL_XTAL_MODE': '$f0', # Crystal Oscillator Operating M
+ 'XOSC_CTRL_XTAL_TRIM': '$f', # Crystal Oscillator Load Capaci
+ 'CC_CTRL_0' : '$153', # Channel Control Register 0
+ 'CC_CTRL_0_CC_NUMBER': '$ff', # Channel Number
+ 'CC_CTRL_1' : '$154', # Channel Control Register 1
+ 'CC_CTRL_1_CC_BAND': '$f', # Channel Band
+ 'RX_SYN' : '$155', # Transceiver Receiver Sensitivi
+ 'RX_SYN_RX_PDT_DIS': '$80', # Prevent Frame Reception
+ 'RX_SYN_RX_OVERRIDE': '$40', # Receiver Override Function
+ 'RX_SYN_Res': '$30', # Reserved
+ 'RX_SYN_RX_PDT_LEVEL': '$f', # Reduce Receiver Sensitivity
+ 'TRX_RPC' : '$156', # Transceiver Reduced Power Cons
+ 'TRX_RPC_RX_RPC_CTRL': '$c0', # Smart Receiving Mode Timing
+ 'TRX_RPC_RX_RPC_EN': '$20', # Reciver Smart Receiving Mode E
+ 'TRX_RPC_PDT_RPC_EN': '$10', # Smart Receiving Mode Reduced S
+ 'TRX_RPC_PLL_RPC_EN': '$8', # PLL Smart Receiving Mode Enabl
+ 'TRX_RPC_Res0': '$4', # Reserved
+ 'TRX_RPC_IPAN_RPC_EN': '$2', # Smart Receiving Mode IPAN Hand
+ 'TRX_RPC_XAH_RPC_EN': '$1', # Smart Receiving in Extended Op
+ 'XAH_CTRL_1' : '$157', # Transceiver Acknowledgment Fra
+ 'XAH_CTRL_1_Res': '$c0', # Reserved Bit
+ 'XAH_CTRL_1_AACK_FLTR_RES_FT': '$20', # Filter Reserved Frames
+ 'XAH_CTRL_1_AACK_UPLD_RES_FT': '$10', # Process Reserved Frames
+ 'XAH_CTRL_1_Res': '$8', # Reserved Bit
+ 'XAH_CTRL_1_AACK_ACK_TIME': '$4', # Reduce Acknowledgment Time
+ 'XAH_CTRL_1_AACK_PROM_MODE': '$2', # Enable Promiscuous Mode
+ 'XAH_CTRL_1_Res': '$1', # Reserved Bit
+ 'FTN_CTRL' : '$158', # Transceiver Filter Tuning Cont
+ 'FTN_CTRL_FTN_START': '$80', # Start Calibration Loop of Filt
+ 'PLL_CF' : '$15a', # Transceiver Center Frequency C
+ 'PLL_CF_PLL_CF_START': '$80', # Start Center Frequency Calibra
+ 'PLL_DCU' : '$15b', # Transceiver Delay Cell Calibra
+ 'PLL_DCU_PLL_DCU_START': '$80', # Start Delay Cell Calibration
+ 'PART_NUM' : '$15c', # Device Identification Register
+ 'PART_NUM_PART_NUM': '$ff', # Part Number
+ 'VERSION_NUM' : '$15d', # Device Identification Register
+ 'VERSION_NUM_VERSION_NUM': '$ff', # Version Number
+ 'MAN_ID_0' : '$15e', # Device Identification Register
+ 'MAN_ID_0_MAN_ID_07': '$80', # Manufacturer ID (Low Byte)
+ 'MAN_ID_0_MAN_ID_06': '$40', # Manufacturer ID (Low Byte)
+ 'MAN_ID_0_MAN_ID_05': '$20', # Manufacturer ID (Low Byte)
+ 'MAN_ID_0_MAN_ID_04': '$10', # Manufacturer ID (Low Byte)
+ 'MAN_ID_0_MAN_ID_03': '$8', # Manufacturer ID (Low Byte)
+ 'MAN_ID_0_MAN_ID_02': '$4', # Manufacturer ID (Low Byte)
+ 'MAN_ID_0_MAN_ID_01': '$2', # Manufacturer ID (Low Byte)
+ 'MAN_ID_0_MAN_ID_00': '$1', # Manufacturer ID (Low Byte)
+ 'MAN_ID_1' : '$15f', # Device Identification Register
+ 'MAN_ID_1_MAN_ID_': '$ff', # Manufacturer ID (High Byte)
+ 'SHORT_ADDR_0' : '$160', # Transceiver MAC Short Address
+ 'SHORT_ADDR_0_SHORT_ADDR_07': '$80', # MAC Short Address
+ 'SHORT_ADDR_0_SHORT_ADDR_06': '$40', # MAC Short Address
+ 'SHORT_ADDR_0_SHORT_ADDR_05': '$20', # MAC Short Address
+ 'SHORT_ADDR_0_SHORT_ADDR_04': '$10', # MAC Short Address
+ 'SHORT_ADDR_0_SHORT_ADDR_03': '$8', # MAC Short Address
+ 'SHORT_ADDR_0_SHORT_ADDR_02': '$4', # MAC Short Address
+ 'SHORT_ADDR_0_SHORT_ADDR_01': '$2', # MAC Short Address
+ 'SHORT_ADDR_0_SHORT_ADDR_00': '$1', # MAC Short Address
+ 'SHORT_ADDR_1' : '$161', # Transceiver MAC Short Address
+ 'SHORT_ADDR_1_SHORT_ADDR_': '$ff', # MAC Short Address
+ 'PAN_ID_0' : '$162', # Transceiver Personal Area Netw
+ 'PAN_ID_0_PAN_ID_07': '$80', # MAC Personal Area Network ID
+ 'PAN_ID_0_PAN_ID_06': '$40', # MAC Personal Area Network ID
+ 'PAN_ID_0_PAN_ID_05': '$20', # MAC Personal Area Network ID
+ 'PAN_ID_0_PAN_ID_04': '$10', # MAC Personal Area Network ID
+ 'PAN_ID_0_PAN_ID_03': '$8', # MAC Personal Area Network ID
+ 'PAN_ID_0_PAN_ID_02': '$4', # MAC Personal Area Network ID
+ 'PAN_ID_0_PAN_ID_01': '$2', # MAC Personal Area Network ID
+ 'PAN_ID_0_PAN_ID_00': '$1', # MAC Personal Area Network ID
+ 'PAN_ID_1' : '$163', # Transceiver Personal Area Netw
+ 'PAN_ID_1_PAN_ID_': '$ff', # MAC Personal Area Network ID
+ 'IEEE_ADDR_0' : '$164', # Transceiver MAC IEEE Address R
+ 'IEEE_ADDR_0_IEEE_ADDR_07': '$80', # MAC IEEE Address
+ 'IEEE_ADDR_0_IEEE_ADDR_06': '$40', # MAC IEEE Address
+ 'IEEE_ADDR_0_IEEE_ADDR_05': '$20', # MAC IEEE Address
+ 'IEEE_ADDR_0_IEEE_ADDR_04': '$10', # MAC IEEE Address
+ 'IEEE_ADDR_0_IEEE_ADDR_03': '$8', # MAC IEEE Address
+ 'IEEE_ADDR_0_IEEE_ADDR_02': '$4', # MAC IEEE Address
+ 'IEEE_ADDR_0_IEEE_ADDR_01': '$2', # MAC IEEE Address
+ 'IEEE_ADDR_0_IEEE_ADDR_00': '$1', # MAC IEEE Address
+ 'IEEE_ADDR_1' : '$165', # Transceiver MAC IEEE Address R
+ 'IEEE_ADDR_1_IEEE_ADDR_': '$ff', # MAC IEEE Address
+ 'IEEE_ADDR_2' : '$166', # Transceiver MAC IEEE Address R
+ 'IEEE_ADDR_2_IEEE_ADDR_': '$ff', # MAC IEEE Address
+ 'IEEE_ADDR_3' : '$167', # Transceiver MAC IEEE Address R
+ 'IEEE_ADDR_3_IEEE_ADDR_': '$ff', # MAC IEEE Address
+ 'IEEE_ADDR_4' : '$168', # Transceiver MAC IEEE Address R
+ 'IEEE_ADDR_4_IEEE_ADDR_': '$ff', # MAC IEEE Address
+ 'IEEE_ADDR_5' : '$169', # Transceiver MAC IEEE Address R
+ 'IEEE_ADDR_5_IEEE_ADDR_': '$ff', # MAC IEEE Address
+ 'IEEE_ADDR_6' : '$16a', # Transceiver MAC IEEE Address R
+ 'IEEE_ADDR_6_IEEE_ADDR_': '$ff', # MAC IEEE Address
+ 'IEEE_ADDR_7' : '$16b', # Transceiver MAC IEEE Address R
+ 'IEEE_ADDR_7_IEEE_ADDR_': '$ff', # MAC IEEE Address
+ 'XAH_CTRL_0' : '$16c', # Transceiver Extended Operating
+ 'XAH_CTRL_0_MAX_FRAME_RETRIES': '$f0', # Maximum Number of Frame Re-tra
+ 'XAH_CTRL_0_MAX_CSMA_RETRIES': '$e', # Maximum Number of CSMA-CA Proc
+ 'XAH_CTRL_0_SLOTTED_OPERATION': '$1', # Set Slotted Acknowledgment
+ 'CSMA_SEED_0' : '$16d', # Transceiver CSMA-CA Random Num
+ 'CSMA_SEED_0_CSMA_SEED_07': '$80', # Seed Value for CSMA Random Num
+ 'CSMA_SEED_0_CSMA_SEED_06': '$40', # Seed Value for CSMA Random Num
+ 'CSMA_SEED_0_CSMA_SEED_05': '$20', # Seed Value for CSMA Random Num
+ 'CSMA_SEED_0_CSMA_SEED_04': '$10', # Seed Value for CSMA Random Num
+ 'CSMA_SEED_0_CSMA_SEED_03': '$8', # Seed Value for CSMA Random Num
+ 'CSMA_SEED_0_CSMA_SEED_02': '$4', # Seed Value for CSMA Random Num
+ 'CSMA_SEED_0_CSMA_SEED_01': '$2', # Seed Value for CSMA Random Num
+ 'CSMA_SEED_0_CSMA_SEED_00': '$1', # Seed Value for CSMA Random Num
+ 'CSMA_SEED_1' : '$16e', # Transceiver Acknowledgment Fra
+ 'CSMA_SEED_1_AACK_FVN_MODE': '$c0', # Acknowledgment Frame Filter Mo
+ 'CSMA_SEED_1_AACK_SET_PD': '$20', # Set Frame Pending Sub-field
+ 'CSMA_SEED_1_AACK_DIS_ACK': '$10', # Disable Acknowledgment Frame T
+ 'CSMA_SEED_1_AACK_I_AM_COORD': '$8', # Set Personal Area Network Coor
+ 'CSMA_SEED_1_CSMA_SEED_1': '$7', # Seed Value for CSMA Random Num
+ 'CSMA_BE' : '$16f', # Transceiver CSMA-CA Back-off E
+ 'CSMA_BE_MAX_BE': '$f0', # Maximum Back-off Exponent
+ 'CSMA_BE_MIN_BE': '$f', # Minimum Back-off Exponent
+ 'TST_CTRL_DIGI' : '$176', # Transceiver Digital Test Contr
+ 'TST_CTRL_DIGI_TST_CTRL_DIG': '$f', # Digital Test Controller Regist
+ 'TST_RX_LENGTH' : '$17b', # Transceiver Received Frame Len
+ 'TST_RX_LENGTH_RX_LENGTH': '$ff', # Received Frame Length
+ 'TRXFBST' : '$180', # Start of frame buffer
+ 'TRXFBEND' : '$1ff', # End of frame buffer
+
+# Module SYMCNT
+ 'SCTSTRHH' : '$fc', # Symbol Counter Transmit Frame
+ 'SCTSTRHH_SCTSTRHH': '$ff', # Symbol Counter Transmit Frame
+ 'SCTSTRHL' : '$fb', # Symbol Counter Transmit Frame
+ 'SCTSTRHL_SCTSTRHL': '$ff', # Symbol Counter Transmit Frame
+ 'SCTSTRLH' : '$fa', # Symbol Counter Transmit Frame
+ 'SCTSTRLH_SCTSTRLH': '$ff', # Symbol Counter Transmit Frame
+ 'SCTSTRLL' : '$f9', # Symbol Counter Transmit Frame
+ 'SCTSTRLL_SCTSTRLL': '$ff', # Symbol Counter Transmit Frame
+ 'SCOCR1HH' : '$f8', # Symbol Counter Output Compare
+ 'SCOCR1HH_SCOCR1HH': '$ff', # Symbol Counter Output Compare
+ 'SCOCR1HL' : '$f7', # Symbol Counter Output Compare
+ 'SCOCR1HL_SCOCR1HL': '$ff', # Symbol Counter Output Compare
+ 'SCOCR1LH' : '$f6', # Symbol Counter Output Compare
+ 'SCOCR1LH_SCOCR1LH': '$ff', # Symbol Counter Output Compare
+ 'SCOCR1LL' : '$f5', # Symbol Counter Output Compare
+ 'SCOCR1LL_SCOCR1LL': '$ff', # Symbol Counter Output Compare
+ 'SCOCR2HH' : '$f4', # Symbol Counter Output Compare
+ 'SCOCR2HH_SCOCR2HH': '$ff', # Symbol Counter Output Compare
+ 'SCOCR2HL' : '$f3', # Symbol Counter Output Compare
+ 'SCOCR2HL_SCOCR2HL': '$ff', # Symbol Counter Output Compare
+ 'SCOCR2LH' : '$f2', # Symbol Counter Output Compare
+ 'SCOCR2LH_SCOCR2LH': '$ff', # Symbol Counter Output Compare
+ 'SCOCR2LL' : '$f1', # Symbol Counter Output Compare
+ 'SCOCR2LL_SCOCR2LL': '$ff', # Symbol Counter Output Compare
+ 'SCOCR3HH' : '$f0', # Symbol Counter Output Compare
+ 'SCOCR3HH_SCOCR3HH': '$ff', # Symbol Counter Output Compare
+ 'SCOCR3HL' : '$ef', # Symbol Counter Output Compare
+ 'SCOCR3HL_SCOCR3HL': '$ff', # Symbol Counter Output Compare
+ 'SCOCR3LH' : '$ee', # Symbol Counter Output Compare
+ 'SCOCR3LH_SCOCR3LH': '$ff', # Symbol Counter Output Compare
+ 'SCOCR3LL' : '$ed', # Symbol Counter Output Compare
+ 'SCOCR3LL_SCOCR3LL': '$ff', # Symbol Counter Output Compare
+ 'SCTSRHH' : '$ec', # Symbol Counter Frame Timestamp
+ 'SCTSRHH_SCTSRHH': '$ff', # Symbol Counter Frame Timestamp
+ 'SCTSRHL' : '$eb', # Symbol Counter Frame Timestamp
+ 'SCTSRHL_SCTSRHL': '$ff', # Symbol Counter Frame Timestamp
+ 'SCTSRLH' : '$ea', # Symbol Counter Frame Timestamp
+ 'SCTSRLH_SCTSRLH': '$ff', # Symbol Counter Frame Timestamp
+ 'SCTSRLL' : '$e9', # Symbol Counter Frame Timestamp
+ 'SCTSRLL_SCTSRLL': '$ff', # Symbol Counter Frame Timestamp
+ 'SCBTSRHH' : '$e8', # Symbol Counter Beacon Timestam
+ 'SCBTSRHH_SCBTSRHH': '$ff', # Symbol Counter Beacon Timestam
+ 'SCBTSRHL' : '$e7', # Symbol Counter Beacon Timestam
+ 'SCBTSRHL_SCBTSRHL': '$ff', # Symbol Counter Beacon Timestam
+ 'SCBTSRLH' : '$e6', # Symbol Counter Beacon Timestam
+ 'SCBTSRLH_SCBTSRLH': '$ff', # Symbol Counter Beacon Timestam
+ 'SCBTSRLL' : '$e5', # Symbol Counter Beacon Timestam
+ 'SCBTSRLL_SCBTSRLL': '$ff', # Symbol Counter Beacon Timestam
+ 'SCCNTHH' : '$e4', # Symbol Counter Register HH-Byt
+ 'SCCNTHH_SCCNTHH': '$ff', # Symbol Counter Register HH-Byt
+ 'SCCNTHL' : '$e3', # Symbol Counter Register HL-Byt
+ 'SCCNTHL_SCCNTHL': '$ff', # Symbol Counter Register HL-Byt
+ 'SCCNTLH' : '$e2', # Symbol Counter Register LH-Byt
+ 'SCCNTLH_SCCNTLH': '$ff', # Symbol Counter Register LH-Byt
+ 'SCCNTLL' : '$e1', # Symbol Counter Register LL-Byt
+ 'SCCNTLL_SCCNTLL': '$ff', # Symbol Counter Register LL-Byt
+ 'SCIRQS' : '$e0', # Symbol Counter Interrupt Statu
+ 'SCIRQS_Res': '$e0', # Reserved Bit
+ 'SCIRQS_IRQSBO': '$10', # Backoff Slot Counter IRQ
+ 'SCIRQS_IRQSOF': '$8', # Symbol Counter Overflow IRQ
+ 'SCIRQS_IRQSCP': '$7', # Compare Unit 3 Compare Match I
+ 'SCIRQM' : '$df', # Symbol Counter Interrupt Mask
+ 'SCIRQM_Res': '$e0', # Reserved Bit
+ 'SCIRQM_IRQMBO': '$10', # Backoff Slot Counter IRQ enabl
+ 'SCIRQM_IRQMOF': '$8', # Symbol Counter Overflow IRQ en
+ 'SCIRQM_IRQMCP': '$7', # Symbol Counter Compare Match 3
+ 'SCSR' : '$de', # Symbol Counter Status Register
+ 'SCSR_Res': '$fe', # Reserved Bit
+ 'SCSR_SCBSY': '$1', # Symbol Counter busy
+ 'SCCR1' : '$dd', # Symbol Counter Control Registe
+ 'SCCR1_Res': '$c0', # Reserved Bit
+ 'SCCR1_SCBTSM': '$20', # Symbol Counter Beacon Timestam
+ 'SCCR1_SCCKDIV': '$1c', # Clock divider for synchronous
+ 'SCCR1_SCEECLK': '$2', # Enable External Clock Source o
+ 'SCCR1_SCENBO': '$1', # Backoff Slot Counter enable
+ 'SCCR0' : '$dc', # Symbol Counter Control Registe
+ 'SCCR0_SCRES': '$80', # Symbol Counter Synchronization
+ 'SCCR0_SCMBTS': '$40', # Manual Beacon Timestamp
+ 'SCCR0_SCEN': '$20', # Symbol Counter enable
+ 'SCCR0_SCCKSEL': '$10', # Symbol Counter Clock Source se
+ 'SCCR0_SCTSE': '$8', # Symbol Counter Automatic Times
+ 'SCCR0_SCCMP': '$7', # Symbol Counter Compare Unit 3
+ 'SCCSR' : '$db', # Symbol Counter Compare Source
+ 'SCCSR_Res': '$c0', # Reserved Bit
+ 'SCCSR_SCCS3': '$30', # Symbol Counter Compare Source
+ 'SCCSR_SCCS2': '$c', # Symbol Counter Compare Source
+ 'SCCSR_SCCS1': '$3', # Symbol Counter Compare Source
+ 'SCRSTRHH' : '$da', # Symbol Counter Received Frame
+ 'SCRSTRHH_SCRSTRHH': '$ff', # Symbol Counter Received Frame
+ 'SCRSTRHL' : '$d9', # Symbol Counter Received Frame
+ 'SCRSTRHL_SCRSTRHL': '$ff', # Symbol Counter Received Frame
+ 'SCRSTRLH' : '$d8', # Symbol Counter Received Frame
+ 'SCRSTRLH_SCRSTRLH': '$ff', # Symbol Counter Received Frame
+ 'SCRSTRLL' : '$d7', # Symbol Counter Received Frame
+ 'SCRSTRLL_SCRSTRLL': '$ff', # Symbol Counter Received Frame
+
+# Module EEPROM
+ 'EEAR' : '$41', # EEPROM Address Register Bytes
+ 'EEDR' : '$40', # EEPROM Data Register
+ 'EECR' : '$3f', # EEPROM Control Register
+ 'EECR_Res': '$c0', # Reserved
+ 'EECR_EEPM': '$30', # EEPROM Programming Mode
+ 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
+ 'EECR_EEMPE': '$4', # EEPROM Master Write Enable
+ 'EECR_EEPE': '$2', # EEPROM Programming Enable
+ 'EECR_EERE': '$1', # EEPROM Read Enable
+
+# Module JTAG
+ 'OCDR' : '$51', # On-Chip Debug Register
+ 'OCDR_OCDR': '$ff', # On-Chip Debug Register Data
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_JTD': '$80', # JTAG Interface Disable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+
+# Module EXTERNAL_INTERRUPT
+ 'EICRA' : '$69', # External Interrupt Control Reg
+ 'EICRA_ISC3': '$c0', # External Interrupt 3 Sense Con
+ 'EICRA_ISC2': '$30', # External Interrupt 2 Sense Con
+ 'EICRA_ISC1': '$c', # External Interrupt 1 Sense Con
+ 'EICRA_ISC0': '$3', # External Interrupt 0 Sense Con
+ 'EICRB' : '$6a', # External Interrupt Control Reg
+ 'EICRB_ISC7': '$c0', # External Interrupt 7 Sense Con
+ 'EICRB_ISC6': '$30', # External Interrupt 6 Sense Con
+ 'EICRB_ISC5': '$c', # External Interrupt 5 Sense Con
+ 'EICRB_ISC4': '$3', # External Interrupt 4 Sense Con
+ 'EIMSK' : '$3d', # External Interrupt Mask Regist
+ 'EIMSK_INT': '$ff', # External Interrupt Request Ena
+ 'EIFR' : '$3c', # External Interrupt Flag Regist
+ 'EIFR_INTF': '$ff', # External Interrupt Flag
+ 'PCMSK2' : '$6d', # Pin Change Mask Register 2
+ 'PCMSK2_PCINT': '$ff', # Pin Change Enable Mask
+ 'PCMSK1' : '$6c', # Pin Change Mask Register 1
+ 'PCMSK1_PCINT': '$ff', # Pin Change Enable Mask
+ 'PCMSK0' : '$6b', # Pin Change Mask Register 0
+ 'PCIFR' : '$3b', # Pin Change Interrupt Flag Regi
+ 'PCIFR_Res': '$f8', # Reserved Bit
+ 'PCIFR_PCIF': '$7', # Pin Change Interrupt Flags
+ 'PCICR' : '$68', # Pin Change Interrupt Control R
+ 'PCICR_Res': '$f8', # Reserved Bit
+ 'PCICR_PCIE': '$7', # Pin Change Interrupt Enables
+
+# Module AD_CONVERTER
+ 'ADMUX' : '$7c', # The ADC Multiplexer Selection
+ 'ADMUX_REFS': '$c0', # Reference Selection Bits
+ 'ADMUX_ADLAR': '$20', # ADC Left Adjust Result
+ 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
+ 'ADC' : '$78', # ADC Data Register Bytes
+ 'ADCSRA' : '$7a', # The ADC Control and Status Reg
+ 'ADCSRA_ADEN': '$80', # ADC Enable
+ 'ADCSRA_ADSC': '$40', # ADC Start Conversion
+ 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
+ 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
+ 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
+ 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
+ 'ADCSRB' : '$7b', # The ADC Control and Status Reg
+ 'ADCSRB_AVDDOK': '$80', # AVDD Supply Voltage OK
+ 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
+ 'ADCSRB_REFOK': '$20', # Reference Voltage OK
+ 'ADCSRB_ACCH': '$10', # Analog Channel Change
+ 'ADCSRB_MUX5': '$8', # Analog Channel and Gain Select
+ 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Source
+ 'ADCSRC' : '$77', # The ADC Control and Status Reg
+ 'ADCSRC_ADTHT': '$c0', # ADC Track-and-Hold Time
+ 'ADCSRC_Res0': '$20', # Reserved
+ 'ADCSRC_ADSUT': '$1f', # ADC Start-up Time
+ 'DIDR2' : '$7d', # Digital Input Disable Register
+ 'DIDR2_ADC15D': '$80', # Reserved Bits
+ 'DIDR2_ADC14D': '$40', # Reserved Bits
+ 'DIDR2_ADC13D': '$20', # Reserved Bits
+ 'DIDR2_ADC12D': '$10', # Reserved Bits
+ 'DIDR2_ADC11D': '$8', # Reserved Bits
+ 'DIDR2_ADC10D': '$4', # Reserved Bits
+ 'DIDR2_ADC9D': '$2', # Reserved Bits
+ 'DIDR2_ADC8D': '$1', # Reserved Bits
+ 'DIDR0' : '$7e', # Digital Input Disable Register
+ 'DIDR0_ADC7D': '$80', # Disable ADC7:0 Digital Input
+ 'DIDR0_ADC6D': '$40', # Disable ADC7:0 Digital Input
+ 'DIDR0_ADC5D': '$20', # Disable ADC7:0 Digital Input
+ 'DIDR0_ADC4D': '$10', # Disable ADC7:0 Digital Input
+ 'DIDR0_ADC3D': '$8', # Disable ADC7:0 Digital Input
+ 'DIDR0_ADC2D': '$4', # Disable ADC7:0 Digital Input
+ 'DIDR0_ADC1D': '$2', # Disable ADC7:0 Digital Input
+ 'DIDR0_ADC0D': '$1', # Disable ADC7:0 Digital Input
+
+# Module BOOT_LOAD
+ 'SPMCSR' : '$57', # Store Program Memory Control R
+ 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
+ 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
+ 'SPMCSR_SIGRD': '$20', # Signature Row Read
+ 'SPMCSR_RWWSRE': '$10', # Read While Write Section Read
+ 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
+ 'SPMCSR_PGWRT': '$4', # Page Write
+ 'SPMCSR_PGERS': '$2', # Page Erase
+ 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
+
+# Module CPU
+ 'SREG' : '$5f', # Status Register
+ 'SREG_I': '$80', # Global Interrupt Enable
+ 'SREG_T': '$40', # Bit Copy Storage
+ 'SREG_H': '$20', # Half Carry Flag
+ 'SREG_S': '$10', # Sign Bit
+ 'SREG_V': '$8', # Two's Complement Overflow Flag
+ 'SREG_N': '$4', # Negative Flag
+ 'SREG_Z': '$2', # Zero Flag
+ 'SREG_C': '$1', # Carry Flag
+ 'SP' : '$5d', # Stack Pointer
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_JTD': '$80', # JTAG Interface Disable
+ 'MCUCR_Res': '$60', # Reserved
+ 'MCUCR_PUD': '$10', # Pull-up Disable
+ 'MCUCR_Res': '$c', # Reserved
+ 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
+ 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_Res': '$e0', # Reserved
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+ 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
+ 'MCUSR_BORF': '$4', # Brown-out Reset Flag
+ 'MCUSR_EXTRF': '$2', # External Reset Flag
+ 'MCUSR_PORF': '$1', # Power-on Reset Flag
+ 'OSCCAL' : '$66', # Oscillator Calibration Value
+ 'OSCCAL_CAL': '$ff', # Oscillator Calibration Tuning
+ 'CLKPR' : '$61', # Clock Prescale Register
+ 'CLKPR_CLKPCE': '$80', # Clock Prescaler Change Enable
+ 'CLKPR_Res': '$70', # Reserved
+ 'CLKPR_CLKPS': '$f', # Clock Prescaler Select Bits
+ 'SMCR' : '$53', # Sleep Mode Control Register
+ 'SMCR_Res': '$f0', # Reserved
+ 'SMCR_SM': '$e', # Sleep Mode Select bits
+ 'SMCR_SE': '$1', # Sleep Enable
+ 'RAMPZ' : '$5b', # Extended Z-pointer Register fo
+ 'RAMPZ_Res': '$fe', # Reserved
+ 'RAMPZ_RAMPZ0': '$1', # Extended Z-Pointer Value
+ 'GPIOR2' : '$4b', # General Purpose I/O Register 2
+ 'GPIOR2_GPIOR': '$ff', # General Purpose I/O Register 2
+ 'GPIOR1' : '$4a', # General Purpose IO Register 1
+ 'GPIOR1_GPIOR': '$ff', # General Purpose I/O Register 1
+ 'GPIOR0' : '$3e', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR07': '$80', # General Purpose I/O Register 0
+ 'GPIOR0_GPIOR06': '$40', # General Purpose I/O Register 0
+ 'GPIOR0_GPIOR05': '$20', # General Purpose I/O Register 0
+ 'GPIOR0_GPIOR04': '$10', # General Purpose I/O Register 0
+ 'GPIOR0_GPIOR03': '$8', # General Purpose I/O Register 0
+ 'GPIOR0_GPIOR02': '$4', # General Purpose I/O Register 0
+ 'GPIOR0_GPIOR01': '$2', # General Purpose I/O Register 0
+ 'GPIOR0_GPIOR00': '$1', # General Purpose I/O Register 0
+ 'PRR2' : '$63', # Power Reduction Register 2
+ 'PRR2_Res': '$f0', # Reserved Bit
+ 'PRR2_PRRAM': '$f', # Power Reduction SRAMs
+ 'PRR1' : '$65', # Power Reduction Register 1
+ 'PRR1_Res': '$80', # Reserved Bit
+ 'PRR1_PRTRX24': '$40', # Power Reduction Transceiver
+ 'PRR1_PRTIM5': '$20', # Power Reduction Timer/Counter5
+ 'PRR1_PRTIM4': '$10', # Power Reduction Timer/Counter4
+ 'PRR1_PRTIM3': '$8', # Power Reduction Timer/Counter3
+ 'PRR1_PRUSART1': '$1', # Power Reduction USART1
+ 'PRR0' : '$64', # Power Reduction Register0
+ 'PRR0_PRTWI': '$80', # Power Reduction TWI
+ 'PRR0_PRTIM2': '$40', # Power Reduction Timer/Counter2
+ 'PRR0_PRTIM0': '$20', # Power Reduction Timer/Counter0
+ 'PRR0_PRPGA': '$10', # Power Reduction PGA
+ 'PRR0_PRTIM1': '$8', # Power Reduction Timer/Counter1
+ 'PRR0_PRSPI': '$4', # Power Reduction Serial Periphe
+ 'PRR0_PRUSART0': '$2', # Power Reduction USART
+ 'PRR0_PRADC': '$1', # Power Reduction ADC
+
+# Module FLASH
+ 'NEMCR' : '$75', # Flash Extended-Mode Control-Re
+ 'NEMCR_ENEAM': '$40', # Enable Extended Address Mode f
+ 'NEMCR_AEAM': '$30', # Address for Extended Address M
+ 'BGCR' : '$67', # Reference Voltage Calibration
+ 'BGCR_Res': '$80', # Reserved Bit
+ 'BGCR_BGCAL_FINE': '$78', # Fine Calibration Bits
+ 'BGCR_BGCAL': '$7', # Coarse Calibration Bits
+
+# Module PWRCTRL
+ 'TRXPR' : '$139', # Transceiver Pin Register
+ 'TRXPR_Res': '$f0', # Reserved
+ 'TRXPR_SLPTR': '$2', # Multi-purpose Transceiver Cont
+ 'TRXPR_TRXRST': '$1', # Force Transceiver Reset
+ 'DRTRAM0' : '$135', # Data Retention Configuration R
+ 'DRTRAM0_Res': '$c0', # Reserved
+ 'DRTRAM0_DRTSWOK': '$20', # DRT Switch OK
+ 'DRTRAM0_ENDRT': '$10', # Enable SRAM Data Retention
+ 'DRTRAM1' : '$134', # Data Retention Configuration R
+ 'DRTRAM1_Res': '$c0', # Reserved
+ 'DRTRAM1_DRTSWOK': '$20', # DRT Switch OK
+ 'DRTRAM1_ENDRT': '$10', # Enable SRAM Data Retention
+ 'DRTRAM2' : '$133', # Data Retention Configuration R
+ 'DRTRAM2_Res': '$40', # Reserved Bit
+ 'DRTRAM2_DRTSWOK': '$20', # DRT Switch OK
+ 'DRTRAM2_ENDRT': '$10', # Enable SRAM Data Retention
+ 'DRTRAM3' : '$132', # Data Retention Configuration R
+ 'DRTRAM3_Res': '$c0', # Reserved
+ 'DRTRAM3_DRTSWOK': '$20', # DRT Switch OK
+ 'DRTRAM3_ENDRT': '$10', # Enable SRAM Data Retention
+ 'LLDRL' : '$130', # Low Leakage Voltage Regulator
+ 'LLDRL_Res': '$f0', # Reserved
+ 'LLDRL_LLDRL': '$f', # Low-Byte Data Register Bits
+ 'LLDRH' : '$131', # Low Leakage Voltage Regulator
+ 'LLDRH_Res': '$e0', # Reserved
+ 'LLDRH_LLDRH': '$1f', # High-Byte Data Register Bits
+ 'LLCR' : '$12f', # Low Leakage Voltage Regulator
+ 'LLCR_Res': '$c0', # Reserved Bit
+ 'LLCR_LLDONE': '$20', # Calibration Done
+ 'LLCR_LLCOMP': '$10', # Comparator Output
+ 'LLCR_LLCAL': '$8', # Calibration Active
+ 'LLCR_LLTCO': '$4', # Temperature Coefficient of Cur
+ 'LLCR_LLSHORT': '$2', # Short Lower Calibration Circui
+ 'LLCR_LLENCAL': '$1', # Enable Automatic Calibration
+ 'DPDS0' : '$136', # Port Driver Strength Register
+ 'DPDS0_PFDRV': '$c0', # Driver Strength Port F
+ 'DPDS0_PEDRV': '$30', # Driver Strength Port E
+ 'DPDS0_PDDRV': '$c', # Driver Strength Port D
+ 'DPDS0_PBDRV': '$3', # Driver Strength Port B
+ 'DPDS1' : '$137', # Port Driver Strength Register
+ 'DPDS1_Res': '$fc', # Reserved
+ 'DPDS1_PGDRV': '$3', # Driver Strength Port G
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_PUD': '$10', # Pull-up Disable
+
+# Module USART0_SPI
+ 'UCSR0A' : '$c0', # USART0 MSPIM Control and Statu
+ 'UCSR0A_RXC0': '$80', # USART Receive Complete
+ 'UCSR0A_TXC0': '$40', # USART Transmit Complete
+ 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
+ 'UCSR0B' : '$c1', # USART0 MSPIM Control and Statu
+ 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
+ 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
+ 'UCSR0B_UDRIE0': '$20', # USART Data Register Empty Inte
+ 'UCSR0B_RXEN0': '$10', # Receiver Enable
+ 'UCSR0B_TXEN0': '$8', # Transmitter Enable
+ 'UCSR0C' : '$c2', # USART0 MSPIM Control and Statu
+ 'UCSR0C_UDORD0': '$4', # Data Order
+ 'UCSR0C_UCPHA0': '$2', # Clock Phase
+ 'UCSR0C_UCPOL0': '$1', # Clock Polarity
+
+# Module USART1_SPI
+ 'UCSR1A' : '$c8', # USART1 MSPIM Control and Statu
+ 'UCSR1A_RXC1': '$80', # USART Receive Complete
+ 'UCSR1A_TXC1': '$40', # USART Transmit Complete
+ 'UCSR1A_UDRE1': '$20', # USART Data Register Empty
+ 'UCSR1B' : '$c9', # USART1 MSPIM Control and Statu
+ 'UCSR1B_RXCIE1': '$80', # RX Complete Interrupt Enable
+ 'UCSR1B_TXCIE1': '$40', # TX Complete Interrupt Enable
+ 'UCSR1B_UDRIE1': '$20', # USART Data Register Empty Inte
+ 'UCSR1B_RXEN1': '$10', # Receiver Enable
+ 'UCSR1B_TXEN1': '$8', # Transmitter Enable
+ 'UCSR1C' : '$ca', # USART1 MSPIM Control and Statu
+ 'UCSR1C_UDORD1': '$4', # Data Order
+ 'UCSR1C_UCPHA1': '$2', # Clock Phase
+ 'UCSR1C_UCPOL1': '$1', # Clock Polarity
+
+ '__amforth_dummy':'0'
+}
diff --git a/amforth-6.5/avr8/devices/atmega16/atmega16.frt b/amforth-6.5/avr8/devices/atmega16/atmega16.frt
new file mode 100644
index 0000000..2f95ec1
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega16/atmega16.frt
@@ -0,0 +1,221 @@
+\ Partname: ATmega16
+\ generated automatically
+
+\ TIMER_COUNTER_0
+&83 constant TCCR0 \ Timer/Counter Control Register
+ $80 constant TCCR0_FOC0 \ Force Output Compare
+ $40 constant TCCR0_WGM00 \ Waveform Generation Mode 0
+ $30 constant TCCR0_COM0 \ Compare Match Output Modes
+ $08 constant TCCR0_WGM01 \ Waveform Generation Mode 1
+ $07 constant TCCR0_CS0 \ Clock Selects
+&82 constant TCNT0 \ Timer/Counter Register
+&92 constant OCR0 \ Output Compare Register
+&89 constant TIMSK \ Timer/Counter Interrupt Mask Register
+ $02 constant TIMSK_OCIE0 \ Timer/Counter0 Output Compare Match Interrupt register
+ $01 constant TIMSK_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
+&88 constant TIFR \ Timer/Counter Interrupt Flag register
+ $02 constant TIFR_OCF0 \ Output Compare Flag 0
+ $01 constant TIFR_TOV0 \ Timer/Counter0 Overflow Flag
+&80 constant SFIOR \ Special Function IO Register
+ $01 constant SFIOR_PSR10 \ Prescaler Reset Timer/Counter1 and Timer/Counter0
+\ TIMER_COUNTER_1
+&79 constant TCCR1A \ Timer/Counter1 Control Register A
+ $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
+ $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
+ $08 constant TCCR1A_FOC1A \ Force Output Compare 1A
+ $04 constant TCCR1A_FOC1B \ Force Output Compare 1B
+ $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
+&78 constant TCCR1B \ Timer/Counter1 Control Register B
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
+ $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
+&76 constant TCNT1 \ Timer/Counter1 Bytes
+&74 constant OCR1A \ Timer/Counter1 Output Compare Register Bytes
+&72 constant OCR1B \ Timer/Counter1 Output Compare Register Bytes
+&70 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
+\ EXTERNAL_INTERRUPT
+&91 constant GICR \ General Interrupt Control Register
+ $C0 constant GICR_INT \ External Interrupt Request 1 Enable
+ $20 constant GICR_INT2 \ External Interrupt Request 2 Enable
+ $02 constant GICR_IVSEL \ Interrupt Vector Select
+ $01 constant GICR_IVCE \ Interrupt Vector Change Enable
+&90 constant GIFR \ General Interrupt Flag Register
+ $C0 constant GIFR_INTF \ External Interrupt Flags
+ $20 constant GIFR_INTF2 \ External Interrupt Flag 2
+&85 constant MCUCR \ General Interrupt Control Register
+ $0C constant MCUCR_ISC1 \ Interrupt Sense Control 1 Bits
+ $03 constant MCUCR_ISC0 \ Interrupt Sense Control 0 Bits
+&84 constant MCUCSR \ MCU Control And Status Register
+ $40 constant MCUCSR_ISC2 \ Interrupt Sense Control 2
+\ EEPROM
+&62 constant EEAR \ EEPROM Address Register Bytes
+&61 constant EEDR \ EEPROM Data Register
+&60 constant EECR \ EEPROM Control Register
+ $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
+ $04 constant EECR_EEMWE \ EEPROM Master Write Enable
+ $02 constant EECR_EEWE \ EEPROM Write Enable
+ $01 constant EECR_EERE \ EEPROM Read Enable
+\ CPU
+&95 constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ $08 constant SREG_V \ Two's Complement Overflow Flag
+ $04 constant SREG_N \ Negative Flag
+ $02 constant SREG_Z \ Zero Flag
+ $01 constant SREG_C \ Carry Flag
+&93 constant SP \ Stack Pointer
+&81 constant OSCCAL \ Oscillator Calibration Value
+\ TIMER_COUNTER_2
+&69 constant TCCR2 \ Timer/Counter2 Control Register
+ $80 constant TCCR2_FOC2 \ Force Output Compare
+ $40 constant TCCR2_WGM20 \ Waveform Genration Mode
+ $30 constant TCCR2_COM2 \ Compare Output Mode bits
+ $08 constant TCCR2_WGM21 \ Waveform Generation Mode
+ $07 constant TCCR2_CS2 \ Clock Select bits
+&68 constant TCNT2 \ Timer/Counter2
+&67 constant OCR2 \ Timer/Counter2 Output Compare Register
+&66 constant ASSR \ Asynchronous Status Register
+ $08 constant ASSR_AS2 \ Asynchronous Timer/counter2
+ $04 constant ASSR_TCN2UB \ Timer/Counter2 Update Busy
+ $02 constant ASSR_OCR2UB \ Output Compare Register2 Update Busy
+ $01 constant ASSR_TCR2UB \ Timer/counter Control Register2 Update Busy
+\ SPI
+&47 constant SPDR \ SPI Data Register
+&46 constant SPSR \ SPI Status Register
+ $80 constant SPSR_SPIF \ SPI Interrupt Flag
+ $40 constant SPSR_WCOL \ Write Collision Flag
+ $01 constant SPSR_SPI2X \ Double SPI Speed Bit
+&45 constant SPCR \ SPI Control Register
+ $80 constant SPCR_SPIE \ SPI Interrupt Enable
+ $40 constant SPCR_SPE \ SPI Enable
+ $20 constant SPCR_DORD \ Data Order
+ $10 constant SPCR_MSTR \ Master/Slave Select
+ $08 constant SPCR_CPOL \ Clock polarity
+ $04 constant SPCR_CPHA \ Clock Phase
+ $03 constant SPCR_SPR \ SPI Clock Rate Selects
+\ USART
+&44 constant UDR \ USART I/O Data Register
+&43 constant UCSRA \ USART Control and Status Register A
+ $80 constant UCSRA_RXC \ USART Receive Complete
+ $40 constant UCSRA_TXC \ USART Transmitt Complete
+ $20 constant UCSRA_UDRE \ USART Data Register Empty
+ $10 constant UCSRA_FE \ Framing Error
+ $08 constant UCSRA_DOR \ Data overRun
+ $04 constant UCSRA_UPE \ Parity Error
+ $02 constant UCSRA_U2X \ Double the USART transmission speed
+ $01 constant UCSRA_MPCM \ Multi-processor Communication Mode
+&42 constant UCSRB \ USART Control and Status Register B
+ $80 constant UCSRB_RXCIE \ RX Complete Interrupt Enable
+ $40 constant UCSRB_TXCIE \ TX Complete Interrupt Enable
+ $20 constant UCSRB_UDRIE \ USART Data register Empty Interrupt Enable
+ $10 constant UCSRB_RXEN \ Receiver Enable
+ $08 constant UCSRB_TXEN \ Transmitter Enable
+ $04 constant UCSRB_UCSZ2 \ Character Size
+ $02 constant UCSRB_RXB8 \ Receive Data Bit 8
+ $01 constant UCSRB_TXB8 \ Transmit Data Bit 8
+&64 constant UCSRC \ USART Control and Status Register C
+ $80 constant UCSRC_URSEL \ Register Select
+ $40 constant UCSRC_UMSEL \ USART Mode Select
+ $30 constant UCSRC_UPM \ Parity Mode Bits
+ $08 constant UCSRC_USBS \ Stop Bit Select
+ $06 constant UCSRC_UCSZ \ Character Size
+ $01 constant UCSRC_UCPOL \ Clock Polarity
+&64 constant UBRRH \ USART Baud Rate Register Hight Byte
+&41 constant UBRRL \ USART Baud Rate Register Low Byte
+\ TWI
+&32 constant TWBR \ TWI Bit Rate register
+&86 constant TWCR \ TWI Control Register
+ $80 constant TWCR_TWINT \ TWI Interrupt Flag
+ $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
+ $20 constant TWCR_TWSTA \ TWI Start Condition Bit
+ $10 constant TWCR_TWSTO \ TWI Stop Condition Bit
+ $08 constant TWCR_TWWC \ TWI Write Collition Flag
+ $04 constant TWCR_TWEN \ TWI Enable Bit
+ $01 constant TWCR_TWIE \ TWI Interrupt Enable
+&33 constant TWSR \ TWI Status Register
+ $F8 constant TWSR_TWS \ TWI Status
+ $03 constant TWSR_TWPS \ TWI Prescaler
+&35 constant TWDR \ TWI Data register
+&34 constant TWAR \ TWI (Slave) Address register
+ $FE constant TWAR_TWA \ TWI (Slave) Address register Bits
+ $01 constant TWAR_TWGCE \ TWI General Call Recognition Enable Bit
+\ ANALOG_COMPARATOR
+&40 constant ACSR \ Analog Comparator Control And Status Register
+ $80 constant ACSR_ACD \ Analog Comparator Disable
+ $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
+ $20 constant ACSR_ACO \ Analog Compare Output
+ $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
+ $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
+ $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
+ $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
+\ AD_CONVERTER
+&39 constant ADMUX \ The ADC multiplexer Selection Register
+ $C0 constant ADMUX_REFS \ Reference Selection Bits
+ $20 constant ADMUX_ADLAR \ Left Adjust Result
+ $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
+&38 constant ADCSRA \ The ADC Control and Status register
+ $80 constant ADCSRA_ADEN \ ADC Enable
+ $40 constant ADCSRA_ADSC \ ADC Start Conversion
+ $20 constant ADCSRA_ADATE \ When this bit is written to one,the Timer/Counter2 prescaler will be reset.The bit will be cleared by hardware after the operation is performed.Writing a zero to this bit will have no effect.This bit will always be read as zero if Timer/Counter2 is clocked by the internal CPU clock.If this bit is written when Timer/Counter2 is operating in asynchronous mode,the bit will remain one until the prescaler has been reset.
+ $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
+ $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
+ $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
+&36 constant ADC \ ADC Data Register Bytes
+\ JTAG
+&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
+ $FF constant OCDR_OCDR \ On-Chip Debug Register Bits
+\ BOOT_LOAD
+&87 constant SPMCSR \ Store Program Memory Control Register
+ $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
+ $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
+ $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
+ $04 constant SPMCSR_PGWRT \ Page Write
+ $02 constant SPMCSR_PGERS \ Page Erase
+ $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
+\ PORTA
+&59 constant PORTA \ Port A Data Register
+&58 constant DDRA \ Port A Data Direction Register
+&57 constant PINA \ Port A Input Pins
+\ PORTB
+&56 constant PORTB \ Port B Data Register
+&55 constant DDRB \ Port B Data Direction Register
+&54 constant PINB \ Port B Input Pins
+\ PORTC
+&53 constant PORTC \ Port C Data Register
+&52 constant DDRC \ Port C Data Direction Register
+&51 constant PINC \ Port C Input Pins
+\ PORTD
+&50 constant PORTD \ Port D Data Register
+&49 constant DDRD \ Port D Data Direction Register
+&48 constant PIND \ Port D Input Pins
+\ WATCHDOG
+&65 constant WDTCR \ Watchdog Timer Control Register
+ $10 constant WDTCR_WDTOE \ RW
+ $08 constant WDTCR_WDE \ Watch Dog Enable
+ $07 constant WDTCR_WDP \ Watch Dog Timer Prescaler bits
+
+\ Interrupts
+&2 constant INT0Addr \ External Interrupt Request 0
+&4 constant INT1Addr \ External Interrupt Request 1
+&6 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
+&8 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
+&10 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+&12 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
+&14 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
+&16 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+&18 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
+&20 constant SPI_STCAddr \ Serial Transfer Complete
+&22 constant USART_RXCAddr \ USART, Rx Complete
+&24 constant USART_UDREAddr \ USART Data Register Empty
+&26 constant USART_TXCAddr \ USART, Tx Complete
+&28 constant ADCAddr \ ADC Conversion Complete
+&30 constant EE_RDYAddr \ EEPROM Ready
+&32 constant ANA_COMPAddr \ Analog Comparator
+&34 constant TWIAddr \ 2-wire Serial Interface
+&36 constant INT2Addr \ External Interrupt Request 2
+&38 constant TIMER0_COMPAddr \ Timer/Counter0 Compare Match
+&40 constant SPM_RDYAddr \ Store Program Memory Ready
diff --git a/amforth-6.5/avr8/devices/atmega16/device.asm b/amforth-6.5/avr8/devices/atmega16/device.asm
new file mode 100644
index 0000000..f0ec3af
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega16/device.asm
@@ -0,0 +1,101 @@
+; Partname: ATmega16
+; generated automatically, do not edit
+
+.nolist
+ .include "m16def.inc"
+.list
+
+.equ ramstart = 96
+.equ CELLSIZE = 2
+.macro readflashcell
+ lsl zl
+ rol zh
+ lpm @0, Z+
+ lpm @1, Z+
+.endmacro
+.macro writeflashcell
+ lsl zl
+ rol zh
+.endmacro
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_EEPROM = 0
+.set WANT_CPU = 0
+.set WANT_TIMER_COUNTER_2 = 0
+.set WANT_SPI = 0
+.set WANT_USART = 0
+.set WANT_TWI = 0
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_AD_CONVERTER = 0
+.set WANT_JTAG = 0
+.set WANT_BOOT_LOAD = 0
+.set WANT_PORTA = 0
+.set WANT_PORTB = 0
+.set WANT_PORTC = 0
+.set WANT_PORTD = 0
+.set WANT_WATCHDOG = 0
+.equ intvecsize = 2 ; please verify; flash size: 16384 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.org 2
+ rcall isr ; External Interrupt Request 0
+.org 4
+ rcall isr ; External Interrupt Request 1
+.org 6
+ rcall isr ; Timer/Counter2 Compare Match
+.org 8
+ rcall isr ; Timer/Counter2 Overflow
+.org 10
+ rcall isr ; Timer/Counter1 Capture Event
+.org 12
+ rcall isr ; Timer/Counter1 Compare Match A
+.org 14
+ rcall isr ; Timer/Counter1 Compare Match B
+.org 16
+ rcall isr ; Timer/Counter1 Overflow
+.org 18
+ rcall isr ; Timer/Counter0 Overflow
+.org 20
+ rcall isr ; Serial Transfer Complete
+.org 22
+ rcall isr ; USART, Rx Complete
+.org 24
+ rcall isr ; USART Data Register Empty
+.org 26
+ rcall isr ; USART, Tx Complete
+.org 28
+ rcall isr ; ADC Conversion Complete
+.org 30
+ rcall isr ; EEPROM Ready
+.org 32
+ rcall isr ; Analog Comparator
+.org 34
+ rcall isr ; 2-wire Serial Interface
+.org 36
+ rcall isr ; External Interrupt Request 2
+.org 38
+ rcall isr ; Timer/Counter0 Compare Match
+.org 40
+ rcall isr ; Store Program Memory Ready
+.equ INTVECTORS = 21
+.nooverlap
+
+; compatability layer (maybe empty)
+.equ EEPE = EEWE
+.equ EEMPE = EEMWE
+
+; controller data area, environment query mcu-info
+mcu_info:
+mcu_ramsize:
+ .dw 1024
+mcu_eepromsize:
+ .dw 512
+mcu_maxdp:
+ .dw 14336
+mcu_numints:
+ .dw 21
+mcu_name:
+ .dw 8
+ .db "ATmega16"
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega16/device.inc b/amforth-6.5/avr8/devices/atmega16/device.inc
new file mode 100644
index 0000000..04e4766
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega16/device.inc
@@ -0,0 +1,765 @@
+; Partname: ATmega16
+; generated automatically, no not edit
+
+.if WANT_TIMER_COUNTER_0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register
+VE_TCCR0:
+ .dw $ff05
+ .db "TCCR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0
+XT_TCCR0:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0:
+ .dw 83
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Register
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw 82
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare Register
+VE_OCR0:
+ .dw $ff04
+ .db "OCR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0
+XT_OCR0:
+ .dw PFA_DOVARIABLE
+PFA_OCR0:
+ .dw 92
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Mask Register
+VE_TIMSK:
+ .dw $ff05
+ .db "TIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK
+XT_TIMSK:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK:
+ .dw 89
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Flag register
+VE_TIFR:
+ .dw $ff04
+ .db "TIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR
+XT_TIFR:
+ .dw PFA_DOVARIABLE
+PFA_TIFR:
+ .dw 88
+; ( -- addr ) System Constant
+; R( -- )
+; Special Function IO Register
+VE_SFIOR:
+ .dw $ff05
+ .db "SFIOR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SFIOR
+XT_SFIOR:
+ .dw PFA_DOVARIABLE
+PFA_SFIOR:
+ .dw 80
+
+.endif
+.if WANT_TIMER_COUNTER_1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw 79
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw 78
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Bytes
+VE_TCNT1:
+ .dw $ff05
+ .db "TCNT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1
+XT_TCNT1:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1:
+ .dw 76
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register Bytes
+VE_OCR1A:
+ .dw $ff05
+ .db "OCR1A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1A
+XT_OCR1A:
+ .dw PFA_DOVARIABLE
+PFA_OCR1A:
+ .dw 74
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register Bytes
+VE_OCR1B:
+ .dw $ff05
+ .db "OCR1B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1B
+XT_OCR1B:
+ .dw PFA_DOVARIABLE
+PFA_OCR1B:
+ .dw 72
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Bytes
+VE_ICR1:
+ .dw $ff04
+ .db "ICR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1
+XT_ICR1:
+ .dw PFA_DOVARIABLE
+PFA_ICR1:
+ .dw 70
+
+.endif
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ( -- addr ) System Constant
+; R( -- )
+; General Interrupt Control Register
+VE_GICR:
+ .dw $ff04
+ .db "GICR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GICR
+XT_GICR:
+ .dw PFA_DOVARIABLE
+PFA_GICR:
+ .dw 91
+; ( -- addr ) System Constant
+; R( -- )
+; General Interrupt Flag Register
+VE_GIFR:
+ .dw $ff04
+ .db "GIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GIFR
+XT_GIFR:
+ .dw PFA_DOVARIABLE
+PFA_GIFR:
+ .dw 90
+; ( -- addr ) System Constant
+; R( -- )
+; General Interrupt Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw 85
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control And Status Register
+VE_MCUCSR:
+ .dw $ff06
+ .db "MCUCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCSR
+XT_MCUCSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCSR:
+ .dw 84
+
+.endif
+.if WANT_EEPROM == 1
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Address Register Bytes
+VE_EEAR:
+ .dw $ff04
+ .db "EEAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEAR
+XT_EEAR:
+ .dw PFA_DOVARIABLE
+PFA_EEAR:
+ .dw 62
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw 61
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw 60
+
+.endif
+.if WANT_CPU == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw 95
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer
+VE_SP:
+ .dw $ff02
+ .db "SP"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SP
+XT_SP:
+ .dw PFA_DOVARIABLE
+PFA_SP:
+ .dw 93
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Calibration Value
+VE_OSCCAL:
+ .dw $ff06
+ .db "OSCCAL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSCCAL
+XT_OSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_OSCCAL:
+ .dw 81
+
+.endif
+.if WANT_TIMER_COUNTER_2 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register
+VE_TCCR2:
+ .dw $ff05
+ .db "TCCR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2
+XT_TCCR2:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2:
+ .dw 69
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2
+VE_TCNT2:
+ .dw $ff05
+ .db "TCNT2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT2
+XT_TCNT2:
+ .dw PFA_DOVARIABLE
+PFA_TCNT2:
+ .dw 68
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register
+VE_OCR2:
+ .dw $ff04
+ .db "OCR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2
+XT_OCR2:
+ .dw PFA_DOVARIABLE
+PFA_OCR2:
+ .dw 67
+; ( -- addr ) System Constant
+; R( -- )
+; Asynchronous Status Register
+VE_ASSR:
+ .dw $ff04
+ .db "ASSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ASSR
+XT_ASSR:
+ .dw PFA_DOVARIABLE
+PFA_ASSR:
+ .dw 66
+
+.endif
+.if WANT_SPI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR:
+ .dw $ff04
+ .db "SPDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR
+XT_SPDR:
+ .dw PFA_DOVARIABLE
+PFA_SPDR:
+ .dw 47
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR:
+ .dw $ff04
+ .db "SPSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR
+XT_SPSR:
+ .dw PFA_DOVARIABLE
+PFA_SPSR:
+ .dw 46
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR:
+ .dw $ff04
+ .db "SPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR
+XT_SPCR:
+ .dw PFA_DOVARIABLE
+PFA_SPCR:
+ .dw 45
+
+.endif
+.if WANT_USART == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR:
+ .dw $ff03
+ .db "UDR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR
+XT_UDR:
+ .dw PFA_DOVARIABLE
+PFA_UDR:
+ .dw 44
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSRA:
+ .dw $ff05
+ .db "UCSRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSRA
+XT_UCSRA:
+ .dw PFA_DOVARIABLE
+PFA_UCSRA:
+ .dw 43
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSRB:
+ .dw $ff05
+ .db "UCSRB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSRB
+XT_UCSRB:
+ .dw PFA_DOVARIABLE
+PFA_UCSRB:
+ .dw 42
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSRC:
+ .dw $ff05
+ .db "UCSRC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSRC
+XT_UCSRC:
+ .dw PFA_DOVARIABLE
+PFA_UCSRC:
+ .dw 64
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Hight Byte
+VE_UBRRH:
+ .dw $ff05
+ .db "UBRRH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRRH
+XT_UBRRH:
+ .dw PFA_DOVARIABLE
+PFA_UBRRH:
+ .dw 64
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Low Byte
+VE_UBRRL:
+ .dw $ff05
+ .db "UBRRL",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRRL
+XT_UBRRL:
+ .dw PFA_DOVARIABLE
+PFA_UBRRL:
+ .dw 41
+
+.endif
+.if WANT_TWI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Bit Rate register
+VE_TWBR:
+ .dw $ff04
+ .db "TWBR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWBR
+XT_TWBR:
+ .dw PFA_DOVARIABLE
+PFA_TWBR:
+ .dw 32
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Control Register
+VE_TWCR:
+ .dw $ff04
+ .db "TWCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWCR
+XT_TWCR:
+ .dw PFA_DOVARIABLE
+PFA_TWCR:
+ .dw 86
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Status Register
+VE_TWSR:
+ .dw $ff04
+ .db "TWSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWSR
+XT_TWSR:
+ .dw PFA_DOVARIABLE
+PFA_TWSR:
+ .dw 33
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Data register
+VE_TWDR:
+ .dw $ff04
+ .db "TWDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWDR
+XT_TWDR:
+ .dw PFA_DOVARIABLE
+PFA_TWDR:
+ .dw 35
+; ( -- addr ) System Constant
+; R( -- )
+; TWI (Slave) Address register
+VE_TWAR:
+ .dw $ff04
+ .db "TWAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWAR
+XT_TWAR:
+ .dw PFA_DOVARIABLE
+PFA_TWAR:
+ .dw 34
+
+.endif
+.if WANT_ANALOG_COMPARATOR == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Control And Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw 40
+
+.endif
+.if WANT_AD_CONVERTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC multiplexer Selection Register
+VE_ADMUX:
+ .dw $ff05
+ .db "ADMUX",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADMUX
+XT_ADMUX:
+ .dw PFA_DOVARIABLE
+PFA_ADMUX:
+ .dw 39
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register
+VE_ADCSRA:
+ .dw $ff06
+ .db "ADCSRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRA
+XT_ADCSRA:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRA:
+ .dw 38
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register Bytes
+VE_ADC:
+ .dw $ff03
+ .db "ADC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADC
+XT_ADC:
+ .dw PFA_DOVARIABLE
+PFA_ADC:
+ .dw 36
+
+.endif
+.if WANT_JTAG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; On-Chip Debug Related Register in I/O Memory
+VE_OCDR:
+ .dw $ff04
+ .db "OCDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCDR
+XT_OCDR:
+ .dw PFA_DOVARIABLE
+PFA_OCDR:
+ .dw 81
+
+.endif
+.if WANT_BOOT_LOAD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control Register
+VE_SPMCSR:
+ .dw $ff06
+ .db "SPMCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCSR
+XT_SPMCSR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCSR:
+ .dw 87
+
+.endif
+.if WANT_PORTA == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Register
+VE_PORTA:
+ .dw $ff05
+ .db "PORTA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTA
+XT_PORTA:
+ .dw PFA_DOVARIABLE
+PFA_PORTA:
+ .dw 59
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Direction Register
+VE_DDRA:
+ .dw $ff04
+ .db "DDRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRA
+XT_DDRA:
+ .dw PFA_DOVARIABLE
+PFA_DDRA:
+ .dw 58
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Input Pins
+VE_PINA:
+ .dw $ff04
+ .db "PINA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINA
+XT_PINA:
+ .dw PFA_DOVARIABLE
+PFA_PINA:
+ .dw 57
+
+.endif
+.if WANT_PORTB == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw 56
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw 55
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw 54
+
+.endif
+.if WANT_PORTC == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Register
+VE_PORTC:
+ .dw $ff05
+ .db "PORTC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTC
+XT_PORTC:
+ .dw PFA_DOVARIABLE
+PFA_PORTC:
+ .dw 53
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Direction Register
+VE_DDRC:
+ .dw $ff04
+ .db "DDRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRC
+XT_DDRC:
+ .dw PFA_DOVARIABLE
+PFA_DDRC:
+ .dw 52
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Input Pins
+VE_PINC:
+ .dw $ff04
+ .db "PINC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINC
+XT_PINC:
+ .dw PFA_DOVARIABLE
+PFA_PINC:
+ .dw 51
+
+.endif
+.if WANT_PORTD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw 50
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw 49
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw 48
+
+.endif
+.if WANT_WATCHDOG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCR:
+ .dw $ff05
+ .db "WDTCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCR
+XT_WDTCR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCR:
+ .dw 65
+
+.endif
diff --git a/amforth-6.5/avr8/devices/atmega16/device.py b/amforth-6.5/avr8/devices/atmega16/device.py
new file mode 100644
index 0000000..cd9f581
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega16/device.py
@@ -0,0 +1,284 @@
+# Generated Automatically
+
+# Partname ATmega16
+
+MCUREGS = {
+# Interrupt Vectors
+ 'INT0Addr' : '#2', # External Interrupt Request 0
+ 'INT1Addr' : '#4', # External Interrupt Request 1
+ 'TIMER2_COMPAddr' : '#6', # Timer/Counter2 Compare Match
+ 'TIMER2_OVFAddr' : '#8', # Timer/Counter2 Overflow
+ 'TIMER1_CAPTAddr' : '#10', # Timer/Counter1 Capture Event
+ 'TIMER1_COMPAAddr' : '#12', # Timer/Counter1 Compare Match A
+ 'TIMER1_COMPBAddr' : '#14', # Timer/Counter1 Compare Match B
+ 'TIMER1_OVFAddr' : '#16', # Timer/Counter1 Overflow
+ 'TIMER0_OVFAddr' : '#18', # Timer/Counter0 Overflow
+ 'SPI_STCAddr' : '#20', # Serial Transfer Complete
+ 'USART_RXCAddr' : '#22', # USART, Rx Complete
+ 'USART_UDREAddr' : '#24', # USART Data Register Empty
+ 'USART_TXCAddr' : '#26', # USART, Tx Complete
+ 'ADCAddr' : '#28', # ADC Conversion Complete
+ 'EE_RDYAddr' : '#30', # EEPROM Ready
+ 'ANA_COMPAddr' : '#32', # Analog Comparator
+ 'TWIAddr' : '#34', # 2-wire Serial Interface
+ 'INT2Addr' : '#36', # External Interrupt Request 2
+ 'TIMER0_COMPAddr' : '#38', # Timer/Counter0 Compare Match
+ 'SPM_RDYAddr' : '#40', # Store Program Memory Ready
+
+# Module TIMER_COUNTER_0
+ 'TCCR0' : '$53', # Timer/Counter Control Register
+ 'TCCR0_FOC0': '$80', # Force Output Compare
+ 'TCCR0_WGM00': '$40', # Waveform Generation Mode 0
+ 'TCCR0_COM0': '$30', # Compare Match Output Modes
+ 'TCCR0_WGM01': '$8', # Waveform Generation Mode 1
+ 'TCCR0_CS0': '$7', # Clock Selects
+ 'TCNT0' : '$52', # Timer/Counter Register
+ 'OCR0' : '$5c', # Output Compare Register
+ 'TIMSK' : '$59', # Timer/Counter Interrupt Mask R
+ 'TIMSK_OCIE0': '$2', # Timer/Counter0 Output Compare
+ 'TIMSK_TOIE0': '$1', # Timer/Counter0 Overflow Interr
+ 'TIFR' : '$58', # Timer/Counter Interrupt Flag r
+ 'TIFR_OCF0': '$2', # Output Compare Flag 0
+ 'TIFR_TOV0': '$1', # Timer/Counter0 Overflow Flag
+ 'SFIOR' : '$50', # Special Function IO Register
+ 'SFIOR_PSR10': '$1', # Prescaler Reset Timer/Counter1
+
+# Module TIMER_COUNTER_1
+ 'TIMSK' : '$59', # Timer/Counter Interrupt Mask R
+ 'TIMSK_TICIE1': '$20', # Timer/Counter1 Input Capture I
+ 'TIMSK_OCIE1A': '$10', # Timer/Counter1 Output CompareA
+ 'TIMSK_OCIE1B': '$8', # Timer/Counter1 Output CompareB
+ 'TIMSK_TOIE1': '$4', # Timer/Counter1 Overflow Interr
+ 'TIFR' : '$58', # Timer/Counter Interrupt Flag r
+ 'TIFR_ICF1': '$20', # Input Capture Flag 1
+ 'TIFR_OCF1A': '$10', # Output Compare Flag 1A
+ 'TIFR_OCF1B': '$8', # Output Compare Flag 1B
+ 'TIFR_TOV1': '$4', # Timer/Counter1 Overflow Flag
+ 'TCCR1A' : '$4f', # Timer/Counter1 Control Registe
+ 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
+ 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
+ 'TCCR1A_FOC1A': '$8', # Force Output Compare 1A
+ 'TCCR1A_FOC1B': '$4', # Force Output Compare 1B
+ 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
+ 'TCCR1B' : '$4e', # Timer/Counter1 Control Registe
+ 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
+ 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
+ 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
+ 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
+ 'TCNT1' : '$4c', # Timer/Counter1 Bytes
+ 'OCR1A' : '$4a', # Timer/Counter1 Output Compare
+ 'OCR1B' : '$48', # Timer/Counter1 Output Compare
+ 'ICR1' : '$46', # Timer/Counter1 Input Capture R
+
+# Module EXTERNAL_INTERRUPT
+ 'GICR' : '$5b', # General Interrupt Control Regi
+ 'GICR_INT': '$c0', # External Interrupt Request 1 E
+ 'GICR_INT2': '$20', # External Interrupt Request 2 E
+ 'GICR_IVSEL': '$2', # Interrupt Vector Select
+ 'GICR_IVCE': '$1', # Interrupt Vector Change Enable
+ 'GIFR' : '$5a', # General Interrupt Flag Registe
+ 'GIFR_INTF': '$c0', # External Interrupt Flags
+ 'GIFR_INTF2': '$20', # External Interrupt Flag 2
+ 'MCUCR' : '$55', # General Interrupt Control Regi
+ 'MCUCR_ISC1': '$c', # Interrupt Sense Control 1 Bits
+ 'MCUCR_ISC0': '$3', # Interrupt Sense Control 0 Bits
+ 'MCUCSR' : '$54', # MCU Control And Status Registe
+ 'MCUCSR_ISC2': '$40', # Interrupt Sense Control 2
+
+# Module EEPROM
+ 'EEAR' : '$3e', # EEPROM Address Register Bytes
+ 'EEDR' : '$3d', # EEPROM Data Register
+ 'EECR' : '$3c', # EEPROM Control Register
+ 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
+ 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
+ 'EECR_EEWE': '$2', # EEPROM Write Enable
+ 'EECR_EERE': '$1', # EEPROM Read Enable
+
+# Module CPU
+ 'SREG' : '$5f', # Status Register
+ 'SREG_I': '$80', # Global Interrupt Enable
+ 'SREG_T': '$40', # Bit Copy Storage
+ 'SREG_H': '$20', # Half Carry Flag
+ 'SREG_S': '$10', # Sign Bit
+ 'SREG_V': '$8', # Two's Complement Overflow Flag
+ 'SREG_N': '$4', # Negative Flag
+ 'SREG_Z': '$2', # Zero Flag
+ 'SREG_C': '$1', # Carry Flag
+ 'SP' : '$5d', # Stack Pointer
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_SM': '$b0', # Sleep Mode Select
+ 'MCUCR_SE': '$40', # Sleep Enable
+ 'MCUCR_ISC1': '$c', # Interrupt Sense Control 1 Bits
+ 'MCUCR_ISC0': '$3', # Interrupt Sense Control 0 Bits
+ 'MCUCSR' : '$54', # MCU Control And Status Registe
+ 'MCUCSR_JTD': '$80', # JTAG Interface Disable
+ 'MCUCSR_JTRF': '$10', # JTAG Reset Flag
+ 'MCUCSR_WDRF': '$8', # Watchdog Reset Flag
+ 'MCUCSR_BORF': '$4', # Brown-out Reset Flag
+ 'MCUCSR_EXTRF': '$2', # External Reset Flag
+ 'MCUCSR_PORF': '$1', # Power-on reset flag
+ 'OSCCAL' : '$51', # Oscillator Calibration Value
+ 'SFIOR' : '$50', # Special function I/O register
+ 'SFIOR_PUD': '$4', # Pull-up Disable
+ 'SFIOR_PSR2': '$2', # Prescaler reset
+ 'SFIOR_PSR10': '$1', # Prescaler reset
+
+# Module TIMER_COUNTER_2
+ 'TIMSK' : '$59', # Timer/Counter Interrupt Mask r
+ 'TIMSK_OCIE2': '$80', # Timer/Counter2 Output Compare
+ 'TIMSK_TOIE2': '$40', # Timer/Counter2 Overflow Interr
+ 'TIFR' : '$58', # Timer/Counter Interrupt Flag R
+ 'TIFR_OCF2': '$80', # Output Compare Flag 2
+ 'TIFR_TOV2': '$40', # Timer/Counter2 Overflow Flag
+ 'TCCR2' : '$45', # Timer/Counter2 Control Registe
+ 'TCCR2_FOC2': '$80', # Force Output Compare
+ 'TCCR2_WGM20': '$40', # Waveform Genration Mode
+ 'TCCR2_COM2': '$30', # Compare Output Mode bits
+ 'TCCR2_WGM21': '$8', # Waveform Generation Mode
+ 'TCCR2_CS2': '$7', # Clock Select bits
+ 'TCNT2' : '$44', # Timer/Counter2
+ 'OCR2' : '$43', # Timer/Counter2 Output Compare
+ 'ASSR' : '$42', # Asynchronous Status Register
+ 'ASSR_AS2': '$8', # Asynchronous Timer/counter2
+ 'ASSR_TCN2UB': '$4', # Timer/Counter2 Update Busy
+ 'ASSR_OCR2UB': '$2', # Output Compare Register2 Updat
+ 'ASSR_TCR2UB': '$1', # Timer/counter Control Register
+ 'SFIOR' : '$50', # Special Function IO Register
+ 'SFIOR_PSR2': '$2', # Prescaler Reset Timer/Counter2
+
+# Module SPI
+ 'SPDR' : '$2f', # SPI Data Register
+ 'SPSR' : '$2e', # SPI Status Register
+ 'SPSR_SPIF': '$80', # SPI Interrupt Flag
+ 'SPSR_WCOL': '$40', # Write Collision Flag
+ 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
+ 'SPCR' : '$2d', # SPI Control Register
+ 'SPCR_SPIE': '$80', # SPI Interrupt Enable
+ 'SPCR_SPE': '$40', # SPI Enable
+ 'SPCR_DORD': '$20', # Data Order
+ 'SPCR_MSTR': '$10', # Master/Slave Select
+ 'SPCR_CPOL': '$8', # Clock polarity
+ 'SPCR_CPHA': '$4', # Clock Phase
+ 'SPCR_SPR': '$3', # SPI Clock Rate Selects
+
+# Module USART
+ 'UDR' : '$2c', # USART I/O Data Register
+ 'UCSRA' : '$2b', # USART Control and Status Regis
+ 'UCSRA_RXC': '$80', # USART Receive Complete
+ 'UCSRA_TXC': '$40', # USART Transmitt Complete
+ 'UCSRA_UDRE': '$20', # USART Data Register Empty
+ 'UCSRA_FE': '$10', # Framing Error
+ 'UCSRA_DOR': '$8', # Data overRun
+ 'UCSRA_UPE': '$4', # Parity Error
+ 'UCSRA_U2X': '$2', # Double the USART transmission
+ 'UCSRA_MPCM': '$1', # Multi-processor Communication
+ 'UCSRB' : '$2a', # USART Control and Status Regis
+ 'UCSRB_RXCIE': '$80', # RX Complete Interrupt Enable
+ 'UCSRB_TXCIE': '$40', # TX Complete Interrupt Enable
+ 'UCSRB_UDRIE': '$20', # USART Data register Empty Inte
+ 'UCSRB_RXEN': '$10', # Receiver Enable
+ 'UCSRB_TXEN': '$8', # Transmitter Enable
+ 'UCSRB_UCSZ2': '$4', # Character Size
+ 'UCSRB_RXB8': '$2', # Receive Data Bit 8
+ 'UCSRB_TXB8': '$1', # Transmit Data Bit 8
+ 'UCSRC' : '$40', # USART Control and Status Regis
+ 'UCSRC_URSEL': '$80', # Register Select
+ 'UCSRC_UMSEL': '$40', # USART Mode Select
+ 'UCSRC_UPM': '$30', # Parity Mode Bits
+ 'UCSRC_USBS': '$8', # Stop Bit Select
+ 'UCSRC_UCSZ': '$6', # Character Size
+ 'UCSRC_UCPOL': '$1', # Clock Polarity
+ 'UBRRH' : '$40', # USART Baud Rate Register Hight
+ 'UBRRL' : '$29', # USART Baud Rate Register Low B
+
+# Module TWI
+ 'TWBR' : '$20', # TWI Bit Rate register
+ 'TWCR' : '$56', # TWI Control Register
+ 'TWCR_TWINT': '$80', # TWI Interrupt Flag
+ 'TWCR_TWEA': '$40', # TWI Enable Acknowledge Bit
+ 'TWCR_TWSTA': '$20', # TWI Start Condition Bit
+ 'TWCR_TWSTO': '$10', # TWI Stop Condition Bit
+ 'TWCR_TWWC': '$8', # TWI Write Collition Flag
+ 'TWCR_TWEN': '$4', # TWI Enable Bit
+ 'TWCR_TWIE': '$1', # TWI Interrupt Enable
+ 'TWSR' : '$21', # TWI Status Register
+ 'TWSR_TWS': '$f8', # TWI Status
+ 'TWSR_TWPS': '$3', # TWI Prescaler
+ 'TWDR' : '$23', # TWI Data register
+ 'TWAR' : '$22', # TWI (Slave) Address register
+ 'TWAR_TWA': '$fe', # TWI (Slave) Address register B
+ 'TWAR_TWGCE': '$1', # TWI General Call Recognition E
+
+# Module ANALOG_COMPARATOR
+ 'SFIOR' : '$50', # Special Function IO Register
+ 'SFIOR_ACME': '$8', # Analog Comparator Multiplexer
+ 'ACSR' : '$28', # Analog Comparator Control And
+ 'ACSR_ACD': '$80', # Analog Comparator Disable
+ 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
+ 'ACSR_ACO': '$20', # Analog Compare Output
+ 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
+ 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
+ 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
+ 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
+
+# Module AD_CONVERTER
+ 'ADMUX' : '$27', # The ADC multiplexer Selection
+ 'ADMUX_REFS': '$c0', # Reference Selection Bits
+ 'ADMUX_ADLAR': '$20', # Left Adjust Result
+ 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
+ 'ADCSRA' : '$26', # The ADC Control and Status reg
+ 'ADCSRA_ADEN': '$80', # ADC Enable
+ 'ADCSRA_ADSC': '$40', # ADC Start Conversion
+ 'ADCSRA_ADATE': '$20', # When this bit is written to on
+ 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
+ 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
+ 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
+ 'ADC' : '$24', # ADC Data Register Bytes
+ 'SFIOR' : '$50', # Special Function IO Register
+ 'SFIOR_ADTS': '$e0', # ADC Auto Trigger Sources
+
+# Module JTAG
+ 'OCDR' : '$51', # On-Chip Debug Related Register
+ 'OCDR_OCDR': '$ff', # On-Chip Debug Register Bits
+ 'MCUCSR' : '$54', # MCU Control And Status Registe
+ 'MCUCSR_JTD': '$80', # JTAG Interface Disable
+ 'MCUCSR_JTRF': '$10', # JTAG Reset Flag
+
+# Module BOOT_LOAD
+ 'SPMCSR' : '$57', # Store Program Memory Control R
+ 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
+ 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
+ 'SPMCSR_RWWSRE': '$10', # Read While Write section read
+ 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
+ 'SPMCSR_PGWRT': '$4', # Page Write
+ 'SPMCSR_PGERS': '$2', # Page Erase
+ 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
+
+# Module PORTA
+ 'PORTA' : '$3b', # Port A Data Register
+ 'DDRA' : '$3a', # Port A Data Direction Register
+ 'PINA' : '$39', # Port A Input Pins
+
+# Module PORTB
+ 'PORTB' : '$38', # Port B Data Register
+ 'DDRB' : '$37', # Port B Data Direction Register
+ 'PINB' : '$36', # Port B Input Pins
+
+# Module PORTC
+ 'PORTC' : '$35', # Port C Data Register
+ 'DDRC' : '$34', # Port C Data Direction Register
+ 'PINC' : '$33', # Port C Input Pins
+
+# Module PORTD
+ 'PORTD' : '$32', # Port D Data Register
+ 'DDRD' : '$31', # Port D Data Direction Register
+ 'PIND' : '$30', # Port D Input Pins
+
+# Module WATCHDOG
+ 'WDTCR' : '$41', # Watchdog Timer Control Registe
+ 'WDTCR_WDTOE': '$10', # RW
+ 'WDTCR_WDE': '$8', # Watch Dog Enable
+ 'WDTCR_WDP': '$7', # Watch Dog Timer Prescaler bits
+
+ '__amforth_dummy':'0'
+}
diff --git a/amforth-6.5/avr8/devices/atmega16/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega16/words/no-jtag.asm
new file mode 100644
index 0000000..352a4bb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega16/words/no-jtag.asm
@@ -0,0 +1,14 @@
+; ( -- )
+; ( -- )
+; MCU
+; disable jtag at runtime
+VE_NOJTAG:
+ .dw $FF05
+ .db "-jtag",0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOJTAG
+XT_NOJTAG:
+ .dw PFA_NOJTAG
+PFA_NOJTAG:
+
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega16/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega16/words/no-wdt.asm
new file mode 100644
index 0000000..4a12261
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega16/words/no-wdt.asm
@@ -0,0 +1,22 @@
+; ( -- )
+; MCU
+; disable watch dog timer at runtime
+VE_NOWDT:
+ .dw $ff04
+ .db "-wdt"
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOWDT
+XT_NOWDT:
+ .dw PFA_NOWDT
+PFA_NOWDT:
+
+; Reset WDT
+ wdr
+; Write logical one to WDTOE and WDE
+ in_ temp1, WDTCR
+ ori temp1, (1<<WDTOE)|(1<<WDE)
+ out WDTCR, temp1
+; Turn off WDT
+ ldi temp1, (0<<WDE)
+ out_ WDTCR, temp1
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega16/words/sleep.asm b/amforth-6.5/avr8/devices/atmega16/words/sleep.asm
new file mode 100644
index 0000000..778fa32
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega16/words/sleep.asm
@@ -0,0 +1,24 @@
+; ( mode -- )
+; MCU
+; put the controller into the specified sleep mode
+VE_SLEEP:
+ .dw $ff05
+ .db "sleep", 0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_SLEEP
+XT_SLEEP:
+ .dw PFA_SLEEP
+PFA_SLEEP:
+ andi tosl, 7 ; leave only legal mode bits
+ swap tosl ; move to correct location (bits 6-4, atmega32)
+ ori tosl, $80 ; set the SE bit (atmega32: bit 7, not bit 0)
+ out_ MCUCR, tosl ; set the sleep config (atmega32: MCUCR not SMCR)
+ sleep ; nighty-night
+;; the 4 lower bits of MCUCR should not be touched
+ in_ tosl, MCUCR
+ andi tosl, $0F
+ out_ MCUCR, tosl
+ ;clr tosl ; need to clean up the SMCR reg before we leave
+ ;out SMCR, tosl ; 0 protects against accidental sleeps
+ loadtos ; pop argument from stack
+ jmp DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega161/atmega161.frt b/amforth-6.5/avr8/devices/atmega161/atmega161.frt
new file mode 100644
index 0000000..e8d2119
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega161/atmega161.frt
@@ -0,0 +1,121 @@
+\ Partname: ATmega161
+\ Built using part description XML file version 233
+\ generated automatically
+
+hex
+
+\ ANALOG_COMPARATOR
+28 constant ACSR \ Analog Comparator Control And Status Register
+
+\ CPU
+56 constant EMCUCR \ Extended MCU Control Register
+55 constant MCUCR \ MCU Control Register
+54 constant MCUSR \ MCU Status Register
+5E constant SPH \ Stack Pointer High
+5D constant SPL \ Stack Pointer Low
+57 constant SPMCR \ Store Program Memory Control Register
+5F constant SREG \ Status Register
+
+\ EEPROM
+3F constant EEARH \ EEPROM Address Register High Byte
+3E constant EEARL \ EEPROM Address Register Low Byte
+3C constant EECR \ EEPROM Control Register
+3D constant EEDR \ EEPROM Data Register
+
+\ EXTERNAL_INTERRUPT
+5A constant GIFR \ General Interrupt Flag Register
+5B constant GIMSK \ General Interrupt Mask Register
+
+\ PORTA
+3A constant DDRA \ Port A Data Direction Register
+39 constant PINA \ Port A Input Pins
+3B constant PORTA \ Port A Data Register
+
+\ PORTB
+37 constant DDRB \ Port B Data Direction Register
+36 constant PINB \ Port B Input Pins
+38 constant PORTB \ Port B Data Register
+
+\ PORTC
+34 constant DDRC \ Port C Data Direction Register
+33 constant PINC \ Port C Input Pins
+35 constant PORTC \ Port C Data Register
+
+\ PORTD
+31 constant DDRD \ Port D Data Direction Register
+30 constant PIND \ Port D Input Pins
+32 constant PORTD \ Port D Data Register
+
+\ PORTE
+26 constant DDRE \ Port E Data Direction Register
+25 constant PINE \ Port E Input Pins
+27 constant PORTE \ Port E Data Register
+
+\ SPI
+2D constant SPCR \ SPI Control Register
+2F constant SPDR \ SPI Data Register
+2E constant SPSR \ SPI Status Register
+
+\ TIMER_COUNTER_0
+51 constant OCR0 \ Output Compare Register
+50 constant SFIOR \ Special Function IO Register
+53 constant TCCR0 \ Timer/Counter Control Register
+52 constant TCNT0 \ Timer/Counter Register
+58 constant TIFR \ Timer/Counter Interrupt Flag register
+59 constant TIMSK \ Timer/Counter Interrupt Mask Register
+
+\ TIMER_COUNTER_1
+45 constant ICR1H \ Timer/Counter1 Input Capture Register High Byte
+44 constant ICR1L \ Timer/Counter1 Input Capture Register Low Byte
+4B constant OCR1AH \ Timer/Counter1 Output Compare Register High Byte
+4A constant OCR1AL \ Timer/Counter1 Output Compare Register Low Byte
+49 constant OCR1BH \ Timer/Counter1 Output Compare Register High Byte
+48 constant OCR1BL \ Timer/Counter1 Output Compare Register Low Byte
+4F constant TCCR1A \ Timer/Counter1 Control Register A
+4E constant TCCR1B \ Timer/Counter1 Control Register B
+4D constant TCNT1H \ Timer/Counter1 High Byte
+4C constant TCNT1L \ Timer/Counter1 Low Byte
+
+\ TIMER_COUNTER_2
+46 constant ASSR \ Asynchronous Status Register
+42 constant OCR2 \ Timer/Counter2 Output Compare Register
+47 constant TCCR2 \ Timer/Counter2 Control Register
+43 constant TCNT2 \ Timer/Counter2
+
+\ USART0
+29 constant UBRR0 \ USART Baud Rate Register Byte
+40 constant UBRRHI \ High Byte Baud Rate Register
+2B constant UCSR0A \ USART Control and Status Register A
+2A constant UCSR0B \ USART Control and Status Register B
+2C constant UDR0 \ USART I/O Data Register
+
+\ USART1
+20 constant UBRR1 \ USART Baud Rate Register Byte
+22 constant UCSR1A \ USART Control and Status Register A
+21 constant UCSR1B \ USART Control and Status Register B
+23 constant UDR1 \ USART I/O Data Register
+
+\ WATCHDOG
+41 constant WDTCR \ Watchdog Timer Control Register
+
+\ Interrupts
+002 constant INT0Addr \ External Interrupt 0
+004 constant INT1Addr \ External Interrupt 1
+006 constant INT2Addr \ External Interrupt 2
+008 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
+00A constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
+00C constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+00E constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
+010 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
+012 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+014 constant TIMER0_COMPAddr \ Timer/Counter0 Compare Match
+016 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
+018 constant SPISTCAddr \ Serial Transfer Complete
+01A constant UART0RXAddr \ UART0, Rx Complete
+01C constant UART1RXAddr \ UART1, Rx Complete
+01E constant UART0UDREAddr \ UART0 Data Register Empty
+020 constant UART1UDREAddr \ UART1 Data Register Empty
+022 constant UART0TXAddr \ UART0, Tx Complete
+024 constant UART1TXAddr \ UART1, Tx Complete
+026 constant EE_RDYAddr \ EEPROM Ready
+028 constant ANA_COMPAddr \ Analog Comparator
diff --git a/amforth-6.5/avr8/devices/atmega161/device.asm b/amforth-6.5/avr8/devices/atmega161/device.asm
new file mode 100644
index 0000000..6208a6e
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega161/device.asm
@@ -0,0 +1,113 @@
+; Partname: ATmega161
+; Built using part description XML file version 233
+; generated automatically, do not edit
+
+.nolist
+ .include "m161def.inc"
+.list
+
+.equ ramstart = $60
+.equ CELLSIZE = 2
+.macro readflashcell
+ lsl zl
+ rol zh
+ lpm @0, Z+
+ lpm @1, Z+
+.endmacro
+.macro writeflashcell
+ lsl zl
+ rol zh
+.endmacro
+
+; the following definitions are shortcuts for the respective forth source segments if set to 1
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_CPU = 0
+.set WANT_EEPROM = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_PORTA = 0
+.set WANT_PORTB = 0
+.set WANT_PORTC = 0
+.set WANT_PORTD = 0
+.set WANT_PORTE = 0
+.set WANT_SPI = 0
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_TIMER_COUNTER_2 = 0
+.set WANT_USART0 = 0
+.set WANT_USART1 = 0
+.set WANT_WATCHDOG = 0
+
+
+.ifndef SPMEN
+ .equ SPMEN = SELFPRGEN
+.endif
+
+.ifndef SPMCSR
+ .equ SPMCSR = SPMCR
+.endif
+
+.ifndef EEPE
+ .equ EEPE = EEWE
+.endif
+
+.ifndef EEMPE
+ .equ EEMPE = EEMWE
+.endif
+.equ intvecsize = 2 ; please verify; flash size: 16384 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.equ INTVECTORS = 21
+.org $002
+ rcall isr ; External Interrupt 0
+.org $004
+ rcall isr ; External Interrupt 1
+.org $006
+ rcall isr ; External Interrupt 2
+.org $008
+ rcall isr ; Timer/Counter2 Compare Match
+.org $00A
+ rcall isr ; Timer/Counter2 Overflow
+.org $00C
+ rcall isr ; Timer/Counter1 Capture Event
+.org $00E
+ rcall isr ; Timer/Counter1 Compare Match A
+.org $010
+ rcall isr ; Timer/Counter1 Compare Match B
+.org $012
+ rcall isr ; Timer/Counter1 Overflow
+.org $014
+ rcall isr ; Timer/Counter0 Compare Match
+.org $016
+ rcall isr ; Timer/Counter0 Overflow
+.org $018
+ rcall isr ; Serial Transfer Complete
+.org $01A
+ rcall isr ; UART0, Rx Complete
+.org $01C
+ rcall isr ; UART1, Rx Complete
+.org $01E
+ rcall isr ; UART0 Data Register Empty
+.org $020
+ rcall isr ; UART1 Data Register Empty
+.org $022
+ rcall isr ; UART0, Tx Complete
+.org $024
+ rcall isr ; UART1, Tx Complete
+.org $026
+ rcall isr ; EEPROM Ready
+.org $028
+ rcall isr ; Analog Comparator
+.nooverlap
+mcu_info:
+mcu_ramsize:
+ .dw 1024
+mcu_eepromsize:
+ .dw 512
+mcu_maxdp:
+ .dw 0 ; minimum of 0 (from XML) and 0xffff
+mcu_numints:
+ .dw 21
+mcu_name:
+ .dw 9
+ .db "ATmega161",0
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega161/device.inc b/amforth-6.5/avr8/devices/atmega161/device.inc
new file mode 100644
index 0000000..0cedf69
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega161/device.inc
@@ -0,0 +1,843 @@
+; Partname: ATmega161
+; Built using part description XML file version 233
+; generated automatically, no not edit
+
+; ********
+.if WANT_ANALOG_COMPARATOR == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Control And Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw $28
+
+.endif
+
+; ********
+.if WANT_CPU == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Extended MCU Control Register
+VE_EMCUCR:
+ .dw $ff06
+ .db "EMCUCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EMCUCR
+XT_EMCUCR:
+ .dw PFA_DOVARIABLE
+PFA_EMCUCR:
+ .dw $56
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw $55
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Status Register
+VE_MCUSR:
+ .dw $ff05
+ .db "MCUSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUSR
+XT_MCUSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUSR:
+ .dw $54
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer High
+VE_SPH:
+ .dw $ff03
+ .db "SPH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPH
+XT_SPH:
+ .dw PFA_DOVARIABLE
+PFA_SPH:
+ .dw $5E
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer Low
+VE_SPL:
+ .dw $ff03
+ .db "SPL",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPL
+XT_SPL:
+ .dw PFA_DOVARIABLE
+PFA_SPL:
+ .dw $5D
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control Register
+VE_SPMCR:
+ .dw $ff05
+ .db "SPMCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCR
+XT_SPMCR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCR:
+ .dw $57
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw $5F
+
+.endif
+
+; ********
+.if WANT_EEPROM == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Address Register High Byte
+VE_EEARH:
+ .dw $ff05
+ .db "EEARH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEARH
+XT_EEARH:
+ .dw PFA_DOVARIABLE
+PFA_EEARH:
+ .dw $3F
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Address Register Low Byte
+VE_EEARL:
+ .dw $ff05
+ .db "EEARL",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEARL
+XT_EEARL:
+ .dw PFA_DOVARIABLE
+PFA_EEARL:
+ .dw $3E
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw $3C
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw $3D
+
+.endif
+
+; ********
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; General Interrupt Flag Register
+VE_GIFR:
+ .dw $ff04
+ .db "GIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GIFR
+XT_GIFR:
+ .dw PFA_DOVARIABLE
+PFA_GIFR:
+ .dw $5A
+; ( -- addr ) System Constant
+; R( -- )
+; General Interrupt Mask Register
+VE_GIMSK:
+ .dw $ff05
+ .db "GIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GIMSK
+XT_GIMSK:
+ .dw PFA_DOVARIABLE
+PFA_GIMSK:
+ .dw $5B
+
+.endif
+
+; ********
+.if WANT_PORTA == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Direction Register
+VE_DDRA:
+ .dw $ff04
+ .db "DDRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRA
+XT_DDRA:
+ .dw PFA_DOVARIABLE
+PFA_DDRA:
+ .dw $3A
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Input Pins
+VE_PINA:
+ .dw $ff04
+ .db "PINA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINA
+XT_PINA:
+ .dw PFA_DOVARIABLE
+PFA_PINA:
+ .dw $39
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Register
+VE_PORTA:
+ .dw $ff05
+ .db "PORTA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTA
+XT_PORTA:
+ .dw PFA_DOVARIABLE
+PFA_PORTA:
+ .dw $3B
+
+.endif
+
+; ********
+.if WANT_PORTB == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw $37
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw $36
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw $38
+
+.endif
+
+; ********
+.if WANT_PORTC == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Direction Register
+VE_DDRC:
+ .dw $ff04
+ .db "DDRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRC
+XT_DDRC:
+ .dw PFA_DOVARIABLE
+PFA_DDRC:
+ .dw $34
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Input Pins
+VE_PINC:
+ .dw $ff04
+ .db "PINC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINC
+XT_PINC:
+ .dw PFA_DOVARIABLE
+PFA_PINC:
+ .dw $33
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Register
+VE_PORTC:
+ .dw $ff05
+ .db "PORTC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTC
+XT_PORTC:
+ .dw PFA_DOVARIABLE
+PFA_PORTC:
+ .dw $35
+
+.endif
+
+; ********
+.if WANT_PORTD == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw $31
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw $30
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw $32
+
+.endif
+
+; ********
+.if WANT_PORTE == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Port E Data Direction Register
+VE_DDRE:
+ .dw $ff04
+ .db "DDRE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRE
+XT_DDRE:
+ .dw PFA_DOVARIABLE
+PFA_DDRE:
+ .dw $26
+; ( -- addr ) System Constant
+; R( -- )
+; Port E Input Pins
+VE_PINE:
+ .dw $ff04
+ .db "PINE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINE
+XT_PINE:
+ .dw PFA_DOVARIABLE
+PFA_PINE:
+ .dw $25
+; ( -- addr ) System Constant
+; R( -- )
+; Port E Data Register
+VE_PORTE:
+ .dw $ff05
+ .db "PORTE",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTE
+XT_PORTE:
+ .dw PFA_DOVARIABLE
+PFA_PORTE:
+ .dw $27
+
+.endif
+
+; ********
+.if WANT_SPI == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR:
+ .dw $ff04
+ .db "SPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR
+XT_SPCR:
+ .dw PFA_DOVARIABLE
+PFA_SPCR:
+ .dw $2D
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR:
+ .dw $ff04
+ .db "SPDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR
+XT_SPDR:
+ .dw PFA_DOVARIABLE
+PFA_SPDR:
+ .dw $2F
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR:
+ .dw $ff04
+ .db "SPSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR
+XT_SPSR:
+ .dw PFA_DOVARIABLE
+PFA_SPSR:
+ .dw $2E
+
+.endif
+
+; ********
+.if WANT_TIMER_COUNTER_0 == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare Register
+VE_OCR0:
+ .dw $ff04
+ .db "OCR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0
+XT_OCR0:
+ .dw PFA_DOVARIABLE
+PFA_OCR0:
+ .dw $51
+; ( -- addr ) System Constant
+; R( -- )
+; Special Function IO Register
+VE_SFIOR:
+ .dw $ff05
+ .db "SFIOR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SFIOR
+XT_SFIOR:
+ .dw PFA_DOVARIABLE
+PFA_SFIOR:
+ .dw $50
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register
+VE_TCCR0:
+ .dw $ff05
+ .db "TCCR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0
+XT_TCCR0:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0:
+ .dw $53
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Register
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw $52
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Flag register
+VE_TIFR:
+ .dw $ff04
+ .db "TIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR
+XT_TIFR:
+ .dw PFA_DOVARIABLE
+PFA_TIFR:
+ .dw $58
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Mask Register
+VE_TIMSK:
+ .dw $ff05
+ .db "TIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK
+XT_TIMSK:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK:
+ .dw $59
+
+.endif
+
+; ********
+.if WANT_TIMER_COUNTER_1 == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register High Byte
+VE_ICR1H:
+ .dw $ff05
+ .db "ICR1H",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1H
+XT_ICR1H:
+ .dw PFA_DOVARIABLE
+PFA_ICR1H:
+ .dw $45
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Low Byte
+VE_ICR1L:
+ .dw $ff05
+ .db "ICR1L",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1L
+XT_ICR1L:
+ .dw PFA_DOVARIABLE
+PFA_ICR1L:
+ .dw $44
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register High Byte
+VE_OCR1AH:
+ .dw $ff06
+ .db "OCR1AH"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1AH
+XT_OCR1AH:
+ .dw PFA_DOVARIABLE
+PFA_OCR1AH:
+ .dw $4B
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register Low Byte
+VE_OCR1AL:
+ .dw $ff06
+ .db "OCR1AL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1AL
+XT_OCR1AL:
+ .dw PFA_DOVARIABLE
+PFA_OCR1AL:
+ .dw $4A
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register High Byte
+VE_OCR1BH:
+ .dw $ff06
+ .db "OCR1BH"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1BH
+XT_OCR1BH:
+ .dw PFA_DOVARIABLE
+PFA_OCR1BH:
+ .dw $49
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register Low Byte
+VE_OCR1BL:
+ .dw $ff06
+ .db "OCR1BL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1BL
+XT_OCR1BL:
+ .dw PFA_DOVARIABLE
+PFA_OCR1BL:
+ .dw $48
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw $4F
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw $4E
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 High Byte
+VE_TCNT1H:
+ .dw $ff06
+ .db "TCNT1H"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1H
+XT_TCNT1H:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1H:
+ .dw $4D
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Low Byte
+VE_TCNT1L:
+ .dw $ff06
+ .db "TCNT1L"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1L
+XT_TCNT1L:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1L:
+ .dw $4C
+
+.endif
+
+; ********
+.if WANT_TIMER_COUNTER_2 == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Asynchronous Status Register
+VE_ASSR:
+ .dw $ff04
+ .db "ASSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ASSR
+XT_ASSR:
+ .dw PFA_DOVARIABLE
+PFA_ASSR:
+ .dw $46
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register
+VE_OCR2:
+ .dw $ff04
+ .db "OCR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2
+XT_OCR2:
+ .dw PFA_DOVARIABLE
+PFA_OCR2:
+ .dw $42
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register
+VE_TCCR2:
+ .dw $ff05
+ .db "TCCR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2
+XT_TCCR2:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2:
+ .dw $47
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2
+VE_TCNT2:
+ .dw $ff05
+ .db "TCNT2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT2
+XT_TCNT2:
+ .dw PFA_DOVARIABLE
+PFA_TCNT2:
+ .dw $43
+
+.endif
+
+; ********
+.if WANT_USART0 == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Byte
+VE_UBRR0:
+ .dw $ff05
+ .db "UBRR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR0
+XT_UBRR0:
+ .dw PFA_DOVARIABLE
+PFA_UBRR0:
+ .dw $29
+; ( -- addr ) System Constant
+; R( -- )
+; High Byte Baud Rate Register
+VE_UBRRHI:
+ .dw $ff06
+ .db "UBRRHI"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRRHI
+XT_UBRRHI:
+ .dw PFA_DOVARIABLE
+PFA_UBRRHI:
+ .dw $40
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR0A:
+ .dw $ff06
+ .db "UCSR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0A
+XT_UCSR0A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0A:
+ .dw $2B
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR0B:
+ .dw $ff06
+ .db "UCSR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0B
+XT_UCSR0B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0B:
+ .dw $2A
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR0:
+ .dw $ff04
+ .db "UDR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR0
+XT_UDR0:
+ .dw PFA_DOVARIABLE
+PFA_UDR0:
+ .dw $2C
+
+.endif
+
+; ********
+.if WANT_USART1 == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Byte
+VE_UBRR1:
+ .dw $ff05
+ .db "UBRR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR1
+XT_UBRR1:
+ .dw PFA_DOVARIABLE
+PFA_UBRR1:
+ .dw $20
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR1A:
+ .dw $ff06
+ .db "UCSR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1A
+XT_UCSR1A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1A:
+ .dw $22
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR1B:
+ .dw $ff06
+ .db "UCSR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1B
+XT_UCSR1B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1B:
+ .dw $21
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR1:
+ .dw $ff04
+ .db "UDR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR1
+XT_UDR1:
+ .dw PFA_DOVARIABLE
+PFA_UDR1:
+ .dw $23
+
+.endif
+
+; ********
+.if WANT_WATCHDOG == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCR:
+ .dw $ff05
+ .db "WDTCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCR
+XT_WDTCR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCR:
+ .dw $41
+
+.endif
diff --git a/amforth-6.5/avr8/devices/atmega161/device.py b/amforth-6.5/avr8/devices/atmega161/device.py
new file mode 100644
index 0000000..3f30afc
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega161/device.py
@@ -0,0 +1,87 @@
+# Partname: ATmega161
+# Built using part description XML file version 233
+# generated automatically, do not edit
+MCUREGS = {
+ 'ACSR': '$28',
+ 'EMCUCR': '$56',
+ 'MCUCR': '$55',
+ 'MCUSR': '$54',
+ 'SPH': '$5E',
+ 'SPL': '$5D',
+ 'SPMCR': '$57',
+ 'SREG': '$5F',
+ 'EEARH': '$3F',
+ 'EEARL': '$3E',
+ 'EECR': '$3C',
+ 'EEDR': '$3D',
+ 'GIFR': '$5A',
+ 'GIMSK': '$5B',
+ 'DDRA': '$3A',
+ 'PINA': '$39',
+ 'PORTA': '$3B',
+ 'DDRB': '$37',
+ 'PINB': '$36',
+ 'PORTB': '$38',
+ 'DDRC': '$34',
+ 'PINC': '$33',
+ 'PORTC': '$35',
+ 'DDRD': '$31',
+ 'PIND': '$30',
+ 'PORTD': '$32',
+ 'DDRE': '$26',
+ 'PINE': '$25',
+ 'PORTE': '$27',
+ 'SPCR': '$2D',
+ 'SPDR': '$2F',
+ 'SPSR': '$2E',
+ 'OCR0': '$51',
+ 'SFIOR': '$50',
+ 'TCCR0': '$53',
+ 'TCNT0': '$52',
+ 'TIFR': '$58',
+ 'TIMSK': '$59',
+ 'ICR1H': '$45',
+ 'ICR1L': '$44',
+ 'OCR1AH': '$4B',
+ 'OCR1AL': '$4A',
+ 'OCR1BH': '$49',
+ 'OCR1BL': '$48',
+ 'TCCR1A': '$4F',
+ 'TCCR1B': '$4E',
+ 'TCNT1H': '$4D',
+ 'TCNT1L': '$4C',
+ 'ASSR': '$46',
+ 'OCR2': '$42',
+ 'TCCR2': '$47',
+ 'TCNT2': '$43',
+ 'UBRR0': '$29',
+ 'UBRRHI': '$40',
+ 'UCSR0A': '$2B',
+ 'UCSR0B': '$2A',
+ 'UDR0': '$2C',
+ 'UBRR1': '$20',
+ 'UCSR1A': '$22',
+ 'UCSR1B': '$21',
+ 'UDR1': '$23',
+ 'WDTCR': '$41',
+ 'INT0Addr': '$002',
+ 'INT1Addr': '$004',
+ 'INT2Addr': '$006',
+ 'TIMER2_COMPAddr': '$008',
+ 'TIMER2_OVFAddr': '$00A',
+ 'TIMER1_CAPTAddr': '$00C',
+ 'TIMER1_COMPAAddr': '$00E',
+ 'TIMER1_COMPBAddr': '$010',
+ 'TIMER1_OVFAddr': '$012',
+ 'TIMER0_COMPAddr': '$014',
+ 'TIMER0_OVFAddr': '$016',
+ 'SPISTCAddr': '$018',
+ 'UART0RXAddr': '$01A',
+ 'UART1RXAddr': '$01C',
+ 'UART0UDREAddr': '$01E',
+ 'UART1UDREAddr': '$020',
+ 'UART0TXAddr': '$022',
+ 'UART1TXAddr': '$024',
+ 'EE_RDYAddr': '$026',
+ 'ANA_COMPAddr': '$028'
+} \ No newline at end of file
diff --git a/amforth-6.5/avr8/devices/atmega162/atmega162.frt b/amforth-6.5/avr8/devices/atmega162/atmega162.frt
new file mode 100644
index 0000000..e656277
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega162/atmega162.frt
@@ -0,0 +1,289 @@
+\ Partname: ATmega162
+\ generated automatically
+
+\ TIMER_COUNTER_1
+&89 constant TIMSK \ Timer/Counter Interrupt Mask Register
+ $80 constant TIMSK_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
+ $40 constant TIMSK_OCIE1A \ Timer/Counter1 Output CompareA Match Interrupt Enable
+ $20 constant TIMSK_OCIE1B \ Timer/Counter1 Output CompareB Match Interrupt Enable
+ $08 constant TIMSK_TICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
+&88 constant TIFR \ Timer/Counter Interrupt Flag register
+ $80 constant TIFR_TOV1 \ Timer/Counter1 Overflow Flag
+ $40 constant TIFR_OCF1A \ Output Compare Flag 1A
+ $20 constant TIFR_OCF1B \ Output Compare Flag 1B
+ $08 constant TIFR_ICF1 \ Input Capture Flag 1
+&79 constant TCCR1A \ Timer/Counter1 Control Register A
+ $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
+ $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
+ $08 constant TCCR1A_FOC1A \ Force Output Compare for Channel A
+ $04 constant TCCR1A_FOC1B \ Force Output Compare for Channel B
+ $03 constant TCCR1A_WGM1 \ Pulse Width Modulator Select Bits
+&78 constant TCCR1B \ Timer/Counter1 Control Register B
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ $18 constant TCCR1B_WGM1 \ Pulse Width Modulator Select Bits
+ $07 constant TCCR1B_CS1 \ Clock Select1 bits
+&76 constant TCNT1 \ Timer/Counter1 Bytes
+&74 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
+&72 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
+&68 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
+\ TIMER_COUNTER_2
+&71 constant TCCR2 \ Timer/Counter Control Register
+ $80 constant TCCR2_FOC2 \ Forde Output Compare
+ $40 constant TCCR2_WGM20 \ Pulse Width Modulator Select Bit 0
+ $30 constant TCCR2_COM2 \ Compare Match Output Mode
+ $08 constant TCCR2_WGM21 \ Pulse Width Modulator Select Bit 1
+ $07 constant TCCR2_CS2 \ Clock Select
+&67 constant TCNT2 \ Timer/Counter Register
+&66 constant OCR2 \ Output Compare Register
+&70 constant ASSR \ Asynchronous Status Register
+ $08 constant ASSR_AS2 \ Asynchronous Timer 2
+ $04 constant ASSR_TCN2UB \ Timer/Counter2 Update Busy
+ $02 constant ASSR_OCR2UB \ Output Compare Register2 Update Busy
+ $01 constant ASSR_TCR2UB \ Timer/Counter Control Register2 Update Busy
+\ TIMER_COUNTER_3
+&125 constant ETIMSK \ Extended Timer/Counter Interrupt Mask Register
+ $20 constant ETIMSK_TICIE3 \ Timer/Counter3 Input Capture Interrupt Enable
+ $10 constant ETIMSK_OCIE3A \ Timer/Counter3 Output CompareA Match Interrupt Enable
+ $08 constant ETIMSK_OCIE3B \ Timer/Counter3 Output CompareB Match Interrupt Enable
+ $04 constant ETIMSK_TOIE3 \ Timer/Counter3 Overflow Interrupt Enable
+&124 constant ETIFR \ Extended Timer/Counter Interrupt Flag register
+ $20 constant ETIFR_ICF3 \ Input Capture Flag 3
+ $10 constant ETIFR_OCF3A \ Output Compare Flag 3A
+ $08 constant ETIFR_OCF3B \ Output Compare Flag 3B
+ $04 constant ETIFR_TOV3 \ Timer/Counter3 Overflow Flag
+&139 constant TCCR3A \ Timer/Counter3 Control Register A
+ $C0 constant TCCR3A_COM3A \ Compare Output Mode 3A, bits
+ $30 constant TCCR3A_COM3B \ Compare Output Mode 3B, bits
+ $08 constant TCCR3A_FOC3A \ Force Output Compare for Channel A
+ $04 constant TCCR3A_FOC3B \ Force Output Compare for Channel B
+ $03 constant TCCR3A_WGM3 \ Pulse Width Modulator Select Bits
+&138 constant TCCR3B \ Timer/Counter3 Control Register B
+ $80 constant TCCR3B_ICNC3 \ Input Capture 3 Noise Canceler
+ $40 constant TCCR3B_ICES3 \ Input Capture 3 Edge Select
+ $18 constant TCCR3B_WGM3 \ Pulse Width Modulator Select Bits
+ $07 constant TCCR3B_CS3 \ Clock Select3 bits
+&136 constant TCNT3 \ Timer/Counter3 Bytes
+&134 constant OCR3A \ Timer/Counter3 Output Compare Register A Bytes
+&132 constant OCR3B \ Timer/Counte3 Output Compare Register B Bytes
+&128 constant ICR3 \ Timer/Counter3 Input Capture Register Bytes
+\ ANALOG_COMPARATOR
+&40 constant ACSR \ Analog Comparator Control And Status Register
+ $80 constant ACSR_ACD \ Analog Comparator Disable
+ $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
+ $20 constant ACSR_ACO \ Analog Compare Output
+ $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
+ $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
+ $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
+ $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
+\ USART0
+&44 constant UDR0 \ USART I/O Data Register
+&43 constant UCSR0A \ USART Control and Status Register A
+ $80 constant UCSR0A_RXC0 \ USART Receive Complete
+ $40 constant UCSR0A_TXC0 \ USART Transmitt Complete
+ $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
+ $10 constant UCSR0A_FE0 \ Framing Error
+ $08 constant UCSR0A_DOR0 \ Data overRun
+ $04 constant UCSR0A_UPE0 \ Parity Error
+ $02 constant UCSR0A_U2X0 \ Double the USART transmission speed
+ $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
+&42 constant UCSR0B \ USART Control and Status Register B
+ $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
+ $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
+ $20 constant UCSR0B_UDRIE0 \ USART Data register Empty Interrupt Enable
+ $10 constant UCSR0B_RXEN0 \ Receiver Enable
+ $08 constant UCSR0B_TXEN0 \ Transmitter Enable
+ $04 constant UCSR0B_UCSZ02 \ Character Size
+ $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
+ $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
+&64 constant UCSR0C \ USART Control and Status Register C
+ $80 constant UCSR0C_URSEL0 \ Register Select
+ $40 constant UCSR0C_UMSEL0 \ USART Mode Select
+ $30 constant UCSR0C_UPM0 \ Parity Mode Bits
+ $08 constant UCSR0C_USBS0 \ Stop Bit Select
+ $06 constant UCSR0C_UCSZ0 \ Character Size
+ $01 constant UCSR0C_UCPOL0 \ Clock Polarity
+&64 constant UBRR0H \ USART Baud Rate Register Hight Byte
+&41 constant UBRR0L \ USART Baud Rate Register Low Byte
+\ USART1
+&35 constant UDR \ USART I/O Data Register
+&34 constant UCSR1A \ USART Control and Status Register A
+ $80 constant UCSR1A_RXC1 \ USART Receive Complete
+ $40 constant UCSR1A_TXC1 \ USART Transmitt Complete
+ $20 constant UCSR1A_UDRE1 \ USART Data Register Empty
+ $10 constant UCSR1A_FE1 \ Framing Error
+ $08 constant UCSR1A_DOR1 \ Data overRun
+ $04 constant UCSR1A_UPE1 \ Parity Error
+ $02 constant UCSR1A_U2X1 \ Double the USART transmission speed
+ $01 constant UCSR1A_MPCM1 \ Multi-processor Communication Mode
+&33 constant UCSR1B \ USART Control and Status Register B
+ $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable
+ $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable
+ $20 constant UCSR1B_UDRIE1 \ USART Data register Empty Interrupt Enable
+ $10 constant UCSR1B_RXEN1 \ Receiver Enable
+ $08 constant UCSR1B_TXEN1 \ Transmitter Enable
+ $04 constant UCSR1B_UCSZ12 \ Character Size
+ $02 constant UCSR1B_RXB81 \ Receive Data Bit 8
+ $01 constant UCSR1B_TXB81 \ Transmit Data Bit 8
+&92 constant UCSR1C \ USART Control and Status Register C
+ $80 constant UCSR1C_URSEL1 \ Register Select
+ $40 constant UCSR1C_UMSEL1 \ USART Mode Select
+ $30 constant UCSR1C_UPM1 \ Parity Mode Bits
+ $08 constant UCSR1C_USBS1 \ Stop Bit Select
+ $06 constant UCSR1C_UCSZ1 \ Character Size
+ $01 constant UCSR1C_UCPOL1 \ Clock Polarity
+&92 constant UBRR1H \ USART Baud Rate Register Highg Byte
+&32 constant UBRR1L \ USART Baud Rate Register Low Byte
+\ SPI
+&45 constant SPCR \ SPI Control Register
+ $80 constant SPCR_SPIE \ SPI Interrupt Enable
+ $40 constant SPCR_SPE \ SPI Enable
+ $20 constant SPCR_DORD \ Data Order
+ $10 constant SPCR_MSTR \ Master/Slave Select
+ $08 constant SPCR_CPOL \ Clock polarity
+ $04 constant SPCR_CPHA \ Clock Phase
+ $03 constant SPCR_SPR \ SPI Clock Rate Selects
+&46 constant SPSR \ SPI Status Register
+ $80 constant SPSR_SPIF \ SPI Interrupt Flag
+ $40 constant SPSR_WCOL \ Write Collision Flag
+ $01 constant SPSR_SPI2X \ Double SPI Speed Bit
+&47 constant SPDR \ SPI Data Register
+\ CPU
+&95 constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ $08 constant SREG_V \ Two's Complement Overflow Flag
+ $04 constant SREG_N \ Negative Flag
+ $02 constant SREG_Z \ Zero Flag
+ $01 constant SREG_C \ Carry Flag
+&93 constant SP \ Stack Pointer
+&85 constant MCUCR \ MCU Control Register
+ $80 constant MCUCR_SRE \ External SRAM Enable
+ $40 constant MCUCR_SRW10 \ External SRAM Wait State Select
+ $20 constant MCUCR_SE \ Sleep Enable
+ $10 constant MCUCR_SM1 \ Sleep Mode Select
+ $0C constant MCUCR_ISC1 \ Interrupt Sense Control 1 bits
+ $03 constant MCUCR_ISC0 \ Interrupt Sense Control 0 bits
+&84 constant MCUCSR \ MCU Control And Status Register
+ $80 constant MCUCSR_JDT \ JTAG Interface Disable
+ $20 constant MCUCSR_SM2 \ Sleep Mode Select Bit 2
+ $10 constant MCUCSR_JTRF \ JTAG Reset Flag
+ $08 constant MCUCSR_WDRF \ Watchdog Reset Flag
+ $04 constant MCUCSR_BORF \ Brown-out Reset Flag
+ $02 constant MCUCSR_EXTRF \ External Reset Flag
+ $01 constant MCUCSR_PORF \ Power-on reset flag
+&86 constant EMCUCR \ Extended MCU Control Register
+ $80 constant EMCUCR_SM0 \ Sleep mode Select Bit 0
+ $70 constant EMCUCR_SRL \ Wait State Sector Limit Bits
+ $0C constant EMCUCR_SRW0 \ Wait State Select Bit 1 for Lower Sector
+ $02 constant EMCUCR_SRW11 \ Wait State Select Bit 1 for Upper Sector
+ $01 constant EMCUCR_ISC2 \ Interrupt Sense Control 2
+&36 constant OSCCAL \ Oscillator Calibration Value
+&97 constant CLKPR \ Clock prescale register
+ $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable
+ $0F constant CLKPR_CLKPS \ Clock Prescaler Select Bits
+&80 constant SFIOR \ Special Function IO Register
+ $80 constant SFIOR_TSM \ Timer/Counter Synchronization Mode
+ $40 constant SFIOR_XMBK \ External Memory Bus Keeper Enable
+ $38 constant SFIOR_XMM \ External Memory High Mask Bits
+ $04 constant SFIOR_PUD \ Pull-up Disable
+ $02 constant SFIOR_PSR2 \ Prescaler Reset Timer/Counter2
+ $01 constant SFIOR_PSR310 \ Prescaler Reset Timer/Counter3, Timer/Counter1 and Timer/Counter0
+\ JTAG
+&36 constant OCDR \ On-Chip Debug Related Register in I/O Memory
+ $FF constant OCDR_OCDR \ On-Chip Debug Register Bits
+\ BOOT_LOAD
+&87 constant SPMCR \ Store Program Memory Control Register
+ $80 constant SPMCR_SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCR_RWWSB \ Read While Write Section Busy
+ $10 constant SPMCR_RWWSRE \ Read While Write secion read enable
+ $08 constant SPMCR_BLBSET \ Boot Lock Bit Set
+ $04 constant SPMCR_PGWRT \ Page Write
+ $02 constant SPMCR_PGERS \ Page Erase
+ $01 constant SPMCR_SPMEN \ Store Program Memory Enable
+\ EEPROM
+&62 constant EEAR \ EEPROM Address Register Bytes
+&61 constant EEDR \ EEPROM Data Register
+&60 constant EECR \ EEPROM Control Register
+ $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
+ $04 constant EECR_EEMWE \ EEPROM Master Write Enable
+ $02 constant EECR_EEWE \ EEPROM Write Enable
+ $01 constant EECR_EERE \ EEPROM Read Enable
+\ PORTA
+&59 constant PORTA \ Port A Data Register
+&58 constant DDRA \ Port A Data Direction Register
+&57 constant PINA \ Port A Input Pins
+\ PORTB
+&56 constant PORTB \ Port B Data Register
+&55 constant DDRB \ Port B Data Direction Register
+&54 constant PINB \ Port B Input Pins
+\ PORTC
+&53 constant PORTC \ Port C Data Register
+&52 constant DDRC \ Port C Data Direction Register
+&51 constant PINC \ Port C Input Pins
+\ PORTD
+&50 constant PORTD \ Port D Data Register
+&49 constant DDRD \ Port D Data Direction Register
+&48 constant PIND \ Port D Input Pins
+\ TIMER_COUNTER_0
+&83 constant TCCR0 \ Timer/Counter 0 Control Register
+ $80 constant TCCR0_FOC0 \ Force Output Compare
+ $40 constant TCCR0_WGM00 \ Waveform Generation Mode 0
+ $30 constant TCCR0_COM0 \ Compare Match Output Modes
+ $08 constant TCCR0_WGM01 \ Waveform Generation Mode 1
+ $07 constant TCCR0_CS0 \ Clock Selects
+&82 constant TCNT0 \ Timer/Counter 0 Register
+&81 constant OCR0 \ Timer/Counter 0 Output Compare Register
+\ WATCHDOG
+&65 constant WDTCR \ Watchdog Timer Control Register
+ $10 constant WDTCR_WDCE \ Watchdog Change Enable
+ $08 constant WDTCR_WDE \ Watch Dog Enable
+ $07 constant WDTCR_WDP \ Watch Dog Timer Prescaler bits
+\ PORTE
+&39 constant PORTE \ Data Register, Port E
+&38 constant DDRE \ Data Direction Register, Port E
+&37 constant PINE \ Input Pins, Port E
+\ EXTERNAL_INTERRUPT
+&91 constant GICR \ General Interrupt Control Register
+ $C0 constant GICR_INT \ External Interrupt Request 1 Enable
+ $20 constant GICR_INT2 \ External Interrupt Request 2 Enable
+ $18 constant GICR_PCIE \ Pin Change Interrupt Enables
+ $02 constant GICR_IVSEL \ Interrupt Vector Select
+ $01 constant GICR_IVCE \ Interrupt Vector Change Enable
+&90 constant GIFR \ General Interrupt Flag Register
+ $C0 constant GIFR_INTF \ External Interrupt Flags
+ $20 constant GIFR_INTF2 \ External Interrupt Flag 2
+ $18 constant GIFR_PCIF \ Pin Change Interrupt Flags
+&108 constant PCMSK1 \ Pin Change Mask Register 1
+&107 constant PCMSK0 \ Pin Change Enable Mask
+
+\ Interrupts
+&2 constant INT0Addr \ External Interrupt Request 0
+&4 constant INT1Addr \ External Interrupt Request 1
+&6 constant INT2Addr \ External Interrupt Request 2
+&8 constant PCINT0Addr \ Pin Change Interrupt Request 0
+&10 constant PCINT1Addr \ Pin Change Interrupt Request 1
+&12 constant TIMER3_CAPTAddr \ Timer/Counter3 Capture Event
+&14 constant TIMER3_COMPAAddr \ Timer/Counter3 Compare Match A
+&16 constant TIMER3_COMPBAddr \ Timer/Counter3 Compare Match B
+&18 constant TIMER3_OVFAddr \ Timer/Counter3 Overflow
+&20 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
+&22 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
+&24 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+&26 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
+&28 constant TIMER1_COMPBAddr \ Timer/Counter Compare Match B
+&30 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+&32 constant TIMER0_COMPAddr \ Timer/Counter0 Compare Match
+&34 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
+&36 constant SPI__STCAddr \ SPI Serial Transfer Complete
+&38 constant USART0__RXCAddr \ USART0, Rx Complete
+&40 constant USART1__RXCAddr \ USART1, Rx Complete
+&42 constant USART0__UDREAddr \ USART0 Data register Empty
+&44 constant USART1__UDREAddr \ USART1, Data register Empty
+&46 constant USART0__TXCAddr \ USART0, Tx Complete
+&48 constant USART1__TXCAddr \ USART1, Tx Complete
+&50 constant EE_RDYAddr \ EEPROM Ready
+&52 constant ANA_COMPAddr \ Analog Comparator
+&54 constant SPM_RDYAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/atmega162/device.asm b/amforth-6.5/avr8/devices/atmega162/device.asm
new file mode 100644
index 0000000..b61f439
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega162/device.asm
@@ -0,0 +1,117 @@
+; Partname: ATmega162
+; generated automatically, do not edit
+
+.nolist
+ .include "m162def.inc"
+.list
+
+.equ ramstart = 256
+.equ CELLSIZE = 2
+.macro readflashcell
+ lsl zl
+ rol zh
+ lpm @0, Z+
+ lpm @1, Z+
+.endmacro
+.macro writeflashcell
+ lsl zl
+ rol zh
+.endmacro
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_TIMER_COUNTER_2 = 0
+.set WANT_TIMER_COUNTER_3 = 0
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_USART0 = 0
+.set WANT_USART1 = 0
+.set WANT_SPI = 0
+.set WANT_CPU = 0
+.set WANT_JTAG = 0
+.set WANT_BOOT_LOAD = 0
+.set WANT_EEPROM = 0
+.set WANT_PORTA = 0
+.set WANT_PORTB = 0
+.set WANT_PORTC = 0
+.set WANT_PORTD = 0
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_WATCHDOG = 0
+.set WANT_PORTE = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.equ intvecsize = 2 ; please verify; flash size: 16384 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.org 2
+ rcall isr ; External Interrupt Request 0
+.org 4
+ rcall isr ; External Interrupt Request 1
+.org 6
+ rcall isr ; External Interrupt Request 2
+.org 8
+ rcall isr ; Pin Change Interrupt Request 0
+.org 10
+ rcall isr ; Pin Change Interrupt Request 1
+.org 12
+ rcall isr ; Timer/Counter3 Capture Event
+.org 14
+ rcall isr ; Timer/Counter3 Compare Match A
+.org 16
+ rcall isr ; Timer/Counter3 Compare Match B
+.org 18
+ rcall isr ; Timer/Counter3 Overflow
+.org 20
+ rcall isr ; Timer/Counter2 Compare Match
+.org 22
+ rcall isr ; Timer/Counter2 Overflow
+.org 24
+ rcall isr ; Timer/Counter1 Capture Event
+.org 26
+ rcall isr ; Timer/Counter1 Compare Match A
+.org 28
+ rcall isr ; Timer/Counter Compare Match B
+.org 30
+ rcall isr ; Timer/Counter1 Overflow
+.org 32
+ rcall isr ; Timer/Counter0 Compare Match
+.org 34
+ rcall isr ; Timer/Counter0 Overflow
+.org 36
+ rcall isr ; SPI Serial Transfer Complete
+.org 38
+ rcall isr ; USART0, Rx Complete
+.org 40
+ rcall isr ; USART1, Rx Complete
+.org 42
+ rcall isr ; USART0 Data register Empty
+.org 44
+ rcall isr ; USART1, Data register Empty
+.org 46
+ rcall isr ; USART0, Tx Complete
+.org 48
+ rcall isr ; USART1, Tx Complete
+.org 50
+ rcall isr ; EEPROM Ready
+.org 52
+ rcall isr ; Analog Comparator
+.org 54
+ rcall isr ; Store Program Memory Read
+.equ INTVECTORS = 28
+.nooverlap
+
+; compatability layer (maybe empty)
+.equ SPMCSR = SPMCR
+.equ EEPE = EEWE
+.equ EEMPE = EEMWE
+
+; controller data area, environment query mcu-info
+mcu_info:
+mcu_ramsize:
+ .dw 1024
+mcu_eepromsize:
+ .dw 512
+mcu_maxdp:
+ .dw 14336
+mcu_numints:
+ .dw 28
+mcu_name:
+ .dw 9
+ .db "ATmega162",0
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega162/device.inc b/amforth-6.5/avr8/devices/atmega162/device.inc
new file mode 100644
index 0000000..8d0e695
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega162/device.inc
@@ -0,0 +1,924 @@
+; Partname: ATmega162
+; generated automatically, no not edit
+
+.if WANT_TIMER_COUNTER_1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Mask Register
+VE_TIMSK:
+ .dw $ff05
+ .db "TIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK
+XT_TIMSK:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK:
+ .dw 89
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Flag register
+VE_TIFR:
+ .dw $ff04
+ .db "TIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR
+XT_TIFR:
+ .dw PFA_DOVARIABLE
+PFA_TIFR:
+ .dw 88
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw 79
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw 78
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Bytes
+VE_TCNT1:
+ .dw $ff05
+ .db "TCNT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1
+XT_TCNT1:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1:
+ .dw 76
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register A Bytes
+VE_OCR1A:
+ .dw $ff05
+ .db "OCR1A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1A
+XT_OCR1A:
+ .dw PFA_DOVARIABLE
+PFA_OCR1A:
+ .dw 74
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register B Bytes
+VE_OCR1B:
+ .dw $ff05
+ .db "OCR1B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1B
+XT_OCR1B:
+ .dw PFA_DOVARIABLE
+PFA_OCR1B:
+ .dw 72
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Bytes
+VE_ICR1:
+ .dw $ff04
+ .db "ICR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1
+XT_ICR1:
+ .dw PFA_DOVARIABLE
+PFA_ICR1:
+ .dw 68
+
+.endif
+.if WANT_TIMER_COUNTER_2 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register
+VE_TCCR2:
+ .dw $ff05
+ .db "TCCR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2
+XT_TCCR2:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2:
+ .dw 71
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Register
+VE_TCNT2:
+ .dw $ff05
+ .db "TCNT2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT2
+XT_TCNT2:
+ .dw PFA_DOVARIABLE
+PFA_TCNT2:
+ .dw 67
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare Register
+VE_OCR2:
+ .dw $ff04
+ .db "OCR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2
+XT_OCR2:
+ .dw PFA_DOVARIABLE
+PFA_OCR2:
+ .dw 66
+; ( -- addr ) System Constant
+; R( -- )
+; Asynchronous Status Register
+VE_ASSR:
+ .dw $ff04
+ .db "ASSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ASSR
+XT_ASSR:
+ .dw PFA_DOVARIABLE
+PFA_ASSR:
+ .dw 70
+
+.endif
+.if WANT_TIMER_COUNTER_3 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Extended Timer/Counter Interrupt Mask Register
+VE_ETIMSK:
+ .dw $ff06
+ .db "ETIMSK"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ETIMSK
+XT_ETIMSK:
+ .dw PFA_DOVARIABLE
+PFA_ETIMSK:
+ .dw 125
+; ( -- addr ) System Constant
+; R( -- )
+; Extended Timer/Counter Interrupt Flag register
+VE_ETIFR:
+ .dw $ff05
+ .db "ETIFR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ETIFR
+XT_ETIFR:
+ .dw PFA_DOVARIABLE
+PFA_ETIFR:
+ .dw 124
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Control Register A
+VE_TCCR3A:
+ .dw $ff06
+ .db "TCCR3A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR3A
+XT_TCCR3A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR3A:
+ .dw 139
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Control Register B
+VE_TCCR3B:
+ .dw $ff06
+ .db "TCCR3B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR3B
+XT_TCCR3B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR3B:
+ .dw 138
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Bytes
+VE_TCNT3:
+ .dw $ff05
+ .db "TCNT3",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT3
+XT_TCNT3:
+ .dw PFA_DOVARIABLE
+PFA_TCNT3:
+ .dw 136
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Output Compare Register A Bytes
+VE_OCR3A:
+ .dw $ff05
+ .db "OCR3A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR3A
+XT_OCR3A:
+ .dw PFA_DOVARIABLE
+PFA_OCR3A:
+ .dw 134
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counte3 Output Compare Register B Bytes
+VE_OCR3B:
+ .dw $ff05
+ .db "OCR3B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR3B
+XT_OCR3B:
+ .dw PFA_DOVARIABLE
+PFA_OCR3B:
+ .dw 132
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Input Capture Register Bytes
+VE_ICR3:
+ .dw $ff04
+ .db "ICR3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR3
+XT_ICR3:
+ .dw PFA_DOVARIABLE
+PFA_ICR3:
+ .dw 128
+
+.endif
+.if WANT_ANALOG_COMPARATOR == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Control And Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw 40
+
+.endif
+.if WANT_USART0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR0:
+ .dw $ff04
+ .db "UDR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR0
+XT_UDR0:
+ .dw PFA_DOVARIABLE
+PFA_UDR0:
+ .dw 44
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR0A:
+ .dw $ff06
+ .db "UCSR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0A
+XT_UCSR0A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0A:
+ .dw 43
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR0B:
+ .dw $ff06
+ .db "UCSR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0B
+XT_UCSR0B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0B:
+ .dw 42
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR0C:
+ .dw $ff06
+ .db "UCSR0C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0C
+XT_UCSR0C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0C:
+ .dw 64
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Hight Byte
+VE_UBRR0H:
+ .dw $ff06
+ .db "UBRR0H"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR0H
+XT_UBRR0H:
+ .dw PFA_DOVARIABLE
+PFA_UBRR0H:
+ .dw 64
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Low Byte
+VE_UBRR0L:
+ .dw $ff06
+ .db "UBRR0L"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR0L
+XT_UBRR0L:
+ .dw PFA_DOVARIABLE
+PFA_UBRR0L:
+ .dw 41
+
+.endif
+.if WANT_USART1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR:
+ .dw $ff03
+ .db "UDR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR
+XT_UDR:
+ .dw PFA_DOVARIABLE
+PFA_UDR:
+ .dw 35
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR1A:
+ .dw $ff06
+ .db "UCSR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1A
+XT_UCSR1A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1A:
+ .dw 34
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR1B:
+ .dw $ff06
+ .db "UCSR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1B
+XT_UCSR1B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1B:
+ .dw 33
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR1C:
+ .dw $ff06
+ .db "UCSR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1C
+XT_UCSR1C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1C:
+ .dw 92
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Highg Byte
+VE_UBRR1H:
+ .dw $ff06
+ .db "UBRR1H"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR1H
+XT_UBRR1H:
+ .dw PFA_DOVARIABLE
+PFA_UBRR1H:
+ .dw 92
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Low Byte
+VE_UBRR1L:
+ .dw $ff06
+ .db "UBRR1L"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR1L
+XT_UBRR1L:
+ .dw PFA_DOVARIABLE
+PFA_UBRR1L:
+ .dw 32
+
+.endif
+.if WANT_SPI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR:
+ .dw $ff04
+ .db "SPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR
+XT_SPCR:
+ .dw PFA_DOVARIABLE
+PFA_SPCR:
+ .dw 45
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR:
+ .dw $ff04
+ .db "SPSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR
+XT_SPSR:
+ .dw PFA_DOVARIABLE
+PFA_SPSR:
+ .dw 46
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR:
+ .dw $ff04
+ .db "SPDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR
+XT_SPDR:
+ .dw PFA_DOVARIABLE
+PFA_SPDR:
+ .dw 47
+
+.endif
+.if WANT_CPU == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw 95
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer
+VE_SP:
+ .dw $ff02
+ .db "SP"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SP
+XT_SP:
+ .dw PFA_DOVARIABLE
+PFA_SP:
+ .dw 93
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw 85
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control And Status Register
+VE_MCUCSR:
+ .dw $ff06
+ .db "MCUCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCSR
+XT_MCUCSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCSR:
+ .dw 84
+; ( -- addr ) System Constant
+; R( -- )
+; Extended MCU Control Register
+VE_EMCUCR:
+ .dw $ff06
+ .db "EMCUCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EMCUCR
+XT_EMCUCR:
+ .dw PFA_DOVARIABLE
+PFA_EMCUCR:
+ .dw 86
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Calibration Value
+VE_OSCCAL:
+ .dw $ff06
+ .db "OSCCAL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSCCAL
+XT_OSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_OSCCAL:
+ .dw 36
+; ( -- addr ) System Constant
+; R( -- )
+; Clock prescale register
+VE_CLKPR:
+ .dw $ff05
+ .db "CLKPR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKPR
+XT_CLKPR:
+ .dw PFA_DOVARIABLE
+PFA_CLKPR:
+ .dw 97
+; ( -- addr ) System Constant
+; R( -- )
+; Special Function IO Register
+VE_SFIOR:
+ .dw $ff05
+ .db "SFIOR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SFIOR
+XT_SFIOR:
+ .dw PFA_DOVARIABLE
+PFA_SFIOR:
+ .dw 80
+
+.endif
+.if WANT_JTAG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; On-Chip Debug Related Register in I/O Memory
+VE_OCDR:
+ .dw $ff04
+ .db "OCDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCDR
+XT_OCDR:
+ .dw PFA_DOVARIABLE
+PFA_OCDR:
+ .dw 36
+
+.endif
+.if WANT_BOOT_LOAD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control Register
+VE_SPMCR:
+ .dw $ff05
+ .db "SPMCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCR
+XT_SPMCR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCR:
+ .dw 87
+
+.endif
+.if WANT_EEPROM == 1
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Address Register Bytes
+VE_EEAR:
+ .dw $ff04
+ .db "EEAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEAR
+XT_EEAR:
+ .dw PFA_DOVARIABLE
+PFA_EEAR:
+ .dw 62
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw 61
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw 60
+
+.endif
+.if WANT_PORTA == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Register
+VE_PORTA:
+ .dw $ff05
+ .db "PORTA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTA
+XT_PORTA:
+ .dw PFA_DOVARIABLE
+PFA_PORTA:
+ .dw 59
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Direction Register
+VE_DDRA:
+ .dw $ff04
+ .db "DDRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRA
+XT_DDRA:
+ .dw PFA_DOVARIABLE
+PFA_DDRA:
+ .dw 58
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Input Pins
+VE_PINA:
+ .dw $ff04
+ .db "PINA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINA
+XT_PINA:
+ .dw PFA_DOVARIABLE
+PFA_PINA:
+ .dw 57
+
+.endif
+.if WANT_PORTB == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw 56
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw 55
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw 54
+
+.endif
+.if WANT_PORTC == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Register
+VE_PORTC:
+ .dw $ff05
+ .db "PORTC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTC
+XT_PORTC:
+ .dw PFA_DOVARIABLE
+PFA_PORTC:
+ .dw 53
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Direction Register
+VE_DDRC:
+ .dw $ff04
+ .db "DDRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRC
+XT_DDRC:
+ .dw PFA_DOVARIABLE
+PFA_DDRC:
+ .dw 52
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Input Pins
+VE_PINC:
+ .dw $ff04
+ .db "PINC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINC
+XT_PINC:
+ .dw PFA_DOVARIABLE
+PFA_PINC:
+ .dw 51
+
+.endif
+.if WANT_PORTD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw 50
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw 49
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw 48
+
+.endif
+.if WANT_TIMER_COUNTER_0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter 0 Control Register
+VE_TCCR0:
+ .dw $ff05
+ .db "TCCR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0
+XT_TCCR0:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0:
+ .dw 83
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter 0 Register
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw 82
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter 0 Output Compare Register
+VE_OCR0:
+ .dw $ff04
+ .db "OCR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0
+XT_OCR0:
+ .dw PFA_DOVARIABLE
+PFA_OCR0:
+ .dw 81
+
+.endif
+.if WANT_WATCHDOG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCR:
+ .dw $ff05
+ .db "WDTCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCR
+XT_WDTCR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCR:
+ .dw 65
+
+.endif
+.if WANT_PORTE == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port E
+VE_PORTE:
+ .dw $ff05
+ .db "PORTE",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTE
+XT_PORTE:
+ .dw PFA_DOVARIABLE
+PFA_PORTE:
+ .dw 39
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port E
+VE_DDRE:
+ .dw $ff04
+ .db "DDRE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRE
+XT_DDRE:
+ .dw PFA_DOVARIABLE
+PFA_DDRE:
+ .dw 38
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port E
+VE_PINE:
+ .dw $ff04
+ .db "PINE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINE
+XT_PINE:
+ .dw PFA_DOVARIABLE
+PFA_PINE:
+ .dw 37
+
+.endif
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ( -- addr ) System Constant
+; R( -- )
+; General Interrupt Control Register
+VE_GICR:
+ .dw $ff04
+ .db "GICR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GICR
+XT_GICR:
+ .dw PFA_DOVARIABLE
+PFA_GICR:
+ .dw 91
+; ( -- addr ) System Constant
+; R( -- )
+; General Interrupt Flag Register
+VE_GIFR:
+ .dw $ff04
+ .db "GIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GIFR
+XT_GIFR:
+ .dw PFA_DOVARIABLE
+PFA_GIFR:
+ .dw 90
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 1
+VE_PCMSK1:
+ .dw $ff06
+ .db "PCMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK1
+XT_PCMSK1:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK1:
+ .dw 108
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Enable Mask
+VE_PCMSK0:
+ .dw $ff06
+ .db "PCMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK0
+XT_PCMSK0:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK0:
+ .dw 107
+
+.endif
diff --git a/amforth-6.5/avr8/devices/atmega162/device.py b/amforth-6.5/avr8/devices/atmega162/device.py
new file mode 100644
index 0000000..850bee2
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega162/device.py
@@ -0,0 +1,332 @@
+# Generated Automatically
+
+# Partname ATmega162
+
+MCUREGS = {
+# Interrupt Vectors
+ 'INT0Addr' : '#2', # External Interrupt Request 0
+ 'INT1Addr' : '#4', # External Interrupt Request 1
+ 'INT2Addr' : '#6', # External Interrupt Request 2
+ 'PCINT0Addr' : '#8', # Pin Change Interrupt Request 0
+ 'PCINT1Addr' : '#10', # Pin Change Interrupt Request 1
+ 'TIMER3_CAPTAddr' : '#12', # Timer/Counter3 Capture Event
+ 'TIMER3_COMPAAddr' : '#14', # Timer/Counter3 Compare Match A
+ 'TIMER3_COMPBAddr' : '#16', # Timer/Counter3 Compare Match B
+ 'TIMER3_OVFAddr' : '#18', # Timer/Counter3 Overflow
+ 'TIMER2_COMPAddr' : '#20', # Timer/Counter2 Compare Match
+ 'TIMER2_OVFAddr' : '#22', # Timer/Counter2 Overflow
+ 'TIMER1_CAPTAddr' : '#24', # Timer/Counter1 Capture Event
+ 'TIMER1_COMPAAddr' : '#26', # Timer/Counter1 Compare Match A
+ 'TIMER1_COMPBAddr' : '#28', # Timer/Counter Compare Match B
+ 'TIMER1_OVFAddr' : '#30', # Timer/Counter1 Overflow
+ 'TIMER0_COMPAddr' : '#32', # Timer/Counter0 Compare Match
+ 'TIMER0_OVFAddr' : '#34', # Timer/Counter0 Overflow
+ 'SPI_STCAddr' : '#36', # SPI Serial Transfer Complete
+ 'USART0_RXCAddr' : '#38', # USART0, Rx Complete
+ 'USART1_RXCAddr' : '#40', # USART1, Rx Complete
+ 'USART0_UDREAddr' : '#42', # USART0 Data register Empty
+ 'USART1_UDREAddr' : '#44', # USART1, Data register Empty
+ 'USART0_TXCAddr' : '#46', # USART0, Tx Complete
+ 'USART1_TXCAddr' : '#48', # USART1, Tx Complete
+ 'EE_RDYAddr' : '#50', # EEPROM Ready
+ 'ANA_COMPAddr' : '#52', # Analog Comparator
+ 'SPM_RDYAddr' : '#54', # Store Program Memory Read
+
+# Module TIMER_COUNTER_1
+ 'TIMSK' : '$59', # Timer/Counter Interrupt Mask R
+ 'TIMSK_TOIE1': '$80', # Timer/Counter1 Overflow Interr
+ 'TIMSK_OCIE1A': '$40', # Timer/Counter1 Output CompareA
+ 'TIMSK_OCIE1B': '$20', # Timer/Counter1 Output CompareB
+ 'TIMSK_TICIE1': '$8', # Timer/Counter1 Input Capture I
+ 'TIFR' : '$58', # Timer/Counter Interrupt Flag r
+ 'TIFR_TOV1': '$80', # Timer/Counter1 Overflow Flag
+ 'TIFR_OCF1A': '$40', # Output Compare Flag 1A
+ 'TIFR_OCF1B': '$20', # Output Compare Flag 1B
+ 'TIFR_ICF1': '$8', # Input Capture Flag 1
+ 'TCCR1A' : '$4f', # Timer/Counter1 Control Registe
+ 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
+ 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
+ 'TCCR1A_FOC1A': '$8', # Force Output Compare for Chann
+ 'TCCR1A_FOC1B': '$4', # Force Output Compare for Chann
+ 'TCCR1A_WGM1': '$3', # Pulse Width Modulator Select B
+ 'TCCR1B' : '$4e', # Timer/Counter1 Control Registe
+ 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
+ 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
+ 'TCCR1B_WGM1': '$18', # Pulse Width Modulator Select B
+ 'TCCR1B_CS1': '$7', # Clock Select1 bits
+ 'TCNT1' : '$4c', # Timer/Counter1 Bytes
+ 'OCR1A' : '$4a', # Timer/Counter1 Output Compare
+ 'OCR1B' : '$48', # Timer/Counter1 Output Compare
+ 'ICR1' : '$44', # Timer/Counter1 Input Capture R
+
+# Module TIMER_COUNTER_2
+ 'TCCR2' : '$47', # Timer/Counter Control Register
+ 'TCCR2_FOC2': '$80', # Forde Output Compare
+ 'TCCR2_WGM20': '$40', # Pulse Width Modulator Select B
+ 'TCCR2_COM2': '$30', # Compare Match Output Mode
+ 'TCCR2_WGM21': '$8', # Pulse Width Modulator Select B
+ 'TCCR2_CS2': '$7', # Clock Select
+ 'TCNT2' : '$43', # Timer/Counter Register
+ 'OCR2' : '$42', # Output Compare Register
+ 'TIMSK' : '$59', # Timer/Counter Interrupt Mask R
+ 'TIMSK_OCIE2': '$10', # Timer/Counter2 Output Compare
+ 'TIMSK_TOIE2': '$4', # Timer/Counter2 Overflow Interr
+ 'TIFR' : '$58', # Timer/Counter Interrupt Flag R
+ 'TIFR_OCF2': '$10', # Output Compare Flag 2
+ 'TIFR_TOV2': '$4', # Timer/Counter2 Overflow Flag
+ 'ASSR' : '$46', # Asynchronous Status Register
+ 'ASSR_AS2': '$8', # Asynchronous Timer 2
+ 'ASSR_TCN2UB': '$4', # Timer/Counter2 Update Busy
+ 'ASSR_OCR2UB': '$2', # Output Compare Register2 Updat
+ 'ASSR_TCR2UB': '$1', # Timer/Counter Control Register
+
+# Module TIMER_COUNTER_3
+ 'ETIMSK' : '$7d', # Extended Timer/Counter Interru
+ 'ETIMSK_TICIE3': '$20', # Timer/Counter3 Input Capture I
+ 'ETIMSK_OCIE3A': '$10', # Timer/Counter3 Output CompareA
+ 'ETIMSK_OCIE3B': '$8', # Timer/Counter3 Output CompareB
+ 'ETIMSK_TOIE3': '$4', # Timer/Counter3 Overflow Interr
+ 'ETIFR' : '$7c', # Extended Timer/Counter Interru
+ 'ETIFR_ICF3': '$20', # Input Capture Flag 3
+ 'ETIFR_OCF3A': '$10', # Output Compare Flag 3A
+ 'ETIFR_OCF3B': '$8', # Output Compare Flag 3B
+ 'ETIFR_TOV3': '$4', # Timer/Counter3 Overflow Flag
+ 'TCCR3A' : '$8b', # Timer/Counter3 Control Registe
+ 'TCCR3A_COM3A': '$c0', # Compare Output Mode 3A, bits
+ 'TCCR3A_COM3B': '$30', # Compare Output Mode 3B, bits
+ 'TCCR3A_FOC3A': '$8', # Force Output Compare for Chann
+ 'TCCR3A_FOC3B': '$4', # Force Output Compare for Chann
+ 'TCCR3A_WGM3': '$3', # Pulse Width Modulator Select B
+ 'TCCR3B' : '$8a', # Timer/Counter3 Control Registe
+ 'TCCR3B_ICNC3': '$80', # Input Capture 3 Noise Canceler
+ 'TCCR3B_ICES3': '$40', # Input Capture 3 Edge Select
+ 'TCCR3B_WGM3': '$18', # Pulse Width Modulator Select B
+ 'TCCR3B_CS3': '$7', # Clock Select3 bits
+ 'TCNT3' : '$88', # Timer/Counter3 Bytes
+ 'OCR3A' : '$86', # Timer/Counter3 Output Compare
+ 'OCR3B' : '$84', # Timer/Counte3 Output Compare R
+ 'ICR3' : '$80', # Timer/Counter3 Input Capture R
+
+# Module ANALOG_COMPARATOR
+ 'ACSR' : '$28', # Analog Comparator Control And
+ 'ACSR_ACD': '$80', # Analog Comparator Disable
+ 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
+ 'ACSR_ACO': '$20', # Analog Compare Output
+ 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
+ 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
+ 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
+ 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
+
+# Module USART0
+ 'UDR0' : '$2c', # USART I/O Data Register
+ 'UCSR0A' : '$2b', # USART Control and Status Regis
+ 'UCSR0A_RXC0': '$80', # USART Receive Complete
+ 'UCSR0A_TXC0': '$40', # USART Transmitt Complete
+ 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
+ 'UCSR0A_FE0': '$10', # Framing Error
+ 'UCSR0A_DOR0': '$8', # Data overRun
+ 'UCSR0A_UPE0': '$4', # Parity Error
+ 'UCSR0A_U2X0': '$2', # Double the USART transmission
+ 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
+ 'UCSR0B' : '$2a', # USART Control and Status Regis
+ 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
+ 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
+ 'UCSR0B_UDRIE0': '$20', # USART Data register Empty Inte
+ 'UCSR0B_RXEN0': '$10', # Receiver Enable
+ 'UCSR0B_TXEN0': '$8', # Transmitter Enable
+ 'UCSR0B_UCSZ02': '$4', # Character Size
+ 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
+ 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
+ 'UCSR0C' : '$40', # USART Control and Status Regis
+ 'UCSR0C_URSEL0': '$80', # Register Select
+ 'UCSR0C_UMSEL0': '$40', # USART Mode Select
+ 'UCSR0C_UPM0': '$30', # Parity Mode Bits
+ 'UCSR0C_USBS0': '$8', # Stop Bit Select
+ 'UCSR0C_UCSZ0': '$6', # Character Size
+ 'UCSR0C_UCPOL0': '$1', # Clock Polarity
+ 'UBRR0H' : '$40', # USART Baud Rate Register Hight
+ 'UBRR0L' : '$29', # USART Baud Rate Register Low B
+
+# Module USART1
+ 'UDR' : '$23', # USART I/O Data Register
+ 'UCSR1A' : '$22', # USART Control and Status Regis
+ 'UCSR1A_RXC1': '$80', # USART Receive Complete
+ 'UCSR1A_TXC1': '$40', # USART Transmitt Complete
+ 'UCSR1A_UDRE1': '$20', # USART Data Register Empty
+ 'UCSR1A_FE1': '$10', # Framing Error
+ 'UCSR1A_DOR1': '$8', # Data overRun
+ 'UCSR1A_UPE1': '$4', # Parity Error
+ 'UCSR1A_U2X1': '$2', # Double the USART transmission
+ 'UCSR1A_MPCM1': '$1', # Multi-processor Communication
+ 'UCSR1B' : '$21', # USART Control and Status Regis
+ 'UCSR1B_RXCIE1': '$80', # RX Complete Interrupt Enable
+ 'UCSR1B_TXCIE1': '$40', # TX Complete Interrupt Enable
+ 'UCSR1B_UDRIE1': '$20', # USART Data register Empty Inte
+ 'UCSR1B_RXEN1': '$10', # Receiver Enable
+ 'UCSR1B_TXEN1': '$8', # Transmitter Enable
+ 'UCSR1B_UCSZ12': '$4', # Character Size
+ 'UCSR1B_RXB81': '$2', # Receive Data Bit 8
+ 'UCSR1B_TXB81': '$1', # Transmit Data Bit 8
+ 'UCSR1C' : '$5c', # USART Control and Status Regis
+ 'UCSR1C_URSEL1': '$80', # Register Select
+ 'UCSR1C_UMSEL1': '$40', # USART Mode Select
+ 'UCSR1C_UPM1': '$30', # Parity Mode Bits
+ 'UCSR1C_USBS1': '$8', # Stop Bit Select
+ 'UCSR1C_UCSZ1': '$6', # Character Size
+ 'UCSR1C_UCPOL1': '$1', # Clock Polarity
+ 'UBRR1H' : '$5c', # USART Baud Rate Register Highg
+ 'UBRR1L' : '$20', # USART Baud Rate Register Low B
+
+# Module SPI
+ 'SPCR' : '$2d', # SPI Control Register
+ 'SPCR_SPIE': '$80', # SPI Interrupt Enable
+ 'SPCR_SPE': '$40', # SPI Enable
+ 'SPCR_DORD': '$20', # Data Order
+ 'SPCR_MSTR': '$10', # Master/Slave Select
+ 'SPCR_CPOL': '$8', # Clock polarity
+ 'SPCR_CPHA': '$4', # Clock Phase
+ 'SPCR_SPR': '$3', # SPI Clock Rate Selects
+ 'SPSR' : '$2e', # SPI Status Register
+ 'SPSR_SPIF': '$80', # SPI Interrupt Flag
+ 'SPSR_WCOL': '$40', # Write Collision Flag
+ 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
+ 'SPDR' : '$2f', # SPI Data Register
+
+# Module CPU
+ 'SREG' : '$5f', # Status Register
+ 'SREG_I': '$80', # Global Interrupt Enable
+ 'SREG_T': '$40', # Bit Copy Storage
+ 'SREG_H': '$20', # Half Carry Flag
+ 'SREG_S': '$10', # Sign Bit
+ 'SREG_V': '$8', # Two's Complement Overflow Flag
+ 'SREG_N': '$4', # Negative Flag
+ 'SREG_Z': '$2', # Zero Flag
+ 'SREG_C': '$1', # Carry Flag
+ 'SP' : '$5d', # Stack Pointer
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_SRE': '$80', # External SRAM Enable
+ 'MCUCR_SRW10': '$40', # External SRAM Wait State Selec
+ 'MCUCR_SE': '$20', # Sleep Enable
+ 'MCUCR_SM1': '$10', # Sleep Mode Select
+ 'MCUCR_ISC1': '$c', # Interrupt Sense Control 1 bits
+ 'MCUCR_ISC0': '$3', # Interrupt Sense Control 0 bits
+ 'MCUCSR' : '$54', # MCU Control And Status Registe
+ 'MCUCSR_JDT': '$80', # JTAG Interface Disable
+ 'MCUCSR_SM2': '$20', # Sleep Mode Select Bit 2
+ 'MCUCSR_JTRF': '$10', # JTAG Reset Flag
+ 'MCUCSR_WDRF': '$8', # Watchdog Reset Flag
+ 'MCUCSR_BORF': '$4', # Brown-out Reset Flag
+ 'MCUCSR_EXTRF': '$2', # External Reset Flag
+ 'MCUCSR_PORF': '$1', # Power-on reset flag
+ 'EMCUCR' : '$56', # Extended MCU Control Register
+ 'EMCUCR_SM0': '$80', # Sleep mode Select Bit 0
+ 'EMCUCR_SRL': '$70', # Wait State Sector Limit Bits
+ 'EMCUCR_SRW0': '$c', # Wait State Select Bit 1 for Lo
+ 'EMCUCR_SRW11': '$2', # Wait State Select Bit 1 for Up
+ 'EMCUCR_ISC2': '$1', # Interrupt Sense Control 2
+ 'OSCCAL' : '$24', # Oscillator Calibration Value
+ 'CLKPR' : '$61', # Clock prescale register
+ 'CLKPR_CLKPCE': '$80', # Clock Prescaler Change Enable
+ 'CLKPR_CLKPS': '$f', # Clock Prescaler Select Bits
+ 'SFIOR' : '$50', # Special Function IO Register
+ 'SFIOR_TSM': '$80', # Timer/Counter Synchronization
+ 'SFIOR_XMBK': '$40', # External Memory Bus Keeper Ena
+ 'SFIOR_XMM': '$38', # External Memory High Mask Bits
+ 'SFIOR_PUD': '$4', # Pull-up Disable
+ 'SFIOR_PSR2': '$2', # Prescaler Reset Timer/Counter2
+ 'SFIOR_PSR310': '$1', # Prescaler Reset Timer/Counter3
+
+# Module JTAG
+ 'OCDR' : '$24', # On-Chip Debug Related Register
+ 'OCDR_OCDR': '$ff', # On-Chip Debug Register Bits
+ 'MCUCSR' : '$54', # MCU Control And Status Registe
+ 'MCUCSR_JTD': '$80', # JTAG Interface Disable
+ 'MCUCSR_JTRF': '$10', # JTAG Reset Flag
+
+# Module BOOT_LOAD
+ 'SPMCR' : '$57', # Store Program Memory Control R
+ 'SPMCR_SPMIE': '$80', # SPM Interrupt Enable
+ 'SPMCR_RWWSB': '$40', # Read While Write Section Busy
+ 'SPMCR_RWWSRE': '$10', # Read While Write secion read e
+ 'SPMCR_BLBSET': '$8', # Boot Lock Bit Set
+ 'SPMCR_PGWRT': '$4', # Page Write
+ 'SPMCR_PGERS': '$2', # Page Erase
+ 'SPMCR_SPMEN': '$1', # Store Program Memory Enable
+
+# Module EEPROM
+ 'EEAR' : '$3e', # EEPROM Address Register Bytes
+ 'EEDR' : '$3d', # EEPROM Data Register
+ 'EECR' : '$3c', # EEPROM Control Register
+ 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
+ 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
+ 'EECR_EEWE': '$2', # EEPROM Write Enable
+ 'EECR_EERE': '$1', # EEPROM Read Enable
+
+# Module PORTA
+ 'PORTA' : '$3b', # Port A Data Register
+ 'DDRA' : '$3a', # Port A Data Direction Register
+ 'PINA' : '$39', # Port A Input Pins
+
+# Module PORTB
+ 'PORTB' : '$38', # Port B Data Register
+ 'DDRB' : '$37', # Port B Data Direction Register
+ 'PINB' : '$36', # Port B Input Pins
+
+# Module PORTC
+ 'PORTC' : '$35', # Port C Data Register
+ 'DDRC' : '$34', # Port C Data Direction Register
+ 'PINC' : '$33', # Port C Input Pins
+
+# Module PORTD
+ 'PORTD' : '$32', # Port D Data Register
+ 'DDRD' : '$31', # Port D Data Direction Register
+ 'PIND' : '$30', # Port D Input Pins
+
+# Module TIMER_COUNTER_0
+ 'TCCR0' : '$53', # Timer/Counter 0 Control Regist
+ 'TCCR0_FOC0': '$80', # Force Output Compare
+ 'TCCR0_WGM00': '$40', # Waveform Generation Mode 0
+ 'TCCR0_COM0': '$30', # Compare Match Output Modes
+ 'TCCR0_WGM01': '$8', # Waveform Generation Mode 1
+ 'TCCR0_CS0': '$7', # Clock Selects
+ 'TCNT0' : '$52', # Timer/Counter 0 Register
+ 'OCR0' : '$51', # Timer/Counter 0 Output Compare
+ 'TIMSK' : '$59', # Timer/Counter Interrupt Mask R
+ 'TIMSK_TOIE0': '$2', # Timer/Counter0 Overflow Interr
+ 'TIMSK_OCIE0': '$1', # Timer/Counter0 Output Compare
+ 'TIFR' : '$58', # Timer/Counter Interrupt Flag r
+ 'TIFR_TOV0': '$2', # Timer/Counter0 Overflow Flag
+ 'TIFR_OCF0': '$1', # Output Compare Flag 0
+
+# Module WATCHDOG
+ 'WDTCR' : '$41', # Watchdog Timer Control Registe
+ 'WDTCR_WDCE': '$10', # Watchdog Change Enable
+ 'WDTCR_WDE': '$8', # Watch Dog Enable
+ 'WDTCR_WDP': '$7', # Watch Dog Timer Prescaler bits
+
+# Module PORTE
+ 'PORTE' : '$27', # Data Register, Port E
+ 'DDRE' : '$26', # Data Direction Register, Port
+ 'PINE' : '$25', # Input Pins, Port E
+
+# Module EXTERNAL_INTERRUPT
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_ISC1': '$c', # Interrupt Sense Control 1 Bits
+ 'MCUCR_ISC0': '$3', # Interrupt Sense Control 0 Bits
+ 'EMCUCR' : '$56', # Extended MCU Control Register
+ 'EMCUCR_ISC2': '$1', # Interrupt Sense Control 2
+ 'GICR' : '$5b', # General Interrupt Control Regi
+ 'GICR_INT': '$c0', # External Interrupt Request 1 E
+ 'GICR_INT2': '$20', # External Interrupt Request 2 E
+ 'GICR_PCIE': '$18', # Pin Change Interrupt Enables
+ 'GICR_IVSEL': '$2', # Interrupt Vector Select
+ 'GICR_IVCE': '$1', # Interrupt Vector Change Enable
+ 'GIFR' : '$5a', # General Interrupt Flag Registe
+ 'GIFR_INTF': '$c0', # External Interrupt Flags
+ 'GIFR_INTF2': '$20', # External Interrupt Flag 2
+ 'GIFR_PCIF': '$18', # Pin Change Interrupt Flags
+ 'PCMSK1' : '$6c', # Pin Change Mask Register 1
+ 'PCMSK0' : '$6b', # Pin Change Enable Mask
+
+ '__amforth_dummy':'0'
+}
diff --git a/amforth-6.5/avr8/devices/atmega162/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega162/words/no-jtag.asm
new file mode 100644
index 0000000..352a4bb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega162/words/no-jtag.asm
@@ -0,0 +1,14 @@
+; ( -- )
+; ( -- )
+; MCU
+; disable jtag at runtime
+VE_NOJTAG:
+ .dw $FF05
+ .db "-jtag",0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOJTAG
+XT_NOJTAG:
+ .dw PFA_NOJTAG
+PFA_NOJTAG:
+
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega162/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega162/words/no-wdt.asm
new file mode 100644
index 0000000..4a12261
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega162/words/no-wdt.asm
@@ -0,0 +1,22 @@
+; ( -- )
+; MCU
+; disable watch dog timer at runtime
+VE_NOWDT:
+ .dw $ff04
+ .db "-wdt"
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOWDT
+XT_NOWDT:
+ .dw PFA_NOWDT
+PFA_NOWDT:
+
+; Reset WDT
+ wdr
+; Write logical one to WDTOE and WDE
+ in_ temp1, WDTCR
+ ori temp1, (1<<WDTOE)|(1<<WDE)
+ out WDTCR, temp1
+; Turn off WDT
+ ldi temp1, (0<<WDE)
+ out_ WDTCR, temp1
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega162/words/sleep.asm b/amforth-6.5/avr8/devices/atmega162/words/sleep.asm
new file mode 100644
index 0000000..778fa32
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega162/words/sleep.asm
@@ -0,0 +1,24 @@
+; ( mode -- )
+; MCU
+; put the controller into the specified sleep mode
+VE_SLEEP:
+ .dw $ff05
+ .db "sleep", 0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_SLEEP
+XT_SLEEP:
+ .dw PFA_SLEEP
+PFA_SLEEP:
+ andi tosl, 7 ; leave only legal mode bits
+ swap tosl ; move to correct location (bits 6-4, atmega32)
+ ori tosl, $80 ; set the SE bit (atmega32: bit 7, not bit 0)
+ out_ MCUCR, tosl ; set the sleep config (atmega32: MCUCR not SMCR)
+ sleep ; nighty-night
+;; the 4 lower bits of MCUCR should not be touched
+ in_ tosl, MCUCR
+ andi tosl, $0F
+ out_ MCUCR, tosl
+ ;clr tosl ; need to clean up the SMCR reg before we leave
+ ;out SMCR, tosl ; 0 protects against accidental sleeps
+ loadtos ; pop argument from stack
+ jmp DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega163/atmega163.frt b/amforth-6.5/avr8/devices/atmega163/atmega163.frt
new file mode 100644
index 0000000..796fd3f
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega163/atmega163.frt
@@ -0,0 +1,121 @@
+\ Partname: ATmega163
+\ Built using part description XML file version 207
+\ generated automatically
+
+hex
+
+\ AD_CONVERTER
+25 constant ADCH \ ADC Data Register High Byte
+24 constant ADCL \ ADC Data Register Low Byte
+26 constant ADCSR \ The ADC Control and Status register
+27 constant ADMUX \ The ADC multiplexer Selection Register
+
+\ ANALOG_COMPARATOR
+28 constant ACSR \ Analog Comparator Control And Status Register
+50 constant SFIOR \ Special Function IO Register
+
+\ BOOT_LOAD
+57 constant SPMCR \ Store Program Memory Control Register
+
+\ CPU
+55 constant MCUCR \ MCU Control register
+54 constant MCUSR \ MCU Status Register
+51 constant OSCCAL \ Oscillator Calibration Value
+5E constant SPH \ Stack Pointer High
+5D constant SPL \ Stack Pointer Low
+5F constant SREG \ Status Register
+
+\ EEPROM
+3F constant EEARH \ EEPROM Address Register High Byte
+3E constant EEARL \ EEPROM Address Register Low Byte
+3C constant EECR \ EEPROM Control Register
+3D constant EEDR \ EEPROM Data Register
+
+\ EXTERNAL_INTERRUPT
+5A constant GIFR \ General Interrupt Flag register
+5B constant GIMSK \ General Interrupt Mask Register
+
+\ PORTA
+3A constant DDRA \ Port A Data Direction Register
+39 constant PINA \ Port A Input Pins
+3B constant PORTA \ Port A Data Register
+
+\ PORTB
+37 constant DDRB \ Port B Data Direction Register
+36 constant PINB \ Port B Input Pins
+38 constant PORTB \ Port B Data Register
+
+\ PORTC
+34 constant DDRC \ Port C Data Direction Register
+33 constant PINC \ Port C Input Pins
+35 constant PORTC \ Port C Data Register
+
+\ PORTD
+31 constant DDRD \ Port D Data Direction Register
+30 constant PIND \ Port D Input Pins
+32 constant PORTD \ Port D Data Register
+
+\ SPI
+2D constant SPCR \ SPI Control Register
+2F constant SPDR \ SPI Data Register
+2E constant SPSR \ SPI Status Register
+
+\ TIMER_COUNTER_0
+53 constant TCCR0 \ Timer/Counter0 Control Register
+52 constant TCNT0 \ Timer Counter 0
+58 constant TIFR \ Timer/Counter Interrupt Flag register
+59 constant TIMSK \ Timer/Counter Interrupt Mask Register
+
+\ TIMER_COUNTER_1
+47 constant ICR1H \ Timer/Counter1 Input Capture Register High Byte
+46 constant ICR1L \ Timer/Counter1 Input Capture Register Low Byte
+4B constant OCR1AH \ Timer/Counter1 Output Compare Register High Byte
+4A constant OCR1AL \ Timer/Counter1 Output Compare Register Low Byte
+49 constant OCR1BH \ Timer/Counter1 Output Compare Register High Byte
+48 constant OCR1BL \ Timer/Counter1 Output Compare Register Low Byte
+4F constant TCCR1A \ Timer/Counter1 Control Register A
+4E constant TCCR1B \ Timer/Counter1 Control Register B
+4D constant TCNT1H \ Timer/Counter1 High Byte
+4C constant TCNT1L \ Timer/Counter1 Low Byte
+
+\ TIMER_COUNTER_2
+42 constant ASSR \ Asynchronous Status Register
+43 constant OCR2 \ Timer/Counter2 Output Compare Register
+45 constant TCCR2 \ Timer/Counter2 Control Register
+44 constant TCNT2 \ Timer/Counter2
+
+\ TWI
+22 constant TWAR \ TWI (Slave) Address register
+20 constant TWBR \ TWI Bit Rate register
+56 constant TWCR \ TWI Control Register
+23 constant TWDR \ TWI Data register
+21 constant TWSR \ TWI Status Register
+
+\ UART
+29 constant UBRR \ UART Baud Rate Register
+40 constant UBRRHI \ UART Baud Rate Register High Byte
+2B constant UCSRA \ UART Control and Status register A
+2A constant UCSRB \ UART Control an Status register B
+2C constant UDR \ UART I/O Data Register
+
+\ WATCHDOG
+41 constant WDTCR \ Watchdog Timer Control Register
+
+\ Interrupts
+002 constant INT0Addr \ External Interrupt 0
+004 constant INT1Addr \ External Interrupt 1
+006 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
+008 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
+00A constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+00C constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
+00E constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
+010 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+012 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
+014 constant SPISTCAddr \ SPI Serial Transfer Complete
+016 constant UARTRXAddr \ UART, RX Complete
+018 constant UARTUDREAddr \ UART Data Register Empty
+01A constant UARTTXAddr \ UART, TX Complete
+01C constant ADCAddr \ ADC Conversion Complete
+01E constant EE_RDYAddr \ EEPROM Ready
+020 constant ANA_COMPAddr \ Analog Comparator
+022 constant TWIAddr \ 2-Wire Serial Interface
diff --git a/amforth-6.5/avr8/devices/atmega163/device.asm b/amforth-6.5/avr8/devices/atmega163/device.asm
new file mode 100644
index 0000000..2a6a80f
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega163/device.asm
@@ -0,0 +1,108 @@
+; Partname: ATmega163
+; Built using part description XML file version 207
+; generated automatically, do not edit
+
+.nolist
+ .include "m163def.inc"
+.list
+
+.equ ramstart = $60
+.equ CELLSIZE = 2
+.macro readflashcell
+ lsl zl
+ rol zh
+ lpm @0, Z+
+ lpm @1, Z+
+.endmacro
+.macro writeflashcell
+ lsl zl
+ rol zh
+.endmacro
+
+; the following definitions are shortcuts for the respective forth source segments if set to 1
+.set WANT_AD_CONVERTER = 0
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_BOOT_LOAD = 0
+.set WANT_CPU = 0
+.set WANT_EEPROM = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_PORTA = 0
+.set WANT_PORTB = 0
+.set WANT_PORTC = 0
+.set WANT_PORTD = 0
+.set WANT_SPI = 0
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_TIMER_COUNTER_2 = 0
+.set WANT_TWI = 0
+.set WANT_UART = 0
+.set WANT_WATCHDOG = 0
+
+
+.ifndef SPMEN
+ .equ SPMEN = SELFPRGEN
+.endif
+
+.ifndef SPMCSR
+ .equ SPMCSR = SPMCR
+.endif
+
+.ifndef EEPE
+ .equ EEPE = EEWE
+.endif
+
+.ifndef EEMPE
+ .equ EEMPE = EEMWE
+.endif
+.equ intvecsize = 2 ; please verify; flash size: 16384 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.equ INTVECTORS = 18
+.org $002
+ rcall isr ; External Interrupt 0
+.org $004
+ rcall isr ; External Interrupt 1
+.org $006
+ rcall isr ; Timer/Counter2 Compare Match
+.org $008
+ rcall isr ; Timer/Counter2 Overflow
+.org $00A
+ rcall isr ; Timer/Counter1 Capture Event
+.org $00C
+ rcall isr ; Timer/Counter1 Compare Match A
+.org $00E
+ rcall isr ; Timer/Counter1 Compare Match B
+.org $010
+ rcall isr ; Timer/Counter1 Overflow
+.org $012
+ rcall isr ; Timer/Counter0 Overflow
+.org $014
+ rcall isr ; SPI Serial Transfer Complete
+.org $016
+ rcall isr ; UART, RX Complete
+.org $018
+ rcall isr ; UART Data Register Empty
+.org $01A
+ rcall isr ; UART, TX Complete
+.org $01C
+ rcall isr ; ADC Conversion Complete
+.org $01E
+ rcall isr ; EEPROM Ready
+.org $020
+ rcall isr ; Analog Comparator
+.org $022
+ rcall isr ; 2-Wire Serial Interface
+.nooverlap
+mcu_info:
+mcu_ramsize:
+ .dw 1024
+mcu_eepromsize:
+ .dw 512
+mcu_maxdp:
+ .dw 0 ; minimum of 0 (from XML) and 0xffff
+mcu_numints:
+ .dw 18
+mcu_name:
+ .dw 9
+ .db "ATmega163",0
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega163/device.inc b/amforth-6.5/avr8/devices/atmega163/device.inc
new file mode 100644
index 0000000..6f6359e
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega163/device.inc
@@ -0,0 +1,861 @@
+; Partname: ATmega163
+; Built using part description XML file version 207
+; generated automatically, no not edit
+
+; ********
+.if WANT_AD_CONVERTER == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register High Byte
+VE_ADCH:
+ .dw $ff04
+ .db "ADCH"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCH
+XT_ADCH:
+ .dw PFA_DOVARIABLE
+PFA_ADCH:
+ .dw $25
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register Low Byte
+VE_ADCL:
+ .dw $ff04
+ .db "ADCL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCL
+XT_ADCL:
+ .dw PFA_DOVARIABLE
+PFA_ADCL:
+ .dw $24
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register
+VE_ADCSR:
+ .dw $ff05
+ .db "ADCSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSR
+XT_ADCSR:
+ .dw PFA_DOVARIABLE
+PFA_ADCSR:
+ .dw $26
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC multiplexer Selection Register
+VE_ADMUX:
+ .dw $ff05
+ .db "ADMUX",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADMUX
+XT_ADMUX:
+ .dw PFA_DOVARIABLE
+PFA_ADMUX:
+ .dw $27
+
+.endif
+
+; ********
+.if WANT_ANALOG_COMPARATOR == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Control And Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw $28
+; ( -- addr ) System Constant
+; R( -- )
+; Special Function IO Register
+VE_SFIOR:
+ .dw $ff05
+ .db "SFIOR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SFIOR
+XT_SFIOR:
+ .dw PFA_DOVARIABLE
+PFA_SFIOR:
+ .dw $50
+
+.endif
+
+; ********
+.if WANT_BOOT_LOAD == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control Register
+VE_SPMCR:
+ .dw $ff05
+ .db "SPMCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCR
+XT_SPMCR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCR:
+ .dw $57
+
+.endif
+
+; ********
+.if WANT_CPU == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw $55
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Status Register
+VE_MCUSR:
+ .dw $ff05
+ .db "MCUSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUSR
+XT_MCUSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUSR:
+ .dw $54
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Calibration Value
+VE_OSCCAL:
+ .dw $ff06
+ .db "OSCCAL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSCCAL
+XT_OSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_OSCCAL:
+ .dw $51
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer High
+VE_SPH:
+ .dw $ff03
+ .db "SPH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPH
+XT_SPH:
+ .dw PFA_DOVARIABLE
+PFA_SPH:
+ .dw $5E
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer Low
+VE_SPL:
+ .dw $ff03
+ .db "SPL",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPL
+XT_SPL:
+ .dw PFA_DOVARIABLE
+PFA_SPL:
+ .dw $5D
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw $5F
+
+.endif
+
+; ********
+.if WANT_EEPROM == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Address Register High Byte
+VE_EEARH:
+ .dw $ff05
+ .db "EEARH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEARH
+XT_EEARH:
+ .dw PFA_DOVARIABLE
+PFA_EEARH:
+ .dw $3F
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Address Register Low Byte
+VE_EEARL:
+ .dw $ff05
+ .db "EEARL",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEARL
+XT_EEARL:
+ .dw PFA_DOVARIABLE
+PFA_EEARL:
+ .dw $3E
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw $3C
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw $3D
+
+.endif
+
+; ********
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; General Interrupt Flag register
+VE_GIFR:
+ .dw $ff04
+ .db "GIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GIFR
+XT_GIFR:
+ .dw PFA_DOVARIABLE
+PFA_GIFR:
+ .dw $5A
+; ( -- addr ) System Constant
+; R( -- )
+; General Interrupt Mask Register
+VE_GIMSK:
+ .dw $ff05
+ .db "GIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GIMSK
+XT_GIMSK:
+ .dw PFA_DOVARIABLE
+PFA_GIMSK:
+ .dw $5B
+
+.endif
+
+; ********
+.if WANT_PORTA == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Direction Register
+VE_DDRA:
+ .dw $ff04
+ .db "DDRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRA
+XT_DDRA:
+ .dw PFA_DOVARIABLE
+PFA_DDRA:
+ .dw $3A
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Input Pins
+VE_PINA:
+ .dw $ff04
+ .db "PINA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINA
+XT_PINA:
+ .dw PFA_DOVARIABLE
+PFA_PINA:
+ .dw $39
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Register
+VE_PORTA:
+ .dw $ff05
+ .db "PORTA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTA
+XT_PORTA:
+ .dw PFA_DOVARIABLE
+PFA_PORTA:
+ .dw $3B
+
+.endif
+
+; ********
+.if WANT_PORTB == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw $37
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw $36
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw $38
+
+.endif
+
+; ********
+.if WANT_PORTC == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Direction Register
+VE_DDRC:
+ .dw $ff04
+ .db "DDRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRC
+XT_DDRC:
+ .dw PFA_DOVARIABLE
+PFA_DDRC:
+ .dw $34
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Input Pins
+VE_PINC:
+ .dw $ff04
+ .db "PINC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINC
+XT_PINC:
+ .dw PFA_DOVARIABLE
+PFA_PINC:
+ .dw $33
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Register
+VE_PORTC:
+ .dw $ff05
+ .db "PORTC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTC
+XT_PORTC:
+ .dw PFA_DOVARIABLE
+PFA_PORTC:
+ .dw $35
+
+.endif
+
+; ********
+.if WANT_PORTD == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw $31
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw $30
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw $32
+
+.endif
+
+; ********
+.if WANT_SPI == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR:
+ .dw $ff04
+ .db "SPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR
+XT_SPCR:
+ .dw PFA_DOVARIABLE
+PFA_SPCR:
+ .dw $2D
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR:
+ .dw $ff04
+ .db "SPDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR
+XT_SPDR:
+ .dw PFA_DOVARIABLE
+PFA_SPDR:
+ .dw $2F
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR:
+ .dw $ff04
+ .db "SPSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR
+XT_SPSR:
+ .dw PFA_DOVARIABLE
+PFA_SPSR:
+ .dw $2E
+
+.endif
+
+; ********
+.if WANT_TIMER_COUNTER_0 == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Control Register
+VE_TCCR0:
+ .dw $ff05
+ .db "TCCR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0
+XT_TCCR0:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0:
+ .dw $53
+; ( -- addr ) System Constant
+; R( -- )
+; Timer Counter 0
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw $52
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Flag register
+VE_TIFR:
+ .dw $ff04
+ .db "TIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR
+XT_TIFR:
+ .dw PFA_DOVARIABLE
+PFA_TIFR:
+ .dw $58
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Mask Register
+VE_TIMSK:
+ .dw $ff05
+ .db "TIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK
+XT_TIMSK:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK:
+ .dw $59
+
+.endif
+
+; ********
+.if WANT_TIMER_COUNTER_1 == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register High Byte
+VE_ICR1H:
+ .dw $ff05
+ .db "ICR1H",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1H
+XT_ICR1H:
+ .dw PFA_DOVARIABLE
+PFA_ICR1H:
+ .dw $47
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Low Byte
+VE_ICR1L:
+ .dw $ff05
+ .db "ICR1L",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1L
+XT_ICR1L:
+ .dw PFA_DOVARIABLE
+PFA_ICR1L:
+ .dw $46
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register High Byte
+VE_OCR1AH:
+ .dw $ff06
+ .db "OCR1AH"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1AH
+XT_OCR1AH:
+ .dw PFA_DOVARIABLE
+PFA_OCR1AH:
+ .dw $4B
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register Low Byte
+VE_OCR1AL:
+ .dw $ff06
+ .db "OCR1AL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1AL
+XT_OCR1AL:
+ .dw PFA_DOVARIABLE
+PFA_OCR1AL:
+ .dw $4A
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register High Byte
+VE_OCR1BH:
+ .dw $ff06
+ .db "OCR1BH"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1BH
+XT_OCR1BH:
+ .dw PFA_DOVARIABLE
+PFA_OCR1BH:
+ .dw $49
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register Low Byte
+VE_OCR1BL:
+ .dw $ff06
+ .db "OCR1BL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1BL
+XT_OCR1BL:
+ .dw PFA_DOVARIABLE
+PFA_OCR1BL:
+ .dw $48
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw $4F
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw $4E
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 High Byte
+VE_TCNT1H:
+ .dw $ff06
+ .db "TCNT1H"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1H
+XT_TCNT1H:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1H:
+ .dw $4D
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Low Byte
+VE_TCNT1L:
+ .dw $ff06
+ .db "TCNT1L"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1L
+XT_TCNT1L:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1L:
+ .dw $4C
+
+.endif
+
+; ********
+.if WANT_TIMER_COUNTER_2 == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Asynchronous Status Register
+VE_ASSR:
+ .dw $ff04
+ .db "ASSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ASSR
+XT_ASSR:
+ .dw PFA_DOVARIABLE
+PFA_ASSR:
+ .dw $42
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register
+VE_OCR2:
+ .dw $ff04
+ .db "OCR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2
+XT_OCR2:
+ .dw PFA_DOVARIABLE
+PFA_OCR2:
+ .dw $43
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register
+VE_TCCR2:
+ .dw $ff05
+ .db "TCCR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2
+XT_TCCR2:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2:
+ .dw $45
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2
+VE_TCNT2:
+ .dw $ff05
+ .db "TCNT2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT2
+XT_TCNT2:
+ .dw PFA_DOVARIABLE
+PFA_TCNT2:
+ .dw $44
+
+.endif
+
+; ********
+.if WANT_TWI == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; TWI (Slave) Address register
+VE_TWAR:
+ .dw $ff04
+ .db "TWAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWAR
+XT_TWAR:
+ .dw PFA_DOVARIABLE
+PFA_TWAR:
+ .dw $22
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Bit Rate register
+VE_TWBR:
+ .dw $ff04
+ .db "TWBR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWBR
+XT_TWBR:
+ .dw PFA_DOVARIABLE
+PFA_TWBR:
+ .dw $20
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Control Register
+VE_TWCR:
+ .dw $ff04
+ .db "TWCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWCR
+XT_TWCR:
+ .dw PFA_DOVARIABLE
+PFA_TWCR:
+ .dw $56
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Data register
+VE_TWDR:
+ .dw $ff04
+ .db "TWDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWDR
+XT_TWDR:
+ .dw PFA_DOVARIABLE
+PFA_TWDR:
+ .dw $23
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Status Register
+VE_TWSR:
+ .dw $ff04
+ .db "TWSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWSR
+XT_TWSR:
+ .dw PFA_DOVARIABLE
+PFA_TWSR:
+ .dw $21
+
+.endif
+
+; ********
+.if WANT_UART == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; UART Baud Rate Register
+VE_UBRR:
+ .dw $ff04
+ .db "UBRR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR
+XT_UBRR:
+ .dw PFA_DOVARIABLE
+PFA_UBRR:
+ .dw $29
+; ( -- addr ) System Constant
+; R( -- )
+; UART Baud Rate Register High Byte
+VE_UBRRHI:
+ .dw $ff06
+ .db "UBRRHI"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRRHI
+XT_UBRRHI:
+ .dw PFA_DOVARIABLE
+PFA_UBRRHI:
+ .dw $40
+; ( -- addr ) System Constant
+; R( -- )
+; UART Control and Status register A
+VE_UCSRA:
+ .dw $ff05
+ .db "UCSRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSRA
+XT_UCSRA:
+ .dw PFA_DOVARIABLE
+PFA_UCSRA:
+ .dw $2B
+; ( -- addr ) System Constant
+; R( -- )
+; UART Control an Status register B
+VE_UCSRB:
+ .dw $ff05
+ .db "UCSRB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSRB
+XT_UCSRB:
+ .dw PFA_DOVARIABLE
+PFA_UCSRB:
+ .dw $2A
+; ( -- addr ) System Constant
+; R( -- )
+; UART I/O Data Register
+VE_UDR:
+ .dw $ff03
+ .db "UDR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR
+XT_UDR:
+ .dw PFA_DOVARIABLE
+PFA_UDR:
+ .dw $2C
+
+.endif
+
+; ********
+.if WANT_WATCHDOG == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCR:
+ .dw $ff05
+ .db "WDTCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCR
+XT_WDTCR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCR:
+ .dw $41
+
+.endif
diff --git a/amforth-6.5/avr8/devices/atmega163/device.py b/amforth-6.5/avr8/devices/atmega163/device.py
new file mode 100644
index 0000000..f344075
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega163/device.py
@@ -0,0 +1,85 @@
+# Partname: ATmega163
+# Built using part description XML file version 207
+# generated automatically, do not edit
+MCUREGS = {
+ 'ADCH': '$25',
+ 'ADCL': '$24',
+ 'ADCSR': '$26',
+ 'ADMUX': '$27',
+ 'ACSR': '$28',
+ 'SFIOR': '$50',
+ 'SPMCR': '$57',
+ 'MCUCR': '$55',
+ 'MCUSR': '$54',
+ 'OSCCAL': '$51',
+ 'SPH': '$5E',
+ 'SPL': '$5D',
+ 'SREG': '$5F',
+ 'EEARH': '$3F',
+ 'EEARL': '$3E',
+ 'EECR': '$3C',
+ 'EEDR': '$3D',
+ 'GIFR': '$5A',
+ 'GIMSK': '$5B',
+ 'DDRA': '$3A',
+ 'PINA': '$39',
+ 'PORTA': '$3B',
+ 'DDRB': '$37',
+ 'PINB': '$36',
+ 'PORTB': '$38',
+ 'DDRC': '$34',
+ 'PINC': '$33',
+ 'PORTC': '$35',
+ 'DDRD': '$31',
+ 'PIND': '$30',
+ 'PORTD': '$32',
+ 'SPCR': '$2D',
+ 'SPDR': '$2F',
+ 'SPSR': '$2E',
+ 'TCCR0': '$53',
+ 'TCNT0': '$52',
+ 'TIFR': '$58',
+ 'TIMSK': '$59',
+ 'ICR1H': '$47',
+ 'ICR1L': '$46',
+ 'OCR1AH': '$4B',
+ 'OCR1AL': '$4A',
+ 'OCR1BH': '$49',
+ 'OCR1BL': '$48',
+ 'TCCR1A': '$4F',
+ 'TCCR1B': '$4E',
+ 'TCNT1H': '$4D',
+ 'TCNT1L': '$4C',
+ 'ASSR': '$42',
+ 'OCR2': '$43',
+ 'TCCR2': '$45',
+ 'TCNT2': '$44',
+ 'TWAR': '$22',
+ 'TWBR': '$20',
+ 'TWCR': '$56',
+ 'TWDR': '$23',
+ 'TWSR': '$21',
+ 'UBRR': '$29',
+ 'UBRRHI': '$40',
+ 'UCSRA': '$2B',
+ 'UCSRB': '$2A',
+ 'UDR': '$2C',
+ 'WDTCR': '$41',
+ 'INT0Addr': '$002',
+ 'INT1Addr': '$004',
+ 'TIMER2_COMPAddr': '$006',
+ 'TIMER2_OVFAddr': '$008',
+ 'TIMER1_CAPTAddr': '$00A',
+ 'TIMER1_COMPAAddr': '$00C',
+ 'TIMER1_COMPBAddr': '$00E',
+ 'TIMER1_OVFAddr': '$010',
+ 'TIMER0_OVFAddr': '$012',
+ 'SPISTCAddr': '$014',
+ 'UARTRXAddr': '$016',
+ 'UARTUDREAddr': '$018',
+ 'UARTTXAddr': '$01A',
+ 'ADCAddr': '$01C',
+ 'EE_RDYAddr': '$01E',
+ 'ANA_COMPAddr': '$020',
+ 'TWIAddr': '$022'
+} \ No newline at end of file
diff --git a/amforth-6.5/avr8/devices/atmega164a/atmega164a.frt b/amforth-6.5/avr8/devices/atmega164a/atmega164a.frt
new file mode 100644
index 0000000..52631ae
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega164a/atmega164a.frt
@@ -0,0 +1,347 @@
+\ Partname: ATmega164A
+\ generated automatically
+
+\ ANALOG_COMPARATOR
+&123 constant ADCSRB \ ADC Control and Status Register B
+ $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer Enable
+&80 constant ACSR \ Analog Comparator Control And Status Register
+ $80 constant ACSR_ACD \ Analog Comparator Disable
+ $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
+ $20 constant ACSR_ACO \ Analog Compare Output
+ $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
+ $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
+ $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
+ $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
+&127 constant DIDR1 \ Digital Input Disable Register 1
+ $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
+ $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
+\ USART0
+&198 constant UDR0 \ USART I/O Data Register
+&192 constant UCSR0A \ USART Control and Status Register A
+ $80 constant UCSR0A_RXC0 \ USART Receive Complete
+ $40 constant UCSR0A_TXC0 \ USART Transmitt Complete
+ $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
+ $10 constant UCSR0A_FE0 \ Framing Error
+ $08 constant UCSR0A_DOR0 \ Data overRun
+ $04 constant UCSR0A_UPE0 \ Parity Error
+ $02 constant UCSR0A_U2X0 \ Double the USART transmission speed
+ $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
+&193 constant UCSR0B \ USART Control and Status Register B
+ $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
+ $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
+ $20 constant UCSR0B_UDRIE0 \ USART Data register Empty Interrupt Enable
+ $10 constant UCSR0B_RXEN0 \ Receiver Enable
+ $08 constant UCSR0B_TXEN0 \ Transmitter Enable
+ $04 constant UCSR0B_UCSZ02 \ Character Size
+ $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
+ $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
+&194 constant UCSR0C \ USART Control and Status Register C
+ $C0 constant UCSR0C_UMSEL0 \ USART Mode Select
+ $30 constant UCSR0C_UPM0 \ Parity Mode Bits
+ $08 constant UCSR0C_USBS0 \ Stop Bit Select
+ $06 constant UCSR0C_UCSZ0 \ Character Size
+ $01 constant UCSR0C_UCPOL0 \ Clock Polarity
+&196 constant UBRR0 \ USART Baud Rate Register Bytes
+\ PORTA
+&34 constant PORTA \ Port A Data Register
+&33 constant DDRA \ Port A Data Direction Register
+&32 constant PINA \ Port A Input Pins
+\ PORTB
+&37 constant PORTB \ Port B Data Register
+&36 constant DDRB \ Port B Data Direction Register
+&35 constant PINB \ Port B Input Pins
+\ PORTC
+&40 constant PORTC \ Port C Data Register
+&39 constant DDRC \ Port C Data Direction Register
+&38 constant PINC \ Port C Input Pins
+\ PORTD
+&43 constant PORTD \ Port D Data Register
+&42 constant DDRD \ Port D Data Direction Register
+&41 constant PIND \ Port D Input Pins
+\ TIMER_COUNTER_0
+&72 constant OCR0B \ Timer/Counter0 Output Compare Register
+&71 constant OCR0A \ Timer/Counter0 Output Compare Register
+&70 constant TCNT0 \ Timer/Counter0
+&69 constant TCCR0B \ Timer/Counter Control Register B
+ $80 constant TCCR0B_FOC0A \ Force Output Compare A
+ $40 constant TCCR0B_FOC0B \ Force Output Compare B
+ $08 constant TCCR0B_WGM02 \
+ $07 constant TCCR0B_CS0 \ Clock Select
+&68 constant TCCR0A \ Timer/Counter Control Register A
+ $C0 constant TCCR0A_COM0A \ Compare Output Mode, Phase Correct PWM Mode
+ $30 constant TCCR0A_COM0B \ Compare Output Mode, Fast PWm
+ $03 constant TCCR0A_WGM0 \ Waveform Generation Mode
+&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
+ $04 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare Match B Interrupt Enable
+ $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match A Interrupt Enable
+ $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
+&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
+ $04 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare Flag 0B
+ $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0A
+ $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
+&67 constant GTCCR \ General Timer/Counter Control Register
+ $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
+ $01 constant GTCCR_PSRSYNC \ Prescaler Reset Timer/Counter1 and Timer/Counter0
+\ TIMER_COUNTER_2
+&112 constant TIMSK2 \ Timer/Counter Interrupt Mask register
+ $04 constant TIMSK2_OCIE2B \ Timer/Counter2 Output Compare Match B Interrupt Enable
+ $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match A Interrupt Enable
+ $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
+&55 constant TIFR2 \ Timer/Counter Interrupt Flag Register
+ $04 constant TIFR2_OCF2B \ Output Compare Flag 2B
+ $02 constant TIFR2_OCF2A \ Output Compare Flag 2A
+ $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
+&176 constant TCCR2A \ Timer/Counter2 Control Register A
+ $C0 constant TCCR2A_COM2A \ Compare Output Mode bits
+ $30 constant TCCR2A_COM2B \ Compare Output Mode bits
+ $03 constant TCCR2A_WGM2 \ Waveform Genration Mode
+&177 constant TCCR2B \ Timer/Counter2 Control Register B
+ $80 constant TCCR2B_FOC2A \ Force Output Compare A
+ $40 constant TCCR2B_FOC2B \ Force Output Compare B
+ $08 constant TCCR2B_WGM22 \ Waveform Generation Mode
+ $07 constant TCCR2B_CS2 \ Clock Select bits
+&178 constant TCNT2 \ Timer/Counter2
+&180 constant OCR2B \ Timer/Counter2 Output Compare Register B
+&179 constant OCR2A \ Timer/Counter2 Output Compare Register A
+&182 constant ASSR \ Asynchronous Status Register
+ $40 constant ASSR_EXCLK \ Enable External Clock Input
+ $20 constant ASSR_AS2 \ Asynchronous Timer/Counter2
+ $10 constant ASSR_TCN2UB \ Timer/Counter2 Update Busy
+ $08 constant ASSR_OCR2AUB \ Output Compare Register2 Update Busy
+ $04 constant ASSR_OCR2BUB \ Output Compare Register 2 Update Busy
+ $02 constant ASSR_TCR2AUB \ Timer/Counter Control Register2 Update Busy
+ $01 constant ASSR_TCR2BUB \ Timer/Counter Control Register2 Update Busy
+\ WATCHDOG
+&96 constant WDTCSR \ Watchdog Timer Control Register
+ $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Flag
+ $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Enable
+ $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
+ $10 constant WDTCSR_WDCE \ Watchdog Change Enable
+ $08 constant WDTCSR_WDE \ Watch Dog Enable
+\ JTAG
+&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
+&85 constant MCUCR \ MCU Control Register
+ $80 constant MCUCR_JTD \ JTAG Interface Disable
+&84 constant MCUSR \ MCU Status Register
+ $10 constant MCUSR_JTRF \ JTAG Reset Flag
+\ BOOT_LOAD
+&87 constant SPMCSR \ Store Program Memory Control Register
+ $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
+ $20 constant SPMCSR_SIGRD \ Signature Row Read
+ $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
+ $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
+ $04 constant SPMCSR_PGWRT \ Page Write
+ $02 constant SPMCSR_PGERS \ Page Erase
+ $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
+\ EXTERNAL_INTERRUPT
+&105 constant EICRA \ External Interrupt Control Register A
+ $30 constant EICRA_ISC2 \ External Interrupt Sense Control Bit
+ $0C constant EICRA_ISC1 \ External Interrupt Sense Control Bit
+ $03 constant EICRA_ISC0 \ External Interrupt Sense Control Bit
+&61 constant EIMSK \ External Interrupt Mask Register
+ $07 constant EIMSK_INT \ External Interrupt Request 2 Enable
+&60 constant EIFR \ External Interrupt Flag Register
+ $07 constant EIFR_INTF \ External Interrupt Flags
+&115 constant PCMSK3 \ Pin Change Mask Register 3
+ $FF constant PCMSK3_PCINT \ Pin Change Enable Masks
+&109 constant PCMSK2 \ Pin Change Mask Register 2
+ $FF constant PCMSK2_PCINT \ Pin Change Enable Masks
+&108 constant PCMSK1 \ Pin Change Mask Register 1
+ $FF constant PCMSK1_PCINT \ Pin Change Enable Masks
+&107 constant PCMSK0 \ Pin Change Mask Register 0
+ $FF constant PCMSK0_PCINT \ Pin Change Enable Masks
+&59 constant PCIFR \ Pin Change Interrupt Flag Register
+ $0F constant PCIFR_PCIF \ Pin Change Interrupt Flags
+&104 constant PCICR \ Pin Change Interrupt Control Register
+ $0F constant PCICR_PCIE \ Pin Change Interrupt Enables
+\ AD_CONVERTER
+&124 constant ADMUX \ The ADC multiplexer Selection Register
+ $C0 constant ADMUX_REFS \ Reference Selection Bits
+ $20 constant ADMUX_ADLAR \ Left Adjust Result
+ $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
+&120 constant ADC \ ADC Data Register Bytes
+&122 constant ADCSRA \ The ADC Control and Status register A
+ $80 constant ADCSRA_ADEN \ ADC Enable
+ $40 constant ADCSRA_ADSC \ ADC Start Conversion
+ $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
+ $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
+ $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
+ $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
+&126 constant DIDR0 \ Digital Input Disable Register
+ $80 constant DIDR0_ADC7D \
+ $40 constant DIDR0_ADC6D \
+ $20 constant DIDR0_ADC5D \
+ $10 constant DIDR0_ADC4D \
+ $08 constant DIDR0_ADC3D \
+ $04 constant DIDR0_ADC2D \
+ $02 constant DIDR0_ADC1D \
+ $01 constant DIDR0_ADC0D \
+\ TIMER_COUNTER_1
+&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
+ $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
+ $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
+ $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
+ $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
+&54 constant TIFR1 \ Timer/Counter Interrupt Flag register
+ $20 constant TIFR1_ICF1 \ Timer/Counter1 Input Capture Flag
+ $04 constant TIFR1_OCF1B \ Timer/Counter1 Output Compare B Match Flag
+ $02 constant TIFR1_OCF1A \ Timer/Counter1 Output Compare A Match Flag
+ $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
+&128 constant TCCR1A \ Timer/Counter1 Control Register A
+ $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
+ $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
+ $03 constant TCCR1A_WGM1 \ Pulse Width Modulator Select Bits
+&129 constant TCCR1B \ Timer/Counter1 Control Register B
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ $18 constant TCCR1B_WGM1 \ Waveform Generation Mode Bits
+ $07 constant TCCR1B_CS1 \ Clock Select1 bits
+&130 constant TCCR1C \ Timer/Counter1 Control Register C
+ $80 constant TCCR1C_FOC1A \ Force Output Compare for Channel A
+ $40 constant TCCR1C_FOC1B \ Force Output Compare for Channel B
+&132 constant TCNT1 \ Timer/Counter1 Bytes
+&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
+&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
+&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
+\ EEPROM
+&65 constant EEAR \ EEPROM Address Register Low Bytes
+&64 constant EEDR \ EEPROM Data Register
+&63 constant EECR \ EEPROM Control Register
+ $30 constant EECR_EEPM \ EEPROM Programming Mode Bits
+ $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
+ $04 constant EECR_EEMPE \ EEPROM Master Write Enable
+ $02 constant EECR_EEPE \ EEPROM Write Enable
+ $01 constant EECR_EERE \ EEPROM Read Enable
+\ SPI
+&78 constant SPDR0 \ SPI Data Register
+&77 constant SPSR0 \ SPI Status Register
+ $80 constant SPSR0_SPIF0 \ SPI Interrupt Flag
+ $40 constant SPSR0_WCOL0 \ Write Collision Flag
+ $01 constant SPSR0_SPI2X0 \ Double SPI Speed Bit
+&76 constant SPCR0 \ SPI Control Register
+ $80 constant SPCR0_SPIE0 \ SPI Interrupt Enable
+ $40 constant SPCR0_SPE0 \ SPI Enable
+ $20 constant SPCR0_DORD0 \ Data Order
+ $10 constant SPCR0_MSTR0 \ Master/Slave Select
+ $08 constant SPCR0_CPOL0 \ Clock polarity
+ $04 constant SPCR0_CPHA0 \ Clock Phase
+ $02 constant SPCR0_SPR10 \ SPI Clock Rate Select 1
+ $01 constant SPCR0_SPR00 \ SPI Clock Rate Select 0
+\ TWI
+&189 constant TWAMR \ TWI (Slave) Address Mask Register
+ $FE constant TWAMR_TWAM \
+&184 constant TWBR \ TWI Bit Rate register
+&188 constant TWCR \ TWI Control Register
+ $80 constant TWCR_TWINT \ TWI Interrupt Flag
+ $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
+ $20 constant TWCR_TWSTA \ TWI Start Condition Bit
+ $10 constant TWCR_TWSTO \ TWI Stop Condition Bit
+ $08 constant TWCR_TWWC \ TWI Write Collition Flag
+ $04 constant TWCR_TWEN \ TWI Enable Bit
+ $01 constant TWCR_TWIE \ TWI Interrupt Enable
+&185 constant TWSR \ TWI Status Register
+ $F8 constant TWSR_TWS \ TWI Status
+ $03 constant TWSR_TWPS \ TWI Prescaler
+&187 constant TWDR \ TWI Data register
+&186 constant TWAR \ TWI (Slave) Address register
+ $FE constant TWAR_TWA \ TWI (Slave) Address register Bits
+ $01 constant TWAR_TWGCE \ TWI General Call Recognition Enable Bit
+\ USART1
+&206 constant UDR1 \ USART I/O Data Register
+&200 constant UCSR1A \ USART Control and Status Register A
+ $80 constant UCSR1A_RXC1 \ USART Receive Complete
+ $40 constant UCSR1A_TXC1 \ USART Transmitt Complete
+ $20 constant UCSR1A_UDRE1 \ USART Data Register Empty
+ $10 constant UCSR1A_FE1 \ Framing Error
+ $08 constant UCSR1A_DOR1 \ Data overRun
+ $04 constant UCSR1A_UPE1 \ Parity Error
+ $02 constant UCSR1A_U2X1 \ Double the USART transmission speed
+ $01 constant UCSR1A_MPCM1 \ Multi-processor Communication Mode
+&201 constant UCSR1B \ USART Control and Status Register B
+ $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable
+ $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable
+ $20 constant UCSR1B_UDRIE1 \ USART Data register Empty Interrupt Enable
+ $10 constant UCSR1B_RXEN1 \ Receiver Enable
+ $08 constant UCSR1B_TXEN1 \ Transmitter Enable
+ $04 constant UCSR1B_UCSZ12 \ Character Size
+ $02 constant UCSR1B_RXB81 \ Receive Data Bit 8
+ $01 constant UCSR1B_TXB81 \ Transmit Data Bit 8
+&202 constant UCSR1C \ USART Control and Status Register C
+ $C0 constant UCSR1C_UMSEL1 \ USART Mode Select
+ $30 constant UCSR1C_UPM1 \ Parity Mode Bits
+ $08 constant UCSR1C_USBS1 \ Stop Bit Select
+ $06 constant UCSR1C_UCSZ1 \ Character Size
+ $01 constant UCSR1C_UCPOL1 \ Clock Polarity
+&204 constant UBRR1 \ USART Baud Rate Register Bytes
+\ CPU
+&95 constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ $08 constant SREG_V \ Two's Complement Overflow Flag
+ $04 constant SREG_N \ Negative Flag
+ $02 constant SREG_Z \ Zero Flag
+ $01 constant SREG_C \ Carry Flag
+&93 constant SP \ Stack Pointer
+&102 constant OSCCAL \ Oscillator Calibration Value
+&97 constant CLKPR \
+ $80 constant CLKPR_CLKPCE \
+ $0F constant CLKPR_CLKPS \
+&83 constant SMCR \ Sleep Mode Control Register
+ $0E constant SMCR_SM \ Sleep Mode Select bits
+ $01 constant SMCR_SE \ Sleep Enable
+&75 constant GPIOR2 \ General Purpose IO Register 2
+ $FF constant GPIOR2_GPIOR \ General Purpose IO Register 2 bis
+&74 constant GPIOR1 \ General Purpose IO Register 1
+ $FF constant GPIOR1_GPIOR \ General Purpose IO Register 1 bis
+&62 constant GPIOR0 \ General Purpose IO Register 0
+ $80 constant GPIOR0_GPIOR07 \ General Purpose IO Register 0 bit 7
+ $40 constant GPIOR0_GPIOR06 \ General Purpose IO Register 0 bit 6
+ $20 constant GPIOR0_GPIOR05 \ General Purpose IO Register 0 bit 5
+ $10 constant GPIOR0_GPIOR04 \ General Purpose IO Register 0 bit 4
+ $08 constant GPIOR0_GPIOR03 \ General Purpose IO Register 0 bit 3
+ $04 constant GPIOR0_GPIOR02 \ General Purpose IO Register 0 bit 2
+ $02 constant GPIOR0_GPIOR01 \ General Purpose IO Register 0 bit 1
+ $01 constant GPIOR0_GPIOR00 \ General Purpose IO Register 0 bit 0
+&100 constant PRR0 \ Power Reduction Register0
+ $80 constant PRR0_PRTWI \ Power Reduction TWI
+ $40 constant PRR0_PRTIM2 \ Power Reduction Timer/Counter2
+ $20 constant PRR0_PRTIM0 \ Power Reduction Timer/Counter0
+ $12 constant PRR0_PRUSART \ Power Reduction USARTs
+ $08 constant PRR0_PRTIM1 \ Power Reduction Timer/Counter1
+ $04 constant PRR0_PRSPI \ Power Reduction Serial Peripheral Interface
+ $01 constant PRR0_PRADC \ Power Reduction ADC
+
+\ Interrupts
+&2 constant INT0Addr \ External Interrupt Request 0
+&4 constant INT1Addr \ External Interrupt Request 1
+&6 constant INT2Addr \ External Interrupt Request 2
+&8 constant PCINT0Addr \ Pin Change Interrupt Request 0
+&10 constant PCINT1Addr \ Pin Change Interrupt Request 1
+&12 constant PCINT2Addr \ Pin Change Interrupt Request 2
+&14 constant PCINT3Addr \ Pin Change Interrupt Request 3
+&16 constant WDTAddr \ Watchdog Time-out Interrupt
+&18 constant TIMER2_COMPAAddr \ Timer/Counter2 Compare Match A
+&20 constant TIMER2_COMPBAddr \ Timer/Counter2 Compare Match B
+&22 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
+&24 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+&26 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
+&28 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
+&30 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+&32 constant TIMER0_COMPAAddr \ Timer/Counter0 Compare Match A
+&34 constant TIMER0_COMPBAddr \ Timer/Counter0 Compare Match B
+&36 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
+&38 constant SPI__STCAddr \ SPI Serial Transfer Complete
+&40 constant USART0__RXAddr \ USART0, Rx Complete
+&42 constant USART0__UDREAddr \ USART0 Data register Empty
+&44 constant USART0__TXAddr \ USART0, Tx Complete
+&46 constant ANALOG_COMPAddr \ Analog Comparator
+&48 constant ADCAddr \ ADC Conversion Complete
+&50 constant EE_READYAddr \ EEPROM Ready
+&52 constant TWIAddr \ 2-wire Serial Interface
+&54 constant SPM_READYAddr \ Store Program Memory Read
+&56 constant USART1_RXAddr \ USART1 RX complete
+&58 constant USART1_UDREAddr \ USART1 Data Register Empty
+&60 constant USART1_TXAddr \ USART1 TX complete
diff --git a/amforth-6.5/avr8/devices/atmega164a/blocks/AD_CONVERTER.frt b/amforth-6.5/avr8/devices/atmega164a/blocks/AD_CONVERTER.frt
new file mode 100644
index 0000000..12944ca
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega164a/blocks/AD_CONVERTER.frt
@@ -0,0 +1,47 @@
+\ Generated automatically for atmega164a
+\ #require bitnames.frt
+
+\ AD_CONVERTER
+$7c constant ADMUX \ The ADC multiplexer Selection
+ $c0 constant ADMUX_REFS \ Reference Selection Bits
+ 7c $c0 bitmask: ADMUX.REFS \ Reference Selection Bits
+ $20 constant ADMUX_ADLAR \ Left Adjust Result
+ 7c $20 bitmask: ADMUX.ADLAR \ Left Adjust Result
+ $1f constant ADMUX_MUX \ Analog Channel and Gain Select
+ 7c $1f bitmask: ADMUX.MUX \ Analog Channel and Gain Select
+$78 constant ADC \ ADC Data Register Bytes
+$7a constant ADCSRA \ The ADC Control and Status reg
+ $80 constant ADCSRA_ADEN \ ADC Enable
+ 7a $80 bitmask: ADCSRA.ADEN \ ADC Enable
+ $40 constant ADCSRA_ADSC \ ADC Start Conversion
+ 7a $40 bitmask: ADCSRA.ADSC \ ADC Start Conversion
+ $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
+ 7a $20 bitmask: ADCSRA.ADATE \ ADC Auto Trigger Enable
+ $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
+ 7a $10 bitmask: ADCSRA.ADIF \ ADC Interrupt Flag
+ $8 constant ADCSRA_ADIE \ ADC Interrupt Enable
+ 7a $8 bitmask: ADCSRA.ADIE \ ADC Interrupt Enable
+ $7 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
+ 7a $7 bitmask: ADCSRA.ADPS \ ADC Prescaler Select Bits
+$7b constant ADCSRB \ The ADC Control and Status reg
+ $40 constant ADCSRB_ACME \
+ 7b $40 bitmask: ADCSRB.ACME \
+ $7 constant ADCSRB_ADTS \ ADC Auto Trigger Source bits
+ 7b $7 bitmask: ADCSRB.ADTS \ ADC Auto Trigger Source bits
+$7e constant DIDR0 \ Digital Input Disable Register
+ $80 constant DIDR0_ADC7D \
+ 7e $80 bitmask: DIDR0.ADC7D \
+ $40 constant DIDR0_ADC6D \
+ 7e $40 bitmask: DIDR0.ADC6D \
+ $20 constant DIDR0_ADC5D \
+ 7e $20 bitmask: DIDR0.ADC5D \
+ $10 constant DIDR0_ADC4D \
+ 7e $10 bitmask: DIDR0.ADC4D \
+ $8 constant DIDR0_ADC3D \
+ 7e $8 bitmask: DIDR0.ADC3D \
+ $4 constant DIDR0_ADC2D \
+ 7e $4 bitmask: DIDR0.ADC2D \
+ $2 constant DIDR0_ADC1D \
+ 7e $2 bitmask: DIDR0.ADC1D \
+ $1 constant DIDR0_ADC0D \
+ 7e $1 bitmask: DIDR0.ADC0D \
diff --git a/amforth-6.5/avr8/devices/atmega164a/blocks/ANALOG_COMPARATOR.frt b/amforth-6.5/avr8/devices/atmega164a/blocks/ANALOG_COMPARATOR.frt
new file mode 100644
index 0000000..b7caf2f
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega164a/blocks/ANALOG_COMPARATOR.frt
@@ -0,0 +1,27 @@
+\ Generated automatically for atmega164a
+\ #require bitnames.frt
+
+\ ANALOG_COMPARATOR
+$7b constant ADCSRB \ ADC Control and Status Registe
+ $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer
+ 7b $40 bitmask: ADCSRB.ACME \ Analog Comparator Multiplexer
+$50 constant ACSR \ Analog Comparator Control And
+ $80 constant ACSR_ACD \ Analog Comparator Disable
+ 50 $80 bitmask: ACSR.ACD \ Analog Comparator Disable
+ $40 constant ACSR_ACBG \ Analog Comparator Bandgap Sele
+ 50 $40 bitmask: ACSR.ACBG \ Analog Comparator Bandgap Sele
+ $20 constant ACSR_ACO \ Analog Compare Output
+ 50 $20 bitmask: ACSR.ACO \ Analog Compare Output
+ $10 constant ACSR_ACI \ Analog Comparator Interrupt Fl
+ 50 $10 bitmask: ACSR.ACI \ Analog Comparator Interrupt Fl
+ $8 constant ACSR_ACIE \ Analog Comparator Interrupt En
+ 50 $8 bitmask: ACSR.ACIE \ Analog Comparator Interrupt En
+ $4 constant ACSR_ACIC \ Analog Comparator Input Captur
+ 50 $4 bitmask: ACSR.ACIC \ Analog Comparator Input Captur
+ $3 constant ACSR_ACIS \ Analog Comparator Interrupt Mo
+ 50 $3 bitmask: ACSR.ACIS \ Analog Comparator Interrupt Mo
+$7f constant DIDR1 \ Digital Input Disable Register
+ $2 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
+ 7f $2 bitmask: DIDR1.AIN1D \ AIN1 Digital Input Disable
+ $1 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
+ 7f $1 bitmask: DIDR1.AIN0D \ AIN0 Digital Input Disable
diff --git a/amforth-6.5/avr8/devices/atmega164a/blocks/BOOT_LOAD.frt b/amforth-6.5/avr8/devices/atmega164a/blocks/BOOT_LOAD.frt
new file mode 100644
index 0000000..d229c7f
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega164a/blocks/BOOT_LOAD.frt
@@ -0,0 +1,21 @@
+\ Generated automatically for atmega164a
+\ #require bitnames.frt
+
+\ BOOT_LOAD
+$57 constant SPMCSR \ Store Program Memory Control R
+ $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
+ 57 $80 bitmask: SPMCSR.SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
+ 57 $40 bitmask: SPMCSR.RWWSB \ Read While Write Section Busy
+ $20 constant SPMCSR_SIGRD \ Signature Row Read
+ 57 $20 bitmask: SPMCSR.SIGRD \ Signature Row Read
+ $10 constant SPMCSR_RWWSRE \ Read While Write section read
+ 57 $10 bitmask: SPMCSR.RWWSRE \ Read While Write section read
+ $8 constant SPMCSR_BLBSET \ Boot Lock Bit Set
+ 57 $8 bitmask: SPMCSR.BLBSET \ Boot Lock Bit Set
+ $4 constant SPMCSR_PGWRT \ Page Write
+ 57 $4 bitmask: SPMCSR.PGWRT \ Page Write
+ $2 constant SPMCSR_PGERS \ Page Erase
+ 57 $2 bitmask: SPMCSR.PGERS \ Page Erase
+ $1 constant SPMCSR_SPMEN \ Store Program Memory Enable
+ 57 $1 bitmask: SPMCSR.SPMEN \ Store Program Memory Enable
diff --git a/amforth-6.5/avr8/devices/atmega164a/blocks/CPU.frt b/amforth-6.5/avr8/devices/atmega164a/blocks/CPU.frt
new file mode 100644
index 0000000..bbf9d5c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega164a/blocks/CPU.frt
@@ -0,0 +1,91 @@
+\ Generated automatically for atmega164a
+\ #require bitnames.frt
+
+\ CPU
+$5f constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ 5f $80 bitmask: SREG.I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ 5f $40 bitmask: SREG.T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ 5f $20 bitmask: SREG.H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ 5f $10 bitmask: SREG.S \ Sign Bit
+ $8 constant SREG_V \ Two's Complement Overflow Flag
+ 5f $8 bitmask: SREG.V \ Two's Complement Overflow Flag
+ $4 constant SREG_N \ Negative Flag
+ 5f $4 bitmask: SREG.N \ Negative Flag
+ $2 constant SREG_Z \ Zero Flag
+ 5f $2 bitmask: SREG.Z \ Zero Flag
+ $1 constant SREG_C \ Carry Flag
+ 5f $1 bitmask: SREG.C \ Carry Flag
+$5d constant SP \ Stack Pointer
+$55 constant MCUCR \ MCU Control Register
+ $80 constant MCUCR_JTD \ JTAG Interface Disable
+ 55 $80 bitmask: MCUCR.JTD \ JTAG Interface Disable
+ $10 constant MCUCR_PUD \ Pull-up disable
+ 55 $10 bitmask: MCUCR.PUD \ Pull-up disable
+ $2 constant MCUCR_IVSEL \ Interrupt Vector Select
+ 55 $2 bitmask: MCUCR.IVSEL \ Interrupt Vector Select
+ $1 constant MCUCR_IVCE \ Interrupt Vector Change Enable
+ 55 $1 bitmask: MCUCR.IVCE \ Interrupt Vector Change Enable
+$54 constant MCUSR \ MCU Status Register
+ $10 constant MCUSR_JTRF \ JTAG Reset Flag
+ 54 $10 bitmask: MCUSR.JTRF \ JTAG Reset Flag
+ $8 constant MCUSR_WDRF \ Watchdog Reset Flag
+ 54 $8 bitmask: MCUSR.WDRF \ Watchdog Reset Flag
+ $4 constant MCUSR_BORF \ Brown-out Reset Flag
+ 54 $4 bitmask: MCUSR.BORF \ Brown-out Reset Flag
+ $2 constant MCUSR_EXTRF \ External Reset Flag
+ 54 $2 bitmask: MCUSR.EXTRF \ External Reset Flag
+ $1 constant MCUSR_PORF \ Power-on reset flag
+ 54 $1 bitmask: MCUSR.PORF \ Power-on reset flag
+$66 constant OSCCAL \ Oscillator Calibration Value
+$61 constant CLKPR \
+ $80 constant CLKPR_CLKPCE \
+ 61 $80 bitmask: CLKPR.CLKPCE \
+ $f constant CLKPR_CLKPS \
+ 61 $f bitmask: CLKPR.CLKPS \
+$53 constant SMCR \ Sleep Mode Control Register
+ $e constant SMCR_SM \ Sleep Mode Select bits
+ 53 $e bitmask: SMCR.SM \ Sleep Mode Select bits
+ $1 constant SMCR_SE \ Sleep Enable
+ 53 $1 bitmask: SMCR.SE \ Sleep Enable
+$4b constant GPIOR2 \ General Purpose IO Register 2
+ $ff constant GPIOR2_GPIOR \ General Purpose IO Register 2
+ 4b $ff bitmask: GPIOR2.GPIOR \ General Purpose IO Register 2
+$4a constant GPIOR1 \ General Purpose IO Register 1
+ $ff constant GPIOR1_GPIOR \ General Purpose IO Register 1
+ 4a $ff bitmask: GPIOR1.GPIOR \ General Purpose IO Register 1
+$3e constant GPIOR0 \ General Purpose IO Register 0
+ $80 constant GPIOR0_GPIOR07 \ General Purpose IO Register 0
+ 3e $80 bitmask: GPIOR0.GPIOR07 \ General Purpose IO Register 0
+ $40 constant GPIOR0_GPIOR06 \ General Purpose IO Register 0
+ 3e $40 bitmask: GPIOR0.GPIOR06 \ General Purpose IO Register 0
+ $20 constant GPIOR0_GPIOR05 \ General Purpose IO Register 0
+ 3e $20 bitmask: GPIOR0.GPIOR05 \ General Purpose IO Register 0
+ $10 constant GPIOR0_GPIOR04 \ General Purpose IO Register 0
+ 3e $10 bitmask: GPIOR0.GPIOR04 \ General Purpose IO Register 0
+ $8 constant GPIOR0_GPIOR03 \ General Purpose IO Register 0
+ 3e $8 bitmask: GPIOR0.GPIOR03 \ General Purpose IO Register 0
+ $4 constant GPIOR0_GPIOR02 \ General Purpose IO Register 0
+ 3e $4 bitmask: GPIOR0.GPIOR02 \ General Purpose IO Register 0
+ $2 constant GPIOR0_GPIOR01 \ General Purpose IO Register 0
+ 3e $2 bitmask: GPIOR0.GPIOR01 \ General Purpose IO Register 0
+ $1 constant GPIOR0_GPIOR00 \ General Purpose IO Register 0
+ 3e $1 bitmask: GPIOR0.GPIOR00 \ General Purpose IO Register 0
+$64 constant PRR0 \ Power Reduction Register0
+ $80 constant PRR0_PRTWI \ Power Reduction TWI
+ 64 $80 bitmask: PRR0.PRTWI \ Power Reduction TWI
+ $40 constant PRR0_PRTIM2 \ Power Reduction Timer/Counter2
+ 64 $40 bitmask: PRR0.PRTIM2 \ Power Reduction Timer/Counter2
+ $20 constant PRR0_PRTIM0 \ Power Reduction Timer/Counter0
+ 64 $20 bitmask: PRR0.PRTIM0 \ Power Reduction Timer/Counter0
+ $12 constant PRR0_PRUSART \ Power Reduction USARTs
+ 64 $12 bitmask: PRR0.PRUSART \ Power Reduction USARTs
+ $8 constant PRR0_PRTIM1 \ Power Reduction Timer/Counter1
+ 64 $8 bitmask: PRR0.PRTIM1 \ Power Reduction Timer/Counter1
+ $4 constant PRR0_PRSPI \ Power Reduction Serial Periphe
+ 64 $4 bitmask: PRR0.PRSPI \ Power Reduction Serial Periphe
+ $1 constant PRR0_PRADC \ Power Reduction ADC
+ 64 $1 bitmask: PRR0.PRADC \ Power Reduction ADC
diff --git a/amforth-6.5/avr8/devices/atmega164a/blocks/EEPROM.frt b/amforth-6.5/avr8/devices/atmega164a/blocks/EEPROM.frt
new file mode 100644
index 0000000..b18c275
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega164a/blocks/EEPROM.frt
@@ -0,0 +1,17 @@
+\ Generated automatically for atmega164a
+\ #require bitnames.frt
+
+\ EEPROM
+$41 constant EEAR \ EEPROM Address Register Low By
+$40 constant EEDR \ EEPROM Data Register
+$3f constant EECR \ EEPROM Control Register
+ $30 constant EECR_EEPM \ EEPROM Programming Mode Bits
+ 3f $30 bitmask: EECR.EEPM \ EEPROM Programming Mode Bits
+ $8 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
+ 3f $8 bitmask: EECR.EERIE \ EEPROM Ready Interrupt Enable
+ $4 constant EECR_EEMPE \ EEPROM Master Write Enable
+ 3f $4 bitmask: EECR.EEMPE \ EEPROM Master Write Enable
+ $2 constant EECR_EEPE \ EEPROM Write Enable
+ 3f $2 bitmask: EECR.EEPE \ EEPROM Write Enable
+ $1 constant EECR_EERE \ EEPROM Read Enable
+ 3f $1 bitmask: EECR.EERE \ EEPROM Read Enable
diff --git a/amforth-6.5/avr8/devices/atmega164a/blocks/EXTERNAL_INTERRUPT.frt b/amforth-6.5/avr8/devices/atmega164a/blocks/EXTERNAL_INTERRUPT.frt
new file mode 100644
index 0000000..13ed947
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega164a/blocks/EXTERNAL_INTERRUPT.frt
@@ -0,0 +1,35 @@
+\ Generated automatically for atmega164a
+\ #require bitnames.frt
+
+\ EXTERNAL_INTERRUPT
+$69 constant EICRA \ External Interrupt Control Reg
+ $30 constant EICRA_ISC2 \ External Interrupt Sense Contr
+ 69 $30 bitmask: EICRA.ISC2 \ External Interrupt Sense Contr
+ $c constant EICRA_ISC1 \ External Interrupt Sense Contr
+ 69 $c bitmask: EICRA.ISC1 \ External Interrupt Sense Contr
+ $3 constant EICRA_ISC0 \ External Interrupt Sense Contr
+ 69 $3 bitmask: EICRA.ISC0 \ External Interrupt Sense Contr
+$3d constant EIMSK \ External Interrupt Mask Regist
+ $7 constant EIMSK_INT \ External Interrupt Request 2 E
+ 3d $7 bitmask: EIMSK.INT \ External Interrupt Request 2 E
+$3c constant EIFR \ External Interrupt Flag Regist
+ $7 constant EIFR_INTF \ External Interrupt Flags
+ 3c $7 bitmask: EIFR.INTF \ External Interrupt Flags
+$73 constant PCMSK3 \ Pin Change Mask Register 3
+ $ff constant PCMSK3_PCINT \ Pin Change Enable Masks
+ 73 $ff bitmask: PCMSK3.PCINT \ Pin Change Enable Masks
+$6d constant PCMSK2 \ Pin Change Mask Register 2
+ $ff constant PCMSK2_PCINT \ Pin Change Enable Masks
+ 6d $ff bitmask: PCMSK2.PCINT \ Pin Change Enable Masks
+$6c constant PCMSK1 \ Pin Change Mask Register 1
+ $ff constant PCMSK1_PCINT \ Pin Change Enable Masks
+ 6c $ff bitmask: PCMSK1.PCINT \ Pin Change Enable Masks
+$6b constant PCMSK0 \ Pin Change Mask Register 0
+ $ff constant PCMSK0_PCINT \ Pin Change Enable Masks
+ 6b $ff bitmask: PCMSK0.PCINT \ Pin Change Enable Masks
+$3b constant PCIFR \ Pin Change Interrupt Flag Regi
+ $f constant PCIFR_PCIF \ Pin Change Interrupt Flags
+ 3b $f bitmask: PCIFR.PCIF \ Pin Change Interrupt Flags
+$68 constant PCICR \ Pin Change Interrupt Control R
+ $f constant PCICR_PCIE \ Pin Change Interrupt Enables
+ 68 $f bitmask: PCICR.PCIE \ Pin Change Interrupt Enables
diff --git a/amforth-6.5/avr8/devices/atmega164a/blocks/JTAG.frt b/amforth-6.5/avr8/devices/atmega164a/blocks/JTAG.frt
new file mode 100644
index 0000000..cd82742
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega164a/blocks/JTAG.frt
@@ -0,0 +1,11 @@
+\ Generated automatically for atmega164a
+\ #require bitnames.frt
+
+\ JTAG
+$51 constant OCDR \ On-Chip Debug Related Register
+$55 constant MCUCR \ MCU Control Register
+ $80 constant MCUCR_JTD \ JTAG Interface Disable
+ 55 $80 bitmask: MCUCR.JTD \ JTAG Interface Disable
+$54 constant MCUSR \ MCU Status Register
+ $10 constant MCUSR_JTRF \ JTAG Reset Flag
+ 54 $10 bitmask: MCUSR.JTRF \ JTAG Reset Flag
diff --git a/amforth-6.5/avr8/devices/atmega164a/blocks/PORTA.frt b/amforth-6.5/avr8/devices/atmega164a/blocks/PORTA.frt
new file mode 100644
index 0000000..afbaa67
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega164a/blocks/PORTA.frt
@@ -0,0 +1,7 @@
+\ Generated automatically for atmega164a
+\ #require bitnames.frt
+
+\ PORTA
+$22 constant PORTA \ Port A Data Register
+$21 constant DDRA \ Port A Data Direction Register
+$20 constant PINA \ Port A Input Pins
diff --git a/amforth-6.5/avr8/devices/atmega164a/blocks/PORTB.frt b/amforth-6.5/avr8/devices/atmega164a/blocks/PORTB.frt
new file mode 100644
index 0000000..0ec791c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega164a/blocks/PORTB.frt
@@ -0,0 +1,7 @@
+\ Generated automatically for atmega164a
+\ #require bitnames.frt
+
+\ PORTB
+$25 constant PORTB \ Port B Data Register
+$24 constant DDRB \ Port B Data Direction Register
+$23 constant PINB \ Port B Input Pins
diff --git a/amforth-6.5/avr8/devices/atmega164a/blocks/PORTC.frt b/amforth-6.5/avr8/devices/atmega164a/blocks/PORTC.frt
new file mode 100644
index 0000000..9855199
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega164a/blocks/PORTC.frt
@@ -0,0 +1,7 @@
+\ Generated automatically for atmega164a
+\ #require bitnames.frt
+
+\ PORTC
+$28 constant PORTC \ Port C Data Register
+$27 constant DDRC \ Port C Data Direction Register
+$26 constant PINC \ Port C Input Pins
diff --git a/amforth-6.5/avr8/devices/atmega164a/blocks/PORTD.frt b/amforth-6.5/avr8/devices/atmega164a/blocks/PORTD.frt
new file mode 100644
index 0000000..9015b02
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega164a/blocks/PORTD.frt
@@ -0,0 +1,7 @@
+\ Generated automatically for atmega164a
+\ #require bitnames.frt
+
+\ PORTD
+$2b constant PORTD \ Port D Data Register
+$2a constant DDRD \ Port D Data Direction Register
+$29 constant PIND \ Port D Input Pins
diff --git a/amforth-6.5/avr8/devices/atmega164a/blocks/SPI.frt b/amforth-6.5/avr8/devices/atmega164a/blocks/SPI.frt
new file mode 100644
index 0000000..c548ee9
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega164a/blocks/SPI.frt
@@ -0,0 +1,29 @@
+\ Generated automatically for atmega164a
+\ #require bitnames.frt
+
+\ SPI
+$4e constant SPDR0 \ SPI Data Register
+$4d constant SPSR0 \ SPI Status Register
+ $80 constant SPSR0_SPIF0 \ SPI Interrupt Flag
+ 4d $80 bitmask: SPSR0.SPIF0 \ SPI Interrupt Flag
+ $40 constant SPSR0_WCOL0 \ Write Collision Flag
+ 4d $40 bitmask: SPSR0.WCOL0 \ Write Collision Flag
+ $1 constant SPSR0_SPI2X0 \ Double SPI Speed Bit
+ 4d $1 bitmask: SPSR0.SPI2X0 \ Double SPI Speed Bit
+$4c constant SPCR0 \ SPI Control Register
+ $80 constant SPCR0_SPIE0 \ SPI Interrupt Enable
+ 4c $80 bitmask: SPCR0.SPIE0 \ SPI Interrupt Enable
+ $40 constant SPCR0_SPE0 \ SPI Enable
+ 4c $40 bitmask: SPCR0.SPE0 \ SPI Enable
+ $20 constant SPCR0_DORD0 \ Data Order
+ 4c $20 bitmask: SPCR0.DORD0 \ Data Order
+ $10 constant SPCR0_MSTR0 \ Master/Slave Select
+ 4c $10 bitmask: SPCR0.MSTR0 \ Master/Slave Select
+ $8 constant SPCR0_CPOL0 \ Clock polarity
+ 4c $8 bitmask: SPCR0.CPOL0 \ Clock polarity
+ $4 constant SPCR0_CPHA0 \ Clock Phase
+ 4c $4 bitmask: SPCR0.CPHA0 \ Clock Phase
+ $2 constant SPCR0_SPR10 \ SPI Clock Rate Select 1
+ 4c $2 bitmask: SPCR0.SPR10 \ SPI Clock Rate Select 1
+ $1 constant SPCR0_SPR00 \ SPI Clock Rate Select 0
+ 4c $1 bitmask: SPCR0.SPR00 \ SPI Clock Rate Select 0
diff --git a/amforth-6.5/avr8/devices/atmega164a/blocks/TIMER_COUNTER_0.frt b/amforth-6.5/avr8/devices/atmega164a/blocks/TIMER_COUNTER_0.frt
new file mode 100644
index 0000000..c2de345
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega164a/blocks/TIMER_COUNTER_0.frt
@@ -0,0 +1,42 @@
+\ Generated automatically for atmega164a
+\ #require bitnames.frt
+
+\ TIMER_COUNTER_0
+$48 constant OCR0B \ Timer/Counter0 Output Compare
+$47 constant OCR0A \ Timer/Counter0 Output Compare
+$46 constant TCNT0 \ Timer/Counter0
+$45 constant TCCR0B \ Timer/Counter Control Register
+ $80 constant TCCR0B_FOC0A \ Force Output Compare A
+ 45 $80 bitmask: TCCR0B.FOC0A \ Force Output Compare A
+ $40 constant TCCR0B_FOC0B \ Force Output Compare B
+ 45 $40 bitmask: TCCR0B.FOC0B \ Force Output Compare B
+ $8 constant TCCR0B_WGM02 \
+ 45 $8 bitmask: TCCR0B.WGM02 \
+ $7 constant TCCR0B_CS0 \ Clock Select
+ 45 $7 bitmask: TCCR0B.CS0 \ Clock Select
+$44 constant TCCR0A \ Timer/Counter Control Registe
+ $c0 constant TCCR0A_COM0A \ Compare Output Mode, Phase Cor
+ 44 $c0 bitmask: TCCR0A.COM0A \ Compare Output Mode, Phase Cor
+ $30 constant TCCR0A_COM0B \ Compare Output Mode, Fast PWm
+ 44 $30 bitmask: TCCR0A.COM0B \ Compare Output Mode, Fast PWm
+ $3 constant TCCR0A_WGM0 \ Waveform Generation Mode
+ 44 $3 bitmask: TCCR0A.WGM0 \ Waveform Generation Mode
+$6e constant TIMSK0 \ Timer/Counter0 Interrupt Mask
+ $4 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare
+ 6e $4 bitmask: TIMSK0.OCIE0B \ Timer/Counter0 Output Compare
+ $2 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare
+ 6e $2 bitmask: TIMSK0.OCIE0A \ Timer/Counter0 Output Compare
+ $1 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interr
+ 6e $1 bitmask: TIMSK0.TOIE0 \ Timer/Counter0 Overflow Interr
+$35 constant TIFR0 \ Timer/Counter0 Interrupt Flag
+ $4 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare
+ 35 $4 bitmask: TIFR0.OCF0B \ Timer/Counter0 Output Compare
+ $2 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare
+ 35 $2 bitmask: TIFR0.OCF0A \ Timer/Counter0 Output Compare
+ $1 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
+ 35 $1 bitmask: TIFR0.TOV0 \ Timer/Counter0 Overflow Flag
+$43 constant GTCCR \ General Timer/Counter Control
+ $80 constant GTCCR_TSM \ Timer/Counter Synchronization
+ 43 $80 bitmask: GTCCR.TSM \ Timer/Counter Synchronization
+ $1 constant GTCCR_PSRSYNC \ Prescaler Reset Timer/Counter1
+ 43 $1 bitmask: GTCCR.PSRSYNC \ Prescaler Reset Timer/Counter1
diff --git a/amforth-6.5/avr8/devices/atmega164a/blocks/TIMER_COUNTER_1.frt b/amforth-6.5/avr8/devices/atmega164a/blocks/TIMER_COUNTER_1.frt
new file mode 100644
index 0000000..43e5db2
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega164a/blocks/TIMER_COUNTER_1.frt
@@ -0,0 +1,47 @@
+\ Generated automatically for atmega164a
+\ #require bitnames.frt
+
+\ TIMER_COUNTER_1
+$6f constant TIMSK1 \ Timer/Counter1 Interrupt Mask
+ $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture I
+ 6f $20 bitmask: TIMSK1.ICIE1 \ Timer/Counter1 Input Capture I
+ $4 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare
+ 6f $4 bitmask: TIMSK1.OCIE1B \ Timer/Counter1 Output Compare
+ $2 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare
+ 6f $2 bitmask: TIMSK1.OCIE1A \ Timer/Counter1 Output Compare
+ $1 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interr
+ 6f $1 bitmask: TIMSK1.TOIE1 \ Timer/Counter1 Overflow Interr
+$36 constant TIFR1 \ Timer/Counter Interrupt Flag r
+ $20 constant TIFR1_ICF1 \ Timer/Counter1 Input Capture F
+ 36 $20 bitmask: TIFR1.ICF1 \ Timer/Counter1 Input Capture F
+ $4 constant TIFR1_OCF1B \ Timer/Counter1 Output Compare
+ 36 $4 bitmask: TIFR1.OCF1B \ Timer/Counter1 Output Compare
+ $2 constant TIFR1_OCF1A \ Timer/Counter1 Output Compare
+ 36 $2 bitmask: TIFR1.OCF1A \ Timer/Counter1 Output Compare
+ $1 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
+ 36 $1 bitmask: TIFR1.TOV1 \ Timer/Counter1 Overflow Flag
+$80 constant TCCR1A \ Timer/Counter1 Control Registe
+ $c0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
+ 80 $c0 bitmask: TCCR1A.COM1A \ Compare Output Mode 1A, bits
+ $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
+ 80 $30 bitmask: TCCR1A.COM1B \ Compare Output Mode 1B, bits
+ $3 constant TCCR1A_WGM1 \ Pulse Width Modulator Select B
+ 80 $3 bitmask: TCCR1A.WGM1 \ Pulse Width Modulator Select B
+$81 constant TCCR1B \ Timer/Counter1 Control Registe
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
+ 81 $80 bitmask: TCCR1B.ICNC1 \ Input Capture 1 Noise Canceler
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ 81 $40 bitmask: TCCR1B.ICES1 \ Input Capture 1 Edge Select
+ $18 constant TCCR1B_WGM1 \ Waveform Generation Mode Bits
+ 81 $18 bitmask: TCCR1B.WGM1 \ Waveform Generation Mode Bits
+ $7 constant TCCR1B_CS1 \ Clock Select1 bits
+ 81 $7 bitmask: TCCR1B.CS1 \ Clock Select1 bits
+$82 constant TCCR1C \ Timer/Counter1 Control Registe
+ $80 constant TCCR1C_FOC1A \ Force Output Compare for Chann
+ 82 $80 bitmask: TCCR1C.FOC1A \ Force Output Compare for Chann
+ $40 constant TCCR1C_FOC1B \ Force Output Compare for Chann
+ 82 $40 bitmask: TCCR1C.FOC1B \ Force Output Compare for Chann
+$84 constant TCNT1 \ Timer/Counter1 Bytes
+$88 constant OCR1A \ Timer/Counter1 Output Compare
+$8a constant OCR1B \ Timer/Counter1 Output Compare
+$86 constant ICR1 \ Timer/Counter1 Input Capture R
diff --git a/amforth-6.5/avr8/devices/atmega164a/blocks/TIMER_COUNTER_2.frt b/amforth-6.5/avr8/devices/atmega164a/blocks/TIMER_COUNTER_2.frt
new file mode 100644
index 0000000..2dd0720
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega164a/blocks/TIMER_COUNTER_2.frt
@@ -0,0 +1,57 @@
+\ Generated automatically for atmega164a
+\ #require bitnames.frt
+
+\ TIMER_COUNTER_2
+$70 constant TIMSK2 \ Timer/Counter Interrupt Mask r
+ $4 constant TIMSK2_OCIE2B \ Timer/Counter2 Output Compare
+ 70 $4 bitmask: TIMSK2.OCIE2B \ Timer/Counter2 Output Compare
+ $2 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare
+ 70 $2 bitmask: TIMSK2.OCIE2A \ Timer/Counter2 Output Compare
+ $1 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interr
+ 70 $1 bitmask: TIMSK2.TOIE2 \ Timer/Counter2 Overflow Interr
+$37 constant TIFR2 \ Timer/Counter Interrupt Flag R
+ $4 constant TIFR2_OCF2B \ Output Compare Flag 2B
+ 37 $4 bitmask: TIFR2.OCF2B \ Output Compare Flag 2B
+ $2 constant TIFR2_OCF2A \ Output Compare Flag 2A
+ 37 $2 bitmask: TIFR2.OCF2A \ Output Compare Flag 2A
+ $1 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
+ 37 $1 bitmask: TIFR2.TOV2 \ Timer/Counter2 Overflow Flag
+$b0 constant TCCR2A \ Timer/Counter2 Control Registe
+ $c0 constant TCCR2A_COM2A \ Compare Output Mode bits
+ b0 $c0 bitmask: TCCR2A.COM2A \ Compare Output Mode bits
+ $30 constant TCCR2A_COM2B \ Compare Output Mode bits
+ b0 $30 bitmask: TCCR2A.COM2B \ Compare Output Mode bits
+ $3 constant TCCR2A_WGM2 \ Waveform Genration Mode
+ b0 $3 bitmask: TCCR2A.WGM2 \ Waveform Genration Mode
+$b1 constant TCCR2B \ Timer/Counter2 Control Registe
+ $80 constant TCCR2B_FOC2A \ Force Output Compare A
+ b1 $80 bitmask: TCCR2B.FOC2A \ Force Output Compare A
+ $40 constant TCCR2B_FOC2B \ Force Output Compare B
+ b1 $40 bitmask: TCCR2B.FOC2B \ Force Output Compare B
+ $8 constant TCCR2B_WGM22 \ Waveform Generation Mode
+ b1 $8 bitmask: TCCR2B.WGM22 \ Waveform Generation Mode
+ $7 constant TCCR2B_CS2 \ Clock Select bits
+ b1 $7 bitmask: TCCR2B.CS2 \ Clock Select bits
+$b2 constant TCNT2 \ Timer/Counter2
+$b4 constant OCR2B \ Timer/Counter2 Output Compare
+$b3 constant OCR2A \ Timer/Counter2 Output Compare
+$b6 constant ASSR \ Asynchronous Status Register
+ $40 constant ASSR_EXCLK \ Enable External Clock Input
+ b6 $40 bitmask: ASSR.EXCLK \ Enable External Clock Input
+ $20 constant ASSR_AS2 \ Asynchronous Timer/Counter2
+ b6 $20 bitmask: ASSR.AS2 \ Asynchronous Timer/Counter2
+ $10 constant ASSR_TCN2UB \ Timer/Counter2 Update Busy
+ b6 $10 bitmask: ASSR.TCN2UB \ Timer/Counter2 Update Busy
+ $8 constant ASSR_OCR2AUB \ Output Compare Register2 Updat
+ b6 $8 bitmask: ASSR.OCR2AUB \ Output Compare Register2 Updat
+ $4 constant ASSR_OCR2BUB \ Output Compare Register 2 Upda
+ b6 $4 bitmask: ASSR.OCR2BUB \ Output Compare Register 2 Upda
+ $2 constant ASSR_TCR2AUB \ Timer/Counter Control Register
+ b6 $2 bitmask: ASSR.TCR2AUB \ Timer/Counter Control Register
+ $1 constant ASSR_TCR2BUB \ Timer/Counter Control Register
+ b6 $1 bitmask: ASSR.TCR2BUB \ Timer/Counter Control Register
+$43 constant GTCCR \ General Timer Counter Control
+ $80 constant GTCCR_TSM \ Timer/Counter Synchronization
+ 43 $80 bitmask: GTCCR.TSM \ Timer/Counter Synchronization
+ $2 constant GTCCR_PSRASY \ Prescaler Reset Timer/Counter2
+ 43 $2 bitmask: GTCCR.PSRASY \ Prescaler Reset Timer/Counter2
diff --git a/amforth-6.5/avr8/devices/atmega164a/blocks/TWI.frt b/amforth-6.5/avr8/devices/atmega164a/blocks/TWI.frt
new file mode 100644
index 0000000..d30b667
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega164a/blocks/TWI.frt
@@ -0,0 +1,34 @@
+\ Generated automatically for atmega164a
+\ #require bitnames.frt
+
+\ TWI
+$bd constant TWAMR \ TWI (Slave) Address Mask Regis
+ $fe constant TWAMR_TWAM \
+ bd $fe bitmask: TWAMR.TWAM \
+$b8 constant TWBR \ TWI Bit Rate register
+$bc constant TWCR \ TWI Control Register
+ $80 constant TWCR_TWINT \ TWI Interrupt Flag
+ bc $80 bitmask: TWCR.TWINT \ TWI Interrupt Flag
+ $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
+ bc $40 bitmask: TWCR.TWEA \ TWI Enable Acknowledge Bit
+ $20 constant TWCR_TWSTA \ TWI Start Condition Bit
+ bc $20 bitmask: TWCR.TWSTA \ TWI Start Condition Bit
+ $10 constant TWCR_TWSTO \ TWI Stop Condition Bit
+ bc $10 bitmask: TWCR.TWSTO \ TWI Stop Condition Bit
+ $8 constant TWCR_TWWC \ TWI Write Collition Flag
+ bc $8 bitmask: TWCR.TWWC \ TWI Write Collition Flag
+ $4 constant TWCR_TWEN \ TWI Enable Bit
+ bc $4 bitmask: TWCR.TWEN \ TWI Enable Bit
+ $1 constant TWCR_TWIE \ TWI Interrupt Enable
+ bc $1 bitmask: TWCR.TWIE \ TWI Interrupt Enable
+$b9 constant TWSR \ TWI Status Register
+ $f8 constant TWSR_TWS \ TWI Status
+ b9 $f8 bitmask: TWSR.TWS \ TWI Status
+ $3 constant TWSR_TWPS \ TWI Prescaler
+ b9 $3 bitmask: TWSR.TWPS \ TWI Prescaler
+$bb constant TWDR \ TWI Data register
+$ba constant TWAR \ TWI (Slave) Address register
+ $fe constant TWAR_TWA \ TWI (Slave) Address register B
+ ba $fe bitmask: TWAR.TWA \ TWI (Slave) Address register B
+ $1 constant TWAR_TWGCE \ TWI General Call Recognition E
+ ba $1 bitmask: TWAR.TWGCE \ TWI General Call Recognition E
diff --git a/amforth-6.5/avr8/devices/atmega164a/blocks/USART0.frt b/amforth-6.5/avr8/devices/atmega164a/blocks/USART0.frt
new file mode 100644
index 0000000..ae51362
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega164a/blocks/USART0.frt
@@ -0,0 +1,51 @@
+\ Generated automatically for atmega164a
+\ #require bitnames.frt
+
+\ USART0
+$c6 constant UDR0 \ USART I/O Data Register
+$c0 constant UCSR0A \ USART Control and Status Regis
+ $80 constant UCSR0A_RXC0 \ USART Receive Complete
+ c0 $80 bitmask: UCSR0A.RXC0 \ USART Receive Complete
+ $40 constant UCSR0A_TXC0 \ USART Transmitt Complete
+ c0 $40 bitmask: UCSR0A.TXC0 \ USART Transmitt Complete
+ $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
+ c0 $20 bitmask: UCSR0A.UDRE0 \ USART Data Register Empty
+ $10 constant UCSR0A_FE0 \ Framing Error
+ c0 $10 bitmask: UCSR0A.FE0 \ Framing Error
+ $8 constant UCSR0A_DOR0 \ Data overRun
+ c0 $8 bitmask: UCSR0A.DOR0 \ Data overRun
+ $4 constant UCSR0A_UPE0 \ Parity Error
+ c0 $4 bitmask: UCSR0A.UPE0 \ Parity Error
+ $2 constant UCSR0A_U2X0 \ Double the USART transmission
+ c0 $2 bitmask: UCSR0A.U2X0 \ Double the USART transmission
+ $1 constant UCSR0A_MPCM0 \ Multi-processor Communication
+ c0 $1 bitmask: UCSR0A.MPCM0 \ Multi-processor Communication
+$c1 constant UCSR0B \ USART Control and Status Regis
+ $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
+ c1 $80 bitmask: UCSR0B.RXCIE0 \ RX Complete Interrupt Enable
+ $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
+ c1 $40 bitmask: UCSR0B.TXCIE0 \ TX Complete Interrupt Enable
+ $20 constant UCSR0B_UDRIE0 \ USART Data register Empty Inte
+ c1 $20 bitmask: UCSR0B.UDRIE0 \ USART Data register Empty Inte
+ $10 constant UCSR0B_RXEN0 \ Receiver Enable
+ c1 $10 bitmask: UCSR0B.RXEN0 \ Receiver Enable
+ $8 constant UCSR0B_TXEN0 \ Transmitter Enable
+ c1 $8 bitmask: UCSR0B.TXEN0 \ Transmitter Enable
+ $4 constant UCSR0B_UCSZ02 \ Character Size
+ c1 $4 bitmask: UCSR0B.UCSZ02 \ Character Size
+ $2 constant UCSR0B_RXB80 \ Receive Data Bit 8
+ c1 $2 bitmask: UCSR0B.RXB80 \ Receive Data Bit 8
+ $1 constant UCSR0B_TXB80 \ Transmit Data Bit 8
+ c1 $1 bitmask: UCSR0B.TXB80 \ Transmit Data Bit 8
+$c2 constant UCSR0C \ USART Control and Status Regis
+ $c0 constant UCSR0C_UMSEL0 \ USART Mode Select
+ c2 $c0 bitmask: UCSR0C.UMSEL0 \ USART Mode Select
+ $30 constant UCSR0C_UPM0 \ Parity Mode Bits
+ c2 $30 bitmask: UCSR0C.UPM0 \ Parity Mode Bits
+ $8 constant UCSR0C_USBS0 \ Stop Bit Select
+ c2 $8 bitmask: UCSR0C.USBS0 \ Stop Bit Select
+ $6 constant UCSR0C_UCSZ0 \ Character Size
+ c2 $6 bitmask: UCSR0C.UCSZ0 \ Character Size
+ $1 constant UCSR0C_UCPOL0 \ Clock Polarity
+ c2 $1 bitmask: UCSR0C.UCPOL0 \ Clock Polarity
+$c4 constant UBRR0 \ USART Baud Rate Register Byte
diff --git a/amforth-6.5/avr8/devices/atmega164a/blocks/USART1.frt b/amforth-6.5/avr8/devices/atmega164a/blocks/USART1.frt
new file mode 100644
index 0000000..6bb4ff9
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega164a/blocks/USART1.frt
@@ -0,0 +1,51 @@
+\ Generated automatically for atmega164a
+\ #require bitnames.frt
+
+\ USART1
+$ce constant UDR1 \ USART I/O Data Register
+$c8 constant UCSR1A \ USART Control and Status Regis
+ $80 constant UCSR1A_RXC1 \ USART Receive Complete
+ c8 $80 bitmask: UCSR1A.RXC1 \ USART Receive Complete
+ $40 constant UCSR1A_TXC1 \ USART Transmitt Complete
+ c8 $40 bitmask: UCSR1A.TXC1 \ USART Transmitt Complete
+ $20 constant UCSR1A_UDRE1 \ USART Data Register Empty
+ c8 $20 bitmask: UCSR1A.UDRE1 \ USART Data Register Empty
+ $10 constant UCSR1A_FE1 \ Framing Error
+ c8 $10 bitmask: UCSR1A.FE1 \ Framing Error
+ $8 constant UCSR1A_DOR1 \ Data overRun
+ c8 $8 bitmask: UCSR1A.DOR1 \ Data overRun
+ $4 constant UCSR1A_UPE1 \ Parity Error
+ c8 $4 bitmask: UCSR1A.UPE1 \ Parity Error
+ $2 constant UCSR1A_U2X1 \ Double the USART transmission
+ c8 $2 bitmask: UCSR1A.U2X1 \ Double the USART transmission
+ $1 constant UCSR1A_MPCM1 \ Multi-processor Communication
+ c8 $1 bitmask: UCSR1A.MPCM1 \ Multi-processor Communication
+$c9 constant UCSR1B \ USART Control and Status Regis
+ $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable
+ c9 $80 bitmask: UCSR1B.RXCIE1 \ RX Complete Interrupt Enable
+ $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable
+ c9 $40 bitmask: UCSR1B.TXCIE1 \ TX Complete Interrupt Enable
+ $20 constant UCSR1B_UDRIE1 \ USART Data register Empty Inte
+ c9 $20 bitmask: UCSR1B.UDRIE1 \ USART Data register Empty Inte
+ $10 constant UCSR1B_RXEN1 \ Receiver Enable
+ c9 $10 bitmask: UCSR1B.RXEN1 \ Receiver Enable
+ $8 constant UCSR1B_TXEN1 \ Transmitter Enable
+ c9 $8 bitmask: UCSR1B.TXEN1 \ Transmitter Enable
+ $4 constant UCSR1B_UCSZ12 \ Character Size
+ c9 $4 bitmask: UCSR1B.UCSZ12 \ Character Size
+ $2 constant UCSR1B_RXB81 \ Receive Data Bit 8
+ c9 $2 bitmask: UCSR1B.RXB81 \ Receive Data Bit 8
+ $1 constant UCSR1B_TXB81 \ Transmit Data Bit 8
+ c9 $1 bitmask: UCSR1B.TXB81 \ Transmit Data Bit 8
+$ca constant UCSR1C \ USART Control and Status Regis
+ $c0 constant UCSR1C_UMSEL1 \ USART Mode Select
+ ca $c0 bitmask: UCSR1C.UMSEL1 \ USART Mode Select
+ $30 constant UCSR1C_UPM1 \ Parity Mode Bits
+ ca $30 bitmask: UCSR1C.UPM1 \ Parity Mode Bits
+ $8 constant UCSR1C_USBS1 \ Stop Bit Select
+ ca $8 bitmask: UCSR1C.USBS1 \ Stop Bit Select
+ $6 constant UCSR1C_UCSZ1 \ Character Size
+ ca $6 bitmask: UCSR1C.UCSZ1 \ Character Size
+ $1 constant UCSR1C_UCPOL1 \ Clock Polarity
+ ca $1 bitmask: UCSR1C.UCPOL1 \ Clock Polarity
+$cc constant UBRR1 \ USART Baud Rate Register Byte
diff --git a/amforth-6.5/avr8/devices/atmega164a/blocks/WATCHDOG.frt b/amforth-6.5/avr8/devices/atmega164a/blocks/WATCHDOG.frt
new file mode 100644
index 0000000..3dc985f
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega164a/blocks/WATCHDOG.frt
@@ -0,0 +1,15 @@
+\ Generated automatically for atmega164a
+\ #require bitnames.frt
+
+\ WATCHDOG
+$60 constant WDTCSR \ Watchdog Timer Control Registe
+ $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Fla
+ 60 $80 bitmask: WDTCSR.WDIF \ Watchdog Timeout Interrupt Fla
+ $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Ena
+ 60 $40 bitmask: WDTCSR.WDIE \ Watchdog Timeout Interrupt Ena
+ $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
+ 60 $27 bitmask: WDTCSR.WDP \ Watchdog Timer Prescaler Bits
+ $10 constant WDTCSR_WDCE \ Watchdog Change Enable
+ 60 $10 bitmask: WDTCSR.WDCE \ Watchdog Change Enable
+ $8 constant WDTCSR_WDE \ Watch Dog Enable
+ 60 $8 bitmask: WDTCSR.WDE \ Watch Dog Enable
diff --git a/amforth-6.5/avr8/devices/atmega164a/device.asm b/amforth-6.5/avr8/devices/atmega164a/device.asm
new file mode 100644
index 0000000..dc12da8
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega164a/device.asm
@@ -0,0 +1,120 @@
+; Partname: ATmega164A
+; generated automatically, do not edit
+
+.nolist
+ .include "m164Adef.inc"
+.list
+
+.equ ramstart = 256
+.equ CELLSIZE = 2
+.macro readflashcell
+ lsl zl
+ rol zh
+ lpm @0, Z+
+ lpm @1, Z+
+.endmacro
+.macro writeflashcell
+ lsl zl
+ rol zh
+.endmacro
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_USART0 = 0
+.set WANT_PORTA = 0
+.set WANT_PORTB = 0
+.set WANT_PORTC = 0
+.set WANT_PORTD = 0
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_TIMER_COUNTER_2 = 0
+.set WANT_WATCHDOG = 0
+.set WANT_JTAG = 0
+.set WANT_BOOT_LOAD = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_AD_CONVERTER = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_EEPROM = 0
+.set WANT_SPI = 0
+.set WANT_TWI = 0
+.set WANT_USART1 = 0
+.set WANT_CPU = 0
+.equ intvecsize = 2 ; please verify; flash size: 16384 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.org 2
+ rcall isr ; External Interrupt Request 0
+.org 4
+ rcall isr ; External Interrupt Request 1
+.org 6
+ rcall isr ; External Interrupt Request 2
+.org 8
+ rcall isr ; Pin Change Interrupt Request 0
+.org 10
+ rcall isr ; Pin Change Interrupt Request 1
+.org 12
+ rcall isr ; Pin Change Interrupt Request 2
+.org 14
+ rcall isr ; Pin Change Interrupt Request 3
+.org 16
+ rcall isr ; Watchdog Time-out Interrupt
+.org 18
+ rcall isr ; Timer/Counter2 Compare Match A
+.org 20
+ rcall isr ; Timer/Counter2 Compare Match B
+.org 22
+ rcall isr ; Timer/Counter2 Overflow
+.org 24
+ rcall isr ; Timer/Counter1 Capture Event
+.org 26
+ rcall isr ; Timer/Counter1 Compare Match A
+.org 28
+ rcall isr ; Timer/Counter1 Compare Match B
+.org 30
+ rcall isr ; Timer/Counter1 Overflow
+.org 32
+ rcall isr ; Timer/Counter0 Compare Match A
+.org 34
+ rcall isr ; Timer/Counter0 Compare Match B
+.org 36
+ rcall isr ; Timer/Counter0 Overflow
+.org 38
+ rcall isr ; SPI Serial Transfer Complete
+.org 40
+ rcall isr ; USART0, Rx Complete
+.org 42
+ rcall isr ; USART0 Data register Empty
+.org 44
+ rcall isr ; USART0, Tx Complete
+.org 46
+ rcall isr ; Analog Comparator
+.org 48
+ rcall isr ; ADC Conversion Complete
+.org 50
+ rcall isr ; EEPROM Ready
+.org 52
+ rcall isr ; 2-wire Serial Interface
+.org 54
+ rcall isr ; Store Program Memory Read
+.org 56
+ rcall isr ; USART1 RX complete
+.org 58
+ rcall isr ; USART1 Data Register Empty
+.org 60
+ rcall isr ; USART1 TX complete
+.equ INTVECTORS = 31
+.nooverlap
+
+; compatability layer (maybe empty)
+
+; controller data area, environment query mcu-info
+mcu_info:
+mcu_ramsize:
+ .dw 1024
+mcu_eepromsize:
+ .dw 512
+mcu_maxdp:
+ .dw 14336
+mcu_numints:
+ .dw 31
+mcu_name:
+ .dw 10
+ .db "ATmega164A"
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega164a/device.inc b/amforth-6.5/avr8/devices/atmega164a/device.inc
new file mode 100644
index 0000000..79c054f
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega164a/device.inc
@@ -0,0 +1,1128 @@
+; Partname: ATmega164A
+; generated automatically, no not edit
+
+.if WANT_ANALOG_COMPARATOR == 1
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Control and Status Register B
+VE_ADCSRB:
+ .dw $ff06
+ .db "ADCSRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRB
+XT_ADCSRB:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRB:
+ .dw 123
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Control And Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw 80
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 1
+VE_DIDR1:
+ .dw $ff05
+ .db "DIDR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR1
+XT_DIDR1:
+ .dw PFA_DOVARIABLE
+PFA_DIDR1:
+ .dw 127
+
+.endif
+.if WANT_USART0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR0:
+ .dw $ff04
+ .db "UDR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR0
+XT_UDR0:
+ .dw PFA_DOVARIABLE
+PFA_UDR0:
+ .dw 198
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR0A:
+ .dw $ff06
+ .db "UCSR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0A
+XT_UCSR0A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0A:
+ .dw 192
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR0B:
+ .dw $ff06
+ .db "UCSR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0B
+XT_UCSR0B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0B:
+ .dw 193
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR0C:
+ .dw $ff06
+ .db "UCSR0C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0C
+XT_UCSR0C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0C:
+ .dw 194
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Bytes
+VE_UBRR0:
+ .dw $ff05
+ .db "UBRR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR0
+XT_UBRR0:
+ .dw PFA_DOVARIABLE
+PFA_UBRR0:
+ .dw 196
+
+.endif
+.if WANT_PORTA == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Register
+VE_PORTA:
+ .dw $ff05
+ .db "PORTA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTA
+XT_PORTA:
+ .dw PFA_DOVARIABLE
+PFA_PORTA:
+ .dw 34
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Direction Register
+VE_DDRA:
+ .dw $ff04
+ .db "DDRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRA
+XT_DDRA:
+ .dw PFA_DOVARIABLE
+PFA_DDRA:
+ .dw 33
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Input Pins
+VE_PINA:
+ .dw $ff04
+ .db "PINA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINA
+XT_PINA:
+ .dw PFA_DOVARIABLE
+PFA_PINA:
+ .dw 32
+
+.endif
+.if WANT_PORTB == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw 37
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw 36
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw 35
+
+.endif
+.if WANT_PORTC == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Register
+VE_PORTC:
+ .dw $ff05
+ .db "PORTC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTC
+XT_PORTC:
+ .dw PFA_DOVARIABLE
+PFA_PORTC:
+ .dw 40
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Direction Register
+VE_DDRC:
+ .dw $ff04
+ .db "DDRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRC
+XT_DDRC:
+ .dw PFA_DOVARIABLE
+PFA_DDRC:
+ .dw 39
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Input Pins
+VE_PINC:
+ .dw $ff04
+ .db "PINC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINC
+XT_PINC:
+ .dw PFA_DOVARIABLE
+PFA_PINC:
+ .dw 38
+
+.endif
+.if WANT_PORTD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw 43
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw 42
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw 41
+
+.endif
+.if WANT_TIMER_COUNTER_0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0B:
+ .dw $ff05
+ .db "OCR0B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0B
+XT_OCR0B:
+ .dw PFA_DOVARIABLE
+PFA_OCR0B:
+ .dw 72
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0A:
+ .dw $ff05
+ .db "OCR0A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0A
+XT_OCR0A:
+ .dw PFA_DOVARIABLE
+PFA_OCR0A:
+ .dw 71
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw 70
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register B
+VE_TCCR0B:
+ .dw $ff06
+ .db "TCCR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0B
+XT_TCCR0B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0B:
+ .dw 69
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register A
+VE_TCCR0A:
+ .dw $ff06
+ .db "TCCR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0A
+XT_TCCR0A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0A:
+ .dw 68
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Mask Register
+VE_TIMSK0:
+ .dw $ff06
+ .db "TIMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK0
+XT_TIMSK0:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK0:
+ .dw 110
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Flag register
+VE_TIFR0:
+ .dw $ff05
+ .db "TIFR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR0
+XT_TIFR0:
+ .dw PFA_DOVARIABLE
+PFA_TIFR0:
+ .dw 53
+; ( -- addr ) System Constant
+; R( -- )
+; General Timer/Counter Control Register
+VE_GTCCR:
+ .dw $ff05
+ .db "GTCCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GTCCR
+XT_GTCCR:
+ .dw PFA_DOVARIABLE
+PFA_GTCCR:
+ .dw 67
+
+.endif
+.if WANT_TIMER_COUNTER_2 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Mask register
+VE_TIMSK2:
+ .dw $ff06
+ .db "TIMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK2
+XT_TIMSK2:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK2:
+ .dw 112
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Flag Register
+VE_TIFR2:
+ .dw $ff05
+ .db "TIFR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR2
+XT_TIFR2:
+ .dw PFA_DOVARIABLE
+PFA_TIFR2:
+ .dw 55
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register A
+VE_TCCR2A:
+ .dw $ff06
+ .db "TCCR2A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2A
+XT_TCCR2A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2A:
+ .dw 176
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register B
+VE_TCCR2B:
+ .dw $ff06
+ .db "TCCR2B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2B
+XT_TCCR2B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2B:
+ .dw 177
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2
+VE_TCNT2:
+ .dw $ff05
+ .db "TCNT2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT2
+XT_TCNT2:
+ .dw PFA_DOVARIABLE
+PFA_TCNT2:
+ .dw 178
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register B
+VE_OCR2B:
+ .dw $ff05
+ .db "OCR2B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2B
+XT_OCR2B:
+ .dw PFA_DOVARIABLE
+PFA_OCR2B:
+ .dw 180
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register A
+VE_OCR2A:
+ .dw $ff05
+ .db "OCR2A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2A
+XT_OCR2A:
+ .dw PFA_DOVARIABLE
+PFA_OCR2A:
+ .dw 179
+; ( -- addr ) System Constant
+; R( -- )
+; Asynchronous Status Register
+VE_ASSR:
+ .dw $ff04
+ .db "ASSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ASSR
+XT_ASSR:
+ .dw PFA_DOVARIABLE
+PFA_ASSR:
+ .dw 182
+
+.endif
+.if WANT_WATCHDOG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCSR:
+ .dw $ff06
+ .db "WDTCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCSR
+XT_WDTCSR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCSR:
+ .dw 96
+
+.endif
+.if WANT_JTAG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; On-Chip Debug Related Register in I/O Memory
+VE_OCDR:
+ .dw $ff04
+ .db "OCDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCDR
+XT_OCDR:
+ .dw PFA_DOVARIABLE
+PFA_OCDR:
+ .dw 81
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw 85
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Status Register
+VE_MCUSR:
+ .dw $ff05
+ .db "MCUSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUSR
+XT_MCUSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUSR:
+ .dw 84
+
+.endif
+.if WANT_BOOT_LOAD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control Register
+VE_SPMCSR:
+ .dw $ff06
+ .db "SPMCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCSR
+XT_SPMCSR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCSR:
+ .dw 87
+
+.endif
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register A
+VE_EICRA:
+ .dw $ff05
+ .db "EICRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRA
+XT_EICRA:
+ .dw PFA_DOVARIABLE
+PFA_EICRA:
+ .dw 105
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Mask Register
+VE_EIMSK:
+ .dw $ff05
+ .db "EIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIMSK
+XT_EIMSK:
+ .dw PFA_DOVARIABLE
+PFA_EIMSK:
+ .dw 61
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Flag Register
+VE_EIFR:
+ .dw $ff04
+ .db "EIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIFR
+XT_EIFR:
+ .dw PFA_DOVARIABLE
+PFA_EIFR:
+ .dw 60
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 3
+VE_PCMSK3:
+ .dw $ff06
+ .db "PCMSK3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK3
+XT_PCMSK3:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK3:
+ .dw 115
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 2
+VE_PCMSK2:
+ .dw $ff06
+ .db "PCMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK2
+XT_PCMSK2:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK2:
+ .dw 109
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 1
+VE_PCMSK1:
+ .dw $ff06
+ .db "PCMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK1
+XT_PCMSK1:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK1:
+ .dw 108
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 0
+VE_PCMSK0:
+ .dw $ff06
+ .db "PCMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK0
+XT_PCMSK0:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK0:
+ .dw 107
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Interrupt Flag Register
+VE_PCIFR:
+ .dw $ff05
+ .db "PCIFR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCIFR
+XT_PCIFR:
+ .dw PFA_DOVARIABLE
+PFA_PCIFR:
+ .dw 59
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Interrupt Control Register
+VE_PCICR:
+ .dw $ff05
+ .db "PCICR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCICR
+XT_PCICR:
+ .dw PFA_DOVARIABLE
+PFA_PCICR:
+ .dw 104
+
+.endif
+.if WANT_AD_CONVERTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC multiplexer Selection Register
+VE_ADMUX:
+ .dw $ff05
+ .db "ADMUX",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADMUX
+XT_ADMUX:
+ .dw PFA_DOVARIABLE
+PFA_ADMUX:
+ .dw 124
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register Bytes
+VE_ADC:
+ .dw $ff03
+ .db "ADC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADC
+XT_ADC:
+ .dw PFA_DOVARIABLE
+PFA_ADC:
+ .dw 120
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register A
+VE_ADCSRA:
+ .dw $ff06
+ .db "ADCSRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRA
+XT_ADCSRA:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRA:
+ .dw 122
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register
+VE_DIDR0:
+ .dw $ff05
+ .db "DIDR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR0
+XT_DIDR0:
+ .dw PFA_DOVARIABLE
+PFA_DIDR0:
+ .dw 126
+
+.endif
+.if WANT_TIMER_COUNTER_1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Mask Register
+VE_TIMSK1:
+ .dw $ff06
+ .db "TIMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK1
+XT_TIMSK1:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK1:
+ .dw 111
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Flag register
+VE_TIFR1:
+ .dw $ff05
+ .db "TIFR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR1
+XT_TIFR1:
+ .dw PFA_DOVARIABLE
+PFA_TIFR1:
+ .dw 54
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw 128
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw 129
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register C
+VE_TCCR1C:
+ .dw $ff06
+ .db "TCCR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1C
+XT_TCCR1C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1C:
+ .dw 130
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Bytes
+VE_TCNT1:
+ .dw $ff05
+ .db "TCNT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1
+XT_TCNT1:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1:
+ .dw 132
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register A Bytes
+VE_OCR1A:
+ .dw $ff05
+ .db "OCR1A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1A
+XT_OCR1A:
+ .dw PFA_DOVARIABLE
+PFA_OCR1A:
+ .dw 136
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register B Bytes
+VE_OCR1B:
+ .dw $ff05
+ .db "OCR1B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1B
+XT_OCR1B:
+ .dw PFA_DOVARIABLE
+PFA_OCR1B:
+ .dw 138
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Bytes
+VE_ICR1:
+ .dw $ff04
+ .db "ICR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1
+XT_ICR1:
+ .dw PFA_DOVARIABLE
+PFA_ICR1:
+ .dw 134
+
+.endif
+.if WANT_EEPROM == 1
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Address Register Low Bytes
+VE_EEAR:
+ .dw $ff04
+ .db "EEAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEAR
+XT_EEAR:
+ .dw PFA_DOVARIABLE
+PFA_EEAR:
+ .dw 65
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw 64
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw 63
+
+.endif
+.if WANT_SPI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR0:
+ .dw $ff05
+ .db "SPDR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR0
+XT_SPDR0:
+ .dw PFA_DOVARIABLE
+PFA_SPDR0:
+ .dw 78
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR0:
+ .dw $ff05
+ .db "SPSR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR0
+XT_SPSR0:
+ .dw PFA_DOVARIABLE
+PFA_SPSR0:
+ .dw 77
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR0:
+ .dw $ff05
+ .db "SPCR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR0
+XT_SPCR0:
+ .dw PFA_DOVARIABLE
+PFA_SPCR0:
+ .dw 76
+
+.endif
+.if WANT_TWI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; TWI (Slave) Address Mask Register
+VE_TWAMR:
+ .dw $ff05
+ .db "TWAMR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWAMR
+XT_TWAMR:
+ .dw PFA_DOVARIABLE
+PFA_TWAMR:
+ .dw 189
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Bit Rate register
+VE_TWBR:
+ .dw $ff04
+ .db "TWBR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWBR
+XT_TWBR:
+ .dw PFA_DOVARIABLE
+PFA_TWBR:
+ .dw 184
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Control Register
+VE_TWCR:
+ .dw $ff04
+ .db "TWCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWCR
+XT_TWCR:
+ .dw PFA_DOVARIABLE
+PFA_TWCR:
+ .dw 188
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Status Register
+VE_TWSR:
+ .dw $ff04
+ .db "TWSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWSR
+XT_TWSR:
+ .dw PFA_DOVARIABLE
+PFA_TWSR:
+ .dw 185
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Data register
+VE_TWDR:
+ .dw $ff04
+ .db "TWDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWDR
+XT_TWDR:
+ .dw PFA_DOVARIABLE
+PFA_TWDR:
+ .dw 187
+; ( -- addr ) System Constant
+; R( -- )
+; TWI (Slave) Address register
+VE_TWAR:
+ .dw $ff04
+ .db "TWAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWAR
+XT_TWAR:
+ .dw PFA_DOVARIABLE
+PFA_TWAR:
+ .dw 186
+
+.endif
+.if WANT_USART1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR1:
+ .dw $ff04
+ .db "UDR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR1
+XT_UDR1:
+ .dw PFA_DOVARIABLE
+PFA_UDR1:
+ .dw 206
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR1A:
+ .dw $ff06
+ .db "UCSR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1A
+XT_UCSR1A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1A:
+ .dw 200
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR1B:
+ .dw $ff06
+ .db "UCSR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1B
+XT_UCSR1B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1B:
+ .dw 201
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR1C:
+ .dw $ff06
+ .db "UCSR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1C
+XT_UCSR1C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1C:
+ .dw 202
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Bytes
+VE_UBRR1:
+ .dw $ff05
+ .db "UBRR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR1
+XT_UBRR1:
+ .dw PFA_DOVARIABLE
+PFA_UBRR1:
+ .dw 204
+
+.endif
+.if WANT_CPU == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw 95
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer
+VE_SP:
+ .dw $ff02
+ .db "SP"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SP
+XT_SP:
+ .dw PFA_DOVARIABLE
+PFA_SP:
+ .dw 93
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Calibration Value
+VE_OSCCAL:
+ .dw $ff06
+ .db "OSCCAL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSCCAL
+XT_OSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_OSCCAL:
+ .dw 102
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_CLKPR:
+ .dw $ff05
+ .db "CLKPR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKPR
+XT_CLKPR:
+ .dw PFA_DOVARIABLE
+PFA_CLKPR:
+ .dw 97
+; ( -- addr ) System Constant
+; R( -- )
+; Sleep Mode Control Register
+VE_SMCR:
+ .dw $ff04
+ .db "SMCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SMCR
+XT_SMCR:
+ .dw PFA_DOVARIABLE
+PFA_SMCR:
+ .dw 83
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 2
+VE_GPIOR2:
+ .dw $ff06
+ .db "GPIOR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR2
+XT_GPIOR2:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR2:
+ .dw 75
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 1
+VE_GPIOR1:
+ .dw $ff06
+ .db "GPIOR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR1
+XT_GPIOR1:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR1:
+ .dw 74
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 0
+VE_GPIOR0:
+ .dw $ff06
+ .db "GPIOR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR0
+XT_GPIOR0:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR0:
+ .dw 62
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register0
+VE_PRR0:
+ .dw $ff04
+ .db "PRR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR0
+XT_PRR0:
+ .dw PFA_DOVARIABLE
+PFA_PRR0:
+ .dw 100
+
+.endif
diff --git a/amforth-6.5/avr8/devices/atmega164a/device.py b/amforth-6.5/avr8/devices/atmega164a/device.py
new file mode 100644
index 0000000..ea2ebc4
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega164a/device.py
@@ -0,0 +1,387 @@
+# Generated Automatically
+
+# Partname ATmega164A
+
+MCUREGS = {
+# Interrupt Vectors
+ 'INT0Addr' : '#2', # External Interrupt Request 0
+ 'INT1Addr' : '#4', # External Interrupt Request 1
+ 'INT2Addr' : '#6', # External Interrupt Request 2
+ 'PCINT0Addr' : '#8', # Pin Change Interrupt Request 0
+ 'PCINT1Addr' : '#10', # Pin Change Interrupt Request 1
+ 'PCINT2Addr' : '#12', # Pin Change Interrupt Request 2
+ 'PCINT3Addr' : '#14', # Pin Change Interrupt Request 3
+ 'WDTAddr' : '#16', # Watchdog Time-out Interrupt
+ 'TIMER2_COMPAAddr' : '#18', # Timer/Counter2 Compare Match A
+ 'TIMER2_COMPBAddr' : '#20', # Timer/Counter2 Compare Match B
+ 'TIMER2_OVFAddr' : '#22', # Timer/Counter2 Overflow
+ 'TIMER1_CAPTAddr' : '#24', # Timer/Counter1 Capture Event
+ 'TIMER1_COMPAAddr' : '#26', # Timer/Counter1 Compare Match A
+ 'TIMER1_COMPBAddr' : '#28', # Timer/Counter1 Compare Match B
+ 'TIMER1_OVFAddr' : '#30', # Timer/Counter1 Overflow
+ 'TIMER0_COMPAAddr' : '#32', # Timer/Counter0 Compare Match A
+ 'TIMER0_COMPBAddr' : '#34', # Timer/Counter0 Compare Match B
+ 'TIMER0_OVFAddr' : '#36', # Timer/Counter0 Overflow
+ 'SPI_STCAddr' : '#38', # SPI Serial Transfer Complete
+ 'USART0_RXAddr' : '#40', # USART0, Rx Complete
+ 'USART0_UDREAddr' : '#42', # USART0 Data register Empty
+ 'USART0_TXAddr' : '#44', # USART0, Tx Complete
+ 'ANALOG_COMPAddr' : '#46', # Analog Comparator
+ 'ADCAddr' : '#48', # ADC Conversion Complete
+ 'EE_READYAddr' : '#50', # EEPROM Ready
+ 'TWIAddr' : '#52', # 2-wire Serial Interface
+ 'SPM_READYAddr' : '#54', # Store Program Memory Read
+ 'USART1_RXAddr' : '#56', # USART1 RX complete
+ 'USART1_UDREAddr' : '#58', # USART1 Data Register Empty
+ 'USART1_TXAddr' : '#60', # USART1 TX complete
+
+# Module ANALOG_COMPARATOR
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
+ 'ACSR' : '$50', # Analog Comparator Control And
+ 'ACSR_ACD': '$80', # Analog Comparator Disable
+ 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
+ 'ACSR_ACO': '$20', # Analog Compare Output
+ 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
+ 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
+ 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
+ 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
+ 'DIDR1' : '$7f', # Digital Input Disable Register
+ 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
+ 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
+
+# Module USART0
+ 'UDR0' : '$c6', # USART I/O Data Register
+ 'UCSR0A' : '$c0', # USART Control and Status Regis
+ 'UCSR0A_RXC0': '$80', # USART Receive Complete
+ 'UCSR0A_TXC0': '$40', # USART Transmitt Complete
+ 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
+ 'UCSR0A_FE0': '$10', # Framing Error
+ 'UCSR0A_DOR0': '$8', # Data overRun
+ 'UCSR0A_UPE0': '$4', # Parity Error
+ 'UCSR0A_U2X0': '$2', # Double the USART transmission
+ 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
+ 'UCSR0B' : '$c1', # USART Control and Status Regis
+ 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
+ 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
+ 'UCSR0B_UDRIE0': '$20', # USART Data register Empty Inte
+ 'UCSR0B_RXEN0': '$10', # Receiver Enable
+ 'UCSR0B_TXEN0': '$8', # Transmitter Enable
+ 'UCSR0B_UCSZ02': '$4', # Character Size
+ 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
+ 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
+ 'UCSR0C' : '$c2', # USART Control and Status Regis
+ 'UCSR0C_UMSEL0': '$c0', # USART Mode Select
+ 'UCSR0C_UPM0': '$30', # Parity Mode Bits
+ 'UCSR0C_USBS0': '$8', # Stop Bit Select
+ 'UCSR0C_UCSZ0': '$6', # Character Size
+ 'UCSR0C_UCPOL0': '$1', # Clock Polarity
+ 'UBRR0' : '$c4', # USART Baud Rate Register Byte
+
+# Module PORTA
+ 'PORTA' : '$22', # Port A Data Register
+ 'DDRA' : '$21', # Port A Data Direction Register
+ 'PINA' : '$20', # Port A Input Pins
+
+# Module PORTB
+ 'PORTB' : '$25', # Port B Data Register
+ 'DDRB' : '$24', # Port B Data Direction Register
+ 'PINB' : '$23', # Port B Input Pins
+
+# Module PORTC
+ 'PORTC' : '$28', # Port C Data Register
+ 'DDRC' : '$27', # Port C Data Direction Register
+ 'PINC' : '$26', # Port C Input Pins
+
+# Module PORTD
+ 'PORTD' : '$2b', # Port D Data Register
+ 'DDRD' : '$2a', # Port D Data Direction Register
+ 'PIND' : '$29', # Port D Input Pins
+
+# Module TIMER_COUNTER_0
+ 'OCR0B' : '$48', # Timer/Counter0 Output Compare
+ 'OCR0A' : '$47', # Timer/Counter0 Output Compare
+ 'TCNT0' : '$46', # Timer/Counter0
+ 'TCCR0B' : '$45', # Timer/Counter Control Register
+ 'TCCR0B_FOC0A': '$80', # Force Output Compare A
+ 'TCCR0B_FOC0B': '$40', # Force Output Compare B
+ 'TCCR0B_WGM02': '$8', #
+ 'TCCR0B_CS0': '$7', # Clock Select
+ 'TCCR0A' : '$44', # Timer/Counter Control Registe
+ 'TCCR0A_COM0A': '$c0', # Compare Output Mode, Phase Cor
+ 'TCCR0A_COM0B': '$30', # Compare Output Mode, Fast PWm
+ 'TCCR0A_WGM0': '$3', # Waveform Generation Mode
+ 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
+ 'TIMSK0_OCIE0B': '$4', # Timer/Counter0 Output Compare
+ 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
+ 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
+ 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
+ 'TIFR0_OCF0B': '$4', # Timer/Counter0 Output Compare
+ 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
+ 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSRSYNC': '$1', # Prescaler Reset Timer/Counter1
+
+# Module TIMER_COUNTER_2
+ 'TIMSK2' : '$70', # Timer/Counter Interrupt Mask r
+ 'TIMSK2_OCIE2B': '$4', # Timer/Counter2 Output Compare
+ 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
+ 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
+ 'TIFR2' : '$37', # Timer/Counter Interrupt Flag R
+ 'TIFR2_OCF2B': '$4', # Output Compare Flag 2B
+ 'TIFR2_OCF2A': '$2', # Output Compare Flag 2A
+ 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
+ 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
+ 'TCCR2A_COM2A': '$c0', # Compare Output Mode bits
+ 'TCCR2A_COM2B': '$30', # Compare Output Mode bits
+ 'TCCR2A_WGM2': '$3', # Waveform Genration Mode
+ 'TCCR2B' : '$b1', # Timer/Counter2 Control Registe
+ 'TCCR2B_FOC2A': '$80', # Force Output Compare A
+ 'TCCR2B_FOC2B': '$40', # Force Output Compare B
+ 'TCCR2B_WGM22': '$8', # Waveform Generation Mode
+ 'TCCR2B_CS2': '$7', # Clock Select bits
+ 'TCNT2' : '$b2', # Timer/Counter2
+ 'OCR2B' : '$b4', # Timer/Counter2 Output Compare
+ 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
+ 'ASSR' : '$b6', # Asynchronous Status Register
+ 'ASSR_EXCLK': '$40', # Enable External Clock Input
+ 'ASSR_AS2': '$20', # Asynchronous Timer/Counter2
+ 'ASSR_TCN2UB': '$10', # Timer/Counter2 Update Busy
+ 'ASSR_OCR2AUB': '$8', # Output Compare Register2 Updat
+ 'ASSR_OCR2BUB': '$4', # Output Compare Register 2 Upda
+ 'ASSR_TCR2AUB': '$2', # Timer/Counter Control Register
+ 'ASSR_TCR2BUB': '$1', # Timer/Counter Control Register
+ 'GTCCR' : '$43', # General Timer Counter Control
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSRASY': '$2', # Prescaler Reset Timer/Counter2
+
+# Module WATCHDOG
+ 'WDTCSR' : '$60', # Watchdog Timer Control Registe
+ 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
+ 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
+ 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
+ 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
+ 'WDTCSR_WDE': '$8', # Watch Dog Enable
+
+# Module JTAG
+ 'OCDR' : '$51', # On-Chip Debug Related Register
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_JTD': '$80', # JTAG Interface Disable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+
+# Module BOOT_LOAD
+ 'SPMCSR' : '$57', # Store Program Memory Control R
+ 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
+ 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
+ 'SPMCSR_SIGRD': '$20', # Signature Row Read
+ 'SPMCSR_RWWSRE': '$10', # Read While Write section read
+ 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
+ 'SPMCSR_PGWRT': '$4', # Page Write
+ 'SPMCSR_PGERS': '$2', # Page Erase
+ 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
+
+# Module EXTERNAL_INTERRUPT
+ 'EICRA' : '$69', # External Interrupt Control Reg
+ 'EICRA_ISC2': '$30', # External Interrupt Sense Contr
+ 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
+ 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
+ 'EIMSK' : '$3d', # External Interrupt Mask Regist
+ 'EIMSK_INT': '$7', # External Interrupt Request 2 E
+ 'EIFR' : '$3c', # External Interrupt Flag Regist
+ 'EIFR_INTF': '$7', # External Interrupt Flags
+ 'PCMSK3' : '$73', # Pin Change Mask Register 3
+ 'PCMSK3_PCINT': '$ff', # Pin Change Enable Masks
+ 'PCMSK2' : '$6d', # Pin Change Mask Register 2
+ 'PCMSK2_PCINT': '$ff', # Pin Change Enable Masks
+ 'PCMSK1' : '$6c', # Pin Change Mask Register 1
+ 'PCMSK1_PCINT': '$ff', # Pin Change Enable Masks
+ 'PCMSK0' : '$6b', # Pin Change Mask Register 0
+ 'PCMSK0_PCINT': '$ff', # Pin Change Enable Masks
+ 'PCIFR' : '$3b', # Pin Change Interrupt Flag Regi
+ 'PCIFR_PCIF': '$f', # Pin Change Interrupt Flags
+ 'PCICR' : '$68', # Pin Change Interrupt Control R
+ 'PCICR_PCIE': '$f', # Pin Change Interrupt Enables
+
+# Module AD_CONVERTER
+ 'ADMUX' : '$7c', # The ADC multiplexer Selection
+ 'ADMUX_REFS': '$c0', # Reference Selection Bits
+ 'ADMUX_ADLAR': '$20', # Left Adjust Result
+ 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
+ 'ADC' : '$78', # ADC Data Register Bytes
+ 'ADCSRA' : '$7a', # The ADC Control and Status reg
+ 'ADCSRA_ADEN': '$80', # ADC Enable
+ 'ADCSRA_ADSC': '$40', # ADC Start Conversion
+ 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
+ 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
+ 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
+ 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
+ 'ADCSRB' : '$7b', # The ADC Control and Status reg
+ 'ADCSRB_ACME': '$40', #
+ 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Source bits
+ 'DIDR0' : '$7e', # Digital Input Disable Register
+ 'DIDR0_ADC7D': '$80', #
+ 'DIDR0_ADC6D': '$40', #
+ 'DIDR0_ADC5D': '$20', #
+ 'DIDR0_ADC4D': '$10', #
+ 'DIDR0_ADC3D': '$8', #
+ 'DIDR0_ADC2D': '$4', #
+ 'DIDR0_ADC1D': '$2', #
+ 'DIDR0_ADC0D': '$1', #
+
+# Module TIMER_COUNTER_1
+ 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
+ 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
+ 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
+ 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
+ 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
+ 'TIFR1' : '$36', # Timer/Counter Interrupt Flag r
+ 'TIFR1_ICF1': '$20', # Timer/Counter1 Input Capture F
+ 'TIFR1_OCF1B': '$4', # Timer/Counter1 Output Compare
+ 'TIFR1_OCF1A': '$2', # Timer/Counter1 Output Compare
+ 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
+ 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
+ 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
+ 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
+ 'TCCR1A_WGM1': '$3', # Pulse Width Modulator Select B
+ 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
+ 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
+ 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
+ 'TCCR1B_WGM1': '$18', # Waveform Generation Mode Bits
+ 'TCCR1B_CS1': '$7', # Clock Select1 bits
+ 'TCCR1C' : '$82', # Timer/Counter1 Control Registe
+ 'TCCR1C_FOC1A': '$80', # Force Output Compare for Chann
+ 'TCCR1C_FOC1B': '$40', # Force Output Compare for Chann
+ 'TCNT1' : '$84', # Timer/Counter1 Bytes
+ 'OCR1A' : '$88', # Timer/Counter1 Output Compare
+ 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
+ 'ICR1' : '$86', # Timer/Counter1 Input Capture R
+
+# Module EEPROM
+ 'EEAR' : '$41', # EEPROM Address Register Low By
+ 'EEDR' : '$40', # EEPROM Data Register
+ 'EECR' : '$3f', # EEPROM Control Register
+ 'EECR_EEPM': '$30', # EEPROM Programming Mode Bits
+ 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
+ 'EECR_EEMPE': '$4', # EEPROM Master Write Enable
+ 'EECR_EEPE': '$2', # EEPROM Write Enable
+ 'EECR_EERE': '$1', # EEPROM Read Enable
+
+# Module SPI
+ 'SPDR0' : '$4e', # SPI Data Register
+ 'SPSR0' : '$4d', # SPI Status Register
+ 'SPSR0_SPIF0': '$80', # SPI Interrupt Flag
+ 'SPSR0_WCOL0': '$40', # Write Collision Flag
+ 'SPSR0_SPI2X0': '$1', # Double SPI Speed Bit
+ 'SPCR0' : '$4c', # SPI Control Register
+ 'SPCR0_SPIE0': '$80', # SPI Interrupt Enable
+ 'SPCR0_SPE0': '$40', # SPI Enable
+ 'SPCR0_DORD0': '$20', # Data Order
+ 'SPCR0_MSTR0': '$10', # Master/Slave Select
+ 'SPCR0_CPOL0': '$8', # Clock polarity
+ 'SPCR0_CPHA0': '$4', # Clock Phase
+ 'SPCR0_SPR10': '$2', # SPI Clock Rate Select 1
+ 'SPCR0_SPR00': '$1', # SPI Clock Rate Select 0
+
+# Module TWI
+ 'TWAMR' : '$bd', # TWI (Slave) Address Mask Regis
+ 'TWAMR_TWAM': '$fe', #
+ 'TWBR' : '$b8', # TWI Bit Rate register
+ 'TWCR' : '$bc', # TWI Control Register
+ 'TWCR_TWINT': '$80', # TWI Interrupt Flag
+ 'TWCR_TWEA': '$40', # TWI Enable Acknowledge Bit
+ 'TWCR_TWSTA': '$20', # TWI Start Condition Bit
+ 'TWCR_TWSTO': '$10', # TWI Stop Condition Bit
+ 'TWCR_TWWC': '$8', # TWI Write Collition Flag
+ 'TWCR_TWEN': '$4', # TWI Enable Bit
+ 'TWCR_TWIE': '$1', # TWI Interrupt Enable
+ 'TWSR' : '$b9', # TWI Status Register
+ 'TWSR_TWS': '$f8', # TWI Status
+ 'TWSR_TWPS': '$3', # TWI Prescaler
+ 'TWDR' : '$bb', # TWI Data register
+ 'TWAR' : '$ba', # TWI (Slave) Address register
+ 'TWAR_TWA': '$fe', # TWI (Slave) Address register B
+ 'TWAR_TWGCE': '$1', # TWI General Call Recognition E
+
+# Module USART1
+ 'UDR1' : '$ce', # USART I/O Data Register
+ 'UCSR1A' : '$c8', # USART Control and Status Regis
+ 'UCSR1A_RXC1': '$80', # USART Receive Complete
+ 'UCSR1A_TXC1': '$40', # USART Transmitt Complete
+ 'UCSR1A_UDRE1': '$20', # USART Data Register Empty
+ 'UCSR1A_FE1': '$10', # Framing Error
+ 'UCSR1A_DOR1': '$8', # Data overRun
+ 'UCSR1A_UPE1': '$4', # Parity Error
+ 'UCSR1A_U2X1': '$2', # Double the USART transmission
+ 'UCSR1A_MPCM1': '$1', # Multi-processor Communication
+ 'UCSR1B' : '$c9', # USART Control and Status Regis
+ 'UCSR1B_RXCIE1': '$80', # RX Complete Interrupt Enable
+ 'UCSR1B_TXCIE1': '$40', # TX Complete Interrupt Enable
+ 'UCSR1B_UDRIE1': '$20', # USART Data register Empty Inte
+ 'UCSR1B_RXEN1': '$10', # Receiver Enable
+ 'UCSR1B_TXEN1': '$8', # Transmitter Enable
+ 'UCSR1B_UCSZ12': '$4', # Character Size
+ 'UCSR1B_RXB81': '$2', # Receive Data Bit 8
+ 'UCSR1B_TXB81': '$1', # Transmit Data Bit 8
+ 'UCSR1C' : '$ca', # USART Control and Status Regis
+ 'UCSR1C_UMSEL1': '$c0', # USART Mode Select
+ 'UCSR1C_UPM1': '$30', # Parity Mode Bits
+ 'UCSR1C_USBS1': '$8', # Stop Bit Select
+ 'UCSR1C_UCSZ1': '$6', # Character Size
+ 'UCSR1C_UCPOL1': '$1', # Clock Polarity
+ 'UBRR1' : '$cc', # USART Baud Rate Register Byte
+
+# Module CPU
+ 'SREG' : '$5f', # Status Register
+ 'SREG_I': '$80', # Global Interrupt Enable
+ 'SREG_T': '$40', # Bit Copy Storage
+ 'SREG_H': '$20', # Half Carry Flag
+ 'SREG_S': '$10', # Sign Bit
+ 'SREG_V': '$8', # Two's Complement Overflow Flag
+ 'SREG_N': '$4', # Negative Flag
+ 'SREG_Z': '$2', # Zero Flag
+ 'SREG_C': '$1', # Carry Flag
+ 'SP' : '$5d', # Stack Pointer
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_JTD': '$80', # JTAG Interface Disable
+ 'MCUCR_PUD': '$10', # Pull-up disable
+ 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
+ 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+ 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
+ 'MCUSR_BORF': '$4', # Brown-out Reset Flag
+ 'MCUSR_EXTRF': '$2', # External Reset Flag
+ 'MCUSR_PORF': '$1', # Power-on reset flag
+ 'OSCCAL' : '$66', # Oscillator Calibration Value
+ 'CLKPR' : '$61', #
+ 'CLKPR_CLKPCE': '$80', #
+ 'CLKPR_CLKPS': '$f', #
+ 'SMCR' : '$53', # Sleep Mode Control Register
+ 'SMCR_SM': '$e', # Sleep Mode Select bits
+ 'SMCR_SE': '$1', # Sleep Enable
+ 'GPIOR2' : '$4b', # General Purpose IO Register 2
+ 'GPIOR2_GPIOR': '$ff', # General Purpose IO Register 2
+ 'GPIOR1' : '$4a', # General Purpose IO Register 1
+ 'GPIOR1_GPIOR': '$ff', # General Purpose IO Register 1
+ 'GPIOR0' : '$3e', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR07': '$80', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR06': '$40', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR05': '$20', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR04': '$10', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR03': '$8', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR02': '$4', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR01': '$2', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR00': '$1', # General Purpose IO Register 0
+ 'PRR0' : '$64', # Power Reduction Register0
+ 'PRR0_PRTWI': '$80', # Power Reduction TWI
+ 'PRR0_PRTIM2': '$40', # Power Reduction Timer/Counter2
+ 'PRR0_PRTIM0': '$20', # Power Reduction Timer/Counter0
+ 'PRR0_PRUSART': '$12', # Power Reduction USARTs
+ 'PRR0_PRTIM1': '$8', # Power Reduction Timer/Counter1
+ 'PRR0_PRSPI': '$4', # Power Reduction Serial Periphe
+ 'PRR0_PRADC': '$1', # Power Reduction ADC
+
+ '__amforth_dummy':'0'
+}
diff --git a/amforth-6.5/avr8/devices/atmega164a/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega164a/words/no-jtag.asm
new file mode 100644
index 0000000..352a4bb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega164a/words/no-jtag.asm
@@ -0,0 +1,14 @@
+; ( -- )
+; ( -- )
+; MCU
+; disable jtag at runtime
+VE_NOJTAG:
+ .dw $FF05
+ .db "-jtag",0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOJTAG
+XT_NOJTAG:
+ .dw PFA_NOJTAG
+PFA_NOJTAG:
+
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega164a/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega164a/words/no-wdt.asm
new file mode 100644
index 0000000..ff6ddd1
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega164a/words/no-wdt.asm
@@ -0,0 +1,34 @@
+; ( -- )
+; MCU
+; disable watch dog timer at runtime
+VE_NOWDT:
+ .dw $ff04
+ .db "-wdt"
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOWDT
+XT_NOWDT:
+ .dw PFA_NOWDT
+PFA_NOWDT:
+
+ in temp1,SREG
+ push temp1
+ ; Turn always off global interrupt.
+ cli
+ ; Reset Watchdog Timer
+ wdr
+ ; Clear WDRF in MCUSR
+ in temp1, MCUSR
+ andi temp1, (0xff & (0<<WDRF))
+ out MCUSR, temp1
+ ; Write logical one to WDCE and WDE
+ ; Keep old prescaler setting to prevent unintentional time-out
+ in_ temp1, WDTCSR
+ ori temp1, (1<<WDCE) | (1<<WDE)
+ out_ WDTCSR, temp1
+ ; Turn off WDT
+ ldi temp1, (0<<WDE)
+ out_ WDTCSR, temp1
+ ; restore status register
+ pop temp1
+ out SREG,temp1
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega164a/words/sleep.asm b/amforth-6.5/avr8/devices/atmega164a/words/sleep.asm
new file mode 100644
index 0000000..256249c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega164a/words/sleep.asm
@@ -0,0 +1,19 @@
+; ( mode -- )
+; MCU
+; put the controller into the specified sleep mode
+VE_SLEEP:
+ .dw $ff05
+ .db "sleep", 0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_SLEEP
+XT_SLEEP:
+ .dw PFA_SLEEP
+PFA_SLEEP:
+ andi tosl, 7 ; leave only legal mode bits
+ lsl tosl ; move to correct location (bits 3-1)
+ ori tosl, 1 ; set the SE bit
+ out_ SMCR, tosl ; set the sleep config
+ sleep ; nighty-night
+ out_ SMCR, zerol ; 0 protects against accidental sleeps
+ loadtos ; pop argument from stack
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega164p/atmega164p.frt b/amforth-6.5/avr8/devices/atmega164p/atmega164p.frt
new file mode 100644
index 0000000..da5cdf7
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega164p/atmega164p.frt
@@ -0,0 +1,347 @@
+\ Partname: ATmega164P
+\ generated automatically
+
+\ ANALOG_COMPARATOR
+&123 constant ADCSRB \ ADC Control and Status Register B
+ $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer Enable
+&80 constant ACSR \ Analog Comparator Control And Status Register
+ $80 constant ACSR_ACD \ Analog Comparator Disable
+ $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
+ $20 constant ACSR_ACO \ Analog Compare Output
+ $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
+ $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
+ $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
+ $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
+&127 constant DIDR1 \ Digital Input Disable Register 1
+ $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
+ $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
+\ USART0
+&198 constant UDR0 \ USART I/O Data Register
+&192 constant UCSR0A \ USART Control and Status Register A
+ $80 constant UCSR0A_RXC0 \ USART Receive Complete
+ $40 constant UCSR0A_TXC0 \ USART Transmitt Complete
+ $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
+ $10 constant UCSR0A_FE0 \ Framing Error
+ $08 constant UCSR0A_DOR0 \ Data overRun
+ $04 constant UCSR0A_UPE0 \ Parity Error
+ $02 constant UCSR0A_U2X0 \ Double the USART transmission speed
+ $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
+&193 constant UCSR0B \ USART Control and Status Register B
+ $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
+ $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
+ $20 constant UCSR0B_UDRIE0 \ USART Data register Empty Interrupt Enable
+ $10 constant UCSR0B_RXEN0 \ Receiver Enable
+ $08 constant UCSR0B_TXEN0 \ Transmitter Enable
+ $04 constant UCSR0B_UCSZ02 \ Character Size
+ $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
+ $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
+&194 constant UCSR0C \ USART Control and Status Register C
+ $C0 constant UCSR0C_UMSEL0 \ USART Mode Select
+ $30 constant UCSR0C_UPM0 \ Parity Mode Bits
+ $08 constant UCSR0C_USBS0 \ Stop Bit Select
+ $06 constant UCSR0C_UCSZ0 \ Character Size
+ $01 constant UCSR0C_UCPOL0 \ Clock Polarity
+&196 constant UBRR0 \ USART Baud Rate Register Bytes
+\ PORTA
+&34 constant PORTA \ Port A Data Register
+&33 constant DDRA \ Port A Data Direction Register
+&32 constant PINA \ Port A Input Pins
+\ PORTB
+&37 constant PORTB \ Port B Data Register
+&36 constant DDRB \ Port B Data Direction Register
+&35 constant PINB \ Port B Input Pins
+\ PORTC
+&40 constant PORTC \ Port C Data Register
+&39 constant DDRC \ Port C Data Direction Register
+&38 constant PINC \ Port C Input Pins
+\ PORTD
+&43 constant PORTD \ Port D Data Register
+&42 constant DDRD \ Port D Data Direction Register
+&41 constant PIND \ Port D Input Pins
+\ TIMER_COUNTER_0
+&72 constant OCR0B \ Timer/Counter0 Output Compare Register
+&71 constant OCR0A \ Timer/Counter0 Output Compare Register
+&70 constant TCNT0 \ Timer/Counter0
+&69 constant TCCR0B \ Timer/Counter Control Register B
+ $80 constant TCCR0B_FOC0A \ Force Output Compare A
+ $40 constant TCCR0B_FOC0B \ Force Output Compare B
+ $08 constant TCCR0B_WGM02 \
+ $07 constant TCCR0B_CS0 \ Clock Select
+&68 constant TCCR0A \ Timer/Counter Control Register A
+ $C0 constant TCCR0A_COM0A \ Compare Output Mode, Phase Correct PWM Mode
+ $30 constant TCCR0A_COM0B \ Compare Output Mode, Fast PWm
+ $03 constant TCCR0A_WGM0 \ Waveform Generation Mode
+&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
+ $04 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare Match B Interrupt Enable
+ $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match A Interrupt Enable
+ $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
+&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
+ $04 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare Flag 0B
+ $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0A
+ $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
+&67 constant GTCCR \ General Timer/Counter Control Register
+ $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
+ $01 constant GTCCR_PSRSYNC \ Prescaler Reset Timer/Counter1 and Timer/Counter0
+\ TIMER_COUNTER_2
+&112 constant TIMSK2 \ Timer/Counter Interrupt Mask register
+ $04 constant TIMSK2_OCIE2B \ Timer/Counter2 Output Compare Match B Interrupt Enable
+ $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match A Interrupt Enable
+ $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
+&55 constant TIFR2 \ Timer/Counter Interrupt Flag Register
+ $04 constant TIFR2_OCF2B \ Output Compare Flag 2B
+ $02 constant TIFR2_OCF2A \ Output Compare Flag 2A
+ $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
+&176 constant TCCR2A \ Timer/Counter2 Control Register A
+ $C0 constant TCCR2A_COM2A \ Compare Output Mode bits
+ $30 constant TCCR2A_COM2B \ Compare Output Mode bits
+ $03 constant TCCR2A_WGM2 \ Waveform Genration Mode
+&177 constant TCCR2B \ Timer/Counter2 Control Register B
+ $80 constant TCCR2B_FOC2A \ Force Output Compare A
+ $40 constant TCCR2B_FOC2B \ Force Output Compare B
+ $08 constant TCCR2B_WGM22 \ Waveform Generation Mode
+ $07 constant TCCR2B_CS2 \ Clock Select bits
+&178 constant TCNT2 \ Timer/Counter2
+&180 constant OCR2B \ Timer/Counter2 Output Compare Register B
+&179 constant OCR2A \ Timer/Counter2 Output Compare Register A
+&182 constant ASSR \ Asynchronous Status Register
+ $40 constant ASSR_EXCLK \ Enable External Clock Input
+ $20 constant ASSR_AS2 \ Asynchronous Timer/Counter2
+ $10 constant ASSR_TCN2UB \ Timer/Counter2 Update Busy
+ $08 constant ASSR_OCR2AUB \ Output Compare Register2 Update Busy
+ $04 constant ASSR_OCR2BUB \ Output Compare Register 2 Update Busy
+ $02 constant ASSR_TCR2AUB \ Timer/Counter Control Register2 Update Busy
+ $01 constant ASSR_TCR2BUB \ Timer/Counter Control Register2 Update Busy
+\ WATCHDOG
+&96 constant WDTCSR \ Watchdog Timer Control Register
+ $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Flag
+ $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Enable
+ $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
+ $10 constant WDTCSR_WDCE \ Watchdog Change Enable
+ $08 constant WDTCSR_WDE \ Watch Dog Enable
+\ JTAG
+&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
+&85 constant MCUCR \ MCU Control Register
+ $80 constant MCUCR_JTD \ JTAG Interface Disable
+&84 constant MCUSR \ MCU Status Register
+ $10 constant MCUSR_JTRF \ JTAG Reset Flag
+\ BOOT_LOAD
+&87 constant SPMCSR \ Store Program Memory Control Register
+ $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
+ $20 constant SPMCSR_SIGRD \ Signature Row Read
+ $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
+ $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
+ $04 constant SPMCSR_PGWRT \ Page Write
+ $02 constant SPMCSR_PGERS \ Page Erase
+ $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
+\ EXTERNAL_INTERRUPT
+&105 constant EICRA \ External Interrupt Control Register A
+ $30 constant EICRA_ISC2 \ External Interrupt Sense Control Bit
+ $0C constant EICRA_ISC1 \ External Interrupt Sense Control Bit
+ $03 constant EICRA_ISC0 \ External Interrupt Sense Control Bit
+&61 constant EIMSK \ External Interrupt Mask Register
+ $07 constant EIMSK_INT \ External Interrupt Request 2 Enable
+&60 constant EIFR \ External Interrupt Flag Register
+ $07 constant EIFR_INTF \ External Interrupt Flags
+&115 constant PCMSK3 \ Pin Change Mask Register 3
+ $FF constant PCMSK3_PCINT \ Pin Change Enable Masks
+&109 constant PCMSK2 \ Pin Change Mask Register 2
+ $FF constant PCMSK2_PCINT \ Pin Change Enable Masks
+&108 constant PCMSK1 \ Pin Change Mask Register 1
+ $FF constant PCMSK1_PCINT \ Pin Change Enable Masks
+&107 constant PCMSK0 \ Pin Change Mask Register 0
+ $FF constant PCMSK0_PCINT \ Pin Change Enable Masks
+&59 constant PCIFR \ Pin Change Interrupt Flag Register
+ $0F constant PCIFR_PCIF \ Pin Change Interrupt Flags
+&104 constant PCICR \ Pin Change Interrupt Control Register
+ $0F constant PCICR_PCIE \ Pin Change Interrupt Enables
+\ AD_CONVERTER
+&124 constant ADMUX \ The ADC multiplexer Selection Register
+ $C0 constant ADMUX_REFS \ Reference Selection Bits
+ $20 constant ADMUX_ADLAR \ Left Adjust Result
+ $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
+&120 constant ADC \ ADC Data Register Bytes
+&122 constant ADCSRA \ The ADC Control and Status register A
+ $80 constant ADCSRA_ADEN \ ADC Enable
+ $40 constant ADCSRA_ADSC \ ADC Start Conversion
+ $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
+ $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
+ $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
+ $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
+&126 constant DIDR0 \ Digital Input Disable Register
+ $80 constant DIDR0_ADC7D \
+ $40 constant DIDR0_ADC6D \
+ $20 constant DIDR0_ADC5D \
+ $10 constant DIDR0_ADC4D \
+ $08 constant DIDR0_ADC3D \
+ $04 constant DIDR0_ADC2D \
+ $02 constant DIDR0_ADC1D \
+ $01 constant DIDR0_ADC0D \
+\ TIMER_COUNTER_1
+&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
+ $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
+ $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
+ $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
+ $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
+&54 constant TIFR1 \ Timer/Counter Interrupt Flag register
+ $20 constant TIFR1_ICF1 \ Timer/Counter1 Input Capture Flag
+ $04 constant TIFR1_OCF1B \ Timer/Counter1 Output Compare B Match Flag
+ $02 constant TIFR1_OCF1A \ Timer/Counter1 Output Compare A Match Flag
+ $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
+&128 constant TCCR1A \ Timer/Counter1 Control Register A
+ $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
+ $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
+ $03 constant TCCR1A_WGM1 \ Pulse Width Modulator Select Bits
+&129 constant TCCR1B \ Timer/Counter1 Control Register B
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ $18 constant TCCR1B_WGM1 \ Waveform Generation Mode Bits
+ $07 constant TCCR1B_CS1 \ Clock Select1 bits
+&130 constant TCCR1C \ Timer/Counter1 Control Register C
+ $80 constant TCCR1C_FOC1A \ Force Output Compare for Channel A
+ $40 constant TCCR1C_FOC1B \ Force Output Compare for Channel B
+&132 constant TCNT1 \ Timer/Counter1 Bytes
+&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
+&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
+&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
+\ EEPROM
+&65 constant EEAR \ EEPROM Address Register Low Bytes
+&64 constant EEDR \ EEPROM Data Register
+&63 constant EECR \ EEPROM Control Register
+ $30 constant EECR_EEPM \ EEPROM Programming Mode Bits
+ $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
+ $04 constant EECR_EEMPE \ EEPROM Master Write Enable
+ $02 constant EECR_EEPE \ EEPROM Write Enable
+ $01 constant EECR_EERE \ EEPROM Read Enable
+\ SPI
+&78 constant SPDR0 \ SPI Data Register
+&77 constant SPSR0 \ SPI Status Register
+ $80 constant SPSR0_SPIF0 \ SPI Interrupt Flag
+ $40 constant SPSR0_WCOL0 \ Write Collision Flag
+ $01 constant SPSR0_SPI2X0 \ Double SPI Speed Bit
+&76 constant SPCR0 \ SPI Control Register
+ $80 constant SPCR0_SPIE0 \ SPI Interrupt Enable
+ $40 constant SPCR0_SPE0 \ SPI Enable
+ $20 constant SPCR0_DORD0 \ Data Order
+ $10 constant SPCR0_MSTR0 \ Master/Slave Select
+ $08 constant SPCR0_CPOL0 \ Clock polarity
+ $04 constant SPCR0_CPHA0 \ Clock Phase
+ $02 constant SPCR0_SPR10 \ SPI Clock Rate Select 1
+ $01 constant SPCR0_SPR00 \ SPI Clock Rate Select 0
+\ TWI
+&189 constant TWAMR \ TWI (Slave) Address Mask Register
+ $FE constant TWAMR_TWAM \
+&184 constant TWBR \ TWI Bit Rate register
+&188 constant TWCR \ TWI Control Register
+ $80 constant TWCR_TWINT \ TWI Interrupt Flag
+ $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
+ $20 constant TWCR_TWSTA \ TWI Start Condition Bit
+ $10 constant TWCR_TWSTO \ TWI Stop Condition Bit
+ $08 constant TWCR_TWWC \ TWI Write Collition Flag
+ $04 constant TWCR_TWEN \ TWI Enable Bit
+ $01 constant TWCR_TWIE \ TWI Interrupt Enable
+&185 constant TWSR \ TWI Status Register
+ $F8 constant TWSR_TWS \ TWI Status
+ $03 constant TWSR_TWPS \ TWI Prescaler
+&187 constant TWDR \ TWI Data register
+&186 constant TWAR \ TWI (Slave) Address register
+ $FE constant TWAR_TWA \ TWI (Slave) Address register Bits
+ $01 constant TWAR_TWGCE \ TWI General Call Recognition Enable Bit
+\ USART1
+&206 constant UDR1 \ USART I/O Data Register
+&200 constant UCSR1A \ USART Control and Status Register A
+ $80 constant UCSR1A_RXC1 \ USART Receive Complete
+ $40 constant UCSR1A_TXC1 \ USART Transmitt Complete
+ $20 constant UCSR1A_UDRE1 \ USART Data Register Empty
+ $10 constant UCSR1A_FE1 \ Framing Error
+ $08 constant UCSR1A_DOR1 \ Data overRun
+ $04 constant UCSR1A_UPE1 \ Parity Error
+ $02 constant UCSR1A_U2X1 \ Double the USART transmission speed
+ $01 constant UCSR1A_MPCM1 \ Multi-processor Communication Mode
+&201 constant UCSR1B \ USART Control and Status Register B
+ $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable
+ $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable
+ $20 constant UCSR1B_UDRIE1 \ USART Data register Empty Interrupt Enable
+ $10 constant UCSR1B_RXEN1 \ Receiver Enable
+ $08 constant UCSR1B_TXEN1 \ Transmitter Enable
+ $04 constant UCSR1B_UCSZ12 \ Character Size
+ $02 constant UCSR1B_RXB81 \ Receive Data Bit 8
+ $01 constant UCSR1B_TXB81 \ Transmit Data Bit 8
+&202 constant UCSR1C \ USART Control and Status Register C
+ $C0 constant UCSR1C_UMSEL1 \ USART Mode Select
+ $30 constant UCSR1C_UPM1 \ Parity Mode Bits
+ $08 constant UCSR1C_USBS1 \ Stop Bit Select
+ $06 constant UCSR1C_UCSZ1 \ Character Size
+ $01 constant UCSR1C_UCPOL1 \ Clock Polarity
+&204 constant UBRR1 \ USART Baud Rate Register Bytes
+\ CPU
+&95 constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ $08 constant SREG_V \ Two's Complement Overflow Flag
+ $04 constant SREG_N \ Negative Flag
+ $02 constant SREG_Z \ Zero Flag
+ $01 constant SREG_C \ Carry Flag
+&93 constant SP \ Stack Pointer
+&102 constant OSCCAL \ Oscillator Calibration Value
+&97 constant CLKPR \
+ $80 constant CLKPR_CLKPCE \
+ $0F constant CLKPR_CLKPS \
+&83 constant SMCR \ Sleep Mode Control Register
+ $0E constant SMCR_SM \ Sleep Mode Select bits
+ $01 constant SMCR_SE \ Sleep Enable
+&75 constant GPIOR2 \ General Purpose IO Register 2
+ $FF constant GPIOR2_GPIOR \ General Purpose IO Register 2 bis
+&74 constant GPIOR1 \ General Purpose IO Register 1
+ $FF constant GPIOR1_GPIOR \ General Purpose IO Register 1 bis
+&62 constant GPIOR0 \ General Purpose IO Register 0
+ $80 constant GPIOR0_GPIOR07 \ General Purpose IO Register 0 bit 7
+ $40 constant GPIOR0_GPIOR06 \ General Purpose IO Register 0 bit 6
+ $20 constant GPIOR0_GPIOR05 \ General Purpose IO Register 0 bit 5
+ $10 constant GPIOR0_GPIOR04 \ General Purpose IO Register 0 bit 4
+ $08 constant GPIOR0_GPIOR03 \ General Purpose IO Register 0 bit 3
+ $04 constant GPIOR0_GPIOR02 \ General Purpose IO Register 0 bit 2
+ $02 constant GPIOR0_GPIOR01 \ General Purpose IO Register 0 bit 1
+ $01 constant GPIOR0_GPIOR00 \ General Purpose IO Register 0 bit 0
+&100 constant PRR0 \ Power Reduction Register0
+ $80 constant PRR0_PRTWI \ Power Reduction TWI
+ $40 constant PRR0_PRTIM2 \ Power Reduction Timer/Counter2
+ $20 constant PRR0_PRTIM0 \ Power Reduction Timer/Counter0
+ $12 constant PRR0_PRUSART \ Power Reduction USARTs
+ $08 constant PRR0_PRTIM1 \ Power Reduction Timer/Counter1
+ $04 constant PRR0_PRSPI \ Power Reduction Serial Peripheral Interface
+ $01 constant PRR0_PRADC \ Power Reduction ADC
+
+\ Interrupts
+&2 constant INT0Addr \ External Interrupt Request 0
+&4 constant INT1Addr \ External Interrupt Request 1
+&6 constant INT2Addr \ External Interrupt Request 2
+&8 constant PCINT0Addr \ Pin Change Interrupt Request 0
+&10 constant PCINT1Addr \ Pin Change Interrupt Request 1
+&12 constant PCINT2Addr \ Pin Change Interrupt Request 2
+&14 constant PCINT3Addr \ Pin Change Interrupt Request 3
+&16 constant WDTAddr \ Watchdog Time-out Interrupt
+&18 constant TIMER2_COMPAAddr \ Timer/Counter2 Compare Match A
+&20 constant TIMER2_COMPBAddr \ Timer/Counter2 Compare Match B
+&22 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
+&24 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+&26 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
+&28 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
+&30 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+&32 constant TIMER0_COMPAAddr \ Timer/Counter0 Compare Match A
+&34 constant TIMER0_COMPBAddr \ Timer/Counter0 Compare Match B
+&36 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
+&38 constant SPI__STCAddr \ SPI Serial Transfer Complete
+&40 constant USART0__RXAddr \ USART0, Rx Complete
+&42 constant USART0__UDREAddr \ USART0 Data register Empty
+&44 constant USART0__TXAddr \ USART0, Tx Complete
+&46 constant ANALOG_COMPAddr \ Analog Comparator
+&48 constant ADCAddr \ ADC Conversion Complete
+&50 constant EE_READYAddr \ EEPROM Ready
+&52 constant TWIAddr \ 2-wire Serial Interface
+&54 constant SPM_READYAddr \ Store Program Memory Read
+&56 constant USART1_RXAddr \ USART1 RX complete
+&58 constant USART1_UDREAddr \ USART1 Data Register Empty
+&60 constant USART1_TXAddr \ USART1 TX complete
diff --git a/amforth-6.5/avr8/devices/atmega164p/device.asm b/amforth-6.5/avr8/devices/atmega164p/device.asm
new file mode 100644
index 0000000..5fad484
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega164p/device.asm
@@ -0,0 +1,120 @@
+; Partname: ATmega164P
+; generated automatically, do not edit
+
+.nolist
+ .include "m164Pdef.inc"
+.list
+
+.equ ramstart = 256
+.equ CELLSIZE = 2
+.macro readflashcell
+ lsl zl
+ rol zh
+ lpm @0, Z+
+ lpm @1, Z+
+.endmacro
+.macro writeflashcell
+ lsl zl
+ rol zh
+.endmacro
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_USART0 = 0
+.set WANT_PORTA = 0
+.set WANT_PORTB = 0
+.set WANT_PORTC = 0
+.set WANT_PORTD = 0
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_TIMER_COUNTER_2 = 0
+.set WANT_WATCHDOG = 0
+.set WANT_JTAG = 0
+.set WANT_BOOT_LOAD = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_AD_CONVERTER = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_EEPROM = 0
+.set WANT_SPI = 0
+.set WANT_TWI = 0
+.set WANT_USART1 = 0
+.set WANT_CPU = 0
+.equ intvecsize = 2 ; please verify; flash size: 16384 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.org 2
+ rcall isr ; External Interrupt Request 0
+.org 4
+ rcall isr ; External Interrupt Request 1
+.org 6
+ rcall isr ; External Interrupt Request 2
+.org 8
+ rcall isr ; Pin Change Interrupt Request 0
+.org 10
+ rcall isr ; Pin Change Interrupt Request 1
+.org 12
+ rcall isr ; Pin Change Interrupt Request 2
+.org 14
+ rcall isr ; Pin Change Interrupt Request 3
+.org 16
+ rcall isr ; Watchdog Time-out Interrupt
+.org 18
+ rcall isr ; Timer/Counter2 Compare Match A
+.org 20
+ rcall isr ; Timer/Counter2 Compare Match B
+.org 22
+ rcall isr ; Timer/Counter2 Overflow
+.org 24
+ rcall isr ; Timer/Counter1 Capture Event
+.org 26
+ rcall isr ; Timer/Counter1 Compare Match A
+.org 28
+ rcall isr ; Timer/Counter1 Compare Match B
+.org 30
+ rcall isr ; Timer/Counter1 Overflow
+.org 32
+ rcall isr ; Timer/Counter0 Compare Match A
+.org 34
+ rcall isr ; Timer/Counter0 Compare Match B
+.org 36
+ rcall isr ; Timer/Counter0 Overflow
+.org 38
+ rcall isr ; SPI Serial Transfer Complete
+.org 40
+ rcall isr ; USART0, Rx Complete
+.org 42
+ rcall isr ; USART0 Data register Empty
+.org 44
+ rcall isr ; USART0, Tx Complete
+.org 46
+ rcall isr ; Analog Comparator
+.org 48
+ rcall isr ; ADC Conversion Complete
+.org 50
+ rcall isr ; EEPROM Ready
+.org 52
+ rcall isr ; 2-wire Serial Interface
+.org 54
+ rcall isr ; Store Program Memory Read
+.org 56
+ rcall isr ; USART1 RX complete
+.org 58
+ rcall isr ; USART1 Data Register Empty
+.org 60
+ rcall isr ; USART1 TX complete
+.equ INTVECTORS = 31
+.nooverlap
+
+; compatability layer (maybe empty)
+
+; controller data area, environment query mcu-info
+mcu_info:
+mcu_ramsize:
+ .dw 1024
+mcu_eepromsize:
+ .dw 512
+mcu_maxdp:
+ .dw 14336
+mcu_numints:
+ .dw 31
+mcu_name:
+ .dw 10
+ .db "ATmega164P"
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega164p/device.inc b/amforth-6.5/avr8/devices/atmega164p/device.inc
new file mode 100644
index 0000000..47d31fe
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega164p/device.inc
@@ -0,0 +1,1128 @@
+; Partname: ATmega164P
+; generated automatically, no not edit
+
+.if WANT_ANALOG_COMPARATOR == 1
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Control and Status Register B
+VE_ADCSRB:
+ .dw $ff06
+ .db "ADCSRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRB
+XT_ADCSRB:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRB:
+ .dw 123
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Control And Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw 80
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 1
+VE_DIDR1:
+ .dw $ff05
+ .db "DIDR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR1
+XT_DIDR1:
+ .dw PFA_DOVARIABLE
+PFA_DIDR1:
+ .dw 127
+
+.endif
+.if WANT_USART0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR0:
+ .dw $ff04
+ .db "UDR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR0
+XT_UDR0:
+ .dw PFA_DOVARIABLE
+PFA_UDR0:
+ .dw 198
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR0A:
+ .dw $ff06
+ .db "UCSR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0A
+XT_UCSR0A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0A:
+ .dw 192
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR0B:
+ .dw $ff06
+ .db "UCSR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0B
+XT_UCSR0B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0B:
+ .dw 193
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR0C:
+ .dw $ff06
+ .db "UCSR0C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0C
+XT_UCSR0C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0C:
+ .dw 194
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Bytes
+VE_UBRR0:
+ .dw $ff05
+ .db "UBRR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR0
+XT_UBRR0:
+ .dw PFA_DOVARIABLE
+PFA_UBRR0:
+ .dw 196
+
+.endif
+.if WANT_PORTA == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Register
+VE_PORTA:
+ .dw $ff05
+ .db "PORTA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTA
+XT_PORTA:
+ .dw PFA_DOVARIABLE
+PFA_PORTA:
+ .dw 34
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Direction Register
+VE_DDRA:
+ .dw $ff04
+ .db "DDRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRA
+XT_DDRA:
+ .dw PFA_DOVARIABLE
+PFA_DDRA:
+ .dw 33
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Input Pins
+VE_PINA:
+ .dw $ff04
+ .db "PINA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINA
+XT_PINA:
+ .dw PFA_DOVARIABLE
+PFA_PINA:
+ .dw 32
+
+.endif
+.if WANT_PORTB == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw 37
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw 36
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw 35
+
+.endif
+.if WANT_PORTC == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Register
+VE_PORTC:
+ .dw $ff05
+ .db "PORTC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTC
+XT_PORTC:
+ .dw PFA_DOVARIABLE
+PFA_PORTC:
+ .dw 40
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Direction Register
+VE_DDRC:
+ .dw $ff04
+ .db "DDRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRC
+XT_DDRC:
+ .dw PFA_DOVARIABLE
+PFA_DDRC:
+ .dw 39
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Input Pins
+VE_PINC:
+ .dw $ff04
+ .db "PINC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINC
+XT_PINC:
+ .dw PFA_DOVARIABLE
+PFA_PINC:
+ .dw 38
+
+.endif
+.if WANT_PORTD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw 43
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw 42
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw 41
+
+.endif
+.if WANT_TIMER_COUNTER_0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0B:
+ .dw $ff05
+ .db "OCR0B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0B
+XT_OCR0B:
+ .dw PFA_DOVARIABLE
+PFA_OCR0B:
+ .dw 72
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0A:
+ .dw $ff05
+ .db "OCR0A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0A
+XT_OCR0A:
+ .dw PFA_DOVARIABLE
+PFA_OCR0A:
+ .dw 71
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw 70
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register B
+VE_TCCR0B:
+ .dw $ff06
+ .db "TCCR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0B
+XT_TCCR0B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0B:
+ .dw 69
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register A
+VE_TCCR0A:
+ .dw $ff06
+ .db "TCCR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0A
+XT_TCCR0A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0A:
+ .dw 68
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Mask Register
+VE_TIMSK0:
+ .dw $ff06
+ .db "TIMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK0
+XT_TIMSK0:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK0:
+ .dw 110
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Flag register
+VE_TIFR0:
+ .dw $ff05
+ .db "TIFR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR0
+XT_TIFR0:
+ .dw PFA_DOVARIABLE
+PFA_TIFR0:
+ .dw 53
+; ( -- addr ) System Constant
+; R( -- )
+; General Timer/Counter Control Register
+VE_GTCCR:
+ .dw $ff05
+ .db "GTCCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GTCCR
+XT_GTCCR:
+ .dw PFA_DOVARIABLE
+PFA_GTCCR:
+ .dw 67
+
+.endif
+.if WANT_TIMER_COUNTER_2 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Mask register
+VE_TIMSK2:
+ .dw $ff06
+ .db "TIMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK2
+XT_TIMSK2:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK2:
+ .dw 112
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Flag Register
+VE_TIFR2:
+ .dw $ff05
+ .db "TIFR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR2
+XT_TIFR2:
+ .dw PFA_DOVARIABLE
+PFA_TIFR2:
+ .dw 55
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register A
+VE_TCCR2A:
+ .dw $ff06
+ .db "TCCR2A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2A
+XT_TCCR2A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2A:
+ .dw 176
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register B
+VE_TCCR2B:
+ .dw $ff06
+ .db "TCCR2B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2B
+XT_TCCR2B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2B:
+ .dw 177
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2
+VE_TCNT2:
+ .dw $ff05
+ .db "TCNT2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT2
+XT_TCNT2:
+ .dw PFA_DOVARIABLE
+PFA_TCNT2:
+ .dw 178
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register B
+VE_OCR2B:
+ .dw $ff05
+ .db "OCR2B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2B
+XT_OCR2B:
+ .dw PFA_DOVARIABLE
+PFA_OCR2B:
+ .dw 180
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register A
+VE_OCR2A:
+ .dw $ff05
+ .db "OCR2A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2A
+XT_OCR2A:
+ .dw PFA_DOVARIABLE
+PFA_OCR2A:
+ .dw 179
+; ( -- addr ) System Constant
+; R( -- )
+; Asynchronous Status Register
+VE_ASSR:
+ .dw $ff04
+ .db "ASSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ASSR
+XT_ASSR:
+ .dw PFA_DOVARIABLE
+PFA_ASSR:
+ .dw 182
+
+.endif
+.if WANT_WATCHDOG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCSR:
+ .dw $ff06
+ .db "WDTCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCSR
+XT_WDTCSR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCSR:
+ .dw 96
+
+.endif
+.if WANT_JTAG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; On-Chip Debug Related Register in I/O Memory
+VE_OCDR:
+ .dw $ff04
+ .db "OCDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCDR
+XT_OCDR:
+ .dw PFA_DOVARIABLE
+PFA_OCDR:
+ .dw 81
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw 85
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Status Register
+VE_MCUSR:
+ .dw $ff05
+ .db "MCUSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUSR
+XT_MCUSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUSR:
+ .dw 84
+
+.endif
+.if WANT_BOOT_LOAD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control Register
+VE_SPMCSR:
+ .dw $ff06
+ .db "SPMCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCSR
+XT_SPMCSR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCSR:
+ .dw 87
+
+.endif
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register A
+VE_EICRA:
+ .dw $ff05
+ .db "EICRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRA
+XT_EICRA:
+ .dw PFA_DOVARIABLE
+PFA_EICRA:
+ .dw 105
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Mask Register
+VE_EIMSK:
+ .dw $ff05
+ .db "EIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIMSK
+XT_EIMSK:
+ .dw PFA_DOVARIABLE
+PFA_EIMSK:
+ .dw 61
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Flag Register
+VE_EIFR:
+ .dw $ff04
+ .db "EIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIFR
+XT_EIFR:
+ .dw PFA_DOVARIABLE
+PFA_EIFR:
+ .dw 60
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 3
+VE_PCMSK3:
+ .dw $ff06
+ .db "PCMSK3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK3
+XT_PCMSK3:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK3:
+ .dw 115
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 2
+VE_PCMSK2:
+ .dw $ff06
+ .db "PCMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK2
+XT_PCMSK2:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK2:
+ .dw 109
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 1
+VE_PCMSK1:
+ .dw $ff06
+ .db "PCMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK1
+XT_PCMSK1:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK1:
+ .dw 108
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 0
+VE_PCMSK0:
+ .dw $ff06
+ .db "PCMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK0
+XT_PCMSK0:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK0:
+ .dw 107
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Interrupt Flag Register
+VE_PCIFR:
+ .dw $ff05
+ .db "PCIFR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCIFR
+XT_PCIFR:
+ .dw PFA_DOVARIABLE
+PFA_PCIFR:
+ .dw 59
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Interrupt Control Register
+VE_PCICR:
+ .dw $ff05
+ .db "PCICR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCICR
+XT_PCICR:
+ .dw PFA_DOVARIABLE
+PFA_PCICR:
+ .dw 104
+
+.endif
+.if WANT_AD_CONVERTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC multiplexer Selection Register
+VE_ADMUX:
+ .dw $ff05
+ .db "ADMUX",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADMUX
+XT_ADMUX:
+ .dw PFA_DOVARIABLE
+PFA_ADMUX:
+ .dw 124
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register Bytes
+VE_ADC:
+ .dw $ff03
+ .db "ADC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADC
+XT_ADC:
+ .dw PFA_DOVARIABLE
+PFA_ADC:
+ .dw 120
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register A
+VE_ADCSRA:
+ .dw $ff06
+ .db "ADCSRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRA
+XT_ADCSRA:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRA:
+ .dw 122
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register
+VE_DIDR0:
+ .dw $ff05
+ .db "DIDR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR0
+XT_DIDR0:
+ .dw PFA_DOVARIABLE
+PFA_DIDR0:
+ .dw 126
+
+.endif
+.if WANT_TIMER_COUNTER_1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Mask Register
+VE_TIMSK1:
+ .dw $ff06
+ .db "TIMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK1
+XT_TIMSK1:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK1:
+ .dw 111
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Flag register
+VE_TIFR1:
+ .dw $ff05
+ .db "TIFR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR1
+XT_TIFR1:
+ .dw PFA_DOVARIABLE
+PFA_TIFR1:
+ .dw 54
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw 128
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw 129
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register C
+VE_TCCR1C:
+ .dw $ff06
+ .db "TCCR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1C
+XT_TCCR1C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1C:
+ .dw 130
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Bytes
+VE_TCNT1:
+ .dw $ff05
+ .db "TCNT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1
+XT_TCNT1:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1:
+ .dw 132
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register A Bytes
+VE_OCR1A:
+ .dw $ff05
+ .db "OCR1A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1A
+XT_OCR1A:
+ .dw PFA_DOVARIABLE
+PFA_OCR1A:
+ .dw 136
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register B Bytes
+VE_OCR1B:
+ .dw $ff05
+ .db "OCR1B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1B
+XT_OCR1B:
+ .dw PFA_DOVARIABLE
+PFA_OCR1B:
+ .dw 138
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Bytes
+VE_ICR1:
+ .dw $ff04
+ .db "ICR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1
+XT_ICR1:
+ .dw PFA_DOVARIABLE
+PFA_ICR1:
+ .dw 134
+
+.endif
+.if WANT_EEPROM == 1
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Address Register Low Bytes
+VE_EEAR:
+ .dw $ff04
+ .db "EEAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEAR
+XT_EEAR:
+ .dw PFA_DOVARIABLE
+PFA_EEAR:
+ .dw 65
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw 64
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw 63
+
+.endif
+.if WANT_SPI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR0:
+ .dw $ff05
+ .db "SPDR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR0
+XT_SPDR0:
+ .dw PFA_DOVARIABLE
+PFA_SPDR0:
+ .dw 78
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR0:
+ .dw $ff05
+ .db "SPSR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR0
+XT_SPSR0:
+ .dw PFA_DOVARIABLE
+PFA_SPSR0:
+ .dw 77
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR0:
+ .dw $ff05
+ .db "SPCR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR0
+XT_SPCR0:
+ .dw PFA_DOVARIABLE
+PFA_SPCR0:
+ .dw 76
+
+.endif
+.if WANT_TWI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; TWI (Slave) Address Mask Register
+VE_TWAMR:
+ .dw $ff05
+ .db "TWAMR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWAMR
+XT_TWAMR:
+ .dw PFA_DOVARIABLE
+PFA_TWAMR:
+ .dw 189
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Bit Rate register
+VE_TWBR:
+ .dw $ff04
+ .db "TWBR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWBR
+XT_TWBR:
+ .dw PFA_DOVARIABLE
+PFA_TWBR:
+ .dw 184
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Control Register
+VE_TWCR:
+ .dw $ff04
+ .db "TWCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWCR
+XT_TWCR:
+ .dw PFA_DOVARIABLE
+PFA_TWCR:
+ .dw 188
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Status Register
+VE_TWSR:
+ .dw $ff04
+ .db "TWSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWSR
+XT_TWSR:
+ .dw PFA_DOVARIABLE
+PFA_TWSR:
+ .dw 185
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Data register
+VE_TWDR:
+ .dw $ff04
+ .db "TWDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWDR
+XT_TWDR:
+ .dw PFA_DOVARIABLE
+PFA_TWDR:
+ .dw 187
+; ( -- addr ) System Constant
+; R( -- )
+; TWI (Slave) Address register
+VE_TWAR:
+ .dw $ff04
+ .db "TWAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWAR
+XT_TWAR:
+ .dw PFA_DOVARIABLE
+PFA_TWAR:
+ .dw 186
+
+.endif
+.if WANT_USART1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR1:
+ .dw $ff04
+ .db "UDR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR1
+XT_UDR1:
+ .dw PFA_DOVARIABLE
+PFA_UDR1:
+ .dw 206
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR1A:
+ .dw $ff06
+ .db "UCSR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1A
+XT_UCSR1A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1A:
+ .dw 200
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR1B:
+ .dw $ff06
+ .db "UCSR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1B
+XT_UCSR1B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1B:
+ .dw 201
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR1C:
+ .dw $ff06
+ .db "UCSR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1C
+XT_UCSR1C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1C:
+ .dw 202
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Bytes
+VE_UBRR1:
+ .dw $ff05
+ .db "UBRR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR1
+XT_UBRR1:
+ .dw PFA_DOVARIABLE
+PFA_UBRR1:
+ .dw 204
+
+.endif
+.if WANT_CPU == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw 95
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer
+VE_SP:
+ .dw $ff02
+ .db "SP"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SP
+XT_SP:
+ .dw PFA_DOVARIABLE
+PFA_SP:
+ .dw 93
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Calibration Value
+VE_OSCCAL:
+ .dw $ff06
+ .db "OSCCAL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSCCAL
+XT_OSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_OSCCAL:
+ .dw 102
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_CLKPR:
+ .dw $ff05
+ .db "CLKPR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKPR
+XT_CLKPR:
+ .dw PFA_DOVARIABLE
+PFA_CLKPR:
+ .dw 97
+; ( -- addr ) System Constant
+; R( -- )
+; Sleep Mode Control Register
+VE_SMCR:
+ .dw $ff04
+ .db "SMCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SMCR
+XT_SMCR:
+ .dw PFA_DOVARIABLE
+PFA_SMCR:
+ .dw 83
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 2
+VE_GPIOR2:
+ .dw $ff06
+ .db "GPIOR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR2
+XT_GPIOR2:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR2:
+ .dw 75
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 1
+VE_GPIOR1:
+ .dw $ff06
+ .db "GPIOR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR1
+XT_GPIOR1:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR1:
+ .dw 74
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 0
+VE_GPIOR0:
+ .dw $ff06
+ .db "GPIOR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR0
+XT_GPIOR0:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR0:
+ .dw 62
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register0
+VE_PRR0:
+ .dw $ff04
+ .db "PRR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR0
+XT_PRR0:
+ .dw PFA_DOVARIABLE
+PFA_PRR0:
+ .dw 100
+
+.endif
diff --git a/amforth-6.5/avr8/devices/atmega164p/device.py b/amforth-6.5/avr8/devices/atmega164p/device.py
new file mode 100644
index 0000000..31eda10
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega164p/device.py
@@ -0,0 +1,389 @@
+# Generated Automatically
+
+# Partname ATmega164P
+
+MCUREGS = {
+# Interrupt Vectors
+ 'INT0Addr' : '#2', # External Interrupt Request 0
+ 'INT1Addr' : '#4', # External Interrupt Request 1
+ 'INT2Addr' : '#6', # External Interrupt Request 2
+ 'PCINT0Addr' : '#8', # Pin Change Interrupt Request 0
+ 'PCINT1Addr' : '#10', # Pin Change Interrupt Request 1
+ 'PCINT2Addr' : '#12', # Pin Change Interrupt Request 2
+ 'PCINT3Addr' : '#14', # Pin Change Interrupt Request 3
+ 'WDTAddr' : '#16', # Watchdog Time-out Interrupt
+ 'TIMER2_COMPAAddr' : '#18', # Timer/Counter2 Compare Match A
+ 'TIMER2_COMPBAddr' : '#20', # Timer/Counter2 Compare Match B
+ 'TIMER2_OVFAddr' : '#22', # Timer/Counter2 Overflow
+ 'TIMER1_CAPTAddr' : '#24', # Timer/Counter1 Capture Event
+ 'TIMER1_COMPAAddr' : '#26', # Timer/Counter1 Compare Match A
+ 'TIMER1_COMPBAddr' : '#28', # Timer/Counter1 Compare Match B
+ 'TIMER1_OVFAddr' : '#30', # Timer/Counter1 Overflow
+ 'TIMER0_COMPAAddr' : '#32', # Timer/Counter0 Compare Match A
+ 'TIMER0_COMPBAddr' : '#34', # Timer/Counter0 Compare Match B
+ 'TIMER0_OVFAddr' : '#36', # Timer/Counter0 Overflow
+ 'SPI_STCAddr' : '#38', # SPI Serial Transfer Complete
+ 'USART0_RXAddr' : '#40', # USART0, Rx Complete
+ 'USART0_UDREAddr' : '#42', # USART0 Data register Empty
+ 'USART0_TXAddr' : '#44', # USART0, Tx Complete
+ 'ANALOG_COMPAddr' : '#46', # Analog Comparator
+ 'ADCAddr' : '#48', # ADC Conversion Complete
+ 'EE_READYAddr' : '#50', # EEPROM Ready
+ 'TWIAddr' : '#52', # 2-wire Serial Interface
+ 'SPM_READYAddr' : '#54', # Store Program Memory Read
+ 'USART1_RXAddr' : '#56', # USART1 RX complete
+ 'USART1_UDREAddr' : '#58', # USART1 Data Register Empty
+ 'USART1_TXAddr' : '#60', # USART1 TX complete
+
+# Module ANALOG_COMPARATOR
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
+ 'ACSR' : '$50', # Analog Comparator Control And
+ 'ACSR_ACD': '$80', # Analog Comparator Disable
+ 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
+ 'ACSR_ACO': '$20', # Analog Compare Output
+ 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
+ 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
+ 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
+ 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
+ 'DIDR1' : '$7f', # Digital Input Disable Register
+ 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
+ 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
+
+# Module USART0
+ 'UDR0' : '$c6', # USART I/O Data Register
+ 'UCSR0A' : '$c0', # USART Control and Status Regis
+ 'UCSR0A_RXC0': '$80', # USART Receive Complete
+ 'UCSR0A_TXC0': '$40', # USART Transmitt Complete
+ 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
+ 'UCSR0A_FE0': '$10', # Framing Error
+ 'UCSR0A_DOR0': '$8', # Data overRun
+ 'UCSR0A_UPE0': '$4', # Parity Error
+ 'UCSR0A_U2X0': '$2', # Double the USART transmission
+ 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
+ 'UCSR0B' : '$c1', # USART Control and Status Regis
+ 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
+ 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
+ 'UCSR0B_UDRIE0': '$20', # USART Data register Empty Inte
+ 'UCSR0B_RXEN0': '$10', # Receiver Enable
+ 'UCSR0B_TXEN0': '$8', # Transmitter Enable
+ 'UCSR0B_UCSZ02': '$4', # Character Size
+ 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
+ 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
+ 'UCSR0C' : '$c2', # USART Control and Status Regis
+ 'UCSR0C_UMSEL0': '$c0', # USART Mode Select
+ 'UCSR0C_UPM0': '$30', # Parity Mode Bits
+ 'UCSR0C_USBS0': '$8', # Stop Bit Select
+ 'UCSR0C_UCSZ0': '$6', # Character Size
+ 'UCSR0C_UCPOL0': '$1', # Clock Polarity
+ 'UBRR0' : '$c4', # USART Baud Rate Register Byte
+
+# Module PORTA
+ 'PORTA' : '$22', # Port A Data Register
+ 'DDRA' : '$21', # Port A Data Direction Register
+ 'PINA' : '$20', # Port A Input Pins
+
+# Module PORTB
+ 'PORTB' : '$25', # Port B Data Register
+ 'DDRB' : '$24', # Port B Data Direction Register
+ 'PINB' : '$23', # Port B Input Pins
+
+# Module PORTC
+ 'PORTC' : '$28', # Port C Data Register
+ 'DDRC' : '$27', # Port C Data Direction Register
+ 'PINC' : '$26', # Port C Input Pins
+
+# Module PORTD
+ 'PORTD' : '$2b', # Port D Data Register
+ 'DDRD' : '$2a', # Port D Data Direction Register
+ 'PIND' : '$29', # Port D Input Pins
+
+# Module TIMER_COUNTER_0
+ 'OCR0B' : '$48', # Timer/Counter0 Output Compare
+ 'OCR0A' : '$47', # Timer/Counter0 Output Compare
+ 'TCNT0' : '$46', # Timer/Counter0
+ 'TCCR0B' : '$45', # Timer/Counter Control Register
+ 'TCCR0B_FOC0A': '$80', # Force Output Compare A
+ 'TCCR0B_FOC0B': '$40', # Force Output Compare B
+ 'TCCR0B_WGM02': '$8', #
+ 'TCCR0B_CS0': '$7', # Clock Select
+ 'TCCR0A' : '$44', # Timer/Counter Control Registe
+ 'TCCR0A_COM0A': '$c0', # Compare Output Mode, Phase Cor
+ 'TCCR0A_COM0B': '$30', # Compare Output Mode, Fast PWm
+ 'TCCR0A_WGM0': '$3', # Waveform Generation Mode
+ 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
+ 'TIMSK0_OCIE0B': '$4', # Timer/Counter0 Output Compare
+ 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
+ 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
+ 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
+ 'TIFR0_OCF0B': '$4', # Timer/Counter0 Output Compare
+ 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
+ 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSRSYNC': '$1', # Prescaler Reset Timer/Counter1
+
+# Module TIMER_COUNTER_2
+ 'TIMSK2' : '$70', # Timer/Counter Interrupt Mask r
+ 'TIMSK2_OCIE2B': '$4', # Timer/Counter2 Output Compare
+ 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
+ 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
+ 'TIFR2' : '$37', # Timer/Counter Interrupt Flag R
+ 'TIFR2_OCF2B': '$4', # Output Compare Flag 2B
+ 'TIFR2_OCF2A': '$2', # Output Compare Flag 2A
+ 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
+ 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
+ 'TCCR2A_COM2A': '$c0', # Compare Output Mode bits
+ 'TCCR2A_COM2B': '$30', # Compare Output Mode bits
+ 'TCCR2A_WGM2': '$3', # Waveform Genration Mode
+ 'TCCR2B' : '$b1', # Timer/Counter2 Control Registe
+ 'TCCR2B_FOC2A': '$80', # Force Output Compare A
+ 'TCCR2B_FOC2B': '$40', # Force Output Compare B
+ 'TCCR2B_WGM22': '$8', # Waveform Generation Mode
+ 'TCCR2B_CS2': '$7', # Clock Select bits
+ 'TCNT2' : '$b2', # Timer/Counter2
+ 'OCR2B' : '$b4', # Timer/Counter2 Output Compare
+ 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
+ 'ASSR' : '$b6', # Asynchronous Status Register
+ 'ASSR_EXCLK': '$40', # Enable External Clock Input
+ 'ASSR_AS2': '$20', # Asynchronous Timer/Counter2
+ 'ASSR_TCN2UB': '$10', # Timer/Counter2 Update Busy
+ 'ASSR_OCR2AUB': '$8', # Output Compare Register2 Updat
+ 'ASSR_OCR2BUB': '$4', # Output Compare Register 2 Upda
+ 'ASSR_TCR2AUB': '$2', # Timer/Counter Control Register
+ 'ASSR_TCR2BUB': '$1', # Timer/Counter Control Register
+ 'GTCCR' : '$43', # General Timer Counter Control
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSRASY': '$2', # Prescaler Reset Timer/Counter2
+
+# Module WATCHDOG
+ 'WDTCSR' : '$60', # Watchdog Timer Control Registe
+ 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
+ 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
+ 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
+ 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
+ 'WDTCSR_WDE': '$8', # Watch Dog Enable
+
+# Module JTAG
+ 'OCDR' : '$51', # On-Chip Debug Related Register
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_JTD': '$80', # JTAG Interface Disable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+
+# Module BOOT_LOAD
+ 'SPMCSR' : '$57', # Store Program Memory Control R
+ 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
+ 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
+ 'SPMCSR_SIGRD': '$20', # Signature Row Read
+ 'SPMCSR_RWWSRE': '$10', # Read While Write section read
+ 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
+ 'SPMCSR_PGWRT': '$4', # Page Write
+ 'SPMCSR_PGERS': '$2', # Page Erase
+ 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
+
+# Module EXTERNAL_INTERRUPT
+ 'EICRA' : '$69', # External Interrupt Control Reg
+ 'EICRA_ISC2': '$30', # External Interrupt Sense Contr
+ 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
+ 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
+ 'EIMSK' : '$3d', # External Interrupt Mask Regist
+ 'EIMSK_INT': '$7', # External Interrupt Request 2 E
+ 'EIFR' : '$3c', # External Interrupt Flag Regist
+ 'EIFR_INTF': '$7', # External Interrupt Flags
+ 'PCMSK3' : '$73', # Pin Change Mask Register 3
+ 'PCMSK3_PCINT': '$ff', # Pin Change Enable Masks
+ 'PCMSK2' : '$6d', # Pin Change Mask Register 2
+ 'PCMSK2_PCINT': '$ff', # Pin Change Enable Masks
+ 'PCMSK1' : '$6c', # Pin Change Mask Register 1
+ 'PCMSK1_PCINT': '$ff', # Pin Change Enable Masks
+ 'PCMSK0' : '$6b', # Pin Change Mask Register 0
+ 'PCMSK0_PCINT': '$ff', # Pin Change Enable Masks
+ 'PCIFR' : '$3b', # Pin Change Interrupt Flag Regi
+ 'PCIFR_PCIF': '$f', # Pin Change Interrupt Flags
+ 'PCICR' : '$68', # Pin Change Interrupt Control R
+ 'PCICR_PCIE': '$f', # Pin Change Interrupt Enables
+
+# Module AD_CONVERTER
+ 'ADMUX' : '$7c', # The ADC multiplexer Selection
+ 'ADMUX_REFS': '$c0', # Reference Selection Bits
+ 'ADMUX_ADLAR': '$20', # Left Adjust Result
+ 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
+ 'ADC' : '$78', # ADC Data Register Bytes
+ 'ADCSRA' : '$7a', # The ADC Control and Status reg
+ 'ADCSRA_ADEN': '$80', # ADC Enable
+ 'ADCSRA_ADSC': '$40', # ADC Start Conversion
+ 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
+ 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
+ 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
+ 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
+ 'ADCSRB' : '$7b', # The ADC Control and Status reg
+ 'ADCSRB_ACME': '$40', #
+ 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Source bits
+ 'DIDR0' : '$7e', # Digital Input Disable Register
+ 'DIDR0_ADC7D': '$80', #
+ 'DIDR0_ADC6D': '$40', #
+ 'DIDR0_ADC5D': '$20', #
+ 'DIDR0_ADC4D': '$10', #
+ 'DIDR0_ADC3D': '$8', #
+ 'DIDR0_ADC2D': '$4', #
+ 'DIDR0_ADC1D': '$2', #
+ 'DIDR0_ADC0D': '$1', #
+
+# Module TIMER_COUNTER_1
+ 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
+ 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
+ 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
+ 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
+ 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
+ 'TIFR1' : '$36', # Timer/Counter Interrupt Flag r
+ 'TIFR1_ICF1': '$20', # Timer/Counter1 Input Capture F
+ 'TIFR1_OCF1B': '$4', # Timer/Counter1 Output Compare
+ 'TIFR1_OCF1A': '$2', # Timer/Counter1 Output Compare
+ 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
+ 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
+ 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
+ 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
+ 'TCCR1A_WGM1': '$3', # Pulse Width Modulator Select B
+ 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
+ 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
+ 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
+ 'TCCR1B_WGM1': '$18', # Waveform Generation Mode Bits
+ 'TCCR1B_CS1': '$7', # Clock Select1 bits
+ 'TCCR1C' : '$82', # Timer/Counter1 Control Registe
+ 'TCCR1C_FOC1A': '$80', # Force Output Compare for Chann
+ 'TCCR1C_FOC1B': '$40', # Force Output Compare for Chann
+ 'TCNT1' : '$84', # Timer/Counter1 Bytes
+ 'OCR1A' : '$88', # Timer/Counter1 Output Compare
+ 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
+ 'ICR1' : '$86', # Timer/Counter1 Input Capture R
+
+# Module EEPROM
+ 'EEAR' : '$41', # EEPROM Address Register Low By
+ 'EEDR' : '$40', # EEPROM Data Register
+ 'EECR' : '$3f', # EEPROM Control Register
+ 'EECR_EEPM': '$30', # EEPROM Programming Mode Bits
+ 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
+ 'EECR_EEMPE': '$4', # EEPROM Master Write Enable
+ 'EECR_EEPE': '$2', # EEPROM Write Enable
+ 'EECR_EERE': '$1', # EEPROM Read Enable
+
+# Module SPI
+ 'SPDR0' : '$4e', # SPI Data Register
+ 'SPSR0' : '$4d', # SPI Status Register
+ 'SPSR0_SPIF0': '$80', # SPI Interrupt Flag
+ 'SPSR0_WCOL0': '$40', # Write Collision Flag
+ 'SPSR0_SPI2X0': '$1', # Double SPI Speed Bit
+ 'SPCR0' : '$4c', # SPI Control Register
+ 'SPCR0_SPIE0': '$80', # SPI Interrupt Enable
+ 'SPCR0_SPE0': '$40', # SPI Enable
+ 'SPCR0_DORD0': '$20', # Data Order
+ 'SPCR0_MSTR0': '$10', # Master/Slave Select
+ 'SPCR0_CPOL0': '$8', # Clock polarity
+ 'SPCR0_CPHA0': '$4', # Clock Phase
+ 'SPCR0_SPR10': '$2', # SPI Clock Rate Select 1
+ 'SPCR0_SPR00': '$1', # SPI Clock Rate Select 0
+
+# Module TWI
+ 'TWAMR' : '$bd', # TWI (Slave) Address Mask Regis
+ 'TWAMR_TWAM': '$fe', #
+ 'TWBR' : '$b8', # TWI Bit Rate register
+ 'TWCR' : '$bc', # TWI Control Register
+ 'TWCR_TWINT': '$80', # TWI Interrupt Flag
+ 'TWCR_TWEA': '$40', # TWI Enable Acknowledge Bit
+ 'TWCR_TWSTA': '$20', # TWI Start Condition Bit
+ 'TWCR_TWSTO': '$10', # TWI Stop Condition Bit
+ 'TWCR_TWWC': '$8', # TWI Write Collition Flag
+ 'TWCR_TWEN': '$4', # TWI Enable Bit
+ 'TWCR_TWIE': '$1', # TWI Interrupt Enable
+ 'TWSR' : '$b9', # TWI Status Register
+ 'TWSR_TWS': '$f8', # TWI Status
+ 'TWSR_TWPS': '$3', # TWI Prescaler
+ 'TWDR' : '$bb', # TWI Data register
+ 'TWAR' : '$ba', # TWI (Slave) Address register
+ 'TWAR_TWA': '$fe', # TWI (Slave) Address register B
+ 'TWAR_TWGCE': '$1', # TWI General Call Recognition E
+
+# Module USART1
+ 'UDR1' : '$ce', # USART I/O Data Register
+ 'UCSR1A' : '$c8', # USART Control and Status Regis
+ 'UCSR1A_RXC1': '$80', # USART Receive Complete
+ 'UCSR1A_TXC1': '$40', # USART Transmitt Complete
+ 'UCSR1A_UDRE1': '$20', # USART Data Register Empty
+ 'UCSR1A_FE1': '$10', # Framing Error
+ 'UCSR1A_DOR1': '$8', # Data overRun
+ 'UCSR1A_UPE1': '$4', # Parity Error
+ 'UCSR1A_U2X1': '$2', # Double the USART transmission
+ 'UCSR1A_MPCM1': '$1', # Multi-processor Communication
+ 'UCSR1B' : '$c9', # USART Control and Status Regis
+ 'UCSR1B_RXCIE1': '$80', # RX Complete Interrupt Enable
+ 'UCSR1B_TXCIE1': '$40', # TX Complete Interrupt Enable
+ 'UCSR1B_UDRIE1': '$20', # USART Data register Empty Inte
+ 'UCSR1B_RXEN1': '$10', # Receiver Enable
+ 'UCSR1B_TXEN1': '$8', # Transmitter Enable
+ 'UCSR1B_UCSZ12': '$4', # Character Size
+ 'UCSR1B_RXB81': '$2', # Receive Data Bit 8
+ 'UCSR1B_TXB81': '$1', # Transmit Data Bit 8
+ 'UCSR1C' : '$ca', # USART Control and Status Regis
+ 'UCSR1C_UMSEL1': '$c0', # USART Mode Select
+ 'UCSR1C_UPM1': '$30', # Parity Mode Bits
+ 'UCSR1C_USBS1': '$8', # Stop Bit Select
+ 'UCSR1C_UCSZ1': '$6', # Character Size
+ 'UCSR1C_UCPOL1': '$1', # Clock Polarity
+ 'UBRR1' : '$cc', # USART Baud Rate Register Byte
+
+# Module CPU
+ 'SREG' : '$5f', # Status Register
+ 'SREG_I': '$80', # Global Interrupt Enable
+ 'SREG_T': '$40', # Bit Copy Storage
+ 'SREG_H': '$20', # Half Carry Flag
+ 'SREG_S': '$10', # Sign Bit
+ 'SREG_V': '$8', # Two's Complement Overflow Flag
+ 'SREG_N': '$4', # Negative Flag
+ 'SREG_Z': '$2', # Zero Flag
+ 'SREG_C': '$1', # Carry Flag
+ 'SP' : '$5d', # Stack Pointer
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_JTD': '$80', # JTAG Interface Disable
+ 'MCUCR_BODS': '$40', # BOD Power Down in Sleep
+ 'MCUCR_BODSE': '$20', # BOD Power Down in Sleep Enable
+ 'MCUCR_PUD': '$10', # Pull-up disable
+ 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
+ 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+ 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
+ 'MCUSR_BORF': '$4', # Brown-out Reset Flag
+ 'MCUSR_EXTRF': '$2', # External Reset Flag
+ 'MCUSR_PORF': '$1', # Power-on reset flag
+ 'OSCCAL' : '$66', # Oscillator Calibration Value
+ 'CLKPR' : '$61', #
+ 'CLKPR_CLKPCE': '$80', #
+ 'CLKPR_CLKPS': '$f', #
+ 'SMCR' : '$53', # Sleep Mode Control Register
+ 'SMCR_SM': '$e', # Sleep Mode Select bits
+ 'SMCR_SE': '$1', # Sleep Enable
+ 'GPIOR2' : '$4b', # General Purpose IO Register 2
+ 'GPIOR2_GPIOR': '$ff', # General Purpose IO Register 2
+ 'GPIOR1' : '$4a', # General Purpose IO Register 1
+ 'GPIOR1_GPIOR': '$ff', # General Purpose IO Register 1
+ 'GPIOR0' : '$3e', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR07': '$80', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR06': '$40', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR05': '$20', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR04': '$10', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR03': '$8', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR02': '$4', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR01': '$2', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR00': '$1', # General Purpose IO Register 0
+ 'PRR0' : '$64', # Power Reduction Register0
+ 'PRR0_PRTWI': '$80', # Power Reduction TWI
+ 'PRR0_PRTIM2': '$40', # Power Reduction Timer/Counter2
+ 'PRR0_PRTIM0': '$20', # Power Reduction Timer/Counter0
+ 'PRR0_PRUSART': '$12', # Power Reduction USARTs
+ 'PRR0_PRTIM1': '$8', # Power Reduction Timer/Counter1
+ 'PRR0_PRSPI': '$4', # Power Reduction Serial Periphe
+ 'PRR0_PRADC': '$1', # Power Reduction ADC
+
+ '__amforth_dummy':'0'
+}
diff --git a/amforth-6.5/avr8/devices/atmega164p/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega164p/words/no-jtag.asm
new file mode 100644
index 0000000..352a4bb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega164p/words/no-jtag.asm
@@ -0,0 +1,14 @@
+; ( -- )
+; ( -- )
+; MCU
+; disable jtag at runtime
+VE_NOJTAG:
+ .dw $FF05
+ .db "-jtag",0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOJTAG
+XT_NOJTAG:
+ .dw PFA_NOJTAG
+PFA_NOJTAG:
+
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega164p/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega164p/words/no-wdt.asm
new file mode 100644
index 0000000..ff6ddd1
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega164p/words/no-wdt.asm
@@ -0,0 +1,34 @@
+; ( -- )
+; MCU
+; disable watch dog timer at runtime
+VE_NOWDT:
+ .dw $ff04
+ .db "-wdt"
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOWDT
+XT_NOWDT:
+ .dw PFA_NOWDT
+PFA_NOWDT:
+
+ in temp1,SREG
+ push temp1
+ ; Turn always off global interrupt.
+ cli
+ ; Reset Watchdog Timer
+ wdr
+ ; Clear WDRF in MCUSR
+ in temp1, MCUSR
+ andi temp1, (0xff & (0<<WDRF))
+ out MCUSR, temp1
+ ; Write logical one to WDCE and WDE
+ ; Keep old prescaler setting to prevent unintentional time-out
+ in_ temp1, WDTCSR
+ ori temp1, (1<<WDCE) | (1<<WDE)
+ out_ WDTCSR, temp1
+ ; Turn off WDT
+ ldi temp1, (0<<WDE)
+ out_ WDTCSR, temp1
+ ; restore status register
+ pop temp1
+ out SREG,temp1
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega164p/words/sleep.asm b/amforth-6.5/avr8/devices/atmega164p/words/sleep.asm
new file mode 100644
index 0000000..256249c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega164p/words/sleep.asm
@@ -0,0 +1,19 @@
+; ( mode -- )
+; MCU
+; put the controller into the specified sleep mode
+VE_SLEEP:
+ .dw $ff05
+ .db "sleep", 0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_SLEEP
+XT_SLEEP:
+ .dw PFA_SLEEP
+PFA_SLEEP:
+ andi tosl, 7 ; leave only legal mode bits
+ lsl tosl ; move to correct location (bits 3-1)
+ ori tosl, 1 ; set the SE bit
+ out_ SMCR, tosl ; set the sleep config
+ sleep ; nighty-night
+ out_ SMCR, zerol ; 0 protects against accidental sleeps
+ loadtos ; pop argument from stack
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega164pa/atmega164pa.frt b/amforth-6.5/avr8/devices/atmega164pa/atmega164pa.frt
new file mode 100644
index 0000000..f1b72e3
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega164pa/atmega164pa.frt
@@ -0,0 +1,347 @@
+\ Partname: ATmega164PA
+\ generated automatically
+
+\ ANALOG_COMPARATOR
+&123 constant ADCSRB \ ADC Control and Status Register B
+ $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer Enable
+&80 constant ACSR \ Analog Comparator Control And Status Register
+ $80 constant ACSR_ACD \ Analog Comparator Disable
+ $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
+ $20 constant ACSR_ACO \ Analog Compare Output
+ $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
+ $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
+ $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
+ $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
+&127 constant DIDR1 \ Digital Input Disable Register 1
+ $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
+ $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
+\ USART0
+&198 constant UDR0 \ USART I/O Data Register
+&192 constant UCSR0A \ USART Control and Status Register A
+ $80 constant UCSR0A_RXC0 \ USART Receive Complete
+ $40 constant UCSR0A_TXC0 \ USART Transmitt Complete
+ $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
+ $10 constant UCSR0A_FE0 \ Framing Error
+ $08 constant UCSR0A_DOR0 \ Data overRun
+ $04 constant UCSR0A_UPE0 \ Parity Error
+ $02 constant UCSR0A_U2X0 \ Double the USART transmission speed
+ $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
+&193 constant UCSR0B \ USART Control and Status Register B
+ $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
+ $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
+ $20 constant UCSR0B_UDRIE0 \ USART Data register Empty Interrupt Enable
+ $10 constant UCSR0B_RXEN0 \ Receiver Enable
+ $08 constant UCSR0B_TXEN0 \ Transmitter Enable
+ $04 constant UCSR0B_UCSZ02 \ Character Size
+ $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
+ $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
+&194 constant UCSR0C \ USART Control and Status Register C
+ $C0 constant UCSR0C_UMSEL0 \ USART Mode Select
+ $30 constant UCSR0C_UPM0 \ Parity Mode Bits
+ $08 constant UCSR0C_USBS0 \ Stop Bit Select
+ $06 constant UCSR0C_UCSZ0 \ Character Size
+ $01 constant UCSR0C_UCPOL0 \ Clock Polarity
+&196 constant UBRR0 \ USART Baud Rate Register Bytes
+\ PORTA
+&34 constant PORTA \ Port A Data Register
+&33 constant DDRA \ Port A Data Direction Register
+&32 constant PINA \ Port A Input Pins
+\ PORTB
+&37 constant PORTB \ Port B Data Register
+&36 constant DDRB \ Port B Data Direction Register
+&35 constant PINB \ Port B Input Pins
+\ PORTC
+&40 constant PORTC \ Port C Data Register
+&39 constant DDRC \ Port C Data Direction Register
+&38 constant PINC \ Port C Input Pins
+\ PORTD
+&43 constant PORTD \ Port D Data Register
+&42 constant DDRD \ Port D Data Direction Register
+&41 constant PIND \ Port D Input Pins
+\ TIMER_COUNTER_0
+&72 constant OCR0B \ Timer/Counter0 Output Compare Register
+&71 constant OCR0A \ Timer/Counter0 Output Compare Register
+&70 constant TCNT0 \ Timer/Counter0
+&69 constant TCCR0B \ Timer/Counter Control Register B
+ $80 constant TCCR0B_FOC0A \ Force Output Compare A
+ $40 constant TCCR0B_FOC0B \ Force Output Compare B
+ $08 constant TCCR0B_WGM02 \
+ $07 constant TCCR0B_CS0 \ Clock Select
+&68 constant TCCR0A \ Timer/Counter Control Register A
+ $C0 constant TCCR0A_COM0A \ Compare Output Mode, Phase Correct PWM Mode
+ $30 constant TCCR0A_COM0B \ Compare Output Mode, Fast PWm
+ $03 constant TCCR0A_WGM0 \ Waveform Generation Mode
+&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
+ $04 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare Match B Interrupt Enable
+ $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match A Interrupt Enable
+ $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
+&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
+ $04 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare Flag 0B
+ $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0A
+ $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
+&67 constant GTCCR \ General Timer/Counter Control Register
+ $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
+ $01 constant GTCCR_PSRSYNC \ Prescaler Reset Timer/Counter1 and Timer/Counter0
+\ TIMER_COUNTER_2
+&112 constant TIMSK2 \ Timer/Counter Interrupt Mask register
+ $04 constant TIMSK2_OCIE2B \ Timer/Counter2 Output Compare Match B Interrupt Enable
+ $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match A Interrupt Enable
+ $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
+&55 constant TIFR2 \ Timer/Counter Interrupt Flag Register
+ $04 constant TIFR2_OCF2B \ Output Compare Flag 2B
+ $02 constant TIFR2_OCF2A \ Output Compare Flag 2A
+ $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
+&176 constant TCCR2A \ Timer/Counter2 Control Register A
+ $C0 constant TCCR2A_COM2A \ Compare Output Mode bits
+ $30 constant TCCR2A_COM2B \ Compare Output Mode bits
+ $03 constant TCCR2A_WGM2 \ Waveform Genration Mode
+&177 constant TCCR2B \ Timer/Counter2 Control Register B
+ $80 constant TCCR2B_FOC2A \ Force Output Compare A
+ $40 constant TCCR2B_FOC2B \ Force Output Compare B
+ $08 constant TCCR2B_WGM22 \ Waveform Generation Mode
+ $07 constant TCCR2B_CS2 \ Clock Select bits
+&178 constant TCNT2 \ Timer/Counter2
+&180 constant OCR2B \ Timer/Counter2 Output Compare Register B
+&179 constant OCR2A \ Timer/Counter2 Output Compare Register A
+&182 constant ASSR \ Asynchronous Status Register
+ $40 constant ASSR_EXCLK \ Enable External Clock Input
+ $20 constant ASSR_AS2 \ Asynchronous Timer/Counter2
+ $10 constant ASSR_TCN2UB \ Timer/Counter2 Update Busy
+ $08 constant ASSR_OCR2AUB \ Output Compare Register2 Update Busy
+ $04 constant ASSR_OCR2BUB \ Output Compare Register 2 Update Busy
+ $02 constant ASSR_TCR2AUB \ Timer/Counter Control Register2 Update Busy
+ $01 constant ASSR_TCR2BUB \ Timer/Counter Control Register2 Update Busy
+\ WATCHDOG
+&96 constant WDTCSR \ Watchdog Timer Control Register
+ $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Flag
+ $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Enable
+ $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
+ $10 constant WDTCSR_WDCE \ Watchdog Change Enable
+ $08 constant WDTCSR_WDE \ Watch Dog Enable
+\ JTAG
+&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
+&85 constant MCUCR \ MCU Control Register
+ $80 constant MCUCR_JTD \ JTAG Interface Disable
+&84 constant MCUSR \ MCU Status Register
+ $10 constant MCUSR_JTRF \ JTAG Reset Flag
+\ BOOT_LOAD
+&87 constant SPMCSR \ Store Program Memory Control Register
+ $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
+ $20 constant SPMCSR_SIGRD \ Signature Row Read
+ $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
+ $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
+ $04 constant SPMCSR_PGWRT \ Page Write
+ $02 constant SPMCSR_PGERS \ Page Erase
+ $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
+\ EXTERNAL_INTERRUPT
+&105 constant EICRA \ External Interrupt Control Register A
+ $30 constant EICRA_ISC2 \ External Interrupt Sense Control Bit
+ $0C constant EICRA_ISC1 \ External Interrupt Sense Control Bit
+ $03 constant EICRA_ISC0 \ External Interrupt Sense Control Bit
+&61 constant EIMSK \ External Interrupt Mask Register
+ $07 constant EIMSK_INT \ External Interrupt Request 2 Enable
+&60 constant EIFR \ External Interrupt Flag Register
+ $07 constant EIFR_INTF \ External Interrupt Flags
+&115 constant PCMSK3 \ Pin Change Mask Register 3
+ $FF constant PCMSK3_PCINT \ Pin Change Enable Masks
+&109 constant PCMSK2 \ Pin Change Mask Register 2
+ $FF constant PCMSK2_PCINT \ Pin Change Enable Masks
+&108 constant PCMSK1 \ Pin Change Mask Register 1
+ $FF constant PCMSK1_PCINT \ Pin Change Enable Masks
+&107 constant PCMSK0 \ Pin Change Mask Register 0
+ $FF constant PCMSK0_PCINT \ Pin Change Enable Masks
+&59 constant PCIFR \ Pin Change Interrupt Flag Register
+ $0F constant PCIFR_PCIF \ Pin Change Interrupt Flags
+&104 constant PCICR \ Pin Change Interrupt Control Register
+ $0F constant PCICR_PCIE \ Pin Change Interrupt Enables
+\ AD_CONVERTER
+&124 constant ADMUX \ The ADC multiplexer Selection Register
+ $C0 constant ADMUX_REFS \ Reference Selection Bits
+ $20 constant ADMUX_ADLAR \ Left Adjust Result
+ $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
+&120 constant ADC \ ADC Data Register Bytes
+&122 constant ADCSRA \ The ADC Control and Status register A
+ $80 constant ADCSRA_ADEN \ ADC Enable
+ $40 constant ADCSRA_ADSC \ ADC Start Conversion
+ $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
+ $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
+ $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
+ $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
+&126 constant DIDR0 \ Digital Input Disable Register
+ $80 constant DIDR0_ADC7D \
+ $40 constant DIDR0_ADC6D \
+ $20 constant DIDR0_ADC5D \
+ $10 constant DIDR0_ADC4D \
+ $08 constant DIDR0_ADC3D \
+ $04 constant DIDR0_ADC2D \
+ $02 constant DIDR0_ADC1D \
+ $01 constant DIDR0_ADC0D \
+\ TIMER_COUNTER_1
+&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
+ $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
+ $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
+ $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
+ $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
+&54 constant TIFR1 \ Timer/Counter Interrupt Flag register
+ $20 constant TIFR1_ICF1 \ Timer/Counter1 Input Capture Flag
+ $04 constant TIFR1_OCF1B \ Timer/Counter1 Output Compare B Match Flag
+ $02 constant TIFR1_OCF1A \ Timer/Counter1 Output Compare A Match Flag
+ $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
+&128 constant TCCR1A \ Timer/Counter1 Control Register A
+ $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
+ $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
+ $03 constant TCCR1A_WGM1 \ Pulse Width Modulator Select Bits
+&129 constant TCCR1B \ Timer/Counter1 Control Register B
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ $18 constant TCCR1B_WGM1 \ Waveform Generation Mode Bits
+ $07 constant TCCR1B_CS1 \ Clock Select1 bits
+&130 constant TCCR1C \ Timer/Counter1 Control Register C
+ $80 constant TCCR1C_FOC1A \ Force Output Compare for Channel A
+ $40 constant TCCR1C_FOC1B \ Force Output Compare for Channel B
+&132 constant TCNT1 \ Timer/Counter1 Bytes
+&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
+&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
+&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
+\ EEPROM
+&65 constant EEAR \ EEPROM Address Register Low Bytes
+&64 constant EEDR \ EEPROM Data Register
+&63 constant EECR \ EEPROM Control Register
+ $30 constant EECR_EEPM \ EEPROM Programming Mode Bits
+ $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
+ $04 constant EECR_EEMPE \ EEPROM Master Write Enable
+ $02 constant EECR_EEPE \ EEPROM Write Enable
+ $01 constant EECR_EERE \ EEPROM Read Enable
+\ SPI
+&78 constant SPDR0 \ SPI Data Register
+&77 constant SPSR0 \ SPI Status Register
+ $80 constant SPSR0_SPIF0 \ SPI Interrupt Flag
+ $40 constant SPSR0_WCOL0 \ Write Collision Flag
+ $01 constant SPSR0_SPI2X0 \ Double SPI Speed Bit
+&76 constant SPCR0 \ SPI Control Register
+ $80 constant SPCR0_SPIE0 \ SPI Interrupt Enable
+ $40 constant SPCR0_SPE0 \ SPI Enable
+ $20 constant SPCR0_DORD0 \ Data Order
+ $10 constant SPCR0_MSTR0 \ Master/Slave Select
+ $08 constant SPCR0_CPOL0 \ Clock polarity
+ $04 constant SPCR0_CPHA0 \ Clock Phase
+ $02 constant SPCR0_SPR10 \ SPI Clock Rate Select 1
+ $01 constant SPCR0_SPR00 \ SPI Clock Rate Select 0
+\ TWI
+&189 constant TWAMR \ TWI (Slave) Address Mask Register
+ $FE constant TWAMR_TWAM \
+&184 constant TWBR \ TWI Bit Rate register
+&188 constant TWCR \ TWI Control Register
+ $80 constant TWCR_TWINT \ TWI Interrupt Flag
+ $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
+ $20 constant TWCR_TWSTA \ TWI Start Condition Bit
+ $10 constant TWCR_TWSTO \ TWI Stop Condition Bit
+ $08 constant TWCR_TWWC \ TWI Write Collition Flag
+ $04 constant TWCR_TWEN \ TWI Enable Bit
+ $01 constant TWCR_TWIE \ TWI Interrupt Enable
+&185 constant TWSR \ TWI Status Register
+ $F8 constant TWSR_TWS \ TWI Status
+ $03 constant TWSR_TWPS \ TWI Prescaler
+&187 constant TWDR \ TWI Data register
+&186 constant TWAR \ TWI (Slave) Address register
+ $FE constant TWAR_TWA \ TWI (Slave) Address register Bits
+ $01 constant TWAR_TWGCE \ TWI General Call Recognition Enable Bit
+\ USART1
+&206 constant UDR1 \ USART I/O Data Register
+&200 constant UCSR1A \ USART Control and Status Register A
+ $80 constant UCSR1A_RXC1 \ USART Receive Complete
+ $40 constant UCSR1A_TXC1 \ USART Transmitt Complete
+ $20 constant UCSR1A_UDRE1 \ USART Data Register Empty
+ $10 constant UCSR1A_FE1 \ Framing Error
+ $08 constant UCSR1A_DOR1 \ Data overRun
+ $04 constant UCSR1A_UPE1 \ Parity Error
+ $02 constant UCSR1A_U2X1 \ Double the USART transmission speed
+ $01 constant UCSR1A_MPCM1 \ Multi-processor Communication Mode
+&201 constant UCSR1B \ USART Control and Status Register B
+ $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable
+ $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable
+ $20 constant UCSR1B_UDRIE1 \ USART Data register Empty Interrupt Enable
+ $10 constant UCSR1B_RXEN1 \ Receiver Enable
+ $08 constant UCSR1B_TXEN1 \ Transmitter Enable
+ $04 constant UCSR1B_UCSZ12 \ Character Size
+ $02 constant UCSR1B_RXB81 \ Receive Data Bit 8
+ $01 constant UCSR1B_TXB81 \ Transmit Data Bit 8
+&202 constant UCSR1C \ USART Control and Status Register C
+ $C0 constant UCSR1C_UMSEL1 \ USART Mode Select
+ $30 constant UCSR1C_UPM1 \ Parity Mode Bits
+ $08 constant UCSR1C_USBS1 \ Stop Bit Select
+ $06 constant UCSR1C_UCSZ1 \ Character Size
+ $01 constant UCSR1C_UCPOL1 \ Clock Polarity
+&204 constant UBRR1 \ USART Baud Rate Register Bytes
+\ CPU
+&95 constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ $08 constant SREG_V \ Two's Complement Overflow Flag
+ $04 constant SREG_N \ Negative Flag
+ $02 constant SREG_Z \ Zero Flag
+ $01 constant SREG_C \ Carry Flag
+&93 constant SP \ Stack Pointer
+&102 constant OSCCAL \ Oscillator Calibration Value
+&97 constant CLKPR \
+ $80 constant CLKPR_CLKPCE \
+ $0F constant CLKPR_CLKPS \
+&83 constant SMCR \ Sleep Mode Control Register
+ $0E constant SMCR_SM \ Sleep Mode Select bits
+ $01 constant SMCR_SE \ Sleep Enable
+&75 constant GPIOR2 \ General Purpose IO Register 2
+ $FF constant GPIOR2_GPIOR \ General Purpose IO Register 2 bis
+&74 constant GPIOR1 \ General Purpose IO Register 1
+ $FF constant GPIOR1_GPIOR \ General Purpose IO Register 1 bis
+&62 constant GPIOR0 \ General Purpose IO Register 0
+ $80 constant GPIOR0_GPIOR07 \ General Purpose IO Register 0 bit 7
+ $40 constant GPIOR0_GPIOR06 \ General Purpose IO Register 0 bit 6
+ $20 constant GPIOR0_GPIOR05 \ General Purpose IO Register 0 bit 5
+ $10 constant GPIOR0_GPIOR04 \ General Purpose IO Register 0 bit 4
+ $08 constant GPIOR0_GPIOR03 \ General Purpose IO Register 0 bit 3
+ $04 constant GPIOR0_GPIOR02 \ General Purpose IO Register 0 bit 2
+ $02 constant GPIOR0_GPIOR01 \ General Purpose IO Register 0 bit 1
+ $01 constant GPIOR0_GPIOR00 \ General Purpose IO Register 0 bit 0
+&100 constant PRR0 \ Power Reduction Register0
+ $80 constant PRR0_PRTWI \ Power Reduction TWI
+ $40 constant PRR0_PRTIM2 \ Power Reduction Timer/Counter2
+ $20 constant PRR0_PRTIM0 \ Power Reduction Timer/Counter0
+ $12 constant PRR0_PRUSART \ Power Reduction USARTs
+ $08 constant PRR0_PRTIM1 \ Power Reduction Timer/Counter1
+ $04 constant PRR0_PRSPI \ Power Reduction Serial Peripheral Interface
+ $01 constant PRR0_PRADC \ Power Reduction ADC
+
+\ Interrupts
+&2 constant INT0Addr \ External Interrupt Request 0
+&4 constant INT1Addr \ External Interrupt Request 1
+&6 constant INT2Addr \ External Interrupt Request 2
+&8 constant PCINT0Addr \ Pin Change Interrupt Request 0
+&10 constant PCINT1Addr \ Pin Change Interrupt Request 1
+&12 constant PCINT2Addr \ Pin Change Interrupt Request 2
+&14 constant PCINT3Addr \ Pin Change Interrupt Request 3
+&16 constant WDTAddr \ Watchdog Time-out Interrupt
+&18 constant TIMER2_COMPAAddr \ Timer/Counter2 Compare Match A
+&20 constant TIMER2_COMPBAddr \ Timer/Counter2 Compare Match B
+&22 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
+&24 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+&26 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
+&28 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
+&30 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+&32 constant TIMER0_COMPAAddr \ Timer/Counter0 Compare Match A
+&34 constant TIMER0_COMPBAddr \ Timer/Counter0 Compare Match B
+&36 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
+&38 constant SPI__STCAddr \ SPI Serial Transfer Complete
+&40 constant USART0__RXAddr \ USART0, Rx Complete
+&42 constant USART0__UDREAddr \ USART0 Data register Empty
+&44 constant USART0__TXAddr \ USART0, Tx Complete
+&46 constant ANALOG_COMPAddr \ Analog Comparator
+&48 constant ADCAddr \ ADC Conversion Complete
+&50 constant EE_READYAddr \ EEPROM Ready
+&52 constant TWIAddr \ 2-wire Serial Interface
+&54 constant SPM_READYAddr \ Store Program Memory Read
+&56 constant USART1_RXAddr \ USART1 RX complete
+&58 constant USART1_UDREAddr \ USART1 Data Register Empty
+&60 constant USART1_TXAddr \ USART1 TX complete
diff --git a/amforth-6.5/avr8/devices/atmega164pa/device.asm b/amforth-6.5/avr8/devices/atmega164pa/device.asm
new file mode 100644
index 0000000..95ce3e5
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega164pa/device.asm
@@ -0,0 +1,120 @@
+; Partname: ATmega164PA
+; generated automatically, do not edit
+
+.nolist
+ .include "m164PAdef.inc"
+.list
+
+.equ ramstart = 256
+.equ CELLSIZE = 2
+.macro readflashcell
+ lsl zl
+ rol zh
+ lpm @0, Z+
+ lpm @1, Z+
+.endmacro
+.macro writeflashcell
+ lsl zl
+ rol zh
+.endmacro
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_USART0 = 0
+.set WANT_PORTA = 0
+.set WANT_PORTB = 0
+.set WANT_PORTC = 0
+.set WANT_PORTD = 0
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_TIMER_COUNTER_2 = 0
+.set WANT_WATCHDOG = 0
+.set WANT_JTAG = 0
+.set WANT_BOOT_LOAD = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_AD_CONVERTER = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_EEPROM = 0
+.set WANT_SPI = 0
+.set WANT_TWI = 0
+.set WANT_USART1 = 0
+.set WANT_CPU = 0
+.equ intvecsize = 2 ; please verify; flash size: 16384 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.org 2
+ rcall isr ; External Interrupt Request 0
+.org 4
+ rcall isr ; External Interrupt Request 1
+.org 6
+ rcall isr ; External Interrupt Request 2
+.org 8
+ rcall isr ; Pin Change Interrupt Request 0
+.org 10
+ rcall isr ; Pin Change Interrupt Request 1
+.org 12
+ rcall isr ; Pin Change Interrupt Request 2
+.org 14
+ rcall isr ; Pin Change Interrupt Request 3
+.org 16
+ rcall isr ; Watchdog Time-out Interrupt
+.org 18
+ rcall isr ; Timer/Counter2 Compare Match A
+.org 20
+ rcall isr ; Timer/Counter2 Compare Match B
+.org 22
+ rcall isr ; Timer/Counter2 Overflow
+.org 24
+ rcall isr ; Timer/Counter1 Capture Event
+.org 26
+ rcall isr ; Timer/Counter1 Compare Match A
+.org 28
+ rcall isr ; Timer/Counter1 Compare Match B
+.org 30
+ rcall isr ; Timer/Counter1 Overflow
+.org 32
+ rcall isr ; Timer/Counter0 Compare Match A
+.org 34
+ rcall isr ; Timer/Counter0 Compare Match B
+.org 36
+ rcall isr ; Timer/Counter0 Overflow
+.org 38
+ rcall isr ; SPI Serial Transfer Complete
+.org 40
+ rcall isr ; USART0, Rx Complete
+.org 42
+ rcall isr ; USART0 Data register Empty
+.org 44
+ rcall isr ; USART0, Tx Complete
+.org 46
+ rcall isr ; Analog Comparator
+.org 48
+ rcall isr ; ADC Conversion Complete
+.org 50
+ rcall isr ; EEPROM Ready
+.org 52
+ rcall isr ; 2-wire Serial Interface
+.org 54
+ rcall isr ; Store Program Memory Read
+.org 56
+ rcall isr ; USART1 RX complete
+.org 58
+ rcall isr ; USART1 Data Register Empty
+.org 60
+ rcall isr ; USART1 TX complete
+.equ INTVECTORS = 31
+.nooverlap
+
+; compatability layer (maybe empty)
+
+; controller data area, environment query mcu-info
+mcu_info:
+mcu_ramsize:
+ .dw 1024
+mcu_eepromsize:
+ .dw 512
+mcu_maxdp:
+ .dw 14336
+mcu_numints:
+ .dw 31
+mcu_name:
+ .dw 11
+ .db "ATmega164PA",0
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega164pa/device.inc b/amforth-6.5/avr8/devices/atmega164pa/device.inc
new file mode 100644
index 0000000..2c39861
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega164pa/device.inc
@@ -0,0 +1,1128 @@
+; Partname: ATmega164PA
+; generated automatically, no not edit
+
+.if WANT_ANALOG_COMPARATOR == 1
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Control and Status Register B
+VE_ADCSRB:
+ .dw $ff06
+ .db "ADCSRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRB
+XT_ADCSRB:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRB:
+ .dw 123
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Control And Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw 80
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 1
+VE_DIDR1:
+ .dw $ff05
+ .db "DIDR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR1
+XT_DIDR1:
+ .dw PFA_DOVARIABLE
+PFA_DIDR1:
+ .dw 127
+
+.endif
+.if WANT_USART0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR0:
+ .dw $ff04
+ .db "UDR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR0
+XT_UDR0:
+ .dw PFA_DOVARIABLE
+PFA_UDR0:
+ .dw 198
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR0A:
+ .dw $ff06
+ .db "UCSR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0A
+XT_UCSR0A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0A:
+ .dw 192
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR0B:
+ .dw $ff06
+ .db "UCSR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0B
+XT_UCSR0B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0B:
+ .dw 193
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR0C:
+ .dw $ff06
+ .db "UCSR0C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0C
+XT_UCSR0C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0C:
+ .dw 194
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Bytes
+VE_UBRR0:
+ .dw $ff05
+ .db "UBRR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR0
+XT_UBRR0:
+ .dw PFA_DOVARIABLE
+PFA_UBRR0:
+ .dw 196
+
+.endif
+.if WANT_PORTA == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Register
+VE_PORTA:
+ .dw $ff05
+ .db "PORTA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTA
+XT_PORTA:
+ .dw PFA_DOVARIABLE
+PFA_PORTA:
+ .dw 34
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Direction Register
+VE_DDRA:
+ .dw $ff04
+ .db "DDRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRA
+XT_DDRA:
+ .dw PFA_DOVARIABLE
+PFA_DDRA:
+ .dw 33
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Input Pins
+VE_PINA:
+ .dw $ff04
+ .db "PINA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINA
+XT_PINA:
+ .dw PFA_DOVARIABLE
+PFA_PINA:
+ .dw 32
+
+.endif
+.if WANT_PORTB == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw 37
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw 36
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw 35
+
+.endif
+.if WANT_PORTC == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Register
+VE_PORTC:
+ .dw $ff05
+ .db "PORTC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTC
+XT_PORTC:
+ .dw PFA_DOVARIABLE
+PFA_PORTC:
+ .dw 40
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Direction Register
+VE_DDRC:
+ .dw $ff04
+ .db "DDRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRC
+XT_DDRC:
+ .dw PFA_DOVARIABLE
+PFA_DDRC:
+ .dw 39
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Input Pins
+VE_PINC:
+ .dw $ff04
+ .db "PINC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINC
+XT_PINC:
+ .dw PFA_DOVARIABLE
+PFA_PINC:
+ .dw 38
+
+.endif
+.if WANT_PORTD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw 43
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw 42
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw 41
+
+.endif
+.if WANT_TIMER_COUNTER_0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0B:
+ .dw $ff05
+ .db "OCR0B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0B
+XT_OCR0B:
+ .dw PFA_DOVARIABLE
+PFA_OCR0B:
+ .dw 72
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0A:
+ .dw $ff05
+ .db "OCR0A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0A
+XT_OCR0A:
+ .dw PFA_DOVARIABLE
+PFA_OCR0A:
+ .dw 71
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw 70
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register B
+VE_TCCR0B:
+ .dw $ff06
+ .db "TCCR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0B
+XT_TCCR0B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0B:
+ .dw 69
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register A
+VE_TCCR0A:
+ .dw $ff06
+ .db "TCCR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0A
+XT_TCCR0A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0A:
+ .dw 68
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Mask Register
+VE_TIMSK0:
+ .dw $ff06
+ .db "TIMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK0
+XT_TIMSK0:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK0:
+ .dw 110
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Flag register
+VE_TIFR0:
+ .dw $ff05
+ .db "TIFR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR0
+XT_TIFR0:
+ .dw PFA_DOVARIABLE
+PFA_TIFR0:
+ .dw 53
+; ( -- addr ) System Constant
+; R( -- )
+; General Timer/Counter Control Register
+VE_GTCCR:
+ .dw $ff05
+ .db "GTCCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GTCCR
+XT_GTCCR:
+ .dw PFA_DOVARIABLE
+PFA_GTCCR:
+ .dw 67
+
+.endif
+.if WANT_TIMER_COUNTER_2 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Mask register
+VE_TIMSK2:
+ .dw $ff06
+ .db "TIMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK2
+XT_TIMSK2:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK2:
+ .dw 112
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Flag Register
+VE_TIFR2:
+ .dw $ff05
+ .db "TIFR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR2
+XT_TIFR2:
+ .dw PFA_DOVARIABLE
+PFA_TIFR2:
+ .dw 55
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register A
+VE_TCCR2A:
+ .dw $ff06
+ .db "TCCR2A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2A
+XT_TCCR2A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2A:
+ .dw 176
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register B
+VE_TCCR2B:
+ .dw $ff06
+ .db "TCCR2B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2B
+XT_TCCR2B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2B:
+ .dw 177
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2
+VE_TCNT2:
+ .dw $ff05
+ .db "TCNT2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT2
+XT_TCNT2:
+ .dw PFA_DOVARIABLE
+PFA_TCNT2:
+ .dw 178
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register B
+VE_OCR2B:
+ .dw $ff05
+ .db "OCR2B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2B
+XT_OCR2B:
+ .dw PFA_DOVARIABLE
+PFA_OCR2B:
+ .dw 180
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register A
+VE_OCR2A:
+ .dw $ff05
+ .db "OCR2A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2A
+XT_OCR2A:
+ .dw PFA_DOVARIABLE
+PFA_OCR2A:
+ .dw 179
+; ( -- addr ) System Constant
+; R( -- )
+; Asynchronous Status Register
+VE_ASSR:
+ .dw $ff04
+ .db "ASSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ASSR
+XT_ASSR:
+ .dw PFA_DOVARIABLE
+PFA_ASSR:
+ .dw 182
+
+.endif
+.if WANT_WATCHDOG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCSR:
+ .dw $ff06
+ .db "WDTCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCSR
+XT_WDTCSR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCSR:
+ .dw 96
+
+.endif
+.if WANT_JTAG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; On-Chip Debug Related Register in I/O Memory
+VE_OCDR:
+ .dw $ff04
+ .db "OCDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCDR
+XT_OCDR:
+ .dw PFA_DOVARIABLE
+PFA_OCDR:
+ .dw 81
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw 85
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Status Register
+VE_MCUSR:
+ .dw $ff05
+ .db "MCUSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUSR
+XT_MCUSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUSR:
+ .dw 84
+
+.endif
+.if WANT_BOOT_LOAD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control Register
+VE_SPMCSR:
+ .dw $ff06
+ .db "SPMCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCSR
+XT_SPMCSR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCSR:
+ .dw 87
+
+.endif
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register A
+VE_EICRA:
+ .dw $ff05
+ .db "EICRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRA
+XT_EICRA:
+ .dw PFA_DOVARIABLE
+PFA_EICRA:
+ .dw 105
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Mask Register
+VE_EIMSK:
+ .dw $ff05
+ .db "EIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIMSK
+XT_EIMSK:
+ .dw PFA_DOVARIABLE
+PFA_EIMSK:
+ .dw 61
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Flag Register
+VE_EIFR:
+ .dw $ff04
+ .db "EIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIFR
+XT_EIFR:
+ .dw PFA_DOVARIABLE
+PFA_EIFR:
+ .dw 60
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 3
+VE_PCMSK3:
+ .dw $ff06
+ .db "PCMSK3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK3
+XT_PCMSK3:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK3:
+ .dw 115
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 2
+VE_PCMSK2:
+ .dw $ff06
+ .db "PCMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK2
+XT_PCMSK2:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK2:
+ .dw 109
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 1
+VE_PCMSK1:
+ .dw $ff06
+ .db "PCMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK1
+XT_PCMSK1:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK1:
+ .dw 108
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 0
+VE_PCMSK0:
+ .dw $ff06
+ .db "PCMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK0
+XT_PCMSK0:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK0:
+ .dw 107
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Interrupt Flag Register
+VE_PCIFR:
+ .dw $ff05
+ .db "PCIFR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCIFR
+XT_PCIFR:
+ .dw PFA_DOVARIABLE
+PFA_PCIFR:
+ .dw 59
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Interrupt Control Register
+VE_PCICR:
+ .dw $ff05
+ .db "PCICR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCICR
+XT_PCICR:
+ .dw PFA_DOVARIABLE
+PFA_PCICR:
+ .dw 104
+
+.endif
+.if WANT_AD_CONVERTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC multiplexer Selection Register
+VE_ADMUX:
+ .dw $ff05
+ .db "ADMUX",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADMUX
+XT_ADMUX:
+ .dw PFA_DOVARIABLE
+PFA_ADMUX:
+ .dw 124
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register Bytes
+VE_ADC:
+ .dw $ff03
+ .db "ADC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADC
+XT_ADC:
+ .dw PFA_DOVARIABLE
+PFA_ADC:
+ .dw 120
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register A
+VE_ADCSRA:
+ .dw $ff06
+ .db "ADCSRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRA
+XT_ADCSRA:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRA:
+ .dw 122
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register
+VE_DIDR0:
+ .dw $ff05
+ .db "DIDR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR0
+XT_DIDR0:
+ .dw PFA_DOVARIABLE
+PFA_DIDR0:
+ .dw 126
+
+.endif
+.if WANT_TIMER_COUNTER_1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Mask Register
+VE_TIMSK1:
+ .dw $ff06
+ .db "TIMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK1
+XT_TIMSK1:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK1:
+ .dw 111
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Flag register
+VE_TIFR1:
+ .dw $ff05
+ .db "TIFR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR1
+XT_TIFR1:
+ .dw PFA_DOVARIABLE
+PFA_TIFR1:
+ .dw 54
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw 128
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw 129
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register C
+VE_TCCR1C:
+ .dw $ff06
+ .db "TCCR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1C
+XT_TCCR1C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1C:
+ .dw 130
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Bytes
+VE_TCNT1:
+ .dw $ff05
+ .db "TCNT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1
+XT_TCNT1:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1:
+ .dw 132
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register A Bytes
+VE_OCR1A:
+ .dw $ff05
+ .db "OCR1A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1A
+XT_OCR1A:
+ .dw PFA_DOVARIABLE
+PFA_OCR1A:
+ .dw 136
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register B Bytes
+VE_OCR1B:
+ .dw $ff05
+ .db "OCR1B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1B
+XT_OCR1B:
+ .dw PFA_DOVARIABLE
+PFA_OCR1B:
+ .dw 138
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Bytes
+VE_ICR1:
+ .dw $ff04
+ .db "ICR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1
+XT_ICR1:
+ .dw PFA_DOVARIABLE
+PFA_ICR1:
+ .dw 134
+
+.endif
+.if WANT_EEPROM == 1
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Address Register Low Bytes
+VE_EEAR:
+ .dw $ff04
+ .db "EEAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEAR
+XT_EEAR:
+ .dw PFA_DOVARIABLE
+PFA_EEAR:
+ .dw 65
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw 64
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw 63
+
+.endif
+.if WANT_SPI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR0:
+ .dw $ff05
+ .db "SPDR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR0
+XT_SPDR0:
+ .dw PFA_DOVARIABLE
+PFA_SPDR0:
+ .dw 78
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR0:
+ .dw $ff05
+ .db "SPSR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR0
+XT_SPSR0:
+ .dw PFA_DOVARIABLE
+PFA_SPSR0:
+ .dw 77
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR0:
+ .dw $ff05
+ .db "SPCR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR0
+XT_SPCR0:
+ .dw PFA_DOVARIABLE
+PFA_SPCR0:
+ .dw 76
+
+.endif
+.if WANT_TWI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; TWI (Slave) Address Mask Register
+VE_TWAMR:
+ .dw $ff05
+ .db "TWAMR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWAMR
+XT_TWAMR:
+ .dw PFA_DOVARIABLE
+PFA_TWAMR:
+ .dw 189
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Bit Rate register
+VE_TWBR:
+ .dw $ff04
+ .db "TWBR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWBR
+XT_TWBR:
+ .dw PFA_DOVARIABLE
+PFA_TWBR:
+ .dw 184
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Control Register
+VE_TWCR:
+ .dw $ff04
+ .db "TWCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWCR
+XT_TWCR:
+ .dw PFA_DOVARIABLE
+PFA_TWCR:
+ .dw 188
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Status Register
+VE_TWSR:
+ .dw $ff04
+ .db "TWSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWSR
+XT_TWSR:
+ .dw PFA_DOVARIABLE
+PFA_TWSR:
+ .dw 185
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Data register
+VE_TWDR:
+ .dw $ff04
+ .db "TWDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWDR
+XT_TWDR:
+ .dw PFA_DOVARIABLE
+PFA_TWDR:
+ .dw 187
+; ( -- addr ) System Constant
+; R( -- )
+; TWI (Slave) Address register
+VE_TWAR:
+ .dw $ff04
+ .db "TWAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWAR
+XT_TWAR:
+ .dw PFA_DOVARIABLE
+PFA_TWAR:
+ .dw 186
+
+.endif
+.if WANT_USART1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR1:
+ .dw $ff04
+ .db "UDR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR1
+XT_UDR1:
+ .dw PFA_DOVARIABLE
+PFA_UDR1:
+ .dw 206
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR1A:
+ .dw $ff06
+ .db "UCSR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1A
+XT_UCSR1A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1A:
+ .dw 200
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR1B:
+ .dw $ff06
+ .db "UCSR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1B
+XT_UCSR1B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1B:
+ .dw 201
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR1C:
+ .dw $ff06
+ .db "UCSR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1C
+XT_UCSR1C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1C:
+ .dw 202
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Bytes
+VE_UBRR1:
+ .dw $ff05
+ .db "UBRR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR1
+XT_UBRR1:
+ .dw PFA_DOVARIABLE
+PFA_UBRR1:
+ .dw 204
+
+.endif
+.if WANT_CPU == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw 95
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer
+VE_SP:
+ .dw $ff02
+ .db "SP"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SP
+XT_SP:
+ .dw PFA_DOVARIABLE
+PFA_SP:
+ .dw 93
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Calibration Value
+VE_OSCCAL:
+ .dw $ff06
+ .db "OSCCAL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSCCAL
+XT_OSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_OSCCAL:
+ .dw 102
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_CLKPR:
+ .dw $ff05
+ .db "CLKPR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKPR
+XT_CLKPR:
+ .dw PFA_DOVARIABLE
+PFA_CLKPR:
+ .dw 97
+; ( -- addr ) System Constant
+; R( -- )
+; Sleep Mode Control Register
+VE_SMCR:
+ .dw $ff04
+ .db "SMCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SMCR
+XT_SMCR:
+ .dw PFA_DOVARIABLE
+PFA_SMCR:
+ .dw 83
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 2
+VE_GPIOR2:
+ .dw $ff06
+ .db "GPIOR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR2
+XT_GPIOR2:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR2:
+ .dw 75
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 1
+VE_GPIOR1:
+ .dw $ff06
+ .db "GPIOR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR1
+XT_GPIOR1:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR1:
+ .dw 74
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 0
+VE_GPIOR0:
+ .dw $ff06
+ .db "GPIOR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR0
+XT_GPIOR0:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR0:
+ .dw 62
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register0
+VE_PRR0:
+ .dw $ff04
+ .db "PRR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR0
+XT_PRR0:
+ .dw PFA_DOVARIABLE
+PFA_PRR0:
+ .dw 100
+
+.endif
diff --git a/amforth-6.5/avr8/devices/atmega164pa/device.py b/amforth-6.5/avr8/devices/atmega164pa/device.py
new file mode 100644
index 0000000..5dd57e8
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega164pa/device.py
@@ -0,0 +1,389 @@
+# Generated Automatically
+
+# Partname ATmega164PA
+
+MCUREGS = {
+# Interrupt Vectors
+ 'INT0Addr' : '#2', # External Interrupt Request 0
+ 'INT1Addr' : '#4', # External Interrupt Request 1
+ 'INT2Addr' : '#6', # External Interrupt Request 2
+ 'PCINT0Addr' : '#8', # Pin Change Interrupt Request 0
+ 'PCINT1Addr' : '#10', # Pin Change Interrupt Request 1
+ 'PCINT2Addr' : '#12', # Pin Change Interrupt Request 2
+ 'PCINT3Addr' : '#14', # Pin Change Interrupt Request 3
+ 'WDTAddr' : '#16', # Watchdog Time-out Interrupt
+ 'TIMER2_COMPAAddr' : '#18', # Timer/Counter2 Compare Match A
+ 'TIMER2_COMPBAddr' : '#20', # Timer/Counter2 Compare Match B
+ 'TIMER2_OVFAddr' : '#22', # Timer/Counter2 Overflow
+ 'TIMER1_CAPTAddr' : '#24', # Timer/Counter1 Capture Event
+ 'TIMER1_COMPAAddr' : '#26', # Timer/Counter1 Compare Match A
+ 'TIMER1_COMPBAddr' : '#28', # Timer/Counter1 Compare Match B
+ 'TIMER1_OVFAddr' : '#30', # Timer/Counter1 Overflow
+ 'TIMER0_COMPAAddr' : '#32', # Timer/Counter0 Compare Match A
+ 'TIMER0_COMPBAddr' : '#34', # Timer/Counter0 Compare Match B
+ 'TIMER0_OVFAddr' : '#36', # Timer/Counter0 Overflow
+ 'SPI_STCAddr' : '#38', # SPI Serial Transfer Complete
+ 'USART0_RXAddr' : '#40', # USART0, Rx Complete
+ 'USART0_UDREAddr' : '#42', # USART0 Data register Empty
+ 'USART0_TXAddr' : '#44', # USART0, Tx Complete
+ 'ANALOG_COMPAddr' : '#46', # Analog Comparator
+ 'ADCAddr' : '#48', # ADC Conversion Complete
+ 'EE_READYAddr' : '#50', # EEPROM Ready
+ 'TWIAddr' : '#52', # 2-wire Serial Interface
+ 'SPM_READYAddr' : '#54', # Store Program Memory Read
+ 'USART1_RXAddr' : '#56', # USART1 RX complete
+ 'USART1_UDREAddr' : '#58', # USART1 Data Register Empty
+ 'USART1_TXAddr' : '#60', # USART1 TX complete
+
+# Module ANALOG_COMPARATOR
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
+ 'ACSR' : '$50', # Analog Comparator Control And
+ 'ACSR_ACD': '$80', # Analog Comparator Disable
+ 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
+ 'ACSR_ACO': '$20', # Analog Compare Output
+ 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
+ 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
+ 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
+ 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
+ 'DIDR1' : '$7f', # Digital Input Disable Register
+ 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
+ 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
+
+# Module USART0
+ 'UDR0' : '$c6', # USART I/O Data Register
+ 'UCSR0A' : '$c0', # USART Control and Status Regis
+ 'UCSR0A_RXC0': '$80', # USART Receive Complete
+ 'UCSR0A_TXC0': '$40', # USART Transmitt Complete
+ 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
+ 'UCSR0A_FE0': '$10', # Framing Error
+ 'UCSR0A_DOR0': '$8', # Data overRun
+ 'UCSR0A_UPE0': '$4', # Parity Error
+ 'UCSR0A_U2X0': '$2', # Double the USART transmission
+ 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
+ 'UCSR0B' : '$c1', # USART Control and Status Regis
+ 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
+ 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
+ 'UCSR0B_UDRIE0': '$20', # USART Data register Empty Inte
+ 'UCSR0B_RXEN0': '$10', # Receiver Enable
+ 'UCSR0B_TXEN0': '$8', # Transmitter Enable
+ 'UCSR0B_UCSZ02': '$4', # Character Size
+ 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
+ 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
+ 'UCSR0C' : '$c2', # USART Control and Status Regis
+ 'UCSR0C_UMSEL0': '$c0', # USART Mode Select
+ 'UCSR0C_UPM0': '$30', # Parity Mode Bits
+ 'UCSR0C_USBS0': '$8', # Stop Bit Select
+ 'UCSR0C_UCSZ0': '$6', # Character Size
+ 'UCSR0C_UCPOL0': '$1', # Clock Polarity
+ 'UBRR0' : '$c4', # USART Baud Rate Register Byte
+
+# Module PORTA
+ 'PORTA' : '$22', # Port A Data Register
+ 'DDRA' : '$21', # Port A Data Direction Register
+ 'PINA' : '$20', # Port A Input Pins
+
+# Module PORTB
+ 'PORTB' : '$25', # Port B Data Register
+ 'DDRB' : '$24', # Port B Data Direction Register
+ 'PINB' : '$23', # Port B Input Pins
+
+# Module PORTC
+ 'PORTC' : '$28', # Port C Data Register
+ 'DDRC' : '$27', # Port C Data Direction Register
+ 'PINC' : '$26', # Port C Input Pins
+
+# Module PORTD
+ 'PORTD' : '$2b', # Port D Data Register
+ 'DDRD' : '$2a', # Port D Data Direction Register
+ 'PIND' : '$29', # Port D Input Pins
+
+# Module TIMER_COUNTER_0
+ 'OCR0B' : '$48', # Timer/Counter0 Output Compare
+ 'OCR0A' : '$47', # Timer/Counter0 Output Compare
+ 'TCNT0' : '$46', # Timer/Counter0
+ 'TCCR0B' : '$45', # Timer/Counter Control Register
+ 'TCCR0B_FOC0A': '$80', # Force Output Compare A
+ 'TCCR0B_FOC0B': '$40', # Force Output Compare B
+ 'TCCR0B_WGM02': '$8', #
+ 'TCCR0B_CS0': '$7', # Clock Select
+ 'TCCR0A' : '$44', # Timer/Counter Control Registe
+ 'TCCR0A_COM0A': '$c0', # Compare Output Mode, Phase Cor
+ 'TCCR0A_COM0B': '$30', # Compare Output Mode, Fast PWm
+ 'TCCR0A_WGM0': '$3', # Waveform Generation Mode
+ 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
+ 'TIMSK0_OCIE0B': '$4', # Timer/Counter0 Output Compare
+ 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
+ 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
+ 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
+ 'TIFR0_OCF0B': '$4', # Timer/Counter0 Output Compare
+ 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
+ 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSRSYNC': '$1', # Prescaler Reset Timer/Counter1
+
+# Module TIMER_COUNTER_2
+ 'TIMSK2' : '$70', # Timer/Counter Interrupt Mask r
+ 'TIMSK2_OCIE2B': '$4', # Timer/Counter2 Output Compare
+ 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
+ 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
+ 'TIFR2' : '$37', # Timer/Counter Interrupt Flag R
+ 'TIFR2_OCF2B': '$4', # Output Compare Flag 2B
+ 'TIFR2_OCF2A': '$2', # Output Compare Flag 2A
+ 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
+ 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
+ 'TCCR2A_COM2A': '$c0', # Compare Output Mode bits
+ 'TCCR2A_COM2B': '$30', # Compare Output Mode bits
+ 'TCCR2A_WGM2': '$3', # Waveform Genration Mode
+ 'TCCR2B' : '$b1', # Timer/Counter2 Control Registe
+ 'TCCR2B_FOC2A': '$80', # Force Output Compare A
+ 'TCCR2B_FOC2B': '$40', # Force Output Compare B
+ 'TCCR2B_WGM22': '$8', # Waveform Generation Mode
+ 'TCCR2B_CS2': '$7', # Clock Select bits
+ 'TCNT2' : '$b2', # Timer/Counter2
+ 'OCR2B' : '$b4', # Timer/Counter2 Output Compare
+ 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
+ 'ASSR' : '$b6', # Asynchronous Status Register
+ 'ASSR_EXCLK': '$40', # Enable External Clock Input
+ 'ASSR_AS2': '$20', # Asynchronous Timer/Counter2
+ 'ASSR_TCN2UB': '$10', # Timer/Counter2 Update Busy
+ 'ASSR_OCR2AUB': '$8', # Output Compare Register2 Updat
+ 'ASSR_OCR2BUB': '$4', # Output Compare Register 2 Upda
+ 'ASSR_TCR2AUB': '$2', # Timer/Counter Control Register
+ 'ASSR_TCR2BUB': '$1', # Timer/Counter Control Register
+ 'GTCCR' : '$43', # General Timer Counter Control
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSRASY': '$2', # Prescaler Reset Timer/Counter2
+
+# Module WATCHDOG
+ 'WDTCSR' : '$60', # Watchdog Timer Control Registe
+ 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
+ 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
+ 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
+ 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
+ 'WDTCSR_WDE': '$8', # Watch Dog Enable
+
+# Module JTAG
+ 'OCDR' : '$51', # On-Chip Debug Related Register
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_JTD': '$80', # JTAG Interface Disable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+
+# Module BOOT_LOAD
+ 'SPMCSR' : '$57', # Store Program Memory Control R
+ 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
+ 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
+ 'SPMCSR_SIGRD': '$20', # Signature Row Read
+ 'SPMCSR_RWWSRE': '$10', # Read While Write section read
+ 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
+ 'SPMCSR_PGWRT': '$4', # Page Write
+ 'SPMCSR_PGERS': '$2', # Page Erase
+ 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
+
+# Module EXTERNAL_INTERRUPT
+ 'EICRA' : '$69', # External Interrupt Control Reg
+ 'EICRA_ISC2': '$30', # External Interrupt Sense Contr
+ 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
+ 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
+ 'EIMSK' : '$3d', # External Interrupt Mask Regist
+ 'EIMSK_INT': '$7', # External Interrupt Request 2 E
+ 'EIFR' : '$3c', # External Interrupt Flag Regist
+ 'EIFR_INTF': '$7', # External Interrupt Flags
+ 'PCMSK3' : '$73', # Pin Change Mask Register 3
+ 'PCMSK3_PCINT': '$ff', # Pin Change Enable Masks
+ 'PCMSK2' : '$6d', # Pin Change Mask Register 2
+ 'PCMSK2_PCINT': '$ff', # Pin Change Enable Masks
+ 'PCMSK1' : '$6c', # Pin Change Mask Register 1
+ 'PCMSK1_PCINT': '$ff', # Pin Change Enable Masks
+ 'PCMSK0' : '$6b', # Pin Change Mask Register 0
+ 'PCMSK0_PCINT': '$ff', # Pin Change Enable Masks
+ 'PCIFR' : '$3b', # Pin Change Interrupt Flag Regi
+ 'PCIFR_PCIF': '$f', # Pin Change Interrupt Flags
+ 'PCICR' : '$68', # Pin Change Interrupt Control R
+ 'PCICR_PCIE': '$f', # Pin Change Interrupt Enables
+
+# Module AD_CONVERTER
+ 'ADMUX' : '$7c', # The ADC multiplexer Selection
+ 'ADMUX_REFS': '$c0', # Reference Selection Bits
+ 'ADMUX_ADLAR': '$20', # Left Adjust Result
+ 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
+ 'ADC' : '$78', # ADC Data Register Bytes
+ 'ADCSRA' : '$7a', # The ADC Control and Status reg
+ 'ADCSRA_ADEN': '$80', # ADC Enable
+ 'ADCSRA_ADSC': '$40', # ADC Start Conversion
+ 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
+ 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
+ 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
+ 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
+ 'ADCSRB' : '$7b', # The ADC Control and Status reg
+ 'ADCSRB_ACME': '$40', #
+ 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Source bits
+ 'DIDR0' : '$7e', # Digital Input Disable Register
+ 'DIDR0_ADC7D': '$80', #
+ 'DIDR0_ADC6D': '$40', #
+ 'DIDR0_ADC5D': '$20', #
+ 'DIDR0_ADC4D': '$10', #
+ 'DIDR0_ADC3D': '$8', #
+ 'DIDR0_ADC2D': '$4', #
+ 'DIDR0_ADC1D': '$2', #
+ 'DIDR0_ADC0D': '$1', #
+
+# Module TIMER_COUNTER_1
+ 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
+ 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
+ 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
+ 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
+ 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
+ 'TIFR1' : '$36', # Timer/Counter Interrupt Flag r
+ 'TIFR1_ICF1': '$20', # Timer/Counter1 Input Capture F
+ 'TIFR1_OCF1B': '$4', # Timer/Counter1 Output Compare
+ 'TIFR1_OCF1A': '$2', # Timer/Counter1 Output Compare
+ 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
+ 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
+ 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
+ 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
+ 'TCCR1A_WGM1': '$3', # Pulse Width Modulator Select B
+ 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
+ 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
+ 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
+ 'TCCR1B_WGM1': '$18', # Waveform Generation Mode Bits
+ 'TCCR1B_CS1': '$7', # Clock Select1 bits
+ 'TCCR1C' : '$82', # Timer/Counter1 Control Registe
+ 'TCCR1C_FOC1A': '$80', # Force Output Compare for Chann
+ 'TCCR1C_FOC1B': '$40', # Force Output Compare for Chann
+ 'TCNT1' : '$84', # Timer/Counter1 Bytes
+ 'OCR1A' : '$88', # Timer/Counter1 Output Compare
+ 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
+ 'ICR1' : '$86', # Timer/Counter1 Input Capture R
+
+# Module EEPROM
+ 'EEAR' : '$41', # EEPROM Address Register Low By
+ 'EEDR' : '$40', # EEPROM Data Register
+ 'EECR' : '$3f', # EEPROM Control Register
+ 'EECR_EEPM': '$30', # EEPROM Programming Mode Bits
+ 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
+ 'EECR_EEMPE': '$4', # EEPROM Master Write Enable
+ 'EECR_EEPE': '$2', # EEPROM Write Enable
+ 'EECR_EERE': '$1', # EEPROM Read Enable
+
+# Module SPI
+ 'SPDR0' : '$4e', # SPI Data Register
+ 'SPSR0' : '$4d', # SPI Status Register
+ 'SPSR0_SPIF0': '$80', # SPI Interrupt Flag
+ 'SPSR0_WCOL0': '$40', # Write Collision Flag
+ 'SPSR0_SPI2X0': '$1', # Double SPI Speed Bit
+ 'SPCR0' : '$4c', # SPI Control Register
+ 'SPCR0_SPIE0': '$80', # SPI Interrupt Enable
+ 'SPCR0_SPE0': '$40', # SPI Enable
+ 'SPCR0_DORD0': '$20', # Data Order
+ 'SPCR0_MSTR0': '$10', # Master/Slave Select
+ 'SPCR0_CPOL0': '$8', # Clock polarity
+ 'SPCR0_CPHA0': '$4', # Clock Phase
+ 'SPCR0_SPR10': '$2', # SPI Clock Rate Select 1
+ 'SPCR0_SPR00': '$1', # SPI Clock Rate Select 0
+
+# Module TWI
+ 'TWAMR' : '$bd', # TWI (Slave) Address Mask Regis
+ 'TWAMR_TWAM': '$fe', #
+ 'TWBR' : '$b8', # TWI Bit Rate register
+ 'TWCR' : '$bc', # TWI Control Register
+ 'TWCR_TWINT': '$80', # TWI Interrupt Flag
+ 'TWCR_TWEA': '$40', # TWI Enable Acknowledge Bit
+ 'TWCR_TWSTA': '$20', # TWI Start Condition Bit
+ 'TWCR_TWSTO': '$10', # TWI Stop Condition Bit
+ 'TWCR_TWWC': '$8', # TWI Write Collition Flag
+ 'TWCR_TWEN': '$4', # TWI Enable Bit
+ 'TWCR_TWIE': '$1', # TWI Interrupt Enable
+ 'TWSR' : '$b9', # TWI Status Register
+ 'TWSR_TWS': '$f8', # TWI Status
+ 'TWSR_TWPS': '$3', # TWI Prescaler
+ 'TWDR' : '$bb', # TWI Data register
+ 'TWAR' : '$ba', # TWI (Slave) Address register
+ 'TWAR_TWA': '$fe', # TWI (Slave) Address register B
+ 'TWAR_TWGCE': '$1', # TWI General Call Recognition E
+
+# Module USART1
+ 'UDR1' : '$ce', # USART I/O Data Register
+ 'UCSR1A' : '$c8', # USART Control and Status Regis
+ 'UCSR1A_RXC1': '$80', # USART Receive Complete
+ 'UCSR1A_TXC1': '$40', # USART Transmitt Complete
+ 'UCSR1A_UDRE1': '$20', # USART Data Register Empty
+ 'UCSR1A_FE1': '$10', # Framing Error
+ 'UCSR1A_DOR1': '$8', # Data overRun
+ 'UCSR1A_UPE1': '$4', # Parity Error
+ 'UCSR1A_U2X1': '$2', # Double the USART transmission
+ 'UCSR1A_MPCM1': '$1', # Multi-processor Communication
+ 'UCSR1B' : '$c9', # USART Control and Status Regis
+ 'UCSR1B_RXCIE1': '$80', # RX Complete Interrupt Enable
+ 'UCSR1B_TXCIE1': '$40', # TX Complete Interrupt Enable
+ 'UCSR1B_UDRIE1': '$20', # USART Data register Empty Inte
+ 'UCSR1B_RXEN1': '$10', # Receiver Enable
+ 'UCSR1B_TXEN1': '$8', # Transmitter Enable
+ 'UCSR1B_UCSZ12': '$4', # Character Size
+ 'UCSR1B_RXB81': '$2', # Receive Data Bit 8
+ 'UCSR1B_TXB81': '$1', # Transmit Data Bit 8
+ 'UCSR1C' : '$ca', # USART Control and Status Regis
+ 'UCSR1C_UMSEL1': '$c0', # USART Mode Select
+ 'UCSR1C_UPM1': '$30', # Parity Mode Bits
+ 'UCSR1C_USBS1': '$8', # Stop Bit Select
+ 'UCSR1C_UCSZ1': '$6', # Character Size
+ 'UCSR1C_UCPOL1': '$1', # Clock Polarity
+ 'UBRR1' : '$cc', # USART Baud Rate Register Byte
+
+# Module CPU
+ 'SREG' : '$5f', # Status Register
+ 'SREG_I': '$80', # Global Interrupt Enable
+ 'SREG_T': '$40', # Bit Copy Storage
+ 'SREG_H': '$20', # Half Carry Flag
+ 'SREG_S': '$10', # Sign Bit
+ 'SREG_V': '$8', # Two's Complement Overflow Flag
+ 'SREG_N': '$4', # Negative Flag
+ 'SREG_Z': '$2', # Zero Flag
+ 'SREG_C': '$1', # Carry Flag
+ 'SP' : '$5d', # Stack Pointer
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_JTD': '$80', # JTAG Interface Disable
+ 'MCUCR_BODS': '$40', # BOD Power Down in Sleep
+ 'MCUCR_BODSE': '$20', # BOD Power Down in Sleep Enable
+ 'MCUCR_PUD': '$10', # Pull-up disable
+ 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
+ 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+ 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
+ 'MCUSR_BORF': '$4', # Brown-out Reset Flag
+ 'MCUSR_EXTRF': '$2', # External Reset Flag
+ 'MCUSR_PORF': '$1', # Power-on reset flag
+ 'OSCCAL' : '$66', # Oscillator Calibration Value
+ 'CLKPR' : '$61', #
+ 'CLKPR_CLKPCE': '$80', #
+ 'CLKPR_CLKPS': '$f', #
+ 'SMCR' : '$53', # Sleep Mode Control Register
+ 'SMCR_SM': '$e', # Sleep Mode Select bits
+ 'SMCR_SE': '$1', # Sleep Enable
+ 'GPIOR2' : '$4b', # General Purpose IO Register 2
+ 'GPIOR2_GPIOR': '$ff', # General Purpose IO Register 2
+ 'GPIOR1' : '$4a', # General Purpose IO Register 1
+ 'GPIOR1_GPIOR': '$ff', # General Purpose IO Register 1
+ 'GPIOR0' : '$3e', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR07': '$80', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR06': '$40', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR05': '$20', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR04': '$10', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR03': '$8', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR02': '$4', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR01': '$2', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR00': '$1', # General Purpose IO Register 0
+ 'PRR0' : '$64', # Power Reduction Register0
+ 'PRR0_PRTWI': '$80', # Power Reduction TWI
+ 'PRR0_PRTIM2': '$40', # Power Reduction Timer/Counter2
+ 'PRR0_PRTIM0': '$20', # Power Reduction Timer/Counter0
+ 'PRR0_PRUSART': '$12', # Power Reduction USARTs
+ 'PRR0_PRTIM1': '$8', # Power Reduction Timer/Counter1
+ 'PRR0_PRSPI': '$4', # Power Reduction Serial Periphe
+ 'PRR0_PRADC': '$1', # Power Reduction ADC
+
+ '__amforth_dummy':'0'
+}
diff --git a/amforth-6.5/avr8/devices/atmega164pa/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega164pa/words/no-jtag.asm
new file mode 100644
index 0000000..352a4bb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega164pa/words/no-jtag.asm
@@ -0,0 +1,14 @@
+; ( -- )
+; ( -- )
+; MCU
+; disable jtag at runtime
+VE_NOJTAG:
+ .dw $FF05
+ .db "-jtag",0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOJTAG
+XT_NOJTAG:
+ .dw PFA_NOJTAG
+PFA_NOJTAG:
+
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega164pa/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega164pa/words/no-wdt.asm
new file mode 100644
index 0000000..ff6ddd1
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega164pa/words/no-wdt.asm
@@ -0,0 +1,34 @@
+; ( -- )
+; MCU
+; disable watch dog timer at runtime
+VE_NOWDT:
+ .dw $ff04
+ .db "-wdt"
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOWDT
+XT_NOWDT:
+ .dw PFA_NOWDT
+PFA_NOWDT:
+
+ in temp1,SREG
+ push temp1
+ ; Turn always off global interrupt.
+ cli
+ ; Reset Watchdog Timer
+ wdr
+ ; Clear WDRF in MCUSR
+ in temp1, MCUSR
+ andi temp1, (0xff & (0<<WDRF))
+ out MCUSR, temp1
+ ; Write logical one to WDCE and WDE
+ ; Keep old prescaler setting to prevent unintentional time-out
+ in_ temp1, WDTCSR
+ ori temp1, (1<<WDCE) | (1<<WDE)
+ out_ WDTCSR, temp1
+ ; Turn off WDT
+ ldi temp1, (0<<WDE)
+ out_ WDTCSR, temp1
+ ; restore status register
+ pop temp1
+ out SREG,temp1
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega164pa/words/sleep.asm b/amforth-6.5/avr8/devices/atmega164pa/words/sleep.asm
new file mode 100644
index 0000000..256249c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega164pa/words/sleep.asm
@@ -0,0 +1,19 @@
+; ( mode -- )
+; MCU
+; put the controller into the specified sleep mode
+VE_SLEEP:
+ .dw $ff05
+ .db "sleep", 0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_SLEEP
+XT_SLEEP:
+ .dw PFA_SLEEP
+PFA_SLEEP:
+ andi tosl, 7 ; leave only legal mode bits
+ lsl tosl ; move to correct location (bits 3-1)
+ ori tosl, 1 ; set the SE bit
+ out_ SMCR, tosl ; set the sleep config
+ sleep ; nighty-night
+ out_ SMCR, zerol ; 0 protects against accidental sleeps
+ loadtos ; pop argument from stack
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega165/atmega165.frt b/amforth-6.5/avr8/devices/atmega165/atmega165.frt
new file mode 100644
index 0000000..25fea57
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega165/atmega165.frt
@@ -0,0 +1,160 @@
+\ Partname: ATmega165
+\ Built using part description XML file version 126
+\ generated automatically
+
+hex
+
+\ AD_CONVERTER
+79 constant ADCH \ ADC Data Register High Byte
+78 constant ADCL \ ADC Data Register Low Byte
+7A constant ADCSRA \ The ADC Control and Status register
+7B constant ADCSRB \ ADC Control and Status Register B
+7C constant ADMUX \ The ADC multiplexer Selection Register
+7E constant DIDR0 \ Digital Input Disable Register 0
+
+\ ANALOG_COMPARATOR
+50 constant ACSR \ Analog Comparator Control And Status Register
+7F constant DIDR1 \ Digital Input Disable Register 1
+
+\ BOOT_LOAD
+57 constant SPMCSR \ Store Program Memory Control Register
+
+\ CPU
+61 constant CLKPR \ Clock Prescale Register
+3E constant GPIOR0 \ General Purpose IO Register 0
+4A constant GPIOR1 \ General Purpose IO Register 1
+4B constant GPIOR2 \ General Purpose IO Register 2
+55 constant MCUCR \ MCU Control Register
+54 constant MCUSR \ MCU Status Register
+66 constant OSCCAL \ Oscillator Calibration Value
+64 constant PRR \ Power Reduction Register
+53 constant SMCR \ Sleep Mode Control Register
+5E constant SPH \ Stack Pointer High
+5D constant SPL \ Stack Pointer Low
+5F constant SREG \ Status Register
+
+\ EEPROM
+42 constant EEARH \ EEPROM Address Register High Byte
+41 constant EEARL \ EEPROM Address Register Low Byte
+3F constant EECR \ EEPROM Control Register
+40 constant EEDR \ EEPROM Data Register
+
+\ EXTERNAL_INTERRUPT
+69 constant EICRA \ External Interrupt Control Register
+3C constant EIFR \ External Interrupt Flag Register
+3D constant EIMSK \ External Interrupt Mask Register
+6B constant PCMSK0 \ Pin Change Mask Register 0
+6C constant PCMSK1 \ Pin Change Mask Register 1
+
+\ JTAG
+51 constant OCDR \ On-Chip Debug Related Register in I/O Memory
+
+\ PORTA
+21 constant DDRA \ Port A Data Direction Register
+20 constant PINA \ Port A Input Pins
+22 constant PORTA \ Port A Data Register
+
+\ PORTB
+24 constant DDRB \ Port B Data Direction Register
+23 constant PINB \ Port B Input Pins
+25 constant PORTB \ Port B Data Register
+
+\ PORTC
+27 constant DDRC \ Port C Data Direction Register
+26 constant PINC \ Port C Input Pins
+28 constant PORTC \ Port C Data Register
+
+\ PORTD
+2A constant DDRD \ Port D Data Direction Register
+29 constant PIND \ Port D Input Pins
+2B constant PORTD \ Port D Data Register
+
+\ PORTE
+2D constant DDRE \ Data Direction Register, Port E
+2C constant PINE \ Input Pins, Port E
+2E constant PORTE \ Data Register, Port E
+
+\ PORTF
+30 constant DDRF \ Data Direction Register, Port F
+2F constant PINF \ Input Pins, Port F
+31 constant PORTF \ Data Register, Port F
+
+\ PORTG
+33 constant DDRG \ Port G Data Direction Register
+32 constant PING \ Port G Input Pins
+34 constant PORTG \ Port G Data Register
+
+\ SPI
+4C constant SPCR \ SPI Control Register
+4E constant SPDR \ SPI Data Register
+4D constant SPSR \ SPI Status Register
+
+\ TIMER_COUNTER_0
+43 constant GTCCR \ General Timer/Control Register
+47 constant OCR0A \ Timer/Counter0 Output Compare Register
+44 constant TCCR0A \ Timer/Counter0 Control Register
+46 constant TCNT0 \ Timer/Counter0
+35 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
+6E constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
+
+\ TIMER_COUNTER_1
+87 constant ICR1H \ Timer/Counter1 Input Capture Register High Byte
+86 constant ICR1L \ Timer/Counter1 Input Capture Register Low Byte
+89 constant OCR1AH \ Timer/Counter1 Output Compare Register A High Byte
+88 constant OCR1AL \ Timer/Counter1 Output Compare Register A Low Byte
+8B constant OCR1BH \ Timer/Counter1 Output Compare Register B High Byte
+8A constant OCR1BL \ Timer/Counter1 Output Compare Register B Low Byte
+80 constant TCCR1A \ Timer/Counter1 Control Register A
+81 constant TCCR1B \ Timer/Counter1 Control Register B
+82 constant TCCR1C \ Timer/Counter 1 Control Register C
+85 constant TCNT1H \ Timer/Counter1 High Byte
+84 constant TCNT1L \ Timer/Counter1 Low Byte
+36 constant TIFR1 \ Timer/Counter1 Interrupt Flag register
+6F constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
+
+\ TIMER_COUNTER_2
+B6 constant ASSR \ Asynchronous Status Register
+B3 constant OCR2A \ Timer/Counter2 Output Compare Register
+B0 constant TCCR2A \ Timer/Counter2 Control Register
+B2 constant TCNT2 \ Timer/Counter2
+37 constant TIFR2 \ Timer/Counter2 Interrupt Flag Register
+70 constant TIMSK2 \ Timer/Counter2 Interrupt Mask register
+
+\ USART0
+C5 constant UBRR0H \ USART Baud Rate Register High Byte
+C4 constant UBRR0L \ USART Baud Rate Register Low Byte
+C0 constant UCSR0A \ USART Control and Status Register A
+C1 constant UCSR0B \ USART Control and Status Register B
+C2 constant UCSR0C \ USART Control and Status Register C
+C6 constant UDR0 \ USART I/O Data Register
+
+\ USI
+B8 constant USICR \ USI Control Register
+BA constant USIDR \ USI Data Register
+B9 constant USISR \ USI Status Register
+
+\ WATCHDOG
+60 constant WDTCR \ Watchdog Timer Control Register
+
+\ Interrupts
+002 constant INT0Addr \ External Interrupt Request 0
+004 constant PCINT0Addr \ Pin Change Interrupt Request 0
+006 constant PCINT1Addr \ Pin Change Interrupt Request 1
+008 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
+00A constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
+00C constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+00E constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
+010 constant TIMER1_COMPBAddr \ Timer/Counter Compare Match B
+012 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+014 constant TIMER0_COMPAddr \ Timer/Counter0 Compare Match
+016 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
+018 constant SPI_STCAddr \ SPI Serial Transfer Complete
+01A constant USART0_RXAddr \ USART0, Rx Complete
+01C constant USART0_UDREAddr \ USART0 Data register Empty
+01E constant USART0_TXAddr \ USART0, Tx Complete
+020 constant USI_STARTAddr \ USI Start Condition
+022 constant USI_OVERFLOWAddr \ USI Overflow
+024 constant ANALOG_COMPAddr \ Analog Comparator
+026 constant ADCAddr \ ADC Conversion Complete
+028 constant EE_READYAddr \ EEPROM Ready
+02A constant SPM_READYAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/atmega165/device.asm b/amforth-6.5/avr8/devices/atmega165/device.asm
new file mode 100644
index 0000000..87aad59
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega165/device.asm
@@ -0,0 +1,120 @@
+; Partname: ATmega165
+; Built using part description XML file version 126
+; generated automatically, do not edit
+
+.nolist
+ .include "m165def.inc"
+.list
+
+.equ ramstart = $100
+.equ CELLSIZE = 2
+.macro readflashcell
+ lsl zl
+ rol zh
+ lpm @0, Z+
+ lpm @1, Z+
+.endmacro
+.macro writeflashcell
+ lsl zl
+ rol zh
+.endmacro
+
+; the following definitions are shortcuts for the respective forth source segments if set to 1
+.set WANT_AD_CONVERTER = 0
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_BOOT_LOAD = 0
+.set WANT_CPU = 0
+.set WANT_EEPROM = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_JTAG = 0
+.set WANT_PORTA = 0
+.set WANT_PORTB = 0
+.set WANT_PORTC = 0
+.set WANT_PORTD = 0
+.set WANT_PORTE = 0
+.set WANT_PORTF = 0
+.set WANT_PORTG = 0
+.set WANT_SPI = 0
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_TIMER_COUNTER_2 = 0
+.set WANT_USART0 = 0
+.set WANT_USI = 0
+.set WANT_WATCHDOG = 0
+
+
+.ifndef SPMEN
+ .equ SPMEN = SELFPRGEN
+.endif
+
+.ifndef SPMCSR
+ .equ SPMCSR = SPMCR
+.endif
+
+.ifndef EEPE
+ .equ EEPE = EEWE
+.endif
+
+.ifndef EEMPE
+ .equ EEMPE = EEMWE
+.endif
+.equ intvecsize = 2 ; please verify; flash size: 16384 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.equ INTVECTORS = 22
+.org $002
+ rcall isr ; External Interrupt Request 0
+.org $004
+ rcall isr ; Pin Change Interrupt Request 0
+.org $006
+ rcall isr ; Pin Change Interrupt Request 1
+.org $008
+ rcall isr ; Timer/Counter2 Compare Match
+.org $00A
+ rcall isr ; Timer/Counter2 Overflow
+.org $00C
+ rcall isr ; Timer/Counter1 Capture Event
+.org $00E
+ rcall isr ; Timer/Counter1 Compare Match A
+.org $010
+ rcall isr ; Timer/Counter Compare Match B
+.org $012
+ rcall isr ; Timer/Counter1 Overflow
+.org $014
+ rcall isr ; Timer/Counter0 Compare Match
+.org $016
+ rcall isr ; Timer/Counter0 Overflow
+.org $018
+ rcall isr ; SPI Serial Transfer Complete
+.org $01A
+ rcall isr ; USART0, Rx Complete
+.org $01C
+ rcall isr ; USART0 Data register Empty
+.org $01E
+ rcall isr ; USART0, Tx Complete
+.org $020
+ rcall isr ; USI Start Condition
+.org $022
+ rcall isr ; USI Overflow
+.org $024
+ rcall isr ; Analog Comparator
+.org $026
+ rcall isr ; ADC Conversion Complete
+.org $028
+ rcall isr ; EEPROM Ready
+.org $02A
+ rcall isr ; Store Program Memory Read
+.nooverlap
+mcu_info:
+mcu_ramsize:
+ .dw 1024
+mcu_eepromsize:
+ .dw 512
+mcu_maxdp:
+ .dw 7168 ; minimum of 0x1C00 (from XML) and 0xffff
+mcu_numints:
+ .dw 22
+mcu_name:
+ .dw 9
+ .db "ATmega165",0
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega165/device.inc b/amforth-6.5/avr8/devices/atmega165/device.inc
new file mode 100644
index 0000000..739f874
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega165/device.inc
@@ -0,0 +1,1209 @@
+; Partname: ATmega165
+; Built using part description XML file version 126
+; generated automatically, no not edit
+
+; ********
+.if WANT_AD_CONVERTER == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register High Byte
+VE_ADCH:
+ .dw $ff04
+ .db "ADCH"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCH
+XT_ADCH:
+ .dw PFA_DOVARIABLE
+PFA_ADCH:
+ .dw $79
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register Low Byte
+VE_ADCL:
+ .dw $ff04
+ .db "ADCL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCL
+XT_ADCL:
+ .dw PFA_DOVARIABLE
+PFA_ADCL:
+ .dw $78
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register
+VE_ADCSRA:
+ .dw $ff06
+ .db "ADCSRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRA
+XT_ADCSRA:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRA:
+ .dw $7A
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Control and Status Register B
+VE_ADCSRB:
+ .dw $ff06
+ .db "ADCSRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRB
+XT_ADCSRB:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRB:
+ .dw $7B
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC multiplexer Selection Register
+VE_ADMUX:
+ .dw $ff05
+ .db "ADMUX",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADMUX
+XT_ADMUX:
+ .dw PFA_DOVARIABLE
+PFA_ADMUX:
+ .dw $7C
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 0
+VE_DIDR0:
+ .dw $ff05
+ .db "DIDR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR0
+XT_DIDR0:
+ .dw PFA_DOVARIABLE
+PFA_DIDR0:
+ .dw $7E
+
+.endif
+
+; ********
+.if WANT_ANALOG_COMPARATOR == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Control And Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw $50
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 1
+VE_DIDR1:
+ .dw $ff05
+ .db "DIDR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR1
+XT_DIDR1:
+ .dw PFA_DOVARIABLE
+PFA_DIDR1:
+ .dw $7F
+
+.endif
+
+; ********
+.if WANT_BOOT_LOAD == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control Register
+VE_SPMCSR:
+ .dw $ff06
+ .db "SPMCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCSR
+XT_SPMCSR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCSR:
+ .dw $57
+
+.endif
+
+; ********
+.if WANT_CPU == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Clock Prescale Register
+VE_CLKPR:
+ .dw $ff05
+ .db "CLKPR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKPR
+XT_CLKPR:
+ .dw PFA_DOVARIABLE
+PFA_CLKPR:
+ .dw $61
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 0
+VE_GPIOR0:
+ .dw $ff06
+ .db "GPIOR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR0
+XT_GPIOR0:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR0:
+ .dw $3E
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 1
+VE_GPIOR1:
+ .dw $ff06
+ .db "GPIOR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR1
+XT_GPIOR1:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR1:
+ .dw $4A
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 2
+VE_GPIOR2:
+ .dw $ff06
+ .db "GPIOR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR2
+XT_GPIOR2:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR2:
+ .dw $4B
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw $55
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Status Register
+VE_MCUSR:
+ .dw $ff05
+ .db "MCUSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUSR
+XT_MCUSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUSR:
+ .dw $54
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Calibration Value
+VE_OSCCAL:
+ .dw $ff06
+ .db "OSCCAL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSCCAL
+XT_OSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_OSCCAL:
+ .dw $66
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register
+VE_PRR:
+ .dw $ff03
+ .db "PRR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR
+XT_PRR:
+ .dw PFA_DOVARIABLE
+PFA_PRR:
+ .dw $64
+; ( -- addr ) System Constant
+; R( -- )
+; Sleep Mode Control Register
+VE_SMCR:
+ .dw $ff04
+ .db "SMCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SMCR
+XT_SMCR:
+ .dw PFA_DOVARIABLE
+PFA_SMCR:
+ .dw $53
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer High
+VE_SPH:
+ .dw $ff03
+ .db "SPH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPH
+XT_SPH:
+ .dw PFA_DOVARIABLE
+PFA_SPH:
+ .dw $5E
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer Low
+VE_SPL:
+ .dw $ff03
+ .db "SPL",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPL
+XT_SPL:
+ .dw PFA_DOVARIABLE
+PFA_SPL:
+ .dw $5D
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw $5F
+
+.endif
+
+; ********
+.if WANT_EEPROM == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Address Register High Byte
+VE_EEARH:
+ .dw $ff05
+ .db "EEARH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEARH
+XT_EEARH:
+ .dw PFA_DOVARIABLE
+PFA_EEARH:
+ .dw $42
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Address Register Low Byte
+VE_EEARL:
+ .dw $ff05
+ .db "EEARL",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEARL
+XT_EEARL:
+ .dw PFA_DOVARIABLE
+PFA_EEARL:
+ .dw $41
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw $3F
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw $40
+
+.endif
+
+; ********
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register
+VE_EICRA:
+ .dw $ff05
+ .db "EICRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRA
+XT_EICRA:
+ .dw PFA_DOVARIABLE
+PFA_EICRA:
+ .dw $69
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Flag Register
+VE_EIFR:
+ .dw $ff04
+ .db "EIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIFR
+XT_EIFR:
+ .dw PFA_DOVARIABLE
+PFA_EIFR:
+ .dw $3C
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Mask Register
+VE_EIMSK:
+ .dw $ff05
+ .db "EIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIMSK
+XT_EIMSK:
+ .dw PFA_DOVARIABLE
+PFA_EIMSK:
+ .dw $3D
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 0
+VE_PCMSK0:
+ .dw $ff06
+ .db "PCMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK0
+XT_PCMSK0:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK0:
+ .dw $6B
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 1
+VE_PCMSK1:
+ .dw $ff06
+ .db "PCMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK1
+XT_PCMSK1:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK1:
+ .dw $6C
+
+.endif
+
+; ********
+.if WANT_JTAG == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; On-Chip Debug Related Register in I/O Memory
+VE_OCDR:
+ .dw $ff04
+ .db "OCDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCDR
+XT_OCDR:
+ .dw PFA_DOVARIABLE
+PFA_OCDR:
+ .dw $51
+
+.endif
+
+; ********
+.if WANT_PORTA == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Direction Register
+VE_DDRA:
+ .dw $ff04
+ .db "DDRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRA
+XT_DDRA:
+ .dw PFA_DOVARIABLE
+PFA_DDRA:
+ .dw $21
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Input Pins
+VE_PINA:
+ .dw $ff04
+ .db "PINA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINA
+XT_PINA:
+ .dw PFA_DOVARIABLE
+PFA_PINA:
+ .dw $20
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Register
+VE_PORTA:
+ .dw $ff05
+ .db "PORTA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTA
+XT_PORTA:
+ .dw PFA_DOVARIABLE
+PFA_PORTA:
+ .dw $22
+
+.endif
+
+; ********
+.if WANT_PORTB == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw $24
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw $23
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw $25
+
+.endif
+
+; ********
+.if WANT_PORTC == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Direction Register
+VE_DDRC:
+ .dw $ff04
+ .db "DDRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRC
+XT_DDRC:
+ .dw PFA_DOVARIABLE
+PFA_DDRC:
+ .dw $27
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Input Pins
+VE_PINC:
+ .dw $ff04
+ .db "PINC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINC
+XT_PINC:
+ .dw PFA_DOVARIABLE
+PFA_PINC:
+ .dw $26
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Register
+VE_PORTC:
+ .dw $ff05
+ .db "PORTC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTC
+XT_PORTC:
+ .dw PFA_DOVARIABLE
+PFA_PORTC:
+ .dw $28
+
+.endif
+
+; ********
+.if WANT_PORTD == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw $2A
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw $29
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw $2B
+
+.endif
+
+; ********
+.if WANT_PORTE == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port E
+VE_DDRE:
+ .dw $ff04
+ .db "DDRE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRE
+XT_DDRE:
+ .dw PFA_DOVARIABLE
+PFA_DDRE:
+ .dw $2D
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port E
+VE_PINE:
+ .dw $ff04
+ .db "PINE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINE
+XT_PINE:
+ .dw PFA_DOVARIABLE
+PFA_PINE:
+ .dw $2C
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port E
+VE_PORTE:
+ .dw $ff05
+ .db "PORTE",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTE
+XT_PORTE:
+ .dw PFA_DOVARIABLE
+PFA_PORTE:
+ .dw $2E
+
+.endif
+
+; ********
+.if WANT_PORTF == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port F
+VE_DDRF:
+ .dw $ff04
+ .db "DDRF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRF
+XT_DDRF:
+ .dw PFA_DOVARIABLE
+PFA_DDRF:
+ .dw $30
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port F
+VE_PINF:
+ .dw $ff04
+ .db "PINF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINF
+XT_PINF:
+ .dw PFA_DOVARIABLE
+PFA_PINF:
+ .dw $2F
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port F
+VE_PORTF:
+ .dw $ff05
+ .db "PORTF",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTF
+XT_PORTF:
+ .dw PFA_DOVARIABLE
+PFA_PORTF:
+ .dw $31
+
+.endif
+
+; ********
+.if WANT_PORTG == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Data Direction Register
+VE_DDRG:
+ .dw $ff04
+ .db "DDRG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRG
+XT_DDRG:
+ .dw PFA_DOVARIABLE
+PFA_DDRG:
+ .dw $33
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Input Pins
+VE_PING:
+ .dw $ff04
+ .db "PING"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PING
+XT_PING:
+ .dw PFA_DOVARIABLE
+PFA_PING:
+ .dw $32
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Data Register
+VE_PORTG:
+ .dw $ff05
+ .db "PORTG",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTG
+XT_PORTG:
+ .dw PFA_DOVARIABLE
+PFA_PORTG:
+ .dw $34
+
+.endif
+
+; ********
+.if WANT_SPI == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR:
+ .dw $ff04
+ .db "SPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR
+XT_SPCR:
+ .dw PFA_DOVARIABLE
+PFA_SPCR:
+ .dw $4C
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR:
+ .dw $ff04
+ .db "SPDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR
+XT_SPDR:
+ .dw PFA_DOVARIABLE
+PFA_SPDR:
+ .dw $4E
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR:
+ .dw $ff04
+ .db "SPSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR
+XT_SPSR:
+ .dw PFA_DOVARIABLE
+PFA_SPSR:
+ .dw $4D
+
+.endif
+
+; ********
+.if WANT_TIMER_COUNTER_0 == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; General Timer/Control Register
+VE_GTCCR:
+ .dw $ff05
+ .db "GTCCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GTCCR
+XT_GTCCR:
+ .dw PFA_DOVARIABLE
+PFA_GTCCR:
+ .dw $43
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0A:
+ .dw $ff05
+ .db "OCR0A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0A
+XT_OCR0A:
+ .dw PFA_DOVARIABLE
+PFA_OCR0A:
+ .dw $47
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Control Register
+VE_TCCR0A:
+ .dw $ff06
+ .db "TCCR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0A
+XT_TCCR0A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0A:
+ .dw $44
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw $46
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Flag register
+VE_TIFR0:
+ .dw $ff05
+ .db "TIFR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR0
+XT_TIFR0:
+ .dw PFA_DOVARIABLE
+PFA_TIFR0:
+ .dw $35
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Mask Register
+VE_TIMSK0:
+ .dw $ff06
+ .db "TIMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK0
+XT_TIMSK0:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK0:
+ .dw $6E
+
+.endif
+
+; ********
+.if WANT_TIMER_COUNTER_1 == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register High Byte
+VE_ICR1H:
+ .dw $ff05
+ .db "ICR1H",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1H
+XT_ICR1H:
+ .dw PFA_DOVARIABLE
+PFA_ICR1H:
+ .dw $87
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Low Byte
+VE_ICR1L:
+ .dw $ff05
+ .db "ICR1L",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1L
+XT_ICR1L:
+ .dw PFA_DOVARIABLE
+PFA_ICR1L:
+ .dw $86
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register A High Byte
+VE_OCR1AH:
+ .dw $ff06
+ .db "OCR1AH"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1AH
+XT_OCR1AH:
+ .dw PFA_DOVARIABLE
+PFA_OCR1AH:
+ .dw $89
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register A Low Byte
+VE_OCR1AL:
+ .dw $ff06
+ .db "OCR1AL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1AL
+XT_OCR1AL:
+ .dw PFA_DOVARIABLE
+PFA_OCR1AL:
+ .dw $88
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register B High Byte
+VE_OCR1BH:
+ .dw $ff06
+ .db "OCR1BH"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1BH
+XT_OCR1BH:
+ .dw PFA_DOVARIABLE
+PFA_OCR1BH:
+ .dw $8B
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register B Low Byte
+VE_OCR1BL:
+ .dw $ff06
+ .db "OCR1BL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1BL
+XT_OCR1BL:
+ .dw PFA_DOVARIABLE
+PFA_OCR1BL:
+ .dw $8A
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw $80
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw $81
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter 1 Control Register C
+VE_TCCR1C:
+ .dw $ff06
+ .db "TCCR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1C
+XT_TCCR1C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1C:
+ .dw $82
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 High Byte
+VE_TCNT1H:
+ .dw $ff06
+ .db "TCNT1H"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1H
+XT_TCNT1H:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1H:
+ .dw $85
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Low Byte
+VE_TCNT1L:
+ .dw $ff06
+ .db "TCNT1L"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1L
+XT_TCNT1L:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1L:
+ .dw $84
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Flag register
+VE_TIFR1:
+ .dw $ff05
+ .db "TIFR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR1
+XT_TIFR1:
+ .dw PFA_DOVARIABLE
+PFA_TIFR1:
+ .dw $36
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Mask Register
+VE_TIMSK1:
+ .dw $ff06
+ .db "TIMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK1
+XT_TIMSK1:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK1:
+ .dw $6F
+
+.endif
+
+; ********
+.if WANT_TIMER_COUNTER_2 == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Asynchronous Status Register
+VE_ASSR:
+ .dw $ff04
+ .db "ASSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ASSR
+XT_ASSR:
+ .dw PFA_DOVARIABLE
+PFA_ASSR:
+ .dw $B6
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register
+VE_OCR2A:
+ .dw $ff05
+ .db "OCR2A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2A
+XT_OCR2A:
+ .dw PFA_DOVARIABLE
+PFA_OCR2A:
+ .dw $B3
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register
+VE_TCCR2A:
+ .dw $ff06
+ .db "TCCR2A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2A
+XT_TCCR2A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2A:
+ .dw $B0
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2
+VE_TCNT2:
+ .dw $ff05
+ .db "TCNT2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT2
+XT_TCNT2:
+ .dw PFA_DOVARIABLE
+PFA_TCNT2:
+ .dw $B2
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Interrupt Flag Register
+VE_TIFR2:
+ .dw $ff05
+ .db "TIFR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR2
+XT_TIFR2:
+ .dw PFA_DOVARIABLE
+PFA_TIFR2:
+ .dw $37
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Interrupt Mask register
+VE_TIMSK2:
+ .dw $ff06
+ .db "TIMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK2
+XT_TIMSK2:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK2:
+ .dw $70
+
+.endif
+
+; ********
+.if WANT_USART0 == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register High Byte
+VE_UBRR0H:
+ .dw $ff06
+ .db "UBRR0H"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR0H
+XT_UBRR0H:
+ .dw PFA_DOVARIABLE
+PFA_UBRR0H:
+ .dw $C5
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Low Byte
+VE_UBRR0L:
+ .dw $ff06
+ .db "UBRR0L"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR0L
+XT_UBRR0L:
+ .dw PFA_DOVARIABLE
+PFA_UBRR0L:
+ .dw $C4
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR0A:
+ .dw $ff06
+ .db "UCSR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0A
+XT_UCSR0A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0A:
+ .dw $C0
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR0B:
+ .dw $ff06
+ .db "UCSR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0B
+XT_UCSR0B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0B:
+ .dw $C1
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR0C:
+ .dw $ff06
+ .db "UCSR0C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0C
+XT_UCSR0C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0C:
+ .dw $C2
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR0:
+ .dw $ff04
+ .db "UDR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR0
+XT_UDR0:
+ .dw PFA_DOVARIABLE
+PFA_UDR0:
+ .dw $C6
+
+.endif
+
+; ********
+.if WANT_USI == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; USI Control Register
+VE_USICR:
+ .dw $ff05
+ .db "USICR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USICR
+XT_USICR:
+ .dw PFA_DOVARIABLE
+PFA_USICR:
+ .dw $B8
+; ( -- addr ) System Constant
+; R( -- )
+; USI Data Register
+VE_USIDR:
+ .dw $ff05
+ .db "USIDR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USIDR
+XT_USIDR:
+ .dw PFA_DOVARIABLE
+PFA_USIDR:
+ .dw $BA
+; ( -- addr ) System Constant
+; R( -- )
+; USI Status Register
+VE_USISR:
+ .dw $ff05
+ .db "USISR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USISR
+XT_USISR:
+ .dw PFA_DOVARIABLE
+PFA_USISR:
+ .dw $B9
+
+.endif
+
+; ********
+.if WANT_WATCHDOG == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCR:
+ .dw $ff05
+ .db "WDTCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCR
+XT_WDTCR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCR:
+ .dw $60
+
+.endif
diff --git a/amforth-6.5/avr8/devices/atmega165/device.py b/amforth-6.5/avr8/devices/atmega165/device.py
new file mode 100644
index 0000000..bd637ca
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega165/device.py
@@ -0,0 +1,319 @@
+# Generated Automatically
+
+# Partname ATmega165A
+
+MCUREGS = {
+# Interrupt Vectors
+ 'INT0Addr' : '#2', # External Interrupt Request 0
+ 'PCINT0Addr' : '#4', # Pin Change Interrupt Request 0
+ 'PCINT1Addr' : '#6', # Pin Change Interrupt Request 1
+ 'TIMER2_COMPAddr' : '#8', # Timer/Counter2 Compare Match
+ 'TIMER2_OVFAddr' : '#10', # Timer/Counter2 Overflow
+ 'TIMER1_CAPTAddr' : '#12', # Timer/Counter1 Capture Event
+ 'TIMER1_COMPAAddr' : '#14', # Timer/Counter1 Compare Match A
+ 'TIMER1_COMPBAddr' : '#16', # Timer/Counter Compare Match B
+ 'TIMER1_OVFAddr' : '#18', # Timer/Counter1 Overflow
+ 'TIMER0_COMPAddr' : '#20', # Timer/Counter0 Compare Match
+ 'TIMER0_OVFAddr' : '#22', # Timer/Counter0 Overflow
+ 'SPI_STCAddr' : '#24', # SPI Serial Transfer Complete
+ 'USART0_RXAddr' : '#26', # USART0, Rx Complete
+ 'USART0_UDREAddr' : '#28', # USART0 Data register Empty
+ 'USART0_TXAddr' : '#30', # USART0, Tx Complete
+ 'USI_STARTAddr' : '#32', # USI Start Condition
+ 'USI_OVERFLOWAddr' : '#34', # USI Overflow
+ 'ANALOG_COMPAddr' : '#36', # Analog Comparator
+ 'ADCAddr' : '#38', # ADC Conversion Complete
+ 'EE_READYAddr' : '#40', # EEPROM Ready
+ 'SPM_READYAddr' : '#42', # Store Program Memory Read
+
+# Module TIMER_COUNTER_0
+ 'TCCR0A' : '$44', # Timer/Counter0 Control Registe
+ 'TCCR0A_FOC0A': '$80', # Force Output Compare
+ 'TCCR0A_WGM00': '$40', # Waveform Generation Mode 0
+ 'TCCR0A_COM0A': '$30', # Compare Match Output Modes
+ 'TCCR0A_WGM01': '$8', # Waveform Generation Mode 1
+ 'TCCR0A_CS0': '$7', # Clock Selects
+ 'TCNT0' : '$46', # Timer/Counter0
+ 'OCR0A' : '$47', # Timer/Counter0 Output Compare
+ 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
+ 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
+ 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
+ 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
+ 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
+ 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Control Register
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSR310': '$1', # Prescaler Reset Timer/Counter1
+
+# Module TIMER_COUNTER_1
+ 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
+ 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
+ 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
+ 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
+ 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
+ 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
+ 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
+ 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
+ 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
+ 'TCCR1C' : '$82', # Timer/Counter 1 Control Regist
+ 'TCCR1C_FOC1A': '$80', # Force Output Compare 1A
+ 'TCCR1C_FOC1B': '$40', # Force Output Compare 1B
+ 'TCNT1' : '$84', # Timer/Counter1 Bytes
+ 'OCR1A' : '$88', # Timer/Counter1 Output Compare
+ 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
+ 'ICR1' : '$86', # Timer/Counter1 Input Capture R
+ 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
+ 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
+ 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
+ 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
+ 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
+ 'TIFR1' : '$36', # Timer/Counter1 Interrupt Flag
+ 'TIFR1_ICF1': '$20', # Input Capture Flag 1
+ 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
+ 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
+ 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
+
+# Module TIMER_COUNTER_2
+ 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
+ 'TCCR2A_FOC2A': '$80', # Force Output Compare A
+ 'TCCR2A_WGM20': '$40', # Waveform Generation Mode
+ 'TCCR2A_COM2A': '$30', # Compare Output Mode bits
+ 'TCCR2A_WGM21': '$8', # Waveform Generation Mode
+ 'TCCR2A_CS2': '$7', # Clock Select bits
+ 'TCNT2' : '$b2', # Timer/Counter2
+ 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
+ 'TIMSK2' : '$70', # Timer/Counter2 Interrupt Mask
+ 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
+ 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
+ 'TIFR2' : '$37', # Timer/Counter2 Interrupt Flag
+ 'TIFR2_OCF2A': '$2', # Timer/Counter2 Output Compare
+ 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_PSR2': '$2', # Prescaler Reset Timer/Counter2
+ 'ASSR' : '$b6', # Asynchronous Status Register
+ 'ASSR_EXCLK': '$10', # Enable External Clock Interrup
+ 'ASSR_AS2': '$8', # AS2: Asynchronous Timer/Counte
+ 'ASSR_TCN2UB': '$4', # TCN2UB: Timer/Counter2 Update
+ 'ASSR_OCR2UB': '$2', # Output Compare Register2 Updat
+ 'ASSR_TCR2UB': '$1', # TCR2UB: Timer/Counter Control
+
+# Module WATCHDOG
+ 'WDTCR' : '$60', # Watchdog Timer Control Registe
+ 'WDTCR_WDCE': '$10', # Watchdog Change Enable
+ 'WDTCR_WDE': '$8', # Watch Dog Enable
+ 'WDTCR_WDP': '$7', # Watch Dog Timer Prescaler bits
+
+# Module EEPROM
+ 'EEAR' : '$41', # EEPROM Address Register Bytes
+ 'EEDR' : '$40', # EEPROM Data Register
+ 'EECR' : '$3f', # EEPROM Control Register
+ 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
+ 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
+ 'EECR_EEWE': '$2', # EEPROM Write Enable
+ 'EECR_EERE': '$1', # EEPROM Read Enable
+
+# Module SPI
+ 'SPCR' : '$4c', # SPI Control Register
+ 'SPCR_SPIE': '$80', # SPI Interrupt Enable
+ 'SPCR_SPE': '$40', # SPI Enable
+ 'SPCR_DORD': '$20', # Data Order
+ 'SPCR_MSTR': '$10', # Master/Slave Select
+ 'SPCR_CPOL': '$8', # Clock polarity
+ 'SPCR_CPHA': '$4', # Clock Phase
+ 'SPCR_SPR': '$3', # SPI Clock Rate Selects
+ 'SPSR' : '$4d', # SPI Status Register
+ 'SPSR_SPIF': '$80', # SPI Interrupt Flag
+ 'SPSR_WCOL': '$40', # Write Collision Flag
+ 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
+ 'SPDR' : '$4e', # SPI Data Register
+
+# Module PORTA
+ 'PORTA' : '$22', # Port A Data Register
+ 'DDRA' : '$21', # Port A Data Direction Register
+ 'PINA' : '$20', # Port A Input Pins
+
+# Module PORTB
+ 'PORTB' : '$25', # Port B Data Register
+ 'DDRB' : '$24', # Port B Data Direction Register
+ 'PINB' : '$23', # Port B Input Pins
+
+# Module PORTC
+ 'PORTC' : '$28', # Port C Data Register
+ 'DDRC' : '$27', # Port C Data Direction Register
+ 'PINC' : '$26', # Port C Input Pins
+
+# Module PORTD
+ 'PORTD' : '$2b', # Port D Data Register
+ 'DDRD' : '$2a', # Port D Data Direction Register
+ 'PIND' : '$29', # Port D Input Pins
+
+# Module ANALOG_COMPARATOR
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
+ 'ACSR' : '$50', # Analog Comparator Control And
+ 'ACSR_ACD': '$80', # Analog Comparator Disable
+ 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
+ 'ACSR_ACO': '$20', # Analog Compare Output
+ 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
+ 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
+ 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
+ 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
+ 'DIDR1' : '$7f', # Digital Input Disable Register
+ 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
+ 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
+
+# Module PORTE
+ 'PORTE' : '$2e', # Data Register, Port E
+ 'DDRE' : '$2d', # Data Direction Register, Port
+ 'PINE' : '$2c', # Input Pins, Port E
+
+# Module PORTF
+ 'PORTF' : '$31', # Data Register, Port F
+ 'DDRF' : '$30', # Data Direction Register, Port
+ 'PINF' : '$2f', # Input Pins, Port F
+
+# Module PORTG
+ 'PORTG' : '$34', # Port G Data Register
+ 'DDRG' : '$33', # Port G Data Direction Register
+ 'PING' : '$32', # Port G Input Pins
+
+# Module JTAG
+ 'OCDR' : '$51', # On-Chip Debug Related Register
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_JTD': '$80', # JTAG Interface Disable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+
+# Module USI
+ 'USIDR' : '$ba', # USI Data Register
+ 'USISR' : '$b9', # USI Status Register
+ 'USISR_USISIF': '$80', # Start Condition Interrupt Flag
+ 'USISR_USIOIF': '$40', # Counter Overflow Interrupt Fla
+ 'USISR_USIPF': '$20', # Stop Condition Flag
+ 'USISR_USIDC': '$10', # Data Output Collision
+ 'USISR_USICNT': '$f', # USI Counter Value Bits
+ 'USICR' : '$b8', # USI Control Register
+ 'USICR_USISIE': '$80', # Start Condition Interrupt Enab
+ 'USICR_USIOIE': '$40', # Counter Overflow Interrupt Ena
+ 'USICR_USIWM': '$30', # USI Wire Mode Bits
+ 'USICR_USICS': '$c', # USI Clock Source Select Bits
+ 'USICR_USICLK': '$2', # Clock Strobe
+ 'USICR_USITC': '$1', # Toggle Clock Port Pin
+
+# Module AD_CONVERTER
+ 'ADMUX' : '$7c', # The ADC multiplexer Selection
+ 'ADMUX_REFS': '$c0', # Reference Selection Bits
+ 'ADMUX_ADLAR': '$20', # Left Adjust Result
+ 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
+ 'ADCSRA' : '$7a', # The ADC Control and Status reg
+ 'ADCSRA_ADEN': '$80', # ADC Enable
+ 'ADCSRA_ADSC': '$40', # ADC Start Conversion
+ 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
+ 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
+ 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
+ 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
+ 'ADC' : '$78', # ADC Data Register Bytes
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Sources
+ 'DIDR0' : '$7e', # Digital Input Disable Register
+ 'DIDR0_ADC7D': '$80', # ADC7 Digital input Disable
+ 'DIDR0_ADC6D': '$40', # ADC6 Digital input Disable
+ 'DIDR0_ADC5D': '$20', # ADC5 Digital input Disable
+ 'DIDR0_ADC4D': '$10', # ADC4 Digital input Disable
+ 'DIDR0_ADC3D': '$8', # ADC3 Digital input Disable
+ 'DIDR0_ADC2D': '$4', # ADC2 Digital input Disable
+ 'DIDR0_ADC1D': '$2', # ADC1 Digital input Disable
+ 'DIDR0_ADC0D': '$1', # ADC0 Digital input Disable
+
+# Module BOOT_LOAD
+ 'SPMCSR' : '$57', # Store Program Memory Control R
+ 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
+ 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
+ 'SPMCSR_RWWSRE': '$10', # Read While Write section read
+ 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
+ 'SPMCSR_PGWRT': '$4', # Page Write
+ 'SPMCSR_PGERS': '$2', # Page Erase
+ 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
+
+# Module USART0
+ 'UDR0' : '$c6', # USART I/O Data Register
+ 'UCSR0A' : '$c0', # USART Control and Status Regis
+ 'UCSR0A_RXC0': '$80', # USART Receive Complete
+ 'UCSR0A_TXC0': '$40', # USART Transmit Complete
+ 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
+ 'UCSR0A_FE0': '$10', # Framing Error
+ 'UCSR0A_DOR0': '$8', # Data OverRun
+ 'UCSR0A_UPE0': '$4', # USART Parity Error
+ 'UCSR0A_U2X0': '$2', # Double the USART Transmission
+ 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
+ 'UCSR0B' : '$c1', # USART Control and Status Regis
+ 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
+ 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
+ 'UCSR0B_UDRIE0': '$20', # USART Data Register Empty Inte
+ 'UCSR0B_RXEN0': '$10', # Receiver Enable
+ 'UCSR0B_TXEN0': '$8', # Transmitter Enable
+ 'UCSR0B_UCSZ02': '$4', # Character Size
+ 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
+ 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
+ 'UCSR0C' : '$c2', # USART Control and Status Regis
+ 'UCSR0C_UMSEL0': '$40', # USART Mode Select
+ 'UCSR0C_UPM0': '$30', # Parity Mode Bits
+ 'UCSR0C_USBS0': '$8', # Stop Bit Select
+ 'UCSR0C_UCSZ0': '$6', # Character Size
+ 'UCSR0C_UCPOL0': '$1', # Clock Polarity
+ 'UBRR0' : '$c4', # USART Baud Rate Register Byte
+
+# Module EXTERNAL_INTERRUPT
+ 'EICRA' : '$69', # External Interrupt Control Reg
+ 'EICRA_ISC01': '$2', # External Interrupt Sense Contr
+ 'EICRA_ISC00': '$1', # External Interrupt Sense Contr
+ 'EIMSK' : '$3d', # External Interrupt Mask Regist
+ 'EIMSK_PCIE': '$30', # Pin Change Interrupt Enables
+ 'EIMSK_INT0': '$1', # External Interrupt Request 0 E
+ 'EIFR' : '$3c', # External Interrupt Flag Regist
+ 'EIFR_PCIF': '$30', # Pin Change Interrupt Flags
+ 'EIFR_INTF0': '$1', # External Interrupt Flag 0
+ 'PCMSK1' : '$6c', # Pin Change Mask Register 1
+ 'PCMSK1_PCINT': '$ff', # Pin Change Enable Masks
+ 'PCMSK0' : '$6b', # Pin Change Mask Register 0
+ 'PCMSK0_PCINT': '$ff', # Pin Change Enable Masks
+
+# Module CPU
+ 'SREG' : '$5f', # Status Register
+ 'SREG_I': '$80', # Global Interrupt Enable
+ 'SREG_T': '$40', # Bit Copy Storage
+ 'SREG_H': '$20', # Half Carry Flag
+ 'SREG_S': '$10', # Sign Bit
+ 'SREG_V': '$8', # Two's Complement Overflow Flag
+ 'SREG_N': '$4', # Negative Flag
+ 'SREG_Z': '$2', # Zero Flag
+ 'SREG_C': '$1', # Carry Flag
+ 'SP' : '$5d', # Stack Pointer
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_PUD': '$10', # Pull-up disable
+ 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
+ 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+ 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
+ 'MCUSR_BORF': '$4', # Brown-out Reset Flag
+ 'MCUSR_EXTRF': '$2', # External Reset Flag
+ 'MCUSR_PORF': '$1', # Power-on reset flag
+ 'OSCCAL' : '$66', # Oscillator Calibration Value
+ 'CLKPR' : '$61', # Clock Prescale Register
+ 'CLKPR_CLKPCE': '$80', # Clock Prescaler Change Enable
+ 'CLKPR_CLKPS': '$f', # Clock Prescaler Select Bits
+ 'PRR' : '$64', # Power Reduction Register
+ 'PRR_PRTIM1': '$8', # Power Reduction Timer/Counter1
+ 'PRR_PRSPI': '$4', # Power Reduction Serial Periphe
+ 'PRR_PRUSART0': '$2', # Power Reduction USART
+ 'PRR_PRADC': '$1', # Power Reduction ADC
+ 'SMCR' : '$53', # Sleep Mode Control Register
+ 'SMCR_SM': '$e', # Sleep Mode Select bits
+ 'SMCR_SE': '$1', # Sleep Enable
+ 'GPIOR2' : '$4b', # General Purpose IO Register 2
+ 'GPIOR1' : '$4a', # General Purpose IO Register 1
+ 'GPIOR0' : '$3e', # General Purpose IO Register 0
+
+ '__amforth_dummy':'0'
+}
diff --git a/amforth-6.5/avr8/devices/atmega165a/atmega165a.frt b/amforth-6.5/avr8/devices/atmega165a/atmega165a.frt
new file mode 100644
index 0000000..8ed9a41
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega165a/atmega165a.frt
@@ -0,0 +1,280 @@
+\ Partname: ATmega165A
+\ generated automatically
+
+\ TIMER_COUNTER_0
+&68 constant TCCR0A \ Timer/Counter0 Control Register
+ $80 constant TCCR0A_FOC0A \ Force Output Compare
+ $40 constant TCCR0A_WGM00 \ Waveform Generation Mode 0
+ $30 constant TCCR0A_COM0A \ Compare Match Output Modes
+ $08 constant TCCR0A_WGM01 \ Waveform Generation Mode 1
+ $07 constant TCCR0A_CS0 \ Clock Selects
+&70 constant TCNT0 \ Timer/Counter0
+&71 constant OCR0A \ Timer/Counter0 Output Compare Register
+&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
+ $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match Interrupt Enable
+ $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
+&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
+ $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0
+ $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
+&67 constant GTCCR \ General Timer/Control Register
+ $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
+ $01 constant GTCCR_PSR310 \ Prescaler Reset Timer/Counter1 and Timer/Counter0
+\ TIMER_COUNTER_1
+&128 constant TCCR1A \ Timer/Counter1 Control Register A
+ $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
+ $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
+ $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
+&129 constant TCCR1B \ Timer/Counter1 Control Register B
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
+ $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
+&130 constant TCCR1C \ Timer/Counter 1 Control Register C
+ $80 constant TCCR1C_FOC1A \ Force Output Compare 1A
+ $40 constant TCCR1C_FOC1B \ Force Output Compare 1B
+&132 constant TCNT1 \ Timer/Counter1 Bytes
+&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
+&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
+&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
+&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
+ $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
+ $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
+ $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
+ $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
+&54 constant TIFR1 \ Timer/Counter1 Interrupt Flag register
+ $20 constant TIFR1_ICF1 \ Input Capture Flag 1
+ $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
+ $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
+ $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
+\ TIMER_COUNTER_2
+&176 constant TCCR2A \ Timer/Counter2 Control Register
+ $80 constant TCCR2A_FOC2A \ Force Output Compare A
+ $40 constant TCCR2A_WGM20 \ Waveform Generation Mode
+ $30 constant TCCR2A_COM2A \ Compare Output Mode bits
+ $08 constant TCCR2A_WGM21 \ Waveform Generation Mode
+ $07 constant TCCR2A_CS2 \ Clock Select bits
+&178 constant TCNT2 \ Timer/Counter2
+&179 constant OCR2A \ Timer/Counter2 Output Compare Register
+&112 constant TIMSK2 \ Timer/Counter2 Interrupt Mask register
+ $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match Interrupt Enable
+ $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
+&55 constant TIFR2 \ Timer/Counter2 Interrupt Flag Register
+ $02 constant TIFR2_OCF2A \ Timer/Counter2 Output Compare Flag 2
+ $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
+&182 constant ASSR \ Asynchronous Status Register
+ $10 constant ASSR_EXCLK \ Enable External Clock Interrupt
+ $08 constant ASSR_AS2 \ AS2: Asynchronous Timer/Counter2
+ $04 constant ASSR_TCN2UB \ TCN2UB: Timer/Counter2 Update Busy
+ $02 constant ASSR_OCR2UB \ Output Compare Register2 Update Busy
+ $01 constant ASSR_TCR2UB \ TCR2UB: Timer/Counter Control Register2 Update Busy
+\ WATCHDOG
+&96 constant WDTCR \ Watchdog Timer Control Register
+ $10 constant WDTCR_WDCE \ Watchdog Change Enable
+ $08 constant WDTCR_WDE \ Watch Dog Enable
+ $07 constant WDTCR_WDP \ Watch Dog Timer Prescaler bits
+\ EEPROM
+&65 constant EEAR \ EEPROM Address Register Bytes
+&64 constant EEDR \ EEPROM Data Register
+&63 constant EECR \ EEPROM Control Register
+ $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
+ $04 constant EECR_EEMWE \ EEPROM Master Write Enable
+ $02 constant EECR_EEWE \ EEPROM Write Enable
+ $01 constant EECR_EERE \ EEPROM Read Enable
+\ SPI
+&76 constant SPCR \ SPI Control Register
+ $80 constant SPCR_SPIE \ SPI Interrupt Enable
+ $40 constant SPCR_SPE \ SPI Enable
+ $20 constant SPCR_DORD \ Data Order
+ $10 constant SPCR_MSTR \ Master/Slave Select
+ $08 constant SPCR_CPOL \ Clock polarity
+ $04 constant SPCR_CPHA \ Clock Phase
+ $03 constant SPCR_SPR \ SPI Clock Rate Selects
+&77 constant SPSR \ SPI Status Register
+ $80 constant SPSR_SPIF \ SPI Interrupt Flag
+ $40 constant SPSR_WCOL \ Write Collision Flag
+ $01 constant SPSR_SPI2X \ Double SPI Speed Bit
+&78 constant SPDR \ SPI Data Register
+\ PORTA
+&34 constant PORTA \ Port A Data Register
+&33 constant DDRA \ Port A Data Direction Register
+&32 constant PINA \ Port A Input Pins
+\ PORTB
+&37 constant PORTB \ Port B Data Register
+&36 constant DDRB \ Port B Data Direction Register
+&35 constant PINB \ Port B Input Pins
+\ PORTC
+&40 constant PORTC \ Port C Data Register
+&39 constant DDRC \ Port C Data Direction Register
+&38 constant PINC \ Port C Input Pins
+\ PORTD
+&43 constant PORTD \ Port D Data Register
+&42 constant DDRD \ Port D Data Direction Register
+&41 constant PIND \ Port D Input Pins
+\ ANALOG_COMPARATOR
+&123 constant ADCSRB \ ADC Control and Status Register B
+ $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer Enable
+&80 constant ACSR \ Analog Comparator Control And Status Register
+ $80 constant ACSR_ACD \ Analog Comparator Disable
+ $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
+ $20 constant ACSR_ACO \ Analog Compare Output
+ $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
+ $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
+ $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
+ $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
+&127 constant DIDR1 \ Digital Input Disable Register 1
+ $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
+ $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
+\ PORTE
+&46 constant PORTE \ Data Register, Port E
+&45 constant DDRE \ Data Direction Register, Port E
+&44 constant PINE \ Input Pins, Port E
+\ PORTF
+&49 constant PORTF \ Data Register, Port F
+&48 constant DDRF \ Data Direction Register, Port F
+&47 constant PINF \ Input Pins, Port F
+\ PORTG
+&52 constant PORTG \ Port G Data Register
+&51 constant DDRG \ Port G Data Direction Register
+&50 constant PING \ Port G Input Pins
+\ JTAG
+&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
+&85 constant MCUCR \ MCU Control Register
+ $80 constant MCUCR_JTD \ JTAG Interface Disable
+&84 constant MCUSR \ MCU Status Register
+ $10 constant MCUSR_JTRF \ JTAG Reset Flag
+\ USI
+&186 constant USIDR \ USI Data Register
+&185 constant USISR \ USI Status Register
+ $80 constant USISR_USISIF \ Start Condition Interrupt Flag
+ $40 constant USISR_USIOIF \ Counter Overflow Interrupt Flag
+ $20 constant USISR_USIPF \ Stop Condition Flag
+ $10 constant USISR_USIDC \ Data Output Collision
+ $0F constant USISR_USICNT \ USI Counter Value Bits
+&184 constant USICR \ USI Control Register
+ $80 constant USICR_USISIE \ Start Condition Interrupt Enable
+ $40 constant USICR_USIOIE \ Counter Overflow Interrupt Enable
+ $30 constant USICR_USIWM \ USI Wire Mode Bits
+ $0C constant USICR_USICS \ USI Clock Source Select Bits
+ $02 constant USICR_USICLK \ Clock Strobe
+ $01 constant USICR_USITC \ Toggle Clock Port Pin
+\ AD_CONVERTER
+&124 constant ADMUX \ The ADC multiplexer Selection Register
+ $C0 constant ADMUX_REFS \ Reference Selection Bits
+ $20 constant ADMUX_ADLAR \ Left Adjust Result
+ $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
+&122 constant ADCSRA \ The ADC Control and Status register
+ $80 constant ADCSRA_ADEN \ ADC Enable
+ $40 constant ADCSRA_ADSC \ ADC Start Conversion
+ $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
+ $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
+ $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
+ $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
+&120 constant ADC \ ADC Data Register Bytes
+&126 constant DIDR0 \ Digital Input Disable Register 0
+ $80 constant DIDR0_ADC7D \ ADC7 Digital input Disable
+ $40 constant DIDR0_ADC6D \ ADC6 Digital input Disable
+ $20 constant DIDR0_ADC5D \ ADC5 Digital input Disable
+ $10 constant DIDR0_ADC4D \ ADC4 Digital input Disable
+ $08 constant DIDR0_ADC3D \ ADC3 Digital input Disable
+ $04 constant DIDR0_ADC2D \ ADC2 Digital input Disable
+ $02 constant DIDR0_ADC1D \ ADC1 Digital input Disable
+ $01 constant DIDR0_ADC0D \ ADC0 Digital input Disable
+\ BOOT_LOAD
+&87 constant SPMCSR \ Store Program Memory Control Register
+ $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
+ $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
+ $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
+ $04 constant SPMCSR_PGWRT \ Page Write
+ $02 constant SPMCSR_PGERS \ Page Erase
+ $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
+\ USART0
+&198 constant UDR0 \ USART I/O Data Register
+&192 constant UCSR0A \ USART Control and Status Register A
+ $80 constant UCSR0A_RXC0 \ USART Receive Complete
+ $40 constant UCSR0A_TXC0 \ USART Transmit Complete
+ $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
+ $10 constant UCSR0A_FE0 \ Framing Error
+ $08 constant UCSR0A_DOR0 \ Data OverRun
+ $04 constant UCSR0A_UPE0 \ USART Parity Error
+ $02 constant UCSR0A_U2X0 \ Double the USART Transmission Speed
+ $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
+&193 constant UCSR0B \ USART Control and Status Register B
+ $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
+ $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
+ $20 constant UCSR0B_UDRIE0 \ USART Data Register Empty Interrupt Enable
+ $10 constant UCSR0B_RXEN0 \ Receiver Enable
+ $08 constant UCSR0B_TXEN0 \ Transmitter Enable
+ $04 constant UCSR0B_UCSZ02 \ Character Size
+ $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
+ $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
+&194 constant UCSR0C \ USART Control and Status Register C
+ $40 constant UCSR0C_UMSEL0 \ USART Mode Select
+ $30 constant UCSR0C_UPM0 \ Parity Mode Bits
+ $08 constant UCSR0C_USBS0 \ Stop Bit Select
+ $06 constant UCSR0C_UCSZ0 \ Character Size
+ $01 constant UCSR0C_UCPOL0 \ Clock Polarity
+&196 constant UBRR0 \ USART Baud Rate Register Bytes
+\ EXTERNAL_INTERRUPT
+&105 constant EICRA \ External Interrupt Control Register
+ $02 constant EICRA_ISC01 \ External Interrupt Sense Control 0 Bit 1
+ $01 constant EICRA_ISC00 \ External Interrupt Sense Control 0 Bit 0
+&61 constant EIMSK \ External Interrupt Mask Register
+ $30 constant EIMSK_PCIE \ Pin Change Interrupt Enables
+ $01 constant EIMSK_INT0 \ External Interrupt Request 0 Enable
+&60 constant EIFR \ External Interrupt Flag Register
+ $30 constant EIFR_PCIF \ Pin Change Interrupt Flags
+ $01 constant EIFR_INTF0 \ External Interrupt Flag 0
+&108 constant PCMSK1 \ Pin Change Mask Register 1
+ $FF constant PCMSK1_PCINT \ Pin Change Enable Masks
+&107 constant PCMSK0 \ Pin Change Mask Register 0
+ $FF constant PCMSK0_PCINT \ Pin Change Enable Masks
+\ CPU
+&95 constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ $08 constant SREG_V \ Two's Complement Overflow Flag
+ $04 constant SREG_N \ Negative Flag
+ $02 constant SREG_Z \ Zero Flag
+ $01 constant SREG_C \ Carry Flag
+&93 constant SP \ Stack Pointer
+&102 constant OSCCAL \ Oscillator Calibration Value
+&97 constant CLKPR \ Clock Prescale Register
+ $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable
+ $0F constant CLKPR_CLKPS \ Clock Prescaler Select Bits
+&100 constant PRR \ Power Reduction Register
+ $08 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
+ $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
+ $02 constant PRR_PRUSART0 \ Power Reduction USART
+ $01 constant PRR_PRADC \ Power Reduction ADC
+&83 constant SMCR \ Sleep Mode Control Register
+ $0E constant SMCR_SM \ Sleep Mode Select bits
+ $01 constant SMCR_SE \ Sleep Enable
+&75 constant GPIOR2 \ General Purpose IO Register 2
+&74 constant GPIOR1 \ General Purpose IO Register 1
+&62 constant GPIOR0 \ General Purpose IO Register 0
+
+\ Interrupts
+&2 constant INT0Addr \ External Interrupt Request 0
+&4 constant PCINT0Addr \ Pin Change Interrupt Request 0
+&6 constant PCINT1Addr \ Pin Change Interrupt Request 1
+&8 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
+&10 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
+&12 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+&14 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
+&16 constant TIMER1_COMPBAddr \ Timer/Counter Compare Match B
+&18 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+&20 constant TIMER0_COMPAddr \ Timer/Counter0 Compare Match
+&22 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
+&24 constant SPI__STCAddr \ SPI Serial Transfer Complete
+&26 constant USART0__RXAddr \ USART0, Rx Complete
+&28 constant USART0__UDREAddr \ USART0 Data register Empty
+&30 constant USART0__TXAddr \ USART0, Tx Complete
+&32 constant USI_STARTAddr \ USI Start Condition
+&34 constant USI_OVERFLOWAddr \ USI Overflow
+&36 constant ANALOG_COMPAddr \ Analog Comparator
+&38 constant ADCAddr \ ADC Conversion Complete
+&40 constant EE_READYAddr \ EEPROM Ready
+&42 constant SPM_READYAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/atmega165a/device.asm b/amforth-6.5/avr8/devices/atmega165a/device.asm
new file mode 100644
index 0000000..f060f41
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega165a/device.asm
@@ -0,0 +1,106 @@
+; Partname: ATmega165A
+; generated automatically, do not edit
+
+.nolist
+ .include "m165Adef.inc"
+.list
+
+.equ ramstart = 256
+.equ CELLSIZE = 2
+.macro readflashcell
+ lsl zl
+ rol zh
+ lpm @0, Z+
+ lpm @1, Z+
+.endmacro
+.macro writeflashcell
+ lsl zl
+ rol zh
+.endmacro
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_TIMER_COUNTER_2 = 0
+.set WANT_WATCHDOG = 0
+.set WANT_EEPROM = 0
+.set WANT_SPI = 0
+.set WANT_PORTA = 0
+.set WANT_PORTB = 0
+.set WANT_PORTC = 0
+.set WANT_PORTD = 0
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_PORTE = 0
+.set WANT_PORTF = 0
+.set WANT_PORTG = 0
+.set WANT_JTAG = 0
+.set WANT_USI = 0
+.set WANT_AD_CONVERTER = 0
+.set WANT_BOOT_LOAD = 0
+.set WANT_USART0 = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_CPU = 0
+.equ intvecsize = 2 ; please verify; flash size: 16384 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.org 2
+ rcall isr ; External Interrupt Request 0
+.org 4
+ rcall isr ; Pin Change Interrupt Request 0
+.org 6
+ rcall isr ; Pin Change Interrupt Request 1
+.org 8
+ rcall isr ; Timer/Counter2 Compare Match
+.org 10
+ rcall isr ; Timer/Counter2 Overflow
+.org 12
+ rcall isr ; Timer/Counter1 Capture Event
+.org 14
+ rcall isr ; Timer/Counter1 Compare Match A
+.org 16
+ rcall isr ; Timer/Counter Compare Match B
+.org 18
+ rcall isr ; Timer/Counter1 Overflow
+.org 20
+ rcall isr ; Timer/Counter0 Compare Match
+.org 22
+ rcall isr ; Timer/Counter0 Overflow
+.org 24
+ rcall isr ; SPI Serial Transfer Complete
+.org 26
+ rcall isr ; USART0, Rx Complete
+.org 28
+ rcall isr ; USART0 Data register Empty
+.org 30
+ rcall isr ; USART0, Tx Complete
+.org 32
+ rcall isr ; USI Start Condition
+.org 34
+ rcall isr ; USI Overflow
+.org 36
+ rcall isr ; Analog Comparator
+.org 38
+ rcall isr ; ADC Conversion Complete
+.org 40
+ rcall isr ; EEPROM Ready
+.org 42
+ rcall isr ; Store Program Memory Read
+.equ INTVECTORS = 22
+.nooverlap
+
+; compatability layer (maybe empty)
+.equ EEPE = EEWE
+.equ EEMPE = EEMWE
+
+; controller data area, environment query mcu-info
+mcu_info:
+mcu_ramsize:
+ .dw 1024
+mcu_eepromsize:
+ .dw 512
+mcu_maxdp:
+ .dw 14336
+mcu_numints:
+ .dw 22
+mcu_name:
+ .dw 10
+ .db "ATmega165A"
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega165a/device.inc b/amforth-6.5/avr8/devices/atmega165a/device.inc
new file mode 100644
index 0000000..8fb0e73
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega165a/device.inc
@@ -0,0 +1,1050 @@
+; Partname: ATmega165A
+; generated automatically, no not edit
+
+.if WANT_TIMER_COUNTER_0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Control Register
+VE_TCCR0A:
+ .dw $ff06
+ .db "TCCR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0A
+XT_TCCR0A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0A:
+ .dw 68
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw 70
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0A:
+ .dw $ff05
+ .db "OCR0A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0A
+XT_OCR0A:
+ .dw PFA_DOVARIABLE
+PFA_OCR0A:
+ .dw 71
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Mask Register
+VE_TIMSK0:
+ .dw $ff06
+ .db "TIMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK0
+XT_TIMSK0:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK0:
+ .dw 110
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Flag register
+VE_TIFR0:
+ .dw $ff05
+ .db "TIFR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR0
+XT_TIFR0:
+ .dw PFA_DOVARIABLE
+PFA_TIFR0:
+ .dw 53
+; ( -- addr ) System Constant
+; R( -- )
+; General Timer/Control Register
+VE_GTCCR:
+ .dw $ff05
+ .db "GTCCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GTCCR
+XT_GTCCR:
+ .dw PFA_DOVARIABLE
+PFA_GTCCR:
+ .dw 67
+
+.endif
+.if WANT_TIMER_COUNTER_1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw 128
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw 129
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter 1 Control Register C
+VE_TCCR1C:
+ .dw $ff06
+ .db "TCCR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1C
+XT_TCCR1C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1C:
+ .dw 130
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Bytes
+VE_TCNT1:
+ .dw $ff05
+ .db "TCNT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1
+XT_TCNT1:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1:
+ .dw 132
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register A Bytes
+VE_OCR1A:
+ .dw $ff05
+ .db "OCR1A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1A
+XT_OCR1A:
+ .dw PFA_DOVARIABLE
+PFA_OCR1A:
+ .dw 136
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register B Bytes
+VE_OCR1B:
+ .dw $ff05
+ .db "OCR1B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1B
+XT_OCR1B:
+ .dw PFA_DOVARIABLE
+PFA_OCR1B:
+ .dw 138
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Bytes
+VE_ICR1:
+ .dw $ff04
+ .db "ICR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1
+XT_ICR1:
+ .dw PFA_DOVARIABLE
+PFA_ICR1:
+ .dw 134
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Mask Register
+VE_TIMSK1:
+ .dw $ff06
+ .db "TIMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK1
+XT_TIMSK1:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK1:
+ .dw 111
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Flag register
+VE_TIFR1:
+ .dw $ff05
+ .db "TIFR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR1
+XT_TIFR1:
+ .dw PFA_DOVARIABLE
+PFA_TIFR1:
+ .dw 54
+
+.endif
+.if WANT_TIMER_COUNTER_2 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register
+VE_TCCR2A:
+ .dw $ff06
+ .db "TCCR2A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2A
+XT_TCCR2A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2A:
+ .dw 176
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2
+VE_TCNT2:
+ .dw $ff05
+ .db "TCNT2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT2
+XT_TCNT2:
+ .dw PFA_DOVARIABLE
+PFA_TCNT2:
+ .dw 178
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register
+VE_OCR2A:
+ .dw $ff05
+ .db "OCR2A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2A
+XT_OCR2A:
+ .dw PFA_DOVARIABLE
+PFA_OCR2A:
+ .dw 179
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Interrupt Mask register
+VE_TIMSK2:
+ .dw $ff06
+ .db "TIMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK2
+XT_TIMSK2:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK2:
+ .dw 112
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Interrupt Flag Register
+VE_TIFR2:
+ .dw $ff05
+ .db "TIFR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR2
+XT_TIFR2:
+ .dw PFA_DOVARIABLE
+PFA_TIFR2:
+ .dw 55
+; ( -- addr ) System Constant
+; R( -- )
+; Asynchronous Status Register
+VE_ASSR:
+ .dw $ff04
+ .db "ASSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ASSR
+XT_ASSR:
+ .dw PFA_DOVARIABLE
+PFA_ASSR:
+ .dw 182
+
+.endif
+.if WANT_WATCHDOG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCR:
+ .dw $ff05
+ .db "WDTCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCR
+XT_WDTCR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCR:
+ .dw 96
+
+.endif
+.if WANT_EEPROM == 1
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Address Register Bytes
+VE_EEAR:
+ .dw $ff04
+ .db "EEAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEAR
+XT_EEAR:
+ .dw PFA_DOVARIABLE
+PFA_EEAR:
+ .dw 65
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw 64
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw 63
+
+.endif
+.if WANT_SPI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR:
+ .dw $ff04
+ .db "SPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR
+XT_SPCR:
+ .dw PFA_DOVARIABLE
+PFA_SPCR:
+ .dw 76
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR:
+ .dw $ff04
+ .db "SPSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR
+XT_SPSR:
+ .dw PFA_DOVARIABLE
+PFA_SPSR:
+ .dw 77
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR:
+ .dw $ff04
+ .db "SPDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR
+XT_SPDR:
+ .dw PFA_DOVARIABLE
+PFA_SPDR:
+ .dw 78
+
+.endif
+.if WANT_PORTA == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Register
+VE_PORTA:
+ .dw $ff05
+ .db "PORTA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTA
+XT_PORTA:
+ .dw PFA_DOVARIABLE
+PFA_PORTA:
+ .dw 34
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Direction Register
+VE_DDRA:
+ .dw $ff04
+ .db "DDRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRA
+XT_DDRA:
+ .dw PFA_DOVARIABLE
+PFA_DDRA:
+ .dw 33
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Input Pins
+VE_PINA:
+ .dw $ff04
+ .db "PINA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINA
+XT_PINA:
+ .dw PFA_DOVARIABLE
+PFA_PINA:
+ .dw 32
+
+.endif
+.if WANT_PORTB == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw 37
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw 36
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw 35
+
+.endif
+.if WANT_PORTC == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Register
+VE_PORTC:
+ .dw $ff05
+ .db "PORTC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTC
+XT_PORTC:
+ .dw PFA_DOVARIABLE
+PFA_PORTC:
+ .dw 40
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Direction Register
+VE_DDRC:
+ .dw $ff04
+ .db "DDRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRC
+XT_DDRC:
+ .dw PFA_DOVARIABLE
+PFA_DDRC:
+ .dw 39
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Input Pins
+VE_PINC:
+ .dw $ff04
+ .db "PINC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINC
+XT_PINC:
+ .dw PFA_DOVARIABLE
+PFA_PINC:
+ .dw 38
+
+.endif
+.if WANT_PORTD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw 43
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw 42
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw 41
+
+.endif
+.if WANT_ANALOG_COMPARATOR == 1
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Control and Status Register B
+VE_ADCSRB:
+ .dw $ff06
+ .db "ADCSRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRB
+XT_ADCSRB:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRB:
+ .dw 123
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Control And Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw 80
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 1
+VE_DIDR1:
+ .dw $ff05
+ .db "DIDR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR1
+XT_DIDR1:
+ .dw PFA_DOVARIABLE
+PFA_DIDR1:
+ .dw 127
+
+.endif
+.if WANT_PORTE == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port E
+VE_PORTE:
+ .dw $ff05
+ .db "PORTE",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTE
+XT_PORTE:
+ .dw PFA_DOVARIABLE
+PFA_PORTE:
+ .dw 46
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port E
+VE_DDRE:
+ .dw $ff04
+ .db "DDRE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRE
+XT_DDRE:
+ .dw PFA_DOVARIABLE
+PFA_DDRE:
+ .dw 45
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port E
+VE_PINE:
+ .dw $ff04
+ .db "PINE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINE
+XT_PINE:
+ .dw PFA_DOVARIABLE
+PFA_PINE:
+ .dw 44
+
+.endif
+.if WANT_PORTF == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port F
+VE_PORTF:
+ .dw $ff05
+ .db "PORTF",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTF
+XT_PORTF:
+ .dw PFA_DOVARIABLE
+PFA_PORTF:
+ .dw 49
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port F
+VE_DDRF:
+ .dw $ff04
+ .db "DDRF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRF
+XT_DDRF:
+ .dw PFA_DOVARIABLE
+PFA_DDRF:
+ .dw 48
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port F
+VE_PINF:
+ .dw $ff04
+ .db "PINF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINF
+XT_PINF:
+ .dw PFA_DOVARIABLE
+PFA_PINF:
+ .dw 47
+
+.endif
+.if WANT_PORTG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Data Register
+VE_PORTG:
+ .dw $ff05
+ .db "PORTG",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTG
+XT_PORTG:
+ .dw PFA_DOVARIABLE
+PFA_PORTG:
+ .dw 52
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Data Direction Register
+VE_DDRG:
+ .dw $ff04
+ .db "DDRG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRG
+XT_DDRG:
+ .dw PFA_DOVARIABLE
+PFA_DDRG:
+ .dw 51
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Input Pins
+VE_PING:
+ .dw $ff04
+ .db "PING"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PING
+XT_PING:
+ .dw PFA_DOVARIABLE
+PFA_PING:
+ .dw 50
+
+.endif
+.if WANT_JTAG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; On-Chip Debug Related Register in I/O Memory
+VE_OCDR:
+ .dw $ff04
+ .db "OCDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCDR
+XT_OCDR:
+ .dw PFA_DOVARIABLE
+PFA_OCDR:
+ .dw 81
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw 85
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Status Register
+VE_MCUSR:
+ .dw $ff05
+ .db "MCUSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUSR
+XT_MCUSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUSR:
+ .dw 84
+
+.endif
+.if WANT_USI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USI Data Register
+VE_USIDR:
+ .dw $ff05
+ .db "USIDR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USIDR
+XT_USIDR:
+ .dw PFA_DOVARIABLE
+PFA_USIDR:
+ .dw 186
+; ( -- addr ) System Constant
+; R( -- )
+; USI Status Register
+VE_USISR:
+ .dw $ff05
+ .db "USISR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USISR
+XT_USISR:
+ .dw PFA_DOVARIABLE
+PFA_USISR:
+ .dw 185
+; ( -- addr ) System Constant
+; R( -- )
+; USI Control Register
+VE_USICR:
+ .dw $ff05
+ .db "USICR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USICR
+XT_USICR:
+ .dw PFA_DOVARIABLE
+PFA_USICR:
+ .dw 184
+
+.endif
+.if WANT_AD_CONVERTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC multiplexer Selection Register
+VE_ADMUX:
+ .dw $ff05
+ .db "ADMUX",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADMUX
+XT_ADMUX:
+ .dw PFA_DOVARIABLE
+PFA_ADMUX:
+ .dw 124
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register
+VE_ADCSRA:
+ .dw $ff06
+ .db "ADCSRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRA
+XT_ADCSRA:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRA:
+ .dw 122
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register Bytes
+VE_ADC:
+ .dw $ff03
+ .db "ADC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADC
+XT_ADC:
+ .dw PFA_DOVARIABLE
+PFA_ADC:
+ .dw 120
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 0
+VE_DIDR0:
+ .dw $ff05
+ .db "DIDR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR0
+XT_DIDR0:
+ .dw PFA_DOVARIABLE
+PFA_DIDR0:
+ .dw 126
+
+.endif
+.if WANT_BOOT_LOAD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control Register
+VE_SPMCSR:
+ .dw $ff06
+ .db "SPMCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCSR
+XT_SPMCSR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCSR:
+ .dw 87
+
+.endif
+.if WANT_USART0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR0:
+ .dw $ff04
+ .db "UDR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR0
+XT_UDR0:
+ .dw PFA_DOVARIABLE
+PFA_UDR0:
+ .dw 198
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR0A:
+ .dw $ff06
+ .db "UCSR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0A
+XT_UCSR0A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0A:
+ .dw 192
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR0B:
+ .dw $ff06
+ .db "UCSR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0B
+XT_UCSR0B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0B:
+ .dw 193
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR0C:
+ .dw $ff06
+ .db "UCSR0C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0C
+XT_UCSR0C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0C:
+ .dw 194
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Bytes
+VE_UBRR0:
+ .dw $ff05
+ .db "UBRR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR0
+XT_UBRR0:
+ .dw PFA_DOVARIABLE
+PFA_UBRR0:
+ .dw 196
+
+.endif
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register
+VE_EICRA:
+ .dw $ff05
+ .db "EICRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRA
+XT_EICRA:
+ .dw PFA_DOVARIABLE
+PFA_EICRA:
+ .dw 105
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Mask Register
+VE_EIMSK:
+ .dw $ff05
+ .db "EIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIMSK
+XT_EIMSK:
+ .dw PFA_DOVARIABLE
+PFA_EIMSK:
+ .dw 61
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Flag Register
+VE_EIFR:
+ .dw $ff04
+ .db "EIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIFR
+XT_EIFR:
+ .dw PFA_DOVARIABLE
+PFA_EIFR:
+ .dw 60
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 1
+VE_PCMSK1:
+ .dw $ff06
+ .db "PCMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK1
+XT_PCMSK1:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK1:
+ .dw 108
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 0
+VE_PCMSK0:
+ .dw $ff06
+ .db "PCMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK0
+XT_PCMSK0:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK0:
+ .dw 107
+
+.endif
+.if WANT_CPU == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw 95
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer
+VE_SP:
+ .dw $ff02
+ .db "SP"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SP
+XT_SP:
+ .dw PFA_DOVARIABLE
+PFA_SP:
+ .dw 93
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Calibration Value
+VE_OSCCAL:
+ .dw $ff06
+ .db "OSCCAL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSCCAL
+XT_OSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_OSCCAL:
+ .dw 102
+; ( -- addr ) System Constant
+; R( -- )
+; Clock Prescale Register
+VE_CLKPR:
+ .dw $ff05
+ .db "CLKPR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKPR
+XT_CLKPR:
+ .dw PFA_DOVARIABLE
+PFA_CLKPR:
+ .dw 97
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register
+VE_PRR:
+ .dw $ff03
+ .db "PRR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR
+XT_PRR:
+ .dw PFA_DOVARIABLE
+PFA_PRR:
+ .dw 100
+; ( -- addr ) System Constant
+; R( -- )
+; Sleep Mode Control Register
+VE_SMCR:
+ .dw $ff04
+ .db "SMCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SMCR
+XT_SMCR:
+ .dw PFA_DOVARIABLE
+PFA_SMCR:
+ .dw 83
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 2
+VE_GPIOR2:
+ .dw $ff06
+ .db "GPIOR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR2
+XT_GPIOR2:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR2:
+ .dw 75
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 1
+VE_GPIOR1:
+ .dw $ff06
+ .db "GPIOR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR1
+XT_GPIOR1:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR1:
+ .dw 74
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 0
+VE_GPIOR0:
+ .dw $ff06
+ .db "GPIOR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR0
+XT_GPIOR0:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR0:
+ .dw 62
+
+.endif
diff --git a/amforth-6.5/avr8/devices/atmega165a/device.py b/amforth-6.5/avr8/devices/atmega165a/device.py
new file mode 100644
index 0000000..e5790dd
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega165a/device.py
@@ -0,0 +1,258 @@
+# Partname: ATmega165A
+# generated automatically, do not edit
+MCUREGS = {
+ 'TCCR0A': '&68',
+ 'TCCR0A_FOC0A': '$80',
+ 'TCCR0A_WGM00': '$40',
+ 'TCCR0A_COM0A': '$30',
+ 'TCCR0A_WGM01': '$08',
+ 'TCCR0A_CS0': '$07',
+ 'TCNT0': '&70',
+ 'OCR0A': '&71',
+ 'TIMSK0': '&110',
+ 'TIMSK0_OCIE0A': '$02',
+ 'TIMSK0_TOIE0': '$01',
+ 'TIFR0': '&53',
+ 'TIFR0_OCF0A': '$02',
+ 'TIFR0_TOV0': '$01',
+ 'GTCCR': '&67',
+ 'GTCCR_TSM': '$80',
+ 'GTCCR_PSR310': '$01',
+ 'TCCR1A': '&128',
+ 'TCCR1A_COM1A': '$C0',
+ 'TCCR1A_COM1B': '$30',
+ 'TCCR1A_WGM1': '$03',
+ 'TCCR1B': '&129',
+ 'TCCR1B_ICNC1': '$80',
+ 'TCCR1B_ICES1': '$40',
+ 'TCCR1B_WGM1': '$18',
+ 'TCCR1B_CS1': '$07',
+ 'TCCR1C': '&130',
+ 'TCCR1C_FOC1A': '$80',
+ 'TCCR1C_FOC1B': '$40',
+ 'TCNT1': '&132',
+ 'OCR1A': '&136',
+ 'OCR1B': '&138',
+ 'ICR1': '&134',
+ 'TIMSK1': '&111',
+ 'TIMSK1_ICIE1': '$20',
+ 'TIMSK1_OCIE1B': '$04',
+ 'TIMSK1_OCIE1A': '$02',
+ 'TIMSK1_TOIE1': '$01',
+ 'TIFR1': '&54',
+ 'TIFR1_ICF1': '$20',
+ 'TIFR1_OCF1B': '$04',
+ 'TIFR1_OCF1A': '$02',
+ 'TIFR1_TOV1': '$01',
+ 'TCCR2A': '&176',
+ 'TCCR2A_FOC2A': '$80',
+ 'TCCR2A_WGM20': '$40',
+ 'TCCR2A_COM2A': '$30',
+ 'TCCR2A_WGM21': '$08',
+ 'TCCR2A_CS2': '$07',
+ 'TCNT2': '&178',
+ 'OCR2A': '&179',
+ 'TIMSK2': '&112',
+ 'TIMSK2_OCIE2A': '$02',
+ 'TIMSK2_TOIE2': '$01',
+ 'TIFR2': '&55',
+ 'TIFR2_OCF2A': '$02',
+ 'TIFR2_TOV2': '$01',
+ 'ASSR': '&182',
+ 'ASSR_EXCLK': '$10',
+ 'ASSR_AS2': '$08',
+ 'ASSR_TCN2UB': '$04',
+ 'ASSR_OCR2UB': '$02',
+ 'ASSR_TCR2UB': '$01',
+ 'WDTCR': '&96',
+ 'WDTCR_WDCE': '$10',
+ 'WDTCR_WDE': '$08',
+ 'WDTCR_WDP': '$07',
+ 'EEAR': '&65',
+ 'EEDR': '&64',
+ 'EECR': '&63',
+ 'EECR_EERIE': '$08',
+ 'EECR_EEMWE': '$04',
+ 'EECR_EEWE': '$02',
+ 'EECR_EERE': '$01',
+ 'SPCR': '&76',
+ 'SPCR_SPIE': '$80',
+ 'SPCR_SPE': '$40',
+ 'SPCR_DORD': '$20',
+ 'SPCR_MSTR': '$10',
+ 'SPCR_CPOL': '$08',
+ 'SPCR_CPHA': '$04',
+ 'SPCR_SPR': '$03',
+ 'SPSR': '&77',
+ 'SPSR_SPIF': '$80',
+ 'SPSR_WCOL': '$40',
+ 'SPSR_SPI2X': '$01',
+ 'SPDR': '&78',
+ 'PORTA': '&34',
+ 'DDRA': '&33',
+ 'PINA': '&32',
+ 'PORTB': '&37',
+ 'DDRB': '&36',
+ 'PINB': '&35',
+ 'PORTC': '&40',
+ 'DDRC': '&39',
+ 'PINC': '&38',
+ 'PORTD': '&43',
+ 'DDRD': '&42',
+ 'PIND': '&41',
+ 'ADCSRB': '&123',
+ 'ADCSRB_ACME': '$40',
+ 'ACSR': '&80',
+ 'ACSR_ACD': '$80',
+ 'ACSR_ACBG': '$40',
+ 'ACSR_ACO': '$20',
+ 'ACSR_ACI': '$10',
+ 'ACSR_ACIE': '$08',
+ 'ACSR_ACIC': '$04',
+ 'ACSR_ACIS': '$03',
+ 'DIDR1': '&127',
+ 'DIDR1_AIN1D': '$02',
+ 'DIDR1_AIN0D': '$01',
+ 'PORTE': '&46',
+ 'DDRE': '&45',
+ 'PINE': '&44',
+ 'PORTF': '&49',
+ 'DDRF': '&48',
+ 'PINF': '&47',
+ 'PORTG': '&52',
+ 'DDRG': '&51',
+ 'PING': '&50',
+ 'OCDR': '&81',
+ 'MCUCR': '&85',
+ 'MCUCR_JTD': '$80',
+ 'MCUSR': '&84',
+ 'MCUSR_JTRF': '$10',
+ 'USIDR': '&186',
+ 'USISR': '&185',
+ 'USISR_USISIF': '$80',
+ 'USISR_USIOIF': '$40',
+ 'USISR_USIPF': '$20',
+ 'USISR_USIDC': '$10',
+ 'USISR_USICNT': '$0F',
+ 'USICR': '&184',
+ 'USICR_USISIE': '$80',
+ 'USICR_USIOIE': '$40',
+ 'USICR_USIWM': '$30',
+ 'USICR_USICS': '$0C',
+ 'USICR_USICLK': '$02',
+ 'USICR_USITC': '$01',
+ 'ADMUX': '&124',
+ 'ADMUX_REFS': '$C0',
+ 'ADMUX_ADLAR': '$20',
+ 'ADMUX_MUX': '$1F',
+ 'ADCSRA': '&122',
+ 'ADCSRA_ADEN': '$80',
+ 'ADCSRA_ADSC': '$40',
+ 'ADCSRA_ADATE': '$20',
+ 'ADCSRA_ADIF': '$10',
+ 'ADCSRA_ADIE': '$08',
+ 'ADCSRA_ADPS': '$07',
+ 'ADC': '&120',
+ 'DIDR0': '&126',
+ 'DIDR0_ADC7D': '$80',
+ 'DIDR0_ADC6D': '$40',
+ 'DIDR0_ADC5D': '$20',
+ 'DIDR0_ADC4D': '$10',
+ 'DIDR0_ADC3D': '$08',
+ 'DIDR0_ADC2D': '$04',
+ 'DIDR0_ADC1D': '$02',
+ 'DIDR0_ADC0D': '$01',
+ 'SPMCSR': '&87',
+ 'SPMCSR_SPMIE': '$80',
+ 'SPMCSR_RWWSB': '$40',
+ 'SPMCSR_RWWSRE': '$10',
+ 'SPMCSR_BLBSET': '$08',
+ 'SPMCSR_PGWRT': '$04',
+ 'SPMCSR_PGERS': '$02',
+ 'SPMCSR_SPMEN': '$01',
+ 'UDR0': '&198',
+ 'UCSR0A': '&192',
+ 'UCSR0A_RXC0': '$80',
+ 'UCSR0A_TXC0': '$40',
+ 'UCSR0A_UDRE0': '$20',
+ 'UCSR0A_FE0': '$10',
+ 'UCSR0A_DOR0': '$08',
+ 'UCSR0A_UPE0': '$04',
+ 'UCSR0A_U2X0': '$02',
+ 'UCSR0A_MPCM0': '$01',
+ 'UCSR0B': '&193',
+ 'UCSR0B_RXCIE0': '$80',
+ 'UCSR0B_TXCIE0': '$40',
+ 'UCSR0B_UDRIE0': '$20',
+ 'UCSR0B_RXEN0': '$10',
+ 'UCSR0B_TXEN0': '$08',
+ 'UCSR0B_UCSZ02': '$04',
+ 'UCSR0B_RXB80': '$02',
+ 'UCSR0B_TXB80': '$01',
+ 'UCSR0C': '&194',
+ 'UCSR0C_UMSEL0': '$40',
+ 'UCSR0C_UPM0': '$30',
+ 'UCSR0C_USBS0': '$08',
+ 'UCSR0C_UCSZ0': '$06',
+ 'UCSR0C_UCPOL0': '$01',
+ 'UBRR0': '&196',
+ 'EICRA': '&105',
+ 'EICRA_ISC01': '$02',
+ 'EICRA_ISC00': '$01',
+ 'EIMSK': '&61',
+ 'EIMSK_PCIE': '$30',
+ 'EIMSK_INT0': '$01',
+ 'EIFR': '&60',
+ 'EIFR_PCIF': '$30',
+ 'EIFR_INTF0': '$01',
+ 'PCMSK1': '&108',
+ 'PCMSK1_PCINT': '$FF',
+ 'PCMSK0': '&107',
+ 'PCMSK0_PCINT': '$FF',
+ 'SREG': '&95',
+ 'SREG_I': '$80',
+ 'SREG_T': '$40',
+ 'SREG_H': '$20',
+ 'SREG_S': '$10',
+ 'SREG_V': '$08',
+ 'SREG_N': '$04',
+ 'SREG_Z': '$02',
+ 'SREG_C': '$01',
+ 'SP': '&93',
+ 'OSCCAL': '&102',
+ 'CLKPR': '&97',
+ 'CLKPR_CLKPCE': '$80',
+ 'CLKPR_CLKPS': '$0F',
+ 'PRR': '&100',
+ 'PRR_PRTIM1': '$08',
+ 'PRR_PRSPI': '$04',
+ 'PRR_PRUSART0': '$02',
+ 'PRR_PRADC': '$01',
+ 'SMCR': '&83',
+ 'SMCR_SM': '$0E',
+ 'SMCR_SE': '$01',
+ 'GPIOR2': '&75',
+ 'GPIOR1': '&74',
+ 'GPIOR0': '&62',
+ 'INT0Addr': '2',
+ 'PCINT0Addr': '4',
+ 'PCINT1Addr': '6',
+ 'TIMER2_COMPAddr': '8',
+ 'TIMER2_OVFAddr': '10',
+ 'TIMER1_CAPTAddr': '12',
+ 'TIMER1_COMPAAddr': '14',
+ 'TIMER1_COMPBAddr': '16',
+ 'TIMER1_OVFAddr': '18',
+ 'TIMER0_COMPAddr': '20',
+ 'TIMER0_OVFAddr': '22',
+ 'SPI__STCAddr': '24',
+ 'USART0__RXAddr': '26',
+ 'USART0__UDREAddr': '28',
+ 'USART0__TXAddr': '30',
+ 'USI_STARTAddr': '32',
+ 'USI_OVERFLOWAddr': '34',
+ 'ANALOG_COMPAddr': '36',
+ 'ADCAddr': '38',
+ 'EE_READYAddr': '40',
+ 'SPM_READYAddr': '42'
+} \ No newline at end of file
diff --git a/amforth-6.5/avr8/devices/atmega165a/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega165a/words/no-jtag.asm
new file mode 100644
index 0000000..352a4bb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega165a/words/no-jtag.asm
@@ -0,0 +1,14 @@
+; ( -- )
+; ( -- )
+; MCU
+; disable jtag at runtime
+VE_NOJTAG:
+ .dw $FF05
+ .db "-jtag",0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOJTAG
+XT_NOJTAG:
+ .dw PFA_NOJTAG
+PFA_NOJTAG:
+
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega165a/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega165a/words/no-wdt.asm
new file mode 100644
index 0000000..4a12261
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega165a/words/no-wdt.asm
@@ -0,0 +1,22 @@
+; ( -- )
+; MCU
+; disable watch dog timer at runtime
+VE_NOWDT:
+ .dw $ff04
+ .db "-wdt"
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOWDT
+XT_NOWDT:
+ .dw PFA_NOWDT
+PFA_NOWDT:
+
+; Reset WDT
+ wdr
+; Write logical one to WDTOE and WDE
+ in_ temp1, WDTCR
+ ori temp1, (1<<WDTOE)|(1<<WDE)
+ out WDTCR, temp1
+; Turn off WDT
+ ldi temp1, (0<<WDE)
+ out_ WDTCR, temp1
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega165a/words/sleep.asm b/amforth-6.5/avr8/devices/atmega165a/words/sleep.asm
new file mode 100644
index 0000000..256249c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega165a/words/sleep.asm
@@ -0,0 +1,19 @@
+; ( mode -- )
+; MCU
+; put the controller into the specified sleep mode
+VE_SLEEP:
+ .dw $ff05
+ .db "sleep", 0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_SLEEP
+XT_SLEEP:
+ .dw PFA_SLEEP
+PFA_SLEEP:
+ andi tosl, 7 ; leave only legal mode bits
+ lsl tosl ; move to correct location (bits 3-1)
+ ori tosl, 1 ; set the SE bit
+ out_ SMCR, tosl ; set the sleep config
+ sleep ; nighty-night
+ out_ SMCR, zerol ; 0 protects against accidental sleeps
+ loadtos ; pop argument from stack
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega165p/atmega165p.frt b/amforth-6.5/avr8/devices/atmega165p/atmega165p.frt
new file mode 100644
index 0000000..914aac0
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega165p/atmega165p.frt
@@ -0,0 +1,280 @@
+\ Partname: ATmega165P
+\ generated automatically
+
+\ TIMER_COUNTER_0
+&68 constant TCCR0A \ Timer/Counter0 Control Register
+ $80 constant TCCR0A_FOC0A \ Force Output Compare
+ $40 constant TCCR0A_WGM00 \ Waveform Generation Mode 0
+ $30 constant TCCR0A_COM0A \ Compare Match Output Modes
+ $08 constant TCCR0A_WGM01 \ Waveform Generation Mode 1
+ $07 constant TCCR0A_CS0 \ Clock Selects
+&70 constant TCNT0 \ Timer/Counter0
+&71 constant OCR0A \ Timer/Counter0 Output Compare Register
+&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
+ $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match Interrupt Enable
+ $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
+&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
+ $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0
+ $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
+&67 constant GTCCR \ General Timer/Control Register
+ $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
+ $01 constant GTCCR_PSR310 \ Prescaler Reset Timer/Counter1 and Timer/Counter0
+\ TIMER_COUNTER_1
+&128 constant TCCR1A \ Timer/Counter1 Control Register A
+ $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
+ $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
+ $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
+&129 constant TCCR1B \ Timer/Counter1 Control Register B
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
+ $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
+&130 constant TCCR1C \ Timer/Counter 1 Control Register C
+ $80 constant TCCR1C_FOC1A \ Force Output Compare 1A
+ $40 constant TCCR1C_FOC1B \ Force Output Compare 1B
+&132 constant TCNT1 \ Timer/Counter1 Bytes
+&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
+&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
+&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
+&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
+ $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
+ $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
+ $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
+ $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
+&54 constant TIFR1 \ Timer/Counter1 Interrupt Flag register
+ $20 constant TIFR1_ICF1 \ Input Capture Flag 1
+ $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
+ $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
+ $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
+\ TIMER_COUNTER_2
+&176 constant TCCR2A \ Timer/Counter2 Control Register
+ $80 constant TCCR2A_FOC2A \ Force Output Compare A
+ $40 constant TCCR2A_WGM20 \ Waveform Generation Mode
+ $30 constant TCCR2A_COM2A \ Compare Output Mode bits
+ $08 constant TCCR2A_WGM21 \ Waveform Generation Mode
+ $07 constant TCCR2A_CS2 \ Clock Select bits
+&178 constant TCNT2 \ Timer/Counter2
+&179 constant OCR2A \ Timer/Counter2 Output Compare Register
+&112 constant TIMSK2 \ Timer/Counter2 Interrupt Mask register
+ $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match Interrupt Enable
+ $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
+&55 constant TIFR2 \ Timer/Counter2 Interrupt Flag Register
+ $02 constant TIFR2_OCF2A \ Timer/Counter2 Output Compare Flag 2
+ $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
+&182 constant ASSR \ Asynchronous Status Register
+ $10 constant ASSR_EXCLK \ Enable External Clock Interrupt
+ $08 constant ASSR_AS2 \ AS2: Asynchronous Timer/Counter2
+ $04 constant ASSR_TCN2UB \ TCN2UB: Timer/Counter2 Update Busy
+ $02 constant ASSR_OCR2UB \ Output Compare Register2 Update Busy
+ $01 constant ASSR_TCR2UB \ TCR2UB: Timer/Counter Control Register2 Update Busy
+\ WATCHDOG
+&96 constant WDTCR \ Watchdog Timer Control Register
+ $10 constant WDTCR_WDCE \ Watchdog Change Enable
+ $08 constant WDTCR_WDE \ Watch Dog Enable
+ $07 constant WDTCR_WDP \ Watch Dog Timer Prescaler bits
+\ EEPROM
+&65 constant EEAR \ EEPROM Address Register Bytes
+&64 constant EEDR \ EEPROM Data Register
+&63 constant EECR \ EEPROM Control Register
+ $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
+ $04 constant EECR_EEMWE \ EEPROM Master Write Enable
+ $02 constant EECR_EEWE \ EEPROM Write Enable
+ $01 constant EECR_EERE \ EEPROM Read Enable
+\ SPI
+&76 constant SPCR \ SPI Control Register
+ $80 constant SPCR_SPIE \ SPI Interrupt Enable
+ $40 constant SPCR_SPE \ SPI Enable
+ $20 constant SPCR_DORD \ Data Order
+ $10 constant SPCR_MSTR \ Master/Slave Select
+ $08 constant SPCR_CPOL \ Clock polarity
+ $04 constant SPCR_CPHA \ Clock Phase
+ $03 constant SPCR_SPR \ SPI Clock Rate Selects
+&77 constant SPSR \ SPI Status Register
+ $80 constant SPSR_SPIF \ SPI Interrupt Flag
+ $40 constant SPSR_WCOL \ Write Collision Flag
+ $01 constant SPSR_SPI2X \ Double SPI Speed Bit
+&78 constant SPDR \ SPI Data Register
+\ PORTA
+&34 constant PORTA \ Port A Data Register
+&33 constant DDRA \ Port A Data Direction Register
+&32 constant PINA \ Port A Input Pins
+\ PORTB
+&37 constant PORTB \ Port B Data Register
+&36 constant DDRB \ Port B Data Direction Register
+&35 constant PINB \ Port B Input Pins
+\ PORTC
+&40 constant PORTC \ Port C Data Register
+&39 constant DDRC \ Port C Data Direction Register
+&38 constant PINC \ Port C Input Pins
+\ PORTD
+&43 constant PORTD \ Port D Data Register
+&42 constant DDRD \ Port D Data Direction Register
+&41 constant PIND \ Port D Input Pins
+\ ANALOG_COMPARATOR
+&123 constant ADCSRB \ ADC Control and Status Register B
+ $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer Enable
+&80 constant ACSR \ Analog Comparator Control And Status Register
+ $80 constant ACSR_ACD \ Analog Comparator Disable
+ $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
+ $20 constant ACSR_ACO \ Analog Compare Output
+ $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
+ $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
+ $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
+ $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
+&127 constant DIDR1 \ Digital Input Disable Register 1
+ $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
+ $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
+\ PORTE
+&46 constant PORTE \ Data Register, Port E
+&45 constant DDRE \ Data Direction Register, Port E
+&44 constant PINE \ Input Pins, Port E
+\ PORTF
+&49 constant PORTF \ Data Register, Port F
+&48 constant DDRF \ Data Direction Register, Port F
+&47 constant PINF \ Input Pins, Port F
+\ PORTG
+&52 constant PORTG \ Port G Data Register
+&51 constant DDRG \ Port G Data Direction Register
+&50 constant PING \ Port G Input Pins
+\ JTAG
+&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
+&85 constant MCUCR \ MCU Control Register
+ $80 constant MCUCR_JTD \ JTAG Interface Disable
+&84 constant MCUSR \ MCU Status Register
+ $10 constant MCUSR_JTRF \ JTAG Reset Flag
+\ EXTERNAL_INTERRUPT
+&105 constant EICRA \ External Interrupt Control Register
+ $02 constant EICRA_ISC01 \ External Interrupt Sense Control 0 Bit 1
+ $01 constant EICRA_ISC00 \ External Interrupt Sense Control 0 Bit 0
+&61 constant EIMSK \ External Interrupt Mask Register
+ $C0 constant EIMSK_PCIE \ Pin Change Interrupt Enables
+ $01 constant EIMSK_INT0 \ External Interrupt Request 0 Enable
+&60 constant EIFR \ External Interrupt Flag Register
+ $C0 constant EIFR_PCIF \ Pin Change Interrupt Flags
+ $01 constant EIFR_INTF0 \ External Interrupt Flag 0
+&108 constant PCMSK1 \ Pin Change Mask Register 1
+ $FF constant PCMSK1_PCINT \ Pin Change Enable Masks
+&107 constant PCMSK0 \ Pin Change Mask Register 0
+ $FF constant PCMSK0_PCINT \ Pin Change Enable Masks
+\ USI
+&186 constant USIDR \ USI Data Register
+&185 constant USISR \ USI Status Register
+ $80 constant USISR_USISIF \ Start Condition Interrupt Flag
+ $40 constant USISR_USIOIF \ Counter Overflow Interrupt Flag
+ $20 constant USISR_USIPF \ Stop Condition Flag
+ $10 constant USISR_USIDC \ Data Output Collision
+ $0F constant USISR_USICNT \ USI Counter Value Bits
+&184 constant USICR \ USI Control Register
+ $80 constant USICR_USISIE \ Start Condition Interrupt Enable
+ $40 constant USICR_USIOIE \ Counter Overflow Interrupt Enable
+ $30 constant USICR_USIWM \ USI Wire Mode Bits
+ $0C constant USICR_USICS \ USI Clock Source Select Bits
+ $02 constant USICR_USICLK \ Clock Strobe
+ $01 constant USICR_USITC \ Toggle Clock Port Pin
+\ AD_CONVERTER
+&124 constant ADMUX \ The ADC multiplexer Selection Register
+ $C0 constant ADMUX_REFS \ Reference Selection Bits
+ $20 constant ADMUX_ADLAR \ Left Adjust Result
+ $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
+&122 constant ADCSRA \ The ADC Control and Status register
+ $80 constant ADCSRA_ADEN \ ADC Enable
+ $40 constant ADCSRA_ADSC \ ADC Start Conversion
+ $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
+ $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
+ $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
+ $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
+&120 constant ADC \ ADC Data Register Bytes
+&126 constant DIDR0 \ Digital Input Disable Register 0
+ $80 constant DIDR0_ADC7D \ ADC7 Digital input Disable
+ $40 constant DIDR0_ADC6D \ ADC6 Digital input Disable
+ $20 constant DIDR0_ADC5D \ ADC5 Digital input Disable
+ $10 constant DIDR0_ADC4D \ ADC4 Digital input Disable
+ $08 constant DIDR0_ADC3D \ ADC3 Digital input Disable
+ $04 constant DIDR0_ADC2D \ ADC2 Digital input Disable
+ $02 constant DIDR0_ADC1D \ ADC1 Digital input Disable
+ $01 constant DIDR0_ADC0D \ ADC0 Digital input Disable
+\ BOOT_LOAD
+&87 constant SPMCSR \ Store Program Memory Control Register
+ $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
+ $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
+ $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
+ $04 constant SPMCSR_PGWRT \ Page Write
+ $02 constant SPMCSR_PGERS \ Page Erase
+ $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
+\ USART0
+&198 constant UDR0 \ USART I/O Data Register
+&192 constant UCSR0A \ USART Control and Status Register A
+ $80 constant UCSR0A_RXC0 \ USART Receive Complete
+ $40 constant UCSR0A_TXC0 \ USART Transmit Complete
+ $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
+ $10 constant UCSR0A_FE0 \ Framing Error
+ $08 constant UCSR0A_DOR0 \ Data OverRun
+ $04 constant UCSR0A_UPE0 \ USART Parity Error
+ $02 constant UCSR0A_U2X0 \ Double the USART Transmission Speed
+ $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
+&193 constant UCSR0B \ USART Control and Status Register B
+ $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
+ $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
+ $20 constant UCSR0B_UDRIE0 \ USART Data Register Empty Interrupt Enable
+ $10 constant UCSR0B_RXEN0 \ Receiver Enable
+ $08 constant UCSR0B_TXEN0 \ Transmitter Enable
+ $04 constant UCSR0B_UCSZ02 \ Character Size
+ $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
+ $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
+&194 constant UCSR0C \ USART Control and Status Register C
+ $40 constant UCSR0C_UMSEL0 \ USART Mode Select
+ $30 constant UCSR0C_UPM0 \ Parity Mode Bits
+ $08 constant UCSR0C_USBS0 \ Stop Bit Select
+ $06 constant UCSR0C_UCSZ0 \ Character Size
+ $01 constant UCSR0C_UCPOL0 \ Clock Polarity
+&196 constant UBRR0 \ USART Baud Rate Register Bytes
+\ CPU
+&95 constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ $08 constant SREG_V \ Two's Complement Overflow Flag
+ $04 constant SREG_N \ Negative Flag
+ $02 constant SREG_Z \ Zero Flag
+ $01 constant SREG_C \ Carry Flag
+&93 constant SP \ Stack Pointer
+&102 constant OSCCAL \ Oscillator Calibration Value
+&97 constant CLKPR \ Clock Prescale Register
+ $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable
+ $0F constant CLKPR_CLKPS \ Clock Prescaler Select Bits
+&100 constant PRR \ Power Reduction Register
+ $08 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
+ $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
+ $02 constant PRR_PRUSART0 \ Power Reduction USART
+ $01 constant PRR_PRADC \ Power Reduction ADC
+&83 constant SMCR \ Sleep Mode Control Register
+ $0E constant SMCR_SM \ Sleep Mode Select bits
+ $01 constant SMCR_SE \ Sleep Enable
+&75 constant GPIOR2 \ General Purpose IO Register 2
+&74 constant GPIOR1 \ General Purpose IO Register 1
+&62 constant GPIOR0 \ General Purpose IO Register 0
+
+\ Interrupts
+&2 constant INT0Addr \ External Interrupt Request 0
+&4 constant PCINT0Addr \ Pin Change Interrupt Request 0
+&6 constant PCINT1Addr \ Pin Change Interrupt Request 1
+&8 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
+&10 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
+&12 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+&14 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
+&16 constant TIMER1_COMPBAddr \ Timer/Counter Compare Match B
+&18 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+&20 constant TIMER0_COMPAddr \ Timer/Counter0 Compare Match
+&22 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
+&24 constant SPI__STCAddr \ SPI Serial Transfer Complete
+&26 constant USART0__RXAddr \ USART0, Rx Complete
+&28 constant USART0__UDREAddr \ USART0 Data register Empty
+&30 constant USART0__TXAddr \ USART0, Tx Complete
+&32 constant USI_STARTAddr \ USI Start Condition
+&34 constant USI_OVERFLOWAddr \ USI Overflow
+&36 constant ANALOG_COMPAddr \ Analog Comparator
+&38 constant ADCAddr \ ADC Conversion Complete
+&40 constant EE_READYAddr \ EEPROM Ready
+&42 constant SPM_READYAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/atmega165p/device.asm b/amforth-6.5/avr8/devices/atmega165p/device.asm
new file mode 100644
index 0000000..ee78665
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega165p/device.asm
@@ -0,0 +1,106 @@
+; Partname: ATmega165P
+; generated automatically, do not edit
+
+.nolist
+ .include "m165Pdef.inc"
+.list
+
+.equ ramstart = 256
+.equ CELLSIZE = 2
+.macro readflashcell
+ lsl zl
+ rol zh
+ lpm @0, Z+
+ lpm @1, Z+
+.endmacro
+.macro writeflashcell
+ lsl zl
+ rol zh
+.endmacro
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_TIMER_COUNTER_2 = 0
+.set WANT_WATCHDOG = 0
+.set WANT_EEPROM = 0
+.set WANT_SPI = 0
+.set WANT_PORTA = 0
+.set WANT_PORTB = 0
+.set WANT_PORTC = 0
+.set WANT_PORTD = 0
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_PORTE = 0
+.set WANT_PORTF = 0
+.set WANT_PORTG = 0
+.set WANT_JTAG = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_USI = 0
+.set WANT_AD_CONVERTER = 0
+.set WANT_BOOT_LOAD = 0
+.set WANT_USART0 = 0
+.set WANT_CPU = 0
+.equ intvecsize = 2 ; please verify; flash size: 16384 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.org 2
+ rcall isr ; External Interrupt Request 0
+.org 4
+ rcall isr ; Pin Change Interrupt Request 0
+.org 6
+ rcall isr ; Pin Change Interrupt Request 1
+.org 8
+ rcall isr ; Timer/Counter2 Compare Match
+.org 10
+ rcall isr ; Timer/Counter2 Overflow
+.org 12
+ rcall isr ; Timer/Counter1 Capture Event
+.org 14
+ rcall isr ; Timer/Counter1 Compare Match A
+.org 16
+ rcall isr ; Timer/Counter Compare Match B
+.org 18
+ rcall isr ; Timer/Counter1 Overflow
+.org 20
+ rcall isr ; Timer/Counter0 Compare Match
+.org 22
+ rcall isr ; Timer/Counter0 Overflow
+.org 24
+ rcall isr ; SPI Serial Transfer Complete
+.org 26
+ rcall isr ; USART0, Rx Complete
+.org 28
+ rcall isr ; USART0 Data register Empty
+.org 30
+ rcall isr ; USART0, Tx Complete
+.org 32
+ rcall isr ; USI Start Condition
+.org 34
+ rcall isr ; USI Overflow
+.org 36
+ rcall isr ; Analog Comparator
+.org 38
+ rcall isr ; ADC Conversion Complete
+.org 40
+ rcall isr ; EEPROM Ready
+.org 42
+ rcall isr ; Store Program Memory Read
+.equ INTVECTORS = 22
+.nooverlap
+
+; compatability layer (maybe empty)
+.equ EEPE = EEWE
+.equ EEMPE = EEMWE
+
+; controller data area, environment query mcu-info
+mcu_info:
+mcu_ramsize:
+ .dw 1024
+mcu_eepromsize:
+ .dw 512
+mcu_maxdp:
+ .dw 14336
+mcu_numints:
+ .dw 22
+mcu_name:
+ .dw 10
+ .db "ATmega165P"
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega165p/device.inc b/amforth-6.5/avr8/devices/atmega165p/device.inc
new file mode 100644
index 0000000..9760615
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega165p/device.inc
@@ -0,0 +1,1050 @@
+; Partname: ATmega165P
+; generated automatically, no not edit
+
+.if WANT_TIMER_COUNTER_0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Control Register
+VE_TCCR0A:
+ .dw $ff06
+ .db "TCCR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0A
+XT_TCCR0A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0A:
+ .dw 68
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw 70
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0A:
+ .dw $ff05
+ .db "OCR0A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0A
+XT_OCR0A:
+ .dw PFA_DOVARIABLE
+PFA_OCR0A:
+ .dw 71
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Mask Register
+VE_TIMSK0:
+ .dw $ff06
+ .db "TIMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK0
+XT_TIMSK0:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK0:
+ .dw 110
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Flag register
+VE_TIFR0:
+ .dw $ff05
+ .db "TIFR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR0
+XT_TIFR0:
+ .dw PFA_DOVARIABLE
+PFA_TIFR0:
+ .dw 53
+; ( -- addr ) System Constant
+; R( -- )
+; General Timer/Control Register
+VE_GTCCR:
+ .dw $ff05
+ .db "GTCCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GTCCR
+XT_GTCCR:
+ .dw PFA_DOVARIABLE
+PFA_GTCCR:
+ .dw 67
+
+.endif
+.if WANT_TIMER_COUNTER_1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw 128
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw 129
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter 1 Control Register C
+VE_TCCR1C:
+ .dw $ff06
+ .db "TCCR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1C
+XT_TCCR1C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1C:
+ .dw 130
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Bytes
+VE_TCNT1:
+ .dw $ff05
+ .db "TCNT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1
+XT_TCNT1:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1:
+ .dw 132
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register A Bytes
+VE_OCR1A:
+ .dw $ff05
+ .db "OCR1A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1A
+XT_OCR1A:
+ .dw PFA_DOVARIABLE
+PFA_OCR1A:
+ .dw 136
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register B Bytes
+VE_OCR1B:
+ .dw $ff05
+ .db "OCR1B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1B
+XT_OCR1B:
+ .dw PFA_DOVARIABLE
+PFA_OCR1B:
+ .dw 138
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Bytes
+VE_ICR1:
+ .dw $ff04
+ .db "ICR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1
+XT_ICR1:
+ .dw PFA_DOVARIABLE
+PFA_ICR1:
+ .dw 134
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Mask Register
+VE_TIMSK1:
+ .dw $ff06
+ .db "TIMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK1
+XT_TIMSK1:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK1:
+ .dw 111
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Flag register
+VE_TIFR1:
+ .dw $ff05
+ .db "TIFR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR1
+XT_TIFR1:
+ .dw PFA_DOVARIABLE
+PFA_TIFR1:
+ .dw 54
+
+.endif
+.if WANT_TIMER_COUNTER_2 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register
+VE_TCCR2A:
+ .dw $ff06
+ .db "TCCR2A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2A
+XT_TCCR2A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2A:
+ .dw 176
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2
+VE_TCNT2:
+ .dw $ff05
+ .db "TCNT2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT2
+XT_TCNT2:
+ .dw PFA_DOVARIABLE
+PFA_TCNT2:
+ .dw 178
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register
+VE_OCR2A:
+ .dw $ff05
+ .db "OCR2A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2A
+XT_OCR2A:
+ .dw PFA_DOVARIABLE
+PFA_OCR2A:
+ .dw 179
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Interrupt Mask register
+VE_TIMSK2:
+ .dw $ff06
+ .db "TIMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK2
+XT_TIMSK2:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK2:
+ .dw 112
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Interrupt Flag Register
+VE_TIFR2:
+ .dw $ff05
+ .db "TIFR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR2
+XT_TIFR2:
+ .dw PFA_DOVARIABLE
+PFA_TIFR2:
+ .dw 55
+; ( -- addr ) System Constant
+; R( -- )
+; Asynchronous Status Register
+VE_ASSR:
+ .dw $ff04
+ .db "ASSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ASSR
+XT_ASSR:
+ .dw PFA_DOVARIABLE
+PFA_ASSR:
+ .dw 182
+
+.endif
+.if WANT_WATCHDOG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCR:
+ .dw $ff05
+ .db "WDTCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCR
+XT_WDTCR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCR:
+ .dw 96
+
+.endif
+.if WANT_EEPROM == 1
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Address Register Bytes
+VE_EEAR:
+ .dw $ff04
+ .db "EEAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEAR
+XT_EEAR:
+ .dw PFA_DOVARIABLE
+PFA_EEAR:
+ .dw 65
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw 64
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw 63
+
+.endif
+.if WANT_SPI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR:
+ .dw $ff04
+ .db "SPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR
+XT_SPCR:
+ .dw PFA_DOVARIABLE
+PFA_SPCR:
+ .dw 76
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR:
+ .dw $ff04
+ .db "SPSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR
+XT_SPSR:
+ .dw PFA_DOVARIABLE
+PFA_SPSR:
+ .dw 77
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR:
+ .dw $ff04
+ .db "SPDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR
+XT_SPDR:
+ .dw PFA_DOVARIABLE
+PFA_SPDR:
+ .dw 78
+
+.endif
+.if WANT_PORTA == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Register
+VE_PORTA:
+ .dw $ff05
+ .db "PORTA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTA
+XT_PORTA:
+ .dw PFA_DOVARIABLE
+PFA_PORTA:
+ .dw 34
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Direction Register
+VE_DDRA:
+ .dw $ff04
+ .db "DDRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRA
+XT_DDRA:
+ .dw PFA_DOVARIABLE
+PFA_DDRA:
+ .dw 33
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Input Pins
+VE_PINA:
+ .dw $ff04
+ .db "PINA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINA
+XT_PINA:
+ .dw PFA_DOVARIABLE
+PFA_PINA:
+ .dw 32
+
+.endif
+.if WANT_PORTB == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw 37
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw 36
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw 35
+
+.endif
+.if WANT_PORTC == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Register
+VE_PORTC:
+ .dw $ff05
+ .db "PORTC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTC
+XT_PORTC:
+ .dw PFA_DOVARIABLE
+PFA_PORTC:
+ .dw 40
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Direction Register
+VE_DDRC:
+ .dw $ff04
+ .db "DDRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRC
+XT_DDRC:
+ .dw PFA_DOVARIABLE
+PFA_DDRC:
+ .dw 39
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Input Pins
+VE_PINC:
+ .dw $ff04
+ .db "PINC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINC
+XT_PINC:
+ .dw PFA_DOVARIABLE
+PFA_PINC:
+ .dw 38
+
+.endif
+.if WANT_PORTD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw 43
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw 42
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw 41
+
+.endif
+.if WANT_ANALOG_COMPARATOR == 1
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Control and Status Register B
+VE_ADCSRB:
+ .dw $ff06
+ .db "ADCSRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRB
+XT_ADCSRB:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRB:
+ .dw 123
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Control And Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw 80
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 1
+VE_DIDR1:
+ .dw $ff05
+ .db "DIDR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR1
+XT_DIDR1:
+ .dw PFA_DOVARIABLE
+PFA_DIDR1:
+ .dw 127
+
+.endif
+.if WANT_PORTE == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port E
+VE_PORTE:
+ .dw $ff05
+ .db "PORTE",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTE
+XT_PORTE:
+ .dw PFA_DOVARIABLE
+PFA_PORTE:
+ .dw 46
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port E
+VE_DDRE:
+ .dw $ff04
+ .db "DDRE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRE
+XT_DDRE:
+ .dw PFA_DOVARIABLE
+PFA_DDRE:
+ .dw 45
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port E
+VE_PINE:
+ .dw $ff04
+ .db "PINE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINE
+XT_PINE:
+ .dw PFA_DOVARIABLE
+PFA_PINE:
+ .dw 44
+
+.endif
+.if WANT_PORTF == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port F
+VE_PORTF:
+ .dw $ff05
+ .db "PORTF",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTF
+XT_PORTF:
+ .dw PFA_DOVARIABLE
+PFA_PORTF:
+ .dw 49
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port F
+VE_DDRF:
+ .dw $ff04
+ .db "DDRF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRF
+XT_DDRF:
+ .dw PFA_DOVARIABLE
+PFA_DDRF:
+ .dw 48
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port F
+VE_PINF:
+ .dw $ff04
+ .db "PINF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINF
+XT_PINF:
+ .dw PFA_DOVARIABLE
+PFA_PINF:
+ .dw 47
+
+.endif
+.if WANT_PORTG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Data Register
+VE_PORTG:
+ .dw $ff05
+ .db "PORTG",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTG
+XT_PORTG:
+ .dw PFA_DOVARIABLE
+PFA_PORTG:
+ .dw 52
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Data Direction Register
+VE_DDRG:
+ .dw $ff04
+ .db "DDRG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRG
+XT_DDRG:
+ .dw PFA_DOVARIABLE
+PFA_DDRG:
+ .dw 51
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Input Pins
+VE_PING:
+ .dw $ff04
+ .db "PING"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PING
+XT_PING:
+ .dw PFA_DOVARIABLE
+PFA_PING:
+ .dw 50
+
+.endif
+.if WANT_JTAG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; On-Chip Debug Related Register in I/O Memory
+VE_OCDR:
+ .dw $ff04
+ .db "OCDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCDR
+XT_OCDR:
+ .dw PFA_DOVARIABLE
+PFA_OCDR:
+ .dw 81
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw 85
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Status Register
+VE_MCUSR:
+ .dw $ff05
+ .db "MCUSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUSR
+XT_MCUSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUSR:
+ .dw 84
+
+.endif
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register
+VE_EICRA:
+ .dw $ff05
+ .db "EICRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRA
+XT_EICRA:
+ .dw PFA_DOVARIABLE
+PFA_EICRA:
+ .dw 105
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Mask Register
+VE_EIMSK:
+ .dw $ff05
+ .db "EIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIMSK
+XT_EIMSK:
+ .dw PFA_DOVARIABLE
+PFA_EIMSK:
+ .dw 61
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Flag Register
+VE_EIFR:
+ .dw $ff04
+ .db "EIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIFR
+XT_EIFR:
+ .dw PFA_DOVARIABLE
+PFA_EIFR:
+ .dw 60
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 1
+VE_PCMSK1:
+ .dw $ff06
+ .db "PCMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK1
+XT_PCMSK1:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK1:
+ .dw 108
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 0
+VE_PCMSK0:
+ .dw $ff06
+ .db "PCMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK0
+XT_PCMSK0:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK0:
+ .dw 107
+
+.endif
+.if WANT_USI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USI Data Register
+VE_USIDR:
+ .dw $ff05
+ .db "USIDR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USIDR
+XT_USIDR:
+ .dw PFA_DOVARIABLE
+PFA_USIDR:
+ .dw 186
+; ( -- addr ) System Constant
+; R( -- )
+; USI Status Register
+VE_USISR:
+ .dw $ff05
+ .db "USISR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USISR
+XT_USISR:
+ .dw PFA_DOVARIABLE
+PFA_USISR:
+ .dw 185
+; ( -- addr ) System Constant
+; R( -- )
+; USI Control Register
+VE_USICR:
+ .dw $ff05
+ .db "USICR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USICR
+XT_USICR:
+ .dw PFA_DOVARIABLE
+PFA_USICR:
+ .dw 184
+
+.endif
+.if WANT_AD_CONVERTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC multiplexer Selection Register
+VE_ADMUX:
+ .dw $ff05
+ .db "ADMUX",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADMUX
+XT_ADMUX:
+ .dw PFA_DOVARIABLE
+PFA_ADMUX:
+ .dw 124
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register
+VE_ADCSRA:
+ .dw $ff06
+ .db "ADCSRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRA
+XT_ADCSRA:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRA:
+ .dw 122
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register Bytes
+VE_ADC:
+ .dw $ff03
+ .db "ADC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADC
+XT_ADC:
+ .dw PFA_DOVARIABLE
+PFA_ADC:
+ .dw 120
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 0
+VE_DIDR0:
+ .dw $ff05
+ .db "DIDR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR0
+XT_DIDR0:
+ .dw PFA_DOVARIABLE
+PFA_DIDR0:
+ .dw 126
+
+.endif
+.if WANT_BOOT_LOAD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control Register
+VE_SPMCSR:
+ .dw $ff06
+ .db "SPMCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCSR
+XT_SPMCSR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCSR:
+ .dw 87
+
+.endif
+.if WANT_USART0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR0:
+ .dw $ff04
+ .db "UDR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR0
+XT_UDR0:
+ .dw PFA_DOVARIABLE
+PFA_UDR0:
+ .dw 198
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR0A:
+ .dw $ff06
+ .db "UCSR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0A
+XT_UCSR0A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0A:
+ .dw 192
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR0B:
+ .dw $ff06
+ .db "UCSR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0B
+XT_UCSR0B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0B:
+ .dw 193
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR0C:
+ .dw $ff06
+ .db "UCSR0C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0C
+XT_UCSR0C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0C:
+ .dw 194
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Bytes
+VE_UBRR0:
+ .dw $ff05
+ .db "UBRR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR0
+XT_UBRR0:
+ .dw PFA_DOVARIABLE
+PFA_UBRR0:
+ .dw 196
+
+.endif
+.if WANT_CPU == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw 95
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer
+VE_SP:
+ .dw $ff02
+ .db "SP"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SP
+XT_SP:
+ .dw PFA_DOVARIABLE
+PFA_SP:
+ .dw 93
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Calibration Value
+VE_OSCCAL:
+ .dw $ff06
+ .db "OSCCAL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSCCAL
+XT_OSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_OSCCAL:
+ .dw 102
+; ( -- addr ) System Constant
+; R( -- )
+; Clock Prescale Register
+VE_CLKPR:
+ .dw $ff05
+ .db "CLKPR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKPR
+XT_CLKPR:
+ .dw PFA_DOVARIABLE
+PFA_CLKPR:
+ .dw 97
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register
+VE_PRR:
+ .dw $ff03
+ .db "PRR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR
+XT_PRR:
+ .dw PFA_DOVARIABLE
+PFA_PRR:
+ .dw 100
+; ( -- addr ) System Constant
+; R( -- )
+; Sleep Mode Control Register
+VE_SMCR:
+ .dw $ff04
+ .db "SMCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SMCR
+XT_SMCR:
+ .dw PFA_DOVARIABLE
+PFA_SMCR:
+ .dw 83
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 2
+VE_GPIOR2:
+ .dw $ff06
+ .db "GPIOR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR2
+XT_GPIOR2:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR2:
+ .dw 75
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 1
+VE_GPIOR1:
+ .dw $ff06
+ .db "GPIOR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR1
+XT_GPIOR1:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR1:
+ .dw 74
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 0
+VE_GPIOR0:
+ .dw $ff06
+ .db "GPIOR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR0
+XT_GPIOR0:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR0:
+ .dw 62
+
+.endif
diff --git a/amforth-6.5/avr8/devices/atmega165p/device.py b/amforth-6.5/avr8/devices/atmega165p/device.py
new file mode 100644
index 0000000..1b63682
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega165p/device.py
@@ -0,0 +1,319 @@
+# Generated Automatically
+
+# Partname ATmega165P
+
+MCUREGS = {
+# Interrupt Vectors
+ 'INT0Addr' : '#2', # External Interrupt Request 0
+ 'PCINT0Addr' : '#4', # Pin Change Interrupt Request 0
+ 'PCINT1Addr' : '#6', # Pin Change Interrupt Request 1
+ 'TIMER2_COMPAddr' : '#8', # Timer/Counter2 Compare Match
+ 'TIMER2_OVFAddr' : '#10', # Timer/Counter2 Overflow
+ 'TIMER1_CAPTAddr' : '#12', # Timer/Counter1 Capture Event
+ 'TIMER1_COMPAAddr' : '#14', # Timer/Counter1 Compare Match A
+ 'TIMER1_COMPBAddr' : '#16', # Timer/Counter Compare Match B
+ 'TIMER1_OVFAddr' : '#18', # Timer/Counter1 Overflow
+ 'TIMER0_COMPAddr' : '#20', # Timer/Counter0 Compare Match
+ 'TIMER0_OVFAddr' : '#22', # Timer/Counter0 Overflow
+ 'SPI_STCAddr' : '#24', # SPI Serial Transfer Complete
+ 'USART0_RXAddr' : '#26', # USART0, Rx Complete
+ 'USART0_UDREAddr' : '#28', # USART0 Data register Empty
+ 'USART0_TXAddr' : '#30', # USART0, Tx Complete
+ 'USI_STARTAddr' : '#32', # USI Start Condition
+ 'USI_OVERFLOWAddr' : '#34', # USI Overflow
+ 'ANALOG_COMPAddr' : '#36', # Analog Comparator
+ 'ADCAddr' : '#38', # ADC Conversion Complete
+ 'EE_READYAddr' : '#40', # EEPROM Ready
+ 'SPM_READYAddr' : '#42', # Store Program Memory Read
+
+# Module TIMER_COUNTER_0
+ 'TCCR0A' : '$44', # Timer/Counter0 Control Registe
+ 'TCCR0A_FOC0A': '$80', # Force Output Compare
+ 'TCCR0A_WGM00': '$40', # Waveform Generation Mode 0
+ 'TCCR0A_COM0A': '$30', # Compare Match Output Modes
+ 'TCCR0A_WGM01': '$8', # Waveform Generation Mode 1
+ 'TCCR0A_CS0': '$7', # Clock Selects
+ 'TCNT0' : '$46', # Timer/Counter0
+ 'OCR0A' : '$47', # Timer/Counter0 Output Compare
+ 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
+ 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
+ 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
+ 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
+ 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
+ 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Control Register
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSR310': '$1', # Prescaler Reset Timer/Counter1
+
+# Module TIMER_COUNTER_1
+ 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
+ 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
+ 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
+ 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
+ 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
+ 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
+ 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
+ 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
+ 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
+ 'TCCR1C' : '$82', # Timer/Counter 1 Control Regist
+ 'TCCR1C_FOC1A': '$80', # Force Output Compare 1A
+ 'TCCR1C_FOC1B': '$40', # Force Output Compare 1B
+ 'TCNT1' : '$84', # Timer/Counter1 Bytes
+ 'OCR1A' : '$88', # Timer/Counter1 Output Compare
+ 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
+ 'ICR1' : '$86', # Timer/Counter1 Input Capture R
+ 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
+ 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
+ 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
+ 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
+ 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
+ 'TIFR1' : '$36', # Timer/Counter1 Interrupt Flag
+ 'TIFR1_ICF1': '$20', # Input Capture Flag 1
+ 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
+ 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
+ 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
+
+# Module TIMER_COUNTER_2
+ 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
+ 'TCCR2A_FOC2A': '$80', # Force Output Compare A
+ 'TCCR2A_WGM20': '$40', # Waveform Generation Mode
+ 'TCCR2A_COM2A': '$30', # Compare Output Mode bits
+ 'TCCR2A_WGM21': '$8', # Waveform Generation Mode
+ 'TCCR2A_CS2': '$7', # Clock Select bits
+ 'TCNT2' : '$b2', # Timer/Counter2
+ 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
+ 'TIMSK2' : '$70', # Timer/Counter2 Interrupt Mask
+ 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
+ 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
+ 'TIFR2' : '$37', # Timer/Counter2 Interrupt Flag
+ 'TIFR2_OCF2A': '$2', # Timer/Counter2 Output Compare
+ 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_PSR2': '$2', # Prescaler Reset Timer/Counter2
+ 'ASSR' : '$b6', # Asynchronous Status Register
+ 'ASSR_EXCLK': '$10', # Enable External Clock Interrup
+ 'ASSR_AS2': '$8', # AS2: Asynchronous Timer/Counte
+ 'ASSR_TCN2UB': '$4', # TCN2UB: Timer/Counter2 Update
+ 'ASSR_OCR2UB': '$2', # Output Compare Register2 Updat
+ 'ASSR_TCR2UB': '$1', # TCR2UB: Timer/Counter Control
+
+# Module WATCHDOG
+ 'WDTCR' : '$60', # Watchdog Timer Control Registe
+ 'WDTCR_WDCE': '$10', # Watchdog Change Enable
+ 'WDTCR_WDE': '$8', # Watch Dog Enable
+ 'WDTCR_WDP': '$7', # Watch Dog Timer Prescaler bits
+
+# Module EEPROM
+ 'EEAR' : '$41', # EEPROM Address Register Bytes
+ 'EEDR' : '$40', # EEPROM Data Register
+ 'EECR' : '$3f', # EEPROM Control Register
+ 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
+ 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
+ 'EECR_EEWE': '$2', # EEPROM Write Enable
+ 'EECR_EERE': '$1', # EEPROM Read Enable
+
+# Module SPI
+ 'SPCR' : '$4c', # SPI Control Register
+ 'SPCR_SPIE': '$80', # SPI Interrupt Enable
+ 'SPCR_SPE': '$40', # SPI Enable
+ 'SPCR_DORD': '$20', # Data Order
+ 'SPCR_MSTR': '$10', # Master/Slave Select
+ 'SPCR_CPOL': '$8', # Clock polarity
+ 'SPCR_CPHA': '$4', # Clock Phase
+ 'SPCR_SPR': '$3', # SPI Clock Rate Selects
+ 'SPSR' : '$4d', # SPI Status Register
+ 'SPSR_SPIF': '$80', # SPI Interrupt Flag
+ 'SPSR_WCOL': '$40', # Write Collision Flag
+ 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
+ 'SPDR' : '$4e', # SPI Data Register
+
+# Module PORTA
+ 'PORTA' : '$22', # Port A Data Register
+ 'DDRA' : '$21', # Port A Data Direction Register
+ 'PINA' : '$20', # Port A Input Pins
+
+# Module PORTB
+ 'PORTB' : '$25', # Port B Data Register
+ 'DDRB' : '$24', # Port B Data Direction Register
+ 'PINB' : '$23', # Port B Input Pins
+
+# Module PORTC
+ 'PORTC' : '$28', # Port C Data Register
+ 'DDRC' : '$27', # Port C Data Direction Register
+ 'PINC' : '$26', # Port C Input Pins
+
+# Module PORTD
+ 'PORTD' : '$2b', # Port D Data Register
+ 'DDRD' : '$2a', # Port D Data Direction Register
+ 'PIND' : '$29', # Port D Input Pins
+
+# Module ANALOG_COMPARATOR
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
+ 'ACSR' : '$50', # Analog Comparator Control And
+ 'ACSR_ACD': '$80', # Analog Comparator Disable
+ 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
+ 'ACSR_ACO': '$20', # Analog Compare Output
+ 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
+ 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
+ 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
+ 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
+ 'DIDR1' : '$7f', # Digital Input Disable Register
+ 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
+ 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
+
+# Module PORTE
+ 'PORTE' : '$2e', # Data Register, Port E
+ 'DDRE' : '$2d', # Data Direction Register, Port
+ 'PINE' : '$2c', # Input Pins, Port E
+
+# Module PORTF
+ 'PORTF' : '$31', # Data Register, Port F
+ 'DDRF' : '$30', # Data Direction Register, Port
+ 'PINF' : '$2f', # Input Pins, Port F
+
+# Module PORTG
+ 'PORTG' : '$34', # Port G Data Register
+ 'DDRG' : '$33', # Port G Data Direction Register
+ 'PING' : '$32', # Port G Input Pins
+
+# Module JTAG
+ 'OCDR' : '$51', # On-Chip Debug Related Register
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_JTD': '$80', # JTAG Interface Disable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+
+# Module EXTERNAL_INTERRUPT
+ 'EICRA' : '$69', # External Interrupt Control Reg
+ 'EICRA_ISC01': '$2', # External Interrupt Sense Contr
+ 'EICRA_ISC00': '$1', # External Interrupt Sense Contr
+ 'EIMSK' : '$3d', # External Interrupt Mask Regist
+ 'EIMSK_PCIE': '$c0', # Pin Change Interrupt Enables
+ 'EIMSK_INT0': '$1', # External Interrupt Request 0 E
+ 'EIFR' : '$3c', # External Interrupt Flag Regist
+ 'EIFR_PCIF': '$c0', # Pin Change Interrupt Flags
+ 'EIFR_INTF0': '$1', # External Interrupt Flag 0
+ 'PCMSK1' : '$6c', # Pin Change Mask Register 1
+ 'PCMSK1_PCINT': '$ff', # Pin Change Enable Masks
+ 'PCMSK0' : '$6b', # Pin Change Mask Register 0
+ 'PCMSK0_PCINT': '$ff', # Pin Change Enable Masks
+
+# Module USI
+ 'USIDR' : '$ba', # USI Data Register
+ 'USISR' : '$b9', # USI Status Register
+ 'USISR_USISIF': '$80', # Start Condition Interrupt Flag
+ 'USISR_USIOIF': '$40', # Counter Overflow Interrupt Fla
+ 'USISR_USIPF': '$20', # Stop Condition Flag
+ 'USISR_USIDC': '$10', # Data Output Collision
+ 'USISR_USICNT': '$f', # USI Counter Value Bits
+ 'USICR' : '$b8', # USI Control Register
+ 'USICR_USISIE': '$80', # Start Condition Interrupt Enab
+ 'USICR_USIOIE': '$40', # Counter Overflow Interrupt Ena
+ 'USICR_USIWM': '$30', # USI Wire Mode Bits
+ 'USICR_USICS': '$c', # USI Clock Source Select Bits
+ 'USICR_USICLK': '$2', # Clock Strobe
+ 'USICR_USITC': '$1', # Toggle Clock Port Pin
+
+# Module AD_CONVERTER
+ 'ADMUX' : '$7c', # The ADC multiplexer Selection
+ 'ADMUX_REFS': '$c0', # Reference Selection Bits
+ 'ADMUX_ADLAR': '$20', # Left Adjust Result
+ 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
+ 'ADCSRA' : '$7a', # The ADC Control and Status reg
+ 'ADCSRA_ADEN': '$80', # ADC Enable
+ 'ADCSRA_ADSC': '$40', # ADC Start Conversion
+ 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
+ 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
+ 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
+ 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
+ 'ADC' : '$78', # ADC Data Register Bytes
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Sources
+ 'DIDR0' : '$7e', # Digital Input Disable Register
+ 'DIDR0_ADC7D': '$80', # ADC7 Digital input Disable
+ 'DIDR0_ADC6D': '$40', # ADC6 Digital input Disable
+ 'DIDR0_ADC5D': '$20', # ADC5 Digital input Disable
+ 'DIDR0_ADC4D': '$10', # ADC4 Digital input Disable
+ 'DIDR0_ADC3D': '$8', # ADC3 Digital input Disable
+ 'DIDR0_ADC2D': '$4', # ADC2 Digital input Disable
+ 'DIDR0_ADC1D': '$2', # ADC1 Digital input Disable
+ 'DIDR0_ADC0D': '$1', # ADC0 Digital input Disable
+
+# Module BOOT_LOAD
+ 'SPMCSR' : '$57', # Store Program Memory Control R
+ 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
+ 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
+ 'SPMCSR_RWWSRE': '$10', # Read While Write section read
+ 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
+ 'SPMCSR_PGWRT': '$4', # Page Write
+ 'SPMCSR_PGERS': '$2', # Page Erase
+ 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
+
+# Module USART0
+ 'UDR0' : '$c6', # USART I/O Data Register
+ 'UCSR0A' : '$c0', # USART Control and Status Regis
+ 'UCSR0A_RXC0': '$80', # USART Receive Complete
+ 'UCSR0A_TXC0': '$40', # USART Transmit Complete
+ 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
+ 'UCSR0A_FE0': '$10', # Framing Error
+ 'UCSR0A_DOR0': '$8', # Data OverRun
+ 'UCSR0A_UPE0': '$4', # USART Parity Error
+ 'UCSR0A_U2X0': '$2', # Double the USART Transmission
+ 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
+ 'UCSR0B' : '$c1', # USART Control and Status Regis
+ 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
+ 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
+ 'UCSR0B_UDRIE0': '$20', # USART Data Register Empty Inte
+ 'UCSR0B_RXEN0': '$10', # Receiver Enable
+ 'UCSR0B_TXEN0': '$8', # Transmitter Enable
+ 'UCSR0B_UCSZ02': '$4', # Character Size
+ 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
+ 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
+ 'UCSR0C' : '$c2', # USART Control and Status Regis
+ 'UCSR0C_UMSEL0': '$40', # USART Mode Select
+ 'UCSR0C_UPM0': '$30', # Parity Mode Bits
+ 'UCSR0C_USBS0': '$8', # Stop Bit Select
+ 'UCSR0C_UCSZ0': '$6', # Character Size
+ 'UCSR0C_UCPOL0': '$1', # Clock Polarity
+ 'UBRR0' : '$c4', # USART Baud Rate Register Byte
+
+# Module CPU
+ 'SREG' : '$5f', # Status Register
+ 'SREG_I': '$80', # Global Interrupt Enable
+ 'SREG_T': '$40', # Bit Copy Storage
+ 'SREG_H': '$20', # Half Carry Flag
+ 'SREG_S': '$10', # Sign Bit
+ 'SREG_V': '$8', # Two's Complement Overflow Flag
+ 'SREG_N': '$4', # Negative Flag
+ 'SREG_Z': '$2', # Zero Flag
+ 'SREG_C': '$1', # Carry Flag
+ 'SP' : '$5d', # Stack Pointer
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_PUD': '$10', # Pull-up disable
+ 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
+ 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+ 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
+ 'MCUSR_BORF': '$4', # Brown-out Reset Flag
+ 'MCUSR_EXTRF': '$2', # External Reset Flag
+ 'MCUSR_PORF': '$1', # Power-on reset flag
+ 'OSCCAL' : '$66', # Oscillator Calibration Value
+ 'CLKPR' : '$61', # Clock Prescale Register
+ 'CLKPR_CLKPCE': '$80', # Clock Prescaler Change Enable
+ 'CLKPR_CLKPS': '$f', # Clock Prescaler Select Bits
+ 'PRR' : '$64', # Power Reduction Register
+ 'PRR_PRTIM1': '$8', # Power Reduction Timer/Counter1
+ 'PRR_PRSPI': '$4', # Power Reduction Serial Periphe
+ 'PRR_PRUSART0': '$2', # Power Reduction USART
+ 'PRR_PRADC': '$1', # Power Reduction ADC
+ 'SMCR' : '$53', # Sleep Mode Control Register
+ 'SMCR_SM': '$e', # Sleep Mode Select bits
+ 'SMCR_SE': '$1', # Sleep Enable
+ 'GPIOR2' : '$4b', # General Purpose IO Register 2
+ 'GPIOR1' : '$4a', # General Purpose IO Register 1
+ 'GPIOR0' : '$3e', # General Purpose IO Register 0
+
+ '__amforth_dummy':'0'
+}
diff --git a/amforth-6.5/avr8/devices/atmega165p/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega165p/words/no-jtag.asm
new file mode 100644
index 0000000..352a4bb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega165p/words/no-jtag.asm
@@ -0,0 +1,14 @@
+; ( -- )
+; ( -- )
+; MCU
+; disable jtag at runtime
+VE_NOJTAG:
+ .dw $FF05
+ .db "-jtag",0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOJTAG
+XT_NOJTAG:
+ .dw PFA_NOJTAG
+PFA_NOJTAG:
+
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega165p/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega165p/words/no-wdt.asm
new file mode 100644
index 0000000..4a12261
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega165p/words/no-wdt.asm
@@ -0,0 +1,22 @@
+; ( -- )
+; MCU
+; disable watch dog timer at runtime
+VE_NOWDT:
+ .dw $ff04
+ .db "-wdt"
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOWDT
+XT_NOWDT:
+ .dw PFA_NOWDT
+PFA_NOWDT:
+
+; Reset WDT
+ wdr
+; Write logical one to WDTOE and WDE
+ in_ temp1, WDTCR
+ ori temp1, (1<<WDTOE)|(1<<WDE)
+ out WDTCR, temp1
+; Turn off WDT
+ ldi temp1, (0<<WDE)
+ out_ WDTCR, temp1
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega165p/words/sleep.asm b/amforth-6.5/avr8/devices/atmega165p/words/sleep.asm
new file mode 100644
index 0000000..256249c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega165p/words/sleep.asm
@@ -0,0 +1,19 @@
+; ( mode -- )
+; MCU
+; put the controller into the specified sleep mode
+VE_SLEEP:
+ .dw $ff05
+ .db "sleep", 0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_SLEEP
+XT_SLEEP:
+ .dw PFA_SLEEP
+PFA_SLEEP:
+ andi tosl, 7 ; leave only legal mode bits
+ lsl tosl ; move to correct location (bits 3-1)
+ ori tosl, 1 ; set the SE bit
+ out_ SMCR, tosl ; set the sleep config
+ sleep ; nighty-night
+ out_ SMCR, zerol ; 0 protects against accidental sleeps
+ loadtos ; pop argument from stack
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega165pa/atmega165pa.frt b/amforth-6.5/avr8/devices/atmega165pa/atmega165pa.frt
new file mode 100644
index 0000000..4a85d66
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega165pa/atmega165pa.frt
@@ -0,0 +1,280 @@
+\ Partname: ATmega165PA
+\ generated automatically
+
+\ TIMER_COUNTER_0
+&68 constant TCCR0A \ Timer/Counter0 Control Register
+ $80 constant TCCR0A_FOC0A \ Force Output Compare
+ $40 constant TCCR0A_WGM00 \ Waveform Generation Mode 0
+ $30 constant TCCR0A_COM0A \ Compare Match Output Modes
+ $08 constant TCCR0A_WGM01 \ Waveform Generation Mode 1
+ $07 constant TCCR0A_CS0 \ Clock Selects
+&70 constant TCNT0 \ Timer/Counter0
+&71 constant OCR0A \ Timer/Counter0 Output Compare Register
+&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
+ $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match Interrupt Enable
+ $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
+&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
+ $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0
+ $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
+&67 constant GTCCR \ General Timer/Control Register
+ $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
+ $01 constant GTCCR_PSR310 \ Prescaler Reset Timer/Counter1 and Timer/Counter0
+\ TIMER_COUNTER_1
+&128 constant TCCR1A \ Timer/Counter1 Control Register A
+ $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
+ $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
+ $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
+&129 constant TCCR1B \ Timer/Counter1 Control Register B
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
+ $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
+&130 constant TCCR1C \ Timer/Counter 1 Control Register C
+ $80 constant TCCR1C_FOC1A \ Force Output Compare 1A
+ $40 constant TCCR1C_FOC1B \ Force Output Compare 1B
+&132 constant TCNT1 \ Timer/Counter1 Bytes
+&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
+&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
+&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
+&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
+ $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
+ $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
+ $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
+ $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
+&54 constant TIFR1 \ Timer/Counter1 Interrupt Flag register
+ $20 constant TIFR1_ICF1 \ Input Capture Flag 1
+ $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
+ $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
+ $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
+\ TIMER_COUNTER_2
+&176 constant TCCR2A \ Timer/Counter2 Control Register
+ $80 constant TCCR2A_FOC2A \ Force Output Compare A
+ $40 constant TCCR2A_WGM20 \ Waveform Generation Mode
+ $30 constant TCCR2A_COM2A \ Compare Output Mode bits
+ $08 constant TCCR2A_WGM21 \ Waveform Generation Mode
+ $07 constant TCCR2A_CS2 \ Clock Select bits
+&178 constant TCNT2 \ Timer/Counter2
+&179 constant OCR2A \ Timer/Counter2 Output Compare Register
+&112 constant TIMSK2 \ Timer/Counter2 Interrupt Mask register
+ $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match Interrupt Enable
+ $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
+&55 constant TIFR2 \ Timer/Counter2 Interrupt Flag Register
+ $02 constant TIFR2_OCF2A \ Timer/Counter2 Output Compare Flag 2
+ $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
+&182 constant ASSR \ Asynchronous Status Register
+ $10 constant ASSR_EXCLK \ Enable External Clock Interrupt
+ $08 constant ASSR_AS2 \ AS2: Asynchronous Timer/Counter2
+ $04 constant ASSR_TCN2UB \ TCN2UB: Timer/Counter2 Update Busy
+ $02 constant ASSR_OCR2UB \ Output Compare Register2 Update Busy
+ $01 constant ASSR_TCR2UB \ TCR2UB: Timer/Counter Control Register2 Update Busy
+\ WATCHDOG
+&96 constant WDTCR \ Watchdog Timer Control Register
+ $10 constant WDTCR_WDCE \ Watchdog Change Enable
+ $08 constant WDTCR_WDE \ Watch Dog Enable
+ $07 constant WDTCR_WDP \ Watch Dog Timer Prescaler bits
+\ EEPROM
+&65 constant EEAR \ EEPROM Address Register Bytes
+&64 constant EEDR \ EEPROM Data Register
+&63 constant EECR \ EEPROM Control Register
+ $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
+ $04 constant EECR_EEMWE \ EEPROM Master Write Enable
+ $02 constant EECR_EEWE \ EEPROM Write Enable
+ $01 constant EECR_EERE \ EEPROM Read Enable
+\ SPI
+&76 constant SPCR \ SPI Control Register
+ $80 constant SPCR_SPIE \ SPI Interrupt Enable
+ $40 constant SPCR_SPE \ SPI Enable
+ $20 constant SPCR_DORD \ Data Order
+ $10 constant SPCR_MSTR \ Master/Slave Select
+ $08 constant SPCR_CPOL \ Clock polarity
+ $04 constant SPCR_CPHA \ Clock Phase
+ $03 constant SPCR_SPR \ SPI Clock Rate Selects
+&77 constant SPSR \ SPI Status Register
+ $80 constant SPSR_SPIF \ SPI Interrupt Flag
+ $40 constant SPSR_WCOL \ Write Collision Flag
+ $01 constant SPSR_SPI2X \ Double SPI Speed Bit
+&78 constant SPDR \ SPI Data Register
+\ PORTA
+&34 constant PORTA \ Port A Data Register
+&33 constant DDRA \ Port A Data Direction Register
+&32 constant PINA \ Port A Input Pins
+\ PORTB
+&37 constant PORTB \ Port B Data Register
+&36 constant DDRB \ Port B Data Direction Register
+&35 constant PINB \ Port B Input Pins
+\ PORTC
+&40 constant PORTC \ Port C Data Register
+&39 constant DDRC \ Port C Data Direction Register
+&38 constant PINC \ Port C Input Pins
+\ PORTD
+&43 constant PORTD \ Port D Data Register
+&42 constant DDRD \ Port D Data Direction Register
+&41 constant PIND \ Port D Input Pins
+\ ANALOG_COMPARATOR
+&123 constant ADCSRB \ ADC Control and Status Register B
+ $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer Enable
+&80 constant ACSR \ Analog Comparator Control And Status Register
+ $80 constant ACSR_ACD \ Analog Comparator Disable
+ $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
+ $20 constant ACSR_ACO \ Analog Compare Output
+ $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
+ $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
+ $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
+ $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
+&127 constant DIDR1 \ Digital Input Disable Register 1
+ $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
+ $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
+\ PORTE
+&46 constant PORTE \ Data Register, Port E
+&45 constant DDRE \ Data Direction Register, Port E
+&44 constant PINE \ Input Pins, Port E
+\ PORTF
+&49 constant PORTF \ Data Register, Port F
+&48 constant DDRF \ Data Direction Register, Port F
+&47 constant PINF \ Input Pins, Port F
+\ PORTG
+&52 constant PORTG \ Port G Data Register
+&51 constant DDRG \ Port G Data Direction Register
+&50 constant PING \ Port G Input Pins
+\ JTAG
+&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
+&85 constant MCUCR \ MCU Control Register
+ $80 constant MCUCR_JTD \ JTAG Interface Disable
+&84 constant MCUSR \ MCU Status Register
+ $10 constant MCUSR_JTRF \ JTAG Reset Flag
+\ USI
+&186 constant USIDR \ USI Data Register
+&185 constant USISR \ USI Status Register
+ $80 constant USISR_USISIF \ Start Condition Interrupt Flag
+ $40 constant USISR_USIOIF \ Counter Overflow Interrupt Flag
+ $20 constant USISR_USIPF \ Stop Condition Flag
+ $10 constant USISR_USIDC \ Data Output Collision
+ $0F constant USISR_USICNT \ USI Counter Value Bits
+&184 constant USICR \ USI Control Register
+ $80 constant USICR_USISIE \ Start Condition Interrupt Enable
+ $40 constant USICR_USIOIE \ Counter Overflow Interrupt Enable
+ $30 constant USICR_USIWM \ USI Wire Mode Bits
+ $0C constant USICR_USICS \ USI Clock Source Select Bits
+ $02 constant USICR_USICLK \ Clock Strobe
+ $01 constant USICR_USITC \ Toggle Clock Port Pin
+\ AD_CONVERTER
+&124 constant ADMUX \ The ADC multiplexer Selection Register
+ $C0 constant ADMUX_REFS \ Reference Selection Bits
+ $20 constant ADMUX_ADLAR \ Left Adjust Result
+ $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
+&122 constant ADCSRA \ The ADC Control and Status register
+ $80 constant ADCSRA_ADEN \ ADC Enable
+ $40 constant ADCSRA_ADSC \ ADC Start Conversion
+ $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
+ $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
+ $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
+ $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
+&120 constant ADC \ ADC Data Register Bytes
+&126 constant DIDR0 \ Digital Input Disable Register 0
+ $80 constant DIDR0_ADC7D \ ADC7 Digital input Disable
+ $40 constant DIDR0_ADC6D \ ADC6 Digital input Disable
+ $20 constant DIDR0_ADC5D \ ADC5 Digital input Disable
+ $10 constant DIDR0_ADC4D \ ADC4 Digital input Disable
+ $08 constant DIDR0_ADC3D \ ADC3 Digital input Disable
+ $04 constant DIDR0_ADC2D \ ADC2 Digital input Disable
+ $02 constant DIDR0_ADC1D \ ADC1 Digital input Disable
+ $01 constant DIDR0_ADC0D \ ADC0 Digital input Disable
+\ BOOT_LOAD
+&87 constant SPMCSR \ Store Program Memory Control Register
+ $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
+ $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
+ $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
+ $04 constant SPMCSR_PGWRT \ Page Write
+ $02 constant SPMCSR_PGERS \ Page Erase
+ $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
+\ USART0
+&198 constant UDR0 \ USART I/O Data Register
+&192 constant UCSR0A \ USART Control and Status Register A
+ $80 constant UCSR0A_RXC0 \ USART Receive Complete
+ $40 constant UCSR0A_TXC0 \ USART Transmit Complete
+ $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
+ $10 constant UCSR0A_FE0 \ Framing Error
+ $08 constant UCSR0A_DOR0 \ Data OverRun
+ $04 constant UCSR0A_UPE0 \ USART Parity Error
+ $02 constant UCSR0A_U2X0 \ Double the USART Transmission Speed
+ $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
+&193 constant UCSR0B \ USART Control and Status Register B
+ $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
+ $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
+ $20 constant UCSR0B_UDRIE0 \ USART Data Register Empty Interrupt Enable
+ $10 constant UCSR0B_RXEN0 \ Receiver Enable
+ $08 constant UCSR0B_TXEN0 \ Transmitter Enable
+ $04 constant UCSR0B_UCSZ02 \ Character Size
+ $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
+ $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
+&194 constant UCSR0C \ USART Control and Status Register C
+ $40 constant UCSR0C_UMSEL0 \ USART Mode Select
+ $30 constant UCSR0C_UPM0 \ Parity Mode Bits
+ $08 constant UCSR0C_USBS0 \ Stop Bit Select
+ $06 constant UCSR0C_UCSZ0 \ Character Size
+ $01 constant UCSR0C_UCPOL0 \ Clock Polarity
+&196 constant UBRR0 \ USART Baud Rate Register Bytes
+\ EXTERNAL_INTERRUPT
+&105 constant EICRA \ External Interrupt Control Register
+ $02 constant EICRA_ISC01 \ External Interrupt Sense Control 0 Bit 1
+ $01 constant EICRA_ISC00 \ External Interrupt Sense Control 0 Bit 0
+&61 constant EIMSK \ External Interrupt Mask Register
+ $30 constant EIMSK_PCIE \ Pin Change Interrupt Enables
+ $01 constant EIMSK_INT0 \ External Interrupt Request 0 Enable
+&60 constant EIFR \ External Interrupt Flag Register
+ $30 constant EIFR_PCIF \ Pin Change Interrupt Flags
+ $01 constant EIFR_INTF0 \ External Interrupt Flag 0
+&108 constant PCMSK1 \ Pin Change Mask Register 1
+ $FF constant PCMSK1_PCINT \ Pin Change Enable Masks
+&107 constant PCMSK0 \ Pin Change Mask Register 0
+ $FF constant PCMSK0_PCINT \ Pin Change Enable Masks
+\ CPU
+&95 constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ $08 constant SREG_V \ Two's Complement Overflow Flag
+ $04 constant SREG_N \ Negative Flag
+ $02 constant SREG_Z \ Zero Flag
+ $01 constant SREG_C \ Carry Flag
+&93 constant SP \ Stack Pointer
+&102 constant OSCCAL \ Oscillator Calibration Value
+&97 constant CLKPR \ Clock Prescale Register
+ $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable
+ $0F constant CLKPR_CLKPS \ Clock Prescaler Select Bits
+&100 constant PRR \ Power Reduction Register
+ $08 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
+ $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
+ $02 constant PRR_PRUSART0 \ Power Reduction USART
+ $01 constant PRR_PRADC \ Power Reduction ADC
+&83 constant SMCR \ Sleep Mode Control Register
+ $0E constant SMCR_SM \ Sleep Mode Select bits
+ $01 constant SMCR_SE \ Sleep Enable
+&75 constant GPIOR2 \ General Purpose IO Register 2
+&74 constant GPIOR1 \ General Purpose IO Register 1
+&62 constant GPIOR0 \ General Purpose IO Register 0
+
+\ Interrupts
+&2 constant INT0Addr \ External Interrupt Request 0
+&4 constant PCINT0Addr \ Pin Change Interrupt Request 0
+&6 constant PCINT1Addr \ Pin Change Interrupt Request 1
+&8 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
+&10 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
+&12 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+&14 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
+&16 constant TIMER1_COMPBAddr \ Timer/Counter Compare Match B
+&18 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+&20 constant TIMER0_COMPAddr \ Timer/Counter0 Compare Match
+&22 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
+&24 constant SPI__STCAddr \ SPI Serial Transfer Complete
+&26 constant USART0__RXAddr \ USART0, Rx Complete
+&28 constant USART0__UDREAddr \ USART0 Data register Empty
+&30 constant USART0__TXAddr \ USART0, Tx Complete
+&32 constant USI_STARTAddr \ USI Start Condition
+&34 constant USI_OVERFLOWAddr \ USI Overflow
+&36 constant ANALOG_COMPAddr \ Analog Comparator
+&38 constant ADCAddr \ ADC Conversion Complete
+&40 constant EE_READYAddr \ EEPROM Ready
+&42 constant SPM_READYAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/atmega165pa/device.asm b/amforth-6.5/avr8/devices/atmega165pa/device.asm
new file mode 100644
index 0000000..3d624b8
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega165pa/device.asm
@@ -0,0 +1,106 @@
+; Partname: ATmega165PA
+; generated automatically, do not edit
+
+.nolist
+ .include "m165PAdef.inc"
+.list
+
+.equ ramstart = 256
+.equ CELLSIZE = 2
+.macro readflashcell
+ lsl zl
+ rol zh
+ lpm @0, Z+
+ lpm @1, Z+
+.endmacro
+.macro writeflashcell
+ lsl zl
+ rol zh
+.endmacro
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_TIMER_COUNTER_2 = 0
+.set WANT_WATCHDOG = 0
+.set WANT_EEPROM = 0
+.set WANT_SPI = 0
+.set WANT_PORTA = 0
+.set WANT_PORTB = 0
+.set WANT_PORTC = 0
+.set WANT_PORTD = 0
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_PORTE = 0
+.set WANT_PORTF = 0
+.set WANT_PORTG = 0
+.set WANT_JTAG = 0
+.set WANT_USI = 0
+.set WANT_AD_CONVERTER = 0
+.set WANT_BOOT_LOAD = 0
+.set WANT_USART0 = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_CPU = 0
+.equ intvecsize = 2 ; please verify; flash size: 16384 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.org 2
+ rcall isr ; External Interrupt Request 0
+.org 4
+ rcall isr ; Pin Change Interrupt Request 0
+.org 6
+ rcall isr ; Pin Change Interrupt Request 1
+.org 8
+ rcall isr ; Timer/Counter2 Compare Match
+.org 10
+ rcall isr ; Timer/Counter2 Overflow
+.org 12
+ rcall isr ; Timer/Counter1 Capture Event
+.org 14
+ rcall isr ; Timer/Counter1 Compare Match A
+.org 16
+ rcall isr ; Timer/Counter Compare Match B
+.org 18
+ rcall isr ; Timer/Counter1 Overflow
+.org 20
+ rcall isr ; Timer/Counter0 Compare Match
+.org 22
+ rcall isr ; Timer/Counter0 Overflow
+.org 24
+ rcall isr ; SPI Serial Transfer Complete
+.org 26
+ rcall isr ; USART0, Rx Complete
+.org 28
+ rcall isr ; USART0 Data register Empty
+.org 30
+ rcall isr ; USART0, Tx Complete
+.org 32
+ rcall isr ; USI Start Condition
+.org 34
+ rcall isr ; USI Overflow
+.org 36
+ rcall isr ; Analog Comparator
+.org 38
+ rcall isr ; ADC Conversion Complete
+.org 40
+ rcall isr ; EEPROM Ready
+.org 42
+ rcall isr ; Store Program Memory Read
+.equ INTVECTORS = 22
+.nooverlap
+
+; compatability layer (maybe empty)
+.equ EEPE = EEWE
+.equ EEMPE = EEMWE
+
+; controller data area, environment query mcu-info
+mcu_info:
+mcu_ramsize:
+ .dw 1024
+mcu_eepromsize:
+ .dw 512
+mcu_maxdp:
+ .dw 14336
+mcu_numints:
+ .dw 22
+mcu_name:
+ .dw 11
+ .db "ATmega165PA",0
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega165pa/device.inc b/amforth-6.5/avr8/devices/atmega165pa/device.inc
new file mode 100644
index 0000000..311d06f
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega165pa/device.inc
@@ -0,0 +1,1050 @@
+; Partname: ATmega165PA
+; generated automatically, no not edit
+
+.if WANT_TIMER_COUNTER_0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Control Register
+VE_TCCR0A:
+ .dw $ff06
+ .db "TCCR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0A
+XT_TCCR0A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0A:
+ .dw 68
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw 70
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0A:
+ .dw $ff05
+ .db "OCR0A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0A
+XT_OCR0A:
+ .dw PFA_DOVARIABLE
+PFA_OCR0A:
+ .dw 71
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Mask Register
+VE_TIMSK0:
+ .dw $ff06
+ .db "TIMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK0
+XT_TIMSK0:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK0:
+ .dw 110
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Flag register
+VE_TIFR0:
+ .dw $ff05
+ .db "TIFR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR0
+XT_TIFR0:
+ .dw PFA_DOVARIABLE
+PFA_TIFR0:
+ .dw 53
+; ( -- addr ) System Constant
+; R( -- )
+; General Timer/Control Register
+VE_GTCCR:
+ .dw $ff05
+ .db "GTCCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GTCCR
+XT_GTCCR:
+ .dw PFA_DOVARIABLE
+PFA_GTCCR:
+ .dw 67
+
+.endif
+.if WANT_TIMER_COUNTER_1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw 128
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw 129
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter 1 Control Register C
+VE_TCCR1C:
+ .dw $ff06
+ .db "TCCR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1C
+XT_TCCR1C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1C:
+ .dw 130
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Bytes
+VE_TCNT1:
+ .dw $ff05
+ .db "TCNT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1
+XT_TCNT1:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1:
+ .dw 132
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register A Bytes
+VE_OCR1A:
+ .dw $ff05
+ .db "OCR1A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1A
+XT_OCR1A:
+ .dw PFA_DOVARIABLE
+PFA_OCR1A:
+ .dw 136
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register B Bytes
+VE_OCR1B:
+ .dw $ff05
+ .db "OCR1B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1B
+XT_OCR1B:
+ .dw PFA_DOVARIABLE
+PFA_OCR1B:
+ .dw 138
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Bytes
+VE_ICR1:
+ .dw $ff04
+ .db "ICR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1
+XT_ICR1:
+ .dw PFA_DOVARIABLE
+PFA_ICR1:
+ .dw 134
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Mask Register
+VE_TIMSK1:
+ .dw $ff06
+ .db "TIMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK1
+XT_TIMSK1:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK1:
+ .dw 111
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Flag register
+VE_TIFR1:
+ .dw $ff05
+ .db "TIFR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR1
+XT_TIFR1:
+ .dw PFA_DOVARIABLE
+PFA_TIFR1:
+ .dw 54
+
+.endif
+.if WANT_TIMER_COUNTER_2 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register
+VE_TCCR2A:
+ .dw $ff06
+ .db "TCCR2A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2A
+XT_TCCR2A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2A:
+ .dw 176
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2
+VE_TCNT2:
+ .dw $ff05
+ .db "TCNT2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT2
+XT_TCNT2:
+ .dw PFA_DOVARIABLE
+PFA_TCNT2:
+ .dw 178
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register
+VE_OCR2A:
+ .dw $ff05
+ .db "OCR2A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2A
+XT_OCR2A:
+ .dw PFA_DOVARIABLE
+PFA_OCR2A:
+ .dw 179
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Interrupt Mask register
+VE_TIMSK2:
+ .dw $ff06
+ .db "TIMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK2
+XT_TIMSK2:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK2:
+ .dw 112
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Interrupt Flag Register
+VE_TIFR2:
+ .dw $ff05
+ .db "TIFR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR2
+XT_TIFR2:
+ .dw PFA_DOVARIABLE
+PFA_TIFR2:
+ .dw 55
+; ( -- addr ) System Constant
+; R( -- )
+; Asynchronous Status Register
+VE_ASSR:
+ .dw $ff04
+ .db "ASSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ASSR
+XT_ASSR:
+ .dw PFA_DOVARIABLE
+PFA_ASSR:
+ .dw 182
+
+.endif
+.if WANT_WATCHDOG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCR:
+ .dw $ff05
+ .db "WDTCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCR
+XT_WDTCR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCR:
+ .dw 96
+
+.endif
+.if WANT_EEPROM == 1
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Address Register Bytes
+VE_EEAR:
+ .dw $ff04
+ .db "EEAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEAR
+XT_EEAR:
+ .dw PFA_DOVARIABLE
+PFA_EEAR:
+ .dw 65
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw 64
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw 63
+
+.endif
+.if WANT_SPI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR:
+ .dw $ff04
+ .db "SPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR
+XT_SPCR:
+ .dw PFA_DOVARIABLE
+PFA_SPCR:
+ .dw 76
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR:
+ .dw $ff04
+ .db "SPSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR
+XT_SPSR:
+ .dw PFA_DOVARIABLE
+PFA_SPSR:
+ .dw 77
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR:
+ .dw $ff04
+ .db "SPDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR
+XT_SPDR:
+ .dw PFA_DOVARIABLE
+PFA_SPDR:
+ .dw 78
+
+.endif
+.if WANT_PORTA == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Register
+VE_PORTA:
+ .dw $ff05
+ .db "PORTA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTA
+XT_PORTA:
+ .dw PFA_DOVARIABLE
+PFA_PORTA:
+ .dw 34
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Direction Register
+VE_DDRA:
+ .dw $ff04
+ .db "DDRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRA
+XT_DDRA:
+ .dw PFA_DOVARIABLE
+PFA_DDRA:
+ .dw 33
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Input Pins
+VE_PINA:
+ .dw $ff04
+ .db "PINA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINA
+XT_PINA:
+ .dw PFA_DOVARIABLE
+PFA_PINA:
+ .dw 32
+
+.endif
+.if WANT_PORTB == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw 37
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw 36
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw 35
+
+.endif
+.if WANT_PORTC == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Register
+VE_PORTC:
+ .dw $ff05
+ .db "PORTC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTC
+XT_PORTC:
+ .dw PFA_DOVARIABLE
+PFA_PORTC:
+ .dw 40
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Direction Register
+VE_DDRC:
+ .dw $ff04
+ .db "DDRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRC
+XT_DDRC:
+ .dw PFA_DOVARIABLE
+PFA_DDRC:
+ .dw 39
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Input Pins
+VE_PINC:
+ .dw $ff04
+ .db "PINC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINC
+XT_PINC:
+ .dw PFA_DOVARIABLE
+PFA_PINC:
+ .dw 38
+
+.endif
+.if WANT_PORTD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw 43
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw 42
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw 41
+
+.endif
+.if WANT_ANALOG_COMPARATOR == 1
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Control and Status Register B
+VE_ADCSRB:
+ .dw $ff06
+ .db "ADCSRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRB
+XT_ADCSRB:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRB:
+ .dw 123
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Control And Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw 80
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 1
+VE_DIDR1:
+ .dw $ff05
+ .db "DIDR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR1
+XT_DIDR1:
+ .dw PFA_DOVARIABLE
+PFA_DIDR1:
+ .dw 127
+
+.endif
+.if WANT_PORTE == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port E
+VE_PORTE:
+ .dw $ff05
+ .db "PORTE",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTE
+XT_PORTE:
+ .dw PFA_DOVARIABLE
+PFA_PORTE:
+ .dw 46
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port E
+VE_DDRE:
+ .dw $ff04
+ .db "DDRE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRE
+XT_DDRE:
+ .dw PFA_DOVARIABLE
+PFA_DDRE:
+ .dw 45
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port E
+VE_PINE:
+ .dw $ff04
+ .db "PINE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINE
+XT_PINE:
+ .dw PFA_DOVARIABLE
+PFA_PINE:
+ .dw 44
+
+.endif
+.if WANT_PORTF == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port F
+VE_PORTF:
+ .dw $ff05
+ .db "PORTF",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTF
+XT_PORTF:
+ .dw PFA_DOVARIABLE
+PFA_PORTF:
+ .dw 49
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port F
+VE_DDRF:
+ .dw $ff04
+ .db "DDRF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRF
+XT_DDRF:
+ .dw PFA_DOVARIABLE
+PFA_DDRF:
+ .dw 48
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port F
+VE_PINF:
+ .dw $ff04
+ .db "PINF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINF
+XT_PINF:
+ .dw PFA_DOVARIABLE
+PFA_PINF:
+ .dw 47
+
+.endif
+.if WANT_PORTG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Data Register
+VE_PORTG:
+ .dw $ff05
+ .db "PORTG",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTG
+XT_PORTG:
+ .dw PFA_DOVARIABLE
+PFA_PORTG:
+ .dw 52
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Data Direction Register
+VE_DDRG:
+ .dw $ff04
+ .db "DDRG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRG
+XT_DDRG:
+ .dw PFA_DOVARIABLE
+PFA_DDRG:
+ .dw 51
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Input Pins
+VE_PING:
+ .dw $ff04
+ .db "PING"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PING
+XT_PING:
+ .dw PFA_DOVARIABLE
+PFA_PING:
+ .dw 50
+
+.endif
+.if WANT_JTAG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; On-Chip Debug Related Register in I/O Memory
+VE_OCDR:
+ .dw $ff04
+ .db "OCDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCDR
+XT_OCDR:
+ .dw PFA_DOVARIABLE
+PFA_OCDR:
+ .dw 81
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw 85
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Status Register
+VE_MCUSR:
+ .dw $ff05
+ .db "MCUSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUSR
+XT_MCUSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUSR:
+ .dw 84
+
+.endif
+.if WANT_USI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USI Data Register
+VE_USIDR:
+ .dw $ff05
+ .db "USIDR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USIDR
+XT_USIDR:
+ .dw PFA_DOVARIABLE
+PFA_USIDR:
+ .dw 186
+; ( -- addr ) System Constant
+; R( -- )
+; USI Status Register
+VE_USISR:
+ .dw $ff05
+ .db "USISR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USISR
+XT_USISR:
+ .dw PFA_DOVARIABLE
+PFA_USISR:
+ .dw 185
+; ( -- addr ) System Constant
+; R( -- )
+; USI Control Register
+VE_USICR:
+ .dw $ff05
+ .db "USICR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USICR
+XT_USICR:
+ .dw PFA_DOVARIABLE
+PFA_USICR:
+ .dw 184
+
+.endif
+.if WANT_AD_CONVERTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC multiplexer Selection Register
+VE_ADMUX:
+ .dw $ff05
+ .db "ADMUX",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADMUX
+XT_ADMUX:
+ .dw PFA_DOVARIABLE
+PFA_ADMUX:
+ .dw 124
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register
+VE_ADCSRA:
+ .dw $ff06
+ .db "ADCSRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRA
+XT_ADCSRA:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRA:
+ .dw 122
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register Bytes
+VE_ADC:
+ .dw $ff03
+ .db "ADC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADC
+XT_ADC:
+ .dw PFA_DOVARIABLE
+PFA_ADC:
+ .dw 120
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 0
+VE_DIDR0:
+ .dw $ff05
+ .db "DIDR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR0
+XT_DIDR0:
+ .dw PFA_DOVARIABLE
+PFA_DIDR0:
+ .dw 126
+
+.endif
+.if WANT_BOOT_LOAD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control Register
+VE_SPMCSR:
+ .dw $ff06
+ .db "SPMCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCSR
+XT_SPMCSR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCSR:
+ .dw 87
+
+.endif
+.if WANT_USART0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR0:
+ .dw $ff04
+ .db "UDR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR0
+XT_UDR0:
+ .dw PFA_DOVARIABLE
+PFA_UDR0:
+ .dw 198
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR0A:
+ .dw $ff06
+ .db "UCSR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0A
+XT_UCSR0A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0A:
+ .dw 192
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR0B:
+ .dw $ff06
+ .db "UCSR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0B
+XT_UCSR0B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0B:
+ .dw 193
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR0C:
+ .dw $ff06
+ .db "UCSR0C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0C
+XT_UCSR0C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0C:
+ .dw 194
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Bytes
+VE_UBRR0:
+ .dw $ff05
+ .db "UBRR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR0
+XT_UBRR0:
+ .dw PFA_DOVARIABLE
+PFA_UBRR0:
+ .dw 196
+
+.endif
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register
+VE_EICRA:
+ .dw $ff05
+ .db "EICRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRA
+XT_EICRA:
+ .dw PFA_DOVARIABLE
+PFA_EICRA:
+ .dw 105
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Mask Register
+VE_EIMSK:
+ .dw $ff05
+ .db "EIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIMSK
+XT_EIMSK:
+ .dw PFA_DOVARIABLE
+PFA_EIMSK:
+ .dw 61
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Flag Register
+VE_EIFR:
+ .dw $ff04
+ .db "EIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIFR
+XT_EIFR:
+ .dw PFA_DOVARIABLE
+PFA_EIFR:
+ .dw 60
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 1
+VE_PCMSK1:
+ .dw $ff06
+ .db "PCMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK1
+XT_PCMSK1:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK1:
+ .dw 108
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 0
+VE_PCMSK0:
+ .dw $ff06
+ .db "PCMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK0
+XT_PCMSK0:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK0:
+ .dw 107
+
+.endif
+.if WANT_CPU == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw 95
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer
+VE_SP:
+ .dw $ff02
+ .db "SP"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SP
+XT_SP:
+ .dw PFA_DOVARIABLE
+PFA_SP:
+ .dw 93
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Calibration Value
+VE_OSCCAL:
+ .dw $ff06
+ .db "OSCCAL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSCCAL
+XT_OSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_OSCCAL:
+ .dw 102
+; ( -- addr ) System Constant
+; R( -- )
+; Clock Prescale Register
+VE_CLKPR:
+ .dw $ff05
+ .db "CLKPR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKPR
+XT_CLKPR:
+ .dw PFA_DOVARIABLE
+PFA_CLKPR:
+ .dw 97
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register
+VE_PRR:
+ .dw $ff03
+ .db "PRR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR
+XT_PRR:
+ .dw PFA_DOVARIABLE
+PFA_PRR:
+ .dw 100
+; ( -- addr ) System Constant
+; R( -- )
+; Sleep Mode Control Register
+VE_SMCR:
+ .dw $ff04
+ .db "SMCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SMCR
+XT_SMCR:
+ .dw PFA_DOVARIABLE
+PFA_SMCR:
+ .dw 83
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 2
+VE_GPIOR2:
+ .dw $ff06
+ .db "GPIOR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR2
+XT_GPIOR2:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR2:
+ .dw 75
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 1
+VE_GPIOR1:
+ .dw $ff06
+ .db "GPIOR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR1
+XT_GPIOR1:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR1:
+ .dw 74
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 0
+VE_GPIOR0:
+ .dw $ff06
+ .db "GPIOR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR0
+XT_GPIOR0:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR0:
+ .dw 62
+
+.endif
diff --git a/amforth-6.5/avr8/devices/atmega165pa/device.py b/amforth-6.5/avr8/devices/atmega165pa/device.py
new file mode 100644
index 0000000..f970f06
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega165pa/device.py
@@ -0,0 +1,321 @@
+# Generated Automatically
+
+# Partname ATmega165PA
+
+MCUREGS = {
+# Interrupt Vectors
+ 'INT0Addr' : '#2', # External Interrupt Request 0
+ 'PCINT0Addr' : '#4', # Pin Change Interrupt Request 0
+ 'PCINT1Addr' : '#6', # Pin Change Interrupt Request 1
+ 'TIMER2_COMPAddr' : '#8', # Timer/Counter2 Compare Match
+ 'TIMER2_OVFAddr' : '#10', # Timer/Counter2 Overflow
+ 'TIMER1_CAPTAddr' : '#12', # Timer/Counter1 Capture Event
+ 'TIMER1_COMPAAddr' : '#14', # Timer/Counter1 Compare Match A
+ 'TIMER1_COMPBAddr' : '#16', # Timer/Counter Compare Match B
+ 'TIMER1_OVFAddr' : '#18', # Timer/Counter1 Overflow
+ 'TIMER0_COMPAddr' : '#20', # Timer/Counter0 Compare Match
+ 'TIMER0_OVFAddr' : '#22', # Timer/Counter0 Overflow
+ 'SPI_STCAddr' : '#24', # SPI Serial Transfer Complete
+ 'USART0_RXAddr' : '#26', # USART0, Rx Complete
+ 'USART0_UDREAddr' : '#28', # USART0 Data register Empty
+ 'USART0_TXAddr' : '#30', # USART0, Tx Complete
+ 'USI_STARTAddr' : '#32', # USI Start Condition
+ 'USI_OVERFLOWAddr' : '#34', # USI Overflow
+ 'ANALOG_COMPAddr' : '#36', # Analog Comparator
+ 'ADCAddr' : '#38', # ADC Conversion Complete
+ 'EE_READYAddr' : '#40', # EEPROM Ready
+ 'SPM_READYAddr' : '#42', # Store Program Memory Read
+
+# Module TIMER_COUNTER_0
+ 'TCCR0A' : '$44', # Timer/Counter0 Control Registe
+ 'TCCR0A_FOC0A': '$80', # Force Output Compare
+ 'TCCR0A_WGM00': '$40', # Waveform Generation Mode 0
+ 'TCCR0A_COM0A': '$30', # Compare Match Output Modes
+ 'TCCR0A_WGM01': '$8', # Waveform Generation Mode 1
+ 'TCCR0A_CS0': '$7', # Clock Selects
+ 'TCNT0' : '$46', # Timer/Counter0
+ 'OCR0A' : '$47', # Timer/Counter0 Output Compare
+ 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
+ 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
+ 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
+ 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
+ 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
+ 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Control Register
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSR310': '$1', # Prescaler Reset Timer/Counter1
+
+# Module TIMER_COUNTER_1
+ 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
+ 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
+ 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
+ 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
+ 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
+ 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
+ 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
+ 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
+ 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
+ 'TCCR1C' : '$82', # Timer/Counter 1 Control Regist
+ 'TCCR1C_FOC1A': '$80', # Force Output Compare 1A
+ 'TCCR1C_FOC1B': '$40', # Force Output Compare 1B
+ 'TCNT1' : '$84', # Timer/Counter1 Bytes
+ 'OCR1A' : '$88', # Timer/Counter1 Output Compare
+ 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
+ 'ICR1' : '$86', # Timer/Counter1 Input Capture R
+ 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
+ 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
+ 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
+ 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
+ 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
+ 'TIFR1' : '$36', # Timer/Counter1 Interrupt Flag
+ 'TIFR1_ICF1': '$20', # Input Capture Flag 1
+ 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
+ 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
+ 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
+
+# Module TIMER_COUNTER_2
+ 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
+ 'TCCR2A_FOC2A': '$80', # Force Output Compare A
+ 'TCCR2A_WGM20': '$40', # Waveform Generation Mode
+ 'TCCR2A_COM2A': '$30', # Compare Output Mode bits
+ 'TCCR2A_WGM21': '$8', # Waveform Generation Mode
+ 'TCCR2A_CS2': '$7', # Clock Select bits
+ 'TCNT2' : '$b2', # Timer/Counter2
+ 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
+ 'TIMSK2' : '$70', # Timer/Counter2 Interrupt Mask
+ 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
+ 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
+ 'TIFR2' : '$37', # Timer/Counter2 Interrupt Flag
+ 'TIFR2_OCF2A': '$2', # Timer/Counter2 Output Compare
+ 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_PSR2': '$2', # Prescaler Reset Timer/Counter2
+ 'ASSR' : '$b6', # Asynchronous Status Register
+ 'ASSR_EXCLK': '$10', # Enable External Clock Interrup
+ 'ASSR_AS2': '$8', # AS2: Asynchronous Timer/Counte
+ 'ASSR_TCN2UB': '$4', # TCN2UB: Timer/Counter2 Update
+ 'ASSR_OCR2UB': '$2', # Output Compare Register2 Updat
+ 'ASSR_TCR2UB': '$1', # TCR2UB: Timer/Counter Control
+
+# Module WATCHDOG
+ 'WDTCR' : '$60', # Watchdog Timer Control Registe
+ 'WDTCR_WDCE': '$10', # Watchdog Change Enable
+ 'WDTCR_WDE': '$8', # Watch Dog Enable
+ 'WDTCR_WDP': '$7', # Watch Dog Timer Prescaler bits
+
+# Module EEPROM
+ 'EEAR' : '$41', # EEPROM Address Register Bytes
+ 'EEDR' : '$40', # EEPROM Data Register
+ 'EECR' : '$3f', # EEPROM Control Register
+ 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
+ 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
+ 'EECR_EEWE': '$2', # EEPROM Write Enable
+ 'EECR_EERE': '$1', # EEPROM Read Enable
+
+# Module SPI
+ 'SPCR' : '$4c', # SPI Control Register
+ 'SPCR_SPIE': '$80', # SPI Interrupt Enable
+ 'SPCR_SPE': '$40', # SPI Enable
+ 'SPCR_DORD': '$20', # Data Order
+ 'SPCR_MSTR': '$10', # Master/Slave Select
+ 'SPCR_CPOL': '$8', # Clock polarity
+ 'SPCR_CPHA': '$4', # Clock Phase
+ 'SPCR_SPR': '$3', # SPI Clock Rate Selects
+ 'SPSR' : '$4d', # SPI Status Register
+ 'SPSR_SPIF': '$80', # SPI Interrupt Flag
+ 'SPSR_WCOL': '$40', # Write Collision Flag
+ 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
+ 'SPDR' : '$4e', # SPI Data Register
+
+# Module PORTA
+ 'PORTA' : '$22', # Port A Data Register
+ 'DDRA' : '$21', # Port A Data Direction Register
+ 'PINA' : '$20', # Port A Input Pins
+
+# Module PORTB
+ 'PORTB' : '$25', # Port B Data Register
+ 'DDRB' : '$24', # Port B Data Direction Register
+ 'PINB' : '$23', # Port B Input Pins
+
+# Module PORTC
+ 'PORTC' : '$28', # Port C Data Register
+ 'DDRC' : '$27', # Port C Data Direction Register
+ 'PINC' : '$26', # Port C Input Pins
+
+# Module PORTD
+ 'PORTD' : '$2b', # Port D Data Register
+ 'DDRD' : '$2a', # Port D Data Direction Register
+ 'PIND' : '$29', # Port D Input Pins
+
+# Module ANALOG_COMPARATOR
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
+ 'ACSR' : '$50', # Analog Comparator Control And
+ 'ACSR_ACD': '$80', # Analog Comparator Disable
+ 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
+ 'ACSR_ACO': '$20', # Analog Compare Output
+ 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
+ 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
+ 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
+ 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
+ 'DIDR1' : '$7f', # Digital Input Disable Register
+ 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
+ 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
+
+# Module PORTE
+ 'PORTE' : '$2e', # Data Register, Port E
+ 'DDRE' : '$2d', # Data Direction Register, Port
+ 'PINE' : '$2c', # Input Pins, Port E
+
+# Module PORTF
+ 'PORTF' : '$31', # Data Register, Port F
+ 'DDRF' : '$30', # Data Direction Register, Port
+ 'PINF' : '$2f', # Input Pins, Port F
+
+# Module PORTG
+ 'PORTG' : '$34', # Port G Data Register
+ 'DDRG' : '$33', # Port G Data Direction Register
+ 'PING' : '$32', # Port G Input Pins
+
+# Module JTAG
+ 'OCDR' : '$51', # On-Chip Debug Related Register
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_JTD': '$80', # JTAG Interface Disable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+
+# Module USI
+ 'USIDR' : '$ba', # USI Data Register
+ 'USISR' : '$b9', # USI Status Register
+ 'USISR_USISIF': '$80', # Start Condition Interrupt Flag
+ 'USISR_USIOIF': '$40', # Counter Overflow Interrupt Fla
+ 'USISR_USIPF': '$20', # Stop Condition Flag
+ 'USISR_USIDC': '$10', # Data Output Collision
+ 'USISR_USICNT': '$f', # USI Counter Value Bits
+ 'USICR' : '$b8', # USI Control Register
+ 'USICR_USISIE': '$80', # Start Condition Interrupt Enab
+ 'USICR_USIOIE': '$40', # Counter Overflow Interrupt Ena
+ 'USICR_USIWM': '$30', # USI Wire Mode Bits
+ 'USICR_USICS': '$c', # USI Clock Source Select Bits
+ 'USICR_USICLK': '$2', # Clock Strobe
+ 'USICR_USITC': '$1', # Toggle Clock Port Pin
+
+# Module AD_CONVERTER
+ 'ADMUX' : '$7c', # The ADC multiplexer Selection
+ 'ADMUX_REFS': '$c0', # Reference Selection Bits
+ 'ADMUX_ADLAR': '$20', # Left Adjust Result
+ 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
+ 'ADCSRA' : '$7a', # The ADC Control and Status reg
+ 'ADCSRA_ADEN': '$80', # ADC Enable
+ 'ADCSRA_ADSC': '$40', # ADC Start Conversion
+ 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
+ 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
+ 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
+ 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
+ 'ADC' : '$78', # ADC Data Register Bytes
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Sources
+ 'DIDR0' : '$7e', # Digital Input Disable Register
+ 'DIDR0_ADC7D': '$80', # ADC7 Digital input Disable
+ 'DIDR0_ADC6D': '$40', # ADC6 Digital input Disable
+ 'DIDR0_ADC5D': '$20', # ADC5 Digital input Disable
+ 'DIDR0_ADC4D': '$10', # ADC4 Digital input Disable
+ 'DIDR0_ADC3D': '$8', # ADC3 Digital input Disable
+ 'DIDR0_ADC2D': '$4', # ADC2 Digital input Disable
+ 'DIDR0_ADC1D': '$2', # ADC1 Digital input Disable
+ 'DIDR0_ADC0D': '$1', # ADC0 Digital input Disable
+
+# Module BOOT_LOAD
+ 'SPMCSR' : '$57', # Store Program Memory Control R
+ 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
+ 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
+ 'SPMCSR_RWWSRE': '$10', # Read While Write section read
+ 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
+ 'SPMCSR_PGWRT': '$4', # Page Write
+ 'SPMCSR_PGERS': '$2', # Page Erase
+ 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
+
+# Module USART0
+ 'UDR0' : '$c6', # USART I/O Data Register
+ 'UCSR0A' : '$c0', # USART Control and Status Regis
+ 'UCSR0A_RXC0': '$80', # USART Receive Complete
+ 'UCSR0A_TXC0': '$40', # USART Transmit Complete
+ 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
+ 'UCSR0A_FE0': '$10', # Framing Error
+ 'UCSR0A_DOR0': '$8', # Data OverRun
+ 'UCSR0A_UPE0': '$4', # USART Parity Error
+ 'UCSR0A_U2X0': '$2', # Double the USART Transmission
+ 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
+ 'UCSR0B' : '$c1', # USART Control and Status Regis
+ 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
+ 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
+ 'UCSR0B_UDRIE0': '$20', # USART Data Register Empty Inte
+ 'UCSR0B_RXEN0': '$10', # Receiver Enable
+ 'UCSR0B_TXEN0': '$8', # Transmitter Enable
+ 'UCSR0B_UCSZ02': '$4', # Character Size
+ 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
+ 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
+ 'UCSR0C' : '$c2', # USART Control and Status Regis
+ 'UCSR0C_UMSEL0': '$40', # USART Mode Select
+ 'UCSR0C_UPM0': '$30', # Parity Mode Bits
+ 'UCSR0C_USBS0': '$8', # Stop Bit Select
+ 'UCSR0C_UCSZ0': '$6', # Character Size
+ 'UCSR0C_UCPOL0': '$1', # Clock Polarity
+ 'UBRR0' : '$c4', # USART Baud Rate Register Byte
+
+# Module EXTERNAL_INTERRUPT
+ 'EICRA' : '$69', # External Interrupt Control Reg
+ 'EICRA_ISC01': '$2', # External Interrupt Sense Contr
+ 'EICRA_ISC00': '$1', # External Interrupt Sense Contr
+ 'EIMSK' : '$3d', # External Interrupt Mask Regist
+ 'EIMSK_PCIE': '$30', # Pin Change Interrupt Enables
+ 'EIMSK_INT0': '$1', # External Interrupt Request 0 E
+ 'EIFR' : '$3c', # External Interrupt Flag Regist
+ 'EIFR_PCIF': '$30', # Pin Change Interrupt Flags
+ 'EIFR_INTF0': '$1', # External Interrupt Flag 0
+ 'PCMSK1' : '$6c', # Pin Change Mask Register 1
+ 'PCMSK1_PCINT': '$ff', # Pin Change Enable Masks
+ 'PCMSK0' : '$6b', # Pin Change Mask Register 0
+ 'PCMSK0_PCINT': '$ff', # Pin Change Enable Masks
+
+# Module CPU
+ 'SREG' : '$5f', # Status Register
+ 'SREG_I': '$80', # Global Interrupt Enable
+ 'SREG_T': '$40', # Bit Copy Storage
+ 'SREG_H': '$20', # Half Carry Flag
+ 'SREG_S': '$10', # Sign Bit
+ 'SREG_V': '$8', # Two's Complement Overflow Flag
+ 'SREG_N': '$4', # Negative Flag
+ 'SREG_Z': '$2', # Zero Flag
+ 'SREG_C': '$1', # Carry Flag
+ 'SP' : '$5d', # Stack Pointer
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_BODS': '$40', # BOD Sleep
+ 'MCUCR_BODSE': '$20', # BOD Sleep Enable
+ 'MCUCR_PUD': '$10', # Pull-up disable
+ 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
+ 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+ 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
+ 'MCUSR_BORF': '$4', # Brown-out Reset Flag
+ 'MCUSR_EXTRF': '$2', # External Reset Flag
+ 'MCUSR_PORF': '$1', # Power-on reset flag
+ 'OSCCAL' : '$66', # Oscillator Calibration Value
+ 'CLKPR' : '$61', # Clock Prescale Register
+ 'CLKPR_CLKPCE': '$80', # Clock Prescaler Change Enable
+ 'CLKPR_CLKPS': '$f', # Clock Prescaler Select Bits
+ 'PRR' : '$64', # Power Reduction Register
+ 'PRR_PRTIM1': '$8', # Power Reduction Timer/Counter1
+ 'PRR_PRSPI': '$4', # Power Reduction Serial Periphe
+ 'PRR_PRUSART0': '$2', # Power Reduction USART
+ 'PRR_PRADC': '$1', # Power Reduction ADC
+ 'SMCR' : '$53', # Sleep Mode Control Register
+ 'SMCR_SM': '$e', # Sleep Mode Select bits
+ 'SMCR_SE': '$1', # Sleep Enable
+ 'GPIOR2' : '$4b', # General Purpose IO Register 2
+ 'GPIOR1' : '$4a', # General Purpose IO Register 1
+ 'GPIOR0' : '$3e', # General Purpose IO Register 0
+
+ '__amforth_dummy':'0'
+}
diff --git a/amforth-6.5/avr8/devices/atmega165pa/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega165pa/words/no-jtag.asm
new file mode 100644
index 0000000..352a4bb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega165pa/words/no-jtag.asm
@@ -0,0 +1,14 @@
+; ( -- )
+; ( -- )
+; MCU
+; disable jtag at runtime
+VE_NOJTAG:
+ .dw $FF05
+ .db "-jtag",0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOJTAG
+XT_NOJTAG:
+ .dw PFA_NOJTAG
+PFA_NOJTAG:
+
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega165pa/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega165pa/words/no-wdt.asm
new file mode 100644
index 0000000..4a12261
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega165pa/words/no-wdt.asm
@@ -0,0 +1,22 @@
+; ( -- )
+; MCU
+; disable watch dog timer at runtime
+VE_NOWDT:
+ .dw $ff04
+ .db "-wdt"
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOWDT
+XT_NOWDT:
+ .dw PFA_NOWDT
+PFA_NOWDT:
+
+; Reset WDT
+ wdr
+; Write logical one to WDTOE and WDE
+ in_ temp1, WDTCR
+ ori temp1, (1<<WDTOE)|(1<<WDE)
+ out WDTCR, temp1
+; Turn off WDT
+ ldi temp1, (0<<WDE)
+ out_ WDTCR, temp1
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega165pa/words/sleep.asm b/amforth-6.5/avr8/devices/atmega165pa/words/sleep.asm
new file mode 100644
index 0000000..256249c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega165pa/words/sleep.asm
@@ -0,0 +1,19 @@
+; ( mode -- )
+; MCU
+; put the controller into the specified sleep mode
+VE_SLEEP:
+ .dw $ff05
+ .db "sleep", 0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_SLEEP
+XT_SLEEP:
+ .dw PFA_SLEEP
+PFA_SLEEP:
+ andi tosl, 7 ; leave only legal mode bits
+ lsl tosl ; move to correct location (bits 3-1)
+ ori tosl, 1 ; set the SE bit
+ out_ SMCR, tosl ; set the sleep config
+ sleep ; nighty-night
+ out_ SMCR, zerol ; 0 protects against accidental sleeps
+ loadtos ; pop argument from stack
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega168/atmega168.frt b/amforth-6.5/avr8/devices/atmega168/atmega168.frt
new file mode 100644
index 0000000..df0b666
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega168/atmega168.frt
@@ -0,0 +1,297 @@
+\ Partname: ATmega168
+\ generated automatically
+
+\ USART0
+&198 constant UDR0 \ USART I/O Data Register
+&192 constant UCSR0A \ USART Control and Status Register A
+ $80 constant UCSR0A_RXC0 \ USART Receive Complete
+ $40 constant UCSR0A_TXC0 \ USART Transmitt Complete
+ $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
+ $10 constant UCSR0A_FE0 \ Framing Error
+ $08 constant UCSR0A_DOR0 \ Data overRun
+ $04 constant UCSR0A_UPE0 \ Parity Error
+ $02 constant UCSR0A_U2X0 \ Double the USART transmission speed
+ $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
+&193 constant UCSR0B \ USART Control and Status Register B
+ $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
+ $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
+ $20 constant UCSR0B_UDRIE0 \ USART Data register Empty Interrupt Enable
+ $10 constant UCSR0B_RXEN0 \ Receiver Enable
+ $08 constant UCSR0B_TXEN0 \ Transmitter Enable
+ $04 constant UCSR0B_UCSZ02 \ Character Size
+ $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
+ $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
+&194 constant UCSR0C \ USART Control and Status Register C
+ $C0 constant UCSR0C_UMSEL0 \ USART Mode Select
+ $30 constant UCSR0C_UPM0 \ Parity Mode Bits
+ $08 constant UCSR0C_USBS0 \ Stop Bit Select
+ $06 constant UCSR0C_UCSZ0 \ Character Size
+ $01 constant UCSR0C_UCPOL0 \ Clock Polarity
+&196 constant UBRR0 \ USART Baud Rate Register Bytes
+\ TWI
+&189 constant TWAMR \ TWI (Slave) Address Mask Register
+ $FE constant TWAMR_TWAM \
+&184 constant TWBR \ TWI Bit Rate register
+&188 constant TWCR \ TWI Control Register
+ $80 constant TWCR_TWINT \ TWI Interrupt Flag
+ $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
+ $20 constant TWCR_TWSTA \ TWI Start Condition Bit
+ $10 constant TWCR_TWSTO \ TWI Stop Condition Bit
+ $08 constant TWCR_TWWC \ TWI Write Collition Flag
+ $04 constant TWCR_TWEN \ TWI Enable Bit
+ $01 constant TWCR_TWIE \ TWI Interrupt Enable
+&185 constant TWSR \ TWI Status Register
+ $F8 constant TWSR_TWS \ TWI Status
+ $03 constant TWSR_TWPS \ TWI Prescaler
+&187 constant TWDR \ TWI Data register
+&186 constant TWAR \ TWI (Slave) Address register
+ $FE constant TWAR_TWA \ TWI (Slave) Address register Bits
+ $01 constant TWAR_TWGCE \ TWI General Call Recognition Enable Bit
+\ TIMER_COUNTER_1
+&111 constant TIMSK1 \ Timer/Counter Interrupt Mask Register
+ $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
+ $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output CompareB Match Interrupt Enable
+ $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output CompareA Match Interrupt Enable
+ $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
+&54 constant TIFR1 \ Timer/Counter Interrupt Flag register
+ $20 constant TIFR1_ICF1 \ Input Capture Flag 1
+ $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
+ $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
+ $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
+&128 constant TCCR1A \ Timer/Counter1 Control Register A
+ $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
+ $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
+ $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
+&129 constant TCCR1B \ Timer/Counter1 Control Register B
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
+ $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
+&130 constant TCCR1C \ Timer/Counter1 Control Register C
+ $80 constant TCCR1C_FOC1A \
+ $40 constant TCCR1C_FOC1B \
+&132 constant TCNT1 \ Timer/Counter1 Bytes
+&136 constant OCR1A \ Timer/Counter1 Output Compare Register Bytes
+&138 constant OCR1B \ Timer/Counter1 Output Compare Register Bytes
+&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
+&67 constant GTCCR \ General Timer/Counter Control Register
+ $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
+ $01 constant GTCCR_PSRSYNC \ Prescaler Reset Timer/Counter1 and Timer/Counter0
+\ TIMER_COUNTER_2
+&112 constant TIMSK2 \ Timer/Counter Interrupt Mask register
+ $04 constant TIMSK2_OCIE2B \ Timer/Counter2 Output Compare Match B Interrupt Enable
+ $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match A Interrupt Enable
+ $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
+&55 constant TIFR2 \ Timer/Counter Interrupt Flag Register
+ $04 constant TIFR2_OCF2B \ Output Compare Flag 2B
+ $02 constant TIFR2_OCF2A \ Output Compare Flag 2A
+ $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
+&176 constant TCCR2A \ Timer/Counter2 Control Register A
+ $C0 constant TCCR2A_COM2A \ Compare Output Mode bits
+ $30 constant TCCR2A_COM2B \ Compare Output Mode bits
+ $03 constant TCCR2A_WGM2 \ Waveform Genration Mode
+&177 constant TCCR2B \ Timer/Counter2 Control Register B
+ $80 constant TCCR2B_FOC2A \ Force Output Compare A
+ $40 constant TCCR2B_FOC2B \ Force Output Compare B
+ $08 constant TCCR2B_WGM22 \ Waveform Generation Mode
+ $07 constant TCCR2B_CS2 \ Clock Select bits
+&178 constant TCNT2 \ Timer/Counter2
+&180 constant OCR2B \ Timer/Counter2 Output Compare Register B
+&179 constant OCR2A \ Timer/Counter2 Output Compare Register A
+&182 constant ASSR \ Asynchronous Status Register
+ $40 constant ASSR_EXCLK \ Enable External Clock Input
+ $20 constant ASSR_AS2 \ Asynchronous Timer/Counter2
+ $10 constant ASSR_TCN2UB \ Timer/Counter2 Update Busy
+ $08 constant ASSR_OCR2AUB \ Output Compare Register2 Update Busy
+ $04 constant ASSR_OCR2BUB \ Output Compare Register 2 Update Busy
+ $02 constant ASSR_TCR2AUB \ Timer/Counter Control Register2 Update Busy
+ $01 constant ASSR_TCR2BUB \ Timer/Counter Control Register2 Update Busy
+\ AD_CONVERTER
+&124 constant ADMUX \ The ADC multiplexer Selection Register
+ $C0 constant ADMUX_REFS \ Reference Selection Bits
+ $20 constant ADMUX_ADLAR \ Left Adjust Result
+ $0F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
+&120 constant ADC \ ADC Data Register Bytes
+&122 constant ADCSRA \ The ADC Control and Status register A
+ $80 constant ADCSRA_ADEN \ ADC Enable
+ $40 constant ADCSRA_ADSC \ ADC Start Conversion
+ $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
+ $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
+ $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
+ $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
+&123 constant ADCSRB \ The ADC Control and Status register B
+ $40 constant ADCSRB_ACME \
+ $07 constant ADCSRB_ADTS \ ADC Auto Trigger Source bits
+&126 constant DIDR0 \ Digital Input Disable Register
+ $20 constant DIDR0_ADC5D \
+ $10 constant DIDR0_ADC4D \
+ $08 constant DIDR0_ADC3D \
+ $04 constant DIDR0_ADC2D \
+ $02 constant DIDR0_ADC1D \
+ $01 constant DIDR0_ADC0D \
+\ ANALOG_COMPARATOR
+&80 constant ACSR \ Analog Comparator Control And Status Register
+ $80 constant ACSR_ACD \ Analog Comparator Disable
+ $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
+ $20 constant ACSR_ACO \ Analog Compare Output
+ $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
+ $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
+ $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
+ $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
+&127 constant DIDR1 \ Digital Input Disable Register 1
+ $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
+ $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
+\ PORTB
+&37 constant PORTB \ Port B Data Register
+&36 constant DDRB \ Port B Data Direction Register
+&35 constant PINB \ Port B Input Pins
+\ PORTC
+&40 constant PORTC \ Port C Data Register
+&39 constant DDRC \ Port C Data Direction Register
+&38 constant PINC \ Port C Input Pins
+\ PORTD
+&43 constant PORTD \ Port D Data Register
+&42 constant DDRD \ Port D Data Direction Register
+&41 constant PIND \ Port D Input Pins
+\ TIMER_COUNTER_0
+&72 constant OCR0B \ Timer/Counter0 Output Compare Register
+&71 constant OCR0A \ Timer/Counter0 Output Compare Register
+&70 constant TCNT0 \ Timer/Counter0
+&69 constant TCCR0B \ Timer/Counter Control Register B
+ $80 constant TCCR0B_FOC0A \ Force Output Compare A
+ $40 constant TCCR0B_FOC0B \ Force Output Compare B
+ $08 constant TCCR0B_WGM02 \
+ $07 constant TCCR0B_CS0 \ Clock Select
+&68 constant TCCR0A \ Timer/Counter Control Register A
+ $C0 constant TCCR0A_COM0A \ Compare Output Mode, Phase Correct PWM Mode
+ $30 constant TCCR0A_COM0B \ Compare Output Mode, Fast PWm
+ $03 constant TCCR0A_WGM0 \ Waveform Generation Mode
+&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
+ $04 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare Match B Interrupt Enable
+ $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match A Interrupt Enable
+ $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
+&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
+ $04 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare Flag 0B
+ $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0A
+ $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
+\ EXTERNAL_INTERRUPT
+&105 constant EICRA \ External Interrupt Control Register
+ $0C constant EICRA_ISC1 \ External Interrupt Sense Control 1 Bits
+ $03 constant EICRA_ISC0 \ External Interrupt Sense Control 0 Bits
+&61 constant EIMSK \ External Interrupt Mask Register
+ $03 constant EIMSK_INT \ External Interrupt Request 1 Enable
+&60 constant EIFR \ External Interrupt Flag Register
+ $03 constant EIFR_INTF \ External Interrupt Flags
+&104 constant PCICR \ Pin Change Interrupt Control Register
+ $07 constant PCICR_PCIE \ Pin Change Interrupt Enables
+&109 constant PCMSK2 \ Pin Change Mask Register 2
+ $FF constant PCMSK2_PCINT \ Pin Change Enable Masks
+&108 constant PCMSK1 \ Pin Change Mask Register 1
+ $7F constant PCMSK1_PCINT \ Pin Change Enable Masks
+&107 constant PCMSK0 \ Pin Change Mask Register 0
+ $FF constant PCMSK0_PCINT \ Pin Change Enable Masks
+&59 constant PCIFR \ Pin Change Interrupt Flag Register
+ $07 constant PCIFR_PCIF \ Pin Change Interrupt Flags
+\ SPI
+&78 constant SPDR \ SPI Data Register
+&77 constant SPSR \ SPI Status Register
+ $80 constant SPSR_SPIF \ SPI Interrupt Flag
+ $40 constant SPSR_WCOL \ Write Collision Flag
+ $01 constant SPSR_SPI2X \ Double SPI Speed Bit
+&76 constant SPCR \ SPI Control Register
+ $80 constant SPCR_SPIE \ SPI Interrupt Enable
+ $40 constant SPCR_SPE \ SPI Enable
+ $20 constant SPCR_DORD \ Data Order
+ $10 constant SPCR_MSTR \ Master/Slave Select
+ $08 constant SPCR_CPOL \ Clock polarity
+ $04 constant SPCR_CPHA \ Clock Phase
+ $03 constant SPCR_SPR \ SPI Clock Rate Selects
+\ CPU
+&100 constant PRR \ Power Reduction Register
+ $80 constant PRR_PRTWI \ Power Reduction TWI
+ $40 constant PRR_PRTIM2 \ Power Reduction Timer/Counter2
+ $20 constant PRR_PRTIM0 \ Power Reduction Timer/Counter0
+ $08 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
+ $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
+ $02 constant PRR_PRUSART0 \ Power Reduction USART
+ $01 constant PRR_PRADC \ Power Reduction ADC
+&102 constant OSCCAL \ Oscillator Calibration Value
+&97 constant CLKPR \ Clock Prescale Register
+ $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable
+ $0F constant CLKPR_CLKPS \ Clock Prescaler Select Bits
+&95 constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ $08 constant SREG_V \ Two's Complement Overflow Flag
+ $04 constant SREG_N \ Negative Flag
+ $02 constant SREG_Z \ Zero Flag
+ $01 constant SREG_C \ Carry Flag
+&93 constant SP \ Stack Pointer
+&87 constant SPMCSR \ Store Program Memory Control and Status Register
+ $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCSR_RWWSB \ Read-While-Write Section Busy
+ $10 constant SPMCSR_RWWSRE \ Read-While-Write section read enable
+ $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
+ $04 constant SPMCSR_PGWRT \ Page Write
+ $02 constant SPMCSR_PGERS \ Page Erase
+ $01 constant SPMCSR_SELFPRGEN \ Self Programming Enable
+&85 constant MCUCR \ MCU Control Register
+ $10 constant MCUCR_PUD \
+ $02 constant MCUCR_IVSEL \
+ $01 constant MCUCR_IVCE \
+&84 constant MCUSR \ MCU Status Register
+ $08 constant MCUSR_WDRF \ Watchdog Reset Flag
+ $04 constant MCUSR_BORF \ Brown-out Reset Flag
+ $02 constant MCUSR_EXTRF \ External Reset Flag
+ $01 constant MCUSR_PORF \ Power-on reset flag
+&83 constant SMCR \
+ $0E constant SMCR_SM \
+ $01 constant SMCR_SE \
+&75 constant GPIOR2 \ General Purpose I/O Register 2
+&74 constant GPIOR1 \ General Purpose I/O Register 1
+&62 constant GPIOR0 \ General Purpose I/O Register 0
+\ WATCHDOG
+&96 constant WDTCSR \ Watchdog Timer Control Register
+ $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Flag
+ $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Enable
+ $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
+ $10 constant WDTCSR_WDCE \ Watchdog Change Enable
+ $08 constant WDTCSR_WDE \ Watch Dog Enable
+\ EEPROM
+&65 constant EEAR \ EEPROM Address Register Bytes
+&64 constant EEDR \ EEPROM Data Register
+&63 constant EECR \ EEPROM Control Register
+ $30 constant EECR_EEPM \ EEPROM Programming Mode Bits
+ $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
+ $04 constant EECR_EEMPE \ EEPROM Master Write Enable
+ $02 constant EECR_EEPE \ EEPROM Write Enable
+ $01 constant EECR_EERE \ EEPROM Read Enable
+
+\ Interrupts
+&2 constant INT0Addr \ External Interrupt Request 0
+&4 constant INT1Addr \ External Interrupt Request 1
+&6 constant PCINT0Addr \ Pin Change Interrupt Request 0
+&8 constant PCINT1Addr \ Pin Change Interrupt Request 0
+&10 constant PCINT2Addr \ Pin Change Interrupt Request 1
+&12 constant WDTAddr \ Watchdog Time-out Interrupt
+&14 constant TIMER2_COMPAAddr \ Timer/Counter2 Compare Match A
+&16 constant TIMER2_COMPBAddr \ Timer/Counter2 Compare Match A
+&18 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
+&20 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+&22 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
+&24 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
+&26 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+&28 constant TIMER0_COMPAAddr \ TimerCounter0 Compare Match A
+&30 constant TIMER0_COMPBAddr \ TimerCounter0 Compare Match B
+&32 constant TIMER0_OVFAddr \ Timer/Couner0 Overflow
+&34 constant SPI__STCAddr \ SPI Serial Transfer Complete
+&36 constant USART__RXAddr \ USART Rx Complete
+&38 constant USART__UDREAddr \ USART, Data Register Empty
+&40 constant USART__TXAddr \ USART Tx Complete
+&42 constant ADCAddr \ ADC Conversion Complete
+&44 constant EE_READYAddr \ EEPROM Ready
+&46 constant ANALOG_COMPAddr \ Analog Comparator
+&48 constant TWIAddr \ Two-wire Serial Interface
+&50 constant SPM_ReadyAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/atmega168/device.asm b/amforth-6.5/avr8/devices/atmega168/device.asm
new file mode 100644
index 0000000..74bda58
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega168/device.asm
@@ -0,0 +1,107 @@
+; Partname: ATmega168
+; generated automatically, do not edit
+
+.nolist
+ .include "m168def.inc"
+.list
+
+.equ ramstart = 256
+.equ CELLSIZE = 2
+.macro readflashcell
+ lsl zl
+ rol zh
+ lpm @0, Z+
+ lpm @1, Z+
+.endmacro
+.macro writeflashcell
+ lsl zl
+ rol zh
+.endmacro
+.set WANT_USART0 = 0
+.set WANT_TWI = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_TIMER_COUNTER_2 = 0
+.set WANT_AD_CONVERTER = 0
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_PORTB = 0
+.set WANT_PORTC = 0
+.set WANT_PORTD = 0
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_SPI = 0
+.set WANT_CPU = 0
+.set WANT_WATCHDOG = 0
+.set WANT_EEPROM = 0
+.equ intvecsize = 2 ; please verify; flash size: 16384 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.org 2
+ rcall isr ; External Interrupt Request 0
+.org 4
+ rcall isr ; External Interrupt Request 1
+.org 6
+ rcall isr ; Pin Change Interrupt Request 0
+.org 8
+ rcall isr ; Pin Change Interrupt Request 0
+.org 10
+ rcall isr ; Pin Change Interrupt Request 1
+.org 12
+ rcall isr ; Watchdog Time-out Interrupt
+.org 14
+ rcall isr ; Timer/Counter2 Compare Match A
+.org 16
+ rcall isr ; Timer/Counter2 Compare Match A
+.org 18
+ rcall isr ; Timer/Counter2 Overflow
+.org 20
+ rcall isr ; Timer/Counter1 Capture Event
+.org 22
+ rcall isr ; Timer/Counter1 Compare Match A
+.org 24
+ rcall isr ; Timer/Counter1 Compare Match B
+.org 26
+ rcall isr ; Timer/Counter1 Overflow
+.org 28
+ rcall isr ; TimerCounter0 Compare Match A
+.org 30
+ rcall isr ; TimerCounter0 Compare Match B
+.org 32
+ rcall isr ; Timer/Couner0 Overflow
+.org 34
+ rcall isr ; SPI Serial Transfer Complete
+.org 36
+ rcall isr ; USART Rx Complete
+.org 38
+ rcall isr ; USART, Data Register Empty
+.org 40
+ rcall isr ; USART Tx Complete
+.org 42
+ rcall isr ; ADC Conversion Complete
+.org 44
+ rcall isr ; EEPROM Ready
+.org 46
+ rcall isr ; Analog Comparator
+.org 48
+ rcall isr ; Two-wire Serial Interface
+.org 50
+ rcall isr ; Store Program Memory Read
+.equ INTVECTORS = 26
+.nooverlap
+
+; compatability layer (maybe empty)
+.equ SPMEN = SELFPRGEN
+
+; controller data area, environment query mcu-info
+mcu_info:
+mcu_ramsize:
+ .dw 1024
+mcu_eepromsize:
+ .dw 512
+mcu_maxdp:
+ .dw 14336
+mcu_numints:
+ .dw 26
+mcu_name:
+ .dw 9
+ .db "ATmega168",0
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega168/device.inc b/amforth-6.5/avr8/devices/atmega168/device.inc
new file mode 100644
index 0000000..47d5dcd
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega168/device.inc
@@ -0,0 +1,996 @@
+; Partname: ATmega168
+; generated automatically, no not edit
+
+.if WANT_USART0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR0:
+ .dw $ff04
+ .db "UDR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR0
+XT_UDR0:
+ .dw PFA_DOVARIABLE
+PFA_UDR0:
+ .dw 198
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR0A:
+ .dw $ff06
+ .db "UCSR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0A
+XT_UCSR0A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0A:
+ .dw 192
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR0B:
+ .dw $ff06
+ .db "UCSR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0B
+XT_UCSR0B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0B:
+ .dw 193
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR0C:
+ .dw $ff06
+ .db "UCSR0C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0C
+XT_UCSR0C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0C:
+ .dw 194
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Bytes
+VE_UBRR0:
+ .dw $ff05
+ .db "UBRR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR0
+XT_UBRR0:
+ .dw PFA_DOVARIABLE
+PFA_UBRR0:
+ .dw 196
+
+.endif
+.if WANT_TWI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; TWI (Slave) Address Mask Register
+VE_TWAMR:
+ .dw $ff05
+ .db "TWAMR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWAMR
+XT_TWAMR:
+ .dw PFA_DOVARIABLE
+PFA_TWAMR:
+ .dw 189
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Bit Rate register
+VE_TWBR:
+ .dw $ff04
+ .db "TWBR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWBR
+XT_TWBR:
+ .dw PFA_DOVARIABLE
+PFA_TWBR:
+ .dw 184
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Control Register
+VE_TWCR:
+ .dw $ff04
+ .db "TWCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWCR
+XT_TWCR:
+ .dw PFA_DOVARIABLE
+PFA_TWCR:
+ .dw 188
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Status Register
+VE_TWSR:
+ .dw $ff04
+ .db "TWSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWSR
+XT_TWSR:
+ .dw PFA_DOVARIABLE
+PFA_TWSR:
+ .dw 185
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Data register
+VE_TWDR:
+ .dw $ff04
+ .db "TWDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWDR
+XT_TWDR:
+ .dw PFA_DOVARIABLE
+PFA_TWDR:
+ .dw 187
+; ( -- addr ) System Constant
+; R( -- )
+; TWI (Slave) Address register
+VE_TWAR:
+ .dw $ff04
+ .db "TWAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWAR
+XT_TWAR:
+ .dw PFA_DOVARIABLE
+PFA_TWAR:
+ .dw 186
+
+.endif
+.if WANT_TIMER_COUNTER_1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Mask Register
+VE_TIMSK1:
+ .dw $ff06
+ .db "TIMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK1
+XT_TIMSK1:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK1:
+ .dw 111
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Flag register
+VE_TIFR1:
+ .dw $ff05
+ .db "TIFR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR1
+XT_TIFR1:
+ .dw PFA_DOVARIABLE
+PFA_TIFR1:
+ .dw 54
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw 128
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw 129
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register C
+VE_TCCR1C:
+ .dw $ff06
+ .db "TCCR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1C
+XT_TCCR1C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1C:
+ .dw 130
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Bytes
+VE_TCNT1:
+ .dw $ff05
+ .db "TCNT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1
+XT_TCNT1:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1:
+ .dw 132
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register Bytes
+VE_OCR1A:
+ .dw $ff05
+ .db "OCR1A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1A
+XT_OCR1A:
+ .dw PFA_DOVARIABLE
+PFA_OCR1A:
+ .dw 136
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register Bytes
+VE_OCR1B:
+ .dw $ff05
+ .db "OCR1B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1B
+XT_OCR1B:
+ .dw PFA_DOVARIABLE
+PFA_OCR1B:
+ .dw 138
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Bytes
+VE_ICR1:
+ .dw $ff04
+ .db "ICR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1
+XT_ICR1:
+ .dw PFA_DOVARIABLE
+PFA_ICR1:
+ .dw 134
+; ( -- addr ) System Constant
+; R( -- )
+; General Timer/Counter Control Register
+VE_GTCCR:
+ .dw $ff05
+ .db "GTCCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GTCCR
+XT_GTCCR:
+ .dw PFA_DOVARIABLE
+PFA_GTCCR:
+ .dw 67
+
+.endif
+.if WANT_TIMER_COUNTER_2 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Mask register
+VE_TIMSK2:
+ .dw $ff06
+ .db "TIMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK2
+XT_TIMSK2:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK2:
+ .dw 112
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Flag Register
+VE_TIFR2:
+ .dw $ff05
+ .db "TIFR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR2
+XT_TIFR2:
+ .dw PFA_DOVARIABLE
+PFA_TIFR2:
+ .dw 55
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register A
+VE_TCCR2A:
+ .dw $ff06
+ .db "TCCR2A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2A
+XT_TCCR2A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2A:
+ .dw 176
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register B
+VE_TCCR2B:
+ .dw $ff06
+ .db "TCCR2B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2B
+XT_TCCR2B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2B:
+ .dw 177
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2
+VE_TCNT2:
+ .dw $ff05
+ .db "TCNT2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT2
+XT_TCNT2:
+ .dw PFA_DOVARIABLE
+PFA_TCNT2:
+ .dw 178
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register B
+VE_OCR2B:
+ .dw $ff05
+ .db "OCR2B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2B
+XT_OCR2B:
+ .dw PFA_DOVARIABLE
+PFA_OCR2B:
+ .dw 180
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register A
+VE_OCR2A:
+ .dw $ff05
+ .db "OCR2A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2A
+XT_OCR2A:
+ .dw PFA_DOVARIABLE
+PFA_OCR2A:
+ .dw 179
+; ( -- addr ) System Constant
+; R( -- )
+; Asynchronous Status Register
+VE_ASSR:
+ .dw $ff04
+ .db "ASSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ASSR
+XT_ASSR:
+ .dw PFA_DOVARIABLE
+PFA_ASSR:
+ .dw 182
+
+.endif
+.if WANT_AD_CONVERTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC multiplexer Selection Register
+VE_ADMUX:
+ .dw $ff05
+ .db "ADMUX",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADMUX
+XT_ADMUX:
+ .dw PFA_DOVARIABLE
+PFA_ADMUX:
+ .dw 124
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register Bytes
+VE_ADC:
+ .dw $ff03
+ .db "ADC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADC
+XT_ADC:
+ .dw PFA_DOVARIABLE
+PFA_ADC:
+ .dw 120
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register A
+VE_ADCSRA:
+ .dw $ff06
+ .db "ADCSRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRA
+XT_ADCSRA:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRA:
+ .dw 122
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register B
+VE_ADCSRB:
+ .dw $ff06
+ .db "ADCSRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRB
+XT_ADCSRB:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRB:
+ .dw 123
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register
+VE_DIDR0:
+ .dw $ff05
+ .db "DIDR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR0
+XT_DIDR0:
+ .dw PFA_DOVARIABLE
+PFA_DIDR0:
+ .dw 126
+
+.endif
+.if WANT_ANALOG_COMPARATOR == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Control And Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw 80
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 1
+VE_DIDR1:
+ .dw $ff05
+ .db "DIDR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR1
+XT_DIDR1:
+ .dw PFA_DOVARIABLE
+PFA_DIDR1:
+ .dw 127
+
+.endif
+.if WANT_PORTB == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw 37
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw 36
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw 35
+
+.endif
+.if WANT_PORTC == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Register
+VE_PORTC:
+ .dw $ff05
+ .db "PORTC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTC
+XT_PORTC:
+ .dw PFA_DOVARIABLE
+PFA_PORTC:
+ .dw 40
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Direction Register
+VE_DDRC:
+ .dw $ff04
+ .db "DDRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRC
+XT_DDRC:
+ .dw PFA_DOVARIABLE
+PFA_DDRC:
+ .dw 39
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Input Pins
+VE_PINC:
+ .dw $ff04
+ .db "PINC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINC
+XT_PINC:
+ .dw PFA_DOVARIABLE
+PFA_PINC:
+ .dw 38
+
+.endif
+.if WANT_PORTD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw 43
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw 42
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw 41
+
+.endif
+.if WANT_TIMER_COUNTER_0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0B:
+ .dw $ff05
+ .db "OCR0B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0B
+XT_OCR0B:
+ .dw PFA_DOVARIABLE
+PFA_OCR0B:
+ .dw 72
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0A:
+ .dw $ff05
+ .db "OCR0A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0A
+XT_OCR0A:
+ .dw PFA_DOVARIABLE
+PFA_OCR0A:
+ .dw 71
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw 70
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register B
+VE_TCCR0B:
+ .dw $ff06
+ .db "TCCR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0B
+XT_TCCR0B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0B:
+ .dw 69
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register A
+VE_TCCR0A:
+ .dw $ff06
+ .db "TCCR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0A
+XT_TCCR0A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0A:
+ .dw 68
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Mask Register
+VE_TIMSK0:
+ .dw $ff06
+ .db "TIMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK0
+XT_TIMSK0:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK0:
+ .dw 110
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Flag register
+VE_TIFR0:
+ .dw $ff05
+ .db "TIFR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR0
+XT_TIFR0:
+ .dw PFA_DOVARIABLE
+PFA_TIFR0:
+ .dw 53
+
+.endif
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register
+VE_EICRA:
+ .dw $ff05
+ .db "EICRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRA
+XT_EICRA:
+ .dw PFA_DOVARIABLE
+PFA_EICRA:
+ .dw 105
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Mask Register
+VE_EIMSK:
+ .dw $ff05
+ .db "EIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIMSK
+XT_EIMSK:
+ .dw PFA_DOVARIABLE
+PFA_EIMSK:
+ .dw 61
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Flag Register
+VE_EIFR:
+ .dw $ff04
+ .db "EIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIFR
+XT_EIFR:
+ .dw PFA_DOVARIABLE
+PFA_EIFR:
+ .dw 60
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Interrupt Control Register
+VE_PCICR:
+ .dw $ff05
+ .db "PCICR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCICR
+XT_PCICR:
+ .dw PFA_DOVARIABLE
+PFA_PCICR:
+ .dw 104
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 2
+VE_PCMSK2:
+ .dw $ff06
+ .db "PCMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK2
+XT_PCMSK2:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK2:
+ .dw 109
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 1
+VE_PCMSK1:
+ .dw $ff06
+ .db "PCMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK1
+XT_PCMSK1:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK1:
+ .dw 108
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 0
+VE_PCMSK0:
+ .dw $ff06
+ .db "PCMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK0
+XT_PCMSK0:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK0:
+ .dw 107
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Interrupt Flag Register
+VE_PCIFR:
+ .dw $ff05
+ .db "PCIFR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCIFR
+XT_PCIFR:
+ .dw PFA_DOVARIABLE
+PFA_PCIFR:
+ .dw 59
+
+.endif
+.if WANT_SPI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR:
+ .dw $ff04
+ .db "SPDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR
+XT_SPDR:
+ .dw PFA_DOVARIABLE
+PFA_SPDR:
+ .dw 78
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR:
+ .dw $ff04
+ .db "SPSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR
+XT_SPSR:
+ .dw PFA_DOVARIABLE
+PFA_SPSR:
+ .dw 77
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR:
+ .dw $ff04
+ .db "SPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR
+XT_SPCR:
+ .dw PFA_DOVARIABLE
+PFA_SPCR:
+ .dw 76
+
+.endif
+.if WANT_CPU == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register
+VE_PRR:
+ .dw $ff03
+ .db "PRR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR
+XT_PRR:
+ .dw PFA_DOVARIABLE
+PFA_PRR:
+ .dw 100
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Calibration Value
+VE_OSCCAL:
+ .dw $ff06
+ .db "OSCCAL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSCCAL
+XT_OSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_OSCCAL:
+ .dw 102
+; ( -- addr ) System Constant
+; R( -- )
+; Clock Prescale Register
+VE_CLKPR:
+ .dw $ff05
+ .db "CLKPR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKPR
+XT_CLKPR:
+ .dw PFA_DOVARIABLE
+PFA_CLKPR:
+ .dw 97
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw 95
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer
+VE_SP:
+ .dw $ff02
+ .db "SP"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SP
+XT_SP:
+ .dw PFA_DOVARIABLE
+PFA_SP:
+ .dw 93
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control and Status Register
+VE_SPMCSR:
+ .dw $ff06
+ .db "SPMCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCSR
+XT_SPMCSR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCSR:
+ .dw 87
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw 85
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Status Register
+VE_MCUSR:
+ .dw $ff05
+ .db "MCUSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUSR
+XT_MCUSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUSR:
+ .dw 84
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_SMCR:
+ .dw $ff04
+ .db "SMCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SMCR
+XT_SMCR:
+ .dw PFA_DOVARIABLE
+PFA_SMCR:
+ .dw 83
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose I/O Register 2
+VE_GPIOR2:
+ .dw $ff06
+ .db "GPIOR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR2
+XT_GPIOR2:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR2:
+ .dw 75
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose I/O Register 1
+VE_GPIOR1:
+ .dw $ff06
+ .db "GPIOR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR1
+XT_GPIOR1:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR1:
+ .dw 74
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose I/O Register 0
+VE_GPIOR0:
+ .dw $ff06
+ .db "GPIOR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR0
+XT_GPIOR0:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR0:
+ .dw 62
+
+.endif
+.if WANT_WATCHDOG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCSR:
+ .dw $ff06
+ .db "WDTCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCSR
+XT_WDTCSR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCSR:
+ .dw 96
+
+.endif
+.if WANT_EEPROM == 1
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Address Register Bytes
+VE_EEAR:
+ .dw $ff04
+ .db "EEAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEAR
+XT_EEAR:
+ .dw PFA_DOVARIABLE
+PFA_EEAR:
+ .dw 65
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw 64
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw 63
+
+.endif
diff --git a/amforth-6.5/avr8/devices/atmega168/device.py b/amforth-6.5/avr8/devices/atmega168/device.py
new file mode 100644
index 0000000..f2179e8
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega168/device.py
@@ -0,0 +1,322 @@
+# Generated Automatically
+
+# Partname ATmega168
+
+MCUREGS = {
+# Interrupt Vectors
+ 'INT0Addr' : '#2', # External Interrupt Request 0
+ 'INT1Addr' : '#4', # External Interrupt Request 1
+ 'PCINT0Addr' : '#6', # Pin Change Interrupt Request 0
+ 'PCINT1Addr' : '#8', # Pin Change Interrupt Request 0
+ 'PCINT2Addr' : '#10', # Pin Change Interrupt Request 1
+ 'WDTAddr' : '#12', # Watchdog Time-out Interrupt
+ 'TIMER2_COMPAAddr' : '#14', # Timer/Counter2 Compare Match A
+ 'TIMER2_COMPBAddr' : '#16', # Timer/Counter2 Compare Match A
+ 'TIMER2_OVFAddr' : '#18', # Timer/Counter2 Overflow
+ 'TIMER1_CAPTAddr' : '#20', # Timer/Counter1 Capture Event
+ 'TIMER1_COMPAAddr' : '#22', # Timer/Counter1 Compare Match A
+ 'TIMER1_COMPBAddr' : '#24', # Timer/Counter1 Compare Match B
+ 'TIMER1_OVFAddr' : '#26', # Timer/Counter1 Overflow
+ 'TIMER0_COMPAAddr' : '#28', # TimerCounter0 Compare Match A
+ 'TIMER0_COMPBAddr' : '#30', # TimerCounter0 Compare Match B
+ 'TIMER0_OVFAddr' : '#32', # Timer/Couner0 Overflow
+ 'SPI_STCAddr' : '#34', # SPI Serial Transfer Complete
+ 'USART_RXAddr' : '#36', # USART Rx Complete
+ 'USART_UDREAddr' : '#38', # USART, Data Register Empty
+ 'USART_TXAddr' : '#40', # USART Tx Complete
+ 'ADCAddr' : '#42', # ADC Conversion Complete
+ 'EE_READYAddr' : '#44', # EEPROM Ready
+ 'ANALOG_COMPAddr' : '#46', # Analog Comparator
+ 'TWIAddr' : '#48', # Two-wire Serial Interface
+ 'SPM_ReadyAddr' : '#50', # Store Program Memory Read
+
+# Module USART0
+ 'UDR0' : '$c6', # USART I/O Data Register
+ 'UCSR0A' : '$c0', # USART Control and Status Regis
+ 'UCSR0A_RXC0': '$80', # USART Receive Complete
+ 'UCSR0A_TXC0': '$40', # USART Transmitt Complete
+ 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
+ 'UCSR0A_FE0': '$10', # Framing Error
+ 'UCSR0A_DOR0': '$8', # Data overRun
+ 'UCSR0A_UPE0': '$4', # Parity Error
+ 'UCSR0A_U2X0': '$2', # Double the USART transmission
+ 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
+ 'UCSR0B' : '$c1', # USART Control and Status Regis
+ 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
+ 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
+ 'UCSR0B_UDRIE0': '$20', # USART Data register Empty Inte
+ 'UCSR0B_RXEN0': '$10', # Receiver Enable
+ 'UCSR0B_TXEN0': '$8', # Transmitter Enable
+ 'UCSR0B_UCSZ02': '$4', # Character Size
+ 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
+ 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
+ 'UCSR0C' : '$c2', # USART Control and Status Regis
+ 'UCSR0C_UMSEL0': '$c0', # USART Mode Select
+ 'UCSR0C_UPM0': '$30', # Parity Mode Bits
+ 'UCSR0C_USBS0': '$8', # Stop Bit Select
+ 'UCSR0C_UCSZ0': '$6', # Character Size
+ 'UCSR0C_UCPOL0': '$1', # Clock Polarity
+ 'UBRR0' : '$c4', # USART Baud Rate Register Byte
+
+# Module TWI
+ 'TWAMR' : '$bd', # TWI (Slave) Address Mask Regis
+ 'TWAMR_TWAM': '$fe', #
+ 'TWBR' : '$b8', # TWI Bit Rate register
+ 'TWCR' : '$bc', # TWI Control Register
+ 'TWCR_TWINT': '$80', # TWI Interrupt Flag
+ 'TWCR_TWEA': '$40', # TWI Enable Acknowledge Bit
+ 'TWCR_TWSTA': '$20', # TWI Start Condition Bit
+ 'TWCR_TWSTO': '$10', # TWI Stop Condition Bit
+ 'TWCR_TWWC': '$8', # TWI Write Collition Flag
+ 'TWCR_TWEN': '$4', # TWI Enable Bit
+ 'TWCR_TWIE': '$1', # TWI Interrupt Enable
+ 'TWSR' : '$b9', # TWI Status Register
+ 'TWSR_TWS': '$f8', # TWI Status
+ 'TWSR_TWPS': '$3', # TWI Prescaler
+ 'TWDR' : '$bb', # TWI Data register
+ 'TWAR' : '$ba', # TWI (Slave) Address register
+ 'TWAR_TWA': '$fe', # TWI (Slave) Address register B
+ 'TWAR_TWGCE': '$1', # TWI General Call Recognition E
+
+# Module TIMER_COUNTER_1
+ 'TIMSK1' : '$6f', # Timer/Counter Interrupt Mask R
+ 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
+ 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output CompareB
+ 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output CompareA
+ 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
+ 'TIFR1' : '$36', # Timer/Counter Interrupt Flag r
+ 'TIFR1_ICF1': '$20', # Input Capture Flag 1
+ 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
+ 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
+ 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
+ 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
+ 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
+ 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
+ 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
+ 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
+ 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
+ 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
+ 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
+ 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
+ 'TCCR1C' : '$82', # Timer/Counter1 Control Registe
+ 'TCCR1C_FOC1A': '$80', #
+ 'TCCR1C_FOC1B': '$40', #
+ 'TCNT1' : '$84', # Timer/Counter1 Bytes
+ 'OCR1A' : '$88', # Timer/Counter1 Output Compare
+ 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
+ 'ICR1' : '$86', # Timer/Counter1 Input Capture R
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSRSYNC': '$1', # Prescaler Reset Timer/Counter1
+
+# Module TIMER_COUNTER_2
+ 'TIMSK2' : '$70', # Timer/Counter Interrupt Mask r
+ 'TIMSK2_OCIE2B': '$4', # Timer/Counter2 Output Compare
+ 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
+ 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
+ 'TIFR2' : '$37', # Timer/Counter Interrupt Flag R
+ 'TIFR2_OCF2B': '$4', # Output Compare Flag 2B
+ 'TIFR2_OCF2A': '$2', # Output Compare Flag 2A
+ 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
+ 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
+ 'TCCR2A_COM2A': '$c0', # Compare Output Mode bits
+ 'TCCR2A_COM2B': '$30', # Compare Output Mode bits
+ 'TCCR2A_WGM2': '$3', # Waveform Genration Mode
+ 'TCCR2B' : '$b1', # Timer/Counter2 Control Registe
+ 'TCCR2B_FOC2A': '$80', # Force Output Compare A
+ 'TCCR2B_FOC2B': '$40', # Force Output Compare B
+ 'TCCR2B_WGM22': '$8', # Waveform Generation Mode
+ 'TCCR2B_CS2': '$7', # Clock Select bits
+ 'TCNT2' : '$b2', # Timer/Counter2
+ 'OCR2B' : '$b4', # Timer/Counter2 Output Compare
+ 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
+ 'ASSR' : '$b6', # Asynchronous Status Register
+ 'ASSR_EXCLK': '$40', # Enable External Clock Input
+ 'ASSR_AS2': '$20', # Asynchronous Timer/Counter2
+ 'ASSR_TCN2UB': '$10', # Timer/Counter2 Update Busy
+ 'ASSR_OCR2AUB': '$8', # Output Compare Register2 Updat
+ 'ASSR_OCR2BUB': '$4', # Output Compare Register 2 Upda
+ 'ASSR_TCR2AUB': '$2', # Timer/Counter Control Register
+ 'ASSR_TCR2BUB': '$1', # Timer/Counter Control Register
+ 'GTCCR' : '$43', # General Timer Counter Control
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSRASY': '$2', # Prescaler Reset Timer/Counter2
+
+# Module AD_CONVERTER
+ 'ADMUX' : '$7c', # The ADC multiplexer Selection
+ 'ADMUX_REFS': '$c0', # Reference Selection Bits
+ 'ADMUX_ADLAR': '$20', # Left Adjust Result
+ 'ADMUX_MUX': '$f', # Analog Channel and Gain Select
+ 'ADC' : '$78', # ADC Data Register Bytes
+ 'ADCSRA' : '$7a', # The ADC Control and Status reg
+ 'ADCSRA_ADEN': '$80', # ADC Enable
+ 'ADCSRA_ADSC': '$40', # ADC Start Conversion
+ 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
+ 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
+ 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
+ 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
+ 'ADCSRB' : '$7b', # The ADC Control and Status reg
+ 'ADCSRB_ACME': '$40', #
+ 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Source bits
+ 'DIDR0' : '$7e', # Digital Input Disable Register
+ 'DIDR0_ADC5D': '$20', #
+ 'DIDR0_ADC4D': '$10', #
+ 'DIDR0_ADC3D': '$8', #
+ 'DIDR0_ADC2D': '$4', #
+ 'DIDR0_ADC1D': '$2', #
+ 'DIDR0_ADC0D': '$1', #
+
+# Module ANALOG_COMPARATOR
+ 'ACSR' : '$50', # Analog Comparator Control And
+ 'ACSR_ACD': '$80', # Analog Comparator Disable
+ 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
+ 'ACSR_ACO': '$20', # Analog Compare Output
+ 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
+ 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
+ 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
+ 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
+ 'DIDR1' : '$7f', # Digital Input Disable Register
+ 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
+ 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
+
+# Module PORTB
+ 'PORTB' : '$25', # Port B Data Register
+ 'DDRB' : '$24', # Port B Data Direction Register
+ 'PINB' : '$23', # Port B Input Pins
+
+# Module PORTC
+ 'PORTC' : '$28', # Port C Data Register
+ 'DDRC' : '$27', # Port C Data Direction Register
+ 'PINC' : '$26', # Port C Input Pins
+
+# Module PORTD
+ 'PORTD' : '$2b', # Port D Data Register
+ 'DDRD' : '$2a', # Port D Data Direction Register
+ 'PIND' : '$29', # Port D Input Pins
+
+# Module TIMER_COUNTER_0
+ 'OCR0B' : '$48', # Timer/Counter0 Output Compare
+ 'OCR0A' : '$47', # Timer/Counter0 Output Compare
+ 'TCNT0' : '$46', # Timer/Counter0
+ 'TCCR0B' : '$45', # Timer/Counter Control Register
+ 'TCCR0B_FOC0A': '$80', # Force Output Compare A
+ 'TCCR0B_FOC0B': '$40', # Force Output Compare B
+ 'TCCR0B_WGM02': '$8', #
+ 'TCCR0B_CS0': '$7', # Clock Select
+ 'TCCR0A' : '$44', # Timer/Counter Control Registe
+ 'TCCR0A_COM0A': '$c0', # Compare Output Mode, Phase Cor
+ 'TCCR0A_COM0B': '$30', # Compare Output Mode, Fast PWm
+ 'TCCR0A_WGM0': '$3', # Waveform Generation Mode
+ 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
+ 'TIMSK0_OCIE0B': '$4', # Timer/Counter0 Output Compare
+ 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
+ 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
+ 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
+ 'TIFR0_OCF0B': '$4', # Timer/Counter0 Output Compare
+ 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
+ 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSRSYNC': '$1', # Prescaler Reset Timer/Counter1
+
+# Module EXTERNAL_INTERRUPT
+ 'EICRA' : '$69', # External Interrupt Control Reg
+ 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
+ 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
+ 'EIMSK' : '$3d', # External Interrupt Mask Regist
+ 'EIMSK_INT': '$3', # External Interrupt Request 1 E
+ 'EIFR' : '$3c', # External Interrupt Flag Regist
+ 'EIFR_INTF': '$3', # External Interrupt Flags
+ 'PCICR' : '$68', # Pin Change Interrupt Control R
+ 'PCICR_PCIE': '$7', # Pin Change Interrupt Enables
+ 'PCMSK2' : '$6d', # Pin Change Mask Register 2
+ 'PCMSK2_PCINT': '$ff', # Pin Change Enable Masks
+ 'PCMSK1' : '$6c', # Pin Change Mask Register 1
+ 'PCMSK1_PCINT': '$7f', # Pin Change Enable Masks
+ 'PCMSK0' : '$6b', # Pin Change Mask Register 0
+ 'PCMSK0_PCINT': '$ff', # Pin Change Enable Masks
+ 'PCIFR' : '$3b', # Pin Change Interrupt Flag Regi
+ 'PCIFR_PCIF': '$7', # Pin Change Interrupt Flags
+
+# Module SPI
+ 'SPDR' : '$4e', # SPI Data Register
+ 'SPSR' : '$4d', # SPI Status Register
+ 'SPSR_SPIF': '$80', # SPI Interrupt Flag
+ 'SPSR_WCOL': '$40', # Write Collision Flag
+ 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
+ 'SPCR' : '$4c', # SPI Control Register
+ 'SPCR_SPIE': '$80', # SPI Interrupt Enable
+ 'SPCR_SPE': '$40', # SPI Enable
+ 'SPCR_DORD': '$20', # Data Order
+ 'SPCR_MSTR': '$10', # Master/Slave Select
+ 'SPCR_CPOL': '$8', # Clock polarity
+ 'SPCR_CPHA': '$4', # Clock Phase
+ 'SPCR_SPR': '$3', # SPI Clock Rate Selects
+
+# Module CPU
+ 'PRR' : '$64', # Power Reduction Register
+ 'PRR_PRTWI': '$80', # Power Reduction TWI
+ 'PRR_PRTIM2': '$40', # Power Reduction Timer/Counter2
+ 'PRR_PRTIM0': '$20', # Power Reduction Timer/Counter0
+ 'PRR_PRTIM1': '$8', # Power Reduction Timer/Counter1
+ 'PRR_PRSPI': '$4', # Power Reduction Serial Periphe
+ 'PRR_PRUSART0': '$2', # Power Reduction USART
+ 'PRR_PRADC': '$1', # Power Reduction ADC
+ 'OSCCAL' : '$66', # Oscillator Calibration Value
+ 'CLKPR' : '$61', # Clock Prescale Register
+ 'CLKPR_CLKPCE': '$80', # Clock Prescaler Change Enable
+ 'CLKPR_CLKPS': '$f', # Clock Prescaler Select Bits
+ 'SREG' : '$5f', # Status Register
+ 'SREG_I': '$80', # Global Interrupt Enable
+ 'SREG_T': '$40', # Bit Copy Storage
+ 'SREG_H': '$20', # Half Carry Flag
+ 'SREG_S': '$10', # Sign Bit
+ 'SREG_V': '$8', # Two's Complement Overflow Flag
+ 'SREG_N': '$4', # Negative Flag
+ 'SREG_Z': '$2', # Zero Flag
+ 'SREG_C': '$1', # Carry Flag
+ 'SP' : '$5d', # Stack Pointer
+ 'SPMCSR' : '$57', # Store Program Memory Control a
+ 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
+ 'SPMCSR_RWWSB': '$40', # Read-While-Write Section Busy
+ 'SPMCSR_RWWSRE': '$10', # Read-While-Write section read
+ 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
+ 'SPMCSR_PGWRT': '$4', # Page Write
+ 'SPMCSR_PGERS': '$2', # Page Erase
+ 'SPMCSR_SELFPRGEN': '$1', # Self Programming Enable
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_PUD': '$10', #
+ 'MCUCR_IVSEL': '$2', #
+ 'MCUCR_IVCE': '$1', #
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
+ 'MCUSR_BORF': '$4', # Brown-out Reset Flag
+ 'MCUSR_EXTRF': '$2', # External Reset Flag
+ 'MCUSR_PORF': '$1', # Power-on reset flag
+ 'SMCR' : '$53', #
+ 'SMCR_SM': '$e', #
+ 'SMCR_SE': '$1', #
+ 'GPIOR2' : '$4b', # General Purpose I/O Register 2
+ 'GPIOR1' : '$4a', # General Purpose I/O Register 1
+ 'GPIOR0' : '$3e', # General Purpose I/O Register 0
+
+# Module WATCHDOG
+ 'WDTCSR' : '$60', # Watchdog Timer Control Registe
+ 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
+ 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
+ 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
+ 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
+ 'WDTCSR_WDE': '$8', # Watch Dog Enable
+
+# Module EEPROM
+ 'EEAR' : '$41', # EEPROM Address Register Bytes
+ 'EEDR' : '$40', # EEPROM Data Register
+ 'EECR' : '$3f', # EEPROM Control Register
+ 'EECR_EEPM': '$30', # EEPROM Programming Mode Bits
+ 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
+ 'EECR_EEMPE': '$4', # EEPROM Master Write Enable
+ 'EECR_EEPE': '$2', # EEPROM Write Enable
+ 'EECR_EERE': '$1', # EEPROM Read Enable
+
+ '__amforth_dummy':'0'
+}
diff --git a/amforth-6.5/avr8/devices/atmega168/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega168/words/no-jtag.asm
new file mode 100644
index 0000000..352a4bb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega168/words/no-jtag.asm
@@ -0,0 +1,14 @@
+; ( -- )
+; ( -- )
+; MCU
+; disable jtag at runtime
+VE_NOJTAG:
+ .dw $FF05
+ .db "-jtag",0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOJTAG
+XT_NOJTAG:
+ .dw PFA_NOJTAG
+PFA_NOJTAG:
+
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega168/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega168/words/no-wdt.asm
new file mode 100644
index 0000000..ff6ddd1
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega168/words/no-wdt.asm
@@ -0,0 +1,34 @@
+; ( -- )
+; MCU
+; disable watch dog timer at runtime
+VE_NOWDT:
+ .dw $ff04
+ .db "-wdt"
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOWDT
+XT_NOWDT:
+ .dw PFA_NOWDT
+PFA_NOWDT:
+
+ in temp1,SREG
+ push temp1
+ ; Turn always off global interrupt.
+ cli
+ ; Reset Watchdog Timer
+ wdr
+ ; Clear WDRF in MCUSR
+ in temp1, MCUSR
+ andi temp1, (0xff & (0<<WDRF))
+ out MCUSR, temp1
+ ; Write logical one to WDCE and WDE
+ ; Keep old prescaler setting to prevent unintentional time-out
+ in_ temp1, WDTCSR
+ ori temp1, (1<<WDCE) | (1<<WDE)
+ out_ WDTCSR, temp1
+ ; Turn off WDT
+ ldi temp1, (0<<WDE)
+ out_ WDTCSR, temp1
+ ; restore status register
+ pop temp1
+ out SREG,temp1
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega168/words/sleep.asm b/amforth-6.5/avr8/devices/atmega168/words/sleep.asm
new file mode 100644
index 0000000..256249c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega168/words/sleep.asm
@@ -0,0 +1,19 @@
+; ( mode -- )
+; MCU
+; put the controller into the specified sleep mode
+VE_SLEEP:
+ .dw $ff05
+ .db "sleep", 0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_SLEEP
+XT_SLEEP:
+ .dw PFA_SLEEP
+PFA_SLEEP:
+ andi tosl, 7 ; leave only legal mode bits
+ lsl tosl ; move to correct location (bits 3-1)
+ ori tosl, 1 ; set the SE bit
+ out_ SMCR, tosl ; set the sleep config
+ sleep ; nighty-night
+ out_ SMCR, zerol ; 0 protects against accidental sleeps
+ loadtos ; pop argument from stack
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega168a/atmega168a.frt b/amforth-6.5/avr8/devices/atmega168a/atmega168a.frt
new file mode 100644
index 0000000..6ec7083
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega168a/atmega168a.frt
@@ -0,0 +1,297 @@
+\ Partname: ATmega168A
+\ generated automatically
+
+\ USART0
+&198 constant UDR0 \ USART I/O Data Register
+&192 constant UCSR0A \ USART Control and Status Register A
+ $80 constant UCSR0A_RXC0 \ USART Receive Complete
+ $40 constant UCSR0A_TXC0 \ USART Transmitt Complete
+ $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
+ $10 constant UCSR0A_FE0 \ Framing Error
+ $08 constant UCSR0A_DOR0 \ Data overRun
+ $04 constant UCSR0A_UPE0 \ Parity Error
+ $02 constant UCSR0A_U2X0 \ Double the USART transmission speed
+ $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
+&193 constant UCSR0B \ USART Control and Status Register B
+ $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
+ $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
+ $20 constant UCSR0B_UDRIE0 \ USART Data register Empty Interrupt Enable
+ $10 constant UCSR0B_RXEN0 \ Receiver Enable
+ $08 constant UCSR0B_TXEN0 \ Transmitter Enable
+ $04 constant UCSR0B_UCSZ02 \ Character Size
+ $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
+ $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
+&194 constant UCSR0C \ USART Control and Status Register C
+ $C0 constant UCSR0C_UMSEL0 \ USART Mode Select
+ $30 constant UCSR0C_UPM0 \ Parity Mode Bits
+ $08 constant UCSR0C_USBS0 \ Stop Bit Select
+ $06 constant UCSR0C_UCSZ0 \ Character Size
+ $01 constant UCSR0C_UCPOL0 \ Clock Polarity
+&196 constant UBRR0 \ USART Baud Rate Register Bytes
+\ TWI
+&189 constant TWAMR \ TWI (Slave) Address Mask Register
+ $FE constant TWAMR_TWAM \
+&184 constant TWBR \ TWI Bit Rate register
+&188 constant TWCR \ TWI Control Register
+ $80 constant TWCR_TWINT \ TWI Interrupt Flag
+ $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
+ $20 constant TWCR_TWSTA \ TWI Start Condition Bit
+ $10 constant TWCR_TWSTO \ TWI Stop Condition Bit
+ $08 constant TWCR_TWWC \ TWI Write Collition Flag
+ $04 constant TWCR_TWEN \ TWI Enable Bit
+ $01 constant TWCR_TWIE \ TWI Interrupt Enable
+&185 constant TWSR \ TWI Status Register
+ $F8 constant TWSR_TWS \ TWI Status
+ $03 constant TWSR_TWPS \ TWI Prescaler
+&187 constant TWDR \ TWI Data register
+&186 constant TWAR \ TWI (Slave) Address register
+ $FE constant TWAR_TWA \ TWI (Slave) Address register Bits
+ $01 constant TWAR_TWGCE \ TWI General Call Recognition Enable Bit
+\ TIMER_COUNTER_1
+&111 constant TIMSK1 \ Timer/Counter Interrupt Mask Register
+ $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
+ $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output CompareB Match Interrupt Enable
+ $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output CompareA Match Interrupt Enable
+ $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
+&54 constant TIFR1 \ Timer/Counter Interrupt Flag register
+ $20 constant TIFR1_ICF1 \ Input Capture Flag 1
+ $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
+ $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
+ $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
+&128 constant TCCR1A \ Timer/Counter1 Control Register A
+ $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
+ $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
+ $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
+&129 constant TCCR1B \ Timer/Counter1 Control Register B
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
+ $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
+&130 constant TCCR1C \ Timer/Counter1 Control Register C
+ $80 constant TCCR1C_FOC1A \
+ $40 constant TCCR1C_FOC1B \
+&132 constant TCNT1 \ Timer/Counter1 Bytes
+&136 constant OCR1A \ Timer/Counter1 Output Compare Register Bytes
+&138 constant OCR1B \ Timer/Counter1 Output Compare Register Bytes
+&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
+&67 constant GTCCR \ General Timer/Counter Control Register
+ $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
+ $01 constant GTCCR_PSRSYNC \ Prescaler Reset Timer/Counter1 and Timer/Counter0
+\ TIMER_COUNTER_2
+&112 constant TIMSK2 \ Timer/Counter Interrupt Mask register
+ $04 constant TIMSK2_OCIE2B \ Timer/Counter2 Output Compare Match B Interrupt Enable
+ $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match A Interrupt Enable
+ $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
+&55 constant TIFR2 \ Timer/Counter Interrupt Flag Register
+ $04 constant TIFR2_OCF2B \ Output Compare Flag 2B
+ $02 constant TIFR2_OCF2A \ Output Compare Flag 2A
+ $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
+&176 constant TCCR2A \ Timer/Counter2 Control Register A
+ $C0 constant TCCR2A_COM2A \ Compare Output Mode bits
+ $30 constant TCCR2A_COM2B \ Compare Output Mode bits
+ $03 constant TCCR2A_WGM2 \ Waveform Genration Mode
+&177 constant TCCR2B \ Timer/Counter2 Control Register B
+ $80 constant TCCR2B_FOC2A \ Force Output Compare A
+ $40 constant TCCR2B_FOC2B \ Force Output Compare B
+ $08 constant TCCR2B_WGM22 \ Waveform Generation Mode
+ $07 constant TCCR2B_CS2 \ Clock Select bits
+&178 constant TCNT2 \ Timer/Counter2
+&180 constant OCR2B \ Timer/Counter2 Output Compare Register B
+&179 constant OCR2A \ Timer/Counter2 Output Compare Register A
+&182 constant ASSR \ Asynchronous Status Register
+ $40 constant ASSR_EXCLK \ Enable External Clock Input
+ $20 constant ASSR_AS2 \ Asynchronous Timer/Counter2
+ $10 constant ASSR_TCN2UB \ Timer/Counter2 Update Busy
+ $08 constant ASSR_OCR2AUB \ Output Compare Register2 Update Busy
+ $04 constant ASSR_OCR2BUB \ Output Compare Register 2 Update Busy
+ $02 constant ASSR_TCR2AUB \ Timer/Counter Control Register2 Update Busy
+ $01 constant ASSR_TCR2BUB \ Timer/Counter Control Register2 Update Busy
+\ AD_CONVERTER
+&124 constant ADMUX \ The ADC multiplexer Selection Register
+ $C0 constant ADMUX_REFS \ Reference Selection Bits
+ $20 constant ADMUX_ADLAR \ Left Adjust Result
+ $0F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
+&120 constant ADC \ ADC Data Register Bytes
+&122 constant ADCSRA \ The ADC Control and Status register A
+ $80 constant ADCSRA_ADEN \ ADC Enable
+ $40 constant ADCSRA_ADSC \ ADC Start Conversion
+ $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
+ $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
+ $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
+ $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
+&123 constant ADCSRB \ The ADC Control and Status register B
+ $40 constant ADCSRB_ACME \
+ $07 constant ADCSRB_ADTS \ ADC Auto Trigger Source bits
+&126 constant DIDR0 \ Digital Input Disable Register
+ $20 constant DIDR0_ADC5D \
+ $10 constant DIDR0_ADC4D \
+ $08 constant DIDR0_ADC3D \
+ $04 constant DIDR0_ADC2D \
+ $02 constant DIDR0_ADC1D \
+ $01 constant DIDR0_ADC0D \
+\ ANALOG_COMPARATOR
+&80 constant ACSR \ Analog Comparator Control And Status Register
+ $80 constant ACSR_ACD \ Analog Comparator Disable
+ $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
+ $20 constant ACSR_ACO \ Analog Compare Output
+ $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
+ $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
+ $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
+ $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
+&127 constant DIDR1 \ Digital Input Disable Register 1
+ $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
+ $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
+\ PORTB
+&37 constant PORTB \ Port B Data Register
+&36 constant DDRB \ Port B Data Direction Register
+&35 constant PINB \ Port B Input Pins
+\ PORTC
+&40 constant PORTC \ Port C Data Register
+&39 constant DDRC \ Port C Data Direction Register
+&38 constant PINC \ Port C Input Pins
+\ PORTD
+&43 constant PORTD \ Port D Data Register
+&42 constant DDRD \ Port D Data Direction Register
+&41 constant PIND \ Port D Input Pins
+\ TIMER_COUNTER_0
+&72 constant OCR0B \ Timer/Counter0 Output Compare Register
+&71 constant OCR0A \ Timer/Counter0 Output Compare Register
+&70 constant TCNT0 \ Timer/Counter0
+&69 constant TCCR0B \ Timer/Counter Control Register B
+ $80 constant TCCR0B_FOC0A \ Force Output Compare A
+ $40 constant TCCR0B_FOC0B \ Force Output Compare B
+ $08 constant TCCR0B_WGM02 \
+ $07 constant TCCR0B_CS0 \ Clock Select
+&68 constant TCCR0A \ Timer/Counter Control Register A
+ $C0 constant TCCR0A_COM0A \ Compare Output Mode, Phase Correct PWM Mode
+ $30 constant TCCR0A_COM0B \ Compare Output Mode, Fast PWm
+ $03 constant TCCR0A_WGM0 \ Waveform Generation Mode
+&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
+ $04 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare Match B Interrupt Enable
+ $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match A Interrupt Enable
+ $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
+&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
+ $04 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare Flag 0B
+ $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0A
+ $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
+\ EXTERNAL_INTERRUPT
+&105 constant EICRA \ External Interrupt Control Register
+ $0C constant EICRA_ISC1 \ External Interrupt Sense Control 1 Bits
+ $03 constant EICRA_ISC0 \ External Interrupt Sense Control 0 Bits
+&61 constant EIMSK \ External Interrupt Mask Register
+ $03 constant EIMSK_INT \ External Interrupt Request 1 Enable
+&60 constant EIFR \ External Interrupt Flag Register
+ $03 constant EIFR_INTF \ External Interrupt Flags
+&104 constant PCICR \ Pin Change Interrupt Control Register
+ $07 constant PCICR_PCIE \ Pin Change Interrupt Enables
+&109 constant PCMSK2 \ Pin Change Mask Register 2
+ $FF constant PCMSK2_PCINT \ Pin Change Enable Masks
+&108 constant PCMSK1 \ Pin Change Mask Register 1
+ $7F constant PCMSK1_PCINT \ Pin Change Enable Masks
+&107 constant PCMSK0 \ Pin Change Mask Register 0
+ $FF constant PCMSK0_PCINT \ Pin Change Enable Masks
+&59 constant PCIFR \ Pin Change Interrupt Flag Register
+ $07 constant PCIFR_PCIF \ Pin Change Interrupt Flags
+\ SPI
+&78 constant SPDR \ SPI Data Register
+&77 constant SPSR \ SPI Status Register
+ $80 constant SPSR_SPIF \ SPI Interrupt Flag
+ $40 constant SPSR_WCOL \ Write Collision Flag
+ $01 constant SPSR_SPI2X \ Double SPI Speed Bit
+&76 constant SPCR \ SPI Control Register
+ $80 constant SPCR_SPIE \ SPI Interrupt Enable
+ $40 constant SPCR_SPE \ SPI Enable
+ $20 constant SPCR_DORD \ Data Order
+ $10 constant SPCR_MSTR \ Master/Slave Select
+ $08 constant SPCR_CPOL \ Clock polarity
+ $04 constant SPCR_CPHA \ Clock Phase
+ $03 constant SPCR_SPR \ SPI Clock Rate Selects
+\ WATCHDOG
+&96 constant WDTCSR \ Watchdog Timer Control Register
+ $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Flag
+ $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Enable
+ $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
+ $10 constant WDTCSR_WDCE \ Watchdog Change Enable
+ $08 constant WDTCSR_WDE \ Watch Dog Enable
+\ EEPROM
+&65 constant EEAR \ EEPROM Address Register Bytes
+&64 constant EEDR \ EEPROM Data Register
+&63 constant EECR \ EEPROM Control Register
+ $30 constant EECR_EEPM \ EEPROM Programming Mode Bits
+ $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
+ $04 constant EECR_EEMPE \ EEPROM Master Write Enable
+ $02 constant EECR_EEPE \ EEPROM Write Enable
+ $01 constant EECR_EERE \ EEPROM Read Enable
+\ CPU
+&100 constant PRR \ Power Reduction Register
+ $80 constant PRR_PRTWI \ Power Reduction TWI
+ $40 constant PRR_PRTIM2 \ Power Reduction Timer/Counter2
+ $20 constant PRR_PRTIM0 \ Power Reduction Timer/Counter0
+ $08 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
+ $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
+ $02 constant PRR_PRUSART0 \ Power Reduction USART
+ $01 constant PRR_PRADC \ Power Reduction ADC
+&102 constant OSCCAL \ Oscillator Calibration Value
+&97 constant CLKPR \ Clock Prescale Register
+ $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable
+ $0F constant CLKPR_CLKPS \ Clock Prescaler Select Bits
+&95 constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ $08 constant SREG_V \ Two's Complement Overflow Flag
+ $04 constant SREG_N \ Negative Flag
+ $02 constant SREG_Z \ Zero Flag
+ $01 constant SREG_C \ Carry Flag
+&93 constant SP \ Stack Pointer
+&87 constant SPMCSR \ Store Program Memory Control and Status Register
+ $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCSR_RWWSB \ Read-While-Write Section Busy
+ $10 constant SPMCSR_RWWSRE \ Read-While-Write section read enable
+ $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
+ $04 constant SPMCSR_PGWRT \ Page Write
+ $02 constant SPMCSR_PGERS \ Page Erase
+ $01 constant SPMCSR_SELFPRGEN \ Self Programming Enable
+&85 constant MCUCR \ MCU Control Register
+ $10 constant MCUCR_PUD \
+ $02 constant MCUCR_IVSEL \
+ $01 constant MCUCR_IVCE \
+&84 constant MCUSR \ MCU Status Register
+ $08 constant MCUSR_WDRF \ Watchdog Reset Flag
+ $04 constant MCUSR_BORF \ Brown-out Reset Flag
+ $02 constant MCUSR_EXTRF \ External Reset Flag
+ $01 constant MCUSR_PORF \ Power-on reset flag
+&83 constant SMCR \ Sleep Mode Control Register
+ $0E constant SMCR_SM \ Sleep Mode Select Bits
+ $01 constant SMCR_SE \ Sleep Enable
+&75 constant GPIOR2 \ General Purpose I/O Register 2
+&74 constant GPIOR1 \ General Purpose I/O Register 1
+&62 constant GPIOR0 \ General Purpose I/O Register 0
+
+\ Interrupts
+&2 constant INT0Addr \ External Interrupt Request 0
+&4 constant INT1Addr \ External Interrupt Request 1
+&6 constant PCINT0Addr \ Pin Change Interrupt Request 0
+&8 constant PCINT1Addr \ Pin Change Interrupt Request 0
+&10 constant PCINT2Addr \ Pin Change Interrupt Request 1
+&12 constant WDTAddr \ Watchdog Time-out Interrupt
+&14 constant TIMER2_COMPAAddr \ Timer/Counter2 Compare Match A
+&16 constant TIMER2_COMPBAddr \ Timer/Counter2 Compare Match A
+&18 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
+&20 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+&22 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
+&24 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
+&26 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+&28 constant TIMER0_COMPAAddr \ TimerCounter0 Compare Match A
+&30 constant TIMER0_COMPBAddr \ TimerCounter0 Compare Match B
+&32 constant TIMER0_OVFAddr \ Timer/Couner0 Overflow
+&34 constant SPI__STCAddr \ SPI Serial Transfer Complete
+&36 constant USART__RXAddr \ USART Rx Complete
+&38 constant USART__UDREAddr \ USART, Data Register Empty
+&40 constant USART__TXAddr \ USART Tx Complete
+&42 constant ADCAddr \ ADC Conversion Complete
+&44 constant EE_READYAddr \ EEPROM Ready
+&46 constant ANALOG_COMPAddr \ Analog Comparator
+&48 constant TWIAddr \ Two-wire Serial Interface
+&50 constant SPM_ReadyAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/atmega168a/device.asm b/amforth-6.5/avr8/devices/atmega168a/device.asm
new file mode 100644
index 0000000..ffb34ff
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega168a/device.asm
@@ -0,0 +1,107 @@
+; Partname: ATmega168A
+; generated automatically, do not edit
+
+.nolist
+ .include "m168Adef.inc"
+.list
+
+.equ ramstart = 256
+.equ CELLSIZE = 2
+.macro readflashcell
+ lsl zl
+ rol zh
+ lpm @0, Z+
+ lpm @1, Z+
+.endmacro
+.macro writeflashcell
+ lsl zl
+ rol zh
+.endmacro
+.set WANT_USART0 = 0
+.set WANT_TWI = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_TIMER_COUNTER_2 = 0
+.set WANT_AD_CONVERTER = 0
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_PORTB = 0
+.set WANT_PORTC = 0
+.set WANT_PORTD = 0
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_SPI = 0
+.set WANT_WATCHDOG = 0
+.set WANT_EEPROM = 0
+.set WANT_CPU = 0
+.equ intvecsize = 2 ; please verify; flash size: 16384 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.org 2
+ rcall isr ; External Interrupt Request 0
+.org 4
+ rcall isr ; External Interrupt Request 1
+.org 6
+ rcall isr ; Pin Change Interrupt Request 0
+.org 8
+ rcall isr ; Pin Change Interrupt Request 0
+.org 10
+ rcall isr ; Pin Change Interrupt Request 1
+.org 12
+ rcall isr ; Watchdog Time-out Interrupt
+.org 14
+ rcall isr ; Timer/Counter2 Compare Match A
+.org 16
+ rcall isr ; Timer/Counter2 Compare Match A
+.org 18
+ rcall isr ; Timer/Counter2 Overflow
+.org 20
+ rcall isr ; Timer/Counter1 Capture Event
+.org 22
+ rcall isr ; Timer/Counter1 Compare Match A
+.org 24
+ rcall isr ; Timer/Counter1 Compare Match B
+.org 26
+ rcall isr ; Timer/Counter1 Overflow
+.org 28
+ rcall isr ; TimerCounter0 Compare Match A
+.org 30
+ rcall isr ; TimerCounter0 Compare Match B
+.org 32
+ rcall isr ; Timer/Couner0 Overflow
+.org 34
+ rcall isr ; SPI Serial Transfer Complete
+.org 36
+ rcall isr ; USART Rx Complete
+.org 38
+ rcall isr ; USART, Data Register Empty
+.org 40
+ rcall isr ; USART Tx Complete
+.org 42
+ rcall isr ; ADC Conversion Complete
+.org 44
+ rcall isr ; EEPROM Ready
+.org 46
+ rcall isr ; Analog Comparator
+.org 48
+ rcall isr ; Two-wire Serial Interface
+.org 50
+ rcall isr ; Store Program Memory Read
+.equ INTVECTORS = 26
+.nooverlap
+
+; compatability layer (maybe empty)
+.equ SPMEN = SELFPRGEN
+
+; controller data area, environment query mcu-info
+mcu_info:
+mcu_ramsize:
+ .dw 1024
+mcu_eepromsize:
+ .dw 512
+mcu_maxdp:
+ .dw 14336
+mcu_numints:
+ .dw 26
+mcu_name:
+ .dw 10
+ .db "ATmega168A"
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega168a/device.inc b/amforth-6.5/avr8/devices/atmega168a/device.inc
new file mode 100644
index 0000000..d497913
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega168a/device.inc
@@ -0,0 +1,996 @@
+; Partname: ATmega168A
+; generated automatically, no not edit
+
+.if WANT_USART0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR0:
+ .dw $ff04
+ .db "UDR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR0
+XT_UDR0:
+ .dw PFA_DOVARIABLE
+PFA_UDR0:
+ .dw 198
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR0A:
+ .dw $ff06
+ .db "UCSR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0A
+XT_UCSR0A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0A:
+ .dw 192
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR0B:
+ .dw $ff06
+ .db "UCSR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0B
+XT_UCSR0B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0B:
+ .dw 193
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR0C:
+ .dw $ff06
+ .db "UCSR0C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0C
+XT_UCSR0C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0C:
+ .dw 194
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Bytes
+VE_UBRR0:
+ .dw $ff05
+ .db "UBRR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR0
+XT_UBRR0:
+ .dw PFA_DOVARIABLE
+PFA_UBRR0:
+ .dw 196
+
+.endif
+.if WANT_TWI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; TWI (Slave) Address Mask Register
+VE_TWAMR:
+ .dw $ff05
+ .db "TWAMR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWAMR
+XT_TWAMR:
+ .dw PFA_DOVARIABLE
+PFA_TWAMR:
+ .dw 189
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Bit Rate register
+VE_TWBR:
+ .dw $ff04
+ .db "TWBR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWBR
+XT_TWBR:
+ .dw PFA_DOVARIABLE
+PFA_TWBR:
+ .dw 184
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Control Register
+VE_TWCR:
+ .dw $ff04
+ .db "TWCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWCR
+XT_TWCR:
+ .dw PFA_DOVARIABLE
+PFA_TWCR:
+ .dw 188
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Status Register
+VE_TWSR:
+ .dw $ff04
+ .db "TWSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWSR
+XT_TWSR:
+ .dw PFA_DOVARIABLE
+PFA_TWSR:
+ .dw 185
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Data register
+VE_TWDR:
+ .dw $ff04
+ .db "TWDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWDR
+XT_TWDR:
+ .dw PFA_DOVARIABLE
+PFA_TWDR:
+ .dw 187
+; ( -- addr ) System Constant
+; R( -- )
+; TWI (Slave) Address register
+VE_TWAR:
+ .dw $ff04
+ .db "TWAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWAR
+XT_TWAR:
+ .dw PFA_DOVARIABLE
+PFA_TWAR:
+ .dw 186
+
+.endif
+.if WANT_TIMER_COUNTER_1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Mask Register
+VE_TIMSK1:
+ .dw $ff06
+ .db "TIMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK1
+XT_TIMSK1:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK1:
+ .dw 111
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Flag register
+VE_TIFR1:
+ .dw $ff05
+ .db "TIFR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR1
+XT_TIFR1:
+ .dw PFA_DOVARIABLE
+PFA_TIFR1:
+ .dw 54
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw 128
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw 129
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register C
+VE_TCCR1C:
+ .dw $ff06
+ .db "TCCR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1C
+XT_TCCR1C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1C:
+ .dw 130
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Bytes
+VE_TCNT1:
+ .dw $ff05
+ .db "TCNT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1
+XT_TCNT1:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1:
+ .dw 132
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register Bytes
+VE_OCR1A:
+ .dw $ff05
+ .db "OCR1A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1A
+XT_OCR1A:
+ .dw PFA_DOVARIABLE
+PFA_OCR1A:
+ .dw 136
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register Bytes
+VE_OCR1B:
+ .dw $ff05
+ .db "OCR1B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1B
+XT_OCR1B:
+ .dw PFA_DOVARIABLE
+PFA_OCR1B:
+ .dw 138
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Bytes
+VE_ICR1:
+ .dw $ff04
+ .db "ICR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1
+XT_ICR1:
+ .dw PFA_DOVARIABLE
+PFA_ICR1:
+ .dw 134
+; ( -- addr ) System Constant
+; R( -- )
+; General Timer/Counter Control Register
+VE_GTCCR:
+ .dw $ff05
+ .db "GTCCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GTCCR
+XT_GTCCR:
+ .dw PFA_DOVARIABLE
+PFA_GTCCR:
+ .dw 67
+
+.endif
+.if WANT_TIMER_COUNTER_2 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Mask register
+VE_TIMSK2:
+ .dw $ff06
+ .db "TIMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK2
+XT_TIMSK2:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK2:
+ .dw 112
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Flag Register
+VE_TIFR2:
+ .dw $ff05
+ .db "TIFR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR2
+XT_TIFR2:
+ .dw PFA_DOVARIABLE
+PFA_TIFR2:
+ .dw 55
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register A
+VE_TCCR2A:
+ .dw $ff06
+ .db "TCCR2A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2A
+XT_TCCR2A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2A:
+ .dw 176
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register B
+VE_TCCR2B:
+ .dw $ff06
+ .db "TCCR2B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2B
+XT_TCCR2B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2B:
+ .dw 177
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2
+VE_TCNT2:
+ .dw $ff05
+ .db "TCNT2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT2
+XT_TCNT2:
+ .dw PFA_DOVARIABLE
+PFA_TCNT2:
+ .dw 178
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register B
+VE_OCR2B:
+ .dw $ff05
+ .db "OCR2B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2B
+XT_OCR2B:
+ .dw PFA_DOVARIABLE
+PFA_OCR2B:
+ .dw 180
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register A
+VE_OCR2A:
+ .dw $ff05
+ .db "OCR2A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2A
+XT_OCR2A:
+ .dw PFA_DOVARIABLE
+PFA_OCR2A:
+ .dw 179
+; ( -- addr ) System Constant
+; R( -- )
+; Asynchronous Status Register
+VE_ASSR:
+ .dw $ff04
+ .db "ASSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ASSR
+XT_ASSR:
+ .dw PFA_DOVARIABLE
+PFA_ASSR:
+ .dw 182
+
+.endif
+.if WANT_AD_CONVERTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC multiplexer Selection Register
+VE_ADMUX:
+ .dw $ff05
+ .db "ADMUX",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADMUX
+XT_ADMUX:
+ .dw PFA_DOVARIABLE
+PFA_ADMUX:
+ .dw 124
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register Bytes
+VE_ADC:
+ .dw $ff03
+ .db "ADC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADC
+XT_ADC:
+ .dw PFA_DOVARIABLE
+PFA_ADC:
+ .dw 120
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register A
+VE_ADCSRA:
+ .dw $ff06
+ .db "ADCSRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRA
+XT_ADCSRA:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRA:
+ .dw 122
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register B
+VE_ADCSRB:
+ .dw $ff06
+ .db "ADCSRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRB
+XT_ADCSRB:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRB:
+ .dw 123
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register
+VE_DIDR0:
+ .dw $ff05
+ .db "DIDR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR0
+XT_DIDR0:
+ .dw PFA_DOVARIABLE
+PFA_DIDR0:
+ .dw 126
+
+.endif
+.if WANT_ANALOG_COMPARATOR == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Control And Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw 80
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 1
+VE_DIDR1:
+ .dw $ff05
+ .db "DIDR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR1
+XT_DIDR1:
+ .dw PFA_DOVARIABLE
+PFA_DIDR1:
+ .dw 127
+
+.endif
+.if WANT_PORTB == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw 37
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw 36
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw 35
+
+.endif
+.if WANT_PORTC == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Register
+VE_PORTC:
+ .dw $ff05
+ .db "PORTC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTC
+XT_PORTC:
+ .dw PFA_DOVARIABLE
+PFA_PORTC:
+ .dw 40
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Direction Register
+VE_DDRC:
+ .dw $ff04
+ .db "DDRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRC
+XT_DDRC:
+ .dw PFA_DOVARIABLE
+PFA_DDRC:
+ .dw 39
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Input Pins
+VE_PINC:
+ .dw $ff04
+ .db "PINC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINC
+XT_PINC:
+ .dw PFA_DOVARIABLE
+PFA_PINC:
+ .dw 38
+
+.endif
+.if WANT_PORTD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw 43
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw 42
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw 41
+
+.endif
+.if WANT_TIMER_COUNTER_0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0B:
+ .dw $ff05
+ .db "OCR0B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0B
+XT_OCR0B:
+ .dw PFA_DOVARIABLE
+PFA_OCR0B:
+ .dw 72
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0A:
+ .dw $ff05
+ .db "OCR0A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0A
+XT_OCR0A:
+ .dw PFA_DOVARIABLE
+PFA_OCR0A:
+ .dw 71
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw 70
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register B
+VE_TCCR0B:
+ .dw $ff06
+ .db "TCCR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0B
+XT_TCCR0B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0B:
+ .dw 69
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register A
+VE_TCCR0A:
+ .dw $ff06
+ .db "TCCR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0A
+XT_TCCR0A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0A:
+ .dw 68
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Mask Register
+VE_TIMSK0:
+ .dw $ff06
+ .db "TIMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK0
+XT_TIMSK0:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK0:
+ .dw 110
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Flag register
+VE_TIFR0:
+ .dw $ff05
+ .db "TIFR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR0
+XT_TIFR0:
+ .dw PFA_DOVARIABLE
+PFA_TIFR0:
+ .dw 53
+
+.endif
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register
+VE_EICRA:
+ .dw $ff05
+ .db "EICRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRA
+XT_EICRA:
+ .dw PFA_DOVARIABLE
+PFA_EICRA:
+ .dw 105
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Mask Register
+VE_EIMSK:
+ .dw $ff05
+ .db "EIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIMSK
+XT_EIMSK:
+ .dw PFA_DOVARIABLE
+PFA_EIMSK:
+ .dw 61
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Flag Register
+VE_EIFR:
+ .dw $ff04
+ .db "EIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIFR
+XT_EIFR:
+ .dw PFA_DOVARIABLE
+PFA_EIFR:
+ .dw 60
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Interrupt Control Register
+VE_PCICR:
+ .dw $ff05
+ .db "PCICR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCICR
+XT_PCICR:
+ .dw PFA_DOVARIABLE
+PFA_PCICR:
+ .dw 104
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 2
+VE_PCMSK2:
+ .dw $ff06
+ .db "PCMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK2
+XT_PCMSK2:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK2:
+ .dw 109
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 1
+VE_PCMSK1:
+ .dw $ff06
+ .db "PCMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK1
+XT_PCMSK1:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK1:
+ .dw 108
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 0
+VE_PCMSK0:
+ .dw $ff06
+ .db "PCMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK0
+XT_PCMSK0:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK0:
+ .dw 107
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Interrupt Flag Register
+VE_PCIFR:
+ .dw $ff05
+ .db "PCIFR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCIFR
+XT_PCIFR:
+ .dw PFA_DOVARIABLE
+PFA_PCIFR:
+ .dw 59
+
+.endif
+.if WANT_SPI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR:
+ .dw $ff04
+ .db "SPDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR
+XT_SPDR:
+ .dw PFA_DOVARIABLE
+PFA_SPDR:
+ .dw 78
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR:
+ .dw $ff04
+ .db "SPSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR
+XT_SPSR:
+ .dw PFA_DOVARIABLE
+PFA_SPSR:
+ .dw 77
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR:
+ .dw $ff04
+ .db "SPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR
+XT_SPCR:
+ .dw PFA_DOVARIABLE
+PFA_SPCR:
+ .dw 76
+
+.endif
+.if WANT_WATCHDOG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCSR:
+ .dw $ff06
+ .db "WDTCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCSR
+XT_WDTCSR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCSR:
+ .dw 96
+
+.endif
+.if WANT_EEPROM == 1
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Address Register Bytes
+VE_EEAR:
+ .dw $ff04
+ .db "EEAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEAR
+XT_EEAR:
+ .dw PFA_DOVARIABLE
+PFA_EEAR:
+ .dw 65
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw 64
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw 63
+
+.endif
+.if WANT_CPU == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register
+VE_PRR:
+ .dw $ff03
+ .db "PRR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR
+XT_PRR:
+ .dw PFA_DOVARIABLE
+PFA_PRR:
+ .dw 100
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Calibration Value
+VE_OSCCAL:
+ .dw $ff06
+ .db "OSCCAL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSCCAL
+XT_OSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_OSCCAL:
+ .dw 102
+; ( -- addr ) System Constant
+; R( -- )
+; Clock Prescale Register
+VE_CLKPR:
+ .dw $ff05
+ .db "CLKPR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKPR
+XT_CLKPR:
+ .dw PFA_DOVARIABLE
+PFA_CLKPR:
+ .dw 97
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw 95
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer
+VE_SP:
+ .dw $ff02
+ .db "SP"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SP
+XT_SP:
+ .dw PFA_DOVARIABLE
+PFA_SP:
+ .dw 93
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control and Status Register
+VE_SPMCSR:
+ .dw $ff06
+ .db "SPMCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCSR
+XT_SPMCSR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCSR:
+ .dw 87
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw 85
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Status Register
+VE_MCUSR:
+ .dw $ff05
+ .db "MCUSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUSR
+XT_MCUSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUSR:
+ .dw 84
+; ( -- addr ) System Constant
+; R( -- )
+; Sleep Mode Control Register
+VE_SMCR:
+ .dw $ff04
+ .db "SMCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SMCR
+XT_SMCR:
+ .dw PFA_DOVARIABLE
+PFA_SMCR:
+ .dw 83
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose I/O Register 2
+VE_GPIOR2:
+ .dw $ff06
+ .db "GPIOR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR2
+XT_GPIOR2:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR2:
+ .dw 75
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose I/O Register 1
+VE_GPIOR1:
+ .dw $ff06
+ .db "GPIOR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR1
+XT_GPIOR1:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR1:
+ .dw 74
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose I/O Register 0
+VE_GPIOR0:
+ .dw $ff06
+ .db "GPIOR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR0
+XT_GPIOR0:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR0:
+ .dw 62
+
+.endif
diff --git a/amforth-6.5/avr8/devices/atmega168a/device.py b/amforth-6.5/avr8/devices/atmega168a/device.py
new file mode 100644
index 0000000..7bb795d
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega168a/device.py
@@ -0,0 +1,322 @@
+# Generated Automatically
+
+# Partname ATmega168A
+
+MCUREGS = {
+# Interrupt Vectors
+ 'INT0Addr' : '#2', # External Interrupt Request 0
+ 'INT1Addr' : '#4', # External Interrupt Request 1
+ 'PCINT0Addr' : '#6', # Pin Change Interrupt Request 0
+ 'PCINT1Addr' : '#8', # Pin Change Interrupt Request 0
+ 'PCINT2Addr' : '#10', # Pin Change Interrupt Request 1
+ 'WDTAddr' : '#12', # Watchdog Time-out Interrupt
+ 'TIMER2_COMPAAddr' : '#14', # Timer/Counter2 Compare Match A
+ 'TIMER2_COMPBAddr' : '#16', # Timer/Counter2 Compare Match A
+ 'TIMER2_OVFAddr' : '#18', # Timer/Counter2 Overflow
+ 'TIMER1_CAPTAddr' : '#20', # Timer/Counter1 Capture Event
+ 'TIMER1_COMPAAddr' : '#22', # Timer/Counter1 Compare Match A
+ 'TIMER1_COMPBAddr' : '#24', # Timer/Counter1 Compare Match B
+ 'TIMER1_OVFAddr' : '#26', # Timer/Counter1 Overflow
+ 'TIMER0_COMPAAddr' : '#28', # TimerCounter0 Compare Match A
+ 'TIMER0_COMPBAddr' : '#30', # TimerCounter0 Compare Match B
+ 'TIMER0_OVFAddr' : '#32', # Timer/Couner0 Overflow
+ 'SPI_STCAddr' : '#34', # SPI Serial Transfer Complete
+ 'USART_RXAddr' : '#36', # USART Rx Complete
+ 'USART_UDREAddr' : '#38', # USART, Data Register Empty
+ 'USART_TXAddr' : '#40', # USART Tx Complete
+ 'ADCAddr' : '#42', # ADC Conversion Complete
+ 'EE_READYAddr' : '#44', # EEPROM Ready
+ 'ANALOG_COMPAddr' : '#46', # Analog Comparator
+ 'TWIAddr' : '#48', # Two-wire Serial Interface
+ 'SPM_ReadyAddr' : '#50', # Store Program Memory Read
+
+# Module USART0
+ 'UDR0' : '$c6', # USART I/O Data Register
+ 'UCSR0A' : '$c0', # USART Control and Status Regis
+ 'UCSR0A_RXC0': '$80', # USART Receive Complete
+ 'UCSR0A_TXC0': '$40', # USART Transmitt Complete
+ 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
+ 'UCSR0A_FE0': '$10', # Framing Error
+ 'UCSR0A_DOR0': '$8', # Data overRun
+ 'UCSR0A_UPE0': '$4', # Parity Error
+ 'UCSR0A_U2X0': '$2', # Double the USART transmission
+ 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
+ 'UCSR0B' : '$c1', # USART Control and Status Regis
+ 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
+ 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
+ 'UCSR0B_UDRIE0': '$20', # USART Data register Empty Inte
+ 'UCSR0B_RXEN0': '$10', # Receiver Enable
+ 'UCSR0B_TXEN0': '$8', # Transmitter Enable
+ 'UCSR0B_UCSZ02': '$4', # Character Size
+ 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
+ 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
+ 'UCSR0C' : '$c2', # USART Control and Status Regis
+ 'UCSR0C_UMSEL0': '$c0', # USART Mode Select
+ 'UCSR0C_UPM0': '$30', # Parity Mode Bits
+ 'UCSR0C_USBS0': '$8', # Stop Bit Select
+ 'UCSR0C_UCSZ0': '$6', # Character Size
+ 'UCSR0C_UCPOL0': '$1', # Clock Polarity
+ 'UBRR0' : '$c4', # USART Baud Rate Register Byte
+
+# Module TWI
+ 'TWAMR' : '$bd', # TWI (Slave) Address Mask Regis
+ 'TWAMR_TWAM': '$fe', #
+ 'TWBR' : '$b8', # TWI Bit Rate register
+ 'TWCR' : '$bc', # TWI Control Register
+ 'TWCR_TWINT': '$80', # TWI Interrupt Flag
+ 'TWCR_TWEA': '$40', # TWI Enable Acknowledge Bit
+ 'TWCR_TWSTA': '$20', # TWI Start Condition Bit
+ 'TWCR_TWSTO': '$10', # TWI Stop Condition Bit
+ 'TWCR_TWWC': '$8', # TWI Write Collition Flag
+ 'TWCR_TWEN': '$4', # TWI Enable Bit
+ 'TWCR_TWIE': '$1', # TWI Interrupt Enable
+ 'TWSR' : '$b9', # TWI Status Register
+ 'TWSR_TWS': '$f8', # TWI Status
+ 'TWSR_TWPS': '$3', # TWI Prescaler
+ 'TWDR' : '$bb', # TWI Data register
+ 'TWAR' : '$ba', # TWI (Slave) Address register
+ 'TWAR_TWA': '$fe', # TWI (Slave) Address register B
+ 'TWAR_TWGCE': '$1', # TWI General Call Recognition E
+
+# Module TIMER_COUNTER_1
+ 'TIMSK1' : '$6f', # Timer/Counter Interrupt Mask R
+ 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
+ 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output CompareB
+ 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output CompareA
+ 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
+ 'TIFR1' : '$36', # Timer/Counter Interrupt Flag r
+ 'TIFR1_ICF1': '$20', # Input Capture Flag 1
+ 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
+ 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
+ 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
+ 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
+ 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
+ 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
+ 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
+ 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
+ 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
+ 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
+ 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
+ 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
+ 'TCCR1C' : '$82', # Timer/Counter1 Control Registe
+ 'TCCR1C_FOC1A': '$80', #
+ 'TCCR1C_FOC1B': '$40', #
+ 'TCNT1' : '$84', # Timer/Counter1 Bytes
+ 'OCR1A' : '$88', # Timer/Counter1 Output Compare
+ 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
+ 'ICR1' : '$86', # Timer/Counter1 Input Capture R
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSRSYNC': '$1', # Prescaler Reset Timer/Counter1
+
+# Module TIMER_COUNTER_2
+ 'TIMSK2' : '$70', # Timer/Counter Interrupt Mask r
+ 'TIMSK2_OCIE2B': '$4', # Timer/Counter2 Output Compare
+ 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
+ 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
+ 'TIFR2' : '$37', # Timer/Counter Interrupt Flag R
+ 'TIFR2_OCF2B': '$4', # Output Compare Flag 2B
+ 'TIFR2_OCF2A': '$2', # Output Compare Flag 2A
+ 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
+ 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
+ 'TCCR2A_COM2A': '$c0', # Compare Output Mode bits
+ 'TCCR2A_COM2B': '$30', # Compare Output Mode bits
+ 'TCCR2A_WGM2': '$3', # Waveform Genration Mode
+ 'TCCR2B' : '$b1', # Timer/Counter2 Control Registe
+ 'TCCR2B_FOC2A': '$80', # Force Output Compare A
+ 'TCCR2B_FOC2B': '$40', # Force Output Compare B
+ 'TCCR2B_WGM22': '$8', # Waveform Generation Mode
+ 'TCCR2B_CS2': '$7', # Clock Select bits
+ 'TCNT2' : '$b2', # Timer/Counter2
+ 'OCR2B' : '$b4', # Timer/Counter2 Output Compare
+ 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
+ 'ASSR' : '$b6', # Asynchronous Status Register
+ 'ASSR_EXCLK': '$40', # Enable External Clock Input
+ 'ASSR_AS2': '$20', # Asynchronous Timer/Counter2
+ 'ASSR_TCN2UB': '$10', # Timer/Counter2 Update Busy
+ 'ASSR_OCR2AUB': '$8', # Output Compare Register2 Updat
+ 'ASSR_OCR2BUB': '$4', # Output Compare Register 2 Upda
+ 'ASSR_TCR2AUB': '$2', # Timer/Counter Control Register
+ 'ASSR_TCR2BUB': '$1', # Timer/Counter Control Register
+ 'GTCCR' : '$43', # General Timer Counter Control
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSRASY': '$2', # Prescaler Reset Timer/Counter2
+
+# Module AD_CONVERTER
+ 'ADMUX' : '$7c', # The ADC multiplexer Selection
+ 'ADMUX_REFS': '$c0', # Reference Selection Bits
+ 'ADMUX_ADLAR': '$20', # Left Adjust Result
+ 'ADMUX_MUX': '$f', # Analog Channel and Gain Select
+ 'ADC' : '$78', # ADC Data Register Bytes
+ 'ADCSRA' : '$7a', # The ADC Control and Status reg
+ 'ADCSRA_ADEN': '$80', # ADC Enable
+ 'ADCSRA_ADSC': '$40', # ADC Start Conversion
+ 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
+ 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
+ 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
+ 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
+ 'ADCSRB' : '$7b', # The ADC Control and Status reg
+ 'ADCSRB_ACME': '$40', #
+ 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Source bits
+ 'DIDR0' : '$7e', # Digital Input Disable Register
+ 'DIDR0_ADC5D': '$20', #
+ 'DIDR0_ADC4D': '$10', #
+ 'DIDR0_ADC3D': '$8', #
+ 'DIDR0_ADC2D': '$4', #
+ 'DIDR0_ADC1D': '$2', #
+ 'DIDR0_ADC0D': '$1', #
+
+# Module ANALOG_COMPARATOR
+ 'ACSR' : '$50', # Analog Comparator Control And
+ 'ACSR_ACD': '$80', # Analog Comparator Disable
+ 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
+ 'ACSR_ACO': '$20', # Analog Compare Output
+ 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
+ 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
+ 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
+ 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
+ 'DIDR1' : '$7f', # Digital Input Disable Register
+ 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
+ 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
+
+# Module PORTB
+ 'PORTB' : '$25', # Port B Data Register
+ 'DDRB' : '$24', # Port B Data Direction Register
+ 'PINB' : '$23', # Port B Input Pins
+
+# Module PORTC
+ 'PORTC' : '$28', # Port C Data Register
+ 'DDRC' : '$27', # Port C Data Direction Register
+ 'PINC' : '$26', # Port C Input Pins
+
+# Module PORTD
+ 'PORTD' : '$2b', # Port D Data Register
+ 'DDRD' : '$2a', # Port D Data Direction Register
+ 'PIND' : '$29', # Port D Input Pins
+
+# Module TIMER_COUNTER_0
+ 'OCR0B' : '$48', # Timer/Counter0 Output Compare
+ 'OCR0A' : '$47', # Timer/Counter0 Output Compare
+ 'TCNT0' : '$46', # Timer/Counter0
+ 'TCCR0B' : '$45', # Timer/Counter Control Register
+ 'TCCR0B_FOC0A': '$80', # Force Output Compare A
+ 'TCCR0B_FOC0B': '$40', # Force Output Compare B
+ 'TCCR0B_WGM02': '$8', #
+ 'TCCR0B_CS0': '$7', # Clock Select
+ 'TCCR0A' : '$44', # Timer/Counter Control Registe
+ 'TCCR0A_COM0A': '$c0', # Compare Output Mode, Phase Cor
+ 'TCCR0A_COM0B': '$30', # Compare Output Mode, Fast PWm
+ 'TCCR0A_WGM0': '$3', # Waveform Generation Mode
+ 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
+ 'TIMSK0_OCIE0B': '$4', # Timer/Counter0 Output Compare
+ 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
+ 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
+ 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
+ 'TIFR0_OCF0B': '$4', # Timer/Counter0 Output Compare
+ 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
+ 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSRSYNC': '$1', # Prescaler Reset Timer/Counter1
+
+# Module EXTERNAL_INTERRUPT
+ 'EICRA' : '$69', # External Interrupt Control Reg
+ 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
+ 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
+ 'EIMSK' : '$3d', # External Interrupt Mask Regist
+ 'EIMSK_INT': '$3', # External Interrupt Request 1 E
+ 'EIFR' : '$3c', # External Interrupt Flag Regist
+ 'EIFR_INTF': '$3', # External Interrupt Flags
+ 'PCICR' : '$68', # Pin Change Interrupt Control R
+ 'PCICR_PCIE': '$7', # Pin Change Interrupt Enables
+ 'PCMSK2' : '$6d', # Pin Change Mask Register 2
+ 'PCMSK2_PCINT': '$ff', # Pin Change Enable Masks
+ 'PCMSK1' : '$6c', # Pin Change Mask Register 1
+ 'PCMSK1_PCINT': '$7f', # Pin Change Enable Masks
+ 'PCMSK0' : '$6b', # Pin Change Mask Register 0
+ 'PCMSK0_PCINT': '$ff', # Pin Change Enable Masks
+ 'PCIFR' : '$3b', # Pin Change Interrupt Flag Regi
+ 'PCIFR_PCIF': '$7', # Pin Change Interrupt Flags
+
+# Module SPI
+ 'SPDR' : '$4e', # SPI Data Register
+ 'SPSR' : '$4d', # SPI Status Register
+ 'SPSR_SPIF': '$80', # SPI Interrupt Flag
+ 'SPSR_WCOL': '$40', # Write Collision Flag
+ 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
+ 'SPCR' : '$4c', # SPI Control Register
+ 'SPCR_SPIE': '$80', # SPI Interrupt Enable
+ 'SPCR_SPE': '$40', # SPI Enable
+ 'SPCR_DORD': '$20', # Data Order
+ 'SPCR_MSTR': '$10', # Master/Slave Select
+ 'SPCR_CPOL': '$8', # Clock polarity
+ 'SPCR_CPHA': '$4', # Clock Phase
+ 'SPCR_SPR': '$3', # SPI Clock Rate Selects
+
+# Module WATCHDOG
+ 'WDTCSR' : '$60', # Watchdog Timer Control Registe
+ 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
+ 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
+ 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
+ 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
+ 'WDTCSR_WDE': '$8', # Watch Dog Enable
+
+# Module EEPROM
+ 'EEAR' : '$41', # EEPROM Address Register Bytes
+ 'EEDR' : '$40', # EEPROM Data Register
+ 'EECR' : '$3f', # EEPROM Control Register
+ 'EECR_EEPM': '$30', # EEPROM Programming Mode Bits
+ 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
+ 'EECR_EEMPE': '$4', # EEPROM Master Write Enable
+ 'EECR_EEPE': '$2', # EEPROM Write Enable
+ 'EECR_EERE': '$1', # EEPROM Read Enable
+
+# Module CPU
+ 'PRR' : '$64', # Power Reduction Register
+ 'PRR_PRTWI': '$80', # Power Reduction TWI
+ 'PRR_PRTIM2': '$40', # Power Reduction Timer/Counter2
+ 'PRR_PRTIM0': '$20', # Power Reduction Timer/Counter0
+ 'PRR_PRTIM1': '$8', # Power Reduction Timer/Counter1
+ 'PRR_PRSPI': '$4', # Power Reduction Serial Periphe
+ 'PRR_PRUSART0': '$2', # Power Reduction USART
+ 'PRR_PRADC': '$1', # Power Reduction ADC
+ 'OSCCAL' : '$66', # Oscillator Calibration Value
+ 'CLKPR' : '$61', # Clock Prescale Register
+ 'CLKPR_CLKPCE': '$80', # Clock Prescaler Change Enable
+ 'CLKPR_CLKPS': '$f', # Clock Prescaler Select Bits
+ 'SREG' : '$5f', # Status Register
+ 'SREG_I': '$80', # Global Interrupt Enable
+ 'SREG_T': '$40', # Bit Copy Storage
+ 'SREG_H': '$20', # Half Carry Flag
+ 'SREG_S': '$10', # Sign Bit
+ 'SREG_V': '$8', # Two's Complement Overflow Flag
+ 'SREG_N': '$4', # Negative Flag
+ 'SREG_Z': '$2', # Zero Flag
+ 'SREG_C': '$1', # Carry Flag
+ 'SP' : '$5d', # Stack Pointer
+ 'SPMCSR' : '$57', # Store Program Memory Control a
+ 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
+ 'SPMCSR_RWWSB': '$40', # Read-While-Write Section Busy
+ 'SPMCSR_RWWSRE': '$10', # Read-While-Write section read
+ 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
+ 'SPMCSR_PGWRT': '$4', # Page Write
+ 'SPMCSR_PGERS': '$2', # Page Erase
+ 'SPMCSR_SELFPRGEN': '$1', # Self Programming Enable
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_PUD': '$10', #
+ 'MCUCR_IVSEL': '$2', #
+ 'MCUCR_IVCE': '$1', #
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
+ 'MCUSR_BORF': '$4', # Brown-out Reset Flag
+ 'MCUSR_EXTRF': '$2', # External Reset Flag
+ 'MCUSR_PORF': '$1', # Power-on reset flag
+ 'SMCR' : '$53', # Sleep Mode Control Register
+ 'SMCR_SM': '$e', # Sleep Mode Select Bits
+ 'SMCR_SE': '$1', # Sleep Enable
+ 'GPIOR2' : '$4b', # General Purpose I/O Register 2
+ 'GPIOR1' : '$4a', # General Purpose I/O Register 1
+ 'GPIOR0' : '$3e', # General Purpose I/O Register 0
+
+ '__amforth_dummy':'0'
+}
diff --git a/amforth-6.5/avr8/devices/atmega168a/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega168a/words/no-jtag.asm
new file mode 100644
index 0000000..352a4bb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega168a/words/no-jtag.asm
@@ -0,0 +1,14 @@
+; ( -- )
+; ( -- )
+; MCU
+; disable jtag at runtime
+VE_NOJTAG:
+ .dw $FF05
+ .db "-jtag",0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOJTAG
+XT_NOJTAG:
+ .dw PFA_NOJTAG
+PFA_NOJTAG:
+
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega168a/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega168a/words/no-wdt.asm
new file mode 100644
index 0000000..ff6ddd1
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega168a/words/no-wdt.asm
@@ -0,0 +1,34 @@
+; ( -- )
+; MCU
+; disable watch dog timer at runtime
+VE_NOWDT:
+ .dw $ff04
+ .db "-wdt"
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOWDT
+XT_NOWDT:
+ .dw PFA_NOWDT
+PFA_NOWDT:
+
+ in temp1,SREG
+ push temp1
+ ; Turn always off global interrupt.
+ cli
+ ; Reset Watchdog Timer
+ wdr
+ ; Clear WDRF in MCUSR
+ in temp1, MCUSR
+ andi temp1, (0xff & (0<<WDRF))
+ out MCUSR, temp1
+ ; Write logical one to WDCE and WDE
+ ; Keep old prescaler setting to prevent unintentional time-out
+ in_ temp1, WDTCSR
+ ori temp1, (1<<WDCE) | (1<<WDE)
+ out_ WDTCSR, temp1
+ ; Turn off WDT
+ ldi temp1, (0<<WDE)
+ out_ WDTCSR, temp1
+ ; restore status register
+ pop temp1
+ out SREG,temp1
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega168a/words/sleep.asm b/amforth-6.5/avr8/devices/atmega168a/words/sleep.asm
new file mode 100644
index 0000000..256249c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega168a/words/sleep.asm
@@ -0,0 +1,19 @@
+; ( mode -- )
+; MCU
+; put the controller into the specified sleep mode
+VE_SLEEP:
+ .dw $ff05
+ .db "sleep", 0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_SLEEP
+XT_SLEEP:
+ .dw PFA_SLEEP
+PFA_SLEEP:
+ andi tosl, 7 ; leave only legal mode bits
+ lsl tosl ; move to correct location (bits 3-1)
+ ori tosl, 1 ; set the SE bit
+ out_ SMCR, tosl ; set the sleep config
+ sleep ; nighty-night
+ out_ SMCR, zerol ; 0 protects against accidental sleeps
+ loadtos ; pop argument from stack
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega168p/atmega168p.frt b/amforth-6.5/avr8/devices/atmega168p/atmega168p.frt
new file mode 100644
index 0000000..5e3d702
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega168p/atmega168p.frt
@@ -0,0 +1,299 @@
+\ Partname: ATmega168P
+\ generated automatically
+
+\ USART0
+&198 constant UDR0 \ USART I/O Data Register
+&192 constant UCSR0A \ USART Control and Status Register A
+ $80 constant UCSR0A_RXC0 \ USART Receive Complete
+ $40 constant UCSR0A_TXC0 \ USART Transmitt Complete
+ $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
+ $10 constant UCSR0A_FE0 \ Framing Error
+ $08 constant UCSR0A_DOR0 \ Data overRun
+ $04 constant UCSR0A_UPE0 \ Parity Error
+ $02 constant UCSR0A_U2X0 \ Double the USART transmission speed
+ $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
+&193 constant UCSR0B \ USART Control and Status Register B
+ $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
+ $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
+ $20 constant UCSR0B_UDRIE0 \ USART Data register Empty Interrupt Enable
+ $10 constant UCSR0B_RXEN0 \ Receiver Enable
+ $08 constant UCSR0B_TXEN0 \ Transmitter Enable
+ $04 constant UCSR0B_UCSZ02 \ Character Size
+ $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
+ $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
+&194 constant UCSR0C \ USART Control and Status Register C
+ $C0 constant UCSR0C_UMSEL0 \ USART Mode Select
+ $30 constant UCSR0C_UPM0 \ Parity Mode Bits
+ $08 constant UCSR0C_USBS0 \ Stop Bit Select
+ $06 constant UCSR0C_UCSZ0 \ Character Size
+ $01 constant UCSR0C_UCPOL0 \ Clock Polarity
+&196 constant UBRR0 \ USART Baud Rate Register Bytes
+\ TWI
+&189 constant TWAMR \ TWI (Slave) Address Mask Register
+ $FE constant TWAMR_TWAM \
+&184 constant TWBR \ TWI Bit Rate register
+&188 constant TWCR \ TWI Control Register
+ $80 constant TWCR_TWINT \ TWI Interrupt Flag
+ $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
+ $20 constant TWCR_TWSTA \ TWI Start Condition Bit
+ $10 constant TWCR_TWSTO \ TWI Stop Condition Bit
+ $08 constant TWCR_TWWC \ TWI Write Collition Flag
+ $04 constant TWCR_TWEN \ TWI Enable Bit
+ $01 constant TWCR_TWIE \ TWI Interrupt Enable
+&185 constant TWSR \ TWI Status Register
+ $F8 constant TWSR_TWS \ TWI Status
+ $03 constant TWSR_TWPS \ TWI Prescaler
+&187 constant TWDR \ TWI Data register
+&186 constant TWAR \ TWI (Slave) Address register
+ $FE constant TWAR_TWA \ TWI (Slave) Address register Bits
+ $01 constant TWAR_TWGCE \ TWI General Call Recognition Enable Bit
+\ TIMER_COUNTER_1
+&111 constant TIMSK1 \ Timer/Counter Interrupt Mask Register
+ $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
+ $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output CompareB Match Interrupt Enable
+ $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output CompareA Match Interrupt Enable
+ $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
+&54 constant TIFR1 \ Timer/Counter Interrupt Flag register
+ $20 constant TIFR1_ICF1 \ Input Capture Flag 1
+ $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
+ $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
+ $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
+&128 constant TCCR1A \ Timer/Counter1 Control Register A
+ $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
+ $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
+ $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
+&129 constant TCCR1B \ Timer/Counter1 Control Register B
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
+ $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
+&130 constant TCCR1C \ Timer/Counter1 Control Register C
+ $80 constant TCCR1C_FOC1A \
+ $40 constant TCCR1C_FOC1B \
+&132 constant TCNT1 \ Timer/Counter1 Bytes
+&136 constant OCR1A \ Timer/Counter1 Output Compare Register Bytes
+&138 constant OCR1B \ Timer/Counter1 Output Compare Register Bytes
+&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
+&67 constant GTCCR \ General Timer/Counter Control Register
+ $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
+ $01 constant GTCCR_PSRSYNC \ Prescaler Reset Timer/Counter1 and Timer/Counter0
+\ TIMER_COUNTER_2
+&112 constant TIMSK2 \ Timer/Counter Interrupt Mask register
+ $04 constant TIMSK2_OCIE2B \ Timer/Counter2 Output Compare Match B Interrupt Enable
+ $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match A Interrupt Enable
+ $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
+&55 constant TIFR2 \ Timer/Counter Interrupt Flag Register
+ $04 constant TIFR2_OCF2B \ Output Compare Flag 2B
+ $02 constant TIFR2_OCF2A \ Output Compare Flag 2A
+ $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
+&176 constant TCCR2A \ Timer/Counter2 Control Register A
+ $C0 constant TCCR2A_COM2A \ Compare Output Mode bits
+ $30 constant TCCR2A_COM2B \ Compare Output Mode bits
+ $03 constant TCCR2A_WGM2 \ Waveform Genration Mode
+&177 constant TCCR2B \ Timer/Counter2 Control Register B
+ $80 constant TCCR2B_FOC2A \ Force Output Compare A
+ $40 constant TCCR2B_FOC2B \ Force Output Compare B
+ $08 constant TCCR2B_WGM22 \ Waveform Generation Mode
+ $07 constant TCCR2B_CS2 \ Clock Select bits
+&178 constant TCNT2 \ Timer/Counter2
+&180 constant OCR2B \ Timer/Counter2 Output Compare Register B
+&179 constant OCR2A \ Timer/Counter2 Output Compare Register A
+&182 constant ASSR \ Asynchronous Status Register
+ $40 constant ASSR_EXCLK \ Enable External Clock Input
+ $20 constant ASSR_AS2 \ Asynchronous Timer/Counter2
+ $10 constant ASSR_TCN2UB \ Timer/Counter2 Update Busy
+ $08 constant ASSR_OCR2AUB \ Output Compare Register2 Update Busy
+ $04 constant ASSR_OCR2BUB \ Output Compare Register 2 Update Busy
+ $02 constant ASSR_TCR2AUB \ Timer/Counter Control Register2 Update Busy
+ $01 constant ASSR_TCR2BUB \ Timer/Counter Control Register2 Update Busy
+\ AD_CONVERTER
+&124 constant ADMUX \ The ADC multiplexer Selection Register
+ $C0 constant ADMUX_REFS \ Reference Selection Bits
+ $20 constant ADMUX_ADLAR \ Left Adjust Result
+ $0F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
+&120 constant ADC \ ADC Data Register Bytes
+&122 constant ADCSRA \ The ADC Control and Status register A
+ $80 constant ADCSRA_ADEN \ ADC Enable
+ $40 constant ADCSRA_ADSC \ ADC Start Conversion
+ $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
+ $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
+ $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
+ $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
+&123 constant ADCSRB \ The ADC Control and Status register B
+ $40 constant ADCSRB_ACME \
+ $07 constant ADCSRB_ADTS \ ADC Auto Trigger Source bits
+&126 constant DIDR0 \ Digital Input Disable Register
+ $20 constant DIDR0_ADC5D \
+ $10 constant DIDR0_ADC4D \
+ $08 constant DIDR0_ADC3D \
+ $04 constant DIDR0_ADC2D \
+ $02 constant DIDR0_ADC1D \
+ $01 constant DIDR0_ADC0D \
+\ ANALOG_COMPARATOR
+&80 constant ACSR \ Analog Comparator Control And Status Register
+ $80 constant ACSR_ACD \ Analog Comparator Disable
+ $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
+ $20 constant ACSR_ACO \ Analog Compare Output
+ $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
+ $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
+ $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
+ $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
+&127 constant DIDR1 \ Digital Input Disable Register 1
+ $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
+ $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
+\ PORTB
+&37 constant PORTB \ Port B Data Register
+&36 constant DDRB \ Port B Data Direction Register
+&35 constant PINB \ Port B Input Pins
+\ PORTC
+&40 constant PORTC \ Port C Data Register
+&39 constant DDRC \ Port C Data Direction Register
+&38 constant PINC \ Port C Input Pins
+\ PORTD
+&43 constant PORTD \ Port D Data Register
+&42 constant DDRD \ Port D Data Direction Register
+&41 constant PIND \ Port D Input Pins
+\ TIMER_COUNTER_0
+&72 constant OCR0B \ Timer/Counter0 Output Compare Register
+&71 constant OCR0A \ Timer/Counter0 Output Compare Register
+&70 constant TCNT0 \ Timer/Counter0
+&69 constant TCCR0B \ Timer/Counter Control Register B
+ $80 constant TCCR0B_FOC0A \ Force Output Compare A
+ $40 constant TCCR0B_FOC0B \ Force Output Compare B
+ $08 constant TCCR0B_WGM02 \
+ $07 constant TCCR0B_CS0 \ Clock Select
+&68 constant TCCR0A \ Timer/Counter Control Register A
+ $C0 constant TCCR0A_COM0A \ Compare Output Mode, Phase Correct PWM Mode
+ $30 constant TCCR0A_COM0B \ Compare Output Mode, Fast PWm
+ $03 constant TCCR0A_WGM0 \ Waveform Generation Mode
+&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
+ $04 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare Match B Interrupt Enable
+ $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match A Interrupt Enable
+ $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
+&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
+ $04 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare Flag 0B
+ $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0A
+ $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
+\ EXTERNAL_INTERRUPT
+&105 constant EICRA \ External Interrupt Control Register
+ $0C constant EICRA_ISC1 \ External Interrupt Sense Control 1 Bits
+ $03 constant EICRA_ISC0 \ External Interrupt Sense Control 0 Bits
+&61 constant EIMSK \ External Interrupt Mask Register
+ $03 constant EIMSK_INT \ External Interrupt Request 1 Enable
+&60 constant EIFR \ External Interrupt Flag Register
+ $03 constant EIFR_INTF \ External Interrupt Flags
+&104 constant PCICR \ Pin Change Interrupt Control Register
+ $07 constant PCICR_PCIE \ Pin Change Interrupt Enables
+&109 constant PCMSK2 \ Pin Change Mask Register 2
+ $FF constant PCMSK2_PCINT \ Pin Change Enable Masks
+&108 constant PCMSK1 \ Pin Change Mask Register 1
+ $7F constant PCMSK1_PCINT \ Pin Change Enable Masks
+&107 constant PCMSK0 \ Pin Change Mask Register 0
+ $FF constant PCMSK0_PCINT \ Pin Change Enable Masks
+&59 constant PCIFR \ Pin Change Interrupt Flag Register
+ $07 constant PCIFR_PCIF \ Pin Change Interrupt Flags
+\ SPI
+&78 constant SPDR \ SPI Data Register
+&77 constant SPSR \ SPI Status Register
+ $80 constant SPSR_SPIF \ SPI Interrupt Flag
+ $40 constant SPSR_WCOL \ Write Collision Flag
+ $01 constant SPSR_SPI2X \ Double SPI Speed Bit
+&76 constant SPCR \ SPI Control Register
+ $80 constant SPCR_SPIE \ SPI Interrupt Enable
+ $40 constant SPCR_SPE \ SPI Enable
+ $20 constant SPCR_DORD \ Data Order
+ $10 constant SPCR_MSTR \ Master/Slave Select
+ $08 constant SPCR_CPOL \ Clock polarity
+ $04 constant SPCR_CPHA \ Clock Phase
+ $03 constant SPCR_SPR \ SPI Clock Rate Selects
+\ WATCHDOG
+&96 constant WDTCSR \ Watchdog Timer Control Register
+ $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Flag
+ $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Enable
+ $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
+ $10 constant WDTCSR_WDCE \ Watchdog Change Enable
+ $08 constant WDTCSR_WDE \ Watch Dog Enable
+\ EEPROM
+&65 constant EEAR \ EEPROM Address Register Bytes
+&64 constant EEDR \ EEPROM Data Register
+&63 constant EECR \ EEPROM Control Register
+ $30 constant EECR_EEPM \ EEPROM Programming Mode Bits
+ $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
+ $04 constant EECR_EEMPE \ EEPROM Master Write Enable
+ $02 constant EECR_EEPE \ EEPROM Write Enable
+ $01 constant EECR_EERE \ EEPROM Read Enable
+\ CPU
+&100 constant PRR \ Power Reduction Register
+ $80 constant PRR_PRTWI \ Power Reduction TWI
+ $40 constant PRR_PRTIM2 \ Power Reduction Timer/Counter2
+ $20 constant PRR_PRTIM0 \ Power Reduction Timer/Counter0
+ $08 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
+ $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
+ $02 constant PRR_PRUSART0 \ Power Reduction USART
+ $01 constant PRR_PRADC \ Power Reduction ADC
+&102 constant OSCCAL \ Oscillator Calibration Value
+&97 constant CLKPR \ Clock Prescale Register
+ $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable
+ $0F constant CLKPR_CLKPS \ Clock Prescaler Select Bits
+&95 constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ $08 constant SREG_V \ Two's Complement Overflow Flag
+ $04 constant SREG_N \ Negative Flag
+ $02 constant SREG_Z \ Zero Flag
+ $01 constant SREG_C \ Carry Flag
+&93 constant SP \ Stack Pointer
+&87 constant SPMCSR \ Store Program Memory Control and Status Register
+ $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCSR_RWWSB \ Read-While-Write Section Busy
+ $10 constant SPMCSR_RWWSRE \ Read-While-Write section read enable
+ $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
+ $04 constant SPMCSR_PGWRT \ Page Write
+ $02 constant SPMCSR_PGERS \ Page Erase
+ $01 constant SPMCSR_SELFPRGEN \ Self Programming Enable
+&85 constant MCUCR \ MCU Control Register
+ $40 constant MCUCR_BODS \ BOD Sleep
+ $20 constant MCUCR_BODSE \ BOD Sleep Enable
+ $10 constant MCUCR_PUD \
+ $02 constant MCUCR_IVSEL \
+ $01 constant MCUCR_IVCE \
+&84 constant MCUSR \ MCU Status Register
+ $08 constant MCUSR_WDRF \ Watchdog Reset Flag
+ $04 constant MCUSR_BORF \ Brown-out Reset Flag
+ $02 constant MCUSR_EXTRF \ External Reset Flag
+ $01 constant MCUSR_PORF \ Power-on reset flag
+&83 constant SMCR \ Sleep Mode Control Register
+ $0E constant SMCR_SM \ Sleep Mode Select Bits
+ $01 constant SMCR_SE \ Sleep Enable
+&75 constant GPIOR2 \ General Purpose I/O Register 2
+&74 constant GPIOR1 \ General Purpose I/O Register 1
+&62 constant GPIOR0 \ General Purpose I/O Register 0
+
+\ Interrupts
+&2 constant INT0Addr \ External Interrupt Request 0
+&4 constant INT1Addr \ External Interrupt Request 1
+&6 constant PCINT0Addr \ Pin Change Interrupt Request 0
+&8 constant PCINT1Addr \ Pin Change Interrupt Request 0
+&10 constant PCINT2Addr \ Pin Change Interrupt Request 1
+&12 constant WDTAddr \ Watchdog Time-out Interrupt
+&14 constant TIMER2_COMPAAddr \ Timer/Counter2 Compare Match A
+&16 constant TIMER2_COMPBAddr \ Timer/Counter2 Compare Match A
+&18 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
+&20 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+&22 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
+&24 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
+&26 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+&28 constant TIMER0_COMPAAddr \ TimerCounter0 Compare Match A
+&30 constant TIMER0_COMPBAddr \ TimerCounter0 Compare Match B
+&32 constant TIMER0_OVFAddr \ Timer/Couner0 Overflow
+&34 constant SPI__STCAddr \ SPI Serial Transfer Complete
+&36 constant USART__RXAddr \ USART Rx Complete
+&38 constant USART__UDREAddr \ USART, Data Register Empty
+&40 constant USART__TXAddr \ USART Tx Complete
+&42 constant ADCAddr \ ADC Conversion Complete
+&44 constant EE_READYAddr \ EEPROM Ready
+&46 constant ANALOG_COMPAddr \ Analog Comparator
+&48 constant TWIAddr \ Two-wire Serial Interface
+&50 constant SPM_ReadyAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/atmega168p/device.asm b/amforth-6.5/avr8/devices/atmega168p/device.asm
new file mode 100644
index 0000000..81583e4
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega168p/device.asm
@@ -0,0 +1,107 @@
+; Partname: ATmega168P
+; generated automatically, do not edit
+
+.nolist
+ .include "m168Pdef.inc"
+.list
+
+.equ ramstart = 256
+.equ CELLSIZE = 2
+.macro readflashcell
+ lsl zl
+ rol zh
+ lpm @0, Z+
+ lpm @1, Z+
+.endmacro
+.macro writeflashcell
+ lsl zl
+ rol zh
+.endmacro
+.set WANT_USART0 = 0
+.set WANT_TWI = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_TIMER_COUNTER_2 = 0
+.set WANT_AD_CONVERTER = 0
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_PORTB = 0
+.set WANT_PORTC = 0
+.set WANT_PORTD = 0
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_SPI = 0
+.set WANT_WATCHDOG = 0
+.set WANT_EEPROM = 0
+.set WANT_CPU = 0
+.equ intvecsize = 2 ; please verify; flash size: 16384 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.org 2
+ rcall isr ; External Interrupt Request 0
+.org 4
+ rcall isr ; External Interrupt Request 1
+.org 6
+ rcall isr ; Pin Change Interrupt Request 0
+.org 8
+ rcall isr ; Pin Change Interrupt Request 0
+.org 10
+ rcall isr ; Pin Change Interrupt Request 1
+.org 12
+ rcall isr ; Watchdog Time-out Interrupt
+.org 14
+ rcall isr ; Timer/Counter2 Compare Match A
+.org 16
+ rcall isr ; Timer/Counter2 Compare Match A
+.org 18
+ rcall isr ; Timer/Counter2 Overflow
+.org 20
+ rcall isr ; Timer/Counter1 Capture Event
+.org 22
+ rcall isr ; Timer/Counter1 Compare Match A
+.org 24
+ rcall isr ; Timer/Counter1 Compare Match B
+.org 26
+ rcall isr ; Timer/Counter1 Overflow
+.org 28
+ rcall isr ; TimerCounter0 Compare Match A
+.org 30
+ rcall isr ; TimerCounter0 Compare Match B
+.org 32
+ rcall isr ; Timer/Couner0 Overflow
+.org 34
+ rcall isr ; SPI Serial Transfer Complete
+.org 36
+ rcall isr ; USART Rx Complete
+.org 38
+ rcall isr ; USART, Data Register Empty
+.org 40
+ rcall isr ; USART Tx Complete
+.org 42
+ rcall isr ; ADC Conversion Complete
+.org 44
+ rcall isr ; EEPROM Ready
+.org 46
+ rcall isr ; Analog Comparator
+.org 48
+ rcall isr ; Two-wire Serial Interface
+.org 50
+ rcall isr ; Store Program Memory Read
+.equ INTVECTORS = 26
+.nooverlap
+
+; compatability layer (maybe empty)
+.equ SPMEN = SELFPRGEN
+
+; controller data area, environment query mcu-info
+mcu_info:
+mcu_ramsize:
+ .dw 1024
+mcu_eepromsize:
+ .dw 512
+mcu_maxdp:
+ .dw 14336
+mcu_numints:
+ .dw 26
+mcu_name:
+ .dw 10
+ .db "ATmega168P"
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega168p/device.inc b/amforth-6.5/avr8/devices/atmega168p/device.inc
new file mode 100644
index 0000000..e544ad4
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega168p/device.inc
@@ -0,0 +1,996 @@
+; Partname: ATmega168P
+; generated automatically, no not edit
+
+.if WANT_USART0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR0:
+ .dw $ff04
+ .db "UDR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR0
+XT_UDR0:
+ .dw PFA_DOVARIABLE
+PFA_UDR0:
+ .dw 198
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR0A:
+ .dw $ff06
+ .db "UCSR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0A
+XT_UCSR0A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0A:
+ .dw 192
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR0B:
+ .dw $ff06
+ .db "UCSR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0B
+XT_UCSR0B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0B:
+ .dw 193
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR0C:
+ .dw $ff06
+ .db "UCSR0C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0C
+XT_UCSR0C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0C:
+ .dw 194
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Bytes
+VE_UBRR0:
+ .dw $ff05
+ .db "UBRR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR0
+XT_UBRR0:
+ .dw PFA_DOVARIABLE
+PFA_UBRR0:
+ .dw 196
+
+.endif
+.if WANT_TWI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; TWI (Slave) Address Mask Register
+VE_TWAMR:
+ .dw $ff05
+ .db "TWAMR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWAMR
+XT_TWAMR:
+ .dw PFA_DOVARIABLE
+PFA_TWAMR:
+ .dw 189
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Bit Rate register
+VE_TWBR:
+ .dw $ff04
+ .db "TWBR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWBR
+XT_TWBR:
+ .dw PFA_DOVARIABLE
+PFA_TWBR:
+ .dw 184
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Control Register
+VE_TWCR:
+ .dw $ff04
+ .db "TWCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWCR
+XT_TWCR:
+ .dw PFA_DOVARIABLE
+PFA_TWCR:
+ .dw 188
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Status Register
+VE_TWSR:
+ .dw $ff04
+ .db "TWSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWSR
+XT_TWSR:
+ .dw PFA_DOVARIABLE
+PFA_TWSR:
+ .dw 185
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Data register
+VE_TWDR:
+ .dw $ff04
+ .db "TWDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWDR
+XT_TWDR:
+ .dw PFA_DOVARIABLE
+PFA_TWDR:
+ .dw 187
+; ( -- addr ) System Constant
+; R( -- )
+; TWI (Slave) Address register
+VE_TWAR:
+ .dw $ff04
+ .db "TWAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWAR
+XT_TWAR:
+ .dw PFA_DOVARIABLE
+PFA_TWAR:
+ .dw 186
+
+.endif
+.if WANT_TIMER_COUNTER_1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Mask Register
+VE_TIMSK1:
+ .dw $ff06
+ .db "TIMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK1
+XT_TIMSK1:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK1:
+ .dw 111
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Flag register
+VE_TIFR1:
+ .dw $ff05
+ .db "TIFR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR1
+XT_TIFR1:
+ .dw PFA_DOVARIABLE
+PFA_TIFR1:
+ .dw 54
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw 128
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw 129
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register C
+VE_TCCR1C:
+ .dw $ff06
+ .db "TCCR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1C
+XT_TCCR1C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1C:
+ .dw 130
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Bytes
+VE_TCNT1:
+ .dw $ff05
+ .db "TCNT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1
+XT_TCNT1:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1:
+ .dw 132
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register Bytes
+VE_OCR1A:
+ .dw $ff05
+ .db "OCR1A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1A
+XT_OCR1A:
+ .dw PFA_DOVARIABLE
+PFA_OCR1A:
+ .dw 136
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register Bytes
+VE_OCR1B:
+ .dw $ff05
+ .db "OCR1B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1B
+XT_OCR1B:
+ .dw PFA_DOVARIABLE
+PFA_OCR1B:
+ .dw 138
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Bytes
+VE_ICR1:
+ .dw $ff04
+ .db "ICR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1
+XT_ICR1:
+ .dw PFA_DOVARIABLE
+PFA_ICR1:
+ .dw 134
+; ( -- addr ) System Constant
+; R( -- )
+; General Timer/Counter Control Register
+VE_GTCCR:
+ .dw $ff05
+ .db "GTCCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GTCCR
+XT_GTCCR:
+ .dw PFA_DOVARIABLE
+PFA_GTCCR:
+ .dw 67
+
+.endif
+.if WANT_TIMER_COUNTER_2 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Mask register
+VE_TIMSK2:
+ .dw $ff06
+ .db "TIMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK2
+XT_TIMSK2:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK2:
+ .dw 112
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Flag Register
+VE_TIFR2:
+ .dw $ff05
+ .db "TIFR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR2
+XT_TIFR2:
+ .dw PFA_DOVARIABLE
+PFA_TIFR2:
+ .dw 55
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register A
+VE_TCCR2A:
+ .dw $ff06
+ .db "TCCR2A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2A
+XT_TCCR2A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2A:
+ .dw 176
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register B
+VE_TCCR2B:
+ .dw $ff06
+ .db "TCCR2B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2B
+XT_TCCR2B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2B:
+ .dw 177
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2
+VE_TCNT2:
+ .dw $ff05
+ .db "TCNT2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT2
+XT_TCNT2:
+ .dw PFA_DOVARIABLE
+PFA_TCNT2:
+ .dw 178
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register B
+VE_OCR2B:
+ .dw $ff05
+ .db "OCR2B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2B
+XT_OCR2B:
+ .dw PFA_DOVARIABLE
+PFA_OCR2B:
+ .dw 180
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register A
+VE_OCR2A:
+ .dw $ff05
+ .db "OCR2A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2A
+XT_OCR2A:
+ .dw PFA_DOVARIABLE
+PFA_OCR2A:
+ .dw 179
+; ( -- addr ) System Constant
+; R( -- )
+; Asynchronous Status Register
+VE_ASSR:
+ .dw $ff04
+ .db "ASSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ASSR
+XT_ASSR:
+ .dw PFA_DOVARIABLE
+PFA_ASSR:
+ .dw 182
+
+.endif
+.if WANT_AD_CONVERTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC multiplexer Selection Register
+VE_ADMUX:
+ .dw $ff05
+ .db "ADMUX",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADMUX
+XT_ADMUX:
+ .dw PFA_DOVARIABLE
+PFA_ADMUX:
+ .dw 124
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register Bytes
+VE_ADC:
+ .dw $ff03
+ .db "ADC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADC
+XT_ADC:
+ .dw PFA_DOVARIABLE
+PFA_ADC:
+ .dw 120
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register A
+VE_ADCSRA:
+ .dw $ff06
+ .db "ADCSRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRA
+XT_ADCSRA:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRA:
+ .dw 122
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register B
+VE_ADCSRB:
+ .dw $ff06
+ .db "ADCSRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRB
+XT_ADCSRB:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRB:
+ .dw 123
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register
+VE_DIDR0:
+ .dw $ff05
+ .db "DIDR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR0
+XT_DIDR0:
+ .dw PFA_DOVARIABLE
+PFA_DIDR0:
+ .dw 126
+
+.endif
+.if WANT_ANALOG_COMPARATOR == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Control And Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw 80
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 1
+VE_DIDR1:
+ .dw $ff05
+ .db "DIDR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR1
+XT_DIDR1:
+ .dw PFA_DOVARIABLE
+PFA_DIDR1:
+ .dw 127
+
+.endif
+.if WANT_PORTB == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw 37
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw 36
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw 35
+
+.endif
+.if WANT_PORTC == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Register
+VE_PORTC:
+ .dw $ff05
+ .db "PORTC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTC
+XT_PORTC:
+ .dw PFA_DOVARIABLE
+PFA_PORTC:
+ .dw 40
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Direction Register
+VE_DDRC:
+ .dw $ff04
+ .db "DDRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRC
+XT_DDRC:
+ .dw PFA_DOVARIABLE
+PFA_DDRC:
+ .dw 39
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Input Pins
+VE_PINC:
+ .dw $ff04
+ .db "PINC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINC
+XT_PINC:
+ .dw PFA_DOVARIABLE
+PFA_PINC:
+ .dw 38
+
+.endif
+.if WANT_PORTD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw 43
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw 42
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw 41
+
+.endif
+.if WANT_TIMER_COUNTER_0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0B:
+ .dw $ff05
+ .db "OCR0B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0B
+XT_OCR0B:
+ .dw PFA_DOVARIABLE
+PFA_OCR0B:
+ .dw 72
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0A:
+ .dw $ff05
+ .db "OCR0A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0A
+XT_OCR0A:
+ .dw PFA_DOVARIABLE
+PFA_OCR0A:
+ .dw 71
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw 70
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register B
+VE_TCCR0B:
+ .dw $ff06
+ .db "TCCR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0B
+XT_TCCR0B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0B:
+ .dw 69
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register A
+VE_TCCR0A:
+ .dw $ff06
+ .db "TCCR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0A
+XT_TCCR0A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0A:
+ .dw 68
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Mask Register
+VE_TIMSK0:
+ .dw $ff06
+ .db "TIMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK0
+XT_TIMSK0:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK0:
+ .dw 110
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Flag register
+VE_TIFR0:
+ .dw $ff05
+ .db "TIFR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR0
+XT_TIFR0:
+ .dw PFA_DOVARIABLE
+PFA_TIFR0:
+ .dw 53
+
+.endif
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register
+VE_EICRA:
+ .dw $ff05
+ .db "EICRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRA
+XT_EICRA:
+ .dw PFA_DOVARIABLE
+PFA_EICRA:
+ .dw 105
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Mask Register
+VE_EIMSK:
+ .dw $ff05
+ .db "EIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIMSK
+XT_EIMSK:
+ .dw PFA_DOVARIABLE
+PFA_EIMSK:
+ .dw 61
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Flag Register
+VE_EIFR:
+ .dw $ff04
+ .db "EIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIFR
+XT_EIFR:
+ .dw PFA_DOVARIABLE
+PFA_EIFR:
+ .dw 60
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Interrupt Control Register
+VE_PCICR:
+ .dw $ff05
+ .db "PCICR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCICR
+XT_PCICR:
+ .dw PFA_DOVARIABLE
+PFA_PCICR:
+ .dw 104
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 2
+VE_PCMSK2:
+ .dw $ff06
+ .db "PCMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK2
+XT_PCMSK2:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK2:
+ .dw 109
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 1
+VE_PCMSK1:
+ .dw $ff06
+ .db "PCMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK1
+XT_PCMSK1:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK1:
+ .dw 108
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 0
+VE_PCMSK0:
+ .dw $ff06
+ .db "PCMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK0
+XT_PCMSK0:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK0:
+ .dw 107
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Interrupt Flag Register
+VE_PCIFR:
+ .dw $ff05
+ .db "PCIFR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCIFR
+XT_PCIFR:
+ .dw PFA_DOVARIABLE
+PFA_PCIFR:
+ .dw 59
+
+.endif
+.if WANT_SPI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR:
+ .dw $ff04
+ .db "SPDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR
+XT_SPDR:
+ .dw PFA_DOVARIABLE
+PFA_SPDR:
+ .dw 78
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR:
+ .dw $ff04
+ .db "SPSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR
+XT_SPSR:
+ .dw PFA_DOVARIABLE
+PFA_SPSR:
+ .dw 77
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR:
+ .dw $ff04
+ .db "SPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR
+XT_SPCR:
+ .dw PFA_DOVARIABLE
+PFA_SPCR:
+ .dw 76
+
+.endif
+.if WANT_WATCHDOG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCSR:
+ .dw $ff06
+ .db "WDTCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCSR
+XT_WDTCSR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCSR:
+ .dw 96
+
+.endif
+.if WANT_EEPROM == 1
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Address Register Bytes
+VE_EEAR:
+ .dw $ff04
+ .db "EEAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEAR
+XT_EEAR:
+ .dw PFA_DOVARIABLE
+PFA_EEAR:
+ .dw 65
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw 64
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw 63
+
+.endif
+.if WANT_CPU == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register
+VE_PRR:
+ .dw $ff03
+ .db "PRR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR
+XT_PRR:
+ .dw PFA_DOVARIABLE
+PFA_PRR:
+ .dw 100
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Calibration Value
+VE_OSCCAL:
+ .dw $ff06
+ .db "OSCCAL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSCCAL
+XT_OSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_OSCCAL:
+ .dw 102
+; ( -- addr ) System Constant
+; R( -- )
+; Clock Prescale Register
+VE_CLKPR:
+ .dw $ff05
+ .db "CLKPR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKPR
+XT_CLKPR:
+ .dw PFA_DOVARIABLE
+PFA_CLKPR:
+ .dw 97
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw 95
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer
+VE_SP:
+ .dw $ff02
+ .db "SP"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SP
+XT_SP:
+ .dw PFA_DOVARIABLE
+PFA_SP:
+ .dw 93
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control and Status Register
+VE_SPMCSR:
+ .dw $ff06
+ .db "SPMCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCSR
+XT_SPMCSR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCSR:
+ .dw 87
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw 85
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Status Register
+VE_MCUSR:
+ .dw $ff05
+ .db "MCUSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUSR
+XT_MCUSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUSR:
+ .dw 84
+; ( -- addr ) System Constant
+; R( -- )
+; Sleep Mode Control Register
+VE_SMCR:
+ .dw $ff04
+ .db "SMCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SMCR
+XT_SMCR:
+ .dw PFA_DOVARIABLE
+PFA_SMCR:
+ .dw 83
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose I/O Register 2
+VE_GPIOR2:
+ .dw $ff06
+ .db "GPIOR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR2
+XT_GPIOR2:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR2:
+ .dw 75
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose I/O Register 1
+VE_GPIOR1:
+ .dw $ff06
+ .db "GPIOR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR1
+XT_GPIOR1:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR1:
+ .dw 74
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose I/O Register 0
+VE_GPIOR0:
+ .dw $ff06
+ .db "GPIOR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR0
+XT_GPIOR0:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR0:
+ .dw 62
+
+.endif
diff --git a/amforth-6.5/avr8/devices/atmega168p/device.py b/amforth-6.5/avr8/devices/atmega168p/device.py
new file mode 100644
index 0000000..50c5f5b
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega168p/device.py
@@ -0,0 +1,324 @@
+# Generated Automatically
+
+# Partname ATmega168P
+
+MCUREGS = {
+# Interrupt Vectors
+ 'INT0Addr' : '#2', # External Interrupt Request 0
+ 'INT1Addr' : '#4', # External Interrupt Request 1
+ 'PCINT0Addr' : '#6', # Pin Change Interrupt Request 0
+ 'PCINT1Addr' : '#8', # Pin Change Interrupt Request 0
+ 'PCINT2Addr' : '#10', # Pin Change Interrupt Request 1
+ 'WDTAddr' : '#12', # Watchdog Time-out Interrupt
+ 'TIMER2_COMPAAddr' : '#14', # Timer/Counter2 Compare Match A
+ 'TIMER2_COMPBAddr' : '#16', # Timer/Counter2 Compare Match A
+ 'TIMER2_OVFAddr' : '#18', # Timer/Counter2 Overflow
+ 'TIMER1_CAPTAddr' : '#20', # Timer/Counter1 Capture Event
+ 'TIMER1_COMPAAddr' : '#22', # Timer/Counter1 Compare Match A
+ 'TIMER1_COMPBAddr' : '#24', # Timer/Counter1 Compare Match B
+ 'TIMER1_OVFAddr' : '#26', # Timer/Counter1 Overflow
+ 'TIMER0_COMPAAddr' : '#28', # TimerCounter0 Compare Match A
+ 'TIMER0_COMPBAddr' : '#30', # TimerCounter0 Compare Match B
+ 'TIMER0_OVFAddr' : '#32', # Timer/Couner0 Overflow
+ 'SPI_STCAddr' : '#34', # SPI Serial Transfer Complete
+ 'USART_RXAddr' : '#36', # USART Rx Complete
+ 'USART_UDREAddr' : '#38', # USART, Data Register Empty
+ 'USART_TXAddr' : '#40', # USART Tx Complete
+ 'ADCAddr' : '#42', # ADC Conversion Complete
+ 'EE_READYAddr' : '#44', # EEPROM Ready
+ 'ANALOG_COMPAddr' : '#46', # Analog Comparator
+ 'TWIAddr' : '#48', # Two-wire Serial Interface
+ 'SPM_ReadyAddr' : '#50', # Store Program Memory Read
+
+# Module USART0
+ 'UDR0' : '$c6', # USART I/O Data Register
+ 'UCSR0A' : '$c0', # USART Control and Status Regis
+ 'UCSR0A_RXC0': '$80', # USART Receive Complete
+ 'UCSR0A_TXC0': '$40', # USART Transmitt Complete
+ 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
+ 'UCSR0A_FE0': '$10', # Framing Error
+ 'UCSR0A_DOR0': '$8', # Data overRun
+ 'UCSR0A_UPE0': '$4', # Parity Error
+ 'UCSR0A_U2X0': '$2', # Double the USART transmission
+ 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
+ 'UCSR0B' : '$c1', # USART Control and Status Regis
+ 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
+ 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
+ 'UCSR0B_UDRIE0': '$20', # USART Data register Empty Inte
+ 'UCSR0B_RXEN0': '$10', # Receiver Enable
+ 'UCSR0B_TXEN0': '$8', # Transmitter Enable
+ 'UCSR0B_UCSZ02': '$4', # Character Size
+ 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
+ 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
+ 'UCSR0C' : '$c2', # USART Control and Status Regis
+ 'UCSR0C_UMSEL0': '$c0', # USART Mode Select
+ 'UCSR0C_UPM0': '$30', # Parity Mode Bits
+ 'UCSR0C_USBS0': '$8', # Stop Bit Select
+ 'UCSR0C_UCSZ0': '$6', # Character Size
+ 'UCSR0C_UCPOL0': '$1', # Clock Polarity
+ 'UBRR0' : '$c4', # USART Baud Rate Register Byte
+
+# Module TWI
+ 'TWAMR' : '$bd', # TWI (Slave) Address Mask Regis
+ 'TWAMR_TWAM': '$fe', #
+ 'TWBR' : '$b8', # TWI Bit Rate register
+ 'TWCR' : '$bc', # TWI Control Register
+ 'TWCR_TWINT': '$80', # TWI Interrupt Flag
+ 'TWCR_TWEA': '$40', # TWI Enable Acknowledge Bit
+ 'TWCR_TWSTA': '$20', # TWI Start Condition Bit
+ 'TWCR_TWSTO': '$10', # TWI Stop Condition Bit
+ 'TWCR_TWWC': '$8', # TWI Write Collition Flag
+ 'TWCR_TWEN': '$4', # TWI Enable Bit
+ 'TWCR_TWIE': '$1', # TWI Interrupt Enable
+ 'TWSR' : '$b9', # TWI Status Register
+ 'TWSR_TWS': '$f8', # TWI Status
+ 'TWSR_TWPS': '$3', # TWI Prescaler
+ 'TWDR' : '$bb', # TWI Data register
+ 'TWAR' : '$ba', # TWI (Slave) Address register
+ 'TWAR_TWA': '$fe', # TWI (Slave) Address register B
+ 'TWAR_TWGCE': '$1', # TWI General Call Recognition E
+
+# Module TIMER_COUNTER_1
+ 'TIMSK1' : '$6f', # Timer/Counter Interrupt Mask R
+ 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
+ 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output CompareB
+ 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output CompareA
+ 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
+ 'TIFR1' : '$36', # Timer/Counter Interrupt Flag r
+ 'TIFR1_ICF1': '$20', # Input Capture Flag 1
+ 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
+ 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
+ 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
+ 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
+ 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
+ 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
+ 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
+ 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
+ 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
+ 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
+ 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
+ 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
+ 'TCCR1C' : '$82', # Timer/Counter1 Control Registe
+ 'TCCR1C_FOC1A': '$80', #
+ 'TCCR1C_FOC1B': '$40', #
+ 'TCNT1' : '$84', # Timer/Counter1 Bytes
+ 'OCR1A' : '$88', # Timer/Counter1 Output Compare
+ 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
+ 'ICR1' : '$86', # Timer/Counter1 Input Capture R
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSRSYNC': '$1', # Prescaler Reset Timer/Counter1
+
+# Module TIMER_COUNTER_2
+ 'TIMSK2' : '$70', # Timer/Counter Interrupt Mask r
+ 'TIMSK2_OCIE2B': '$4', # Timer/Counter2 Output Compare
+ 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
+ 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
+ 'TIFR2' : '$37', # Timer/Counter Interrupt Flag R
+ 'TIFR2_OCF2B': '$4', # Output Compare Flag 2B
+ 'TIFR2_OCF2A': '$2', # Output Compare Flag 2A
+ 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
+ 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
+ 'TCCR2A_COM2A': '$c0', # Compare Output Mode bits
+ 'TCCR2A_COM2B': '$30', # Compare Output Mode bits
+ 'TCCR2A_WGM2': '$3', # Waveform Genration Mode
+ 'TCCR2B' : '$b1', # Timer/Counter2 Control Registe
+ 'TCCR2B_FOC2A': '$80', # Force Output Compare A
+ 'TCCR2B_FOC2B': '$40', # Force Output Compare B
+ 'TCCR2B_WGM22': '$8', # Waveform Generation Mode
+ 'TCCR2B_CS2': '$7', # Clock Select bits
+ 'TCNT2' : '$b2', # Timer/Counter2
+ 'OCR2B' : '$b4', # Timer/Counter2 Output Compare
+ 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
+ 'ASSR' : '$b6', # Asynchronous Status Register
+ 'ASSR_EXCLK': '$40', # Enable External Clock Input
+ 'ASSR_AS2': '$20', # Asynchronous Timer/Counter2
+ 'ASSR_TCN2UB': '$10', # Timer/Counter2 Update Busy
+ 'ASSR_OCR2AUB': '$8', # Output Compare Register2 Updat
+ 'ASSR_OCR2BUB': '$4', # Output Compare Register 2 Upda
+ 'ASSR_TCR2AUB': '$2', # Timer/Counter Control Register
+ 'ASSR_TCR2BUB': '$1', # Timer/Counter Control Register
+ 'GTCCR' : '$43', # General Timer Counter Control
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSRASY': '$2', # Prescaler Reset Timer/Counter2
+
+# Module AD_CONVERTER
+ 'ADMUX' : '$7c', # The ADC multiplexer Selection
+ 'ADMUX_REFS': '$c0', # Reference Selection Bits
+ 'ADMUX_ADLAR': '$20', # Left Adjust Result
+ 'ADMUX_MUX': '$f', # Analog Channel and Gain Select
+ 'ADC' : '$78', # ADC Data Register Bytes
+ 'ADCSRA' : '$7a', # The ADC Control and Status reg
+ 'ADCSRA_ADEN': '$80', # ADC Enable
+ 'ADCSRA_ADSC': '$40', # ADC Start Conversion
+ 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
+ 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
+ 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
+ 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
+ 'ADCSRB' : '$7b', # The ADC Control and Status reg
+ 'ADCSRB_ACME': '$40', #
+ 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Source bits
+ 'DIDR0' : '$7e', # Digital Input Disable Register
+ 'DIDR0_ADC5D': '$20', #
+ 'DIDR0_ADC4D': '$10', #
+ 'DIDR0_ADC3D': '$8', #
+ 'DIDR0_ADC2D': '$4', #
+ 'DIDR0_ADC1D': '$2', #
+ 'DIDR0_ADC0D': '$1', #
+
+# Module ANALOG_COMPARATOR
+ 'ACSR' : '$50', # Analog Comparator Control And
+ 'ACSR_ACD': '$80', # Analog Comparator Disable
+ 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
+ 'ACSR_ACO': '$20', # Analog Compare Output
+ 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
+ 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
+ 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
+ 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
+ 'DIDR1' : '$7f', # Digital Input Disable Register
+ 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
+ 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
+
+# Module PORTB
+ 'PORTB' : '$25', # Port B Data Register
+ 'DDRB' : '$24', # Port B Data Direction Register
+ 'PINB' : '$23', # Port B Input Pins
+
+# Module PORTC
+ 'PORTC' : '$28', # Port C Data Register
+ 'DDRC' : '$27', # Port C Data Direction Register
+ 'PINC' : '$26', # Port C Input Pins
+
+# Module PORTD
+ 'PORTD' : '$2b', # Port D Data Register
+ 'DDRD' : '$2a', # Port D Data Direction Register
+ 'PIND' : '$29', # Port D Input Pins
+
+# Module TIMER_COUNTER_0
+ 'OCR0B' : '$48', # Timer/Counter0 Output Compare
+ 'OCR0A' : '$47', # Timer/Counter0 Output Compare
+ 'TCNT0' : '$46', # Timer/Counter0
+ 'TCCR0B' : '$45', # Timer/Counter Control Register
+ 'TCCR0B_FOC0A': '$80', # Force Output Compare A
+ 'TCCR0B_FOC0B': '$40', # Force Output Compare B
+ 'TCCR0B_WGM02': '$8', #
+ 'TCCR0B_CS0': '$7', # Clock Select
+ 'TCCR0A' : '$44', # Timer/Counter Control Registe
+ 'TCCR0A_COM0A': '$c0', # Compare Output Mode, Phase Cor
+ 'TCCR0A_COM0B': '$30', # Compare Output Mode, Fast PWm
+ 'TCCR0A_WGM0': '$3', # Waveform Generation Mode
+ 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
+ 'TIMSK0_OCIE0B': '$4', # Timer/Counter0 Output Compare
+ 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
+ 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
+ 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
+ 'TIFR0_OCF0B': '$4', # Timer/Counter0 Output Compare
+ 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
+ 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSRSYNC': '$1', # Prescaler Reset Timer/Counter1
+
+# Module EXTERNAL_INTERRUPT
+ 'EICRA' : '$69', # External Interrupt Control Reg
+ 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
+ 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
+ 'EIMSK' : '$3d', # External Interrupt Mask Regist
+ 'EIMSK_INT': '$3', # External Interrupt Request 1 E
+ 'EIFR' : '$3c', # External Interrupt Flag Regist
+ 'EIFR_INTF': '$3', # External Interrupt Flags
+ 'PCICR' : '$68', # Pin Change Interrupt Control R
+ 'PCICR_PCIE': '$7', # Pin Change Interrupt Enables
+ 'PCMSK2' : '$6d', # Pin Change Mask Register 2
+ 'PCMSK2_PCINT': '$ff', # Pin Change Enable Masks
+ 'PCMSK1' : '$6c', # Pin Change Mask Register 1
+ 'PCMSK1_PCINT': '$7f', # Pin Change Enable Masks
+ 'PCMSK0' : '$6b', # Pin Change Mask Register 0
+ 'PCMSK0_PCINT': '$ff', # Pin Change Enable Masks
+ 'PCIFR' : '$3b', # Pin Change Interrupt Flag Regi
+ 'PCIFR_PCIF': '$7', # Pin Change Interrupt Flags
+
+# Module SPI
+ 'SPDR' : '$4e', # SPI Data Register
+ 'SPSR' : '$4d', # SPI Status Register
+ 'SPSR_SPIF': '$80', # SPI Interrupt Flag
+ 'SPSR_WCOL': '$40', # Write Collision Flag
+ 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
+ 'SPCR' : '$4c', # SPI Control Register
+ 'SPCR_SPIE': '$80', # SPI Interrupt Enable
+ 'SPCR_SPE': '$40', # SPI Enable
+ 'SPCR_DORD': '$20', # Data Order
+ 'SPCR_MSTR': '$10', # Master/Slave Select
+ 'SPCR_CPOL': '$8', # Clock polarity
+ 'SPCR_CPHA': '$4', # Clock Phase
+ 'SPCR_SPR': '$3', # SPI Clock Rate Selects
+
+# Module WATCHDOG
+ 'WDTCSR' : '$60', # Watchdog Timer Control Registe
+ 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
+ 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
+ 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
+ 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
+ 'WDTCSR_WDE': '$8', # Watch Dog Enable
+
+# Module EEPROM
+ 'EEAR' : '$41', # EEPROM Address Register Bytes
+ 'EEDR' : '$40', # EEPROM Data Register
+ 'EECR' : '$3f', # EEPROM Control Register
+ 'EECR_EEPM': '$30', # EEPROM Programming Mode Bits
+ 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
+ 'EECR_EEMPE': '$4', # EEPROM Master Write Enable
+ 'EECR_EEPE': '$2', # EEPROM Write Enable
+ 'EECR_EERE': '$1', # EEPROM Read Enable
+
+# Module CPU
+ 'PRR' : '$64', # Power Reduction Register
+ 'PRR_PRTWI': '$80', # Power Reduction TWI
+ 'PRR_PRTIM2': '$40', # Power Reduction Timer/Counter2
+ 'PRR_PRTIM0': '$20', # Power Reduction Timer/Counter0
+ 'PRR_PRTIM1': '$8', # Power Reduction Timer/Counter1
+ 'PRR_PRSPI': '$4', # Power Reduction Serial Periphe
+ 'PRR_PRUSART0': '$2', # Power Reduction USART
+ 'PRR_PRADC': '$1', # Power Reduction ADC
+ 'OSCCAL' : '$66', # Oscillator Calibration Value
+ 'CLKPR' : '$61', # Clock Prescale Register
+ 'CLKPR_CLKPCE': '$80', # Clock Prescaler Change Enable
+ 'CLKPR_CLKPS': '$f', # Clock Prescaler Select Bits
+ 'SREG' : '$5f', # Status Register
+ 'SREG_I': '$80', # Global Interrupt Enable
+ 'SREG_T': '$40', # Bit Copy Storage
+ 'SREG_H': '$20', # Half Carry Flag
+ 'SREG_S': '$10', # Sign Bit
+ 'SREG_V': '$8', # Two's Complement Overflow Flag
+ 'SREG_N': '$4', # Negative Flag
+ 'SREG_Z': '$2', # Zero Flag
+ 'SREG_C': '$1', # Carry Flag
+ 'SP' : '$5d', # Stack Pointer
+ 'SPMCSR' : '$57', # Store Program Memory Control a
+ 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
+ 'SPMCSR_RWWSB': '$40', # Read-While-Write Section Busy
+ 'SPMCSR_RWWSRE': '$10', # Read-While-Write section read
+ 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
+ 'SPMCSR_PGWRT': '$4', # Page Write
+ 'SPMCSR_PGERS': '$2', # Page Erase
+ 'SPMCSR_SELFPRGEN': '$1', # Self Programming Enable
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_BODS': '$40', # BOD Sleep
+ 'MCUCR_BODSE': '$20', # BOD Sleep Enable
+ 'MCUCR_PUD': '$10', #
+ 'MCUCR_IVSEL': '$2', #
+ 'MCUCR_IVCE': '$1', #
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
+ 'MCUSR_BORF': '$4', # Brown-out Reset Flag
+ 'MCUSR_EXTRF': '$2', # External Reset Flag
+ 'MCUSR_PORF': '$1', # Power-on reset flag
+ 'SMCR' : '$53', # Sleep Mode Control Register
+ 'SMCR_SM': '$e', # Sleep Mode Select Bits
+ 'SMCR_SE': '$1', # Sleep Enable
+ 'GPIOR2' : '$4b', # General Purpose I/O Register 2
+ 'GPIOR1' : '$4a', # General Purpose I/O Register 1
+ 'GPIOR0' : '$3e', # General Purpose I/O Register 0
+
+ '__amforth_dummy':'0'
+}
diff --git a/amforth-6.5/avr8/devices/atmega168p/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega168p/words/no-jtag.asm
new file mode 100644
index 0000000..352a4bb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega168p/words/no-jtag.asm
@@ -0,0 +1,14 @@
+; ( -- )
+; ( -- )
+; MCU
+; disable jtag at runtime
+VE_NOJTAG:
+ .dw $FF05
+ .db "-jtag",0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOJTAG
+XT_NOJTAG:
+ .dw PFA_NOJTAG
+PFA_NOJTAG:
+
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega168p/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega168p/words/no-wdt.asm
new file mode 100644
index 0000000..ff6ddd1
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega168p/words/no-wdt.asm
@@ -0,0 +1,34 @@
+; ( -- )
+; MCU
+; disable watch dog timer at runtime
+VE_NOWDT:
+ .dw $ff04
+ .db "-wdt"
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOWDT
+XT_NOWDT:
+ .dw PFA_NOWDT
+PFA_NOWDT:
+
+ in temp1,SREG
+ push temp1
+ ; Turn always off global interrupt.
+ cli
+ ; Reset Watchdog Timer
+ wdr
+ ; Clear WDRF in MCUSR
+ in temp1, MCUSR
+ andi temp1, (0xff & (0<<WDRF))
+ out MCUSR, temp1
+ ; Write logical one to WDCE and WDE
+ ; Keep old prescaler setting to prevent unintentional time-out
+ in_ temp1, WDTCSR
+ ori temp1, (1<<WDCE) | (1<<WDE)
+ out_ WDTCSR, temp1
+ ; Turn off WDT
+ ldi temp1, (0<<WDE)
+ out_ WDTCSR, temp1
+ ; restore status register
+ pop temp1
+ out SREG,temp1
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega168p/words/sleep.asm b/amforth-6.5/avr8/devices/atmega168p/words/sleep.asm
new file mode 100644
index 0000000..256249c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega168p/words/sleep.asm
@@ -0,0 +1,19 @@
+; ( mode -- )
+; MCU
+; put the controller into the specified sleep mode
+VE_SLEEP:
+ .dw $ff05
+ .db "sleep", 0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_SLEEP
+XT_SLEEP:
+ .dw PFA_SLEEP
+PFA_SLEEP:
+ andi tosl, 7 ; leave only legal mode bits
+ lsl tosl ; move to correct location (bits 3-1)
+ ori tosl, 1 ; set the SE bit
+ out_ SMCR, tosl ; set the sleep config
+ sleep ; nighty-night
+ out_ SMCR, zerol ; 0 protects against accidental sleeps
+ loadtos ; pop argument from stack
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega168pa/atmega168pa.frt b/amforth-6.5/avr8/devices/atmega168pa/atmega168pa.frt
new file mode 100644
index 0000000..120d837
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega168pa/atmega168pa.frt
@@ -0,0 +1,299 @@
+\ Partname: ATmega168PA
+\ generated automatically
+
+\ USART0
+&198 constant UDR0 \ USART I/O Data Register
+&192 constant UCSR0A \ USART Control and Status Register A
+ $80 constant UCSR0A_RXC0 \ USART Receive Complete
+ $40 constant UCSR0A_TXC0 \ USART Transmitt Complete
+ $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
+ $10 constant UCSR0A_FE0 \ Framing Error
+ $08 constant UCSR0A_DOR0 \ Data overRun
+ $04 constant UCSR0A_UPE0 \ Parity Error
+ $02 constant UCSR0A_U2X0 \ Double the USART transmission speed
+ $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
+&193 constant UCSR0B \ USART Control and Status Register B
+ $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
+ $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
+ $20 constant UCSR0B_UDRIE0 \ USART Data register Empty Interrupt Enable
+ $10 constant UCSR0B_RXEN0 \ Receiver Enable
+ $08 constant UCSR0B_TXEN0 \ Transmitter Enable
+ $04 constant UCSR0B_UCSZ02 \ Character Size
+ $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
+ $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
+&194 constant UCSR0C \ USART Control and Status Register C
+ $C0 constant UCSR0C_UMSEL0 \ USART Mode Select
+ $30 constant UCSR0C_UPM0 \ Parity Mode Bits
+ $08 constant UCSR0C_USBS0 \ Stop Bit Select
+ $06 constant UCSR0C_UCSZ0 \ Character Size
+ $01 constant UCSR0C_UCPOL0 \ Clock Polarity
+&196 constant UBRR0 \ USART Baud Rate Register Bytes
+\ TWI
+&189 constant TWAMR \ TWI (Slave) Address Mask Register
+ $FE constant TWAMR_TWAM \
+&184 constant TWBR \ TWI Bit Rate register
+&188 constant TWCR \ TWI Control Register
+ $80 constant TWCR_TWINT \ TWI Interrupt Flag
+ $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
+ $20 constant TWCR_TWSTA \ TWI Start Condition Bit
+ $10 constant TWCR_TWSTO \ TWI Stop Condition Bit
+ $08 constant TWCR_TWWC \ TWI Write Collition Flag
+ $04 constant TWCR_TWEN \ TWI Enable Bit
+ $01 constant TWCR_TWIE \ TWI Interrupt Enable
+&185 constant TWSR \ TWI Status Register
+ $F8 constant TWSR_TWS \ TWI Status
+ $03 constant TWSR_TWPS \ TWI Prescaler
+&187 constant TWDR \ TWI Data register
+&186 constant TWAR \ TWI (Slave) Address register
+ $FE constant TWAR_TWA \ TWI (Slave) Address register Bits
+ $01 constant TWAR_TWGCE \ TWI General Call Recognition Enable Bit
+\ TIMER_COUNTER_1
+&111 constant TIMSK1 \ Timer/Counter Interrupt Mask Register
+ $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
+ $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output CompareB Match Interrupt Enable
+ $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output CompareA Match Interrupt Enable
+ $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
+&54 constant TIFR1 \ Timer/Counter Interrupt Flag register
+ $20 constant TIFR1_ICF1 \ Input Capture Flag 1
+ $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
+ $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
+ $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
+&128 constant TCCR1A \ Timer/Counter1 Control Register A
+ $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
+ $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
+ $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
+&129 constant TCCR1B \ Timer/Counter1 Control Register B
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
+ $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
+&130 constant TCCR1C \ Timer/Counter1 Control Register C
+ $80 constant TCCR1C_FOC1A \
+ $40 constant TCCR1C_FOC1B \
+&132 constant TCNT1 \ Timer/Counter1 Bytes
+&136 constant OCR1A \ Timer/Counter1 Output Compare Register Bytes
+&138 constant OCR1B \ Timer/Counter1 Output Compare Register Bytes
+&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
+&67 constant GTCCR \ General Timer/Counter Control Register
+ $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
+ $01 constant GTCCR_PSRSYNC \ Prescaler Reset Timer/Counter1 and Timer/Counter0
+\ TIMER_COUNTER_2
+&112 constant TIMSK2 \ Timer/Counter Interrupt Mask register
+ $04 constant TIMSK2_OCIE2B \ Timer/Counter2 Output Compare Match B Interrupt Enable
+ $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match A Interrupt Enable
+ $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
+&55 constant TIFR2 \ Timer/Counter Interrupt Flag Register
+ $04 constant TIFR2_OCF2B \ Output Compare Flag 2B
+ $02 constant TIFR2_OCF2A \ Output Compare Flag 2A
+ $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
+&176 constant TCCR2A \ Timer/Counter2 Control Register A
+ $C0 constant TCCR2A_COM2A \ Compare Output Mode bits
+ $30 constant TCCR2A_COM2B \ Compare Output Mode bits
+ $03 constant TCCR2A_WGM2 \ Waveform Genration Mode
+&177 constant TCCR2B \ Timer/Counter2 Control Register B
+ $80 constant TCCR2B_FOC2A \ Force Output Compare A
+ $40 constant TCCR2B_FOC2B \ Force Output Compare B
+ $08 constant TCCR2B_WGM22 \ Waveform Generation Mode
+ $07 constant TCCR2B_CS2 \ Clock Select bits
+&178 constant TCNT2 \ Timer/Counter2
+&180 constant OCR2B \ Timer/Counter2 Output Compare Register B
+&179 constant OCR2A \ Timer/Counter2 Output Compare Register A
+&182 constant ASSR \ Asynchronous Status Register
+ $40 constant ASSR_EXCLK \ Enable External Clock Input
+ $20 constant ASSR_AS2 \ Asynchronous Timer/Counter2
+ $10 constant ASSR_TCN2UB \ Timer/Counter2 Update Busy
+ $08 constant ASSR_OCR2AUB \ Output Compare Register2 Update Busy
+ $04 constant ASSR_OCR2BUB \ Output Compare Register 2 Update Busy
+ $02 constant ASSR_TCR2AUB \ Timer/Counter Control Register2 Update Busy
+ $01 constant ASSR_TCR2BUB \ Timer/Counter Control Register2 Update Busy
+\ AD_CONVERTER
+&124 constant ADMUX \ The ADC multiplexer Selection Register
+ $C0 constant ADMUX_REFS \ Reference Selection Bits
+ $20 constant ADMUX_ADLAR \ Left Adjust Result
+ $0F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
+&120 constant ADC \ ADC Data Register Bytes
+&122 constant ADCSRA \ The ADC Control and Status register A
+ $80 constant ADCSRA_ADEN \ ADC Enable
+ $40 constant ADCSRA_ADSC \ ADC Start Conversion
+ $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
+ $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
+ $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
+ $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
+&123 constant ADCSRB \ The ADC Control and Status register B
+ $40 constant ADCSRB_ACME \
+ $07 constant ADCSRB_ADTS \ ADC Auto Trigger Source bits
+&126 constant DIDR0 \ Digital Input Disable Register
+ $20 constant DIDR0_ADC5D \
+ $10 constant DIDR0_ADC4D \
+ $08 constant DIDR0_ADC3D \
+ $04 constant DIDR0_ADC2D \
+ $02 constant DIDR0_ADC1D \
+ $01 constant DIDR0_ADC0D \
+\ ANALOG_COMPARATOR
+&80 constant ACSR \ Analog Comparator Control And Status Register
+ $80 constant ACSR_ACD \ Analog Comparator Disable
+ $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
+ $20 constant ACSR_ACO \ Analog Compare Output
+ $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
+ $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
+ $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
+ $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
+&127 constant DIDR1 \ Digital Input Disable Register 1
+ $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
+ $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
+\ PORTB
+&37 constant PORTB \ Port B Data Register
+&36 constant DDRB \ Port B Data Direction Register
+&35 constant PINB \ Port B Input Pins
+\ PORTC
+&40 constant PORTC \ Port C Data Register
+&39 constant DDRC \ Port C Data Direction Register
+&38 constant PINC \ Port C Input Pins
+\ PORTD
+&43 constant PORTD \ Port D Data Register
+&42 constant DDRD \ Port D Data Direction Register
+&41 constant PIND \ Port D Input Pins
+\ TIMER_COUNTER_0
+&72 constant OCR0B \ Timer/Counter0 Output Compare Register
+&71 constant OCR0A \ Timer/Counter0 Output Compare Register
+&70 constant TCNT0 \ Timer/Counter0
+&69 constant TCCR0B \ Timer/Counter Control Register B
+ $80 constant TCCR0B_FOC0A \ Force Output Compare A
+ $40 constant TCCR0B_FOC0B \ Force Output Compare B
+ $08 constant TCCR0B_WGM02 \
+ $07 constant TCCR0B_CS0 \ Clock Select
+&68 constant TCCR0A \ Timer/Counter Control Register A
+ $C0 constant TCCR0A_COM0A \ Compare Output Mode, Phase Correct PWM Mode
+ $30 constant TCCR0A_COM0B \ Compare Output Mode, Fast PWm
+ $03 constant TCCR0A_WGM0 \ Waveform Generation Mode
+&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
+ $04 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare Match B Interrupt Enable
+ $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match A Interrupt Enable
+ $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
+&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
+ $04 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare Flag 0B
+ $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0A
+ $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
+\ EXTERNAL_INTERRUPT
+&105 constant EICRA \ External Interrupt Control Register
+ $0C constant EICRA_ISC1 \ External Interrupt Sense Control 1 Bits
+ $03 constant EICRA_ISC0 \ External Interrupt Sense Control 0 Bits
+&61 constant EIMSK \ External Interrupt Mask Register
+ $03 constant EIMSK_INT \ External Interrupt Request 1 Enable
+&60 constant EIFR \ External Interrupt Flag Register
+ $03 constant EIFR_INTF \ External Interrupt Flags
+&104 constant PCICR \ Pin Change Interrupt Control Register
+ $07 constant PCICR_PCIE \ Pin Change Interrupt Enables
+&109 constant PCMSK2 \ Pin Change Mask Register 2
+ $FF constant PCMSK2_PCINT \ Pin Change Enable Masks
+&108 constant PCMSK1 \ Pin Change Mask Register 1
+ $7F constant PCMSK1_PCINT \ Pin Change Enable Masks
+&107 constant PCMSK0 \ Pin Change Mask Register 0
+ $FF constant PCMSK0_PCINT \ Pin Change Enable Masks
+&59 constant PCIFR \ Pin Change Interrupt Flag Register
+ $07 constant PCIFR_PCIF \ Pin Change Interrupt Flags
+\ SPI
+&78 constant SPDR \ SPI Data Register
+&77 constant SPSR \ SPI Status Register
+ $80 constant SPSR_SPIF \ SPI Interrupt Flag
+ $40 constant SPSR_WCOL \ Write Collision Flag
+ $01 constant SPSR_SPI2X \ Double SPI Speed Bit
+&76 constant SPCR \ SPI Control Register
+ $80 constant SPCR_SPIE \ SPI Interrupt Enable
+ $40 constant SPCR_SPE \ SPI Enable
+ $20 constant SPCR_DORD \ Data Order
+ $10 constant SPCR_MSTR \ Master/Slave Select
+ $08 constant SPCR_CPOL \ Clock polarity
+ $04 constant SPCR_CPHA \ Clock Phase
+ $03 constant SPCR_SPR \ SPI Clock Rate Selects
+\ WATCHDOG
+&96 constant WDTCSR \ Watchdog Timer Control Register
+ $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Flag
+ $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Enable
+ $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
+ $10 constant WDTCSR_WDCE \ Watchdog Change Enable
+ $08 constant WDTCSR_WDE \ Watch Dog Enable
+\ EEPROM
+&65 constant EEAR \ EEPROM Address Register Bytes
+&64 constant EEDR \ EEPROM Data Register
+&63 constant EECR \ EEPROM Control Register
+ $30 constant EECR_EEPM \ EEPROM Programming Mode Bits
+ $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
+ $04 constant EECR_EEMPE \ EEPROM Master Write Enable
+ $02 constant EECR_EEPE \ EEPROM Write Enable
+ $01 constant EECR_EERE \ EEPROM Read Enable
+\ CPU
+&100 constant PRR \ Power Reduction Register
+ $80 constant PRR_PRTWI \ Power Reduction TWI
+ $40 constant PRR_PRTIM2 \ Power Reduction Timer/Counter2
+ $20 constant PRR_PRTIM0 \ Power Reduction Timer/Counter0
+ $08 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
+ $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
+ $02 constant PRR_PRUSART0 \ Power Reduction USART
+ $01 constant PRR_PRADC \ Power Reduction ADC
+&102 constant OSCCAL \ Oscillator Calibration Value
+&97 constant CLKPR \ Clock Prescale Register
+ $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable
+ $0F constant CLKPR_CLKPS \ Clock Prescaler Select Bits
+&95 constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ $08 constant SREG_V \ Two's Complement Overflow Flag
+ $04 constant SREG_N \ Negative Flag
+ $02 constant SREG_Z \ Zero Flag
+ $01 constant SREG_C \ Carry Flag
+&93 constant SP \ Stack Pointer
+&87 constant SPMCSR \ Store Program Memory Control and Status Register
+ $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCSR_RWWSB \ Read-While-Write Section Busy
+ $10 constant SPMCSR_RWWSRE \ Read-While-Write section read enable
+ $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
+ $04 constant SPMCSR_PGWRT \ Page Write
+ $02 constant SPMCSR_PGERS \ Page Erase
+ $01 constant SPMCSR_SELFPRGEN \ Self Programming Enable
+&85 constant MCUCR \ MCU Control Register
+ $40 constant MCUCR_BODS \ BOD Sleep
+ $20 constant MCUCR_BODSE \ BOD Sleep Enable
+ $10 constant MCUCR_PUD \
+ $02 constant MCUCR_IVSEL \
+ $01 constant MCUCR_IVCE \
+&84 constant MCUSR \ MCU Status Register
+ $08 constant MCUSR_WDRF \ Watchdog Reset Flag
+ $04 constant MCUSR_BORF \ Brown-out Reset Flag
+ $02 constant MCUSR_EXTRF \ External Reset Flag
+ $01 constant MCUSR_PORF \ Power-on reset flag
+&83 constant SMCR \ Sleep Mode Control Register
+ $0E constant SMCR_SM \ Sleep Mode Select Bits
+ $01 constant SMCR_SE \ Sleep Enable
+&75 constant GPIOR2 \ General Purpose I/O Register 2
+&74 constant GPIOR1 \ General Purpose I/O Register 1
+&62 constant GPIOR0 \ General Purpose I/O Register 0
+
+\ Interrupts
+&2 constant INT0Addr \ External Interrupt Request 0
+&4 constant INT1Addr \ External Interrupt Request 1
+&6 constant PCINT0Addr \ Pin Change Interrupt Request 0
+&8 constant PCINT1Addr \ Pin Change Interrupt Request 0
+&10 constant PCINT2Addr \ Pin Change Interrupt Request 1
+&12 constant WDTAddr \ Watchdog Time-out Interrupt
+&14 constant TIMER2_COMPAAddr \ Timer/Counter2 Compare Match A
+&16 constant TIMER2_COMPBAddr \ Timer/Counter2 Compare Match A
+&18 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
+&20 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+&22 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
+&24 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
+&26 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+&28 constant TIMER0_COMPAAddr \ TimerCounter0 Compare Match A
+&30 constant TIMER0_COMPBAddr \ TimerCounter0 Compare Match B
+&32 constant TIMER0_OVFAddr \ Timer/Couner0 Overflow
+&34 constant SPI__STCAddr \ SPI Serial Transfer Complete
+&36 constant USART__RXAddr \ USART Rx Complete
+&38 constant USART__UDREAddr \ USART, Data Register Empty
+&40 constant USART__TXAddr \ USART Tx Complete
+&42 constant ADCAddr \ ADC Conversion Complete
+&44 constant EE_READYAddr \ EEPROM Ready
+&46 constant ANALOG_COMPAddr \ Analog Comparator
+&48 constant TWIAddr \ Two-wire Serial Interface
+&50 constant SPM_ReadyAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/atmega168pa/device.asm b/amforth-6.5/avr8/devices/atmega168pa/device.asm
new file mode 100644
index 0000000..2b9e346
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega168pa/device.asm
@@ -0,0 +1,107 @@
+; Partname: ATmega168PA
+; generated automatically, do not edit
+
+.nolist
+ .include "m168PAdef.inc"
+.list
+
+.equ ramstart = 256
+.equ CELLSIZE = 2
+.macro readflashcell
+ lsl zl
+ rol zh
+ lpm @0, Z+
+ lpm @1, Z+
+.endmacro
+.macro writeflashcell
+ lsl zl
+ rol zh
+.endmacro
+.set WANT_USART0 = 0
+.set WANT_TWI = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_TIMER_COUNTER_2 = 0
+.set WANT_AD_CONVERTER = 0
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_PORTB = 0
+.set WANT_PORTC = 0
+.set WANT_PORTD = 0
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_SPI = 0
+.set WANT_WATCHDOG = 0
+.set WANT_EEPROM = 0
+.set WANT_CPU = 0
+.equ intvecsize = 2 ; please verify; flash size: 16384 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.org 2
+ rcall isr ; External Interrupt Request 0
+.org 4
+ rcall isr ; External Interrupt Request 1
+.org 6
+ rcall isr ; Pin Change Interrupt Request 0
+.org 8
+ rcall isr ; Pin Change Interrupt Request 0
+.org 10
+ rcall isr ; Pin Change Interrupt Request 1
+.org 12
+ rcall isr ; Watchdog Time-out Interrupt
+.org 14
+ rcall isr ; Timer/Counter2 Compare Match A
+.org 16
+ rcall isr ; Timer/Counter2 Compare Match A
+.org 18
+ rcall isr ; Timer/Counter2 Overflow
+.org 20
+ rcall isr ; Timer/Counter1 Capture Event
+.org 22
+ rcall isr ; Timer/Counter1 Compare Match A
+.org 24
+ rcall isr ; Timer/Counter1 Compare Match B
+.org 26
+ rcall isr ; Timer/Counter1 Overflow
+.org 28
+ rcall isr ; TimerCounter0 Compare Match A
+.org 30
+ rcall isr ; TimerCounter0 Compare Match B
+.org 32
+ rcall isr ; Timer/Couner0 Overflow
+.org 34
+ rcall isr ; SPI Serial Transfer Complete
+.org 36
+ rcall isr ; USART Rx Complete
+.org 38
+ rcall isr ; USART, Data Register Empty
+.org 40
+ rcall isr ; USART Tx Complete
+.org 42
+ rcall isr ; ADC Conversion Complete
+.org 44
+ rcall isr ; EEPROM Ready
+.org 46
+ rcall isr ; Analog Comparator
+.org 48
+ rcall isr ; Two-wire Serial Interface
+.org 50
+ rcall isr ; Store Program Memory Read
+.equ INTVECTORS = 26
+.nooverlap
+
+; compatability layer (maybe empty)
+.equ SPMEN = SELFPRGEN
+
+; controller data area, environment query mcu-info
+mcu_info:
+mcu_ramsize:
+ .dw 1024
+mcu_eepromsize:
+ .dw 512
+mcu_maxdp:
+ .dw 14336
+mcu_numints:
+ .dw 26
+mcu_name:
+ .dw 11
+ .db "ATmega168PA",0
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega168pa/device.inc b/amforth-6.5/avr8/devices/atmega168pa/device.inc
new file mode 100644
index 0000000..dc2ad5b
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega168pa/device.inc
@@ -0,0 +1,996 @@
+; Partname: ATmega168PA
+; generated automatically, no not edit
+
+.if WANT_USART0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR0:
+ .dw $ff04
+ .db "UDR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR0
+XT_UDR0:
+ .dw PFA_DOVARIABLE
+PFA_UDR0:
+ .dw 198
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR0A:
+ .dw $ff06
+ .db "UCSR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0A
+XT_UCSR0A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0A:
+ .dw 192
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR0B:
+ .dw $ff06
+ .db "UCSR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0B
+XT_UCSR0B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0B:
+ .dw 193
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR0C:
+ .dw $ff06
+ .db "UCSR0C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0C
+XT_UCSR0C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0C:
+ .dw 194
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Bytes
+VE_UBRR0:
+ .dw $ff05
+ .db "UBRR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR0
+XT_UBRR0:
+ .dw PFA_DOVARIABLE
+PFA_UBRR0:
+ .dw 196
+
+.endif
+.if WANT_TWI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; TWI (Slave) Address Mask Register
+VE_TWAMR:
+ .dw $ff05
+ .db "TWAMR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWAMR
+XT_TWAMR:
+ .dw PFA_DOVARIABLE
+PFA_TWAMR:
+ .dw 189
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Bit Rate register
+VE_TWBR:
+ .dw $ff04
+ .db "TWBR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWBR
+XT_TWBR:
+ .dw PFA_DOVARIABLE
+PFA_TWBR:
+ .dw 184
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Control Register
+VE_TWCR:
+ .dw $ff04
+ .db "TWCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWCR
+XT_TWCR:
+ .dw PFA_DOVARIABLE
+PFA_TWCR:
+ .dw 188
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Status Register
+VE_TWSR:
+ .dw $ff04
+ .db "TWSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWSR
+XT_TWSR:
+ .dw PFA_DOVARIABLE
+PFA_TWSR:
+ .dw 185
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Data register
+VE_TWDR:
+ .dw $ff04
+ .db "TWDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWDR
+XT_TWDR:
+ .dw PFA_DOVARIABLE
+PFA_TWDR:
+ .dw 187
+; ( -- addr ) System Constant
+; R( -- )
+; TWI (Slave) Address register
+VE_TWAR:
+ .dw $ff04
+ .db "TWAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWAR
+XT_TWAR:
+ .dw PFA_DOVARIABLE
+PFA_TWAR:
+ .dw 186
+
+.endif
+.if WANT_TIMER_COUNTER_1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Mask Register
+VE_TIMSK1:
+ .dw $ff06
+ .db "TIMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK1
+XT_TIMSK1:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK1:
+ .dw 111
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Flag register
+VE_TIFR1:
+ .dw $ff05
+ .db "TIFR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR1
+XT_TIFR1:
+ .dw PFA_DOVARIABLE
+PFA_TIFR1:
+ .dw 54
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw 128
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw 129
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register C
+VE_TCCR1C:
+ .dw $ff06
+ .db "TCCR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1C
+XT_TCCR1C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1C:
+ .dw 130
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Bytes
+VE_TCNT1:
+ .dw $ff05
+ .db "TCNT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1
+XT_TCNT1:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1:
+ .dw 132
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register Bytes
+VE_OCR1A:
+ .dw $ff05
+ .db "OCR1A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1A
+XT_OCR1A:
+ .dw PFA_DOVARIABLE
+PFA_OCR1A:
+ .dw 136
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register Bytes
+VE_OCR1B:
+ .dw $ff05
+ .db "OCR1B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1B
+XT_OCR1B:
+ .dw PFA_DOVARIABLE
+PFA_OCR1B:
+ .dw 138
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Bytes
+VE_ICR1:
+ .dw $ff04
+ .db "ICR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1
+XT_ICR1:
+ .dw PFA_DOVARIABLE
+PFA_ICR1:
+ .dw 134
+; ( -- addr ) System Constant
+; R( -- )
+; General Timer/Counter Control Register
+VE_GTCCR:
+ .dw $ff05
+ .db "GTCCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GTCCR
+XT_GTCCR:
+ .dw PFA_DOVARIABLE
+PFA_GTCCR:
+ .dw 67
+
+.endif
+.if WANT_TIMER_COUNTER_2 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Mask register
+VE_TIMSK2:
+ .dw $ff06
+ .db "TIMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK2
+XT_TIMSK2:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK2:
+ .dw 112
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Flag Register
+VE_TIFR2:
+ .dw $ff05
+ .db "TIFR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR2
+XT_TIFR2:
+ .dw PFA_DOVARIABLE
+PFA_TIFR2:
+ .dw 55
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register A
+VE_TCCR2A:
+ .dw $ff06
+ .db "TCCR2A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2A
+XT_TCCR2A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2A:
+ .dw 176
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register B
+VE_TCCR2B:
+ .dw $ff06
+ .db "TCCR2B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2B
+XT_TCCR2B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2B:
+ .dw 177
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2
+VE_TCNT2:
+ .dw $ff05
+ .db "TCNT2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT2
+XT_TCNT2:
+ .dw PFA_DOVARIABLE
+PFA_TCNT2:
+ .dw 178
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register B
+VE_OCR2B:
+ .dw $ff05
+ .db "OCR2B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2B
+XT_OCR2B:
+ .dw PFA_DOVARIABLE
+PFA_OCR2B:
+ .dw 180
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register A
+VE_OCR2A:
+ .dw $ff05
+ .db "OCR2A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2A
+XT_OCR2A:
+ .dw PFA_DOVARIABLE
+PFA_OCR2A:
+ .dw 179
+; ( -- addr ) System Constant
+; R( -- )
+; Asynchronous Status Register
+VE_ASSR:
+ .dw $ff04
+ .db "ASSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ASSR
+XT_ASSR:
+ .dw PFA_DOVARIABLE
+PFA_ASSR:
+ .dw 182
+
+.endif
+.if WANT_AD_CONVERTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC multiplexer Selection Register
+VE_ADMUX:
+ .dw $ff05
+ .db "ADMUX",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADMUX
+XT_ADMUX:
+ .dw PFA_DOVARIABLE
+PFA_ADMUX:
+ .dw 124
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register Bytes
+VE_ADC:
+ .dw $ff03
+ .db "ADC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADC
+XT_ADC:
+ .dw PFA_DOVARIABLE
+PFA_ADC:
+ .dw 120
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register A
+VE_ADCSRA:
+ .dw $ff06
+ .db "ADCSRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRA
+XT_ADCSRA:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRA:
+ .dw 122
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register B
+VE_ADCSRB:
+ .dw $ff06
+ .db "ADCSRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRB
+XT_ADCSRB:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRB:
+ .dw 123
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register
+VE_DIDR0:
+ .dw $ff05
+ .db "DIDR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR0
+XT_DIDR0:
+ .dw PFA_DOVARIABLE
+PFA_DIDR0:
+ .dw 126
+
+.endif
+.if WANT_ANALOG_COMPARATOR == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Control And Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw 80
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 1
+VE_DIDR1:
+ .dw $ff05
+ .db "DIDR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR1
+XT_DIDR1:
+ .dw PFA_DOVARIABLE
+PFA_DIDR1:
+ .dw 127
+
+.endif
+.if WANT_PORTB == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw 37
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw 36
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw 35
+
+.endif
+.if WANT_PORTC == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Register
+VE_PORTC:
+ .dw $ff05
+ .db "PORTC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTC
+XT_PORTC:
+ .dw PFA_DOVARIABLE
+PFA_PORTC:
+ .dw 40
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Direction Register
+VE_DDRC:
+ .dw $ff04
+ .db "DDRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRC
+XT_DDRC:
+ .dw PFA_DOVARIABLE
+PFA_DDRC:
+ .dw 39
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Input Pins
+VE_PINC:
+ .dw $ff04
+ .db "PINC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINC
+XT_PINC:
+ .dw PFA_DOVARIABLE
+PFA_PINC:
+ .dw 38
+
+.endif
+.if WANT_PORTD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw 43
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw 42
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw 41
+
+.endif
+.if WANT_TIMER_COUNTER_0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0B:
+ .dw $ff05
+ .db "OCR0B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0B
+XT_OCR0B:
+ .dw PFA_DOVARIABLE
+PFA_OCR0B:
+ .dw 72
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0A:
+ .dw $ff05
+ .db "OCR0A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0A
+XT_OCR0A:
+ .dw PFA_DOVARIABLE
+PFA_OCR0A:
+ .dw 71
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw 70
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register B
+VE_TCCR0B:
+ .dw $ff06
+ .db "TCCR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0B
+XT_TCCR0B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0B:
+ .dw 69
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register A
+VE_TCCR0A:
+ .dw $ff06
+ .db "TCCR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0A
+XT_TCCR0A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0A:
+ .dw 68
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Mask Register
+VE_TIMSK0:
+ .dw $ff06
+ .db "TIMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK0
+XT_TIMSK0:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK0:
+ .dw 110
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Flag register
+VE_TIFR0:
+ .dw $ff05
+ .db "TIFR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR0
+XT_TIFR0:
+ .dw PFA_DOVARIABLE
+PFA_TIFR0:
+ .dw 53
+
+.endif
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register
+VE_EICRA:
+ .dw $ff05
+ .db "EICRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRA
+XT_EICRA:
+ .dw PFA_DOVARIABLE
+PFA_EICRA:
+ .dw 105
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Mask Register
+VE_EIMSK:
+ .dw $ff05
+ .db "EIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIMSK
+XT_EIMSK:
+ .dw PFA_DOVARIABLE
+PFA_EIMSK:
+ .dw 61
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Flag Register
+VE_EIFR:
+ .dw $ff04
+ .db "EIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIFR
+XT_EIFR:
+ .dw PFA_DOVARIABLE
+PFA_EIFR:
+ .dw 60
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Interrupt Control Register
+VE_PCICR:
+ .dw $ff05
+ .db "PCICR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCICR
+XT_PCICR:
+ .dw PFA_DOVARIABLE
+PFA_PCICR:
+ .dw 104
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 2
+VE_PCMSK2:
+ .dw $ff06
+ .db "PCMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK2
+XT_PCMSK2:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK2:
+ .dw 109
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 1
+VE_PCMSK1:
+ .dw $ff06
+ .db "PCMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK1
+XT_PCMSK1:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK1:
+ .dw 108
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 0
+VE_PCMSK0:
+ .dw $ff06
+ .db "PCMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK0
+XT_PCMSK0:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK0:
+ .dw 107
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Interrupt Flag Register
+VE_PCIFR:
+ .dw $ff05
+ .db "PCIFR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCIFR
+XT_PCIFR:
+ .dw PFA_DOVARIABLE
+PFA_PCIFR:
+ .dw 59
+
+.endif
+.if WANT_SPI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR:
+ .dw $ff04
+ .db "SPDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR
+XT_SPDR:
+ .dw PFA_DOVARIABLE
+PFA_SPDR:
+ .dw 78
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR:
+ .dw $ff04
+ .db "SPSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR
+XT_SPSR:
+ .dw PFA_DOVARIABLE
+PFA_SPSR:
+ .dw 77
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR:
+ .dw $ff04
+ .db "SPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR
+XT_SPCR:
+ .dw PFA_DOVARIABLE
+PFA_SPCR:
+ .dw 76
+
+.endif
+.if WANT_WATCHDOG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCSR:
+ .dw $ff06
+ .db "WDTCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCSR
+XT_WDTCSR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCSR:
+ .dw 96
+
+.endif
+.if WANT_EEPROM == 1
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Address Register Bytes
+VE_EEAR:
+ .dw $ff04
+ .db "EEAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEAR
+XT_EEAR:
+ .dw PFA_DOVARIABLE
+PFA_EEAR:
+ .dw 65
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw 64
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw 63
+
+.endif
+.if WANT_CPU == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register
+VE_PRR:
+ .dw $ff03
+ .db "PRR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR
+XT_PRR:
+ .dw PFA_DOVARIABLE
+PFA_PRR:
+ .dw 100
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Calibration Value
+VE_OSCCAL:
+ .dw $ff06
+ .db "OSCCAL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSCCAL
+XT_OSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_OSCCAL:
+ .dw 102
+; ( -- addr ) System Constant
+; R( -- )
+; Clock Prescale Register
+VE_CLKPR:
+ .dw $ff05
+ .db "CLKPR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKPR
+XT_CLKPR:
+ .dw PFA_DOVARIABLE
+PFA_CLKPR:
+ .dw 97
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw 95
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer
+VE_SP:
+ .dw $ff02
+ .db "SP"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SP
+XT_SP:
+ .dw PFA_DOVARIABLE
+PFA_SP:
+ .dw 93
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control and Status Register
+VE_SPMCSR:
+ .dw $ff06
+ .db "SPMCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCSR
+XT_SPMCSR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCSR:
+ .dw 87
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw 85
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Status Register
+VE_MCUSR:
+ .dw $ff05
+ .db "MCUSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUSR
+XT_MCUSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUSR:
+ .dw 84
+; ( -- addr ) System Constant
+; R( -- )
+; Sleep Mode Control Register
+VE_SMCR:
+ .dw $ff04
+ .db "SMCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SMCR
+XT_SMCR:
+ .dw PFA_DOVARIABLE
+PFA_SMCR:
+ .dw 83
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose I/O Register 2
+VE_GPIOR2:
+ .dw $ff06
+ .db "GPIOR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR2
+XT_GPIOR2:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR2:
+ .dw 75
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose I/O Register 1
+VE_GPIOR1:
+ .dw $ff06
+ .db "GPIOR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR1
+XT_GPIOR1:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR1:
+ .dw 74
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose I/O Register 0
+VE_GPIOR0:
+ .dw $ff06
+ .db "GPIOR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR0
+XT_GPIOR0:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR0:
+ .dw 62
+
+.endif
diff --git a/amforth-6.5/avr8/devices/atmega168pa/device.py b/amforth-6.5/avr8/devices/atmega168pa/device.py
new file mode 100644
index 0000000..8001e5c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega168pa/device.py
@@ -0,0 +1,324 @@
+# Generated Automatically
+
+# Partname ATmega168PA
+
+MCUREGS = {
+# Interrupt Vectors
+ 'INT0Addr' : '#2', # External Interrupt Request 0
+ 'INT1Addr' : '#4', # External Interrupt Request 1
+ 'PCINT0Addr' : '#6', # Pin Change Interrupt Request 0
+ 'PCINT1Addr' : '#8', # Pin Change Interrupt Request 0
+ 'PCINT2Addr' : '#10', # Pin Change Interrupt Request 1
+ 'WDTAddr' : '#12', # Watchdog Time-out Interrupt
+ 'TIMER2_COMPAAddr' : '#14', # Timer/Counter2 Compare Match A
+ 'TIMER2_COMPBAddr' : '#16', # Timer/Counter2 Compare Match A
+ 'TIMER2_OVFAddr' : '#18', # Timer/Counter2 Overflow
+ 'TIMER1_CAPTAddr' : '#20', # Timer/Counter1 Capture Event
+ 'TIMER1_COMPAAddr' : '#22', # Timer/Counter1 Compare Match A
+ 'TIMER1_COMPBAddr' : '#24', # Timer/Counter1 Compare Match B
+ 'TIMER1_OVFAddr' : '#26', # Timer/Counter1 Overflow
+ 'TIMER0_COMPAAddr' : '#28', # TimerCounter0 Compare Match A
+ 'TIMER0_COMPBAddr' : '#30', # TimerCounter0 Compare Match B
+ 'TIMER0_OVFAddr' : '#32', # Timer/Couner0 Overflow
+ 'SPI_STCAddr' : '#34', # SPI Serial Transfer Complete
+ 'USART_RXAddr' : '#36', # USART Rx Complete
+ 'USART_UDREAddr' : '#38', # USART, Data Register Empty
+ 'USART_TXAddr' : '#40', # USART Tx Complete
+ 'ADCAddr' : '#42', # ADC Conversion Complete
+ 'EE_READYAddr' : '#44', # EEPROM Ready
+ 'ANALOG_COMPAddr' : '#46', # Analog Comparator
+ 'TWIAddr' : '#48', # Two-wire Serial Interface
+ 'SPM_ReadyAddr' : '#50', # Store Program Memory Read
+
+# Module USART0
+ 'UDR0' : '$c6', # USART I/O Data Register
+ 'UCSR0A' : '$c0', # USART Control and Status Regis
+ 'UCSR0A_RXC0': '$80', # USART Receive Complete
+ 'UCSR0A_TXC0': '$40', # USART Transmitt Complete
+ 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
+ 'UCSR0A_FE0': '$10', # Framing Error
+ 'UCSR0A_DOR0': '$8', # Data overRun
+ 'UCSR0A_UPE0': '$4', # Parity Error
+ 'UCSR0A_U2X0': '$2', # Double the USART transmission
+ 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
+ 'UCSR0B' : '$c1', # USART Control and Status Regis
+ 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
+ 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
+ 'UCSR0B_UDRIE0': '$20', # USART Data register Empty Inte
+ 'UCSR0B_RXEN0': '$10', # Receiver Enable
+ 'UCSR0B_TXEN0': '$8', # Transmitter Enable
+ 'UCSR0B_UCSZ02': '$4', # Character Size
+ 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
+ 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
+ 'UCSR0C' : '$c2', # USART Control and Status Regis
+ 'UCSR0C_UMSEL0': '$c0', # USART Mode Select
+ 'UCSR0C_UPM0': '$30', # Parity Mode Bits
+ 'UCSR0C_USBS0': '$8', # Stop Bit Select
+ 'UCSR0C_UCSZ0': '$6', # Character Size
+ 'UCSR0C_UCPOL0': '$1', # Clock Polarity
+ 'UBRR0' : '$c4', # USART Baud Rate Register Byte
+
+# Module TWI
+ 'TWAMR' : '$bd', # TWI (Slave) Address Mask Regis
+ 'TWAMR_TWAM': '$fe', #
+ 'TWBR' : '$b8', # TWI Bit Rate register
+ 'TWCR' : '$bc', # TWI Control Register
+ 'TWCR_TWINT': '$80', # TWI Interrupt Flag
+ 'TWCR_TWEA': '$40', # TWI Enable Acknowledge Bit
+ 'TWCR_TWSTA': '$20', # TWI Start Condition Bit
+ 'TWCR_TWSTO': '$10', # TWI Stop Condition Bit
+ 'TWCR_TWWC': '$8', # TWI Write Collition Flag
+ 'TWCR_TWEN': '$4', # TWI Enable Bit
+ 'TWCR_TWIE': '$1', # TWI Interrupt Enable
+ 'TWSR' : '$b9', # TWI Status Register
+ 'TWSR_TWS': '$f8', # TWI Status
+ 'TWSR_TWPS': '$3', # TWI Prescaler
+ 'TWDR' : '$bb', # TWI Data register
+ 'TWAR' : '$ba', # TWI (Slave) Address register
+ 'TWAR_TWA': '$fe', # TWI (Slave) Address register B
+ 'TWAR_TWGCE': '$1', # TWI General Call Recognition E
+
+# Module TIMER_COUNTER_1
+ 'TIMSK1' : '$6f', # Timer/Counter Interrupt Mask R
+ 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
+ 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output CompareB
+ 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output CompareA
+ 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
+ 'TIFR1' : '$36', # Timer/Counter Interrupt Flag r
+ 'TIFR1_ICF1': '$20', # Input Capture Flag 1
+ 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
+ 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
+ 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
+ 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
+ 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
+ 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
+ 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
+ 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
+ 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
+ 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
+ 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
+ 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
+ 'TCCR1C' : '$82', # Timer/Counter1 Control Registe
+ 'TCCR1C_FOC1A': '$80', #
+ 'TCCR1C_FOC1B': '$40', #
+ 'TCNT1' : '$84', # Timer/Counter1 Bytes
+ 'OCR1A' : '$88', # Timer/Counter1 Output Compare
+ 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
+ 'ICR1' : '$86', # Timer/Counter1 Input Capture R
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSRSYNC': '$1', # Prescaler Reset Timer/Counter1
+
+# Module TIMER_COUNTER_2
+ 'TIMSK2' : '$70', # Timer/Counter Interrupt Mask r
+ 'TIMSK2_OCIE2B': '$4', # Timer/Counter2 Output Compare
+ 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
+ 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
+ 'TIFR2' : '$37', # Timer/Counter Interrupt Flag R
+ 'TIFR2_OCF2B': '$4', # Output Compare Flag 2B
+ 'TIFR2_OCF2A': '$2', # Output Compare Flag 2A
+ 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
+ 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
+ 'TCCR2A_COM2A': '$c0', # Compare Output Mode bits
+ 'TCCR2A_COM2B': '$30', # Compare Output Mode bits
+ 'TCCR2A_WGM2': '$3', # Waveform Genration Mode
+ 'TCCR2B' : '$b1', # Timer/Counter2 Control Registe
+ 'TCCR2B_FOC2A': '$80', # Force Output Compare A
+ 'TCCR2B_FOC2B': '$40', # Force Output Compare B
+ 'TCCR2B_WGM22': '$8', # Waveform Generation Mode
+ 'TCCR2B_CS2': '$7', # Clock Select bits
+ 'TCNT2' : '$b2', # Timer/Counter2
+ 'OCR2B' : '$b4', # Timer/Counter2 Output Compare
+ 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
+ 'ASSR' : '$b6', # Asynchronous Status Register
+ 'ASSR_EXCLK': '$40', # Enable External Clock Input
+ 'ASSR_AS2': '$20', # Asynchronous Timer/Counter2
+ 'ASSR_TCN2UB': '$10', # Timer/Counter2 Update Busy
+ 'ASSR_OCR2AUB': '$8', # Output Compare Register2 Updat
+ 'ASSR_OCR2BUB': '$4', # Output Compare Register 2 Upda
+ 'ASSR_TCR2AUB': '$2', # Timer/Counter Control Register
+ 'ASSR_TCR2BUB': '$1', # Timer/Counter Control Register
+ 'GTCCR' : '$43', # General Timer Counter Control
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSRASY': '$2', # Prescaler Reset Timer/Counter2
+
+# Module AD_CONVERTER
+ 'ADMUX' : '$7c', # The ADC multiplexer Selection
+ 'ADMUX_REFS': '$c0', # Reference Selection Bits
+ 'ADMUX_ADLAR': '$20', # Left Adjust Result
+ 'ADMUX_MUX': '$f', # Analog Channel and Gain Select
+ 'ADC' : '$78', # ADC Data Register Bytes
+ 'ADCSRA' : '$7a', # The ADC Control and Status reg
+ 'ADCSRA_ADEN': '$80', # ADC Enable
+ 'ADCSRA_ADSC': '$40', # ADC Start Conversion
+ 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
+ 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
+ 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
+ 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
+ 'ADCSRB' : '$7b', # The ADC Control and Status reg
+ 'ADCSRB_ACME': '$40', #
+ 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Source bits
+ 'DIDR0' : '$7e', # Digital Input Disable Register
+ 'DIDR0_ADC5D': '$20', #
+ 'DIDR0_ADC4D': '$10', #
+ 'DIDR0_ADC3D': '$8', #
+ 'DIDR0_ADC2D': '$4', #
+ 'DIDR0_ADC1D': '$2', #
+ 'DIDR0_ADC0D': '$1', #
+
+# Module ANALOG_COMPARATOR
+ 'ACSR' : '$50', # Analog Comparator Control And
+ 'ACSR_ACD': '$80', # Analog Comparator Disable
+ 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
+ 'ACSR_ACO': '$20', # Analog Compare Output
+ 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
+ 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
+ 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
+ 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
+ 'DIDR1' : '$7f', # Digital Input Disable Register
+ 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
+ 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
+
+# Module PORTB
+ 'PORTB' : '$25', # Port B Data Register
+ 'DDRB' : '$24', # Port B Data Direction Register
+ 'PINB' : '$23', # Port B Input Pins
+
+# Module PORTC
+ 'PORTC' : '$28', # Port C Data Register
+ 'DDRC' : '$27', # Port C Data Direction Register
+ 'PINC' : '$26', # Port C Input Pins
+
+# Module PORTD
+ 'PORTD' : '$2b', # Port D Data Register
+ 'DDRD' : '$2a', # Port D Data Direction Register
+ 'PIND' : '$29', # Port D Input Pins
+
+# Module TIMER_COUNTER_0
+ 'OCR0B' : '$48', # Timer/Counter0 Output Compare
+ 'OCR0A' : '$47', # Timer/Counter0 Output Compare
+ 'TCNT0' : '$46', # Timer/Counter0
+ 'TCCR0B' : '$45', # Timer/Counter Control Register
+ 'TCCR0B_FOC0A': '$80', # Force Output Compare A
+ 'TCCR0B_FOC0B': '$40', # Force Output Compare B
+ 'TCCR0B_WGM02': '$8', #
+ 'TCCR0B_CS0': '$7', # Clock Select
+ 'TCCR0A' : '$44', # Timer/Counter Control Registe
+ 'TCCR0A_COM0A': '$c0', # Compare Output Mode, Phase Cor
+ 'TCCR0A_COM0B': '$30', # Compare Output Mode, Fast PWm
+ 'TCCR0A_WGM0': '$3', # Waveform Generation Mode
+ 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
+ 'TIMSK0_OCIE0B': '$4', # Timer/Counter0 Output Compare
+ 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
+ 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
+ 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
+ 'TIFR0_OCF0B': '$4', # Timer/Counter0 Output Compare
+ 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
+ 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSRSYNC': '$1', # Prescaler Reset Timer/Counter1
+
+# Module EXTERNAL_INTERRUPT
+ 'EICRA' : '$69', # External Interrupt Control Reg
+ 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
+ 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
+ 'EIMSK' : '$3d', # External Interrupt Mask Regist
+ 'EIMSK_INT': '$3', # External Interrupt Request 1 E
+ 'EIFR' : '$3c', # External Interrupt Flag Regist
+ 'EIFR_INTF': '$3', # External Interrupt Flags
+ 'PCICR' : '$68', # Pin Change Interrupt Control R
+ 'PCICR_PCIE': '$7', # Pin Change Interrupt Enables
+ 'PCMSK2' : '$6d', # Pin Change Mask Register 2
+ 'PCMSK2_PCINT': '$ff', # Pin Change Enable Masks
+ 'PCMSK1' : '$6c', # Pin Change Mask Register 1
+ 'PCMSK1_PCINT': '$7f', # Pin Change Enable Masks
+ 'PCMSK0' : '$6b', # Pin Change Mask Register 0
+ 'PCMSK0_PCINT': '$ff', # Pin Change Enable Masks
+ 'PCIFR' : '$3b', # Pin Change Interrupt Flag Regi
+ 'PCIFR_PCIF': '$7', # Pin Change Interrupt Flags
+
+# Module SPI
+ 'SPDR' : '$4e', # SPI Data Register
+ 'SPSR' : '$4d', # SPI Status Register
+ 'SPSR_SPIF': '$80', # SPI Interrupt Flag
+ 'SPSR_WCOL': '$40', # Write Collision Flag
+ 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
+ 'SPCR' : '$4c', # SPI Control Register
+ 'SPCR_SPIE': '$80', # SPI Interrupt Enable
+ 'SPCR_SPE': '$40', # SPI Enable
+ 'SPCR_DORD': '$20', # Data Order
+ 'SPCR_MSTR': '$10', # Master/Slave Select
+ 'SPCR_CPOL': '$8', # Clock polarity
+ 'SPCR_CPHA': '$4', # Clock Phase
+ 'SPCR_SPR': '$3', # SPI Clock Rate Selects
+
+# Module WATCHDOG
+ 'WDTCSR' : '$60', # Watchdog Timer Control Registe
+ 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
+ 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
+ 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
+ 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
+ 'WDTCSR_WDE': '$8', # Watch Dog Enable
+
+# Module EEPROM
+ 'EEAR' : '$41', # EEPROM Address Register Bytes
+ 'EEDR' : '$40', # EEPROM Data Register
+ 'EECR' : '$3f', # EEPROM Control Register
+ 'EECR_EEPM': '$30', # EEPROM Programming Mode Bits
+ 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
+ 'EECR_EEMPE': '$4', # EEPROM Master Write Enable
+ 'EECR_EEPE': '$2', # EEPROM Write Enable
+ 'EECR_EERE': '$1', # EEPROM Read Enable
+
+# Module CPU
+ 'PRR' : '$64', # Power Reduction Register
+ 'PRR_PRTWI': '$80', # Power Reduction TWI
+ 'PRR_PRTIM2': '$40', # Power Reduction Timer/Counter2
+ 'PRR_PRTIM0': '$20', # Power Reduction Timer/Counter0
+ 'PRR_PRTIM1': '$8', # Power Reduction Timer/Counter1
+ 'PRR_PRSPI': '$4', # Power Reduction Serial Periphe
+ 'PRR_PRUSART0': '$2', # Power Reduction USART
+ 'PRR_PRADC': '$1', # Power Reduction ADC
+ 'OSCCAL' : '$66', # Oscillator Calibration Value
+ 'CLKPR' : '$61', # Clock Prescale Register
+ 'CLKPR_CLKPCE': '$80', # Clock Prescaler Change Enable
+ 'CLKPR_CLKPS': '$f', # Clock Prescaler Select Bits
+ 'SREG' : '$5f', # Status Register
+ 'SREG_I': '$80', # Global Interrupt Enable
+ 'SREG_T': '$40', # Bit Copy Storage
+ 'SREG_H': '$20', # Half Carry Flag
+ 'SREG_S': '$10', # Sign Bit
+ 'SREG_V': '$8', # Two's Complement Overflow Flag
+ 'SREG_N': '$4', # Negative Flag
+ 'SREG_Z': '$2', # Zero Flag
+ 'SREG_C': '$1', # Carry Flag
+ 'SP' : '$5d', # Stack Pointer
+ 'SPMCSR' : '$57', # Store Program Memory Control a
+ 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
+ 'SPMCSR_RWWSB': '$40', # Read-While-Write Section Busy
+ 'SPMCSR_RWWSRE': '$10', # Read-While-Write section read
+ 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
+ 'SPMCSR_PGWRT': '$4', # Page Write
+ 'SPMCSR_PGERS': '$2', # Page Erase
+ 'SPMCSR_SELFPRGEN': '$1', # Self Programming Enable
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_BODS': '$40', # BOD Sleep
+ 'MCUCR_BODSE': '$20', # BOD Sleep Enable
+ 'MCUCR_PUD': '$10', #
+ 'MCUCR_IVSEL': '$2', #
+ 'MCUCR_IVCE': '$1', #
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
+ 'MCUSR_BORF': '$4', # Brown-out Reset Flag
+ 'MCUSR_EXTRF': '$2', # External Reset Flag
+ 'MCUSR_PORF': '$1', # Power-on reset flag
+ 'SMCR' : '$53', # Sleep Mode Control Register
+ 'SMCR_SM': '$e', # Sleep Mode Select Bits
+ 'SMCR_SE': '$1', # Sleep Enable
+ 'GPIOR2' : '$4b', # General Purpose I/O Register 2
+ 'GPIOR1' : '$4a', # General Purpose I/O Register 1
+ 'GPIOR0' : '$3e', # General Purpose I/O Register 0
+
+ '__amforth_dummy':'0'
+}
diff --git a/amforth-6.5/avr8/devices/atmega168pa/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega168pa/words/no-jtag.asm
new file mode 100644
index 0000000..352a4bb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega168pa/words/no-jtag.asm
@@ -0,0 +1,14 @@
+; ( -- )
+; ( -- )
+; MCU
+; disable jtag at runtime
+VE_NOJTAG:
+ .dw $FF05
+ .db "-jtag",0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOJTAG
+XT_NOJTAG:
+ .dw PFA_NOJTAG
+PFA_NOJTAG:
+
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega168pa/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega168pa/words/no-wdt.asm
new file mode 100644
index 0000000..ff6ddd1
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega168pa/words/no-wdt.asm
@@ -0,0 +1,34 @@
+; ( -- )
+; MCU
+; disable watch dog timer at runtime
+VE_NOWDT:
+ .dw $ff04
+ .db "-wdt"
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOWDT
+XT_NOWDT:
+ .dw PFA_NOWDT
+PFA_NOWDT:
+
+ in temp1,SREG
+ push temp1
+ ; Turn always off global interrupt.
+ cli
+ ; Reset Watchdog Timer
+ wdr
+ ; Clear WDRF in MCUSR
+ in temp1, MCUSR
+ andi temp1, (0xff & (0<<WDRF))
+ out MCUSR, temp1
+ ; Write logical one to WDCE and WDE
+ ; Keep old prescaler setting to prevent unintentional time-out
+ in_ temp1, WDTCSR
+ ori temp1, (1<<WDCE) | (1<<WDE)
+ out_ WDTCSR, temp1
+ ; Turn off WDT
+ ldi temp1, (0<<WDE)
+ out_ WDTCSR, temp1
+ ; restore status register
+ pop temp1
+ out SREG,temp1
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega168pa/words/sleep.asm b/amforth-6.5/avr8/devices/atmega168pa/words/sleep.asm
new file mode 100644
index 0000000..256249c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega168pa/words/sleep.asm
@@ -0,0 +1,19 @@
+; ( mode -- )
+; MCU
+; put the controller into the specified sleep mode
+VE_SLEEP:
+ .dw $ff05
+ .db "sleep", 0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_SLEEP
+XT_SLEEP:
+ .dw PFA_SLEEP
+PFA_SLEEP:
+ andi tosl, 7 ; leave only legal mode bits
+ lsl tosl ; move to correct location (bits 3-1)
+ ori tosl, 1 ; set the SE bit
+ out_ SMCR, tosl ; set the sleep config
+ sleep ; nighty-night
+ out_ SMCR, zerol ; 0 protects against accidental sleeps
+ loadtos ; pop argument from stack
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega169/atmega169.frt b/amforth-6.5/avr8/devices/atmega169/atmega169.frt
new file mode 100644
index 0000000..97e7d87
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega169/atmega169.frt
@@ -0,0 +1,183 @@
+\ Partname: ATmega169
+\ Built using part description XML file version 300
+\ generated automatically
+
+hex
+
+\ AD_CONVERTER
+79 constant ADCH \ ADC Data Register High Byte
+78 constant ADCL \ ADC Data Register Low Byte
+7A constant ADCSRA \ The ADC Control and Status register
+7B constant ADCSRB \ ADC Control and Status Register B
+7C constant ADMUX \ The ADC multiplexer Selection Register
+7E constant DIDR0 \ Digital Input Disable Register 0
+
+\ ANALOG_COMPARATOR
+50 constant ACSR \ Analog Comparator Control And Status Register
+7F constant DIDR1 \ Digital Input Disable Register 1
+
+\ BOOT_LOAD
+57 constant SPMCSR \ Store Program Memory Control Register
+
+\ CPU
+61 constant CLKPR \ Clock Prescale Register
+3E constant GPIOR0 \ General Purpose IO Register 0
+4A constant GPIOR1 \ General Purpose IO Register 1
+4B constant GPIOR2 \ General Purpose IO Register 2
+55 constant MCUCR \ MCU Control Register
+54 constant MCUSR \ MCU Status Register
+66 constant OSCCAL \ Oscillator Calibration Value
+64 constant PRR \ Power Reduction Register
+53 constant SMCR \ Sleep Mode Control Register
+5E constant SPH \ Stack Pointer High
+5D constant SPL \ Stack Pointer Low
+5F constant SREG \ Status Register
+
+\ EEPROM
+42 constant EEARH \ EEPROM Address Register High Byte
+41 constant EEARL \ EEPROM Address Register Low Byte
+3F constant EECR \ EEPROM Control Register
+40 constant EEDR \ EEPROM Data Register
+
+\ EXTERNAL_INTERRUPT
+69 constant EICRA \ External Interrupt Control Register
+3C constant EIFR \ External Interrupt Flag Register
+3D constant EIMSK \ External Interrupt Mask Register
+6B constant PCMSK0 \ Pin Change Mask Register 0
+6C constant PCMSK1 \ Pin Change Mask Register 1
+
+\ JTAG
+51 constant OCDR \ On-Chip Debug Related Register in I/O Memory
+
+\ LCD
+E7 constant LCDCCR \ LCD Contrast Control Register
+E4 constant LCDCRA \ LCD Control Register A
+E5 constant LCDCRB \ LCD Control and Status Register B
+EC constant LCDDR0 \ LCD Data Register 0
+ED constant LCDDR1 \ LCD Data Register 1
+F6 constant LCDDR10 \ LCD Data Register 10
+F7 constant LCDDR11 \ LCD Data Register 11
+F8 constant LCDDR12 \ LCD Data Register 12
+F9 constant LCDDR13 \ LCD Data Register 13
+FB constant LCDDR15 \ LCD Data Register 15
+FC constant LCDDR16 \ LCD Data Register 16
+FD constant LCDDR17 \ LCD Data Register 17
+FE constant LCDDR18 \ LCD Data Register 18
+EE constant LCDDR2 \ LCD Data Register 2
+EF constant LCDDR3 \ LCD Data Register 3
+F1 constant LCDDR5 \ LCD Data Register 5
+F2 constant LCDDR6 \ LCD Data Register 6
+F3 constant LCDDR7 \ LCD Data Register 7
+F4 constant LCDDR8 \ LCD Data Register 8
+E6 constant LCDFRR \ LCD Frame Rate Register
+
+\ PORTA
+21 constant DDRA \ Port A Data Direction Register
+20 constant PINA \ Port A Input Pins
+22 constant PORTA \ Port A Data Register
+
+\ PORTB
+24 constant DDRB \ Port B Data Direction Register
+23 constant PINB \ Port B Input Pins
+25 constant PORTB \ Port B Data Register
+
+\ PORTC
+27 constant DDRC \ Port C Data Direction Register
+26 constant PINC \ Port C Input Pins
+28 constant PORTC \ Port C Data Register
+
+\ PORTD
+2A constant DDRD \ Port D Data Direction Register
+29 constant PIND \ Port D Input Pins
+2B constant PORTD \ Port D Data Register
+
+\ PORTE
+2D constant DDRE \ Data Direction Register, Port E
+2C constant PINE \ Input Pins, Port E
+2E constant PORTE \ Data Register, Port E
+
+\ PORTF
+30 constant DDRF \ Data Direction Register, Port F
+2F constant PINF \ Input Pins, Port F
+31 constant PORTF \ Data Register, Port F
+
+\ PORTG
+33 constant DDRG \ Port G Data Direction Register
+32 constant PING \ Port G Input Pins
+34 constant PORTG \ Port G Data Register
+
+\ SPI
+4C constant SPCR \ SPI Control Register
+4E constant SPDR \ SPI Data Register
+4D constant SPSR \ SPI Status Register
+
+\ TIMER_COUNTER_0
+43 constant GTCCR \ General Timer/Control Register
+47 constant OCR0A \ Timer/Counter0 Output Compare Register
+44 constant TCCR0A \ Timer/Counter0 Control Register
+46 constant TCNT0 \ Timer/Counter0
+35 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
+6E constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
+
+\ TIMER_COUNTER_1
+87 constant ICR1H \ Timer/Counter1 Input Capture Register High Byte
+86 constant ICR1L \ Timer/Counter1 Input Capture Register Low Byte
+89 constant OCR1AH \ Timer/Counter1 Output Compare Register A High Byte
+88 constant OCR1AL \ Timer/Counter1 Output Compare Register A Low Byte
+8B constant OCR1BH \ Timer/Counter1 Output Compare Register B High Byte
+8A constant OCR1BL \ Timer/Counter1 Output Compare Register B Low Byte
+80 constant TCCR1A \ Timer/Counter1 Control Register A
+81 constant TCCR1B \ Timer/Counter1 Control Register B
+82 constant TCCR1C \ Timer/Counter 1 Control Register C
+85 constant TCNT1H \ Timer/Counter1 High Byte
+84 constant TCNT1L \ Timer/Counter1 Low Byte
+36 constant TIFR1 \ Timer/Counter1 Interrupt Flag register
+6F constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
+
+\ TIMER_COUNTER_2
+B6 constant ASSR \ Asynchronous Status Register
+B3 constant OCR2A \ Timer/Counter2 Output Compare Register
+B0 constant TCCR2A \ Timer/Counter2 Control Register
+B2 constant TCNT2 \ Timer/Counter2
+37 constant TIFR2 \ Timer/Counter2 Interrupt Flag Register
+70 constant TIMSK2 \ Timer/Counter2 Interrupt Mask register
+
+\ USART0
+C5 constant UBRR0H \ USART Baud Rate Register High Byte
+C4 constant UBRR0L \ USART Baud Rate Register Low Byte
+C0 constant UCSR0A \ USART Control and Status Register A
+C1 constant UCSR0B \ USART Control and Status Register B
+C2 constant UCSR0C \ USART Control and Status Register C
+C6 constant UDR0 \ USART I/O Data Register
+
+\ USI
+B8 constant USICR \ USI Control Register
+BA constant USIDR \ USI Data Register
+B9 constant USISR \ USI Status Register
+
+\ WATCHDOG
+60 constant WDTCR \ Watchdog Timer Control Register
+
+\ Interrupts
+002 constant INT0Addr \ External Interrupt Request 0
+004 constant PCINT0Addr \ Pin Change Interrupt Request 0
+006 constant PCINT1Addr \ Pin Change Interrupt Request 1
+008 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
+00A constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
+00C constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+00E constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
+010 constant TIMER1_COMPBAddr \ Timer/Counter Compare Match B
+012 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+014 constant TIMER0_COMPAddr \ Timer/Counter0 Compare Match
+016 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
+018 constant SPI_STCAddr \ SPI Serial Transfer Complete
+01A constant USART0_RXAddr \ USART0, Rx Complete
+01C constant USART0_UDREAddr \ USART0 Data register Empty
+01E constant USART0_TXAddr \ USART0, Tx Complete
+020 constant USI_STARTAddr \ USI Start Condition
+022 constant USI_OVERFLOWAddr \ USI Overflow
+024 constant ANALOG_COMPAddr \ Analog Comparator
+026 constant ADCAddr \ ADC Conversion Complete
+028 constant EE_READYAddr \ EEPROM Ready
+02A constant SPM_READYAddr \ Store Program Memory Read
+02C constant LCDAddr \ LCD Start of Frame
diff --git a/amforth-6.5/avr8/devices/atmega169/device.asm b/amforth-6.5/avr8/devices/atmega169/device.asm
new file mode 100644
index 0000000..e80445b
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega169/device.asm
@@ -0,0 +1,123 @@
+; Partname: ATmega169
+; Built using part description XML file version 300
+; generated automatically, do not edit
+
+.nolist
+ .include "m169def.inc"
+.list
+
+.equ ramstart = $100
+.equ CELLSIZE = 2
+.macro readflashcell
+ lsl zl
+ rol zh
+ lpm @0, Z+
+ lpm @1, Z+
+.endmacro
+.macro writeflashcell
+ lsl zl
+ rol zh
+.endmacro
+
+; the following definitions are shortcuts for the respective forth source segments if set to 1
+.set WANT_AD_CONVERTER = 0
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_BOOT_LOAD = 0
+.set WANT_CPU = 0
+.set WANT_EEPROM = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_JTAG = 0
+.set WANT_LCD = 0
+.set WANT_PORTA = 0
+.set WANT_PORTB = 0
+.set WANT_PORTC = 0
+.set WANT_PORTD = 0
+.set WANT_PORTE = 0
+.set WANT_PORTF = 0
+.set WANT_PORTG = 0
+.set WANT_SPI = 0
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_TIMER_COUNTER_2 = 0
+.set WANT_USART0 = 0
+.set WANT_USI = 0
+.set WANT_WATCHDOG = 0
+
+
+.ifndef SPMEN
+ .equ SPMEN = SELFPRGEN
+.endif
+
+.ifndef SPMCSR
+ .equ SPMCSR = SPMCR
+.endif
+
+.ifndef EEPE
+ .equ EEPE = EEWE
+.endif
+
+.ifndef EEMPE
+ .equ EEMPE = EEMWE
+.endif
+.equ intvecsize = 2 ; please verify; flash size: 16384 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.equ INTVECTORS = 23
+.org $002
+ rcall isr ; External Interrupt Request 0
+.org $004
+ rcall isr ; Pin Change Interrupt Request 0
+.org $006
+ rcall isr ; Pin Change Interrupt Request 1
+.org $008
+ rcall isr ; Timer/Counter2 Compare Match
+.org $00A
+ rcall isr ; Timer/Counter2 Overflow
+.org $00C
+ rcall isr ; Timer/Counter1 Capture Event
+.org $00E
+ rcall isr ; Timer/Counter1 Compare Match A
+.org $010
+ rcall isr ; Timer/Counter Compare Match B
+.org $012
+ rcall isr ; Timer/Counter1 Overflow
+.org $014
+ rcall isr ; Timer/Counter0 Compare Match
+.org $016
+ rcall isr ; Timer/Counter0 Overflow
+.org $018
+ rcall isr ; SPI Serial Transfer Complete
+.org $01A
+ rcall isr ; USART0, Rx Complete
+.org $01C
+ rcall isr ; USART0 Data register Empty
+.org $01E
+ rcall isr ; USART0, Tx Complete
+.org $020
+ rcall isr ; USI Start Condition
+.org $022
+ rcall isr ; USI Overflow
+.org $024
+ rcall isr ; Analog Comparator
+.org $026
+ rcall isr ; ADC Conversion Complete
+.org $028
+ rcall isr ; EEPROM Ready
+.org $02A
+ rcall isr ; Store Program Memory Read
+.org $02C
+ rcall isr ; LCD Start of Frame
+.nooverlap
+mcu_info:
+mcu_ramsize:
+ .dw 1024
+mcu_eepromsize:
+ .dw 512
+mcu_maxdp:
+ .dw 7168 ; minimum of 0x1C00 (from XML) and 0xffff
+mcu_numints:
+ .dw 23
+mcu_name:
+ .dw 9
+ .db "ATmega169",0
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega169/device.inc b/amforth-6.5/avr8/devices/atmega169/device.inc
new file mode 100644
index 0000000..84d4954
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega169/device.inc
@@ -0,0 +1,1455 @@
+; Partname: ATmega169
+; Built using part description XML file version 300
+; generated automatically, no not edit
+
+; ********
+.if WANT_AD_CONVERTER == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register High Byte
+VE_ADCH:
+ .dw $ff04
+ .db "ADCH"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCH
+XT_ADCH:
+ .dw PFA_DOVARIABLE
+PFA_ADCH:
+ .dw $79
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register Low Byte
+VE_ADCL:
+ .dw $ff04
+ .db "ADCL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCL
+XT_ADCL:
+ .dw PFA_DOVARIABLE
+PFA_ADCL:
+ .dw $78
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register
+VE_ADCSRA:
+ .dw $ff06
+ .db "ADCSRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRA
+XT_ADCSRA:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRA:
+ .dw $7A
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Control and Status Register B
+VE_ADCSRB:
+ .dw $ff06
+ .db "ADCSRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRB
+XT_ADCSRB:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRB:
+ .dw $7B
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC multiplexer Selection Register
+VE_ADMUX:
+ .dw $ff05
+ .db "ADMUX",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADMUX
+XT_ADMUX:
+ .dw PFA_DOVARIABLE
+PFA_ADMUX:
+ .dw $7C
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 0
+VE_DIDR0:
+ .dw $ff05
+ .db "DIDR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR0
+XT_DIDR0:
+ .dw PFA_DOVARIABLE
+PFA_DIDR0:
+ .dw $7E
+
+.endif
+
+; ********
+.if WANT_ANALOG_COMPARATOR == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Control And Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw $50
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 1
+VE_DIDR1:
+ .dw $ff05
+ .db "DIDR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR1
+XT_DIDR1:
+ .dw PFA_DOVARIABLE
+PFA_DIDR1:
+ .dw $7F
+
+.endif
+
+; ********
+.if WANT_BOOT_LOAD == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control Register
+VE_SPMCSR:
+ .dw $ff06
+ .db "SPMCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCSR
+XT_SPMCSR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCSR:
+ .dw $57
+
+.endif
+
+; ********
+.if WANT_CPU == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Clock Prescale Register
+VE_CLKPR:
+ .dw $ff05
+ .db "CLKPR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKPR
+XT_CLKPR:
+ .dw PFA_DOVARIABLE
+PFA_CLKPR:
+ .dw $61
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 0
+VE_GPIOR0:
+ .dw $ff06
+ .db "GPIOR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR0
+XT_GPIOR0:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR0:
+ .dw $3E
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 1
+VE_GPIOR1:
+ .dw $ff06
+ .db "GPIOR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR1
+XT_GPIOR1:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR1:
+ .dw $4A
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 2
+VE_GPIOR2:
+ .dw $ff06
+ .db "GPIOR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR2
+XT_GPIOR2:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR2:
+ .dw $4B
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw $55
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Status Register
+VE_MCUSR:
+ .dw $ff05
+ .db "MCUSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUSR
+XT_MCUSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUSR:
+ .dw $54
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Calibration Value
+VE_OSCCAL:
+ .dw $ff06
+ .db "OSCCAL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSCCAL
+XT_OSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_OSCCAL:
+ .dw $66
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register
+VE_PRR:
+ .dw $ff03
+ .db "PRR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR
+XT_PRR:
+ .dw PFA_DOVARIABLE
+PFA_PRR:
+ .dw $64
+; ( -- addr ) System Constant
+; R( -- )
+; Sleep Mode Control Register
+VE_SMCR:
+ .dw $ff04
+ .db "SMCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SMCR
+XT_SMCR:
+ .dw PFA_DOVARIABLE
+PFA_SMCR:
+ .dw $53
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer High
+VE_SPH:
+ .dw $ff03
+ .db "SPH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPH
+XT_SPH:
+ .dw PFA_DOVARIABLE
+PFA_SPH:
+ .dw $5E
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer Low
+VE_SPL:
+ .dw $ff03
+ .db "SPL",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPL
+XT_SPL:
+ .dw PFA_DOVARIABLE
+PFA_SPL:
+ .dw $5D
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw $5F
+
+.endif
+
+; ********
+.if WANT_EEPROM == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Address Register High Byte
+VE_EEARH:
+ .dw $ff05
+ .db "EEARH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEARH
+XT_EEARH:
+ .dw PFA_DOVARIABLE
+PFA_EEARH:
+ .dw $42
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Address Register Low Byte
+VE_EEARL:
+ .dw $ff05
+ .db "EEARL",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEARL
+XT_EEARL:
+ .dw PFA_DOVARIABLE
+PFA_EEARL:
+ .dw $41
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw $3F
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw $40
+
+.endif
+
+; ********
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register
+VE_EICRA:
+ .dw $ff05
+ .db "EICRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRA
+XT_EICRA:
+ .dw PFA_DOVARIABLE
+PFA_EICRA:
+ .dw $69
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Flag Register
+VE_EIFR:
+ .dw $ff04
+ .db "EIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIFR
+XT_EIFR:
+ .dw PFA_DOVARIABLE
+PFA_EIFR:
+ .dw $3C
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Mask Register
+VE_EIMSK:
+ .dw $ff05
+ .db "EIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIMSK
+XT_EIMSK:
+ .dw PFA_DOVARIABLE
+PFA_EIMSK:
+ .dw $3D
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 0
+VE_PCMSK0:
+ .dw $ff06
+ .db "PCMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK0
+XT_PCMSK0:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK0:
+ .dw $6B
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 1
+VE_PCMSK1:
+ .dw $ff06
+ .db "PCMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK1
+XT_PCMSK1:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK1:
+ .dw $6C
+
+.endif
+
+; ********
+.if WANT_JTAG == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; On-Chip Debug Related Register in I/O Memory
+VE_OCDR:
+ .dw $ff04
+ .db "OCDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCDR
+XT_OCDR:
+ .dw PFA_DOVARIABLE
+PFA_OCDR:
+ .dw $51
+
+.endif
+
+; ********
+.if WANT_LCD == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Contrast Control Register
+VE_LCDCCR:
+ .dw $ff06
+ .db "LCDCCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDCCR
+XT_LCDCCR:
+ .dw PFA_DOVARIABLE
+PFA_LCDCCR:
+ .dw $E7
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Control Register A
+VE_LCDCRA:
+ .dw $ff06
+ .db "LCDCRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDCRA
+XT_LCDCRA:
+ .dw PFA_DOVARIABLE
+PFA_LCDCRA:
+ .dw $E4
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Control and Status Register B
+VE_LCDCRB:
+ .dw $ff06
+ .db "LCDCRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDCRB
+XT_LCDCRB:
+ .dw PFA_DOVARIABLE
+PFA_LCDCRB:
+ .dw $E5
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 0
+VE_LCDDR0:
+ .dw $ff06
+ .db "LCDDR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR0
+XT_LCDDR0:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR0:
+ .dw $EC
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 1
+VE_LCDDR1:
+ .dw $ff06
+ .db "LCDDR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR1
+XT_LCDDR1:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR1:
+ .dw $ED
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 10
+VE_LCDDR10:
+ .dw $ff07
+ .db "LCDDR10",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR10
+XT_LCDDR10:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR10:
+ .dw $F6
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 11
+VE_LCDDR11:
+ .dw $ff07
+ .db "LCDDR11",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR11
+XT_LCDDR11:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR11:
+ .dw $F7
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 12
+VE_LCDDR12:
+ .dw $ff07
+ .db "LCDDR12",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR12
+XT_LCDDR12:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR12:
+ .dw $F8
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 13
+VE_LCDDR13:
+ .dw $ff07
+ .db "LCDDR13",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR13
+XT_LCDDR13:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR13:
+ .dw $F9
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 15
+VE_LCDDR15:
+ .dw $ff07
+ .db "LCDDR15",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR15
+XT_LCDDR15:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR15:
+ .dw $FB
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 16
+VE_LCDDR16:
+ .dw $ff07
+ .db "LCDDR16",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR16
+XT_LCDDR16:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR16:
+ .dw $FC
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 17
+VE_LCDDR17:
+ .dw $ff07
+ .db "LCDDR17",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR17
+XT_LCDDR17:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR17:
+ .dw $FD
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 18
+VE_LCDDR18:
+ .dw $ff07
+ .db "LCDDR18",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR18
+XT_LCDDR18:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR18:
+ .dw $FE
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 2
+VE_LCDDR2:
+ .dw $ff06
+ .db "LCDDR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR2
+XT_LCDDR2:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR2:
+ .dw $EE
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 3
+VE_LCDDR3:
+ .dw $ff06
+ .db "LCDDR3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR3
+XT_LCDDR3:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR3:
+ .dw $EF
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 5
+VE_LCDDR5:
+ .dw $ff06
+ .db "LCDDR5"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR5
+XT_LCDDR5:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR5:
+ .dw $F1
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 6
+VE_LCDDR6:
+ .dw $ff06
+ .db "LCDDR6"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR6
+XT_LCDDR6:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR6:
+ .dw $F2
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 7
+VE_LCDDR7:
+ .dw $ff06
+ .db "LCDDR7"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR7
+XT_LCDDR7:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR7:
+ .dw $F3
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 8
+VE_LCDDR8:
+ .dw $ff06
+ .db "LCDDR8"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR8
+XT_LCDDR8:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR8:
+ .dw $F4
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Frame Rate Register
+VE_LCDFRR:
+ .dw $ff06
+ .db "LCDFRR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDFRR
+XT_LCDFRR:
+ .dw PFA_DOVARIABLE
+PFA_LCDFRR:
+ .dw $E6
+
+.endif
+
+; ********
+.if WANT_PORTA == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Direction Register
+VE_DDRA:
+ .dw $ff04
+ .db "DDRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRA
+XT_DDRA:
+ .dw PFA_DOVARIABLE
+PFA_DDRA:
+ .dw $21
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Input Pins
+VE_PINA:
+ .dw $ff04
+ .db "PINA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINA
+XT_PINA:
+ .dw PFA_DOVARIABLE
+PFA_PINA:
+ .dw $20
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Register
+VE_PORTA:
+ .dw $ff05
+ .db "PORTA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTA
+XT_PORTA:
+ .dw PFA_DOVARIABLE
+PFA_PORTA:
+ .dw $22
+
+.endif
+
+; ********
+.if WANT_PORTB == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw $24
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw $23
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw $25
+
+.endif
+
+; ********
+.if WANT_PORTC == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Direction Register
+VE_DDRC:
+ .dw $ff04
+ .db "DDRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRC
+XT_DDRC:
+ .dw PFA_DOVARIABLE
+PFA_DDRC:
+ .dw $27
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Input Pins
+VE_PINC:
+ .dw $ff04
+ .db "PINC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINC
+XT_PINC:
+ .dw PFA_DOVARIABLE
+PFA_PINC:
+ .dw $26
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Register
+VE_PORTC:
+ .dw $ff05
+ .db "PORTC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTC
+XT_PORTC:
+ .dw PFA_DOVARIABLE
+PFA_PORTC:
+ .dw $28
+
+.endif
+
+; ********
+.if WANT_PORTD == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw $2A
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw $29
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw $2B
+
+.endif
+
+; ********
+.if WANT_PORTE == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port E
+VE_DDRE:
+ .dw $ff04
+ .db "DDRE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRE
+XT_DDRE:
+ .dw PFA_DOVARIABLE
+PFA_DDRE:
+ .dw $2D
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port E
+VE_PINE:
+ .dw $ff04
+ .db "PINE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINE
+XT_PINE:
+ .dw PFA_DOVARIABLE
+PFA_PINE:
+ .dw $2C
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port E
+VE_PORTE:
+ .dw $ff05
+ .db "PORTE",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTE
+XT_PORTE:
+ .dw PFA_DOVARIABLE
+PFA_PORTE:
+ .dw $2E
+
+.endif
+
+; ********
+.if WANT_PORTF == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port F
+VE_DDRF:
+ .dw $ff04
+ .db "DDRF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRF
+XT_DDRF:
+ .dw PFA_DOVARIABLE
+PFA_DDRF:
+ .dw $30
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port F
+VE_PINF:
+ .dw $ff04
+ .db "PINF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINF
+XT_PINF:
+ .dw PFA_DOVARIABLE
+PFA_PINF:
+ .dw $2F
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port F
+VE_PORTF:
+ .dw $ff05
+ .db "PORTF",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTF
+XT_PORTF:
+ .dw PFA_DOVARIABLE
+PFA_PORTF:
+ .dw $31
+
+.endif
+
+; ********
+.if WANT_PORTG == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Data Direction Register
+VE_DDRG:
+ .dw $ff04
+ .db "DDRG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRG
+XT_DDRG:
+ .dw PFA_DOVARIABLE
+PFA_DDRG:
+ .dw $33
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Input Pins
+VE_PING:
+ .dw $ff04
+ .db "PING"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PING
+XT_PING:
+ .dw PFA_DOVARIABLE
+PFA_PING:
+ .dw $32
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Data Register
+VE_PORTG:
+ .dw $ff05
+ .db "PORTG",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTG
+XT_PORTG:
+ .dw PFA_DOVARIABLE
+PFA_PORTG:
+ .dw $34
+
+.endif
+
+; ********
+.if WANT_SPI == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR:
+ .dw $ff04
+ .db "SPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR
+XT_SPCR:
+ .dw PFA_DOVARIABLE
+PFA_SPCR:
+ .dw $4C
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR:
+ .dw $ff04
+ .db "SPDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR
+XT_SPDR:
+ .dw PFA_DOVARIABLE
+PFA_SPDR:
+ .dw $4E
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR:
+ .dw $ff04
+ .db "SPSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR
+XT_SPSR:
+ .dw PFA_DOVARIABLE
+PFA_SPSR:
+ .dw $4D
+
+.endif
+
+; ********
+.if WANT_TIMER_COUNTER_0 == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; General Timer/Control Register
+VE_GTCCR:
+ .dw $ff05
+ .db "GTCCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GTCCR
+XT_GTCCR:
+ .dw PFA_DOVARIABLE
+PFA_GTCCR:
+ .dw $43
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0A:
+ .dw $ff05
+ .db "OCR0A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0A
+XT_OCR0A:
+ .dw PFA_DOVARIABLE
+PFA_OCR0A:
+ .dw $47
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Control Register
+VE_TCCR0A:
+ .dw $ff06
+ .db "TCCR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0A
+XT_TCCR0A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0A:
+ .dw $44
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw $46
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Flag register
+VE_TIFR0:
+ .dw $ff05
+ .db "TIFR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR0
+XT_TIFR0:
+ .dw PFA_DOVARIABLE
+PFA_TIFR0:
+ .dw $35
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Mask Register
+VE_TIMSK0:
+ .dw $ff06
+ .db "TIMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK0
+XT_TIMSK0:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK0:
+ .dw $6E
+
+.endif
+
+; ********
+.if WANT_TIMER_COUNTER_1 == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register High Byte
+VE_ICR1H:
+ .dw $ff05
+ .db "ICR1H",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1H
+XT_ICR1H:
+ .dw PFA_DOVARIABLE
+PFA_ICR1H:
+ .dw $87
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Low Byte
+VE_ICR1L:
+ .dw $ff05
+ .db "ICR1L",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1L
+XT_ICR1L:
+ .dw PFA_DOVARIABLE
+PFA_ICR1L:
+ .dw $86
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register A High Byte
+VE_OCR1AH:
+ .dw $ff06
+ .db "OCR1AH"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1AH
+XT_OCR1AH:
+ .dw PFA_DOVARIABLE
+PFA_OCR1AH:
+ .dw $89
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register A Low Byte
+VE_OCR1AL:
+ .dw $ff06
+ .db "OCR1AL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1AL
+XT_OCR1AL:
+ .dw PFA_DOVARIABLE
+PFA_OCR1AL:
+ .dw $88
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register B High Byte
+VE_OCR1BH:
+ .dw $ff06
+ .db "OCR1BH"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1BH
+XT_OCR1BH:
+ .dw PFA_DOVARIABLE
+PFA_OCR1BH:
+ .dw $8B
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register B Low Byte
+VE_OCR1BL:
+ .dw $ff06
+ .db "OCR1BL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1BL
+XT_OCR1BL:
+ .dw PFA_DOVARIABLE
+PFA_OCR1BL:
+ .dw $8A
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw $80
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw $81
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter 1 Control Register C
+VE_TCCR1C:
+ .dw $ff06
+ .db "TCCR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1C
+XT_TCCR1C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1C:
+ .dw $82
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 High Byte
+VE_TCNT1H:
+ .dw $ff06
+ .db "TCNT1H"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1H
+XT_TCNT1H:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1H:
+ .dw $85
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Low Byte
+VE_TCNT1L:
+ .dw $ff06
+ .db "TCNT1L"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1L
+XT_TCNT1L:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1L:
+ .dw $84
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Flag register
+VE_TIFR1:
+ .dw $ff05
+ .db "TIFR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR1
+XT_TIFR1:
+ .dw PFA_DOVARIABLE
+PFA_TIFR1:
+ .dw $36
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Mask Register
+VE_TIMSK1:
+ .dw $ff06
+ .db "TIMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK1
+XT_TIMSK1:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK1:
+ .dw $6F
+
+.endif
+
+; ********
+.if WANT_TIMER_COUNTER_2 == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Asynchronous Status Register
+VE_ASSR:
+ .dw $ff04
+ .db "ASSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ASSR
+XT_ASSR:
+ .dw PFA_DOVARIABLE
+PFA_ASSR:
+ .dw $B6
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register
+VE_OCR2A:
+ .dw $ff05
+ .db "OCR2A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2A
+XT_OCR2A:
+ .dw PFA_DOVARIABLE
+PFA_OCR2A:
+ .dw $B3
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register
+VE_TCCR2A:
+ .dw $ff06
+ .db "TCCR2A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2A
+XT_TCCR2A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2A:
+ .dw $B0
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2
+VE_TCNT2:
+ .dw $ff05
+ .db "TCNT2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT2
+XT_TCNT2:
+ .dw PFA_DOVARIABLE
+PFA_TCNT2:
+ .dw $B2
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Interrupt Flag Register
+VE_TIFR2:
+ .dw $ff05
+ .db "TIFR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR2
+XT_TIFR2:
+ .dw PFA_DOVARIABLE
+PFA_TIFR2:
+ .dw $37
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Interrupt Mask register
+VE_TIMSK2:
+ .dw $ff06
+ .db "TIMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK2
+XT_TIMSK2:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK2:
+ .dw $70
+
+.endif
+
+; ********
+.if WANT_USART0 == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register High Byte
+VE_UBRR0H:
+ .dw $ff06
+ .db "UBRR0H"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR0H
+XT_UBRR0H:
+ .dw PFA_DOVARIABLE
+PFA_UBRR0H:
+ .dw $C5
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Low Byte
+VE_UBRR0L:
+ .dw $ff06
+ .db "UBRR0L"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR0L
+XT_UBRR0L:
+ .dw PFA_DOVARIABLE
+PFA_UBRR0L:
+ .dw $C4
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR0A:
+ .dw $ff06
+ .db "UCSR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0A
+XT_UCSR0A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0A:
+ .dw $C0
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR0B:
+ .dw $ff06
+ .db "UCSR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0B
+XT_UCSR0B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0B:
+ .dw $C1
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR0C:
+ .dw $ff06
+ .db "UCSR0C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0C
+XT_UCSR0C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0C:
+ .dw $C2
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR0:
+ .dw $ff04
+ .db "UDR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR0
+XT_UDR0:
+ .dw PFA_DOVARIABLE
+PFA_UDR0:
+ .dw $C6
+
+.endif
+
+; ********
+.if WANT_USI == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; USI Control Register
+VE_USICR:
+ .dw $ff05
+ .db "USICR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USICR
+XT_USICR:
+ .dw PFA_DOVARIABLE
+PFA_USICR:
+ .dw $B8
+; ( -- addr ) System Constant
+; R( -- )
+; USI Data Register
+VE_USIDR:
+ .dw $ff05
+ .db "USIDR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USIDR
+XT_USIDR:
+ .dw PFA_DOVARIABLE
+PFA_USIDR:
+ .dw $BA
+; ( -- addr ) System Constant
+; R( -- )
+; USI Status Register
+VE_USISR:
+ .dw $ff05
+ .db "USISR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USISR
+XT_USISR:
+ .dw PFA_DOVARIABLE
+PFA_USISR:
+ .dw $B9
+
+.endif
+
+; ********
+.if WANT_WATCHDOG == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCR:
+ .dw $ff05
+ .db "WDTCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCR
+XT_WDTCR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCR:
+ .dw $60
+
+.endif
diff --git a/amforth-6.5/avr8/devices/atmega169/device.py b/amforth-6.5/avr8/devices/atmega169/device.py
new file mode 100644
index 0000000..4dc59ba
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega169/device.py
@@ -0,0 +1,137 @@
+# Partname: ATmega169
+# Built using part description XML file version 300
+# generated automatically, do not edit
+MCUREGS = {
+ 'ADCH': '$79',
+ 'ADCL': '$78',
+ 'ADCSRA': '$7A',
+ 'ADCSRB': '$7B',
+ 'ADMUX': '$7C',
+ 'DIDR0': '$7E',
+ 'ACSR': '$50',
+ 'DIDR1': '$7F',
+ 'SPMCSR': '$57',
+ 'CLKPR': '$61',
+ 'GPIOR0': '$3E',
+ 'GPIOR1': '$4A',
+ 'GPIOR2': '$4B',
+ 'MCUCR': '$55',
+ 'MCUSR': '$54',
+ 'OSCCAL': '$66',
+ 'PRR': '$64',
+ 'SMCR': '$53',
+ 'SPH': '$5E',
+ 'SPL': '$5D',
+ 'SREG': '$5F',
+ 'EEARH': '$42',
+ 'EEARL': '$41',
+ 'EECR': '$3F',
+ 'EEDR': '$40',
+ 'EICRA': '$69',
+ 'EIFR': '$3C',
+ 'EIMSK': '$3D',
+ 'PCMSK0': '$6B',
+ 'PCMSK1': '$6C',
+ 'OCDR': '$51',
+ 'LCDCCR': '$E7',
+ 'LCDCRA': '$E4',
+ 'LCDCRB': '$E5',
+ 'LCDDR0': '$EC',
+ 'LCDDR1': '$ED',
+ 'LCDDR10': '$F6',
+ 'LCDDR11': '$F7',
+ 'LCDDR12': '$F8',
+ 'LCDDR13': '$F9',
+ 'LCDDR15': '$FB',
+ 'LCDDR16': '$FC',
+ 'LCDDR17': '$FD',
+ 'LCDDR18': '$FE',
+ 'LCDDR2': '$EE',
+ 'LCDDR3': '$EF',
+ 'LCDDR5': '$F1',
+ 'LCDDR6': '$F2',
+ 'LCDDR7': '$F3',
+ 'LCDDR8': '$F4',
+ 'LCDFRR': '$E6',
+ 'DDRA': '$21',
+ 'PINA': '$20',
+ 'PORTA': '$22',
+ 'DDRB': '$24',
+ 'PINB': '$23',
+ 'PORTB': '$25',
+ 'DDRC': '$27',
+ 'PINC': '$26',
+ 'PORTC': '$28',
+ 'DDRD': '$2A',
+ 'PIND': '$29',
+ 'PORTD': '$2B',
+ 'DDRE': '$2D',
+ 'PINE': '$2C',
+ 'PORTE': '$2E',
+ 'DDRF': '$30',
+ 'PINF': '$2F',
+ 'PORTF': '$31',
+ 'DDRG': '$33',
+ 'PING': '$32',
+ 'PORTG': '$34',
+ 'SPCR': '$4C',
+ 'SPDR': '$4E',
+ 'SPSR': '$4D',
+ 'GTCCR': '$43',
+ 'OCR0A': '$47',
+ 'TCCR0A': '$44',
+ 'TCNT0': '$46',
+ 'TIFR0': '$35',
+ 'TIMSK0': '$6E',
+ 'ICR1H': '$87',
+ 'ICR1L': '$86',
+ 'OCR1AH': '$89',
+ 'OCR1AL': '$88',
+ 'OCR1BH': '$8B',
+ 'OCR1BL': '$8A',
+ 'TCCR1A': '$80',
+ 'TCCR1B': '$81',
+ 'TCCR1C': '$82',
+ 'TCNT1H': '$85',
+ 'TCNT1L': '$84',
+ 'TIFR1': '$36',
+ 'TIMSK1': '$6F',
+ 'ASSR': '$B6',
+ 'OCR2A': '$B3',
+ 'TCCR2A': '$B0',
+ 'TCNT2': '$B2',
+ 'TIFR2': '$37',
+ 'TIMSK2': '$70',
+ 'UBRR0H': '$C5',
+ 'UBRR0L': '$C4',
+ 'UCSR0A': '$C0',
+ 'UCSR0B': '$C1',
+ 'UCSR0C': '$C2',
+ 'UDR0': '$C6',
+ 'USICR': '$B8',
+ 'USIDR': '$BA',
+ 'USISR': '$B9',
+ 'WDTCR': '$60',
+ 'INT0Addr': '$002',
+ 'PCINT0Addr': '$004',
+ 'PCINT1Addr': '$006',
+ 'TIMER2_COMPAddr': '$008',
+ 'TIMER2_OVFAddr': '$00A',
+ 'TIMER1_CAPTAddr': '$00C',
+ 'TIMER1_COMPAAddr': '$00E',
+ 'TIMER1_COMPBAddr': '$010',
+ 'TIMER1_OVFAddr': '$012',
+ 'TIMER0_COMPAddr': '$014',
+ 'TIMER0_OVFAddr': '$016',
+ 'SPI_STCAddr': '$018',
+ 'USART0_RXAddr': '$01A',
+ 'USART0_UDREAddr': '$01C',
+ 'USART0_TXAddr': '$01E',
+ 'USI_STARTAddr': '$020',
+ 'USI_OVERFLOWAddr': '$022',
+ 'ANALOG_COMPAddr': '$024',
+ 'ADCAddr': '$026',
+ 'EE_READYAddr': '$028',
+ 'SPM_READYAddr': '$02A',
+ 'LCDAddr': '$02C'
+} \ No newline at end of file
diff --git a/amforth-6.5/avr8/devices/atmega169a/atmega169a.frt b/amforth-6.5/avr8/devices/atmega169a/atmega169a.frt
new file mode 100644
index 0000000..3cde548
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega169a/atmega169a.frt
@@ -0,0 +1,319 @@
+\ Partname: ATmega169A
+\ generated automatically
+
+\ TIMER_COUNTER_0
+&68 constant TCCR0A \ Timer/Counter0 Control Register
+ $80 constant TCCR0A_FOC0A \ Force Output Compare
+ $40 constant TCCR0A_WGM00 \ Waveform Generation Mode 0
+ $30 constant TCCR0A_COM0A \ Compare Match Output Modes
+ $08 constant TCCR0A_WGM01 \ Waveform Generation Mode 1
+ $07 constant TCCR0A_CS0 \ Clock Selects
+&70 constant TCNT0 \ Timer/Counter0
+&71 constant OCR0A \ Timer/Counter0 Output Compare Register
+&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
+ $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match Interrupt Enable
+ $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
+&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
+ $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0
+ $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
+&67 constant GTCCR \ General Timer/Control Register
+ $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
+ $01 constant GTCCR_PSR310 \ Prescaler Reset Timer/Counter1 and Timer/Counter0
+\ TIMER_COUNTER_1
+&128 constant TCCR1A \ Timer/Counter1 Control Register A
+ $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
+ $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
+ $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
+&129 constant TCCR1B \ Timer/Counter1 Control Register B
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
+ $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
+&130 constant TCCR1C \ Timer/Counter 1 Control Register C
+ $80 constant TCCR1C_FOC1A \ Force Output Compare 1A
+ $40 constant TCCR1C_FOC1B \ Force Output Compare 1B
+&132 constant TCNT1 \ Timer/Counter1 Bytes
+&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
+&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
+&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
+&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
+ $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
+ $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
+ $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
+ $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
+&54 constant TIFR1 \ Timer/Counter1 Interrupt Flag register
+ $20 constant TIFR1_ICF1 \ Input Capture Flag 1
+ $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
+ $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
+ $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
+\ TIMER_COUNTER_2
+&176 constant TCCR2A \ Timer/Counter2 Control Register
+ $80 constant TCCR2A_FOC2A \ Force Output Compare A
+ $40 constant TCCR2A_WGM20 \ Waveform Generation Mode
+ $30 constant TCCR2A_COM2A \ Compare Output Mode bits
+ $08 constant TCCR2A_WGM21 \ Waveform Generation Mode
+ $07 constant TCCR2A_CS2 \ Clock Select bits
+&178 constant TCNT2 \ Timer/Counter2
+&179 constant OCR2A \ Timer/Counter2 Output Compare Register
+&112 constant TIMSK2 \ Timer/Counter2 Interrupt Mask register
+ $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match Interrupt Enable
+ $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
+&55 constant TIFR2 \ Timer/Counter2 Interrupt Flag Register
+ $02 constant TIFR2_OCF2A \ Timer/Counter2 Output Compare Flag 2
+ $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
+&182 constant ASSR \ Asynchronous Status Register
+ $10 constant ASSR_EXCLK \ Enable External Clock Interrupt
+ $08 constant ASSR_AS2 \ AS2: Asynchronous Timer/Counter2
+ $04 constant ASSR_TCN2UB \ TCN2UB: Timer/Counter2 Update Busy
+ $02 constant ASSR_OCR2UB \ Output Compare Register2 Update Busy
+ $01 constant ASSR_TCR2UB \ TCR2UB: Timer/Counter Control Register2 Update Busy
+\ WATCHDOG
+&96 constant WDTCR \ Watchdog Timer Control Register
+ $10 constant WDTCR_WDCE \ Watchdog Change Enable
+ $08 constant WDTCR_WDE \ Watch Dog Enable
+ $07 constant WDTCR_WDP \ Watch Dog Timer Prescaler bits
+\ EEPROM
+&65 constant EEAR \ EEPROM Address Register Bytes
+&64 constant EEDR \ EEPROM Data Register
+&63 constant EECR \ EEPROM Control Register
+ $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
+ $04 constant EECR_EEMWE \ EEPROM Master Write Enable
+ $02 constant EECR_EEWE \ EEPROM Write Enable
+ $01 constant EECR_EERE \ EEPROM Read Enable
+\ SPI
+&76 constant SPCR \ SPI Control Register
+ $80 constant SPCR_SPIE \ SPI Interrupt Enable
+ $40 constant SPCR_SPE \ SPI Enable
+ $20 constant SPCR_DORD \ Data Order
+ $10 constant SPCR_MSTR \ Master/Slave Select
+ $08 constant SPCR_CPOL \ Clock polarity
+ $04 constant SPCR_CPHA \ Clock Phase
+ $03 constant SPCR_SPR \ SPI Clock Rate Selects
+&77 constant SPSR \ SPI Status Register
+ $80 constant SPSR_SPIF \ SPI Interrupt Flag
+ $40 constant SPSR_WCOL \ Write Collision Flag
+ $01 constant SPSR_SPI2X \ Double SPI Speed Bit
+&78 constant SPDR \ SPI Data Register
+\ PORTA
+&34 constant PORTA \ Port A Data Register
+&33 constant DDRA \ Port A Data Direction Register
+&32 constant PINA \ Port A Input Pins
+\ PORTB
+&37 constant PORTB \ Port B Data Register
+&36 constant DDRB \ Port B Data Direction Register
+&35 constant PINB \ Port B Input Pins
+\ PORTC
+&40 constant PORTC \ Port C Data Register
+&39 constant DDRC \ Port C Data Direction Register
+&38 constant PINC \ Port C Input Pins
+\ PORTD
+&43 constant PORTD \ Port D Data Register
+&42 constant DDRD \ Port D Data Direction Register
+&41 constant PIND \ Port D Input Pins
+\ ANALOG_COMPARATOR
+&123 constant ADCSRB \ ADC Control and Status Register B
+ $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer Enable
+&80 constant ACSR \ Analog Comparator Control And Status Register
+ $80 constant ACSR_ACD \ Analog Comparator Disable
+ $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
+ $20 constant ACSR_ACO \ Analog Compare Output
+ $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
+ $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
+ $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
+ $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
+&127 constant DIDR1 \ Digital Input Disable Register 1
+ $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
+ $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
+\ PORTE
+&46 constant PORTE \ Data Register, Port E
+&45 constant DDRE \ Data Direction Register, Port E
+&44 constant PINE \ Input Pins, Port E
+\ PORTF
+&49 constant PORTF \ Data Register, Port F
+&48 constant DDRF \ Data Direction Register, Port F
+&47 constant PINF \ Input Pins, Port F
+\ JTAG
+&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
+&85 constant MCUCR \ MCU Control Register
+ $80 constant MCUCR_JTD \ JTAG Interface Disable
+&84 constant MCUSR \ MCU Status Register
+ $10 constant MCUSR_JTRF \ JTAG Reset Flag
+\ LCD
+&228 constant LCDCRA \ LCD Control Register A
+ $80 constant LCDCRA_LCDEN \ LCD Enable
+ $40 constant LCDCRA_LCDAB \ LCD A or B waveform
+ $10 constant LCDCRA_LCDIF \ LCD Interrupt Flag
+ $08 constant LCDCRA_LCDIE \ LCD Interrupt Enable
+ $04 constant LCDCRA_LCDBD \ LCD Buffer Disable
+ $02 constant LCDCRA_LCDCCD \ LCD Contrast Control Disable
+ $01 constant LCDCRA_LCDBL \ LCD Blanking
+&229 constant LCDCRB \ LCD Control and Status Register B
+ $80 constant LCDCRB_LCDCS \ LCD CLock Select
+ $40 constant LCDCRB_LCD2B \ LCD 1/2 Bias Select
+ $30 constant LCDCRB_LCDMUX \ LCD Mux Selects
+ $07 constant LCDCRB_LCDPM \ LCD Port Masks
+&230 constant LCDFRR \ LCD Frame Rate Register
+ $70 constant LCDFRR_LCDPS \ LCD Prescaler Selects
+ $07 constant LCDFRR_LCDCD \ LCD Clock Dividers
+&231 constant LCDCCR \ LCD Contrast Control Register
+ $E0 constant LCDCCR_LCDDC \ LCD Display Configuration Bits
+ $10 constant LCDCCR_LCDMDT \ LCD Maximum Drive Time
+ $0F constant LCDCCR_LCDCC \ LCD Contrast Controls
+&254 constant LCDDR18 \ LCD Data Register 18
+&253 constant LCDDR17 \ LCD Data Register 17
+&252 constant LCDDR16 \ LCD Data Register 16
+&251 constant LCDDR15 \ LCD Data Register 15
+&249 constant LCDDR13 \ LCD Data Register 13
+&248 constant LCDDR12 \ LCD Data Register 12
+&247 constant LCDDR11 \ LCD Data Register 11
+&246 constant LCDDR10 \ LCD Data Register 10
+&244 constant LCDDR8 \ LCD Data Register 8
+&243 constant LCDDR7 \ LCD Data Register 7
+&242 constant LCDDR6 \ LCD Data Register 6
+&241 constant LCDDR5 \ LCD Data Register 5
+&239 constant LCDDR3 \ LCD Data Register 3
+&238 constant LCDDR2 \ LCD Data Register 2
+&237 constant LCDDR1 \ LCD Data Register 1
+&236 constant LCDDR0 \ LCD Data Register 0
+\ USI
+&186 constant USIDR \ USI Data Register
+&185 constant USISR \ USI Status Register
+ $80 constant USISR_USISIF \ Start Condition Interrupt Flag
+ $40 constant USISR_USIOIF \ Counter Overflow Interrupt Flag
+ $20 constant USISR_USIPF \ Stop Condition Flag
+ $10 constant USISR_USIDC \ Data Output Collision
+ $0F constant USISR_USICNT \ USI Counter Value Bits
+&184 constant USICR \ USI Control Register
+ $80 constant USICR_USISIE \ Start Condition Interrupt Enable
+ $40 constant USICR_USIOIE \ Counter Overflow Interrupt Enable
+ $30 constant USICR_USIWM \ USI Wire Mode Bits
+ $0C constant USICR_USICS \ USI Clock Source Select Bits
+ $02 constant USICR_USICLK \ Clock Strobe
+ $01 constant USICR_USITC \ Toggle Clock Port Pin
+\ AD_CONVERTER
+&124 constant ADMUX \ The ADC multiplexer Selection Register
+ $C0 constant ADMUX_REFS \ Reference Selection Bits
+ $20 constant ADMUX_ADLAR \ Left Adjust Result
+ $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
+&122 constant ADCSRA \ The ADC Control and Status register
+ $80 constant ADCSRA_ADEN \ ADC Enable
+ $40 constant ADCSRA_ADSC \ ADC Start Conversion
+ $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
+ $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
+ $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
+ $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
+&120 constant ADC \ ADC Data Register Bytes
+&126 constant DIDR0 \ Digital Input Disable Register 0
+ $80 constant DIDR0_ADC7D \ ADC7 Digital input Disable
+ $40 constant DIDR0_ADC6D \ ADC6 Digital input Disable
+ $20 constant DIDR0_ADC5D \ ADC5 Digital input Disable
+ $10 constant DIDR0_ADC4D \ ADC4 Digital input Disable
+ $08 constant DIDR0_ADC3D \ ADC3 Digital input Disable
+ $04 constant DIDR0_ADC2D \ ADC2 Digital input Disable
+ $02 constant DIDR0_ADC1D \ ADC1 Digital input Disable
+ $01 constant DIDR0_ADC0D \ ADC0 Digital input Disable
+\ BOOT_LOAD
+&87 constant SPMCSR \ Store Program Memory Control Register
+ $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
+ $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
+ $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
+ $04 constant SPMCSR_PGWRT \ Page Write
+ $02 constant SPMCSR_PGERS \ Page Erase
+ $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
+\ USART0
+&198 constant UDR0 \ USART I/O Data Register
+&192 constant UCSR0A \ USART Control and Status Register A
+ $80 constant UCSR0A_RXC0 \ USART Receive Complete
+ $40 constant UCSR0A_TXC0 \ USART Transmit Complete
+ $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
+ $10 constant UCSR0A_FE0 \ Framing Error
+ $08 constant UCSR0A_DOR0 \ Data OverRun
+ $04 constant UCSR0A_UPE0 \ USART Parity Error
+ $02 constant UCSR0A_U2X0 \ Double the USART Transmission Speed
+ $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
+&193 constant UCSR0B \ USART Control and Status Register B
+ $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
+ $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
+ $20 constant UCSR0B_UDRIE0 \ USART Data Register Empty Interrupt Enable
+ $10 constant UCSR0B_RXEN0 \ Receiver Enable
+ $08 constant UCSR0B_TXEN0 \ Transmitter Enable
+ $04 constant UCSR0B_UCSZ02 \ Character Size
+ $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
+ $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
+&194 constant UCSR0C \ USART Control and Status Register C
+ $40 constant UCSR0C_UMSEL0 \ USART Mode Select
+ $30 constant UCSR0C_UPM0 \ Parity Mode Bits
+ $08 constant UCSR0C_USBS0 \ Stop Bit Select
+ $06 constant UCSR0C_UCSZ0 \ Character Size
+ $01 constant UCSR0C_UCPOL0 \ Clock Polarity
+&196 constant UBRR0 \ USART Baud Rate Register Bytes
+\ PORTG
+&52 constant PORTG \ Port G Data Register
+&51 constant DDRG \ Port G Data Direction Register
+&50 constant PING \ Port G Input Pins
+\ EXTERNAL_INTERRUPT
+&105 constant EICRA \ External Interrupt Control Register
+ $02 constant EICRA_ISC01 \ External Interrupt Sense Control 0 Bit 1
+ $01 constant EICRA_ISC00 \ External Interrupt Sense Control 0 Bit 0
+&61 constant EIMSK \ External Interrupt Mask Register
+ $30 constant EIMSK_PCIE \ Pin Change Interrupt Enables
+ $01 constant EIMSK_INT0 \ External Interrupt Request 0 Enable
+&60 constant EIFR \ External Interrupt Flag Register
+ $30 constant EIFR_PCIF \ Pin Change Interrupt Flags
+ $01 constant EIFR_INTF0 \ External Interrupt Flag 0
+&108 constant PCMSK1 \ Pin Change Mask Register 1
+ $FF constant PCMSK1_PCINT \ Pin Change Enable Masks
+&107 constant PCMSK0 \ Pin Change Mask Register 0
+ $FF constant PCMSK0_PCINT \ Pin Change Enable Masks
+\ CPU
+&95 constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ $08 constant SREG_V \ Two's Complement Overflow Flag
+ $04 constant SREG_N \ Negative Flag
+ $02 constant SREG_Z \ Zero Flag
+ $01 constant SREG_C \ Carry Flag
+&93 constant SP \ Stack Pointer
+&102 constant OSCCAL \ Oscillator Calibration Value
+&97 constant CLKPR \ Clock Prescale Register
+ $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable
+ $0F constant CLKPR_CLKPS \ Clock Prescaler Select Bits
+&100 constant PRR \ Power Reduction Register
+ $10 constant PRR_PRLCD \ Power Reduction LCD
+ $08 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
+ $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
+ $02 constant PRR_PRUSART0 \ Power Reduction USART
+ $01 constant PRR_PRADC \ Power Reduction ADC
+&83 constant SMCR \ Sleep Mode Control Register
+ $0E constant SMCR_SM \ Sleep Mode Select bits
+ $01 constant SMCR_SE \ Sleep Enable
+&75 constant GPIOR2 \ General Purpose IO Register 2
+&74 constant GPIOR1 \ General Purpose IO Register 1
+&62 constant GPIOR0 \ General Purpose IO Register 0
+
+\ Interrupts
+&2 constant INT0Addr \ External Interrupt Request 0
+&4 constant PCINT0Addr \ Pin Change Interrupt Request 0
+&6 constant PCINT1Addr \ Pin Change Interrupt Request 1
+&8 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
+&10 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
+&12 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+&14 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
+&16 constant TIMER1_COMPBAddr \ Timer/Counter Compare Match B
+&18 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+&20 constant TIMER0_COMPAddr \ Timer/Counter0 Compare Match
+&22 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
+&24 constant SPI__STCAddr \ SPI Serial Transfer Complete
+&26 constant USART0__RXAddr \ USART0, Rx Complete
+&28 constant USART0__UDREAddr \ USART0 Data register Empty
+&30 constant USART0__TXAddr \ USART0, Tx Complete
+&32 constant USI_STARTAddr \ USI Start Condition
+&34 constant USI_OVERFLOWAddr \ USI Overflow
+&36 constant ANALOG_COMPAddr \ Analog Comparator
+&38 constant ADCAddr \ ADC Conversion Complete
+&40 constant EE_READYAddr \ EEPROM Ready
+&42 constant SPM_READYAddr \ Store Program Memory Read
+&44 constant LCDAddr \ LCD Start of Frame
diff --git a/amforth-6.5/avr8/devices/atmega169a/device.asm b/amforth-6.5/avr8/devices/atmega169a/device.asm
new file mode 100644
index 0000000..6723bf7
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega169a/device.asm
@@ -0,0 +1,109 @@
+; Partname: ATmega169A
+; generated automatically, do not edit
+
+.nolist
+ .include "m169Adef.inc"
+.list
+
+.equ ramstart = 256
+.equ CELLSIZE = 2
+.macro readflashcell
+ lsl zl
+ rol zh
+ lpm @0, Z+
+ lpm @1, Z+
+.endmacro
+.macro writeflashcell
+ lsl zl
+ rol zh
+.endmacro
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_TIMER_COUNTER_2 = 0
+.set WANT_WATCHDOG = 0
+.set WANT_EEPROM = 0
+.set WANT_SPI = 0
+.set WANT_PORTA = 0
+.set WANT_PORTB = 0
+.set WANT_PORTC = 0
+.set WANT_PORTD = 0
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_PORTE = 0
+.set WANT_PORTF = 0
+.set WANT_JTAG = 0
+.set WANT_LCD = 0
+.set WANT_USI = 0
+.set WANT_AD_CONVERTER = 0
+.set WANT_BOOT_LOAD = 0
+.set WANT_USART0 = 0
+.set WANT_PORTG = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_CPU = 0
+.equ intvecsize = 2 ; please verify; flash size: 16384 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.org 2
+ rcall isr ; External Interrupt Request 0
+.org 4
+ rcall isr ; Pin Change Interrupt Request 0
+.org 6
+ rcall isr ; Pin Change Interrupt Request 1
+.org 8
+ rcall isr ; Timer/Counter2 Compare Match
+.org 10
+ rcall isr ; Timer/Counter2 Overflow
+.org 12
+ rcall isr ; Timer/Counter1 Capture Event
+.org 14
+ rcall isr ; Timer/Counter1 Compare Match A
+.org 16
+ rcall isr ; Timer/Counter Compare Match B
+.org 18
+ rcall isr ; Timer/Counter1 Overflow
+.org 20
+ rcall isr ; Timer/Counter0 Compare Match
+.org 22
+ rcall isr ; Timer/Counter0 Overflow
+.org 24
+ rcall isr ; SPI Serial Transfer Complete
+.org 26
+ rcall isr ; USART0, Rx Complete
+.org 28
+ rcall isr ; USART0 Data register Empty
+.org 30
+ rcall isr ; USART0, Tx Complete
+.org 32
+ rcall isr ; USI Start Condition
+.org 34
+ rcall isr ; USI Overflow
+.org 36
+ rcall isr ; Analog Comparator
+.org 38
+ rcall isr ; ADC Conversion Complete
+.org 40
+ rcall isr ; EEPROM Ready
+.org 42
+ rcall isr ; Store Program Memory Read
+.org 44
+ rcall isr ; LCD Start of Frame
+.equ INTVECTORS = 23
+.nooverlap
+
+; compatability layer (maybe empty)
+.equ EEPE = EEWE
+.equ EEMPE = EEMWE
+
+; controller data area, environment query mcu-info
+mcu_info:
+mcu_ramsize:
+ .dw 1024
+mcu_eepromsize:
+ .dw 512
+mcu_maxdp:
+ .dw 14336
+mcu_numints:
+ .dw 23
+mcu_name:
+ .dw 10
+ .db "ATmega169A"
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega169a/device.inc b/amforth-6.5/avr8/devices/atmega169a/device.inc
new file mode 100644
index 0000000..6e926e1
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega169a/device.inc
@@ -0,0 +1,1293 @@
+; Partname: ATmega169A
+; generated automatically, no not edit
+
+.if WANT_TIMER_COUNTER_0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Control Register
+VE_TCCR0A:
+ .dw $ff06
+ .db "TCCR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0A
+XT_TCCR0A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0A:
+ .dw 68
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw 70
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0A:
+ .dw $ff05
+ .db "OCR0A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0A
+XT_OCR0A:
+ .dw PFA_DOVARIABLE
+PFA_OCR0A:
+ .dw 71
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Mask Register
+VE_TIMSK0:
+ .dw $ff06
+ .db "TIMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK0
+XT_TIMSK0:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK0:
+ .dw 110
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Flag register
+VE_TIFR0:
+ .dw $ff05
+ .db "TIFR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR0
+XT_TIFR0:
+ .dw PFA_DOVARIABLE
+PFA_TIFR0:
+ .dw 53
+; ( -- addr ) System Constant
+; R( -- )
+; General Timer/Control Register
+VE_GTCCR:
+ .dw $ff05
+ .db "GTCCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GTCCR
+XT_GTCCR:
+ .dw PFA_DOVARIABLE
+PFA_GTCCR:
+ .dw 67
+
+.endif
+.if WANT_TIMER_COUNTER_1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw 128
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw 129
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter 1 Control Register C
+VE_TCCR1C:
+ .dw $ff06
+ .db "TCCR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1C
+XT_TCCR1C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1C:
+ .dw 130
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Bytes
+VE_TCNT1:
+ .dw $ff05
+ .db "TCNT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1
+XT_TCNT1:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1:
+ .dw 132
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register A Bytes
+VE_OCR1A:
+ .dw $ff05
+ .db "OCR1A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1A
+XT_OCR1A:
+ .dw PFA_DOVARIABLE
+PFA_OCR1A:
+ .dw 136
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register B Bytes
+VE_OCR1B:
+ .dw $ff05
+ .db "OCR1B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1B
+XT_OCR1B:
+ .dw PFA_DOVARIABLE
+PFA_OCR1B:
+ .dw 138
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Bytes
+VE_ICR1:
+ .dw $ff04
+ .db "ICR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1
+XT_ICR1:
+ .dw PFA_DOVARIABLE
+PFA_ICR1:
+ .dw 134
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Mask Register
+VE_TIMSK1:
+ .dw $ff06
+ .db "TIMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK1
+XT_TIMSK1:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK1:
+ .dw 111
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Flag register
+VE_TIFR1:
+ .dw $ff05
+ .db "TIFR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR1
+XT_TIFR1:
+ .dw PFA_DOVARIABLE
+PFA_TIFR1:
+ .dw 54
+
+.endif
+.if WANT_TIMER_COUNTER_2 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register
+VE_TCCR2A:
+ .dw $ff06
+ .db "TCCR2A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2A
+XT_TCCR2A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2A:
+ .dw 176
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2
+VE_TCNT2:
+ .dw $ff05
+ .db "TCNT2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT2
+XT_TCNT2:
+ .dw PFA_DOVARIABLE
+PFA_TCNT2:
+ .dw 178
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register
+VE_OCR2A:
+ .dw $ff05
+ .db "OCR2A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2A
+XT_OCR2A:
+ .dw PFA_DOVARIABLE
+PFA_OCR2A:
+ .dw 179
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Interrupt Mask register
+VE_TIMSK2:
+ .dw $ff06
+ .db "TIMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK2
+XT_TIMSK2:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK2:
+ .dw 112
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Interrupt Flag Register
+VE_TIFR2:
+ .dw $ff05
+ .db "TIFR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR2
+XT_TIFR2:
+ .dw PFA_DOVARIABLE
+PFA_TIFR2:
+ .dw 55
+; ( -- addr ) System Constant
+; R( -- )
+; Asynchronous Status Register
+VE_ASSR:
+ .dw $ff04
+ .db "ASSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ASSR
+XT_ASSR:
+ .dw PFA_DOVARIABLE
+PFA_ASSR:
+ .dw 182
+
+.endif
+.if WANT_WATCHDOG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCR:
+ .dw $ff05
+ .db "WDTCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCR
+XT_WDTCR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCR:
+ .dw 96
+
+.endif
+.if WANT_EEPROM == 1
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Address Register Bytes
+VE_EEAR:
+ .dw $ff04
+ .db "EEAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEAR
+XT_EEAR:
+ .dw PFA_DOVARIABLE
+PFA_EEAR:
+ .dw 65
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw 64
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw 63
+
+.endif
+.if WANT_SPI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR:
+ .dw $ff04
+ .db "SPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR
+XT_SPCR:
+ .dw PFA_DOVARIABLE
+PFA_SPCR:
+ .dw 76
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR:
+ .dw $ff04
+ .db "SPSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR
+XT_SPSR:
+ .dw PFA_DOVARIABLE
+PFA_SPSR:
+ .dw 77
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR:
+ .dw $ff04
+ .db "SPDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR
+XT_SPDR:
+ .dw PFA_DOVARIABLE
+PFA_SPDR:
+ .dw 78
+
+.endif
+.if WANT_PORTA == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Register
+VE_PORTA:
+ .dw $ff05
+ .db "PORTA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTA
+XT_PORTA:
+ .dw PFA_DOVARIABLE
+PFA_PORTA:
+ .dw 34
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Direction Register
+VE_DDRA:
+ .dw $ff04
+ .db "DDRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRA
+XT_DDRA:
+ .dw PFA_DOVARIABLE
+PFA_DDRA:
+ .dw 33
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Input Pins
+VE_PINA:
+ .dw $ff04
+ .db "PINA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINA
+XT_PINA:
+ .dw PFA_DOVARIABLE
+PFA_PINA:
+ .dw 32
+
+.endif
+.if WANT_PORTB == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw 37
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw 36
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw 35
+
+.endif
+.if WANT_PORTC == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Register
+VE_PORTC:
+ .dw $ff05
+ .db "PORTC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTC
+XT_PORTC:
+ .dw PFA_DOVARIABLE
+PFA_PORTC:
+ .dw 40
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Direction Register
+VE_DDRC:
+ .dw $ff04
+ .db "DDRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRC
+XT_DDRC:
+ .dw PFA_DOVARIABLE
+PFA_DDRC:
+ .dw 39
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Input Pins
+VE_PINC:
+ .dw $ff04
+ .db "PINC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINC
+XT_PINC:
+ .dw PFA_DOVARIABLE
+PFA_PINC:
+ .dw 38
+
+.endif
+.if WANT_PORTD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw 43
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw 42
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw 41
+
+.endif
+.if WANT_ANALOG_COMPARATOR == 1
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Control and Status Register B
+VE_ADCSRB:
+ .dw $ff06
+ .db "ADCSRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRB
+XT_ADCSRB:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRB:
+ .dw 123
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Control And Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw 80
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 1
+VE_DIDR1:
+ .dw $ff05
+ .db "DIDR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR1
+XT_DIDR1:
+ .dw PFA_DOVARIABLE
+PFA_DIDR1:
+ .dw 127
+
+.endif
+.if WANT_PORTE == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port E
+VE_PORTE:
+ .dw $ff05
+ .db "PORTE",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTE
+XT_PORTE:
+ .dw PFA_DOVARIABLE
+PFA_PORTE:
+ .dw 46
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port E
+VE_DDRE:
+ .dw $ff04
+ .db "DDRE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRE
+XT_DDRE:
+ .dw PFA_DOVARIABLE
+PFA_DDRE:
+ .dw 45
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port E
+VE_PINE:
+ .dw $ff04
+ .db "PINE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINE
+XT_PINE:
+ .dw PFA_DOVARIABLE
+PFA_PINE:
+ .dw 44
+
+.endif
+.if WANT_PORTF == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port F
+VE_PORTF:
+ .dw $ff05
+ .db "PORTF",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTF
+XT_PORTF:
+ .dw PFA_DOVARIABLE
+PFA_PORTF:
+ .dw 49
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port F
+VE_DDRF:
+ .dw $ff04
+ .db "DDRF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRF
+XT_DDRF:
+ .dw PFA_DOVARIABLE
+PFA_DDRF:
+ .dw 48
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port F
+VE_PINF:
+ .dw $ff04
+ .db "PINF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINF
+XT_PINF:
+ .dw PFA_DOVARIABLE
+PFA_PINF:
+ .dw 47
+
+.endif
+.if WANT_JTAG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; On-Chip Debug Related Register in I/O Memory
+VE_OCDR:
+ .dw $ff04
+ .db "OCDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCDR
+XT_OCDR:
+ .dw PFA_DOVARIABLE
+PFA_OCDR:
+ .dw 81
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw 85
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Status Register
+VE_MCUSR:
+ .dw $ff05
+ .db "MCUSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUSR
+XT_MCUSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUSR:
+ .dw 84
+
+.endif
+.if WANT_LCD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Control Register A
+VE_LCDCRA:
+ .dw $ff06
+ .db "LCDCRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDCRA
+XT_LCDCRA:
+ .dw PFA_DOVARIABLE
+PFA_LCDCRA:
+ .dw 228
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Control and Status Register B
+VE_LCDCRB:
+ .dw $ff06
+ .db "LCDCRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDCRB
+XT_LCDCRB:
+ .dw PFA_DOVARIABLE
+PFA_LCDCRB:
+ .dw 229
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Frame Rate Register
+VE_LCDFRR:
+ .dw $ff06
+ .db "LCDFRR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDFRR
+XT_LCDFRR:
+ .dw PFA_DOVARIABLE
+PFA_LCDFRR:
+ .dw 230
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Contrast Control Register
+VE_LCDCCR:
+ .dw $ff06
+ .db "LCDCCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDCCR
+XT_LCDCCR:
+ .dw PFA_DOVARIABLE
+PFA_LCDCCR:
+ .dw 231
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 18
+VE_LCDDR18:
+ .dw $ff07
+ .db "LCDDR18",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR18
+XT_LCDDR18:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR18:
+ .dw 254
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 17
+VE_LCDDR17:
+ .dw $ff07
+ .db "LCDDR17",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR17
+XT_LCDDR17:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR17:
+ .dw 253
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 16
+VE_LCDDR16:
+ .dw $ff07
+ .db "LCDDR16",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR16
+XT_LCDDR16:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR16:
+ .dw 252
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 15
+VE_LCDDR15:
+ .dw $ff07
+ .db "LCDDR15",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR15
+XT_LCDDR15:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR15:
+ .dw 251
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 13
+VE_LCDDR13:
+ .dw $ff07
+ .db "LCDDR13",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR13
+XT_LCDDR13:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR13:
+ .dw 249
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 12
+VE_LCDDR12:
+ .dw $ff07
+ .db "LCDDR12",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR12
+XT_LCDDR12:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR12:
+ .dw 248
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 11
+VE_LCDDR11:
+ .dw $ff07
+ .db "LCDDR11",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR11
+XT_LCDDR11:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR11:
+ .dw 247
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 10
+VE_LCDDR10:
+ .dw $ff07
+ .db "LCDDR10",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR10
+XT_LCDDR10:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR10:
+ .dw 246
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 8
+VE_LCDDR8:
+ .dw $ff06
+ .db "LCDDR8"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR8
+XT_LCDDR8:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR8:
+ .dw 244
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 7
+VE_LCDDR7:
+ .dw $ff06
+ .db "LCDDR7"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR7
+XT_LCDDR7:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR7:
+ .dw 243
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 6
+VE_LCDDR6:
+ .dw $ff06
+ .db "LCDDR6"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR6
+XT_LCDDR6:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR6:
+ .dw 242
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 5
+VE_LCDDR5:
+ .dw $ff06
+ .db "LCDDR5"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR5
+XT_LCDDR5:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR5:
+ .dw 241
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 3
+VE_LCDDR3:
+ .dw $ff06
+ .db "LCDDR3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR3
+XT_LCDDR3:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR3:
+ .dw 239
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 2
+VE_LCDDR2:
+ .dw $ff06
+ .db "LCDDR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR2
+XT_LCDDR2:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR2:
+ .dw 238
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 1
+VE_LCDDR1:
+ .dw $ff06
+ .db "LCDDR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR1
+XT_LCDDR1:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR1:
+ .dw 237
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 0
+VE_LCDDR0:
+ .dw $ff06
+ .db "LCDDR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR0
+XT_LCDDR0:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR0:
+ .dw 236
+
+.endif
+.if WANT_USI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USI Data Register
+VE_USIDR:
+ .dw $ff05
+ .db "USIDR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USIDR
+XT_USIDR:
+ .dw PFA_DOVARIABLE
+PFA_USIDR:
+ .dw 186
+; ( -- addr ) System Constant
+; R( -- )
+; USI Status Register
+VE_USISR:
+ .dw $ff05
+ .db "USISR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USISR
+XT_USISR:
+ .dw PFA_DOVARIABLE
+PFA_USISR:
+ .dw 185
+; ( -- addr ) System Constant
+; R( -- )
+; USI Control Register
+VE_USICR:
+ .dw $ff05
+ .db "USICR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USICR
+XT_USICR:
+ .dw PFA_DOVARIABLE
+PFA_USICR:
+ .dw 184
+
+.endif
+.if WANT_AD_CONVERTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC multiplexer Selection Register
+VE_ADMUX:
+ .dw $ff05
+ .db "ADMUX",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADMUX
+XT_ADMUX:
+ .dw PFA_DOVARIABLE
+PFA_ADMUX:
+ .dw 124
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register
+VE_ADCSRA:
+ .dw $ff06
+ .db "ADCSRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRA
+XT_ADCSRA:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRA:
+ .dw 122
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register Bytes
+VE_ADC:
+ .dw $ff03
+ .db "ADC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADC
+XT_ADC:
+ .dw PFA_DOVARIABLE
+PFA_ADC:
+ .dw 120
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 0
+VE_DIDR0:
+ .dw $ff05
+ .db "DIDR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR0
+XT_DIDR0:
+ .dw PFA_DOVARIABLE
+PFA_DIDR0:
+ .dw 126
+
+.endif
+.if WANT_BOOT_LOAD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control Register
+VE_SPMCSR:
+ .dw $ff06
+ .db "SPMCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCSR
+XT_SPMCSR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCSR:
+ .dw 87
+
+.endif
+.if WANT_USART0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR0:
+ .dw $ff04
+ .db "UDR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR0
+XT_UDR0:
+ .dw PFA_DOVARIABLE
+PFA_UDR0:
+ .dw 198
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR0A:
+ .dw $ff06
+ .db "UCSR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0A
+XT_UCSR0A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0A:
+ .dw 192
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR0B:
+ .dw $ff06
+ .db "UCSR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0B
+XT_UCSR0B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0B:
+ .dw 193
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR0C:
+ .dw $ff06
+ .db "UCSR0C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0C
+XT_UCSR0C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0C:
+ .dw 194
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Bytes
+VE_UBRR0:
+ .dw $ff05
+ .db "UBRR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR0
+XT_UBRR0:
+ .dw PFA_DOVARIABLE
+PFA_UBRR0:
+ .dw 196
+
+.endif
+.if WANT_PORTG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Data Register
+VE_PORTG:
+ .dw $ff05
+ .db "PORTG",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTG
+XT_PORTG:
+ .dw PFA_DOVARIABLE
+PFA_PORTG:
+ .dw 52
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Data Direction Register
+VE_DDRG:
+ .dw $ff04
+ .db "DDRG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRG
+XT_DDRG:
+ .dw PFA_DOVARIABLE
+PFA_DDRG:
+ .dw 51
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Input Pins
+VE_PING:
+ .dw $ff04
+ .db "PING"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PING
+XT_PING:
+ .dw PFA_DOVARIABLE
+PFA_PING:
+ .dw 50
+
+.endif
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register
+VE_EICRA:
+ .dw $ff05
+ .db "EICRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRA
+XT_EICRA:
+ .dw PFA_DOVARIABLE
+PFA_EICRA:
+ .dw 105
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Mask Register
+VE_EIMSK:
+ .dw $ff05
+ .db "EIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIMSK
+XT_EIMSK:
+ .dw PFA_DOVARIABLE
+PFA_EIMSK:
+ .dw 61
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Flag Register
+VE_EIFR:
+ .dw $ff04
+ .db "EIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIFR
+XT_EIFR:
+ .dw PFA_DOVARIABLE
+PFA_EIFR:
+ .dw 60
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 1
+VE_PCMSK1:
+ .dw $ff06
+ .db "PCMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK1
+XT_PCMSK1:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK1:
+ .dw 108
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 0
+VE_PCMSK0:
+ .dw $ff06
+ .db "PCMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK0
+XT_PCMSK0:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK0:
+ .dw 107
+
+.endif
+.if WANT_CPU == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw 95
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer
+VE_SP:
+ .dw $ff02
+ .db "SP"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SP
+XT_SP:
+ .dw PFA_DOVARIABLE
+PFA_SP:
+ .dw 93
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Calibration Value
+VE_OSCCAL:
+ .dw $ff06
+ .db "OSCCAL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSCCAL
+XT_OSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_OSCCAL:
+ .dw 102
+; ( -- addr ) System Constant
+; R( -- )
+; Clock Prescale Register
+VE_CLKPR:
+ .dw $ff05
+ .db "CLKPR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKPR
+XT_CLKPR:
+ .dw PFA_DOVARIABLE
+PFA_CLKPR:
+ .dw 97
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register
+VE_PRR:
+ .dw $ff03
+ .db "PRR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR
+XT_PRR:
+ .dw PFA_DOVARIABLE
+PFA_PRR:
+ .dw 100
+; ( -- addr ) System Constant
+; R( -- )
+; Sleep Mode Control Register
+VE_SMCR:
+ .dw $ff04
+ .db "SMCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SMCR
+XT_SMCR:
+ .dw PFA_DOVARIABLE
+PFA_SMCR:
+ .dw 83
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 2
+VE_GPIOR2:
+ .dw $ff06
+ .db "GPIOR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR2
+XT_GPIOR2:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR2:
+ .dw 75
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 1
+VE_GPIOR1:
+ .dw $ff06
+ .db "GPIOR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR1
+XT_GPIOR1:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR1:
+ .dw 74
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 0
+VE_GPIOR0:
+ .dw $ff06
+ .db "GPIOR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR0
+XT_GPIOR0:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR0:
+ .dw 62
+
+.endif
diff --git a/amforth-6.5/avr8/devices/atmega169a/device.py b/amforth-6.5/avr8/devices/atmega169a/device.py
new file mode 100644
index 0000000..ad1432d
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega169a/device.py
@@ -0,0 +1,359 @@
+# Generated Automatically
+
+# Partname ATmega169A
+
+MCUREGS = {
+# Interrupt Vectors
+ 'INT0Addr' : '#2', # External Interrupt Request 0
+ 'PCINT0Addr' : '#4', # Pin Change Interrupt Request 0
+ 'PCINT1Addr' : '#6', # Pin Change Interrupt Request 1
+ 'TIMER2_COMPAddr' : '#8', # Timer/Counter2 Compare Match
+ 'TIMER2_OVFAddr' : '#10', # Timer/Counter2 Overflow
+ 'TIMER1_CAPTAddr' : '#12', # Timer/Counter1 Capture Event
+ 'TIMER1_COMPAAddr' : '#14', # Timer/Counter1 Compare Match A
+ 'TIMER1_COMPBAddr' : '#16', # Timer/Counter Compare Match B
+ 'TIMER1_OVFAddr' : '#18', # Timer/Counter1 Overflow
+ 'TIMER0_COMPAddr' : '#20', # Timer/Counter0 Compare Match
+ 'TIMER0_OVFAddr' : '#22', # Timer/Counter0 Overflow
+ 'SPI_STCAddr' : '#24', # SPI Serial Transfer Complete
+ 'USART0_RXAddr' : '#26', # USART0, Rx Complete
+ 'USART0_UDREAddr' : '#28', # USART0 Data register Empty
+ 'USART0_TXAddr' : '#30', # USART0, Tx Complete
+ 'USI_STARTAddr' : '#32', # USI Start Condition
+ 'USI_OVERFLOWAddr' : '#34', # USI Overflow
+ 'ANALOG_COMPAddr' : '#36', # Analog Comparator
+ 'ADCAddr' : '#38', # ADC Conversion Complete
+ 'EE_READYAddr' : '#40', # EEPROM Ready
+ 'SPM_READYAddr' : '#42', # Store Program Memory Read
+ 'LCDAddr' : '#44', # LCD Start of Frame
+
+# Module TIMER_COUNTER_0
+ 'TCCR0A' : '$44', # Timer/Counter0 Control Registe
+ 'TCCR0A_FOC0A': '$80', # Force Output Compare
+ 'TCCR0A_WGM00': '$40', # Waveform Generation Mode 0
+ 'TCCR0A_COM0A': '$30', # Compare Match Output Modes
+ 'TCCR0A_WGM01': '$8', # Waveform Generation Mode 1
+ 'TCCR0A_CS0': '$7', # Clock Selects
+ 'TCNT0' : '$46', # Timer/Counter0
+ 'OCR0A' : '$47', # Timer/Counter0 Output Compare
+ 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
+ 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
+ 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
+ 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
+ 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
+ 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Control Register
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSR310': '$1', # Prescaler Reset Timer/Counter1
+
+# Module TIMER_COUNTER_1
+ 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
+ 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
+ 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
+ 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
+ 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
+ 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
+ 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
+ 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
+ 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
+ 'TCCR1C' : '$82', # Timer/Counter 1 Control Regist
+ 'TCCR1C_FOC1A': '$80', # Force Output Compare 1A
+ 'TCCR1C_FOC1B': '$40', # Force Output Compare 1B
+ 'TCNT1' : '$84', # Timer/Counter1 Bytes
+ 'OCR1A' : '$88', # Timer/Counter1 Output Compare
+ 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
+ 'ICR1' : '$86', # Timer/Counter1 Input Capture R
+ 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
+ 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
+ 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
+ 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
+ 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
+ 'TIFR1' : '$36', # Timer/Counter1 Interrupt Flag
+ 'TIFR1_ICF1': '$20', # Input Capture Flag 1
+ 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
+ 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
+ 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
+
+# Module TIMER_COUNTER_2
+ 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
+ 'TCCR2A_FOC2A': '$80', # Force Output Compare A
+ 'TCCR2A_WGM20': '$40', # Waveform Generation Mode
+ 'TCCR2A_COM2A': '$30', # Compare Output Mode bits
+ 'TCCR2A_WGM21': '$8', # Waveform Generation Mode
+ 'TCCR2A_CS2': '$7', # Clock Select bits
+ 'TCNT2' : '$b2', # Timer/Counter2
+ 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
+ 'TIMSK2' : '$70', # Timer/Counter2 Interrupt Mask
+ 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
+ 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
+ 'TIFR2' : '$37', # Timer/Counter2 Interrupt Flag
+ 'TIFR2_OCF2A': '$2', # Timer/Counter2 Output Compare
+ 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_PSR2': '$2', # Prescaler Reset Timer/Counter2
+ 'ASSR' : '$b6', # Asynchronous Status Register
+ 'ASSR_EXCLK': '$10', # Enable External Clock Interrup
+ 'ASSR_AS2': '$8', # AS2: Asynchronous Timer/Counte
+ 'ASSR_TCN2UB': '$4', # TCN2UB: Timer/Counter2 Update
+ 'ASSR_OCR2UB': '$2', # Output Compare Register2 Updat
+ 'ASSR_TCR2UB': '$1', # TCR2UB: Timer/Counter Control
+
+# Module WATCHDOG
+ 'WDTCR' : '$60', # Watchdog Timer Control Registe
+ 'WDTCR_WDCE': '$10', # Watchdog Change Enable
+ 'WDTCR_WDE': '$8', # Watch Dog Enable
+ 'WDTCR_WDP': '$7', # Watch Dog Timer Prescaler bits
+
+# Module EEPROM
+ 'EEAR' : '$41', # EEPROM Address Register Bytes
+ 'EEDR' : '$40', # EEPROM Data Register
+ 'EECR' : '$3f', # EEPROM Control Register
+ 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
+ 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
+ 'EECR_EEWE': '$2', # EEPROM Write Enable
+ 'EECR_EERE': '$1', # EEPROM Read Enable
+
+# Module SPI
+ 'SPCR' : '$4c', # SPI Control Register
+ 'SPCR_SPIE': '$80', # SPI Interrupt Enable
+ 'SPCR_SPE': '$40', # SPI Enable
+ 'SPCR_DORD': '$20', # Data Order
+ 'SPCR_MSTR': '$10', # Master/Slave Select
+ 'SPCR_CPOL': '$8', # Clock polarity
+ 'SPCR_CPHA': '$4', # Clock Phase
+ 'SPCR_SPR': '$3', # SPI Clock Rate Selects
+ 'SPSR' : '$4d', # SPI Status Register
+ 'SPSR_SPIF': '$80', # SPI Interrupt Flag
+ 'SPSR_WCOL': '$40', # Write Collision Flag
+ 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
+ 'SPDR' : '$4e', # SPI Data Register
+
+# Module PORTA
+ 'PORTA' : '$22', # Port A Data Register
+ 'DDRA' : '$21', # Port A Data Direction Register
+ 'PINA' : '$20', # Port A Input Pins
+
+# Module PORTB
+ 'PORTB' : '$25', # Port B Data Register
+ 'DDRB' : '$24', # Port B Data Direction Register
+ 'PINB' : '$23', # Port B Input Pins
+
+# Module PORTC
+ 'PORTC' : '$28', # Port C Data Register
+ 'DDRC' : '$27', # Port C Data Direction Register
+ 'PINC' : '$26', # Port C Input Pins
+
+# Module PORTD
+ 'PORTD' : '$2b', # Port D Data Register
+ 'DDRD' : '$2a', # Port D Data Direction Register
+ 'PIND' : '$29', # Port D Input Pins
+
+# Module ANALOG_COMPARATOR
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
+ 'ACSR' : '$50', # Analog Comparator Control And
+ 'ACSR_ACD': '$80', # Analog Comparator Disable
+ 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
+ 'ACSR_ACO': '$20', # Analog Compare Output
+ 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
+ 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
+ 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
+ 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
+ 'DIDR1' : '$7f', # Digital Input Disable Register
+ 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
+ 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
+
+# Module PORTE
+ 'PORTE' : '$2e', # Data Register, Port E
+ 'DDRE' : '$2d', # Data Direction Register, Port
+ 'PINE' : '$2c', # Input Pins, Port E
+
+# Module PORTF
+ 'PORTF' : '$31', # Data Register, Port F
+ 'DDRF' : '$30', # Data Direction Register, Port
+ 'PINF' : '$2f', # Input Pins, Port F
+
+# Module JTAG
+ 'OCDR' : '$51', # On-Chip Debug Related Register
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_JTD': '$80', # JTAG Interface Disable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+
+# Module LCD
+ 'LCDCRA' : '$e4', # LCD Control Register A
+ 'LCDCRA_LCDEN': '$80', # LCD Enable
+ 'LCDCRA_LCDAB': '$40', # LCD A or B waveform
+ 'LCDCRA_LCDIF': '$10', # LCD Interrupt Flag
+ 'LCDCRA_LCDIE': '$8', # LCD Interrupt Enable
+ 'LCDCRA_LCDBD': '$4', # LCD Buffer Disable
+ 'LCDCRA_LCDCCD': '$2', # LCD Contrast Control Disable
+ 'LCDCRA_LCDBL': '$1', # LCD Blanking
+ 'LCDCRB' : '$e5', # LCD Control and Status Registe
+ 'LCDCRB_LCDCS': '$80', # LCD CLock Select
+ 'LCDCRB_LCD2B': '$40', # LCD 1/2 Bias Select
+ 'LCDCRB_LCDMUX': '$30', # LCD Mux Selects
+ 'LCDCRB_LCDPM': '$7', # LCD Port Masks
+ 'LCDFRR' : '$e6', # LCD Frame Rate Register
+ 'LCDFRR_LCDPS': '$70', # LCD Prescaler Selects
+ 'LCDFRR_LCDCD': '$7', # LCD Clock Dividers
+ 'LCDCCR' : '$e7', # LCD Contrast Control Register
+ 'LCDCCR_LCDDC': '$e0', # LCD Display Configuration Bits
+ 'LCDCCR_LCDMDT': '$10', # LCD Maximum Drive Time
+ 'LCDCCR_LCDCC': '$f', # LCD Contrast Controls
+ 'LCDDR18' : '$fe', # LCD Data Register 18
+ 'LCDDR17' : '$fd', # LCD Data Register 17
+ 'LCDDR16' : '$fc', # LCD Data Register 16
+ 'LCDDR15' : '$fb', # LCD Data Register 15
+ 'LCDDR13' : '$f9', # LCD Data Register 13
+ 'LCDDR12' : '$f8', # LCD Data Register 12
+ 'LCDDR11' : '$f7', # LCD Data Register 11
+ 'LCDDR10' : '$f6', # LCD Data Register 10
+ 'LCDDR8' : '$f4', # LCD Data Register 8
+ 'LCDDR7' : '$f3', # LCD Data Register 7
+ 'LCDDR6' : '$f2', # LCD Data Register 6
+ 'LCDDR5' : '$f1', # LCD Data Register 5
+ 'LCDDR3' : '$ef', # LCD Data Register 3
+ 'LCDDR2' : '$ee', # LCD Data Register 2
+ 'LCDDR1' : '$ed', # LCD Data Register 1
+ 'LCDDR0' : '$ec', # LCD Data Register 0
+
+# Module USI
+ 'USIDR' : '$ba', # USI Data Register
+ 'USISR' : '$b9', # USI Status Register
+ 'USISR_USISIF': '$80', # Start Condition Interrupt Flag
+ 'USISR_USIOIF': '$40', # Counter Overflow Interrupt Fla
+ 'USISR_USIPF': '$20', # Stop Condition Flag
+ 'USISR_USIDC': '$10', # Data Output Collision
+ 'USISR_USICNT': '$f', # USI Counter Value Bits
+ 'USICR' : '$b8', # USI Control Register
+ 'USICR_USISIE': '$80', # Start Condition Interrupt Enab
+ 'USICR_USIOIE': '$40', # Counter Overflow Interrupt Ena
+ 'USICR_USIWM': '$30', # USI Wire Mode Bits
+ 'USICR_USICS': '$c', # USI Clock Source Select Bits
+ 'USICR_USICLK': '$2', # Clock Strobe
+ 'USICR_USITC': '$1', # Toggle Clock Port Pin
+
+# Module AD_CONVERTER
+ 'ADMUX' : '$7c', # The ADC multiplexer Selection
+ 'ADMUX_REFS': '$c0', # Reference Selection Bits
+ 'ADMUX_ADLAR': '$20', # Left Adjust Result
+ 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
+ 'ADCSRA' : '$7a', # The ADC Control and Status reg
+ 'ADCSRA_ADEN': '$80', # ADC Enable
+ 'ADCSRA_ADSC': '$40', # ADC Start Conversion
+ 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
+ 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
+ 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
+ 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
+ 'ADC' : '$78', # ADC Data Register Bytes
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Sources
+ 'DIDR0' : '$7e', # Digital Input Disable Register
+ 'DIDR0_ADC7D': '$80', # ADC7 Digital input Disable
+ 'DIDR0_ADC6D': '$40', # ADC6 Digital input Disable
+ 'DIDR0_ADC5D': '$20', # ADC5 Digital input Disable
+ 'DIDR0_ADC4D': '$10', # ADC4 Digital input Disable
+ 'DIDR0_ADC3D': '$8', # ADC3 Digital input Disable
+ 'DIDR0_ADC2D': '$4', # ADC2 Digital input Disable
+ 'DIDR0_ADC1D': '$2', # ADC1 Digital input Disable
+ 'DIDR0_ADC0D': '$1', # ADC0 Digital input Disable
+
+# Module BOOT_LOAD
+ 'SPMCSR' : '$57', # Store Program Memory Control R
+ 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
+ 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
+ 'SPMCSR_RWWSRE': '$10', # Read While Write section read
+ 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
+ 'SPMCSR_PGWRT': '$4', # Page Write
+ 'SPMCSR_PGERS': '$2', # Page Erase
+ 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
+
+# Module USART0
+ 'UDR0' : '$c6', # USART I/O Data Register
+ 'UCSR0A' : '$c0', # USART Control and Status Regis
+ 'UCSR0A_RXC0': '$80', # USART Receive Complete
+ 'UCSR0A_TXC0': '$40', # USART Transmit Complete
+ 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
+ 'UCSR0A_FE0': '$10', # Framing Error
+ 'UCSR0A_DOR0': '$8', # Data OverRun
+ 'UCSR0A_UPE0': '$4', # USART Parity Error
+ 'UCSR0A_U2X0': '$2', # Double the USART Transmission
+ 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
+ 'UCSR0B' : '$c1', # USART Control and Status Regis
+ 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
+ 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
+ 'UCSR0B_UDRIE0': '$20', # USART Data Register Empty Inte
+ 'UCSR0B_RXEN0': '$10', # Receiver Enable
+ 'UCSR0B_TXEN0': '$8', # Transmitter Enable
+ 'UCSR0B_UCSZ02': '$4', # Character Size
+ 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
+ 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
+ 'UCSR0C' : '$c2', # USART Control and Status Regis
+ 'UCSR0C_UMSEL0': '$40', # USART Mode Select
+ 'UCSR0C_UPM0': '$30', # Parity Mode Bits
+ 'UCSR0C_USBS0': '$8', # Stop Bit Select
+ 'UCSR0C_UCSZ0': '$6', # Character Size
+ 'UCSR0C_UCPOL0': '$1', # Clock Polarity
+ 'UBRR0' : '$c4', # USART Baud Rate Register Byte
+
+# Module PORTG
+ 'PORTG' : '$34', # Port G Data Register
+ 'DDRG' : '$33', # Port G Data Direction Register
+ 'PING' : '$32', # Port G Input Pins
+
+# Module EXTERNAL_INTERRUPT
+ 'EICRA' : '$69', # External Interrupt Control Reg
+ 'EICRA_ISC01': '$2', # External Interrupt Sense Contr
+ 'EICRA_ISC00': '$1', # External Interrupt Sense Contr
+ 'EIMSK' : '$3d', # External Interrupt Mask Regist
+ 'EIMSK_PCIE': '$30', # Pin Change Interrupt Enables
+ 'EIMSK_INT0': '$1', # External Interrupt Request 0 E
+ 'EIFR' : '$3c', # External Interrupt Flag Regist
+ 'EIFR_PCIF': '$30', # Pin Change Interrupt Flags
+ 'EIFR_INTF0': '$1', # External Interrupt Flag 0
+ 'PCMSK1' : '$6c', # Pin Change Mask Register 1
+ 'PCMSK1_PCINT': '$ff', # Pin Change Enable Masks
+ 'PCMSK0' : '$6b', # Pin Change Mask Register 0
+ 'PCMSK0_PCINT': '$ff', # Pin Change Enable Masks
+
+# Module CPU
+ 'SREG' : '$5f', # Status Register
+ 'SREG_I': '$80', # Global Interrupt Enable
+ 'SREG_T': '$40', # Bit Copy Storage
+ 'SREG_H': '$20', # Half Carry Flag
+ 'SREG_S': '$10', # Sign Bit
+ 'SREG_V': '$8', # Two's Complement Overflow Flag
+ 'SREG_N': '$4', # Negative Flag
+ 'SREG_Z': '$2', # Zero Flag
+ 'SREG_C': '$1', # Carry Flag
+ 'SP' : '$5d', # Stack Pointer
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_PUD': '$10', # Pull-up disable
+ 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
+ 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+ 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
+ 'MCUSR_BORF': '$4', # Brown-out Reset Flag
+ 'MCUSR_EXTRF': '$2', # External Reset Flag
+ 'MCUSR_PORF': '$1', # Power-on reset flag
+ 'OSCCAL' : '$66', # Oscillator Calibration Value
+ 'CLKPR' : '$61', # Clock Prescale Register
+ 'CLKPR_CLKPCE': '$80', # Clock Prescaler Change Enable
+ 'CLKPR_CLKPS': '$f', # Clock Prescaler Select Bits
+ 'PRR' : '$64', # Power Reduction Register
+ 'PRR_PRLCD': '$10', # Power Reduction LCD
+ 'PRR_PRTIM1': '$8', # Power Reduction Timer/Counter1
+ 'PRR_PRSPI': '$4', # Power Reduction Serial Periphe
+ 'PRR_PRUSART0': '$2', # Power Reduction USART
+ 'PRR_PRADC': '$1', # Power Reduction ADC
+ 'SMCR' : '$53', # Sleep Mode Control Register
+ 'SMCR_SM': '$e', # Sleep Mode Select bits
+ 'SMCR_SE': '$1', # Sleep Enable
+ 'GPIOR2' : '$4b', # General Purpose IO Register 2
+ 'GPIOR1' : '$4a', # General Purpose IO Register 1
+ 'GPIOR0' : '$3e', # General Purpose IO Register 0
+
+ '__amforth_dummy':'0'
+}
diff --git a/amforth-6.5/avr8/devices/atmega169a/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega169a/words/no-jtag.asm
new file mode 100644
index 0000000..352a4bb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega169a/words/no-jtag.asm
@@ -0,0 +1,14 @@
+; ( -- )
+; ( -- )
+; MCU
+; disable jtag at runtime
+VE_NOJTAG:
+ .dw $FF05
+ .db "-jtag",0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOJTAG
+XT_NOJTAG:
+ .dw PFA_NOJTAG
+PFA_NOJTAG:
+
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega169a/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega169a/words/no-wdt.asm
new file mode 100644
index 0000000..4a12261
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega169a/words/no-wdt.asm
@@ -0,0 +1,22 @@
+; ( -- )
+; MCU
+; disable watch dog timer at runtime
+VE_NOWDT:
+ .dw $ff04
+ .db "-wdt"
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOWDT
+XT_NOWDT:
+ .dw PFA_NOWDT
+PFA_NOWDT:
+
+; Reset WDT
+ wdr
+; Write logical one to WDTOE and WDE
+ in_ temp1, WDTCR
+ ori temp1, (1<<WDTOE)|(1<<WDE)
+ out WDTCR, temp1
+; Turn off WDT
+ ldi temp1, (0<<WDE)
+ out_ WDTCR, temp1
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega169a/words/sleep.asm b/amforth-6.5/avr8/devices/atmega169a/words/sleep.asm
new file mode 100644
index 0000000..256249c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega169a/words/sleep.asm
@@ -0,0 +1,19 @@
+; ( mode -- )
+; MCU
+; put the controller into the specified sleep mode
+VE_SLEEP:
+ .dw $ff05
+ .db "sleep", 0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_SLEEP
+XT_SLEEP:
+ .dw PFA_SLEEP
+PFA_SLEEP:
+ andi tosl, 7 ; leave only legal mode bits
+ lsl tosl ; move to correct location (bits 3-1)
+ ori tosl, 1 ; set the SE bit
+ out_ SMCR, tosl ; set the sleep config
+ sleep ; nighty-night
+ out_ SMCR, zerol ; 0 protects against accidental sleeps
+ loadtos ; pop argument from stack
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega169p/atmega169p.frt b/amforth-6.5/avr8/devices/atmega169p/atmega169p.frt
new file mode 100644
index 0000000..e4cc0e8
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega169p/atmega169p.frt
@@ -0,0 +1,319 @@
+\ Partname: ATmega169P
+\ generated automatically
+
+\ TIMER_COUNTER_0
+&68 constant TCCR0A \ Timer/Counter0 Control Register
+ $80 constant TCCR0A_FOC0A \ Force Output Compare
+ $40 constant TCCR0A_WGM00 \ Waveform Generation Mode 0
+ $30 constant TCCR0A_COM0A \ Compare Match Output Modes
+ $08 constant TCCR0A_WGM01 \ Waveform Generation Mode 1
+ $07 constant TCCR0A_CS0 \ Clock Selects
+&70 constant TCNT0 \ Timer/Counter0
+&71 constant OCR0A \ Timer/Counter0 Output Compare Register
+&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
+ $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match Interrupt Enable
+ $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
+&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
+ $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0
+ $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
+&67 constant GTCCR \ General Timer/Control Register
+ $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
+ $01 constant GTCCR_PSR310 \ Prescaler Reset Timer/Counter1 and Timer/Counter0
+\ TIMER_COUNTER_1
+&128 constant TCCR1A \ Timer/Counter1 Control Register A
+ $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
+ $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
+ $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
+&129 constant TCCR1B \ Timer/Counter1 Control Register B
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
+ $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
+&130 constant TCCR1C \ Timer/Counter 1 Control Register C
+ $80 constant TCCR1C_FOC1A \ Force Output Compare 1A
+ $40 constant TCCR1C_FOC1B \ Force Output Compare 1B
+&132 constant TCNT1 \ Timer/Counter1 Bytes
+&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
+&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
+&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
+&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
+ $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
+ $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
+ $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
+ $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
+&54 constant TIFR1 \ Timer/Counter1 Interrupt Flag register
+ $20 constant TIFR1_ICF1 \ Input Capture Flag 1
+ $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
+ $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
+ $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
+\ TIMER_COUNTER_2
+&176 constant TCCR2A \ Timer/Counter2 Control Register
+ $80 constant TCCR2A_FOC2A \ Force Output Compare A
+ $40 constant TCCR2A_WGM20 \ Waveform Generation Mode
+ $30 constant TCCR2A_COM2A \ Compare Output Mode bits
+ $08 constant TCCR2A_WGM21 \ Waveform Generation Mode
+ $07 constant TCCR2A_CS2 \ Clock Select bits
+&178 constant TCNT2 \ Timer/Counter2
+&179 constant OCR2A \ Timer/Counter2 Output Compare Register
+&112 constant TIMSK2 \ Timer/Counter2 Interrupt Mask register
+ $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match Interrupt Enable
+ $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
+&55 constant TIFR2 \ Timer/Counter2 Interrupt Flag Register
+ $02 constant TIFR2_OCF2A \ Timer/Counter2 Output Compare Flag 2
+ $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
+&182 constant ASSR \ Asynchronous Status Register
+ $10 constant ASSR_EXCLK \ Enable External Clock Interrupt
+ $08 constant ASSR_AS2 \ AS2: Asynchronous Timer/Counter2
+ $04 constant ASSR_TCN2UB \ TCN2UB: Timer/Counter2 Update Busy
+ $02 constant ASSR_OCR2UB \ Output Compare Register2 Update Busy
+ $01 constant ASSR_TCR2UB \ TCR2UB: Timer/Counter Control Register2 Update Busy
+\ WATCHDOG
+&96 constant WDTCR \ Watchdog Timer Control Register
+ $10 constant WDTCR_WDCE \ Watchdog Change Enable
+ $08 constant WDTCR_WDE \ Watch Dog Enable
+ $07 constant WDTCR_WDP \ Watch Dog Timer Prescaler bits
+\ EEPROM
+&65 constant EEAR \ EEPROM Address Register Bytes
+&64 constant EEDR \ EEPROM Data Register
+&63 constant EECR \ EEPROM Control Register
+ $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
+ $04 constant EECR_EEMWE \ EEPROM Master Write Enable
+ $02 constant EECR_EEWE \ EEPROM Write Enable
+ $01 constant EECR_EERE \ EEPROM Read Enable
+\ SPI
+&76 constant SPCR \ SPI Control Register
+ $80 constant SPCR_SPIE \ SPI Interrupt Enable
+ $40 constant SPCR_SPE \ SPI Enable
+ $20 constant SPCR_DORD \ Data Order
+ $10 constant SPCR_MSTR \ Master/Slave Select
+ $08 constant SPCR_CPOL \ Clock polarity
+ $04 constant SPCR_CPHA \ Clock Phase
+ $03 constant SPCR_SPR \ SPI Clock Rate Selects
+&77 constant SPSR \ SPI Status Register
+ $80 constant SPSR_SPIF \ SPI Interrupt Flag
+ $40 constant SPSR_WCOL \ Write Collision Flag
+ $01 constant SPSR_SPI2X \ Double SPI Speed Bit
+&78 constant SPDR \ SPI Data Register
+\ PORTA
+&34 constant PORTA \ Port A Data Register
+&33 constant DDRA \ Port A Data Direction Register
+&32 constant PINA \ Port A Input Pins
+\ PORTB
+&37 constant PORTB \ Port B Data Register
+&36 constant DDRB \ Port B Data Direction Register
+&35 constant PINB \ Port B Input Pins
+\ PORTC
+&40 constant PORTC \ Port C Data Register
+&39 constant DDRC \ Port C Data Direction Register
+&38 constant PINC \ Port C Input Pins
+\ PORTD
+&43 constant PORTD \ Port D Data Register
+&42 constant DDRD \ Port D Data Direction Register
+&41 constant PIND \ Port D Input Pins
+\ ANALOG_COMPARATOR
+&123 constant ADCSRB \ ADC Control and Status Register B
+ $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer Enable
+&80 constant ACSR \ Analog Comparator Control And Status Register
+ $80 constant ACSR_ACD \ Analog Comparator Disable
+ $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
+ $20 constant ACSR_ACO \ Analog Compare Output
+ $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
+ $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
+ $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
+ $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
+&127 constant DIDR1 \ Digital Input Disable Register 1
+ $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
+ $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
+\ PORTE
+&46 constant PORTE \ Data Register, Port E
+&45 constant DDRE \ Data Direction Register, Port E
+&44 constant PINE \ Input Pins, Port E
+\ PORTF
+&49 constant PORTF \ Data Register, Port F
+&48 constant DDRF \ Data Direction Register, Port F
+&47 constant PINF \ Input Pins, Port F
+\ JTAG
+&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
+&85 constant MCUCR \ MCU Control Register
+ $80 constant MCUCR_JTD \ JTAG Interface Disable
+&84 constant MCUSR \ MCU Status Register
+ $10 constant MCUSR_JTRF \ JTAG Reset Flag
+\ LCD
+&228 constant LCDCRA \ LCD Control Register A
+ $80 constant LCDCRA_LCDEN \ LCD Enable
+ $40 constant LCDCRA_LCDAB \ LCD A or B waveform
+ $10 constant LCDCRA_LCDIF \ LCD Interrupt Flag
+ $08 constant LCDCRA_LCDIE \ LCD Interrupt Enable
+ $04 constant LCDCRA_LCDBD \ LCD Buffer Disable
+ $02 constant LCDCRA_LCDCCD \ LCD Contrast Control Disable
+ $01 constant LCDCRA_LCDBL \ LCD Blanking
+&229 constant LCDCRB \ LCD Control and Status Register B
+ $80 constant LCDCRB_LCDCS \ LCD CLock Select
+ $40 constant LCDCRB_LCD2B \ LCD 1/2 Bias Select
+ $30 constant LCDCRB_LCDMUX \ LCD Mux Selects
+ $07 constant LCDCRB_LCDPM \ LCD Port Masks
+&230 constant LCDFRR \ LCD Frame Rate Register
+ $70 constant LCDFRR_LCDPS \ LCD Prescaler Selects
+ $07 constant LCDFRR_LCDCD \ LCD Clock Dividers
+&231 constant LCDCCR \ LCD Contrast Control Register
+ $E0 constant LCDCCR_LCDDC \ LCD Display Configuration Bits
+ $10 constant LCDCCR_LCDMDT \ LCD Maximum Drive Time
+ $0F constant LCDCCR_LCDCC \ LCD Contrast Controls
+&254 constant LCDDR18 \ LCD Data Register 18
+&253 constant LCDDR17 \ LCD Data Register 17
+&252 constant LCDDR16 \ LCD Data Register 16
+&251 constant LCDDR15 \ LCD Data Register 15
+&249 constant LCDDR13 \ LCD Data Register 13
+&248 constant LCDDR12 \ LCD Data Register 12
+&247 constant LCDDR11 \ LCD Data Register 11
+&246 constant LCDDR10 \ LCD Data Register 10
+&244 constant LCDDR8 \ LCD Data Register 8
+&243 constant LCDDR7 \ LCD Data Register 7
+&242 constant LCDDR6 \ LCD Data Register 6
+&241 constant LCDDR5 \ LCD Data Register 5
+&239 constant LCDDR3 \ LCD Data Register 3
+&238 constant LCDDR2 \ LCD Data Register 2
+&237 constant LCDDR1 \ LCD Data Register 1
+&236 constant LCDDR0 \ LCD Data Register 0
+\ EXTERNAL_INTERRUPT
+&105 constant EICRA \ External Interrupt Control Register
+ $02 constant EICRA_ISC01 \ External Interrupt Sense Control 0 Bit 1
+ $01 constant EICRA_ISC00 \ External Interrupt Sense Control 0 Bit 0
+&61 constant EIMSK \ External Interrupt Mask Register
+ $C0 constant EIMSK_PCIE \ Pin Change Interrupt Enables
+ $01 constant EIMSK_INT0 \ External Interrupt Request 0 Enable
+&60 constant EIFR \ External Interrupt Flag Register
+ $C0 constant EIFR_PCIF \ Pin Change Interrupt Flags
+ $01 constant EIFR_INTF0 \ External Interrupt Flag 0
+&108 constant PCMSK1 \ Pin Change Mask Register 1
+ $FF constant PCMSK1_PCINT \ Pin Change Enable Masks
+&107 constant PCMSK0 \ Pin Change Mask Register 0
+ $FF constant PCMSK0_PCINT \ Pin Change Enable Masks
+\ USI
+&186 constant USIDR \ USI Data Register
+&185 constant USISR \ USI Status Register
+ $80 constant USISR_USISIF \ Start Condition Interrupt Flag
+ $40 constant USISR_USIOIF \ Counter Overflow Interrupt Flag
+ $20 constant USISR_USIPF \ Stop Condition Flag
+ $10 constant USISR_USIDC \ Data Output Collision
+ $0F constant USISR_USICNT \ USI Counter Value Bits
+&184 constant USICR \ USI Control Register
+ $80 constant USICR_USISIE \ Start Condition Interrupt Enable
+ $40 constant USICR_USIOIE \ Counter Overflow Interrupt Enable
+ $30 constant USICR_USIWM \ USI Wire Mode Bits
+ $0C constant USICR_USICS \ USI Clock Source Select Bits
+ $02 constant USICR_USICLK \ Clock Strobe
+ $01 constant USICR_USITC \ Toggle Clock Port Pin
+\ AD_CONVERTER
+&124 constant ADMUX \ The ADC multiplexer Selection Register
+ $C0 constant ADMUX_REFS \ Reference Selection Bits
+ $20 constant ADMUX_ADLAR \ Left Adjust Result
+ $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
+&122 constant ADCSRA \ The ADC Control and Status register
+ $80 constant ADCSRA_ADEN \ ADC Enable
+ $40 constant ADCSRA_ADSC \ ADC Start Conversion
+ $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
+ $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
+ $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
+ $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
+&120 constant ADC \ ADC Data Register Bytes
+&126 constant DIDR0 \ Digital Input Disable Register 0
+ $80 constant DIDR0_ADC7D \ ADC7 Digital input Disable
+ $40 constant DIDR0_ADC6D \ ADC6 Digital input Disable
+ $20 constant DIDR0_ADC5D \ ADC5 Digital input Disable
+ $10 constant DIDR0_ADC4D \ ADC4 Digital input Disable
+ $08 constant DIDR0_ADC3D \ ADC3 Digital input Disable
+ $04 constant DIDR0_ADC2D \ ADC2 Digital input Disable
+ $02 constant DIDR0_ADC1D \ ADC1 Digital input Disable
+ $01 constant DIDR0_ADC0D \ ADC0 Digital input Disable
+\ BOOT_LOAD
+&87 constant SPMCSR \ Store Program Memory Control Register
+ $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
+ $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
+ $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
+ $04 constant SPMCSR_PGWRT \ Page Write
+ $02 constant SPMCSR_PGERS \ Page Erase
+ $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
+\ USART0
+&198 constant UDR0 \ USART I/O Data Register
+&192 constant UCSR0A \ USART Control and Status Register A
+ $80 constant UCSR0A_RXC0 \ USART Receive Complete
+ $40 constant UCSR0A_TXC0 \ USART Transmit Complete
+ $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
+ $10 constant UCSR0A_FE0 \ Framing Error
+ $08 constant UCSR0A_DOR0 \ Data OverRun
+ $04 constant UCSR0A_UPE0 \ USART Parity Error
+ $02 constant UCSR0A_U2X0 \ Double the USART Transmission Speed
+ $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
+&193 constant UCSR0B \ USART Control and Status Register B
+ $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
+ $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
+ $20 constant UCSR0B_UDRIE0 \ USART Data Register Empty Interrupt Enable
+ $10 constant UCSR0B_RXEN0 \ Receiver Enable
+ $08 constant UCSR0B_TXEN0 \ Transmitter Enable
+ $04 constant UCSR0B_UCSZ02 \ Character Size
+ $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
+ $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
+&194 constant UCSR0C \ USART Control and Status Register C
+ $40 constant UCSR0C_UMSEL0 \ USART Mode Select
+ $30 constant UCSR0C_UPM0 \ Parity Mode Bits
+ $08 constant UCSR0C_USBS0 \ Stop Bit Select
+ $06 constant UCSR0C_UCSZ0 \ Character Size
+ $01 constant UCSR0C_UCPOL0 \ Clock Polarity
+&196 constant UBRR0 \ USART Baud Rate Register Bytes
+\ CPU
+&95 constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ $08 constant SREG_V \ Two's Complement Overflow Flag
+ $04 constant SREG_N \ Negative Flag
+ $02 constant SREG_Z \ Zero Flag
+ $01 constant SREG_C \ Carry Flag
+&93 constant SP \ Stack Pointer
+&102 constant OSCCAL \ Oscillator Calibration Value
+&97 constant CLKPR \ Clock Prescale Register
+ $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable
+ $0F constant CLKPR_CLKPS \ Clock Prescaler Select Bits
+&100 constant PRR \ Power Reduction Register
+ $10 constant PRR_PRLCD \ Power Reduction LCD
+ $08 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
+ $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
+ $02 constant PRR_PRUSART0 \ Power Reduction USART
+ $01 constant PRR_PRADC \ Power Reduction ADC
+&83 constant SMCR \ Sleep Mode Control Register
+ $0E constant SMCR_SM \ Sleep Mode Select bits
+ $01 constant SMCR_SE \ Sleep Enable
+&75 constant GPIOR2 \ General Purpose IO Register 2
+&74 constant GPIOR1 \ General Purpose IO Register 1
+&62 constant GPIOR0 \ General Purpose IO Register 0
+\ PORTG
+&52 constant PORTG \ Port G Data Register
+&51 constant DDRG \ Port G Data Direction Register
+&50 constant PING \ Port G Input Pins
+
+\ Interrupts
+&2 constant INT0Addr \ External Interrupt Request 0
+&4 constant PCINT0Addr \ Pin Change Interrupt Request 0
+&6 constant PCINT1Addr \ Pin Change Interrupt Request 1
+&8 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
+&10 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
+&12 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+&14 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
+&16 constant TIMER1_COMPBAddr \ Timer/Counter Compare Match B
+&18 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+&20 constant TIMER0_COMPAddr \ Timer/Counter0 Compare Match
+&22 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
+&24 constant SPI__STCAddr \ SPI Serial Transfer Complete
+&26 constant USART0__RXAddr \ USART0, Rx Complete
+&28 constant USART0__UDREAddr \ USART0 Data register Empty
+&30 constant USART0__TXAddr \ USART0, Tx Complete
+&32 constant USI_STARTAddr \ USI Start Condition
+&34 constant USI_OVERFLOWAddr \ USI Overflow
+&36 constant ANALOG_COMPAddr \ Analog Comparator
+&38 constant ADCAddr \ ADC Conversion Complete
+&40 constant EE_READYAddr \ EEPROM Ready
+&42 constant SPM_READYAddr \ Store Program Memory Read
+&44 constant LCDAddr \ LCD Start of Frame
diff --git a/amforth-6.5/avr8/devices/atmega169p/device.asm b/amforth-6.5/avr8/devices/atmega169p/device.asm
new file mode 100644
index 0000000..cbd28a2
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega169p/device.asm
@@ -0,0 +1,109 @@
+; Partname: ATmega169P
+; generated automatically, do not edit
+
+.nolist
+ .include "m169Pdef.inc"
+.list
+
+.equ ramstart = 256
+.equ CELLSIZE = 2
+.macro readflashcell
+ lsl zl
+ rol zh
+ lpm @0, Z+
+ lpm @1, Z+
+.endmacro
+.macro writeflashcell
+ lsl zl
+ rol zh
+.endmacro
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_TIMER_COUNTER_2 = 0
+.set WANT_WATCHDOG = 0
+.set WANT_EEPROM = 0
+.set WANT_SPI = 0
+.set WANT_PORTA = 0
+.set WANT_PORTB = 0
+.set WANT_PORTC = 0
+.set WANT_PORTD = 0
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_PORTE = 0
+.set WANT_PORTF = 0
+.set WANT_JTAG = 0
+.set WANT_LCD = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_USI = 0
+.set WANT_AD_CONVERTER = 0
+.set WANT_BOOT_LOAD = 0
+.set WANT_USART0 = 0
+.set WANT_CPU = 0
+.set WANT_PORTG = 0
+.equ intvecsize = 2 ; please verify; flash size: 16384 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.org 2
+ rcall isr ; External Interrupt Request 0
+.org 4
+ rcall isr ; Pin Change Interrupt Request 0
+.org 6
+ rcall isr ; Pin Change Interrupt Request 1
+.org 8
+ rcall isr ; Timer/Counter2 Compare Match
+.org 10
+ rcall isr ; Timer/Counter2 Overflow
+.org 12
+ rcall isr ; Timer/Counter1 Capture Event
+.org 14
+ rcall isr ; Timer/Counter1 Compare Match A
+.org 16
+ rcall isr ; Timer/Counter Compare Match B
+.org 18
+ rcall isr ; Timer/Counter1 Overflow
+.org 20
+ rcall isr ; Timer/Counter0 Compare Match
+.org 22
+ rcall isr ; Timer/Counter0 Overflow
+.org 24
+ rcall isr ; SPI Serial Transfer Complete
+.org 26
+ rcall isr ; USART0, Rx Complete
+.org 28
+ rcall isr ; USART0 Data register Empty
+.org 30
+ rcall isr ; USART0, Tx Complete
+.org 32
+ rcall isr ; USI Start Condition
+.org 34
+ rcall isr ; USI Overflow
+.org 36
+ rcall isr ; Analog Comparator
+.org 38
+ rcall isr ; ADC Conversion Complete
+.org 40
+ rcall isr ; EEPROM Ready
+.org 42
+ rcall isr ; Store Program Memory Read
+.org 44
+ rcall isr ; LCD Start of Frame
+.equ INTVECTORS = 23
+.nooverlap
+
+; compatability layer (maybe empty)
+.equ EEPE = EEWE
+.equ EEMPE = EEMWE
+
+; controller data area, environment query mcu-info
+mcu_info:
+mcu_ramsize:
+ .dw 1024
+mcu_eepromsize:
+ .dw 512
+mcu_maxdp:
+ .dw 14336
+mcu_numints:
+ .dw 23
+mcu_name:
+ .dw 10
+ .db "ATmega169P"
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega169p/device.inc b/amforth-6.5/avr8/devices/atmega169p/device.inc
new file mode 100644
index 0000000..f4b9135
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega169p/device.inc
@@ -0,0 +1,1293 @@
+; Partname: ATmega169P
+; generated automatically, no not edit
+
+.if WANT_TIMER_COUNTER_0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Control Register
+VE_TCCR0A:
+ .dw $ff06
+ .db "TCCR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0A
+XT_TCCR0A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0A:
+ .dw 68
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw 70
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0A:
+ .dw $ff05
+ .db "OCR0A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0A
+XT_OCR0A:
+ .dw PFA_DOVARIABLE
+PFA_OCR0A:
+ .dw 71
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Mask Register
+VE_TIMSK0:
+ .dw $ff06
+ .db "TIMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK0
+XT_TIMSK0:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK0:
+ .dw 110
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Flag register
+VE_TIFR0:
+ .dw $ff05
+ .db "TIFR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR0
+XT_TIFR0:
+ .dw PFA_DOVARIABLE
+PFA_TIFR0:
+ .dw 53
+; ( -- addr ) System Constant
+; R( -- )
+; General Timer/Control Register
+VE_GTCCR:
+ .dw $ff05
+ .db "GTCCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GTCCR
+XT_GTCCR:
+ .dw PFA_DOVARIABLE
+PFA_GTCCR:
+ .dw 67
+
+.endif
+.if WANT_TIMER_COUNTER_1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw 128
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw 129
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter 1 Control Register C
+VE_TCCR1C:
+ .dw $ff06
+ .db "TCCR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1C
+XT_TCCR1C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1C:
+ .dw 130
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Bytes
+VE_TCNT1:
+ .dw $ff05
+ .db "TCNT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1
+XT_TCNT1:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1:
+ .dw 132
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register A Bytes
+VE_OCR1A:
+ .dw $ff05
+ .db "OCR1A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1A
+XT_OCR1A:
+ .dw PFA_DOVARIABLE
+PFA_OCR1A:
+ .dw 136
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register B Bytes
+VE_OCR1B:
+ .dw $ff05
+ .db "OCR1B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1B
+XT_OCR1B:
+ .dw PFA_DOVARIABLE
+PFA_OCR1B:
+ .dw 138
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Bytes
+VE_ICR1:
+ .dw $ff04
+ .db "ICR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1
+XT_ICR1:
+ .dw PFA_DOVARIABLE
+PFA_ICR1:
+ .dw 134
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Mask Register
+VE_TIMSK1:
+ .dw $ff06
+ .db "TIMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK1
+XT_TIMSK1:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK1:
+ .dw 111
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Flag register
+VE_TIFR1:
+ .dw $ff05
+ .db "TIFR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR1
+XT_TIFR1:
+ .dw PFA_DOVARIABLE
+PFA_TIFR1:
+ .dw 54
+
+.endif
+.if WANT_TIMER_COUNTER_2 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register
+VE_TCCR2A:
+ .dw $ff06
+ .db "TCCR2A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2A
+XT_TCCR2A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2A:
+ .dw 176
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2
+VE_TCNT2:
+ .dw $ff05
+ .db "TCNT2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT2
+XT_TCNT2:
+ .dw PFA_DOVARIABLE
+PFA_TCNT2:
+ .dw 178
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register
+VE_OCR2A:
+ .dw $ff05
+ .db "OCR2A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2A
+XT_OCR2A:
+ .dw PFA_DOVARIABLE
+PFA_OCR2A:
+ .dw 179
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Interrupt Mask register
+VE_TIMSK2:
+ .dw $ff06
+ .db "TIMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK2
+XT_TIMSK2:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK2:
+ .dw 112
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Interrupt Flag Register
+VE_TIFR2:
+ .dw $ff05
+ .db "TIFR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR2
+XT_TIFR2:
+ .dw PFA_DOVARIABLE
+PFA_TIFR2:
+ .dw 55
+; ( -- addr ) System Constant
+; R( -- )
+; Asynchronous Status Register
+VE_ASSR:
+ .dw $ff04
+ .db "ASSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ASSR
+XT_ASSR:
+ .dw PFA_DOVARIABLE
+PFA_ASSR:
+ .dw 182
+
+.endif
+.if WANT_WATCHDOG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCR:
+ .dw $ff05
+ .db "WDTCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCR
+XT_WDTCR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCR:
+ .dw 96
+
+.endif
+.if WANT_EEPROM == 1
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Address Register Bytes
+VE_EEAR:
+ .dw $ff04
+ .db "EEAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEAR
+XT_EEAR:
+ .dw PFA_DOVARIABLE
+PFA_EEAR:
+ .dw 65
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw 64
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw 63
+
+.endif
+.if WANT_SPI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR:
+ .dw $ff04
+ .db "SPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR
+XT_SPCR:
+ .dw PFA_DOVARIABLE
+PFA_SPCR:
+ .dw 76
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR:
+ .dw $ff04
+ .db "SPSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR
+XT_SPSR:
+ .dw PFA_DOVARIABLE
+PFA_SPSR:
+ .dw 77
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR:
+ .dw $ff04
+ .db "SPDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR
+XT_SPDR:
+ .dw PFA_DOVARIABLE
+PFA_SPDR:
+ .dw 78
+
+.endif
+.if WANT_PORTA == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Register
+VE_PORTA:
+ .dw $ff05
+ .db "PORTA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTA
+XT_PORTA:
+ .dw PFA_DOVARIABLE
+PFA_PORTA:
+ .dw 34
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Direction Register
+VE_DDRA:
+ .dw $ff04
+ .db "DDRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRA
+XT_DDRA:
+ .dw PFA_DOVARIABLE
+PFA_DDRA:
+ .dw 33
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Input Pins
+VE_PINA:
+ .dw $ff04
+ .db "PINA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINA
+XT_PINA:
+ .dw PFA_DOVARIABLE
+PFA_PINA:
+ .dw 32
+
+.endif
+.if WANT_PORTB == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw 37
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw 36
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw 35
+
+.endif
+.if WANT_PORTC == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Register
+VE_PORTC:
+ .dw $ff05
+ .db "PORTC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTC
+XT_PORTC:
+ .dw PFA_DOVARIABLE
+PFA_PORTC:
+ .dw 40
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Direction Register
+VE_DDRC:
+ .dw $ff04
+ .db "DDRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRC
+XT_DDRC:
+ .dw PFA_DOVARIABLE
+PFA_DDRC:
+ .dw 39
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Input Pins
+VE_PINC:
+ .dw $ff04
+ .db "PINC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINC
+XT_PINC:
+ .dw PFA_DOVARIABLE
+PFA_PINC:
+ .dw 38
+
+.endif
+.if WANT_PORTD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw 43
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw 42
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw 41
+
+.endif
+.if WANT_ANALOG_COMPARATOR == 1
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Control and Status Register B
+VE_ADCSRB:
+ .dw $ff06
+ .db "ADCSRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRB
+XT_ADCSRB:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRB:
+ .dw 123
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Control And Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw 80
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 1
+VE_DIDR1:
+ .dw $ff05
+ .db "DIDR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR1
+XT_DIDR1:
+ .dw PFA_DOVARIABLE
+PFA_DIDR1:
+ .dw 127
+
+.endif
+.if WANT_PORTE == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port E
+VE_PORTE:
+ .dw $ff05
+ .db "PORTE",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTE
+XT_PORTE:
+ .dw PFA_DOVARIABLE
+PFA_PORTE:
+ .dw 46
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port E
+VE_DDRE:
+ .dw $ff04
+ .db "DDRE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRE
+XT_DDRE:
+ .dw PFA_DOVARIABLE
+PFA_DDRE:
+ .dw 45
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port E
+VE_PINE:
+ .dw $ff04
+ .db "PINE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINE
+XT_PINE:
+ .dw PFA_DOVARIABLE
+PFA_PINE:
+ .dw 44
+
+.endif
+.if WANT_PORTF == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port F
+VE_PORTF:
+ .dw $ff05
+ .db "PORTF",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTF
+XT_PORTF:
+ .dw PFA_DOVARIABLE
+PFA_PORTF:
+ .dw 49
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port F
+VE_DDRF:
+ .dw $ff04
+ .db "DDRF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRF
+XT_DDRF:
+ .dw PFA_DOVARIABLE
+PFA_DDRF:
+ .dw 48
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port F
+VE_PINF:
+ .dw $ff04
+ .db "PINF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINF
+XT_PINF:
+ .dw PFA_DOVARIABLE
+PFA_PINF:
+ .dw 47
+
+.endif
+.if WANT_JTAG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; On-Chip Debug Related Register in I/O Memory
+VE_OCDR:
+ .dw $ff04
+ .db "OCDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCDR
+XT_OCDR:
+ .dw PFA_DOVARIABLE
+PFA_OCDR:
+ .dw 81
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw 85
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Status Register
+VE_MCUSR:
+ .dw $ff05
+ .db "MCUSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUSR
+XT_MCUSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUSR:
+ .dw 84
+
+.endif
+.if WANT_LCD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Control Register A
+VE_LCDCRA:
+ .dw $ff06
+ .db "LCDCRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDCRA
+XT_LCDCRA:
+ .dw PFA_DOVARIABLE
+PFA_LCDCRA:
+ .dw 228
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Control and Status Register B
+VE_LCDCRB:
+ .dw $ff06
+ .db "LCDCRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDCRB
+XT_LCDCRB:
+ .dw PFA_DOVARIABLE
+PFA_LCDCRB:
+ .dw 229
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Frame Rate Register
+VE_LCDFRR:
+ .dw $ff06
+ .db "LCDFRR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDFRR
+XT_LCDFRR:
+ .dw PFA_DOVARIABLE
+PFA_LCDFRR:
+ .dw 230
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Contrast Control Register
+VE_LCDCCR:
+ .dw $ff06
+ .db "LCDCCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDCCR
+XT_LCDCCR:
+ .dw PFA_DOVARIABLE
+PFA_LCDCCR:
+ .dw 231
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 18
+VE_LCDDR18:
+ .dw $ff07
+ .db "LCDDR18",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR18
+XT_LCDDR18:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR18:
+ .dw 254
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 17
+VE_LCDDR17:
+ .dw $ff07
+ .db "LCDDR17",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR17
+XT_LCDDR17:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR17:
+ .dw 253
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 16
+VE_LCDDR16:
+ .dw $ff07
+ .db "LCDDR16",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR16
+XT_LCDDR16:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR16:
+ .dw 252
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 15
+VE_LCDDR15:
+ .dw $ff07
+ .db "LCDDR15",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR15
+XT_LCDDR15:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR15:
+ .dw 251
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 13
+VE_LCDDR13:
+ .dw $ff07
+ .db "LCDDR13",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR13
+XT_LCDDR13:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR13:
+ .dw 249
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 12
+VE_LCDDR12:
+ .dw $ff07
+ .db "LCDDR12",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR12
+XT_LCDDR12:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR12:
+ .dw 248
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 11
+VE_LCDDR11:
+ .dw $ff07
+ .db "LCDDR11",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR11
+XT_LCDDR11:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR11:
+ .dw 247
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 10
+VE_LCDDR10:
+ .dw $ff07
+ .db "LCDDR10",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR10
+XT_LCDDR10:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR10:
+ .dw 246
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 8
+VE_LCDDR8:
+ .dw $ff06
+ .db "LCDDR8"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR8
+XT_LCDDR8:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR8:
+ .dw 244
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 7
+VE_LCDDR7:
+ .dw $ff06
+ .db "LCDDR7"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR7
+XT_LCDDR7:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR7:
+ .dw 243
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 6
+VE_LCDDR6:
+ .dw $ff06
+ .db "LCDDR6"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR6
+XT_LCDDR6:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR6:
+ .dw 242
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 5
+VE_LCDDR5:
+ .dw $ff06
+ .db "LCDDR5"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR5
+XT_LCDDR5:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR5:
+ .dw 241
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 3
+VE_LCDDR3:
+ .dw $ff06
+ .db "LCDDR3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR3
+XT_LCDDR3:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR3:
+ .dw 239
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 2
+VE_LCDDR2:
+ .dw $ff06
+ .db "LCDDR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR2
+XT_LCDDR2:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR2:
+ .dw 238
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 1
+VE_LCDDR1:
+ .dw $ff06
+ .db "LCDDR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR1
+XT_LCDDR1:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR1:
+ .dw 237
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 0
+VE_LCDDR0:
+ .dw $ff06
+ .db "LCDDR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR0
+XT_LCDDR0:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR0:
+ .dw 236
+
+.endif
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register
+VE_EICRA:
+ .dw $ff05
+ .db "EICRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRA
+XT_EICRA:
+ .dw PFA_DOVARIABLE
+PFA_EICRA:
+ .dw 105
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Mask Register
+VE_EIMSK:
+ .dw $ff05
+ .db "EIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIMSK
+XT_EIMSK:
+ .dw PFA_DOVARIABLE
+PFA_EIMSK:
+ .dw 61
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Flag Register
+VE_EIFR:
+ .dw $ff04
+ .db "EIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIFR
+XT_EIFR:
+ .dw PFA_DOVARIABLE
+PFA_EIFR:
+ .dw 60
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 1
+VE_PCMSK1:
+ .dw $ff06
+ .db "PCMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK1
+XT_PCMSK1:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK1:
+ .dw 108
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 0
+VE_PCMSK0:
+ .dw $ff06
+ .db "PCMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK0
+XT_PCMSK0:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK0:
+ .dw 107
+
+.endif
+.if WANT_USI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USI Data Register
+VE_USIDR:
+ .dw $ff05
+ .db "USIDR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USIDR
+XT_USIDR:
+ .dw PFA_DOVARIABLE
+PFA_USIDR:
+ .dw 186
+; ( -- addr ) System Constant
+; R( -- )
+; USI Status Register
+VE_USISR:
+ .dw $ff05
+ .db "USISR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USISR
+XT_USISR:
+ .dw PFA_DOVARIABLE
+PFA_USISR:
+ .dw 185
+; ( -- addr ) System Constant
+; R( -- )
+; USI Control Register
+VE_USICR:
+ .dw $ff05
+ .db "USICR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USICR
+XT_USICR:
+ .dw PFA_DOVARIABLE
+PFA_USICR:
+ .dw 184
+
+.endif
+.if WANT_AD_CONVERTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC multiplexer Selection Register
+VE_ADMUX:
+ .dw $ff05
+ .db "ADMUX",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADMUX
+XT_ADMUX:
+ .dw PFA_DOVARIABLE
+PFA_ADMUX:
+ .dw 124
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register
+VE_ADCSRA:
+ .dw $ff06
+ .db "ADCSRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRA
+XT_ADCSRA:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRA:
+ .dw 122
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register Bytes
+VE_ADC:
+ .dw $ff03
+ .db "ADC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADC
+XT_ADC:
+ .dw PFA_DOVARIABLE
+PFA_ADC:
+ .dw 120
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 0
+VE_DIDR0:
+ .dw $ff05
+ .db "DIDR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR0
+XT_DIDR0:
+ .dw PFA_DOVARIABLE
+PFA_DIDR0:
+ .dw 126
+
+.endif
+.if WANT_BOOT_LOAD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control Register
+VE_SPMCSR:
+ .dw $ff06
+ .db "SPMCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCSR
+XT_SPMCSR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCSR:
+ .dw 87
+
+.endif
+.if WANT_USART0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR0:
+ .dw $ff04
+ .db "UDR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR0
+XT_UDR0:
+ .dw PFA_DOVARIABLE
+PFA_UDR0:
+ .dw 198
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR0A:
+ .dw $ff06
+ .db "UCSR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0A
+XT_UCSR0A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0A:
+ .dw 192
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR0B:
+ .dw $ff06
+ .db "UCSR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0B
+XT_UCSR0B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0B:
+ .dw 193
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR0C:
+ .dw $ff06
+ .db "UCSR0C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0C
+XT_UCSR0C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0C:
+ .dw 194
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Bytes
+VE_UBRR0:
+ .dw $ff05
+ .db "UBRR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR0
+XT_UBRR0:
+ .dw PFA_DOVARIABLE
+PFA_UBRR0:
+ .dw 196
+
+.endif
+.if WANT_CPU == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw 95
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer
+VE_SP:
+ .dw $ff02
+ .db "SP"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SP
+XT_SP:
+ .dw PFA_DOVARIABLE
+PFA_SP:
+ .dw 93
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Calibration Value
+VE_OSCCAL:
+ .dw $ff06
+ .db "OSCCAL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSCCAL
+XT_OSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_OSCCAL:
+ .dw 102
+; ( -- addr ) System Constant
+; R( -- )
+; Clock Prescale Register
+VE_CLKPR:
+ .dw $ff05
+ .db "CLKPR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKPR
+XT_CLKPR:
+ .dw PFA_DOVARIABLE
+PFA_CLKPR:
+ .dw 97
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register
+VE_PRR:
+ .dw $ff03
+ .db "PRR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR
+XT_PRR:
+ .dw PFA_DOVARIABLE
+PFA_PRR:
+ .dw 100
+; ( -- addr ) System Constant
+; R( -- )
+; Sleep Mode Control Register
+VE_SMCR:
+ .dw $ff04
+ .db "SMCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SMCR
+XT_SMCR:
+ .dw PFA_DOVARIABLE
+PFA_SMCR:
+ .dw 83
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 2
+VE_GPIOR2:
+ .dw $ff06
+ .db "GPIOR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR2
+XT_GPIOR2:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR2:
+ .dw 75
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 1
+VE_GPIOR1:
+ .dw $ff06
+ .db "GPIOR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR1
+XT_GPIOR1:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR1:
+ .dw 74
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 0
+VE_GPIOR0:
+ .dw $ff06
+ .db "GPIOR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR0
+XT_GPIOR0:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR0:
+ .dw 62
+
+.endif
+.if WANT_PORTG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Data Register
+VE_PORTG:
+ .dw $ff05
+ .db "PORTG",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTG
+XT_PORTG:
+ .dw PFA_DOVARIABLE
+PFA_PORTG:
+ .dw 52
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Data Direction Register
+VE_DDRG:
+ .dw $ff04
+ .db "DDRG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRG
+XT_DDRG:
+ .dw PFA_DOVARIABLE
+PFA_DDRG:
+ .dw 51
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Input Pins
+VE_PING:
+ .dw $ff04
+ .db "PING"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PING
+XT_PING:
+ .dw PFA_DOVARIABLE
+PFA_PING:
+ .dw 50
+
+.endif
diff --git a/amforth-6.5/avr8/devices/atmega169p/device.py b/amforth-6.5/avr8/devices/atmega169p/device.py
new file mode 100644
index 0000000..71d9500
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega169p/device.py
@@ -0,0 +1,359 @@
+# Generated Automatically
+
+# Partname ATmega169P
+
+MCUREGS = {
+# Interrupt Vectors
+ 'INT0Addr' : '#2', # External Interrupt Request 0
+ 'PCINT0Addr' : '#4', # Pin Change Interrupt Request 0
+ 'PCINT1Addr' : '#6', # Pin Change Interrupt Request 1
+ 'TIMER2_COMPAddr' : '#8', # Timer/Counter2 Compare Match
+ 'TIMER2_OVFAddr' : '#10', # Timer/Counter2 Overflow
+ 'TIMER1_CAPTAddr' : '#12', # Timer/Counter1 Capture Event
+ 'TIMER1_COMPAAddr' : '#14', # Timer/Counter1 Compare Match A
+ 'TIMER1_COMPBAddr' : '#16', # Timer/Counter Compare Match B
+ 'TIMER1_OVFAddr' : '#18', # Timer/Counter1 Overflow
+ 'TIMER0_COMPAddr' : '#20', # Timer/Counter0 Compare Match
+ 'TIMER0_OVFAddr' : '#22', # Timer/Counter0 Overflow
+ 'SPI_STCAddr' : '#24', # SPI Serial Transfer Complete
+ 'USART0_RXAddr' : '#26', # USART0, Rx Complete
+ 'USART0_UDREAddr' : '#28', # USART0 Data register Empty
+ 'USART0_TXAddr' : '#30', # USART0, Tx Complete
+ 'USI_STARTAddr' : '#32', # USI Start Condition
+ 'USI_OVERFLOWAddr' : '#34', # USI Overflow
+ 'ANALOG_COMPAddr' : '#36', # Analog Comparator
+ 'ADCAddr' : '#38', # ADC Conversion Complete
+ 'EE_READYAddr' : '#40', # EEPROM Ready
+ 'SPM_READYAddr' : '#42', # Store Program Memory Read
+ 'LCDAddr' : '#44', # LCD Start of Frame
+
+# Module TIMER_COUNTER_0
+ 'TCCR0A' : '$44', # Timer/Counter0 Control Registe
+ 'TCCR0A_FOC0A': '$80', # Force Output Compare
+ 'TCCR0A_WGM00': '$40', # Waveform Generation Mode 0
+ 'TCCR0A_COM0A': '$30', # Compare Match Output Modes
+ 'TCCR0A_WGM01': '$8', # Waveform Generation Mode 1
+ 'TCCR0A_CS0': '$7', # Clock Selects
+ 'TCNT0' : '$46', # Timer/Counter0
+ 'OCR0A' : '$47', # Timer/Counter0 Output Compare
+ 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
+ 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
+ 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
+ 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
+ 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
+ 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Control Register
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSR310': '$1', # Prescaler Reset Timer/Counter1
+
+# Module TIMER_COUNTER_1
+ 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
+ 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
+ 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
+ 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
+ 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
+ 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
+ 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
+ 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
+ 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
+ 'TCCR1C' : '$82', # Timer/Counter 1 Control Regist
+ 'TCCR1C_FOC1A': '$80', # Force Output Compare 1A
+ 'TCCR1C_FOC1B': '$40', # Force Output Compare 1B
+ 'TCNT1' : '$84', # Timer/Counter1 Bytes
+ 'OCR1A' : '$88', # Timer/Counter1 Output Compare
+ 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
+ 'ICR1' : '$86', # Timer/Counter1 Input Capture R
+ 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
+ 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
+ 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
+ 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
+ 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
+ 'TIFR1' : '$36', # Timer/Counter1 Interrupt Flag
+ 'TIFR1_ICF1': '$20', # Input Capture Flag 1
+ 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
+ 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
+ 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
+
+# Module TIMER_COUNTER_2
+ 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
+ 'TCCR2A_FOC2A': '$80', # Force Output Compare A
+ 'TCCR2A_WGM20': '$40', # Waveform Generation Mode
+ 'TCCR2A_COM2A': '$30', # Compare Output Mode bits
+ 'TCCR2A_WGM21': '$8', # Waveform Generation Mode
+ 'TCCR2A_CS2': '$7', # Clock Select bits
+ 'TCNT2' : '$b2', # Timer/Counter2
+ 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
+ 'TIMSK2' : '$70', # Timer/Counter2 Interrupt Mask
+ 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
+ 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
+ 'TIFR2' : '$37', # Timer/Counter2 Interrupt Flag
+ 'TIFR2_OCF2A': '$2', # Timer/Counter2 Output Compare
+ 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_PSR2': '$2', # Prescaler Reset Timer/Counter2
+ 'ASSR' : '$b6', # Asynchronous Status Register
+ 'ASSR_EXCLK': '$10', # Enable External Clock Interrup
+ 'ASSR_AS2': '$8', # AS2: Asynchronous Timer/Counte
+ 'ASSR_TCN2UB': '$4', # TCN2UB: Timer/Counter2 Update
+ 'ASSR_OCR2UB': '$2', # Output Compare Register2 Updat
+ 'ASSR_TCR2UB': '$1', # TCR2UB: Timer/Counter Control
+
+# Module WATCHDOG
+ 'WDTCR' : '$60', # Watchdog Timer Control Registe
+ 'WDTCR_WDCE': '$10', # Watchdog Change Enable
+ 'WDTCR_WDE': '$8', # Watch Dog Enable
+ 'WDTCR_WDP': '$7', # Watch Dog Timer Prescaler bits
+
+# Module EEPROM
+ 'EEAR' : '$41', # EEPROM Address Register Bytes
+ 'EEDR' : '$40', # EEPROM Data Register
+ 'EECR' : '$3f', # EEPROM Control Register
+ 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
+ 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
+ 'EECR_EEWE': '$2', # EEPROM Write Enable
+ 'EECR_EERE': '$1', # EEPROM Read Enable
+
+# Module SPI
+ 'SPCR' : '$4c', # SPI Control Register
+ 'SPCR_SPIE': '$80', # SPI Interrupt Enable
+ 'SPCR_SPE': '$40', # SPI Enable
+ 'SPCR_DORD': '$20', # Data Order
+ 'SPCR_MSTR': '$10', # Master/Slave Select
+ 'SPCR_CPOL': '$8', # Clock polarity
+ 'SPCR_CPHA': '$4', # Clock Phase
+ 'SPCR_SPR': '$3', # SPI Clock Rate Selects
+ 'SPSR' : '$4d', # SPI Status Register
+ 'SPSR_SPIF': '$80', # SPI Interrupt Flag
+ 'SPSR_WCOL': '$40', # Write Collision Flag
+ 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
+ 'SPDR' : '$4e', # SPI Data Register
+
+# Module PORTA
+ 'PORTA' : '$22', # Port A Data Register
+ 'DDRA' : '$21', # Port A Data Direction Register
+ 'PINA' : '$20', # Port A Input Pins
+
+# Module PORTB
+ 'PORTB' : '$25', # Port B Data Register
+ 'DDRB' : '$24', # Port B Data Direction Register
+ 'PINB' : '$23', # Port B Input Pins
+
+# Module PORTC
+ 'PORTC' : '$28', # Port C Data Register
+ 'DDRC' : '$27', # Port C Data Direction Register
+ 'PINC' : '$26', # Port C Input Pins
+
+# Module PORTD
+ 'PORTD' : '$2b', # Port D Data Register
+ 'DDRD' : '$2a', # Port D Data Direction Register
+ 'PIND' : '$29', # Port D Input Pins
+
+# Module ANALOG_COMPARATOR
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
+ 'ACSR' : '$50', # Analog Comparator Control And
+ 'ACSR_ACD': '$80', # Analog Comparator Disable
+ 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
+ 'ACSR_ACO': '$20', # Analog Compare Output
+ 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
+ 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
+ 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
+ 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
+ 'DIDR1' : '$7f', # Digital Input Disable Register
+ 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
+ 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
+
+# Module PORTE
+ 'PORTE' : '$2e', # Data Register, Port E
+ 'DDRE' : '$2d', # Data Direction Register, Port
+ 'PINE' : '$2c', # Input Pins, Port E
+
+# Module PORTF
+ 'PORTF' : '$31', # Data Register, Port F
+ 'DDRF' : '$30', # Data Direction Register, Port
+ 'PINF' : '$2f', # Input Pins, Port F
+
+# Module JTAG
+ 'OCDR' : '$51', # On-Chip Debug Related Register
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_JTD': '$80', # JTAG Interface Disable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+
+# Module LCD
+ 'LCDCRA' : '$e4', # LCD Control Register A
+ 'LCDCRA_LCDEN': '$80', # LCD Enable
+ 'LCDCRA_LCDAB': '$40', # LCD A or B waveform
+ 'LCDCRA_LCDIF': '$10', # LCD Interrupt Flag
+ 'LCDCRA_LCDIE': '$8', # LCD Interrupt Enable
+ 'LCDCRA_LCDBD': '$4', # LCD Buffer Disable
+ 'LCDCRA_LCDCCD': '$2', # LCD Contrast Control Disable
+ 'LCDCRA_LCDBL': '$1', # LCD Blanking
+ 'LCDCRB' : '$e5', # LCD Control and Status Registe
+ 'LCDCRB_LCDCS': '$80', # LCD CLock Select
+ 'LCDCRB_LCD2B': '$40', # LCD 1/2 Bias Select
+ 'LCDCRB_LCDMUX': '$30', # LCD Mux Selects
+ 'LCDCRB_LCDPM': '$7', # LCD Port Masks
+ 'LCDFRR' : '$e6', # LCD Frame Rate Register
+ 'LCDFRR_LCDPS': '$70', # LCD Prescaler Selects
+ 'LCDFRR_LCDCD': '$7', # LCD Clock Dividers
+ 'LCDCCR' : '$e7', # LCD Contrast Control Register
+ 'LCDCCR_LCDDC': '$e0', # LCD Display Configuration Bits
+ 'LCDCCR_LCDMDT': '$10', # LCD Maximum Drive Time
+ 'LCDCCR_LCDCC': '$f', # LCD Contrast Controls
+ 'LCDDR18' : '$fe', # LCD Data Register 18
+ 'LCDDR17' : '$fd', # LCD Data Register 17
+ 'LCDDR16' : '$fc', # LCD Data Register 16
+ 'LCDDR15' : '$fb', # LCD Data Register 15
+ 'LCDDR13' : '$f9', # LCD Data Register 13
+ 'LCDDR12' : '$f8', # LCD Data Register 12
+ 'LCDDR11' : '$f7', # LCD Data Register 11
+ 'LCDDR10' : '$f6', # LCD Data Register 10
+ 'LCDDR8' : '$f4', # LCD Data Register 8
+ 'LCDDR7' : '$f3', # LCD Data Register 7
+ 'LCDDR6' : '$f2', # LCD Data Register 6
+ 'LCDDR5' : '$f1', # LCD Data Register 5
+ 'LCDDR3' : '$ef', # LCD Data Register 3
+ 'LCDDR2' : '$ee', # LCD Data Register 2
+ 'LCDDR1' : '$ed', # LCD Data Register 1
+ 'LCDDR0' : '$ec', # LCD Data Register 0
+
+# Module EXTERNAL_INTERRUPT
+ 'EICRA' : '$69', # External Interrupt Control Reg
+ 'EICRA_ISC01': '$2', # External Interrupt Sense Contr
+ 'EICRA_ISC00': '$1', # External Interrupt Sense Contr
+ 'EIMSK' : '$3d', # External Interrupt Mask Regist
+ 'EIMSK_PCIE': '$c0', # Pin Change Interrupt Enables
+ 'EIMSK_INT0': '$1', # External Interrupt Request 0 E
+ 'EIFR' : '$3c', # External Interrupt Flag Regist
+ 'EIFR_PCIF': '$c0', # Pin Change Interrupt Flags
+ 'EIFR_INTF0': '$1', # External Interrupt Flag 0
+ 'PCMSK1' : '$6c', # Pin Change Mask Register 1
+ 'PCMSK1_PCINT': '$ff', # Pin Change Enable Masks
+ 'PCMSK0' : '$6b', # Pin Change Mask Register 0
+ 'PCMSK0_PCINT': '$ff', # Pin Change Enable Masks
+
+# Module USI
+ 'USIDR' : '$ba', # USI Data Register
+ 'USISR' : '$b9', # USI Status Register
+ 'USISR_USISIF': '$80', # Start Condition Interrupt Flag
+ 'USISR_USIOIF': '$40', # Counter Overflow Interrupt Fla
+ 'USISR_USIPF': '$20', # Stop Condition Flag
+ 'USISR_USIDC': '$10', # Data Output Collision
+ 'USISR_USICNT': '$f', # USI Counter Value Bits
+ 'USICR' : '$b8', # USI Control Register
+ 'USICR_USISIE': '$80', # Start Condition Interrupt Enab
+ 'USICR_USIOIE': '$40', # Counter Overflow Interrupt Ena
+ 'USICR_USIWM': '$30', # USI Wire Mode Bits
+ 'USICR_USICS': '$c', # USI Clock Source Select Bits
+ 'USICR_USICLK': '$2', # Clock Strobe
+ 'USICR_USITC': '$1', # Toggle Clock Port Pin
+
+# Module AD_CONVERTER
+ 'ADMUX' : '$7c', # The ADC multiplexer Selection
+ 'ADMUX_REFS': '$c0', # Reference Selection Bits
+ 'ADMUX_ADLAR': '$20', # Left Adjust Result
+ 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
+ 'ADCSRA' : '$7a', # The ADC Control and Status reg
+ 'ADCSRA_ADEN': '$80', # ADC Enable
+ 'ADCSRA_ADSC': '$40', # ADC Start Conversion
+ 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
+ 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
+ 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
+ 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
+ 'ADC' : '$78', # ADC Data Register Bytes
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Sources
+ 'DIDR0' : '$7e', # Digital Input Disable Register
+ 'DIDR0_ADC7D': '$80', # ADC7 Digital input Disable
+ 'DIDR0_ADC6D': '$40', # ADC6 Digital input Disable
+ 'DIDR0_ADC5D': '$20', # ADC5 Digital input Disable
+ 'DIDR0_ADC4D': '$10', # ADC4 Digital input Disable
+ 'DIDR0_ADC3D': '$8', # ADC3 Digital input Disable
+ 'DIDR0_ADC2D': '$4', # ADC2 Digital input Disable
+ 'DIDR0_ADC1D': '$2', # ADC1 Digital input Disable
+ 'DIDR0_ADC0D': '$1', # ADC0 Digital input Disable
+
+# Module BOOT_LOAD
+ 'SPMCSR' : '$57', # Store Program Memory Control R
+ 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
+ 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
+ 'SPMCSR_RWWSRE': '$10', # Read While Write section read
+ 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
+ 'SPMCSR_PGWRT': '$4', # Page Write
+ 'SPMCSR_PGERS': '$2', # Page Erase
+ 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
+
+# Module USART0
+ 'UDR0' : '$c6', # USART I/O Data Register
+ 'UCSR0A' : '$c0', # USART Control and Status Regis
+ 'UCSR0A_RXC0': '$80', # USART Receive Complete
+ 'UCSR0A_TXC0': '$40', # USART Transmit Complete
+ 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
+ 'UCSR0A_FE0': '$10', # Framing Error
+ 'UCSR0A_DOR0': '$8', # Data OverRun
+ 'UCSR0A_UPE0': '$4', # USART Parity Error
+ 'UCSR0A_U2X0': '$2', # Double the USART Transmission
+ 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
+ 'UCSR0B' : '$c1', # USART Control and Status Regis
+ 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
+ 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
+ 'UCSR0B_UDRIE0': '$20', # USART Data Register Empty Inte
+ 'UCSR0B_RXEN0': '$10', # Receiver Enable
+ 'UCSR0B_TXEN0': '$8', # Transmitter Enable
+ 'UCSR0B_UCSZ02': '$4', # Character Size
+ 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
+ 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
+ 'UCSR0C' : '$c2', # USART Control and Status Regis
+ 'UCSR0C_UMSEL0': '$40', # USART Mode Select
+ 'UCSR0C_UPM0': '$30', # Parity Mode Bits
+ 'UCSR0C_USBS0': '$8', # Stop Bit Select
+ 'UCSR0C_UCSZ0': '$6', # Character Size
+ 'UCSR0C_UCPOL0': '$1', # Clock Polarity
+ 'UBRR0' : '$c4', # USART Baud Rate Register Byte
+
+# Module CPU
+ 'SREG' : '$5f', # Status Register
+ 'SREG_I': '$80', # Global Interrupt Enable
+ 'SREG_T': '$40', # Bit Copy Storage
+ 'SREG_H': '$20', # Half Carry Flag
+ 'SREG_S': '$10', # Sign Bit
+ 'SREG_V': '$8', # Two's Complement Overflow Flag
+ 'SREG_N': '$4', # Negative Flag
+ 'SREG_Z': '$2', # Zero Flag
+ 'SREG_C': '$1', # Carry Flag
+ 'SP' : '$5d', # Stack Pointer
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_PUD': '$10', # Pull-up disable
+ 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
+ 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+ 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
+ 'MCUSR_BORF': '$4', # Brown-out Reset Flag
+ 'MCUSR_EXTRF': '$2', # External Reset Flag
+ 'MCUSR_PORF': '$1', # Power-on reset flag
+ 'OSCCAL' : '$66', # Oscillator Calibration Value
+ 'CLKPR' : '$61', # Clock Prescale Register
+ 'CLKPR_CLKPCE': '$80', # Clock Prescaler Change Enable
+ 'CLKPR_CLKPS': '$f', # Clock Prescaler Select Bits
+ 'PRR' : '$64', # Power Reduction Register
+ 'PRR_PRLCD': '$10', # Power Reduction LCD
+ 'PRR_PRTIM1': '$8', # Power Reduction Timer/Counter1
+ 'PRR_PRSPI': '$4', # Power Reduction Serial Periphe
+ 'PRR_PRUSART0': '$2', # Power Reduction USART
+ 'PRR_PRADC': '$1', # Power Reduction ADC
+ 'SMCR' : '$53', # Sleep Mode Control Register
+ 'SMCR_SM': '$e', # Sleep Mode Select bits
+ 'SMCR_SE': '$1', # Sleep Enable
+ 'GPIOR2' : '$4b', # General Purpose IO Register 2
+ 'GPIOR1' : '$4a', # General Purpose IO Register 1
+ 'GPIOR0' : '$3e', # General Purpose IO Register 0
+
+# Module PORTG
+ 'PORTG' : '$34', # Port G Data Register
+ 'DDRG' : '$33', # Port G Data Direction Register
+ 'PING' : '$32', # Port G Input Pins
+
+ '__amforth_dummy':'0'
+}
diff --git a/amforth-6.5/avr8/devices/atmega169p/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega169p/words/no-jtag.asm
new file mode 100644
index 0000000..352a4bb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega169p/words/no-jtag.asm
@@ -0,0 +1,14 @@
+; ( -- )
+; ( -- )
+; MCU
+; disable jtag at runtime
+VE_NOJTAG:
+ .dw $FF05
+ .db "-jtag",0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOJTAG
+XT_NOJTAG:
+ .dw PFA_NOJTAG
+PFA_NOJTAG:
+
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega169p/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega169p/words/no-wdt.asm
new file mode 100644
index 0000000..4a12261
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega169p/words/no-wdt.asm
@@ -0,0 +1,22 @@
+; ( -- )
+; MCU
+; disable watch dog timer at runtime
+VE_NOWDT:
+ .dw $ff04
+ .db "-wdt"
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOWDT
+XT_NOWDT:
+ .dw PFA_NOWDT
+PFA_NOWDT:
+
+; Reset WDT
+ wdr
+; Write logical one to WDTOE and WDE
+ in_ temp1, WDTCR
+ ori temp1, (1<<WDTOE)|(1<<WDE)
+ out WDTCR, temp1
+; Turn off WDT
+ ldi temp1, (0<<WDE)
+ out_ WDTCR, temp1
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega169p/words/sleep.asm b/amforth-6.5/avr8/devices/atmega169p/words/sleep.asm
new file mode 100644
index 0000000..256249c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega169p/words/sleep.asm
@@ -0,0 +1,19 @@
+; ( mode -- )
+; MCU
+; put the controller into the specified sleep mode
+VE_SLEEP:
+ .dw $ff05
+ .db "sleep", 0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_SLEEP
+XT_SLEEP:
+ .dw PFA_SLEEP
+PFA_SLEEP:
+ andi tosl, 7 ; leave only legal mode bits
+ lsl tosl ; move to correct location (bits 3-1)
+ ori tosl, 1 ; set the SE bit
+ out_ SMCR, tosl ; set the sleep config
+ sleep ; nighty-night
+ out_ SMCR, zerol ; 0 protects against accidental sleeps
+ loadtos ; pop argument from stack
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega169pa/atmega169pa.frt b/amforth-6.5/avr8/devices/atmega169pa/atmega169pa.frt
new file mode 100644
index 0000000..a4be875
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega169pa/atmega169pa.frt
@@ -0,0 +1,319 @@
+\ Partname: ATmega169PA
+\ generated automatically
+
+\ TIMER_COUNTER_0
+&68 constant TCCR0A \ Timer/Counter0 Control Register
+ $80 constant TCCR0A_FOC0A \ Force Output Compare
+ $40 constant TCCR0A_WGM00 \ Waveform Generation Mode 0
+ $30 constant TCCR0A_COM0A \ Compare Match Output Modes
+ $08 constant TCCR0A_WGM01 \ Waveform Generation Mode 1
+ $07 constant TCCR0A_CS0 \ Clock Selects
+&70 constant TCNT0 \ Timer/Counter0
+&71 constant OCR0A \ Timer/Counter0 Output Compare Register
+&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
+ $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match Interrupt Enable
+ $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
+&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
+ $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0
+ $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
+&67 constant GTCCR \ General Timer/Control Register
+ $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
+ $01 constant GTCCR_PSR310 \ Prescaler Reset Timer/Counter1 and Timer/Counter0
+\ TIMER_COUNTER_1
+&128 constant TCCR1A \ Timer/Counter1 Control Register A
+ $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
+ $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
+ $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
+&129 constant TCCR1B \ Timer/Counter1 Control Register B
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
+ $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
+&130 constant TCCR1C \ Timer/Counter 1 Control Register C
+ $80 constant TCCR1C_FOC1A \ Force Output Compare 1A
+ $40 constant TCCR1C_FOC1B \ Force Output Compare 1B
+&132 constant TCNT1 \ Timer/Counter1 Bytes
+&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
+&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
+&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
+&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
+ $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
+ $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
+ $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
+ $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
+&54 constant TIFR1 \ Timer/Counter1 Interrupt Flag register
+ $20 constant TIFR1_ICF1 \ Input Capture Flag 1
+ $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
+ $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
+ $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
+\ TIMER_COUNTER_2
+&176 constant TCCR2A \ Timer/Counter2 Control Register
+ $80 constant TCCR2A_FOC2A \ Force Output Compare A
+ $40 constant TCCR2A_WGM20 \ Waveform Generation Mode
+ $30 constant TCCR2A_COM2A \ Compare Output Mode bits
+ $08 constant TCCR2A_WGM21 \ Waveform Generation Mode
+ $07 constant TCCR2A_CS2 \ Clock Select bits
+&178 constant TCNT2 \ Timer/Counter2
+&179 constant OCR2A \ Timer/Counter2 Output Compare Register
+&112 constant TIMSK2 \ Timer/Counter2 Interrupt Mask register
+ $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match Interrupt Enable
+ $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
+&55 constant TIFR2 \ Timer/Counter2 Interrupt Flag Register
+ $02 constant TIFR2_OCF2A \ Timer/Counter2 Output Compare Flag 2
+ $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
+&182 constant ASSR \ Asynchronous Status Register
+ $10 constant ASSR_EXCLK \ Enable External Clock Interrupt
+ $08 constant ASSR_AS2 \ AS2: Asynchronous Timer/Counter2
+ $04 constant ASSR_TCN2UB \ TCN2UB: Timer/Counter2 Update Busy
+ $02 constant ASSR_OCR2UB \ Output Compare Register2 Update Busy
+ $01 constant ASSR_TCR2UB \ TCR2UB: Timer/Counter Control Register2 Update Busy
+\ WATCHDOG
+&96 constant WDTCR \ Watchdog Timer Control Register
+ $10 constant WDTCR_WDCE \ Watchdog Change Enable
+ $08 constant WDTCR_WDE \ Watch Dog Enable
+ $07 constant WDTCR_WDP \ Watch Dog Timer Prescaler bits
+\ EEPROM
+&65 constant EEAR \ EEPROM Address Register Bytes
+&64 constant EEDR \ EEPROM Data Register
+&63 constant EECR \ EEPROM Control Register
+ $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
+ $04 constant EECR_EEMWE \ EEPROM Master Write Enable
+ $02 constant EECR_EEWE \ EEPROM Write Enable
+ $01 constant EECR_EERE \ EEPROM Read Enable
+\ SPI
+&76 constant SPCR \ SPI Control Register
+ $80 constant SPCR_SPIE \ SPI Interrupt Enable
+ $40 constant SPCR_SPE \ SPI Enable
+ $20 constant SPCR_DORD \ Data Order
+ $10 constant SPCR_MSTR \ Master/Slave Select
+ $08 constant SPCR_CPOL \ Clock polarity
+ $04 constant SPCR_CPHA \ Clock Phase
+ $03 constant SPCR_SPR \ SPI Clock Rate Selects
+&77 constant SPSR \ SPI Status Register
+ $80 constant SPSR_SPIF \ SPI Interrupt Flag
+ $40 constant SPSR_WCOL \ Write Collision Flag
+ $01 constant SPSR_SPI2X \ Double SPI Speed Bit
+&78 constant SPDR \ SPI Data Register
+\ PORTA
+&34 constant PORTA \ Port A Data Register
+&33 constant DDRA \ Port A Data Direction Register
+&32 constant PINA \ Port A Input Pins
+\ PORTB
+&37 constant PORTB \ Port B Data Register
+&36 constant DDRB \ Port B Data Direction Register
+&35 constant PINB \ Port B Input Pins
+\ PORTC
+&40 constant PORTC \ Port C Data Register
+&39 constant DDRC \ Port C Data Direction Register
+&38 constant PINC \ Port C Input Pins
+\ PORTD
+&43 constant PORTD \ Port D Data Register
+&42 constant DDRD \ Port D Data Direction Register
+&41 constant PIND \ Port D Input Pins
+\ ANALOG_COMPARATOR
+&123 constant ADCSRB \ ADC Control and Status Register B
+ $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer Enable
+&80 constant ACSR \ Analog Comparator Control And Status Register
+ $80 constant ACSR_ACD \ Analog Comparator Disable
+ $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
+ $20 constant ACSR_ACO \ Analog Compare Output
+ $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
+ $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
+ $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
+ $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
+&127 constant DIDR1 \ Digital Input Disable Register 1
+ $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
+ $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
+\ PORTE
+&46 constant PORTE \ Data Register, Port E
+&45 constant DDRE \ Data Direction Register, Port E
+&44 constant PINE \ Input Pins, Port E
+\ PORTF
+&49 constant PORTF \ Data Register, Port F
+&48 constant DDRF \ Data Direction Register, Port F
+&47 constant PINF \ Input Pins, Port F
+\ JTAG
+&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
+&85 constant MCUCR \ MCU Control Register
+ $80 constant MCUCR_JTD \ JTAG Interface Disable
+&84 constant MCUSR \ MCU Status Register
+ $10 constant MCUSR_JTRF \ JTAG Reset Flag
+\ LCD
+&228 constant LCDCRA \ LCD Control Register A
+ $80 constant LCDCRA_LCDEN \ LCD Enable
+ $40 constant LCDCRA_LCDAB \ LCD A or B waveform
+ $10 constant LCDCRA_LCDIF \ LCD Interrupt Flag
+ $08 constant LCDCRA_LCDIE \ LCD Interrupt Enable
+ $04 constant LCDCRA_LCDBD \ LCD Buffer Disable
+ $02 constant LCDCRA_LCDCCD \ LCD Contrast Control Disable
+ $01 constant LCDCRA_LCDBL \ LCD Blanking
+&229 constant LCDCRB \ LCD Control and Status Register B
+ $80 constant LCDCRB_LCDCS \ LCD CLock Select
+ $40 constant LCDCRB_LCD2B \ LCD 1/2 Bias Select
+ $30 constant LCDCRB_LCDMUX \ LCD Mux Selects
+ $07 constant LCDCRB_LCDPM \ LCD Port Masks
+&230 constant LCDFRR \ LCD Frame Rate Register
+ $70 constant LCDFRR_LCDPS \ LCD Prescaler Selects
+ $07 constant LCDFRR_LCDCD \ LCD Clock Dividers
+&231 constant LCDCCR \ LCD Contrast Control Register
+ $E0 constant LCDCCR_LCDDC \ LCD Display Configuration Bits
+ $10 constant LCDCCR_LCDMDT \ LCD Maximum Drive Time
+ $0F constant LCDCCR_LCDCC \ LCD Contrast Controls
+&254 constant LCDDR18 \ LCD Data Register 18
+&253 constant LCDDR17 \ LCD Data Register 17
+&252 constant LCDDR16 \ LCD Data Register 16
+&251 constant LCDDR15 \ LCD Data Register 15
+&249 constant LCDDR13 \ LCD Data Register 13
+&248 constant LCDDR12 \ LCD Data Register 12
+&247 constant LCDDR11 \ LCD Data Register 11
+&246 constant LCDDR10 \ LCD Data Register 10
+&244 constant LCDDR8 \ LCD Data Register 8
+&243 constant LCDDR7 \ LCD Data Register 7
+&242 constant LCDDR6 \ LCD Data Register 6
+&241 constant LCDDR5 \ LCD Data Register 5
+&239 constant LCDDR3 \ LCD Data Register 3
+&238 constant LCDDR2 \ LCD Data Register 2
+&237 constant LCDDR1 \ LCD Data Register 1
+&236 constant LCDDR0 \ LCD Data Register 0
+\ USI
+&186 constant USIDR \ USI Data Register
+&185 constant USISR \ USI Status Register
+ $80 constant USISR_USISIF \ Start Condition Interrupt Flag
+ $40 constant USISR_USIOIF \ Counter Overflow Interrupt Flag
+ $20 constant USISR_USIPF \ Stop Condition Flag
+ $10 constant USISR_USIDC \ Data Output Collision
+ $0F constant USISR_USICNT \ USI Counter Value Bits
+&184 constant USICR \ USI Control Register
+ $80 constant USICR_USISIE \ Start Condition Interrupt Enable
+ $40 constant USICR_USIOIE \ Counter Overflow Interrupt Enable
+ $30 constant USICR_USIWM \ USI Wire Mode Bits
+ $0C constant USICR_USICS \ USI Clock Source Select Bits
+ $02 constant USICR_USICLK \ Clock Strobe
+ $01 constant USICR_USITC \ Toggle Clock Port Pin
+\ AD_CONVERTER
+&124 constant ADMUX \ The ADC multiplexer Selection Register
+ $C0 constant ADMUX_REFS \ Reference Selection Bits
+ $20 constant ADMUX_ADLAR \ Left Adjust Result
+ $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
+&122 constant ADCSRA \ The ADC Control and Status register
+ $80 constant ADCSRA_ADEN \ ADC Enable
+ $40 constant ADCSRA_ADSC \ ADC Start Conversion
+ $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
+ $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
+ $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
+ $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
+&120 constant ADC \ ADC Data Register Bytes
+&126 constant DIDR0 \ Digital Input Disable Register 0
+ $80 constant DIDR0_ADC7D \ ADC7 Digital input Disable
+ $40 constant DIDR0_ADC6D \ ADC6 Digital input Disable
+ $20 constant DIDR0_ADC5D \ ADC5 Digital input Disable
+ $10 constant DIDR0_ADC4D \ ADC4 Digital input Disable
+ $08 constant DIDR0_ADC3D \ ADC3 Digital input Disable
+ $04 constant DIDR0_ADC2D \ ADC2 Digital input Disable
+ $02 constant DIDR0_ADC1D \ ADC1 Digital input Disable
+ $01 constant DIDR0_ADC0D \ ADC0 Digital input Disable
+\ BOOT_LOAD
+&87 constant SPMCSR \ Store Program Memory Control Register
+ $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
+ $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
+ $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
+ $04 constant SPMCSR_PGWRT \ Page Write
+ $02 constant SPMCSR_PGERS \ Page Erase
+ $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
+\ USART0
+&198 constant UDR0 \ USART I/O Data Register
+&192 constant UCSR0A \ USART Control and Status Register A
+ $80 constant UCSR0A_RXC0 \ USART Receive Complete
+ $40 constant UCSR0A_TXC0 \ USART Transmit Complete
+ $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
+ $10 constant UCSR0A_FE0 \ Framing Error
+ $08 constant UCSR0A_DOR0 \ Data OverRun
+ $04 constant UCSR0A_UPE0 \ USART Parity Error
+ $02 constant UCSR0A_U2X0 \ Double the USART Transmission Speed
+ $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
+&193 constant UCSR0B \ USART Control and Status Register B
+ $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
+ $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
+ $20 constant UCSR0B_UDRIE0 \ USART Data Register Empty Interrupt Enable
+ $10 constant UCSR0B_RXEN0 \ Receiver Enable
+ $08 constant UCSR0B_TXEN0 \ Transmitter Enable
+ $04 constant UCSR0B_UCSZ02 \ Character Size
+ $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
+ $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
+&194 constant UCSR0C \ USART Control and Status Register C
+ $40 constant UCSR0C_UMSEL0 \ USART Mode Select
+ $30 constant UCSR0C_UPM0 \ Parity Mode Bits
+ $08 constant UCSR0C_USBS0 \ Stop Bit Select
+ $06 constant UCSR0C_UCSZ0 \ Character Size
+ $01 constant UCSR0C_UCPOL0 \ Clock Polarity
+&196 constant UBRR0 \ USART Baud Rate Register Bytes
+\ PORTG
+&52 constant PORTG \ Port G Data Register
+&51 constant DDRG \ Port G Data Direction Register
+&50 constant PING \ Port G Input Pins
+\ EXTERNAL_INTERRUPT
+&105 constant EICRA \ External Interrupt Control Register
+ $02 constant EICRA_ISC01 \ External Interrupt Sense Control 0 Bit 1
+ $01 constant EICRA_ISC00 \ External Interrupt Sense Control 0 Bit 0
+&61 constant EIMSK \ External Interrupt Mask Register
+ $30 constant EIMSK_PCIE \ Pin Change Interrupt Enables
+ $01 constant EIMSK_INT0 \ External Interrupt Request 0 Enable
+&60 constant EIFR \ External Interrupt Flag Register
+ $30 constant EIFR_PCIF \ Pin Change Interrupt Flags
+ $01 constant EIFR_INTF0 \ External Interrupt Flag 0
+&108 constant PCMSK1 \ Pin Change Mask Register 1
+ $FF constant PCMSK1_PCINT \ Pin Change Enable Masks
+&107 constant PCMSK0 \ Pin Change Mask Register 0
+ $FF constant PCMSK0_PCINT \ Pin Change Enable Masks
+\ CPU
+&95 constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ $08 constant SREG_V \ Two's Complement Overflow Flag
+ $04 constant SREG_N \ Negative Flag
+ $02 constant SREG_Z \ Zero Flag
+ $01 constant SREG_C \ Carry Flag
+&93 constant SP \ Stack Pointer
+&102 constant OSCCAL \ Oscillator Calibration Value
+&97 constant CLKPR \ Clock Prescale Register
+ $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable
+ $0F constant CLKPR_CLKPS \ Clock Prescaler Select Bits
+&100 constant PRR \ Power Reduction Register
+ $10 constant PRR_PRLCD \ Power Reduction LCD
+ $08 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
+ $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
+ $02 constant PRR_PRUSART0 \ Power Reduction USART
+ $01 constant PRR_PRADC \ Power Reduction ADC
+&83 constant SMCR \ Sleep Mode Control Register
+ $0E constant SMCR_SM \ Sleep Mode Select bits
+ $01 constant SMCR_SE \ Sleep Enable
+&75 constant GPIOR2 \ General Purpose IO Register 2
+&74 constant GPIOR1 \ General Purpose IO Register 1
+&62 constant GPIOR0 \ General Purpose IO Register 0
+
+\ Interrupts
+&2 constant INT0Addr \ External Interrupt Request 0
+&4 constant PCINT0Addr \ Pin Change Interrupt Request 0
+&6 constant PCINT1Addr \ Pin Change Interrupt Request 1
+&8 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
+&10 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
+&12 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+&14 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
+&16 constant TIMER1_COMPBAddr \ Timer/Counter Compare Match B
+&18 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+&20 constant TIMER0_COMPAddr \ Timer/Counter0 Compare Match
+&22 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
+&24 constant SPI__STCAddr \ SPI Serial Transfer Complete
+&26 constant USART0__RXAddr \ USART0, Rx Complete
+&28 constant USART0__UDREAddr \ USART0 Data register Empty
+&30 constant USART0__TXAddr \ USART0, Tx Complete
+&32 constant USI_STARTAddr \ USI Start Condition
+&34 constant USI_OVERFLOWAddr \ USI Overflow
+&36 constant ANALOG_COMPAddr \ Analog Comparator
+&38 constant ADCAddr \ ADC Conversion Complete
+&40 constant EE_READYAddr \ EEPROM Ready
+&42 constant SPM_READYAddr \ Store Program Memory Read
+&44 constant LCDAddr \ LCD Start of Frame
diff --git a/amforth-6.5/avr8/devices/atmega169pa/device.asm b/amforth-6.5/avr8/devices/atmega169pa/device.asm
new file mode 100644
index 0000000..af233d4
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega169pa/device.asm
@@ -0,0 +1,109 @@
+; Partname: ATmega169PA
+; generated automatically, do not edit
+
+.nolist
+ .include "m169PAdef.inc"
+.list
+
+.equ ramstart = 256
+.equ CELLSIZE = 2
+.macro readflashcell
+ lsl zl
+ rol zh
+ lpm @0, Z+
+ lpm @1, Z+
+.endmacro
+.macro writeflashcell
+ lsl zl
+ rol zh
+.endmacro
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_TIMER_COUNTER_2 = 0
+.set WANT_WATCHDOG = 0
+.set WANT_EEPROM = 0
+.set WANT_SPI = 0
+.set WANT_PORTA = 0
+.set WANT_PORTB = 0
+.set WANT_PORTC = 0
+.set WANT_PORTD = 0
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_PORTE = 0
+.set WANT_PORTF = 0
+.set WANT_JTAG = 0
+.set WANT_LCD = 0
+.set WANT_USI = 0
+.set WANT_AD_CONVERTER = 0
+.set WANT_BOOT_LOAD = 0
+.set WANT_USART0 = 0
+.set WANT_PORTG = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_CPU = 0
+.equ intvecsize = 2 ; please verify; flash size: 16384 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.org 2
+ rcall isr ; External Interrupt Request 0
+.org 4
+ rcall isr ; Pin Change Interrupt Request 0
+.org 6
+ rcall isr ; Pin Change Interrupt Request 1
+.org 8
+ rcall isr ; Timer/Counter2 Compare Match
+.org 10
+ rcall isr ; Timer/Counter2 Overflow
+.org 12
+ rcall isr ; Timer/Counter1 Capture Event
+.org 14
+ rcall isr ; Timer/Counter1 Compare Match A
+.org 16
+ rcall isr ; Timer/Counter Compare Match B
+.org 18
+ rcall isr ; Timer/Counter1 Overflow
+.org 20
+ rcall isr ; Timer/Counter0 Compare Match
+.org 22
+ rcall isr ; Timer/Counter0 Overflow
+.org 24
+ rcall isr ; SPI Serial Transfer Complete
+.org 26
+ rcall isr ; USART0, Rx Complete
+.org 28
+ rcall isr ; USART0 Data register Empty
+.org 30
+ rcall isr ; USART0, Tx Complete
+.org 32
+ rcall isr ; USI Start Condition
+.org 34
+ rcall isr ; USI Overflow
+.org 36
+ rcall isr ; Analog Comparator
+.org 38
+ rcall isr ; ADC Conversion Complete
+.org 40
+ rcall isr ; EEPROM Ready
+.org 42
+ rcall isr ; Store Program Memory Read
+.org 44
+ rcall isr ; LCD Start of Frame
+.equ INTVECTORS = 23
+.nooverlap
+
+; compatability layer (maybe empty)
+.equ EEPE = EEWE
+.equ EEMPE = EEMWE
+
+; controller data area, environment query mcu-info
+mcu_info:
+mcu_ramsize:
+ .dw 1024
+mcu_eepromsize:
+ .dw 512
+mcu_maxdp:
+ .dw 14336
+mcu_numints:
+ .dw 23
+mcu_name:
+ .dw 11
+ .db "ATmega169PA",0
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega169pa/device.inc b/amforth-6.5/avr8/devices/atmega169pa/device.inc
new file mode 100644
index 0000000..6c34070
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega169pa/device.inc
@@ -0,0 +1,1293 @@
+; Partname: ATmega169PA
+; generated automatically, no not edit
+
+.if WANT_TIMER_COUNTER_0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Control Register
+VE_TCCR0A:
+ .dw $ff06
+ .db "TCCR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0A
+XT_TCCR0A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0A:
+ .dw 68
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw 70
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0A:
+ .dw $ff05
+ .db "OCR0A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0A
+XT_OCR0A:
+ .dw PFA_DOVARIABLE
+PFA_OCR0A:
+ .dw 71
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Mask Register
+VE_TIMSK0:
+ .dw $ff06
+ .db "TIMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK0
+XT_TIMSK0:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK0:
+ .dw 110
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Flag register
+VE_TIFR0:
+ .dw $ff05
+ .db "TIFR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR0
+XT_TIFR0:
+ .dw PFA_DOVARIABLE
+PFA_TIFR0:
+ .dw 53
+; ( -- addr ) System Constant
+; R( -- )
+; General Timer/Control Register
+VE_GTCCR:
+ .dw $ff05
+ .db "GTCCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GTCCR
+XT_GTCCR:
+ .dw PFA_DOVARIABLE
+PFA_GTCCR:
+ .dw 67
+
+.endif
+.if WANT_TIMER_COUNTER_1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw 128
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw 129
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter 1 Control Register C
+VE_TCCR1C:
+ .dw $ff06
+ .db "TCCR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1C
+XT_TCCR1C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1C:
+ .dw 130
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Bytes
+VE_TCNT1:
+ .dw $ff05
+ .db "TCNT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1
+XT_TCNT1:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1:
+ .dw 132
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register A Bytes
+VE_OCR1A:
+ .dw $ff05
+ .db "OCR1A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1A
+XT_OCR1A:
+ .dw PFA_DOVARIABLE
+PFA_OCR1A:
+ .dw 136
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register B Bytes
+VE_OCR1B:
+ .dw $ff05
+ .db "OCR1B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1B
+XT_OCR1B:
+ .dw PFA_DOVARIABLE
+PFA_OCR1B:
+ .dw 138
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Bytes
+VE_ICR1:
+ .dw $ff04
+ .db "ICR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1
+XT_ICR1:
+ .dw PFA_DOVARIABLE
+PFA_ICR1:
+ .dw 134
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Mask Register
+VE_TIMSK1:
+ .dw $ff06
+ .db "TIMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK1
+XT_TIMSK1:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK1:
+ .dw 111
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Flag register
+VE_TIFR1:
+ .dw $ff05
+ .db "TIFR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR1
+XT_TIFR1:
+ .dw PFA_DOVARIABLE
+PFA_TIFR1:
+ .dw 54
+
+.endif
+.if WANT_TIMER_COUNTER_2 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register
+VE_TCCR2A:
+ .dw $ff06
+ .db "TCCR2A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2A
+XT_TCCR2A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2A:
+ .dw 176
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2
+VE_TCNT2:
+ .dw $ff05
+ .db "TCNT2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT2
+XT_TCNT2:
+ .dw PFA_DOVARIABLE
+PFA_TCNT2:
+ .dw 178
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register
+VE_OCR2A:
+ .dw $ff05
+ .db "OCR2A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2A
+XT_OCR2A:
+ .dw PFA_DOVARIABLE
+PFA_OCR2A:
+ .dw 179
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Interrupt Mask register
+VE_TIMSK2:
+ .dw $ff06
+ .db "TIMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK2
+XT_TIMSK2:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK2:
+ .dw 112
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Interrupt Flag Register
+VE_TIFR2:
+ .dw $ff05
+ .db "TIFR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR2
+XT_TIFR2:
+ .dw PFA_DOVARIABLE
+PFA_TIFR2:
+ .dw 55
+; ( -- addr ) System Constant
+; R( -- )
+; Asynchronous Status Register
+VE_ASSR:
+ .dw $ff04
+ .db "ASSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ASSR
+XT_ASSR:
+ .dw PFA_DOVARIABLE
+PFA_ASSR:
+ .dw 182
+
+.endif
+.if WANT_WATCHDOG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCR:
+ .dw $ff05
+ .db "WDTCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCR
+XT_WDTCR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCR:
+ .dw 96
+
+.endif
+.if WANT_EEPROM == 1
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Address Register Bytes
+VE_EEAR:
+ .dw $ff04
+ .db "EEAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEAR
+XT_EEAR:
+ .dw PFA_DOVARIABLE
+PFA_EEAR:
+ .dw 65
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw 64
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw 63
+
+.endif
+.if WANT_SPI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR:
+ .dw $ff04
+ .db "SPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR
+XT_SPCR:
+ .dw PFA_DOVARIABLE
+PFA_SPCR:
+ .dw 76
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR:
+ .dw $ff04
+ .db "SPSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR
+XT_SPSR:
+ .dw PFA_DOVARIABLE
+PFA_SPSR:
+ .dw 77
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR:
+ .dw $ff04
+ .db "SPDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR
+XT_SPDR:
+ .dw PFA_DOVARIABLE
+PFA_SPDR:
+ .dw 78
+
+.endif
+.if WANT_PORTA == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Register
+VE_PORTA:
+ .dw $ff05
+ .db "PORTA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTA
+XT_PORTA:
+ .dw PFA_DOVARIABLE
+PFA_PORTA:
+ .dw 34
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Direction Register
+VE_DDRA:
+ .dw $ff04
+ .db "DDRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRA
+XT_DDRA:
+ .dw PFA_DOVARIABLE
+PFA_DDRA:
+ .dw 33
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Input Pins
+VE_PINA:
+ .dw $ff04
+ .db "PINA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINA
+XT_PINA:
+ .dw PFA_DOVARIABLE
+PFA_PINA:
+ .dw 32
+
+.endif
+.if WANT_PORTB == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw 37
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw 36
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw 35
+
+.endif
+.if WANT_PORTC == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Register
+VE_PORTC:
+ .dw $ff05
+ .db "PORTC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTC
+XT_PORTC:
+ .dw PFA_DOVARIABLE
+PFA_PORTC:
+ .dw 40
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Direction Register
+VE_DDRC:
+ .dw $ff04
+ .db "DDRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRC
+XT_DDRC:
+ .dw PFA_DOVARIABLE
+PFA_DDRC:
+ .dw 39
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Input Pins
+VE_PINC:
+ .dw $ff04
+ .db "PINC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINC
+XT_PINC:
+ .dw PFA_DOVARIABLE
+PFA_PINC:
+ .dw 38
+
+.endif
+.if WANT_PORTD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw 43
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw 42
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw 41
+
+.endif
+.if WANT_ANALOG_COMPARATOR == 1
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Control and Status Register B
+VE_ADCSRB:
+ .dw $ff06
+ .db "ADCSRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRB
+XT_ADCSRB:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRB:
+ .dw 123
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Control And Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw 80
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 1
+VE_DIDR1:
+ .dw $ff05
+ .db "DIDR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR1
+XT_DIDR1:
+ .dw PFA_DOVARIABLE
+PFA_DIDR1:
+ .dw 127
+
+.endif
+.if WANT_PORTE == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port E
+VE_PORTE:
+ .dw $ff05
+ .db "PORTE",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTE
+XT_PORTE:
+ .dw PFA_DOVARIABLE
+PFA_PORTE:
+ .dw 46
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port E
+VE_DDRE:
+ .dw $ff04
+ .db "DDRE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRE
+XT_DDRE:
+ .dw PFA_DOVARIABLE
+PFA_DDRE:
+ .dw 45
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port E
+VE_PINE:
+ .dw $ff04
+ .db "PINE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINE
+XT_PINE:
+ .dw PFA_DOVARIABLE
+PFA_PINE:
+ .dw 44
+
+.endif
+.if WANT_PORTF == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port F
+VE_PORTF:
+ .dw $ff05
+ .db "PORTF",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTF
+XT_PORTF:
+ .dw PFA_DOVARIABLE
+PFA_PORTF:
+ .dw 49
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port F
+VE_DDRF:
+ .dw $ff04
+ .db "DDRF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRF
+XT_DDRF:
+ .dw PFA_DOVARIABLE
+PFA_DDRF:
+ .dw 48
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port F
+VE_PINF:
+ .dw $ff04
+ .db "PINF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINF
+XT_PINF:
+ .dw PFA_DOVARIABLE
+PFA_PINF:
+ .dw 47
+
+.endif
+.if WANT_JTAG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; On-Chip Debug Related Register in I/O Memory
+VE_OCDR:
+ .dw $ff04
+ .db "OCDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCDR
+XT_OCDR:
+ .dw PFA_DOVARIABLE
+PFA_OCDR:
+ .dw 81
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw 85
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Status Register
+VE_MCUSR:
+ .dw $ff05
+ .db "MCUSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUSR
+XT_MCUSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUSR:
+ .dw 84
+
+.endif
+.if WANT_LCD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Control Register A
+VE_LCDCRA:
+ .dw $ff06
+ .db "LCDCRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDCRA
+XT_LCDCRA:
+ .dw PFA_DOVARIABLE
+PFA_LCDCRA:
+ .dw 228
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Control and Status Register B
+VE_LCDCRB:
+ .dw $ff06
+ .db "LCDCRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDCRB
+XT_LCDCRB:
+ .dw PFA_DOVARIABLE
+PFA_LCDCRB:
+ .dw 229
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Frame Rate Register
+VE_LCDFRR:
+ .dw $ff06
+ .db "LCDFRR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDFRR
+XT_LCDFRR:
+ .dw PFA_DOVARIABLE
+PFA_LCDFRR:
+ .dw 230
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Contrast Control Register
+VE_LCDCCR:
+ .dw $ff06
+ .db "LCDCCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDCCR
+XT_LCDCCR:
+ .dw PFA_DOVARIABLE
+PFA_LCDCCR:
+ .dw 231
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 18
+VE_LCDDR18:
+ .dw $ff07
+ .db "LCDDR18",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR18
+XT_LCDDR18:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR18:
+ .dw 254
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 17
+VE_LCDDR17:
+ .dw $ff07
+ .db "LCDDR17",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR17
+XT_LCDDR17:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR17:
+ .dw 253
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 16
+VE_LCDDR16:
+ .dw $ff07
+ .db "LCDDR16",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR16
+XT_LCDDR16:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR16:
+ .dw 252
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 15
+VE_LCDDR15:
+ .dw $ff07
+ .db "LCDDR15",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR15
+XT_LCDDR15:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR15:
+ .dw 251
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 13
+VE_LCDDR13:
+ .dw $ff07
+ .db "LCDDR13",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR13
+XT_LCDDR13:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR13:
+ .dw 249
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 12
+VE_LCDDR12:
+ .dw $ff07
+ .db "LCDDR12",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR12
+XT_LCDDR12:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR12:
+ .dw 248
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 11
+VE_LCDDR11:
+ .dw $ff07
+ .db "LCDDR11",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR11
+XT_LCDDR11:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR11:
+ .dw 247
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 10
+VE_LCDDR10:
+ .dw $ff07
+ .db "LCDDR10",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR10
+XT_LCDDR10:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR10:
+ .dw 246
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 8
+VE_LCDDR8:
+ .dw $ff06
+ .db "LCDDR8"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR8
+XT_LCDDR8:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR8:
+ .dw 244
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 7
+VE_LCDDR7:
+ .dw $ff06
+ .db "LCDDR7"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR7
+XT_LCDDR7:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR7:
+ .dw 243
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 6
+VE_LCDDR6:
+ .dw $ff06
+ .db "LCDDR6"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR6
+XT_LCDDR6:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR6:
+ .dw 242
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 5
+VE_LCDDR5:
+ .dw $ff06
+ .db "LCDDR5"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR5
+XT_LCDDR5:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR5:
+ .dw 241
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 3
+VE_LCDDR3:
+ .dw $ff06
+ .db "LCDDR3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR3
+XT_LCDDR3:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR3:
+ .dw 239
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 2
+VE_LCDDR2:
+ .dw $ff06
+ .db "LCDDR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR2
+XT_LCDDR2:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR2:
+ .dw 238
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 1
+VE_LCDDR1:
+ .dw $ff06
+ .db "LCDDR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR1
+XT_LCDDR1:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR1:
+ .dw 237
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 0
+VE_LCDDR0:
+ .dw $ff06
+ .db "LCDDR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR0
+XT_LCDDR0:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR0:
+ .dw 236
+
+.endif
+.if WANT_USI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USI Data Register
+VE_USIDR:
+ .dw $ff05
+ .db "USIDR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USIDR
+XT_USIDR:
+ .dw PFA_DOVARIABLE
+PFA_USIDR:
+ .dw 186
+; ( -- addr ) System Constant
+; R( -- )
+; USI Status Register
+VE_USISR:
+ .dw $ff05
+ .db "USISR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USISR
+XT_USISR:
+ .dw PFA_DOVARIABLE
+PFA_USISR:
+ .dw 185
+; ( -- addr ) System Constant
+; R( -- )
+; USI Control Register
+VE_USICR:
+ .dw $ff05
+ .db "USICR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USICR
+XT_USICR:
+ .dw PFA_DOVARIABLE
+PFA_USICR:
+ .dw 184
+
+.endif
+.if WANT_AD_CONVERTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC multiplexer Selection Register
+VE_ADMUX:
+ .dw $ff05
+ .db "ADMUX",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADMUX
+XT_ADMUX:
+ .dw PFA_DOVARIABLE
+PFA_ADMUX:
+ .dw 124
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register
+VE_ADCSRA:
+ .dw $ff06
+ .db "ADCSRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRA
+XT_ADCSRA:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRA:
+ .dw 122
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register Bytes
+VE_ADC:
+ .dw $ff03
+ .db "ADC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADC
+XT_ADC:
+ .dw PFA_DOVARIABLE
+PFA_ADC:
+ .dw 120
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 0
+VE_DIDR0:
+ .dw $ff05
+ .db "DIDR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR0
+XT_DIDR0:
+ .dw PFA_DOVARIABLE
+PFA_DIDR0:
+ .dw 126
+
+.endif
+.if WANT_BOOT_LOAD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control Register
+VE_SPMCSR:
+ .dw $ff06
+ .db "SPMCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCSR
+XT_SPMCSR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCSR:
+ .dw 87
+
+.endif
+.if WANT_USART0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR0:
+ .dw $ff04
+ .db "UDR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR0
+XT_UDR0:
+ .dw PFA_DOVARIABLE
+PFA_UDR0:
+ .dw 198
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR0A:
+ .dw $ff06
+ .db "UCSR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0A
+XT_UCSR0A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0A:
+ .dw 192
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR0B:
+ .dw $ff06
+ .db "UCSR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0B
+XT_UCSR0B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0B:
+ .dw 193
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR0C:
+ .dw $ff06
+ .db "UCSR0C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0C
+XT_UCSR0C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0C:
+ .dw 194
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Bytes
+VE_UBRR0:
+ .dw $ff05
+ .db "UBRR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR0
+XT_UBRR0:
+ .dw PFA_DOVARIABLE
+PFA_UBRR0:
+ .dw 196
+
+.endif
+.if WANT_PORTG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Data Register
+VE_PORTG:
+ .dw $ff05
+ .db "PORTG",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTG
+XT_PORTG:
+ .dw PFA_DOVARIABLE
+PFA_PORTG:
+ .dw 52
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Data Direction Register
+VE_DDRG:
+ .dw $ff04
+ .db "DDRG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRG
+XT_DDRG:
+ .dw PFA_DOVARIABLE
+PFA_DDRG:
+ .dw 51
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Input Pins
+VE_PING:
+ .dw $ff04
+ .db "PING"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PING
+XT_PING:
+ .dw PFA_DOVARIABLE
+PFA_PING:
+ .dw 50
+
+.endif
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register
+VE_EICRA:
+ .dw $ff05
+ .db "EICRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRA
+XT_EICRA:
+ .dw PFA_DOVARIABLE
+PFA_EICRA:
+ .dw 105
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Mask Register
+VE_EIMSK:
+ .dw $ff05
+ .db "EIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIMSK
+XT_EIMSK:
+ .dw PFA_DOVARIABLE
+PFA_EIMSK:
+ .dw 61
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Flag Register
+VE_EIFR:
+ .dw $ff04
+ .db "EIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIFR
+XT_EIFR:
+ .dw PFA_DOVARIABLE
+PFA_EIFR:
+ .dw 60
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 1
+VE_PCMSK1:
+ .dw $ff06
+ .db "PCMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK1
+XT_PCMSK1:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK1:
+ .dw 108
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 0
+VE_PCMSK0:
+ .dw $ff06
+ .db "PCMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK0
+XT_PCMSK0:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK0:
+ .dw 107
+
+.endif
+.if WANT_CPU == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw 95
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer
+VE_SP:
+ .dw $ff02
+ .db "SP"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SP
+XT_SP:
+ .dw PFA_DOVARIABLE
+PFA_SP:
+ .dw 93
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Calibration Value
+VE_OSCCAL:
+ .dw $ff06
+ .db "OSCCAL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSCCAL
+XT_OSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_OSCCAL:
+ .dw 102
+; ( -- addr ) System Constant
+; R( -- )
+; Clock Prescale Register
+VE_CLKPR:
+ .dw $ff05
+ .db "CLKPR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKPR
+XT_CLKPR:
+ .dw PFA_DOVARIABLE
+PFA_CLKPR:
+ .dw 97
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register
+VE_PRR:
+ .dw $ff03
+ .db "PRR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR
+XT_PRR:
+ .dw PFA_DOVARIABLE
+PFA_PRR:
+ .dw 100
+; ( -- addr ) System Constant
+; R( -- )
+; Sleep Mode Control Register
+VE_SMCR:
+ .dw $ff04
+ .db "SMCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SMCR
+XT_SMCR:
+ .dw PFA_DOVARIABLE
+PFA_SMCR:
+ .dw 83
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 2
+VE_GPIOR2:
+ .dw $ff06
+ .db "GPIOR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR2
+XT_GPIOR2:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR2:
+ .dw 75
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 1
+VE_GPIOR1:
+ .dw $ff06
+ .db "GPIOR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR1
+XT_GPIOR1:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR1:
+ .dw 74
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 0
+VE_GPIOR0:
+ .dw $ff06
+ .db "GPIOR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR0
+XT_GPIOR0:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR0:
+ .dw 62
+
+.endif
diff --git a/amforth-6.5/avr8/devices/atmega169pa/device.py b/amforth-6.5/avr8/devices/atmega169pa/device.py
new file mode 100644
index 0000000..728dd6f
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega169pa/device.py
@@ -0,0 +1,361 @@
+# Generated Automatically
+
+# Partname ATmega169PA
+
+MCUREGS = {
+# Interrupt Vectors
+ 'INT0Addr' : '#2', # External Interrupt Request 0
+ 'PCINT0Addr' : '#4', # Pin Change Interrupt Request 0
+ 'PCINT1Addr' : '#6', # Pin Change Interrupt Request 1
+ 'TIMER2_COMPAddr' : '#8', # Timer/Counter2 Compare Match
+ 'TIMER2_OVFAddr' : '#10', # Timer/Counter2 Overflow
+ 'TIMER1_CAPTAddr' : '#12', # Timer/Counter1 Capture Event
+ 'TIMER1_COMPAAddr' : '#14', # Timer/Counter1 Compare Match A
+ 'TIMER1_COMPBAddr' : '#16', # Timer/Counter Compare Match B
+ 'TIMER1_OVFAddr' : '#18', # Timer/Counter1 Overflow
+ 'TIMER0_COMPAddr' : '#20', # Timer/Counter0 Compare Match
+ 'TIMER0_OVFAddr' : '#22', # Timer/Counter0 Overflow
+ 'SPI_STCAddr' : '#24', # SPI Serial Transfer Complete
+ 'USART0_RXAddr' : '#26', # USART0, Rx Complete
+ 'USART0_UDREAddr' : '#28', # USART0 Data register Empty
+ 'USART0_TXAddr' : '#30', # USART0, Tx Complete
+ 'USI_STARTAddr' : '#32', # USI Start Condition
+ 'USI_OVERFLOWAddr' : '#34', # USI Overflow
+ 'ANALOG_COMPAddr' : '#36', # Analog Comparator
+ 'ADCAddr' : '#38', # ADC Conversion Complete
+ 'EE_READYAddr' : '#40', # EEPROM Ready
+ 'SPM_READYAddr' : '#42', # Store Program Memory Read
+ 'LCDAddr' : '#44', # LCD Start of Frame
+
+# Module TIMER_COUNTER_0
+ 'TCCR0A' : '$44', # Timer/Counter0 Control Registe
+ 'TCCR0A_FOC0A': '$80', # Force Output Compare
+ 'TCCR0A_WGM00': '$40', # Waveform Generation Mode 0
+ 'TCCR0A_COM0A': '$30', # Compare Match Output Modes
+ 'TCCR0A_WGM01': '$8', # Waveform Generation Mode 1
+ 'TCCR0A_CS0': '$7', # Clock Selects
+ 'TCNT0' : '$46', # Timer/Counter0
+ 'OCR0A' : '$47', # Timer/Counter0 Output Compare
+ 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
+ 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
+ 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
+ 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
+ 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
+ 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Control Register
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSR310': '$1', # Prescaler Reset Timer/Counter1
+
+# Module TIMER_COUNTER_1
+ 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
+ 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
+ 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
+ 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
+ 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
+ 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
+ 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
+ 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
+ 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
+ 'TCCR1C' : '$82', # Timer/Counter 1 Control Regist
+ 'TCCR1C_FOC1A': '$80', # Force Output Compare 1A
+ 'TCCR1C_FOC1B': '$40', # Force Output Compare 1B
+ 'TCNT1' : '$84', # Timer/Counter1 Bytes
+ 'OCR1A' : '$88', # Timer/Counter1 Output Compare
+ 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
+ 'ICR1' : '$86', # Timer/Counter1 Input Capture R
+ 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
+ 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
+ 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
+ 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
+ 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
+ 'TIFR1' : '$36', # Timer/Counter1 Interrupt Flag
+ 'TIFR1_ICF1': '$20', # Input Capture Flag 1
+ 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
+ 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
+ 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
+
+# Module TIMER_COUNTER_2
+ 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
+ 'TCCR2A_FOC2A': '$80', # Force Output Compare A
+ 'TCCR2A_WGM20': '$40', # Waveform Generation Mode
+ 'TCCR2A_COM2A': '$30', # Compare Output Mode bits
+ 'TCCR2A_WGM21': '$8', # Waveform Generation Mode
+ 'TCCR2A_CS2': '$7', # Clock Select bits
+ 'TCNT2' : '$b2', # Timer/Counter2
+ 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
+ 'TIMSK2' : '$70', # Timer/Counter2 Interrupt Mask
+ 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
+ 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
+ 'TIFR2' : '$37', # Timer/Counter2 Interrupt Flag
+ 'TIFR2_OCF2A': '$2', # Timer/Counter2 Output Compare
+ 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_PSR2': '$2', # Prescaler Reset Timer/Counter2
+ 'ASSR' : '$b6', # Asynchronous Status Register
+ 'ASSR_EXCLK': '$10', # Enable External Clock Interrup
+ 'ASSR_AS2': '$8', # AS2: Asynchronous Timer/Counte
+ 'ASSR_TCN2UB': '$4', # TCN2UB: Timer/Counter2 Update
+ 'ASSR_OCR2UB': '$2', # Output Compare Register2 Updat
+ 'ASSR_TCR2UB': '$1', # TCR2UB: Timer/Counter Control
+
+# Module WATCHDOG
+ 'WDTCR' : '$60', # Watchdog Timer Control Registe
+ 'WDTCR_WDCE': '$10', # Watchdog Change Enable
+ 'WDTCR_WDE': '$8', # Watch Dog Enable
+ 'WDTCR_WDP': '$7', # Watch Dog Timer Prescaler bits
+
+# Module EEPROM
+ 'EEAR' : '$41', # EEPROM Address Register Bytes
+ 'EEDR' : '$40', # EEPROM Data Register
+ 'EECR' : '$3f', # EEPROM Control Register
+ 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
+ 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
+ 'EECR_EEWE': '$2', # EEPROM Write Enable
+ 'EECR_EERE': '$1', # EEPROM Read Enable
+
+# Module SPI
+ 'SPCR' : '$4c', # SPI Control Register
+ 'SPCR_SPIE': '$80', # SPI Interrupt Enable
+ 'SPCR_SPE': '$40', # SPI Enable
+ 'SPCR_DORD': '$20', # Data Order
+ 'SPCR_MSTR': '$10', # Master/Slave Select
+ 'SPCR_CPOL': '$8', # Clock polarity
+ 'SPCR_CPHA': '$4', # Clock Phase
+ 'SPCR_SPR': '$3', # SPI Clock Rate Selects
+ 'SPSR' : '$4d', # SPI Status Register
+ 'SPSR_SPIF': '$80', # SPI Interrupt Flag
+ 'SPSR_WCOL': '$40', # Write Collision Flag
+ 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
+ 'SPDR' : '$4e', # SPI Data Register
+
+# Module PORTA
+ 'PORTA' : '$22', # Port A Data Register
+ 'DDRA' : '$21', # Port A Data Direction Register
+ 'PINA' : '$20', # Port A Input Pins
+
+# Module PORTB
+ 'PORTB' : '$25', # Port B Data Register
+ 'DDRB' : '$24', # Port B Data Direction Register
+ 'PINB' : '$23', # Port B Input Pins
+
+# Module PORTC
+ 'PORTC' : '$28', # Port C Data Register
+ 'DDRC' : '$27', # Port C Data Direction Register
+ 'PINC' : '$26', # Port C Input Pins
+
+# Module PORTD
+ 'PORTD' : '$2b', # Port D Data Register
+ 'DDRD' : '$2a', # Port D Data Direction Register
+ 'PIND' : '$29', # Port D Input Pins
+
+# Module ANALOG_COMPARATOR
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
+ 'ACSR' : '$50', # Analog Comparator Control And
+ 'ACSR_ACD': '$80', # Analog Comparator Disable
+ 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
+ 'ACSR_ACO': '$20', # Analog Compare Output
+ 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
+ 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
+ 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
+ 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
+ 'DIDR1' : '$7f', # Digital Input Disable Register
+ 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
+ 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
+
+# Module PORTE
+ 'PORTE' : '$2e', # Data Register, Port E
+ 'DDRE' : '$2d', # Data Direction Register, Port
+ 'PINE' : '$2c', # Input Pins, Port E
+
+# Module PORTF
+ 'PORTF' : '$31', # Data Register, Port F
+ 'DDRF' : '$30', # Data Direction Register, Port
+ 'PINF' : '$2f', # Input Pins, Port F
+
+# Module JTAG
+ 'OCDR' : '$51', # On-Chip Debug Related Register
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_JTD': '$80', # JTAG Interface Disable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+
+# Module LCD
+ 'LCDCRA' : '$e4', # LCD Control Register A
+ 'LCDCRA_LCDEN': '$80', # LCD Enable
+ 'LCDCRA_LCDAB': '$40', # LCD A or B waveform
+ 'LCDCRA_LCDIF': '$10', # LCD Interrupt Flag
+ 'LCDCRA_LCDIE': '$8', # LCD Interrupt Enable
+ 'LCDCRA_LCDBD': '$4', # LCD Buffer Disable
+ 'LCDCRA_LCDCCD': '$2', # LCD Contrast Control Disable
+ 'LCDCRA_LCDBL': '$1', # LCD Blanking
+ 'LCDCRB' : '$e5', # LCD Control and Status Registe
+ 'LCDCRB_LCDCS': '$80', # LCD CLock Select
+ 'LCDCRB_LCD2B': '$40', # LCD 1/2 Bias Select
+ 'LCDCRB_LCDMUX': '$30', # LCD Mux Selects
+ 'LCDCRB_LCDPM': '$7', # LCD Port Masks
+ 'LCDFRR' : '$e6', # LCD Frame Rate Register
+ 'LCDFRR_LCDPS': '$70', # LCD Prescaler Selects
+ 'LCDFRR_LCDCD': '$7', # LCD Clock Dividers
+ 'LCDCCR' : '$e7', # LCD Contrast Control Register
+ 'LCDCCR_LCDDC': '$e0', # LCD Display Configuration Bits
+ 'LCDCCR_LCDMDT': '$10', # LCD Maximum Drive Time
+ 'LCDCCR_LCDCC': '$f', # LCD Contrast Controls
+ 'LCDDR18' : '$fe', # LCD Data Register 18
+ 'LCDDR17' : '$fd', # LCD Data Register 17
+ 'LCDDR16' : '$fc', # LCD Data Register 16
+ 'LCDDR15' : '$fb', # LCD Data Register 15
+ 'LCDDR13' : '$f9', # LCD Data Register 13
+ 'LCDDR12' : '$f8', # LCD Data Register 12
+ 'LCDDR11' : '$f7', # LCD Data Register 11
+ 'LCDDR10' : '$f6', # LCD Data Register 10
+ 'LCDDR8' : '$f4', # LCD Data Register 8
+ 'LCDDR7' : '$f3', # LCD Data Register 7
+ 'LCDDR6' : '$f2', # LCD Data Register 6
+ 'LCDDR5' : '$f1', # LCD Data Register 5
+ 'LCDDR3' : '$ef', # LCD Data Register 3
+ 'LCDDR2' : '$ee', # LCD Data Register 2
+ 'LCDDR1' : '$ed', # LCD Data Register 1
+ 'LCDDR0' : '$ec', # LCD Data Register 0
+
+# Module USI
+ 'USIDR' : '$ba', # USI Data Register
+ 'USISR' : '$b9', # USI Status Register
+ 'USISR_USISIF': '$80', # Start Condition Interrupt Flag
+ 'USISR_USIOIF': '$40', # Counter Overflow Interrupt Fla
+ 'USISR_USIPF': '$20', # Stop Condition Flag
+ 'USISR_USIDC': '$10', # Data Output Collision
+ 'USISR_USICNT': '$f', # USI Counter Value Bits
+ 'USICR' : '$b8', # USI Control Register
+ 'USICR_USISIE': '$80', # Start Condition Interrupt Enab
+ 'USICR_USIOIE': '$40', # Counter Overflow Interrupt Ena
+ 'USICR_USIWM': '$30', # USI Wire Mode Bits
+ 'USICR_USICS': '$c', # USI Clock Source Select Bits
+ 'USICR_USICLK': '$2', # Clock Strobe
+ 'USICR_USITC': '$1', # Toggle Clock Port Pin
+
+# Module AD_CONVERTER
+ 'ADMUX' : '$7c', # The ADC multiplexer Selection
+ 'ADMUX_REFS': '$c0', # Reference Selection Bits
+ 'ADMUX_ADLAR': '$20', # Left Adjust Result
+ 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
+ 'ADCSRA' : '$7a', # The ADC Control and Status reg
+ 'ADCSRA_ADEN': '$80', # ADC Enable
+ 'ADCSRA_ADSC': '$40', # ADC Start Conversion
+ 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
+ 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
+ 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
+ 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
+ 'ADC' : '$78', # ADC Data Register Bytes
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Sources
+ 'DIDR0' : '$7e', # Digital Input Disable Register
+ 'DIDR0_ADC7D': '$80', # ADC7 Digital input Disable
+ 'DIDR0_ADC6D': '$40', # ADC6 Digital input Disable
+ 'DIDR0_ADC5D': '$20', # ADC5 Digital input Disable
+ 'DIDR0_ADC4D': '$10', # ADC4 Digital input Disable
+ 'DIDR0_ADC3D': '$8', # ADC3 Digital input Disable
+ 'DIDR0_ADC2D': '$4', # ADC2 Digital input Disable
+ 'DIDR0_ADC1D': '$2', # ADC1 Digital input Disable
+ 'DIDR0_ADC0D': '$1', # ADC0 Digital input Disable
+
+# Module BOOT_LOAD
+ 'SPMCSR' : '$57', # Store Program Memory Control R
+ 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
+ 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
+ 'SPMCSR_RWWSRE': '$10', # Read While Write section read
+ 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
+ 'SPMCSR_PGWRT': '$4', # Page Write
+ 'SPMCSR_PGERS': '$2', # Page Erase
+ 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
+
+# Module USART0
+ 'UDR0' : '$c6', # USART I/O Data Register
+ 'UCSR0A' : '$c0', # USART Control and Status Regis
+ 'UCSR0A_RXC0': '$80', # USART Receive Complete
+ 'UCSR0A_TXC0': '$40', # USART Transmit Complete
+ 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
+ 'UCSR0A_FE0': '$10', # Framing Error
+ 'UCSR0A_DOR0': '$8', # Data OverRun
+ 'UCSR0A_UPE0': '$4', # USART Parity Error
+ 'UCSR0A_U2X0': '$2', # Double the USART Transmission
+ 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
+ 'UCSR0B' : '$c1', # USART Control and Status Regis
+ 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
+ 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
+ 'UCSR0B_UDRIE0': '$20', # USART Data Register Empty Inte
+ 'UCSR0B_RXEN0': '$10', # Receiver Enable
+ 'UCSR0B_TXEN0': '$8', # Transmitter Enable
+ 'UCSR0B_UCSZ02': '$4', # Character Size
+ 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
+ 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
+ 'UCSR0C' : '$c2', # USART Control and Status Regis
+ 'UCSR0C_UMSEL0': '$40', # USART Mode Select
+ 'UCSR0C_UPM0': '$30', # Parity Mode Bits
+ 'UCSR0C_USBS0': '$8', # Stop Bit Select
+ 'UCSR0C_UCSZ0': '$6', # Character Size
+ 'UCSR0C_UCPOL0': '$1', # Clock Polarity
+ 'UBRR0' : '$c4', # USART Baud Rate Register Byte
+
+# Module PORTG
+ 'PORTG' : '$34', # Port G Data Register
+ 'DDRG' : '$33', # Port G Data Direction Register
+ 'PING' : '$32', # Port G Input Pins
+
+# Module EXTERNAL_INTERRUPT
+ 'EICRA' : '$69', # External Interrupt Control Reg
+ 'EICRA_ISC01': '$2', # External Interrupt Sense Contr
+ 'EICRA_ISC00': '$1', # External Interrupt Sense Contr
+ 'EIMSK' : '$3d', # External Interrupt Mask Regist
+ 'EIMSK_PCIE': '$30', # Pin Change Interrupt Enables
+ 'EIMSK_INT0': '$1', # External Interrupt Request 0 E
+ 'EIFR' : '$3c', # External Interrupt Flag Regist
+ 'EIFR_PCIF': '$30', # Pin Change Interrupt Flags
+ 'EIFR_INTF0': '$1', # External Interrupt Flag 0
+ 'PCMSK1' : '$6c', # Pin Change Mask Register 1
+ 'PCMSK1_PCINT': '$ff', # Pin Change Enable Masks
+ 'PCMSK0' : '$6b', # Pin Change Mask Register 0
+ 'PCMSK0_PCINT': '$ff', # Pin Change Enable Masks
+
+# Module CPU
+ 'SREG' : '$5f', # Status Register
+ 'SREG_I': '$80', # Global Interrupt Enable
+ 'SREG_T': '$40', # Bit Copy Storage
+ 'SREG_H': '$20', # Half Carry Flag
+ 'SREG_S': '$10', # Sign Bit
+ 'SREG_V': '$8', # Two's Complement Overflow Flag
+ 'SREG_N': '$4', # Negative Flag
+ 'SREG_Z': '$2', # Zero Flag
+ 'SREG_C': '$1', # Carry Flag
+ 'SP' : '$5d', # Stack Pointer
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_BODS': '$40', # BOD Sleep
+ 'MCUCR_BODSE': '$20', # BOD Sleep Enable
+ 'MCUCR_PUD': '$10', # Pull-up disable
+ 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
+ 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+ 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
+ 'MCUSR_BORF': '$4', # Brown-out Reset Flag
+ 'MCUSR_EXTRF': '$2', # External Reset Flag
+ 'MCUSR_PORF': '$1', # Power-on reset flag
+ 'OSCCAL' : '$66', # Oscillator Calibration Value
+ 'CLKPR' : '$61', # Clock Prescale Register
+ 'CLKPR_CLKPCE': '$80', # Clock Prescaler Change Enable
+ 'CLKPR_CLKPS': '$f', # Clock Prescaler Select Bits
+ 'PRR' : '$64', # Power Reduction Register
+ 'PRR_PRLCD': '$10', # Power Reduction LCD
+ 'PRR_PRTIM1': '$8', # Power Reduction Timer/Counter1
+ 'PRR_PRSPI': '$4', # Power Reduction Serial Periphe
+ 'PRR_PRUSART0': '$2', # Power Reduction USART
+ 'PRR_PRADC': '$1', # Power Reduction ADC
+ 'SMCR' : '$53', # Sleep Mode Control Register
+ 'SMCR_SM': '$e', # Sleep Mode Select bits
+ 'SMCR_SE': '$1', # Sleep Enable
+ 'GPIOR2' : '$4b', # General Purpose IO Register 2
+ 'GPIOR1' : '$4a', # General Purpose IO Register 1
+ 'GPIOR0' : '$3e', # General Purpose IO Register 0
+
+ '__amforth_dummy':'0'
+}
diff --git a/amforth-6.5/avr8/devices/atmega169pa/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega169pa/words/no-jtag.asm
new file mode 100644
index 0000000..352a4bb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega169pa/words/no-jtag.asm
@@ -0,0 +1,14 @@
+; ( -- )
+; ( -- )
+; MCU
+; disable jtag at runtime
+VE_NOJTAG:
+ .dw $FF05
+ .db "-jtag",0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOJTAG
+XT_NOJTAG:
+ .dw PFA_NOJTAG
+PFA_NOJTAG:
+
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega169pa/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega169pa/words/no-wdt.asm
new file mode 100644
index 0000000..4a12261
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega169pa/words/no-wdt.asm
@@ -0,0 +1,22 @@
+; ( -- )
+; MCU
+; disable watch dog timer at runtime
+VE_NOWDT:
+ .dw $ff04
+ .db "-wdt"
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOWDT
+XT_NOWDT:
+ .dw PFA_NOWDT
+PFA_NOWDT:
+
+; Reset WDT
+ wdr
+; Write logical one to WDTOE and WDE
+ in_ temp1, WDTCR
+ ori temp1, (1<<WDTOE)|(1<<WDE)
+ out WDTCR, temp1
+; Turn off WDT
+ ldi temp1, (0<<WDE)
+ out_ WDTCR, temp1
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega169pa/words/sleep.asm b/amforth-6.5/avr8/devices/atmega169pa/words/sleep.asm
new file mode 100644
index 0000000..256249c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega169pa/words/sleep.asm
@@ -0,0 +1,19 @@
+; ( mode -- )
+; MCU
+; put the controller into the specified sleep mode
+VE_SLEEP:
+ .dw $ff05
+ .db "sleep", 0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_SLEEP
+XT_SLEEP:
+ .dw PFA_SLEEP
+PFA_SLEEP:
+ andi tosl, 7 ; leave only legal mode bits
+ lsl tosl ; move to correct location (bits 3-1)
+ ori tosl, 1 ; set the SE bit
+ out_ SMCR, tosl ; set the sleep config
+ sleep ; nighty-night
+ out_ SMCR, zerol ; 0 protects against accidental sleeps
+ loadtos ; pop argument from stack
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega16a/atmega16a.frt b/amforth-6.5/avr8/devices/atmega16a/atmega16a.frt
new file mode 100644
index 0000000..2552e5b
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega16a/atmega16a.frt
@@ -0,0 +1,221 @@
+\ Partname: ATmega16A
+\ generated automatically
+
+\ TIMER_COUNTER_0
+&83 constant TCCR0 \ Timer/Counter Control Register
+ $80 constant TCCR0_FOC0 \ Force Output Compare
+ $40 constant TCCR0_WGM00 \ Waveform Generation Mode 0
+ $30 constant TCCR0_COM0 \ Compare Match Output Modes
+ $08 constant TCCR0_WGM01 \ Waveform Generation Mode 1
+ $07 constant TCCR0_CS0 \ Clock Selects
+&82 constant TCNT0 \ Timer/Counter Register
+&92 constant OCR0 \ Output Compare Register
+&89 constant TIMSK \ Timer/Counter Interrupt Mask Register
+ $02 constant TIMSK_OCIE0 \ Timer/Counter0 Output Compare Match Interrupt register
+ $01 constant TIMSK_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
+&88 constant TIFR \ Timer/Counter Interrupt Flag register
+ $02 constant TIFR_OCF0 \ Output Compare Flag 0
+ $01 constant TIFR_TOV0 \ Timer/Counter0 Overflow Flag
+&80 constant SFIOR \ Special Function IO Register
+ $01 constant SFIOR_PSR10 \ Prescaler Reset Timer/Counter1 and Timer/Counter0
+\ TIMER_COUNTER_1
+&79 constant TCCR1A \ Timer/Counter1 Control Register A
+ $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
+ $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
+ $08 constant TCCR1A_FOC1A \ Force Output Compare 1A
+ $04 constant TCCR1A_FOC1B \ Force Output Compare 1B
+ $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
+&78 constant TCCR1B \ Timer/Counter1 Control Register B
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
+ $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
+&76 constant TCNT1 \ Timer/Counter1 Bytes
+&74 constant OCR1A \ Timer/Counter1 Output Compare Register Bytes
+&72 constant OCR1B \ Timer/Counter1 Output Compare Register Bytes
+&70 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
+\ EXTERNAL_INTERRUPT
+&91 constant GICR \ General Interrupt Control Register
+ $C0 constant GICR_INT \ External Interrupt Request 1 Enable
+ $20 constant GICR_INT2 \ External Interrupt Request 2 Enable
+ $02 constant GICR_IVSEL \ Interrupt Vector Select
+ $01 constant GICR_IVCE \ Interrupt Vector Change Enable
+&90 constant GIFR \ General Interrupt Flag Register
+ $C0 constant GIFR_INTF \ External Interrupt Flags
+ $20 constant GIFR_INTF2 \ External Interrupt Flag 2
+&85 constant MCUCR \ General Interrupt Control Register
+ $0C constant MCUCR_ISC1 \ Interrupt Sense Control 1 Bits
+ $03 constant MCUCR_ISC0 \ Interrupt Sense Control 0 Bits
+&84 constant MCUCSR \ MCU Control And Status Register
+ $40 constant MCUCSR_ISC2 \ Interrupt Sense Control 2
+\ EEPROM
+&62 constant EEAR \ EEPROM Address Register Bytes
+&61 constant EEDR \ EEPROM Data Register
+&60 constant EECR \ EEPROM Control Register
+ $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
+ $04 constant EECR_EEMWE \ EEPROM Master Write Enable
+ $02 constant EECR_EEWE \ EEPROM Write Enable
+ $01 constant EECR_EERE \ EEPROM Read Enable
+\ CPU
+&95 constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ $08 constant SREG_V \ Two's Complement Overflow Flag
+ $04 constant SREG_N \ Negative Flag
+ $02 constant SREG_Z \ Zero Flag
+ $01 constant SREG_C \ Carry Flag
+&93 constant SP \ Stack Pointer
+&81 constant OSCCAL \ Oscillator Calibration Value
+\ TIMER_COUNTER_2
+&69 constant TCCR2 \ Timer/Counter2 Control Register
+ $80 constant TCCR2_FOC2 \ Force Output Compare
+ $40 constant TCCR2_WGM20 \ Waveform Genration Mode
+ $30 constant TCCR2_COM2 \ Compare Output Mode bits
+ $08 constant TCCR2_WGM21 \ Waveform Generation Mode
+ $07 constant TCCR2_CS2 \ Clock Select bits
+&68 constant TCNT2 \ Timer/Counter2
+&67 constant OCR2 \ Timer/Counter2 Output Compare Register
+&66 constant ASSR \ Asynchronous Status Register
+ $08 constant ASSR_AS2 \ Asynchronous Timer/counter2
+ $04 constant ASSR_TCN2UB \ Timer/Counter2 Update Busy
+ $02 constant ASSR_OCR2UB \ Output Compare Register2 Update Busy
+ $01 constant ASSR_TCR2UB \ Timer/counter Control Register2 Update Busy
+\ SPI
+&47 constant SPDR \ SPI Data Register
+&46 constant SPSR \ SPI Status Register
+ $80 constant SPSR_SPIF \ SPI Interrupt Flag
+ $40 constant SPSR_WCOL \ Write Collision Flag
+ $01 constant SPSR_SPI2X \ Double SPI Speed Bit
+&45 constant SPCR \ SPI Control Register
+ $80 constant SPCR_SPIE \ SPI Interrupt Enable
+ $40 constant SPCR_SPE \ SPI Enable
+ $20 constant SPCR_DORD \ Data Order
+ $10 constant SPCR_MSTR \ Master/Slave Select
+ $08 constant SPCR_CPOL \ Clock polarity
+ $04 constant SPCR_CPHA \ Clock Phase
+ $03 constant SPCR_SPR \ SPI Clock Rate Selects
+\ USART
+&44 constant UDR \ USART I/O Data Register
+&43 constant UCSRA \ USART Control and Status Register A
+ $80 constant UCSRA_RXC \ USART Receive Complete
+ $40 constant UCSRA_TXC \ USART Transmitt Complete
+ $20 constant UCSRA_UDRE \ USART Data Register Empty
+ $10 constant UCSRA_FE \ Framing Error
+ $08 constant UCSRA_DOR \ Data overRun
+ $04 constant UCSRA_UPE \ Parity Error
+ $02 constant UCSRA_U2X \ Double the USART transmission speed
+ $01 constant UCSRA_MPCM \ Multi-processor Communication Mode
+&42 constant UCSRB \ USART Control and Status Register B
+ $80 constant UCSRB_RXCIE \ RX Complete Interrupt Enable
+ $40 constant UCSRB_TXCIE \ TX Complete Interrupt Enable
+ $20 constant UCSRB_UDRIE \ USART Data register Empty Interrupt Enable
+ $10 constant UCSRB_RXEN \ Receiver Enable
+ $08 constant UCSRB_TXEN \ Transmitter Enable
+ $04 constant UCSRB_UCSZ2 \ Character Size
+ $02 constant UCSRB_RXB8 \ Receive Data Bit 8
+ $01 constant UCSRB_TXB8 \ Transmit Data Bit 8
+&64 constant UCSRC \ USART Control and Status Register C
+ $80 constant UCSRC_URSEL \ Register Select
+ $40 constant UCSRC_UMSEL \ USART Mode Select
+ $30 constant UCSRC_UPM \ Parity Mode Bits
+ $08 constant UCSRC_USBS \ Stop Bit Select
+ $06 constant UCSRC_UCSZ \ Character Size
+ $01 constant UCSRC_UCPOL \ Clock Polarity
+&64 constant UBRRH \ USART Baud Rate Register Hight Byte
+&41 constant UBRRL \ USART Baud Rate Register Low Byte
+\ TWI
+&32 constant TWBR \ TWI Bit Rate register
+&86 constant TWCR \ TWI Control Register
+ $80 constant TWCR_TWINT \ TWI Interrupt Flag
+ $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
+ $20 constant TWCR_TWSTA \ TWI Start Condition Bit
+ $10 constant TWCR_TWSTO \ TWI Stop Condition Bit
+ $08 constant TWCR_TWWC \ TWI Write Collition Flag
+ $04 constant TWCR_TWEN \ TWI Enable Bit
+ $01 constant TWCR_TWIE \ TWI Interrupt Enable
+&33 constant TWSR \ TWI Status Register
+ $F8 constant TWSR_TWS \ TWI Status
+ $03 constant TWSR_TWPS \ TWI Prescaler
+&35 constant TWDR \ TWI Data register
+&34 constant TWAR \ TWI (Slave) Address register
+ $FE constant TWAR_TWA \ TWI (Slave) Address register Bits
+ $01 constant TWAR_TWGCE \ TWI General Call Recognition Enable Bit
+\ ANALOG_COMPARATOR
+&40 constant ACSR \ Analog Comparator Control And Status Register
+ $80 constant ACSR_ACD \ Analog Comparator Disable
+ $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
+ $20 constant ACSR_ACO \ Analog Compare Output
+ $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
+ $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
+ $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
+ $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
+\ AD_CONVERTER
+&39 constant ADMUX \ The ADC multiplexer Selection Register
+ $C0 constant ADMUX_REFS \ Reference Selection Bits
+ $20 constant ADMUX_ADLAR \ Left Adjust Result
+ $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
+&38 constant ADCSRA \ The ADC Control and Status register
+ $80 constant ADCSRA_ADEN \ ADC Enable
+ $40 constant ADCSRA_ADSC \ ADC Start Conversion
+ $20 constant ADCSRA_ADATE \ When this bit is written to one,the Timer/Counter2 prescaler will be reset.The bit will be cleared by hardware after the operation is performed.Writing a zero to this bit will have no effect.This bit will always be read as zero if Timer/Counter2 is clocked by the internal CPU clock.If this bit is written when Timer/Counter2 is operating in asynchronous mode,the bit will remain one until the prescaler has been reset.
+ $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
+ $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
+ $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
+&36 constant ADC \ ADC Data Register Bytes
+\ JTAG
+&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
+ $FF constant OCDR_OCDR \ On-Chip Debug Register Bits
+\ BOOT_LOAD
+&87 constant SPMCSR \ Store Program Memory Control Register
+ $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
+ $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
+ $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
+ $04 constant SPMCSR_PGWRT \ Page Write
+ $02 constant SPMCSR_PGERS \ Page Erase
+ $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
+\ PORTA
+&59 constant PORTA \ Port A Data Register
+&58 constant DDRA \ Port A Data Direction Register
+&57 constant PINA \ Port A Input Pins
+\ PORTB
+&56 constant PORTB \ Port B Data Register
+&55 constant DDRB \ Port B Data Direction Register
+&54 constant PINB \ Port B Input Pins
+\ PORTC
+&53 constant PORTC \ Port C Data Register
+&52 constant DDRC \ Port C Data Direction Register
+&51 constant PINC \ Port C Input Pins
+\ PORTD
+&50 constant PORTD \ Port D Data Register
+&49 constant DDRD \ Port D Data Direction Register
+&48 constant PIND \ Port D Input Pins
+\ WATCHDOG
+&65 constant WDTCR \ Watchdog Timer Control Register
+ $10 constant WDTCR_WDTOE \ RW
+ $08 constant WDTCR_WDE \ Watch Dog Enable
+ $07 constant WDTCR_WDP \ Watch Dog Timer Prescaler bits
+
+\ Interrupts
+&2 constant INT0Addr \ External Interrupt Request 0
+&4 constant INT1Addr \ External Interrupt Request 1
+&6 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
+&8 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
+&10 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+&12 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
+&14 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
+&16 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+&18 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
+&20 constant SPI_STCAddr \ Serial Transfer Complete
+&22 constant USART_RXCAddr \ USART, Rx Complete
+&24 constant USART_UDREAddr \ USART Data Register Empty
+&26 constant USART_TXCAddr \ USART, Tx Complete
+&28 constant ADCAddr \ ADC Conversion Complete
+&30 constant EE_RDYAddr \ EEPROM Ready
+&32 constant ANA_COMPAddr \ Analog Comparator
+&34 constant TWIAddr \ 2-wire Serial Interface
+&36 constant INT2Addr \ External Interrupt Request 2
+&38 constant TIMER0_COMPAddr \ Timer/Counter0 Compare Match
+&40 constant SPM_RDYAddr \ Store Program Memory Ready
diff --git a/amforth-6.5/avr8/devices/atmega16a/device.asm b/amforth-6.5/avr8/devices/atmega16a/device.asm
new file mode 100644
index 0000000..1a01ca4
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega16a/device.asm
@@ -0,0 +1,101 @@
+; Partname: ATmega16A
+; generated automatically, do not edit
+
+.nolist
+ .include "m16Adef.inc"
+.list
+
+.equ ramstart = 96
+.equ CELLSIZE = 2
+.macro readflashcell
+ lsl zl
+ rol zh
+ lpm @0, Z+
+ lpm @1, Z+
+.endmacro
+.macro writeflashcell
+ lsl zl
+ rol zh
+.endmacro
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_EEPROM = 0
+.set WANT_CPU = 0
+.set WANT_TIMER_COUNTER_2 = 0
+.set WANT_SPI = 0
+.set WANT_USART = 0
+.set WANT_TWI = 0
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_AD_CONVERTER = 0
+.set WANT_JTAG = 0
+.set WANT_BOOT_LOAD = 0
+.set WANT_PORTA = 0
+.set WANT_PORTB = 0
+.set WANT_PORTC = 0
+.set WANT_PORTD = 0
+.set WANT_WATCHDOG = 0
+.equ intvecsize = 2 ; please verify; flash size: 16384 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.org 2
+ rcall isr ; External Interrupt Request 0
+.org 4
+ rcall isr ; External Interrupt Request 1
+.org 6
+ rcall isr ; Timer/Counter2 Compare Match
+.org 8
+ rcall isr ; Timer/Counter2 Overflow
+.org 10
+ rcall isr ; Timer/Counter1 Capture Event
+.org 12
+ rcall isr ; Timer/Counter1 Compare Match A
+.org 14
+ rcall isr ; Timer/Counter1 Compare Match B
+.org 16
+ rcall isr ; Timer/Counter1 Overflow
+.org 18
+ rcall isr ; Timer/Counter0 Overflow
+.org 20
+ rcall isr ; Serial Transfer Complete
+.org 22
+ rcall isr ; USART, Rx Complete
+.org 24
+ rcall isr ; USART Data Register Empty
+.org 26
+ rcall isr ; USART, Tx Complete
+.org 28
+ rcall isr ; ADC Conversion Complete
+.org 30
+ rcall isr ; EEPROM Ready
+.org 32
+ rcall isr ; Analog Comparator
+.org 34
+ rcall isr ; 2-wire Serial Interface
+.org 36
+ rcall isr ; External Interrupt Request 2
+.org 38
+ rcall isr ; Timer/Counter0 Compare Match
+.org 40
+ rcall isr ; Store Program Memory Ready
+.equ INTVECTORS = 21
+.nooverlap
+
+; compatability layer (maybe empty)
+.equ EEPE = EEWE
+.equ EEMPE = EEMWE
+
+; controller data area, environment query mcu-info
+mcu_info:
+mcu_ramsize:
+ .dw 1024
+mcu_eepromsize:
+ .dw 512
+mcu_maxdp:
+ .dw 14336
+mcu_numints:
+ .dw 21
+mcu_name:
+ .dw 9
+ .db "ATmega16A",0
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega16a/device.inc b/amforth-6.5/avr8/devices/atmega16a/device.inc
new file mode 100644
index 0000000..03920ee
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega16a/device.inc
@@ -0,0 +1,765 @@
+; Partname: ATmega16A
+; generated automatically, no not edit
+
+.if WANT_TIMER_COUNTER_0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register
+VE_TCCR0:
+ .dw $ff05
+ .db "TCCR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0
+XT_TCCR0:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0:
+ .dw 83
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Register
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw 82
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare Register
+VE_OCR0:
+ .dw $ff04
+ .db "OCR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0
+XT_OCR0:
+ .dw PFA_DOVARIABLE
+PFA_OCR0:
+ .dw 92
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Mask Register
+VE_TIMSK:
+ .dw $ff05
+ .db "TIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK
+XT_TIMSK:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK:
+ .dw 89
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Flag register
+VE_TIFR:
+ .dw $ff04
+ .db "TIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR
+XT_TIFR:
+ .dw PFA_DOVARIABLE
+PFA_TIFR:
+ .dw 88
+; ( -- addr ) System Constant
+; R( -- )
+; Special Function IO Register
+VE_SFIOR:
+ .dw $ff05
+ .db "SFIOR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SFIOR
+XT_SFIOR:
+ .dw PFA_DOVARIABLE
+PFA_SFIOR:
+ .dw 80
+
+.endif
+.if WANT_TIMER_COUNTER_1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw 79
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw 78
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Bytes
+VE_TCNT1:
+ .dw $ff05
+ .db "TCNT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1
+XT_TCNT1:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1:
+ .dw 76
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register Bytes
+VE_OCR1A:
+ .dw $ff05
+ .db "OCR1A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1A
+XT_OCR1A:
+ .dw PFA_DOVARIABLE
+PFA_OCR1A:
+ .dw 74
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register Bytes
+VE_OCR1B:
+ .dw $ff05
+ .db "OCR1B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1B
+XT_OCR1B:
+ .dw PFA_DOVARIABLE
+PFA_OCR1B:
+ .dw 72
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Bytes
+VE_ICR1:
+ .dw $ff04
+ .db "ICR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1
+XT_ICR1:
+ .dw PFA_DOVARIABLE
+PFA_ICR1:
+ .dw 70
+
+.endif
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ( -- addr ) System Constant
+; R( -- )
+; General Interrupt Control Register
+VE_GICR:
+ .dw $ff04
+ .db "GICR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GICR
+XT_GICR:
+ .dw PFA_DOVARIABLE
+PFA_GICR:
+ .dw 91
+; ( -- addr ) System Constant
+; R( -- )
+; General Interrupt Flag Register
+VE_GIFR:
+ .dw $ff04
+ .db "GIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GIFR
+XT_GIFR:
+ .dw PFA_DOVARIABLE
+PFA_GIFR:
+ .dw 90
+; ( -- addr ) System Constant
+; R( -- )
+; General Interrupt Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw 85
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control And Status Register
+VE_MCUCSR:
+ .dw $ff06
+ .db "MCUCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCSR
+XT_MCUCSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCSR:
+ .dw 84
+
+.endif
+.if WANT_EEPROM == 1
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Address Register Bytes
+VE_EEAR:
+ .dw $ff04
+ .db "EEAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEAR
+XT_EEAR:
+ .dw PFA_DOVARIABLE
+PFA_EEAR:
+ .dw 62
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw 61
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw 60
+
+.endif
+.if WANT_CPU == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw 95
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer
+VE_SP:
+ .dw $ff02
+ .db "SP"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SP
+XT_SP:
+ .dw PFA_DOVARIABLE
+PFA_SP:
+ .dw 93
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Calibration Value
+VE_OSCCAL:
+ .dw $ff06
+ .db "OSCCAL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSCCAL
+XT_OSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_OSCCAL:
+ .dw 81
+
+.endif
+.if WANT_TIMER_COUNTER_2 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register
+VE_TCCR2:
+ .dw $ff05
+ .db "TCCR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2
+XT_TCCR2:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2:
+ .dw 69
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2
+VE_TCNT2:
+ .dw $ff05
+ .db "TCNT2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT2
+XT_TCNT2:
+ .dw PFA_DOVARIABLE
+PFA_TCNT2:
+ .dw 68
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register
+VE_OCR2:
+ .dw $ff04
+ .db "OCR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2
+XT_OCR2:
+ .dw PFA_DOVARIABLE
+PFA_OCR2:
+ .dw 67
+; ( -- addr ) System Constant
+; R( -- )
+; Asynchronous Status Register
+VE_ASSR:
+ .dw $ff04
+ .db "ASSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ASSR
+XT_ASSR:
+ .dw PFA_DOVARIABLE
+PFA_ASSR:
+ .dw 66
+
+.endif
+.if WANT_SPI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR:
+ .dw $ff04
+ .db "SPDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR
+XT_SPDR:
+ .dw PFA_DOVARIABLE
+PFA_SPDR:
+ .dw 47
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR:
+ .dw $ff04
+ .db "SPSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR
+XT_SPSR:
+ .dw PFA_DOVARIABLE
+PFA_SPSR:
+ .dw 46
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR:
+ .dw $ff04
+ .db "SPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR
+XT_SPCR:
+ .dw PFA_DOVARIABLE
+PFA_SPCR:
+ .dw 45
+
+.endif
+.if WANT_USART == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR:
+ .dw $ff03
+ .db "UDR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR
+XT_UDR:
+ .dw PFA_DOVARIABLE
+PFA_UDR:
+ .dw 44
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSRA:
+ .dw $ff05
+ .db "UCSRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSRA
+XT_UCSRA:
+ .dw PFA_DOVARIABLE
+PFA_UCSRA:
+ .dw 43
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSRB:
+ .dw $ff05
+ .db "UCSRB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSRB
+XT_UCSRB:
+ .dw PFA_DOVARIABLE
+PFA_UCSRB:
+ .dw 42
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSRC:
+ .dw $ff05
+ .db "UCSRC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSRC
+XT_UCSRC:
+ .dw PFA_DOVARIABLE
+PFA_UCSRC:
+ .dw 64
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Hight Byte
+VE_UBRRH:
+ .dw $ff05
+ .db "UBRRH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRRH
+XT_UBRRH:
+ .dw PFA_DOVARIABLE
+PFA_UBRRH:
+ .dw 64
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Low Byte
+VE_UBRRL:
+ .dw $ff05
+ .db "UBRRL",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRRL
+XT_UBRRL:
+ .dw PFA_DOVARIABLE
+PFA_UBRRL:
+ .dw 41
+
+.endif
+.if WANT_TWI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Bit Rate register
+VE_TWBR:
+ .dw $ff04
+ .db "TWBR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWBR
+XT_TWBR:
+ .dw PFA_DOVARIABLE
+PFA_TWBR:
+ .dw 32
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Control Register
+VE_TWCR:
+ .dw $ff04
+ .db "TWCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWCR
+XT_TWCR:
+ .dw PFA_DOVARIABLE
+PFA_TWCR:
+ .dw 86
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Status Register
+VE_TWSR:
+ .dw $ff04
+ .db "TWSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWSR
+XT_TWSR:
+ .dw PFA_DOVARIABLE
+PFA_TWSR:
+ .dw 33
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Data register
+VE_TWDR:
+ .dw $ff04
+ .db "TWDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWDR
+XT_TWDR:
+ .dw PFA_DOVARIABLE
+PFA_TWDR:
+ .dw 35
+; ( -- addr ) System Constant
+; R( -- )
+; TWI (Slave) Address register
+VE_TWAR:
+ .dw $ff04
+ .db "TWAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWAR
+XT_TWAR:
+ .dw PFA_DOVARIABLE
+PFA_TWAR:
+ .dw 34
+
+.endif
+.if WANT_ANALOG_COMPARATOR == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Control And Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw 40
+
+.endif
+.if WANT_AD_CONVERTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC multiplexer Selection Register
+VE_ADMUX:
+ .dw $ff05
+ .db "ADMUX",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADMUX
+XT_ADMUX:
+ .dw PFA_DOVARIABLE
+PFA_ADMUX:
+ .dw 39
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register
+VE_ADCSRA:
+ .dw $ff06
+ .db "ADCSRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRA
+XT_ADCSRA:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRA:
+ .dw 38
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register Bytes
+VE_ADC:
+ .dw $ff03
+ .db "ADC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADC
+XT_ADC:
+ .dw PFA_DOVARIABLE
+PFA_ADC:
+ .dw 36
+
+.endif
+.if WANT_JTAG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; On-Chip Debug Related Register in I/O Memory
+VE_OCDR:
+ .dw $ff04
+ .db "OCDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCDR
+XT_OCDR:
+ .dw PFA_DOVARIABLE
+PFA_OCDR:
+ .dw 81
+
+.endif
+.if WANT_BOOT_LOAD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control Register
+VE_SPMCSR:
+ .dw $ff06
+ .db "SPMCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCSR
+XT_SPMCSR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCSR:
+ .dw 87
+
+.endif
+.if WANT_PORTA == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Register
+VE_PORTA:
+ .dw $ff05
+ .db "PORTA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTA
+XT_PORTA:
+ .dw PFA_DOVARIABLE
+PFA_PORTA:
+ .dw 59
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Direction Register
+VE_DDRA:
+ .dw $ff04
+ .db "DDRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRA
+XT_DDRA:
+ .dw PFA_DOVARIABLE
+PFA_DDRA:
+ .dw 58
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Input Pins
+VE_PINA:
+ .dw $ff04
+ .db "PINA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINA
+XT_PINA:
+ .dw PFA_DOVARIABLE
+PFA_PINA:
+ .dw 57
+
+.endif
+.if WANT_PORTB == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw 56
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw 55
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw 54
+
+.endif
+.if WANT_PORTC == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Register
+VE_PORTC:
+ .dw $ff05
+ .db "PORTC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTC
+XT_PORTC:
+ .dw PFA_DOVARIABLE
+PFA_PORTC:
+ .dw 53
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Direction Register
+VE_DDRC:
+ .dw $ff04
+ .db "DDRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRC
+XT_DDRC:
+ .dw PFA_DOVARIABLE
+PFA_DDRC:
+ .dw 52
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Input Pins
+VE_PINC:
+ .dw $ff04
+ .db "PINC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINC
+XT_PINC:
+ .dw PFA_DOVARIABLE
+PFA_PINC:
+ .dw 51
+
+.endif
+.if WANT_PORTD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw 50
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw 49
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw 48
+
+.endif
+.if WANT_WATCHDOG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCR:
+ .dw $ff05
+ .db "WDTCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCR
+XT_WDTCR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCR:
+ .dw 65
+
+.endif
diff --git a/amforth-6.5/avr8/devices/atmega16a/device.py b/amforth-6.5/avr8/devices/atmega16a/device.py
new file mode 100644
index 0000000..9d8e095
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega16a/device.py
@@ -0,0 +1,284 @@
+# Generated Automatically
+
+# Partname ATmega16A
+
+MCUREGS = {
+# Interrupt Vectors
+ 'INT0Addr' : '#2', # External Interrupt Request 0
+ 'INT1Addr' : '#4', # External Interrupt Request 1
+ 'TIMER2_COMPAddr' : '#6', # Timer/Counter2 Compare Match
+ 'TIMER2_OVFAddr' : '#8', # Timer/Counter2 Overflow
+ 'TIMER1_CAPTAddr' : '#10', # Timer/Counter1 Capture Event
+ 'TIMER1_COMPAAddr' : '#12', # Timer/Counter1 Compare Match A
+ 'TIMER1_COMPBAddr' : '#14', # Timer/Counter1 Compare Match B
+ 'TIMER1_OVFAddr' : '#16', # Timer/Counter1 Overflow
+ 'TIMER0_OVFAddr' : '#18', # Timer/Counter0 Overflow
+ 'SPI_STCAddr' : '#20', # Serial Transfer Complete
+ 'USART_RXCAddr' : '#22', # USART, Rx Complete
+ 'USART_UDREAddr' : '#24', # USART Data Register Empty
+ 'USART_TXCAddr' : '#26', # USART, Tx Complete
+ 'ADCAddr' : '#28', # ADC Conversion Complete
+ 'EE_RDYAddr' : '#30', # EEPROM Ready
+ 'ANA_COMPAddr' : '#32', # Analog Comparator
+ 'TWIAddr' : '#34', # 2-wire Serial Interface
+ 'INT2Addr' : '#36', # External Interrupt Request 2
+ 'TIMER0_COMPAddr' : '#38', # Timer/Counter0 Compare Match
+ 'SPM_RDYAddr' : '#40', # Store Program Memory Ready
+
+# Module TIMER_COUNTER_0
+ 'TCCR0' : '$53', # Timer/Counter Control Register
+ 'TCCR0_FOC0': '$80', # Force Output Compare
+ 'TCCR0_WGM00': '$40', # Waveform Generation Mode 0
+ 'TCCR0_COM0': '$30', # Compare Match Output Modes
+ 'TCCR0_WGM01': '$8', # Waveform Generation Mode 1
+ 'TCCR0_CS0': '$7', # Clock Selects
+ 'TCNT0' : '$52', # Timer/Counter Register
+ 'OCR0' : '$5c', # Output Compare Register
+ 'TIMSK' : '$59', # Timer/Counter Interrupt Mask R
+ 'TIMSK_OCIE0': '$2', # Timer/Counter0 Output Compare
+ 'TIMSK_TOIE0': '$1', # Timer/Counter0 Overflow Interr
+ 'TIFR' : '$58', # Timer/Counter Interrupt Flag r
+ 'TIFR_OCF0': '$2', # Output Compare Flag 0
+ 'TIFR_TOV0': '$1', # Timer/Counter0 Overflow Flag
+ 'SFIOR' : '$50', # Special Function IO Register
+ 'SFIOR_PSR10': '$1', # Prescaler Reset Timer/Counter1
+
+# Module TIMER_COUNTER_1
+ 'TIMSK' : '$59', # Timer/Counter Interrupt Mask R
+ 'TIMSK_TICIE1': '$20', # Timer/Counter1 Input Capture I
+ 'TIMSK_OCIE1A': '$10', # Timer/Counter1 Output CompareA
+ 'TIMSK_OCIE1B': '$8', # Timer/Counter1 Output CompareB
+ 'TIMSK_TOIE1': '$4', # Timer/Counter1 Overflow Interr
+ 'TIFR' : '$58', # Timer/Counter Interrupt Flag r
+ 'TIFR_ICF1': '$20', # Input Capture Flag 1
+ 'TIFR_OCF1A': '$10', # Output Compare Flag 1A
+ 'TIFR_OCF1B': '$8', # Output Compare Flag 1B
+ 'TIFR_TOV1': '$4', # Timer/Counter1 Overflow Flag
+ 'TCCR1A' : '$4f', # Timer/Counter1 Control Registe
+ 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
+ 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
+ 'TCCR1A_FOC1A': '$8', # Force Output Compare 1A
+ 'TCCR1A_FOC1B': '$4', # Force Output Compare 1B
+ 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
+ 'TCCR1B' : '$4e', # Timer/Counter1 Control Registe
+ 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
+ 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
+ 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
+ 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
+ 'TCNT1' : '$4c', # Timer/Counter1 Bytes
+ 'OCR1A' : '$4a', # Timer/Counter1 Output Compare
+ 'OCR1B' : '$48', # Timer/Counter1 Output Compare
+ 'ICR1' : '$46', # Timer/Counter1 Input Capture R
+
+# Module EXTERNAL_INTERRUPT
+ 'GICR' : '$5b', # General Interrupt Control Regi
+ 'GICR_INT': '$c0', # External Interrupt Request 1 E
+ 'GICR_INT2': '$20', # External Interrupt Request 2 E
+ 'GICR_IVSEL': '$2', # Interrupt Vector Select
+ 'GICR_IVCE': '$1', # Interrupt Vector Change Enable
+ 'GIFR' : '$5a', # General Interrupt Flag Registe
+ 'GIFR_INTF': '$c0', # External Interrupt Flags
+ 'GIFR_INTF2': '$20', # External Interrupt Flag 2
+ 'MCUCR' : '$55', # General Interrupt Control Regi
+ 'MCUCR_ISC1': '$c', # Interrupt Sense Control 1 Bits
+ 'MCUCR_ISC0': '$3', # Interrupt Sense Control 0 Bits
+ 'MCUCSR' : '$54', # MCU Control And Status Registe
+ 'MCUCSR_ISC2': '$40', # Interrupt Sense Control 2
+
+# Module EEPROM
+ 'EEAR' : '$3e', # EEPROM Address Register Bytes
+ 'EEDR' : '$3d', # EEPROM Data Register
+ 'EECR' : '$3c', # EEPROM Control Register
+ 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
+ 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
+ 'EECR_EEWE': '$2', # EEPROM Write Enable
+ 'EECR_EERE': '$1', # EEPROM Read Enable
+
+# Module CPU
+ 'SREG' : '$5f', # Status Register
+ 'SREG_I': '$80', # Global Interrupt Enable
+ 'SREG_T': '$40', # Bit Copy Storage
+ 'SREG_H': '$20', # Half Carry Flag
+ 'SREG_S': '$10', # Sign Bit
+ 'SREG_V': '$8', # Two's Complement Overflow Flag
+ 'SREG_N': '$4', # Negative Flag
+ 'SREG_Z': '$2', # Zero Flag
+ 'SREG_C': '$1', # Carry Flag
+ 'SP' : '$5d', # Stack Pointer
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_SM': '$b0', # Sleep Mode Select
+ 'MCUCR_SE': '$40', # Sleep Enable
+ 'MCUCR_ISC1': '$c', # Interrupt Sense Control 1 Bits
+ 'MCUCR_ISC0': '$3', # Interrupt Sense Control 0 Bits
+ 'MCUCSR' : '$54', # MCU Control And Status Registe
+ 'MCUCSR_JTD': '$80', # JTAG Interface Disable
+ 'MCUCSR_JTRF': '$10', # JTAG Reset Flag
+ 'MCUCSR_WDRF': '$8', # Watchdog Reset Flag
+ 'MCUCSR_BORF': '$4', # Brown-out Reset Flag
+ 'MCUCSR_EXTRF': '$2', # External Reset Flag
+ 'MCUCSR_PORF': '$1', # Power-on reset flag
+ 'OSCCAL' : '$51', # Oscillator Calibration Value
+ 'SFIOR' : '$50', # Special function I/O register
+ 'SFIOR_PUD': '$4', # Pull-up Disable
+ 'SFIOR_PSR2': '$2', # Prescaler reset
+ 'SFIOR_PSR10': '$1', # Prescaler reset
+
+# Module TIMER_COUNTER_2
+ 'TIMSK' : '$59', # Timer/Counter Interrupt Mask r
+ 'TIMSK_OCIE2': '$80', # Timer/Counter2 Output Compare
+ 'TIMSK_TOIE2': '$40', # Timer/Counter2 Overflow Interr
+ 'TIFR' : '$58', # Timer/Counter Interrupt Flag R
+ 'TIFR_OCF2': '$80', # Output Compare Flag 2
+ 'TIFR_TOV2': '$40', # Timer/Counter2 Overflow Flag
+ 'TCCR2' : '$45', # Timer/Counter2 Control Registe
+ 'TCCR2_FOC2': '$80', # Force Output Compare
+ 'TCCR2_WGM20': '$40', # Waveform Genration Mode
+ 'TCCR2_COM2': '$30', # Compare Output Mode bits
+ 'TCCR2_WGM21': '$8', # Waveform Generation Mode
+ 'TCCR2_CS2': '$7', # Clock Select bits
+ 'TCNT2' : '$44', # Timer/Counter2
+ 'OCR2' : '$43', # Timer/Counter2 Output Compare
+ 'ASSR' : '$42', # Asynchronous Status Register
+ 'ASSR_AS2': '$8', # Asynchronous Timer/counter2
+ 'ASSR_TCN2UB': '$4', # Timer/Counter2 Update Busy
+ 'ASSR_OCR2UB': '$2', # Output Compare Register2 Updat
+ 'ASSR_TCR2UB': '$1', # Timer/counter Control Register
+ 'SFIOR' : '$50', # Special Function IO Register
+ 'SFIOR_PSR2': '$2', # Prescaler Reset Timer/Counter2
+
+# Module SPI
+ 'SPDR' : '$2f', # SPI Data Register
+ 'SPSR' : '$2e', # SPI Status Register
+ 'SPSR_SPIF': '$80', # SPI Interrupt Flag
+ 'SPSR_WCOL': '$40', # Write Collision Flag
+ 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
+ 'SPCR' : '$2d', # SPI Control Register
+ 'SPCR_SPIE': '$80', # SPI Interrupt Enable
+ 'SPCR_SPE': '$40', # SPI Enable
+ 'SPCR_DORD': '$20', # Data Order
+ 'SPCR_MSTR': '$10', # Master/Slave Select
+ 'SPCR_CPOL': '$8', # Clock polarity
+ 'SPCR_CPHA': '$4', # Clock Phase
+ 'SPCR_SPR': '$3', # SPI Clock Rate Selects
+
+# Module USART
+ 'UDR' : '$2c', # USART I/O Data Register
+ 'UCSRA' : '$2b', # USART Control and Status Regis
+ 'UCSRA_RXC': '$80', # USART Receive Complete
+ 'UCSRA_TXC': '$40', # USART Transmitt Complete
+ 'UCSRA_UDRE': '$20', # USART Data Register Empty
+ 'UCSRA_FE': '$10', # Framing Error
+ 'UCSRA_DOR': '$8', # Data overRun
+ 'UCSRA_UPE': '$4', # Parity Error
+ 'UCSRA_U2X': '$2', # Double the USART transmission
+ 'UCSRA_MPCM': '$1', # Multi-processor Communication
+ 'UCSRB' : '$2a', # USART Control and Status Regis
+ 'UCSRB_RXCIE': '$80', # RX Complete Interrupt Enable
+ 'UCSRB_TXCIE': '$40', # TX Complete Interrupt Enable
+ 'UCSRB_UDRIE': '$20', # USART Data register Empty Inte
+ 'UCSRB_RXEN': '$10', # Receiver Enable
+ 'UCSRB_TXEN': '$8', # Transmitter Enable
+ 'UCSRB_UCSZ2': '$4', # Character Size
+ 'UCSRB_RXB8': '$2', # Receive Data Bit 8
+ 'UCSRB_TXB8': '$1', # Transmit Data Bit 8
+ 'UCSRC' : '$40', # USART Control and Status Regis
+ 'UCSRC_URSEL': '$80', # Register Select
+ 'UCSRC_UMSEL': '$40', # USART Mode Select
+ 'UCSRC_UPM': '$30', # Parity Mode Bits
+ 'UCSRC_USBS': '$8', # Stop Bit Select
+ 'UCSRC_UCSZ': '$6', # Character Size
+ 'UCSRC_UCPOL': '$1', # Clock Polarity
+ 'UBRRH' : '$40', # USART Baud Rate Register Hight
+ 'UBRRL' : '$29', # USART Baud Rate Register Low B
+
+# Module TWI
+ 'TWBR' : '$20', # TWI Bit Rate register
+ 'TWCR' : '$56', # TWI Control Register
+ 'TWCR_TWINT': '$80', # TWI Interrupt Flag
+ 'TWCR_TWEA': '$40', # TWI Enable Acknowledge Bit
+ 'TWCR_TWSTA': '$20', # TWI Start Condition Bit
+ 'TWCR_TWSTO': '$10', # TWI Stop Condition Bit
+ 'TWCR_TWWC': '$8', # TWI Write Collition Flag
+ 'TWCR_TWEN': '$4', # TWI Enable Bit
+ 'TWCR_TWIE': '$1', # TWI Interrupt Enable
+ 'TWSR' : '$21', # TWI Status Register
+ 'TWSR_TWS': '$f8', # TWI Status
+ 'TWSR_TWPS': '$3', # TWI Prescaler
+ 'TWDR' : '$23', # TWI Data register
+ 'TWAR' : '$22', # TWI (Slave) Address register
+ 'TWAR_TWA': '$fe', # TWI (Slave) Address register B
+ 'TWAR_TWGCE': '$1', # TWI General Call Recognition E
+
+# Module ANALOG_COMPARATOR
+ 'SFIOR' : '$50', # Special Function IO Register
+ 'SFIOR_ACME': '$8', # Analog Comparator Multiplexer
+ 'ACSR' : '$28', # Analog Comparator Control And
+ 'ACSR_ACD': '$80', # Analog Comparator Disable
+ 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
+ 'ACSR_ACO': '$20', # Analog Compare Output
+ 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
+ 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
+ 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
+ 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
+
+# Module AD_CONVERTER
+ 'ADMUX' : '$27', # The ADC multiplexer Selection
+ 'ADMUX_REFS': '$c0', # Reference Selection Bits
+ 'ADMUX_ADLAR': '$20', # Left Adjust Result
+ 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
+ 'ADCSRA' : '$26', # The ADC Control and Status reg
+ 'ADCSRA_ADEN': '$80', # ADC Enable
+ 'ADCSRA_ADSC': '$40', # ADC Start Conversion
+ 'ADCSRA_ADATE': '$20', # When this bit is written to on
+ 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
+ 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
+ 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
+ 'ADC' : '$24', # ADC Data Register Bytes
+ 'SFIOR' : '$50', # Special Function IO Register
+ 'SFIOR_ADTS': '$e0', # ADC Auto Trigger Sources
+
+# Module JTAG
+ 'OCDR' : '$51', # On-Chip Debug Related Register
+ 'OCDR_OCDR': '$ff', # On-Chip Debug Register Bits
+ 'MCUCSR' : '$54', # MCU Control And Status Registe
+ 'MCUCSR_JTD': '$80', # JTAG Interface Disable
+ 'MCUCSR_JTRF': '$10', # JTAG Reset Flag
+
+# Module BOOT_LOAD
+ 'SPMCSR' : '$57', # Store Program Memory Control R
+ 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
+ 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
+ 'SPMCSR_RWWSRE': '$10', # Read While Write section read
+ 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
+ 'SPMCSR_PGWRT': '$4', # Page Write
+ 'SPMCSR_PGERS': '$2', # Page Erase
+ 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
+
+# Module PORTA
+ 'PORTA' : '$3b', # Port A Data Register
+ 'DDRA' : '$3a', # Port A Data Direction Register
+ 'PINA' : '$39', # Port A Input Pins
+
+# Module PORTB
+ 'PORTB' : '$38', # Port B Data Register
+ 'DDRB' : '$37', # Port B Data Direction Register
+ 'PINB' : '$36', # Port B Input Pins
+
+# Module PORTC
+ 'PORTC' : '$35', # Port C Data Register
+ 'DDRC' : '$34', # Port C Data Direction Register
+ 'PINC' : '$33', # Port C Input Pins
+
+# Module PORTD
+ 'PORTD' : '$32', # Port D Data Register
+ 'DDRD' : '$31', # Port D Data Direction Register
+ 'PIND' : '$30', # Port D Input Pins
+
+# Module WATCHDOG
+ 'WDTCR' : '$41', # Watchdog Timer Control Registe
+ 'WDTCR_WDTOE': '$10', # RW
+ 'WDTCR_WDE': '$8', # Watch Dog Enable
+ 'WDTCR_WDP': '$7', # Watch Dog Timer Prescaler bits
+
+ '__amforth_dummy':'0'
+}
diff --git a/amforth-6.5/avr8/devices/atmega16a/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega16a/words/no-jtag.asm
new file mode 100644
index 0000000..352a4bb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega16a/words/no-jtag.asm
@@ -0,0 +1,14 @@
+; ( -- )
+; ( -- )
+; MCU
+; disable jtag at runtime
+VE_NOJTAG:
+ .dw $FF05
+ .db "-jtag",0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOJTAG
+XT_NOJTAG:
+ .dw PFA_NOJTAG
+PFA_NOJTAG:
+
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega16a/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega16a/words/no-wdt.asm
new file mode 100644
index 0000000..4a12261
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega16a/words/no-wdt.asm
@@ -0,0 +1,22 @@
+; ( -- )
+; MCU
+; disable watch dog timer at runtime
+VE_NOWDT:
+ .dw $ff04
+ .db "-wdt"
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOWDT
+XT_NOWDT:
+ .dw PFA_NOWDT
+PFA_NOWDT:
+
+; Reset WDT
+ wdr
+; Write logical one to WDTOE and WDE
+ in_ temp1, WDTCR
+ ori temp1, (1<<WDTOE)|(1<<WDE)
+ out WDTCR, temp1
+; Turn off WDT
+ ldi temp1, (0<<WDE)
+ out_ WDTCR, temp1
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega16a/words/sleep.asm b/amforth-6.5/avr8/devices/atmega16a/words/sleep.asm
new file mode 100644
index 0000000..778fa32
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega16a/words/sleep.asm
@@ -0,0 +1,24 @@
+; ( mode -- )
+; MCU
+; put the controller into the specified sleep mode
+VE_SLEEP:
+ .dw $ff05
+ .db "sleep", 0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_SLEEP
+XT_SLEEP:
+ .dw PFA_SLEEP
+PFA_SLEEP:
+ andi tosl, 7 ; leave only legal mode bits
+ swap tosl ; move to correct location (bits 6-4, atmega32)
+ ori tosl, $80 ; set the SE bit (atmega32: bit 7, not bit 0)
+ out_ MCUCR, tosl ; set the sleep config (atmega32: MCUCR not SMCR)
+ sleep ; nighty-night
+;; the 4 lower bits of MCUCR should not be touched
+ in_ tosl, MCUCR
+ andi tosl, $0F
+ out_ MCUCR, tosl
+ ;clr tosl ; need to clean up the SMCR reg before we leave
+ ;out SMCR, tosl ; 0 protects against accidental sleeps
+ loadtos ; pop argument from stack
+ jmp DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega16hva/atmega16hva.frt b/amforth-6.5/avr8/devices/atmega16hva/atmega16hva.frt
new file mode 100644
index 0000000..6e3bec4
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega16hva/atmega16hva.frt
@@ -0,0 +1,140 @@
+\ Partname: ATmega16HVA
+\ Built using part description XML file version 40
+\ generated automatically
+
+hex
+
+\ AD_CONVERTER
+79 constant VADCH \ VADC Data Register High Byte
+78 constant VADCL \ VADC Data Register Low Byte
+7A constant VADCSR \ The VADC Control and Status register
+7C constant VADMUX \ The VADC multiplexer Selection Register
+
+\ BANDGAP
+D0 constant BGCCR \ Bandgap Calibration Register
+D1 constant BGCRR \ Bandgap Calibration of Resistor Ladder
+
+\ BATTERY_PROTECTION
+F9 constant BPCHCD \ Battery Protection Charge-High-current Detection Level Register
+F7 constant BPCOCD \ Battery Protection Charge-Over-current Detection Level Register
+FD constant BPCR \ Battery Protection Control Register
+F8 constant BPDHCD \ Battery Protection Discharge-High-current Detection Level Register
+F6 constant BPDOCD \ Battery Protection Discharge-Over-current Detection Level Register
+FC constant BPHCTR \ Battery Protection Short-current Timing Register
+F3 constant BPIFR \ Battery Protection Interrupt Flag Register
+F2 constant BPIMSK \ Battery Protection Interrupt Mask Register
+FB constant BPOCTR \ Battery Protection Over-current Timing Register
+FE constant BPPLR \ Battery Protection Parameter Lock Register
+F5 constant BPSCD \ Battery Protection Short-Circuit Detection Level Register
+FA constant BPSCTR \ Battery Protection Short-current Timing Register
+
+\ BOOT_LOAD
+57 constant SPMCSR \ Store Program Memory Control and Status Register
+
+\ COULOMB_COUNTER
+E0 constant CADAC0 \ ADC Accumulate Current
+E1 constant CADAC1 \ ADC Accumulate Current
+E2 constant CADAC2 \ ADC Accumulate Current
+E3 constant CADAC3 \ ADC Accumulate Current
+E4 constant CADCSRA \ CC-ADC Control and Status Register A
+E5 constant CADCSRB \ CC-ADC Control and Status Register B
+E9 constant CADICH \ CC-ADC Instantaneous Current
+E8 constant CADICL \ CC-ADC Instantaneous Current
+E6 constant CADRC \ CC-ADC Regular Current
+
+\ CPU
+61 constant CLKPR \ Clock Prescale Register
+7E constant DIDR0 \ Digital Input Disable Register
+66 constant FOSCCAL \ Fast Oscillator Calibration Value
+3E constant GPIOR0 \ General Purpose IO Register 0
+4A constant GPIOR1 \ General Purpose IO Register 1
+4B constant GPIOR2 \ General Purpose IO Register 2
+55 constant MCUCR \ MCU Control Register
+54 constant MCUSR \ MCU Status Register
+37 constant OSICSR \ Oscillator Sampling Interface Control and Status Register
+64 constant PRR0 \ Power Reduction Register 0
+53 constant SMCR \ Sleep Mode Control Register
+5E constant SPH \ Stack Pointer High
+5D constant SPL \ Stack Pointer Low
+5F constant SREG \ Status Register
+
+\ EEPROM
+41 constant EEAR \ EEPROM Read/Write Access
+3F constant EECR \ EEPROM Control Register
+40 constant EEDR \ EEPROM Data Register
+
+\ EXTERNAL_INTERRUPT
+69 constant EICRA \ External Interrupt Control Register
+3C constant EIFR \ External Interrupt Flag Register
+3D constant EIMSK \ External Interrupt Mask Register
+
+\ FET
+F0 constant FCSR \ FET Control and Status Register
+
+\ PORTA
+21 constant DDRA \ Port A Data Direction Register
+20 constant PINA \ Port A Input Pins
+22 constant PORTA \ Port A Data Register
+
+\ PORTB
+24 constant DDRB \ Data Direction Register, Port B
+23 constant PINB \ Input Pins, Port B
+25 constant PORTB \ Data Register, Port B
+
+\ PORTC
+26 constant PINC \ Port C Input Pins
+28 constant PORTC \ Port C Data Register
+
+\ SPI
+4c constant SPCR \ SPI Control Register
+4e constant SPDR \ SPI Data Register
+4d constant SPSR \ SPI Status Register
+
+\ TIMER_COUNTER_0
+48 constant OCR0A \ Output compare Register A
+49 constant OCR0B \ Output compare Register B
+44 constant TCCR0A \ Timer/Counter0 Control Register
+45 constant TCCR0B \ Timer/Counter0 Control Register
+47 constant TCNT0H \ Timer Counter 0 High Byte
+46 constant TCNT0L \ Timer Counter 0 Low Byte
+35 constant TIFR0 \ Timer/Counter Interrupt Flag register
+6E constant TIMSK0 \ Timer/Counter Interrupt Mask Register
+
+\ TIMER_COUNTER_1
+43 constant GTCCR \ General Timer/Counter Control Register
+88 constant OCR1A \ Output Compare Register 1A
+89 constant OCR1B \ Output Compare Register B
+80 constant TCCR1A \ Timer/Counter 1 Control Register A
+81 constant TCCR1B \ Timer/Counter1 Control Register B
+85 constant TCNT1H \ Timer Counter 1 High Byte
+84 constant TCNT1L \ Timer Counter 1 Low Byte
+36 constant TIFR1 \ Timer/Counter Interrupt Flag register
+6F constant TIMSK1 \ Timer/Counter Interrupt Mask Register
+
+\ VOLTAGE_REGULATOR
+C8 constant ROCR \ Regulator Operating Condition Register
+
+\ WATCHDOG
+60 constant WDTCSR \ Watchdog Timer Control Register
+
+\ Interrupts
+0002 constant BPINTAddr \ Battery Protection Interrupt
+0004 constant VREGMONAddr \ Voltage regulator monitor interrupt
+0006 constant INT0Addr \ External Interrupt Request 0
+0008 constant INT1Addr \ External Interrupt Request 1
+000A constant INT2Addr \ External Interrupt Request 2
+000C constant WDTAddr \ Watchdog Timeout Interrupt
+000E constant TIMER1_ICAddr \ Timer 1 Input capture
+0010 constant TIMER1_COMPAAddr \ Timer 1 Compare Match A
+0012 constant TIMER1_COMPBAddr \ Timer 1 Compare Match B
+0014 constant TIMER1_OVFAddr \ Timer 1 overflow
+0016 constant TIMER0_ICAddr \ Timer 0 Input Capture
+0018 constant TIMER0_COMPAAddr \ Timer 0 Comapre Match A
+001A constant TIMER0_COMPBAddr \ Timer 0 Compare Match B
+001C constant TIMER0_OVFAddr \ Timer 0 Overflow
+001E constant SPI;STCAddr \ SPI Serial transfer complete
+0020 constant VADCAddr \ Voltage ADC Conversion Complete
+0022 constant CCADC_CONVAddr \ Coulomb Counter ADC Conversion Complete
+0024 constant CCADC_REG_CURAddr \ Coloumb Counter ADC Regular Current
+0026 constant CCADC_ACCAddr \ Coloumb Counter ADC Accumulator
+028 constant EE_READYAddr \ EEPROM Ready
diff --git a/amforth-6.5/avr8/devices/atmega16hva/device.asm b/amforth-6.5/avr8/devices/atmega16hva/device.asm
new file mode 100644
index 0000000..1f5b109
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega16hva/device.asm
@@ -0,0 +1,114 @@
+; Partname: ATmega16HVA
+; Built using part description XML file version 40
+; generated automatically, do not edit
+
+.nolist
+ .include "m16HVAdef.inc"
+.list
+
+.equ ramstart = $100
+.equ CELLSIZE = 2
+.macro readflashcell
+ lsl zl
+ rol zh
+ lpm @0, Z+
+ lpm @1, Z+
+.endmacro
+.macro writeflashcell
+ lsl zl
+ rol zh
+.endmacro
+
+; the following definitions are shortcuts for the respective forth source segments if set to 1
+.set WANT_AD_CONVERTER = 0
+.set WANT_BANDGAP = 0
+.set WANT_BATTERY_PROTECTION = 0
+.set WANT_BOOT_LOAD = 0
+.set WANT_COULOMB_COUNTER = 0
+.set WANT_CPU = 0
+.set WANT_EEPROM = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_FET = 0
+.set WANT_PORTA = 0
+.set WANT_PORTB = 0
+.set WANT_PORTC = 0
+.set WANT_SPI = 0
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_VOLTAGE_REGULATOR = 0
+.set WANT_WATCHDOG = 0
+
+
+.ifndef SPMEN
+ .equ SPMEN = SELFPRGEN
+.endif
+
+.ifndef SPMCSR
+ .equ SPMCSR = SPMCR
+.endif
+
+.ifndef EEPE
+ .equ EEPE = EEWE
+.endif
+
+.ifndef EEMPE
+ .equ EEMPE = EEMWE
+.endif
+.equ intvecsize = 2 ; please verify; flash size: 16384 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.equ INTVECTORS = 21
+.org $0002
+ rcall isr ; Battery Protection Interrupt
+.org $0004
+ rcall isr ; Voltage regulator monitor interrupt
+.org $0006
+ rcall isr ; External Interrupt Request 0
+.org $0008
+ rcall isr ; External Interrupt Request 1
+.org $000A
+ rcall isr ; External Interrupt Request 2
+.org $000C
+ rcall isr ; Watchdog Timeout Interrupt
+.org $000E
+ rcall isr ; Timer 1 Input capture
+.org $0010
+ rcall isr ; Timer 1 Compare Match A
+.org $0012
+ rcall isr ; Timer 1 Compare Match B
+.org $0014
+ rcall isr ; Timer 1 overflow
+.org $0016
+ rcall isr ; Timer 0 Input Capture
+.org $0018
+ rcall isr ; Timer 0 Comapre Match A
+.org $001A
+ rcall isr ; Timer 0 Compare Match B
+.org $001C
+ rcall isr ; Timer 0 Overflow
+.org $001E
+ rcall isr ; SPI Serial transfer complete
+.org $0020
+ rcall isr ; Voltage ADC Conversion Complete
+.org $0022
+ rcall isr ; Coulomb Counter ADC Conversion Complete
+.org $0024
+ rcall isr ; Coloumb Counter ADC Regular Current
+.org $0026
+ rcall isr ; Coloumb Counter ADC Accumulator
+.org $028
+ rcall isr ; EEPROM Ready
+.nooverlap
+mcu_info:
+mcu_ramsize:
+ .dw 512
+mcu_eepromsize:
+ .dw 256
+mcu_maxdp:
+ .dw 0 ; minimum of 0 (from XML) and 0xffff
+mcu_numints:
+ .dw 21
+mcu_name:
+ .dw 11
+ .db "ATmega16HVA",0
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega16hva/device.inc b/amforth-6.5/avr8/devices/atmega16hva/device.inc
new file mode 100644
index 0000000..8664a17
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega16hva/device.inc
@@ -0,0 +1,1053 @@
+; Partname: ATmega16HVA
+; Built using part description XML file version 40
+; generated automatically, no not edit
+
+; ********
+.if WANT_AD_CONVERTER == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; VADC Data Register High Byte
+VE_VADCH:
+ .dw $ff05
+ .db "VADCH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_VADCH
+XT_VADCH:
+ .dw PFA_DOVARIABLE
+PFA_VADCH:
+ .dw $79
+; ( -- addr ) System Constant
+; R( -- )
+; VADC Data Register Low Byte
+VE_VADCL:
+ .dw $ff05
+ .db "VADCL",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_VADCL
+XT_VADCL:
+ .dw PFA_DOVARIABLE
+PFA_VADCL:
+ .dw $78
+; ( -- addr ) System Constant
+; R( -- )
+; The VADC Control and Status register
+VE_VADCSR:
+ .dw $ff06
+ .db "VADCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_VADCSR
+XT_VADCSR:
+ .dw PFA_DOVARIABLE
+PFA_VADCSR:
+ .dw $7A
+; ( -- addr ) System Constant
+; R( -- )
+; The VADC multiplexer Selection Register
+VE_VADMUX:
+ .dw $ff06
+ .db "VADMUX"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_VADMUX
+XT_VADMUX:
+ .dw PFA_DOVARIABLE
+PFA_VADMUX:
+ .dw $7C
+
+.endif
+
+; ********
+.if WANT_BANDGAP == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Bandgap Calibration Register
+VE_BGCCR:
+ .dw $ff05
+ .db "BGCCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_BGCCR
+XT_BGCCR:
+ .dw PFA_DOVARIABLE
+PFA_BGCCR:
+ .dw $D0
+; ( -- addr ) System Constant
+; R( -- )
+; Bandgap Calibration of Resistor Ladder
+VE_BGCRR:
+ .dw $ff05
+ .db "BGCRR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_BGCRR
+XT_BGCRR:
+ .dw PFA_DOVARIABLE
+PFA_BGCRR:
+ .dw $D1
+
+.endif
+
+; ********
+.if WANT_BATTERY_PROTECTION == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Battery Protection Charge-High-current Detection Level Register
+VE_BPCHCD:
+ .dw $ff06
+ .db "BPCHCD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_BPCHCD
+XT_BPCHCD:
+ .dw PFA_DOVARIABLE
+PFA_BPCHCD:
+ .dw $F9
+; ( -- addr ) System Constant
+; R( -- )
+; Battery Protection Charge-Over-current Detection Level Register
+VE_BPCOCD:
+ .dw $ff06
+ .db "BPCOCD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_BPCOCD
+XT_BPCOCD:
+ .dw PFA_DOVARIABLE
+PFA_BPCOCD:
+ .dw $F7
+; ( -- addr ) System Constant
+; R( -- )
+; Battery Protection Control Register
+VE_BPCR:
+ .dw $ff04
+ .db "BPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_BPCR
+XT_BPCR:
+ .dw PFA_DOVARIABLE
+PFA_BPCR:
+ .dw $FD
+; ( -- addr ) System Constant
+; R( -- )
+; Battery Protection Discharge-High-current Detection Level Register
+VE_BPDHCD:
+ .dw $ff06
+ .db "BPDHCD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_BPDHCD
+XT_BPDHCD:
+ .dw PFA_DOVARIABLE
+PFA_BPDHCD:
+ .dw $F8
+; ( -- addr ) System Constant
+; R( -- )
+; Battery Protection Discharge-Over-current Detection Level Register
+VE_BPDOCD:
+ .dw $ff06
+ .db "BPDOCD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_BPDOCD
+XT_BPDOCD:
+ .dw PFA_DOVARIABLE
+PFA_BPDOCD:
+ .dw $F6
+; ( -- addr ) System Constant
+; R( -- )
+; Battery Protection Short-current Timing Register
+VE_BPHCTR:
+ .dw $ff06
+ .db "BPHCTR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_BPHCTR
+XT_BPHCTR:
+ .dw PFA_DOVARIABLE
+PFA_BPHCTR:
+ .dw $FC
+; ( -- addr ) System Constant
+; R( -- )
+; Battery Protection Interrupt Flag Register
+VE_BPIFR:
+ .dw $ff05
+ .db "BPIFR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_BPIFR
+XT_BPIFR:
+ .dw PFA_DOVARIABLE
+PFA_BPIFR:
+ .dw $F3
+; ( -- addr ) System Constant
+; R( -- )
+; Battery Protection Interrupt Mask Register
+VE_BPIMSK:
+ .dw $ff06
+ .db "BPIMSK"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_BPIMSK
+XT_BPIMSK:
+ .dw PFA_DOVARIABLE
+PFA_BPIMSK:
+ .dw $F2
+; ( -- addr ) System Constant
+; R( -- )
+; Battery Protection Over-current Timing Register
+VE_BPOCTR:
+ .dw $ff06
+ .db "BPOCTR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_BPOCTR
+XT_BPOCTR:
+ .dw PFA_DOVARIABLE
+PFA_BPOCTR:
+ .dw $FB
+; ( -- addr ) System Constant
+; R( -- )
+; Battery Protection Parameter Lock Register
+VE_BPPLR:
+ .dw $ff05
+ .db "BPPLR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_BPPLR
+XT_BPPLR:
+ .dw PFA_DOVARIABLE
+PFA_BPPLR:
+ .dw $FE
+; ( -- addr ) System Constant
+; R( -- )
+; Battery Protection Short-Circuit Detection Level Register
+VE_BPSCD:
+ .dw $ff05
+ .db "BPSCD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_BPSCD
+XT_BPSCD:
+ .dw PFA_DOVARIABLE
+PFA_BPSCD:
+ .dw $F5
+; ( -- addr ) System Constant
+; R( -- )
+; Battery Protection Short-current Timing Register
+VE_BPSCTR:
+ .dw $ff06
+ .db "BPSCTR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_BPSCTR
+XT_BPSCTR:
+ .dw PFA_DOVARIABLE
+PFA_BPSCTR:
+ .dw $FA
+
+.endif
+
+; ********
+.if WANT_BOOT_LOAD == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control and Status Register
+VE_SPMCSR:
+ .dw $ff06
+ .db "SPMCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCSR
+XT_SPMCSR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCSR:
+ .dw $57
+
+.endif
+
+; ********
+.if WANT_COULOMB_COUNTER == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Accumulate Current
+VE_CADAC0:
+ .dw $ff06
+ .db "CADAC0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CADAC0
+XT_CADAC0:
+ .dw PFA_DOVARIABLE
+PFA_CADAC0:
+ .dw $E0
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Accumulate Current
+VE_CADAC1:
+ .dw $ff06
+ .db "CADAC1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CADAC1
+XT_CADAC1:
+ .dw PFA_DOVARIABLE
+PFA_CADAC1:
+ .dw $E1
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Accumulate Current
+VE_CADAC2:
+ .dw $ff06
+ .db "CADAC2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CADAC2
+XT_CADAC2:
+ .dw PFA_DOVARIABLE
+PFA_CADAC2:
+ .dw $E2
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Accumulate Current
+VE_CADAC3:
+ .dw $ff06
+ .db "CADAC3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CADAC3
+XT_CADAC3:
+ .dw PFA_DOVARIABLE
+PFA_CADAC3:
+ .dw $E3
+; ( -- addr ) System Constant
+; R( -- )
+; CC-ADC Control and Status Register A
+VE_CADCSRA:
+ .dw $ff07
+ .db "CADCSRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CADCSRA
+XT_CADCSRA:
+ .dw PFA_DOVARIABLE
+PFA_CADCSRA:
+ .dw $E4
+; ( -- addr ) System Constant
+; R( -- )
+; CC-ADC Control and Status Register B
+VE_CADCSRB:
+ .dw $ff07
+ .db "CADCSRB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CADCSRB
+XT_CADCSRB:
+ .dw PFA_DOVARIABLE
+PFA_CADCSRB:
+ .dw $E5
+; ( -- addr ) System Constant
+; R( -- )
+; CC-ADC Instantaneous Current
+VE_CADICH:
+ .dw $ff06
+ .db "CADICH"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CADICH
+XT_CADICH:
+ .dw PFA_DOVARIABLE
+PFA_CADICH:
+ .dw $E9
+; ( -- addr ) System Constant
+; R( -- )
+; CC-ADC Instantaneous Current
+VE_CADICL:
+ .dw $ff06
+ .db "CADICL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CADICL
+XT_CADICL:
+ .dw PFA_DOVARIABLE
+PFA_CADICL:
+ .dw $E8
+; ( -- addr ) System Constant
+; R( -- )
+; CC-ADC Regular Current
+VE_CADRC:
+ .dw $ff05
+ .db "CADRC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CADRC
+XT_CADRC:
+ .dw PFA_DOVARIABLE
+PFA_CADRC:
+ .dw $E6
+
+.endif
+
+; ********
+.if WANT_CPU == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Clock Prescale Register
+VE_CLKPR:
+ .dw $ff05
+ .db "CLKPR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKPR
+XT_CLKPR:
+ .dw PFA_DOVARIABLE
+PFA_CLKPR:
+ .dw $61
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register
+VE_DIDR0:
+ .dw $ff05
+ .db "DIDR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR0
+XT_DIDR0:
+ .dw PFA_DOVARIABLE
+PFA_DIDR0:
+ .dw $7E
+; ( -- addr ) System Constant
+; R( -- )
+; Fast Oscillator Calibration Value
+VE_FOSCCAL:
+ .dw $ff07
+ .db "FOSCCAL",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_FOSCCAL
+XT_FOSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_FOSCCAL:
+ .dw $66
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 0
+VE_GPIOR0:
+ .dw $ff06
+ .db "GPIOR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR0
+XT_GPIOR0:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR0:
+ .dw $3E
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 1
+VE_GPIOR1:
+ .dw $ff06
+ .db "GPIOR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR1
+XT_GPIOR1:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR1:
+ .dw $4A
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 2
+VE_GPIOR2:
+ .dw $ff06
+ .db "GPIOR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR2
+XT_GPIOR2:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR2:
+ .dw $4B
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw $55
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Status Register
+VE_MCUSR:
+ .dw $ff05
+ .db "MCUSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUSR
+XT_MCUSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUSR:
+ .dw $54
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Sampling Interface Control and Status Register
+VE_OSICSR:
+ .dw $ff06
+ .db "OSICSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSICSR
+XT_OSICSR:
+ .dw PFA_DOVARIABLE
+PFA_OSICSR:
+ .dw $37
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register 0
+VE_PRR0:
+ .dw $ff04
+ .db "PRR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR0
+XT_PRR0:
+ .dw PFA_DOVARIABLE
+PFA_PRR0:
+ .dw $64
+; ( -- addr ) System Constant
+; R( -- )
+; Sleep Mode Control Register
+VE_SMCR:
+ .dw $ff04
+ .db "SMCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SMCR
+XT_SMCR:
+ .dw PFA_DOVARIABLE
+PFA_SMCR:
+ .dw $53
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer High
+VE_SPH:
+ .dw $ff03
+ .db "SPH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPH
+XT_SPH:
+ .dw PFA_DOVARIABLE
+PFA_SPH:
+ .dw $5E
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer Low
+VE_SPL:
+ .dw $ff03
+ .db "SPL",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPL
+XT_SPL:
+ .dw PFA_DOVARIABLE
+PFA_SPL:
+ .dw $5D
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw $5F
+
+.endif
+
+; ********
+.if WANT_EEPROM == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Read/Write Access
+VE_EEAR:
+ .dw $ff04
+ .db "EEAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEAR
+XT_EEAR:
+ .dw PFA_DOVARIABLE
+PFA_EEAR:
+ .dw $41
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw $3F
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw $40
+
+.endif
+
+; ********
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register
+VE_EICRA:
+ .dw $ff05
+ .db "EICRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRA
+XT_EICRA:
+ .dw PFA_DOVARIABLE
+PFA_EICRA:
+ .dw $69
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Flag Register
+VE_EIFR:
+ .dw $ff04
+ .db "EIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIFR
+XT_EIFR:
+ .dw PFA_DOVARIABLE
+PFA_EIFR:
+ .dw $3C
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Mask Register
+VE_EIMSK:
+ .dw $ff05
+ .db "EIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIMSK
+XT_EIMSK:
+ .dw PFA_DOVARIABLE
+PFA_EIMSK:
+ .dw $3D
+
+.endif
+
+; ********
+.if WANT_FET == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; FET Control and Status Register
+VE_FCSR:
+ .dw $ff04
+ .db "FCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_FCSR
+XT_FCSR:
+ .dw PFA_DOVARIABLE
+PFA_FCSR:
+ .dw $F0
+
+.endif
+
+; ********
+.if WANT_PORTA == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Direction Register
+VE_DDRA:
+ .dw $ff04
+ .db "DDRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRA
+XT_DDRA:
+ .dw PFA_DOVARIABLE
+PFA_DDRA:
+ .dw $21
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Input Pins
+VE_PINA:
+ .dw $ff04
+ .db "PINA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINA
+XT_PINA:
+ .dw PFA_DOVARIABLE
+PFA_PINA:
+ .dw $20
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Register
+VE_PORTA:
+ .dw $ff05
+ .db "PORTA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTA
+XT_PORTA:
+ .dw PFA_DOVARIABLE
+PFA_PORTA:
+ .dw $22
+
+.endif
+
+; ********
+.if WANT_PORTB == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port B
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw $24
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port B
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw $23
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port B
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw $25
+
+.endif
+
+; ********
+.if WANT_PORTC == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Input Pins
+VE_PINC:
+ .dw $ff04
+ .db "PINC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINC
+XT_PINC:
+ .dw PFA_DOVARIABLE
+PFA_PINC:
+ .dw $26
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Register
+VE_PORTC:
+ .dw $ff05
+ .db "PORTC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTC
+XT_PORTC:
+ .dw PFA_DOVARIABLE
+PFA_PORTC:
+ .dw $28
+
+.endif
+
+; ********
+.if WANT_SPI == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR:
+ .dw $ff04
+ .db "SPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR
+XT_SPCR:
+ .dw PFA_DOVARIABLE
+PFA_SPCR:
+ .dw $4c
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR:
+ .dw $ff04
+ .db "SPDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR
+XT_SPDR:
+ .dw PFA_DOVARIABLE
+PFA_SPDR:
+ .dw $4e
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR:
+ .dw $ff04
+ .db "SPSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR
+XT_SPSR:
+ .dw PFA_DOVARIABLE
+PFA_SPSR:
+ .dw $4d
+
+.endif
+
+; ********
+.if WANT_TIMER_COUNTER_0 == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Output compare Register A
+VE_OCR0A:
+ .dw $ff05
+ .db "OCR0A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0A
+XT_OCR0A:
+ .dw PFA_DOVARIABLE
+PFA_OCR0A:
+ .dw $48
+; ( -- addr ) System Constant
+; R( -- )
+; Output compare Register B
+VE_OCR0B:
+ .dw $ff05
+ .db "OCR0B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0B
+XT_OCR0B:
+ .dw PFA_DOVARIABLE
+PFA_OCR0B:
+ .dw $49
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Control Register
+VE_TCCR0A:
+ .dw $ff06
+ .db "TCCR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0A
+XT_TCCR0A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0A:
+ .dw $44
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Control Register
+VE_TCCR0B:
+ .dw $ff06
+ .db "TCCR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0B
+XT_TCCR0B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0B:
+ .dw $45
+; ( -- addr ) System Constant
+; R( -- )
+; Timer Counter 0 High Byte
+VE_TCNT0H:
+ .dw $ff06
+ .db "TCNT0H"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0H
+XT_TCNT0H:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0H:
+ .dw $47
+; ( -- addr ) System Constant
+; R( -- )
+; Timer Counter 0 Low Byte
+VE_TCNT0L:
+ .dw $ff06
+ .db "TCNT0L"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0L
+XT_TCNT0L:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0L:
+ .dw $46
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Flag register
+VE_TIFR0:
+ .dw $ff05
+ .db "TIFR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR0
+XT_TIFR0:
+ .dw PFA_DOVARIABLE
+PFA_TIFR0:
+ .dw $35
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Mask Register
+VE_TIMSK0:
+ .dw $ff06
+ .db "TIMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK0
+XT_TIMSK0:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK0:
+ .dw $6E
+
+.endif
+
+; ********
+.if WANT_TIMER_COUNTER_1 == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; General Timer/Counter Control Register
+VE_GTCCR:
+ .dw $ff05
+ .db "GTCCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GTCCR
+XT_GTCCR:
+ .dw PFA_DOVARIABLE
+PFA_GTCCR:
+ .dw $43
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare Register 1A
+VE_OCR1A:
+ .dw $ff05
+ .db "OCR1A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1A
+XT_OCR1A:
+ .dw PFA_DOVARIABLE
+PFA_OCR1A:
+ .dw $88
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare Register B
+VE_OCR1B:
+ .dw $ff05
+ .db "OCR1B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1B
+XT_OCR1B:
+ .dw PFA_DOVARIABLE
+PFA_OCR1B:
+ .dw $89
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter 1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw $80
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw $81
+; ( -- addr ) System Constant
+; R( -- )
+; Timer Counter 1 High Byte
+VE_TCNT1H:
+ .dw $ff06
+ .db "TCNT1H"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1H
+XT_TCNT1H:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1H:
+ .dw $85
+; ( -- addr ) System Constant
+; R( -- )
+; Timer Counter 1 Low Byte
+VE_TCNT1L:
+ .dw $ff06
+ .db "TCNT1L"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1L
+XT_TCNT1L:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1L:
+ .dw $84
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Flag register
+VE_TIFR1:
+ .dw $ff05
+ .db "TIFR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR1
+XT_TIFR1:
+ .dw PFA_DOVARIABLE
+PFA_TIFR1:
+ .dw $36
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Mask Register
+VE_TIMSK1:
+ .dw $ff06
+ .db "TIMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK1
+XT_TIMSK1:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK1:
+ .dw $6F
+
+.endif
+
+; ********
+.if WANT_VOLTAGE_REGULATOR == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Regulator Operating Condition Register
+VE_ROCR:
+ .dw $ff04
+ .db "ROCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ROCR
+XT_ROCR:
+ .dw PFA_DOVARIABLE
+PFA_ROCR:
+ .dw $C8
+
+.endif
+
+; ********
+.if WANT_WATCHDOG == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCSR:
+ .dw $ff06
+ .db "WDTCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCSR
+XT_WDTCSR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCSR:
+ .dw $60
+
+.endif
diff --git a/amforth-6.5/avr8/devices/atmega16hva/device.py b/amforth-6.5/avr8/devices/atmega16hva/device.py
new file mode 100644
index 0000000..fdbd4c4
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega16hva/device.py
@@ -0,0 +1,274 @@
+# Generated Automatically
+
+# Partname ATmega16HVA
+
+MCUREGS = {
+# Interrupt Vectors
+ 'BPINTAddr' : '#2', # Battery Protection Interrupt
+ 'VREGMONAddr' : '#4', # Voltage regulator monitor interrupt
+ 'INT0Addr' : '#6', # External Interrupt Request 0
+ 'INT1Addr' : '#8', # External Interrupt Request 1
+ 'INT2Addr' : '#10', # External Interrupt Request 2
+ 'WDTAddr' : '#12', # Watchdog Timeout Interrupt
+ 'TIMER1_ICAddr' : '#14', # Timer 1 Input capture
+ 'TIMER1_COMPAAddr' : '#16', # Timer 1 Compare Match A
+ 'TIMER1_COMPBAddr' : '#18', # Timer 1 Compare Match B
+ 'TIMER1_OVFAddr' : '#20', # Timer 1 overflow
+ 'TIMER0_ICAddr' : '#22', # Timer 0 Input Capture
+ 'TIMER0_COMPAAddr' : '#24', # Timer 0 Comapre Match A
+ 'TIMER0_COMPBAddr' : '#26', # Timer 0 Compare Match B
+ 'TIMER0_OVFAddr' : '#28', # Timer 0 Overflow
+ 'SPI_STCAddr' : '#30', # SPI Serial transfer complete
+ 'VADCAddr' : '#32', # Voltage ADC Conversion Complete
+ 'CCADC_CONVAddr' : '#34', # Coulomb Counter ADC Conversion Complete
+ 'CCADC_REG_CURAddr' : '#36', # Coloumb Counter ADC Regular Current
+ 'CCADC_ACCAddr' : '#38', # Coloumb Counter ADC Accumulator
+ 'EE_READYAddr' : '#40', # EEPROM Ready
+
+# Module AD_CONVERTER
+ 'VADMUX' : '$7c', # The VADC multiplexer Selection
+ 'VADMUX_VADMUX': '$f', # Analog Channel and Gain Select
+ 'VADC' : '$78', # VADC Data Register Bytes
+ 'VADCSR' : '$7a', # The VADC Control and Status re
+ 'VADCSR_VADEN': '$8', # VADC Enable
+ 'VADCSR_VADSC': '$4', # VADC Satrt Conversion
+ 'VADCSR_VADCCIF': '$2', # VADC Conversion Complete Inter
+ 'VADCSR_VADCCIE': '$1', # VADC Conversion Complete Inter
+
+# Module WATCHDOG
+ 'WDTCSR' : '$60', # Watchdog Timer Control Registe
+ 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
+ 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
+ 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
+ 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
+ 'WDTCSR_WDE': '$8', # Watch Dog Enable
+
+# Module BANDGAP
+ 'BGCRR' : '$d1', # Bandgap Calibration of Resisto
+ 'BGCCR' : '$d0', # Bandgap Calibration Register
+ 'BGCCR_BGD': '$80', # Setting the BGD bit to one wil
+ 'BGCCR_BGCC': '$3f', # BG Calibration of PTAT Current
+
+# Module EXTERNAL_INTERRUPT
+ 'EICRA' : '$69', # External Interrupt Control Reg
+ 'EICRA_ISC2': '$30', # External Interrupt Sense Contr
+ 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
+ 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
+ 'EIMSK' : '$3d', # External Interrupt Mask Regist
+ 'EIMSK_INT': '$7', # External Interrupt Request 2 E
+ 'EIFR' : '$3c', # External Interrupt Flag Regist
+ 'EIFR_INTF': '$7', # External Interrupt Flags
+
+# Module PORTC
+ 'PORTC' : '$28', # Port C Data Register
+ 'PINC' : '$26', # Port C Input Pins
+
+# Module PORTA
+ 'PORTA' : '$22', # Port A Data Register
+ 'DDRA' : '$21', # Port A Data Direction Register
+ 'PINA' : '$20', # Port A Input Pins
+
+# Module FET
+ 'FCSR' : '$f0', # FET Control and Status Registe
+ 'FCSR_DUVRD': '$8', # Deep Under-Voltage Recovery Di
+ 'FCSR_CPS': '$4', # Current Protection Status
+ 'FCSR_DFE': '$2', # Discharge FET Enable
+ 'FCSR_CFE': '$1', # Charge FET Enable
+
+# Module SPI
+ 'SPCR' : '$4c', # SPI Control Register
+ 'SPCR_SPIE': '$80', # SPI Interrupt Enable
+ 'SPCR_SPE': '$40', # SPI Enable
+ 'SPCR_DORD': '$20', # Data Order
+ 'SPCR_MSTR': '$10', # Master/Slave Select
+ 'SPCR_CPOL': '$8', # Clock polarity
+ 'SPCR_CPHA': '$4', # Clock Phase
+ 'SPCR_SPR': '$3', # SPI Clock Rate Selects
+ 'SPSR' : '$4d', # SPI Status Register
+ 'SPSR_SPIF': '$80', # SPI Interrupt Flag
+ 'SPSR_WCOL': '$40', # Write Collision Flag
+ 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
+ 'SPDR' : '$4e', # SPI Data Register
+
+# Module BOOT_LOAD
+ 'SPMCSR' : '$57', # Store Program Memory Control a
+ 'SPMCSR_SIGRD': '$20', # Signature Row Read
+ 'SPMCSR_CTPB': '$10', # Clear Temporary Page Buffer
+ 'SPMCSR_RFLB': '$8', # Read Fuse and Lock Bits
+ 'SPMCSR_PGWRT': '$4', # Page Write
+ 'SPMCSR_PGERS': '$2', # Page Erase
+ 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
+
+# Module PORTB
+ 'PORTB' : '$25', # Data Register, Port B
+ 'DDRB' : '$24', # Data Direction Register, Port
+ 'PINB' : '$23', # Input Pins, Port B
+
+# Module CPU
+ 'SREG' : '$5f', # Status Register
+ 'SREG_I': '$80', # Global Interrupt Enable
+ 'SREG_T': '$40', # Bit Copy Storage
+ 'SREG_H': '$20', # Half Carry Flag
+ 'SREG_S': '$10', # Sign Bit
+ 'SREG_V': '$8', # Two's Complement Overflow Flag
+ 'SREG_N': '$4', # Negative Flag
+ 'SREG_Z': '$2', # Zero Flag
+ 'SREG_C': '$1', # Carry Flag
+ 'SP' : '$5d', # Stack Pointer
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_CKOE': '$20', # Clock Output Enable
+ 'MCUCR_PUD': '$10', # Pull-up disable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_OCDRF': '$10', # OCD Reset Flag
+ 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
+ 'MCUSR_BODRF': '$4', # Brown-out Reset Flag
+ 'MCUSR_EXTRF': '$2', # External Reset Flag
+ 'MCUSR_PORF': '$1', # Power-on reset flag
+ 'FOSCCAL' : '$66', # Fast Oscillator Calibration Va
+ 'OSICSR' : '$37', # Oscillator Sampling Interface
+ 'OSICSR_OSISEL0': '$10', # Oscillator Sampling Interface
+ 'OSICSR_OSIST': '$2', # Oscillator Sampling Interface
+ 'OSICSR_OSIEN': '$1', # Oscillator Sampling Interface
+ 'SMCR' : '$53', # Sleep Mode Control Register
+ 'SMCR_SM': '$e', # Sleep Mode Select bits
+ 'SMCR_SE': '$1', # Sleep Enable
+ 'GPIOR2' : '$4b', # General Purpose IO Register 2
+ 'GPIOR1' : '$4a', # General Purpose IO Register 1
+ 'GPIOR0' : '$3e', # General Purpose IO Register 0
+ 'DIDR0' : '$7e', # Digital Input Disable Register
+ 'DIDR0_PA1DID': '$2', # When this bit is written logic
+ 'DIDR0_PA0DID': '$1', # When this bit is written logic
+ 'PRR0' : '$64', # Power Reduction Register 0
+ 'PRR0_PRVRM': '$20', # Power Reduction Voltage Regula
+ 'PRR0_PRSPI': '$8', # Power reduction SPI
+ 'PRR0_PRTIM1': '$4', # Power Reduction Timer/Counter1
+ 'PRR0_PRTIM0': '$2', # Power Reduction Timer/Counter0
+ 'PRR0_PRVADC': '$1', # Power Reduction V-ADC
+ 'CLKPR' : '$61', # Clock Prescale Register
+ 'CLKPR_CLKPCE': '$80', # Clock Prescaler Change Enable
+ 'CLKPR_CLKPS': '$3', # Clock Prescaler Select Bits
+
+# Module BATTERY_PROTECTION
+ 'BPPLR' : '$fe', # Battery Protection Parameter L
+ 'BPPLR_BPPLE': '$2', # Battery Protection Parameter L
+ 'BPPLR_BPPL': '$1', # Battery Protection Parameter L
+ 'BPCR' : '$fd', # Battery Protection Control Reg
+ 'BPCR_SCD': '$10', # Short Circuit Protection Disab
+ 'BPCR_DOCD': '$8', # Discharge Over-current Protect
+ 'BPCR_COCD': '$4', # Charge Over-current Protection
+ 'BPCR_DHCD': '$2', # Discharge High-current Protect
+ 'BPCR_CHCD': '$1', # Charge High-current Protection
+ 'BPHCTR' : '$fc', # Battery Protection Short-curre
+ 'BPOCTR' : '$fb', # Battery Protection Over-curren
+ 'BPSCTR' : '$fa', # Battery Protection Short-curre
+ 'BPCHCD' : '$f9', # Battery Protection Charge-High
+ 'BPDHCD' : '$f8', # Battery Protection Discharge-H
+ 'BPCOCD' : '$f7', # Battery Protection Charge-Over
+ 'BPDOCD' : '$f6', # Battery Protection Discharge-O
+ 'BPSCD' : '$f5', # Battery Protection Short-Circu
+ 'BPIFR' : '$f3', # Battery Protection Interrupt F
+ 'BPIFR_SCIF': '$10', # Short-circuit Protection Activ
+ 'BPIFR_DOCIF': '$8', # Discharge Over-current Protect
+ 'BPIFR_COCIF': '$4', # Charge Over-current Protection
+ 'BPIFR_DHCIF': '$2', # Disharge High-current Protecti
+ 'BPIFR_CHCIF': '$1', # Charge High-current Protection
+ 'BPIMSK' : '$f2', # Battery Protection Interrupt M
+ 'BPIMSK_SCIE': '$10', # Short-circuit Protection Activ
+ 'BPIMSK_DOCIE': '$8', # Discharge Over-current Protect
+ 'BPIMSK_COCIE': '$4', # Charge Over-current Protection
+ 'BPIMSK_DHCIE': '$2', # Discharger High-current Protec
+ 'BPIMSK_CHCIE': '$1', # Charger High-current Protectio
+
+# Module EEPROM
+ 'EEAR' : '$41', # EEPROM Read/Write Access
+ 'EEDR' : '$40', # EEPROM Data Register
+ 'EECR' : '$3f', # EEPROM Control Register
+ 'EECR_EEPM': '$30', #
+ 'EECR_EERIE': '$8', # EEProm Ready Interrupt Enable
+ 'EECR_EEMPE': '$4', # EEPROM Master Write Enable
+ 'EECR_EEPE': '$2', # EEPROM Write Enable
+ 'EECR_EERE': '$1', # EEPROM Read Enable
+
+# Module TIMER_COUNTER_1
+ 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
+ 'TCCR1B_CS': '$7', # Clock Select1 bis
+ 'TCCR1A' : '$80', # Timer/Counter 1 Control Regist
+ 'TCCR1A_TCW1': '$80', # Timer/Counter Width
+ 'TCCR1A_ICEN1': '$40', # Input Capture Mode Enable
+ 'TCCR1A_ICNC1': '$20', # Input Capture Noise Canceler
+ 'TCCR1A_ICES1': '$10', # Input Capture Edge Select
+ 'TCCR1A_ICS1': '$8', # Input Capture Select
+ 'TCCR1A_WGM10': '$1', # Waveform Generation Mode
+ 'TCNT1' : '$84', # Timer Counter 1 Bytes
+ 'OCR1A' : '$88', # Output Compare Register 1A
+ 'OCR1B' : '$89', # Output Compare Register B
+ 'TIMSK1' : '$6f', # Timer/Counter Interrupt Mask R
+ 'TIMSK1_ICIE1': '$8', # Timer/Counter n Input Capture
+ 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
+ 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
+ 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
+ 'TIFR1' : '$36', # Timer/Counter Interrupt Flag r
+ 'TIFR1_ICF1': '$8', # Timer/Counter 1 Input Capture
+ 'TIFR1_OCF1B': '$4', # Timer/Counter1 Output Compare
+ 'TIFR1_OCF1A': '$2', # Timer/Counter1 Output Compare
+ 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSRSYNC': '$1', # Prescaler Reset
+
+# Module COULOMB_COUNTER
+ 'CADCSRA' : '$e4', # CC-ADC Control and Status Regi
+ 'CADCSRA_CADEN': '$80', # When the CADEN bit is cleared
+ 'CADCSRA_CADPOL': '$40', #
+ 'CADCSRA_CADUB': '$20', # CC_ADC Update Busy
+ 'CADCSRA_CADAS': '$18', # CC_ADC Accumulate Current Sele
+ 'CADCSRA_CADSI': '$6', # The CADSI bits determine the c
+ 'CADCSRA_CADSE': '$1', # When the CADSE bit is written
+ 'CADCSRB' : '$e5', # CC-ADC Control and Status Regi
+ 'CADCSRB_CADACIE': '$40', #
+ 'CADCSRB_CADRCIE': '$20', # Regular Current Interrupt Enab
+ 'CADCSRB_CADICIE': '$10', # CAD Instantenous Current Inter
+ 'CADCSRB_CADACIF': '$4', # CC-ADC Accumulate Current Inte
+ 'CADCSRB_CADRCIF': '$2', # CC-ADC Accumulate Current Inte
+ 'CADCSRB_CADICIF': '$1', # CC-ADC Instantaneous Current I
+ 'CADIC' : '$e8', # CC-ADC Instantaneous Current
+ 'CADAC3' : '$e3', # ADC Accumulate Current
+ 'CADAC2' : '$e2', # ADC Accumulate Current
+ 'CADAC1' : '$e1', # ADC Accumulate Current
+ 'CADAC0' : '$e0', # ADC Accumulate Current
+ 'CADRC' : '$e6', # CC-ADC Regular Current
+
+# Module TIMER_COUNTER_0
+ 'TCCR0A' : '$44', # Timer/Counter0 Control Registe
+ 'TCCR0A_TCW0': '$80', # Timer/Counter Width
+ 'TCCR0A_ICEN0': '$40', # Input Capture Mode Enable
+ 'TCCR0A_ICNC0': '$20', # Input Capture Noise Canceler
+ 'TCCR0A_ICES0': '$10', # Input Capture Edge Select
+ 'TCCR0A_ICS0': '$8', # Input Capture Select
+ 'TCCR0A_WGM00': '$1', # Clock Select0 bit 0
+ 'TCCR0B' : '$45', # Timer/Counter0 Control Registe
+ 'TCCR0B_CS02': '$4', # Clock Select0 bit 2
+ 'TCCR0B_CS01': '$2', # Clock Select0 bit 1
+ 'TCCR0B_CS00': '$1', # Clock Select0 bit 0
+ 'TCNT0' : '$46', # Timer Counter 0 Bytes
+ 'OCR0A' : '$48', # Output compare Register A
+ 'OCR0B' : '$49', # Output compare Register B
+ 'TIMSK0' : '$6e', # Timer/Counter Interrupt Mask R
+ 'TIMSK0_ICIE0': '$8', # Timer/Counter n Input Capture
+ 'TIMSK0_OCIE0B': '$4', # Output Compare Interrupt Enabl
+ 'TIMSK0_OCIE0A': '$2', # Output Compare Interrupt Enabl
+ 'TIMSK0_TOIE0': '$1', # Overflow Interrupt Enable
+ 'TIFR0' : '$35', # Timer/Counter Interrupt Flag r
+ 'TIFR0_ICF0': '$8', # Timer/Counter Interrupt Flag R
+ 'TIFR0_OCF0B': '$4', # Output Compare Flag
+ 'TIFR0_OCF0A': '$2', # Output Compare Flag
+ 'TIFR0_TOV0': '$1', # Overflow Flag
+
+# Module VOLTAGE_REGULATOR
+ 'ROCR' : '$c8', # Regulator Operating Condition
+ 'ROCR_ROCS': '$80', # ROC Status
+ 'ROCR_ROCWIF': '$2', # ROC Warning Interrupt Flag
+ 'ROCR_ROCWIE': '$1', # ROC Warning Interrupt Enable
+
+ '__amforth_dummy':'0'
+}
diff --git a/amforth-6.5/avr8/devices/atmega16hva2/atmega16hva2.frt b/amforth-6.5/avr8/devices/atmega16hva2/atmega16hva2.frt
new file mode 100644
index 0000000..fe9f503
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega16hva2/atmega16hva2.frt
@@ -0,0 +1,144 @@
+\ Partname: ATmega16HVA2
+\ Built using part description XML file version 1
+\ generated automatically
+
+hex
+
+\ AD_CONVERTER
+79 constant VADCH \ VADC Data Register High Byte
+78 constant VADCL \ VADC Data Register Low Byte
+7A constant VADCSR \ The VADC Control and Status register
+7C constant VADMUX \ The VADC multiplexer Selection Register
+
+\ BANDGAP
+D0 constant BGCCR \ Bandgap Calibration Register
+D1 constant BGCRR \ Bandgap Calibration of Resistor Ladder
+
+\ BATTERY_PROTECTION
+F9 constant BPCHCD \ Battery Protection Charge-High-current Detection Level Register
+F7 constant BPCOCD \ Battery Protection Charge-Over-current Detection Level Register
+FD constant BPCR \ Battery Protection Control Register
+F8 constant BPDHCD \ Battery Protection Discharge-High-current Detection Level Register
+F6 constant BPDOCD \ Battery Protection Discharge-Over-current Detection Level Register
+FC constant BPHCTR \ Battery Protection Short-current Timing Register
+F3 constant BPIFR \ Battery Protection Interrupt Flag Register
+F2 constant BPIMSK \ Battery Protection Interrupt Mask Register
+FB constant BPOCTR \ Battery Protection Over-current Timing Register
+FE constant BPPLR \ Battery Protection Parameter Lock Register
+F5 constant BPSCD \ Battery Protection Short-Circuit Detection Level Register
+FA constant BPSCTR \ Battery Protection Short-current Timing Register
+
+\ BOOT_LOAD
+57 constant SPMCSR \ Store Program Memory Control and Status Register
+
+\ COULOMB_COUNTER
+E0 constant CADAC0 \ ADC Accumulate Current
+E1 constant CADAC1 \ ADC Accumulate Current
+E2 constant CADAC2 \ ADC Accumulate Current
+E3 constant CADAC3 \ ADC Accumulate Current
+E4 constant CADCSRA \ CC-ADC Control and Status Register A
+E5 constant CADCSRB \ CC-ADC Control and Status Register B
+E9 constant CADICH \ CC-ADC Instantaneous Current
+E8 constant CADICL \ CC-ADC Instantaneous Current
+E6 constant CADRC \ CC-ADC Regular Current
+
+\ CPU
+61 constant CLKPR \ Clock Prescale Register
+7E constant DIDR0 \ Digital Input Disable Register
+66 constant FOSCCAL \ Fast Oscillator Calibration Value
+3E constant GPIOR0 \ General Purpose IO Register 0
+4A constant GPIOR1 \ General Purpose IO Register 1
+4B constant GPIOR2 \ General Purpose IO Register 2
+55 constant MCUCR \ MCU Control Register
+54 constant MCUSR \ MCU Status Register
+37 constant OSICSR \ Oscillator Sampling Interface Control and Status Register
+64 constant PRR0 \ Power Reduction Register 0
+53 constant SMCR \ Sleep Mode Control Register
+5E constant SPH \ Stack Pointer High
+5D constant SPL \ Stack Pointer Low
+5F constant SREG \ Status Register
+
+\ EEPROM
+41 constant EEAR \ EEPROM Read/Write Access
+3F constant EECR \ EEPROM Control Register
+40 constant EEDR \ EEPROM Data Register
+
+\ EXTERNAL_INTERRUPT
+69 constant EICRA \ External Interrupt Control Register
+3C constant EIFR \ External Interrupt Flag Register
+3D constant EIMSK \ External Interrupt Mask Register
+68 constant PCICR \ Pin Change Interrupt Control Register
+3B constant PCIFR \ Pin Change Interrupt Flag Register
+6B constant PCMSK0 \ Pin Change Mask Register 0
+
+\ FET
+F0 constant FCSR \ FET Control and Status Register
+
+\ PORTA
+21 constant DDRA \ Port A Data Direction Register
+20 constant PINA \ Port A Input Pins
+22 constant PORTA \ Port A Data Register
+
+\ PORTB
+24 constant DDRB \ Data Direction Register, Port B
+23 constant PINB \ Input Pins, Port B
+25 constant PORTB \ Data Register, Port B
+
+\ PORTC
+26 constant PINC \ Port C Input Pins
+28 constant PORTC \ Port C Data Register
+
+\ SPI
+4c constant SPCR \ SPI Control Register
+4e constant SPDR \ SPI Data Register
+4d constant SPSR \ SPI Status Register
+
+\ TIMER_COUNTER_0
+48 constant OCR0A \ Output compare Register A
+49 constant OCR0B \ Output compare Register B
+44 constant TCCR0A \ Timer/Counter0 Control Register
+45 constant TCCR0B \ Timer/Counter0 Control Register
+47 constant TCNT0H \ Timer Counter 0 High Byte
+46 constant TCNT0L \ Timer Counter 0 Low Byte
+35 constant TIFR0 \ Timer/Counter Interrupt Flag register
+6E constant TIMSK0 \ Timer/Counter Interrupt Mask Register
+
+\ TIMER_COUNTER_1
+43 constant GTCCR \ General Timer/Counter Control Register
+88 constant OCR1A \ Output Compare Register 1A
+89 constant OCR1B \ Output Compare Register B
+80 constant TCCR1A \ Timer/Counter 1 Control Register A
+81 constant TCCR1B \ Timer/Counter1 Control Register B
+85 constant TCNT1H \ Timer Counter 1 High Byte
+84 constant TCNT1L \ Timer Counter 1 Low Byte
+36 constant TIFR1 \ Timer/Counter Interrupt Flag register
+6F constant TIMSK1 \ Timer/Counter Interrupt Mask Register
+
+\ VOLTAGE_REGULATOR
+C8 constant ROCR \ Regulator Operating Condition Register
+
+\ WATCHDOG
+60 constant WDTCSR \ Watchdog Timer Control Register
+
+\ Interrupts
+0002 constant BPINTAddr \ Battery Protection Interrupt
+0004 constant VREGMONAddr \ Voltage regulator monitor interrupt
+0006 constant INT0Addr \ External Interrupt Request 0
+0008 constant INT1Addr \ External Interrupt Request 1
+000A constant INT2Addr \ External Interrupt Request 2
+000C constant PCINT0Addr \ Pin Change Interrupt Request 0
+000E constant WDTAddr \ Watchdog Timeout Interrupt
+0010 constant TIMER1_ICAddr \ Timer 1 Input capture
+0012 constant TIMER1_COMPAAddr \ Timer 1 Compare Match A
+0014 constant TIMER1_COMPBAddr \ Timer 1 Compare Match B
+0016 constant TIMER1_OVFAddr \ Timer 1 overflow
+0018 constant TIMER0_ICAddr \ Timer 0 Input Capture
+001A constant TIMER0_COMPAAddr \ Timer 0 Comapre Match A
+001C constant TIMER0_COMPBAddr \ Timer 0 Compare Match B
+001E constant TIMER0_OVFAddr \ Timer 0 Overflow
+0020 constant SPI;STCAddr \ SPI Serial transfer complete
+0022 constant VADCAddr \ Voltage ADC Conversion Complete
+0024 constant CCADC_CONVAddr \ Coulomb Counter ADC Conversion Complete
+0026 constant CCADC_REG_CURAddr \ Coloumb Counter ADC Regular Current
+0028 constant CCADC_ACCAddr \ Coloumb Counter ADC Accumulator
+02A constant EE_READYAddr \ EEPROM Ready
diff --git a/amforth-6.5/avr8/devices/atmega16hva2/device.asm b/amforth-6.5/avr8/devices/atmega16hva2/device.asm
new file mode 100644
index 0000000..7ce9455
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega16hva2/device.asm
@@ -0,0 +1,116 @@
+; Partname: ATmega16HVA2
+; Built using part description XML file version 1
+; generated automatically, do not edit
+
+.nolist
+ .include "m16HVA2def.inc"
+.list
+
+.equ ramstart = $100
+.equ CELLSIZE = 2
+.macro readflashcell
+ lsl zl
+ rol zh
+ lpm @0, Z+
+ lpm @1, Z+
+.endmacro
+.macro writeflashcell
+ lsl zl
+ rol zh
+.endmacro
+
+; the following definitions are shortcuts for the respective forth source segments if set to 1
+.set WANT_AD_CONVERTER = 0
+.set WANT_BANDGAP = 0
+.set WANT_BATTERY_PROTECTION = 0
+.set WANT_BOOT_LOAD = 0
+.set WANT_COULOMB_COUNTER = 0
+.set WANT_CPU = 0
+.set WANT_EEPROM = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_FET = 0
+.set WANT_PORTA = 0
+.set WANT_PORTB = 0
+.set WANT_PORTC = 0
+.set WANT_SPI = 0
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_VOLTAGE_REGULATOR = 0
+.set WANT_WATCHDOG = 0
+
+
+.ifndef SPMEN
+ .equ SPMEN = SELFPRGEN
+.endif
+
+.ifndef SPMCSR
+ .equ SPMCSR = SPMCR
+.endif
+
+.ifndef EEPE
+ .equ EEPE = EEWE
+.endif
+
+.ifndef EEMPE
+ .equ EEMPE = EEMWE
+.endif
+.equ intvecsize = 2 ; please verify; flash size: 16384 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.equ INTVECTORS = 22
+.org $0002
+ rcall isr ; Battery Protection Interrupt
+.org $0004
+ rcall isr ; Voltage regulator monitor interrupt
+.org $0006
+ rcall isr ; External Interrupt Request 0
+.org $0008
+ rcall isr ; External Interrupt Request 1
+.org $000A
+ rcall isr ; External Interrupt Request 2
+.org $000C
+ rcall isr ; Pin Change Interrupt Request 0
+.org $000E
+ rcall isr ; Watchdog Timeout Interrupt
+.org $0010
+ rcall isr ; Timer 1 Input capture
+.org $0012
+ rcall isr ; Timer 1 Compare Match A
+.org $0014
+ rcall isr ; Timer 1 Compare Match B
+.org $0016
+ rcall isr ; Timer 1 overflow
+.org $0018
+ rcall isr ; Timer 0 Input Capture
+.org $001A
+ rcall isr ; Timer 0 Comapre Match A
+.org $001C
+ rcall isr ; Timer 0 Compare Match B
+.org $001E
+ rcall isr ; Timer 0 Overflow
+.org $0020
+ rcall isr ; SPI Serial transfer complete
+.org $0022
+ rcall isr ; Voltage ADC Conversion Complete
+.org $0024
+ rcall isr ; Coulomb Counter ADC Conversion Complete
+.org $0026
+ rcall isr ; Coloumb Counter ADC Regular Current
+.org $0028
+ rcall isr ; Coloumb Counter ADC Accumulator
+.org $02A
+ rcall isr ; EEPROM Ready
+.nooverlap
+mcu_info:
+mcu_ramsize:
+ .dw 1024
+mcu_eepromsize:
+ .dw 256
+mcu_maxdp:
+ .dw 0 ; minimum of 0 (from XML) and 0xffff
+mcu_numints:
+ .dw 22
+mcu_name:
+ .dw 12
+ .db "ATmega16HVA2"
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega16hva2/device.inc b/amforth-6.5/avr8/devices/atmega16hva2/device.inc
new file mode 100644
index 0000000..c0f9e0a
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega16hva2/device.inc
@@ -0,0 +1,1089 @@
+; Partname: ATmega16HVA2
+; Built using part description XML file version 1
+; generated automatically, no not edit
+
+; ********
+.if WANT_AD_CONVERTER == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; VADC Data Register High Byte
+VE_VADCH:
+ .dw $ff05
+ .db "VADCH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_VADCH
+XT_VADCH:
+ .dw PFA_DOVARIABLE
+PFA_VADCH:
+ .dw $79
+; ( -- addr ) System Constant
+; R( -- )
+; VADC Data Register Low Byte
+VE_VADCL:
+ .dw $ff05
+ .db "VADCL",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_VADCL
+XT_VADCL:
+ .dw PFA_DOVARIABLE
+PFA_VADCL:
+ .dw $78
+; ( -- addr ) System Constant
+; R( -- )
+; The VADC Control and Status register
+VE_VADCSR:
+ .dw $ff06
+ .db "VADCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_VADCSR
+XT_VADCSR:
+ .dw PFA_DOVARIABLE
+PFA_VADCSR:
+ .dw $7A
+; ( -- addr ) System Constant
+; R( -- )
+; The VADC multiplexer Selection Register
+VE_VADMUX:
+ .dw $ff06
+ .db "VADMUX"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_VADMUX
+XT_VADMUX:
+ .dw PFA_DOVARIABLE
+PFA_VADMUX:
+ .dw $7C
+
+.endif
+
+; ********
+.if WANT_BANDGAP == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Bandgap Calibration Register
+VE_BGCCR:
+ .dw $ff05
+ .db "BGCCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_BGCCR
+XT_BGCCR:
+ .dw PFA_DOVARIABLE
+PFA_BGCCR:
+ .dw $D0
+; ( -- addr ) System Constant
+; R( -- )
+; Bandgap Calibration of Resistor Ladder
+VE_BGCRR:
+ .dw $ff05
+ .db "BGCRR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_BGCRR
+XT_BGCRR:
+ .dw PFA_DOVARIABLE
+PFA_BGCRR:
+ .dw $D1
+
+.endif
+
+; ********
+.if WANT_BATTERY_PROTECTION == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Battery Protection Charge-High-current Detection Level Register
+VE_BPCHCD:
+ .dw $ff06
+ .db "BPCHCD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_BPCHCD
+XT_BPCHCD:
+ .dw PFA_DOVARIABLE
+PFA_BPCHCD:
+ .dw $F9
+; ( -- addr ) System Constant
+; R( -- )
+; Battery Protection Charge-Over-current Detection Level Register
+VE_BPCOCD:
+ .dw $ff06
+ .db "BPCOCD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_BPCOCD
+XT_BPCOCD:
+ .dw PFA_DOVARIABLE
+PFA_BPCOCD:
+ .dw $F7
+; ( -- addr ) System Constant
+; R( -- )
+; Battery Protection Control Register
+VE_BPCR:
+ .dw $ff04
+ .db "BPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_BPCR
+XT_BPCR:
+ .dw PFA_DOVARIABLE
+PFA_BPCR:
+ .dw $FD
+; ( -- addr ) System Constant
+; R( -- )
+; Battery Protection Discharge-High-current Detection Level Register
+VE_BPDHCD:
+ .dw $ff06
+ .db "BPDHCD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_BPDHCD
+XT_BPDHCD:
+ .dw PFA_DOVARIABLE
+PFA_BPDHCD:
+ .dw $F8
+; ( -- addr ) System Constant
+; R( -- )
+; Battery Protection Discharge-Over-current Detection Level Register
+VE_BPDOCD:
+ .dw $ff06
+ .db "BPDOCD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_BPDOCD
+XT_BPDOCD:
+ .dw PFA_DOVARIABLE
+PFA_BPDOCD:
+ .dw $F6
+; ( -- addr ) System Constant
+; R( -- )
+; Battery Protection Short-current Timing Register
+VE_BPHCTR:
+ .dw $ff06
+ .db "BPHCTR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_BPHCTR
+XT_BPHCTR:
+ .dw PFA_DOVARIABLE
+PFA_BPHCTR:
+ .dw $FC
+; ( -- addr ) System Constant
+; R( -- )
+; Battery Protection Interrupt Flag Register
+VE_BPIFR:
+ .dw $ff05
+ .db "BPIFR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_BPIFR
+XT_BPIFR:
+ .dw PFA_DOVARIABLE
+PFA_BPIFR:
+ .dw $F3
+; ( -- addr ) System Constant
+; R( -- )
+; Battery Protection Interrupt Mask Register
+VE_BPIMSK:
+ .dw $ff06
+ .db "BPIMSK"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_BPIMSK
+XT_BPIMSK:
+ .dw PFA_DOVARIABLE
+PFA_BPIMSK:
+ .dw $F2
+; ( -- addr ) System Constant
+; R( -- )
+; Battery Protection Over-current Timing Register
+VE_BPOCTR:
+ .dw $ff06
+ .db "BPOCTR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_BPOCTR
+XT_BPOCTR:
+ .dw PFA_DOVARIABLE
+PFA_BPOCTR:
+ .dw $FB
+; ( -- addr ) System Constant
+; R( -- )
+; Battery Protection Parameter Lock Register
+VE_BPPLR:
+ .dw $ff05
+ .db "BPPLR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_BPPLR
+XT_BPPLR:
+ .dw PFA_DOVARIABLE
+PFA_BPPLR:
+ .dw $FE
+; ( -- addr ) System Constant
+; R( -- )
+; Battery Protection Short-Circuit Detection Level Register
+VE_BPSCD:
+ .dw $ff05
+ .db "BPSCD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_BPSCD
+XT_BPSCD:
+ .dw PFA_DOVARIABLE
+PFA_BPSCD:
+ .dw $F5
+; ( -- addr ) System Constant
+; R( -- )
+; Battery Protection Short-current Timing Register
+VE_BPSCTR:
+ .dw $ff06
+ .db "BPSCTR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_BPSCTR
+XT_BPSCTR:
+ .dw PFA_DOVARIABLE
+PFA_BPSCTR:
+ .dw $FA
+
+.endif
+
+; ********
+.if WANT_BOOT_LOAD == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control and Status Register
+VE_SPMCSR:
+ .dw $ff06
+ .db "SPMCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCSR
+XT_SPMCSR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCSR:
+ .dw $57
+
+.endif
+
+; ********
+.if WANT_COULOMB_COUNTER == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Accumulate Current
+VE_CADAC0:
+ .dw $ff06
+ .db "CADAC0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CADAC0
+XT_CADAC0:
+ .dw PFA_DOVARIABLE
+PFA_CADAC0:
+ .dw $E0
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Accumulate Current
+VE_CADAC1:
+ .dw $ff06
+ .db "CADAC1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CADAC1
+XT_CADAC1:
+ .dw PFA_DOVARIABLE
+PFA_CADAC1:
+ .dw $E1
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Accumulate Current
+VE_CADAC2:
+ .dw $ff06
+ .db "CADAC2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CADAC2
+XT_CADAC2:
+ .dw PFA_DOVARIABLE
+PFA_CADAC2:
+ .dw $E2
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Accumulate Current
+VE_CADAC3:
+ .dw $ff06
+ .db "CADAC3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CADAC3
+XT_CADAC3:
+ .dw PFA_DOVARIABLE
+PFA_CADAC3:
+ .dw $E3
+; ( -- addr ) System Constant
+; R( -- )
+; CC-ADC Control and Status Register A
+VE_CADCSRA:
+ .dw $ff07
+ .db "CADCSRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CADCSRA
+XT_CADCSRA:
+ .dw PFA_DOVARIABLE
+PFA_CADCSRA:
+ .dw $E4
+; ( -- addr ) System Constant
+; R( -- )
+; CC-ADC Control and Status Register B
+VE_CADCSRB:
+ .dw $ff07
+ .db "CADCSRB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CADCSRB
+XT_CADCSRB:
+ .dw PFA_DOVARIABLE
+PFA_CADCSRB:
+ .dw $E5
+; ( -- addr ) System Constant
+; R( -- )
+; CC-ADC Instantaneous Current
+VE_CADICH:
+ .dw $ff06
+ .db "CADICH"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CADICH
+XT_CADICH:
+ .dw PFA_DOVARIABLE
+PFA_CADICH:
+ .dw $E9
+; ( -- addr ) System Constant
+; R( -- )
+; CC-ADC Instantaneous Current
+VE_CADICL:
+ .dw $ff06
+ .db "CADICL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CADICL
+XT_CADICL:
+ .dw PFA_DOVARIABLE
+PFA_CADICL:
+ .dw $E8
+; ( -- addr ) System Constant
+; R( -- )
+; CC-ADC Regular Current
+VE_CADRC:
+ .dw $ff05
+ .db "CADRC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CADRC
+XT_CADRC:
+ .dw PFA_DOVARIABLE
+PFA_CADRC:
+ .dw $E6
+
+.endif
+
+; ********
+.if WANT_CPU == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Clock Prescale Register
+VE_CLKPR:
+ .dw $ff05
+ .db "CLKPR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKPR
+XT_CLKPR:
+ .dw PFA_DOVARIABLE
+PFA_CLKPR:
+ .dw $61
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register
+VE_DIDR0:
+ .dw $ff05
+ .db "DIDR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR0
+XT_DIDR0:
+ .dw PFA_DOVARIABLE
+PFA_DIDR0:
+ .dw $7E
+; ( -- addr ) System Constant
+; R( -- )
+; Fast Oscillator Calibration Value
+VE_FOSCCAL:
+ .dw $ff07
+ .db "FOSCCAL",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_FOSCCAL
+XT_FOSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_FOSCCAL:
+ .dw $66
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 0
+VE_GPIOR0:
+ .dw $ff06
+ .db "GPIOR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR0
+XT_GPIOR0:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR0:
+ .dw $3E
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 1
+VE_GPIOR1:
+ .dw $ff06
+ .db "GPIOR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR1
+XT_GPIOR1:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR1:
+ .dw $4A
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 2
+VE_GPIOR2:
+ .dw $ff06
+ .db "GPIOR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR2
+XT_GPIOR2:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR2:
+ .dw $4B
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw $55
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Status Register
+VE_MCUSR:
+ .dw $ff05
+ .db "MCUSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUSR
+XT_MCUSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUSR:
+ .dw $54
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Sampling Interface Control and Status Register
+VE_OSICSR:
+ .dw $ff06
+ .db "OSICSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSICSR
+XT_OSICSR:
+ .dw PFA_DOVARIABLE
+PFA_OSICSR:
+ .dw $37
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register 0
+VE_PRR0:
+ .dw $ff04
+ .db "PRR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR0
+XT_PRR0:
+ .dw PFA_DOVARIABLE
+PFA_PRR0:
+ .dw $64
+; ( -- addr ) System Constant
+; R( -- )
+; Sleep Mode Control Register
+VE_SMCR:
+ .dw $ff04
+ .db "SMCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SMCR
+XT_SMCR:
+ .dw PFA_DOVARIABLE
+PFA_SMCR:
+ .dw $53
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer High
+VE_SPH:
+ .dw $ff03
+ .db "SPH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPH
+XT_SPH:
+ .dw PFA_DOVARIABLE
+PFA_SPH:
+ .dw $5E
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer Low
+VE_SPL:
+ .dw $ff03
+ .db "SPL",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPL
+XT_SPL:
+ .dw PFA_DOVARIABLE
+PFA_SPL:
+ .dw $5D
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw $5F
+
+.endif
+
+; ********
+.if WANT_EEPROM == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Read/Write Access
+VE_EEAR:
+ .dw $ff04
+ .db "EEAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEAR
+XT_EEAR:
+ .dw PFA_DOVARIABLE
+PFA_EEAR:
+ .dw $41
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw $3F
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw $40
+
+.endif
+
+; ********
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register
+VE_EICRA:
+ .dw $ff05
+ .db "EICRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRA
+XT_EICRA:
+ .dw PFA_DOVARIABLE
+PFA_EICRA:
+ .dw $69
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Flag Register
+VE_EIFR:
+ .dw $ff04
+ .db "EIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIFR
+XT_EIFR:
+ .dw PFA_DOVARIABLE
+PFA_EIFR:
+ .dw $3C
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Mask Register
+VE_EIMSK:
+ .dw $ff05
+ .db "EIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIMSK
+XT_EIMSK:
+ .dw PFA_DOVARIABLE
+PFA_EIMSK:
+ .dw $3D
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Interrupt Control Register
+VE_PCICR:
+ .dw $ff05
+ .db "PCICR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCICR
+XT_PCICR:
+ .dw PFA_DOVARIABLE
+PFA_PCICR:
+ .dw $68
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Interrupt Flag Register
+VE_PCIFR:
+ .dw $ff05
+ .db "PCIFR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCIFR
+XT_PCIFR:
+ .dw PFA_DOVARIABLE
+PFA_PCIFR:
+ .dw $3B
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 0
+VE_PCMSK0:
+ .dw $ff06
+ .db "PCMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK0
+XT_PCMSK0:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK0:
+ .dw $6B
+
+.endif
+
+; ********
+.if WANT_FET == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; FET Control and Status Register
+VE_FCSR:
+ .dw $ff04
+ .db "FCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_FCSR
+XT_FCSR:
+ .dw PFA_DOVARIABLE
+PFA_FCSR:
+ .dw $F0
+
+.endif
+
+; ********
+.if WANT_PORTA == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Direction Register
+VE_DDRA:
+ .dw $ff04
+ .db "DDRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRA
+XT_DDRA:
+ .dw PFA_DOVARIABLE
+PFA_DDRA:
+ .dw $21
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Input Pins
+VE_PINA:
+ .dw $ff04
+ .db "PINA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINA
+XT_PINA:
+ .dw PFA_DOVARIABLE
+PFA_PINA:
+ .dw $20
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Register
+VE_PORTA:
+ .dw $ff05
+ .db "PORTA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTA
+XT_PORTA:
+ .dw PFA_DOVARIABLE
+PFA_PORTA:
+ .dw $22
+
+.endif
+
+; ********
+.if WANT_PORTB == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port B
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw $24
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port B
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw $23
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port B
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw $25
+
+.endif
+
+; ********
+.if WANT_PORTC == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Input Pins
+VE_PINC:
+ .dw $ff04
+ .db "PINC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINC
+XT_PINC:
+ .dw PFA_DOVARIABLE
+PFA_PINC:
+ .dw $26
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Register
+VE_PORTC:
+ .dw $ff05
+ .db "PORTC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTC
+XT_PORTC:
+ .dw PFA_DOVARIABLE
+PFA_PORTC:
+ .dw $28
+
+.endif
+
+; ********
+.if WANT_SPI == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR:
+ .dw $ff04
+ .db "SPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR
+XT_SPCR:
+ .dw PFA_DOVARIABLE
+PFA_SPCR:
+ .dw $4c
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR:
+ .dw $ff04
+ .db "SPDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR
+XT_SPDR:
+ .dw PFA_DOVARIABLE
+PFA_SPDR:
+ .dw $4e
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR:
+ .dw $ff04
+ .db "SPSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR
+XT_SPSR:
+ .dw PFA_DOVARIABLE
+PFA_SPSR:
+ .dw $4d
+
+.endif
+
+; ********
+.if WANT_TIMER_COUNTER_0 == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Output compare Register A
+VE_OCR0A:
+ .dw $ff05
+ .db "OCR0A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0A
+XT_OCR0A:
+ .dw PFA_DOVARIABLE
+PFA_OCR0A:
+ .dw $48
+; ( -- addr ) System Constant
+; R( -- )
+; Output compare Register B
+VE_OCR0B:
+ .dw $ff05
+ .db "OCR0B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0B
+XT_OCR0B:
+ .dw PFA_DOVARIABLE
+PFA_OCR0B:
+ .dw $49
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Control Register
+VE_TCCR0A:
+ .dw $ff06
+ .db "TCCR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0A
+XT_TCCR0A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0A:
+ .dw $44
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Control Register
+VE_TCCR0B:
+ .dw $ff06
+ .db "TCCR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0B
+XT_TCCR0B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0B:
+ .dw $45
+; ( -- addr ) System Constant
+; R( -- )
+; Timer Counter 0 High Byte
+VE_TCNT0H:
+ .dw $ff06
+ .db "TCNT0H"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0H
+XT_TCNT0H:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0H:
+ .dw $47
+; ( -- addr ) System Constant
+; R( -- )
+; Timer Counter 0 Low Byte
+VE_TCNT0L:
+ .dw $ff06
+ .db "TCNT0L"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0L
+XT_TCNT0L:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0L:
+ .dw $46
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Flag register
+VE_TIFR0:
+ .dw $ff05
+ .db "TIFR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR0
+XT_TIFR0:
+ .dw PFA_DOVARIABLE
+PFA_TIFR0:
+ .dw $35
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Mask Register
+VE_TIMSK0:
+ .dw $ff06
+ .db "TIMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK0
+XT_TIMSK0:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK0:
+ .dw $6E
+
+.endif
+
+; ********
+.if WANT_TIMER_COUNTER_1 == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; General Timer/Counter Control Register
+VE_GTCCR:
+ .dw $ff05
+ .db "GTCCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GTCCR
+XT_GTCCR:
+ .dw PFA_DOVARIABLE
+PFA_GTCCR:
+ .dw $43
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare Register 1A
+VE_OCR1A:
+ .dw $ff05
+ .db "OCR1A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1A
+XT_OCR1A:
+ .dw PFA_DOVARIABLE
+PFA_OCR1A:
+ .dw $88
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare Register B
+VE_OCR1B:
+ .dw $ff05
+ .db "OCR1B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1B
+XT_OCR1B:
+ .dw PFA_DOVARIABLE
+PFA_OCR1B:
+ .dw $89
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter 1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw $80
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw $81
+; ( -- addr ) System Constant
+; R( -- )
+; Timer Counter 1 High Byte
+VE_TCNT1H:
+ .dw $ff06
+ .db "TCNT1H"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1H
+XT_TCNT1H:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1H:
+ .dw $85
+; ( -- addr ) System Constant
+; R( -- )
+; Timer Counter 1 Low Byte
+VE_TCNT1L:
+ .dw $ff06
+ .db "TCNT1L"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1L
+XT_TCNT1L:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1L:
+ .dw $84
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Flag register
+VE_TIFR1:
+ .dw $ff05
+ .db "TIFR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR1
+XT_TIFR1:
+ .dw PFA_DOVARIABLE
+PFA_TIFR1:
+ .dw $36
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Mask Register
+VE_TIMSK1:
+ .dw $ff06
+ .db "TIMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK1
+XT_TIMSK1:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK1:
+ .dw $6F
+
+.endif
+
+; ********
+.if WANT_VOLTAGE_REGULATOR == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Regulator Operating Condition Register
+VE_ROCR:
+ .dw $ff04
+ .db "ROCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ROCR
+XT_ROCR:
+ .dw PFA_DOVARIABLE
+PFA_ROCR:
+ .dw $C8
+
+.endif
+
+; ********
+.if WANT_WATCHDOG == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCSR:
+ .dw $ff06
+ .db "WDTCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCSR
+XT_WDTCSR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCSR:
+ .dw $60
+
+.endif
diff --git a/amforth-6.5/avr8/devices/atmega16hva2/device.py b/amforth-6.5/avr8/devices/atmega16hva2/device.py
new file mode 100644
index 0000000..fb080dc
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega16hva2/device.py
@@ -0,0 +1,108 @@
+# Partname: ATmega16HVA2
+# Built using part description XML file version 1
+# generated automatically, do not edit
+MCUREGS = {
+ 'VADCH': '$79',
+ 'VADCL': '$78',
+ 'VADCSR': '$7A',
+ 'VADMUX': '$7C',
+ 'BGCCR': '$D0',
+ 'BGCRR': '$D1',
+ 'BPCHCD': '$F9',
+ 'BPCOCD': '$F7',
+ 'BPCR': '$FD',
+ 'BPDHCD': '$F8',
+ 'BPDOCD': '$F6',
+ 'BPHCTR': '$FC',
+ 'BPIFR': '$F3',
+ 'BPIMSK': '$F2',
+ 'BPOCTR': '$FB',
+ 'BPPLR': '$FE',
+ 'BPSCD': '$F5',
+ 'BPSCTR': '$FA',
+ 'SPMCSR': '$57',
+ 'CADAC0': '$E0',
+ 'CADAC1': '$E1',
+ 'CADAC2': '$E2',
+ 'CADAC3': '$E3',
+ 'CADCSRA': '$E4',
+ 'CADCSRB': '$E5',
+ 'CADICH': '$E9',
+ 'CADICL': '$E8',
+ 'CADRC': '$E6',
+ 'CLKPR': '$61',
+ 'DIDR0': '$7E',
+ 'FOSCCAL': '$66',
+ 'GPIOR0': '$3E',
+ 'GPIOR1': '$4A',
+ 'GPIOR2': '$4B',
+ 'MCUCR': '$55',
+ 'MCUSR': '$54',
+ 'OSICSR': '$37',
+ 'PRR0': '$64',
+ 'SMCR': '$53',
+ 'SPH': '$5E',
+ 'SPL': '$5D',
+ 'SREG': '$5F',
+ 'EEAR': '$41',
+ 'EECR': '$3F',
+ 'EEDR': '$40',
+ 'EICRA': '$69',
+ 'EIFR': '$3C',
+ 'EIMSK': '$3D',
+ 'PCICR': '$68',
+ 'PCIFR': '$3B',
+ 'PCMSK0': '$6B',
+ 'FCSR': '$F0',
+ 'DDRA': '$21',
+ 'PINA': '$20',
+ 'PORTA': '$22',
+ 'DDRB': '$24',
+ 'PINB': '$23',
+ 'PORTB': '$25',
+ 'PINC': '$26',
+ 'PORTC': '$28',
+ 'SPCR': '$4c',
+ 'SPDR': '$4e',
+ 'SPSR': '$4d',
+ 'OCR0A': '$48',
+ 'OCR0B': '$49',
+ 'TCCR0A': '$44',
+ 'TCCR0B': '$45',
+ 'TCNT0H': '$47',
+ 'TCNT0L': '$46',
+ 'TIFR0': '$35',
+ 'TIMSK0': '$6E',
+ 'GTCCR': '$43',
+ 'OCR1A': '$88',
+ 'OCR1B': '$89',
+ 'TCCR1A': '$80',
+ 'TCCR1B': '$81',
+ 'TCNT1H': '$85',
+ 'TCNT1L': '$84',
+ 'TIFR1': '$36',
+ 'TIMSK1': '$6F',
+ 'ROCR': '$C8',
+ 'WDTCSR': '$60',
+ 'BPINTAddr': '$0002',
+ 'VREGMONAddr': '$0004',
+ 'INT0Addr': '$0006',
+ 'INT1Addr': '$0008',
+ 'INT2Addr': '$000A',
+ 'PCINT0Addr': '$000C',
+ 'WDTAddr': '$000E',
+ 'TIMER1_ICAddr': '$0010',
+ 'TIMER1_COMPAAddr': '$0012',
+ 'TIMER1_COMPBAddr': '$0014',
+ 'TIMER1_OVFAddr': '$0016',
+ 'TIMER0_ICAddr': '$0018',
+ 'TIMER0_COMPAAddr': '$001A',
+ 'TIMER0_COMPBAddr': '$001C',
+ 'TIMER0_OVFAddr': '$001E',
+ 'SPI;STCAddr': '$0020',
+ 'VADCAddr': '$0022',
+ 'CCADC_CONVAddr': '$0024',
+ 'CCADC_REG_CURAddr': '$0026',
+ 'CCADC_ACCAddr': '$0028',
+ 'EE_READYAddr': '$02A'
+} \ No newline at end of file
diff --git a/amforth-6.5/avr8/devices/atmega16hvb/atmega16hvb.frt b/amforth-6.5/avr8/devices/atmega16hvb/atmega16hvb.frt
new file mode 100644
index 0000000..90542af
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega16hvb/atmega16hvb.frt
@@ -0,0 +1,33 @@
+\ Partname: ATmega16HVB
+\ generated automatically
+
+
+\ Interrupts
+&2 constant BPINTAddr \ Battery Protection Interrupt
+&4 constant VREGMONAddr \ Voltage regulator monitor interrupt
+&6 constant INT0Addr \ External Interrupt Request 0
+&8 constant INT1Addr \ External Interrupt Request 1
+&10 constant INT2Addr \ External Interrupt Request 2
+&12 constant INT3Addr \ External Interrupt Request 3
+&14 constant PCINT0Addr \ Pin Change Interrupt 0
+&16 constant PCINT1Addr \ Pin Change Interrupt 1
+&18 constant WDTAddr \ Watchdog Timeout Interrupt
+&20 constant BGSCDAddr \ Bandgap Buffer Short Circuit Detected
+&22 constant CHDETAddr \ Charger Detect
+&24 constant TIMER1_ICAddr \ Timer 1 Input capture
+&26 constant TIMER1_COMPAAddr \ Timer 1 Compare Match A
+&28 constant TIMER1_COMPBAddr \ Timer 1 Compare Match B
+&30 constant TIMER1_OVFAddr \ Timer 1 overflow
+&32 constant TIMER0_ICAddr \ Timer 0 Input Capture
+&34 constant TIMER0_COMPAAddr \ Timer 0 Comapre Match A
+&36 constant TIMER0_COMPBAddr \ Timer 0 Compare Match B
+&38 constant TIMER0_OVFAddr \ Timer 0 Overflow
+&40 constant TWIBUSCDAddr \ Two-Wire Bus Connect/Disconnect
+&42 constant TWIAddr \ Two-Wire Serial Interface
+&44 constant SPI_STCAddr \ SPI Serial transfer complete
+&46 constant VADCAddr \ Voltage ADC Conversion Complete
+&48 constant CCADC_CONVAddr \ Coulomb Counter ADC Conversion Complete
+&50 constant CCADC_REG_CURAddr \ Coloumb Counter ADC Regular Current
+&52 constant CCADC_ACCAddr \ Coloumb Counter ADC Accumulator
+&54 constant EE_READYAddr \ EEPROM Ready
+&56 constant SPMAddr \ SPM Ready
diff --git a/amforth-6.5/avr8/devices/atmega16hvb/device.asm b/amforth-6.5/avr8/devices/atmega16hvb/device.asm
new file mode 100644
index 0000000..f128900
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega16hvb/device.asm
@@ -0,0 +1,101 @@
+; Partname: ATmega16HVB
+; generated automatically, do not edit
+
+.nolist
+ .include "m16HVBdef.inc"
+.list
+
+.equ ramstart = 256
+.equ CELLSIZE = 2
+.macro readflashcell
+ lsl zl
+ rol zh
+ lpm @0, Z+
+ lpm @1, Z+
+.endmacro
+.macro writeflashcell
+ lsl zl
+ rol zh
+.endmacro
+.equ intvecsize = 2 ; please verify; flash size: 16384 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.org 2
+ rcall isr ; Battery Protection Interrupt
+.org 4
+ rcall isr ; Voltage regulator monitor interrupt
+.org 6
+ rcall isr ; External Interrupt Request 0
+.org 8
+ rcall isr ; External Interrupt Request 1
+.org 10
+ rcall isr ; External Interrupt Request 2
+.org 12
+ rcall isr ; External Interrupt Request 3
+.org 14
+ rcall isr ; Pin Change Interrupt 0
+.org 16
+ rcall isr ; Pin Change Interrupt 1
+.org 18
+ rcall isr ; Watchdog Timeout Interrupt
+.org 20
+ rcall isr ; Bandgap Buffer Short Circuit Detected
+.org 22
+ rcall isr ; Charger Detect
+.org 24
+ rcall isr ; Timer 1 Input capture
+.org 26
+ rcall isr ; Timer 1 Compare Match A
+.org 28
+ rcall isr ; Timer 1 Compare Match B
+.org 30
+ rcall isr ; Timer 1 overflow
+.org 32
+ rcall isr ; Timer 0 Input Capture
+.org 34
+ rcall isr ; Timer 0 Comapre Match A
+.org 36
+ rcall isr ; Timer 0 Compare Match B
+.org 38
+ rcall isr ; Timer 0 Overflow
+.org 40
+ rcall isr ; Two-Wire Bus Connect/Disconnect
+.org 42
+ rcall isr ; Two-Wire Serial Interface
+.org 44
+ rcall isr ; SPI Serial transfer complete
+.org 46
+ rcall isr ; Voltage ADC Conversion Complete
+.org 48
+ rcall isr ; Coulomb Counter ADC Conversion Complete
+.org 50
+ rcall isr ; Coloumb Counter ADC Regular Current
+.org 52
+ rcall isr ; Coloumb Counter ADC Accumulator
+.org 54
+ rcall isr ; EEPROM Ready
+.org 56
+ rcall isr ; SPM Ready
+.equ INTVECTORS = 29
+.nooverlap
+
+; compatability layer (maybe empty)
+.equ SPMEN = SELFPRGEN
+.equ SPMCSR = SPMCR
+.equ EEPE = EEWE
+.equ EEMPE = EEMWE
+
+; controller data area, environment query mcu-info
+mcu_info:
+mcu_ramsize:
+ .dw 1024
+mcu_eepromsize:
+ .dw 512
+mcu_maxdp:
+ .dw 12288
+mcu_numints:
+ .dw 29
+mcu_name:
+ .dw 11
+ .db "ATmega16HVB",0
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega16hvb/device.inc b/amforth-6.5/avr8/devices/atmega16hvb/device.inc
new file mode 100644
index 0000000..1f86f17
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega16hvb/device.inc
@@ -0,0 +1,3 @@
+; Partname: ATmega16HVB
+; generated automatically, no not edit
+
diff --git a/amforth-6.5/avr8/devices/atmega16hvb/device.py b/amforth-6.5/avr8/devices/atmega16hvb/device.py
new file mode 100644
index 0000000..f5b504f
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega16hvb/device.py
@@ -0,0 +1,342 @@
+# Generated Automatically
+
+# Partname ATmega16HVB
+
+MCUREGS = {
+# Interrupt Vectors
+ 'BPINTAddr' : '#2', # Battery Protection Interrupt
+ 'VREGMONAddr' : '#4', # Voltage regulator monitor interrupt
+ 'INT0Addr' : '#6', # External Interrupt Request 0
+ 'INT1Addr' : '#8', # External Interrupt Request 1
+ 'INT2Addr' : '#10', # External Interrupt Request 2
+ 'INT3Addr' : '#12', # External Interrupt Request 3
+ 'PCINT0Addr' : '#14', # Pin Change Interrupt 0
+ 'PCINT1Addr' : '#16', # Pin Change Interrupt 1
+ 'WDTAddr' : '#18', # Watchdog Timeout Interrupt
+ 'BGSCDAddr' : '#20', # Bandgap Buffer Short Circuit Detected
+ 'CHDETAddr' : '#22', # Charger Detect
+ 'TIMER1_ICAddr' : '#24', # Timer 1 Input capture
+ 'TIMER1_COMPAAddr' : '#26', # Timer 1 Compare Match A
+ 'TIMER1_COMPBAddr' : '#28', # Timer 1 Compare Match B
+ 'TIMER1_OVFAddr' : '#30', # Timer 1 overflow
+ 'TIMER0_ICAddr' : '#32', # Timer 0 Input Capture
+ 'TIMER0_COMPAAddr' : '#34', # Timer 0 Comapre Match A
+ 'TIMER0_COMPBAddr' : '#36', # Timer 0 Compare Match B
+ 'TIMER0_OVFAddr' : '#38', # Timer 0 Overflow
+ 'TWIBUSCDAddr' : '#40', # Two-Wire Bus Connect/Disconnect
+ 'TWIAddr' : '#42', # Two-Wire Serial Interface
+ 'SPI_STCAddr' : '#44', # SPI Serial transfer complete
+ 'VADCAddr' : '#46', # Voltage ADC Conversion Complete
+ 'CCADC_CONVAddr' : '#48', # Coulomb Counter ADC Conversion Complete
+ 'CCADC_REG_CURAddr' : '#50', # Coloumb Counter ADC Regular Current
+ 'CCADC_ACCAddr' : '#52', # Coloumb Counter ADC Accumulator
+ 'EE_READYAddr' : '#54', # EEPROM Ready
+ 'SPMAddr' : '#56', # SPM Ready
+
+# Module AD_CONVERTER
+ 'VADMUX' : '$7c', # The VADC multiplexer Selection
+ 'VADMUX_VADMUX': '$f', # Analog Channel and Gain Select
+ 'VADC' : '$78', # VADC Data Register Bytes
+ 'VADCSR' : '$7a', # The VADC Control and Status re
+ 'VADCSR_VADEN': '$8', # VADC Enable
+ 'VADCSR_VADSC': '$4', # VADC Satrt Conversion
+ 'VADCSR_VADCCIF': '$2', # VADC Conversion Complete Inter
+ 'VADCSR_VADCCIE': '$1', # VADC Conversion Complete Inter
+
+# Module WATCHDOG
+ 'WDTCSR' : '$60', # Watchdog Timer Control Registe
+ 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
+ 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
+ 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
+ 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
+ 'WDTCSR_WDE': '$8', # Watch Dog Enable
+
+# Module FET
+ 'FCSR' : '$f0', # FET Control and Status Registe
+ 'FCSR_DUVRD': '$8', # Deep Under-Voltage Recovery Di
+ 'FCSR_CPS': '$4', # Current Protection Status
+ 'FCSR_DFE': '$2', # Discharge FET Enable
+ 'FCSR_CFE': '$1', # Charge FET Enable
+
+# Module SPI
+ 'SPCR' : '$4c', # SPI Control Register
+ 'SPCR_SPIE': '$80', # SPI Interrupt Enable
+ 'SPCR_SPE': '$40', # SPI Enable
+ 'SPCR_DORD': '$20', # Data Order
+ 'SPCR_MSTR': '$10', # Master/Slave Select
+ 'SPCR_CPOL': '$8', # Clock polarity
+ 'SPCR_CPHA': '$4', # Clock Phase
+ 'SPCR_SPR': '$3', # SPI Clock Rate Selects
+ 'SPSR' : '$4d', # SPI Status Register
+ 'SPSR_SPIF': '$80', # SPI Interrupt Flag
+ 'SPSR_WCOL': '$40', # Write Collision Flag
+ 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
+ 'SPDR' : '$4e', # SPI Data Register
+
+# Module EEPROM
+ 'EEAR' : '$41', # EEPROM Read/Write Access
+ 'EEDR' : '$40', # EEPROM Data Register
+ 'EECR' : '$3f', # EEPROM Control Register
+ 'EECR_EEPM': '$30', #
+ 'EECR_EERIE': '$8', # EEProm Ready Interrupt Enable
+ 'EECR_EEMPE': '$4', # EEPROM Master Write Enable
+ 'EECR_EEPE': '$2', # EEPROM Write Enable
+ 'EECR_EERE': '$1', # EEPROM Read Enable
+
+# Module COULOMB_COUNTER
+ 'CADCSRA' : '$e6', # CC-ADC Control and Status Regi
+ 'CADCSRA_CADEN': '$80', # When the CADEN bit is cleared
+ 'CADCSRA_CADPOL': '$40', #
+ 'CADCSRA_CADUB': '$20', # CC_ADC Update Busy
+ 'CADCSRA_CADAS': '$18', # CC_ADC Accumulate Current Sele
+ 'CADCSRA_CADSI': '$6', # The CADSI bits determine the c
+ 'CADCSRA_CADSE': '$1', # When the CADSE bit is written
+ 'CADCSRB' : '$e7', # CC-ADC Control and Status Regi
+ 'CADCSRB_CADACIE': '$40', #
+ 'CADCSRB_CADRCIE': '$20', # Regular Current Interrupt Enab
+ 'CADCSRB_CADICIE': '$10', # CAD Instantenous Current Inter
+ 'CADCSRB_CADACIF': '$4', # CC-ADC Accumulate Current Inte
+ 'CADCSRB_CADRCIF': '$2', # CC-ADC Accumulate Current Inte
+ 'CADCSRB_CADICIF': '$1', # CC-ADC Instantaneous Current I
+ 'CADCSRC' : '$e8', # CC-ADC Control and Status Regi
+ 'CADCSRC_CADVSE': '$1', # CC-ADC Voltage Scaling Enable
+ 'CADIC' : '$e4', # CC-ADC Instantaneous Current
+ 'CADAC3' : '$e3', # ADC Accumulate Current
+ 'CADAC2' : '$e2', # ADC Accumulate Current
+ 'CADAC1' : '$e1', # ADC Accumulate Current
+ 'CADAC0' : '$e0', # ADC Accumulate Current
+ 'CADRCC' : '$e9', # CC-ADC Regular Charge Current
+ 'CADRDC' : '$ea', # CC-ADC Regular Discharge Curre
+
+# Module TWI
+ 'TWBCSR' : '$be', # TWI Bus Control and Status Reg
+ 'TWBCSR_TWBCIF': '$80', # TWI Bus Connect/Disconnect Int
+ 'TWBCSR_TWBCIE': '$40', # TWI Bus Connect/Disconnect Int
+ 'TWBCSR_TWBDT': '$6', # TWI Bus Disconnect Time-out Pe
+ 'TWBCSR_TWBCIP': '$1', # TWI Bus Connect/Disconnect Int
+ 'TWAMR' : '$bd', # TWI (Slave) Address Mask Regis
+ 'TWAMR_TWAM': '$fe', #
+ 'TWBR' : '$b8', # TWI Bit Rate register
+ 'TWCR' : '$bc', # TWI Control Register
+ 'TWCR_TWINT': '$80', # TWI Interrupt Flag
+ 'TWCR_TWEA': '$40', # TWI Enable Acknowledge Bit
+ 'TWCR_TWSTA': '$20', # TWI Start Condition Bit
+ 'TWCR_TWSTO': '$10', # TWI Stop Condition Bit
+ 'TWCR_TWWC': '$8', # TWI Write Collition Flag
+ 'TWCR_TWEN': '$4', # TWI Enable Bit
+ 'TWCR_TWIE': '$1', # TWI Interrupt Enable
+ 'TWSR' : '$b9', # TWI Status Register
+ 'TWSR_TWS': '$f8', # TWI Status
+ 'TWSR_TWPS': '$3', # TWI Prescaler
+ 'TWDR' : '$bb', # TWI Data register
+ 'TWAR' : '$ba', # TWI (Slave) Address register
+ 'TWAR_TWA': '$fe', # TWI (Slave) Address register B
+ 'TWAR_TWGCE': '$1', # TWI General Call Recognition E
+
+# Module EXTERNAL_INTERRUPT
+ 'EICRA' : '$69', # External Interrupt Control Reg
+ 'EICRA_ISC3': '$c0', # External Interrupt Sense Contr
+ 'EICRA_ISC2': '$30', # External Interrupt Sense Contr
+ 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
+ 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
+ 'EIMSK' : '$3d', # External Interrupt Mask Regist
+ 'EIMSK_INT': '$f', # External Interrupt Request 3 E
+ 'EIFR' : '$3c', # External Interrupt Flag Regist
+ 'EIFR_INTF': '$f', # External Interrupt Flags
+ 'PCICR' : '$68', # Pin Change Interrupt Control R
+ 'PCICR_PCIE': '$3', # Pin Change Interrupt Enables
+ 'PCIFR' : '$3b', # Pin Change Interrupt Flag Regi
+ 'PCIFR_PCIF': '$3', # Pin Change Interrupt Flags
+ 'PCMSK1' : '$6c', # Pin Change Enable Mask Registe
+ 'PCMSK0' : '$6b', # Pin Change Enable Mask Registe
+
+# Module TIMER_COUNTER_1
+ 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
+ 'TCCR1B_CS': '$7', # Clock Select1 bis
+ 'TCCR1A' : '$80', # Timer/Counter 1 Control Regist
+ 'TCCR1A_TCW1': '$80', # Timer/Counter Width
+ 'TCCR1A_ICEN1': '$40', # Input Capture Mode Enable
+ 'TCCR1A_ICNC1': '$20', # Input Capture Noise Canceler
+ 'TCCR1A_ICES1': '$10', # Input Capture Edge Select
+ 'TCCR1A_ICS1': '$8', # Input Capture Select
+ 'TCCR1A_WGM10': '$1', # Waveform Generation Mode
+ 'TCNT1' : '$84', # Timer Counter 1 Bytes
+ 'OCR1A' : '$88', # Output Compare Register 1A
+ 'OCR1B' : '$89', # Output Compare Register B
+ 'TIMSK1' : '$6f', # Timer/Counter Interrupt Mask R
+ 'TIMSK1_ICIE1': '$8', # Timer/Counter n Input Capture
+ 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
+ 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
+ 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
+ 'TIFR1' : '$36', # Timer/Counter Interrupt Flag r
+ 'TIFR1_ICF1': '$8', # Timer/Counter 1 Input Capture
+ 'TIFR1_OCF1B': '$4', # Timer/Counter1 Output Compare
+ 'TIFR1_OCF1A': '$2', # Timer/Counter1 Output Compare
+ 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSRSYNC': '$1', # Prescaler Reset
+
+# Module CELL_BALANCING
+ 'CBCR' : '$f1', # Cell Balancing Control Registe
+ 'CBCR_CBE': '$f', # Cell Balancing Enables
+
+# Module BATTERY_PROTECTION
+ 'BPPLR' : '$fe', # Battery Protection Parameter L
+ 'BPPLR_BPPLE': '$2', # Battery Protection Parameter L
+ 'BPPLR_BPPL': '$1', # Battery Protection Parameter L
+ 'BPCR' : '$fd', # Battery Protection Control Reg
+ 'BPCR_EPID': '$20', # External Protection Input Disa
+ 'BPCR_SCD': '$10', # Short Circuit Protection Disab
+ 'BPCR_DOCD': '$8', # Discharge Over-current Protect
+ 'BPCR_COCD': '$4', # Charge Over-current Protection
+ 'BPCR_DHCD': '$2', # Discharge High-current Protect
+ 'BPCR_CHCD': '$1', # Charge High-current Protection
+ 'BPHCTR' : '$fc', # Battery Protection Short-curre
+ 'BPOCTR' : '$fb', # Battery Protection Over-curren
+ 'BPSCTR' : '$fa', # Battery Protection Short-curre
+ 'BPCHCD' : '$f9', # Battery Protection Charge-High
+ 'BPDHCD' : '$f8', # Battery Protection Discharge-H
+ 'BPCOCD' : '$f7', # Battery Protection Charge-Over
+ 'BPDOCD' : '$f6', # Battery Protection Discharge-O
+ 'BPSCD' : '$f5', # Battery Protection Short-Circu
+ 'BPIFR' : '$f3', # Battery Protection Interrupt F
+ 'BPIFR_SCIF': '$10', # Short-circuit Protection Activ
+ 'BPIFR_DOCIF': '$8', # Discharge Over-current Protect
+ 'BPIFR_COCIF': '$4', # Charge Over-current Protection
+ 'BPIFR_DHCIF': '$2', # Disharge High-current Protecti
+ 'BPIFR_CHCIF': '$1', # Charge High-current Protection
+ 'BPIMSK' : '$f2', # Battery Protection Interrupt M
+ 'BPIMSK_SCIE': '$10', # Short-circuit Protection Activ
+ 'BPIMSK_DOCIE': '$8', # Discharge Over-current Protect
+ 'BPIMSK_COCIE': '$4', # Charge Over-current Protection
+ 'BPIMSK_DHCIE': '$2', # Discharger High-current Protec
+ 'BPIMSK_CHCIE': '$1', # Charger High-current Protectio
+
+# Module CHARGER_DETECT
+ 'CHGDCSR' : '$d4', # Charger Detect Control and Sta
+ 'CHGDCSR_BATTPVL': '$10', # BATT Pin Voltage Level
+ 'CHGDCSR_CHGDISC': '$c', # Charger Detect Interrupt Sense
+ 'CHGDCSR_CHGDIF': '$2', # Charger Detect Interrupt Flag
+ 'CHGDCSR_CHGDIE': '$1', # Charger Detect Interrupt Enabl
+
+# Module VOLTAGE_REGULATOR
+ 'ROCR' : '$c8', # Regulator Operating Condition
+ 'ROCR_ROCS': '$80', # ROC Status
+ 'ROCR_ROCD': '$10', # ROC Disable
+ 'ROCR_ROCWIF': '$2', # ROC Warning Interrupt Flag
+ 'ROCR_ROCWIE': '$1', # ROC Warning Interrupt Enable
+
+# Module BANDGAP
+ 'BGCSR' : '$d2', # Bandgap Control and Status Reg
+ 'BGCSR_BGD': '$20', # Bandgap Disable
+ 'BGCSR_BGSCDE': '$10', # Bandgap Short Circuit Detectio
+ 'BGCSR_BGSCDIF': '$2', # Bandgap Short Circuit Detectio
+ 'BGCSR_BGSCDIE': '$1', # Bandgap Short Circuit Detectio
+ 'BGCRR' : '$d1', # Bandgap Calibration of Resisto
+ 'BGCCR' : '$d0', # Bandgap Calibration Register
+ 'BGCCR_BGCC': '$3f', # BG Calibration of PTAT Current
+
+# Module CPU
+ 'SREG' : '$5f', # Status Register
+ 'SREG_I': '$80', # Global Interrupt Enable
+ 'SREG_T': '$40', # Bit Copy Storage
+ 'SREG_H': '$20', # Half Carry Flag
+ 'SREG_S': '$10', # Sign Bit
+ 'SREG_V': '$8', # Two's Complement Overflow Flag
+ 'SREG_N': '$4', # Negative Flag
+ 'SREG_Z': '$2', # Zero Flag
+ 'SREG_C': '$1', # Carry Flag
+ 'SP' : '$5d', # Stack Pointer
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_CKOE': '$20', # Clock Output Enable
+ 'MCUCR_PUD': '$10', # Pull-up disable
+ 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
+ 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_OCDRF': '$10', # OCD Reset Flag
+ 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
+ 'MCUSR_BODRF': '$4', # Brown-out Reset Flag
+ 'MCUSR_EXTRF': '$2', # External Reset Flag
+ 'MCUSR_PORF': '$1', # Power-on reset flag
+ 'FOSCCAL' : '$66', # Fast Oscillator Calibration Va
+ 'OSICSR' : '$37', # Oscillator Sampling Interface
+ 'OSICSR_OSISEL0': '$10', # Oscillator Sampling Interface
+ 'OSICSR_OSIST': '$2', # Oscillator Sampling Interface
+ 'OSICSR_OSIEN': '$1', # Oscillator Sampling Interface
+ 'SMCR' : '$53', # Sleep Mode Control Register
+ 'SMCR_SM': '$e', # Sleep Mode Select bits
+ 'SMCR_SE': '$1', # Sleep Enable
+ 'GPIOR2' : '$4b', # General Purpose IO Register 2
+ 'GPIOR1' : '$4a', # General Purpose IO Register 1
+ 'GPIOR0' : '$3e', # General Purpose IO Register 0
+ 'DIDR0' : '$7e', # Digital Input Disable Register
+ 'DIDR0_PA1DID': '$2', # When this bit is written logic
+ 'DIDR0_PA0DID': '$1', # When this bit is written logic
+ 'PRR0' : '$64', # Power Reduction Register 0
+ 'PRR0_PRTWI': '$40', # Power Reduction TWI
+ 'PRR0_PRVRM': '$20', # Power Reduction Voltage Regula
+ 'PRR0_PRSPI': '$8', # Power reduction SPI
+ 'PRR0_PRTIM1': '$4', # Power Reduction Timer/Counter1
+ 'PRR0_PRTIM0': '$2', # Power Reduction Timer/Counter0
+ 'PRR0_PRVADC': '$1', # Power Reduction V-ADC
+ 'CLKPR' : '$61', # Clock Prescale Register
+ 'CLKPR_CLKPCE': '$80', # Clock Prescaler Change Enable
+ 'CLKPR_CLKPS': '$3', # Clock Prescaler Select Bits
+
+# Module PORTA
+ 'PORTA' : '$22', # Port A Data Register
+ 'DDRA' : '$21', # Port A Data Direction Register
+ 'PINA' : '$20', # Port A Input Pins
+
+# Module PORTB
+ 'PORTB' : '$25', # Port B Data Register
+ 'DDRB' : '$24', # Port B Data Direction Register
+ 'PINB' : '$23', # Port B Input Pins
+
+# Module PORTC
+ 'PORTC' : '$28', # Port C Data Register
+ 'PINC' : '$26', # Port C Input Pins
+
+# Module TIMER_COUNTER_0
+ 'TCCR0B' : '$45', # Timer/Counter0 Control Registe
+ 'TCCR0B_CS02': '$4', # Clock Select0 bit 2
+ 'TCCR0B_CS01': '$2', # Clock Select0 bit 1
+ 'TCCR0B_CS00': '$1', # Clock Select0 bit 0
+ 'TCCR0A' : '$44', # Timer/Counter 0 Control Regist
+ 'TCCR0A_TCW0': '$80', # Timer/Counter Width
+ 'TCCR0A_ICEN0': '$40', # Input Capture Mode Enable
+ 'TCCR0A_ICNC0': '$20', # Input Capture Noise Canceler
+ 'TCCR0A_ICES0': '$10', # Input Capture Edge Select
+ 'TCCR0A_ICS0': '$8', # Input Capture Select
+ 'TCCR0A_WGM00': '$1', # Waveform Generation Mode
+ 'TCNT0' : '$46', # Timer Counter 0 Bytes
+ 'OCR0A' : '$48', # Output Compare Register 0A
+ 'OCR0B' : '$49', # Output Compare Register B
+ 'TIMSK0' : '$6e', # Timer/Counter Interrupt Mask R
+ 'TIMSK0_ICIE0': '$8', # Timer/Counter n Input Capture
+ 'TIMSK0_OCIE0B': '$4', # Timer/Counter0 Output Compare
+ 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
+ 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
+ 'TIFR0' : '$35', # Timer/Counter Interrupt Flag r
+ 'TIFR0_ICF0': '$8', # Timer/Counter 0 Input Capture
+ 'TIFR0_OCF0B': '$4', # Timer/Counter0 Output Compare
+ 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
+ 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSRSYNC': '$1', # Prescaler Reset
+
+# Module BOOT_LOAD
+ 'SPMCSR' : '$57', # Store Program Memory Control a
+ 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
+ 'SPMCSR_RWWSB': '$40', # Read-While-Write Section Busy
+ 'SPMCSR_SIGRD': '$20', # Signature Row Read
+ 'SPMCSR_RWWSRE': '$10', # Read-While-Write Section Read
+ 'SPMCSR_LBSET': '$8', # Lock Bit Set
+ 'SPMCSR_PGWRT': '$4', # Page Write
+ 'SPMCSR_PGERS': '$2', # Page Erase
+ 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
+
+ '__amforth_dummy':'0'
+}
diff --git a/amforth-6.5/avr8/devices/atmega16hvb/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega16hvb/words/no-jtag.asm
new file mode 100644
index 0000000..352a4bb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega16hvb/words/no-jtag.asm
@@ -0,0 +1,14 @@
+; ( -- )
+; ( -- )
+; MCU
+; disable jtag at runtime
+VE_NOJTAG:
+ .dw $FF05
+ .db "-jtag",0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOJTAG
+XT_NOJTAG:
+ .dw PFA_NOJTAG
+PFA_NOJTAG:
+
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega16hvb/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega16hvb/words/no-wdt.asm
new file mode 100644
index 0000000..4a12261
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega16hvb/words/no-wdt.asm
@@ -0,0 +1,22 @@
+; ( -- )
+; MCU
+; disable watch dog timer at runtime
+VE_NOWDT:
+ .dw $ff04
+ .db "-wdt"
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOWDT
+XT_NOWDT:
+ .dw PFA_NOWDT
+PFA_NOWDT:
+
+; Reset WDT
+ wdr
+; Write logical one to WDTOE and WDE
+ in_ temp1, WDTCR
+ ori temp1, (1<<WDTOE)|(1<<WDE)
+ out WDTCR, temp1
+; Turn off WDT
+ ldi temp1, (0<<WDE)
+ out_ WDTCR, temp1
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega16hvb/words/sleep.asm b/amforth-6.5/avr8/devices/atmega16hvb/words/sleep.asm
new file mode 100644
index 0000000..778fa32
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega16hvb/words/sleep.asm
@@ -0,0 +1,24 @@
+; ( mode -- )
+; MCU
+; put the controller into the specified sleep mode
+VE_SLEEP:
+ .dw $ff05
+ .db "sleep", 0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_SLEEP
+XT_SLEEP:
+ .dw PFA_SLEEP
+PFA_SLEEP:
+ andi tosl, 7 ; leave only legal mode bits
+ swap tosl ; move to correct location (bits 6-4, atmega32)
+ ori tosl, $80 ; set the SE bit (atmega32: bit 7, not bit 0)
+ out_ MCUCR, tosl ; set the sleep config (atmega32: MCUCR not SMCR)
+ sleep ; nighty-night
+;; the 4 lower bits of MCUCR should not be touched
+ in_ tosl, MCUCR
+ andi tosl, $0F
+ out_ MCUCR, tosl
+ ;clr tosl ; need to clean up the SMCR reg before we leave
+ ;out SMCR, tosl ; 0 protects against accidental sleeps
+ loadtos ; pop argument from stack
+ jmp DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega16hvbrevb/atmega16hvbrevb.frt b/amforth-6.5/avr8/devices/atmega16hvbrevb/atmega16hvbrevb.frt
new file mode 100644
index 0000000..77246ab
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega16hvbrevb/atmega16hvbrevb.frt
@@ -0,0 +1,33 @@
+\ Partname: ATmega16HVBrevB
+\ generated automatically
+
+
+\ Interrupts
+&2 constant BPINTAddr \ Battery Protection Interrupt
+&4 constant VREGMONAddr \ Voltage regulator monitor interrupt
+&6 constant INT0Addr \ External Interrupt Request 0
+&8 constant INT1Addr \ External Interrupt Request 1
+&10 constant INT2Addr \ External Interrupt Request 2
+&12 constant INT3Addr \ External Interrupt Request 3
+&14 constant PCINT0Addr \ Pin Change Interrupt 0
+&16 constant PCINT1Addr \ Pin Change Interrupt 1
+&18 constant WDTAddr \ Watchdog Timeout Interrupt
+&20 constant BGSCDAddr \ Bandgap Buffer Short Circuit Detected
+&22 constant CHDETAddr \ Charger Detect
+&24 constant TIMER1_ICAddr \ Timer 1 Input capture
+&26 constant TIMER1_COMPAAddr \ Timer 1 Compare Match A
+&28 constant TIMER1_COMPBAddr \ Timer 1 Compare Match B
+&30 constant TIMER1_OVFAddr \ Timer 1 overflow
+&32 constant TIMER0_ICAddr \ Timer 0 Input Capture
+&34 constant TIMER0_COMPAAddr \ Timer 0 Comapre Match A
+&36 constant TIMER0_COMPBAddr \ Timer 0 Compare Match B
+&38 constant TIMER0_OVFAddr \ Timer 0 Overflow
+&40 constant TWIBUSCDAddr \ Two-Wire Bus Connect/Disconnect
+&42 constant TWIAddr \ Two-Wire Serial Interface
+&44 constant SPI_STCAddr \ SPI Serial transfer complete
+&46 constant VADCAddr \ Voltage ADC Conversion Complete
+&48 constant CCADC_CONVAddr \ Coulomb Counter ADC Conversion Complete
+&50 constant CCADC_REG_CURAddr \ Coloumb Counter ADC Regular Current
+&52 constant CCADC_ACCAddr \ Coloumb Counter ADC Accumulator
+&54 constant EE_READYAddr \ EEPROM Ready
+&56 constant SPMAddr \ SPM Ready
diff --git a/amforth-6.5/avr8/devices/atmega16hvbrevb/device.asm b/amforth-6.5/avr8/devices/atmega16hvbrevb/device.asm
new file mode 100644
index 0000000..c9dcb8c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega16hvbrevb/device.asm
@@ -0,0 +1,101 @@
+; Partname: ATmega16HVBrevB
+; generated automatically, do not edit
+
+.nolist
+ .include "m16HVBrevBdef.inc"
+.list
+
+.equ ramstart = 256
+.equ CELLSIZE = 2
+.macro readflashcell
+ lsl zl
+ rol zh
+ lpm @0, Z+
+ lpm @1, Z+
+.endmacro
+.macro writeflashcell
+ lsl zl
+ rol zh
+.endmacro
+.equ intvecsize = 2 ; please verify; flash size: 16384 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.org 2
+ rcall isr ; Battery Protection Interrupt
+.org 4
+ rcall isr ; Voltage regulator monitor interrupt
+.org 6
+ rcall isr ; External Interrupt Request 0
+.org 8
+ rcall isr ; External Interrupt Request 1
+.org 10
+ rcall isr ; External Interrupt Request 2
+.org 12
+ rcall isr ; External Interrupt Request 3
+.org 14
+ rcall isr ; Pin Change Interrupt 0
+.org 16
+ rcall isr ; Pin Change Interrupt 1
+.org 18
+ rcall isr ; Watchdog Timeout Interrupt
+.org 20
+ rcall isr ; Bandgap Buffer Short Circuit Detected
+.org 22
+ rcall isr ; Charger Detect
+.org 24
+ rcall isr ; Timer 1 Input capture
+.org 26
+ rcall isr ; Timer 1 Compare Match A
+.org 28
+ rcall isr ; Timer 1 Compare Match B
+.org 30
+ rcall isr ; Timer 1 overflow
+.org 32
+ rcall isr ; Timer 0 Input Capture
+.org 34
+ rcall isr ; Timer 0 Comapre Match A
+.org 36
+ rcall isr ; Timer 0 Compare Match B
+.org 38
+ rcall isr ; Timer 0 Overflow
+.org 40
+ rcall isr ; Two-Wire Bus Connect/Disconnect
+.org 42
+ rcall isr ; Two-Wire Serial Interface
+.org 44
+ rcall isr ; SPI Serial transfer complete
+.org 46
+ rcall isr ; Voltage ADC Conversion Complete
+.org 48
+ rcall isr ; Coulomb Counter ADC Conversion Complete
+.org 50
+ rcall isr ; Coloumb Counter ADC Regular Current
+.org 52
+ rcall isr ; Coloumb Counter ADC Accumulator
+.org 54
+ rcall isr ; EEPROM Ready
+.org 56
+ rcall isr ; SPM Ready
+.equ INTVECTORS = 29
+.nooverlap
+
+; compatability layer (maybe empty)
+.equ SPMEN = SELFPRGEN
+.equ SPMCSR = SPMCR
+.equ EEPE = EEWE
+.equ EEMPE = EEMWE
+
+; controller data area, environment query mcu-info
+mcu_info:
+mcu_ramsize:
+ .dw 1024
+mcu_eepromsize:
+ .dw 512
+mcu_maxdp:
+ .dw 12288
+mcu_numints:
+ .dw 29
+mcu_name:
+ .dw 15
+ .db "ATmega16HVBrevB",0
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega16hvbrevb/device.inc b/amforth-6.5/avr8/devices/atmega16hvbrevb/device.inc
new file mode 100644
index 0000000..6765fb4
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega16hvbrevb/device.inc
@@ -0,0 +1,3 @@
+; Partname: ATmega16HVBrevB
+; generated automatically, no not edit
+
diff --git a/amforth-6.5/avr8/devices/atmega16hvbrevb/device.py b/amforth-6.5/avr8/devices/atmega16hvbrevb/device.py
new file mode 100644
index 0000000..9f1a319
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega16hvbrevb/device.py
@@ -0,0 +1,342 @@
+# Generated Automatically
+
+# Partname ATmega16HVBrevB
+
+MCUREGS = {
+# Interrupt Vectors
+ 'BPINTAddr' : '#2', # Battery Protection Interrupt
+ 'VREGMONAddr' : '#4', # Voltage regulator monitor interrupt
+ 'INT0Addr' : '#6', # External Interrupt Request 0
+ 'INT1Addr' : '#8', # External Interrupt Request 1
+ 'INT2Addr' : '#10', # External Interrupt Request 2
+ 'INT3Addr' : '#12', # External Interrupt Request 3
+ 'PCINT0Addr' : '#14', # Pin Change Interrupt 0
+ 'PCINT1Addr' : '#16', # Pin Change Interrupt 1
+ 'WDTAddr' : '#18', # Watchdog Timeout Interrupt
+ 'BGSCDAddr' : '#20', # Bandgap Buffer Short Circuit Detected
+ 'CHDETAddr' : '#22', # Charger Detect
+ 'TIMER1_ICAddr' : '#24', # Timer 1 Input capture
+ 'TIMER1_COMPAAddr' : '#26', # Timer 1 Compare Match A
+ 'TIMER1_COMPBAddr' : '#28', # Timer 1 Compare Match B
+ 'TIMER1_OVFAddr' : '#30', # Timer 1 overflow
+ 'TIMER0_ICAddr' : '#32', # Timer 0 Input Capture
+ 'TIMER0_COMPAAddr' : '#34', # Timer 0 Comapre Match A
+ 'TIMER0_COMPBAddr' : '#36', # Timer 0 Compare Match B
+ 'TIMER0_OVFAddr' : '#38', # Timer 0 Overflow
+ 'TWIBUSCDAddr' : '#40', # Two-Wire Bus Connect/Disconnect
+ 'TWIAddr' : '#42', # Two-Wire Serial Interface
+ 'SPI_STCAddr' : '#44', # SPI Serial transfer complete
+ 'VADCAddr' : '#46', # Voltage ADC Conversion Complete
+ 'CCADC_CONVAddr' : '#48', # Coulomb Counter ADC Conversion Complete
+ 'CCADC_REG_CURAddr' : '#50', # Coloumb Counter ADC Regular Current
+ 'CCADC_ACCAddr' : '#52', # Coloumb Counter ADC Accumulator
+ 'EE_READYAddr' : '#54', # EEPROM Ready
+ 'SPMAddr' : '#56', # SPM Ready
+
+# Module AD_CONVERTER
+ 'VADMUX' : '$7c', # The VADC multiplexer Selection
+ 'VADMUX_VADMUX': '$f', # Analog Channel and Gain Select
+ 'VADC' : '$78', # VADC Data Register Bytes
+ 'VADCSR' : '$7a', # The VADC Control and Status re
+ 'VADCSR_VADEN': '$8', # VADC Enable
+ 'VADCSR_VADSC': '$4', # VADC Satrt Conversion
+ 'VADCSR_VADCCIF': '$2', # VADC Conversion Complete Inter
+ 'VADCSR_VADCCIE': '$1', # VADC Conversion Complete Inter
+
+# Module WATCHDOG
+ 'WDTCSR' : '$60', # Watchdog Timer Control Registe
+ 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
+ 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
+ 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
+ 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
+ 'WDTCSR_WDE': '$8', # Watch Dog Enable
+
+# Module FET
+ 'FCSR' : '$f0', # FET Control and Status Registe
+ 'FCSR_DUVRD': '$8', # Deep Under-Voltage Recovery Di
+ 'FCSR_CPS': '$4', # Current Protection Status
+ 'FCSR_DFE': '$2', # Discharge FET Enable
+ 'FCSR_CFE': '$1', # Charge FET Enable
+
+# Module SPI
+ 'SPCR' : '$4c', # SPI Control Register
+ 'SPCR_SPIE': '$80', # SPI Interrupt Enable
+ 'SPCR_SPE': '$40', # SPI Enable
+ 'SPCR_DORD': '$20', # Data Order
+ 'SPCR_MSTR': '$10', # Master/Slave Select
+ 'SPCR_CPOL': '$8', # Clock polarity
+ 'SPCR_CPHA': '$4', # Clock Phase
+ 'SPCR_SPR': '$3', # SPI Clock Rate Selects
+ 'SPSR' : '$4d', # SPI Status Register
+ 'SPSR_SPIF': '$80', # SPI Interrupt Flag
+ 'SPSR_WCOL': '$40', # Write Collision Flag
+ 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
+ 'SPDR' : '$4e', # SPI Data Register
+
+# Module EEPROM
+ 'EEAR' : '$41', # EEPROM Read/Write Access
+ 'EEDR' : '$40', # EEPROM Data Register
+ 'EECR' : '$3f', # EEPROM Control Register
+ 'EECR_EEPM': '$30', #
+ 'EECR_EERIE': '$8', # EEProm Ready Interrupt Enable
+ 'EECR_EEMPE': '$4', # EEPROM Master Write Enable
+ 'EECR_EEPE': '$2', # EEPROM Write Enable
+ 'EECR_EERE': '$1', # EEPROM Read Enable
+
+# Module COULOMB_COUNTER
+ 'CADCSRA' : '$e6', # CC-ADC Control and Status Regi
+ 'CADCSRA_CADEN': '$80', # When the CADEN bit is cleared
+ 'CADCSRA_CADPOL': '$40', #
+ 'CADCSRA_CADUB': '$20', # CC_ADC Update Busy
+ 'CADCSRA_CADAS': '$18', # CC_ADC Accumulate Current Sele
+ 'CADCSRA_CADSI': '$6', # The CADSI bits determine the c
+ 'CADCSRA_CADSE': '$1', # When the CADSE bit is written
+ 'CADCSRB' : '$e7', # CC-ADC Control and Status Regi
+ 'CADCSRB_CADACIE': '$40', #
+ 'CADCSRB_CADRCIE': '$20', # Regular Current Interrupt Enab
+ 'CADCSRB_CADICIE': '$10', # CAD Instantenous Current Inter
+ 'CADCSRB_CADACIF': '$4', # CC-ADC Accumulate Current Inte
+ 'CADCSRB_CADRCIF': '$2', # CC-ADC Accumulate Current Inte
+ 'CADCSRB_CADICIF': '$1', # CC-ADC Instantaneous Current I
+ 'CADCSRC' : '$e8', # CC-ADC Control and Status Regi
+ 'CADCSRC_CADVSE': '$1', # CC-ADC Voltage Scaling Enable
+ 'CADIC' : '$e4', # CC-ADC Instantaneous Current
+ 'CADAC3' : '$e3', # ADC Accumulate Current
+ 'CADAC2' : '$e2', # ADC Accumulate Current
+ 'CADAC1' : '$e1', # ADC Accumulate Current
+ 'CADAC0' : '$e0', # ADC Accumulate Current
+ 'CADRCC' : '$e9', # CC-ADC Regular Charge Current
+ 'CADRDC' : '$ea', # CC-ADC Regular Discharge Curre
+
+# Module TWI
+ 'TWBCSR' : '$be', # TWI Bus Control and Status Reg
+ 'TWBCSR_TWBCIF': '$80', # TWI Bus Connect/Disconnect Int
+ 'TWBCSR_TWBCIE': '$40', # TWI Bus Connect/Disconnect Int
+ 'TWBCSR_TWBDT': '$6', # TWI Bus Disconnect Time-out Pe
+ 'TWBCSR_TWBCIP': '$1', # TWI Bus Connect/Disconnect Int
+ 'TWAMR' : '$bd', # TWI (Slave) Address Mask Regis
+ 'TWAMR_TWAM': '$fe', #
+ 'TWBR' : '$b8', # TWI Bit Rate register
+ 'TWCR' : '$bc', # TWI Control Register
+ 'TWCR_TWINT': '$80', # TWI Interrupt Flag
+ 'TWCR_TWEA': '$40', # TWI Enable Acknowledge Bit
+ 'TWCR_TWSTA': '$20', # TWI Start Condition Bit
+ 'TWCR_TWSTO': '$10', # TWI Stop Condition Bit
+ 'TWCR_TWWC': '$8', # TWI Write Collition Flag
+ 'TWCR_TWEN': '$4', # TWI Enable Bit
+ 'TWCR_TWIE': '$1', # TWI Interrupt Enable
+ 'TWSR' : '$b9', # TWI Status Register
+ 'TWSR_TWS': '$f8', # TWI Status
+ 'TWSR_TWPS': '$3', # TWI Prescaler
+ 'TWDR' : '$bb', # TWI Data register
+ 'TWAR' : '$ba', # TWI (Slave) Address register
+ 'TWAR_TWA': '$fe', # TWI (Slave) Address register B
+ 'TWAR_TWGCE': '$1', # TWI General Call Recognition E
+
+# Module EXTERNAL_INTERRUPT
+ 'EICRA' : '$69', # External Interrupt Control Reg
+ 'EICRA_ISC3': '$c0', # External Interrupt Sense Contr
+ 'EICRA_ISC2': '$30', # External Interrupt Sense Contr
+ 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
+ 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
+ 'EIMSK' : '$3d', # External Interrupt Mask Regist
+ 'EIMSK_INT': '$f', # External Interrupt Request 3 E
+ 'EIFR' : '$3c', # External Interrupt Flag Regist
+ 'EIFR_INTF': '$f', # External Interrupt Flags
+ 'PCICR' : '$68', # Pin Change Interrupt Control R
+ 'PCICR_PCIE': '$3', # Pin Change Interrupt Enables
+ 'PCIFR' : '$3b', # Pin Change Interrupt Flag Regi
+ 'PCIFR_PCIF': '$3', # Pin Change Interrupt Flags
+ 'PCMSK1' : '$6c', # Pin Change Enable Mask Registe
+ 'PCMSK0' : '$6b', # Pin Change Enable Mask Registe
+
+# Module TIMER_COUNTER_1
+ 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
+ 'TCCR1B_CS': '$7', # Clock Select1 bis
+ 'TCCR1A' : '$80', # Timer/Counter 1 Control Regist
+ 'TCCR1A_TCW1': '$80', # Timer/Counter Width
+ 'TCCR1A_ICEN1': '$40', # Input Capture Mode Enable
+ 'TCCR1A_ICNC1': '$20', # Input Capture Noise Canceler
+ 'TCCR1A_ICES1': '$10', # Input Capture Edge Select
+ 'TCCR1A_ICS1': '$8', # Input Capture Select
+ 'TCCR1A_WGM10': '$1', # Waveform Generation Mode
+ 'TCNT1' : '$84', # Timer Counter 1 Bytes
+ 'OCR1A' : '$88', # Output Compare Register 1A
+ 'OCR1B' : '$89', # Output Compare Register B
+ 'TIMSK1' : '$6f', # Timer/Counter Interrupt Mask R
+ 'TIMSK1_ICIE1': '$8', # Timer/Counter n Input Capture
+ 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
+ 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
+ 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
+ 'TIFR1' : '$36', # Timer/Counter Interrupt Flag r
+ 'TIFR1_ICF1': '$8', # Timer/Counter 1 Input Capture
+ 'TIFR1_OCF1B': '$4', # Timer/Counter1 Output Compare
+ 'TIFR1_OCF1A': '$2', # Timer/Counter1 Output Compare
+ 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSRSYNC': '$1', # Prescaler Reset
+
+# Module CELL_BALANCING
+ 'CBCR' : '$f1', # Cell Balancing Control Registe
+ 'CBCR_CBE': '$f', # Cell Balancing Enables
+
+# Module BATTERY_PROTECTION
+ 'BPPLR' : '$fe', # Battery Protection Parameter L
+ 'BPPLR_BPPLE': '$2', # Battery Protection Parameter L
+ 'BPPLR_BPPL': '$1', # Battery Protection Parameter L
+ 'BPCR' : '$fd', # Battery Protection Control Reg
+ 'BPCR_EPID': '$20', # External Protection Input Disa
+ 'BPCR_SCD': '$10', # Short Circuit Protection Disab
+ 'BPCR_DOCD': '$8', # Discharge Over-current Protect
+ 'BPCR_COCD': '$4', # Charge Over-current Protection
+ 'BPCR_DHCD': '$2', # Discharge High-current Protect
+ 'BPCR_CHCD': '$1', # Charge High-current Protection
+ 'BPHCTR' : '$fc', # Battery Protection Short-curre
+ 'BPOCTR' : '$fb', # Battery Protection Over-curren
+ 'BPSCTR' : '$fa', # Battery Protection Short-curre
+ 'BPCHCD' : '$f9', # Battery Protection Charge-High
+ 'BPDHCD' : '$f8', # Battery Protection Discharge-H
+ 'BPCOCD' : '$f7', # Battery Protection Charge-Over
+ 'BPDOCD' : '$f6', # Battery Protection Discharge-O
+ 'BPSCD' : '$f5', # Battery Protection Short-Circu
+ 'BPIFR' : '$f3', # Battery Protection Interrupt F
+ 'BPIFR_SCIF': '$10', # Short-circuit Protection Activ
+ 'BPIFR_DOCIF': '$8', # Discharge Over-current Protect
+ 'BPIFR_COCIF': '$4', # Charge Over-current Protection
+ 'BPIFR_DHCIF': '$2', # Disharge High-current Protecti
+ 'BPIFR_CHCIF': '$1', # Charge High-current Protection
+ 'BPIMSK' : '$f2', # Battery Protection Interrupt M
+ 'BPIMSK_SCIE': '$10', # Short-circuit Protection Activ
+ 'BPIMSK_DOCIE': '$8', # Discharge Over-current Protect
+ 'BPIMSK_COCIE': '$4', # Charge Over-current Protection
+ 'BPIMSK_DHCIE': '$2', # Discharger High-current Protec
+ 'BPIMSK_CHCIE': '$1', # Charger High-current Protectio
+
+# Module CHARGER_DETECT
+ 'CHGDCSR' : '$d4', # Charger Detect Control and Sta
+ 'CHGDCSR_BATTPVL': '$10', # BATT Pin Voltage Level
+ 'CHGDCSR_CHGDISC': '$c', # Charger Detect Interrupt Sense
+ 'CHGDCSR_CHGDIF': '$2', # Charger Detect Interrupt Flag
+ 'CHGDCSR_CHGDIE': '$1', # Charger Detect Interrupt Enabl
+
+# Module VOLTAGE_REGULATOR
+ 'ROCR' : '$c8', # Regulator Operating Condition
+ 'ROCR_ROCS': '$80', # ROC Status
+ 'ROCR_ROCD': '$10', # ROC Disable
+ 'ROCR_ROCWIF': '$2', # ROC Warning Interrupt Flag
+ 'ROCR_ROCWIE': '$1', # ROC Warning Interrupt Enable
+
+# Module BANDGAP
+ 'BGCSR' : '$d2', # Bandgap Control and Status Reg
+ 'BGCSR_BGD': '$20', # Bandgap Disable
+ 'BGCSR_BGSCDE': '$10', # Bandgap Short Circuit Detectio
+ 'BGCSR_BGSCDIF': '$2', # Bandgap Short Circuit Detectio
+ 'BGCSR_BGSCDIE': '$1', # Bandgap Short Circuit Detectio
+ 'BGCRR' : '$d1', # Bandgap Calibration of Resisto
+ 'BGCCR' : '$d0', # Bandgap Calibration Register
+ 'BGCCR_BGCC': '$3f', # BG Calibration of PTAT Current
+
+# Module CPU
+ 'SREG' : '$5f', # Status Register
+ 'SREG_I': '$80', # Global Interrupt Enable
+ 'SREG_T': '$40', # Bit Copy Storage
+ 'SREG_H': '$20', # Half Carry Flag
+ 'SREG_S': '$10', # Sign Bit
+ 'SREG_V': '$8', # Two's Complement Overflow Flag
+ 'SREG_N': '$4', # Negative Flag
+ 'SREG_Z': '$2', # Zero Flag
+ 'SREG_C': '$1', # Carry Flag
+ 'SP' : '$5d', # Stack Pointer
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_CKOE': '$20', # Clock Output Enable
+ 'MCUCR_PUD': '$10', # Pull-up disable
+ 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
+ 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_OCDRF': '$10', # OCD Reset Flag
+ 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
+ 'MCUSR_BODRF': '$4', # Brown-out Reset Flag
+ 'MCUSR_EXTRF': '$2', # External Reset Flag
+ 'MCUSR_PORF': '$1', # Power-on reset flag
+ 'FOSCCAL' : '$66', # Fast Oscillator Calibration Va
+ 'OSICSR' : '$37', # Oscillator Sampling Interface
+ 'OSICSR_OSISEL0': '$10', # Oscillator Sampling Interface
+ 'OSICSR_OSIST': '$2', # Oscillator Sampling Interface
+ 'OSICSR_OSIEN': '$1', # Oscillator Sampling Interface
+ 'SMCR' : '$53', # Sleep Mode Control Register
+ 'SMCR_SM': '$e', # Sleep Mode Select bits
+ 'SMCR_SE': '$1', # Sleep Enable
+ 'GPIOR2' : '$4b', # General Purpose IO Register 2
+ 'GPIOR1' : '$4a', # General Purpose IO Register 1
+ 'GPIOR0' : '$3e', # General Purpose IO Register 0
+ 'DIDR0' : '$7e', # Digital Input Disable Register
+ 'DIDR0_PA1DID': '$2', # When this bit is written logic
+ 'DIDR0_PA0DID': '$1', # When this bit is written logic
+ 'PRR0' : '$64', # Power Reduction Register 0
+ 'PRR0_PRTWI': '$40', # Power Reduction TWI
+ 'PRR0_PRVRM': '$20', # Power Reduction Voltage Regula
+ 'PRR0_PRSPI': '$8', # Power reduction SPI
+ 'PRR0_PRTIM1': '$4', # Power Reduction Timer/Counter1
+ 'PRR0_PRTIM0': '$2', # Power Reduction Timer/Counter0
+ 'PRR0_PRVADC': '$1', # Power Reduction V-ADC
+ 'CLKPR' : '$61', # Clock Prescale Register
+ 'CLKPR_CLKPCE': '$80', # Clock Prescaler Change Enable
+ 'CLKPR_CLKPS': '$3', # Clock Prescaler Select Bits
+
+# Module PORTA
+ 'PORTA' : '$22', # Port A Data Register
+ 'DDRA' : '$21', # Port A Data Direction Register
+ 'PINA' : '$20', # Port A Input Pins
+
+# Module PORTB
+ 'PORTB' : '$25', # Port B Data Register
+ 'DDRB' : '$24', # Port B Data Direction Register
+ 'PINB' : '$23', # Port B Input Pins
+
+# Module PORTC
+ 'PORTC' : '$28', # Port C Data Register
+ 'PINC' : '$26', # Port C Input Pins
+
+# Module TIMER_COUNTER_0
+ 'TCCR0B' : '$45', # Timer/Counter0 Control Registe
+ 'TCCR0B_CS02': '$4', # Clock Select0 bit 2
+ 'TCCR0B_CS01': '$2', # Clock Select0 bit 1
+ 'TCCR0B_CS00': '$1', # Clock Select0 bit 0
+ 'TCCR0A' : '$44', # Timer/Counter 0 Control Regist
+ 'TCCR0A_TCW0': '$80', # Timer/Counter Width
+ 'TCCR0A_ICEN0': '$40', # Input Capture Mode Enable
+ 'TCCR0A_ICNC0': '$20', # Input Capture Noise Canceler
+ 'TCCR0A_ICES0': '$10', # Input Capture Edge Select
+ 'TCCR0A_ICS0': '$8', # Input Capture Select
+ 'TCCR0A_WGM00': '$1', # Waveform Generation Mode
+ 'TCNT0' : '$46', # Timer Counter 0 Bytes
+ 'OCR0A' : '$48', # Output Compare Register 0A
+ 'OCR0B' : '$49', # Output Compare Register B
+ 'TIMSK0' : '$6e', # Timer/Counter Interrupt Mask R
+ 'TIMSK0_ICIE0': '$8', # Timer/Counter n Input Capture
+ 'TIMSK0_OCIE0B': '$4', # Timer/Counter0 Output Compare
+ 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
+ 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
+ 'TIFR0' : '$35', # Timer/Counter Interrupt Flag r
+ 'TIFR0_ICF0': '$8', # Timer/Counter 0 Input Capture
+ 'TIFR0_OCF0B': '$4', # Timer/Counter0 Output Compare
+ 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
+ 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSRSYNC': '$1', # Prescaler Reset
+
+# Module BOOT_LOAD
+ 'SPMCSR' : '$57', # Store Program Memory Control a
+ 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
+ 'SPMCSR_RWWSB': '$40', # Read-While-Write Section Busy
+ 'SPMCSR_SIGRD': '$20', # Signature Row Read
+ 'SPMCSR_RWWSRE': '$10', # Read-While-Write Section Read
+ 'SPMCSR_LBSET': '$8', # Lock Bit Set
+ 'SPMCSR_PGWRT': '$4', # Page Write
+ 'SPMCSR_PGERS': '$2', # Page Erase
+ 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
+
+ '__amforth_dummy':'0'
+}
diff --git a/amforth-6.5/avr8/devices/atmega16hvbrevb/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega16hvbrevb/words/no-jtag.asm
new file mode 100644
index 0000000..352a4bb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega16hvbrevb/words/no-jtag.asm
@@ -0,0 +1,14 @@
+; ( -- )
+; ( -- )
+; MCU
+; disable jtag at runtime
+VE_NOJTAG:
+ .dw $FF05
+ .db "-jtag",0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOJTAG
+XT_NOJTAG:
+ .dw PFA_NOJTAG
+PFA_NOJTAG:
+
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega16hvbrevb/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega16hvbrevb/words/no-wdt.asm
new file mode 100644
index 0000000..4a12261
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega16hvbrevb/words/no-wdt.asm
@@ -0,0 +1,22 @@
+; ( -- )
+; MCU
+; disable watch dog timer at runtime
+VE_NOWDT:
+ .dw $ff04
+ .db "-wdt"
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOWDT
+XT_NOWDT:
+ .dw PFA_NOWDT
+PFA_NOWDT:
+
+; Reset WDT
+ wdr
+; Write logical one to WDTOE and WDE
+ in_ temp1, WDTCR
+ ori temp1, (1<<WDTOE)|(1<<WDE)
+ out WDTCR, temp1
+; Turn off WDT
+ ldi temp1, (0<<WDE)
+ out_ WDTCR, temp1
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega16hvbrevb/words/sleep.asm b/amforth-6.5/avr8/devices/atmega16hvbrevb/words/sleep.asm
new file mode 100644
index 0000000..778fa32
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega16hvbrevb/words/sleep.asm
@@ -0,0 +1,24 @@
+; ( mode -- )
+; MCU
+; put the controller into the specified sleep mode
+VE_SLEEP:
+ .dw $ff05
+ .db "sleep", 0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_SLEEP
+XT_SLEEP:
+ .dw PFA_SLEEP
+PFA_SLEEP:
+ andi tosl, 7 ; leave only legal mode bits
+ swap tosl ; move to correct location (bits 6-4, atmega32)
+ ori tosl, $80 ; set the SE bit (atmega32: bit 7, not bit 0)
+ out_ MCUCR, tosl ; set the sleep config (atmega32: MCUCR not SMCR)
+ sleep ; nighty-night
+;; the 4 lower bits of MCUCR should not be touched
+ in_ tosl, MCUCR
+ andi tosl, $0F
+ out_ MCUCR, tosl
+ ;clr tosl ; need to clean up the SMCR reg before we leave
+ ;out SMCR, tosl ; 0 protects against accidental sleeps
+ loadtos ; pop argument from stack
+ jmp DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega16m1/atmega16m1.frt b/amforth-6.5/avr8/devices/atmega16m1/atmega16m1.frt
new file mode 100644
index 0000000..3d6977c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega16m1/atmega16m1.frt
@@ -0,0 +1,513 @@
+\ Partname: ATmega16M1
+\ generated automatically
+
+\ PORTB
+&37 constant PORTB \ Port B Data Register
+&36 constant DDRB \ Port B Data Direction Register
+&35 constant PINB \ Port B Input Pins
+\ PORTC
+&40 constant PORTC \ Port C Data Register
+&39 constant DDRC \ Port C Data Direction Register
+&38 constant PINC \ Port C Input Pins
+\ PORTD
+&43 constant PORTD \ Port D Data Register
+&42 constant DDRD \ Port D Data Direction Register
+&41 constant PIND \ Port D Input Pins
+\ CAN
+&216 constant CANGCON \ CAN General Control Register
+ $80 constant CANGCON_ABRQ \ Abort Request
+ $40 constant CANGCON_OVRQ \ Overload Frame Request
+ $20 constant CANGCON_TTC \ Time Trigger Communication
+ $10 constant CANGCON_SYNTTC \ Synchronization of TTC
+ $08 constant CANGCON_LISTEN \ Listening Mode
+ $04 constant CANGCON_TEST \ Test Mode
+ $02 constant CANGCON_ENASTB \ Enable / Standby
+ $01 constant CANGCON_SWRES \ Software Reset Request
+&217 constant CANGSTA \ CAN General Status Register
+ $40 constant CANGSTA_OVFG \ Overload Frame Flag
+ $10 constant CANGSTA_TXBSY \ Transmitter Busy
+ $08 constant CANGSTA_RXBSY \ Receiver Busy
+ $04 constant CANGSTA_ENFG \ Enable Flag
+ $02 constant CANGSTA_BOFF \ Bus Off Mode
+ $01 constant CANGSTA_ERRP \ Error Passive Mode
+&218 constant CANGIT \ CAN General Interrupt Register Flags
+ $80 constant CANGIT_CANIT \ General Interrupt Flag
+ $40 constant CANGIT_BOFFIT \ Bus Off Interrupt Flag
+ $20 constant CANGIT_OVRTIM \ Overrun CAN Timer Flag
+ $10 constant CANGIT_BXOK \ Burst Receive Interrupt Flag
+ $08 constant CANGIT_SERG \ Stuff Error General Flag
+ $04 constant CANGIT_CERG \ CRC Error General Flag
+ $02 constant CANGIT_FERG \ Form Error General Flag
+ $01 constant CANGIT_AERG \ Ackknowledgement Error General Flag
+&219 constant CANGIE \ CAN General Interrupt Enable Register
+ $80 constant CANGIE_ENIT \ Enable all Interrupts
+ $40 constant CANGIE_ENBOFF \ Enable Bus Off Interrupt
+ $20 constant CANGIE_ENRX \ Enable Receive Interrupt
+ $10 constant CANGIE_ENTX \ Enable Transmitt Interrupt
+ $08 constant CANGIE_ENERR \ Enable MOb Error Interrupt
+ $04 constant CANGIE_ENBX \ Enable Burst Receive Interrupt
+ $02 constant CANGIE_ENERG \ Enable General Error Interrupt
+ $01 constant CANGIE_ENOVRT \ Enable CAN Timer Overrun Interrupt
+&220 constant CANEN2 \ Enable MOb Register 2
+ $3F constant CANEN2_ENMOB \ Enable MObs
+&221 constant CANEN1 \ Enable MOb Register 1(empty)
+&222 constant CANIE2 \ Enable Interrupt MOb Register 2
+ $3F constant CANIE2_IEMOB \ Interrupt Enable MObs
+&223 constant CANIE1 \ Enable Interrupt MOb Register 1 (empty)
+&224 constant CANSIT2 \ CAN Status Interrupt MOb Register 2
+ $3F constant CANSIT2_SIT \ Status of Interrupt MObs
+&225 constant CANSIT1 \ CAN Status Interrupt MOb Register 1 (empty)
+&226 constant CANBT1 \ CAN Bit Timing Register 1
+ $7E constant CANBT1_BRP \ Baud Rate Prescaler bits
+&227 constant CANBT2 \ CAN Bit Timing Register 2
+ $60 constant CANBT2_SJW \ Re-Sync Jump Width bits
+ $0E constant CANBT2_PRS \ Propagation Time Segment bits
+&228 constant CANBT3 \ CAN Bit Timing Register 3
+ $70 constant CANBT3_PHS2 \ Phase Segment 2 bits
+ $0E constant CANBT3_PHS1 \ Phase Segment 1 bits
+ $01 constant CANBT3_SMP \ Sample Type
+&229 constant CANTCON \ Timer Control Register
+&230 constant CANTIML \ Timer Register Low
+&231 constant CANTIMH \ Timer Register High
+&232 constant CANTTCL \ TTC Timer Register Low
+&233 constant CANTTCH \ TTC Timer Register High
+&234 constant CANTEC \ Transmit Error Counter Register
+&235 constant CANREC \ Receive Error Counter Register
+&236 constant CANHPMOB \ Highest Priority MOb Register
+ $F0 constant CANHPMOB_HPMOB \ Highest Priority MOb Number bits
+ $0F constant CANHPMOB_CGP \ CAN General Purpose bits
+&237 constant CANPAGE \ Page MOb Register
+ $F0 constant CANPAGE_MOBNB \ MOb Number bits
+ $08 constant CANPAGE_AINC \ MOb Data Buffer Auto Increment (Active Low)
+ $07 constant CANPAGE_INDX \ Data Buffer Index bits
+&238 constant CANSTMOB \ MOb Status Register
+ $80 constant CANSTMOB_DLCW \ Data Length Code Warning on MOb
+ $40 constant CANSTMOB_TXOK \ Transmit OK on MOb
+ $20 constant CANSTMOB_RXOK \ Receive OK on MOb
+ $10 constant CANSTMOB_BERR \ Bit Error on MOb
+ $08 constant CANSTMOB_SERR \ Stuff Error on MOb
+ $04 constant CANSTMOB_CERR \ CRC Error on MOb
+ $02 constant CANSTMOB_FERR \ Form Error on MOb
+ $01 constant CANSTMOB_AERR \ Ackknowledgement Error on MOb
+&239 constant CANCDMOB \ MOb Control and DLC Register
+ $C0 constant CANCDMOB_CONMOB \ MOb Config bits
+ $20 constant CANCDMOB_RPLV \ Reply Valid
+ $10 constant CANCDMOB_IDE \ Identifier Extension
+ $0F constant CANCDMOB_DLC \ Data Length Code bits
+&240 constant CANIDT4 \ Identifier Tag Register 4
+ $F8 constant CANIDT4_IDT \
+ $04 constant CANIDT4_RTRTAG \
+ $02 constant CANIDT4_RB1TAG \
+ $01 constant CANIDT4_RB0TAG \
+&241 constant CANIDT3 \ Identifier Tag Register 3
+&242 constant CANIDT2 \ Identifier Tag Register 2
+&243 constant CANIDT1 \ Identifier Tag Register 1
+&244 constant CANIDM4 \ Identifier Mask Register 4
+&245 constant CANIDM3 \ Identifier Mask Register 3
+&246 constant CANIDM2 \ Identifier Mask Register 2
+&247 constant CANIDM1 \ Identifier Mask Register 1
+&248 constant CANSTML \ Time Stamp Register Low
+&249 constant CANSTMH \ Time Stamp Register High
+&250 constant CANMSG \ Message Data Register
+\ ANALOG_COMPARATOR
+&148 constant AC0CON \ Analog Comparator 0 Control Register
+ $80 constant AC0CON_AC0EN \ Analog Comparator 0 Enable Bit
+ $40 constant AC0CON_AC0IE \ Analog Comparator 0 Interrupt Enable Bit
+ $30 constant AC0CON_AC0IS \ Analog Comparator 0 Interrupt Select Bits
+ $08 constant AC0CON_ACCKSEL \ Analog Comparator Clock Select
+ $07 constant AC0CON_AC0M \ Analog Comparator 0 Multiplexer Register
+&149 constant AC1CON \ Analog Comparator 1 Control Register
+ $80 constant AC1CON_AC1EN \ Analog Comparator 1 Enable Bit
+ $40 constant AC1CON_AC1IE \ Analog Comparator 1 Interrupt Enable Bit
+ $30 constant AC1CON_AC1IS \ Analog Comparator 1 Interrupt Select Bit
+ $08 constant AC1CON_AC1ICE \ Analog Comparator 1 Interrupt Capture Enable Bit
+ $07 constant AC1CON_AC1M \ Analog Comparator 1 Multiplexer Register
+&150 constant AC2CON \ Analog Comparator 2 Control Register
+ $80 constant AC2CON_AC2EN \ Analog Comparator 2 Enable Bit
+ $40 constant AC2CON_AC2IE \ Analog Comparator 2 Interrupt Enable Bit
+ $30 constant AC2CON_AC2IS \ Analog Comparator 2 Interrupt Select Bit
+ $07 constant AC2CON_AC2M \ Analog Comparator 2 Multiplexer Register
+&151 constant AC3CON \ Analog Comparator 3 Control Register
+ $80 constant AC3CON_AC3EN \ Analog Comparator 3 Enable Bit
+ $40 constant AC3CON_AC3IE \ Analog Comparator 3 Interrupt Enable Bit
+ $30 constant AC3CON_AC3IS \ Analog Comparator 3 Interrupt Select Bit
+ $07 constant AC3CON_AC3M \ Analog Comparator 3 Multiplexer Register
+&80 constant ACSR \ Analog Comparator Status Register
+ $80 constant ACSR_AC3IF \ Analog Comparator 3 Interrupt Flag Bit
+ $40 constant ACSR_AC2IF \ Analog Comparator 2 Interrupt Flag Bit
+ $20 constant ACSR_AC1IF \ Analog Comparator 1 Interrupt Flag Bit
+ $10 constant ACSR_AC0IF \ Analog Comparator 0 Interrupt Flag Bit
+ $08 constant ACSR_AC3O \ Analog Comparator 3 Output Bit
+ $04 constant ACSR_AC2O \ Analog Comparator 2 Output Bit
+ $02 constant ACSR_AC1O \ Analog Comparator 1 Output Bit
+ $01 constant ACSR_AC0O \ Analog Comparator 0 Output Bit
+\ DA_CONVERTER
+&146 constant DACH \ DAC Data Register High Byte
+ $FF constant DACH_DACH \ DAC Data Register High Byte Bits
+&145 constant DACL \ DAC Data Register Low Byte
+ $FF constant DACL_DACL \ DAC Data Register Low Byte Bits
+&144 constant DACON \ DAC Control Register
+ $80 constant DACON_DAATE \ DAC Auto Trigger Enable Bit
+ $70 constant DACON_DATS \ DAC Trigger Selection Bits
+ $04 constant DACON_DALA \ DAC Left Adjust
+ $01 constant DACON_DAEN \ DAC Enable Bit
+\ CPU
+&87 constant SPMCSR \ Store Program Memory Control Register
+ $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
+ $20 constant SPMCSR_SIGRD \ Signature Row Read
+ $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
+ $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
+ $04 constant SPMCSR_PGWRT \ Page Write
+ $02 constant SPMCSR_PGERS \ Page Erase
+ $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
+&95 constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ $08 constant SREG_V \ Two's Complement Overflow Flag
+ $04 constant SREG_N \ Negative Flag
+ $02 constant SREG_Z \ Zero Flag
+ $01 constant SREG_C \ Carry Flag
+&93 constant SP \ Stack Pointer
+&85 constant MCUCR \ MCU Control Register
+ $80 constant MCUCR_SPIPS \ SPI Pin Select
+ $10 constant MCUCR_PUD \ Pull-up disable
+ $02 constant MCUCR_IVSEL \ Interrupt Vector Select
+ $01 constant MCUCR_IVCE \ Interrupt Vector Change Enable
+&84 constant MCUSR \ MCU Status Register
+ $08 constant MCUSR_WDRF \ Watchdog Reset Flag
+ $04 constant MCUSR_BORF \ Brown-out Reset Flag
+ $02 constant MCUSR_EXTRF \ External Reset Flag
+ $01 constant MCUSR_PORF \ Power-on reset flag
+&102 constant OSCCAL \ Oscillator Calibration Value
+&97 constant CLKPR \
+ $80 constant CLKPR_CLKPCE \
+ $0F constant CLKPR_CLKPS \
+&83 constant SMCR \ Sleep Mode Control Register
+ $0E constant SMCR_SM \ Sleep Mode Select bits
+ $01 constant SMCR_SE \ Sleep Enable
+&58 constant GPIOR2 \ General Purpose IO Register 2
+ $FF constant GPIOR2_GPIOR \ General Purpose IO Register 2 bis
+&57 constant GPIOR1 \ General Purpose IO Register 1
+ $FF constant GPIOR1_GPIOR \ General Purpose IO Register 1 bis
+&62 constant GPIOR0 \ General Purpose IO Register 0
+ $80 constant GPIOR0_GPIOR07 \ General Purpose IO Register 0 bit 7
+ $40 constant GPIOR0_GPIOR06 \ General Purpose IO Register 0 bit 6
+ $20 constant GPIOR0_GPIOR05 \ General Purpose IO Register 0 bit 5
+ $10 constant GPIOR0_GPIOR04 \ General Purpose IO Register 0 bit 4
+ $08 constant GPIOR0_GPIOR03 \ General Purpose IO Register 0 bit 3
+ $04 constant GPIOR0_GPIOR02 \ General Purpose IO Register 0 bit 2
+ $02 constant GPIOR0_GPIOR01 \ General Purpose IO Register 0 bit 1
+ $01 constant GPIOR0_GPIOR00 \ General Purpose IO Register 0 bit 0
+&73 constant PLLCSR \ PLL Control And Status Register
+ $04 constant PLLCSR_PLLF \ PLL Factor
+ $02 constant PLLCSR_PLLE \ PLL Enable
+ $01 constant PLLCSR_PLOCK \ PLL Lock Detector
+&100 constant PRR \ Power Reduction Register
+ $40 constant PRR_PRCAN \ Power Reduction CAN
+ $20 constant PRR_PRPSC \ Power Reduction PSC
+ $10 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
+ $08 constant PRR_PRTIM0 \ Power Reduction Timer/Counter0
+ $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
+ $02 constant PRR_PRLIN \ Power Reduction LIN UART
+ $01 constant PRR_PRADC \ Power Reduction ADC
+\ PORTE
+&46 constant PORTE \ Port E Data Register
+&45 constant DDRE \ Port E Data Direction Register
+&44 constant PINE \ Port E Input Pins
+\ TIMER_COUNTER_0
+&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
+ $04 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare Match B Interrupt Enable
+ $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match A Interrupt Enable
+ $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
+&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
+ $04 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare Flag 0B
+ $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0A
+ $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
+&68 constant TCCR0A \ Timer/Counter Control Register A
+ $C0 constant TCCR0A_COM0A \ Compare Output Mode, Phase Correct PWM Mode
+ $30 constant TCCR0A_COM0B \ Compare Output Mode, Fast PWm
+ $03 constant TCCR0A_WGM0 \ Waveform Generation Mode
+&69 constant TCCR0B \ Timer/Counter Control Register B
+ $80 constant TCCR0B_FOC0A \ Force Output Compare A
+ $40 constant TCCR0B_FOC0B \ Force Output Compare B
+ $08 constant TCCR0B_WGM02 \
+ $07 constant TCCR0B_CS0 \ Clock Select
+&70 constant TCNT0 \ Timer/Counter0
+&71 constant OCR0A \ Timer/Counter0 Output Compare Register
+&72 constant OCR0B \ Timer/Counter0 Output Compare Register
+&67 constant GTCCR \ General Timer/Counter Control Register
+ $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
+ $40 constant GTCCR_ICPSEL1 \ Timer1 Input Capture Selection Bit
+ $01 constant GTCCR_PSR10 \ Prescaler Reset Timer/Counter1 and Timer/Counter0
+\ TIMER_COUNTER_1
+&111 constant TIMSK1 \ Timer/Counter Interrupt Mask Register
+ $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
+ $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output CompareB Match Interrupt Enable
+ $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output CompareA Match Interrupt Enable
+ $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
+&54 constant TIFR1 \ Timer/Counter Interrupt Flag register
+ $20 constant TIFR1_ICF1 \ Input Capture Flag 1
+ $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
+ $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
+ $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
+&128 constant TCCR1A \ Timer/Counter1 Control Register A
+ $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
+ $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
+ $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
+&129 constant TCCR1B \ Timer/Counter1 Control Register B
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
+ $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
+&130 constant TCCR1C \ Timer/Counter1 Control Register C
+ $80 constant TCCR1C_FOC1A \
+ $40 constant TCCR1C_FOC1B \
+&132 constant TCNT1 \ Timer/Counter1 Bytes
+&136 constant OCR1A \ Timer/Counter1 Output Compare Register Bytes
+&138 constant OCR1B \ Timer/Counter1 Output Compare Register Bytes
+&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
+\ AD_CONVERTER
+&124 constant ADMUX \ The ADC multiplexer Selection Register
+ $C0 constant ADMUX_REFS \ Reference Selection Bits
+ $20 constant ADMUX_ADLAR \ Left Adjust Result
+ $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
+&122 constant ADCSRA \ The ADC Control and Status register
+ $80 constant ADCSRA_ADEN \ ADC Enable
+ $40 constant ADCSRA_ADSC \ ADC Start Conversion
+ $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
+ $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
+ $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
+ $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
+&120 constant ADC \ ADC Data Register Bytes
+&123 constant ADCSRB \ ADC Control and Status Register B
+ $80 constant ADCSRB_ADHSM \ ADC High Speed Mode
+ $40 constant ADCSRB_ISRCEN \ Current Source Enable
+ $20 constant ADCSRB_AREFEN \ Analog Reference pin Enable
+ $0F constant ADCSRB_ADTS \ ADC Auto Trigger Sources
+&126 constant DIDR0 \ Digital Input Disable Register 0
+ $80 constant DIDR0_ADC7D \ ADC7 Digital input Disable
+ $40 constant DIDR0_ADC6D \ ADC6 Digital input Disable
+ $20 constant DIDR0_ADC5D \ ADC5 Digital input Disable
+ $10 constant DIDR0_ADC4D \ ADC4 Digital input Disable
+ $08 constant DIDR0_ADC3D \ ADC3 Digital input Disable
+ $04 constant DIDR0_ADC2D \ ADC2 Digital input Disable
+ $02 constant DIDR0_ADC1D \ ADC1 Digital input Disable
+ $01 constant DIDR0_ADC0D \ ADC0 Digital input Disable
+&127 constant DIDR1 \ Digital Input Disable Register 0
+ $40 constant DIDR1_AMP2PD \ AMP2P Pin Digital input Disable
+ $20 constant DIDR1_ACMP0D \ ACMP0 Pin Digital input Disable
+ $10 constant DIDR1_AMP0PD \ AMP0P Pin Digital input Disable
+ $08 constant DIDR1_AMP0ND \ AMP0N Pin Digital input Disable
+ $04 constant DIDR1_ADC10D \ ADC10 Pin Digital input Disable
+ $02 constant DIDR1_ADC9D \ ADC9 Pin Digital input Disable
+ $01 constant DIDR1_ADC8D \ ADC8 Pin Digital input Disable
+&117 constant AMP0CSR \
+ $80 constant AMP0CSR_AMP0EN \
+ $40 constant AMP0CSR_AMP0IS \
+ $30 constant AMP0CSR_AMP0G \
+ $08 constant AMP0CSR_AMPCMP0 \ Amplifier 0 - Comparator 0 Connection
+ $07 constant AMP0CSR_AMP0TS \
+&118 constant AMP1CSR \
+ $80 constant AMP1CSR_AMP1EN \
+ $40 constant AMP1CSR_AMP1IS \
+ $30 constant AMP1CSR_AMP1G \
+ $08 constant AMP1CSR_AMPCMP1 \ Amplifier 1 - Comparator 1 Connection
+ $07 constant AMP1CSR_AMP1TS \
+&119 constant AMP2CSR \
+ $80 constant AMP2CSR_AMP2EN \
+ $40 constant AMP2CSR_AMP2IS \
+ $30 constant AMP2CSR_AMP2G \
+ $08 constant AMP2CSR_AMPCMP2 \ Amplifier 2 - Comparator 2 Connection
+ $07 constant AMP2CSR_AMP2TS \
+\ LINUART
+&200 constant LINCR \ LIN Control Register
+ $80 constant LINCR_LSWRES \ Software Reset
+ $40 constant LINCR_LIN13 \ LIN Standard
+ $30 constant LINCR_LCONF \ LIN Configuration bits
+ $08 constant LINCR_LENA \ LIN or UART Enable
+ $07 constant LINCR_LCMD \ LIN Command and Mode bits
+&201 constant LINSIR \ LIN Status and Interrupt Register
+ $E0 constant LINSIR_LIDST \ Identifier Status bits
+ $10 constant LINSIR_LBUSY \ Busy Signal
+ $08 constant LINSIR_LERR \ Error Interrupt
+ $04 constant LINSIR_LIDOK \ Identifier Interrupt
+ $02 constant LINSIR_LTXOK \ Transmit Performed Interrupt
+ $01 constant LINSIR_LRXOK \ Receive Performed Interrupt
+&202 constant LINENIR \ LIN Enable Interrupt Register
+ $08 constant LINENIR_LENERR \ Enable Error Interrupt
+ $04 constant LINENIR_LENIDOK \ Enable Identifier Interrupt
+ $02 constant LINENIR_LENTXOK \ Enable Transmit Performed Interrupt
+ $01 constant LINENIR_LENRXOK \ Enable Receive Performed Interrupt
+&203 constant LINERR \ LIN Error Register
+ $80 constant LINERR_LABORT \ Abort Flag
+ $40 constant LINERR_LTOERR \ Frame Time Out Error Flag
+ $20 constant LINERR_LOVERR \ Overrun Error Flag
+ $10 constant LINERR_LFERR \ Framing Error Flag
+ $08 constant LINERR_LSERR \ Synchronization Error Flag
+ $04 constant LINERR_LPERR \ Parity Error Flag
+ $02 constant LINERR_LCERR \ Checksum Error Flag
+ $01 constant LINERR_LBERR \ Bit Error Flag
+&204 constant LINBTR \ LIN Bit Timing Register
+ $80 constant LINBTR_LDISR \ Disable Bit Timing Resynchronization
+ $3F constant LINBTR_LBT \ LIN Bit Timing bits
+&205 constant LINBRRL \ LIN Baud Rate Low Register
+ $FF constant LINBRRL_LDIV \
+&206 constant LINBRRH \ LIN Baud Rate High Register
+ $0F constant LINBRRH_LDIV \
+&207 constant LINDLR \ LIN Data Length Register
+ $F0 constant LINDLR_LTXDL \ LIN Transmit Data Length bits
+ $0F constant LINDLR_LRXDL \ LIN Receive Data Length bits
+&208 constant LINIDR \ LIN Identifier Register
+ $C0 constant LINIDR_LP \ Parity bits
+ $3F constant LINIDR_LID \ Identifier bit 5 or Data Length bits
+&209 constant LINSEL \ LIN Data Buffer Selection Register
+ $08 constant LINSEL_LAINC \ Auto Increment of Data Buffer Index (Active Low)
+ $07 constant LINSEL_LINDX \ FIFO LIN Data Buffer Index bits
+&210 constant LINDAT \ LIN Data Register
+ $FF constant LINDAT_LDATA \
+\ SPI
+&76 constant SPCR \ SPI Control Register
+ $80 constant SPCR_SPIE \ SPI Interrupt Enable
+ $40 constant SPCR_SPE \ SPI Enable
+ $20 constant SPCR_DORD \ Data Order
+ $10 constant SPCR_MSTR \ Master/Slave Select
+ $08 constant SPCR_CPOL \ Clock polarity
+ $04 constant SPCR_CPHA \ Clock Phase
+ $03 constant SPCR_SPR \ SPI Clock Rate Selects
+&77 constant SPSR \ SPI Status Register
+ $80 constant SPSR_SPIF \ SPI Interrupt Flag
+ $40 constant SPSR_WCOL \ Write Collision Flag
+ $01 constant SPSR_SPI2X \ Double SPI Speed Bit
+&78 constant SPDR \ SPI Data Register
+\ WATCHDOG
+&96 constant WDTCSR \ Watchdog Timer Control Register
+ $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Flag
+ $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Enable
+ $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
+ $10 constant WDTCSR_WDCE \ Watchdog Change Enable
+ $08 constant WDTCSR_WDE \ Watch Dog Enable
+\ EXTERNAL_INTERRUPT
+&105 constant EICRA \ External Interrupt Control Register
+ $C0 constant EICRA_ISC3 \ External Interrupt Sense Control Bit
+ $30 constant EICRA_ISC2 \ External Interrupt Sense Control Bit
+ $0C constant EICRA_ISC1 \ External Interrupt Sense Control 1 Bits
+ $03 constant EICRA_ISC0 \ External Interrupt Sense Control 0 Bits
+&61 constant EIMSK \ External Interrupt Mask Register
+ $0F constant EIMSK_INT \ External Interrupt Request 3 Enable
+&60 constant EIFR \ External Interrupt Flag Register
+ $0F constant EIFR_INTF \ External Interrupt Flags
+&104 constant PCICR \ Pin Change Interrupt Control Register
+ $0F constant PCICR_PCIE \ Pin Change Interrupt Enables
+&109 constant PCMSK3 \ Pin Change Mask Register 3
+ $07 constant PCMSK3_PCINT \ Pin Change Enable Masks
+&108 constant PCMSK2 \ Pin Change Mask Register 2
+ $FF constant PCMSK2_PCINT \ Pin Change Enable Masks
+&107 constant PCMSK1 \ Pin Change Mask Register 1
+ $FF constant PCMSK1_PCINT \ Pin Change Enable Masks
+&106 constant PCMSK0 \ Pin Change Mask Register 0
+ $FF constant PCMSK0_PCINT \ Pin Change Enable Masks
+&59 constant PCIFR \ Pin Change Interrupt Flag Register
+ $0F constant PCIFR_PCIF \ Pin Change Interrupt Flags
+\ EEPROM
+&65 constant EEAR \ EEPROM Read/Write Access
+&64 constant EEDR \ EEPROM Data Register
+&63 constant EECR \ EEPROM Control Register
+ $30 constant EECR_EEPM \
+ $08 constant EECR_EERIE \ EEProm Ready Interrupt Enable
+ $04 constant EECR_EEMWE \ EEPROM Master Write Enable
+ $02 constant EECR_EEWE \ EEPROM Write Enable
+ $01 constant EECR_EERE \ EEPROM Read Enable
+\ PSC
+&188 constant PIFR \ PSC Interrupt Flag Register
+ $0E constant PIFR_PEV \ PSC External Event 2 Interrupt
+ $01 constant PIFR_PEOP \ PSC End of Cycle Interrupt
+&187 constant PIM \ PSC Interrupt Mask Register
+ $0E constant PIM_PEVE \ External Event 2 Interrupt Enable
+ $01 constant PIM_PEOPE \ PSC End of Cycle Interrupt Enable
+&186 constant PMIC2 \ PSC Module 2 Input Control Register
+ $80 constant PMIC2_POVEN2 \ PSC Module 2 Overlap Enable
+ $40 constant PMIC2_PISEL2 \ PSC Module 2 Input Select
+ $20 constant PMIC2_PELEV2 \ PSC Module 2 Input Level Selector
+ $10 constant PMIC2_PFLTE2 \ PSC Module 2 Input Filter Enable
+ $08 constant PMIC2_PAOC2 \ PSC Module 2 Asynchronous Output Control
+ $07 constant PMIC2_PRFM2 \ PSC Module 2 Input Mode bits
+&185 constant PMIC1 \ PSC Module 1 Input Control Register
+ $80 constant PMIC1_POVEN1 \ PSC Module 1 Overlap Enable
+ $40 constant PMIC1_PISEL1 \ PSC Module 1 Input Select
+ $20 constant PMIC1_PELEV1 \ PSC Module 1 Input Level Selector
+ $10 constant PMIC1_PFLTE1 \ PSC Module 1 Input Filter Enable
+ $08 constant PMIC1_PAOC1 \ PSC Module 1 Asynchronous Output Control
+ $07 constant PMIC1_PRFM1 \ PSC Module 1 Input Mode bits
+&184 constant PMIC0 \ PSC Module 0 Input Control Register
+ $80 constant PMIC0_POVEN0 \ PSC Module 0 Overlap Enable
+ $40 constant PMIC0_PISEL0 \ PSC Module 0 Input Select
+ $20 constant PMIC0_PELEV0 \ PSC Module 0 Input Level Selector
+ $10 constant PMIC0_PFLTE0 \ PSC Module 0 Input Filter Enable
+ $08 constant PMIC0_PAOC0 \ PSC Module 0 Asynchronous Output Control
+ $07 constant PMIC0_PRFM0 \ PSC Module 0 Input Mode bits
+&183 constant PCTL \ PSC Control Register
+ $C0 constant PCTL_PPRE \ PSC Prescaler Select bits
+ $20 constant PCTL_PCLKSEL \ PSC Input Clock Select
+ $02 constant PCTL_PCCYC \ PSC Complete Cycle
+ $01 constant PCTL_PRUN \ PSC Run
+&182 constant POC \ PSC Output Configuration
+ $20 constant POC_POEN2B \ PSC Output 2B Enable
+ $10 constant POC_POEN2A \ PSC Output 2A Enable
+ $08 constant POC_POEN1B \ PSC Output 1B Enable
+ $04 constant POC_POEN1A \ PSC Output 1A Enable
+ $02 constant POC_POEN0B \ PSC Output 0B Enable
+ $01 constant POC_POEN0A \ PSC Output 0A Enable
+&181 constant PCNF \ PSC Configuration Register
+ $20 constant PCNF_PULOCK \ PSC Update Lock
+ $10 constant PCNF_PMODE \ PSC Mode
+ $08 constant PCNF_POPB \ PSC Output B Polarity
+ $04 constant PCNF_POPA \ PSC Output A Polarity
+&180 constant PSYNC \ PSC Synchro Configuration
+ $30 constant PSYNC_PSYNC2 \ Selection of Synchronization Out for ADC
+ $0C constant PSYNC_PSYNC1 \ Selection of Synchronization Out for ADC
+ $03 constant PSYNC_PSYNC0 \ Selection of Synchronization Out for ADC
+&178 constant POCR_RB \ PSC Output Compare RB Register
+&176 constant POCR2SB \ PSC Module 2 Output Compare SB Register
+&174 constant POCR2RA \ PSC Module 2 Output Compare RA Register
+&172 constant POCR2SA \ PSC Module 2 Output Compare SA Register
+&170 constant POCR1SB \ PSC Module 1 Output Compare SB Register
+&168 constant POCR1RA \ PSC Module 1 Output Compare RA Register
+&166 constant POCR1SA \ PSC Output Compare SA Register
+&164 constant POCR0SB \ PSC Output Compare SB Register
+&162 constant POCR0RA \ PSC Module 0 Output Compare RA Register
+&160 constant POCR0SA \ PSC Module 0 Output Compare SA Register
+
+\ Interrupts
+&2 constant ANACOMP0Addr \ Analog Comparator 0
+&4 constant ANACOMP1Addr \ Analog Comparator 1
+&6 constant ANACOMP2Addr \ Analog Comparator 2
+&8 constant ANACOMP3Addr \ Analog Comparator 3
+&10 constant PSC_FAULTAddr \ PSC Fault
+&12 constant PSC_ECAddr \ PSC End of Cycle
+&14 constant INT0Addr \ External Interrupt Request 0
+&16 constant INT1Addr \ External Interrupt Request 1
+&18 constant INT2Addr \ External Interrupt Request 2
+&20 constant INT3Addr \ External Interrupt Request 3
+&22 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+&24 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
+&26 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
+&28 constant TIMER1_OVFAddr \ Timer1/Counter1 Overflow
+&30 constant TIMER0_COMPAAddr \ Timer/Counter0 Compare Match A
+&32 constant TIMER0_COMPBAddr \ Timer/Counter0 Compare Match B
+&34 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
+&36 constant CAN_INTAddr \ CAN MOB, Burst, General Errors
+&38 constant CAN_TOVFAddr \ CAN Timer Overflow
+&40 constant LIN_TCAddr \ LIN Transfer Complete
+&42 constant LIN_ERRAddr \ LIN Error
+&44 constant PCINT0Addr \ Pin Change Interrupt Request 0
+&46 constant PCINT1Addr \ Pin Change Interrupt Request 1
+&48 constant PCINT2Addr \ Pin Change Interrupt Request 2
+&50 constant PCINT3Addr \ Pin Change Interrupt Request 3
+&52 constant SPI__STCAddr \ SPI Serial Transfer Complete
+&54 constant ADCAddr \ ADC Conversion Complete
+&56 constant WDTAddr \ Watchdog Time-Out Interrupt
+&58 constant EE_READYAddr \ EEPROM Ready
+&60 constant SPM_READYAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/atmega16m1/device.asm b/amforth-6.5/avr8/devices/atmega16m1/device.asm
new file mode 100644
index 0000000..f214c92
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega16m1/device.asm
@@ -0,0 +1,120 @@
+; Partname: ATmega16M1
+; generated automatically, do not edit
+
+.nolist
+ .include "m16M1def.inc"
+.list
+
+.equ ramstart = 256
+.equ CELLSIZE = 2
+.macro readflashcell
+ lsl zl
+ rol zh
+ lpm @0, Z+
+ lpm @1, Z+
+.endmacro
+.macro writeflashcell
+ lsl zl
+ rol zh
+.endmacro
+.set WANT_PORTB = 0
+.set WANT_PORTC = 0
+.set WANT_PORTD = 0
+.set WANT_CAN = 0
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_DA_CONVERTER = 0
+.set WANT_CPU = 0
+.set WANT_PORTE = 0
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_AD_CONVERTER = 0
+.set WANT_LINUART = 0
+.set WANT_SPI = 0
+.set WANT_WATCHDOG = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_EEPROM = 0
+.set WANT_PSC = 0
+.equ intvecsize = 2 ; please verify; flash size: 16384 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.org 2
+ rcall isr ; Analog Comparator 0
+.org 4
+ rcall isr ; Analog Comparator 1
+.org 6
+ rcall isr ; Analog Comparator 2
+.org 8
+ rcall isr ; Analog Comparator 3
+.org 10
+ rcall isr ; PSC Fault
+.org 12
+ rcall isr ; PSC End of Cycle
+.org 14
+ rcall isr ; External Interrupt Request 0
+.org 16
+ rcall isr ; External Interrupt Request 1
+.org 18
+ rcall isr ; External Interrupt Request 2
+.org 20
+ rcall isr ; External Interrupt Request 3
+.org 22
+ rcall isr ; Timer/Counter1 Capture Event
+.org 24
+ rcall isr ; Timer/Counter1 Compare Match A
+.org 26
+ rcall isr ; Timer/Counter1 Compare Match B
+.org 28
+ rcall isr ; Timer1/Counter1 Overflow
+.org 30
+ rcall isr ; Timer/Counter0 Compare Match A
+.org 32
+ rcall isr ; Timer/Counter0 Compare Match B
+.org 34
+ rcall isr ; Timer/Counter0 Overflow
+.org 36
+ rcall isr ; CAN MOB, Burst, General Errors
+.org 38
+ rcall isr ; CAN Timer Overflow
+.org 40
+ rcall isr ; LIN Transfer Complete
+.org 42
+ rcall isr ; LIN Error
+.org 44
+ rcall isr ; Pin Change Interrupt Request 0
+.org 46
+ rcall isr ; Pin Change Interrupt Request 1
+.org 48
+ rcall isr ; Pin Change Interrupt Request 2
+.org 50
+ rcall isr ; Pin Change Interrupt Request 3
+.org 52
+ rcall isr ; SPI Serial Transfer Complete
+.org 54
+ rcall isr ; ADC Conversion Complete
+.org 56
+ rcall isr ; Watchdog Time-Out Interrupt
+.org 58
+ rcall isr ; EEPROM Ready
+.org 60
+ rcall isr ; Store Program Memory Read
+.equ INTVECTORS = 31
+.nooverlap
+
+; compatability layer (maybe empty)
+.equ EEPE = EEWE
+.equ EEMPE = EEMWE
+
+; controller data area, environment query mcu-info
+mcu_info:
+mcu_ramsize:
+ .dw 1024
+mcu_eepromsize:
+ .dw 512
+mcu_maxdp:
+ .dw 12288
+mcu_numints:
+ .dw 31
+mcu_name:
+ .dw 10
+ .db "ATmega16M1"
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega16m1/device.inc b/amforth-6.5/avr8/devices/atmega16m1/device.inc
new file mode 100644
index 0000000..27ba973
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega16m1/device.inc
@@ -0,0 +1,1734 @@
+; Partname: ATmega16M1
+; generated automatically, no not edit
+
+.if WANT_PORTB == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw 37
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw 36
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw 35
+
+.endif
+.if WANT_PORTC == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Register
+VE_PORTC:
+ .dw $ff05
+ .db "PORTC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTC
+XT_PORTC:
+ .dw PFA_DOVARIABLE
+PFA_PORTC:
+ .dw 40
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Direction Register
+VE_DDRC:
+ .dw $ff04
+ .db "DDRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRC
+XT_DDRC:
+ .dw PFA_DOVARIABLE
+PFA_DDRC:
+ .dw 39
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Input Pins
+VE_PINC:
+ .dw $ff04
+ .db "PINC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINC
+XT_PINC:
+ .dw PFA_DOVARIABLE
+PFA_PINC:
+ .dw 38
+
+.endif
+.if WANT_PORTD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw 43
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw 42
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw 41
+
+.endif
+.if WANT_CAN == 1
+; ( -- addr ) System Constant
+; R( -- )
+; CAN General Control Register
+VE_CANGCON:
+ .dw $ff07
+ .db "CANGCON",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANGCON
+XT_CANGCON:
+ .dw PFA_DOVARIABLE
+PFA_CANGCON:
+ .dw 216
+; ( -- addr ) System Constant
+; R( -- )
+; CAN General Status Register
+VE_CANGSTA:
+ .dw $ff07
+ .db "CANGSTA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANGSTA
+XT_CANGSTA:
+ .dw PFA_DOVARIABLE
+PFA_CANGSTA:
+ .dw 217
+; ( -- addr ) System Constant
+; R( -- )
+; CAN General Interrupt Register Flags
+VE_CANGIT:
+ .dw $ff06
+ .db "CANGIT"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANGIT
+XT_CANGIT:
+ .dw PFA_DOVARIABLE
+PFA_CANGIT:
+ .dw 218
+; ( -- addr ) System Constant
+; R( -- )
+; CAN General Interrupt Enable Register
+VE_CANGIE:
+ .dw $ff06
+ .db "CANGIE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANGIE
+XT_CANGIE:
+ .dw PFA_DOVARIABLE
+PFA_CANGIE:
+ .dw 219
+; ( -- addr ) System Constant
+; R( -- )
+; Enable MOb Register 2
+VE_CANEN2:
+ .dw $ff06
+ .db "CANEN2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANEN2
+XT_CANEN2:
+ .dw PFA_DOVARIABLE
+PFA_CANEN2:
+ .dw 220
+; ( -- addr ) System Constant
+; R( -- )
+; Enable MOb Register 1(empty)
+VE_CANEN1:
+ .dw $ff06
+ .db "CANEN1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANEN1
+XT_CANEN1:
+ .dw PFA_DOVARIABLE
+PFA_CANEN1:
+ .dw 221
+; ( -- addr ) System Constant
+; R( -- )
+; Enable Interrupt MOb Register 2
+VE_CANIE2:
+ .dw $ff06
+ .db "CANIE2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANIE2
+XT_CANIE2:
+ .dw PFA_DOVARIABLE
+PFA_CANIE2:
+ .dw 222
+; ( -- addr ) System Constant
+; R( -- )
+; Enable Interrupt MOb Register 1 (empty)
+VE_CANIE1:
+ .dw $ff06
+ .db "CANIE1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANIE1
+XT_CANIE1:
+ .dw PFA_DOVARIABLE
+PFA_CANIE1:
+ .dw 223
+; ( -- addr ) System Constant
+; R( -- )
+; CAN Status Interrupt MOb Register 2
+VE_CANSIT2:
+ .dw $ff07
+ .db "CANSIT2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANSIT2
+XT_CANSIT2:
+ .dw PFA_DOVARIABLE
+PFA_CANSIT2:
+ .dw 224
+; ( -- addr ) System Constant
+; R( -- )
+; CAN Status Interrupt MOb Register 1 (empty)
+VE_CANSIT1:
+ .dw $ff07
+ .db "CANSIT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANSIT1
+XT_CANSIT1:
+ .dw PFA_DOVARIABLE
+PFA_CANSIT1:
+ .dw 225
+; ( -- addr ) System Constant
+; R( -- )
+; CAN Bit Timing Register 1
+VE_CANBT1:
+ .dw $ff06
+ .db "CANBT1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANBT1
+XT_CANBT1:
+ .dw PFA_DOVARIABLE
+PFA_CANBT1:
+ .dw 226
+; ( -- addr ) System Constant
+; R( -- )
+; CAN Bit Timing Register 2
+VE_CANBT2:
+ .dw $ff06
+ .db "CANBT2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANBT2
+XT_CANBT2:
+ .dw PFA_DOVARIABLE
+PFA_CANBT2:
+ .dw 227
+; ( -- addr ) System Constant
+; R( -- )
+; CAN Bit Timing Register 3
+VE_CANBT3:
+ .dw $ff06
+ .db "CANBT3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANBT3
+XT_CANBT3:
+ .dw PFA_DOVARIABLE
+PFA_CANBT3:
+ .dw 228
+; ( -- addr ) System Constant
+; R( -- )
+; Timer Control Register
+VE_CANTCON:
+ .dw $ff07
+ .db "CANTCON",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANTCON
+XT_CANTCON:
+ .dw PFA_DOVARIABLE
+PFA_CANTCON:
+ .dw 229
+; ( -- addr ) System Constant
+; R( -- )
+; Timer Register Low
+VE_CANTIML:
+ .dw $ff07
+ .db "CANTIML",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANTIML
+XT_CANTIML:
+ .dw PFA_DOVARIABLE
+PFA_CANTIML:
+ .dw 230
+; ( -- addr ) System Constant
+; R( -- )
+; Timer Register High
+VE_CANTIMH:
+ .dw $ff07
+ .db "CANTIMH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANTIMH
+XT_CANTIMH:
+ .dw PFA_DOVARIABLE
+PFA_CANTIMH:
+ .dw 231
+; ( -- addr ) System Constant
+; R( -- )
+; TTC Timer Register Low
+VE_CANTTCL:
+ .dw $ff07
+ .db "CANTTCL",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANTTCL
+XT_CANTTCL:
+ .dw PFA_DOVARIABLE
+PFA_CANTTCL:
+ .dw 232
+; ( -- addr ) System Constant
+; R( -- )
+; TTC Timer Register High
+VE_CANTTCH:
+ .dw $ff07
+ .db "CANTTCH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANTTCH
+XT_CANTTCH:
+ .dw PFA_DOVARIABLE
+PFA_CANTTCH:
+ .dw 233
+; ( -- addr ) System Constant
+; R( -- )
+; Transmit Error Counter Register
+VE_CANTEC:
+ .dw $ff06
+ .db "CANTEC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANTEC
+XT_CANTEC:
+ .dw PFA_DOVARIABLE
+PFA_CANTEC:
+ .dw 234
+; ( -- addr ) System Constant
+; R( -- )
+; Receive Error Counter Register
+VE_CANREC:
+ .dw $ff06
+ .db "CANREC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANREC
+XT_CANREC:
+ .dw PFA_DOVARIABLE
+PFA_CANREC:
+ .dw 235
+; ( -- addr ) System Constant
+; R( -- )
+; Highest Priority MOb Register
+VE_CANHPMOB:
+ .dw $ff08
+ .db "CANHPMOB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANHPMOB
+XT_CANHPMOB:
+ .dw PFA_DOVARIABLE
+PFA_CANHPMOB:
+ .dw 236
+; ( -- addr ) System Constant
+; R( -- )
+; Page MOb Register
+VE_CANPAGE:
+ .dw $ff07
+ .db "CANPAGE",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANPAGE
+XT_CANPAGE:
+ .dw PFA_DOVARIABLE
+PFA_CANPAGE:
+ .dw 237
+; ( -- addr ) System Constant
+; R( -- )
+; MOb Status Register
+VE_CANSTMOB:
+ .dw $ff08
+ .db "CANSTMOB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANSTMOB
+XT_CANSTMOB:
+ .dw PFA_DOVARIABLE
+PFA_CANSTMOB:
+ .dw 238
+; ( -- addr ) System Constant
+; R( -- )
+; MOb Control and DLC Register
+VE_CANCDMOB:
+ .dw $ff08
+ .db "CANCDMOB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANCDMOB
+XT_CANCDMOB:
+ .dw PFA_DOVARIABLE
+PFA_CANCDMOB:
+ .dw 239
+; ( -- addr ) System Constant
+; R( -- )
+; Identifier Tag Register 4
+VE_CANIDT4:
+ .dw $ff07
+ .db "CANIDT4",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANIDT4
+XT_CANIDT4:
+ .dw PFA_DOVARIABLE
+PFA_CANIDT4:
+ .dw 240
+; ( -- addr ) System Constant
+; R( -- )
+; Identifier Tag Register 3
+VE_CANIDT3:
+ .dw $ff07
+ .db "CANIDT3",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANIDT3
+XT_CANIDT3:
+ .dw PFA_DOVARIABLE
+PFA_CANIDT3:
+ .dw 241
+; ( -- addr ) System Constant
+; R( -- )
+; Identifier Tag Register 2
+VE_CANIDT2:
+ .dw $ff07
+ .db "CANIDT2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANIDT2
+XT_CANIDT2:
+ .dw PFA_DOVARIABLE
+PFA_CANIDT2:
+ .dw 242
+; ( -- addr ) System Constant
+; R( -- )
+; Identifier Tag Register 1
+VE_CANIDT1:
+ .dw $ff07
+ .db "CANIDT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANIDT1
+XT_CANIDT1:
+ .dw PFA_DOVARIABLE
+PFA_CANIDT1:
+ .dw 243
+; ( -- addr ) System Constant
+; R( -- )
+; Identifier Mask Register 4
+VE_CANIDM4:
+ .dw $ff07
+ .db "CANIDM4",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANIDM4
+XT_CANIDM4:
+ .dw PFA_DOVARIABLE
+PFA_CANIDM4:
+ .dw 244
+; ( -- addr ) System Constant
+; R( -- )
+; Identifier Mask Register 3
+VE_CANIDM3:
+ .dw $ff07
+ .db "CANIDM3",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANIDM3
+XT_CANIDM3:
+ .dw PFA_DOVARIABLE
+PFA_CANIDM3:
+ .dw 245
+; ( -- addr ) System Constant
+; R( -- )
+; Identifier Mask Register 2
+VE_CANIDM2:
+ .dw $ff07
+ .db "CANIDM2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANIDM2
+XT_CANIDM2:
+ .dw PFA_DOVARIABLE
+PFA_CANIDM2:
+ .dw 246
+; ( -- addr ) System Constant
+; R( -- )
+; Identifier Mask Register 1
+VE_CANIDM1:
+ .dw $ff07
+ .db "CANIDM1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANIDM1
+XT_CANIDM1:
+ .dw PFA_DOVARIABLE
+PFA_CANIDM1:
+ .dw 247
+; ( -- addr ) System Constant
+; R( -- )
+; Time Stamp Register Low
+VE_CANSTML:
+ .dw $ff07
+ .db "CANSTML",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANSTML
+XT_CANSTML:
+ .dw PFA_DOVARIABLE
+PFA_CANSTML:
+ .dw 248
+; ( -- addr ) System Constant
+; R( -- )
+; Time Stamp Register High
+VE_CANSTMH:
+ .dw $ff07
+ .db "CANSTMH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANSTMH
+XT_CANSTMH:
+ .dw PFA_DOVARIABLE
+PFA_CANSTMH:
+ .dw 249
+; ( -- addr ) System Constant
+; R( -- )
+; Message Data Register
+VE_CANMSG:
+ .dw $ff06
+ .db "CANMSG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANMSG
+XT_CANMSG:
+ .dw PFA_DOVARIABLE
+PFA_CANMSG:
+ .dw 250
+
+.endif
+.if WANT_ANALOG_COMPARATOR == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator 0 Control Register
+VE_AC0CON:
+ .dw $ff06
+ .db "AC0CON"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_AC0CON
+XT_AC0CON:
+ .dw PFA_DOVARIABLE
+PFA_AC0CON:
+ .dw 148
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator 1 Control Register
+VE_AC1CON:
+ .dw $ff06
+ .db "AC1CON"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_AC1CON
+XT_AC1CON:
+ .dw PFA_DOVARIABLE
+PFA_AC1CON:
+ .dw 149
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator 2 Control Register
+VE_AC2CON:
+ .dw $ff06
+ .db "AC2CON"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_AC2CON
+XT_AC2CON:
+ .dw PFA_DOVARIABLE
+PFA_AC2CON:
+ .dw 150
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator 3 Control Register
+VE_AC3CON:
+ .dw $ff06
+ .db "AC3CON"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_AC3CON
+XT_AC3CON:
+ .dw PFA_DOVARIABLE
+PFA_AC3CON:
+ .dw 151
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw 80
+
+.endif
+.if WANT_DA_CONVERTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; DAC Data Register High Byte
+VE_DACH:
+ .dw $ff04
+ .db "DACH"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DACH
+XT_DACH:
+ .dw PFA_DOVARIABLE
+PFA_DACH:
+ .dw 146
+; ( -- addr ) System Constant
+; R( -- )
+; DAC Data Register Low Byte
+VE_DACL:
+ .dw $ff04
+ .db "DACL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DACL
+XT_DACL:
+ .dw PFA_DOVARIABLE
+PFA_DACL:
+ .dw 145
+; ( -- addr ) System Constant
+; R( -- )
+; DAC Control Register
+VE_DACON:
+ .dw $ff05
+ .db "DACON",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DACON
+XT_DACON:
+ .dw PFA_DOVARIABLE
+PFA_DACON:
+ .dw 144
+
+.endif
+.if WANT_CPU == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control Register
+VE_SPMCSR:
+ .dw $ff06
+ .db "SPMCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCSR
+XT_SPMCSR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCSR:
+ .dw 87
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw 95
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer
+VE_SP:
+ .dw $ff02
+ .db "SP"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SP
+XT_SP:
+ .dw PFA_DOVARIABLE
+PFA_SP:
+ .dw 93
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw 85
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Status Register
+VE_MCUSR:
+ .dw $ff05
+ .db "MCUSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUSR
+XT_MCUSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUSR:
+ .dw 84
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Calibration Value
+VE_OSCCAL:
+ .dw $ff06
+ .db "OSCCAL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSCCAL
+XT_OSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_OSCCAL:
+ .dw 102
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_CLKPR:
+ .dw $ff05
+ .db "CLKPR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKPR
+XT_CLKPR:
+ .dw PFA_DOVARIABLE
+PFA_CLKPR:
+ .dw 97
+; ( -- addr ) System Constant
+; R( -- )
+; Sleep Mode Control Register
+VE_SMCR:
+ .dw $ff04
+ .db "SMCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SMCR
+XT_SMCR:
+ .dw PFA_DOVARIABLE
+PFA_SMCR:
+ .dw 83
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 2
+VE_GPIOR2:
+ .dw $ff06
+ .db "GPIOR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR2
+XT_GPIOR2:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR2:
+ .dw 58
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 1
+VE_GPIOR1:
+ .dw $ff06
+ .db "GPIOR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR1
+XT_GPIOR1:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR1:
+ .dw 57
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 0
+VE_GPIOR0:
+ .dw $ff06
+ .db "GPIOR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR0
+XT_GPIOR0:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR0:
+ .dw 62
+; ( -- addr ) System Constant
+; R( -- )
+; PLL Control And Status Register
+VE_PLLCSR:
+ .dw $ff06
+ .db "PLLCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PLLCSR
+XT_PLLCSR:
+ .dw PFA_DOVARIABLE
+PFA_PLLCSR:
+ .dw 73
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register
+VE_PRR:
+ .dw $ff03
+ .db "PRR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR
+XT_PRR:
+ .dw PFA_DOVARIABLE
+PFA_PRR:
+ .dw 100
+
+.endif
+.if WANT_PORTE == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port E Data Register
+VE_PORTE:
+ .dw $ff05
+ .db "PORTE",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTE
+XT_PORTE:
+ .dw PFA_DOVARIABLE
+PFA_PORTE:
+ .dw 46
+; ( -- addr ) System Constant
+; R( -- )
+; Port E Data Direction Register
+VE_DDRE:
+ .dw $ff04
+ .db "DDRE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRE
+XT_DDRE:
+ .dw PFA_DOVARIABLE
+PFA_DDRE:
+ .dw 45
+; ( -- addr ) System Constant
+; R( -- )
+; Port E Input Pins
+VE_PINE:
+ .dw $ff04
+ .db "PINE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINE
+XT_PINE:
+ .dw PFA_DOVARIABLE
+PFA_PINE:
+ .dw 44
+
+.endif
+.if WANT_TIMER_COUNTER_0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Mask Register
+VE_TIMSK0:
+ .dw $ff06
+ .db "TIMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK0
+XT_TIMSK0:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK0:
+ .dw 110
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Flag register
+VE_TIFR0:
+ .dw $ff05
+ .db "TIFR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR0
+XT_TIFR0:
+ .dw PFA_DOVARIABLE
+PFA_TIFR0:
+ .dw 53
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register A
+VE_TCCR0A:
+ .dw $ff06
+ .db "TCCR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0A
+XT_TCCR0A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0A:
+ .dw 68
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register B
+VE_TCCR0B:
+ .dw $ff06
+ .db "TCCR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0B
+XT_TCCR0B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0B:
+ .dw 69
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw 70
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0A:
+ .dw $ff05
+ .db "OCR0A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0A
+XT_OCR0A:
+ .dw PFA_DOVARIABLE
+PFA_OCR0A:
+ .dw 71
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0B:
+ .dw $ff05
+ .db "OCR0B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0B
+XT_OCR0B:
+ .dw PFA_DOVARIABLE
+PFA_OCR0B:
+ .dw 72
+; ( -- addr ) System Constant
+; R( -- )
+; General Timer/Counter Control Register
+VE_GTCCR:
+ .dw $ff05
+ .db "GTCCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GTCCR
+XT_GTCCR:
+ .dw PFA_DOVARIABLE
+PFA_GTCCR:
+ .dw 67
+
+.endif
+.if WANT_TIMER_COUNTER_1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Mask Register
+VE_TIMSK1:
+ .dw $ff06
+ .db "TIMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK1
+XT_TIMSK1:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK1:
+ .dw 111
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Flag register
+VE_TIFR1:
+ .dw $ff05
+ .db "TIFR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR1
+XT_TIFR1:
+ .dw PFA_DOVARIABLE
+PFA_TIFR1:
+ .dw 54
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw 128
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw 129
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register C
+VE_TCCR1C:
+ .dw $ff06
+ .db "TCCR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1C
+XT_TCCR1C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1C:
+ .dw 130
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Bytes
+VE_TCNT1:
+ .dw $ff05
+ .db "TCNT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1
+XT_TCNT1:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1:
+ .dw 132
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register Bytes
+VE_OCR1A:
+ .dw $ff05
+ .db "OCR1A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1A
+XT_OCR1A:
+ .dw PFA_DOVARIABLE
+PFA_OCR1A:
+ .dw 136
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register Bytes
+VE_OCR1B:
+ .dw $ff05
+ .db "OCR1B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1B
+XT_OCR1B:
+ .dw PFA_DOVARIABLE
+PFA_OCR1B:
+ .dw 138
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Bytes
+VE_ICR1:
+ .dw $ff04
+ .db "ICR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1
+XT_ICR1:
+ .dw PFA_DOVARIABLE
+PFA_ICR1:
+ .dw 134
+
+.endif
+.if WANT_AD_CONVERTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC multiplexer Selection Register
+VE_ADMUX:
+ .dw $ff05
+ .db "ADMUX",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADMUX
+XT_ADMUX:
+ .dw PFA_DOVARIABLE
+PFA_ADMUX:
+ .dw 124
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register
+VE_ADCSRA:
+ .dw $ff06
+ .db "ADCSRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRA
+XT_ADCSRA:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRA:
+ .dw 122
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register Bytes
+VE_ADC:
+ .dw $ff03
+ .db "ADC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADC
+XT_ADC:
+ .dw PFA_DOVARIABLE
+PFA_ADC:
+ .dw 120
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Control and Status Register B
+VE_ADCSRB:
+ .dw $ff06
+ .db "ADCSRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRB
+XT_ADCSRB:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRB:
+ .dw 123
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 0
+VE_DIDR0:
+ .dw $ff05
+ .db "DIDR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR0
+XT_DIDR0:
+ .dw PFA_DOVARIABLE
+PFA_DIDR0:
+ .dw 126
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 0
+VE_DIDR1:
+ .dw $ff05
+ .db "DIDR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR1
+XT_DIDR1:
+ .dw PFA_DOVARIABLE
+PFA_DIDR1:
+ .dw 127
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_AMP0CSR:
+ .dw $ff07
+ .db "AMP0CSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_AMP0CSR
+XT_AMP0CSR:
+ .dw PFA_DOVARIABLE
+PFA_AMP0CSR:
+ .dw 117
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_AMP1CSR:
+ .dw $ff07
+ .db "AMP1CSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_AMP1CSR
+XT_AMP1CSR:
+ .dw PFA_DOVARIABLE
+PFA_AMP1CSR:
+ .dw 118
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_AMP2CSR:
+ .dw $ff07
+ .db "AMP2CSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_AMP2CSR
+XT_AMP2CSR:
+ .dw PFA_DOVARIABLE
+PFA_AMP2CSR:
+ .dw 119
+
+.endif
+.if WANT_LINUART == 1
+; ( -- addr ) System Constant
+; R( -- )
+; LIN Control Register
+VE_LINCR:
+ .dw $ff05
+ .db "LINCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LINCR
+XT_LINCR:
+ .dw PFA_DOVARIABLE
+PFA_LINCR:
+ .dw 200
+; ( -- addr ) System Constant
+; R( -- )
+; LIN Status and Interrupt Register
+VE_LINSIR:
+ .dw $ff06
+ .db "LINSIR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LINSIR
+XT_LINSIR:
+ .dw PFA_DOVARIABLE
+PFA_LINSIR:
+ .dw 201
+; ( -- addr ) System Constant
+; R( -- )
+; LIN Enable Interrupt Register
+VE_LINENIR:
+ .dw $ff07
+ .db "LINENIR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LINENIR
+XT_LINENIR:
+ .dw PFA_DOVARIABLE
+PFA_LINENIR:
+ .dw 202
+; ( -- addr ) System Constant
+; R( -- )
+; LIN Error Register
+VE_LINERR:
+ .dw $ff06
+ .db "LINERR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LINERR
+XT_LINERR:
+ .dw PFA_DOVARIABLE
+PFA_LINERR:
+ .dw 203
+; ( -- addr ) System Constant
+; R( -- )
+; LIN Bit Timing Register
+VE_LINBTR:
+ .dw $ff06
+ .db "LINBTR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LINBTR
+XT_LINBTR:
+ .dw PFA_DOVARIABLE
+PFA_LINBTR:
+ .dw 204
+; ( -- addr ) System Constant
+; R( -- )
+; LIN Baud Rate Low Register
+VE_LINBRRL:
+ .dw $ff07
+ .db "LINBRRL",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LINBRRL
+XT_LINBRRL:
+ .dw PFA_DOVARIABLE
+PFA_LINBRRL:
+ .dw 205
+; ( -- addr ) System Constant
+; R( -- )
+; LIN Baud Rate High Register
+VE_LINBRRH:
+ .dw $ff07
+ .db "LINBRRH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LINBRRH
+XT_LINBRRH:
+ .dw PFA_DOVARIABLE
+PFA_LINBRRH:
+ .dw 206
+; ( -- addr ) System Constant
+; R( -- )
+; LIN Data Length Register
+VE_LINDLR:
+ .dw $ff06
+ .db "LINDLR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LINDLR
+XT_LINDLR:
+ .dw PFA_DOVARIABLE
+PFA_LINDLR:
+ .dw 207
+; ( -- addr ) System Constant
+; R( -- )
+; LIN Identifier Register
+VE_LINIDR:
+ .dw $ff06
+ .db "LINIDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LINIDR
+XT_LINIDR:
+ .dw PFA_DOVARIABLE
+PFA_LINIDR:
+ .dw 208
+; ( -- addr ) System Constant
+; R( -- )
+; LIN Data Buffer Selection Register
+VE_LINSEL:
+ .dw $ff06
+ .db "LINSEL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LINSEL
+XT_LINSEL:
+ .dw PFA_DOVARIABLE
+PFA_LINSEL:
+ .dw 209
+; ( -- addr ) System Constant
+; R( -- )
+; LIN Data Register
+VE_LINDAT:
+ .dw $ff06
+ .db "LINDAT"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LINDAT
+XT_LINDAT:
+ .dw PFA_DOVARIABLE
+PFA_LINDAT:
+ .dw 210
+
+.endif
+.if WANT_SPI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR:
+ .dw $ff04
+ .db "SPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR
+XT_SPCR:
+ .dw PFA_DOVARIABLE
+PFA_SPCR:
+ .dw 76
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR:
+ .dw $ff04
+ .db "SPSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR
+XT_SPSR:
+ .dw PFA_DOVARIABLE
+PFA_SPSR:
+ .dw 77
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR:
+ .dw $ff04
+ .db "SPDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR
+XT_SPDR:
+ .dw PFA_DOVARIABLE
+PFA_SPDR:
+ .dw 78
+
+.endif
+.if WANT_WATCHDOG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCSR:
+ .dw $ff06
+ .db "WDTCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCSR
+XT_WDTCSR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCSR:
+ .dw 96
+
+.endif
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register
+VE_EICRA:
+ .dw $ff05
+ .db "EICRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRA
+XT_EICRA:
+ .dw PFA_DOVARIABLE
+PFA_EICRA:
+ .dw 105
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Mask Register
+VE_EIMSK:
+ .dw $ff05
+ .db "EIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIMSK
+XT_EIMSK:
+ .dw PFA_DOVARIABLE
+PFA_EIMSK:
+ .dw 61
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Flag Register
+VE_EIFR:
+ .dw $ff04
+ .db "EIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIFR
+XT_EIFR:
+ .dw PFA_DOVARIABLE
+PFA_EIFR:
+ .dw 60
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Interrupt Control Register
+VE_PCICR:
+ .dw $ff05
+ .db "PCICR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCICR
+XT_PCICR:
+ .dw PFA_DOVARIABLE
+PFA_PCICR:
+ .dw 104
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 3
+VE_PCMSK3:
+ .dw $ff06
+ .db "PCMSK3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK3
+XT_PCMSK3:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK3:
+ .dw 109
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 2
+VE_PCMSK2:
+ .dw $ff06
+ .db "PCMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK2
+XT_PCMSK2:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK2:
+ .dw 108
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 1
+VE_PCMSK1:
+ .dw $ff06
+ .db "PCMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK1
+XT_PCMSK1:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK1:
+ .dw 107
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 0
+VE_PCMSK0:
+ .dw $ff06
+ .db "PCMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK0
+XT_PCMSK0:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK0:
+ .dw 106
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Interrupt Flag Register
+VE_PCIFR:
+ .dw $ff05
+ .db "PCIFR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCIFR
+XT_PCIFR:
+ .dw PFA_DOVARIABLE
+PFA_PCIFR:
+ .dw 59
+
+.endif
+.if WANT_EEPROM == 1
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Read/Write Access
+VE_EEAR:
+ .dw $ff04
+ .db "EEAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEAR
+XT_EEAR:
+ .dw PFA_DOVARIABLE
+PFA_EEAR:
+ .dw 65
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw 64
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw 63
+
+.endif
+.if WANT_PSC == 1
+; ( -- addr ) System Constant
+; R( -- )
+; PSC Interrupt Flag Register
+VE_PIFR:
+ .dw $ff04
+ .db "PIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIFR
+XT_PIFR:
+ .dw PFA_DOVARIABLE
+PFA_PIFR:
+ .dw 188
+; ( -- addr ) System Constant
+; R( -- )
+; PSC Interrupt Mask Register
+VE_PIM:
+ .dw $ff03
+ .db "PIM",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIM
+XT_PIM:
+ .dw PFA_DOVARIABLE
+PFA_PIM:
+ .dw 187
+; ( -- addr ) System Constant
+; R( -- )
+; PSC Module 2 Input Control Register
+VE_PMIC2:
+ .dw $ff05
+ .db "PMIC2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PMIC2
+XT_PMIC2:
+ .dw PFA_DOVARIABLE
+PFA_PMIC2:
+ .dw 186
+; ( -- addr ) System Constant
+; R( -- )
+; PSC Module 1 Input Control Register
+VE_PMIC1:
+ .dw $ff05
+ .db "PMIC1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PMIC1
+XT_PMIC1:
+ .dw PFA_DOVARIABLE
+PFA_PMIC1:
+ .dw 185
+; ( -- addr ) System Constant
+; R( -- )
+; PSC Module 0 Input Control Register
+VE_PMIC0:
+ .dw $ff05
+ .db "PMIC0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PMIC0
+XT_PMIC0:
+ .dw PFA_DOVARIABLE
+PFA_PMIC0:
+ .dw 184
+; ( -- addr ) System Constant
+; R( -- )
+; PSC Control Register
+VE_PCTL:
+ .dw $ff04
+ .db "PCTL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCTL
+XT_PCTL:
+ .dw PFA_DOVARIABLE
+PFA_PCTL:
+ .dw 183
+; ( -- addr ) System Constant
+; R( -- )
+; PSC Output Configuration
+VE_POC:
+ .dw $ff03
+ .db "POC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_POC
+XT_POC:
+ .dw PFA_DOVARIABLE
+PFA_POC:
+ .dw 182
+; ( -- addr ) System Constant
+; R( -- )
+; PSC Configuration Register
+VE_PCNF:
+ .dw $ff04
+ .db "PCNF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCNF
+XT_PCNF:
+ .dw PFA_DOVARIABLE
+PFA_PCNF:
+ .dw 181
+; ( -- addr ) System Constant
+; R( -- )
+; PSC Synchro Configuration
+VE_PSYNC:
+ .dw $ff05
+ .db "PSYNC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PSYNC
+XT_PSYNC:
+ .dw PFA_DOVARIABLE
+PFA_PSYNC:
+ .dw 180
+; ( -- addr ) System Constant
+; R( -- )
+; PSC Output Compare RB Register
+VE_POCR_RB:
+ .dw $ff07
+ .db "POCR_RB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_POCR_RB
+XT_POCR_RB:
+ .dw PFA_DOVARIABLE
+PFA_POCR_RB:
+ .dw 178
+; ( -- addr ) System Constant
+; R( -- )
+; PSC Module 2 Output Compare SB Register
+VE_POCR2SB:
+ .dw $ff07
+ .db "POCR2SB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_POCR2SB
+XT_POCR2SB:
+ .dw PFA_DOVARIABLE
+PFA_POCR2SB:
+ .dw 176
+; ( -- addr ) System Constant
+; R( -- )
+; PSC Module 2 Output Compare RA Register
+VE_POCR2RA:
+ .dw $ff07
+ .db "POCR2RA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_POCR2RA
+XT_POCR2RA:
+ .dw PFA_DOVARIABLE
+PFA_POCR2RA:
+ .dw 174
+; ( -- addr ) System Constant
+; R( -- )
+; PSC Module 2 Output Compare SA Register
+VE_POCR2SA:
+ .dw $ff07
+ .db "POCR2SA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_POCR2SA
+XT_POCR2SA:
+ .dw PFA_DOVARIABLE
+PFA_POCR2SA:
+ .dw 172
+; ( -- addr ) System Constant
+; R( -- )
+; PSC Module 1 Output Compare SB Register
+VE_POCR1SB:
+ .dw $ff07
+ .db "POCR1SB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_POCR1SB
+XT_POCR1SB:
+ .dw PFA_DOVARIABLE
+PFA_POCR1SB:
+ .dw 170
+; ( -- addr ) System Constant
+; R( -- )
+; PSC Module 1 Output Compare RA Register
+VE_POCR1RA:
+ .dw $ff07
+ .db "POCR1RA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_POCR1RA
+XT_POCR1RA:
+ .dw PFA_DOVARIABLE
+PFA_POCR1RA:
+ .dw 168
+; ( -- addr ) System Constant
+; R( -- )
+; PSC Output Compare SA Register
+VE_POCR1SA:
+ .dw $ff07
+ .db "POCR1SA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_POCR1SA
+XT_POCR1SA:
+ .dw PFA_DOVARIABLE
+PFA_POCR1SA:
+ .dw 166
+; ( -- addr ) System Constant
+; R( -- )
+; PSC Output Compare SB Register
+VE_POCR0SB:
+ .dw $ff07
+ .db "POCR0SB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_POCR0SB
+XT_POCR0SB:
+ .dw PFA_DOVARIABLE
+PFA_POCR0SB:
+ .dw 164
+; ( -- addr ) System Constant
+; R( -- )
+; PSC Module 0 Output Compare RA Register
+VE_POCR0RA:
+ .dw $ff07
+ .db "POCR0RA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_POCR0RA
+XT_POCR0RA:
+ .dw PFA_DOVARIABLE
+PFA_POCR0RA:
+ .dw 162
+; ( -- addr ) System Constant
+; R( -- )
+; PSC Module 0 Output Compare SA Register
+VE_POCR0SA:
+ .dw $ff07
+ .db "POCR0SA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_POCR0SA
+XT_POCR0SA:
+ .dw PFA_DOVARIABLE
+PFA_POCR0SA:
+ .dw 160
+
+.endif
diff --git a/amforth-6.5/avr8/devices/atmega16m1/device.py b/amforth-6.5/avr8/devices/atmega16m1/device.py
new file mode 100644
index 0000000..a25c529
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega16m1/device.py
@@ -0,0 +1,537 @@
+# Generated Automatically
+
+# Partname ATmega16M1
+
+MCUREGS = {
+# Interrupt Vectors
+ 'ANACOMP0Addr' : '#2', # Analog Comparator 0
+ 'ANACOMP1Addr' : '#4', # Analog Comparator 1
+ 'ANACOMP2Addr' : '#6', # Analog Comparator 2
+ 'ANACOMP3Addr' : '#8', # Analog Comparator 3
+ 'PSC_FAULTAddr' : '#10', # PSC Fault
+ 'PSC_ECAddr' : '#12', # PSC End of Cycle
+ 'INT0Addr' : '#14', # External Interrupt Request 0
+ 'INT1Addr' : '#16', # External Interrupt Request 1
+ 'INT2Addr' : '#18', # External Interrupt Request 2
+ 'INT3Addr' : '#20', # External Interrupt Request 3
+ 'TIMER1_CAPTAddr' : '#22', # Timer/Counter1 Capture Event
+ 'TIMER1_COMPAAddr' : '#24', # Timer/Counter1 Compare Match A
+ 'TIMER1_COMPBAddr' : '#26', # Timer/Counter1 Compare Match B
+ 'TIMER1_OVFAddr' : '#28', # Timer1/Counter1 Overflow
+ 'TIMER0_COMPAAddr' : '#30', # Timer/Counter0 Compare Match A
+ 'TIMER0_COMPBAddr' : '#32', # Timer/Counter0 Compare Match B
+ 'TIMER0_OVFAddr' : '#34', # Timer/Counter0 Overflow
+ 'CAN_INTAddr' : '#36', # CAN MOB, Burst, General Errors
+ 'CAN_TOVFAddr' : '#38', # CAN Timer Overflow
+ 'LIN_TCAddr' : '#40', # LIN Transfer Complete
+ 'LIN_ERRAddr' : '#42', # LIN Error
+ 'PCINT0Addr' : '#44', # Pin Change Interrupt Request 0
+ 'PCINT1Addr' : '#46', # Pin Change Interrupt Request 1
+ 'PCINT2Addr' : '#48', # Pin Change Interrupt Request 2
+ 'PCINT3Addr' : '#50', # Pin Change Interrupt Request 3
+ 'SPI_STCAddr' : '#52', # SPI Serial Transfer Complete
+ 'ADCAddr' : '#54', # ADC Conversion Complete
+ 'WDTAddr' : '#56', # Watchdog Time-Out Interrupt
+ 'EE_READYAddr' : '#58', # EEPROM Ready
+ 'SPM_READYAddr' : '#60', # Store Program Memory Read
+
+# Module PORTB
+ 'PORTB' : '$25', # Port B Data Register
+ 'DDRB' : '$24', # Port B Data Direction Register
+ 'PINB' : '$23', # Port B Input Pins
+
+# Module PORTC
+ 'PORTC' : '$28', # Port C Data Register
+ 'DDRC' : '$27', # Port C Data Direction Register
+ 'PINC' : '$26', # Port C Input Pins
+
+# Module PORTD
+ 'PORTD' : '$2b', # Port D Data Register
+ 'DDRD' : '$2a', # Port D Data Direction Register
+ 'PIND' : '$29', # Port D Input Pins
+
+# Module CAN
+ 'CANGCON' : '$d8', # CAN General Control Register
+ 'CANGCON_ABRQ': '$80', # Abort Request
+ 'CANGCON_OVRQ': '$40', # Overload Frame Request
+ 'CANGCON_TTC': '$20', # Time Trigger Communication
+ 'CANGCON_SYNTTC': '$10', # Synchronization of TTC
+ 'CANGCON_LISTEN': '$8', # Listening Mode
+ 'CANGCON_TEST': '$4', # Test Mode
+ 'CANGCON_ENASTB': '$2', # Enable / Standby
+ 'CANGCON_SWRES': '$1', # Software Reset Request
+ 'CANGSTA' : '$d9', # CAN General Status Register
+ 'CANGSTA_OVFG': '$40', # Overload Frame Flag
+ 'CANGSTA_TXBSY': '$10', # Transmitter Busy
+ 'CANGSTA_RXBSY': '$8', # Receiver Busy
+ 'CANGSTA_ENFG': '$4', # Enable Flag
+ 'CANGSTA_BOFF': '$2', # Bus Off Mode
+ 'CANGSTA_ERRP': '$1', # Error Passive Mode
+ 'CANGIT' : '$da', # CAN General Interrupt Register
+ 'CANGIT_CANIT': '$80', # General Interrupt Flag
+ 'CANGIT_BOFFIT': '$40', # Bus Off Interrupt Flag
+ 'CANGIT_OVRTIM': '$20', # Overrun CAN Timer Flag
+ 'CANGIT_BXOK': '$10', # Burst Receive Interrupt Flag
+ 'CANGIT_SERG': '$8', # Stuff Error General Flag
+ 'CANGIT_CERG': '$4', # CRC Error General Flag
+ 'CANGIT_FERG': '$2', # Form Error General Flag
+ 'CANGIT_AERG': '$1', # Ackknowledgement Error General
+ 'CANGIE' : '$db', # CAN General Interrupt Enable R
+ 'CANGIE_ENIT': '$80', # Enable all Interrupts
+ 'CANGIE_ENBOFF': '$40', # Enable Bus Off Interrupt
+ 'CANGIE_ENRX': '$20', # Enable Receive Interrupt
+ 'CANGIE_ENTX': '$10', # Enable Transmitt Interrupt
+ 'CANGIE_ENERR': '$8', # Enable MOb Error Interrupt
+ 'CANGIE_ENBX': '$4', # Enable Burst Receive Interrupt
+ 'CANGIE_ENERG': '$2', # Enable General Error Interrupt
+ 'CANGIE_ENOVRT': '$1', # Enable CAN Timer Overrun Inter
+ 'CANEN2' : '$dc', # Enable MOb Register 2
+ 'CANEN2_ENMOB': '$3f', # Enable MObs
+ 'CANEN1' : '$dd', # Enable MOb Register 1(empty)
+ 'CANIE2' : '$de', # Enable Interrupt MOb Register
+ 'CANIE2_IEMOB': '$3f', # Interrupt Enable MObs
+ 'CANIE1' : '$df', # Enable Interrupt MOb Register
+ 'CANSIT2' : '$e0', # CAN Status Interrupt MOb Regis
+ 'CANSIT2_SIT': '$3f', # Status of Interrupt MObs
+ 'CANSIT1' : '$e1', # CAN Status Interrupt MOb Regis
+ 'CANBT1' : '$e2', # CAN Bit Timing Register 1
+ 'CANBT1_BRP': '$7e', # Baud Rate Prescaler bits
+ 'CANBT2' : '$e3', # CAN Bit Timing Register 2
+ 'CANBT2_SJW': '$60', # Re-Sync Jump Width bits
+ 'CANBT2_PRS': '$e', # Propagation Time Segment bits
+ 'CANBT3' : '$e4', # CAN Bit Timing Register 3
+ 'CANBT3_PHS2': '$70', # Phase Segment 2 bits
+ 'CANBT3_PHS1': '$e', # Phase Segment 1 bits
+ 'CANBT3_SMP': '$1', # Sample Type
+ 'CANTCON' : '$e5', # Timer Control Register
+ 'CANTIML' : '$e6', # Timer Register Low
+ 'CANTIMH' : '$e7', # Timer Register High
+ 'CANTTCL' : '$e8', # TTC Timer Register Low
+ 'CANTTCH' : '$e9', # TTC Timer Register High
+ 'CANTEC' : '$ea', # Transmit Error Counter Registe
+ 'CANREC' : '$eb', # Receive Error Counter Register
+ 'CANHPMOB' : '$ec', # Highest Priority MOb Register
+ 'CANHPMOB_HPMOB': '$f0', # Highest Priority MOb Number bi
+ 'CANHPMOB_CGP': '$f', # CAN General Purpose bits
+ 'CANPAGE' : '$ed', # Page MOb Register
+ 'CANPAGE_MOBNB': '$f0', # MOb Number bits
+ 'CANPAGE_AINC': '$8', # MOb Data Buffer Auto Increment
+ 'CANPAGE_INDX': '$7', # Data Buffer Index bits
+ 'CANSTMOB' : '$ee', # MOb Status Register
+ 'CANSTMOB_DLCW': '$80', # Data Length Code Warning on MO
+ 'CANSTMOB_TXOK': '$40', # Transmit OK on MOb
+ 'CANSTMOB_RXOK': '$20', # Receive OK on MOb
+ 'CANSTMOB_BERR': '$10', # Bit Error on MOb
+ 'CANSTMOB_SERR': '$8', # Stuff Error on MOb
+ 'CANSTMOB_CERR': '$4', # CRC Error on MOb
+ 'CANSTMOB_FERR': '$2', # Form Error on MOb
+ 'CANSTMOB_AERR': '$1', # Ackknowledgement Error on MOb
+ 'CANCDMOB' : '$ef', # MOb Control and DLC Register
+ 'CANCDMOB_CONMOB': '$c0', # MOb Config bits
+ 'CANCDMOB_RPLV': '$20', # Reply Valid
+ 'CANCDMOB_IDE': '$10', # Identifier Extension
+ 'CANCDMOB_DLC': '$f', # Data Length Code bits
+ 'CANIDT4' : '$f0', # Identifier Tag Register 4
+ 'CANIDT4_IDT': '$f8', #
+ 'CANIDT4_RTRTAG': '$4', #
+ 'CANIDT4_RB1TAG': '$2', #
+ 'CANIDT4_RB0TAG': '$1', #
+ 'CANIDT3' : '$f1', # Identifier Tag Register 3
+ 'CANIDT2' : '$f2', # Identifier Tag Register 2
+ 'CANIDT1' : '$f3', # Identifier Tag Register 1
+ 'CANIDM4' : '$f4', # Identifier Mask Register 4
+ 'CANIDM3' : '$f5', # Identifier Mask Register 3
+ 'CANIDM2' : '$f6', # Identifier Mask Register 2
+ 'CANIDM1' : '$f7', # Identifier Mask Register 1
+ 'CANSTML' : '$f8', # Time Stamp Register Low
+ 'CANSTMH' : '$f9', # Time Stamp Register High
+ 'CANMSG' : '$fa', # Message Data Register
+
+# Module ANALOG_COMPARATOR
+ 'AC0CON' : '$94', # Analog Comparator 0 Control Re
+ 'AC0CON_AC0EN': '$80', # Analog Comparator 0 Enable Bit
+ 'AC0CON_AC0IE': '$40', # Analog Comparator 0 Interrupt
+ 'AC0CON_AC0IS': '$30', # Analog Comparator 0 Interrupt
+ 'AC0CON_ACCKSEL': '$8', # Analog Comparator Clock Select
+ 'AC0CON_AC0M': '$7', # Analog Comparator 0 Multiplexe
+ 'AC1CON' : '$95', # Analog Comparator 1 Control Re
+ 'AC1CON_AC1EN': '$80', # Analog Comparator 1 Enable Bit
+ 'AC1CON_AC1IE': '$40', # Analog Comparator 1 Interrupt
+ 'AC1CON_AC1IS': '$30', # Analog Comparator 1 Interrupt
+ 'AC1CON_AC1ICE': '$8', # Analog Comparator 1 Interrupt
+ 'AC1CON_AC1M': '$7', # Analog Comparator 1 Multiplexe
+ 'AC2CON' : '$96', # Analog Comparator 2 Control Re
+ 'AC2CON_AC2EN': '$80', # Analog Comparator 2 Enable Bit
+ 'AC2CON_AC2IE': '$40', # Analog Comparator 2 Interrupt
+ 'AC2CON_AC2IS': '$30', # Analog Comparator 2 Interrupt
+ 'AC2CON_AC2M': '$7', # Analog Comparator 2 Multiplexe
+ 'AC3CON' : '$97', # Analog Comparator 3 Control Re
+ 'AC3CON_AC3EN': '$80', # Analog Comparator 3 Enable Bit
+ 'AC3CON_AC3IE': '$40', # Analog Comparator 3 Interrupt
+ 'AC3CON_AC3IS': '$30', # Analog Comparator 3 Interrupt
+ 'AC3CON_AC3M': '$7', # Analog Comparator 3 Multiplexe
+ 'ACSR' : '$50', # Analog Comparator Status Regis
+ 'ACSR_AC3IF': '$80', # Analog Comparator 3 Interrupt
+ 'ACSR_AC2IF': '$40', # Analog Comparator 2 Interrupt
+ 'ACSR_AC1IF': '$20', # Analog Comparator 1 Interrupt
+ 'ACSR_AC0IF': '$10', # Analog Comparator 0 Interrupt
+ 'ACSR_AC3O': '$8', # Analog Comparator 3 Output Bit
+ 'ACSR_AC2O': '$4', # Analog Comparator 2 Output Bit
+ 'ACSR_AC1O': '$2', # Analog Comparator 1 Output Bit
+ 'ACSR_AC0O': '$1', # Analog Comparator 0 Output Bit
+
+# Module DA_CONVERTER
+ 'DACH' : '$92', # DAC Data Register High Byte
+ 'DACH_DACH': '$ff', # DAC Data Register High Byte Bi
+ 'DACL' : '$91', # DAC Data Register Low Byte
+ 'DACL_DACL': '$ff', # DAC Data Register Low Byte Bit
+ 'DACON' : '$90', # DAC Control Register
+ 'DACON_DAATE': '$80', # DAC Auto Trigger Enable Bit
+ 'DACON_DATS': '$70', # DAC Trigger Selection Bits
+ 'DACON_DALA': '$4', # DAC Left Adjust
+ 'DACON_DAEN': '$1', # DAC Enable Bit
+
+# Module CPU
+ 'SPMCSR' : '$57', # Store Program Memory Control R
+ 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
+ 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
+ 'SPMCSR_SIGRD': '$20', # Signature Row Read
+ 'SPMCSR_RWWSRE': '$10', # Read While Write section read
+ 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
+ 'SPMCSR_PGWRT': '$4', # Page Write
+ 'SPMCSR_PGERS': '$2', # Page Erase
+ 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
+ 'SREG' : '$5f', # Status Register
+ 'SREG_I': '$80', # Global Interrupt Enable
+ 'SREG_T': '$40', # Bit Copy Storage
+ 'SREG_H': '$20', # Half Carry Flag
+ 'SREG_S': '$10', # Sign Bit
+ 'SREG_V': '$8', # Two's Complement Overflow Flag
+ 'SREG_N': '$4', # Negative Flag
+ 'SREG_Z': '$2', # Zero Flag
+ 'SREG_C': '$1', # Carry Flag
+ 'SP' : '$5d', # Stack Pointer
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_SPIPS': '$80', # SPI Pin Select
+ 'MCUCR_PUD': '$10', # Pull-up disable
+ 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
+ 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
+ 'MCUSR_BORF': '$4', # Brown-out Reset Flag
+ 'MCUSR_EXTRF': '$2', # External Reset Flag
+ 'MCUSR_PORF': '$1', # Power-on reset flag
+ 'OSCCAL' : '$66', # Oscillator Calibration Value
+ 'CLKPR' : '$61', #
+ 'CLKPR_CLKPCE': '$80', #
+ 'CLKPR_CLKPS': '$f', #
+ 'SMCR' : '$53', # Sleep Mode Control Register
+ 'SMCR_SM': '$e', # Sleep Mode Select bits
+ 'SMCR_SE': '$1', # Sleep Enable
+ 'GPIOR2' : '$3a', # General Purpose IO Register 2
+ 'GPIOR2_GPIOR': '$ff', # General Purpose IO Register 2
+ 'GPIOR1' : '$39', # General Purpose IO Register 1
+ 'GPIOR1_GPIOR': '$ff', # General Purpose IO Register 1
+ 'GPIOR0' : '$3e', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR07': '$80', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR06': '$40', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR05': '$20', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR04': '$10', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR03': '$8', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR02': '$4', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR01': '$2', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR00': '$1', # General Purpose IO Register 0
+ 'PLLCSR' : '$49', # PLL Control And Status Registe
+ 'PLLCSR_PLLF': '$4', # PLL Factor
+ 'PLLCSR_PLLE': '$2', # PLL Enable
+ 'PLLCSR_PLOCK': '$1', # PLL Lock Detector
+ 'PRR' : '$64', # Power Reduction Register
+ 'PRR_PRCAN': '$40', # Power Reduction CAN
+ 'PRR_PRPSC': '$20', # Power Reduction PSC
+ 'PRR_PRTIM1': '$10', # Power Reduction Timer/Counter1
+ 'PRR_PRTIM0': '$8', # Power Reduction Timer/Counter0
+ 'PRR_PRSPI': '$4', # Power Reduction Serial Periphe
+ 'PRR_PRLIN': '$2', # Power Reduction LIN UART
+ 'PRR_PRADC': '$1', # Power Reduction ADC
+
+# Module PORTE
+ 'PORTE' : '$2e', # Port E Data Register
+ 'DDRE' : '$2d', # Port E Data Direction Register
+ 'PINE' : '$2c', # Port E Input Pins
+
+# Module TIMER_COUNTER_0
+ 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
+ 'TIMSK0_OCIE0B': '$4', # Timer/Counter0 Output Compare
+ 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
+ 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
+ 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
+ 'TIFR0_OCF0B': '$4', # Timer/Counter0 Output Compare
+ 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
+ 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
+ 'TCCR0A' : '$44', # Timer/Counter Control Registe
+ 'TCCR0A_COM0A': '$c0', # Compare Output Mode, Phase Cor
+ 'TCCR0A_COM0B': '$30', # Compare Output Mode, Fast PWm
+ 'TCCR0A_WGM0': '$3', # Waveform Generation Mode
+ 'TCCR0B' : '$45', # Timer/Counter Control Register
+ 'TCCR0B_FOC0A': '$80', # Force Output Compare A
+ 'TCCR0B_FOC0B': '$40', # Force Output Compare B
+ 'TCCR0B_WGM02': '$8', #
+ 'TCCR0B_CS0': '$7', # Clock Select
+ 'TCNT0' : '$46', # Timer/Counter0
+ 'OCR0A' : '$47', # Timer/Counter0 Output Compare
+ 'OCR0B' : '$48', # Timer/Counter0 Output Compare
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_ICPSEL1': '$40', # Timer1 Input Capture Selection
+ 'GTCCR_PSR10': '$1', # Prescaler Reset Timer/Counter1
+
+# Module TIMER_COUNTER_1
+ 'TIMSK1' : '$6f', # Timer/Counter Interrupt Mask R
+ 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
+ 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output CompareB
+ 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output CompareA
+ 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
+ 'TIFR1' : '$36', # Timer/Counter Interrupt Flag r
+ 'TIFR1_ICF1': '$20', # Input Capture Flag 1
+ 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
+ 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
+ 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
+ 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
+ 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
+ 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
+ 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
+ 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
+ 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
+ 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
+ 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
+ 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
+ 'TCCR1C' : '$82', # Timer/Counter1 Control Registe
+ 'TCCR1C_FOC1A': '$80', #
+ 'TCCR1C_FOC1B': '$40', #
+ 'TCNT1' : '$84', # Timer/Counter1 Bytes
+ 'OCR1A' : '$88', # Timer/Counter1 Output Compare
+ 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
+ 'ICR1' : '$86', # Timer/Counter1 Input Capture R
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSRSYNC': '$1', # Prescaler Reset Timer/Counter1
+
+# Module AD_CONVERTER
+ 'ADMUX' : '$7c', # The ADC multiplexer Selection
+ 'ADMUX_REFS': '$c0', # Reference Selection Bits
+ 'ADMUX_ADLAR': '$20', # Left Adjust Result
+ 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
+ 'ADCSRA' : '$7a', # The ADC Control and Status reg
+ 'ADCSRA_ADEN': '$80', # ADC Enable
+ 'ADCSRA_ADSC': '$40', # ADC Start Conversion
+ 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
+ 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
+ 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
+ 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
+ 'ADC' : '$78', # ADC Data Register Bytes
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ADHSM': '$80', # ADC High Speed Mode
+ 'ADCSRB_ISRCEN': '$40', # Current Source Enable
+ 'ADCSRB_AREFEN': '$20', # Analog Reference pin Enable
+ 'ADCSRB_ADTS': '$f', # ADC Auto Trigger Sources
+ 'DIDR0' : '$7e', # Digital Input Disable Register
+ 'DIDR0_ADC7D': '$80', # ADC7 Digital input Disable
+ 'DIDR0_ADC6D': '$40', # ADC6 Digital input Disable
+ 'DIDR0_ADC5D': '$20', # ADC5 Digital input Disable
+ 'DIDR0_ADC4D': '$10', # ADC4 Digital input Disable
+ 'DIDR0_ADC3D': '$8', # ADC3 Digital input Disable
+ 'DIDR0_ADC2D': '$4', # ADC2 Digital input Disable
+ 'DIDR0_ADC1D': '$2', # ADC1 Digital input Disable
+ 'DIDR0_ADC0D': '$1', # ADC0 Digital input Disable
+ 'DIDR1' : '$7f', # Digital Input Disable Register
+ 'DIDR1_AMP2PD': '$40', # AMP2P Pin Digital input Disabl
+ 'DIDR1_ACMP0D': '$20', # ACMP0 Pin Digital input Disabl
+ 'DIDR1_AMP0PD': '$10', # AMP0P Pin Digital input Disabl
+ 'DIDR1_AMP0ND': '$8', # AMP0N Pin Digital input Disabl
+ 'DIDR1_ADC10D': '$4', # ADC10 Pin Digital input Disabl
+ 'DIDR1_ADC9D': '$2', # ADC9 Pin Digital input Disable
+ 'DIDR1_ADC8D': '$1', # ADC8 Pin Digital input Disable
+ 'AMP0CSR' : '$75', #
+ 'AMP0CSR_AMP0EN': '$80', #
+ 'AMP0CSR_AMP0IS': '$40', #
+ 'AMP0CSR_AMP0G': '$30', #
+ 'AMP0CSR_AMPCMP0': '$8', # Amplifier 0 - Comparator 0 Con
+ 'AMP0CSR_AMP0TS': '$7', #
+ 'AMP1CSR' : '$76', #
+ 'AMP1CSR_AMP1EN': '$80', #
+ 'AMP1CSR_AMP1IS': '$40', #
+ 'AMP1CSR_AMP1G': '$30', #
+ 'AMP1CSR_AMPCMP1': '$8', # Amplifier 1 - Comparator 1 Con
+ 'AMP1CSR_AMP1TS': '$7', #
+ 'AMP2CSR' : '$77', #
+ 'AMP2CSR_AMP2EN': '$80', #
+ 'AMP2CSR_AMP2IS': '$40', #
+ 'AMP2CSR_AMP2G': '$30', #
+ 'AMP2CSR_AMPCMP2': '$8', # Amplifier 2 - Comparator 2 Con
+ 'AMP2CSR_AMP2TS': '$7', #
+
+# Module LINUART
+ 'LINCR' : '$c8', # LIN Control Register
+ 'LINCR_LSWRES': '$80', # Software Reset
+ 'LINCR_LIN13': '$40', # LIN Standard
+ 'LINCR_LCONF': '$30', # LIN Configuration bits
+ 'LINCR_LENA': '$8', # LIN or UART Enable
+ 'LINCR_LCMD': '$7', # LIN Command and Mode bits
+ 'LINSIR' : '$c9', # LIN Status and Interrupt Regis
+ 'LINSIR_LIDST': '$e0', # Identifier Status bits
+ 'LINSIR_LBUSY': '$10', # Busy Signal
+ 'LINSIR_LERR': '$8', # Error Interrupt
+ 'LINSIR_LIDOK': '$4', # Identifier Interrupt
+ 'LINSIR_LTXOK': '$2', # Transmit Performed Interrupt
+ 'LINSIR_LRXOK': '$1', # Receive Performed Interrupt
+ 'LINENIR' : '$ca', # LIN Enable Interrupt Register
+ 'LINENIR_LENERR': '$8', # Enable Error Interrupt
+ 'LINENIR_LENIDOK': '$4', # Enable Identifier Interrupt
+ 'LINENIR_LENTXOK': '$2', # Enable Transmit Performed Inte
+ 'LINENIR_LENRXOK': '$1', # Enable Receive Performed Inter
+ 'LINERR' : '$cb', # LIN Error Register
+ 'LINERR_LABORT': '$80', # Abort Flag
+ 'LINERR_LTOERR': '$40', # Frame Time Out Error Flag
+ 'LINERR_LOVERR': '$20', # Overrun Error Flag
+ 'LINERR_LFERR': '$10', # Framing Error Flag
+ 'LINERR_LSERR': '$8', # Synchronization Error Flag
+ 'LINERR_LPERR': '$4', # Parity Error Flag
+ 'LINERR_LCERR': '$2', # Checksum Error Flag
+ 'LINERR_LBERR': '$1', # Bit Error Flag
+ 'LINBTR' : '$cc', # LIN Bit Timing Register
+ 'LINBTR_LDISR': '$80', # Disable Bit Timing Resynchroni
+ 'LINBTR_LBT': '$3f', # LIN Bit Timing bits
+ 'LINBRRL' : '$cd', # LIN Baud Rate Low Register
+ 'LINBRRL_LDIV': '$ff', #
+ 'LINBRRH' : '$ce', # LIN Baud Rate High Register
+ 'LINBRRH_LDIV': '$f', #
+ 'LINDLR' : '$cf', # LIN Data Length Register
+ 'LINDLR_LTXDL': '$f0', # LIN Transmit Data Length bits
+ 'LINDLR_LRXDL': '$f', # LIN Receive Data Length bits
+ 'LINIDR' : '$d0', # LIN Identifier Register
+ 'LINIDR_LP': '$c0', # Parity bits
+ 'LINIDR_LID': '$3f', # Identifier bit 5 or Data Lengt
+ 'LINSEL' : '$d1', # LIN Data Buffer Selection Regi
+ 'LINSEL_LAINC': '$8', # Auto Increment of Data Buffer
+ 'LINSEL_LINDX': '$7', # FIFO LIN Data Buffer Index bit
+ 'LINDAT' : '$d2', # LIN Data Register
+ 'LINDAT_LDATA': '$ff', #
+
+# Module SPI
+ 'SPCR' : '$4c', # SPI Control Register
+ 'SPCR_SPIE': '$80', # SPI Interrupt Enable
+ 'SPCR_SPE': '$40', # SPI Enable
+ 'SPCR_DORD': '$20', # Data Order
+ 'SPCR_MSTR': '$10', # Master/Slave Select
+ 'SPCR_CPOL': '$8', # Clock polarity
+ 'SPCR_CPHA': '$4', # Clock Phase
+ 'SPCR_SPR': '$3', # SPI Clock Rate Selects
+ 'SPSR' : '$4d', # SPI Status Register
+ 'SPSR_SPIF': '$80', # SPI Interrupt Flag
+ 'SPSR_WCOL': '$40', # Write Collision Flag
+ 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
+ 'SPDR' : '$4e', # SPI Data Register
+
+# Module WATCHDOG
+ 'WDTCSR' : '$60', # Watchdog Timer Control Registe
+ 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
+ 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
+ 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
+ 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
+ 'WDTCSR_WDE': '$8', # Watch Dog Enable
+
+# Module EXTERNAL_INTERRUPT
+ 'EICRA' : '$69', # External Interrupt Control Reg
+ 'EICRA_ISC3': '$c0', # External Interrupt Sense Contr
+ 'EICRA_ISC2': '$30', # External Interrupt Sense Contr
+ 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
+ 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
+ 'EIMSK' : '$3d', # External Interrupt Mask Regist
+ 'EIMSK_INT': '$f', # External Interrupt Request 3 E
+ 'EIFR' : '$3c', # External Interrupt Flag Regist
+ 'EIFR_INTF': '$f', # External Interrupt Flags
+ 'PCICR' : '$68', # Pin Change Interrupt Control R
+ 'PCICR_PCIE': '$f', # Pin Change Interrupt Enables
+ 'PCMSK3' : '$6d', # Pin Change Mask Register 3
+ 'PCMSK3_PCINT': '$7', # Pin Change Enable Masks
+ 'PCMSK2' : '$6c', # Pin Change Mask Register 2
+ 'PCMSK2_PCINT': '$ff', # Pin Change Enable Masks
+ 'PCMSK1' : '$6b', # Pin Change Mask Register 1
+ 'PCMSK1_PCINT': '$ff', # Pin Change Enable Masks
+ 'PCMSK0' : '$6a', # Pin Change Mask Register 0
+ 'PCMSK0_PCINT': '$ff', # Pin Change Enable Masks
+ 'PCIFR' : '$3b', # Pin Change Interrupt Flag Regi
+ 'PCIFR_PCIF': '$f', # Pin Change Interrupt Flags
+
+# Module EEPROM
+ 'EEAR' : '$41', # EEPROM Read/Write Access
+ 'EEDR' : '$40', # EEPROM Data Register
+ 'EECR' : '$3f', # EEPROM Control Register
+ 'EECR_EEPM': '$30', #
+ 'EECR_EERIE': '$8', # EEProm Ready Interrupt Enable
+ 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
+ 'EECR_EEWE': '$2', # EEPROM Write Enable
+ 'EECR_EERE': '$1', # EEPROM Read Enable
+
+# Module PSC
+ 'PIFR' : '$bc', # PSC Interrupt Flag Register
+ 'PIFR_PEV': '$e', # PSC External Event 2 Interrupt
+ 'PIFR_PEOP': '$1', # PSC End of Cycle Interrupt
+ 'PIM' : '$bb', # PSC Interrupt Mask Register
+ 'PIM_PEVE': '$e', # External Event 2 Interrupt Ena
+ 'PIM_PEOPE': '$1', # PSC End of Cycle Interrupt Ena
+ 'PMIC2' : '$ba', # PSC Module 2 Input Control Reg
+ 'PMIC2_POVEN2': '$80', # PSC Module 2 Overlap Enable
+ 'PMIC2_PISEL2': '$40', # PSC Module 2 Input Select
+ 'PMIC2_PELEV2': '$20', # PSC Module 2 Input Level Selec
+ 'PMIC2_PFLTE2': '$10', # PSC Module 2 Input Filter Enab
+ 'PMIC2_PAOC2': '$8', # PSC Module 2 Asynchronous Outp
+ 'PMIC2_PRFM2': '$7', # PSC Module 2 Input Mode bits
+ 'PMIC1' : '$b9', # PSC Module 1 Input Control Reg
+ 'PMIC1_POVEN1': '$80', # PSC Module 1 Overlap Enable
+ 'PMIC1_PISEL1': '$40', # PSC Module 1 Input Select
+ 'PMIC1_PELEV1': '$20', # PSC Module 1 Input Level Selec
+ 'PMIC1_PFLTE1': '$10', # PSC Module 1 Input Filter Enab
+ 'PMIC1_PAOC1': '$8', # PSC Module 1 Asynchronous Outp
+ 'PMIC1_PRFM1': '$7', # PSC Module 1 Input Mode bits
+ 'PMIC0' : '$b8', # PSC Module 0 Input Control Reg
+ 'PMIC0_POVEN0': '$80', # PSC Module 0 Overlap Enable
+ 'PMIC0_PISEL0': '$40', # PSC Module 0 Input Select
+ 'PMIC0_PELEV0': '$20', # PSC Module 0 Input Level Selec
+ 'PMIC0_PFLTE0': '$10', # PSC Module 0 Input Filter Enab
+ 'PMIC0_PAOC0': '$8', # PSC Module 0 Asynchronous Outp
+ 'PMIC0_PRFM0': '$7', # PSC Module 0 Input Mode bits
+ 'PCTL' : '$b7', # PSC Control Register
+ 'PCTL_PPRE': '$c0', # PSC Prescaler Select bits
+ 'PCTL_PCLKSEL': '$20', # PSC Input Clock Select
+ 'PCTL_PCCYC': '$2', # PSC Complete Cycle
+ 'PCTL_PRUN': '$1', # PSC Run
+ 'POC' : '$b6', # PSC Output Configuration
+ 'POC_POEN2B': '$20', # PSC Output 2B Enable
+ 'POC_POEN2A': '$10', # PSC Output 2A Enable
+ 'POC_POEN1B': '$8', # PSC Output 1B Enable
+ 'POC_POEN1A': '$4', # PSC Output 1A Enable
+ 'POC_POEN0B': '$2', # PSC Output 0B Enable
+ 'POC_POEN0A': '$1', # PSC Output 0A Enable
+ 'PCNF' : '$b5', # PSC Configuration Register
+ 'PCNF_PULOCK': '$20', # PSC Update Lock
+ 'PCNF_PMODE': '$10', # PSC Mode
+ 'PCNF_POPB': '$8', # PSC Output B Polarity
+ 'PCNF_POPA': '$4', # PSC Output A Polarity
+ 'PSYNC' : '$b4', # PSC Synchro Configuration
+ 'PSYNC_PSYNC2': '$30', # Selection of Synchronization O
+ 'PSYNC_PSYNC1': '$c', # Selection of Synchronization O
+ 'PSYNC_PSYNC0': '$3', # Selection of Synchronization O
+ 'POCR_RB' : '$b2', # PSC Output Compare RB Register
+ 'POCR2SB' : '$b0', # PSC Module 2 Output Compare SB
+ 'POCR2RA' : '$ae', # PSC Module 2 Output Compare RA
+ 'POCR2SA' : '$ac', # PSC Module 2 Output Compare SA
+ 'POCR1SB' : '$aa', # PSC Module 1 Output Compare SB
+ 'POCR1RA' : '$a8', # PSC Module 1 Output Compare RA
+ 'POCR1SA' : '$a6', # PSC Output Compare SA Register
+ 'POCR0SB' : '$a4', # PSC Output Compare SB Register
+ 'POCR0RA' : '$a2', # PSC Module 0 Output Compare RA
+ 'POCR0SA' : '$a0', # PSC Module 0 Output Compare SA
+
+ '__amforth_dummy':'0'
+}
diff --git a/amforth-6.5/avr8/devices/atmega16m1/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega16m1/words/no-jtag.asm
new file mode 100644
index 0000000..352a4bb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega16m1/words/no-jtag.asm
@@ -0,0 +1,14 @@
+; ( -- )
+; ( -- )
+; MCU
+; disable jtag at runtime
+VE_NOJTAG:
+ .dw $FF05
+ .db "-jtag",0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOJTAG
+XT_NOJTAG:
+ .dw PFA_NOJTAG
+PFA_NOJTAG:
+
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega16m1/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega16m1/words/no-wdt.asm
new file mode 100644
index 0000000..ff6ddd1
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega16m1/words/no-wdt.asm
@@ -0,0 +1,34 @@
+; ( -- )
+; MCU
+; disable watch dog timer at runtime
+VE_NOWDT:
+ .dw $ff04
+ .db "-wdt"
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOWDT
+XT_NOWDT:
+ .dw PFA_NOWDT
+PFA_NOWDT:
+
+ in temp1,SREG
+ push temp1
+ ; Turn always off global interrupt.
+ cli
+ ; Reset Watchdog Timer
+ wdr
+ ; Clear WDRF in MCUSR
+ in temp1, MCUSR
+ andi temp1, (0xff & (0<<WDRF))
+ out MCUSR, temp1
+ ; Write logical one to WDCE and WDE
+ ; Keep old prescaler setting to prevent unintentional time-out
+ in_ temp1, WDTCSR
+ ori temp1, (1<<WDCE) | (1<<WDE)
+ out_ WDTCSR, temp1
+ ; Turn off WDT
+ ldi temp1, (0<<WDE)
+ out_ WDTCSR, temp1
+ ; restore status register
+ pop temp1
+ out SREG,temp1
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega16m1/words/sleep.asm b/amforth-6.5/avr8/devices/atmega16m1/words/sleep.asm
new file mode 100644
index 0000000..256249c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega16m1/words/sleep.asm
@@ -0,0 +1,19 @@
+; ( mode -- )
+; MCU
+; put the controller into the specified sleep mode
+VE_SLEEP:
+ .dw $ff05
+ .db "sleep", 0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_SLEEP
+XT_SLEEP:
+ .dw PFA_SLEEP
+PFA_SLEEP:
+ andi tosl, 7 ; leave only legal mode bits
+ lsl tosl ; move to correct location (bits 3-1)
+ ori tosl, 1 ; set the SE bit
+ out_ SMCR, tosl ; set the sleep config
+ sleep ; nighty-night
+ out_ SMCR, zerol ; 0 protects against accidental sleeps
+ loadtos ; pop argument from stack
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega16u2/atmega16u2.frt b/amforth-6.5/avr8/devices/atmega16u2/atmega16u2.frt
new file mode 100644
index 0000000..89a6927
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega16u2/atmega16u2.frt
@@ -0,0 +1,367 @@
+\ Partname: ATmega16U2
+\ generated automatically
+
+\ PORTB
+&37 constant PORTB \ Port B Data Register
+&36 constant DDRB \ Port B Data Direction Register
+&35 constant PINB \ Port B Input Pins
+\ PORTD
+&43 constant PORTD \ Port D Data Register
+&42 constant DDRD \ Port D Data Direction Register
+&41 constant PIND \ Port D Input Pins
+\ SPI
+&76 constant SPCR \ SPI Control Register
+ $80 constant SPCR_SPIE \ SPI Interrupt Enable
+ $40 constant SPCR_SPE \ SPI Enable
+ $20 constant SPCR_DORD \ Data Order
+ $10 constant SPCR_MSTR \ Master/Slave Select
+ $08 constant SPCR_CPOL \ Clock polarity
+ $04 constant SPCR_CPHA \ Clock Phase
+ $03 constant SPCR_SPR \ SPI Clock Rate Selects
+&77 constant SPSR \ SPI Status Register
+ $80 constant SPSR_SPIF \ SPI Interrupt Flag
+ $40 constant SPSR_WCOL \ Write Collision Flag
+ $01 constant SPSR_SPI2X \ Double SPI Speed Bit
+&78 constant SPDR \ SPI Data Register
+\ BOOT_LOAD
+&87 constant SPMCSR \ Store Program Memory Control Register
+ $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
+ $20 constant SPMCSR_SIGRD \ Signature Row Read
+ $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
+ $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
+ $04 constant SPMCSR_PGWRT \ Page Write
+ $02 constant SPMCSR_PGERS \ Page Erase
+ $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
+\ EEPROM
+&65 constant EEAR \ EEPROM Address Register Low Bytes
+&64 constant EEDR \ EEPROM Data Register
+&63 constant EECR \ EEPROM Control Register
+ $30 constant EECR_EEPM \ EEPROM Programming Mode Bits
+ $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
+ $04 constant EECR_EEMPE \ EEPROM Master Write Enable
+ $02 constant EECR_EEPE \ EEPROM Write Enable
+ $01 constant EECR_EERE \ EEPROM Read Enable
+\ TIMER_COUNTER_0
+&72 constant OCR0B \ Timer/Counter0 Output Compare Register
+&71 constant OCR0A \ Timer/Counter0 Output Compare Register
+&70 constant TCNT0 \ Timer/Counter0
+&69 constant TCCR0B \ Timer/Counter Control Register B
+ $80 constant TCCR0B_FOC0A \ Force Output Compare A
+ $40 constant TCCR0B_FOC0B \ Force Output Compare B
+ $08 constant TCCR0B_WGM02 \
+ $07 constant TCCR0B_CS0 \ Clock Select
+&68 constant TCCR0A \ Timer/Counter Control Register A
+ $C0 constant TCCR0A_COM0A \ Compare Output Mode, Phase Correct PWM Mode
+ $30 constant TCCR0A_COM0B \ Compare Output Mode, Fast PWm
+ $03 constant TCCR0A_WGM0 \ Waveform Generation Mode
+&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
+ $04 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare Match B Interrupt Enable
+ $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match A Interrupt Enable
+ $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
+&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
+ $04 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare Flag 0B
+ $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0A
+ $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
+&67 constant GTCCR \ General Timer/Counter Control Register
+ $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
+ $01 constant GTCCR_PSRSYNC \ Prescaler Reset Timer/Counter1 and Timer/Counter0
+\ TIMER_COUNTER_1
+&128 constant TCCR1A \ Timer/Counter1 Control Register A
+ $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
+ $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
+ $0C constant TCCR1A_COM1C \ Compare Output Mode 1C, bits
+ $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
+&129 constant TCCR1B \ Timer/Counter1 Control Register B
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
+ $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
+&130 constant TCCR1C \ Timer/Counter 1 Control Register C
+ $80 constant TCCR1C_FOC1A \ Force Output Compare 1A
+ $40 constant TCCR1C_FOC1B \ Force Output Compare 1B
+ $20 constant TCCR1C_FOC1C \ Force Output Compare 1C
+&132 constant TCNT1 \ Timer/Counter1 Bytes
+&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
+&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
+&140 constant OCR1C \ Timer/Counter1 Output Compare Register C Bytes
+&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
+&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
+ $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
+ $08 constant TIMSK1_OCIE1C \ Timer/Counter1 Output Compare C Match Interrupt Enable
+ $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
+ $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
+ $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
+&54 constant TIFR1 \ Timer/Counter1 Interrupt Flag register
+ $20 constant TIFR1_ICF1 \ Input Capture Flag 1
+ $08 constant TIFR1_OCF1C \ Output Compare Flag 1C
+ $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
+ $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
+ $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
+\ PLL
+&73 constant PLLCSR \ PLL Status and Control register
+ $1C constant PLLCSR_PLLP \ PLL prescaler Bits
+ $02 constant PLLCSR_PLLE \ PLL Enable Bit
+ $01 constant PLLCSR_PLOCK \ PLL Lock Status Bit
+\ USB_DEVICE
+&244 constant UEINT \
+&242 constant UEBCLX \
+&241 constant UEDATX \
+&240 constant UEIENX \
+ $80 constant UEIENX_FLERRE \
+ $40 constant UEIENX_NAKINE \
+ $10 constant UEIENX_NAKOUTE \
+ $08 constant UEIENX_RXSTPE \
+ $04 constant UEIENX_RXOUTE \
+ $02 constant UEIENX_STALLEDE \
+ $01 constant UEIENX_TXINE \
+&239 constant UESTA1X \
+ $04 constant UESTA1X_CTRLDIR \
+ $03 constant UESTA1X_CURRBK \
+&238 constant UESTA0X \
+ $80 constant UESTA0X_CFGOK \
+ $40 constant UESTA0X_OVERFI \
+ $20 constant UESTA0X_UNDERFI \
+ $0C constant UESTA0X_DTSEQ \
+ $03 constant UESTA0X_NBUSYBK \
+&237 constant UECFG1X \
+ $70 constant UECFG1X_EPSIZE \
+ $0C constant UECFG1X_EPBK \
+ $02 constant UECFG1X_ALLOC \
+&236 constant UECFG0X \
+ $C0 constant UECFG0X_EPTYPE \
+ $01 constant UECFG0X_EPDIR \
+&235 constant UECONX \
+ $20 constant UECONX_STALLRQ \
+ $10 constant UECONX_STALLRQC \
+ $08 constant UECONX_RSTDT \
+ $01 constant UECONX_EPEN \
+&234 constant UERST \
+ $1F constant UERST_EPRST \
+&233 constant UENUM \
+&232 constant UEINTX \
+ $80 constant UEINTX_FIFOCON \
+ $40 constant UEINTX_NAKINI \
+ $20 constant UEINTX_RWAL \
+ $10 constant UEINTX_NAKOUTI \
+ $08 constant UEINTX_RXSTPI \
+ $04 constant UEINTX_RXOUTI \
+ $02 constant UEINTX_STALLEDI \
+ $01 constant UEINTX_TXINI \
+&230 constant UDMFN \
+ $10 constant UDMFN_FNCERR \
+&228 constant UDFNUM \
+&227 constant UDADDR \
+ $80 constant UDADDR_ADDEN \
+ $7F constant UDADDR_UADD \
+&226 constant UDIEN \
+ $40 constant UDIEN_UPRSME \
+ $20 constant UDIEN_EORSME \
+ $10 constant UDIEN_WAKEUPE \
+ $08 constant UDIEN_EORSTE \
+ $04 constant UDIEN_SOFE \
+ $01 constant UDIEN_SUSPE \
+&225 constant UDINT \
+ $40 constant UDINT_UPRSMI \
+ $20 constant UDINT_EORSMI \
+ $10 constant UDINT_WAKEUPI \
+ $08 constant UDINT_EORSTI \
+ $04 constant UDINT_SOFI \
+ $01 constant UDINT_SUSPI \
+&224 constant UDCON \
+ $04 constant UDCON_RSTCPU \
+ $02 constant UDCON_RMWKUP \
+ $01 constant UDCON_DETACH \
+&216 constant USBCON \ USB General Control Register
+ $80 constant USBCON_USBE \
+ $20 constant USBCON_FRZCLK \
+&99 constant REGCR \ Regulator Control Register
+ $01 constant REGCR_REGDIS \
+\ PS2
+&251 constant UPOE \
+ $C0 constant UPOE_UPWE \
+ $30 constant UPOE_UPDRV \
+ $08 constant UPOE_SCKI \
+ $04 constant UPOE_DATAI \
+ $02 constant UPOE_DPI \
+ $01 constant UPOE_DMI \
+&250 constant PS2CON \ PS2 Pad Enable register
+ $01 constant PS2CON_PS2EN \ Enable
+\ CPU
+&95 constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ $08 constant SREG_V \ Two's Complement Overflow Flag
+ $04 constant SREG_N \ Negative Flag
+ $02 constant SREG_Z \ Zero Flag
+ $01 constant SREG_C \ Carry Flag
+&93 constant SP \ Stack Pointer
+&85 constant MCUCR \ MCU Control Register
+ $10 constant MCUCR_PUD \ Pull-up disable
+ $02 constant MCUCR_IVSEL \ Interrupt Vector Select
+ $01 constant MCUCR_IVCE \ Interrupt Vector Change Enable
+&84 constant MCUSR \ MCU Status Register
+ $20 constant MCUSR_USBRF \ USB reset flag
+ $08 constant MCUSR_WDRF \ Watchdog Reset Flag
+ $04 constant MCUSR_BORF \ Brown-out Reset Flag
+ $02 constant MCUSR_EXTRF \ External Reset Flag
+ $01 constant MCUSR_PORF \ Power-on reset flag
+&102 constant OSCCAL \ Oscillator Calibration Value
+&97 constant CLKPR \
+ $80 constant CLKPR_CLKPCE \
+ $0F constant CLKPR_CLKPS \
+&83 constant SMCR \ Sleep Mode Control Register
+ $0E constant SMCR_SM \ Sleep Mode Select bits
+ $01 constant SMCR_SE \ Sleep Enable
+&92 constant EIND \ Extended Indirect Register
+&75 constant GPIOR2 \ General Purpose IO Register 2
+ $FF constant GPIOR2_GPIOR \ General Purpose IO Register 2 bis
+&74 constant GPIOR1 \ General Purpose IO Register 1
+ $FF constant GPIOR1_GPIOR \ General Purpose IO Register 1 bis
+&62 constant GPIOR0 \ General Purpose IO Register 0
+ $80 constant GPIOR0_GPIOR07 \ General Purpose IO Register 0 bit 7
+ $40 constant GPIOR0_GPIOR06 \ General Purpose IO Register 0 bit 6
+ $20 constant GPIOR0_GPIOR05 \ General Purpose IO Register 0 bit 5
+ $10 constant GPIOR0_GPIOR04 \ General Purpose IO Register 0 bit 4
+ $08 constant GPIOR0_GPIOR03 \ General Purpose IO Register 0 bit 3
+ $04 constant GPIOR0_GPIOR02 \ General Purpose IO Register 0 bit 2
+ $02 constant GPIOR0_GPIOR01 \ General Purpose IO Register 0 bit 1
+ $01 constant GPIOR0_GPIOR00 \ General Purpose IO Register 0 bit 0
+&101 constant PRR1 \ Power Reduction Register1
+ $80 constant PRR1_PRUSB \ Power Reduction USB
+ $01 constant PRR1_PRUSART1 \ Power Reduction USART1
+&100 constant PRR0 \ Power Reduction Register0
+ $20 constant PRR0_PRTIM0 \ Power Reduction Timer/Counter0
+ $08 constant PRR0_PRTIM1 \ Power Reduction Timer/Counter1
+ $04 constant PRR0_PRSPI \ Power Reduction Serial Peripheral Interface
+&210 constant CLKSTA \
+ $02 constant CLKSTA_RCON \
+ $01 constant CLKSTA_EXTON \
+&209 constant CLKSEL1 \
+ $F0 constant CLKSEL1_RCCKSEL \
+ $0F constant CLKSEL1_EXCKSEL \
+&208 constant CLKSEL0 \
+ $C0 constant CLKSEL0_RCSUT \
+ $30 constant CLKSEL0_EXSUT \
+ $08 constant CLKSEL0_RCE \
+ $04 constant CLKSEL0_EXTE \
+ $01 constant CLKSEL0_CLKS \
+&81 constant DWDR \ debugWire communication register
+\ EXTERNAL_INTERRUPT
+&105 constant EICRA \ External Interrupt Control Register A
+ $C0 constant EICRA_ISC3 \ External Interrupt Sense Control Bit
+ $30 constant EICRA_ISC2 \ External Interrupt Sense Control Bit
+ $0C constant EICRA_ISC1 \ External Interrupt Sense Control Bit
+ $03 constant EICRA_ISC0 \ External Interrupt Sense Control Bit
+&106 constant EICRB \ External Interrupt Control Register B
+ $C0 constant EICRB_ISC7 \ External Interrupt 7-4 Sense Control Bit
+ $30 constant EICRB_ISC6 \ External Interrupt 7-4 Sense Control Bit
+ $0C constant EICRB_ISC5 \ External Interrupt 7-4 Sense Control Bit
+ $03 constant EICRB_ISC4 \ External Interrupt 7-4 Sense Control Bit
+&61 constant EIMSK \ External Interrupt Mask Register
+ $FF constant EIMSK_INT \ External Interrupt Request 7 Enable
+&60 constant EIFR \ External Interrupt Flag Register
+ $FF constant EIFR_INTF \ External Interrupt Flags
+&107 constant PCMSK0 \ Pin Change Mask Register 0
+ $FF constant PCMSK0_PCINT \ Pin Change Enable Masks
+&108 constant PCMSK1 \ Pin Change Mask Register 1
+ $1F constant PCMSK1_PCINT \
+&59 constant PCIFR \ Pin Change Interrupt Flag Register
+ $03 constant PCIFR_PCIF \ Pin Change Interrupt Flags
+&104 constant PCICR \ Pin Change Interrupt Control Register
+ $03 constant PCICR_PCIE \ Pin Change Interrupt Enables
+\ USART1
+&206 constant UDR1 \ USART I/O Data Register
+&200 constant UCSR1A \ USART Control and Status Register A
+ $80 constant UCSR1A_RXC1 \ USART Receive Complete
+ $40 constant UCSR1A_TXC1 \ USART Transmitt Complete
+ $20 constant UCSR1A_UDRE1 \ USART Data Register Empty
+ $10 constant UCSR1A_FE1 \ Framing Error
+ $08 constant UCSR1A_DOR1 \ Data overRun
+ $04 constant UCSR1A_UPE1 \ Parity Error
+ $02 constant UCSR1A_U2X1 \ Double the USART transmission speed
+ $01 constant UCSR1A_MPCM1 \ Multi-processor Communication Mode
+&201 constant UCSR1B \ USART Control and Status Register B
+ $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable
+ $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable
+ $20 constant UCSR1B_UDRIE1 \ USART Data register Empty Interrupt Enable
+ $10 constant UCSR1B_RXEN1 \ Receiver Enable
+ $08 constant UCSR1B_TXEN1 \ Transmitter Enable
+ $04 constant UCSR1B_UCSZ12 \ Character Size
+ $02 constant UCSR1B_RXB81 \ Receive Data Bit 8
+ $01 constant UCSR1B_TXB81 \ Transmit Data Bit 8
+&202 constant UCSR1C \ USART Control and Status Register C
+ $C0 constant UCSR1C_UMSEL1 \ USART Mode Select
+ $30 constant UCSR1C_UPM1 \ Parity Mode Bits
+ $08 constant UCSR1C_USBS1 \ Stop Bit Select
+ $06 constant UCSR1C_UCSZ1 \ Character Size
+ $01 constant UCSR1C_UCPOL1 \ Clock Polarity
+&203 constant UCSR1D \ USART Control and Status Register D
+ $02 constant UCSR1D_CTSEN \ CTS Enable
+ $01 constant UCSR1D_RTSEN \ RTS Enable
+&204 constant UBRR1 \ USART Baud Rate Register Bytes
+\ WATCHDOG
+&96 constant WDTCSR \ Watchdog Timer Control Register
+ $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Flag
+ $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Enable
+ $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
+ $10 constant WDTCSR_WDCE \ Watchdog Change Enable
+ $08 constant WDTCSR_WDE \ Watch Dog Enable
+&98 constant WDTCKD \ Watchdog Timer Clock Divider
+ $08 constant WDTCKD_WDEWIF \ Watchdog Early Warning Interrupt Flag
+ $04 constant WDTCKD_WDEWIE \ Watchdog Early Warning Interrupt Enable
+ $03 constant WDTCKD_WCLKD \ Watchdog Timer Clock Dividers
+\ ANALOG_COMPARATOR
+&80 constant ACSR \ Analog Comparator Control And Status Register
+ $80 constant ACSR_ACD \ Analog Comparator Disable
+ $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
+ $20 constant ACSR_ACO \ Analog Compare Output
+ $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
+ $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
+ $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
+ $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
+&127 constant DIDR1 \
+ $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
+ $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
+\ PORTC
+&40 constant PORTC \ Port C Data Register
+ $F0 constant PORTC_PORTC \ Port C Data Register bits
+ $07 constant PORTC_PORTC \ Port C Data Register bits
+&39 constant DDRC \ Port C Data Direction Register
+ $F0 constant DDRC_DDC \ Port C Data Direction Register bits
+ $07 constant DDRC_DDC \ Port C Data Direction Register bits
+&38 constant PINC \ Port C Input Pins
+ $F0 constant PINC_PINC \ Port C Input Pins bits
+ $07 constant PINC_PINC \ Port C Input Pins bits
+
+\ Interrupts
+&2 constant INT0Addr \ External Interrupt Request 0
+&4 constant INT1Addr \ External Interrupt Request 1
+&6 constant INT2Addr \ External Interrupt Request 2
+&8 constant INT3Addr \ External Interrupt Request 3
+&10 constant INT4Addr \ External Interrupt Request 4
+&12 constant INT5Addr \ External Interrupt Request 5
+&14 constant INT6Addr \ External Interrupt Request 6
+&16 constant INT7Addr \ External Interrupt Request 7
+&18 constant PCINT0Addr \ Pin Change Interrupt Request 0
+&20 constant PCINT1Addr \ Pin Change Interrupt Request 1
+&22 constant USB_GENAddr \ USB General Interrupt Request
+&24 constant USB_COMAddr \ USB Endpoint/Pipe Interrupt Communication Reque
+&26 constant WDTAddr \ Watchdog Time-out Interrupt
+&28 constant TIMER1_CAPTAddr \ Timer/Counter2 Capture Event
+&30 constant TIMER1_COMPAAddr \ Timer/Counter2 Compare Match B
+&32 constant TIMER1_COMPBAddr \ Timer/Counter2 Compare Match B
+&34 constant TIMER1_COMPCAddr \ Timer/Counter2 Compare Match C
+&36 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+&38 constant TIMER0_COMPAAddr \ Timer/Counter0 Compare Match A
+&40 constant TIMER0_COMPBAddr \ Timer/Counter0 Compare Match B
+&42 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
+&44 constant SPI__STCAddr \ SPI Serial Transfer Complete
+&46 constant USART1__RXAddr \ USART1, Rx Complete
+&48 constant USART1__UDREAddr \ USART1 Data register Empty
+&50 constant USART1__TXAddr \ USART1, Tx Complete
+&52 constant ANALOG_COMPAddr \ Analog Comparator
+&54 constant EE_READYAddr \ EEPROM Ready
+&56 constant SPM_READYAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/atmega16u2/device.asm b/amforth-6.5/avr8/devices/atmega16u2/device.asm
new file mode 100644
index 0000000..a70caa8
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega16u2/device.asm
@@ -0,0 +1,113 @@
+; Partname: ATmega16U2
+; generated automatically, do not edit
+
+.nolist
+ .include "m16U2def.inc"
+.list
+
+.equ ramstart = 256
+.equ CELLSIZE = 2
+.macro readflashcell
+ lsl zl
+ rol zh
+ lpm @0, Z+
+ lpm @1, Z+
+.endmacro
+.macro writeflashcell
+ lsl zl
+ rol zh
+.endmacro
+.set WANT_PORTB = 0
+.set WANT_PORTD = 0
+.set WANT_SPI = 0
+.set WANT_BOOT_LOAD = 0
+.set WANT_EEPROM = 0
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_PLL = 0
+.set WANT_USB_DEVICE = 0
+.set WANT_PS2 = 0
+.set WANT_CPU = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_USART1 = 0
+.set WANT_WATCHDOG = 0
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_PORTC = 0
+.equ intvecsize = 2 ; please verify; flash size: 16384 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.org 2
+ rcall isr ; External Interrupt Request 0
+.org 4
+ rcall isr ; External Interrupt Request 1
+.org 6
+ rcall isr ; External Interrupt Request 2
+.org 8
+ rcall isr ; External Interrupt Request 3
+.org 10
+ rcall isr ; External Interrupt Request 4
+.org 12
+ rcall isr ; External Interrupt Request 5
+.org 14
+ rcall isr ; External Interrupt Request 6
+.org 16
+ rcall isr ; External Interrupt Request 7
+.org 18
+ rcall isr ; Pin Change Interrupt Request 0
+.org 20
+ rcall isr ; Pin Change Interrupt Request 1
+.org 22
+ rcall isr ; USB General Interrupt Request
+.org 24
+ rcall isr ; USB Endpoint/Pipe Interrupt Communication Request
+.org 26
+ rcall isr ; Watchdog Time-out Interrupt
+.org 28
+ rcall isr ; Timer/Counter2 Capture Event
+.org 30
+ rcall isr ; Timer/Counter2 Compare Match B
+.org 32
+ rcall isr ; Timer/Counter2 Compare Match B
+.org 34
+ rcall isr ; Timer/Counter2 Compare Match C
+.org 36
+ rcall isr ; Timer/Counter1 Overflow
+.org 38
+ rcall isr ; Timer/Counter0 Compare Match A
+.org 40
+ rcall isr ; Timer/Counter0 Compare Match B
+.org 42
+ rcall isr ; Timer/Counter0 Overflow
+.org 44
+ rcall isr ; SPI Serial Transfer Complete
+.org 46
+ rcall isr ; USART1, Rx Complete
+.org 48
+ rcall isr ; USART1 Data register Empty
+.org 50
+ rcall isr ; USART1, Tx Complete
+.org 52
+ rcall isr ; Analog Comparator
+.org 54
+ rcall isr ; EEPROM Ready
+.org 56
+ rcall isr ; Store Program Memory Read
+.equ INTVECTORS = 29
+.nooverlap
+
+; compatability layer (maybe empty)
+
+; controller data area, environment query mcu-info
+mcu_info:
+mcu_ramsize:
+ .dw 512
+mcu_eepromsize:
+ .dw 512
+mcu_maxdp:
+ .dw 12288
+mcu_numints:
+ .dw 29
+mcu_name:
+ .dw 10
+ .db "ATmega16U2"
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega16u2/device.inc b/amforth-6.5/avr8/devices/atmega16u2/device.inc
new file mode 100644
index 0000000..667ef57
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega16u2/device.inc
@@ -0,0 +1,1155 @@
+; Partname: ATmega16U2
+; generated automatically, no not edit
+
+.if WANT_PORTB == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw 37
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw 36
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw 35
+
+.endif
+.if WANT_PORTD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw 43
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw 42
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw 41
+
+.endif
+.if WANT_SPI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR:
+ .dw $ff04
+ .db "SPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR
+XT_SPCR:
+ .dw PFA_DOVARIABLE
+PFA_SPCR:
+ .dw 76
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR:
+ .dw $ff04
+ .db "SPSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR
+XT_SPSR:
+ .dw PFA_DOVARIABLE
+PFA_SPSR:
+ .dw 77
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR:
+ .dw $ff04
+ .db "SPDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR
+XT_SPDR:
+ .dw PFA_DOVARIABLE
+PFA_SPDR:
+ .dw 78
+
+.endif
+.if WANT_BOOT_LOAD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control Register
+VE_SPMCSR:
+ .dw $ff06
+ .db "SPMCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCSR
+XT_SPMCSR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCSR:
+ .dw 87
+
+.endif
+.if WANT_EEPROM == 1
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Address Register Low Bytes
+VE_EEAR:
+ .dw $ff04
+ .db "EEAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEAR
+XT_EEAR:
+ .dw PFA_DOVARIABLE
+PFA_EEAR:
+ .dw 65
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw 64
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw 63
+
+.endif
+.if WANT_TIMER_COUNTER_0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0B:
+ .dw $ff05
+ .db "OCR0B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0B
+XT_OCR0B:
+ .dw PFA_DOVARIABLE
+PFA_OCR0B:
+ .dw 72
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0A:
+ .dw $ff05
+ .db "OCR0A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0A
+XT_OCR0A:
+ .dw PFA_DOVARIABLE
+PFA_OCR0A:
+ .dw 71
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw 70
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register B
+VE_TCCR0B:
+ .dw $ff06
+ .db "TCCR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0B
+XT_TCCR0B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0B:
+ .dw 69
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register A
+VE_TCCR0A:
+ .dw $ff06
+ .db "TCCR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0A
+XT_TCCR0A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0A:
+ .dw 68
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Mask Register
+VE_TIMSK0:
+ .dw $ff06
+ .db "TIMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK0
+XT_TIMSK0:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK0:
+ .dw 110
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Flag register
+VE_TIFR0:
+ .dw $ff05
+ .db "TIFR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR0
+XT_TIFR0:
+ .dw PFA_DOVARIABLE
+PFA_TIFR0:
+ .dw 53
+; ( -- addr ) System Constant
+; R( -- )
+; General Timer/Counter Control Register
+VE_GTCCR:
+ .dw $ff05
+ .db "GTCCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GTCCR
+XT_GTCCR:
+ .dw PFA_DOVARIABLE
+PFA_GTCCR:
+ .dw 67
+
+.endif
+.if WANT_TIMER_COUNTER_1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw 128
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw 129
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter 1 Control Register C
+VE_TCCR1C:
+ .dw $ff06
+ .db "TCCR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1C
+XT_TCCR1C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1C:
+ .dw 130
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Bytes
+VE_TCNT1:
+ .dw $ff05
+ .db "TCNT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1
+XT_TCNT1:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1:
+ .dw 132
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register A Bytes
+VE_OCR1A:
+ .dw $ff05
+ .db "OCR1A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1A
+XT_OCR1A:
+ .dw PFA_DOVARIABLE
+PFA_OCR1A:
+ .dw 136
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register B Bytes
+VE_OCR1B:
+ .dw $ff05
+ .db "OCR1B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1B
+XT_OCR1B:
+ .dw PFA_DOVARIABLE
+PFA_OCR1B:
+ .dw 138
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register C Bytes
+VE_OCR1C:
+ .dw $ff05
+ .db "OCR1C",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1C
+XT_OCR1C:
+ .dw PFA_DOVARIABLE
+PFA_OCR1C:
+ .dw 140
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Bytes
+VE_ICR1:
+ .dw $ff04
+ .db "ICR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1
+XT_ICR1:
+ .dw PFA_DOVARIABLE
+PFA_ICR1:
+ .dw 134
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Mask Register
+VE_TIMSK1:
+ .dw $ff06
+ .db "TIMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK1
+XT_TIMSK1:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK1:
+ .dw 111
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Flag register
+VE_TIFR1:
+ .dw $ff05
+ .db "TIFR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR1
+XT_TIFR1:
+ .dw PFA_DOVARIABLE
+PFA_TIFR1:
+ .dw 54
+
+.endif
+.if WANT_PLL == 1
+; ( -- addr ) System Constant
+; R( -- )
+; PLL Status and Control register
+VE_PLLCSR:
+ .dw $ff06
+ .db "PLLCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PLLCSR
+XT_PLLCSR:
+ .dw PFA_DOVARIABLE
+PFA_PLLCSR:
+ .dw 73
+
+.endif
+.if WANT_USB_DEVICE == 1
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UEINT:
+ .dw $ff05
+ .db "UEINT",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UEINT
+XT_UEINT:
+ .dw PFA_DOVARIABLE
+PFA_UEINT:
+ .dw 244
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UEBCLX:
+ .dw $ff06
+ .db "UEBCLX"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UEBCLX
+XT_UEBCLX:
+ .dw PFA_DOVARIABLE
+PFA_UEBCLX:
+ .dw 242
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UEDATX:
+ .dw $ff06
+ .db "UEDATX"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UEDATX
+XT_UEDATX:
+ .dw PFA_DOVARIABLE
+PFA_UEDATX:
+ .dw 241
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UEIENX:
+ .dw $ff06
+ .db "UEIENX"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UEIENX
+XT_UEIENX:
+ .dw PFA_DOVARIABLE
+PFA_UEIENX:
+ .dw 240
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UESTA1X:
+ .dw $ff07
+ .db "UESTA1X",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UESTA1X
+XT_UESTA1X:
+ .dw PFA_DOVARIABLE
+PFA_UESTA1X:
+ .dw 239
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UESTA0X:
+ .dw $ff07
+ .db "UESTA0X",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UESTA0X
+XT_UESTA0X:
+ .dw PFA_DOVARIABLE
+PFA_UESTA0X:
+ .dw 238
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UECFG1X:
+ .dw $ff07
+ .db "UECFG1X",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UECFG1X
+XT_UECFG1X:
+ .dw PFA_DOVARIABLE
+PFA_UECFG1X:
+ .dw 237
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UECFG0X:
+ .dw $ff07
+ .db "UECFG0X",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UECFG0X
+XT_UECFG0X:
+ .dw PFA_DOVARIABLE
+PFA_UECFG0X:
+ .dw 236
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UECONX:
+ .dw $ff06
+ .db "UECONX"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UECONX
+XT_UECONX:
+ .dw PFA_DOVARIABLE
+PFA_UECONX:
+ .dw 235
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UERST:
+ .dw $ff05
+ .db "UERST",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UERST
+XT_UERST:
+ .dw PFA_DOVARIABLE
+PFA_UERST:
+ .dw 234
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UENUM:
+ .dw $ff05
+ .db "UENUM",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UENUM
+XT_UENUM:
+ .dw PFA_DOVARIABLE
+PFA_UENUM:
+ .dw 233
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UEINTX:
+ .dw $ff06
+ .db "UEINTX"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UEINTX
+XT_UEINTX:
+ .dw PFA_DOVARIABLE
+PFA_UEINTX:
+ .dw 232
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UDMFN:
+ .dw $ff05
+ .db "UDMFN",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDMFN
+XT_UDMFN:
+ .dw PFA_DOVARIABLE
+PFA_UDMFN:
+ .dw 230
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UDFNUM:
+ .dw $ff06
+ .db "UDFNUM"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDFNUM
+XT_UDFNUM:
+ .dw PFA_DOVARIABLE
+PFA_UDFNUM:
+ .dw 228
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UDADDR:
+ .dw $ff06
+ .db "UDADDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDADDR
+XT_UDADDR:
+ .dw PFA_DOVARIABLE
+PFA_UDADDR:
+ .dw 227
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UDIEN:
+ .dw $ff05
+ .db "UDIEN",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDIEN
+XT_UDIEN:
+ .dw PFA_DOVARIABLE
+PFA_UDIEN:
+ .dw 226
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UDINT:
+ .dw $ff05
+ .db "UDINT",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDINT
+XT_UDINT:
+ .dw PFA_DOVARIABLE
+PFA_UDINT:
+ .dw 225
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UDCON:
+ .dw $ff05
+ .db "UDCON",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDCON
+XT_UDCON:
+ .dw PFA_DOVARIABLE
+PFA_UDCON:
+ .dw 224
+; ( -- addr ) System Constant
+; R( -- )
+; USB General Control Register
+VE_USBCON:
+ .dw $ff06
+ .db "USBCON"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USBCON
+XT_USBCON:
+ .dw PFA_DOVARIABLE
+PFA_USBCON:
+ .dw 216
+; ( -- addr ) System Constant
+; R( -- )
+; Regulator Control Register
+VE_REGCR:
+ .dw $ff05
+ .db "REGCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_REGCR
+XT_REGCR:
+ .dw PFA_DOVARIABLE
+PFA_REGCR:
+ .dw 99
+
+.endif
+.if WANT_PS2 == 1
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UPOE:
+ .dw $ff04
+ .db "UPOE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UPOE
+XT_UPOE:
+ .dw PFA_DOVARIABLE
+PFA_UPOE:
+ .dw 251
+; ( -- addr ) System Constant
+; R( -- )
+; PS2 Pad Enable register
+VE_PS2CON:
+ .dw $ff06
+ .db "PS2CON"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PS2CON
+XT_PS2CON:
+ .dw PFA_DOVARIABLE
+PFA_PS2CON:
+ .dw 250
+
+.endif
+.if WANT_CPU == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw 95
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer
+VE_SP:
+ .dw $ff02
+ .db "SP"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SP
+XT_SP:
+ .dw PFA_DOVARIABLE
+PFA_SP:
+ .dw 93
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw 85
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Status Register
+VE_MCUSR:
+ .dw $ff05
+ .db "MCUSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUSR
+XT_MCUSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUSR:
+ .dw 84
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Calibration Value
+VE_OSCCAL:
+ .dw $ff06
+ .db "OSCCAL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSCCAL
+XT_OSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_OSCCAL:
+ .dw 102
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_CLKPR:
+ .dw $ff05
+ .db "CLKPR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKPR
+XT_CLKPR:
+ .dw PFA_DOVARIABLE
+PFA_CLKPR:
+ .dw 97
+; ( -- addr ) System Constant
+; R( -- )
+; Sleep Mode Control Register
+VE_SMCR:
+ .dw $ff04
+ .db "SMCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SMCR
+XT_SMCR:
+ .dw PFA_DOVARIABLE
+PFA_SMCR:
+ .dw 83
+; ( -- addr ) System Constant
+; R( -- )
+; Extended Indirect Register
+VE_EIND:
+ .dw $ff04
+ .db "EIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIND
+XT_EIND:
+ .dw PFA_DOVARIABLE
+PFA_EIND:
+ .dw 92
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 2
+VE_GPIOR2:
+ .dw $ff06
+ .db "GPIOR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR2
+XT_GPIOR2:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR2:
+ .dw 75
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 1
+VE_GPIOR1:
+ .dw $ff06
+ .db "GPIOR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR1
+XT_GPIOR1:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR1:
+ .dw 74
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 0
+VE_GPIOR0:
+ .dw $ff06
+ .db "GPIOR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR0
+XT_GPIOR0:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR0:
+ .dw 62
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register1
+VE_PRR1:
+ .dw $ff04
+ .db "PRR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR1
+XT_PRR1:
+ .dw PFA_DOVARIABLE
+PFA_PRR1:
+ .dw 101
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register0
+VE_PRR0:
+ .dw $ff04
+ .db "PRR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR0
+XT_PRR0:
+ .dw PFA_DOVARIABLE
+PFA_PRR0:
+ .dw 100
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_CLKSTA:
+ .dw $ff06
+ .db "CLKSTA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKSTA
+XT_CLKSTA:
+ .dw PFA_DOVARIABLE
+PFA_CLKSTA:
+ .dw 210
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_CLKSEL1:
+ .dw $ff07
+ .db "CLKSEL1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKSEL1
+XT_CLKSEL1:
+ .dw PFA_DOVARIABLE
+PFA_CLKSEL1:
+ .dw 209
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_CLKSEL0:
+ .dw $ff07
+ .db "CLKSEL0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKSEL0
+XT_CLKSEL0:
+ .dw PFA_DOVARIABLE
+PFA_CLKSEL0:
+ .dw 208
+; ( -- addr ) System Constant
+; R( -- )
+; debugWire communication register
+VE_DWDR:
+ .dw $ff04
+ .db "DWDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DWDR
+XT_DWDR:
+ .dw PFA_DOVARIABLE
+PFA_DWDR:
+ .dw 81
+
+.endif
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register A
+VE_EICRA:
+ .dw $ff05
+ .db "EICRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRA
+XT_EICRA:
+ .dw PFA_DOVARIABLE
+PFA_EICRA:
+ .dw 105
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register B
+VE_EICRB:
+ .dw $ff05
+ .db "EICRB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRB
+XT_EICRB:
+ .dw PFA_DOVARIABLE
+PFA_EICRB:
+ .dw 106
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Mask Register
+VE_EIMSK:
+ .dw $ff05
+ .db "EIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIMSK
+XT_EIMSK:
+ .dw PFA_DOVARIABLE
+PFA_EIMSK:
+ .dw 61
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Flag Register
+VE_EIFR:
+ .dw $ff04
+ .db "EIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIFR
+XT_EIFR:
+ .dw PFA_DOVARIABLE
+PFA_EIFR:
+ .dw 60
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 0
+VE_PCMSK0:
+ .dw $ff06
+ .db "PCMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK0
+XT_PCMSK0:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK0:
+ .dw 107
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 1
+VE_PCMSK1:
+ .dw $ff06
+ .db "PCMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK1
+XT_PCMSK1:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK1:
+ .dw 108
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Interrupt Flag Register
+VE_PCIFR:
+ .dw $ff05
+ .db "PCIFR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCIFR
+XT_PCIFR:
+ .dw PFA_DOVARIABLE
+PFA_PCIFR:
+ .dw 59
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Interrupt Control Register
+VE_PCICR:
+ .dw $ff05
+ .db "PCICR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCICR
+XT_PCICR:
+ .dw PFA_DOVARIABLE
+PFA_PCICR:
+ .dw 104
+
+.endif
+.if WANT_USART1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR1:
+ .dw $ff04
+ .db "UDR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR1
+XT_UDR1:
+ .dw PFA_DOVARIABLE
+PFA_UDR1:
+ .dw 206
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR1A:
+ .dw $ff06
+ .db "UCSR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1A
+XT_UCSR1A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1A:
+ .dw 200
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR1B:
+ .dw $ff06
+ .db "UCSR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1B
+XT_UCSR1B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1B:
+ .dw 201
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR1C:
+ .dw $ff06
+ .db "UCSR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1C
+XT_UCSR1C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1C:
+ .dw 202
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register D
+VE_UCSR1D:
+ .dw $ff06
+ .db "UCSR1D"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1D
+XT_UCSR1D:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1D:
+ .dw 203
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Bytes
+VE_UBRR1:
+ .dw $ff05
+ .db "UBRR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR1
+XT_UBRR1:
+ .dw PFA_DOVARIABLE
+PFA_UBRR1:
+ .dw 204
+
+.endif
+.if WANT_WATCHDOG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCSR:
+ .dw $ff06
+ .db "WDTCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCSR
+XT_WDTCSR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCSR:
+ .dw 96
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Clock Divider
+VE_WDTCKD:
+ .dw $ff06
+ .db "WDTCKD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCKD
+XT_WDTCKD:
+ .dw PFA_DOVARIABLE
+PFA_WDTCKD:
+ .dw 98
+
+.endif
+.if WANT_ANALOG_COMPARATOR == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Control And Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw 80
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_DIDR1:
+ .dw $ff05
+ .db "DIDR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR1
+XT_DIDR1:
+ .dw PFA_DOVARIABLE
+PFA_DIDR1:
+ .dw 127
+
+.endif
+.if WANT_PORTC == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Register
+VE_PORTC:
+ .dw $ff05
+ .db "PORTC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTC
+XT_PORTC:
+ .dw PFA_DOVARIABLE
+PFA_PORTC:
+ .dw 40
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Direction Register
+VE_DDRC:
+ .dw $ff04
+ .db "DDRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRC
+XT_DDRC:
+ .dw PFA_DOVARIABLE
+PFA_DDRC:
+ .dw 39
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Input Pins
+VE_PINC:
+ .dw $ff04
+ .db "PINC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINC
+XT_PINC:
+ .dw PFA_DOVARIABLE
+PFA_PINC:
+ .dw 38
+
+.endif
diff --git a/amforth-6.5/avr8/devices/atmega16u2/device.py b/amforth-6.5/avr8/devices/atmega16u2/device.py
new file mode 100644
index 0000000..592910d
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega16u2/device.py
@@ -0,0 +1,387 @@
+# Generated Automatically
+
+# Partname ATmega16U2
+
+MCUREGS = {
+# Interrupt Vectors
+ 'INT0Addr' : '#2', # External Interrupt Request 0
+ 'INT1Addr' : '#4', # External Interrupt Request 1
+ 'INT2Addr' : '#6', # External Interrupt Request 2
+ 'INT3Addr' : '#8', # External Interrupt Request 3
+ 'INT4Addr' : '#10', # External Interrupt Request 4
+ 'INT5Addr' : '#12', # External Interrupt Request 5
+ 'INT6Addr' : '#14', # External Interrupt Request 6
+ 'INT7Addr' : '#16', # External Interrupt Request 7
+ 'PCINT0Addr' : '#18', # Pin Change Interrupt Request 0
+ 'PCINT1Addr' : '#20', # Pin Change Interrupt Request 1
+ 'USB_GENAddr' : '#22', # USB General Interrupt Request
+ 'USB_COMAddr' : '#24', # USB Endpoint/Pipe Interrupt Communication Request
+ 'WDTAddr' : '#26', # Watchdog Time-out Interrupt
+ 'TIMER1_CAPTAddr' : '#28', # Timer/Counter2 Capture Event
+ 'TIMER1_COMPAAddr' : '#30', # Timer/Counter2 Compare Match B
+ 'TIMER1_COMPBAddr' : '#32', # Timer/Counter2 Compare Match B
+ 'TIMER1_COMPCAddr' : '#34', # Timer/Counter2 Compare Match C
+ 'TIMER1_OVFAddr' : '#36', # Timer/Counter1 Overflow
+ 'TIMER0_COMPAAddr' : '#38', # Timer/Counter0 Compare Match A
+ 'TIMER0_COMPBAddr' : '#40', # Timer/Counter0 Compare Match B
+ 'TIMER0_OVFAddr' : '#42', # Timer/Counter0 Overflow
+ 'SPI_STCAddr' : '#44', # SPI Serial Transfer Complete
+ 'USART1_RXAddr' : '#46', # USART1, Rx Complete
+ 'USART1_UDREAddr' : '#48', # USART1 Data register Empty
+ 'USART1_TXAddr' : '#50', # USART1, Tx Complete
+ 'ANALOG_COMPAddr' : '#52', # Analog Comparator
+ 'EE_READYAddr' : '#54', # EEPROM Ready
+ 'SPM_READYAddr' : '#56', # Store Program Memory Read
+
+# Module PORTB
+ 'PORTB' : '$25', # Port B Data Register
+ 'DDRB' : '$24', # Port B Data Direction Register
+ 'PINB' : '$23', # Port B Input Pins
+
+# Module PORTD
+ 'PORTD' : '$2b', # Port D Data Register
+ 'DDRD' : '$2a', # Port D Data Direction Register
+ 'PIND' : '$29', # Port D Input Pins
+
+# Module SPI
+ 'SPCR' : '$4c', # SPI Control Register
+ 'SPCR_SPIE': '$80', # SPI Interrupt Enable
+ 'SPCR_SPE': '$40', # SPI Enable
+ 'SPCR_DORD': '$20', # Data Order
+ 'SPCR_MSTR': '$10', # Master/Slave Select
+ 'SPCR_CPOL': '$8', # Clock polarity
+ 'SPCR_CPHA': '$4', # Clock Phase
+ 'SPCR_SPR': '$3', # SPI Clock Rate Selects
+ 'SPSR' : '$4d', # SPI Status Register
+ 'SPSR_SPIF': '$80', # SPI Interrupt Flag
+ 'SPSR_WCOL': '$40', # Write Collision Flag
+ 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
+ 'SPDR' : '$4e', # SPI Data Register
+
+# Module BOOT_LOAD
+ 'SPMCSR' : '$57', # Store Program Memory Control R
+ 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
+ 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
+ 'SPMCSR_SIGRD': '$20', # Signature Row Read
+ 'SPMCSR_RWWSRE': '$10', # Read While Write section read
+ 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
+ 'SPMCSR_PGWRT': '$4', # Page Write
+ 'SPMCSR_PGERS': '$2', # Page Erase
+ 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
+
+# Module EEPROM
+ 'EEAR' : '$41', # EEPROM Address Register Low By
+ 'EEDR' : '$40', # EEPROM Data Register
+ 'EECR' : '$3f', # EEPROM Control Register
+ 'EECR_EEPM': '$30', # EEPROM Programming Mode Bits
+ 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
+ 'EECR_EEMPE': '$4', # EEPROM Master Write Enable
+ 'EECR_EEPE': '$2', # EEPROM Write Enable
+ 'EECR_EERE': '$1', # EEPROM Read Enable
+
+# Module TIMER_COUNTER_0
+ 'OCR0B' : '$48', # Timer/Counter0 Output Compare
+ 'OCR0A' : '$47', # Timer/Counter0 Output Compare
+ 'TCNT0' : '$46', # Timer/Counter0
+ 'TCCR0B' : '$45', # Timer/Counter Control Register
+ 'TCCR0B_FOC0A': '$80', # Force Output Compare A
+ 'TCCR0B_FOC0B': '$40', # Force Output Compare B
+ 'TCCR0B_WGM02': '$8', #
+ 'TCCR0B_CS0': '$7', # Clock Select
+ 'TCCR0A' : '$44', # Timer/Counter Control Registe
+ 'TCCR0A_COM0A': '$c0', # Compare Output Mode, Phase Cor
+ 'TCCR0A_COM0B': '$30', # Compare Output Mode, Fast PWm
+ 'TCCR0A_WGM0': '$3', # Waveform Generation Mode
+ 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
+ 'TIMSK0_OCIE0B': '$4', # Timer/Counter0 Output Compare
+ 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
+ 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
+ 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
+ 'TIFR0_OCF0B': '$4', # Timer/Counter0 Output Compare
+ 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
+ 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSRSYNC': '$1', # Prescaler Reset Timer/Counter1
+
+# Module TIMER_COUNTER_1
+ 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
+ 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
+ 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
+ 'TCCR1A_COM1C': '$c', # Compare Output Mode 1C, bits
+ 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
+ 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
+ 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
+ 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
+ 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
+ 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
+ 'TCCR1C' : '$82', # Timer/Counter 1 Control Regist
+ 'TCCR1C_FOC1A': '$80', # Force Output Compare 1A
+ 'TCCR1C_FOC1B': '$40', # Force Output Compare 1B
+ 'TCCR1C_FOC1C': '$20', # Force Output Compare 1C
+ 'TCNT1' : '$84', # Timer/Counter1 Bytes
+ 'OCR1A' : '$88', # Timer/Counter1 Output Compare
+ 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
+ 'OCR1C' : '$8c', # Timer/Counter1 Output Compare
+ 'ICR1' : '$86', # Timer/Counter1 Input Capture R
+ 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
+ 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
+ 'TIMSK1_OCIE1C': '$8', # Timer/Counter1 Output Compare
+ 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
+ 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
+ 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
+ 'TIFR1' : '$36', # Timer/Counter1 Interrupt Flag
+ 'TIFR1_ICF1': '$20', # Input Capture Flag 1
+ 'TIFR1_OCF1C': '$8', # Output Compare Flag 1C
+ 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
+ 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
+ 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
+
+# Module PLL
+ 'PLLCSR' : '$49', # PLL Status and Control registe
+ 'PLLCSR_PLLP': '$1c', # PLL prescaler Bits
+ 'PLLCSR_PLLE': '$2', # PLL Enable Bit
+ 'PLLCSR_PLOCK': '$1', # PLL Lock Status Bit
+
+# Module USB_DEVICE
+ 'UEINT' : '$f4', #
+ 'UEBCLX' : '$f2', #
+ 'UEDATX' : '$f1', #
+ 'UEIENX' : '$f0', #
+ 'UEIENX_FLERRE': '$80', #
+ 'UEIENX_NAKINE': '$40', #
+ 'UEIENX_NAKOUTE': '$10', #
+ 'UEIENX_RXSTPE': '$8', #
+ 'UEIENX_RXOUTE': '$4', #
+ 'UEIENX_STALLEDE': '$2', #
+ 'UEIENX_TXINE': '$1', #
+ 'UESTA1X' : '$ef', #
+ 'UESTA1X_CTRLDIR': '$4', #
+ 'UESTA1X_CURRBK': '$3', #
+ 'UESTA0X' : '$ee', #
+ 'UESTA0X_CFGOK': '$80', #
+ 'UESTA0X_OVERFI': '$40', #
+ 'UESTA0X_UNDERFI': '$20', #
+ 'UESTA0X_DTSEQ': '$c', #
+ 'UESTA0X_NBUSYBK': '$3', #
+ 'UECFG1X' : '$ed', #
+ 'UECFG1X_EPSIZE': '$70', #
+ 'UECFG1X_EPBK': '$c', #
+ 'UECFG1X_ALLOC': '$2', #
+ 'UECFG0X' : '$ec', #
+ 'UECFG0X_EPTYPE': '$c0', #
+ 'UECFG0X_EPDIR': '$1', #
+ 'UECONX' : '$eb', #
+ 'UECONX_STALLRQ': '$20', #
+ 'UECONX_STALLRQC': '$10', #
+ 'UECONX_RSTDT': '$8', #
+ 'UECONX_EPEN': '$1', #
+ 'UERST' : '$ea', #
+ 'UERST_EPRST': '$1f', #
+ 'UENUM' : '$e9', #
+ 'UEINTX' : '$e8', #
+ 'UEINTX_FIFOCON': '$80', #
+ 'UEINTX_NAKINI': '$40', #
+ 'UEINTX_RWAL': '$20', #
+ 'UEINTX_NAKOUTI': '$10', #
+ 'UEINTX_RXSTPI': '$8', #
+ 'UEINTX_RXOUTI': '$4', #
+ 'UEINTX_STALLEDI': '$2', #
+ 'UEINTX_TXINI': '$1', #
+ 'UDMFN' : '$e6', #
+ 'UDMFN_FNCERR': '$10', #
+ 'UDFNUM' : '$e4', #
+ 'UDADDR' : '$e3', #
+ 'UDADDR_ADDEN': '$80', #
+ 'UDADDR_UADD': '$7f', #
+ 'UDIEN' : '$e2', #
+ 'UDIEN_UPRSME': '$40', #
+ 'UDIEN_EORSME': '$20', #
+ 'UDIEN_WAKEUPE': '$10', #
+ 'UDIEN_EORSTE': '$8', #
+ 'UDIEN_SOFE': '$4', #
+ 'UDIEN_SUSPE': '$1', #
+ 'UDINT' : '$e1', #
+ 'UDINT_UPRSMI': '$40', #
+ 'UDINT_EORSMI': '$20', #
+ 'UDINT_WAKEUPI': '$10', #
+ 'UDINT_EORSTI': '$8', #
+ 'UDINT_SOFI': '$4', #
+ 'UDINT_SUSPI': '$1', #
+ 'UDCON' : '$e0', #
+ 'UDCON_RSTCPU': '$4', #
+ 'UDCON_RMWKUP': '$2', #
+ 'UDCON_DETACH': '$1', #
+ 'USBCON' : '$d8', # USB General Control Register
+ 'USBCON_USBE': '$80', #
+ 'USBCON_FRZCLK': '$20', #
+ 'REGCR' : '$63', # Regulator Control Register
+ 'REGCR_REGDIS': '$1', #
+
+# Module PS2
+ 'UPOE' : '$fb', #
+ 'UPOE_UPWE': '$c0', #
+ 'UPOE_UPDRV': '$30', #
+ 'UPOE_SCKI': '$8', #
+ 'UPOE_DATAI': '$4', #
+ 'UPOE_DPI': '$2', #
+ 'UPOE_DMI': '$1', #
+ 'PS2CON' : '$fa', # PS2 Pad Enable register
+ 'PS2CON_PS2EN': '$1', # Enable
+
+# Module CPU
+ 'SREG' : '$5f', # Status Register
+ 'SREG_I': '$80', # Global Interrupt Enable
+ 'SREG_T': '$40', # Bit Copy Storage
+ 'SREG_H': '$20', # Half Carry Flag
+ 'SREG_S': '$10', # Sign Bit
+ 'SREG_V': '$8', # Two's Complement Overflow Flag
+ 'SREG_N': '$4', # Negative Flag
+ 'SREG_Z': '$2', # Zero Flag
+ 'SREG_C': '$1', # Carry Flag
+ 'SP' : '$5d', # Stack Pointer
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_PUD': '$10', # Pull-up disable
+ 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
+ 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_USBRF': '$20', # USB reset flag
+ 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
+ 'MCUSR_BORF': '$4', # Brown-out Reset Flag
+ 'MCUSR_EXTRF': '$2', # External Reset Flag
+ 'MCUSR_PORF': '$1', # Power-on reset flag
+ 'OSCCAL' : '$66', # Oscillator Calibration Value
+ 'CLKPR' : '$61', #
+ 'CLKPR_CLKPCE': '$80', #
+ 'CLKPR_CLKPS': '$f', #
+ 'SMCR' : '$53', # Sleep Mode Control Register
+ 'SMCR_SM': '$e', # Sleep Mode Select bits
+ 'SMCR_SE': '$1', # Sleep Enable
+ 'EIND' : '$5c', # Extended Indirect Register
+ 'GPIOR2' : '$4b', # General Purpose IO Register 2
+ 'GPIOR2_GPIOR': '$ff', # General Purpose IO Register 2
+ 'GPIOR1' : '$4a', # General Purpose IO Register 1
+ 'GPIOR1_GPIOR': '$ff', # General Purpose IO Register 1
+ 'GPIOR0' : '$3e', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR07': '$80', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR06': '$40', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR05': '$20', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR04': '$10', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR03': '$8', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR02': '$4', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR01': '$2', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR00': '$1', # General Purpose IO Register 0
+ 'PRR1' : '$65', # Power Reduction Register1
+ 'PRR1_PRUSB': '$80', # Power Reduction USB
+ 'PRR1_PRUSART1': '$1', # Power Reduction USART1
+ 'PRR0' : '$64', # Power Reduction Register0
+ 'PRR0_PRTIM0': '$20', # Power Reduction Timer/Counter0
+ 'PRR0_PRTIM1': '$8', # Power Reduction Timer/Counter1
+ 'PRR0_PRSPI': '$4', # Power Reduction Serial Periphe
+ 'CLKSTA' : '$d2', #
+ 'CLKSTA_RCON': '$2', #
+ 'CLKSTA_EXTON': '$1', #
+ 'CLKSEL1' : '$d1', #
+ 'CLKSEL1_RCCKSEL': '$f0', #
+ 'CLKSEL1_EXCKSEL': '$f', #
+ 'CLKSEL0' : '$d0', #
+ 'CLKSEL0_RCSUT': '$c0', #
+ 'CLKSEL0_EXSUT': '$30', #
+ 'CLKSEL0_RCE': '$8', #
+ 'CLKSEL0_EXTE': '$4', #
+ 'CLKSEL0_CLKS': '$1', #
+ 'DWDR' : '$51', # debugWire communication regist
+
+# Module EXTERNAL_INTERRUPT
+ 'EICRA' : '$69', # External Interrupt Control Reg
+ 'EICRA_ISC3': '$c0', # External Interrupt Sense Contr
+ 'EICRA_ISC2': '$30', # External Interrupt Sense Contr
+ 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
+ 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
+ 'EICRB' : '$6a', # External Interrupt Control Reg
+ 'EICRB_ISC7': '$c0', # External Interrupt 7-4 Sense C
+ 'EICRB_ISC6': '$30', # External Interrupt 7-4 Sense C
+ 'EICRB_ISC5': '$c', # External Interrupt 7-4 Sense C
+ 'EICRB_ISC4': '$3', # External Interrupt 7-4 Sense C
+ 'EIMSK' : '$3d', # External Interrupt Mask Regist
+ 'EIMSK_INT': '$ff', # External Interrupt Request 7 E
+ 'EIFR' : '$3c', # External Interrupt Flag Regist
+ 'EIFR_INTF': '$ff', # External Interrupt Flags
+ 'PCMSK0' : '$6b', # Pin Change Mask Register 0
+ 'PCMSK0_PCINT': '$ff', # Pin Change Enable Masks
+ 'PCMSK1' : '$6c', # Pin Change Mask Register 1
+ 'PCMSK1_PCINT': '$1f', #
+ 'PCIFR' : '$3b', # Pin Change Interrupt Flag Regi
+ 'PCIFR_PCIF': '$3', # Pin Change Interrupt Flags
+ 'PCICR' : '$68', # Pin Change Interrupt Control R
+ 'PCICR_PCIE': '$3', # Pin Change Interrupt Enables
+
+# Module USART1
+ 'UDR1' : '$ce', # USART I/O Data Register
+ 'UCSR1A' : '$c8', # USART Control and Status Regis
+ 'UCSR1A_RXC1': '$80', # USART Receive Complete
+ 'UCSR1A_TXC1': '$40', # USART Transmitt Complete
+ 'UCSR1A_UDRE1': '$20', # USART Data Register Empty
+ 'UCSR1A_FE1': '$10', # Framing Error
+ 'UCSR1A_DOR1': '$8', # Data overRun
+ 'UCSR1A_UPE1': '$4', # Parity Error
+ 'UCSR1A_U2X1': '$2', # Double the USART transmission
+ 'UCSR1A_MPCM1': '$1', # Multi-processor Communication
+ 'UCSR1B' : '$c9', # USART Control and Status Regis
+ 'UCSR1B_RXCIE1': '$80', # RX Complete Interrupt Enable
+ 'UCSR1B_TXCIE1': '$40', # TX Complete Interrupt Enable
+ 'UCSR1B_UDRIE1': '$20', # USART Data register Empty Inte
+ 'UCSR1B_RXEN1': '$10', # Receiver Enable
+ 'UCSR1B_TXEN1': '$8', # Transmitter Enable
+ 'UCSR1B_UCSZ12': '$4', # Character Size
+ 'UCSR1B_RXB81': '$2', # Receive Data Bit 8
+ 'UCSR1B_TXB81': '$1', # Transmit Data Bit 8
+ 'UCSR1C' : '$ca', # USART Control and Status Regis
+ 'UCSR1C_UMSEL1': '$c0', # USART Mode Select
+ 'UCSR1C_UPM1': '$30', # Parity Mode Bits
+ 'UCSR1C_USBS1': '$8', # Stop Bit Select
+ 'UCSR1C_UCSZ1': '$6', # Character Size
+ 'UCSR1C_UCPOL1': '$1', # Clock Polarity
+ 'UCSR1D' : '$cb', # USART Control and Status Regis
+ 'UCSR1D_CTSEN': '$2', # CTS Enable
+ 'UCSR1D_RTSEN': '$1', # RTS Enable
+ 'UBRR1' : '$cc', # USART Baud Rate Register Byte
+
+# Module WATCHDOG
+ 'WDTCSR' : '$60', # Watchdog Timer Control Registe
+ 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
+ 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
+ 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
+ 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
+ 'WDTCSR_WDE': '$8', # Watch Dog Enable
+ 'WDTCKD' : '$62', # Watchdog Timer Clock Divider
+ 'WDTCKD_WDEWIF': '$8', # Watchdog Early Warning Interru
+ 'WDTCKD_WDEWIE': '$4', # Watchdog Early Warning Interru
+ 'WDTCKD_WCLKD': '$3', # Watchdog Timer Clock Dividers
+
+# Module ANALOG_COMPARATOR
+ 'ACSR' : '$50', # Analog Comparator Control And
+ 'ACSR_ACD': '$80', # Analog Comparator Disable
+ 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
+ 'ACSR_ACO': '$20', # Analog Compare Output
+ 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
+ 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
+ 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
+ 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
+ 'DIDR1' : '$7f', #
+ 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
+ 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
+
+# Module PORTC
+ 'PORTC' : '$28', # Port C Data Register
+ 'PORTC_PORTC': '$f0', # Port C Data Register bits
+ 'PORTC_PORTC': '$7', # Port C Data Register bits
+ 'DDRC' : '$27', # Port C Data Direction Register
+ 'DDRC_DDC': '$f0', # Port C Data Direction Register
+ 'DDRC_DDC': '$7', # Port C Data Direction Register
+ 'PINC' : '$26', # Port C Input Pins
+ 'PINC_PINC': '$f0', # Port C Input Pins bits
+ 'PINC_PINC': '$7', # Port C Input Pins bits
+
+ '__amforth_dummy':'0'
+}
diff --git a/amforth-6.5/avr8/devices/atmega16u2/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega16u2/words/no-jtag.asm
new file mode 100644
index 0000000..352a4bb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega16u2/words/no-jtag.asm
@@ -0,0 +1,14 @@
+; ( -- )
+; ( -- )
+; MCU
+; disable jtag at runtime
+VE_NOJTAG:
+ .dw $FF05
+ .db "-jtag",0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOJTAG
+XT_NOJTAG:
+ .dw PFA_NOJTAG
+PFA_NOJTAG:
+
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega16u2/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega16u2/words/no-wdt.asm
new file mode 100644
index 0000000..ff6ddd1
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega16u2/words/no-wdt.asm
@@ -0,0 +1,34 @@
+; ( -- )
+; MCU
+; disable watch dog timer at runtime
+VE_NOWDT:
+ .dw $ff04
+ .db "-wdt"
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOWDT
+XT_NOWDT:
+ .dw PFA_NOWDT
+PFA_NOWDT:
+
+ in temp1,SREG
+ push temp1
+ ; Turn always off global interrupt.
+ cli
+ ; Reset Watchdog Timer
+ wdr
+ ; Clear WDRF in MCUSR
+ in temp1, MCUSR
+ andi temp1, (0xff & (0<<WDRF))
+ out MCUSR, temp1
+ ; Write logical one to WDCE and WDE
+ ; Keep old prescaler setting to prevent unintentional time-out
+ in_ temp1, WDTCSR
+ ori temp1, (1<<WDCE) | (1<<WDE)
+ out_ WDTCSR, temp1
+ ; Turn off WDT
+ ldi temp1, (0<<WDE)
+ out_ WDTCSR, temp1
+ ; restore status register
+ pop temp1
+ out SREG,temp1
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega16u2/words/sleep.asm b/amforth-6.5/avr8/devices/atmega16u2/words/sleep.asm
new file mode 100644
index 0000000..256249c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega16u2/words/sleep.asm
@@ -0,0 +1,19 @@
+; ( mode -- )
+; MCU
+; put the controller into the specified sleep mode
+VE_SLEEP:
+ .dw $ff05
+ .db "sleep", 0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_SLEEP
+XT_SLEEP:
+ .dw PFA_SLEEP
+PFA_SLEEP:
+ andi tosl, 7 ; leave only legal mode bits
+ lsl tosl ; move to correct location (bits 3-1)
+ ori tosl, 1 ; set the SE bit
+ out_ SMCR, tosl ; set the sleep config
+ sleep ; nighty-night
+ out_ SMCR, zerol ; 0 protects against accidental sleeps
+ loadtos ; pop argument from stack
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega16u4/atmega16u4.frt b/amforth-6.5/avr8/devices/atmega16u4/atmega16u4.frt
new file mode 100644
index 0000000..44c50e1
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega16u4/atmega16u4.frt
@@ -0,0 +1,496 @@
+\ Partname: ATmega16U4
+\ generated automatically
+
+\ WATCHDOG
+&96 constant WDTCSR \ Watchdog Timer Control Register
+ $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Flag
+ $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Enable
+ $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
+ $10 constant WDTCSR_WDCE \ Watchdog Change Enable
+ $08 constant WDTCSR_WDE \ Watch Dog Enable
+\ PORTD
+&43 constant PORTD \ Port D Data Register
+&42 constant DDRD \ Port D Data Direction Register
+&41 constant PIND \ Port D Input Pins
+\ SPI
+&76 constant SPCR \ SPI Control Register
+ $80 constant SPCR_SPIE \ SPI Interrupt Enable
+ $40 constant SPCR_SPE \ SPI Enable
+ $20 constant SPCR_DORD \ Data Order
+ $10 constant SPCR_MSTR \ Master/Slave Select
+ $08 constant SPCR_CPOL \ Clock polarity
+ $04 constant SPCR_CPHA \ Clock Phase
+ $03 constant SPCR_SPR \ SPI Clock Rate Selects
+&77 constant SPSR \ SPI Status Register
+ $80 constant SPSR_SPIF \ SPI Interrupt Flag
+ $40 constant SPSR_WCOL \ Write Collision Flag
+ $01 constant SPSR_SPI2X \ Double SPI Speed Bit
+&78 constant SPDR \ SPI Data Register
+\ USART1
+&206 constant UDR1 \ USART I/O Data Register
+&200 constant UCSR1A \ USART Control and Status Register A
+ $80 constant UCSR1A_RXC1 \ USART Receive Complete
+ $40 constant UCSR1A_TXC1 \ USART Transmitt Complete
+ $20 constant UCSR1A_UDRE1 \ USART Data Register Empty
+ $10 constant UCSR1A_FE1 \ Framing Error
+ $08 constant UCSR1A_DOR1 \ Data overRun
+ $04 constant UCSR1A_UPE1 \ Parity Error
+ $02 constant UCSR1A_U2X1 \ Double the USART transmission speed
+ $01 constant UCSR1A_MPCM1 \ Multi-processor Communication Mode
+&201 constant UCSR1B \ USART Control and Status Register B
+ $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable
+ $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable
+ $20 constant UCSR1B_UDRIE1 \ USART Data register Empty Interrupt Enable
+ $10 constant UCSR1B_RXEN1 \ Receiver Enable
+ $08 constant UCSR1B_TXEN1 \ Transmitter Enable
+ $04 constant UCSR1B_UCSZ12 \ Character Size
+ $02 constant UCSR1B_RXB81 \ Receive Data Bit 8
+ $01 constant UCSR1B_TXB81 \ Transmit Data Bit 8
+&202 constant UCSR1C \ USART Control and Status Register C
+ $C0 constant UCSR1C_UMSEL1 \ USART Mode Select
+ $30 constant UCSR1C_UPM1 \ Parity Mode Bits
+ $08 constant UCSR1C_USBS1 \ Stop Bit Select
+ $06 constant UCSR1C_UCSZ1 \ Character Size
+ $01 constant UCSR1C_UCPOL1 \ Clock Polarity
+&204 constant UBRR1 \ USART Baud Rate Register Bytes
+\ BOOT_LOAD
+&87 constant SPMCSR \ Store Program Memory Control Register
+ $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
+ $20 constant SPMCSR_SIGRD \ Signature Row Read
+ $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
+ $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
+ $04 constant SPMCSR_PGWRT \ Page Write
+ $02 constant SPMCSR_PGERS \ Page Erase
+ $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
+\ EEPROM
+&65 constant EEAR \ EEPROM Address Register Low Bytes
+&64 constant EEDR \ EEPROM Data Register
+&63 constant EECR \ EEPROM Control Register
+ $30 constant EECR_EEPM \ EEPROM Programming Mode Bits
+ $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
+ $04 constant EECR_EEMPE \ EEPROM Master Write Enable
+ $02 constant EECR_EEPE \ EEPROM Write Enable
+ $01 constant EECR_EERE \ EEPROM Read Enable
+\ TIMER_COUNTER_0
+&72 constant OCR0B \ Timer/Counter0 Output Compare Register
+&71 constant OCR0A \ Timer/Counter0 Output Compare Register
+&70 constant TCNT0 \ Timer/Counter0
+&69 constant TCCR0B \ Timer/Counter Control Register B
+ $80 constant TCCR0B_FOC0A \ Force Output Compare A
+ $40 constant TCCR0B_FOC0B \ Force Output Compare B
+ $08 constant TCCR0B_WGM02 \
+ $07 constant TCCR0B_CS0 \ Clock Select
+&68 constant TCCR0A \ Timer/Counter Control Register A
+ $C0 constant TCCR0A_COM0A \ Compare Output Mode, Phase Correct PWM Mode
+ $30 constant TCCR0A_COM0B \ Compare Output Mode, Fast PWm
+ $03 constant TCCR0A_WGM0 \ Waveform Generation Mode
+&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
+ $04 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare Match B Interrupt Enable
+ $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match A Interrupt Enable
+ $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
+&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
+ $04 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare Flag 0B
+ $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0A
+ $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
+&67 constant GTCCR \ General Timer/Counter Control Register
+ $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
+ $01 constant GTCCR_PSRSYNC \ Prescaler Reset Timer/Counter1 and Timer/Counter0
+\ TIMER_COUNTER_3
+&144 constant TCCR3A \ Timer/Counter3 Control Register A
+ $C0 constant TCCR3A_COM3A \ Compare Output Mode 1A, bits
+ $30 constant TCCR3A_COM3B \ Compare Output Mode 3B, bits
+ $0C constant TCCR3A_COM3C \ Compare Output Mode 3C, bits
+ $03 constant TCCR3A_WGM3 \ Waveform Generation Mode
+&145 constant TCCR3B \ Timer/Counter3 Control Register B
+ $80 constant TCCR3B_ICNC3 \ Input Capture 3 Noise Canceler
+ $40 constant TCCR3B_ICES3 \ Input Capture 3 Edge Select
+ $18 constant TCCR3B_WGM3 \ Waveform Generation Mode
+ $07 constant TCCR3B_CS3 \ Prescaler source of Timer/Counter 3
+&146 constant TCCR3C \ Timer/Counter 3 Control Register C
+ $80 constant TCCR3C_FOC3A \ Force Output Compare 3A
+ $40 constant TCCR3C_FOC3B \ Force Output Compare 3B
+ $20 constant TCCR3C_FOC3C \ Force Output Compare 3C
+&148 constant TCNT3 \ Timer/Counter3 Bytes
+&152 constant OCR3A \ Timer/Counter3 Output Compare Register A Bytes
+&154 constant OCR3B \ Timer/Counter3 Output Compare Register B Bytes
+&156 constant OCR3C \ Timer/Counter3 Output Compare Register B Bytes
+&150 constant ICR3 \ Timer/Counter3 Input Capture Register Bytes
+&113 constant TIMSK3 \ Timer/Counter3 Interrupt Mask Register
+ $20 constant TIMSK3_ICIE3 \ Timer/Counter3 Input Capture Interrupt Enable
+ $08 constant TIMSK3_OCIE3C \ Timer/Counter3 Output Compare C Match Interrupt Enable
+ $04 constant TIMSK3_OCIE3B \ Timer/Counter3 Output Compare B Match Interrupt Enable
+ $02 constant TIMSK3_OCIE3A \ Timer/Counter3 Output Compare A Match Interrupt Enable
+ $01 constant TIMSK3_TOIE3 \ Timer/Counter3 Overflow Interrupt Enable
+&56 constant TIFR3 \ Timer/Counter3 Interrupt Flag register
+ $20 constant TIFR3_ICF3 \ Input Capture Flag 3
+ $08 constant TIFR3_OCF3C \ Output Compare Flag 3C
+ $04 constant TIFR3_OCF3B \ Output Compare Flag 3B
+ $02 constant TIFR3_OCF3A \ Output Compare Flag 3A
+ $01 constant TIFR3_TOV3 \ Timer/Counter3 Overflow Flag
+\ TIMER_COUNTER_1
+&128 constant TCCR1A \ Timer/Counter1 Control Register A
+ $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
+ $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
+ $0C constant TCCR1A_COM1C \ Compare Output Mode 1C, bits
+ $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
+&129 constant TCCR1B \ Timer/Counter1 Control Register B
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
+ $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
+&130 constant TCCR1C \ Timer/Counter 1 Control Register C
+ $80 constant TCCR1C_FOC1A \ Force Output Compare 1A
+ $40 constant TCCR1C_FOC1B \ Force Output Compare 1B
+ $20 constant TCCR1C_FOC1C \ Force Output Compare 1C
+&132 constant TCNT1 \ Timer/Counter1 Bytes
+&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
+&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
+&140 constant OCR1C \ Timer/Counter1 Output Compare Register C Bytes
+&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
+&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
+ $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
+ $08 constant TIMSK1_OCIE1C \ Timer/Counter1 Output Compare C Match Interrupt Enable
+ $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
+ $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
+ $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
+&54 constant TIFR1 \ Timer/Counter1 Interrupt Flag register
+ $20 constant TIFR1_ICF1 \ Input Capture Flag 1
+ $08 constant TIFR1_OCF1C \ Output Compare Flag 1C
+ $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
+ $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
+ $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
+\ JTAG
+&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
+&85 constant MCUCR \ MCU Control Register
+ $80 constant MCUCR_JTD \ JTAG Interface Disable
+&84 constant MCUSR \ MCU Status Register
+ $10 constant MCUSR_JTRF \ JTAG Reset Flag
+\ EXTERNAL_INTERRUPT
+&105 constant EICRA \ External Interrupt Control Register A
+ $C0 constant EICRA_ISC3 \ External Interrupt Sense Control Bit
+ $30 constant EICRA_ISC2 \ External Interrupt Sense Control Bit
+ $0C constant EICRA_ISC1 \ External Interrupt Sense Control Bit
+ $03 constant EICRA_ISC0 \ External Interrupt Sense Control Bit
+&106 constant EICRB \ External Interrupt Control Register B
+ $C0 constant EICRB_ISC7 \ External Interrupt 7-4 Sense Control Bit
+ $30 constant EICRB_ISC6 \ External Interrupt 7-4 Sense Control Bit
+ $0C constant EICRB_ISC5 \ External Interrupt 7-4 Sense Control Bit
+ $03 constant EICRB_ISC4 \ External Interrupt 7-4 Sense Control Bit
+&61 constant EIMSK \ External Interrupt Mask Register
+ $FF constant EIMSK_INT \ External Interrupt Request 7 Enable
+&60 constant EIFR \ External Interrupt Flag Register
+ $FF constant EIFR_INTF \ External Interrupt Flags
+&107 constant PCMSK0 \ Pin Change Mask Register 0
+&59 constant PCIFR \ Pin Change Interrupt Flag Register
+ $01 constant PCIFR_PCIF0 \ Pin Change Interrupt Flag 0
+&104 constant PCICR \ Pin Change Interrupt Control Register
+ $01 constant PCICR_PCIE0 \ Pin Change Interrupt Enable 0
+\ TIMER_COUNTER_4
+&192 constant TCCR4A \ Timer/Counter4 Control Register A
+ $C0 constant TCCR4A_COM4A \ Compare Output Mode 1A, bits
+ $30 constant TCCR4A_COM4B \ Compare Output Mode 4B, bits
+ $08 constant TCCR4A_FOC4A \ Force Output Compare Match 4A
+ $04 constant TCCR4A_FOC4B \ Force Output Compare Match 4B
+ $02 constant TCCR4A_PWM4A \
+ $01 constant TCCR4A_PWM4B \
+&193 constant TCCR4B \ Timer/Counter4 Control Register B
+ $80 constant TCCR4B_PWM4X \ PWM Inversion Mode
+ $40 constant TCCR4B_PSR4 \ Prescaler Reset Timer/Counter 4
+ $30 constant TCCR4B_DTPS4 \ Dead Time Prescaler Bits
+ $0F constant TCCR4B_CS4 \ Clock Select Bits
+&194 constant TCCR4C \ Timer/Counter 4 Control Register C
+ $80 constant TCCR4C_COM4A1S \ Comparator A Output Mode
+ $40 constant TCCR4C_COM4A0S \ Comparator A Output Mode
+ $20 constant TCCR4C_COM4B1S \ Comparator B Output Mode
+ $10 constant TCCR4C_COM4B0S \ Comparator B Output Mode
+ $0C constant TCCR4C_COM4D \ Comparator D Output Mode
+ $02 constant TCCR4C_FOC4D \ Force Output Compare Match 4D
+ $01 constant TCCR4C_PWM4D \ Pulse Width Modulator D Enable
+&195 constant TCCR4D \ Timer/Counter 4 Control Register D
+ $80 constant TCCR4D_FPIE4 \ Fault Protection Interrupt Enable
+ $40 constant TCCR4D_FPEN4 \ Fault Protection Mode Enable
+ $20 constant TCCR4D_FPNC4 \ Fault Protection Noise Canceler
+ $10 constant TCCR4D_FPES4 \ Fault Protection Edge Select
+ $08 constant TCCR4D_FPAC4 \ Fault Protection Analog Comparator Enable
+ $04 constant TCCR4D_FPF4 \ Fault Protection Interrupt Flag
+ $03 constant TCCR4D_WGM4 \ Waveform Generation Mode bits
+&196 constant TCCR4E \ Timer/Counter 4 Control Register E
+ $80 constant TCCR4E_TLOCK4 \ Register Update Lock
+ $40 constant TCCR4E_ENHC4 \ Enhanced Compare/PWM Mode
+ $3F constant TCCR4E_OC4OE \ Output Compare Override Enable bit
+&190 constant TCNT4 \ Timer/Counter4 Low Bytes
+&191 constant TC4H \ Timer/Counter4
+&207 constant OCR4A \ Timer/Counter4 Output Compare Register A
+&208 constant OCR4B \ Timer/Counter4 Output Compare Register B
+&209 constant OCR4C \ Timer/Counter4 Output Compare Register C
+&210 constant OCR4D \ Timer/Counter4 Output Compare Register D
+&114 constant TIMSK4 \ Timer/Counter4 Interrupt Mask Register
+ $80 constant TIMSK4_OCIE4D \ Timer/Counter4 Output Compare D Match Interrupt Enable
+ $40 constant TIMSK4_OCIE4A \ Timer/Counter4 Output Compare A Match Interrupt Enable
+ $20 constant TIMSK4_OCIE4B \ Timer/Counter4 Output Compare B Match Interrupt Enable
+ $04 constant TIMSK4_TOIE4 \ Timer/Counter4 Overflow Interrupt Enable
+&57 constant TIFR4 \ Timer/Counter4 Interrupt Flag register
+ $80 constant TIFR4_OCF4D \ Output Compare Flag 4D
+ $40 constant TIFR4_OCF4A \ Output Compare Flag 4A
+ $20 constant TIFR4_OCF4B \ Output Compare Flag 4B
+ $04 constant TIFR4_TOV4 \ Timer/Counter4 Overflow Flag
+&212 constant DT4 \ Timer/Counter 4 Dead Time Value
+ $FF constant DT4_DT4L \ Timer/Counter 4 Dead Time Value Bits
+\ PORTB
+&37 constant PORTB \ Port B Data Register
+&36 constant DDRB \ Port B Data Direction Register
+&35 constant PINB \ Port B Input Pins
+\ PORTC
+&40 constant PORTC \ Port C Data Register
+&39 constant DDRC \ Port C Data Direction Register
+&38 constant PINC \ Port C Input Pins
+\ PORTE
+&46 constant PORTE \ Data Register, Port E
+&45 constant DDRE \ Data Direction Register, Port E
+&44 constant PINE \ Input Pins, Port E
+\ PORTF
+&49 constant PORTF \ Data Register, Port F
+&48 constant DDRF \ Data Direction Register, Port F
+&47 constant PINF \ Input Pins, Port F
+\ AD_CONVERTER
+&124 constant ADMUX \ The ADC multiplexer Selection Register
+ $C0 constant ADMUX_REFS \ Reference Selection Bits
+ $20 constant ADMUX_ADLAR \ Left Adjust Result
+ $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
+&122 constant ADCSRA \ The ADC Control and Status register
+ $80 constant ADCSRA_ADEN \ ADC Enable
+ $40 constant ADCSRA_ADSC \ ADC Start Conversion
+ $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
+ $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
+ $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
+ $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
+&120 constant ADC \ ADC Data Register Bytes
+&123 constant ADCSRB \ ADC Control and Status Register B
+ $80 constant ADCSRB_ADHSM \ ADC High Speed Mode
+ $20 constant ADCSRB_MUX5 \ Analog Channel and Gain Selection Bits
+ $17 constant ADCSRB_ADTS \ ADC Auto Trigger Sources
+&126 constant DIDR0 \ Digital Input Disable Register 1
+ $80 constant DIDR0_ADC7D \ ADC7 Digital input Disable
+ $40 constant DIDR0_ADC6D \ ADC6 Digital input Disable
+ $20 constant DIDR0_ADC5D \ ADC5 Digital input Disable
+ $10 constant DIDR0_ADC4D \ ADC4 Digital input Disable
+ $08 constant DIDR0_ADC3D \ ADC3 Digital input Disable
+ $04 constant DIDR0_ADC2D \ ADC2 Digital input Disable
+ $02 constant DIDR0_ADC1D \ ADC1 Digital input Disable
+ $01 constant DIDR0_ADC0D \ ADC0 Digital input Disable
+&125 constant DIDR2 \ Digital Input Disable Register 1
+ $20 constant DIDR2_ADC13D \ ADC13 Digital input Disable
+ $10 constant DIDR2_ADC12D \ ADC12 Digital input Disable
+ $08 constant DIDR2_ADC11D \ ADC11 Digital input Disable
+ $04 constant DIDR2_ADC10D \ ADC10 Digital input Disable
+ $02 constant DIDR2_ADC9D \ ADC9 Digital input Disable
+ $01 constant DIDR2_ADC8D \ ADC8 Digital input Disable
+\ ANALOG_COMPARATOR
+&80 constant ACSR \ Analog Comparator Control And Status Register
+ $80 constant ACSR_ACD \ Analog Comparator Disable
+ $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
+ $20 constant ACSR_ACO \ Analog Compare Output
+ $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
+ $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
+ $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
+ $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
+&127 constant DIDR1 \
+ $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
+ $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
+\ CPU
+&95 constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ $08 constant SREG_V \ Two's Complement Overflow Flag
+ $04 constant SREG_N \ Negative Flag
+ $02 constant SREG_Z \ Zero Flag
+ $01 constant SREG_C \ Carry Flag
+&93 constant SP \ Stack Pointer
+&102 constant OSCCAL \ Oscillator Calibration Value
+&103 constant RCCTRL \ Oscillator Control Register
+ $01 constant RCCTRL_RCFREQ \
+&97 constant CLKPR \
+ $80 constant CLKPR_CLKPCE \
+ $0F constant CLKPR_CLKPS \
+&83 constant SMCR \ Sleep Mode Control Register
+ $0E constant SMCR_SM \ Sleep Mode Select bits
+ $01 constant SMCR_SE \ Sleep Enable
+&92 constant EIND \ Extended Indirect Register
+&75 constant GPIOR2 \ General Purpose IO Register 2
+ $FF constant GPIOR2_GPIOR \ General Purpose IO Register 2 bis
+&74 constant GPIOR1 \ General Purpose IO Register 1
+ $FF constant GPIOR1_GPIOR \ General Purpose IO Register 1 bis
+&62 constant GPIOR0 \ General Purpose IO Register 0
+ $80 constant GPIOR0_GPIOR07 \ General Purpose IO Register 0 bit 7
+ $40 constant GPIOR0_GPIOR06 \ General Purpose IO Register 0 bit 6
+ $20 constant GPIOR0_GPIOR05 \ General Purpose IO Register 0 bit 5
+ $10 constant GPIOR0_GPIOR04 \ General Purpose IO Register 0 bit 4
+ $08 constant GPIOR0_GPIOR03 \ General Purpose IO Register 0 bit 3
+ $04 constant GPIOR0_GPIOR02 \ General Purpose IO Register 0 bit 2
+ $02 constant GPIOR0_GPIOR01 \ General Purpose IO Register 0 bit 1
+ $01 constant GPIOR0_GPIOR00 \ General Purpose IO Register 0 bit 0
+&101 constant PRR1 \ Power Reduction Register1
+ $80 constant PRR1_PRUSB \ Power Reduction USB
+ $08 constant PRR1_PRTIM3 \ Power Reduction Timer/Counter3
+ $01 constant PRR1_PRUSART1 \ Power Reduction USART1
+&100 constant PRR0 \ Power Reduction Register0
+ $80 constant PRR0_PRTWI \ Power Reduction TWI
+ $40 constant PRR0_PRTIM2 \ Power Reduction Timer/Counter2
+ $20 constant PRR0_PRTIM0 \ Power Reduction Timer/Counter0
+ $08 constant PRR0_PRTIM1 \ Power Reduction Timer/Counter1
+ $04 constant PRR0_PRSPI \ Power Reduction Serial Peripheral Interface
+ $02 constant PRR0_PRUSART0 \ Power Reduction USART
+ $01 constant PRR0_PRADC \ Power Reduction ADC
+&199 constant CLKSTA \
+ $02 constant CLKSTA_RCON \
+ $01 constant CLKSTA_EXTON \
+&198 constant CLKSEL1 \
+ $F0 constant CLKSEL1_RCCKSEL \
+ $0F constant CLKSEL1_EXCKSEL \
+&197 constant CLKSEL0 \
+ $C0 constant CLKSEL0_RCSUT \
+ $30 constant CLKSEL0_EXSUT \
+ $08 constant CLKSEL0_RCE \
+ $04 constant CLKSEL0_EXTE \
+ $01 constant CLKSEL0_CLKS \
+\ PLL
+&73 constant PLLCSR \ PLL Status and Control register
+ $10 constant PLLCSR_PINDIV \ PLL prescaler Bit 2
+ $02 constant PLLCSR_PLLE \ PLL Enable Bit
+ $01 constant PLLCSR_PLOCK \ PLL Lock Status Bit
+&82 constant PLLFRQ \ PLL Frequency Control Register
+ $80 constant PLLFRQ_PINMUX \
+ $40 constant PLLFRQ_PLLUSB \
+ $30 constant PLLFRQ_PLLTM \
+ $0F constant PLLFRQ_PDIV \
+\ USB_DEVICE
+&244 constant UEINT \
+&243 constant UEBCHX \
+&242 constant UEBCLX \
+&241 constant UEDATX \
+ $FF constant UEDATX_DAT \
+&240 constant UEIENX \
+ $80 constant UEIENX_FLERRE \
+ $40 constant UEIENX_NAKINE \
+ $10 constant UEIENX_NAKOUTE \
+ $08 constant UEIENX_RXSTPE \
+ $04 constant UEIENX_RXOUTE \
+ $02 constant UEIENX_STALLEDE \
+ $01 constant UEIENX_TXINE \
+&239 constant UESTA1X \
+ $04 constant UESTA1X_CTRLDIR \
+ $03 constant UESTA1X_CURRBK \
+&238 constant UESTA0X \
+ $80 constant UESTA0X_CFGOK \
+ $40 constant UESTA0X_OVERFI \
+ $20 constant UESTA0X_UNDERFI \
+ $0C constant UESTA0X_DTSEQ \
+ $03 constant UESTA0X_NBUSYBK \
+&237 constant UECFG1X \
+ $70 constant UECFG1X_EPSIZE \
+ $0C constant UECFG1X_EPBK \
+ $02 constant UECFG1X_ALLOC \
+&236 constant UECFG0X \
+ $C0 constant UECFG0X_EPTYPE \
+ $01 constant UECFG0X_EPDIR \
+&235 constant UECONX \
+ $20 constant UECONX_STALLRQ \
+ $10 constant UECONX_STALLRQC \
+ $08 constant UECONX_RSTDT \
+ $01 constant UECONX_EPEN \
+&234 constant UERST \
+ $7F constant UERST_EPRST \
+&233 constant UENUM \
+&232 constant UEINTX \
+ $80 constant UEINTX_FIFOCON \
+ $40 constant UEINTX_NAKINI \
+ $20 constant UEINTX_RWAL \
+ $10 constant UEINTX_NAKOUTI \
+ $08 constant UEINTX_RXSTPI \
+ $04 constant UEINTX_RXOUTI \
+ $02 constant UEINTX_STALLEDI \
+ $01 constant UEINTX_TXINI \
+&230 constant UDMFN \
+ $10 constant UDMFN_FNCERR \
+&228 constant UDFNUM \
+&227 constant UDADDR \
+ $80 constant UDADDR_ADDEN \
+ $7F constant UDADDR_UADD \
+&226 constant UDIEN \
+ $40 constant UDIEN_UPRSME \
+ $20 constant UDIEN_EORSME \
+ $10 constant UDIEN_WAKEUPE \
+ $08 constant UDIEN_EORSTE \
+ $04 constant UDIEN_SOFE \
+ $01 constant UDIEN_SUSPE \
+&225 constant UDINT \
+ $40 constant UDINT_UPRSMI \
+ $20 constant UDINT_EORSMI \
+ $10 constant UDINT_WAKEUPI \
+ $08 constant UDINT_EORSTI \
+ $04 constant UDINT_SOFI \
+ $01 constant UDINT_SUSPI \
+&224 constant UDCON \
+ $04 constant UDCON_LSM \ USB low speed mode
+ $08 constant UDCON_RSTCPU \
+ $02 constant UDCON_RMWKUP \
+ $01 constant UDCON_DETACH \
+&216 constant USBCON \ USB General Control Register
+ $80 constant USBCON_USBE \
+ $20 constant USBCON_FRZCLK \
+ $10 constant USBCON_OTGPADE \
+ $01 constant USBCON_VBUSTE \
+&218 constant USBINT \
+ $01 constant USBINT_VBUSTI \
+&217 constant USBSTA \
+ $08 constant USBSTA_SPEED \
+ $01 constant USBSTA_VBUS \
+&215 constant UHWCON \
+ $01 constant UHWCON_UVREGE \
+
+\ Interrupts
+&2 constant INT0Addr \ External Interrupt Request 0
+&4 constant INT1Addr \ External Interrupt Request 1
+&6 constant INT2Addr \ External Interrupt Request 2
+&8 constant INT3Addr \ External Interrupt Request 3
+&10 constant Reserved1Addr \ Reserved1
+&12 constant Reserved2Addr \ Reserved2
+&14 constant INT6Addr \ External Interrupt Request 6
+&16 constant Reserved3Addr \ Reserved3
+&18 constant PCINT0Addr \ Pin Change Interrupt Request 0
+&20 constant USB_GENAddr \ USB General Interrupt Request
+&22 constant USB_COMAddr \ USB Endpoint/Pipe Interrupt Communication Reque
+&24 constant WDTAddr \ Watchdog Time-out Interrupt
+&26 constant Reserved4Addr \ Reserved4
+&28 constant Reserved5Addr \ Reserved5
+&30 constant Reserved6Addr \ Reserved6
+&32 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+&34 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
+&36 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
+&38 constant TIMER1_COMPCAddr \ Timer/Counter1 Compare Match C
+&40 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+&42 constant TIMER0_COMPAAddr \ Timer/Counter0 Compare Match A
+&44 constant TIMER0_COMPBAddr \ Timer/Counter0 Compare Match B
+&46 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
+&48 constant SPI__STCAddr \ SPI Serial Transfer Complete
+&50 constant USART1__RXAddr \ USART1, Rx Complete
+&52 constant USART1__UDREAddr \ USART1 Data register Empty
+&54 constant USART1__TXAddr \ USART1, Tx Complete
+&56 constant ANALOG_COMPAddr \ Analog Comparator
+&58 constant ADCAddr \ ADC Conversion Complete
+&60 constant EE_READYAddr \ EEPROM Ready
+&62 constant TIMER3_CAPTAddr \ Timer/Counter3 Capture Event
+&64 constant TIMER3_COMPAAddr \ Timer/Counter3 Compare Match A
+&66 constant TIMER3_COMPBAddr \ Timer/Counter3 Compare Match B
+&68 constant TIMER3_COMPCAddr \ Timer/Counter3 Compare Match C
+&70 constant TIMER3_OVFAddr \ Timer/Counter3 Overflow
+&72 constant TWIAddr \ 2-wire Serial Interface
+&74 constant SPM_READYAddr \ Store Program Memory Read
+&76 constant TIMER4_COMPAAddr \ Timer/Counter4 Compare Match A
+&78 constant TIMER4_COMPBAddr \ Timer/Counter4 Compare Match B
+&80 constant TIMER4_COMPDAddr \ Timer/Counter4 Compare Match D
+&82 constant TIMER4_OVFAddr \ Timer/Counter4 Overflow
+&84 constant TIMER4_FPFAddr \ Timer/Counter4 Fault Protection Interrupt
diff --git a/amforth-6.5/avr8/devices/atmega16u4/device.asm b/amforth-6.5/avr8/devices/atmega16u4/device.asm
new file mode 100644
index 0000000..eb03743
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega16u4/device.asm
@@ -0,0 +1,146 @@
+; Partname: ATmega16U4
+; generated automatically, do not edit
+
+.nolist
+ .include "m16U4def.inc"
+.list
+
+.equ ramstart = 256
+.equ CELLSIZE = 2
+.macro readflashcell
+ lsl zl
+ rol zh
+ lpm @0, Z+
+ lpm @1, Z+
+.endmacro
+.macro writeflashcell
+ lsl zl
+ rol zh
+.endmacro
+.set WANT_WATCHDOG = 0
+.set WANT_PORTD = 0
+.set WANT_SPI = 0
+.set WANT_USART1 = 0
+.set WANT_BOOT_LOAD = 0
+.set WANT_EEPROM = 0
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_TIMER_COUNTER_3 = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_JTAG = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_TIMER_COUNTER_4 = 0
+.set WANT_PORTB = 0
+.set WANT_PORTC = 0
+.set WANT_PORTE = 0
+.set WANT_PORTF = 0
+.set WANT_AD_CONVERTER = 0
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_CPU = 0
+.set WANT_PLL = 0
+.set WANT_USB_DEVICE = 0
+.equ intvecsize = 2 ; please verify; flash size: 16384 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.org 2
+ rcall isr ; External Interrupt Request 0
+.org 4
+ rcall isr ; External Interrupt Request 1
+.org 6
+ rcall isr ; External Interrupt Request 2
+.org 8
+ rcall isr ; External Interrupt Request 3
+.org 10
+ rcall isr ; Reserved1
+.org 12
+ rcall isr ; Reserved2
+.org 14
+ rcall isr ; External Interrupt Request 6
+.org 16
+ rcall isr ; Reserved3
+.org 18
+ rcall isr ; Pin Change Interrupt Request 0
+.org 20
+ rcall isr ; USB General Interrupt Request
+.org 22
+ rcall isr ; USB Endpoint/Pipe Interrupt Communication Request
+.org 24
+ rcall isr ; Watchdog Time-out Interrupt
+.org 26
+ rcall isr ; Reserved4
+.org 28
+ rcall isr ; Reserved5
+.org 30
+ rcall isr ; Reserved6
+.org 32
+ rcall isr ; Timer/Counter1 Capture Event
+.org 34
+ rcall isr ; Timer/Counter1 Compare Match A
+.org 36
+ rcall isr ; Timer/Counter1 Compare Match B
+.org 38
+ rcall isr ; Timer/Counter1 Compare Match C
+.org 40
+ rcall isr ; Timer/Counter1 Overflow
+.org 42
+ rcall isr ; Timer/Counter0 Compare Match A
+.org 44
+ rcall isr ; Timer/Counter0 Compare Match B
+.org 46
+ rcall isr ; Timer/Counter0 Overflow
+.org 48
+ rcall isr ; SPI Serial Transfer Complete
+.org 50
+ rcall isr ; USART1, Rx Complete
+.org 52
+ rcall isr ; USART1 Data register Empty
+.org 54
+ rcall isr ; USART1, Tx Complete
+.org 56
+ rcall isr ; Analog Comparator
+.org 58
+ rcall isr ; ADC Conversion Complete
+.org 60
+ rcall isr ; EEPROM Ready
+.org 62
+ rcall isr ; Timer/Counter3 Capture Event
+.org 64
+ rcall isr ; Timer/Counter3 Compare Match A
+.org 66
+ rcall isr ; Timer/Counter3 Compare Match B
+.org 68
+ rcall isr ; Timer/Counter3 Compare Match C
+.org 70
+ rcall isr ; Timer/Counter3 Overflow
+.org 72
+ rcall isr ; 2-wire Serial Interface
+.org 74
+ rcall isr ; Store Program Memory Read
+.org 76
+ rcall isr ; Timer/Counter4 Compare Match A
+.org 78
+ rcall isr ; Timer/Counter4 Compare Match B
+.org 80
+ rcall isr ; Timer/Counter4 Compare Match D
+.org 82
+ rcall isr ; Timer/Counter4 Overflow
+.org 84
+ rcall isr ; Timer/Counter4 Fault Protection Interrupt
+.equ INTVECTORS = 43
+.nooverlap
+
+; compatability layer (maybe empty)
+
+; controller data area, environment query mcu-info
+mcu_info:
+mcu_ramsize:
+ .dw 1280
+mcu_eepromsize:
+ .dw 512
+mcu_maxdp:
+ .dw 12288
+mcu_numints:
+ .dw 43
+mcu_name:
+ .dw 10
+ .db "ATmega16U4"
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega16u4/device.inc b/amforth-6.5/avr8/devices/atmega16u4/device.inc
new file mode 100644
index 0000000..f0de2d7
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega16u4/device.inc
@@ -0,0 +1,1602 @@
+; Partname: ATmega16U4
+; generated automatically, no not edit
+
+.if WANT_WATCHDOG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCSR:
+ .dw $ff06
+ .db "WDTCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCSR
+XT_WDTCSR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCSR:
+ .dw 96
+
+.endif
+.if WANT_PORTD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw 43
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw 42
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw 41
+
+.endif
+.if WANT_SPI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR:
+ .dw $ff04
+ .db "SPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR
+XT_SPCR:
+ .dw PFA_DOVARIABLE
+PFA_SPCR:
+ .dw 76
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR:
+ .dw $ff04
+ .db "SPSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR
+XT_SPSR:
+ .dw PFA_DOVARIABLE
+PFA_SPSR:
+ .dw 77
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR:
+ .dw $ff04
+ .db "SPDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR
+XT_SPDR:
+ .dw PFA_DOVARIABLE
+PFA_SPDR:
+ .dw 78
+
+.endif
+.if WANT_USART1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR1:
+ .dw $ff04
+ .db "UDR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR1
+XT_UDR1:
+ .dw PFA_DOVARIABLE
+PFA_UDR1:
+ .dw 206
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR1A:
+ .dw $ff06
+ .db "UCSR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1A
+XT_UCSR1A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1A:
+ .dw 200
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR1B:
+ .dw $ff06
+ .db "UCSR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1B
+XT_UCSR1B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1B:
+ .dw 201
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR1C:
+ .dw $ff06
+ .db "UCSR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1C
+XT_UCSR1C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1C:
+ .dw 202
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Bytes
+VE_UBRR1:
+ .dw $ff05
+ .db "UBRR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR1
+XT_UBRR1:
+ .dw PFA_DOVARIABLE
+PFA_UBRR1:
+ .dw 204
+
+.endif
+.if WANT_BOOT_LOAD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control Register
+VE_SPMCSR:
+ .dw $ff06
+ .db "SPMCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCSR
+XT_SPMCSR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCSR:
+ .dw 87
+
+.endif
+.if WANT_EEPROM == 1
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Address Register Low Bytes
+VE_EEAR:
+ .dw $ff04
+ .db "EEAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEAR
+XT_EEAR:
+ .dw PFA_DOVARIABLE
+PFA_EEAR:
+ .dw 65
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw 64
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw 63
+
+.endif
+.if WANT_TIMER_COUNTER_0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0B:
+ .dw $ff05
+ .db "OCR0B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0B
+XT_OCR0B:
+ .dw PFA_DOVARIABLE
+PFA_OCR0B:
+ .dw 72
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0A:
+ .dw $ff05
+ .db "OCR0A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0A
+XT_OCR0A:
+ .dw PFA_DOVARIABLE
+PFA_OCR0A:
+ .dw 71
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw 70
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register B
+VE_TCCR0B:
+ .dw $ff06
+ .db "TCCR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0B
+XT_TCCR0B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0B:
+ .dw 69
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register A
+VE_TCCR0A:
+ .dw $ff06
+ .db "TCCR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0A
+XT_TCCR0A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0A:
+ .dw 68
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Mask Register
+VE_TIMSK0:
+ .dw $ff06
+ .db "TIMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK0
+XT_TIMSK0:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK0:
+ .dw 110
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Flag register
+VE_TIFR0:
+ .dw $ff05
+ .db "TIFR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR0
+XT_TIFR0:
+ .dw PFA_DOVARIABLE
+PFA_TIFR0:
+ .dw 53
+; ( -- addr ) System Constant
+; R( -- )
+; General Timer/Counter Control Register
+VE_GTCCR:
+ .dw $ff05
+ .db "GTCCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GTCCR
+XT_GTCCR:
+ .dw PFA_DOVARIABLE
+PFA_GTCCR:
+ .dw 67
+
+.endif
+.if WANT_TIMER_COUNTER_3 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Control Register A
+VE_TCCR3A:
+ .dw $ff06
+ .db "TCCR3A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR3A
+XT_TCCR3A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR3A:
+ .dw 144
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Control Register B
+VE_TCCR3B:
+ .dw $ff06
+ .db "TCCR3B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR3B
+XT_TCCR3B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR3B:
+ .dw 145
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter 3 Control Register C
+VE_TCCR3C:
+ .dw $ff06
+ .db "TCCR3C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR3C
+XT_TCCR3C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR3C:
+ .dw 146
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Bytes
+VE_TCNT3:
+ .dw $ff05
+ .db "TCNT3",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT3
+XT_TCNT3:
+ .dw PFA_DOVARIABLE
+PFA_TCNT3:
+ .dw 148
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Output Compare Register A Bytes
+VE_OCR3A:
+ .dw $ff05
+ .db "OCR3A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR3A
+XT_OCR3A:
+ .dw PFA_DOVARIABLE
+PFA_OCR3A:
+ .dw 152
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Output Compare Register B Bytes
+VE_OCR3B:
+ .dw $ff05
+ .db "OCR3B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR3B
+XT_OCR3B:
+ .dw PFA_DOVARIABLE
+PFA_OCR3B:
+ .dw 154
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Output Compare Register B Bytes
+VE_OCR3C:
+ .dw $ff05
+ .db "OCR3C",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR3C
+XT_OCR3C:
+ .dw PFA_DOVARIABLE
+PFA_OCR3C:
+ .dw 156
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Input Capture Register Bytes
+VE_ICR3:
+ .dw $ff04
+ .db "ICR3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR3
+XT_ICR3:
+ .dw PFA_DOVARIABLE
+PFA_ICR3:
+ .dw 150
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Interrupt Mask Register
+VE_TIMSK3:
+ .dw $ff06
+ .db "TIMSK3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK3
+XT_TIMSK3:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK3:
+ .dw 113
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Interrupt Flag register
+VE_TIFR3:
+ .dw $ff05
+ .db "TIFR3",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR3
+XT_TIFR3:
+ .dw PFA_DOVARIABLE
+PFA_TIFR3:
+ .dw 56
+
+.endif
+.if WANT_TIMER_COUNTER_1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw 128
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw 129
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter 1 Control Register C
+VE_TCCR1C:
+ .dw $ff06
+ .db "TCCR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1C
+XT_TCCR1C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1C:
+ .dw 130
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Bytes
+VE_TCNT1:
+ .dw $ff05
+ .db "TCNT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1
+XT_TCNT1:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1:
+ .dw 132
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register A Bytes
+VE_OCR1A:
+ .dw $ff05
+ .db "OCR1A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1A
+XT_OCR1A:
+ .dw PFA_DOVARIABLE
+PFA_OCR1A:
+ .dw 136
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register B Bytes
+VE_OCR1B:
+ .dw $ff05
+ .db "OCR1B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1B
+XT_OCR1B:
+ .dw PFA_DOVARIABLE
+PFA_OCR1B:
+ .dw 138
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register C Bytes
+VE_OCR1C:
+ .dw $ff05
+ .db "OCR1C",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1C
+XT_OCR1C:
+ .dw PFA_DOVARIABLE
+PFA_OCR1C:
+ .dw 140
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Bytes
+VE_ICR1:
+ .dw $ff04
+ .db "ICR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1
+XT_ICR1:
+ .dw PFA_DOVARIABLE
+PFA_ICR1:
+ .dw 134
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Mask Register
+VE_TIMSK1:
+ .dw $ff06
+ .db "TIMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK1
+XT_TIMSK1:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK1:
+ .dw 111
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Flag register
+VE_TIFR1:
+ .dw $ff05
+ .db "TIFR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR1
+XT_TIFR1:
+ .dw PFA_DOVARIABLE
+PFA_TIFR1:
+ .dw 54
+
+.endif
+.if WANT_JTAG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; On-Chip Debug Related Register in I/O Memory
+VE_OCDR:
+ .dw $ff04
+ .db "OCDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCDR
+XT_OCDR:
+ .dw PFA_DOVARIABLE
+PFA_OCDR:
+ .dw 81
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw 85
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Status Register
+VE_MCUSR:
+ .dw $ff05
+ .db "MCUSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUSR
+XT_MCUSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUSR:
+ .dw 84
+
+.endif
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register A
+VE_EICRA:
+ .dw $ff05
+ .db "EICRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRA
+XT_EICRA:
+ .dw PFA_DOVARIABLE
+PFA_EICRA:
+ .dw 105
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register B
+VE_EICRB:
+ .dw $ff05
+ .db "EICRB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRB
+XT_EICRB:
+ .dw PFA_DOVARIABLE
+PFA_EICRB:
+ .dw 106
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Mask Register
+VE_EIMSK:
+ .dw $ff05
+ .db "EIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIMSK
+XT_EIMSK:
+ .dw PFA_DOVARIABLE
+PFA_EIMSK:
+ .dw 61
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Flag Register
+VE_EIFR:
+ .dw $ff04
+ .db "EIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIFR
+XT_EIFR:
+ .dw PFA_DOVARIABLE
+PFA_EIFR:
+ .dw 60
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 0
+VE_PCMSK0:
+ .dw $ff06
+ .db "PCMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK0
+XT_PCMSK0:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK0:
+ .dw 107
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Interrupt Flag Register
+VE_PCIFR:
+ .dw $ff05
+ .db "PCIFR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCIFR
+XT_PCIFR:
+ .dw PFA_DOVARIABLE
+PFA_PCIFR:
+ .dw 59
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Interrupt Control Register
+VE_PCICR:
+ .dw $ff05
+ .db "PCICR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCICR
+XT_PCICR:
+ .dw PFA_DOVARIABLE
+PFA_PCICR:
+ .dw 104
+
+.endif
+.if WANT_TIMER_COUNTER_4 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter4 Control Register A
+VE_TCCR4A:
+ .dw $ff06
+ .db "TCCR4A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR4A
+XT_TCCR4A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR4A:
+ .dw 192
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter4 Control Register B
+VE_TCCR4B:
+ .dw $ff06
+ .db "TCCR4B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR4B
+XT_TCCR4B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR4B:
+ .dw 193
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter 4 Control Register C
+VE_TCCR4C:
+ .dw $ff06
+ .db "TCCR4C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR4C
+XT_TCCR4C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR4C:
+ .dw 194
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter 4 Control Register D
+VE_TCCR4D:
+ .dw $ff06
+ .db "TCCR4D"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR4D
+XT_TCCR4D:
+ .dw PFA_DOVARIABLE
+PFA_TCCR4D:
+ .dw 195
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter 4 Control Register E
+VE_TCCR4E:
+ .dw $ff06
+ .db "TCCR4E"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR4E
+XT_TCCR4E:
+ .dw PFA_DOVARIABLE
+PFA_TCCR4E:
+ .dw 196
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter4 Low Bytes
+VE_TCNT4:
+ .dw $ff05
+ .db "TCNT4",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT4
+XT_TCNT4:
+ .dw PFA_DOVARIABLE
+PFA_TCNT4:
+ .dw 190
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter4
+VE_TC4H:
+ .dw $ff04
+ .db "TC4H"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TC4H
+XT_TC4H:
+ .dw PFA_DOVARIABLE
+PFA_TC4H:
+ .dw 191
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter4 Output Compare Register A
+VE_OCR4A:
+ .dw $ff05
+ .db "OCR4A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR4A
+XT_OCR4A:
+ .dw PFA_DOVARIABLE
+PFA_OCR4A:
+ .dw 207
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter4 Output Compare Register B
+VE_OCR4B:
+ .dw $ff05
+ .db "OCR4B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR4B
+XT_OCR4B:
+ .dw PFA_DOVARIABLE
+PFA_OCR4B:
+ .dw 208
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter4 Output Compare Register C
+VE_OCR4C:
+ .dw $ff05
+ .db "OCR4C",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR4C
+XT_OCR4C:
+ .dw PFA_DOVARIABLE
+PFA_OCR4C:
+ .dw 209
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter4 Output Compare Register D
+VE_OCR4D:
+ .dw $ff05
+ .db "OCR4D",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR4D
+XT_OCR4D:
+ .dw PFA_DOVARIABLE
+PFA_OCR4D:
+ .dw 210
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter4 Interrupt Mask Register
+VE_TIMSK4:
+ .dw $ff06
+ .db "TIMSK4"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK4
+XT_TIMSK4:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK4:
+ .dw 114
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter4 Interrupt Flag register
+VE_TIFR4:
+ .dw $ff05
+ .db "TIFR4",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR4
+XT_TIFR4:
+ .dw PFA_DOVARIABLE
+PFA_TIFR4:
+ .dw 57
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter 4 Dead Time Value
+VE_DT4:
+ .dw $ff03
+ .db "DT4",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DT4
+XT_DT4:
+ .dw PFA_DOVARIABLE
+PFA_DT4:
+ .dw 212
+
+.endif
+.if WANT_PORTB == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw 37
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw 36
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw 35
+
+.endif
+.if WANT_PORTC == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Register
+VE_PORTC:
+ .dw $ff05
+ .db "PORTC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTC
+XT_PORTC:
+ .dw PFA_DOVARIABLE
+PFA_PORTC:
+ .dw 40
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Direction Register
+VE_DDRC:
+ .dw $ff04
+ .db "DDRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRC
+XT_DDRC:
+ .dw PFA_DOVARIABLE
+PFA_DDRC:
+ .dw 39
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Input Pins
+VE_PINC:
+ .dw $ff04
+ .db "PINC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINC
+XT_PINC:
+ .dw PFA_DOVARIABLE
+PFA_PINC:
+ .dw 38
+
+.endif
+.if WANT_PORTE == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port E
+VE_PORTE:
+ .dw $ff05
+ .db "PORTE",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTE
+XT_PORTE:
+ .dw PFA_DOVARIABLE
+PFA_PORTE:
+ .dw 46
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port E
+VE_DDRE:
+ .dw $ff04
+ .db "DDRE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRE
+XT_DDRE:
+ .dw PFA_DOVARIABLE
+PFA_DDRE:
+ .dw 45
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port E
+VE_PINE:
+ .dw $ff04
+ .db "PINE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINE
+XT_PINE:
+ .dw PFA_DOVARIABLE
+PFA_PINE:
+ .dw 44
+
+.endif
+.if WANT_PORTF == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port F
+VE_PORTF:
+ .dw $ff05
+ .db "PORTF",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTF
+XT_PORTF:
+ .dw PFA_DOVARIABLE
+PFA_PORTF:
+ .dw 49
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port F
+VE_DDRF:
+ .dw $ff04
+ .db "DDRF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRF
+XT_DDRF:
+ .dw PFA_DOVARIABLE
+PFA_DDRF:
+ .dw 48
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port F
+VE_PINF:
+ .dw $ff04
+ .db "PINF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINF
+XT_PINF:
+ .dw PFA_DOVARIABLE
+PFA_PINF:
+ .dw 47
+
+.endif
+.if WANT_AD_CONVERTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC multiplexer Selection Register
+VE_ADMUX:
+ .dw $ff05
+ .db "ADMUX",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADMUX
+XT_ADMUX:
+ .dw PFA_DOVARIABLE
+PFA_ADMUX:
+ .dw 124
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register
+VE_ADCSRA:
+ .dw $ff06
+ .db "ADCSRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRA
+XT_ADCSRA:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRA:
+ .dw 122
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register Bytes
+VE_ADC:
+ .dw $ff03
+ .db "ADC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADC
+XT_ADC:
+ .dw PFA_DOVARIABLE
+PFA_ADC:
+ .dw 120
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Control and Status Register B
+VE_ADCSRB:
+ .dw $ff06
+ .db "ADCSRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRB
+XT_ADCSRB:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRB:
+ .dw 123
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 1
+VE_DIDR0:
+ .dw $ff05
+ .db "DIDR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR0
+XT_DIDR0:
+ .dw PFA_DOVARIABLE
+PFA_DIDR0:
+ .dw 126
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 1
+VE_DIDR2:
+ .dw $ff05
+ .db "DIDR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR2
+XT_DIDR2:
+ .dw PFA_DOVARIABLE
+PFA_DIDR2:
+ .dw 125
+
+.endif
+.if WANT_ANALOG_COMPARATOR == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Control And Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw 80
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_DIDR1:
+ .dw $ff05
+ .db "DIDR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR1
+XT_DIDR1:
+ .dw PFA_DOVARIABLE
+PFA_DIDR1:
+ .dw 127
+
+.endif
+.if WANT_CPU == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw 95
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer
+VE_SP:
+ .dw $ff02
+ .db "SP"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SP
+XT_SP:
+ .dw PFA_DOVARIABLE
+PFA_SP:
+ .dw 93
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Calibration Value
+VE_OSCCAL:
+ .dw $ff06
+ .db "OSCCAL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSCCAL
+XT_OSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_OSCCAL:
+ .dw 102
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Control Register
+VE_RCCTRL:
+ .dw $ff06
+ .db "RCCTRL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_RCCTRL
+XT_RCCTRL:
+ .dw PFA_DOVARIABLE
+PFA_RCCTRL:
+ .dw 103
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_CLKPR:
+ .dw $ff05
+ .db "CLKPR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKPR
+XT_CLKPR:
+ .dw PFA_DOVARIABLE
+PFA_CLKPR:
+ .dw 97
+; ( -- addr ) System Constant
+; R( -- )
+; Sleep Mode Control Register
+VE_SMCR:
+ .dw $ff04
+ .db "SMCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SMCR
+XT_SMCR:
+ .dw PFA_DOVARIABLE
+PFA_SMCR:
+ .dw 83
+; ( -- addr ) System Constant
+; R( -- )
+; Extended Indirect Register
+VE_EIND:
+ .dw $ff04
+ .db "EIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIND
+XT_EIND:
+ .dw PFA_DOVARIABLE
+PFA_EIND:
+ .dw 92
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 2
+VE_GPIOR2:
+ .dw $ff06
+ .db "GPIOR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR2
+XT_GPIOR2:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR2:
+ .dw 75
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 1
+VE_GPIOR1:
+ .dw $ff06
+ .db "GPIOR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR1
+XT_GPIOR1:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR1:
+ .dw 74
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 0
+VE_GPIOR0:
+ .dw $ff06
+ .db "GPIOR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR0
+XT_GPIOR0:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR0:
+ .dw 62
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register1
+VE_PRR1:
+ .dw $ff04
+ .db "PRR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR1
+XT_PRR1:
+ .dw PFA_DOVARIABLE
+PFA_PRR1:
+ .dw 101
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register0
+VE_PRR0:
+ .dw $ff04
+ .db "PRR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR0
+XT_PRR0:
+ .dw PFA_DOVARIABLE
+PFA_PRR0:
+ .dw 100
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_CLKSTA:
+ .dw $ff06
+ .db "CLKSTA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKSTA
+XT_CLKSTA:
+ .dw PFA_DOVARIABLE
+PFA_CLKSTA:
+ .dw 199
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_CLKSEL1:
+ .dw $ff07
+ .db "CLKSEL1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKSEL1
+XT_CLKSEL1:
+ .dw PFA_DOVARIABLE
+PFA_CLKSEL1:
+ .dw 198
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_CLKSEL0:
+ .dw $ff07
+ .db "CLKSEL0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKSEL0
+XT_CLKSEL0:
+ .dw PFA_DOVARIABLE
+PFA_CLKSEL0:
+ .dw 197
+
+.endif
+.if WANT_PLL == 1
+; ( -- addr ) System Constant
+; R( -- )
+; PLL Status and Control register
+VE_PLLCSR:
+ .dw $ff06
+ .db "PLLCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PLLCSR
+XT_PLLCSR:
+ .dw PFA_DOVARIABLE
+PFA_PLLCSR:
+ .dw 73
+; ( -- addr ) System Constant
+; R( -- )
+; PLL Frequency Control Register
+VE_PLLFRQ:
+ .dw $ff06
+ .db "PLLFRQ"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PLLFRQ
+XT_PLLFRQ:
+ .dw PFA_DOVARIABLE
+PFA_PLLFRQ:
+ .dw 82
+
+.endif
+.if WANT_USB_DEVICE == 1
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UEINT:
+ .dw $ff05
+ .db "UEINT",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UEINT
+XT_UEINT:
+ .dw PFA_DOVARIABLE
+PFA_UEINT:
+ .dw 244
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UEBCHX:
+ .dw $ff06
+ .db "UEBCHX"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UEBCHX
+XT_UEBCHX:
+ .dw PFA_DOVARIABLE
+PFA_UEBCHX:
+ .dw 243
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UEBCLX:
+ .dw $ff06
+ .db "UEBCLX"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UEBCLX
+XT_UEBCLX:
+ .dw PFA_DOVARIABLE
+PFA_UEBCLX:
+ .dw 242
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UEDATX:
+ .dw $ff06
+ .db "UEDATX"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UEDATX
+XT_UEDATX:
+ .dw PFA_DOVARIABLE
+PFA_UEDATX:
+ .dw 241
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UEIENX:
+ .dw $ff06
+ .db "UEIENX"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UEIENX
+XT_UEIENX:
+ .dw PFA_DOVARIABLE
+PFA_UEIENX:
+ .dw 240
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UESTA1X:
+ .dw $ff07
+ .db "UESTA1X",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UESTA1X
+XT_UESTA1X:
+ .dw PFA_DOVARIABLE
+PFA_UESTA1X:
+ .dw 239
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UESTA0X:
+ .dw $ff07
+ .db "UESTA0X",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UESTA0X
+XT_UESTA0X:
+ .dw PFA_DOVARIABLE
+PFA_UESTA0X:
+ .dw 238
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UECFG1X:
+ .dw $ff07
+ .db "UECFG1X",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UECFG1X
+XT_UECFG1X:
+ .dw PFA_DOVARIABLE
+PFA_UECFG1X:
+ .dw 237
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UECFG0X:
+ .dw $ff07
+ .db "UECFG0X",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UECFG0X
+XT_UECFG0X:
+ .dw PFA_DOVARIABLE
+PFA_UECFG0X:
+ .dw 236
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UECONX:
+ .dw $ff06
+ .db "UECONX"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UECONX
+XT_UECONX:
+ .dw PFA_DOVARIABLE
+PFA_UECONX:
+ .dw 235
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UERST:
+ .dw $ff05
+ .db "UERST",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UERST
+XT_UERST:
+ .dw PFA_DOVARIABLE
+PFA_UERST:
+ .dw 234
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UENUM:
+ .dw $ff05
+ .db "UENUM",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UENUM
+XT_UENUM:
+ .dw PFA_DOVARIABLE
+PFA_UENUM:
+ .dw 233
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UEINTX:
+ .dw $ff06
+ .db "UEINTX"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UEINTX
+XT_UEINTX:
+ .dw PFA_DOVARIABLE
+PFA_UEINTX:
+ .dw 232
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UDMFN:
+ .dw $ff05
+ .db "UDMFN",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDMFN
+XT_UDMFN:
+ .dw PFA_DOVARIABLE
+PFA_UDMFN:
+ .dw 230
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UDFNUM:
+ .dw $ff06
+ .db "UDFNUM"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDFNUM
+XT_UDFNUM:
+ .dw PFA_DOVARIABLE
+PFA_UDFNUM:
+ .dw 228
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UDADDR:
+ .dw $ff06
+ .db "UDADDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDADDR
+XT_UDADDR:
+ .dw PFA_DOVARIABLE
+PFA_UDADDR:
+ .dw 227
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UDIEN:
+ .dw $ff05
+ .db "UDIEN",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDIEN
+XT_UDIEN:
+ .dw PFA_DOVARIABLE
+PFA_UDIEN:
+ .dw 226
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UDINT:
+ .dw $ff05
+ .db "UDINT",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDINT
+XT_UDINT:
+ .dw PFA_DOVARIABLE
+PFA_UDINT:
+ .dw 225
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UDCON:
+ .dw $ff05
+ .db "UDCON",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDCON
+XT_UDCON:
+ .dw PFA_DOVARIABLE
+PFA_UDCON:
+ .dw 224
+; ( -- addr ) System Constant
+; R( -- )
+; USB General Control Register
+VE_USBCON:
+ .dw $ff06
+ .db "USBCON"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USBCON
+XT_USBCON:
+ .dw PFA_DOVARIABLE
+PFA_USBCON:
+ .dw 216
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_USBINT:
+ .dw $ff06
+ .db "USBINT"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USBINT
+XT_USBINT:
+ .dw PFA_DOVARIABLE
+PFA_USBINT:
+ .dw 218
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_USBSTA:
+ .dw $ff06
+ .db "USBSTA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USBSTA
+XT_USBSTA:
+ .dw PFA_DOVARIABLE
+PFA_USBSTA:
+ .dw 217
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UHWCON:
+ .dw $ff06
+ .db "UHWCON"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UHWCON
+XT_UHWCON:
+ .dw PFA_DOVARIABLE
+PFA_UHWCON:
+ .dw 215
+
+.endif
diff --git a/amforth-6.5/avr8/devices/atmega16u4/device.py b/amforth-6.5/avr8/devices/atmega16u4/device.py
new file mode 100644
index 0000000..2a03486
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega16u4/device.py
@@ -0,0 +1,554 @@
+# Generated Automatically
+
+# Partname ATmega16U4
+
+MCUREGS = {
+# Interrupt Vectors
+ 'INT0Addr' : '#2', # External Interrupt Request 0
+ 'INT1Addr' : '#4', # External Interrupt Request 1
+ 'INT2Addr' : '#6', # External Interrupt Request 2
+ 'INT3Addr' : '#8', # External Interrupt Request 3
+ 'Reserved1Addr' : '#10', # Reserved1
+ 'Reserved2Addr' : '#12', # Reserved2
+ 'INT6Addr' : '#14', # External Interrupt Request 6
+ 'Reserved3Addr' : '#16', # Reserved3
+ 'PCINT0Addr' : '#18', # Pin Change Interrupt Request 0
+ 'USB_GENAddr' : '#20', # USB General Interrupt Request
+ 'USB_COMAddr' : '#22', # USB Endpoint/Pipe Interrupt Communication Request
+ 'WDTAddr' : '#24', # Watchdog Time-out Interrupt
+ 'Reserved4Addr' : '#26', # Reserved4
+ 'Reserved5Addr' : '#28', # Reserved5
+ 'Reserved6Addr' : '#30', # Reserved6
+ 'TIMER1_CAPTAddr' : '#32', # Timer/Counter1 Capture Event
+ 'TIMER1_COMPAAddr' : '#34', # Timer/Counter1 Compare Match A
+ 'TIMER1_COMPBAddr' : '#36', # Timer/Counter1 Compare Match B
+ 'TIMER1_COMPCAddr' : '#38', # Timer/Counter1 Compare Match C
+ 'TIMER1_OVFAddr' : '#40', # Timer/Counter1 Overflow
+ 'TIMER0_COMPAAddr' : '#42', # Timer/Counter0 Compare Match A
+ 'TIMER0_COMPBAddr' : '#44', # Timer/Counter0 Compare Match B
+ 'TIMER0_OVFAddr' : '#46', # Timer/Counter0 Overflow
+ 'SPI_STCAddr' : '#48', # SPI Serial Transfer Complete
+ 'USART1_RXAddr' : '#50', # USART1, Rx Complete
+ 'USART1_UDREAddr' : '#52', # USART1 Data register Empty
+ 'USART1_TXAddr' : '#54', # USART1, Tx Complete
+ 'ANALOG_COMPAddr' : '#56', # Analog Comparator
+ 'ADCAddr' : '#58', # ADC Conversion Complete
+ 'EE_READYAddr' : '#60', # EEPROM Ready
+ 'TIMER3_CAPTAddr' : '#62', # Timer/Counter3 Capture Event
+ 'TIMER3_COMPAAddr' : '#64', # Timer/Counter3 Compare Match A
+ 'TIMER3_COMPBAddr' : '#66', # Timer/Counter3 Compare Match B
+ 'TIMER3_COMPCAddr' : '#68', # Timer/Counter3 Compare Match C
+ 'TIMER3_OVFAddr' : '#70', # Timer/Counter3 Overflow
+ 'TWIAddr' : '#72', # 2-wire Serial Interface
+ 'SPM_READYAddr' : '#74', # Store Program Memory Read
+ 'TIMER4_COMPAAddr' : '#76', # Timer/Counter4 Compare Match A
+ 'TIMER4_COMPBAddr' : '#78', # Timer/Counter4 Compare Match B
+ 'TIMER4_COMPDAddr' : '#80', # Timer/Counter4 Compare Match D
+ 'TIMER4_OVFAddr' : '#82', # Timer/Counter4 Overflow
+ 'TIMER4_FPFAddr' : '#84', # Timer/Counter4 Fault Protection Interrupt
+
+# Module WATCHDOG
+ 'WDTCSR' : '$60', # Watchdog Timer Control Registe
+ 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
+ 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
+ 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
+ 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
+ 'WDTCSR_WDE': '$8', # Watch Dog Enable
+
+# Module PORTD
+ 'PORTD' : '$2b', # Port D Data Register
+ 'DDRD' : '$2a', # Port D Data Direction Register
+ 'PIND' : '$29', # Port D Input Pins
+
+# Module SPI
+ 'SPCR' : '$4c', # SPI Control Register
+ 'SPCR_SPIE': '$80', # SPI Interrupt Enable
+ 'SPCR_SPE': '$40', # SPI Enable
+ 'SPCR_DORD': '$20', # Data Order
+ 'SPCR_MSTR': '$10', # Master/Slave Select
+ 'SPCR_CPOL': '$8', # Clock polarity
+ 'SPCR_CPHA': '$4', # Clock Phase
+ 'SPCR_SPR': '$3', # SPI Clock Rate Selects
+ 'SPSR' : '$4d', # SPI Status Register
+ 'SPSR_SPIF': '$80', # SPI Interrupt Flag
+ 'SPSR_WCOL': '$40', # Write Collision Flag
+ 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
+ 'SPDR' : '$4e', # SPI Data Register
+
+# Module USART1
+ 'UDR1' : '$ce', # USART I/O Data Register
+ 'UCSR1A' : '$c8', # USART Control and Status Regis
+ 'UCSR1A_RXC1': '$80', # USART Receive Complete
+ 'UCSR1A_TXC1': '$40', # USART Transmitt Complete
+ 'UCSR1A_UDRE1': '$20', # USART Data Register Empty
+ 'UCSR1A_FE1': '$10', # Framing Error
+ 'UCSR1A_DOR1': '$8', # Data overRun
+ 'UCSR1A_UPE1': '$4', # Parity Error
+ 'UCSR1A_U2X1': '$2', # Double the USART transmission
+ 'UCSR1A_MPCM1': '$1', # Multi-processor Communication
+ 'UCSR1B' : '$c9', # USART Control and Status Regis
+ 'UCSR1B_RXCIE1': '$80', # RX Complete Interrupt Enable
+ 'UCSR1B_TXCIE1': '$40', # TX Complete Interrupt Enable
+ 'UCSR1B_UDRIE1': '$20', # USART Data register Empty Inte
+ 'UCSR1B_RXEN1': '$10', # Receiver Enable
+ 'UCSR1B_TXEN1': '$8', # Transmitter Enable
+ 'UCSR1B_UCSZ12': '$4', # Character Size
+ 'UCSR1B_RXB81': '$2', # Receive Data Bit 8
+ 'UCSR1B_TXB81': '$1', # Transmit Data Bit 8
+ 'UCSR1C' : '$ca', # USART Control and Status Regis
+ 'UCSR1C_UMSEL1': '$c0', # USART Mode Select
+ 'UCSR1C_UPM1': '$30', # Parity Mode Bits
+ 'UCSR1C_USBS1': '$8', # Stop Bit Select
+ 'UCSR1C_UCSZ1': '$6', # Character Size
+ 'UCSR1C_UCPOL1': '$1', # Clock Polarity
+ 'UBRR1' : '$cc', # USART Baud Rate Register Byte
+
+# Module BOOT_LOAD
+ 'SPMCSR' : '$57', # Store Program Memory Control R
+ 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
+ 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
+ 'SPMCSR_SIGRD': '$20', # Signature Row Read
+ 'SPMCSR_RWWSRE': '$10', # Read While Write section read
+ 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
+ 'SPMCSR_PGWRT': '$4', # Page Write
+ 'SPMCSR_PGERS': '$2', # Page Erase
+ 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
+
+# Module EEPROM
+ 'EEAR' : '$41', # EEPROM Address Register Low By
+ 'EEDR' : '$40', # EEPROM Data Register
+ 'EECR' : '$3f', # EEPROM Control Register
+ 'EECR_EEPM': '$30', # EEPROM Programming Mode Bits
+ 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
+ 'EECR_EEMPE': '$4', # EEPROM Master Write Enable
+ 'EECR_EEPE': '$2', # EEPROM Write Enable
+ 'EECR_EERE': '$1', # EEPROM Read Enable
+
+# Module TIMER_COUNTER_0
+ 'OCR0B' : '$48', # Timer/Counter0 Output Compare
+ 'OCR0A' : '$47', # Timer/Counter0 Output Compare
+ 'TCNT0' : '$46', # Timer/Counter0
+ 'TCCR0B' : '$45', # Timer/Counter Control Register
+ 'TCCR0B_FOC0A': '$80', # Force Output Compare A
+ 'TCCR0B_FOC0B': '$40', # Force Output Compare B
+ 'TCCR0B_WGM02': '$8', #
+ 'TCCR0B_CS0': '$7', # Clock Select
+ 'TCCR0A' : '$44', # Timer/Counter Control Registe
+ 'TCCR0A_COM0A': '$c0', # Compare Output Mode, Phase Cor
+ 'TCCR0A_COM0B': '$30', # Compare Output Mode, Fast PWm
+ 'TCCR0A_WGM0': '$3', # Waveform Generation Mode
+ 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
+ 'TIMSK0_OCIE0B': '$4', # Timer/Counter0 Output Compare
+ 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
+ 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
+ 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
+ 'TIFR0_OCF0B': '$4', # Timer/Counter0 Output Compare
+ 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
+ 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSRSYNC': '$1', # Prescaler Reset Timer/Counter1
+
+# Module TIMER_COUNTER_3
+ 'TCCR3A' : '$90', # Timer/Counter3 Control Registe
+ 'TCCR3A_COM3A': '$c0', # Compare Output Mode 1A, bits
+ 'TCCR3A_COM3B': '$30', # Compare Output Mode 3B, bits
+ 'TCCR3A_COM3C': '$c', # Compare Output Mode 3C, bits
+ 'TCCR3A_WGM3': '$3', # Waveform Generation Mode
+ 'TCCR3B' : '$91', # Timer/Counter3 Control Registe
+ 'TCCR3B_ICNC3': '$80', # Input Capture 3 Noise Canceler
+ 'TCCR3B_ICES3': '$40', # Input Capture 3 Edge Select
+ 'TCCR3B_WGM3': '$18', # Waveform Generation Mode
+ 'TCCR3B_CS3': '$7', # Prescaler source of Timer/Coun
+ 'TCCR3C' : '$92', # Timer/Counter 3 Control Regist
+ 'TCCR3C_FOC3A': '$80', # Force Output Compare 3A
+ 'TCCR3C_FOC3B': '$40', # Force Output Compare 3B
+ 'TCCR3C_FOC3C': '$20', # Force Output Compare 3C
+ 'TCNT3' : '$94', # Timer/Counter3 Bytes
+ 'OCR3A' : '$98', # Timer/Counter3 Output Compare
+ 'OCR3B' : '$9a', # Timer/Counter3 Output Compare
+ 'OCR3C' : '$9c', # Timer/Counter3 Output Compare
+ 'ICR3' : '$96', # Timer/Counter3 Input Capture R
+ 'TIMSK3' : '$71', # Timer/Counter3 Interrupt Mask
+ 'TIMSK3_ICIE3': '$20', # Timer/Counter3 Input Capture I
+ 'TIMSK3_OCIE3C': '$8', # Timer/Counter3 Output Compare
+ 'TIMSK3_OCIE3B': '$4', # Timer/Counter3 Output Compare
+ 'TIMSK3_OCIE3A': '$2', # Timer/Counter3 Output Compare
+ 'TIMSK3_TOIE3': '$1', # Timer/Counter3 Overflow Interr
+ 'TIFR3' : '$38', # Timer/Counter3 Interrupt Flag
+ 'TIFR3_ICF3': '$20', # Input Capture Flag 3
+ 'TIFR3_OCF3C': '$8', # Output Compare Flag 3C
+ 'TIFR3_OCF3B': '$4', # Output Compare Flag 3B
+ 'TIFR3_OCF3A': '$2', # Output Compare Flag 3A
+ 'TIFR3_TOV3': '$1', # Timer/Counter3 Overflow Flag
+
+# Module TIMER_COUNTER_1
+ 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
+ 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
+ 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
+ 'TCCR1A_COM1C': '$c', # Compare Output Mode 1C, bits
+ 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
+ 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
+ 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
+ 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
+ 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
+ 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
+ 'TCCR1C' : '$82', # Timer/Counter 1 Control Regist
+ 'TCCR1C_FOC1A': '$80', # Force Output Compare 1A
+ 'TCCR1C_FOC1B': '$40', # Force Output Compare 1B
+ 'TCCR1C_FOC1C': '$20', # Force Output Compare 1C
+ 'TCNT1' : '$84', # Timer/Counter1 Bytes
+ 'OCR1A' : '$88', # Timer/Counter1 Output Compare
+ 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
+ 'OCR1C' : '$8c', # Timer/Counter1 Output Compare
+ 'ICR1' : '$86', # Timer/Counter1 Input Capture R
+ 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
+ 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
+ 'TIMSK1_OCIE1C': '$8', # Timer/Counter1 Output Compare
+ 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
+ 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
+ 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
+ 'TIFR1' : '$36', # Timer/Counter1 Interrupt Flag
+ 'TIFR1_ICF1': '$20', # Input Capture Flag 1
+ 'TIFR1_OCF1C': '$8', # Output Compare Flag 1C
+ 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
+ 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
+ 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
+
+# Module JTAG
+ 'OCDR' : '$51', # On-Chip Debug Related Register
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_JTD': '$80', # JTAG Interface Disable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+
+# Module EXTERNAL_INTERRUPT
+ 'EICRA' : '$69', # External Interrupt Control Reg
+ 'EICRA_ISC3': '$c0', # External Interrupt Sense Contr
+ 'EICRA_ISC2': '$30', # External Interrupt Sense Contr
+ 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
+ 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
+ 'EICRB' : '$6a', # External Interrupt Control Reg
+ 'EICRB_ISC7': '$c0', # External Interrupt 7-4 Sense C
+ 'EICRB_ISC6': '$30', # External Interrupt 7-4 Sense C
+ 'EICRB_ISC5': '$c', # External Interrupt 7-4 Sense C
+ 'EICRB_ISC4': '$3', # External Interrupt 7-4 Sense C
+ 'EIMSK' : '$3d', # External Interrupt Mask Regist
+ 'EIMSK_INT': '$ff', # External Interrupt Request 7 E
+ 'EIFR' : '$3c', # External Interrupt Flag Regist
+ 'EIFR_INTF': '$ff', # External Interrupt Flags
+ 'PCMSK0' : '$6b', # Pin Change Mask Register 0
+ 'PCIFR' : '$3b', # Pin Change Interrupt Flag Regi
+ 'PCIFR_PCIF0': '$1', # Pin Change Interrupt Flag 0
+ 'PCICR' : '$68', # Pin Change Interrupt Control R
+ 'PCICR_PCIE0': '$1', # Pin Change Interrupt Enable 0
+
+# Module TIMER_COUNTER_4
+ 'TCCR4A' : '$c0', # Timer/Counter4 Control Registe
+ 'TCCR4A_COM4A': '$c0', # Compare Output Mode 1A, bits
+ 'TCCR4A_COM4B': '$30', # Compare Output Mode 4B, bits
+ 'TCCR4A_FOC4A': '$8', # Force Output Compare Match 4A
+ 'TCCR4A_FOC4B': '$4', # Force Output Compare Match 4B
+ 'TCCR4A_PWM4A': '$2', #
+ 'TCCR4A_PWM4B': '$1', #
+ 'TCCR4B' : '$c1', # Timer/Counter4 Control Registe
+ 'TCCR4B_PWM4X': '$80', # PWM Inversion Mode
+ 'TCCR4B_PSR4': '$40', # Prescaler Reset Timer/Counter
+ 'TCCR4B_DTPS4': '$30', # Dead Time Prescaler Bits
+ 'TCCR4B_CS4': '$f', # Clock Select Bits
+ 'TCCR4C' : '$c2', # Timer/Counter 4 Control Regist
+ 'TCCR4C_COM4A1S': '$80', # Comparator A Output Mode
+ 'TCCR4C_COM4A0S': '$40', # Comparator A Output Mode
+ 'TCCR4C_COM4B1S': '$20', # Comparator B Output Mode
+ 'TCCR4C_COM4B0S': '$10', # Comparator B Output Mode
+ 'TCCR4C_COM4D': '$c', # Comparator D Output Mode
+ 'TCCR4C_FOC4D': '$2', # Force Output Compare Match 4D
+ 'TCCR4C_PWM4D': '$1', # Pulse Width Modulator D Enable
+ 'TCCR4D' : '$c3', # Timer/Counter 4 Control Regist
+ 'TCCR4D_FPIE4': '$80', # Fault Protection Interrupt Ena
+ 'TCCR4D_FPEN4': '$40', # Fault Protection Mode Enable
+ 'TCCR4D_FPNC4': '$20', # Fault Protection Noise Cancele
+ 'TCCR4D_FPES4': '$10', # Fault Protection Edge Select
+ 'TCCR4D_FPAC4': '$8', # Fault Protection Analog Compar
+ 'TCCR4D_FPF4': '$4', # Fault Protection Interrupt Fla
+ 'TCCR4D_WGM4': '$3', # Waveform Generation Mode bits
+ 'TCCR4E' : '$c4', # Timer/Counter 4 Control Regist
+ 'TCCR4E_TLOCK4': '$80', # Register Update Lock
+ 'TCCR4E_ENHC4': '$40', # Enhanced Compare/PWM Mode
+ 'TCCR4E_OC4OE': '$3f', # Output Compare Override Enable
+ 'TCNT4' : '$be', # Timer/Counter4 Low Bytes
+ 'TC4H' : '$bf', # Timer/Counter4
+ 'OCR4A' : '$cf', # Timer/Counter4 Output Compare
+ 'OCR4B' : '$d0', # Timer/Counter4 Output Compare
+ 'OCR4C' : '$d1', # Timer/Counter4 Output Compare
+ 'OCR4D' : '$d2', # Timer/Counter4 Output Compare
+ 'TIMSK4' : '$72', # Timer/Counter4 Interrupt Mask
+ 'TIMSK4_OCIE4D': '$80', # Timer/Counter4 Output Compare
+ 'TIMSK4_OCIE4A': '$40', # Timer/Counter4 Output Compare
+ 'TIMSK4_OCIE4B': '$20', # Timer/Counter4 Output Compare
+ 'TIMSK4_TOIE4': '$4', # Timer/Counter4 Overflow Interr
+ 'TIFR4' : '$39', # Timer/Counter4 Interrupt Flag
+ 'TIFR4_OCF4D': '$80', # Output Compare Flag 4D
+ 'TIFR4_OCF4A': '$40', # Output Compare Flag 4A
+ 'TIFR4_OCF4B': '$20', # Output Compare Flag 4B
+ 'TIFR4_TOV4': '$4', # Timer/Counter4 Overflow Flag
+ 'DT4' : '$d4', # Timer/Counter 4 Dead Time Valu
+ 'DT4_DT4L': '$ff', # Timer/Counter 4 Dead Time Valu
+
+# Module PORTB
+ 'PORTB' : '$25', # Port B Data Register
+ 'DDRB' : '$24', # Port B Data Direction Register
+ 'PINB' : '$23', # Port B Input Pins
+
+# Module PORTC
+ 'PORTC' : '$28', # Port C Data Register
+ 'DDRC' : '$27', # Port C Data Direction Register
+ 'PINC' : '$26', # Port C Input Pins
+
+# Module PORTE
+ 'PORTE' : '$2e', # Data Register, Port E
+ 'DDRE' : '$2d', # Data Direction Register, Port
+ 'PINE' : '$2c', # Input Pins, Port E
+
+# Module PORTF
+ 'PORTF' : '$31', # Data Register, Port F
+ 'DDRF' : '$30', # Data Direction Register, Port
+ 'PINF' : '$2f', # Input Pins, Port F
+
+# Module TWI
+ 'TWAMR' : '$bd', # TWI (Slave) Address Mask Regis
+ 'TWAMR_TWAM': '$fe', #
+ 'TWBR' : '$b8', # TWI Bit Rate register
+ 'TWCR' : '$bc', # TWI Control Register
+ 'TWCR_TWINT': '$80', # TWI Interrupt Flag
+ 'TWCR_TWEA': '$40', # TWI Enable Acknowledge Bit
+ 'TWCR_TWSTA': '$20', # TWI Start Condition Bit
+ 'TWCR_TWSTO': '$10', # TWI Stop Condition Bit
+ 'TWCR_TWWC': '$8', # TWI Write Collition Flag
+ 'TWCR_TWEN': '$4', # TWI Enable Bit
+ 'TWCR_TWIE': '$1', # TWI Interrupt Enable
+ 'TWSR' : '$b9', # TWI Status Register
+ 'TWSR_TWS': '$f8', # TWI Status
+ 'TWSR_TWPS': '$3', # TWI Prescaler
+ 'TWDR' : '$bb', # TWI Data register
+ 'TWAR' : '$ba', # TWI (Slave) Address register
+ 'TWAR_TWA': '$fe', # TWI (Slave) Address register B
+ 'TWAR_TWGCE': '$1', # TWI General Call Recognition E
+
+# Module AD_CONVERTER
+ 'ADMUX' : '$7c', # The ADC multiplexer Selection
+ 'ADMUX_REFS': '$c0', # Reference Selection Bits
+ 'ADMUX_ADLAR': '$20', # Left Adjust Result
+ 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
+ 'ADCSRA' : '$7a', # The ADC Control and Status reg
+ 'ADCSRA_ADEN': '$80', # ADC Enable
+ 'ADCSRA_ADSC': '$40', # ADC Start Conversion
+ 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
+ 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
+ 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
+ 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
+ 'ADC' : '$78', # ADC Data Register Bytes
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ADHSM': '$80', # ADC High Speed Mode
+ 'ADCSRB_MUX5': '$20', # Analog Channel and Gain Select
+ 'ADCSRB_ADTS': '$17', # ADC Auto Trigger Sources
+ 'DIDR0' : '$7e', # Digital Input Disable Register
+ 'DIDR0_ADC7D': '$80', # ADC7 Digital input Disable
+ 'DIDR0_ADC6D': '$40', # ADC6 Digital input Disable
+ 'DIDR0_ADC5D': '$20', # ADC5 Digital input Disable
+ 'DIDR0_ADC4D': '$10', # ADC4 Digital input Disable
+ 'DIDR0_ADC3D': '$8', # ADC3 Digital input Disable
+ 'DIDR0_ADC2D': '$4', # ADC2 Digital input Disable
+ 'DIDR0_ADC1D': '$2', # ADC1 Digital input Disable
+ 'DIDR0_ADC0D': '$1', # ADC0 Digital input Disable
+ 'DIDR2' : '$7d', # Digital Input Disable Register
+ 'DIDR2_ADC13D': '$20', # ADC13 Digital input Disable
+ 'DIDR2_ADC12D': '$10', # ADC12 Digital input Disable
+ 'DIDR2_ADC11D': '$8', # ADC11 Digital input Disable
+ 'DIDR2_ADC10D': '$4', # ADC10 Digital input Disable
+ 'DIDR2_ADC9D': '$2', # ADC9 Digital input Disable
+ 'DIDR2_ADC8D': '$1', # ADC8 Digital input Disable
+
+# Module ANALOG_COMPARATOR
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
+ 'ACSR' : '$50', # Analog Comparator Control And
+ 'ACSR_ACD': '$80', # Analog Comparator Disable
+ 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
+ 'ACSR_ACO': '$20', # Analog Compare Output
+ 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
+ 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
+ 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
+ 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
+ 'DIDR1' : '$7f', #
+ 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
+ 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
+
+# Module CPU
+ 'SREG' : '$5f', # Status Register
+ 'SREG_I': '$80', # Global Interrupt Enable
+ 'SREG_T': '$40', # Bit Copy Storage
+ 'SREG_H': '$20', # Half Carry Flag
+ 'SREG_S': '$10', # Sign Bit
+ 'SREG_V': '$8', # Two's Complement Overflow Flag
+ 'SREG_N': '$4', # Negative Flag
+ 'SREG_Z': '$2', # Zero Flag
+ 'SREG_C': '$1', # Carry Flag
+ 'SP' : '$5d', # Stack Pointer
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_JTD': '$80', # JTAG Interface Disable
+ 'MCUCR_PUD': '$10', # Pull-up disable
+ 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
+ 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+ 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
+ 'MCUSR_BORF': '$4', # Brown-out Reset Flag
+ 'MCUSR_EXTRF': '$2', # External Reset Flag
+ 'MCUSR_PORF': '$1', # Power-on reset flag
+ 'OSCCAL' : '$66', # Oscillator Calibration Value
+ 'RCCTRL' : '$67', # Oscillator Control Register
+ 'RCCTRL_RCFREQ': '$1', #
+ 'CLKPR' : '$61', #
+ 'CLKPR_CLKPCE': '$80', #
+ 'CLKPR_CLKPS': '$f', #
+ 'SMCR' : '$53', # Sleep Mode Control Register
+ 'SMCR_SM': '$e', # Sleep Mode Select bits
+ 'SMCR_SE': '$1', # Sleep Enable
+ 'EIND' : '$5c', # Extended Indirect Register
+ 'GPIOR2' : '$4b', # General Purpose IO Register 2
+ 'GPIOR2_GPIOR': '$ff', # General Purpose IO Register 2
+ 'GPIOR1' : '$4a', # General Purpose IO Register 1
+ 'GPIOR1_GPIOR': '$ff', # General Purpose IO Register 1
+ 'GPIOR0' : '$3e', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR07': '$80', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR06': '$40', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR05': '$20', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR04': '$10', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR03': '$8', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR02': '$4', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR01': '$2', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR00': '$1', # General Purpose IO Register 0
+ 'PRR1' : '$65', # Power Reduction Register1
+ 'PRR1_PRUSB': '$80', # Power Reduction USB
+ 'PRR1_PRTIM3': '$8', # Power Reduction Timer/Counter3
+ 'PRR1_PRUSART1': '$1', # Power Reduction USART1
+ 'PRR0' : '$64', # Power Reduction Register0
+ 'PRR0_PRTWI': '$80', # Power Reduction TWI
+ 'PRR0_PRTIM2': '$40', # Power Reduction Timer/Counter2
+ 'PRR0_PRTIM0': '$20', # Power Reduction Timer/Counter0
+ 'PRR0_PRTIM1': '$8', # Power Reduction Timer/Counter1
+ 'PRR0_PRSPI': '$4', # Power Reduction Serial Periphe
+ 'PRR0_PRUSART0': '$2', # Power Reduction USART
+ 'PRR0_PRADC': '$1', # Power Reduction ADC
+ 'CLKSTA' : '$c7', #
+ 'CLKSTA_RCON': '$2', #
+ 'CLKSTA_EXTON': '$1', #
+ 'CLKSEL1' : '$c6', #
+ 'CLKSEL1_RCCKSEL': '$f0', #
+ 'CLKSEL1_EXCKSEL': '$f', #
+ 'CLKSEL0' : '$c5', #
+ 'CLKSEL0_RCSUT': '$c0', #
+ 'CLKSEL0_EXSUT': '$30', #
+ 'CLKSEL0_RCE': '$8', #
+ 'CLKSEL0_EXTE': '$4', #
+ 'CLKSEL0_CLKS': '$1', #
+
+# Module PLL
+ 'PLLCSR' : '$49', # PLL Status and Control registe
+ 'PLLCSR_PINDIV': '$10', # PLL prescaler Bit 2
+ 'PLLCSR_PLLE': '$2', # PLL Enable Bit
+ 'PLLCSR_PLOCK': '$1', # PLL Lock Status Bit
+ 'PLLFRQ' : '$52', # PLL Frequency Control Register
+ 'PLLFRQ_PINMUX': '$80', #
+ 'PLLFRQ_PLLUSB': '$40', #
+ 'PLLFRQ_PLLTM': '$30', #
+ 'PLLFRQ_PDIV': '$f', #
+
+# Module USB_DEVICE
+ 'UEINT' : '$f4', #
+ 'UEBCHX' : '$f3', #
+ 'UEBCLX' : '$f2', #
+ 'UEDATX' : '$f1', #
+ 'UEDATX_DAT': '$ff', #
+ 'UEIENX' : '$f0', #
+ 'UEIENX_FLERRE': '$80', #
+ 'UEIENX_NAKINE': '$40', #
+ 'UEIENX_NAKOUTE': '$10', #
+ 'UEIENX_RXSTPE': '$8', #
+ 'UEIENX_RXOUTE': '$4', #
+ 'UEIENX_STALLEDE': '$2', #
+ 'UEIENX_TXINE': '$1', #
+ 'UESTA1X' : '$ef', #
+ 'UESTA1X_CTRLDIR': '$4', #
+ 'UESTA1X_CURRBK': '$3', #
+ 'UESTA0X' : '$ee', #
+ 'UESTA0X_CFGOK': '$80', #
+ 'UESTA0X_OVERFI': '$40', #
+ 'UESTA0X_UNDERFI': '$20', #
+ 'UESTA0X_DTSEQ': '$c', #
+ 'UESTA0X_NBUSYBK': '$3', #
+ 'UECFG1X' : '$ed', #
+ 'UECFG1X_EPSIZE': '$70', #
+ 'UECFG1X_EPBK': '$c', #
+ 'UECFG1X_ALLOC': '$2', #
+ 'UECFG0X' : '$ec', #
+ 'UECFG0X_EPTYPE': '$c0', #
+ 'UECFG0X_EPDIR': '$1', #
+ 'UECONX' : '$eb', #
+ 'UECONX_STALLRQ': '$20', #
+ 'UECONX_STALLRQC': '$10', #
+ 'UECONX_RSTDT': '$8', #
+ 'UECONX_EPEN': '$1', #
+ 'UERST' : '$ea', #
+ 'UERST_EPRST': '$7f', #
+ 'UENUM' : '$e9', #
+ 'UEINTX' : '$e8', #
+ 'UEINTX_FIFOCON': '$80', #
+ 'UEINTX_NAKINI': '$40', #
+ 'UEINTX_RWAL': '$20', #
+ 'UEINTX_NAKOUTI': '$10', #
+ 'UEINTX_RXSTPI': '$8', #
+ 'UEINTX_RXOUTI': '$4', #
+ 'UEINTX_STALLEDI': '$2', #
+ 'UEINTX_TXINI': '$1', #
+ 'UDMFN' : '$e6', #
+ 'UDMFN_FNCERR': '$10', #
+ 'UDFNUM' : '$e4', #
+ 'UDADDR' : '$e3', #
+ 'UDADDR_ADDEN': '$80', #
+ 'UDADDR_UADD': '$7f', #
+ 'UDIEN' : '$e2', #
+ 'UDIEN_UPRSME': '$40', #
+ 'UDIEN_EORSME': '$20', #
+ 'UDIEN_WAKEUPE': '$10', #
+ 'UDIEN_EORSTE': '$8', #
+ 'UDIEN_SOFE': '$4', #
+ 'UDIEN_SUSPE': '$1', #
+ 'UDINT' : '$e1', #
+ 'UDINT_UPRSMI': '$40', #
+ 'UDINT_EORSMI': '$20', #
+ 'UDINT_WAKEUPI': '$10', #
+ 'UDINT_EORSTI': '$8', #
+ 'UDINT_SOFI': '$4', #
+ 'UDINT_SUSPI': '$1', #
+ 'UDCON' : '$e0', #
+ 'UDCON_LSM': '$4', # USB low speed mode
+ 'UDCON_RSTCPU': '$8', #
+ 'UDCON_RMWKUP': '$2', #
+ 'UDCON_DETACH': '$1', #
+ 'USBCON' : '$d8', # USB General Control Register
+ 'USBCON_USBE': '$80', #
+ 'USBCON_FRZCLK': '$20', #
+ 'USBCON_OTGPADE': '$10', #
+ 'USBCON_VBUSTE': '$1', #
+ 'USBINT' : '$da', #
+ 'USBINT_VBUSTI': '$1', #
+ 'USBSTA' : '$d9', #
+ 'USBSTA_SPEED': '$8', #
+ 'USBSTA_VBUS': '$1', #
+ 'UHWCON' : '$d7', #
+ 'UHWCON_UVREGE': '$1', #
+
+ '__amforth_dummy':'0'
+}
diff --git a/amforth-6.5/avr8/devices/atmega16u4/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega16u4/words/no-jtag.asm
new file mode 100644
index 0000000..352a4bb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega16u4/words/no-jtag.asm
@@ -0,0 +1,14 @@
+; ( -- )
+; ( -- )
+; MCU
+; disable jtag at runtime
+VE_NOJTAG:
+ .dw $FF05
+ .db "-jtag",0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOJTAG
+XT_NOJTAG:
+ .dw PFA_NOJTAG
+PFA_NOJTAG:
+
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega16u4/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega16u4/words/no-wdt.asm
new file mode 100644
index 0000000..ff6ddd1
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega16u4/words/no-wdt.asm
@@ -0,0 +1,34 @@
+; ( -- )
+; MCU
+; disable watch dog timer at runtime
+VE_NOWDT:
+ .dw $ff04
+ .db "-wdt"
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOWDT
+XT_NOWDT:
+ .dw PFA_NOWDT
+PFA_NOWDT:
+
+ in temp1,SREG
+ push temp1
+ ; Turn always off global interrupt.
+ cli
+ ; Reset Watchdog Timer
+ wdr
+ ; Clear WDRF in MCUSR
+ in temp1, MCUSR
+ andi temp1, (0xff & (0<<WDRF))
+ out MCUSR, temp1
+ ; Write logical one to WDCE and WDE
+ ; Keep old prescaler setting to prevent unintentional time-out
+ in_ temp1, WDTCSR
+ ori temp1, (1<<WDCE) | (1<<WDE)
+ out_ WDTCSR, temp1
+ ; Turn off WDT
+ ldi temp1, (0<<WDE)
+ out_ WDTCSR, temp1
+ ; restore status register
+ pop temp1
+ out SREG,temp1
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega16u4/words/sleep.asm b/amforth-6.5/avr8/devices/atmega16u4/words/sleep.asm
new file mode 100644
index 0000000..256249c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega16u4/words/sleep.asm
@@ -0,0 +1,19 @@
+; ( mode -- )
+; MCU
+; put the controller into the specified sleep mode
+VE_SLEEP:
+ .dw $ff05
+ .db "sleep", 0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_SLEEP
+XT_SLEEP:
+ .dw PFA_SLEEP
+PFA_SLEEP:
+ andi tosl, 7 ; leave only legal mode bits
+ lsl tosl ; move to correct location (bits 3-1)
+ ori tosl, 1 ; set the SE bit
+ out_ SMCR, tosl ; set the sleep config
+ sleep ; nighty-night
+ out_ SMCR, zerol ; 0 protects against accidental sleeps
+ loadtos ; pop argument from stack
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega2560/atmega2560.frt b/amforth-6.5/avr8/devices/atmega2560/atmega2560.frt
new file mode 100644
index 0000000..b73f112
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega2560/atmega2560.frt
@@ -0,0 +1,580 @@
+\ Partname: ATmega2560
+\ generated automatically
+
+\ ANALOG_COMPARATOR
+&123 constant ADCSRB \ ADC Control and Status Register B
+ $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer Enable
+&80 constant ACSR \ Analog Comparator Control And Status Register
+ $80 constant ACSR_ACD \ Analog Comparator Disable
+ $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
+ $20 constant ACSR_ACO \ Analog Compare Output
+ $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
+ $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
+ $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
+ $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
+&127 constant DIDR1 \ Digital Input Disable Register 1
+ $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
+ $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
+\ USART0
+&198 constant UDR0 \ USART I/O Data Register
+&192 constant UCSR0A \ USART Control and Status Register A
+ $80 constant UCSR0A_RXC0 \ USART Receive Complete
+ $40 constant UCSR0A_TXC0 \ USART Transmitt Complete
+ $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
+ $10 constant UCSR0A_FE0 \ Framing Error
+ $08 constant UCSR0A_DOR0 \ Data overRun
+ $04 constant UCSR0A_UPE0 \ Parity Error
+ $02 constant UCSR0A_U2X0 \ Double the USART transmission speed
+ $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
+&193 constant UCSR0B \ USART Control and Status Register B
+ $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
+ $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
+ $20 constant UCSR0B_UDRIE0 \ USART Data register Empty Interrupt Enable
+ $10 constant UCSR0B_RXEN0 \ Receiver Enable
+ $08 constant UCSR0B_TXEN0 \ Transmitter Enable
+ $04 constant UCSR0B_UCSZ02 \ Character Size
+ $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
+ $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
+&194 constant UCSR0C \ USART Control and Status Register C
+ $C0 constant UCSR0C_UMSEL0 \ USART Mode Select
+ $30 constant UCSR0C_UPM0 \ Parity Mode Bits
+ $08 constant UCSR0C_USBS0 \ Stop Bit Select
+ $06 constant UCSR0C_UCSZ0 \ Character Size
+ $01 constant UCSR0C_UCPOL0 \ Clock Polarity
+&196 constant UBRR0 \ USART Baud Rate Register Bytes
+\ TWI
+&189 constant TWAMR \ TWI (Slave) Address Mask Register
+ $FE constant TWAMR_TWAM \
+&184 constant TWBR \ TWI Bit Rate register
+&188 constant TWCR \ TWI Control Register
+ $80 constant TWCR_TWINT \ TWI Interrupt Flag
+ $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
+ $20 constant TWCR_TWSTA \ TWI Start Condition Bit
+ $10 constant TWCR_TWSTO \ TWI Stop Condition Bit
+ $08 constant TWCR_TWWC \ TWI Write Collition Flag
+ $04 constant TWCR_TWEN \ TWI Enable Bit
+ $01 constant TWCR_TWIE \ TWI Interrupt Enable
+&185 constant TWSR \ TWI Status Register
+ $F8 constant TWSR_TWS \ TWI Status
+ $03 constant TWSR_TWPS \ TWI Prescaler
+&187 constant TWDR \ TWI Data register
+&186 constant TWAR \ TWI (Slave) Address register
+ $FE constant TWAR_TWA \ TWI (Slave) Address register Bits
+ $01 constant TWAR_TWGCE \ TWI General Call Recognition Enable Bit
+\ SPI
+&76 constant SPCR \ SPI Control Register
+ $80 constant SPCR_SPIE \ SPI Interrupt Enable
+ $40 constant SPCR_SPE \ SPI Enable
+ $20 constant SPCR_DORD \ Data Order
+ $10 constant SPCR_MSTR \ Master/Slave Select
+ $08 constant SPCR_CPOL \ Clock polarity
+ $04 constant SPCR_CPHA \ Clock Phase
+ $03 constant SPCR_SPR \ SPI Clock Rate Selects
+&77 constant SPSR \ SPI Status Register
+ $80 constant SPSR_SPIF \ SPI Interrupt Flag
+ $40 constant SPSR_WCOL \ Write Collision Flag
+ $01 constant SPSR_SPI2X \ Double SPI Speed Bit
+&78 constant SPDR \ SPI Data Register
+\ PORTA
+&34 constant PORTA \ Port A Data Register
+&33 constant DDRA \ Port A Data Direction Register
+&32 constant PINA \ Port A Input Pins
+\ PORTB
+&37 constant PORTB \ Port B Data Register
+&36 constant DDRB \ Port B Data Direction Register
+&35 constant PINB \ Port B Input Pins
+\ PORTC
+&40 constant PORTC \ Port C Data Register
+&39 constant DDRC \ Port C Data Direction Register
+&38 constant PINC \ Port C Input Pins
+\ PORTD
+&43 constant PORTD \ Port D Data Register
+&42 constant DDRD \ Port D Data Direction Register
+&41 constant PIND \ Port D Input Pins
+\ PORTE
+&46 constant PORTE \ Data Register, Port E
+&45 constant DDRE \ Data Direction Register, Port E
+&44 constant PINE \ Input Pins, Port E
+\ PORTF
+&49 constant PORTF \ Data Register, Port F
+&48 constant DDRF \ Data Direction Register, Port F
+&47 constant PINF \ Input Pins, Port F
+\ PORTG
+&52 constant PORTG \ Data Register, Port G
+&51 constant DDRG \ Data Direction Register, Port G
+&50 constant PING \ Input Pins, Port G
+\ PORTH
+&258 constant PORTH \ PORT H Data Register
+&257 constant DDRH \ PORT H Data Direction Register
+&256 constant PINH \ PORT H Input Pins
+\ PORTJ
+&261 constant PORTJ \ PORT J Data Register
+&260 constant DDRJ \ PORT J Data Direction Register
+&259 constant PINJ \ PORT J Input Pins
+\ PORTK
+&264 constant PORTK \ PORT K Data Register
+&263 constant DDRK \ PORT K Data Direction Register
+&262 constant PINK \ PORT K Input Pins
+\ PORTL
+&267 constant PORTL \ PORT L Data Register
+&266 constant DDRL \ PORT L Data Direction Register
+&265 constant PINL \ PORT L Input Pins
+\ TIMER_COUNTER_0
+&72 constant OCR0B \ Timer/Counter0 Output Compare Register
+&71 constant OCR0A \ Timer/Counter0 Output Compare Register
+&70 constant TCNT0 \ Timer/Counter0
+&69 constant TCCR0B \ Timer/Counter Control Register B
+ $80 constant TCCR0B_FOC0A \ Force Output Compare A
+ $40 constant TCCR0B_FOC0B \ Force Output Compare B
+ $08 constant TCCR0B_WGM02 \
+ $07 constant TCCR0B_CS0 \ Clock Select
+&68 constant TCCR0A \ Timer/Counter Control Register A
+ $C0 constant TCCR0A_COM0A \ Compare Output Mode, Phase Correct PWM Mode
+ $30 constant TCCR0A_COM0B \ Compare Output Mode, Fast PWm
+ $03 constant TCCR0A_WGM0 \ Waveform Generation Mode
+&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
+ $04 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare Match B Interrupt Enable
+ $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match A Interrupt Enable
+ $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
+&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
+ $04 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare Flag 0B
+ $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0A
+ $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
+&67 constant GTCCR \ General Timer/Counter Control Register
+ $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
+ $01 constant GTCCR_PSRSYNC \ Prescaler Reset Timer/Counter1 and Timer/Counter0
+\ TIMER_COUNTER_2
+&112 constant TIMSK2 \ Timer/Counter Interrupt Mask register
+ $04 constant TIMSK2_OCIE2B \ Timer/Counter2 Output Compare Match B Interrupt Enable
+ $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match A Interrupt Enable
+ $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
+&55 constant TIFR2 \ Timer/Counter Interrupt Flag Register
+ $04 constant TIFR2_OCF2B \ Output Compare Flag 2B
+ $02 constant TIFR2_OCF2A \ Output Compare Flag 2A
+ $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
+&176 constant TCCR2A \ Timer/Counter2 Control Register A
+ $C0 constant TCCR2A_COM2A \ Compare Output Mode bits
+ $30 constant TCCR2A_COM2B \ Compare Output Mode bits
+ $03 constant TCCR2A_WGM2 \ Waveform Genration Mode
+&177 constant TCCR2B \ Timer/Counter2 Control Register B
+ $80 constant TCCR2B_FOC2A \ Force Output Compare A
+ $40 constant TCCR2B_FOC2B \ Force Output Compare B
+ $08 constant TCCR2B_WGM22 \ Waveform Generation Mode
+ $07 constant TCCR2B_CS2 \ Clock Select bits
+&178 constant TCNT2 \ Timer/Counter2
+&180 constant OCR2B \ Timer/Counter2 Output Compare Register B
+&179 constant OCR2A \ Timer/Counter2 Output Compare Register A
+&182 constant ASSR \ Asynchronous Status Register
+ $40 constant ASSR_EXCLK \ Enable External Clock Input
+ $20 constant ASSR_AS2 \ Asynchronous Timer/Counter2
+ $10 constant ASSR_TCN2UB \ Timer/Counter2 Update Busy
+ $08 constant ASSR_OCR2AUB \ Output Compare Register2 Update Busy
+ $04 constant ASSR_OCR2BUB \ Output Compare Register 2 Update Busy
+ $02 constant ASSR_TCR2AUB \ Timer/Counter Control Register2 Update Busy
+ $01 constant ASSR_TCR2BUB \ Timer/Counter Control Register2 Update Busy
+\ WATCHDOG
+&96 constant WDTCSR \ Watchdog Timer Control Register
+ $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Flag
+ $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Enable
+ $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
+ $10 constant WDTCSR_WDCE \ Watchdog Change Enable
+ $08 constant WDTCSR_WDE \ Watch Dog Enable
+\ USART1
+&206 constant UDR1 \ USART I/O Data Register
+&200 constant UCSR1A \ USART Control and Status Register A
+ $80 constant UCSR1A_RXC1 \ USART Receive Complete
+ $40 constant UCSR1A_TXC1 \ USART Transmitt Complete
+ $20 constant UCSR1A_UDRE1 \ USART Data Register Empty
+ $10 constant UCSR1A_FE1 \ Framing Error
+ $08 constant UCSR1A_DOR1 \ Data overRun
+ $04 constant UCSR1A_UPE1 \ Parity Error
+ $02 constant UCSR1A_U2X1 \ Double the USART transmission speed
+ $01 constant UCSR1A_MPCM1 \ Multi-processor Communication Mode
+&201 constant UCSR1B \ USART Control and Status Register B
+ $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable
+ $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable
+ $20 constant UCSR1B_UDRIE1 \ USART Data register Empty Interrupt Enable
+ $10 constant UCSR1B_RXEN1 \ Receiver Enable
+ $08 constant UCSR1B_TXEN1 \ Transmitter Enable
+ $04 constant UCSR1B_UCSZ12 \ Character Size
+ $02 constant UCSR1B_RXB81 \ Receive Data Bit 8
+ $01 constant UCSR1B_TXB81 \ Transmit Data Bit 8
+&202 constant UCSR1C \ USART Control and Status Register C
+ $C0 constant UCSR1C_UMSEL1 \ USART Mode Select
+ $30 constant UCSR1C_UPM1 \ Parity Mode Bits
+ $08 constant UCSR1C_USBS1 \ Stop Bit Select
+ $06 constant UCSR1C_UCSZ1 \ Character Size
+ $01 constant UCSR1C_UCPOL1 \ Clock Polarity
+&204 constant UBRR1 \ USART Baud Rate Register Bytes
+\ EEPROM
+&65 constant EEAR \ EEPROM Address Register Low Bytes
+&64 constant EEDR \ EEPROM Data Register
+&63 constant EECR \ EEPROM Control Register
+ $30 constant EECR_EEPM \ EEPROM Programming Mode Bits
+ $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
+ $04 constant EECR_EEMPE \ EEPROM Master Write Enable
+ $02 constant EECR_EEPE \ EEPROM Write Enable
+ $01 constant EECR_EERE \ EEPROM Read Enable
+\ TIMER_COUNTER_5
+&288 constant TCCR5A \ Timer/Counter5 Control Register A
+ $C0 constant TCCR5A_COM5A \ Compare Output Mode 1A, bits
+ $30 constant TCCR5A_COM5B \ Compare Output Mode 5B, bits
+ $0C constant TCCR5A_COM5C \ Compare Output Mode 5C, bits
+ $03 constant TCCR5A_WGM5 \ Waveform Generation Mode
+&289 constant TCCR5B \ Timer/Counter5 Control Register B
+ $80 constant TCCR5B_ICNC5 \ Input Capture 5 Noise Canceler
+ $40 constant TCCR5B_ICES5 \ Input Capture 5 Edge Select
+ $18 constant TCCR5B_WGM5 \ Waveform Generation Mode
+ $07 constant TCCR5B_CS5 \ Prescaler source of Timer/Counter 5
+&290 constant TCCR5C \ Timer/Counter 5 Control Register C
+ $80 constant TCCR5C_FOC5A \ Force Output Compare 5A
+ $40 constant TCCR5C_FOC5B \ Force Output Compare 5B
+ $20 constant TCCR5C_FOC5C \ Force Output Compare 5C
+&292 constant TCNT5 \ Timer/Counter5 Bytes
+&296 constant OCR5A \ Timer/Counter5 Output Compare Register A Bytes
+&298 constant OCR5B \ Timer/Counter5 Output Compare Register B Bytes
+&300 constant OCR5C \ Timer/Counter5 Output Compare Register B Bytes
+&294 constant ICR5 \ Timer/Counter5 Input Capture Register Bytes
+&115 constant TIMSK5 \ Timer/Counter5 Interrupt Mask Register
+ $20 constant TIMSK5_ICIE5 \ Timer/Counter5 Input Capture Interrupt Enable
+ $08 constant TIMSK5_OCIE5C \ Timer/Counter5 Output Compare C Match Interrupt Enable
+ $04 constant TIMSK5_OCIE5B \ Timer/Counter5 Output Compare B Match Interrupt Enable
+ $02 constant TIMSK5_OCIE5A \ Timer/Counter5 Output Compare A Match Interrupt Enable
+ $01 constant TIMSK5_TOIE5 \ Timer/Counter5 Overflow Interrupt Enable
+&58 constant TIFR5 \ Timer/Counter5 Interrupt Flag register
+ $20 constant TIFR5_ICF5 \ Input Capture Flag 5
+ $08 constant TIFR5_OCF5C \ Output Compare Flag 5C
+ $04 constant TIFR5_OCF5B \ Output Compare Flag 5B
+ $02 constant TIFR5_OCF5A \ Output Compare Flag 5A
+ $01 constant TIFR5_TOV5 \ Timer/Counter5 Overflow Flag
+\ TIMER_COUNTER_4
+&160 constant TCCR4A \ Timer/Counter4 Control Register A
+ $C0 constant TCCR4A_COM4A \ Compare Output Mode 1A, bits
+ $30 constant TCCR4A_COM4B \ Compare Output Mode 4B, bits
+ $0C constant TCCR4A_COM4C \ Compare Output Mode 4C, bits
+ $03 constant TCCR4A_WGM4 \ Waveform Generation Mode
+&161 constant TCCR4B \ Timer/Counter4 Control Register B
+ $80 constant TCCR4B_ICNC4 \ Input Capture 4 Noise Canceler
+ $40 constant TCCR4B_ICES4 \ Input Capture 4 Edge Select
+ $18 constant TCCR4B_WGM4 \ Waveform Generation Mode
+ $07 constant TCCR4B_CS4 \ Prescaler source of Timer/Counter 4
+&162 constant TCCR4C \ Timer/Counter 4 Control Register C
+ $80 constant TCCR4C_FOC4A \ Force Output Compare 4A
+ $40 constant TCCR4C_FOC4B \ Force Output Compare 4B
+ $20 constant TCCR4C_FOC4C \ Force Output Compare 4C
+&164 constant TCNT4 \ Timer/Counter4 Bytes
+&168 constant OCR4A \ Timer/Counter4 Output Compare Register A Bytes
+&170 constant OCR4B \ Timer/Counter4 Output Compare Register B Bytes
+&172 constant OCR4C \ Timer/Counter4 Output Compare Register B Bytes
+&166 constant ICR4 \ Timer/Counter4 Input Capture Register Bytes
+&114 constant TIMSK4 \ Timer/Counter4 Interrupt Mask Register
+ $20 constant TIMSK4_ICIE4 \ Timer/Counter4 Input Capture Interrupt Enable
+ $08 constant TIMSK4_OCIE4C \ Timer/Counter4 Output Compare C Match Interrupt Enable
+ $04 constant TIMSK4_OCIE4B \ Timer/Counter4 Output Compare B Match Interrupt Enable
+ $02 constant TIMSK4_OCIE4A \ Timer/Counter4 Output Compare A Match Interrupt Enable
+ $01 constant TIMSK4_TOIE4 \ Timer/Counter4 Overflow Interrupt Enable
+&57 constant TIFR4 \ Timer/Counter4 Interrupt Flag register
+ $20 constant TIFR4_ICF4 \ Input Capture Flag 4
+ $08 constant TIFR4_OCF4C \ Output Compare Flag 4C
+ $04 constant TIFR4_OCF4B \ Output Compare Flag 4B
+ $02 constant TIFR4_OCF4A \ Output Compare Flag 4A
+ $01 constant TIFR4_TOV4 \ Timer/Counter4 Overflow Flag
+\ TIMER_COUNTER_3
+&144 constant TCCR3A \ Timer/Counter3 Control Register A
+ $C0 constant TCCR3A_COM3A \ Compare Output Mode 1A, bits
+ $30 constant TCCR3A_COM3B \ Compare Output Mode 3B, bits
+ $0C constant TCCR3A_COM3C \ Compare Output Mode 3C, bits
+ $03 constant TCCR3A_WGM3 \ Waveform Generation Mode
+&145 constant TCCR3B \ Timer/Counter3 Control Register B
+ $80 constant TCCR3B_ICNC3 \ Input Capture 3 Noise Canceler
+ $40 constant TCCR3B_ICES3 \ Input Capture 3 Edge Select
+ $18 constant TCCR3B_WGM3 \ Waveform Generation Mode
+ $07 constant TCCR3B_CS3 \ Prescaler source of Timer/Counter 3
+&146 constant TCCR3C \ Timer/Counter 3 Control Register C
+ $80 constant TCCR3C_FOC3A \ Force Output Compare 3A
+ $40 constant TCCR3C_FOC3B \ Force Output Compare 3B
+ $20 constant TCCR3C_FOC3C \ Force Output Compare 3C
+&148 constant TCNT3 \ Timer/Counter3 Bytes
+&152 constant OCR3A \ Timer/Counter3 Output Compare Register A Bytes
+&154 constant OCR3B \ Timer/Counter3 Output Compare Register B Bytes
+&156 constant OCR3C \ Timer/Counter3 Output Compare Register B Bytes
+&150 constant ICR3 \ Timer/Counter3 Input Capture Register Bytes
+&113 constant TIMSK3 \ Timer/Counter3 Interrupt Mask Register
+ $20 constant TIMSK3_ICIE3 \ Timer/Counter3 Input Capture Interrupt Enable
+ $08 constant TIMSK3_OCIE3C \ Timer/Counter3 Output Compare C Match Interrupt Enable
+ $04 constant TIMSK3_OCIE3B \ Timer/Counter3 Output Compare B Match Interrupt Enable
+ $02 constant TIMSK3_OCIE3A \ Timer/Counter3 Output Compare A Match Interrupt Enable
+ $01 constant TIMSK3_TOIE3 \ Timer/Counter3 Overflow Interrupt Enable
+&56 constant TIFR3 \ Timer/Counter3 Interrupt Flag register
+ $20 constant TIFR3_ICF3 \ Input Capture Flag 3
+ $08 constant TIFR3_OCF3C \ Output Compare Flag 3C
+ $04 constant TIFR3_OCF3B \ Output Compare Flag 3B
+ $02 constant TIFR3_OCF3A \ Output Compare Flag 3A
+ $01 constant TIFR3_TOV3 \ Timer/Counter3 Overflow Flag
+\ TIMER_COUNTER_1
+&128 constant TCCR1A \ Timer/Counter1 Control Register A
+ $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
+ $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
+ $0C constant TCCR1A_COM1C \ Compare Output Mode 1C, bits
+ $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
+&129 constant TCCR1B \ Timer/Counter1 Control Register B
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
+ $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
+&130 constant TCCR1C \ Timer/Counter 1 Control Register C
+ $80 constant TCCR1C_FOC1A \ Force Output Compare 1A
+ $40 constant TCCR1C_FOC1B \ Force Output Compare 1B
+ $20 constant TCCR1C_FOC1C \ Force Output Compare 1C
+&132 constant TCNT1 \ Timer/Counter1 Bytes
+&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
+&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
+&140 constant OCR1C \ Timer/Counter1 Output Compare Register C Bytes
+&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
+&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
+ $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
+ $08 constant TIMSK1_OCIE1C \ Timer/Counter1 Output Compare C Match Interrupt Enable
+ $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
+ $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
+ $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
+&54 constant TIFR1 \ Timer/Counter1 Interrupt Flag register
+ $20 constant TIFR1_ICF1 \ Input Capture Flag 1
+ $08 constant TIFR1_OCF1C \ Output Compare Flag 1C
+ $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
+ $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
+ $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
+\ JTAG
+&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
+&85 constant MCUCR \ MCU Control Register
+ $80 constant MCUCR_JTD \ JTAG Interface Disable
+&84 constant MCUSR \ MCU Status Register
+ $10 constant MCUSR_JTRF \ JTAG Reset Flag
+\ EXTERNAL_INTERRUPT
+&105 constant EICRA \ External Interrupt Control Register A
+ $C0 constant EICRA_ISC3 \ External Interrupt Sense Control Bit
+ $30 constant EICRA_ISC2 \ External Interrupt Sense Control Bit
+ $0C constant EICRA_ISC1 \ External Interrupt Sense Control Bit
+ $03 constant EICRA_ISC0 \ External Interrupt Sense Control Bit
+&106 constant EICRB \ External Interrupt Control Register B
+ $C0 constant EICRB_ISC7 \ External Interrupt 7-4 Sense Control Bit
+ $30 constant EICRB_ISC6 \ External Interrupt 7-4 Sense Control Bit
+ $0C constant EICRB_ISC5 \ External Interrupt 7-4 Sense Control Bit
+ $03 constant EICRB_ISC4 \ External Interrupt 7-4 Sense Control Bit
+&61 constant EIMSK \ External Interrupt Mask Register
+ $FF constant EIMSK_INT \ External Interrupt Request 7 Enable
+&60 constant EIFR \ External Interrupt Flag Register
+ $FF constant EIFR_INTF \ External Interrupt Flags
+&109 constant PCMSK2 \ Pin Change Mask Register 2
+&108 constant PCMSK1 \ Pin Change Mask Register 1
+&107 constant PCMSK0 \ Pin Change Mask Register 0
+&59 constant PCIFR \ Pin Change Interrupt Flag Register
+ $07 constant PCIFR_PCIF \ Pin Change Interrupt Flags
+&104 constant PCICR \ Pin Change Interrupt Control Register
+ $07 constant PCICR_PCIE \ Pin Change Interrupt Enables
+\ CPU
+&95 constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ $08 constant SREG_V \ Two's Complement Overflow Flag
+ $04 constant SREG_N \ Negative Flag
+ $02 constant SREG_Z \ Zero Flag
+ $01 constant SREG_C \ Carry Flag
+&93 constant SP \ Stack Pointer
+&116 constant XMCRA \ External Memory Control Register A
+ $80 constant XMCRA_SRE \ External SRAM Enable
+ $70 constant XMCRA_SRL \ Wait state page limit
+ $0C constant XMCRA_SRW1 \ Wait state select bit upper page
+ $03 constant XMCRA_SRW0 \ Wait state select bit lower page
+&117 constant XMCRB \ External Memory Control Register B
+ $80 constant XMCRB_XMBK \ External Memory Bus Keeper Enable
+ $07 constant XMCRB_XMM \ External Memory High Mask
+&102 constant OSCCAL \ Oscillator Calibration Value
+&97 constant CLKPR \
+ $80 constant CLKPR_CLKPCE \
+ $0F constant CLKPR_CLKPS \
+&83 constant SMCR \ Sleep Mode Control Register
+ $0E constant SMCR_SM \ Sleep Mode Select bits
+ $01 constant SMCR_SE \ Sleep Enable
+&92 constant EIND \ Extended Indirect Register
+&91 constant RAMPZ \ RAM Page Z Select Register
+&75 constant GPIOR2 \ General Purpose IO Register 2
+ $FF constant GPIOR2_GPIOR \ General Purpose IO Register 2 bis
+&74 constant GPIOR1 \ General Purpose IO Register 1
+ $FF constant GPIOR1_GPIOR \ General Purpose IO Register 1 bis
+&62 constant GPIOR0 \ General Purpose IO Register 0
+ $80 constant GPIOR0_GPIOR07 \ General Purpose IO Register 0 bit 7
+ $40 constant GPIOR0_GPIOR06 \ General Purpose IO Register 0 bit 6
+ $20 constant GPIOR0_GPIOR05 \ General Purpose IO Register 0 bit 5
+ $10 constant GPIOR0_GPIOR04 \ General Purpose IO Register 0 bit 4
+ $08 constant GPIOR0_GPIOR03 \ General Purpose IO Register 0 bit 3
+ $04 constant GPIOR0_GPIOR02 \ General Purpose IO Register 0 bit 2
+ $02 constant GPIOR0_GPIOR01 \ General Purpose IO Register 0 bit 1
+ $01 constant GPIOR0_GPIOR00 \ General Purpose IO Register 0 bit 0
+&101 constant PRR1 \ Power Reduction Register1
+ $20 constant PRR1_PRTIM5 \ Power Reduction Timer/Counter5
+ $10 constant PRR1_PRTIM4 \ Power Reduction Timer/Counter4
+ $08 constant PRR1_PRTIM3 \ Power Reduction Timer/Counter3
+ $07 constant PRR1_PRUSART \ Power Reduction USART3
+&100 constant PRR0 \ Power Reduction Register0
+ $80 constant PRR0_PRTWI \ Power Reduction TWI
+ $40 constant PRR0_PRTIM2 \ Power Reduction Timer/Counter2
+ $20 constant PRR0_PRTIM0 \ Power Reduction Timer/Counter0
+ $08 constant PRR0_PRTIM1 \ Power Reduction Timer/Counter1
+ $04 constant PRR0_PRSPI \ Power Reduction Serial Peripheral Interface
+ $02 constant PRR0_PRUSART0 \ Power Reduction USART
+ $01 constant PRR0_PRADC \ Power Reduction ADC
+\ AD_CONVERTER
+&124 constant ADMUX \ The ADC multiplexer Selection Register
+ $C0 constant ADMUX_REFS \ Reference Selection Bits
+ $20 constant ADMUX_ADLAR \ Left Adjust Result
+ $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
+&120 constant ADC \ ADC Data Register Bytes
+&122 constant ADCSRA \ The ADC Control and Status register A
+ $80 constant ADCSRA_ADEN \ ADC Enable
+ $40 constant ADCSRA_ADSC \ ADC Start Conversion
+ $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
+ $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
+ $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
+ $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
+&125 constant DIDR2 \ Digital Input Disable Register
+ $80 constant DIDR2_ADC15D \
+ $40 constant DIDR2_ADC14D \
+ $20 constant DIDR2_ADC13D \
+ $10 constant DIDR2_ADC12D \
+ $08 constant DIDR2_ADC11D \
+ $04 constant DIDR2_ADC10D \
+ $02 constant DIDR2_ADC9D \
+ $01 constant DIDR2_ADC8D \
+&126 constant DIDR0 \ Digital Input Disable Register
+ $80 constant DIDR0_ADC7D \
+ $40 constant DIDR0_ADC6D \
+ $20 constant DIDR0_ADC5D \
+ $10 constant DIDR0_ADC4D \
+ $08 constant DIDR0_ADC3D \
+ $04 constant DIDR0_ADC2D \
+ $02 constant DIDR0_ADC1D \
+ $01 constant DIDR0_ADC0D \
+\ BOOT_LOAD
+&87 constant SPMCSR \ Store Program Memory Control Register
+ $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
+ $20 constant SPMCSR_SIGRD \ Signature Row Read
+ $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
+ $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
+ $04 constant SPMCSR_PGWRT \ Page Write
+ $02 constant SPMCSR_PGERS \ Page Erase
+ $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
+\ USART2
+&214 constant UDR2 \ USART I/O Data Register
+&208 constant UCSR2A \ USART Control and Status Register A
+ $80 constant UCSR2A_RXC2 \ USART Receive Complete
+ $40 constant UCSR2A_TXC2 \ USART Transmitt Complete
+ $20 constant UCSR2A_UDRE2 \ USART Data Register Empty
+ $10 constant UCSR2A_FE2 \ Framing Error
+ $08 constant UCSR2A_DOR2 \ Data overRun
+ $04 constant UCSR2A_UPE2 \ Parity Error
+ $02 constant UCSR2A_U2X2 \ Double the USART transmission speed
+ $01 constant UCSR2A_MPCM2 \ Multi-processor Communication Mode
+&209 constant UCSR2B \ USART Control and Status Register B
+ $80 constant UCSR2B_RXCIE2 \ RX Complete Interrupt Enable
+ $40 constant UCSR2B_TXCIE2 \ TX Complete Interrupt Enable
+ $20 constant UCSR2B_UDRIE2 \ USART Data register Empty Interrupt Enable
+ $10 constant UCSR2B_RXEN2 \ Receiver Enable
+ $08 constant UCSR2B_TXEN2 \ Transmitter Enable
+ $04 constant UCSR2B_UCSZ22 \ Character Size
+ $02 constant UCSR2B_RXB82 \ Receive Data Bit 8
+ $01 constant UCSR2B_TXB82 \ Transmit Data Bit 8
+&210 constant UCSR2C \ USART Control and Status Register C
+ $C0 constant UCSR2C_UMSEL2 \ USART Mode Select
+ $30 constant UCSR2C_UPM2 \ Parity Mode Bits
+ $08 constant UCSR2C_USBS2 \ Stop Bit Select
+ $06 constant UCSR2C_UCSZ2 \ Character Size
+ $01 constant UCSR2C_UCPOL2 \ Clock Polarity
+&212 constant UBRR2 \ USART Baud Rate Register Bytes
+\ USART3
+&310 constant UDR3 \ USART I/O Data Register
+&304 constant UCSR3A \ USART Control and Status Register A
+ $80 constant UCSR3A_RXC3 \ USART Receive Complete
+ $40 constant UCSR3A_TXC3 \ USART Transmitt Complete
+ $20 constant UCSR3A_UDRE3 \ USART Data Register Empty
+ $10 constant UCSR3A_FE3 \ Framing Error
+ $08 constant UCSR3A_DOR3 \ Data overRun
+ $04 constant UCSR3A_UPE3 \ Parity Error
+ $02 constant UCSR3A_U2X3 \ Double the USART transmission speed
+ $01 constant UCSR3A_MPCM3 \ Multi-processor Communication Mode
+&305 constant UCSR3B \ USART Control and Status Register B
+ $80 constant UCSR3B_RXCIE3 \ RX Complete Interrupt Enable
+ $40 constant UCSR3B_TXCIE3 \ TX Complete Interrupt Enable
+ $20 constant UCSR3B_UDRIE3 \ USART Data register Empty Interrupt Enable
+ $10 constant UCSR3B_RXEN3 \ Receiver Enable
+ $08 constant UCSR3B_TXEN3 \ Transmitter Enable
+ $04 constant UCSR3B_UCSZ32 \ Character Size
+ $02 constant UCSR3B_RXB83 \ Receive Data Bit 8
+ $01 constant UCSR3B_TXB83 \ Transmit Data Bit 8
+&306 constant UCSR3C \ USART Control and Status Register C
+ $C0 constant UCSR3C_UMSEL3 \ USART Mode Select
+ $30 constant UCSR3C_UPM3 \ Parity Mode Bits
+ $08 constant UCSR3C_USBS3 \ Stop Bit Select
+ $06 constant UCSR3C_UCSZ3 \ Character Size
+ $01 constant UCSR3C_UCPOL3 \ Clock Polarity
+&308 constant UBRR3 \ USART Baud Rate Register Bytes
+
+\ Interrupts
+&2 constant INT0Addr \ External Interrupt Request 0
+&4 constant INT1Addr \ External Interrupt Request 1
+&6 constant INT2Addr \ External Interrupt Request 2
+&8 constant INT3Addr \ External Interrupt Request 3
+&10 constant INT4Addr \ External Interrupt Request 4
+&12 constant INT5Addr \ External Interrupt Request 5
+&14 constant INT6Addr \ External Interrupt Request 6
+&16 constant INT7Addr \ External Interrupt Request 7
+&18 constant PCINT0Addr \ Pin Change Interrupt Request 0
+&20 constant PCINT1Addr \ Pin Change Interrupt Request 1
+&22 constant PCINT2Addr \ Pin Change Interrupt Request 2
+&24 constant WDTAddr \ Watchdog Time-out Interrupt
+&26 constant TIMER2_COMPAAddr \ Timer/Counter2 Compare Match A
+&28 constant TIMER2_COMPBAddr \ Timer/Counter2 Compare Match B
+&30 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
+&32 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+&34 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
+&36 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
+&38 constant TIMER1_COMPCAddr \ Timer/Counter1 Compare Match C
+&40 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+&42 constant TIMER0_COMPAAddr \ Timer/Counter0 Compare Match A
+&44 constant TIMER0_COMPBAddr \ Timer/Counter0 Compare Match B
+&46 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
+&48 constant SPI__STCAddr \ SPI Serial Transfer Complete
+&50 constant USART0__RXAddr \ USART0, Rx Complete
+&52 constant USART0__UDREAddr \ USART0 Data register Empty
+&54 constant USART0__TXAddr \ USART0, Tx Complete
+&56 constant ANALOG_COMPAddr \ Analog Comparator
+&58 constant ADCAddr \ ADC Conversion Complete
+&60 constant EE_READYAddr \ EEPROM Ready
+&62 constant TIMER3_CAPTAddr \ Timer/Counter3 Capture Event
+&64 constant TIMER3_COMPAAddr \ Timer/Counter3 Compare Match A
+&66 constant TIMER3_COMPBAddr \ Timer/Counter3 Compare Match B
+&68 constant TIMER3_COMPCAddr \ Timer/Counter3 Compare Match C
+&70 constant TIMER3_OVFAddr \ Timer/Counter3 Overflow
+&72 constant USART1__RXAddr \ USART1, Rx Complete
+&74 constant USART1__UDREAddr \ USART1 Data register Empty
+&76 constant USART1__TXAddr \ USART1, Tx Complete
+&78 constant TWIAddr \ 2-wire Serial Interface
+&80 constant SPM_READYAddr \ Store Program Memory Read
+&82 constant TIMER4_CAPTAddr \ Timer/Counter4 Capture Event
+&84 constant TIMER4_COMPAAddr \ Timer/Counter4 Compare Match A
+&86 constant TIMER4_COMPBAddr \ Timer/Counter4 Compare Match B
+&88 constant TIMER4_COMPCAddr \ Timer/Counter4 Compare Match C
+&90 constant TIMER4_OVFAddr \ Timer/Counter4 Overflow
+&92 constant TIMER5_CAPTAddr \ Timer/Counter5 Capture Event
+&94 constant TIMER5_COMPAAddr \ Timer/Counter5 Compare Match A
+&96 constant TIMER5_COMPBAddr \ Timer/Counter5 Compare Match B
+&98 constant TIMER5_COMPCAddr \ Timer/Counter5 Compare Match C
+&100 constant TIMER5_OVFAddr \ Timer/Counter5 Overflow
+&102 constant USART2__RXAddr \ USART2, Rx Complete
+&104 constant USART2__UDREAddr \ USART2 Data register Empty
+&106 constant USART2__TXAddr \ USART2, Tx Complete
+&108 constant USART3__RXAddr \ USART3, Rx Complete
+&110 constant USART3__UDREAddr \ USART3 Data register Empty
+&112 constant USART3__TXAddr \ USART3, Tx Complete
diff --git a/amforth-6.5/avr8/devices/atmega2560/device.asm b/amforth-6.5/avr8/devices/atmega2560/device.asm
new file mode 100644
index 0000000..7f07ee1
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega2560/device.asm
@@ -0,0 +1,190 @@
+; Partname: ATmega2560
+; generated automatically, do not edit
+
+.nolist
+ .include "m2560def.inc"
+.list
+
+.equ ramstart = 512
+.equ CELLSIZE = 2
+.macro readflashcell
+ clr temp7
+ lsl zl
+ rol zh
+ rol temp7
+ out_ RAMPZ, temp7
+ elpm @0, Z+
+ elpm @1, Z+
+.endmacro
+.macro writeflashcell
+ clr temp7
+ lsl zl
+ rol zh
+ rol temp7
+ out_ RAMPZ, temp7
+.endmacro
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_USART0 = 0
+.set WANT_TWI = 0
+.set WANT_SPI = 0
+.set WANT_PORTA = 0
+.set WANT_PORTB = 0
+.set WANT_PORTC = 0
+.set WANT_PORTD = 0
+.set WANT_PORTE = 0
+.set WANT_PORTF = 0
+.set WANT_PORTG = 0
+.set WANT_PORTH = 0
+.set WANT_PORTJ = 0
+.set WANT_PORTK = 0
+.set WANT_PORTL = 0
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_TIMER_COUNTER_2 = 0
+.set WANT_WATCHDOG = 0
+.set WANT_USART1 = 0
+.set WANT_EEPROM = 0
+.set WANT_TIMER_COUNTER_5 = 0
+.set WANT_TIMER_COUNTER_4 = 0
+.set WANT_TIMER_COUNTER_3 = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_JTAG = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_CPU = 0
+.set WANT_AD_CONVERTER = 0
+.set WANT_BOOT_LOAD = 0
+.set WANT_USART2 = 0
+.set WANT_USART3 = 0
+.equ intvecsize = 2 ; please verify; flash size: 262144 bytes
+.equ pclen = 3 ; please verify
+.overlap
+.org 2
+ rcall isr ; External Interrupt Request 0
+.org 4
+ rcall isr ; External Interrupt Request 1
+.org 6
+ rcall isr ; External Interrupt Request 2
+.org 8
+ rcall isr ; External Interrupt Request 3
+.org 10
+ rcall isr ; External Interrupt Request 4
+.org 12
+ rcall isr ; External Interrupt Request 5
+.org 14
+ rcall isr ; External Interrupt Request 6
+.org 16
+ rcall isr ; External Interrupt Request 7
+.org 18
+ rcall isr ; Pin Change Interrupt Request 0
+.org 20
+ rcall isr ; Pin Change Interrupt Request 1
+.org 22
+ rcall isr ; Pin Change Interrupt Request 2
+.org 24
+ rcall isr ; Watchdog Time-out Interrupt
+.org 26
+ rcall isr ; Timer/Counter2 Compare Match A
+.org 28
+ rcall isr ; Timer/Counter2 Compare Match B
+.org 30
+ rcall isr ; Timer/Counter2 Overflow
+.org 32
+ rcall isr ; Timer/Counter1 Capture Event
+.org 34
+ rcall isr ; Timer/Counter1 Compare Match A
+.org 36
+ rcall isr ; Timer/Counter1 Compare Match B
+.org 38
+ rcall isr ; Timer/Counter1 Compare Match C
+.org 40
+ rcall isr ; Timer/Counter1 Overflow
+.org 42
+ rcall isr ; Timer/Counter0 Compare Match A
+.org 44
+ rcall isr ; Timer/Counter0 Compare Match B
+.org 46
+ rcall isr ; Timer/Counter0 Overflow
+.org 48
+ rcall isr ; SPI Serial Transfer Complete
+.org 50
+ rcall isr ; USART0, Rx Complete
+.org 52
+ rcall isr ; USART0 Data register Empty
+.org 54
+ rcall isr ; USART0, Tx Complete
+.org 56
+ rcall isr ; Analog Comparator
+.org 58
+ rcall isr ; ADC Conversion Complete
+.org 60
+ rcall isr ; EEPROM Ready
+.org 62
+ rcall isr ; Timer/Counter3 Capture Event
+.org 64
+ rcall isr ; Timer/Counter3 Compare Match A
+.org 66
+ rcall isr ; Timer/Counter3 Compare Match B
+.org 68
+ rcall isr ; Timer/Counter3 Compare Match C
+.org 70
+ rcall isr ; Timer/Counter3 Overflow
+.org 72
+ rcall isr ; USART1, Rx Complete
+.org 74
+ rcall isr ; USART1 Data register Empty
+.org 76
+ rcall isr ; USART1, Tx Complete
+.org 78
+ rcall isr ; 2-wire Serial Interface
+.org 80
+ rcall isr ; Store Program Memory Read
+.org 82
+ rcall isr ; Timer/Counter4 Capture Event
+.org 84
+ rcall isr ; Timer/Counter4 Compare Match A
+.org 86
+ rcall isr ; Timer/Counter4 Compare Match B
+.org 88
+ rcall isr ; Timer/Counter4 Compare Match C
+.org 90
+ rcall isr ; Timer/Counter4 Overflow
+.org 92
+ rcall isr ; Timer/Counter5 Capture Event
+.org 94
+ rcall isr ; Timer/Counter5 Compare Match A
+.org 96
+ rcall isr ; Timer/Counter5 Compare Match B
+.org 98
+ rcall isr ; Timer/Counter5 Compare Match C
+.org 100
+ rcall isr ; Timer/Counter5 Overflow
+.org 102
+ rcall isr ; USART2, Rx Complete
+.org 104
+ rcall isr ; USART2 Data register Empty
+.org 106
+ rcall isr ; USART2, Tx Complete
+.org 108
+ rcall isr ; USART3, Rx Complete
+.org 110
+ rcall isr ; USART3 Data register Empty
+.org 112
+ rcall isr ; USART3, Tx Complete
+.equ INTVECTORS = 57
+.nooverlap
+
+; compatability layer (maybe empty)
+
+; controller data area, environment query mcu-info
+mcu_info:
+mcu_ramsize:
+ .dw 8192
+mcu_eepromsize:
+ .dw 4096
+mcu_maxdp:
+ .dw 65535
+mcu_numints:
+ .dw 57
+mcu_name:
+ .dw 10
+ .db "ATmega2560"
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega2560/device.inc b/amforth-6.5/avr8/devices/atmega2560/device.inc
new file mode 100644
index 0000000..a683c18
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega2560/device.inc
@@ -0,0 +1,1980 @@
+; Partname: ATmega2560
+; generated automatically, no not edit
+
+.if WANT_ANALOG_COMPARATOR == 1
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Control and Status Register B
+VE_ADCSRB:
+ .dw $ff06
+ .db "ADCSRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRB
+XT_ADCSRB:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRB:
+ .dw 123
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Control And Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw 80
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 1
+VE_DIDR1:
+ .dw $ff05
+ .db "DIDR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR1
+XT_DIDR1:
+ .dw PFA_DOVARIABLE
+PFA_DIDR1:
+ .dw 127
+
+.endif
+.if WANT_USART0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR0:
+ .dw $ff04
+ .db "UDR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR0
+XT_UDR0:
+ .dw PFA_DOVARIABLE
+PFA_UDR0:
+ .dw 198
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR0A:
+ .dw $ff06
+ .db "UCSR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0A
+XT_UCSR0A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0A:
+ .dw 192
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR0B:
+ .dw $ff06
+ .db "UCSR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0B
+XT_UCSR0B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0B:
+ .dw 193
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR0C:
+ .dw $ff06
+ .db "UCSR0C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0C
+XT_UCSR0C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0C:
+ .dw 194
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Bytes
+VE_UBRR0:
+ .dw $ff05
+ .db "UBRR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR0
+XT_UBRR0:
+ .dw PFA_DOVARIABLE
+PFA_UBRR0:
+ .dw 196
+
+.endif
+.if WANT_TWI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; TWI (Slave) Address Mask Register
+VE_TWAMR:
+ .dw $ff05
+ .db "TWAMR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWAMR
+XT_TWAMR:
+ .dw PFA_DOVARIABLE
+PFA_TWAMR:
+ .dw 189
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Bit Rate register
+VE_TWBR:
+ .dw $ff04
+ .db "TWBR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWBR
+XT_TWBR:
+ .dw PFA_DOVARIABLE
+PFA_TWBR:
+ .dw 184
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Control Register
+VE_TWCR:
+ .dw $ff04
+ .db "TWCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWCR
+XT_TWCR:
+ .dw PFA_DOVARIABLE
+PFA_TWCR:
+ .dw 188
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Status Register
+VE_TWSR:
+ .dw $ff04
+ .db "TWSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWSR
+XT_TWSR:
+ .dw PFA_DOVARIABLE
+PFA_TWSR:
+ .dw 185
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Data register
+VE_TWDR:
+ .dw $ff04
+ .db "TWDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWDR
+XT_TWDR:
+ .dw PFA_DOVARIABLE
+PFA_TWDR:
+ .dw 187
+; ( -- addr ) System Constant
+; R( -- )
+; TWI (Slave) Address register
+VE_TWAR:
+ .dw $ff04
+ .db "TWAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWAR
+XT_TWAR:
+ .dw PFA_DOVARIABLE
+PFA_TWAR:
+ .dw 186
+
+.endif
+.if WANT_SPI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR:
+ .dw $ff04
+ .db "SPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR
+XT_SPCR:
+ .dw PFA_DOVARIABLE
+PFA_SPCR:
+ .dw 76
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR:
+ .dw $ff04
+ .db "SPSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR
+XT_SPSR:
+ .dw PFA_DOVARIABLE
+PFA_SPSR:
+ .dw 77
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR:
+ .dw $ff04
+ .db "SPDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR
+XT_SPDR:
+ .dw PFA_DOVARIABLE
+PFA_SPDR:
+ .dw 78
+
+.endif
+.if WANT_PORTA == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Register
+VE_PORTA:
+ .dw $ff05
+ .db "PORTA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTA
+XT_PORTA:
+ .dw PFA_DOVARIABLE
+PFA_PORTA:
+ .dw 34
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Direction Register
+VE_DDRA:
+ .dw $ff04
+ .db "DDRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRA
+XT_DDRA:
+ .dw PFA_DOVARIABLE
+PFA_DDRA:
+ .dw 33
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Input Pins
+VE_PINA:
+ .dw $ff04
+ .db "PINA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINA
+XT_PINA:
+ .dw PFA_DOVARIABLE
+PFA_PINA:
+ .dw 32
+
+.endif
+.if WANT_PORTB == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw 37
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw 36
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw 35
+
+.endif
+.if WANT_PORTC == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Register
+VE_PORTC:
+ .dw $ff05
+ .db "PORTC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTC
+XT_PORTC:
+ .dw PFA_DOVARIABLE
+PFA_PORTC:
+ .dw 40
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Direction Register
+VE_DDRC:
+ .dw $ff04
+ .db "DDRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRC
+XT_DDRC:
+ .dw PFA_DOVARIABLE
+PFA_DDRC:
+ .dw 39
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Input Pins
+VE_PINC:
+ .dw $ff04
+ .db "PINC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINC
+XT_PINC:
+ .dw PFA_DOVARIABLE
+PFA_PINC:
+ .dw 38
+
+.endif
+.if WANT_PORTD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw 43
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw 42
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw 41
+
+.endif
+.if WANT_PORTE == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port E
+VE_PORTE:
+ .dw $ff05
+ .db "PORTE",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTE
+XT_PORTE:
+ .dw PFA_DOVARIABLE
+PFA_PORTE:
+ .dw 46
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port E
+VE_DDRE:
+ .dw $ff04
+ .db "DDRE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRE
+XT_DDRE:
+ .dw PFA_DOVARIABLE
+PFA_DDRE:
+ .dw 45
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port E
+VE_PINE:
+ .dw $ff04
+ .db "PINE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINE
+XT_PINE:
+ .dw PFA_DOVARIABLE
+PFA_PINE:
+ .dw 44
+
+.endif
+.if WANT_PORTF == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port F
+VE_PORTF:
+ .dw $ff05
+ .db "PORTF",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTF
+XT_PORTF:
+ .dw PFA_DOVARIABLE
+PFA_PORTF:
+ .dw 49
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port F
+VE_DDRF:
+ .dw $ff04
+ .db "DDRF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRF
+XT_DDRF:
+ .dw PFA_DOVARIABLE
+PFA_DDRF:
+ .dw 48
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port F
+VE_PINF:
+ .dw $ff04
+ .db "PINF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINF
+XT_PINF:
+ .dw PFA_DOVARIABLE
+PFA_PINF:
+ .dw 47
+
+.endif
+.if WANT_PORTG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port G
+VE_PORTG:
+ .dw $ff05
+ .db "PORTG",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTG
+XT_PORTG:
+ .dw PFA_DOVARIABLE
+PFA_PORTG:
+ .dw 52
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port G
+VE_DDRG:
+ .dw $ff04
+ .db "DDRG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRG
+XT_DDRG:
+ .dw PFA_DOVARIABLE
+PFA_DDRG:
+ .dw 51
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port G
+VE_PING:
+ .dw $ff04
+ .db "PING"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PING
+XT_PING:
+ .dw PFA_DOVARIABLE
+PFA_PING:
+ .dw 50
+
+.endif
+.if WANT_PORTH == 1
+; ( -- addr ) System Constant
+; R( -- )
+; PORT H Data Register
+VE_PORTH:
+ .dw $ff05
+ .db "PORTH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTH
+XT_PORTH:
+ .dw PFA_DOVARIABLE
+PFA_PORTH:
+ .dw 258
+; ( -- addr ) System Constant
+; R( -- )
+; PORT H Data Direction Register
+VE_DDRH:
+ .dw $ff04
+ .db "DDRH"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRH
+XT_DDRH:
+ .dw PFA_DOVARIABLE
+PFA_DDRH:
+ .dw 257
+; ( -- addr ) System Constant
+; R( -- )
+; PORT H Input Pins
+VE_PINH:
+ .dw $ff04
+ .db "PINH"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINH
+XT_PINH:
+ .dw PFA_DOVARIABLE
+PFA_PINH:
+ .dw 256
+
+.endif
+.if WANT_PORTJ == 1
+; ( -- addr ) System Constant
+; R( -- )
+; PORT J Data Register
+VE_PORTJ:
+ .dw $ff05
+ .db "PORTJ",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTJ
+XT_PORTJ:
+ .dw PFA_DOVARIABLE
+PFA_PORTJ:
+ .dw 261
+; ( -- addr ) System Constant
+; R( -- )
+; PORT J Data Direction Register
+VE_DDRJ:
+ .dw $ff04
+ .db "DDRJ"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRJ
+XT_DDRJ:
+ .dw PFA_DOVARIABLE
+PFA_DDRJ:
+ .dw 260
+; ( -- addr ) System Constant
+; R( -- )
+; PORT J Input Pins
+VE_PINJ:
+ .dw $ff04
+ .db "PINJ"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINJ
+XT_PINJ:
+ .dw PFA_DOVARIABLE
+PFA_PINJ:
+ .dw 259
+
+.endif
+.if WANT_PORTK == 1
+; ( -- addr ) System Constant
+; R( -- )
+; PORT K Data Register
+VE_PORTK:
+ .dw $ff05
+ .db "PORTK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTK
+XT_PORTK:
+ .dw PFA_DOVARIABLE
+PFA_PORTK:
+ .dw 264
+; ( -- addr ) System Constant
+; R( -- )
+; PORT K Data Direction Register
+VE_DDRK:
+ .dw $ff04
+ .db "DDRK"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRK
+XT_DDRK:
+ .dw PFA_DOVARIABLE
+PFA_DDRK:
+ .dw 263
+; ( -- addr ) System Constant
+; R( -- )
+; PORT K Input Pins
+VE_PINK:
+ .dw $ff04
+ .db "PINK"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINK
+XT_PINK:
+ .dw PFA_DOVARIABLE
+PFA_PINK:
+ .dw 262
+
+.endif
+.if WANT_PORTL == 1
+; ( -- addr ) System Constant
+; R( -- )
+; PORT L Data Register
+VE_PORTL:
+ .dw $ff05
+ .db "PORTL",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTL
+XT_PORTL:
+ .dw PFA_DOVARIABLE
+PFA_PORTL:
+ .dw 267
+; ( -- addr ) System Constant
+; R( -- )
+; PORT L Data Direction Register
+VE_DDRL:
+ .dw $ff04
+ .db "DDRL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRL
+XT_DDRL:
+ .dw PFA_DOVARIABLE
+PFA_DDRL:
+ .dw 266
+; ( -- addr ) System Constant
+; R( -- )
+; PORT L Input Pins
+VE_PINL:
+ .dw $ff04
+ .db "PINL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINL
+XT_PINL:
+ .dw PFA_DOVARIABLE
+PFA_PINL:
+ .dw 265
+
+.endif
+.if WANT_TIMER_COUNTER_0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0B:
+ .dw $ff05
+ .db "OCR0B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0B
+XT_OCR0B:
+ .dw PFA_DOVARIABLE
+PFA_OCR0B:
+ .dw 72
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0A:
+ .dw $ff05
+ .db "OCR0A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0A
+XT_OCR0A:
+ .dw PFA_DOVARIABLE
+PFA_OCR0A:
+ .dw 71
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw 70
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register B
+VE_TCCR0B:
+ .dw $ff06
+ .db "TCCR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0B
+XT_TCCR0B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0B:
+ .dw 69
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register A
+VE_TCCR0A:
+ .dw $ff06
+ .db "TCCR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0A
+XT_TCCR0A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0A:
+ .dw 68
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Mask Register
+VE_TIMSK0:
+ .dw $ff06
+ .db "TIMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK0
+XT_TIMSK0:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK0:
+ .dw 110
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Flag register
+VE_TIFR0:
+ .dw $ff05
+ .db "TIFR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR0
+XT_TIFR0:
+ .dw PFA_DOVARIABLE
+PFA_TIFR0:
+ .dw 53
+; ( -- addr ) System Constant
+; R( -- )
+; General Timer/Counter Control Register
+VE_GTCCR:
+ .dw $ff05
+ .db "GTCCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GTCCR
+XT_GTCCR:
+ .dw PFA_DOVARIABLE
+PFA_GTCCR:
+ .dw 67
+
+.endif
+.if WANT_TIMER_COUNTER_2 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Mask register
+VE_TIMSK2:
+ .dw $ff06
+ .db "TIMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK2
+XT_TIMSK2:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK2:
+ .dw 112
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Flag Register
+VE_TIFR2:
+ .dw $ff05
+ .db "TIFR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR2
+XT_TIFR2:
+ .dw PFA_DOVARIABLE
+PFA_TIFR2:
+ .dw 55
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register A
+VE_TCCR2A:
+ .dw $ff06
+ .db "TCCR2A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2A
+XT_TCCR2A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2A:
+ .dw 176
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register B
+VE_TCCR2B:
+ .dw $ff06
+ .db "TCCR2B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2B
+XT_TCCR2B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2B:
+ .dw 177
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2
+VE_TCNT2:
+ .dw $ff05
+ .db "TCNT2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT2
+XT_TCNT2:
+ .dw PFA_DOVARIABLE
+PFA_TCNT2:
+ .dw 178
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register B
+VE_OCR2B:
+ .dw $ff05
+ .db "OCR2B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2B
+XT_OCR2B:
+ .dw PFA_DOVARIABLE
+PFA_OCR2B:
+ .dw 180
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register A
+VE_OCR2A:
+ .dw $ff05
+ .db "OCR2A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2A
+XT_OCR2A:
+ .dw PFA_DOVARIABLE
+PFA_OCR2A:
+ .dw 179
+; ( -- addr ) System Constant
+; R( -- )
+; Asynchronous Status Register
+VE_ASSR:
+ .dw $ff04
+ .db "ASSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ASSR
+XT_ASSR:
+ .dw PFA_DOVARIABLE
+PFA_ASSR:
+ .dw 182
+
+.endif
+.if WANT_WATCHDOG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCSR:
+ .dw $ff06
+ .db "WDTCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCSR
+XT_WDTCSR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCSR:
+ .dw 96
+
+.endif
+.if WANT_USART1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR1:
+ .dw $ff04
+ .db "UDR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR1
+XT_UDR1:
+ .dw PFA_DOVARIABLE
+PFA_UDR1:
+ .dw 206
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR1A:
+ .dw $ff06
+ .db "UCSR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1A
+XT_UCSR1A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1A:
+ .dw 200
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR1B:
+ .dw $ff06
+ .db "UCSR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1B
+XT_UCSR1B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1B:
+ .dw 201
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR1C:
+ .dw $ff06
+ .db "UCSR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1C
+XT_UCSR1C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1C:
+ .dw 202
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Bytes
+VE_UBRR1:
+ .dw $ff05
+ .db "UBRR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR1
+XT_UBRR1:
+ .dw PFA_DOVARIABLE
+PFA_UBRR1:
+ .dw 204
+
+.endif
+.if WANT_EEPROM == 1
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Address Register Low Bytes
+VE_EEAR:
+ .dw $ff04
+ .db "EEAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEAR
+XT_EEAR:
+ .dw PFA_DOVARIABLE
+PFA_EEAR:
+ .dw 65
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw 64
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw 63
+
+.endif
+.if WANT_TIMER_COUNTER_5 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter5 Control Register A
+VE_TCCR5A:
+ .dw $ff06
+ .db "TCCR5A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR5A
+XT_TCCR5A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR5A:
+ .dw 288
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter5 Control Register B
+VE_TCCR5B:
+ .dw $ff06
+ .db "TCCR5B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR5B
+XT_TCCR5B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR5B:
+ .dw 289
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter 5 Control Register C
+VE_TCCR5C:
+ .dw $ff06
+ .db "TCCR5C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR5C
+XT_TCCR5C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR5C:
+ .dw 290
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter5 Bytes
+VE_TCNT5:
+ .dw $ff05
+ .db "TCNT5",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT5
+XT_TCNT5:
+ .dw PFA_DOVARIABLE
+PFA_TCNT5:
+ .dw 292
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter5 Output Compare Register A Bytes
+VE_OCR5A:
+ .dw $ff05
+ .db "OCR5A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR5A
+XT_OCR5A:
+ .dw PFA_DOVARIABLE
+PFA_OCR5A:
+ .dw 296
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter5 Output Compare Register B Bytes
+VE_OCR5B:
+ .dw $ff05
+ .db "OCR5B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR5B
+XT_OCR5B:
+ .dw PFA_DOVARIABLE
+PFA_OCR5B:
+ .dw 298
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter5 Output Compare Register B Bytes
+VE_OCR5C:
+ .dw $ff05
+ .db "OCR5C",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR5C
+XT_OCR5C:
+ .dw PFA_DOVARIABLE
+PFA_OCR5C:
+ .dw 300
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter5 Input Capture Register Bytes
+VE_ICR5:
+ .dw $ff04
+ .db "ICR5"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR5
+XT_ICR5:
+ .dw PFA_DOVARIABLE
+PFA_ICR5:
+ .dw 294
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter5 Interrupt Mask Register
+VE_TIMSK5:
+ .dw $ff06
+ .db "TIMSK5"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK5
+XT_TIMSK5:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK5:
+ .dw 115
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter5 Interrupt Flag register
+VE_TIFR5:
+ .dw $ff05
+ .db "TIFR5",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR5
+XT_TIFR5:
+ .dw PFA_DOVARIABLE
+PFA_TIFR5:
+ .dw 58
+
+.endif
+.if WANT_TIMER_COUNTER_4 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter4 Control Register A
+VE_TCCR4A:
+ .dw $ff06
+ .db "TCCR4A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR4A
+XT_TCCR4A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR4A:
+ .dw 160
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter4 Control Register B
+VE_TCCR4B:
+ .dw $ff06
+ .db "TCCR4B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR4B
+XT_TCCR4B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR4B:
+ .dw 161
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter 4 Control Register C
+VE_TCCR4C:
+ .dw $ff06
+ .db "TCCR4C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR4C
+XT_TCCR4C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR4C:
+ .dw 162
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter4 Bytes
+VE_TCNT4:
+ .dw $ff05
+ .db "TCNT4",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT4
+XT_TCNT4:
+ .dw PFA_DOVARIABLE
+PFA_TCNT4:
+ .dw 164
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter4 Output Compare Register A Bytes
+VE_OCR4A:
+ .dw $ff05
+ .db "OCR4A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR4A
+XT_OCR4A:
+ .dw PFA_DOVARIABLE
+PFA_OCR4A:
+ .dw 168
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter4 Output Compare Register B Bytes
+VE_OCR4B:
+ .dw $ff05
+ .db "OCR4B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR4B
+XT_OCR4B:
+ .dw PFA_DOVARIABLE
+PFA_OCR4B:
+ .dw 170
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter4 Output Compare Register B Bytes
+VE_OCR4C:
+ .dw $ff05
+ .db "OCR4C",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR4C
+XT_OCR4C:
+ .dw PFA_DOVARIABLE
+PFA_OCR4C:
+ .dw 172
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter4 Input Capture Register Bytes
+VE_ICR4:
+ .dw $ff04
+ .db "ICR4"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR4
+XT_ICR4:
+ .dw PFA_DOVARIABLE
+PFA_ICR4:
+ .dw 166
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter4 Interrupt Mask Register
+VE_TIMSK4:
+ .dw $ff06
+ .db "TIMSK4"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK4
+XT_TIMSK4:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK4:
+ .dw 114
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter4 Interrupt Flag register
+VE_TIFR4:
+ .dw $ff05
+ .db "TIFR4",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR4
+XT_TIFR4:
+ .dw PFA_DOVARIABLE
+PFA_TIFR4:
+ .dw 57
+
+.endif
+.if WANT_TIMER_COUNTER_3 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Control Register A
+VE_TCCR3A:
+ .dw $ff06
+ .db "TCCR3A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR3A
+XT_TCCR3A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR3A:
+ .dw 144
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Control Register B
+VE_TCCR3B:
+ .dw $ff06
+ .db "TCCR3B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR3B
+XT_TCCR3B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR3B:
+ .dw 145
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter 3 Control Register C
+VE_TCCR3C:
+ .dw $ff06
+ .db "TCCR3C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR3C
+XT_TCCR3C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR3C:
+ .dw 146
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Bytes
+VE_TCNT3:
+ .dw $ff05
+ .db "TCNT3",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT3
+XT_TCNT3:
+ .dw PFA_DOVARIABLE
+PFA_TCNT3:
+ .dw 148
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Output Compare Register A Bytes
+VE_OCR3A:
+ .dw $ff05
+ .db "OCR3A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR3A
+XT_OCR3A:
+ .dw PFA_DOVARIABLE
+PFA_OCR3A:
+ .dw 152
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Output Compare Register B Bytes
+VE_OCR3B:
+ .dw $ff05
+ .db "OCR3B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR3B
+XT_OCR3B:
+ .dw PFA_DOVARIABLE
+PFA_OCR3B:
+ .dw 154
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Output Compare Register B Bytes
+VE_OCR3C:
+ .dw $ff05
+ .db "OCR3C",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR3C
+XT_OCR3C:
+ .dw PFA_DOVARIABLE
+PFA_OCR3C:
+ .dw 156
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Input Capture Register Bytes
+VE_ICR3:
+ .dw $ff04
+ .db "ICR3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR3
+XT_ICR3:
+ .dw PFA_DOVARIABLE
+PFA_ICR3:
+ .dw 150
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Interrupt Mask Register
+VE_TIMSK3:
+ .dw $ff06
+ .db "TIMSK3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK3
+XT_TIMSK3:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK3:
+ .dw 113
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Interrupt Flag register
+VE_TIFR3:
+ .dw $ff05
+ .db "TIFR3",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR3
+XT_TIFR3:
+ .dw PFA_DOVARIABLE
+PFA_TIFR3:
+ .dw 56
+
+.endif
+.if WANT_TIMER_COUNTER_1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw 128
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw 129
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter 1 Control Register C
+VE_TCCR1C:
+ .dw $ff06
+ .db "TCCR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1C
+XT_TCCR1C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1C:
+ .dw 130
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Bytes
+VE_TCNT1:
+ .dw $ff05
+ .db "TCNT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1
+XT_TCNT1:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1:
+ .dw 132
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register A Bytes
+VE_OCR1A:
+ .dw $ff05
+ .db "OCR1A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1A
+XT_OCR1A:
+ .dw PFA_DOVARIABLE
+PFA_OCR1A:
+ .dw 136
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register B Bytes
+VE_OCR1B:
+ .dw $ff05
+ .db "OCR1B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1B
+XT_OCR1B:
+ .dw PFA_DOVARIABLE
+PFA_OCR1B:
+ .dw 138
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register C Bytes
+VE_OCR1C:
+ .dw $ff05
+ .db "OCR1C",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1C
+XT_OCR1C:
+ .dw PFA_DOVARIABLE
+PFA_OCR1C:
+ .dw 140
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Bytes
+VE_ICR1:
+ .dw $ff04
+ .db "ICR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1
+XT_ICR1:
+ .dw PFA_DOVARIABLE
+PFA_ICR1:
+ .dw 134
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Mask Register
+VE_TIMSK1:
+ .dw $ff06
+ .db "TIMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK1
+XT_TIMSK1:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK1:
+ .dw 111
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Flag register
+VE_TIFR1:
+ .dw $ff05
+ .db "TIFR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR1
+XT_TIFR1:
+ .dw PFA_DOVARIABLE
+PFA_TIFR1:
+ .dw 54
+
+.endif
+.if WANT_JTAG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; On-Chip Debug Related Register in I/O Memory
+VE_OCDR:
+ .dw $ff04
+ .db "OCDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCDR
+XT_OCDR:
+ .dw PFA_DOVARIABLE
+PFA_OCDR:
+ .dw 81
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw 85
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Status Register
+VE_MCUSR:
+ .dw $ff05
+ .db "MCUSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUSR
+XT_MCUSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUSR:
+ .dw 84
+
+.endif
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register A
+VE_EICRA:
+ .dw $ff05
+ .db "EICRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRA
+XT_EICRA:
+ .dw PFA_DOVARIABLE
+PFA_EICRA:
+ .dw 105
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register B
+VE_EICRB:
+ .dw $ff05
+ .db "EICRB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRB
+XT_EICRB:
+ .dw PFA_DOVARIABLE
+PFA_EICRB:
+ .dw 106
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Mask Register
+VE_EIMSK:
+ .dw $ff05
+ .db "EIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIMSK
+XT_EIMSK:
+ .dw PFA_DOVARIABLE
+PFA_EIMSK:
+ .dw 61
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Flag Register
+VE_EIFR:
+ .dw $ff04
+ .db "EIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIFR
+XT_EIFR:
+ .dw PFA_DOVARIABLE
+PFA_EIFR:
+ .dw 60
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 2
+VE_PCMSK2:
+ .dw $ff06
+ .db "PCMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK2
+XT_PCMSK2:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK2:
+ .dw 109
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 1
+VE_PCMSK1:
+ .dw $ff06
+ .db "PCMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK1
+XT_PCMSK1:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK1:
+ .dw 108
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 0
+VE_PCMSK0:
+ .dw $ff06
+ .db "PCMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK0
+XT_PCMSK0:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK0:
+ .dw 107
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Interrupt Flag Register
+VE_PCIFR:
+ .dw $ff05
+ .db "PCIFR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCIFR
+XT_PCIFR:
+ .dw PFA_DOVARIABLE
+PFA_PCIFR:
+ .dw 59
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Interrupt Control Register
+VE_PCICR:
+ .dw $ff05
+ .db "PCICR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCICR
+XT_PCICR:
+ .dw PFA_DOVARIABLE
+PFA_PCICR:
+ .dw 104
+
+.endif
+.if WANT_CPU == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw 95
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer
+VE_SP:
+ .dw $ff02
+ .db "SP"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SP
+XT_SP:
+ .dw PFA_DOVARIABLE
+PFA_SP:
+ .dw 93
+; ( -- addr ) System Constant
+; R( -- )
+; External Memory Control Register A
+VE_XMCRA:
+ .dw $ff05
+ .db "XMCRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_XMCRA
+XT_XMCRA:
+ .dw PFA_DOVARIABLE
+PFA_XMCRA:
+ .dw 116
+; ( -- addr ) System Constant
+; R( -- )
+; External Memory Control Register B
+VE_XMCRB:
+ .dw $ff05
+ .db "XMCRB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_XMCRB
+XT_XMCRB:
+ .dw PFA_DOVARIABLE
+PFA_XMCRB:
+ .dw 117
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Calibration Value
+VE_OSCCAL:
+ .dw $ff06
+ .db "OSCCAL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSCCAL
+XT_OSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_OSCCAL:
+ .dw 102
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_CLKPR:
+ .dw $ff05
+ .db "CLKPR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKPR
+XT_CLKPR:
+ .dw PFA_DOVARIABLE
+PFA_CLKPR:
+ .dw 97
+; ( -- addr ) System Constant
+; R( -- )
+; Sleep Mode Control Register
+VE_SMCR:
+ .dw $ff04
+ .db "SMCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SMCR
+XT_SMCR:
+ .dw PFA_DOVARIABLE
+PFA_SMCR:
+ .dw 83
+; ( -- addr ) System Constant
+; R( -- )
+; Extended Indirect Register
+VE_EIND:
+ .dw $ff04
+ .db "EIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIND
+XT_EIND:
+ .dw PFA_DOVARIABLE
+PFA_EIND:
+ .dw 92
+; ( -- addr ) System Constant
+; R( -- )
+; RAM Page Z Select Register
+VE_RAMPZ:
+ .dw $ff05
+ .db "RAMPZ",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_RAMPZ
+XT_RAMPZ:
+ .dw PFA_DOVARIABLE
+PFA_RAMPZ:
+ .dw 91
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 2
+VE_GPIOR2:
+ .dw $ff06
+ .db "GPIOR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR2
+XT_GPIOR2:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR2:
+ .dw 75
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 1
+VE_GPIOR1:
+ .dw $ff06
+ .db "GPIOR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR1
+XT_GPIOR1:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR1:
+ .dw 74
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 0
+VE_GPIOR0:
+ .dw $ff06
+ .db "GPIOR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR0
+XT_GPIOR0:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR0:
+ .dw 62
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register1
+VE_PRR1:
+ .dw $ff04
+ .db "PRR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR1
+XT_PRR1:
+ .dw PFA_DOVARIABLE
+PFA_PRR1:
+ .dw 101
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register0
+VE_PRR0:
+ .dw $ff04
+ .db "PRR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR0
+XT_PRR0:
+ .dw PFA_DOVARIABLE
+PFA_PRR0:
+ .dw 100
+
+.endif
+.if WANT_AD_CONVERTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC multiplexer Selection Register
+VE_ADMUX:
+ .dw $ff05
+ .db "ADMUX",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADMUX
+XT_ADMUX:
+ .dw PFA_DOVARIABLE
+PFA_ADMUX:
+ .dw 124
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register Bytes
+VE_ADC:
+ .dw $ff03
+ .db "ADC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADC
+XT_ADC:
+ .dw PFA_DOVARIABLE
+PFA_ADC:
+ .dw 120
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register A
+VE_ADCSRA:
+ .dw $ff06
+ .db "ADCSRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRA
+XT_ADCSRA:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRA:
+ .dw 122
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register
+VE_DIDR2:
+ .dw $ff05
+ .db "DIDR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR2
+XT_DIDR2:
+ .dw PFA_DOVARIABLE
+PFA_DIDR2:
+ .dw 125
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register
+VE_DIDR0:
+ .dw $ff05
+ .db "DIDR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR0
+XT_DIDR0:
+ .dw PFA_DOVARIABLE
+PFA_DIDR0:
+ .dw 126
+
+.endif
+.if WANT_BOOT_LOAD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control Register
+VE_SPMCSR:
+ .dw $ff06
+ .db "SPMCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCSR
+XT_SPMCSR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCSR:
+ .dw 87
+
+.endif
+.if WANT_USART2 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR2:
+ .dw $ff04
+ .db "UDR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR2
+XT_UDR2:
+ .dw PFA_DOVARIABLE
+PFA_UDR2:
+ .dw 214
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR2A:
+ .dw $ff06
+ .db "UCSR2A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR2A
+XT_UCSR2A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR2A:
+ .dw 208
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR2B:
+ .dw $ff06
+ .db "UCSR2B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR2B
+XT_UCSR2B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR2B:
+ .dw 209
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR2C:
+ .dw $ff06
+ .db "UCSR2C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR2C
+XT_UCSR2C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR2C:
+ .dw 210
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Bytes
+VE_UBRR2:
+ .dw $ff05
+ .db "UBRR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR2
+XT_UBRR2:
+ .dw PFA_DOVARIABLE
+PFA_UBRR2:
+ .dw 212
+
+.endif
+.if WANT_USART3 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR3:
+ .dw $ff04
+ .db "UDR3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR3
+XT_UDR3:
+ .dw PFA_DOVARIABLE
+PFA_UDR3:
+ .dw 310
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR3A:
+ .dw $ff06
+ .db "UCSR3A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR3A
+XT_UCSR3A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR3A:
+ .dw 304
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR3B:
+ .dw $ff06
+ .db "UCSR3B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR3B
+XT_UCSR3B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR3B:
+ .dw 305
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR3C:
+ .dw $ff06
+ .db "UCSR3C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR3C
+XT_UCSR3C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR3C:
+ .dw 306
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Bytes
+VE_UBRR3:
+ .dw $ff05
+ .db "UBRR3",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR3
+XT_UBRR3:
+ .dw PFA_DOVARIABLE
+PFA_UBRR3:
+ .dw 308
+
+.endif
diff --git a/amforth-6.5/avr8/devices/atmega2560/device.py b/amforth-6.5/avr8/devices/atmega2560/device.py
new file mode 100644
index 0000000..fd51a56
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega2560/device.py
@@ -0,0 +1,633 @@
+# Generated Automatically
+
+# Partname ATmega2560
+
+MCUREGS = {
+# Interrupt Vectors
+ 'INT0Addr' : '#2', # External Interrupt Request 0
+ 'INT1Addr' : '#4', # External Interrupt Request 1
+ 'INT2Addr' : '#6', # External Interrupt Request 2
+ 'INT3Addr' : '#8', # External Interrupt Request 3
+ 'INT4Addr' : '#10', # External Interrupt Request 4
+ 'INT5Addr' : '#12', # External Interrupt Request 5
+ 'INT6Addr' : '#14', # External Interrupt Request 6
+ 'INT7Addr' : '#16', # External Interrupt Request 7
+ 'PCINT0Addr' : '#18', # Pin Change Interrupt Request 0
+ 'PCINT1Addr' : '#20', # Pin Change Interrupt Request 1
+ 'PCINT2Addr' : '#22', # Pin Change Interrupt Request 2
+ 'WDTAddr' : '#24', # Watchdog Time-out Interrupt
+ 'TIMER2_COMPAAddr' : '#26', # Timer/Counter2 Compare Match A
+ 'TIMER2_COMPBAddr' : '#28', # Timer/Counter2 Compare Match B
+ 'TIMER2_OVFAddr' : '#30', # Timer/Counter2 Overflow
+ 'TIMER1_CAPTAddr' : '#32', # Timer/Counter1 Capture Event
+ 'TIMER1_COMPAAddr' : '#34', # Timer/Counter1 Compare Match A
+ 'TIMER1_COMPBAddr' : '#36', # Timer/Counter1 Compare Match B
+ 'TIMER1_COMPCAddr' : '#38', # Timer/Counter1 Compare Match C
+ 'TIMER1_OVFAddr' : '#40', # Timer/Counter1 Overflow
+ 'TIMER0_COMPAAddr' : '#42', # Timer/Counter0 Compare Match A
+ 'TIMER0_COMPBAddr' : '#44', # Timer/Counter0 Compare Match B
+ 'TIMER0_OVFAddr' : '#46', # Timer/Counter0 Overflow
+ 'SPI_STCAddr' : '#48', # SPI Serial Transfer Complete
+ 'USART0_RXAddr' : '#50', # USART0, Rx Complete
+ 'USART0_UDREAddr' : '#52', # USART0 Data register Empty
+ 'USART0_TXAddr' : '#54', # USART0, Tx Complete
+ 'ANALOG_COMPAddr' : '#56', # Analog Comparator
+ 'ADCAddr' : '#58', # ADC Conversion Complete
+ 'EE_READYAddr' : '#60', # EEPROM Ready
+ 'TIMER3_CAPTAddr' : '#62', # Timer/Counter3 Capture Event
+ 'TIMER3_COMPAAddr' : '#64', # Timer/Counter3 Compare Match A
+ 'TIMER3_COMPBAddr' : '#66', # Timer/Counter3 Compare Match B
+ 'TIMER3_COMPCAddr' : '#68', # Timer/Counter3 Compare Match C
+ 'TIMER3_OVFAddr' : '#70', # Timer/Counter3 Overflow
+ 'USART1_RXAddr' : '#72', # USART1, Rx Complete
+ 'USART1_UDREAddr' : '#74', # USART1 Data register Empty
+ 'USART1_TXAddr' : '#76', # USART1, Tx Complete
+ 'TWIAddr' : '#78', # 2-wire Serial Interface
+ 'SPM_READYAddr' : '#80', # Store Program Memory Read
+ 'TIMER4_CAPTAddr' : '#82', # Timer/Counter4 Capture Event
+ 'TIMER4_COMPAAddr' : '#84', # Timer/Counter4 Compare Match A
+ 'TIMER4_COMPBAddr' : '#86', # Timer/Counter4 Compare Match B
+ 'TIMER4_COMPCAddr' : '#88', # Timer/Counter4 Compare Match C
+ 'TIMER4_OVFAddr' : '#90', # Timer/Counter4 Overflow
+ 'TIMER5_CAPTAddr' : '#92', # Timer/Counter5 Capture Event
+ 'TIMER5_COMPAAddr' : '#94', # Timer/Counter5 Compare Match A
+ 'TIMER5_COMPBAddr' : '#96', # Timer/Counter5 Compare Match B
+ 'TIMER5_COMPCAddr' : '#98', # Timer/Counter5 Compare Match C
+ 'TIMER5_OVFAddr' : '#100', # Timer/Counter5 Overflow
+ 'USART2_RXAddr' : '#102', # USART2, Rx Complete
+ 'USART2_UDREAddr' : '#104', # USART2 Data register Empty
+ 'USART2_TXAddr' : '#106', # USART2, Tx Complete
+ 'USART3_RXAddr' : '#108', # USART3, Rx Complete
+ 'USART3_UDREAddr' : '#110', # USART3 Data register Empty
+ 'USART3_TXAddr' : '#112', # USART3, Tx Complete
+
+# Module ANALOG_COMPARATOR
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
+ 'ACSR' : '$50', # Analog Comparator Control And
+ 'ACSR_ACD': '$80', # Analog Comparator Disable
+ 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
+ 'ACSR_ACO': '$20', # Analog Compare Output
+ 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
+ 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
+ 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
+ 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
+ 'DIDR1' : '$7f', # Digital Input Disable Register
+ 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
+ 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
+
+# Module USART0
+ 'UDR0' : '$c6', # USART I/O Data Register
+ 'UCSR0A' : '$c0', # USART Control and Status Regis
+ 'UCSR0A_RXC0': '$80', # USART Receive Complete
+ 'UCSR0A_TXC0': '$40', # USART Transmitt Complete
+ 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
+ 'UCSR0A_FE0': '$10', # Framing Error
+ 'UCSR0A_DOR0': '$8', # Data overRun
+ 'UCSR0A_UPE0': '$4', # Parity Error
+ 'UCSR0A_U2X0': '$2', # Double the USART transmission
+ 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
+ 'UCSR0B' : '$c1', # USART Control and Status Regis
+ 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
+ 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
+ 'UCSR0B_UDRIE0': '$20', # USART Data register Empty Inte
+ 'UCSR0B_RXEN0': '$10', # Receiver Enable
+ 'UCSR0B_TXEN0': '$8', # Transmitter Enable
+ 'UCSR0B_UCSZ02': '$4', # Character Size
+ 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
+ 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
+ 'UCSR0C' : '$c2', # USART Control and Status Regis
+ 'UCSR0C_UMSEL0': '$c0', # USART Mode Select
+ 'UCSR0C_UPM0': '$30', # Parity Mode Bits
+ 'UCSR0C_USBS0': '$8', # Stop Bit Select
+ 'UCSR0C_UCSZ0': '$6', # Character Size
+ 'UCSR0C_UCPOL0': '$1', # Clock Polarity
+ 'UBRR0' : '$c4', # USART Baud Rate Register Byte
+
+# Module TWI
+ 'TWAMR' : '$bd', # TWI (Slave) Address Mask Regis
+ 'TWAMR_TWAM': '$fe', #
+ 'TWBR' : '$b8', # TWI Bit Rate register
+ 'TWCR' : '$bc', # TWI Control Register
+ 'TWCR_TWINT': '$80', # TWI Interrupt Flag
+ 'TWCR_TWEA': '$40', # TWI Enable Acknowledge Bit
+ 'TWCR_TWSTA': '$20', # TWI Start Condition Bit
+ 'TWCR_TWSTO': '$10', # TWI Stop Condition Bit
+ 'TWCR_TWWC': '$8', # TWI Write Collition Flag
+ 'TWCR_TWEN': '$4', # TWI Enable Bit
+ 'TWCR_TWIE': '$1', # TWI Interrupt Enable
+ 'TWSR' : '$b9', # TWI Status Register
+ 'TWSR_TWS': '$f8', # TWI Status
+ 'TWSR_TWPS': '$3', # TWI Prescaler
+ 'TWDR' : '$bb', # TWI Data register
+ 'TWAR' : '$ba', # TWI (Slave) Address register
+ 'TWAR_TWA': '$fe', # TWI (Slave) Address register B
+ 'TWAR_TWGCE': '$1', # TWI General Call Recognition E
+
+# Module SPI
+ 'SPCR' : '$4c', # SPI Control Register
+ 'SPCR_SPIE': '$80', # SPI Interrupt Enable
+ 'SPCR_SPE': '$40', # SPI Enable
+ 'SPCR_DORD': '$20', # Data Order
+ 'SPCR_MSTR': '$10', # Master/Slave Select
+ 'SPCR_CPOL': '$8', # Clock polarity
+ 'SPCR_CPHA': '$4', # Clock Phase
+ 'SPCR_SPR': '$3', # SPI Clock Rate Selects
+ 'SPSR' : '$4d', # SPI Status Register
+ 'SPSR_SPIF': '$80', # SPI Interrupt Flag
+ 'SPSR_WCOL': '$40', # Write Collision Flag
+ 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
+ 'SPDR' : '$4e', # SPI Data Register
+
+# Module PORTA
+ 'PORTA' : '$22', # Port A Data Register
+ 'DDRA' : '$21', # Port A Data Direction Register
+ 'PINA' : '$20', # Port A Input Pins
+
+# Module PORTB
+ 'PORTB' : '$25', # Port B Data Register
+ 'DDRB' : '$24', # Port B Data Direction Register
+ 'PINB' : '$23', # Port B Input Pins
+
+# Module PORTC
+ 'PORTC' : '$28', # Port C Data Register
+ 'DDRC' : '$27', # Port C Data Direction Register
+ 'PINC' : '$26', # Port C Input Pins
+
+# Module PORTD
+ 'PORTD' : '$2b', # Port D Data Register
+ 'DDRD' : '$2a', # Port D Data Direction Register
+ 'PIND' : '$29', # Port D Input Pins
+
+# Module PORTE
+ 'PORTE' : '$2e', # Data Register, Port E
+ 'DDRE' : '$2d', # Data Direction Register, Port
+ 'PINE' : '$2c', # Input Pins, Port E
+
+# Module PORTF
+ 'PORTF' : '$31', # Data Register, Port F
+ 'DDRF' : '$30', # Data Direction Register, Port
+ 'PINF' : '$2f', # Input Pins, Port F
+
+# Module PORTG
+ 'PORTG' : '$34', # Data Register, Port G
+ 'DDRG' : '$33', # Data Direction Register, Port
+ 'PING' : '$32', # Input Pins, Port G
+
+# Module PORTH
+ 'PORTH' : '$102', # PORT H Data Register
+ 'DDRH' : '$101', # PORT H Data Direction Register
+ 'PINH' : '$100', # PORT H Input Pins
+
+# Module PORTJ
+ 'PORTJ' : '$105', # PORT J Data Register
+ 'DDRJ' : '$104', # PORT J Data Direction Register
+ 'PINJ' : '$103', # PORT J Input Pins
+
+# Module PORTK
+ 'PORTK' : '$108', # PORT K Data Register
+ 'DDRK' : '$107', # PORT K Data Direction Register
+ 'PINK' : '$106', # PORT K Input Pins
+
+# Module PORTL
+ 'PORTL' : '$10b', # PORT L Data Register
+ 'DDRL' : '$10a', # PORT L Data Direction Register
+ 'PINL' : '$109', # PORT L Input Pins
+
+# Module TIMER_COUNTER_0
+ 'OCR0B' : '$48', # Timer/Counter0 Output Compare
+ 'OCR0A' : '$47', # Timer/Counter0 Output Compare
+ 'TCNT0' : '$46', # Timer/Counter0
+ 'TCCR0B' : '$45', # Timer/Counter Control Register
+ 'TCCR0B_FOC0A': '$80', # Force Output Compare A
+ 'TCCR0B_FOC0B': '$40', # Force Output Compare B
+ 'TCCR0B_WGM02': '$8', #
+ 'TCCR0B_CS0': '$7', # Clock Select
+ 'TCCR0A' : '$44', # Timer/Counter Control Registe
+ 'TCCR0A_COM0A': '$c0', # Compare Output Mode, Phase Cor
+ 'TCCR0A_COM0B': '$30', # Compare Output Mode, Fast PWm
+ 'TCCR0A_WGM0': '$3', # Waveform Generation Mode
+ 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
+ 'TIMSK0_OCIE0B': '$4', # Timer/Counter0 Output Compare
+ 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
+ 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
+ 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
+ 'TIFR0_OCF0B': '$4', # Timer/Counter0 Output Compare
+ 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
+ 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSRSYNC': '$1', # Prescaler Reset Timer/Counter1
+
+# Module TIMER_COUNTER_2
+ 'TIMSK2' : '$70', # Timer/Counter Interrupt Mask r
+ 'TIMSK2_OCIE2B': '$4', # Timer/Counter2 Output Compare
+ 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
+ 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
+ 'TIFR2' : '$37', # Timer/Counter Interrupt Flag R
+ 'TIFR2_OCF2B': '$4', # Output Compare Flag 2B
+ 'TIFR2_OCF2A': '$2', # Output Compare Flag 2A
+ 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
+ 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
+ 'TCCR2A_COM2A': '$c0', # Compare Output Mode bits
+ 'TCCR2A_COM2B': '$30', # Compare Output Mode bits
+ 'TCCR2A_WGM2': '$3', # Waveform Genration Mode
+ 'TCCR2B' : '$b1', # Timer/Counter2 Control Registe
+ 'TCCR2B_FOC2A': '$80', # Force Output Compare A
+ 'TCCR2B_FOC2B': '$40', # Force Output Compare B
+ 'TCCR2B_WGM22': '$8', # Waveform Generation Mode
+ 'TCCR2B_CS2': '$7', # Clock Select bits
+ 'TCNT2' : '$b2', # Timer/Counter2
+ 'OCR2B' : '$b4', # Timer/Counter2 Output Compare
+ 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
+ 'ASSR' : '$b6', # Asynchronous Status Register
+ 'ASSR_EXCLK': '$40', # Enable External Clock Input
+ 'ASSR_AS2': '$20', # Asynchronous Timer/Counter2
+ 'ASSR_TCN2UB': '$10', # Timer/Counter2 Update Busy
+ 'ASSR_OCR2AUB': '$8', # Output Compare Register2 Updat
+ 'ASSR_OCR2BUB': '$4', # Output Compare Register 2 Upda
+ 'ASSR_TCR2AUB': '$2', # Timer/Counter Control Register
+ 'ASSR_TCR2BUB': '$1', # Timer/Counter Control Register
+ 'GTCCR' : '$43', # General Timer Counter Control
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSRASY': '$2', # Prescaler Reset Timer/Counter2
+
+# Module WATCHDOG
+ 'WDTCSR' : '$60', # Watchdog Timer Control Registe
+ 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
+ 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
+ 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
+ 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
+ 'WDTCSR_WDE': '$8', # Watch Dog Enable
+
+# Module USART1
+ 'UDR1' : '$ce', # USART I/O Data Register
+ 'UCSR1A' : '$c8', # USART Control and Status Regis
+ 'UCSR1A_RXC1': '$80', # USART Receive Complete
+ 'UCSR1A_TXC1': '$40', # USART Transmitt Complete
+ 'UCSR1A_UDRE1': '$20', # USART Data Register Empty
+ 'UCSR1A_FE1': '$10', # Framing Error
+ 'UCSR1A_DOR1': '$8', # Data overRun
+ 'UCSR1A_UPE1': '$4', # Parity Error
+ 'UCSR1A_U2X1': '$2', # Double the USART transmission
+ 'UCSR1A_MPCM1': '$1', # Multi-processor Communication
+ 'UCSR1B' : '$c9', # USART Control and Status Regis
+ 'UCSR1B_RXCIE1': '$80', # RX Complete Interrupt Enable
+ 'UCSR1B_TXCIE1': '$40', # TX Complete Interrupt Enable
+ 'UCSR1B_UDRIE1': '$20', # USART Data register Empty Inte
+ 'UCSR1B_RXEN1': '$10', # Receiver Enable
+ 'UCSR1B_TXEN1': '$8', # Transmitter Enable
+ 'UCSR1B_UCSZ12': '$4', # Character Size
+ 'UCSR1B_RXB81': '$2', # Receive Data Bit 8
+ 'UCSR1B_TXB81': '$1', # Transmit Data Bit 8
+ 'UCSR1C' : '$ca', # USART Control and Status Regis
+ 'UCSR1C_UMSEL1': '$c0', # USART Mode Select
+ 'UCSR1C_UPM1': '$30', # Parity Mode Bits
+ 'UCSR1C_USBS1': '$8', # Stop Bit Select
+ 'UCSR1C_UCSZ1': '$6', # Character Size
+ 'UCSR1C_UCPOL1': '$1', # Clock Polarity
+ 'UBRR1' : '$cc', # USART Baud Rate Register Byte
+
+# Module EEPROM
+ 'EEAR' : '$41', # EEPROM Address Register Low By
+ 'EEDR' : '$40', # EEPROM Data Register
+ 'EECR' : '$3f', # EEPROM Control Register
+ 'EECR_EEPM': '$30', # EEPROM Programming Mode Bits
+ 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
+ 'EECR_EEMPE': '$4', # EEPROM Master Write Enable
+ 'EECR_EEPE': '$2', # EEPROM Write Enable
+ 'EECR_EERE': '$1', # EEPROM Read Enable
+
+# Module TIMER_COUNTER_5
+ 'TCCR5A' : '$120', # Timer/Counter5 Control Registe
+ 'TCCR5A_COM5A': '$c0', # Compare Output Mode 1A, bits
+ 'TCCR5A_COM5B': '$30', # Compare Output Mode 5B, bits
+ 'TCCR5A_COM5C': '$c', # Compare Output Mode 5C, bits
+ 'TCCR5A_WGM5': '$3', # Waveform Generation Mode
+ 'TCCR5B' : '$121', # Timer/Counter5 Control Registe
+ 'TCCR5B_ICNC5': '$80', # Input Capture 5 Noise Canceler
+ 'TCCR5B_ICES5': '$40', # Input Capture 5 Edge Select
+ 'TCCR5B_WGM5': '$18', # Waveform Generation Mode
+ 'TCCR5B_CS5': '$7', # Prescaler source of Timer/Coun
+ 'TCCR5C' : '$122', # Timer/Counter 5 Control Regist
+ 'TCCR5C_FOC5A': '$80', # Force Output Compare 5A
+ 'TCCR5C_FOC5B': '$40', # Force Output Compare 5B
+ 'TCCR5C_FOC5C': '$20', # Force Output Compare 5C
+ 'TCNT5' : '$124', # Timer/Counter5 Bytes
+ 'OCR5A' : '$128', # Timer/Counter5 Output Compare
+ 'OCR5B' : '$12a', # Timer/Counter5 Output Compare
+ 'OCR5C' : '$12c', # Timer/Counter5 Output Compare
+ 'ICR5' : '$126', # Timer/Counter5 Input Capture R
+ 'TIMSK5' : '$73', # Timer/Counter5 Interrupt Mask
+ 'TIMSK5_ICIE5': '$20', # Timer/Counter5 Input Capture I
+ 'TIMSK5_OCIE5C': '$8', # Timer/Counter5 Output Compare
+ 'TIMSK5_OCIE5B': '$4', # Timer/Counter5 Output Compare
+ 'TIMSK5_OCIE5A': '$2', # Timer/Counter5 Output Compare
+ 'TIMSK5_TOIE5': '$1', # Timer/Counter5 Overflow Interr
+ 'TIFR5' : '$3a', # Timer/Counter5 Interrupt Flag
+ 'TIFR5_ICF5': '$20', # Input Capture Flag 5
+ 'TIFR5_OCF5C': '$8', # Output Compare Flag 5C
+ 'TIFR5_OCF5B': '$4', # Output Compare Flag 5B
+ 'TIFR5_OCF5A': '$2', # Output Compare Flag 5A
+ 'TIFR5_TOV5': '$1', # Timer/Counter5 Overflow Flag
+
+# Module TIMER_COUNTER_4
+ 'TCCR4A' : '$a0', # Timer/Counter4 Control Registe
+ 'TCCR4A_COM4A': '$c0', # Compare Output Mode 1A, bits
+ 'TCCR4A_COM4B': '$30', # Compare Output Mode 4B, bits
+ 'TCCR4A_COM4C': '$c', # Compare Output Mode 4C, bits
+ 'TCCR4A_WGM4': '$3', # Waveform Generation Mode
+ 'TCCR4B' : '$a1', # Timer/Counter4 Control Registe
+ 'TCCR4B_ICNC4': '$80', # Input Capture 4 Noise Canceler
+ 'TCCR4B_ICES4': '$40', # Input Capture 4 Edge Select
+ 'TCCR4B_WGM4': '$18', # Waveform Generation Mode
+ 'TCCR4B_CS4': '$7', # Prescaler source of Timer/Coun
+ 'TCCR4C' : '$a2', # Timer/Counter 4 Control Regist
+ 'TCCR4C_FOC4A': '$80', # Force Output Compare 4A
+ 'TCCR4C_FOC4B': '$40', # Force Output Compare 4B
+ 'TCCR4C_FOC4C': '$20', # Force Output Compare 4C
+ 'TCNT4' : '$a4', # Timer/Counter4 Bytes
+ 'OCR4A' : '$a8', # Timer/Counter4 Output Compare
+ 'OCR4B' : '$aa', # Timer/Counter4 Output Compare
+ 'OCR4C' : '$ac', # Timer/Counter4 Output Compare
+ 'ICR4' : '$a6', # Timer/Counter4 Input Capture R
+ 'TIMSK4' : '$72', # Timer/Counter4 Interrupt Mask
+ 'TIMSK4_ICIE4': '$20', # Timer/Counter4 Input Capture I
+ 'TIMSK4_OCIE4C': '$8', # Timer/Counter4 Output Compare
+ 'TIMSK4_OCIE4B': '$4', # Timer/Counter4 Output Compare
+ 'TIMSK4_OCIE4A': '$2', # Timer/Counter4 Output Compare
+ 'TIMSK4_TOIE4': '$1', # Timer/Counter4 Overflow Interr
+ 'TIFR4' : '$39', # Timer/Counter4 Interrupt Flag
+ 'TIFR4_ICF4': '$20', # Input Capture Flag 4
+ 'TIFR4_OCF4C': '$8', # Output Compare Flag 4C
+ 'TIFR4_OCF4B': '$4', # Output Compare Flag 4B
+ 'TIFR4_OCF4A': '$2', # Output Compare Flag 4A
+ 'TIFR4_TOV4': '$1', # Timer/Counter4 Overflow Flag
+
+# Module TIMER_COUNTER_3
+ 'TCCR3A' : '$90', # Timer/Counter3 Control Registe
+ 'TCCR3A_COM3A': '$c0', # Compare Output Mode 1A, bits
+ 'TCCR3A_COM3B': '$30', # Compare Output Mode 3B, bits
+ 'TCCR3A_COM3C': '$c', # Compare Output Mode 3C, bits
+ 'TCCR3A_WGM3': '$3', # Waveform Generation Mode
+ 'TCCR3B' : '$91', # Timer/Counter3 Control Registe
+ 'TCCR3B_ICNC3': '$80', # Input Capture 3 Noise Canceler
+ 'TCCR3B_ICES3': '$40', # Input Capture 3 Edge Select
+ 'TCCR3B_WGM3': '$18', # Waveform Generation Mode
+ 'TCCR3B_CS3': '$7', # Prescaler source of Timer/Coun
+ 'TCCR3C' : '$92', # Timer/Counter 3 Control Regist
+ 'TCCR3C_FOC3A': '$80', # Force Output Compare 3A
+ 'TCCR3C_FOC3B': '$40', # Force Output Compare 3B
+ 'TCCR3C_FOC3C': '$20', # Force Output Compare 3C
+ 'TCNT3' : '$94', # Timer/Counter3 Bytes
+ 'OCR3A' : '$98', # Timer/Counter3 Output Compare
+ 'OCR3B' : '$9a', # Timer/Counter3 Output Compare
+ 'OCR3C' : '$9c', # Timer/Counter3 Output Compare
+ 'ICR3' : '$96', # Timer/Counter3 Input Capture R
+ 'TIMSK3' : '$71', # Timer/Counter3 Interrupt Mask
+ 'TIMSK3_ICIE3': '$20', # Timer/Counter3 Input Capture I
+ 'TIMSK3_OCIE3C': '$8', # Timer/Counter3 Output Compare
+ 'TIMSK3_OCIE3B': '$4', # Timer/Counter3 Output Compare
+ 'TIMSK3_OCIE3A': '$2', # Timer/Counter3 Output Compare
+ 'TIMSK3_TOIE3': '$1', # Timer/Counter3 Overflow Interr
+ 'TIFR3' : '$38', # Timer/Counter3 Interrupt Flag
+ 'TIFR3_ICF3': '$20', # Input Capture Flag 3
+ 'TIFR3_OCF3C': '$8', # Output Compare Flag 3C
+ 'TIFR3_OCF3B': '$4', # Output Compare Flag 3B
+ 'TIFR3_OCF3A': '$2', # Output Compare Flag 3A
+ 'TIFR3_TOV3': '$1', # Timer/Counter3 Overflow Flag
+
+# Module TIMER_COUNTER_1
+ 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
+ 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
+ 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
+ 'TCCR1A_COM1C': '$c', # Compare Output Mode 1C, bits
+ 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
+ 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
+ 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
+ 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
+ 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
+ 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
+ 'TCCR1C' : '$82', # Timer/Counter 1 Control Regist
+ 'TCCR1C_FOC1A': '$80', # Force Output Compare 1A
+ 'TCCR1C_FOC1B': '$40', # Force Output Compare 1B
+ 'TCCR1C_FOC1C': '$20', # Force Output Compare 1C
+ 'TCNT1' : '$84', # Timer/Counter1 Bytes
+ 'OCR1A' : '$88', # Timer/Counter1 Output Compare
+ 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
+ 'OCR1C' : '$8c', # Timer/Counter1 Output Compare
+ 'ICR1' : '$86', # Timer/Counter1 Input Capture R
+ 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
+ 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
+ 'TIMSK1_OCIE1C': '$8', # Timer/Counter1 Output Compare
+ 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
+ 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
+ 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
+ 'TIFR1' : '$36', # Timer/Counter1 Interrupt Flag
+ 'TIFR1_ICF1': '$20', # Input Capture Flag 1
+ 'TIFR1_OCF1C': '$8', # Output Compare Flag 1C
+ 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
+ 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
+ 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
+
+# Module JTAG
+ 'OCDR' : '$51', # On-Chip Debug Related Register
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_JTD': '$80', # JTAG Interface Disable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+
+# Module EXTERNAL_INTERRUPT
+ 'EICRA' : '$69', # External Interrupt Control Reg
+ 'EICRA_ISC3': '$c0', # External Interrupt Sense Contr
+ 'EICRA_ISC2': '$30', # External Interrupt Sense Contr
+ 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
+ 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
+ 'EICRB' : '$6a', # External Interrupt Control Reg
+ 'EICRB_ISC7': '$c0', # External Interrupt 7-4 Sense C
+ 'EICRB_ISC6': '$30', # External Interrupt 7-4 Sense C
+ 'EICRB_ISC5': '$c', # External Interrupt 7-4 Sense C
+ 'EICRB_ISC4': '$3', # External Interrupt 7-4 Sense C
+ 'EIMSK' : '$3d', # External Interrupt Mask Regist
+ 'EIMSK_INT': '$ff', # External Interrupt Request 7 E
+ 'EIFR' : '$3c', # External Interrupt Flag Regist
+ 'EIFR_INTF': '$ff', # External Interrupt Flags
+ 'PCMSK2' : '$6d', # Pin Change Mask Register 2
+ 'PCMSK1' : '$6c', # Pin Change Mask Register 1
+ 'PCMSK0' : '$6b', # Pin Change Mask Register 0
+ 'PCIFR' : '$3b', # Pin Change Interrupt Flag Regi
+ 'PCIFR_PCIF': '$7', # Pin Change Interrupt Flags
+ 'PCICR' : '$68', # Pin Change Interrupt Control R
+ 'PCICR_PCIE': '$7', # Pin Change Interrupt Enables
+
+# Module CPU
+ 'SREG' : '$5f', # Status Register
+ 'SREG_I': '$80', # Global Interrupt Enable
+ 'SREG_T': '$40', # Bit Copy Storage
+ 'SREG_H': '$20', # Half Carry Flag
+ 'SREG_S': '$10', # Sign Bit
+ 'SREG_V': '$8', # Two's Complement Overflow Flag
+ 'SREG_N': '$4', # Negative Flag
+ 'SREG_Z': '$2', # Zero Flag
+ 'SREG_C': '$1', # Carry Flag
+ 'SP' : '$5d', # Stack Pointer
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_JTD': '$80', # JTAG Interface Disable
+ 'MCUCR_PUD': '$10', # Pull-up disable
+ 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
+ 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+ 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
+ 'MCUSR_BORF': '$4', # Brown-out Reset Flag
+ 'MCUSR_EXTRF': '$2', # External Reset Flag
+ 'MCUSR_PORF': '$1', # Power-on reset flag
+ 'XMCRA' : '$74', # External Memory Control Regist
+ 'XMCRA_SRE': '$80', # External SRAM Enable
+ 'XMCRA_SRL': '$70', # Wait state page limit
+ 'XMCRA_SRW1': '$c', # Wait state select bit upper pa
+ 'XMCRA_SRW0': '$3', # Wait state select bit lower pa
+ 'XMCRB' : '$75', # External Memory Control Regist
+ 'XMCRB_XMBK': '$80', # External Memory Bus Keeper Ena
+ 'XMCRB_XMM': '$7', # External Memory High Mask
+ 'OSCCAL' : '$66', # Oscillator Calibration Value
+ 'CLKPR' : '$61', #
+ 'CLKPR_CLKPCE': '$80', #
+ 'CLKPR_CLKPS': '$f', #
+ 'SMCR' : '$53', # Sleep Mode Control Register
+ 'SMCR_SM': '$e', # Sleep Mode Select bits
+ 'SMCR_SE': '$1', # Sleep Enable
+ 'EIND' : '$5c', # Extended Indirect Register
+ 'RAMPZ' : '$5b', # RAM Page Z Select Register
+ 'GPIOR2' : '$4b', # General Purpose IO Register 2
+ 'GPIOR2_GPIOR': '$ff', # General Purpose IO Register 2
+ 'GPIOR1' : '$4a', # General Purpose IO Register 1
+ 'GPIOR1_GPIOR': '$ff', # General Purpose IO Register 1
+ 'GPIOR0' : '$3e', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR07': '$80', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR06': '$40', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR05': '$20', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR04': '$10', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR03': '$8', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR02': '$4', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR01': '$2', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR00': '$1', # General Purpose IO Register 0
+ 'PRR1' : '$65', # Power Reduction Register1
+ 'PRR1_PRTIM5': '$20', # Power Reduction Timer/Counter5
+ 'PRR1_PRTIM4': '$10', # Power Reduction Timer/Counter4
+ 'PRR1_PRTIM3': '$8', # Power Reduction Timer/Counter3
+ 'PRR1_PRUSART': '$7', # Power Reduction USART3
+ 'PRR0' : '$64', # Power Reduction Register0
+ 'PRR0_PRTWI': '$80', # Power Reduction TWI
+ 'PRR0_PRTIM2': '$40', # Power Reduction Timer/Counter2
+ 'PRR0_PRTIM0': '$20', # Power Reduction Timer/Counter0
+ 'PRR0_PRTIM1': '$8', # Power Reduction Timer/Counter1
+ 'PRR0_PRSPI': '$4', # Power Reduction Serial Periphe
+ 'PRR0_PRUSART0': '$2', # Power Reduction USART
+ 'PRR0_PRADC': '$1', # Power Reduction ADC
+
+# Module AD_CONVERTER
+ 'ADMUX' : '$7c', # The ADC multiplexer Selection
+ 'ADMUX_REFS': '$c0', # Reference Selection Bits
+ 'ADMUX_ADLAR': '$20', # Left Adjust Result
+ 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
+ 'ADC' : '$78', # ADC Data Register Bytes
+ 'ADCSRA' : '$7a', # The ADC Control and Status reg
+ 'ADCSRA_ADEN': '$80', # ADC Enable
+ 'ADCSRA_ADSC': '$40', # ADC Start Conversion
+ 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
+ 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
+ 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
+ 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
+ 'ADCSRB' : '$7b', # The ADC Control and Status reg
+ 'ADCSRB_ACME': '$40', #
+ 'ADCSRB_MUX5': '$8', # Analog Channel and Gain Select
+ 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Source bits
+ 'DIDR2' : '$7d', # Digital Input Disable Register
+ 'DIDR2_ADC15D': '$80', #
+ 'DIDR2_ADC14D': '$40', #
+ 'DIDR2_ADC13D': '$20', #
+ 'DIDR2_ADC12D': '$10', #
+ 'DIDR2_ADC11D': '$8', #
+ 'DIDR2_ADC10D': '$4', #
+ 'DIDR2_ADC9D': '$2', #
+ 'DIDR2_ADC8D': '$1', #
+ 'DIDR0' : '$7e', # Digital Input Disable Register
+ 'DIDR0_ADC7D': '$80', #
+ 'DIDR0_ADC6D': '$40', #
+ 'DIDR0_ADC5D': '$20', #
+ 'DIDR0_ADC4D': '$10', #
+ 'DIDR0_ADC3D': '$8', #
+ 'DIDR0_ADC2D': '$4', #
+ 'DIDR0_ADC1D': '$2', #
+ 'DIDR0_ADC0D': '$1', #
+
+# Module BOOT_LOAD
+ 'SPMCSR' : '$57', # Store Program Memory Control R
+ 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
+ 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
+ 'SPMCSR_SIGRD': '$20', # Signature Row Read
+ 'SPMCSR_RWWSRE': '$10', # Read While Write section read
+ 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
+ 'SPMCSR_PGWRT': '$4', # Page Write
+ 'SPMCSR_PGERS': '$2', # Page Erase
+ 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
+
+# Module USART2
+ 'UDR2' : '$d6', # USART I/O Data Register
+ 'UCSR2A' : '$d0', # USART Control and Status Regis
+ 'UCSR2A_RXC2': '$80', # USART Receive Complete
+ 'UCSR2A_TXC2': '$40', # USART Transmitt Complete
+ 'UCSR2A_UDRE2': '$20', # USART Data Register Empty
+ 'UCSR2A_FE2': '$10', # Framing Error
+ 'UCSR2A_DOR2': '$8', # Data overRun
+ 'UCSR2A_UPE2': '$4', # Parity Error
+ 'UCSR2A_U2X2': '$2', # Double the USART transmission
+ 'UCSR2A_MPCM2': '$1', # Multi-processor Communication
+ 'UCSR2B' : '$d1', # USART Control and Status Regis
+ 'UCSR2B_RXCIE2': '$80', # RX Complete Interrupt Enable
+ 'UCSR2B_TXCIE2': '$40', # TX Complete Interrupt Enable
+ 'UCSR2B_UDRIE2': '$20', # USART Data register Empty Inte
+ 'UCSR2B_RXEN2': '$10', # Receiver Enable
+ 'UCSR2B_TXEN2': '$8', # Transmitter Enable
+ 'UCSR2B_UCSZ22': '$4', # Character Size
+ 'UCSR2B_RXB82': '$2', # Receive Data Bit 8
+ 'UCSR2B_TXB82': '$1', # Transmit Data Bit 8
+ 'UCSR2C' : '$d2', # USART Control and Status Regis
+ 'UCSR2C_UMSEL2': '$c0', # USART Mode Select
+ 'UCSR2C_UPM2': '$30', # Parity Mode Bits
+ 'UCSR2C_USBS2': '$8', # Stop Bit Select
+ 'UCSR2C_UCSZ2': '$6', # Character Size
+ 'UCSR2C_UCPOL2': '$1', # Clock Polarity
+ 'UBRR2' : '$d4', # USART Baud Rate Register Byte
+
+# Module USART3
+ 'UDR3' : '$136', # USART I/O Data Register
+ 'UCSR3A' : '$130', # USART Control and Status Regis
+ 'UCSR3A_RXC3': '$80', # USART Receive Complete
+ 'UCSR3A_TXC3': '$40', # USART Transmitt Complete
+ 'UCSR3A_UDRE3': '$20', # USART Data Register Empty
+ 'UCSR3A_FE3': '$10', # Framing Error
+ 'UCSR3A_DOR3': '$8', # Data overRun
+ 'UCSR3A_UPE3': '$4', # Parity Error
+ 'UCSR3A_U2X3': '$2', # Double the USART transmission
+ 'UCSR3A_MPCM3': '$1', # Multi-processor Communication
+ 'UCSR3B' : '$131', # USART Control and Status Regis
+ 'UCSR3B_RXCIE3': '$80', # RX Complete Interrupt Enable
+ 'UCSR3B_TXCIE3': '$40', # TX Complete Interrupt Enable
+ 'UCSR3B_UDRIE3': '$20', # USART Data register Empty Inte
+ 'UCSR3B_RXEN3': '$10', # Receiver Enable
+ 'UCSR3B_TXEN3': '$8', # Transmitter Enable
+ 'UCSR3B_UCSZ32': '$4', # Character Size
+ 'UCSR3B_RXB83': '$2', # Receive Data Bit 8
+ 'UCSR3B_TXB83': '$1', # Transmit Data Bit 8
+ 'UCSR3C' : '$132', # USART Control and Status Regis
+ 'UCSR3C_UMSEL3': '$c0', # USART Mode Select
+ 'UCSR3C_UPM3': '$30', # Parity Mode Bits
+ 'UCSR3C_USBS3': '$8', # Stop Bit Select
+ 'UCSR3C_UCSZ3': '$6', # Character Size
+ 'UCSR3C_UCPOL3': '$1', # Clock Polarity
+ 'UBRR3' : '$134', # USART Baud Rate Register Byte
+
+ '__amforth_dummy':'0'
+}
diff --git a/amforth-6.5/avr8/devices/atmega2560/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega2560/words/no-jtag.asm
new file mode 100644
index 0000000..352a4bb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega2560/words/no-jtag.asm
@@ -0,0 +1,14 @@
+; ( -- )
+; ( -- )
+; MCU
+; disable jtag at runtime
+VE_NOJTAG:
+ .dw $FF05
+ .db "-jtag",0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOJTAG
+XT_NOJTAG:
+ .dw PFA_NOJTAG
+PFA_NOJTAG:
+
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega2560/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega2560/words/no-wdt.asm
new file mode 100644
index 0000000..ff6ddd1
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega2560/words/no-wdt.asm
@@ -0,0 +1,34 @@
+; ( -- )
+; MCU
+; disable watch dog timer at runtime
+VE_NOWDT:
+ .dw $ff04
+ .db "-wdt"
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOWDT
+XT_NOWDT:
+ .dw PFA_NOWDT
+PFA_NOWDT:
+
+ in temp1,SREG
+ push temp1
+ ; Turn always off global interrupt.
+ cli
+ ; Reset Watchdog Timer
+ wdr
+ ; Clear WDRF in MCUSR
+ in temp1, MCUSR
+ andi temp1, (0xff & (0<<WDRF))
+ out MCUSR, temp1
+ ; Write logical one to WDCE and WDE
+ ; Keep old prescaler setting to prevent unintentional time-out
+ in_ temp1, WDTCSR
+ ori temp1, (1<<WDCE) | (1<<WDE)
+ out_ WDTCSR, temp1
+ ; Turn off WDT
+ ldi temp1, (0<<WDE)
+ out_ WDTCSR, temp1
+ ; restore status register
+ pop temp1
+ out SREG,temp1
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega2560/words/sleep.asm b/amforth-6.5/avr8/devices/atmega2560/words/sleep.asm
new file mode 100644
index 0000000..256249c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega2560/words/sleep.asm
@@ -0,0 +1,19 @@
+; ( mode -- )
+; MCU
+; put the controller into the specified sleep mode
+VE_SLEEP:
+ .dw $ff05
+ .db "sleep", 0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_SLEEP
+XT_SLEEP:
+ .dw PFA_SLEEP
+PFA_SLEEP:
+ andi tosl, 7 ; leave only legal mode bits
+ lsl tosl ; move to correct location (bits 3-1)
+ ori tosl, 1 ; set the SE bit
+ out_ SMCR, tosl ; set the sleep config
+ sleep ; nighty-night
+ out_ SMCR, zerol ; 0 protects against accidental sleeps
+ loadtos ; pop argument from stack
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega2561/atmega2561.frt b/amforth-6.5/avr8/devices/atmega2561/atmega2561.frt
new file mode 100644
index 0000000..ead48f6
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega2561/atmega2561.frt
@@ -0,0 +1,510 @@
+\ Partname: ATmega2561
+\ generated automatically
+
+\ ANALOG_COMPARATOR
+&123 constant ADCSRB \ ADC Control and Status Register B
+ $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer Enable
+&80 constant ACSR \ Analog Comparator Control And Status Register
+ $80 constant ACSR_ACD \ Analog Comparator Disable
+ $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
+ $20 constant ACSR_ACO \ Analog Compare Output
+ $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
+ $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
+ $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
+ $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
+&127 constant DIDR1 \ Digital Input Disable Register 1
+ $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
+ $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
+\ USART0
+&198 constant UDR0 \ USART I/O Data Register
+&192 constant UCSR0A \ USART Control and Status Register A
+ $80 constant UCSR0A_RXC0 \ USART Receive Complete
+ $40 constant UCSR0A_TXC0 \ USART Transmitt Complete
+ $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
+ $10 constant UCSR0A_FE0 \ Framing Error
+ $08 constant UCSR0A_DOR0 \ Data overRun
+ $04 constant UCSR0A_UPE0 \ Parity Error
+ $02 constant UCSR0A_U2X0 \ Double the USART transmission speed
+ $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
+&193 constant UCSR0B \ USART Control and Status Register B
+ $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
+ $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
+ $20 constant UCSR0B_UDRIE0 \ USART Data register Empty Interrupt Enable
+ $10 constant UCSR0B_RXEN0 \ Receiver Enable
+ $08 constant UCSR0B_TXEN0 \ Transmitter Enable
+ $04 constant UCSR0B_UCSZ02 \ Character Size
+ $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
+ $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
+&194 constant UCSR0C \ USART Control and Status Register C
+ $C0 constant UCSR0C_UMSEL0 \ USART Mode Select
+ $30 constant UCSR0C_UPM0 \ Parity Mode Bits
+ $08 constant UCSR0C_USBS0 \ Stop Bit Select
+ $06 constant UCSR0C_UCSZ0 \ Character Size
+ $01 constant UCSR0C_UCPOL0 \ Clock Polarity
+&196 constant UBRR0 \ USART Baud Rate Register Bytes
+\ TWI
+&189 constant TWAMR \ TWI (Slave) Address Mask Register
+ $FE constant TWAMR_TWAM \
+&184 constant TWBR \ TWI Bit Rate register
+&188 constant TWCR \ TWI Control Register
+ $80 constant TWCR_TWINT \ TWI Interrupt Flag
+ $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
+ $20 constant TWCR_TWSTA \ TWI Start Condition Bit
+ $10 constant TWCR_TWSTO \ TWI Stop Condition Bit
+ $08 constant TWCR_TWWC \ TWI Write Collition Flag
+ $04 constant TWCR_TWEN \ TWI Enable Bit
+ $01 constant TWCR_TWIE \ TWI Interrupt Enable
+&185 constant TWSR \ TWI Status Register
+ $F8 constant TWSR_TWS \ TWI Status
+ $03 constant TWSR_TWPS \ TWI Prescaler
+&187 constant TWDR \ TWI Data register
+&186 constant TWAR \ TWI (Slave) Address register
+ $FE constant TWAR_TWA \ TWI (Slave) Address register Bits
+ $01 constant TWAR_TWGCE \ TWI General Call Recognition Enable Bit
+\ SPI
+&76 constant SPCR \ SPI Control Register
+ $80 constant SPCR_SPIE \ SPI Interrupt Enable
+ $40 constant SPCR_SPE \ SPI Enable
+ $20 constant SPCR_DORD \ Data Order
+ $10 constant SPCR_MSTR \ Master/Slave Select
+ $08 constant SPCR_CPOL \ Clock polarity
+ $04 constant SPCR_CPHA \ Clock Phase
+ $03 constant SPCR_SPR \ SPI Clock Rate Selects
+&77 constant SPSR \ SPI Status Register
+ $80 constant SPSR_SPIF \ SPI Interrupt Flag
+ $40 constant SPSR_WCOL \ Write Collision Flag
+ $01 constant SPSR_SPI2X \ Double SPI Speed Bit
+&78 constant SPDR \ SPI Data Register
+\ PORTA
+&34 constant PORTA \ Port A Data Register
+&33 constant DDRA \ Port A Data Direction Register
+&32 constant PINA \ Port A Input Pins
+\ PORTB
+&37 constant PORTB \ Port B Data Register
+&36 constant DDRB \ Port B Data Direction Register
+&35 constant PINB \ Port B Input Pins
+\ PORTC
+&40 constant PORTC \ Port C Data Register
+&39 constant DDRC \ Port C Data Direction Register
+&38 constant PINC \ Port C Input Pins
+\ PORTD
+&43 constant PORTD \ Port D Data Register
+&42 constant DDRD \ Port D Data Direction Register
+&41 constant PIND \ Port D Input Pins
+\ PORTE
+&46 constant PORTE \ Data Register, Port E
+&45 constant DDRE \ Data Direction Register, Port E
+&44 constant PINE \ Input Pins, Port E
+\ PORTF
+&49 constant PORTF \ Data Register, Port F
+&48 constant DDRF \ Data Direction Register, Port F
+&47 constant PINF \ Input Pins, Port F
+\ PORTG
+&52 constant PORTG \ Data Register, Port G
+&51 constant DDRG \ Data Direction Register, Port G
+&50 constant PING \ Input Pins, Port G
+\ TIMER_COUNTER_0
+&72 constant OCR0B \ Timer/Counter0 Output Compare Register
+&71 constant OCR0A \ Timer/Counter0 Output Compare Register
+&70 constant TCNT0 \ Timer/Counter0
+&69 constant TCCR0B \ Timer/Counter Control Register B
+ $80 constant TCCR0B_FOC0A \ Force Output Compare A
+ $40 constant TCCR0B_FOC0B \ Force Output Compare B
+ $08 constant TCCR0B_WGM02 \
+ $07 constant TCCR0B_CS0 \ Clock Select
+&68 constant TCCR0A \ Timer/Counter Control Register A
+ $C0 constant TCCR0A_COM0A \ Compare Output Mode, Phase Correct PWM Mode
+ $30 constant TCCR0A_COM0B \ Compare Output Mode, Fast PWm
+ $03 constant TCCR0A_WGM0 \ Waveform Generation Mode
+&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
+ $04 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare Match B Interrupt Enable
+ $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match A Interrupt Enable
+ $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
+&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
+ $04 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare Flag 0B
+ $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0A
+ $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
+&67 constant GTCCR \ General Timer/Counter Control Register
+ $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
+ $01 constant GTCCR_PSRSYNC \ Prescaler Reset Timer/Counter1 and Timer/Counter0
+\ TIMER_COUNTER_2
+&112 constant TIMSK2 \ Timer/Counter Interrupt Mask register
+ $04 constant TIMSK2_OCIE2B \ Timer/Counter2 Output Compare Match B Interrupt Enable
+ $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match A Interrupt Enable
+ $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
+&55 constant TIFR2 \ Timer/Counter Interrupt Flag Register
+ $04 constant TIFR2_OCF2B \ Output Compare Flag 2B
+ $02 constant TIFR2_OCF2A \ Output Compare Flag 2A
+ $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
+&176 constant TCCR2A \ Timer/Counter2 Control Register A
+ $C0 constant TCCR2A_COM2A \ Compare Output Mode bits
+ $30 constant TCCR2A_COM2B \ Compare Output Mode bits
+ $03 constant TCCR2A_WGM2 \ Waveform Genration Mode
+&177 constant TCCR2B \ Timer/Counter2 Control Register B
+ $80 constant TCCR2B_FOC2A \ Force Output Compare A
+ $40 constant TCCR2B_FOC2B \ Force Output Compare B
+ $08 constant TCCR2B_WGM22 \ Waveform Generation Mode
+ $07 constant TCCR2B_CS2 \ Clock Select bits
+&178 constant TCNT2 \ Timer/Counter2
+&180 constant OCR2B \ Timer/Counter2 Output Compare Register B
+&179 constant OCR2A \ Timer/Counter2 Output Compare Register A
+&182 constant ASSR \ Asynchronous Status Register
+ $40 constant ASSR_EXCLK \ Enable External Clock Input
+ $20 constant ASSR_AS2 \ Asynchronous Timer/Counter2
+ $10 constant ASSR_TCN2UB \ Timer/Counter2 Update Busy
+ $08 constant ASSR_OCR2AUB \ Output Compare Register2 Update Busy
+ $04 constant ASSR_OCR2BUB \ Output Compare Register 2 Update Busy
+ $02 constant ASSR_TCR2AUB \ Timer/Counter Control Register2 Update Busy
+ $01 constant ASSR_TCR2BUB \ Timer/Counter Control Register2 Update Busy
+\ WATCHDOG
+&96 constant WDTCSR \ Watchdog Timer Control Register
+ $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Flag
+ $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Enable
+ $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
+ $10 constant WDTCSR_WDCE \ Watchdog Change Enable
+ $08 constant WDTCSR_WDE \ Watch Dog Enable
+\ USART1
+&206 constant UDR1 \ USART I/O Data Register
+&200 constant UCSR1A \ USART Control and Status Register A
+ $80 constant UCSR1A_RXC1 \ USART Receive Complete
+ $40 constant UCSR1A_TXC1 \ USART Transmitt Complete
+ $20 constant UCSR1A_UDRE1 \ USART Data Register Empty
+ $10 constant UCSR1A_FE1 \ Framing Error
+ $08 constant UCSR1A_DOR1 \ Data overRun
+ $04 constant UCSR1A_UPE1 \ Parity Error
+ $02 constant UCSR1A_U2X1 \ Double the USART transmission speed
+ $01 constant UCSR1A_MPCM1 \ Multi-processor Communication Mode
+&201 constant UCSR1B \ USART Control and Status Register B
+ $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable
+ $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable
+ $20 constant UCSR1B_UDRIE1 \ USART Data register Empty Interrupt Enable
+ $10 constant UCSR1B_RXEN1 \ Receiver Enable
+ $08 constant UCSR1B_TXEN1 \ Transmitter Enable
+ $04 constant UCSR1B_UCSZ12 \ Character Size
+ $02 constant UCSR1B_RXB81 \ Receive Data Bit 8
+ $01 constant UCSR1B_TXB81 \ Transmit Data Bit 8
+&202 constant UCSR1C \ USART Control and Status Register C
+ $C0 constant UCSR1C_UMSEL1 \ USART Mode Select
+ $30 constant UCSR1C_UPM1 \ Parity Mode Bits
+ $08 constant UCSR1C_USBS1 \ Stop Bit Select
+ $06 constant UCSR1C_UCSZ1 \ Character Size
+ $01 constant UCSR1C_UCPOL1 \ Clock Polarity
+&204 constant UBRR1 \ USART Baud Rate Register Bytes
+\ EEPROM
+&65 constant EEAR \ EEPROM Address Register Low Bytes
+&64 constant EEDR \ EEPROM Data Register
+&63 constant EECR \ EEPROM Control Register
+ $30 constant EECR_EEPM \ EEPROM Programming Mode Bits
+ $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
+ $04 constant EECR_EEMPE \ EEPROM Master Write Enable
+ $02 constant EECR_EEPE \ EEPROM Write Enable
+ $01 constant EECR_EERE \ EEPROM Read Enable
+\ TIMER_COUNTER_5
+&288 constant TCCR5A \ Timer/Counter5 Control Register A
+ $C0 constant TCCR5A_COM5A \ Compare Output Mode 1A, bits
+ $30 constant TCCR5A_COM5B \ Compare Output Mode 5B, bits
+ $0C constant TCCR5A_COM5C \ Compare Output Mode 5C, bits
+ $03 constant TCCR5A_WGM5 \ Waveform Generation Mode
+&289 constant TCCR5B \ Timer/Counter5 Control Register B
+ $80 constant TCCR5B_ICNC5 \ Input Capture 5 Noise Canceler
+ $40 constant TCCR5B_ICES5 \ Input Capture 5 Edge Select
+ $18 constant TCCR5B_WGM5 \ Waveform Generation Mode
+ $07 constant TCCR5B_CS5 \ Prescaler source of Timer/Counter 5
+&290 constant TCCR5C \ Timer/Counter 5 Control Register C
+ $80 constant TCCR5C_FOC5A \ Force Output Compare 5A
+ $40 constant TCCR5C_FOC5B \ Force Output Compare 5B
+ $20 constant TCCR5C_FOC5C \ Force Output Compare 5C
+&292 constant TCNT5 \ Timer/Counter5 Bytes
+&296 constant OCR5A \ Timer/Counter5 Output Compare Register A Bytes
+&298 constant OCR5B \ Timer/Counter5 Output Compare Register B Bytes
+&300 constant OCR5C \ Timer/Counter5 Output Compare Register B Bytes
+&294 constant ICR5 \ Timer/Counter5 Input Capture Register Bytes
+&115 constant TIMSK5 \ Timer/Counter5 Interrupt Mask Register
+ $20 constant TIMSK5_ICIE5 \ Timer/Counter5 Input Capture Interrupt Enable
+ $08 constant TIMSK5_OCIE5C \ Timer/Counter5 Output Compare C Match Interrupt Enable
+ $04 constant TIMSK5_OCIE5B \ Timer/Counter5 Output Compare B Match Interrupt Enable
+ $02 constant TIMSK5_OCIE5A \ Timer/Counter5 Output Compare A Match Interrupt Enable
+ $01 constant TIMSK5_TOIE5 \ Timer/Counter5 Overflow Interrupt Enable
+&58 constant TIFR5 \ Timer/Counter5 Interrupt Flag register
+ $20 constant TIFR5_ICF5 \ Input Capture Flag 5
+ $08 constant TIFR5_OCF5C \ Output Compare Flag 5C
+ $04 constant TIFR5_OCF5B \ Output Compare Flag 5B
+ $02 constant TIFR5_OCF5A \ Output Compare Flag 5A
+ $01 constant TIFR5_TOV5 \ Timer/Counter5 Overflow Flag
+\ TIMER_COUNTER_4
+&160 constant TCCR4A \ Timer/Counter4 Control Register A
+ $C0 constant TCCR4A_COM4A \ Compare Output Mode 1A, bits
+ $30 constant TCCR4A_COM4B \ Compare Output Mode 4B, bits
+ $0C constant TCCR4A_COM4C \ Compare Output Mode 4C, bits
+ $03 constant TCCR4A_WGM4 \ Waveform Generation Mode
+&161 constant TCCR4B \ Timer/Counter4 Control Register B
+ $80 constant TCCR4B_ICNC4 \ Input Capture 4 Noise Canceler
+ $40 constant TCCR4B_ICES4 \ Input Capture 4 Edge Select
+ $18 constant TCCR4B_WGM4 \ Waveform Generation Mode
+ $07 constant TCCR4B_CS4 \ Prescaler source of Timer/Counter 4
+&162 constant TCCR4C \ Timer/Counter 4 Control Register C
+ $80 constant TCCR4C_FOC4A \ Force Output Compare 4A
+ $40 constant TCCR4C_FOC4B \ Force Output Compare 4B
+ $20 constant TCCR4C_FOC4C \ Force Output Compare 4C
+&164 constant TCNT4 \ Timer/Counter4 Bytes
+&168 constant OCR4A \ Timer/Counter4 Output Compare Register A Bytes
+&170 constant OCR4B \ Timer/Counter4 Output Compare Register B Bytes
+&172 constant OCR4C \ Timer/Counter4 Output Compare Register B Bytes
+&166 constant ICR4 \ Timer/Counter4 Input Capture Register Bytes
+&114 constant TIMSK4 \ Timer/Counter4 Interrupt Mask Register
+ $20 constant TIMSK4_ICIE4 \ Timer/Counter4 Input Capture Interrupt Enable
+ $08 constant TIMSK4_OCIE4C \ Timer/Counter4 Output Compare C Match Interrupt Enable
+ $04 constant TIMSK4_OCIE4B \ Timer/Counter4 Output Compare B Match Interrupt Enable
+ $02 constant TIMSK4_OCIE4A \ Timer/Counter4 Output Compare A Match Interrupt Enable
+ $01 constant TIMSK4_TOIE4 \ Timer/Counter4 Overflow Interrupt Enable
+&57 constant TIFR4 \ Timer/Counter4 Interrupt Flag register
+ $20 constant TIFR4_ICF4 \ Input Capture Flag 4
+ $08 constant TIFR4_OCF4C \ Output Compare Flag 4C
+ $04 constant TIFR4_OCF4B \ Output Compare Flag 4B
+ $02 constant TIFR4_OCF4A \ Output Compare Flag 4A
+ $01 constant TIFR4_TOV4 \ Timer/Counter4 Overflow Flag
+\ TIMER_COUNTER_3
+&144 constant TCCR3A \ Timer/Counter3 Control Register A
+ $C0 constant TCCR3A_COM3A \ Compare Output Mode 1A, bits
+ $30 constant TCCR3A_COM3B \ Compare Output Mode 3B, bits
+ $0C constant TCCR3A_COM3C \ Compare Output Mode 3C, bits
+ $03 constant TCCR3A_WGM3 \ Waveform Generation Mode
+&145 constant TCCR3B \ Timer/Counter3 Control Register B
+ $80 constant TCCR3B_ICNC3 \ Input Capture 3 Noise Canceler
+ $40 constant TCCR3B_ICES3 \ Input Capture 3 Edge Select
+ $18 constant TCCR3B_WGM3 \ Waveform Generation Mode
+ $07 constant TCCR3B_CS3 \ Prescaler source of Timer/Counter 3
+&146 constant TCCR3C \ Timer/Counter 3 Control Register C
+ $80 constant TCCR3C_FOC3A \ Force Output Compare 3A
+ $40 constant TCCR3C_FOC3B \ Force Output Compare 3B
+ $20 constant TCCR3C_FOC3C \ Force Output Compare 3C
+&148 constant TCNT3 \ Timer/Counter3 Bytes
+&152 constant OCR3A \ Timer/Counter3 Output Compare Register A Bytes
+&154 constant OCR3B \ Timer/Counter3 Output Compare Register B Bytes
+&156 constant OCR3C \ Timer/Counter3 Output Compare Register B Bytes
+&150 constant ICR3 \ Timer/Counter3 Input Capture Register Bytes
+&113 constant TIMSK3 \ Timer/Counter3 Interrupt Mask Register
+ $20 constant TIMSK3_ICIE3 \ Timer/Counter3 Input Capture Interrupt Enable
+ $08 constant TIMSK3_OCIE3C \ Timer/Counter3 Output Compare C Match Interrupt Enable
+ $04 constant TIMSK3_OCIE3B \ Timer/Counter3 Output Compare B Match Interrupt Enable
+ $02 constant TIMSK3_OCIE3A \ Timer/Counter3 Output Compare A Match Interrupt Enable
+ $01 constant TIMSK3_TOIE3 \ Timer/Counter3 Overflow Interrupt Enable
+&56 constant TIFR3 \ Timer/Counter3 Interrupt Flag register
+ $20 constant TIFR3_ICF3 \ Input Capture Flag 3
+ $08 constant TIFR3_OCF3C \ Output Compare Flag 3C
+ $04 constant TIFR3_OCF3B \ Output Compare Flag 3B
+ $02 constant TIFR3_OCF3A \ Output Compare Flag 3A
+ $01 constant TIFR3_TOV3 \ Timer/Counter3 Overflow Flag
+\ TIMER_COUNTER_1
+&128 constant TCCR1A \ Timer/Counter1 Control Register A
+ $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
+ $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
+ $0C constant TCCR1A_COM1C \ Compare Output Mode 1C, bits
+ $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
+&129 constant TCCR1B \ Timer/Counter1 Control Register B
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
+ $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
+&130 constant TCCR1C \ Timer/Counter 1 Control Register C
+ $80 constant TCCR1C_FOC1A \ Force Output Compare 1A
+ $40 constant TCCR1C_FOC1B \ Force Output Compare 1B
+ $20 constant TCCR1C_FOC1C \ Force Output Compare 1C
+&132 constant TCNT1 \ Timer/Counter1 Bytes
+&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
+&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
+&140 constant OCR1C \ Timer/Counter1 Output Compare Register C Bytes
+&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
+&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
+ $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
+ $08 constant TIMSK1_OCIE1C \ Timer/Counter1 Output Compare C Match Interrupt Enable
+ $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
+ $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
+ $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
+&54 constant TIFR1 \ Timer/Counter1 Interrupt Flag register
+ $20 constant TIFR1_ICF1 \ Input Capture Flag 1
+ $08 constant TIFR1_OCF1C \ Output Compare Flag 1C
+ $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
+ $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
+ $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
+\ JTAG
+&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
+&85 constant MCUCR \ MCU Control Register
+ $80 constant MCUCR_JTD \ JTAG Interface Disable
+&84 constant MCUSR \ MCU Status Register
+ $10 constant MCUSR_JTRF \ JTAG Reset Flag
+\ EXTERNAL_INTERRUPT
+&105 constant EICRA \ External Interrupt Control Register A
+ $C0 constant EICRA_ISC3 \ External Interrupt Sense Control Bit
+ $30 constant EICRA_ISC2 \ External Interrupt Sense Control Bit
+ $0C constant EICRA_ISC1 \ External Interrupt Sense Control Bit
+ $03 constant EICRA_ISC0 \ External Interrupt Sense Control Bit
+&106 constant EICRB \ External Interrupt Control Register B
+ $C0 constant EICRB_ISC7 \ External Interrupt 7-4 Sense Control Bit
+ $30 constant EICRB_ISC6 \ External Interrupt 7-4 Sense Control Bit
+ $0C constant EICRB_ISC5 \ External Interrupt 7-4 Sense Control Bit
+ $03 constant EICRB_ISC4 \ External Interrupt 7-4 Sense Control Bit
+&61 constant EIMSK \ External Interrupt Mask Register
+ $FF constant EIMSK_INT \ External Interrupt Request 7 Enable
+&60 constant EIFR \ External Interrupt Flag Register
+ $FF constant EIFR_INTF \ External Interrupt Flags
+&109 constant PCMSK2 \ Pin Change Mask Register 2
+&108 constant PCMSK1 \ Pin Change Mask Register 1
+&107 constant PCMSK0 \ Pin Change Mask Register 0
+&59 constant PCIFR \ Pin Change Interrupt Flag Register
+ $07 constant PCIFR_PCIF \ Pin Change Interrupt Flags
+&104 constant PCICR \ Pin Change Interrupt Control Register
+ $07 constant PCICR_PCIE \ Pin Change Interrupt Enables
+\ CPU
+&95 constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ $08 constant SREG_V \ Two's Complement Overflow Flag
+ $04 constant SREG_N \ Negative Flag
+ $02 constant SREG_Z \ Zero Flag
+ $01 constant SREG_C \ Carry Flag
+&93 constant SP \ Stack Pointer
+&116 constant XMCRA \ External Memory Control Register A
+ $80 constant XMCRA_SRE \ External SRAM Enable
+ $70 constant XMCRA_SRL \ Wait state page limit
+ $0C constant XMCRA_SRW1 \ Wait state select bit upper page
+ $03 constant XMCRA_SRW0 \ Wait state select bit lower page
+&117 constant XMCRB \ External Memory Control Register B
+ $80 constant XMCRB_XMBK \ External Memory Bus Keeper Enable
+ $07 constant XMCRB_XMM \ External Memory High Mask
+&102 constant OSCCAL \ Oscillator Calibration Value
+&97 constant CLKPR \
+ $80 constant CLKPR_CLKPCE \
+ $0F constant CLKPR_CLKPS \
+&83 constant SMCR \ Sleep Mode Control Register
+ $0E constant SMCR_SM \ Sleep Mode Select bits
+ $01 constant SMCR_SE \ Sleep Enable
+&92 constant EIND \ Extended Indirect Register
+&91 constant RAMPZ \ RAM Page Z Select Register
+&75 constant GPIOR2 \ General Purpose IO Register 2
+ $FF constant GPIOR2_GPIOR \ General Purpose IO Register 2 bis
+&74 constant GPIOR1 \ General Purpose IO Register 1
+ $FF constant GPIOR1_GPIOR \ General Purpose IO Register 1 bis
+&62 constant GPIOR0 \ General Purpose IO Register 0
+ $80 constant GPIOR0_GPIOR07 \ General Purpose IO Register 0 bit 7
+ $40 constant GPIOR0_GPIOR06 \ General Purpose IO Register 0 bit 6
+ $20 constant GPIOR0_GPIOR05 \ General Purpose IO Register 0 bit 5
+ $10 constant GPIOR0_GPIOR04 \ General Purpose IO Register 0 bit 4
+ $08 constant GPIOR0_GPIOR03 \ General Purpose IO Register 0 bit 3
+ $04 constant GPIOR0_GPIOR02 \ General Purpose IO Register 0 bit 2
+ $02 constant GPIOR0_GPIOR01 \ General Purpose IO Register 0 bit 1
+ $01 constant GPIOR0_GPIOR00 \ General Purpose IO Register 0 bit 0
+&101 constant PRR1 \ Power Reduction Register1
+ $20 constant PRR1_PRTIM5 \ Power Reduction Timer/Counter5
+ $10 constant PRR1_PRTIM4 \ Power Reduction Timer/Counter4
+ $08 constant PRR1_PRTIM3 \ Power Reduction Timer/Counter3
+ $07 constant PRR1_PRUSART \ Power Reduction USART3
+&100 constant PRR0 \ Power Reduction Register0
+ $80 constant PRR0_PRTWI \ Power Reduction TWI
+ $40 constant PRR0_PRTIM2 \ Power Reduction Timer/Counter2
+ $20 constant PRR0_PRTIM0 \ Power Reduction Timer/Counter0
+ $08 constant PRR0_PRTIM1 \ Power Reduction Timer/Counter1
+ $04 constant PRR0_PRSPI \ Power Reduction Serial Peripheral Interface
+ $02 constant PRR0_PRUSART0 \ Power Reduction USART
+ $01 constant PRR0_PRADC \ Power Reduction ADC
+\ AD_CONVERTER
+&124 constant ADMUX \ The ADC multiplexer Selection Register
+ $C0 constant ADMUX_REFS \ Reference Selection Bits
+ $20 constant ADMUX_ADLAR \ Left Adjust Result
+ $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
+&120 constant ADC \ ADC Data Register Bytes
+&122 constant ADCSRA \ The ADC Control and Status register A
+ $80 constant ADCSRA_ADEN \ ADC Enable
+ $40 constant ADCSRA_ADSC \ ADC Start Conversion
+ $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
+ $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
+ $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
+ $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
+&125 constant DIDR2 \ Digital Input Disable Register
+ $80 constant DIDR2_ADC15D \
+ $40 constant DIDR2_ADC14D \
+ $20 constant DIDR2_ADC13D \
+ $10 constant DIDR2_ADC12D \
+ $08 constant DIDR2_ADC11D \
+ $04 constant DIDR2_ADC10D \
+ $02 constant DIDR2_ADC9D \
+ $01 constant DIDR2_ADC8D \
+&126 constant DIDR0 \ Digital Input Disable Register
+ $80 constant DIDR0_ADC7D \
+ $40 constant DIDR0_ADC6D \
+ $20 constant DIDR0_ADC5D \
+ $10 constant DIDR0_ADC4D \
+ $08 constant DIDR0_ADC3D \
+ $04 constant DIDR0_ADC2D \
+ $02 constant DIDR0_ADC1D \
+ $01 constant DIDR0_ADC0D \
+\ BOOT_LOAD
+&87 constant SPMCSR \ Store Program Memory Control Register
+ $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
+ $20 constant SPMCSR_SIGRD \ Signature Row Read
+ $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
+ $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
+ $04 constant SPMCSR_PGWRT \ Page Write
+ $02 constant SPMCSR_PGERS \ Page Erase
+ $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
+
+\ Interrupts
+&2 constant INT0Addr \ External Interrupt Request 0
+&4 constant INT1Addr \ External Interrupt Request 1
+&6 constant INT2Addr \ External Interrupt Request 2
+&8 constant INT3Addr \ External Interrupt Request 3
+&10 constant INT4Addr \ External Interrupt Request 4
+&12 constant INT5Addr \ External Interrupt Request 5
+&14 constant INT6Addr \ External Interrupt Request 6
+&16 constant INT7Addr \ External Interrupt Request 7
+&18 constant PCINT0Addr \ Pin Change Interrupt Request 0
+&20 constant PCINT1Addr \ Pin Change Interrupt Request 1
+&22 constant PCINT2Addr \ Pin Change Interrupt Request 2
+&24 constant WDTAddr \ Watchdog Time-out Interrupt
+&26 constant TIMER2_COMPAAddr \ Timer/Counter2 Compare Match A
+&28 constant TIMER2_COMPBAddr \ Timer/Counter2 Compare Match B
+&30 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
+&32 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+&34 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
+&36 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
+&38 constant TIMER1_COMPCAddr \ Timer/Counter1 Compare Match C
+&40 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+&42 constant TIMER0_COMPAAddr \ Timer/Counter0 Compare Match A
+&44 constant TIMER0_COMPBAddr \ Timer/Counter0 Compare Match B
+&46 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
+&48 constant SPI__STCAddr \ SPI Serial Transfer Complete
+&50 constant USART0__RXAddr \ USART0, Rx Complete
+&52 constant USART0__UDREAddr \ USART0 Data register Empty
+&54 constant USART0__TXAddr \ USART0, Tx Complete
+&56 constant ANALOG_COMPAddr \ Analog Comparator
+&58 constant ADCAddr \ ADC Conversion Complete
+&60 constant EE_READYAddr \ EEPROM Ready
+&62 constant TIMER3_CAPTAddr \ Timer/Counter3 Capture Event
+&64 constant TIMER3_COMPAAddr \ Timer/Counter3 Compare Match A
+&66 constant TIMER3_COMPBAddr \ Timer/Counter3 Compare Match B
+&68 constant TIMER3_COMPCAddr \ Timer/Counter3 Compare Match C
+&70 constant TIMER3_OVFAddr \ Timer/Counter3 Overflow
+&72 constant USART1__RXAddr \ USART1, Rx Complete
+&74 constant USART1__UDREAddr \ USART1 Data register Empty
+&76 constant USART1__TXAddr \ USART1, Tx Complete
+&78 constant TWIAddr \ 2-wire Serial Interface
+&80 constant SPM_READYAddr \ Store Program Memory Read
+&82 constant TIMER4_CAPTAddr \ Timer/Counter4 Capture Event
+&84 constant TIMER4_COMPAAddr \ Timer/Counter4 Compare Match A
+&86 constant TIMER4_COMPBAddr \ Timer/Counter4 Compare Match B
+&88 constant TIMER4_COMPCAddr \ Timer/Counter4 Compare Match C
+&90 constant TIMER4_OVFAddr \ Timer/Counter4 Overflow
+&92 constant TIMER5_CAPTAddr \ Timer/Counter5 Capture Event
+&94 constant TIMER5_COMPAAddr \ Timer/Counter5 Compare Match A
+&96 constant TIMER5_COMPBAddr \ Timer/Counter5 Compare Match B
+&98 constant TIMER5_COMPCAddr \ Timer/Counter5 Compare Match C
+&100 constant TIMER5_OVFAddr \ Timer/Counter5 Overflow
+&102 constant USART2__RXAddr \ USART2, Rx Complete
+&104 constant USART2__UDREAddr \ USART2 Data register Empty
+&106 constant USART2__TXAddr \ USART2, Tx Complete
+&108 constant USART3__RXAddr \ USART3, Rx Complete
+&110 constant USART3__UDREAddr \ USART3 Data register Empty
+&112 constant USART3__TXAddr \ USART3, Tx Complete
diff --git a/amforth-6.5/avr8/devices/atmega2561/device.asm b/amforth-6.5/avr8/devices/atmega2561/device.asm
new file mode 100644
index 0000000..e36ccef
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega2561/device.asm
@@ -0,0 +1,184 @@
+; Partname: ATmega2561
+; generated automatically, do not edit
+
+.nolist
+ .include "m2561def.inc"
+.list
+
+.equ ramstart = 512
+.equ CELLSIZE = 2
+.macro readflashcell
+ clr temp7
+ lsl zl
+ rol zh
+ rol temp7
+ out_ RAMPZ, temp7
+ elpm @0, Z+
+ elpm @1, Z+
+.endmacro
+.macro writeflashcell
+ clr temp7
+ lsl zl
+ rol zh
+ rol temp7
+ out_ RAMPZ, temp7
+.endmacro
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_USART0 = 0
+.set WANT_TWI = 0
+.set WANT_SPI = 0
+.set WANT_PORTA = 0
+.set WANT_PORTB = 0
+.set WANT_PORTC = 0
+.set WANT_PORTD = 0
+.set WANT_PORTE = 0
+.set WANT_PORTF = 0
+.set WANT_PORTG = 0
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_TIMER_COUNTER_2 = 0
+.set WANT_WATCHDOG = 0
+.set WANT_USART1 = 0
+.set WANT_EEPROM = 0
+.set WANT_TIMER_COUNTER_5 = 0
+.set WANT_TIMER_COUNTER_4 = 0
+.set WANT_TIMER_COUNTER_3 = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_JTAG = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_CPU = 0
+.set WANT_AD_CONVERTER = 0
+.set WANT_BOOT_LOAD = 0
+.equ intvecsize = 2 ; please verify; flash size: 262144 bytes
+.equ pclen = 3 ; please verify
+.overlap
+.org 2
+ rcall isr ; External Interrupt Request 0
+.org 4
+ rcall isr ; External Interrupt Request 1
+.org 6
+ rcall isr ; External Interrupt Request 2
+.org 8
+ rcall isr ; External Interrupt Request 3
+.org 10
+ rcall isr ; External Interrupt Request 4
+.org 12
+ rcall isr ; External Interrupt Request 5
+.org 14
+ rcall isr ; External Interrupt Request 6
+.org 16
+ rcall isr ; External Interrupt Request 7
+.org 18
+ rcall isr ; Pin Change Interrupt Request 0
+.org 20
+ rcall isr ; Pin Change Interrupt Request 1
+.org 22
+ rcall isr ; Pin Change Interrupt Request 2
+.org 24
+ rcall isr ; Watchdog Time-out Interrupt
+.org 26
+ rcall isr ; Timer/Counter2 Compare Match A
+.org 28
+ rcall isr ; Timer/Counter2 Compare Match B
+.org 30
+ rcall isr ; Timer/Counter2 Overflow
+.org 32
+ rcall isr ; Timer/Counter1 Capture Event
+.org 34
+ rcall isr ; Timer/Counter1 Compare Match A
+.org 36
+ rcall isr ; Timer/Counter1 Compare Match B
+.org 38
+ rcall isr ; Timer/Counter1 Compare Match C
+.org 40
+ rcall isr ; Timer/Counter1 Overflow
+.org 42
+ rcall isr ; Timer/Counter0 Compare Match A
+.org 44
+ rcall isr ; Timer/Counter0 Compare Match B
+.org 46
+ rcall isr ; Timer/Counter0 Overflow
+.org 48
+ rcall isr ; SPI Serial Transfer Complete
+.org 50
+ rcall isr ; USART0, Rx Complete
+.org 52
+ rcall isr ; USART0 Data register Empty
+.org 54
+ rcall isr ; USART0, Tx Complete
+.org 56
+ rcall isr ; Analog Comparator
+.org 58
+ rcall isr ; ADC Conversion Complete
+.org 60
+ rcall isr ; EEPROM Ready
+.org 62
+ rcall isr ; Timer/Counter3 Capture Event
+.org 64
+ rcall isr ; Timer/Counter3 Compare Match A
+.org 66
+ rcall isr ; Timer/Counter3 Compare Match B
+.org 68
+ rcall isr ; Timer/Counter3 Compare Match C
+.org 70
+ rcall isr ; Timer/Counter3 Overflow
+.org 72
+ rcall isr ; USART1, Rx Complete
+.org 74
+ rcall isr ; USART1 Data register Empty
+.org 76
+ rcall isr ; USART1, Tx Complete
+.org 78
+ rcall isr ; 2-wire Serial Interface
+.org 80
+ rcall isr ; Store Program Memory Read
+.org 82
+ rcall isr ; Timer/Counter4 Capture Event
+.org 84
+ rcall isr ; Timer/Counter4 Compare Match A
+.org 86
+ rcall isr ; Timer/Counter4 Compare Match B
+.org 88
+ rcall isr ; Timer/Counter4 Compare Match C
+.org 90
+ rcall isr ; Timer/Counter4 Overflow
+.org 92
+ rcall isr ; Timer/Counter5 Capture Event
+.org 94
+ rcall isr ; Timer/Counter5 Compare Match A
+.org 96
+ rcall isr ; Timer/Counter5 Compare Match B
+.org 98
+ rcall isr ; Timer/Counter5 Compare Match C
+.org 100
+ rcall isr ; Timer/Counter5 Overflow
+.org 102
+ rcall isr ; USART2, Rx Complete
+.org 104
+ rcall isr ; USART2 Data register Empty
+.org 106
+ rcall isr ; USART2, Tx Complete
+.org 108
+ rcall isr ; USART3, Rx Complete
+.org 110
+ rcall isr ; USART3 Data register Empty
+.org 112
+ rcall isr ; USART3, Tx Complete
+.equ INTVECTORS = 57
+.nooverlap
+
+; compatability layer (maybe empty)
+
+; controller data area, environment query mcu-info
+mcu_info:
+mcu_ramsize:
+ .dw 8192
+mcu_eepromsize:
+ .dw 4096
+mcu_maxdp:
+ .dw 65535
+mcu_numints:
+ .dw 57
+mcu_name:
+ .dw 10
+ .db "ATmega2561"
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega2561/device.inc b/amforth-6.5/avr8/devices/atmega2561/device.inc
new file mode 100644
index 0000000..15ef0ad
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega2561/device.inc
@@ -0,0 +1,1698 @@
+; Partname: ATmega2561
+; generated automatically, no not edit
+
+.if WANT_ANALOG_COMPARATOR == 1
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Control and Status Register B
+VE_ADCSRB:
+ .dw $ff06
+ .db "ADCSRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRB
+XT_ADCSRB:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRB:
+ .dw 123
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Control And Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw 80
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 1
+VE_DIDR1:
+ .dw $ff05
+ .db "DIDR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR1
+XT_DIDR1:
+ .dw PFA_DOVARIABLE
+PFA_DIDR1:
+ .dw 127
+
+.endif
+.if WANT_USART0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR0:
+ .dw $ff04
+ .db "UDR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR0
+XT_UDR0:
+ .dw PFA_DOVARIABLE
+PFA_UDR0:
+ .dw 198
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR0A:
+ .dw $ff06
+ .db "UCSR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0A
+XT_UCSR0A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0A:
+ .dw 192
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR0B:
+ .dw $ff06
+ .db "UCSR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0B
+XT_UCSR0B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0B:
+ .dw 193
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR0C:
+ .dw $ff06
+ .db "UCSR0C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0C
+XT_UCSR0C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0C:
+ .dw 194
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Bytes
+VE_UBRR0:
+ .dw $ff05
+ .db "UBRR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR0
+XT_UBRR0:
+ .dw PFA_DOVARIABLE
+PFA_UBRR0:
+ .dw 196
+
+.endif
+.if WANT_TWI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; TWI (Slave) Address Mask Register
+VE_TWAMR:
+ .dw $ff05
+ .db "TWAMR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWAMR
+XT_TWAMR:
+ .dw PFA_DOVARIABLE
+PFA_TWAMR:
+ .dw 189
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Bit Rate register
+VE_TWBR:
+ .dw $ff04
+ .db "TWBR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWBR
+XT_TWBR:
+ .dw PFA_DOVARIABLE
+PFA_TWBR:
+ .dw 184
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Control Register
+VE_TWCR:
+ .dw $ff04
+ .db "TWCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWCR
+XT_TWCR:
+ .dw PFA_DOVARIABLE
+PFA_TWCR:
+ .dw 188
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Status Register
+VE_TWSR:
+ .dw $ff04
+ .db "TWSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWSR
+XT_TWSR:
+ .dw PFA_DOVARIABLE
+PFA_TWSR:
+ .dw 185
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Data register
+VE_TWDR:
+ .dw $ff04
+ .db "TWDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWDR
+XT_TWDR:
+ .dw PFA_DOVARIABLE
+PFA_TWDR:
+ .dw 187
+; ( -- addr ) System Constant
+; R( -- )
+; TWI (Slave) Address register
+VE_TWAR:
+ .dw $ff04
+ .db "TWAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWAR
+XT_TWAR:
+ .dw PFA_DOVARIABLE
+PFA_TWAR:
+ .dw 186
+
+.endif
+.if WANT_SPI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR:
+ .dw $ff04
+ .db "SPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR
+XT_SPCR:
+ .dw PFA_DOVARIABLE
+PFA_SPCR:
+ .dw 76
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR:
+ .dw $ff04
+ .db "SPSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR
+XT_SPSR:
+ .dw PFA_DOVARIABLE
+PFA_SPSR:
+ .dw 77
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR:
+ .dw $ff04
+ .db "SPDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR
+XT_SPDR:
+ .dw PFA_DOVARIABLE
+PFA_SPDR:
+ .dw 78
+
+.endif
+.if WANT_PORTA == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Register
+VE_PORTA:
+ .dw $ff05
+ .db "PORTA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTA
+XT_PORTA:
+ .dw PFA_DOVARIABLE
+PFA_PORTA:
+ .dw 34
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Direction Register
+VE_DDRA:
+ .dw $ff04
+ .db "DDRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRA
+XT_DDRA:
+ .dw PFA_DOVARIABLE
+PFA_DDRA:
+ .dw 33
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Input Pins
+VE_PINA:
+ .dw $ff04
+ .db "PINA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINA
+XT_PINA:
+ .dw PFA_DOVARIABLE
+PFA_PINA:
+ .dw 32
+
+.endif
+.if WANT_PORTB == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw 37
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw 36
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw 35
+
+.endif
+.if WANT_PORTC == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Register
+VE_PORTC:
+ .dw $ff05
+ .db "PORTC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTC
+XT_PORTC:
+ .dw PFA_DOVARIABLE
+PFA_PORTC:
+ .dw 40
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Direction Register
+VE_DDRC:
+ .dw $ff04
+ .db "DDRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRC
+XT_DDRC:
+ .dw PFA_DOVARIABLE
+PFA_DDRC:
+ .dw 39
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Input Pins
+VE_PINC:
+ .dw $ff04
+ .db "PINC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINC
+XT_PINC:
+ .dw PFA_DOVARIABLE
+PFA_PINC:
+ .dw 38
+
+.endif
+.if WANT_PORTD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw 43
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw 42
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw 41
+
+.endif
+.if WANT_PORTE == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port E
+VE_PORTE:
+ .dw $ff05
+ .db "PORTE",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTE
+XT_PORTE:
+ .dw PFA_DOVARIABLE
+PFA_PORTE:
+ .dw 46
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port E
+VE_DDRE:
+ .dw $ff04
+ .db "DDRE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRE
+XT_DDRE:
+ .dw PFA_DOVARIABLE
+PFA_DDRE:
+ .dw 45
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port E
+VE_PINE:
+ .dw $ff04
+ .db "PINE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINE
+XT_PINE:
+ .dw PFA_DOVARIABLE
+PFA_PINE:
+ .dw 44
+
+.endif
+.if WANT_PORTF == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port F
+VE_PORTF:
+ .dw $ff05
+ .db "PORTF",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTF
+XT_PORTF:
+ .dw PFA_DOVARIABLE
+PFA_PORTF:
+ .dw 49
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port F
+VE_DDRF:
+ .dw $ff04
+ .db "DDRF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRF
+XT_DDRF:
+ .dw PFA_DOVARIABLE
+PFA_DDRF:
+ .dw 48
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port F
+VE_PINF:
+ .dw $ff04
+ .db "PINF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINF
+XT_PINF:
+ .dw PFA_DOVARIABLE
+PFA_PINF:
+ .dw 47
+
+.endif
+.if WANT_PORTG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port G
+VE_PORTG:
+ .dw $ff05
+ .db "PORTG",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTG
+XT_PORTG:
+ .dw PFA_DOVARIABLE
+PFA_PORTG:
+ .dw 52
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port G
+VE_DDRG:
+ .dw $ff04
+ .db "DDRG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRG
+XT_DDRG:
+ .dw PFA_DOVARIABLE
+PFA_DDRG:
+ .dw 51
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port G
+VE_PING:
+ .dw $ff04
+ .db "PING"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PING
+XT_PING:
+ .dw PFA_DOVARIABLE
+PFA_PING:
+ .dw 50
+
+.endif
+.if WANT_TIMER_COUNTER_0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0B:
+ .dw $ff05
+ .db "OCR0B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0B
+XT_OCR0B:
+ .dw PFA_DOVARIABLE
+PFA_OCR0B:
+ .dw 72
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0A:
+ .dw $ff05
+ .db "OCR0A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0A
+XT_OCR0A:
+ .dw PFA_DOVARIABLE
+PFA_OCR0A:
+ .dw 71
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw 70
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register B
+VE_TCCR0B:
+ .dw $ff06
+ .db "TCCR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0B
+XT_TCCR0B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0B:
+ .dw 69
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register A
+VE_TCCR0A:
+ .dw $ff06
+ .db "TCCR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0A
+XT_TCCR0A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0A:
+ .dw 68
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Mask Register
+VE_TIMSK0:
+ .dw $ff06
+ .db "TIMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK0
+XT_TIMSK0:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK0:
+ .dw 110
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Flag register
+VE_TIFR0:
+ .dw $ff05
+ .db "TIFR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR0
+XT_TIFR0:
+ .dw PFA_DOVARIABLE
+PFA_TIFR0:
+ .dw 53
+; ( -- addr ) System Constant
+; R( -- )
+; General Timer/Counter Control Register
+VE_GTCCR:
+ .dw $ff05
+ .db "GTCCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GTCCR
+XT_GTCCR:
+ .dw PFA_DOVARIABLE
+PFA_GTCCR:
+ .dw 67
+
+.endif
+.if WANT_TIMER_COUNTER_2 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Mask register
+VE_TIMSK2:
+ .dw $ff06
+ .db "TIMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK2
+XT_TIMSK2:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK2:
+ .dw 112
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Flag Register
+VE_TIFR2:
+ .dw $ff05
+ .db "TIFR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR2
+XT_TIFR2:
+ .dw PFA_DOVARIABLE
+PFA_TIFR2:
+ .dw 55
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register A
+VE_TCCR2A:
+ .dw $ff06
+ .db "TCCR2A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2A
+XT_TCCR2A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2A:
+ .dw 176
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register B
+VE_TCCR2B:
+ .dw $ff06
+ .db "TCCR2B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2B
+XT_TCCR2B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2B:
+ .dw 177
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2
+VE_TCNT2:
+ .dw $ff05
+ .db "TCNT2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT2
+XT_TCNT2:
+ .dw PFA_DOVARIABLE
+PFA_TCNT2:
+ .dw 178
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register B
+VE_OCR2B:
+ .dw $ff05
+ .db "OCR2B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2B
+XT_OCR2B:
+ .dw PFA_DOVARIABLE
+PFA_OCR2B:
+ .dw 180
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register A
+VE_OCR2A:
+ .dw $ff05
+ .db "OCR2A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2A
+XT_OCR2A:
+ .dw PFA_DOVARIABLE
+PFA_OCR2A:
+ .dw 179
+; ( -- addr ) System Constant
+; R( -- )
+; Asynchronous Status Register
+VE_ASSR:
+ .dw $ff04
+ .db "ASSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ASSR
+XT_ASSR:
+ .dw PFA_DOVARIABLE
+PFA_ASSR:
+ .dw 182
+
+.endif
+.if WANT_WATCHDOG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCSR:
+ .dw $ff06
+ .db "WDTCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCSR
+XT_WDTCSR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCSR:
+ .dw 96
+
+.endif
+.if WANT_USART1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR1:
+ .dw $ff04
+ .db "UDR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR1
+XT_UDR1:
+ .dw PFA_DOVARIABLE
+PFA_UDR1:
+ .dw 206
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR1A:
+ .dw $ff06
+ .db "UCSR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1A
+XT_UCSR1A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1A:
+ .dw 200
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR1B:
+ .dw $ff06
+ .db "UCSR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1B
+XT_UCSR1B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1B:
+ .dw 201
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR1C:
+ .dw $ff06
+ .db "UCSR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1C
+XT_UCSR1C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1C:
+ .dw 202
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Bytes
+VE_UBRR1:
+ .dw $ff05
+ .db "UBRR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR1
+XT_UBRR1:
+ .dw PFA_DOVARIABLE
+PFA_UBRR1:
+ .dw 204
+
+.endif
+.if WANT_EEPROM == 1
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Address Register Low Bytes
+VE_EEAR:
+ .dw $ff04
+ .db "EEAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEAR
+XT_EEAR:
+ .dw PFA_DOVARIABLE
+PFA_EEAR:
+ .dw 65
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw 64
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw 63
+
+.endif
+.if WANT_TIMER_COUNTER_5 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter5 Control Register A
+VE_TCCR5A:
+ .dw $ff06
+ .db "TCCR5A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR5A
+XT_TCCR5A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR5A:
+ .dw 288
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter5 Control Register B
+VE_TCCR5B:
+ .dw $ff06
+ .db "TCCR5B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR5B
+XT_TCCR5B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR5B:
+ .dw 289
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter 5 Control Register C
+VE_TCCR5C:
+ .dw $ff06
+ .db "TCCR5C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR5C
+XT_TCCR5C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR5C:
+ .dw 290
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter5 Bytes
+VE_TCNT5:
+ .dw $ff05
+ .db "TCNT5",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT5
+XT_TCNT5:
+ .dw PFA_DOVARIABLE
+PFA_TCNT5:
+ .dw 292
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter5 Output Compare Register A Bytes
+VE_OCR5A:
+ .dw $ff05
+ .db "OCR5A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR5A
+XT_OCR5A:
+ .dw PFA_DOVARIABLE
+PFA_OCR5A:
+ .dw 296
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter5 Output Compare Register B Bytes
+VE_OCR5B:
+ .dw $ff05
+ .db "OCR5B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR5B
+XT_OCR5B:
+ .dw PFA_DOVARIABLE
+PFA_OCR5B:
+ .dw 298
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter5 Output Compare Register B Bytes
+VE_OCR5C:
+ .dw $ff05
+ .db "OCR5C",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR5C
+XT_OCR5C:
+ .dw PFA_DOVARIABLE
+PFA_OCR5C:
+ .dw 300
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter5 Input Capture Register Bytes
+VE_ICR5:
+ .dw $ff04
+ .db "ICR5"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR5
+XT_ICR5:
+ .dw PFA_DOVARIABLE
+PFA_ICR5:
+ .dw 294
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter5 Interrupt Mask Register
+VE_TIMSK5:
+ .dw $ff06
+ .db "TIMSK5"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK5
+XT_TIMSK5:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK5:
+ .dw 115
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter5 Interrupt Flag register
+VE_TIFR5:
+ .dw $ff05
+ .db "TIFR5",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR5
+XT_TIFR5:
+ .dw PFA_DOVARIABLE
+PFA_TIFR5:
+ .dw 58
+
+.endif
+.if WANT_TIMER_COUNTER_4 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter4 Control Register A
+VE_TCCR4A:
+ .dw $ff06
+ .db "TCCR4A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR4A
+XT_TCCR4A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR4A:
+ .dw 160
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter4 Control Register B
+VE_TCCR4B:
+ .dw $ff06
+ .db "TCCR4B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR4B
+XT_TCCR4B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR4B:
+ .dw 161
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter 4 Control Register C
+VE_TCCR4C:
+ .dw $ff06
+ .db "TCCR4C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR4C
+XT_TCCR4C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR4C:
+ .dw 162
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter4 Bytes
+VE_TCNT4:
+ .dw $ff05
+ .db "TCNT4",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT4
+XT_TCNT4:
+ .dw PFA_DOVARIABLE
+PFA_TCNT4:
+ .dw 164
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter4 Output Compare Register A Bytes
+VE_OCR4A:
+ .dw $ff05
+ .db "OCR4A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR4A
+XT_OCR4A:
+ .dw PFA_DOVARIABLE
+PFA_OCR4A:
+ .dw 168
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter4 Output Compare Register B Bytes
+VE_OCR4B:
+ .dw $ff05
+ .db "OCR4B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR4B
+XT_OCR4B:
+ .dw PFA_DOVARIABLE
+PFA_OCR4B:
+ .dw 170
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter4 Output Compare Register B Bytes
+VE_OCR4C:
+ .dw $ff05
+ .db "OCR4C",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR4C
+XT_OCR4C:
+ .dw PFA_DOVARIABLE
+PFA_OCR4C:
+ .dw 172
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter4 Input Capture Register Bytes
+VE_ICR4:
+ .dw $ff04
+ .db "ICR4"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR4
+XT_ICR4:
+ .dw PFA_DOVARIABLE
+PFA_ICR4:
+ .dw 166
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter4 Interrupt Mask Register
+VE_TIMSK4:
+ .dw $ff06
+ .db "TIMSK4"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK4
+XT_TIMSK4:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK4:
+ .dw 114
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter4 Interrupt Flag register
+VE_TIFR4:
+ .dw $ff05
+ .db "TIFR4",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR4
+XT_TIFR4:
+ .dw PFA_DOVARIABLE
+PFA_TIFR4:
+ .dw 57
+
+.endif
+.if WANT_TIMER_COUNTER_3 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Control Register A
+VE_TCCR3A:
+ .dw $ff06
+ .db "TCCR3A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR3A
+XT_TCCR3A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR3A:
+ .dw 144
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Control Register B
+VE_TCCR3B:
+ .dw $ff06
+ .db "TCCR3B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR3B
+XT_TCCR3B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR3B:
+ .dw 145
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter 3 Control Register C
+VE_TCCR3C:
+ .dw $ff06
+ .db "TCCR3C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR3C
+XT_TCCR3C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR3C:
+ .dw 146
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Bytes
+VE_TCNT3:
+ .dw $ff05
+ .db "TCNT3",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT3
+XT_TCNT3:
+ .dw PFA_DOVARIABLE
+PFA_TCNT3:
+ .dw 148
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Output Compare Register A Bytes
+VE_OCR3A:
+ .dw $ff05
+ .db "OCR3A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR3A
+XT_OCR3A:
+ .dw PFA_DOVARIABLE
+PFA_OCR3A:
+ .dw 152
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Output Compare Register B Bytes
+VE_OCR3B:
+ .dw $ff05
+ .db "OCR3B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR3B
+XT_OCR3B:
+ .dw PFA_DOVARIABLE
+PFA_OCR3B:
+ .dw 154
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Output Compare Register B Bytes
+VE_OCR3C:
+ .dw $ff05
+ .db "OCR3C",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR3C
+XT_OCR3C:
+ .dw PFA_DOVARIABLE
+PFA_OCR3C:
+ .dw 156
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Input Capture Register Bytes
+VE_ICR3:
+ .dw $ff04
+ .db "ICR3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR3
+XT_ICR3:
+ .dw PFA_DOVARIABLE
+PFA_ICR3:
+ .dw 150
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Interrupt Mask Register
+VE_TIMSK3:
+ .dw $ff06
+ .db "TIMSK3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK3
+XT_TIMSK3:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK3:
+ .dw 113
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Interrupt Flag register
+VE_TIFR3:
+ .dw $ff05
+ .db "TIFR3",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR3
+XT_TIFR3:
+ .dw PFA_DOVARIABLE
+PFA_TIFR3:
+ .dw 56
+
+.endif
+.if WANT_TIMER_COUNTER_1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw 128
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw 129
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter 1 Control Register C
+VE_TCCR1C:
+ .dw $ff06
+ .db "TCCR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1C
+XT_TCCR1C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1C:
+ .dw 130
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Bytes
+VE_TCNT1:
+ .dw $ff05
+ .db "TCNT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1
+XT_TCNT1:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1:
+ .dw 132
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register A Bytes
+VE_OCR1A:
+ .dw $ff05
+ .db "OCR1A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1A
+XT_OCR1A:
+ .dw PFA_DOVARIABLE
+PFA_OCR1A:
+ .dw 136
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register B Bytes
+VE_OCR1B:
+ .dw $ff05
+ .db "OCR1B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1B
+XT_OCR1B:
+ .dw PFA_DOVARIABLE
+PFA_OCR1B:
+ .dw 138
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register C Bytes
+VE_OCR1C:
+ .dw $ff05
+ .db "OCR1C",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1C
+XT_OCR1C:
+ .dw PFA_DOVARIABLE
+PFA_OCR1C:
+ .dw 140
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Bytes
+VE_ICR1:
+ .dw $ff04
+ .db "ICR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1
+XT_ICR1:
+ .dw PFA_DOVARIABLE
+PFA_ICR1:
+ .dw 134
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Mask Register
+VE_TIMSK1:
+ .dw $ff06
+ .db "TIMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK1
+XT_TIMSK1:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK1:
+ .dw 111
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Flag register
+VE_TIFR1:
+ .dw $ff05
+ .db "TIFR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR1
+XT_TIFR1:
+ .dw PFA_DOVARIABLE
+PFA_TIFR1:
+ .dw 54
+
+.endif
+.if WANT_JTAG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; On-Chip Debug Related Register in I/O Memory
+VE_OCDR:
+ .dw $ff04
+ .db "OCDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCDR
+XT_OCDR:
+ .dw PFA_DOVARIABLE
+PFA_OCDR:
+ .dw 81
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw 85
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Status Register
+VE_MCUSR:
+ .dw $ff05
+ .db "MCUSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUSR
+XT_MCUSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUSR:
+ .dw 84
+
+.endif
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register A
+VE_EICRA:
+ .dw $ff05
+ .db "EICRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRA
+XT_EICRA:
+ .dw PFA_DOVARIABLE
+PFA_EICRA:
+ .dw 105
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register B
+VE_EICRB:
+ .dw $ff05
+ .db "EICRB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRB
+XT_EICRB:
+ .dw PFA_DOVARIABLE
+PFA_EICRB:
+ .dw 106
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Mask Register
+VE_EIMSK:
+ .dw $ff05
+ .db "EIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIMSK
+XT_EIMSK:
+ .dw PFA_DOVARIABLE
+PFA_EIMSK:
+ .dw 61
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Flag Register
+VE_EIFR:
+ .dw $ff04
+ .db "EIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIFR
+XT_EIFR:
+ .dw PFA_DOVARIABLE
+PFA_EIFR:
+ .dw 60
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 2
+VE_PCMSK2:
+ .dw $ff06
+ .db "PCMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK2
+XT_PCMSK2:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK2:
+ .dw 109
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 1
+VE_PCMSK1:
+ .dw $ff06
+ .db "PCMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK1
+XT_PCMSK1:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK1:
+ .dw 108
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 0
+VE_PCMSK0:
+ .dw $ff06
+ .db "PCMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK0
+XT_PCMSK0:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK0:
+ .dw 107
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Interrupt Flag Register
+VE_PCIFR:
+ .dw $ff05
+ .db "PCIFR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCIFR
+XT_PCIFR:
+ .dw PFA_DOVARIABLE
+PFA_PCIFR:
+ .dw 59
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Interrupt Control Register
+VE_PCICR:
+ .dw $ff05
+ .db "PCICR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCICR
+XT_PCICR:
+ .dw PFA_DOVARIABLE
+PFA_PCICR:
+ .dw 104
+
+.endif
+.if WANT_CPU == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw 95
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer
+VE_SP:
+ .dw $ff02
+ .db "SP"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SP
+XT_SP:
+ .dw PFA_DOVARIABLE
+PFA_SP:
+ .dw 93
+; ( -- addr ) System Constant
+; R( -- )
+; External Memory Control Register A
+VE_XMCRA:
+ .dw $ff05
+ .db "XMCRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_XMCRA
+XT_XMCRA:
+ .dw PFA_DOVARIABLE
+PFA_XMCRA:
+ .dw 116
+; ( -- addr ) System Constant
+; R( -- )
+; External Memory Control Register B
+VE_XMCRB:
+ .dw $ff05
+ .db "XMCRB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_XMCRB
+XT_XMCRB:
+ .dw PFA_DOVARIABLE
+PFA_XMCRB:
+ .dw 117
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Calibration Value
+VE_OSCCAL:
+ .dw $ff06
+ .db "OSCCAL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSCCAL
+XT_OSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_OSCCAL:
+ .dw 102
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_CLKPR:
+ .dw $ff05
+ .db "CLKPR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKPR
+XT_CLKPR:
+ .dw PFA_DOVARIABLE
+PFA_CLKPR:
+ .dw 97
+; ( -- addr ) System Constant
+; R( -- )
+; Sleep Mode Control Register
+VE_SMCR:
+ .dw $ff04
+ .db "SMCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SMCR
+XT_SMCR:
+ .dw PFA_DOVARIABLE
+PFA_SMCR:
+ .dw 83
+; ( -- addr ) System Constant
+; R( -- )
+; Extended Indirect Register
+VE_EIND:
+ .dw $ff04
+ .db "EIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIND
+XT_EIND:
+ .dw PFA_DOVARIABLE
+PFA_EIND:
+ .dw 92
+; ( -- addr ) System Constant
+; R( -- )
+; RAM Page Z Select Register
+VE_RAMPZ:
+ .dw $ff05
+ .db "RAMPZ",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_RAMPZ
+XT_RAMPZ:
+ .dw PFA_DOVARIABLE
+PFA_RAMPZ:
+ .dw 91
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 2
+VE_GPIOR2:
+ .dw $ff06
+ .db "GPIOR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR2
+XT_GPIOR2:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR2:
+ .dw 75
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 1
+VE_GPIOR1:
+ .dw $ff06
+ .db "GPIOR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR1
+XT_GPIOR1:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR1:
+ .dw 74
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 0
+VE_GPIOR0:
+ .dw $ff06
+ .db "GPIOR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR0
+XT_GPIOR0:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR0:
+ .dw 62
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register1
+VE_PRR1:
+ .dw $ff04
+ .db "PRR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR1
+XT_PRR1:
+ .dw PFA_DOVARIABLE
+PFA_PRR1:
+ .dw 101
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register0
+VE_PRR0:
+ .dw $ff04
+ .db "PRR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR0
+XT_PRR0:
+ .dw PFA_DOVARIABLE
+PFA_PRR0:
+ .dw 100
+
+.endif
+.if WANT_AD_CONVERTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC multiplexer Selection Register
+VE_ADMUX:
+ .dw $ff05
+ .db "ADMUX",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADMUX
+XT_ADMUX:
+ .dw PFA_DOVARIABLE
+PFA_ADMUX:
+ .dw 124
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register Bytes
+VE_ADC:
+ .dw $ff03
+ .db "ADC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADC
+XT_ADC:
+ .dw PFA_DOVARIABLE
+PFA_ADC:
+ .dw 120
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register A
+VE_ADCSRA:
+ .dw $ff06
+ .db "ADCSRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRA
+XT_ADCSRA:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRA:
+ .dw 122
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register
+VE_DIDR2:
+ .dw $ff05
+ .db "DIDR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR2
+XT_DIDR2:
+ .dw PFA_DOVARIABLE
+PFA_DIDR2:
+ .dw 125
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register
+VE_DIDR0:
+ .dw $ff05
+ .db "DIDR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR0
+XT_DIDR0:
+ .dw PFA_DOVARIABLE
+PFA_DIDR0:
+ .dw 126
+
+.endif
+.if WANT_BOOT_LOAD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control Register
+VE_SPMCSR:
+ .dw $ff06
+ .db "SPMCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCSR
+XT_SPMCSR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCSR:
+ .dw 87
+
+.endif
diff --git a/amforth-6.5/avr8/devices/atmega2561/device.py b/amforth-6.5/avr8/devices/atmega2561/device.py
new file mode 100644
index 0000000..90120d0
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega2561/device.py
@@ -0,0 +1,557 @@
+# Generated Automatically
+
+# Partname ATmega2561
+
+MCUREGS = {
+# Interrupt Vectors
+ 'INT0Addr' : '#2', # External Interrupt Request 0
+ 'INT1Addr' : '#4', # External Interrupt Request 1
+ 'INT2Addr' : '#6', # External Interrupt Request 2
+ 'INT3Addr' : '#8', # External Interrupt Request 3
+ 'INT4Addr' : '#10', # External Interrupt Request 4
+ 'INT5Addr' : '#12', # External Interrupt Request 5
+ 'INT6Addr' : '#14', # External Interrupt Request 6
+ 'INT7Addr' : '#16', # External Interrupt Request 7
+ 'PCINT0Addr' : '#18', # Pin Change Interrupt Request 0
+ 'PCINT1Addr' : '#20', # Pin Change Interrupt Request 1
+ 'PCINT2Addr' : '#22', # Pin Change Interrupt Request 2
+ 'WDTAddr' : '#24', # Watchdog Time-out Interrupt
+ 'TIMER2_COMPAAddr' : '#26', # Timer/Counter2 Compare Match A
+ 'TIMER2_COMPBAddr' : '#28', # Timer/Counter2 Compare Match B
+ 'TIMER2_OVFAddr' : '#30', # Timer/Counter2 Overflow
+ 'TIMER1_CAPTAddr' : '#32', # Timer/Counter1 Capture Event
+ 'TIMER1_COMPAAddr' : '#34', # Timer/Counter1 Compare Match A
+ 'TIMER1_COMPBAddr' : '#36', # Timer/Counter1 Compare Match B
+ 'TIMER1_COMPCAddr' : '#38', # Timer/Counter1 Compare Match C
+ 'TIMER1_OVFAddr' : '#40', # Timer/Counter1 Overflow
+ 'TIMER0_COMPAAddr' : '#42', # Timer/Counter0 Compare Match A
+ 'TIMER0_COMPBAddr' : '#44', # Timer/Counter0 Compare Match B
+ 'TIMER0_OVFAddr' : '#46', # Timer/Counter0 Overflow
+ 'SPI_STCAddr' : '#48', # SPI Serial Transfer Complete
+ 'USART0_RXAddr' : '#50', # USART0, Rx Complete
+ 'USART0_UDREAddr' : '#52', # USART0 Data register Empty
+ 'USART0_TXAddr' : '#54', # USART0, Tx Complete
+ 'ANALOG_COMPAddr' : '#56', # Analog Comparator
+ 'ADCAddr' : '#58', # ADC Conversion Complete
+ 'EE_READYAddr' : '#60', # EEPROM Ready
+ 'TIMER3_CAPTAddr' : '#62', # Timer/Counter3 Capture Event
+ 'TIMER3_COMPAAddr' : '#64', # Timer/Counter3 Compare Match A
+ 'TIMER3_COMPBAddr' : '#66', # Timer/Counter3 Compare Match B
+ 'TIMER3_COMPCAddr' : '#68', # Timer/Counter3 Compare Match C
+ 'TIMER3_OVFAddr' : '#70', # Timer/Counter3 Overflow
+ 'USART1_RXAddr' : '#72', # USART1, Rx Complete
+ 'USART1_UDREAddr' : '#74', # USART1 Data register Empty
+ 'USART1_TXAddr' : '#76', # USART1, Tx Complete
+ 'TWIAddr' : '#78', # 2-wire Serial Interface
+ 'SPM_READYAddr' : '#80', # Store Program Memory Read
+ 'TIMER4_CAPTAddr' : '#82', # Timer/Counter4 Capture Event
+ 'TIMER4_COMPAAddr' : '#84', # Timer/Counter4 Compare Match A
+ 'TIMER4_COMPBAddr' : '#86', # Timer/Counter4 Compare Match B
+ 'TIMER4_COMPCAddr' : '#88', # Timer/Counter4 Compare Match C
+ 'TIMER4_OVFAddr' : '#90', # Timer/Counter4 Overflow
+ 'TIMER5_CAPTAddr' : '#92', # Timer/Counter5 Capture Event
+ 'TIMER5_COMPAAddr' : '#94', # Timer/Counter5 Compare Match A
+ 'TIMER5_COMPBAddr' : '#96', # Timer/Counter5 Compare Match B
+ 'TIMER5_COMPCAddr' : '#98', # Timer/Counter5 Compare Match C
+ 'TIMER5_OVFAddr' : '#100', # Timer/Counter5 Overflow
+ 'USART2_RXAddr' : '#102', # USART2, Rx Complete
+ 'USART2_UDREAddr' : '#104', # USART2 Data register Empty
+ 'USART2_TXAddr' : '#106', # USART2, Tx Complete
+ 'USART3_RXAddr' : '#108', # USART3, Rx Complete
+ 'USART3_UDREAddr' : '#110', # USART3 Data register Empty
+ 'USART3_TXAddr' : '#112', # USART3, Tx Complete
+
+# Module ANALOG_COMPARATOR
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
+ 'ACSR' : '$50', # Analog Comparator Control And
+ 'ACSR_ACD': '$80', # Analog Comparator Disable
+ 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
+ 'ACSR_ACO': '$20', # Analog Compare Output
+ 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
+ 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
+ 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
+ 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
+ 'DIDR1' : '$7f', # Digital Input Disable Register
+ 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
+ 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
+
+# Module USART0
+ 'UDR0' : '$c6', # USART I/O Data Register
+ 'UCSR0A' : '$c0', # USART Control and Status Regis
+ 'UCSR0A_RXC0': '$80', # USART Receive Complete
+ 'UCSR0A_TXC0': '$40', # USART Transmitt Complete
+ 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
+ 'UCSR0A_FE0': '$10', # Framing Error
+ 'UCSR0A_DOR0': '$8', # Data overRun
+ 'UCSR0A_UPE0': '$4', # Parity Error
+ 'UCSR0A_U2X0': '$2', # Double the USART transmission
+ 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
+ 'UCSR0B' : '$c1', # USART Control and Status Regis
+ 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
+ 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
+ 'UCSR0B_UDRIE0': '$20', # USART Data register Empty Inte
+ 'UCSR0B_RXEN0': '$10', # Receiver Enable
+ 'UCSR0B_TXEN0': '$8', # Transmitter Enable
+ 'UCSR0B_UCSZ02': '$4', # Character Size
+ 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
+ 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
+ 'UCSR0C' : '$c2', # USART Control and Status Regis
+ 'UCSR0C_UMSEL0': '$c0', # USART Mode Select
+ 'UCSR0C_UPM0': '$30', # Parity Mode Bits
+ 'UCSR0C_USBS0': '$8', # Stop Bit Select
+ 'UCSR0C_UCSZ0': '$6', # Character Size
+ 'UCSR0C_UCPOL0': '$1', # Clock Polarity
+ 'UBRR0' : '$c4', # USART Baud Rate Register Byte
+
+# Module TWI
+ 'TWAMR' : '$bd', # TWI (Slave) Address Mask Regis
+ 'TWAMR_TWAM': '$fe', #
+ 'TWBR' : '$b8', # TWI Bit Rate register
+ 'TWCR' : '$bc', # TWI Control Register
+ 'TWCR_TWINT': '$80', # TWI Interrupt Flag
+ 'TWCR_TWEA': '$40', # TWI Enable Acknowledge Bit
+ 'TWCR_TWSTA': '$20', # TWI Start Condition Bit
+ 'TWCR_TWSTO': '$10', # TWI Stop Condition Bit
+ 'TWCR_TWWC': '$8', # TWI Write Collition Flag
+ 'TWCR_TWEN': '$4', # TWI Enable Bit
+ 'TWCR_TWIE': '$1', # TWI Interrupt Enable
+ 'TWSR' : '$b9', # TWI Status Register
+ 'TWSR_TWS': '$f8', # TWI Status
+ 'TWSR_TWPS': '$3', # TWI Prescaler
+ 'TWDR' : '$bb', # TWI Data register
+ 'TWAR' : '$ba', # TWI (Slave) Address register
+ 'TWAR_TWA': '$fe', # TWI (Slave) Address register B
+ 'TWAR_TWGCE': '$1', # TWI General Call Recognition E
+
+# Module SPI
+ 'SPCR' : '$4c', # SPI Control Register
+ 'SPCR_SPIE': '$80', # SPI Interrupt Enable
+ 'SPCR_SPE': '$40', # SPI Enable
+ 'SPCR_DORD': '$20', # Data Order
+ 'SPCR_MSTR': '$10', # Master/Slave Select
+ 'SPCR_CPOL': '$8', # Clock polarity
+ 'SPCR_CPHA': '$4', # Clock Phase
+ 'SPCR_SPR': '$3', # SPI Clock Rate Selects
+ 'SPSR' : '$4d', # SPI Status Register
+ 'SPSR_SPIF': '$80', # SPI Interrupt Flag
+ 'SPSR_WCOL': '$40', # Write Collision Flag
+ 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
+ 'SPDR' : '$4e', # SPI Data Register
+
+# Module PORTA
+ 'PORTA' : '$22', # Port A Data Register
+ 'DDRA' : '$21', # Port A Data Direction Register
+ 'PINA' : '$20', # Port A Input Pins
+
+# Module PORTB
+ 'PORTB' : '$25', # Port B Data Register
+ 'DDRB' : '$24', # Port B Data Direction Register
+ 'PINB' : '$23', # Port B Input Pins
+
+# Module PORTC
+ 'PORTC' : '$28', # Port C Data Register
+ 'DDRC' : '$27', # Port C Data Direction Register
+ 'PINC' : '$26', # Port C Input Pins
+
+# Module PORTD
+ 'PORTD' : '$2b', # Port D Data Register
+ 'DDRD' : '$2a', # Port D Data Direction Register
+ 'PIND' : '$29', # Port D Input Pins
+
+# Module PORTE
+ 'PORTE' : '$2e', # Data Register, Port E
+ 'DDRE' : '$2d', # Data Direction Register, Port
+ 'PINE' : '$2c', # Input Pins, Port E
+
+# Module PORTF
+ 'PORTF' : '$31', # Data Register, Port F
+ 'DDRF' : '$30', # Data Direction Register, Port
+ 'PINF' : '$2f', # Input Pins, Port F
+
+# Module PORTG
+ 'PORTG' : '$34', # Data Register, Port G
+ 'DDRG' : '$33', # Data Direction Register, Port
+ 'PING' : '$32', # Input Pins, Port G
+
+# Module TIMER_COUNTER_0
+ 'OCR0B' : '$48', # Timer/Counter0 Output Compare
+ 'OCR0A' : '$47', # Timer/Counter0 Output Compare
+ 'TCNT0' : '$46', # Timer/Counter0
+ 'TCCR0B' : '$45', # Timer/Counter Control Register
+ 'TCCR0B_FOC0A': '$80', # Force Output Compare A
+ 'TCCR0B_FOC0B': '$40', # Force Output Compare B
+ 'TCCR0B_WGM02': '$8', #
+ 'TCCR0B_CS0': '$7', # Clock Select
+ 'TCCR0A' : '$44', # Timer/Counter Control Registe
+ 'TCCR0A_COM0A': '$c0', # Compare Output Mode, Phase Cor
+ 'TCCR0A_COM0B': '$30', # Compare Output Mode, Fast PWm
+ 'TCCR0A_WGM0': '$3', # Waveform Generation Mode
+ 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
+ 'TIMSK0_OCIE0B': '$4', # Timer/Counter0 Output Compare
+ 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
+ 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
+ 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
+ 'TIFR0_OCF0B': '$4', # Timer/Counter0 Output Compare
+ 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
+ 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSRSYNC': '$1', # Prescaler Reset Timer/Counter1
+
+# Module TIMER_COUNTER_2
+ 'TIMSK2' : '$70', # Timer/Counter Interrupt Mask r
+ 'TIMSK2_OCIE2B': '$4', # Timer/Counter2 Output Compare
+ 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
+ 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
+ 'TIFR2' : '$37', # Timer/Counter Interrupt Flag R
+ 'TIFR2_OCF2B': '$4', # Output Compare Flag 2B
+ 'TIFR2_OCF2A': '$2', # Output Compare Flag 2A
+ 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
+ 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
+ 'TCCR2A_COM2A': '$c0', # Compare Output Mode bits
+ 'TCCR2A_COM2B': '$30', # Compare Output Mode bits
+ 'TCCR2A_WGM2': '$3', # Waveform Genration Mode
+ 'TCCR2B' : '$b1', # Timer/Counter2 Control Registe
+ 'TCCR2B_FOC2A': '$80', # Force Output Compare A
+ 'TCCR2B_FOC2B': '$40', # Force Output Compare B
+ 'TCCR2B_WGM22': '$8', # Waveform Generation Mode
+ 'TCCR2B_CS2': '$7', # Clock Select bits
+ 'TCNT2' : '$b2', # Timer/Counter2
+ 'OCR2B' : '$b4', # Timer/Counter2 Output Compare
+ 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
+ 'ASSR' : '$b6', # Asynchronous Status Register
+ 'ASSR_EXCLK': '$40', # Enable External Clock Input
+ 'ASSR_AS2': '$20', # Asynchronous Timer/Counter2
+ 'ASSR_TCN2UB': '$10', # Timer/Counter2 Update Busy
+ 'ASSR_OCR2AUB': '$8', # Output Compare Register2 Updat
+ 'ASSR_OCR2BUB': '$4', # Output Compare Register 2 Upda
+ 'ASSR_TCR2AUB': '$2', # Timer/Counter Control Register
+ 'ASSR_TCR2BUB': '$1', # Timer/Counter Control Register
+ 'GTCCR' : '$43', # General Timer Counter Control
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSRASY': '$2', # Prescaler Reset Timer/Counter2
+
+# Module WATCHDOG
+ 'WDTCSR' : '$60', # Watchdog Timer Control Registe
+ 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
+ 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
+ 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
+ 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
+ 'WDTCSR_WDE': '$8', # Watch Dog Enable
+
+# Module USART1
+ 'UDR1' : '$ce', # USART I/O Data Register
+ 'UCSR1A' : '$c8', # USART Control and Status Regis
+ 'UCSR1A_RXC1': '$80', # USART Receive Complete
+ 'UCSR1A_TXC1': '$40', # USART Transmitt Complete
+ 'UCSR1A_UDRE1': '$20', # USART Data Register Empty
+ 'UCSR1A_FE1': '$10', # Framing Error
+ 'UCSR1A_DOR1': '$8', # Data overRun
+ 'UCSR1A_UPE1': '$4', # Parity Error
+ 'UCSR1A_U2X1': '$2', # Double the USART transmission
+ 'UCSR1A_MPCM1': '$1', # Multi-processor Communication
+ 'UCSR1B' : '$c9', # USART Control and Status Regis
+ 'UCSR1B_RXCIE1': '$80', # RX Complete Interrupt Enable
+ 'UCSR1B_TXCIE1': '$40', # TX Complete Interrupt Enable
+ 'UCSR1B_UDRIE1': '$20', # USART Data register Empty Inte
+ 'UCSR1B_RXEN1': '$10', # Receiver Enable
+ 'UCSR1B_TXEN1': '$8', # Transmitter Enable
+ 'UCSR1B_UCSZ12': '$4', # Character Size
+ 'UCSR1B_RXB81': '$2', # Receive Data Bit 8
+ 'UCSR1B_TXB81': '$1', # Transmit Data Bit 8
+ 'UCSR1C' : '$ca', # USART Control and Status Regis
+ 'UCSR1C_UMSEL1': '$c0', # USART Mode Select
+ 'UCSR1C_UPM1': '$30', # Parity Mode Bits
+ 'UCSR1C_USBS1': '$8', # Stop Bit Select
+ 'UCSR1C_UCSZ1': '$6', # Character Size
+ 'UCSR1C_UCPOL1': '$1', # Clock Polarity
+ 'UBRR1' : '$cc', # USART Baud Rate Register Byte
+
+# Module EEPROM
+ 'EEAR' : '$41', # EEPROM Address Register Low By
+ 'EEDR' : '$40', # EEPROM Data Register
+ 'EECR' : '$3f', # EEPROM Control Register
+ 'EECR_EEPM': '$30', # EEPROM Programming Mode Bits
+ 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
+ 'EECR_EEMPE': '$4', # EEPROM Master Write Enable
+ 'EECR_EEPE': '$2', # EEPROM Write Enable
+ 'EECR_EERE': '$1', # EEPROM Read Enable
+
+# Module TIMER_COUNTER_5
+ 'TCCR5A' : '$120', # Timer/Counter5 Control Registe
+ 'TCCR5A_COM5A': '$c0', # Compare Output Mode 1A, bits
+ 'TCCR5A_COM5B': '$30', # Compare Output Mode 5B, bits
+ 'TCCR5A_COM5C': '$c', # Compare Output Mode 5C, bits
+ 'TCCR5A_WGM5': '$3', # Waveform Generation Mode
+ 'TCCR5B' : '$121', # Timer/Counter5 Control Registe
+ 'TCCR5B_ICNC5': '$80', # Input Capture 5 Noise Canceler
+ 'TCCR5B_ICES5': '$40', # Input Capture 5 Edge Select
+ 'TCCR5B_WGM5': '$18', # Waveform Generation Mode
+ 'TCCR5B_CS5': '$7', # Prescaler source of Timer/Coun
+ 'TCCR5C' : '$122', # Timer/Counter 5 Control Regist
+ 'TCCR5C_FOC5A': '$80', # Force Output Compare 5A
+ 'TCCR5C_FOC5B': '$40', # Force Output Compare 5B
+ 'TCCR5C_FOC5C': '$20', # Force Output Compare 5C
+ 'TCNT5' : '$124', # Timer/Counter5 Bytes
+ 'OCR5A' : '$128', # Timer/Counter5 Output Compare
+ 'OCR5B' : '$12a', # Timer/Counter5 Output Compare
+ 'OCR5C' : '$12c', # Timer/Counter5 Output Compare
+ 'ICR5' : '$126', # Timer/Counter5 Input Capture R
+ 'TIMSK5' : '$73', # Timer/Counter5 Interrupt Mask
+ 'TIMSK5_ICIE5': '$20', # Timer/Counter5 Input Capture I
+ 'TIMSK5_OCIE5C': '$8', # Timer/Counter5 Output Compare
+ 'TIMSK5_OCIE5B': '$4', # Timer/Counter5 Output Compare
+ 'TIMSK5_OCIE5A': '$2', # Timer/Counter5 Output Compare
+ 'TIMSK5_TOIE5': '$1', # Timer/Counter5 Overflow Interr
+ 'TIFR5' : '$3a', # Timer/Counter5 Interrupt Flag
+ 'TIFR5_ICF5': '$20', # Input Capture Flag 5
+ 'TIFR5_OCF5C': '$8', # Output Compare Flag 5C
+ 'TIFR5_OCF5B': '$4', # Output Compare Flag 5B
+ 'TIFR5_OCF5A': '$2', # Output Compare Flag 5A
+ 'TIFR5_TOV5': '$1', # Timer/Counter5 Overflow Flag
+
+# Module TIMER_COUNTER_4
+ 'TCCR4A' : '$a0', # Timer/Counter4 Control Registe
+ 'TCCR4A_COM4A': '$c0', # Compare Output Mode 1A, bits
+ 'TCCR4A_COM4B': '$30', # Compare Output Mode 4B, bits
+ 'TCCR4A_COM4C': '$c', # Compare Output Mode 4C, bits
+ 'TCCR4A_WGM4': '$3', # Waveform Generation Mode
+ 'TCCR4B' : '$a1', # Timer/Counter4 Control Registe
+ 'TCCR4B_ICNC4': '$80', # Input Capture 4 Noise Canceler
+ 'TCCR4B_ICES4': '$40', # Input Capture 4 Edge Select
+ 'TCCR4B_WGM4': '$18', # Waveform Generation Mode
+ 'TCCR4B_CS4': '$7', # Prescaler source of Timer/Coun
+ 'TCCR4C' : '$a2', # Timer/Counter 4 Control Regist
+ 'TCCR4C_FOC4A': '$80', # Force Output Compare 4A
+ 'TCCR4C_FOC4B': '$40', # Force Output Compare 4B
+ 'TCCR4C_FOC4C': '$20', # Force Output Compare 4C
+ 'TCNT4' : '$a4', # Timer/Counter4 Bytes
+ 'OCR4A' : '$a8', # Timer/Counter4 Output Compare
+ 'OCR4B' : '$aa', # Timer/Counter4 Output Compare
+ 'OCR4C' : '$ac', # Timer/Counter4 Output Compare
+ 'ICR4' : '$a6', # Timer/Counter4 Input Capture R
+ 'TIMSK4' : '$72', # Timer/Counter4 Interrupt Mask
+ 'TIMSK4_ICIE4': '$20', # Timer/Counter4 Input Capture I
+ 'TIMSK4_OCIE4C': '$8', # Timer/Counter4 Output Compare
+ 'TIMSK4_OCIE4B': '$4', # Timer/Counter4 Output Compare
+ 'TIMSK4_OCIE4A': '$2', # Timer/Counter4 Output Compare
+ 'TIMSK4_TOIE4': '$1', # Timer/Counter4 Overflow Interr
+ 'TIFR4' : '$39', # Timer/Counter4 Interrupt Flag
+ 'TIFR4_ICF4': '$20', # Input Capture Flag 4
+ 'TIFR4_OCF4C': '$8', # Output Compare Flag 4C
+ 'TIFR4_OCF4B': '$4', # Output Compare Flag 4B
+ 'TIFR4_OCF4A': '$2', # Output Compare Flag 4A
+ 'TIFR4_TOV4': '$1', # Timer/Counter4 Overflow Flag
+
+# Module TIMER_COUNTER_3
+ 'TCCR3A' : '$90', # Timer/Counter3 Control Registe
+ 'TCCR3A_COM3A': '$c0', # Compare Output Mode 1A, bits
+ 'TCCR3A_COM3B': '$30', # Compare Output Mode 3B, bits
+ 'TCCR3A_COM3C': '$c', # Compare Output Mode 3C, bits
+ 'TCCR3A_WGM3': '$3', # Waveform Generation Mode
+ 'TCCR3B' : '$91', # Timer/Counter3 Control Registe
+ 'TCCR3B_ICNC3': '$80', # Input Capture 3 Noise Canceler
+ 'TCCR3B_ICES3': '$40', # Input Capture 3 Edge Select
+ 'TCCR3B_WGM3': '$18', # Waveform Generation Mode
+ 'TCCR3B_CS3': '$7', # Prescaler source of Timer/Coun
+ 'TCCR3C' : '$92', # Timer/Counter 3 Control Regist
+ 'TCCR3C_FOC3A': '$80', # Force Output Compare 3A
+ 'TCCR3C_FOC3B': '$40', # Force Output Compare 3B
+ 'TCCR3C_FOC3C': '$20', # Force Output Compare 3C
+ 'TCNT3' : '$94', # Timer/Counter3 Bytes
+ 'OCR3A' : '$98', # Timer/Counter3 Output Compare
+ 'OCR3B' : '$9a', # Timer/Counter3 Output Compare
+ 'OCR3C' : '$9c', # Timer/Counter3 Output Compare
+ 'ICR3' : '$96', # Timer/Counter3 Input Capture R
+ 'TIMSK3' : '$71', # Timer/Counter3 Interrupt Mask
+ 'TIMSK3_ICIE3': '$20', # Timer/Counter3 Input Capture I
+ 'TIMSK3_OCIE3C': '$8', # Timer/Counter3 Output Compare
+ 'TIMSK3_OCIE3B': '$4', # Timer/Counter3 Output Compare
+ 'TIMSK3_OCIE3A': '$2', # Timer/Counter3 Output Compare
+ 'TIMSK3_TOIE3': '$1', # Timer/Counter3 Overflow Interr
+ 'TIFR3' : '$38', # Timer/Counter3 Interrupt Flag
+ 'TIFR3_ICF3': '$20', # Input Capture Flag 3
+ 'TIFR3_OCF3C': '$8', # Output Compare Flag 3C
+ 'TIFR3_OCF3B': '$4', # Output Compare Flag 3B
+ 'TIFR3_OCF3A': '$2', # Output Compare Flag 3A
+ 'TIFR3_TOV3': '$1', # Timer/Counter3 Overflow Flag
+
+# Module TIMER_COUNTER_1
+ 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
+ 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
+ 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
+ 'TCCR1A_COM1C': '$c', # Compare Output Mode 1C, bits
+ 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
+ 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
+ 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
+ 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
+ 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
+ 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
+ 'TCCR1C' : '$82', # Timer/Counter 1 Control Regist
+ 'TCCR1C_FOC1A': '$80', # Force Output Compare 1A
+ 'TCCR1C_FOC1B': '$40', # Force Output Compare 1B
+ 'TCCR1C_FOC1C': '$20', # Force Output Compare 1C
+ 'TCNT1' : '$84', # Timer/Counter1 Bytes
+ 'OCR1A' : '$88', # Timer/Counter1 Output Compare
+ 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
+ 'OCR1C' : '$8c', # Timer/Counter1 Output Compare
+ 'ICR1' : '$86', # Timer/Counter1 Input Capture R
+ 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
+ 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
+ 'TIMSK1_OCIE1C': '$8', # Timer/Counter1 Output Compare
+ 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
+ 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
+ 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
+ 'TIFR1' : '$36', # Timer/Counter1 Interrupt Flag
+ 'TIFR1_ICF1': '$20', # Input Capture Flag 1
+ 'TIFR1_OCF1C': '$8', # Output Compare Flag 1C
+ 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
+ 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
+ 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
+
+# Module JTAG
+ 'OCDR' : '$51', # On-Chip Debug Related Register
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_JTD': '$80', # JTAG Interface Disable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+
+# Module EXTERNAL_INTERRUPT
+ 'EICRA' : '$69', # External Interrupt Control Reg
+ 'EICRA_ISC3': '$c0', # External Interrupt Sense Contr
+ 'EICRA_ISC2': '$30', # External Interrupt Sense Contr
+ 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
+ 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
+ 'EICRB' : '$6a', # External Interrupt Control Reg
+ 'EICRB_ISC7': '$c0', # External Interrupt 7-4 Sense C
+ 'EICRB_ISC6': '$30', # External Interrupt 7-4 Sense C
+ 'EICRB_ISC5': '$c', # External Interrupt 7-4 Sense C
+ 'EICRB_ISC4': '$3', # External Interrupt 7-4 Sense C
+ 'EIMSK' : '$3d', # External Interrupt Mask Regist
+ 'EIMSK_INT': '$ff', # External Interrupt Request 7 E
+ 'EIFR' : '$3c', # External Interrupt Flag Regist
+ 'EIFR_INTF': '$ff', # External Interrupt Flags
+ 'PCMSK2' : '$6d', # Pin Change Mask Register 2
+ 'PCMSK1' : '$6c', # Pin Change Mask Register 1
+ 'PCMSK0' : '$6b', # Pin Change Mask Register 0
+ 'PCIFR' : '$3b', # Pin Change Interrupt Flag Regi
+ 'PCIFR_PCIF': '$7', # Pin Change Interrupt Flags
+ 'PCICR' : '$68', # Pin Change Interrupt Control R
+ 'PCICR_PCIE': '$7', # Pin Change Interrupt Enables
+
+# Module CPU
+ 'SREG' : '$5f', # Status Register
+ 'SREG_I': '$80', # Global Interrupt Enable
+ 'SREG_T': '$40', # Bit Copy Storage
+ 'SREG_H': '$20', # Half Carry Flag
+ 'SREG_S': '$10', # Sign Bit
+ 'SREG_V': '$8', # Two's Complement Overflow Flag
+ 'SREG_N': '$4', # Negative Flag
+ 'SREG_Z': '$2', # Zero Flag
+ 'SREG_C': '$1', # Carry Flag
+ 'SP' : '$5d', # Stack Pointer
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_JTD': '$80', # JTAG Interface Disable
+ 'MCUCR_PUD': '$10', # Pull-up disable
+ 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
+ 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+ 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
+ 'MCUSR_BORF': '$4', # Brown-out Reset Flag
+ 'MCUSR_EXTRF': '$2', # External Reset Flag
+ 'MCUSR_PORF': '$1', # Power-on reset flag
+ 'XMCRA' : '$74', # External Memory Control Regist
+ 'XMCRA_SRE': '$80', # External SRAM Enable
+ 'XMCRA_SRL': '$70', # Wait state page limit
+ 'XMCRA_SRW1': '$c', # Wait state select bit upper pa
+ 'XMCRA_SRW0': '$3', # Wait state select bit lower pa
+ 'XMCRB' : '$75', # External Memory Control Regist
+ 'XMCRB_XMBK': '$80', # External Memory Bus Keeper Ena
+ 'XMCRB_XMM': '$7', # External Memory High Mask
+ 'OSCCAL' : '$66', # Oscillator Calibration Value
+ 'CLKPR' : '$61', #
+ 'CLKPR_CLKPCE': '$80', #
+ 'CLKPR_CLKPS': '$f', #
+ 'SMCR' : '$53', # Sleep Mode Control Register
+ 'SMCR_SM': '$e', # Sleep Mode Select bits
+ 'SMCR_SE': '$1', # Sleep Enable
+ 'EIND' : '$5c', # Extended Indirect Register
+ 'RAMPZ' : '$5b', # RAM Page Z Select Register
+ 'GPIOR2' : '$4b', # General Purpose IO Register 2
+ 'GPIOR2_GPIOR': '$ff', # General Purpose IO Register 2
+ 'GPIOR1' : '$4a', # General Purpose IO Register 1
+ 'GPIOR1_GPIOR': '$ff', # General Purpose IO Register 1
+ 'GPIOR0' : '$3e', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR07': '$80', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR06': '$40', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR05': '$20', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR04': '$10', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR03': '$8', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR02': '$4', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR01': '$2', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR00': '$1', # General Purpose IO Register 0
+ 'PRR1' : '$65', # Power Reduction Register1
+ 'PRR1_PRTIM5': '$20', # Power Reduction Timer/Counter5
+ 'PRR1_PRTIM4': '$10', # Power Reduction Timer/Counter4
+ 'PRR1_PRTIM3': '$8', # Power Reduction Timer/Counter3
+ 'PRR1_PRUSART': '$7', # Power Reduction USART3
+ 'PRR0' : '$64', # Power Reduction Register0
+ 'PRR0_PRTWI': '$80', # Power Reduction TWI
+ 'PRR0_PRTIM2': '$40', # Power Reduction Timer/Counter2
+ 'PRR0_PRTIM0': '$20', # Power Reduction Timer/Counter0
+ 'PRR0_PRTIM1': '$8', # Power Reduction Timer/Counter1
+ 'PRR0_PRSPI': '$4', # Power Reduction Serial Periphe
+ 'PRR0_PRUSART0': '$2', # Power Reduction USART
+ 'PRR0_PRADC': '$1', # Power Reduction ADC
+
+# Module AD_CONVERTER
+ 'ADMUX' : '$7c', # The ADC multiplexer Selection
+ 'ADMUX_REFS': '$c0', # Reference Selection Bits
+ 'ADMUX_ADLAR': '$20', # Left Adjust Result
+ 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
+ 'ADC' : '$78', # ADC Data Register Bytes
+ 'ADCSRA' : '$7a', # The ADC Control and Status reg
+ 'ADCSRA_ADEN': '$80', # ADC Enable
+ 'ADCSRA_ADSC': '$40', # ADC Start Conversion
+ 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
+ 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
+ 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
+ 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
+ 'ADCSRB' : '$7b', # The ADC Control and Status reg
+ 'ADCSRB_ACME': '$40', #
+ 'ADCSRB_MUX5': '$8', # Analog Channel and Gain Select
+ 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Source bits
+ 'DIDR2' : '$7d', # Digital Input Disable Register
+ 'DIDR2_ADC15D': '$80', #
+ 'DIDR2_ADC14D': '$40', #
+ 'DIDR2_ADC13D': '$20', #
+ 'DIDR2_ADC12D': '$10', #
+ 'DIDR2_ADC11D': '$8', #
+ 'DIDR2_ADC10D': '$4', #
+ 'DIDR2_ADC9D': '$2', #
+ 'DIDR2_ADC8D': '$1', #
+ 'DIDR0' : '$7e', # Digital Input Disable Register
+ 'DIDR0_ADC7D': '$80', #
+ 'DIDR0_ADC6D': '$40', #
+ 'DIDR0_ADC5D': '$20', #
+ 'DIDR0_ADC4D': '$10', #
+ 'DIDR0_ADC3D': '$8', #
+ 'DIDR0_ADC2D': '$4', #
+ 'DIDR0_ADC1D': '$2', #
+ 'DIDR0_ADC0D': '$1', #
+
+# Module BOOT_LOAD
+ 'SPMCSR' : '$57', # Store Program Memory Control R
+ 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
+ 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
+ 'SPMCSR_SIGRD': '$20', # Signature Row Read
+ 'SPMCSR_RWWSRE': '$10', # Read While Write section read
+ 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
+ 'SPMCSR_PGWRT': '$4', # Page Write
+ 'SPMCSR_PGERS': '$2', # Page Erase
+ 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
+
+ '__amforth_dummy':'0'
+}
diff --git a/amforth-6.5/avr8/devices/atmega2561/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega2561/words/no-jtag.asm
new file mode 100644
index 0000000..352a4bb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega2561/words/no-jtag.asm
@@ -0,0 +1,14 @@
+; ( -- )
+; ( -- )
+; MCU
+; disable jtag at runtime
+VE_NOJTAG:
+ .dw $FF05
+ .db "-jtag",0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOJTAG
+XT_NOJTAG:
+ .dw PFA_NOJTAG
+PFA_NOJTAG:
+
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega2561/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega2561/words/no-wdt.asm
new file mode 100644
index 0000000..ff6ddd1
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega2561/words/no-wdt.asm
@@ -0,0 +1,34 @@
+; ( -- )
+; MCU
+; disable watch dog timer at runtime
+VE_NOWDT:
+ .dw $ff04
+ .db "-wdt"
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOWDT
+XT_NOWDT:
+ .dw PFA_NOWDT
+PFA_NOWDT:
+
+ in temp1,SREG
+ push temp1
+ ; Turn always off global interrupt.
+ cli
+ ; Reset Watchdog Timer
+ wdr
+ ; Clear WDRF in MCUSR
+ in temp1, MCUSR
+ andi temp1, (0xff & (0<<WDRF))
+ out MCUSR, temp1
+ ; Write logical one to WDCE and WDE
+ ; Keep old prescaler setting to prevent unintentional time-out
+ in_ temp1, WDTCSR
+ ori temp1, (1<<WDCE) | (1<<WDE)
+ out_ WDTCSR, temp1
+ ; Turn off WDT
+ ldi temp1, (0<<WDE)
+ out_ WDTCSR, temp1
+ ; restore status register
+ pop temp1
+ out SREG,temp1
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega2561/words/sleep.asm b/amforth-6.5/avr8/devices/atmega2561/words/sleep.asm
new file mode 100644
index 0000000..256249c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega2561/words/sleep.asm
@@ -0,0 +1,19 @@
+; ( mode -- )
+; MCU
+; put the controller into the specified sleep mode
+VE_SLEEP:
+ .dw $ff05
+ .db "sleep", 0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_SLEEP
+XT_SLEEP:
+ .dw PFA_SLEEP
+PFA_SLEEP:
+ andi tosl, 7 ; leave only legal mode bits
+ lsl tosl ; move to correct location (bits 3-1)
+ ori tosl, 1 ; set the SE bit
+ out_ SMCR, tosl ; set the sleep config
+ sleep ; nighty-night
+ out_ SMCR, zerol ; 0 protects against accidental sleeps
+ loadtos ; pop argument from stack
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/AD_CONVERTER.frt b/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/AD_CONVERTER.frt
new file mode 100644
index 0000000..a283d42
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/AD_CONVERTER.frt
@@ -0,0 +1,79 @@
+\ Generated automatically for atmega2564rfr2
+\ #require bitnames.frt
+
+\ AD_CONVERTER
+$7c constant ADMUX \ The ADC Multiplexer Selection
+ $c0 constant ADMUX_REFS \ Reference Selection Bits
+ 7c $c0 bitmask: ADMUX.REFS \ Reference Selection Bits
+ $20 constant ADMUX_ADLAR \ ADC Left Adjust Result
+ 7c $20 bitmask: ADMUX.ADLAR \ ADC Left Adjust Result
+ $1f constant ADMUX_MUX \ Analog Channel and Gain Select
+ 7c $1f bitmask: ADMUX.MUX \ Analog Channel and Gain Select
+$78 constant ADC \ ADC Data Register Bytes
+$7a constant ADCSRA \ The ADC Control and Status Reg
+ $80 constant ADCSRA_ADEN \ ADC Enable
+ 7a $80 bitmask: ADCSRA.ADEN \ ADC Enable
+ $40 constant ADCSRA_ADSC \ ADC Start Conversion
+ 7a $40 bitmask: ADCSRA.ADSC \ ADC Start Conversion
+ $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
+ 7a $20 bitmask: ADCSRA.ADATE \ ADC Auto Trigger Enable
+ $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
+ 7a $10 bitmask: ADCSRA.ADIF \ ADC Interrupt Flag
+ $8 constant ADCSRA_ADIE \ ADC Interrupt Enable
+ 7a $8 bitmask: ADCSRA.ADIE \ ADC Interrupt Enable
+ $7 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
+ 7a $7 bitmask: ADCSRA.ADPS \ ADC Prescaler Select Bits
+$7b constant ADCSRB \ The ADC Control and Status Reg
+ $80 constant ADCSRB_AVDDOK \ AVDD Supply Voltage OK
+ 7b $80 bitmask: ADCSRB.AVDDOK \ AVDD Supply Voltage OK
+ $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer
+ 7b $40 bitmask: ADCSRB.ACME \ Analog Comparator Multiplexer
+ $20 constant ADCSRB_REFOK \ Reference Voltage OK
+ 7b $20 bitmask: ADCSRB.REFOK \ Reference Voltage OK
+ $10 constant ADCSRB_ACCH \ Analog Channel Change
+ 7b $10 bitmask: ADCSRB.ACCH \ Analog Channel Change
+ $8 constant ADCSRB_MUX5 \ Analog Channel and Gain Select
+ 7b $8 bitmask: ADCSRB.MUX5 \ Analog Channel and Gain Select
+ $7 constant ADCSRB_ADTS \ ADC Auto Trigger Source
+ 7b $7 bitmask: ADCSRB.ADTS \ ADC Auto Trigger Source
+$77 constant ADCSRC \ The ADC Control and Status Reg
+ $c0 constant ADCSRC_ADTHT \ ADC Track-and-Hold Time
+ 77 $c0 bitmask: ADCSRC.ADTHT \ ADC Track-and-Hold Time
+ $20 constant ADCSRC_Res0 \ Reserved
+ 77 $20 bitmask: ADCSRC.Res0 \ Reserved
+ $1f constant ADCSRC_ADSUT \ ADC Start-up Time
+ 77 $1f bitmask: ADCSRC.ADSUT \ ADC Start-up Time
+$7d constant DIDR2 \ Digital Input Disable Register
+ $80 constant DIDR2_ADC15D \ Reserved Bits
+ 7d $80 bitmask: DIDR2.ADC15D \ Reserved Bits
+ $40 constant DIDR2_ADC14D \ Reserved Bits
+ 7d $40 bitmask: DIDR2.ADC14D \ Reserved Bits
+ $20 constant DIDR2_ADC13D \ Reserved Bits
+ 7d $20 bitmask: DIDR2.ADC13D \ Reserved Bits
+ $10 constant DIDR2_ADC12D \ Reserved Bits
+ 7d $10 bitmask: DIDR2.ADC12D \ Reserved Bits
+ $8 constant DIDR2_ADC11D \ Reserved Bits
+ 7d $8 bitmask: DIDR2.ADC11D \ Reserved Bits
+ $4 constant DIDR2_ADC10D \ Reserved Bits
+ 7d $4 bitmask: DIDR2.ADC10D \ Reserved Bits
+ $2 constant DIDR2_ADC9D \ Reserved Bits
+ 7d $2 bitmask: DIDR2.ADC9D \ Reserved Bits
+ $1 constant DIDR2_ADC8D \ Reserved Bits
+ 7d $1 bitmask: DIDR2.ADC8D \ Reserved Bits
+$7e constant DIDR0 \ Digital Input Disable Register
+ $80 constant DIDR0_ADC7D \ Disable ADC7:0 Digital Input
+ 7e $80 bitmask: DIDR0.ADC7D \ Disable ADC7:0 Digital Input
+ $40 constant DIDR0_ADC6D \ Disable ADC7:0 Digital Input
+ 7e $40 bitmask: DIDR0.ADC6D \ Disable ADC7:0 Digital Input
+ $20 constant DIDR0_ADC5D \ Disable ADC7:0 Digital Input
+ 7e $20 bitmask: DIDR0.ADC5D \ Disable ADC7:0 Digital Input
+ $10 constant DIDR0_ADC4D \ Disable ADC7:0 Digital Input
+ 7e $10 bitmask: DIDR0.ADC4D \ Disable ADC7:0 Digital Input
+ $8 constant DIDR0_ADC3D \ Disable ADC7:0 Digital Input
+ 7e $8 bitmask: DIDR0.ADC3D \ Disable ADC7:0 Digital Input
+ $4 constant DIDR0_ADC2D \ Disable ADC7:0 Digital Input
+ 7e $4 bitmask: DIDR0.ADC2D \ Disable ADC7:0 Digital Input
+ $2 constant DIDR0_ADC1D \ Disable ADC7:0 Digital Input
+ 7e $2 bitmask: DIDR0.ADC1D \ Disable ADC7:0 Digital Input
+ $1 constant DIDR0_ADC0D \ Disable ADC7:0 Digital Input
+ 7e $1 bitmask: DIDR0.ADC0D \ Disable ADC7:0 Digital Input
diff --git a/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/ANALOG_COMPARATOR.frt b/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/ANALOG_COMPARATOR.frt
new file mode 100644
index 0000000..1c3e910
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/ANALOG_COMPARATOR.frt
@@ -0,0 +1,27 @@
+\ Generated automatically for atmega2564rfr2
+\ #require bitnames.frt
+
+\ ANALOG_COMPARATOR
+$7b constant ADCSRB \ ADC Control and Status Registe
+ $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer
+ 7b $40 bitmask: ADCSRB.ACME \ Analog Comparator Multiplexer
+$50 constant ACSR \ Analog Comparator Control And
+ $80 constant ACSR_ACD \ Analog Comparator Disable
+ 50 $80 bitmask: ACSR.ACD \ Analog Comparator Disable
+ $40 constant ACSR_ACBG \ Analog Comparator Bandgap Sele
+ 50 $40 bitmask: ACSR.ACBG \ Analog Comparator Bandgap Sele
+ $20 constant ACSR_ACO \ Analog Compare Output
+ 50 $20 bitmask: ACSR.ACO \ Analog Compare Output
+ $10 constant ACSR_ACI \ Analog Comparator Interrupt Fl
+ 50 $10 bitmask: ACSR.ACI \ Analog Comparator Interrupt Fl
+ $8 constant ACSR_ACIE \ Analog Comparator Interrupt En
+ 50 $8 bitmask: ACSR.ACIE \ Analog Comparator Interrupt En
+ $4 constant ACSR_ACIC \ Analog Comparator Input Captur
+ 50 $4 bitmask: ACSR.ACIC \ Analog Comparator Input Captur
+ $3 constant ACSR_ACIS \ Analog Comparator Interrupt Mo
+ 50 $3 bitmask: ACSR.ACIS \ Analog Comparator Interrupt Mo
+$7f constant DIDR1 \ Digital Input Disable Register
+ $2 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
+ 7f $2 bitmask: DIDR1.AIN1D \ AIN1 Digital Input Disable
+ $1 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
+ 7f $1 bitmask: DIDR1.AIN0D \ AIN0 Digital Input Disable
diff --git a/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/BOOT_LOAD.frt b/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/BOOT_LOAD.frt
new file mode 100644
index 0000000..fa74497
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/BOOT_LOAD.frt
@@ -0,0 +1,21 @@
+\ Generated automatically for atmega2564rfr2
+\ #require bitnames.frt
+
+\ BOOT_LOAD
+$57 constant SPMCSR \ Store Program Memory Control R
+ $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
+ 57 $80 bitmask: SPMCSR.SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
+ 57 $40 bitmask: SPMCSR.RWWSB \ Read While Write Section Busy
+ $20 constant SPMCSR_SIGRD \ Signature Row Read
+ 57 $20 bitmask: SPMCSR.SIGRD \ Signature Row Read
+ $10 constant SPMCSR_RWWSRE \ Read While Write Section Read
+ 57 $10 bitmask: SPMCSR.RWWSRE \ Read While Write Section Read
+ $8 constant SPMCSR_BLBSET \ Boot Lock Bit Set
+ 57 $8 bitmask: SPMCSR.BLBSET \ Boot Lock Bit Set
+ $4 constant SPMCSR_PGWRT \ Page Write
+ 57 $4 bitmask: SPMCSR.PGWRT \ Page Write
+ $2 constant SPMCSR_PGERS \ Page Erase
+ 57 $2 bitmask: SPMCSR.PGERS \ Page Erase
+ $1 constant SPMCSR_SPMEN \ Store Program Memory Enable
+ 57 $1 bitmask: SPMCSR.SPMEN \ Store Program Memory Enable
diff --git a/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/CPU.frt b/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/CPU.frt
new file mode 100644
index 0000000..ec40f10
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/CPU.frt
@@ -0,0 +1,129 @@
+\ Generated automatically for atmega2564rfr2
+\ #require bitnames.frt
+
+\ CPU
+$5f constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ 5f $80 bitmask: SREG.I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ 5f $40 bitmask: SREG.T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ 5f $20 bitmask: SREG.H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ 5f $10 bitmask: SREG.S \ Sign Bit
+ $8 constant SREG_V \ Two's Complement Overflow Flag
+ 5f $8 bitmask: SREG.V \ Two's Complement Overflow Flag
+ $4 constant SREG_N \ Negative Flag
+ 5f $4 bitmask: SREG.N \ Negative Flag
+ $2 constant SREG_Z \ Zero Flag
+ 5f $2 bitmask: SREG.Z \ Zero Flag
+ $1 constant SREG_C \ Carry Flag
+ 5f $1 bitmask: SREG.C \ Carry Flag
+$5d constant SP \ Stack Pointer
+$55 constant MCUCR \ MCU Control Register
+ $80 constant MCUCR_JTD \ JTAG Interface Disable
+ 55 $80 bitmask: MCUCR.JTD \ JTAG Interface Disable
+ $60 constant MCUCR_Res \ Reserved
+ 55 $60 bitmask: MCUCR.Res \ Reserved
+ $10 constant MCUCR_PUD \ Pull-up Disable
+ 55 $10 bitmask: MCUCR.PUD \ Pull-up Disable
+ $c constant MCUCR_Res \ Reserved
+ 55 $c bitmask: MCUCR.Res \ Reserved
+ $2 constant MCUCR_IVSEL \ Interrupt Vector Select
+ 55 $2 bitmask: MCUCR.IVSEL \ Interrupt Vector Select
+ $1 constant MCUCR_IVCE \ Interrupt Vector Change Enable
+ 55 $1 bitmask: MCUCR.IVCE \ Interrupt Vector Change Enable
+$54 constant MCUSR \ MCU Status Register
+ $e0 constant MCUSR_Res \ Reserved
+ 54 $e0 bitmask: MCUSR.Res \ Reserved
+ $10 constant MCUSR_JTRF \ JTAG Reset Flag
+ 54 $10 bitmask: MCUSR.JTRF \ JTAG Reset Flag
+ $8 constant MCUSR_WDRF \ Watchdog Reset Flag
+ 54 $8 bitmask: MCUSR.WDRF \ Watchdog Reset Flag
+ $4 constant MCUSR_BORF \ Brown-out Reset Flag
+ 54 $4 bitmask: MCUSR.BORF \ Brown-out Reset Flag
+ $2 constant MCUSR_EXTRF \ External Reset Flag
+ 54 $2 bitmask: MCUSR.EXTRF \ External Reset Flag
+ $1 constant MCUSR_PORF \ Power-on Reset Flag
+ 54 $1 bitmask: MCUSR.PORF \ Power-on Reset Flag
+$66 constant OSCCAL \ Oscillator Calibration Value
+ $ff constant OSCCAL_CAL \ Oscillator Calibration Tuning
+ 66 $ff bitmask: OSCCAL.CAL \ Oscillator Calibration Tuning
+$61 constant CLKPR \ Clock Prescale Register
+ $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable
+ 61 $80 bitmask: CLKPR.CLKPCE \ Clock Prescaler Change Enable
+ $70 constant CLKPR_Res \ Reserved
+ 61 $70 bitmask: CLKPR.Res \ Reserved
+ $f constant CLKPR_CLKPS \ Clock Prescaler Select Bits
+ 61 $f bitmask: CLKPR.CLKPS \ Clock Prescaler Select Bits
+$53 constant SMCR \ Sleep Mode Control Register
+ $f0 constant SMCR_Res \ Reserved
+ 53 $f0 bitmask: SMCR.Res \ Reserved
+ $e constant SMCR_SM \ Sleep Mode Select bits
+ 53 $e bitmask: SMCR.SM \ Sleep Mode Select bits
+ $1 constant SMCR_SE \ Sleep Enable
+ 53 $1 bitmask: SMCR.SE \ Sleep Enable
+$5c constant EIND \ Extended Indirect Register
+$5b constant RAMPZ \ Extended Z-pointer Register fo
+ $fc constant RAMPZ_Res \ Reserved
+ 5b $fc bitmask: RAMPZ.Res \ Reserved
+ $3 constant RAMPZ_RAMPZ \ Extended Z-Pointer Value
+ 5b $3 bitmask: RAMPZ.RAMPZ \ Extended Z-Pointer Value
+$4b constant GPIOR2 \ General Purpose I/O Register 2
+ $ff constant GPIOR2_GPIOR \ General Purpose I/O Register 2
+ 4b $ff bitmask: GPIOR2.GPIOR \ General Purpose I/O Register 2
+$4a constant GPIOR1 \ General Purpose IO Register 1
+ $ff constant GPIOR1_GPIOR \ General Purpose I/O Register 1
+ 4a $ff bitmask: GPIOR1.GPIOR \ General Purpose I/O Register 1
+$3e constant GPIOR0 \ General Purpose IO Register 0
+ $80 constant GPIOR0_GPIOR07 \ General Purpose I/O Register 0
+ 3e $80 bitmask: GPIOR0.GPIOR07 \ General Purpose I/O Register 0
+ $40 constant GPIOR0_GPIOR06 \ General Purpose I/O Register 0
+ 3e $40 bitmask: GPIOR0.GPIOR06 \ General Purpose I/O Register 0
+ $20 constant GPIOR0_GPIOR05 \ General Purpose I/O Register 0
+ 3e $20 bitmask: GPIOR0.GPIOR05 \ General Purpose I/O Register 0
+ $10 constant GPIOR0_GPIOR04 \ General Purpose I/O Register 0
+ 3e $10 bitmask: GPIOR0.GPIOR04 \ General Purpose I/O Register 0
+ $8 constant GPIOR0_GPIOR03 \ General Purpose I/O Register 0
+ 3e $8 bitmask: GPIOR0.GPIOR03 \ General Purpose I/O Register 0
+ $4 constant GPIOR0_GPIOR02 \ General Purpose I/O Register 0
+ 3e $4 bitmask: GPIOR0.GPIOR02 \ General Purpose I/O Register 0
+ $2 constant GPIOR0_GPIOR01 \ General Purpose I/O Register 0
+ 3e $2 bitmask: GPIOR0.GPIOR01 \ General Purpose I/O Register 0
+ $1 constant GPIOR0_GPIOR00 \ General Purpose I/O Register 0
+ 3e $1 bitmask: GPIOR0.GPIOR00 \ General Purpose I/O Register 0
+$63 constant PRR2 \ Power Reduction Register 2
+ $f0 constant PRR2_Res \ Reserved Bit
+ 63 $f0 bitmask: PRR2.Res \ Reserved Bit
+ $f constant PRR2_PRRAM \ Power Reduction SRAMs
+ 63 $f bitmask: PRR2.PRRAM \ Power Reduction SRAMs
+$65 constant PRR1 \ Power Reduction Register 1
+ $80 constant PRR1_Res \ Reserved Bit
+ 65 $80 bitmask: PRR1.Res \ Reserved Bit
+ $40 constant PRR1_PRTRX24 \ Power Reduction Transceiver
+ 65 $40 bitmask: PRR1.PRTRX24 \ Power Reduction Transceiver
+ $20 constant PRR1_PRTIM5 \ Power Reduction Timer/Counter5
+ 65 $20 bitmask: PRR1.PRTIM5 \ Power Reduction Timer/Counter5
+ $10 constant PRR1_PRTIM4 \ Power Reduction Timer/Counter4
+ 65 $10 bitmask: PRR1.PRTIM4 \ Power Reduction Timer/Counter4
+ $8 constant PRR1_PRTIM3 \ Power Reduction Timer/Counter3
+ 65 $8 bitmask: PRR1.PRTIM3 \ Power Reduction Timer/Counter3
+ $1 constant PRR1_PRUSART1 \ Power Reduction USART1
+ 65 $1 bitmask: PRR1.PRUSART1 \ Power Reduction USART1
+$64 constant PRR0 \ Power Reduction Register0
+ $80 constant PRR0_PRTWI \ Power Reduction TWI
+ 64 $80 bitmask: PRR0.PRTWI \ Power Reduction TWI
+ $40 constant PRR0_PRTIM2 \ Power Reduction Timer/Counter2
+ 64 $40 bitmask: PRR0.PRTIM2 \ Power Reduction Timer/Counter2
+ $20 constant PRR0_PRTIM0 \ Power Reduction Timer/Counter0
+ 64 $20 bitmask: PRR0.PRTIM0 \ Power Reduction Timer/Counter0
+ $10 constant PRR0_PRPGA \ Power Reduction PGA
+ 64 $10 bitmask: PRR0.PRPGA \ Power Reduction PGA
+ $8 constant PRR0_PRTIM1 \ Power Reduction Timer/Counter1
+ 64 $8 bitmask: PRR0.PRTIM1 \ Power Reduction Timer/Counter1
+ $4 constant PRR0_PRSPI \ Power Reduction Serial Periphe
+ 64 $4 bitmask: PRR0.PRSPI \ Power Reduction Serial Periphe
+ $2 constant PRR0_PRUSART0 \ Power Reduction USART
+ 64 $2 bitmask: PRR0.PRUSART0 \ Power Reduction USART
+ $1 constant PRR0_PRADC \ Power Reduction ADC
+ 64 $1 bitmask: PRR0.PRADC \ Power Reduction ADC
diff --git a/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/EEPROM.frt b/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/EEPROM.frt
new file mode 100644
index 0000000..ee9efc5
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/EEPROM.frt
@@ -0,0 +1,19 @@
+\ Generated automatically for atmega2564rfr2
+\ #require bitnames.frt
+
+\ EEPROM
+$41 constant EEAR \ EEPROM Address Register Bytes
+$40 constant EEDR \ EEPROM Data Register
+$3f constant EECR \ EEPROM Control Register
+ $c0 constant EECR_Res \ Reserved
+ 3f $c0 bitmask: EECR.Res \ Reserved
+ $30 constant EECR_EEPM \ EEPROM Programming Mode
+ 3f $30 bitmask: EECR.EEPM \ EEPROM Programming Mode
+ $8 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
+ 3f $8 bitmask: EECR.EERIE \ EEPROM Ready Interrupt Enable
+ $4 constant EECR_EEMPE \ EEPROM Master Write Enable
+ 3f $4 bitmask: EECR.EEMPE \ EEPROM Master Write Enable
+ $2 constant EECR_EEPE \ EEPROM Programming Enable
+ 3f $2 bitmask: EECR.EEPE \ EEPROM Programming Enable
+ $1 constant EECR_EERE \ EEPROM Read Enable
+ 3f $1 bitmask: EECR.EERE \ EEPROM Read Enable
diff --git a/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/EXTERNAL_INTERRUPT.frt b/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/EXTERNAL_INTERRUPT.frt
new file mode 100644
index 0000000..73eb050
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/EXTERNAL_INTERRUPT.frt
@@ -0,0 +1,45 @@
+\ Generated automatically for atmega2564rfr2
+\ #require bitnames.frt
+
+\ EXTERNAL_INTERRUPT
+$69 constant EICRA \ External Interrupt Control Reg
+ $c0 constant EICRA_ISC3 \ External Interrupt 3 Sense Con
+ 69 $c0 bitmask: EICRA.ISC3 \ External Interrupt 3 Sense Con
+ $30 constant EICRA_ISC2 \ External Interrupt 2 Sense Con
+ 69 $30 bitmask: EICRA.ISC2 \ External Interrupt 2 Sense Con
+ $c constant EICRA_ISC1 \ External Interrupt 1 Sense Con
+ 69 $c bitmask: EICRA.ISC1 \ External Interrupt 1 Sense Con
+ $3 constant EICRA_ISC0 \ External Interrupt 0 Sense Con
+ 69 $3 bitmask: EICRA.ISC0 \ External Interrupt 0 Sense Con
+$6a constant EICRB \ External Interrupt Control Reg
+ $c0 constant EICRB_ISC7 \ External Interrupt 7 Sense Con
+ 6a $c0 bitmask: EICRB.ISC7 \ External Interrupt 7 Sense Con
+ $30 constant EICRB_ISC6 \ External Interrupt 6 Sense Con
+ 6a $30 bitmask: EICRB.ISC6 \ External Interrupt 6 Sense Con
+ $c constant EICRB_ISC5 \ External Interrupt 5 Sense Con
+ 6a $c bitmask: EICRB.ISC5 \ External Interrupt 5 Sense Con
+ $3 constant EICRB_ISC4 \ External Interrupt 4 Sense Con
+ 6a $3 bitmask: EICRB.ISC4 \ External Interrupt 4 Sense Con
+$3d constant EIMSK \ External Interrupt Mask Regist
+ $ff constant EIMSK_INT \ External Interrupt Request Ena
+ 3d $ff bitmask: EIMSK.INT \ External Interrupt Request Ena
+$3c constant EIFR \ External Interrupt Flag Regist
+ $ff constant EIFR_INTF \ External Interrupt Flag
+ 3c $ff bitmask: EIFR.INTF \ External Interrupt Flag
+$6d constant PCMSK2 \ Pin Change Mask Register 2
+ $ff constant PCMSK2_PCINT \ Pin Change Enable Mask
+ 6d $ff bitmask: PCMSK2.PCINT \ Pin Change Enable Mask
+$6c constant PCMSK1 \ Pin Change Mask Register 1
+ $ff constant PCMSK1_PCINT \ Pin Change Enable Mask
+ 6c $ff bitmask: PCMSK1.PCINT \ Pin Change Enable Mask
+$6b constant PCMSK0 \ Pin Change Mask Register 0
+$3b constant PCIFR \ Pin Change Interrupt Flag Regi
+ $f8 constant PCIFR_Res \ Reserved Bit
+ 3b $f8 bitmask: PCIFR.Res \ Reserved Bit
+ $7 constant PCIFR_PCIF \ Pin Change Interrupt Flags
+ 3b $7 bitmask: PCIFR.PCIF \ Pin Change Interrupt Flags
+$68 constant PCICR \ Pin Change Interrupt Control R
+ $f8 constant PCICR_Res \ Reserved Bit
+ 68 $f8 bitmask: PCICR.Res \ Reserved Bit
+ $7 constant PCICR_PCIE \ Pin Change Interrupt Enables
+ 68 $7 bitmask: PCICR.PCIE \ Pin Change Interrupt Enables
diff --git a/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/FLASH.frt b/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/FLASH.frt
new file mode 100644
index 0000000..24391a0
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/FLASH.frt
@@ -0,0 +1,16 @@
+\ Generated automatically for atmega2564rfr2
+\ #require bitnames.frt
+
+\ FLASH
+$75 constant NEMCR \ Flash Extended-Mode Control-Re
+ $40 constant NEMCR_ENEAM \ Enable Extended Address Mode f
+ 75 $40 bitmask: NEMCR.ENEAM \ Enable Extended Address Mode f
+ $30 constant NEMCR_AEAM \ Address for Extended Address M
+ 75 $30 bitmask: NEMCR.AEAM \ Address for Extended Address M
+$67 constant BGCR \ Reference Voltage Calibration
+ $80 constant BGCR_Res \ Reserved Bit
+ 67 $80 bitmask: BGCR.Res \ Reserved Bit
+ $78 constant BGCR_BGCAL_FINE \ Fine Calibration Bits
+ 67 $78 bitmask: BGCR.BGCAL_FINE \ Fine Calibration Bits
+ $7 constant BGCR_BGCAL \ Coarse Calibration Bits
+ 67 $7 bitmask: BGCR.BGCAL \ Coarse Calibration Bits
diff --git a/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/JTAG.frt b/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/JTAG.frt
new file mode 100644
index 0000000..d84e93c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/JTAG.frt
@@ -0,0 +1,13 @@
+\ Generated automatically for atmega2564rfr2
+\ #require bitnames.frt
+
+\ JTAG
+$51 constant OCDR \ On-Chip Debug Register
+ $ff constant OCDR_OCDR \ On-Chip Debug Register Data
+ 51 $ff bitmask: OCDR.OCDR \ On-Chip Debug Register Data
+$55 constant MCUCR \ MCU Control Register
+ $80 constant MCUCR_JTD \ JTAG Interface Disable
+ 55 $80 bitmask: MCUCR.JTD \ JTAG Interface Disable
+$54 constant MCUSR \ MCU Status Register
+ $10 constant MCUSR_JTRF \ JTAG Reset Flag
+ 54 $10 bitmask: MCUSR.JTRF \ JTAG Reset Flag
diff --git a/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/PORTA.frt b/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/PORTA.frt
new file mode 100644
index 0000000..dcc6084
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/PORTA.frt
@@ -0,0 +1,7 @@
+\ Generated automatically for atmega2564rfr2
+\ #require bitnames.frt
+
+\ PORTA
+$22 constant PORTA \ Port A Data Register
+$21 constant DDRA \ Port A Data Direction Register
+$20 constant PINA \ Port A Input Pins Address
diff --git a/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/PORTB.frt b/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/PORTB.frt
new file mode 100644
index 0000000..c01cc3b
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/PORTB.frt
@@ -0,0 +1,7 @@
+\ Generated automatically for atmega2564rfr2
+\ #require bitnames.frt
+
+\ PORTB
+$25 constant PORTB \ Port B Data Register
+$24 constant DDRB \ Port B Data Direction Register
+$23 constant PINB \ Port B Input Pins Address
diff --git a/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/PORTC.frt b/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/PORTC.frt
new file mode 100644
index 0000000..0915669
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/PORTC.frt
@@ -0,0 +1,7 @@
+\ Generated automatically for atmega2564rfr2
+\ #require bitnames.frt
+
+\ PORTC
+$28 constant PORTC \ Port C Data Register
+$27 constant DDRC \ Port C Data Direction Register
+$26 constant PINC \ Port C Input Pins Address
diff --git a/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/PORTD.frt b/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/PORTD.frt
new file mode 100644
index 0000000..445c6b9
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/PORTD.frt
@@ -0,0 +1,7 @@
+\ Generated automatically for atmega2564rfr2
+\ #require bitnames.frt
+
+\ PORTD
+$2b constant PORTD \ Port D Data Register
+$2a constant DDRD \ Port D Data Direction Register
+$29 constant PIND \ Port D Input Pins Address
diff --git a/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/PORTE.frt b/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/PORTE.frt
new file mode 100644
index 0000000..d985ac0
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/PORTE.frt
@@ -0,0 +1,7 @@
+\ Generated automatically for atmega2564rfr2
+\ #require bitnames.frt
+
+\ PORTE
+$2e constant PORTE \ Port E Data Register
+$2d constant DDRE \ Port E Data Direction Register
+$2c constant PINE \ Port E Input Pins Address
diff --git a/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/PORTF.frt b/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/PORTF.frt
new file mode 100644
index 0000000..f0d7c26
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/PORTF.frt
@@ -0,0 +1,7 @@
+\ Generated automatically for atmega2564rfr2
+\ #require bitnames.frt
+
+\ PORTF
+$31 constant PORTF \ Port F Data Register
+$30 constant DDRF \ Port F Data Direction Register
+$2f constant PINF \ Port F Input Pins Address
diff --git a/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/PORTG.frt b/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/PORTG.frt
new file mode 100644
index 0000000..c90621c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/PORTG.frt
@@ -0,0 +1,7 @@
+\ Generated automatically for atmega2564rfr2
+\ #require bitnames.frt
+
+\ PORTG
+$34 constant PORTG \ Port G Data Register
+$33 constant DDRG \ Port G Data Direction Register
+$32 constant PING \ Port G Input Pins Address
diff --git a/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/PWRCTRL.frt b/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/PWRCTRL.frt
new file mode 100644
index 0000000..d1a7358
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/PWRCTRL.frt
@@ -0,0 +1,81 @@
+\ Generated automatically for atmega2564rfr2
+\ #require bitnames.frt
+
+\ PWRCTRL
+$139 constant TRXPR \ Transceiver Pin Register
+ $f0 constant TRXPR_Res \ Reserved
+ 139 $f0 bitmask: TRXPR.Res \ Reserved
+ $2 constant TRXPR_SLPTR \ Multi-purpose Transceiver Cont
+ 139 $2 bitmask: TRXPR.SLPTR \ Multi-purpose Transceiver Cont
+ $1 constant TRXPR_TRXRST \ Force Transceiver Reset
+ 139 $1 bitmask: TRXPR.TRXRST \ Force Transceiver Reset
+$135 constant DRTRAM0 \ Data Retention Configuration R
+ $c0 constant DRTRAM0_Res \ Reserved
+ 135 $c0 bitmask: DRTRAM0.Res \ Reserved
+ $20 constant DRTRAM0_DRTSWOK \ DRT Switch OK
+ 135 $20 bitmask: DRTRAM0.DRTSWOK \ DRT Switch OK
+ $10 constant DRTRAM0_ENDRT \ Enable SRAM Data Retention
+ 135 $10 bitmask: DRTRAM0.ENDRT \ Enable SRAM Data Retention
+$134 constant DRTRAM1 \ Data Retention Configuration R
+ $c0 constant DRTRAM1_Res \ Reserved
+ 134 $c0 bitmask: DRTRAM1.Res \ Reserved
+ $20 constant DRTRAM1_DRTSWOK \ DRT Switch OK
+ 134 $20 bitmask: DRTRAM1.DRTSWOK \ DRT Switch OK
+ $10 constant DRTRAM1_ENDRT \ Enable SRAM Data Retention
+ 134 $10 bitmask: DRTRAM1.ENDRT \ Enable SRAM Data Retention
+$133 constant DRTRAM2 \ Data Retention Configuration R
+ $40 constant DRTRAM2_Res \ Reserved Bit
+ 133 $40 bitmask: DRTRAM2.Res \ Reserved Bit
+ $20 constant DRTRAM2_DRTSWOK \ DRT Switch OK
+ 133 $20 bitmask: DRTRAM2.DRTSWOK \ DRT Switch OK
+ $10 constant DRTRAM2_ENDRT \ Enable SRAM Data Retention
+ 133 $10 bitmask: DRTRAM2.ENDRT \ Enable SRAM Data Retention
+$132 constant DRTRAM3 \ Data Retention Configuration R
+ $c0 constant DRTRAM3_Res \ Reserved
+ 132 $c0 bitmask: DRTRAM3.Res \ Reserved
+ $20 constant DRTRAM3_DRTSWOK \ DRT Switch OK
+ 132 $20 bitmask: DRTRAM3.DRTSWOK \ DRT Switch OK
+ $10 constant DRTRAM3_ENDRT \ Enable SRAM Data Retention
+ 132 $10 bitmask: DRTRAM3.ENDRT \ Enable SRAM Data Retention
+$130 constant LLDRL \ Low Leakage Voltage Regulator
+ $f0 constant LLDRL_Res \ Reserved
+ 130 $f0 bitmask: LLDRL.Res \ Reserved
+ $f constant LLDRL_LLDRL \ Low-Byte Data Register Bits
+ 130 $f bitmask: LLDRL.LLDRL \ Low-Byte Data Register Bits
+$131 constant LLDRH \ Low Leakage Voltage Regulator
+ $e0 constant LLDRH_Res \ Reserved
+ 131 $e0 bitmask: LLDRH.Res \ Reserved
+ $1f constant LLDRH_LLDRH \ High-Byte Data Register Bits
+ 131 $1f bitmask: LLDRH.LLDRH \ High-Byte Data Register Bits
+$12f constant LLCR \ Low Leakage Voltage Regulator
+ $c0 constant LLCR_Res \ Reserved Bit
+ 12f $c0 bitmask: LLCR.Res \ Reserved Bit
+ $20 constant LLCR_LLDONE \ Calibration Done
+ 12f $20 bitmask: LLCR.LLDONE \ Calibration Done
+ $10 constant LLCR_LLCOMP \ Comparator Output
+ 12f $10 bitmask: LLCR.LLCOMP \ Comparator Output
+ $8 constant LLCR_LLCAL \ Calibration Active
+ 12f $8 bitmask: LLCR.LLCAL \ Calibration Active
+ $4 constant LLCR_LLTCO \ Temperature Coefficient of Cur
+ 12f $4 bitmask: LLCR.LLTCO \ Temperature Coefficient of Cur
+ $2 constant LLCR_LLSHORT \ Short Lower Calibration Circui
+ 12f $2 bitmask: LLCR.LLSHORT \ Short Lower Calibration Circui
+ $1 constant LLCR_LLENCAL \ Enable Automatic Calibration
+ 12f $1 bitmask: LLCR.LLENCAL \ Enable Automatic Calibration
+$136 constant DPDS0 \ Port Driver Strength Register
+ $c0 constant DPDS0_PFDRV \ Driver Strength Port F
+ 136 $c0 bitmask: DPDS0.PFDRV \ Driver Strength Port F
+ $30 constant DPDS0_PEDRV \ Driver Strength Port E
+ 136 $30 bitmask: DPDS0.PEDRV \ Driver Strength Port E
+ $c constant DPDS0_PDDRV \ Driver Strength Port D
+ 136 $c bitmask: DPDS0.PDDRV \ Driver Strength Port D
+ $3 constant DPDS0_PBDRV \ Driver Strength Port B
+ 136 $3 bitmask: DPDS0.PBDRV \ Driver Strength Port B
+$137 constant DPDS1 \ Port Driver Strength Register
+ $fc constant DPDS1_Res \ Reserved
+ 137 $fc bitmask: DPDS1.Res \ Reserved
+ $3 constant DPDS1_PGDRV \ Driver Strength Port G
+ 137 $3 bitmask: DPDS1.PGDRV \ Driver Strength Port G
+$55 constant MCUCR \ MCU Control Register
+ $10 constant MCUCR_PUD \ Pull-up Disable
+ 55 $10 bitmask: MCUCR.PUD \ Pull-up Disable
diff --git a/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/SPI.frt b/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/SPI.frt
new file mode 100644
index 0000000..bc4823d
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/SPI.frt
@@ -0,0 +1,29 @@
+\ Generated automatically for atmega2564rfr2
+\ #require bitnames.frt
+
+\ SPI
+$4c constant SPCR \ SPI Control Register
+ $80 constant SPCR_SPIE \ SPI Interrupt Enable
+ 4c $80 bitmask: SPCR.SPIE \ SPI Interrupt Enable
+ $40 constant SPCR_SPE \ SPI Enable
+ 4c $40 bitmask: SPCR.SPE \ SPI Enable
+ $20 constant SPCR_DORD \ Data Order
+ 4c $20 bitmask: SPCR.DORD \ Data Order
+ $10 constant SPCR_MSTR \ Master/Slave Select
+ 4c $10 bitmask: SPCR.MSTR \ Master/Slave Select
+ $8 constant SPCR_CPOL \ Clock polarity
+ 4c $8 bitmask: SPCR.CPOL \ Clock polarity
+ $4 constant SPCR_CPHA \ Clock Phase
+ 4c $4 bitmask: SPCR.CPHA \ Clock Phase
+ $3 constant SPCR_SPR \ SPI Clock Rate Select 1 and 0
+ 4c $3 bitmask: SPCR.SPR \ SPI Clock Rate Select 1 and 0
+$4d constant SPSR \ SPI Status Register
+ $80 constant SPSR_SPIF \ SPI Interrupt Flag
+ 4d $80 bitmask: SPSR.SPIF \ SPI Interrupt Flag
+ $40 constant SPSR_WCOL \ Write Collision Flag
+ 4d $40 bitmask: SPSR.WCOL \ Write Collision Flag
+ $3e constant SPSR_Res \ Reserved
+ 4d $3e bitmask: SPSR.Res \ Reserved
+ $1 constant SPSR_SPI2X \ Double SPI Speed Bit
+ 4d $1 bitmask: SPSR.SPI2X \ Double SPI Speed Bit
+$4e constant SPDR \ SPI Data Register
diff --git a/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/SYMCNT.frt b/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/SYMCNT.frt
new file mode 100644
index 0000000..7d4663c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/SYMCNT.frt
@@ -0,0 +1,156 @@
+\ Generated automatically for atmega2564rfr2
+\ #require bitnames.frt
+
+\ SYMCNT
+$fc constant SCTSTRHH \ Symbol Counter Transmit Frame
+ $ff constant SCTSTRHH_SCTSTRHH \ Symbol Counter Transmit Frame
+ fc $ff bitmask: SCTSTRHH.SCTSTRHH \ Symbol Counter Transmit Frame
+$fb constant SCTSTRHL \ Symbol Counter Transmit Frame
+ $ff constant SCTSTRHL_SCTSTRHL \ Symbol Counter Transmit Frame
+ fb $ff bitmask: SCTSTRHL.SCTSTRHL \ Symbol Counter Transmit Frame
+$fa constant SCTSTRLH \ Symbol Counter Transmit Frame
+ $ff constant SCTSTRLH_SCTSTRLH \ Symbol Counter Transmit Frame
+ fa $ff bitmask: SCTSTRLH.SCTSTRLH \ Symbol Counter Transmit Frame
+$f9 constant SCTSTRLL \ Symbol Counter Transmit Frame
+ $ff constant SCTSTRLL_SCTSTRLL \ Symbol Counter Transmit Frame
+ f9 $ff bitmask: SCTSTRLL.SCTSTRLL \ Symbol Counter Transmit Frame
+$f8 constant SCOCR1HH \ Symbol Counter Output Compare
+ $ff constant SCOCR1HH_SCOCR1HH \ Symbol Counter Output Compare
+ f8 $ff bitmask: SCOCR1HH.SCOCR1HH \ Symbol Counter Output Compare
+$f7 constant SCOCR1HL \ Symbol Counter Output Compare
+ $ff constant SCOCR1HL_SCOCR1HL \ Symbol Counter Output Compare
+ f7 $ff bitmask: SCOCR1HL.SCOCR1HL \ Symbol Counter Output Compare
+$f6 constant SCOCR1LH \ Symbol Counter Output Compare
+ $ff constant SCOCR1LH_SCOCR1LH \ Symbol Counter Output Compare
+ f6 $ff bitmask: SCOCR1LH.SCOCR1LH \ Symbol Counter Output Compare
+$f5 constant SCOCR1LL \ Symbol Counter Output Compare
+ $ff constant SCOCR1LL_SCOCR1LL \ Symbol Counter Output Compare
+ f5 $ff bitmask: SCOCR1LL.SCOCR1LL \ Symbol Counter Output Compare
+$f4 constant SCOCR2HH \ Symbol Counter Output Compare
+ $ff constant SCOCR2HH_SCOCR2HH \ Symbol Counter Output Compare
+ f4 $ff bitmask: SCOCR2HH.SCOCR2HH \ Symbol Counter Output Compare
+$f3 constant SCOCR2HL \ Symbol Counter Output Compare
+ $ff constant SCOCR2HL_SCOCR2HL \ Symbol Counter Output Compare
+ f3 $ff bitmask: SCOCR2HL.SCOCR2HL \ Symbol Counter Output Compare
+$f2 constant SCOCR2LH \ Symbol Counter Output Compare
+ $ff constant SCOCR2LH_SCOCR2LH \ Symbol Counter Output Compare
+ f2 $ff bitmask: SCOCR2LH.SCOCR2LH \ Symbol Counter Output Compare
+$f1 constant SCOCR2LL \ Symbol Counter Output Compare
+ $ff constant SCOCR2LL_SCOCR2LL \ Symbol Counter Output Compare
+ f1 $ff bitmask: SCOCR2LL.SCOCR2LL \ Symbol Counter Output Compare
+$f0 constant SCOCR3HH \ Symbol Counter Output Compare
+ $ff constant SCOCR3HH_SCOCR3HH \ Symbol Counter Output Compare
+ f0 $ff bitmask: SCOCR3HH.SCOCR3HH \ Symbol Counter Output Compare
+$ef constant SCOCR3HL \ Symbol Counter Output Compare
+ $ff constant SCOCR3HL_SCOCR3HL \ Symbol Counter Output Compare
+ ef $ff bitmask: SCOCR3HL.SCOCR3HL \ Symbol Counter Output Compare
+$ee constant SCOCR3LH \ Symbol Counter Output Compare
+ $ff constant SCOCR3LH_SCOCR3LH \ Symbol Counter Output Compare
+ ee $ff bitmask: SCOCR3LH.SCOCR3LH \ Symbol Counter Output Compare
+$ed constant SCOCR3LL \ Symbol Counter Output Compare
+ $ff constant SCOCR3LL_SCOCR3LL \ Symbol Counter Output Compare
+ ed $ff bitmask: SCOCR3LL.SCOCR3LL \ Symbol Counter Output Compare
+$ec constant SCTSRHH \ Symbol Counter Frame Timestamp
+ $ff constant SCTSRHH_SCTSRHH \ Symbol Counter Frame Timestamp
+ ec $ff bitmask: SCTSRHH.SCTSRHH \ Symbol Counter Frame Timestamp
+$eb constant SCTSRHL \ Symbol Counter Frame Timestamp
+ $ff constant SCTSRHL_SCTSRHL \ Symbol Counter Frame Timestamp
+ eb $ff bitmask: SCTSRHL.SCTSRHL \ Symbol Counter Frame Timestamp
+$ea constant SCTSRLH \ Symbol Counter Frame Timestamp
+ $ff constant SCTSRLH_SCTSRLH \ Symbol Counter Frame Timestamp
+ ea $ff bitmask: SCTSRLH.SCTSRLH \ Symbol Counter Frame Timestamp
+$e9 constant SCTSRLL \ Symbol Counter Frame Timestamp
+ $ff constant SCTSRLL_SCTSRLL \ Symbol Counter Frame Timestamp
+ e9 $ff bitmask: SCTSRLL.SCTSRLL \ Symbol Counter Frame Timestamp
+$e8 constant SCBTSRHH \ Symbol Counter Beacon Timestam
+ $ff constant SCBTSRHH_SCBTSRHH \ Symbol Counter Beacon Timestam
+ e8 $ff bitmask: SCBTSRHH.SCBTSRHH \ Symbol Counter Beacon Timestam
+$e7 constant SCBTSRHL \ Symbol Counter Beacon Timestam
+ $ff constant SCBTSRHL_SCBTSRHL \ Symbol Counter Beacon Timestam
+ e7 $ff bitmask: SCBTSRHL.SCBTSRHL \ Symbol Counter Beacon Timestam
+$e6 constant SCBTSRLH \ Symbol Counter Beacon Timestam
+ $ff constant SCBTSRLH_SCBTSRLH \ Symbol Counter Beacon Timestam
+ e6 $ff bitmask: SCBTSRLH.SCBTSRLH \ Symbol Counter Beacon Timestam
+$e5 constant SCBTSRLL \ Symbol Counter Beacon Timestam
+ $ff constant SCBTSRLL_SCBTSRLL \ Symbol Counter Beacon Timestam
+ e5 $ff bitmask: SCBTSRLL.SCBTSRLL \ Symbol Counter Beacon Timestam
+$e4 constant SCCNTHH \ Symbol Counter Register HH-Byt
+ $ff constant SCCNTHH_SCCNTHH \ Symbol Counter Register HH-Byt
+ e4 $ff bitmask: SCCNTHH.SCCNTHH \ Symbol Counter Register HH-Byt
+$e3 constant SCCNTHL \ Symbol Counter Register HL-Byt
+ $ff constant SCCNTHL_SCCNTHL \ Symbol Counter Register HL-Byt
+ e3 $ff bitmask: SCCNTHL.SCCNTHL \ Symbol Counter Register HL-Byt
+$e2 constant SCCNTLH \ Symbol Counter Register LH-Byt
+ $ff constant SCCNTLH_SCCNTLH \ Symbol Counter Register LH-Byt
+ e2 $ff bitmask: SCCNTLH.SCCNTLH \ Symbol Counter Register LH-Byt
+$e1 constant SCCNTLL \ Symbol Counter Register LL-Byt
+ $ff constant SCCNTLL_SCCNTLL \ Symbol Counter Register LL-Byt
+ e1 $ff bitmask: SCCNTLL.SCCNTLL \ Symbol Counter Register LL-Byt
+$e0 constant SCIRQS \ Symbol Counter Interrupt Statu
+ $e0 constant SCIRQS_Res \ Reserved Bit
+ e0 $e0 bitmask: SCIRQS.Res \ Reserved Bit
+ $10 constant SCIRQS_IRQSBO \ Backoff Slot Counter IRQ
+ e0 $10 bitmask: SCIRQS.IRQSBO \ Backoff Slot Counter IRQ
+ $8 constant SCIRQS_IRQSOF \ Symbol Counter Overflow IRQ
+ e0 $8 bitmask: SCIRQS.IRQSOF \ Symbol Counter Overflow IRQ
+ $7 constant SCIRQS_IRQSCP \ Compare Unit 3 Compare Match I
+ e0 $7 bitmask: SCIRQS.IRQSCP \ Compare Unit 3 Compare Match I
+$df constant SCIRQM \ Symbol Counter Interrupt Mask
+ $e0 constant SCIRQM_Res \ Reserved Bit
+ df $e0 bitmask: SCIRQM.Res \ Reserved Bit
+ $10 constant SCIRQM_IRQMBO \ Backoff Slot Counter IRQ enabl
+ df $10 bitmask: SCIRQM.IRQMBO \ Backoff Slot Counter IRQ enabl
+ $8 constant SCIRQM_IRQMOF \ Symbol Counter Overflow IRQ en
+ df $8 bitmask: SCIRQM.IRQMOF \ Symbol Counter Overflow IRQ en
+ $7 constant SCIRQM_IRQMCP \ Symbol Counter Compare Match 3
+ df $7 bitmask: SCIRQM.IRQMCP \ Symbol Counter Compare Match 3
+$de constant SCSR \ Symbol Counter Status Register
+ $fe constant SCSR_Res \ Reserved Bit
+ de $fe bitmask: SCSR.Res \ Reserved Bit
+ $1 constant SCSR_SCBSY \ Symbol Counter busy
+ de $1 bitmask: SCSR.SCBSY \ Symbol Counter busy
+$dd constant SCCR1 \ Symbol Counter Control Registe
+ $c0 constant SCCR1_Res \ Reserved Bit
+ dd $c0 bitmask: SCCR1.Res \ Reserved Bit
+ $20 constant SCCR1_SCBTSM \ Symbol Counter Beacon Timestam
+ dd $20 bitmask: SCCR1.SCBTSM \ Symbol Counter Beacon Timestam
+ $1c constant SCCR1_SCCKDIV \ Clock divider for synchronous
+ dd $1c bitmask: SCCR1.SCCKDIV \ Clock divider for synchronous
+ $2 constant SCCR1_SCEECLK \ Enable External Clock Source o
+ dd $2 bitmask: SCCR1.SCEECLK \ Enable External Clock Source o
+ $1 constant SCCR1_SCENBO \ Backoff Slot Counter enable
+ dd $1 bitmask: SCCR1.SCENBO \ Backoff Slot Counter enable
+$dc constant SCCR0 \ Symbol Counter Control Registe
+ $80 constant SCCR0_SCRES \ Symbol Counter Synchronization
+ dc $80 bitmask: SCCR0.SCRES \ Symbol Counter Synchronization
+ $40 constant SCCR0_SCMBTS \ Manual Beacon Timestamp
+ dc $40 bitmask: SCCR0.SCMBTS \ Manual Beacon Timestamp
+ $20 constant SCCR0_SCEN \ Symbol Counter enable
+ dc $20 bitmask: SCCR0.SCEN \ Symbol Counter enable
+ $10 constant SCCR0_SCCKSEL \ Symbol Counter Clock Source se
+ dc $10 bitmask: SCCR0.SCCKSEL \ Symbol Counter Clock Source se
+ $8 constant SCCR0_SCTSE \ Symbol Counter Automatic Times
+ dc $8 bitmask: SCCR0.SCTSE \ Symbol Counter Automatic Times
+ $7 constant SCCR0_SCCMP \ Symbol Counter Compare Unit 3
+ dc $7 bitmask: SCCR0.SCCMP \ Symbol Counter Compare Unit 3
+$db constant SCCSR \ Symbol Counter Compare Source
+ $c0 constant SCCSR_Res \ Reserved Bit
+ db $c0 bitmask: SCCSR.Res \ Reserved Bit
+ $30 constant SCCSR_SCCS3 \ Symbol Counter Compare Source
+ db $30 bitmask: SCCSR.SCCS3 \ Symbol Counter Compare Source
+ $c constant SCCSR_SCCS2 \ Symbol Counter Compare Source
+ db $c bitmask: SCCSR.SCCS2 \ Symbol Counter Compare Source
+ $3 constant SCCSR_SCCS1 \ Symbol Counter Compare Source
+ db $3 bitmask: SCCSR.SCCS1 \ Symbol Counter Compare Source
+$da constant SCRSTRHH \ Symbol Counter Received Frame
+ $ff constant SCRSTRHH_SCRSTRHH \ Symbol Counter Received Frame
+ da $ff bitmask: SCRSTRHH.SCRSTRHH \ Symbol Counter Received Frame
+$d9 constant SCRSTRHL \ Symbol Counter Received Frame
+ $ff constant SCRSTRHL_SCRSTRHL \ Symbol Counter Received Frame
+ d9 $ff bitmask: SCRSTRHL.SCRSTRHL \ Symbol Counter Received Frame
+$d8 constant SCRSTRLH \ Symbol Counter Received Frame
+ $ff constant SCRSTRLH_SCRSTRLH \ Symbol Counter Received Frame
+ d8 $ff bitmask: SCRSTRLH.SCRSTRLH \ Symbol Counter Received Frame
+$d7 constant SCRSTRLL \ Symbol Counter Received Frame
+ $ff constant SCRSTRLL_SCRSTRLL \ Symbol Counter Received Frame
+ d7 $ff bitmask: SCRSTRLL.SCRSTRLL \ Symbol Counter Received Frame
diff --git a/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/TIMER_COUNTER_0.frt b/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/TIMER_COUNTER_0.frt
new file mode 100644
index 0000000..12e8b21
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/TIMER_COUNTER_0.frt
@@ -0,0 +1,54 @@
+\ Generated automatically for atmega2564rfr2
+\ #require bitnames.frt
+
+\ TIMER_COUNTER_0
+$48 constant OCR0B \ Timer/Counter0 Output Compare
+$47 constant OCR0A \ Timer/Counter0 Output Compare
+$46 constant TCNT0 \ Timer/Counter0 Register
+$45 constant TCCR0B \ Timer/Counter0 Control Registe
+ $80 constant TCCR0B_FOC0A \ Force Output Compare A
+ 45 $80 bitmask: TCCR0B.FOC0A \ Force Output Compare A
+ $40 constant TCCR0B_FOC0B \ Force Output Compare B
+ 45 $40 bitmask: TCCR0B.FOC0B \ Force Output Compare B
+ $30 constant TCCR0B_Res \ Reserved Bit
+ 45 $30 bitmask: TCCR0B.Res \ Reserved Bit
+ $8 constant TCCR0B_WGM02 \
+ 45 $8 bitmask: TCCR0B.WGM02 \
+ $7 constant TCCR0B_CS0 \ Clock Select
+ 45 $7 bitmask: TCCR0B.CS0 \ Clock Select
+$44 constant TCCR0A \ Timer/Counter0 Control Registe
+ $c0 constant TCCR0A_COM0A \ Compare Match Output A Mode
+ 44 $c0 bitmask: TCCR0A.COM0A \ Compare Match Output A Mode
+ $30 constant TCCR0A_COM0B \ Compare Match Output B Mode
+ 44 $30 bitmask: TCCR0A.COM0B \ Compare Match Output B Mode
+ $c constant TCCR0A_Res \ Reserved Bit
+ 44 $c bitmask: TCCR0A.Res \ Reserved Bit
+ $3 constant TCCR0A_WGM0 \ Waveform Generation Mode
+ 44 $3 bitmask: TCCR0A.WGM0 \ Waveform Generation Mode
+$6e constant TIMSK0 \ Timer/Counter0 Interrupt Mask
+ $f8 constant TIMSK0_Res \ Reserved
+ 6e $f8 bitmask: TIMSK0.Res \ Reserved
+ $4 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare
+ 6e $4 bitmask: TIMSK0.OCIE0B \ Timer/Counter0 Output Compare
+ $2 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare
+ 6e $2 bitmask: TIMSK0.OCIE0A \ Timer/Counter0 Output Compare
+ $1 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interr
+ 6e $1 bitmask: TIMSK0.TOIE0 \ Timer/Counter0 Overflow Interr
+$35 constant TIFR0 \ Timer/Counter0 Interrupt Flag
+ $f8 constant TIFR0_Res \ Reserved
+ 35 $f8 bitmask: TIFR0.Res \ Reserved
+ $4 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare
+ 35 $4 bitmask: TIFR0.OCF0B \ Timer/Counter0 Output Compare
+ $2 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare
+ 35 $2 bitmask: TIFR0.OCF0A \ Timer/Counter0 Output Compare
+ $1 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
+ 35 $1 bitmask: TIFR0.TOV0 \ Timer/Counter0 Overflow Flag
+$43 constant GTCCR \ General Timer/Counter Control
+ $80 constant GTCCR_TSM \ Timer/Counter Synchronization
+ 43 $80 bitmask: GTCCR.TSM \ Timer/Counter Synchronization
+ $7c constant GTCCR_Res \ Reserved
+ 43 $7c bitmask: GTCCR.Res \ Reserved
+ $2 constant GTCCR_PSRASY \ Prescaler Reset Timer/Counter2
+ 43 $2 bitmask: GTCCR.PSRASY \ Prescaler Reset Timer/Counter2
+ $1 constant GTCCR_PSRSYNC \ Prescaler Reset for Synchronou
+ 43 $1 bitmask: GTCCR.PSRSYNC \ Prescaler Reset for Synchronou
diff --git a/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/TIMER_COUNTER_1.frt b/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/TIMER_COUNTER_1.frt
new file mode 100644
index 0000000..34419fd
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/TIMER_COUNTER_1.frt
@@ -0,0 +1,68 @@
+\ Generated automatically for atmega2564rfr2
+\ #require bitnames.frt
+
+\ TIMER_COUNTER_1
+$80 constant TCCR1A \ Timer/Counter1 Control Registe
+ $c0 constant TCCR1A_COM1A \ Compare Output Mode for Channe
+ 80 $c0 bitmask: TCCR1A.COM1A \ Compare Output Mode for Channe
+ $30 constant TCCR1A_COM1B \ Compare Output Mode for Channe
+ 80 $30 bitmask: TCCR1A.COM1B \ Compare Output Mode for Channe
+ $c constant TCCR1A_COM1C \ Compare Output Mode for Channe
+ 80 $c bitmask: TCCR1A.COM1C \ Compare Output Mode for Channe
+ $3 constant TCCR1A_WGM1 \ Waveform Generation Mode
+ 80 $3 bitmask: TCCR1A.WGM1 \ Waveform Generation Mode
+$81 constant TCCR1B \ Timer/Counter1 Control Registe
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Cancelle
+ 81 $80 bitmask: TCCR1B.ICNC1 \ Input Capture 1 Noise Cancelle
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ 81 $40 bitmask: TCCR1B.ICES1 \ Input Capture 1 Edge Select
+ $20 constant TCCR1B_Res \ Reserved Bit
+ 81 $20 bitmask: TCCR1B.Res \ Reserved Bit
+ $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
+ 81 $18 bitmask: TCCR1B.WGM1 \ Waveform Generation Mode
+ $7 constant TCCR1B_CS1 \ Clock Select
+ 81 $7 bitmask: TCCR1B.CS1 \ Clock Select
+$82 constant TCCR1C \ Timer/Counter1 Control Registe
+ $80 constant TCCR1C_FOC1A \ Force Output Compare for Chann
+ 82 $80 bitmask: TCCR1C.FOC1A \ Force Output Compare for Chann
+ $40 constant TCCR1C_FOC1B \ Force Output Compare for Chann
+ 82 $40 bitmask: TCCR1C.FOC1B \ Force Output Compare for Chann
+ $20 constant TCCR1C_FOC1C \ Force Output Compare for Chann
+ 82 $20 bitmask: TCCR1C.FOC1C \ Force Output Compare for Chann
+ $1f constant TCCR1C_Res \ Reserved
+ 82 $1f bitmask: TCCR1C.Res \ Reserved
+$84 constant TCNT1 \ Timer/Counter1 Bytes
+$88 constant OCR1A \ Timer/Counter1 Output Compare
+$8a constant OCR1B \ Timer/Counter1 Output Compare
+$8c constant OCR1C \ Timer/Counter1 Output Compare
+$86 constant ICR1 \ Timer/Counter1 Input Capture R
+$6f constant TIMSK1 \ Timer/Counter1 Interrupt Mask
+ $c0 constant TIMSK1_Res \ Reserved Bit
+ 6f $c0 bitmask: TIMSK1.Res \ Reserved Bit
+ $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture I
+ 6f $20 bitmask: TIMSK1.ICIE1 \ Timer/Counter1 Input Capture I
+ $10 constant TIMSK1_Res \ Reserved Bit
+ 6f $10 bitmask: TIMSK1.Res \ Reserved Bit
+ $8 constant TIMSK1_OCIE1C \ Timer/Counter1 Output Compare
+ 6f $8 bitmask: TIMSK1.OCIE1C \ Timer/Counter1 Output Compare
+ $4 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare
+ 6f $4 bitmask: TIMSK1.OCIE1B \ Timer/Counter1 Output Compare
+ $2 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare
+ 6f $2 bitmask: TIMSK1.OCIE1A \ Timer/Counter1 Output Compare
+ $1 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interr
+ 6f $1 bitmask: TIMSK1.TOIE1 \ Timer/Counter1 Overflow Interr
+$36 constant TIFR1 \ Timer/Counter1 Interrupt Flag
+ $c0 constant TIFR1_Res \ Reserved Bit
+ 36 $c0 bitmask: TIFR1.Res \ Reserved Bit
+ $20 constant TIFR1_ICF1 \ Timer/Counter1 Input Capture F
+ 36 $20 bitmask: TIFR1.ICF1 \ Timer/Counter1 Input Capture F
+ $10 constant TIFR1_Res \ Reserved Bit
+ 36 $10 bitmask: TIFR1.Res \ Reserved Bit
+ $8 constant TIFR1_OCF1C \ Timer/Counter1 Output Compare
+ 36 $8 bitmask: TIFR1.OCF1C \ Timer/Counter1 Output Compare
+ $4 constant TIFR1_OCF1B \ Timer/Counter1 Output Compare
+ 36 $4 bitmask: TIFR1.OCF1B \ Timer/Counter1 Output Compare
+ $2 constant TIFR1_OCF1A \ Timer/Counter1 Output Compare
+ 36 $2 bitmask: TIFR1.OCF1A \ Timer/Counter1 Output Compare
+ $1 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
+ 36 $1 bitmask: TIFR1.TOV1 \ Timer/Counter1 Overflow Flag
diff --git a/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/TIMER_COUNTER_2.frt b/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/TIMER_COUNTER_2.frt
new file mode 100644
index 0000000..9ded205
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/TIMER_COUNTER_2.frt
@@ -0,0 +1,67 @@
+\ Generated automatically for atmega2564rfr2
+\ #require bitnames.frt
+
+\ TIMER_COUNTER_2
+$70 constant TIMSK2 \ Timer/Counter Interrupt Mask r
+ $f8 constant TIMSK2_Res \ Reserved Bit
+ 70 $f8 bitmask: TIMSK2.Res \ Reserved Bit
+ $4 constant TIMSK2_OCIE2B \ Timer/Counter2 Output Compare
+ 70 $4 bitmask: TIMSK2.OCIE2B \ Timer/Counter2 Output Compare
+ $2 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare
+ 70 $2 bitmask: TIMSK2.OCIE2A \ Timer/Counter2 Output Compare
+ $1 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interr
+ 70 $1 bitmask: TIMSK2.TOIE2 \ Timer/Counter2 Overflow Interr
+$37 constant TIFR2 \ Timer/Counter Interrupt Flag R
+ $f8 constant TIFR2_Res \ Reserved Bit
+ 37 $f8 bitmask: TIFR2.Res \ Reserved Bit
+ $4 constant TIFR2_OCF2B \ Output Compare Flag 2 B
+ 37 $4 bitmask: TIFR2.OCF2B \ Output Compare Flag 2 B
+ $2 constant TIFR2_OCF2A \ Output Compare Flag 2 A
+ 37 $2 bitmask: TIFR2.OCF2A \ Output Compare Flag 2 A
+ $1 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
+ 37 $1 bitmask: TIFR2.TOV2 \ Timer/Counter2 Overflow Flag
+$b0 constant TCCR2A \ Timer/Counter2 Control Registe
+ $c0 constant TCCR2A_COM2A \ Compare Match Output A Mode
+ b0 $c0 bitmask: TCCR2A.COM2A \ Compare Match Output A Mode
+ $30 constant TCCR2A_COM2B \ Compare Match Output B Mode
+ b0 $30 bitmask: TCCR2A.COM2B \ Compare Match Output B Mode
+ $c constant TCCR2A_Res \ Reserved
+ b0 $c bitmask: TCCR2A.Res \ Reserved
+ $3 constant TCCR2A_WGM2 \ Waveform Generation Mode
+ b0 $3 bitmask: TCCR2A.WGM2 \ Waveform Generation Mode
+$b1 constant TCCR2B \ Timer/Counter2 Control Registe
+ $80 constant TCCR2B_FOC2A \ Force Output Compare A
+ b1 $80 bitmask: TCCR2B.FOC2A \ Force Output Compare A
+ $40 constant TCCR2B_FOC2B \ Force Output Compare B
+ b1 $40 bitmask: TCCR2B.FOC2B \ Force Output Compare B
+ $30 constant TCCR2B_Res \ Reserved
+ b1 $30 bitmask: TCCR2B.Res \ Reserved
+ $8 constant TCCR2B_WGM22 \ Waveform Generation Mode
+ b1 $8 bitmask: TCCR2B.WGM22 \ Waveform Generation Mode
+ $7 constant TCCR2B_CS2 \ Clock Select
+ b1 $7 bitmask: TCCR2B.CS2 \ Clock Select
+$b2 constant TCNT2 \ Timer/Counter2
+$b4 constant OCR2B \ Timer/Counter2 Output Compare
+$b3 constant OCR2A \ Timer/Counter2 Output Compare
+$b6 constant ASSR \ Asynchronous Status Register
+ $80 constant ASSR_EXCLKAMR \ Enable External Clock Input fo
+ b6 $80 bitmask: ASSR.EXCLKAMR \ Enable External Clock Input fo
+ $40 constant ASSR_EXCLK \ Enable External Clock Input
+ b6 $40 bitmask: ASSR.EXCLK \ Enable External Clock Input
+ $20 constant ASSR_AS2 \ Timer/Counter2 Asynchronous Mo
+ b6 $20 bitmask: ASSR.AS2 \ Timer/Counter2 Asynchronous Mo
+ $10 constant ASSR_TCN2UB \ Timer/Counter2 Update Busy
+ b6 $10 bitmask: ASSR.TCN2UB \ Timer/Counter2 Update Busy
+ $8 constant ASSR_OCR2AUB \ Timer/Counter2 Output Compare
+ b6 $8 bitmask: ASSR.OCR2AUB \ Timer/Counter2 Output Compare
+ $4 constant ASSR_OCR2BUB \ Timer/Counter2 Output Compare
+ b6 $4 bitmask: ASSR.OCR2BUB \ Timer/Counter2 Output Compare
+ $2 constant ASSR_TCR2AUB \ Timer/Counter2 Control Registe
+ b6 $2 bitmask: ASSR.TCR2AUB \ Timer/Counter2 Control Registe
+ $1 constant ASSR_TCR2BUB \ Timer/Counter2 Control Registe
+ b6 $1 bitmask: ASSR.TCR2BUB \ Timer/Counter2 Control Registe
+$43 constant GTCCR \ General Timer Counter Control
+ $80 constant GTCCR_TSM \ Timer/Counter Synchronization
+ 43 $80 bitmask: GTCCR.TSM \ Timer/Counter Synchronization
+ $2 constant GTCCR_PSRASY \ Prescaler Reset Timer/Counter2
+ 43 $2 bitmask: GTCCR.PSRASY \ Prescaler Reset Timer/Counter2
diff --git a/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/TIMER_COUNTER_3.frt b/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/TIMER_COUNTER_3.frt
new file mode 100644
index 0000000..9a97103
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/TIMER_COUNTER_3.frt
@@ -0,0 +1,68 @@
+\ Generated automatically for atmega2564rfr2
+\ #require bitnames.frt
+
+\ TIMER_COUNTER_3
+$90 constant TCCR3A \ Timer/Counter3 Control Registe
+ $c0 constant TCCR3A_COM3A \ Compare Output Mode for Channe
+ 90 $c0 bitmask: TCCR3A.COM3A \ Compare Output Mode for Channe
+ $30 constant TCCR3A_COM3B \ Compare Output Mode for Channe
+ 90 $30 bitmask: TCCR3A.COM3B \ Compare Output Mode for Channe
+ $c constant TCCR3A_COM3C \ Compare Output Mode for Channe
+ 90 $c bitmask: TCCR3A.COM3C \ Compare Output Mode for Channe
+ $3 constant TCCR3A_WGM3 \ Waveform Generation Mode
+ 90 $3 bitmask: TCCR3A.WGM3 \ Waveform Generation Mode
+$91 constant TCCR3B \ Timer/Counter3 Control Registe
+ $80 constant TCCR3B_ICNC3 \ Input Capture 3 Noise Cancelle
+ 91 $80 bitmask: TCCR3B.ICNC3 \ Input Capture 3 Noise Cancelle
+ $40 constant TCCR3B_ICES3 \ Input Capture 3 Edge Select
+ 91 $40 bitmask: TCCR3B.ICES3 \ Input Capture 3 Edge Select
+ $20 constant TCCR3B_Res \ Reserved Bit
+ 91 $20 bitmask: TCCR3B.Res \ Reserved Bit
+ $18 constant TCCR3B_WGM3 \ Waveform Generation Mode
+ 91 $18 bitmask: TCCR3B.WGM3 \ Waveform Generation Mode
+ $7 constant TCCR3B_CS3 \ Clock Select
+ 91 $7 bitmask: TCCR3B.CS3 \ Clock Select
+$92 constant TCCR3C \ Timer/Counter3 Control Registe
+ $80 constant TCCR3C_FOC3A \ Force Output Compare for Chann
+ 92 $80 bitmask: TCCR3C.FOC3A \ Force Output Compare for Chann
+ $40 constant TCCR3C_FOC3B \ Force Output Compare for Chann
+ 92 $40 bitmask: TCCR3C.FOC3B \ Force Output Compare for Chann
+ $20 constant TCCR3C_FOC3C \ Force Output Compare for Chann
+ 92 $20 bitmask: TCCR3C.FOC3C \ Force Output Compare for Chann
+ $1f constant TCCR3C_Res \ Reserved
+ 92 $1f bitmask: TCCR3C.Res \ Reserved
+$94 constant TCNT3 \ Timer/Counter3 Bytes
+$98 constant OCR3A \ Timer/Counter3 Output Compare
+$9a constant OCR3B \ Timer/Counter3 Output Compare
+$9c constant OCR3C \ Timer/Counter3 Output Compare
+$96 constant ICR3 \ Timer/Counter3 Input Capture R
+$71 constant TIMSK3 \ Timer/Counter3 Interrupt Mask
+ $c0 constant TIMSK3_Res \ Reserved Bit
+ 71 $c0 bitmask: TIMSK3.Res \ Reserved Bit
+ $20 constant TIMSK3_ICIE3 \ Timer/Counter3 Input Capture I
+ 71 $20 bitmask: TIMSK3.ICIE3 \ Timer/Counter3 Input Capture I
+ $10 constant TIMSK3_Res \ Reserved Bit
+ 71 $10 bitmask: TIMSK3.Res \ Reserved Bit
+ $8 constant TIMSK3_OCIE3C \ Timer/Counter3 Output Compare
+ 71 $8 bitmask: TIMSK3.OCIE3C \ Timer/Counter3 Output Compare
+ $4 constant TIMSK3_OCIE3B \ Timer/Counter3 Output Compare
+ 71 $4 bitmask: TIMSK3.OCIE3B \ Timer/Counter3 Output Compare
+ $2 constant TIMSK3_OCIE3A \ Timer/Counter3 Output Compare
+ 71 $2 bitmask: TIMSK3.OCIE3A \ Timer/Counter3 Output Compare
+ $1 constant TIMSK3_TOIE3 \ Timer/Counter3 Overflow Interr
+ 71 $1 bitmask: TIMSK3.TOIE3 \ Timer/Counter3 Overflow Interr
+$38 constant TIFR3 \ Timer/Counter3 Interrupt Flag
+ $c0 constant TIFR3_Res \ Reserved Bit
+ 38 $c0 bitmask: TIFR3.Res \ Reserved Bit
+ $20 constant TIFR3_ICF3 \ Timer/Counter3 Input Capture F
+ 38 $20 bitmask: TIFR3.ICF3 \ Timer/Counter3 Input Capture F
+ $10 constant TIFR3_Res \ Reserved Bit
+ 38 $10 bitmask: TIFR3.Res \ Reserved Bit
+ $8 constant TIFR3_OCF3C \ Timer/Counter3 Output Compare
+ 38 $8 bitmask: TIFR3.OCF3C \ Timer/Counter3 Output Compare
+ $4 constant TIFR3_OCF3B \ Timer/Counter3 Output Compare
+ 38 $4 bitmask: TIFR3.OCF3B \ Timer/Counter3 Output Compare
+ $2 constant TIFR3_OCF3A \ Timer/Counter3 Output Compare
+ 38 $2 bitmask: TIFR3.OCF3A \ Timer/Counter3 Output Compare
+ $1 constant TIFR3_TOV3 \ Timer/Counter3 Overflow Flag
+ 38 $1 bitmask: TIFR3.TOV3 \ Timer/Counter3 Overflow Flag
diff --git a/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/TIMER_COUNTER_4.frt b/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/TIMER_COUNTER_4.frt
new file mode 100644
index 0000000..058e1ba
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/TIMER_COUNTER_4.frt
@@ -0,0 +1,68 @@
+\ Generated automatically for atmega2564rfr2
+\ #require bitnames.frt
+
+\ TIMER_COUNTER_4
+$a0 constant TCCR4A \ Timer/Counter4 Control Registe
+ $c0 constant TCCR4A_COM4A \ Compare Output Mode for Channe
+ a0 $c0 bitmask: TCCR4A.COM4A \ Compare Output Mode for Channe
+ $30 constant TCCR4A_COM4B \ Compare Output Mode for Channe
+ a0 $30 bitmask: TCCR4A.COM4B \ Compare Output Mode for Channe
+ $c constant TCCR4A_COM4C \ Compare Output Mode for Channe
+ a0 $c bitmask: TCCR4A.COM4C \ Compare Output Mode for Channe
+ $3 constant TCCR4A_WGM4 \ Waveform Generation Mode
+ a0 $3 bitmask: TCCR4A.WGM4 \ Waveform Generation Mode
+$a1 constant TCCR4B \ Timer/Counter4 Control Registe
+ $80 constant TCCR4B_ICNC4 \ Input Capture 4 Noise Cancelle
+ a1 $80 bitmask: TCCR4B.ICNC4 \ Input Capture 4 Noise Cancelle
+ $40 constant TCCR4B_ICES4 \ Input Capture 4 Edge Select
+ a1 $40 bitmask: TCCR4B.ICES4 \ Input Capture 4 Edge Select
+ $20 constant TCCR4B_Res \ Reserved Bit
+ a1 $20 bitmask: TCCR4B.Res \ Reserved Bit
+ $18 constant TCCR4B_WGM4 \ Waveform Generation Mode
+ a1 $18 bitmask: TCCR4B.WGM4 \ Waveform Generation Mode
+ $7 constant TCCR4B_CS4 \ Clock Select
+ a1 $7 bitmask: TCCR4B.CS4 \ Clock Select
+$a2 constant TCCR4C \ Timer/Counter4 Control Registe
+ $80 constant TCCR4C_FOC4A \ Force Output Compare for Chann
+ a2 $80 bitmask: TCCR4C.FOC4A \ Force Output Compare for Chann
+ $40 constant TCCR4C_FOC4B \ Force Output Compare for Chann
+ a2 $40 bitmask: TCCR4C.FOC4B \ Force Output Compare for Chann
+ $20 constant TCCR4C_FOC4C \ Force Output Compare for Chann
+ a2 $20 bitmask: TCCR4C.FOC4C \ Force Output Compare for Chann
+ $1f constant TCCR4C_Res \ Reserved
+ a2 $1f bitmask: TCCR4C.Res \ Reserved
+$a4 constant TCNT4 \ Timer/Counter4 Bytes
+$a8 constant OCR4A \ Timer/Counter4 Output Compare
+$aa constant OCR4B \ Timer/Counter4 Output Compare
+$ac constant OCR4C \ Timer/Counter4 Output Compare
+$a6 constant ICR4 \ Timer/Counter4 Input Capture R
+$72 constant TIMSK4 \ Timer/Counter4 Interrupt Mask
+ $c0 constant TIMSK4_Res \ Reserved Bit
+ 72 $c0 bitmask: TIMSK4.Res \ Reserved Bit
+ $20 constant TIMSK4_ICIE4 \ Timer/Counter4 Input Capture I
+ 72 $20 bitmask: TIMSK4.ICIE4 \ Timer/Counter4 Input Capture I
+ $10 constant TIMSK4_Res \ Reserved Bit
+ 72 $10 bitmask: TIMSK4.Res \ Reserved Bit
+ $8 constant TIMSK4_OCIE4C \ Timer/Counter4 Output Compare
+ 72 $8 bitmask: TIMSK4.OCIE4C \ Timer/Counter4 Output Compare
+ $4 constant TIMSK4_OCIE4B \ Timer/Counter4 Output Compare
+ 72 $4 bitmask: TIMSK4.OCIE4B \ Timer/Counter4 Output Compare
+ $2 constant TIMSK4_OCIE4A \ Timer/Counter4 Output Compare
+ 72 $2 bitmask: TIMSK4.OCIE4A \ Timer/Counter4 Output Compare
+ $1 constant TIMSK4_TOIE4 \ Timer/Counter4 Overflow Interr
+ 72 $1 bitmask: TIMSK4.TOIE4 \ Timer/Counter4 Overflow Interr
+$39 constant TIFR4 \ Timer/Counter4 Interrupt Flag
+ $c0 constant TIFR4_Res \ Reserved Bit
+ 39 $c0 bitmask: TIFR4.Res \ Reserved Bit
+ $20 constant TIFR4_ICF4 \ Timer/Counter4 Input Capture F
+ 39 $20 bitmask: TIFR4.ICF4 \ Timer/Counter4 Input Capture F
+ $10 constant TIFR4_Res \ Reserved Bit
+ 39 $10 bitmask: TIFR4.Res \ Reserved Bit
+ $8 constant TIFR4_OCF4C \ Timer/Counter4 Output Compare
+ 39 $8 bitmask: TIFR4.OCF4C \ Timer/Counter4 Output Compare
+ $4 constant TIFR4_OCF4B \ Timer/Counter4 Output Compare
+ 39 $4 bitmask: TIFR4.OCF4B \ Timer/Counter4 Output Compare
+ $2 constant TIFR4_OCF4A \ Timer/Counter4 Output Compare
+ 39 $2 bitmask: TIFR4.OCF4A \ Timer/Counter4 Output Compare
+ $1 constant TIFR4_TOV4 \ Timer/Counter4 Overflow Flag
+ 39 $1 bitmask: TIFR4.TOV4 \ Timer/Counter4 Overflow Flag
diff --git a/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/TIMER_COUNTER_5.frt b/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/TIMER_COUNTER_5.frt
new file mode 100644
index 0000000..a8a13c8
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/TIMER_COUNTER_5.frt
@@ -0,0 +1,68 @@
+\ Generated automatically for atmega2564rfr2
+\ #require bitnames.frt
+
+\ TIMER_COUNTER_5
+$120 constant TCCR5A \ Timer/Counter5 Control Registe
+ $c0 constant TCCR5A_COM5A \ Compare Output Mode for Channe
+ 120 $c0 bitmask: TCCR5A.COM5A \ Compare Output Mode for Channe
+ $30 constant TCCR5A_COM5B \ Compare Output Mode for Channe
+ 120 $30 bitmask: TCCR5A.COM5B \ Compare Output Mode for Channe
+ $c constant TCCR5A_COM5C \ Compare Output Mode for Channe
+ 120 $c bitmask: TCCR5A.COM5C \ Compare Output Mode for Channe
+ $3 constant TCCR5A_WGM5 \ Waveform Generation Mode
+ 120 $3 bitmask: TCCR5A.WGM5 \ Waveform Generation Mode
+$121 constant TCCR5B \ Timer/Counter5 Control Registe
+ $80 constant TCCR5B_ICNC5 \ Input Capture 5 Noise Cancelle
+ 121 $80 bitmask: TCCR5B.ICNC5 \ Input Capture 5 Noise Cancelle
+ $40 constant TCCR5B_ICES5 \ Input Capture 5 Edge Select
+ 121 $40 bitmask: TCCR5B.ICES5 \ Input Capture 5 Edge Select
+ $20 constant TCCR5B_Res \ Reserved Bit
+ 121 $20 bitmask: TCCR5B.Res \ Reserved Bit
+ $18 constant TCCR5B_WGM5 \ Waveform Generation Mode
+ 121 $18 bitmask: TCCR5B.WGM5 \ Waveform Generation Mode
+ $7 constant TCCR5B_CS5 \ Clock Select
+ 121 $7 bitmask: TCCR5B.CS5 \ Clock Select
+$122 constant TCCR5C \ Timer/Counter5 Control Registe
+ $80 constant TCCR5C_FOC5A \ Force Output Compare for Chann
+ 122 $80 bitmask: TCCR5C.FOC5A \ Force Output Compare for Chann
+ $40 constant TCCR5C_FOC5B \ Force Output Compare for Chann
+ 122 $40 bitmask: TCCR5C.FOC5B \ Force Output Compare for Chann
+ $20 constant TCCR5C_FOC5C \ Force Output Compare for Chann
+ 122 $20 bitmask: TCCR5C.FOC5C \ Force Output Compare for Chann
+ $1f constant TCCR5C_Res \ Reserved
+ 122 $1f bitmask: TCCR5C.Res \ Reserved
+$124 constant TCNT5 \ Timer/Counter5 Bytes
+$128 constant OCR5A \ Timer/Counter5 Output Compare
+$12a constant OCR5B \ Timer/Counter5 Output Compare
+$12c constant OCR5C \ Timer/Counter5 Output Compare
+$126 constant ICR5 \ Timer/Counter5 Input Capture R
+$73 constant TIMSK5 \ Timer/Counter5 Interrupt Mask
+ $c0 constant TIMSK5_Res \ Reserved Bit
+ 73 $c0 bitmask: TIMSK5.Res \ Reserved Bit
+ $20 constant TIMSK5_ICIE5 \ Timer/Counter5 Input Capture I
+ 73 $20 bitmask: TIMSK5.ICIE5 \ Timer/Counter5 Input Capture I
+ $10 constant TIMSK5_Res \ Reserved Bit
+ 73 $10 bitmask: TIMSK5.Res \ Reserved Bit
+ $8 constant TIMSK5_OCIE5C \ Timer/Counter5 Output Compare
+ 73 $8 bitmask: TIMSK5.OCIE5C \ Timer/Counter5 Output Compare
+ $4 constant TIMSK5_OCIE5B \ Timer/Counter5 Output Compare
+ 73 $4 bitmask: TIMSK5.OCIE5B \ Timer/Counter5 Output Compare
+ $2 constant TIMSK5_OCIE5A \ Timer/Counter5 Output Compare
+ 73 $2 bitmask: TIMSK5.OCIE5A \ Timer/Counter5 Output Compare
+ $1 constant TIMSK5_TOIE5 \ Timer/Counter5 Overflow Interr
+ 73 $1 bitmask: TIMSK5.TOIE5 \ Timer/Counter5 Overflow Interr
+$3a constant TIFR5 \ Timer/Counter5 Interrupt Flag
+ $c0 constant TIFR5_Res \ Reserved Bit
+ 3a $c0 bitmask: TIFR5.Res \ Reserved Bit
+ $20 constant TIFR5_ICF5 \ Timer/Counter5 Input Capture F
+ 3a $20 bitmask: TIFR5.ICF5 \ Timer/Counter5 Input Capture F
+ $10 constant TIFR5_Res \ Reserved Bit
+ 3a $10 bitmask: TIFR5.Res \ Reserved Bit
+ $8 constant TIFR5_OCF5C \ Timer/Counter5 Output Compare
+ 3a $8 bitmask: TIFR5.OCF5C \ Timer/Counter5 Output Compare
+ $4 constant TIFR5_OCF5B \ Timer/Counter5 Output Compare
+ 3a $4 bitmask: TIFR5.OCF5B \ Timer/Counter5 Output Compare
+ $2 constant TIFR5_OCF5A \ Timer/Counter5 Output Compare
+ 3a $2 bitmask: TIFR5.OCF5A \ Timer/Counter5 Output Compare
+ $1 constant TIFR5_TOV5 \ Timer/Counter5 Overflow Flag
+ 3a $1 bitmask: TIFR5.TOV5 \ Timer/Counter5 Overflow Flag
diff --git a/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/TRX24.frt b/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/TRX24.frt
new file mode 100644
index 0000000..eaf1722
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/TRX24.frt
@@ -0,0 +1,495 @@
+\ Generated automatically for atmega2564rfr2
+\ #require bitnames.frt
+
+\ TRX24
+$138 constant PARCR \ Power Amplifier Ramp up/down C
+ $e0 constant PARCR_PALTD \ ext. PA Ramp Down Lead Time
+ 138 $e0 bitmask: PARCR.PALTD \ ext. PA Ramp Down Lead Time
+ $1c constant PARCR_PALTU \ ext. PA Ramp Up Lead Time
+ 138 $1c bitmask: PARCR.PALTU \ ext. PA Ramp Up Lead Time
+ $2 constant PARCR_PARDFI \ Power Amplifier Ramp Down Freq
+ 138 $2 bitmask: PARCR.PARDFI \ Power Amplifier Ramp Down Freq
+ $1 constant PARCR_PARUFI \ Power Amplifier Ramp Up Freque
+ 138 $1 bitmask: PARCR.PARUFI \ Power Amplifier Ramp Up Freque
+$10e constant MAFSA0L \ Transceiver MAC Short Address
+ $ff constant MAFSA0L_MAFSA0L \ MAC Short Address low Byte for
+ 10e $ff bitmask: MAFSA0L.MAFSA0L \ MAC Short Address low Byte for
+$10f constant MAFSA0H \ Transceiver MAC Short Address
+ $ff constant MAFSA0H_MAFSA0H \ MAC Short Address high Byte fo
+ 10f $ff bitmask: MAFSA0H.MAFSA0H \ MAC Short Address high Byte fo
+$110 constant MAFPA0L \ Transceiver Personal Area Netw
+ $ff constant MAFPA0L_MAFPA0L \ MAC Personal Area Network ID l
+ 110 $ff bitmask: MAFPA0L.MAFPA0L \ MAC Personal Area Network ID l
+$111 constant MAFPA0H \ Transceiver Personal Area Netw
+ $ff constant MAFPA0H_MAFPA0H \ MAC Personal Area Network ID h
+ 111 $ff bitmask: MAFPA0H.MAFPA0H \ MAC Personal Area Network ID h
+$112 constant MAFSA1L \ Transceiver MAC Short Address
+ $ff constant MAFSA1L_MAFSA1L \ MAC Short Address low Byte for
+ 112 $ff bitmask: MAFSA1L.MAFSA1L \ MAC Short Address low Byte for
+$113 constant MAFSA1H \ Transceiver MAC Short Address
+ $ff constant MAFSA1H_MAFSA1H \ MAC Short Address high Byte fo
+ 113 $ff bitmask: MAFSA1H.MAFSA1H \ MAC Short Address high Byte fo
+$114 constant MAFPA1L \ Transceiver Personal Area Netw
+ $ff constant MAFPA1L_MAFPA1L \ MAC Personal Area Network ID l
+ 114 $ff bitmask: MAFPA1L.MAFPA1L \ MAC Personal Area Network ID l
+$115 constant MAFPA1H \ Transceiver Personal Area Netw
+ $ff constant MAFPA1H_MAFPA1H \ MAC Personal Area Network ID h
+ 115 $ff bitmask: MAFPA1H.MAFPA1H \ MAC Personal Area Network ID h
+$116 constant MAFSA2L \ Transceiver MAC Short Address
+ $ff constant MAFSA2L_MAFSA2L \ MAC Short Address low Byte for
+ 116 $ff bitmask: MAFSA2L.MAFSA2L \ MAC Short Address low Byte for
+$117 constant MAFSA2H \ Transceiver MAC Short Address
+ $ff constant MAFSA2H_MAFSA2H \ MAC Short Address high Byte fo
+ 117 $ff bitmask: MAFSA2H.MAFSA2H \ MAC Short Address high Byte fo
+$118 constant MAFPA2L \ Transceiver Personal Area Netw
+ $ff constant MAFPA2L_MAFPA2L \ MAC Personal Area Network ID l
+ 118 $ff bitmask: MAFPA2L.MAFPA2L \ MAC Personal Area Network ID l
+$119 constant MAFPA2H \ Transceiver Personal Area Netw
+ $ff constant MAFPA2H_MAFPA2H \ MAC Personal Area Network ID h
+ 119 $ff bitmask: MAFPA2H.MAFPA2H \ MAC Personal Area Network ID h
+$11a constant MAFSA3L \ Transceiver MAC Short Address
+ $ff constant MAFSA3L_MAFSA3L \ MAC Short Address low Byte for
+ 11a $ff bitmask: MAFSA3L.MAFSA3L \ MAC Short Address low Byte for
+$11b constant MAFSA3H \ Transceiver MAC Short Address
+ $ff constant MAFSA3H_MAFSA3H \ MAC Short Address high Byte fo
+ 11b $ff bitmask: MAFSA3H.MAFSA3H \ MAC Short Address high Byte fo
+$11c constant MAFPA3L \ Transceiver Personal Area Netw
+ $ff constant MAFPA3L_MAFPA3L \ MAC Personal Area Network ID l
+ 11c $ff bitmask: MAFPA3L.MAFPA3L \ MAC Personal Area Network ID l
+$11d constant MAFPA3H \ Transceiver Personal Area Netw
+ $ff constant MAFPA3H_MAFPA3H \ MAC Personal Area Network ID h
+ 11d $ff bitmask: MAFPA3H.MAFPA3H \ MAC Personal Area Network ID h
+$10c constant MAFCR0 \ Multiple Address Filter Config
+ $f0 constant MAFCR0_Res \ Reserved Bit
+ 10c $f0 bitmask: MAFCR0.Res \ Reserved Bit
+ $8 constant MAFCR0_MAF3EN \ Multiple Address Filter 3 Enab
+ 10c $8 bitmask: MAFCR0.MAF3EN \ Multiple Address Filter 3 Enab
+ $4 constant MAFCR0_MAF2EN \ Multiple Address Filter 2 Enab
+ 10c $4 bitmask: MAFCR0.MAF2EN \ Multiple Address Filter 2 Enab
+ $2 constant MAFCR0_MAF1EN \ Multiple Address Filter 1 Enab
+ 10c $2 bitmask: MAFCR0.MAF1EN \ Multiple Address Filter 1 Enab
+ $1 constant MAFCR0_MAF0EN \ Multiple Address Filter 0 Enab
+ 10c $1 bitmask: MAFCR0.MAF0EN \ Multiple Address Filter 0 Enab
+$10d constant MAFCR1 \ Multiple Address Filter Config
+ $80 constant MAFCR1_AACK_3_SET_PD \ Set Data Pending bit for addre
+ 10d $80 bitmask: MAFCR1.AACK_3_SET_PD \ Set Data Pending bit for addre
+ $40 constant MAFCR1_AACK_3_I_AM_COORD \ Enable PAN Coordinator mode fo
+ 10d $40 bitmask: MAFCR1.AACK_3_I_AM_COORD \ Enable PAN Coordinator mode fo
+ $20 constant MAFCR1_AACK_2_SET_PD \ Set Data Pending bit for addre
+ 10d $20 bitmask: MAFCR1.AACK_2_SET_PD \ Set Data Pending bit for addre
+ $10 constant MAFCR1_AACK_2_I_AM_COORD \ Enable PAN Coordinator mode fo
+ 10d $10 bitmask: MAFCR1.AACK_2_I_AM_COORD \ Enable PAN Coordinator mode fo
+ $8 constant MAFCR1_AACK_1_SET_PD \ Set Data Pending bit for addre
+ 10d $8 bitmask: MAFCR1.AACK_1_SET_PD \ Set Data Pending bit for addre
+ $4 constant MAFCR1_AACK_1_I_AM_COORD \ Enable PAN Coordinator mode fo
+ 10d $4 bitmask: MAFCR1.AACK_1_I_AM_COORD \ Enable PAN Coordinator mode fo
+ $2 constant MAFCR1_AACK_0_SET_PD \ Set Data Pending bit for addre
+ 10d $2 bitmask: MAFCR1.AACK_0_SET_PD \ Set Data Pending bit for addre
+ $1 constant MAFCR1_AACK_0_I_AM_COORD \ Enable PAN Coordinator mode fo
+ 10d $1 bitmask: MAFCR1.AACK_0_I_AM_COORD \ Enable PAN Coordinator mode fo
+$13c constant AES_CTRL \ AES Control Register
+ $80 constant AES_CTRL_AES_REQUEST \ Request AES Operation.
+ 13c $80 bitmask: AES_CTRL.AES_REQUEST \ Request AES Operation.
+ $40 constant AES_CTRL_Res \ Reserved Bit
+ 13c $40 bitmask: AES_CTRL.Res \ Reserved Bit
+ $20 constant AES_CTRL_AES_MODE \ Set AES Operation Mode
+ 13c $20 bitmask: AES_CTRL.AES_MODE \ Set AES Operation Mode
+ $10 constant AES_CTRL_Res \ Reserved Bit
+ 13c $10 bitmask: AES_CTRL.Res \ Reserved Bit
+ $8 constant AES_CTRL_AES_DIR \ Set AES Operation Direction
+ 13c $8 bitmask: AES_CTRL.AES_DIR \ Set AES Operation Direction
+ $4 constant AES_CTRL_AES_IM \ AES Interrupt Enable
+ 13c $4 bitmask: AES_CTRL.AES_IM \ AES Interrupt Enable
+ $3 constant AES_CTRL_Res \ Reserved Bit
+ 13c $3 bitmask: AES_CTRL.Res \ Reserved Bit
+$13d constant AES_STATUS \ AES Status Register
+ $80 constant AES_STATUS_AES_ER \ AES Operation Finished with Er
+ 13d $80 bitmask: AES_STATUS.AES_ER \ AES Operation Finished with Er
+ $7e constant AES_STATUS_Res \ Reserved
+ 13d $7e bitmask: AES_STATUS.Res \ Reserved
+ $1 constant AES_STATUS_AES_DONE \ AES Operation Finished with Su
+ 13d $1 bitmask: AES_STATUS.AES_DONE \ AES Operation Finished with Su
+$13e constant AES_STATE \ AES Plain and Cipher Text Buff
+ $ff constant AES_STATE_AES_STATE \ AES Plain and Cipher Text Buff
+ 13e $ff bitmask: AES_STATE.AES_STATE \ AES Plain and Cipher Text Buff
+$13f constant AES_KEY \ AES Encryption and Decryption
+ $ff constant AES_KEY_AES_KEY \ AES Encryption/Decryption Key
+ 13f $ff bitmask: AES_KEY.AES_KEY \ AES Encryption/Decryption Key
+$141 constant TRX_STATUS \ Transceiver Status Register
+ $80 constant TRX_STATUS_CCA_DONE \ CCA Algorithm Status
+ 141 $80 bitmask: TRX_STATUS.CCA_DONE \ CCA Algorithm Status
+ $40 constant TRX_STATUS_CCA_STATUS \ CCA Status Result
+ 141 $40 bitmask: TRX_STATUS.CCA_STATUS \ CCA Status Result
+ $20 constant TRX_STATUS_TST_STATUS \ Test mode status
+ 141 $20 bitmask: TRX_STATUS.TST_STATUS \ Test mode status
+ $1f constant TRX_STATUS_TRX_STATUS \ Transceiver Main Status
+ 141 $1f bitmask: TRX_STATUS.TRX_STATUS \ Transceiver Main Status
+$142 constant TRX_STATE \ Transceiver State Control Regi
+ $e0 constant TRX_STATE_TRAC_STATUS \ Transaction Status
+ 142 $e0 bitmask: TRX_STATE.TRAC_STATUS \ Transaction Status
+ $1f constant TRX_STATE_TRX_CMD \ State Control Command
+ 142 $1f bitmask: TRX_STATE.TRX_CMD \ State Control Command
+$143 constant TRX_CTRL_0 \ Reserved
+ $80 constant TRX_CTRL_0_Res7 \ Reserved
+ 143 $80 bitmask: TRX_CTRL_0.Res7 \ Reserved
+ $40 constant TRX_CTRL_0_PMU_EN \ Enable Phase Measurement Unit
+ 143 $40 bitmask: TRX_CTRL_0.PMU_EN \ Enable Phase Measurement Unit
+ $20 constant TRX_CTRL_0_PMU_START \ Start of Phase Measurement Uni
+ 143 $20 bitmask: TRX_CTRL_0.PMU_START \ Start of Phase Measurement Uni
+ $10 constant TRX_CTRL_0_PMU_IF_INV \ PMU IF Inverse
+ 143 $10 bitmask: TRX_CTRL_0.PMU_IF_INV \ PMU IF Inverse
+ $f constant TRX_CTRL_0_Res \ Reserved
+ 143 $f bitmask: TRX_CTRL_0.Res \ Reserved
+$144 constant TRX_CTRL_1 \ Transceiver Control Register 1
+ $80 constant TRX_CTRL_1_PA_EXT_EN \ External PA support enable
+ 144 $80 bitmask: TRX_CTRL_1.PA_EXT_EN \ External PA support enable
+ $40 constant TRX_CTRL_1_IRQ_2_EXT_EN \ Connect Frame Start IRQ to TC1
+ 144 $40 bitmask: TRX_CTRL_1.IRQ_2_EXT_EN \ Connect Frame Start IRQ to TC1
+ $20 constant TRX_CTRL_1_TX_AUTO_CRC_ON \ Enable Automatic CRC Calculati
+ 144 $20 bitmask: TRX_CTRL_1.TX_AUTO_CRC_ON \ Enable Automatic CRC Calculati
+ $10 constant TRX_CTRL_1_PLL_TX_FLT \ Enable PLL TX filter
+ 144 $10 bitmask: TRX_CTRL_1.PLL_TX_FLT \ Enable PLL TX filter
+ $f constant TRX_CTRL_1_Res \ Reserved
+ 144 $f bitmask: TRX_CTRL_1.Res \ Reserved
+$145 constant PHY_TX_PWR \ Transceiver Transmit Power Con
+ $f0 constant PHY_TX_PWR_Res \ Reserved
+ 145 $f0 bitmask: PHY_TX_PWR.Res \ Reserved
+ $f constant PHY_TX_PWR_TX_PWR \ Transmit Power Setting
+ 145 $f bitmask: PHY_TX_PWR.TX_PWR \ Transmit Power Setting
+$146 constant PHY_RSSI \ Receiver Signal Strength Indic
+ $80 constant PHY_RSSI_RX_CRC_VALID \ Received Frame CRC Status
+ 146 $80 bitmask: PHY_RSSI.RX_CRC_VALID \ Received Frame CRC Status
+ $60 constant PHY_RSSI_RND_VALUE \ Random Value
+ 146 $60 bitmask: PHY_RSSI.RND_VALUE \ Random Value
+ $1f constant PHY_RSSI_RSSI \ Receiver Signal Strength Indic
+ 146 $1f bitmask: PHY_RSSI.RSSI \ Receiver Signal Strength Indic
+$147 constant PHY_ED_LEVEL \ Transceiver Energy Detection L
+ $ff constant PHY_ED_LEVEL_ED_LEVEL \ Energy Detection Level
+ 147 $ff bitmask: PHY_ED_LEVEL.ED_LEVEL \ Energy Detection Level
+$148 constant PHY_CC_CCA \ Transceiver Clear Channel Asse
+ $80 constant PHY_CC_CCA_CCA_REQUEST \ Manual CCA Measurement Request
+ 148 $80 bitmask: PHY_CC_CCA.CCA_REQUEST \ Manual CCA Measurement Request
+ $60 constant PHY_CC_CCA_CCA_MODE \ Select CCA Measurement Mode
+ 148 $60 bitmask: PHY_CC_CCA.CCA_MODE \ Select CCA Measurement Mode
+ $1f constant PHY_CC_CCA_CHANNEL \ RX/TX Channel Selection
+ 148 $1f bitmask: PHY_CC_CCA.CHANNEL \ RX/TX Channel Selection
+$149 constant CCA_THRES \ Transceiver CCA Threshold Sett
+ $f0 constant CCA_THRES_CCA_CS_THRES \ CS Threshold Level for CCA Mea
+ 149 $f0 bitmask: CCA_THRES.CCA_CS_THRES \ CS Threshold Level for CCA Mea
+ $f constant CCA_THRES_CCA_ED_THRES \ ED Threshold Level for CCA Mea
+ 149 $f bitmask: CCA_THRES.CCA_ED_THRES \ ED Threshold Level for CCA Mea
+$14a constant RX_CTRL \ Transceiver Receive Control Re
+ $f constant RX_CTRL_PDT_THRES \ Receiver Sensitivity Control
+ 14a $f bitmask: RX_CTRL.PDT_THRES \ Receiver Sensitivity Control
+$14b constant SFD_VALUE \ Start of Frame Delimiter Value
+ $ff constant SFD_VALUE_SFD_VALUE \ Start of Frame Delimiter Value
+ 14b $ff bitmask: SFD_VALUE.SFD_VALUE \ Start of Frame Delimiter Value
+$14c constant TRX_CTRL_2 \ Transceiver Control Register 2
+ $80 constant TRX_CTRL_2_RX_SAFE_MODE \ RX Safe Mode
+ 14c $80 bitmask: TRX_CTRL_2.RX_SAFE_MODE \ RX Safe Mode
+ $7c constant TRX_CTRL_2_Res \ Reserved
+ 14c $7c bitmask: TRX_CTRL_2.Res \ Reserved
+ $3 constant TRX_CTRL_2_OQPSK_DATA_RATE \ Data Rate Selection
+ 14c $3 bitmask: TRX_CTRL_2.OQPSK_DATA_RATE \ Data Rate Selection
+$14d constant ANT_DIV \ Antenna Diversity Control Regi
+ $80 constant ANT_DIV_ANT_SEL \ Antenna Diversity Antenna Stat
+ 14d $80 bitmask: ANT_DIV.ANT_SEL \ Antenna Diversity Antenna Stat
+ $70 constant ANT_DIV_Res \ Reserved
+ 14d $70 bitmask: ANT_DIV.Res \ Reserved
+ $8 constant ANT_DIV_ANT_DIV_EN \ Enable Antenna Diversity
+ 14d $8 bitmask: ANT_DIV.ANT_DIV_EN \ Enable Antenna Diversity
+ $4 constant ANT_DIV_ANT_EXT_SW_EN \ Enable External Antenna Switch
+ 14d $4 bitmask: ANT_DIV.ANT_EXT_SW_EN \ Enable External Antenna Switch
+ $3 constant ANT_DIV_ANT_CTRL \ Static Antenna Diversity Switc
+ 14d $3 bitmask: ANT_DIV.ANT_CTRL \ Static Antenna Diversity Switc
+$14e constant IRQ_MASK \ Transceiver Interrupt Enable R
+ $80 constant IRQ_MASK_AWAKE_EN \ Awake Interrupt Enable
+ 14e $80 bitmask: IRQ_MASK.AWAKE_EN \ Awake Interrupt Enable
+ $40 constant IRQ_MASK_TX_END_EN \ TX_END Interrupt Enable
+ 14e $40 bitmask: IRQ_MASK.TX_END_EN \ TX_END Interrupt Enable
+ $20 constant IRQ_MASK_AMI_EN \ Address Match Interrupt Enable
+ 14e $20 bitmask: IRQ_MASK.AMI_EN \ Address Match Interrupt Enable
+ $10 constant IRQ_MASK_CCA_ED_DONE_EN \ End of ED Measurement Interrup
+ 14e $10 bitmask: IRQ_MASK.CCA_ED_DONE_EN \ End of ED Measurement Interrup
+ $8 constant IRQ_MASK_RX_END_EN \ RX_END Interrupt Enable
+ 14e $8 bitmask: IRQ_MASK.RX_END_EN \ RX_END Interrupt Enable
+ $4 constant IRQ_MASK_RX_START_EN \ RX_START Interrupt Enable
+ 14e $4 bitmask: IRQ_MASK.RX_START_EN \ RX_START Interrupt Enable
+ $2 constant IRQ_MASK_PLL_UNLOCK_EN \ PLL Unlock Interrupt Enable
+ 14e $2 bitmask: IRQ_MASK.PLL_UNLOCK_EN \ PLL Unlock Interrupt Enable
+ $1 constant IRQ_MASK_PLL_LOCK_EN \ PLL Lock Interrupt Enable
+ 14e $1 bitmask: IRQ_MASK.PLL_LOCK_EN \ PLL Lock Interrupt Enable
+$14f constant IRQ_STATUS \ Transceiver Interrupt Status R
+ $80 constant IRQ_STATUS_AWAKE \ Awake Interrupt Status
+ 14f $80 bitmask: IRQ_STATUS.AWAKE \ Awake Interrupt Status
+ $40 constant IRQ_STATUS_TX_END \ TX_END Interrupt Status
+ 14f $40 bitmask: IRQ_STATUS.TX_END \ TX_END Interrupt Status
+ $20 constant IRQ_STATUS_AMI \ Address Match Interrupt Status
+ 14f $20 bitmask: IRQ_STATUS.AMI \ Address Match Interrupt Status
+ $10 constant IRQ_STATUS_CCA_ED_DONE \ End of ED Measurement Interrup
+ 14f $10 bitmask: IRQ_STATUS.CCA_ED_DONE \ End of ED Measurement Interrup
+ $8 constant IRQ_STATUS_RX_END \ RX_END Interrupt Status
+ 14f $8 bitmask: IRQ_STATUS.RX_END \ RX_END Interrupt Status
+ $4 constant IRQ_STATUS_RX_START \ RX_START Interrupt Status
+ 14f $4 bitmask: IRQ_STATUS.RX_START \ RX_START Interrupt Status
+ $2 constant IRQ_STATUS_PLL_UNLOCK \ PLL Unlock Interrupt Status
+ 14f $2 bitmask: IRQ_STATUS.PLL_UNLOCK \ PLL Unlock Interrupt Status
+ $1 constant IRQ_STATUS_PLL_LOCK \ PLL Lock Interrupt Status
+ 14f $1 bitmask: IRQ_STATUS.PLL_LOCK \ PLL Lock Interrupt Status
+$be constant IRQ_MASK1 \ Transceiver Interrupt Enable R
+ $e0 constant IRQ_MASK1_Res \ Reserved Bit
+ be $e0 bitmask: IRQ_MASK1.Res \ Reserved Bit
+ $10 constant IRQ_MASK1_MAF_3_AMI_EN \ Address Match Interrupt enable
+ be $10 bitmask: IRQ_MASK1.MAF_3_AMI_EN \ Address Match Interrupt enable
+ $8 constant IRQ_MASK1_MAF_2_AMI_EN \ Address Match Interrupt enable
+ be $8 bitmask: IRQ_MASK1.MAF_2_AMI_EN \ Address Match Interrupt enable
+ $4 constant IRQ_MASK1_MAF_1_AMI_EN \ Address Match Interrupt enable
+ be $4 bitmask: IRQ_MASK1.MAF_1_AMI_EN \ Address Match Interrupt enable
+ $2 constant IRQ_MASK1_MAF_0_AMI_EN \ Address Match Interrupt enable
+ be $2 bitmask: IRQ_MASK1.MAF_0_AMI_EN \ Address Match Interrupt enable
+ $1 constant IRQ_MASK1_TX_START_EN \ Transmit Start Interrupt enabl
+ be $1 bitmask: IRQ_MASK1.TX_START_EN \ Transmit Start Interrupt enabl
+$bf constant IRQ_STATUS1 \ Transceiver Interrupt Status R
+ $e0 constant IRQ_STATUS1_Res \ Reserved Bit
+ bf $e0 bitmask: IRQ_STATUS1.Res \ Reserved Bit
+ $10 constant IRQ_STATUS1_MAF_3_AMI \ Address Match Interrupt Status
+ bf $10 bitmask: IRQ_STATUS1.MAF_3_AMI \ Address Match Interrupt Status
+ $8 constant IRQ_STATUS1_MAF_2_AMI \ Address Match Interrupt Status
+ bf $8 bitmask: IRQ_STATUS1.MAF_2_AMI \ Address Match Interrupt Status
+ $4 constant IRQ_STATUS1_MAF_1_AMI \ Address Match Interrupt Status
+ bf $4 bitmask: IRQ_STATUS1.MAF_1_AMI \ Address Match Interrupt Status
+ $2 constant IRQ_STATUS1_MAF_0_AMI \ Address Match Interrupt Status
+ bf $2 bitmask: IRQ_STATUS1.MAF_0_AMI \ Address Match Interrupt Status
+ $1 constant IRQ_STATUS1_TX_START \ Transmit Start Interrupt Statu
+ bf $1 bitmask: IRQ_STATUS1.TX_START \ Transmit Start Interrupt Statu
+$150 constant VREG_CTRL \ Voltage Regulator Control and
+ $80 constant VREG_CTRL_AVREG_EXT \ Use External AVDD Regulator
+ 150 $80 bitmask: VREG_CTRL.AVREG_EXT \ Use External AVDD Regulator
+ $40 constant VREG_CTRL_AVDD_OK \ AVDD Supply Voltage Valid
+ 150 $40 bitmask: VREG_CTRL.AVDD_OK \ AVDD Supply Voltage Valid
+ $8 constant VREG_CTRL_DVREG_EXT \ Use External DVDD Regulator
+ 150 $8 bitmask: VREG_CTRL.DVREG_EXT \ Use External DVDD Regulator
+ $4 constant VREG_CTRL_DVDD_OK \ DVDD Supply Voltage Valid
+ 150 $4 bitmask: VREG_CTRL.DVDD_OK \ DVDD Supply Voltage Valid
+$151 constant BATMON \ Battery Monitor Control and St
+ $80 constant BATMON_BAT_LOW \ Battery Monitor Interrupt Stat
+ 151 $80 bitmask: BATMON.BAT_LOW \ Battery Monitor Interrupt Stat
+ $40 constant BATMON_BAT_LOW_EN \ Battery Monitor Interrupt Enab
+ 151 $40 bitmask: BATMON.BAT_LOW_EN \ Battery Monitor Interrupt Enab
+ $20 constant BATMON_BATMON_OK \ Battery Monitor Status
+ 151 $20 bitmask: BATMON.BATMON_OK \ Battery Monitor Status
+ $10 constant BATMON_BATMON_HR \ Battery Monitor Voltage Range
+ 151 $10 bitmask: BATMON.BATMON_HR \ Battery Monitor Voltage Range
+ $f constant BATMON_BATMON_VTH \ Battery Monitor Threshold Volt
+ 151 $f bitmask: BATMON.BATMON_VTH \ Battery Monitor Threshold Volt
+$152 constant XOSC_CTRL \ Crystal Oscillator Control Reg
+ $f0 constant XOSC_CTRL_XTAL_MODE \ Crystal Oscillator Operating M
+ 152 $f0 bitmask: XOSC_CTRL.XTAL_MODE \ Crystal Oscillator Operating M
+ $f constant XOSC_CTRL_XTAL_TRIM \ Crystal Oscillator Load Capaci
+ 152 $f bitmask: XOSC_CTRL.XTAL_TRIM \ Crystal Oscillator Load Capaci
+$153 constant CC_CTRL_0 \ Channel Control Register 0
+ $ff constant CC_CTRL_0_CC_NUMBER \ Channel Number
+ 153 $ff bitmask: CC_CTRL_0.CC_NUMBER \ Channel Number
+$154 constant CC_CTRL_1 \ Channel Control Register 1
+ $f constant CC_CTRL_1_CC_BAND \ Channel Band
+ 154 $f bitmask: CC_CTRL_1.CC_BAND \ Channel Band
+$155 constant RX_SYN \ Transceiver Receiver Sensitivi
+ $80 constant RX_SYN_RX_PDT_DIS \ Prevent Frame Reception
+ 155 $80 bitmask: RX_SYN.RX_PDT_DIS \ Prevent Frame Reception
+ $40 constant RX_SYN_RX_OVERRIDE \ Receiver Override Function
+ 155 $40 bitmask: RX_SYN.RX_OVERRIDE \ Receiver Override Function
+ $30 constant RX_SYN_Res \ Reserved
+ 155 $30 bitmask: RX_SYN.Res \ Reserved
+ $f constant RX_SYN_RX_PDT_LEVEL \ Reduce Receiver Sensitivity
+ 155 $f bitmask: RX_SYN.RX_PDT_LEVEL \ Reduce Receiver Sensitivity
+$156 constant TRX_RPC \ Transceiver Reduced Power Cons
+ $c0 constant TRX_RPC_RX_RPC_CTRL \ Smart Receiving Mode Timing
+ 156 $c0 bitmask: TRX_RPC.RX_RPC_CTRL \ Smart Receiving Mode Timing
+ $20 constant TRX_RPC_RX_RPC_EN \ Reciver Smart Receiving Mode E
+ 156 $20 bitmask: TRX_RPC.RX_RPC_EN \ Reciver Smart Receiving Mode E
+ $10 constant TRX_RPC_PDT_RPC_EN \ Smart Receiving Mode Reduced S
+ 156 $10 bitmask: TRX_RPC.PDT_RPC_EN \ Smart Receiving Mode Reduced S
+ $8 constant TRX_RPC_PLL_RPC_EN \ PLL Smart Receiving Mode Enabl
+ 156 $8 bitmask: TRX_RPC.PLL_RPC_EN \ PLL Smart Receiving Mode Enabl
+ $4 constant TRX_RPC_Res0 \ Reserved
+ 156 $4 bitmask: TRX_RPC.Res0 \ Reserved
+ $2 constant TRX_RPC_IPAN_RPC_EN \ Smart Receiving Mode IPAN Hand
+ 156 $2 bitmask: TRX_RPC.IPAN_RPC_EN \ Smart Receiving Mode IPAN Hand
+ $1 constant TRX_RPC_XAH_RPC_EN \ Smart Receiving in Extended Op
+ 156 $1 bitmask: TRX_RPC.XAH_RPC_EN \ Smart Receiving in Extended Op
+$157 constant XAH_CTRL_1 \ Transceiver Acknowledgment Fra
+ $c0 constant XAH_CTRL_1_Res \ Reserved Bit
+ 157 $c0 bitmask: XAH_CTRL_1.Res \ Reserved Bit
+ $20 constant XAH_CTRL_1_AACK_FLTR_RES_FT \ Filter Reserved Frames
+ 157 $20 bitmask: XAH_CTRL_1.AACK_FLTR_RES_FT \ Filter Reserved Frames
+ $10 constant XAH_CTRL_1_AACK_UPLD_RES_FT \ Process Reserved Frames
+ 157 $10 bitmask: XAH_CTRL_1.AACK_UPLD_RES_FT \ Process Reserved Frames
+ $8 constant XAH_CTRL_1_Res \ Reserved Bit
+ 157 $8 bitmask: XAH_CTRL_1.Res \ Reserved Bit
+ $4 constant XAH_CTRL_1_AACK_ACK_TIME \ Reduce Acknowledgment Time
+ 157 $4 bitmask: XAH_CTRL_1.AACK_ACK_TIME \ Reduce Acknowledgment Time
+ $2 constant XAH_CTRL_1_AACK_PROM_MODE \ Enable Promiscuous Mode
+ 157 $2 bitmask: XAH_CTRL_1.AACK_PROM_MODE \ Enable Promiscuous Mode
+ $1 constant XAH_CTRL_1_Res \ Reserved Bit
+ 157 $1 bitmask: XAH_CTRL_1.Res \ Reserved Bit
+$158 constant FTN_CTRL \ Transceiver Filter Tuning Cont
+ $80 constant FTN_CTRL_FTN_START \ Start Calibration Loop of Filt
+ 158 $80 bitmask: FTN_CTRL.FTN_START \ Start Calibration Loop of Filt
+$15a constant PLL_CF \ Transceiver Center Frequency C
+ $80 constant PLL_CF_PLL_CF_START \ Start Center Frequency Calibra
+ 15a $80 bitmask: PLL_CF.PLL_CF_START \ Start Center Frequency Calibra
+$15b constant PLL_DCU \ Transceiver Delay Cell Calibra
+ $80 constant PLL_DCU_PLL_DCU_START \ Start Delay Cell Calibration
+ 15b $80 bitmask: PLL_DCU.PLL_DCU_START \ Start Delay Cell Calibration
+$15c constant PART_NUM \ Device Identification Register
+ $ff constant PART_NUM_PART_NUM \ Part Number
+ 15c $ff bitmask: PART_NUM.PART_NUM \ Part Number
+$15d constant VERSION_NUM \ Device Identification Register
+ $ff constant VERSION_NUM_VERSION_NUM \ Version Number
+ 15d $ff bitmask: VERSION_NUM.VERSION_NUM \ Version Number
+$15e constant MAN_ID_0 \ Device Identification Register
+ $80 constant MAN_ID_0_MAN_ID_07 \ Manufacturer ID (Low Byte)
+ 15e $80 bitmask: MAN_ID_0.MAN_ID_07 \ Manufacturer ID (Low Byte)
+ $40 constant MAN_ID_0_MAN_ID_06 \ Manufacturer ID (Low Byte)
+ 15e $40 bitmask: MAN_ID_0.MAN_ID_06 \ Manufacturer ID (Low Byte)
+ $20 constant MAN_ID_0_MAN_ID_05 \ Manufacturer ID (Low Byte)
+ 15e $20 bitmask: MAN_ID_0.MAN_ID_05 \ Manufacturer ID (Low Byte)
+ $10 constant MAN_ID_0_MAN_ID_04 \ Manufacturer ID (Low Byte)
+ 15e $10 bitmask: MAN_ID_0.MAN_ID_04 \ Manufacturer ID (Low Byte)
+ $8 constant MAN_ID_0_MAN_ID_03 \ Manufacturer ID (Low Byte)
+ 15e $8 bitmask: MAN_ID_0.MAN_ID_03 \ Manufacturer ID (Low Byte)
+ $4 constant MAN_ID_0_MAN_ID_02 \ Manufacturer ID (Low Byte)
+ 15e $4 bitmask: MAN_ID_0.MAN_ID_02 \ Manufacturer ID (Low Byte)
+ $2 constant MAN_ID_0_MAN_ID_01 \ Manufacturer ID (Low Byte)
+ 15e $2 bitmask: MAN_ID_0.MAN_ID_01 \ Manufacturer ID (Low Byte)
+ $1 constant MAN_ID_0_MAN_ID_00 \ Manufacturer ID (Low Byte)
+ 15e $1 bitmask: MAN_ID_0.MAN_ID_00 \ Manufacturer ID (Low Byte)
+$15f constant MAN_ID_1 \ Device Identification Register
+ $ff constant MAN_ID_1_MAN_ID_ \ Manufacturer ID (High Byte)
+ 15f $ff bitmask: MAN_ID_1.MAN_ID_ \ Manufacturer ID (High Byte)
+$160 constant SHORT_ADDR_0 \ Transceiver MAC Short Address
+ $80 constant SHORT_ADDR_0_SHORT_ADDR_07 \ MAC Short Address
+ 160 $80 bitmask: SHORT_ADDR_0.SHORT_ADDR_07 \ MAC Short Address
+ $40 constant SHORT_ADDR_0_SHORT_ADDR_06 \ MAC Short Address
+ 160 $40 bitmask: SHORT_ADDR_0.SHORT_ADDR_06 \ MAC Short Address
+ $20 constant SHORT_ADDR_0_SHORT_ADDR_05 \ MAC Short Address
+ 160 $20 bitmask: SHORT_ADDR_0.SHORT_ADDR_05 \ MAC Short Address
+ $10 constant SHORT_ADDR_0_SHORT_ADDR_04 \ MAC Short Address
+ 160 $10 bitmask: SHORT_ADDR_0.SHORT_ADDR_04 \ MAC Short Address
+ $8 constant SHORT_ADDR_0_SHORT_ADDR_03 \ MAC Short Address
+ 160 $8 bitmask: SHORT_ADDR_0.SHORT_ADDR_03 \ MAC Short Address
+ $4 constant SHORT_ADDR_0_SHORT_ADDR_02 \ MAC Short Address
+ 160 $4 bitmask: SHORT_ADDR_0.SHORT_ADDR_02 \ MAC Short Address
+ $2 constant SHORT_ADDR_0_SHORT_ADDR_01 \ MAC Short Address
+ 160 $2 bitmask: SHORT_ADDR_0.SHORT_ADDR_01 \ MAC Short Address
+ $1 constant SHORT_ADDR_0_SHORT_ADDR_00 \ MAC Short Address
+ 160 $1 bitmask: SHORT_ADDR_0.SHORT_ADDR_00 \ MAC Short Address
+$161 constant SHORT_ADDR_1 \ Transceiver MAC Short Address
+ $ff constant SHORT_ADDR_1_SHORT_ADDR_ \ MAC Short Address
+ 161 $ff bitmask: SHORT_ADDR_1.SHORT_ADDR_ \ MAC Short Address
+$162 constant PAN_ID_0 \ Transceiver Personal Area Netw
+ $80 constant PAN_ID_0_PAN_ID_07 \ MAC Personal Area Network ID
+ 162 $80 bitmask: PAN_ID_0.PAN_ID_07 \ MAC Personal Area Network ID
+ $40 constant PAN_ID_0_PAN_ID_06 \ MAC Personal Area Network ID
+ 162 $40 bitmask: PAN_ID_0.PAN_ID_06 \ MAC Personal Area Network ID
+ $20 constant PAN_ID_0_PAN_ID_05 \ MAC Personal Area Network ID
+ 162 $20 bitmask: PAN_ID_0.PAN_ID_05 \ MAC Personal Area Network ID
+ $10 constant PAN_ID_0_PAN_ID_04 \ MAC Personal Area Network ID
+ 162 $10 bitmask: PAN_ID_0.PAN_ID_04 \ MAC Personal Area Network ID
+ $8 constant PAN_ID_0_PAN_ID_03 \ MAC Personal Area Network ID
+ 162 $8 bitmask: PAN_ID_0.PAN_ID_03 \ MAC Personal Area Network ID
+ $4 constant PAN_ID_0_PAN_ID_02 \ MAC Personal Area Network ID
+ 162 $4 bitmask: PAN_ID_0.PAN_ID_02 \ MAC Personal Area Network ID
+ $2 constant PAN_ID_0_PAN_ID_01 \ MAC Personal Area Network ID
+ 162 $2 bitmask: PAN_ID_0.PAN_ID_01 \ MAC Personal Area Network ID
+ $1 constant PAN_ID_0_PAN_ID_00 \ MAC Personal Area Network ID
+ 162 $1 bitmask: PAN_ID_0.PAN_ID_00 \ MAC Personal Area Network ID
+$163 constant PAN_ID_1 \ Transceiver Personal Area Netw
+ $ff constant PAN_ID_1_PAN_ID_ \ MAC Personal Area Network ID
+ 163 $ff bitmask: PAN_ID_1.PAN_ID_ \ MAC Personal Area Network ID
+$164 constant IEEE_ADDR_0 \ Transceiver MAC IEEE Address R
+ $80 constant IEEE_ADDR_0_IEEE_ADDR_07 \ MAC IEEE Address
+ 164 $80 bitmask: IEEE_ADDR_0.IEEE_ADDR_07 \ MAC IEEE Address
+ $40 constant IEEE_ADDR_0_IEEE_ADDR_06 \ MAC IEEE Address
+ 164 $40 bitmask: IEEE_ADDR_0.IEEE_ADDR_06 \ MAC IEEE Address
+ $20 constant IEEE_ADDR_0_IEEE_ADDR_05 \ MAC IEEE Address
+ 164 $20 bitmask: IEEE_ADDR_0.IEEE_ADDR_05 \ MAC IEEE Address
+ $10 constant IEEE_ADDR_0_IEEE_ADDR_04 \ MAC IEEE Address
+ 164 $10 bitmask: IEEE_ADDR_0.IEEE_ADDR_04 \ MAC IEEE Address
+ $8 constant IEEE_ADDR_0_IEEE_ADDR_03 \ MAC IEEE Address
+ 164 $8 bitmask: IEEE_ADDR_0.IEEE_ADDR_03 \ MAC IEEE Address
+ $4 constant IEEE_ADDR_0_IEEE_ADDR_02 \ MAC IEEE Address
+ 164 $4 bitmask: IEEE_ADDR_0.IEEE_ADDR_02 \ MAC IEEE Address
+ $2 constant IEEE_ADDR_0_IEEE_ADDR_01 \ MAC IEEE Address
+ 164 $2 bitmask: IEEE_ADDR_0.IEEE_ADDR_01 \ MAC IEEE Address
+ $1 constant IEEE_ADDR_0_IEEE_ADDR_00 \ MAC IEEE Address
+ 164 $1 bitmask: IEEE_ADDR_0.IEEE_ADDR_00 \ MAC IEEE Address
+$165 constant IEEE_ADDR_1 \ Transceiver MAC IEEE Address R
+ $ff constant IEEE_ADDR_1_IEEE_ADDR_ \ MAC IEEE Address
+ 165 $ff bitmask: IEEE_ADDR_1.IEEE_ADDR_ \ MAC IEEE Address
+$166 constant IEEE_ADDR_2 \ Transceiver MAC IEEE Address R
+ $ff constant IEEE_ADDR_2_IEEE_ADDR_ \ MAC IEEE Address
+ 166 $ff bitmask: IEEE_ADDR_2.IEEE_ADDR_ \ MAC IEEE Address
+$167 constant IEEE_ADDR_3 \ Transceiver MAC IEEE Address R
+ $ff constant IEEE_ADDR_3_IEEE_ADDR_ \ MAC IEEE Address
+ 167 $ff bitmask: IEEE_ADDR_3.IEEE_ADDR_ \ MAC IEEE Address
+$168 constant IEEE_ADDR_4 \ Transceiver MAC IEEE Address R
+ $ff constant IEEE_ADDR_4_IEEE_ADDR_ \ MAC IEEE Address
+ 168 $ff bitmask: IEEE_ADDR_4.IEEE_ADDR_ \ MAC IEEE Address
+$169 constant IEEE_ADDR_5 \ Transceiver MAC IEEE Address R
+ $ff constant IEEE_ADDR_5_IEEE_ADDR_ \ MAC IEEE Address
+ 169 $ff bitmask: IEEE_ADDR_5.IEEE_ADDR_ \ MAC IEEE Address
+$16a constant IEEE_ADDR_6 \ Transceiver MAC IEEE Address R
+ $ff constant IEEE_ADDR_6_IEEE_ADDR_ \ MAC IEEE Address
+ 16a $ff bitmask: IEEE_ADDR_6.IEEE_ADDR_ \ MAC IEEE Address
+$16b constant IEEE_ADDR_7 \ Transceiver MAC IEEE Address R
+ $ff constant IEEE_ADDR_7_IEEE_ADDR_ \ MAC IEEE Address
+ 16b $ff bitmask: IEEE_ADDR_7.IEEE_ADDR_ \ MAC IEEE Address
+$16c constant XAH_CTRL_0 \ Transceiver Extended Operating
+ $f0 constant XAH_CTRL_0_MAX_FRAME_RETRIES \ Maximum Number of Frame Re-tra
+ 16c $f0 bitmask: XAH_CTRL_0.MAX_FRAME_RETRIES \ Maximum Number of Frame Re-tra
+ $e constant XAH_CTRL_0_MAX_CSMA_RETRIES \ Maximum Number of CSMA-CA Proc
+ 16c $e bitmask: XAH_CTRL_0.MAX_CSMA_RETRIES \ Maximum Number of CSMA-CA Proc
+ $1 constant XAH_CTRL_0_SLOTTED_OPERATION \ Set Slotted Acknowledgment
+ 16c $1 bitmask: XAH_CTRL_0.SLOTTED_OPERATION \ Set Slotted Acknowledgment
+$16d constant CSMA_SEED_0 \ Transceiver CSMA-CA Random Num
+ $80 constant CSMA_SEED_0_CSMA_SEED_07 \ Seed Value for CSMA Random Num
+ 16d $80 bitmask: CSMA_SEED_0.CSMA_SEED_07 \ Seed Value for CSMA Random Num
+ $40 constant CSMA_SEED_0_CSMA_SEED_06 \ Seed Value for CSMA Random Num
+ 16d $40 bitmask: CSMA_SEED_0.CSMA_SEED_06 \ Seed Value for CSMA Random Num
+ $20 constant CSMA_SEED_0_CSMA_SEED_05 \ Seed Value for CSMA Random Num
+ 16d $20 bitmask: CSMA_SEED_0.CSMA_SEED_05 \ Seed Value for CSMA Random Num
+ $10 constant CSMA_SEED_0_CSMA_SEED_04 \ Seed Value for CSMA Random Num
+ 16d $10 bitmask: CSMA_SEED_0.CSMA_SEED_04 \ Seed Value for CSMA Random Num
+ $8 constant CSMA_SEED_0_CSMA_SEED_03 \ Seed Value for CSMA Random Num
+ 16d $8 bitmask: CSMA_SEED_0.CSMA_SEED_03 \ Seed Value for CSMA Random Num
+ $4 constant CSMA_SEED_0_CSMA_SEED_02 \ Seed Value for CSMA Random Num
+ 16d $4 bitmask: CSMA_SEED_0.CSMA_SEED_02 \ Seed Value for CSMA Random Num
+ $2 constant CSMA_SEED_0_CSMA_SEED_01 \ Seed Value for CSMA Random Num
+ 16d $2 bitmask: CSMA_SEED_0.CSMA_SEED_01 \ Seed Value for CSMA Random Num
+ $1 constant CSMA_SEED_0_CSMA_SEED_00 \ Seed Value for CSMA Random Num
+ 16d $1 bitmask: CSMA_SEED_0.CSMA_SEED_00 \ Seed Value for CSMA Random Num
+$16e constant CSMA_SEED_1 \ Transceiver Acknowledgment Fra
+ $c0 constant CSMA_SEED_1_AACK_FVN_MODE \ Acknowledgment Frame Filter Mo
+ 16e $c0 bitmask: CSMA_SEED_1.AACK_FVN_MODE \ Acknowledgment Frame Filter Mo
+ $20 constant CSMA_SEED_1_AACK_SET_PD \ Set Frame Pending Sub-field
+ 16e $20 bitmask: CSMA_SEED_1.AACK_SET_PD \ Set Frame Pending Sub-field
+ $10 constant CSMA_SEED_1_AACK_DIS_ACK \ Disable Acknowledgment Frame T
+ 16e $10 bitmask: CSMA_SEED_1.AACK_DIS_ACK \ Disable Acknowledgment Frame T
+ $8 constant CSMA_SEED_1_AACK_I_AM_COORD \ Set Personal Area Network Coor
+ 16e $8 bitmask: CSMA_SEED_1.AACK_I_AM_COORD \ Set Personal Area Network Coor
+ $7 constant CSMA_SEED_1_CSMA_SEED_1 \ Seed Value for CSMA Random Num
+ 16e $7 bitmask: CSMA_SEED_1.CSMA_SEED_1 \ Seed Value for CSMA Random Num
+$16f constant CSMA_BE \ Transceiver CSMA-CA Back-off E
+ $f0 constant CSMA_BE_MAX_BE \ Maximum Back-off Exponent
+ 16f $f0 bitmask: CSMA_BE.MAX_BE \ Maximum Back-off Exponent
+ $f constant CSMA_BE_MIN_BE \ Minimum Back-off Exponent
+ 16f $f bitmask: CSMA_BE.MIN_BE \ Minimum Back-off Exponent
+$176 constant TST_CTRL_DIGI \ Transceiver Digital Test Contr
+ $f constant TST_CTRL_DIGI_TST_CTRL_DIG \ Digital Test Controller Regist
+ 176 $f bitmask: TST_CTRL_DIGI.TST_CTRL_DIG \ Digital Test Controller Regist
+$17b constant TST_RX_LENGTH \ Transceiver Received Frame Len
+ $ff constant TST_RX_LENGTH_RX_LENGTH \ Received Frame Length
+ 17b $ff bitmask: TST_RX_LENGTH.RX_LENGTH \ Received Frame Length
+$180 constant TRXFBST \ Start of frame buffer
+$1ff constant TRXFBEND \ End of frame buffer
diff --git a/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/TWI.frt b/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/TWI.frt
new file mode 100644
index 0000000..f7914e1
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/TWI.frt
@@ -0,0 +1,40 @@
+\ Generated automatically for atmega2564rfr2
+\ #require bitnames.frt
+
+\ TWI
+$bd constant TWAMR \ TWI (Slave) Address Mask Regis
+ $fe constant TWAMR_TWAM \ TWI Address Mask
+ bd $fe bitmask: TWAMR.TWAM \ TWI Address Mask
+ $1 constant TWAMR_Res \ Reserved Bit
+ bd $1 bitmask: TWAMR.Res \ Reserved Bit
+$b8 constant TWBR \ TWI Bit Rate Register
+$bc constant TWCR \ TWI Control Register
+ $80 constant TWCR_TWINT \ TWI Interrupt Flag
+ bc $80 bitmask: TWCR.TWINT \ TWI Interrupt Flag
+ $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
+ bc $40 bitmask: TWCR.TWEA \ TWI Enable Acknowledge Bit
+ $20 constant TWCR_TWSTA \ TWI START Condition Bit
+ bc $20 bitmask: TWCR.TWSTA \ TWI START Condition Bit
+ $10 constant TWCR_TWSTO \ TWI STOP Condition Bit
+ bc $10 bitmask: TWCR.TWSTO \ TWI STOP Condition Bit
+ $8 constant TWCR_TWWC \ TWI Write Collision Flag
+ bc $8 bitmask: TWCR.TWWC \ TWI Write Collision Flag
+ $4 constant TWCR_TWEN \ TWI Enable Bit
+ bc $4 bitmask: TWCR.TWEN \ TWI Enable Bit
+ $2 constant TWCR_Res \ Reserved Bit
+ bc $2 bitmask: TWCR.Res \ Reserved Bit
+ $1 constant TWCR_TWIE \ TWI Interrupt Enable
+ bc $1 bitmask: TWCR.TWIE \ TWI Interrupt Enable
+$b9 constant TWSR \ TWI Status Register
+ $f8 constant TWSR_TWS \ TWI Status
+ b9 $f8 bitmask: TWSR.TWS \ TWI Status
+ $4 constant TWSR_Res \ Reserved Bit
+ b9 $4 bitmask: TWSR.Res \ Reserved Bit
+ $3 constant TWSR_TWPS \ TWI Prescaler Bits
+ b9 $3 bitmask: TWSR.TWPS \ TWI Prescaler Bits
+$bb constant TWDR \ TWI Data Register
+$ba constant TWAR \ TWI (Slave) Address Register
+ $fe constant TWAR_TWA \ TWI (Slave) Address
+ ba $fe bitmask: TWAR.TWA \ TWI (Slave) Address
+ $1 constant TWAR_TWGCE \ TWI General Call Recognition E
+ ba $1 bitmask: TWAR.TWGCE \ TWI General Call Recognition E
diff --git a/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/USART0.frt b/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/USART0.frt
new file mode 100644
index 0000000..3ea3fd7
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/USART0.frt
@@ -0,0 +1,51 @@
+\ Generated automatically for atmega2564rfr2
+\ #require bitnames.frt
+
+\ USART0
+$c6 constant UDR0 \ USART0 I/O Data Register
+$c0 constant UCSR0A \ USART0 Control and Status Regi
+ $80 constant UCSR0A_RXC0 \ USART Receive Complete
+ c0 $80 bitmask: UCSR0A.RXC0 \ USART Receive Complete
+ $40 constant UCSR0A_TXC0 \ USART Transmit Complete
+ c0 $40 bitmask: UCSR0A.TXC0 \ USART Transmit Complete
+ $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
+ c0 $20 bitmask: UCSR0A.UDRE0 \ USART Data Register Empty
+ $10 constant UCSR0A_FE0 \ Frame Error
+ c0 $10 bitmask: UCSR0A.FE0 \ Frame Error
+ $8 constant UCSR0A_DOR0 \ Data OverRun
+ c0 $8 bitmask: UCSR0A.DOR0 \ Data OverRun
+ $4 constant UCSR0A_UPE0 \ USART Parity Error
+ c0 $4 bitmask: UCSR0A.UPE0 \ USART Parity Error
+ $2 constant UCSR0A_U2X0 \ Double the USART Transmission
+ c0 $2 bitmask: UCSR0A.U2X0 \ Double the USART Transmission
+ $1 constant UCSR0A_MPCM0 \ Multi-processor Communication
+ c0 $1 bitmask: UCSR0A.MPCM0 \ Multi-processor Communication
+$c1 constant UCSR0B \ USART0 Control and Status Regi
+ $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
+ c1 $80 bitmask: UCSR0B.RXCIE0 \ RX Complete Interrupt Enable
+ $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
+ c1 $40 bitmask: UCSR0B.TXCIE0 \ TX Complete Interrupt Enable
+ $20 constant UCSR0B_UDRIE0 \ USART Data Register Empty Inte
+ c1 $20 bitmask: UCSR0B.UDRIE0 \ USART Data Register Empty Inte
+ $10 constant UCSR0B_RXEN0 \ Receiver Enable
+ c1 $10 bitmask: UCSR0B.RXEN0 \ Receiver Enable
+ $8 constant UCSR0B_TXEN0 \ Transmitter Enable
+ c1 $8 bitmask: UCSR0B.TXEN0 \ Transmitter Enable
+ $4 constant UCSR0B_UCSZ02 \ Character Size
+ c1 $4 bitmask: UCSR0B.UCSZ02 \ Character Size
+ $2 constant UCSR0B_RXB80 \ Receive Data Bit 8
+ c1 $2 bitmask: UCSR0B.RXB80 \ Receive Data Bit 8
+ $1 constant UCSR0B_TXB80 \ Transmit Data Bit 8
+ c1 $1 bitmask: UCSR0B.TXB80 \ Transmit Data Bit 8
+$c2 constant UCSR0C \ USART0 Control and Status Regi
+ $c0 constant UCSR0C_UMSEL0 \ USART Mode Select
+ c2 $c0 bitmask: UCSR0C.UMSEL0 \ USART Mode Select
+ $30 constant UCSR0C_UPM0 \ Parity Mode
+ c2 $30 bitmask: UCSR0C.UPM0 \ Parity Mode
+ $8 constant UCSR0C_USBS0 \ Stop Bit Select
+ c2 $8 bitmask: UCSR0C.USBS0 \ Stop Bit Select
+ $6 constant UCSR0C_UCSZ0 \ Character Size
+ c2 $6 bitmask: UCSR0C.UCSZ0 \ Character Size
+ $1 constant UCSR0C_UCPOL0 \ Clock Polarity
+ c2 $1 bitmask: UCSR0C.UCPOL0 \ Clock Polarity
+$c4 constant UBRR0 \ USART0 Baud Rate Register Byt
diff --git a/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/USART0_SPI.frt b/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/USART0_SPI.frt
new file mode 100644
index 0000000..762a5f9
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/USART0_SPI.frt
@@ -0,0 +1,29 @@
+\ Generated automatically for atmega2564rfr2
+\ #require bitnames.frt
+
+\ USART0_SPI
+$c0 constant UCSR0A \ USART0 MSPIM Control and Statu
+ $80 constant UCSR0A_RXC0 \ USART Receive Complete
+ c0 $80 bitmask: UCSR0A.RXC0 \ USART Receive Complete
+ $40 constant UCSR0A_TXC0 \ USART Transmit Complete
+ c0 $40 bitmask: UCSR0A.TXC0 \ USART Transmit Complete
+ $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
+ c0 $20 bitmask: UCSR0A.UDRE0 \ USART Data Register Empty
+$c1 constant UCSR0B \ USART0 MSPIM Control and Statu
+ $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
+ c1 $80 bitmask: UCSR0B.RXCIE0 \ RX Complete Interrupt Enable
+ $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
+ c1 $40 bitmask: UCSR0B.TXCIE0 \ TX Complete Interrupt Enable
+ $20 constant UCSR0B_UDRIE0 \ USART Data Register Empty Inte
+ c1 $20 bitmask: UCSR0B.UDRIE0 \ USART Data Register Empty Inte
+ $10 constant UCSR0B_RXEN0 \ Receiver Enable
+ c1 $10 bitmask: UCSR0B.RXEN0 \ Receiver Enable
+ $8 constant UCSR0B_TXEN0 \ Transmitter Enable
+ c1 $8 bitmask: UCSR0B.TXEN0 \ Transmitter Enable
+$c2 constant UCSR0C \ USART0 MSPIM Control and Statu
+ $4 constant UCSR0C_UDORD0 \ Data Order
+ c2 $4 bitmask: UCSR0C.UDORD0 \ Data Order
+ $2 constant UCSR0C_UCPHA0 \ Clock Phase
+ c2 $2 bitmask: UCSR0C.UCPHA0 \ Clock Phase
+ $1 constant UCSR0C_UCPOL0 \ Clock Polarity
+ c2 $1 bitmask: UCSR0C.UCPOL0 \ Clock Polarity
diff --git a/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/USART1.frt b/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/USART1.frt
new file mode 100644
index 0000000..92c957e
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/USART1.frt
@@ -0,0 +1,51 @@
+\ Generated automatically for atmega2564rfr2
+\ #require bitnames.frt
+
+\ USART1
+$ce constant UDR1 \ USART1 I/O Data Register
+$c8 constant UCSR1A \ USART1 Control and Status Regi
+ $80 constant UCSR1A_RXC1 \ USART Receive Complete
+ c8 $80 bitmask: UCSR1A.RXC1 \ USART Receive Complete
+ $40 constant UCSR1A_TXC1 \ USART Transmit Complete
+ c8 $40 bitmask: UCSR1A.TXC1 \ USART Transmit Complete
+ $20 constant UCSR1A_UDRE1 \ USART Data Register Empty
+ c8 $20 bitmask: UCSR1A.UDRE1 \ USART Data Register Empty
+ $10 constant UCSR1A_FE1 \ Frame Error
+ c8 $10 bitmask: UCSR1A.FE1 \ Frame Error
+ $8 constant UCSR1A_DOR1 \ Data OverRun
+ c8 $8 bitmask: UCSR1A.DOR1 \ Data OverRun
+ $4 constant UCSR1A_UPE1 \ USART Parity Error
+ c8 $4 bitmask: UCSR1A.UPE1 \ USART Parity Error
+ $2 constant UCSR1A_U2X1 \ Double the USART Transmission
+ c8 $2 bitmask: UCSR1A.U2X1 \ Double the USART Transmission
+ $1 constant UCSR1A_MPCM1 \ Multi-processor Communication
+ c8 $1 bitmask: UCSR1A.MPCM1 \ Multi-processor Communication
+$c9 constant UCSR1B \ USART1 Control and Status Regi
+ $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable
+ c9 $80 bitmask: UCSR1B.RXCIE1 \ RX Complete Interrupt Enable
+ $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable
+ c9 $40 bitmask: UCSR1B.TXCIE1 \ TX Complete Interrupt Enable
+ $20 constant UCSR1B_UDRIE1 \ USART Data Register Empty Inte
+ c9 $20 bitmask: UCSR1B.UDRIE1 \ USART Data Register Empty Inte
+ $10 constant UCSR1B_RXEN1 \ Receiver Enable
+ c9 $10 bitmask: UCSR1B.RXEN1 \ Receiver Enable
+ $8 constant UCSR1B_TXEN1 \ Transmitter Enable
+ c9 $8 bitmask: UCSR1B.TXEN1 \ Transmitter Enable
+ $4 constant UCSR1B_UCSZ12 \ Character Size
+ c9 $4 bitmask: UCSR1B.UCSZ12 \ Character Size
+ $2 constant UCSR1B_RXB81 \ Receive Data Bit 8
+ c9 $2 bitmask: UCSR1B.RXB81 \ Receive Data Bit 8
+ $1 constant UCSR1B_TXB81 \ Transmit Data Bit 8
+ c9 $1 bitmask: UCSR1B.TXB81 \ Transmit Data Bit 8
+$ca constant UCSR1C \ USART1 Control and Status Regi
+ $c0 constant UCSR1C_UMSEL1 \ USART Mode Select
+ ca $c0 bitmask: UCSR1C.UMSEL1 \ USART Mode Select
+ $30 constant UCSR1C_UPM1 \ Parity Mode
+ ca $30 bitmask: UCSR1C.UPM1 \ Parity Mode
+ $8 constant UCSR1C_USBS1 \ Stop Bit Select
+ ca $8 bitmask: UCSR1C.USBS1 \ Stop Bit Select
+ $6 constant UCSR1C_UCSZ1 \ Character Size
+ ca $6 bitmask: UCSR1C.UCSZ1 \ Character Size
+ $1 constant UCSR1C_UCPOL1 \ Clock Polarity
+ ca $1 bitmask: UCSR1C.UCPOL1 \ Clock Polarity
+$cc constant UBRR1 \ USART1 Baud Rate Register Byt
diff --git a/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/USART1_SPI.frt b/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/USART1_SPI.frt
new file mode 100644
index 0000000..125d4f9
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/USART1_SPI.frt
@@ -0,0 +1,29 @@
+\ Generated automatically for atmega2564rfr2
+\ #require bitnames.frt
+
+\ USART1_SPI
+$c8 constant UCSR1A \ USART1 MSPIM Control and Statu
+ $80 constant UCSR1A_RXC1 \ USART Receive Complete
+ c8 $80 bitmask: UCSR1A.RXC1 \ USART Receive Complete
+ $40 constant UCSR1A_TXC1 \ USART Transmit Complete
+ c8 $40 bitmask: UCSR1A.TXC1 \ USART Transmit Complete
+ $20 constant UCSR1A_UDRE1 \ USART Data Register Empty
+ c8 $20 bitmask: UCSR1A.UDRE1 \ USART Data Register Empty
+$c9 constant UCSR1B \ USART1 MSPIM Control and Statu
+ $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable
+ c9 $80 bitmask: UCSR1B.RXCIE1 \ RX Complete Interrupt Enable
+ $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable
+ c9 $40 bitmask: UCSR1B.TXCIE1 \ TX Complete Interrupt Enable
+ $20 constant UCSR1B_UDRIE1 \ USART Data Register Empty Inte
+ c9 $20 bitmask: UCSR1B.UDRIE1 \ USART Data Register Empty Inte
+ $10 constant UCSR1B_RXEN1 \ Receiver Enable
+ c9 $10 bitmask: UCSR1B.RXEN1 \ Receiver Enable
+ $8 constant UCSR1B_TXEN1 \ Transmitter Enable
+ c9 $8 bitmask: UCSR1B.TXEN1 \ Transmitter Enable
+$ca constant UCSR1C \ USART1 MSPIM Control and Statu
+ $4 constant UCSR1C_UDORD1 \ Data Order
+ ca $4 bitmask: UCSR1C.UDORD1 \ Data Order
+ $2 constant UCSR1C_UCPHA1 \ Clock Phase
+ ca $2 bitmask: UCSR1C.UCPHA1 \ Clock Phase
+ $1 constant UCSR1C_UCPOL1 \ Clock Polarity
+ ca $1 bitmask: UCSR1C.UCPOL1 \ Clock Polarity
diff --git a/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/WATCHDOG.frt b/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/WATCHDOG.frt
new file mode 100644
index 0000000..662a666
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/WATCHDOG.frt
@@ -0,0 +1,15 @@
+\ Generated automatically for atmega2564rfr2
+\ #require bitnames.frt
+
+\ WATCHDOG
+$60 constant WDTCSR \ Watchdog Timer Control Registe
+ $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Fla
+ 60 $80 bitmask: WDTCSR.WDIF \ Watchdog Timeout Interrupt Fla
+ $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Ena
+ 60 $40 bitmask: WDTCSR.WDIE \ Watchdog Timeout Interrupt Ena
+ $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
+ 60 $27 bitmask: WDTCSR.WDP \ Watchdog Timer Prescaler Bits
+ $10 constant WDTCSR_WDCE \ Watchdog Change Enable
+ 60 $10 bitmask: WDTCSR.WDCE \ Watchdog Change Enable
+ $8 constant WDTCSR_WDE \ Watch Dog Enable
+ 60 $8 bitmask: WDTCSR.WDE \ Watch Dog Enable
diff --git a/amforth-6.5/avr8/devices/atmega2564rfr2/device.asm b/amforth-6.5/avr8/devices/atmega2564rfr2/device.asm
new file mode 100644
index 0000000..41c6805
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega2564rfr2/device.asm
@@ -0,0 +1,166 @@
+; Generated Automatically
+
+.nolist
+ include "m2564RFR2def.inc"
+.list
+FLASHSTART = 0
+FLASHSIZE = 262144
+RAMEND = 33280
+IRAMSTART = 512
+IRAMSIZE = 32768
+EEPROMSIZE = 8192
+; Interrupt Vectors
+.overlap
+.org 2
+ rcall isr ; External Interrupt Request 0
+.org 4
+ rcall isr ; External Interrupt Request 1
+.org 6
+ rcall isr ; External Interrupt Request 2
+.org 8
+ rcall isr ; External Interrupt Request 3
+.org 10
+ rcall isr ; External Interrupt Request 4
+.org 12
+ rcall isr ; External Interrupt Request 5
+.org 14
+ rcall isr ; External Interrupt Request 6
+.org 16
+ rcall isr ; External Interrupt Request 7
+.org 18
+ rcall isr ; Pin Change Interrupt Request 0
+.org 20
+ rcall isr ; Pin Change Interrupt Request 1
+.org 22
+ rcall isr ; Pin Change Interrupt Request 2
+.org 24
+ rcall isr ; Watchdog Time-out Interrupt
+.org 26
+ rcall isr ; Timer/Counter2 Compare Match A
+.org 28
+ rcall isr ; Timer/Counter2 Compare Match B
+.org 30
+ rcall isr ; Timer/Counter2 Overflow
+.org 32
+ rcall isr ; Timer/Counter1 Capture Event
+.org 34
+ rcall isr ; Timer/Counter1 Compare Match A
+.org 36
+ rcall isr ; Timer/Counter1 Compare Match B
+.org 38
+ rcall isr ; Timer/Counter1 Compare Match C
+.org 40
+ rcall isr ; Timer/Counter1 Overflow
+.org 42
+ rcall isr ; Timer/Counter0 Compare Match A
+.org 44
+ rcall isr ; Timer/Counter0 Compare Match B
+.org 46
+ rcall isr ; Timer/Counter0 Overflow
+.org 48
+ rcall isr ; SPI Serial Transfer Complete
+.org 50
+ rcall isr ; USART0, Rx Complete
+.org 52
+ rcall isr ; USART0 Data register Empty
+.org 54
+ rcall isr ; USART0, Tx Complete
+.org 56
+ rcall isr ; Analog Comparator
+.org 58
+ rcall isr ; ADC Conversion Complete
+.org 60
+ rcall isr ; EEPROM Ready
+.org 62
+ rcall isr ; Timer/Counter3 Capture Event
+.org 64
+ rcall isr ; Timer/Counter3 Compare Match A
+.org 66
+ rcall isr ; Timer/Counter3 Compare Match B
+.org 68
+ rcall isr ; Timer/Counter3 Compare Match C
+.org 70
+ rcall isr ; Timer/Counter3 Overflow
+.org 72
+ rcall isr ; USART1, Rx Complete
+.org 74
+ rcall isr ; USART1 Data register Empty
+.org 76
+ rcall isr ; USART1, Tx Complete
+.org 78
+ rcall isr ; 2-wire Serial Interface
+.org 80
+ rcall isr ; Store Program Memory Read
+.org 82
+ rcall isr ; Timer/Counter4 Capture Event
+.org 84
+ rcall isr ; Timer/Counter4 Compare Match A
+.org 86
+ rcall isr ; Timer/Counter4 Compare Match B
+.org 88
+ rcall isr ; Timer/Counter4 Compare Match C
+.org 90
+ rcall isr ; Timer/Counter4 Overflow
+.org 92
+ rcall isr ; Timer/Counter5 Capture Event
+.org 94
+ rcall isr ; Timer/Counter5 Compare Match A
+.org 96
+ rcall isr ; Timer/Counter5 Compare Match B
+.org 98
+ rcall isr ; Timer/Counter5 Compare Match C
+.org 100
+ rcall isr ; Timer/Counter5 Overflow
+.org 102
+ rcall isr ; USART2, Rx Complete
+.org 104
+ rcall isr ; USART2 Data register Empty
+.org 106
+ rcall isr ; USART2, Tx Complete
+.org 108
+ rcall isr ; USART3, Rx Complete
+.org 110
+ rcall isr ; USART3 Data register Empty
+.org 112
+ rcall isr ; USART3, Tx Complete
+.org 114
+ rcall isr ; TRX24 - PLL lock interrupt
+.org 116
+ rcall isr ; TRX24 - PLL unlock interrupt
+.org 118
+ rcall isr ; TRX24 - Receive start interrupt
+.org 120
+ rcall isr ; TRX24 - RX_END interrupt
+.org 122
+ rcall isr ; TRX24 - CCA/ED done interrupt
+.org 124
+ rcall isr ; TRX24 - XAH - AMI
+.org 126
+ rcall isr ; TRX24 - TX_END interrupt
+.org 128
+ rcall isr ; TRX24 AWAKE - tranceiver is reaching state TRX_OFF
+.org 130
+ rcall isr ; Symbol counter - compare match 1 interrupt
+.org 132
+ rcall isr ; Symbol counter - compare match 2 interrupt
+.org 134
+ rcall isr ; Symbol counter - compare match 3 interrupt
+.org 136
+ rcall isr ; Symbol counter - overflow interrupt
+.org 138
+ rcall isr ; Symbol counter - backoff interrupt
+.org 140
+ rcall isr ; AES engine ready interrupt
+.org 142
+ rcall isr ; Battery monitor indicates supply voltage below threshold
+.org 144
+ rcall isr ; TRX24 TX start interrupt
+.org 146
+ rcall isr ; Address match interrupt of address filter 0
+.org 148
+ rcall isr ; Address match interrupt of address filter 1
+.org 150
+ rcall isr ; Address match interrupt of address filter 2
+.org 152
+ rcall isr ; Address match interrupt of address filter 3
+.nooverlap
diff --git a/amforth-6.5/avr8/devices/atmega2564rfr2/device.frt b/amforth-6.5/avr8/devices/atmega2564rfr2/device.frt
new file mode 100644
index 0000000..4ff689f
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega2564rfr2/device.frt
@@ -0,0 +1,1753 @@
+\ Generated Automatically
+
+\ Interrupt Vectors
+#2 constant INT0Addr \ External Interrupt Request 0
+#4 constant INT1Addr \ External Interrupt Request 1
+#6 constant INT2Addr \ External Interrupt Request 2
+#8 constant INT3Addr \ External Interrupt Request 3
+#10 constant INT4Addr \ External Interrupt Request 4
+#12 constant INT5Addr \ External Interrupt Request 5
+#14 constant INT6Addr \ External Interrupt Request 6
+#16 constant INT7Addr \ External Interrupt Request 7
+#18 constant PCINT0Addr \ Pin Change Interrupt Request 0
+#20 constant PCINT1Addr \ Pin Change Interrupt Request 1
+#22 constant PCINT2Addr \ Pin Change Interrupt Request 2
+#24 constant WDTAddr \ Watchdog Time-out Interrupt
+#26 constant TIMER2_COMPAAddr \ Timer/Counter2 Compare Match A
+#28 constant TIMER2_COMPBAddr \ Timer/Counter2 Compare Match B
+#30 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
+#32 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+#34 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
+#36 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
+#38 constant TIMER1_COMPCAddr \ Timer/Counter1 Compare Match C
+#40 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+#42 constant TIMER0_COMPAAddr \ Timer/Counter0 Compare Match A
+#44 constant TIMER0_COMPBAddr \ Timer/Counter0 Compare Match B
+#46 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
+#48 constant SPI_STCAddr \ SPI Serial Transfer Complete
+#50 constant USART0_RXAddr \ USART0, Rx Complete
+#52 constant USART0_UDREAddr \ USART0 Data register Empty
+#54 constant USART0_TXAddr \ USART0, Tx Complete
+#56 constant ANALOG_COMPAddr \ Analog Comparator
+#58 constant ADCAddr \ ADC Conversion Complete
+#60 constant EE_READYAddr \ EEPROM Ready
+#62 constant TIMER3_CAPTAddr \ Timer/Counter3 Capture Event
+#64 constant TIMER3_COMPAAddr \ Timer/Counter3 Compare Match A
+#66 constant TIMER3_COMPBAddr \ Timer/Counter3 Compare Match B
+#68 constant TIMER3_COMPCAddr \ Timer/Counter3 Compare Match C
+#70 constant TIMER3_OVFAddr \ Timer/Counter3 Overflow
+#72 constant USART1_RXAddr \ USART1, Rx Complete
+#74 constant USART1_UDREAddr \ USART1 Data register Empty
+#76 constant USART1_TXAddr \ USART1, Tx Complete
+#78 constant TWIAddr \ 2-wire Serial Interface
+#80 constant SPM_READYAddr \ Store Program Memory Read
+#82 constant TIMER4_CAPTAddr \ Timer/Counter4 Capture Event
+#84 constant TIMER4_COMPAAddr \ Timer/Counter4 Compare Match A
+#86 constant TIMER4_COMPBAddr \ Timer/Counter4 Compare Match B
+#88 constant TIMER4_COMPCAddr \ Timer/Counter4 Compare Match C
+#90 constant TIMER4_OVFAddr \ Timer/Counter4 Overflow
+#92 constant TIMER5_CAPTAddr \ Timer/Counter5 Capture Event
+#94 constant TIMER5_COMPAAddr \ Timer/Counter5 Compare Match A
+#96 constant TIMER5_COMPBAddr \ Timer/Counter5 Compare Match B
+#98 constant TIMER5_COMPCAddr \ Timer/Counter5 Compare Match C
+#100 constant TIMER5_OVFAddr \ Timer/Counter5 Overflow
+#102 constant USART2_RXAddr \ USART2, Rx Complete
+#104 constant USART2_UDREAddr \ USART2 Data register Empty
+#106 constant USART2_TXAddr \ USART2, Tx Complete
+#108 constant USART3_RXAddr \ USART3, Rx Complete
+#110 constant USART3_UDREAddr \ USART3 Data register Empty
+#112 constant USART3_TXAddr \ USART3, Tx Complete
+#114 constant TRX24_PLL_LOCKAddr \ TRX24 - PLL lock interrupt
+#116 constant TRX24_PLL_UNLOCKAddr \ TRX24 - PLL unlock interrupt
+#118 constant TRX24_RX_STARTAddr \ TRX24 - Receive start interrupt
+#120 constant TRX24_RX_ENDAddr \ TRX24 - RX_END interrupt
+#122 constant TRX24_CCA_ED_DONEAddr \ TRX24 - CCA/ED done interrupt
+#124 constant TRX24_XAH_AMIAddr \ TRX24 - XAH - AMI
+#126 constant TRX24_TX_ENDAddr \ TRX24 - TX_END interrupt
+#128 constant TRX24_AWAKEAddr \ TRX24 AWAKE - tranceiver is reaching state TRX_OFF
+#130 constant SCNT_CMP1Addr \ Symbol counter - compare match 1 interrupt
+#132 constant SCNT_CMP2Addr \ Symbol counter - compare match 2 interrupt
+#134 constant SCNT_CMP3Addr \ Symbol counter - compare match 3 interrupt
+#136 constant SCNT_OVFLAddr \ Symbol counter - overflow interrupt
+#138 constant SCNT_BACKOFFAddr \ Symbol counter - backoff interrupt
+#140 constant AES_READYAddr \ AES engine ready interrupt
+#142 constant BAT_LOWAddr \ Battery monitor indicates supply voltage below threshold
+#144 constant TRX24_TX_STARTAddr \ TRX24 TX start interrupt
+#146 constant TRX24_AMI0Addr \ Address match interrupt of address filter 0
+#148 constant TRX24_AMI1Addr \ Address match interrupt of address filter 1
+#150 constant TRX24_AMI2Addr \ Address match interrupt of address filter 2
+#152 constant TRX24_AMI3Addr \ Address match interrupt of address filter 3
+\ ANALOG_COMPARATOR
+$7b constant ADCSRB \ ADC Control and Status Registe
+ $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer
+ 7b $40 bitmask: ADCSRB.ACME \ Analog Comparator Multiplexer
+$50 constant ACSR \ Analog Comparator Control And
+ $80 constant ACSR_ACD \ Analog Comparator Disable
+ 50 $80 bitmask: ACSR.ACD \ Analog Comparator Disable
+ $40 constant ACSR_ACBG \ Analog Comparator Bandgap Sele
+ 50 $40 bitmask: ACSR.ACBG \ Analog Comparator Bandgap Sele
+ $20 constant ACSR_ACO \ Analog Compare Output
+ 50 $20 bitmask: ACSR.ACO \ Analog Compare Output
+ $10 constant ACSR_ACI \ Analog Comparator Interrupt Fl
+ 50 $10 bitmask: ACSR.ACI \ Analog Comparator Interrupt Fl
+ $8 constant ACSR_ACIE \ Analog Comparator Interrupt En
+ 50 $8 bitmask: ACSR.ACIE \ Analog Comparator Interrupt En
+ $4 constant ACSR_ACIC \ Analog Comparator Input Captur
+ 50 $4 bitmask: ACSR.ACIC \ Analog Comparator Input Captur
+ $3 constant ACSR_ACIS \ Analog Comparator Interrupt Mo
+ 50 $3 bitmask: ACSR.ACIS \ Analog Comparator Interrupt Mo
+$7f constant DIDR1 \ Digital Input Disable Register
+ $2 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
+ 7f $2 bitmask: DIDR1.AIN1D \ AIN1 Digital Input Disable
+ $1 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
+ 7f $1 bitmask: DIDR1.AIN0D \ AIN0 Digital Input Disable
+\ USART0
+$c6 constant UDR0 \ USART0 I/O Data Register
+$c0 constant UCSR0A \ USART0 Control and Status Regi
+ $80 constant UCSR0A_RXC0 \ USART Receive Complete
+ c0 $80 bitmask: UCSR0A.RXC0 \ USART Receive Complete
+ $40 constant UCSR0A_TXC0 \ USART Transmit Complete
+ c0 $40 bitmask: UCSR0A.TXC0 \ USART Transmit Complete
+ $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
+ c0 $20 bitmask: UCSR0A.UDRE0 \ USART Data Register Empty
+ $10 constant UCSR0A_FE0 \ Frame Error
+ c0 $10 bitmask: UCSR0A.FE0 \ Frame Error
+ $8 constant UCSR0A_DOR0 \ Data OverRun
+ c0 $8 bitmask: UCSR0A.DOR0 \ Data OverRun
+ $4 constant UCSR0A_UPE0 \ USART Parity Error
+ c0 $4 bitmask: UCSR0A.UPE0 \ USART Parity Error
+ $2 constant UCSR0A_U2X0 \ Double the USART Transmission
+ c0 $2 bitmask: UCSR0A.U2X0 \ Double the USART Transmission
+ $1 constant UCSR0A_MPCM0 \ Multi-processor Communication
+ c0 $1 bitmask: UCSR0A.MPCM0 \ Multi-processor Communication
+$c1 constant UCSR0B \ USART0 Control and Status Regi
+ $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
+ c1 $80 bitmask: UCSR0B.RXCIE0 \ RX Complete Interrupt Enable
+ $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
+ c1 $40 bitmask: UCSR0B.TXCIE0 \ TX Complete Interrupt Enable
+ $20 constant UCSR0B_UDRIE0 \ USART Data Register Empty Inte
+ c1 $20 bitmask: UCSR0B.UDRIE0 \ USART Data Register Empty Inte
+ $10 constant UCSR0B_RXEN0 \ Receiver Enable
+ c1 $10 bitmask: UCSR0B.RXEN0 \ Receiver Enable
+ $8 constant UCSR0B_TXEN0 \ Transmitter Enable
+ c1 $8 bitmask: UCSR0B.TXEN0 \ Transmitter Enable
+ $4 constant UCSR0B_UCSZ02 \ Character Size
+ c1 $4 bitmask: UCSR0B.UCSZ02 \ Character Size
+ $2 constant UCSR0B_RXB80 \ Receive Data Bit 8
+ c1 $2 bitmask: UCSR0B.RXB80 \ Receive Data Bit 8
+ $1 constant UCSR0B_TXB80 \ Transmit Data Bit 8
+ c1 $1 bitmask: UCSR0B.TXB80 \ Transmit Data Bit 8
+$c2 constant UCSR0C \ USART0 Control and Status Regi
+ $c0 constant UCSR0C_UMSEL0 \ USART Mode Select
+ c2 $c0 bitmask: UCSR0C.UMSEL0 \ USART Mode Select
+ $30 constant UCSR0C_UPM0 \ Parity Mode
+ c2 $30 bitmask: UCSR0C.UPM0 \ Parity Mode
+ $8 constant UCSR0C_USBS0 \ Stop Bit Select
+ c2 $8 bitmask: UCSR0C.USBS0 \ Stop Bit Select
+ $6 constant UCSR0C_UCSZ0 \ Character Size
+ c2 $6 bitmask: UCSR0C.UCSZ0 \ Character Size
+ $1 constant UCSR0C_UCPOL0 \ Clock Polarity
+ c2 $1 bitmask: UCSR0C.UCPOL0 \ Clock Polarity
+$c4 constant UBRR0 \ USART0 Baud Rate Register Byt
+\ USART1
+$ce constant UDR1 \ USART1 I/O Data Register
+$c8 constant UCSR1A \ USART1 Control and Status Regi
+ $80 constant UCSR1A_RXC1 \ USART Receive Complete
+ c8 $80 bitmask: UCSR1A.RXC1 \ USART Receive Complete
+ $40 constant UCSR1A_TXC1 \ USART Transmit Complete
+ c8 $40 bitmask: UCSR1A.TXC1 \ USART Transmit Complete
+ $20 constant UCSR1A_UDRE1 \ USART Data Register Empty
+ c8 $20 bitmask: UCSR1A.UDRE1 \ USART Data Register Empty
+ $10 constant UCSR1A_FE1 \ Frame Error
+ c8 $10 bitmask: UCSR1A.FE1 \ Frame Error
+ $8 constant UCSR1A_DOR1 \ Data OverRun
+ c8 $8 bitmask: UCSR1A.DOR1 \ Data OverRun
+ $4 constant UCSR1A_UPE1 \ USART Parity Error
+ c8 $4 bitmask: UCSR1A.UPE1 \ USART Parity Error
+ $2 constant UCSR1A_U2X1 \ Double the USART Transmission
+ c8 $2 bitmask: UCSR1A.U2X1 \ Double the USART Transmission
+ $1 constant UCSR1A_MPCM1 \ Multi-processor Communication
+ c8 $1 bitmask: UCSR1A.MPCM1 \ Multi-processor Communication
+$c9 constant UCSR1B \ USART1 Control and Status Regi
+ $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable
+ c9 $80 bitmask: UCSR1B.RXCIE1 \ RX Complete Interrupt Enable
+ $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable
+ c9 $40 bitmask: UCSR1B.TXCIE1 \ TX Complete Interrupt Enable
+ $20 constant UCSR1B_UDRIE1 \ USART Data Register Empty Inte
+ c9 $20 bitmask: UCSR1B.UDRIE1 \ USART Data Register Empty Inte
+ $10 constant UCSR1B_RXEN1 \ Receiver Enable
+ c9 $10 bitmask: UCSR1B.RXEN1 \ Receiver Enable
+ $8 constant UCSR1B_TXEN1 \ Transmitter Enable
+ c9 $8 bitmask: UCSR1B.TXEN1 \ Transmitter Enable
+ $4 constant UCSR1B_UCSZ12 \ Character Size
+ c9 $4 bitmask: UCSR1B.UCSZ12 \ Character Size
+ $2 constant UCSR1B_RXB81 \ Receive Data Bit 8
+ c9 $2 bitmask: UCSR1B.RXB81 \ Receive Data Bit 8
+ $1 constant UCSR1B_TXB81 \ Transmit Data Bit 8
+ c9 $1 bitmask: UCSR1B.TXB81 \ Transmit Data Bit 8
+$ca constant UCSR1C \ USART1 Control and Status Regi
+ $c0 constant UCSR1C_UMSEL1 \ USART Mode Select
+ ca $c0 bitmask: UCSR1C.UMSEL1 \ USART Mode Select
+ $30 constant UCSR1C_UPM1 \ Parity Mode
+ ca $30 bitmask: UCSR1C.UPM1 \ Parity Mode
+ $8 constant UCSR1C_USBS1 \ Stop Bit Select
+ ca $8 bitmask: UCSR1C.USBS1 \ Stop Bit Select
+ $6 constant UCSR1C_UCSZ1 \ Character Size
+ ca $6 bitmask: UCSR1C.UCSZ1 \ Character Size
+ $1 constant UCSR1C_UCPOL1 \ Clock Polarity
+ ca $1 bitmask: UCSR1C.UCPOL1 \ Clock Polarity
+$cc constant UBRR1 \ USART1 Baud Rate Register Byt
+\ TWI
+$bd constant TWAMR \ TWI (Slave) Address Mask Regis
+ $fe constant TWAMR_TWAM \ TWI Address Mask
+ bd $fe bitmask: TWAMR.TWAM \ TWI Address Mask
+ $1 constant TWAMR_Res \ Reserved Bit
+ bd $1 bitmask: TWAMR.Res \ Reserved Bit
+$b8 constant TWBR \ TWI Bit Rate Register
+$bc constant TWCR \ TWI Control Register
+ $80 constant TWCR_TWINT \ TWI Interrupt Flag
+ bc $80 bitmask: TWCR.TWINT \ TWI Interrupt Flag
+ $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
+ bc $40 bitmask: TWCR.TWEA \ TWI Enable Acknowledge Bit
+ $20 constant TWCR_TWSTA \ TWI START Condition Bit
+ bc $20 bitmask: TWCR.TWSTA \ TWI START Condition Bit
+ $10 constant TWCR_TWSTO \ TWI STOP Condition Bit
+ bc $10 bitmask: TWCR.TWSTO \ TWI STOP Condition Bit
+ $8 constant TWCR_TWWC \ TWI Write Collision Flag
+ bc $8 bitmask: TWCR.TWWC \ TWI Write Collision Flag
+ $4 constant TWCR_TWEN \ TWI Enable Bit
+ bc $4 bitmask: TWCR.TWEN \ TWI Enable Bit
+ $2 constant TWCR_Res \ Reserved Bit
+ bc $2 bitmask: TWCR.Res \ Reserved Bit
+ $1 constant TWCR_TWIE \ TWI Interrupt Enable
+ bc $1 bitmask: TWCR.TWIE \ TWI Interrupt Enable
+$b9 constant TWSR \ TWI Status Register
+ $f8 constant TWSR_TWS \ TWI Status
+ b9 $f8 bitmask: TWSR.TWS \ TWI Status
+ $4 constant TWSR_Res \ Reserved Bit
+ b9 $4 bitmask: TWSR.Res \ Reserved Bit
+ $3 constant TWSR_TWPS \ TWI Prescaler Bits
+ b9 $3 bitmask: TWSR.TWPS \ TWI Prescaler Bits
+$bb constant TWDR \ TWI Data Register
+$ba constant TWAR \ TWI (Slave) Address Register
+ $fe constant TWAR_TWA \ TWI (Slave) Address
+ ba $fe bitmask: TWAR.TWA \ TWI (Slave) Address
+ $1 constant TWAR_TWGCE \ TWI General Call Recognition E
+ ba $1 bitmask: TWAR.TWGCE \ TWI General Call Recognition E
+\ SPI
+$4c constant SPCR \ SPI Control Register
+ $80 constant SPCR_SPIE \ SPI Interrupt Enable
+ 4c $80 bitmask: SPCR.SPIE \ SPI Interrupt Enable
+ $40 constant SPCR_SPE \ SPI Enable
+ 4c $40 bitmask: SPCR.SPE \ SPI Enable
+ $20 constant SPCR_DORD \ Data Order
+ 4c $20 bitmask: SPCR.DORD \ Data Order
+ $10 constant SPCR_MSTR \ Master/Slave Select
+ 4c $10 bitmask: SPCR.MSTR \ Master/Slave Select
+ $8 constant SPCR_CPOL \ Clock polarity
+ 4c $8 bitmask: SPCR.CPOL \ Clock polarity
+ $4 constant SPCR_CPHA \ Clock Phase
+ 4c $4 bitmask: SPCR.CPHA \ Clock Phase
+ $3 constant SPCR_SPR \ SPI Clock Rate Select 1 and 0
+ 4c $3 bitmask: SPCR.SPR \ SPI Clock Rate Select 1 and 0
+$4d constant SPSR \ SPI Status Register
+ $80 constant SPSR_SPIF \ SPI Interrupt Flag
+ 4d $80 bitmask: SPSR.SPIF \ SPI Interrupt Flag
+ $40 constant SPSR_WCOL \ Write Collision Flag
+ 4d $40 bitmask: SPSR.WCOL \ Write Collision Flag
+ $3e constant SPSR_Res \ Reserved
+ 4d $3e bitmask: SPSR.Res \ Reserved
+ $1 constant SPSR_SPI2X \ Double SPI Speed Bit
+ 4d $1 bitmask: SPSR.SPI2X \ Double SPI Speed Bit
+$4e constant SPDR \ SPI Data Register
+\ PORTA
+$22 constant PORTA \ Port A Data Register
+$21 constant DDRA \ Port A Data Direction Register
+$20 constant PINA \ Port A Input Pins Address
+\ PORTB
+$25 constant PORTB \ Port B Data Register
+$24 constant DDRB \ Port B Data Direction Register
+$23 constant PINB \ Port B Input Pins Address
+\ PORTC
+$28 constant PORTC \ Port C Data Register
+$27 constant DDRC \ Port C Data Direction Register
+$26 constant PINC \ Port C Input Pins Address
+\ PORTD
+$2b constant PORTD \ Port D Data Register
+$2a constant DDRD \ Port D Data Direction Register
+$29 constant PIND \ Port D Input Pins Address
+\ PORTE
+$2e constant PORTE \ Port E Data Register
+$2d constant DDRE \ Port E Data Direction Register
+$2c constant PINE \ Port E Input Pins Address
+\ PORTF
+$31 constant PORTF \ Port F Data Register
+$30 constant DDRF \ Port F Data Direction Register
+$2f constant PINF \ Port F Input Pins Address
+\ PORTG
+$34 constant PORTG \ Port G Data Register
+$33 constant DDRG \ Port G Data Direction Register
+$32 constant PING \ Port G Input Pins Address
+\ TIMER_COUNTER_0
+$48 constant OCR0B \ Timer/Counter0 Output Compare
+$47 constant OCR0A \ Timer/Counter0 Output Compare
+$46 constant TCNT0 \ Timer/Counter0 Register
+$45 constant TCCR0B \ Timer/Counter0 Control Registe
+ $80 constant TCCR0B_FOC0A \ Force Output Compare A
+ 45 $80 bitmask: TCCR0B.FOC0A \ Force Output Compare A
+ $40 constant TCCR0B_FOC0B \ Force Output Compare B
+ 45 $40 bitmask: TCCR0B.FOC0B \ Force Output Compare B
+ $30 constant TCCR0B_Res \ Reserved Bit
+ 45 $30 bitmask: TCCR0B.Res \ Reserved Bit
+ $8 constant TCCR0B_WGM02 \
+ 45 $8 bitmask: TCCR0B.WGM02 \
+ $7 constant TCCR0B_CS0 \ Clock Select
+ 45 $7 bitmask: TCCR0B.CS0 \ Clock Select
+$44 constant TCCR0A \ Timer/Counter0 Control Registe
+ $c0 constant TCCR0A_COM0A \ Compare Match Output A Mode
+ 44 $c0 bitmask: TCCR0A.COM0A \ Compare Match Output A Mode
+ $30 constant TCCR0A_COM0B \ Compare Match Output B Mode
+ 44 $30 bitmask: TCCR0A.COM0B \ Compare Match Output B Mode
+ $c constant TCCR0A_Res \ Reserved Bit
+ 44 $c bitmask: TCCR0A.Res \ Reserved Bit
+ $3 constant TCCR0A_WGM0 \ Waveform Generation Mode
+ 44 $3 bitmask: TCCR0A.WGM0 \ Waveform Generation Mode
+$6e constant TIMSK0 \ Timer/Counter0 Interrupt Mask
+ $f8 constant TIMSK0_Res \ Reserved
+ 6e $f8 bitmask: TIMSK0.Res \ Reserved
+ $4 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare
+ 6e $4 bitmask: TIMSK0.OCIE0B \ Timer/Counter0 Output Compare
+ $2 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare
+ 6e $2 bitmask: TIMSK0.OCIE0A \ Timer/Counter0 Output Compare
+ $1 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interr
+ 6e $1 bitmask: TIMSK0.TOIE0 \ Timer/Counter0 Overflow Interr
+$35 constant TIFR0 \ Timer/Counter0 Interrupt Flag
+ $f8 constant TIFR0_Res \ Reserved
+ 35 $f8 bitmask: TIFR0.Res \ Reserved
+ $4 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare
+ 35 $4 bitmask: TIFR0.OCF0B \ Timer/Counter0 Output Compare
+ $2 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare
+ 35 $2 bitmask: TIFR0.OCF0A \ Timer/Counter0 Output Compare
+ $1 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
+ 35 $1 bitmask: TIFR0.TOV0 \ Timer/Counter0 Overflow Flag
+$43 constant GTCCR \ General Timer/Counter Control
+ $80 constant GTCCR_TSM \ Timer/Counter Synchronization
+ 43 $80 bitmask: GTCCR.TSM \ Timer/Counter Synchronization
+ $7c constant GTCCR_Res \ Reserved
+ 43 $7c bitmask: GTCCR.Res \ Reserved
+ $2 constant GTCCR_PSRASY \ Prescaler Reset Timer/Counter2
+ 43 $2 bitmask: GTCCR.PSRASY \ Prescaler Reset Timer/Counter2
+ $1 constant GTCCR_PSRSYNC \ Prescaler Reset for Synchronou
+ 43 $1 bitmask: GTCCR.PSRSYNC \ Prescaler Reset for Synchronou
+\ TIMER_COUNTER_2
+$70 constant TIMSK2 \ Timer/Counter Interrupt Mask r
+ $f8 constant TIMSK2_Res \ Reserved Bit
+ 70 $f8 bitmask: TIMSK2.Res \ Reserved Bit
+ $4 constant TIMSK2_OCIE2B \ Timer/Counter2 Output Compare
+ 70 $4 bitmask: TIMSK2.OCIE2B \ Timer/Counter2 Output Compare
+ $2 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare
+ 70 $2 bitmask: TIMSK2.OCIE2A \ Timer/Counter2 Output Compare
+ $1 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interr
+ 70 $1 bitmask: TIMSK2.TOIE2 \ Timer/Counter2 Overflow Interr
+$37 constant TIFR2 \ Timer/Counter Interrupt Flag R
+ $f8 constant TIFR2_Res \ Reserved Bit
+ 37 $f8 bitmask: TIFR2.Res \ Reserved Bit
+ $4 constant TIFR2_OCF2B \ Output Compare Flag 2 B
+ 37 $4 bitmask: TIFR2.OCF2B \ Output Compare Flag 2 B
+ $2 constant TIFR2_OCF2A \ Output Compare Flag 2 A
+ 37 $2 bitmask: TIFR2.OCF2A \ Output Compare Flag 2 A
+ $1 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
+ 37 $1 bitmask: TIFR2.TOV2 \ Timer/Counter2 Overflow Flag
+$b0 constant TCCR2A \ Timer/Counter2 Control Registe
+ $c0 constant TCCR2A_COM2A \ Compare Match Output A Mode
+ b0 $c0 bitmask: TCCR2A.COM2A \ Compare Match Output A Mode
+ $30 constant TCCR2A_COM2B \ Compare Match Output B Mode
+ b0 $30 bitmask: TCCR2A.COM2B \ Compare Match Output B Mode
+ $c constant TCCR2A_Res \ Reserved
+ b0 $c bitmask: TCCR2A.Res \ Reserved
+ $3 constant TCCR2A_WGM2 \ Waveform Generation Mode
+ b0 $3 bitmask: TCCR2A.WGM2 \ Waveform Generation Mode
+$b1 constant TCCR2B \ Timer/Counter2 Control Registe
+ $80 constant TCCR2B_FOC2A \ Force Output Compare A
+ b1 $80 bitmask: TCCR2B.FOC2A \ Force Output Compare A
+ $40 constant TCCR2B_FOC2B \ Force Output Compare B
+ b1 $40 bitmask: TCCR2B.FOC2B \ Force Output Compare B
+ $30 constant TCCR2B_Res \ Reserved
+ b1 $30 bitmask: TCCR2B.Res \ Reserved
+ $8 constant TCCR2B_WGM22 \ Waveform Generation Mode
+ b1 $8 bitmask: TCCR2B.WGM22 \ Waveform Generation Mode
+ $7 constant TCCR2B_CS2 \ Clock Select
+ b1 $7 bitmask: TCCR2B.CS2 \ Clock Select
+$b2 constant TCNT2 \ Timer/Counter2
+$b4 constant OCR2B \ Timer/Counter2 Output Compare
+$b3 constant OCR2A \ Timer/Counter2 Output Compare
+$b6 constant ASSR \ Asynchronous Status Register
+ $80 constant ASSR_EXCLKAMR \ Enable External Clock Input fo
+ b6 $80 bitmask: ASSR.EXCLKAMR \ Enable External Clock Input fo
+ $40 constant ASSR_EXCLK \ Enable External Clock Input
+ b6 $40 bitmask: ASSR.EXCLK \ Enable External Clock Input
+ $20 constant ASSR_AS2 \ Timer/Counter2 Asynchronous Mo
+ b6 $20 bitmask: ASSR.AS2 \ Timer/Counter2 Asynchronous Mo
+ $10 constant ASSR_TCN2UB \ Timer/Counter2 Update Busy
+ b6 $10 bitmask: ASSR.TCN2UB \ Timer/Counter2 Update Busy
+ $8 constant ASSR_OCR2AUB \ Timer/Counter2 Output Compare
+ b6 $8 bitmask: ASSR.OCR2AUB \ Timer/Counter2 Output Compare
+ $4 constant ASSR_OCR2BUB \ Timer/Counter2 Output Compare
+ b6 $4 bitmask: ASSR.OCR2BUB \ Timer/Counter2 Output Compare
+ $2 constant ASSR_TCR2AUB \ Timer/Counter2 Control Registe
+ b6 $2 bitmask: ASSR.TCR2AUB \ Timer/Counter2 Control Registe
+ $1 constant ASSR_TCR2BUB \ Timer/Counter2 Control Registe
+ b6 $1 bitmask: ASSR.TCR2BUB \ Timer/Counter2 Control Registe
+$43 constant GTCCR \ General Timer Counter Control
+ $80 constant GTCCR_TSM \ Timer/Counter Synchronization
+ 43 $80 bitmask: GTCCR.TSM \ Timer/Counter Synchronization
+ $2 constant GTCCR_PSRASY \ Prescaler Reset Timer/Counter2
+ 43 $2 bitmask: GTCCR.PSRASY \ Prescaler Reset Timer/Counter2
+\ WATCHDOG
+$60 constant WDTCSR \ Watchdog Timer Control Registe
+ $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Fla
+ 60 $80 bitmask: WDTCSR.WDIF \ Watchdog Timeout Interrupt Fla
+ $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Ena
+ 60 $40 bitmask: WDTCSR.WDIE \ Watchdog Timeout Interrupt Ena
+ $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
+ 60 $27 bitmask: WDTCSR.WDP \ Watchdog Timer Prescaler Bits
+ $10 constant WDTCSR_WDCE \ Watchdog Change Enable
+ 60 $10 bitmask: WDTCSR.WDCE \ Watchdog Change Enable
+ $8 constant WDTCSR_WDE \ Watch Dog Enable
+ 60 $8 bitmask: WDTCSR.WDE \ Watch Dog Enable
+\ TIMER_COUNTER_5
+$120 constant TCCR5A \ Timer/Counter5 Control Registe
+ $c0 constant TCCR5A_COM5A \ Compare Output Mode for Channe
+ 120 $c0 bitmask: TCCR5A.COM5A \ Compare Output Mode for Channe
+ $30 constant TCCR5A_COM5B \ Compare Output Mode for Channe
+ 120 $30 bitmask: TCCR5A.COM5B \ Compare Output Mode for Channe
+ $c constant TCCR5A_COM5C \ Compare Output Mode for Channe
+ 120 $c bitmask: TCCR5A.COM5C \ Compare Output Mode for Channe
+ $3 constant TCCR5A_WGM5 \ Waveform Generation Mode
+ 120 $3 bitmask: TCCR5A.WGM5 \ Waveform Generation Mode
+$121 constant TCCR5B \ Timer/Counter5 Control Registe
+ $80 constant TCCR5B_ICNC5 \ Input Capture 5 Noise Cancelle
+ 121 $80 bitmask: TCCR5B.ICNC5 \ Input Capture 5 Noise Cancelle
+ $40 constant TCCR5B_ICES5 \ Input Capture 5 Edge Select
+ 121 $40 bitmask: TCCR5B.ICES5 \ Input Capture 5 Edge Select
+ $20 constant TCCR5B_Res \ Reserved Bit
+ 121 $20 bitmask: TCCR5B.Res \ Reserved Bit
+ $18 constant TCCR5B_WGM5 \ Waveform Generation Mode
+ 121 $18 bitmask: TCCR5B.WGM5 \ Waveform Generation Mode
+ $7 constant TCCR5B_CS5 \ Clock Select
+ 121 $7 bitmask: TCCR5B.CS5 \ Clock Select
+$122 constant TCCR5C \ Timer/Counter5 Control Registe
+ $80 constant TCCR5C_FOC5A \ Force Output Compare for Chann
+ 122 $80 bitmask: TCCR5C.FOC5A \ Force Output Compare for Chann
+ $40 constant TCCR5C_FOC5B \ Force Output Compare for Chann
+ 122 $40 bitmask: TCCR5C.FOC5B \ Force Output Compare for Chann
+ $20 constant TCCR5C_FOC5C \ Force Output Compare for Chann
+ 122 $20 bitmask: TCCR5C.FOC5C \ Force Output Compare for Chann
+ $1f constant TCCR5C_Res \ Reserved
+ 122 $1f bitmask: TCCR5C.Res \ Reserved
+$124 constant TCNT5 \ Timer/Counter5 Bytes
+$128 constant OCR5A \ Timer/Counter5 Output Compare
+$12a constant OCR5B \ Timer/Counter5 Output Compare
+$12c constant OCR5C \ Timer/Counter5 Output Compare
+$126 constant ICR5 \ Timer/Counter5 Input Capture R
+$73 constant TIMSK5 \ Timer/Counter5 Interrupt Mask
+ $c0 constant TIMSK5_Res \ Reserved Bit
+ 73 $c0 bitmask: TIMSK5.Res \ Reserved Bit
+ $20 constant TIMSK5_ICIE5 \ Timer/Counter5 Input Capture I
+ 73 $20 bitmask: TIMSK5.ICIE5 \ Timer/Counter5 Input Capture I
+ $10 constant TIMSK5_Res \ Reserved Bit
+ 73 $10 bitmask: TIMSK5.Res \ Reserved Bit
+ $8 constant TIMSK5_OCIE5C \ Timer/Counter5 Output Compare
+ 73 $8 bitmask: TIMSK5.OCIE5C \ Timer/Counter5 Output Compare
+ $4 constant TIMSK5_OCIE5B \ Timer/Counter5 Output Compare
+ 73 $4 bitmask: TIMSK5.OCIE5B \ Timer/Counter5 Output Compare
+ $2 constant TIMSK5_OCIE5A \ Timer/Counter5 Output Compare
+ 73 $2 bitmask: TIMSK5.OCIE5A \ Timer/Counter5 Output Compare
+ $1 constant TIMSK5_TOIE5 \ Timer/Counter5 Overflow Interr
+ 73 $1 bitmask: TIMSK5.TOIE5 \ Timer/Counter5 Overflow Interr
+$3a constant TIFR5 \ Timer/Counter5 Interrupt Flag
+ $c0 constant TIFR5_Res \ Reserved Bit
+ 3a $c0 bitmask: TIFR5.Res \ Reserved Bit
+ $20 constant TIFR5_ICF5 \ Timer/Counter5 Input Capture F
+ 3a $20 bitmask: TIFR5.ICF5 \ Timer/Counter5 Input Capture F
+ $10 constant TIFR5_Res \ Reserved Bit
+ 3a $10 bitmask: TIFR5.Res \ Reserved Bit
+ $8 constant TIFR5_OCF5C \ Timer/Counter5 Output Compare
+ 3a $8 bitmask: TIFR5.OCF5C \ Timer/Counter5 Output Compare
+ $4 constant TIFR5_OCF5B \ Timer/Counter5 Output Compare
+ 3a $4 bitmask: TIFR5.OCF5B \ Timer/Counter5 Output Compare
+ $2 constant TIFR5_OCF5A \ Timer/Counter5 Output Compare
+ 3a $2 bitmask: TIFR5.OCF5A \ Timer/Counter5 Output Compare
+ $1 constant TIFR5_TOV5 \ Timer/Counter5 Overflow Flag
+ 3a $1 bitmask: TIFR5.TOV5 \ Timer/Counter5 Overflow Flag
+\ TIMER_COUNTER_4
+$a0 constant TCCR4A \ Timer/Counter4 Control Registe
+ $c0 constant TCCR4A_COM4A \ Compare Output Mode for Channe
+ a0 $c0 bitmask: TCCR4A.COM4A \ Compare Output Mode for Channe
+ $30 constant TCCR4A_COM4B \ Compare Output Mode for Channe
+ a0 $30 bitmask: TCCR4A.COM4B \ Compare Output Mode for Channe
+ $c constant TCCR4A_COM4C \ Compare Output Mode for Channe
+ a0 $c bitmask: TCCR4A.COM4C \ Compare Output Mode for Channe
+ $3 constant TCCR4A_WGM4 \ Waveform Generation Mode
+ a0 $3 bitmask: TCCR4A.WGM4 \ Waveform Generation Mode
+$a1 constant TCCR4B \ Timer/Counter4 Control Registe
+ $80 constant TCCR4B_ICNC4 \ Input Capture 4 Noise Cancelle
+ a1 $80 bitmask: TCCR4B.ICNC4 \ Input Capture 4 Noise Cancelle
+ $40 constant TCCR4B_ICES4 \ Input Capture 4 Edge Select
+ a1 $40 bitmask: TCCR4B.ICES4 \ Input Capture 4 Edge Select
+ $20 constant TCCR4B_Res \ Reserved Bit
+ a1 $20 bitmask: TCCR4B.Res \ Reserved Bit
+ $18 constant TCCR4B_WGM4 \ Waveform Generation Mode
+ a1 $18 bitmask: TCCR4B.WGM4 \ Waveform Generation Mode
+ $7 constant TCCR4B_CS4 \ Clock Select
+ a1 $7 bitmask: TCCR4B.CS4 \ Clock Select
+$a2 constant TCCR4C \ Timer/Counter4 Control Registe
+ $80 constant TCCR4C_FOC4A \ Force Output Compare for Chann
+ a2 $80 bitmask: TCCR4C.FOC4A \ Force Output Compare for Chann
+ $40 constant TCCR4C_FOC4B \ Force Output Compare for Chann
+ a2 $40 bitmask: TCCR4C.FOC4B \ Force Output Compare for Chann
+ $20 constant TCCR4C_FOC4C \ Force Output Compare for Chann
+ a2 $20 bitmask: TCCR4C.FOC4C \ Force Output Compare for Chann
+ $1f constant TCCR4C_Res \ Reserved
+ a2 $1f bitmask: TCCR4C.Res \ Reserved
+$a4 constant TCNT4 \ Timer/Counter4 Bytes
+$a8 constant OCR4A \ Timer/Counter4 Output Compare
+$aa constant OCR4B \ Timer/Counter4 Output Compare
+$ac constant OCR4C \ Timer/Counter4 Output Compare
+$a6 constant ICR4 \ Timer/Counter4 Input Capture R
+$72 constant TIMSK4 \ Timer/Counter4 Interrupt Mask
+ $c0 constant TIMSK4_Res \ Reserved Bit
+ 72 $c0 bitmask: TIMSK4.Res \ Reserved Bit
+ $20 constant TIMSK4_ICIE4 \ Timer/Counter4 Input Capture I
+ 72 $20 bitmask: TIMSK4.ICIE4 \ Timer/Counter4 Input Capture I
+ $10 constant TIMSK4_Res \ Reserved Bit
+ 72 $10 bitmask: TIMSK4.Res \ Reserved Bit
+ $8 constant TIMSK4_OCIE4C \ Timer/Counter4 Output Compare
+ 72 $8 bitmask: TIMSK4.OCIE4C \ Timer/Counter4 Output Compare
+ $4 constant TIMSK4_OCIE4B \ Timer/Counter4 Output Compare
+ 72 $4 bitmask: TIMSK4.OCIE4B \ Timer/Counter4 Output Compare
+ $2 constant TIMSK4_OCIE4A \ Timer/Counter4 Output Compare
+ 72 $2 bitmask: TIMSK4.OCIE4A \ Timer/Counter4 Output Compare
+ $1 constant TIMSK4_TOIE4 \ Timer/Counter4 Overflow Interr
+ 72 $1 bitmask: TIMSK4.TOIE4 \ Timer/Counter4 Overflow Interr
+$39 constant TIFR4 \ Timer/Counter4 Interrupt Flag
+ $c0 constant TIFR4_Res \ Reserved Bit
+ 39 $c0 bitmask: TIFR4.Res \ Reserved Bit
+ $20 constant TIFR4_ICF4 \ Timer/Counter4 Input Capture F
+ 39 $20 bitmask: TIFR4.ICF4 \ Timer/Counter4 Input Capture F
+ $10 constant TIFR4_Res \ Reserved Bit
+ 39 $10 bitmask: TIFR4.Res \ Reserved Bit
+ $8 constant TIFR4_OCF4C \ Timer/Counter4 Output Compare
+ 39 $8 bitmask: TIFR4.OCF4C \ Timer/Counter4 Output Compare
+ $4 constant TIFR4_OCF4B \ Timer/Counter4 Output Compare
+ 39 $4 bitmask: TIFR4.OCF4B \ Timer/Counter4 Output Compare
+ $2 constant TIFR4_OCF4A \ Timer/Counter4 Output Compare
+ 39 $2 bitmask: TIFR4.OCF4A \ Timer/Counter4 Output Compare
+ $1 constant TIFR4_TOV4 \ Timer/Counter4 Overflow Flag
+ 39 $1 bitmask: TIFR4.TOV4 \ Timer/Counter4 Overflow Flag
+\ TIMER_COUNTER_3
+$90 constant TCCR3A \ Timer/Counter3 Control Registe
+ $c0 constant TCCR3A_COM3A \ Compare Output Mode for Channe
+ 90 $c0 bitmask: TCCR3A.COM3A \ Compare Output Mode for Channe
+ $30 constant TCCR3A_COM3B \ Compare Output Mode for Channe
+ 90 $30 bitmask: TCCR3A.COM3B \ Compare Output Mode for Channe
+ $c constant TCCR3A_COM3C \ Compare Output Mode for Channe
+ 90 $c bitmask: TCCR3A.COM3C \ Compare Output Mode for Channe
+ $3 constant TCCR3A_WGM3 \ Waveform Generation Mode
+ 90 $3 bitmask: TCCR3A.WGM3 \ Waveform Generation Mode
+$91 constant TCCR3B \ Timer/Counter3 Control Registe
+ $80 constant TCCR3B_ICNC3 \ Input Capture 3 Noise Cancelle
+ 91 $80 bitmask: TCCR3B.ICNC3 \ Input Capture 3 Noise Cancelle
+ $40 constant TCCR3B_ICES3 \ Input Capture 3 Edge Select
+ 91 $40 bitmask: TCCR3B.ICES3 \ Input Capture 3 Edge Select
+ $20 constant TCCR3B_Res \ Reserved Bit
+ 91 $20 bitmask: TCCR3B.Res \ Reserved Bit
+ $18 constant TCCR3B_WGM3 \ Waveform Generation Mode
+ 91 $18 bitmask: TCCR3B.WGM3 \ Waveform Generation Mode
+ $7 constant TCCR3B_CS3 \ Clock Select
+ 91 $7 bitmask: TCCR3B.CS3 \ Clock Select
+$92 constant TCCR3C \ Timer/Counter3 Control Registe
+ $80 constant TCCR3C_FOC3A \ Force Output Compare for Chann
+ 92 $80 bitmask: TCCR3C.FOC3A \ Force Output Compare for Chann
+ $40 constant TCCR3C_FOC3B \ Force Output Compare for Chann
+ 92 $40 bitmask: TCCR3C.FOC3B \ Force Output Compare for Chann
+ $20 constant TCCR3C_FOC3C \ Force Output Compare for Chann
+ 92 $20 bitmask: TCCR3C.FOC3C \ Force Output Compare for Chann
+ $1f constant TCCR3C_Res \ Reserved
+ 92 $1f bitmask: TCCR3C.Res \ Reserved
+$94 constant TCNT3 \ Timer/Counter3 Bytes
+$98 constant OCR3A \ Timer/Counter3 Output Compare
+$9a constant OCR3B \ Timer/Counter3 Output Compare
+$9c constant OCR3C \ Timer/Counter3 Output Compare
+$96 constant ICR3 \ Timer/Counter3 Input Capture R
+$71 constant TIMSK3 \ Timer/Counter3 Interrupt Mask
+ $c0 constant TIMSK3_Res \ Reserved Bit
+ 71 $c0 bitmask: TIMSK3.Res \ Reserved Bit
+ $20 constant TIMSK3_ICIE3 \ Timer/Counter3 Input Capture I
+ 71 $20 bitmask: TIMSK3.ICIE3 \ Timer/Counter3 Input Capture I
+ $10 constant TIMSK3_Res \ Reserved Bit
+ 71 $10 bitmask: TIMSK3.Res \ Reserved Bit
+ $8 constant TIMSK3_OCIE3C \ Timer/Counter3 Output Compare
+ 71 $8 bitmask: TIMSK3.OCIE3C \ Timer/Counter3 Output Compare
+ $4 constant TIMSK3_OCIE3B \ Timer/Counter3 Output Compare
+ 71 $4 bitmask: TIMSK3.OCIE3B \ Timer/Counter3 Output Compare
+ $2 constant TIMSK3_OCIE3A \ Timer/Counter3 Output Compare
+ 71 $2 bitmask: TIMSK3.OCIE3A \ Timer/Counter3 Output Compare
+ $1 constant TIMSK3_TOIE3 \ Timer/Counter3 Overflow Interr
+ 71 $1 bitmask: TIMSK3.TOIE3 \ Timer/Counter3 Overflow Interr
+$38 constant TIFR3 \ Timer/Counter3 Interrupt Flag
+ $c0 constant TIFR3_Res \ Reserved Bit
+ 38 $c0 bitmask: TIFR3.Res \ Reserved Bit
+ $20 constant TIFR3_ICF3 \ Timer/Counter3 Input Capture F
+ 38 $20 bitmask: TIFR3.ICF3 \ Timer/Counter3 Input Capture F
+ $10 constant TIFR3_Res \ Reserved Bit
+ 38 $10 bitmask: TIFR3.Res \ Reserved Bit
+ $8 constant TIFR3_OCF3C \ Timer/Counter3 Output Compare
+ 38 $8 bitmask: TIFR3.OCF3C \ Timer/Counter3 Output Compare
+ $4 constant TIFR3_OCF3B \ Timer/Counter3 Output Compare
+ 38 $4 bitmask: TIFR3.OCF3B \ Timer/Counter3 Output Compare
+ $2 constant TIFR3_OCF3A \ Timer/Counter3 Output Compare
+ 38 $2 bitmask: TIFR3.OCF3A \ Timer/Counter3 Output Compare
+ $1 constant TIFR3_TOV3 \ Timer/Counter3 Overflow Flag
+ 38 $1 bitmask: TIFR3.TOV3 \ Timer/Counter3 Overflow Flag
+\ TIMER_COUNTER_1
+$80 constant TCCR1A \ Timer/Counter1 Control Registe
+ $c0 constant TCCR1A_COM1A \ Compare Output Mode for Channe
+ 80 $c0 bitmask: TCCR1A.COM1A \ Compare Output Mode for Channe
+ $30 constant TCCR1A_COM1B \ Compare Output Mode for Channe
+ 80 $30 bitmask: TCCR1A.COM1B \ Compare Output Mode for Channe
+ $c constant TCCR1A_COM1C \ Compare Output Mode for Channe
+ 80 $c bitmask: TCCR1A.COM1C \ Compare Output Mode for Channe
+ $3 constant TCCR1A_WGM1 \ Waveform Generation Mode
+ 80 $3 bitmask: TCCR1A.WGM1 \ Waveform Generation Mode
+$81 constant TCCR1B \ Timer/Counter1 Control Registe
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Cancelle
+ 81 $80 bitmask: TCCR1B.ICNC1 \ Input Capture 1 Noise Cancelle
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ 81 $40 bitmask: TCCR1B.ICES1 \ Input Capture 1 Edge Select
+ $20 constant TCCR1B_Res \ Reserved Bit
+ 81 $20 bitmask: TCCR1B.Res \ Reserved Bit
+ $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
+ 81 $18 bitmask: TCCR1B.WGM1 \ Waveform Generation Mode
+ $7 constant TCCR1B_CS1 \ Clock Select
+ 81 $7 bitmask: TCCR1B.CS1 \ Clock Select
+$82 constant TCCR1C \ Timer/Counter1 Control Registe
+ $80 constant TCCR1C_FOC1A \ Force Output Compare for Chann
+ 82 $80 bitmask: TCCR1C.FOC1A \ Force Output Compare for Chann
+ $40 constant TCCR1C_FOC1B \ Force Output Compare for Chann
+ 82 $40 bitmask: TCCR1C.FOC1B \ Force Output Compare for Chann
+ $20 constant TCCR1C_FOC1C \ Force Output Compare for Chann
+ 82 $20 bitmask: TCCR1C.FOC1C \ Force Output Compare for Chann
+ $1f constant TCCR1C_Res \ Reserved
+ 82 $1f bitmask: TCCR1C.Res \ Reserved
+$84 constant TCNT1 \ Timer/Counter1 Bytes
+$88 constant OCR1A \ Timer/Counter1 Output Compare
+$8a constant OCR1B \ Timer/Counter1 Output Compare
+$8c constant OCR1C \ Timer/Counter1 Output Compare
+$86 constant ICR1 \ Timer/Counter1 Input Capture R
+$6f constant TIMSK1 \ Timer/Counter1 Interrupt Mask
+ $c0 constant TIMSK1_Res \ Reserved Bit
+ 6f $c0 bitmask: TIMSK1.Res \ Reserved Bit
+ $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture I
+ 6f $20 bitmask: TIMSK1.ICIE1 \ Timer/Counter1 Input Capture I
+ $10 constant TIMSK1_Res \ Reserved Bit
+ 6f $10 bitmask: TIMSK1.Res \ Reserved Bit
+ $8 constant TIMSK1_OCIE1C \ Timer/Counter1 Output Compare
+ 6f $8 bitmask: TIMSK1.OCIE1C \ Timer/Counter1 Output Compare
+ $4 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare
+ 6f $4 bitmask: TIMSK1.OCIE1B \ Timer/Counter1 Output Compare
+ $2 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare
+ 6f $2 bitmask: TIMSK1.OCIE1A \ Timer/Counter1 Output Compare
+ $1 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interr
+ 6f $1 bitmask: TIMSK1.TOIE1 \ Timer/Counter1 Overflow Interr
+$36 constant TIFR1 \ Timer/Counter1 Interrupt Flag
+ $c0 constant TIFR1_Res \ Reserved Bit
+ 36 $c0 bitmask: TIFR1.Res \ Reserved Bit
+ $20 constant TIFR1_ICF1 \ Timer/Counter1 Input Capture F
+ 36 $20 bitmask: TIFR1.ICF1 \ Timer/Counter1 Input Capture F
+ $10 constant TIFR1_Res \ Reserved Bit
+ 36 $10 bitmask: TIFR1.Res \ Reserved Bit
+ $8 constant TIFR1_OCF1C \ Timer/Counter1 Output Compare
+ 36 $8 bitmask: TIFR1.OCF1C \ Timer/Counter1 Output Compare
+ $4 constant TIFR1_OCF1B \ Timer/Counter1 Output Compare
+ 36 $4 bitmask: TIFR1.OCF1B \ Timer/Counter1 Output Compare
+ $2 constant TIFR1_OCF1A \ Timer/Counter1 Output Compare
+ 36 $2 bitmask: TIFR1.OCF1A \ Timer/Counter1 Output Compare
+ $1 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
+ 36 $1 bitmask: TIFR1.TOV1 \ Timer/Counter1 Overflow Flag
+\ TRX24
+$138 constant PARCR \ Power Amplifier Ramp up/down C
+ $e0 constant PARCR_PALTD \ ext. PA Ramp Down Lead Time
+ 138 $e0 bitmask: PARCR.PALTD \ ext. PA Ramp Down Lead Time
+ $1c constant PARCR_PALTU \ ext. PA Ramp Up Lead Time
+ 138 $1c bitmask: PARCR.PALTU \ ext. PA Ramp Up Lead Time
+ $2 constant PARCR_PARDFI \ Power Amplifier Ramp Down Freq
+ 138 $2 bitmask: PARCR.PARDFI \ Power Amplifier Ramp Down Freq
+ $1 constant PARCR_PARUFI \ Power Amplifier Ramp Up Freque
+ 138 $1 bitmask: PARCR.PARUFI \ Power Amplifier Ramp Up Freque
+$10e constant MAFSA0L \ Transceiver MAC Short Address
+ $ff constant MAFSA0L_MAFSA0L \ MAC Short Address low Byte for
+ 10e $ff bitmask: MAFSA0L.MAFSA0L \ MAC Short Address low Byte for
+$10f constant MAFSA0H \ Transceiver MAC Short Address
+ $ff constant MAFSA0H_MAFSA0H \ MAC Short Address high Byte fo
+ 10f $ff bitmask: MAFSA0H.MAFSA0H \ MAC Short Address high Byte fo
+$110 constant MAFPA0L \ Transceiver Personal Area Netw
+ $ff constant MAFPA0L_MAFPA0L \ MAC Personal Area Network ID l
+ 110 $ff bitmask: MAFPA0L.MAFPA0L \ MAC Personal Area Network ID l
+$111 constant MAFPA0H \ Transceiver Personal Area Netw
+ $ff constant MAFPA0H_MAFPA0H \ MAC Personal Area Network ID h
+ 111 $ff bitmask: MAFPA0H.MAFPA0H \ MAC Personal Area Network ID h
+$112 constant MAFSA1L \ Transceiver MAC Short Address
+ $ff constant MAFSA1L_MAFSA1L \ MAC Short Address low Byte for
+ 112 $ff bitmask: MAFSA1L.MAFSA1L \ MAC Short Address low Byte for
+$113 constant MAFSA1H \ Transceiver MAC Short Address
+ $ff constant MAFSA1H_MAFSA1H \ MAC Short Address high Byte fo
+ 113 $ff bitmask: MAFSA1H.MAFSA1H \ MAC Short Address high Byte fo
+$114 constant MAFPA1L \ Transceiver Personal Area Netw
+ $ff constant MAFPA1L_MAFPA1L \ MAC Personal Area Network ID l
+ 114 $ff bitmask: MAFPA1L.MAFPA1L \ MAC Personal Area Network ID l
+$115 constant MAFPA1H \ Transceiver Personal Area Netw
+ $ff constant MAFPA1H_MAFPA1H \ MAC Personal Area Network ID h
+ 115 $ff bitmask: MAFPA1H.MAFPA1H \ MAC Personal Area Network ID h
+$116 constant MAFSA2L \ Transceiver MAC Short Address
+ $ff constant MAFSA2L_MAFSA2L \ MAC Short Address low Byte for
+ 116 $ff bitmask: MAFSA2L.MAFSA2L \ MAC Short Address low Byte for
+$117 constant MAFSA2H \ Transceiver MAC Short Address
+ $ff constant MAFSA2H_MAFSA2H \ MAC Short Address high Byte fo
+ 117 $ff bitmask: MAFSA2H.MAFSA2H \ MAC Short Address high Byte fo
+$118 constant MAFPA2L \ Transceiver Personal Area Netw
+ $ff constant MAFPA2L_MAFPA2L \ MAC Personal Area Network ID l
+ 118 $ff bitmask: MAFPA2L.MAFPA2L \ MAC Personal Area Network ID l
+$119 constant MAFPA2H \ Transceiver Personal Area Netw
+ $ff constant MAFPA2H_MAFPA2H \ MAC Personal Area Network ID h
+ 119 $ff bitmask: MAFPA2H.MAFPA2H \ MAC Personal Area Network ID h
+$11a constant MAFSA3L \ Transceiver MAC Short Address
+ $ff constant MAFSA3L_MAFSA3L \ MAC Short Address low Byte for
+ 11a $ff bitmask: MAFSA3L.MAFSA3L \ MAC Short Address low Byte for
+$11b constant MAFSA3H \ Transceiver MAC Short Address
+ $ff constant MAFSA3H_MAFSA3H \ MAC Short Address high Byte fo
+ 11b $ff bitmask: MAFSA3H.MAFSA3H \ MAC Short Address high Byte fo
+$11c constant MAFPA3L \ Transceiver Personal Area Netw
+ $ff constant MAFPA3L_MAFPA3L \ MAC Personal Area Network ID l
+ 11c $ff bitmask: MAFPA3L.MAFPA3L \ MAC Personal Area Network ID l
+$11d constant MAFPA3H \ Transceiver Personal Area Netw
+ $ff constant MAFPA3H_MAFPA3H \ MAC Personal Area Network ID h
+ 11d $ff bitmask: MAFPA3H.MAFPA3H \ MAC Personal Area Network ID h
+$10c constant MAFCR0 \ Multiple Address Filter Config
+ $f0 constant MAFCR0_Res \ Reserved Bit
+ 10c $f0 bitmask: MAFCR0.Res \ Reserved Bit
+ $8 constant MAFCR0_MAF3EN \ Multiple Address Filter 3 Enab
+ 10c $8 bitmask: MAFCR0.MAF3EN \ Multiple Address Filter 3 Enab
+ $4 constant MAFCR0_MAF2EN \ Multiple Address Filter 2 Enab
+ 10c $4 bitmask: MAFCR0.MAF2EN \ Multiple Address Filter 2 Enab
+ $2 constant MAFCR0_MAF1EN \ Multiple Address Filter 1 Enab
+ 10c $2 bitmask: MAFCR0.MAF1EN \ Multiple Address Filter 1 Enab
+ $1 constant MAFCR0_MAF0EN \ Multiple Address Filter 0 Enab
+ 10c $1 bitmask: MAFCR0.MAF0EN \ Multiple Address Filter 0 Enab
+$10d constant MAFCR1 \ Multiple Address Filter Config
+ $80 constant MAFCR1_AACK_3_SET_PD \ Set Data Pending bit for addre
+ 10d $80 bitmask: MAFCR1.AACK_3_SET_PD \ Set Data Pending bit for addre
+ $40 constant MAFCR1_AACK_3_I_AM_COORD \ Enable PAN Coordinator mode fo
+ 10d $40 bitmask: MAFCR1.AACK_3_I_AM_COORD \ Enable PAN Coordinator mode fo
+ $20 constant MAFCR1_AACK_2_SET_PD \ Set Data Pending bit for addre
+ 10d $20 bitmask: MAFCR1.AACK_2_SET_PD \ Set Data Pending bit for addre
+ $10 constant MAFCR1_AACK_2_I_AM_COORD \ Enable PAN Coordinator mode fo
+ 10d $10 bitmask: MAFCR1.AACK_2_I_AM_COORD \ Enable PAN Coordinator mode fo
+ $8 constant MAFCR1_AACK_1_SET_PD \ Set Data Pending bit for addre
+ 10d $8 bitmask: MAFCR1.AACK_1_SET_PD \ Set Data Pending bit for addre
+ $4 constant MAFCR1_AACK_1_I_AM_COORD \ Enable PAN Coordinator mode fo
+ 10d $4 bitmask: MAFCR1.AACK_1_I_AM_COORD \ Enable PAN Coordinator mode fo
+ $2 constant MAFCR1_AACK_0_SET_PD \ Set Data Pending bit for addre
+ 10d $2 bitmask: MAFCR1.AACK_0_SET_PD \ Set Data Pending bit for addre
+ $1 constant MAFCR1_AACK_0_I_AM_COORD \ Enable PAN Coordinator mode fo
+ 10d $1 bitmask: MAFCR1.AACK_0_I_AM_COORD \ Enable PAN Coordinator mode fo
+$13c constant AES_CTRL \ AES Control Register
+ $80 constant AES_CTRL_AES_REQUEST \ Request AES Operation.
+ 13c $80 bitmask: AES_CTRL.AES_REQUEST \ Request AES Operation.
+ $40 constant AES_CTRL_Res \ Reserved Bit
+ 13c $40 bitmask: AES_CTRL.Res \ Reserved Bit
+ $20 constant AES_CTRL_AES_MODE \ Set AES Operation Mode
+ 13c $20 bitmask: AES_CTRL.AES_MODE \ Set AES Operation Mode
+ $10 constant AES_CTRL_Res \ Reserved Bit
+ 13c $10 bitmask: AES_CTRL.Res \ Reserved Bit
+ $8 constant AES_CTRL_AES_DIR \ Set AES Operation Direction
+ 13c $8 bitmask: AES_CTRL.AES_DIR \ Set AES Operation Direction
+ $4 constant AES_CTRL_AES_IM \ AES Interrupt Enable
+ 13c $4 bitmask: AES_CTRL.AES_IM \ AES Interrupt Enable
+ $3 constant AES_CTRL_Res \ Reserved Bit
+ 13c $3 bitmask: AES_CTRL.Res \ Reserved Bit
+$13d constant AES_STATUS \ AES Status Register
+ $80 constant AES_STATUS_AES_ER \ AES Operation Finished with Er
+ 13d $80 bitmask: AES_STATUS.AES_ER \ AES Operation Finished with Er
+ $7e constant AES_STATUS_Res \ Reserved
+ 13d $7e bitmask: AES_STATUS.Res \ Reserved
+ $1 constant AES_STATUS_AES_DONE \ AES Operation Finished with Su
+ 13d $1 bitmask: AES_STATUS.AES_DONE \ AES Operation Finished with Su
+$13e constant AES_STATE \ AES Plain and Cipher Text Buff
+ $ff constant AES_STATE_AES_STATE \ AES Plain and Cipher Text Buff
+ 13e $ff bitmask: AES_STATE.AES_STATE \ AES Plain and Cipher Text Buff
+$13f constant AES_KEY \ AES Encryption and Decryption
+ $ff constant AES_KEY_AES_KEY \ AES Encryption/Decryption Key
+ 13f $ff bitmask: AES_KEY.AES_KEY \ AES Encryption/Decryption Key
+$141 constant TRX_STATUS \ Transceiver Status Register
+ $80 constant TRX_STATUS_CCA_DONE \ CCA Algorithm Status
+ 141 $80 bitmask: TRX_STATUS.CCA_DONE \ CCA Algorithm Status
+ $40 constant TRX_STATUS_CCA_STATUS \ CCA Status Result
+ 141 $40 bitmask: TRX_STATUS.CCA_STATUS \ CCA Status Result
+ $20 constant TRX_STATUS_TST_STATUS \ Test mode status
+ 141 $20 bitmask: TRX_STATUS.TST_STATUS \ Test mode status
+ $1f constant TRX_STATUS_TRX_STATUS \ Transceiver Main Status
+ 141 $1f bitmask: TRX_STATUS.TRX_STATUS \ Transceiver Main Status
+$142 constant TRX_STATE \ Transceiver State Control Regi
+ $e0 constant TRX_STATE_TRAC_STATUS \ Transaction Status
+ 142 $e0 bitmask: TRX_STATE.TRAC_STATUS \ Transaction Status
+ $1f constant TRX_STATE_TRX_CMD \ State Control Command
+ 142 $1f bitmask: TRX_STATE.TRX_CMD \ State Control Command
+$143 constant TRX_CTRL_0 \ Reserved
+ $80 constant TRX_CTRL_0_Res7 \ Reserved
+ 143 $80 bitmask: TRX_CTRL_0.Res7 \ Reserved
+ $40 constant TRX_CTRL_0_PMU_EN \ Enable Phase Measurement Unit
+ 143 $40 bitmask: TRX_CTRL_0.PMU_EN \ Enable Phase Measurement Unit
+ $20 constant TRX_CTRL_0_PMU_START \ Start of Phase Measurement Uni
+ 143 $20 bitmask: TRX_CTRL_0.PMU_START \ Start of Phase Measurement Uni
+ $10 constant TRX_CTRL_0_PMU_IF_INV \ PMU IF Inverse
+ 143 $10 bitmask: TRX_CTRL_0.PMU_IF_INV \ PMU IF Inverse
+ $f constant TRX_CTRL_0_Res \ Reserved
+ 143 $f bitmask: TRX_CTRL_0.Res \ Reserved
+$144 constant TRX_CTRL_1 \ Transceiver Control Register 1
+ $80 constant TRX_CTRL_1_PA_EXT_EN \ External PA support enable
+ 144 $80 bitmask: TRX_CTRL_1.PA_EXT_EN \ External PA support enable
+ $40 constant TRX_CTRL_1_IRQ_2_EXT_EN \ Connect Frame Start IRQ to TC1
+ 144 $40 bitmask: TRX_CTRL_1.IRQ_2_EXT_EN \ Connect Frame Start IRQ to TC1
+ $20 constant TRX_CTRL_1_TX_AUTO_CRC_ON \ Enable Automatic CRC Calculati
+ 144 $20 bitmask: TRX_CTRL_1.TX_AUTO_CRC_ON \ Enable Automatic CRC Calculati
+ $10 constant TRX_CTRL_1_PLL_TX_FLT \ Enable PLL TX filter
+ 144 $10 bitmask: TRX_CTRL_1.PLL_TX_FLT \ Enable PLL TX filter
+ $f constant TRX_CTRL_1_Res \ Reserved
+ 144 $f bitmask: TRX_CTRL_1.Res \ Reserved
+$145 constant PHY_TX_PWR \ Transceiver Transmit Power Con
+ $f0 constant PHY_TX_PWR_Res \ Reserved
+ 145 $f0 bitmask: PHY_TX_PWR.Res \ Reserved
+ $f constant PHY_TX_PWR_TX_PWR \ Transmit Power Setting
+ 145 $f bitmask: PHY_TX_PWR.TX_PWR \ Transmit Power Setting
+$146 constant PHY_RSSI \ Receiver Signal Strength Indic
+ $80 constant PHY_RSSI_RX_CRC_VALID \ Received Frame CRC Status
+ 146 $80 bitmask: PHY_RSSI.RX_CRC_VALID \ Received Frame CRC Status
+ $60 constant PHY_RSSI_RND_VALUE \ Random Value
+ 146 $60 bitmask: PHY_RSSI.RND_VALUE \ Random Value
+ $1f constant PHY_RSSI_RSSI \ Receiver Signal Strength Indic
+ 146 $1f bitmask: PHY_RSSI.RSSI \ Receiver Signal Strength Indic
+$147 constant PHY_ED_LEVEL \ Transceiver Energy Detection L
+ $ff constant PHY_ED_LEVEL_ED_LEVEL \ Energy Detection Level
+ 147 $ff bitmask: PHY_ED_LEVEL.ED_LEVEL \ Energy Detection Level
+$148 constant PHY_CC_CCA \ Transceiver Clear Channel Asse
+ $80 constant PHY_CC_CCA_CCA_REQUEST \ Manual CCA Measurement Request
+ 148 $80 bitmask: PHY_CC_CCA.CCA_REQUEST \ Manual CCA Measurement Request
+ $60 constant PHY_CC_CCA_CCA_MODE \ Select CCA Measurement Mode
+ 148 $60 bitmask: PHY_CC_CCA.CCA_MODE \ Select CCA Measurement Mode
+ $1f constant PHY_CC_CCA_CHANNEL \ RX/TX Channel Selection
+ 148 $1f bitmask: PHY_CC_CCA.CHANNEL \ RX/TX Channel Selection
+$149 constant CCA_THRES \ Transceiver CCA Threshold Sett
+ $f0 constant CCA_THRES_CCA_CS_THRES \ CS Threshold Level for CCA Mea
+ 149 $f0 bitmask: CCA_THRES.CCA_CS_THRES \ CS Threshold Level for CCA Mea
+ $f constant CCA_THRES_CCA_ED_THRES \ ED Threshold Level for CCA Mea
+ 149 $f bitmask: CCA_THRES.CCA_ED_THRES \ ED Threshold Level for CCA Mea
+$14a constant RX_CTRL \ Transceiver Receive Control Re
+ $f constant RX_CTRL_PDT_THRES \ Receiver Sensitivity Control
+ 14a $f bitmask: RX_CTRL.PDT_THRES \ Receiver Sensitivity Control
+$14b constant SFD_VALUE \ Start of Frame Delimiter Value
+ $ff constant SFD_VALUE_SFD_VALUE \ Start of Frame Delimiter Value
+ 14b $ff bitmask: SFD_VALUE.SFD_VALUE \ Start of Frame Delimiter Value
+$14c constant TRX_CTRL_2 \ Transceiver Control Register 2
+ $80 constant TRX_CTRL_2_RX_SAFE_MODE \ RX Safe Mode
+ 14c $80 bitmask: TRX_CTRL_2.RX_SAFE_MODE \ RX Safe Mode
+ $7c constant TRX_CTRL_2_Res \ Reserved
+ 14c $7c bitmask: TRX_CTRL_2.Res \ Reserved
+ $3 constant TRX_CTRL_2_OQPSK_DATA_RATE \ Data Rate Selection
+ 14c $3 bitmask: TRX_CTRL_2.OQPSK_DATA_RATE \ Data Rate Selection
+$14d constant ANT_DIV \ Antenna Diversity Control Regi
+ $80 constant ANT_DIV_ANT_SEL \ Antenna Diversity Antenna Stat
+ 14d $80 bitmask: ANT_DIV.ANT_SEL \ Antenna Diversity Antenna Stat
+ $70 constant ANT_DIV_Res \ Reserved
+ 14d $70 bitmask: ANT_DIV.Res \ Reserved
+ $8 constant ANT_DIV_ANT_DIV_EN \ Enable Antenna Diversity
+ 14d $8 bitmask: ANT_DIV.ANT_DIV_EN \ Enable Antenna Diversity
+ $4 constant ANT_DIV_ANT_EXT_SW_EN \ Enable External Antenna Switch
+ 14d $4 bitmask: ANT_DIV.ANT_EXT_SW_EN \ Enable External Antenna Switch
+ $3 constant ANT_DIV_ANT_CTRL \ Static Antenna Diversity Switc
+ 14d $3 bitmask: ANT_DIV.ANT_CTRL \ Static Antenna Diversity Switc
+$14e constant IRQ_MASK \ Transceiver Interrupt Enable R
+ $80 constant IRQ_MASK_AWAKE_EN \ Awake Interrupt Enable
+ 14e $80 bitmask: IRQ_MASK.AWAKE_EN \ Awake Interrupt Enable
+ $40 constant IRQ_MASK_TX_END_EN \ TX_END Interrupt Enable
+ 14e $40 bitmask: IRQ_MASK.TX_END_EN \ TX_END Interrupt Enable
+ $20 constant IRQ_MASK_AMI_EN \ Address Match Interrupt Enable
+ 14e $20 bitmask: IRQ_MASK.AMI_EN \ Address Match Interrupt Enable
+ $10 constant IRQ_MASK_CCA_ED_DONE_EN \ End of ED Measurement Interrup
+ 14e $10 bitmask: IRQ_MASK.CCA_ED_DONE_EN \ End of ED Measurement Interrup
+ $8 constant IRQ_MASK_RX_END_EN \ RX_END Interrupt Enable
+ 14e $8 bitmask: IRQ_MASK.RX_END_EN \ RX_END Interrupt Enable
+ $4 constant IRQ_MASK_RX_START_EN \ RX_START Interrupt Enable
+ 14e $4 bitmask: IRQ_MASK.RX_START_EN \ RX_START Interrupt Enable
+ $2 constant IRQ_MASK_PLL_UNLOCK_EN \ PLL Unlock Interrupt Enable
+ 14e $2 bitmask: IRQ_MASK.PLL_UNLOCK_EN \ PLL Unlock Interrupt Enable
+ $1 constant IRQ_MASK_PLL_LOCK_EN \ PLL Lock Interrupt Enable
+ 14e $1 bitmask: IRQ_MASK.PLL_LOCK_EN \ PLL Lock Interrupt Enable
+$14f constant IRQ_STATUS \ Transceiver Interrupt Status R
+ $80 constant IRQ_STATUS_AWAKE \ Awake Interrupt Status
+ 14f $80 bitmask: IRQ_STATUS.AWAKE \ Awake Interrupt Status
+ $40 constant IRQ_STATUS_TX_END \ TX_END Interrupt Status
+ 14f $40 bitmask: IRQ_STATUS.TX_END \ TX_END Interrupt Status
+ $20 constant IRQ_STATUS_AMI \ Address Match Interrupt Status
+ 14f $20 bitmask: IRQ_STATUS.AMI \ Address Match Interrupt Status
+ $10 constant IRQ_STATUS_CCA_ED_DONE \ End of ED Measurement Interrup
+ 14f $10 bitmask: IRQ_STATUS.CCA_ED_DONE \ End of ED Measurement Interrup
+ $8 constant IRQ_STATUS_RX_END \ RX_END Interrupt Status
+ 14f $8 bitmask: IRQ_STATUS.RX_END \ RX_END Interrupt Status
+ $4 constant IRQ_STATUS_RX_START \ RX_START Interrupt Status
+ 14f $4 bitmask: IRQ_STATUS.RX_START \ RX_START Interrupt Status
+ $2 constant IRQ_STATUS_PLL_UNLOCK \ PLL Unlock Interrupt Status
+ 14f $2 bitmask: IRQ_STATUS.PLL_UNLOCK \ PLL Unlock Interrupt Status
+ $1 constant IRQ_STATUS_PLL_LOCK \ PLL Lock Interrupt Status
+ 14f $1 bitmask: IRQ_STATUS.PLL_LOCK \ PLL Lock Interrupt Status
+$be constant IRQ_MASK1 \ Transceiver Interrupt Enable R
+ $e0 constant IRQ_MASK1_Res \ Reserved Bit
+ be $e0 bitmask: IRQ_MASK1.Res \ Reserved Bit
+ $10 constant IRQ_MASK1_MAF_3_AMI_EN \ Address Match Interrupt enable
+ be $10 bitmask: IRQ_MASK1.MAF_3_AMI_EN \ Address Match Interrupt enable
+ $8 constant IRQ_MASK1_MAF_2_AMI_EN \ Address Match Interrupt enable
+ be $8 bitmask: IRQ_MASK1.MAF_2_AMI_EN \ Address Match Interrupt enable
+ $4 constant IRQ_MASK1_MAF_1_AMI_EN \ Address Match Interrupt enable
+ be $4 bitmask: IRQ_MASK1.MAF_1_AMI_EN \ Address Match Interrupt enable
+ $2 constant IRQ_MASK1_MAF_0_AMI_EN \ Address Match Interrupt enable
+ be $2 bitmask: IRQ_MASK1.MAF_0_AMI_EN \ Address Match Interrupt enable
+ $1 constant IRQ_MASK1_TX_START_EN \ Transmit Start Interrupt enabl
+ be $1 bitmask: IRQ_MASK1.TX_START_EN \ Transmit Start Interrupt enabl
+$bf constant IRQ_STATUS1 \ Transceiver Interrupt Status R
+ $e0 constant IRQ_STATUS1_Res \ Reserved Bit
+ bf $e0 bitmask: IRQ_STATUS1.Res \ Reserved Bit
+ $10 constant IRQ_STATUS1_MAF_3_AMI \ Address Match Interrupt Status
+ bf $10 bitmask: IRQ_STATUS1.MAF_3_AMI \ Address Match Interrupt Status
+ $8 constant IRQ_STATUS1_MAF_2_AMI \ Address Match Interrupt Status
+ bf $8 bitmask: IRQ_STATUS1.MAF_2_AMI \ Address Match Interrupt Status
+ $4 constant IRQ_STATUS1_MAF_1_AMI \ Address Match Interrupt Status
+ bf $4 bitmask: IRQ_STATUS1.MAF_1_AMI \ Address Match Interrupt Status
+ $2 constant IRQ_STATUS1_MAF_0_AMI \ Address Match Interrupt Status
+ bf $2 bitmask: IRQ_STATUS1.MAF_0_AMI \ Address Match Interrupt Status
+ $1 constant IRQ_STATUS1_TX_START \ Transmit Start Interrupt Statu
+ bf $1 bitmask: IRQ_STATUS1.TX_START \ Transmit Start Interrupt Statu
+$150 constant VREG_CTRL \ Voltage Regulator Control and
+ $80 constant VREG_CTRL_AVREG_EXT \ Use External AVDD Regulator
+ 150 $80 bitmask: VREG_CTRL.AVREG_EXT \ Use External AVDD Regulator
+ $40 constant VREG_CTRL_AVDD_OK \ AVDD Supply Voltage Valid
+ 150 $40 bitmask: VREG_CTRL.AVDD_OK \ AVDD Supply Voltage Valid
+ $8 constant VREG_CTRL_DVREG_EXT \ Use External DVDD Regulator
+ 150 $8 bitmask: VREG_CTRL.DVREG_EXT \ Use External DVDD Regulator
+ $4 constant VREG_CTRL_DVDD_OK \ DVDD Supply Voltage Valid
+ 150 $4 bitmask: VREG_CTRL.DVDD_OK \ DVDD Supply Voltage Valid
+$151 constant BATMON \ Battery Monitor Control and St
+ $80 constant BATMON_BAT_LOW \ Battery Monitor Interrupt Stat
+ 151 $80 bitmask: BATMON.BAT_LOW \ Battery Monitor Interrupt Stat
+ $40 constant BATMON_BAT_LOW_EN \ Battery Monitor Interrupt Enab
+ 151 $40 bitmask: BATMON.BAT_LOW_EN \ Battery Monitor Interrupt Enab
+ $20 constant BATMON_BATMON_OK \ Battery Monitor Status
+ 151 $20 bitmask: BATMON.BATMON_OK \ Battery Monitor Status
+ $10 constant BATMON_BATMON_HR \ Battery Monitor Voltage Range
+ 151 $10 bitmask: BATMON.BATMON_HR \ Battery Monitor Voltage Range
+ $f constant BATMON_BATMON_VTH \ Battery Monitor Threshold Volt
+ 151 $f bitmask: BATMON.BATMON_VTH \ Battery Monitor Threshold Volt
+$152 constant XOSC_CTRL \ Crystal Oscillator Control Reg
+ $f0 constant XOSC_CTRL_XTAL_MODE \ Crystal Oscillator Operating M
+ 152 $f0 bitmask: XOSC_CTRL.XTAL_MODE \ Crystal Oscillator Operating M
+ $f constant XOSC_CTRL_XTAL_TRIM \ Crystal Oscillator Load Capaci
+ 152 $f bitmask: XOSC_CTRL.XTAL_TRIM \ Crystal Oscillator Load Capaci
+$153 constant CC_CTRL_0 \ Channel Control Register 0
+ $ff constant CC_CTRL_0_CC_NUMBER \ Channel Number
+ 153 $ff bitmask: CC_CTRL_0.CC_NUMBER \ Channel Number
+$154 constant CC_CTRL_1 \ Channel Control Register 1
+ $f constant CC_CTRL_1_CC_BAND \ Channel Band
+ 154 $f bitmask: CC_CTRL_1.CC_BAND \ Channel Band
+$155 constant RX_SYN \ Transceiver Receiver Sensitivi
+ $80 constant RX_SYN_RX_PDT_DIS \ Prevent Frame Reception
+ 155 $80 bitmask: RX_SYN.RX_PDT_DIS \ Prevent Frame Reception
+ $40 constant RX_SYN_RX_OVERRIDE \ Receiver Override Function
+ 155 $40 bitmask: RX_SYN.RX_OVERRIDE \ Receiver Override Function
+ $30 constant RX_SYN_Res \ Reserved
+ 155 $30 bitmask: RX_SYN.Res \ Reserved
+ $f constant RX_SYN_RX_PDT_LEVEL \ Reduce Receiver Sensitivity
+ 155 $f bitmask: RX_SYN.RX_PDT_LEVEL \ Reduce Receiver Sensitivity
+$156 constant TRX_RPC \ Transceiver Reduced Power Cons
+ $c0 constant TRX_RPC_RX_RPC_CTRL \ Smart Receiving Mode Timing
+ 156 $c0 bitmask: TRX_RPC.RX_RPC_CTRL \ Smart Receiving Mode Timing
+ $20 constant TRX_RPC_RX_RPC_EN \ Reciver Smart Receiving Mode E
+ 156 $20 bitmask: TRX_RPC.RX_RPC_EN \ Reciver Smart Receiving Mode E
+ $10 constant TRX_RPC_PDT_RPC_EN \ Smart Receiving Mode Reduced S
+ 156 $10 bitmask: TRX_RPC.PDT_RPC_EN \ Smart Receiving Mode Reduced S
+ $8 constant TRX_RPC_PLL_RPC_EN \ PLL Smart Receiving Mode Enabl
+ 156 $8 bitmask: TRX_RPC.PLL_RPC_EN \ PLL Smart Receiving Mode Enabl
+ $4 constant TRX_RPC_Res0 \ Reserved
+ 156 $4 bitmask: TRX_RPC.Res0 \ Reserved
+ $2 constant TRX_RPC_IPAN_RPC_EN \ Smart Receiving Mode IPAN Hand
+ 156 $2 bitmask: TRX_RPC.IPAN_RPC_EN \ Smart Receiving Mode IPAN Hand
+ $1 constant TRX_RPC_XAH_RPC_EN \ Smart Receiving in Extended Op
+ 156 $1 bitmask: TRX_RPC.XAH_RPC_EN \ Smart Receiving in Extended Op
+$157 constant XAH_CTRL_1 \ Transceiver Acknowledgment Fra
+ $c0 constant XAH_CTRL_1_Res \ Reserved Bit
+ 157 $c0 bitmask: XAH_CTRL_1.Res \ Reserved Bit
+ $20 constant XAH_CTRL_1_AACK_FLTR_RES_FT \ Filter Reserved Frames
+ 157 $20 bitmask: XAH_CTRL_1.AACK_FLTR_RES_FT \ Filter Reserved Frames
+ $10 constant XAH_CTRL_1_AACK_UPLD_RES_FT \ Process Reserved Frames
+ 157 $10 bitmask: XAH_CTRL_1.AACK_UPLD_RES_FT \ Process Reserved Frames
+ $8 constant XAH_CTRL_1_Res \ Reserved Bit
+ 157 $8 bitmask: XAH_CTRL_1.Res \ Reserved Bit
+ $4 constant XAH_CTRL_1_AACK_ACK_TIME \ Reduce Acknowledgment Time
+ 157 $4 bitmask: XAH_CTRL_1.AACK_ACK_TIME \ Reduce Acknowledgment Time
+ $2 constant XAH_CTRL_1_AACK_PROM_MODE \ Enable Promiscuous Mode
+ 157 $2 bitmask: XAH_CTRL_1.AACK_PROM_MODE \ Enable Promiscuous Mode
+ $1 constant XAH_CTRL_1_Res \ Reserved Bit
+ 157 $1 bitmask: XAH_CTRL_1.Res \ Reserved Bit
+$158 constant FTN_CTRL \ Transceiver Filter Tuning Cont
+ $80 constant FTN_CTRL_FTN_START \ Start Calibration Loop of Filt
+ 158 $80 bitmask: FTN_CTRL.FTN_START \ Start Calibration Loop of Filt
+$15a constant PLL_CF \ Transceiver Center Frequency C
+ $80 constant PLL_CF_PLL_CF_START \ Start Center Frequency Calibra
+ 15a $80 bitmask: PLL_CF.PLL_CF_START \ Start Center Frequency Calibra
+$15b constant PLL_DCU \ Transceiver Delay Cell Calibra
+ $80 constant PLL_DCU_PLL_DCU_START \ Start Delay Cell Calibration
+ 15b $80 bitmask: PLL_DCU.PLL_DCU_START \ Start Delay Cell Calibration
+$15c constant PART_NUM \ Device Identification Register
+ $ff constant PART_NUM_PART_NUM \ Part Number
+ 15c $ff bitmask: PART_NUM.PART_NUM \ Part Number
+$15d constant VERSION_NUM \ Device Identification Register
+ $ff constant VERSION_NUM_VERSION_NUM \ Version Number
+ 15d $ff bitmask: VERSION_NUM.VERSION_NUM \ Version Number
+$15e constant MAN_ID_0 \ Device Identification Register
+ $80 constant MAN_ID_0_MAN_ID_07 \ Manufacturer ID (Low Byte)
+ 15e $80 bitmask: MAN_ID_0.MAN_ID_07 \ Manufacturer ID (Low Byte)
+ $40 constant MAN_ID_0_MAN_ID_06 \ Manufacturer ID (Low Byte)
+ 15e $40 bitmask: MAN_ID_0.MAN_ID_06 \ Manufacturer ID (Low Byte)
+ $20 constant MAN_ID_0_MAN_ID_05 \ Manufacturer ID (Low Byte)
+ 15e $20 bitmask: MAN_ID_0.MAN_ID_05 \ Manufacturer ID (Low Byte)
+ $10 constant MAN_ID_0_MAN_ID_04 \ Manufacturer ID (Low Byte)
+ 15e $10 bitmask: MAN_ID_0.MAN_ID_04 \ Manufacturer ID (Low Byte)
+ $8 constant MAN_ID_0_MAN_ID_03 \ Manufacturer ID (Low Byte)
+ 15e $8 bitmask: MAN_ID_0.MAN_ID_03 \ Manufacturer ID (Low Byte)
+ $4 constant MAN_ID_0_MAN_ID_02 \ Manufacturer ID (Low Byte)
+ 15e $4 bitmask: MAN_ID_0.MAN_ID_02 \ Manufacturer ID (Low Byte)
+ $2 constant MAN_ID_0_MAN_ID_01 \ Manufacturer ID (Low Byte)
+ 15e $2 bitmask: MAN_ID_0.MAN_ID_01 \ Manufacturer ID (Low Byte)
+ $1 constant MAN_ID_0_MAN_ID_00 \ Manufacturer ID (Low Byte)
+ 15e $1 bitmask: MAN_ID_0.MAN_ID_00 \ Manufacturer ID (Low Byte)
+$15f constant MAN_ID_1 \ Device Identification Register
+ $ff constant MAN_ID_1_MAN_ID_ \ Manufacturer ID (High Byte)
+ 15f $ff bitmask: MAN_ID_1.MAN_ID_ \ Manufacturer ID (High Byte)
+$160 constant SHORT_ADDR_0 \ Transceiver MAC Short Address
+ $80 constant SHORT_ADDR_0_SHORT_ADDR_07 \ MAC Short Address
+ 160 $80 bitmask: SHORT_ADDR_0.SHORT_ADDR_07 \ MAC Short Address
+ $40 constant SHORT_ADDR_0_SHORT_ADDR_06 \ MAC Short Address
+ 160 $40 bitmask: SHORT_ADDR_0.SHORT_ADDR_06 \ MAC Short Address
+ $20 constant SHORT_ADDR_0_SHORT_ADDR_05 \ MAC Short Address
+ 160 $20 bitmask: SHORT_ADDR_0.SHORT_ADDR_05 \ MAC Short Address
+ $10 constant SHORT_ADDR_0_SHORT_ADDR_04 \ MAC Short Address
+ 160 $10 bitmask: SHORT_ADDR_0.SHORT_ADDR_04 \ MAC Short Address
+ $8 constant SHORT_ADDR_0_SHORT_ADDR_03 \ MAC Short Address
+ 160 $8 bitmask: SHORT_ADDR_0.SHORT_ADDR_03 \ MAC Short Address
+ $4 constant SHORT_ADDR_0_SHORT_ADDR_02 \ MAC Short Address
+ 160 $4 bitmask: SHORT_ADDR_0.SHORT_ADDR_02 \ MAC Short Address
+ $2 constant SHORT_ADDR_0_SHORT_ADDR_01 \ MAC Short Address
+ 160 $2 bitmask: SHORT_ADDR_0.SHORT_ADDR_01 \ MAC Short Address
+ $1 constant SHORT_ADDR_0_SHORT_ADDR_00 \ MAC Short Address
+ 160 $1 bitmask: SHORT_ADDR_0.SHORT_ADDR_00 \ MAC Short Address
+$161 constant SHORT_ADDR_1 \ Transceiver MAC Short Address
+ $ff constant SHORT_ADDR_1_SHORT_ADDR_ \ MAC Short Address
+ 161 $ff bitmask: SHORT_ADDR_1.SHORT_ADDR_ \ MAC Short Address
+$162 constant PAN_ID_0 \ Transceiver Personal Area Netw
+ $80 constant PAN_ID_0_PAN_ID_07 \ MAC Personal Area Network ID
+ 162 $80 bitmask: PAN_ID_0.PAN_ID_07 \ MAC Personal Area Network ID
+ $40 constant PAN_ID_0_PAN_ID_06 \ MAC Personal Area Network ID
+ 162 $40 bitmask: PAN_ID_0.PAN_ID_06 \ MAC Personal Area Network ID
+ $20 constant PAN_ID_0_PAN_ID_05 \ MAC Personal Area Network ID
+ 162 $20 bitmask: PAN_ID_0.PAN_ID_05 \ MAC Personal Area Network ID
+ $10 constant PAN_ID_0_PAN_ID_04 \ MAC Personal Area Network ID
+ 162 $10 bitmask: PAN_ID_0.PAN_ID_04 \ MAC Personal Area Network ID
+ $8 constant PAN_ID_0_PAN_ID_03 \ MAC Personal Area Network ID
+ 162 $8 bitmask: PAN_ID_0.PAN_ID_03 \ MAC Personal Area Network ID
+ $4 constant PAN_ID_0_PAN_ID_02 \ MAC Personal Area Network ID
+ 162 $4 bitmask: PAN_ID_0.PAN_ID_02 \ MAC Personal Area Network ID
+ $2 constant PAN_ID_0_PAN_ID_01 \ MAC Personal Area Network ID
+ 162 $2 bitmask: PAN_ID_0.PAN_ID_01 \ MAC Personal Area Network ID
+ $1 constant PAN_ID_0_PAN_ID_00 \ MAC Personal Area Network ID
+ 162 $1 bitmask: PAN_ID_0.PAN_ID_00 \ MAC Personal Area Network ID
+$163 constant PAN_ID_1 \ Transceiver Personal Area Netw
+ $ff constant PAN_ID_1_PAN_ID_ \ MAC Personal Area Network ID
+ 163 $ff bitmask: PAN_ID_1.PAN_ID_ \ MAC Personal Area Network ID
+$164 constant IEEE_ADDR_0 \ Transceiver MAC IEEE Address R
+ $80 constant IEEE_ADDR_0_IEEE_ADDR_07 \ MAC IEEE Address
+ 164 $80 bitmask: IEEE_ADDR_0.IEEE_ADDR_07 \ MAC IEEE Address
+ $40 constant IEEE_ADDR_0_IEEE_ADDR_06 \ MAC IEEE Address
+ 164 $40 bitmask: IEEE_ADDR_0.IEEE_ADDR_06 \ MAC IEEE Address
+ $20 constant IEEE_ADDR_0_IEEE_ADDR_05 \ MAC IEEE Address
+ 164 $20 bitmask: IEEE_ADDR_0.IEEE_ADDR_05 \ MAC IEEE Address
+ $10 constant IEEE_ADDR_0_IEEE_ADDR_04 \ MAC IEEE Address
+ 164 $10 bitmask: IEEE_ADDR_0.IEEE_ADDR_04 \ MAC IEEE Address
+ $8 constant IEEE_ADDR_0_IEEE_ADDR_03 \ MAC IEEE Address
+ 164 $8 bitmask: IEEE_ADDR_0.IEEE_ADDR_03 \ MAC IEEE Address
+ $4 constant IEEE_ADDR_0_IEEE_ADDR_02 \ MAC IEEE Address
+ 164 $4 bitmask: IEEE_ADDR_0.IEEE_ADDR_02 \ MAC IEEE Address
+ $2 constant IEEE_ADDR_0_IEEE_ADDR_01 \ MAC IEEE Address
+ 164 $2 bitmask: IEEE_ADDR_0.IEEE_ADDR_01 \ MAC IEEE Address
+ $1 constant IEEE_ADDR_0_IEEE_ADDR_00 \ MAC IEEE Address
+ 164 $1 bitmask: IEEE_ADDR_0.IEEE_ADDR_00 \ MAC IEEE Address
+$165 constant IEEE_ADDR_1 \ Transceiver MAC IEEE Address R
+ $ff constant IEEE_ADDR_1_IEEE_ADDR_ \ MAC IEEE Address
+ 165 $ff bitmask: IEEE_ADDR_1.IEEE_ADDR_ \ MAC IEEE Address
+$166 constant IEEE_ADDR_2 \ Transceiver MAC IEEE Address R
+ $ff constant IEEE_ADDR_2_IEEE_ADDR_ \ MAC IEEE Address
+ 166 $ff bitmask: IEEE_ADDR_2.IEEE_ADDR_ \ MAC IEEE Address
+$167 constant IEEE_ADDR_3 \ Transceiver MAC IEEE Address R
+ $ff constant IEEE_ADDR_3_IEEE_ADDR_ \ MAC IEEE Address
+ 167 $ff bitmask: IEEE_ADDR_3.IEEE_ADDR_ \ MAC IEEE Address
+$168 constant IEEE_ADDR_4 \ Transceiver MAC IEEE Address R
+ $ff constant IEEE_ADDR_4_IEEE_ADDR_ \ MAC IEEE Address
+ 168 $ff bitmask: IEEE_ADDR_4.IEEE_ADDR_ \ MAC IEEE Address
+$169 constant IEEE_ADDR_5 \ Transceiver MAC IEEE Address R
+ $ff constant IEEE_ADDR_5_IEEE_ADDR_ \ MAC IEEE Address
+ 169 $ff bitmask: IEEE_ADDR_5.IEEE_ADDR_ \ MAC IEEE Address
+$16a constant IEEE_ADDR_6 \ Transceiver MAC IEEE Address R
+ $ff constant IEEE_ADDR_6_IEEE_ADDR_ \ MAC IEEE Address
+ 16a $ff bitmask: IEEE_ADDR_6.IEEE_ADDR_ \ MAC IEEE Address
+$16b constant IEEE_ADDR_7 \ Transceiver MAC IEEE Address R
+ $ff constant IEEE_ADDR_7_IEEE_ADDR_ \ MAC IEEE Address
+ 16b $ff bitmask: IEEE_ADDR_7.IEEE_ADDR_ \ MAC IEEE Address
+$16c constant XAH_CTRL_0 \ Transceiver Extended Operating
+ $f0 constant XAH_CTRL_0_MAX_FRAME_RETRIES \ Maximum Number of Frame Re-tra
+ 16c $f0 bitmask: XAH_CTRL_0.MAX_FRAME_RETRIES \ Maximum Number of Frame Re-tra
+ $e constant XAH_CTRL_0_MAX_CSMA_RETRIES \ Maximum Number of CSMA-CA Proc
+ 16c $e bitmask: XAH_CTRL_0.MAX_CSMA_RETRIES \ Maximum Number of CSMA-CA Proc
+ $1 constant XAH_CTRL_0_SLOTTED_OPERATION \ Set Slotted Acknowledgment
+ 16c $1 bitmask: XAH_CTRL_0.SLOTTED_OPERATION \ Set Slotted Acknowledgment
+$16d constant CSMA_SEED_0 \ Transceiver CSMA-CA Random Num
+ $80 constant CSMA_SEED_0_CSMA_SEED_07 \ Seed Value for CSMA Random Num
+ 16d $80 bitmask: CSMA_SEED_0.CSMA_SEED_07 \ Seed Value for CSMA Random Num
+ $40 constant CSMA_SEED_0_CSMA_SEED_06 \ Seed Value for CSMA Random Num
+ 16d $40 bitmask: CSMA_SEED_0.CSMA_SEED_06 \ Seed Value for CSMA Random Num
+ $20 constant CSMA_SEED_0_CSMA_SEED_05 \ Seed Value for CSMA Random Num
+ 16d $20 bitmask: CSMA_SEED_0.CSMA_SEED_05 \ Seed Value for CSMA Random Num
+ $10 constant CSMA_SEED_0_CSMA_SEED_04 \ Seed Value for CSMA Random Num
+ 16d $10 bitmask: CSMA_SEED_0.CSMA_SEED_04 \ Seed Value for CSMA Random Num
+ $8 constant CSMA_SEED_0_CSMA_SEED_03 \ Seed Value for CSMA Random Num
+ 16d $8 bitmask: CSMA_SEED_0.CSMA_SEED_03 \ Seed Value for CSMA Random Num
+ $4 constant CSMA_SEED_0_CSMA_SEED_02 \ Seed Value for CSMA Random Num
+ 16d $4 bitmask: CSMA_SEED_0.CSMA_SEED_02 \ Seed Value for CSMA Random Num
+ $2 constant CSMA_SEED_0_CSMA_SEED_01 \ Seed Value for CSMA Random Num
+ 16d $2 bitmask: CSMA_SEED_0.CSMA_SEED_01 \ Seed Value for CSMA Random Num
+ $1 constant CSMA_SEED_0_CSMA_SEED_00 \ Seed Value for CSMA Random Num
+ 16d $1 bitmask: CSMA_SEED_0.CSMA_SEED_00 \ Seed Value for CSMA Random Num
+$16e constant CSMA_SEED_1 \ Transceiver Acknowledgment Fra
+ $c0 constant CSMA_SEED_1_AACK_FVN_MODE \ Acknowledgment Frame Filter Mo
+ 16e $c0 bitmask: CSMA_SEED_1.AACK_FVN_MODE \ Acknowledgment Frame Filter Mo
+ $20 constant CSMA_SEED_1_AACK_SET_PD \ Set Frame Pending Sub-field
+ 16e $20 bitmask: CSMA_SEED_1.AACK_SET_PD \ Set Frame Pending Sub-field
+ $10 constant CSMA_SEED_1_AACK_DIS_ACK \ Disable Acknowledgment Frame T
+ 16e $10 bitmask: CSMA_SEED_1.AACK_DIS_ACK \ Disable Acknowledgment Frame T
+ $8 constant CSMA_SEED_1_AACK_I_AM_COORD \ Set Personal Area Network Coor
+ 16e $8 bitmask: CSMA_SEED_1.AACK_I_AM_COORD \ Set Personal Area Network Coor
+ $7 constant CSMA_SEED_1_CSMA_SEED_1 \ Seed Value for CSMA Random Num
+ 16e $7 bitmask: CSMA_SEED_1.CSMA_SEED_1 \ Seed Value for CSMA Random Num
+$16f constant CSMA_BE \ Transceiver CSMA-CA Back-off E
+ $f0 constant CSMA_BE_MAX_BE \ Maximum Back-off Exponent
+ 16f $f0 bitmask: CSMA_BE.MAX_BE \ Maximum Back-off Exponent
+ $f constant CSMA_BE_MIN_BE \ Minimum Back-off Exponent
+ 16f $f bitmask: CSMA_BE.MIN_BE \ Minimum Back-off Exponent
+$176 constant TST_CTRL_DIGI \ Transceiver Digital Test Contr
+ $f constant TST_CTRL_DIGI_TST_CTRL_DIG \ Digital Test Controller Regist
+ 176 $f bitmask: TST_CTRL_DIGI.TST_CTRL_DIG \ Digital Test Controller Regist
+$17b constant TST_RX_LENGTH \ Transceiver Received Frame Len
+ $ff constant TST_RX_LENGTH_RX_LENGTH \ Received Frame Length
+ 17b $ff bitmask: TST_RX_LENGTH.RX_LENGTH \ Received Frame Length
+$180 constant TRXFBST \ Start of frame buffer
+$1ff constant TRXFBEND \ End of frame buffer
+\ SYMCNT
+$fc constant SCTSTRHH \ Symbol Counter Transmit Frame
+ $ff constant SCTSTRHH_SCTSTRHH \ Symbol Counter Transmit Frame
+ fc $ff bitmask: SCTSTRHH.SCTSTRHH \ Symbol Counter Transmit Frame
+$fb constant SCTSTRHL \ Symbol Counter Transmit Frame
+ $ff constant SCTSTRHL_SCTSTRHL \ Symbol Counter Transmit Frame
+ fb $ff bitmask: SCTSTRHL.SCTSTRHL \ Symbol Counter Transmit Frame
+$fa constant SCTSTRLH \ Symbol Counter Transmit Frame
+ $ff constant SCTSTRLH_SCTSTRLH \ Symbol Counter Transmit Frame
+ fa $ff bitmask: SCTSTRLH.SCTSTRLH \ Symbol Counter Transmit Frame
+$f9 constant SCTSTRLL \ Symbol Counter Transmit Frame
+ $ff constant SCTSTRLL_SCTSTRLL \ Symbol Counter Transmit Frame
+ f9 $ff bitmask: SCTSTRLL.SCTSTRLL \ Symbol Counter Transmit Frame
+$f8 constant SCOCR1HH \ Symbol Counter Output Compare
+ $ff constant SCOCR1HH_SCOCR1HH \ Symbol Counter Output Compare
+ f8 $ff bitmask: SCOCR1HH.SCOCR1HH \ Symbol Counter Output Compare
+$f7 constant SCOCR1HL \ Symbol Counter Output Compare
+ $ff constant SCOCR1HL_SCOCR1HL \ Symbol Counter Output Compare
+ f7 $ff bitmask: SCOCR1HL.SCOCR1HL \ Symbol Counter Output Compare
+$f6 constant SCOCR1LH \ Symbol Counter Output Compare
+ $ff constant SCOCR1LH_SCOCR1LH \ Symbol Counter Output Compare
+ f6 $ff bitmask: SCOCR1LH.SCOCR1LH \ Symbol Counter Output Compare
+$f5 constant SCOCR1LL \ Symbol Counter Output Compare
+ $ff constant SCOCR1LL_SCOCR1LL \ Symbol Counter Output Compare
+ f5 $ff bitmask: SCOCR1LL.SCOCR1LL \ Symbol Counter Output Compare
+$f4 constant SCOCR2HH \ Symbol Counter Output Compare
+ $ff constant SCOCR2HH_SCOCR2HH \ Symbol Counter Output Compare
+ f4 $ff bitmask: SCOCR2HH.SCOCR2HH \ Symbol Counter Output Compare
+$f3 constant SCOCR2HL \ Symbol Counter Output Compare
+ $ff constant SCOCR2HL_SCOCR2HL \ Symbol Counter Output Compare
+ f3 $ff bitmask: SCOCR2HL.SCOCR2HL \ Symbol Counter Output Compare
+$f2 constant SCOCR2LH \ Symbol Counter Output Compare
+ $ff constant SCOCR2LH_SCOCR2LH \ Symbol Counter Output Compare
+ f2 $ff bitmask: SCOCR2LH.SCOCR2LH \ Symbol Counter Output Compare
+$f1 constant SCOCR2LL \ Symbol Counter Output Compare
+ $ff constant SCOCR2LL_SCOCR2LL \ Symbol Counter Output Compare
+ f1 $ff bitmask: SCOCR2LL.SCOCR2LL \ Symbol Counter Output Compare
+$f0 constant SCOCR3HH \ Symbol Counter Output Compare
+ $ff constant SCOCR3HH_SCOCR3HH \ Symbol Counter Output Compare
+ f0 $ff bitmask: SCOCR3HH.SCOCR3HH \ Symbol Counter Output Compare
+$ef constant SCOCR3HL \ Symbol Counter Output Compare
+ $ff constant SCOCR3HL_SCOCR3HL \ Symbol Counter Output Compare
+ ef $ff bitmask: SCOCR3HL.SCOCR3HL \ Symbol Counter Output Compare
+$ee constant SCOCR3LH \ Symbol Counter Output Compare
+ $ff constant SCOCR3LH_SCOCR3LH \ Symbol Counter Output Compare
+ ee $ff bitmask: SCOCR3LH.SCOCR3LH \ Symbol Counter Output Compare
+$ed constant SCOCR3LL \ Symbol Counter Output Compare
+ $ff constant SCOCR3LL_SCOCR3LL \ Symbol Counter Output Compare
+ ed $ff bitmask: SCOCR3LL.SCOCR3LL \ Symbol Counter Output Compare
+$ec constant SCTSRHH \ Symbol Counter Frame Timestamp
+ $ff constant SCTSRHH_SCTSRHH \ Symbol Counter Frame Timestamp
+ ec $ff bitmask: SCTSRHH.SCTSRHH \ Symbol Counter Frame Timestamp
+$eb constant SCTSRHL \ Symbol Counter Frame Timestamp
+ $ff constant SCTSRHL_SCTSRHL \ Symbol Counter Frame Timestamp
+ eb $ff bitmask: SCTSRHL.SCTSRHL \ Symbol Counter Frame Timestamp
+$ea constant SCTSRLH \ Symbol Counter Frame Timestamp
+ $ff constant SCTSRLH_SCTSRLH \ Symbol Counter Frame Timestamp
+ ea $ff bitmask: SCTSRLH.SCTSRLH \ Symbol Counter Frame Timestamp
+$e9 constant SCTSRLL \ Symbol Counter Frame Timestamp
+ $ff constant SCTSRLL_SCTSRLL \ Symbol Counter Frame Timestamp
+ e9 $ff bitmask: SCTSRLL.SCTSRLL \ Symbol Counter Frame Timestamp
+$e8 constant SCBTSRHH \ Symbol Counter Beacon Timestam
+ $ff constant SCBTSRHH_SCBTSRHH \ Symbol Counter Beacon Timestam
+ e8 $ff bitmask: SCBTSRHH.SCBTSRHH \ Symbol Counter Beacon Timestam
+$e7 constant SCBTSRHL \ Symbol Counter Beacon Timestam
+ $ff constant SCBTSRHL_SCBTSRHL \ Symbol Counter Beacon Timestam
+ e7 $ff bitmask: SCBTSRHL.SCBTSRHL \ Symbol Counter Beacon Timestam
+$e6 constant SCBTSRLH \ Symbol Counter Beacon Timestam
+ $ff constant SCBTSRLH_SCBTSRLH \ Symbol Counter Beacon Timestam
+ e6 $ff bitmask: SCBTSRLH.SCBTSRLH \ Symbol Counter Beacon Timestam
+$e5 constant SCBTSRLL \ Symbol Counter Beacon Timestam
+ $ff constant SCBTSRLL_SCBTSRLL \ Symbol Counter Beacon Timestam
+ e5 $ff bitmask: SCBTSRLL.SCBTSRLL \ Symbol Counter Beacon Timestam
+$e4 constant SCCNTHH \ Symbol Counter Register HH-Byt
+ $ff constant SCCNTHH_SCCNTHH \ Symbol Counter Register HH-Byt
+ e4 $ff bitmask: SCCNTHH.SCCNTHH \ Symbol Counter Register HH-Byt
+$e3 constant SCCNTHL \ Symbol Counter Register HL-Byt
+ $ff constant SCCNTHL_SCCNTHL \ Symbol Counter Register HL-Byt
+ e3 $ff bitmask: SCCNTHL.SCCNTHL \ Symbol Counter Register HL-Byt
+$e2 constant SCCNTLH \ Symbol Counter Register LH-Byt
+ $ff constant SCCNTLH_SCCNTLH \ Symbol Counter Register LH-Byt
+ e2 $ff bitmask: SCCNTLH.SCCNTLH \ Symbol Counter Register LH-Byt
+$e1 constant SCCNTLL \ Symbol Counter Register LL-Byt
+ $ff constant SCCNTLL_SCCNTLL \ Symbol Counter Register LL-Byt
+ e1 $ff bitmask: SCCNTLL.SCCNTLL \ Symbol Counter Register LL-Byt
+$e0 constant SCIRQS \ Symbol Counter Interrupt Statu
+ $e0 constant SCIRQS_Res \ Reserved Bit
+ e0 $e0 bitmask: SCIRQS.Res \ Reserved Bit
+ $10 constant SCIRQS_IRQSBO \ Backoff Slot Counter IRQ
+ e0 $10 bitmask: SCIRQS.IRQSBO \ Backoff Slot Counter IRQ
+ $8 constant SCIRQS_IRQSOF \ Symbol Counter Overflow IRQ
+ e0 $8 bitmask: SCIRQS.IRQSOF \ Symbol Counter Overflow IRQ
+ $7 constant SCIRQS_IRQSCP \ Compare Unit 3 Compare Match I
+ e0 $7 bitmask: SCIRQS.IRQSCP \ Compare Unit 3 Compare Match I
+$df constant SCIRQM \ Symbol Counter Interrupt Mask
+ $e0 constant SCIRQM_Res \ Reserved Bit
+ df $e0 bitmask: SCIRQM.Res \ Reserved Bit
+ $10 constant SCIRQM_IRQMBO \ Backoff Slot Counter IRQ enabl
+ df $10 bitmask: SCIRQM.IRQMBO \ Backoff Slot Counter IRQ enabl
+ $8 constant SCIRQM_IRQMOF \ Symbol Counter Overflow IRQ en
+ df $8 bitmask: SCIRQM.IRQMOF \ Symbol Counter Overflow IRQ en
+ $7 constant SCIRQM_IRQMCP \ Symbol Counter Compare Match 3
+ df $7 bitmask: SCIRQM.IRQMCP \ Symbol Counter Compare Match 3
+$de constant SCSR \ Symbol Counter Status Register
+ $fe constant SCSR_Res \ Reserved Bit
+ de $fe bitmask: SCSR.Res \ Reserved Bit
+ $1 constant SCSR_SCBSY \ Symbol Counter busy
+ de $1 bitmask: SCSR.SCBSY \ Symbol Counter busy
+$dd constant SCCR1 \ Symbol Counter Control Registe
+ $c0 constant SCCR1_Res \ Reserved Bit
+ dd $c0 bitmask: SCCR1.Res \ Reserved Bit
+ $20 constant SCCR1_SCBTSM \ Symbol Counter Beacon Timestam
+ dd $20 bitmask: SCCR1.SCBTSM \ Symbol Counter Beacon Timestam
+ $1c constant SCCR1_SCCKDIV \ Clock divider for synchronous
+ dd $1c bitmask: SCCR1.SCCKDIV \ Clock divider for synchronous
+ $2 constant SCCR1_SCEECLK \ Enable External Clock Source o
+ dd $2 bitmask: SCCR1.SCEECLK \ Enable External Clock Source o
+ $1 constant SCCR1_SCENBO \ Backoff Slot Counter enable
+ dd $1 bitmask: SCCR1.SCENBO \ Backoff Slot Counter enable
+$dc constant SCCR0 \ Symbol Counter Control Registe
+ $80 constant SCCR0_SCRES \ Symbol Counter Synchronization
+ dc $80 bitmask: SCCR0.SCRES \ Symbol Counter Synchronization
+ $40 constant SCCR0_SCMBTS \ Manual Beacon Timestamp
+ dc $40 bitmask: SCCR0.SCMBTS \ Manual Beacon Timestamp
+ $20 constant SCCR0_SCEN \ Symbol Counter enable
+ dc $20 bitmask: SCCR0.SCEN \ Symbol Counter enable
+ $10 constant SCCR0_SCCKSEL \ Symbol Counter Clock Source se
+ dc $10 bitmask: SCCR0.SCCKSEL \ Symbol Counter Clock Source se
+ $8 constant SCCR0_SCTSE \ Symbol Counter Automatic Times
+ dc $8 bitmask: SCCR0.SCTSE \ Symbol Counter Automatic Times
+ $7 constant SCCR0_SCCMP \ Symbol Counter Compare Unit 3
+ dc $7 bitmask: SCCR0.SCCMP \ Symbol Counter Compare Unit 3
+$db constant SCCSR \ Symbol Counter Compare Source
+ $c0 constant SCCSR_Res \ Reserved Bit
+ db $c0 bitmask: SCCSR.Res \ Reserved Bit
+ $30 constant SCCSR_SCCS3 \ Symbol Counter Compare Source
+ db $30 bitmask: SCCSR.SCCS3 \ Symbol Counter Compare Source
+ $c constant SCCSR_SCCS2 \ Symbol Counter Compare Source
+ db $c bitmask: SCCSR.SCCS2 \ Symbol Counter Compare Source
+ $3 constant SCCSR_SCCS1 \ Symbol Counter Compare Source
+ db $3 bitmask: SCCSR.SCCS1 \ Symbol Counter Compare Source
+$da constant SCRSTRHH \ Symbol Counter Received Frame
+ $ff constant SCRSTRHH_SCRSTRHH \ Symbol Counter Received Frame
+ da $ff bitmask: SCRSTRHH.SCRSTRHH \ Symbol Counter Received Frame
+$d9 constant SCRSTRHL \ Symbol Counter Received Frame
+ $ff constant SCRSTRHL_SCRSTRHL \ Symbol Counter Received Frame
+ d9 $ff bitmask: SCRSTRHL.SCRSTRHL \ Symbol Counter Received Frame
+$d8 constant SCRSTRLH \ Symbol Counter Received Frame
+ $ff constant SCRSTRLH_SCRSTRLH \ Symbol Counter Received Frame
+ d8 $ff bitmask: SCRSTRLH.SCRSTRLH \ Symbol Counter Received Frame
+$d7 constant SCRSTRLL \ Symbol Counter Received Frame
+ $ff constant SCRSTRLL_SCRSTRLL \ Symbol Counter Received Frame
+ d7 $ff bitmask: SCRSTRLL.SCRSTRLL \ Symbol Counter Received Frame
+\ EEPROM
+$41 constant EEAR \ EEPROM Address Register Bytes
+$40 constant EEDR \ EEPROM Data Register
+$3f constant EECR \ EEPROM Control Register
+ $c0 constant EECR_Res \ Reserved
+ 3f $c0 bitmask: EECR.Res \ Reserved
+ $30 constant EECR_EEPM \ EEPROM Programming Mode
+ 3f $30 bitmask: EECR.EEPM \ EEPROM Programming Mode
+ $8 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
+ 3f $8 bitmask: EECR.EERIE \ EEPROM Ready Interrupt Enable
+ $4 constant EECR_EEMPE \ EEPROM Master Write Enable
+ 3f $4 bitmask: EECR.EEMPE \ EEPROM Master Write Enable
+ $2 constant EECR_EEPE \ EEPROM Programming Enable
+ 3f $2 bitmask: EECR.EEPE \ EEPROM Programming Enable
+ $1 constant EECR_EERE \ EEPROM Read Enable
+ 3f $1 bitmask: EECR.EERE \ EEPROM Read Enable
+\ JTAG
+$51 constant OCDR \ On-Chip Debug Register
+ $ff constant OCDR_OCDR \ On-Chip Debug Register Data
+ 51 $ff bitmask: OCDR.OCDR \ On-Chip Debug Register Data
+$55 constant MCUCR \ MCU Control Register
+ $80 constant MCUCR_JTD \ JTAG Interface Disable
+ 55 $80 bitmask: MCUCR.JTD \ JTAG Interface Disable
+$54 constant MCUSR \ MCU Status Register
+ $10 constant MCUSR_JTRF \ JTAG Reset Flag
+ 54 $10 bitmask: MCUSR.JTRF \ JTAG Reset Flag
+\ EXTERNAL_INTERRUPT
+$69 constant EICRA \ External Interrupt Control Reg
+ $c0 constant EICRA_ISC3 \ External Interrupt 3 Sense Con
+ 69 $c0 bitmask: EICRA.ISC3 \ External Interrupt 3 Sense Con
+ $30 constant EICRA_ISC2 \ External Interrupt 2 Sense Con
+ 69 $30 bitmask: EICRA.ISC2 \ External Interrupt 2 Sense Con
+ $c constant EICRA_ISC1 \ External Interrupt 1 Sense Con
+ 69 $c bitmask: EICRA.ISC1 \ External Interrupt 1 Sense Con
+ $3 constant EICRA_ISC0 \ External Interrupt 0 Sense Con
+ 69 $3 bitmask: EICRA.ISC0 \ External Interrupt 0 Sense Con
+$6a constant EICRB \ External Interrupt Control Reg
+ $c0 constant EICRB_ISC7 \ External Interrupt 7 Sense Con
+ 6a $c0 bitmask: EICRB.ISC7 \ External Interrupt 7 Sense Con
+ $30 constant EICRB_ISC6 \ External Interrupt 6 Sense Con
+ 6a $30 bitmask: EICRB.ISC6 \ External Interrupt 6 Sense Con
+ $c constant EICRB_ISC5 \ External Interrupt 5 Sense Con
+ 6a $c bitmask: EICRB.ISC5 \ External Interrupt 5 Sense Con
+ $3 constant EICRB_ISC4 \ External Interrupt 4 Sense Con
+ 6a $3 bitmask: EICRB.ISC4 \ External Interrupt 4 Sense Con
+$3d constant EIMSK \ External Interrupt Mask Regist
+ $ff constant EIMSK_INT \ External Interrupt Request Ena
+ 3d $ff bitmask: EIMSK.INT \ External Interrupt Request Ena
+$3c constant EIFR \ External Interrupt Flag Regist
+ $ff constant EIFR_INTF \ External Interrupt Flag
+ 3c $ff bitmask: EIFR.INTF \ External Interrupt Flag
+$6d constant PCMSK2 \ Pin Change Mask Register 2
+ $ff constant PCMSK2_PCINT \ Pin Change Enable Mask
+ 6d $ff bitmask: PCMSK2.PCINT \ Pin Change Enable Mask
+$6c constant PCMSK1 \ Pin Change Mask Register 1
+ $ff constant PCMSK1_PCINT \ Pin Change Enable Mask
+ 6c $ff bitmask: PCMSK1.PCINT \ Pin Change Enable Mask
+$6b constant PCMSK0 \ Pin Change Mask Register 0
+$3b constant PCIFR \ Pin Change Interrupt Flag Regi
+ $f8 constant PCIFR_Res \ Reserved Bit
+ 3b $f8 bitmask: PCIFR.Res \ Reserved Bit
+ $7 constant PCIFR_PCIF \ Pin Change Interrupt Flags
+ 3b $7 bitmask: PCIFR.PCIF \ Pin Change Interrupt Flags
+$68 constant PCICR \ Pin Change Interrupt Control R
+ $f8 constant PCICR_Res \ Reserved Bit
+ 68 $f8 bitmask: PCICR.Res \ Reserved Bit
+ $7 constant PCICR_PCIE \ Pin Change Interrupt Enables
+ 68 $7 bitmask: PCICR.PCIE \ Pin Change Interrupt Enables
+\ AD_CONVERTER
+$7c constant ADMUX \ The ADC Multiplexer Selection
+ $c0 constant ADMUX_REFS \ Reference Selection Bits
+ 7c $c0 bitmask: ADMUX.REFS \ Reference Selection Bits
+ $20 constant ADMUX_ADLAR \ ADC Left Adjust Result
+ 7c $20 bitmask: ADMUX.ADLAR \ ADC Left Adjust Result
+ $1f constant ADMUX_MUX \ Analog Channel and Gain Select
+ 7c $1f bitmask: ADMUX.MUX \ Analog Channel and Gain Select
+$78 constant ADC \ ADC Data Register Bytes
+$7a constant ADCSRA \ The ADC Control and Status Reg
+ $80 constant ADCSRA_ADEN \ ADC Enable
+ 7a $80 bitmask: ADCSRA.ADEN \ ADC Enable
+ $40 constant ADCSRA_ADSC \ ADC Start Conversion
+ 7a $40 bitmask: ADCSRA.ADSC \ ADC Start Conversion
+ $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
+ 7a $20 bitmask: ADCSRA.ADATE \ ADC Auto Trigger Enable
+ $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
+ 7a $10 bitmask: ADCSRA.ADIF \ ADC Interrupt Flag
+ $8 constant ADCSRA_ADIE \ ADC Interrupt Enable
+ 7a $8 bitmask: ADCSRA.ADIE \ ADC Interrupt Enable
+ $7 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
+ 7a $7 bitmask: ADCSRA.ADPS \ ADC Prescaler Select Bits
+$7b constant ADCSRB \ The ADC Control and Status Reg
+ $80 constant ADCSRB_AVDDOK \ AVDD Supply Voltage OK
+ 7b $80 bitmask: ADCSRB.AVDDOK \ AVDD Supply Voltage OK
+ $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer
+ 7b $40 bitmask: ADCSRB.ACME \ Analog Comparator Multiplexer
+ $20 constant ADCSRB_REFOK \ Reference Voltage OK
+ 7b $20 bitmask: ADCSRB.REFOK \ Reference Voltage OK
+ $10 constant ADCSRB_ACCH \ Analog Channel Change
+ 7b $10 bitmask: ADCSRB.ACCH \ Analog Channel Change
+ $8 constant ADCSRB_MUX5 \ Analog Channel and Gain Select
+ 7b $8 bitmask: ADCSRB.MUX5 \ Analog Channel and Gain Select
+ $7 constant ADCSRB_ADTS \ ADC Auto Trigger Source
+ 7b $7 bitmask: ADCSRB.ADTS \ ADC Auto Trigger Source
+$77 constant ADCSRC \ The ADC Control and Status Reg
+ $c0 constant ADCSRC_ADTHT \ ADC Track-and-Hold Time
+ 77 $c0 bitmask: ADCSRC.ADTHT \ ADC Track-and-Hold Time
+ $20 constant ADCSRC_Res0 \ Reserved
+ 77 $20 bitmask: ADCSRC.Res0 \ Reserved
+ $1f constant ADCSRC_ADSUT \ ADC Start-up Time
+ 77 $1f bitmask: ADCSRC.ADSUT \ ADC Start-up Time
+$7d constant DIDR2 \ Digital Input Disable Register
+ $80 constant DIDR2_ADC15D \ Reserved Bits
+ 7d $80 bitmask: DIDR2.ADC15D \ Reserved Bits
+ $40 constant DIDR2_ADC14D \ Reserved Bits
+ 7d $40 bitmask: DIDR2.ADC14D \ Reserved Bits
+ $20 constant DIDR2_ADC13D \ Reserved Bits
+ 7d $20 bitmask: DIDR2.ADC13D \ Reserved Bits
+ $10 constant DIDR2_ADC12D \ Reserved Bits
+ 7d $10 bitmask: DIDR2.ADC12D \ Reserved Bits
+ $8 constant DIDR2_ADC11D \ Reserved Bits
+ 7d $8 bitmask: DIDR2.ADC11D \ Reserved Bits
+ $4 constant DIDR2_ADC10D \ Reserved Bits
+ 7d $4 bitmask: DIDR2.ADC10D \ Reserved Bits
+ $2 constant DIDR2_ADC9D \ Reserved Bits
+ 7d $2 bitmask: DIDR2.ADC9D \ Reserved Bits
+ $1 constant DIDR2_ADC8D \ Reserved Bits
+ 7d $1 bitmask: DIDR2.ADC8D \ Reserved Bits
+$7e constant DIDR0 \ Digital Input Disable Register
+ $80 constant DIDR0_ADC7D \ Disable ADC7:0 Digital Input
+ 7e $80 bitmask: DIDR0.ADC7D \ Disable ADC7:0 Digital Input
+ $40 constant DIDR0_ADC6D \ Disable ADC7:0 Digital Input
+ 7e $40 bitmask: DIDR0.ADC6D \ Disable ADC7:0 Digital Input
+ $20 constant DIDR0_ADC5D \ Disable ADC7:0 Digital Input
+ 7e $20 bitmask: DIDR0.ADC5D \ Disable ADC7:0 Digital Input
+ $10 constant DIDR0_ADC4D \ Disable ADC7:0 Digital Input
+ 7e $10 bitmask: DIDR0.ADC4D \ Disable ADC7:0 Digital Input
+ $8 constant DIDR0_ADC3D \ Disable ADC7:0 Digital Input
+ 7e $8 bitmask: DIDR0.ADC3D \ Disable ADC7:0 Digital Input
+ $4 constant DIDR0_ADC2D \ Disable ADC7:0 Digital Input
+ 7e $4 bitmask: DIDR0.ADC2D \ Disable ADC7:0 Digital Input
+ $2 constant DIDR0_ADC1D \ Disable ADC7:0 Digital Input
+ 7e $2 bitmask: DIDR0.ADC1D \ Disable ADC7:0 Digital Input
+ $1 constant DIDR0_ADC0D \ Disable ADC7:0 Digital Input
+ 7e $1 bitmask: DIDR0.ADC0D \ Disable ADC7:0 Digital Input
+\ BOOT_LOAD
+$57 constant SPMCSR \ Store Program Memory Control R
+ $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
+ 57 $80 bitmask: SPMCSR.SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
+ 57 $40 bitmask: SPMCSR.RWWSB \ Read While Write Section Busy
+ $20 constant SPMCSR_SIGRD \ Signature Row Read
+ 57 $20 bitmask: SPMCSR.SIGRD \ Signature Row Read
+ $10 constant SPMCSR_RWWSRE \ Read While Write Section Read
+ 57 $10 bitmask: SPMCSR.RWWSRE \ Read While Write Section Read
+ $8 constant SPMCSR_BLBSET \ Boot Lock Bit Set
+ 57 $8 bitmask: SPMCSR.BLBSET \ Boot Lock Bit Set
+ $4 constant SPMCSR_PGWRT \ Page Write
+ 57 $4 bitmask: SPMCSR.PGWRT \ Page Write
+ $2 constant SPMCSR_PGERS \ Page Erase
+ 57 $2 bitmask: SPMCSR.PGERS \ Page Erase
+ $1 constant SPMCSR_SPMEN \ Store Program Memory Enable
+ 57 $1 bitmask: SPMCSR.SPMEN \ Store Program Memory Enable
+\ CPU
+$5f constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ 5f $80 bitmask: SREG.I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ 5f $40 bitmask: SREG.T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ 5f $20 bitmask: SREG.H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ 5f $10 bitmask: SREG.S \ Sign Bit
+ $8 constant SREG_V \ Two's Complement Overflow Flag
+ 5f $8 bitmask: SREG.V \ Two's Complement Overflow Flag
+ $4 constant SREG_N \ Negative Flag
+ 5f $4 bitmask: SREG.N \ Negative Flag
+ $2 constant SREG_Z \ Zero Flag
+ 5f $2 bitmask: SREG.Z \ Zero Flag
+ $1 constant SREG_C \ Carry Flag
+ 5f $1 bitmask: SREG.C \ Carry Flag
+$5d constant SP \ Stack Pointer
+$55 constant MCUCR \ MCU Control Register
+ $80 constant MCUCR_JTD \ JTAG Interface Disable
+ 55 $80 bitmask: MCUCR.JTD \ JTAG Interface Disable
+ $60 constant MCUCR_Res \ Reserved
+ 55 $60 bitmask: MCUCR.Res \ Reserved
+ $10 constant MCUCR_PUD \ Pull-up Disable
+ 55 $10 bitmask: MCUCR.PUD \ Pull-up Disable
+ $c constant MCUCR_Res \ Reserved
+ 55 $c bitmask: MCUCR.Res \ Reserved
+ $2 constant MCUCR_IVSEL \ Interrupt Vector Select
+ 55 $2 bitmask: MCUCR.IVSEL \ Interrupt Vector Select
+ $1 constant MCUCR_IVCE \ Interrupt Vector Change Enable
+ 55 $1 bitmask: MCUCR.IVCE \ Interrupt Vector Change Enable
+$54 constant MCUSR \ MCU Status Register
+ $e0 constant MCUSR_Res \ Reserved
+ 54 $e0 bitmask: MCUSR.Res \ Reserved
+ $10 constant MCUSR_JTRF \ JTAG Reset Flag
+ 54 $10 bitmask: MCUSR.JTRF \ JTAG Reset Flag
+ $8 constant MCUSR_WDRF \ Watchdog Reset Flag
+ 54 $8 bitmask: MCUSR.WDRF \ Watchdog Reset Flag
+ $4 constant MCUSR_BORF \ Brown-out Reset Flag
+ 54 $4 bitmask: MCUSR.BORF \ Brown-out Reset Flag
+ $2 constant MCUSR_EXTRF \ External Reset Flag
+ 54 $2 bitmask: MCUSR.EXTRF \ External Reset Flag
+ $1 constant MCUSR_PORF \ Power-on Reset Flag
+ 54 $1 bitmask: MCUSR.PORF \ Power-on Reset Flag
+$66 constant OSCCAL \ Oscillator Calibration Value
+ $ff constant OSCCAL_CAL \ Oscillator Calibration Tuning
+ 66 $ff bitmask: OSCCAL.CAL \ Oscillator Calibration Tuning
+$61 constant CLKPR \ Clock Prescale Register
+ $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable
+ 61 $80 bitmask: CLKPR.CLKPCE \ Clock Prescaler Change Enable
+ $70 constant CLKPR_Res \ Reserved
+ 61 $70 bitmask: CLKPR.Res \ Reserved
+ $f constant CLKPR_CLKPS \ Clock Prescaler Select Bits
+ 61 $f bitmask: CLKPR.CLKPS \ Clock Prescaler Select Bits
+$53 constant SMCR \ Sleep Mode Control Register
+ $f0 constant SMCR_Res \ Reserved
+ 53 $f0 bitmask: SMCR.Res \ Reserved
+ $e constant SMCR_SM \ Sleep Mode Select bits
+ 53 $e bitmask: SMCR.SM \ Sleep Mode Select bits
+ $1 constant SMCR_SE \ Sleep Enable
+ 53 $1 bitmask: SMCR.SE \ Sleep Enable
+$5c constant EIND \ Extended Indirect Register
+$5b constant RAMPZ \ Extended Z-pointer Register fo
+ $fc constant RAMPZ_Res \ Reserved
+ 5b $fc bitmask: RAMPZ.Res \ Reserved
+ $3 constant RAMPZ_RAMPZ \ Extended Z-Pointer Value
+ 5b $3 bitmask: RAMPZ.RAMPZ \ Extended Z-Pointer Value
+$4b constant GPIOR2 \ General Purpose I/O Register 2
+ $ff constant GPIOR2_GPIOR \ General Purpose I/O Register 2
+ 4b $ff bitmask: GPIOR2.GPIOR \ General Purpose I/O Register 2
+$4a constant GPIOR1 \ General Purpose IO Register 1
+ $ff constant GPIOR1_GPIOR \ General Purpose I/O Register 1
+ 4a $ff bitmask: GPIOR1.GPIOR \ General Purpose I/O Register 1
+$3e constant GPIOR0 \ General Purpose IO Register 0
+ $80 constant GPIOR0_GPIOR07 \ General Purpose I/O Register 0
+ 3e $80 bitmask: GPIOR0.GPIOR07 \ General Purpose I/O Register 0
+ $40 constant GPIOR0_GPIOR06 \ General Purpose I/O Register 0
+ 3e $40 bitmask: GPIOR0.GPIOR06 \ General Purpose I/O Register 0
+ $20 constant GPIOR0_GPIOR05 \ General Purpose I/O Register 0
+ 3e $20 bitmask: GPIOR0.GPIOR05 \ General Purpose I/O Register 0
+ $10 constant GPIOR0_GPIOR04 \ General Purpose I/O Register 0
+ 3e $10 bitmask: GPIOR0.GPIOR04 \ General Purpose I/O Register 0
+ $8 constant GPIOR0_GPIOR03 \ General Purpose I/O Register 0
+ 3e $8 bitmask: GPIOR0.GPIOR03 \ General Purpose I/O Register 0
+ $4 constant GPIOR0_GPIOR02 \ General Purpose I/O Register 0
+ 3e $4 bitmask: GPIOR0.GPIOR02 \ General Purpose I/O Register 0
+ $2 constant GPIOR0_GPIOR01 \ General Purpose I/O Register 0
+ 3e $2 bitmask: GPIOR0.GPIOR01 \ General Purpose I/O Register 0
+ $1 constant GPIOR0_GPIOR00 \ General Purpose I/O Register 0
+ 3e $1 bitmask: GPIOR0.GPIOR00 \ General Purpose I/O Register 0
+$63 constant PRR2 \ Power Reduction Register 2
+ $f0 constant PRR2_Res \ Reserved Bit
+ 63 $f0 bitmask: PRR2.Res \ Reserved Bit
+ $f constant PRR2_PRRAM \ Power Reduction SRAMs
+ 63 $f bitmask: PRR2.PRRAM \ Power Reduction SRAMs
+$65 constant PRR1 \ Power Reduction Register 1
+ $80 constant PRR1_Res \ Reserved Bit
+ 65 $80 bitmask: PRR1.Res \ Reserved Bit
+ $40 constant PRR1_PRTRX24 \ Power Reduction Transceiver
+ 65 $40 bitmask: PRR1.PRTRX24 \ Power Reduction Transceiver
+ $20 constant PRR1_PRTIM5 \ Power Reduction Timer/Counter5
+ 65 $20 bitmask: PRR1.PRTIM5 \ Power Reduction Timer/Counter5
+ $10 constant PRR1_PRTIM4 \ Power Reduction Timer/Counter4
+ 65 $10 bitmask: PRR1.PRTIM4 \ Power Reduction Timer/Counter4
+ $8 constant PRR1_PRTIM3 \ Power Reduction Timer/Counter3
+ 65 $8 bitmask: PRR1.PRTIM3 \ Power Reduction Timer/Counter3
+ $1 constant PRR1_PRUSART1 \ Power Reduction USART1
+ 65 $1 bitmask: PRR1.PRUSART1 \ Power Reduction USART1
+$64 constant PRR0 \ Power Reduction Register0
+ $80 constant PRR0_PRTWI \ Power Reduction TWI
+ 64 $80 bitmask: PRR0.PRTWI \ Power Reduction TWI
+ $40 constant PRR0_PRTIM2 \ Power Reduction Timer/Counter2
+ 64 $40 bitmask: PRR0.PRTIM2 \ Power Reduction Timer/Counter2
+ $20 constant PRR0_PRTIM0 \ Power Reduction Timer/Counter0
+ 64 $20 bitmask: PRR0.PRTIM0 \ Power Reduction Timer/Counter0
+ $10 constant PRR0_PRPGA \ Power Reduction PGA
+ 64 $10 bitmask: PRR0.PRPGA \ Power Reduction PGA
+ $8 constant PRR0_PRTIM1 \ Power Reduction Timer/Counter1
+ 64 $8 bitmask: PRR0.PRTIM1 \ Power Reduction Timer/Counter1
+ $4 constant PRR0_PRSPI \ Power Reduction Serial Periphe
+ 64 $4 bitmask: PRR0.PRSPI \ Power Reduction Serial Periphe
+ $2 constant PRR0_PRUSART0 \ Power Reduction USART
+ 64 $2 bitmask: PRR0.PRUSART0 \ Power Reduction USART
+ $1 constant PRR0_PRADC \ Power Reduction ADC
+ 64 $1 bitmask: PRR0.PRADC \ Power Reduction ADC
+\ FLASH
+$75 constant NEMCR \ Flash Extended-Mode Control-Re
+ $40 constant NEMCR_ENEAM \ Enable Extended Address Mode f
+ 75 $40 bitmask: NEMCR.ENEAM \ Enable Extended Address Mode f
+ $30 constant NEMCR_AEAM \ Address for Extended Address M
+ 75 $30 bitmask: NEMCR.AEAM \ Address for Extended Address M
+$67 constant BGCR \ Reference Voltage Calibration
+ $80 constant BGCR_Res \ Reserved Bit
+ 67 $80 bitmask: BGCR.Res \ Reserved Bit
+ $78 constant BGCR_BGCAL_FINE \ Fine Calibration Bits
+ 67 $78 bitmask: BGCR.BGCAL_FINE \ Fine Calibration Bits
+ $7 constant BGCR_BGCAL \ Coarse Calibration Bits
+ 67 $7 bitmask: BGCR.BGCAL \ Coarse Calibration Bits
+\ PWRCTRL
+$139 constant TRXPR \ Transceiver Pin Register
+ $f0 constant TRXPR_Res \ Reserved
+ 139 $f0 bitmask: TRXPR.Res \ Reserved
+ $2 constant TRXPR_SLPTR \ Multi-purpose Transceiver Cont
+ 139 $2 bitmask: TRXPR.SLPTR \ Multi-purpose Transceiver Cont
+ $1 constant TRXPR_TRXRST \ Force Transceiver Reset
+ 139 $1 bitmask: TRXPR.TRXRST \ Force Transceiver Reset
+$135 constant DRTRAM0 \ Data Retention Configuration R
+ $c0 constant DRTRAM0_Res \ Reserved
+ 135 $c0 bitmask: DRTRAM0.Res \ Reserved
+ $20 constant DRTRAM0_DRTSWOK \ DRT Switch OK
+ 135 $20 bitmask: DRTRAM0.DRTSWOK \ DRT Switch OK
+ $10 constant DRTRAM0_ENDRT \ Enable SRAM Data Retention
+ 135 $10 bitmask: DRTRAM0.ENDRT \ Enable SRAM Data Retention
+$134 constant DRTRAM1 \ Data Retention Configuration R
+ $c0 constant DRTRAM1_Res \ Reserved
+ 134 $c0 bitmask: DRTRAM1.Res \ Reserved
+ $20 constant DRTRAM1_DRTSWOK \ DRT Switch OK
+ 134 $20 bitmask: DRTRAM1.DRTSWOK \ DRT Switch OK
+ $10 constant DRTRAM1_ENDRT \ Enable SRAM Data Retention
+ 134 $10 bitmask: DRTRAM1.ENDRT \ Enable SRAM Data Retention
+$133 constant DRTRAM2 \ Data Retention Configuration R
+ $40 constant DRTRAM2_Res \ Reserved Bit
+ 133 $40 bitmask: DRTRAM2.Res \ Reserved Bit
+ $20 constant DRTRAM2_DRTSWOK \ DRT Switch OK
+ 133 $20 bitmask: DRTRAM2.DRTSWOK \ DRT Switch OK
+ $10 constant DRTRAM2_ENDRT \ Enable SRAM Data Retention
+ 133 $10 bitmask: DRTRAM2.ENDRT \ Enable SRAM Data Retention
+$132 constant DRTRAM3 \ Data Retention Configuration R
+ $c0 constant DRTRAM3_Res \ Reserved
+ 132 $c0 bitmask: DRTRAM3.Res \ Reserved
+ $20 constant DRTRAM3_DRTSWOK \ DRT Switch OK
+ 132 $20 bitmask: DRTRAM3.DRTSWOK \ DRT Switch OK
+ $10 constant DRTRAM3_ENDRT \ Enable SRAM Data Retention
+ 132 $10 bitmask: DRTRAM3.ENDRT \ Enable SRAM Data Retention
+$130 constant LLDRL \ Low Leakage Voltage Regulator
+ $f0 constant LLDRL_Res \ Reserved
+ 130 $f0 bitmask: LLDRL.Res \ Reserved
+ $f constant LLDRL_LLDRL \ Low-Byte Data Register Bits
+ 130 $f bitmask: LLDRL.LLDRL \ Low-Byte Data Register Bits
+$131 constant LLDRH \ Low Leakage Voltage Regulator
+ $e0 constant LLDRH_Res \ Reserved
+ 131 $e0 bitmask: LLDRH.Res \ Reserved
+ $1f constant LLDRH_LLDRH \ High-Byte Data Register Bits
+ 131 $1f bitmask: LLDRH.LLDRH \ High-Byte Data Register Bits
+$12f constant LLCR \ Low Leakage Voltage Regulator
+ $c0 constant LLCR_Res \ Reserved Bit
+ 12f $c0 bitmask: LLCR.Res \ Reserved Bit
+ $20 constant LLCR_LLDONE \ Calibration Done
+ 12f $20 bitmask: LLCR.LLDONE \ Calibration Done
+ $10 constant LLCR_LLCOMP \ Comparator Output
+ 12f $10 bitmask: LLCR.LLCOMP \ Comparator Output
+ $8 constant LLCR_LLCAL \ Calibration Active
+ 12f $8 bitmask: LLCR.LLCAL \ Calibration Active
+ $4 constant LLCR_LLTCO \ Temperature Coefficient of Cur
+ 12f $4 bitmask: LLCR.LLTCO \ Temperature Coefficient of Cur
+ $2 constant LLCR_LLSHORT \ Short Lower Calibration Circui
+ 12f $2 bitmask: LLCR.LLSHORT \ Short Lower Calibration Circui
+ $1 constant LLCR_LLENCAL \ Enable Automatic Calibration
+ 12f $1 bitmask: LLCR.LLENCAL \ Enable Automatic Calibration
+$136 constant DPDS0 \ Port Driver Strength Register
+ $c0 constant DPDS0_PFDRV \ Driver Strength Port F
+ 136 $c0 bitmask: DPDS0.PFDRV \ Driver Strength Port F
+ $30 constant DPDS0_PEDRV \ Driver Strength Port E
+ 136 $30 bitmask: DPDS0.PEDRV \ Driver Strength Port E
+ $c constant DPDS0_PDDRV \ Driver Strength Port D
+ 136 $c bitmask: DPDS0.PDDRV \ Driver Strength Port D
+ $3 constant DPDS0_PBDRV \ Driver Strength Port B
+ 136 $3 bitmask: DPDS0.PBDRV \ Driver Strength Port B
+$137 constant DPDS1 \ Port Driver Strength Register
+ $fc constant DPDS1_Res \ Reserved
+ 137 $fc bitmask: DPDS1.Res \ Reserved
+ $3 constant DPDS1_PGDRV \ Driver Strength Port G
+ 137 $3 bitmask: DPDS1.PGDRV \ Driver Strength Port G
+$55 constant MCUCR \ MCU Control Register
+ $10 constant MCUCR_PUD \ Pull-up Disable
+ 55 $10 bitmask: MCUCR.PUD \ Pull-up Disable
+\ USART0_SPI
+$c0 constant UCSR0A \ USART0 MSPIM Control and Statu
+ $80 constant UCSR0A_RXC0 \ USART Receive Complete
+ c0 $80 bitmask: UCSR0A.RXC0 \ USART Receive Complete
+ $40 constant UCSR0A_TXC0 \ USART Transmit Complete
+ c0 $40 bitmask: UCSR0A.TXC0 \ USART Transmit Complete
+ $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
+ c0 $20 bitmask: UCSR0A.UDRE0 \ USART Data Register Empty
+$c1 constant UCSR0B \ USART0 MSPIM Control and Statu
+ $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
+ c1 $80 bitmask: UCSR0B.RXCIE0 \ RX Complete Interrupt Enable
+ $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
+ c1 $40 bitmask: UCSR0B.TXCIE0 \ TX Complete Interrupt Enable
+ $20 constant UCSR0B_UDRIE0 \ USART Data Register Empty Inte
+ c1 $20 bitmask: UCSR0B.UDRIE0 \ USART Data Register Empty Inte
+ $10 constant UCSR0B_RXEN0 \ Receiver Enable
+ c1 $10 bitmask: UCSR0B.RXEN0 \ Receiver Enable
+ $8 constant UCSR0B_TXEN0 \ Transmitter Enable
+ c1 $8 bitmask: UCSR0B.TXEN0 \ Transmitter Enable
+$c2 constant UCSR0C \ USART0 MSPIM Control and Statu
+ $4 constant UCSR0C_UDORD0 \ Data Order
+ c2 $4 bitmask: UCSR0C.UDORD0 \ Data Order
+ $2 constant UCSR0C_UCPHA0 \ Clock Phase
+ c2 $2 bitmask: UCSR0C.UCPHA0 \ Clock Phase
+ $1 constant UCSR0C_UCPOL0 \ Clock Polarity
+ c2 $1 bitmask: UCSR0C.UCPOL0 \ Clock Polarity
+\ USART1_SPI
+$c8 constant UCSR1A \ USART1 MSPIM Control and Statu
+ $80 constant UCSR1A_RXC1 \ USART Receive Complete
+ c8 $80 bitmask: UCSR1A.RXC1 \ USART Receive Complete
+ $40 constant UCSR1A_TXC1 \ USART Transmit Complete
+ c8 $40 bitmask: UCSR1A.TXC1 \ USART Transmit Complete
+ $20 constant UCSR1A_UDRE1 \ USART Data Register Empty
+ c8 $20 bitmask: UCSR1A.UDRE1 \ USART Data Register Empty
+$c9 constant UCSR1B \ USART1 MSPIM Control and Statu
+ $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable
+ c9 $80 bitmask: UCSR1B.RXCIE1 \ RX Complete Interrupt Enable
+ $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable
+ c9 $40 bitmask: UCSR1B.TXCIE1 \ TX Complete Interrupt Enable
+ $20 constant UCSR1B_UDRIE1 \ USART Data Register Empty Inte
+ c9 $20 bitmask: UCSR1B.UDRIE1 \ USART Data Register Empty Inte
+ $10 constant UCSR1B_RXEN1 \ Receiver Enable
+ c9 $10 bitmask: UCSR1B.RXEN1 \ Receiver Enable
+ $8 constant UCSR1B_TXEN1 \ Transmitter Enable
+ c9 $8 bitmask: UCSR1B.TXEN1 \ Transmitter Enable
+$ca constant UCSR1C \ USART1 MSPIM Control and Statu
+ $4 constant UCSR1C_UDORD1 \ Data Order
+ ca $4 bitmask: UCSR1C.UDORD1 \ Data Order
+ $2 constant UCSR1C_UCPHA1 \ Clock Phase
+ ca $2 bitmask: UCSR1C.UCPHA1 \ Clock Phase
+ $1 constant UCSR1C_UCPOL1 \ Clock Polarity
+ ca $1 bitmask: UCSR1C.UCPOL1 \ Clock Polarity
diff --git a/amforth-6.5/avr8/devices/atmega2564rfr2/device.py b/amforth-6.5/avr8/devices/atmega2564rfr2/device.py
new file mode 100644
index 0000000..92acde5
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega2564rfr2/device.py
@@ -0,0 +1,1104 @@
+# Generated Automatically
+
+# Partname ATmega2564RFR2
+
+MCUREGS = {
+# Interrupt Vectors
+ 'INT0Addr' : '#2', # External Interrupt Request 0
+ 'INT1Addr' : '#4', # External Interrupt Request 1
+ 'INT2Addr' : '#6', # External Interrupt Request 2
+ 'INT3Addr' : '#8', # External Interrupt Request 3
+ 'INT4Addr' : '#10', # External Interrupt Request 4
+ 'INT5Addr' : '#12', # External Interrupt Request 5
+ 'INT6Addr' : '#14', # External Interrupt Request 6
+ 'INT7Addr' : '#16', # External Interrupt Request 7
+ 'PCINT0Addr' : '#18', # Pin Change Interrupt Request 0
+ 'PCINT1Addr' : '#20', # Pin Change Interrupt Request 1
+ 'PCINT2Addr' : '#22', # Pin Change Interrupt Request 2
+ 'WDTAddr' : '#24', # Watchdog Time-out Interrupt
+ 'TIMER2_COMPAAddr' : '#26', # Timer/Counter2 Compare Match A
+ 'TIMER2_COMPBAddr' : '#28', # Timer/Counter2 Compare Match B
+ 'TIMER2_OVFAddr' : '#30', # Timer/Counter2 Overflow
+ 'TIMER1_CAPTAddr' : '#32', # Timer/Counter1 Capture Event
+ 'TIMER1_COMPAAddr' : '#34', # Timer/Counter1 Compare Match A
+ 'TIMER1_COMPBAddr' : '#36', # Timer/Counter1 Compare Match B
+ 'TIMER1_COMPCAddr' : '#38', # Timer/Counter1 Compare Match C
+ 'TIMER1_OVFAddr' : '#40', # Timer/Counter1 Overflow
+ 'TIMER0_COMPAAddr' : '#42', # Timer/Counter0 Compare Match A
+ 'TIMER0_COMPBAddr' : '#44', # Timer/Counter0 Compare Match B
+ 'TIMER0_OVFAddr' : '#46', # Timer/Counter0 Overflow
+ 'SPI_STCAddr' : '#48', # SPI Serial Transfer Complete
+ 'USART0_RXAddr' : '#50', # USART0, Rx Complete
+ 'USART0_UDREAddr' : '#52', # USART0 Data register Empty
+ 'USART0_TXAddr' : '#54', # USART0, Tx Complete
+ 'ANALOG_COMPAddr' : '#56', # Analog Comparator
+ 'ADCAddr' : '#58', # ADC Conversion Complete
+ 'EE_READYAddr' : '#60', # EEPROM Ready
+ 'TIMER3_CAPTAddr' : '#62', # Timer/Counter3 Capture Event
+ 'TIMER3_COMPAAddr' : '#64', # Timer/Counter3 Compare Match A
+ 'TIMER3_COMPBAddr' : '#66', # Timer/Counter3 Compare Match B
+ 'TIMER3_COMPCAddr' : '#68', # Timer/Counter3 Compare Match C
+ 'TIMER3_OVFAddr' : '#70', # Timer/Counter3 Overflow
+ 'USART1_RXAddr' : '#72', # USART1, Rx Complete
+ 'USART1_UDREAddr' : '#74', # USART1 Data register Empty
+ 'USART1_TXAddr' : '#76', # USART1, Tx Complete
+ 'TWIAddr' : '#78', # 2-wire Serial Interface
+ 'SPM_READYAddr' : '#80', # Store Program Memory Read
+ 'TIMER4_CAPTAddr' : '#82', # Timer/Counter4 Capture Event
+ 'TIMER4_COMPAAddr' : '#84', # Timer/Counter4 Compare Match A
+ 'TIMER4_COMPBAddr' : '#86', # Timer/Counter4 Compare Match B
+ 'TIMER4_COMPCAddr' : '#88', # Timer/Counter4 Compare Match C
+ 'TIMER4_OVFAddr' : '#90', # Timer/Counter4 Overflow
+ 'TIMER5_CAPTAddr' : '#92', # Timer/Counter5 Capture Event
+ 'TIMER5_COMPAAddr' : '#94', # Timer/Counter5 Compare Match A
+ 'TIMER5_COMPBAddr' : '#96', # Timer/Counter5 Compare Match B
+ 'TIMER5_COMPCAddr' : '#98', # Timer/Counter5 Compare Match C
+ 'TIMER5_OVFAddr' : '#100', # Timer/Counter5 Overflow
+ 'USART2_RXAddr' : '#102', # USART2, Rx Complete
+ 'USART2_UDREAddr' : '#104', # USART2 Data register Empty
+ 'USART2_TXAddr' : '#106', # USART2, Tx Complete
+ 'USART3_RXAddr' : '#108', # USART3, Rx Complete
+ 'USART3_UDREAddr' : '#110', # USART3 Data register Empty
+ 'USART3_TXAddr' : '#112', # USART3, Tx Complete
+ 'TRX24_PLL_LOCKAddr' : '#114', # TRX24 - PLL lock interrupt
+ 'TRX24_PLL_UNLOCKAddr' : '#116', # TRX24 - PLL unlock interrupt
+ 'TRX24_RX_STARTAddr' : '#118', # TRX24 - Receive start interrupt
+ 'TRX24_RX_ENDAddr' : '#120', # TRX24 - RX_END interrupt
+ 'TRX24_CCA_ED_DONEAddr' : '#122', # TRX24 - CCA/ED done interrupt
+ 'TRX24_XAH_AMIAddr' : '#124', # TRX24 - XAH - AMI
+ 'TRX24_TX_ENDAddr' : '#126', # TRX24 - TX_END interrupt
+ 'TRX24_AWAKEAddr' : '#128', # TRX24 AWAKE - tranceiver is reaching state TRX_OFF
+ 'SCNT_CMP1Addr' : '#130', # Symbol counter - compare match 1 interrupt
+ 'SCNT_CMP2Addr' : '#132', # Symbol counter - compare match 2 interrupt
+ 'SCNT_CMP3Addr' : '#134', # Symbol counter - compare match 3 interrupt
+ 'SCNT_OVFLAddr' : '#136', # Symbol counter - overflow interrupt
+ 'SCNT_BACKOFFAddr' : '#138', # Symbol counter - backoff interrupt
+ 'AES_READYAddr' : '#140', # AES engine ready interrupt
+ 'BAT_LOWAddr' : '#142', # Battery monitor indicates supply voltage below threshold
+ 'TRX24_TX_STARTAddr' : '#144', # TRX24 TX start interrupt
+ 'TRX24_AMI0Addr' : '#146', # Address match interrupt of address filter 0
+ 'TRX24_AMI1Addr' : '#148', # Address match interrupt of address filter 1
+ 'TRX24_AMI2Addr' : '#150', # Address match interrupt of address filter 2
+ 'TRX24_AMI3Addr' : '#152', # Address match interrupt of address filter 3
+
+# Module ANALOG_COMPARATOR
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
+ 'ACSR' : '$50', # Analog Comparator Control And
+ 'ACSR_ACD': '$80', # Analog Comparator Disable
+ 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
+ 'ACSR_ACO': '$20', # Analog Compare Output
+ 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
+ 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
+ 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
+ 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
+ 'DIDR1' : '$7f', # Digital Input Disable Register
+ 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
+ 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
+
+# Module USART0
+ 'UDR0' : '$c6', # USART0 I/O Data Register
+ 'UCSR0A' : '$c0', # USART0 Control and Status Regi
+ 'UCSR0A_RXC0': '$80', # USART Receive Complete
+ 'UCSR0A_TXC0': '$40', # USART Transmit Complete
+ 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
+ 'UCSR0A_FE0': '$10', # Frame Error
+ 'UCSR0A_DOR0': '$8', # Data OverRun
+ 'UCSR0A_UPE0': '$4', # USART Parity Error
+ 'UCSR0A_U2X0': '$2', # Double the USART Transmission
+ 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
+ 'UCSR0B' : '$c1', # USART0 Control and Status Regi
+ 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
+ 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
+ 'UCSR0B_UDRIE0': '$20', # USART Data Register Empty Inte
+ 'UCSR0B_RXEN0': '$10', # Receiver Enable
+ 'UCSR0B_TXEN0': '$8', # Transmitter Enable
+ 'UCSR0B_UCSZ02': '$4', # Character Size
+ 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
+ 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
+ 'UCSR0C' : '$c2', # USART0 Control and Status Regi
+ 'UCSR0C_UMSEL0': '$c0', # USART Mode Select
+ 'UCSR0C_UPM0': '$30', # Parity Mode
+ 'UCSR0C_USBS0': '$8', # Stop Bit Select
+ 'UCSR0C_UCSZ0': '$6', # Character Size
+ 'UCSR0C_UCPOL0': '$1', # Clock Polarity
+ 'UBRR0' : '$c4', # USART0 Baud Rate Register Byt
+
+# Module USART1
+ 'UDR1' : '$ce', # USART1 I/O Data Register
+ 'UCSR1A' : '$c8', # USART1 Control and Status Regi
+ 'UCSR1A_RXC1': '$80', # USART Receive Complete
+ 'UCSR1A_TXC1': '$40', # USART Transmit Complete
+ 'UCSR1A_UDRE1': '$20', # USART Data Register Empty
+ 'UCSR1A_FE1': '$10', # Frame Error
+ 'UCSR1A_DOR1': '$8', # Data OverRun
+ 'UCSR1A_UPE1': '$4', # USART Parity Error
+ 'UCSR1A_U2X1': '$2', # Double the USART Transmission
+ 'UCSR1A_MPCM1': '$1', # Multi-processor Communication
+ 'UCSR1B' : '$c9', # USART1 Control and Status Regi
+ 'UCSR1B_RXCIE1': '$80', # RX Complete Interrupt Enable
+ 'UCSR1B_TXCIE1': '$40', # TX Complete Interrupt Enable
+ 'UCSR1B_UDRIE1': '$20', # USART Data Register Empty Inte
+ 'UCSR1B_RXEN1': '$10', # Receiver Enable
+ 'UCSR1B_TXEN1': '$8', # Transmitter Enable
+ 'UCSR1B_UCSZ12': '$4', # Character Size
+ 'UCSR1B_RXB81': '$2', # Receive Data Bit 8
+ 'UCSR1B_TXB81': '$1', # Transmit Data Bit 8
+ 'UCSR1C' : '$ca', # USART1 Control and Status Regi
+ 'UCSR1C_UMSEL1': '$c0', # USART Mode Select
+ 'UCSR1C_UPM1': '$30', # Parity Mode
+ 'UCSR1C_USBS1': '$8', # Stop Bit Select
+ 'UCSR1C_UCSZ1': '$6', # Character Size
+ 'UCSR1C_UCPOL1': '$1', # Clock Polarity
+ 'UBRR1' : '$cc', # USART1 Baud Rate Register Byt
+
+# Module TWI
+ 'TWAMR' : '$bd', # TWI (Slave) Address Mask Regis
+ 'TWAMR_TWAM': '$fe', # TWI Address Mask
+ 'TWAMR_Res': '$1', # Reserved Bit
+ 'TWBR' : '$b8', # TWI Bit Rate Register
+ 'TWCR' : '$bc', # TWI Control Register
+ 'TWCR_TWINT': '$80', # TWI Interrupt Flag
+ 'TWCR_TWEA': '$40', # TWI Enable Acknowledge Bit
+ 'TWCR_TWSTA': '$20', # TWI START Condition Bit
+ 'TWCR_TWSTO': '$10', # TWI STOP Condition Bit
+ 'TWCR_TWWC': '$8', # TWI Write Collision Flag
+ 'TWCR_TWEN': '$4', # TWI Enable Bit
+ 'TWCR_Res': '$2', # Reserved Bit
+ 'TWCR_TWIE': '$1', # TWI Interrupt Enable
+ 'TWSR' : '$b9', # TWI Status Register
+ 'TWSR_TWS': '$f8', # TWI Status
+ 'TWSR_Res': '$4', # Reserved Bit
+ 'TWSR_TWPS': '$3', # TWI Prescaler Bits
+ 'TWDR' : '$bb', # TWI Data Register
+ 'TWAR' : '$ba', # TWI (Slave) Address Register
+ 'TWAR_TWA': '$fe', # TWI (Slave) Address
+ 'TWAR_TWGCE': '$1', # TWI General Call Recognition E
+
+# Module SPI
+ 'SPCR' : '$4c', # SPI Control Register
+ 'SPCR_SPIE': '$80', # SPI Interrupt Enable
+ 'SPCR_SPE': '$40', # SPI Enable
+ 'SPCR_DORD': '$20', # Data Order
+ 'SPCR_MSTR': '$10', # Master/Slave Select
+ 'SPCR_CPOL': '$8', # Clock polarity
+ 'SPCR_CPHA': '$4', # Clock Phase
+ 'SPCR_SPR': '$3', # SPI Clock Rate Select 1 and 0
+ 'SPSR' : '$4d', # SPI Status Register
+ 'SPSR_SPIF': '$80', # SPI Interrupt Flag
+ 'SPSR_WCOL': '$40', # Write Collision Flag
+ 'SPSR_Res': '$3e', # Reserved
+ 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
+ 'SPDR' : '$4e', # SPI Data Register
+
+# Module PORTA
+ 'PORTA' : '$22', # Port A Data Register
+ 'DDRA' : '$21', # Port A Data Direction Register
+ 'PINA' : '$20', # Port A Input Pins Address
+
+# Module PORTB
+ 'PORTB' : '$25', # Port B Data Register
+ 'DDRB' : '$24', # Port B Data Direction Register
+ 'PINB' : '$23', # Port B Input Pins Address
+
+# Module PORTC
+ 'PORTC' : '$28', # Port C Data Register
+ 'DDRC' : '$27', # Port C Data Direction Register
+ 'PINC' : '$26', # Port C Input Pins Address
+
+# Module PORTD
+ 'PORTD' : '$2b', # Port D Data Register
+ 'DDRD' : '$2a', # Port D Data Direction Register
+ 'PIND' : '$29', # Port D Input Pins Address
+
+# Module PORTE
+ 'PORTE' : '$2e', # Port E Data Register
+ 'DDRE' : '$2d', # Port E Data Direction Register
+ 'PINE' : '$2c', # Port E Input Pins Address
+
+# Module PORTF
+ 'PORTF' : '$31', # Port F Data Register
+ 'DDRF' : '$30', # Port F Data Direction Register
+ 'PINF' : '$2f', # Port F Input Pins Address
+
+# Module PORTG
+ 'PORTG' : '$34', # Port G Data Register
+ 'DDRG' : '$33', # Port G Data Direction Register
+ 'PING' : '$32', # Port G Input Pins Address
+
+# Module TIMER_COUNTER_0
+ 'OCR0B' : '$48', # Timer/Counter0 Output Compare
+ 'OCR0A' : '$47', # Timer/Counter0 Output Compare
+ 'TCNT0' : '$46', # Timer/Counter0 Register
+ 'TCCR0B' : '$45', # Timer/Counter0 Control Registe
+ 'TCCR0B_FOC0A': '$80', # Force Output Compare A
+ 'TCCR0B_FOC0B': '$40', # Force Output Compare B
+ 'TCCR0B_Res': '$30', # Reserved Bit
+ 'TCCR0B_WGM02': '$8', #
+ 'TCCR0B_CS0': '$7', # Clock Select
+ 'TCCR0A' : '$44', # Timer/Counter0 Control Registe
+ 'TCCR0A_COM0A': '$c0', # Compare Match Output A Mode
+ 'TCCR0A_COM0B': '$30', # Compare Match Output B Mode
+ 'TCCR0A_Res': '$c', # Reserved Bit
+ 'TCCR0A_WGM0': '$3', # Waveform Generation Mode
+ 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
+ 'TIMSK0_Res': '$f8', # Reserved
+ 'TIMSK0_OCIE0B': '$4', # Timer/Counter0 Output Compare
+ 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
+ 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
+ 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
+ 'TIFR0_Res': '$f8', # Reserved
+ 'TIFR0_OCF0B': '$4', # Timer/Counter0 Output Compare
+ 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
+ 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_Res': '$7c', # Reserved
+ 'GTCCR_PSRASY': '$2', # Prescaler Reset Timer/Counter2
+ 'GTCCR_PSRSYNC': '$1', # Prescaler Reset for Synchronou
+
+# Module TIMER_COUNTER_2
+ 'TIMSK2' : '$70', # Timer/Counter Interrupt Mask r
+ 'TIMSK2_Res': '$f8', # Reserved Bit
+ 'TIMSK2_OCIE2B': '$4', # Timer/Counter2 Output Compare
+ 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
+ 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
+ 'TIFR2' : '$37', # Timer/Counter Interrupt Flag R
+ 'TIFR2_Res': '$f8', # Reserved Bit
+ 'TIFR2_OCF2B': '$4', # Output Compare Flag 2 B
+ 'TIFR2_OCF2A': '$2', # Output Compare Flag 2 A
+ 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
+ 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
+ 'TCCR2A_COM2A': '$c0', # Compare Match Output A Mode
+ 'TCCR2A_COM2B': '$30', # Compare Match Output B Mode
+ 'TCCR2A_Res': '$c', # Reserved
+ 'TCCR2A_WGM2': '$3', # Waveform Generation Mode
+ 'TCCR2B' : '$b1', # Timer/Counter2 Control Registe
+ 'TCCR2B_FOC2A': '$80', # Force Output Compare A
+ 'TCCR2B_FOC2B': '$40', # Force Output Compare B
+ 'TCCR2B_Res': '$30', # Reserved
+ 'TCCR2B_WGM22': '$8', # Waveform Generation Mode
+ 'TCCR2B_CS2': '$7', # Clock Select
+ 'TCNT2' : '$b2', # Timer/Counter2
+ 'OCR2B' : '$b4', # Timer/Counter2 Output Compare
+ 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
+ 'ASSR' : '$b6', # Asynchronous Status Register
+ 'ASSR_EXCLKAMR': '$80', # Enable External Clock Input fo
+ 'ASSR_EXCLK': '$40', # Enable External Clock Input
+ 'ASSR_AS2': '$20', # Timer/Counter2 Asynchronous Mo
+ 'ASSR_TCN2UB': '$10', # Timer/Counter2 Update Busy
+ 'ASSR_OCR2AUB': '$8', # Timer/Counter2 Output Compare
+ 'ASSR_OCR2BUB': '$4', # Timer/Counter2 Output Compare
+ 'ASSR_TCR2AUB': '$2', # Timer/Counter2 Control Registe
+ 'ASSR_TCR2BUB': '$1', # Timer/Counter2 Control Registe
+ 'GTCCR' : '$43', # General Timer Counter Control
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSRASY': '$2', # Prescaler Reset Timer/Counter2
+
+# Module WATCHDOG
+ 'WDTCSR' : '$60', # Watchdog Timer Control Registe
+ 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
+ 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
+ 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
+ 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
+ 'WDTCSR_WDE': '$8', # Watch Dog Enable
+
+# Module TIMER_COUNTER_5
+ 'TCCR5A' : '$120', # Timer/Counter5 Control Registe
+ 'TCCR5A_COM5A': '$c0', # Compare Output Mode for Channe
+ 'TCCR5A_COM5B': '$30', # Compare Output Mode for Channe
+ 'TCCR5A_COM5C': '$c', # Compare Output Mode for Channe
+ 'TCCR5A_WGM5': '$3', # Waveform Generation Mode
+ 'TCCR5B' : '$121', # Timer/Counter5 Control Registe
+ 'TCCR5B_ICNC5': '$80', # Input Capture 5 Noise Cancelle
+ 'TCCR5B_ICES5': '$40', # Input Capture 5 Edge Select
+ 'TCCR5B_Res': '$20', # Reserved Bit
+ 'TCCR5B_WGM5': '$18', # Waveform Generation Mode
+ 'TCCR5B_CS5': '$7', # Clock Select
+ 'TCCR5C' : '$122', # Timer/Counter5 Control Registe
+ 'TCCR5C_FOC5A': '$80', # Force Output Compare for Chann
+ 'TCCR5C_FOC5B': '$40', # Force Output Compare for Chann
+ 'TCCR5C_FOC5C': '$20', # Force Output Compare for Chann
+ 'TCCR5C_Res': '$1f', # Reserved
+ 'TCNT5' : '$124', # Timer/Counter5 Bytes
+ 'OCR5A' : '$128', # Timer/Counter5 Output Compare
+ 'OCR5B' : '$12a', # Timer/Counter5 Output Compare
+ 'OCR5C' : '$12c', # Timer/Counter5 Output Compare
+ 'ICR5' : '$126', # Timer/Counter5 Input Capture R
+ 'TIMSK5' : '$73', # Timer/Counter5 Interrupt Mask
+ 'TIMSK5_Res': '$c0', # Reserved Bit
+ 'TIMSK5_ICIE5': '$20', # Timer/Counter5 Input Capture I
+ 'TIMSK5_Res': '$10', # Reserved Bit
+ 'TIMSK5_OCIE5C': '$8', # Timer/Counter5 Output Compare
+ 'TIMSK5_OCIE5B': '$4', # Timer/Counter5 Output Compare
+ 'TIMSK5_OCIE5A': '$2', # Timer/Counter5 Output Compare
+ 'TIMSK5_TOIE5': '$1', # Timer/Counter5 Overflow Interr
+ 'TIFR5' : '$3a', # Timer/Counter5 Interrupt Flag
+ 'TIFR5_Res': '$c0', # Reserved Bit
+ 'TIFR5_ICF5': '$20', # Timer/Counter5 Input Capture F
+ 'TIFR5_Res': '$10', # Reserved Bit
+ 'TIFR5_OCF5C': '$8', # Timer/Counter5 Output Compare
+ 'TIFR5_OCF5B': '$4', # Timer/Counter5 Output Compare
+ 'TIFR5_OCF5A': '$2', # Timer/Counter5 Output Compare
+ 'TIFR5_TOV5': '$1', # Timer/Counter5 Overflow Flag
+
+# Module TIMER_COUNTER_4
+ 'TCCR4A' : '$a0', # Timer/Counter4 Control Registe
+ 'TCCR4A_COM4A': '$c0', # Compare Output Mode for Channe
+ 'TCCR4A_COM4B': '$30', # Compare Output Mode for Channe
+ 'TCCR4A_COM4C': '$c', # Compare Output Mode for Channe
+ 'TCCR4A_WGM4': '$3', # Waveform Generation Mode
+ 'TCCR4B' : '$a1', # Timer/Counter4 Control Registe
+ 'TCCR4B_ICNC4': '$80', # Input Capture 4 Noise Cancelle
+ 'TCCR4B_ICES4': '$40', # Input Capture 4 Edge Select
+ 'TCCR4B_Res': '$20', # Reserved Bit
+ 'TCCR4B_WGM4': '$18', # Waveform Generation Mode
+ 'TCCR4B_CS4': '$7', # Clock Select
+ 'TCCR4C' : '$a2', # Timer/Counter4 Control Registe
+ 'TCCR4C_FOC4A': '$80', # Force Output Compare for Chann
+ 'TCCR4C_FOC4B': '$40', # Force Output Compare for Chann
+ 'TCCR4C_FOC4C': '$20', # Force Output Compare for Chann
+ 'TCCR4C_Res': '$1f', # Reserved
+ 'TCNT4' : '$a4', # Timer/Counter4 Bytes
+ 'OCR4A' : '$a8', # Timer/Counter4 Output Compare
+ 'OCR4B' : '$aa', # Timer/Counter4 Output Compare
+ 'OCR4C' : '$ac', # Timer/Counter4 Output Compare
+ 'ICR4' : '$a6', # Timer/Counter4 Input Capture R
+ 'TIMSK4' : '$72', # Timer/Counter4 Interrupt Mask
+ 'TIMSK4_Res': '$c0', # Reserved Bit
+ 'TIMSK4_ICIE4': '$20', # Timer/Counter4 Input Capture I
+ 'TIMSK4_Res': '$10', # Reserved Bit
+ 'TIMSK4_OCIE4C': '$8', # Timer/Counter4 Output Compare
+ 'TIMSK4_OCIE4B': '$4', # Timer/Counter4 Output Compare
+ 'TIMSK4_OCIE4A': '$2', # Timer/Counter4 Output Compare
+ 'TIMSK4_TOIE4': '$1', # Timer/Counter4 Overflow Interr
+ 'TIFR4' : '$39', # Timer/Counter4 Interrupt Flag
+ 'TIFR4_Res': '$c0', # Reserved Bit
+ 'TIFR4_ICF4': '$20', # Timer/Counter4 Input Capture F
+ 'TIFR4_Res': '$10', # Reserved Bit
+ 'TIFR4_OCF4C': '$8', # Timer/Counter4 Output Compare
+ 'TIFR4_OCF4B': '$4', # Timer/Counter4 Output Compare
+ 'TIFR4_OCF4A': '$2', # Timer/Counter4 Output Compare
+ 'TIFR4_TOV4': '$1', # Timer/Counter4 Overflow Flag
+
+# Module TIMER_COUNTER_3
+ 'TCCR3A' : '$90', # Timer/Counter3 Control Registe
+ 'TCCR3A_COM3A': '$c0', # Compare Output Mode for Channe
+ 'TCCR3A_COM3B': '$30', # Compare Output Mode for Channe
+ 'TCCR3A_COM3C': '$c', # Compare Output Mode for Channe
+ 'TCCR3A_WGM3': '$3', # Waveform Generation Mode
+ 'TCCR3B' : '$91', # Timer/Counter3 Control Registe
+ 'TCCR3B_ICNC3': '$80', # Input Capture 3 Noise Cancelle
+ 'TCCR3B_ICES3': '$40', # Input Capture 3 Edge Select
+ 'TCCR3B_Res': '$20', # Reserved Bit
+ 'TCCR3B_WGM3': '$18', # Waveform Generation Mode
+ 'TCCR3B_CS3': '$7', # Clock Select
+ 'TCCR3C' : '$92', # Timer/Counter3 Control Registe
+ 'TCCR3C_FOC3A': '$80', # Force Output Compare for Chann
+ 'TCCR3C_FOC3B': '$40', # Force Output Compare for Chann
+ 'TCCR3C_FOC3C': '$20', # Force Output Compare for Chann
+ 'TCCR3C_Res': '$1f', # Reserved
+ 'TCNT3' : '$94', # Timer/Counter3 Bytes
+ 'OCR3A' : '$98', # Timer/Counter3 Output Compare
+ 'OCR3B' : '$9a', # Timer/Counter3 Output Compare
+ 'OCR3C' : '$9c', # Timer/Counter3 Output Compare
+ 'ICR3' : '$96', # Timer/Counter3 Input Capture R
+ 'TIMSK3' : '$71', # Timer/Counter3 Interrupt Mask
+ 'TIMSK3_Res': '$c0', # Reserved Bit
+ 'TIMSK3_ICIE3': '$20', # Timer/Counter3 Input Capture I
+ 'TIMSK3_Res': '$10', # Reserved Bit
+ 'TIMSK3_OCIE3C': '$8', # Timer/Counter3 Output Compare
+ 'TIMSK3_OCIE3B': '$4', # Timer/Counter3 Output Compare
+ 'TIMSK3_OCIE3A': '$2', # Timer/Counter3 Output Compare
+ 'TIMSK3_TOIE3': '$1', # Timer/Counter3 Overflow Interr
+ 'TIFR3' : '$38', # Timer/Counter3 Interrupt Flag
+ 'TIFR3_Res': '$c0', # Reserved Bit
+ 'TIFR3_ICF3': '$20', # Timer/Counter3 Input Capture F
+ 'TIFR3_Res': '$10', # Reserved Bit
+ 'TIFR3_OCF3C': '$8', # Timer/Counter3 Output Compare
+ 'TIFR3_OCF3B': '$4', # Timer/Counter3 Output Compare
+ 'TIFR3_OCF3A': '$2', # Timer/Counter3 Output Compare
+ 'TIFR3_TOV3': '$1', # Timer/Counter3 Overflow Flag
+
+# Module TIMER_COUNTER_1
+ 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
+ 'TCCR1A_COM1A': '$c0', # Compare Output Mode for Channe
+ 'TCCR1A_COM1B': '$30', # Compare Output Mode for Channe
+ 'TCCR1A_COM1C': '$c', # Compare Output Mode for Channe
+ 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
+ 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
+ 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Cancelle
+ 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
+ 'TCCR1B_Res': '$20', # Reserved Bit
+ 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
+ 'TCCR1B_CS1': '$7', # Clock Select
+ 'TCCR1C' : '$82', # Timer/Counter1 Control Registe
+ 'TCCR1C_FOC1A': '$80', # Force Output Compare for Chann
+ 'TCCR1C_FOC1B': '$40', # Force Output Compare for Chann
+ 'TCCR1C_FOC1C': '$20', # Force Output Compare for Chann
+ 'TCCR1C_Res': '$1f', # Reserved
+ 'TCNT1' : '$84', # Timer/Counter1 Bytes
+ 'OCR1A' : '$88', # Timer/Counter1 Output Compare
+ 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
+ 'OCR1C' : '$8c', # Timer/Counter1 Output Compare
+ 'ICR1' : '$86', # Timer/Counter1 Input Capture R
+ 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
+ 'TIMSK1_Res': '$c0', # Reserved Bit
+ 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
+ 'TIMSK1_Res': '$10', # Reserved Bit
+ 'TIMSK1_OCIE1C': '$8', # Timer/Counter1 Output Compare
+ 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
+ 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
+ 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
+ 'TIFR1' : '$36', # Timer/Counter1 Interrupt Flag
+ 'TIFR1_Res': '$c0', # Reserved Bit
+ 'TIFR1_ICF1': '$20', # Timer/Counter1 Input Capture F
+ 'TIFR1_Res': '$10', # Reserved Bit
+ 'TIFR1_OCF1C': '$8', # Timer/Counter1 Output Compare
+ 'TIFR1_OCF1B': '$4', # Timer/Counter1 Output Compare
+ 'TIFR1_OCF1A': '$2', # Timer/Counter1 Output Compare
+ 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
+
+# Module TRX24
+ 'PARCR' : '$138', # Power Amplifier Ramp up/down C
+ 'PARCR_PALTD': '$e0', # ext. PA Ramp Down Lead Time
+ 'PARCR_PALTU': '$1c', # ext. PA Ramp Up Lead Time
+ 'PARCR_PARDFI': '$2', # Power Amplifier Ramp Down Freq
+ 'PARCR_PARUFI': '$1', # Power Amplifier Ramp Up Freque
+ 'MAFSA0L' : '$10e', # Transceiver MAC Short Address
+ 'MAFSA0L_MAFSA0L': '$ff', # MAC Short Address low Byte for
+ 'MAFSA0H' : '$10f', # Transceiver MAC Short Address
+ 'MAFSA0H_MAFSA0H': '$ff', # MAC Short Address high Byte fo
+ 'MAFPA0L' : '$110', # Transceiver Personal Area Netw
+ 'MAFPA0L_MAFPA0L': '$ff', # MAC Personal Area Network ID l
+ 'MAFPA0H' : '$111', # Transceiver Personal Area Netw
+ 'MAFPA0H_MAFPA0H': '$ff', # MAC Personal Area Network ID h
+ 'MAFSA1L' : '$112', # Transceiver MAC Short Address
+ 'MAFSA1L_MAFSA1L': '$ff', # MAC Short Address low Byte for
+ 'MAFSA1H' : '$113', # Transceiver MAC Short Address
+ 'MAFSA1H_MAFSA1H': '$ff', # MAC Short Address high Byte fo
+ 'MAFPA1L' : '$114', # Transceiver Personal Area Netw
+ 'MAFPA1L_MAFPA1L': '$ff', # MAC Personal Area Network ID l
+ 'MAFPA1H' : '$115', # Transceiver Personal Area Netw
+ 'MAFPA1H_MAFPA1H': '$ff', # MAC Personal Area Network ID h
+ 'MAFSA2L' : '$116', # Transceiver MAC Short Address
+ 'MAFSA2L_MAFSA2L': '$ff', # MAC Short Address low Byte for
+ 'MAFSA2H' : '$117', # Transceiver MAC Short Address
+ 'MAFSA2H_MAFSA2H': '$ff', # MAC Short Address high Byte fo
+ 'MAFPA2L' : '$118', # Transceiver Personal Area Netw
+ 'MAFPA2L_MAFPA2L': '$ff', # MAC Personal Area Network ID l
+ 'MAFPA2H' : '$119', # Transceiver Personal Area Netw
+ 'MAFPA2H_MAFPA2H': '$ff', # MAC Personal Area Network ID h
+ 'MAFSA3L' : '$11a', # Transceiver MAC Short Address
+ 'MAFSA3L_MAFSA3L': '$ff', # MAC Short Address low Byte for
+ 'MAFSA3H' : '$11b', # Transceiver MAC Short Address
+ 'MAFSA3H_MAFSA3H': '$ff', # MAC Short Address high Byte fo
+ 'MAFPA3L' : '$11c', # Transceiver Personal Area Netw
+ 'MAFPA3L_MAFPA3L': '$ff', # MAC Personal Area Network ID l
+ 'MAFPA3H' : '$11d', # Transceiver Personal Area Netw
+ 'MAFPA3H_MAFPA3H': '$ff', # MAC Personal Area Network ID h
+ 'MAFCR0' : '$10c', # Multiple Address Filter Config
+ 'MAFCR0_Res': '$f0', # Reserved Bit
+ 'MAFCR0_MAF3EN': '$8', # Multiple Address Filter 3 Enab
+ 'MAFCR0_MAF2EN': '$4', # Multiple Address Filter 2 Enab
+ 'MAFCR0_MAF1EN': '$2', # Multiple Address Filter 1 Enab
+ 'MAFCR0_MAF0EN': '$1', # Multiple Address Filter 0 Enab
+ 'MAFCR1' : '$10d', # Multiple Address Filter Config
+ 'MAFCR1_AACK_3_SET_PD': '$80', # Set Data Pending bit for addre
+ 'MAFCR1_AACK_3_I_AM_COORD': '$40', # Enable PAN Coordinator mode fo
+ 'MAFCR1_AACK_2_SET_PD': '$20', # Set Data Pending bit for addre
+ 'MAFCR1_AACK_2_I_AM_COORD': '$10', # Enable PAN Coordinator mode fo
+ 'MAFCR1_AACK_1_SET_PD': '$8', # Set Data Pending bit for addre
+ 'MAFCR1_AACK_1_I_AM_COORD': '$4', # Enable PAN Coordinator mode fo
+ 'MAFCR1_AACK_0_SET_PD': '$2', # Set Data Pending bit for addre
+ 'MAFCR1_AACK_0_I_AM_COORD': '$1', # Enable PAN Coordinator mode fo
+ 'AES_CTRL' : '$13c', # AES Control Register
+ 'AES_CTRL_AES_REQUEST': '$80', # Request AES Operation.
+ 'AES_CTRL_Res': '$40', # Reserved Bit
+ 'AES_CTRL_AES_MODE': '$20', # Set AES Operation Mode
+ 'AES_CTRL_Res': '$10', # Reserved Bit
+ 'AES_CTRL_AES_DIR': '$8', # Set AES Operation Direction
+ 'AES_CTRL_AES_IM': '$4', # AES Interrupt Enable
+ 'AES_CTRL_Res': '$3', # Reserved Bit
+ 'AES_STATUS' : '$13d', # AES Status Register
+ 'AES_STATUS_AES_ER': '$80', # AES Operation Finished with Er
+ 'AES_STATUS_Res': '$7e', # Reserved
+ 'AES_STATUS_AES_DONE': '$1', # AES Operation Finished with Su
+ 'AES_STATE' : '$13e', # AES Plain and Cipher Text Buff
+ 'AES_STATE_AES_STATE': '$ff', # AES Plain and Cipher Text Buff
+ 'AES_KEY' : '$13f', # AES Encryption and Decryption
+ 'AES_KEY_AES_KEY': '$ff', # AES Encryption/Decryption Key
+ 'TRX_STATUS' : '$141', # Transceiver Status Register
+ 'TRX_STATUS_CCA_DONE': '$80', # CCA Algorithm Status
+ 'TRX_STATUS_CCA_STATUS': '$40', # CCA Status Result
+ 'TRX_STATUS_TST_STATUS': '$20', # Test mode status
+ 'TRX_STATUS_TRX_STATUS': '$1f', # Transceiver Main Status
+ 'TRX_STATE' : '$142', # Transceiver State Control Regi
+ 'TRX_STATE_TRAC_STATUS': '$e0', # Transaction Status
+ 'TRX_STATE_TRX_CMD': '$1f', # State Control Command
+ 'TRX_CTRL_0' : '$143', # Reserved
+ 'TRX_CTRL_0_Res7': '$80', # Reserved
+ 'TRX_CTRL_0_PMU_EN': '$40', # Enable Phase Measurement Unit
+ 'TRX_CTRL_0_PMU_START': '$20', # Start of Phase Measurement Uni
+ 'TRX_CTRL_0_PMU_IF_INV': '$10', # PMU IF Inverse
+ 'TRX_CTRL_0_Res': '$f', # Reserved
+ 'TRX_CTRL_1' : '$144', # Transceiver Control Register 1
+ 'TRX_CTRL_1_PA_EXT_EN': '$80', # External PA support enable
+ 'TRX_CTRL_1_IRQ_2_EXT_EN': '$40', # Connect Frame Start IRQ to TC1
+ 'TRX_CTRL_1_TX_AUTO_CRC_ON': '$20', # Enable Automatic CRC Calculati
+ 'TRX_CTRL_1_PLL_TX_FLT': '$10', # Enable PLL TX filter
+ 'TRX_CTRL_1_Res': '$f', # Reserved
+ 'PHY_TX_PWR' : '$145', # Transceiver Transmit Power Con
+ 'PHY_TX_PWR_Res': '$f0', # Reserved
+ 'PHY_TX_PWR_TX_PWR': '$f', # Transmit Power Setting
+ 'PHY_RSSI' : '$146', # Receiver Signal Strength Indic
+ 'PHY_RSSI_RX_CRC_VALID': '$80', # Received Frame CRC Status
+ 'PHY_RSSI_RND_VALUE': '$60', # Random Value
+ 'PHY_RSSI_RSSI': '$1f', # Receiver Signal Strength Indic
+ 'PHY_ED_LEVEL' : '$147', # Transceiver Energy Detection L
+ 'PHY_ED_LEVEL_ED_LEVEL': '$ff', # Energy Detection Level
+ 'PHY_CC_CCA' : '$148', # Transceiver Clear Channel Asse
+ 'PHY_CC_CCA_CCA_REQUEST': '$80', # Manual CCA Measurement Request
+ 'PHY_CC_CCA_CCA_MODE': '$60', # Select CCA Measurement Mode
+ 'PHY_CC_CCA_CHANNEL': '$1f', # RX/TX Channel Selection
+ 'CCA_THRES' : '$149', # Transceiver CCA Threshold Sett
+ 'CCA_THRES_CCA_CS_THRES': '$f0', # CS Threshold Level for CCA Mea
+ 'CCA_THRES_CCA_ED_THRES': '$f', # ED Threshold Level for CCA Mea
+ 'RX_CTRL' : '$14a', # Transceiver Receive Control Re
+ 'RX_CTRL_PDT_THRES': '$f', # Receiver Sensitivity Control
+ 'SFD_VALUE' : '$14b', # Start of Frame Delimiter Value
+ 'SFD_VALUE_SFD_VALUE': '$ff', # Start of Frame Delimiter Value
+ 'TRX_CTRL_2' : '$14c', # Transceiver Control Register 2
+ 'TRX_CTRL_2_RX_SAFE_MODE': '$80', # RX Safe Mode
+ 'TRX_CTRL_2_Res': '$7c', # Reserved
+ 'TRX_CTRL_2_OQPSK_DATA_RATE': '$3', # Data Rate Selection
+ 'ANT_DIV' : '$14d', # Antenna Diversity Control Regi
+ 'ANT_DIV_ANT_SEL': '$80', # Antenna Diversity Antenna Stat
+ 'ANT_DIV_Res': '$70', # Reserved
+ 'ANT_DIV_ANT_DIV_EN': '$8', # Enable Antenna Diversity
+ 'ANT_DIV_ANT_EXT_SW_EN': '$4', # Enable External Antenna Switch
+ 'ANT_DIV_ANT_CTRL': '$3', # Static Antenna Diversity Switc
+ 'IRQ_MASK' : '$14e', # Transceiver Interrupt Enable R
+ 'IRQ_MASK_AWAKE_EN': '$80', # Awake Interrupt Enable
+ 'IRQ_MASK_TX_END_EN': '$40', # TX_END Interrupt Enable
+ 'IRQ_MASK_AMI_EN': '$20', # Address Match Interrupt Enable
+ 'IRQ_MASK_CCA_ED_DONE_EN': '$10', # End of ED Measurement Interrup
+ 'IRQ_MASK_RX_END_EN': '$8', # RX_END Interrupt Enable
+ 'IRQ_MASK_RX_START_EN': '$4', # RX_START Interrupt Enable
+ 'IRQ_MASK_PLL_UNLOCK_EN': '$2', # PLL Unlock Interrupt Enable
+ 'IRQ_MASK_PLL_LOCK_EN': '$1', # PLL Lock Interrupt Enable
+ 'IRQ_STATUS' : '$14f', # Transceiver Interrupt Status R
+ 'IRQ_STATUS_AWAKE': '$80', # Awake Interrupt Status
+ 'IRQ_STATUS_TX_END': '$40', # TX_END Interrupt Status
+ 'IRQ_STATUS_AMI': '$20', # Address Match Interrupt Status
+ 'IRQ_STATUS_CCA_ED_DONE': '$10', # End of ED Measurement Interrup
+ 'IRQ_STATUS_RX_END': '$8', # RX_END Interrupt Status
+ 'IRQ_STATUS_RX_START': '$4', # RX_START Interrupt Status
+ 'IRQ_STATUS_PLL_UNLOCK': '$2', # PLL Unlock Interrupt Status
+ 'IRQ_STATUS_PLL_LOCK': '$1', # PLL Lock Interrupt Status
+ 'IRQ_MASK1' : '$be', # Transceiver Interrupt Enable R
+ 'IRQ_MASK1_Res': '$e0', # Reserved Bit
+ 'IRQ_MASK1_MAF_3_AMI_EN': '$10', # Address Match Interrupt enable
+ 'IRQ_MASK1_MAF_2_AMI_EN': '$8', # Address Match Interrupt enable
+ 'IRQ_MASK1_MAF_1_AMI_EN': '$4', # Address Match Interrupt enable
+ 'IRQ_MASK1_MAF_0_AMI_EN': '$2', # Address Match Interrupt enable
+ 'IRQ_MASK1_TX_START_EN': '$1', # Transmit Start Interrupt enabl
+ 'IRQ_STATUS1' : '$bf', # Transceiver Interrupt Status R
+ 'IRQ_STATUS1_Res': '$e0', # Reserved Bit
+ 'IRQ_STATUS1_MAF_3_AMI': '$10', # Address Match Interrupt Status
+ 'IRQ_STATUS1_MAF_2_AMI': '$8', # Address Match Interrupt Status
+ 'IRQ_STATUS1_MAF_1_AMI': '$4', # Address Match Interrupt Status
+ 'IRQ_STATUS1_MAF_0_AMI': '$2', # Address Match Interrupt Status
+ 'IRQ_STATUS1_TX_START': '$1', # Transmit Start Interrupt Statu
+ 'VREG_CTRL' : '$150', # Voltage Regulator Control and
+ 'VREG_CTRL_AVREG_EXT': '$80', # Use External AVDD Regulator
+ 'VREG_CTRL_AVDD_OK': '$40', # AVDD Supply Voltage Valid
+ 'VREG_CTRL_DVREG_EXT': '$8', # Use External DVDD Regulator
+ 'VREG_CTRL_DVDD_OK': '$4', # DVDD Supply Voltage Valid
+ 'BATMON' : '$151', # Battery Monitor Control and St
+ 'BATMON_BAT_LOW': '$80', # Battery Monitor Interrupt Stat
+ 'BATMON_BAT_LOW_EN': '$40', # Battery Monitor Interrupt Enab
+ 'BATMON_BATMON_OK': '$20', # Battery Monitor Status
+ 'BATMON_BATMON_HR': '$10', # Battery Monitor Voltage Range
+ 'BATMON_BATMON_VTH': '$f', # Battery Monitor Threshold Volt
+ 'XOSC_CTRL' : '$152', # Crystal Oscillator Control Reg
+ 'XOSC_CTRL_XTAL_MODE': '$f0', # Crystal Oscillator Operating M
+ 'XOSC_CTRL_XTAL_TRIM': '$f', # Crystal Oscillator Load Capaci
+ 'CC_CTRL_0' : '$153', # Channel Control Register 0
+ 'CC_CTRL_0_CC_NUMBER': '$ff', # Channel Number
+ 'CC_CTRL_1' : '$154', # Channel Control Register 1
+ 'CC_CTRL_1_CC_BAND': '$f', # Channel Band
+ 'RX_SYN' : '$155', # Transceiver Receiver Sensitivi
+ 'RX_SYN_RX_PDT_DIS': '$80', # Prevent Frame Reception
+ 'RX_SYN_RX_OVERRIDE': '$40', # Receiver Override Function
+ 'RX_SYN_Res': '$30', # Reserved
+ 'RX_SYN_RX_PDT_LEVEL': '$f', # Reduce Receiver Sensitivity
+ 'TRX_RPC' : '$156', # Transceiver Reduced Power Cons
+ 'TRX_RPC_RX_RPC_CTRL': '$c0', # Smart Receiving Mode Timing
+ 'TRX_RPC_RX_RPC_EN': '$20', # Reciver Smart Receiving Mode E
+ 'TRX_RPC_PDT_RPC_EN': '$10', # Smart Receiving Mode Reduced S
+ 'TRX_RPC_PLL_RPC_EN': '$8', # PLL Smart Receiving Mode Enabl
+ 'TRX_RPC_Res0': '$4', # Reserved
+ 'TRX_RPC_IPAN_RPC_EN': '$2', # Smart Receiving Mode IPAN Hand
+ 'TRX_RPC_XAH_RPC_EN': '$1', # Smart Receiving in Extended Op
+ 'XAH_CTRL_1' : '$157', # Transceiver Acknowledgment Fra
+ 'XAH_CTRL_1_Res': '$c0', # Reserved Bit
+ 'XAH_CTRL_1_AACK_FLTR_RES_FT': '$20', # Filter Reserved Frames
+ 'XAH_CTRL_1_AACK_UPLD_RES_FT': '$10', # Process Reserved Frames
+ 'XAH_CTRL_1_Res': '$8', # Reserved Bit
+ 'XAH_CTRL_1_AACK_ACK_TIME': '$4', # Reduce Acknowledgment Time
+ 'XAH_CTRL_1_AACK_PROM_MODE': '$2', # Enable Promiscuous Mode
+ 'XAH_CTRL_1_Res': '$1', # Reserved Bit
+ 'FTN_CTRL' : '$158', # Transceiver Filter Tuning Cont
+ 'FTN_CTRL_FTN_START': '$80', # Start Calibration Loop of Filt
+ 'PLL_CF' : '$15a', # Transceiver Center Frequency C
+ 'PLL_CF_PLL_CF_START': '$80', # Start Center Frequency Calibra
+ 'PLL_DCU' : '$15b', # Transceiver Delay Cell Calibra
+ 'PLL_DCU_PLL_DCU_START': '$80', # Start Delay Cell Calibration
+ 'PART_NUM' : '$15c', # Device Identification Register
+ 'PART_NUM_PART_NUM': '$ff', # Part Number
+ 'VERSION_NUM' : '$15d', # Device Identification Register
+ 'VERSION_NUM_VERSION_NUM': '$ff', # Version Number
+ 'MAN_ID_0' : '$15e', # Device Identification Register
+ 'MAN_ID_0_MAN_ID_07': '$80', # Manufacturer ID (Low Byte)
+ 'MAN_ID_0_MAN_ID_06': '$40', # Manufacturer ID (Low Byte)
+ 'MAN_ID_0_MAN_ID_05': '$20', # Manufacturer ID (Low Byte)
+ 'MAN_ID_0_MAN_ID_04': '$10', # Manufacturer ID (Low Byte)
+ 'MAN_ID_0_MAN_ID_03': '$8', # Manufacturer ID (Low Byte)
+ 'MAN_ID_0_MAN_ID_02': '$4', # Manufacturer ID (Low Byte)
+ 'MAN_ID_0_MAN_ID_01': '$2', # Manufacturer ID (Low Byte)
+ 'MAN_ID_0_MAN_ID_00': '$1', # Manufacturer ID (Low Byte)
+ 'MAN_ID_1' : '$15f', # Device Identification Register
+ 'MAN_ID_1_MAN_ID_': '$ff', # Manufacturer ID (High Byte)
+ 'SHORT_ADDR_0' : '$160', # Transceiver MAC Short Address
+ 'SHORT_ADDR_0_SHORT_ADDR_07': '$80', # MAC Short Address
+ 'SHORT_ADDR_0_SHORT_ADDR_06': '$40', # MAC Short Address
+ 'SHORT_ADDR_0_SHORT_ADDR_05': '$20', # MAC Short Address
+ 'SHORT_ADDR_0_SHORT_ADDR_04': '$10', # MAC Short Address
+ 'SHORT_ADDR_0_SHORT_ADDR_03': '$8', # MAC Short Address
+ 'SHORT_ADDR_0_SHORT_ADDR_02': '$4', # MAC Short Address
+ 'SHORT_ADDR_0_SHORT_ADDR_01': '$2', # MAC Short Address
+ 'SHORT_ADDR_0_SHORT_ADDR_00': '$1', # MAC Short Address
+ 'SHORT_ADDR_1' : '$161', # Transceiver MAC Short Address
+ 'SHORT_ADDR_1_SHORT_ADDR_': '$ff', # MAC Short Address
+ 'PAN_ID_0' : '$162', # Transceiver Personal Area Netw
+ 'PAN_ID_0_PAN_ID_07': '$80', # MAC Personal Area Network ID
+ 'PAN_ID_0_PAN_ID_06': '$40', # MAC Personal Area Network ID
+ 'PAN_ID_0_PAN_ID_05': '$20', # MAC Personal Area Network ID
+ 'PAN_ID_0_PAN_ID_04': '$10', # MAC Personal Area Network ID
+ 'PAN_ID_0_PAN_ID_03': '$8', # MAC Personal Area Network ID
+ 'PAN_ID_0_PAN_ID_02': '$4', # MAC Personal Area Network ID
+ 'PAN_ID_0_PAN_ID_01': '$2', # MAC Personal Area Network ID
+ 'PAN_ID_0_PAN_ID_00': '$1', # MAC Personal Area Network ID
+ 'PAN_ID_1' : '$163', # Transceiver Personal Area Netw
+ 'PAN_ID_1_PAN_ID_': '$ff', # MAC Personal Area Network ID
+ 'IEEE_ADDR_0' : '$164', # Transceiver MAC IEEE Address R
+ 'IEEE_ADDR_0_IEEE_ADDR_07': '$80', # MAC IEEE Address
+ 'IEEE_ADDR_0_IEEE_ADDR_06': '$40', # MAC IEEE Address
+ 'IEEE_ADDR_0_IEEE_ADDR_05': '$20', # MAC IEEE Address
+ 'IEEE_ADDR_0_IEEE_ADDR_04': '$10', # MAC IEEE Address
+ 'IEEE_ADDR_0_IEEE_ADDR_03': '$8', # MAC IEEE Address
+ 'IEEE_ADDR_0_IEEE_ADDR_02': '$4', # MAC IEEE Address
+ 'IEEE_ADDR_0_IEEE_ADDR_01': '$2', # MAC IEEE Address
+ 'IEEE_ADDR_0_IEEE_ADDR_00': '$1', # MAC IEEE Address
+ 'IEEE_ADDR_1' : '$165', # Transceiver MAC IEEE Address R
+ 'IEEE_ADDR_1_IEEE_ADDR_': '$ff', # MAC IEEE Address
+ 'IEEE_ADDR_2' : '$166', # Transceiver MAC IEEE Address R
+ 'IEEE_ADDR_2_IEEE_ADDR_': '$ff', # MAC IEEE Address
+ 'IEEE_ADDR_3' : '$167', # Transceiver MAC IEEE Address R
+ 'IEEE_ADDR_3_IEEE_ADDR_': '$ff', # MAC IEEE Address
+ 'IEEE_ADDR_4' : '$168', # Transceiver MAC IEEE Address R
+ 'IEEE_ADDR_4_IEEE_ADDR_': '$ff', # MAC IEEE Address
+ 'IEEE_ADDR_5' : '$169', # Transceiver MAC IEEE Address R
+ 'IEEE_ADDR_5_IEEE_ADDR_': '$ff', # MAC IEEE Address
+ 'IEEE_ADDR_6' : '$16a', # Transceiver MAC IEEE Address R
+ 'IEEE_ADDR_6_IEEE_ADDR_': '$ff', # MAC IEEE Address
+ 'IEEE_ADDR_7' : '$16b', # Transceiver MAC IEEE Address R
+ 'IEEE_ADDR_7_IEEE_ADDR_': '$ff', # MAC IEEE Address
+ 'XAH_CTRL_0' : '$16c', # Transceiver Extended Operating
+ 'XAH_CTRL_0_MAX_FRAME_RETRIES': '$f0', # Maximum Number of Frame Re-tra
+ 'XAH_CTRL_0_MAX_CSMA_RETRIES': '$e', # Maximum Number of CSMA-CA Proc
+ 'XAH_CTRL_0_SLOTTED_OPERATION': '$1', # Set Slotted Acknowledgment
+ 'CSMA_SEED_0' : '$16d', # Transceiver CSMA-CA Random Num
+ 'CSMA_SEED_0_CSMA_SEED_07': '$80', # Seed Value for CSMA Random Num
+ 'CSMA_SEED_0_CSMA_SEED_06': '$40', # Seed Value for CSMA Random Num
+ 'CSMA_SEED_0_CSMA_SEED_05': '$20', # Seed Value for CSMA Random Num
+ 'CSMA_SEED_0_CSMA_SEED_04': '$10', # Seed Value for CSMA Random Num
+ 'CSMA_SEED_0_CSMA_SEED_03': '$8', # Seed Value for CSMA Random Num
+ 'CSMA_SEED_0_CSMA_SEED_02': '$4', # Seed Value for CSMA Random Num
+ 'CSMA_SEED_0_CSMA_SEED_01': '$2', # Seed Value for CSMA Random Num
+ 'CSMA_SEED_0_CSMA_SEED_00': '$1', # Seed Value for CSMA Random Num
+ 'CSMA_SEED_1' : '$16e', # Transceiver Acknowledgment Fra
+ 'CSMA_SEED_1_AACK_FVN_MODE': '$c0', # Acknowledgment Frame Filter Mo
+ 'CSMA_SEED_1_AACK_SET_PD': '$20', # Set Frame Pending Sub-field
+ 'CSMA_SEED_1_AACK_DIS_ACK': '$10', # Disable Acknowledgment Frame T
+ 'CSMA_SEED_1_AACK_I_AM_COORD': '$8', # Set Personal Area Network Coor
+ 'CSMA_SEED_1_CSMA_SEED_1': '$7', # Seed Value for CSMA Random Num
+ 'CSMA_BE' : '$16f', # Transceiver CSMA-CA Back-off E
+ 'CSMA_BE_MAX_BE': '$f0', # Maximum Back-off Exponent
+ 'CSMA_BE_MIN_BE': '$f', # Minimum Back-off Exponent
+ 'TST_CTRL_DIGI' : '$176', # Transceiver Digital Test Contr
+ 'TST_CTRL_DIGI_TST_CTRL_DIG': '$f', # Digital Test Controller Regist
+ 'TST_RX_LENGTH' : '$17b', # Transceiver Received Frame Len
+ 'TST_RX_LENGTH_RX_LENGTH': '$ff', # Received Frame Length
+ 'TRXFBST' : '$180', # Start of frame buffer
+ 'TRXFBEND' : '$1ff', # End of frame buffer
+
+# Module SYMCNT
+ 'SCTSTRHH' : '$fc', # Symbol Counter Transmit Frame
+ 'SCTSTRHH_SCTSTRHH': '$ff', # Symbol Counter Transmit Frame
+ 'SCTSTRHL' : '$fb', # Symbol Counter Transmit Frame
+ 'SCTSTRHL_SCTSTRHL': '$ff', # Symbol Counter Transmit Frame
+ 'SCTSTRLH' : '$fa', # Symbol Counter Transmit Frame
+ 'SCTSTRLH_SCTSTRLH': '$ff', # Symbol Counter Transmit Frame
+ 'SCTSTRLL' : '$f9', # Symbol Counter Transmit Frame
+ 'SCTSTRLL_SCTSTRLL': '$ff', # Symbol Counter Transmit Frame
+ 'SCOCR1HH' : '$f8', # Symbol Counter Output Compare
+ 'SCOCR1HH_SCOCR1HH': '$ff', # Symbol Counter Output Compare
+ 'SCOCR1HL' : '$f7', # Symbol Counter Output Compare
+ 'SCOCR1HL_SCOCR1HL': '$ff', # Symbol Counter Output Compare
+ 'SCOCR1LH' : '$f6', # Symbol Counter Output Compare
+ 'SCOCR1LH_SCOCR1LH': '$ff', # Symbol Counter Output Compare
+ 'SCOCR1LL' : '$f5', # Symbol Counter Output Compare
+ 'SCOCR1LL_SCOCR1LL': '$ff', # Symbol Counter Output Compare
+ 'SCOCR2HH' : '$f4', # Symbol Counter Output Compare
+ 'SCOCR2HH_SCOCR2HH': '$ff', # Symbol Counter Output Compare
+ 'SCOCR2HL' : '$f3', # Symbol Counter Output Compare
+ 'SCOCR2HL_SCOCR2HL': '$ff', # Symbol Counter Output Compare
+ 'SCOCR2LH' : '$f2', # Symbol Counter Output Compare
+ 'SCOCR2LH_SCOCR2LH': '$ff', # Symbol Counter Output Compare
+ 'SCOCR2LL' : '$f1', # Symbol Counter Output Compare
+ 'SCOCR2LL_SCOCR2LL': '$ff', # Symbol Counter Output Compare
+ 'SCOCR3HH' : '$f0', # Symbol Counter Output Compare
+ 'SCOCR3HH_SCOCR3HH': '$ff', # Symbol Counter Output Compare
+ 'SCOCR3HL' : '$ef', # Symbol Counter Output Compare
+ 'SCOCR3HL_SCOCR3HL': '$ff', # Symbol Counter Output Compare
+ 'SCOCR3LH' : '$ee', # Symbol Counter Output Compare
+ 'SCOCR3LH_SCOCR3LH': '$ff', # Symbol Counter Output Compare
+ 'SCOCR3LL' : '$ed', # Symbol Counter Output Compare
+ 'SCOCR3LL_SCOCR3LL': '$ff', # Symbol Counter Output Compare
+ 'SCTSRHH' : '$ec', # Symbol Counter Frame Timestamp
+ 'SCTSRHH_SCTSRHH': '$ff', # Symbol Counter Frame Timestamp
+ 'SCTSRHL' : '$eb', # Symbol Counter Frame Timestamp
+ 'SCTSRHL_SCTSRHL': '$ff', # Symbol Counter Frame Timestamp
+ 'SCTSRLH' : '$ea', # Symbol Counter Frame Timestamp
+ 'SCTSRLH_SCTSRLH': '$ff', # Symbol Counter Frame Timestamp
+ 'SCTSRLL' : '$e9', # Symbol Counter Frame Timestamp
+ 'SCTSRLL_SCTSRLL': '$ff', # Symbol Counter Frame Timestamp
+ 'SCBTSRHH' : '$e8', # Symbol Counter Beacon Timestam
+ 'SCBTSRHH_SCBTSRHH': '$ff', # Symbol Counter Beacon Timestam
+ 'SCBTSRHL' : '$e7', # Symbol Counter Beacon Timestam
+ 'SCBTSRHL_SCBTSRHL': '$ff', # Symbol Counter Beacon Timestam
+ 'SCBTSRLH' : '$e6', # Symbol Counter Beacon Timestam
+ 'SCBTSRLH_SCBTSRLH': '$ff', # Symbol Counter Beacon Timestam
+ 'SCBTSRLL' : '$e5', # Symbol Counter Beacon Timestam
+ 'SCBTSRLL_SCBTSRLL': '$ff', # Symbol Counter Beacon Timestam
+ 'SCCNTHH' : '$e4', # Symbol Counter Register HH-Byt
+ 'SCCNTHH_SCCNTHH': '$ff', # Symbol Counter Register HH-Byt
+ 'SCCNTHL' : '$e3', # Symbol Counter Register HL-Byt
+ 'SCCNTHL_SCCNTHL': '$ff', # Symbol Counter Register HL-Byt
+ 'SCCNTLH' : '$e2', # Symbol Counter Register LH-Byt
+ 'SCCNTLH_SCCNTLH': '$ff', # Symbol Counter Register LH-Byt
+ 'SCCNTLL' : '$e1', # Symbol Counter Register LL-Byt
+ 'SCCNTLL_SCCNTLL': '$ff', # Symbol Counter Register LL-Byt
+ 'SCIRQS' : '$e0', # Symbol Counter Interrupt Statu
+ 'SCIRQS_Res': '$e0', # Reserved Bit
+ 'SCIRQS_IRQSBO': '$10', # Backoff Slot Counter IRQ
+ 'SCIRQS_IRQSOF': '$8', # Symbol Counter Overflow IRQ
+ 'SCIRQS_IRQSCP': '$7', # Compare Unit 3 Compare Match I
+ 'SCIRQM' : '$df', # Symbol Counter Interrupt Mask
+ 'SCIRQM_Res': '$e0', # Reserved Bit
+ 'SCIRQM_IRQMBO': '$10', # Backoff Slot Counter IRQ enabl
+ 'SCIRQM_IRQMOF': '$8', # Symbol Counter Overflow IRQ en
+ 'SCIRQM_IRQMCP': '$7', # Symbol Counter Compare Match 3
+ 'SCSR' : '$de', # Symbol Counter Status Register
+ 'SCSR_Res': '$fe', # Reserved Bit
+ 'SCSR_SCBSY': '$1', # Symbol Counter busy
+ 'SCCR1' : '$dd', # Symbol Counter Control Registe
+ 'SCCR1_Res': '$c0', # Reserved Bit
+ 'SCCR1_SCBTSM': '$20', # Symbol Counter Beacon Timestam
+ 'SCCR1_SCCKDIV': '$1c', # Clock divider for synchronous
+ 'SCCR1_SCEECLK': '$2', # Enable External Clock Source o
+ 'SCCR1_SCENBO': '$1', # Backoff Slot Counter enable
+ 'SCCR0' : '$dc', # Symbol Counter Control Registe
+ 'SCCR0_SCRES': '$80', # Symbol Counter Synchronization
+ 'SCCR0_SCMBTS': '$40', # Manual Beacon Timestamp
+ 'SCCR0_SCEN': '$20', # Symbol Counter enable
+ 'SCCR0_SCCKSEL': '$10', # Symbol Counter Clock Source se
+ 'SCCR0_SCTSE': '$8', # Symbol Counter Automatic Times
+ 'SCCR0_SCCMP': '$7', # Symbol Counter Compare Unit 3
+ 'SCCSR' : '$db', # Symbol Counter Compare Source
+ 'SCCSR_Res': '$c0', # Reserved Bit
+ 'SCCSR_SCCS3': '$30', # Symbol Counter Compare Source
+ 'SCCSR_SCCS2': '$c', # Symbol Counter Compare Source
+ 'SCCSR_SCCS1': '$3', # Symbol Counter Compare Source
+ 'SCRSTRHH' : '$da', # Symbol Counter Received Frame
+ 'SCRSTRHH_SCRSTRHH': '$ff', # Symbol Counter Received Frame
+ 'SCRSTRHL' : '$d9', # Symbol Counter Received Frame
+ 'SCRSTRHL_SCRSTRHL': '$ff', # Symbol Counter Received Frame
+ 'SCRSTRLH' : '$d8', # Symbol Counter Received Frame
+ 'SCRSTRLH_SCRSTRLH': '$ff', # Symbol Counter Received Frame
+ 'SCRSTRLL' : '$d7', # Symbol Counter Received Frame
+ 'SCRSTRLL_SCRSTRLL': '$ff', # Symbol Counter Received Frame
+
+# Module EEPROM
+ 'EEAR' : '$41', # EEPROM Address Register Bytes
+ 'EEDR' : '$40', # EEPROM Data Register
+ 'EECR' : '$3f', # EEPROM Control Register
+ 'EECR_Res': '$c0', # Reserved
+ 'EECR_EEPM': '$30', # EEPROM Programming Mode
+ 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
+ 'EECR_EEMPE': '$4', # EEPROM Master Write Enable
+ 'EECR_EEPE': '$2', # EEPROM Programming Enable
+ 'EECR_EERE': '$1', # EEPROM Read Enable
+
+# Module JTAG
+ 'OCDR' : '$51', # On-Chip Debug Register
+ 'OCDR_OCDR': '$ff', # On-Chip Debug Register Data
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_JTD': '$80', # JTAG Interface Disable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+
+# Module EXTERNAL_INTERRUPT
+ 'EICRA' : '$69', # External Interrupt Control Reg
+ 'EICRA_ISC3': '$c0', # External Interrupt 3 Sense Con
+ 'EICRA_ISC2': '$30', # External Interrupt 2 Sense Con
+ 'EICRA_ISC1': '$c', # External Interrupt 1 Sense Con
+ 'EICRA_ISC0': '$3', # External Interrupt 0 Sense Con
+ 'EICRB' : '$6a', # External Interrupt Control Reg
+ 'EICRB_ISC7': '$c0', # External Interrupt 7 Sense Con
+ 'EICRB_ISC6': '$30', # External Interrupt 6 Sense Con
+ 'EICRB_ISC5': '$c', # External Interrupt 5 Sense Con
+ 'EICRB_ISC4': '$3', # External Interrupt 4 Sense Con
+ 'EIMSK' : '$3d', # External Interrupt Mask Regist
+ 'EIMSK_INT': '$ff', # External Interrupt Request Ena
+ 'EIFR' : '$3c', # External Interrupt Flag Regist
+ 'EIFR_INTF': '$ff', # External Interrupt Flag
+ 'PCMSK2' : '$6d', # Pin Change Mask Register 2
+ 'PCMSK2_PCINT': '$ff', # Pin Change Enable Mask
+ 'PCMSK1' : '$6c', # Pin Change Mask Register 1
+ 'PCMSK1_PCINT': '$ff', # Pin Change Enable Mask
+ 'PCMSK0' : '$6b', # Pin Change Mask Register 0
+ 'PCIFR' : '$3b', # Pin Change Interrupt Flag Regi
+ 'PCIFR_Res': '$f8', # Reserved Bit
+ 'PCIFR_PCIF': '$7', # Pin Change Interrupt Flags
+ 'PCICR' : '$68', # Pin Change Interrupt Control R
+ 'PCICR_Res': '$f8', # Reserved Bit
+ 'PCICR_PCIE': '$7', # Pin Change Interrupt Enables
+
+# Module AD_CONVERTER
+ 'ADMUX' : '$7c', # The ADC Multiplexer Selection
+ 'ADMUX_REFS': '$c0', # Reference Selection Bits
+ 'ADMUX_ADLAR': '$20', # ADC Left Adjust Result
+ 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
+ 'ADC' : '$78', # ADC Data Register Bytes
+ 'ADCSRA' : '$7a', # The ADC Control and Status Reg
+ 'ADCSRA_ADEN': '$80', # ADC Enable
+ 'ADCSRA_ADSC': '$40', # ADC Start Conversion
+ 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
+ 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
+ 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
+ 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
+ 'ADCSRB' : '$7b', # The ADC Control and Status Reg
+ 'ADCSRB_AVDDOK': '$80', # AVDD Supply Voltage OK
+ 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
+ 'ADCSRB_REFOK': '$20', # Reference Voltage OK
+ 'ADCSRB_ACCH': '$10', # Analog Channel Change
+ 'ADCSRB_MUX5': '$8', # Analog Channel and Gain Select
+ 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Source
+ 'ADCSRC' : '$77', # The ADC Control and Status Reg
+ 'ADCSRC_ADTHT': '$c0', # ADC Track-and-Hold Time
+ 'ADCSRC_Res0': '$20', # Reserved
+ 'ADCSRC_ADSUT': '$1f', # ADC Start-up Time
+ 'DIDR2' : '$7d', # Digital Input Disable Register
+ 'DIDR2_ADC15D': '$80', # Reserved Bits
+ 'DIDR2_ADC14D': '$40', # Reserved Bits
+ 'DIDR2_ADC13D': '$20', # Reserved Bits
+ 'DIDR2_ADC12D': '$10', # Reserved Bits
+ 'DIDR2_ADC11D': '$8', # Reserved Bits
+ 'DIDR2_ADC10D': '$4', # Reserved Bits
+ 'DIDR2_ADC9D': '$2', # Reserved Bits
+ 'DIDR2_ADC8D': '$1', # Reserved Bits
+ 'DIDR0' : '$7e', # Digital Input Disable Register
+ 'DIDR0_ADC7D': '$80', # Disable ADC7:0 Digital Input
+ 'DIDR0_ADC6D': '$40', # Disable ADC7:0 Digital Input
+ 'DIDR0_ADC5D': '$20', # Disable ADC7:0 Digital Input
+ 'DIDR0_ADC4D': '$10', # Disable ADC7:0 Digital Input
+ 'DIDR0_ADC3D': '$8', # Disable ADC7:0 Digital Input
+ 'DIDR0_ADC2D': '$4', # Disable ADC7:0 Digital Input
+ 'DIDR0_ADC1D': '$2', # Disable ADC7:0 Digital Input
+ 'DIDR0_ADC0D': '$1', # Disable ADC7:0 Digital Input
+
+# Module BOOT_LOAD
+ 'SPMCSR' : '$57', # Store Program Memory Control R
+ 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
+ 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
+ 'SPMCSR_SIGRD': '$20', # Signature Row Read
+ 'SPMCSR_RWWSRE': '$10', # Read While Write Section Read
+ 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
+ 'SPMCSR_PGWRT': '$4', # Page Write
+ 'SPMCSR_PGERS': '$2', # Page Erase
+ 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
+
+# Module CPU
+ 'SREG' : '$5f', # Status Register
+ 'SREG_I': '$80', # Global Interrupt Enable
+ 'SREG_T': '$40', # Bit Copy Storage
+ 'SREG_H': '$20', # Half Carry Flag
+ 'SREG_S': '$10', # Sign Bit
+ 'SREG_V': '$8', # Two's Complement Overflow Flag
+ 'SREG_N': '$4', # Negative Flag
+ 'SREG_Z': '$2', # Zero Flag
+ 'SREG_C': '$1', # Carry Flag
+ 'SP' : '$5d', # Stack Pointer
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_JTD': '$80', # JTAG Interface Disable
+ 'MCUCR_Res': '$60', # Reserved
+ 'MCUCR_PUD': '$10', # Pull-up Disable
+ 'MCUCR_Res': '$c', # Reserved
+ 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
+ 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_Res': '$e0', # Reserved
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+ 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
+ 'MCUSR_BORF': '$4', # Brown-out Reset Flag
+ 'MCUSR_EXTRF': '$2', # External Reset Flag
+ 'MCUSR_PORF': '$1', # Power-on Reset Flag
+ 'OSCCAL' : '$66', # Oscillator Calibration Value
+ 'OSCCAL_CAL': '$ff', # Oscillator Calibration Tuning
+ 'CLKPR' : '$61', # Clock Prescale Register
+ 'CLKPR_CLKPCE': '$80', # Clock Prescaler Change Enable
+ 'CLKPR_Res': '$70', # Reserved
+ 'CLKPR_CLKPS': '$f', # Clock Prescaler Select Bits
+ 'SMCR' : '$53', # Sleep Mode Control Register
+ 'SMCR_Res': '$f0', # Reserved
+ 'SMCR_SM': '$e', # Sleep Mode Select bits
+ 'SMCR_SE': '$1', # Sleep Enable
+ 'EIND' : '$5c', # Extended Indirect Register
+ 'RAMPZ' : '$5b', # Extended Z-pointer Register fo
+ 'RAMPZ_Res': '$fc', # Reserved
+ 'RAMPZ_RAMPZ': '$3', # Extended Z-Pointer Value
+ 'GPIOR2' : '$4b', # General Purpose I/O Register 2
+ 'GPIOR2_GPIOR': '$ff', # General Purpose I/O Register 2
+ 'GPIOR1' : '$4a', # General Purpose IO Register 1
+ 'GPIOR1_GPIOR': '$ff', # General Purpose I/O Register 1
+ 'GPIOR0' : '$3e', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR07': '$80', # General Purpose I/O Register 0
+ 'GPIOR0_GPIOR06': '$40', # General Purpose I/O Register 0
+ 'GPIOR0_GPIOR05': '$20', # General Purpose I/O Register 0
+ 'GPIOR0_GPIOR04': '$10', # General Purpose I/O Register 0
+ 'GPIOR0_GPIOR03': '$8', # General Purpose I/O Register 0
+ 'GPIOR0_GPIOR02': '$4', # General Purpose I/O Register 0
+ 'GPIOR0_GPIOR01': '$2', # General Purpose I/O Register 0
+ 'GPIOR0_GPIOR00': '$1', # General Purpose I/O Register 0
+ 'PRR2' : '$63', # Power Reduction Register 2
+ 'PRR2_Res': '$f0', # Reserved Bit
+ 'PRR2_PRRAM': '$f', # Power Reduction SRAMs
+ 'PRR1' : '$65', # Power Reduction Register 1
+ 'PRR1_Res': '$80', # Reserved Bit
+ 'PRR1_PRTRX24': '$40', # Power Reduction Transceiver
+ 'PRR1_PRTIM5': '$20', # Power Reduction Timer/Counter5
+ 'PRR1_PRTIM4': '$10', # Power Reduction Timer/Counter4
+ 'PRR1_PRTIM3': '$8', # Power Reduction Timer/Counter3
+ 'PRR1_PRUSART1': '$1', # Power Reduction USART1
+ 'PRR0' : '$64', # Power Reduction Register0
+ 'PRR0_PRTWI': '$80', # Power Reduction TWI
+ 'PRR0_PRTIM2': '$40', # Power Reduction Timer/Counter2
+ 'PRR0_PRTIM0': '$20', # Power Reduction Timer/Counter0
+ 'PRR0_PRPGA': '$10', # Power Reduction PGA
+ 'PRR0_PRTIM1': '$8', # Power Reduction Timer/Counter1
+ 'PRR0_PRSPI': '$4', # Power Reduction Serial Periphe
+ 'PRR0_PRUSART0': '$2', # Power Reduction USART
+ 'PRR0_PRADC': '$1', # Power Reduction ADC
+
+# Module FLASH
+ 'NEMCR' : '$75', # Flash Extended-Mode Control-Re
+ 'NEMCR_ENEAM': '$40', # Enable Extended Address Mode f
+ 'NEMCR_AEAM': '$30', # Address for Extended Address M
+ 'BGCR' : '$67', # Reference Voltage Calibration
+ 'BGCR_Res': '$80', # Reserved Bit
+ 'BGCR_BGCAL_FINE': '$78', # Fine Calibration Bits
+ 'BGCR_BGCAL': '$7', # Coarse Calibration Bits
+
+# Module PWRCTRL
+ 'TRXPR' : '$139', # Transceiver Pin Register
+ 'TRXPR_Res': '$f0', # Reserved
+ 'TRXPR_SLPTR': '$2', # Multi-purpose Transceiver Cont
+ 'TRXPR_TRXRST': '$1', # Force Transceiver Reset
+ 'DRTRAM0' : '$135', # Data Retention Configuration R
+ 'DRTRAM0_Res': '$c0', # Reserved
+ 'DRTRAM0_DRTSWOK': '$20', # DRT Switch OK
+ 'DRTRAM0_ENDRT': '$10', # Enable SRAM Data Retention
+ 'DRTRAM1' : '$134', # Data Retention Configuration R
+ 'DRTRAM1_Res': '$c0', # Reserved
+ 'DRTRAM1_DRTSWOK': '$20', # DRT Switch OK
+ 'DRTRAM1_ENDRT': '$10', # Enable SRAM Data Retention
+ 'DRTRAM2' : '$133', # Data Retention Configuration R
+ 'DRTRAM2_Res': '$40', # Reserved Bit
+ 'DRTRAM2_DRTSWOK': '$20', # DRT Switch OK
+ 'DRTRAM2_ENDRT': '$10', # Enable SRAM Data Retention
+ 'DRTRAM3' : '$132', # Data Retention Configuration R
+ 'DRTRAM3_Res': '$c0', # Reserved
+ 'DRTRAM3_DRTSWOK': '$20', # DRT Switch OK
+ 'DRTRAM3_ENDRT': '$10', # Enable SRAM Data Retention
+ 'LLDRL' : '$130', # Low Leakage Voltage Regulator
+ 'LLDRL_Res': '$f0', # Reserved
+ 'LLDRL_LLDRL': '$f', # Low-Byte Data Register Bits
+ 'LLDRH' : '$131', # Low Leakage Voltage Regulator
+ 'LLDRH_Res': '$e0', # Reserved
+ 'LLDRH_LLDRH': '$1f', # High-Byte Data Register Bits
+ 'LLCR' : '$12f', # Low Leakage Voltage Regulator
+ 'LLCR_Res': '$c0', # Reserved Bit
+ 'LLCR_LLDONE': '$20', # Calibration Done
+ 'LLCR_LLCOMP': '$10', # Comparator Output
+ 'LLCR_LLCAL': '$8', # Calibration Active
+ 'LLCR_LLTCO': '$4', # Temperature Coefficient of Cur
+ 'LLCR_LLSHORT': '$2', # Short Lower Calibration Circui
+ 'LLCR_LLENCAL': '$1', # Enable Automatic Calibration
+ 'DPDS0' : '$136', # Port Driver Strength Register
+ 'DPDS0_PFDRV': '$c0', # Driver Strength Port F
+ 'DPDS0_PEDRV': '$30', # Driver Strength Port E
+ 'DPDS0_PDDRV': '$c', # Driver Strength Port D
+ 'DPDS0_PBDRV': '$3', # Driver Strength Port B
+ 'DPDS1' : '$137', # Port Driver Strength Register
+ 'DPDS1_Res': '$fc', # Reserved
+ 'DPDS1_PGDRV': '$3', # Driver Strength Port G
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_PUD': '$10', # Pull-up Disable
+
+# Module USART0_SPI
+ 'UCSR0A' : '$c0', # USART0 MSPIM Control and Statu
+ 'UCSR0A_RXC0': '$80', # USART Receive Complete
+ 'UCSR0A_TXC0': '$40', # USART Transmit Complete
+ 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
+ 'UCSR0B' : '$c1', # USART0 MSPIM Control and Statu
+ 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
+ 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
+ 'UCSR0B_UDRIE0': '$20', # USART Data Register Empty Inte
+ 'UCSR0B_RXEN0': '$10', # Receiver Enable
+ 'UCSR0B_TXEN0': '$8', # Transmitter Enable
+ 'UCSR0C' : '$c2', # USART0 MSPIM Control and Statu
+ 'UCSR0C_UDORD0': '$4', # Data Order
+ 'UCSR0C_UCPHA0': '$2', # Clock Phase
+ 'UCSR0C_UCPOL0': '$1', # Clock Polarity
+
+# Module USART1_SPI
+ 'UCSR1A' : '$c8', # USART1 MSPIM Control and Statu
+ 'UCSR1A_RXC1': '$80', # USART Receive Complete
+ 'UCSR1A_TXC1': '$40', # USART Transmit Complete
+ 'UCSR1A_UDRE1': '$20', # USART Data Register Empty
+ 'UCSR1B' : '$c9', # USART1 MSPIM Control and Statu
+ 'UCSR1B_RXCIE1': '$80', # RX Complete Interrupt Enable
+ 'UCSR1B_TXCIE1': '$40', # TX Complete Interrupt Enable
+ 'UCSR1B_UDRIE1': '$20', # USART Data Register Empty Inte
+ 'UCSR1B_RXEN1': '$10', # Receiver Enable
+ 'UCSR1B_TXEN1': '$8', # Transmitter Enable
+ 'UCSR1C' : '$ca', # USART1 MSPIM Control and Statu
+ 'UCSR1C_UDORD1': '$4', # Data Order
+ 'UCSR1C_UCPHA1': '$2', # Clock Phase
+ 'UCSR1C_UCPOL1': '$1', # Clock Polarity
+
+ '__amforth_dummy':'0'
+}
diff --git a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/AD_CONVERTER.frt b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/AD_CONVERTER.frt
new file mode 100644
index 0000000..17d6c7e
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/AD_CONVERTER.frt
@@ -0,0 +1,79 @@
+\ Generated automatically for atmega256rfr2
+\ #require bitnames.frt
+
+\ AD_CONVERTER
+$7c constant ADMUX \ The ADC Multiplexer Selection
+ $c0 constant ADMUX_REFS \ Reference Selection Bits
+ 7c $c0 bitmask: ADMUX.REFS \ Reference Selection Bits
+ $20 constant ADMUX_ADLAR \ ADC Left Adjust Result
+ 7c $20 bitmask: ADMUX.ADLAR \ ADC Left Adjust Result
+ $1f constant ADMUX_MUX \ Analog Channel and Gain Select
+ 7c $1f bitmask: ADMUX.MUX \ Analog Channel and Gain Select
+$78 constant ADC \ ADC Data Register Bytes
+$7a constant ADCSRA \ The ADC Control and Status Reg
+ $80 constant ADCSRA_ADEN \ ADC Enable
+ 7a $80 bitmask: ADCSRA.ADEN \ ADC Enable
+ $40 constant ADCSRA_ADSC \ ADC Start Conversion
+ 7a $40 bitmask: ADCSRA.ADSC \ ADC Start Conversion
+ $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
+ 7a $20 bitmask: ADCSRA.ADATE \ ADC Auto Trigger Enable
+ $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
+ 7a $10 bitmask: ADCSRA.ADIF \ ADC Interrupt Flag
+ $8 constant ADCSRA_ADIE \ ADC Interrupt Enable
+ 7a $8 bitmask: ADCSRA.ADIE \ ADC Interrupt Enable
+ $7 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
+ 7a $7 bitmask: ADCSRA.ADPS \ ADC Prescaler Select Bits
+$7b constant ADCSRB \ The ADC Control and Status Reg
+ $80 constant ADCSRB_AVDDOK \ AVDD Supply Voltage OK
+ 7b $80 bitmask: ADCSRB.AVDDOK \ AVDD Supply Voltage OK
+ $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer
+ 7b $40 bitmask: ADCSRB.ACME \ Analog Comparator Multiplexer
+ $20 constant ADCSRB_REFOK \ Reference Voltage OK
+ 7b $20 bitmask: ADCSRB.REFOK \ Reference Voltage OK
+ $10 constant ADCSRB_ACCH \ Analog Channel Change
+ 7b $10 bitmask: ADCSRB.ACCH \ Analog Channel Change
+ $8 constant ADCSRB_MUX5 \ Analog Channel and Gain Select
+ 7b $8 bitmask: ADCSRB.MUX5 \ Analog Channel and Gain Select
+ $7 constant ADCSRB_ADTS \ ADC Auto Trigger Source
+ 7b $7 bitmask: ADCSRB.ADTS \ ADC Auto Trigger Source
+$77 constant ADCSRC \ The ADC Control and Status Reg
+ $c0 constant ADCSRC_ADTHT \ ADC Track-and-Hold Time
+ 77 $c0 bitmask: ADCSRC.ADTHT \ ADC Track-and-Hold Time
+ $20 constant ADCSRC_Res0 \ Reserved
+ 77 $20 bitmask: ADCSRC.Res0 \ Reserved
+ $1f constant ADCSRC_ADSUT \ ADC Start-up Time
+ 77 $1f bitmask: ADCSRC.ADSUT \ ADC Start-up Time
+$7d constant DIDR2 \ Digital Input Disable Register
+ $80 constant DIDR2_ADC15D \ Reserved Bits
+ 7d $80 bitmask: DIDR2.ADC15D \ Reserved Bits
+ $40 constant DIDR2_ADC14D \ Reserved Bits
+ 7d $40 bitmask: DIDR2.ADC14D \ Reserved Bits
+ $20 constant DIDR2_ADC13D \ Reserved Bits
+ 7d $20 bitmask: DIDR2.ADC13D \ Reserved Bits
+ $10 constant DIDR2_ADC12D \ Reserved Bits
+ 7d $10 bitmask: DIDR2.ADC12D \ Reserved Bits
+ $8 constant DIDR2_ADC11D \ Reserved Bits
+ 7d $8 bitmask: DIDR2.ADC11D \ Reserved Bits
+ $4 constant DIDR2_ADC10D \ Reserved Bits
+ 7d $4 bitmask: DIDR2.ADC10D \ Reserved Bits
+ $2 constant DIDR2_ADC9D \ Reserved Bits
+ 7d $2 bitmask: DIDR2.ADC9D \ Reserved Bits
+ $1 constant DIDR2_ADC8D \ Reserved Bits
+ 7d $1 bitmask: DIDR2.ADC8D \ Reserved Bits
+$7e constant DIDR0 \ Digital Input Disable Register
+ $80 constant DIDR0_ADC7D \ Disable ADC7:0 Digital Input
+ 7e $80 bitmask: DIDR0.ADC7D \ Disable ADC7:0 Digital Input
+ $40 constant DIDR0_ADC6D \ Disable ADC7:0 Digital Input
+ 7e $40 bitmask: DIDR0.ADC6D \ Disable ADC7:0 Digital Input
+ $20 constant DIDR0_ADC5D \ Disable ADC7:0 Digital Input
+ 7e $20 bitmask: DIDR0.ADC5D \ Disable ADC7:0 Digital Input
+ $10 constant DIDR0_ADC4D \ Disable ADC7:0 Digital Input
+ 7e $10 bitmask: DIDR0.ADC4D \ Disable ADC7:0 Digital Input
+ $8 constant DIDR0_ADC3D \ Disable ADC7:0 Digital Input
+ 7e $8 bitmask: DIDR0.ADC3D \ Disable ADC7:0 Digital Input
+ $4 constant DIDR0_ADC2D \ Disable ADC7:0 Digital Input
+ 7e $4 bitmask: DIDR0.ADC2D \ Disable ADC7:0 Digital Input
+ $2 constant DIDR0_ADC1D \ Disable ADC7:0 Digital Input
+ 7e $2 bitmask: DIDR0.ADC1D \ Disable ADC7:0 Digital Input
+ $1 constant DIDR0_ADC0D \ Disable ADC7:0 Digital Input
+ 7e $1 bitmask: DIDR0.ADC0D \ Disable ADC7:0 Digital Input
diff --git a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/ANALOG_COMPARATOR.frt b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/ANALOG_COMPARATOR.frt
new file mode 100644
index 0000000..cf9e656
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/ANALOG_COMPARATOR.frt
@@ -0,0 +1,27 @@
+\ Generated automatically for atmega256rfr2
+\ #require bitnames.frt
+
+\ ANALOG_COMPARATOR
+$7b constant ADCSRB \ ADC Control and Status Registe
+ $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer
+ 7b $40 bitmask: ADCSRB.ACME \ Analog Comparator Multiplexer
+$50 constant ACSR \ Analog Comparator Control And
+ $80 constant ACSR_ACD \ Analog Comparator Disable
+ 50 $80 bitmask: ACSR.ACD \ Analog Comparator Disable
+ $40 constant ACSR_ACBG \ Analog Comparator Bandgap Sele
+ 50 $40 bitmask: ACSR.ACBG \ Analog Comparator Bandgap Sele
+ $20 constant ACSR_ACO \ Analog Compare Output
+ 50 $20 bitmask: ACSR.ACO \ Analog Compare Output
+ $10 constant ACSR_ACI \ Analog Comparator Interrupt Fl
+ 50 $10 bitmask: ACSR.ACI \ Analog Comparator Interrupt Fl
+ $8 constant ACSR_ACIE \ Analog Comparator Interrupt En
+ 50 $8 bitmask: ACSR.ACIE \ Analog Comparator Interrupt En
+ $4 constant ACSR_ACIC \ Analog Comparator Input Captur
+ 50 $4 bitmask: ACSR.ACIC \ Analog Comparator Input Captur
+ $3 constant ACSR_ACIS \ Analog Comparator Interrupt Mo
+ 50 $3 bitmask: ACSR.ACIS \ Analog Comparator Interrupt Mo
+$7f constant DIDR1 \ Digital Input Disable Register
+ $2 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
+ 7f $2 bitmask: DIDR1.AIN1D \ AIN1 Digital Input Disable
+ $1 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
+ 7f $1 bitmask: DIDR1.AIN0D \ AIN0 Digital Input Disable
diff --git a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/BOOT_LOAD.frt b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/BOOT_LOAD.frt
new file mode 100644
index 0000000..d38b796
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/BOOT_LOAD.frt
@@ -0,0 +1,21 @@
+\ Generated automatically for atmega256rfr2
+\ #require bitnames.frt
+
+\ BOOT_LOAD
+$57 constant SPMCSR \ Store Program Memory Control R
+ $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
+ 57 $80 bitmask: SPMCSR.SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
+ 57 $40 bitmask: SPMCSR.RWWSB \ Read While Write Section Busy
+ $20 constant SPMCSR_SIGRD \ Signature Row Read
+ 57 $20 bitmask: SPMCSR.SIGRD \ Signature Row Read
+ $10 constant SPMCSR_RWWSRE \ Read While Write Section Read
+ 57 $10 bitmask: SPMCSR.RWWSRE \ Read While Write Section Read
+ $8 constant SPMCSR_BLBSET \ Boot Lock Bit Set
+ 57 $8 bitmask: SPMCSR.BLBSET \ Boot Lock Bit Set
+ $4 constant SPMCSR_PGWRT \ Page Write
+ 57 $4 bitmask: SPMCSR.PGWRT \ Page Write
+ $2 constant SPMCSR_PGERS \ Page Erase
+ 57 $2 bitmask: SPMCSR.PGERS \ Page Erase
+ $1 constant SPMCSR_SPMEN \ Store Program Memory Enable
+ 57 $1 bitmask: SPMCSR.SPMEN \ Store Program Memory Enable
diff --git a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/CPU.frt b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/CPU.frt
new file mode 100644
index 0000000..f15f877
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/CPU.frt
@@ -0,0 +1,129 @@
+\ Generated automatically for atmega256rfr2
+\ #require bitnames.frt
+
+\ CPU
+$5f constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ 5f $80 bitmask: SREG.I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ 5f $40 bitmask: SREG.T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ 5f $20 bitmask: SREG.H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ 5f $10 bitmask: SREG.S \ Sign Bit
+ $8 constant SREG_V \ Two's Complement Overflow Flag
+ 5f $8 bitmask: SREG.V \ Two's Complement Overflow Flag
+ $4 constant SREG_N \ Negative Flag
+ 5f $4 bitmask: SREG.N \ Negative Flag
+ $2 constant SREG_Z \ Zero Flag
+ 5f $2 bitmask: SREG.Z \ Zero Flag
+ $1 constant SREG_C \ Carry Flag
+ 5f $1 bitmask: SREG.C \ Carry Flag
+$5d constant SP \ Stack Pointer
+$55 constant MCUCR \ MCU Control Register
+ $80 constant MCUCR_JTD \ JTAG Interface Disable
+ 55 $80 bitmask: MCUCR.JTD \ JTAG Interface Disable
+ $60 constant MCUCR_Res \ Reserved
+ 55 $60 bitmask: MCUCR.Res \ Reserved
+ $10 constant MCUCR_PUD \ Pull-up Disable
+ 55 $10 bitmask: MCUCR.PUD \ Pull-up Disable
+ $c constant MCUCR_Res \ Reserved
+ 55 $c bitmask: MCUCR.Res \ Reserved
+ $2 constant MCUCR_IVSEL \ Interrupt Vector Select
+ 55 $2 bitmask: MCUCR.IVSEL \ Interrupt Vector Select
+ $1 constant MCUCR_IVCE \ Interrupt Vector Change Enable
+ 55 $1 bitmask: MCUCR.IVCE \ Interrupt Vector Change Enable
+$54 constant MCUSR \ MCU Status Register
+ $e0 constant MCUSR_Res \ Reserved
+ 54 $e0 bitmask: MCUSR.Res \ Reserved
+ $10 constant MCUSR_JTRF \ JTAG Reset Flag
+ 54 $10 bitmask: MCUSR.JTRF \ JTAG Reset Flag
+ $8 constant MCUSR_WDRF \ Watchdog Reset Flag
+ 54 $8 bitmask: MCUSR.WDRF \ Watchdog Reset Flag
+ $4 constant MCUSR_BORF \ Brown-out Reset Flag
+ 54 $4 bitmask: MCUSR.BORF \ Brown-out Reset Flag
+ $2 constant MCUSR_EXTRF \ External Reset Flag
+ 54 $2 bitmask: MCUSR.EXTRF \ External Reset Flag
+ $1 constant MCUSR_PORF \ Power-on Reset Flag
+ 54 $1 bitmask: MCUSR.PORF \ Power-on Reset Flag
+$66 constant OSCCAL \ Oscillator Calibration Value
+ $ff constant OSCCAL_CAL \ Oscillator Calibration Tuning
+ 66 $ff bitmask: OSCCAL.CAL \ Oscillator Calibration Tuning
+$61 constant CLKPR \ Clock Prescale Register
+ $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable
+ 61 $80 bitmask: CLKPR.CLKPCE \ Clock Prescaler Change Enable
+ $70 constant CLKPR_Res \ Reserved
+ 61 $70 bitmask: CLKPR.Res \ Reserved
+ $f constant CLKPR_CLKPS \ Clock Prescaler Select Bits
+ 61 $f bitmask: CLKPR.CLKPS \ Clock Prescaler Select Bits
+$53 constant SMCR \ Sleep Mode Control Register
+ $f0 constant SMCR_Res \ Reserved
+ 53 $f0 bitmask: SMCR.Res \ Reserved
+ $e constant SMCR_SM \ Sleep Mode Select bits
+ 53 $e bitmask: SMCR.SM \ Sleep Mode Select bits
+ $1 constant SMCR_SE \ Sleep Enable
+ 53 $1 bitmask: SMCR.SE \ Sleep Enable
+$5c constant EIND \ Extended Indirect Register
+$5b constant RAMPZ \ Extended Z-pointer Register fo
+ $fc constant RAMPZ_Res \ Reserved
+ 5b $fc bitmask: RAMPZ.Res \ Reserved
+ $3 constant RAMPZ_RAMPZ \ Extended Z-Pointer Value
+ 5b $3 bitmask: RAMPZ.RAMPZ \ Extended Z-Pointer Value
+$4b constant GPIOR2 \ General Purpose I/O Register 2
+ $ff constant GPIOR2_GPIOR \ General Purpose I/O Register 2
+ 4b $ff bitmask: GPIOR2.GPIOR \ General Purpose I/O Register 2
+$4a constant GPIOR1 \ General Purpose IO Register 1
+ $ff constant GPIOR1_GPIOR \ General Purpose I/O Register 1
+ 4a $ff bitmask: GPIOR1.GPIOR \ General Purpose I/O Register 1
+$3e constant GPIOR0 \ General Purpose IO Register 0
+ $80 constant GPIOR0_GPIOR07 \ General Purpose I/O Register 0
+ 3e $80 bitmask: GPIOR0.GPIOR07 \ General Purpose I/O Register 0
+ $40 constant GPIOR0_GPIOR06 \ General Purpose I/O Register 0
+ 3e $40 bitmask: GPIOR0.GPIOR06 \ General Purpose I/O Register 0
+ $20 constant GPIOR0_GPIOR05 \ General Purpose I/O Register 0
+ 3e $20 bitmask: GPIOR0.GPIOR05 \ General Purpose I/O Register 0
+ $10 constant GPIOR0_GPIOR04 \ General Purpose I/O Register 0
+ 3e $10 bitmask: GPIOR0.GPIOR04 \ General Purpose I/O Register 0
+ $8 constant GPIOR0_GPIOR03 \ General Purpose I/O Register 0
+ 3e $8 bitmask: GPIOR0.GPIOR03 \ General Purpose I/O Register 0
+ $4 constant GPIOR0_GPIOR02 \ General Purpose I/O Register 0
+ 3e $4 bitmask: GPIOR0.GPIOR02 \ General Purpose I/O Register 0
+ $2 constant GPIOR0_GPIOR01 \ General Purpose I/O Register 0
+ 3e $2 bitmask: GPIOR0.GPIOR01 \ General Purpose I/O Register 0
+ $1 constant GPIOR0_GPIOR00 \ General Purpose I/O Register 0
+ 3e $1 bitmask: GPIOR0.GPIOR00 \ General Purpose I/O Register 0
+$63 constant PRR2 \ Power Reduction Register 2
+ $f0 constant PRR2_Res \ Reserved Bit
+ 63 $f0 bitmask: PRR2.Res \ Reserved Bit
+ $f constant PRR2_PRRAM \ Power Reduction SRAMs
+ 63 $f bitmask: PRR2.PRRAM \ Power Reduction SRAMs
+$65 constant PRR1 \ Power Reduction Register 1
+ $80 constant PRR1_Res \ Reserved Bit
+ 65 $80 bitmask: PRR1.Res \ Reserved Bit
+ $40 constant PRR1_PRTRX24 \ Power Reduction Transceiver
+ 65 $40 bitmask: PRR1.PRTRX24 \ Power Reduction Transceiver
+ $20 constant PRR1_PRTIM5 \ Power Reduction Timer/Counter5
+ 65 $20 bitmask: PRR1.PRTIM5 \ Power Reduction Timer/Counter5
+ $10 constant PRR1_PRTIM4 \ Power Reduction Timer/Counter4
+ 65 $10 bitmask: PRR1.PRTIM4 \ Power Reduction Timer/Counter4
+ $8 constant PRR1_PRTIM3 \ Power Reduction Timer/Counter3
+ 65 $8 bitmask: PRR1.PRTIM3 \ Power Reduction Timer/Counter3
+ $1 constant PRR1_PRUSART1 \ Power Reduction USART1
+ 65 $1 bitmask: PRR1.PRUSART1 \ Power Reduction USART1
+$64 constant PRR0 \ Power Reduction Register0
+ $80 constant PRR0_PRTWI \ Power Reduction TWI
+ 64 $80 bitmask: PRR0.PRTWI \ Power Reduction TWI
+ $40 constant PRR0_PRTIM2 \ Power Reduction Timer/Counter2
+ 64 $40 bitmask: PRR0.PRTIM2 \ Power Reduction Timer/Counter2
+ $20 constant PRR0_PRTIM0 \ Power Reduction Timer/Counter0
+ 64 $20 bitmask: PRR0.PRTIM0 \ Power Reduction Timer/Counter0
+ $10 constant PRR0_PRPGA \ Power Reduction PGA
+ 64 $10 bitmask: PRR0.PRPGA \ Power Reduction PGA
+ $8 constant PRR0_PRTIM1 \ Power Reduction Timer/Counter1
+ 64 $8 bitmask: PRR0.PRTIM1 \ Power Reduction Timer/Counter1
+ $4 constant PRR0_PRSPI \ Power Reduction Serial Periphe
+ 64 $4 bitmask: PRR0.PRSPI \ Power Reduction Serial Periphe
+ $2 constant PRR0_PRUSART0 \ Power Reduction USART
+ 64 $2 bitmask: PRR0.PRUSART0 \ Power Reduction USART
+ $1 constant PRR0_PRADC \ Power Reduction ADC
+ 64 $1 bitmask: PRR0.PRADC \ Power Reduction ADC
diff --git a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/EEPROM.frt b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/EEPROM.frt
new file mode 100644
index 0000000..e56ad19
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/EEPROM.frt
@@ -0,0 +1,19 @@
+\ Generated automatically for atmega256rfr2
+\ #require bitnames.frt
+
+\ EEPROM
+$41 constant EEAR \ EEPROM Address Register Bytes
+$40 constant EEDR \ EEPROM Data Register
+$3f constant EECR \ EEPROM Control Register
+ $c0 constant EECR_Res \ Reserved
+ 3f $c0 bitmask: EECR.Res \ Reserved
+ $30 constant EECR_EEPM \ EEPROM Programming Mode
+ 3f $30 bitmask: EECR.EEPM \ EEPROM Programming Mode
+ $8 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
+ 3f $8 bitmask: EECR.EERIE \ EEPROM Ready Interrupt Enable
+ $4 constant EECR_EEMPE \ EEPROM Master Write Enable
+ 3f $4 bitmask: EECR.EEMPE \ EEPROM Master Write Enable
+ $2 constant EECR_EEPE \ EEPROM Programming Enable
+ 3f $2 bitmask: EECR.EEPE \ EEPROM Programming Enable
+ $1 constant EECR_EERE \ EEPROM Read Enable
+ 3f $1 bitmask: EECR.EERE \ EEPROM Read Enable
diff --git a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/EXTERNAL_INTERRUPT.frt b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/EXTERNAL_INTERRUPT.frt
new file mode 100644
index 0000000..4e7c1fc
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/EXTERNAL_INTERRUPT.frt
@@ -0,0 +1,45 @@
+\ Generated automatically for atmega256rfr2
+\ #require bitnames.frt
+
+\ EXTERNAL_INTERRUPT
+$69 constant EICRA \ External Interrupt Control Reg
+ $c0 constant EICRA_ISC3 \ External Interrupt 3 Sense Con
+ 69 $c0 bitmask: EICRA.ISC3 \ External Interrupt 3 Sense Con
+ $30 constant EICRA_ISC2 \ External Interrupt 2 Sense Con
+ 69 $30 bitmask: EICRA.ISC2 \ External Interrupt 2 Sense Con
+ $c constant EICRA_ISC1 \ External Interrupt 1 Sense Con
+ 69 $c bitmask: EICRA.ISC1 \ External Interrupt 1 Sense Con
+ $3 constant EICRA_ISC0 \ External Interrupt 0 Sense Con
+ 69 $3 bitmask: EICRA.ISC0 \ External Interrupt 0 Sense Con
+$6a constant EICRB \ External Interrupt Control Reg
+ $c0 constant EICRB_ISC7 \ External Interrupt 7 Sense Con
+ 6a $c0 bitmask: EICRB.ISC7 \ External Interrupt 7 Sense Con
+ $30 constant EICRB_ISC6 \ External Interrupt 6 Sense Con
+ 6a $30 bitmask: EICRB.ISC6 \ External Interrupt 6 Sense Con
+ $c constant EICRB_ISC5 \ External Interrupt 5 Sense Con
+ 6a $c bitmask: EICRB.ISC5 \ External Interrupt 5 Sense Con
+ $3 constant EICRB_ISC4 \ External Interrupt 4 Sense Con
+ 6a $3 bitmask: EICRB.ISC4 \ External Interrupt 4 Sense Con
+$3d constant EIMSK \ External Interrupt Mask Regist
+ $ff constant EIMSK_INT \ External Interrupt Request Ena
+ 3d $ff bitmask: EIMSK.INT \ External Interrupt Request Ena
+$3c constant EIFR \ External Interrupt Flag Regist
+ $ff constant EIFR_INTF \ External Interrupt Flag
+ 3c $ff bitmask: EIFR.INTF \ External Interrupt Flag
+$6d constant PCMSK2 \ Pin Change Mask Register 2
+ $ff constant PCMSK2_PCINT \ Pin Change Enable Mask
+ 6d $ff bitmask: PCMSK2.PCINT \ Pin Change Enable Mask
+$6c constant PCMSK1 \ Pin Change Mask Register 1
+ $ff constant PCMSK1_PCINT \ Pin Change Enable Mask
+ 6c $ff bitmask: PCMSK1.PCINT \ Pin Change Enable Mask
+$6b constant PCMSK0 \ Pin Change Mask Register 0
+$3b constant PCIFR \ Pin Change Interrupt Flag Regi
+ $f8 constant PCIFR_Res \ Reserved Bit
+ 3b $f8 bitmask: PCIFR.Res \ Reserved Bit
+ $7 constant PCIFR_PCIF \ Pin Change Interrupt Flags
+ 3b $7 bitmask: PCIFR.PCIF \ Pin Change Interrupt Flags
+$68 constant PCICR \ Pin Change Interrupt Control R
+ $f8 constant PCICR_Res \ Reserved Bit
+ 68 $f8 bitmask: PCICR.Res \ Reserved Bit
+ $7 constant PCICR_PCIE \ Pin Change Interrupt Enables
+ 68 $7 bitmask: PCICR.PCIE \ Pin Change Interrupt Enables
diff --git a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/FLASH.frt b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/FLASH.frt
new file mode 100644
index 0000000..c219192
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/FLASH.frt
@@ -0,0 +1,16 @@
+\ Generated automatically for atmega256rfr2
+\ #require bitnames.frt
+
+\ FLASH
+$75 constant NEMCR \ Flash Extended-Mode Control-Re
+ $40 constant NEMCR_ENEAM \ Enable Extended Address Mode f
+ 75 $40 bitmask: NEMCR.ENEAM \ Enable Extended Address Mode f
+ $30 constant NEMCR_AEAM \ Address for Extended Address M
+ 75 $30 bitmask: NEMCR.AEAM \ Address for Extended Address M
+$67 constant BGCR \ Reference Voltage Calibration
+ $80 constant BGCR_Res \ Reserved Bit
+ 67 $80 bitmask: BGCR.Res \ Reserved Bit
+ $78 constant BGCR_BGCAL_FINE \ Fine Calibration Bits
+ 67 $78 bitmask: BGCR.BGCAL_FINE \ Fine Calibration Bits
+ $7 constant BGCR_BGCAL \ Coarse Calibration Bits
+ 67 $7 bitmask: BGCR.BGCAL \ Coarse Calibration Bits
diff --git a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/JTAG.frt b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/JTAG.frt
new file mode 100644
index 0000000..1960eac
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/JTAG.frt
@@ -0,0 +1,13 @@
+\ Generated automatically for atmega256rfr2
+\ #require bitnames.frt
+
+\ JTAG
+$51 constant OCDR \ On-Chip Debug Register
+ $ff constant OCDR_OCDR \ On-Chip Debug Register Data
+ 51 $ff bitmask: OCDR.OCDR \ On-Chip Debug Register Data
+$55 constant MCUCR \ MCU Control Register
+ $80 constant MCUCR_JTD \ JTAG Interface Disable
+ 55 $80 bitmask: MCUCR.JTD \ JTAG Interface Disable
+$54 constant MCUSR \ MCU Status Register
+ $10 constant MCUSR_JTRF \ JTAG Reset Flag
+ 54 $10 bitmask: MCUSR.JTRF \ JTAG Reset Flag
diff --git a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/PORTA.frt b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/PORTA.frt
new file mode 100644
index 0000000..0c4e462
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/PORTA.frt
@@ -0,0 +1,7 @@
+\ Generated automatically for atmega256rfr2
+\ #require bitnames.frt
+
+\ PORTA
+$22 constant PORTA \ Port A Data Register
+$21 constant DDRA \ Port A Data Direction Register
+$20 constant PINA \ Port A Input Pins Address
diff --git a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/PORTB.frt b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/PORTB.frt
new file mode 100644
index 0000000..493d57a
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/PORTB.frt
@@ -0,0 +1,7 @@
+\ Generated automatically for atmega256rfr2
+\ #require bitnames.frt
+
+\ PORTB
+$25 constant PORTB \ Port B Data Register
+$24 constant DDRB \ Port B Data Direction Register
+$23 constant PINB \ Port B Input Pins Address
diff --git a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/PORTC.frt b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/PORTC.frt
new file mode 100644
index 0000000..dfb169b
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/PORTC.frt
@@ -0,0 +1,7 @@
+\ Generated automatically for atmega256rfr2
+\ #require bitnames.frt
+
+\ PORTC
+$28 constant PORTC \ Port C Data Register
+$27 constant DDRC \ Port C Data Direction Register
+$26 constant PINC \ Port C Input Pins Address
diff --git a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/PORTD.frt b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/PORTD.frt
new file mode 100644
index 0000000..d46daaa
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/PORTD.frt
@@ -0,0 +1,7 @@
+\ Generated automatically for atmega256rfr2
+\ #require bitnames.frt
+
+\ PORTD
+$2b constant PORTD \ Port D Data Register
+$2a constant DDRD \ Port D Data Direction Register
+$29 constant PIND \ Port D Input Pins Address
diff --git a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/PORTE.frt b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/PORTE.frt
new file mode 100644
index 0000000..feadc5c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/PORTE.frt
@@ -0,0 +1,7 @@
+\ Generated automatically for atmega256rfr2
+\ #require bitnames.frt
+
+\ PORTE
+$2e constant PORTE \ Port E Data Register
+$2d constant DDRE \ Port E Data Direction Register
+$2c constant PINE \ Port E Input Pins Address
diff --git a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/PORTF.frt b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/PORTF.frt
new file mode 100644
index 0000000..d4c2e02
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/PORTF.frt
@@ -0,0 +1,7 @@
+\ Generated automatically for atmega256rfr2
+\ #require bitnames.frt
+
+\ PORTF
+$31 constant PORTF \ Port F Data Register
+$30 constant DDRF \ Port F Data Direction Register
+$2f constant PINF \ Port F Input Pins Address
diff --git a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/PORTG.frt b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/PORTG.frt
new file mode 100644
index 0000000..53a190c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/PORTG.frt
@@ -0,0 +1,7 @@
+\ Generated automatically for atmega256rfr2
+\ #require bitnames.frt
+
+\ PORTG
+$34 constant PORTG \ Port G Data Register
+$33 constant DDRG \ Port G Data Direction Register
+$32 constant PING \ Port G Input Pins Address
diff --git a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/PWRCTRL.frt b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/PWRCTRL.frt
new file mode 100644
index 0000000..2ba9d2e
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/PWRCTRL.frt
@@ -0,0 +1,81 @@
+\ Generated automatically for atmega256rfr2
+\ #require bitnames.frt
+
+\ PWRCTRL
+$139 constant TRXPR \ Transceiver Pin Register
+ $f0 constant TRXPR_Res \ Reserved
+ 139 $f0 bitmask: TRXPR.Res \ Reserved
+ $2 constant TRXPR_SLPTR \ Multi-purpose Transceiver Cont
+ 139 $2 bitmask: TRXPR.SLPTR \ Multi-purpose Transceiver Cont
+ $1 constant TRXPR_TRXRST \ Force Transceiver Reset
+ 139 $1 bitmask: TRXPR.TRXRST \ Force Transceiver Reset
+$135 constant DRTRAM0 \ Data Retention Configuration R
+ $c0 constant DRTRAM0_Res \ Reserved
+ 135 $c0 bitmask: DRTRAM0.Res \ Reserved
+ $20 constant DRTRAM0_DRTSWOK \ DRT Switch OK
+ 135 $20 bitmask: DRTRAM0.DRTSWOK \ DRT Switch OK
+ $10 constant DRTRAM0_ENDRT \ Enable SRAM Data Retention
+ 135 $10 bitmask: DRTRAM0.ENDRT \ Enable SRAM Data Retention
+$134 constant DRTRAM1 \ Data Retention Configuration R
+ $c0 constant DRTRAM1_Res \ Reserved
+ 134 $c0 bitmask: DRTRAM1.Res \ Reserved
+ $20 constant DRTRAM1_DRTSWOK \ DRT Switch OK
+ 134 $20 bitmask: DRTRAM1.DRTSWOK \ DRT Switch OK
+ $10 constant DRTRAM1_ENDRT \ Enable SRAM Data Retention
+ 134 $10 bitmask: DRTRAM1.ENDRT \ Enable SRAM Data Retention
+$133 constant DRTRAM2 \ Data Retention Configuration R
+ $40 constant DRTRAM2_Res \ Reserved Bit
+ 133 $40 bitmask: DRTRAM2.Res \ Reserved Bit
+ $20 constant DRTRAM2_DRTSWOK \ DRT Switch OK
+ 133 $20 bitmask: DRTRAM2.DRTSWOK \ DRT Switch OK
+ $10 constant DRTRAM2_ENDRT \ Enable SRAM Data Retention
+ 133 $10 bitmask: DRTRAM2.ENDRT \ Enable SRAM Data Retention
+$132 constant DRTRAM3 \ Data Retention Configuration R
+ $c0 constant DRTRAM3_Res \ Reserved
+ 132 $c0 bitmask: DRTRAM3.Res \ Reserved
+ $20 constant DRTRAM3_DRTSWOK \ DRT Switch OK
+ 132 $20 bitmask: DRTRAM3.DRTSWOK \ DRT Switch OK
+ $10 constant DRTRAM3_ENDRT \ Enable SRAM Data Retention
+ 132 $10 bitmask: DRTRAM3.ENDRT \ Enable SRAM Data Retention
+$130 constant LLDRL \ Low Leakage Voltage Regulator
+ $f0 constant LLDRL_Res \ Reserved
+ 130 $f0 bitmask: LLDRL.Res \ Reserved
+ $f constant LLDRL_LLDRL \ Low-Byte Data Register Bits
+ 130 $f bitmask: LLDRL.LLDRL \ Low-Byte Data Register Bits
+$131 constant LLDRH \ Low Leakage Voltage Regulator
+ $e0 constant LLDRH_Res \ Reserved
+ 131 $e0 bitmask: LLDRH.Res \ Reserved
+ $1f constant LLDRH_LLDRH \ High-Byte Data Register Bits
+ 131 $1f bitmask: LLDRH.LLDRH \ High-Byte Data Register Bits
+$12f constant LLCR \ Low Leakage Voltage Regulator
+ $c0 constant LLCR_Res \ Reserved Bit
+ 12f $c0 bitmask: LLCR.Res \ Reserved Bit
+ $20 constant LLCR_LLDONE \ Calibration Done
+ 12f $20 bitmask: LLCR.LLDONE \ Calibration Done
+ $10 constant LLCR_LLCOMP \ Comparator Output
+ 12f $10 bitmask: LLCR.LLCOMP \ Comparator Output
+ $8 constant LLCR_LLCAL \ Calibration Active
+ 12f $8 bitmask: LLCR.LLCAL \ Calibration Active
+ $4 constant LLCR_LLTCO \ Temperature Coefficient of Cur
+ 12f $4 bitmask: LLCR.LLTCO \ Temperature Coefficient of Cur
+ $2 constant LLCR_LLSHORT \ Short Lower Calibration Circui
+ 12f $2 bitmask: LLCR.LLSHORT \ Short Lower Calibration Circui
+ $1 constant LLCR_LLENCAL \ Enable Automatic Calibration
+ 12f $1 bitmask: LLCR.LLENCAL \ Enable Automatic Calibration
+$136 constant DPDS0 \ Port Driver Strength Register
+ $c0 constant DPDS0_PFDRV \ Driver Strength Port F
+ 136 $c0 bitmask: DPDS0.PFDRV \ Driver Strength Port F
+ $30 constant DPDS0_PEDRV \ Driver Strength Port E
+ 136 $30 bitmask: DPDS0.PEDRV \ Driver Strength Port E
+ $c constant DPDS0_PDDRV \ Driver Strength Port D
+ 136 $c bitmask: DPDS0.PDDRV \ Driver Strength Port D
+ $3 constant DPDS0_PBDRV \ Driver Strength Port B
+ 136 $3 bitmask: DPDS0.PBDRV \ Driver Strength Port B
+$137 constant DPDS1 \ Port Driver Strength Register
+ $fc constant DPDS1_Res \ Reserved
+ 137 $fc bitmask: DPDS1.Res \ Reserved
+ $3 constant DPDS1_PGDRV \ Driver Strength Port G
+ 137 $3 bitmask: DPDS1.PGDRV \ Driver Strength Port G
+$55 constant MCUCR \ MCU Control Register
+ $10 constant MCUCR_PUD \ Pull-up Disable
+ 55 $10 bitmask: MCUCR.PUD \ Pull-up Disable
diff --git a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/SPI.frt b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/SPI.frt
new file mode 100644
index 0000000..53bae0e
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/SPI.frt
@@ -0,0 +1,29 @@
+\ Generated automatically for atmega256rfr2
+\ #require bitnames.frt
+
+\ SPI
+$4c constant SPCR \ SPI Control Register
+ $80 constant SPCR_SPIE \ SPI Interrupt Enable
+ 4c $80 bitmask: SPCR.SPIE \ SPI Interrupt Enable
+ $40 constant SPCR_SPE \ SPI Enable
+ 4c $40 bitmask: SPCR.SPE \ SPI Enable
+ $20 constant SPCR_DORD \ Data Order
+ 4c $20 bitmask: SPCR.DORD \ Data Order
+ $10 constant SPCR_MSTR \ Master/Slave Select
+ 4c $10 bitmask: SPCR.MSTR \ Master/Slave Select
+ $8 constant SPCR_CPOL \ Clock polarity
+ 4c $8 bitmask: SPCR.CPOL \ Clock polarity
+ $4 constant SPCR_CPHA \ Clock Phase
+ 4c $4 bitmask: SPCR.CPHA \ Clock Phase
+ $3 constant SPCR_SPR \ SPI Clock Rate Select 1 and 0
+ 4c $3 bitmask: SPCR.SPR \ SPI Clock Rate Select 1 and 0
+$4d constant SPSR \ SPI Status Register
+ $80 constant SPSR_SPIF \ SPI Interrupt Flag
+ 4d $80 bitmask: SPSR.SPIF \ SPI Interrupt Flag
+ $40 constant SPSR_WCOL \ Write Collision Flag
+ 4d $40 bitmask: SPSR.WCOL \ Write Collision Flag
+ $3e constant SPSR_Res \ Reserved
+ 4d $3e bitmask: SPSR.Res \ Reserved
+ $1 constant SPSR_SPI2X \ Double SPI Speed Bit
+ 4d $1 bitmask: SPSR.SPI2X \ Double SPI Speed Bit
+$4e constant SPDR \ SPI Data Register
diff --git a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/SYMCNT.frt b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/SYMCNT.frt
new file mode 100644
index 0000000..26c4758
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/SYMCNT.frt
@@ -0,0 +1,156 @@
+\ Generated automatically for atmega256rfr2
+\ #require bitnames.frt
+
+\ SYMCNT
+$fc constant SCTSTRHH \ Symbol Counter Transmit Frame
+ $ff constant SCTSTRHH_SCTSTRHH \ Symbol Counter Transmit Frame
+ fc $ff bitmask: SCTSTRHH.SCTSTRHH \ Symbol Counter Transmit Frame
+$fb constant SCTSTRHL \ Symbol Counter Transmit Frame
+ $ff constant SCTSTRHL_SCTSTRHL \ Symbol Counter Transmit Frame
+ fb $ff bitmask: SCTSTRHL.SCTSTRHL \ Symbol Counter Transmit Frame
+$fa constant SCTSTRLH \ Symbol Counter Transmit Frame
+ $ff constant SCTSTRLH_SCTSTRLH \ Symbol Counter Transmit Frame
+ fa $ff bitmask: SCTSTRLH.SCTSTRLH \ Symbol Counter Transmit Frame
+$f9 constant SCTSTRLL \ Symbol Counter Transmit Frame
+ $ff constant SCTSTRLL_SCTSTRLL \ Symbol Counter Transmit Frame
+ f9 $ff bitmask: SCTSTRLL.SCTSTRLL \ Symbol Counter Transmit Frame
+$f8 constant SCOCR1HH \ Symbol Counter Output Compare
+ $ff constant SCOCR1HH_SCOCR1HH \ Symbol Counter Output Compare
+ f8 $ff bitmask: SCOCR1HH.SCOCR1HH \ Symbol Counter Output Compare
+$f7 constant SCOCR1HL \ Symbol Counter Output Compare
+ $ff constant SCOCR1HL_SCOCR1HL \ Symbol Counter Output Compare
+ f7 $ff bitmask: SCOCR1HL.SCOCR1HL \ Symbol Counter Output Compare
+$f6 constant SCOCR1LH \ Symbol Counter Output Compare
+ $ff constant SCOCR1LH_SCOCR1LH \ Symbol Counter Output Compare
+ f6 $ff bitmask: SCOCR1LH.SCOCR1LH \ Symbol Counter Output Compare
+$f5 constant SCOCR1LL \ Symbol Counter Output Compare
+ $ff constant SCOCR1LL_SCOCR1LL \ Symbol Counter Output Compare
+ f5 $ff bitmask: SCOCR1LL.SCOCR1LL \ Symbol Counter Output Compare
+$f4 constant SCOCR2HH \ Symbol Counter Output Compare
+ $ff constant SCOCR2HH_SCOCR2HH \ Symbol Counter Output Compare
+ f4 $ff bitmask: SCOCR2HH.SCOCR2HH \ Symbol Counter Output Compare
+$f3 constant SCOCR2HL \ Symbol Counter Output Compare
+ $ff constant SCOCR2HL_SCOCR2HL \ Symbol Counter Output Compare
+ f3 $ff bitmask: SCOCR2HL.SCOCR2HL \ Symbol Counter Output Compare
+$f2 constant SCOCR2LH \ Symbol Counter Output Compare
+ $ff constant SCOCR2LH_SCOCR2LH \ Symbol Counter Output Compare
+ f2 $ff bitmask: SCOCR2LH.SCOCR2LH \ Symbol Counter Output Compare
+$f1 constant SCOCR2LL \ Symbol Counter Output Compare
+ $ff constant SCOCR2LL_SCOCR2LL \ Symbol Counter Output Compare
+ f1 $ff bitmask: SCOCR2LL.SCOCR2LL \ Symbol Counter Output Compare
+$f0 constant SCOCR3HH \ Symbol Counter Output Compare
+ $ff constant SCOCR3HH_SCOCR3HH \ Symbol Counter Output Compare
+ f0 $ff bitmask: SCOCR3HH.SCOCR3HH \ Symbol Counter Output Compare
+$ef constant SCOCR3HL \ Symbol Counter Output Compare
+ $ff constant SCOCR3HL_SCOCR3HL \ Symbol Counter Output Compare
+ ef $ff bitmask: SCOCR3HL.SCOCR3HL \ Symbol Counter Output Compare
+$ee constant SCOCR3LH \ Symbol Counter Output Compare
+ $ff constant SCOCR3LH_SCOCR3LH \ Symbol Counter Output Compare
+ ee $ff bitmask: SCOCR3LH.SCOCR3LH \ Symbol Counter Output Compare
+$ed constant SCOCR3LL \ Symbol Counter Output Compare
+ $ff constant SCOCR3LL_SCOCR3LL \ Symbol Counter Output Compare
+ ed $ff bitmask: SCOCR3LL.SCOCR3LL \ Symbol Counter Output Compare
+$ec constant SCTSRHH \ Symbol Counter Frame Timestamp
+ $ff constant SCTSRHH_SCTSRHH \ Symbol Counter Frame Timestamp
+ ec $ff bitmask: SCTSRHH.SCTSRHH \ Symbol Counter Frame Timestamp
+$eb constant SCTSRHL \ Symbol Counter Frame Timestamp
+ $ff constant SCTSRHL_SCTSRHL \ Symbol Counter Frame Timestamp
+ eb $ff bitmask: SCTSRHL.SCTSRHL \ Symbol Counter Frame Timestamp
+$ea constant SCTSRLH \ Symbol Counter Frame Timestamp
+ $ff constant SCTSRLH_SCTSRLH \ Symbol Counter Frame Timestamp
+ ea $ff bitmask: SCTSRLH.SCTSRLH \ Symbol Counter Frame Timestamp
+$e9 constant SCTSRLL \ Symbol Counter Frame Timestamp
+ $ff constant SCTSRLL_SCTSRLL \ Symbol Counter Frame Timestamp
+ e9 $ff bitmask: SCTSRLL.SCTSRLL \ Symbol Counter Frame Timestamp
+$e8 constant SCBTSRHH \ Symbol Counter Beacon Timestam
+ $ff constant SCBTSRHH_SCBTSRHH \ Symbol Counter Beacon Timestam
+ e8 $ff bitmask: SCBTSRHH.SCBTSRHH \ Symbol Counter Beacon Timestam
+$e7 constant SCBTSRHL \ Symbol Counter Beacon Timestam
+ $ff constant SCBTSRHL_SCBTSRHL \ Symbol Counter Beacon Timestam
+ e7 $ff bitmask: SCBTSRHL.SCBTSRHL \ Symbol Counter Beacon Timestam
+$e6 constant SCBTSRLH \ Symbol Counter Beacon Timestam
+ $ff constant SCBTSRLH_SCBTSRLH \ Symbol Counter Beacon Timestam
+ e6 $ff bitmask: SCBTSRLH.SCBTSRLH \ Symbol Counter Beacon Timestam
+$e5 constant SCBTSRLL \ Symbol Counter Beacon Timestam
+ $ff constant SCBTSRLL_SCBTSRLL \ Symbol Counter Beacon Timestam
+ e5 $ff bitmask: SCBTSRLL.SCBTSRLL \ Symbol Counter Beacon Timestam
+$e4 constant SCCNTHH \ Symbol Counter Register HH-Byt
+ $ff constant SCCNTHH_SCCNTHH \ Symbol Counter Register HH-Byt
+ e4 $ff bitmask: SCCNTHH.SCCNTHH \ Symbol Counter Register HH-Byt
+$e3 constant SCCNTHL \ Symbol Counter Register HL-Byt
+ $ff constant SCCNTHL_SCCNTHL \ Symbol Counter Register HL-Byt
+ e3 $ff bitmask: SCCNTHL.SCCNTHL \ Symbol Counter Register HL-Byt
+$e2 constant SCCNTLH \ Symbol Counter Register LH-Byt
+ $ff constant SCCNTLH_SCCNTLH \ Symbol Counter Register LH-Byt
+ e2 $ff bitmask: SCCNTLH.SCCNTLH \ Symbol Counter Register LH-Byt
+$e1 constant SCCNTLL \ Symbol Counter Register LL-Byt
+ $ff constant SCCNTLL_SCCNTLL \ Symbol Counter Register LL-Byt
+ e1 $ff bitmask: SCCNTLL.SCCNTLL \ Symbol Counter Register LL-Byt
+$e0 constant SCIRQS \ Symbol Counter Interrupt Statu
+ $e0 constant SCIRQS_Res \ Reserved Bit
+ e0 $e0 bitmask: SCIRQS.Res \ Reserved Bit
+ $10 constant SCIRQS_IRQSBO \ Backoff Slot Counter IRQ
+ e0 $10 bitmask: SCIRQS.IRQSBO \ Backoff Slot Counter IRQ
+ $8 constant SCIRQS_IRQSOF \ Symbol Counter Overflow IRQ
+ e0 $8 bitmask: SCIRQS.IRQSOF \ Symbol Counter Overflow IRQ
+ $7 constant SCIRQS_IRQSCP \ Compare Unit 3 Compare Match I
+ e0 $7 bitmask: SCIRQS.IRQSCP \ Compare Unit 3 Compare Match I
+$df constant SCIRQM \ Symbol Counter Interrupt Mask
+ $e0 constant SCIRQM_Res \ Reserved Bit
+ df $e0 bitmask: SCIRQM.Res \ Reserved Bit
+ $10 constant SCIRQM_IRQMBO \ Backoff Slot Counter IRQ enabl
+ df $10 bitmask: SCIRQM.IRQMBO \ Backoff Slot Counter IRQ enabl
+ $8 constant SCIRQM_IRQMOF \ Symbol Counter Overflow IRQ en
+ df $8 bitmask: SCIRQM.IRQMOF \ Symbol Counter Overflow IRQ en
+ $7 constant SCIRQM_IRQMCP \ Symbol Counter Compare Match 3
+ df $7 bitmask: SCIRQM.IRQMCP \ Symbol Counter Compare Match 3
+$de constant SCSR \ Symbol Counter Status Register
+ $fe constant SCSR_Res \ Reserved Bit
+ de $fe bitmask: SCSR.Res \ Reserved Bit
+ $1 constant SCSR_SCBSY \ Symbol Counter busy
+ de $1 bitmask: SCSR.SCBSY \ Symbol Counter busy
+$dd constant SCCR1 \ Symbol Counter Control Registe
+ $c0 constant SCCR1_Res \ Reserved Bit
+ dd $c0 bitmask: SCCR1.Res \ Reserved Bit
+ $20 constant SCCR1_SCBTSM \ Symbol Counter Beacon Timestam
+ dd $20 bitmask: SCCR1.SCBTSM \ Symbol Counter Beacon Timestam
+ $1c constant SCCR1_SCCKDIV \ Clock divider for synchronous
+ dd $1c bitmask: SCCR1.SCCKDIV \ Clock divider for synchronous
+ $2 constant SCCR1_SCEECLK \ Enable External Clock Source o
+ dd $2 bitmask: SCCR1.SCEECLK \ Enable External Clock Source o
+ $1 constant SCCR1_SCENBO \ Backoff Slot Counter enable
+ dd $1 bitmask: SCCR1.SCENBO \ Backoff Slot Counter enable
+$dc constant SCCR0 \ Symbol Counter Control Registe
+ $80 constant SCCR0_SCRES \ Symbol Counter Synchronization
+ dc $80 bitmask: SCCR0.SCRES \ Symbol Counter Synchronization
+ $40 constant SCCR0_SCMBTS \ Manual Beacon Timestamp
+ dc $40 bitmask: SCCR0.SCMBTS \ Manual Beacon Timestamp
+ $20 constant SCCR0_SCEN \ Symbol Counter enable
+ dc $20 bitmask: SCCR0.SCEN \ Symbol Counter enable
+ $10 constant SCCR0_SCCKSEL \ Symbol Counter Clock Source se
+ dc $10 bitmask: SCCR0.SCCKSEL \ Symbol Counter Clock Source se
+ $8 constant SCCR0_SCTSE \ Symbol Counter Automatic Times
+ dc $8 bitmask: SCCR0.SCTSE \ Symbol Counter Automatic Times
+ $7 constant SCCR0_SCCMP \ Symbol Counter Compare Unit 3
+ dc $7 bitmask: SCCR0.SCCMP \ Symbol Counter Compare Unit 3
+$db constant SCCSR \ Symbol Counter Compare Source
+ $c0 constant SCCSR_Res \ Reserved Bit
+ db $c0 bitmask: SCCSR.Res \ Reserved Bit
+ $30 constant SCCSR_SCCS3 \ Symbol Counter Compare Source
+ db $30 bitmask: SCCSR.SCCS3 \ Symbol Counter Compare Source
+ $c constant SCCSR_SCCS2 \ Symbol Counter Compare Source
+ db $c bitmask: SCCSR.SCCS2 \ Symbol Counter Compare Source
+ $3 constant SCCSR_SCCS1 \ Symbol Counter Compare Source
+ db $3 bitmask: SCCSR.SCCS1 \ Symbol Counter Compare Source
+$da constant SCRSTRHH \ Symbol Counter Received Frame
+ $ff constant SCRSTRHH_SCRSTRHH \ Symbol Counter Received Frame
+ da $ff bitmask: SCRSTRHH.SCRSTRHH \ Symbol Counter Received Frame
+$d9 constant SCRSTRHL \ Symbol Counter Received Frame
+ $ff constant SCRSTRHL_SCRSTRHL \ Symbol Counter Received Frame
+ d9 $ff bitmask: SCRSTRHL.SCRSTRHL \ Symbol Counter Received Frame
+$d8 constant SCRSTRLH \ Symbol Counter Received Frame
+ $ff constant SCRSTRLH_SCRSTRLH \ Symbol Counter Received Frame
+ d8 $ff bitmask: SCRSTRLH.SCRSTRLH \ Symbol Counter Received Frame
+$d7 constant SCRSTRLL \ Symbol Counter Received Frame
+ $ff constant SCRSTRLL_SCRSTRLL \ Symbol Counter Received Frame
+ d7 $ff bitmask: SCRSTRLL.SCRSTRLL \ Symbol Counter Received Frame
diff --git a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/TIMER_COUNTER_0.frt b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/TIMER_COUNTER_0.frt
new file mode 100644
index 0000000..50f60a9
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/TIMER_COUNTER_0.frt
@@ -0,0 +1,54 @@
+\ Generated automatically for atmega256rfr2
+\ #require bitnames.frt
+
+\ TIMER_COUNTER_0
+$48 constant OCR0B \ Timer/Counter0 Output Compare
+$47 constant OCR0A \ Timer/Counter0 Output Compare
+$46 constant TCNT0 \ Timer/Counter0 Register
+$45 constant TCCR0B \ Timer/Counter0 Control Registe
+ $80 constant TCCR0B_FOC0A \ Force Output Compare A
+ 45 $80 bitmask: TCCR0B.FOC0A \ Force Output Compare A
+ $40 constant TCCR0B_FOC0B \ Force Output Compare B
+ 45 $40 bitmask: TCCR0B.FOC0B \ Force Output Compare B
+ $30 constant TCCR0B_Res \ Reserved Bit
+ 45 $30 bitmask: TCCR0B.Res \ Reserved Bit
+ $8 constant TCCR0B_WGM02 \
+ 45 $8 bitmask: TCCR0B.WGM02 \
+ $7 constant TCCR0B_CS0 \ Clock Select
+ 45 $7 bitmask: TCCR0B.CS0 \ Clock Select
+$44 constant TCCR0A \ Timer/Counter0 Control Registe
+ $c0 constant TCCR0A_COM0A \ Compare Match Output A Mode
+ 44 $c0 bitmask: TCCR0A.COM0A \ Compare Match Output A Mode
+ $30 constant TCCR0A_COM0B \ Compare Match Output B Mode
+ 44 $30 bitmask: TCCR0A.COM0B \ Compare Match Output B Mode
+ $c constant TCCR0A_Res \ Reserved Bit
+ 44 $c bitmask: TCCR0A.Res \ Reserved Bit
+ $3 constant TCCR0A_WGM0 \ Waveform Generation Mode
+ 44 $3 bitmask: TCCR0A.WGM0 \ Waveform Generation Mode
+$6e constant TIMSK0 \ Timer/Counter0 Interrupt Mask
+ $f8 constant TIMSK0_Res \ Reserved
+ 6e $f8 bitmask: TIMSK0.Res \ Reserved
+ $4 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare
+ 6e $4 bitmask: TIMSK0.OCIE0B \ Timer/Counter0 Output Compare
+ $2 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare
+ 6e $2 bitmask: TIMSK0.OCIE0A \ Timer/Counter0 Output Compare
+ $1 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interr
+ 6e $1 bitmask: TIMSK0.TOIE0 \ Timer/Counter0 Overflow Interr
+$35 constant TIFR0 \ Timer/Counter0 Interrupt Flag
+ $f8 constant TIFR0_Res \ Reserved
+ 35 $f8 bitmask: TIFR0.Res \ Reserved
+ $4 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare
+ 35 $4 bitmask: TIFR0.OCF0B \ Timer/Counter0 Output Compare
+ $2 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare
+ 35 $2 bitmask: TIFR0.OCF0A \ Timer/Counter0 Output Compare
+ $1 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
+ 35 $1 bitmask: TIFR0.TOV0 \ Timer/Counter0 Overflow Flag
+$43 constant GTCCR \ General Timer/Counter Control
+ $80 constant GTCCR_TSM \ Timer/Counter Synchronization
+ 43 $80 bitmask: GTCCR.TSM \ Timer/Counter Synchronization
+ $7c constant GTCCR_Res \ Reserved
+ 43 $7c bitmask: GTCCR.Res \ Reserved
+ $2 constant GTCCR_PSRASY \ Prescaler Reset Timer/Counter2
+ 43 $2 bitmask: GTCCR.PSRASY \ Prescaler Reset Timer/Counter2
+ $1 constant GTCCR_PSRSYNC \ Prescaler Reset for Synchronou
+ 43 $1 bitmask: GTCCR.PSRSYNC \ Prescaler Reset for Synchronou
diff --git a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/TIMER_COUNTER_1.frt b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/TIMER_COUNTER_1.frt
new file mode 100644
index 0000000..d3b8f20
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/TIMER_COUNTER_1.frt
@@ -0,0 +1,68 @@
+\ Generated automatically for atmega256rfr2
+\ #require bitnames.frt
+
+\ TIMER_COUNTER_1
+$80 constant TCCR1A \ Timer/Counter1 Control Registe
+ $c0 constant TCCR1A_COM1A \ Compare Output Mode for Channe
+ 80 $c0 bitmask: TCCR1A.COM1A \ Compare Output Mode for Channe
+ $30 constant TCCR1A_COM1B \ Compare Output Mode for Channe
+ 80 $30 bitmask: TCCR1A.COM1B \ Compare Output Mode for Channe
+ $c constant TCCR1A_COM1C \ Compare Output Mode for Channe
+ 80 $c bitmask: TCCR1A.COM1C \ Compare Output Mode for Channe
+ $3 constant TCCR1A_WGM1 \ Waveform Generation Mode
+ 80 $3 bitmask: TCCR1A.WGM1 \ Waveform Generation Mode
+$81 constant TCCR1B \ Timer/Counter1 Control Registe
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Cancelle
+ 81 $80 bitmask: TCCR1B.ICNC1 \ Input Capture 1 Noise Cancelle
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ 81 $40 bitmask: TCCR1B.ICES1 \ Input Capture 1 Edge Select
+ $20 constant TCCR1B_Res \ Reserved Bit
+ 81 $20 bitmask: TCCR1B.Res \ Reserved Bit
+ $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
+ 81 $18 bitmask: TCCR1B.WGM1 \ Waveform Generation Mode
+ $7 constant TCCR1B_CS1 \ Clock Select
+ 81 $7 bitmask: TCCR1B.CS1 \ Clock Select
+$82 constant TCCR1C \ Timer/Counter1 Control Registe
+ $80 constant TCCR1C_FOC1A \ Force Output Compare for Chann
+ 82 $80 bitmask: TCCR1C.FOC1A \ Force Output Compare for Chann
+ $40 constant TCCR1C_FOC1B \ Force Output Compare for Chann
+ 82 $40 bitmask: TCCR1C.FOC1B \ Force Output Compare for Chann
+ $20 constant TCCR1C_FOC1C \ Force Output Compare for Chann
+ 82 $20 bitmask: TCCR1C.FOC1C \ Force Output Compare for Chann
+ $1f constant TCCR1C_Res \ Reserved
+ 82 $1f bitmask: TCCR1C.Res \ Reserved
+$84 constant TCNT1 \ Timer/Counter1 Bytes
+$88 constant OCR1A \ Timer/Counter1 Output Compare
+$8a constant OCR1B \ Timer/Counter1 Output Compare
+$8c constant OCR1C \ Timer/Counter1 Output Compare
+$86 constant ICR1 \ Timer/Counter1 Input Capture R
+$6f constant TIMSK1 \ Timer/Counter1 Interrupt Mask
+ $c0 constant TIMSK1_Res \ Reserved Bit
+ 6f $c0 bitmask: TIMSK1.Res \ Reserved Bit
+ $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture I
+ 6f $20 bitmask: TIMSK1.ICIE1 \ Timer/Counter1 Input Capture I
+ $10 constant TIMSK1_Res \ Reserved Bit
+ 6f $10 bitmask: TIMSK1.Res \ Reserved Bit
+ $8 constant TIMSK1_OCIE1C \ Timer/Counter1 Output Compare
+ 6f $8 bitmask: TIMSK1.OCIE1C \ Timer/Counter1 Output Compare
+ $4 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare
+ 6f $4 bitmask: TIMSK1.OCIE1B \ Timer/Counter1 Output Compare
+ $2 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare
+ 6f $2 bitmask: TIMSK1.OCIE1A \ Timer/Counter1 Output Compare
+ $1 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interr
+ 6f $1 bitmask: TIMSK1.TOIE1 \ Timer/Counter1 Overflow Interr
+$36 constant TIFR1 \ Timer/Counter1 Interrupt Flag
+ $c0 constant TIFR1_Res \ Reserved Bit
+ 36 $c0 bitmask: TIFR1.Res \ Reserved Bit
+ $20 constant TIFR1_ICF1 \ Timer/Counter1 Input Capture F
+ 36 $20 bitmask: TIFR1.ICF1 \ Timer/Counter1 Input Capture F
+ $10 constant TIFR1_Res \ Reserved Bit
+ 36 $10 bitmask: TIFR1.Res \ Reserved Bit
+ $8 constant TIFR1_OCF1C \ Timer/Counter1 Output Compare
+ 36 $8 bitmask: TIFR1.OCF1C \ Timer/Counter1 Output Compare
+ $4 constant TIFR1_OCF1B \ Timer/Counter1 Output Compare
+ 36 $4 bitmask: TIFR1.OCF1B \ Timer/Counter1 Output Compare
+ $2 constant TIFR1_OCF1A \ Timer/Counter1 Output Compare
+ 36 $2 bitmask: TIFR1.OCF1A \ Timer/Counter1 Output Compare
+ $1 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
+ 36 $1 bitmask: TIFR1.TOV1 \ Timer/Counter1 Overflow Flag
diff --git a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/TIMER_COUNTER_2.frt b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/TIMER_COUNTER_2.frt
new file mode 100644
index 0000000..748cd79
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/TIMER_COUNTER_2.frt
@@ -0,0 +1,67 @@
+\ Generated automatically for atmega256rfr2
+\ #require bitnames.frt
+
+\ TIMER_COUNTER_2
+$70 constant TIMSK2 \ Timer/Counter Interrupt Mask r
+ $f8 constant TIMSK2_Res \ Reserved Bit
+ 70 $f8 bitmask: TIMSK2.Res \ Reserved Bit
+ $4 constant TIMSK2_OCIE2B \ Timer/Counter2 Output Compare
+ 70 $4 bitmask: TIMSK2.OCIE2B \ Timer/Counter2 Output Compare
+ $2 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare
+ 70 $2 bitmask: TIMSK2.OCIE2A \ Timer/Counter2 Output Compare
+ $1 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interr
+ 70 $1 bitmask: TIMSK2.TOIE2 \ Timer/Counter2 Overflow Interr
+$37 constant TIFR2 \ Timer/Counter Interrupt Flag R
+ $f8 constant TIFR2_Res \ Reserved Bit
+ 37 $f8 bitmask: TIFR2.Res \ Reserved Bit
+ $4 constant TIFR2_OCF2B \ Output Compare Flag 2 B
+ 37 $4 bitmask: TIFR2.OCF2B \ Output Compare Flag 2 B
+ $2 constant TIFR2_OCF2A \ Output Compare Flag 2 A
+ 37 $2 bitmask: TIFR2.OCF2A \ Output Compare Flag 2 A
+ $1 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
+ 37 $1 bitmask: TIFR2.TOV2 \ Timer/Counter2 Overflow Flag
+$b0 constant TCCR2A \ Timer/Counter2 Control Registe
+ $c0 constant TCCR2A_COM2A \ Compare Match Output A Mode
+ b0 $c0 bitmask: TCCR2A.COM2A \ Compare Match Output A Mode
+ $30 constant TCCR2A_COM2B \ Compare Match Output B Mode
+ b0 $30 bitmask: TCCR2A.COM2B \ Compare Match Output B Mode
+ $c constant TCCR2A_Res \ Reserved
+ b0 $c bitmask: TCCR2A.Res \ Reserved
+ $3 constant TCCR2A_WGM2 \ Waveform Generation Mode
+ b0 $3 bitmask: TCCR2A.WGM2 \ Waveform Generation Mode
+$b1 constant TCCR2B \ Timer/Counter2 Control Registe
+ $80 constant TCCR2B_FOC2A \ Force Output Compare A
+ b1 $80 bitmask: TCCR2B.FOC2A \ Force Output Compare A
+ $40 constant TCCR2B_FOC2B \ Force Output Compare B
+ b1 $40 bitmask: TCCR2B.FOC2B \ Force Output Compare B
+ $30 constant TCCR2B_Res \ Reserved
+ b1 $30 bitmask: TCCR2B.Res \ Reserved
+ $8 constant TCCR2B_WGM22 \ Waveform Generation Mode
+ b1 $8 bitmask: TCCR2B.WGM22 \ Waveform Generation Mode
+ $7 constant TCCR2B_CS2 \ Clock Select
+ b1 $7 bitmask: TCCR2B.CS2 \ Clock Select
+$b2 constant TCNT2 \ Timer/Counter2
+$b4 constant OCR2B \ Timer/Counter2 Output Compare
+$b3 constant OCR2A \ Timer/Counter2 Output Compare
+$b6 constant ASSR \ Asynchronous Status Register
+ $80 constant ASSR_EXCLKAMR \ Enable External Clock Input fo
+ b6 $80 bitmask: ASSR.EXCLKAMR \ Enable External Clock Input fo
+ $40 constant ASSR_EXCLK \ Enable External Clock Input
+ b6 $40 bitmask: ASSR.EXCLK \ Enable External Clock Input
+ $20 constant ASSR_AS2 \ Timer/Counter2 Asynchronous Mo
+ b6 $20 bitmask: ASSR.AS2 \ Timer/Counter2 Asynchronous Mo
+ $10 constant ASSR_TCN2UB \ Timer/Counter2 Update Busy
+ b6 $10 bitmask: ASSR.TCN2UB \ Timer/Counter2 Update Busy
+ $8 constant ASSR_OCR2AUB \ Timer/Counter2 Output Compare
+ b6 $8 bitmask: ASSR.OCR2AUB \ Timer/Counter2 Output Compare
+ $4 constant ASSR_OCR2BUB \ Timer/Counter2 Output Compare
+ b6 $4 bitmask: ASSR.OCR2BUB \ Timer/Counter2 Output Compare
+ $2 constant ASSR_TCR2AUB \ Timer/Counter2 Control Registe
+ b6 $2 bitmask: ASSR.TCR2AUB \ Timer/Counter2 Control Registe
+ $1 constant ASSR_TCR2BUB \ Timer/Counter2 Control Registe
+ b6 $1 bitmask: ASSR.TCR2BUB \ Timer/Counter2 Control Registe
+$43 constant GTCCR \ General Timer Counter Control
+ $80 constant GTCCR_TSM \ Timer/Counter Synchronization
+ 43 $80 bitmask: GTCCR.TSM \ Timer/Counter Synchronization
+ $2 constant GTCCR_PSRASY \ Prescaler Reset Timer/Counter2
+ 43 $2 bitmask: GTCCR.PSRASY \ Prescaler Reset Timer/Counter2
diff --git a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/TIMER_COUNTER_3.frt b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/TIMER_COUNTER_3.frt
new file mode 100644
index 0000000..30d6566
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/TIMER_COUNTER_3.frt
@@ -0,0 +1,68 @@
+\ Generated automatically for atmega256rfr2
+\ #require bitnames.frt
+
+\ TIMER_COUNTER_3
+$90 constant TCCR3A \ Timer/Counter3 Control Registe
+ $c0 constant TCCR3A_COM3A \ Compare Output Mode for Channe
+ 90 $c0 bitmask: TCCR3A.COM3A \ Compare Output Mode for Channe
+ $30 constant TCCR3A_COM3B \ Compare Output Mode for Channe
+ 90 $30 bitmask: TCCR3A.COM3B \ Compare Output Mode for Channe
+ $c constant TCCR3A_COM3C \ Compare Output Mode for Channe
+ 90 $c bitmask: TCCR3A.COM3C \ Compare Output Mode for Channe
+ $3 constant TCCR3A_WGM3 \ Waveform Generation Mode
+ 90 $3 bitmask: TCCR3A.WGM3 \ Waveform Generation Mode
+$91 constant TCCR3B \ Timer/Counter3 Control Registe
+ $80 constant TCCR3B_ICNC3 \ Input Capture 3 Noise Cancelle
+ 91 $80 bitmask: TCCR3B.ICNC3 \ Input Capture 3 Noise Cancelle
+ $40 constant TCCR3B_ICES3 \ Input Capture 3 Edge Select
+ 91 $40 bitmask: TCCR3B.ICES3 \ Input Capture 3 Edge Select
+ $20 constant TCCR3B_Res \ Reserved Bit
+ 91 $20 bitmask: TCCR3B.Res \ Reserved Bit
+ $18 constant TCCR3B_WGM3 \ Waveform Generation Mode
+ 91 $18 bitmask: TCCR3B.WGM3 \ Waveform Generation Mode
+ $7 constant TCCR3B_CS3 \ Clock Select
+ 91 $7 bitmask: TCCR3B.CS3 \ Clock Select
+$92 constant TCCR3C \ Timer/Counter3 Control Registe
+ $80 constant TCCR3C_FOC3A \ Force Output Compare for Chann
+ 92 $80 bitmask: TCCR3C.FOC3A \ Force Output Compare for Chann
+ $40 constant TCCR3C_FOC3B \ Force Output Compare for Chann
+ 92 $40 bitmask: TCCR3C.FOC3B \ Force Output Compare for Chann
+ $20 constant TCCR3C_FOC3C \ Force Output Compare for Chann
+ 92 $20 bitmask: TCCR3C.FOC3C \ Force Output Compare for Chann
+ $1f constant TCCR3C_Res \ Reserved
+ 92 $1f bitmask: TCCR3C.Res \ Reserved
+$94 constant TCNT3 \ Timer/Counter3 Bytes
+$98 constant OCR3A \ Timer/Counter3 Output Compare
+$9a constant OCR3B \ Timer/Counter3 Output Compare
+$9c constant OCR3C \ Timer/Counter3 Output Compare
+$96 constant ICR3 \ Timer/Counter3 Input Capture R
+$71 constant TIMSK3 \ Timer/Counter3 Interrupt Mask
+ $c0 constant TIMSK3_Res \ Reserved Bit
+ 71 $c0 bitmask: TIMSK3.Res \ Reserved Bit
+ $20 constant TIMSK3_ICIE3 \ Timer/Counter3 Input Capture I
+ 71 $20 bitmask: TIMSK3.ICIE3 \ Timer/Counter3 Input Capture I
+ $10 constant TIMSK3_Res \ Reserved Bit
+ 71 $10 bitmask: TIMSK3.Res \ Reserved Bit
+ $8 constant TIMSK3_OCIE3C \ Timer/Counter3 Output Compare
+ 71 $8 bitmask: TIMSK3.OCIE3C \ Timer/Counter3 Output Compare
+ $4 constant TIMSK3_OCIE3B \ Timer/Counter3 Output Compare
+ 71 $4 bitmask: TIMSK3.OCIE3B \ Timer/Counter3 Output Compare
+ $2 constant TIMSK3_OCIE3A \ Timer/Counter3 Output Compare
+ 71 $2 bitmask: TIMSK3.OCIE3A \ Timer/Counter3 Output Compare
+ $1 constant TIMSK3_TOIE3 \ Timer/Counter3 Overflow Interr
+ 71 $1 bitmask: TIMSK3.TOIE3 \ Timer/Counter3 Overflow Interr
+$38 constant TIFR3 \ Timer/Counter3 Interrupt Flag
+ $c0 constant TIFR3_Res \ Reserved Bit
+ 38 $c0 bitmask: TIFR3.Res \ Reserved Bit
+ $20 constant TIFR3_ICF3 \ Timer/Counter3 Input Capture F
+ 38 $20 bitmask: TIFR3.ICF3 \ Timer/Counter3 Input Capture F
+ $10 constant TIFR3_Res \ Reserved Bit
+ 38 $10 bitmask: TIFR3.Res \ Reserved Bit
+ $8 constant TIFR3_OCF3C \ Timer/Counter3 Output Compare
+ 38 $8 bitmask: TIFR3.OCF3C \ Timer/Counter3 Output Compare
+ $4 constant TIFR3_OCF3B \ Timer/Counter3 Output Compare
+ 38 $4 bitmask: TIFR3.OCF3B \ Timer/Counter3 Output Compare
+ $2 constant TIFR3_OCF3A \ Timer/Counter3 Output Compare
+ 38 $2 bitmask: TIFR3.OCF3A \ Timer/Counter3 Output Compare
+ $1 constant TIFR3_TOV3 \ Timer/Counter3 Overflow Flag
+ 38 $1 bitmask: TIFR3.TOV3 \ Timer/Counter3 Overflow Flag
diff --git a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/TIMER_COUNTER_4.frt b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/TIMER_COUNTER_4.frt
new file mode 100644
index 0000000..4ed5cb6
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/TIMER_COUNTER_4.frt
@@ -0,0 +1,68 @@
+\ Generated automatically for atmega256rfr2
+\ #require bitnames.frt
+
+\ TIMER_COUNTER_4
+$a0 constant TCCR4A \ Timer/Counter4 Control Registe
+ $c0 constant TCCR4A_COM4A \ Compare Output Mode for Channe
+ a0 $c0 bitmask: TCCR4A.COM4A \ Compare Output Mode for Channe
+ $30 constant TCCR4A_COM4B \ Compare Output Mode for Channe
+ a0 $30 bitmask: TCCR4A.COM4B \ Compare Output Mode for Channe
+ $c constant TCCR4A_COM4C \ Compare Output Mode for Channe
+ a0 $c bitmask: TCCR4A.COM4C \ Compare Output Mode for Channe
+ $3 constant TCCR4A_WGM4 \ Waveform Generation Mode
+ a0 $3 bitmask: TCCR4A.WGM4 \ Waveform Generation Mode
+$a1 constant TCCR4B \ Timer/Counter4 Control Registe
+ $80 constant TCCR4B_ICNC4 \ Input Capture 4 Noise Cancelle
+ a1 $80 bitmask: TCCR4B.ICNC4 \ Input Capture 4 Noise Cancelle
+ $40 constant TCCR4B_ICES4 \ Input Capture 4 Edge Select
+ a1 $40 bitmask: TCCR4B.ICES4 \ Input Capture 4 Edge Select
+ $20 constant TCCR4B_Res \ Reserved Bit
+ a1 $20 bitmask: TCCR4B.Res \ Reserved Bit
+ $18 constant TCCR4B_WGM4 \ Waveform Generation Mode
+ a1 $18 bitmask: TCCR4B.WGM4 \ Waveform Generation Mode
+ $7 constant TCCR4B_CS4 \ Clock Select
+ a1 $7 bitmask: TCCR4B.CS4 \ Clock Select
+$a2 constant TCCR4C \ Timer/Counter4 Control Registe
+ $80 constant TCCR4C_FOC4A \ Force Output Compare for Chann
+ a2 $80 bitmask: TCCR4C.FOC4A \ Force Output Compare for Chann
+ $40 constant TCCR4C_FOC4B \ Force Output Compare for Chann
+ a2 $40 bitmask: TCCR4C.FOC4B \ Force Output Compare for Chann
+ $20 constant TCCR4C_FOC4C \ Force Output Compare for Chann
+ a2 $20 bitmask: TCCR4C.FOC4C \ Force Output Compare for Chann
+ $1f constant TCCR4C_Res \ Reserved
+ a2 $1f bitmask: TCCR4C.Res \ Reserved
+$a4 constant TCNT4 \ Timer/Counter4 Bytes
+$a8 constant OCR4A \ Timer/Counter4 Output Compare
+$aa constant OCR4B \ Timer/Counter4 Output Compare
+$ac constant OCR4C \ Timer/Counter4 Output Compare
+$a6 constant ICR4 \ Timer/Counter4 Input Capture R
+$72 constant TIMSK4 \ Timer/Counter4 Interrupt Mask
+ $c0 constant TIMSK4_Res \ Reserved Bit
+ 72 $c0 bitmask: TIMSK4.Res \ Reserved Bit
+ $20 constant TIMSK4_ICIE4 \ Timer/Counter4 Input Capture I
+ 72 $20 bitmask: TIMSK4.ICIE4 \ Timer/Counter4 Input Capture I
+ $10 constant TIMSK4_Res \ Reserved Bit
+ 72 $10 bitmask: TIMSK4.Res \ Reserved Bit
+ $8 constant TIMSK4_OCIE4C \ Timer/Counter4 Output Compare
+ 72 $8 bitmask: TIMSK4.OCIE4C \ Timer/Counter4 Output Compare
+ $4 constant TIMSK4_OCIE4B \ Timer/Counter4 Output Compare
+ 72 $4 bitmask: TIMSK4.OCIE4B \ Timer/Counter4 Output Compare
+ $2 constant TIMSK4_OCIE4A \ Timer/Counter4 Output Compare
+ 72 $2 bitmask: TIMSK4.OCIE4A \ Timer/Counter4 Output Compare
+ $1 constant TIMSK4_TOIE4 \ Timer/Counter4 Overflow Interr
+ 72 $1 bitmask: TIMSK4.TOIE4 \ Timer/Counter4 Overflow Interr
+$39 constant TIFR4 \ Timer/Counter4 Interrupt Flag
+ $c0 constant TIFR4_Res \ Reserved Bit
+ 39 $c0 bitmask: TIFR4.Res \ Reserved Bit
+ $20 constant TIFR4_ICF4 \ Timer/Counter4 Input Capture F
+ 39 $20 bitmask: TIFR4.ICF4 \ Timer/Counter4 Input Capture F
+ $10 constant TIFR4_Res \ Reserved Bit
+ 39 $10 bitmask: TIFR4.Res \ Reserved Bit
+ $8 constant TIFR4_OCF4C \ Timer/Counter4 Output Compare
+ 39 $8 bitmask: TIFR4.OCF4C \ Timer/Counter4 Output Compare
+ $4 constant TIFR4_OCF4B \ Timer/Counter4 Output Compare
+ 39 $4 bitmask: TIFR4.OCF4B \ Timer/Counter4 Output Compare
+ $2 constant TIFR4_OCF4A \ Timer/Counter4 Output Compare
+ 39 $2 bitmask: TIFR4.OCF4A \ Timer/Counter4 Output Compare
+ $1 constant TIFR4_TOV4 \ Timer/Counter4 Overflow Flag
+ 39 $1 bitmask: TIFR4.TOV4 \ Timer/Counter4 Overflow Flag
diff --git a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/TIMER_COUNTER_5.frt b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/TIMER_COUNTER_5.frt
new file mode 100644
index 0000000..434ee3b
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/TIMER_COUNTER_5.frt
@@ -0,0 +1,68 @@
+\ Generated automatically for atmega256rfr2
+\ #require bitnames.frt
+
+\ TIMER_COUNTER_5
+$120 constant TCCR5A \ Timer/Counter5 Control Registe
+ $c0 constant TCCR5A_COM5A \ Compare Output Mode for Channe
+ 120 $c0 bitmask: TCCR5A.COM5A \ Compare Output Mode for Channe
+ $30 constant TCCR5A_COM5B \ Compare Output Mode for Channe
+ 120 $30 bitmask: TCCR5A.COM5B \ Compare Output Mode for Channe
+ $c constant TCCR5A_COM5C \ Compare Output Mode for Channe
+ 120 $c bitmask: TCCR5A.COM5C \ Compare Output Mode for Channe
+ $3 constant TCCR5A_WGM5 \ Waveform Generation Mode
+ 120 $3 bitmask: TCCR5A.WGM5 \ Waveform Generation Mode
+$121 constant TCCR5B \ Timer/Counter5 Control Registe
+ $80 constant TCCR5B_ICNC5 \ Input Capture 5 Noise Cancelle
+ 121 $80 bitmask: TCCR5B.ICNC5 \ Input Capture 5 Noise Cancelle
+ $40 constant TCCR5B_ICES5 \ Input Capture 5 Edge Select
+ 121 $40 bitmask: TCCR5B.ICES5 \ Input Capture 5 Edge Select
+ $20 constant TCCR5B_Res \ Reserved Bit
+ 121 $20 bitmask: TCCR5B.Res \ Reserved Bit
+ $18 constant TCCR5B_WGM5 \ Waveform Generation Mode
+ 121 $18 bitmask: TCCR5B.WGM5 \ Waveform Generation Mode
+ $7 constant TCCR5B_CS5 \ Clock Select
+ 121 $7 bitmask: TCCR5B.CS5 \ Clock Select
+$122 constant TCCR5C \ Timer/Counter5 Control Registe
+ $80 constant TCCR5C_FOC5A \ Force Output Compare for Chann
+ 122 $80 bitmask: TCCR5C.FOC5A \ Force Output Compare for Chann
+ $40 constant TCCR5C_FOC5B \ Force Output Compare for Chann
+ 122 $40 bitmask: TCCR5C.FOC5B \ Force Output Compare for Chann
+ $20 constant TCCR5C_FOC5C \ Force Output Compare for Chann
+ 122 $20 bitmask: TCCR5C.FOC5C \ Force Output Compare for Chann
+ $1f constant TCCR5C_Res \ Reserved
+ 122 $1f bitmask: TCCR5C.Res \ Reserved
+$124 constant TCNT5 \ Timer/Counter5 Bytes
+$128 constant OCR5A \ Timer/Counter5 Output Compare
+$12a constant OCR5B \ Timer/Counter5 Output Compare
+$12c constant OCR5C \ Timer/Counter5 Output Compare
+$126 constant ICR5 \ Timer/Counter5 Input Capture R
+$73 constant TIMSK5 \ Timer/Counter5 Interrupt Mask
+ $c0 constant TIMSK5_Res \ Reserved Bit
+ 73 $c0 bitmask: TIMSK5.Res \ Reserved Bit
+ $20 constant TIMSK5_ICIE5 \ Timer/Counter5 Input Capture I
+ 73 $20 bitmask: TIMSK5.ICIE5 \ Timer/Counter5 Input Capture I
+ $10 constant TIMSK5_Res \ Reserved Bit
+ 73 $10 bitmask: TIMSK5.Res \ Reserved Bit
+ $8 constant TIMSK5_OCIE5C \ Timer/Counter5 Output Compare
+ 73 $8 bitmask: TIMSK5.OCIE5C \ Timer/Counter5 Output Compare
+ $4 constant TIMSK5_OCIE5B \ Timer/Counter5 Output Compare
+ 73 $4 bitmask: TIMSK5.OCIE5B \ Timer/Counter5 Output Compare
+ $2 constant TIMSK5_OCIE5A \ Timer/Counter5 Output Compare
+ 73 $2 bitmask: TIMSK5.OCIE5A \ Timer/Counter5 Output Compare
+ $1 constant TIMSK5_TOIE5 \ Timer/Counter5 Overflow Interr
+ 73 $1 bitmask: TIMSK5.TOIE5 \ Timer/Counter5 Overflow Interr
+$3a constant TIFR5 \ Timer/Counter5 Interrupt Flag
+ $c0 constant TIFR5_Res \ Reserved Bit
+ 3a $c0 bitmask: TIFR5.Res \ Reserved Bit
+ $20 constant TIFR5_ICF5 \ Timer/Counter5 Input Capture F
+ 3a $20 bitmask: TIFR5.ICF5 \ Timer/Counter5 Input Capture F
+ $10 constant TIFR5_Res \ Reserved Bit
+ 3a $10 bitmask: TIFR5.Res \ Reserved Bit
+ $8 constant TIFR5_OCF5C \ Timer/Counter5 Output Compare
+ 3a $8 bitmask: TIFR5.OCF5C \ Timer/Counter5 Output Compare
+ $4 constant TIFR5_OCF5B \ Timer/Counter5 Output Compare
+ 3a $4 bitmask: TIFR5.OCF5B \ Timer/Counter5 Output Compare
+ $2 constant TIFR5_OCF5A \ Timer/Counter5 Output Compare
+ 3a $2 bitmask: TIFR5.OCF5A \ Timer/Counter5 Output Compare
+ $1 constant TIFR5_TOV5 \ Timer/Counter5 Overflow Flag
+ 3a $1 bitmask: TIFR5.TOV5 \ Timer/Counter5 Overflow Flag
diff --git a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/TRX24.frt b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/TRX24.frt
new file mode 100644
index 0000000..d8c6290
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/TRX24.frt
@@ -0,0 +1,495 @@
+\ Generated automatically for atmega256rfr2
+\ #require bitnames.frt
+
+\ TRX24
+$138 constant PARCR \ Power Amplifier Ramp up/down C
+ $e0 constant PARCR_PALTD \ ext. PA Ramp Down Lead Time
+ 138 $e0 bitmask: PARCR.PALTD \ ext. PA Ramp Down Lead Time
+ $1c constant PARCR_PALTU \ ext. PA Ramp Up Lead Time
+ 138 $1c bitmask: PARCR.PALTU \ ext. PA Ramp Up Lead Time
+ $2 constant PARCR_PARDFI \ Power Amplifier Ramp Down Freq
+ 138 $2 bitmask: PARCR.PARDFI \ Power Amplifier Ramp Down Freq
+ $1 constant PARCR_PARUFI \ Power Amplifier Ramp Up Freque
+ 138 $1 bitmask: PARCR.PARUFI \ Power Amplifier Ramp Up Freque
+$10e constant MAFSA0L \ Transceiver MAC Short Address
+ $ff constant MAFSA0L_MAFSA0L \ MAC Short Address low Byte for
+ 10e $ff bitmask: MAFSA0L.MAFSA0L \ MAC Short Address low Byte for
+$10f constant MAFSA0H \ Transceiver MAC Short Address
+ $ff constant MAFSA0H_MAFSA0H \ MAC Short Address high Byte fo
+ 10f $ff bitmask: MAFSA0H.MAFSA0H \ MAC Short Address high Byte fo
+$110 constant MAFPA0L \ Transceiver Personal Area Netw
+ $ff constant MAFPA0L_MAFPA0L \ MAC Personal Area Network ID l
+ 110 $ff bitmask: MAFPA0L.MAFPA0L \ MAC Personal Area Network ID l
+$111 constant MAFPA0H \ Transceiver Personal Area Netw
+ $ff constant MAFPA0H_MAFPA0H \ MAC Personal Area Network ID h
+ 111 $ff bitmask: MAFPA0H.MAFPA0H \ MAC Personal Area Network ID h
+$112 constant MAFSA1L \ Transceiver MAC Short Address
+ $ff constant MAFSA1L_MAFSA1L \ MAC Short Address low Byte for
+ 112 $ff bitmask: MAFSA1L.MAFSA1L \ MAC Short Address low Byte for
+$113 constant MAFSA1H \ Transceiver MAC Short Address
+ $ff constant MAFSA1H_MAFSA1H \ MAC Short Address high Byte fo
+ 113 $ff bitmask: MAFSA1H.MAFSA1H \ MAC Short Address high Byte fo
+$114 constant MAFPA1L \ Transceiver Personal Area Netw
+ $ff constant MAFPA1L_MAFPA1L \ MAC Personal Area Network ID l
+ 114 $ff bitmask: MAFPA1L.MAFPA1L \ MAC Personal Area Network ID l
+$115 constant MAFPA1H \ Transceiver Personal Area Netw
+ $ff constant MAFPA1H_MAFPA1H \ MAC Personal Area Network ID h
+ 115 $ff bitmask: MAFPA1H.MAFPA1H \ MAC Personal Area Network ID h
+$116 constant MAFSA2L \ Transceiver MAC Short Address
+ $ff constant MAFSA2L_MAFSA2L \ MAC Short Address low Byte for
+ 116 $ff bitmask: MAFSA2L.MAFSA2L \ MAC Short Address low Byte for
+$117 constant MAFSA2H \ Transceiver MAC Short Address
+ $ff constant MAFSA2H_MAFSA2H \ MAC Short Address high Byte fo
+ 117 $ff bitmask: MAFSA2H.MAFSA2H \ MAC Short Address high Byte fo
+$118 constant MAFPA2L \ Transceiver Personal Area Netw
+ $ff constant MAFPA2L_MAFPA2L \ MAC Personal Area Network ID l
+ 118 $ff bitmask: MAFPA2L.MAFPA2L \ MAC Personal Area Network ID l
+$119 constant MAFPA2H \ Transceiver Personal Area Netw
+ $ff constant MAFPA2H_MAFPA2H \ MAC Personal Area Network ID h
+ 119 $ff bitmask: MAFPA2H.MAFPA2H \ MAC Personal Area Network ID h
+$11a constant MAFSA3L \ Transceiver MAC Short Address
+ $ff constant MAFSA3L_MAFSA3L \ MAC Short Address low Byte for
+ 11a $ff bitmask: MAFSA3L.MAFSA3L \ MAC Short Address low Byte for
+$11b constant MAFSA3H \ Transceiver MAC Short Address
+ $ff constant MAFSA3H_MAFSA3H \ MAC Short Address high Byte fo
+ 11b $ff bitmask: MAFSA3H.MAFSA3H \ MAC Short Address high Byte fo
+$11c constant MAFPA3L \ Transceiver Personal Area Netw
+ $ff constant MAFPA3L_MAFPA3L \ MAC Personal Area Network ID l
+ 11c $ff bitmask: MAFPA3L.MAFPA3L \ MAC Personal Area Network ID l
+$11d constant MAFPA3H \ Transceiver Personal Area Netw
+ $ff constant MAFPA3H_MAFPA3H \ MAC Personal Area Network ID h
+ 11d $ff bitmask: MAFPA3H.MAFPA3H \ MAC Personal Area Network ID h
+$10c constant MAFCR0 \ Multiple Address Filter Config
+ $f0 constant MAFCR0_Res \ Reserved Bit
+ 10c $f0 bitmask: MAFCR0.Res \ Reserved Bit
+ $8 constant MAFCR0_MAF3EN \ Multiple Address Filter 3 Enab
+ 10c $8 bitmask: MAFCR0.MAF3EN \ Multiple Address Filter 3 Enab
+ $4 constant MAFCR0_MAF2EN \ Multiple Address Filter 2 Enab
+ 10c $4 bitmask: MAFCR0.MAF2EN \ Multiple Address Filter 2 Enab
+ $2 constant MAFCR0_MAF1EN \ Multiple Address Filter 1 Enab
+ 10c $2 bitmask: MAFCR0.MAF1EN \ Multiple Address Filter 1 Enab
+ $1 constant MAFCR0_MAF0EN \ Multiple Address Filter 0 Enab
+ 10c $1 bitmask: MAFCR0.MAF0EN \ Multiple Address Filter 0 Enab
+$10d constant MAFCR1 \ Multiple Address Filter Config
+ $80 constant MAFCR1_AACK_3_SET_PD \ Set Data Pending bit for addre
+ 10d $80 bitmask: MAFCR1.AACK_3_SET_PD \ Set Data Pending bit for addre
+ $40 constant MAFCR1_AACK_3_I_AM_COORD \ Enable PAN Coordinator mode fo
+ 10d $40 bitmask: MAFCR1.AACK_3_I_AM_COORD \ Enable PAN Coordinator mode fo
+ $20 constant MAFCR1_AACK_2_SET_PD \ Set Data Pending bit for addre
+ 10d $20 bitmask: MAFCR1.AACK_2_SET_PD \ Set Data Pending bit for addre
+ $10 constant MAFCR1_AACK_2_I_AM_COORD \ Enable PAN Coordinator mode fo
+ 10d $10 bitmask: MAFCR1.AACK_2_I_AM_COORD \ Enable PAN Coordinator mode fo
+ $8 constant MAFCR1_AACK_1_SET_PD \ Set Data Pending bit for addre
+ 10d $8 bitmask: MAFCR1.AACK_1_SET_PD \ Set Data Pending bit for addre
+ $4 constant MAFCR1_AACK_1_I_AM_COORD \ Enable PAN Coordinator mode fo
+ 10d $4 bitmask: MAFCR1.AACK_1_I_AM_COORD \ Enable PAN Coordinator mode fo
+ $2 constant MAFCR1_AACK_0_SET_PD \ Set Data Pending bit for addre
+ 10d $2 bitmask: MAFCR1.AACK_0_SET_PD \ Set Data Pending bit for addre
+ $1 constant MAFCR1_AACK_0_I_AM_COORD \ Enable PAN Coordinator mode fo
+ 10d $1 bitmask: MAFCR1.AACK_0_I_AM_COORD \ Enable PAN Coordinator mode fo
+$13c constant AES_CTRL \ AES Control Register
+ $80 constant AES_CTRL_AES_REQUEST \ Request AES Operation.
+ 13c $80 bitmask: AES_CTRL.AES_REQUEST \ Request AES Operation.
+ $40 constant AES_CTRL_Res \ Reserved Bit
+ 13c $40 bitmask: AES_CTRL.Res \ Reserved Bit
+ $20 constant AES_CTRL_AES_MODE \ Set AES Operation Mode
+ 13c $20 bitmask: AES_CTRL.AES_MODE \ Set AES Operation Mode
+ $10 constant AES_CTRL_Res \ Reserved Bit
+ 13c $10 bitmask: AES_CTRL.Res \ Reserved Bit
+ $8 constant AES_CTRL_AES_DIR \ Set AES Operation Direction
+ 13c $8 bitmask: AES_CTRL.AES_DIR \ Set AES Operation Direction
+ $4 constant AES_CTRL_AES_IM \ AES Interrupt Enable
+ 13c $4 bitmask: AES_CTRL.AES_IM \ AES Interrupt Enable
+ $3 constant AES_CTRL_Res \ Reserved Bit
+ 13c $3 bitmask: AES_CTRL.Res \ Reserved Bit
+$13d constant AES_STATUS \ AES Status Register
+ $80 constant AES_STATUS_AES_ER \ AES Operation Finished with Er
+ 13d $80 bitmask: AES_STATUS.AES_ER \ AES Operation Finished with Er
+ $7e constant AES_STATUS_Res \ Reserved
+ 13d $7e bitmask: AES_STATUS.Res \ Reserved
+ $1 constant AES_STATUS_AES_DONE \ AES Operation Finished with Su
+ 13d $1 bitmask: AES_STATUS.AES_DONE \ AES Operation Finished with Su
+$13e constant AES_STATE \ AES Plain and Cipher Text Buff
+ $ff constant AES_STATE_AES_STATE \ AES Plain and Cipher Text Buff
+ 13e $ff bitmask: AES_STATE.AES_STATE \ AES Plain and Cipher Text Buff
+$13f constant AES_KEY \ AES Encryption and Decryption
+ $ff constant AES_KEY_AES_KEY \ AES Encryption/Decryption Key
+ 13f $ff bitmask: AES_KEY.AES_KEY \ AES Encryption/Decryption Key
+$141 constant TRX_STATUS \ Transceiver Status Register
+ $80 constant TRX_STATUS_CCA_DONE \ CCA Algorithm Status
+ 141 $80 bitmask: TRX_STATUS.CCA_DONE \ CCA Algorithm Status
+ $40 constant TRX_STATUS_CCA_STATUS \ CCA Status Result
+ 141 $40 bitmask: TRX_STATUS.CCA_STATUS \ CCA Status Result
+ $20 constant TRX_STATUS_TST_STATUS \ Test mode status
+ 141 $20 bitmask: TRX_STATUS.TST_STATUS \ Test mode status
+ $1f constant TRX_STATUS_TRX_STATUS \ Transceiver Main Status
+ 141 $1f bitmask: TRX_STATUS.TRX_STATUS \ Transceiver Main Status
+$142 constant TRX_STATE \ Transceiver State Control Regi
+ $e0 constant TRX_STATE_TRAC_STATUS \ Transaction Status
+ 142 $e0 bitmask: TRX_STATE.TRAC_STATUS \ Transaction Status
+ $1f constant TRX_STATE_TRX_CMD \ State Control Command
+ 142 $1f bitmask: TRX_STATE.TRX_CMD \ State Control Command
+$143 constant TRX_CTRL_0 \ Reserved
+ $80 constant TRX_CTRL_0_Res7 \ Reserved
+ 143 $80 bitmask: TRX_CTRL_0.Res7 \ Reserved
+ $40 constant TRX_CTRL_0_PMU_EN \ Enable Phase Measurement Unit
+ 143 $40 bitmask: TRX_CTRL_0.PMU_EN \ Enable Phase Measurement Unit
+ $20 constant TRX_CTRL_0_PMU_START \ Start of Phase Measurement Uni
+ 143 $20 bitmask: TRX_CTRL_0.PMU_START \ Start of Phase Measurement Uni
+ $10 constant TRX_CTRL_0_PMU_IF_INV \ PMU IF Inverse
+ 143 $10 bitmask: TRX_CTRL_0.PMU_IF_INV \ PMU IF Inverse
+ $f constant TRX_CTRL_0_Res \ Reserved
+ 143 $f bitmask: TRX_CTRL_0.Res \ Reserved
+$144 constant TRX_CTRL_1 \ Transceiver Control Register 1
+ $80 constant TRX_CTRL_1_PA_EXT_EN \ External PA support enable
+ 144 $80 bitmask: TRX_CTRL_1.PA_EXT_EN \ External PA support enable
+ $40 constant TRX_CTRL_1_IRQ_2_EXT_EN \ Connect Frame Start IRQ to TC1
+ 144 $40 bitmask: TRX_CTRL_1.IRQ_2_EXT_EN \ Connect Frame Start IRQ to TC1
+ $20 constant TRX_CTRL_1_TX_AUTO_CRC_ON \ Enable Automatic CRC Calculati
+ 144 $20 bitmask: TRX_CTRL_1.TX_AUTO_CRC_ON \ Enable Automatic CRC Calculati
+ $10 constant TRX_CTRL_1_PLL_TX_FLT \ Enable PLL TX filter
+ 144 $10 bitmask: TRX_CTRL_1.PLL_TX_FLT \ Enable PLL TX filter
+ $f constant TRX_CTRL_1_Res \ Reserved
+ 144 $f bitmask: TRX_CTRL_1.Res \ Reserved
+$145 constant PHY_TX_PWR \ Transceiver Transmit Power Con
+ $f0 constant PHY_TX_PWR_Res \ Reserved
+ 145 $f0 bitmask: PHY_TX_PWR.Res \ Reserved
+ $f constant PHY_TX_PWR_TX_PWR \ Transmit Power Setting
+ 145 $f bitmask: PHY_TX_PWR.TX_PWR \ Transmit Power Setting
+$146 constant PHY_RSSI \ Receiver Signal Strength Indic
+ $80 constant PHY_RSSI_RX_CRC_VALID \ Received Frame CRC Status
+ 146 $80 bitmask: PHY_RSSI.RX_CRC_VALID \ Received Frame CRC Status
+ $60 constant PHY_RSSI_RND_VALUE \ Random Value
+ 146 $60 bitmask: PHY_RSSI.RND_VALUE \ Random Value
+ $1f constant PHY_RSSI_RSSI \ Receiver Signal Strength Indic
+ 146 $1f bitmask: PHY_RSSI.RSSI \ Receiver Signal Strength Indic
+$147 constant PHY_ED_LEVEL \ Transceiver Energy Detection L
+ $ff constant PHY_ED_LEVEL_ED_LEVEL \ Energy Detection Level
+ 147 $ff bitmask: PHY_ED_LEVEL.ED_LEVEL \ Energy Detection Level
+$148 constant PHY_CC_CCA \ Transceiver Clear Channel Asse
+ $80 constant PHY_CC_CCA_CCA_REQUEST \ Manual CCA Measurement Request
+ 148 $80 bitmask: PHY_CC_CCA.CCA_REQUEST \ Manual CCA Measurement Request
+ $60 constant PHY_CC_CCA_CCA_MODE \ Select CCA Measurement Mode
+ 148 $60 bitmask: PHY_CC_CCA.CCA_MODE \ Select CCA Measurement Mode
+ $1f constant PHY_CC_CCA_CHANNEL \ RX/TX Channel Selection
+ 148 $1f bitmask: PHY_CC_CCA.CHANNEL \ RX/TX Channel Selection
+$149 constant CCA_THRES \ Transceiver CCA Threshold Sett
+ $f0 constant CCA_THRES_CCA_CS_THRES \ CS Threshold Level for CCA Mea
+ 149 $f0 bitmask: CCA_THRES.CCA_CS_THRES \ CS Threshold Level for CCA Mea
+ $f constant CCA_THRES_CCA_ED_THRES \ ED Threshold Level for CCA Mea
+ 149 $f bitmask: CCA_THRES.CCA_ED_THRES \ ED Threshold Level for CCA Mea
+$14a constant RX_CTRL \ Transceiver Receive Control Re
+ $f constant RX_CTRL_PDT_THRES \ Receiver Sensitivity Control
+ 14a $f bitmask: RX_CTRL.PDT_THRES \ Receiver Sensitivity Control
+$14b constant SFD_VALUE \ Start of Frame Delimiter Value
+ $ff constant SFD_VALUE_SFD_VALUE \ Start of Frame Delimiter Value
+ 14b $ff bitmask: SFD_VALUE.SFD_VALUE \ Start of Frame Delimiter Value
+$14c constant TRX_CTRL_2 \ Transceiver Control Register 2
+ $80 constant TRX_CTRL_2_RX_SAFE_MODE \ RX Safe Mode
+ 14c $80 bitmask: TRX_CTRL_2.RX_SAFE_MODE \ RX Safe Mode
+ $7c constant TRX_CTRL_2_Res \ Reserved
+ 14c $7c bitmask: TRX_CTRL_2.Res \ Reserved
+ $3 constant TRX_CTRL_2_OQPSK_DATA_RATE \ Data Rate Selection
+ 14c $3 bitmask: TRX_CTRL_2.OQPSK_DATA_RATE \ Data Rate Selection
+$14d constant ANT_DIV \ Antenna Diversity Control Regi
+ $80 constant ANT_DIV_ANT_SEL \ Antenna Diversity Antenna Stat
+ 14d $80 bitmask: ANT_DIV.ANT_SEL \ Antenna Diversity Antenna Stat
+ $70 constant ANT_DIV_Res \ Reserved
+ 14d $70 bitmask: ANT_DIV.Res \ Reserved
+ $8 constant ANT_DIV_ANT_DIV_EN \ Enable Antenna Diversity
+ 14d $8 bitmask: ANT_DIV.ANT_DIV_EN \ Enable Antenna Diversity
+ $4 constant ANT_DIV_ANT_EXT_SW_EN \ Enable External Antenna Switch
+ 14d $4 bitmask: ANT_DIV.ANT_EXT_SW_EN \ Enable External Antenna Switch
+ $3 constant ANT_DIV_ANT_CTRL \ Static Antenna Diversity Switc
+ 14d $3 bitmask: ANT_DIV.ANT_CTRL \ Static Antenna Diversity Switc
+$14e constant IRQ_MASK \ Transceiver Interrupt Enable R
+ $80 constant IRQ_MASK_AWAKE_EN \ Awake Interrupt Enable
+ 14e $80 bitmask: IRQ_MASK.AWAKE_EN \ Awake Interrupt Enable
+ $40 constant IRQ_MASK_TX_END_EN \ TX_END Interrupt Enable
+ 14e $40 bitmask: IRQ_MASK.TX_END_EN \ TX_END Interrupt Enable
+ $20 constant IRQ_MASK_AMI_EN \ Address Match Interrupt Enable
+ 14e $20 bitmask: IRQ_MASK.AMI_EN \ Address Match Interrupt Enable
+ $10 constant IRQ_MASK_CCA_ED_DONE_EN \ End of ED Measurement Interrup
+ 14e $10 bitmask: IRQ_MASK.CCA_ED_DONE_EN \ End of ED Measurement Interrup
+ $8 constant IRQ_MASK_RX_END_EN \ RX_END Interrupt Enable
+ 14e $8 bitmask: IRQ_MASK.RX_END_EN \ RX_END Interrupt Enable
+ $4 constant IRQ_MASK_RX_START_EN \ RX_START Interrupt Enable
+ 14e $4 bitmask: IRQ_MASK.RX_START_EN \ RX_START Interrupt Enable
+ $2 constant IRQ_MASK_PLL_UNLOCK_EN \ PLL Unlock Interrupt Enable
+ 14e $2 bitmask: IRQ_MASK.PLL_UNLOCK_EN \ PLL Unlock Interrupt Enable
+ $1 constant IRQ_MASK_PLL_LOCK_EN \ PLL Lock Interrupt Enable
+ 14e $1 bitmask: IRQ_MASK.PLL_LOCK_EN \ PLL Lock Interrupt Enable
+$14f constant IRQ_STATUS \ Transceiver Interrupt Status R
+ $80 constant IRQ_STATUS_AWAKE \ Awake Interrupt Status
+ 14f $80 bitmask: IRQ_STATUS.AWAKE \ Awake Interrupt Status
+ $40 constant IRQ_STATUS_TX_END \ TX_END Interrupt Status
+ 14f $40 bitmask: IRQ_STATUS.TX_END \ TX_END Interrupt Status
+ $20 constant IRQ_STATUS_AMI \ Address Match Interrupt Status
+ 14f $20 bitmask: IRQ_STATUS.AMI \ Address Match Interrupt Status
+ $10 constant IRQ_STATUS_CCA_ED_DONE \ End of ED Measurement Interrup
+ 14f $10 bitmask: IRQ_STATUS.CCA_ED_DONE \ End of ED Measurement Interrup
+ $8 constant IRQ_STATUS_RX_END \ RX_END Interrupt Status
+ 14f $8 bitmask: IRQ_STATUS.RX_END \ RX_END Interrupt Status
+ $4 constant IRQ_STATUS_RX_START \ RX_START Interrupt Status
+ 14f $4 bitmask: IRQ_STATUS.RX_START \ RX_START Interrupt Status
+ $2 constant IRQ_STATUS_PLL_UNLOCK \ PLL Unlock Interrupt Status
+ 14f $2 bitmask: IRQ_STATUS.PLL_UNLOCK \ PLL Unlock Interrupt Status
+ $1 constant IRQ_STATUS_PLL_LOCK \ PLL Lock Interrupt Status
+ 14f $1 bitmask: IRQ_STATUS.PLL_LOCK \ PLL Lock Interrupt Status
+$be constant IRQ_MASK1 \ Transceiver Interrupt Enable R
+ $e0 constant IRQ_MASK1_Res \ Reserved Bit
+ be $e0 bitmask: IRQ_MASK1.Res \ Reserved Bit
+ $10 constant IRQ_MASK1_MAF_3_AMI_EN \ Address Match Interrupt enable
+ be $10 bitmask: IRQ_MASK1.MAF_3_AMI_EN \ Address Match Interrupt enable
+ $8 constant IRQ_MASK1_MAF_2_AMI_EN \ Address Match Interrupt enable
+ be $8 bitmask: IRQ_MASK1.MAF_2_AMI_EN \ Address Match Interrupt enable
+ $4 constant IRQ_MASK1_MAF_1_AMI_EN \ Address Match Interrupt enable
+ be $4 bitmask: IRQ_MASK1.MAF_1_AMI_EN \ Address Match Interrupt enable
+ $2 constant IRQ_MASK1_MAF_0_AMI_EN \ Address Match Interrupt enable
+ be $2 bitmask: IRQ_MASK1.MAF_0_AMI_EN \ Address Match Interrupt enable
+ $1 constant IRQ_MASK1_TX_START_EN \ Transmit Start Interrupt enabl
+ be $1 bitmask: IRQ_MASK1.TX_START_EN \ Transmit Start Interrupt enabl
+$bf constant IRQ_STATUS1 \ Transceiver Interrupt Status R
+ $e0 constant IRQ_STATUS1_Res \ Reserved Bit
+ bf $e0 bitmask: IRQ_STATUS1.Res \ Reserved Bit
+ $10 constant IRQ_STATUS1_MAF_3_AMI \ Address Match Interrupt Status
+ bf $10 bitmask: IRQ_STATUS1.MAF_3_AMI \ Address Match Interrupt Status
+ $8 constant IRQ_STATUS1_MAF_2_AMI \ Address Match Interrupt Status
+ bf $8 bitmask: IRQ_STATUS1.MAF_2_AMI \ Address Match Interrupt Status
+ $4 constant IRQ_STATUS1_MAF_1_AMI \ Address Match Interrupt Status
+ bf $4 bitmask: IRQ_STATUS1.MAF_1_AMI \ Address Match Interrupt Status
+ $2 constant IRQ_STATUS1_MAF_0_AMI \ Address Match Interrupt Status
+ bf $2 bitmask: IRQ_STATUS1.MAF_0_AMI \ Address Match Interrupt Status
+ $1 constant IRQ_STATUS1_TX_START \ Transmit Start Interrupt Statu
+ bf $1 bitmask: IRQ_STATUS1.TX_START \ Transmit Start Interrupt Statu
+$150 constant VREG_CTRL \ Voltage Regulator Control and
+ $80 constant VREG_CTRL_AVREG_EXT \ Use External AVDD Regulator
+ 150 $80 bitmask: VREG_CTRL.AVREG_EXT \ Use External AVDD Regulator
+ $40 constant VREG_CTRL_AVDD_OK \ AVDD Supply Voltage Valid
+ 150 $40 bitmask: VREG_CTRL.AVDD_OK \ AVDD Supply Voltage Valid
+ $8 constant VREG_CTRL_DVREG_EXT \ Use External DVDD Regulator
+ 150 $8 bitmask: VREG_CTRL.DVREG_EXT \ Use External DVDD Regulator
+ $4 constant VREG_CTRL_DVDD_OK \ DVDD Supply Voltage Valid
+ 150 $4 bitmask: VREG_CTRL.DVDD_OK \ DVDD Supply Voltage Valid
+$151 constant BATMON \ Battery Monitor Control and St
+ $80 constant BATMON_BAT_LOW \ Battery Monitor Interrupt Stat
+ 151 $80 bitmask: BATMON.BAT_LOW \ Battery Monitor Interrupt Stat
+ $40 constant BATMON_BAT_LOW_EN \ Battery Monitor Interrupt Enab
+ 151 $40 bitmask: BATMON.BAT_LOW_EN \ Battery Monitor Interrupt Enab
+ $20 constant BATMON_BATMON_OK \ Battery Monitor Status
+ 151 $20 bitmask: BATMON.BATMON_OK \ Battery Monitor Status
+ $10 constant BATMON_BATMON_HR \ Battery Monitor Voltage Range
+ 151 $10 bitmask: BATMON.BATMON_HR \ Battery Monitor Voltage Range
+ $f constant BATMON_BATMON_VTH \ Battery Monitor Threshold Volt
+ 151 $f bitmask: BATMON.BATMON_VTH \ Battery Monitor Threshold Volt
+$152 constant XOSC_CTRL \ Crystal Oscillator Control Reg
+ $f0 constant XOSC_CTRL_XTAL_MODE \ Crystal Oscillator Operating M
+ 152 $f0 bitmask: XOSC_CTRL.XTAL_MODE \ Crystal Oscillator Operating M
+ $f constant XOSC_CTRL_XTAL_TRIM \ Crystal Oscillator Load Capaci
+ 152 $f bitmask: XOSC_CTRL.XTAL_TRIM \ Crystal Oscillator Load Capaci
+$153 constant CC_CTRL_0 \ Channel Control Register 0
+ $ff constant CC_CTRL_0_CC_NUMBER \ Channel Number
+ 153 $ff bitmask: CC_CTRL_0.CC_NUMBER \ Channel Number
+$154 constant CC_CTRL_1 \ Channel Control Register 1
+ $f constant CC_CTRL_1_CC_BAND \ Channel Band
+ 154 $f bitmask: CC_CTRL_1.CC_BAND \ Channel Band
+$155 constant RX_SYN \ Transceiver Receiver Sensitivi
+ $80 constant RX_SYN_RX_PDT_DIS \ Prevent Frame Reception
+ 155 $80 bitmask: RX_SYN.RX_PDT_DIS \ Prevent Frame Reception
+ $40 constant RX_SYN_RX_OVERRIDE \ Receiver Override Function
+ 155 $40 bitmask: RX_SYN.RX_OVERRIDE \ Receiver Override Function
+ $30 constant RX_SYN_Res \ Reserved
+ 155 $30 bitmask: RX_SYN.Res \ Reserved
+ $f constant RX_SYN_RX_PDT_LEVEL \ Reduce Receiver Sensitivity
+ 155 $f bitmask: RX_SYN.RX_PDT_LEVEL \ Reduce Receiver Sensitivity
+$156 constant TRX_RPC \ Transceiver Reduced Power Cons
+ $c0 constant TRX_RPC_RX_RPC_CTRL \ Smart Receiving Mode Timing
+ 156 $c0 bitmask: TRX_RPC.RX_RPC_CTRL \ Smart Receiving Mode Timing
+ $20 constant TRX_RPC_RX_RPC_EN \ Reciver Smart Receiving Mode E
+ 156 $20 bitmask: TRX_RPC.RX_RPC_EN \ Reciver Smart Receiving Mode E
+ $10 constant TRX_RPC_PDT_RPC_EN \ Smart Receiving Mode Reduced S
+ 156 $10 bitmask: TRX_RPC.PDT_RPC_EN \ Smart Receiving Mode Reduced S
+ $8 constant TRX_RPC_PLL_RPC_EN \ PLL Smart Receiving Mode Enabl
+ 156 $8 bitmask: TRX_RPC.PLL_RPC_EN \ PLL Smart Receiving Mode Enabl
+ $4 constant TRX_RPC_Res0 \ Reserved
+ 156 $4 bitmask: TRX_RPC.Res0 \ Reserved
+ $2 constant TRX_RPC_IPAN_RPC_EN \ Smart Receiving Mode IPAN Hand
+ 156 $2 bitmask: TRX_RPC.IPAN_RPC_EN \ Smart Receiving Mode IPAN Hand
+ $1 constant TRX_RPC_XAH_RPC_EN \ Smart Receiving in Extended Op
+ 156 $1 bitmask: TRX_RPC.XAH_RPC_EN \ Smart Receiving in Extended Op
+$157 constant XAH_CTRL_1 \ Transceiver Acknowledgment Fra
+ $c0 constant XAH_CTRL_1_Res \ Reserved Bit
+ 157 $c0 bitmask: XAH_CTRL_1.Res \ Reserved Bit
+ $20 constant XAH_CTRL_1_AACK_FLTR_RES_FT \ Filter Reserved Frames
+ 157 $20 bitmask: XAH_CTRL_1.AACK_FLTR_RES_FT \ Filter Reserved Frames
+ $10 constant XAH_CTRL_1_AACK_UPLD_RES_FT \ Process Reserved Frames
+ 157 $10 bitmask: XAH_CTRL_1.AACK_UPLD_RES_FT \ Process Reserved Frames
+ $8 constant XAH_CTRL_1_Res \ Reserved Bit
+ 157 $8 bitmask: XAH_CTRL_1.Res \ Reserved Bit
+ $4 constant XAH_CTRL_1_AACK_ACK_TIME \ Reduce Acknowledgment Time
+ 157 $4 bitmask: XAH_CTRL_1.AACK_ACK_TIME \ Reduce Acknowledgment Time
+ $2 constant XAH_CTRL_1_AACK_PROM_MODE \ Enable Promiscuous Mode
+ 157 $2 bitmask: XAH_CTRL_1.AACK_PROM_MODE \ Enable Promiscuous Mode
+ $1 constant XAH_CTRL_1_Res \ Reserved Bit
+ 157 $1 bitmask: XAH_CTRL_1.Res \ Reserved Bit
+$158 constant FTN_CTRL \ Transceiver Filter Tuning Cont
+ $80 constant FTN_CTRL_FTN_START \ Start Calibration Loop of Filt
+ 158 $80 bitmask: FTN_CTRL.FTN_START \ Start Calibration Loop of Filt
+$15a constant PLL_CF \ Transceiver Center Frequency C
+ $80 constant PLL_CF_PLL_CF_START \ Start Center Frequency Calibra
+ 15a $80 bitmask: PLL_CF.PLL_CF_START \ Start Center Frequency Calibra
+$15b constant PLL_DCU \ Transceiver Delay Cell Calibra
+ $80 constant PLL_DCU_PLL_DCU_START \ Start Delay Cell Calibration
+ 15b $80 bitmask: PLL_DCU.PLL_DCU_START \ Start Delay Cell Calibration
+$15c constant PART_NUM \ Device Identification Register
+ $ff constant PART_NUM_PART_NUM \ Part Number
+ 15c $ff bitmask: PART_NUM.PART_NUM \ Part Number
+$15d constant VERSION_NUM \ Device Identification Register
+ $ff constant VERSION_NUM_VERSION_NUM \ Version Number
+ 15d $ff bitmask: VERSION_NUM.VERSION_NUM \ Version Number
+$15e constant MAN_ID_0 \ Device Identification Register
+ $80 constant MAN_ID_0_MAN_ID_07 \ Manufacturer ID (Low Byte)
+ 15e $80 bitmask: MAN_ID_0.MAN_ID_07 \ Manufacturer ID (Low Byte)
+ $40 constant MAN_ID_0_MAN_ID_06 \ Manufacturer ID (Low Byte)
+ 15e $40 bitmask: MAN_ID_0.MAN_ID_06 \ Manufacturer ID (Low Byte)
+ $20 constant MAN_ID_0_MAN_ID_05 \ Manufacturer ID (Low Byte)
+ 15e $20 bitmask: MAN_ID_0.MAN_ID_05 \ Manufacturer ID (Low Byte)
+ $10 constant MAN_ID_0_MAN_ID_04 \ Manufacturer ID (Low Byte)
+ 15e $10 bitmask: MAN_ID_0.MAN_ID_04 \ Manufacturer ID (Low Byte)
+ $8 constant MAN_ID_0_MAN_ID_03 \ Manufacturer ID (Low Byte)
+ 15e $8 bitmask: MAN_ID_0.MAN_ID_03 \ Manufacturer ID (Low Byte)
+ $4 constant MAN_ID_0_MAN_ID_02 \ Manufacturer ID (Low Byte)
+ 15e $4 bitmask: MAN_ID_0.MAN_ID_02 \ Manufacturer ID (Low Byte)
+ $2 constant MAN_ID_0_MAN_ID_01 \ Manufacturer ID (Low Byte)
+ 15e $2 bitmask: MAN_ID_0.MAN_ID_01 \ Manufacturer ID (Low Byte)
+ $1 constant MAN_ID_0_MAN_ID_00 \ Manufacturer ID (Low Byte)
+ 15e $1 bitmask: MAN_ID_0.MAN_ID_00 \ Manufacturer ID (Low Byte)
+$15f constant MAN_ID_1 \ Device Identification Register
+ $ff constant MAN_ID_1_MAN_ID_ \ Manufacturer ID (High Byte)
+ 15f $ff bitmask: MAN_ID_1.MAN_ID_ \ Manufacturer ID (High Byte)
+$160 constant SHORT_ADDR_0 \ Transceiver MAC Short Address
+ $80 constant SHORT_ADDR_0_SHORT_ADDR_07 \ MAC Short Address
+ 160 $80 bitmask: SHORT_ADDR_0.SHORT_ADDR_07 \ MAC Short Address
+ $40 constant SHORT_ADDR_0_SHORT_ADDR_06 \ MAC Short Address
+ 160 $40 bitmask: SHORT_ADDR_0.SHORT_ADDR_06 \ MAC Short Address
+ $20 constant SHORT_ADDR_0_SHORT_ADDR_05 \ MAC Short Address
+ 160 $20 bitmask: SHORT_ADDR_0.SHORT_ADDR_05 \ MAC Short Address
+ $10 constant SHORT_ADDR_0_SHORT_ADDR_04 \ MAC Short Address
+ 160 $10 bitmask: SHORT_ADDR_0.SHORT_ADDR_04 \ MAC Short Address
+ $8 constant SHORT_ADDR_0_SHORT_ADDR_03 \ MAC Short Address
+ 160 $8 bitmask: SHORT_ADDR_0.SHORT_ADDR_03 \ MAC Short Address
+ $4 constant SHORT_ADDR_0_SHORT_ADDR_02 \ MAC Short Address
+ 160 $4 bitmask: SHORT_ADDR_0.SHORT_ADDR_02 \ MAC Short Address
+ $2 constant SHORT_ADDR_0_SHORT_ADDR_01 \ MAC Short Address
+ 160 $2 bitmask: SHORT_ADDR_0.SHORT_ADDR_01 \ MAC Short Address
+ $1 constant SHORT_ADDR_0_SHORT_ADDR_00 \ MAC Short Address
+ 160 $1 bitmask: SHORT_ADDR_0.SHORT_ADDR_00 \ MAC Short Address
+$161 constant SHORT_ADDR_1 \ Transceiver MAC Short Address
+ $ff constant SHORT_ADDR_1_SHORT_ADDR_ \ MAC Short Address
+ 161 $ff bitmask: SHORT_ADDR_1.SHORT_ADDR_ \ MAC Short Address
+$162 constant PAN_ID_0 \ Transceiver Personal Area Netw
+ $80 constant PAN_ID_0_PAN_ID_07 \ MAC Personal Area Network ID
+ 162 $80 bitmask: PAN_ID_0.PAN_ID_07 \ MAC Personal Area Network ID
+ $40 constant PAN_ID_0_PAN_ID_06 \ MAC Personal Area Network ID
+ 162 $40 bitmask: PAN_ID_0.PAN_ID_06 \ MAC Personal Area Network ID
+ $20 constant PAN_ID_0_PAN_ID_05 \ MAC Personal Area Network ID
+ 162 $20 bitmask: PAN_ID_0.PAN_ID_05 \ MAC Personal Area Network ID
+ $10 constant PAN_ID_0_PAN_ID_04 \ MAC Personal Area Network ID
+ 162 $10 bitmask: PAN_ID_0.PAN_ID_04 \ MAC Personal Area Network ID
+ $8 constant PAN_ID_0_PAN_ID_03 \ MAC Personal Area Network ID
+ 162 $8 bitmask: PAN_ID_0.PAN_ID_03 \ MAC Personal Area Network ID
+ $4 constant PAN_ID_0_PAN_ID_02 \ MAC Personal Area Network ID
+ 162 $4 bitmask: PAN_ID_0.PAN_ID_02 \ MAC Personal Area Network ID
+ $2 constant PAN_ID_0_PAN_ID_01 \ MAC Personal Area Network ID
+ 162 $2 bitmask: PAN_ID_0.PAN_ID_01 \ MAC Personal Area Network ID
+ $1 constant PAN_ID_0_PAN_ID_00 \ MAC Personal Area Network ID
+ 162 $1 bitmask: PAN_ID_0.PAN_ID_00 \ MAC Personal Area Network ID
+$163 constant PAN_ID_1 \ Transceiver Personal Area Netw
+ $ff constant PAN_ID_1_PAN_ID_ \ MAC Personal Area Network ID
+ 163 $ff bitmask: PAN_ID_1.PAN_ID_ \ MAC Personal Area Network ID
+$164 constant IEEE_ADDR_0 \ Transceiver MAC IEEE Address R
+ $80 constant IEEE_ADDR_0_IEEE_ADDR_07 \ MAC IEEE Address
+ 164 $80 bitmask: IEEE_ADDR_0.IEEE_ADDR_07 \ MAC IEEE Address
+ $40 constant IEEE_ADDR_0_IEEE_ADDR_06 \ MAC IEEE Address
+ 164 $40 bitmask: IEEE_ADDR_0.IEEE_ADDR_06 \ MAC IEEE Address
+ $20 constant IEEE_ADDR_0_IEEE_ADDR_05 \ MAC IEEE Address
+ 164 $20 bitmask: IEEE_ADDR_0.IEEE_ADDR_05 \ MAC IEEE Address
+ $10 constant IEEE_ADDR_0_IEEE_ADDR_04 \ MAC IEEE Address
+ 164 $10 bitmask: IEEE_ADDR_0.IEEE_ADDR_04 \ MAC IEEE Address
+ $8 constant IEEE_ADDR_0_IEEE_ADDR_03 \ MAC IEEE Address
+ 164 $8 bitmask: IEEE_ADDR_0.IEEE_ADDR_03 \ MAC IEEE Address
+ $4 constant IEEE_ADDR_0_IEEE_ADDR_02 \ MAC IEEE Address
+ 164 $4 bitmask: IEEE_ADDR_0.IEEE_ADDR_02 \ MAC IEEE Address
+ $2 constant IEEE_ADDR_0_IEEE_ADDR_01 \ MAC IEEE Address
+ 164 $2 bitmask: IEEE_ADDR_0.IEEE_ADDR_01 \ MAC IEEE Address
+ $1 constant IEEE_ADDR_0_IEEE_ADDR_00 \ MAC IEEE Address
+ 164 $1 bitmask: IEEE_ADDR_0.IEEE_ADDR_00 \ MAC IEEE Address
+$165 constant IEEE_ADDR_1 \ Transceiver MAC IEEE Address R
+ $ff constant IEEE_ADDR_1_IEEE_ADDR_ \ MAC IEEE Address
+ 165 $ff bitmask: IEEE_ADDR_1.IEEE_ADDR_ \ MAC IEEE Address
+$166 constant IEEE_ADDR_2 \ Transceiver MAC IEEE Address R
+ $ff constant IEEE_ADDR_2_IEEE_ADDR_ \ MAC IEEE Address
+ 166 $ff bitmask: IEEE_ADDR_2.IEEE_ADDR_ \ MAC IEEE Address
+$167 constant IEEE_ADDR_3 \ Transceiver MAC IEEE Address R
+ $ff constant IEEE_ADDR_3_IEEE_ADDR_ \ MAC IEEE Address
+ 167 $ff bitmask: IEEE_ADDR_3.IEEE_ADDR_ \ MAC IEEE Address
+$168 constant IEEE_ADDR_4 \ Transceiver MAC IEEE Address R
+ $ff constant IEEE_ADDR_4_IEEE_ADDR_ \ MAC IEEE Address
+ 168 $ff bitmask: IEEE_ADDR_4.IEEE_ADDR_ \ MAC IEEE Address
+$169 constant IEEE_ADDR_5 \ Transceiver MAC IEEE Address R
+ $ff constant IEEE_ADDR_5_IEEE_ADDR_ \ MAC IEEE Address
+ 169 $ff bitmask: IEEE_ADDR_5.IEEE_ADDR_ \ MAC IEEE Address
+$16a constant IEEE_ADDR_6 \ Transceiver MAC IEEE Address R
+ $ff constant IEEE_ADDR_6_IEEE_ADDR_ \ MAC IEEE Address
+ 16a $ff bitmask: IEEE_ADDR_6.IEEE_ADDR_ \ MAC IEEE Address
+$16b constant IEEE_ADDR_7 \ Transceiver MAC IEEE Address R
+ $ff constant IEEE_ADDR_7_IEEE_ADDR_ \ MAC IEEE Address
+ 16b $ff bitmask: IEEE_ADDR_7.IEEE_ADDR_ \ MAC IEEE Address
+$16c constant XAH_CTRL_0 \ Transceiver Extended Operating
+ $f0 constant XAH_CTRL_0_MAX_FRAME_RETRIES \ Maximum Number of Frame Re-tra
+ 16c $f0 bitmask: XAH_CTRL_0.MAX_FRAME_RETRIES \ Maximum Number of Frame Re-tra
+ $e constant XAH_CTRL_0_MAX_CSMA_RETRIES \ Maximum Number of CSMA-CA Proc
+ 16c $e bitmask: XAH_CTRL_0.MAX_CSMA_RETRIES \ Maximum Number of CSMA-CA Proc
+ $1 constant XAH_CTRL_0_SLOTTED_OPERATION \ Set Slotted Acknowledgment
+ 16c $1 bitmask: XAH_CTRL_0.SLOTTED_OPERATION \ Set Slotted Acknowledgment
+$16d constant CSMA_SEED_0 \ Transceiver CSMA-CA Random Num
+ $80 constant CSMA_SEED_0_CSMA_SEED_07 \ Seed Value for CSMA Random Num
+ 16d $80 bitmask: CSMA_SEED_0.CSMA_SEED_07 \ Seed Value for CSMA Random Num
+ $40 constant CSMA_SEED_0_CSMA_SEED_06 \ Seed Value for CSMA Random Num
+ 16d $40 bitmask: CSMA_SEED_0.CSMA_SEED_06 \ Seed Value for CSMA Random Num
+ $20 constant CSMA_SEED_0_CSMA_SEED_05 \ Seed Value for CSMA Random Num
+ 16d $20 bitmask: CSMA_SEED_0.CSMA_SEED_05 \ Seed Value for CSMA Random Num
+ $10 constant CSMA_SEED_0_CSMA_SEED_04 \ Seed Value for CSMA Random Num
+ 16d $10 bitmask: CSMA_SEED_0.CSMA_SEED_04 \ Seed Value for CSMA Random Num
+ $8 constant CSMA_SEED_0_CSMA_SEED_03 \ Seed Value for CSMA Random Num
+ 16d $8 bitmask: CSMA_SEED_0.CSMA_SEED_03 \ Seed Value for CSMA Random Num
+ $4 constant CSMA_SEED_0_CSMA_SEED_02 \ Seed Value for CSMA Random Num
+ 16d $4 bitmask: CSMA_SEED_0.CSMA_SEED_02 \ Seed Value for CSMA Random Num
+ $2 constant CSMA_SEED_0_CSMA_SEED_01 \ Seed Value for CSMA Random Num
+ 16d $2 bitmask: CSMA_SEED_0.CSMA_SEED_01 \ Seed Value for CSMA Random Num
+ $1 constant CSMA_SEED_0_CSMA_SEED_00 \ Seed Value for CSMA Random Num
+ 16d $1 bitmask: CSMA_SEED_0.CSMA_SEED_00 \ Seed Value for CSMA Random Num
+$16e constant CSMA_SEED_1 \ Transceiver Acknowledgment Fra
+ $c0 constant CSMA_SEED_1_AACK_FVN_MODE \ Acknowledgment Frame Filter Mo
+ 16e $c0 bitmask: CSMA_SEED_1.AACK_FVN_MODE \ Acknowledgment Frame Filter Mo
+ $20 constant CSMA_SEED_1_AACK_SET_PD \ Set Frame Pending Sub-field
+ 16e $20 bitmask: CSMA_SEED_1.AACK_SET_PD \ Set Frame Pending Sub-field
+ $10 constant CSMA_SEED_1_AACK_DIS_ACK \ Disable Acknowledgment Frame T
+ 16e $10 bitmask: CSMA_SEED_1.AACK_DIS_ACK \ Disable Acknowledgment Frame T
+ $8 constant CSMA_SEED_1_AACK_I_AM_COORD \ Set Personal Area Network Coor
+ 16e $8 bitmask: CSMA_SEED_1.AACK_I_AM_COORD \ Set Personal Area Network Coor
+ $7 constant CSMA_SEED_1_CSMA_SEED_1 \ Seed Value for CSMA Random Num
+ 16e $7 bitmask: CSMA_SEED_1.CSMA_SEED_1 \ Seed Value for CSMA Random Num
+$16f constant CSMA_BE \ Transceiver CSMA-CA Back-off E
+ $f0 constant CSMA_BE_MAX_BE \ Maximum Back-off Exponent
+ 16f $f0 bitmask: CSMA_BE.MAX_BE \ Maximum Back-off Exponent
+ $f constant CSMA_BE_MIN_BE \ Minimum Back-off Exponent
+ 16f $f bitmask: CSMA_BE.MIN_BE \ Minimum Back-off Exponent
+$176 constant TST_CTRL_DIGI \ Transceiver Digital Test Contr
+ $f constant TST_CTRL_DIGI_TST_CTRL_DIG \ Digital Test Controller Regist
+ 176 $f bitmask: TST_CTRL_DIGI.TST_CTRL_DIG \ Digital Test Controller Regist
+$17b constant TST_RX_LENGTH \ Transceiver Received Frame Len
+ $ff constant TST_RX_LENGTH_RX_LENGTH \ Received Frame Length
+ 17b $ff bitmask: TST_RX_LENGTH.RX_LENGTH \ Received Frame Length
+$180 constant TRXFBST \ Start of frame buffer
+$1ff constant TRXFBEND \ End of frame buffer
diff --git a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/TWI.frt b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/TWI.frt
new file mode 100644
index 0000000..7ac98fa
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/TWI.frt
@@ -0,0 +1,40 @@
+\ Generated automatically for atmega256rfr2
+\ #require bitnames.frt
+
+\ TWI
+$bd constant TWAMR \ TWI (Slave) Address Mask Regis
+ $fe constant TWAMR_TWAM \ TWI Address Mask
+ bd $fe bitmask: TWAMR.TWAM \ TWI Address Mask
+ $1 constant TWAMR_Res \ Reserved Bit
+ bd $1 bitmask: TWAMR.Res \ Reserved Bit
+$b8 constant TWBR \ TWI Bit Rate Register
+$bc constant TWCR \ TWI Control Register
+ $80 constant TWCR_TWINT \ TWI Interrupt Flag
+ bc $80 bitmask: TWCR.TWINT \ TWI Interrupt Flag
+ $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
+ bc $40 bitmask: TWCR.TWEA \ TWI Enable Acknowledge Bit
+ $20 constant TWCR_TWSTA \ TWI START Condition Bit
+ bc $20 bitmask: TWCR.TWSTA \ TWI START Condition Bit
+ $10 constant TWCR_TWSTO \ TWI STOP Condition Bit
+ bc $10 bitmask: TWCR.TWSTO \ TWI STOP Condition Bit
+ $8 constant TWCR_TWWC \ TWI Write Collision Flag
+ bc $8 bitmask: TWCR.TWWC \ TWI Write Collision Flag
+ $4 constant TWCR_TWEN \ TWI Enable Bit
+ bc $4 bitmask: TWCR.TWEN \ TWI Enable Bit
+ $2 constant TWCR_Res \ Reserved Bit
+ bc $2 bitmask: TWCR.Res \ Reserved Bit
+ $1 constant TWCR_TWIE \ TWI Interrupt Enable
+ bc $1 bitmask: TWCR.TWIE \ TWI Interrupt Enable
+$b9 constant TWSR \ TWI Status Register
+ $f8 constant TWSR_TWS \ TWI Status
+ b9 $f8 bitmask: TWSR.TWS \ TWI Status
+ $4 constant TWSR_Res \ Reserved Bit
+ b9 $4 bitmask: TWSR.Res \ Reserved Bit
+ $3 constant TWSR_TWPS \ TWI Prescaler Bits
+ b9 $3 bitmask: TWSR.TWPS \ TWI Prescaler Bits
+$bb constant TWDR \ TWI Data Register
+$ba constant TWAR \ TWI (Slave) Address Register
+ $fe constant TWAR_TWA \ TWI (Slave) Address
+ ba $fe bitmask: TWAR.TWA \ TWI (Slave) Address
+ $1 constant TWAR_TWGCE \ TWI General Call Recognition E
+ ba $1 bitmask: TWAR.TWGCE \ TWI General Call Recognition E
diff --git a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/USART0.frt b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/USART0.frt
new file mode 100644
index 0000000..3a4431e
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/USART0.frt
@@ -0,0 +1,51 @@
+\ Generated automatically for atmega256rfr2
+\ #require bitnames.frt
+
+\ USART0
+$c6 constant UDR0 \ USART0 I/O Data Register
+$c0 constant UCSR0A \ USART0 Control and Status Regi
+ $80 constant UCSR0A_RXC0 \ USART Receive Complete
+ c0 $80 bitmask: UCSR0A.RXC0 \ USART Receive Complete
+ $40 constant UCSR0A_TXC0 \ USART Transmit Complete
+ c0 $40 bitmask: UCSR0A.TXC0 \ USART Transmit Complete
+ $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
+ c0 $20 bitmask: UCSR0A.UDRE0 \ USART Data Register Empty
+ $10 constant UCSR0A_FE0 \ Frame Error
+ c0 $10 bitmask: UCSR0A.FE0 \ Frame Error
+ $8 constant UCSR0A_DOR0 \ Data OverRun
+ c0 $8 bitmask: UCSR0A.DOR0 \ Data OverRun
+ $4 constant UCSR0A_UPE0 \ USART Parity Error
+ c0 $4 bitmask: UCSR0A.UPE0 \ USART Parity Error
+ $2 constant UCSR0A_U2X0 \ Double the USART Transmission
+ c0 $2 bitmask: UCSR0A.U2X0 \ Double the USART Transmission
+ $1 constant UCSR0A_MPCM0 \ Multi-processor Communication
+ c0 $1 bitmask: UCSR0A.MPCM0 \ Multi-processor Communication
+$c1 constant UCSR0B \ USART0 Control and Status Regi
+ $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
+ c1 $80 bitmask: UCSR0B.RXCIE0 \ RX Complete Interrupt Enable
+ $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
+ c1 $40 bitmask: UCSR0B.TXCIE0 \ TX Complete Interrupt Enable
+ $20 constant UCSR0B_UDRIE0 \ USART Data Register Empty Inte
+ c1 $20 bitmask: UCSR0B.UDRIE0 \ USART Data Register Empty Inte
+ $10 constant UCSR0B_RXEN0 \ Receiver Enable
+ c1 $10 bitmask: UCSR0B.RXEN0 \ Receiver Enable
+ $8 constant UCSR0B_TXEN0 \ Transmitter Enable
+ c1 $8 bitmask: UCSR0B.TXEN0 \ Transmitter Enable
+ $4 constant UCSR0B_UCSZ02 \ Character Size
+ c1 $4 bitmask: UCSR0B.UCSZ02 \ Character Size
+ $2 constant UCSR0B_RXB80 \ Receive Data Bit 8
+ c1 $2 bitmask: UCSR0B.RXB80 \ Receive Data Bit 8
+ $1 constant UCSR0B_TXB80 \ Transmit Data Bit 8
+ c1 $1 bitmask: UCSR0B.TXB80 \ Transmit Data Bit 8
+$c2 constant UCSR0C \ USART0 Control and Status Regi
+ $c0 constant UCSR0C_UMSEL0 \ USART Mode Select
+ c2 $c0 bitmask: UCSR0C.UMSEL0 \ USART Mode Select
+ $30 constant UCSR0C_UPM0 \ Parity Mode
+ c2 $30 bitmask: UCSR0C.UPM0 \ Parity Mode
+ $8 constant UCSR0C_USBS0 \ Stop Bit Select
+ c2 $8 bitmask: UCSR0C.USBS0 \ Stop Bit Select
+ $6 constant UCSR0C_UCSZ0 \ Character Size
+ c2 $6 bitmask: UCSR0C.UCSZ0 \ Character Size
+ $1 constant UCSR0C_UCPOL0 \ Clock Polarity
+ c2 $1 bitmask: UCSR0C.UCPOL0 \ Clock Polarity
+$c4 constant UBRR0 \ USART0 Baud Rate Register Byt
diff --git a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/USART0_SPI.frt b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/USART0_SPI.frt
new file mode 100644
index 0000000..0acd6b4
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/USART0_SPI.frt
@@ -0,0 +1,29 @@
+\ Generated automatically for atmega256rfr2
+\ #require bitnames.frt
+
+\ USART0_SPI
+$c0 constant UCSR0A \ USART0 MSPIM Control and Statu
+ $80 constant UCSR0A_RXC0 \ USART Receive Complete
+ c0 $80 bitmask: UCSR0A.RXC0 \ USART Receive Complete
+ $40 constant UCSR0A_TXC0 \ USART Transmit Complete
+ c0 $40 bitmask: UCSR0A.TXC0 \ USART Transmit Complete
+ $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
+ c0 $20 bitmask: UCSR0A.UDRE0 \ USART Data Register Empty
+$c1 constant UCSR0B \ USART0 MSPIM Control and Statu
+ $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
+ c1 $80 bitmask: UCSR0B.RXCIE0 \ RX Complete Interrupt Enable
+ $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
+ c1 $40 bitmask: UCSR0B.TXCIE0 \ TX Complete Interrupt Enable
+ $20 constant UCSR0B_UDRIE0 \ USART Data Register Empty Inte
+ c1 $20 bitmask: UCSR0B.UDRIE0 \ USART Data Register Empty Inte
+ $10 constant UCSR0B_RXEN0 \ Receiver Enable
+ c1 $10 bitmask: UCSR0B.RXEN0 \ Receiver Enable
+ $8 constant UCSR0B_TXEN0 \ Transmitter Enable
+ c1 $8 bitmask: UCSR0B.TXEN0 \ Transmitter Enable
+$c2 constant UCSR0C \ USART0 MSPIM Control and Statu
+ $4 constant UCSR0C_UDORD0 \ Data Order
+ c2 $4 bitmask: UCSR0C.UDORD0 \ Data Order
+ $2 constant UCSR0C_UCPHA0 \ Clock Phase
+ c2 $2 bitmask: UCSR0C.UCPHA0 \ Clock Phase
+ $1 constant UCSR0C_UCPOL0 \ Clock Polarity
+ c2 $1 bitmask: UCSR0C.UCPOL0 \ Clock Polarity
diff --git a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/USART1.frt b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/USART1.frt
new file mode 100644
index 0000000..0852262
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/USART1.frt
@@ -0,0 +1,51 @@
+\ Generated automatically for atmega256rfr2
+\ #require bitnames.frt
+
+\ USART1
+$ce constant UDR1 \ USART1 I/O Data Register
+$c8 constant UCSR1A \ USART1 Control and Status Regi
+ $80 constant UCSR1A_RXC1 \ USART Receive Complete
+ c8 $80 bitmask: UCSR1A.RXC1 \ USART Receive Complete
+ $40 constant UCSR1A_TXC1 \ USART Transmit Complete
+ c8 $40 bitmask: UCSR1A.TXC1 \ USART Transmit Complete
+ $20 constant UCSR1A_UDRE1 \ USART Data Register Empty
+ c8 $20 bitmask: UCSR1A.UDRE1 \ USART Data Register Empty
+ $10 constant UCSR1A_FE1 \ Frame Error
+ c8 $10 bitmask: UCSR1A.FE1 \ Frame Error
+ $8 constant UCSR1A_DOR1 \ Data OverRun
+ c8 $8 bitmask: UCSR1A.DOR1 \ Data OverRun
+ $4 constant UCSR1A_UPE1 \ USART Parity Error
+ c8 $4 bitmask: UCSR1A.UPE1 \ USART Parity Error
+ $2 constant UCSR1A_U2X1 \ Double the USART Transmission
+ c8 $2 bitmask: UCSR1A.U2X1 \ Double the USART Transmission
+ $1 constant UCSR1A_MPCM1 \ Multi-processor Communication
+ c8 $1 bitmask: UCSR1A.MPCM1 \ Multi-processor Communication
+$c9 constant UCSR1B \ USART1 Control and Status Regi
+ $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable
+ c9 $80 bitmask: UCSR1B.RXCIE1 \ RX Complete Interrupt Enable
+ $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable
+ c9 $40 bitmask: UCSR1B.TXCIE1 \ TX Complete Interrupt Enable
+ $20 constant UCSR1B_UDRIE1 \ USART Data Register Empty Inte
+ c9 $20 bitmask: UCSR1B.UDRIE1 \ USART Data Register Empty Inte
+ $10 constant UCSR1B_RXEN1 \ Receiver Enable
+ c9 $10 bitmask: UCSR1B.RXEN1 \ Receiver Enable
+ $8 constant UCSR1B_TXEN1 \ Transmitter Enable
+ c9 $8 bitmask: UCSR1B.TXEN1 \ Transmitter Enable
+ $4 constant UCSR1B_UCSZ12 \ Character Size
+ c9 $4 bitmask: UCSR1B.UCSZ12 \ Character Size
+ $2 constant UCSR1B_RXB81 \ Receive Data Bit 8
+ c9 $2 bitmask: UCSR1B.RXB81 \ Receive Data Bit 8
+ $1 constant UCSR1B_TXB81 \ Transmit Data Bit 8
+ c9 $1 bitmask: UCSR1B.TXB81 \ Transmit Data Bit 8
+$ca constant UCSR1C \ USART1 Control and Status Regi
+ $c0 constant UCSR1C_UMSEL1 \ USART Mode Select
+ ca $c0 bitmask: UCSR1C.UMSEL1 \ USART Mode Select
+ $30 constant UCSR1C_UPM1 \ Parity Mode
+ ca $30 bitmask: UCSR1C.UPM1 \ Parity Mode
+ $8 constant UCSR1C_USBS1 \ Stop Bit Select
+ ca $8 bitmask: UCSR1C.USBS1 \ Stop Bit Select
+ $6 constant UCSR1C_UCSZ1 \ Character Size
+ ca $6 bitmask: UCSR1C.UCSZ1 \ Character Size
+ $1 constant UCSR1C_UCPOL1 \ Clock Polarity
+ ca $1 bitmask: UCSR1C.UCPOL1 \ Clock Polarity
+$cc constant UBRR1 \ USART1 Baud Rate Register Byt
diff --git a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/USART1_SPI.frt b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/USART1_SPI.frt
new file mode 100644
index 0000000..fa56346
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/USART1_SPI.frt
@@ -0,0 +1,29 @@
+\ Generated automatically for atmega256rfr2
+\ #require bitnames.frt
+
+\ USART1_SPI
+$c8 constant UCSR1A \ USART1 MSPIM Control and Statu
+ $80 constant UCSR1A_RXC1 \ USART Receive Complete
+ c8 $80 bitmask: UCSR1A.RXC1 \ USART Receive Complete
+ $40 constant UCSR1A_TXC1 \ USART Transmit Complete
+ c8 $40 bitmask: UCSR1A.TXC1 \ USART Transmit Complete
+ $20 constant UCSR1A_UDRE1 \ USART Data Register Empty
+ c8 $20 bitmask: UCSR1A.UDRE1 \ USART Data Register Empty
+$c9 constant UCSR1B \ USART1 MSPIM Control and Statu
+ $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable
+ c9 $80 bitmask: UCSR1B.RXCIE1 \ RX Complete Interrupt Enable
+ $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable
+ c9 $40 bitmask: UCSR1B.TXCIE1 \ TX Complete Interrupt Enable
+ $20 constant UCSR1B_UDRIE1 \ USART Data Register Empty Inte
+ c9 $20 bitmask: UCSR1B.UDRIE1 \ USART Data Register Empty Inte
+ $10 constant UCSR1B_RXEN1 \ Receiver Enable
+ c9 $10 bitmask: UCSR1B.RXEN1 \ Receiver Enable
+ $8 constant UCSR1B_TXEN1 \ Transmitter Enable
+ c9 $8 bitmask: UCSR1B.TXEN1 \ Transmitter Enable
+$ca constant UCSR1C \ USART1 MSPIM Control and Statu
+ $4 constant UCSR1C_UDORD1 \ Data Order
+ ca $4 bitmask: UCSR1C.UDORD1 \ Data Order
+ $2 constant UCSR1C_UCPHA1 \ Clock Phase
+ ca $2 bitmask: UCSR1C.UCPHA1 \ Clock Phase
+ $1 constant UCSR1C_UCPOL1 \ Clock Polarity
+ ca $1 bitmask: UCSR1C.UCPOL1 \ Clock Polarity
diff --git a/amforth-6.5/avr8/devices/atmega256rfr2/blocks/WATCHDOG.frt b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/WATCHDOG.frt
new file mode 100644
index 0000000..c695cba
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega256rfr2/blocks/WATCHDOG.frt
@@ -0,0 +1,15 @@
+\ Generated automatically for atmega256rfr2
+\ #require bitnames.frt
+
+\ WATCHDOG
+$60 constant WDTCSR \ Watchdog Timer Control Registe
+ $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Fla
+ 60 $80 bitmask: WDTCSR.WDIF \ Watchdog Timeout Interrupt Fla
+ $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Ena
+ 60 $40 bitmask: WDTCSR.WDIE \ Watchdog Timeout Interrupt Ena
+ $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
+ 60 $27 bitmask: WDTCSR.WDP \ Watchdog Timer Prescaler Bits
+ $10 constant WDTCSR_WDCE \ Watchdog Change Enable
+ 60 $10 bitmask: WDTCSR.WDCE \ Watchdog Change Enable
+ $8 constant WDTCSR_WDE \ Watch Dog Enable
+ 60 $8 bitmask: WDTCSR.WDE \ Watch Dog Enable
diff --git a/amforth-6.5/avr8/devices/atmega256rfr2/device.asm b/amforth-6.5/avr8/devices/atmega256rfr2/device.asm
new file mode 100644
index 0000000..9b76f0a
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega256rfr2/device.asm
@@ -0,0 +1,166 @@
+; Generated Automatically
+
+.nolist
+ include "m256RFR2def.inc"
+.list
+FLASHSTART = 0
+FLASHSIZE = 262144
+RAMEND = 33280
+IRAMSTART = 512
+IRAMSIZE = 32768
+EEPROMSIZE = 8192
+; Interrupt Vectors
+.overlap
+.org 2
+ rcall isr ; External Interrupt Request 0
+.org 4
+ rcall isr ; External Interrupt Request 1
+.org 6
+ rcall isr ; External Interrupt Request 2
+.org 8
+ rcall isr ; External Interrupt Request 3
+.org 10
+ rcall isr ; External Interrupt Request 4
+.org 12
+ rcall isr ; External Interrupt Request 5
+.org 14
+ rcall isr ; External Interrupt Request 6
+.org 16
+ rcall isr ; External Interrupt Request 7
+.org 18
+ rcall isr ; Pin Change Interrupt Request 0
+.org 20
+ rcall isr ; Pin Change Interrupt Request 1
+.org 22
+ rcall isr ; Pin Change Interrupt Request 2
+.org 24
+ rcall isr ; Watchdog Time-out Interrupt
+.org 26
+ rcall isr ; Timer/Counter2 Compare Match A
+.org 28
+ rcall isr ; Timer/Counter2 Compare Match B
+.org 30
+ rcall isr ; Timer/Counter2 Overflow
+.org 32
+ rcall isr ; Timer/Counter1 Capture Event
+.org 34
+ rcall isr ; Timer/Counter1 Compare Match A
+.org 36
+ rcall isr ; Timer/Counter1 Compare Match B
+.org 38
+ rcall isr ; Timer/Counter1 Compare Match C
+.org 40
+ rcall isr ; Timer/Counter1 Overflow
+.org 42
+ rcall isr ; Timer/Counter0 Compare Match A
+.org 44
+ rcall isr ; Timer/Counter0 Compare Match B
+.org 46
+ rcall isr ; Timer/Counter0 Overflow
+.org 48
+ rcall isr ; SPI Serial Transfer Complete
+.org 50
+ rcall isr ; USART0, Rx Complete
+.org 52
+ rcall isr ; USART0 Data register Empty
+.org 54
+ rcall isr ; USART0, Tx Complete
+.org 56
+ rcall isr ; Analog Comparator
+.org 58
+ rcall isr ; ADC Conversion Complete
+.org 60
+ rcall isr ; EEPROM Ready
+.org 62
+ rcall isr ; Timer/Counter3 Capture Event
+.org 64
+ rcall isr ; Timer/Counter3 Compare Match A
+.org 66
+ rcall isr ; Timer/Counter3 Compare Match B
+.org 68
+ rcall isr ; Timer/Counter3 Compare Match C
+.org 70
+ rcall isr ; Timer/Counter3 Overflow
+.org 72
+ rcall isr ; USART1, Rx Complete
+.org 74
+ rcall isr ; USART1 Data register Empty
+.org 76
+ rcall isr ; USART1, Tx Complete
+.org 78
+ rcall isr ; 2-wire Serial Interface
+.org 80
+ rcall isr ; Store Program Memory Read
+.org 82
+ rcall isr ; Timer/Counter4 Capture Event
+.org 84
+ rcall isr ; Timer/Counter4 Compare Match A
+.org 86
+ rcall isr ; Timer/Counter4 Compare Match B
+.org 88
+ rcall isr ; Timer/Counter4 Compare Match C
+.org 90
+ rcall isr ; Timer/Counter4 Overflow
+.org 92
+ rcall isr ; Timer/Counter5 Capture Event
+.org 94
+ rcall isr ; Timer/Counter5 Compare Match A
+.org 96
+ rcall isr ; Timer/Counter5 Compare Match B
+.org 98
+ rcall isr ; Timer/Counter5 Compare Match C
+.org 100
+ rcall isr ; Timer/Counter5 Overflow
+.org 102
+ rcall isr ; USART2, Rx Complete
+.org 104
+ rcall isr ; USART2 Data register Empty
+.org 106
+ rcall isr ; USART2, Tx Complete
+.org 108
+ rcall isr ; USART3, Rx Complete
+.org 110
+ rcall isr ; USART3 Data register Empty
+.org 112
+ rcall isr ; USART3, Tx Complete
+.org 114
+ rcall isr ; TRX24 - PLL lock interrupt
+.org 116
+ rcall isr ; TRX24 - PLL unlock interrupt
+.org 118
+ rcall isr ; TRX24 - Receive start interrupt
+.org 120
+ rcall isr ; TRX24 - RX_END interrupt
+.org 122
+ rcall isr ; TRX24 - CCA/ED done interrupt
+.org 124
+ rcall isr ; TRX24 - XAH - AMI
+.org 126
+ rcall isr ; TRX24 - TX_END interrupt
+.org 128
+ rcall isr ; TRX24 AWAKE - tranceiver is reaching state TRX_OFF
+.org 130
+ rcall isr ; Symbol counter - compare match 1 interrupt
+.org 132
+ rcall isr ; Symbol counter - compare match 2 interrupt
+.org 134
+ rcall isr ; Symbol counter - compare match 3 interrupt
+.org 136
+ rcall isr ; Symbol counter - overflow interrupt
+.org 138
+ rcall isr ; Symbol counter - backoff interrupt
+.org 140
+ rcall isr ; AES engine ready interrupt
+.org 142
+ rcall isr ; Battery monitor indicates supply voltage below threshold
+.org 144
+ rcall isr ; TRX24 TX start interrupt
+.org 146
+ rcall isr ; Address match interrupt of address filter 0
+.org 148
+ rcall isr ; Address match interrupt of address filter 1
+.org 150
+ rcall isr ; Address match interrupt of address filter 2
+.org 152
+ rcall isr ; Address match interrupt of address filter 3
+.nooverlap
diff --git a/amforth-6.5/avr8/devices/atmega256rfr2/device.frt b/amforth-6.5/avr8/devices/atmega256rfr2/device.frt
new file mode 100644
index 0000000..4ff689f
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega256rfr2/device.frt
@@ -0,0 +1,1753 @@
+\ Generated Automatically
+
+\ Interrupt Vectors
+#2 constant INT0Addr \ External Interrupt Request 0
+#4 constant INT1Addr \ External Interrupt Request 1
+#6 constant INT2Addr \ External Interrupt Request 2
+#8 constant INT3Addr \ External Interrupt Request 3
+#10 constant INT4Addr \ External Interrupt Request 4
+#12 constant INT5Addr \ External Interrupt Request 5
+#14 constant INT6Addr \ External Interrupt Request 6
+#16 constant INT7Addr \ External Interrupt Request 7
+#18 constant PCINT0Addr \ Pin Change Interrupt Request 0
+#20 constant PCINT1Addr \ Pin Change Interrupt Request 1
+#22 constant PCINT2Addr \ Pin Change Interrupt Request 2
+#24 constant WDTAddr \ Watchdog Time-out Interrupt
+#26 constant TIMER2_COMPAAddr \ Timer/Counter2 Compare Match A
+#28 constant TIMER2_COMPBAddr \ Timer/Counter2 Compare Match B
+#30 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
+#32 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+#34 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
+#36 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
+#38 constant TIMER1_COMPCAddr \ Timer/Counter1 Compare Match C
+#40 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+#42 constant TIMER0_COMPAAddr \ Timer/Counter0 Compare Match A
+#44 constant TIMER0_COMPBAddr \ Timer/Counter0 Compare Match B
+#46 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
+#48 constant SPI_STCAddr \ SPI Serial Transfer Complete
+#50 constant USART0_RXAddr \ USART0, Rx Complete
+#52 constant USART0_UDREAddr \ USART0 Data register Empty
+#54 constant USART0_TXAddr \ USART0, Tx Complete
+#56 constant ANALOG_COMPAddr \ Analog Comparator
+#58 constant ADCAddr \ ADC Conversion Complete
+#60 constant EE_READYAddr \ EEPROM Ready
+#62 constant TIMER3_CAPTAddr \ Timer/Counter3 Capture Event
+#64 constant TIMER3_COMPAAddr \ Timer/Counter3 Compare Match A
+#66 constant TIMER3_COMPBAddr \ Timer/Counter3 Compare Match B
+#68 constant TIMER3_COMPCAddr \ Timer/Counter3 Compare Match C
+#70 constant TIMER3_OVFAddr \ Timer/Counter3 Overflow
+#72 constant USART1_RXAddr \ USART1, Rx Complete
+#74 constant USART1_UDREAddr \ USART1 Data register Empty
+#76 constant USART1_TXAddr \ USART1, Tx Complete
+#78 constant TWIAddr \ 2-wire Serial Interface
+#80 constant SPM_READYAddr \ Store Program Memory Read
+#82 constant TIMER4_CAPTAddr \ Timer/Counter4 Capture Event
+#84 constant TIMER4_COMPAAddr \ Timer/Counter4 Compare Match A
+#86 constant TIMER4_COMPBAddr \ Timer/Counter4 Compare Match B
+#88 constant TIMER4_COMPCAddr \ Timer/Counter4 Compare Match C
+#90 constant TIMER4_OVFAddr \ Timer/Counter4 Overflow
+#92 constant TIMER5_CAPTAddr \ Timer/Counter5 Capture Event
+#94 constant TIMER5_COMPAAddr \ Timer/Counter5 Compare Match A
+#96 constant TIMER5_COMPBAddr \ Timer/Counter5 Compare Match B
+#98 constant TIMER5_COMPCAddr \ Timer/Counter5 Compare Match C
+#100 constant TIMER5_OVFAddr \ Timer/Counter5 Overflow
+#102 constant USART2_RXAddr \ USART2, Rx Complete
+#104 constant USART2_UDREAddr \ USART2 Data register Empty
+#106 constant USART2_TXAddr \ USART2, Tx Complete
+#108 constant USART3_RXAddr \ USART3, Rx Complete
+#110 constant USART3_UDREAddr \ USART3 Data register Empty
+#112 constant USART3_TXAddr \ USART3, Tx Complete
+#114 constant TRX24_PLL_LOCKAddr \ TRX24 - PLL lock interrupt
+#116 constant TRX24_PLL_UNLOCKAddr \ TRX24 - PLL unlock interrupt
+#118 constant TRX24_RX_STARTAddr \ TRX24 - Receive start interrupt
+#120 constant TRX24_RX_ENDAddr \ TRX24 - RX_END interrupt
+#122 constant TRX24_CCA_ED_DONEAddr \ TRX24 - CCA/ED done interrupt
+#124 constant TRX24_XAH_AMIAddr \ TRX24 - XAH - AMI
+#126 constant TRX24_TX_ENDAddr \ TRX24 - TX_END interrupt
+#128 constant TRX24_AWAKEAddr \ TRX24 AWAKE - tranceiver is reaching state TRX_OFF
+#130 constant SCNT_CMP1Addr \ Symbol counter - compare match 1 interrupt
+#132 constant SCNT_CMP2Addr \ Symbol counter - compare match 2 interrupt
+#134 constant SCNT_CMP3Addr \ Symbol counter - compare match 3 interrupt
+#136 constant SCNT_OVFLAddr \ Symbol counter - overflow interrupt
+#138 constant SCNT_BACKOFFAddr \ Symbol counter - backoff interrupt
+#140 constant AES_READYAddr \ AES engine ready interrupt
+#142 constant BAT_LOWAddr \ Battery monitor indicates supply voltage below threshold
+#144 constant TRX24_TX_STARTAddr \ TRX24 TX start interrupt
+#146 constant TRX24_AMI0Addr \ Address match interrupt of address filter 0
+#148 constant TRX24_AMI1Addr \ Address match interrupt of address filter 1
+#150 constant TRX24_AMI2Addr \ Address match interrupt of address filter 2
+#152 constant TRX24_AMI3Addr \ Address match interrupt of address filter 3
+\ ANALOG_COMPARATOR
+$7b constant ADCSRB \ ADC Control and Status Registe
+ $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer
+ 7b $40 bitmask: ADCSRB.ACME \ Analog Comparator Multiplexer
+$50 constant ACSR \ Analog Comparator Control And
+ $80 constant ACSR_ACD \ Analog Comparator Disable
+ 50 $80 bitmask: ACSR.ACD \ Analog Comparator Disable
+ $40 constant ACSR_ACBG \ Analog Comparator Bandgap Sele
+ 50 $40 bitmask: ACSR.ACBG \ Analog Comparator Bandgap Sele
+ $20 constant ACSR_ACO \ Analog Compare Output
+ 50 $20 bitmask: ACSR.ACO \ Analog Compare Output
+ $10 constant ACSR_ACI \ Analog Comparator Interrupt Fl
+ 50 $10 bitmask: ACSR.ACI \ Analog Comparator Interrupt Fl
+ $8 constant ACSR_ACIE \ Analog Comparator Interrupt En
+ 50 $8 bitmask: ACSR.ACIE \ Analog Comparator Interrupt En
+ $4 constant ACSR_ACIC \ Analog Comparator Input Captur
+ 50 $4 bitmask: ACSR.ACIC \ Analog Comparator Input Captur
+ $3 constant ACSR_ACIS \ Analog Comparator Interrupt Mo
+ 50 $3 bitmask: ACSR.ACIS \ Analog Comparator Interrupt Mo
+$7f constant DIDR1 \ Digital Input Disable Register
+ $2 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
+ 7f $2 bitmask: DIDR1.AIN1D \ AIN1 Digital Input Disable
+ $1 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
+ 7f $1 bitmask: DIDR1.AIN0D \ AIN0 Digital Input Disable
+\ USART0
+$c6 constant UDR0 \ USART0 I/O Data Register
+$c0 constant UCSR0A \ USART0 Control and Status Regi
+ $80 constant UCSR0A_RXC0 \ USART Receive Complete
+ c0 $80 bitmask: UCSR0A.RXC0 \ USART Receive Complete
+ $40 constant UCSR0A_TXC0 \ USART Transmit Complete
+ c0 $40 bitmask: UCSR0A.TXC0 \ USART Transmit Complete
+ $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
+ c0 $20 bitmask: UCSR0A.UDRE0 \ USART Data Register Empty
+ $10 constant UCSR0A_FE0 \ Frame Error
+ c0 $10 bitmask: UCSR0A.FE0 \ Frame Error
+ $8 constant UCSR0A_DOR0 \ Data OverRun
+ c0 $8 bitmask: UCSR0A.DOR0 \ Data OverRun
+ $4 constant UCSR0A_UPE0 \ USART Parity Error
+ c0 $4 bitmask: UCSR0A.UPE0 \ USART Parity Error
+ $2 constant UCSR0A_U2X0 \ Double the USART Transmission
+ c0 $2 bitmask: UCSR0A.U2X0 \ Double the USART Transmission
+ $1 constant UCSR0A_MPCM0 \ Multi-processor Communication
+ c0 $1 bitmask: UCSR0A.MPCM0 \ Multi-processor Communication
+$c1 constant UCSR0B \ USART0 Control and Status Regi
+ $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
+ c1 $80 bitmask: UCSR0B.RXCIE0 \ RX Complete Interrupt Enable
+ $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
+ c1 $40 bitmask: UCSR0B.TXCIE0 \ TX Complete Interrupt Enable
+ $20 constant UCSR0B_UDRIE0 \ USART Data Register Empty Inte
+ c1 $20 bitmask: UCSR0B.UDRIE0 \ USART Data Register Empty Inte
+ $10 constant UCSR0B_RXEN0 \ Receiver Enable
+ c1 $10 bitmask: UCSR0B.RXEN0 \ Receiver Enable
+ $8 constant UCSR0B_TXEN0 \ Transmitter Enable
+ c1 $8 bitmask: UCSR0B.TXEN0 \ Transmitter Enable
+ $4 constant UCSR0B_UCSZ02 \ Character Size
+ c1 $4 bitmask: UCSR0B.UCSZ02 \ Character Size
+ $2 constant UCSR0B_RXB80 \ Receive Data Bit 8
+ c1 $2 bitmask: UCSR0B.RXB80 \ Receive Data Bit 8
+ $1 constant UCSR0B_TXB80 \ Transmit Data Bit 8
+ c1 $1 bitmask: UCSR0B.TXB80 \ Transmit Data Bit 8
+$c2 constant UCSR0C \ USART0 Control and Status Regi
+ $c0 constant UCSR0C_UMSEL0 \ USART Mode Select
+ c2 $c0 bitmask: UCSR0C.UMSEL0 \ USART Mode Select
+ $30 constant UCSR0C_UPM0 \ Parity Mode
+ c2 $30 bitmask: UCSR0C.UPM0 \ Parity Mode
+ $8 constant UCSR0C_USBS0 \ Stop Bit Select
+ c2 $8 bitmask: UCSR0C.USBS0 \ Stop Bit Select
+ $6 constant UCSR0C_UCSZ0 \ Character Size
+ c2 $6 bitmask: UCSR0C.UCSZ0 \ Character Size
+ $1 constant UCSR0C_UCPOL0 \ Clock Polarity
+ c2 $1 bitmask: UCSR0C.UCPOL0 \ Clock Polarity
+$c4 constant UBRR0 \ USART0 Baud Rate Register Byt
+\ USART1
+$ce constant UDR1 \ USART1 I/O Data Register
+$c8 constant UCSR1A \ USART1 Control and Status Regi
+ $80 constant UCSR1A_RXC1 \ USART Receive Complete
+ c8 $80 bitmask: UCSR1A.RXC1 \ USART Receive Complete
+ $40 constant UCSR1A_TXC1 \ USART Transmit Complete
+ c8 $40 bitmask: UCSR1A.TXC1 \ USART Transmit Complete
+ $20 constant UCSR1A_UDRE1 \ USART Data Register Empty
+ c8 $20 bitmask: UCSR1A.UDRE1 \ USART Data Register Empty
+ $10 constant UCSR1A_FE1 \ Frame Error
+ c8 $10 bitmask: UCSR1A.FE1 \ Frame Error
+ $8 constant UCSR1A_DOR1 \ Data OverRun
+ c8 $8 bitmask: UCSR1A.DOR1 \ Data OverRun
+ $4 constant UCSR1A_UPE1 \ USART Parity Error
+ c8 $4 bitmask: UCSR1A.UPE1 \ USART Parity Error
+ $2 constant UCSR1A_U2X1 \ Double the USART Transmission
+ c8 $2 bitmask: UCSR1A.U2X1 \ Double the USART Transmission
+ $1 constant UCSR1A_MPCM1 \ Multi-processor Communication
+ c8 $1 bitmask: UCSR1A.MPCM1 \ Multi-processor Communication
+$c9 constant UCSR1B \ USART1 Control and Status Regi
+ $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable
+ c9 $80 bitmask: UCSR1B.RXCIE1 \ RX Complete Interrupt Enable
+ $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable
+ c9 $40 bitmask: UCSR1B.TXCIE1 \ TX Complete Interrupt Enable
+ $20 constant UCSR1B_UDRIE1 \ USART Data Register Empty Inte
+ c9 $20 bitmask: UCSR1B.UDRIE1 \ USART Data Register Empty Inte
+ $10 constant UCSR1B_RXEN1 \ Receiver Enable
+ c9 $10 bitmask: UCSR1B.RXEN1 \ Receiver Enable
+ $8 constant UCSR1B_TXEN1 \ Transmitter Enable
+ c9 $8 bitmask: UCSR1B.TXEN1 \ Transmitter Enable
+ $4 constant UCSR1B_UCSZ12 \ Character Size
+ c9 $4 bitmask: UCSR1B.UCSZ12 \ Character Size
+ $2 constant UCSR1B_RXB81 \ Receive Data Bit 8
+ c9 $2 bitmask: UCSR1B.RXB81 \ Receive Data Bit 8
+ $1 constant UCSR1B_TXB81 \ Transmit Data Bit 8
+ c9 $1 bitmask: UCSR1B.TXB81 \ Transmit Data Bit 8
+$ca constant UCSR1C \ USART1 Control and Status Regi
+ $c0 constant UCSR1C_UMSEL1 \ USART Mode Select
+ ca $c0 bitmask: UCSR1C.UMSEL1 \ USART Mode Select
+ $30 constant UCSR1C_UPM1 \ Parity Mode
+ ca $30 bitmask: UCSR1C.UPM1 \ Parity Mode
+ $8 constant UCSR1C_USBS1 \ Stop Bit Select
+ ca $8 bitmask: UCSR1C.USBS1 \ Stop Bit Select
+ $6 constant UCSR1C_UCSZ1 \ Character Size
+ ca $6 bitmask: UCSR1C.UCSZ1 \ Character Size
+ $1 constant UCSR1C_UCPOL1 \ Clock Polarity
+ ca $1 bitmask: UCSR1C.UCPOL1 \ Clock Polarity
+$cc constant UBRR1 \ USART1 Baud Rate Register Byt
+\ TWI
+$bd constant TWAMR \ TWI (Slave) Address Mask Regis
+ $fe constant TWAMR_TWAM \ TWI Address Mask
+ bd $fe bitmask: TWAMR.TWAM \ TWI Address Mask
+ $1 constant TWAMR_Res \ Reserved Bit
+ bd $1 bitmask: TWAMR.Res \ Reserved Bit
+$b8 constant TWBR \ TWI Bit Rate Register
+$bc constant TWCR \ TWI Control Register
+ $80 constant TWCR_TWINT \ TWI Interrupt Flag
+ bc $80 bitmask: TWCR.TWINT \ TWI Interrupt Flag
+ $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
+ bc $40 bitmask: TWCR.TWEA \ TWI Enable Acknowledge Bit
+ $20 constant TWCR_TWSTA \ TWI START Condition Bit
+ bc $20 bitmask: TWCR.TWSTA \ TWI START Condition Bit
+ $10 constant TWCR_TWSTO \ TWI STOP Condition Bit
+ bc $10 bitmask: TWCR.TWSTO \ TWI STOP Condition Bit
+ $8 constant TWCR_TWWC \ TWI Write Collision Flag
+ bc $8 bitmask: TWCR.TWWC \ TWI Write Collision Flag
+ $4 constant TWCR_TWEN \ TWI Enable Bit
+ bc $4 bitmask: TWCR.TWEN \ TWI Enable Bit
+ $2 constant TWCR_Res \ Reserved Bit
+ bc $2 bitmask: TWCR.Res \ Reserved Bit
+ $1 constant TWCR_TWIE \ TWI Interrupt Enable
+ bc $1 bitmask: TWCR.TWIE \ TWI Interrupt Enable
+$b9 constant TWSR \ TWI Status Register
+ $f8 constant TWSR_TWS \ TWI Status
+ b9 $f8 bitmask: TWSR.TWS \ TWI Status
+ $4 constant TWSR_Res \ Reserved Bit
+ b9 $4 bitmask: TWSR.Res \ Reserved Bit
+ $3 constant TWSR_TWPS \ TWI Prescaler Bits
+ b9 $3 bitmask: TWSR.TWPS \ TWI Prescaler Bits
+$bb constant TWDR \ TWI Data Register
+$ba constant TWAR \ TWI (Slave) Address Register
+ $fe constant TWAR_TWA \ TWI (Slave) Address
+ ba $fe bitmask: TWAR.TWA \ TWI (Slave) Address
+ $1 constant TWAR_TWGCE \ TWI General Call Recognition E
+ ba $1 bitmask: TWAR.TWGCE \ TWI General Call Recognition E
+\ SPI
+$4c constant SPCR \ SPI Control Register
+ $80 constant SPCR_SPIE \ SPI Interrupt Enable
+ 4c $80 bitmask: SPCR.SPIE \ SPI Interrupt Enable
+ $40 constant SPCR_SPE \ SPI Enable
+ 4c $40 bitmask: SPCR.SPE \ SPI Enable
+ $20 constant SPCR_DORD \ Data Order
+ 4c $20 bitmask: SPCR.DORD \ Data Order
+ $10 constant SPCR_MSTR \ Master/Slave Select
+ 4c $10 bitmask: SPCR.MSTR \ Master/Slave Select
+ $8 constant SPCR_CPOL \ Clock polarity
+ 4c $8 bitmask: SPCR.CPOL \ Clock polarity
+ $4 constant SPCR_CPHA \ Clock Phase
+ 4c $4 bitmask: SPCR.CPHA \ Clock Phase
+ $3 constant SPCR_SPR \ SPI Clock Rate Select 1 and 0
+ 4c $3 bitmask: SPCR.SPR \ SPI Clock Rate Select 1 and 0
+$4d constant SPSR \ SPI Status Register
+ $80 constant SPSR_SPIF \ SPI Interrupt Flag
+ 4d $80 bitmask: SPSR.SPIF \ SPI Interrupt Flag
+ $40 constant SPSR_WCOL \ Write Collision Flag
+ 4d $40 bitmask: SPSR.WCOL \ Write Collision Flag
+ $3e constant SPSR_Res \ Reserved
+ 4d $3e bitmask: SPSR.Res \ Reserved
+ $1 constant SPSR_SPI2X \ Double SPI Speed Bit
+ 4d $1 bitmask: SPSR.SPI2X \ Double SPI Speed Bit
+$4e constant SPDR \ SPI Data Register
+\ PORTA
+$22 constant PORTA \ Port A Data Register
+$21 constant DDRA \ Port A Data Direction Register
+$20 constant PINA \ Port A Input Pins Address
+\ PORTB
+$25 constant PORTB \ Port B Data Register
+$24 constant DDRB \ Port B Data Direction Register
+$23 constant PINB \ Port B Input Pins Address
+\ PORTC
+$28 constant PORTC \ Port C Data Register
+$27 constant DDRC \ Port C Data Direction Register
+$26 constant PINC \ Port C Input Pins Address
+\ PORTD
+$2b constant PORTD \ Port D Data Register
+$2a constant DDRD \ Port D Data Direction Register
+$29 constant PIND \ Port D Input Pins Address
+\ PORTE
+$2e constant PORTE \ Port E Data Register
+$2d constant DDRE \ Port E Data Direction Register
+$2c constant PINE \ Port E Input Pins Address
+\ PORTF
+$31 constant PORTF \ Port F Data Register
+$30 constant DDRF \ Port F Data Direction Register
+$2f constant PINF \ Port F Input Pins Address
+\ PORTG
+$34 constant PORTG \ Port G Data Register
+$33 constant DDRG \ Port G Data Direction Register
+$32 constant PING \ Port G Input Pins Address
+\ TIMER_COUNTER_0
+$48 constant OCR0B \ Timer/Counter0 Output Compare
+$47 constant OCR0A \ Timer/Counter0 Output Compare
+$46 constant TCNT0 \ Timer/Counter0 Register
+$45 constant TCCR0B \ Timer/Counter0 Control Registe
+ $80 constant TCCR0B_FOC0A \ Force Output Compare A
+ 45 $80 bitmask: TCCR0B.FOC0A \ Force Output Compare A
+ $40 constant TCCR0B_FOC0B \ Force Output Compare B
+ 45 $40 bitmask: TCCR0B.FOC0B \ Force Output Compare B
+ $30 constant TCCR0B_Res \ Reserved Bit
+ 45 $30 bitmask: TCCR0B.Res \ Reserved Bit
+ $8 constant TCCR0B_WGM02 \
+ 45 $8 bitmask: TCCR0B.WGM02 \
+ $7 constant TCCR0B_CS0 \ Clock Select
+ 45 $7 bitmask: TCCR0B.CS0 \ Clock Select
+$44 constant TCCR0A \ Timer/Counter0 Control Registe
+ $c0 constant TCCR0A_COM0A \ Compare Match Output A Mode
+ 44 $c0 bitmask: TCCR0A.COM0A \ Compare Match Output A Mode
+ $30 constant TCCR0A_COM0B \ Compare Match Output B Mode
+ 44 $30 bitmask: TCCR0A.COM0B \ Compare Match Output B Mode
+ $c constant TCCR0A_Res \ Reserved Bit
+ 44 $c bitmask: TCCR0A.Res \ Reserved Bit
+ $3 constant TCCR0A_WGM0 \ Waveform Generation Mode
+ 44 $3 bitmask: TCCR0A.WGM0 \ Waveform Generation Mode
+$6e constant TIMSK0 \ Timer/Counter0 Interrupt Mask
+ $f8 constant TIMSK0_Res \ Reserved
+ 6e $f8 bitmask: TIMSK0.Res \ Reserved
+ $4 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare
+ 6e $4 bitmask: TIMSK0.OCIE0B \ Timer/Counter0 Output Compare
+ $2 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare
+ 6e $2 bitmask: TIMSK0.OCIE0A \ Timer/Counter0 Output Compare
+ $1 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interr
+ 6e $1 bitmask: TIMSK0.TOIE0 \ Timer/Counter0 Overflow Interr
+$35 constant TIFR0 \ Timer/Counter0 Interrupt Flag
+ $f8 constant TIFR0_Res \ Reserved
+ 35 $f8 bitmask: TIFR0.Res \ Reserved
+ $4 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare
+ 35 $4 bitmask: TIFR0.OCF0B \ Timer/Counter0 Output Compare
+ $2 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare
+ 35 $2 bitmask: TIFR0.OCF0A \ Timer/Counter0 Output Compare
+ $1 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
+ 35 $1 bitmask: TIFR0.TOV0 \ Timer/Counter0 Overflow Flag
+$43 constant GTCCR \ General Timer/Counter Control
+ $80 constant GTCCR_TSM \ Timer/Counter Synchronization
+ 43 $80 bitmask: GTCCR.TSM \ Timer/Counter Synchronization
+ $7c constant GTCCR_Res \ Reserved
+ 43 $7c bitmask: GTCCR.Res \ Reserved
+ $2 constant GTCCR_PSRASY \ Prescaler Reset Timer/Counter2
+ 43 $2 bitmask: GTCCR.PSRASY \ Prescaler Reset Timer/Counter2
+ $1 constant GTCCR_PSRSYNC \ Prescaler Reset for Synchronou
+ 43 $1 bitmask: GTCCR.PSRSYNC \ Prescaler Reset for Synchronou
+\ TIMER_COUNTER_2
+$70 constant TIMSK2 \ Timer/Counter Interrupt Mask r
+ $f8 constant TIMSK2_Res \ Reserved Bit
+ 70 $f8 bitmask: TIMSK2.Res \ Reserved Bit
+ $4 constant TIMSK2_OCIE2B \ Timer/Counter2 Output Compare
+ 70 $4 bitmask: TIMSK2.OCIE2B \ Timer/Counter2 Output Compare
+ $2 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare
+ 70 $2 bitmask: TIMSK2.OCIE2A \ Timer/Counter2 Output Compare
+ $1 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interr
+ 70 $1 bitmask: TIMSK2.TOIE2 \ Timer/Counter2 Overflow Interr
+$37 constant TIFR2 \ Timer/Counter Interrupt Flag R
+ $f8 constant TIFR2_Res \ Reserved Bit
+ 37 $f8 bitmask: TIFR2.Res \ Reserved Bit
+ $4 constant TIFR2_OCF2B \ Output Compare Flag 2 B
+ 37 $4 bitmask: TIFR2.OCF2B \ Output Compare Flag 2 B
+ $2 constant TIFR2_OCF2A \ Output Compare Flag 2 A
+ 37 $2 bitmask: TIFR2.OCF2A \ Output Compare Flag 2 A
+ $1 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
+ 37 $1 bitmask: TIFR2.TOV2 \ Timer/Counter2 Overflow Flag
+$b0 constant TCCR2A \ Timer/Counter2 Control Registe
+ $c0 constant TCCR2A_COM2A \ Compare Match Output A Mode
+ b0 $c0 bitmask: TCCR2A.COM2A \ Compare Match Output A Mode
+ $30 constant TCCR2A_COM2B \ Compare Match Output B Mode
+ b0 $30 bitmask: TCCR2A.COM2B \ Compare Match Output B Mode
+ $c constant TCCR2A_Res \ Reserved
+ b0 $c bitmask: TCCR2A.Res \ Reserved
+ $3 constant TCCR2A_WGM2 \ Waveform Generation Mode
+ b0 $3 bitmask: TCCR2A.WGM2 \ Waveform Generation Mode
+$b1 constant TCCR2B \ Timer/Counter2 Control Registe
+ $80 constant TCCR2B_FOC2A \ Force Output Compare A
+ b1 $80 bitmask: TCCR2B.FOC2A \ Force Output Compare A
+ $40 constant TCCR2B_FOC2B \ Force Output Compare B
+ b1 $40 bitmask: TCCR2B.FOC2B \ Force Output Compare B
+ $30 constant TCCR2B_Res \ Reserved
+ b1 $30 bitmask: TCCR2B.Res \ Reserved
+ $8 constant TCCR2B_WGM22 \ Waveform Generation Mode
+ b1 $8 bitmask: TCCR2B.WGM22 \ Waveform Generation Mode
+ $7 constant TCCR2B_CS2 \ Clock Select
+ b1 $7 bitmask: TCCR2B.CS2 \ Clock Select
+$b2 constant TCNT2 \ Timer/Counter2
+$b4 constant OCR2B \ Timer/Counter2 Output Compare
+$b3 constant OCR2A \ Timer/Counter2 Output Compare
+$b6 constant ASSR \ Asynchronous Status Register
+ $80 constant ASSR_EXCLKAMR \ Enable External Clock Input fo
+ b6 $80 bitmask: ASSR.EXCLKAMR \ Enable External Clock Input fo
+ $40 constant ASSR_EXCLK \ Enable External Clock Input
+ b6 $40 bitmask: ASSR.EXCLK \ Enable External Clock Input
+ $20 constant ASSR_AS2 \ Timer/Counter2 Asynchronous Mo
+ b6 $20 bitmask: ASSR.AS2 \ Timer/Counter2 Asynchronous Mo
+ $10 constant ASSR_TCN2UB \ Timer/Counter2 Update Busy
+ b6 $10 bitmask: ASSR.TCN2UB \ Timer/Counter2 Update Busy
+ $8 constant ASSR_OCR2AUB \ Timer/Counter2 Output Compare
+ b6 $8 bitmask: ASSR.OCR2AUB \ Timer/Counter2 Output Compare
+ $4 constant ASSR_OCR2BUB \ Timer/Counter2 Output Compare
+ b6 $4 bitmask: ASSR.OCR2BUB \ Timer/Counter2 Output Compare
+ $2 constant ASSR_TCR2AUB \ Timer/Counter2 Control Registe
+ b6 $2 bitmask: ASSR.TCR2AUB \ Timer/Counter2 Control Registe
+ $1 constant ASSR_TCR2BUB \ Timer/Counter2 Control Registe
+ b6 $1 bitmask: ASSR.TCR2BUB \ Timer/Counter2 Control Registe
+$43 constant GTCCR \ General Timer Counter Control
+ $80 constant GTCCR_TSM \ Timer/Counter Synchronization
+ 43 $80 bitmask: GTCCR.TSM \ Timer/Counter Synchronization
+ $2 constant GTCCR_PSRASY \ Prescaler Reset Timer/Counter2
+ 43 $2 bitmask: GTCCR.PSRASY \ Prescaler Reset Timer/Counter2
+\ WATCHDOG
+$60 constant WDTCSR \ Watchdog Timer Control Registe
+ $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Fla
+ 60 $80 bitmask: WDTCSR.WDIF \ Watchdog Timeout Interrupt Fla
+ $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Ena
+ 60 $40 bitmask: WDTCSR.WDIE \ Watchdog Timeout Interrupt Ena
+ $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
+ 60 $27 bitmask: WDTCSR.WDP \ Watchdog Timer Prescaler Bits
+ $10 constant WDTCSR_WDCE \ Watchdog Change Enable
+ 60 $10 bitmask: WDTCSR.WDCE \ Watchdog Change Enable
+ $8 constant WDTCSR_WDE \ Watch Dog Enable
+ 60 $8 bitmask: WDTCSR.WDE \ Watch Dog Enable
+\ TIMER_COUNTER_5
+$120 constant TCCR5A \ Timer/Counter5 Control Registe
+ $c0 constant TCCR5A_COM5A \ Compare Output Mode for Channe
+ 120 $c0 bitmask: TCCR5A.COM5A \ Compare Output Mode for Channe
+ $30 constant TCCR5A_COM5B \ Compare Output Mode for Channe
+ 120 $30 bitmask: TCCR5A.COM5B \ Compare Output Mode for Channe
+ $c constant TCCR5A_COM5C \ Compare Output Mode for Channe
+ 120 $c bitmask: TCCR5A.COM5C \ Compare Output Mode for Channe
+ $3 constant TCCR5A_WGM5 \ Waveform Generation Mode
+ 120 $3 bitmask: TCCR5A.WGM5 \ Waveform Generation Mode
+$121 constant TCCR5B \ Timer/Counter5 Control Registe
+ $80 constant TCCR5B_ICNC5 \ Input Capture 5 Noise Cancelle
+ 121 $80 bitmask: TCCR5B.ICNC5 \ Input Capture 5 Noise Cancelle
+ $40 constant TCCR5B_ICES5 \ Input Capture 5 Edge Select
+ 121 $40 bitmask: TCCR5B.ICES5 \ Input Capture 5 Edge Select
+ $20 constant TCCR5B_Res \ Reserved Bit
+ 121 $20 bitmask: TCCR5B.Res \ Reserved Bit
+ $18 constant TCCR5B_WGM5 \ Waveform Generation Mode
+ 121 $18 bitmask: TCCR5B.WGM5 \ Waveform Generation Mode
+ $7 constant TCCR5B_CS5 \ Clock Select
+ 121 $7 bitmask: TCCR5B.CS5 \ Clock Select
+$122 constant TCCR5C \ Timer/Counter5 Control Registe
+ $80 constant TCCR5C_FOC5A \ Force Output Compare for Chann
+ 122 $80 bitmask: TCCR5C.FOC5A \ Force Output Compare for Chann
+ $40 constant TCCR5C_FOC5B \ Force Output Compare for Chann
+ 122 $40 bitmask: TCCR5C.FOC5B \ Force Output Compare for Chann
+ $20 constant TCCR5C_FOC5C \ Force Output Compare for Chann
+ 122 $20 bitmask: TCCR5C.FOC5C \ Force Output Compare for Chann
+ $1f constant TCCR5C_Res \ Reserved
+ 122 $1f bitmask: TCCR5C.Res \ Reserved
+$124 constant TCNT5 \ Timer/Counter5 Bytes
+$128 constant OCR5A \ Timer/Counter5 Output Compare
+$12a constant OCR5B \ Timer/Counter5 Output Compare
+$12c constant OCR5C \ Timer/Counter5 Output Compare
+$126 constant ICR5 \ Timer/Counter5 Input Capture R
+$73 constant TIMSK5 \ Timer/Counter5 Interrupt Mask
+ $c0 constant TIMSK5_Res \ Reserved Bit
+ 73 $c0 bitmask: TIMSK5.Res \ Reserved Bit
+ $20 constant TIMSK5_ICIE5 \ Timer/Counter5 Input Capture I
+ 73 $20 bitmask: TIMSK5.ICIE5 \ Timer/Counter5 Input Capture I
+ $10 constant TIMSK5_Res \ Reserved Bit
+ 73 $10 bitmask: TIMSK5.Res \ Reserved Bit
+ $8 constant TIMSK5_OCIE5C \ Timer/Counter5 Output Compare
+ 73 $8 bitmask: TIMSK5.OCIE5C \ Timer/Counter5 Output Compare
+ $4 constant TIMSK5_OCIE5B \ Timer/Counter5 Output Compare
+ 73 $4 bitmask: TIMSK5.OCIE5B \ Timer/Counter5 Output Compare
+ $2 constant TIMSK5_OCIE5A \ Timer/Counter5 Output Compare
+ 73 $2 bitmask: TIMSK5.OCIE5A \ Timer/Counter5 Output Compare
+ $1 constant TIMSK5_TOIE5 \ Timer/Counter5 Overflow Interr
+ 73 $1 bitmask: TIMSK5.TOIE5 \ Timer/Counter5 Overflow Interr
+$3a constant TIFR5 \ Timer/Counter5 Interrupt Flag
+ $c0 constant TIFR5_Res \ Reserved Bit
+ 3a $c0 bitmask: TIFR5.Res \ Reserved Bit
+ $20 constant TIFR5_ICF5 \ Timer/Counter5 Input Capture F
+ 3a $20 bitmask: TIFR5.ICF5 \ Timer/Counter5 Input Capture F
+ $10 constant TIFR5_Res \ Reserved Bit
+ 3a $10 bitmask: TIFR5.Res \ Reserved Bit
+ $8 constant TIFR5_OCF5C \ Timer/Counter5 Output Compare
+ 3a $8 bitmask: TIFR5.OCF5C \ Timer/Counter5 Output Compare
+ $4 constant TIFR5_OCF5B \ Timer/Counter5 Output Compare
+ 3a $4 bitmask: TIFR5.OCF5B \ Timer/Counter5 Output Compare
+ $2 constant TIFR5_OCF5A \ Timer/Counter5 Output Compare
+ 3a $2 bitmask: TIFR5.OCF5A \ Timer/Counter5 Output Compare
+ $1 constant TIFR5_TOV5 \ Timer/Counter5 Overflow Flag
+ 3a $1 bitmask: TIFR5.TOV5 \ Timer/Counter5 Overflow Flag
+\ TIMER_COUNTER_4
+$a0 constant TCCR4A \ Timer/Counter4 Control Registe
+ $c0 constant TCCR4A_COM4A \ Compare Output Mode for Channe
+ a0 $c0 bitmask: TCCR4A.COM4A \ Compare Output Mode for Channe
+ $30 constant TCCR4A_COM4B \ Compare Output Mode for Channe
+ a0 $30 bitmask: TCCR4A.COM4B \ Compare Output Mode for Channe
+ $c constant TCCR4A_COM4C \ Compare Output Mode for Channe
+ a0 $c bitmask: TCCR4A.COM4C \ Compare Output Mode for Channe
+ $3 constant TCCR4A_WGM4 \ Waveform Generation Mode
+ a0 $3 bitmask: TCCR4A.WGM4 \ Waveform Generation Mode
+$a1 constant TCCR4B \ Timer/Counter4 Control Registe
+ $80 constant TCCR4B_ICNC4 \ Input Capture 4 Noise Cancelle
+ a1 $80 bitmask: TCCR4B.ICNC4 \ Input Capture 4 Noise Cancelle
+ $40 constant TCCR4B_ICES4 \ Input Capture 4 Edge Select
+ a1 $40 bitmask: TCCR4B.ICES4 \ Input Capture 4 Edge Select
+ $20 constant TCCR4B_Res \ Reserved Bit
+ a1 $20 bitmask: TCCR4B.Res \ Reserved Bit
+ $18 constant TCCR4B_WGM4 \ Waveform Generation Mode
+ a1 $18 bitmask: TCCR4B.WGM4 \ Waveform Generation Mode
+ $7 constant TCCR4B_CS4 \ Clock Select
+ a1 $7 bitmask: TCCR4B.CS4 \ Clock Select
+$a2 constant TCCR4C \ Timer/Counter4 Control Registe
+ $80 constant TCCR4C_FOC4A \ Force Output Compare for Chann
+ a2 $80 bitmask: TCCR4C.FOC4A \ Force Output Compare for Chann
+ $40 constant TCCR4C_FOC4B \ Force Output Compare for Chann
+ a2 $40 bitmask: TCCR4C.FOC4B \ Force Output Compare for Chann
+ $20 constant TCCR4C_FOC4C \ Force Output Compare for Chann
+ a2 $20 bitmask: TCCR4C.FOC4C \ Force Output Compare for Chann
+ $1f constant TCCR4C_Res \ Reserved
+ a2 $1f bitmask: TCCR4C.Res \ Reserved
+$a4 constant TCNT4 \ Timer/Counter4 Bytes
+$a8 constant OCR4A \ Timer/Counter4 Output Compare
+$aa constant OCR4B \ Timer/Counter4 Output Compare
+$ac constant OCR4C \ Timer/Counter4 Output Compare
+$a6 constant ICR4 \ Timer/Counter4 Input Capture R
+$72 constant TIMSK4 \ Timer/Counter4 Interrupt Mask
+ $c0 constant TIMSK4_Res \ Reserved Bit
+ 72 $c0 bitmask: TIMSK4.Res \ Reserved Bit
+ $20 constant TIMSK4_ICIE4 \ Timer/Counter4 Input Capture I
+ 72 $20 bitmask: TIMSK4.ICIE4 \ Timer/Counter4 Input Capture I
+ $10 constant TIMSK4_Res \ Reserved Bit
+ 72 $10 bitmask: TIMSK4.Res \ Reserved Bit
+ $8 constant TIMSK4_OCIE4C \ Timer/Counter4 Output Compare
+ 72 $8 bitmask: TIMSK4.OCIE4C \ Timer/Counter4 Output Compare
+ $4 constant TIMSK4_OCIE4B \ Timer/Counter4 Output Compare
+ 72 $4 bitmask: TIMSK4.OCIE4B \ Timer/Counter4 Output Compare
+ $2 constant TIMSK4_OCIE4A \ Timer/Counter4 Output Compare
+ 72 $2 bitmask: TIMSK4.OCIE4A \ Timer/Counter4 Output Compare
+ $1 constant TIMSK4_TOIE4 \ Timer/Counter4 Overflow Interr
+ 72 $1 bitmask: TIMSK4.TOIE4 \ Timer/Counter4 Overflow Interr
+$39 constant TIFR4 \ Timer/Counter4 Interrupt Flag
+ $c0 constant TIFR4_Res \ Reserved Bit
+ 39 $c0 bitmask: TIFR4.Res \ Reserved Bit
+ $20 constant TIFR4_ICF4 \ Timer/Counter4 Input Capture F
+ 39 $20 bitmask: TIFR4.ICF4 \ Timer/Counter4 Input Capture F
+ $10 constant TIFR4_Res \ Reserved Bit
+ 39 $10 bitmask: TIFR4.Res \ Reserved Bit
+ $8 constant TIFR4_OCF4C \ Timer/Counter4 Output Compare
+ 39 $8 bitmask: TIFR4.OCF4C \ Timer/Counter4 Output Compare
+ $4 constant TIFR4_OCF4B \ Timer/Counter4 Output Compare
+ 39 $4 bitmask: TIFR4.OCF4B \ Timer/Counter4 Output Compare
+ $2 constant TIFR4_OCF4A \ Timer/Counter4 Output Compare
+ 39 $2 bitmask: TIFR4.OCF4A \ Timer/Counter4 Output Compare
+ $1 constant TIFR4_TOV4 \ Timer/Counter4 Overflow Flag
+ 39 $1 bitmask: TIFR4.TOV4 \ Timer/Counter4 Overflow Flag
+\ TIMER_COUNTER_3
+$90 constant TCCR3A \ Timer/Counter3 Control Registe
+ $c0 constant TCCR3A_COM3A \ Compare Output Mode for Channe
+ 90 $c0 bitmask: TCCR3A.COM3A \ Compare Output Mode for Channe
+ $30 constant TCCR3A_COM3B \ Compare Output Mode for Channe
+ 90 $30 bitmask: TCCR3A.COM3B \ Compare Output Mode for Channe
+ $c constant TCCR3A_COM3C \ Compare Output Mode for Channe
+ 90 $c bitmask: TCCR3A.COM3C \ Compare Output Mode for Channe
+ $3 constant TCCR3A_WGM3 \ Waveform Generation Mode
+ 90 $3 bitmask: TCCR3A.WGM3 \ Waveform Generation Mode
+$91 constant TCCR3B \ Timer/Counter3 Control Registe
+ $80 constant TCCR3B_ICNC3 \ Input Capture 3 Noise Cancelle
+ 91 $80 bitmask: TCCR3B.ICNC3 \ Input Capture 3 Noise Cancelle
+ $40 constant TCCR3B_ICES3 \ Input Capture 3 Edge Select
+ 91 $40 bitmask: TCCR3B.ICES3 \ Input Capture 3 Edge Select
+ $20 constant TCCR3B_Res \ Reserved Bit
+ 91 $20 bitmask: TCCR3B.Res \ Reserved Bit
+ $18 constant TCCR3B_WGM3 \ Waveform Generation Mode
+ 91 $18 bitmask: TCCR3B.WGM3 \ Waveform Generation Mode
+ $7 constant TCCR3B_CS3 \ Clock Select
+ 91 $7 bitmask: TCCR3B.CS3 \ Clock Select
+$92 constant TCCR3C \ Timer/Counter3 Control Registe
+ $80 constant TCCR3C_FOC3A \ Force Output Compare for Chann
+ 92 $80 bitmask: TCCR3C.FOC3A \ Force Output Compare for Chann
+ $40 constant TCCR3C_FOC3B \ Force Output Compare for Chann
+ 92 $40 bitmask: TCCR3C.FOC3B \ Force Output Compare for Chann
+ $20 constant TCCR3C_FOC3C \ Force Output Compare for Chann
+ 92 $20 bitmask: TCCR3C.FOC3C \ Force Output Compare for Chann
+ $1f constant TCCR3C_Res \ Reserved
+ 92 $1f bitmask: TCCR3C.Res \ Reserved
+$94 constant TCNT3 \ Timer/Counter3 Bytes
+$98 constant OCR3A \ Timer/Counter3 Output Compare
+$9a constant OCR3B \ Timer/Counter3 Output Compare
+$9c constant OCR3C \ Timer/Counter3 Output Compare
+$96 constant ICR3 \ Timer/Counter3 Input Capture R
+$71 constant TIMSK3 \ Timer/Counter3 Interrupt Mask
+ $c0 constant TIMSK3_Res \ Reserved Bit
+ 71 $c0 bitmask: TIMSK3.Res \ Reserved Bit
+ $20 constant TIMSK3_ICIE3 \ Timer/Counter3 Input Capture I
+ 71 $20 bitmask: TIMSK3.ICIE3 \ Timer/Counter3 Input Capture I
+ $10 constant TIMSK3_Res \ Reserved Bit
+ 71 $10 bitmask: TIMSK3.Res \ Reserved Bit
+ $8 constant TIMSK3_OCIE3C \ Timer/Counter3 Output Compare
+ 71 $8 bitmask: TIMSK3.OCIE3C \ Timer/Counter3 Output Compare
+ $4 constant TIMSK3_OCIE3B \ Timer/Counter3 Output Compare
+ 71 $4 bitmask: TIMSK3.OCIE3B \ Timer/Counter3 Output Compare
+ $2 constant TIMSK3_OCIE3A \ Timer/Counter3 Output Compare
+ 71 $2 bitmask: TIMSK3.OCIE3A \ Timer/Counter3 Output Compare
+ $1 constant TIMSK3_TOIE3 \ Timer/Counter3 Overflow Interr
+ 71 $1 bitmask: TIMSK3.TOIE3 \ Timer/Counter3 Overflow Interr
+$38 constant TIFR3 \ Timer/Counter3 Interrupt Flag
+ $c0 constant TIFR3_Res \ Reserved Bit
+ 38 $c0 bitmask: TIFR3.Res \ Reserved Bit
+ $20 constant TIFR3_ICF3 \ Timer/Counter3 Input Capture F
+ 38 $20 bitmask: TIFR3.ICF3 \ Timer/Counter3 Input Capture F
+ $10 constant TIFR3_Res \ Reserved Bit
+ 38 $10 bitmask: TIFR3.Res \ Reserved Bit
+ $8 constant TIFR3_OCF3C \ Timer/Counter3 Output Compare
+ 38 $8 bitmask: TIFR3.OCF3C \ Timer/Counter3 Output Compare
+ $4 constant TIFR3_OCF3B \ Timer/Counter3 Output Compare
+ 38 $4 bitmask: TIFR3.OCF3B \ Timer/Counter3 Output Compare
+ $2 constant TIFR3_OCF3A \ Timer/Counter3 Output Compare
+ 38 $2 bitmask: TIFR3.OCF3A \ Timer/Counter3 Output Compare
+ $1 constant TIFR3_TOV3 \ Timer/Counter3 Overflow Flag
+ 38 $1 bitmask: TIFR3.TOV3 \ Timer/Counter3 Overflow Flag
+\ TIMER_COUNTER_1
+$80 constant TCCR1A \ Timer/Counter1 Control Registe
+ $c0 constant TCCR1A_COM1A \ Compare Output Mode for Channe
+ 80 $c0 bitmask: TCCR1A.COM1A \ Compare Output Mode for Channe
+ $30 constant TCCR1A_COM1B \ Compare Output Mode for Channe
+ 80 $30 bitmask: TCCR1A.COM1B \ Compare Output Mode for Channe
+ $c constant TCCR1A_COM1C \ Compare Output Mode for Channe
+ 80 $c bitmask: TCCR1A.COM1C \ Compare Output Mode for Channe
+ $3 constant TCCR1A_WGM1 \ Waveform Generation Mode
+ 80 $3 bitmask: TCCR1A.WGM1 \ Waveform Generation Mode
+$81 constant TCCR1B \ Timer/Counter1 Control Registe
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Cancelle
+ 81 $80 bitmask: TCCR1B.ICNC1 \ Input Capture 1 Noise Cancelle
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ 81 $40 bitmask: TCCR1B.ICES1 \ Input Capture 1 Edge Select
+ $20 constant TCCR1B_Res \ Reserved Bit
+ 81 $20 bitmask: TCCR1B.Res \ Reserved Bit
+ $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
+ 81 $18 bitmask: TCCR1B.WGM1 \ Waveform Generation Mode
+ $7 constant TCCR1B_CS1 \ Clock Select
+ 81 $7 bitmask: TCCR1B.CS1 \ Clock Select
+$82 constant TCCR1C \ Timer/Counter1 Control Registe
+ $80 constant TCCR1C_FOC1A \ Force Output Compare for Chann
+ 82 $80 bitmask: TCCR1C.FOC1A \ Force Output Compare for Chann
+ $40 constant TCCR1C_FOC1B \ Force Output Compare for Chann
+ 82 $40 bitmask: TCCR1C.FOC1B \ Force Output Compare for Chann
+ $20 constant TCCR1C_FOC1C \ Force Output Compare for Chann
+ 82 $20 bitmask: TCCR1C.FOC1C \ Force Output Compare for Chann
+ $1f constant TCCR1C_Res \ Reserved
+ 82 $1f bitmask: TCCR1C.Res \ Reserved
+$84 constant TCNT1 \ Timer/Counter1 Bytes
+$88 constant OCR1A \ Timer/Counter1 Output Compare
+$8a constant OCR1B \ Timer/Counter1 Output Compare
+$8c constant OCR1C \ Timer/Counter1 Output Compare
+$86 constant ICR1 \ Timer/Counter1 Input Capture R
+$6f constant TIMSK1 \ Timer/Counter1 Interrupt Mask
+ $c0 constant TIMSK1_Res \ Reserved Bit
+ 6f $c0 bitmask: TIMSK1.Res \ Reserved Bit
+ $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture I
+ 6f $20 bitmask: TIMSK1.ICIE1 \ Timer/Counter1 Input Capture I
+ $10 constant TIMSK1_Res \ Reserved Bit
+ 6f $10 bitmask: TIMSK1.Res \ Reserved Bit
+ $8 constant TIMSK1_OCIE1C \ Timer/Counter1 Output Compare
+ 6f $8 bitmask: TIMSK1.OCIE1C \ Timer/Counter1 Output Compare
+ $4 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare
+ 6f $4 bitmask: TIMSK1.OCIE1B \ Timer/Counter1 Output Compare
+ $2 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare
+ 6f $2 bitmask: TIMSK1.OCIE1A \ Timer/Counter1 Output Compare
+ $1 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interr
+ 6f $1 bitmask: TIMSK1.TOIE1 \ Timer/Counter1 Overflow Interr
+$36 constant TIFR1 \ Timer/Counter1 Interrupt Flag
+ $c0 constant TIFR1_Res \ Reserved Bit
+ 36 $c0 bitmask: TIFR1.Res \ Reserved Bit
+ $20 constant TIFR1_ICF1 \ Timer/Counter1 Input Capture F
+ 36 $20 bitmask: TIFR1.ICF1 \ Timer/Counter1 Input Capture F
+ $10 constant TIFR1_Res \ Reserved Bit
+ 36 $10 bitmask: TIFR1.Res \ Reserved Bit
+ $8 constant TIFR1_OCF1C \ Timer/Counter1 Output Compare
+ 36 $8 bitmask: TIFR1.OCF1C \ Timer/Counter1 Output Compare
+ $4 constant TIFR1_OCF1B \ Timer/Counter1 Output Compare
+ 36 $4 bitmask: TIFR1.OCF1B \ Timer/Counter1 Output Compare
+ $2 constant TIFR1_OCF1A \ Timer/Counter1 Output Compare
+ 36 $2 bitmask: TIFR1.OCF1A \ Timer/Counter1 Output Compare
+ $1 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
+ 36 $1 bitmask: TIFR1.TOV1 \ Timer/Counter1 Overflow Flag
+\ TRX24
+$138 constant PARCR \ Power Amplifier Ramp up/down C
+ $e0 constant PARCR_PALTD \ ext. PA Ramp Down Lead Time
+ 138 $e0 bitmask: PARCR.PALTD \ ext. PA Ramp Down Lead Time
+ $1c constant PARCR_PALTU \ ext. PA Ramp Up Lead Time
+ 138 $1c bitmask: PARCR.PALTU \ ext. PA Ramp Up Lead Time
+ $2 constant PARCR_PARDFI \ Power Amplifier Ramp Down Freq
+ 138 $2 bitmask: PARCR.PARDFI \ Power Amplifier Ramp Down Freq
+ $1 constant PARCR_PARUFI \ Power Amplifier Ramp Up Freque
+ 138 $1 bitmask: PARCR.PARUFI \ Power Amplifier Ramp Up Freque
+$10e constant MAFSA0L \ Transceiver MAC Short Address
+ $ff constant MAFSA0L_MAFSA0L \ MAC Short Address low Byte for
+ 10e $ff bitmask: MAFSA0L.MAFSA0L \ MAC Short Address low Byte for
+$10f constant MAFSA0H \ Transceiver MAC Short Address
+ $ff constant MAFSA0H_MAFSA0H \ MAC Short Address high Byte fo
+ 10f $ff bitmask: MAFSA0H.MAFSA0H \ MAC Short Address high Byte fo
+$110 constant MAFPA0L \ Transceiver Personal Area Netw
+ $ff constant MAFPA0L_MAFPA0L \ MAC Personal Area Network ID l
+ 110 $ff bitmask: MAFPA0L.MAFPA0L \ MAC Personal Area Network ID l
+$111 constant MAFPA0H \ Transceiver Personal Area Netw
+ $ff constant MAFPA0H_MAFPA0H \ MAC Personal Area Network ID h
+ 111 $ff bitmask: MAFPA0H.MAFPA0H \ MAC Personal Area Network ID h
+$112 constant MAFSA1L \ Transceiver MAC Short Address
+ $ff constant MAFSA1L_MAFSA1L \ MAC Short Address low Byte for
+ 112 $ff bitmask: MAFSA1L.MAFSA1L \ MAC Short Address low Byte for
+$113 constant MAFSA1H \ Transceiver MAC Short Address
+ $ff constant MAFSA1H_MAFSA1H \ MAC Short Address high Byte fo
+ 113 $ff bitmask: MAFSA1H.MAFSA1H \ MAC Short Address high Byte fo
+$114 constant MAFPA1L \ Transceiver Personal Area Netw
+ $ff constant MAFPA1L_MAFPA1L \ MAC Personal Area Network ID l
+ 114 $ff bitmask: MAFPA1L.MAFPA1L \ MAC Personal Area Network ID l
+$115 constant MAFPA1H \ Transceiver Personal Area Netw
+ $ff constant MAFPA1H_MAFPA1H \ MAC Personal Area Network ID h
+ 115 $ff bitmask: MAFPA1H.MAFPA1H \ MAC Personal Area Network ID h
+$116 constant MAFSA2L \ Transceiver MAC Short Address
+ $ff constant MAFSA2L_MAFSA2L \ MAC Short Address low Byte for
+ 116 $ff bitmask: MAFSA2L.MAFSA2L \ MAC Short Address low Byte for
+$117 constant MAFSA2H \ Transceiver MAC Short Address
+ $ff constant MAFSA2H_MAFSA2H \ MAC Short Address high Byte fo
+ 117 $ff bitmask: MAFSA2H.MAFSA2H \ MAC Short Address high Byte fo
+$118 constant MAFPA2L \ Transceiver Personal Area Netw
+ $ff constant MAFPA2L_MAFPA2L \ MAC Personal Area Network ID l
+ 118 $ff bitmask: MAFPA2L.MAFPA2L \ MAC Personal Area Network ID l
+$119 constant MAFPA2H \ Transceiver Personal Area Netw
+ $ff constant MAFPA2H_MAFPA2H \ MAC Personal Area Network ID h
+ 119 $ff bitmask: MAFPA2H.MAFPA2H \ MAC Personal Area Network ID h
+$11a constant MAFSA3L \ Transceiver MAC Short Address
+ $ff constant MAFSA3L_MAFSA3L \ MAC Short Address low Byte for
+ 11a $ff bitmask: MAFSA3L.MAFSA3L \ MAC Short Address low Byte for
+$11b constant MAFSA3H \ Transceiver MAC Short Address
+ $ff constant MAFSA3H_MAFSA3H \ MAC Short Address high Byte fo
+ 11b $ff bitmask: MAFSA3H.MAFSA3H \ MAC Short Address high Byte fo
+$11c constant MAFPA3L \ Transceiver Personal Area Netw
+ $ff constant MAFPA3L_MAFPA3L \ MAC Personal Area Network ID l
+ 11c $ff bitmask: MAFPA3L.MAFPA3L \ MAC Personal Area Network ID l
+$11d constant MAFPA3H \ Transceiver Personal Area Netw
+ $ff constant MAFPA3H_MAFPA3H \ MAC Personal Area Network ID h
+ 11d $ff bitmask: MAFPA3H.MAFPA3H \ MAC Personal Area Network ID h
+$10c constant MAFCR0 \ Multiple Address Filter Config
+ $f0 constant MAFCR0_Res \ Reserved Bit
+ 10c $f0 bitmask: MAFCR0.Res \ Reserved Bit
+ $8 constant MAFCR0_MAF3EN \ Multiple Address Filter 3 Enab
+ 10c $8 bitmask: MAFCR0.MAF3EN \ Multiple Address Filter 3 Enab
+ $4 constant MAFCR0_MAF2EN \ Multiple Address Filter 2 Enab
+ 10c $4 bitmask: MAFCR0.MAF2EN \ Multiple Address Filter 2 Enab
+ $2 constant MAFCR0_MAF1EN \ Multiple Address Filter 1 Enab
+ 10c $2 bitmask: MAFCR0.MAF1EN \ Multiple Address Filter 1 Enab
+ $1 constant MAFCR0_MAF0EN \ Multiple Address Filter 0 Enab
+ 10c $1 bitmask: MAFCR0.MAF0EN \ Multiple Address Filter 0 Enab
+$10d constant MAFCR1 \ Multiple Address Filter Config
+ $80 constant MAFCR1_AACK_3_SET_PD \ Set Data Pending bit for addre
+ 10d $80 bitmask: MAFCR1.AACK_3_SET_PD \ Set Data Pending bit for addre
+ $40 constant MAFCR1_AACK_3_I_AM_COORD \ Enable PAN Coordinator mode fo
+ 10d $40 bitmask: MAFCR1.AACK_3_I_AM_COORD \ Enable PAN Coordinator mode fo
+ $20 constant MAFCR1_AACK_2_SET_PD \ Set Data Pending bit for addre
+ 10d $20 bitmask: MAFCR1.AACK_2_SET_PD \ Set Data Pending bit for addre
+ $10 constant MAFCR1_AACK_2_I_AM_COORD \ Enable PAN Coordinator mode fo
+ 10d $10 bitmask: MAFCR1.AACK_2_I_AM_COORD \ Enable PAN Coordinator mode fo
+ $8 constant MAFCR1_AACK_1_SET_PD \ Set Data Pending bit for addre
+ 10d $8 bitmask: MAFCR1.AACK_1_SET_PD \ Set Data Pending bit for addre
+ $4 constant MAFCR1_AACK_1_I_AM_COORD \ Enable PAN Coordinator mode fo
+ 10d $4 bitmask: MAFCR1.AACK_1_I_AM_COORD \ Enable PAN Coordinator mode fo
+ $2 constant MAFCR1_AACK_0_SET_PD \ Set Data Pending bit for addre
+ 10d $2 bitmask: MAFCR1.AACK_0_SET_PD \ Set Data Pending bit for addre
+ $1 constant MAFCR1_AACK_0_I_AM_COORD \ Enable PAN Coordinator mode fo
+ 10d $1 bitmask: MAFCR1.AACK_0_I_AM_COORD \ Enable PAN Coordinator mode fo
+$13c constant AES_CTRL \ AES Control Register
+ $80 constant AES_CTRL_AES_REQUEST \ Request AES Operation.
+ 13c $80 bitmask: AES_CTRL.AES_REQUEST \ Request AES Operation.
+ $40 constant AES_CTRL_Res \ Reserved Bit
+ 13c $40 bitmask: AES_CTRL.Res \ Reserved Bit
+ $20 constant AES_CTRL_AES_MODE \ Set AES Operation Mode
+ 13c $20 bitmask: AES_CTRL.AES_MODE \ Set AES Operation Mode
+ $10 constant AES_CTRL_Res \ Reserved Bit
+ 13c $10 bitmask: AES_CTRL.Res \ Reserved Bit
+ $8 constant AES_CTRL_AES_DIR \ Set AES Operation Direction
+ 13c $8 bitmask: AES_CTRL.AES_DIR \ Set AES Operation Direction
+ $4 constant AES_CTRL_AES_IM \ AES Interrupt Enable
+ 13c $4 bitmask: AES_CTRL.AES_IM \ AES Interrupt Enable
+ $3 constant AES_CTRL_Res \ Reserved Bit
+ 13c $3 bitmask: AES_CTRL.Res \ Reserved Bit
+$13d constant AES_STATUS \ AES Status Register
+ $80 constant AES_STATUS_AES_ER \ AES Operation Finished with Er
+ 13d $80 bitmask: AES_STATUS.AES_ER \ AES Operation Finished with Er
+ $7e constant AES_STATUS_Res \ Reserved
+ 13d $7e bitmask: AES_STATUS.Res \ Reserved
+ $1 constant AES_STATUS_AES_DONE \ AES Operation Finished with Su
+ 13d $1 bitmask: AES_STATUS.AES_DONE \ AES Operation Finished with Su
+$13e constant AES_STATE \ AES Plain and Cipher Text Buff
+ $ff constant AES_STATE_AES_STATE \ AES Plain and Cipher Text Buff
+ 13e $ff bitmask: AES_STATE.AES_STATE \ AES Plain and Cipher Text Buff
+$13f constant AES_KEY \ AES Encryption and Decryption
+ $ff constant AES_KEY_AES_KEY \ AES Encryption/Decryption Key
+ 13f $ff bitmask: AES_KEY.AES_KEY \ AES Encryption/Decryption Key
+$141 constant TRX_STATUS \ Transceiver Status Register
+ $80 constant TRX_STATUS_CCA_DONE \ CCA Algorithm Status
+ 141 $80 bitmask: TRX_STATUS.CCA_DONE \ CCA Algorithm Status
+ $40 constant TRX_STATUS_CCA_STATUS \ CCA Status Result
+ 141 $40 bitmask: TRX_STATUS.CCA_STATUS \ CCA Status Result
+ $20 constant TRX_STATUS_TST_STATUS \ Test mode status
+ 141 $20 bitmask: TRX_STATUS.TST_STATUS \ Test mode status
+ $1f constant TRX_STATUS_TRX_STATUS \ Transceiver Main Status
+ 141 $1f bitmask: TRX_STATUS.TRX_STATUS \ Transceiver Main Status
+$142 constant TRX_STATE \ Transceiver State Control Regi
+ $e0 constant TRX_STATE_TRAC_STATUS \ Transaction Status
+ 142 $e0 bitmask: TRX_STATE.TRAC_STATUS \ Transaction Status
+ $1f constant TRX_STATE_TRX_CMD \ State Control Command
+ 142 $1f bitmask: TRX_STATE.TRX_CMD \ State Control Command
+$143 constant TRX_CTRL_0 \ Reserved
+ $80 constant TRX_CTRL_0_Res7 \ Reserved
+ 143 $80 bitmask: TRX_CTRL_0.Res7 \ Reserved
+ $40 constant TRX_CTRL_0_PMU_EN \ Enable Phase Measurement Unit
+ 143 $40 bitmask: TRX_CTRL_0.PMU_EN \ Enable Phase Measurement Unit
+ $20 constant TRX_CTRL_0_PMU_START \ Start of Phase Measurement Uni
+ 143 $20 bitmask: TRX_CTRL_0.PMU_START \ Start of Phase Measurement Uni
+ $10 constant TRX_CTRL_0_PMU_IF_INV \ PMU IF Inverse
+ 143 $10 bitmask: TRX_CTRL_0.PMU_IF_INV \ PMU IF Inverse
+ $f constant TRX_CTRL_0_Res \ Reserved
+ 143 $f bitmask: TRX_CTRL_0.Res \ Reserved
+$144 constant TRX_CTRL_1 \ Transceiver Control Register 1
+ $80 constant TRX_CTRL_1_PA_EXT_EN \ External PA support enable
+ 144 $80 bitmask: TRX_CTRL_1.PA_EXT_EN \ External PA support enable
+ $40 constant TRX_CTRL_1_IRQ_2_EXT_EN \ Connect Frame Start IRQ to TC1
+ 144 $40 bitmask: TRX_CTRL_1.IRQ_2_EXT_EN \ Connect Frame Start IRQ to TC1
+ $20 constant TRX_CTRL_1_TX_AUTO_CRC_ON \ Enable Automatic CRC Calculati
+ 144 $20 bitmask: TRX_CTRL_1.TX_AUTO_CRC_ON \ Enable Automatic CRC Calculati
+ $10 constant TRX_CTRL_1_PLL_TX_FLT \ Enable PLL TX filter
+ 144 $10 bitmask: TRX_CTRL_1.PLL_TX_FLT \ Enable PLL TX filter
+ $f constant TRX_CTRL_1_Res \ Reserved
+ 144 $f bitmask: TRX_CTRL_1.Res \ Reserved
+$145 constant PHY_TX_PWR \ Transceiver Transmit Power Con
+ $f0 constant PHY_TX_PWR_Res \ Reserved
+ 145 $f0 bitmask: PHY_TX_PWR.Res \ Reserved
+ $f constant PHY_TX_PWR_TX_PWR \ Transmit Power Setting
+ 145 $f bitmask: PHY_TX_PWR.TX_PWR \ Transmit Power Setting
+$146 constant PHY_RSSI \ Receiver Signal Strength Indic
+ $80 constant PHY_RSSI_RX_CRC_VALID \ Received Frame CRC Status
+ 146 $80 bitmask: PHY_RSSI.RX_CRC_VALID \ Received Frame CRC Status
+ $60 constant PHY_RSSI_RND_VALUE \ Random Value
+ 146 $60 bitmask: PHY_RSSI.RND_VALUE \ Random Value
+ $1f constant PHY_RSSI_RSSI \ Receiver Signal Strength Indic
+ 146 $1f bitmask: PHY_RSSI.RSSI \ Receiver Signal Strength Indic
+$147 constant PHY_ED_LEVEL \ Transceiver Energy Detection L
+ $ff constant PHY_ED_LEVEL_ED_LEVEL \ Energy Detection Level
+ 147 $ff bitmask: PHY_ED_LEVEL.ED_LEVEL \ Energy Detection Level
+$148 constant PHY_CC_CCA \ Transceiver Clear Channel Asse
+ $80 constant PHY_CC_CCA_CCA_REQUEST \ Manual CCA Measurement Request
+ 148 $80 bitmask: PHY_CC_CCA.CCA_REQUEST \ Manual CCA Measurement Request
+ $60 constant PHY_CC_CCA_CCA_MODE \ Select CCA Measurement Mode
+ 148 $60 bitmask: PHY_CC_CCA.CCA_MODE \ Select CCA Measurement Mode
+ $1f constant PHY_CC_CCA_CHANNEL \ RX/TX Channel Selection
+ 148 $1f bitmask: PHY_CC_CCA.CHANNEL \ RX/TX Channel Selection
+$149 constant CCA_THRES \ Transceiver CCA Threshold Sett
+ $f0 constant CCA_THRES_CCA_CS_THRES \ CS Threshold Level for CCA Mea
+ 149 $f0 bitmask: CCA_THRES.CCA_CS_THRES \ CS Threshold Level for CCA Mea
+ $f constant CCA_THRES_CCA_ED_THRES \ ED Threshold Level for CCA Mea
+ 149 $f bitmask: CCA_THRES.CCA_ED_THRES \ ED Threshold Level for CCA Mea
+$14a constant RX_CTRL \ Transceiver Receive Control Re
+ $f constant RX_CTRL_PDT_THRES \ Receiver Sensitivity Control
+ 14a $f bitmask: RX_CTRL.PDT_THRES \ Receiver Sensitivity Control
+$14b constant SFD_VALUE \ Start of Frame Delimiter Value
+ $ff constant SFD_VALUE_SFD_VALUE \ Start of Frame Delimiter Value
+ 14b $ff bitmask: SFD_VALUE.SFD_VALUE \ Start of Frame Delimiter Value
+$14c constant TRX_CTRL_2 \ Transceiver Control Register 2
+ $80 constant TRX_CTRL_2_RX_SAFE_MODE \ RX Safe Mode
+ 14c $80 bitmask: TRX_CTRL_2.RX_SAFE_MODE \ RX Safe Mode
+ $7c constant TRX_CTRL_2_Res \ Reserved
+ 14c $7c bitmask: TRX_CTRL_2.Res \ Reserved
+ $3 constant TRX_CTRL_2_OQPSK_DATA_RATE \ Data Rate Selection
+ 14c $3 bitmask: TRX_CTRL_2.OQPSK_DATA_RATE \ Data Rate Selection
+$14d constant ANT_DIV \ Antenna Diversity Control Regi
+ $80 constant ANT_DIV_ANT_SEL \ Antenna Diversity Antenna Stat
+ 14d $80 bitmask: ANT_DIV.ANT_SEL \ Antenna Diversity Antenna Stat
+ $70 constant ANT_DIV_Res \ Reserved
+ 14d $70 bitmask: ANT_DIV.Res \ Reserved
+ $8 constant ANT_DIV_ANT_DIV_EN \ Enable Antenna Diversity
+ 14d $8 bitmask: ANT_DIV.ANT_DIV_EN \ Enable Antenna Diversity
+ $4 constant ANT_DIV_ANT_EXT_SW_EN \ Enable External Antenna Switch
+ 14d $4 bitmask: ANT_DIV.ANT_EXT_SW_EN \ Enable External Antenna Switch
+ $3 constant ANT_DIV_ANT_CTRL \ Static Antenna Diversity Switc
+ 14d $3 bitmask: ANT_DIV.ANT_CTRL \ Static Antenna Diversity Switc
+$14e constant IRQ_MASK \ Transceiver Interrupt Enable R
+ $80 constant IRQ_MASK_AWAKE_EN \ Awake Interrupt Enable
+ 14e $80 bitmask: IRQ_MASK.AWAKE_EN \ Awake Interrupt Enable
+ $40 constant IRQ_MASK_TX_END_EN \ TX_END Interrupt Enable
+ 14e $40 bitmask: IRQ_MASK.TX_END_EN \ TX_END Interrupt Enable
+ $20 constant IRQ_MASK_AMI_EN \ Address Match Interrupt Enable
+ 14e $20 bitmask: IRQ_MASK.AMI_EN \ Address Match Interrupt Enable
+ $10 constant IRQ_MASK_CCA_ED_DONE_EN \ End of ED Measurement Interrup
+ 14e $10 bitmask: IRQ_MASK.CCA_ED_DONE_EN \ End of ED Measurement Interrup
+ $8 constant IRQ_MASK_RX_END_EN \ RX_END Interrupt Enable
+ 14e $8 bitmask: IRQ_MASK.RX_END_EN \ RX_END Interrupt Enable
+ $4 constant IRQ_MASK_RX_START_EN \ RX_START Interrupt Enable
+ 14e $4 bitmask: IRQ_MASK.RX_START_EN \ RX_START Interrupt Enable
+ $2 constant IRQ_MASK_PLL_UNLOCK_EN \ PLL Unlock Interrupt Enable
+ 14e $2 bitmask: IRQ_MASK.PLL_UNLOCK_EN \ PLL Unlock Interrupt Enable
+ $1 constant IRQ_MASK_PLL_LOCK_EN \ PLL Lock Interrupt Enable
+ 14e $1 bitmask: IRQ_MASK.PLL_LOCK_EN \ PLL Lock Interrupt Enable
+$14f constant IRQ_STATUS \ Transceiver Interrupt Status R
+ $80 constant IRQ_STATUS_AWAKE \ Awake Interrupt Status
+ 14f $80 bitmask: IRQ_STATUS.AWAKE \ Awake Interrupt Status
+ $40 constant IRQ_STATUS_TX_END \ TX_END Interrupt Status
+ 14f $40 bitmask: IRQ_STATUS.TX_END \ TX_END Interrupt Status
+ $20 constant IRQ_STATUS_AMI \ Address Match Interrupt Status
+ 14f $20 bitmask: IRQ_STATUS.AMI \ Address Match Interrupt Status
+ $10 constant IRQ_STATUS_CCA_ED_DONE \ End of ED Measurement Interrup
+ 14f $10 bitmask: IRQ_STATUS.CCA_ED_DONE \ End of ED Measurement Interrup
+ $8 constant IRQ_STATUS_RX_END \ RX_END Interrupt Status
+ 14f $8 bitmask: IRQ_STATUS.RX_END \ RX_END Interrupt Status
+ $4 constant IRQ_STATUS_RX_START \ RX_START Interrupt Status
+ 14f $4 bitmask: IRQ_STATUS.RX_START \ RX_START Interrupt Status
+ $2 constant IRQ_STATUS_PLL_UNLOCK \ PLL Unlock Interrupt Status
+ 14f $2 bitmask: IRQ_STATUS.PLL_UNLOCK \ PLL Unlock Interrupt Status
+ $1 constant IRQ_STATUS_PLL_LOCK \ PLL Lock Interrupt Status
+ 14f $1 bitmask: IRQ_STATUS.PLL_LOCK \ PLL Lock Interrupt Status
+$be constant IRQ_MASK1 \ Transceiver Interrupt Enable R
+ $e0 constant IRQ_MASK1_Res \ Reserved Bit
+ be $e0 bitmask: IRQ_MASK1.Res \ Reserved Bit
+ $10 constant IRQ_MASK1_MAF_3_AMI_EN \ Address Match Interrupt enable
+ be $10 bitmask: IRQ_MASK1.MAF_3_AMI_EN \ Address Match Interrupt enable
+ $8 constant IRQ_MASK1_MAF_2_AMI_EN \ Address Match Interrupt enable
+ be $8 bitmask: IRQ_MASK1.MAF_2_AMI_EN \ Address Match Interrupt enable
+ $4 constant IRQ_MASK1_MAF_1_AMI_EN \ Address Match Interrupt enable
+ be $4 bitmask: IRQ_MASK1.MAF_1_AMI_EN \ Address Match Interrupt enable
+ $2 constant IRQ_MASK1_MAF_0_AMI_EN \ Address Match Interrupt enable
+ be $2 bitmask: IRQ_MASK1.MAF_0_AMI_EN \ Address Match Interrupt enable
+ $1 constant IRQ_MASK1_TX_START_EN \ Transmit Start Interrupt enabl
+ be $1 bitmask: IRQ_MASK1.TX_START_EN \ Transmit Start Interrupt enabl
+$bf constant IRQ_STATUS1 \ Transceiver Interrupt Status R
+ $e0 constant IRQ_STATUS1_Res \ Reserved Bit
+ bf $e0 bitmask: IRQ_STATUS1.Res \ Reserved Bit
+ $10 constant IRQ_STATUS1_MAF_3_AMI \ Address Match Interrupt Status
+ bf $10 bitmask: IRQ_STATUS1.MAF_3_AMI \ Address Match Interrupt Status
+ $8 constant IRQ_STATUS1_MAF_2_AMI \ Address Match Interrupt Status
+ bf $8 bitmask: IRQ_STATUS1.MAF_2_AMI \ Address Match Interrupt Status
+ $4 constant IRQ_STATUS1_MAF_1_AMI \ Address Match Interrupt Status
+ bf $4 bitmask: IRQ_STATUS1.MAF_1_AMI \ Address Match Interrupt Status
+ $2 constant IRQ_STATUS1_MAF_0_AMI \ Address Match Interrupt Status
+ bf $2 bitmask: IRQ_STATUS1.MAF_0_AMI \ Address Match Interrupt Status
+ $1 constant IRQ_STATUS1_TX_START \ Transmit Start Interrupt Statu
+ bf $1 bitmask: IRQ_STATUS1.TX_START \ Transmit Start Interrupt Statu
+$150 constant VREG_CTRL \ Voltage Regulator Control and
+ $80 constant VREG_CTRL_AVREG_EXT \ Use External AVDD Regulator
+ 150 $80 bitmask: VREG_CTRL.AVREG_EXT \ Use External AVDD Regulator
+ $40 constant VREG_CTRL_AVDD_OK \ AVDD Supply Voltage Valid
+ 150 $40 bitmask: VREG_CTRL.AVDD_OK \ AVDD Supply Voltage Valid
+ $8 constant VREG_CTRL_DVREG_EXT \ Use External DVDD Regulator
+ 150 $8 bitmask: VREG_CTRL.DVREG_EXT \ Use External DVDD Regulator
+ $4 constant VREG_CTRL_DVDD_OK \ DVDD Supply Voltage Valid
+ 150 $4 bitmask: VREG_CTRL.DVDD_OK \ DVDD Supply Voltage Valid
+$151 constant BATMON \ Battery Monitor Control and St
+ $80 constant BATMON_BAT_LOW \ Battery Monitor Interrupt Stat
+ 151 $80 bitmask: BATMON.BAT_LOW \ Battery Monitor Interrupt Stat
+ $40 constant BATMON_BAT_LOW_EN \ Battery Monitor Interrupt Enab
+ 151 $40 bitmask: BATMON.BAT_LOW_EN \ Battery Monitor Interrupt Enab
+ $20 constant BATMON_BATMON_OK \ Battery Monitor Status
+ 151 $20 bitmask: BATMON.BATMON_OK \ Battery Monitor Status
+ $10 constant BATMON_BATMON_HR \ Battery Monitor Voltage Range
+ 151 $10 bitmask: BATMON.BATMON_HR \ Battery Monitor Voltage Range
+ $f constant BATMON_BATMON_VTH \ Battery Monitor Threshold Volt
+ 151 $f bitmask: BATMON.BATMON_VTH \ Battery Monitor Threshold Volt
+$152 constant XOSC_CTRL \ Crystal Oscillator Control Reg
+ $f0 constant XOSC_CTRL_XTAL_MODE \ Crystal Oscillator Operating M
+ 152 $f0 bitmask: XOSC_CTRL.XTAL_MODE \ Crystal Oscillator Operating M
+ $f constant XOSC_CTRL_XTAL_TRIM \ Crystal Oscillator Load Capaci
+ 152 $f bitmask: XOSC_CTRL.XTAL_TRIM \ Crystal Oscillator Load Capaci
+$153 constant CC_CTRL_0 \ Channel Control Register 0
+ $ff constant CC_CTRL_0_CC_NUMBER \ Channel Number
+ 153 $ff bitmask: CC_CTRL_0.CC_NUMBER \ Channel Number
+$154 constant CC_CTRL_1 \ Channel Control Register 1
+ $f constant CC_CTRL_1_CC_BAND \ Channel Band
+ 154 $f bitmask: CC_CTRL_1.CC_BAND \ Channel Band
+$155 constant RX_SYN \ Transceiver Receiver Sensitivi
+ $80 constant RX_SYN_RX_PDT_DIS \ Prevent Frame Reception
+ 155 $80 bitmask: RX_SYN.RX_PDT_DIS \ Prevent Frame Reception
+ $40 constant RX_SYN_RX_OVERRIDE \ Receiver Override Function
+ 155 $40 bitmask: RX_SYN.RX_OVERRIDE \ Receiver Override Function
+ $30 constant RX_SYN_Res \ Reserved
+ 155 $30 bitmask: RX_SYN.Res \ Reserved
+ $f constant RX_SYN_RX_PDT_LEVEL \ Reduce Receiver Sensitivity
+ 155 $f bitmask: RX_SYN.RX_PDT_LEVEL \ Reduce Receiver Sensitivity
+$156 constant TRX_RPC \ Transceiver Reduced Power Cons
+ $c0 constant TRX_RPC_RX_RPC_CTRL \ Smart Receiving Mode Timing
+ 156 $c0 bitmask: TRX_RPC.RX_RPC_CTRL \ Smart Receiving Mode Timing
+ $20 constant TRX_RPC_RX_RPC_EN \ Reciver Smart Receiving Mode E
+ 156 $20 bitmask: TRX_RPC.RX_RPC_EN \ Reciver Smart Receiving Mode E
+ $10 constant TRX_RPC_PDT_RPC_EN \ Smart Receiving Mode Reduced S
+ 156 $10 bitmask: TRX_RPC.PDT_RPC_EN \ Smart Receiving Mode Reduced S
+ $8 constant TRX_RPC_PLL_RPC_EN \ PLL Smart Receiving Mode Enabl
+ 156 $8 bitmask: TRX_RPC.PLL_RPC_EN \ PLL Smart Receiving Mode Enabl
+ $4 constant TRX_RPC_Res0 \ Reserved
+ 156 $4 bitmask: TRX_RPC.Res0 \ Reserved
+ $2 constant TRX_RPC_IPAN_RPC_EN \ Smart Receiving Mode IPAN Hand
+ 156 $2 bitmask: TRX_RPC.IPAN_RPC_EN \ Smart Receiving Mode IPAN Hand
+ $1 constant TRX_RPC_XAH_RPC_EN \ Smart Receiving in Extended Op
+ 156 $1 bitmask: TRX_RPC.XAH_RPC_EN \ Smart Receiving in Extended Op
+$157 constant XAH_CTRL_1 \ Transceiver Acknowledgment Fra
+ $c0 constant XAH_CTRL_1_Res \ Reserved Bit
+ 157 $c0 bitmask: XAH_CTRL_1.Res \ Reserved Bit
+ $20 constant XAH_CTRL_1_AACK_FLTR_RES_FT \ Filter Reserved Frames
+ 157 $20 bitmask: XAH_CTRL_1.AACK_FLTR_RES_FT \ Filter Reserved Frames
+ $10 constant XAH_CTRL_1_AACK_UPLD_RES_FT \ Process Reserved Frames
+ 157 $10 bitmask: XAH_CTRL_1.AACK_UPLD_RES_FT \ Process Reserved Frames
+ $8 constant XAH_CTRL_1_Res \ Reserved Bit
+ 157 $8 bitmask: XAH_CTRL_1.Res \ Reserved Bit
+ $4 constant XAH_CTRL_1_AACK_ACK_TIME \ Reduce Acknowledgment Time
+ 157 $4 bitmask: XAH_CTRL_1.AACK_ACK_TIME \ Reduce Acknowledgment Time
+ $2 constant XAH_CTRL_1_AACK_PROM_MODE \ Enable Promiscuous Mode
+ 157 $2 bitmask: XAH_CTRL_1.AACK_PROM_MODE \ Enable Promiscuous Mode
+ $1 constant XAH_CTRL_1_Res \ Reserved Bit
+ 157 $1 bitmask: XAH_CTRL_1.Res \ Reserved Bit
+$158 constant FTN_CTRL \ Transceiver Filter Tuning Cont
+ $80 constant FTN_CTRL_FTN_START \ Start Calibration Loop of Filt
+ 158 $80 bitmask: FTN_CTRL.FTN_START \ Start Calibration Loop of Filt
+$15a constant PLL_CF \ Transceiver Center Frequency C
+ $80 constant PLL_CF_PLL_CF_START \ Start Center Frequency Calibra
+ 15a $80 bitmask: PLL_CF.PLL_CF_START \ Start Center Frequency Calibra
+$15b constant PLL_DCU \ Transceiver Delay Cell Calibra
+ $80 constant PLL_DCU_PLL_DCU_START \ Start Delay Cell Calibration
+ 15b $80 bitmask: PLL_DCU.PLL_DCU_START \ Start Delay Cell Calibration
+$15c constant PART_NUM \ Device Identification Register
+ $ff constant PART_NUM_PART_NUM \ Part Number
+ 15c $ff bitmask: PART_NUM.PART_NUM \ Part Number
+$15d constant VERSION_NUM \ Device Identification Register
+ $ff constant VERSION_NUM_VERSION_NUM \ Version Number
+ 15d $ff bitmask: VERSION_NUM.VERSION_NUM \ Version Number
+$15e constant MAN_ID_0 \ Device Identification Register
+ $80 constant MAN_ID_0_MAN_ID_07 \ Manufacturer ID (Low Byte)
+ 15e $80 bitmask: MAN_ID_0.MAN_ID_07 \ Manufacturer ID (Low Byte)
+ $40 constant MAN_ID_0_MAN_ID_06 \ Manufacturer ID (Low Byte)
+ 15e $40 bitmask: MAN_ID_0.MAN_ID_06 \ Manufacturer ID (Low Byte)
+ $20 constant MAN_ID_0_MAN_ID_05 \ Manufacturer ID (Low Byte)
+ 15e $20 bitmask: MAN_ID_0.MAN_ID_05 \ Manufacturer ID (Low Byte)
+ $10 constant MAN_ID_0_MAN_ID_04 \ Manufacturer ID (Low Byte)
+ 15e $10 bitmask: MAN_ID_0.MAN_ID_04 \ Manufacturer ID (Low Byte)
+ $8 constant MAN_ID_0_MAN_ID_03 \ Manufacturer ID (Low Byte)
+ 15e $8 bitmask: MAN_ID_0.MAN_ID_03 \ Manufacturer ID (Low Byte)
+ $4 constant MAN_ID_0_MAN_ID_02 \ Manufacturer ID (Low Byte)
+ 15e $4 bitmask: MAN_ID_0.MAN_ID_02 \ Manufacturer ID (Low Byte)
+ $2 constant MAN_ID_0_MAN_ID_01 \ Manufacturer ID (Low Byte)
+ 15e $2 bitmask: MAN_ID_0.MAN_ID_01 \ Manufacturer ID (Low Byte)
+ $1 constant MAN_ID_0_MAN_ID_00 \ Manufacturer ID (Low Byte)
+ 15e $1 bitmask: MAN_ID_0.MAN_ID_00 \ Manufacturer ID (Low Byte)
+$15f constant MAN_ID_1 \ Device Identification Register
+ $ff constant MAN_ID_1_MAN_ID_ \ Manufacturer ID (High Byte)
+ 15f $ff bitmask: MAN_ID_1.MAN_ID_ \ Manufacturer ID (High Byte)
+$160 constant SHORT_ADDR_0 \ Transceiver MAC Short Address
+ $80 constant SHORT_ADDR_0_SHORT_ADDR_07 \ MAC Short Address
+ 160 $80 bitmask: SHORT_ADDR_0.SHORT_ADDR_07 \ MAC Short Address
+ $40 constant SHORT_ADDR_0_SHORT_ADDR_06 \ MAC Short Address
+ 160 $40 bitmask: SHORT_ADDR_0.SHORT_ADDR_06 \ MAC Short Address
+ $20 constant SHORT_ADDR_0_SHORT_ADDR_05 \ MAC Short Address
+ 160 $20 bitmask: SHORT_ADDR_0.SHORT_ADDR_05 \ MAC Short Address
+ $10 constant SHORT_ADDR_0_SHORT_ADDR_04 \ MAC Short Address
+ 160 $10 bitmask: SHORT_ADDR_0.SHORT_ADDR_04 \ MAC Short Address
+ $8 constant SHORT_ADDR_0_SHORT_ADDR_03 \ MAC Short Address
+ 160 $8 bitmask: SHORT_ADDR_0.SHORT_ADDR_03 \ MAC Short Address
+ $4 constant SHORT_ADDR_0_SHORT_ADDR_02 \ MAC Short Address
+ 160 $4 bitmask: SHORT_ADDR_0.SHORT_ADDR_02 \ MAC Short Address
+ $2 constant SHORT_ADDR_0_SHORT_ADDR_01 \ MAC Short Address
+ 160 $2 bitmask: SHORT_ADDR_0.SHORT_ADDR_01 \ MAC Short Address
+ $1 constant SHORT_ADDR_0_SHORT_ADDR_00 \ MAC Short Address
+ 160 $1 bitmask: SHORT_ADDR_0.SHORT_ADDR_00 \ MAC Short Address
+$161 constant SHORT_ADDR_1 \ Transceiver MAC Short Address
+ $ff constant SHORT_ADDR_1_SHORT_ADDR_ \ MAC Short Address
+ 161 $ff bitmask: SHORT_ADDR_1.SHORT_ADDR_ \ MAC Short Address
+$162 constant PAN_ID_0 \ Transceiver Personal Area Netw
+ $80 constant PAN_ID_0_PAN_ID_07 \ MAC Personal Area Network ID
+ 162 $80 bitmask: PAN_ID_0.PAN_ID_07 \ MAC Personal Area Network ID
+ $40 constant PAN_ID_0_PAN_ID_06 \ MAC Personal Area Network ID
+ 162 $40 bitmask: PAN_ID_0.PAN_ID_06 \ MAC Personal Area Network ID
+ $20 constant PAN_ID_0_PAN_ID_05 \ MAC Personal Area Network ID
+ 162 $20 bitmask: PAN_ID_0.PAN_ID_05 \ MAC Personal Area Network ID
+ $10 constant PAN_ID_0_PAN_ID_04 \ MAC Personal Area Network ID
+ 162 $10 bitmask: PAN_ID_0.PAN_ID_04 \ MAC Personal Area Network ID
+ $8 constant PAN_ID_0_PAN_ID_03 \ MAC Personal Area Network ID
+ 162 $8 bitmask: PAN_ID_0.PAN_ID_03 \ MAC Personal Area Network ID
+ $4 constant PAN_ID_0_PAN_ID_02 \ MAC Personal Area Network ID
+ 162 $4 bitmask: PAN_ID_0.PAN_ID_02 \ MAC Personal Area Network ID
+ $2 constant PAN_ID_0_PAN_ID_01 \ MAC Personal Area Network ID
+ 162 $2 bitmask: PAN_ID_0.PAN_ID_01 \ MAC Personal Area Network ID
+ $1 constant PAN_ID_0_PAN_ID_00 \ MAC Personal Area Network ID
+ 162 $1 bitmask: PAN_ID_0.PAN_ID_00 \ MAC Personal Area Network ID
+$163 constant PAN_ID_1 \ Transceiver Personal Area Netw
+ $ff constant PAN_ID_1_PAN_ID_ \ MAC Personal Area Network ID
+ 163 $ff bitmask: PAN_ID_1.PAN_ID_ \ MAC Personal Area Network ID
+$164 constant IEEE_ADDR_0 \ Transceiver MAC IEEE Address R
+ $80 constant IEEE_ADDR_0_IEEE_ADDR_07 \ MAC IEEE Address
+ 164 $80 bitmask: IEEE_ADDR_0.IEEE_ADDR_07 \ MAC IEEE Address
+ $40 constant IEEE_ADDR_0_IEEE_ADDR_06 \ MAC IEEE Address
+ 164 $40 bitmask: IEEE_ADDR_0.IEEE_ADDR_06 \ MAC IEEE Address
+ $20 constant IEEE_ADDR_0_IEEE_ADDR_05 \ MAC IEEE Address
+ 164 $20 bitmask: IEEE_ADDR_0.IEEE_ADDR_05 \ MAC IEEE Address
+ $10 constant IEEE_ADDR_0_IEEE_ADDR_04 \ MAC IEEE Address
+ 164 $10 bitmask: IEEE_ADDR_0.IEEE_ADDR_04 \ MAC IEEE Address
+ $8 constant IEEE_ADDR_0_IEEE_ADDR_03 \ MAC IEEE Address
+ 164 $8 bitmask: IEEE_ADDR_0.IEEE_ADDR_03 \ MAC IEEE Address
+ $4 constant IEEE_ADDR_0_IEEE_ADDR_02 \ MAC IEEE Address
+ 164 $4 bitmask: IEEE_ADDR_0.IEEE_ADDR_02 \ MAC IEEE Address
+ $2 constant IEEE_ADDR_0_IEEE_ADDR_01 \ MAC IEEE Address
+ 164 $2 bitmask: IEEE_ADDR_0.IEEE_ADDR_01 \ MAC IEEE Address
+ $1 constant IEEE_ADDR_0_IEEE_ADDR_00 \ MAC IEEE Address
+ 164 $1 bitmask: IEEE_ADDR_0.IEEE_ADDR_00 \ MAC IEEE Address
+$165 constant IEEE_ADDR_1 \ Transceiver MAC IEEE Address R
+ $ff constant IEEE_ADDR_1_IEEE_ADDR_ \ MAC IEEE Address
+ 165 $ff bitmask: IEEE_ADDR_1.IEEE_ADDR_ \ MAC IEEE Address
+$166 constant IEEE_ADDR_2 \ Transceiver MAC IEEE Address R
+ $ff constant IEEE_ADDR_2_IEEE_ADDR_ \ MAC IEEE Address
+ 166 $ff bitmask: IEEE_ADDR_2.IEEE_ADDR_ \ MAC IEEE Address
+$167 constant IEEE_ADDR_3 \ Transceiver MAC IEEE Address R
+ $ff constant IEEE_ADDR_3_IEEE_ADDR_ \ MAC IEEE Address
+ 167 $ff bitmask: IEEE_ADDR_3.IEEE_ADDR_ \ MAC IEEE Address
+$168 constant IEEE_ADDR_4 \ Transceiver MAC IEEE Address R
+ $ff constant IEEE_ADDR_4_IEEE_ADDR_ \ MAC IEEE Address
+ 168 $ff bitmask: IEEE_ADDR_4.IEEE_ADDR_ \ MAC IEEE Address
+$169 constant IEEE_ADDR_5 \ Transceiver MAC IEEE Address R
+ $ff constant IEEE_ADDR_5_IEEE_ADDR_ \ MAC IEEE Address
+ 169 $ff bitmask: IEEE_ADDR_5.IEEE_ADDR_ \ MAC IEEE Address
+$16a constant IEEE_ADDR_6 \ Transceiver MAC IEEE Address R
+ $ff constant IEEE_ADDR_6_IEEE_ADDR_ \ MAC IEEE Address
+ 16a $ff bitmask: IEEE_ADDR_6.IEEE_ADDR_ \ MAC IEEE Address
+$16b constant IEEE_ADDR_7 \ Transceiver MAC IEEE Address R
+ $ff constant IEEE_ADDR_7_IEEE_ADDR_ \ MAC IEEE Address
+ 16b $ff bitmask: IEEE_ADDR_7.IEEE_ADDR_ \ MAC IEEE Address
+$16c constant XAH_CTRL_0 \ Transceiver Extended Operating
+ $f0 constant XAH_CTRL_0_MAX_FRAME_RETRIES \ Maximum Number of Frame Re-tra
+ 16c $f0 bitmask: XAH_CTRL_0.MAX_FRAME_RETRIES \ Maximum Number of Frame Re-tra
+ $e constant XAH_CTRL_0_MAX_CSMA_RETRIES \ Maximum Number of CSMA-CA Proc
+ 16c $e bitmask: XAH_CTRL_0.MAX_CSMA_RETRIES \ Maximum Number of CSMA-CA Proc
+ $1 constant XAH_CTRL_0_SLOTTED_OPERATION \ Set Slotted Acknowledgment
+ 16c $1 bitmask: XAH_CTRL_0.SLOTTED_OPERATION \ Set Slotted Acknowledgment
+$16d constant CSMA_SEED_0 \ Transceiver CSMA-CA Random Num
+ $80 constant CSMA_SEED_0_CSMA_SEED_07 \ Seed Value for CSMA Random Num
+ 16d $80 bitmask: CSMA_SEED_0.CSMA_SEED_07 \ Seed Value for CSMA Random Num
+ $40 constant CSMA_SEED_0_CSMA_SEED_06 \ Seed Value for CSMA Random Num
+ 16d $40 bitmask: CSMA_SEED_0.CSMA_SEED_06 \ Seed Value for CSMA Random Num
+ $20 constant CSMA_SEED_0_CSMA_SEED_05 \ Seed Value for CSMA Random Num
+ 16d $20 bitmask: CSMA_SEED_0.CSMA_SEED_05 \ Seed Value for CSMA Random Num
+ $10 constant CSMA_SEED_0_CSMA_SEED_04 \ Seed Value for CSMA Random Num
+ 16d $10 bitmask: CSMA_SEED_0.CSMA_SEED_04 \ Seed Value for CSMA Random Num
+ $8 constant CSMA_SEED_0_CSMA_SEED_03 \ Seed Value for CSMA Random Num
+ 16d $8 bitmask: CSMA_SEED_0.CSMA_SEED_03 \ Seed Value for CSMA Random Num
+ $4 constant CSMA_SEED_0_CSMA_SEED_02 \ Seed Value for CSMA Random Num
+ 16d $4 bitmask: CSMA_SEED_0.CSMA_SEED_02 \ Seed Value for CSMA Random Num
+ $2 constant CSMA_SEED_0_CSMA_SEED_01 \ Seed Value for CSMA Random Num
+ 16d $2 bitmask: CSMA_SEED_0.CSMA_SEED_01 \ Seed Value for CSMA Random Num
+ $1 constant CSMA_SEED_0_CSMA_SEED_00 \ Seed Value for CSMA Random Num
+ 16d $1 bitmask: CSMA_SEED_0.CSMA_SEED_00 \ Seed Value for CSMA Random Num
+$16e constant CSMA_SEED_1 \ Transceiver Acknowledgment Fra
+ $c0 constant CSMA_SEED_1_AACK_FVN_MODE \ Acknowledgment Frame Filter Mo
+ 16e $c0 bitmask: CSMA_SEED_1.AACK_FVN_MODE \ Acknowledgment Frame Filter Mo
+ $20 constant CSMA_SEED_1_AACK_SET_PD \ Set Frame Pending Sub-field
+ 16e $20 bitmask: CSMA_SEED_1.AACK_SET_PD \ Set Frame Pending Sub-field
+ $10 constant CSMA_SEED_1_AACK_DIS_ACK \ Disable Acknowledgment Frame T
+ 16e $10 bitmask: CSMA_SEED_1.AACK_DIS_ACK \ Disable Acknowledgment Frame T
+ $8 constant CSMA_SEED_1_AACK_I_AM_COORD \ Set Personal Area Network Coor
+ 16e $8 bitmask: CSMA_SEED_1.AACK_I_AM_COORD \ Set Personal Area Network Coor
+ $7 constant CSMA_SEED_1_CSMA_SEED_1 \ Seed Value for CSMA Random Num
+ 16e $7 bitmask: CSMA_SEED_1.CSMA_SEED_1 \ Seed Value for CSMA Random Num
+$16f constant CSMA_BE \ Transceiver CSMA-CA Back-off E
+ $f0 constant CSMA_BE_MAX_BE \ Maximum Back-off Exponent
+ 16f $f0 bitmask: CSMA_BE.MAX_BE \ Maximum Back-off Exponent
+ $f constant CSMA_BE_MIN_BE \ Minimum Back-off Exponent
+ 16f $f bitmask: CSMA_BE.MIN_BE \ Minimum Back-off Exponent
+$176 constant TST_CTRL_DIGI \ Transceiver Digital Test Contr
+ $f constant TST_CTRL_DIGI_TST_CTRL_DIG \ Digital Test Controller Regist
+ 176 $f bitmask: TST_CTRL_DIGI.TST_CTRL_DIG \ Digital Test Controller Regist
+$17b constant TST_RX_LENGTH \ Transceiver Received Frame Len
+ $ff constant TST_RX_LENGTH_RX_LENGTH \ Received Frame Length
+ 17b $ff bitmask: TST_RX_LENGTH.RX_LENGTH \ Received Frame Length
+$180 constant TRXFBST \ Start of frame buffer
+$1ff constant TRXFBEND \ End of frame buffer
+\ SYMCNT
+$fc constant SCTSTRHH \ Symbol Counter Transmit Frame
+ $ff constant SCTSTRHH_SCTSTRHH \ Symbol Counter Transmit Frame
+ fc $ff bitmask: SCTSTRHH.SCTSTRHH \ Symbol Counter Transmit Frame
+$fb constant SCTSTRHL \ Symbol Counter Transmit Frame
+ $ff constant SCTSTRHL_SCTSTRHL \ Symbol Counter Transmit Frame
+ fb $ff bitmask: SCTSTRHL.SCTSTRHL \ Symbol Counter Transmit Frame
+$fa constant SCTSTRLH \ Symbol Counter Transmit Frame
+ $ff constant SCTSTRLH_SCTSTRLH \ Symbol Counter Transmit Frame
+ fa $ff bitmask: SCTSTRLH.SCTSTRLH \ Symbol Counter Transmit Frame
+$f9 constant SCTSTRLL \ Symbol Counter Transmit Frame
+ $ff constant SCTSTRLL_SCTSTRLL \ Symbol Counter Transmit Frame
+ f9 $ff bitmask: SCTSTRLL.SCTSTRLL \ Symbol Counter Transmit Frame
+$f8 constant SCOCR1HH \ Symbol Counter Output Compare
+ $ff constant SCOCR1HH_SCOCR1HH \ Symbol Counter Output Compare
+ f8 $ff bitmask: SCOCR1HH.SCOCR1HH \ Symbol Counter Output Compare
+$f7 constant SCOCR1HL \ Symbol Counter Output Compare
+ $ff constant SCOCR1HL_SCOCR1HL \ Symbol Counter Output Compare
+ f7 $ff bitmask: SCOCR1HL.SCOCR1HL \ Symbol Counter Output Compare
+$f6 constant SCOCR1LH \ Symbol Counter Output Compare
+ $ff constant SCOCR1LH_SCOCR1LH \ Symbol Counter Output Compare
+ f6 $ff bitmask: SCOCR1LH.SCOCR1LH \ Symbol Counter Output Compare
+$f5 constant SCOCR1LL \ Symbol Counter Output Compare
+ $ff constant SCOCR1LL_SCOCR1LL \ Symbol Counter Output Compare
+ f5 $ff bitmask: SCOCR1LL.SCOCR1LL \ Symbol Counter Output Compare
+$f4 constant SCOCR2HH \ Symbol Counter Output Compare
+ $ff constant SCOCR2HH_SCOCR2HH \ Symbol Counter Output Compare
+ f4 $ff bitmask: SCOCR2HH.SCOCR2HH \ Symbol Counter Output Compare
+$f3 constant SCOCR2HL \ Symbol Counter Output Compare
+ $ff constant SCOCR2HL_SCOCR2HL \ Symbol Counter Output Compare
+ f3 $ff bitmask: SCOCR2HL.SCOCR2HL \ Symbol Counter Output Compare
+$f2 constant SCOCR2LH \ Symbol Counter Output Compare
+ $ff constant SCOCR2LH_SCOCR2LH \ Symbol Counter Output Compare
+ f2 $ff bitmask: SCOCR2LH.SCOCR2LH \ Symbol Counter Output Compare
+$f1 constant SCOCR2LL \ Symbol Counter Output Compare
+ $ff constant SCOCR2LL_SCOCR2LL \ Symbol Counter Output Compare
+ f1 $ff bitmask: SCOCR2LL.SCOCR2LL \ Symbol Counter Output Compare
+$f0 constant SCOCR3HH \ Symbol Counter Output Compare
+ $ff constant SCOCR3HH_SCOCR3HH \ Symbol Counter Output Compare
+ f0 $ff bitmask: SCOCR3HH.SCOCR3HH \ Symbol Counter Output Compare
+$ef constant SCOCR3HL \ Symbol Counter Output Compare
+ $ff constant SCOCR3HL_SCOCR3HL \ Symbol Counter Output Compare
+ ef $ff bitmask: SCOCR3HL.SCOCR3HL \ Symbol Counter Output Compare
+$ee constant SCOCR3LH \ Symbol Counter Output Compare
+ $ff constant SCOCR3LH_SCOCR3LH \ Symbol Counter Output Compare
+ ee $ff bitmask: SCOCR3LH.SCOCR3LH \ Symbol Counter Output Compare
+$ed constant SCOCR3LL \ Symbol Counter Output Compare
+ $ff constant SCOCR3LL_SCOCR3LL \ Symbol Counter Output Compare
+ ed $ff bitmask: SCOCR3LL.SCOCR3LL \ Symbol Counter Output Compare
+$ec constant SCTSRHH \ Symbol Counter Frame Timestamp
+ $ff constant SCTSRHH_SCTSRHH \ Symbol Counter Frame Timestamp
+ ec $ff bitmask: SCTSRHH.SCTSRHH \ Symbol Counter Frame Timestamp
+$eb constant SCTSRHL \ Symbol Counter Frame Timestamp
+ $ff constant SCTSRHL_SCTSRHL \ Symbol Counter Frame Timestamp
+ eb $ff bitmask: SCTSRHL.SCTSRHL \ Symbol Counter Frame Timestamp
+$ea constant SCTSRLH \ Symbol Counter Frame Timestamp
+ $ff constant SCTSRLH_SCTSRLH \ Symbol Counter Frame Timestamp
+ ea $ff bitmask: SCTSRLH.SCTSRLH \ Symbol Counter Frame Timestamp
+$e9 constant SCTSRLL \ Symbol Counter Frame Timestamp
+ $ff constant SCTSRLL_SCTSRLL \ Symbol Counter Frame Timestamp
+ e9 $ff bitmask: SCTSRLL.SCTSRLL \ Symbol Counter Frame Timestamp
+$e8 constant SCBTSRHH \ Symbol Counter Beacon Timestam
+ $ff constant SCBTSRHH_SCBTSRHH \ Symbol Counter Beacon Timestam
+ e8 $ff bitmask: SCBTSRHH.SCBTSRHH \ Symbol Counter Beacon Timestam
+$e7 constant SCBTSRHL \ Symbol Counter Beacon Timestam
+ $ff constant SCBTSRHL_SCBTSRHL \ Symbol Counter Beacon Timestam
+ e7 $ff bitmask: SCBTSRHL.SCBTSRHL \ Symbol Counter Beacon Timestam
+$e6 constant SCBTSRLH \ Symbol Counter Beacon Timestam
+ $ff constant SCBTSRLH_SCBTSRLH \ Symbol Counter Beacon Timestam
+ e6 $ff bitmask: SCBTSRLH.SCBTSRLH \ Symbol Counter Beacon Timestam
+$e5 constant SCBTSRLL \ Symbol Counter Beacon Timestam
+ $ff constant SCBTSRLL_SCBTSRLL \ Symbol Counter Beacon Timestam
+ e5 $ff bitmask: SCBTSRLL.SCBTSRLL \ Symbol Counter Beacon Timestam
+$e4 constant SCCNTHH \ Symbol Counter Register HH-Byt
+ $ff constant SCCNTHH_SCCNTHH \ Symbol Counter Register HH-Byt
+ e4 $ff bitmask: SCCNTHH.SCCNTHH \ Symbol Counter Register HH-Byt
+$e3 constant SCCNTHL \ Symbol Counter Register HL-Byt
+ $ff constant SCCNTHL_SCCNTHL \ Symbol Counter Register HL-Byt
+ e3 $ff bitmask: SCCNTHL.SCCNTHL \ Symbol Counter Register HL-Byt
+$e2 constant SCCNTLH \ Symbol Counter Register LH-Byt
+ $ff constant SCCNTLH_SCCNTLH \ Symbol Counter Register LH-Byt
+ e2 $ff bitmask: SCCNTLH.SCCNTLH \ Symbol Counter Register LH-Byt
+$e1 constant SCCNTLL \ Symbol Counter Register LL-Byt
+ $ff constant SCCNTLL_SCCNTLL \ Symbol Counter Register LL-Byt
+ e1 $ff bitmask: SCCNTLL.SCCNTLL \ Symbol Counter Register LL-Byt
+$e0 constant SCIRQS \ Symbol Counter Interrupt Statu
+ $e0 constant SCIRQS_Res \ Reserved Bit
+ e0 $e0 bitmask: SCIRQS.Res \ Reserved Bit
+ $10 constant SCIRQS_IRQSBO \ Backoff Slot Counter IRQ
+ e0 $10 bitmask: SCIRQS.IRQSBO \ Backoff Slot Counter IRQ
+ $8 constant SCIRQS_IRQSOF \ Symbol Counter Overflow IRQ
+ e0 $8 bitmask: SCIRQS.IRQSOF \ Symbol Counter Overflow IRQ
+ $7 constant SCIRQS_IRQSCP \ Compare Unit 3 Compare Match I
+ e0 $7 bitmask: SCIRQS.IRQSCP \ Compare Unit 3 Compare Match I
+$df constant SCIRQM \ Symbol Counter Interrupt Mask
+ $e0 constant SCIRQM_Res \ Reserved Bit
+ df $e0 bitmask: SCIRQM.Res \ Reserved Bit
+ $10 constant SCIRQM_IRQMBO \ Backoff Slot Counter IRQ enabl
+ df $10 bitmask: SCIRQM.IRQMBO \ Backoff Slot Counter IRQ enabl
+ $8 constant SCIRQM_IRQMOF \ Symbol Counter Overflow IRQ en
+ df $8 bitmask: SCIRQM.IRQMOF \ Symbol Counter Overflow IRQ en
+ $7 constant SCIRQM_IRQMCP \ Symbol Counter Compare Match 3
+ df $7 bitmask: SCIRQM.IRQMCP \ Symbol Counter Compare Match 3
+$de constant SCSR \ Symbol Counter Status Register
+ $fe constant SCSR_Res \ Reserved Bit
+ de $fe bitmask: SCSR.Res \ Reserved Bit
+ $1 constant SCSR_SCBSY \ Symbol Counter busy
+ de $1 bitmask: SCSR.SCBSY \ Symbol Counter busy
+$dd constant SCCR1 \ Symbol Counter Control Registe
+ $c0 constant SCCR1_Res \ Reserved Bit
+ dd $c0 bitmask: SCCR1.Res \ Reserved Bit
+ $20 constant SCCR1_SCBTSM \ Symbol Counter Beacon Timestam
+ dd $20 bitmask: SCCR1.SCBTSM \ Symbol Counter Beacon Timestam
+ $1c constant SCCR1_SCCKDIV \ Clock divider for synchronous
+ dd $1c bitmask: SCCR1.SCCKDIV \ Clock divider for synchronous
+ $2 constant SCCR1_SCEECLK \ Enable External Clock Source o
+ dd $2 bitmask: SCCR1.SCEECLK \ Enable External Clock Source o
+ $1 constant SCCR1_SCENBO \ Backoff Slot Counter enable
+ dd $1 bitmask: SCCR1.SCENBO \ Backoff Slot Counter enable
+$dc constant SCCR0 \ Symbol Counter Control Registe
+ $80 constant SCCR0_SCRES \ Symbol Counter Synchronization
+ dc $80 bitmask: SCCR0.SCRES \ Symbol Counter Synchronization
+ $40 constant SCCR0_SCMBTS \ Manual Beacon Timestamp
+ dc $40 bitmask: SCCR0.SCMBTS \ Manual Beacon Timestamp
+ $20 constant SCCR0_SCEN \ Symbol Counter enable
+ dc $20 bitmask: SCCR0.SCEN \ Symbol Counter enable
+ $10 constant SCCR0_SCCKSEL \ Symbol Counter Clock Source se
+ dc $10 bitmask: SCCR0.SCCKSEL \ Symbol Counter Clock Source se
+ $8 constant SCCR0_SCTSE \ Symbol Counter Automatic Times
+ dc $8 bitmask: SCCR0.SCTSE \ Symbol Counter Automatic Times
+ $7 constant SCCR0_SCCMP \ Symbol Counter Compare Unit 3
+ dc $7 bitmask: SCCR0.SCCMP \ Symbol Counter Compare Unit 3
+$db constant SCCSR \ Symbol Counter Compare Source
+ $c0 constant SCCSR_Res \ Reserved Bit
+ db $c0 bitmask: SCCSR.Res \ Reserved Bit
+ $30 constant SCCSR_SCCS3 \ Symbol Counter Compare Source
+ db $30 bitmask: SCCSR.SCCS3 \ Symbol Counter Compare Source
+ $c constant SCCSR_SCCS2 \ Symbol Counter Compare Source
+ db $c bitmask: SCCSR.SCCS2 \ Symbol Counter Compare Source
+ $3 constant SCCSR_SCCS1 \ Symbol Counter Compare Source
+ db $3 bitmask: SCCSR.SCCS1 \ Symbol Counter Compare Source
+$da constant SCRSTRHH \ Symbol Counter Received Frame
+ $ff constant SCRSTRHH_SCRSTRHH \ Symbol Counter Received Frame
+ da $ff bitmask: SCRSTRHH.SCRSTRHH \ Symbol Counter Received Frame
+$d9 constant SCRSTRHL \ Symbol Counter Received Frame
+ $ff constant SCRSTRHL_SCRSTRHL \ Symbol Counter Received Frame
+ d9 $ff bitmask: SCRSTRHL.SCRSTRHL \ Symbol Counter Received Frame
+$d8 constant SCRSTRLH \ Symbol Counter Received Frame
+ $ff constant SCRSTRLH_SCRSTRLH \ Symbol Counter Received Frame
+ d8 $ff bitmask: SCRSTRLH.SCRSTRLH \ Symbol Counter Received Frame
+$d7 constant SCRSTRLL \ Symbol Counter Received Frame
+ $ff constant SCRSTRLL_SCRSTRLL \ Symbol Counter Received Frame
+ d7 $ff bitmask: SCRSTRLL.SCRSTRLL \ Symbol Counter Received Frame
+\ EEPROM
+$41 constant EEAR \ EEPROM Address Register Bytes
+$40 constant EEDR \ EEPROM Data Register
+$3f constant EECR \ EEPROM Control Register
+ $c0 constant EECR_Res \ Reserved
+ 3f $c0 bitmask: EECR.Res \ Reserved
+ $30 constant EECR_EEPM \ EEPROM Programming Mode
+ 3f $30 bitmask: EECR.EEPM \ EEPROM Programming Mode
+ $8 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
+ 3f $8 bitmask: EECR.EERIE \ EEPROM Ready Interrupt Enable
+ $4 constant EECR_EEMPE \ EEPROM Master Write Enable
+ 3f $4 bitmask: EECR.EEMPE \ EEPROM Master Write Enable
+ $2 constant EECR_EEPE \ EEPROM Programming Enable
+ 3f $2 bitmask: EECR.EEPE \ EEPROM Programming Enable
+ $1 constant EECR_EERE \ EEPROM Read Enable
+ 3f $1 bitmask: EECR.EERE \ EEPROM Read Enable
+\ JTAG
+$51 constant OCDR \ On-Chip Debug Register
+ $ff constant OCDR_OCDR \ On-Chip Debug Register Data
+ 51 $ff bitmask: OCDR.OCDR \ On-Chip Debug Register Data
+$55 constant MCUCR \ MCU Control Register
+ $80 constant MCUCR_JTD \ JTAG Interface Disable
+ 55 $80 bitmask: MCUCR.JTD \ JTAG Interface Disable
+$54 constant MCUSR \ MCU Status Register
+ $10 constant MCUSR_JTRF \ JTAG Reset Flag
+ 54 $10 bitmask: MCUSR.JTRF \ JTAG Reset Flag
+\ EXTERNAL_INTERRUPT
+$69 constant EICRA \ External Interrupt Control Reg
+ $c0 constant EICRA_ISC3 \ External Interrupt 3 Sense Con
+ 69 $c0 bitmask: EICRA.ISC3 \ External Interrupt 3 Sense Con
+ $30 constant EICRA_ISC2 \ External Interrupt 2 Sense Con
+ 69 $30 bitmask: EICRA.ISC2 \ External Interrupt 2 Sense Con
+ $c constant EICRA_ISC1 \ External Interrupt 1 Sense Con
+ 69 $c bitmask: EICRA.ISC1 \ External Interrupt 1 Sense Con
+ $3 constant EICRA_ISC0 \ External Interrupt 0 Sense Con
+ 69 $3 bitmask: EICRA.ISC0 \ External Interrupt 0 Sense Con
+$6a constant EICRB \ External Interrupt Control Reg
+ $c0 constant EICRB_ISC7 \ External Interrupt 7 Sense Con
+ 6a $c0 bitmask: EICRB.ISC7 \ External Interrupt 7 Sense Con
+ $30 constant EICRB_ISC6 \ External Interrupt 6 Sense Con
+ 6a $30 bitmask: EICRB.ISC6 \ External Interrupt 6 Sense Con
+ $c constant EICRB_ISC5 \ External Interrupt 5 Sense Con
+ 6a $c bitmask: EICRB.ISC5 \ External Interrupt 5 Sense Con
+ $3 constant EICRB_ISC4 \ External Interrupt 4 Sense Con
+ 6a $3 bitmask: EICRB.ISC4 \ External Interrupt 4 Sense Con
+$3d constant EIMSK \ External Interrupt Mask Regist
+ $ff constant EIMSK_INT \ External Interrupt Request Ena
+ 3d $ff bitmask: EIMSK.INT \ External Interrupt Request Ena
+$3c constant EIFR \ External Interrupt Flag Regist
+ $ff constant EIFR_INTF \ External Interrupt Flag
+ 3c $ff bitmask: EIFR.INTF \ External Interrupt Flag
+$6d constant PCMSK2 \ Pin Change Mask Register 2
+ $ff constant PCMSK2_PCINT \ Pin Change Enable Mask
+ 6d $ff bitmask: PCMSK2.PCINT \ Pin Change Enable Mask
+$6c constant PCMSK1 \ Pin Change Mask Register 1
+ $ff constant PCMSK1_PCINT \ Pin Change Enable Mask
+ 6c $ff bitmask: PCMSK1.PCINT \ Pin Change Enable Mask
+$6b constant PCMSK0 \ Pin Change Mask Register 0
+$3b constant PCIFR \ Pin Change Interrupt Flag Regi
+ $f8 constant PCIFR_Res \ Reserved Bit
+ 3b $f8 bitmask: PCIFR.Res \ Reserved Bit
+ $7 constant PCIFR_PCIF \ Pin Change Interrupt Flags
+ 3b $7 bitmask: PCIFR.PCIF \ Pin Change Interrupt Flags
+$68 constant PCICR \ Pin Change Interrupt Control R
+ $f8 constant PCICR_Res \ Reserved Bit
+ 68 $f8 bitmask: PCICR.Res \ Reserved Bit
+ $7 constant PCICR_PCIE \ Pin Change Interrupt Enables
+ 68 $7 bitmask: PCICR.PCIE \ Pin Change Interrupt Enables
+\ AD_CONVERTER
+$7c constant ADMUX \ The ADC Multiplexer Selection
+ $c0 constant ADMUX_REFS \ Reference Selection Bits
+ 7c $c0 bitmask: ADMUX.REFS \ Reference Selection Bits
+ $20 constant ADMUX_ADLAR \ ADC Left Adjust Result
+ 7c $20 bitmask: ADMUX.ADLAR \ ADC Left Adjust Result
+ $1f constant ADMUX_MUX \ Analog Channel and Gain Select
+ 7c $1f bitmask: ADMUX.MUX \ Analog Channel and Gain Select
+$78 constant ADC \ ADC Data Register Bytes
+$7a constant ADCSRA \ The ADC Control and Status Reg
+ $80 constant ADCSRA_ADEN \ ADC Enable
+ 7a $80 bitmask: ADCSRA.ADEN \ ADC Enable
+ $40 constant ADCSRA_ADSC \ ADC Start Conversion
+ 7a $40 bitmask: ADCSRA.ADSC \ ADC Start Conversion
+ $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
+ 7a $20 bitmask: ADCSRA.ADATE \ ADC Auto Trigger Enable
+ $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
+ 7a $10 bitmask: ADCSRA.ADIF \ ADC Interrupt Flag
+ $8 constant ADCSRA_ADIE \ ADC Interrupt Enable
+ 7a $8 bitmask: ADCSRA.ADIE \ ADC Interrupt Enable
+ $7 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
+ 7a $7 bitmask: ADCSRA.ADPS \ ADC Prescaler Select Bits
+$7b constant ADCSRB \ The ADC Control and Status Reg
+ $80 constant ADCSRB_AVDDOK \ AVDD Supply Voltage OK
+ 7b $80 bitmask: ADCSRB.AVDDOK \ AVDD Supply Voltage OK
+ $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer
+ 7b $40 bitmask: ADCSRB.ACME \ Analog Comparator Multiplexer
+ $20 constant ADCSRB_REFOK \ Reference Voltage OK
+ 7b $20 bitmask: ADCSRB.REFOK \ Reference Voltage OK
+ $10 constant ADCSRB_ACCH \ Analog Channel Change
+ 7b $10 bitmask: ADCSRB.ACCH \ Analog Channel Change
+ $8 constant ADCSRB_MUX5 \ Analog Channel and Gain Select
+ 7b $8 bitmask: ADCSRB.MUX5 \ Analog Channel and Gain Select
+ $7 constant ADCSRB_ADTS \ ADC Auto Trigger Source
+ 7b $7 bitmask: ADCSRB.ADTS \ ADC Auto Trigger Source
+$77 constant ADCSRC \ The ADC Control and Status Reg
+ $c0 constant ADCSRC_ADTHT \ ADC Track-and-Hold Time
+ 77 $c0 bitmask: ADCSRC.ADTHT \ ADC Track-and-Hold Time
+ $20 constant ADCSRC_Res0 \ Reserved
+ 77 $20 bitmask: ADCSRC.Res0 \ Reserved
+ $1f constant ADCSRC_ADSUT \ ADC Start-up Time
+ 77 $1f bitmask: ADCSRC.ADSUT \ ADC Start-up Time
+$7d constant DIDR2 \ Digital Input Disable Register
+ $80 constant DIDR2_ADC15D \ Reserved Bits
+ 7d $80 bitmask: DIDR2.ADC15D \ Reserved Bits
+ $40 constant DIDR2_ADC14D \ Reserved Bits
+ 7d $40 bitmask: DIDR2.ADC14D \ Reserved Bits
+ $20 constant DIDR2_ADC13D \ Reserved Bits
+ 7d $20 bitmask: DIDR2.ADC13D \ Reserved Bits
+ $10 constant DIDR2_ADC12D \ Reserved Bits
+ 7d $10 bitmask: DIDR2.ADC12D \ Reserved Bits
+ $8 constant DIDR2_ADC11D \ Reserved Bits
+ 7d $8 bitmask: DIDR2.ADC11D \ Reserved Bits
+ $4 constant DIDR2_ADC10D \ Reserved Bits
+ 7d $4 bitmask: DIDR2.ADC10D \ Reserved Bits
+ $2 constant DIDR2_ADC9D \ Reserved Bits
+ 7d $2 bitmask: DIDR2.ADC9D \ Reserved Bits
+ $1 constant DIDR2_ADC8D \ Reserved Bits
+ 7d $1 bitmask: DIDR2.ADC8D \ Reserved Bits
+$7e constant DIDR0 \ Digital Input Disable Register
+ $80 constant DIDR0_ADC7D \ Disable ADC7:0 Digital Input
+ 7e $80 bitmask: DIDR0.ADC7D \ Disable ADC7:0 Digital Input
+ $40 constant DIDR0_ADC6D \ Disable ADC7:0 Digital Input
+ 7e $40 bitmask: DIDR0.ADC6D \ Disable ADC7:0 Digital Input
+ $20 constant DIDR0_ADC5D \ Disable ADC7:0 Digital Input
+ 7e $20 bitmask: DIDR0.ADC5D \ Disable ADC7:0 Digital Input
+ $10 constant DIDR0_ADC4D \ Disable ADC7:0 Digital Input
+ 7e $10 bitmask: DIDR0.ADC4D \ Disable ADC7:0 Digital Input
+ $8 constant DIDR0_ADC3D \ Disable ADC7:0 Digital Input
+ 7e $8 bitmask: DIDR0.ADC3D \ Disable ADC7:0 Digital Input
+ $4 constant DIDR0_ADC2D \ Disable ADC7:0 Digital Input
+ 7e $4 bitmask: DIDR0.ADC2D \ Disable ADC7:0 Digital Input
+ $2 constant DIDR0_ADC1D \ Disable ADC7:0 Digital Input
+ 7e $2 bitmask: DIDR0.ADC1D \ Disable ADC7:0 Digital Input
+ $1 constant DIDR0_ADC0D \ Disable ADC7:0 Digital Input
+ 7e $1 bitmask: DIDR0.ADC0D \ Disable ADC7:0 Digital Input
+\ BOOT_LOAD
+$57 constant SPMCSR \ Store Program Memory Control R
+ $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
+ 57 $80 bitmask: SPMCSR.SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
+ 57 $40 bitmask: SPMCSR.RWWSB \ Read While Write Section Busy
+ $20 constant SPMCSR_SIGRD \ Signature Row Read
+ 57 $20 bitmask: SPMCSR.SIGRD \ Signature Row Read
+ $10 constant SPMCSR_RWWSRE \ Read While Write Section Read
+ 57 $10 bitmask: SPMCSR.RWWSRE \ Read While Write Section Read
+ $8 constant SPMCSR_BLBSET \ Boot Lock Bit Set
+ 57 $8 bitmask: SPMCSR.BLBSET \ Boot Lock Bit Set
+ $4 constant SPMCSR_PGWRT \ Page Write
+ 57 $4 bitmask: SPMCSR.PGWRT \ Page Write
+ $2 constant SPMCSR_PGERS \ Page Erase
+ 57 $2 bitmask: SPMCSR.PGERS \ Page Erase
+ $1 constant SPMCSR_SPMEN \ Store Program Memory Enable
+ 57 $1 bitmask: SPMCSR.SPMEN \ Store Program Memory Enable
+\ CPU
+$5f constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ 5f $80 bitmask: SREG.I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ 5f $40 bitmask: SREG.T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ 5f $20 bitmask: SREG.H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ 5f $10 bitmask: SREG.S \ Sign Bit
+ $8 constant SREG_V \ Two's Complement Overflow Flag
+ 5f $8 bitmask: SREG.V \ Two's Complement Overflow Flag
+ $4 constant SREG_N \ Negative Flag
+ 5f $4 bitmask: SREG.N \ Negative Flag
+ $2 constant SREG_Z \ Zero Flag
+ 5f $2 bitmask: SREG.Z \ Zero Flag
+ $1 constant SREG_C \ Carry Flag
+ 5f $1 bitmask: SREG.C \ Carry Flag
+$5d constant SP \ Stack Pointer
+$55 constant MCUCR \ MCU Control Register
+ $80 constant MCUCR_JTD \ JTAG Interface Disable
+ 55 $80 bitmask: MCUCR.JTD \ JTAG Interface Disable
+ $60 constant MCUCR_Res \ Reserved
+ 55 $60 bitmask: MCUCR.Res \ Reserved
+ $10 constant MCUCR_PUD \ Pull-up Disable
+ 55 $10 bitmask: MCUCR.PUD \ Pull-up Disable
+ $c constant MCUCR_Res \ Reserved
+ 55 $c bitmask: MCUCR.Res \ Reserved
+ $2 constant MCUCR_IVSEL \ Interrupt Vector Select
+ 55 $2 bitmask: MCUCR.IVSEL \ Interrupt Vector Select
+ $1 constant MCUCR_IVCE \ Interrupt Vector Change Enable
+ 55 $1 bitmask: MCUCR.IVCE \ Interrupt Vector Change Enable
+$54 constant MCUSR \ MCU Status Register
+ $e0 constant MCUSR_Res \ Reserved
+ 54 $e0 bitmask: MCUSR.Res \ Reserved
+ $10 constant MCUSR_JTRF \ JTAG Reset Flag
+ 54 $10 bitmask: MCUSR.JTRF \ JTAG Reset Flag
+ $8 constant MCUSR_WDRF \ Watchdog Reset Flag
+ 54 $8 bitmask: MCUSR.WDRF \ Watchdog Reset Flag
+ $4 constant MCUSR_BORF \ Brown-out Reset Flag
+ 54 $4 bitmask: MCUSR.BORF \ Brown-out Reset Flag
+ $2 constant MCUSR_EXTRF \ External Reset Flag
+ 54 $2 bitmask: MCUSR.EXTRF \ External Reset Flag
+ $1 constant MCUSR_PORF \ Power-on Reset Flag
+ 54 $1 bitmask: MCUSR.PORF \ Power-on Reset Flag
+$66 constant OSCCAL \ Oscillator Calibration Value
+ $ff constant OSCCAL_CAL \ Oscillator Calibration Tuning
+ 66 $ff bitmask: OSCCAL.CAL \ Oscillator Calibration Tuning
+$61 constant CLKPR \ Clock Prescale Register
+ $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable
+ 61 $80 bitmask: CLKPR.CLKPCE \ Clock Prescaler Change Enable
+ $70 constant CLKPR_Res \ Reserved
+ 61 $70 bitmask: CLKPR.Res \ Reserved
+ $f constant CLKPR_CLKPS \ Clock Prescaler Select Bits
+ 61 $f bitmask: CLKPR.CLKPS \ Clock Prescaler Select Bits
+$53 constant SMCR \ Sleep Mode Control Register
+ $f0 constant SMCR_Res \ Reserved
+ 53 $f0 bitmask: SMCR.Res \ Reserved
+ $e constant SMCR_SM \ Sleep Mode Select bits
+ 53 $e bitmask: SMCR.SM \ Sleep Mode Select bits
+ $1 constant SMCR_SE \ Sleep Enable
+ 53 $1 bitmask: SMCR.SE \ Sleep Enable
+$5c constant EIND \ Extended Indirect Register
+$5b constant RAMPZ \ Extended Z-pointer Register fo
+ $fc constant RAMPZ_Res \ Reserved
+ 5b $fc bitmask: RAMPZ.Res \ Reserved
+ $3 constant RAMPZ_RAMPZ \ Extended Z-Pointer Value
+ 5b $3 bitmask: RAMPZ.RAMPZ \ Extended Z-Pointer Value
+$4b constant GPIOR2 \ General Purpose I/O Register 2
+ $ff constant GPIOR2_GPIOR \ General Purpose I/O Register 2
+ 4b $ff bitmask: GPIOR2.GPIOR \ General Purpose I/O Register 2
+$4a constant GPIOR1 \ General Purpose IO Register 1
+ $ff constant GPIOR1_GPIOR \ General Purpose I/O Register 1
+ 4a $ff bitmask: GPIOR1.GPIOR \ General Purpose I/O Register 1
+$3e constant GPIOR0 \ General Purpose IO Register 0
+ $80 constant GPIOR0_GPIOR07 \ General Purpose I/O Register 0
+ 3e $80 bitmask: GPIOR0.GPIOR07 \ General Purpose I/O Register 0
+ $40 constant GPIOR0_GPIOR06 \ General Purpose I/O Register 0
+ 3e $40 bitmask: GPIOR0.GPIOR06 \ General Purpose I/O Register 0
+ $20 constant GPIOR0_GPIOR05 \ General Purpose I/O Register 0
+ 3e $20 bitmask: GPIOR0.GPIOR05 \ General Purpose I/O Register 0
+ $10 constant GPIOR0_GPIOR04 \ General Purpose I/O Register 0
+ 3e $10 bitmask: GPIOR0.GPIOR04 \ General Purpose I/O Register 0
+ $8 constant GPIOR0_GPIOR03 \ General Purpose I/O Register 0
+ 3e $8 bitmask: GPIOR0.GPIOR03 \ General Purpose I/O Register 0
+ $4 constant GPIOR0_GPIOR02 \ General Purpose I/O Register 0
+ 3e $4 bitmask: GPIOR0.GPIOR02 \ General Purpose I/O Register 0
+ $2 constant GPIOR0_GPIOR01 \ General Purpose I/O Register 0
+ 3e $2 bitmask: GPIOR0.GPIOR01 \ General Purpose I/O Register 0
+ $1 constant GPIOR0_GPIOR00 \ General Purpose I/O Register 0
+ 3e $1 bitmask: GPIOR0.GPIOR00 \ General Purpose I/O Register 0
+$63 constant PRR2 \ Power Reduction Register 2
+ $f0 constant PRR2_Res \ Reserved Bit
+ 63 $f0 bitmask: PRR2.Res \ Reserved Bit
+ $f constant PRR2_PRRAM \ Power Reduction SRAMs
+ 63 $f bitmask: PRR2.PRRAM \ Power Reduction SRAMs
+$65 constant PRR1 \ Power Reduction Register 1
+ $80 constant PRR1_Res \ Reserved Bit
+ 65 $80 bitmask: PRR1.Res \ Reserved Bit
+ $40 constant PRR1_PRTRX24 \ Power Reduction Transceiver
+ 65 $40 bitmask: PRR1.PRTRX24 \ Power Reduction Transceiver
+ $20 constant PRR1_PRTIM5 \ Power Reduction Timer/Counter5
+ 65 $20 bitmask: PRR1.PRTIM5 \ Power Reduction Timer/Counter5
+ $10 constant PRR1_PRTIM4 \ Power Reduction Timer/Counter4
+ 65 $10 bitmask: PRR1.PRTIM4 \ Power Reduction Timer/Counter4
+ $8 constant PRR1_PRTIM3 \ Power Reduction Timer/Counter3
+ 65 $8 bitmask: PRR1.PRTIM3 \ Power Reduction Timer/Counter3
+ $1 constant PRR1_PRUSART1 \ Power Reduction USART1
+ 65 $1 bitmask: PRR1.PRUSART1 \ Power Reduction USART1
+$64 constant PRR0 \ Power Reduction Register0
+ $80 constant PRR0_PRTWI \ Power Reduction TWI
+ 64 $80 bitmask: PRR0.PRTWI \ Power Reduction TWI
+ $40 constant PRR0_PRTIM2 \ Power Reduction Timer/Counter2
+ 64 $40 bitmask: PRR0.PRTIM2 \ Power Reduction Timer/Counter2
+ $20 constant PRR0_PRTIM0 \ Power Reduction Timer/Counter0
+ 64 $20 bitmask: PRR0.PRTIM0 \ Power Reduction Timer/Counter0
+ $10 constant PRR0_PRPGA \ Power Reduction PGA
+ 64 $10 bitmask: PRR0.PRPGA \ Power Reduction PGA
+ $8 constant PRR0_PRTIM1 \ Power Reduction Timer/Counter1
+ 64 $8 bitmask: PRR0.PRTIM1 \ Power Reduction Timer/Counter1
+ $4 constant PRR0_PRSPI \ Power Reduction Serial Periphe
+ 64 $4 bitmask: PRR0.PRSPI \ Power Reduction Serial Periphe
+ $2 constant PRR0_PRUSART0 \ Power Reduction USART
+ 64 $2 bitmask: PRR0.PRUSART0 \ Power Reduction USART
+ $1 constant PRR0_PRADC \ Power Reduction ADC
+ 64 $1 bitmask: PRR0.PRADC \ Power Reduction ADC
+\ FLASH
+$75 constant NEMCR \ Flash Extended-Mode Control-Re
+ $40 constant NEMCR_ENEAM \ Enable Extended Address Mode f
+ 75 $40 bitmask: NEMCR.ENEAM \ Enable Extended Address Mode f
+ $30 constant NEMCR_AEAM \ Address for Extended Address M
+ 75 $30 bitmask: NEMCR.AEAM \ Address for Extended Address M
+$67 constant BGCR \ Reference Voltage Calibration
+ $80 constant BGCR_Res \ Reserved Bit
+ 67 $80 bitmask: BGCR.Res \ Reserved Bit
+ $78 constant BGCR_BGCAL_FINE \ Fine Calibration Bits
+ 67 $78 bitmask: BGCR.BGCAL_FINE \ Fine Calibration Bits
+ $7 constant BGCR_BGCAL \ Coarse Calibration Bits
+ 67 $7 bitmask: BGCR.BGCAL \ Coarse Calibration Bits
+\ PWRCTRL
+$139 constant TRXPR \ Transceiver Pin Register
+ $f0 constant TRXPR_Res \ Reserved
+ 139 $f0 bitmask: TRXPR.Res \ Reserved
+ $2 constant TRXPR_SLPTR \ Multi-purpose Transceiver Cont
+ 139 $2 bitmask: TRXPR.SLPTR \ Multi-purpose Transceiver Cont
+ $1 constant TRXPR_TRXRST \ Force Transceiver Reset
+ 139 $1 bitmask: TRXPR.TRXRST \ Force Transceiver Reset
+$135 constant DRTRAM0 \ Data Retention Configuration R
+ $c0 constant DRTRAM0_Res \ Reserved
+ 135 $c0 bitmask: DRTRAM0.Res \ Reserved
+ $20 constant DRTRAM0_DRTSWOK \ DRT Switch OK
+ 135 $20 bitmask: DRTRAM0.DRTSWOK \ DRT Switch OK
+ $10 constant DRTRAM0_ENDRT \ Enable SRAM Data Retention
+ 135 $10 bitmask: DRTRAM0.ENDRT \ Enable SRAM Data Retention
+$134 constant DRTRAM1 \ Data Retention Configuration R
+ $c0 constant DRTRAM1_Res \ Reserved
+ 134 $c0 bitmask: DRTRAM1.Res \ Reserved
+ $20 constant DRTRAM1_DRTSWOK \ DRT Switch OK
+ 134 $20 bitmask: DRTRAM1.DRTSWOK \ DRT Switch OK
+ $10 constant DRTRAM1_ENDRT \ Enable SRAM Data Retention
+ 134 $10 bitmask: DRTRAM1.ENDRT \ Enable SRAM Data Retention
+$133 constant DRTRAM2 \ Data Retention Configuration R
+ $40 constant DRTRAM2_Res \ Reserved Bit
+ 133 $40 bitmask: DRTRAM2.Res \ Reserved Bit
+ $20 constant DRTRAM2_DRTSWOK \ DRT Switch OK
+ 133 $20 bitmask: DRTRAM2.DRTSWOK \ DRT Switch OK
+ $10 constant DRTRAM2_ENDRT \ Enable SRAM Data Retention
+ 133 $10 bitmask: DRTRAM2.ENDRT \ Enable SRAM Data Retention
+$132 constant DRTRAM3 \ Data Retention Configuration R
+ $c0 constant DRTRAM3_Res \ Reserved
+ 132 $c0 bitmask: DRTRAM3.Res \ Reserved
+ $20 constant DRTRAM3_DRTSWOK \ DRT Switch OK
+ 132 $20 bitmask: DRTRAM3.DRTSWOK \ DRT Switch OK
+ $10 constant DRTRAM3_ENDRT \ Enable SRAM Data Retention
+ 132 $10 bitmask: DRTRAM3.ENDRT \ Enable SRAM Data Retention
+$130 constant LLDRL \ Low Leakage Voltage Regulator
+ $f0 constant LLDRL_Res \ Reserved
+ 130 $f0 bitmask: LLDRL.Res \ Reserved
+ $f constant LLDRL_LLDRL \ Low-Byte Data Register Bits
+ 130 $f bitmask: LLDRL.LLDRL \ Low-Byte Data Register Bits
+$131 constant LLDRH \ Low Leakage Voltage Regulator
+ $e0 constant LLDRH_Res \ Reserved
+ 131 $e0 bitmask: LLDRH.Res \ Reserved
+ $1f constant LLDRH_LLDRH \ High-Byte Data Register Bits
+ 131 $1f bitmask: LLDRH.LLDRH \ High-Byte Data Register Bits
+$12f constant LLCR \ Low Leakage Voltage Regulator
+ $c0 constant LLCR_Res \ Reserved Bit
+ 12f $c0 bitmask: LLCR.Res \ Reserved Bit
+ $20 constant LLCR_LLDONE \ Calibration Done
+ 12f $20 bitmask: LLCR.LLDONE \ Calibration Done
+ $10 constant LLCR_LLCOMP \ Comparator Output
+ 12f $10 bitmask: LLCR.LLCOMP \ Comparator Output
+ $8 constant LLCR_LLCAL \ Calibration Active
+ 12f $8 bitmask: LLCR.LLCAL \ Calibration Active
+ $4 constant LLCR_LLTCO \ Temperature Coefficient of Cur
+ 12f $4 bitmask: LLCR.LLTCO \ Temperature Coefficient of Cur
+ $2 constant LLCR_LLSHORT \ Short Lower Calibration Circui
+ 12f $2 bitmask: LLCR.LLSHORT \ Short Lower Calibration Circui
+ $1 constant LLCR_LLENCAL \ Enable Automatic Calibration
+ 12f $1 bitmask: LLCR.LLENCAL \ Enable Automatic Calibration
+$136 constant DPDS0 \ Port Driver Strength Register
+ $c0 constant DPDS0_PFDRV \ Driver Strength Port F
+ 136 $c0 bitmask: DPDS0.PFDRV \ Driver Strength Port F
+ $30 constant DPDS0_PEDRV \ Driver Strength Port E
+ 136 $30 bitmask: DPDS0.PEDRV \ Driver Strength Port E
+ $c constant DPDS0_PDDRV \ Driver Strength Port D
+ 136 $c bitmask: DPDS0.PDDRV \ Driver Strength Port D
+ $3 constant DPDS0_PBDRV \ Driver Strength Port B
+ 136 $3 bitmask: DPDS0.PBDRV \ Driver Strength Port B
+$137 constant DPDS1 \ Port Driver Strength Register
+ $fc constant DPDS1_Res \ Reserved
+ 137 $fc bitmask: DPDS1.Res \ Reserved
+ $3 constant DPDS1_PGDRV \ Driver Strength Port G
+ 137 $3 bitmask: DPDS1.PGDRV \ Driver Strength Port G
+$55 constant MCUCR \ MCU Control Register
+ $10 constant MCUCR_PUD \ Pull-up Disable
+ 55 $10 bitmask: MCUCR.PUD \ Pull-up Disable
+\ USART0_SPI
+$c0 constant UCSR0A \ USART0 MSPIM Control and Statu
+ $80 constant UCSR0A_RXC0 \ USART Receive Complete
+ c0 $80 bitmask: UCSR0A.RXC0 \ USART Receive Complete
+ $40 constant UCSR0A_TXC0 \ USART Transmit Complete
+ c0 $40 bitmask: UCSR0A.TXC0 \ USART Transmit Complete
+ $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
+ c0 $20 bitmask: UCSR0A.UDRE0 \ USART Data Register Empty
+$c1 constant UCSR0B \ USART0 MSPIM Control and Statu
+ $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
+ c1 $80 bitmask: UCSR0B.RXCIE0 \ RX Complete Interrupt Enable
+ $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
+ c1 $40 bitmask: UCSR0B.TXCIE0 \ TX Complete Interrupt Enable
+ $20 constant UCSR0B_UDRIE0 \ USART Data Register Empty Inte
+ c1 $20 bitmask: UCSR0B.UDRIE0 \ USART Data Register Empty Inte
+ $10 constant UCSR0B_RXEN0 \ Receiver Enable
+ c1 $10 bitmask: UCSR0B.RXEN0 \ Receiver Enable
+ $8 constant UCSR0B_TXEN0 \ Transmitter Enable
+ c1 $8 bitmask: UCSR0B.TXEN0 \ Transmitter Enable
+$c2 constant UCSR0C \ USART0 MSPIM Control and Statu
+ $4 constant UCSR0C_UDORD0 \ Data Order
+ c2 $4 bitmask: UCSR0C.UDORD0 \ Data Order
+ $2 constant UCSR0C_UCPHA0 \ Clock Phase
+ c2 $2 bitmask: UCSR0C.UCPHA0 \ Clock Phase
+ $1 constant UCSR0C_UCPOL0 \ Clock Polarity
+ c2 $1 bitmask: UCSR0C.UCPOL0 \ Clock Polarity
+\ USART1_SPI
+$c8 constant UCSR1A \ USART1 MSPIM Control and Statu
+ $80 constant UCSR1A_RXC1 \ USART Receive Complete
+ c8 $80 bitmask: UCSR1A.RXC1 \ USART Receive Complete
+ $40 constant UCSR1A_TXC1 \ USART Transmit Complete
+ c8 $40 bitmask: UCSR1A.TXC1 \ USART Transmit Complete
+ $20 constant UCSR1A_UDRE1 \ USART Data Register Empty
+ c8 $20 bitmask: UCSR1A.UDRE1 \ USART Data Register Empty
+$c9 constant UCSR1B \ USART1 MSPIM Control and Statu
+ $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable
+ c9 $80 bitmask: UCSR1B.RXCIE1 \ RX Complete Interrupt Enable
+ $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable
+ c9 $40 bitmask: UCSR1B.TXCIE1 \ TX Complete Interrupt Enable
+ $20 constant UCSR1B_UDRIE1 \ USART Data Register Empty Inte
+ c9 $20 bitmask: UCSR1B.UDRIE1 \ USART Data Register Empty Inte
+ $10 constant UCSR1B_RXEN1 \ Receiver Enable
+ c9 $10 bitmask: UCSR1B.RXEN1 \ Receiver Enable
+ $8 constant UCSR1B_TXEN1 \ Transmitter Enable
+ c9 $8 bitmask: UCSR1B.TXEN1 \ Transmitter Enable
+$ca constant UCSR1C \ USART1 MSPIM Control and Statu
+ $4 constant UCSR1C_UDORD1 \ Data Order
+ ca $4 bitmask: UCSR1C.UDORD1 \ Data Order
+ $2 constant UCSR1C_UCPHA1 \ Clock Phase
+ ca $2 bitmask: UCSR1C.UCPHA1 \ Clock Phase
+ $1 constant UCSR1C_UCPOL1 \ Clock Polarity
+ ca $1 bitmask: UCSR1C.UCPOL1 \ Clock Polarity
diff --git a/amforth-6.5/avr8/devices/atmega256rfr2/device.py b/amforth-6.5/avr8/devices/atmega256rfr2/device.py
new file mode 100644
index 0000000..14b2cdc
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega256rfr2/device.py
@@ -0,0 +1,1104 @@
+# Generated Automatically
+
+# Partname ATmega256RFR2
+
+MCUREGS = {
+# Interrupt Vectors
+ 'INT0Addr' : '#2', # External Interrupt Request 0
+ 'INT1Addr' : '#4', # External Interrupt Request 1
+ 'INT2Addr' : '#6', # External Interrupt Request 2
+ 'INT3Addr' : '#8', # External Interrupt Request 3
+ 'INT4Addr' : '#10', # External Interrupt Request 4
+ 'INT5Addr' : '#12', # External Interrupt Request 5
+ 'INT6Addr' : '#14', # External Interrupt Request 6
+ 'INT7Addr' : '#16', # External Interrupt Request 7
+ 'PCINT0Addr' : '#18', # Pin Change Interrupt Request 0
+ 'PCINT1Addr' : '#20', # Pin Change Interrupt Request 1
+ 'PCINT2Addr' : '#22', # Pin Change Interrupt Request 2
+ 'WDTAddr' : '#24', # Watchdog Time-out Interrupt
+ 'TIMER2_COMPAAddr' : '#26', # Timer/Counter2 Compare Match A
+ 'TIMER2_COMPBAddr' : '#28', # Timer/Counter2 Compare Match B
+ 'TIMER2_OVFAddr' : '#30', # Timer/Counter2 Overflow
+ 'TIMER1_CAPTAddr' : '#32', # Timer/Counter1 Capture Event
+ 'TIMER1_COMPAAddr' : '#34', # Timer/Counter1 Compare Match A
+ 'TIMER1_COMPBAddr' : '#36', # Timer/Counter1 Compare Match B
+ 'TIMER1_COMPCAddr' : '#38', # Timer/Counter1 Compare Match C
+ 'TIMER1_OVFAddr' : '#40', # Timer/Counter1 Overflow
+ 'TIMER0_COMPAAddr' : '#42', # Timer/Counter0 Compare Match A
+ 'TIMER0_COMPBAddr' : '#44', # Timer/Counter0 Compare Match B
+ 'TIMER0_OVFAddr' : '#46', # Timer/Counter0 Overflow
+ 'SPI_STCAddr' : '#48', # SPI Serial Transfer Complete
+ 'USART0_RXAddr' : '#50', # USART0, Rx Complete
+ 'USART0_UDREAddr' : '#52', # USART0 Data register Empty
+ 'USART0_TXAddr' : '#54', # USART0, Tx Complete
+ 'ANALOG_COMPAddr' : '#56', # Analog Comparator
+ 'ADCAddr' : '#58', # ADC Conversion Complete
+ 'EE_READYAddr' : '#60', # EEPROM Ready
+ 'TIMER3_CAPTAddr' : '#62', # Timer/Counter3 Capture Event
+ 'TIMER3_COMPAAddr' : '#64', # Timer/Counter3 Compare Match A
+ 'TIMER3_COMPBAddr' : '#66', # Timer/Counter3 Compare Match B
+ 'TIMER3_COMPCAddr' : '#68', # Timer/Counter3 Compare Match C
+ 'TIMER3_OVFAddr' : '#70', # Timer/Counter3 Overflow
+ 'USART1_RXAddr' : '#72', # USART1, Rx Complete
+ 'USART1_UDREAddr' : '#74', # USART1 Data register Empty
+ 'USART1_TXAddr' : '#76', # USART1, Tx Complete
+ 'TWIAddr' : '#78', # 2-wire Serial Interface
+ 'SPM_READYAddr' : '#80', # Store Program Memory Read
+ 'TIMER4_CAPTAddr' : '#82', # Timer/Counter4 Capture Event
+ 'TIMER4_COMPAAddr' : '#84', # Timer/Counter4 Compare Match A
+ 'TIMER4_COMPBAddr' : '#86', # Timer/Counter4 Compare Match B
+ 'TIMER4_COMPCAddr' : '#88', # Timer/Counter4 Compare Match C
+ 'TIMER4_OVFAddr' : '#90', # Timer/Counter4 Overflow
+ 'TIMER5_CAPTAddr' : '#92', # Timer/Counter5 Capture Event
+ 'TIMER5_COMPAAddr' : '#94', # Timer/Counter5 Compare Match A
+ 'TIMER5_COMPBAddr' : '#96', # Timer/Counter5 Compare Match B
+ 'TIMER5_COMPCAddr' : '#98', # Timer/Counter5 Compare Match C
+ 'TIMER5_OVFAddr' : '#100', # Timer/Counter5 Overflow
+ 'USART2_RXAddr' : '#102', # USART2, Rx Complete
+ 'USART2_UDREAddr' : '#104', # USART2 Data register Empty
+ 'USART2_TXAddr' : '#106', # USART2, Tx Complete
+ 'USART3_RXAddr' : '#108', # USART3, Rx Complete
+ 'USART3_UDREAddr' : '#110', # USART3 Data register Empty
+ 'USART3_TXAddr' : '#112', # USART3, Tx Complete
+ 'TRX24_PLL_LOCKAddr' : '#114', # TRX24 - PLL lock interrupt
+ 'TRX24_PLL_UNLOCKAddr' : '#116', # TRX24 - PLL unlock interrupt
+ 'TRX24_RX_STARTAddr' : '#118', # TRX24 - Receive start interrupt
+ 'TRX24_RX_ENDAddr' : '#120', # TRX24 - RX_END interrupt
+ 'TRX24_CCA_ED_DONEAddr' : '#122', # TRX24 - CCA/ED done interrupt
+ 'TRX24_XAH_AMIAddr' : '#124', # TRX24 - XAH - AMI
+ 'TRX24_TX_ENDAddr' : '#126', # TRX24 - TX_END interrupt
+ 'TRX24_AWAKEAddr' : '#128', # TRX24 AWAKE - tranceiver is reaching state TRX_OFF
+ 'SCNT_CMP1Addr' : '#130', # Symbol counter - compare match 1 interrupt
+ 'SCNT_CMP2Addr' : '#132', # Symbol counter - compare match 2 interrupt
+ 'SCNT_CMP3Addr' : '#134', # Symbol counter - compare match 3 interrupt
+ 'SCNT_OVFLAddr' : '#136', # Symbol counter - overflow interrupt
+ 'SCNT_BACKOFFAddr' : '#138', # Symbol counter - backoff interrupt
+ 'AES_READYAddr' : '#140', # AES engine ready interrupt
+ 'BAT_LOWAddr' : '#142', # Battery monitor indicates supply voltage below threshold
+ 'TRX24_TX_STARTAddr' : '#144', # TRX24 TX start interrupt
+ 'TRX24_AMI0Addr' : '#146', # Address match interrupt of address filter 0
+ 'TRX24_AMI1Addr' : '#148', # Address match interrupt of address filter 1
+ 'TRX24_AMI2Addr' : '#150', # Address match interrupt of address filter 2
+ 'TRX24_AMI3Addr' : '#152', # Address match interrupt of address filter 3
+
+# Module ANALOG_COMPARATOR
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
+ 'ACSR' : '$50', # Analog Comparator Control And
+ 'ACSR_ACD': '$80', # Analog Comparator Disable
+ 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
+ 'ACSR_ACO': '$20', # Analog Compare Output
+ 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
+ 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
+ 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
+ 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
+ 'DIDR1' : '$7f', # Digital Input Disable Register
+ 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
+ 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
+
+# Module USART0
+ 'UDR0' : '$c6', # USART0 I/O Data Register
+ 'UCSR0A' : '$c0', # USART0 Control and Status Regi
+ 'UCSR0A_RXC0': '$80', # USART Receive Complete
+ 'UCSR0A_TXC0': '$40', # USART Transmit Complete
+ 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
+ 'UCSR0A_FE0': '$10', # Frame Error
+ 'UCSR0A_DOR0': '$8', # Data OverRun
+ 'UCSR0A_UPE0': '$4', # USART Parity Error
+ 'UCSR0A_U2X0': '$2', # Double the USART Transmission
+ 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
+ 'UCSR0B' : '$c1', # USART0 Control and Status Regi
+ 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
+ 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
+ 'UCSR0B_UDRIE0': '$20', # USART Data Register Empty Inte
+ 'UCSR0B_RXEN0': '$10', # Receiver Enable
+ 'UCSR0B_TXEN0': '$8', # Transmitter Enable
+ 'UCSR0B_UCSZ02': '$4', # Character Size
+ 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
+ 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
+ 'UCSR0C' : '$c2', # USART0 Control and Status Regi
+ 'UCSR0C_UMSEL0': '$c0', # USART Mode Select
+ 'UCSR0C_UPM0': '$30', # Parity Mode
+ 'UCSR0C_USBS0': '$8', # Stop Bit Select
+ 'UCSR0C_UCSZ0': '$6', # Character Size
+ 'UCSR0C_UCPOL0': '$1', # Clock Polarity
+ 'UBRR0' : '$c4', # USART0 Baud Rate Register Byt
+
+# Module USART1
+ 'UDR1' : '$ce', # USART1 I/O Data Register
+ 'UCSR1A' : '$c8', # USART1 Control and Status Regi
+ 'UCSR1A_RXC1': '$80', # USART Receive Complete
+ 'UCSR1A_TXC1': '$40', # USART Transmit Complete
+ 'UCSR1A_UDRE1': '$20', # USART Data Register Empty
+ 'UCSR1A_FE1': '$10', # Frame Error
+ 'UCSR1A_DOR1': '$8', # Data OverRun
+ 'UCSR1A_UPE1': '$4', # USART Parity Error
+ 'UCSR1A_U2X1': '$2', # Double the USART Transmission
+ 'UCSR1A_MPCM1': '$1', # Multi-processor Communication
+ 'UCSR1B' : '$c9', # USART1 Control and Status Regi
+ 'UCSR1B_RXCIE1': '$80', # RX Complete Interrupt Enable
+ 'UCSR1B_TXCIE1': '$40', # TX Complete Interrupt Enable
+ 'UCSR1B_UDRIE1': '$20', # USART Data Register Empty Inte
+ 'UCSR1B_RXEN1': '$10', # Receiver Enable
+ 'UCSR1B_TXEN1': '$8', # Transmitter Enable
+ 'UCSR1B_UCSZ12': '$4', # Character Size
+ 'UCSR1B_RXB81': '$2', # Receive Data Bit 8
+ 'UCSR1B_TXB81': '$1', # Transmit Data Bit 8
+ 'UCSR1C' : '$ca', # USART1 Control and Status Regi
+ 'UCSR1C_UMSEL1': '$c0', # USART Mode Select
+ 'UCSR1C_UPM1': '$30', # Parity Mode
+ 'UCSR1C_USBS1': '$8', # Stop Bit Select
+ 'UCSR1C_UCSZ1': '$6', # Character Size
+ 'UCSR1C_UCPOL1': '$1', # Clock Polarity
+ 'UBRR1' : '$cc', # USART1 Baud Rate Register Byt
+
+# Module TWI
+ 'TWAMR' : '$bd', # TWI (Slave) Address Mask Regis
+ 'TWAMR_TWAM': '$fe', # TWI Address Mask
+ 'TWAMR_Res': '$1', # Reserved Bit
+ 'TWBR' : '$b8', # TWI Bit Rate Register
+ 'TWCR' : '$bc', # TWI Control Register
+ 'TWCR_TWINT': '$80', # TWI Interrupt Flag
+ 'TWCR_TWEA': '$40', # TWI Enable Acknowledge Bit
+ 'TWCR_TWSTA': '$20', # TWI START Condition Bit
+ 'TWCR_TWSTO': '$10', # TWI STOP Condition Bit
+ 'TWCR_TWWC': '$8', # TWI Write Collision Flag
+ 'TWCR_TWEN': '$4', # TWI Enable Bit
+ 'TWCR_Res': '$2', # Reserved Bit
+ 'TWCR_TWIE': '$1', # TWI Interrupt Enable
+ 'TWSR' : '$b9', # TWI Status Register
+ 'TWSR_TWS': '$f8', # TWI Status
+ 'TWSR_Res': '$4', # Reserved Bit
+ 'TWSR_TWPS': '$3', # TWI Prescaler Bits
+ 'TWDR' : '$bb', # TWI Data Register
+ 'TWAR' : '$ba', # TWI (Slave) Address Register
+ 'TWAR_TWA': '$fe', # TWI (Slave) Address
+ 'TWAR_TWGCE': '$1', # TWI General Call Recognition E
+
+# Module SPI
+ 'SPCR' : '$4c', # SPI Control Register
+ 'SPCR_SPIE': '$80', # SPI Interrupt Enable
+ 'SPCR_SPE': '$40', # SPI Enable
+ 'SPCR_DORD': '$20', # Data Order
+ 'SPCR_MSTR': '$10', # Master/Slave Select
+ 'SPCR_CPOL': '$8', # Clock polarity
+ 'SPCR_CPHA': '$4', # Clock Phase
+ 'SPCR_SPR': '$3', # SPI Clock Rate Select 1 and 0
+ 'SPSR' : '$4d', # SPI Status Register
+ 'SPSR_SPIF': '$80', # SPI Interrupt Flag
+ 'SPSR_WCOL': '$40', # Write Collision Flag
+ 'SPSR_Res': '$3e', # Reserved
+ 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
+ 'SPDR' : '$4e', # SPI Data Register
+
+# Module PORTA
+ 'PORTA' : '$22', # Port A Data Register
+ 'DDRA' : '$21', # Port A Data Direction Register
+ 'PINA' : '$20', # Port A Input Pins Address
+
+# Module PORTB
+ 'PORTB' : '$25', # Port B Data Register
+ 'DDRB' : '$24', # Port B Data Direction Register
+ 'PINB' : '$23', # Port B Input Pins Address
+
+# Module PORTC
+ 'PORTC' : '$28', # Port C Data Register
+ 'DDRC' : '$27', # Port C Data Direction Register
+ 'PINC' : '$26', # Port C Input Pins Address
+
+# Module PORTD
+ 'PORTD' : '$2b', # Port D Data Register
+ 'DDRD' : '$2a', # Port D Data Direction Register
+ 'PIND' : '$29', # Port D Input Pins Address
+
+# Module PORTE
+ 'PORTE' : '$2e', # Port E Data Register
+ 'DDRE' : '$2d', # Port E Data Direction Register
+ 'PINE' : '$2c', # Port E Input Pins Address
+
+# Module PORTF
+ 'PORTF' : '$31', # Port F Data Register
+ 'DDRF' : '$30', # Port F Data Direction Register
+ 'PINF' : '$2f', # Port F Input Pins Address
+
+# Module PORTG
+ 'PORTG' : '$34', # Port G Data Register
+ 'DDRG' : '$33', # Port G Data Direction Register
+ 'PING' : '$32', # Port G Input Pins Address
+
+# Module TIMER_COUNTER_0
+ 'OCR0B' : '$48', # Timer/Counter0 Output Compare
+ 'OCR0A' : '$47', # Timer/Counter0 Output Compare
+ 'TCNT0' : '$46', # Timer/Counter0 Register
+ 'TCCR0B' : '$45', # Timer/Counter0 Control Registe
+ 'TCCR0B_FOC0A': '$80', # Force Output Compare A
+ 'TCCR0B_FOC0B': '$40', # Force Output Compare B
+ 'TCCR0B_Res': '$30', # Reserved Bit
+ 'TCCR0B_WGM02': '$8', #
+ 'TCCR0B_CS0': '$7', # Clock Select
+ 'TCCR0A' : '$44', # Timer/Counter0 Control Registe
+ 'TCCR0A_COM0A': '$c0', # Compare Match Output A Mode
+ 'TCCR0A_COM0B': '$30', # Compare Match Output B Mode
+ 'TCCR0A_Res': '$c', # Reserved Bit
+ 'TCCR0A_WGM0': '$3', # Waveform Generation Mode
+ 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
+ 'TIMSK0_Res': '$f8', # Reserved
+ 'TIMSK0_OCIE0B': '$4', # Timer/Counter0 Output Compare
+ 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
+ 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
+ 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
+ 'TIFR0_Res': '$f8', # Reserved
+ 'TIFR0_OCF0B': '$4', # Timer/Counter0 Output Compare
+ 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
+ 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_Res': '$7c', # Reserved
+ 'GTCCR_PSRASY': '$2', # Prescaler Reset Timer/Counter2
+ 'GTCCR_PSRSYNC': '$1', # Prescaler Reset for Synchronou
+
+# Module TIMER_COUNTER_2
+ 'TIMSK2' : '$70', # Timer/Counter Interrupt Mask r
+ 'TIMSK2_Res': '$f8', # Reserved Bit
+ 'TIMSK2_OCIE2B': '$4', # Timer/Counter2 Output Compare
+ 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
+ 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
+ 'TIFR2' : '$37', # Timer/Counter Interrupt Flag R
+ 'TIFR2_Res': '$f8', # Reserved Bit
+ 'TIFR2_OCF2B': '$4', # Output Compare Flag 2 B
+ 'TIFR2_OCF2A': '$2', # Output Compare Flag 2 A
+ 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
+ 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
+ 'TCCR2A_COM2A': '$c0', # Compare Match Output A Mode
+ 'TCCR2A_COM2B': '$30', # Compare Match Output B Mode
+ 'TCCR2A_Res': '$c', # Reserved
+ 'TCCR2A_WGM2': '$3', # Waveform Generation Mode
+ 'TCCR2B' : '$b1', # Timer/Counter2 Control Registe
+ 'TCCR2B_FOC2A': '$80', # Force Output Compare A
+ 'TCCR2B_FOC2B': '$40', # Force Output Compare B
+ 'TCCR2B_Res': '$30', # Reserved
+ 'TCCR2B_WGM22': '$8', # Waveform Generation Mode
+ 'TCCR2B_CS2': '$7', # Clock Select
+ 'TCNT2' : '$b2', # Timer/Counter2
+ 'OCR2B' : '$b4', # Timer/Counter2 Output Compare
+ 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
+ 'ASSR' : '$b6', # Asynchronous Status Register
+ 'ASSR_EXCLKAMR': '$80', # Enable External Clock Input fo
+ 'ASSR_EXCLK': '$40', # Enable External Clock Input
+ 'ASSR_AS2': '$20', # Timer/Counter2 Asynchronous Mo
+ 'ASSR_TCN2UB': '$10', # Timer/Counter2 Update Busy
+ 'ASSR_OCR2AUB': '$8', # Timer/Counter2 Output Compare
+ 'ASSR_OCR2BUB': '$4', # Timer/Counter2 Output Compare
+ 'ASSR_TCR2AUB': '$2', # Timer/Counter2 Control Registe
+ 'ASSR_TCR2BUB': '$1', # Timer/Counter2 Control Registe
+ 'GTCCR' : '$43', # General Timer Counter Control
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSRASY': '$2', # Prescaler Reset Timer/Counter2
+
+# Module WATCHDOG
+ 'WDTCSR' : '$60', # Watchdog Timer Control Registe
+ 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
+ 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
+ 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
+ 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
+ 'WDTCSR_WDE': '$8', # Watch Dog Enable
+
+# Module TIMER_COUNTER_5
+ 'TCCR5A' : '$120', # Timer/Counter5 Control Registe
+ 'TCCR5A_COM5A': '$c0', # Compare Output Mode for Channe
+ 'TCCR5A_COM5B': '$30', # Compare Output Mode for Channe
+ 'TCCR5A_COM5C': '$c', # Compare Output Mode for Channe
+ 'TCCR5A_WGM5': '$3', # Waveform Generation Mode
+ 'TCCR5B' : '$121', # Timer/Counter5 Control Registe
+ 'TCCR5B_ICNC5': '$80', # Input Capture 5 Noise Cancelle
+ 'TCCR5B_ICES5': '$40', # Input Capture 5 Edge Select
+ 'TCCR5B_Res': '$20', # Reserved Bit
+ 'TCCR5B_WGM5': '$18', # Waveform Generation Mode
+ 'TCCR5B_CS5': '$7', # Clock Select
+ 'TCCR5C' : '$122', # Timer/Counter5 Control Registe
+ 'TCCR5C_FOC5A': '$80', # Force Output Compare for Chann
+ 'TCCR5C_FOC5B': '$40', # Force Output Compare for Chann
+ 'TCCR5C_FOC5C': '$20', # Force Output Compare for Chann
+ 'TCCR5C_Res': '$1f', # Reserved
+ 'TCNT5' : '$124', # Timer/Counter5 Bytes
+ 'OCR5A' : '$128', # Timer/Counter5 Output Compare
+ 'OCR5B' : '$12a', # Timer/Counter5 Output Compare
+ 'OCR5C' : '$12c', # Timer/Counter5 Output Compare
+ 'ICR5' : '$126', # Timer/Counter5 Input Capture R
+ 'TIMSK5' : '$73', # Timer/Counter5 Interrupt Mask
+ 'TIMSK5_Res': '$c0', # Reserved Bit
+ 'TIMSK5_ICIE5': '$20', # Timer/Counter5 Input Capture I
+ 'TIMSK5_Res': '$10', # Reserved Bit
+ 'TIMSK5_OCIE5C': '$8', # Timer/Counter5 Output Compare
+ 'TIMSK5_OCIE5B': '$4', # Timer/Counter5 Output Compare
+ 'TIMSK5_OCIE5A': '$2', # Timer/Counter5 Output Compare
+ 'TIMSK5_TOIE5': '$1', # Timer/Counter5 Overflow Interr
+ 'TIFR5' : '$3a', # Timer/Counter5 Interrupt Flag
+ 'TIFR5_Res': '$c0', # Reserved Bit
+ 'TIFR5_ICF5': '$20', # Timer/Counter5 Input Capture F
+ 'TIFR5_Res': '$10', # Reserved Bit
+ 'TIFR5_OCF5C': '$8', # Timer/Counter5 Output Compare
+ 'TIFR5_OCF5B': '$4', # Timer/Counter5 Output Compare
+ 'TIFR5_OCF5A': '$2', # Timer/Counter5 Output Compare
+ 'TIFR5_TOV5': '$1', # Timer/Counter5 Overflow Flag
+
+# Module TIMER_COUNTER_4
+ 'TCCR4A' : '$a0', # Timer/Counter4 Control Registe
+ 'TCCR4A_COM4A': '$c0', # Compare Output Mode for Channe
+ 'TCCR4A_COM4B': '$30', # Compare Output Mode for Channe
+ 'TCCR4A_COM4C': '$c', # Compare Output Mode for Channe
+ 'TCCR4A_WGM4': '$3', # Waveform Generation Mode
+ 'TCCR4B' : '$a1', # Timer/Counter4 Control Registe
+ 'TCCR4B_ICNC4': '$80', # Input Capture 4 Noise Cancelle
+ 'TCCR4B_ICES4': '$40', # Input Capture 4 Edge Select
+ 'TCCR4B_Res': '$20', # Reserved Bit
+ 'TCCR4B_WGM4': '$18', # Waveform Generation Mode
+ 'TCCR4B_CS4': '$7', # Clock Select
+ 'TCCR4C' : '$a2', # Timer/Counter4 Control Registe
+ 'TCCR4C_FOC4A': '$80', # Force Output Compare for Chann
+ 'TCCR4C_FOC4B': '$40', # Force Output Compare for Chann
+ 'TCCR4C_FOC4C': '$20', # Force Output Compare for Chann
+ 'TCCR4C_Res': '$1f', # Reserved
+ 'TCNT4' : '$a4', # Timer/Counter4 Bytes
+ 'OCR4A' : '$a8', # Timer/Counter4 Output Compare
+ 'OCR4B' : '$aa', # Timer/Counter4 Output Compare
+ 'OCR4C' : '$ac', # Timer/Counter4 Output Compare
+ 'ICR4' : '$a6', # Timer/Counter4 Input Capture R
+ 'TIMSK4' : '$72', # Timer/Counter4 Interrupt Mask
+ 'TIMSK4_Res': '$c0', # Reserved Bit
+ 'TIMSK4_ICIE4': '$20', # Timer/Counter4 Input Capture I
+ 'TIMSK4_Res': '$10', # Reserved Bit
+ 'TIMSK4_OCIE4C': '$8', # Timer/Counter4 Output Compare
+ 'TIMSK4_OCIE4B': '$4', # Timer/Counter4 Output Compare
+ 'TIMSK4_OCIE4A': '$2', # Timer/Counter4 Output Compare
+ 'TIMSK4_TOIE4': '$1', # Timer/Counter4 Overflow Interr
+ 'TIFR4' : '$39', # Timer/Counter4 Interrupt Flag
+ 'TIFR4_Res': '$c0', # Reserved Bit
+ 'TIFR4_ICF4': '$20', # Timer/Counter4 Input Capture F
+ 'TIFR4_Res': '$10', # Reserved Bit
+ 'TIFR4_OCF4C': '$8', # Timer/Counter4 Output Compare
+ 'TIFR4_OCF4B': '$4', # Timer/Counter4 Output Compare
+ 'TIFR4_OCF4A': '$2', # Timer/Counter4 Output Compare
+ 'TIFR4_TOV4': '$1', # Timer/Counter4 Overflow Flag
+
+# Module TIMER_COUNTER_3
+ 'TCCR3A' : '$90', # Timer/Counter3 Control Registe
+ 'TCCR3A_COM3A': '$c0', # Compare Output Mode for Channe
+ 'TCCR3A_COM3B': '$30', # Compare Output Mode for Channe
+ 'TCCR3A_COM3C': '$c', # Compare Output Mode for Channe
+ 'TCCR3A_WGM3': '$3', # Waveform Generation Mode
+ 'TCCR3B' : '$91', # Timer/Counter3 Control Registe
+ 'TCCR3B_ICNC3': '$80', # Input Capture 3 Noise Cancelle
+ 'TCCR3B_ICES3': '$40', # Input Capture 3 Edge Select
+ 'TCCR3B_Res': '$20', # Reserved Bit
+ 'TCCR3B_WGM3': '$18', # Waveform Generation Mode
+ 'TCCR3B_CS3': '$7', # Clock Select
+ 'TCCR3C' : '$92', # Timer/Counter3 Control Registe
+ 'TCCR3C_FOC3A': '$80', # Force Output Compare for Chann
+ 'TCCR3C_FOC3B': '$40', # Force Output Compare for Chann
+ 'TCCR3C_FOC3C': '$20', # Force Output Compare for Chann
+ 'TCCR3C_Res': '$1f', # Reserved
+ 'TCNT3' : '$94', # Timer/Counter3 Bytes
+ 'OCR3A' : '$98', # Timer/Counter3 Output Compare
+ 'OCR3B' : '$9a', # Timer/Counter3 Output Compare
+ 'OCR3C' : '$9c', # Timer/Counter3 Output Compare
+ 'ICR3' : '$96', # Timer/Counter3 Input Capture R
+ 'TIMSK3' : '$71', # Timer/Counter3 Interrupt Mask
+ 'TIMSK3_Res': '$c0', # Reserved Bit
+ 'TIMSK3_ICIE3': '$20', # Timer/Counter3 Input Capture I
+ 'TIMSK3_Res': '$10', # Reserved Bit
+ 'TIMSK3_OCIE3C': '$8', # Timer/Counter3 Output Compare
+ 'TIMSK3_OCIE3B': '$4', # Timer/Counter3 Output Compare
+ 'TIMSK3_OCIE3A': '$2', # Timer/Counter3 Output Compare
+ 'TIMSK3_TOIE3': '$1', # Timer/Counter3 Overflow Interr
+ 'TIFR3' : '$38', # Timer/Counter3 Interrupt Flag
+ 'TIFR3_Res': '$c0', # Reserved Bit
+ 'TIFR3_ICF3': '$20', # Timer/Counter3 Input Capture F
+ 'TIFR3_Res': '$10', # Reserved Bit
+ 'TIFR3_OCF3C': '$8', # Timer/Counter3 Output Compare
+ 'TIFR3_OCF3B': '$4', # Timer/Counter3 Output Compare
+ 'TIFR3_OCF3A': '$2', # Timer/Counter3 Output Compare
+ 'TIFR3_TOV3': '$1', # Timer/Counter3 Overflow Flag
+
+# Module TIMER_COUNTER_1
+ 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
+ 'TCCR1A_COM1A': '$c0', # Compare Output Mode for Channe
+ 'TCCR1A_COM1B': '$30', # Compare Output Mode for Channe
+ 'TCCR1A_COM1C': '$c', # Compare Output Mode for Channe
+ 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
+ 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
+ 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Cancelle
+ 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
+ 'TCCR1B_Res': '$20', # Reserved Bit
+ 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
+ 'TCCR1B_CS1': '$7', # Clock Select
+ 'TCCR1C' : '$82', # Timer/Counter1 Control Registe
+ 'TCCR1C_FOC1A': '$80', # Force Output Compare for Chann
+ 'TCCR1C_FOC1B': '$40', # Force Output Compare for Chann
+ 'TCCR1C_FOC1C': '$20', # Force Output Compare for Chann
+ 'TCCR1C_Res': '$1f', # Reserved
+ 'TCNT1' : '$84', # Timer/Counter1 Bytes
+ 'OCR1A' : '$88', # Timer/Counter1 Output Compare
+ 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
+ 'OCR1C' : '$8c', # Timer/Counter1 Output Compare
+ 'ICR1' : '$86', # Timer/Counter1 Input Capture R
+ 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
+ 'TIMSK1_Res': '$c0', # Reserved Bit
+ 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
+ 'TIMSK1_Res': '$10', # Reserved Bit
+ 'TIMSK1_OCIE1C': '$8', # Timer/Counter1 Output Compare
+ 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
+ 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
+ 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
+ 'TIFR1' : '$36', # Timer/Counter1 Interrupt Flag
+ 'TIFR1_Res': '$c0', # Reserved Bit
+ 'TIFR1_ICF1': '$20', # Timer/Counter1 Input Capture F
+ 'TIFR1_Res': '$10', # Reserved Bit
+ 'TIFR1_OCF1C': '$8', # Timer/Counter1 Output Compare
+ 'TIFR1_OCF1B': '$4', # Timer/Counter1 Output Compare
+ 'TIFR1_OCF1A': '$2', # Timer/Counter1 Output Compare
+ 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
+
+# Module TRX24
+ 'PARCR' : '$138', # Power Amplifier Ramp up/down C
+ 'PARCR_PALTD': '$e0', # ext. PA Ramp Down Lead Time
+ 'PARCR_PALTU': '$1c', # ext. PA Ramp Up Lead Time
+ 'PARCR_PARDFI': '$2', # Power Amplifier Ramp Down Freq
+ 'PARCR_PARUFI': '$1', # Power Amplifier Ramp Up Freque
+ 'MAFSA0L' : '$10e', # Transceiver MAC Short Address
+ 'MAFSA0L_MAFSA0L': '$ff', # MAC Short Address low Byte for
+ 'MAFSA0H' : '$10f', # Transceiver MAC Short Address
+ 'MAFSA0H_MAFSA0H': '$ff', # MAC Short Address high Byte fo
+ 'MAFPA0L' : '$110', # Transceiver Personal Area Netw
+ 'MAFPA0L_MAFPA0L': '$ff', # MAC Personal Area Network ID l
+ 'MAFPA0H' : '$111', # Transceiver Personal Area Netw
+ 'MAFPA0H_MAFPA0H': '$ff', # MAC Personal Area Network ID h
+ 'MAFSA1L' : '$112', # Transceiver MAC Short Address
+ 'MAFSA1L_MAFSA1L': '$ff', # MAC Short Address low Byte for
+ 'MAFSA1H' : '$113', # Transceiver MAC Short Address
+ 'MAFSA1H_MAFSA1H': '$ff', # MAC Short Address high Byte fo
+ 'MAFPA1L' : '$114', # Transceiver Personal Area Netw
+ 'MAFPA1L_MAFPA1L': '$ff', # MAC Personal Area Network ID l
+ 'MAFPA1H' : '$115', # Transceiver Personal Area Netw
+ 'MAFPA1H_MAFPA1H': '$ff', # MAC Personal Area Network ID h
+ 'MAFSA2L' : '$116', # Transceiver MAC Short Address
+ 'MAFSA2L_MAFSA2L': '$ff', # MAC Short Address low Byte for
+ 'MAFSA2H' : '$117', # Transceiver MAC Short Address
+ 'MAFSA2H_MAFSA2H': '$ff', # MAC Short Address high Byte fo
+ 'MAFPA2L' : '$118', # Transceiver Personal Area Netw
+ 'MAFPA2L_MAFPA2L': '$ff', # MAC Personal Area Network ID l
+ 'MAFPA2H' : '$119', # Transceiver Personal Area Netw
+ 'MAFPA2H_MAFPA2H': '$ff', # MAC Personal Area Network ID h
+ 'MAFSA3L' : '$11a', # Transceiver MAC Short Address
+ 'MAFSA3L_MAFSA3L': '$ff', # MAC Short Address low Byte for
+ 'MAFSA3H' : '$11b', # Transceiver MAC Short Address
+ 'MAFSA3H_MAFSA3H': '$ff', # MAC Short Address high Byte fo
+ 'MAFPA3L' : '$11c', # Transceiver Personal Area Netw
+ 'MAFPA3L_MAFPA3L': '$ff', # MAC Personal Area Network ID l
+ 'MAFPA3H' : '$11d', # Transceiver Personal Area Netw
+ 'MAFPA3H_MAFPA3H': '$ff', # MAC Personal Area Network ID h
+ 'MAFCR0' : '$10c', # Multiple Address Filter Config
+ 'MAFCR0_Res': '$f0', # Reserved Bit
+ 'MAFCR0_MAF3EN': '$8', # Multiple Address Filter 3 Enab
+ 'MAFCR0_MAF2EN': '$4', # Multiple Address Filter 2 Enab
+ 'MAFCR0_MAF1EN': '$2', # Multiple Address Filter 1 Enab
+ 'MAFCR0_MAF0EN': '$1', # Multiple Address Filter 0 Enab
+ 'MAFCR1' : '$10d', # Multiple Address Filter Config
+ 'MAFCR1_AACK_3_SET_PD': '$80', # Set Data Pending bit for addre
+ 'MAFCR1_AACK_3_I_AM_COORD': '$40', # Enable PAN Coordinator mode fo
+ 'MAFCR1_AACK_2_SET_PD': '$20', # Set Data Pending bit for addre
+ 'MAFCR1_AACK_2_I_AM_COORD': '$10', # Enable PAN Coordinator mode fo
+ 'MAFCR1_AACK_1_SET_PD': '$8', # Set Data Pending bit for addre
+ 'MAFCR1_AACK_1_I_AM_COORD': '$4', # Enable PAN Coordinator mode fo
+ 'MAFCR1_AACK_0_SET_PD': '$2', # Set Data Pending bit for addre
+ 'MAFCR1_AACK_0_I_AM_COORD': '$1', # Enable PAN Coordinator mode fo
+ 'AES_CTRL' : '$13c', # AES Control Register
+ 'AES_CTRL_AES_REQUEST': '$80', # Request AES Operation.
+ 'AES_CTRL_Res': '$40', # Reserved Bit
+ 'AES_CTRL_AES_MODE': '$20', # Set AES Operation Mode
+ 'AES_CTRL_Res': '$10', # Reserved Bit
+ 'AES_CTRL_AES_DIR': '$8', # Set AES Operation Direction
+ 'AES_CTRL_AES_IM': '$4', # AES Interrupt Enable
+ 'AES_CTRL_Res': '$3', # Reserved Bit
+ 'AES_STATUS' : '$13d', # AES Status Register
+ 'AES_STATUS_AES_ER': '$80', # AES Operation Finished with Er
+ 'AES_STATUS_Res': '$7e', # Reserved
+ 'AES_STATUS_AES_DONE': '$1', # AES Operation Finished with Su
+ 'AES_STATE' : '$13e', # AES Plain and Cipher Text Buff
+ 'AES_STATE_AES_STATE': '$ff', # AES Plain and Cipher Text Buff
+ 'AES_KEY' : '$13f', # AES Encryption and Decryption
+ 'AES_KEY_AES_KEY': '$ff', # AES Encryption/Decryption Key
+ 'TRX_STATUS' : '$141', # Transceiver Status Register
+ 'TRX_STATUS_CCA_DONE': '$80', # CCA Algorithm Status
+ 'TRX_STATUS_CCA_STATUS': '$40', # CCA Status Result
+ 'TRX_STATUS_TST_STATUS': '$20', # Test mode status
+ 'TRX_STATUS_TRX_STATUS': '$1f', # Transceiver Main Status
+ 'TRX_STATE' : '$142', # Transceiver State Control Regi
+ 'TRX_STATE_TRAC_STATUS': '$e0', # Transaction Status
+ 'TRX_STATE_TRX_CMD': '$1f', # State Control Command
+ 'TRX_CTRL_0' : '$143', # Reserved
+ 'TRX_CTRL_0_Res7': '$80', # Reserved
+ 'TRX_CTRL_0_PMU_EN': '$40', # Enable Phase Measurement Unit
+ 'TRX_CTRL_0_PMU_START': '$20', # Start of Phase Measurement Uni
+ 'TRX_CTRL_0_PMU_IF_INV': '$10', # PMU IF Inverse
+ 'TRX_CTRL_0_Res': '$f', # Reserved
+ 'TRX_CTRL_1' : '$144', # Transceiver Control Register 1
+ 'TRX_CTRL_1_PA_EXT_EN': '$80', # External PA support enable
+ 'TRX_CTRL_1_IRQ_2_EXT_EN': '$40', # Connect Frame Start IRQ to TC1
+ 'TRX_CTRL_1_TX_AUTO_CRC_ON': '$20', # Enable Automatic CRC Calculati
+ 'TRX_CTRL_1_PLL_TX_FLT': '$10', # Enable PLL TX filter
+ 'TRX_CTRL_1_Res': '$f', # Reserved
+ 'PHY_TX_PWR' : '$145', # Transceiver Transmit Power Con
+ 'PHY_TX_PWR_Res': '$f0', # Reserved
+ 'PHY_TX_PWR_TX_PWR': '$f', # Transmit Power Setting
+ 'PHY_RSSI' : '$146', # Receiver Signal Strength Indic
+ 'PHY_RSSI_RX_CRC_VALID': '$80', # Received Frame CRC Status
+ 'PHY_RSSI_RND_VALUE': '$60', # Random Value
+ 'PHY_RSSI_RSSI': '$1f', # Receiver Signal Strength Indic
+ 'PHY_ED_LEVEL' : '$147', # Transceiver Energy Detection L
+ 'PHY_ED_LEVEL_ED_LEVEL': '$ff', # Energy Detection Level
+ 'PHY_CC_CCA' : '$148', # Transceiver Clear Channel Asse
+ 'PHY_CC_CCA_CCA_REQUEST': '$80', # Manual CCA Measurement Request
+ 'PHY_CC_CCA_CCA_MODE': '$60', # Select CCA Measurement Mode
+ 'PHY_CC_CCA_CHANNEL': '$1f', # RX/TX Channel Selection
+ 'CCA_THRES' : '$149', # Transceiver CCA Threshold Sett
+ 'CCA_THRES_CCA_CS_THRES': '$f0', # CS Threshold Level for CCA Mea
+ 'CCA_THRES_CCA_ED_THRES': '$f', # ED Threshold Level for CCA Mea
+ 'RX_CTRL' : '$14a', # Transceiver Receive Control Re
+ 'RX_CTRL_PDT_THRES': '$f', # Receiver Sensitivity Control
+ 'SFD_VALUE' : '$14b', # Start of Frame Delimiter Value
+ 'SFD_VALUE_SFD_VALUE': '$ff', # Start of Frame Delimiter Value
+ 'TRX_CTRL_2' : '$14c', # Transceiver Control Register 2
+ 'TRX_CTRL_2_RX_SAFE_MODE': '$80', # RX Safe Mode
+ 'TRX_CTRL_2_Res': '$7c', # Reserved
+ 'TRX_CTRL_2_OQPSK_DATA_RATE': '$3', # Data Rate Selection
+ 'ANT_DIV' : '$14d', # Antenna Diversity Control Regi
+ 'ANT_DIV_ANT_SEL': '$80', # Antenna Diversity Antenna Stat
+ 'ANT_DIV_Res': '$70', # Reserved
+ 'ANT_DIV_ANT_DIV_EN': '$8', # Enable Antenna Diversity
+ 'ANT_DIV_ANT_EXT_SW_EN': '$4', # Enable External Antenna Switch
+ 'ANT_DIV_ANT_CTRL': '$3', # Static Antenna Diversity Switc
+ 'IRQ_MASK' : '$14e', # Transceiver Interrupt Enable R
+ 'IRQ_MASK_AWAKE_EN': '$80', # Awake Interrupt Enable
+ 'IRQ_MASK_TX_END_EN': '$40', # TX_END Interrupt Enable
+ 'IRQ_MASK_AMI_EN': '$20', # Address Match Interrupt Enable
+ 'IRQ_MASK_CCA_ED_DONE_EN': '$10', # End of ED Measurement Interrup
+ 'IRQ_MASK_RX_END_EN': '$8', # RX_END Interrupt Enable
+ 'IRQ_MASK_RX_START_EN': '$4', # RX_START Interrupt Enable
+ 'IRQ_MASK_PLL_UNLOCK_EN': '$2', # PLL Unlock Interrupt Enable
+ 'IRQ_MASK_PLL_LOCK_EN': '$1', # PLL Lock Interrupt Enable
+ 'IRQ_STATUS' : '$14f', # Transceiver Interrupt Status R
+ 'IRQ_STATUS_AWAKE': '$80', # Awake Interrupt Status
+ 'IRQ_STATUS_TX_END': '$40', # TX_END Interrupt Status
+ 'IRQ_STATUS_AMI': '$20', # Address Match Interrupt Status
+ 'IRQ_STATUS_CCA_ED_DONE': '$10', # End of ED Measurement Interrup
+ 'IRQ_STATUS_RX_END': '$8', # RX_END Interrupt Status
+ 'IRQ_STATUS_RX_START': '$4', # RX_START Interrupt Status
+ 'IRQ_STATUS_PLL_UNLOCK': '$2', # PLL Unlock Interrupt Status
+ 'IRQ_STATUS_PLL_LOCK': '$1', # PLL Lock Interrupt Status
+ 'IRQ_MASK1' : '$be', # Transceiver Interrupt Enable R
+ 'IRQ_MASK1_Res': '$e0', # Reserved Bit
+ 'IRQ_MASK1_MAF_3_AMI_EN': '$10', # Address Match Interrupt enable
+ 'IRQ_MASK1_MAF_2_AMI_EN': '$8', # Address Match Interrupt enable
+ 'IRQ_MASK1_MAF_1_AMI_EN': '$4', # Address Match Interrupt enable
+ 'IRQ_MASK1_MAF_0_AMI_EN': '$2', # Address Match Interrupt enable
+ 'IRQ_MASK1_TX_START_EN': '$1', # Transmit Start Interrupt enabl
+ 'IRQ_STATUS1' : '$bf', # Transceiver Interrupt Status R
+ 'IRQ_STATUS1_Res': '$e0', # Reserved Bit
+ 'IRQ_STATUS1_MAF_3_AMI': '$10', # Address Match Interrupt Status
+ 'IRQ_STATUS1_MAF_2_AMI': '$8', # Address Match Interrupt Status
+ 'IRQ_STATUS1_MAF_1_AMI': '$4', # Address Match Interrupt Status
+ 'IRQ_STATUS1_MAF_0_AMI': '$2', # Address Match Interrupt Status
+ 'IRQ_STATUS1_TX_START': '$1', # Transmit Start Interrupt Statu
+ 'VREG_CTRL' : '$150', # Voltage Regulator Control and
+ 'VREG_CTRL_AVREG_EXT': '$80', # Use External AVDD Regulator
+ 'VREG_CTRL_AVDD_OK': '$40', # AVDD Supply Voltage Valid
+ 'VREG_CTRL_DVREG_EXT': '$8', # Use External DVDD Regulator
+ 'VREG_CTRL_DVDD_OK': '$4', # DVDD Supply Voltage Valid
+ 'BATMON' : '$151', # Battery Monitor Control and St
+ 'BATMON_BAT_LOW': '$80', # Battery Monitor Interrupt Stat
+ 'BATMON_BAT_LOW_EN': '$40', # Battery Monitor Interrupt Enab
+ 'BATMON_BATMON_OK': '$20', # Battery Monitor Status
+ 'BATMON_BATMON_HR': '$10', # Battery Monitor Voltage Range
+ 'BATMON_BATMON_VTH': '$f', # Battery Monitor Threshold Volt
+ 'XOSC_CTRL' : '$152', # Crystal Oscillator Control Reg
+ 'XOSC_CTRL_XTAL_MODE': '$f0', # Crystal Oscillator Operating M
+ 'XOSC_CTRL_XTAL_TRIM': '$f', # Crystal Oscillator Load Capaci
+ 'CC_CTRL_0' : '$153', # Channel Control Register 0
+ 'CC_CTRL_0_CC_NUMBER': '$ff', # Channel Number
+ 'CC_CTRL_1' : '$154', # Channel Control Register 1
+ 'CC_CTRL_1_CC_BAND': '$f', # Channel Band
+ 'RX_SYN' : '$155', # Transceiver Receiver Sensitivi
+ 'RX_SYN_RX_PDT_DIS': '$80', # Prevent Frame Reception
+ 'RX_SYN_RX_OVERRIDE': '$40', # Receiver Override Function
+ 'RX_SYN_Res': '$30', # Reserved
+ 'RX_SYN_RX_PDT_LEVEL': '$f', # Reduce Receiver Sensitivity
+ 'TRX_RPC' : '$156', # Transceiver Reduced Power Cons
+ 'TRX_RPC_RX_RPC_CTRL': '$c0', # Smart Receiving Mode Timing
+ 'TRX_RPC_RX_RPC_EN': '$20', # Reciver Smart Receiving Mode E
+ 'TRX_RPC_PDT_RPC_EN': '$10', # Smart Receiving Mode Reduced S
+ 'TRX_RPC_PLL_RPC_EN': '$8', # PLL Smart Receiving Mode Enabl
+ 'TRX_RPC_Res0': '$4', # Reserved
+ 'TRX_RPC_IPAN_RPC_EN': '$2', # Smart Receiving Mode IPAN Hand
+ 'TRX_RPC_XAH_RPC_EN': '$1', # Smart Receiving in Extended Op
+ 'XAH_CTRL_1' : '$157', # Transceiver Acknowledgment Fra
+ 'XAH_CTRL_1_Res': '$c0', # Reserved Bit
+ 'XAH_CTRL_1_AACK_FLTR_RES_FT': '$20', # Filter Reserved Frames
+ 'XAH_CTRL_1_AACK_UPLD_RES_FT': '$10', # Process Reserved Frames
+ 'XAH_CTRL_1_Res': '$8', # Reserved Bit
+ 'XAH_CTRL_1_AACK_ACK_TIME': '$4', # Reduce Acknowledgment Time
+ 'XAH_CTRL_1_AACK_PROM_MODE': '$2', # Enable Promiscuous Mode
+ 'XAH_CTRL_1_Res': '$1', # Reserved Bit
+ 'FTN_CTRL' : '$158', # Transceiver Filter Tuning Cont
+ 'FTN_CTRL_FTN_START': '$80', # Start Calibration Loop of Filt
+ 'PLL_CF' : '$15a', # Transceiver Center Frequency C
+ 'PLL_CF_PLL_CF_START': '$80', # Start Center Frequency Calibra
+ 'PLL_DCU' : '$15b', # Transceiver Delay Cell Calibra
+ 'PLL_DCU_PLL_DCU_START': '$80', # Start Delay Cell Calibration
+ 'PART_NUM' : '$15c', # Device Identification Register
+ 'PART_NUM_PART_NUM': '$ff', # Part Number
+ 'VERSION_NUM' : '$15d', # Device Identification Register
+ 'VERSION_NUM_VERSION_NUM': '$ff', # Version Number
+ 'MAN_ID_0' : '$15e', # Device Identification Register
+ 'MAN_ID_0_MAN_ID_07': '$80', # Manufacturer ID (Low Byte)
+ 'MAN_ID_0_MAN_ID_06': '$40', # Manufacturer ID (Low Byte)
+ 'MAN_ID_0_MAN_ID_05': '$20', # Manufacturer ID (Low Byte)
+ 'MAN_ID_0_MAN_ID_04': '$10', # Manufacturer ID (Low Byte)
+ 'MAN_ID_0_MAN_ID_03': '$8', # Manufacturer ID (Low Byte)
+ 'MAN_ID_0_MAN_ID_02': '$4', # Manufacturer ID (Low Byte)
+ 'MAN_ID_0_MAN_ID_01': '$2', # Manufacturer ID (Low Byte)
+ 'MAN_ID_0_MAN_ID_00': '$1', # Manufacturer ID (Low Byte)
+ 'MAN_ID_1' : '$15f', # Device Identification Register
+ 'MAN_ID_1_MAN_ID_': '$ff', # Manufacturer ID (High Byte)
+ 'SHORT_ADDR_0' : '$160', # Transceiver MAC Short Address
+ 'SHORT_ADDR_0_SHORT_ADDR_07': '$80', # MAC Short Address
+ 'SHORT_ADDR_0_SHORT_ADDR_06': '$40', # MAC Short Address
+ 'SHORT_ADDR_0_SHORT_ADDR_05': '$20', # MAC Short Address
+ 'SHORT_ADDR_0_SHORT_ADDR_04': '$10', # MAC Short Address
+ 'SHORT_ADDR_0_SHORT_ADDR_03': '$8', # MAC Short Address
+ 'SHORT_ADDR_0_SHORT_ADDR_02': '$4', # MAC Short Address
+ 'SHORT_ADDR_0_SHORT_ADDR_01': '$2', # MAC Short Address
+ 'SHORT_ADDR_0_SHORT_ADDR_00': '$1', # MAC Short Address
+ 'SHORT_ADDR_1' : '$161', # Transceiver MAC Short Address
+ 'SHORT_ADDR_1_SHORT_ADDR_': '$ff', # MAC Short Address
+ 'PAN_ID_0' : '$162', # Transceiver Personal Area Netw
+ 'PAN_ID_0_PAN_ID_07': '$80', # MAC Personal Area Network ID
+ 'PAN_ID_0_PAN_ID_06': '$40', # MAC Personal Area Network ID
+ 'PAN_ID_0_PAN_ID_05': '$20', # MAC Personal Area Network ID
+ 'PAN_ID_0_PAN_ID_04': '$10', # MAC Personal Area Network ID
+ 'PAN_ID_0_PAN_ID_03': '$8', # MAC Personal Area Network ID
+ 'PAN_ID_0_PAN_ID_02': '$4', # MAC Personal Area Network ID
+ 'PAN_ID_0_PAN_ID_01': '$2', # MAC Personal Area Network ID
+ 'PAN_ID_0_PAN_ID_00': '$1', # MAC Personal Area Network ID
+ 'PAN_ID_1' : '$163', # Transceiver Personal Area Netw
+ 'PAN_ID_1_PAN_ID_': '$ff', # MAC Personal Area Network ID
+ 'IEEE_ADDR_0' : '$164', # Transceiver MAC IEEE Address R
+ 'IEEE_ADDR_0_IEEE_ADDR_07': '$80', # MAC IEEE Address
+ 'IEEE_ADDR_0_IEEE_ADDR_06': '$40', # MAC IEEE Address
+ 'IEEE_ADDR_0_IEEE_ADDR_05': '$20', # MAC IEEE Address
+ 'IEEE_ADDR_0_IEEE_ADDR_04': '$10', # MAC IEEE Address
+ 'IEEE_ADDR_0_IEEE_ADDR_03': '$8', # MAC IEEE Address
+ 'IEEE_ADDR_0_IEEE_ADDR_02': '$4', # MAC IEEE Address
+ 'IEEE_ADDR_0_IEEE_ADDR_01': '$2', # MAC IEEE Address
+ 'IEEE_ADDR_0_IEEE_ADDR_00': '$1', # MAC IEEE Address
+ 'IEEE_ADDR_1' : '$165', # Transceiver MAC IEEE Address R
+ 'IEEE_ADDR_1_IEEE_ADDR_': '$ff', # MAC IEEE Address
+ 'IEEE_ADDR_2' : '$166', # Transceiver MAC IEEE Address R
+ 'IEEE_ADDR_2_IEEE_ADDR_': '$ff', # MAC IEEE Address
+ 'IEEE_ADDR_3' : '$167', # Transceiver MAC IEEE Address R
+ 'IEEE_ADDR_3_IEEE_ADDR_': '$ff', # MAC IEEE Address
+ 'IEEE_ADDR_4' : '$168', # Transceiver MAC IEEE Address R
+ 'IEEE_ADDR_4_IEEE_ADDR_': '$ff', # MAC IEEE Address
+ 'IEEE_ADDR_5' : '$169', # Transceiver MAC IEEE Address R
+ 'IEEE_ADDR_5_IEEE_ADDR_': '$ff', # MAC IEEE Address
+ 'IEEE_ADDR_6' : '$16a', # Transceiver MAC IEEE Address R
+ 'IEEE_ADDR_6_IEEE_ADDR_': '$ff', # MAC IEEE Address
+ 'IEEE_ADDR_7' : '$16b', # Transceiver MAC IEEE Address R
+ 'IEEE_ADDR_7_IEEE_ADDR_': '$ff', # MAC IEEE Address
+ 'XAH_CTRL_0' : '$16c', # Transceiver Extended Operating
+ 'XAH_CTRL_0_MAX_FRAME_RETRIES': '$f0', # Maximum Number of Frame Re-tra
+ 'XAH_CTRL_0_MAX_CSMA_RETRIES': '$e', # Maximum Number of CSMA-CA Proc
+ 'XAH_CTRL_0_SLOTTED_OPERATION': '$1', # Set Slotted Acknowledgment
+ 'CSMA_SEED_0' : '$16d', # Transceiver CSMA-CA Random Num
+ 'CSMA_SEED_0_CSMA_SEED_07': '$80', # Seed Value for CSMA Random Num
+ 'CSMA_SEED_0_CSMA_SEED_06': '$40', # Seed Value for CSMA Random Num
+ 'CSMA_SEED_0_CSMA_SEED_05': '$20', # Seed Value for CSMA Random Num
+ 'CSMA_SEED_0_CSMA_SEED_04': '$10', # Seed Value for CSMA Random Num
+ 'CSMA_SEED_0_CSMA_SEED_03': '$8', # Seed Value for CSMA Random Num
+ 'CSMA_SEED_0_CSMA_SEED_02': '$4', # Seed Value for CSMA Random Num
+ 'CSMA_SEED_0_CSMA_SEED_01': '$2', # Seed Value for CSMA Random Num
+ 'CSMA_SEED_0_CSMA_SEED_00': '$1', # Seed Value for CSMA Random Num
+ 'CSMA_SEED_1' : '$16e', # Transceiver Acknowledgment Fra
+ 'CSMA_SEED_1_AACK_FVN_MODE': '$c0', # Acknowledgment Frame Filter Mo
+ 'CSMA_SEED_1_AACK_SET_PD': '$20', # Set Frame Pending Sub-field
+ 'CSMA_SEED_1_AACK_DIS_ACK': '$10', # Disable Acknowledgment Frame T
+ 'CSMA_SEED_1_AACK_I_AM_COORD': '$8', # Set Personal Area Network Coor
+ 'CSMA_SEED_1_CSMA_SEED_1': '$7', # Seed Value for CSMA Random Num
+ 'CSMA_BE' : '$16f', # Transceiver CSMA-CA Back-off E
+ 'CSMA_BE_MAX_BE': '$f0', # Maximum Back-off Exponent
+ 'CSMA_BE_MIN_BE': '$f', # Minimum Back-off Exponent
+ 'TST_CTRL_DIGI' : '$176', # Transceiver Digital Test Contr
+ 'TST_CTRL_DIGI_TST_CTRL_DIG': '$f', # Digital Test Controller Regist
+ 'TST_RX_LENGTH' : '$17b', # Transceiver Received Frame Len
+ 'TST_RX_LENGTH_RX_LENGTH': '$ff', # Received Frame Length
+ 'TRXFBST' : '$180', # Start of frame buffer
+ 'TRXFBEND' : '$1ff', # End of frame buffer
+
+# Module SYMCNT
+ 'SCTSTRHH' : '$fc', # Symbol Counter Transmit Frame
+ 'SCTSTRHH_SCTSTRHH': '$ff', # Symbol Counter Transmit Frame
+ 'SCTSTRHL' : '$fb', # Symbol Counter Transmit Frame
+ 'SCTSTRHL_SCTSTRHL': '$ff', # Symbol Counter Transmit Frame
+ 'SCTSTRLH' : '$fa', # Symbol Counter Transmit Frame
+ 'SCTSTRLH_SCTSTRLH': '$ff', # Symbol Counter Transmit Frame
+ 'SCTSTRLL' : '$f9', # Symbol Counter Transmit Frame
+ 'SCTSTRLL_SCTSTRLL': '$ff', # Symbol Counter Transmit Frame
+ 'SCOCR1HH' : '$f8', # Symbol Counter Output Compare
+ 'SCOCR1HH_SCOCR1HH': '$ff', # Symbol Counter Output Compare
+ 'SCOCR1HL' : '$f7', # Symbol Counter Output Compare
+ 'SCOCR1HL_SCOCR1HL': '$ff', # Symbol Counter Output Compare
+ 'SCOCR1LH' : '$f6', # Symbol Counter Output Compare
+ 'SCOCR1LH_SCOCR1LH': '$ff', # Symbol Counter Output Compare
+ 'SCOCR1LL' : '$f5', # Symbol Counter Output Compare
+ 'SCOCR1LL_SCOCR1LL': '$ff', # Symbol Counter Output Compare
+ 'SCOCR2HH' : '$f4', # Symbol Counter Output Compare
+ 'SCOCR2HH_SCOCR2HH': '$ff', # Symbol Counter Output Compare
+ 'SCOCR2HL' : '$f3', # Symbol Counter Output Compare
+ 'SCOCR2HL_SCOCR2HL': '$ff', # Symbol Counter Output Compare
+ 'SCOCR2LH' : '$f2', # Symbol Counter Output Compare
+ 'SCOCR2LH_SCOCR2LH': '$ff', # Symbol Counter Output Compare
+ 'SCOCR2LL' : '$f1', # Symbol Counter Output Compare
+ 'SCOCR2LL_SCOCR2LL': '$ff', # Symbol Counter Output Compare
+ 'SCOCR3HH' : '$f0', # Symbol Counter Output Compare
+ 'SCOCR3HH_SCOCR3HH': '$ff', # Symbol Counter Output Compare
+ 'SCOCR3HL' : '$ef', # Symbol Counter Output Compare
+ 'SCOCR3HL_SCOCR3HL': '$ff', # Symbol Counter Output Compare
+ 'SCOCR3LH' : '$ee', # Symbol Counter Output Compare
+ 'SCOCR3LH_SCOCR3LH': '$ff', # Symbol Counter Output Compare
+ 'SCOCR3LL' : '$ed', # Symbol Counter Output Compare
+ 'SCOCR3LL_SCOCR3LL': '$ff', # Symbol Counter Output Compare
+ 'SCTSRHH' : '$ec', # Symbol Counter Frame Timestamp
+ 'SCTSRHH_SCTSRHH': '$ff', # Symbol Counter Frame Timestamp
+ 'SCTSRHL' : '$eb', # Symbol Counter Frame Timestamp
+ 'SCTSRHL_SCTSRHL': '$ff', # Symbol Counter Frame Timestamp
+ 'SCTSRLH' : '$ea', # Symbol Counter Frame Timestamp
+ 'SCTSRLH_SCTSRLH': '$ff', # Symbol Counter Frame Timestamp
+ 'SCTSRLL' : '$e9', # Symbol Counter Frame Timestamp
+ 'SCTSRLL_SCTSRLL': '$ff', # Symbol Counter Frame Timestamp
+ 'SCBTSRHH' : '$e8', # Symbol Counter Beacon Timestam
+ 'SCBTSRHH_SCBTSRHH': '$ff', # Symbol Counter Beacon Timestam
+ 'SCBTSRHL' : '$e7', # Symbol Counter Beacon Timestam
+ 'SCBTSRHL_SCBTSRHL': '$ff', # Symbol Counter Beacon Timestam
+ 'SCBTSRLH' : '$e6', # Symbol Counter Beacon Timestam
+ 'SCBTSRLH_SCBTSRLH': '$ff', # Symbol Counter Beacon Timestam
+ 'SCBTSRLL' : '$e5', # Symbol Counter Beacon Timestam
+ 'SCBTSRLL_SCBTSRLL': '$ff', # Symbol Counter Beacon Timestam
+ 'SCCNTHH' : '$e4', # Symbol Counter Register HH-Byt
+ 'SCCNTHH_SCCNTHH': '$ff', # Symbol Counter Register HH-Byt
+ 'SCCNTHL' : '$e3', # Symbol Counter Register HL-Byt
+ 'SCCNTHL_SCCNTHL': '$ff', # Symbol Counter Register HL-Byt
+ 'SCCNTLH' : '$e2', # Symbol Counter Register LH-Byt
+ 'SCCNTLH_SCCNTLH': '$ff', # Symbol Counter Register LH-Byt
+ 'SCCNTLL' : '$e1', # Symbol Counter Register LL-Byt
+ 'SCCNTLL_SCCNTLL': '$ff', # Symbol Counter Register LL-Byt
+ 'SCIRQS' : '$e0', # Symbol Counter Interrupt Statu
+ 'SCIRQS_Res': '$e0', # Reserved Bit
+ 'SCIRQS_IRQSBO': '$10', # Backoff Slot Counter IRQ
+ 'SCIRQS_IRQSOF': '$8', # Symbol Counter Overflow IRQ
+ 'SCIRQS_IRQSCP': '$7', # Compare Unit 3 Compare Match I
+ 'SCIRQM' : '$df', # Symbol Counter Interrupt Mask
+ 'SCIRQM_Res': '$e0', # Reserved Bit
+ 'SCIRQM_IRQMBO': '$10', # Backoff Slot Counter IRQ enabl
+ 'SCIRQM_IRQMOF': '$8', # Symbol Counter Overflow IRQ en
+ 'SCIRQM_IRQMCP': '$7', # Symbol Counter Compare Match 3
+ 'SCSR' : '$de', # Symbol Counter Status Register
+ 'SCSR_Res': '$fe', # Reserved Bit
+ 'SCSR_SCBSY': '$1', # Symbol Counter busy
+ 'SCCR1' : '$dd', # Symbol Counter Control Registe
+ 'SCCR1_Res': '$c0', # Reserved Bit
+ 'SCCR1_SCBTSM': '$20', # Symbol Counter Beacon Timestam
+ 'SCCR1_SCCKDIV': '$1c', # Clock divider for synchronous
+ 'SCCR1_SCEECLK': '$2', # Enable External Clock Source o
+ 'SCCR1_SCENBO': '$1', # Backoff Slot Counter enable
+ 'SCCR0' : '$dc', # Symbol Counter Control Registe
+ 'SCCR0_SCRES': '$80', # Symbol Counter Synchronization
+ 'SCCR0_SCMBTS': '$40', # Manual Beacon Timestamp
+ 'SCCR0_SCEN': '$20', # Symbol Counter enable
+ 'SCCR0_SCCKSEL': '$10', # Symbol Counter Clock Source se
+ 'SCCR0_SCTSE': '$8', # Symbol Counter Automatic Times
+ 'SCCR0_SCCMP': '$7', # Symbol Counter Compare Unit 3
+ 'SCCSR' : '$db', # Symbol Counter Compare Source
+ 'SCCSR_Res': '$c0', # Reserved Bit
+ 'SCCSR_SCCS3': '$30', # Symbol Counter Compare Source
+ 'SCCSR_SCCS2': '$c', # Symbol Counter Compare Source
+ 'SCCSR_SCCS1': '$3', # Symbol Counter Compare Source
+ 'SCRSTRHH' : '$da', # Symbol Counter Received Frame
+ 'SCRSTRHH_SCRSTRHH': '$ff', # Symbol Counter Received Frame
+ 'SCRSTRHL' : '$d9', # Symbol Counter Received Frame
+ 'SCRSTRHL_SCRSTRHL': '$ff', # Symbol Counter Received Frame
+ 'SCRSTRLH' : '$d8', # Symbol Counter Received Frame
+ 'SCRSTRLH_SCRSTRLH': '$ff', # Symbol Counter Received Frame
+ 'SCRSTRLL' : '$d7', # Symbol Counter Received Frame
+ 'SCRSTRLL_SCRSTRLL': '$ff', # Symbol Counter Received Frame
+
+# Module EEPROM
+ 'EEAR' : '$41', # EEPROM Address Register Bytes
+ 'EEDR' : '$40', # EEPROM Data Register
+ 'EECR' : '$3f', # EEPROM Control Register
+ 'EECR_Res': '$c0', # Reserved
+ 'EECR_EEPM': '$30', # EEPROM Programming Mode
+ 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
+ 'EECR_EEMPE': '$4', # EEPROM Master Write Enable
+ 'EECR_EEPE': '$2', # EEPROM Programming Enable
+ 'EECR_EERE': '$1', # EEPROM Read Enable
+
+# Module JTAG
+ 'OCDR' : '$51', # On-Chip Debug Register
+ 'OCDR_OCDR': '$ff', # On-Chip Debug Register Data
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_JTD': '$80', # JTAG Interface Disable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+
+# Module EXTERNAL_INTERRUPT
+ 'EICRA' : '$69', # External Interrupt Control Reg
+ 'EICRA_ISC3': '$c0', # External Interrupt 3 Sense Con
+ 'EICRA_ISC2': '$30', # External Interrupt 2 Sense Con
+ 'EICRA_ISC1': '$c', # External Interrupt 1 Sense Con
+ 'EICRA_ISC0': '$3', # External Interrupt 0 Sense Con
+ 'EICRB' : '$6a', # External Interrupt Control Reg
+ 'EICRB_ISC7': '$c0', # External Interrupt 7 Sense Con
+ 'EICRB_ISC6': '$30', # External Interrupt 6 Sense Con
+ 'EICRB_ISC5': '$c', # External Interrupt 5 Sense Con
+ 'EICRB_ISC4': '$3', # External Interrupt 4 Sense Con
+ 'EIMSK' : '$3d', # External Interrupt Mask Regist
+ 'EIMSK_INT': '$ff', # External Interrupt Request Ena
+ 'EIFR' : '$3c', # External Interrupt Flag Regist
+ 'EIFR_INTF': '$ff', # External Interrupt Flag
+ 'PCMSK2' : '$6d', # Pin Change Mask Register 2
+ 'PCMSK2_PCINT': '$ff', # Pin Change Enable Mask
+ 'PCMSK1' : '$6c', # Pin Change Mask Register 1
+ 'PCMSK1_PCINT': '$ff', # Pin Change Enable Mask
+ 'PCMSK0' : '$6b', # Pin Change Mask Register 0
+ 'PCIFR' : '$3b', # Pin Change Interrupt Flag Regi
+ 'PCIFR_Res': '$f8', # Reserved Bit
+ 'PCIFR_PCIF': '$7', # Pin Change Interrupt Flags
+ 'PCICR' : '$68', # Pin Change Interrupt Control R
+ 'PCICR_Res': '$f8', # Reserved Bit
+ 'PCICR_PCIE': '$7', # Pin Change Interrupt Enables
+
+# Module AD_CONVERTER
+ 'ADMUX' : '$7c', # The ADC Multiplexer Selection
+ 'ADMUX_REFS': '$c0', # Reference Selection Bits
+ 'ADMUX_ADLAR': '$20', # ADC Left Adjust Result
+ 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
+ 'ADC' : '$78', # ADC Data Register Bytes
+ 'ADCSRA' : '$7a', # The ADC Control and Status Reg
+ 'ADCSRA_ADEN': '$80', # ADC Enable
+ 'ADCSRA_ADSC': '$40', # ADC Start Conversion
+ 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
+ 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
+ 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
+ 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
+ 'ADCSRB' : '$7b', # The ADC Control and Status Reg
+ 'ADCSRB_AVDDOK': '$80', # AVDD Supply Voltage OK
+ 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
+ 'ADCSRB_REFOK': '$20', # Reference Voltage OK
+ 'ADCSRB_ACCH': '$10', # Analog Channel Change
+ 'ADCSRB_MUX5': '$8', # Analog Channel and Gain Select
+ 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Source
+ 'ADCSRC' : '$77', # The ADC Control and Status Reg
+ 'ADCSRC_ADTHT': '$c0', # ADC Track-and-Hold Time
+ 'ADCSRC_Res0': '$20', # Reserved
+ 'ADCSRC_ADSUT': '$1f', # ADC Start-up Time
+ 'DIDR2' : '$7d', # Digital Input Disable Register
+ 'DIDR2_ADC15D': '$80', # Reserved Bits
+ 'DIDR2_ADC14D': '$40', # Reserved Bits
+ 'DIDR2_ADC13D': '$20', # Reserved Bits
+ 'DIDR2_ADC12D': '$10', # Reserved Bits
+ 'DIDR2_ADC11D': '$8', # Reserved Bits
+ 'DIDR2_ADC10D': '$4', # Reserved Bits
+ 'DIDR2_ADC9D': '$2', # Reserved Bits
+ 'DIDR2_ADC8D': '$1', # Reserved Bits
+ 'DIDR0' : '$7e', # Digital Input Disable Register
+ 'DIDR0_ADC7D': '$80', # Disable ADC7:0 Digital Input
+ 'DIDR0_ADC6D': '$40', # Disable ADC7:0 Digital Input
+ 'DIDR0_ADC5D': '$20', # Disable ADC7:0 Digital Input
+ 'DIDR0_ADC4D': '$10', # Disable ADC7:0 Digital Input
+ 'DIDR0_ADC3D': '$8', # Disable ADC7:0 Digital Input
+ 'DIDR0_ADC2D': '$4', # Disable ADC7:0 Digital Input
+ 'DIDR0_ADC1D': '$2', # Disable ADC7:0 Digital Input
+ 'DIDR0_ADC0D': '$1', # Disable ADC7:0 Digital Input
+
+# Module BOOT_LOAD
+ 'SPMCSR' : '$57', # Store Program Memory Control R
+ 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
+ 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
+ 'SPMCSR_SIGRD': '$20', # Signature Row Read
+ 'SPMCSR_RWWSRE': '$10', # Read While Write Section Read
+ 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
+ 'SPMCSR_PGWRT': '$4', # Page Write
+ 'SPMCSR_PGERS': '$2', # Page Erase
+ 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
+
+# Module CPU
+ 'SREG' : '$5f', # Status Register
+ 'SREG_I': '$80', # Global Interrupt Enable
+ 'SREG_T': '$40', # Bit Copy Storage
+ 'SREG_H': '$20', # Half Carry Flag
+ 'SREG_S': '$10', # Sign Bit
+ 'SREG_V': '$8', # Two's Complement Overflow Flag
+ 'SREG_N': '$4', # Negative Flag
+ 'SREG_Z': '$2', # Zero Flag
+ 'SREG_C': '$1', # Carry Flag
+ 'SP' : '$5d', # Stack Pointer
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_JTD': '$80', # JTAG Interface Disable
+ 'MCUCR_Res': '$60', # Reserved
+ 'MCUCR_PUD': '$10', # Pull-up Disable
+ 'MCUCR_Res': '$c', # Reserved
+ 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
+ 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_Res': '$e0', # Reserved
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+ 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
+ 'MCUSR_BORF': '$4', # Brown-out Reset Flag
+ 'MCUSR_EXTRF': '$2', # External Reset Flag
+ 'MCUSR_PORF': '$1', # Power-on Reset Flag
+ 'OSCCAL' : '$66', # Oscillator Calibration Value
+ 'OSCCAL_CAL': '$ff', # Oscillator Calibration Tuning
+ 'CLKPR' : '$61', # Clock Prescale Register
+ 'CLKPR_CLKPCE': '$80', # Clock Prescaler Change Enable
+ 'CLKPR_Res': '$70', # Reserved
+ 'CLKPR_CLKPS': '$f', # Clock Prescaler Select Bits
+ 'SMCR' : '$53', # Sleep Mode Control Register
+ 'SMCR_Res': '$f0', # Reserved
+ 'SMCR_SM': '$e', # Sleep Mode Select bits
+ 'SMCR_SE': '$1', # Sleep Enable
+ 'EIND' : '$5c', # Extended Indirect Register
+ 'RAMPZ' : '$5b', # Extended Z-pointer Register fo
+ 'RAMPZ_Res': '$fc', # Reserved
+ 'RAMPZ_RAMPZ': '$3', # Extended Z-Pointer Value
+ 'GPIOR2' : '$4b', # General Purpose I/O Register 2
+ 'GPIOR2_GPIOR': '$ff', # General Purpose I/O Register 2
+ 'GPIOR1' : '$4a', # General Purpose IO Register 1
+ 'GPIOR1_GPIOR': '$ff', # General Purpose I/O Register 1
+ 'GPIOR0' : '$3e', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR07': '$80', # General Purpose I/O Register 0
+ 'GPIOR0_GPIOR06': '$40', # General Purpose I/O Register 0
+ 'GPIOR0_GPIOR05': '$20', # General Purpose I/O Register 0
+ 'GPIOR0_GPIOR04': '$10', # General Purpose I/O Register 0
+ 'GPIOR0_GPIOR03': '$8', # General Purpose I/O Register 0
+ 'GPIOR0_GPIOR02': '$4', # General Purpose I/O Register 0
+ 'GPIOR0_GPIOR01': '$2', # General Purpose I/O Register 0
+ 'GPIOR0_GPIOR00': '$1', # General Purpose I/O Register 0
+ 'PRR2' : '$63', # Power Reduction Register 2
+ 'PRR2_Res': '$f0', # Reserved Bit
+ 'PRR2_PRRAM': '$f', # Power Reduction SRAMs
+ 'PRR1' : '$65', # Power Reduction Register 1
+ 'PRR1_Res': '$80', # Reserved Bit
+ 'PRR1_PRTRX24': '$40', # Power Reduction Transceiver
+ 'PRR1_PRTIM5': '$20', # Power Reduction Timer/Counter5
+ 'PRR1_PRTIM4': '$10', # Power Reduction Timer/Counter4
+ 'PRR1_PRTIM3': '$8', # Power Reduction Timer/Counter3
+ 'PRR1_PRUSART1': '$1', # Power Reduction USART1
+ 'PRR0' : '$64', # Power Reduction Register0
+ 'PRR0_PRTWI': '$80', # Power Reduction TWI
+ 'PRR0_PRTIM2': '$40', # Power Reduction Timer/Counter2
+ 'PRR0_PRTIM0': '$20', # Power Reduction Timer/Counter0
+ 'PRR0_PRPGA': '$10', # Power Reduction PGA
+ 'PRR0_PRTIM1': '$8', # Power Reduction Timer/Counter1
+ 'PRR0_PRSPI': '$4', # Power Reduction Serial Periphe
+ 'PRR0_PRUSART0': '$2', # Power Reduction USART
+ 'PRR0_PRADC': '$1', # Power Reduction ADC
+
+# Module FLASH
+ 'NEMCR' : '$75', # Flash Extended-Mode Control-Re
+ 'NEMCR_ENEAM': '$40', # Enable Extended Address Mode f
+ 'NEMCR_AEAM': '$30', # Address for Extended Address M
+ 'BGCR' : '$67', # Reference Voltage Calibration
+ 'BGCR_Res': '$80', # Reserved Bit
+ 'BGCR_BGCAL_FINE': '$78', # Fine Calibration Bits
+ 'BGCR_BGCAL': '$7', # Coarse Calibration Bits
+
+# Module PWRCTRL
+ 'TRXPR' : '$139', # Transceiver Pin Register
+ 'TRXPR_Res': '$f0', # Reserved
+ 'TRXPR_SLPTR': '$2', # Multi-purpose Transceiver Cont
+ 'TRXPR_TRXRST': '$1', # Force Transceiver Reset
+ 'DRTRAM0' : '$135', # Data Retention Configuration R
+ 'DRTRAM0_Res': '$c0', # Reserved
+ 'DRTRAM0_DRTSWOK': '$20', # DRT Switch OK
+ 'DRTRAM0_ENDRT': '$10', # Enable SRAM Data Retention
+ 'DRTRAM1' : '$134', # Data Retention Configuration R
+ 'DRTRAM1_Res': '$c0', # Reserved
+ 'DRTRAM1_DRTSWOK': '$20', # DRT Switch OK
+ 'DRTRAM1_ENDRT': '$10', # Enable SRAM Data Retention
+ 'DRTRAM2' : '$133', # Data Retention Configuration R
+ 'DRTRAM2_Res': '$40', # Reserved Bit
+ 'DRTRAM2_DRTSWOK': '$20', # DRT Switch OK
+ 'DRTRAM2_ENDRT': '$10', # Enable SRAM Data Retention
+ 'DRTRAM3' : '$132', # Data Retention Configuration R
+ 'DRTRAM3_Res': '$c0', # Reserved
+ 'DRTRAM3_DRTSWOK': '$20', # DRT Switch OK
+ 'DRTRAM3_ENDRT': '$10', # Enable SRAM Data Retention
+ 'LLDRL' : '$130', # Low Leakage Voltage Regulator
+ 'LLDRL_Res': '$f0', # Reserved
+ 'LLDRL_LLDRL': '$f', # Low-Byte Data Register Bits
+ 'LLDRH' : '$131', # Low Leakage Voltage Regulator
+ 'LLDRH_Res': '$e0', # Reserved
+ 'LLDRH_LLDRH': '$1f', # High-Byte Data Register Bits
+ 'LLCR' : '$12f', # Low Leakage Voltage Regulator
+ 'LLCR_Res': '$c0', # Reserved Bit
+ 'LLCR_LLDONE': '$20', # Calibration Done
+ 'LLCR_LLCOMP': '$10', # Comparator Output
+ 'LLCR_LLCAL': '$8', # Calibration Active
+ 'LLCR_LLTCO': '$4', # Temperature Coefficient of Cur
+ 'LLCR_LLSHORT': '$2', # Short Lower Calibration Circui
+ 'LLCR_LLENCAL': '$1', # Enable Automatic Calibration
+ 'DPDS0' : '$136', # Port Driver Strength Register
+ 'DPDS0_PFDRV': '$c0', # Driver Strength Port F
+ 'DPDS0_PEDRV': '$30', # Driver Strength Port E
+ 'DPDS0_PDDRV': '$c', # Driver Strength Port D
+ 'DPDS0_PBDRV': '$3', # Driver Strength Port B
+ 'DPDS1' : '$137', # Port Driver Strength Register
+ 'DPDS1_Res': '$fc', # Reserved
+ 'DPDS1_PGDRV': '$3', # Driver Strength Port G
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_PUD': '$10', # Pull-up Disable
+
+# Module USART0_SPI
+ 'UCSR0A' : '$c0', # USART0 MSPIM Control and Statu
+ 'UCSR0A_RXC0': '$80', # USART Receive Complete
+ 'UCSR0A_TXC0': '$40', # USART Transmit Complete
+ 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
+ 'UCSR0B' : '$c1', # USART0 MSPIM Control and Statu
+ 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
+ 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
+ 'UCSR0B_UDRIE0': '$20', # USART Data Register Empty Inte
+ 'UCSR0B_RXEN0': '$10', # Receiver Enable
+ 'UCSR0B_TXEN0': '$8', # Transmitter Enable
+ 'UCSR0C' : '$c2', # USART0 MSPIM Control and Statu
+ 'UCSR0C_UDORD0': '$4', # Data Order
+ 'UCSR0C_UCPHA0': '$2', # Clock Phase
+ 'UCSR0C_UCPOL0': '$1', # Clock Polarity
+
+# Module USART1_SPI
+ 'UCSR1A' : '$c8', # USART1 MSPIM Control and Statu
+ 'UCSR1A_RXC1': '$80', # USART Receive Complete
+ 'UCSR1A_TXC1': '$40', # USART Transmit Complete
+ 'UCSR1A_UDRE1': '$20', # USART Data Register Empty
+ 'UCSR1B' : '$c9', # USART1 MSPIM Control and Statu
+ 'UCSR1B_RXCIE1': '$80', # RX Complete Interrupt Enable
+ 'UCSR1B_TXCIE1': '$40', # TX Complete Interrupt Enable
+ 'UCSR1B_UDRIE1': '$20', # USART Data Register Empty Inte
+ 'UCSR1B_RXEN1': '$10', # Receiver Enable
+ 'UCSR1B_TXEN1': '$8', # Transmitter Enable
+ 'UCSR1C' : '$ca', # USART1 MSPIM Control and Statu
+ 'UCSR1C_UDORD1': '$4', # Data Order
+ 'UCSR1C_UCPHA1': '$2', # Clock Phase
+ 'UCSR1C_UCPOL1': '$1', # Clock Polarity
+
+ '__amforth_dummy':'0'
+}
diff --git a/amforth-6.5/avr8/devices/atmega32/atmega32.frt b/amforth-6.5/avr8/devices/atmega32/atmega32.frt
new file mode 100644
index 0000000..522ee66
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega32/atmega32.frt
@@ -0,0 +1,216 @@
+\ Partname: ATmega32
+\ generated automatically
+
+\ EEPROM
+&62 constant EEAR \ EEPROM Read/Write Access Bytes
+&61 constant EEDR \ EEPROM Data Register
+&60 constant EECR \ EEPROM Control Register
+ $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
+ $04 constant EECR_EEMWE \ EEPROM Master Write Enable
+ $02 constant EECR_EEWE \ EEPROM Write Enable
+ $01 constant EECR_EERE \ EEPROM Read Enable
+\ WATCHDOG
+&65 constant WDTCR \ Watchdog Timer Control Register
+ $10 constant WDTCR_WDTOE \ RW
+ $08 constant WDTCR_WDE \ Watch Dog Enable
+ $07 constant WDTCR_WDP \ Watch Dog Timer Prescaler bits
+\ EXTERNAL_INTERRUPT
+&91 constant GICR \ General Interrupt Control Register
+ $C0 constant GICR_INT \ External Interrupt Request 1 Enable
+ $20 constant GICR_INT2 \ External Interrupt Request 2 Enable
+ $02 constant GICR_IVSEL \ Interrupt Vector Select
+ $01 constant GICR_IVCE \ Interrupt Vector Change Enable
+&90 constant GIFR \ General Interrupt Flag Register
+ $C0 constant GIFR_INTF \ External Interrupt Flags
+ $20 constant GIFR_INTF2 \ External Interrupt Flag 2
+&85 constant MCUCR \ General Interrupt Control Register
+ $0C constant MCUCR_ISC1 \ Interrupt Sense Control 1 Bits
+ $03 constant MCUCR_ISC0 \ Interrupt Sense Control 0 Bits
+&84 constant MCUCSR \ MCU Control And Status Register
+ $40 constant MCUCSR_ISC2 \ Interrupt Sense Control 2
+\ TIMER_COUNTER_0
+&83 constant TCCR0 \ Timer/Counter Control Register
+ $80 constant TCCR0_FOC0 \ Force Output Compare
+ $40 constant TCCR0_WGM00 \ Waveform Generation Mode
+ $30 constant TCCR0_COM0 \ Compare Match Output Modes
+ $08 constant TCCR0_WGM01 \ Waveform Generation Mode 1
+ $07 constant TCCR0_CS0 \ Clock Selects
+&82 constant TCNT0 \ Timer/Counter Register
+&92 constant OCR0 \ Output Compare Register
+&89 constant TIMSK \ Timer/Counter Interrupt Mask Register
+ $02 constant TIMSK_OCIE0 \ Timer/Counter0 Output Compare Match Interrupt register
+ $01 constant TIMSK_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
+&88 constant TIFR \ Timer/Counter Interrupt Flag register
+ $02 constant TIFR_OCF0 \ Output Compare Flag 0
+ $01 constant TIFR_TOV0 \ Timer/Counter0 Overflow Flag
+\ TIMER_COUNTER_2
+&69 constant TCCR2 \ Timer/Counter2 Control Register
+ $80 constant TCCR2_FOC2 \ Force Output Compare
+ $40 constant TCCR2_WGM20 \ Pulse Width Modulator Enable
+ $30 constant TCCR2_COM2 \ Compare Output Mode bits
+ $08 constant TCCR2_WGM21 \ Clear Timer/Counter2 on Compare Match
+ $07 constant TCCR2_CS2 \ Clock Select bits
+&68 constant TCNT2 \ Timer/Counter2
+&67 constant OCR2 \ Timer/Counter2 Output Compare Register
+&66 constant ASSR \ Asynchronous Status Register
+ $08 constant ASSR_AS2 \ Asynchronous Timer/counter2
+ $04 constant ASSR_TCN2UB \ Timer/Counter2 Update Busy
+ $02 constant ASSR_OCR2UB \ Output Compare Register2 Update Busy
+ $01 constant ASSR_TCR2UB \ Timer/counter Control Register2 Update Busy
+\ TIMER_COUNTER_1
+&79 constant TCCR1A \ Timer/Counter1 Control Register A
+ $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
+ $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
+ $08 constant TCCR1A_FOC1A \ Force Output Compare 1A
+ $04 constant TCCR1A_FOC1B \ Force Output Compare 1B
+ $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
+&78 constant TCCR1B \ Timer/Counter1 Control Register B
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
+ $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
+&76 constant TCNT1 \ Timer/Counter1 Bytes
+&74 constant OCR1A \ Timer/Counter1 Output Compare Register Bytes
+&72 constant OCR1B \ Timer/Counter1 Output Compare Register Bytes
+&70 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
+\ SPI
+&47 constant SPDR \ SPI Data Register
+&46 constant SPSR \ SPI Status Register
+ $80 constant SPSR_SPIF \ SPI Interrupt Flag
+ $40 constant SPSR_WCOL \ Write Collision Flag
+ $01 constant SPSR_SPI2X \ Double SPI Speed Bit
+&45 constant SPCR \ SPI Control Register
+ $80 constant SPCR_SPIE \ SPI Interrupt Enable
+ $40 constant SPCR_SPE \ SPI Enable
+ $20 constant SPCR_DORD \ Data Order
+ $10 constant SPCR_MSTR \ Master/Slave Select
+ $08 constant SPCR_CPOL \ Clock polarity
+ $04 constant SPCR_CPHA \ Clock Phase
+ $03 constant SPCR_SPR \ SPI Clock Rate Selects
+\ USART
+&44 constant UDR \ USART I/O Data Register
+&43 constant UCSRA \ USART Control and Status Register A
+ $80 constant UCSRA_RXC \ USART Receive Complete
+ $40 constant UCSRA_TXC \ USART Transmitt Complete
+ $20 constant UCSRA_UDRE \ USART Data Register Empty
+ $10 constant UCSRA_FE \ Framing Error
+ $08 constant UCSRA_DOR \ Data overRun
+ $04 constant UCSRA_UPE \ Parity Error
+ $02 constant UCSRA_U2X \ Double the USART transmission speed
+ $01 constant UCSRA_MPCM \ Multi-processor Communication Mode
+&42 constant UCSRB \ USART Control and Status Register B
+ $80 constant UCSRB_RXCIE \ RX Complete Interrupt Enable
+ $40 constant UCSRB_TXCIE \ TX Complete Interrupt Enable
+ $20 constant UCSRB_UDRIE \ USART Data register Empty Interrupt Enable
+ $10 constant UCSRB_RXEN \ Receiver Enable
+ $08 constant UCSRB_TXEN \ Transmitter Enable
+ $04 constant UCSRB_UCSZ2 \ Character Size
+ $02 constant UCSRB_RXB8 \ Receive Data Bit 8
+ $01 constant UCSRB_TXB8 \ Transmit Data Bit 8
+&64 constant UCSRC \ USART Control and Status Register C
+ $80 constant UCSRC_URSEL \ Register Select
+ $40 constant UCSRC_UMSEL \ USART Mode Select
+ $30 constant UCSRC_UPM \ Parity Mode Bits
+ $08 constant UCSRC_USBS \ Stop Bit Select
+ $06 constant UCSRC_UCSZ \ Character Size
+ $01 constant UCSRC_UCPOL \ Clock Polarity
+&64 constant UBRRH \ USART Baud Rate Register Hight Byte
+&41 constant UBRRL \ USART Baud Rate Register Low Byte
+\ ANALOG_COMPARATOR
+&80 constant SFIOR \ Special Function IO Register
+ $08 constant SFIOR_ACME \ Analog Comparator Multiplexer Enable
+&40 constant ACSR \ Analog Comparator Control And Status Register
+ $80 constant ACSR_ACD \ Analog Comparator Disable
+ $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
+ $20 constant ACSR_ACO \ Analog Compare Output
+ $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
+ $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
+ $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
+ $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
+\ AD_CONVERTER
+&39 constant ADMUX \ The ADC multiplexer Selection Register
+ $C0 constant ADMUX_REFS \ Reference Selection Bits
+ $20 constant ADMUX_ADLAR \ Left Adjust Result
+ $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
+&38 constant ADCSRA \ The ADC Control and Status register
+ $80 constant ADCSRA_ADEN \ ADC Enable
+ $40 constant ADCSRA_ADSC \ ADC Start Conversion
+ $20 constant ADCSRA_ADATE \ When this bit is written to one,the Timer/Counter2 prescaler will be reset.The bit will be cleared by hardware after the operation is performed.Writing a zero to this bit will have no effect.This bit will always be read as zero if Timer/Counter2 is clocked by the internal CPU clock.If this bit is written when Timer/Counter2 is operating in asynchronous mode,the bit will remain one until the prescaler has been reset.
+ $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
+ $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
+ $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
+&36 constant ADC \ ADC Data Register Bytes
+\ PORTA
+&59 constant PORTA \ Port A Data Register
+&58 constant DDRA \ Port A Data Direction Register
+&57 constant PINA \ Port A Input Pins
+\ PORTB
+&56 constant PORTB \ Port B Data Register
+&55 constant DDRB \ Port B Data Direction Register
+&54 constant PINB \ Port B Input Pins
+\ PORTC
+&53 constant PORTC \ Port C Data Register
+&52 constant DDRC \ Port C Data Direction Register
+&51 constant PINC \ Port C Input Pins
+\ PORTD
+&50 constant PORTD \ Port D Data Register
+&49 constant DDRD \ Port D Data Direction Register
+&48 constant PIND \ Port D Input Pins
+\ CPU
+&95 constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ $08 constant SREG_V \ Two's Complement Overflow Flag
+ $04 constant SREG_N \ Negative Flag
+ $02 constant SREG_Z \ Zero Flag
+ $01 constant SREG_C \ Carry Flag
+&93 constant SP \ Stack Pointer
+&81 constant OSCCAL \ Oscillator Calibration Value
+\ BOOT_LOAD
+&87 constant SPMCR \ Store Program Memory Control Register
+ $80 constant SPMCR_SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCR_RWWSB \ Read While Write Section Busy
+ $10 constant SPMCR_RWWSRE \ Read While Write secion read enable
+ $08 constant SPMCR_BLBSET \ Boot Lock Bit Set
+ $04 constant SPMCR_PGWRT \ Page Write
+ $02 constant SPMCR_PGERS \ Page Erase
+ $01 constant SPMCR_SPMEN \ Store Program Memory Enable
+\ TWI
+&32 constant TWBR \ TWI Bit Rate register
+&86 constant TWCR \ TWI Control Register
+ $80 constant TWCR_TWINT \ TWI Interrupt Flag
+ $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
+ $20 constant TWCR_TWSTA \ TWI Start Condition Bit
+ $10 constant TWCR_TWSTO \ TWI Stop Condition Bit
+ $08 constant TWCR_TWWC \ TWI Write Collition Flag
+ $04 constant TWCR_TWEN \ TWI Enable Bit
+ $01 constant TWCR_TWIE \ TWI Interrupt Enable
+&33 constant TWSR \ TWI Status Register
+ $F8 constant TWSR_TWS \ TWI Status
+ $03 constant TWSR_TWPS \ TWI Prescaler bits
+&35 constant TWDR \ TWI Data register
+&34 constant TWAR \ TWI (Slave) Address register
+
+\ Interrupts
+&2 constant INT0Addr \ External Interrupt Request 0
+&4 constant INT1Addr \ External Interrupt Request 1
+&6 constant INT2Addr \ External Interrupt Request 2
+&8 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
+&10 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
+&12 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+&14 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
+&16 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
+&18 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+&20 constant TIMER0_COMPAddr \ Timer/Counter0 Compare Match
+&22 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
+&24 constant SPI__STCAddr \ Serial Transfer Complete
+&26 constant USART__RXCAddr \ USART, Rx Complete
+&28 constant USART__UDREAddr \ USART Data Register Empty
+&30 constant USART__TXCAddr \ USART, Tx Complete
+&32 constant ADCAddr \ ADC Conversion Complete
+&34 constant EE_RDYAddr \ EEPROM Ready
+&36 constant ANA_COMPAddr \ Analog Comparator
+&38 constant TWIAddr \ 2-wire Serial Interface
+&40 constant SPM_RDYAddr \ Store Program Memory Ready
diff --git a/amforth-6.5/avr8/devices/atmega32/device.asm b/amforth-6.5/avr8/devices/atmega32/device.asm
new file mode 100644
index 0000000..4e25271
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega32/device.asm
@@ -0,0 +1,101 @@
+; Partname: ATmega32
+; generated automatically, do not edit
+
+.nolist
+ .include "m32def.inc"
+.list
+
+.equ ramstart = 96
+.equ CELLSIZE = 2
+.macro readflashcell
+ lsl zl
+ rol zh
+ lpm @0, Z+
+ lpm @1, Z+
+.endmacro
+.macro writeflashcell
+ lsl zl
+ rol zh
+.endmacro
+.set WANT_EEPROM = 0
+.set WANT_WATCHDOG = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_TIMER_COUNTER_2 = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_SPI = 0
+.set WANT_USART = 0
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_AD_CONVERTER = 0
+.set WANT_PORTA = 0
+.set WANT_PORTB = 0
+.set WANT_PORTC = 0
+.set WANT_PORTD = 0
+.set WANT_CPU = 0
+.set WANT_BOOT_LOAD = 0
+.set WANT_TWI = 0
+.equ intvecsize = 2 ; please verify; flash size: 32768 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.org 2
+ rcall isr ; External Interrupt Request 0
+.org 4
+ rcall isr ; External Interrupt Request 1
+.org 6
+ rcall isr ; External Interrupt Request 2
+.org 8
+ rcall isr ; Timer/Counter2 Compare Match
+.org 10
+ rcall isr ; Timer/Counter2 Overflow
+.org 12
+ rcall isr ; Timer/Counter1 Capture Event
+.org 14
+ rcall isr ; Timer/Counter1 Compare Match A
+.org 16
+ rcall isr ; Timer/Counter1 Compare Match B
+.org 18
+ rcall isr ; Timer/Counter1 Overflow
+.org 20
+ rcall isr ; Timer/Counter0 Compare Match
+.org 22
+ rcall isr ; Timer/Counter0 Overflow
+.org 24
+ rcall isr ; Serial Transfer Complete
+.org 26
+ rcall isr ; USART, Rx Complete
+.org 28
+ rcall isr ; USART Data Register Empty
+.org 30
+ rcall isr ; USART, Tx Complete
+.org 32
+ rcall isr ; ADC Conversion Complete
+.org 34
+ rcall isr ; EEPROM Ready
+.org 36
+ rcall isr ; Analog Comparator
+.org 38
+ rcall isr ; 2-wire Serial Interface
+.org 40
+ rcall isr ; Store Program Memory Ready
+.equ INTVECTORS = 21
+.nooverlap
+
+; compatability layer (maybe empty)
+.equ SPMCSR = SPMCR
+.equ EEPE = EEWE
+.equ EEMPE = EEMWE
+
+; controller data area, environment query mcu-info
+mcu_info:
+mcu_ramsize:
+ .dw 2048
+mcu_eepromsize:
+ .dw 1024
+mcu_maxdp:
+ .dw 28672
+mcu_numints:
+ .dw 21
+mcu_name:
+ .dw 8
+ .db "ATmega32"
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega32/device.inc b/amforth-6.5/avr8/devices/atmega32/device.inc
new file mode 100644
index 0000000..fec57ca
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega32/device.inc
@@ -0,0 +1,750 @@
+; Partname: ATmega32
+; generated automatically, no not edit
+
+.if WANT_EEPROM == 1
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Read/Write Access Bytes
+VE_EEAR:
+ .dw $ff04
+ .db "EEAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEAR
+XT_EEAR:
+ .dw PFA_DOVARIABLE
+PFA_EEAR:
+ .dw 62
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw 61
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw 60
+
+.endif
+.if WANT_WATCHDOG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCR:
+ .dw $ff05
+ .db "WDTCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCR
+XT_WDTCR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCR:
+ .dw 65
+
+.endif
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ( -- addr ) System Constant
+; R( -- )
+; General Interrupt Control Register
+VE_GICR:
+ .dw $ff04
+ .db "GICR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GICR
+XT_GICR:
+ .dw PFA_DOVARIABLE
+PFA_GICR:
+ .dw 91
+; ( -- addr ) System Constant
+; R( -- )
+; General Interrupt Flag Register
+VE_GIFR:
+ .dw $ff04
+ .db "GIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GIFR
+XT_GIFR:
+ .dw PFA_DOVARIABLE
+PFA_GIFR:
+ .dw 90
+; ( -- addr ) System Constant
+; R( -- )
+; General Interrupt Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw 85
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control And Status Register
+VE_MCUCSR:
+ .dw $ff06
+ .db "MCUCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCSR
+XT_MCUCSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCSR:
+ .dw 84
+
+.endif
+.if WANT_TIMER_COUNTER_0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register
+VE_TCCR0:
+ .dw $ff05
+ .db "TCCR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0
+XT_TCCR0:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0:
+ .dw 83
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Register
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw 82
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare Register
+VE_OCR0:
+ .dw $ff04
+ .db "OCR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0
+XT_OCR0:
+ .dw PFA_DOVARIABLE
+PFA_OCR0:
+ .dw 92
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Mask Register
+VE_TIMSK:
+ .dw $ff05
+ .db "TIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK
+XT_TIMSK:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK:
+ .dw 89
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Flag register
+VE_TIFR:
+ .dw $ff04
+ .db "TIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR
+XT_TIFR:
+ .dw PFA_DOVARIABLE
+PFA_TIFR:
+ .dw 88
+
+.endif
+.if WANT_TIMER_COUNTER_2 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register
+VE_TCCR2:
+ .dw $ff05
+ .db "TCCR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2
+XT_TCCR2:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2:
+ .dw 69
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2
+VE_TCNT2:
+ .dw $ff05
+ .db "TCNT2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT2
+XT_TCNT2:
+ .dw PFA_DOVARIABLE
+PFA_TCNT2:
+ .dw 68
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register
+VE_OCR2:
+ .dw $ff04
+ .db "OCR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2
+XT_OCR2:
+ .dw PFA_DOVARIABLE
+PFA_OCR2:
+ .dw 67
+; ( -- addr ) System Constant
+; R( -- )
+; Asynchronous Status Register
+VE_ASSR:
+ .dw $ff04
+ .db "ASSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ASSR
+XT_ASSR:
+ .dw PFA_DOVARIABLE
+PFA_ASSR:
+ .dw 66
+
+.endif
+.if WANT_TIMER_COUNTER_1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw 79
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw 78
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Bytes
+VE_TCNT1:
+ .dw $ff05
+ .db "TCNT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1
+XT_TCNT1:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1:
+ .dw 76
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register Bytes
+VE_OCR1A:
+ .dw $ff05
+ .db "OCR1A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1A
+XT_OCR1A:
+ .dw PFA_DOVARIABLE
+PFA_OCR1A:
+ .dw 74
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register Bytes
+VE_OCR1B:
+ .dw $ff05
+ .db "OCR1B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1B
+XT_OCR1B:
+ .dw PFA_DOVARIABLE
+PFA_OCR1B:
+ .dw 72
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Bytes
+VE_ICR1:
+ .dw $ff04
+ .db "ICR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1
+XT_ICR1:
+ .dw PFA_DOVARIABLE
+PFA_ICR1:
+ .dw 70
+
+.endif
+.if WANT_SPI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR:
+ .dw $ff04
+ .db "SPDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR
+XT_SPDR:
+ .dw PFA_DOVARIABLE
+PFA_SPDR:
+ .dw 47
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR:
+ .dw $ff04
+ .db "SPSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR
+XT_SPSR:
+ .dw PFA_DOVARIABLE
+PFA_SPSR:
+ .dw 46
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR:
+ .dw $ff04
+ .db "SPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR
+XT_SPCR:
+ .dw PFA_DOVARIABLE
+PFA_SPCR:
+ .dw 45
+
+.endif
+.if WANT_USART == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR:
+ .dw $ff03
+ .db "UDR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR
+XT_UDR:
+ .dw PFA_DOVARIABLE
+PFA_UDR:
+ .dw 44
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSRA:
+ .dw $ff05
+ .db "UCSRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSRA
+XT_UCSRA:
+ .dw PFA_DOVARIABLE
+PFA_UCSRA:
+ .dw 43
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSRB:
+ .dw $ff05
+ .db "UCSRB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSRB
+XT_UCSRB:
+ .dw PFA_DOVARIABLE
+PFA_UCSRB:
+ .dw 42
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSRC:
+ .dw $ff05
+ .db "UCSRC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSRC
+XT_UCSRC:
+ .dw PFA_DOVARIABLE
+PFA_UCSRC:
+ .dw 64
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Hight Byte
+VE_UBRRH:
+ .dw $ff05
+ .db "UBRRH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRRH
+XT_UBRRH:
+ .dw PFA_DOVARIABLE
+PFA_UBRRH:
+ .dw 64
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Low Byte
+VE_UBRRL:
+ .dw $ff05
+ .db "UBRRL",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRRL
+XT_UBRRL:
+ .dw PFA_DOVARIABLE
+PFA_UBRRL:
+ .dw 41
+
+.endif
+.if WANT_ANALOG_COMPARATOR == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Special Function IO Register
+VE_SFIOR:
+ .dw $ff05
+ .db "SFIOR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SFIOR
+XT_SFIOR:
+ .dw PFA_DOVARIABLE
+PFA_SFIOR:
+ .dw 80
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Control And Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw 40
+
+.endif
+.if WANT_AD_CONVERTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC multiplexer Selection Register
+VE_ADMUX:
+ .dw $ff05
+ .db "ADMUX",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADMUX
+XT_ADMUX:
+ .dw PFA_DOVARIABLE
+PFA_ADMUX:
+ .dw 39
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register
+VE_ADCSRA:
+ .dw $ff06
+ .db "ADCSRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRA
+XT_ADCSRA:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRA:
+ .dw 38
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register Bytes
+VE_ADC:
+ .dw $ff03
+ .db "ADC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADC
+XT_ADC:
+ .dw PFA_DOVARIABLE
+PFA_ADC:
+ .dw 36
+
+.endif
+.if WANT_PORTA == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Register
+VE_PORTA:
+ .dw $ff05
+ .db "PORTA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTA
+XT_PORTA:
+ .dw PFA_DOVARIABLE
+PFA_PORTA:
+ .dw 59
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Direction Register
+VE_DDRA:
+ .dw $ff04
+ .db "DDRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRA
+XT_DDRA:
+ .dw PFA_DOVARIABLE
+PFA_DDRA:
+ .dw 58
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Input Pins
+VE_PINA:
+ .dw $ff04
+ .db "PINA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINA
+XT_PINA:
+ .dw PFA_DOVARIABLE
+PFA_PINA:
+ .dw 57
+
+.endif
+.if WANT_PORTB == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw 56
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw 55
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw 54
+
+.endif
+.if WANT_PORTC == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Register
+VE_PORTC:
+ .dw $ff05
+ .db "PORTC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTC
+XT_PORTC:
+ .dw PFA_DOVARIABLE
+PFA_PORTC:
+ .dw 53
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Direction Register
+VE_DDRC:
+ .dw $ff04
+ .db "DDRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRC
+XT_DDRC:
+ .dw PFA_DOVARIABLE
+PFA_DDRC:
+ .dw 52
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Input Pins
+VE_PINC:
+ .dw $ff04
+ .db "PINC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINC
+XT_PINC:
+ .dw PFA_DOVARIABLE
+PFA_PINC:
+ .dw 51
+
+.endif
+.if WANT_PORTD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw 50
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw 49
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw 48
+
+.endif
+.if WANT_CPU == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw 95
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer
+VE_SP:
+ .dw $ff02
+ .db "SP"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SP
+XT_SP:
+ .dw PFA_DOVARIABLE
+PFA_SP:
+ .dw 93
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Calibration Value
+VE_OSCCAL:
+ .dw $ff06
+ .db "OSCCAL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSCCAL
+XT_OSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_OSCCAL:
+ .dw 81
+
+.endif
+.if WANT_BOOT_LOAD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control Register
+VE_SPMCR:
+ .dw $ff05
+ .db "SPMCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCR
+XT_SPMCR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCR:
+ .dw 87
+
+.endif
+.if WANT_TWI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Bit Rate register
+VE_TWBR:
+ .dw $ff04
+ .db "TWBR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWBR
+XT_TWBR:
+ .dw PFA_DOVARIABLE
+PFA_TWBR:
+ .dw 32
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Control Register
+VE_TWCR:
+ .dw $ff04
+ .db "TWCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWCR
+XT_TWCR:
+ .dw PFA_DOVARIABLE
+PFA_TWCR:
+ .dw 86
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Status Register
+VE_TWSR:
+ .dw $ff04
+ .db "TWSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWSR
+XT_TWSR:
+ .dw PFA_DOVARIABLE
+PFA_TWSR:
+ .dw 33
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Data register
+VE_TWDR:
+ .dw $ff04
+ .db "TWDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWDR
+XT_TWDR:
+ .dw PFA_DOVARIABLE
+PFA_TWDR:
+ .dw 35
+; ( -- addr ) System Constant
+; R( -- )
+; TWI (Slave) Address register
+VE_TWAR:
+ .dw $ff04
+ .db "TWAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWAR
+XT_TWAR:
+ .dw PFA_DOVARIABLE
+PFA_TWAR:
+ .dw 34
+
+.endif
diff --git a/amforth-6.5/avr8/devices/atmega32/device.py b/amforth-6.5/avr8/devices/atmega32/device.py
new file mode 100644
index 0000000..73c9f77
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega32/device.py
@@ -0,0 +1,268 @@
+# Generated Automatically
+
+# Partname ATmega32
+
+MCUREGS = {
+# Interrupt Vectors
+ 'INT0Addr' : '#2', # External Interrupt Request 0
+ 'INT1Addr' : '#4', # External Interrupt Request 1
+ 'INT2Addr' : '#6', # External Interrupt Request 2
+ 'TIMER2_COMPAddr' : '#8', # Timer/Counter2 Compare Match
+ 'TIMER2_OVFAddr' : '#10', # Timer/Counter2 Overflow
+ 'TIMER1_CAPTAddr' : '#12', # Timer/Counter1 Capture Event
+ 'TIMER1_COMPAAddr' : '#14', # Timer/Counter1 Compare Match A
+ 'TIMER1_COMPBAddr' : '#16', # Timer/Counter1 Compare Match B
+ 'TIMER1_OVFAddr' : '#18', # Timer/Counter1 Overflow
+ 'TIMER0_COMPAddr' : '#20', # Timer/Counter0 Compare Match
+ 'TIMER0_OVFAddr' : '#22', # Timer/Counter0 Overflow
+ 'SPI_STCAddr' : '#24', # Serial Transfer Complete
+ 'USART_RXCAddr' : '#26', # USART, Rx Complete
+ 'USART_UDREAddr' : '#28', # USART Data Register Empty
+ 'USART_TXCAddr' : '#30', # USART, Tx Complete
+ 'ADCAddr' : '#32', # ADC Conversion Complete
+ 'EE_RDYAddr' : '#34', # EEPROM Ready
+ 'ANA_COMPAddr' : '#36', # Analog Comparator
+ 'TWIAddr' : '#38', # 2-wire Serial Interface
+ 'SPM_RDYAddr' : '#40', # Store Program Memory Ready
+
+# Module EEPROM
+ 'EEAR' : '$3e', # EEPROM Read/Write Access Byte
+ 'EEDR' : '$3d', # EEPROM Data Register
+ 'EECR' : '$3c', # EEPROM Control Register
+ 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
+ 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
+ 'EECR_EEWE': '$2', # EEPROM Write Enable
+ 'EECR_EERE': '$1', # EEPROM Read Enable
+
+# Module WATCHDOG
+ 'WDTCR' : '$41', # Watchdog Timer Control Registe
+ 'WDTCR_WDTOE': '$10', # RW
+ 'WDTCR_WDE': '$8', # Watch Dog Enable
+ 'WDTCR_WDP': '$7', # Watch Dog Timer Prescaler bits
+
+# Module EXTERNAL_INTERRUPT
+ 'GICR' : '$5b', # General Interrupt Control Regi
+ 'GICR_INT': '$c0', # External Interrupt Request 1 E
+ 'GICR_INT2': '$20', # External Interrupt Request 2 E
+ 'GICR_IVSEL': '$2', # Interrupt Vector Select
+ 'GICR_IVCE': '$1', # Interrupt Vector Change Enable
+ 'GIFR' : '$5a', # General Interrupt Flag Registe
+ 'GIFR_INTF': '$c0', # External Interrupt Flags
+ 'GIFR_INTF2': '$20', # External Interrupt Flag 2
+ 'MCUCR' : '$55', # General Interrupt Control Regi
+ 'MCUCR_ISC1': '$c', # Interrupt Sense Control 1 Bits
+ 'MCUCR_ISC0': '$3', # Interrupt Sense Control 0 Bits
+ 'MCUCSR' : '$54', # MCU Control And Status Registe
+ 'MCUCSR_ISC2': '$40', # Interrupt Sense Control 2
+
+# Module TIMER_COUNTER_0
+ 'TCCR0' : '$53', # Timer/Counter Control Register
+ 'TCCR0_FOC0': '$80', # Force Output Compare
+ 'TCCR0_WGM00': '$40', # Waveform Generation Mode
+ 'TCCR0_COM0': '$30', # Compare Match Output Modes
+ 'TCCR0_WGM01': '$8', # Waveform Generation Mode 1
+ 'TCCR0_CS0': '$7', # Clock Selects
+ 'TCNT0' : '$52', # Timer/Counter Register
+ 'OCR0' : '$5c', # Output Compare Register
+ 'TIMSK' : '$59', # Timer/Counter Interrupt Mask R
+ 'TIMSK_OCIE0': '$2', # Timer/Counter0 Output Compare
+ 'TIMSK_TOIE0': '$1', # Timer/Counter0 Overflow Interr
+ 'TIFR' : '$58', # Timer/Counter Interrupt Flag r
+ 'TIFR_OCF0': '$2', # Output Compare Flag 0
+ 'TIFR_TOV0': '$1', # Timer/Counter0 Overflow Flag
+
+# Module TIMER_COUNTER_2
+ 'TIMSK' : '$59', # Timer/Counter Interrupt Mask r
+ 'TIMSK_OCIE2': '$80', # Timer/Counter2 Output Compare
+ 'TIMSK_TOIE2': '$40', # Timer/Counter2 Overflow Interr
+ 'TIFR' : '$58', # Timer/Counter Interrupt Flag R
+ 'TIFR_OCF2': '$80', # Output Compare Flag 2
+ 'TIFR_TOV2': '$40', # Timer/Counter2 Overflow Flag
+ 'TCCR2' : '$45', # Timer/Counter2 Control Registe
+ 'TCCR2_FOC2': '$80', # Force Output Compare
+ 'TCCR2_WGM20': '$40', # Pulse Width Modulator Enable
+ 'TCCR2_COM2': '$30', # Compare Output Mode bits
+ 'TCCR2_WGM21': '$8', # Clear Timer/Counter2 on Compar
+ 'TCCR2_CS2': '$7', # Clock Select bits
+ 'TCNT2' : '$44', # Timer/Counter2
+ 'OCR2' : '$43', # Timer/Counter2 Output Compare
+ 'ASSR' : '$42', # Asynchronous Status Register
+ 'ASSR_AS2': '$8', # Asynchronous Timer/counter2
+ 'ASSR_TCN2UB': '$4', # Timer/Counter2 Update Busy
+ 'ASSR_OCR2UB': '$2', # Output Compare Register2 Updat
+ 'ASSR_TCR2UB': '$1', # Timer/counter Control Register
+
+# Module TIMER_COUNTER_1
+ 'TIMSK' : '$59', # Timer/Counter Interrupt Mask R
+ 'TIMSK_TICIE1': '$20', # Timer/Counter1 Input Capture I
+ 'TIMSK_OCIE1A': '$10', # Timer/Counter1 Output CompareA
+ 'TIMSK_OCIE1B': '$8', # Timer/Counter1 Output CompareB
+ 'TIMSK_TOIE1': '$4', # Timer/Counter1 Overflow Interr
+ 'TIFR' : '$58', # Timer/Counter Interrupt Flag r
+ 'TIFR_ICF1': '$20', # Input Capture Flag 1
+ 'TIFR_OCF1A': '$10', # Output Compare Flag 1A
+ 'TIFR_OCF1B': '$8', # Output Compare Flag 1B
+ 'TIFR_TOV1': '$4', # Timer/Counter1 Overflow Flag
+ 'TCCR1A' : '$4f', # Timer/Counter1 Control Registe
+ 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
+ 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
+ 'TCCR1A_FOC1A': '$8', # Force Output Compare 1A
+ 'TCCR1A_FOC1B': '$4', # Force Output Compare 1B
+ 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
+ 'TCCR1B' : '$4e', # Timer/Counter1 Control Registe
+ 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
+ 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
+ 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
+ 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
+ 'TCNT1' : '$4c', # Timer/Counter1 Bytes
+ 'OCR1A' : '$4a', # Timer/Counter1 Output Compare
+ 'OCR1B' : '$48', # Timer/Counter1 Output Compare
+ 'ICR1' : '$46', # Timer/Counter1 Input Capture R
+
+# Module SPI
+ 'SPDR' : '$2f', # SPI Data Register
+ 'SPSR' : '$2e', # SPI Status Register
+ 'SPSR_SPIF': '$80', # SPI Interrupt Flag
+ 'SPSR_WCOL': '$40', # Write Collision Flag
+ 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
+ 'SPCR' : '$2d', # SPI Control Register
+ 'SPCR_SPIE': '$80', # SPI Interrupt Enable
+ 'SPCR_SPE': '$40', # SPI Enable
+ 'SPCR_DORD': '$20', # Data Order
+ 'SPCR_MSTR': '$10', # Master/Slave Select
+ 'SPCR_CPOL': '$8', # Clock polarity
+ 'SPCR_CPHA': '$4', # Clock Phase
+ 'SPCR_SPR': '$3', # SPI Clock Rate Selects
+
+# Module USART
+ 'UDR' : '$2c', # USART I/O Data Register
+ 'UCSRA' : '$2b', # USART Control and Status Regis
+ 'UCSRA_RXC': '$80', # USART Receive Complete
+ 'UCSRA_TXC': '$40', # USART Transmitt Complete
+ 'UCSRA_UDRE': '$20', # USART Data Register Empty
+ 'UCSRA_FE': '$10', # Framing Error
+ 'UCSRA_DOR': '$8', # Data overRun
+ 'UCSRA_UPE': '$4', # Parity Error
+ 'UCSRA_U2X': '$2', # Double the USART transmission
+ 'UCSRA_MPCM': '$1', # Multi-processor Communication
+ 'UCSRB' : '$2a', # USART Control and Status Regis
+ 'UCSRB_RXCIE': '$80', # RX Complete Interrupt Enable
+ 'UCSRB_TXCIE': '$40', # TX Complete Interrupt Enable
+ 'UCSRB_UDRIE': '$20', # USART Data register Empty Inte
+ 'UCSRB_RXEN': '$10', # Receiver Enable
+ 'UCSRB_TXEN': '$8', # Transmitter Enable
+ 'UCSRB_UCSZ2': '$4', # Character Size
+ 'UCSRB_RXB8': '$2', # Receive Data Bit 8
+ 'UCSRB_TXB8': '$1', # Transmit Data Bit 8
+ 'UCSRC' : '$40', # USART Control and Status Regis
+ 'UCSRC_URSEL': '$80', # Register Select
+ 'UCSRC_UMSEL': '$40', # USART Mode Select
+ 'UCSRC_UPM': '$30', # Parity Mode Bits
+ 'UCSRC_USBS': '$8', # Stop Bit Select
+ 'UCSRC_UCSZ': '$6', # Character Size
+ 'UCSRC_UCPOL': '$1', # Clock Polarity
+ 'UBRRH' : '$40', # USART Baud Rate Register Hight
+ 'UBRRL' : '$29', # USART Baud Rate Register Low B
+
+# Module ANALOG_COMPARATOR
+ 'SFIOR' : '$50', # Special Function IO Register
+ 'SFIOR_ACME': '$8', # Analog Comparator Multiplexer
+ 'ACSR' : '$28', # Analog Comparator Control And
+ 'ACSR_ACD': '$80', # Analog Comparator Disable
+ 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
+ 'ACSR_ACO': '$20', # Analog Compare Output
+ 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
+ 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
+ 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
+ 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
+
+# Module AD_CONVERTER
+ 'ADMUX' : '$27', # The ADC multiplexer Selection
+ 'ADMUX_REFS': '$c0', # Reference Selection Bits
+ 'ADMUX_ADLAR': '$20', # Left Adjust Result
+ 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
+ 'ADCSRA' : '$26', # The ADC Control and Status reg
+ 'ADCSRA_ADEN': '$80', # ADC Enable
+ 'ADCSRA_ADSC': '$40', # ADC Start Conversion
+ 'ADCSRA_ADATE': '$20', # When this bit is written to on
+ 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
+ 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
+ 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
+ 'ADC' : '$24', # ADC Data Register Bytes
+ 'SFIOR' : '$50', # Special Function IO Register
+ 'SFIOR_ADTS': '$e0', # ADC Auto Trigger Sources
+
+# Module PORTA
+ 'PORTA' : '$3b', # Port A Data Register
+ 'DDRA' : '$3a', # Port A Data Direction Register
+ 'PINA' : '$39', # Port A Input Pins
+
+# Module PORTB
+ 'PORTB' : '$38', # Port B Data Register
+ 'DDRB' : '$37', # Port B Data Direction Register
+ 'PINB' : '$36', # Port B Input Pins
+
+# Module PORTC
+ 'PORTC' : '$35', # Port C Data Register
+ 'DDRC' : '$34', # Port C Data Direction Register
+ 'PINC' : '$33', # Port C Input Pins
+
+# Module PORTD
+ 'PORTD' : '$32', # Port D Data Register
+ 'DDRD' : '$31', # Port D Data Direction Register
+ 'PIND' : '$30', # Port D Input Pins
+
+# Module CPU
+ 'SREG' : '$5f', # Status Register
+ 'SREG_I': '$80', # Global Interrupt Enable
+ 'SREG_T': '$40', # Bit Copy Storage
+ 'SREG_H': '$20', # Half Carry Flag
+ 'SREG_S': '$10', # Sign Bit
+ 'SREG_V': '$8', # Two's Complement Overflow Flag
+ 'SREG_N': '$4', # Negative Flag
+ 'SREG_Z': '$2', # Zero Flag
+ 'SREG_C': '$1', # Carry Flag
+ 'SP' : '$5d', # Stack Pointer
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_SE': '$80', # Sleep Enable
+ 'MCUCR_SM': '$70', # Sleep Mode Select
+ 'MCUCR_ISC1': '$c', # Interrupt Sense Control 1 Bits
+ 'MCUCR_ISC0': '$3', # Interrupt Sense Control 0 Bits
+ 'MCUCSR' : '$54', # MCU Control And Status Registe
+ 'MCUCSR_JTD': '$80', # JTAG Interface Disable
+ 'MCUCSR_JTRF': '$10', # JTAG Reset Flag
+ 'MCUCSR_WDRF': '$8', # Watchdog Reset Flag
+ 'MCUCSR_BORF': '$4', # Brown-out Reset Flag
+ 'MCUCSR_EXTRF': '$2', # External Reset Flag
+ 'MCUCSR_PORF': '$1', # Power-on reset flag
+ 'OSCCAL' : '$51', # Oscillator Calibration Value
+ 'SFIOR' : '$50', # Special Function IO Register
+
+# Module BOOT_LOAD
+ 'SPMCR' : '$57', # Store Program Memory Control R
+ 'SPMCR_SPMIE': '$80', # SPM Interrupt Enable
+ 'SPMCR_RWWSB': '$40', # Read While Write Section Busy
+ 'SPMCR_RWWSRE': '$10', # Read While Write secion read e
+ 'SPMCR_BLBSET': '$8', # Boot Lock Bit Set
+ 'SPMCR_PGWRT': '$4', # Page Write
+ 'SPMCR_PGERS': '$2', # Page Erase
+ 'SPMCR_SPMEN': '$1', # Store Program Memory Enable
+
+# Module TWI
+ 'TWBR' : '$20', # TWI Bit Rate register
+ 'TWCR' : '$56', # TWI Control Register
+ 'TWCR_TWINT': '$80', # TWI Interrupt Flag
+ 'TWCR_TWEA': '$40', # TWI Enable Acknowledge Bit
+ 'TWCR_TWSTA': '$20', # TWI Start Condition Bit
+ 'TWCR_TWSTO': '$10', # TWI Stop Condition Bit
+ 'TWCR_TWWC': '$8', # TWI Write Collition Flag
+ 'TWCR_TWEN': '$4', # TWI Enable Bit
+ 'TWCR_TWIE': '$1', # TWI Interrupt Enable
+ 'TWSR' : '$21', # TWI Status Register
+ 'TWSR_TWS': '$f8', # TWI Status
+ 'TWSR_TWPS': '$3', # TWI Prescaler bits
+ 'TWDR' : '$23', # TWI Data register
+ 'TWAR' : '$22', # TWI (Slave) Address register
+
+ '__amforth_dummy':'0'
+}
diff --git a/amforth-6.5/avr8/devices/atmega32/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega32/words/no-jtag.asm
new file mode 100644
index 0000000..352a4bb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega32/words/no-jtag.asm
@@ -0,0 +1,14 @@
+; ( -- )
+; ( -- )
+; MCU
+; disable jtag at runtime
+VE_NOJTAG:
+ .dw $FF05
+ .db "-jtag",0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOJTAG
+XT_NOJTAG:
+ .dw PFA_NOJTAG
+PFA_NOJTAG:
+
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega32/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega32/words/no-wdt.asm
new file mode 100644
index 0000000..4a12261
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega32/words/no-wdt.asm
@@ -0,0 +1,22 @@
+; ( -- )
+; MCU
+; disable watch dog timer at runtime
+VE_NOWDT:
+ .dw $ff04
+ .db "-wdt"
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOWDT
+XT_NOWDT:
+ .dw PFA_NOWDT
+PFA_NOWDT:
+
+; Reset WDT
+ wdr
+; Write logical one to WDTOE and WDE
+ in_ temp1, WDTCR
+ ori temp1, (1<<WDTOE)|(1<<WDE)
+ out WDTCR, temp1
+; Turn off WDT
+ ldi temp1, (0<<WDE)
+ out_ WDTCR, temp1
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega32/words/sleep.asm b/amforth-6.5/avr8/devices/atmega32/words/sleep.asm
new file mode 100644
index 0000000..778fa32
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega32/words/sleep.asm
@@ -0,0 +1,24 @@
+; ( mode -- )
+; MCU
+; put the controller into the specified sleep mode
+VE_SLEEP:
+ .dw $ff05
+ .db "sleep", 0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_SLEEP
+XT_SLEEP:
+ .dw PFA_SLEEP
+PFA_SLEEP:
+ andi tosl, 7 ; leave only legal mode bits
+ swap tosl ; move to correct location (bits 6-4, atmega32)
+ ori tosl, $80 ; set the SE bit (atmega32: bit 7, not bit 0)
+ out_ MCUCR, tosl ; set the sleep config (atmega32: MCUCR not SMCR)
+ sleep ; nighty-night
+;; the 4 lower bits of MCUCR should not be touched
+ in_ tosl, MCUCR
+ andi tosl, $0F
+ out_ MCUCR, tosl
+ ;clr tosl ; need to clean up the SMCR reg before we leave
+ ;out SMCR, tosl ; 0 protects against accidental sleeps
+ loadtos ; pop argument from stack
+ jmp DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega323/atmega323.frt b/amforth-6.5/avr8/devices/atmega323/atmega323.frt
new file mode 100644
index 0000000..bb14f0a
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega323/atmega323.frt
@@ -0,0 +1,123 @@
+\ Partname: ATmega323
+\ Built using part description XML file version 203
+\ generated automatically
+
+hex
+
+\ AD_CONVERTER
+25 constant ADCH \ ADC Data Register High Byte
+24 constant ADCL \ ADC Data Register Low Byte
+26 constant ADCSR \ The ADC Control and Status register
+27 constant ADMUX \ The ADC multiplexer Selection Register
+
+\ ANALOG_COMPARATOR
+28 constant ACSR \ Analog Comparator Control And Status Register
+50 constant SFIOR \ Special Function IO Register
+
+\ CPU
+55 constant MCUCR \ MCU Control Register
+54 constant MCUCSR \ MCU Control And Status Register
+51 constant OSCCAL \ Oscillator Calibration Value
+5E constant SPH \ Stack Pointer High
+5D constant SPL \ Stack Pointer Low
+57 constant SPMCR \ Store Program Memory Control Register
+5F constant SREG \ Status Register
+
+\ EEPROM
+3F constant EEARH \ EEPROM Read/Write Access High Byte
+3E constant EEARL \ EEPROM Read/Write Access Low Byte
+3C constant EECR \ EEPROM Control Register
+3D constant EEDR \ EEPROM Data Register
+
+\ EXTERNAL_INTERRUPT
+5B constant GICR \ General Interrupt Control Register
+5A constant GIFR \ General Interrupt Flag Register
+
+\ PORTA
+3A constant DDRA \ Port A Data Direction Register
+39 constant PINA \ Port A Input Pins
+3B constant PORTA \ Port A Data Register
+
+\ PORTB
+37 constant DDRB \ Port B Data Direction Register
+36 constant PINB \ Port B Input Pins
+38 constant PORTB \ Port B Data Register
+
+\ PORTC
+34 constant DDRC \ Port C Data Direction Register
+33 constant PINC \ Port C Input Pins
+35 constant PORTC \ Port C Data Register
+
+\ PORTD
+31 constant DDRD \ Port D Data Direction Register
+30 constant PIND \ Port D Input Pins
+32 constant PORTD \ Port D Data Register
+
+\ SPI
+2D constant SPCR \ SPI Control Register
+2F constant SPDR \ SPI Data Register
+2E constant SPSR \ SPI Status Register
+
+\ TIMER_COUNTER_0
+5C constant OCR0 \ Output Compare Register
+53 constant TCCR0 \ Timer/Counter Control Register
+52 constant TCNT0 \ Timer/Counter Register
+58 constant TIFR \ Timer/Counter Interrupt Flag register
+59 constant TIMSK \ Timer/Counter Interrupt Mask Register
+
+\ TIMER_COUNTER_1
+47 constant ICR1H \ Timer/Counter1 Input Capture Register High Byte
+46 constant ICR1L \ Timer/Counter1 Input Capture Register Low Byte
+4B constant OCR1AH \ Timer/Counter1 Output Compare Register High Byte
+4A constant OCR1AL \ Timer/Counter1 Output Compare Register Low Byte
+49 constant OCR1BH \ Timer/Counter1 Output Compare Register High Byte
+48 constant OCR1BL \ Timer/Counter1 Output Compare Register Low Byte
+4F constant TCCR1A \ Timer/Counter1 Control Register A
+4E constant TCCR1B \ Timer/Counter1 Control Register B
+4D constant TCNT1H \ Timer/Counter1 High Byte
+4C constant TCNT1L \ Timer/Counter1 Low Byte
+
+\ TIMER_COUNTER_2
+42 constant ASSR \ Asynchronous Status Register
+43 constant OCR2 \ Timer/Counter2 Output Compare Register
+45 constant TCCR2 \ Timer/Counter2 Control Register
+44 constant TCNT2 \ Timer/Counter2
+
+\ TWI
+22 constant TWAR \ TWI (Slave) Address register
+20 constant TWBR \ TWI Bit Rate register
+56 constant TWCR \ TWI Control Register
+23 constant TWDR \ TWI Data register
+21 constant TWSR \ TWI Status Register
+
+\ USART
+40 constant UBRRH \ USART Baud Rate Register Hight Byte
+29 constant UBRRL \ USART Baud Rate Register Low Byte
+2B constant UCSRA \ USART Control and Status Register A
+2A constant UCSRB \ USART Control and Status Register B
+2C constant UDR \ USART I/O Data Register
+
+\ WATCHDOG
+41 constant WDTCR \ Watchdog Timer Control Register
+
+\ Interrupts
+002 constant INT0Addr \ External Interrupt Request 0
+004 constant INT1Addr \ External Interrupt Request 1
+006 constant INT2Addr \ External Interrupt Request 2
+008 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
+00A constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
+00C constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+00E constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
+010 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
+012 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+014 constant TIMER0_COMPAddr \ Timer/Counter0 Compare Match
+016 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
+018 constant SPI_STCAddr \ Serial Transfer Complete
+01A constant USART_RXCAddr \ USART, Rx Complete
+01C constant USART_UDREAddr \ USART Data Register Empty
+01E constant USART_TXCAddr \ USART, Tx Complete
+020 constant ADCAddr \ ADC Conversion Complete
+022 constant EE_RDYAddr \ EEPROM Ready
+024 constant ANA_COMPAddr \ Analog Comparator
+026 constant TWIAddr \ 2-wire Serial Interface
+28 constant SPM_RDYAddr \ Store Program Memory Ready
diff --git a/amforth-6.5/avr8/devices/atmega323/device.asm b/amforth-6.5/avr8/devices/atmega323/device.asm
new file mode 100644
index 0000000..bc753f4
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega323/device.asm
@@ -0,0 +1,113 @@
+; Partname: ATmega323
+; Built using part description XML file version 203
+; generated automatically, do not edit
+
+.nolist
+ .include "m323def.inc"
+.list
+
+.equ ramstart = $60
+.equ CELLSIZE = 2
+.macro readflashcell
+ lsl zl
+ rol zh
+ lpm @0, Z+
+ lpm @1, Z+
+.endmacro
+.macro writeflashcell
+ lsl zl
+ rol zh
+.endmacro
+
+; the following definitions are shortcuts for the respective forth source segments if set to 1
+.set WANT_AD_CONVERTER = 0
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_CPU = 0
+.set WANT_EEPROM = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_PORTA = 0
+.set WANT_PORTB = 0
+.set WANT_PORTC = 0
+.set WANT_PORTD = 0
+.set WANT_SPI = 0
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_TIMER_COUNTER_2 = 0
+.set WANT_TWI = 0
+.set WANT_USART = 0
+.set WANT_WATCHDOG = 0
+
+
+.ifndef SPMEN
+ .equ SPMEN = SELFPRGEN
+.endif
+
+.ifndef SPMCSR
+ .equ SPMCSR = SPMCR
+.endif
+
+.ifndef EEPE
+ .equ EEPE = EEWE
+.endif
+
+.ifndef EEMPE
+ .equ EEMPE = EEMWE
+.endif
+.equ intvecsize = 2 ; please verify; flash size: 32768 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.equ INTVECTORS = 21
+.org $002
+ rcall isr ; External Interrupt Request 0
+.org $004
+ rcall isr ; External Interrupt Request 1
+.org $006
+ rcall isr ; External Interrupt Request 2
+.org $008
+ rcall isr ; Timer/Counter2 Compare Match
+.org $00A
+ rcall isr ; Timer/Counter2 Overflow
+.org $00C
+ rcall isr ; Timer/Counter1 Capture Event
+.org $00E
+ rcall isr ; Timer/Counter1 Compare Match A
+.org $010
+ rcall isr ; Timer/Counter1 Compare Match B
+.org $012
+ rcall isr ; Timer/Counter1 Overflow
+.org $014
+ rcall isr ; Timer/Counter0 Compare Match
+.org $016
+ rcall isr ; Timer/Counter0 Overflow
+.org $018
+ rcall isr ; Serial Transfer Complete
+.org $01A
+ rcall isr ; USART, Rx Complete
+.org $01C
+ rcall isr ; USART Data Register Empty
+.org $01E
+ rcall isr ; USART, Tx Complete
+.org $020
+ rcall isr ; ADC Conversion Complete
+.org $022
+ rcall isr ; EEPROM Ready
+.org $024
+ rcall isr ; Analog Comparator
+.org $026
+ rcall isr ; 2-wire Serial Interface
+.org $28
+ rcall isr ; Store Program Memory Ready
+.nooverlap
+mcu_info:
+mcu_ramsize:
+ .dw 2048
+mcu_eepromsize:
+ .dw 1024
+mcu_maxdp:
+ .dw 0 ; minimum of 0 (from XML) and 0xffff
+mcu_numints:
+ .dw 21
+mcu_name:
+ .dw 9
+ .db "ATmega323",0
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega323/device.inc b/amforth-6.5/avr8/devices/atmega323/device.inc
new file mode 100644
index 0000000..3027d03
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega323/device.inc
@@ -0,0 +1,867 @@
+; Partname: ATmega323
+; Built using part description XML file version 203
+; generated automatically, no not edit
+
+; ********
+.if WANT_AD_CONVERTER == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register High Byte
+VE_ADCH:
+ .dw $ff04
+ .db "ADCH"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCH
+XT_ADCH:
+ .dw PFA_DOVARIABLE
+PFA_ADCH:
+ .dw $25
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register Low Byte
+VE_ADCL:
+ .dw $ff04
+ .db "ADCL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCL
+XT_ADCL:
+ .dw PFA_DOVARIABLE
+PFA_ADCL:
+ .dw $24
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register
+VE_ADCSR:
+ .dw $ff05
+ .db "ADCSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSR
+XT_ADCSR:
+ .dw PFA_DOVARIABLE
+PFA_ADCSR:
+ .dw $26
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC multiplexer Selection Register
+VE_ADMUX:
+ .dw $ff05
+ .db "ADMUX",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADMUX
+XT_ADMUX:
+ .dw PFA_DOVARIABLE
+PFA_ADMUX:
+ .dw $27
+
+.endif
+
+; ********
+.if WANT_ANALOG_COMPARATOR == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Control And Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw $28
+; ( -- addr ) System Constant
+; R( -- )
+; Special Function IO Register
+VE_SFIOR:
+ .dw $ff05
+ .db "SFIOR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SFIOR
+XT_SFIOR:
+ .dw PFA_DOVARIABLE
+PFA_SFIOR:
+ .dw $50
+
+.endif
+
+; ********
+.if WANT_CPU == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw $55
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control And Status Register
+VE_MCUCSR:
+ .dw $ff06
+ .db "MCUCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCSR
+XT_MCUCSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCSR:
+ .dw $54
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Calibration Value
+VE_OSCCAL:
+ .dw $ff06
+ .db "OSCCAL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSCCAL
+XT_OSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_OSCCAL:
+ .dw $51
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer High
+VE_SPH:
+ .dw $ff03
+ .db "SPH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPH
+XT_SPH:
+ .dw PFA_DOVARIABLE
+PFA_SPH:
+ .dw $5E
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer Low
+VE_SPL:
+ .dw $ff03
+ .db "SPL",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPL
+XT_SPL:
+ .dw PFA_DOVARIABLE
+PFA_SPL:
+ .dw $5D
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control Register
+VE_SPMCR:
+ .dw $ff05
+ .db "SPMCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCR
+XT_SPMCR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCR:
+ .dw $57
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw $5F
+
+.endif
+
+; ********
+.if WANT_EEPROM == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Read/Write Access High Byte
+VE_EEARH:
+ .dw $ff05
+ .db "EEARH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEARH
+XT_EEARH:
+ .dw PFA_DOVARIABLE
+PFA_EEARH:
+ .dw $3F
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Read/Write Access Low Byte
+VE_EEARL:
+ .dw $ff05
+ .db "EEARL",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEARL
+XT_EEARL:
+ .dw PFA_DOVARIABLE
+PFA_EEARL:
+ .dw $3E
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw $3C
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw $3D
+
+.endif
+
+; ********
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; General Interrupt Control Register
+VE_GICR:
+ .dw $ff04
+ .db "GICR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GICR
+XT_GICR:
+ .dw PFA_DOVARIABLE
+PFA_GICR:
+ .dw $5B
+; ( -- addr ) System Constant
+; R( -- )
+; General Interrupt Flag Register
+VE_GIFR:
+ .dw $ff04
+ .db "GIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GIFR
+XT_GIFR:
+ .dw PFA_DOVARIABLE
+PFA_GIFR:
+ .dw $5A
+
+.endif
+
+; ********
+.if WANT_PORTA == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Direction Register
+VE_DDRA:
+ .dw $ff04
+ .db "DDRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRA
+XT_DDRA:
+ .dw PFA_DOVARIABLE
+PFA_DDRA:
+ .dw $3A
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Input Pins
+VE_PINA:
+ .dw $ff04
+ .db "PINA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINA
+XT_PINA:
+ .dw PFA_DOVARIABLE
+PFA_PINA:
+ .dw $39
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Register
+VE_PORTA:
+ .dw $ff05
+ .db "PORTA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTA
+XT_PORTA:
+ .dw PFA_DOVARIABLE
+PFA_PORTA:
+ .dw $3B
+
+.endif
+
+; ********
+.if WANT_PORTB == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw $37
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw $36
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw $38
+
+.endif
+
+; ********
+.if WANT_PORTC == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Direction Register
+VE_DDRC:
+ .dw $ff04
+ .db "DDRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRC
+XT_DDRC:
+ .dw PFA_DOVARIABLE
+PFA_DDRC:
+ .dw $34
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Input Pins
+VE_PINC:
+ .dw $ff04
+ .db "PINC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINC
+XT_PINC:
+ .dw PFA_DOVARIABLE
+PFA_PINC:
+ .dw $33
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Register
+VE_PORTC:
+ .dw $ff05
+ .db "PORTC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTC
+XT_PORTC:
+ .dw PFA_DOVARIABLE
+PFA_PORTC:
+ .dw $35
+
+.endif
+
+; ********
+.if WANT_PORTD == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw $31
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw $30
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw $32
+
+.endif
+
+; ********
+.if WANT_SPI == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR:
+ .dw $ff04
+ .db "SPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR
+XT_SPCR:
+ .dw PFA_DOVARIABLE
+PFA_SPCR:
+ .dw $2D
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR:
+ .dw $ff04
+ .db "SPDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR
+XT_SPDR:
+ .dw PFA_DOVARIABLE
+PFA_SPDR:
+ .dw $2F
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR:
+ .dw $ff04
+ .db "SPSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR
+XT_SPSR:
+ .dw PFA_DOVARIABLE
+PFA_SPSR:
+ .dw $2E
+
+.endif
+
+; ********
+.if WANT_TIMER_COUNTER_0 == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare Register
+VE_OCR0:
+ .dw $ff04
+ .db "OCR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0
+XT_OCR0:
+ .dw PFA_DOVARIABLE
+PFA_OCR0:
+ .dw $5C
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register
+VE_TCCR0:
+ .dw $ff05
+ .db "TCCR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0
+XT_TCCR0:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0:
+ .dw $53
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Register
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw $52
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Flag register
+VE_TIFR:
+ .dw $ff04
+ .db "TIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR
+XT_TIFR:
+ .dw PFA_DOVARIABLE
+PFA_TIFR:
+ .dw $58
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Mask Register
+VE_TIMSK:
+ .dw $ff05
+ .db "TIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK
+XT_TIMSK:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK:
+ .dw $59
+
+.endif
+
+; ********
+.if WANT_TIMER_COUNTER_1 == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register High Byte
+VE_ICR1H:
+ .dw $ff05
+ .db "ICR1H",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1H
+XT_ICR1H:
+ .dw PFA_DOVARIABLE
+PFA_ICR1H:
+ .dw $47
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Low Byte
+VE_ICR1L:
+ .dw $ff05
+ .db "ICR1L",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1L
+XT_ICR1L:
+ .dw PFA_DOVARIABLE
+PFA_ICR1L:
+ .dw $46
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register High Byte
+VE_OCR1AH:
+ .dw $ff06
+ .db "OCR1AH"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1AH
+XT_OCR1AH:
+ .dw PFA_DOVARIABLE
+PFA_OCR1AH:
+ .dw $4B
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register Low Byte
+VE_OCR1AL:
+ .dw $ff06
+ .db "OCR1AL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1AL
+XT_OCR1AL:
+ .dw PFA_DOVARIABLE
+PFA_OCR1AL:
+ .dw $4A
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register High Byte
+VE_OCR1BH:
+ .dw $ff06
+ .db "OCR1BH"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1BH
+XT_OCR1BH:
+ .dw PFA_DOVARIABLE
+PFA_OCR1BH:
+ .dw $49
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register Low Byte
+VE_OCR1BL:
+ .dw $ff06
+ .db "OCR1BL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1BL
+XT_OCR1BL:
+ .dw PFA_DOVARIABLE
+PFA_OCR1BL:
+ .dw $48
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw $4F
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw $4E
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 High Byte
+VE_TCNT1H:
+ .dw $ff06
+ .db "TCNT1H"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1H
+XT_TCNT1H:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1H:
+ .dw $4D
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Low Byte
+VE_TCNT1L:
+ .dw $ff06
+ .db "TCNT1L"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1L
+XT_TCNT1L:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1L:
+ .dw $4C
+
+.endif
+
+; ********
+.if WANT_TIMER_COUNTER_2 == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Asynchronous Status Register
+VE_ASSR:
+ .dw $ff04
+ .db "ASSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ASSR
+XT_ASSR:
+ .dw PFA_DOVARIABLE
+PFA_ASSR:
+ .dw $42
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register
+VE_OCR2:
+ .dw $ff04
+ .db "OCR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2
+XT_OCR2:
+ .dw PFA_DOVARIABLE
+PFA_OCR2:
+ .dw $43
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register
+VE_TCCR2:
+ .dw $ff05
+ .db "TCCR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2
+XT_TCCR2:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2:
+ .dw $45
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2
+VE_TCNT2:
+ .dw $ff05
+ .db "TCNT2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT2
+XT_TCNT2:
+ .dw PFA_DOVARIABLE
+PFA_TCNT2:
+ .dw $44
+
+.endif
+
+; ********
+.if WANT_TWI == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; TWI (Slave) Address register
+VE_TWAR:
+ .dw $ff04
+ .db "TWAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWAR
+XT_TWAR:
+ .dw PFA_DOVARIABLE
+PFA_TWAR:
+ .dw $22
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Bit Rate register
+VE_TWBR:
+ .dw $ff04
+ .db "TWBR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWBR
+XT_TWBR:
+ .dw PFA_DOVARIABLE
+PFA_TWBR:
+ .dw $20
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Control Register
+VE_TWCR:
+ .dw $ff04
+ .db "TWCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWCR
+XT_TWCR:
+ .dw PFA_DOVARIABLE
+PFA_TWCR:
+ .dw $56
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Data register
+VE_TWDR:
+ .dw $ff04
+ .db "TWDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWDR
+XT_TWDR:
+ .dw PFA_DOVARIABLE
+PFA_TWDR:
+ .dw $23
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Status Register
+VE_TWSR:
+ .dw $ff04
+ .db "TWSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWSR
+XT_TWSR:
+ .dw PFA_DOVARIABLE
+PFA_TWSR:
+ .dw $21
+
+.endif
+
+; ********
+.if WANT_USART == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Hight Byte
+VE_UBRRH:
+ .dw $ff05
+ .db "UBRRH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRRH
+XT_UBRRH:
+ .dw PFA_DOVARIABLE
+PFA_UBRRH:
+ .dw $40
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Low Byte
+VE_UBRRL:
+ .dw $ff05
+ .db "UBRRL",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRRL
+XT_UBRRL:
+ .dw PFA_DOVARIABLE
+PFA_UBRRL:
+ .dw $29
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSRA:
+ .dw $ff05
+ .db "UCSRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSRA
+XT_UCSRA:
+ .dw PFA_DOVARIABLE
+PFA_UCSRA:
+ .dw $2B
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSRB:
+ .dw $ff05
+ .db "UCSRB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSRB
+XT_UCSRB:
+ .dw PFA_DOVARIABLE
+PFA_UCSRB:
+ .dw $2A
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR:
+ .dw $ff03
+ .db "UDR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR
+XT_UDR:
+ .dw PFA_DOVARIABLE
+PFA_UDR:
+ .dw $2C
+
+.endif
+
+; ********
+.if WANT_WATCHDOG == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCR:
+ .dw $ff05
+ .db "WDTCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCR
+XT_WDTCR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCR:
+ .dw $41
+
+.endif
diff --git a/amforth-6.5/avr8/devices/atmega323/device.py b/amforth-6.5/avr8/devices/atmega323/device.py
new file mode 100644
index 0000000..b954e83
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega323/device.py
@@ -0,0 +1,89 @@
+# Partname: ATmega323
+# Built using part description XML file version 203
+# generated automatically, do not edit
+MCUREGS = {
+ 'ADCH': '$25',
+ 'ADCL': '$24',
+ 'ADCSR': '$26',
+ 'ADMUX': '$27',
+ 'ACSR': '$28',
+ 'SFIOR': '$50',
+ 'MCUCR': '$55',
+ 'MCUCSR': '$54',
+ 'OSCCAL': '$51',
+ 'SPH': '$5E',
+ 'SPL': '$5D',
+ 'SPMCR': '$57',
+ 'SREG': '$5F',
+ 'EEARH': '$3F',
+ 'EEARL': '$3E',
+ 'EECR': '$3C',
+ 'EEDR': '$3D',
+ 'GICR': '$5B',
+ 'GIFR': '$5A',
+ 'DDRA': '$3A',
+ 'PINA': '$39',
+ 'PORTA': '$3B',
+ 'DDRB': '$37',
+ 'PINB': '$36',
+ 'PORTB': '$38',
+ 'DDRC': '$34',
+ 'PINC': '$33',
+ 'PORTC': '$35',
+ 'DDRD': '$31',
+ 'PIND': '$30',
+ 'PORTD': '$32',
+ 'SPCR': '$2D',
+ 'SPDR': '$2F',
+ 'SPSR': '$2E',
+ 'OCR0': '$5C',
+ 'TCCR0': '$53',
+ 'TCNT0': '$52',
+ 'TIFR': '$58',
+ 'TIMSK': '$59',
+ 'ICR1H': '$47',
+ 'ICR1L': '$46',
+ 'OCR1AH': '$4B',
+ 'OCR1AL': '$4A',
+ 'OCR1BH': '$49',
+ 'OCR1BL': '$48',
+ 'TCCR1A': '$4F',
+ 'TCCR1B': '$4E',
+ 'TCNT1H': '$4D',
+ 'TCNT1L': '$4C',
+ 'ASSR': '$42',
+ 'OCR2': '$43',
+ 'TCCR2': '$45',
+ 'TCNT2': '$44',
+ 'TWAR': '$22',
+ 'TWBR': '$20',
+ 'TWCR': '$56',
+ 'TWDR': '$23',
+ 'TWSR': '$21',
+ 'UBRRH': '$40',
+ 'UBRRL': '$29',
+ 'UCSRA': '$2B',
+ 'UCSRB': '$2A',
+ 'UDR': '$2C',
+ 'WDTCR': '$41',
+ 'INT0Addr': '$002',
+ 'INT1Addr': '$004',
+ 'INT2Addr': '$006',
+ 'TIMER2_COMPAddr': '$008',
+ 'TIMER2_OVFAddr': '$00A',
+ 'TIMER1_CAPTAddr': '$00C',
+ 'TIMER1_COMPAAddr': '$00E',
+ 'TIMER1_COMPBAddr': '$010',
+ 'TIMER1_OVFAddr': '$012',
+ 'TIMER0_COMPAddr': '$014',
+ 'TIMER0_OVFAddr': '$016',
+ 'SPI_STCAddr': '$018',
+ 'USART_RXCAddr': '$01A',
+ 'USART_UDREAddr': '$01C',
+ 'USART_TXCAddr': '$01E',
+ 'ADCAddr': '$020',
+ 'EE_RDYAddr': '$022',
+ 'ANA_COMPAddr': '$024',
+ 'TWIAddr': '$026',
+ 'SPM_RDYAddr': '$28'
+} \ No newline at end of file
diff --git a/amforth-6.5/avr8/devices/atmega324a/atmega324a.frt b/amforth-6.5/avr8/devices/atmega324a/atmega324a.frt
new file mode 100644
index 0000000..0299dc2
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega324a/atmega324a.frt
@@ -0,0 +1,347 @@
+\ Partname: ATmega324A
+\ generated automatically
+
+\ ANALOG_COMPARATOR
+&123 constant ADCSRB \ ADC Control and Status Register B
+ $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer Enable
+&80 constant ACSR \ Analog Comparator Control And Status Register
+ $80 constant ACSR_ACD \ Analog Comparator Disable
+ $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
+ $20 constant ACSR_ACO \ Analog Compare Output
+ $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
+ $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
+ $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
+ $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
+&127 constant DIDR1 \ Digital Input Disable Register 1
+ $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
+ $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
+\ USART0
+&198 constant UDR0 \ USART I/O Data Register
+&192 constant UCSR0A \ USART Control and Status Register A
+ $80 constant UCSR0A_RXC0 \ USART Receive Complete
+ $40 constant UCSR0A_TXC0 \ USART Transmitt Complete
+ $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
+ $10 constant UCSR0A_FE0 \ Framing Error
+ $08 constant UCSR0A_DOR0 \ Data overRun
+ $04 constant UCSR0A_UPE0 \ Parity Error
+ $02 constant UCSR0A_U2X0 \ Double the USART transmission speed
+ $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
+&193 constant UCSR0B \ USART Control and Status Register B
+ $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
+ $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
+ $20 constant UCSR0B_UDRIE0 \ USART Data register Empty Interrupt Enable
+ $10 constant UCSR0B_RXEN0 \ Receiver Enable
+ $08 constant UCSR0B_TXEN0 \ Transmitter Enable
+ $04 constant UCSR0B_UCSZ02 \ Character Size
+ $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
+ $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
+&194 constant UCSR0C \ USART Control and Status Register C
+ $C0 constant UCSR0C_UMSEL0 \ USART Mode Select
+ $30 constant UCSR0C_UPM0 \ Parity Mode Bits
+ $08 constant UCSR0C_USBS0 \ Stop Bit Select
+ $06 constant UCSR0C_UCSZ0 \ Character Size
+ $01 constant UCSR0C_UCPOL0 \ Clock Polarity
+&196 constant UBRR0 \ USART Baud Rate Register Bytes
+\ PORTA
+&34 constant PORTA \ Port A Data Register
+&33 constant DDRA \ Port A Data Direction Register
+&32 constant PINA \ Port A Input Pins
+\ PORTB
+&37 constant PORTB \ Port B Data Register
+&36 constant DDRB \ Port B Data Direction Register
+&35 constant PINB \ Port B Input Pins
+\ PORTC
+&40 constant PORTC \ Port C Data Register
+&39 constant DDRC \ Port C Data Direction Register
+&38 constant PINC \ Port C Input Pins
+\ PORTD
+&43 constant PORTD \ Port D Data Register
+&42 constant DDRD \ Port D Data Direction Register
+&41 constant PIND \ Port D Input Pins
+\ TIMER_COUNTER_0
+&72 constant OCR0B \ Timer/Counter0 Output Compare Register
+&71 constant OCR0A \ Timer/Counter0 Output Compare Register
+&70 constant TCNT0 \ Timer/Counter0
+&69 constant TCCR0B \ Timer/Counter Control Register B
+ $80 constant TCCR0B_FOC0A \ Force Output Compare A
+ $40 constant TCCR0B_FOC0B \ Force Output Compare B
+ $08 constant TCCR0B_WGM02 \
+ $07 constant TCCR0B_CS0 \ Clock Select
+&68 constant TCCR0A \ Timer/Counter Control Register A
+ $C0 constant TCCR0A_COM0A \ Compare Output Mode, Phase Correct PWM Mode
+ $30 constant TCCR0A_COM0B \ Compare Output Mode, Fast PWm
+ $03 constant TCCR0A_WGM0 \ Waveform Generation Mode
+&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
+ $04 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare Match B Interrupt Enable
+ $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match A Interrupt Enable
+ $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
+&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
+ $04 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare Flag 0B
+ $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0A
+ $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
+&67 constant GTCCR \ General Timer/Counter Control Register
+ $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
+ $01 constant GTCCR_PSRSYNC \ Prescaler Reset Timer/Counter1 and Timer/Counter0
+\ TIMER_COUNTER_2
+&112 constant TIMSK2 \ Timer/Counter Interrupt Mask register
+ $04 constant TIMSK2_OCIE2B \ Timer/Counter2 Output Compare Match B Interrupt Enable
+ $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match A Interrupt Enable
+ $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
+&55 constant TIFR2 \ Timer/Counter Interrupt Flag Register
+ $04 constant TIFR2_OCF2B \ Output Compare Flag 2B
+ $02 constant TIFR2_OCF2A \ Output Compare Flag 2A
+ $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
+&176 constant TCCR2A \ Timer/Counter2 Control Register A
+ $C0 constant TCCR2A_COM2A \ Compare Output Mode bits
+ $30 constant TCCR2A_COM2B \ Compare Output Mode bits
+ $03 constant TCCR2A_WGM2 \ Waveform Genration Mode
+&177 constant TCCR2B \ Timer/Counter2 Control Register B
+ $80 constant TCCR2B_FOC2A \ Force Output Compare A
+ $40 constant TCCR2B_FOC2B \ Force Output Compare B
+ $08 constant TCCR2B_WGM22 \ Waveform Generation Mode
+ $07 constant TCCR2B_CS2 \ Clock Select bits
+&178 constant TCNT2 \ Timer/Counter2
+&180 constant OCR2B \ Timer/Counter2 Output Compare Register B
+&179 constant OCR2A \ Timer/Counter2 Output Compare Register A
+&182 constant ASSR \ Asynchronous Status Register
+ $40 constant ASSR_EXCLK \ Enable External Clock Input
+ $20 constant ASSR_AS2 \ Asynchronous Timer/Counter2
+ $10 constant ASSR_TCN2UB \ Timer/Counter2 Update Busy
+ $08 constant ASSR_OCR2AUB \ Output Compare Register2 Update Busy
+ $04 constant ASSR_OCR2BUB \ Output Compare Register 2 Update Busy
+ $02 constant ASSR_TCR2AUB \ Timer/Counter Control Register2 Update Busy
+ $01 constant ASSR_TCR2BUB \ Timer/Counter Control Register2 Update Busy
+\ WATCHDOG
+&96 constant WDTCSR \ Watchdog Timer Control Register
+ $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Flag
+ $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Enable
+ $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
+ $10 constant WDTCSR_WDCE \ Watchdog Change Enable
+ $08 constant WDTCSR_WDE \ Watch Dog Enable
+\ JTAG
+&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
+&85 constant MCUCR \ MCU Control Register
+ $80 constant MCUCR_JTD \ JTAG Interface Disable
+&84 constant MCUSR \ MCU Status Register
+ $10 constant MCUSR_JTRF \ JTAG Reset Flag
+\ BOOT_LOAD
+&87 constant SPMCSR \ Store Program Memory Control Register
+ $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
+ $20 constant SPMCSR_SIGRD \ Signature Row Read
+ $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
+ $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
+ $04 constant SPMCSR_PGWRT \ Page Write
+ $02 constant SPMCSR_PGERS \ Page Erase
+ $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
+\ EXTERNAL_INTERRUPT
+&105 constant EICRA \ External Interrupt Control Register A
+ $30 constant EICRA_ISC2 \ External Interrupt Sense Control Bit
+ $0C constant EICRA_ISC1 \ External Interrupt Sense Control Bit
+ $03 constant EICRA_ISC0 \ External Interrupt Sense Control Bit
+&61 constant EIMSK \ External Interrupt Mask Register
+ $07 constant EIMSK_INT \ External Interrupt Request 2 Enable
+&60 constant EIFR \ External Interrupt Flag Register
+ $07 constant EIFR_INTF \ External Interrupt Flags
+&115 constant PCMSK3 \ Pin Change Mask Register 3
+ $FF constant PCMSK3_PCINT \ Pin Change Enable Masks
+&109 constant PCMSK2 \ Pin Change Mask Register 2
+ $FF constant PCMSK2_PCINT \ Pin Change Enable Masks
+&108 constant PCMSK1 \ Pin Change Mask Register 1
+ $FF constant PCMSK1_PCINT \ Pin Change Enable Masks
+&107 constant PCMSK0 \ Pin Change Mask Register 0
+ $FF constant PCMSK0_PCINT \ Pin Change Enable Masks
+&59 constant PCIFR \ Pin Change Interrupt Flag Register
+ $0F constant PCIFR_PCIF \ Pin Change Interrupt Flags
+&104 constant PCICR \ Pin Change Interrupt Control Register
+ $0F constant PCICR_PCIE \ Pin Change Interrupt Enables
+\ AD_CONVERTER
+&124 constant ADMUX \ The ADC multiplexer Selection Register
+ $C0 constant ADMUX_REFS \ Reference Selection Bits
+ $20 constant ADMUX_ADLAR \ Left Adjust Result
+ $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
+&120 constant ADC \ ADC Data Register Bytes
+&122 constant ADCSRA \ The ADC Control and Status register A
+ $80 constant ADCSRA_ADEN \ ADC Enable
+ $40 constant ADCSRA_ADSC \ ADC Start Conversion
+ $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
+ $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
+ $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
+ $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
+&126 constant DIDR0 \ Digital Input Disable Register
+ $80 constant DIDR0_ADC7D \
+ $40 constant DIDR0_ADC6D \
+ $20 constant DIDR0_ADC5D \
+ $10 constant DIDR0_ADC4D \
+ $08 constant DIDR0_ADC3D \
+ $04 constant DIDR0_ADC2D \
+ $02 constant DIDR0_ADC1D \
+ $01 constant DIDR0_ADC0D \
+\ TIMER_COUNTER_1
+&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
+ $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
+ $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
+ $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
+ $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
+&54 constant TIFR1 \ Timer/Counter Interrupt Flag register
+ $20 constant TIFR1_ICF1 \ Timer/Counter1 Input Capture Flag
+ $04 constant TIFR1_OCF1B \ Timer/Counter1 Output Compare B Match Flag
+ $02 constant TIFR1_OCF1A \ Timer/Counter1 Output Compare A Match Flag
+ $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
+&128 constant TCCR1A \ Timer/Counter1 Control Register A
+ $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
+ $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
+ $03 constant TCCR1A_WGM1 \ Pulse Width Modulator Select Bits
+&129 constant TCCR1B \ Timer/Counter1 Control Register B
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ $18 constant TCCR1B_WGM1 \ Waveform Generation Mode Bits
+ $07 constant TCCR1B_CS1 \ Clock Select1 bits
+&130 constant TCCR1C \ Timer/Counter1 Control Register C
+ $80 constant TCCR1C_FOC1A \ Force Output Compare for Channel A
+ $40 constant TCCR1C_FOC1B \ Force Output Compare for Channel B
+&132 constant TCNT1 \ Timer/Counter1 Bytes
+&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
+&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
+&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
+\ EEPROM
+&65 constant EEAR \ EEPROM Address Register Low Bytes
+&64 constant EEDR \ EEPROM Data Register
+&63 constant EECR \ EEPROM Control Register
+ $30 constant EECR_EEPM \ EEPROM Programming Mode Bits
+ $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
+ $04 constant EECR_EEMPE \ EEPROM Master Write Enable
+ $02 constant EECR_EEPE \ EEPROM Write Enable
+ $01 constant EECR_EERE \ EEPROM Read Enable
+\ SPI
+&78 constant SPDR0 \ SPI Data Register
+&77 constant SPSR0 \ SPI Status Register
+ $80 constant SPSR0_SPIF0 \ SPI Interrupt Flag
+ $40 constant SPSR0_WCOL0 \ Write Collision Flag
+ $01 constant SPSR0_SPI2X0 \ Double SPI Speed Bit
+&76 constant SPCR0 \ SPI Control Register
+ $80 constant SPCR0_SPIE0 \ SPI Interrupt Enable
+ $40 constant SPCR0_SPE0 \ SPI Enable
+ $20 constant SPCR0_DORD0 \ Data Order
+ $10 constant SPCR0_MSTR0 \ Master/Slave Select
+ $08 constant SPCR0_CPOL0 \ Clock polarity
+ $04 constant SPCR0_CPHA0 \ Clock Phase
+ $02 constant SPCR0_SPR10 \ SPI Clock Rate Select 1
+ $01 constant SPCR0_SPR00 \ SPI Clock Rate Select 0
+\ TWI
+&189 constant TWAMR \ TWI (Slave) Address Mask Register
+ $FE constant TWAMR_TWAM \
+&184 constant TWBR \ TWI Bit Rate register
+&188 constant TWCR \ TWI Control Register
+ $80 constant TWCR_TWINT \ TWI Interrupt Flag
+ $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
+ $20 constant TWCR_TWSTA \ TWI Start Condition Bit
+ $10 constant TWCR_TWSTO \ TWI Stop Condition Bit
+ $08 constant TWCR_TWWC \ TWI Write Collition Flag
+ $04 constant TWCR_TWEN \ TWI Enable Bit
+ $01 constant TWCR_TWIE \ TWI Interrupt Enable
+&185 constant TWSR \ TWI Status Register
+ $F8 constant TWSR_TWS \ TWI Status
+ $03 constant TWSR_TWPS \ TWI Prescaler
+&187 constant TWDR \ TWI Data register
+&186 constant TWAR \ TWI (Slave) Address register
+ $FE constant TWAR_TWA \ TWI (Slave) Address register Bits
+ $01 constant TWAR_TWGCE \ TWI General Call Recognition Enable Bit
+\ USART1
+&206 constant UDR1 \ USART I/O Data Register
+&200 constant UCSR1A \ USART Control and Status Register A
+ $80 constant UCSR1A_RXC1 \ USART Receive Complete
+ $40 constant UCSR1A_TXC1 \ USART Transmitt Complete
+ $20 constant UCSR1A_UDRE1 \ USART Data Register Empty
+ $10 constant UCSR1A_FE1 \ Framing Error
+ $08 constant UCSR1A_DOR1 \ Data overRun
+ $04 constant UCSR1A_UPE1 \ Parity Error
+ $02 constant UCSR1A_U2X1 \ Double the USART transmission speed
+ $01 constant UCSR1A_MPCM1 \ Multi-processor Communication Mode
+&201 constant UCSR1B \ USART Control and Status Register B
+ $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable
+ $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable
+ $20 constant UCSR1B_UDRIE1 \ USART Data register Empty Interrupt Enable
+ $10 constant UCSR1B_RXEN1 \ Receiver Enable
+ $08 constant UCSR1B_TXEN1 \ Transmitter Enable
+ $04 constant UCSR1B_UCSZ12 \ Character Size
+ $02 constant UCSR1B_RXB81 \ Receive Data Bit 8
+ $01 constant UCSR1B_TXB81 \ Transmit Data Bit 8
+&202 constant UCSR1C \ USART Control and Status Register C
+ $C0 constant UCSR1C_UMSEL1 \ USART Mode Select
+ $30 constant UCSR1C_UPM1 \ Parity Mode Bits
+ $08 constant UCSR1C_USBS1 \ Stop Bit Select
+ $06 constant UCSR1C_UCSZ1 \ Character Size
+ $01 constant UCSR1C_UCPOL1 \ Clock Polarity
+&204 constant UBRR1 \ USART Baud Rate Register Bytes
+\ CPU
+&95 constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ $08 constant SREG_V \ Two's Complement Overflow Flag
+ $04 constant SREG_N \ Negative Flag
+ $02 constant SREG_Z \ Zero Flag
+ $01 constant SREG_C \ Carry Flag
+&93 constant SP \ Stack Pointer
+&102 constant OSCCAL \ Oscillator Calibration Value
+&97 constant CLKPR \
+ $80 constant CLKPR_CLKPCE \
+ $0F constant CLKPR_CLKPS \
+&83 constant SMCR \ Sleep Mode Control Register
+ $0E constant SMCR_SM \ Sleep Mode Select bits
+ $01 constant SMCR_SE \ Sleep Enable
+&75 constant GPIOR2 \ General Purpose IO Register 2
+ $FF constant GPIOR2_GPIOR \ General Purpose IO Register 2 bis
+&74 constant GPIOR1 \ General Purpose IO Register 1
+ $FF constant GPIOR1_GPIOR \ General Purpose IO Register 1 bis
+&62 constant GPIOR0 \ General Purpose IO Register 0
+ $80 constant GPIOR0_GPIOR07 \ General Purpose IO Register 0 bit 7
+ $40 constant GPIOR0_GPIOR06 \ General Purpose IO Register 0 bit 6
+ $20 constant GPIOR0_GPIOR05 \ General Purpose IO Register 0 bit 5
+ $10 constant GPIOR0_GPIOR04 \ General Purpose IO Register 0 bit 4
+ $08 constant GPIOR0_GPIOR03 \ General Purpose IO Register 0 bit 3
+ $04 constant GPIOR0_GPIOR02 \ General Purpose IO Register 0 bit 2
+ $02 constant GPIOR0_GPIOR01 \ General Purpose IO Register 0 bit 1
+ $01 constant GPIOR0_GPIOR00 \ General Purpose IO Register 0 bit 0
+&100 constant PRR0 \ Power Reduction Register0
+ $80 constant PRR0_PRTWI \ Power Reduction TWI
+ $40 constant PRR0_PRTIM2 \ Power Reduction Timer/Counter2
+ $20 constant PRR0_PRTIM0 \ Power Reduction Timer/Counter0
+ $12 constant PRR0_PRUSART \ Power Reduction USARTs
+ $08 constant PRR0_PRTIM1 \ Power Reduction Timer/Counter1
+ $04 constant PRR0_PRSPI \ Power Reduction Serial Peripheral Interface
+ $01 constant PRR0_PRADC \ Power Reduction ADC
+
+\ Interrupts
+&2 constant INT0Addr \ External Interrupt Request 0
+&4 constant INT1Addr \ External Interrupt Request 1
+&6 constant INT2Addr \ External Interrupt Request 2
+&8 constant PCINT0Addr \ Pin Change Interrupt Request 0
+&10 constant PCINT1Addr \ Pin Change Interrupt Request 1
+&12 constant PCINT2Addr \ Pin Change Interrupt Request 2
+&14 constant PCINT3Addr \ Pin Change Interrupt Request 3
+&16 constant WDTAddr \ Watchdog Time-out Interrupt
+&18 constant TIMER2_COMPAAddr \ Timer/Counter2 Compare Match A
+&20 constant TIMER2_COMPBAddr \ Timer/Counter2 Compare Match B
+&22 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
+&24 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+&26 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
+&28 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
+&30 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+&32 constant TIMER0_COMPAAddr \ Timer/Counter0 Compare Match A
+&34 constant TIMER0_COMPBAddr \ Timer/Counter0 Compare Match B
+&36 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
+&38 constant SPI__STCAddr \ SPI Serial Transfer Complete
+&40 constant USART0__RXAddr \ USART0, Rx Complete
+&42 constant USART0__UDREAddr \ USART0 Data register Empty
+&44 constant USART0__TXAddr \ USART0, Tx Complete
+&46 constant ANALOG_COMPAddr \ Analog Comparator
+&48 constant ADCAddr \ ADC Conversion Complete
+&50 constant EE_READYAddr \ EEPROM Ready
+&52 constant TWIAddr \ 2-wire Serial Interface
+&54 constant SPM_READYAddr \ Store Program Memory Read
+&56 constant USART1_RXAddr \ USART1 RX complete
+&58 constant USART1_UDREAddr \ USART1 Data Register Empty
+&60 constant USART1_TXAddr \ USART1 TX complete
diff --git a/amforth-6.5/avr8/devices/atmega324a/device.asm b/amforth-6.5/avr8/devices/atmega324a/device.asm
new file mode 100644
index 0000000..2b22c76
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega324a/device.asm
@@ -0,0 +1,120 @@
+; Partname: ATmega324A
+; generated automatically, do not edit
+
+.nolist
+ .include "m324Adef.inc"
+.list
+
+.equ ramstart = 256
+.equ CELLSIZE = 2
+.macro readflashcell
+ lsl zl
+ rol zh
+ lpm @0, Z+
+ lpm @1, Z+
+.endmacro
+.macro writeflashcell
+ lsl zl
+ rol zh
+.endmacro
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_USART0 = 0
+.set WANT_PORTA = 0
+.set WANT_PORTB = 0
+.set WANT_PORTC = 0
+.set WANT_PORTD = 0
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_TIMER_COUNTER_2 = 0
+.set WANT_WATCHDOG = 0
+.set WANT_JTAG = 0
+.set WANT_BOOT_LOAD = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_AD_CONVERTER = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_EEPROM = 0
+.set WANT_SPI = 0
+.set WANT_TWI = 0
+.set WANT_USART1 = 0
+.set WANT_CPU = 0
+.equ intvecsize = 2 ; please verify; flash size: 32768 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.org 2
+ rcall isr ; External Interrupt Request 0
+.org 4
+ rcall isr ; External Interrupt Request 1
+.org 6
+ rcall isr ; External Interrupt Request 2
+.org 8
+ rcall isr ; Pin Change Interrupt Request 0
+.org 10
+ rcall isr ; Pin Change Interrupt Request 1
+.org 12
+ rcall isr ; Pin Change Interrupt Request 2
+.org 14
+ rcall isr ; Pin Change Interrupt Request 3
+.org 16
+ rcall isr ; Watchdog Time-out Interrupt
+.org 18
+ rcall isr ; Timer/Counter2 Compare Match A
+.org 20
+ rcall isr ; Timer/Counter2 Compare Match B
+.org 22
+ rcall isr ; Timer/Counter2 Overflow
+.org 24
+ rcall isr ; Timer/Counter1 Capture Event
+.org 26
+ rcall isr ; Timer/Counter1 Compare Match A
+.org 28
+ rcall isr ; Timer/Counter1 Compare Match B
+.org 30
+ rcall isr ; Timer/Counter1 Overflow
+.org 32
+ rcall isr ; Timer/Counter0 Compare Match A
+.org 34
+ rcall isr ; Timer/Counter0 Compare Match B
+.org 36
+ rcall isr ; Timer/Counter0 Overflow
+.org 38
+ rcall isr ; SPI Serial Transfer Complete
+.org 40
+ rcall isr ; USART0, Rx Complete
+.org 42
+ rcall isr ; USART0 Data register Empty
+.org 44
+ rcall isr ; USART0, Tx Complete
+.org 46
+ rcall isr ; Analog Comparator
+.org 48
+ rcall isr ; ADC Conversion Complete
+.org 50
+ rcall isr ; EEPROM Ready
+.org 52
+ rcall isr ; 2-wire Serial Interface
+.org 54
+ rcall isr ; Store Program Memory Read
+.org 56
+ rcall isr ; USART1 RX complete
+.org 58
+ rcall isr ; USART1 Data Register Empty
+.org 60
+ rcall isr ; USART1 TX complete
+.equ INTVECTORS = 31
+.nooverlap
+
+; compatability layer (maybe empty)
+
+; controller data area, environment query mcu-info
+mcu_info:
+mcu_ramsize:
+ .dw 2048
+mcu_eepromsize:
+ .dw 1024
+mcu_maxdp:
+ .dw 28672
+mcu_numints:
+ .dw 31
+mcu_name:
+ .dw 10
+ .db "ATmega324A"
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega324a/device.inc b/amforth-6.5/avr8/devices/atmega324a/device.inc
new file mode 100644
index 0000000..ab2771b
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega324a/device.inc
@@ -0,0 +1,1128 @@
+; Partname: ATmega324A
+; generated automatically, no not edit
+
+.if WANT_ANALOG_COMPARATOR == 1
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Control and Status Register B
+VE_ADCSRB:
+ .dw $ff06
+ .db "ADCSRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRB
+XT_ADCSRB:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRB:
+ .dw 123
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Control And Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw 80
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 1
+VE_DIDR1:
+ .dw $ff05
+ .db "DIDR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR1
+XT_DIDR1:
+ .dw PFA_DOVARIABLE
+PFA_DIDR1:
+ .dw 127
+
+.endif
+.if WANT_USART0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR0:
+ .dw $ff04
+ .db "UDR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR0
+XT_UDR0:
+ .dw PFA_DOVARIABLE
+PFA_UDR0:
+ .dw 198
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR0A:
+ .dw $ff06
+ .db "UCSR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0A
+XT_UCSR0A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0A:
+ .dw 192
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR0B:
+ .dw $ff06
+ .db "UCSR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0B
+XT_UCSR0B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0B:
+ .dw 193
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR0C:
+ .dw $ff06
+ .db "UCSR0C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0C
+XT_UCSR0C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0C:
+ .dw 194
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Bytes
+VE_UBRR0:
+ .dw $ff05
+ .db "UBRR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR0
+XT_UBRR0:
+ .dw PFA_DOVARIABLE
+PFA_UBRR0:
+ .dw 196
+
+.endif
+.if WANT_PORTA == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Register
+VE_PORTA:
+ .dw $ff05
+ .db "PORTA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTA
+XT_PORTA:
+ .dw PFA_DOVARIABLE
+PFA_PORTA:
+ .dw 34
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Direction Register
+VE_DDRA:
+ .dw $ff04
+ .db "DDRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRA
+XT_DDRA:
+ .dw PFA_DOVARIABLE
+PFA_DDRA:
+ .dw 33
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Input Pins
+VE_PINA:
+ .dw $ff04
+ .db "PINA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINA
+XT_PINA:
+ .dw PFA_DOVARIABLE
+PFA_PINA:
+ .dw 32
+
+.endif
+.if WANT_PORTB == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw 37
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw 36
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw 35
+
+.endif
+.if WANT_PORTC == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Register
+VE_PORTC:
+ .dw $ff05
+ .db "PORTC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTC
+XT_PORTC:
+ .dw PFA_DOVARIABLE
+PFA_PORTC:
+ .dw 40
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Direction Register
+VE_DDRC:
+ .dw $ff04
+ .db "DDRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRC
+XT_DDRC:
+ .dw PFA_DOVARIABLE
+PFA_DDRC:
+ .dw 39
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Input Pins
+VE_PINC:
+ .dw $ff04
+ .db "PINC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINC
+XT_PINC:
+ .dw PFA_DOVARIABLE
+PFA_PINC:
+ .dw 38
+
+.endif
+.if WANT_PORTD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw 43
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw 42
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw 41
+
+.endif
+.if WANT_TIMER_COUNTER_0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0B:
+ .dw $ff05
+ .db "OCR0B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0B
+XT_OCR0B:
+ .dw PFA_DOVARIABLE
+PFA_OCR0B:
+ .dw 72
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0A:
+ .dw $ff05
+ .db "OCR0A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0A
+XT_OCR0A:
+ .dw PFA_DOVARIABLE
+PFA_OCR0A:
+ .dw 71
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw 70
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register B
+VE_TCCR0B:
+ .dw $ff06
+ .db "TCCR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0B
+XT_TCCR0B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0B:
+ .dw 69
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register A
+VE_TCCR0A:
+ .dw $ff06
+ .db "TCCR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0A
+XT_TCCR0A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0A:
+ .dw 68
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Mask Register
+VE_TIMSK0:
+ .dw $ff06
+ .db "TIMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK0
+XT_TIMSK0:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK0:
+ .dw 110
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Flag register
+VE_TIFR0:
+ .dw $ff05
+ .db "TIFR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR0
+XT_TIFR0:
+ .dw PFA_DOVARIABLE
+PFA_TIFR0:
+ .dw 53
+; ( -- addr ) System Constant
+; R( -- )
+; General Timer/Counter Control Register
+VE_GTCCR:
+ .dw $ff05
+ .db "GTCCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GTCCR
+XT_GTCCR:
+ .dw PFA_DOVARIABLE
+PFA_GTCCR:
+ .dw 67
+
+.endif
+.if WANT_TIMER_COUNTER_2 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Mask register
+VE_TIMSK2:
+ .dw $ff06
+ .db "TIMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK2
+XT_TIMSK2:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK2:
+ .dw 112
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Flag Register
+VE_TIFR2:
+ .dw $ff05
+ .db "TIFR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR2
+XT_TIFR2:
+ .dw PFA_DOVARIABLE
+PFA_TIFR2:
+ .dw 55
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register A
+VE_TCCR2A:
+ .dw $ff06
+ .db "TCCR2A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2A
+XT_TCCR2A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2A:
+ .dw 176
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register B
+VE_TCCR2B:
+ .dw $ff06
+ .db "TCCR2B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2B
+XT_TCCR2B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2B:
+ .dw 177
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2
+VE_TCNT2:
+ .dw $ff05
+ .db "TCNT2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT2
+XT_TCNT2:
+ .dw PFA_DOVARIABLE
+PFA_TCNT2:
+ .dw 178
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register B
+VE_OCR2B:
+ .dw $ff05
+ .db "OCR2B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2B
+XT_OCR2B:
+ .dw PFA_DOVARIABLE
+PFA_OCR2B:
+ .dw 180
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register A
+VE_OCR2A:
+ .dw $ff05
+ .db "OCR2A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2A
+XT_OCR2A:
+ .dw PFA_DOVARIABLE
+PFA_OCR2A:
+ .dw 179
+; ( -- addr ) System Constant
+; R( -- )
+; Asynchronous Status Register
+VE_ASSR:
+ .dw $ff04
+ .db "ASSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ASSR
+XT_ASSR:
+ .dw PFA_DOVARIABLE
+PFA_ASSR:
+ .dw 182
+
+.endif
+.if WANT_WATCHDOG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCSR:
+ .dw $ff06
+ .db "WDTCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCSR
+XT_WDTCSR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCSR:
+ .dw 96
+
+.endif
+.if WANT_JTAG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; On-Chip Debug Related Register in I/O Memory
+VE_OCDR:
+ .dw $ff04
+ .db "OCDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCDR
+XT_OCDR:
+ .dw PFA_DOVARIABLE
+PFA_OCDR:
+ .dw 81
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw 85
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Status Register
+VE_MCUSR:
+ .dw $ff05
+ .db "MCUSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUSR
+XT_MCUSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUSR:
+ .dw 84
+
+.endif
+.if WANT_BOOT_LOAD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control Register
+VE_SPMCSR:
+ .dw $ff06
+ .db "SPMCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCSR
+XT_SPMCSR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCSR:
+ .dw 87
+
+.endif
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register A
+VE_EICRA:
+ .dw $ff05
+ .db "EICRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRA
+XT_EICRA:
+ .dw PFA_DOVARIABLE
+PFA_EICRA:
+ .dw 105
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Mask Register
+VE_EIMSK:
+ .dw $ff05
+ .db "EIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIMSK
+XT_EIMSK:
+ .dw PFA_DOVARIABLE
+PFA_EIMSK:
+ .dw 61
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Flag Register
+VE_EIFR:
+ .dw $ff04
+ .db "EIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIFR
+XT_EIFR:
+ .dw PFA_DOVARIABLE
+PFA_EIFR:
+ .dw 60
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 3
+VE_PCMSK3:
+ .dw $ff06
+ .db "PCMSK3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK3
+XT_PCMSK3:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK3:
+ .dw 115
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 2
+VE_PCMSK2:
+ .dw $ff06
+ .db "PCMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK2
+XT_PCMSK2:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK2:
+ .dw 109
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 1
+VE_PCMSK1:
+ .dw $ff06
+ .db "PCMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK1
+XT_PCMSK1:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK1:
+ .dw 108
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 0
+VE_PCMSK0:
+ .dw $ff06
+ .db "PCMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK0
+XT_PCMSK0:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK0:
+ .dw 107
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Interrupt Flag Register
+VE_PCIFR:
+ .dw $ff05
+ .db "PCIFR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCIFR
+XT_PCIFR:
+ .dw PFA_DOVARIABLE
+PFA_PCIFR:
+ .dw 59
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Interrupt Control Register
+VE_PCICR:
+ .dw $ff05
+ .db "PCICR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCICR
+XT_PCICR:
+ .dw PFA_DOVARIABLE
+PFA_PCICR:
+ .dw 104
+
+.endif
+.if WANT_AD_CONVERTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC multiplexer Selection Register
+VE_ADMUX:
+ .dw $ff05
+ .db "ADMUX",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADMUX
+XT_ADMUX:
+ .dw PFA_DOVARIABLE
+PFA_ADMUX:
+ .dw 124
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register Bytes
+VE_ADC:
+ .dw $ff03
+ .db "ADC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADC
+XT_ADC:
+ .dw PFA_DOVARIABLE
+PFA_ADC:
+ .dw 120
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register A
+VE_ADCSRA:
+ .dw $ff06
+ .db "ADCSRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRA
+XT_ADCSRA:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRA:
+ .dw 122
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register
+VE_DIDR0:
+ .dw $ff05
+ .db "DIDR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR0
+XT_DIDR0:
+ .dw PFA_DOVARIABLE
+PFA_DIDR0:
+ .dw 126
+
+.endif
+.if WANT_TIMER_COUNTER_1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Mask Register
+VE_TIMSK1:
+ .dw $ff06
+ .db "TIMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK1
+XT_TIMSK1:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK1:
+ .dw 111
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Flag register
+VE_TIFR1:
+ .dw $ff05
+ .db "TIFR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR1
+XT_TIFR1:
+ .dw PFA_DOVARIABLE
+PFA_TIFR1:
+ .dw 54
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw 128
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw 129
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register C
+VE_TCCR1C:
+ .dw $ff06
+ .db "TCCR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1C
+XT_TCCR1C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1C:
+ .dw 130
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Bytes
+VE_TCNT1:
+ .dw $ff05
+ .db "TCNT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1
+XT_TCNT1:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1:
+ .dw 132
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register A Bytes
+VE_OCR1A:
+ .dw $ff05
+ .db "OCR1A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1A
+XT_OCR1A:
+ .dw PFA_DOVARIABLE
+PFA_OCR1A:
+ .dw 136
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register B Bytes
+VE_OCR1B:
+ .dw $ff05
+ .db "OCR1B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1B
+XT_OCR1B:
+ .dw PFA_DOVARIABLE
+PFA_OCR1B:
+ .dw 138
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Bytes
+VE_ICR1:
+ .dw $ff04
+ .db "ICR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1
+XT_ICR1:
+ .dw PFA_DOVARIABLE
+PFA_ICR1:
+ .dw 134
+
+.endif
+.if WANT_EEPROM == 1
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Address Register Low Bytes
+VE_EEAR:
+ .dw $ff04
+ .db "EEAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEAR
+XT_EEAR:
+ .dw PFA_DOVARIABLE
+PFA_EEAR:
+ .dw 65
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw 64
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw 63
+
+.endif
+.if WANT_SPI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR0:
+ .dw $ff05
+ .db "SPDR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR0
+XT_SPDR0:
+ .dw PFA_DOVARIABLE
+PFA_SPDR0:
+ .dw 78
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR0:
+ .dw $ff05
+ .db "SPSR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR0
+XT_SPSR0:
+ .dw PFA_DOVARIABLE
+PFA_SPSR0:
+ .dw 77
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR0:
+ .dw $ff05
+ .db "SPCR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR0
+XT_SPCR0:
+ .dw PFA_DOVARIABLE
+PFA_SPCR0:
+ .dw 76
+
+.endif
+.if WANT_TWI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; TWI (Slave) Address Mask Register
+VE_TWAMR:
+ .dw $ff05
+ .db "TWAMR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWAMR
+XT_TWAMR:
+ .dw PFA_DOVARIABLE
+PFA_TWAMR:
+ .dw 189
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Bit Rate register
+VE_TWBR:
+ .dw $ff04
+ .db "TWBR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWBR
+XT_TWBR:
+ .dw PFA_DOVARIABLE
+PFA_TWBR:
+ .dw 184
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Control Register
+VE_TWCR:
+ .dw $ff04
+ .db "TWCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWCR
+XT_TWCR:
+ .dw PFA_DOVARIABLE
+PFA_TWCR:
+ .dw 188
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Status Register
+VE_TWSR:
+ .dw $ff04
+ .db "TWSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWSR
+XT_TWSR:
+ .dw PFA_DOVARIABLE
+PFA_TWSR:
+ .dw 185
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Data register
+VE_TWDR:
+ .dw $ff04
+ .db "TWDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWDR
+XT_TWDR:
+ .dw PFA_DOVARIABLE
+PFA_TWDR:
+ .dw 187
+; ( -- addr ) System Constant
+; R( -- )
+; TWI (Slave) Address register
+VE_TWAR:
+ .dw $ff04
+ .db "TWAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWAR
+XT_TWAR:
+ .dw PFA_DOVARIABLE
+PFA_TWAR:
+ .dw 186
+
+.endif
+.if WANT_USART1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR1:
+ .dw $ff04
+ .db "UDR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR1
+XT_UDR1:
+ .dw PFA_DOVARIABLE
+PFA_UDR1:
+ .dw 206
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR1A:
+ .dw $ff06
+ .db "UCSR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1A
+XT_UCSR1A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1A:
+ .dw 200
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR1B:
+ .dw $ff06
+ .db "UCSR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1B
+XT_UCSR1B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1B:
+ .dw 201
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR1C:
+ .dw $ff06
+ .db "UCSR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1C
+XT_UCSR1C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1C:
+ .dw 202
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Bytes
+VE_UBRR1:
+ .dw $ff05
+ .db "UBRR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR1
+XT_UBRR1:
+ .dw PFA_DOVARIABLE
+PFA_UBRR1:
+ .dw 204
+
+.endif
+.if WANT_CPU == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw 95
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer
+VE_SP:
+ .dw $ff02
+ .db "SP"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SP
+XT_SP:
+ .dw PFA_DOVARIABLE
+PFA_SP:
+ .dw 93
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Calibration Value
+VE_OSCCAL:
+ .dw $ff06
+ .db "OSCCAL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSCCAL
+XT_OSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_OSCCAL:
+ .dw 102
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_CLKPR:
+ .dw $ff05
+ .db "CLKPR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKPR
+XT_CLKPR:
+ .dw PFA_DOVARIABLE
+PFA_CLKPR:
+ .dw 97
+; ( -- addr ) System Constant
+; R( -- )
+; Sleep Mode Control Register
+VE_SMCR:
+ .dw $ff04
+ .db "SMCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SMCR
+XT_SMCR:
+ .dw PFA_DOVARIABLE
+PFA_SMCR:
+ .dw 83
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 2
+VE_GPIOR2:
+ .dw $ff06
+ .db "GPIOR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR2
+XT_GPIOR2:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR2:
+ .dw 75
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 1
+VE_GPIOR1:
+ .dw $ff06
+ .db "GPIOR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR1
+XT_GPIOR1:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR1:
+ .dw 74
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 0
+VE_GPIOR0:
+ .dw $ff06
+ .db "GPIOR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR0
+XT_GPIOR0:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR0:
+ .dw 62
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register0
+VE_PRR0:
+ .dw $ff04
+ .db "PRR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR0
+XT_PRR0:
+ .dw PFA_DOVARIABLE
+PFA_PRR0:
+ .dw 100
+
+.endif
diff --git a/amforth-6.5/avr8/devices/atmega324a/device.py b/amforth-6.5/avr8/devices/atmega324a/device.py
new file mode 100644
index 0000000..8c0a285
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega324a/device.py
@@ -0,0 +1,388 @@
+# Generated Automatically
+
+# Partname ATmega324A
+
+MCUREGS = {
+# Interrupt Vectors
+ 'INT0Addr' : '#2', # External Interrupt Request 0
+ 'INT1Addr' : '#4', # External Interrupt Request 1
+ 'INT2Addr' : '#6', # External Interrupt Request 2
+ 'PCINT0Addr' : '#8', # Pin Change Interrupt Request 0
+ 'PCINT1Addr' : '#10', # Pin Change Interrupt Request 1
+ 'PCINT2Addr' : '#12', # Pin Change Interrupt Request 2
+ 'PCINT3Addr' : '#14', # Pin Change Interrupt Request 3
+ 'WDTAddr' : '#16', # Watchdog Time-out Interrupt
+ 'TIMER2_COMPAAddr' : '#18', # Timer/Counter2 Compare Match A
+ 'TIMER2_COMPBAddr' : '#20', # Timer/Counter2 Compare Match B
+ 'TIMER2_OVFAddr' : '#22', # Timer/Counter2 Overflow
+ 'TIMER1_CAPTAddr' : '#24', # Timer/Counter1 Capture Event
+ 'TIMER1_COMPAAddr' : '#26', # Timer/Counter1 Compare Match A
+ 'TIMER1_COMPBAddr' : '#28', # Timer/Counter1 Compare Match B
+ 'TIMER1_OVFAddr' : '#30', # Timer/Counter1 Overflow
+ 'TIMER0_COMPAAddr' : '#32', # Timer/Counter0 Compare Match A
+ 'TIMER0_COMPBAddr' : '#34', # Timer/Counter0 Compare Match B
+ 'TIMER0_OVFAddr' : '#36', # Timer/Counter0 Overflow
+ 'SPI_STCAddr' : '#38', # SPI Serial Transfer Complete
+ 'USART0_RXAddr' : '#40', # USART0, Rx Complete
+ 'USART0_UDREAddr' : '#42', # USART0 Data register Empty
+ 'USART0_TXAddr' : '#44', # USART0, Tx Complete
+ 'ANALOG_COMPAddr' : '#46', # Analog Comparator
+ 'ADCAddr' : '#48', # ADC Conversion Complete
+ 'EE_READYAddr' : '#50', # EEPROM Ready
+ 'TWIAddr' : '#52', # 2-wire Serial Interface
+ 'SPM_READYAddr' : '#54', # Store Program Memory Read
+ 'USART1_RXAddr' : '#56', # USART1 RX complete
+ 'USART1_UDREAddr' : '#58', # USART1 Data Register Empty
+ 'USART1_TXAddr' : '#60', # USART1 TX complete
+
+# Module ANALOG_COMPARATOR
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
+ 'ACSR' : '$50', # Analog Comparator Control And
+ 'ACSR_ACD': '$80', # Analog Comparator Disable
+ 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
+ 'ACSR_ACO': '$20', # Analog Compare Output
+ 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
+ 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
+ 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
+ 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
+ 'DIDR1' : '$7f', # Digital Input Disable Register
+ 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
+ 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
+
+# Module USART0
+ 'UDR0' : '$c6', # USART I/O Data Register
+ 'UCSR0A' : '$c0', # USART Control and Status Regis
+ 'UCSR0A_RXC0': '$80', # USART Receive Complete
+ 'UCSR0A_TXC0': '$40', # USART Transmitt Complete
+ 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
+ 'UCSR0A_FE0': '$10', # Framing Error
+ 'UCSR0A_DOR0': '$8', # Data overRun
+ 'UCSR0A_UPE0': '$4', # Parity Error
+ 'UCSR0A_U2X0': '$2', # Double the USART transmission
+ 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
+ 'UCSR0B' : '$c1', # USART Control and Status Regis
+ 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
+ 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
+ 'UCSR0B_UDRIE0': '$20', # USART Data register Empty Inte
+ 'UCSR0B_RXEN0': '$10', # Receiver Enable
+ 'UCSR0B_TXEN0': '$8', # Transmitter Enable
+ 'UCSR0B_UCSZ02': '$4', # Character Size
+ 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
+ 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
+ 'UCSR0C' : '$c2', # USART Control and Status Regis
+ 'UCSR0C_UMSEL0': '$c0', # USART Mode Select
+ 'UCSR0C_UPM0': '$30', # Parity Mode Bits
+ 'UCSR0C_USBS0': '$8', # Stop Bit Select
+ 'UCSR0C_UCSZ0': '$6', # Character Size
+ 'UCSR0C_UCPOL0': '$1', # Clock Polarity
+ 'UBRR0' : '$c4', # USART Baud Rate Register Byte
+
+# Module PORTA
+ 'PORTA' : '$22', # Port A Data Register
+ 'DDRA' : '$21', # Port A Data Direction Register
+ 'PINA' : '$20', # Port A Input Pins
+
+# Module PORTB
+ 'PORTB' : '$25', # Port B Data Register
+ 'DDRB' : '$24', # Port B Data Direction Register
+ 'PINB' : '$23', # Port B Input Pins
+
+# Module PORTC
+ 'PORTC' : '$28', # Port C Data Register
+ 'DDRC' : '$27', # Port C Data Direction Register
+ 'PINC' : '$26', # Port C Input Pins
+
+# Module PORTD
+ 'PORTD' : '$2b', # Port D Data Register
+ 'DDRD' : '$2a', # Port D Data Direction Register
+ 'PIND' : '$29', # Port D Input Pins
+
+# Module TIMER_COUNTER_0
+ 'OCR0B' : '$48', # Timer/Counter0 Output Compare
+ 'OCR0A' : '$47', # Timer/Counter0 Output Compare
+ 'TCNT0' : '$46', # Timer/Counter0
+ 'TCCR0B' : '$45', # Timer/Counter Control Register
+ 'TCCR0B_FOC0A': '$80', # Force Output Compare A
+ 'TCCR0B_FOC0B': '$40', # Force Output Compare B
+ 'TCCR0B_WGM02': '$8', #
+ 'TCCR0B_CS0': '$7', # Clock Select
+ 'TCCR0A' : '$44', # Timer/Counter Control Registe
+ 'TCCR0A_COM0A': '$c0', # Compare Output Mode, Phase Cor
+ 'TCCR0A_COM0B': '$30', # Compare Output Mode, Fast PWm
+ 'TCCR0A_WGM0': '$3', # Waveform Generation Mode
+ 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
+ 'TIMSK0_OCIE0B': '$4', # Timer/Counter0 Output Compare
+ 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
+ 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
+ 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
+ 'TIFR0_OCF0B': '$4', # Timer/Counter0 Output Compare
+ 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
+ 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSRSYNC': '$1', # Prescaler Reset Timer/Counter1
+
+# Module TIMER_COUNTER_2
+ 'TIMSK2' : '$70', # Timer/Counter Interrupt Mask r
+ 'TIMSK2_OCIE2B': '$4', # Timer/Counter2 Output Compare
+ 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
+ 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
+ 'TIFR2' : '$37', # Timer/Counter Interrupt Flag R
+ 'TIFR2_OCF2B': '$4', # Output Compare Flag 2B
+ 'TIFR2_OCF2A': '$2', # Output Compare Flag 2A
+ 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
+ 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
+ 'TCCR2A_COM2A': '$c0', # Compare Output Mode bits
+ 'TCCR2A_COM2B': '$30', # Compare Output Mode bits
+ 'TCCR2A_WGM2': '$3', # Waveform Genration Mode
+ 'TCCR2B' : '$b1', # Timer/Counter2 Control Registe
+ 'TCCR2B_FOC2A': '$80', # Force Output Compare A
+ 'TCCR2B_FOC2B': '$40', # Force Output Compare B
+ 'TCCR2B_WGM22': '$8', # Waveform Generation Mode
+ 'TCCR2B_CS2': '$7', # Clock Select bits
+ 'TCNT2' : '$b2', # Timer/Counter2
+ 'OCR2B' : '$b4', # Timer/Counter2 Output Compare
+ 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
+ 'ASSR' : '$b6', # Asynchronous Status Register
+ 'ASSR_EXCLK': '$40', # Enable External Clock Input
+ 'ASSR_AS2': '$20', # Asynchronous Timer/Counter2
+ 'ASSR_TCN2UB': '$10', # Timer/Counter2 Update Busy
+ 'ASSR_OCR2AUB': '$8', # Output Compare Register2 Updat
+ 'ASSR_OCR2BUB': '$4', # Output Compare Register 2 Upda
+ 'ASSR_TCR2AUB': '$2', # Timer/Counter Control Register
+ 'ASSR_TCR2BUB': '$1', # Timer/Counter Control Register
+ 'GTCCR' : '$43', # General Timer Counter Control
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSRASY': '$2', # Prescaler Reset Timer/Counter2
+
+# Module WATCHDOG
+ 'WDTCSR' : '$60', # Watchdog Timer Control Registe
+ 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
+ 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
+ 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
+ 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
+ 'WDTCSR_WDE': '$8', # Watch Dog Enable
+
+# Module JTAG
+ 'OCDR' : '$51', # On-Chip Debug Related Register
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_JTD': '$80', # JTAG Interface Disable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+
+# Module BOOT_LOAD
+ 'SPMCSR' : '$57', # Store Program Memory Control R
+ 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
+ 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
+ 'SPMCSR_SIGRD': '$20', # Signature Row Read
+ 'SPMCSR_RWWSRE': '$10', # Read While Write section read
+ 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
+ 'SPMCSR_PGWRT': '$4', # Page Write
+ 'SPMCSR_PGERS': '$2', # Page Erase
+ 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
+
+# Module EXTERNAL_INTERRUPT
+ 'EICRA' : '$69', # External Interrupt Control Reg
+ 'EICRA_ISC2': '$30', # External Interrupt Sense Contr
+ 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
+ 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
+ 'EIMSK' : '$3d', # External Interrupt Mask Regist
+ 'EIMSK_INT': '$7', # External Interrupt Request 2 E
+ 'EIFR' : '$3c', # External Interrupt Flag Regist
+ 'EIFR_INTF': '$7', # External Interrupt Flags
+ 'PCMSK3' : '$73', # Pin Change Mask Register 3
+ 'PCMSK3_PCINT': '$ff', # Pin Change Enable Masks
+ 'PCMSK2' : '$6d', # Pin Change Mask Register 2
+ 'PCMSK2_PCINT': '$ff', # Pin Change Enable Masks
+ 'PCMSK1' : '$6c', # Pin Change Mask Register 1
+ 'PCMSK1_PCINT': '$ff', # Pin Change Enable Masks
+ 'PCMSK0' : '$6b', # Pin Change Mask Register 0
+ 'PCMSK0_PCINT': '$ff', # Pin Change Enable Masks
+ 'PCIFR' : '$3b', # Pin Change Interrupt Flag Regi
+ 'PCIFR_PCIF': '$f', # Pin Change Interrupt Flags
+ 'PCICR' : '$68', # Pin Change Interrupt Control R
+ 'PCICR_PCIE': '$f', # Pin Change Interrupt Enables
+
+# Module AD_CONVERTER
+ 'ADMUX' : '$7c', # The ADC multiplexer Selection
+ 'ADMUX_REFS': '$c0', # Reference Selection Bits
+ 'ADMUX_ADLAR': '$20', # Left Adjust Result
+ 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
+ 'ADC' : '$78', # ADC Data Register Bytes
+ 'ADCSRA' : '$7a', # The ADC Control and Status reg
+ 'ADCSRA_ADEN': '$80', # ADC Enable
+ 'ADCSRA_ADSC': '$40', # ADC Start Conversion
+ 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
+ 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
+ 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
+ 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
+ 'ADCSRB' : '$7b', # The ADC Control and Status reg
+ 'ADCSRB_ACME': '$40', #
+ 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Source bits
+ 'DIDR0' : '$7e', # Digital Input Disable Register
+ 'DIDR0_ADC7D': '$80', #
+ 'DIDR0_ADC6D': '$40', #
+ 'DIDR0_ADC5D': '$20', #
+ 'DIDR0_ADC4D': '$10', #
+ 'DIDR0_ADC3D': '$8', #
+ 'DIDR0_ADC2D': '$4', #
+ 'DIDR0_ADC1D': '$2', #
+ 'DIDR0_ADC0D': '$1', #
+
+# Module TIMER_COUNTER_1
+ 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
+ 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
+ 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
+ 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
+ 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
+ 'TIFR1' : '$36', # Timer/Counter Interrupt Flag r
+ 'TIFR1_ICF1': '$20', # Timer/Counter1 Input Capture F
+ 'TIFR1_OCF1B': '$4', # Timer/Counter1 Output Compare
+ 'TIFR1_OCF1A': '$2', # Timer/Counter1 Output Compare
+ 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
+ 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
+ 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
+ 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
+ 'TCCR1A_WGM1': '$3', # Pulse Width Modulator Select B
+ 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
+ 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
+ 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
+ 'TCCR1B_WGM1': '$18', # Waveform Generation Mode Bits
+ 'TCCR1B_CS1': '$7', # Clock Select1 bits
+ 'TCCR1C' : '$82', # Timer/Counter1 Control Registe
+ 'TCCR1C_FOC1A': '$80', # Force Output Compare for Chann
+ 'TCCR1C_FOC1B': '$40', # Force Output Compare for Chann
+ 'TCNT1' : '$84', # Timer/Counter1 Bytes
+ 'OCR1A' : '$88', # Timer/Counter1 Output Compare
+ 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
+ 'ICR1' : '$86', # Timer/Counter1 Input Capture R
+
+# Module EEPROM
+ 'EEAR' : '$41', # EEPROM Address Register Low By
+ 'EEDR' : '$40', # EEPROM Data Register
+ 'EECR' : '$3f', # EEPROM Control Register
+ 'EECR_EEPM': '$30', # EEPROM Programming Mode Bits
+ 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
+ 'EECR_EEMPE': '$4', # EEPROM Master Write Enable
+ 'EECR_EEPE': '$2', # EEPROM Write Enable
+ 'EECR_EERE': '$1', # EEPROM Read Enable
+
+# Module SPI
+ 'SPDR0' : '$4e', # SPI Data Register
+ 'SPSR0' : '$4d', # SPI Status Register
+ 'SPSR0_SPIF0': '$80', # SPI Interrupt Flag
+ 'SPSR0_WCOL0': '$40', # Write Collision Flag
+ 'SPSR0_SPI2X0': '$1', # Double SPI Speed Bit
+ 'SPCR0' : '$4c', # SPI Control Register
+ 'SPCR0_SPIE0': '$80', # SPI Interrupt Enable
+ 'SPCR0_SPE0': '$40', # SPI Enable
+ 'SPCR0_DORD0': '$20', # Data Order
+ 'SPCR0_MSTR0': '$10', # Master/Slave Select
+ 'SPCR0_CPOL0': '$8', # Clock polarity
+ 'SPCR0_CPHA0': '$4', # Clock Phase
+ 'SPCR0_SPR10': '$2', # SPI Clock Rate Select 1
+ 'SPCR0_SPR00': '$1', # SPI Clock Rate Select 0
+
+# Module TWI
+ 'TWAMR' : '$bd', # TWI (Slave) Address Mask Regis
+ 'TWAMR_TWAM': '$fe', #
+ 'TWBR' : '$b8', # TWI Bit Rate register
+ 'TWCR' : '$bc', # TWI Control Register
+ 'TWCR_TWINT': '$80', # TWI Interrupt Flag
+ 'TWCR_TWEA': '$40', # TWI Enable Acknowledge Bit
+ 'TWCR_TWSTA': '$20', # TWI Start Condition Bit
+ 'TWCR_TWSTO': '$10', # TWI Stop Condition Bit
+ 'TWCR_TWWC': '$8', # TWI Write Collition Flag
+ 'TWCR_TWEN': '$4', # TWI Enable Bit
+ 'TWCR_TWIE': '$1', # TWI Interrupt Enable
+ 'TWSR' : '$b9', # TWI Status Register
+ 'TWSR_TWS': '$f8', # TWI Status
+ 'TWSR_TWPS': '$3', # TWI Prescaler
+ 'TWDR' : '$bb', # TWI Data register
+ 'TWAR' : '$ba', # TWI (Slave) Address register
+ 'TWAR_TWA': '$fe', # TWI (Slave) Address register B
+ 'TWAR_TWGCE': '$1', # TWI General Call Recognition E
+
+# Module USART1
+ 'UDR1' : '$ce', # USART I/O Data Register
+ 'UCSR1A' : '$c8', # USART Control and Status Regis
+ 'UCSR1A_RXC1': '$80', # USART Receive Complete
+ 'UCSR1A_TXC1': '$40', # USART Transmitt Complete
+ 'UCSR1A_UDRE1': '$20', # USART Data Register Empty
+ 'UCSR1A_FE1': '$10', # Framing Error
+ 'UCSR1A_DOR1': '$8', # Data overRun
+ 'UCSR1A_UPE1': '$4', # Parity Error
+ 'UCSR1A_U2X1': '$2', # Double the USART transmission
+ 'UCSR1A_MPCM1': '$1', # Multi-processor Communication
+ 'UCSR1B' : '$c9', # USART Control and Status Regis
+ 'UCSR1B_RXCIE1': '$80', # RX Complete Interrupt Enable
+ 'UCSR1B_TXCIE1': '$40', # TX Complete Interrupt Enable
+ 'UCSR1B_UDRIE1': '$20', # USART Data register Empty Inte
+ 'UCSR1B_RXEN1': '$10', # Receiver Enable
+ 'UCSR1B_TXEN1': '$8', # Transmitter Enable
+ 'UCSR1B_UCSZ12': '$4', # Character Size
+ 'UCSR1B_RXB81': '$2', # Receive Data Bit 8
+ 'UCSR1B_TXB81': '$1', # Transmit Data Bit 8
+ 'UCSR1C' : '$ca', # USART Control and Status Regis
+ 'UCSR1C_UMSEL1': '$c0', # USART Mode Select
+ 'UCSR1C_UPM1': '$30', # Parity Mode Bits
+ 'UCSR1C_USBS1': '$8', # Stop Bit Select
+ 'UCSR1C_UCSZ1': '$6', # Character Size
+ 'UCSR1C_UCPOL1': '$1', # Clock Polarity
+ 'UBRR1' : '$cc', # USART Baud Rate Register Byte
+
+# Module CPU
+ 'SREG' : '$5f', # Status Register
+ 'SREG_I': '$80', # Global Interrupt Enable
+ 'SREG_T': '$40', # Bit Copy Storage
+ 'SREG_H': '$20', # Half Carry Flag
+ 'SREG_S': '$10', # Sign Bit
+ 'SREG_V': '$8', # Two's Complement Overflow Flag
+ 'SREG_N': '$4', # Negative Flag
+ 'SREG_Z': '$2', # Zero Flag
+ 'SREG_C': '$1', # Carry Flag
+ 'SP' : '$5d', # Stack Pointer
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_JTD': '$80', # JTAG Interface Disable
+ 'MCUCR_PUD': '$10', # Pull-up disable
+ 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
+ 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+ 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
+ 'MCUSR_BORF': '$4', # Brown-out Reset Flag
+ 'MCUSR_EXTRF': '$2', # External Reset Flag
+ 'MCUSR_PORF': '$1', # Power-on reset flag
+ 'OSCCAL' : '$66', # Oscillator Calibration Value
+ 'CLKPR' : '$61', #
+ 'CLKPR_CLKPCE': '$80', #
+ 'CLKPR_CLKPS': '$f', #
+ 'SMCR' : '$53', # Sleep Mode Control Register
+ 'SMCR_SM': '$e', # Sleep Mode Select bits
+ 'SMCR_SE': '$1', # Sleep Enable
+ 'GPIOR2' : '$4b', # General Purpose IO Register 2
+ 'GPIOR2_GPIOR': '$ff', # General Purpose IO Register 2
+ 'GPIOR1' : '$4a', # General Purpose IO Register 1
+ 'GPIOR1_GPIOR': '$ff', # General Purpose IO Register 1
+ 'GPIOR0' : '$3e', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR07': '$80', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR06': '$40', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR05': '$20', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR04': '$10', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR03': '$8', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR02': '$4', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR01': '$2', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR00': '$1', # General Purpose IO Register 0
+ 'PRR0' : '$64', # Power Reduction Register0
+ 'PRR0_PRTWI': '$80', # Power Reduction TWI
+ 'PRR0_PRTIM2': '$40', # Power Reduction Timer/Counter2
+ 'PRR0_PRTIM0': '$20', # Power Reduction Timer/Counter0
+ 'PRR0_PRUSART1': '$10', # Power Reduction USARTs
+ 'PRR0_PRTIM1': '$8', # Power Reduction Timer/Counter1
+ 'PRR0_PRSPI': '$4', # Power Reduction Serial Periphe
+ 'PRR0_PRUSART0': '$2', # Power Reduction USARTs
+ 'PRR0_PRADC': '$1', # Power Reduction ADC
+
+ '__amforth_dummy':'0'
+}
diff --git a/amforth-6.5/avr8/devices/atmega324a/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega324a/words/no-jtag.asm
new file mode 100644
index 0000000..352a4bb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega324a/words/no-jtag.asm
@@ -0,0 +1,14 @@
+; ( -- )
+; ( -- )
+; MCU
+; disable jtag at runtime
+VE_NOJTAG:
+ .dw $FF05
+ .db "-jtag",0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOJTAG
+XT_NOJTAG:
+ .dw PFA_NOJTAG
+PFA_NOJTAG:
+
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega324a/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega324a/words/no-wdt.asm
new file mode 100644
index 0000000..ff6ddd1
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega324a/words/no-wdt.asm
@@ -0,0 +1,34 @@
+; ( -- )
+; MCU
+; disable watch dog timer at runtime
+VE_NOWDT:
+ .dw $ff04
+ .db "-wdt"
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOWDT
+XT_NOWDT:
+ .dw PFA_NOWDT
+PFA_NOWDT:
+
+ in temp1,SREG
+ push temp1
+ ; Turn always off global interrupt.
+ cli
+ ; Reset Watchdog Timer
+ wdr
+ ; Clear WDRF in MCUSR
+ in temp1, MCUSR
+ andi temp1, (0xff & (0<<WDRF))
+ out MCUSR, temp1
+ ; Write logical one to WDCE and WDE
+ ; Keep old prescaler setting to prevent unintentional time-out
+ in_ temp1, WDTCSR
+ ori temp1, (1<<WDCE) | (1<<WDE)
+ out_ WDTCSR, temp1
+ ; Turn off WDT
+ ldi temp1, (0<<WDE)
+ out_ WDTCSR, temp1
+ ; restore status register
+ pop temp1
+ out SREG,temp1
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega324a/words/sleep.asm b/amforth-6.5/avr8/devices/atmega324a/words/sleep.asm
new file mode 100644
index 0000000..256249c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega324a/words/sleep.asm
@@ -0,0 +1,19 @@
+; ( mode -- )
+; MCU
+; put the controller into the specified sleep mode
+VE_SLEEP:
+ .dw $ff05
+ .db "sleep", 0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_SLEEP
+XT_SLEEP:
+ .dw PFA_SLEEP
+PFA_SLEEP:
+ andi tosl, 7 ; leave only legal mode bits
+ lsl tosl ; move to correct location (bits 3-1)
+ ori tosl, 1 ; set the SE bit
+ out_ SMCR, tosl ; set the sleep config
+ sleep ; nighty-night
+ out_ SMCR, zerol ; 0 protects against accidental sleeps
+ loadtos ; pop argument from stack
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega324p/atmega324p.frt b/amforth-6.5/avr8/devices/atmega324p/atmega324p.frt
new file mode 100644
index 0000000..de8d590
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega324p/atmega324p.frt
@@ -0,0 +1,347 @@
+\ Partname: ATmega324P
+\ generated automatically
+
+\ ANALOG_COMPARATOR
+&123 constant ADCSRB \ ADC Control and Status Register B
+ $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer Enable
+&80 constant ACSR \ Analog Comparator Control And Status Register
+ $80 constant ACSR_ACD \ Analog Comparator Disable
+ $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
+ $20 constant ACSR_ACO \ Analog Compare Output
+ $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
+ $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
+ $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
+ $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
+&127 constant DIDR1 \ Digital Input Disable Register 1
+ $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
+ $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
+\ USART0
+&198 constant UDR0 \ USART I/O Data Register
+&192 constant UCSR0A \ USART Control and Status Register A
+ $80 constant UCSR0A_RXC0 \ USART Receive Complete
+ $40 constant UCSR0A_TXC0 \ USART Transmitt Complete
+ $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
+ $10 constant UCSR0A_FE0 \ Framing Error
+ $08 constant UCSR0A_DOR0 \ Data overRun
+ $04 constant UCSR0A_UPE0 \ Parity Error
+ $02 constant UCSR0A_U2X0 \ Double the USART transmission speed
+ $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
+&193 constant UCSR0B \ USART Control and Status Register B
+ $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
+ $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
+ $20 constant UCSR0B_UDRIE0 \ USART Data register Empty Interrupt Enable
+ $10 constant UCSR0B_RXEN0 \ Receiver Enable
+ $08 constant UCSR0B_TXEN0 \ Transmitter Enable
+ $04 constant UCSR0B_UCSZ02 \ Character Size
+ $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
+ $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
+&194 constant UCSR0C \ USART Control and Status Register C
+ $C0 constant UCSR0C_UMSEL0 \ USART Mode Select
+ $30 constant UCSR0C_UPM0 \ Parity Mode Bits
+ $08 constant UCSR0C_USBS0 \ Stop Bit Select
+ $06 constant UCSR0C_UCSZ0 \ Character Size
+ $01 constant UCSR0C_UCPOL0 \ Clock Polarity
+&196 constant UBRR0 \ USART Baud Rate Register Bytes
+\ PORTA
+&34 constant PORTA \ Port A Data Register
+&33 constant DDRA \ Port A Data Direction Register
+&32 constant PINA \ Port A Input Pins
+\ PORTB
+&37 constant PORTB \ Port B Data Register
+&36 constant DDRB \ Port B Data Direction Register
+&35 constant PINB \ Port B Input Pins
+\ PORTC
+&40 constant PORTC \ Port C Data Register
+&39 constant DDRC \ Port C Data Direction Register
+&38 constant PINC \ Port C Input Pins
+\ PORTD
+&43 constant PORTD \ Port D Data Register
+&42 constant DDRD \ Port D Data Direction Register
+&41 constant PIND \ Port D Input Pins
+\ TIMER_COUNTER_0
+&72 constant OCR0B \ Timer/Counter0 Output Compare Register
+&71 constant OCR0A \ Timer/Counter0 Output Compare Register
+&70 constant TCNT0 \ Timer/Counter0
+&69 constant TCCR0B \ Timer/Counter Control Register B
+ $80 constant TCCR0B_FOC0A \ Force Output Compare A
+ $40 constant TCCR0B_FOC0B \ Force Output Compare B
+ $08 constant TCCR0B_WGM02 \
+ $07 constant TCCR0B_CS0 \ Clock Select
+&68 constant TCCR0A \ Timer/Counter Control Register A
+ $C0 constant TCCR0A_COM0A \ Compare Output Mode, Phase Correct PWM Mode
+ $30 constant TCCR0A_COM0B \ Compare Output Mode, Fast PWm
+ $03 constant TCCR0A_WGM0 \ Waveform Generation Mode
+&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
+ $04 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare Match B Interrupt Enable
+ $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match A Interrupt Enable
+ $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
+&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
+ $04 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare Flag 0B
+ $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0A
+ $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
+&67 constant GTCCR \ General Timer/Counter Control Register
+ $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
+ $01 constant GTCCR_PSRSYNC \ Prescaler Reset Timer/Counter1 and Timer/Counter0
+\ TIMER_COUNTER_2
+&112 constant TIMSK2 \ Timer/Counter Interrupt Mask register
+ $04 constant TIMSK2_OCIE2B \ Timer/Counter2 Output Compare Match B Interrupt Enable
+ $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match A Interrupt Enable
+ $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
+&55 constant TIFR2 \ Timer/Counter Interrupt Flag Register
+ $04 constant TIFR2_OCF2B \ Output Compare Flag 2B
+ $02 constant TIFR2_OCF2A \ Output Compare Flag 2A
+ $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
+&176 constant TCCR2A \ Timer/Counter2 Control Register A
+ $C0 constant TCCR2A_COM2A \ Compare Output Mode bits
+ $30 constant TCCR2A_COM2B \ Compare Output Mode bits
+ $03 constant TCCR2A_WGM2 \ Waveform Genration Mode
+&177 constant TCCR2B \ Timer/Counter2 Control Register B
+ $80 constant TCCR2B_FOC2A \ Force Output Compare A
+ $40 constant TCCR2B_FOC2B \ Force Output Compare B
+ $08 constant TCCR2B_WGM22 \ Waveform Generation Mode
+ $07 constant TCCR2B_CS2 \ Clock Select bits
+&178 constant TCNT2 \ Timer/Counter2
+&180 constant OCR2B \ Timer/Counter2 Output Compare Register B
+&179 constant OCR2A \ Timer/Counter2 Output Compare Register A
+&182 constant ASSR \ Asynchronous Status Register
+ $40 constant ASSR_EXCLK \ Enable External Clock Input
+ $20 constant ASSR_AS2 \ Asynchronous Timer/Counter2
+ $10 constant ASSR_TCN2UB \ Timer/Counter2 Update Busy
+ $08 constant ASSR_OCR2AUB \ Output Compare Register2 Update Busy
+ $04 constant ASSR_OCR2BUB \ Output Compare Register 2 Update Busy
+ $02 constant ASSR_TCR2AUB \ Timer/Counter Control Register2 Update Busy
+ $01 constant ASSR_TCR2BUB \ Timer/Counter Control Register2 Update Busy
+\ WATCHDOG
+&96 constant WDTCSR \ Watchdog Timer Control Register
+ $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Flag
+ $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Enable
+ $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
+ $10 constant WDTCSR_WDCE \ Watchdog Change Enable
+ $08 constant WDTCSR_WDE \ Watch Dog Enable
+\ JTAG
+&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
+&85 constant MCUCR \ MCU Control Register
+ $80 constant MCUCR_JTD \ JTAG Interface Disable
+&84 constant MCUSR \ MCU Status Register
+ $10 constant MCUSR_JTRF \ JTAG Reset Flag
+\ BOOT_LOAD
+&87 constant SPMCSR \ Store Program Memory Control Register
+ $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
+ $20 constant SPMCSR_SIGRD \ Signature Row Read
+ $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
+ $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
+ $04 constant SPMCSR_PGWRT \ Page Write
+ $02 constant SPMCSR_PGERS \ Page Erase
+ $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
+\ EXTERNAL_INTERRUPT
+&105 constant EICRA \ External Interrupt Control Register A
+ $30 constant EICRA_ISC2 \ External Interrupt Sense Control Bit
+ $0C constant EICRA_ISC1 \ External Interrupt Sense Control Bit
+ $03 constant EICRA_ISC0 \ External Interrupt Sense Control Bit
+&61 constant EIMSK \ External Interrupt Mask Register
+ $07 constant EIMSK_INT \ External Interrupt Request 2 Enable
+&60 constant EIFR \ External Interrupt Flag Register
+ $07 constant EIFR_INTF \ External Interrupt Flags
+&115 constant PCMSK3 \ Pin Change Mask Register 3
+ $FF constant PCMSK3_PCINT \ Pin Change Enable Masks
+&109 constant PCMSK2 \ Pin Change Mask Register 2
+ $FF constant PCMSK2_PCINT \ Pin Change Enable Masks
+&108 constant PCMSK1 \ Pin Change Mask Register 1
+ $FF constant PCMSK1_PCINT \ Pin Change Enable Masks
+&107 constant PCMSK0 \ Pin Change Mask Register 0
+ $FF constant PCMSK0_PCINT \ Pin Change Enable Masks
+&59 constant PCIFR \ Pin Change Interrupt Flag Register
+ $0F constant PCIFR_PCIF \ Pin Change Interrupt Flags
+&104 constant PCICR \ Pin Change Interrupt Control Register
+ $0F constant PCICR_PCIE \ Pin Change Interrupt Enables
+\ AD_CONVERTER
+&124 constant ADMUX \ The ADC multiplexer Selection Register
+ $C0 constant ADMUX_REFS \ Reference Selection Bits
+ $20 constant ADMUX_ADLAR \ Left Adjust Result
+ $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
+&120 constant ADC \ ADC Data Register Bytes
+&122 constant ADCSRA \ The ADC Control and Status register A
+ $80 constant ADCSRA_ADEN \ ADC Enable
+ $40 constant ADCSRA_ADSC \ ADC Start Conversion
+ $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
+ $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
+ $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
+ $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
+&126 constant DIDR0 \ Digital Input Disable Register
+ $80 constant DIDR0_ADC7D \
+ $40 constant DIDR0_ADC6D \
+ $20 constant DIDR0_ADC5D \
+ $10 constant DIDR0_ADC4D \
+ $08 constant DIDR0_ADC3D \
+ $04 constant DIDR0_ADC2D \
+ $02 constant DIDR0_ADC1D \
+ $01 constant DIDR0_ADC0D \
+\ TIMER_COUNTER_1
+&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
+ $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
+ $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
+ $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
+ $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
+&54 constant TIFR1 \ Timer/Counter Interrupt Flag register
+ $20 constant TIFR1_ICF1 \ Timer/Counter1 Input Capture Flag
+ $04 constant TIFR1_OCF1B \ Timer/Counter1 Output Compare B Match Flag
+ $02 constant TIFR1_OCF1A \ Timer/Counter1 Output Compare A Match Flag
+ $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
+&128 constant TCCR1A \ Timer/Counter1 Control Register A
+ $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
+ $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
+ $03 constant TCCR1A_WGM1 \ Pulse Width Modulator Select Bits
+&129 constant TCCR1B \ Timer/Counter1 Control Register B
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ $18 constant TCCR1B_WGM1 \ Waveform Generation Mode Bits
+ $07 constant TCCR1B_CS1 \ Clock Select1 bits
+&130 constant TCCR1C \ Timer/Counter1 Control Register C
+ $80 constant TCCR1C_FOC1A \ Force Output Compare for Channel A
+ $40 constant TCCR1C_FOC1B \ Force Output Compare for Channel B
+&132 constant TCNT1 \ Timer/Counter1 Bytes
+&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
+&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
+&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
+\ EEPROM
+&65 constant EEAR \ EEPROM Address Register Low Bytes
+&64 constant EEDR \ EEPROM Data Register
+&63 constant EECR \ EEPROM Control Register
+ $30 constant EECR_EEPM \ EEPROM Programming Mode Bits
+ $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
+ $04 constant EECR_EEMPE \ EEPROM Master Write Enable
+ $02 constant EECR_EEPE \ EEPROM Write Enable
+ $01 constant EECR_EERE \ EEPROM Read Enable
+\ SPI
+&78 constant SPDR0 \ SPI Data Register
+&77 constant SPSR0 \ SPI Status Register
+ $80 constant SPSR0_SPIF0 \ SPI Interrupt Flag
+ $40 constant SPSR0_WCOL0 \ Write Collision Flag
+ $01 constant SPSR0_SPI2X0 \ Double SPI Speed Bit
+&76 constant SPCR0 \ SPI Control Register
+ $80 constant SPCR0_SPIE0 \ SPI Interrupt Enable
+ $40 constant SPCR0_SPE0 \ SPI Enable
+ $20 constant SPCR0_DORD0 \ Data Order
+ $10 constant SPCR0_MSTR0 \ Master/Slave Select
+ $08 constant SPCR0_CPOL0 \ Clock polarity
+ $04 constant SPCR0_CPHA0 \ Clock Phase
+ $02 constant SPCR0_SPR10 \ SPI Clock Rate Select 1
+ $01 constant SPCR0_SPR00 \ SPI Clock Rate Select 0
+\ TWI
+&189 constant TWAMR \ TWI (Slave) Address Mask Register
+ $FE constant TWAMR_TWAM \
+&184 constant TWBR \ TWI Bit Rate register
+&188 constant TWCR \ TWI Control Register
+ $80 constant TWCR_TWINT \ TWI Interrupt Flag
+ $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
+ $20 constant TWCR_TWSTA \ TWI Start Condition Bit
+ $10 constant TWCR_TWSTO \ TWI Stop Condition Bit
+ $08 constant TWCR_TWWC \ TWI Write Collition Flag
+ $04 constant TWCR_TWEN \ TWI Enable Bit
+ $01 constant TWCR_TWIE \ TWI Interrupt Enable
+&185 constant TWSR \ TWI Status Register
+ $F8 constant TWSR_TWS \ TWI Status
+ $03 constant TWSR_TWPS \ TWI Prescaler
+&187 constant TWDR \ TWI Data register
+&186 constant TWAR \ TWI (Slave) Address register
+ $FE constant TWAR_TWA \ TWI (Slave) Address register Bits
+ $01 constant TWAR_TWGCE \ TWI General Call Recognition Enable Bit
+\ USART1
+&206 constant UDR1 \ USART I/O Data Register
+&200 constant UCSR1A \ USART Control and Status Register A
+ $80 constant UCSR1A_RXC1 \ USART Receive Complete
+ $40 constant UCSR1A_TXC1 \ USART Transmitt Complete
+ $20 constant UCSR1A_UDRE1 \ USART Data Register Empty
+ $10 constant UCSR1A_FE1 \ Framing Error
+ $08 constant UCSR1A_DOR1 \ Data overRun
+ $04 constant UCSR1A_UPE1 \ Parity Error
+ $02 constant UCSR1A_U2X1 \ Double the USART transmission speed
+ $01 constant UCSR1A_MPCM1 \ Multi-processor Communication Mode
+&201 constant UCSR1B \ USART Control and Status Register B
+ $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable
+ $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable
+ $20 constant UCSR1B_UDRIE1 \ USART Data register Empty Interrupt Enable
+ $10 constant UCSR1B_RXEN1 \ Receiver Enable
+ $08 constant UCSR1B_TXEN1 \ Transmitter Enable
+ $04 constant UCSR1B_UCSZ12 \ Character Size
+ $02 constant UCSR1B_RXB81 \ Receive Data Bit 8
+ $01 constant UCSR1B_TXB81 \ Transmit Data Bit 8
+&202 constant UCSR1C \ USART Control and Status Register C
+ $C0 constant UCSR1C_UMSEL1 \ USART Mode Select
+ $30 constant UCSR1C_UPM1 \ Parity Mode Bits
+ $08 constant UCSR1C_USBS1 \ Stop Bit Select
+ $06 constant UCSR1C_UCSZ1 \ Character Size
+ $01 constant UCSR1C_UCPOL1 \ Clock Polarity
+&204 constant UBRR1 \ USART Baud Rate Register Bytes
+\ CPU
+&95 constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ $08 constant SREG_V \ Two's Complement Overflow Flag
+ $04 constant SREG_N \ Negative Flag
+ $02 constant SREG_Z \ Zero Flag
+ $01 constant SREG_C \ Carry Flag
+&93 constant SP \ Stack Pointer
+&102 constant OSCCAL \ Oscillator Calibration Value
+&97 constant CLKPR \
+ $80 constant CLKPR_CLKPCE \
+ $0F constant CLKPR_CLKPS \
+&83 constant SMCR \ Sleep Mode Control Register
+ $0E constant SMCR_SM \ Sleep Mode Select bits
+ $01 constant SMCR_SE \ Sleep Enable
+&75 constant GPIOR2 \ General Purpose IO Register 2
+ $FF constant GPIOR2_GPIOR \ General Purpose IO Register 2 bis
+&74 constant GPIOR1 \ General Purpose IO Register 1
+ $FF constant GPIOR1_GPIOR \ General Purpose IO Register 1 bis
+&62 constant GPIOR0 \ General Purpose IO Register 0
+ $80 constant GPIOR0_GPIOR07 \ General Purpose IO Register 0 bit 7
+ $40 constant GPIOR0_GPIOR06 \ General Purpose IO Register 0 bit 6
+ $20 constant GPIOR0_GPIOR05 \ General Purpose IO Register 0 bit 5
+ $10 constant GPIOR0_GPIOR04 \ General Purpose IO Register 0 bit 4
+ $08 constant GPIOR0_GPIOR03 \ General Purpose IO Register 0 bit 3
+ $04 constant GPIOR0_GPIOR02 \ General Purpose IO Register 0 bit 2
+ $02 constant GPIOR0_GPIOR01 \ General Purpose IO Register 0 bit 1
+ $01 constant GPIOR0_GPIOR00 \ General Purpose IO Register 0 bit 0
+&100 constant PRR0 \ Power Reduction Register0
+ $80 constant PRR0_PRTWI \ Power Reduction TWI
+ $40 constant PRR0_PRTIM2 \ Power Reduction Timer/Counter2
+ $20 constant PRR0_PRTIM0 \ Power Reduction Timer/Counter0
+ $12 constant PRR0_PRUSART \ Power Reduction USARTs
+ $08 constant PRR0_PRTIM1 \ Power Reduction Timer/Counter1
+ $04 constant PRR0_PRSPI \ Power Reduction Serial Peripheral Interface
+ $01 constant PRR0_PRADC \ Power Reduction ADC
+
+\ Interrupts
+&2 constant INT0Addr \ External Interrupt Request 0
+&4 constant INT1Addr \ External Interrupt Request 1
+&6 constant INT2Addr \ External Interrupt Request 2
+&8 constant PCINT0Addr \ Pin Change Interrupt Request 0
+&10 constant PCINT1Addr \ Pin Change Interrupt Request 1
+&12 constant PCINT2Addr \ Pin Change Interrupt Request 2
+&14 constant PCINT3Addr \ Pin Change Interrupt Request 3
+&16 constant WDTAddr \ Watchdog Time-out Interrupt
+&18 constant TIMER2_COMPAAddr \ Timer/Counter2 Compare Match A
+&20 constant TIMER2_COMPBAddr \ Timer/Counter2 Compare Match B
+&22 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
+&24 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+&26 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
+&28 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
+&30 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+&32 constant TIMER0_COMPAAddr \ Timer/Counter0 Compare Match A
+&34 constant TIMER0_COMPBAddr \ Timer/Counter0 Compare Match B
+&36 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
+&38 constant SPI__STCAddr \ SPI Serial Transfer Complete
+&40 constant USART0__RXAddr \ USART0, Rx Complete
+&42 constant USART0__UDREAddr \ USART0 Data register Empty
+&44 constant USART0__TXAddr \ USART0, Tx Complete
+&46 constant ANALOG_COMPAddr \ Analog Comparator
+&48 constant ADCAddr \ ADC Conversion Complete
+&50 constant EE_READYAddr \ EEPROM Ready
+&52 constant TWIAddr \ 2-wire Serial Interface
+&54 constant SPM_READYAddr \ Store Program Memory Read
+&56 constant USART1_RXAddr \ USART1 RX complete
+&58 constant USART1_UDREAddr \ USART1 Data Register Empty
+&60 constant USART1_TXAddr \ USART1 TX complete
diff --git a/amforth-6.5/avr8/devices/atmega324p/device.asm b/amforth-6.5/avr8/devices/atmega324p/device.asm
new file mode 100644
index 0000000..09eee51
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega324p/device.asm
@@ -0,0 +1,120 @@
+; Partname: ATmega324P
+; generated automatically, do not edit
+
+.nolist
+ .include "m324Pdef.inc"
+.list
+
+.equ ramstart = 256
+.equ CELLSIZE = 2
+.macro readflashcell
+ lsl zl
+ rol zh
+ lpm @0, Z+
+ lpm @1, Z+
+.endmacro
+.macro writeflashcell
+ lsl zl
+ rol zh
+.endmacro
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_USART0 = 0
+.set WANT_PORTA = 0
+.set WANT_PORTB = 0
+.set WANT_PORTC = 0
+.set WANT_PORTD = 0
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_TIMER_COUNTER_2 = 0
+.set WANT_WATCHDOG = 0
+.set WANT_JTAG = 0
+.set WANT_BOOT_LOAD = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_AD_CONVERTER = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_EEPROM = 0
+.set WANT_SPI = 0
+.set WANT_TWI = 0
+.set WANT_USART1 = 0
+.set WANT_CPU = 0
+.equ intvecsize = 2 ; please verify; flash size: 32768 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.org 2
+ rcall isr ; External Interrupt Request 0
+.org 4
+ rcall isr ; External Interrupt Request 1
+.org 6
+ rcall isr ; External Interrupt Request 2
+.org 8
+ rcall isr ; Pin Change Interrupt Request 0
+.org 10
+ rcall isr ; Pin Change Interrupt Request 1
+.org 12
+ rcall isr ; Pin Change Interrupt Request 2
+.org 14
+ rcall isr ; Pin Change Interrupt Request 3
+.org 16
+ rcall isr ; Watchdog Time-out Interrupt
+.org 18
+ rcall isr ; Timer/Counter2 Compare Match A
+.org 20
+ rcall isr ; Timer/Counter2 Compare Match B
+.org 22
+ rcall isr ; Timer/Counter2 Overflow
+.org 24
+ rcall isr ; Timer/Counter1 Capture Event
+.org 26
+ rcall isr ; Timer/Counter1 Compare Match A
+.org 28
+ rcall isr ; Timer/Counter1 Compare Match B
+.org 30
+ rcall isr ; Timer/Counter1 Overflow
+.org 32
+ rcall isr ; Timer/Counter0 Compare Match A
+.org 34
+ rcall isr ; Timer/Counter0 Compare Match B
+.org 36
+ rcall isr ; Timer/Counter0 Overflow
+.org 38
+ rcall isr ; SPI Serial Transfer Complete
+.org 40
+ rcall isr ; USART0, Rx Complete
+.org 42
+ rcall isr ; USART0 Data register Empty
+.org 44
+ rcall isr ; USART0, Tx Complete
+.org 46
+ rcall isr ; Analog Comparator
+.org 48
+ rcall isr ; ADC Conversion Complete
+.org 50
+ rcall isr ; EEPROM Ready
+.org 52
+ rcall isr ; 2-wire Serial Interface
+.org 54
+ rcall isr ; Store Program Memory Read
+.org 56
+ rcall isr ; USART1 RX complete
+.org 58
+ rcall isr ; USART1 Data Register Empty
+.org 60
+ rcall isr ; USART1 TX complete
+.equ INTVECTORS = 31
+.nooverlap
+
+; compatability layer (maybe empty)
+
+; controller data area, environment query mcu-info
+mcu_info:
+mcu_ramsize:
+ .dw 2048
+mcu_eepromsize:
+ .dw 1024
+mcu_maxdp:
+ .dw 28672
+mcu_numints:
+ .dw 31
+mcu_name:
+ .dw 10
+ .db "ATmega324P"
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega324p/device.inc b/amforth-6.5/avr8/devices/atmega324p/device.inc
new file mode 100644
index 0000000..15f90e9
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega324p/device.inc
@@ -0,0 +1,1128 @@
+; Partname: ATmega324P
+; generated automatically, no not edit
+
+.if WANT_ANALOG_COMPARATOR == 1
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Control and Status Register B
+VE_ADCSRB:
+ .dw $ff06
+ .db "ADCSRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRB
+XT_ADCSRB:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRB:
+ .dw 123
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Control And Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw 80
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 1
+VE_DIDR1:
+ .dw $ff05
+ .db "DIDR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR1
+XT_DIDR1:
+ .dw PFA_DOVARIABLE
+PFA_DIDR1:
+ .dw 127
+
+.endif
+.if WANT_USART0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR0:
+ .dw $ff04
+ .db "UDR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR0
+XT_UDR0:
+ .dw PFA_DOVARIABLE
+PFA_UDR0:
+ .dw 198
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR0A:
+ .dw $ff06
+ .db "UCSR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0A
+XT_UCSR0A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0A:
+ .dw 192
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR0B:
+ .dw $ff06
+ .db "UCSR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0B
+XT_UCSR0B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0B:
+ .dw 193
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR0C:
+ .dw $ff06
+ .db "UCSR0C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0C
+XT_UCSR0C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0C:
+ .dw 194
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Bytes
+VE_UBRR0:
+ .dw $ff05
+ .db "UBRR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR0
+XT_UBRR0:
+ .dw PFA_DOVARIABLE
+PFA_UBRR0:
+ .dw 196
+
+.endif
+.if WANT_PORTA == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Register
+VE_PORTA:
+ .dw $ff05
+ .db "PORTA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTA
+XT_PORTA:
+ .dw PFA_DOVARIABLE
+PFA_PORTA:
+ .dw 34
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Direction Register
+VE_DDRA:
+ .dw $ff04
+ .db "DDRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRA
+XT_DDRA:
+ .dw PFA_DOVARIABLE
+PFA_DDRA:
+ .dw 33
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Input Pins
+VE_PINA:
+ .dw $ff04
+ .db "PINA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINA
+XT_PINA:
+ .dw PFA_DOVARIABLE
+PFA_PINA:
+ .dw 32
+
+.endif
+.if WANT_PORTB == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw 37
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw 36
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw 35
+
+.endif
+.if WANT_PORTC == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Register
+VE_PORTC:
+ .dw $ff05
+ .db "PORTC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTC
+XT_PORTC:
+ .dw PFA_DOVARIABLE
+PFA_PORTC:
+ .dw 40
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Direction Register
+VE_DDRC:
+ .dw $ff04
+ .db "DDRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRC
+XT_DDRC:
+ .dw PFA_DOVARIABLE
+PFA_DDRC:
+ .dw 39
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Input Pins
+VE_PINC:
+ .dw $ff04
+ .db "PINC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINC
+XT_PINC:
+ .dw PFA_DOVARIABLE
+PFA_PINC:
+ .dw 38
+
+.endif
+.if WANT_PORTD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw 43
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw 42
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw 41
+
+.endif
+.if WANT_TIMER_COUNTER_0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0B:
+ .dw $ff05
+ .db "OCR0B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0B
+XT_OCR0B:
+ .dw PFA_DOVARIABLE
+PFA_OCR0B:
+ .dw 72
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0A:
+ .dw $ff05
+ .db "OCR0A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0A
+XT_OCR0A:
+ .dw PFA_DOVARIABLE
+PFA_OCR0A:
+ .dw 71
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw 70
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register B
+VE_TCCR0B:
+ .dw $ff06
+ .db "TCCR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0B
+XT_TCCR0B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0B:
+ .dw 69
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register A
+VE_TCCR0A:
+ .dw $ff06
+ .db "TCCR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0A
+XT_TCCR0A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0A:
+ .dw 68
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Mask Register
+VE_TIMSK0:
+ .dw $ff06
+ .db "TIMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK0
+XT_TIMSK0:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK0:
+ .dw 110
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Flag register
+VE_TIFR0:
+ .dw $ff05
+ .db "TIFR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR0
+XT_TIFR0:
+ .dw PFA_DOVARIABLE
+PFA_TIFR0:
+ .dw 53
+; ( -- addr ) System Constant
+; R( -- )
+; General Timer/Counter Control Register
+VE_GTCCR:
+ .dw $ff05
+ .db "GTCCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GTCCR
+XT_GTCCR:
+ .dw PFA_DOVARIABLE
+PFA_GTCCR:
+ .dw 67
+
+.endif
+.if WANT_TIMER_COUNTER_2 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Mask register
+VE_TIMSK2:
+ .dw $ff06
+ .db "TIMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK2
+XT_TIMSK2:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK2:
+ .dw 112
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Flag Register
+VE_TIFR2:
+ .dw $ff05
+ .db "TIFR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR2
+XT_TIFR2:
+ .dw PFA_DOVARIABLE
+PFA_TIFR2:
+ .dw 55
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register A
+VE_TCCR2A:
+ .dw $ff06
+ .db "TCCR2A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2A
+XT_TCCR2A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2A:
+ .dw 176
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register B
+VE_TCCR2B:
+ .dw $ff06
+ .db "TCCR2B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2B
+XT_TCCR2B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2B:
+ .dw 177
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2
+VE_TCNT2:
+ .dw $ff05
+ .db "TCNT2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT2
+XT_TCNT2:
+ .dw PFA_DOVARIABLE
+PFA_TCNT2:
+ .dw 178
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register B
+VE_OCR2B:
+ .dw $ff05
+ .db "OCR2B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2B
+XT_OCR2B:
+ .dw PFA_DOVARIABLE
+PFA_OCR2B:
+ .dw 180
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register A
+VE_OCR2A:
+ .dw $ff05
+ .db "OCR2A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2A
+XT_OCR2A:
+ .dw PFA_DOVARIABLE
+PFA_OCR2A:
+ .dw 179
+; ( -- addr ) System Constant
+; R( -- )
+; Asynchronous Status Register
+VE_ASSR:
+ .dw $ff04
+ .db "ASSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ASSR
+XT_ASSR:
+ .dw PFA_DOVARIABLE
+PFA_ASSR:
+ .dw 182
+
+.endif
+.if WANT_WATCHDOG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCSR:
+ .dw $ff06
+ .db "WDTCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCSR
+XT_WDTCSR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCSR:
+ .dw 96
+
+.endif
+.if WANT_JTAG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; On-Chip Debug Related Register in I/O Memory
+VE_OCDR:
+ .dw $ff04
+ .db "OCDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCDR
+XT_OCDR:
+ .dw PFA_DOVARIABLE
+PFA_OCDR:
+ .dw 81
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw 85
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Status Register
+VE_MCUSR:
+ .dw $ff05
+ .db "MCUSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUSR
+XT_MCUSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUSR:
+ .dw 84
+
+.endif
+.if WANT_BOOT_LOAD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control Register
+VE_SPMCSR:
+ .dw $ff06
+ .db "SPMCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCSR
+XT_SPMCSR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCSR:
+ .dw 87
+
+.endif
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register A
+VE_EICRA:
+ .dw $ff05
+ .db "EICRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRA
+XT_EICRA:
+ .dw PFA_DOVARIABLE
+PFA_EICRA:
+ .dw 105
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Mask Register
+VE_EIMSK:
+ .dw $ff05
+ .db "EIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIMSK
+XT_EIMSK:
+ .dw PFA_DOVARIABLE
+PFA_EIMSK:
+ .dw 61
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Flag Register
+VE_EIFR:
+ .dw $ff04
+ .db "EIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIFR
+XT_EIFR:
+ .dw PFA_DOVARIABLE
+PFA_EIFR:
+ .dw 60
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 3
+VE_PCMSK3:
+ .dw $ff06
+ .db "PCMSK3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK3
+XT_PCMSK3:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK3:
+ .dw 115
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 2
+VE_PCMSK2:
+ .dw $ff06
+ .db "PCMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK2
+XT_PCMSK2:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK2:
+ .dw 109
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 1
+VE_PCMSK1:
+ .dw $ff06
+ .db "PCMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK1
+XT_PCMSK1:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK1:
+ .dw 108
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 0
+VE_PCMSK0:
+ .dw $ff06
+ .db "PCMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK0
+XT_PCMSK0:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK0:
+ .dw 107
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Interrupt Flag Register
+VE_PCIFR:
+ .dw $ff05
+ .db "PCIFR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCIFR
+XT_PCIFR:
+ .dw PFA_DOVARIABLE
+PFA_PCIFR:
+ .dw 59
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Interrupt Control Register
+VE_PCICR:
+ .dw $ff05
+ .db "PCICR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCICR
+XT_PCICR:
+ .dw PFA_DOVARIABLE
+PFA_PCICR:
+ .dw 104
+
+.endif
+.if WANT_AD_CONVERTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC multiplexer Selection Register
+VE_ADMUX:
+ .dw $ff05
+ .db "ADMUX",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADMUX
+XT_ADMUX:
+ .dw PFA_DOVARIABLE
+PFA_ADMUX:
+ .dw 124
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register Bytes
+VE_ADC:
+ .dw $ff03
+ .db "ADC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADC
+XT_ADC:
+ .dw PFA_DOVARIABLE
+PFA_ADC:
+ .dw 120
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register A
+VE_ADCSRA:
+ .dw $ff06
+ .db "ADCSRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRA
+XT_ADCSRA:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRA:
+ .dw 122
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register
+VE_DIDR0:
+ .dw $ff05
+ .db "DIDR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR0
+XT_DIDR0:
+ .dw PFA_DOVARIABLE
+PFA_DIDR0:
+ .dw 126
+
+.endif
+.if WANT_TIMER_COUNTER_1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Mask Register
+VE_TIMSK1:
+ .dw $ff06
+ .db "TIMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK1
+XT_TIMSK1:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK1:
+ .dw 111
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Flag register
+VE_TIFR1:
+ .dw $ff05
+ .db "TIFR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR1
+XT_TIFR1:
+ .dw PFA_DOVARIABLE
+PFA_TIFR1:
+ .dw 54
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw 128
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw 129
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register C
+VE_TCCR1C:
+ .dw $ff06
+ .db "TCCR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1C
+XT_TCCR1C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1C:
+ .dw 130
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Bytes
+VE_TCNT1:
+ .dw $ff05
+ .db "TCNT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1
+XT_TCNT1:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1:
+ .dw 132
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register A Bytes
+VE_OCR1A:
+ .dw $ff05
+ .db "OCR1A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1A
+XT_OCR1A:
+ .dw PFA_DOVARIABLE
+PFA_OCR1A:
+ .dw 136
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register B Bytes
+VE_OCR1B:
+ .dw $ff05
+ .db "OCR1B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1B
+XT_OCR1B:
+ .dw PFA_DOVARIABLE
+PFA_OCR1B:
+ .dw 138
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Bytes
+VE_ICR1:
+ .dw $ff04
+ .db "ICR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1
+XT_ICR1:
+ .dw PFA_DOVARIABLE
+PFA_ICR1:
+ .dw 134
+
+.endif
+.if WANT_EEPROM == 1
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Address Register Low Bytes
+VE_EEAR:
+ .dw $ff04
+ .db "EEAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEAR
+XT_EEAR:
+ .dw PFA_DOVARIABLE
+PFA_EEAR:
+ .dw 65
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw 64
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw 63
+
+.endif
+.if WANT_SPI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR0:
+ .dw $ff05
+ .db "SPDR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR0
+XT_SPDR0:
+ .dw PFA_DOVARIABLE
+PFA_SPDR0:
+ .dw 78
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR0:
+ .dw $ff05
+ .db "SPSR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR0
+XT_SPSR0:
+ .dw PFA_DOVARIABLE
+PFA_SPSR0:
+ .dw 77
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR0:
+ .dw $ff05
+ .db "SPCR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR0
+XT_SPCR0:
+ .dw PFA_DOVARIABLE
+PFA_SPCR0:
+ .dw 76
+
+.endif
+.if WANT_TWI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; TWI (Slave) Address Mask Register
+VE_TWAMR:
+ .dw $ff05
+ .db "TWAMR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWAMR
+XT_TWAMR:
+ .dw PFA_DOVARIABLE
+PFA_TWAMR:
+ .dw 189
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Bit Rate register
+VE_TWBR:
+ .dw $ff04
+ .db "TWBR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWBR
+XT_TWBR:
+ .dw PFA_DOVARIABLE
+PFA_TWBR:
+ .dw 184
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Control Register
+VE_TWCR:
+ .dw $ff04
+ .db "TWCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWCR
+XT_TWCR:
+ .dw PFA_DOVARIABLE
+PFA_TWCR:
+ .dw 188
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Status Register
+VE_TWSR:
+ .dw $ff04
+ .db "TWSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWSR
+XT_TWSR:
+ .dw PFA_DOVARIABLE
+PFA_TWSR:
+ .dw 185
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Data register
+VE_TWDR:
+ .dw $ff04
+ .db "TWDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWDR
+XT_TWDR:
+ .dw PFA_DOVARIABLE
+PFA_TWDR:
+ .dw 187
+; ( -- addr ) System Constant
+; R( -- )
+; TWI (Slave) Address register
+VE_TWAR:
+ .dw $ff04
+ .db "TWAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWAR
+XT_TWAR:
+ .dw PFA_DOVARIABLE
+PFA_TWAR:
+ .dw 186
+
+.endif
+.if WANT_USART1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR1:
+ .dw $ff04
+ .db "UDR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR1
+XT_UDR1:
+ .dw PFA_DOVARIABLE
+PFA_UDR1:
+ .dw 206
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR1A:
+ .dw $ff06
+ .db "UCSR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1A
+XT_UCSR1A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1A:
+ .dw 200
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR1B:
+ .dw $ff06
+ .db "UCSR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1B
+XT_UCSR1B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1B:
+ .dw 201
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR1C:
+ .dw $ff06
+ .db "UCSR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1C
+XT_UCSR1C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1C:
+ .dw 202
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Bytes
+VE_UBRR1:
+ .dw $ff05
+ .db "UBRR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR1
+XT_UBRR1:
+ .dw PFA_DOVARIABLE
+PFA_UBRR1:
+ .dw 204
+
+.endif
+.if WANT_CPU == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw 95
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer
+VE_SP:
+ .dw $ff02
+ .db "SP"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SP
+XT_SP:
+ .dw PFA_DOVARIABLE
+PFA_SP:
+ .dw 93
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Calibration Value
+VE_OSCCAL:
+ .dw $ff06
+ .db "OSCCAL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSCCAL
+XT_OSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_OSCCAL:
+ .dw 102
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_CLKPR:
+ .dw $ff05
+ .db "CLKPR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKPR
+XT_CLKPR:
+ .dw PFA_DOVARIABLE
+PFA_CLKPR:
+ .dw 97
+; ( -- addr ) System Constant
+; R( -- )
+; Sleep Mode Control Register
+VE_SMCR:
+ .dw $ff04
+ .db "SMCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SMCR
+XT_SMCR:
+ .dw PFA_DOVARIABLE
+PFA_SMCR:
+ .dw 83
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 2
+VE_GPIOR2:
+ .dw $ff06
+ .db "GPIOR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR2
+XT_GPIOR2:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR2:
+ .dw 75
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 1
+VE_GPIOR1:
+ .dw $ff06
+ .db "GPIOR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR1
+XT_GPIOR1:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR1:
+ .dw 74
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 0
+VE_GPIOR0:
+ .dw $ff06
+ .db "GPIOR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR0
+XT_GPIOR0:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR0:
+ .dw 62
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register0
+VE_PRR0:
+ .dw $ff04
+ .db "PRR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR0
+XT_PRR0:
+ .dw PFA_DOVARIABLE
+PFA_PRR0:
+ .dw 100
+
+.endif
diff --git a/amforth-6.5/avr8/devices/atmega324p/device.py b/amforth-6.5/avr8/devices/atmega324p/device.py
new file mode 100644
index 0000000..6cdc7eb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega324p/device.py
@@ -0,0 +1,390 @@
+# Generated Automatically
+
+# Partname ATmega324P
+
+MCUREGS = {
+# Interrupt Vectors
+ 'INT0Addr' : '#2', # External Interrupt Request 0
+ 'INT1Addr' : '#4', # External Interrupt Request 1
+ 'INT2Addr' : '#6', # External Interrupt Request 2
+ 'PCINT0Addr' : '#8', # Pin Change Interrupt Request 0
+ 'PCINT1Addr' : '#10', # Pin Change Interrupt Request 1
+ 'PCINT2Addr' : '#12', # Pin Change Interrupt Request 2
+ 'PCINT3Addr' : '#14', # Pin Change Interrupt Request 3
+ 'WDTAddr' : '#16', # Watchdog Time-out Interrupt
+ 'TIMER2_COMPAAddr' : '#18', # Timer/Counter2 Compare Match A
+ 'TIMER2_COMPBAddr' : '#20', # Timer/Counter2 Compare Match B
+ 'TIMER2_OVFAddr' : '#22', # Timer/Counter2 Overflow
+ 'TIMER1_CAPTAddr' : '#24', # Timer/Counter1 Capture Event
+ 'TIMER1_COMPAAddr' : '#26', # Timer/Counter1 Compare Match A
+ 'TIMER1_COMPBAddr' : '#28', # Timer/Counter1 Compare Match B
+ 'TIMER1_OVFAddr' : '#30', # Timer/Counter1 Overflow
+ 'TIMER0_COMPAAddr' : '#32', # Timer/Counter0 Compare Match A
+ 'TIMER0_COMPBAddr' : '#34', # Timer/Counter0 Compare Match B
+ 'TIMER0_OVFAddr' : '#36', # Timer/Counter0 Overflow
+ 'SPI_STCAddr' : '#38', # SPI Serial Transfer Complete
+ 'USART0_RXAddr' : '#40', # USART0, Rx Complete
+ 'USART0_UDREAddr' : '#42', # USART0 Data register Empty
+ 'USART0_TXAddr' : '#44', # USART0, Tx Complete
+ 'ANALOG_COMPAddr' : '#46', # Analog Comparator
+ 'ADCAddr' : '#48', # ADC Conversion Complete
+ 'EE_READYAddr' : '#50', # EEPROM Ready
+ 'TWIAddr' : '#52', # 2-wire Serial Interface
+ 'SPM_READYAddr' : '#54', # Store Program Memory Read
+ 'USART1_RXAddr' : '#56', # USART1 RX complete
+ 'USART1_UDREAddr' : '#58', # USART1 Data Register Empty
+ 'USART1_TXAddr' : '#60', # USART1 TX complete
+
+# Module ANALOG_COMPARATOR
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
+ 'ACSR' : '$50', # Analog Comparator Control And
+ 'ACSR_ACD': '$80', # Analog Comparator Disable
+ 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
+ 'ACSR_ACO': '$20', # Analog Compare Output
+ 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
+ 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
+ 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
+ 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
+ 'DIDR1' : '$7f', # Digital Input Disable Register
+ 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
+ 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
+
+# Module USART0
+ 'UDR0' : '$c6', # USART I/O Data Register
+ 'UCSR0A' : '$c0', # USART Control and Status Regis
+ 'UCSR0A_RXC0': '$80', # USART Receive Complete
+ 'UCSR0A_TXC0': '$40', # USART Transmitt Complete
+ 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
+ 'UCSR0A_FE0': '$10', # Framing Error
+ 'UCSR0A_DOR0': '$8', # Data overRun
+ 'UCSR0A_UPE0': '$4', # Parity Error
+ 'UCSR0A_U2X0': '$2', # Double the USART transmission
+ 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
+ 'UCSR0B' : '$c1', # USART Control and Status Regis
+ 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
+ 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
+ 'UCSR0B_UDRIE0': '$20', # USART Data register Empty Inte
+ 'UCSR0B_RXEN0': '$10', # Receiver Enable
+ 'UCSR0B_TXEN0': '$8', # Transmitter Enable
+ 'UCSR0B_UCSZ02': '$4', # Character Size
+ 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
+ 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
+ 'UCSR0C' : '$c2', # USART Control and Status Regis
+ 'UCSR0C_UMSEL0': '$c0', # USART Mode Select
+ 'UCSR0C_UPM0': '$30', # Parity Mode Bits
+ 'UCSR0C_USBS0': '$8', # Stop Bit Select
+ 'UCSR0C_UCSZ0': '$6', # Character Size
+ 'UCSR0C_UCPOL0': '$1', # Clock Polarity
+ 'UBRR0' : '$c4', # USART Baud Rate Register Byte
+
+# Module PORTA
+ 'PORTA' : '$22', # Port A Data Register
+ 'DDRA' : '$21', # Port A Data Direction Register
+ 'PINA' : '$20', # Port A Input Pins
+
+# Module PORTB
+ 'PORTB' : '$25', # Port B Data Register
+ 'DDRB' : '$24', # Port B Data Direction Register
+ 'PINB' : '$23', # Port B Input Pins
+
+# Module PORTC
+ 'PORTC' : '$28', # Port C Data Register
+ 'DDRC' : '$27', # Port C Data Direction Register
+ 'PINC' : '$26', # Port C Input Pins
+
+# Module PORTD
+ 'PORTD' : '$2b', # Port D Data Register
+ 'DDRD' : '$2a', # Port D Data Direction Register
+ 'PIND' : '$29', # Port D Input Pins
+
+# Module TIMER_COUNTER_0
+ 'OCR0B' : '$48', # Timer/Counter0 Output Compare
+ 'OCR0A' : '$47', # Timer/Counter0 Output Compare
+ 'TCNT0' : '$46', # Timer/Counter0
+ 'TCCR0B' : '$45', # Timer/Counter Control Register
+ 'TCCR0B_FOC0A': '$80', # Force Output Compare A
+ 'TCCR0B_FOC0B': '$40', # Force Output Compare B
+ 'TCCR0B_WGM02': '$8', #
+ 'TCCR0B_CS0': '$7', # Clock Select
+ 'TCCR0A' : '$44', # Timer/Counter Control Registe
+ 'TCCR0A_COM0A': '$c0', # Compare Output Mode, Phase Cor
+ 'TCCR0A_COM0B': '$30', # Compare Output Mode, Fast PWm
+ 'TCCR0A_WGM0': '$3', # Waveform Generation Mode
+ 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
+ 'TIMSK0_OCIE0B': '$4', # Timer/Counter0 Output Compare
+ 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
+ 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
+ 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
+ 'TIFR0_OCF0B': '$4', # Timer/Counter0 Output Compare
+ 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
+ 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSRSYNC': '$1', # Prescaler Reset Timer/Counter1
+
+# Module TIMER_COUNTER_2
+ 'TIMSK2' : '$70', # Timer/Counter Interrupt Mask r
+ 'TIMSK2_OCIE2B': '$4', # Timer/Counter2 Output Compare
+ 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
+ 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
+ 'TIFR2' : '$37', # Timer/Counter Interrupt Flag R
+ 'TIFR2_OCF2B': '$4', # Output Compare Flag 2B
+ 'TIFR2_OCF2A': '$2', # Output Compare Flag 2A
+ 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
+ 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
+ 'TCCR2A_COM2A': '$c0', # Compare Output Mode bits
+ 'TCCR2A_COM2B': '$30', # Compare Output Mode bits
+ 'TCCR2A_WGM2': '$3', # Waveform Genration Mode
+ 'TCCR2B' : '$b1', # Timer/Counter2 Control Registe
+ 'TCCR2B_FOC2A': '$80', # Force Output Compare A
+ 'TCCR2B_FOC2B': '$40', # Force Output Compare B
+ 'TCCR2B_WGM22': '$8', # Waveform Generation Mode
+ 'TCCR2B_CS2': '$7', # Clock Select bits
+ 'TCNT2' : '$b2', # Timer/Counter2
+ 'OCR2B' : '$b4', # Timer/Counter2 Output Compare
+ 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
+ 'ASSR' : '$b6', # Asynchronous Status Register
+ 'ASSR_EXCLK': '$40', # Enable External Clock Input
+ 'ASSR_AS2': '$20', # Asynchronous Timer/Counter2
+ 'ASSR_TCN2UB': '$10', # Timer/Counter2 Update Busy
+ 'ASSR_OCR2AUB': '$8', # Output Compare Register2 Updat
+ 'ASSR_OCR2BUB': '$4', # Output Compare Register 2 Upda
+ 'ASSR_TCR2AUB': '$2', # Timer/Counter Control Register
+ 'ASSR_TCR2BUB': '$1', # Timer/Counter Control Register
+ 'GTCCR' : '$43', # General Timer Counter Control
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSRASY': '$2', # Prescaler Reset Timer/Counter2
+
+# Module WATCHDOG
+ 'WDTCSR' : '$60', # Watchdog Timer Control Registe
+ 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
+ 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
+ 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
+ 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
+ 'WDTCSR_WDE': '$8', # Watch Dog Enable
+
+# Module JTAG
+ 'OCDR' : '$51', # On-Chip Debug Related Register
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_JTD': '$80', # JTAG Interface Disable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+
+# Module BOOT_LOAD
+ 'SPMCSR' : '$57', # Store Program Memory Control R
+ 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
+ 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
+ 'SPMCSR_SIGRD': '$20', # Signature Row Read
+ 'SPMCSR_RWWSRE': '$10', # Read While Write section read
+ 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
+ 'SPMCSR_PGWRT': '$4', # Page Write
+ 'SPMCSR_PGERS': '$2', # Page Erase
+ 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
+
+# Module EXTERNAL_INTERRUPT
+ 'EICRA' : '$69', # External Interrupt Control Reg
+ 'EICRA_ISC2': '$30', # External Interrupt Sense Contr
+ 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
+ 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
+ 'EIMSK' : '$3d', # External Interrupt Mask Regist
+ 'EIMSK_INT': '$7', # External Interrupt Request 2 E
+ 'EIFR' : '$3c', # External Interrupt Flag Regist
+ 'EIFR_INTF': '$7', # External Interrupt Flags
+ 'PCMSK3' : '$73', # Pin Change Mask Register 3
+ 'PCMSK3_PCINT': '$ff', # Pin Change Enable Masks
+ 'PCMSK2' : '$6d', # Pin Change Mask Register 2
+ 'PCMSK2_PCINT': '$ff', # Pin Change Enable Masks
+ 'PCMSK1' : '$6c', # Pin Change Mask Register 1
+ 'PCMSK1_PCINT': '$ff', # Pin Change Enable Masks
+ 'PCMSK0' : '$6b', # Pin Change Mask Register 0
+ 'PCMSK0_PCINT': '$ff', # Pin Change Enable Masks
+ 'PCIFR' : '$3b', # Pin Change Interrupt Flag Regi
+ 'PCIFR_PCIF': '$f', # Pin Change Interrupt Flags
+ 'PCICR' : '$68', # Pin Change Interrupt Control R
+ 'PCICR_PCIE': '$f', # Pin Change Interrupt Enables
+
+# Module AD_CONVERTER
+ 'ADMUX' : '$7c', # The ADC multiplexer Selection
+ 'ADMUX_REFS': '$c0', # Reference Selection Bits
+ 'ADMUX_ADLAR': '$20', # Left Adjust Result
+ 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
+ 'ADC' : '$78', # ADC Data Register Bytes
+ 'ADCSRA' : '$7a', # The ADC Control and Status reg
+ 'ADCSRA_ADEN': '$80', # ADC Enable
+ 'ADCSRA_ADSC': '$40', # ADC Start Conversion
+ 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
+ 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
+ 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
+ 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
+ 'ADCSRB' : '$7b', # The ADC Control and Status reg
+ 'ADCSRB_ACME': '$40', #
+ 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Source bits
+ 'DIDR0' : '$7e', # Digital Input Disable Register
+ 'DIDR0_ADC7D': '$80', #
+ 'DIDR0_ADC6D': '$40', #
+ 'DIDR0_ADC5D': '$20', #
+ 'DIDR0_ADC4D': '$10', #
+ 'DIDR0_ADC3D': '$8', #
+ 'DIDR0_ADC2D': '$4', #
+ 'DIDR0_ADC1D': '$2', #
+ 'DIDR0_ADC0D': '$1', #
+
+# Module TIMER_COUNTER_1
+ 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
+ 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
+ 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
+ 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
+ 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
+ 'TIFR1' : '$36', # Timer/Counter Interrupt Flag r
+ 'TIFR1_ICF1': '$20', # Timer/Counter1 Input Capture F
+ 'TIFR1_OCF1B': '$4', # Timer/Counter1 Output Compare
+ 'TIFR1_OCF1A': '$2', # Timer/Counter1 Output Compare
+ 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
+ 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
+ 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
+ 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
+ 'TCCR1A_WGM1': '$3', # Pulse Width Modulator Select B
+ 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
+ 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
+ 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
+ 'TCCR1B_WGM1': '$18', # Waveform Generation Mode Bits
+ 'TCCR1B_CS1': '$7', # Clock Select1 bits
+ 'TCCR1C' : '$82', # Timer/Counter1 Control Registe
+ 'TCCR1C_FOC1A': '$80', # Force Output Compare for Chann
+ 'TCCR1C_FOC1B': '$40', # Force Output Compare for Chann
+ 'TCNT1' : '$84', # Timer/Counter1 Bytes
+ 'OCR1A' : '$88', # Timer/Counter1 Output Compare
+ 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
+ 'ICR1' : '$86', # Timer/Counter1 Input Capture R
+
+# Module EEPROM
+ 'EEAR' : '$41', # EEPROM Address Register Low By
+ 'EEDR' : '$40', # EEPROM Data Register
+ 'EECR' : '$3f', # EEPROM Control Register
+ 'EECR_EEPM': '$30', # EEPROM Programming Mode Bits
+ 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
+ 'EECR_EEMPE': '$4', # EEPROM Master Write Enable
+ 'EECR_EEPE': '$2', # EEPROM Write Enable
+ 'EECR_EERE': '$1', # EEPROM Read Enable
+
+# Module SPI
+ 'SPDR0' : '$4e', # SPI Data Register
+ 'SPSR0' : '$4d', # SPI Status Register
+ 'SPSR0_SPIF0': '$80', # SPI Interrupt Flag
+ 'SPSR0_WCOL0': '$40', # Write Collision Flag
+ 'SPSR0_SPI2X0': '$1', # Double SPI Speed Bit
+ 'SPCR0' : '$4c', # SPI Control Register
+ 'SPCR0_SPIE0': '$80', # SPI Interrupt Enable
+ 'SPCR0_SPE0': '$40', # SPI Enable
+ 'SPCR0_DORD0': '$20', # Data Order
+ 'SPCR0_MSTR0': '$10', # Master/Slave Select
+ 'SPCR0_CPOL0': '$8', # Clock polarity
+ 'SPCR0_CPHA0': '$4', # Clock Phase
+ 'SPCR0_SPR10': '$2', # SPI Clock Rate Select 1
+ 'SPCR0_SPR00': '$1', # SPI Clock Rate Select 0
+
+# Module TWI
+ 'TWAMR' : '$bd', # TWI (Slave) Address Mask Regis
+ 'TWAMR_TWAM': '$fe', #
+ 'TWBR' : '$b8', # TWI Bit Rate register
+ 'TWCR' : '$bc', # TWI Control Register
+ 'TWCR_TWINT': '$80', # TWI Interrupt Flag
+ 'TWCR_TWEA': '$40', # TWI Enable Acknowledge Bit
+ 'TWCR_TWSTA': '$20', # TWI Start Condition Bit
+ 'TWCR_TWSTO': '$10', # TWI Stop Condition Bit
+ 'TWCR_TWWC': '$8', # TWI Write Collition Flag
+ 'TWCR_TWEN': '$4', # TWI Enable Bit
+ 'TWCR_TWIE': '$1', # TWI Interrupt Enable
+ 'TWSR' : '$b9', # TWI Status Register
+ 'TWSR_TWS': '$f8', # TWI Status
+ 'TWSR_TWPS': '$3', # TWI Prescaler
+ 'TWDR' : '$bb', # TWI Data register
+ 'TWAR' : '$ba', # TWI (Slave) Address register
+ 'TWAR_TWA': '$fe', # TWI (Slave) Address register B
+ 'TWAR_TWGCE': '$1', # TWI General Call Recognition E
+
+# Module USART1
+ 'UDR1' : '$ce', # USART I/O Data Register
+ 'UCSR1A' : '$c8', # USART Control and Status Regis
+ 'UCSR1A_RXC1': '$80', # USART Receive Complete
+ 'UCSR1A_TXC1': '$40', # USART Transmitt Complete
+ 'UCSR1A_UDRE1': '$20', # USART Data Register Empty
+ 'UCSR1A_FE1': '$10', # Framing Error
+ 'UCSR1A_DOR1': '$8', # Data overRun
+ 'UCSR1A_UPE1': '$4', # Parity Error
+ 'UCSR1A_U2X1': '$2', # Double the USART transmission
+ 'UCSR1A_MPCM1': '$1', # Multi-processor Communication
+ 'UCSR1B' : '$c9', # USART Control and Status Regis
+ 'UCSR1B_RXCIE1': '$80', # RX Complete Interrupt Enable
+ 'UCSR1B_TXCIE1': '$40', # TX Complete Interrupt Enable
+ 'UCSR1B_UDRIE1': '$20', # USART Data register Empty Inte
+ 'UCSR1B_RXEN1': '$10', # Receiver Enable
+ 'UCSR1B_TXEN1': '$8', # Transmitter Enable
+ 'UCSR1B_UCSZ12': '$4', # Character Size
+ 'UCSR1B_RXB81': '$2', # Receive Data Bit 8
+ 'UCSR1B_TXB81': '$1', # Transmit Data Bit 8
+ 'UCSR1C' : '$ca', # USART Control and Status Regis
+ 'UCSR1C_UMSEL1': '$c0', # USART Mode Select
+ 'UCSR1C_UPM1': '$30', # Parity Mode Bits
+ 'UCSR1C_USBS1': '$8', # Stop Bit Select
+ 'UCSR1C_UCSZ1': '$6', # Character Size
+ 'UCSR1C_UCPOL1': '$1', # Clock Polarity
+ 'UBRR1' : '$cc', # USART Baud Rate Register Byte
+
+# Module CPU
+ 'SREG' : '$5f', # Status Register
+ 'SREG_I': '$80', # Global Interrupt Enable
+ 'SREG_T': '$40', # Bit Copy Storage
+ 'SREG_H': '$20', # Half Carry Flag
+ 'SREG_S': '$10', # Sign Bit
+ 'SREG_V': '$8', # Two's Complement Overflow Flag
+ 'SREG_N': '$4', # Negative Flag
+ 'SREG_Z': '$2', # Zero Flag
+ 'SREG_C': '$1', # Carry Flag
+ 'SP' : '$5d', # Stack Pointer
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_JTD': '$80', # JTAG Interface Disable
+ 'MCUCR_BODS': '$40', # BOD Power Down in Sleep
+ 'MCUCR_BODSE': '$20', # BOD Power Down in Sleep Enable
+ 'MCUCR_PUD': '$10', # Pull-up disable
+ 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
+ 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+ 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
+ 'MCUSR_BORF': '$4', # Brown-out Reset Flag
+ 'MCUSR_EXTRF': '$2', # External Reset Flag
+ 'MCUSR_PORF': '$1', # Power-on reset flag
+ 'OSCCAL' : '$66', # Oscillator Calibration Value
+ 'CLKPR' : '$61', #
+ 'CLKPR_CLKPCE': '$80', #
+ 'CLKPR_CLKPS': '$f', #
+ 'SMCR' : '$53', # Sleep Mode Control Register
+ 'SMCR_SM': '$e', # Sleep Mode Select bits
+ 'SMCR_SE': '$1', # Sleep Enable
+ 'GPIOR2' : '$4b', # General Purpose IO Register 2
+ 'GPIOR2_GPIOR': '$ff', # General Purpose IO Register 2
+ 'GPIOR1' : '$4a', # General Purpose IO Register 1
+ 'GPIOR1_GPIOR': '$ff', # General Purpose IO Register 1
+ 'GPIOR0' : '$3e', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR07': '$80', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR06': '$40', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR05': '$20', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR04': '$10', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR03': '$8', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR02': '$4', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR01': '$2', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR00': '$1', # General Purpose IO Register 0
+ 'PRR0' : '$64', # Power Reduction Register0
+ 'PRR0_PRTWI': '$80', # Power Reduction TWI
+ 'PRR0_PRTIM2': '$40', # Power Reduction Timer/Counter2
+ 'PRR0_PRTIM0': '$20', # Power Reduction Timer/Counter0
+ 'PRR0_PRUSART1': '$10', # Power Reduction USARTs
+ 'PRR0_PRTIM1': '$8', # Power Reduction Timer/Counter1
+ 'PRR0_PRSPI': '$4', # Power Reduction Serial Periphe
+ 'PRR0_PRUSART0': '$2', # Power Reduction USARTs
+ 'PRR0_PRADC': '$1', # Power Reduction ADC
+
+ '__amforth_dummy':'0'
+}
diff --git a/amforth-6.5/avr8/devices/atmega324p/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega324p/words/no-jtag.asm
new file mode 100644
index 0000000..352a4bb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega324p/words/no-jtag.asm
@@ -0,0 +1,14 @@
+; ( -- )
+; ( -- )
+; MCU
+; disable jtag at runtime
+VE_NOJTAG:
+ .dw $FF05
+ .db "-jtag",0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOJTAG
+XT_NOJTAG:
+ .dw PFA_NOJTAG
+PFA_NOJTAG:
+
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega324p/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega324p/words/no-wdt.asm
new file mode 100644
index 0000000..ff6ddd1
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega324p/words/no-wdt.asm
@@ -0,0 +1,34 @@
+; ( -- )
+; MCU
+; disable watch dog timer at runtime
+VE_NOWDT:
+ .dw $ff04
+ .db "-wdt"
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOWDT
+XT_NOWDT:
+ .dw PFA_NOWDT
+PFA_NOWDT:
+
+ in temp1,SREG
+ push temp1
+ ; Turn always off global interrupt.
+ cli
+ ; Reset Watchdog Timer
+ wdr
+ ; Clear WDRF in MCUSR
+ in temp1, MCUSR
+ andi temp1, (0xff & (0<<WDRF))
+ out MCUSR, temp1
+ ; Write logical one to WDCE and WDE
+ ; Keep old prescaler setting to prevent unintentional time-out
+ in_ temp1, WDTCSR
+ ori temp1, (1<<WDCE) | (1<<WDE)
+ out_ WDTCSR, temp1
+ ; Turn off WDT
+ ldi temp1, (0<<WDE)
+ out_ WDTCSR, temp1
+ ; restore status register
+ pop temp1
+ out SREG,temp1
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega324p/words/sleep.asm b/amforth-6.5/avr8/devices/atmega324p/words/sleep.asm
new file mode 100644
index 0000000..256249c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega324p/words/sleep.asm
@@ -0,0 +1,19 @@
+; ( mode -- )
+; MCU
+; put the controller into the specified sleep mode
+VE_SLEEP:
+ .dw $ff05
+ .db "sleep", 0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_SLEEP
+XT_SLEEP:
+ .dw PFA_SLEEP
+PFA_SLEEP:
+ andi tosl, 7 ; leave only legal mode bits
+ lsl tosl ; move to correct location (bits 3-1)
+ ori tosl, 1 ; set the SE bit
+ out_ SMCR, tosl ; set the sleep config
+ sleep ; nighty-night
+ out_ SMCR, zerol ; 0 protects against accidental sleeps
+ loadtos ; pop argument from stack
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega324pa/atmega324pa.frt b/amforth-6.5/avr8/devices/atmega324pa/atmega324pa.frt
new file mode 100644
index 0000000..db288cd
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega324pa/atmega324pa.frt
@@ -0,0 +1,347 @@
+\ Partname: ATmega324PA
+\ generated automatically
+
+\ ANALOG_COMPARATOR
+&123 constant ADCSRB \ ADC Control and Status Register B
+ $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer Enable
+&80 constant ACSR \ Analog Comparator Control And Status Register
+ $80 constant ACSR_ACD \ Analog Comparator Disable
+ $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
+ $20 constant ACSR_ACO \ Analog Compare Output
+ $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
+ $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
+ $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
+ $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
+&127 constant DIDR1 \ Digital Input Disable Register 1
+ $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
+ $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
+\ USART0
+&198 constant UDR0 \ USART I/O Data Register
+&192 constant UCSR0A \ USART Control and Status Register A
+ $80 constant UCSR0A_RXC0 \ USART Receive Complete
+ $40 constant UCSR0A_TXC0 \ USART Transmitt Complete
+ $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
+ $10 constant UCSR0A_FE0 \ Framing Error
+ $08 constant UCSR0A_DOR0 \ Data overRun
+ $04 constant UCSR0A_UPE0 \ Parity Error
+ $02 constant UCSR0A_U2X0 \ Double the USART transmission speed
+ $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
+&193 constant UCSR0B \ USART Control and Status Register B
+ $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
+ $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
+ $20 constant UCSR0B_UDRIE0 \ USART Data register Empty Interrupt Enable
+ $10 constant UCSR0B_RXEN0 \ Receiver Enable
+ $08 constant UCSR0B_TXEN0 \ Transmitter Enable
+ $04 constant UCSR0B_UCSZ02 \ Character Size
+ $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
+ $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
+&194 constant UCSR0C \ USART Control and Status Register C
+ $C0 constant UCSR0C_UMSEL0 \ USART Mode Select
+ $30 constant UCSR0C_UPM0 \ Parity Mode Bits
+ $08 constant UCSR0C_USBS0 \ Stop Bit Select
+ $06 constant UCSR0C_UCSZ0 \ Character Size
+ $01 constant UCSR0C_UCPOL0 \ Clock Polarity
+&196 constant UBRR0 \ USART Baud Rate Register Bytes
+\ PORTA
+&34 constant PORTA \ Port A Data Register
+&33 constant DDRA \ Port A Data Direction Register
+&32 constant PINA \ Port A Input Pins
+\ PORTB
+&37 constant PORTB \ Port B Data Register
+&36 constant DDRB \ Port B Data Direction Register
+&35 constant PINB \ Port B Input Pins
+\ PORTC
+&40 constant PORTC \ Port C Data Register
+&39 constant DDRC \ Port C Data Direction Register
+&38 constant PINC \ Port C Input Pins
+\ PORTD
+&43 constant PORTD \ Port D Data Register
+&42 constant DDRD \ Port D Data Direction Register
+&41 constant PIND \ Port D Input Pins
+\ TIMER_COUNTER_0
+&72 constant OCR0B \ Timer/Counter0 Output Compare Register
+&71 constant OCR0A \ Timer/Counter0 Output Compare Register
+&70 constant TCNT0 \ Timer/Counter0
+&69 constant TCCR0B \ Timer/Counter Control Register B
+ $80 constant TCCR0B_FOC0A \ Force Output Compare A
+ $40 constant TCCR0B_FOC0B \ Force Output Compare B
+ $08 constant TCCR0B_WGM02 \
+ $07 constant TCCR0B_CS0 \ Clock Select
+&68 constant TCCR0A \ Timer/Counter Control Register A
+ $C0 constant TCCR0A_COM0A \ Compare Output Mode, Phase Correct PWM Mode
+ $30 constant TCCR0A_COM0B \ Compare Output Mode, Fast PWm
+ $03 constant TCCR0A_WGM0 \ Waveform Generation Mode
+&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
+ $04 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare Match B Interrupt Enable
+ $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match A Interrupt Enable
+ $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
+&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
+ $04 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare Flag 0B
+ $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0A
+ $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
+&67 constant GTCCR \ General Timer/Counter Control Register
+ $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
+ $01 constant GTCCR_PSRSYNC \ Prescaler Reset Timer/Counter1 and Timer/Counter0
+\ TIMER_COUNTER_2
+&112 constant TIMSK2 \ Timer/Counter Interrupt Mask register
+ $04 constant TIMSK2_OCIE2B \ Timer/Counter2 Output Compare Match B Interrupt Enable
+ $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match A Interrupt Enable
+ $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
+&55 constant TIFR2 \ Timer/Counter Interrupt Flag Register
+ $04 constant TIFR2_OCF2B \ Output Compare Flag 2B
+ $02 constant TIFR2_OCF2A \ Output Compare Flag 2A
+ $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
+&176 constant TCCR2A \ Timer/Counter2 Control Register A
+ $C0 constant TCCR2A_COM2A \ Compare Output Mode bits
+ $30 constant TCCR2A_COM2B \ Compare Output Mode bits
+ $03 constant TCCR2A_WGM2 \ Waveform Genration Mode
+&177 constant TCCR2B \ Timer/Counter2 Control Register B
+ $80 constant TCCR2B_FOC2A \ Force Output Compare A
+ $40 constant TCCR2B_FOC2B \ Force Output Compare B
+ $08 constant TCCR2B_WGM22 \ Waveform Generation Mode
+ $07 constant TCCR2B_CS2 \ Clock Select bits
+&178 constant TCNT2 \ Timer/Counter2
+&180 constant OCR2B \ Timer/Counter2 Output Compare Register B
+&179 constant OCR2A \ Timer/Counter2 Output Compare Register A
+&182 constant ASSR \ Asynchronous Status Register
+ $40 constant ASSR_EXCLK \ Enable External Clock Input
+ $20 constant ASSR_AS2 \ Asynchronous Timer/Counter2
+ $10 constant ASSR_TCN2UB \ Timer/Counter2 Update Busy
+ $08 constant ASSR_OCR2AUB \ Output Compare Register2 Update Busy
+ $04 constant ASSR_OCR2BUB \ Output Compare Register 2 Update Busy
+ $02 constant ASSR_TCR2AUB \ Timer/Counter Control Register2 Update Busy
+ $01 constant ASSR_TCR2BUB \ Timer/Counter Control Register2 Update Busy
+\ WATCHDOG
+&96 constant WDTCSR \ Watchdog Timer Control Register
+ $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Flag
+ $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Enable
+ $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
+ $10 constant WDTCSR_WDCE \ Watchdog Change Enable
+ $08 constant WDTCSR_WDE \ Watch Dog Enable
+\ JTAG
+&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
+&85 constant MCUCR \ MCU Control Register
+ $80 constant MCUCR_JTD \ JTAG Interface Disable
+&84 constant MCUSR \ MCU Status Register
+ $10 constant MCUSR_JTRF \ JTAG Reset Flag
+\ BOOT_LOAD
+&87 constant SPMCSR \ Store Program Memory Control Register
+ $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
+ $20 constant SPMCSR_SIGRD \ Signature Row Read
+ $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
+ $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
+ $04 constant SPMCSR_PGWRT \ Page Write
+ $02 constant SPMCSR_PGERS \ Page Erase
+ $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
+\ EXTERNAL_INTERRUPT
+&105 constant EICRA \ External Interrupt Control Register A
+ $30 constant EICRA_ISC2 \ External Interrupt Sense Control Bit
+ $0C constant EICRA_ISC1 \ External Interrupt Sense Control Bit
+ $03 constant EICRA_ISC0 \ External Interrupt Sense Control Bit
+&61 constant EIMSK \ External Interrupt Mask Register
+ $07 constant EIMSK_INT \ External Interrupt Request 2 Enable
+&60 constant EIFR \ External Interrupt Flag Register
+ $07 constant EIFR_INTF \ External Interrupt Flags
+&115 constant PCMSK3 \ Pin Change Mask Register 3
+ $FF constant PCMSK3_PCINT \ Pin Change Enable Masks
+&109 constant PCMSK2 \ Pin Change Mask Register 2
+ $FF constant PCMSK2_PCINT \ Pin Change Enable Masks
+&108 constant PCMSK1 \ Pin Change Mask Register 1
+ $FF constant PCMSK1_PCINT \ Pin Change Enable Masks
+&107 constant PCMSK0 \ Pin Change Mask Register 0
+ $FF constant PCMSK0_PCINT \ Pin Change Enable Masks
+&59 constant PCIFR \ Pin Change Interrupt Flag Register
+ $0F constant PCIFR_PCIF \ Pin Change Interrupt Flags
+&104 constant PCICR \ Pin Change Interrupt Control Register
+ $0F constant PCICR_PCIE \ Pin Change Interrupt Enables
+\ AD_CONVERTER
+&124 constant ADMUX \ The ADC multiplexer Selection Register
+ $C0 constant ADMUX_REFS \ Reference Selection Bits
+ $20 constant ADMUX_ADLAR \ Left Adjust Result
+ $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
+&120 constant ADC \ ADC Data Register Bytes
+&122 constant ADCSRA \ The ADC Control and Status register A
+ $80 constant ADCSRA_ADEN \ ADC Enable
+ $40 constant ADCSRA_ADSC \ ADC Start Conversion
+ $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
+ $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
+ $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
+ $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
+&126 constant DIDR0 \ Digital Input Disable Register
+ $80 constant DIDR0_ADC7D \
+ $40 constant DIDR0_ADC6D \
+ $20 constant DIDR0_ADC5D \
+ $10 constant DIDR0_ADC4D \
+ $08 constant DIDR0_ADC3D \
+ $04 constant DIDR0_ADC2D \
+ $02 constant DIDR0_ADC1D \
+ $01 constant DIDR0_ADC0D \
+\ TIMER_COUNTER_1
+&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
+ $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
+ $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
+ $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
+ $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
+&54 constant TIFR1 \ Timer/Counter Interrupt Flag register
+ $20 constant TIFR1_ICF1 \ Timer/Counter1 Input Capture Flag
+ $04 constant TIFR1_OCF1B \ Timer/Counter1 Output Compare B Match Flag
+ $02 constant TIFR1_OCF1A \ Timer/Counter1 Output Compare A Match Flag
+ $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
+&128 constant TCCR1A \ Timer/Counter1 Control Register A
+ $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
+ $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
+ $03 constant TCCR1A_WGM1 \ Pulse Width Modulator Select Bits
+&129 constant TCCR1B \ Timer/Counter1 Control Register B
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ $18 constant TCCR1B_WGM1 \ Waveform Generation Mode Bits
+ $07 constant TCCR1B_CS1 \ Clock Select1 bits
+&130 constant TCCR1C \ Timer/Counter1 Control Register C
+ $80 constant TCCR1C_FOC1A \ Force Output Compare for Channel A
+ $40 constant TCCR1C_FOC1B \ Force Output Compare for Channel B
+&132 constant TCNT1 \ Timer/Counter1 Bytes
+&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
+&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
+&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
+\ EEPROM
+&65 constant EEAR \ EEPROM Address Register Low Bytes
+&64 constant EEDR \ EEPROM Data Register
+&63 constant EECR \ EEPROM Control Register
+ $30 constant EECR_EEPM \ EEPROM Programming Mode Bits
+ $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
+ $04 constant EECR_EEMPE \ EEPROM Master Write Enable
+ $02 constant EECR_EEPE \ EEPROM Write Enable
+ $01 constant EECR_EERE \ EEPROM Read Enable
+\ SPI
+&78 constant SPDR0 \ SPI Data Register
+&77 constant SPSR0 \ SPI Status Register
+ $80 constant SPSR0_SPIF0 \ SPI Interrupt Flag
+ $40 constant SPSR0_WCOL0 \ Write Collision Flag
+ $01 constant SPSR0_SPI2X0 \ Double SPI Speed Bit
+&76 constant SPCR0 \ SPI Control Register
+ $80 constant SPCR0_SPIE0 \ SPI Interrupt Enable
+ $40 constant SPCR0_SPE0 \ SPI Enable
+ $20 constant SPCR0_DORD0 \ Data Order
+ $10 constant SPCR0_MSTR0 \ Master/Slave Select
+ $08 constant SPCR0_CPOL0 \ Clock polarity
+ $04 constant SPCR0_CPHA0 \ Clock Phase
+ $02 constant SPCR0_SPR10 \ SPI Clock Rate Select 1
+ $01 constant SPCR0_SPR00 \ SPI Clock Rate Select 0
+\ TWI
+&189 constant TWAMR \ TWI (Slave) Address Mask Register
+ $FE constant TWAMR_TWAM \
+&184 constant TWBR \ TWI Bit Rate register
+&188 constant TWCR \ TWI Control Register
+ $80 constant TWCR_TWINT \ TWI Interrupt Flag
+ $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
+ $20 constant TWCR_TWSTA \ TWI Start Condition Bit
+ $10 constant TWCR_TWSTO \ TWI Stop Condition Bit
+ $08 constant TWCR_TWWC \ TWI Write Collition Flag
+ $04 constant TWCR_TWEN \ TWI Enable Bit
+ $01 constant TWCR_TWIE \ TWI Interrupt Enable
+&185 constant TWSR \ TWI Status Register
+ $F8 constant TWSR_TWS \ TWI Status
+ $03 constant TWSR_TWPS \ TWI Prescaler
+&187 constant TWDR \ TWI Data register
+&186 constant TWAR \ TWI (Slave) Address register
+ $FE constant TWAR_TWA \ TWI (Slave) Address register Bits
+ $01 constant TWAR_TWGCE \ TWI General Call Recognition Enable Bit
+\ USART1
+&206 constant UDR1 \ USART I/O Data Register
+&200 constant UCSR1A \ USART Control and Status Register A
+ $80 constant UCSR1A_RXC1 \ USART Receive Complete
+ $40 constant UCSR1A_TXC1 \ USART Transmitt Complete
+ $20 constant UCSR1A_UDRE1 \ USART Data Register Empty
+ $10 constant UCSR1A_FE1 \ Framing Error
+ $08 constant UCSR1A_DOR1 \ Data overRun
+ $04 constant UCSR1A_UPE1 \ Parity Error
+ $02 constant UCSR1A_U2X1 \ Double the USART transmission speed
+ $01 constant UCSR1A_MPCM1 \ Multi-processor Communication Mode
+&201 constant UCSR1B \ USART Control and Status Register B
+ $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable
+ $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable
+ $20 constant UCSR1B_UDRIE1 \ USART Data register Empty Interrupt Enable
+ $10 constant UCSR1B_RXEN1 \ Receiver Enable
+ $08 constant UCSR1B_TXEN1 \ Transmitter Enable
+ $04 constant UCSR1B_UCSZ12 \ Character Size
+ $02 constant UCSR1B_RXB81 \ Receive Data Bit 8
+ $01 constant UCSR1B_TXB81 \ Transmit Data Bit 8
+&202 constant UCSR1C \ USART Control and Status Register C
+ $C0 constant UCSR1C_UMSEL1 \ USART Mode Select
+ $30 constant UCSR1C_UPM1 \ Parity Mode Bits
+ $08 constant UCSR1C_USBS1 \ Stop Bit Select
+ $06 constant UCSR1C_UCSZ1 \ Character Size
+ $01 constant UCSR1C_UCPOL1 \ Clock Polarity
+&204 constant UBRR1 \ USART Baud Rate Register Bytes
+\ CPU
+&95 constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ $08 constant SREG_V \ Two's Complement Overflow Flag
+ $04 constant SREG_N \ Negative Flag
+ $02 constant SREG_Z \ Zero Flag
+ $01 constant SREG_C \ Carry Flag
+&93 constant SP \ Stack Pointer
+&102 constant OSCCAL \ Oscillator Calibration Value
+&97 constant CLKPR \
+ $80 constant CLKPR_CLKPCE \
+ $0F constant CLKPR_CLKPS \
+&83 constant SMCR \ Sleep Mode Control Register
+ $0E constant SMCR_SM \ Sleep Mode Select bits
+ $01 constant SMCR_SE \ Sleep Enable
+&75 constant GPIOR2 \ General Purpose IO Register 2
+ $FF constant GPIOR2_GPIOR \ General Purpose IO Register 2 bis
+&74 constant GPIOR1 \ General Purpose IO Register 1
+ $FF constant GPIOR1_GPIOR \ General Purpose IO Register 1 bis
+&62 constant GPIOR0 \ General Purpose IO Register 0
+ $80 constant GPIOR0_GPIOR07 \ General Purpose IO Register 0 bit 7
+ $40 constant GPIOR0_GPIOR06 \ General Purpose IO Register 0 bit 6
+ $20 constant GPIOR0_GPIOR05 \ General Purpose IO Register 0 bit 5
+ $10 constant GPIOR0_GPIOR04 \ General Purpose IO Register 0 bit 4
+ $08 constant GPIOR0_GPIOR03 \ General Purpose IO Register 0 bit 3
+ $04 constant GPIOR0_GPIOR02 \ General Purpose IO Register 0 bit 2
+ $02 constant GPIOR0_GPIOR01 \ General Purpose IO Register 0 bit 1
+ $01 constant GPIOR0_GPIOR00 \ General Purpose IO Register 0 bit 0
+&100 constant PRR0 \ Power Reduction Register0
+ $80 constant PRR0_PRTWI \ Power Reduction TWI
+ $40 constant PRR0_PRTIM2 \ Power Reduction Timer/Counter2
+ $20 constant PRR0_PRTIM0 \ Power Reduction Timer/Counter0
+ $12 constant PRR0_PRUSART \ Power Reduction USARTs
+ $08 constant PRR0_PRTIM1 \ Power Reduction Timer/Counter1
+ $04 constant PRR0_PRSPI \ Power Reduction Serial Peripheral Interface
+ $01 constant PRR0_PRADC \ Power Reduction ADC
+
+\ Interrupts
+&2 constant INT0Addr \ External Interrupt Request 0
+&4 constant INT1Addr \ External Interrupt Request 1
+&6 constant INT2Addr \ External Interrupt Request 2
+&8 constant PCINT0Addr \ Pin Change Interrupt Request 0
+&10 constant PCINT1Addr \ Pin Change Interrupt Request 1
+&12 constant PCINT2Addr \ Pin Change Interrupt Request 2
+&14 constant PCINT3Addr \ Pin Change Interrupt Request 3
+&16 constant WDTAddr \ Watchdog Time-out Interrupt
+&18 constant TIMER2_COMPAAddr \ Timer/Counter2 Compare Match A
+&20 constant TIMER2_COMPBAddr \ Timer/Counter2 Compare Match B
+&22 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
+&24 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+&26 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
+&28 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
+&30 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+&32 constant TIMER0_COMPAAddr \ Timer/Counter0 Compare Match A
+&34 constant TIMER0_COMPBAddr \ Timer/Counter0 Compare Match B
+&36 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
+&38 constant SPI__STCAddr \ SPI Serial Transfer Complete
+&40 constant USART0__RXAddr \ USART0, Rx Complete
+&42 constant USART0__UDREAddr \ USART0 Data register Empty
+&44 constant USART0__TXAddr \ USART0, Tx Complete
+&46 constant ANALOG_COMPAddr \ Analog Comparator
+&48 constant ADCAddr \ ADC Conversion Complete
+&50 constant EE_READYAddr \ EEPROM Ready
+&52 constant TWIAddr \ 2-wire Serial Interface
+&54 constant SPM_READYAddr \ Store Program Memory Read
+&56 constant USART1_RXAddr \ USART1 RX complete
+&58 constant USART1_UDREAddr \ USART1 Data Register Empty
+&60 constant USART1_TXAddr \ USART1 TX complete
diff --git a/amforth-6.5/avr8/devices/atmega324pa/device.asm b/amforth-6.5/avr8/devices/atmega324pa/device.asm
new file mode 100644
index 0000000..3651f34
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega324pa/device.asm
@@ -0,0 +1,120 @@
+; Partname: ATmega324PA
+; generated automatically, do not edit
+
+.nolist
+ .include "m324PAdef.inc"
+.list
+
+.equ ramstart = 256
+.equ CELLSIZE = 2
+.macro readflashcell
+ lsl zl
+ rol zh
+ lpm @0, Z+
+ lpm @1, Z+
+.endmacro
+.macro writeflashcell
+ lsl zl
+ rol zh
+.endmacro
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_USART0 = 0
+.set WANT_PORTA = 0
+.set WANT_PORTB = 0
+.set WANT_PORTC = 0
+.set WANT_PORTD = 0
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_TIMER_COUNTER_2 = 0
+.set WANT_WATCHDOG = 0
+.set WANT_JTAG = 0
+.set WANT_BOOT_LOAD = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_AD_CONVERTER = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_EEPROM = 0
+.set WANT_SPI = 0
+.set WANT_TWI = 0
+.set WANT_USART1 = 0
+.set WANT_CPU = 0
+.equ intvecsize = 2 ; please verify; flash size: 32768 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.org 2
+ rcall isr ; External Interrupt Request 0
+.org 4
+ rcall isr ; External Interrupt Request 1
+.org 6
+ rcall isr ; External Interrupt Request 2
+.org 8
+ rcall isr ; Pin Change Interrupt Request 0
+.org 10
+ rcall isr ; Pin Change Interrupt Request 1
+.org 12
+ rcall isr ; Pin Change Interrupt Request 2
+.org 14
+ rcall isr ; Pin Change Interrupt Request 3
+.org 16
+ rcall isr ; Watchdog Time-out Interrupt
+.org 18
+ rcall isr ; Timer/Counter2 Compare Match A
+.org 20
+ rcall isr ; Timer/Counter2 Compare Match B
+.org 22
+ rcall isr ; Timer/Counter2 Overflow
+.org 24
+ rcall isr ; Timer/Counter1 Capture Event
+.org 26
+ rcall isr ; Timer/Counter1 Compare Match A
+.org 28
+ rcall isr ; Timer/Counter1 Compare Match B
+.org 30
+ rcall isr ; Timer/Counter1 Overflow
+.org 32
+ rcall isr ; Timer/Counter0 Compare Match A
+.org 34
+ rcall isr ; Timer/Counter0 Compare Match B
+.org 36
+ rcall isr ; Timer/Counter0 Overflow
+.org 38
+ rcall isr ; SPI Serial Transfer Complete
+.org 40
+ rcall isr ; USART0, Rx Complete
+.org 42
+ rcall isr ; USART0 Data register Empty
+.org 44
+ rcall isr ; USART0, Tx Complete
+.org 46
+ rcall isr ; Analog Comparator
+.org 48
+ rcall isr ; ADC Conversion Complete
+.org 50
+ rcall isr ; EEPROM Ready
+.org 52
+ rcall isr ; 2-wire Serial Interface
+.org 54
+ rcall isr ; Store Program Memory Read
+.org 56
+ rcall isr ; USART1 RX complete
+.org 58
+ rcall isr ; USART1 Data Register Empty
+.org 60
+ rcall isr ; USART1 TX complete
+.equ INTVECTORS = 31
+.nooverlap
+
+; compatability layer (maybe empty)
+
+; controller data area, environment query mcu-info
+mcu_info:
+mcu_ramsize:
+ .dw 2048
+mcu_eepromsize:
+ .dw 1024
+mcu_maxdp:
+ .dw 28672
+mcu_numints:
+ .dw 31
+mcu_name:
+ .dw 11
+ .db "ATmega324PA",0
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega324pa/device.inc b/amforth-6.5/avr8/devices/atmega324pa/device.inc
new file mode 100644
index 0000000..8741996
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega324pa/device.inc
@@ -0,0 +1,1128 @@
+; Partname: ATmega324PA
+; generated automatically, no not edit
+
+.if WANT_ANALOG_COMPARATOR == 1
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Control and Status Register B
+VE_ADCSRB:
+ .dw $ff06
+ .db "ADCSRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRB
+XT_ADCSRB:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRB:
+ .dw 123
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Control And Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw 80
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 1
+VE_DIDR1:
+ .dw $ff05
+ .db "DIDR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR1
+XT_DIDR1:
+ .dw PFA_DOVARIABLE
+PFA_DIDR1:
+ .dw 127
+
+.endif
+.if WANT_USART0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR0:
+ .dw $ff04
+ .db "UDR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR0
+XT_UDR0:
+ .dw PFA_DOVARIABLE
+PFA_UDR0:
+ .dw 198
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR0A:
+ .dw $ff06
+ .db "UCSR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0A
+XT_UCSR0A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0A:
+ .dw 192
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR0B:
+ .dw $ff06
+ .db "UCSR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0B
+XT_UCSR0B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0B:
+ .dw 193
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR0C:
+ .dw $ff06
+ .db "UCSR0C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0C
+XT_UCSR0C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0C:
+ .dw 194
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Bytes
+VE_UBRR0:
+ .dw $ff05
+ .db "UBRR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR0
+XT_UBRR0:
+ .dw PFA_DOVARIABLE
+PFA_UBRR0:
+ .dw 196
+
+.endif
+.if WANT_PORTA == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Register
+VE_PORTA:
+ .dw $ff05
+ .db "PORTA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTA
+XT_PORTA:
+ .dw PFA_DOVARIABLE
+PFA_PORTA:
+ .dw 34
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Direction Register
+VE_DDRA:
+ .dw $ff04
+ .db "DDRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRA
+XT_DDRA:
+ .dw PFA_DOVARIABLE
+PFA_DDRA:
+ .dw 33
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Input Pins
+VE_PINA:
+ .dw $ff04
+ .db "PINA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINA
+XT_PINA:
+ .dw PFA_DOVARIABLE
+PFA_PINA:
+ .dw 32
+
+.endif
+.if WANT_PORTB == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw 37
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw 36
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw 35
+
+.endif
+.if WANT_PORTC == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Register
+VE_PORTC:
+ .dw $ff05
+ .db "PORTC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTC
+XT_PORTC:
+ .dw PFA_DOVARIABLE
+PFA_PORTC:
+ .dw 40
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Direction Register
+VE_DDRC:
+ .dw $ff04
+ .db "DDRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRC
+XT_DDRC:
+ .dw PFA_DOVARIABLE
+PFA_DDRC:
+ .dw 39
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Input Pins
+VE_PINC:
+ .dw $ff04
+ .db "PINC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINC
+XT_PINC:
+ .dw PFA_DOVARIABLE
+PFA_PINC:
+ .dw 38
+
+.endif
+.if WANT_PORTD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw 43
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw 42
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw 41
+
+.endif
+.if WANT_TIMER_COUNTER_0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0B:
+ .dw $ff05
+ .db "OCR0B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0B
+XT_OCR0B:
+ .dw PFA_DOVARIABLE
+PFA_OCR0B:
+ .dw 72
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0A:
+ .dw $ff05
+ .db "OCR0A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0A
+XT_OCR0A:
+ .dw PFA_DOVARIABLE
+PFA_OCR0A:
+ .dw 71
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw 70
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register B
+VE_TCCR0B:
+ .dw $ff06
+ .db "TCCR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0B
+XT_TCCR0B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0B:
+ .dw 69
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register A
+VE_TCCR0A:
+ .dw $ff06
+ .db "TCCR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0A
+XT_TCCR0A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0A:
+ .dw 68
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Mask Register
+VE_TIMSK0:
+ .dw $ff06
+ .db "TIMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK0
+XT_TIMSK0:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK0:
+ .dw 110
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Flag register
+VE_TIFR0:
+ .dw $ff05
+ .db "TIFR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR0
+XT_TIFR0:
+ .dw PFA_DOVARIABLE
+PFA_TIFR0:
+ .dw 53
+; ( -- addr ) System Constant
+; R( -- )
+; General Timer/Counter Control Register
+VE_GTCCR:
+ .dw $ff05
+ .db "GTCCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GTCCR
+XT_GTCCR:
+ .dw PFA_DOVARIABLE
+PFA_GTCCR:
+ .dw 67
+
+.endif
+.if WANT_TIMER_COUNTER_2 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Mask register
+VE_TIMSK2:
+ .dw $ff06
+ .db "TIMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK2
+XT_TIMSK2:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK2:
+ .dw 112
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Flag Register
+VE_TIFR2:
+ .dw $ff05
+ .db "TIFR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR2
+XT_TIFR2:
+ .dw PFA_DOVARIABLE
+PFA_TIFR2:
+ .dw 55
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register A
+VE_TCCR2A:
+ .dw $ff06
+ .db "TCCR2A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2A
+XT_TCCR2A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2A:
+ .dw 176
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register B
+VE_TCCR2B:
+ .dw $ff06
+ .db "TCCR2B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2B
+XT_TCCR2B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2B:
+ .dw 177
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2
+VE_TCNT2:
+ .dw $ff05
+ .db "TCNT2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT2
+XT_TCNT2:
+ .dw PFA_DOVARIABLE
+PFA_TCNT2:
+ .dw 178
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register B
+VE_OCR2B:
+ .dw $ff05
+ .db "OCR2B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2B
+XT_OCR2B:
+ .dw PFA_DOVARIABLE
+PFA_OCR2B:
+ .dw 180
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register A
+VE_OCR2A:
+ .dw $ff05
+ .db "OCR2A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2A
+XT_OCR2A:
+ .dw PFA_DOVARIABLE
+PFA_OCR2A:
+ .dw 179
+; ( -- addr ) System Constant
+; R( -- )
+; Asynchronous Status Register
+VE_ASSR:
+ .dw $ff04
+ .db "ASSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ASSR
+XT_ASSR:
+ .dw PFA_DOVARIABLE
+PFA_ASSR:
+ .dw 182
+
+.endif
+.if WANT_WATCHDOG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCSR:
+ .dw $ff06
+ .db "WDTCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCSR
+XT_WDTCSR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCSR:
+ .dw 96
+
+.endif
+.if WANT_JTAG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; On-Chip Debug Related Register in I/O Memory
+VE_OCDR:
+ .dw $ff04
+ .db "OCDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCDR
+XT_OCDR:
+ .dw PFA_DOVARIABLE
+PFA_OCDR:
+ .dw 81
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw 85
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Status Register
+VE_MCUSR:
+ .dw $ff05
+ .db "MCUSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUSR
+XT_MCUSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUSR:
+ .dw 84
+
+.endif
+.if WANT_BOOT_LOAD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control Register
+VE_SPMCSR:
+ .dw $ff06
+ .db "SPMCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCSR
+XT_SPMCSR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCSR:
+ .dw 87
+
+.endif
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register A
+VE_EICRA:
+ .dw $ff05
+ .db "EICRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRA
+XT_EICRA:
+ .dw PFA_DOVARIABLE
+PFA_EICRA:
+ .dw 105
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Mask Register
+VE_EIMSK:
+ .dw $ff05
+ .db "EIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIMSK
+XT_EIMSK:
+ .dw PFA_DOVARIABLE
+PFA_EIMSK:
+ .dw 61
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Flag Register
+VE_EIFR:
+ .dw $ff04
+ .db "EIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIFR
+XT_EIFR:
+ .dw PFA_DOVARIABLE
+PFA_EIFR:
+ .dw 60
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 3
+VE_PCMSK3:
+ .dw $ff06
+ .db "PCMSK3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK3
+XT_PCMSK3:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK3:
+ .dw 115
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 2
+VE_PCMSK2:
+ .dw $ff06
+ .db "PCMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK2
+XT_PCMSK2:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK2:
+ .dw 109
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 1
+VE_PCMSK1:
+ .dw $ff06
+ .db "PCMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK1
+XT_PCMSK1:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK1:
+ .dw 108
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 0
+VE_PCMSK0:
+ .dw $ff06
+ .db "PCMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK0
+XT_PCMSK0:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK0:
+ .dw 107
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Interrupt Flag Register
+VE_PCIFR:
+ .dw $ff05
+ .db "PCIFR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCIFR
+XT_PCIFR:
+ .dw PFA_DOVARIABLE
+PFA_PCIFR:
+ .dw 59
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Interrupt Control Register
+VE_PCICR:
+ .dw $ff05
+ .db "PCICR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCICR
+XT_PCICR:
+ .dw PFA_DOVARIABLE
+PFA_PCICR:
+ .dw 104
+
+.endif
+.if WANT_AD_CONVERTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC multiplexer Selection Register
+VE_ADMUX:
+ .dw $ff05
+ .db "ADMUX",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADMUX
+XT_ADMUX:
+ .dw PFA_DOVARIABLE
+PFA_ADMUX:
+ .dw 124
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register Bytes
+VE_ADC:
+ .dw $ff03
+ .db "ADC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADC
+XT_ADC:
+ .dw PFA_DOVARIABLE
+PFA_ADC:
+ .dw 120
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register A
+VE_ADCSRA:
+ .dw $ff06
+ .db "ADCSRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRA
+XT_ADCSRA:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRA:
+ .dw 122
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register
+VE_DIDR0:
+ .dw $ff05
+ .db "DIDR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR0
+XT_DIDR0:
+ .dw PFA_DOVARIABLE
+PFA_DIDR0:
+ .dw 126
+
+.endif
+.if WANT_TIMER_COUNTER_1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Mask Register
+VE_TIMSK1:
+ .dw $ff06
+ .db "TIMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK1
+XT_TIMSK1:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK1:
+ .dw 111
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Flag register
+VE_TIFR1:
+ .dw $ff05
+ .db "TIFR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR1
+XT_TIFR1:
+ .dw PFA_DOVARIABLE
+PFA_TIFR1:
+ .dw 54
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw 128
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw 129
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register C
+VE_TCCR1C:
+ .dw $ff06
+ .db "TCCR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1C
+XT_TCCR1C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1C:
+ .dw 130
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Bytes
+VE_TCNT1:
+ .dw $ff05
+ .db "TCNT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1
+XT_TCNT1:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1:
+ .dw 132
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register A Bytes
+VE_OCR1A:
+ .dw $ff05
+ .db "OCR1A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1A
+XT_OCR1A:
+ .dw PFA_DOVARIABLE
+PFA_OCR1A:
+ .dw 136
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register B Bytes
+VE_OCR1B:
+ .dw $ff05
+ .db "OCR1B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1B
+XT_OCR1B:
+ .dw PFA_DOVARIABLE
+PFA_OCR1B:
+ .dw 138
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Bytes
+VE_ICR1:
+ .dw $ff04
+ .db "ICR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1
+XT_ICR1:
+ .dw PFA_DOVARIABLE
+PFA_ICR1:
+ .dw 134
+
+.endif
+.if WANT_EEPROM == 1
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Address Register Low Bytes
+VE_EEAR:
+ .dw $ff04
+ .db "EEAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEAR
+XT_EEAR:
+ .dw PFA_DOVARIABLE
+PFA_EEAR:
+ .dw 65
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw 64
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw 63
+
+.endif
+.if WANT_SPI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR0:
+ .dw $ff05
+ .db "SPDR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR0
+XT_SPDR0:
+ .dw PFA_DOVARIABLE
+PFA_SPDR0:
+ .dw 78
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR0:
+ .dw $ff05
+ .db "SPSR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR0
+XT_SPSR0:
+ .dw PFA_DOVARIABLE
+PFA_SPSR0:
+ .dw 77
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR0:
+ .dw $ff05
+ .db "SPCR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR0
+XT_SPCR0:
+ .dw PFA_DOVARIABLE
+PFA_SPCR0:
+ .dw 76
+
+.endif
+.if WANT_TWI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; TWI (Slave) Address Mask Register
+VE_TWAMR:
+ .dw $ff05
+ .db "TWAMR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWAMR
+XT_TWAMR:
+ .dw PFA_DOVARIABLE
+PFA_TWAMR:
+ .dw 189
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Bit Rate register
+VE_TWBR:
+ .dw $ff04
+ .db "TWBR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWBR
+XT_TWBR:
+ .dw PFA_DOVARIABLE
+PFA_TWBR:
+ .dw 184
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Control Register
+VE_TWCR:
+ .dw $ff04
+ .db "TWCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWCR
+XT_TWCR:
+ .dw PFA_DOVARIABLE
+PFA_TWCR:
+ .dw 188
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Status Register
+VE_TWSR:
+ .dw $ff04
+ .db "TWSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWSR
+XT_TWSR:
+ .dw PFA_DOVARIABLE
+PFA_TWSR:
+ .dw 185
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Data register
+VE_TWDR:
+ .dw $ff04
+ .db "TWDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWDR
+XT_TWDR:
+ .dw PFA_DOVARIABLE
+PFA_TWDR:
+ .dw 187
+; ( -- addr ) System Constant
+; R( -- )
+; TWI (Slave) Address register
+VE_TWAR:
+ .dw $ff04
+ .db "TWAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWAR
+XT_TWAR:
+ .dw PFA_DOVARIABLE
+PFA_TWAR:
+ .dw 186
+
+.endif
+.if WANT_USART1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR1:
+ .dw $ff04
+ .db "UDR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR1
+XT_UDR1:
+ .dw PFA_DOVARIABLE
+PFA_UDR1:
+ .dw 206
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR1A:
+ .dw $ff06
+ .db "UCSR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1A
+XT_UCSR1A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1A:
+ .dw 200
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR1B:
+ .dw $ff06
+ .db "UCSR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1B
+XT_UCSR1B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1B:
+ .dw 201
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR1C:
+ .dw $ff06
+ .db "UCSR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1C
+XT_UCSR1C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1C:
+ .dw 202
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Bytes
+VE_UBRR1:
+ .dw $ff05
+ .db "UBRR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR1
+XT_UBRR1:
+ .dw PFA_DOVARIABLE
+PFA_UBRR1:
+ .dw 204
+
+.endif
+.if WANT_CPU == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw 95
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer
+VE_SP:
+ .dw $ff02
+ .db "SP"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SP
+XT_SP:
+ .dw PFA_DOVARIABLE
+PFA_SP:
+ .dw 93
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Calibration Value
+VE_OSCCAL:
+ .dw $ff06
+ .db "OSCCAL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSCCAL
+XT_OSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_OSCCAL:
+ .dw 102
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_CLKPR:
+ .dw $ff05
+ .db "CLKPR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKPR
+XT_CLKPR:
+ .dw PFA_DOVARIABLE
+PFA_CLKPR:
+ .dw 97
+; ( -- addr ) System Constant
+; R( -- )
+; Sleep Mode Control Register
+VE_SMCR:
+ .dw $ff04
+ .db "SMCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SMCR
+XT_SMCR:
+ .dw PFA_DOVARIABLE
+PFA_SMCR:
+ .dw 83
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 2
+VE_GPIOR2:
+ .dw $ff06
+ .db "GPIOR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR2
+XT_GPIOR2:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR2:
+ .dw 75
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 1
+VE_GPIOR1:
+ .dw $ff06
+ .db "GPIOR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR1
+XT_GPIOR1:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR1:
+ .dw 74
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 0
+VE_GPIOR0:
+ .dw $ff06
+ .db "GPIOR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR0
+XT_GPIOR0:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR0:
+ .dw 62
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register0
+VE_PRR0:
+ .dw $ff04
+ .db "PRR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR0
+XT_PRR0:
+ .dw PFA_DOVARIABLE
+PFA_PRR0:
+ .dw 100
+
+.endif
diff --git a/amforth-6.5/avr8/devices/atmega324pa/device.py b/amforth-6.5/avr8/devices/atmega324pa/device.py
new file mode 100644
index 0000000..c1ee97d
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega324pa/device.py
@@ -0,0 +1,389 @@
+# Generated Automatically
+
+# Partname ATmega324PA
+
+MCUREGS = {
+# Interrupt Vectors
+ 'INT0Addr' : '#2', # External Interrupt Request 0
+ 'INT1Addr' : '#4', # External Interrupt Request 1
+ 'INT2Addr' : '#6', # External Interrupt Request 2
+ 'PCINT0Addr' : '#8', # Pin Change Interrupt Request 0
+ 'PCINT1Addr' : '#10', # Pin Change Interrupt Request 1
+ 'PCINT2Addr' : '#12', # Pin Change Interrupt Request 2
+ 'PCINT3Addr' : '#14', # Pin Change Interrupt Request 3
+ 'WDTAddr' : '#16', # Watchdog Time-out Interrupt
+ 'TIMER2_COMPAAddr' : '#18', # Timer/Counter2 Compare Match A
+ 'TIMER2_COMPBAddr' : '#20', # Timer/Counter2 Compare Match B
+ 'TIMER2_OVFAddr' : '#22', # Timer/Counter2 Overflow
+ 'TIMER1_CAPTAddr' : '#24', # Timer/Counter1 Capture Event
+ 'TIMER1_COMPAAddr' : '#26', # Timer/Counter1 Compare Match A
+ 'TIMER1_COMPBAddr' : '#28', # Timer/Counter1 Compare Match B
+ 'TIMER1_OVFAddr' : '#30', # Timer/Counter1 Overflow
+ 'TIMER0_COMPAAddr' : '#32', # Timer/Counter0 Compare Match A
+ 'TIMER0_COMPBAddr' : '#34', # Timer/Counter0 Compare Match B
+ 'TIMER0_OVFAddr' : '#36', # Timer/Counter0 Overflow
+ 'SPI_STCAddr' : '#38', # SPI Serial Transfer Complete
+ 'USART0_RXAddr' : '#40', # USART0, Rx Complete
+ 'USART0_UDREAddr' : '#42', # USART0 Data register Empty
+ 'USART0_TXAddr' : '#44', # USART0, Tx Complete
+ 'ANALOG_COMPAddr' : '#46', # Analog Comparator
+ 'ADCAddr' : '#48', # ADC Conversion Complete
+ 'EE_READYAddr' : '#50', # EEPROM Ready
+ 'TWIAddr' : '#52', # 2-wire Serial Interface
+ 'SPM_READYAddr' : '#54', # Store Program Memory Read
+ 'USART1_RXAddr' : '#56', # USART1 RX complete
+ 'USART1_UDREAddr' : '#58', # USART1 Data Register Empty
+ 'USART1_TXAddr' : '#60', # USART1 TX complete
+
+# Module ANALOG_COMPARATOR
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
+ 'ACSR' : '$50', # Analog Comparator Control And
+ 'ACSR_ACD': '$80', # Analog Comparator Disable
+ 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
+ 'ACSR_ACO': '$20', # Analog Compare Output
+ 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
+ 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
+ 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
+ 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
+ 'DIDR1' : '$7f', # Digital Input Disable Register
+ 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
+ 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
+
+# Module USART0
+ 'UDR0' : '$c6', # USART I/O Data Register
+ 'UCSR0A' : '$c0', # USART Control and Status Regis
+ 'UCSR0A_RXC0': '$80', # USART Receive Complete
+ 'UCSR0A_TXC0': '$40', # USART Transmitt Complete
+ 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
+ 'UCSR0A_FE0': '$10', # Framing Error
+ 'UCSR0A_DOR0': '$8', # Data overRun
+ 'UCSR0A_UPE0': '$4', # Parity Error
+ 'UCSR0A_U2X0': '$2', # Double the USART transmission
+ 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
+ 'UCSR0B' : '$c1', # USART Control and Status Regis
+ 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
+ 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
+ 'UCSR0B_UDRIE0': '$20', # USART Data register Empty Inte
+ 'UCSR0B_RXEN0': '$10', # Receiver Enable
+ 'UCSR0B_TXEN0': '$8', # Transmitter Enable
+ 'UCSR0B_UCSZ02': '$4', # Character Size
+ 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
+ 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
+ 'UCSR0C' : '$c2', # USART Control and Status Regis
+ 'UCSR0C_UMSEL0': '$c0', # USART Mode Select
+ 'UCSR0C_UPM0': '$30', # Parity Mode Bits
+ 'UCSR0C_USBS0': '$8', # Stop Bit Select
+ 'UCSR0C_UCSZ0': '$6', # Character Size
+ 'UCSR0C_UCPOL0': '$1', # Clock Polarity
+ 'UBRR0' : '$c4', # USART Baud Rate Register Byte
+
+# Module PORTA
+ 'PORTA' : '$22', # Port A Data Register
+ 'DDRA' : '$21', # Port A Data Direction Register
+ 'PINA' : '$20', # Port A Input Pins
+
+# Module PORTB
+ 'PORTB' : '$25', # Port B Data Register
+ 'DDRB' : '$24', # Port B Data Direction Register
+ 'PINB' : '$23', # Port B Input Pins
+
+# Module PORTC
+ 'PORTC' : '$28', # Port C Data Register
+ 'DDRC' : '$27', # Port C Data Direction Register
+ 'PINC' : '$26', # Port C Input Pins
+
+# Module PORTD
+ 'PORTD' : '$2b', # Port D Data Register
+ 'DDRD' : '$2a', # Port D Data Direction Register
+ 'PIND' : '$29', # Port D Input Pins
+
+# Module TIMER_COUNTER_0
+ 'OCR0B' : '$48', # Timer/Counter0 Output Compare
+ 'OCR0A' : '$47', # Timer/Counter0 Output Compare
+ 'TCNT0' : '$46', # Timer/Counter0
+ 'TCCR0B' : '$45', # Timer/Counter Control Register
+ 'TCCR0B_FOC0A': '$80', # Force Output Compare A
+ 'TCCR0B_FOC0B': '$40', # Force Output Compare B
+ 'TCCR0B_WGM02': '$8', #
+ 'TCCR0B_CS0': '$7', # Clock Select
+ 'TCCR0A' : '$44', # Timer/Counter Control Registe
+ 'TCCR0A_COM0A': '$c0', # Compare Output Mode, Phase Cor
+ 'TCCR0A_COM0B': '$30', # Compare Output Mode, Fast PWm
+ 'TCCR0A_WGM0': '$3', # Waveform Generation Mode
+ 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
+ 'TIMSK0_OCIE0B': '$4', # Timer/Counter0 Output Compare
+ 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
+ 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
+ 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
+ 'TIFR0_OCF0B': '$4', # Timer/Counter0 Output Compare
+ 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
+ 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSRSYNC': '$1', # Prescaler Reset Timer/Counter1
+
+# Module TIMER_COUNTER_2
+ 'TIMSK2' : '$70', # Timer/Counter Interrupt Mask r
+ 'TIMSK2_OCIE2B': '$4', # Timer/Counter2 Output Compare
+ 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
+ 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
+ 'TIFR2' : '$37', # Timer/Counter Interrupt Flag R
+ 'TIFR2_OCF2B': '$4', # Output Compare Flag 2B
+ 'TIFR2_OCF2A': '$2', # Output Compare Flag 2A
+ 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
+ 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
+ 'TCCR2A_COM2A': '$c0', # Compare Output Mode bits
+ 'TCCR2A_COM2B': '$30', # Compare Output Mode bits
+ 'TCCR2A_WGM2': '$3', # Waveform Genration Mode
+ 'TCCR2B' : '$b1', # Timer/Counter2 Control Registe
+ 'TCCR2B_FOC2A': '$80', # Force Output Compare A
+ 'TCCR2B_FOC2B': '$40', # Force Output Compare B
+ 'TCCR2B_WGM22': '$8', # Waveform Generation Mode
+ 'TCCR2B_CS2': '$7', # Clock Select bits
+ 'TCNT2' : '$b2', # Timer/Counter2
+ 'OCR2B' : '$b4', # Timer/Counter2 Output Compare
+ 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
+ 'ASSR' : '$b6', # Asynchronous Status Register
+ 'ASSR_EXCLK': '$40', # Enable External Clock Input
+ 'ASSR_AS2': '$20', # Asynchronous Timer/Counter2
+ 'ASSR_TCN2UB': '$10', # Timer/Counter2 Update Busy
+ 'ASSR_OCR2AUB': '$8', # Output Compare Register2 Updat
+ 'ASSR_OCR2BUB': '$4', # Output Compare Register 2 Upda
+ 'ASSR_TCR2AUB': '$2', # Timer/Counter Control Register
+ 'ASSR_TCR2BUB': '$1', # Timer/Counter Control Register
+ 'GTCCR' : '$43', # General Timer Counter Control
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSRASY': '$2', # Prescaler Reset Timer/Counter2
+
+# Module WATCHDOG
+ 'WDTCSR' : '$60', # Watchdog Timer Control Registe
+ 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
+ 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
+ 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
+ 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
+ 'WDTCSR_WDE': '$8', # Watch Dog Enable
+
+# Module JTAG
+ 'OCDR' : '$51', # On-Chip Debug Related Register
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_JTD': '$80', # JTAG Interface Disable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+
+# Module BOOT_LOAD
+ 'SPMCSR' : '$57', # Store Program Memory Control R
+ 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
+ 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
+ 'SPMCSR_SIGRD': '$20', # Signature Row Read
+ 'SPMCSR_RWWSRE': '$10', # Read While Write section read
+ 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
+ 'SPMCSR_PGWRT': '$4', # Page Write
+ 'SPMCSR_PGERS': '$2', # Page Erase
+ 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
+
+# Module EXTERNAL_INTERRUPT
+ 'EICRA' : '$69', # External Interrupt Control Reg
+ 'EICRA_ISC2': '$30', # External Interrupt Sense Contr
+ 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
+ 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
+ 'EIMSK' : '$3d', # External Interrupt Mask Regist
+ 'EIMSK_INT': '$7', # External Interrupt Request 2 E
+ 'EIFR' : '$3c', # External Interrupt Flag Regist
+ 'EIFR_INTF': '$7', # External Interrupt Flags
+ 'PCMSK3' : '$73', # Pin Change Mask Register 3
+ 'PCMSK3_PCINT': '$ff', # Pin Change Enable Masks
+ 'PCMSK2' : '$6d', # Pin Change Mask Register 2
+ 'PCMSK2_PCINT': '$ff', # Pin Change Enable Masks
+ 'PCMSK1' : '$6c', # Pin Change Mask Register 1
+ 'PCMSK1_PCINT': '$ff', # Pin Change Enable Masks
+ 'PCMSK0' : '$6b', # Pin Change Mask Register 0
+ 'PCMSK0_PCINT': '$ff', # Pin Change Enable Masks
+ 'PCIFR' : '$3b', # Pin Change Interrupt Flag Regi
+ 'PCIFR_PCIF': '$f', # Pin Change Interrupt Flags
+ 'PCICR' : '$68', # Pin Change Interrupt Control R
+ 'PCICR_PCIE': '$f', # Pin Change Interrupt Enables
+
+# Module AD_CONVERTER
+ 'ADMUX' : '$7c', # The ADC multiplexer Selection
+ 'ADMUX_REFS': '$c0', # Reference Selection Bits
+ 'ADMUX_ADLAR': '$20', # Left Adjust Result
+ 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
+ 'ADC' : '$78', # ADC Data Register Bytes
+ 'ADCSRA' : '$7a', # The ADC Control and Status reg
+ 'ADCSRA_ADEN': '$80', # ADC Enable
+ 'ADCSRA_ADSC': '$40', # ADC Start Conversion
+ 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
+ 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
+ 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
+ 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
+ 'ADCSRB' : '$7b', # The ADC Control and Status reg
+ 'ADCSRB_ACME': '$40', #
+ 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Source bits
+ 'DIDR0' : '$7e', # Digital Input Disable Register
+ 'DIDR0_ADC7D': '$80', #
+ 'DIDR0_ADC6D': '$40', #
+ 'DIDR0_ADC5D': '$20', #
+ 'DIDR0_ADC4D': '$10', #
+ 'DIDR0_ADC3D': '$8', #
+ 'DIDR0_ADC2D': '$4', #
+ 'DIDR0_ADC1D': '$2', #
+ 'DIDR0_ADC0D': '$1', #
+
+# Module TIMER_COUNTER_1
+ 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
+ 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
+ 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
+ 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
+ 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
+ 'TIFR1' : '$36', # Timer/Counter Interrupt Flag r
+ 'TIFR1_ICF1': '$20', # Timer/Counter1 Input Capture F
+ 'TIFR1_OCF1B': '$4', # Timer/Counter1 Output Compare
+ 'TIFR1_OCF1A': '$2', # Timer/Counter1 Output Compare
+ 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
+ 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
+ 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
+ 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
+ 'TCCR1A_WGM1': '$3', # Pulse Width Modulator Select B
+ 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
+ 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
+ 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
+ 'TCCR1B_WGM1': '$18', # Waveform Generation Mode Bits
+ 'TCCR1B_CS1': '$7', # Clock Select1 bits
+ 'TCCR1C' : '$82', # Timer/Counter1 Control Registe
+ 'TCCR1C_FOC1A': '$80', # Force Output Compare for Chann
+ 'TCCR1C_FOC1B': '$40', # Force Output Compare for Chann
+ 'TCNT1' : '$84', # Timer/Counter1 Bytes
+ 'OCR1A' : '$88', # Timer/Counter1 Output Compare
+ 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
+ 'ICR1' : '$86', # Timer/Counter1 Input Capture R
+
+# Module EEPROM
+ 'EEAR' : '$41', # EEPROM Address Register Low By
+ 'EEDR' : '$40', # EEPROM Data Register
+ 'EECR' : '$3f', # EEPROM Control Register
+ 'EECR_EEPM': '$30', # EEPROM Programming Mode Bits
+ 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
+ 'EECR_EEMPE': '$4', # EEPROM Master Write Enable
+ 'EECR_EEPE': '$2', # EEPROM Write Enable
+ 'EECR_EERE': '$1', # EEPROM Read Enable
+
+# Module SPI
+ 'SPDR0' : '$4e', # SPI Data Register
+ 'SPSR0' : '$4d', # SPI Status Register
+ 'SPSR0_SPIF0': '$80', # SPI Interrupt Flag
+ 'SPSR0_WCOL0': '$40', # Write Collision Flag
+ 'SPSR0_SPI2X0': '$1', # Double SPI Speed Bit
+ 'SPCR0' : '$4c', # SPI Control Register
+ 'SPCR0_SPIE0': '$80', # SPI Interrupt Enable
+ 'SPCR0_SPE0': '$40', # SPI Enable
+ 'SPCR0_DORD0': '$20', # Data Order
+ 'SPCR0_MSTR0': '$10', # Master/Slave Select
+ 'SPCR0_CPOL0': '$8', # Clock polarity
+ 'SPCR0_CPHA0': '$4', # Clock Phase
+ 'SPCR0_SPR10': '$2', # SPI Clock Rate Select 1
+ 'SPCR0_SPR00': '$1', # SPI Clock Rate Select 0
+
+# Module TWI
+ 'TWAMR' : '$bd', # TWI (Slave) Address Mask Regis
+ 'TWAMR_TWAM': '$fe', #
+ 'TWBR' : '$b8', # TWI Bit Rate register
+ 'TWCR' : '$bc', # TWI Control Register
+ 'TWCR_TWINT': '$80', # TWI Interrupt Flag
+ 'TWCR_TWEA': '$40', # TWI Enable Acknowledge Bit
+ 'TWCR_TWSTA': '$20', # TWI Start Condition Bit
+ 'TWCR_TWSTO': '$10', # TWI Stop Condition Bit
+ 'TWCR_TWWC': '$8', # TWI Write Collition Flag
+ 'TWCR_TWEN': '$4', # TWI Enable Bit
+ 'TWCR_TWIE': '$1', # TWI Interrupt Enable
+ 'TWSR' : '$b9', # TWI Status Register
+ 'TWSR_TWS': '$f8', # TWI Status
+ 'TWSR_TWPS': '$3', # TWI Prescaler
+ 'TWDR' : '$bb', # TWI Data register
+ 'TWAR' : '$ba', # TWI (Slave) Address register
+ 'TWAR_TWA': '$fe', # TWI (Slave) Address register B
+ 'TWAR_TWGCE': '$1', # TWI General Call Recognition E
+
+# Module USART1
+ 'UDR1' : '$ce', # USART I/O Data Register
+ 'UCSR1A' : '$c8', # USART Control and Status Regis
+ 'UCSR1A_RXC1': '$80', # USART Receive Complete
+ 'UCSR1A_TXC1': '$40', # USART Transmitt Complete
+ 'UCSR1A_UDRE1': '$20', # USART Data Register Empty
+ 'UCSR1A_FE1': '$10', # Framing Error
+ 'UCSR1A_DOR1': '$8', # Data overRun
+ 'UCSR1A_UPE1': '$4', # Parity Error
+ 'UCSR1A_U2X1': '$2', # Double the USART transmission
+ 'UCSR1A_MPCM1': '$1', # Multi-processor Communication
+ 'UCSR1B' : '$c9', # USART Control and Status Regis
+ 'UCSR1B_RXCIE1': '$80', # RX Complete Interrupt Enable
+ 'UCSR1B_TXCIE1': '$40', # TX Complete Interrupt Enable
+ 'UCSR1B_UDRIE1': '$20', # USART Data register Empty Inte
+ 'UCSR1B_RXEN1': '$10', # Receiver Enable
+ 'UCSR1B_TXEN1': '$8', # Transmitter Enable
+ 'UCSR1B_UCSZ12': '$4', # Character Size
+ 'UCSR1B_RXB81': '$2', # Receive Data Bit 8
+ 'UCSR1B_TXB81': '$1', # Transmit Data Bit 8
+ 'UCSR1C' : '$ca', # USART Control and Status Regis
+ 'UCSR1C_UMSEL1': '$c0', # USART Mode Select
+ 'UCSR1C_UPM1': '$30', # Parity Mode Bits
+ 'UCSR1C_USBS1': '$8', # Stop Bit Select
+ 'UCSR1C_UCSZ1': '$6', # Character Size
+ 'UCSR1C_UCPOL1': '$1', # Clock Polarity
+ 'UBRR1' : '$cc', # USART Baud Rate Register Byte
+
+# Module CPU
+ 'SREG' : '$5f', # Status Register
+ 'SREG_I': '$80', # Global Interrupt Enable
+ 'SREG_T': '$40', # Bit Copy Storage
+ 'SREG_H': '$20', # Half Carry Flag
+ 'SREG_S': '$10', # Sign Bit
+ 'SREG_V': '$8', # Two's Complement Overflow Flag
+ 'SREG_N': '$4', # Negative Flag
+ 'SREG_Z': '$2', # Zero Flag
+ 'SREG_C': '$1', # Carry Flag
+ 'SP' : '$5d', # Stack Pointer
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_JTD': '$80', # JTAG Interface Disable
+ 'MCUCR_BODS': '$40', # BOD Power Down in Sleep
+ 'MCUCR_BODSE': '$20', # BOD Power Down in Sleep Enable
+ 'MCUCR_PUD': '$10', # Pull-up disable
+ 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
+ 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+ 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
+ 'MCUSR_BORF': '$4', # Brown-out Reset Flag
+ 'MCUSR_EXTRF': '$2', # External Reset Flag
+ 'MCUSR_PORF': '$1', # Power-on reset flag
+ 'OSCCAL' : '$66', # Oscillator Calibration Value
+ 'CLKPR' : '$61', #
+ 'CLKPR_CLKPCE': '$80', #
+ 'CLKPR_CLKPS': '$f', #
+ 'SMCR' : '$53', # Sleep Mode Control Register
+ 'SMCR_SM': '$e', # Sleep Mode Select bits
+ 'SMCR_SE': '$1', # Sleep Enable
+ 'GPIOR2' : '$4b', # General Purpose IO Register 2
+ 'GPIOR2_GPIOR': '$ff', # General Purpose IO Register 2
+ 'GPIOR1' : '$4a', # General Purpose IO Register 1
+ 'GPIOR1_GPIOR': '$ff', # General Purpose IO Register 1
+ 'GPIOR0' : '$3e', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR07': '$80', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR06': '$40', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR05': '$20', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR04': '$10', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR03': '$8', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR02': '$4', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR01': '$2', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR00': '$1', # General Purpose IO Register 0
+ 'PRR0' : '$64', # Power Reduction Register0
+ 'PRR0_PRTWI': '$80', # Power Reduction TWI
+ 'PRR0_PRTIM2': '$40', # Power Reduction Timer/Counter2
+ 'PRR0_PRTIM0': '$20', # Power Reduction Timer/Counter0
+ 'PRR0_PRUSART': '$12', # Power Reduction USARTs
+ 'PRR0_PRTIM1': '$8', # Power Reduction Timer/Counter1
+ 'PRR0_PRSPI': '$4', # Power Reduction Serial Periphe
+ 'PRR0_PRADC': '$1', # Power Reduction ADC
+
+ '__amforth_dummy':'0'
+}
diff --git a/amforth-6.5/avr8/devices/atmega324pa/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega324pa/words/no-jtag.asm
new file mode 100644
index 0000000..352a4bb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega324pa/words/no-jtag.asm
@@ -0,0 +1,14 @@
+; ( -- )
+; ( -- )
+; MCU
+; disable jtag at runtime
+VE_NOJTAG:
+ .dw $FF05
+ .db "-jtag",0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOJTAG
+XT_NOJTAG:
+ .dw PFA_NOJTAG
+PFA_NOJTAG:
+
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega324pa/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega324pa/words/no-wdt.asm
new file mode 100644
index 0000000..ff6ddd1
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega324pa/words/no-wdt.asm
@@ -0,0 +1,34 @@
+; ( -- )
+; MCU
+; disable watch dog timer at runtime
+VE_NOWDT:
+ .dw $ff04
+ .db "-wdt"
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOWDT
+XT_NOWDT:
+ .dw PFA_NOWDT
+PFA_NOWDT:
+
+ in temp1,SREG
+ push temp1
+ ; Turn always off global interrupt.
+ cli
+ ; Reset Watchdog Timer
+ wdr
+ ; Clear WDRF in MCUSR
+ in temp1, MCUSR
+ andi temp1, (0xff & (0<<WDRF))
+ out MCUSR, temp1
+ ; Write logical one to WDCE and WDE
+ ; Keep old prescaler setting to prevent unintentional time-out
+ in_ temp1, WDTCSR
+ ori temp1, (1<<WDCE) | (1<<WDE)
+ out_ WDTCSR, temp1
+ ; Turn off WDT
+ ldi temp1, (0<<WDE)
+ out_ WDTCSR, temp1
+ ; restore status register
+ pop temp1
+ out SREG,temp1
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega324pa/words/sleep.asm b/amforth-6.5/avr8/devices/atmega324pa/words/sleep.asm
new file mode 100644
index 0000000..256249c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega324pa/words/sleep.asm
@@ -0,0 +1,19 @@
+; ( mode -- )
+; MCU
+; put the controller into the specified sleep mode
+VE_SLEEP:
+ .dw $ff05
+ .db "sleep", 0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_SLEEP
+XT_SLEEP:
+ .dw PFA_SLEEP
+PFA_SLEEP:
+ andi tosl, 7 ; leave only legal mode bits
+ lsl tosl ; move to correct location (bits 3-1)
+ ori tosl, 1 ; set the SE bit
+ out_ SMCR, tosl ; set the sleep config
+ sleep ; nighty-night
+ out_ SMCR, zerol ; 0 protects against accidental sleeps
+ loadtos ; pop argument from stack
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega325/atmega325.frt b/amforth-6.5/avr8/devices/atmega325/atmega325.frt
new file mode 100644
index 0000000..4030095
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega325/atmega325.frt
@@ -0,0 +1,278 @@
+\ Partname: ATmega325
+\ generated automatically
+
+\ AD_CONVERTER
+&124 constant ADMUX \ The ADC multiplexer Selection Register
+ $C0 constant ADMUX_REFS \ Reference Selection Bits
+ $20 constant ADMUX_ADLAR \ Left Adjust Result
+ $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
+&122 constant ADCSRA \ The ADC Control and Status register
+ $80 constant ADCSRA_ADEN \ ADC Enable
+ $40 constant ADCSRA_ADSC \ ADC Start Conversion
+ $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
+ $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
+ $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
+ $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
+&120 constant ADC \ ADC Data Register Bytes
+&123 constant ADCSRB \ ADC Control and Status Register B
+ $07 constant ADCSRB_ADTS \ ADC Auto Trigger Sources
+&126 constant DIDR0 \ Digital Input Disable Register 0
+ $80 constant DIDR0_ADC7D \ ADC7 Digital input Disable
+ $40 constant DIDR0_ADC6D \ ADC6 Digital input Disable
+ $20 constant DIDR0_ADC5D \ ADC5 Digital input Disable
+ $10 constant DIDR0_ADC4D \ ADC4 Digital input Disable
+ $08 constant DIDR0_ADC3D \ ADC3 Digital input Disable
+ $04 constant DIDR0_ADC2D \ ADC2 Digital input Disable
+ $02 constant DIDR0_ADC1D \ ADC1 Digital input Disable
+ $01 constant DIDR0_ADC0D \ ADC0 Digital input Disable
+\ ANALOG_COMPARATOR
+&80 constant ACSR \ Analog Comparator Control And Status Register
+ $80 constant ACSR_ACD \ Analog Comparator Disable
+ $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
+ $20 constant ACSR_ACO \ Analog Compare Output
+ $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
+ $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
+ $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
+ $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
+&127 constant DIDR1 \ Digital Input Disable Register 1
+ $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
+ $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
+\ USART0
+&198 constant UDR0 \ USART I/O Data Register
+&192 constant UCSR0A \ USART Control and Status Register A
+ $80 constant UCSR0A_RXC0 \ USART Receive Complete
+ $40 constant UCSR0A_TXC0 \ USART Transmit Complete
+ $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
+ $10 constant UCSR0A_FE0 \ Framing Error
+ $08 constant UCSR0A_DOR0 \ Data OverRun
+ $04 constant UCSR0A_UPE0 \ USART Parity Error
+ $02 constant UCSR0A_U2X0 \ Double the USART Transmission Speed
+ $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
+&193 constant UCSR0B \ USART Control and Status Register B
+ $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
+ $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
+ $20 constant UCSR0B_UDRIE0 \ USART Data Register Empty Interrupt Enable
+ $10 constant UCSR0B_RXEN0 \ Receiver Enable
+ $08 constant UCSR0B_TXEN0 \ Transmitter Enable
+ $04 constant UCSR0B_UCSZ02 \ Character Size
+ $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
+ $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
+&194 constant UCSR0C \ USART Control and Status Register C
+ $40 constant UCSR0C_UMSEL0 \ USART Mode Select
+ $30 constant UCSR0C_UPM0 \ Parity Mode Bits
+ $08 constant UCSR0C_USBS0 \ Stop Bit Select
+ $06 constant UCSR0C_UCSZ0 \ Character Size
+ $01 constant UCSR0C_UCPOL0 \ Clock Polarity
+&196 constant UBRR0 \ USART Baud Rate Register Bytes
+\ USI
+&186 constant USIDR \ USI Data Register
+&185 constant USISR \ USI Status Register
+ $80 constant USISR_USISIF \ Start Condition Interrupt Flag
+ $40 constant USISR_USIOIF \ Counter Overflow Interrupt Flag
+ $20 constant USISR_USIPF \ Stop Condition Flag
+ $10 constant USISR_USIDC \ Data Output Collision
+ $0F constant USISR_USICNT \ USI Counter Value Bits
+&184 constant USICR \ USI Control Register
+ $80 constant USICR_USISIE \ Start Condition Interrupt Enable
+ $40 constant USICR_USIOIE \ Counter Overflow Interrupt Enable
+ $30 constant USICR_USIWM \ USI Wire Mode Bits
+ $0C constant USICR_USICS \ USI Clock Source Select Bits
+ $02 constant USICR_USICLK \ Clock Strobe
+ $01 constant USICR_USITC \ Toggle Clock Port Pin
+\ SPI
+&76 constant SPCR \ SPI Control Register
+ $80 constant SPCR_SPIE \ SPI Interrupt Enable
+ $40 constant SPCR_SPE \ SPI Enable
+ $20 constant SPCR_DORD \ Data Order
+ $10 constant SPCR_MSTR \ Master/Slave Select
+ $08 constant SPCR_CPOL \ Clock polarity
+ $04 constant SPCR_CPHA \ Clock Phase
+ $03 constant SPCR_SPR \ SPI Clock Rate Selects
+&77 constant SPSR \ SPI Status Register
+ $80 constant SPSR_SPIF \ SPI Interrupt Flag
+ $40 constant SPSR_WCOL \ Write Collision Flag
+ $01 constant SPSR_SPI2X \ Double SPI Speed Bit
+&78 constant SPDR \ SPI Data Register
+\ BOOT_LOAD
+&87 constant SPMCSR \ Store Program Memory Control Register
+ $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
+ $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
+ $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
+ $04 constant SPMCSR_PGWRT \ Page Write
+ $02 constant SPMCSR_PGERS \ Page Erase
+ $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
+\ JTAG
+&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
+&85 constant MCUCR \ MCU Control Register
+ $80 constant MCUCR_JTD \ JTAG Interface Disable
+&84 constant MCUSR \ MCU Status Register
+ $10 constant MCUSR_JTRF \ JTAG Reset Flag
+\ EXTERNAL_INTERRUPT
+&105 constant EICRA \ External Interrupt Control Register A
+ $02 constant EICRA_ISC01 \ External Interrupt Sense Control 0 Bit 1
+ $01 constant EICRA_ISC00 \ External Interrupt Sense Control 0 Bit 0
+&61 constant EIMSK \ External Interrupt Mask Register
+ $F0 constant EIMSK_PCIE \ Pin Change Interrupt Enables
+ $01 constant EIMSK_INT0 \ External Interrupt Request 0 Enable
+&60 constant EIFR \ External Interrupt Flag Register
+ $F0 constant EIFR_PCIF \ Pin Change Interrupt Flags
+ $01 constant EIFR_INTF0 \ External Interrupt Flag 0
+&108 constant PCMSK1 \ Pin Change Mask Register 1
+&107 constant PCMSK0 \ Pin Change Mask Register 0
+\ EEPROM
+&65 constant EEAR \ EEPROM Read/Write Access Bytes
+&64 constant EEDR \ EEPROM Data Register
+&63 constant EECR \ EEPROM Control Register
+ $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
+ $04 constant EECR_EEMWE \ EEPROM Master Write Enable
+ $02 constant EECR_EEWE \ EEPROM Write Enable
+ $01 constant EECR_EERE \ EEPROM Read Enable
+\ PORTA
+&34 constant PORTA \ Port A Data Register
+&33 constant DDRA \ Port A Data Direction Register
+&32 constant PINA \ Port A Input Pins
+\ PORTB
+&37 constant PORTB \ Port B Data Register
+&36 constant DDRB \ Port B Data Direction Register
+&35 constant PINB \ Port B Input Pins
+\ PORTC
+&40 constant PORTC \ Port C Data Register
+&39 constant DDRC \ Port C Data Direction Register
+&38 constant PINC \ Port C Input Pins
+\ PORTD
+&43 constant PORTD \ Port D Data Register
+&42 constant DDRD \ Port D Data Direction Register
+&41 constant PIND \ Port D Input Pins
+\ PORTE
+&46 constant PORTE \ Data Register, Port E
+&45 constant DDRE \ Data Direction Register, Port E
+&44 constant PINE \ Input Pins, Port E
+\ PORTF
+&49 constant PORTF \ Data Register, Port F
+&48 constant DDRF \ Data Direction Register, Port F
+&47 constant PINF \ Input Pins, Port F
+\ PORTG
+&52 constant PORTG \ Port G Data Register
+&51 constant DDRG \ Port G Data Direction Register
+&50 constant PING \ Port G Input Pins
+\ TIMER_COUNTER_0
+&68 constant TCCR0A \ Timer/Counter0 Control Register
+ $80 constant TCCR0A_FOC0A \ Force Output Compare
+ $40 constant TCCR0A_WGM00 \ Waveform Generation Mode 0
+ $30 constant TCCR0A_COM0A \ Compare Match Output Modes
+ $08 constant TCCR0A_WGM01 \ Waveform Generation Mode 1
+ $07 constant TCCR0A_CS0 \ Clock Selects
+&70 constant TCNT0 \ Timer/Counter0
+&71 constant OCR0A \ Timer/Counter0 Output Compare Register
+&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
+ $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match Interrupt Enable
+ $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
+&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
+ $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0
+ $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
+&67 constant GTCCR \ General Timer/Control Register
+ $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
+ $01 constant GTCCR_PSR310 \ Prescaler Reset Timer/Counter1 and Timer/Counter0
+\ TIMER_COUNTER_1
+&128 constant TCCR1A \ Timer/Counter1 Control Register A
+ $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
+ $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
+ $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
+&129 constant TCCR1B \ Timer/Counter1 Control Register B
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
+ $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
+&130 constant TCCR1C \ Timer/Counter 1 Control Register C
+ $80 constant TCCR1C_FOC1A \ Force Output Compare 1A
+ $40 constant TCCR1C_FOC1B \ Force Output Compare 1B
+&132 constant TCNT1 \ Timer/Counter1 Bytes
+&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
+&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
+&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
+&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
+ $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
+ $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
+ $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
+ $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
+&54 constant TIFR1 \ Timer/Counter1 Interrupt Flag register
+ $20 constant TIFR1_ICF1 \ Input Capture Flag 1
+ $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
+ $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
+ $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
+\ TIMER_COUNTER_2
+&176 constant TCCR2A \ Timer/Counter2 Control Register
+ $80 constant TCCR2A_FOC2A \ Force Output Compare A
+ $40 constant TCCR2A_WGM20 \ Waveform Generation Mode
+ $30 constant TCCR2A_COM2A \ Compare Output Mode bits
+ $08 constant TCCR2A_WGM21 \ Waveform Generation Mode
+ $07 constant TCCR2A_CS2 \ Clock Select bits
+&178 constant TCNT2 \ Timer/Counter2
+&179 constant OCR2A \ Timer/Counter2 Output Compare Register
+&112 constant TIMSK2 \ Timer/Counter2 Interrupt Mask register
+ $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match Interrupt Enable
+ $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
+&55 constant TIFR2 \ Timer/Counter2 Interrupt Flag Register
+ $02 constant TIFR2_OCF2A \ Timer/Counter2 Output Compare Flag 2
+ $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
+&182 constant ASSR \ Asynchronous Status Register
+ $10 constant ASSR_EXCLK \ Enable External Clock Interrupt
+ $08 constant ASSR_AS2 \ AS2: Asynchronous Timer/Counter2
+ $04 constant ASSR_TCN2UB \ TCN2UB: Timer/Counter2 Update Busy
+ $02 constant ASSR_OCR2UB \ Output Compare Register2 Update Busy
+ $01 constant ASSR_TCR2UB \ TCR2UB: Timer/Counter Control Register2 Update Busy
+\ WATCHDOG
+&96 constant WDTCR \ Watchdog Timer Control Register
+ $10 constant WDTCR_WDCE \ Watchdog Change Enable
+ $08 constant WDTCR_WDE \ Watch Dog Enable
+ $07 constant WDTCR_WDP \ Watch Dog Timer Prescaler bits
+\ CPU
+&95 constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ $08 constant SREG_V \ Two's Complement Overflow Flag
+ $04 constant SREG_N \ Negative Flag
+ $02 constant SREG_Z \ Zero Flag
+ $01 constant SREG_C \ Carry Flag
+&93 constant SP \ Stack Pointer
+&102 constant OSCCAL \ Oscillator Calibration Value
+&97 constant CLKPR \ Clock Prescale Register
+ $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable
+ $0F constant CLKPR_CLKPS \ Clock Prescaler Select Bits
+&100 constant PRR \ Power Reduction Register
+ $08 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
+ $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
+ $02 constant PRR_PRUSART0 \ Power Reduction USART
+ $01 constant PRR_PRADC \ Power Reduction ADC
+&83 constant SMCR \ Sleep Mode Control Register
+ $0E constant SMCR_SM \ Sleep Mode Select bits
+ $01 constant SMCR_SE \ Sleep Enable
+&75 constant GPIOR2 \ General Purpose IO Register 2
+&74 constant GPIOR1 \ General Purpose IO Register 1
+&62 constant GPIOR0 \ General Purpose IO Register 0
+
+\ Interrupts
+&2 constant INT0Addr \ External Interrupt Request 0
+&4 constant PCINT0Addr \ Pin Change Interrupt Request 0
+&6 constant PCINT1Addr \ Pin Change Interrupt Request 1
+&8 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
+&10 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
+&12 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+&14 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
+&16 constant TIMER1_COMPBAddr \ Timer/Counter Compare Match B
+&18 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+&20 constant TIMER0_COMPAddr \ Timer/Counter0 Compare Match
+&22 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
+&24 constant SPI__STCAddr \ SPI Serial Transfer Complete
+&26 constant USART0__RXAddr \ USART0, Rx Complete
+&28 constant USART0__UDREAddr \ USART0 Data register Empty
+&30 constant USART0__TXAddr \ USART0, Tx Complete
+&32 constant USI_STARTAddr \ USI Start Condition
+&34 constant USI_OVERFLOWAddr \ USI Overflow
+&36 constant ANALOG_COMPAddr \ Analog Comparator
+&38 constant ADCAddr \ ADC Conversion Complete
+&40 constant EE_READYAddr \ EEPROM Ready
+&42 constant SPM_READYAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/atmega325/device.asm b/amforth-6.5/avr8/devices/atmega325/device.asm
new file mode 100644
index 0000000..e7713db
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega325/device.asm
@@ -0,0 +1,106 @@
+; Partname: ATmega325
+; generated automatically, do not edit
+
+.nolist
+ .include "m325def.inc"
+.list
+
+.equ ramstart = 256
+.equ CELLSIZE = 2
+.macro readflashcell
+ lsl zl
+ rol zh
+ lpm @0, Z+
+ lpm @1, Z+
+.endmacro
+.macro writeflashcell
+ lsl zl
+ rol zh
+.endmacro
+.set WANT_AD_CONVERTER = 0
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_USART0 = 0
+.set WANT_USI = 0
+.set WANT_SPI = 0
+.set WANT_BOOT_LOAD = 0
+.set WANT_JTAG = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_EEPROM = 0
+.set WANT_PORTA = 0
+.set WANT_PORTB = 0
+.set WANT_PORTC = 0
+.set WANT_PORTD = 0
+.set WANT_PORTE = 0
+.set WANT_PORTF = 0
+.set WANT_PORTG = 0
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_TIMER_COUNTER_2 = 0
+.set WANT_WATCHDOG = 0
+.set WANT_CPU = 0
+.equ intvecsize = 2 ; please verify; flash size: 32768 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.org 2
+ rcall isr ; External Interrupt Request 0
+.org 4
+ rcall isr ; Pin Change Interrupt Request 0
+.org 6
+ rcall isr ; Pin Change Interrupt Request 1
+.org 8
+ rcall isr ; Timer/Counter2 Compare Match
+.org 10
+ rcall isr ; Timer/Counter2 Overflow
+.org 12
+ rcall isr ; Timer/Counter1 Capture Event
+.org 14
+ rcall isr ; Timer/Counter1 Compare Match A
+.org 16
+ rcall isr ; Timer/Counter Compare Match B
+.org 18
+ rcall isr ; Timer/Counter1 Overflow
+.org 20
+ rcall isr ; Timer/Counter0 Compare Match
+.org 22
+ rcall isr ; Timer/Counter0 Overflow
+.org 24
+ rcall isr ; SPI Serial Transfer Complete
+.org 26
+ rcall isr ; USART0, Rx Complete
+.org 28
+ rcall isr ; USART0 Data register Empty
+.org 30
+ rcall isr ; USART0, Tx Complete
+.org 32
+ rcall isr ; USI Start Condition
+.org 34
+ rcall isr ; USI Overflow
+.org 36
+ rcall isr ; Analog Comparator
+.org 38
+ rcall isr ; ADC Conversion Complete
+.org 40
+ rcall isr ; EEPROM Ready
+.org 42
+ rcall isr ; Store Program Memory Read
+.equ INTVECTORS = 22
+.nooverlap
+
+; compatability layer (maybe empty)
+.equ EEPE = EEWE
+.equ EEMPE = EEMWE
+
+; controller data area, environment query mcu-info
+mcu_info:
+mcu_ramsize:
+ .dw 2048
+mcu_eepromsize:
+ .dw 1024
+mcu_maxdp:
+ .dw 28672
+mcu_numints:
+ .dw 22
+mcu_name:
+ .dw 9
+ .db "ATmega325",0
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega325/device.inc b/amforth-6.5/avr8/devices/atmega325/device.inc
new file mode 100644
index 0000000..e150e01
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega325/device.inc
@@ -0,0 +1,1050 @@
+; Partname: ATmega325
+; generated automatically, no not edit
+
+.if WANT_AD_CONVERTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC multiplexer Selection Register
+VE_ADMUX:
+ .dw $ff05
+ .db "ADMUX",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADMUX
+XT_ADMUX:
+ .dw PFA_DOVARIABLE
+PFA_ADMUX:
+ .dw 124
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register
+VE_ADCSRA:
+ .dw $ff06
+ .db "ADCSRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRA
+XT_ADCSRA:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRA:
+ .dw 122
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register Bytes
+VE_ADC:
+ .dw $ff03
+ .db "ADC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADC
+XT_ADC:
+ .dw PFA_DOVARIABLE
+PFA_ADC:
+ .dw 120
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Control and Status Register B
+VE_ADCSRB:
+ .dw $ff06
+ .db "ADCSRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRB
+XT_ADCSRB:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRB:
+ .dw 123
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 0
+VE_DIDR0:
+ .dw $ff05
+ .db "DIDR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR0
+XT_DIDR0:
+ .dw PFA_DOVARIABLE
+PFA_DIDR0:
+ .dw 126
+
+.endif
+.if WANT_ANALOG_COMPARATOR == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Control And Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw 80
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 1
+VE_DIDR1:
+ .dw $ff05
+ .db "DIDR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR1
+XT_DIDR1:
+ .dw PFA_DOVARIABLE
+PFA_DIDR1:
+ .dw 127
+
+.endif
+.if WANT_USART0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR0:
+ .dw $ff04
+ .db "UDR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR0
+XT_UDR0:
+ .dw PFA_DOVARIABLE
+PFA_UDR0:
+ .dw 198
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR0A:
+ .dw $ff06
+ .db "UCSR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0A
+XT_UCSR0A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0A:
+ .dw 192
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR0B:
+ .dw $ff06
+ .db "UCSR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0B
+XT_UCSR0B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0B:
+ .dw 193
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR0C:
+ .dw $ff06
+ .db "UCSR0C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0C
+XT_UCSR0C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0C:
+ .dw 194
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Bytes
+VE_UBRR0:
+ .dw $ff05
+ .db "UBRR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR0
+XT_UBRR0:
+ .dw PFA_DOVARIABLE
+PFA_UBRR0:
+ .dw 196
+
+.endif
+.if WANT_USI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USI Data Register
+VE_USIDR:
+ .dw $ff05
+ .db "USIDR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USIDR
+XT_USIDR:
+ .dw PFA_DOVARIABLE
+PFA_USIDR:
+ .dw 186
+; ( -- addr ) System Constant
+; R( -- )
+; USI Status Register
+VE_USISR:
+ .dw $ff05
+ .db "USISR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USISR
+XT_USISR:
+ .dw PFA_DOVARIABLE
+PFA_USISR:
+ .dw 185
+; ( -- addr ) System Constant
+; R( -- )
+; USI Control Register
+VE_USICR:
+ .dw $ff05
+ .db "USICR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USICR
+XT_USICR:
+ .dw PFA_DOVARIABLE
+PFA_USICR:
+ .dw 184
+
+.endif
+.if WANT_SPI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR:
+ .dw $ff04
+ .db "SPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR
+XT_SPCR:
+ .dw PFA_DOVARIABLE
+PFA_SPCR:
+ .dw 76
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR:
+ .dw $ff04
+ .db "SPSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR
+XT_SPSR:
+ .dw PFA_DOVARIABLE
+PFA_SPSR:
+ .dw 77
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR:
+ .dw $ff04
+ .db "SPDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR
+XT_SPDR:
+ .dw PFA_DOVARIABLE
+PFA_SPDR:
+ .dw 78
+
+.endif
+.if WANT_BOOT_LOAD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control Register
+VE_SPMCSR:
+ .dw $ff06
+ .db "SPMCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCSR
+XT_SPMCSR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCSR:
+ .dw 87
+
+.endif
+.if WANT_JTAG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; On-Chip Debug Related Register in I/O Memory
+VE_OCDR:
+ .dw $ff04
+ .db "OCDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCDR
+XT_OCDR:
+ .dw PFA_DOVARIABLE
+PFA_OCDR:
+ .dw 81
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw 85
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Status Register
+VE_MCUSR:
+ .dw $ff05
+ .db "MCUSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUSR
+XT_MCUSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUSR:
+ .dw 84
+
+.endif
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register A
+VE_EICRA:
+ .dw $ff05
+ .db "EICRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRA
+XT_EICRA:
+ .dw PFA_DOVARIABLE
+PFA_EICRA:
+ .dw 105
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Mask Register
+VE_EIMSK:
+ .dw $ff05
+ .db "EIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIMSK
+XT_EIMSK:
+ .dw PFA_DOVARIABLE
+PFA_EIMSK:
+ .dw 61
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Flag Register
+VE_EIFR:
+ .dw $ff04
+ .db "EIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIFR
+XT_EIFR:
+ .dw PFA_DOVARIABLE
+PFA_EIFR:
+ .dw 60
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 1
+VE_PCMSK1:
+ .dw $ff06
+ .db "PCMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK1
+XT_PCMSK1:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK1:
+ .dw 108
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 0
+VE_PCMSK0:
+ .dw $ff06
+ .db "PCMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK0
+XT_PCMSK0:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK0:
+ .dw 107
+
+.endif
+.if WANT_EEPROM == 1
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Read/Write Access Bytes
+VE_EEAR:
+ .dw $ff04
+ .db "EEAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEAR
+XT_EEAR:
+ .dw PFA_DOVARIABLE
+PFA_EEAR:
+ .dw 65
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw 64
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw 63
+
+.endif
+.if WANT_PORTA == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Register
+VE_PORTA:
+ .dw $ff05
+ .db "PORTA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTA
+XT_PORTA:
+ .dw PFA_DOVARIABLE
+PFA_PORTA:
+ .dw 34
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Direction Register
+VE_DDRA:
+ .dw $ff04
+ .db "DDRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRA
+XT_DDRA:
+ .dw PFA_DOVARIABLE
+PFA_DDRA:
+ .dw 33
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Input Pins
+VE_PINA:
+ .dw $ff04
+ .db "PINA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINA
+XT_PINA:
+ .dw PFA_DOVARIABLE
+PFA_PINA:
+ .dw 32
+
+.endif
+.if WANT_PORTB == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw 37
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw 36
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw 35
+
+.endif
+.if WANT_PORTC == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Register
+VE_PORTC:
+ .dw $ff05
+ .db "PORTC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTC
+XT_PORTC:
+ .dw PFA_DOVARIABLE
+PFA_PORTC:
+ .dw 40
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Direction Register
+VE_DDRC:
+ .dw $ff04
+ .db "DDRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRC
+XT_DDRC:
+ .dw PFA_DOVARIABLE
+PFA_DDRC:
+ .dw 39
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Input Pins
+VE_PINC:
+ .dw $ff04
+ .db "PINC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINC
+XT_PINC:
+ .dw PFA_DOVARIABLE
+PFA_PINC:
+ .dw 38
+
+.endif
+.if WANT_PORTD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw 43
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw 42
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw 41
+
+.endif
+.if WANT_PORTE == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port E
+VE_PORTE:
+ .dw $ff05
+ .db "PORTE",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTE
+XT_PORTE:
+ .dw PFA_DOVARIABLE
+PFA_PORTE:
+ .dw 46
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port E
+VE_DDRE:
+ .dw $ff04
+ .db "DDRE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRE
+XT_DDRE:
+ .dw PFA_DOVARIABLE
+PFA_DDRE:
+ .dw 45
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port E
+VE_PINE:
+ .dw $ff04
+ .db "PINE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINE
+XT_PINE:
+ .dw PFA_DOVARIABLE
+PFA_PINE:
+ .dw 44
+
+.endif
+.if WANT_PORTF == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port F
+VE_PORTF:
+ .dw $ff05
+ .db "PORTF",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTF
+XT_PORTF:
+ .dw PFA_DOVARIABLE
+PFA_PORTF:
+ .dw 49
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port F
+VE_DDRF:
+ .dw $ff04
+ .db "DDRF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRF
+XT_DDRF:
+ .dw PFA_DOVARIABLE
+PFA_DDRF:
+ .dw 48
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port F
+VE_PINF:
+ .dw $ff04
+ .db "PINF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINF
+XT_PINF:
+ .dw PFA_DOVARIABLE
+PFA_PINF:
+ .dw 47
+
+.endif
+.if WANT_PORTG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Data Register
+VE_PORTG:
+ .dw $ff05
+ .db "PORTG",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTG
+XT_PORTG:
+ .dw PFA_DOVARIABLE
+PFA_PORTG:
+ .dw 52
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Data Direction Register
+VE_DDRG:
+ .dw $ff04
+ .db "DDRG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRG
+XT_DDRG:
+ .dw PFA_DOVARIABLE
+PFA_DDRG:
+ .dw 51
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Input Pins
+VE_PING:
+ .dw $ff04
+ .db "PING"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PING
+XT_PING:
+ .dw PFA_DOVARIABLE
+PFA_PING:
+ .dw 50
+
+.endif
+.if WANT_TIMER_COUNTER_0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Control Register
+VE_TCCR0A:
+ .dw $ff06
+ .db "TCCR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0A
+XT_TCCR0A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0A:
+ .dw 68
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw 70
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0A:
+ .dw $ff05
+ .db "OCR0A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0A
+XT_OCR0A:
+ .dw PFA_DOVARIABLE
+PFA_OCR0A:
+ .dw 71
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Mask Register
+VE_TIMSK0:
+ .dw $ff06
+ .db "TIMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK0
+XT_TIMSK0:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK0:
+ .dw 110
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Flag register
+VE_TIFR0:
+ .dw $ff05
+ .db "TIFR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR0
+XT_TIFR0:
+ .dw PFA_DOVARIABLE
+PFA_TIFR0:
+ .dw 53
+; ( -- addr ) System Constant
+; R( -- )
+; General Timer/Control Register
+VE_GTCCR:
+ .dw $ff05
+ .db "GTCCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GTCCR
+XT_GTCCR:
+ .dw PFA_DOVARIABLE
+PFA_GTCCR:
+ .dw 67
+
+.endif
+.if WANT_TIMER_COUNTER_1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw 128
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw 129
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter 1 Control Register C
+VE_TCCR1C:
+ .dw $ff06
+ .db "TCCR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1C
+XT_TCCR1C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1C:
+ .dw 130
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Bytes
+VE_TCNT1:
+ .dw $ff05
+ .db "TCNT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1
+XT_TCNT1:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1:
+ .dw 132
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register A Bytes
+VE_OCR1A:
+ .dw $ff05
+ .db "OCR1A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1A
+XT_OCR1A:
+ .dw PFA_DOVARIABLE
+PFA_OCR1A:
+ .dw 136
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register B Bytes
+VE_OCR1B:
+ .dw $ff05
+ .db "OCR1B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1B
+XT_OCR1B:
+ .dw PFA_DOVARIABLE
+PFA_OCR1B:
+ .dw 138
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Bytes
+VE_ICR1:
+ .dw $ff04
+ .db "ICR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1
+XT_ICR1:
+ .dw PFA_DOVARIABLE
+PFA_ICR1:
+ .dw 134
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Mask Register
+VE_TIMSK1:
+ .dw $ff06
+ .db "TIMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK1
+XT_TIMSK1:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK1:
+ .dw 111
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Flag register
+VE_TIFR1:
+ .dw $ff05
+ .db "TIFR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR1
+XT_TIFR1:
+ .dw PFA_DOVARIABLE
+PFA_TIFR1:
+ .dw 54
+
+.endif
+.if WANT_TIMER_COUNTER_2 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register
+VE_TCCR2A:
+ .dw $ff06
+ .db "TCCR2A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2A
+XT_TCCR2A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2A:
+ .dw 176
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2
+VE_TCNT2:
+ .dw $ff05
+ .db "TCNT2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT2
+XT_TCNT2:
+ .dw PFA_DOVARIABLE
+PFA_TCNT2:
+ .dw 178
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register
+VE_OCR2A:
+ .dw $ff05
+ .db "OCR2A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2A
+XT_OCR2A:
+ .dw PFA_DOVARIABLE
+PFA_OCR2A:
+ .dw 179
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Interrupt Mask register
+VE_TIMSK2:
+ .dw $ff06
+ .db "TIMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK2
+XT_TIMSK2:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK2:
+ .dw 112
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Interrupt Flag Register
+VE_TIFR2:
+ .dw $ff05
+ .db "TIFR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR2
+XT_TIFR2:
+ .dw PFA_DOVARIABLE
+PFA_TIFR2:
+ .dw 55
+; ( -- addr ) System Constant
+; R( -- )
+; Asynchronous Status Register
+VE_ASSR:
+ .dw $ff04
+ .db "ASSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ASSR
+XT_ASSR:
+ .dw PFA_DOVARIABLE
+PFA_ASSR:
+ .dw 182
+
+.endif
+.if WANT_WATCHDOG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCR:
+ .dw $ff05
+ .db "WDTCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCR
+XT_WDTCR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCR:
+ .dw 96
+
+.endif
+.if WANT_CPU == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw 95
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer
+VE_SP:
+ .dw $ff02
+ .db "SP"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SP
+XT_SP:
+ .dw PFA_DOVARIABLE
+PFA_SP:
+ .dw 93
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Calibration Value
+VE_OSCCAL:
+ .dw $ff06
+ .db "OSCCAL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSCCAL
+XT_OSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_OSCCAL:
+ .dw 102
+; ( -- addr ) System Constant
+; R( -- )
+; Clock Prescale Register
+VE_CLKPR:
+ .dw $ff05
+ .db "CLKPR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKPR
+XT_CLKPR:
+ .dw PFA_DOVARIABLE
+PFA_CLKPR:
+ .dw 97
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register
+VE_PRR:
+ .dw $ff03
+ .db "PRR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR
+XT_PRR:
+ .dw PFA_DOVARIABLE
+PFA_PRR:
+ .dw 100
+; ( -- addr ) System Constant
+; R( -- )
+; Sleep Mode Control Register
+VE_SMCR:
+ .dw $ff04
+ .db "SMCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SMCR
+XT_SMCR:
+ .dw PFA_DOVARIABLE
+PFA_SMCR:
+ .dw 83
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 2
+VE_GPIOR2:
+ .dw $ff06
+ .db "GPIOR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR2
+XT_GPIOR2:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR2:
+ .dw 75
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 1
+VE_GPIOR1:
+ .dw $ff06
+ .db "GPIOR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR1
+XT_GPIOR1:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR1:
+ .dw 74
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 0
+VE_GPIOR0:
+ .dw $ff06
+ .db "GPIOR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR0
+XT_GPIOR0:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR0:
+ .dw 62
+
+.endif
diff --git a/amforth-6.5/avr8/devices/atmega325/device.py b/amforth-6.5/avr8/devices/atmega325/device.py
new file mode 100644
index 0000000..433c5ca
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega325/device.py
@@ -0,0 +1,317 @@
+# Generated Automatically
+
+# Partname ATmega325
+
+MCUREGS = {
+# Interrupt Vectors
+ 'INT0Addr' : '#2', # External Interrupt Request 0
+ 'PCINT0Addr' : '#4', # Pin Change Interrupt Request 0
+ 'PCINT1Addr' : '#6', # Pin Change Interrupt Request 1
+ 'TIMER2_COMPAddr' : '#8', # Timer/Counter2 Compare Match
+ 'TIMER2_OVFAddr' : '#10', # Timer/Counter2 Overflow
+ 'TIMER1_CAPTAddr' : '#12', # Timer/Counter1 Capture Event
+ 'TIMER1_COMPAAddr' : '#14', # Timer/Counter1 Compare Match A
+ 'TIMER1_COMPBAddr' : '#16', # Timer/Counter Compare Match B
+ 'TIMER1_OVFAddr' : '#18', # Timer/Counter1 Overflow
+ 'TIMER0_COMPAddr' : '#20', # Timer/Counter0 Compare Match
+ 'TIMER0_OVFAddr' : '#22', # Timer/Counter0 Overflow
+ 'SPI_STCAddr' : '#24', # SPI Serial Transfer Complete
+ 'USART0_RXAddr' : '#26', # USART0, Rx Complete
+ 'USART0_UDREAddr' : '#28', # USART0 Data register Empty
+ 'USART0_TXAddr' : '#30', # USART0, Tx Complete
+ 'USI_STARTAddr' : '#32', # USI Start Condition
+ 'USI_OVERFLOWAddr' : '#34', # USI Overflow
+ 'ANALOG_COMPAddr' : '#36', # Analog Comparator
+ 'ADCAddr' : '#38', # ADC Conversion Complete
+ 'EE_READYAddr' : '#40', # EEPROM Ready
+ 'SPM_READYAddr' : '#42', # Store Program Memory Read
+
+# Module AD_CONVERTER
+ 'ADMUX' : '$7c', # The ADC multiplexer Selection
+ 'ADMUX_REFS': '$c0', # Reference Selection Bits
+ 'ADMUX_ADLAR': '$20', # Left Adjust Result
+ 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
+ 'ADCSRA' : '$7a', # The ADC Control and Status reg
+ 'ADCSRA_ADEN': '$80', # ADC Enable
+ 'ADCSRA_ADSC': '$40', # ADC Start Conversion
+ 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
+ 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
+ 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
+ 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
+ 'ADC' : '$78', # ADC Data Register Bytes
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Sources
+ 'DIDR0' : '$7e', # Digital Input Disable Register
+ 'DIDR0_ADC7D': '$80', # ADC7 Digital input Disable
+ 'DIDR0_ADC6D': '$40', # ADC6 Digital input Disable
+ 'DIDR0_ADC5D': '$20', # ADC5 Digital input Disable
+ 'DIDR0_ADC4D': '$10', # ADC4 Digital input Disable
+ 'DIDR0_ADC3D': '$8', # ADC3 Digital input Disable
+ 'DIDR0_ADC2D': '$4', # ADC2 Digital input Disable
+ 'DIDR0_ADC1D': '$2', # ADC1 Digital input Disable
+ 'DIDR0_ADC0D': '$1', # ADC0 Digital input Disable
+
+# Module ANALOG_COMPARATOR
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
+ 'ACSR' : '$50', # Analog Comparator Control And
+ 'ACSR_ACD': '$80', # Analog Comparator Disable
+ 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
+ 'ACSR_ACO': '$20', # Analog Compare Output
+ 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
+ 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
+ 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
+ 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
+ 'DIDR1' : '$7f', # Digital Input Disable Register
+ 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
+ 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
+
+# Module USART0
+ 'UDR0' : '$c6', # USART I/O Data Register
+ 'UCSR0A' : '$c0', # USART Control and Status Regis
+ 'UCSR0A_RXC0': '$80', # USART Receive Complete
+ 'UCSR0A_TXC0': '$40', # USART Transmit Complete
+ 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
+ 'UCSR0A_FE0': '$10', # Framing Error
+ 'UCSR0A_DOR0': '$8', # Data OverRun
+ 'UCSR0A_UPE0': '$4', # USART Parity Error
+ 'UCSR0A_U2X0': '$2', # Double the USART Transmission
+ 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
+ 'UCSR0B' : '$c1', # USART Control and Status Regis
+ 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
+ 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
+ 'UCSR0B_UDRIE0': '$20', # USART Data Register Empty Inte
+ 'UCSR0B_RXEN0': '$10', # Receiver Enable
+ 'UCSR0B_TXEN0': '$8', # Transmitter Enable
+ 'UCSR0B_UCSZ02': '$4', # Character Size
+ 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
+ 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
+ 'UCSR0C' : '$c2', # USART Control and Status Regis
+ 'UCSR0C_UMSEL0': '$40', # USART Mode Select
+ 'UCSR0C_UPM0': '$30', # Parity Mode Bits
+ 'UCSR0C_USBS0': '$8', # Stop Bit Select
+ 'UCSR0C_UCSZ0': '$6', # Character Size
+ 'UCSR0C_UCPOL0': '$1', # Clock Polarity
+ 'UBRR0' : '$c4', # USART Baud Rate Register Byte
+
+# Module USI
+ 'USIDR' : '$ba', # USI Data Register
+ 'USISR' : '$b9', # USI Status Register
+ 'USISR_USISIF': '$80', # Start Condition Interrupt Flag
+ 'USISR_USIOIF': '$40', # Counter Overflow Interrupt Fla
+ 'USISR_USIPF': '$20', # Stop Condition Flag
+ 'USISR_USIDC': '$10', # Data Output Collision
+ 'USISR_USICNT': '$f', # USI Counter Value Bits
+ 'USICR' : '$b8', # USI Control Register
+ 'USICR_USISIE': '$80', # Start Condition Interrupt Enab
+ 'USICR_USIOIE': '$40', # Counter Overflow Interrupt Ena
+ 'USICR_USIWM': '$30', # USI Wire Mode Bits
+ 'USICR_USICS': '$c', # USI Clock Source Select Bits
+ 'USICR_USICLK': '$2', # Clock Strobe
+ 'USICR_USITC': '$1', # Toggle Clock Port Pin
+
+# Module SPI
+ 'SPCR' : '$4c', # SPI Control Register
+ 'SPCR_SPIE': '$80', # SPI Interrupt Enable
+ 'SPCR_SPE': '$40', # SPI Enable
+ 'SPCR_DORD': '$20', # Data Order
+ 'SPCR_MSTR': '$10', # Master/Slave Select
+ 'SPCR_CPOL': '$8', # Clock polarity
+ 'SPCR_CPHA': '$4', # Clock Phase
+ 'SPCR_SPR': '$3', # SPI Clock Rate Selects
+ 'SPSR' : '$4d', # SPI Status Register
+ 'SPSR_SPIF': '$80', # SPI Interrupt Flag
+ 'SPSR_WCOL': '$40', # Write Collision Flag
+ 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
+ 'SPDR' : '$4e', # SPI Data Register
+
+# Module BOOT_LOAD
+ 'SPMCSR' : '$57', # Store Program Memory Control R
+ 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
+ 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
+ 'SPMCSR_RWWSRE': '$10', # Read While Write section read
+ 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
+ 'SPMCSR_PGWRT': '$4', # Page Write
+ 'SPMCSR_PGERS': '$2', # Page Erase
+ 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
+
+# Module JTAG
+ 'OCDR' : '$51', # On-Chip Debug Related Register
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_JTD': '$80', # JTAG Interface Disable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+
+# Module EXTERNAL_INTERRUPT
+ 'EICRA' : '$69', # External Interrupt Control Reg
+ 'EICRA_ISC01': '$2', # External Interrupt Sense Contr
+ 'EICRA_ISC00': '$1', # External Interrupt Sense Contr
+ 'EIMSK' : '$3d', # External Interrupt Mask Regist
+ 'EIMSK_PCIE': '$f0', # Pin Change Interrupt Enables
+ 'EIMSK_INT0': '$1', # External Interrupt Request 0 E
+ 'EIFR' : '$3c', # External Interrupt Flag Regist
+ 'EIFR_PCIF': '$f0', # Pin Change Interrupt Flags
+ 'EIFR_INTF0': '$1', # External Interrupt Flag 0
+ 'PCMSK1' : '$6c', # Pin Change Mask Register 1
+ 'PCMSK0' : '$6b', # Pin Change Mask Register 0
+
+# Module EEPROM
+ 'EEAR' : '$41', # EEPROM Read/Write Access Byte
+ 'EEDR' : '$40', # EEPROM Data Register
+ 'EECR' : '$3f', # EEPROM Control Register
+ 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
+ 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
+ 'EECR_EEWE': '$2', # EEPROM Write Enable
+ 'EECR_EERE': '$1', # EEPROM Read Enable
+
+# Module PORTA
+ 'PORTA' : '$22', # Port A Data Register
+ 'DDRA' : '$21', # Port A Data Direction Register
+ 'PINA' : '$20', # Port A Input Pins
+
+# Module PORTB
+ 'PORTB' : '$25', # Port B Data Register
+ 'DDRB' : '$24', # Port B Data Direction Register
+ 'PINB' : '$23', # Port B Input Pins
+
+# Module PORTC
+ 'PORTC' : '$28', # Port C Data Register
+ 'DDRC' : '$27', # Port C Data Direction Register
+ 'PINC' : '$26', # Port C Input Pins
+
+# Module PORTD
+ 'PORTD' : '$2b', # Port D Data Register
+ 'DDRD' : '$2a', # Port D Data Direction Register
+ 'PIND' : '$29', # Port D Input Pins
+
+# Module PORTE
+ 'PORTE' : '$2e', # Data Register, Port E
+ 'DDRE' : '$2d', # Data Direction Register, Port
+ 'PINE' : '$2c', # Input Pins, Port E
+
+# Module PORTF
+ 'PORTF' : '$31', # Data Register, Port F
+ 'DDRF' : '$30', # Data Direction Register, Port
+ 'PINF' : '$2f', # Input Pins, Port F
+
+# Module PORTG
+ 'PORTG' : '$34', # Port G Data Register
+ 'DDRG' : '$33', # Port G Data Direction Register
+ 'PING' : '$32', # Port G Input Pins
+
+# Module TIMER_COUNTER_0
+ 'TCCR0A' : '$44', # Timer/Counter0 Control Registe
+ 'TCCR0A_FOC0A': '$80', # Force Output Compare
+ 'TCCR0A_WGM00': '$40', # Waveform Generation Mode 0
+ 'TCCR0A_COM0A': '$30', # Compare Match Output Modes
+ 'TCCR0A_WGM01': '$8', # Waveform Generation Mode 1
+ 'TCCR0A_CS0': '$7', # Clock Selects
+ 'TCNT0' : '$46', # Timer/Counter0
+ 'OCR0A' : '$47', # Timer/Counter0 Output Compare
+ 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
+ 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
+ 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
+ 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
+ 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
+ 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Control Register
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSR310': '$1', # Prescaler Reset Timer/Counter1
+
+# Module TIMER_COUNTER_1
+ 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
+ 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
+ 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
+ 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
+ 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
+ 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
+ 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
+ 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
+ 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
+ 'TCCR1C' : '$82', # Timer/Counter 1 Control Regist
+ 'TCCR1C_FOC1A': '$80', # Force Output Compare 1A
+ 'TCCR1C_FOC1B': '$40', # Force Output Compare 1B
+ 'TCNT1' : '$84', # Timer/Counter1 Bytes
+ 'OCR1A' : '$88', # Timer/Counter1 Output Compare
+ 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
+ 'ICR1' : '$86', # Timer/Counter1 Input Capture R
+ 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
+ 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
+ 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
+ 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
+ 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
+ 'TIFR1' : '$36', # Timer/Counter1 Interrupt Flag
+ 'TIFR1_ICF1': '$20', # Input Capture Flag 1
+ 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
+ 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
+ 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
+
+# Module TIMER_COUNTER_2
+ 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
+ 'TCCR2A_FOC2A': '$80', # Force Output Compare A
+ 'TCCR2A_WGM20': '$40', # Waveform Generation Mode
+ 'TCCR2A_COM2A': '$30', # Compare Output Mode bits
+ 'TCCR2A_WGM21': '$8', # Waveform Generation Mode
+ 'TCCR2A_CS2': '$7', # Clock Select bits
+ 'TCNT2' : '$b2', # Timer/Counter2
+ 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
+ 'TIMSK2' : '$70', # Timer/Counter2 Interrupt Mask
+ 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
+ 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
+ 'TIFR2' : '$37', # Timer/Counter2 Interrupt Flag
+ 'TIFR2_OCF2A': '$2', # Timer/Counter2 Output Compare
+ 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_PSR2': '$2', # Prescaler Reset Timer/Counter2
+ 'ASSR' : '$b6', # Asynchronous Status Register
+ 'ASSR_EXCLK': '$10', # Enable External Clock Interrup
+ 'ASSR_AS2': '$8', # AS2: Asynchronous Timer/Counte
+ 'ASSR_TCN2UB': '$4', # TCN2UB: Timer/Counter2 Update
+ 'ASSR_OCR2UB': '$2', # Output Compare Register2 Updat
+ 'ASSR_TCR2UB': '$1', # TCR2UB: Timer/Counter Control
+
+# Module WATCHDOG
+ 'WDTCR' : '$60', # Watchdog Timer Control Registe
+ 'WDTCR_WDCE': '$10', # Watchdog Change Enable
+ 'WDTCR_WDE': '$8', # Watch Dog Enable
+ 'WDTCR_WDP': '$7', # Watch Dog Timer Prescaler bits
+
+# Module CPU
+ 'SREG' : '$5f', # Status Register
+ 'SREG_I': '$80', # Global Interrupt Enable
+ 'SREG_T': '$40', # Bit Copy Storage
+ 'SREG_H': '$20', # Half Carry Flag
+ 'SREG_S': '$10', # Sign Bit
+ 'SREG_V': '$8', # Two's Complement Overflow Flag
+ 'SREG_N': '$4', # Negative Flag
+ 'SREG_Z': '$2', # Zero Flag
+ 'SREG_C': '$1', # Carry Flag
+ 'SP' : '$5d', # Stack Pointer
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_PUD': '$10', # Pull-up disable
+ 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
+ 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+ 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
+ 'MCUSR_BORF': '$4', # Brown-out Reset Flag
+ 'MCUSR_EXTRF': '$2', # External Reset Flag
+ 'MCUSR_PORF': '$1', # Power-on reset flag
+ 'OSCCAL' : '$66', # Oscillator Calibration Value
+ 'CLKPR' : '$61', # Clock Prescale Register
+ 'CLKPR_CLKPCE': '$80', # Clock Prescaler Change Enable
+ 'CLKPR_CLKPS': '$f', # Clock Prescaler Select Bits
+ 'PRR' : '$64', # Power Reduction Register
+ 'PRR_PRTIM1': '$8', # Power Reduction Timer/Counter1
+ 'PRR_PRSPI': '$4', # Power Reduction Serial Periphe
+ 'PRR_PRUSART0': '$2', # Power Reduction USART
+ 'PRR_PRADC': '$1', # Power Reduction ADC
+ 'SMCR' : '$53', # Sleep Mode Control Register
+ 'SMCR_SM': '$e', # Sleep Mode Select bits
+ 'SMCR_SE': '$1', # Sleep Enable
+ 'GPIOR2' : '$4b', # General Purpose IO Register 2
+ 'GPIOR1' : '$4a', # General Purpose IO Register 1
+ 'GPIOR0' : '$3e', # General Purpose IO Register 0
+
+ '__amforth_dummy':'0'
+}
diff --git a/amforth-6.5/avr8/devices/atmega325/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega325/words/no-jtag.asm
new file mode 100644
index 0000000..352a4bb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega325/words/no-jtag.asm
@@ -0,0 +1,14 @@
+; ( -- )
+; ( -- )
+; MCU
+; disable jtag at runtime
+VE_NOJTAG:
+ .dw $FF05
+ .db "-jtag",0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOJTAG
+XT_NOJTAG:
+ .dw PFA_NOJTAG
+PFA_NOJTAG:
+
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega325/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega325/words/no-wdt.asm
new file mode 100644
index 0000000..4a12261
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega325/words/no-wdt.asm
@@ -0,0 +1,22 @@
+; ( -- )
+; MCU
+; disable watch dog timer at runtime
+VE_NOWDT:
+ .dw $ff04
+ .db "-wdt"
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOWDT
+XT_NOWDT:
+ .dw PFA_NOWDT
+PFA_NOWDT:
+
+; Reset WDT
+ wdr
+; Write logical one to WDTOE and WDE
+ in_ temp1, WDTCR
+ ori temp1, (1<<WDTOE)|(1<<WDE)
+ out WDTCR, temp1
+; Turn off WDT
+ ldi temp1, (0<<WDE)
+ out_ WDTCR, temp1
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega325/words/sleep.asm b/amforth-6.5/avr8/devices/atmega325/words/sleep.asm
new file mode 100644
index 0000000..256249c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega325/words/sleep.asm
@@ -0,0 +1,19 @@
+; ( mode -- )
+; MCU
+; put the controller into the specified sleep mode
+VE_SLEEP:
+ .dw $ff05
+ .db "sleep", 0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_SLEEP
+XT_SLEEP:
+ .dw PFA_SLEEP
+PFA_SLEEP:
+ andi tosl, 7 ; leave only legal mode bits
+ lsl tosl ; move to correct location (bits 3-1)
+ ori tosl, 1 ; set the SE bit
+ out_ SMCR, tosl ; set the sleep config
+ sleep ; nighty-night
+ out_ SMCR, zerol ; 0 protects against accidental sleeps
+ loadtos ; pop argument from stack
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega3250/atmega3250.frt b/amforth-6.5/avr8/devices/atmega3250/atmega3250.frt
new file mode 100644
index 0000000..93c4b3f
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega3250/atmega3250.frt
@@ -0,0 +1,292 @@
+\ Partname: ATmega3250
+\ generated automatically
+
+\ TIMER_COUNTER_0
+&68 constant TCCR0A \ Timer/Counter0 Control Register
+ $80 constant TCCR0A_FOC0A \ Force Output Compare
+ $40 constant TCCR0A_WGM00 \ Waveform Generation Mode 0
+ $30 constant TCCR0A_COM0A \ Compare Match Output Modes
+ $08 constant TCCR0A_WGM01 \ Waveform Generation Mode 1
+ $07 constant TCCR0A_CS0 \ Clock Selects
+&70 constant TCNT0 \ Timer/Counter0
+&71 constant OCR0A \ Timer/Counter0 Output Compare Register
+&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
+ $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match Interrupt Enable
+ $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
+&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
+ $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0
+ $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
+&67 constant GTCCR \ General Timer/Control Register
+ $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
+ $01 constant GTCCR_PSR310 \ Prescaler Reset Timer/Counter1 and Timer/Counter0
+\ TIMER_COUNTER_1
+&128 constant TCCR1A \ Timer/Counter1 Control Register A
+ $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
+ $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
+ $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
+&129 constant TCCR1B \ Timer/Counter1 Control Register B
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
+ $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
+&130 constant TCCR1C \ Timer/Counter 1 Control Register C
+ $80 constant TCCR1C_FOC1A \ Force Output Compare 1A
+ $40 constant TCCR1C_FOC1B \ Force Output Compare 1B
+&132 constant TCNT1 \ Timer/Counter1 Bytes
+&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
+&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
+&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
+&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
+ $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
+ $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
+ $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
+ $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
+&54 constant TIFR1 \ Timer/Counter1 Interrupt Flag register
+ $20 constant TIFR1_ICF1 \ Input Capture Flag 1
+ $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
+ $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
+ $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
+\ TIMER_COUNTER_2
+&176 constant TCCR2A \ Timer/Counter2 Control Register
+ $80 constant TCCR2A_FOC2A \ Force Output Compare A
+ $40 constant TCCR2A_WGM20 \ Waveform Generation Mode
+ $30 constant TCCR2A_COM2A \ Compare Output Mode bits
+ $08 constant TCCR2A_WGM21 \ Waveform Generation Mode
+ $07 constant TCCR2A_CS2 \ Clock Select bits
+&178 constant TCNT2 \ Timer/Counter2
+&179 constant OCR2A \ Timer/Counter2 Output Compare Register
+&112 constant TIMSK2 \ Timer/Counter2 Interrupt Mask register
+ $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match Interrupt Enable
+ $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
+&55 constant TIFR2 \ Timer/Counter2 Interrupt Flag Register
+ $02 constant TIFR2_OCF2A \ Timer/Counter2 Output Compare Flag 2
+ $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
+&182 constant ASSR \ Asynchronous Status Register
+ $10 constant ASSR_EXCLK \ Enable External Clock Interrupt
+ $08 constant ASSR_AS2 \ AS2: Asynchronous Timer/Counter2
+ $04 constant ASSR_TCN2UB \ TCN2UB: Timer/Counter2 Update Busy
+ $02 constant ASSR_OCR2UB \ Output Compare Register2 Update Busy
+ $01 constant ASSR_TCR2UB \ TCR2UB: Timer/Counter Control Register2 Update Busy
+\ WATCHDOG
+&96 constant WDTCR \ Watchdog Timer Control Register
+ $10 constant WDTCR_WDCE \ Watchdog Change Enable
+ $08 constant WDTCR_WDE \ Watch Dog Enable
+ $07 constant WDTCR_WDP \ Watch Dog Timer Prescaler bits
+\ EEPROM
+&65 constant EEAR \ EEPROM Read/Write Access Bytes
+&64 constant EEDR \ EEPROM Data Register
+&63 constant EECR \ EEPROM Control Register
+ $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
+ $04 constant EECR_EEMWE \ EEPROM Master Write Enable
+ $02 constant EECR_EEWE \ EEPROM Write Enable
+ $01 constant EECR_EERE \ EEPROM Read Enable
+\ SPI
+&76 constant SPCR \ SPI Control Register
+ $80 constant SPCR_SPIE \ SPI Interrupt Enable
+ $40 constant SPCR_SPE \ SPI Enable
+ $20 constant SPCR_DORD \ Data Order
+ $10 constant SPCR_MSTR \ Master/Slave Select
+ $08 constant SPCR_CPOL \ Clock polarity
+ $04 constant SPCR_CPHA \ Clock Phase
+ $03 constant SPCR_SPR \ SPI Clock Rate Selects
+&77 constant SPSR \ SPI Status Register
+ $80 constant SPSR_SPIF \ SPI Interrupt Flag
+ $40 constant SPSR_WCOL \ Write Collision Flag
+ $01 constant SPSR_SPI2X \ Double SPI Speed Bit
+&78 constant SPDR \ SPI Data Register
+\ PORTA
+&34 constant PORTA \ Port A Data Register
+&33 constant DDRA \ Port A Data Direction Register
+&32 constant PINA \ Port A Input Pins
+\ PORTB
+&37 constant PORTB \ Port B Data Register
+&36 constant DDRB \ Port B Data Direction Register
+&35 constant PINB \ Port B Input Pins
+\ PORTC
+&40 constant PORTC \ Port C Data Register
+&39 constant DDRC \ Port C Data Direction Register
+&38 constant PINC \ Port C Input Pins
+\ PORTD
+&43 constant PORTD \ Port D Data Register
+&42 constant DDRD \ Port D Data Direction Register
+&41 constant PIND \ Port D Input Pins
+\ ANALOG_COMPARATOR
+&123 constant ADCSRB \ ADC Control and Status Register B
+ $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer Enable
+&80 constant ACSR \ Analog Comparator Control And Status Register
+ $80 constant ACSR_ACD \ Analog Comparator Disable
+ $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
+ $20 constant ACSR_ACO \ Analog Compare Output
+ $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
+ $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
+ $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
+ $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
+&127 constant DIDR1 \ Digital Input Disable Register 1
+ $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
+ $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
+\ PORTE
+&46 constant PORTE \ Data Register, Port E
+&45 constant DDRE \ Data Direction Register, Port E
+&44 constant PINE \ Input Pins, Port E
+\ PORTF
+&49 constant PORTF \ Data Register, Port F
+&48 constant DDRF \ Data Direction Register, Port F
+&47 constant PINF \ Input Pins, Port F
+\ PORTG
+&52 constant PORTG \ Port G Data Register
+&51 constant DDRG \ Port G Data Direction Register
+&50 constant PING \ Port G Input Pins
+\ JTAG
+&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
+&85 constant MCUCR \ MCU Control Register
+ $80 constant MCUCR_JTD \ JTAG Interface Disable
+&84 constant MCUSR \ MCU Status Register
+ $10 constant MCUSR_JTRF \ JTAG Reset Flag
+\ EXTERNAL_INTERRUPT
+&105 constant EICRA \ External Interrupt Control Register A
+ $02 constant EICRA_ISC01 \ External Interrupt Sense Control 0 Bit 1
+ $01 constant EICRA_ISC00 \ External Interrupt Sense Control 0 Bit 0
+&61 constant EIMSK \ External Interrupt Mask Register
+ $F0 constant EIMSK_PCIE \ Pin Change Interrupt Enables
+ $01 constant EIMSK_INT0 \ External Interrupt Request 0 Enable
+&60 constant EIFR \ External Interrupt Flag Register
+ $F0 constant EIFR_PCIF \ Pin Change Interrupt Flags
+ $01 constant EIFR_INTF0 \ External Interrupt Flag 0
+&115 constant PCMSK3 \ Pin Change Mask Register 3
+&109 constant PCMSK2 \ Pin Change Mask Register 2
+&108 constant PCMSK1 \ Pin Change Mask Register 1
+&107 constant PCMSK0 \ Pin Change Mask Register 0
+\ CPU
+&95 constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ $08 constant SREG_V \ Two's Complement Overflow Flag
+ $04 constant SREG_N \ Negative Flag
+ $02 constant SREG_Z \ Zero Flag
+ $01 constant SREG_C \ Carry Flag
+&93 constant SP \ Stack Pointer
+&102 constant OSCCAL \ Oscillator Calibration Value
+&97 constant CLKPR \ Clock Prescale Register
+ $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable
+ $0F constant CLKPR_CLKPS \ Clock Prescaler Select Bits
+&100 constant PRR \ Power Reduction Register
+ $10 constant PRR_PRLCD \ Power Reduction LCD
+ $08 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
+ $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
+ $02 constant PRR_PRUSART0 \ Power Reduction USART
+ $01 constant PRR_PRADC \ Power Reduction ADC
+&83 constant SMCR \ Sleep Mode Control Register
+ $0E constant SMCR_SM \ Sleep Mode Select bits
+ $01 constant SMCR_SE \ Sleep Enable
+&75 constant GPIOR2 \ General Purpose IO Register 2
+&74 constant GPIOR1 \ General Purpose IO Register 1
+&62 constant GPIOR0 \ General Purpose IO Register 0
+\ USI
+&186 constant USIDR \ USI Data Register
+&185 constant USISR \ USI Status Register
+ $80 constant USISR_USISIF \ Start Condition Interrupt Flag
+ $40 constant USISR_USIOIF \ Counter Overflow Interrupt Flag
+ $20 constant USISR_USIPF \ Stop Condition Flag
+ $10 constant USISR_USIDC \ Data Output Collision
+ $0F constant USISR_USICNT \ USI Counter Value Bits
+&184 constant USICR \ USI Control Register
+ $80 constant USICR_USISIE \ Start Condition Interrupt Enable
+ $40 constant USICR_USIOIE \ Counter Overflow Interrupt Enable
+ $30 constant USICR_USIWM \ USI Wire Mode Bits
+ $0C constant USICR_USICS \ USI Clock Source Select Bits
+ $02 constant USICR_USICLK \ Clock Strobe
+ $01 constant USICR_USITC \ Toggle Clock Port Pin
+\ AD_CONVERTER
+&124 constant ADMUX \ The ADC multiplexer Selection Register
+ $C0 constant ADMUX_REFS \ Reference Selection Bits
+ $20 constant ADMUX_ADLAR \ Left Adjust Result
+ $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
+&122 constant ADCSRA \ The ADC Control and Status register
+ $80 constant ADCSRA_ADEN \ ADC Enable
+ $40 constant ADCSRA_ADSC \ ADC Start Conversion
+ $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
+ $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
+ $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
+ $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
+&120 constant ADC \ ADC Data Register Bytes
+&126 constant DIDR0 \ Digital Input Disable Register 0
+ $80 constant DIDR0_ADC7D \ ADC7 Digital input Disable
+ $40 constant DIDR0_ADC6D \ ADC6 Digital input Disable
+ $20 constant DIDR0_ADC5D \ ADC5 Digital input Disable
+ $10 constant DIDR0_ADC4D \ ADC4 Digital input Disable
+ $08 constant DIDR0_ADC3D \ ADC3 Digital input Disable
+ $04 constant DIDR0_ADC2D \ ADC2 Digital input Disable
+ $02 constant DIDR0_ADC1D \ ADC1 Digital input Disable
+ $01 constant DIDR0_ADC0D \ ADC0 Digital input Disable
+\ BOOT_LOAD
+&87 constant SPMCSR \ Store Program Memory Control Register
+ $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
+ $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
+ $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
+ $04 constant SPMCSR_PGWRT \ Page Write
+ $02 constant SPMCSR_PGERS \ Page Erase
+ $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
+\ USART0
+&198 constant UDR0 \ USART I/O Data Register
+&192 constant UCSR0A \ USART Control and Status Register A
+ $80 constant UCSR0A_RXC0 \ USART Receive Complete
+ $40 constant UCSR0A_TXC0 \ USART Transmit Complete
+ $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
+ $10 constant UCSR0A_FE0 \ Framing Error
+ $08 constant UCSR0A_DOR0 \ Data OverRun
+ $04 constant UCSR0A_UPE0 \ USART Parity Error
+ $02 constant UCSR0A_U2X0 \ Double the USART Transmission Speed
+ $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
+&193 constant UCSR0B \ USART Control and Status Register B
+ $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
+ $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
+ $20 constant UCSR0B_UDRIE0 \ USART Data Register Empty Interrupt Enable
+ $10 constant UCSR0B_RXEN0 \ Receiver Enable
+ $08 constant UCSR0B_TXEN0 \ Transmitter Enable
+ $04 constant UCSR0B_UCSZ02 \ Character Size
+ $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
+ $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
+&194 constant UCSR0C \ USART Control and Status Register C
+ $40 constant UCSR0C_UMSEL0 \ USART Mode Select
+ $30 constant UCSR0C_UPM0 \ Parity Mode Bits
+ $08 constant UCSR0C_USBS0 \ Stop Bit Select
+ $06 constant UCSR0C_UCSZ0 \ Character Size
+ $01 constant UCSR0C_UCPOL0 \ Clock Polarity
+&196 constant UBRR0 \ USART Baud Rate Register Bytes
+\ PORTH
+&218 constant PORTH \ PORT H Data Register
+&217 constant DDRH \ PORT H Data Direction Register
+&216 constant PINH \ PORT H Input Pins
+\ PORTJ
+&221 constant PORTJ \ PORT J Data Register
+&220 constant DDRJ \ PORT J Data Direction Register
+&219 constant PINJ \ PORT J Input Pins
+
+\ Interrupts
+&2 constant INT0Addr \ External Interrupt Request 0
+&4 constant PCINT0Addr \ Pin Change Interrupt Request 0
+&6 constant PCINT1Addr \ Pin Change Interrupt Request 1
+&8 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
+&10 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
+&12 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+&14 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
+&16 constant TIMER1_COMPBAddr \ Timer/Counter Compare Match B
+&18 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+&20 constant TIMER0_COMPAddr \ Timer/Counter0 Compare Match
+&22 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
+&24 constant SPI__STCAddr \ SPI Serial Transfer Complete
+&26 constant USART__RXAddr \ USART, Rx Complete
+&28 constant USART__UDREAddr \ USART Data register Empty
+&30 constant USART0__TXAddr \ USART0, Tx Complete
+&32 constant USI_STARTAddr \ USI Start Condition
+&34 constant USI_OVERFLOWAddr \ USI Overflow
+&36 constant ANALOG_COMPAddr \ Analog Comparator
+&38 constant ADCAddr \ ADC Conversion Complete
+&40 constant EE_READYAddr \ EEPROM Ready
+&42 constant SPM_READYAddr \ Store Program Memory Read
+&44 constant NOT_USEDAddr \ RESERVED
+&46 constant PCINT2Addr \ Pin Change Interrupt Request 2
+&48 constant PCINT3Addr \ Pin Change Interrupt Request 3
diff --git a/amforth-6.5/avr8/devices/atmega3250/device.asm b/amforth-6.5/avr8/devices/atmega3250/device.asm
new file mode 100644
index 0000000..c6c401d
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega3250/device.asm
@@ -0,0 +1,114 @@
+; Partname: ATmega3250
+; generated automatically, do not edit
+
+.nolist
+ .include "m3250def.inc"
+.list
+
+.equ ramstart = 256
+.equ CELLSIZE = 2
+.macro readflashcell
+ lsl zl
+ rol zh
+ lpm @0, Z+
+ lpm @1, Z+
+.endmacro
+.macro writeflashcell
+ lsl zl
+ rol zh
+.endmacro
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_TIMER_COUNTER_2 = 0
+.set WANT_WATCHDOG = 0
+.set WANT_EEPROM = 0
+.set WANT_SPI = 0
+.set WANT_PORTA = 0
+.set WANT_PORTB = 0
+.set WANT_PORTC = 0
+.set WANT_PORTD = 0
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_PORTE = 0
+.set WANT_PORTF = 0
+.set WANT_PORTG = 0
+.set WANT_JTAG = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_CPU = 0
+.set WANT_USI = 0
+.set WANT_AD_CONVERTER = 0
+.set WANT_BOOT_LOAD = 0
+.set WANT_USART0 = 0
+.set WANT_PORTH = 0
+.set WANT_PORTJ = 0
+.equ intvecsize = 2 ; please verify; flash size: 32768 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.org 2
+ rcall isr ; External Interrupt Request 0
+.org 4
+ rcall isr ; Pin Change Interrupt Request 0
+.org 6
+ rcall isr ; Pin Change Interrupt Request 1
+.org 8
+ rcall isr ; Timer/Counter2 Compare Match
+.org 10
+ rcall isr ; Timer/Counter2 Overflow
+.org 12
+ rcall isr ; Timer/Counter1 Capture Event
+.org 14
+ rcall isr ; Timer/Counter1 Compare Match A
+.org 16
+ rcall isr ; Timer/Counter Compare Match B
+.org 18
+ rcall isr ; Timer/Counter1 Overflow
+.org 20
+ rcall isr ; Timer/Counter0 Compare Match
+.org 22
+ rcall isr ; Timer/Counter0 Overflow
+.org 24
+ rcall isr ; SPI Serial Transfer Complete
+.org 26
+ rcall isr ; USART, Rx Complete
+.org 28
+ rcall isr ; USART Data register Empty
+.org 30
+ rcall isr ; USART0, Tx Complete
+.org 32
+ rcall isr ; USI Start Condition
+.org 34
+ rcall isr ; USI Overflow
+.org 36
+ rcall isr ; Analog Comparator
+.org 38
+ rcall isr ; ADC Conversion Complete
+.org 40
+ rcall isr ; EEPROM Ready
+.org 42
+ rcall isr ; Store Program Memory Read
+.org 44
+ rcall isr ; RESERVED
+.org 46
+ rcall isr ; Pin Change Interrupt Request 2
+.org 48
+ rcall isr ; Pin Change Interrupt Request 3
+.equ INTVECTORS = 25
+.nooverlap
+
+; compatability layer (maybe empty)
+.equ EEPE = EEWE
+.equ EEMPE = EEMWE
+
+; controller data area, environment query mcu-info
+mcu_info:
+mcu_ramsize:
+ .dw 2048
+mcu_eepromsize:
+ .dw 1024
+mcu_maxdp:
+ .dw 28672
+mcu_numints:
+ .dw 25
+mcu_name:
+ .dw 10
+ .db "ATmega3250"
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega3250/device.inc b/amforth-6.5/avr8/devices/atmega3250/device.inc
new file mode 100644
index 0000000..22567c4
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega3250/device.inc
@@ -0,0 +1,1152 @@
+; Partname: ATmega3250
+; generated automatically, no not edit
+
+.if WANT_TIMER_COUNTER_0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Control Register
+VE_TCCR0A:
+ .dw $ff06
+ .db "TCCR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0A
+XT_TCCR0A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0A:
+ .dw 68
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw 70
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0A:
+ .dw $ff05
+ .db "OCR0A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0A
+XT_OCR0A:
+ .dw PFA_DOVARIABLE
+PFA_OCR0A:
+ .dw 71
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Mask Register
+VE_TIMSK0:
+ .dw $ff06
+ .db "TIMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK0
+XT_TIMSK0:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK0:
+ .dw 110
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Flag register
+VE_TIFR0:
+ .dw $ff05
+ .db "TIFR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR0
+XT_TIFR0:
+ .dw PFA_DOVARIABLE
+PFA_TIFR0:
+ .dw 53
+; ( -- addr ) System Constant
+; R( -- )
+; General Timer/Control Register
+VE_GTCCR:
+ .dw $ff05
+ .db "GTCCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GTCCR
+XT_GTCCR:
+ .dw PFA_DOVARIABLE
+PFA_GTCCR:
+ .dw 67
+
+.endif
+.if WANT_TIMER_COUNTER_1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw 128
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw 129
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter 1 Control Register C
+VE_TCCR1C:
+ .dw $ff06
+ .db "TCCR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1C
+XT_TCCR1C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1C:
+ .dw 130
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Bytes
+VE_TCNT1:
+ .dw $ff05
+ .db "TCNT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1
+XT_TCNT1:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1:
+ .dw 132
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register A Bytes
+VE_OCR1A:
+ .dw $ff05
+ .db "OCR1A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1A
+XT_OCR1A:
+ .dw PFA_DOVARIABLE
+PFA_OCR1A:
+ .dw 136
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register B Bytes
+VE_OCR1B:
+ .dw $ff05
+ .db "OCR1B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1B
+XT_OCR1B:
+ .dw PFA_DOVARIABLE
+PFA_OCR1B:
+ .dw 138
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Bytes
+VE_ICR1:
+ .dw $ff04
+ .db "ICR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1
+XT_ICR1:
+ .dw PFA_DOVARIABLE
+PFA_ICR1:
+ .dw 134
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Mask Register
+VE_TIMSK1:
+ .dw $ff06
+ .db "TIMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK1
+XT_TIMSK1:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK1:
+ .dw 111
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Flag register
+VE_TIFR1:
+ .dw $ff05
+ .db "TIFR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR1
+XT_TIFR1:
+ .dw PFA_DOVARIABLE
+PFA_TIFR1:
+ .dw 54
+
+.endif
+.if WANT_TIMER_COUNTER_2 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register
+VE_TCCR2A:
+ .dw $ff06
+ .db "TCCR2A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2A
+XT_TCCR2A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2A:
+ .dw 176
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2
+VE_TCNT2:
+ .dw $ff05
+ .db "TCNT2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT2
+XT_TCNT2:
+ .dw PFA_DOVARIABLE
+PFA_TCNT2:
+ .dw 178
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register
+VE_OCR2A:
+ .dw $ff05
+ .db "OCR2A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2A
+XT_OCR2A:
+ .dw PFA_DOVARIABLE
+PFA_OCR2A:
+ .dw 179
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Interrupt Mask register
+VE_TIMSK2:
+ .dw $ff06
+ .db "TIMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK2
+XT_TIMSK2:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK2:
+ .dw 112
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Interrupt Flag Register
+VE_TIFR2:
+ .dw $ff05
+ .db "TIFR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR2
+XT_TIFR2:
+ .dw PFA_DOVARIABLE
+PFA_TIFR2:
+ .dw 55
+; ( -- addr ) System Constant
+; R( -- )
+; Asynchronous Status Register
+VE_ASSR:
+ .dw $ff04
+ .db "ASSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ASSR
+XT_ASSR:
+ .dw PFA_DOVARIABLE
+PFA_ASSR:
+ .dw 182
+
+.endif
+.if WANT_WATCHDOG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCR:
+ .dw $ff05
+ .db "WDTCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCR
+XT_WDTCR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCR:
+ .dw 96
+
+.endif
+.if WANT_EEPROM == 1
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Read/Write Access Bytes
+VE_EEAR:
+ .dw $ff04
+ .db "EEAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEAR
+XT_EEAR:
+ .dw PFA_DOVARIABLE
+PFA_EEAR:
+ .dw 65
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw 64
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw 63
+
+.endif
+.if WANT_SPI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR:
+ .dw $ff04
+ .db "SPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR
+XT_SPCR:
+ .dw PFA_DOVARIABLE
+PFA_SPCR:
+ .dw 76
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR:
+ .dw $ff04
+ .db "SPSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR
+XT_SPSR:
+ .dw PFA_DOVARIABLE
+PFA_SPSR:
+ .dw 77
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR:
+ .dw $ff04
+ .db "SPDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR
+XT_SPDR:
+ .dw PFA_DOVARIABLE
+PFA_SPDR:
+ .dw 78
+
+.endif
+.if WANT_PORTA == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Register
+VE_PORTA:
+ .dw $ff05
+ .db "PORTA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTA
+XT_PORTA:
+ .dw PFA_DOVARIABLE
+PFA_PORTA:
+ .dw 34
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Direction Register
+VE_DDRA:
+ .dw $ff04
+ .db "DDRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRA
+XT_DDRA:
+ .dw PFA_DOVARIABLE
+PFA_DDRA:
+ .dw 33
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Input Pins
+VE_PINA:
+ .dw $ff04
+ .db "PINA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINA
+XT_PINA:
+ .dw PFA_DOVARIABLE
+PFA_PINA:
+ .dw 32
+
+.endif
+.if WANT_PORTB == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw 37
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw 36
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw 35
+
+.endif
+.if WANT_PORTC == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Register
+VE_PORTC:
+ .dw $ff05
+ .db "PORTC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTC
+XT_PORTC:
+ .dw PFA_DOVARIABLE
+PFA_PORTC:
+ .dw 40
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Direction Register
+VE_DDRC:
+ .dw $ff04
+ .db "DDRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRC
+XT_DDRC:
+ .dw PFA_DOVARIABLE
+PFA_DDRC:
+ .dw 39
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Input Pins
+VE_PINC:
+ .dw $ff04
+ .db "PINC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINC
+XT_PINC:
+ .dw PFA_DOVARIABLE
+PFA_PINC:
+ .dw 38
+
+.endif
+.if WANT_PORTD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw 43
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw 42
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw 41
+
+.endif
+.if WANT_ANALOG_COMPARATOR == 1
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Control and Status Register B
+VE_ADCSRB:
+ .dw $ff06
+ .db "ADCSRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRB
+XT_ADCSRB:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRB:
+ .dw 123
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Control And Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw 80
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 1
+VE_DIDR1:
+ .dw $ff05
+ .db "DIDR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR1
+XT_DIDR1:
+ .dw PFA_DOVARIABLE
+PFA_DIDR1:
+ .dw 127
+
+.endif
+.if WANT_PORTE == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port E
+VE_PORTE:
+ .dw $ff05
+ .db "PORTE",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTE
+XT_PORTE:
+ .dw PFA_DOVARIABLE
+PFA_PORTE:
+ .dw 46
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port E
+VE_DDRE:
+ .dw $ff04
+ .db "DDRE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRE
+XT_DDRE:
+ .dw PFA_DOVARIABLE
+PFA_DDRE:
+ .dw 45
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port E
+VE_PINE:
+ .dw $ff04
+ .db "PINE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINE
+XT_PINE:
+ .dw PFA_DOVARIABLE
+PFA_PINE:
+ .dw 44
+
+.endif
+.if WANT_PORTF == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port F
+VE_PORTF:
+ .dw $ff05
+ .db "PORTF",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTF
+XT_PORTF:
+ .dw PFA_DOVARIABLE
+PFA_PORTF:
+ .dw 49
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port F
+VE_DDRF:
+ .dw $ff04
+ .db "DDRF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRF
+XT_DDRF:
+ .dw PFA_DOVARIABLE
+PFA_DDRF:
+ .dw 48
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port F
+VE_PINF:
+ .dw $ff04
+ .db "PINF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINF
+XT_PINF:
+ .dw PFA_DOVARIABLE
+PFA_PINF:
+ .dw 47
+
+.endif
+.if WANT_PORTG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Data Register
+VE_PORTG:
+ .dw $ff05
+ .db "PORTG",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTG
+XT_PORTG:
+ .dw PFA_DOVARIABLE
+PFA_PORTG:
+ .dw 52
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Data Direction Register
+VE_DDRG:
+ .dw $ff04
+ .db "DDRG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRG
+XT_DDRG:
+ .dw PFA_DOVARIABLE
+PFA_DDRG:
+ .dw 51
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Input Pins
+VE_PING:
+ .dw $ff04
+ .db "PING"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PING
+XT_PING:
+ .dw PFA_DOVARIABLE
+PFA_PING:
+ .dw 50
+
+.endif
+.if WANT_JTAG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; On-Chip Debug Related Register in I/O Memory
+VE_OCDR:
+ .dw $ff04
+ .db "OCDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCDR
+XT_OCDR:
+ .dw PFA_DOVARIABLE
+PFA_OCDR:
+ .dw 81
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw 85
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Status Register
+VE_MCUSR:
+ .dw $ff05
+ .db "MCUSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUSR
+XT_MCUSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUSR:
+ .dw 84
+
+.endif
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register A
+VE_EICRA:
+ .dw $ff05
+ .db "EICRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRA
+XT_EICRA:
+ .dw PFA_DOVARIABLE
+PFA_EICRA:
+ .dw 105
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Mask Register
+VE_EIMSK:
+ .dw $ff05
+ .db "EIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIMSK
+XT_EIMSK:
+ .dw PFA_DOVARIABLE
+PFA_EIMSK:
+ .dw 61
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Flag Register
+VE_EIFR:
+ .dw $ff04
+ .db "EIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIFR
+XT_EIFR:
+ .dw PFA_DOVARIABLE
+PFA_EIFR:
+ .dw 60
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 3
+VE_PCMSK3:
+ .dw $ff06
+ .db "PCMSK3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK3
+XT_PCMSK3:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK3:
+ .dw 115
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 2
+VE_PCMSK2:
+ .dw $ff06
+ .db "PCMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK2
+XT_PCMSK2:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK2:
+ .dw 109
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 1
+VE_PCMSK1:
+ .dw $ff06
+ .db "PCMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK1
+XT_PCMSK1:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK1:
+ .dw 108
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 0
+VE_PCMSK0:
+ .dw $ff06
+ .db "PCMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK0
+XT_PCMSK0:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK0:
+ .dw 107
+
+.endif
+.if WANT_CPU == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw 95
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer
+VE_SP:
+ .dw $ff02
+ .db "SP"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SP
+XT_SP:
+ .dw PFA_DOVARIABLE
+PFA_SP:
+ .dw 93
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Calibration Value
+VE_OSCCAL:
+ .dw $ff06
+ .db "OSCCAL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSCCAL
+XT_OSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_OSCCAL:
+ .dw 102
+; ( -- addr ) System Constant
+; R( -- )
+; Clock Prescale Register
+VE_CLKPR:
+ .dw $ff05
+ .db "CLKPR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKPR
+XT_CLKPR:
+ .dw PFA_DOVARIABLE
+PFA_CLKPR:
+ .dw 97
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register
+VE_PRR:
+ .dw $ff03
+ .db "PRR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR
+XT_PRR:
+ .dw PFA_DOVARIABLE
+PFA_PRR:
+ .dw 100
+; ( -- addr ) System Constant
+; R( -- )
+; Sleep Mode Control Register
+VE_SMCR:
+ .dw $ff04
+ .db "SMCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SMCR
+XT_SMCR:
+ .dw PFA_DOVARIABLE
+PFA_SMCR:
+ .dw 83
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 2
+VE_GPIOR2:
+ .dw $ff06
+ .db "GPIOR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR2
+XT_GPIOR2:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR2:
+ .dw 75
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 1
+VE_GPIOR1:
+ .dw $ff06
+ .db "GPIOR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR1
+XT_GPIOR1:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR1:
+ .dw 74
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 0
+VE_GPIOR0:
+ .dw $ff06
+ .db "GPIOR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR0
+XT_GPIOR0:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR0:
+ .dw 62
+
+.endif
+.if WANT_USI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USI Data Register
+VE_USIDR:
+ .dw $ff05
+ .db "USIDR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USIDR
+XT_USIDR:
+ .dw PFA_DOVARIABLE
+PFA_USIDR:
+ .dw 186
+; ( -- addr ) System Constant
+; R( -- )
+; USI Status Register
+VE_USISR:
+ .dw $ff05
+ .db "USISR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USISR
+XT_USISR:
+ .dw PFA_DOVARIABLE
+PFA_USISR:
+ .dw 185
+; ( -- addr ) System Constant
+; R( -- )
+; USI Control Register
+VE_USICR:
+ .dw $ff05
+ .db "USICR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USICR
+XT_USICR:
+ .dw PFA_DOVARIABLE
+PFA_USICR:
+ .dw 184
+
+.endif
+.if WANT_AD_CONVERTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC multiplexer Selection Register
+VE_ADMUX:
+ .dw $ff05
+ .db "ADMUX",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADMUX
+XT_ADMUX:
+ .dw PFA_DOVARIABLE
+PFA_ADMUX:
+ .dw 124
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register
+VE_ADCSRA:
+ .dw $ff06
+ .db "ADCSRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRA
+XT_ADCSRA:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRA:
+ .dw 122
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register Bytes
+VE_ADC:
+ .dw $ff03
+ .db "ADC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADC
+XT_ADC:
+ .dw PFA_DOVARIABLE
+PFA_ADC:
+ .dw 120
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 0
+VE_DIDR0:
+ .dw $ff05
+ .db "DIDR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR0
+XT_DIDR0:
+ .dw PFA_DOVARIABLE
+PFA_DIDR0:
+ .dw 126
+
+.endif
+.if WANT_BOOT_LOAD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control Register
+VE_SPMCSR:
+ .dw $ff06
+ .db "SPMCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCSR
+XT_SPMCSR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCSR:
+ .dw 87
+
+.endif
+.if WANT_USART0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR0:
+ .dw $ff04
+ .db "UDR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR0
+XT_UDR0:
+ .dw PFA_DOVARIABLE
+PFA_UDR0:
+ .dw 198
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR0A:
+ .dw $ff06
+ .db "UCSR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0A
+XT_UCSR0A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0A:
+ .dw 192
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR0B:
+ .dw $ff06
+ .db "UCSR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0B
+XT_UCSR0B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0B:
+ .dw 193
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR0C:
+ .dw $ff06
+ .db "UCSR0C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0C
+XT_UCSR0C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0C:
+ .dw 194
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Bytes
+VE_UBRR0:
+ .dw $ff05
+ .db "UBRR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR0
+XT_UBRR0:
+ .dw PFA_DOVARIABLE
+PFA_UBRR0:
+ .dw 196
+
+.endif
+.if WANT_PORTH == 1
+; ( -- addr ) System Constant
+; R( -- )
+; PORT H Data Register
+VE_PORTH:
+ .dw $ff05
+ .db "PORTH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTH
+XT_PORTH:
+ .dw PFA_DOVARIABLE
+PFA_PORTH:
+ .dw 218
+; ( -- addr ) System Constant
+; R( -- )
+; PORT H Data Direction Register
+VE_DDRH:
+ .dw $ff04
+ .db "DDRH"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRH
+XT_DDRH:
+ .dw PFA_DOVARIABLE
+PFA_DDRH:
+ .dw 217
+; ( -- addr ) System Constant
+; R( -- )
+; PORT H Input Pins
+VE_PINH:
+ .dw $ff04
+ .db "PINH"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINH
+XT_PINH:
+ .dw PFA_DOVARIABLE
+PFA_PINH:
+ .dw 216
+
+.endif
+.if WANT_PORTJ == 1
+; ( -- addr ) System Constant
+; R( -- )
+; PORT J Data Register
+VE_PORTJ:
+ .dw $ff05
+ .db "PORTJ",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTJ
+XT_PORTJ:
+ .dw PFA_DOVARIABLE
+PFA_PORTJ:
+ .dw 221
+; ( -- addr ) System Constant
+; R( -- )
+; PORT J Data Direction Register
+VE_DDRJ:
+ .dw $ff04
+ .db "DDRJ"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRJ
+XT_DDRJ:
+ .dw PFA_DOVARIABLE
+PFA_DDRJ:
+ .dw 220
+; ( -- addr ) System Constant
+; R( -- )
+; PORT J Input Pins
+VE_PINJ:
+ .dw $ff04
+ .db "PINJ"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINJ
+XT_PINJ:
+ .dw PFA_DOVARIABLE
+PFA_PINJ:
+ .dw 219
+
+.endif
diff --git a/amforth-6.5/avr8/devices/atmega3250/device.py b/amforth-6.5/avr8/devices/atmega3250/device.py
new file mode 100644
index 0000000..f3dbb9a
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega3250/device.py
@@ -0,0 +1,333 @@
+# Generated Automatically
+
+# Partname ATmega3250
+
+MCUREGS = {
+# Interrupt Vectors
+ 'INT0Addr' : '#2', # External Interrupt Request 0
+ 'PCINT0Addr' : '#4', # Pin Change Interrupt Request 0
+ 'PCINT1Addr' : '#6', # Pin Change Interrupt Request 1
+ 'TIMER2_COMPAddr' : '#8', # Timer/Counter2 Compare Match
+ 'TIMER2_OVFAddr' : '#10', # Timer/Counter2 Overflow
+ 'TIMER1_CAPTAddr' : '#12', # Timer/Counter1 Capture Event
+ 'TIMER1_COMPAAddr' : '#14', # Timer/Counter1 Compare Match A
+ 'TIMER1_COMPBAddr' : '#16', # Timer/Counter Compare Match B
+ 'TIMER1_OVFAddr' : '#18', # Timer/Counter1 Overflow
+ 'TIMER0_COMPAddr' : '#20', # Timer/Counter0 Compare Match
+ 'TIMER0_OVFAddr' : '#22', # Timer/Counter0 Overflow
+ 'SPI_STCAddr' : '#24', # SPI Serial Transfer Complete
+ 'USART_RXAddr' : '#26', # USART, Rx Complete
+ 'USART_UDREAddr' : '#28', # USART Data register Empty
+ 'USART0_TXAddr' : '#30', # USART0, Tx Complete
+ 'USI_STARTAddr' : '#32', # USI Start Condition
+ 'USI_OVERFLOWAddr' : '#34', # USI Overflow
+ 'ANALOG_COMPAddr' : '#36', # Analog Comparator
+ 'ADCAddr' : '#38', # ADC Conversion Complete
+ 'EE_READYAddr' : '#40', # EEPROM Ready
+ 'SPM_READYAddr' : '#42', # Store Program Memory Read
+ 'NOT_USEDAddr' : '#44', # RESERVED
+ 'PCINT2Addr' : '#46', # Pin Change Interrupt Request 2
+ 'PCINT3Addr' : '#48', # Pin Change Interrupt Request 3
+
+# Module TIMER_COUNTER_0
+ 'TCCR0A' : '$44', # Timer/Counter0 Control Registe
+ 'TCCR0A_FOC0A': '$80', # Force Output Compare
+ 'TCCR0A_WGM00': '$40', # Waveform Generation Mode 0
+ 'TCCR0A_COM0A': '$30', # Compare Match Output Modes
+ 'TCCR0A_WGM01': '$8', # Waveform Generation Mode 1
+ 'TCCR0A_CS0': '$7', # Clock Selects
+ 'TCNT0' : '$46', # Timer/Counter0
+ 'OCR0A' : '$47', # Timer/Counter0 Output Compare
+ 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
+ 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
+ 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
+ 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
+ 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
+ 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Control Register
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSR310': '$1', # Prescaler Reset Timer/Counter1
+
+# Module TIMER_COUNTER_1
+ 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
+ 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
+ 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
+ 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
+ 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
+ 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
+ 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
+ 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
+ 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
+ 'TCCR1C' : '$82', # Timer/Counter 1 Control Regist
+ 'TCCR1C_FOC1A': '$80', # Force Output Compare 1A
+ 'TCCR1C_FOC1B': '$40', # Force Output Compare 1B
+ 'TCNT1' : '$84', # Timer/Counter1 Bytes
+ 'OCR1A' : '$88', # Timer/Counter1 Output Compare
+ 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
+ 'ICR1' : '$86', # Timer/Counter1 Input Capture R
+ 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
+ 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
+ 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
+ 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
+ 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
+ 'TIFR1' : '$36', # Timer/Counter1 Interrupt Flag
+ 'TIFR1_ICF1': '$20', # Input Capture Flag 1
+ 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
+ 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
+ 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
+
+# Module TIMER_COUNTER_2
+ 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
+ 'TCCR2A_FOC2A': '$80', # Force Output Compare A
+ 'TCCR2A_WGM20': '$40', # Waveform Generation Mode
+ 'TCCR2A_COM2A': '$30', # Compare Output Mode bits
+ 'TCCR2A_WGM21': '$8', # Waveform Generation Mode
+ 'TCCR2A_CS2': '$7', # Clock Select bits
+ 'TCNT2' : '$b2', # Timer/Counter2
+ 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
+ 'TIMSK2' : '$70', # Timer/Counter2 Interrupt Mask
+ 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
+ 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
+ 'TIFR2' : '$37', # Timer/Counter2 Interrupt Flag
+ 'TIFR2_OCF2A': '$2', # Timer/Counter2 Output Compare
+ 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_PSR2': '$2', # Prescaler Reset Timer/Counter2
+ 'ASSR' : '$b6', # Asynchronous Status Register
+ 'ASSR_EXCLK': '$10', # Enable External Clock Interrup
+ 'ASSR_AS2': '$8', # AS2: Asynchronous Timer/Counte
+ 'ASSR_TCN2UB': '$4', # TCN2UB: Timer/Counter2 Update
+ 'ASSR_OCR2UB': '$2', # Output Compare Register2 Updat
+ 'ASSR_TCR2UB': '$1', # TCR2UB: Timer/Counter Control
+
+# Module WATCHDOG
+ 'WDTCR' : '$60', # Watchdog Timer Control Registe
+ 'WDTCR_WDCE': '$10', # Watchdog Change Enable
+ 'WDTCR_WDE': '$8', # Watch Dog Enable
+ 'WDTCR_WDP': '$7', # Watch Dog Timer Prescaler bits
+
+# Module EEPROM
+ 'EEAR' : '$41', # EEPROM Read/Write Access Byte
+ 'EEDR' : '$40', # EEPROM Data Register
+ 'EECR' : '$3f', # EEPROM Control Register
+ 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
+ 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
+ 'EECR_EEWE': '$2', # EEPROM Write Enable
+ 'EECR_EERE': '$1', # EEPROM Read Enable
+
+# Module SPI
+ 'SPCR' : '$4c', # SPI Control Register
+ 'SPCR_SPIE': '$80', # SPI Interrupt Enable
+ 'SPCR_SPE': '$40', # SPI Enable
+ 'SPCR_DORD': '$20', # Data Order
+ 'SPCR_MSTR': '$10', # Master/Slave Select
+ 'SPCR_CPOL': '$8', # Clock polarity
+ 'SPCR_CPHA': '$4', # Clock Phase
+ 'SPCR_SPR': '$3', # SPI Clock Rate Selects
+ 'SPSR' : '$4d', # SPI Status Register
+ 'SPSR_SPIF': '$80', # SPI Interrupt Flag
+ 'SPSR_WCOL': '$40', # Write Collision Flag
+ 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
+ 'SPDR' : '$4e', # SPI Data Register
+
+# Module PORTA
+ 'PORTA' : '$22', # Port A Data Register
+ 'DDRA' : '$21', # Port A Data Direction Register
+ 'PINA' : '$20', # Port A Input Pins
+
+# Module PORTB
+ 'PORTB' : '$25', # Port B Data Register
+ 'DDRB' : '$24', # Port B Data Direction Register
+ 'PINB' : '$23', # Port B Input Pins
+
+# Module PORTC
+ 'PORTC' : '$28', # Port C Data Register
+ 'DDRC' : '$27', # Port C Data Direction Register
+ 'PINC' : '$26', # Port C Input Pins
+
+# Module PORTD
+ 'PORTD' : '$2b', # Port D Data Register
+ 'DDRD' : '$2a', # Port D Data Direction Register
+ 'PIND' : '$29', # Port D Input Pins
+
+# Module ANALOG_COMPARATOR
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
+ 'ACSR' : '$50', # Analog Comparator Control And
+ 'ACSR_ACD': '$80', # Analog Comparator Disable
+ 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
+ 'ACSR_ACO': '$20', # Analog Compare Output
+ 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
+ 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
+ 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
+ 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
+ 'DIDR1' : '$7f', # Digital Input Disable Register
+ 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
+ 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
+
+# Module PORTE
+ 'PORTE' : '$2e', # Data Register, Port E
+ 'DDRE' : '$2d', # Data Direction Register, Port
+ 'PINE' : '$2c', # Input Pins, Port E
+
+# Module PORTF
+ 'PORTF' : '$31', # Data Register, Port F
+ 'DDRF' : '$30', # Data Direction Register, Port
+ 'PINF' : '$2f', # Input Pins, Port F
+
+# Module PORTG
+ 'PORTG' : '$34', # Port G Data Register
+ 'DDRG' : '$33', # Port G Data Direction Register
+ 'PING' : '$32', # Port G Input Pins
+
+# Module JTAG
+ 'OCDR' : '$51', # On-Chip Debug Related Register
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_JTD': '$80', # JTAG Interface Disable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+
+# Module EXTERNAL_INTERRUPT
+ 'EICRA' : '$69', # External Interrupt Control Reg
+ 'EICRA_ISC01': '$2', # External Interrupt Sense Contr
+ 'EICRA_ISC00': '$1', # External Interrupt Sense Contr
+ 'EIMSK' : '$3d', # External Interrupt Mask Regist
+ 'EIMSK_PCIE': '$f0', # Pin Change Interrupt Enables
+ 'EIMSK_INT0': '$1', # External Interrupt Request 0 E
+ 'EIFR' : '$3c', # External Interrupt Flag Regist
+ 'EIFR_PCIF': '$f0', # Pin Change Interrupt Flags
+ 'EIFR_INTF0': '$1', # External Interrupt Flag 0
+ 'PCMSK3' : '$73', # Pin Change Mask Register 3
+ 'PCMSK2' : '$6d', # Pin Change Mask Register 2
+ 'PCMSK1' : '$6c', # Pin Change Mask Register 1
+ 'PCMSK0' : '$6b', # Pin Change Mask Register 0
+
+# Module CPU
+ 'SREG' : '$5f', # Status Register
+ 'SREG_I': '$80', # Global Interrupt Enable
+ 'SREG_T': '$40', # Bit Copy Storage
+ 'SREG_H': '$20', # Half Carry Flag
+ 'SREG_S': '$10', # Sign Bit
+ 'SREG_V': '$8', # Two's Complement Overflow Flag
+ 'SREG_N': '$4', # Negative Flag
+ 'SREG_Z': '$2', # Zero Flag
+ 'SREG_C': '$1', # Carry Flag
+ 'SP' : '$5d', # Stack Pointer
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_PUD': '$10', # Pull-up disable
+ 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
+ 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+ 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
+ 'MCUSR_BORF': '$4', # Brown-out Reset Flag
+ 'MCUSR_EXTRF': '$2', # External Reset Flag
+ 'MCUSR_PORF': '$1', # Power-on reset flag
+ 'OSCCAL' : '$66', # Oscillator Calibration Value
+ 'CLKPR' : '$61', # Clock Prescale Register
+ 'CLKPR_CLKPCE': '$80', # Clock Prescaler Change Enable
+ 'CLKPR_CLKPS': '$f', # Clock Prescaler Select Bits
+ 'PRR' : '$64', # Power Reduction Register
+ 'PRR_PRLCD': '$10', # Power Reduction LCD
+ 'PRR_PRTIM1': '$8', # Power Reduction Timer/Counter1
+ 'PRR_PRSPI': '$4', # Power Reduction Serial Periphe
+ 'PRR_PRUSART0': '$2', # Power Reduction USART
+ 'PRR_PRADC': '$1', # Power Reduction ADC
+ 'SMCR' : '$53', # Sleep Mode Control Register
+ 'SMCR_SM': '$e', # Sleep Mode Select bits
+ 'SMCR_SE': '$1', # Sleep Enable
+ 'GPIOR2' : '$4b', # General Purpose IO Register 2
+ 'GPIOR1' : '$4a', # General Purpose IO Register 1
+ 'GPIOR0' : '$3e', # General Purpose IO Register 0
+
+# Module USI
+ 'USIDR' : '$ba', # USI Data Register
+ 'USISR' : '$b9', # USI Status Register
+ 'USISR_USISIF': '$80', # Start Condition Interrupt Flag
+ 'USISR_USIOIF': '$40', # Counter Overflow Interrupt Fla
+ 'USISR_USIPF': '$20', # Stop Condition Flag
+ 'USISR_USIDC': '$10', # Data Output Collision
+ 'USISR_USICNT': '$f', # USI Counter Value Bits
+ 'USICR' : '$b8', # USI Control Register
+ 'USICR_USISIE': '$80', # Start Condition Interrupt Enab
+ 'USICR_USIOIE': '$40', # Counter Overflow Interrupt Ena
+ 'USICR_USIWM': '$30', # USI Wire Mode Bits
+ 'USICR_USICS': '$c', # USI Clock Source Select Bits
+ 'USICR_USICLK': '$2', # Clock Strobe
+ 'USICR_USITC': '$1', # Toggle Clock Port Pin
+
+# Module AD_CONVERTER
+ 'ADMUX' : '$7c', # The ADC multiplexer Selection
+ 'ADMUX_REFS': '$c0', # Reference Selection Bits
+ 'ADMUX_ADLAR': '$20', # Left Adjust Result
+ 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
+ 'ADCSRA' : '$7a', # The ADC Control and Status reg
+ 'ADCSRA_ADEN': '$80', # ADC Enable
+ 'ADCSRA_ADSC': '$40', # ADC Start Conversion
+ 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
+ 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
+ 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
+ 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
+ 'ADC' : '$78', # ADC Data Register Bytes
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Sources
+ 'DIDR0' : '$7e', # Digital Input Disable Register
+ 'DIDR0_ADC7D': '$80', # ADC7 Digital input Disable
+ 'DIDR0_ADC6D': '$40', # ADC6 Digital input Disable
+ 'DIDR0_ADC5D': '$20', # ADC5 Digital input Disable
+ 'DIDR0_ADC4D': '$10', # ADC4 Digital input Disable
+ 'DIDR0_ADC3D': '$8', # ADC3 Digital input Disable
+ 'DIDR0_ADC2D': '$4', # ADC2 Digital input Disable
+ 'DIDR0_ADC1D': '$2', # ADC1 Digital input Disable
+ 'DIDR0_ADC0D': '$1', # ADC0 Digital input Disable
+
+# Module BOOT_LOAD
+ 'SPMCSR' : '$57', # Store Program Memory Control R
+ 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
+ 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
+ 'SPMCSR_RWWSRE': '$10', # Read While Write section read
+ 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
+ 'SPMCSR_PGWRT': '$4', # Page Write
+ 'SPMCSR_PGERS': '$2', # Page Erase
+ 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
+
+# Module USART0
+ 'UDR0' : '$c6', # USART I/O Data Register
+ 'UCSR0A' : '$c0', # USART Control and Status Regis
+ 'UCSR0A_RXC0': '$80', # USART Receive Complete
+ 'UCSR0A_TXC0': '$40', # USART Transmit Complete
+ 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
+ 'UCSR0A_FE0': '$10', # Framing Error
+ 'UCSR0A_DOR0': '$8', # Data OverRun
+ 'UCSR0A_UPE0': '$4', # USART Parity Error
+ 'UCSR0A_U2X0': '$2', # Double the USART Transmission
+ 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
+ 'UCSR0B' : '$c1', # USART Control and Status Regis
+ 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
+ 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
+ 'UCSR0B_UDRIE0': '$20', # USART Data Register Empty Inte
+ 'UCSR0B_RXEN0': '$10', # Receiver Enable
+ 'UCSR0B_TXEN0': '$8', # Transmitter Enable
+ 'UCSR0B_UCSZ02': '$4', # Character Size
+ 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
+ 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
+ 'UCSR0C' : '$c2', # USART Control and Status Regis
+ 'UCSR0C_UMSEL0': '$40', # USART Mode Select
+ 'UCSR0C_UPM0': '$30', # Parity Mode Bits
+ 'UCSR0C_USBS0': '$8', # Stop Bit Select
+ 'UCSR0C_UCSZ0': '$6', # Character Size
+ 'UCSR0C_UCPOL0': '$1', # Clock Polarity
+ 'UBRR0' : '$c4', # USART Baud Rate Register Byte
+
+# Module PORTH
+ 'PORTH' : '$da', # PORT H Data Register
+ 'DDRH' : '$d9', # PORT H Data Direction Register
+ 'PINH' : '$d8', # PORT H Input Pins
+
+# Module PORTJ
+ 'PORTJ' : '$dd', # PORT J Data Register
+ 'DDRJ' : '$dc', # PORT J Data Direction Register
+ 'PINJ' : '$db', # PORT J Input Pins
+
+ '__amforth_dummy':'0'
+}
diff --git a/amforth-6.5/avr8/devices/atmega3250/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega3250/words/no-jtag.asm
new file mode 100644
index 0000000..352a4bb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega3250/words/no-jtag.asm
@@ -0,0 +1,14 @@
+; ( -- )
+; ( -- )
+; MCU
+; disable jtag at runtime
+VE_NOJTAG:
+ .dw $FF05
+ .db "-jtag",0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOJTAG
+XT_NOJTAG:
+ .dw PFA_NOJTAG
+PFA_NOJTAG:
+
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega3250/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega3250/words/no-wdt.asm
new file mode 100644
index 0000000..4a12261
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega3250/words/no-wdt.asm
@@ -0,0 +1,22 @@
+; ( -- )
+; MCU
+; disable watch dog timer at runtime
+VE_NOWDT:
+ .dw $ff04
+ .db "-wdt"
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOWDT
+XT_NOWDT:
+ .dw PFA_NOWDT
+PFA_NOWDT:
+
+; Reset WDT
+ wdr
+; Write logical one to WDTOE and WDE
+ in_ temp1, WDTCR
+ ori temp1, (1<<WDTOE)|(1<<WDE)
+ out WDTCR, temp1
+; Turn off WDT
+ ldi temp1, (0<<WDE)
+ out_ WDTCR, temp1
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega3250/words/sleep.asm b/amforth-6.5/avr8/devices/atmega3250/words/sleep.asm
new file mode 100644
index 0000000..256249c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega3250/words/sleep.asm
@@ -0,0 +1,19 @@
+; ( mode -- )
+; MCU
+; put the controller into the specified sleep mode
+VE_SLEEP:
+ .dw $ff05
+ .db "sleep", 0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_SLEEP
+XT_SLEEP:
+ .dw PFA_SLEEP
+PFA_SLEEP:
+ andi tosl, 7 ; leave only legal mode bits
+ lsl tosl ; move to correct location (bits 3-1)
+ ori tosl, 1 ; set the SE bit
+ out_ SMCR, tosl ; set the sleep config
+ sleep ; nighty-night
+ out_ SMCR, zerol ; 0 protects against accidental sleeps
+ loadtos ; pop argument from stack
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega3250a/atmega3250a.frt b/amforth-6.5/avr8/devices/atmega3250a/atmega3250a.frt
new file mode 100644
index 0000000..9d7b26c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega3250a/atmega3250a.frt
@@ -0,0 +1,292 @@
+\ Partname: ATmega3250A
+\ generated automatically
+
+\ TIMER_COUNTER_0
+&68 constant TCCR0A \ Timer/Counter0 Control Register
+ $80 constant TCCR0A_FOC0A \ Force Output Compare
+ $40 constant TCCR0A_WGM00 \ Waveform Generation Mode 0
+ $30 constant TCCR0A_COM0A \ Compare Match Output Modes
+ $08 constant TCCR0A_WGM01 \ Waveform Generation Mode 1
+ $07 constant TCCR0A_CS0 \ Clock Selects
+&70 constant TCNT0 \ Timer/Counter0
+&71 constant OCR0A \ Timer/Counter0 Output Compare Register
+&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
+ $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match Interrupt Enable
+ $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
+&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
+ $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0
+ $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
+&67 constant GTCCR \ General Timer/Control Register
+ $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
+ $01 constant GTCCR_PSR310 \ Prescaler Reset Timer/Counter1 and Timer/Counter0
+\ TIMER_COUNTER_1
+&128 constant TCCR1A \ Timer/Counter1 Control Register A
+ $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
+ $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
+ $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
+&129 constant TCCR1B \ Timer/Counter1 Control Register B
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
+ $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
+&130 constant TCCR1C \ Timer/Counter 1 Control Register C
+ $80 constant TCCR1C_FOC1A \ Force Output Compare 1A
+ $40 constant TCCR1C_FOC1B \ Force Output Compare 1B
+&132 constant TCNT1 \ Timer/Counter1 Bytes
+&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
+&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
+&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
+&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
+ $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
+ $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
+ $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
+ $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
+&54 constant TIFR1 \ Timer/Counter1 Interrupt Flag register
+ $20 constant TIFR1_ICF1 \ Input Capture Flag 1
+ $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
+ $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
+ $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
+\ TIMER_COUNTER_2
+&176 constant TCCR2A \ Timer/Counter2 Control Register
+ $80 constant TCCR2A_FOC2A \ Force Output Compare A
+ $40 constant TCCR2A_WGM20 \ Waveform Generation Mode
+ $30 constant TCCR2A_COM2A \ Compare Output Mode bits
+ $08 constant TCCR2A_WGM21 \ Waveform Generation Mode
+ $07 constant TCCR2A_CS2 \ Clock Select bits
+&178 constant TCNT2 \ Timer/Counter2
+&179 constant OCR2A \ Timer/Counter2 Output Compare Register
+&112 constant TIMSK2 \ Timer/Counter2 Interrupt Mask register
+ $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match Interrupt Enable
+ $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
+&55 constant TIFR2 \ Timer/Counter2 Interrupt Flag Register
+ $02 constant TIFR2_OCF2A \ Timer/Counter2 Output Compare Flag 2
+ $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
+&182 constant ASSR \ Asynchronous Status Register
+ $10 constant ASSR_EXCLK \ Enable External Clock Interrupt
+ $08 constant ASSR_AS2 \ AS2: Asynchronous Timer/Counter2
+ $04 constant ASSR_TCN2UB \ TCN2UB: Timer/Counter2 Update Busy
+ $02 constant ASSR_OCR2UB \ Output Compare Register2 Update Busy
+ $01 constant ASSR_TCR2UB \ TCR2UB: Timer/Counter Control Register2 Update Busy
+\ WATCHDOG
+&96 constant WDTCR \ Watchdog Timer Control Register
+ $10 constant WDTCR_WDCE \ Watchdog Change Enable
+ $08 constant WDTCR_WDE \ Watch Dog Enable
+ $07 constant WDTCR_WDP \ Watch Dog Timer Prescaler bits
+\ EEPROM
+&65 constant EEAR \ EEPROM Read/Write Access Bytes
+&64 constant EEDR \ EEPROM Data Register
+&63 constant EECR \ EEPROM Control Register
+ $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
+ $04 constant EECR_EEMWE \ EEPROM Master Write Enable
+ $02 constant EECR_EEWE \ EEPROM Write Enable
+ $01 constant EECR_EERE \ EEPROM Read Enable
+\ SPI
+&76 constant SPCR \ SPI Control Register
+ $80 constant SPCR_SPIE \ SPI Interrupt Enable
+ $40 constant SPCR_SPE \ SPI Enable
+ $20 constant SPCR_DORD \ Data Order
+ $10 constant SPCR_MSTR \ Master/Slave Select
+ $08 constant SPCR_CPOL \ Clock polarity
+ $04 constant SPCR_CPHA \ Clock Phase
+ $03 constant SPCR_SPR \ SPI Clock Rate Selects
+&77 constant SPSR \ SPI Status Register
+ $80 constant SPSR_SPIF \ SPI Interrupt Flag
+ $40 constant SPSR_WCOL \ Write Collision Flag
+ $01 constant SPSR_SPI2X \ Double SPI Speed Bit
+&78 constant SPDR \ SPI Data Register
+\ PORTA
+&34 constant PORTA \ Port A Data Register
+&33 constant DDRA \ Port A Data Direction Register
+&32 constant PINA \ Port A Input Pins
+\ PORTB
+&37 constant PORTB \ Port B Data Register
+&36 constant DDRB \ Port B Data Direction Register
+&35 constant PINB \ Port B Input Pins
+\ PORTC
+&40 constant PORTC \ Port C Data Register
+&39 constant DDRC \ Port C Data Direction Register
+&38 constant PINC \ Port C Input Pins
+\ PORTD
+&43 constant PORTD \ Port D Data Register
+&42 constant DDRD \ Port D Data Direction Register
+&41 constant PIND \ Port D Input Pins
+\ ANALOG_COMPARATOR
+&123 constant ADCSRB \ ADC Control and Status Register B
+ $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer Enable
+&80 constant ACSR \ Analog Comparator Control And Status Register
+ $80 constant ACSR_ACD \ Analog Comparator Disable
+ $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
+ $20 constant ACSR_ACO \ Analog Compare Output
+ $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
+ $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
+ $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
+ $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
+&127 constant DIDR1 \ Digital Input Disable Register 1
+ $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
+ $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
+\ PORTE
+&46 constant PORTE \ Data Register, Port E
+&45 constant DDRE \ Data Direction Register, Port E
+&44 constant PINE \ Input Pins, Port E
+\ PORTF
+&49 constant PORTF \ Data Register, Port F
+&48 constant DDRF \ Data Direction Register, Port F
+&47 constant PINF \ Input Pins, Port F
+\ PORTG
+&52 constant PORTG \ Port G Data Register
+&51 constant DDRG \ Port G Data Direction Register
+&50 constant PING \ Port G Input Pins
+\ JTAG
+&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
+&85 constant MCUCR \ MCU Control Register
+ $80 constant MCUCR_JTD \ JTAG Interface Disable
+&84 constant MCUSR \ MCU Status Register
+ $10 constant MCUSR_JTRF \ JTAG Reset Flag
+\ EXTERNAL_INTERRUPT
+&105 constant EICRA \ External Interrupt Control Register A
+ $02 constant EICRA_ISC01 \ External Interrupt Sense Control 0 Bit 1
+ $01 constant EICRA_ISC00 \ External Interrupt Sense Control 0 Bit 0
+&61 constant EIMSK \ External Interrupt Mask Register
+ $F0 constant EIMSK_PCIE \ Pin Change Interrupt Enables
+ $01 constant EIMSK_INT0 \ External Interrupt Request 0 Enable
+&60 constant EIFR \ External Interrupt Flag Register
+ $F0 constant EIFR_PCIF \ Pin Change Interrupt Flags
+ $01 constant EIFR_INTF0 \ External Interrupt Flag 0
+&115 constant PCMSK3 \ Pin Change Mask Register 3
+&109 constant PCMSK2 \ Pin Change Mask Register 2
+&108 constant PCMSK1 \ Pin Change Mask Register 1
+&107 constant PCMSK0 \ Pin Change Mask Register 0
+\ USI
+&186 constant USIDR \ USI Data Register
+&185 constant USISR \ USI Status Register
+ $80 constant USISR_USISIF \ Start Condition Interrupt Flag
+ $40 constant USISR_USIOIF \ Counter Overflow Interrupt Flag
+ $20 constant USISR_USIPF \ Stop Condition Flag
+ $10 constant USISR_USIDC \ Data Output Collision
+ $0F constant USISR_USICNT \ USI Counter Value Bits
+&184 constant USICR \ USI Control Register
+ $80 constant USICR_USISIE \ Start Condition Interrupt Enable
+ $40 constant USICR_USIOIE \ Counter Overflow Interrupt Enable
+ $30 constant USICR_USIWM \ USI Wire Mode Bits
+ $0C constant USICR_USICS \ USI Clock Source Select Bits
+ $02 constant USICR_USICLK \ Clock Strobe
+ $01 constant USICR_USITC \ Toggle Clock Port Pin
+\ AD_CONVERTER
+&124 constant ADMUX \ The ADC multiplexer Selection Register
+ $C0 constant ADMUX_REFS \ Reference Selection Bits
+ $20 constant ADMUX_ADLAR \ Left Adjust Result
+ $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
+&122 constant ADCSRA \ The ADC Control and Status register
+ $80 constant ADCSRA_ADEN \ ADC Enable
+ $40 constant ADCSRA_ADSC \ ADC Start Conversion
+ $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
+ $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
+ $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
+ $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
+&120 constant ADC \ ADC Data Register Bytes
+&126 constant DIDR0 \ Digital Input Disable Register 0
+ $80 constant DIDR0_ADC7D \ ADC7 Digital input Disable
+ $40 constant DIDR0_ADC6D \ ADC6 Digital input Disable
+ $20 constant DIDR0_ADC5D \ ADC5 Digital input Disable
+ $10 constant DIDR0_ADC4D \ ADC4 Digital input Disable
+ $08 constant DIDR0_ADC3D \ ADC3 Digital input Disable
+ $04 constant DIDR0_ADC2D \ ADC2 Digital input Disable
+ $02 constant DIDR0_ADC1D \ ADC1 Digital input Disable
+ $01 constant DIDR0_ADC0D \ ADC0 Digital input Disable
+\ BOOT_LOAD
+&87 constant SPMCSR \ Store Program Memory Control Register
+ $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
+ $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
+ $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
+ $04 constant SPMCSR_PGWRT \ Page Write
+ $02 constant SPMCSR_PGERS \ Page Erase
+ $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
+\ USART0
+&198 constant UDR0 \ USART I/O Data Register
+&192 constant UCSR0A \ USART Control and Status Register A
+ $80 constant UCSR0A_RXC0 \ USART Receive Complete
+ $40 constant UCSR0A_TXC0 \ USART Transmit Complete
+ $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
+ $10 constant UCSR0A_FE0 \ Framing Error
+ $08 constant UCSR0A_DOR0 \ Data OverRun
+ $04 constant UCSR0A_UPE0 \ USART Parity Error
+ $02 constant UCSR0A_U2X0 \ Double the USART Transmission Speed
+ $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
+&193 constant UCSR0B \ USART Control and Status Register B
+ $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
+ $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
+ $20 constant UCSR0B_UDRIE0 \ USART Data Register Empty Interrupt Enable
+ $10 constant UCSR0B_RXEN0 \ Receiver Enable
+ $08 constant UCSR0B_TXEN0 \ Transmitter Enable
+ $04 constant UCSR0B_UCSZ02 \ Character Size
+ $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
+ $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
+&194 constant UCSR0C \ USART Control and Status Register C
+ $40 constant UCSR0C_UMSEL0 \ USART Mode Select
+ $30 constant UCSR0C_UPM0 \ Parity Mode Bits
+ $08 constant UCSR0C_USBS0 \ Stop Bit Select
+ $06 constant UCSR0C_UCSZ0 \ Character Size
+ $01 constant UCSR0C_UCPOL0 \ Clock Polarity
+&196 constant UBRR0 \ USART Baud Rate Register Bytes
+\ PORTH
+&218 constant PORTH \ PORT H Data Register
+&217 constant DDRH \ PORT H Data Direction Register
+&216 constant PINH \ PORT H Input Pins
+\ PORTJ
+&221 constant PORTJ \ PORT J Data Register
+&220 constant DDRJ \ PORT J Data Direction Register
+&219 constant PINJ \ PORT J Input Pins
+\ CPU
+&95 constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ $08 constant SREG_V \ Two's Complement Overflow Flag
+ $04 constant SREG_N \ Negative Flag
+ $02 constant SREG_Z \ Zero Flag
+ $01 constant SREG_C \ Carry Flag
+&93 constant SP \ Stack Pointer
+&102 constant OSCCAL \ Oscillator Calibration Value
+&97 constant CLKPR \ Clock Prescale Register
+ $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable
+ $0F constant CLKPR_CLKPS \ Clock Prescaler Select Bits
+&100 constant PRR \ Power Reduction Register
+ $10 constant PRR_PRLCD \ Power Reduction LCD
+ $08 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
+ $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
+ $02 constant PRR_PRUSART0 \ Power Reduction USART
+ $01 constant PRR_PRADC \ Power Reduction ADC
+&83 constant SMCR \ Sleep Mode Control Register
+ $0E constant SMCR_SM \ Sleep Mode Select bits
+ $01 constant SMCR_SE \ Sleep Enable
+&75 constant GPIOR2 \ General Purpose IO Register 2
+&74 constant GPIOR1 \ General Purpose IO Register 1
+&62 constant GPIOR0 \ General Purpose IO Register 0
+
+\ Interrupts
+&2 constant INT0Addr \ External Interrupt Request 0
+&4 constant PCINT0Addr \ Pin Change Interrupt Request 0
+&6 constant PCINT1Addr \ Pin Change Interrupt Request 1
+&8 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
+&10 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
+&12 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+&14 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
+&16 constant TIMER1_COMPBAddr \ Timer/Counter Compare Match B
+&18 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+&20 constant TIMER0_COMPAddr \ Timer/Counter0 Compare Match
+&22 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
+&24 constant SPI__STCAddr \ SPI Serial Transfer Complete
+&26 constant USART__RXAddr \ USART, Rx Complete
+&28 constant USART__UDREAddr \ USART Data register Empty
+&30 constant USART0__TXAddr \ USART0, Tx Complete
+&32 constant USI_STARTAddr \ USI Start Condition
+&34 constant USI_OVERFLOWAddr \ USI Overflow
+&36 constant ANALOG_COMPAddr \ Analog Comparator
+&38 constant ADCAddr \ ADC Conversion Complete
+&40 constant EE_READYAddr \ EEPROM Ready
+&42 constant SPM_READYAddr \ Store Program Memory Read
+&44 constant NOT_USEDAddr \ RESERVED
+&46 constant PCINT2Addr \ Pin Change Interrupt Request 2
+&48 constant PCINT3Addr \ Pin Change Interrupt Request 3
diff --git a/amforth-6.5/avr8/devices/atmega3250a/device.asm b/amforth-6.5/avr8/devices/atmega3250a/device.asm
new file mode 100644
index 0000000..01060c0
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega3250a/device.asm
@@ -0,0 +1,114 @@
+; Partname: ATmega3250A
+; generated automatically, do not edit
+
+.nolist
+ .include "m3250Adef.inc"
+.list
+
+.equ ramstart = 256
+.equ CELLSIZE = 2
+.macro readflashcell
+ lsl zl
+ rol zh
+ lpm @0, Z+
+ lpm @1, Z+
+.endmacro
+.macro writeflashcell
+ lsl zl
+ rol zh
+.endmacro
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_TIMER_COUNTER_2 = 0
+.set WANT_WATCHDOG = 0
+.set WANT_EEPROM = 0
+.set WANT_SPI = 0
+.set WANT_PORTA = 0
+.set WANT_PORTB = 0
+.set WANT_PORTC = 0
+.set WANT_PORTD = 0
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_PORTE = 0
+.set WANT_PORTF = 0
+.set WANT_PORTG = 0
+.set WANT_JTAG = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_USI = 0
+.set WANT_AD_CONVERTER = 0
+.set WANT_BOOT_LOAD = 0
+.set WANT_USART0 = 0
+.set WANT_PORTH = 0
+.set WANT_PORTJ = 0
+.set WANT_CPU = 0
+.equ intvecsize = 2 ; please verify; flash size: 32768 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.org 2
+ rcall isr ; External Interrupt Request 0
+.org 4
+ rcall isr ; Pin Change Interrupt Request 0
+.org 6
+ rcall isr ; Pin Change Interrupt Request 1
+.org 8
+ rcall isr ; Timer/Counter2 Compare Match
+.org 10
+ rcall isr ; Timer/Counter2 Overflow
+.org 12
+ rcall isr ; Timer/Counter1 Capture Event
+.org 14
+ rcall isr ; Timer/Counter1 Compare Match A
+.org 16
+ rcall isr ; Timer/Counter Compare Match B
+.org 18
+ rcall isr ; Timer/Counter1 Overflow
+.org 20
+ rcall isr ; Timer/Counter0 Compare Match
+.org 22
+ rcall isr ; Timer/Counter0 Overflow
+.org 24
+ rcall isr ; SPI Serial Transfer Complete
+.org 26
+ rcall isr ; USART, Rx Complete
+.org 28
+ rcall isr ; USART Data register Empty
+.org 30
+ rcall isr ; USART0, Tx Complete
+.org 32
+ rcall isr ; USI Start Condition
+.org 34
+ rcall isr ; USI Overflow
+.org 36
+ rcall isr ; Analog Comparator
+.org 38
+ rcall isr ; ADC Conversion Complete
+.org 40
+ rcall isr ; EEPROM Ready
+.org 42
+ rcall isr ; Store Program Memory Read
+.org 44
+ rcall isr ; RESERVED
+.org 46
+ rcall isr ; Pin Change Interrupt Request 2
+.org 48
+ rcall isr ; Pin Change Interrupt Request 3
+.equ INTVECTORS = 25
+.nooverlap
+
+; compatability layer (maybe empty)
+.equ EEPE = EEWE
+.equ EEMPE = EEMWE
+
+; controller data area, environment query mcu-info
+mcu_info:
+mcu_ramsize:
+ .dw 2048
+mcu_eepromsize:
+ .dw 1024
+mcu_maxdp:
+ .dw 28672
+mcu_numints:
+ .dw 25
+mcu_name:
+ .dw 11
+ .db "ATmega3250A",0
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega3250a/device.inc b/amforth-6.5/avr8/devices/atmega3250a/device.inc
new file mode 100644
index 0000000..5f083a7
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega3250a/device.inc
@@ -0,0 +1,1152 @@
+; Partname: ATmega3250A
+; generated automatically, no not edit
+
+.if WANT_TIMER_COUNTER_0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Control Register
+VE_TCCR0A:
+ .dw $ff06
+ .db "TCCR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0A
+XT_TCCR0A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0A:
+ .dw 68
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw 70
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0A:
+ .dw $ff05
+ .db "OCR0A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0A
+XT_OCR0A:
+ .dw PFA_DOVARIABLE
+PFA_OCR0A:
+ .dw 71
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Mask Register
+VE_TIMSK0:
+ .dw $ff06
+ .db "TIMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK0
+XT_TIMSK0:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK0:
+ .dw 110
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Flag register
+VE_TIFR0:
+ .dw $ff05
+ .db "TIFR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR0
+XT_TIFR0:
+ .dw PFA_DOVARIABLE
+PFA_TIFR0:
+ .dw 53
+; ( -- addr ) System Constant
+; R( -- )
+; General Timer/Control Register
+VE_GTCCR:
+ .dw $ff05
+ .db "GTCCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GTCCR
+XT_GTCCR:
+ .dw PFA_DOVARIABLE
+PFA_GTCCR:
+ .dw 67
+
+.endif
+.if WANT_TIMER_COUNTER_1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw 128
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw 129
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter 1 Control Register C
+VE_TCCR1C:
+ .dw $ff06
+ .db "TCCR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1C
+XT_TCCR1C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1C:
+ .dw 130
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Bytes
+VE_TCNT1:
+ .dw $ff05
+ .db "TCNT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1
+XT_TCNT1:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1:
+ .dw 132
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register A Bytes
+VE_OCR1A:
+ .dw $ff05
+ .db "OCR1A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1A
+XT_OCR1A:
+ .dw PFA_DOVARIABLE
+PFA_OCR1A:
+ .dw 136
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register B Bytes
+VE_OCR1B:
+ .dw $ff05
+ .db "OCR1B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1B
+XT_OCR1B:
+ .dw PFA_DOVARIABLE
+PFA_OCR1B:
+ .dw 138
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Bytes
+VE_ICR1:
+ .dw $ff04
+ .db "ICR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1
+XT_ICR1:
+ .dw PFA_DOVARIABLE
+PFA_ICR1:
+ .dw 134
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Mask Register
+VE_TIMSK1:
+ .dw $ff06
+ .db "TIMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK1
+XT_TIMSK1:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK1:
+ .dw 111
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Flag register
+VE_TIFR1:
+ .dw $ff05
+ .db "TIFR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR1
+XT_TIFR1:
+ .dw PFA_DOVARIABLE
+PFA_TIFR1:
+ .dw 54
+
+.endif
+.if WANT_TIMER_COUNTER_2 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register
+VE_TCCR2A:
+ .dw $ff06
+ .db "TCCR2A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2A
+XT_TCCR2A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2A:
+ .dw 176
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2
+VE_TCNT2:
+ .dw $ff05
+ .db "TCNT2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT2
+XT_TCNT2:
+ .dw PFA_DOVARIABLE
+PFA_TCNT2:
+ .dw 178
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register
+VE_OCR2A:
+ .dw $ff05
+ .db "OCR2A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2A
+XT_OCR2A:
+ .dw PFA_DOVARIABLE
+PFA_OCR2A:
+ .dw 179
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Interrupt Mask register
+VE_TIMSK2:
+ .dw $ff06
+ .db "TIMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK2
+XT_TIMSK2:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK2:
+ .dw 112
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Interrupt Flag Register
+VE_TIFR2:
+ .dw $ff05
+ .db "TIFR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR2
+XT_TIFR2:
+ .dw PFA_DOVARIABLE
+PFA_TIFR2:
+ .dw 55
+; ( -- addr ) System Constant
+; R( -- )
+; Asynchronous Status Register
+VE_ASSR:
+ .dw $ff04
+ .db "ASSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ASSR
+XT_ASSR:
+ .dw PFA_DOVARIABLE
+PFA_ASSR:
+ .dw 182
+
+.endif
+.if WANT_WATCHDOG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCR:
+ .dw $ff05
+ .db "WDTCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCR
+XT_WDTCR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCR:
+ .dw 96
+
+.endif
+.if WANT_EEPROM == 1
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Read/Write Access Bytes
+VE_EEAR:
+ .dw $ff04
+ .db "EEAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEAR
+XT_EEAR:
+ .dw PFA_DOVARIABLE
+PFA_EEAR:
+ .dw 65
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw 64
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw 63
+
+.endif
+.if WANT_SPI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR:
+ .dw $ff04
+ .db "SPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR
+XT_SPCR:
+ .dw PFA_DOVARIABLE
+PFA_SPCR:
+ .dw 76
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR:
+ .dw $ff04
+ .db "SPSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR
+XT_SPSR:
+ .dw PFA_DOVARIABLE
+PFA_SPSR:
+ .dw 77
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR:
+ .dw $ff04
+ .db "SPDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR
+XT_SPDR:
+ .dw PFA_DOVARIABLE
+PFA_SPDR:
+ .dw 78
+
+.endif
+.if WANT_PORTA == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Register
+VE_PORTA:
+ .dw $ff05
+ .db "PORTA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTA
+XT_PORTA:
+ .dw PFA_DOVARIABLE
+PFA_PORTA:
+ .dw 34
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Direction Register
+VE_DDRA:
+ .dw $ff04
+ .db "DDRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRA
+XT_DDRA:
+ .dw PFA_DOVARIABLE
+PFA_DDRA:
+ .dw 33
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Input Pins
+VE_PINA:
+ .dw $ff04
+ .db "PINA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINA
+XT_PINA:
+ .dw PFA_DOVARIABLE
+PFA_PINA:
+ .dw 32
+
+.endif
+.if WANT_PORTB == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw 37
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw 36
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw 35
+
+.endif
+.if WANT_PORTC == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Register
+VE_PORTC:
+ .dw $ff05
+ .db "PORTC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTC
+XT_PORTC:
+ .dw PFA_DOVARIABLE
+PFA_PORTC:
+ .dw 40
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Direction Register
+VE_DDRC:
+ .dw $ff04
+ .db "DDRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRC
+XT_DDRC:
+ .dw PFA_DOVARIABLE
+PFA_DDRC:
+ .dw 39
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Input Pins
+VE_PINC:
+ .dw $ff04
+ .db "PINC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINC
+XT_PINC:
+ .dw PFA_DOVARIABLE
+PFA_PINC:
+ .dw 38
+
+.endif
+.if WANT_PORTD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw 43
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw 42
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw 41
+
+.endif
+.if WANT_ANALOG_COMPARATOR == 1
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Control and Status Register B
+VE_ADCSRB:
+ .dw $ff06
+ .db "ADCSRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRB
+XT_ADCSRB:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRB:
+ .dw 123
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Control And Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw 80
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 1
+VE_DIDR1:
+ .dw $ff05
+ .db "DIDR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR1
+XT_DIDR1:
+ .dw PFA_DOVARIABLE
+PFA_DIDR1:
+ .dw 127
+
+.endif
+.if WANT_PORTE == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port E
+VE_PORTE:
+ .dw $ff05
+ .db "PORTE",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTE
+XT_PORTE:
+ .dw PFA_DOVARIABLE
+PFA_PORTE:
+ .dw 46
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port E
+VE_DDRE:
+ .dw $ff04
+ .db "DDRE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRE
+XT_DDRE:
+ .dw PFA_DOVARIABLE
+PFA_DDRE:
+ .dw 45
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port E
+VE_PINE:
+ .dw $ff04
+ .db "PINE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINE
+XT_PINE:
+ .dw PFA_DOVARIABLE
+PFA_PINE:
+ .dw 44
+
+.endif
+.if WANT_PORTF == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port F
+VE_PORTF:
+ .dw $ff05
+ .db "PORTF",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTF
+XT_PORTF:
+ .dw PFA_DOVARIABLE
+PFA_PORTF:
+ .dw 49
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port F
+VE_DDRF:
+ .dw $ff04
+ .db "DDRF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRF
+XT_DDRF:
+ .dw PFA_DOVARIABLE
+PFA_DDRF:
+ .dw 48
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port F
+VE_PINF:
+ .dw $ff04
+ .db "PINF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINF
+XT_PINF:
+ .dw PFA_DOVARIABLE
+PFA_PINF:
+ .dw 47
+
+.endif
+.if WANT_PORTG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Data Register
+VE_PORTG:
+ .dw $ff05
+ .db "PORTG",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTG
+XT_PORTG:
+ .dw PFA_DOVARIABLE
+PFA_PORTG:
+ .dw 52
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Data Direction Register
+VE_DDRG:
+ .dw $ff04
+ .db "DDRG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRG
+XT_DDRG:
+ .dw PFA_DOVARIABLE
+PFA_DDRG:
+ .dw 51
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Input Pins
+VE_PING:
+ .dw $ff04
+ .db "PING"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PING
+XT_PING:
+ .dw PFA_DOVARIABLE
+PFA_PING:
+ .dw 50
+
+.endif
+.if WANT_JTAG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; On-Chip Debug Related Register in I/O Memory
+VE_OCDR:
+ .dw $ff04
+ .db "OCDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCDR
+XT_OCDR:
+ .dw PFA_DOVARIABLE
+PFA_OCDR:
+ .dw 81
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw 85
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Status Register
+VE_MCUSR:
+ .dw $ff05
+ .db "MCUSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUSR
+XT_MCUSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUSR:
+ .dw 84
+
+.endif
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register A
+VE_EICRA:
+ .dw $ff05
+ .db "EICRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRA
+XT_EICRA:
+ .dw PFA_DOVARIABLE
+PFA_EICRA:
+ .dw 105
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Mask Register
+VE_EIMSK:
+ .dw $ff05
+ .db "EIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIMSK
+XT_EIMSK:
+ .dw PFA_DOVARIABLE
+PFA_EIMSK:
+ .dw 61
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Flag Register
+VE_EIFR:
+ .dw $ff04
+ .db "EIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIFR
+XT_EIFR:
+ .dw PFA_DOVARIABLE
+PFA_EIFR:
+ .dw 60
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 3
+VE_PCMSK3:
+ .dw $ff06
+ .db "PCMSK3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK3
+XT_PCMSK3:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK3:
+ .dw 115
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 2
+VE_PCMSK2:
+ .dw $ff06
+ .db "PCMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK2
+XT_PCMSK2:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK2:
+ .dw 109
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 1
+VE_PCMSK1:
+ .dw $ff06
+ .db "PCMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK1
+XT_PCMSK1:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK1:
+ .dw 108
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 0
+VE_PCMSK0:
+ .dw $ff06
+ .db "PCMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK0
+XT_PCMSK0:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK0:
+ .dw 107
+
+.endif
+.if WANT_USI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USI Data Register
+VE_USIDR:
+ .dw $ff05
+ .db "USIDR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USIDR
+XT_USIDR:
+ .dw PFA_DOVARIABLE
+PFA_USIDR:
+ .dw 186
+; ( -- addr ) System Constant
+; R( -- )
+; USI Status Register
+VE_USISR:
+ .dw $ff05
+ .db "USISR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USISR
+XT_USISR:
+ .dw PFA_DOVARIABLE
+PFA_USISR:
+ .dw 185
+; ( -- addr ) System Constant
+; R( -- )
+; USI Control Register
+VE_USICR:
+ .dw $ff05
+ .db "USICR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USICR
+XT_USICR:
+ .dw PFA_DOVARIABLE
+PFA_USICR:
+ .dw 184
+
+.endif
+.if WANT_AD_CONVERTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC multiplexer Selection Register
+VE_ADMUX:
+ .dw $ff05
+ .db "ADMUX",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADMUX
+XT_ADMUX:
+ .dw PFA_DOVARIABLE
+PFA_ADMUX:
+ .dw 124
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register
+VE_ADCSRA:
+ .dw $ff06
+ .db "ADCSRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRA
+XT_ADCSRA:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRA:
+ .dw 122
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register Bytes
+VE_ADC:
+ .dw $ff03
+ .db "ADC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADC
+XT_ADC:
+ .dw PFA_DOVARIABLE
+PFA_ADC:
+ .dw 120
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 0
+VE_DIDR0:
+ .dw $ff05
+ .db "DIDR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR0
+XT_DIDR0:
+ .dw PFA_DOVARIABLE
+PFA_DIDR0:
+ .dw 126
+
+.endif
+.if WANT_BOOT_LOAD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control Register
+VE_SPMCSR:
+ .dw $ff06
+ .db "SPMCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCSR
+XT_SPMCSR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCSR:
+ .dw 87
+
+.endif
+.if WANT_USART0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR0:
+ .dw $ff04
+ .db "UDR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR0
+XT_UDR0:
+ .dw PFA_DOVARIABLE
+PFA_UDR0:
+ .dw 198
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR0A:
+ .dw $ff06
+ .db "UCSR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0A
+XT_UCSR0A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0A:
+ .dw 192
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR0B:
+ .dw $ff06
+ .db "UCSR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0B
+XT_UCSR0B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0B:
+ .dw 193
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR0C:
+ .dw $ff06
+ .db "UCSR0C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0C
+XT_UCSR0C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0C:
+ .dw 194
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Bytes
+VE_UBRR0:
+ .dw $ff05
+ .db "UBRR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR0
+XT_UBRR0:
+ .dw PFA_DOVARIABLE
+PFA_UBRR0:
+ .dw 196
+
+.endif
+.if WANT_PORTH == 1
+; ( -- addr ) System Constant
+; R( -- )
+; PORT H Data Register
+VE_PORTH:
+ .dw $ff05
+ .db "PORTH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTH
+XT_PORTH:
+ .dw PFA_DOVARIABLE
+PFA_PORTH:
+ .dw 218
+; ( -- addr ) System Constant
+; R( -- )
+; PORT H Data Direction Register
+VE_DDRH:
+ .dw $ff04
+ .db "DDRH"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRH
+XT_DDRH:
+ .dw PFA_DOVARIABLE
+PFA_DDRH:
+ .dw 217
+; ( -- addr ) System Constant
+; R( -- )
+; PORT H Input Pins
+VE_PINH:
+ .dw $ff04
+ .db "PINH"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINH
+XT_PINH:
+ .dw PFA_DOVARIABLE
+PFA_PINH:
+ .dw 216
+
+.endif
+.if WANT_PORTJ == 1
+; ( -- addr ) System Constant
+; R( -- )
+; PORT J Data Register
+VE_PORTJ:
+ .dw $ff05
+ .db "PORTJ",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTJ
+XT_PORTJ:
+ .dw PFA_DOVARIABLE
+PFA_PORTJ:
+ .dw 221
+; ( -- addr ) System Constant
+; R( -- )
+; PORT J Data Direction Register
+VE_DDRJ:
+ .dw $ff04
+ .db "DDRJ"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRJ
+XT_DDRJ:
+ .dw PFA_DOVARIABLE
+PFA_DDRJ:
+ .dw 220
+; ( -- addr ) System Constant
+; R( -- )
+; PORT J Input Pins
+VE_PINJ:
+ .dw $ff04
+ .db "PINJ"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINJ
+XT_PINJ:
+ .dw PFA_DOVARIABLE
+PFA_PINJ:
+ .dw 219
+
+.endif
+.if WANT_CPU == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw 95
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer
+VE_SP:
+ .dw $ff02
+ .db "SP"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SP
+XT_SP:
+ .dw PFA_DOVARIABLE
+PFA_SP:
+ .dw 93
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Calibration Value
+VE_OSCCAL:
+ .dw $ff06
+ .db "OSCCAL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSCCAL
+XT_OSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_OSCCAL:
+ .dw 102
+; ( -- addr ) System Constant
+; R( -- )
+; Clock Prescale Register
+VE_CLKPR:
+ .dw $ff05
+ .db "CLKPR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKPR
+XT_CLKPR:
+ .dw PFA_DOVARIABLE
+PFA_CLKPR:
+ .dw 97
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register
+VE_PRR:
+ .dw $ff03
+ .db "PRR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR
+XT_PRR:
+ .dw PFA_DOVARIABLE
+PFA_PRR:
+ .dw 100
+; ( -- addr ) System Constant
+; R( -- )
+; Sleep Mode Control Register
+VE_SMCR:
+ .dw $ff04
+ .db "SMCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SMCR
+XT_SMCR:
+ .dw PFA_DOVARIABLE
+PFA_SMCR:
+ .dw 83
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 2
+VE_GPIOR2:
+ .dw $ff06
+ .db "GPIOR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR2
+XT_GPIOR2:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR2:
+ .dw 75
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 1
+VE_GPIOR1:
+ .dw $ff06
+ .db "GPIOR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR1
+XT_GPIOR1:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR1:
+ .dw 74
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 0
+VE_GPIOR0:
+ .dw $ff06
+ .db "GPIOR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR0
+XT_GPIOR0:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR0:
+ .dw 62
+
+.endif
diff --git a/amforth-6.5/avr8/devices/atmega3250a/device.py b/amforth-6.5/avr8/devices/atmega3250a/device.py
new file mode 100644
index 0000000..43b6376
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega3250a/device.py
@@ -0,0 +1,336 @@
+# Generated Automatically
+
+# Partname ATmega3250PA
+
+MCUREGS = {
+# Interrupt Vectors
+ 'INT0Addr' : '#2', # External Interrupt Request 0
+ 'PCINT0Addr' : '#4', # Pin Change Interrupt Request 0
+ 'PCINT1Addr' : '#6', # Pin Change Interrupt Request 1
+ 'TIMER2_COMPAddr' : '#8', # Timer/Counter2 Compare Match
+ 'TIMER2_OVFAddr' : '#10', # Timer/Counter2 Overflow
+ 'TIMER1_CAPTAddr' : '#12', # Timer/Counter1 Capture Event
+ 'TIMER1_COMPAAddr' : '#14', # Timer/Counter1 Compare Match A
+ 'TIMER1_COMPBAddr' : '#16', # Timer/Counter Compare Match B
+ 'TIMER1_OVFAddr' : '#18', # Timer/Counter1 Overflow
+ 'TIMER0_COMPAddr' : '#20', # Timer/Counter0 Compare Match
+ 'TIMER0_OVFAddr' : '#22', # Timer/Counter0 Overflow
+ 'SPI_STCAddr' : '#24', # SPI Serial Transfer Complete
+ 'USART_RXAddr' : '#26', # USART, Rx Complete
+ 'USART_UDREAddr' : '#28', # USART Data register Empty
+ 'USART0_TXAddr' : '#30', # USART0, Tx Complete
+ 'USI_STARTAddr' : '#32', # USI Start Condition
+ 'USI_OVERFLOWAddr' : '#34', # USI Overflow
+ 'ANALOG_COMPAddr' : '#36', # Analog Comparator
+ 'ADCAddr' : '#38', # ADC Conversion Complete
+ 'EE_READYAddr' : '#40', # EEPROM Ready
+ 'SPM_READYAddr' : '#42', # Store Program Memory Read
+ 'NOT_USEDAddr' : '#44', # RESERVED
+ 'PCINT2Addr' : '#46', # Pin Change Interrupt Request 2
+ 'PCINT3Addr' : '#48', # Pin Change Interrupt Request 3
+
+# Module TIMER_COUNTER_0
+ 'TCCR0A' : '$44', # Timer/Counter0 Control Registe
+ 'TCCR0A_FOC0A': '$80', # Force Output Compare
+ 'TCCR0A_WGM00': '$40', # Waveform Generation Mode 0
+ 'TCCR0A_COM0A': '$30', # Compare Match Output Modes
+ 'TCCR0A_WGM01': '$8', # Waveform Generation Mode 1
+ 'TCCR0A_CS0': '$7', # Clock Selects
+ 'TCNT0' : '$46', # Timer/Counter0
+ 'OCR0A' : '$47', # Timer/Counter0 Output Compare
+ 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
+ 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
+ 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
+ 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
+ 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
+ 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Control Register
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSR310': '$1', # Prescaler Reset Timer/Counter1
+
+# Module TIMER_COUNTER_1
+ 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
+ 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
+ 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
+ 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
+ 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
+ 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
+ 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
+ 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
+ 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
+ 'TCCR1C' : '$82', # Timer/Counter 1 Control Regist
+ 'TCCR1C_FOC1A': '$80', # Force Output Compare 1A
+ 'TCCR1C_FOC1B': '$40', # Force Output Compare 1B
+ 'TCNT1' : '$84', # Timer/Counter1 Bytes
+ 'OCR1A' : '$88', # Timer/Counter1 Output Compare
+ 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
+ 'ICR1' : '$86', # Timer/Counter1 Input Capture R
+ 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
+ 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
+ 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
+ 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
+ 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
+ 'TIFR1' : '$36', # Timer/Counter1 Interrupt Flag
+ 'TIFR1_ICF1': '$20', # Input Capture Flag 1
+ 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
+ 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
+ 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
+
+# Module TIMER_COUNTER_2
+ 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
+ 'TCCR2A_FOC2A': '$80', # Force Output Compare A
+ 'TCCR2A_WGM20': '$40', # Waveform Generation Mode
+ 'TCCR2A_COM2A': '$30', # Compare Output Mode bits
+ 'TCCR2A_WGM21': '$8', # Waveform Generation Mode
+ 'TCCR2A_CS2': '$7', # Clock Select bits
+ 'TCNT2' : '$b2', # Timer/Counter2
+ 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
+ 'TIMSK2' : '$70', # Timer/Counter2 Interrupt Mask
+ 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
+ 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
+ 'TIFR2' : '$37', # Timer/Counter2 Interrupt Flag
+ 'TIFR2_OCF2A': '$2', # Timer/Counter2 Output Compare
+ 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_PSR2': '$2', # Prescaler Reset Timer/Counter2
+ 'ASSR' : '$b6', # Asynchronous Status Register
+ 'ASSR_EXCLK': '$10', # Enable External Clock Interrup
+ 'ASSR_AS2': '$8', # AS2: Asynchronous Timer/Counte
+ 'ASSR_TCN2UB': '$4', # TCN2UB: Timer/Counter2 Update
+ 'ASSR_OCR2UB': '$2', # Output Compare Register2 Updat
+ 'ASSR_TCR2UB': '$1', # TCR2UB: Timer/Counter Control
+
+# Module WATCHDOG
+ 'WDTCR' : '$60', # Watchdog Timer Control Registe
+ 'WDTCR_WDCE': '$10', # Watchdog Change Enable
+ 'WDTCR_WDE': '$8', # Watch Dog Enable
+ 'WDTCR_WDP': '$7', # Watch Dog Timer Prescaler bits
+
+# Module EEPROM
+ 'EEAR' : '$41', # EEPROM Read/Write Access Byte
+ 'EEDR' : '$40', # EEPROM Data Register
+ 'EECR' : '$3f', # EEPROM Control Register
+ 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
+ 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
+ 'EECR_EEWE': '$2', # EEPROM Write Enable
+ 'EECR_EERE': '$1', # EEPROM Read Enable
+
+# Module SPI
+ 'SPCR' : '$4c', # SPI Control Register
+ 'SPCR_SPIE': '$80', # SPI Interrupt Enable
+ 'SPCR_SPE': '$40', # SPI Enable
+ 'SPCR_DORD': '$20', # Data Order
+ 'SPCR_MSTR': '$10', # Master/Slave Select
+ 'SPCR_CPOL': '$8', # Clock polarity
+ 'SPCR_CPHA': '$4', # Clock Phase
+ 'SPCR_SPR': '$3', # SPI Clock Rate Selects
+ 'SPSR' : '$4d', # SPI Status Register
+ 'SPSR_SPIF': '$80', # SPI Interrupt Flag
+ 'SPSR_WCOL': '$40', # Write Collision Flag
+ 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
+ 'SPDR' : '$4e', # SPI Data Register
+
+# Module PORTA
+ 'PORTA' : '$22', # Port A Data Register
+ 'DDRA' : '$21', # Port A Data Direction Register
+ 'PINA' : '$20', # Port A Input Pins
+
+# Module PORTB
+ 'PORTB' : '$25', # Port B Data Register
+ 'DDRB' : '$24', # Port B Data Direction Register
+ 'PINB' : '$23', # Port B Input Pins
+
+# Module PORTC
+ 'PORTC' : '$28', # Port C Data Register
+ 'DDRC' : '$27', # Port C Data Direction Register
+ 'PINC' : '$26', # Port C Input Pins
+
+# Module PORTD
+ 'PORTD' : '$2b', # Port D Data Register
+ 'DDRD' : '$2a', # Port D Data Direction Register
+ 'PIND' : '$29', # Port D Input Pins
+
+# Module ANALOG_COMPARATOR
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
+ 'ACSR' : '$50', # Analog Comparator Control And
+ 'ACSR_ACD': '$80', # Analog Comparator Disable
+ 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
+ 'ACSR_ACO': '$20', # Analog Compare Output
+ 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
+ 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
+ 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
+ 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
+ 'DIDR1' : '$7f', # Digital Input Disable Register
+ 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
+ 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
+
+# Module PORTE
+ 'PORTE' : '$2e', # Data Register, Port E
+ 'DDRE' : '$2d', # Data Direction Register, Port
+ 'PINE' : '$2c', # Input Pins, Port E
+
+# Module PORTF
+ 'PORTF' : '$31', # Data Register, Port F
+ 'DDRF' : '$30', # Data Direction Register, Port
+ 'PINF' : '$2f', # Input Pins, Port F
+
+# Module PORTG
+ 'PORTG' : '$34', # Port G Data Register
+ 'DDRG' : '$33', # Port G Data Direction Register
+ 'PING' : '$32', # Port G Input Pins
+
+# Module JTAG
+ 'OCDR' : '$51', # On-Chip Debug Related Register
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_JTD': '$80', # JTAG Interface Disable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+
+# Module EXTERNAL_INTERRUPT
+ 'EICRA' : '$69', # External Interrupt Control Reg
+ 'EICRA_ISC01': '$2', # External Interrupt Sense Contr
+ 'EICRA_ISC00': '$1', # External Interrupt Sense Contr
+ 'EIMSK' : '$3d', # External Interrupt Mask Regist
+ 'EIMSK_PCIE': '$f0', # Pin Change Interrupt Enables
+ 'EIMSK_INT0': '$1', # External Interrupt Request 0 E
+ 'EIFR' : '$3c', # External Interrupt Flag Regist
+ 'EIFR_PCIF': '$f0', # Pin Change Interrupt Flags
+ 'EIFR_INTF0': '$1', # External Interrupt Flag 0
+ 'PCMSK3' : '$73', # Pin Change Mask Register 3
+ 'PCMSK2' : '$6d', # Pin Change Mask Register 2
+ 'PCMSK1' : '$6c', # Pin Change Mask Register 1
+ 'PCMSK0' : '$6b', # Pin Change Mask Register 0
+
+# Module USI
+ 'USIDR' : '$ba', # USI Data Register
+ 'USISR' : '$b9', # USI Status Register
+ 'USISR_USISIF': '$80', # Start Condition Interrupt Flag
+ 'USISR_USIOIF': '$40', # Counter Overflow Interrupt Fla
+ 'USISR_USIPF': '$20', # Stop Condition Flag
+ 'USISR_USIDC': '$10', # Data Output Collision
+ 'USISR_USICNT': '$f', # USI Counter Value Bits
+ 'USICR' : '$b8', # USI Control Register
+ 'USICR_USISIE': '$80', # Start Condition Interrupt Enab
+ 'USICR_USIOIE': '$40', # Counter Overflow Interrupt Ena
+ 'USICR_USIWM': '$30', # USI Wire Mode Bits
+ 'USICR_USICS': '$c', # USI Clock Source Select Bits
+ 'USICR_USICLK': '$2', # Clock Strobe
+ 'USICR_USITC': '$1', # Toggle Clock Port Pin
+
+# Module AD_CONVERTER
+ 'ADMUX' : '$7c', # The ADC multiplexer Selection
+ 'ADMUX_REFS': '$c0', # Reference Selection Bits
+ 'ADMUX_ADLAR': '$20', # Left Adjust Result
+ 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
+ 'ADCSRA' : '$7a', # The ADC Control and Status reg
+ 'ADCSRA_ADEN': '$80', # ADC Enable
+ 'ADCSRA_ADSC': '$40', # ADC Start Conversion
+ 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
+ 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
+ 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
+ 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
+ 'ADC' : '$78', # ADC Data Register Bytes
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Sources
+ 'DIDR0' : '$7e', # Digital Input Disable Register
+ 'DIDR0_ADC7D': '$80', # ADC7 Digital input Disable
+ 'DIDR0_ADC6D': '$40', # ADC6 Digital input Disable
+ 'DIDR0_ADC5D': '$20', # ADC5 Digital input Disable
+ 'DIDR0_ADC4D': '$10', # ADC4 Digital input Disable
+ 'DIDR0_ADC3D': '$8', # ADC3 Digital input Disable
+ 'DIDR0_ADC2D': '$4', # ADC2 Digital input Disable
+ 'DIDR0_ADC1D': '$2', # ADC1 Digital input Disable
+ 'DIDR0_ADC0D': '$1', # ADC0 Digital input Disable
+
+# Module BOOT_LOAD
+ 'SPMCSR' : '$57', # Store Program Memory Control R
+ 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
+ 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
+ 'SPMCSR_RWWSRE': '$10', # Read While Write section read
+ 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
+ 'SPMCSR_PGWRT': '$4', # Page Write
+ 'SPMCSR_PGERS': '$2', # Page Erase
+ 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
+
+# Module USART0
+ 'UDR0' : '$c6', # USART I/O Data Register
+ 'UCSR0A' : '$c0', # USART Control and Status Regis
+ 'UCSR0A_RXC0': '$80', # USART Receive Complete
+ 'UCSR0A_TXC0': '$40', # USART Transmit Complete
+ 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
+ 'UCSR0A_FE0': '$10', # Framing Error
+ 'UCSR0A_DOR0': '$8', # Data OverRun
+ 'UCSR0A_UPE0': '$4', # USART Parity Error
+ 'UCSR0A_U2X0': '$2', # Double the USART Transmission
+ 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
+ 'UCSR0B' : '$c1', # USART Control and Status Regis
+ 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
+ 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
+ 'UCSR0B_UDRIE0': '$20', # USART Data Register Empty Inte
+ 'UCSR0B_RXEN0': '$10', # Receiver Enable
+ 'UCSR0B_TXEN0': '$8', # Transmitter Enable
+ 'UCSR0B_UCSZ02': '$4', # Character Size
+ 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
+ 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
+ 'UCSR0C' : '$c2', # USART Control and Status Regis
+ 'UCSR0C_UMSEL0': '$40', # USART Mode Select
+ 'UCSR0C_UPM0': '$30', # Parity Mode Bits
+ 'UCSR0C_USBS0': '$8', # Stop Bit Select
+ 'UCSR0C_UCSZ0': '$6', # Character Size
+ 'UCSR0C_UCPOL0': '$1', # Clock Polarity
+ 'UBRR0' : '$c4', # USART Baud Rate Register Byte
+
+# Module PORTH
+ 'PORTH' : '$da', # PORT H Data Register
+ 'DDRH' : '$d9', # PORT H Data Direction Register
+ 'PINH' : '$d8', # PORT H Input Pins
+
+# Module PORTJ
+ 'PORTJ' : '$dd', # PORT J Data Register
+ 'DDRJ' : '$dc', # PORT J Data Direction Register
+ 'PINJ' : '$db', # PORT J Input Pins
+
+# Module CPU
+ 'SREG' : '$5f', # Status Register
+ 'SREG_I': '$80', # Global Interrupt Enable
+ 'SREG_T': '$40', # Bit Copy Storage
+ 'SREG_H': '$20', # Half Carry Flag
+ 'SREG_S': '$10', # Sign Bit
+ 'SREG_V': '$8', # Two's Complement Overflow Flag
+ 'SREG_N': '$4', # Negative Flag
+ 'SREG_Z': '$2', # Zero Flag
+ 'SREG_C': '$1', # Carry Flag
+ 'SP' : '$5d', # Stack Pointer
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_JTD': '$80', # JTAG Interface Disable
+ 'MCUCR_BODS': '$40', # BOD Sleep
+ 'MCUCR_BODSE': '$20', # BOD Sleep Enable
+ 'MCUCR_PUD': '$10', # Pull-up disable
+ 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
+ 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+ 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
+ 'MCUSR_BORF': '$4', # Brown-out Reset Flag
+ 'MCUSR_EXTRF': '$2', # External Reset Flag
+ 'MCUSR_PORF': '$1', # Power-on reset flag
+ 'OSCCAL' : '$66', # Oscillator Calibration Value
+ 'CLKPR' : '$61', # Clock Prescale Register
+ 'CLKPR_CLKPCE': '$80', # Clock Prescaler Change Enable
+ 'CLKPR_CLKPS': '$f', # Clock Prescaler Select Bits
+ 'PRR' : '$64', # Power Reduction Register
+ 'PRR_PRLCD': '$10', # Power Reduction LCD
+ 'PRR_PRTIM1': '$8', # Power Reduction Timer/Counter1
+ 'PRR_PRSPI': '$4', # Power Reduction Serial Periphe
+ 'PRR_PRUSART0': '$2', # Power Reduction USART
+ 'PRR_PRADC': '$1', # Power Reduction ADC
+ 'SMCR' : '$53', # Sleep Mode Control Register
+ 'SMCR_SM': '$e', # Sleep Mode Select bits
+ 'SMCR_SE': '$1', # Sleep Enable
+ 'GPIOR2' : '$4b', # General Purpose IO Register 2
+ 'GPIOR1' : '$4a', # General Purpose IO Register 1
+ 'GPIOR0' : '$3e', # General Purpose IO Register 0
+
+ '__amforth_dummy':'0'
+}
diff --git a/amforth-6.5/avr8/devices/atmega3250a/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega3250a/words/no-jtag.asm
new file mode 100644
index 0000000..352a4bb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega3250a/words/no-jtag.asm
@@ -0,0 +1,14 @@
+; ( -- )
+; ( -- )
+; MCU
+; disable jtag at runtime
+VE_NOJTAG:
+ .dw $FF05
+ .db "-jtag",0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOJTAG
+XT_NOJTAG:
+ .dw PFA_NOJTAG
+PFA_NOJTAG:
+
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega3250a/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega3250a/words/no-wdt.asm
new file mode 100644
index 0000000..4a12261
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega3250a/words/no-wdt.asm
@@ -0,0 +1,22 @@
+; ( -- )
+; MCU
+; disable watch dog timer at runtime
+VE_NOWDT:
+ .dw $ff04
+ .db "-wdt"
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOWDT
+XT_NOWDT:
+ .dw PFA_NOWDT
+PFA_NOWDT:
+
+; Reset WDT
+ wdr
+; Write logical one to WDTOE and WDE
+ in_ temp1, WDTCR
+ ori temp1, (1<<WDTOE)|(1<<WDE)
+ out WDTCR, temp1
+; Turn off WDT
+ ldi temp1, (0<<WDE)
+ out_ WDTCR, temp1
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega3250a/words/sleep.asm b/amforth-6.5/avr8/devices/atmega3250a/words/sleep.asm
new file mode 100644
index 0000000..256249c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega3250a/words/sleep.asm
@@ -0,0 +1,19 @@
+; ( mode -- )
+; MCU
+; put the controller into the specified sleep mode
+VE_SLEEP:
+ .dw $ff05
+ .db "sleep", 0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_SLEEP
+XT_SLEEP:
+ .dw PFA_SLEEP
+PFA_SLEEP:
+ andi tosl, 7 ; leave only legal mode bits
+ lsl tosl ; move to correct location (bits 3-1)
+ ori tosl, 1 ; set the SE bit
+ out_ SMCR, tosl ; set the sleep config
+ sleep ; nighty-night
+ out_ SMCR, zerol ; 0 protects against accidental sleeps
+ loadtos ; pop argument from stack
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega3250p/atmega3250p.frt b/amforth-6.5/avr8/devices/atmega3250p/atmega3250p.frt
new file mode 100644
index 0000000..cf321ee
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega3250p/atmega3250p.frt
@@ -0,0 +1,292 @@
+\ Partname: ATmega3250P
+\ generated automatically
+
+\ TIMER_COUNTER_0
+&68 constant TCCR0A \ Timer/Counter0 Control Register
+ $80 constant TCCR0A_FOC0A \ Force Output Compare
+ $40 constant TCCR0A_WGM00 \ Waveform Generation Mode 0
+ $30 constant TCCR0A_COM0A \ Compare Match Output Modes
+ $08 constant TCCR0A_WGM01 \ Waveform Generation Mode 1
+ $07 constant TCCR0A_CS0 \ Clock Selects
+&70 constant TCNT0 \ Timer/Counter0
+&71 constant OCR0A \ Timer/Counter0 Output Compare Register
+&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
+ $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match Interrupt Enable
+ $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
+&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
+ $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0
+ $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
+&67 constant GTCCR \ General Timer/Control Register
+ $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
+ $01 constant GTCCR_PSR310 \ Prescaler Reset Timer/Counter1 and Timer/Counter0
+\ TIMER_COUNTER_1
+&128 constant TCCR1A \ Timer/Counter1 Control Register A
+ $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
+ $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
+ $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
+&129 constant TCCR1B \ Timer/Counter1 Control Register B
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
+ $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
+&130 constant TCCR1C \ Timer/Counter 1 Control Register C
+ $80 constant TCCR1C_FOC1A \ Force Output Compare 1A
+ $40 constant TCCR1C_FOC1B \ Force Output Compare 1B
+&132 constant TCNT1 \ Timer/Counter1 Bytes
+&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
+&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
+&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
+&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
+ $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
+ $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
+ $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
+ $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
+&54 constant TIFR1 \ Timer/Counter1 Interrupt Flag register
+ $20 constant TIFR1_ICF1 \ Input Capture Flag 1
+ $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
+ $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
+ $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
+\ TIMER_COUNTER_2
+&176 constant TCCR2A \ Timer/Counter2 Control Register
+ $80 constant TCCR2A_FOC2A \ Force Output Compare A
+ $40 constant TCCR2A_WGM20 \ Waveform Generation Mode
+ $30 constant TCCR2A_COM2A \ Compare Output Mode bits
+ $08 constant TCCR2A_WGM21 \ Waveform Generation Mode
+ $07 constant TCCR2A_CS2 \ Clock Select bits
+&178 constant TCNT2 \ Timer/Counter2
+&179 constant OCR2A \ Timer/Counter2 Output Compare Register
+&112 constant TIMSK2 \ Timer/Counter2 Interrupt Mask register
+ $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match Interrupt Enable
+ $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
+&55 constant TIFR2 \ Timer/Counter2 Interrupt Flag Register
+ $02 constant TIFR2_OCF2A \ Timer/Counter2 Output Compare Flag 2
+ $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
+&182 constant ASSR \ Asynchronous Status Register
+ $10 constant ASSR_EXCLK \ Enable External Clock Interrupt
+ $08 constant ASSR_AS2 \ AS2: Asynchronous Timer/Counter2
+ $04 constant ASSR_TCN2UB \ TCN2UB: Timer/Counter2 Update Busy
+ $02 constant ASSR_OCR2UB \ Output Compare Register2 Update Busy
+ $01 constant ASSR_TCR2UB \ TCR2UB: Timer/Counter Control Register2 Update Busy
+\ WATCHDOG
+&96 constant WDTCR \ Watchdog Timer Control Register
+ $10 constant WDTCR_WDCE \ Watchdog Change Enable
+ $08 constant WDTCR_WDE \ Watch Dog Enable
+ $07 constant WDTCR_WDP \ Watch Dog Timer Prescaler bits
+\ EEPROM
+&65 constant EEAR \ EEPROM Read/Write Access Bytes
+&64 constant EEDR \ EEPROM Data Register
+&63 constant EECR \ EEPROM Control Register
+ $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
+ $04 constant EECR_EEMWE \ EEPROM Master Write Enable
+ $02 constant EECR_EEWE \ EEPROM Write Enable
+ $01 constant EECR_EERE \ EEPROM Read Enable
+\ SPI
+&76 constant SPCR \ SPI Control Register
+ $80 constant SPCR_SPIE \ SPI Interrupt Enable
+ $40 constant SPCR_SPE \ SPI Enable
+ $20 constant SPCR_DORD \ Data Order
+ $10 constant SPCR_MSTR \ Master/Slave Select
+ $08 constant SPCR_CPOL \ Clock polarity
+ $04 constant SPCR_CPHA \ Clock Phase
+ $03 constant SPCR_SPR \ SPI Clock Rate Selects
+&77 constant SPSR \ SPI Status Register
+ $80 constant SPSR_SPIF \ SPI Interrupt Flag
+ $40 constant SPSR_WCOL \ Write Collision Flag
+ $01 constant SPSR_SPI2X \ Double SPI Speed Bit
+&78 constant SPDR \ SPI Data Register
+\ PORTA
+&34 constant PORTA \ Port A Data Register
+&33 constant DDRA \ Port A Data Direction Register
+&32 constant PINA \ Port A Input Pins
+\ PORTB
+&37 constant PORTB \ Port B Data Register
+&36 constant DDRB \ Port B Data Direction Register
+&35 constant PINB \ Port B Input Pins
+\ PORTC
+&40 constant PORTC \ Port C Data Register
+&39 constant DDRC \ Port C Data Direction Register
+&38 constant PINC \ Port C Input Pins
+\ PORTD
+&43 constant PORTD \ Port D Data Register
+&42 constant DDRD \ Port D Data Direction Register
+&41 constant PIND \ Port D Input Pins
+\ ANALOG_COMPARATOR
+&123 constant ADCSRB \ ADC Control and Status Register B
+ $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer Enable
+&80 constant ACSR \ Analog Comparator Control And Status Register
+ $80 constant ACSR_ACD \ Analog Comparator Disable
+ $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
+ $20 constant ACSR_ACO \ Analog Compare Output
+ $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
+ $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
+ $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
+ $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
+&127 constant DIDR1 \ Digital Input Disable Register 1
+ $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
+ $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
+\ PORTE
+&46 constant PORTE \ Data Register, Port E
+&45 constant DDRE \ Data Direction Register, Port E
+&44 constant PINE \ Input Pins, Port E
+\ PORTF
+&49 constant PORTF \ Data Register, Port F
+&48 constant DDRF \ Data Direction Register, Port F
+&47 constant PINF \ Input Pins, Port F
+\ PORTG
+&52 constant PORTG \ Port G Data Register
+&51 constant DDRG \ Port G Data Direction Register
+&50 constant PING \ Port G Input Pins
+\ JTAG
+&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
+&85 constant MCUCR \ MCU Control Register
+ $80 constant MCUCR_JTD \ JTAG Interface Disable
+&84 constant MCUSR \ MCU Status Register
+ $10 constant MCUSR_JTRF \ JTAG Reset Flag
+\ EXTERNAL_INTERRUPT
+&105 constant EICRA \ External Interrupt Control Register A
+ $02 constant EICRA_ISC01 \ External Interrupt Sense Control 0 Bit 1
+ $01 constant EICRA_ISC00 \ External Interrupt Sense Control 0 Bit 0
+&61 constant EIMSK \ External Interrupt Mask Register
+ $F0 constant EIMSK_PCIE \ Pin Change Interrupt Enables
+ $01 constant EIMSK_INT0 \ External Interrupt Request 0 Enable
+&60 constant EIFR \ External Interrupt Flag Register
+ $F0 constant EIFR_PCIF \ Pin Change Interrupt Flags
+ $01 constant EIFR_INTF0 \ External Interrupt Flag 0
+&115 constant PCMSK3 \ Pin Change Mask Register 3
+&109 constant PCMSK2 \ Pin Change Mask Register 2
+&108 constant PCMSK1 \ Pin Change Mask Register 1
+&107 constant PCMSK0 \ Pin Change Mask Register 0
+\ USI
+&186 constant USIDR \ USI Data Register
+&185 constant USISR \ USI Status Register
+ $80 constant USISR_USISIF \ Start Condition Interrupt Flag
+ $40 constant USISR_USIOIF \ Counter Overflow Interrupt Flag
+ $20 constant USISR_USIPF \ Stop Condition Flag
+ $10 constant USISR_USIDC \ Data Output Collision
+ $0F constant USISR_USICNT \ USI Counter Value Bits
+&184 constant USICR \ USI Control Register
+ $80 constant USICR_USISIE \ Start Condition Interrupt Enable
+ $40 constant USICR_USIOIE \ Counter Overflow Interrupt Enable
+ $30 constant USICR_USIWM \ USI Wire Mode Bits
+ $0C constant USICR_USICS \ USI Clock Source Select Bits
+ $02 constant USICR_USICLK \ Clock Strobe
+ $01 constant USICR_USITC \ Toggle Clock Port Pin
+\ AD_CONVERTER
+&124 constant ADMUX \ The ADC multiplexer Selection Register
+ $C0 constant ADMUX_REFS \ Reference Selection Bits
+ $20 constant ADMUX_ADLAR \ Left Adjust Result
+ $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
+&122 constant ADCSRA \ The ADC Control and Status register
+ $80 constant ADCSRA_ADEN \ ADC Enable
+ $40 constant ADCSRA_ADSC \ ADC Start Conversion
+ $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
+ $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
+ $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
+ $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
+&120 constant ADC \ ADC Data Register Bytes
+&126 constant DIDR0 \ Digital Input Disable Register 0
+ $80 constant DIDR0_ADC7D \ ADC7 Digital input Disable
+ $40 constant DIDR0_ADC6D \ ADC6 Digital input Disable
+ $20 constant DIDR0_ADC5D \ ADC5 Digital input Disable
+ $10 constant DIDR0_ADC4D \ ADC4 Digital input Disable
+ $08 constant DIDR0_ADC3D \ ADC3 Digital input Disable
+ $04 constant DIDR0_ADC2D \ ADC2 Digital input Disable
+ $02 constant DIDR0_ADC1D \ ADC1 Digital input Disable
+ $01 constant DIDR0_ADC0D \ ADC0 Digital input Disable
+\ BOOT_LOAD
+&87 constant SPMCSR \ Store Program Memory Control Register
+ $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
+ $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
+ $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
+ $04 constant SPMCSR_PGWRT \ Page Write
+ $02 constant SPMCSR_PGERS \ Page Erase
+ $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
+\ USART0
+&198 constant UDR0 \ USART I/O Data Register
+&192 constant UCSR0A \ USART Control and Status Register A
+ $80 constant UCSR0A_RXC0 \ USART Receive Complete
+ $40 constant UCSR0A_TXC0 \ USART Transmit Complete
+ $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
+ $10 constant UCSR0A_FE0 \ Framing Error
+ $08 constant UCSR0A_DOR0 \ Data OverRun
+ $04 constant UCSR0A_UPE0 \ USART Parity Error
+ $02 constant UCSR0A_U2X0 \ Double the USART Transmission Speed
+ $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
+&193 constant UCSR0B \ USART Control and Status Register B
+ $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
+ $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
+ $20 constant UCSR0B_UDRIE0 \ USART Data Register Empty Interrupt Enable
+ $10 constant UCSR0B_RXEN0 \ Receiver Enable
+ $08 constant UCSR0B_TXEN0 \ Transmitter Enable
+ $04 constant UCSR0B_UCSZ02 \ Character Size
+ $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
+ $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
+&194 constant UCSR0C \ USART Control and Status Register C
+ $40 constant UCSR0C_UMSEL0 \ USART Mode Select
+ $30 constant UCSR0C_UPM0 \ Parity Mode Bits
+ $08 constant UCSR0C_USBS0 \ Stop Bit Select
+ $06 constant UCSR0C_UCSZ0 \ Character Size
+ $01 constant UCSR0C_UCPOL0 \ Clock Polarity
+&196 constant UBRR0 \ USART Baud Rate Register Bytes
+\ PORTH
+&218 constant PORTH \ PORT H Data Register
+&217 constant DDRH \ PORT H Data Direction Register
+&216 constant PINH \ PORT H Input Pins
+\ PORTJ
+&221 constant PORTJ \ PORT J Data Register
+&220 constant DDRJ \ PORT J Data Direction Register
+&219 constant PINJ \ PORT J Input Pins
+\ CPU
+&95 constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ $08 constant SREG_V \ Two's Complement Overflow Flag
+ $04 constant SREG_N \ Negative Flag
+ $02 constant SREG_Z \ Zero Flag
+ $01 constant SREG_C \ Carry Flag
+&93 constant SP \ Stack Pointer
+&102 constant OSCCAL \ Oscillator Calibration Value
+&97 constant CLKPR \ Clock Prescale Register
+ $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable
+ $0F constant CLKPR_CLKPS \ Clock Prescaler Select Bits
+&100 constant PRR \ Power Reduction Register
+ $10 constant PRR_PRLCD \ Power Reduction LCD
+ $08 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
+ $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
+ $02 constant PRR_PRUSART0 \ Power Reduction USART
+ $01 constant PRR_PRADC \ Power Reduction ADC
+&83 constant SMCR \ Sleep Mode Control Register
+ $0E constant SMCR_SM \ Sleep Mode Select bits
+ $01 constant SMCR_SE \ Sleep Enable
+&75 constant GPIOR2 \ General Purpose IO Register 2
+&74 constant GPIOR1 \ General Purpose IO Register 1
+&62 constant GPIOR0 \ General Purpose IO Register 0
+
+\ Interrupts
+&2 constant INT0Addr \ External Interrupt Request 0
+&4 constant PCINT0Addr \ Pin Change Interrupt Request 0
+&6 constant PCINT1Addr \ Pin Change Interrupt Request 1
+&8 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
+&10 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
+&12 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+&14 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
+&16 constant TIMER1_COMPBAddr \ Timer/Counter Compare Match B
+&18 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+&20 constant TIMER0_COMPAddr \ Timer/Counter0 Compare Match
+&22 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
+&24 constant SPI__STCAddr \ SPI Serial Transfer Complete
+&26 constant USART__RXAddr \ USART, Rx Complete
+&28 constant USART__UDREAddr \ USART Data register Empty
+&30 constant USART0__TXAddr \ USART0, Tx Complete
+&32 constant USI_STARTAddr \ USI Start Condition
+&34 constant USI_OVERFLOWAddr \ USI Overflow
+&36 constant ANALOG_COMPAddr \ Analog Comparator
+&38 constant ADCAddr \ ADC Conversion Complete
+&40 constant EE_READYAddr \ EEPROM Ready
+&42 constant SPM_READYAddr \ Store Program Memory Read
+&44 constant NOT_USEDAddr \ RESERVED
+&46 constant PCINT2Addr \ Pin Change Interrupt Request 2
+&48 constant PCINT3Addr \ Pin Change Interrupt Request 3
diff --git a/amforth-6.5/avr8/devices/atmega3250p/device.asm b/amforth-6.5/avr8/devices/atmega3250p/device.asm
new file mode 100644
index 0000000..13b7973
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega3250p/device.asm
@@ -0,0 +1,114 @@
+; Partname: ATmega3250P
+; generated automatically, do not edit
+
+.nolist
+ .include "m3250Pdef.inc"
+.list
+
+.equ ramstart = 256
+.equ CELLSIZE = 2
+.macro readflashcell
+ lsl zl
+ rol zh
+ lpm @0, Z+
+ lpm @1, Z+
+.endmacro
+.macro writeflashcell
+ lsl zl
+ rol zh
+.endmacro
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_TIMER_COUNTER_2 = 0
+.set WANT_WATCHDOG = 0
+.set WANT_EEPROM = 0
+.set WANT_SPI = 0
+.set WANT_PORTA = 0
+.set WANT_PORTB = 0
+.set WANT_PORTC = 0
+.set WANT_PORTD = 0
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_PORTE = 0
+.set WANT_PORTF = 0
+.set WANT_PORTG = 0
+.set WANT_JTAG = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_USI = 0
+.set WANT_AD_CONVERTER = 0
+.set WANT_BOOT_LOAD = 0
+.set WANT_USART0 = 0
+.set WANT_PORTH = 0
+.set WANT_PORTJ = 0
+.set WANT_CPU = 0
+.equ intvecsize = 2 ; please verify; flash size: 32768 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.org 2
+ rcall isr ; External Interrupt Request 0
+.org 4
+ rcall isr ; Pin Change Interrupt Request 0
+.org 6
+ rcall isr ; Pin Change Interrupt Request 1
+.org 8
+ rcall isr ; Timer/Counter2 Compare Match
+.org 10
+ rcall isr ; Timer/Counter2 Overflow
+.org 12
+ rcall isr ; Timer/Counter1 Capture Event
+.org 14
+ rcall isr ; Timer/Counter1 Compare Match A
+.org 16
+ rcall isr ; Timer/Counter Compare Match B
+.org 18
+ rcall isr ; Timer/Counter1 Overflow
+.org 20
+ rcall isr ; Timer/Counter0 Compare Match
+.org 22
+ rcall isr ; Timer/Counter0 Overflow
+.org 24
+ rcall isr ; SPI Serial Transfer Complete
+.org 26
+ rcall isr ; USART, Rx Complete
+.org 28
+ rcall isr ; USART Data register Empty
+.org 30
+ rcall isr ; USART0, Tx Complete
+.org 32
+ rcall isr ; USI Start Condition
+.org 34
+ rcall isr ; USI Overflow
+.org 36
+ rcall isr ; Analog Comparator
+.org 38
+ rcall isr ; ADC Conversion Complete
+.org 40
+ rcall isr ; EEPROM Ready
+.org 42
+ rcall isr ; Store Program Memory Read
+.org 44
+ rcall isr ; RESERVED
+.org 46
+ rcall isr ; Pin Change Interrupt Request 2
+.org 48
+ rcall isr ; Pin Change Interrupt Request 3
+.equ INTVECTORS = 25
+.nooverlap
+
+; compatability layer (maybe empty)
+.equ EEPE = EEWE
+.equ EEMPE = EEMWE
+
+; controller data area, environment query mcu-info
+mcu_info:
+mcu_ramsize:
+ .dw 2048
+mcu_eepromsize:
+ .dw 1024
+mcu_maxdp:
+ .dw 28672
+mcu_numints:
+ .dw 25
+mcu_name:
+ .dw 11
+ .db "ATmega3250P",0
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega3250p/device.inc b/amforth-6.5/avr8/devices/atmega3250p/device.inc
new file mode 100644
index 0000000..cd120e1
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega3250p/device.inc
@@ -0,0 +1,1152 @@
+; Partname: ATmega3250P
+; generated automatically, no not edit
+
+.if WANT_TIMER_COUNTER_0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Control Register
+VE_TCCR0A:
+ .dw $ff06
+ .db "TCCR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0A
+XT_TCCR0A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0A:
+ .dw 68
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw 70
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0A:
+ .dw $ff05
+ .db "OCR0A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0A
+XT_OCR0A:
+ .dw PFA_DOVARIABLE
+PFA_OCR0A:
+ .dw 71
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Mask Register
+VE_TIMSK0:
+ .dw $ff06
+ .db "TIMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK0
+XT_TIMSK0:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK0:
+ .dw 110
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Flag register
+VE_TIFR0:
+ .dw $ff05
+ .db "TIFR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR0
+XT_TIFR0:
+ .dw PFA_DOVARIABLE
+PFA_TIFR0:
+ .dw 53
+; ( -- addr ) System Constant
+; R( -- )
+; General Timer/Control Register
+VE_GTCCR:
+ .dw $ff05
+ .db "GTCCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GTCCR
+XT_GTCCR:
+ .dw PFA_DOVARIABLE
+PFA_GTCCR:
+ .dw 67
+
+.endif
+.if WANT_TIMER_COUNTER_1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw 128
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw 129
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter 1 Control Register C
+VE_TCCR1C:
+ .dw $ff06
+ .db "TCCR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1C
+XT_TCCR1C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1C:
+ .dw 130
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Bytes
+VE_TCNT1:
+ .dw $ff05
+ .db "TCNT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1
+XT_TCNT1:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1:
+ .dw 132
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register A Bytes
+VE_OCR1A:
+ .dw $ff05
+ .db "OCR1A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1A
+XT_OCR1A:
+ .dw PFA_DOVARIABLE
+PFA_OCR1A:
+ .dw 136
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register B Bytes
+VE_OCR1B:
+ .dw $ff05
+ .db "OCR1B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1B
+XT_OCR1B:
+ .dw PFA_DOVARIABLE
+PFA_OCR1B:
+ .dw 138
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Bytes
+VE_ICR1:
+ .dw $ff04
+ .db "ICR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1
+XT_ICR1:
+ .dw PFA_DOVARIABLE
+PFA_ICR1:
+ .dw 134
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Mask Register
+VE_TIMSK1:
+ .dw $ff06
+ .db "TIMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK1
+XT_TIMSK1:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK1:
+ .dw 111
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Flag register
+VE_TIFR1:
+ .dw $ff05
+ .db "TIFR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR1
+XT_TIFR1:
+ .dw PFA_DOVARIABLE
+PFA_TIFR1:
+ .dw 54
+
+.endif
+.if WANT_TIMER_COUNTER_2 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register
+VE_TCCR2A:
+ .dw $ff06
+ .db "TCCR2A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2A
+XT_TCCR2A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2A:
+ .dw 176
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2
+VE_TCNT2:
+ .dw $ff05
+ .db "TCNT2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT2
+XT_TCNT2:
+ .dw PFA_DOVARIABLE
+PFA_TCNT2:
+ .dw 178
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register
+VE_OCR2A:
+ .dw $ff05
+ .db "OCR2A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2A
+XT_OCR2A:
+ .dw PFA_DOVARIABLE
+PFA_OCR2A:
+ .dw 179
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Interrupt Mask register
+VE_TIMSK2:
+ .dw $ff06
+ .db "TIMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK2
+XT_TIMSK2:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK2:
+ .dw 112
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Interrupt Flag Register
+VE_TIFR2:
+ .dw $ff05
+ .db "TIFR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR2
+XT_TIFR2:
+ .dw PFA_DOVARIABLE
+PFA_TIFR2:
+ .dw 55
+; ( -- addr ) System Constant
+; R( -- )
+; Asynchronous Status Register
+VE_ASSR:
+ .dw $ff04
+ .db "ASSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ASSR
+XT_ASSR:
+ .dw PFA_DOVARIABLE
+PFA_ASSR:
+ .dw 182
+
+.endif
+.if WANT_WATCHDOG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCR:
+ .dw $ff05
+ .db "WDTCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCR
+XT_WDTCR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCR:
+ .dw 96
+
+.endif
+.if WANT_EEPROM == 1
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Read/Write Access Bytes
+VE_EEAR:
+ .dw $ff04
+ .db "EEAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEAR
+XT_EEAR:
+ .dw PFA_DOVARIABLE
+PFA_EEAR:
+ .dw 65
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw 64
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw 63
+
+.endif
+.if WANT_SPI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR:
+ .dw $ff04
+ .db "SPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR
+XT_SPCR:
+ .dw PFA_DOVARIABLE
+PFA_SPCR:
+ .dw 76
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR:
+ .dw $ff04
+ .db "SPSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR
+XT_SPSR:
+ .dw PFA_DOVARIABLE
+PFA_SPSR:
+ .dw 77
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR:
+ .dw $ff04
+ .db "SPDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR
+XT_SPDR:
+ .dw PFA_DOVARIABLE
+PFA_SPDR:
+ .dw 78
+
+.endif
+.if WANT_PORTA == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Register
+VE_PORTA:
+ .dw $ff05
+ .db "PORTA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTA
+XT_PORTA:
+ .dw PFA_DOVARIABLE
+PFA_PORTA:
+ .dw 34
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Direction Register
+VE_DDRA:
+ .dw $ff04
+ .db "DDRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRA
+XT_DDRA:
+ .dw PFA_DOVARIABLE
+PFA_DDRA:
+ .dw 33
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Input Pins
+VE_PINA:
+ .dw $ff04
+ .db "PINA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINA
+XT_PINA:
+ .dw PFA_DOVARIABLE
+PFA_PINA:
+ .dw 32
+
+.endif
+.if WANT_PORTB == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw 37
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw 36
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw 35
+
+.endif
+.if WANT_PORTC == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Register
+VE_PORTC:
+ .dw $ff05
+ .db "PORTC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTC
+XT_PORTC:
+ .dw PFA_DOVARIABLE
+PFA_PORTC:
+ .dw 40
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Direction Register
+VE_DDRC:
+ .dw $ff04
+ .db "DDRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRC
+XT_DDRC:
+ .dw PFA_DOVARIABLE
+PFA_DDRC:
+ .dw 39
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Input Pins
+VE_PINC:
+ .dw $ff04
+ .db "PINC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINC
+XT_PINC:
+ .dw PFA_DOVARIABLE
+PFA_PINC:
+ .dw 38
+
+.endif
+.if WANT_PORTD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw 43
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw 42
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw 41
+
+.endif
+.if WANT_ANALOG_COMPARATOR == 1
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Control and Status Register B
+VE_ADCSRB:
+ .dw $ff06
+ .db "ADCSRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRB
+XT_ADCSRB:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRB:
+ .dw 123
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Control And Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw 80
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 1
+VE_DIDR1:
+ .dw $ff05
+ .db "DIDR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR1
+XT_DIDR1:
+ .dw PFA_DOVARIABLE
+PFA_DIDR1:
+ .dw 127
+
+.endif
+.if WANT_PORTE == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port E
+VE_PORTE:
+ .dw $ff05
+ .db "PORTE",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTE
+XT_PORTE:
+ .dw PFA_DOVARIABLE
+PFA_PORTE:
+ .dw 46
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port E
+VE_DDRE:
+ .dw $ff04
+ .db "DDRE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRE
+XT_DDRE:
+ .dw PFA_DOVARIABLE
+PFA_DDRE:
+ .dw 45
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port E
+VE_PINE:
+ .dw $ff04
+ .db "PINE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINE
+XT_PINE:
+ .dw PFA_DOVARIABLE
+PFA_PINE:
+ .dw 44
+
+.endif
+.if WANT_PORTF == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port F
+VE_PORTF:
+ .dw $ff05
+ .db "PORTF",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTF
+XT_PORTF:
+ .dw PFA_DOVARIABLE
+PFA_PORTF:
+ .dw 49
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port F
+VE_DDRF:
+ .dw $ff04
+ .db "DDRF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRF
+XT_DDRF:
+ .dw PFA_DOVARIABLE
+PFA_DDRF:
+ .dw 48
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port F
+VE_PINF:
+ .dw $ff04
+ .db "PINF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINF
+XT_PINF:
+ .dw PFA_DOVARIABLE
+PFA_PINF:
+ .dw 47
+
+.endif
+.if WANT_PORTG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Data Register
+VE_PORTG:
+ .dw $ff05
+ .db "PORTG",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTG
+XT_PORTG:
+ .dw PFA_DOVARIABLE
+PFA_PORTG:
+ .dw 52
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Data Direction Register
+VE_DDRG:
+ .dw $ff04
+ .db "DDRG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRG
+XT_DDRG:
+ .dw PFA_DOVARIABLE
+PFA_DDRG:
+ .dw 51
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Input Pins
+VE_PING:
+ .dw $ff04
+ .db "PING"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PING
+XT_PING:
+ .dw PFA_DOVARIABLE
+PFA_PING:
+ .dw 50
+
+.endif
+.if WANT_JTAG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; On-Chip Debug Related Register in I/O Memory
+VE_OCDR:
+ .dw $ff04
+ .db "OCDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCDR
+XT_OCDR:
+ .dw PFA_DOVARIABLE
+PFA_OCDR:
+ .dw 81
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw 85
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Status Register
+VE_MCUSR:
+ .dw $ff05
+ .db "MCUSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUSR
+XT_MCUSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUSR:
+ .dw 84
+
+.endif
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register A
+VE_EICRA:
+ .dw $ff05
+ .db "EICRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRA
+XT_EICRA:
+ .dw PFA_DOVARIABLE
+PFA_EICRA:
+ .dw 105
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Mask Register
+VE_EIMSK:
+ .dw $ff05
+ .db "EIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIMSK
+XT_EIMSK:
+ .dw PFA_DOVARIABLE
+PFA_EIMSK:
+ .dw 61
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Flag Register
+VE_EIFR:
+ .dw $ff04
+ .db "EIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIFR
+XT_EIFR:
+ .dw PFA_DOVARIABLE
+PFA_EIFR:
+ .dw 60
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 3
+VE_PCMSK3:
+ .dw $ff06
+ .db "PCMSK3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK3
+XT_PCMSK3:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK3:
+ .dw 115
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 2
+VE_PCMSK2:
+ .dw $ff06
+ .db "PCMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK2
+XT_PCMSK2:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK2:
+ .dw 109
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 1
+VE_PCMSK1:
+ .dw $ff06
+ .db "PCMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK1
+XT_PCMSK1:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK1:
+ .dw 108
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 0
+VE_PCMSK0:
+ .dw $ff06
+ .db "PCMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK0
+XT_PCMSK0:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK0:
+ .dw 107
+
+.endif
+.if WANT_USI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USI Data Register
+VE_USIDR:
+ .dw $ff05
+ .db "USIDR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USIDR
+XT_USIDR:
+ .dw PFA_DOVARIABLE
+PFA_USIDR:
+ .dw 186
+; ( -- addr ) System Constant
+; R( -- )
+; USI Status Register
+VE_USISR:
+ .dw $ff05
+ .db "USISR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USISR
+XT_USISR:
+ .dw PFA_DOVARIABLE
+PFA_USISR:
+ .dw 185
+; ( -- addr ) System Constant
+; R( -- )
+; USI Control Register
+VE_USICR:
+ .dw $ff05
+ .db "USICR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USICR
+XT_USICR:
+ .dw PFA_DOVARIABLE
+PFA_USICR:
+ .dw 184
+
+.endif
+.if WANT_AD_CONVERTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC multiplexer Selection Register
+VE_ADMUX:
+ .dw $ff05
+ .db "ADMUX",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADMUX
+XT_ADMUX:
+ .dw PFA_DOVARIABLE
+PFA_ADMUX:
+ .dw 124
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register
+VE_ADCSRA:
+ .dw $ff06
+ .db "ADCSRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRA
+XT_ADCSRA:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRA:
+ .dw 122
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register Bytes
+VE_ADC:
+ .dw $ff03
+ .db "ADC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADC
+XT_ADC:
+ .dw PFA_DOVARIABLE
+PFA_ADC:
+ .dw 120
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 0
+VE_DIDR0:
+ .dw $ff05
+ .db "DIDR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR0
+XT_DIDR0:
+ .dw PFA_DOVARIABLE
+PFA_DIDR0:
+ .dw 126
+
+.endif
+.if WANT_BOOT_LOAD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control Register
+VE_SPMCSR:
+ .dw $ff06
+ .db "SPMCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCSR
+XT_SPMCSR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCSR:
+ .dw 87
+
+.endif
+.if WANT_USART0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR0:
+ .dw $ff04
+ .db "UDR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR0
+XT_UDR0:
+ .dw PFA_DOVARIABLE
+PFA_UDR0:
+ .dw 198
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR0A:
+ .dw $ff06
+ .db "UCSR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0A
+XT_UCSR0A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0A:
+ .dw 192
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR0B:
+ .dw $ff06
+ .db "UCSR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0B
+XT_UCSR0B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0B:
+ .dw 193
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR0C:
+ .dw $ff06
+ .db "UCSR0C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0C
+XT_UCSR0C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0C:
+ .dw 194
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Bytes
+VE_UBRR0:
+ .dw $ff05
+ .db "UBRR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR0
+XT_UBRR0:
+ .dw PFA_DOVARIABLE
+PFA_UBRR0:
+ .dw 196
+
+.endif
+.if WANT_PORTH == 1
+; ( -- addr ) System Constant
+; R( -- )
+; PORT H Data Register
+VE_PORTH:
+ .dw $ff05
+ .db "PORTH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTH
+XT_PORTH:
+ .dw PFA_DOVARIABLE
+PFA_PORTH:
+ .dw 218
+; ( -- addr ) System Constant
+; R( -- )
+; PORT H Data Direction Register
+VE_DDRH:
+ .dw $ff04
+ .db "DDRH"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRH
+XT_DDRH:
+ .dw PFA_DOVARIABLE
+PFA_DDRH:
+ .dw 217
+; ( -- addr ) System Constant
+; R( -- )
+; PORT H Input Pins
+VE_PINH:
+ .dw $ff04
+ .db "PINH"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINH
+XT_PINH:
+ .dw PFA_DOVARIABLE
+PFA_PINH:
+ .dw 216
+
+.endif
+.if WANT_PORTJ == 1
+; ( -- addr ) System Constant
+; R( -- )
+; PORT J Data Register
+VE_PORTJ:
+ .dw $ff05
+ .db "PORTJ",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTJ
+XT_PORTJ:
+ .dw PFA_DOVARIABLE
+PFA_PORTJ:
+ .dw 221
+; ( -- addr ) System Constant
+; R( -- )
+; PORT J Data Direction Register
+VE_DDRJ:
+ .dw $ff04
+ .db "DDRJ"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRJ
+XT_DDRJ:
+ .dw PFA_DOVARIABLE
+PFA_DDRJ:
+ .dw 220
+; ( -- addr ) System Constant
+; R( -- )
+; PORT J Input Pins
+VE_PINJ:
+ .dw $ff04
+ .db "PINJ"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINJ
+XT_PINJ:
+ .dw PFA_DOVARIABLE
+PFA_PINJ:
+ .dw 219
+
+.endif
+.if WANT_CPU == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw 95
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer
+VE_SP:
+ .dw $ff02
+ .db "SP"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SP
+XT_SP:
+ .dw PFA_DOVARIABLE
+PFA_SP:
+ .dw 93
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Calibration Value
+VE_OSCCAL:
+ .dw $ff06
+ .db "OSCCAL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSCCAL
+XT_OSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_OSCCAL:
+ .dw 102
+; ( -- addr ) System Constant
+; R( -- )
+; Clock Prescale Register
+VE_CLKPR:
+ .dw $ff05
+ .db "CLKPR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKPR
+XT_CLKPR:
+ .dw PFA_DOVARIABLE
+PFA_CLKPR:
+ .dw 97
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register
+VE_PRR:
+ .dw $ff03
+ .db "PRR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR
+XT_PRR:
+ .dw PFA_DOVARIABLE
+PFA_PRR:
+ .dw 100
+; ( -- addr ) System Constant
+; R( -- )
+; Sleep Mode Control Register
+VE_SMCR:
+ .dw $ff04
+ .db "SMCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SMCR
+XT_SMCR:
+ .dw PFA_DOVARIABLE
+PFA_SMCR:
+ .dw 83
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 2
+VE_GPIOR2:
+ .dw $ff06
+ .db "GPIOR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR2
+XT_GPIOR2:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR2:
+ .dw 75
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 1
+VE_GPIOR1:
+ .dw $ff06
+ .db "GPIOR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR1
+XT_GPIOR1:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR1:
+ .dw 74
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 0
+VE_GPIOR0:
+ .dw $ff06
+ .db "GPIOR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR0
+XT_GPIOR0:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR0:
+ .dw 62
+
+.endif
diff --git a/amforth-6.5/avr8/devices/atmega3250p/device.py b/amforth-6.5/avr8/devices/atmega3250p/device.py
new file mode 100644
index 0000000..43b6376
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega3250p/device.py
@@ -0,0 +1,336 @@
+# Generated Automatically
+
+# Partname ATmega3250PA
+
+MCUREGS = {
+# Interrupt Vectors
+ 'INT0Addr' : '#2', # External Interrupt Request 0
+ 'PCINT0Addr' : '#4', # Pin Change Interrupt Request 0
+ 'PCINT1Addr' : '#6', # Pin Change Interrupt Request 1
+ 'TIMER2_COMPAddr' : '#8', # Timer/Counter2 Compare Match
+ 'TIMER2_OVFAddr' : '#10', # Timer/Counter2 Overflow
+ 'TIMER1_CAPTAddr' : '#12', # Timer/Counter1 Capture Event
+ 'TIMER1_COMPAAddr' : '#14', # Timer/Counter1 Compare Match A
+ 'TIMER1_COMPBAddr' : '#16', # Timer/Counter Compare Match B
+ 'TIMER1_OVFAddr' : '#18', # Timer/Counter1 Overflow
+ 'TIMER0_COMPAddr' : '#20', # Timer/Counter0 Compare Match
+ 'TIMER0_OVFAddr' : '#22', # Timer/Counter0 Overflow
+ 'SPI_STCAddr' : '#24', # SPI Serial Transfer Complete
+ 'USART_RXAddr' : '#26', # USART, Rx Complete
+ 'USART_UDREAddr' : '#28', # USART Data register Empty
+ 'USART0_TXAddr' : '#30', # USART0, Tx Complete
+ 'USI_STARTAddr' : '#32', # USI Start Condition
+ 'USI_OVERFLOWAddr' : '#34', # USI Overflow
+ 'ANALOG_COMPAddr' : '#36', # Analog Comparator
+ 'ADCAddr' : '#38', # ADC Conversion Complete
+ 'EE_READYAddr' : '#40', # EEPROM Ready
+ 'SPM_READYAddr' : '#42', # Store Program Memory Read
+ 'NOT_USEDAddr' : '#44', # RESERVED
+ 'PCINT2Addr' : '#46', # Pin Change Interrupt Request 2
+ 'PCINT3Addr' : '#48', # Pin Change Interrupt Request 3
+
+# Module TIMER_COUNTER_0
+ 'TCCR0A' : '$44', # Timer/Counter0 Control Registe
+ 'TCCR0A_FOC0A': '$80', # Force Output Compare
+ 'TCCR0A_WGM00': '$40', # Waveform Generation Mode 0
+ 'TCCR0A_COM0A': '$30', # Compare Match Output Modes
+ 'TCCR0A_WGM01': '$8', # Waveform Generation Mode 1
+ 'TCCR0A_CS0': '$7', # Clock Selects
+ 'TCNT0' : '$46', # Timer/Counter0
+ 'OCR0A' : '$47', # Timer/Counter0 Output Compare
+ 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
+ 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
+ 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
+ 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
+ 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
+ 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Control Register
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSR310': '$1', # Prescaler Reset Timer/Counter1
+
+# Module TIMER_COUNTER_1
+ 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
+ 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
+ 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
+ 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
+ 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
+ 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
+ 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
+ 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
+ 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
+ 'TCCR1C' : '$82', # Timer/Counter 1 Control Regist
+ 'TCCR1C_FOC1A': '$80', # Force Output Compare 1A
+ 'TCCR1C_FOC1B': '$40', # Force Output Compare 1B
+ 'TCNT1' : '$84', # Timer/Counter1 Bytes
+ 'OCR1A' : '$88', # Timer/Counter1 Output Compare
+ 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
+ 'ICR1' : '$86', # Timer/Counter1 Input Capture R
+ 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
+ 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
+ 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
+ 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
+ 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
+ 'TIFR1' : '$36', # Timer/Counter1 Interrupt Flag
+ 'TIFR1_ICF1': '$20', # Input Capture Flag 1
+ 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
+ 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
+ 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
+
+# Module TIMER_COUNTER_2
+ 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
+ 'TCCR2A_FOC2A': '$80', # Force Output Compare A
+ 'TCCR2A_WGM20': '$40', # Waveform Generation Mode
+ 'TCCR2A_COM2A': '$30', # Compare Output Mode bits
+ 'TCCR2A_WGM21': '$8', # Waveform Generation Mode
+ 'TCCR2A_CS2': '$7', # Clock Select bits
+ 'TCNT2' : '$b2', # Timer/Counter2
+ 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
+ 'TIMSK2' : '$70', # Timer/Counter2 Interrupt Mask
+ 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
+ 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
+ 'TIFR2' : '$37', # Timer/Counter2 Interrupt Flag
+ 'TIFR2_OCF2A': '$2', # Timer/Counter2 Output Compare
+ 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_PSR2': '$2', # Prescaler Reset Timer/Counter2
+ 'ASSR' : '$b6', # Asynchronous Status Register
+ 'ASSR_EXCLK': '$10', # Enable External Clock Interrup
+ 'ASSR_AS2': '$8', # AS2: Asynchronous Timer/Counte
+ 'ASSR_TCN2UB': '$4', # TCN2UB: Timer/Counter2 Update
+ 'ASSR_OCR2UB': '$2', # Output Compare Register2 Updat
+ 'ASSR_TCR2UB': '$1', # TCR2UB: Timer/Counter Control
+
+# Module WATCHDOG
+ 'WDTCR' : '$60', # Watchdog Timer Control Registe
+ 'WDTCR_WDCE': '$10', # Watchdog Change Enable
+ 'WDTCR_WDE': '$8', # Watch Dog Enable
+ 'WDTCR_WDP': '$7', # Watch Dog Timer Prescaler bits
+
+# Module EEPROM
+ 'EEAR' : '$41', # EEPROM Read/Write Access Byte
+ 'EEDR' : '$40', # EEPROM Data Register
+ 'EECR' : '$3f', # EEPROM Control Register
+ 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
+ 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
+ 'EECR_EEWE': '$2', # EEPROM Write Enable
+ 'EECR_EERE': '$1', # EEPROM Read Enable
+
+# Module SPI
+ 'SPCR' : '$4c', # SPI Control Register
+ 'SPCR_SPIE': '$80', # SPI Interrupt Enable
+ 'SPCR_SPE': '$40', # SPI Enable
+ 'SPCR_DORD': '$20', # Data Order
+ 'SPCR_MSTR': '$10', # Master/Slave Select
+ 'SPCR_CPOL': '$8', # Clock polarity
+ 'SPCR_CPHA': '$4', # Clock Phase
+ 'SPCR_SPR': '$3', # SPI Clock Rate Selects
+ 'SPSR' : '$4d', # SPI Status Register
+ 'SPSR_SPIF': '$80', # SPI Interrupt Flag
+ 'SPSR_WCOL': '$40', # Write Collision Flag
+ 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
+ 'SPDR' : '$4e', # SPI Data Register
+
+# Module PORTA
+ 'PORTA' : '$22', # Port A Data Register
+ 'DDRA' : '$21', # Port A Data Direction Register
+ 'PINA' : '$20', # Port A Input Pins
+
+# Module PORTB
+ 'PORTB' : '$25', # Port B Data Register
+ 'DDRB' : '$24', # Port B Data Direction Register
+ 'PINB' : '$23', # Port B Input Pins
+
+# Module PORTC
+ 'PORTC' : '$28', # Port C Data Register
+ 'DDRC' : '$27', # Port C Data Direction Register
+ 'PINC' : '$26', # Port C Input Pins
+
+# Module PORTD
+ 'PORTD' : '$2b', # Port D Data Register
+ 'DDRD' : '$2a', # Port D Data Direction Register
+ 'PIND' : '$29', # Port D Input Pins
+
+# Module ANALOG_COMPARATOR
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
+ 'ACSR' : '$50', # Analog Comparator Control And
+ 'ACSR_ACD': '$80', # Analog Comparator Disable
+ 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
+ 'ACSR_ACO': '$20', # Analog Compare Output
+ 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
+ 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
+ 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
+ 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
+ 'DIDR1' : '$7f', # Digital Input Disable Register
+ 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
+ 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
+
+# Module PORTE
+ 'PORTE' : '$2e', # Data Register, Port E
+ 'DDRE' : '$2d', # Data Direction Register, Port
+ 'PINE' : '$2c', # Input Pins, Port E
+
+# Module PORTF
+ 'PORTF' : '$31', # Data Register, Port F
+ 'DDRF' : '$30', # Data Direction Register, Port
+ 'PINF' : '$2f', # Input Pins, Port F
+
+# Module PORTG
+ 'PORTG' : '$34', # Port G Data Register
+ 'DDRG' : '$33', # Port G Data Direction Register
+ 'PING' : '$32', # Port G Input Pins
+
+# Module JTAG
+ 'OCDR' : '$51', # On-Chip Debug Related Register
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_JTD': '$80', # JTAG Interface Disable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+
+# Module EXTERNAL_INTERRUPT
+ 'EICRA' : '$69', # External Interrupt Control Reg
+ 'EICRA_ISC01': '$2', # External Interrupt Sense Contr
+ 'EICRA_ISC00': '$1', # External Interrupt Sense Contr
+ 'EIMSK' : '$3d', # External Interrupt Mask Regist
+ 'EIMSK_PCIE': '$f0', # Pin Change Interrupt Enables
+ 'EIMSK_INT0': '$1', # External Interrupt Request 0 E
+ 'EIFR' : '$3c', # External Interrupt Flag Regist
+ 'EIFR_PCIF': '$f0', # Pin Change Interrupt Flags
+ 'EIFR_INTF0': '$1', # External Interrupt Flag 0
+ 'PCMSK3' : '$73', # Pin Change Mask Register 3
+ 'PCMSK2' : '$6d', # Pin Change Mask Register 2
+ 'PCMSK1' : '$6c', # Pin Change Mask Register 1
+ 'PCMSK0' : '$6b', # Pin Change Mask Register 0
+
+# Module USI
+ 'USIDR' : '$ba', # USI Data Register
+ 'USISR' : '$b9', # USI Status Register
+ 'USISR_USISIF': '$80', # Start Condition Interrupt Flag
+ 'USISR_USIOIF': '$40', # Counter Overflow Interrupt Fla
+ 'USISR_USIPF': '$20', # Stop Condition Flag
+ 'USISR_USIDC': '$10', # Data Output Collision
+ 'USISR_USICNT': '$f', # USI Counter Value Bits
+ 'USICR' : '$b8', # USI Control Register
+ 'USICR_USISIE': '$80', # Start Condition Interrupt Enab
+ 'USICR_USIOIE': '$40', # Counter Overflow Interrupt Ena
+ 'USICR_USIWM': '$30', # USI Wire Mode Bits
+ 'USICR_USICS': '$c', # USI Clock Source Select Bits
+ 'USICR_USICLK': '$2', # Clock Strobe
+ 'USICR_USITC': '$1', # Toggle Clock Port Pin
+
+# Module AD_CONVERTER
+ 'ADMUX' : '$7c', # The ADC multiplexer Selection
+ 'ADMUX_REFS': '$c0', # Reference Selection Bits
+ 'ADMUX_ADLAR': '$20', # Left Adjust Result
+ 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
+ 'ADCSRA' : '$7a', # The ADC Control and Status reg
+ 'ADCSRA_ADEN': '$80', # ADC Enable
+ 'ADCSRA_ADSC': '$40', # ADC Start Conversion
+ 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
+ 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
+ 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
+ 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
+ 'ADC' : '$78', # ADC Data Register Bytes
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Sources
+ 'DIDR0' : '$7e', # Digital Input Disable Register
+ 'DIDR0_ADC7D': '$80', # ADC7 Digital input Disable
+ 'DIDR0_ADC6D': '$40', # ADC6 Digital input Disable
+ 'DIDR0_ADC5D': '$20', # ADC5 Digital input Disable
+ 'DIDR0_ADC4D': '$10', # ADC4 Digital input Disable
+ 'DIDR0_ADC3D': '$8', # ADC3 Digital input Disable
+ 'DIDR0_ADC2D': '$4', # ADC2 Digital input Disable
+ 'DIDR0_ADC1D': '$2', # ADC1 Digital input Disable
+ 'DIDR0_ADC0D': '$1', # ADC0 Digital input Disable
+
+# Module BOOT_LOAD
+ 'SPMCSR' : '$57', # Store Program Memory Control R
+ 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
+ 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
+ 'SPMCSR_RWWSRE': '$10', # Read While Write section read
+ 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
+ 'SPMCSR_PGWRT': '$4', # Page Write
+ 'SPMCSR_PGERS': '$2', # Page Erase
+ 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
+
+# Module USART0
+ 'UDR0' : '$c6', # USART I/O Data Register
+ 'UCSR0A' : '$c0', # USART Control and Status Regis
+ 'UCSR0A_RXC0': '$80', # USART Receive Complete
+ 'UCSR0A_TXC0': '$40', # USART Transmit Complete
+ 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
+ 'UCSR0A_FE0': '$10', # Framing Error
+ 'UCSR0A_DOR0': '$8', # Data OverRun
+ 'UCSR0A_UPE0': '$4', # USART Parity Error
+ 'UCSR0A_U2X0': '$2', # Double the USART Transmission
+ 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
+ 'UCSR0B' : '$c1', # USART Control and Status Regis
+ 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
+ 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
+ 'UCSR0B_UDRIE0': '$20', # USART Data Register Empty Inte
+ 'UCSR0B_RXEN0': '$10', # Receiver Enable
+ 'UCSR0B_TXEN0': '$8', # Transmitter Enable
+ 'UCSR0B_UCSZ02': '$4', # Character Size
+ 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
+ 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
+ 'UCSR0C' : '$c2', # USART Control and Status Regis
+ 'UCSR0C_UMSEL0': '$40', # USART Mode Select
+ 'UCSR0C_UPM0': '$30', # Parity Mode Bits
+ 'UCSR0C_USBS0': '$8', # Stop Bit Select
+ 'UCSR0C_UCSZ0': '$6', # Character Size
+ 'UCSR0C_UCPOL0': '$1', # Clock Polarity
+ 'UBRR0' : '$c4', # USART Baud Rate Register Byte
+
+# Module PORTH
+ 'PORTH' : '$da', # PORT H Data Register
+ 'DDRH' : '$d9', # PORT H Data Direction Register
+ 'PINH' : '$d8', # PORT H Input Pins
+
+# Module PORTJ
+ 'PORTJ' : '$dd', # PORT J Data Register
+ 'DDRJ' : '$dc', # PORT J Data Direction Register
+ 'PINJ' : '$db', # PORT J Input Pins
+
+# Module CPU
+ 'SREG' : '$5f', # Status Register
+ 'SREG_I': '$80', # Global Interrupt Enable
+ 'SREG_T': '$40', # Bit Copy Storage
+ 'SREG_H': '$20', # Half Carry Flag
+ 'SREG_S': '$10', # Sign Bit
+ 'SREG_V': '$8', # Two's Complement Overflow Flag
+ 'SREG_N': '$4', # Negative Flag
+ 'SREG_Z': '$2', # Zero Flag
+ 'SREG_C': '$1', # Carry Flag
+ 'SP' : '$5d', # Stack Pointer
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_JTD': '$80', # JTAG Interface Disable
+ 'MCUCR_BODS': '$40', # BOD Sleep
+ 'MCUCR_BODSE': '$20', # BOD Sleep Enable
+ 'MCUCR_PUD': '$10', # Pull-up disable
+ 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
+ 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+ 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
+ 'MCUSR_BORF': '$4', # Brown-out Reset Flag
+ 'MCUSR_EXTRF': '$2', # External Reset Flag
+ 'MCUSR_PORF': '$1', # Power-on reset flag
+ 'OSCCAL' : '$66', # Oscillator Calibration Value
+ 'CLKPR' : '$61', # Clock Prescale Register
+ 'CLKPR_CLKPCE': '$80', # Clock Prescaler Change Enable
+ 'CLKPR_CLKPS': '$f', # Clock Prescaler Select Bits
+ 'PRR' : '$64', # Power Reduction Register
+ 'PRR_PRLCD': '$10', # Power Reduction LCD
+ 'PRR_PRTIM1': '$8', # Power Reduction Timer/Counter1
+ 'PRR_PRSPI': '$4', # Power Reduction Serial Periphe
+ 'PRR_PRUSART0': '$2', # Power Reduction USART
+ 'PRR_PRADC': '$1', # Power Reduction ADC
+ 'SMCR' : '$53', # Sleep Mode Control Register
+ 'SMCR_SM': '$e', # Sleep Mode Select bits
+ 'SMCR_SE': '$1', # Sleep Enable
+ 'GPIOR2' : '$4b', # General Purpose IO Register 2
+ 'GPIOR1' : '$4a', # General Purpose IO Register 1
+ 'GPIOR0' : '$3e', # General Purpose IO Register 0
+
+ '__amforth_dummy':'0'
+}
diff --git a/amforth-6.5/avr8/devices/atmega3250p/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega3250p/words/no-jtag.asm
new file mode 100644
index 0000000..352a4bb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega3250p/words/no-jtag.asm
@@ -0,0 +1,14 @@
+; ( -- )
+; ( -- )
+; MCU
+; disable jtag at runtime
+VE_NOJTAG:
+ .dw $FF05
+ .db "-jtag",0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOJTAG
+XT_NOJTAG:
+ .dw PFA_NOJTAG
+PFA_NOJTAG:
+
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega3250p/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega3250p/words/no-wdt.asm
new file mode 100644
index 0000000..4a12261
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega3250p/words/no-wdt.asm
@@ -0,0 +1,22 @@
+; ( -- )
+; MCU
+; disable watch dog timer at runtime
+VE_NOWDT:
+ .dw $ff04
+ .db "-wdt"
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOWDT
+XT_NOWDT:
+ .dw PFA_NOWDT
+PFA_NOWDT:
+
+; Reset WDT
+ wdr
+; Write logical one to WDTOE and WDE
+ in_ temp1, WDTCR
+ ori temp1, (1<<WDTOE)|(1<<WDE)
+ out WDTCR, temp1
+; Turn off WDT
+ ldi temp1, (0<<WDE)
+ out_ WDTCR, temp1
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega3250p/words/sleep.asm b/amforth-6.5/avr8/devices/atmega3250p/words/sleep.asm
new file mode 100644
index 0000000..256249c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega3250p/words/sleep.asm
@@ -0,0 +1,19 @@
+; ( mode -- )
+; MCU
+; put the controller into the specified sleep mode
+VE_SLEEP:
+ .dw $ff05
+ .db "sleep", 0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_SLEEP
+XT_SLEEP:
+ .dw PFA_SLEEP
+PFA_SLEEP:
+ andi tosl, 7 ; leave only legal mode bits
+ lsl tosl ; move to correct location (bits 3-1)
+ ori tosl, 1 ; set the SE bit
+ out_ SMCR, tosl ; set the sleep config
+ sleep ; nighty-night
+ out_ SMCR, zerol ; 0 protects against accidental sleeps
+ loadtos ; pop argument from stack
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega3250pa/atmega3250pa.frt b/amforth-6.5/avr8/devices/atmega3250pa/atmega3250pa.frt
new file mode 100644
index 0000000..2fcaf06
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega3250pa/atmega3250pa.frt
@@ -0,0 +1,292 @@
+\ Partname: ATmega3250PA
+\ generated automatically
+
+\ TIMER_COUNTER_0
+&68 constant TCCR0A \ Timer/Counter0 Control Register
+ $80 constant TCCR0A_FOC0A \ Force Output Compare
+ $40 constant TCCR0A_WGM00 \ Waveform Generation Mode 0
+ $30 constant TCCR0A_COM0A \ Compare Match Output Modes
+ $08 constant TCCR0A_WGM01 \ Waveform Generation Mode 1
+ $07 constant TCCR0A_CS0 \ Clock Selects
+&70 constant TCNT0 \ Timer/Counter0
+&71 constant OCR0A \ Timer/Counter0 Output Compare Register
+&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
+ $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match Interrupt Enable
+ $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
+&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
+ $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0
+ $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
+&67 constant GTCCR \ General Timer/Control Register
+ $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
+ $01 constant GTCCR_PSR310 \ Prescaler Reset Timer/Counter1 and Timer/Counter0
+\ TIMER_COUNTER_1
+&128 constant TCCR1A \ Timer/Counter1 Control Register A
+ $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
+ $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
+ $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
+&129 constant TCCR1B \ Timer/Counter1 Control Register B
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
+ $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
+&130 constant TCCR1C \ Timer/Counter 1 Control Register C
+ $80 constant TCCR1C_FOC1A \ Force Output Compare 1A
+ $40 constant TCCR1C_FOC1B \ Force Output Compare 1B
+&132 constant TCNT1 \ Timer/Counter1 Bytes
+&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
+&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
+&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
+&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
+ $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
+ $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
+ $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
+ $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
+&54 constant TIFR1 \ Timer/Counter1 Interrupt Flag register
+ $20 constant TIFR1_ICF1 \ Input Capture Flag 1
+ $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
+ $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
+ $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
+\ TIMER_COUNTER_2
+&176 constant TCCR2A \ Timer/Counter2 Control Register
+ $80 constant TCCR2A_FOC2A \ Force Output Compare A
+ $40 constant TCCR2A_WGM20 \ Waveform Generation Mode
+ $30 constant TCCR2A_COM2A \ Compare Output Mode bits
+ $08 constant TCCR2A_WGM21 \ Waveform Generation Mode
+ $07 constant TCCR2A_CS2 \ Clock Select bits
+&178 constant TCNT2 \ Timer/Counter2
+&179 constant OCR2A \ Timer/Counter2 Output Compare Register
+&112 constant TIMSK2 \ Timer/Counter2 Interrupt Mask register
+ $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match Interrupt Enable
+ $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
+&55 constant TIFR2 \ Timer/Counter2 Interrupt Flag Register
+ $02 constant TIFR2_OCF2A \ Timer/Counter2 Output Compare Flag 2
+ $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
+&182 constant ASSR \ Asynchronous Status Register
+ $10 constant ASSR_EXCLK \ Enable External Clock Interrupt
+ $08 constant ASSR_AS2 \ AS2: Asynchronous Timer/Counter2
+ $04 constant ASSR_TCN2UB \ TCN2UB: Timer/Counter2 Update Busy
+ $02 constant ASSR_OCR2UB \ Output Compare Register2 Update Busy
+ $01 constant ASSR_TCR2UB \ TCR2UB: Timer/Counter Control Register2 Update Busy
+\ WATCHDOG
+&96 constant WDTCR \ Watchdog Timer Control Register
+ $10 constant WDTCR_WDCE \ Watchdog Change Enable
+ $08 constant WDTCR_WDE \ Watch Dog Enable
+ $07 constant WDTCR_WDP \ Watch Dog Timer Prescaler bits
+\ EEPROM
+&65 constant EEAR \ EEPROM Read/Write Access Bytes
+&64 constant EEDR \ EEPROM Data Register
+&63 constant EECR \ EEPROM Control Register
+ $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
+ $04 constant EECR_EEMWE \ EEPROM Master Write Enable
+ $02 constant EECR_EEWE \ EEPROM Write Enable
+ $01 constant EECR_EERE \ EEPROM Read Enable
+\ SPI
+&76 constant SPCR \ SPI Control Register
+ $80 constant SPCR_SPIE \ SPI Interrupt Enable
+ $40 constant SPCR_SPE \ SPI Enable
+ $20 constant SPCR_DORD \ Data Order
+ $10 constant SPCR_MSTR \ Master/Slave Select
+ $08 constant SPCR_CPOL \ Clock polarity
+ $04 constant SPCR_CPHA \ Clock Phase
+ $03 constant SPCR_SPR \ SPI Clock Rate Selects
+&77 constant SPSR \ SPI Status Register
+ $80 constant SPSR_SPIF \ SPI Interrupt Flag
+ $40 constant SPSR_WCOL \ Write Collision Flag
+ $01 constant SPSR_SPI2X \ Double SPI Speed Bit
+&78 constant SPDR \ SPI Data Register
+\ PORTA
+&34 constant PORTA \ Port A Data Register
+&33 constant DDRA \ Port A Data Direction Register
+&32 constant PINA \ Port A Input Pins
+\ PORTB
+&37 constant PORTB \ Port B Data Register
+&36 constant DDRB \ Port B Data Direction Register
+&35 constant PINB \ Port B Input Pins
+\ PORTC
+&40 constant PORTC \ Port C Data Register
+&39 constant DDRC \ Port C Data Direction Register
+&38 constant PINC \ Port C Input Pins
+\ PORTD
+&43 constant PORTD \ Port D Data Register
+&42 constant DDRD \ Port D Data Direction Register
+&41 constant PIND \ Port D Input Pins
+\ ANALOG_COMPARATOR
+&123 constant ADCSRB \ ADC Control and Status Register B
+ $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer Enable
+&80 constant ACSR \ Analog Comparator Control And Status Register
+ $80 constant ACSR_ACD \ Analog Comparator Disable
+ $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
+ $20 constant ACSR_ACO \ Analog Compare Output
+ $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
+ $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
+ $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
+ $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
+&127 constant DIDR1 \ Digital Input Disable Register 1
+ $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
+ $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
+\ PORTE
+&46 constant PORTE \ Data Register, Port E
+&45 constant DDRE \ Data Direction Register, Port E
+&44 constant PINE \ Input Pins, Port E
+\ PORTF
+&49 constant PORTF \ Data Register, Port F
+&48 constant DDRF \ Data Direction Register, Port F
+&47 constant PINF \ Input Pins, Port F
+\ PORTG
+&52 constant PORTG \ Port G Data Register
+&51 constant DDRG \ Port G Data Direction Register
+&50 constant PING \ Port G Input Pins
+\ JTAG
+&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
+&85 constant MCUCR \ MCU Control Register
+ $80 constant MCUCR_JTD \ JTAG Interface Disable
+&84 constant MCUSR \ MCU Status Register
+ $10 constant MCUSR_JTRF \ JTAG Reset Flag
+\ EXTERNAL_INTERRUPT
+&105 constant EICRA \ External Interrupt Control Register A
+ $02 constant EICRA_ISC01 \ External Interrupt Sense Control 0 Bit 1
+ $01 constant EICRA_ISC00 \ External Interrupt Sense Control 0 Bit 0
+&61 constant EIMSK \ External Interrupt Mask Register
+ $F0 constant EIMSK_PCIE \ Pin Change Interrupt Enables
+ $01 constant EIMSK_INT0 \ External Interrupt Request 0 Enable
+&60 constant EIFR \ External Interrupt Flag Register
+ $F0 constant EIFR_PCIF \ Pin Change Interrupt Flags
+ $01 constant EIFR_INTF0 \ External Interrupt Flag 0
+&115 constant PCMSK3 \ Pin Change Mask Register 3
+&109 constant PCMSK2 \ Pin Change Mask Register 2
+&108 constant PCMSK1 \ Pin Change Mask Register 1
+&107 constant PCMSK0 \ Pin Change Mask Register 0
+\ USI
+&186 constant USIDR \ USI Data Register
+&185 constant USISR \ USI Status Register
+ $80 constant USISR_USISIF \ Start Condition Interrupt Flag
+ $40 constant USISR_USIOIF \ Counter Overflow Interrupt Flag
+ $20 constant USISR_USIPF \ Stop Condition Flag
+ $10 constant USISR_USIDC \ Data Output Collision
+ $0F constant USISR_USICNT \ USI Counter Value Bits
+&184 constant USICR \ USI Control Register
+ $80 constant USICR_USISIE \ Start Condition Interrupt Enable
+ $40 constant USICR_USIOIE \ Counter Overflow Interrupt Enable
+ $30 constant USICR_USIWM \ USI Wire Mode Bits
+ $0C constant USICR_USICS \ USI Clock Source Select Bits
+ $02 constant USICR_USICLK \ Clock Strobe
+ $01 constant USICR_USITC \ Toggle Clock Port Pin
+\ AD_CONVERTER
+&124 constant ADMUX \ The ADC multiplexer Selection Register
+ $C0 constant ADMUX_REFS \ Reference Selection Bits
+ $20 constant ADMUX_ADLAR \ Left Adjust Result
+ $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
+&122 constant ADCSRA \ The ADC Control and Status register
+ $80 constant ADCSRA_ADEN \ ADC Enable
+ $40 constant ADCSRA_ADSC \ ADC Start Conversion
+ $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
+ $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
+ $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
+ $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
+&120 constant ADC \ ADC Data Register Bytes
+&126 constant DIDR0 \ Digital Input Disable Register 0
+ $80 constant DIDR0_ADC7D \ ADC7 Digital input Disable
+ $40 constant DIDR0_ADC6D \ ADC6 Digital input Disable
+ $20 constant DIDR0_ADC5D \ ADC5 Digital input Disable
+ $10 constant DIDR0_ADC4D \ ADC4 Digital input Disable
+ $08 constant DIDR0_ADC3D \ ADC3 Digital input Disable
+ $04 constant DIDR0_ADC2D \ ADC2 Digital input Disable
+ $02 constant DIDR0_ADC1D \ ADC1 Digital input Disable
+ $01 constant DIDR0_ADC0D \ ADC0 Digital input Disable
+\ BOOT_LOAD
+&87 constant SPMCSR \ Store Program Memory Control Register
+ $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
+ $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
+ $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
+ $04 constant SPMCSR_PGWRT \ Page Write
+ $02 constant SPMCSR_PGERS \ Page Erase
+ $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
+\ USART0
+&198 constant UDR0 \ USART I/O Data Register
+&192 constant UCSR0A \ USART Control and Status Register A
+ $80 constant UCSR0A_RXC0 \ USART Receive Complete
+ $40 constant UCSR0A_TXC0 \ USART Transmit Complete
+ $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
+ $10 constant UCSR0A_FE0 \ Framing Error
+ $08 constant UCSR0A_DOR0 \ Data OverRun
+ $04 constant UCSR0A_UPE0 \ USART Parity Error
+ $02 constant UCSR0A_U2X0 \ Double the USART Transmission Speed
+ $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
+&193 constant UCSR0B \ USART Control and Status Register B
+ $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
+ $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
+ $20 constant UCSR0B_UDRIE0 \ USART Data Register Empty Interrupt Enable
+ $10 constant UCSR0B_RXEN0 \ Receiver Enable
+ $08 constant UCSR0B_TXEN0 \ Transmitter Enable
+ $04 constant UCSR0B_UCSZ02 \ Character Size
+ $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
+ $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
+&194 constant UCSR0C \ USART Control and Status Register C
+ $40 constant UCSR0C_UMSEL0 \ USART Mode Select
+ $30 constant UCSR0C_UPM0 \ Parity Mode Bits
+ $08 constant UCSR0C_USBS0 \ Stop Bit Select
+ $06 constant UCSR0C_UCSZ0 \ Character Size
+ $01 constant UCSR0C_UCPOL0 \ Clock Polarity
+&196 constant UBRR0 \ USART Baud Rate Register Bytes
+\ PORTH
+&218 constant PORTH \ PORT H Data Register
+&217 constant DDRH \ PORT H Data Direction Register
+&216 constant PINH \ PORT H Input Pins
+\ PORTJ
+&221 constant PORTJ \ PORT J Data Register
+&220 constant DDRJ \ PORT J Data Direction Register
+&219 constant PINJ \ PORT J Input Pins
+\ CPU
+&95 constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ $08 constant SREG_V \ Two's Complement Overflow Flag
+ $04 constant SREG_N \ Negative Flag
+ $02 constant SREG_Z \ Zero Flag
+ $01 constant SREG_C \ Carry Flag
+&93 constant SP \ Stack Pointer
+&102 constant OSCCAL \ Oscillator Calibration Value
+&97 constant CLKPR \ Clock Prescale Register
+ $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable
+ $0F constant CLKPR_CLKPS \ Clock Prescaler Select Bits
+&100 constant PRR \ Power Reduction Register
+ $10 constant PRR_PRLCD \ Power Reduction LCD
+ $08 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
+ $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
+ $02 constant PRR_PRUSART0 \ Power Reduction USART
+ $01 constant PRR_PRADC \ Power Reduction ADC
+&83 constant SMCR \ Sleep Mode Control Register
+ $0E constant SMCR_SM \ Sleep Mode Select bits
+ $01 constant SMCR_SE \ Sleep Enable
+&75 constant GPIOR2 \ General Purpose IO Register 2
+&74 constant GPIOR1 \ General Purpose IO Register 1
+&62 constant GPIOR0 \ General Purpose IO Register 0
+
+\ Interrupts
+&2 constant INT0Addr \ External Interrupt Request 0
+&4 constant PCINT0Addr \ Pin Change Interrupt Request 0
+&6 constant PCINT1Addr \ Pin Change Interrupt Request 1
+&8 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
+&10 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
+&12 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+&14 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
+&16 constant TIMER1_COMPBAddr \ Timer/Counter Compare Match B
+&18 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+&20 constant TIMER0_COMPAddr \ Timer/Counter0 Compare Match
+&22 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
+&24 constant SPI__STCAddr \ SPI Serial Transfer Complete
+&26 constant USART__RXAddr \ USART, Rx Complete
+&28 constant USART__UDREAddr \ USART Data register Empty
+&30 constant USART0__TXAddr \ USART0, Tx Complete
+&32 constant USI_STARTAddr \ USI Start Condition
+&34 constant USI_OVERFLOWAddr \ USI Overflow
+&36 constant ANALOG_COMPAddr \ Analog Comparator
+&38 constant ADCAddr \ ADC Conversion Complete
+&40 constant EE_READYAddr \ EEPROM Ready
+&42 constant SPM_READYAddr \ Store Program Memory Read
+&44 constant NOT_USEDAddr \ RESERVED
+&46 constant PCINT2Addr \ Pin Change Interrupt Request 2
+&48 constant PCINT3Addr \ Pin Change Interrupt Request 3
diff --git a/amforth-6.5/avr8/devices/atmega3250pa/device.asm b/amforth-6.5/avr8/devices/atmega3250pa/device.asm
new file mode 100644
index 0000000..043962e
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega3250pa/device.asm
@@ -0,0 +1,114 @@
+; Partname: ATmega3250PA
+; generated automatically, do not edit
+
+.nolist
+ .include "m3250PAdef.inc"
+.list
+
+.equ ramstart = 256
+.equ CELLSIZE = 2
+.macro readflashcell
+ lsl zl
+ rol zh
+ lpm @0, Z+
+ lpm @1, Z+
+.endmacro
+.macro writeflashcell
+ lsl zl
+ rol zh
+.endmacro
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_TIMER_COUNTER_2 = 0
+.set WANT_WATCHDOG = 0
+.set WANT_EEPROM = 0
+.set WANT_SPI = 0
+.set WANT_PORTA = 0
+.set WANT_PORTB = 0
+.set WANT_PORTC = 0
+.set WANT_PORTD = 0
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_PORTE = 0
+.set WANT_PORTF = 0
+.set WANT_PORTG = 0
+.set WANT_JTAG = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_USI = 0
+.set WANT_AD_CONVERTER = 0
+.set WANT_BOOT_LOAD = 0
+.set WANT_USART0 = 0
+.set WANT_PORTH = 0
+.set WANT_PORTJ = 0
+.set WANT_CPU = 0
+.equ intvecsize = 2 ; please verify; flash size: 32768 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.org 2
+ rcall isr ; External Interrupt Request 0
+.org 4
+ rcall isr ; Pin Change Interrupt Request 0
+.org 6
+ rcall isr ; Pin Change Interrupt Request 1
+.org 8
+ rcall isr ; Timer/Counter2 Compare Match
+.org 10
+ rcall isr ; Timer/Counter2 Overflow
+.org 12
+ rcall isr ; Timer/Counter1 Capture Event
+.org 14
+ rcall isr ; Timer/Counter1 Compare Match A
+.org 16
+ rcall isr ; Timer/Counter Compare Match B
+.org 18
+ rcall isr ; Timer/Counter1 Overflow
+.org 20
+ rcall isr ; Timer/Counter0 Compare Match
+.org 22
+ rcall isr ; Timer/Counter0 Overflow
+.org 24
+ rcall isr ; SPI Serial Transfer Complete
+.org 26
+ rcall isr ; USART, Rx Complete
+.org 28
+ rcall isr ; USART Data register Empty
+.org 30
+ rcall isr ; USART0, Tx Complete
+.org 32
+ rcall isr ; USI Start Condition
+.org 34
+ rcall isr ; USI Overflow
+.org 36
+ rcall isr ; Analog Comparator
+.org 38
+ rcall isr ; ADC Conversion Complete
+.org 40
+ rcall isr ; EEPROM Ready
+.org 42
+ rcall isr ; Store Program Memory Read
+.org 44
+ rcall isr ; RESERVED
+.org 46
+ rcall isr ; Pin Change Interrupt Request 2
+.org 48
+ rcall isr ; Pin Change Interrupt Request 3
+.equ INTVECTORS = 25
+.nooverlap
+
+; compatability layer (maybe empty)
+.equ EEPE = EEWE
+.equ EEMPE = EEMWE
+
+; controller data area, environment query mcu-info
+mcu_info:
+mcu_ramsize:
+ .dw 2048
+mcu_eepromsize:
+ .dw 1024
+mcu_maxdp:
+ .dw 28672
+mcu_numints:
+ .dw 25
+mcu_name:
+ .dw 12
+ .db "ATmega3250PA"
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega3250pa/device.inc b/amforth-6.5/avr8/devices/atmega3250pa/device.inc
new file mode 100644
index 0000000..b8cd934
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega3250pa/device.inc
@@ -0,0 +1,1152 @@
+; Partname: ATmega3250PA
+; generated automatically, no not edit
+
+.if WANT_TIMER_COUNTER_0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Control Register
+VE_TCCR0A:
+ .dw $ff06
+ .db "TCCR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0A
+XT_TCCR0A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0A:
+ .dw 68
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw 70
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0A:
+ .dw $ff05
+ .db "OCR0A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0A
+XT_OCR0A:
+ .dw PFA_DOVARIABLE
+PFA_OCR0A:
+ .dw 71
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Mask Register
+VE_TIMSK0:
+ .dw $ff06
+ .db "TIMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK0
+XT_TIMSK0:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK0:
+ .dw 110
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Flag register
+VE_TIFR0:
+ .dw $ff05
+ .db "TIFR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR0
+XT_TIFR0:
+ .dw PFA_DOVARIABLE
+PFA_TIFR0:
+ .dw 53
+; ( -- addr ) System Constant
+; R( -- )
+; General Timer/Control Register
+VE_GTCCR:
+ .dw $ff05
+ .db "GTCCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GTCCR
+XT_GTCCR:
+ .dw PFA_DOVARIABLE
+PFA_GTCCR:
+ .dw 67
+
+.endif
+.if WANT_TIMER_COUNTER_1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw 128
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw 129
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter 1 Control Register C
+VE_TCCR1C:
+ .dw $ff06
+ .db "TCCR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1C
+XT_TCCR1C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1C:
+ .dw 130
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Bytes
+VE_TCNT1:
+ .dw $ff05
+ .db "TCNT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1
+XT_TCNT1:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1:
+ .dw 132
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register A Bytes
+VE_OCR1A:
+ .dw $ff05
+ .db "OCR1A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1A
+XT_OCR1A:
+ .dw PFA_DOVARIABLE
+PFA_OCR1A:
+ .dw 136
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register B Bytes
+VE_OCR1B:
+ .dw $ff05
+ .db "OCR1B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1B
+XT_OCR1B:
+ .dw PFA_DOVARIABLE
+PFA_OCR1B:
+ .dw 138
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Bytes
+VE_ICR1:
+ .dw $ff04
+ .db "ICR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1
+XT_ICR1:
+ .dw PFA_DOVARIABLE
+PFA_ICR1:
+ .dw 134
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Mask Register
+VE_TIMSK1:
+ .dw $ff06
+ .db "TIMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK1
+XT_TIMSK1:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK1:
+ .dw 111
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Flag register
+VE_TIFR1:
+ .dw $ff05
+ .db "TIFR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR1
+XT_TIFR1:
+ .dw PFA_DOVARIABLE
+PFA_TIFR1:
+ .dw 54
+
+.endif
+.if WANT_TIMER_COUNTER_2 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register
+VE_TCCR2A:
+ .dw $ff06
+ .db "TCCR2A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2A
+XT_TCCR2A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2A:
+ .dw 176
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2
+VE_TCNT2:
+ .dw $ff05
+ .db "TCNT2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT2
+XT_TCNT2:
+ .dw PFA_DOVARIABLE
+PFA_TCNT2:
+ .dw 178
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register
+VE_OCR2A:
+ .dw $ff05
+ .db "OCR2A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2A
+XT_OCR2A:
+ .dw PFA_DOVARIABLE
+PFA_OCR2A:
+ .dw 179
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Interrupt Mask register
+VE_TIMSK2:
+ .dw $ff06
+ .db "TIMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK2
+XT_TIMSK2:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK2:
+ .dw 112
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Interrupt Flag Register
+VE_TIFR2:
+ .dw $ff05
+ .db "TIFR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR2
+XT_TIFR2:
+ .dw PFA_DOVARIABLE
+PFA_TIFR2:
+ .dw 55
+; ( -- addr ) System Constant
+; R( -- )
+; Asynchronous Status Register
+VE_ASSR:
+ .dw $ff04
+ .db "ASSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ASSR
+XT_ASSR:
+ .dw PFA_DOVARIABLE
+PFA_ASSR:
+ .dw 182
+
+.endif
+.if WANT_WATCHDOG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCR:
+ .dw $ff05
+ .db "WDTCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCR
+XT_WDTCR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCR:
+ .dw 96
+
+.endif
+.if WANT_EEPROM == 1
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Read/Write Access Bytes
+VE_EEAR:
+ .dw $ff04
+ .db "EEAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEAR
+XT_EEAR:
+ .dw PFA_DOVARIABLE
+PFA_EEAR:
+ .dw 65
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw 64
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw 63
+
+.endif
+.if WANT_SPI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR:
+ .dw $ff04
+ .db "SPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR
+XT_SPCR:
+ .dw PFA_DOVARIABLE
+PFA_SPCR:
+ .dw 76
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR:
+ .dw $ff04
+ .db "SPSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR
+XT_SPSR:
+ .dw PFA_DOVARIABLE
+PFA_SPSR:
+ .dw 77
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR:
+ .dw $ff04
+ .db "SPDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR
+XT_SPDR:
+ .dw PFA_DOVARIABLE
+PFA_SPDR:
+ .dw 78
+
+.endif
+.if WANT_PORTA == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Register
+VE_PORTA:
+ .dw $ff05
+ .db "PORTA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTA
+XT_PORTA:
+ .dw PFA_DOVARIABLE
+PFA_PORTA:
+ .dw 34
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Direction Register
+VE_DDRA:
+ .dw $ff04
+ .db "DDRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRA
+XT_DDRA:
+ .dw PFA_DOVARIABLE
+PFA_DDRA:
+ .dw 33
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Input Pins
+VE_PINA:
+ .dw $ff04
+ .db "PINA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINA
+XT_PINA:
+ .dw PFA_DOVARIABLE
+PFA_PINA:
+ .dw 32
+
+.endif
+.if WANT_PORTB == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw 37
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw 36
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw 35
+
+.endif
+.if WANT_PORTC == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Register
+VE_PORTC:
+ .dw $ff05
+ .db "PORTC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTC
+XT_PORTC:
+ .dw PFA_DOVARIABLE
+PFA_PORTC:
+ .dw 40
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Direction Register
+VE_DDRC:
+ .dw $ff04
+ .db "DDRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRC
+XT_DDRC:
+ .dw PFA_DOVARIABLE
+PFA_DDRC:
+ .dw 39
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Input Pins
+VE_PINC:
+ .dw $ff04
+ .db "PINC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINC
+XT_PINC:
+ .dw PFA_DOVARIABLE
+PFA_PINC:
+ .dw 38
+
+.endif
+.if WANT_PORTD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw 43
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw 42
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw 41
+
+.endif
+.if WANT_ANALOG_COMPARATOR == 1
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Control and Status Register B
+VE_ADCSRB:
+ .dw $ff06
+ .db "ADCSRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRB
+XT_ADCSRB:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRB:
+ .dw 123
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Control And Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw 80
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 1
+VE_DIDR1:
+ .dw $ff05
+ .db "DIDR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR1
+XT_DIDR1:
+ .dw PFA_DOVARIABLE
+PFA_DIDR1:
+ .dw 127
+
+.endif
+.if WANT_PORTE == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port E
+VE_PORTE:
+ .dw $ff05
+ .db "PORTE",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTE
+XT_PORTE:
+ .dw PFA_DOVARIABLE
+PFA_PORTE:
+ .dw 46
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port E
+VE_DDRE:
+ .dw $ff04
+ .db "DDRE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRE
+XT_DDRE:
+ .dw PFA_DOVARIABLE
+PFA_DDRE:
+ .dw 45
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port E
+VE_PINE:
+ .dw $ff04
+ .db "PINE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINE
+XT_PINE:
+ .dw PFA_DOVARIABLE
+PFA_PINE:
+ .dw 44
+
+.endif
+.if WANT_PORTF == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port F
+VE_PORTF:
+ .dw $ff05
+ .db "PORTF",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTF
+XT_PORTF:
+ .dw PFA_DOVARIABLE
+PFA_PORTF:
+ .dw 49
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port F
+VE_DDRF:
+ .dw $ff04
+ .db "DDRF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRF
+XT_DDRF:
+ .dw PFA_DOVARIABLE
+PFA_DDRF:
+ .dw 48
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port F
+VE_PINF:
+ .dw $ff04
+ .db "PINF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINF
+XT_PINF:
+ .dw PFA_DOVARIABLE
+PFA_PINF:
+ .dw 47
+
+.endif
+.if WANT_PORTG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Data Register
+VE_PORTG:
+ .dw $ff05
+ .db "PORTG",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTG
+XT_PORTG:
+ .dw PFA_DOVARIABLE
+PFA_PORTG:
+ .dw 52
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Data Direction Register
+VE_DDRG:
+ .dw $ff04
+ .db "DDRG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRG
+XT_DDRG:
+ .dw PFA_DOVARIABLE
+PFA_DDRG:
+ .dw 51
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Input Pins
+VE_PING:
+ .dw $ff04
+ .db "PING"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PING
+XT_PING:
+ .dw PFA_DOVARIABLE
+PFA_PING:
+ .dw 50
+
+.endif
+.if WANT_JTAG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; On-Chip Debug Related Register in I/O Memory
+VE_OCDR:
+ .dw $ff04
+ .db "OCDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCDR
+XT_OCDR:
+ .dw PFA_DOVARIABLE
+PFA_OCDR:
+ .dw 81
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw 85
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Status Register
+VE_MCUSR:
+ .dw $ff05
+ .db "MCUSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUSR
+XT_MCUSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUSR:
+ .dw 84
+
+.endif
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register A
+VE_EICRA:
+ .dw $ff05
+ .db "EICRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRA
+XT_EICRA:
+ .dw PFA_DOVARIABLE
+PFA_EICRA:
+ .dw 105
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Mask Register
+VE_EIMSK:
+ .dw $ff05
+ .db "EIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIMSK
+XT_EIMSK:
+ .dw PFA_DOVARIABLE
+PFA_EIMSK:
+ .dw 61
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Flag Register
+VE_EIFR:
+ .dw $ff04
+ .db "EIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIFR
+XT_EIFR:
+ .dw PFA_DOVARIABLE
+PFA_EIFR:
+ .dw 60
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 3
+VE_PCMSK3:
+ .dw $ff06
+ .db "PCMSK3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK3
+XT_PCMSK3:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK3:
+ .dw 115
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 2
+VE_PCMSK2:
+ .dw $ff06
+ .db "PCMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK2
+XT_PCMSK2:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK2:
+ .dw 109
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 1
+VE_PCMSK1:
+ .dw $ff06
+ .db "PCMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK1
+XT_PCMSK1:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK1:
+ .dw 108
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 0
+VE_PCMSK0:
+ .dw $ff06
+ .db "PCMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK0
+XT_PCMSK0:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK0:
+ .dw 107
+
+.endif
+.if WANT_USI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USI Data Register
+VE_USIDR:
+ .dw $ff05
+ .db "USIDR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USIDR
+XT_USIDR:
+ .dw PFA_DOVARIABLE
+PFA_USIDR:
+ .dw 186
+; ( -- addr ) System Constant
+; R( -- )
+; USI Status Register
+VE_USISR:
+ .dw $ff05
+ .db "USISR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USISR
+XT_USISR:
+ .dw PFA_DOVARIABLE
+PFA_USISR:
+ .dw 185
+; ( -- addr ) System Constant
+; R( -- )
+; USI Control Register
+VE_USICR:
+ .dw $ff05
+ .db "USICR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USICR
+XT_USICR:
+ .dw PFA_DOVARIABLE
+PFA_USICR:
+ .dw 184
+
+.endif
+.if WANT_AD_CONVERTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC multiplexer Selection Register
+VE_ADMUX:
+ .dw $ff05
+ .db "ADMUX",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADMUX
+XT_ADMUX:
+ .dw PFA_DOVARIABLE
+PFA_ADMUX:
+ .dw 124
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register
+VE_ADCSRA:
+ .dw $ff06
+ .db "ADCSRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRA
+XT_ADCSRA:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRA:
+ .dw 122
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register Bytes
+VE_ADC:
+ .dw $ff03
+ .db "ADC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADC
+XT_ADC:
+ .dw PFA_DOVARIABLE
+PFA_ADC:
+ .dw 120
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 0
+VE_DIDR0:
+ .dw $ff05
+ .db "DIDR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR0
+XT_DIDR0:
+ .dw PFA_DOVARIABLE
+PFA_DIDR0:
+ .dw 126
+
+.endif
+.if WANT_BOOT_LOAD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control Register
+VE_SPMCSR:
+ .dw $ff06
+ .db "SPMCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCSR
+XT_SPMCSR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCSR:
+ .dw 87
+
+.endif
+.if WANT_USART0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR0:
+ .dw $ff04
+ .db "UDR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR0
+XT_UDR0:
+ .dw PFA_DOVARIABLE
+PFA_UDR0:
+ .dw 198
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR0A:
+ .dw $ff06
+ .db "UCSR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0A
+XT_UCSR0A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0A:
+ .dw 192
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR0B:
+ .dw $ff06
+ .db "UCSR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0B
+XT_UCSR0B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0B:
+ .dw 193
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR0C:
+ .dw $ff06
+ .db "UCSR0C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0C
+XT_UCSR0C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0C:
+ .dw 194
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Bytes
+VE_UBRR0:
+ .dw $ff05
+ .db "UBRR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR0
+XT_UBRR0:
+ .dw PFA_DOVARIABLE
+PFA_UBRR0:
+ .dw 196
+
+.endif
+.if WANT_PORTH == 1
+; ( -- addr ) System Constant
+; R( -- )
+; PORT H Data Register
+VE_PORTH:
+ .dw $ff05
+ .db "PORTH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTH
+XT_PORTH:
+ .dw PFA_DOVARIABLE
+PFA_PORTH:
+ .dw 218
+; ( -- addr ) System Constant
+; R( -- )
+; PORT H Data Direction Register
+VE_DDRH:
+ .dw $ff04
+ .db "DDRH"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRH
+XT_DDRH:
+ .dw PFA_DOVARIABLE
+PFA_DDRH:
+ .dw 217
+; ( -- addr ) System Constant
+; R( -- )
+; PORT H Input Pins
+VE_PINH:
+ .dw $ff04
+ .db "PINH"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINH
+XT_PINH:
+ .dw PFA_DOVARIABLE
+PFA_PINH:
+ .dw 216
+
+.endif
+.if WANT_PORTJ == 1
+; ( -- addr ) System Constant
+; R( -- )
+; PORT J Data Register
+VE_PORTJ:
+ .dw $ff05
+ .db "PORTJ",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTJ
+XT_PORTJ:
+ .dw PFA_DOVARIABLE
+PFA_PORTJ:
+ .dw 221
+; ( -- addr ) System Constant
+; R( -- )
+; PORT J Data Direction Register
+VE_DDRJ:
+ .dw $ff04
+ .db "DDRJ"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRJ
+XT_DDRJ:
+ .dw PFA_DOVARIABLE
+PFA_DDRJ:
+ .dw 220
+; ( -- addr ) System Constant
+; R( -- )
+; PORT J Input Pins
+VE_PINJ:
+ .dw $ff04
+ .db "PINJ"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINJ
+XT_PINJ:
+ .dw PFA_DOVARIABLE
+PFA_PINJ:
+ .dw 219
+
+.endif
+.if WANT_CPU == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw 95
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer
+VE_SP:
+ .dw $ff02
+ .db "SP"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SP
+XT_SP:
+ .dw PFA_DOVARIABLE
+PFA_SP:
+ .dw 93
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Calibration Value
+VE_OSCCAL:
+ .dw $ff06
+ .db "OSCCAL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSCCAL
+XT_OSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_OSCCAL:
+ .dw 102
+; ( -- addr ) System Constant
+; R( -- )
+; Clock Prescale Register
+VE_CLKPR:
+ .dw $ff05
+ .db "CLKPR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKPR
+XT_CLKPR:
+ .dw PFA_DOVARIABLE
+PFA_CLKPR:
+ .dw 97
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register
+VE_PRR:
+ .dw $ff03
+ .db "PRR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR
+XT_PRR:
+ .dw PFA_DOVARIABLE
+PFA_PRR:
+ .dw 100
+; ( -- addr ) System Constant
+; R( -- )
+; Sleep Mode Control Register
+VE_SMCR:
+ .dw $ff04
+ .db "SMCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SMCR
+XT_SMCR:
+ .dw PFA_DOVARIABLE
+PFA_SMCR:
+ .dw 83
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 2
+VE_GPIOR2:
+ .dw $ff06
+ .db "GPIOR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR2
+XT_GPIOR2:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR2:
+ .dw 75
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 1
+VE_GPIOR1:
+ .dw $ff06
+ .db "GPIOR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR1
+XT_GPIOR1:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR1:
+ .dw 74
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 0
+VE_GPIOR0:
+ .dw $ff06
+ .db "GPIOR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR0
+XT_GPIOR0:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR0:
+ .dw 62
+
+.endif
diff --git a/amforth-6.5/avr8/devices/atmega3250pa/device.py b/amforth-6.5/avr8/devices/atmega3250pa/device.py
new file mode 100644
index 0000000..43db5ea
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega3250pa/device.py
@@ -0,0 +1,321 @@
+# Generated Automatically
+
+# Partname ATmega325PA
+
+MCUREGS = {
+# Interrupt Vectors
+ 'INT0Addr' : '#2', # External Interrupt Request 0
+ 'PCINT0Addr' : '#4', # Pin Change Interrupt Request 0
+ 'PCINT1Addr' : '#6', # Pin Change Interrupt Request 1
+ 'TIMER2_COMPAddr' : '#8', # Timer/Counter2 Compare Match
+ 'TIMER2_OVFAddr' : '#10', # Timer/Counter2 Overflow
+ 'TIMER1_CAPTAddr' : '#12', # Timer/Counter1 Capture Event
+ 'TIMER1_COMPAAddr' : '#14', # Timer/Counter1 Compare Match A
+ 'TIMER1_COMPBAddr' : '#16', # Timer/Counter Compare Match B
+ 'TIMER1_OVFAddr' : '#18', # Timer/Counter1 Overflow
+ 'TIMER0_COMPAddr' : '#20', # Timer/Counter0 Compare Match
+ 'TIMER0_OVFAddr' : '#22', # Timer/Counter0 Overflow
+ 'SPI_STCAddr' : '#24', # SPI Serial Transfer Complete
+ 'USART0_RXAddr' : '#26', # USART0, Rx Complete
+ 'USART0_UDREAddr' : '#28', # USART0 Data register Empty
+ 'USART0_TXAddr' : '#30', # USART0, Tx Complete
+ 'USI_STARTAddr' : '#32', # USI Start Condition
+ 'USI_OVERFLOWAddr' : '#34', # USI Overflow
+ 'ANALOG_COMPAddr' : '#36', # Analog Comparator
+ 'ADCAddr' : '#38', # ADC Conversion Complete
+ 'EE_READYAddr' : '#40', # EEPROM Ready
+ 'SPM_READYAddr' : '#42', # Store Program Memory Read
+
+# Module AD_CONVERTER
+ 'ADMUX' : '$7c', # The ADC multiplexer Selection
+ 'ADMUX_REFS': '$c0', # Reference Selection Bits
+ 'ADMUX_ADLAR': '$20', # Left Adjust Result
+ 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
+ 'ADCSRA' : '$7a', # The ADC Control and Status reg
+ 'ADCSRA_ADEN': '$80', # ADC Enable
+ 'ADCSRA_ADSC': '$40', # ADC Start Conversion
+ 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
+ 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
+ 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
+ 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
+ 'ADC' : '$78', # ADC Data Register Bytes
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Sources
+ 'DIDR0' : '$7e', # Digital Input Disable Register
+ 'DIDR0_ADC7D': '$80', # ADC7 Digital input Disable
+ 'DIDR0_ADC6D': '$40', # ADC6 Digital input Disable
+ 'DIDR0_ADC5D': '$20', # ADC5 Digital input Disable
+ 'DIDR0_ADC4D': '$10', # ADC4 Digital input Disable
+ 'DIDR0_ADC3D': '$8', # ADC3 Digital input Disable
+ 'DIDR0_ADC2D': '$4', # ADC2 Digital input Disable
+ 'DIDR0_ADC1D': '$2', # ADC1 Digital input Disable
+ 'DIDR0_ADC0D': '$1', # ADC0 Digital input Disable
+
+# Module ANALOG_COMPARATOR
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
+ 'ACSR' : '$50', # Analog Comparator Control And
+ 'ACSR_ACD': '$80', # Analog Comparator Disable
+ 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
+ 'ACSR_ACO': '$20', # Analog Compare Output
+ 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
+ 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
+ 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
+ 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
+ 'DIDR1' : '$7f', # Digital Input Disable Register
+ 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
+ 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
+
+# Module USART0
+ 'UDR0' : '$c6', # USART I/O Data Register
+ 'UCSR0A' : '$c0', # USART Control and Status Regis
+ 'UCSR0A_RXC0': '$80', # USART Receive Complete
+ 'UCSR0A_TXC0': '$40', # USART Transmit Complete
+ 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
+ 'UCSR0A_FE0': '$10', # Framing Error
+ 'UCSR0A_DOR0': '$8', # Data OverRun
+ 'UCSR0A_UPE0': '$4', # USART Parity Error
+ 'UCSR0A_U2X0': '$2', # Double the USART Transmission
+ 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
+ 'UCSR0B' : '$c1', # USART Control and Status Regis
+ 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
+ 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
+ 'UCSR0B_UDRIE0': '$20', # USART Data Register Empty Inte
+ 'UCSR0B_RXEN0': '$10', # Receiver Enable
+ 'UCSR0B_TXEN0': '$8', # Transmitter Enable
+ 'UCSR0B_UCSZ02': '$4', # Character Size
+ 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
+ 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
+ 'UCSR0C' : '$c2', # USART Control and Status Regis
+ 'UCSR0C_UMSEL0': '$40', # USART Mode Select
+ 'UCSR0C_UPM0': '$30', # Parity Mode Bits
+ 'UCSR0C_USBS0': '$8', # Stop Bit Select
+ 'UCSR0C_UCSZ0': '$6', # Character Size
+ 'UCSR0C_UCPOL0': '$1', # Clock Polarity
+ 'UBRR0' : '$c4', # USART Baud Rate Register Byte
+
+# Module USI
+ 'USIDR' : '$ba', # USI Data Register
+ 'USISR' : '$b9', # USI Status Register
+ 'USISR_USISIF': '$80', # Start Condition Interrupt Flag
+ 'USISR_USIOIF': '$40', # Counter Overflow Interrupt Fla
+ 'USISR_USIPF': '$20', # Stop Condition Flag
+ 'USISR_USIDC': '$10', # Data Output Collision
+ 'USISR_USICNT': '$f', # USI Counter Value Bits
+ 'USICR' : '$b8', # USI Control Register
+ 'USICR_USISIE': '$80', # Start Condition Interrupt Enab
+ 'USICR_USIOIE': '$40', # Counter Overflow Interrupt Ena
+ 'USICR_USIWM': '$30', # USI Wire Mode Bits
+ 'USICR_USICS': '$c', # USI Clock Source Select Bits
+ 'USICR_USICLK': '$2', # Clock Strobe
+ 'USICR_USITC': '$1', # Toggle Clock Port Pin
+
+# Module SPI
+ 'SPCR' : '$4c', # SPI Control Register
+ 'SPCR_SPIE': '$80', # SPI Interrupt Enable
+ 'SPCR_SPE': '$40', # SPI Enable
+ 'SPCR_DORD': '$20', # Data Order
+ 'SPCR_MSTR': '$10', # Master/Slave Select
+ 'SPCR_CPOL': '$8', # Clock polarity
+ 'SPCR_CPHA': '$4', # Clock Phase
+ 'SPCR_SPR': '$3', # SPI Clock Rate Selects
+ 'SPSR' : '$4d', # SPI Status Register
+ 'SPSR_SPIF': '$80', # SPI Interrupt Flag
+ 'SPSR_WCOL': '$40', # Write Collision Flag
+ 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
+ 'SPDR' : '$4e', # SPI Data Register
+
+# Module BOOT_LOAD
+ 'SPMCSR' : '$57', # Store Program Memory Control R
+ 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
+ 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
+ 'SPMCSR_RWWSRE': '$10', # Read While Write section read
+ 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
+ 'SPMCSR_PGWRT': '$4', # Page Write
+ 'SPMCSR_PGERS': '$2', # Page Erase
+ 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
+
+# Module JTAG
+ 'OCDR' : '$51', # On-Chip Debug Related Register
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_JTD': '$80', # JTAG Interface Disable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+
+# Module EXTERNAL_INTERRUPT
+ 'EICRA' : '$69', # External Interrupt Control Reg
+ 'EICRA_ISC01': '$2', # External Interrupt Sense Contr
+ 'EICRA_ISC00': '$1', # External Interrupt Sense Contr
+ 'EIMSK' : '$3d', # External Interrupt Mask Regist
+ 'EIMSK_PCIE': '$f0', # Pin Change Interrupt Enables
+ 'EIMSK_INT0': '$1', # External Interrupt Request 0 E
+ 'EIFR' : '$3c', # External Interrupt Flag Regist
+ 'EIFR_PCIF': '$f0', # Pin Change Interrupt Flags
+ 'EIFR_INTF0': '$1', # External Interrupt Flag 0
+ 'PCMSK1' : '$6c', # Pin Change Mask Register 1
+ 'PCMSK0' : '$6b', # Pin Change Mask Register 0
+
+# Module EEPROM
+ 'EEAR' : '$41', # EEPROM Read/Write Access Byte
+ 'EEDR' : '$40', # EEPROM Data Register
+ 'EECR' : '$3f', # EEPROM Control Register
+ 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
+ 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
+ 'EECR_EEWE': '$2', # EEPROM Write Enable
+ 'EECR_EERE': '$1', # EEPROM Read Enable
+
+# Module PORTA
+ 'PORTA' : '$22', # Port A Data Register
+ 'DDRA' : '$21', # Port A Data Direction Register
+ 'PINA' : '$20', # Port A Input Pins
+
+# Module PORTB
+ 'PORTB' : '$25', # Port B Data Register
+ 'DDRB' : '$24', # Port B Data Direction Register
+ 'PINB' : '$23', # Port B Input Pins
+
+# Module PORTC
+ 'PORTC' : '$28', # Port C Data Register
+ 'DDRC' : '$27', # Port C Data Direction Register
+ 'PINC' : '$26', # Port C Input Pins
+
+# Module PORTD
+ 'PORTD' : '$2b', # Port D Data Register
+ 'DDRD' : '$2a', # Port D Data Direction Register
+ 'PIND' : '$29', # Port D Input Pins
+
+# Module PORTE
+ 'PORTE' : '$2e', # Data Register, Port E
+ 'DDRE' : '$2d', # Data Direction Register, Port
+ 'PINE' : '$2c', # Input Pins, Port E
+
+# Module PORTF
+ 'PORTF' : '$31', # Data Register, Port F
+ 'DDRF' : '$30', # Data Direction Register, Port
+ 'PINF' : '$2f', # Input Pins, Port F
+
+# Module PORTG
+ 'PORTG' : '$34', # Port G Data Register
+ 'DDRG' : '$33', # Port G Data Direction Register
+ 'PING' : '$32', # Port G Input Pins
+
+# Module TIMER_COUNTER_0
+ 'TCCR0A' : '$44', # Timer/Counter0 Control Registe
+ 'TCCR0A_FOC0A': '$80', # Force Output Compare
+ 'TCCR0A_WGM00': '$40', # Waveform Generation Mode 0
+ 'TCCR0A_COM0A': '$30', # Compare Match Output Modes
+ 'TCCR0A_WGM01': '$8', # Waveform Generation Mode 1
+ 'TCCR0A_CS0': '$7', # Clock Selects
+ 'TCNT0' : '$46', # Timer/Counter0
+ 'OCR0A' : '$47', # Timer/Counter0 Output Compare
+ 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
+ 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
+ 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
+ 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
+ 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
+ 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Control Register
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSR310': '$1', # Prescaler Reset Timer/Counter1
+
+# Module TIMER_COUNTER_1
+ 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
+ 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
+ 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
+ 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
+ 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
+ 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
+ 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
+ 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
+ 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
+ 'TCCR1C' : '$82', # Timer/Counter 1 Control Regist
+ 'TCCR1C_FOC1A': '$80', # Force Output Compare 1A
+ 'TCCR1C_FOC1B': '$40', # Force Output Compare 1B
+ 'TCNT1' : '$84', # Timer/Counter1 Bytes
+ 'OCR1A' : '$88', # Timer/Counter1 Output Compare
+ 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
+ 'ICR1' : '$86', # Timer/Counter1 Input Capture R
+ 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
+ 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
+ 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
+ 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
+ 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
+ 'TIFR1' : '$36', # Timer/Counter1 Interrupt Flag
+ 'TIFR1_ICF1': '$20', # Input Capture Flag 1
+ 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
+ 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
+ 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
+
+# Module TIMER_COUNTER_2
+ 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
+ 'TCCR2A_FOC2A': '$80', # Force Output Compare A
+ 'TCCR2A_WGM20': '$40', # Waveform Generation Mode
+ 'TCCR2A_COM2A': '$30', # Compare Output Mode bits
+ 'TCCR2A_WGM21': '$8', # Waveform Generation Mode
+ 'TCCR2A_CS2': '$7', # Clock Select bits
+ 'TCNT2' : '$b2', # Timer/Counter2
+ 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
+ 'TIMSK2' : '$70', # Timer/Counter2 Interrupt Mask
+ 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
+ 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
+ 'TIFR2' : '$37', # Timer/Counter2 Interrupt Flag
+ 'TIFR2_OCF2A': '$2', # Timer/Counter2 Output Compare
+ 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_PSR2': '$2', # Prescaler Reset Timer/Counter2
+ 'ASSR' : '$b6', # Asynchronous Status Register
+ 'ASSR_EXCLK': '$10', # Enable External Clock Interrup
+ 'ASSR_AS2': '$8', # AS2: Asynchronous Timer/Counte
+ 'ASSR_TCN2UB': '$4', # TCN2UB: Timer/Counter2 Update
+ 'ASSR_OCR2UB': '$2', # Output Compare Register2 Updat
+ 'ASSR_TCR2UB': '$1', # TCR2UB: Timer/Counter Control
+
+# Module WATCHDOG
+ 'WDTCR' : '$60', # Watchdog Timer Control Registe
+ 'WDTCR_WDCE': '$10', # Watchdog Change Enable
+ 'WDTCR_WDE': '$8', # Watch Dog Enable
+ 'WDTCR_WDP': '$7', # Watch Dog Timer Prescaler bits
+
+# Module CPU
+ 'SREG' : '$5f', # Status Register
+ 'SREG_I': '$80', # Global Interrupt Enable
+ 'SREG_T': '$40', # Bit Copy Storage
+ 'SREG_H': '$20', # Half Carry Flag
+ 'SREG_S': '$10', # Sign Bit
+ 'SREG_V': '$8', # Two's Complement Overflow Flag
+ 'SREG_N': '$4', # Negative Flag
+ 'SREG_Z': '$2', # Zero Flag
+ 'SREG_C': '$1', # Carry Flag
+ 'SP' : '$5d', # Stack Pointer
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_JTD': '$80', # JTAG Interface Disable
+ 'MCUCR_BODS': '$40', # BOD Sleep
+ 'MCUCR_BODSE': '$20', # BOD Sleep Enable
+ 'MCUCR_PUD': '$10', # Pull-up disable
+ 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
+ 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+ 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
+ 'MCUSR_BORF': '$4', # Brown-out Reset Flag
+ 'MCUSR_EXTRF': '$2', # External Reset Flag
+ 'MCUSR_PORF': '$1', # Power-on reset flag
+ 'OSCCAL' : '$66', # Oscillator Calibration Value
+ 'CLKPR' : '$61', # Clock Prescale Register
+ 'CLKPR_CLKPCE': '$80', # Clock Prescaler Change Enable
+ 'CLKPR_CLKPS': '$f', # Clock Prescaler Select Bits
+ 'PRR' : '$64', # Power Reduction Register
+ 'PRR_PRLCD': '$10', # Power Reduction LCD
+ 'PRR_PRTIM1': '$8', # Power Reduction Timer/Counter1
+ 'PRR_PRSPI': '$4', # Power Reduction Serial Periphe
+ 'PRR_PRUSART0': '$2', # Power Reduction USART
+ 'PRR_PRADC': '$1', # Power Reduction ADC
+ 'SMCR' : '$53', # Sleep Mode Control Register
+ 'SMCR_SM': '$e', # Sleep Mode Select bits
+ 'SMCR_SE': '$1', # Sleep Enable
+ 'GPIOR2' : '$4b', # General Purpose IO Register 2
+ 'GPIOR1' : '$4a', # General Purpose IO Register 1
+ 'GPIOR0' : '$3e', # General Purpose IO Register 0
+
+ '__amforth_dummy':'0'
+}
diff --git a/amforth-6.5/avr8/devices/atmega3250pa/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega3250pa/words/no-jtag.asm
new file mode 100644
index 0000000..352a4bb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega3250pa/words/no-jtag.asm
@@ -0,0 +1,14 @@
+; ( -- )
+; ( -- )
+; MCU
+; disable jtag at runtime
+VE_NOJTAG:
+ .dw $FF05
+ .db "-jtag",0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOJTAG
+XT_NOJTAG:
+ .dw PFA_NOJTAG
+PFA_NOJTAG:
+
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega3250pa/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega3250pa/words/no-wdt.asm
new file mode 100644
index 0000000..4a12261
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega3250pa/words/no-wdt.asm
@@ -0,0 +1,22 @@
+; ( -- )
+; MCU
+; disable watch dog timer at runtime
+VE_NOWDT:
+ .dw $ff04
+ .db "-wdt"
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOWDT
+XT_NOWDT:
+ .dw PFA_NOWDT
+PFA_NOWDT:
+
+; Reset WDT
+ wdr
+; Write logical one to WDTOE and WDE
+ in_ temp1, WDTCR
+ ori temp1, (1<<WDTOE)|(1<<WDE)
+ out WDTCR, temp1
+; Turn off WDT
+ ldi temp1, (0<<WDE)
+ out_ WDTCR, temp1
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega3250pa/words/sleep.asm b/amforth-6.5/avr8/devices/atmega3250pa/words/sleep.asm
new file mode 100644
index 0000000..256249c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega3250pa/words/sleep.asm
@@ -0,0 +1,19 @@
+; ( mode -- )
+; MCU
+; put the controller into the specified sleep mode
+VE_SLEEP:
+ .dw $ff05
+ .db "sleep", 0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_SLEEP
+XT_SLEEP:
+ .dw PFA_SLEEP
+PFA_SLEEP:
+ andi tosl, 7 ; leave only legal mode bits
+ lsl tosl ; move to correct location (bits 3-1)
+ ori tosl, 1 ; set the SE bit
+ out_ SMCR, tosl ; set the sleep config
+ sleep ; nighty-night
+ out_ SMCR, zerol ; 0 protects against accidental sleeps
+ loadtos ; pop argument from stack
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega325a/atmega325a.frt b/amforth-6.5/avr8/devices/atmega325a/atmega325a.frt
new file mode 100644
index 0000000..df67434
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega325a/atmega325a.frt
@@ -0,0 +1,279 @@
+\ Partname: ATmega325A
+\ generated automatically
+
+\ AD_CONVERTER
+&124 constant ADMUX \ The ADC multiplexer Selection Register
+ $C0 constant ADMUX_REFS \ Reference Selection Bits
+ $20 constant ADMUX_ADLAR \ Left Adjust Result
+ $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
+&122 constant ADCSRA \ The ADC Control and Status register
+ $80 constant ADCSRA_ADEN \ ADC Enable
+ $40 constant ADCSRA_ADSC \ ADC Start Conversion
+ $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
+ $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
+ $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
+ $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
+&120 constant ADC \ ADC Data Register Bytes
+&123 constant ADCSRB \ ADC Control and Status Register B
+ $07 constant ADCSRB_ADTS \ ADC Auto Trigger Sources
+&126 constant DIDR0 \ Digital Input Disable Register 0
+ $80 constant DIDR0_ADC7D \ ADC7 Digital input Disable
+ $40 constant DIDR0_ADC6D \ ADC6 Digital input Disable
+ $20 constant DIDR0_ADC5D \ ADC5 Digital input Disable
+ $10 constant DIDR0_ADC4D \ ADC4 Digital input Disable
+ $08 constant DIDR0_ADC3D \ ADC3 Digital input Disable
+ $04 constant DIDR0_ADC2D \ ADC2 Digital input Disable
+ $02 constant DIDR0_ADC1D \ ADC1 Digital input Disable
+ $01 constant DIDR0_ADC0D \ ADC0 Digital input Disable
+\ ANALOG_COMPARATOR
+&80 constant ACSR \ Analog Comparator Control And Status Register
+ $80 constant ACSR_ACD \ Analog Comparator Disable
+ $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
+ $20 constant ACSR_ACO \ Analog Compare Output
+ $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
+ $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
+ $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
+ $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
+&127 constant DIDR1 \ Digital Input Disable Register 1
+ $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
+ $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
+\ USART0
+&198 constant UDR0 \ USART I/O Data Register
+&192 constant UCSR0A \ USART Control and Status Register A
+ $80 constant UCSR0A_RXC0 \ USART Receive Complete
+ $40 constant UCSR0A_TXC0 \ USART Transmit Complete
+ $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
+ $10 constant UCSR0A_FE0 \ Framing Error
+ $08 constant UCSR0A_DOR0 \ Data OverRun
+ $04 constant UCSR0A_UPE0 \ USART Parity Error
+ $02 constant UCSR0A_U2X0 \ Double the USART Transmission Speed
+ $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
+&193 constant UCSR0B \ USART Control and Status Register B
+ $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
+ $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
+ $20 constant UCSR0B_UDRIE0 \ USART Data Register Empty Interrupt Enable
+ $10 constant UCSR0B_RXEN0 \ Receiver Enable
+ $08 constant UCSR0B_TXEN0 \ Transmitter Enable
+ $04 constant UCSR0B_UCSZ02 \ Character Size
+ $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
+ $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
+&194 constant UCSR0C \ USART Control and Status Register C
+ $40 constant UCSR0C_UMSEL0 \ USART Mode Select
+ $30 constant UCSR0C_UPM0 \ Parity Mode Bits
+ $08 constant UCSR0C_USBS0 \ Stop Bit Select
+ $06 constant UCSR0C_UCSZ0 \ Character Size
+ $01 constant UCSR0C_UCPOL0 \ Clock Polarity
+&196 constant UBRR0 \ USART Baud Rate Register Bytes
+\ USI
+&186 constant USIDR \ USI Data Register
+&185 constant USISR \ USI Status Register
+ $80 constant USISR_USISIF \ Start Condition Interrupt Flag
+ $40 constant USISR_USIOIF \ Counter Overflow Interrupt Flag
+ $20 constant USISR_USIPF \ Stop Condition Flag
+ $10 constant USISR_USIDC \ Data Output Collision
+ $0F constant USISR_USICNT \ USI Counter Value Bits
+&184 constant USICR \ USI Control Register
+ $80 constant USICR_USISIE \ Start Condition Interrupt Enable
+ $40 constant USICR_USIOIE \ Counter Overflow Interrupt Enable
+ $30 constant USICR_USIWM \ USI Wire Mode Bits
+ $0C constant USICR_USICS \ USI Clock Source Select Bits
+ $02 constant USICR_USICLK \ Clock Strobe
+ $01 constant USICR_USITC \ Toggle Clock Port Pin
+\ SPI
+&76 constant SPCR \ SPI Control Register
+ $80 constant SPCR_SPIE \ SPI Interrupt Enable
+ $40 constant SPCR_SPE \ SPI Enable
+ $20 constant SPCR_DORD \ Data Order
+ $10 constant SPCR_MSTR \ Master/Slave Select
+ $08 constant SPCR_CPOL \ Clock polarity
+ $04 constant SPCR_CPHA \ Clock Phase
+ $03 constant SPCR_SPR \ SPI Clock Rate Selects
+&77 constant SPSR \ SPI Status Register
+ $80 constant SPSR_SPIF \ SPI Interrupt Flag
+ $40 constant SPSR_WCOL \ Write Collision Flag
+ $01 constant SPSR_SPI2X \ Double SPI Speed Bit
+&78 constant SPDR \ SPI Data Register
+\ BOOT_LOAD
+&87 constant SPMCSR \ Store Program Memory Control Register
+ $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
+ $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
+ $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
+ $04 constant SPMCSR_PGWRT \ Page Write
+ $02 constant SPMCSR_PGERS \ Page Erase
+ $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
+\ JTAG
+&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
+&85 constant MCUCR \ MCU Control Register
+ $80 constant MCUCR_JTD \ JTAG Interface Disable
+&84 constant MCUSR \ MCU Status Register
+ $10 constant MCUSR_JTRF \ JTAG Reset Flag
+\ EXTERNAL_INTERRUPT
+&105 constant EICRA \ External Interrupt Control Register A
+ $02 constant EICRA_ISC01 \ External Interrupt Sense Control 0 Bit 1
+ $01 constant EICRA_ISC00 \ External Interrupt Sense Control 0 Bit 0
+&61 constant EIMSK \ External Interrupt Mask Register
+ $F0 constant EIMSK_PCIE \ Pin Change Interrupt Enables
+ $01 constant EIMSK_INT0 \ External Interrupt Request 0 Enable
+&60 constant EIFR \ External Interrupt Flag Register
+ $F0 constant EIFR_PCIF \ Pin Change Interrupt Flags
+ $01 constant EIFR_INTF0 \ External Interrupt Flag 0
+&108 constant PCMSK1 \ Pin Change Mask Register 1
+&107 constant PCMSK0 \ Pin Change Mask Register 0
+\ EEPROM
+&65 constant EEAR \ EEPROM Read/Write Access Bytes
+&64 constant EEDR \ EEPROM Data Register
+&63 constant EECR \ EEPROM Control Register
+ $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
+ $04 constant EECR_EEMWE \ EEPROM Master Write Enable
+ $02 constant EECR_EEWE \ EEPROM Write Enable
+ $01 constant EECR_EERE \ EEPROM Read Enable
+\ PORTA
+&34 constant PORTA \ Port A Data Register
+&33 constant DDRA \ Port A Data Direction Register
+&32 constant PINA \ Port A Input Pins
+\ PORTB
+&37 constant PORTB \ Port B Data Register
+&36 constant DDRB \ Port B Data Direction Register
+&35 constant PINB \ Port B Input Pins
+\ PORTC
+&40 constant PORTC \ Port C Data Register
+&39 constant DDRC \ Port C Data Direction Register
+&38 constant PINC \ Port C Input Pins
+\ PORTD
+&43 constant PORTD \ Port D Data Register
+&42 constant DDRD \ Port D Data Direction Register
+&41 constant PIND \ Port D Input Pins
+\ PORTE
+&46 constant PORTE \ Data Register, Port E
+&45 constant DDRE \ Data Direction Register, Port E
+&44 constant PINE \ Input Pins, Port E
+\ PORTF
+&49 constant PORTF \ Data Register, Port F
+&48 constant DDRF \ Data Direction Register, Port F
+&47 constant PINF \ Input Pins, Port F
+\ PORTG
+&52 constant PORTG \ Port G Data Register
+&51 constant DDRG \ Port G Data Direction Register
+&50 constant PING \ Port G Input Pins
+\ TIMER_COUNTER_0
+&68 constant TCCR0A \ Timer/Counter0 Control Register
+ $80 constant TCCR0A_FOC0A \ Force Output Compare
+ $40 constant TCCR0A_WGM00 \ Waveform Generation Mode 0
+ $30 constant TCCR0A_COM0A \ Compare Match Output Modes
+ $08 constant TCCR0A_WGM01 \ Waveform Generation Mode 1
+ $07 constant TCCR0A_CS0 \ Clock Selects
+&70 constant TCNT0 \ Timer/Counter0
+&71 constant OCR0A \ Timer/Counter0 Output Compare Register
+&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
+ $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match Interrupt Enable
+ $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
+&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
+ $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0
+ $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
+&67 constant GTCCR \ General Timer/Control Register
+ $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
+ $01 constant GTCCR_PSR310 \ Prescaler Reset Timer/Counter1 and Timer/Counter0
+\ TIMER_COUNTER_1
+&128 constant TCCR1A \ Timer/Counter1 Control Register A
+ $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
+ $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
+ $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
+&129 constant TCCR1B \ Timer/Counter1 Control Register B
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
+ $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
+&130 constant TCCR1C \ Timer/Counter 1 Control Register C
+ $80 constant TCCR1C_FOC1A \ Force Output Compare 1A
+ $40 constant TCCR1C_FOC1B \ Force Output Compare 1B
+&132 constant TCNT1 \ Timer/Counter1 Bytes
+&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
+&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
+&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
+&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
+ $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
+ $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
+ $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
+ $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
+&54 constant TIFR1 \ Timer/Counter1 Interrupt Flag register
+ $20 constant TIFR1_ICF1 \ Input Capture Flag 1
+ $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
+ $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
+ $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
+\ TIMER_COUNTER_2
+&176 constant TCCR2A \ Timer/Counter2 Control Register
+ $80 constant TCCR2A_FOC2A \ Force Output Compare A
+ $40 constant TCCR2A_WGM20 \ Waveform Generation Mode
+ $30 constant TCCR2A_COM2A \ Compare Output Mode bits
+ $08 constant TCCR2A_WGM21 \ Waveform Generation Mode
+ $07 constant TCCR2A_CS2 \ Clock Select bits
+&178 constant TCNT2 \ Timer/Counter2
+&179 constant OCR2A \ Timer/Counter2 Output Compare Register
+&112 constant TIMSK2 \ Timer/Counter2 Interrupt Mask register
+ $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match Interrupt Enable
+ $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
+&55 constant TIFR2 \ Timer/Counter2 Interrupt Flag Register
+ $02 constant TIFR2_OCF2A \ Timer/Counter2 Output Compare Flag 2
+ $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
+&182 constant ASSR \ Asynchronous Status Register
+ $10 constant ASSR_EXCLK \ Enable External Clock Interrupt
+ $08 constant ASSR_AS2 \ AS2: Asynchronous Timer/Counter2
+ $04 constant ASSR_TCN2UB \ TCN2UB: Timer/Counter2 Update Busy
+ $02 constant ASSR_OCR2UB \ Output Compare Register2 Update Busy
+ $01 constant ASSR_TCR2UB \ TCR2UB: Timer/Counter Control Register2 Update Busy
+\ WATCHDOG
+&96 constant WDTCR \ Watchdog Timer Control Register
+ $10 constant WDTCR_WDCE \ Watchdog Change Enable
+ $08 constant WDTCR_WDE \ Watch Dog Enable
+ $07 constant WDTCR_WDP \ Watch Dog Timer Prescaler bits
+\ CPU
+&95 constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ $08 constant SREG_V \ Two's Complement Overflow Flag
+ $04 constant SREG_N \ Negative Flag
+ $02 constant SREG_Z \ Zero Flag
+ $01 constant SREG_C \ Carry Flag
+&93 constant SP \ Stack Pointer
+&102 constant OSCCAL \ Oscillator Calibration Value
+&97 constant CLKPR \ Clock Prescale Register
+ $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable
+ $0F constant CLKPR_CLKPS \ Clock Prescaler Select Bits
+&100 constant PRR \ Power Reduction Register
+ $10 constant PRR_PRLCD \ Power Reduction LCD
+ $08 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
+ $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
+ $02 constant PRR_PRUSART0 \ Power Reduction USART
+ $01 constant PRR_PRADC \ Power Reduction ADC
+&83 constant SMCR \ Sleep Mode Control Register
+ $0E constant SMCR_SM \ Sleep Mode Select bits
+ $01 constant SMCR_SE \ Sleep Enable
+&75 constant GPIOR2 \ General Purpose IO Register 2
+&74 constant GPIOR1 \ General Purpose IO Register 1
+&62 constant GPIOR0 \ General Purpose IO Register 0
+
+\ Interrupts
+&2 constant INT0Addr \ External Interrupt Request 0
+&4 constant PCINT0Addr \ Pin Change Interrupt Request 0
+&6 constant PCINT1Addr \ Pin Change Interrupt Request 1
+&8 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
+&10 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
+&12 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+&14 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
+&16 constant TIMER1_COMPBAddr \ Timer/Counter Compare Match B
+&18 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+&20 constant TIMER0_COMPAddr \ Timer/Counter0 Compare Match
+&22 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
+&24 constant SPI__STCAddr \ SPI Serial Transfer Complete
+&26 constant USART0__RXAddr \ USART0, Rx Complete
+&28 constant USART0__UDREAddr \ USART0 Data register Empty
+&30 constant USART0__TXAddr \ USART0, Tx Complete
+&32 constant USI_STARTAddr \ USI Start Condition
+&34 constant USI_OVERFLOWAddr \ USI Overflow
+&36 constant ANALOG_COMPAddr \ Analog Comparator
+&38 constant ADCAddr \ ADC Conversion Complete
+&40 constant EE_READYAddr \ EEPROM Ready
+&42 constant SPM_READYAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/atmega325a/device.asm b/amforth-6.5/avr8/devices/atmega325a/device.asm
new file mode 100644
index 0000000..75dd6c3
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega325a/device.asm
@@ -0,0 +1,106 @@
+; Partname: ATmega325A
+; generated automatically, do not edit
+
+.nolist
+ .include "m325Adef.inc"
+.list
+
+.equ ramstart = 256
+.equ CELLSIZE = 2
+.macro readflashcell
+ lsl zl
+ rol zh
+ lpm @0, Z+
+ lpm @1, Z+
+.endmacro
+.macro writeflashcell
+ lsl zl
+ rol zh
+.endmacro
+.set WANT_AD_CONVERTER = 0
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_USART0 = 0
+.set WANT_USI = 0
+.set WANT_SPI = 0
+.set WANT_BOOT_LOAD = 0
+.set WANT_JTAG = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_EEPROM = 0
+.set WANT_PORTA = 0
+.set WANT_PORTB = 0
+.set WANT_PORTC = 0
+.set WANT_PORTD = 0
+.set WANT_PORTE = 0
+.set WANT_PORTF = 0
+.set WANT_PORTG = 0
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_TIMER_COUNTER_2 = 0
+.set WANT_WATCHDOG = 0
+.set WANT_CPU = 0
+.equ intvecsize = 2 ; please verify; flash size: 32768 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.org 2
+ rcall isr ; External Interrupt Request 0
+.org 4
+ rcall isr ; Pin Change Interrupt Request 0
+.org 6
+ rcall isr ; Pin Change Interrupt Request 1
+.org 8
+ rcall isr ; Timer/Counter2 Compare Match
+.org 10
+ rcall isr ; Timer/Counter2 Overflow
+.org 12
+ rcall isr ; Timer/Counter1 Capture Event
+.org 14
+ rcall isr ; Timer/Counter1 Compare Match A
+.org 16
+ rcall isr ; Timer/Counter Compare Match B
+.org 18
+ rcall isr ; Timer/Counter1 Overflow
+.org 20
+ rcall isr ; Timer/Counter0 Compare Match
+.org 22
+ rcall isr ; Timer/Counter0 Overflow
+.org 24
+ rcall isr ; SPI Serial Transfer Complete
+.org 26
+ rcall isr ; USART0, Rx Complete
+.org 28
+ rcall isr ; USART0 Data register Empty
+.org 30
+ rcall isr ; USART0, Tx Complete
+.org 32
+ rcall isr ; USI Start Condition
+.org 34
+ rcall isr ; USI Overflow
+.org 36
+ rcall isr ; Analog Comparator
+.org 38
+ rcall isr ; ADC Conversion Complete
+.org 40
+ rcall isr ; EEPROM Ready
+.org 42
+ rcall isr ; Store Program Memory Read
+.equ INTVECTORS = 22
+.nooverlap
+
+; compatability layer (maybe empty)
+.equ EEPE = EEWE
+.equ EEMPE = EEMWE
+
+; controller data area, environment query mcu-info
+mcu_info:
+mcu_ramsize:
+ .dw 2048
+mcu_eepromsize:
+ .dw 1024
+mcu_maxdp:
+ .dw 28672
+mcu_numints:
+ .dw 22
+mcu_name:
+ .dw 10
+ .db "ATmega325A"
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega325a/device.inc b/amforth-6.5/avr8/devices/atmega325a/device.inc
new file mode 100644
index 0000000..563abd6
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega325a/device.inc
@@ -0,0 +1,1050 @@
+; Partname: ATmega325A
+; generated automatically, no not edit
+
+.if WANT_AD_CONVERTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC multiplexer Selection Register
+VE_ADMUX:
+ .dw $ff05
+ .db "ADMUX",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADMUX
+XT_ADMUX:
+ .dw PFA_DOVARIABLE
+PFA_ADMUX:
+ .dw 124
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register
+VE_ADCSRA:
+ .dw $ff06
+ .db "ADCSRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRA
+XT_ADCSRA:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRA:
+ .dw 122
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register Bytes
+VE_ADC:
+ .dw $ff03
+ .db "ADC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADC
+XT_ADC:
+ .dw PFA_DOVARIABLE
+PFA_ADC:
+ .dw 120
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Control and Status Register B
+VE_ADCSRB:
+ .dw $ff06
+ .db "ADCSRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRB
+XT_ADCSRB:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRB:
+ .dw 123
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 0
+VE_DIDR0:
+ .dw $ff05
+ .db "DIDR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR0
+XT_DIDR0:
+ .dw PFA_DOVARIABLE
+PFA_DIDR0:
+ .dw 126
+
+.endif
+.if WANT_ANALOG_COMPARATOR == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Control And Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw 80
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 1
+VE_DIDR1:
+ .dw $ff05
+ .db "DIDR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR1
+XT_DIDR1:
+ .dw PFA_DOVARIABLE
+PFA_DIDR1:
+ .dw 127
+
+.endif
+.if WANT_USART0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR0:
+ .dw $ff04
+ .db "UDR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR0
+XT_UDR0:
+ .dw PFA_DOVARIABLE
+PFA_UDR0:
+ .dw 198
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR0A:
+ .dw $ff06
+ .db "UCSR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0A
+XT_UCSR0A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0A:
+ .dw 192
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR0B:
+ .dw $ff06
+ .db "UCSR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0B
+XT_UCSR0B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0B:
+ .dw 193
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR0C:
+ .dw $ff06
+ .db "UCSR0C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0C
+XT_UCSR0C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0C:
+ .dw 194
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Bytes
+VE_UBRR0:
+ .dw $ff05
+ .db "UBRR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR0
+XT_UBRR0:
+ .dw PFA_DOVARIABLE
+PFA_UBRR0:
+ .dw 196
+
+.endif
+.if WANT_USI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USI Data Register
+VE_USIDR:
+ .dw $ff05
+ .db "USIDR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USIDR
+XT_USIDR:
+ .dw PFA_DOVARIABLE
+PFA_USIDR:
+ .dw 186
+; ( -- addr ) System Constant
+; R( -- )
+; USI Status Register
+VE_USISR:
+ .dw $ff05
+ .db "USISR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USISR
+XT_USISR:
+ .dw PFA_DOVARIABLE
+PFA_USISR:
+ .dw 185
+; ( -- addr ) System Constant
+; R( -- )
+; USI Control Register
+VE_USICR:
+ .dw $ff05
+ .db "USICR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USICR
+XT_USICR:
+ .dw PFA_DOVARIABLE
+PFA_USICR:
+ .dw 184
+
+.endif
+.if WANT_SPI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR:
+ .dw $ff04
+ .db "SPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR
+XT_SPCR:
+ .dw PFA_DOVARIABLE
+PFA_SPCR:
+ .dw 76
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR:
+ .dw $ff04
+ .db "SPSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR
+XT_SPSR:
+ .dw PFA_DOVARIABLE
+PFA_SPSR:
+ .dw 77
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR:
+ .dw $ff04
+ .db "SPDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR
+XT_SPDR:
+ .dw PFA_DOVARIABLE
+PFA_SPDR:
+ .dw 78
+
+.endif
+.if WANT_BOOT_LOAD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control Register
+VE_SPMCSR:
+ .dw $ff06
+ .db "SPMCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCSR
+XT_SPMCSR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCSR:
+ .dw 87
+
+.endif
+.if WANT_JTAG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; On-Chip Debug Related Register in I/O Memory
+VE_OCDR:
+ .dw $ff04
+ .db "OCDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCDR
+XT_OCDR:
+ .dw PFA_DOVARIABLE
+PFA_OCDR:
+ .dw 81
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw 85
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Status Register
+VE_MCUSR:
+ .dw $ff05
+ .db "MCUSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUSR
+XT_MCUSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUSR:
+ .dw 84
+
+.endif
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register A
+VE_EICRA:
+ .dw $ff05
+ .db "EICRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRA
+XT_EICRA:
+ .dw PFA_DOVARIABLE
+PFA_EICRA:
+ .dw 105
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Mask Register
+VE_EIMSK:
+ .dw $ff05
+ .db "EIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIMSK
+XT_EIMSK:
+ .dw PFA_DOVARIABLE
+PFA_EIMSK:
+ .dw 61
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Flag Register
+VE_EIFR:
+ .dw $ff04
+ .db "EIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIFR
+XT_EIFR:
+ .dw PFA_DOVARIABLE
+PFA_EIFR:
+ .dw 60
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 1
+VE_PCMSK1:
+ .dw $ff06
+ .db "PCMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK1
+XT_PCMSK1:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK1:
+ .dw 108
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 0
+VE_PCMSK0:
+ .dw $ff06
+ .db "PCMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK0
+XT_PCMSK0:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK0:
+ .dw 107
+
+.endif
+.if WANT_EEPROM == 1
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Read/Write Access Bytes
+VE_EEAR:
+ .dw $ff04
+ .db "EEAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEAR
+XT_EEAR:
+ .dw PFA_DOVARIABLE
+PFA_EEAR:
+ .dw 65
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw 64
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw 63
+
+.endif
+.if WANT_PORTA == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Register
+VE_PORTA:
+ .dw $ff05
+ .db "PORTA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTA
+XT_PORTA:
+ .dw PFA_DOVARIABLE
+PFA_PORTA:
+ .dw 34
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Direction Register
+VE_DDRA:
+ .dw $ff04
+ .db "DDRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRA
+XT_DDRA:
+ .dw PFA_DOVARIABLE
+PFA_DDRA:
+ .dw 33
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Input Pins
+VE_PINA:
+ .dw $ff04
+ .db "PINA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINA
+XT_PINA:
+ .dw PFA_DOVARIABLE
+PFA_PINA:
+ .dw 32
+
+.endif
+.if WANT_PORTB == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw 37
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw 36
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw 35
+
+.endif
+.if WANT_PORTC == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Register
+VE_PORTC:
+ .dw $ff05
+ .db "PORTC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTC
+XT_PORTC:
+ .dw PFA_DOVARIABLE
+PFA_PORTC:
+ .dw 40
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Direction Register
+VE_DDRC:
+ .dw $ff04
+ .db "DDRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRC
+XT_DDRC:
+ .dw PFA_DOVARIABLE
+PFA_DDRC:
+ .dw 39
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Input Pins
+VE_PINC:
+ .dw $ff04
+ .db "PINC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINC
+XT_PINC:
+ .dw PFA_DOVARIABLE
+PFA_PINC:
+ .dw 38
+
+.endif
+.if WANT_PORTD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw 43
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw 42
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw 41
+
+.endif
+.if WANT_PORTE == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port E
+VE_PORTE:
+ .dw $ff05
+ .db "PORTE",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTE
+XT_PORTE:
+ .dw PFA_DOVARIABLE
+PFA_PORTE:
+ .dw 46
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port E
+VE_DDRE:
+ .dw $ff04
+ .db "DDRE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRE
+XT_DDRE:
+ .dw PFA_DOVARIABLE
+PFA_DDRE:
+ .dw 45
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port E
+VE_PINE:
+ .dw $ff04
+ .db "PINE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINE
+XT_PINE:
+ .dw PFA_DOVARIABLE
+PFA_PINE:
+ .dw 44
+
+.endif
+.if WANT_PORTF == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port F
+VE_PORTF:
+ .dw $ff05
+ .db "PORTF",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTF
+XT_PORTF:
+ .dw PFA_DOVARIABLE
+PFA_PORTF:
+ .dw 49
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port F
+VE_DDRF:
+ .dw $ff04
+ .db "DDRF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRF
+XT_DDRF:
+ .dw PFA_DOVARIABLE
+PFA_DDRF:
+ .dw 48
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port F
+VE_PINF:
+ .dw $ff04
+ .db "PINF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINF
+XT_PINF:
+ .dw PFA_DOVARIABLE
+PFA_PINF:
+ .dw 47
+
+.endif
+.if WANT_PORTG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Data Register
+VE_PORTG:
+ .dw $ff05
+ .db "PORTG",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTG
+XT_PORTG:
+ .dw PFA_DOVARIABLE
+PFA_PORTG:
+ .dw 52
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Data Direction Register
+VE_DDRG:
+ .dw $ff04
+ .db "DDRG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRG
+XT_DDRG:
+ .dw PFA_DOVARIABLE
+PFA_DDRG:
+ .dw 51
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Input Pins
+VE_PING:
+ .dw $ff04
+ .db "PING"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PING
+XT_PING:
+ .dw PFA_DOVARIABLE
+PFA_PING:
+ .dw 50
+
+.endif
+.if WANT_TIMER_COUNTER_0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Control Register
+VE_TCCR0A:
+ .dw $ff06
+ .db "TCCR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0A
+XT_TCCR0A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0A:
+ .dw 68
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw 70
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0A:
+ .dw $ff05
+ .db "OCR0A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0A
+XT_OCR0A:
+ .dw PFA_DOVARIABLE
+PFA_OCR0A:
+ .dw 71
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Mask Register
+VE_TIMSK0:
+ .dw $ff06
+ .db "TIMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK0
+XT_TIMSK0:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK0:
+ .dw 110
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Flag register
+VE_TIFR0:
+ .dw $ff05
+ .db "TIFR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR0
+XT_TIFR0:
+ .dw PFA_DOVARIABLE
+PFA_TIFR0:
+ .dw 53
+; ( -- addr ) System Constant
+; R( -- )
+; General Timer/Control Register
+VE_GTCCR:
+ .dw $ff05
+ .db "GTCCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GTCCR
+XT_GTCCR:
+ .dw PFA_DOVARIABLE
+PFA_GTCCR:
+ .dw 67
+
+.endif
+.if WANT_TIMER_COUNTER_1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw 128
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw 129
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter 1 Control Register C
+VE_TCCR1C:
+ .dw $ff06
+ .db "TCCR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1C
+XT_TCCR1C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1C:
+ .dw 130
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Bytes
+VE_TCNT1:
+ .dw $ff05
+ .db "TCNT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1
+XT_TCNT1:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1:
+ .dw 132
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register A Bytes
+VE_OCR1A:
+ .dw $ff05
+ .db "OCR1A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1A
+XT_OCR1A:
+ .dw PFA_DOVARIABLE
+PFA_OCR1A:
+ .dw 136
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register B Bytes
+VE_OCR1B:
+ .dw $ff05
+ .db "OCR1B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1B
+XT_OCR1B:
+ .dw PFA_DOVARIABLE
+PFA_OCR1B:
+ .dw 138
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Bytes
+VE_ICR1:
+ .dw $ff04
+ .db "ICR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1
+XT_ICR1:
+ .dw PFA_DOVARIABLE
+PFA_ICR1:
+ .dw 134
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Mask Register
+VE_TIMSK1:
+ .dw $ff06
+ .db "TIMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK1
+XT_TIMSK1:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK1:
+ .dw 111
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Flag register
+VE_TIFR1:
+ .dw $ff05
+ .db "TIFR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR1
+XT_TIFR1:
+ .dw PFA_DOVARIABLE
+PFA_TIFR1:
+ .dw 54
+
+.endif
+.if WANT_TIMER_COUNTER_2 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register
+VE_TCCR2A:
+ .dw $ff06
+ .db "TCCR2A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2A
+XT_TCCR2A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2A:
+ .dw 176
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2
+VE_TCNT2:
+ .dw $ff05
+ .db "TCNT2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT2
+XT_TCNT2:
+ .dw PFA_DOVARIABLE
+PFA_TCNT2:
+ .dw 178
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register
+VE_OCR2A:
+ .dw $ff05
+ .db "OCR2A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2A
+XT_OCR2A:
+ .dw PFA_DOVARIABLE
+PFA_OCR2A:
+ .dw 179
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Interrupt Mask register
+VE_TIMSK2:
+ .dw $ff06
+ .db "TIMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK2
+XT_TIMSK2:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK2:
+ .dw 112
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Interrupt Flag Register
+VE_TIFR2:
+ .dw $ff05
+ .db "TIFR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR2
+XT_TIFR2:
+ .dw PFA_DOVARIABLE
+PFA_TIFR2:
+ .dw 55
+; ( -- addr ) System Constant
+; R( -- )
+; Asynchronous Status Register
+VE_ASSR:
+ .dw $ff04
+ .db "ASSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ASSR
+XT_ASSR:
+ .dw PFA_DOVARIABLE
+PFA_ASSR:
+ .dw 182
+
+.endif
+.if WANT_WATCHDOG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCR:
+ .dw $ff05
+ .db "WDTCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCR
+XT_WDTCR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCR:
+ .dw 96
+
+.endif
+.if WANT_CPU == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw 95
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer
+VE_SP:
+ .dw $ff02
+ .db "SP"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SP
+XT_SP:
+ .dw PFA_DOVARIABLE
+PFA_SP:
+ .dw 93
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Calibration Value
+VE_OSCCAL:
+ .dw $ff06
+ .db "OSCCAL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSCCAL
+XT_OSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_OSCCAL:
+ .dw 102
+; ( -- addr ) System Constant
+; R( -- )
+; Clock Prescale Register
+VE_CLKPR:
+ .dw $ff05
+ .db "CLKPR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKPR
+XT_CLKPR:
+ .dw PFA_DOVARIABLE
+PFA_CLKPR:
+ .dw 97
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register
+VE_PRR:
+ .dw $ff03
+ .db "PRR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR
+XT_PRR:
+ .dw PFA_DOVARIABLE
+PFA_PRR:
+ .dw 100
+; ( -- addr ) System Constant
+; R( -- )
+; Sleep Mode Control Register
+VE_SMCR:
+ .dw $ff04
+ .db "SMCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SMCR
+XT_SMCR:
+ .dw PFA_DOVARIABLE
+PFA_SMCR:
+ .dw 83
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 2
+VE_GPIOR2:
+ .dw $ff06
+ .db "GPIOR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR2
+XT_GPIOR2:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR2:
+ .dw 75
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 1
+VE_GPIOR1:
+ .dw $ff06
+ .db "GPIOR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR1
+XT_GPIOR1:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR1:
+ .dw 74
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 0
+VE_GPIOR0:
+ .dw $ff06
+ .db "GPIOR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR0
+XT_GPIOR0:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR0:
+ .dw 62
+
+.endif
diff --git a/amforth-6.5/avr8/devices/atmega325a/device.py b/amforth-6.5/avr8/devices/atmega325a/device.py
new file mode 100644
index 0000000..801a088
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega325a/device.py
@@ -0,0 +1,319 @@
+# Generated Automatically
+
+# Partname ATmega325A
+
+MCUREGS = {
+# Interrupt Vectors
+ 'INT0Addr' : '#2', # External Interrupt Request 0
+ 'PCINT0Addr' : '#4', # Pin Change Interrupt Request 0
+ 'PCINT1Addr' : '#6', # Pin Change Interrupt Request 1
+ 'TIMER2_COMPAddr' : '#8', # Timer/Counter2 Compare Match
+ 'TIMER2_OVFAddr' : '#10', # Timer/Counter2 Overflow
+ 'TIMER1_CAPTAddr' : '#12', # Timer/Counter1 Capture Event
+ 'TIMER1_COMPAAddr' : '#14', # Timer/Counter1 Compare Match A
+ 'TIMER1_COMPBAddr' : '#16', # Timer/Counter Compare Match B
+ 'TIMER1_OVFAddr' : '#18', # Timer/Counter1 Overflow
+ 'TIMER0_COMPAddr' : '#20', # Timer/Counter0 Compare Match
+ 'TIMER0_OVFAddr' : '#22', # Timer/Counter0 Overflow
+ 'SPI_STCAddr' : '#24', # SPI Serial Transfer Complete
+ 'USART0_RXAddr' : '#26', # USART0, Rx Complete
+ 'USART0_UDREAddr' : '#28', # USART0 Data register Empty
+ 'USART0_TXAddr' : '#30', # USART0, Tx Complete
+ 'USI_STARTAddr' : '#32', # USI Start Condition
+ 'USI_OVERFLOWAddr' : '#34', # USI Overflow
+ 'ANALOG_COMPAddr' : '#36', # Analog Comparator
+ 'ADCAddr' : '#38', # ADC Conversion Complete
+ 'EE_READYAddr' : '#40', # EEPROM Ready
+ 'SPM_READYAddr' : '#42', # Store Program Memory Read
+
+# Module AD_CONVERTER
+ 'ADMUX' : '$7c', # The ADC multiplexer Selection
+ 'ADMUX_REFS': '$c0', # Reference Selection Bits
+ 'ADMUX_ADLAR': '$20', # Left Adjust Result
+ 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
+ 'ADCSRA' : '$7a', # The ADC Control and Status reg
+ 'ADCSRA_ADEN': '$80', # ADC Enable
+ 'ADCSRA_ADSC': '$40', # ADC Start Conversion
+ 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
+ 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
+ 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
+ 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
+ 'ADC' : '$78', # ADC Data Register Bytes
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Sources
+ 'DIDR0' : '$7e', # Digital Input Disable Register
+ 'DIDR0_ADC7D': '$80', # ADC7 Digital input Disable
+ 'DIDR0_ADC6D': '$40', # ADC6 Digital input Disable
+ 'DIDR0_ADC5D': '$20', # ADC5 Digital input Disable
+ 'DIDR0_ADC4D': '$10', # ADC4 Digital input Disable
+ 'DIDR0_ADC3D': '$8', # ADC3 Digital input Disable
+ 'DIDR0_ADC2D': '$4', # ADC2 Digital input Disable
+ 'DIDR0_ADC1D': '$2', # ADC1 Digital input Disable
+ 'DIDR0_ADC0D': '$1', # ADC0 Digital input Disable
+
+# Module ANALOG_COMPARATOR
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
+ 'ACSR' : '$50', # Analog Comparator Control And
+ 'ACSR_ACD': '$80', # Analog Comparator Disable
+ 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
+ 'ACSR_ACO': '$20', # Analog Compare Output
+ 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
+ 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
+ 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
+ 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
+ 'DIDR1' : '$7f', # Digital Input Disable Register
+ 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
+ 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
+
+# Module USART0
+ 'UDR0' : '$c6', # USART I/O Data Register
+ 'UCSR0A' : '$c0', # USART Control and Status Regis
+ 'UCSR0A_RXC0': '$80', # USART Receive Complete
+ 'UCSR0A_TXC0': '$40', # USART Transmit Complete
+ 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
+ 'UCSR0A_FE0': '$10', # Framing Error
+ 'UCSR0A_DOR0': '$8', # Data OverRun
+ 'UCSR0A_UPE0': '$4', # USART Parity Error
+ 'UCSR0A_U2X0': '$2', # Double the USART Transmission
+ 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
+ 'UCSR0B' : '$c1', # USART Control and Status Regis
+ 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
+ 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
+ 'UCSR0B_UDRIE0': '$20', # USART Data Register Empty Inte
+ 'UCSR0B_RXEN0': '$10', # Receiver Enable
+ 'UCSR0B_TXEN0': '$8', # Transmitter Enable
+ 'UCSR0B_UCSZ02': '$4', # Character Size
+ 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
+ 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
+ 'UCSR0C' : '$c2', # USART Control and Status Regis
+ 'UCSR0C_UMSEL0': '$40', # USART Mode Select
+ 'UCSR0C_UPM0': '$30', # Parity Mode Bits
+ 'UCSR0C_USBS0': '$8', # Stop Bit Select
+ 'UCSR0C_UCSZ0': '$6', # Character Size
+ 'UCSR0C_UCPOL0': '$1', # Clock Polarity
+ 'UBRR0' : '$c4', # USART Baud Rate Register Byte
+
+# Module USI
+ 'USIDR' : '$ba', # USI Data Register
+ 'USISR' : '$b9', # USI Status Register
+ 'USISR_USISIF': '$80', # Start Condition Interrupt Flag
+ 'USISR_USIOIF': '$40', # Counter Overflow Interrupt Fla
+ 'USISR_USIPF': '$20', # Stop Condition Flag
+ 'USISR_USIDC': '$10', # Data Output Collision
+ 'USISR_USICNT': '$f', # USI Counter Value Bits
+ 'USICR' : '$b8', # USI Control Register
+ 'USICR_USISIE': '$80', # Start Condition Interrupt Enab
+ 'USICR_USIOIE': '$40', # Counter Overflow Interrupt Ena
+ 'USICR_USIWM': '$30', # USI Wire Mode Bits
+ 'USICR_USICS': '$c', # USI Clock Source Select Bits
+ 'USICR_USICLK': '$2', # Clock Strobe
+ 'USICR_USITC': '$1', # Toggle Clock Port Pin
+
+# Module SPI
+ 'SPCR' : '$4c', # SPI Control Register
+ 'SPCR_SPIE': '$80', # SPI Interrupt Enable
+ 'SPCR_SPE': '$40', # SPI Enable
+ 'SPCR_DORD': '$20', # Data Order
+ 'SPCR_MSTR': '$10', # Master/Slave Select
+ 'SPCR_CPOL': '$8', # Clock polarity
+ 'SPCR_CPHA': '$4', # Clock Phase
+ 'SPCR_SPR': '$3', # SPI Clock Rate Selects
+ 'SPSR' : '$4d', # SPI Status Register
+ 'SPSR_SPIF': '$80', # SPI Interrupt Flag
+ 'SPSR_WCOL': '$40', # Write Collision Flag
+ 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
+ 'SPDR' : '$4e', # SPI Data Register
+
+# Module BOOT_LOAD
+ 'SPMCSR' : '$57', # Store Program Memory Control R
+ 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
+ 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
+ 'SPMCSR_RWWSRE': '$10', # Read While Write section read
+ 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
+ 'SPMCSR_PGWRT': '$4', # Page Write
+ 'SPMCSR_PGERS': '$2', # Page Erase
+ 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
+
+# Module JTAG
+ 'OCDR' : '$51', # On-Chip Debug Related Register
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_JTD': '$80', # JTAG Interface Disable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+
+# Module EXTERNAL_INTERRUPT
+ 'EICRA' : '$69', # External Interrupt Control Reg
+ 'EICRA_ISC01': '$2', # External Interrupt Sense Contr
+ 'EICRA_ISC00': '$1', # External Interrupt Sense Contr
+ 'EIMSK' : '$3d', # External Interrupt Mask Regist
+ 'EIMSK_PCIE': '$f0', # Pin Change Interrupt Enables
+ 'EIMSK_INT0': '$1', # External Interrupt Request 0 E
+ 'EIFR' : '$3c', # External Interrupt Flag Regist
+ 'EIFR_PCIF': '$f0', # Pin Change Interrupt Flags
+ 'EIFR_INTF0': '$1', # External Interrupt Flag 0
+ 'PCMSK1' : '$6c', # Pin Change Mask Register 1
+ 'PCMSK0' : '$6b', # Pin Change Mask Register 0
+
+# Module EEPROM
+ 'EEAR' : '$41', # EEPROM Read/Write Access Byte
+ 'EEDR' : '$40', # EEPROM Data Register
+ 'EECR' : '$3f', # EEPROM Control Register
+ 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
+ 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
+ 'EECR_EEWE': '$2', # EEPROM Write Enable
+ 'EECR_EERE': '$1', # EEPROM Read Enable
+
+# Module PORTA
+ 'PORTA' : '$22', # Port A Data Register
+ 'DDRA' : '$21', # Port A Data Direction Register
+ 'PINA' : '$20', # Port A Input Pins
+
+# Module PORTB
+ 'PORTB' : '$25', # Port B Data Register
+ 'DDRB' : '$24', # Port B Data Direction Register
+ 'PINB' : '$23', # Port B Input Pins
+
+# Module PORTC
+ 'PORTC' : '$28', # Port C Data Register
+ 'DDRC' : '$27', # Port C Data Direction Register
+ 'PINC' : '$26', # Port C Input Pins
+
+# Module PORTD
+ 'PORTD' : '$2b', # Port D Data Register
+ 'DDRD' : '$2a', # Port D Data Direction Register
+ 'PIND' : '$29', # Port D Input Pins
+
+# Module PORTE
+ 'PORTE' : '$2e', # Data Register, Port E
+ 'DDRE' : '$2d', # Data Direction Register, Port
+ 'PINE' : '$2c', # Input Pins, Port E
+
+# Module PORTF
+ 'PORTF' : '$31', # Data Register, Port F
+ 'DDRF' : '$30', # Data Direction Register, Port
+ 'PINF' : '$2f', # Input Pins, Port F
+
+# Module PORTG
+ 'PORTG' : '$34', # Port G Data Register
+ 'DDRG' : '$33', # Port G Data Direction Register
+ 'PING' : '$32', # Port G Input Pins
+
+# Module TIMER_COUNTER_0
+ 'TCCR0A' : '$44', # Timer/Counter0 Control Registe
+ 'TCCR0A_FOC0A': '$80', # Force Output Compare
+ 'TCCR0A_WGM00': '$40', # Waveform Generation Mode 0
+ 'TCCR0A_COM0A': '$30', # Compare Match Output Modes
+ 'TCCR0A_WGM01': '$8', # Waveform Generation Mode 1
+ 'TCCR0A_CS0': '$7', # Clock Selects
+ 'TCNT0' : '$46', # Timer/Counter0
+ 'OCR0A' : '$47', # Timer/Counter0 Output Compare
+ 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
+ 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
+ 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
+ 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
+ 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
+ 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Control Register
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSR310': '$1', # Prescaler Reset Timer/Counter1
+
+# Module TIMER_COUNTER_1
+ 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
+ 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
+ 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
+ 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
+ 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
+ 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
+ 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
+ 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
+ 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
+ 'TCCR1C' : '$82', # Timer/Counter 1 Control Regist
+ 'TCCR1C_FOC1A': '$80', # Force Output Compare 1A
+ 'TCCR1C_FOC1B': '$40', # Force Output Compare 1B
+ 'TCNT1' : '$84', # Timer/Counter1 Bytes
+ 'OCR1A' : '$88', # Timer/Counter1 Output Compare
+ 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
+ 'ICR1' : '$86', # Timer/Counter1 Input Capture R
+ 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
+ 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
+ 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
+ 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
+ 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
+ 'TIFR1' : '$36', # Timer/Counter1 Interrupt Flag
+ 'TIFR1_ICF1': '$20', # Input Capture Flag 1
+ 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
+ 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
+ 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
+
+# Module TIMER_COUNTER_2
+ 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
+ 'TCCR2A_FOC2A': '$80', # Force Output Compare A
+ 'TCCR2A_WGM20': '$40', # Waveform Generation Mode
+ 'TCCR2A_COM2A': '$30', # Compare Output Mode bits
+ 'TCCR2A_WGM21': '$8', # Waveform Generation Mode
+ 'TCCR2A_CS2': '$7', # Clock Select bits
+ 'TCNT2' : '$b2', # Timer/Counter2
+ 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
+ 'TIMSK2' : '$70', # Timer/Counter2 Interrupt Mask
+ 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
+ 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
+ 'TIFR2' : '$37', # Timer/Counter2 Interrupt Flag
+ 'TIFR2_OCF2A': '$2', # Timer/Counter2 Output Compare
+ 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_PSR2': '$2', # Prescaler Reset Timer/Counter2
+ 'ASSR' : '$b6', # Asynchronous Status Register
+ 'ASSR_EXCLK': '$10', # Enable External Clock Interrup
+ 'ASSR_AS2': '$8', # AS2: Asynchronous Timer/Counte
+ 'ASSR_TCN2UB': '$4', # TCN2UB: Timer/Counter2 Update
+ 'ASSR_OCR2UB': '$2', # Output Compare Register2 Updat
+ 'ASSR_TCR2UB': '$1', # TCR2UB: Timer/Counter Control
+
+# Module WATCHDOG
+ 'WDTCR' : '$60', # Watchdog Timer Control Registe
+ 'WDTCR_WDCE': '$10', # Watchdog Change Enable
+ 'WDTCR_WDE': '$8', # Watch Dog Enable
+ 'WDTCR_WDP': '$7', # Watch Dog Timer Prescaler bits
+
+# Module CPU
+ 'SREG' : '$5f', # Status Register
+ 'SREG_I': '$80', # Global Interrupt Enable
+ 'SREG_T': '$40', # Bit Copy Storage
+ 'SREG_H': '$20', # Half Carry Flag
+ 'SREG_S': '$10', # Sign Bit
+ 'SREG_V': '$8', # Two's Complement Overflow Flag
+ 'SREG_N': '$4', # Negative Flag
+ 'SREG_Z': '$2', # Zero Flag
+ 'SREG_C': '$1', # Carry Flag
+ 'SP' : '$5d', # Stack Pointer
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_JTD': '$80', # JTAG Interface Disable
+ 'MCUCR_PUD': '$10', # Pull-up disable
+ 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
+ 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+ 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
+ 'MCUSR_BORF': '$4', # Brown-out Reset Flag
+ 'MCUSR_EXTRF': '$2', # External Reset Flag
+ 'MCUSR_PORF': '$1', # Power-on reset flag
+ 'OSCCAL' : '$66', # Oscillator Calibration Value
+ 'CLKPR' : '$61', # Clock Prescale Register
+ 'CLKPR_CLKPCE': '$80', # Clock Prescaler Change Enable
+ 'CLKPR_CLKPS': '$f', # Clock Prescaler Select Bits
+ 'PRR' : '$64', # Power Reduction Register
+ 'PRR_PRLCD': '$10', # Power Reduction LCD
+ 'PRR_PRTIM1': '$8', # Power Reduction Timer/Counter1
+ 'PRR_PRSPI': '$4', # Power Reduction Serial Periphe
+ 'PRR_PRUSART0': '$2', # Power Reduction USART
+ 'PRR_PRADC': '$1', # Power Reduction ADC
+ 'SMCR' : '$53', # Sleep Mode Control Register
+ 'SMCR_SM': '$e', # Sleep Mode Select bits
+ 'SMCR_SE': '$1', # Sleep Enable
+ 'GPIOR2' : '$4b', # General Purpose IO Register 2
+ 'GPIOR1' : '$4a', # General Purpose IO Register 1
+ 'GPIOR0' : '$3e', # General Purpose IO Register 0
+
+ '__amforth_dummy':'0'
+}
diff --git a/amforth-6.5/avr8/devices/atmega325a/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega325a/words/no-jtag.asm
new file mode 100644
index 0000000..352a4bb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega325a/words/no-jtag.asm
@@ -0,0 +1,14 @@
+; ( -- )
+; ( -- )
+; MCU
+; disable jtag at runtime
+VE_NOJTAG:
+ .dw $FF05
+ .db "-jtag",0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOJTAG
+XT_NOJTAG:
+ .dw PFA_NOJTAG
+PFA_NOJTAG:
+
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega325a/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega325a/words/no-wdt.asm
new file mode 100644
index 0000000..4a12261
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega325a/words/no-wdt.asm
@@ -0,0 +1,22 @@
+; ( -- )
+; MCU
+; disable watch dog timer at runtime
+VE_NOWDT:
+ .dw $ff04
+ .db "-wdt"
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOWDT
+XT_NOWDT:
+ .dw PFA_NOWDT
+PFA_NOWDT:
+
+; Reset WDT
+ wdr
+; Write logical one to WDTOE and WDE
+ in_ temp1, WDTCR
+ ori temp1, (1<<WDTOE)|(1<<WDE)
+ out WDTCR, temp1
+; Turn off WDT
+ ldi temp1, (0<<WDE)
+ out_ WDTCR, temp1
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega325a/words/sleep.asm b/amforth-6.5/avr8/devices/atmega325a/words/sleep.asm
new file mode 100644
index 0000000..256249c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega325a/words/sleep.asm
@@ -0,0 +1,19 @@
+; ( mode -- )
+; MCU
+; put the controller into the specified sleep mode
+VE_SLEEP:
+ .dw $ff05
+ .db "sleep", 0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_SLEEP
+XT_SLEEP:
+ .dw PFA_SLEEP
+PFA_SLEEP:
+ andi tosl, 7 ; leave only legal mode bits
+ lsl tosl ; move to correct location (bits 3-1)
+ ori tosl, 1 ; set the SE bit
+ out_ SMCR, tosl ; set the sleep config
+ sleep ; nighty-night
+ out_ SMCR, zerol ; 0 protects against accidental sleeps
+ loadtos ; pop argument from stack
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega325p/atmega325p.frt b/amforth-6.5/avr8/devices/atmega325p/atmega325p.frt
new file mode 100644
index 0000000..36fd302
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega325p/atmega325p.frt
@@ -0,0 +1,279 @@
+\ Partname: ATmega325P
+\ generated automatically
+
+\ AD_CONVERTER
+&124 constant ADMUX \ The ADC multiplexer Selection Register
+ $C0 constant ADMUX_REFS \ Reference Selection Bits
+ $20 constant ADMUX_ADLAR \ Left Adjust Result
+ $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
+&122 constant ADCSRA \ The ADC Control and Status register
+ $80 constant ADCSRA_ADEN \ ADC Enable
+ $40 constant ADCSRA_ADSC \ ADC Start Conversion
+ $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
+ $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
+ $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
+ $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
+&120 constant ADC \ ADC Data Register Bytes
+&123 constant ADCSRB \ ADC Control and Status Register B
+ $07 constant ADCSRB_ADTS \ ADC Auto Trigger Sources
+&126 constant DIDR0 \ Digital Input Disable Register 0
+ $80 constant DIDR0_ADC7D \ ADC7 Digital input Disable
+ $40 constant DIDR0_ADC6D \ ADC6 Digital input Disable
+ $20 constant DIDR0_ADC5D \ ADC5 Digital input Disable
+ $10 constant DIDR0_ADC4D \ ADC4 Digital input Disable
+ $08 constant DIDR0_ADC3D \ ADC3 Digital input Disable
+ $04 constant DIDR0_ADC2D \ ADC2 Digital input Disable
+ $02 constant DIDR0_ADC1D \ ADC1 Digital input Disable
+ $01 constant DIDR0_ADC0D \ ADC0 Digital input Disable
+\ ANALOG_COMPARATOR
+&80 constant ACSR \ Analog Comparator Control And Status Register
+ $80 constant ACSR_ACD \ Analog Comparator Disable
+ $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
+ $20 constant ACSR_ACO \ Analog Compare Output
+ $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
+ $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
+ $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
+ $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
+&127 constant DIDR1 \ Digital Input Disable Register 1
+ $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
+ $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
+\ USART0
+&198 constant UDR0 \ USART I/O Data Register
+&192 constant UCSR0A \ USART Control and Status Register A
+ $80 constant UCSR0A_RXC0 \ USART Receive Complete
+ $40 constant UCSR0A_TXC0 \ USART Transmit Complete
+ $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
+ $10 constant UCSR0A_FE0 \ Framing Error
+ $08 constant UCSR0A_DOR0 \ Data OverRun
+ $04 constant UCSR0A_UPE0 \ USART Parity Error
+ $02 constant UCSR0A_U2X0 \ Double the USART Transmission Speed
+ $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
+&193 constant UCSR0B \ USART Control and Status Register B
+ $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
+ $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
+ $20 constant UCSR0B_UDRIE0 \ USART Data Register Empty Interrupt Enable
+ $10 constant UCSR0B_RXEN0 \ Receiver Enable
+ $08 constant UCSR0B_TXEN0 \ Transmitter Enable
+ $04 constant UCSR0B_UCSZ02 \ Character Size
+ $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
+ $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
+&194 constant UCSR0C \ USART Control and Status Register C
+ $40 constant UCSR0C_UMSEL0 \ USART Mode Select
+ $30 constant UCSR0C_UPM0 \ Parity Mode Bits
+ $08 constant UCSR0C_USBS0 \ Stop Bit Select
+ $06 constant UCSR0C_UCSZ0 \ Character Size
+ $01 constant UCSR0C_UCPOL0 \ Clock Polarity
+&196 constant UBRR0 \ USART Baud Rate Register Bytes
+\ USI
+&186 constant USIDR \ USI Data Register
+&185 constant USISR \ USI Status Register
+ $80 constant USISR_USISIF \ Start Condition Interrupt Flag
+ $40 constant USISR_USIOIF \ Counter Overflow Interrupt Flag
+ $20 constant USISR_USIPF \ Stop Condition Flag
+ $10 constant USISR_USIDC \ Data Output Collision
+ $0F constant USISR_USICNT \ USI Counter Value Bits
+&184 constant USICR \ USI Control Register
+ $80 constant USICR_USISIE \ Start Condition Interrupt Enable
+ $40 constant USICR_USIOIE \ Counter Overflow Interrupt Enable
+ $30 constant USICR_USIWM \ USI Wire Mode Bits
+ $0C constant USICR_USICS \ USI Clock Source Select Bits
+ $02 constant USICR_USICLK \ Clock Strobe
+ $01 constant USICR_USITC \ Toggle Clock Port Pin
+\ SPI
+&76 constant SPCR \ SPI Control Register
+ $80 constant SPCR_SPIE \ SPI Interrupt Enable
+ $40 constant SPCR_SPE \ SPI Enable
+ $20 constant SPCR_DORD \ Data Order
+ $10 constant SPCR_MSTR \ Master/Slave Select
+ $08 constant SPCR_CPOL \ Clock polarity
+ $04 constant SPCR_CPHA \ Clock Phase
+ $03 constant SPCR_SPR \ SPI Clock Rate Selects
+&77 constant SPSR \ SPI Status Register
+ $80 constant SPSR_SPIF \ SPI Interrupt Flag
+ $40 constant SPSR_WCOL \ Write Collision Flag
+ $01 constant SPSR_SPI2X \ Double SPI Speed Bit
+&78 constant SPDR \ SPI Data Register
+\ BOOT_LOAD
+&87 constant SPMCSR \ Store Program Memory Control Register
+ $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
+ $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
+ $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
+ $04 constant SPMCSR_PGWRT \ Page Write
+ $02 constant SPMCSR_PGERS \ Page Erase
+ $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
+\ JTAG
+&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
+&85 constant MCUCR \ MCU Control Register
+ $80 constant MCUCR_JTD \ JTAG Interface Disable
+&84 constant MCUSR \ MCU Status Register
+ $10 constant MCUSR_JTRF \ JTAG Reset Flag
+\ EXTERNAL_INTERRUPT
+&105 constant EICRA \ External Interrupt Control Register A
+ $02 constant EICRA_ISC01 \ External Interrupt Sense Control 0 Bit 1
+ $01 constant EICRA_ISC00 \ External Interrupt Sense Control 0 Bit 0
+&61 constant EIMSK \ External Interrupt Mask Register
+ $F0 constant EIMSK_PCIE \ Pin Change Interrupt Enables
+ $01 constant EIMSK_INT0 \ External Interrupt Request 0 Enable
+&60 constant EIFR \ External Interrupt Flag Register
+ $F0 constant EIFR_PCIF \ Pin Change Interrupt Flags
+ $01 constant EIFR_INTF0 \ External Interrupt Flag 0
+&108 constant PCMSK1 \ Pin Change Mask Register 1
+&107 constant PCMSK0 \ Pin Change Mask Register 0
+\ EEPROM
+&65 constant EEAR \ EEPROM Read/Write Access Bytes
+&64 constant EEDR \ EEPROM Data Register
+&63 constant EECR \ EEPROM Control Register
+ $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
+ $04 constant EECR_EEMWE \ EEPROM Master Write Enable
+ $02 constant EECR_EEWE \ EEPROM Write Enable
+ $01 constant EECR_EERE \ EEPROM Read Enable
+\ PORTA
+&34 constant PORTA \ Port A Data Register
+&33 constant DDRA \ Port A Data Direction Register
+&32 constant PINA \ Port A Input Pins
+\ PORTB
+&37 constant PORTB \ Port B Data Register
+&36 constant DDRB \ Port B Data Direction Register
+&35 constant PINB \ Port B Input Pins
+\ PORTC
+&40 constant PORTC \ Port C Data Register
+&39 constant DDRC \ Port C Data Direction Register
+&38 constant PINC \ Port C Input Pins
+\ PORTD
+&43 constant PORTD \ Port D Data Register
+&42 constant DDRD \ Port D Data Direction Register
+&41 constant PIND \ Port D Input Pins
+\ PORTE
+&46 constant PORTE \ Data Register, Port E
+&45 constant DDRE \ Data Direction Register, Port E
+&44 constant PINE \ Input Pins, Port E
+\ PORTF
+&49 constant PORTF \ Data Register, Port F
+&48 constant DDRF \ Data Direction Register, Port F
+&47 constant PINF \ Input Pins, Port F
+\ PORTG
+&52 constant PORTG \ Port G Data Register
+&51 constant DDRG \ Port G Data Direction Register
+&50 constant PING \ Port G Input Pins
+\ TIMER_COUNTER_0
+&68 constant TCCR0A \ Timer/Counter0 Control Register
+ $80 constant TCCR0A_FOC0A \ Force Output Compare
+ $40 constant TCCR0A_WGM00 \ Waveform Generation Mode 0
+ $30 constant TCCR0A_COM0A \ Compare Match Output Modes
+ $08 constant TCCR0A_WGM01 \ Waveform Generation Mode 1
+ $07 constant TCCR0A_CS0 \ Clock Selects
+&70 constant TCNT0 \ Timer/Counter0
+&71 constant OCR0A \ Timer/Counter0 Output Compare Register
+&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
+ $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match Interrupt Enable
+ $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
+&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
+ $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0
+ $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
+&67 constant GTCCR \ General Timer/Control Register
+ $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
+ $01 constant GTCCR_PSR310 \ Prescaler Reset Timer/Counter1 and Timer/Counter0
+\ TIMER_COUNTER_1
+&128 constant TCCR1A \ Timer/Counter1 Control Register A
+ $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
+ $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
+ $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
+&129 constant TCCR1B \ Timer/Counter1 Control Register B
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
+ $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
+&130 constant TCCR1C \ Timer/Counter 1 Control Register C
+ $80 constant TCCR1C_FOC1A \ Force Output Compare 1A
+ $40 constant TCCR1C_FOC1B \ Force Output Compare 1B
+&132 constant TCNT1 \ Timer/Counter1 Bytes
+&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
+&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
+&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
+&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
+ $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
+ $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
+ $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
+ $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
+&54 constant TIFR1 \ Timer/Counter1 Interrupt Flag register
+ $20 constant TIFR1_ICF1 \ Input Capture Flag 1
+ $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
+ $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
+ $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
+\ TIMER_COUNTER_2
+&176 constant TCCR2A \ Timer/Counter2 Control Register
+ $80 constant TCCR2A_FOC2A \ Force Output Compare A
+ $40 constant TCCR2A_WGM20 \ Waveform Generation Mode
+ $30 constant TCCR2A_COM2A \ Compare Output Mode bits
+ $08 constant TCCR2A_WGM21 \ Waveform Generation Mode
+ $07 constant TCCR2A_CS2 \ Clock Select bits
+&178 constant TCNT2 \ Timer/Counter2
+&179 constant OCR2A \ Timer/Counter2 Output Compare Register
+&112 constant TIMSK2 \ Timer/Counter2 Interrupt Mask register
+ $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match Interrupt Enable
+ $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
+&55 constant TIFR2 \ Timer/Counter2 Interrupt Flag Register
+ $02 constant TIFR2_OCF2A \ Timer/Counter2 Output Compare Flag 2
+ $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
+&182 constant ASSR \ Asynchronous Status Register
+ $10 constant ASSR_EXCLK \ Enable External Clock Interrupt
+ $08 constant ASSR_AS2 \ AS2: Asynchronous Timer/Counter2
+ $04 constant ASSR_TCN2UB \ TCN2UB: Timer/Counter2 Update Busy
+ $02 constant ASSR_OCR2UB \ Output Compare Register2 Update Busy
+ $01 constant ASSR_TCR2UB \ TCR2UB: Timer/Counter Control Register2 Update Busy
+\ WATCHDOG
+&96 constant WDTCR \ Watchdog Timer Control Register
+ $10 constant WDTCR_WDCE \ Watchdog Change Enable
+ $08 constant WDTCR_WDE \ Watch Dog Enable
+ $07 constant WDTCR_WDP \ Watch Dog Timer Prescaler bits
+\ CPU
+&95 constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ $08 constant SREG_V \ Two's Complement Overflow Flag
+ $04 constant SREG_N \ Negative Flag
+ $02 constant SREG_Z \ Zero Flag
+ $01 constant SREG_C \ Carry Flag
+&93 constant SP \ Stack Pointer
+&102 constant OSCCAL \ Oscillator Calibration Value
+&97 constant CLKPR \ Clock Prescale Register
+ $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable
+ $0F constant CLKPR_CLKPS \ Clock Prescaler Select Bits
+&100 constant PRR \ Power Reduction Register
+ $10 constant PRR_PRLCD \ Power Reduction LCD
+ $08 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
+ $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
+ $02 constant PRR_PRUSART0 \ Power Reduction USART
+ $01 constant PRR_PRADC \ Power Reduction ADC
+&83 constant SMCR \ Sleep Mode Control Register
+ $0E constant SMCR_SM \ Sleep Mode Select bits
+ $01 constant SMCR_SE \ Sleep Enable
+&75 constant GPIOR2 \ General Purpose IO Register 2
+&74 constant GPIOR1 \ General Purpose IO Register 1
+&62 constant GPIOR0 \ General Purpose IO Register 0
+
+\ Interrupts
+&2 constant INT0Addr \ External Interrupt Request 0
+&4 constant PCINT0Addr \ Pin Change Interrupt Request 0
+&6 constant PCINT1Addr \ Pin Change Interrupt Request 1
+&8 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
+&10 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
+&12 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+&14 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
+&16 constant TIMER1_COMPBAddr \ Timer/Counter Compare Match B
+&18 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+&20 constant TIMER0_COMPAddr \ Timer/Counter0 Compare Match
+&22 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
+&24 constant SPI__STCAddr \ SPI Serial Transfer Complete
+&26 constant USART0__RXAddr \ USART0, Rx Complete
+&28 constant USART0__UDREAddr \ USART0 Data register Empty
+&30 constant USART0__TXAddr \ USART0, Tx Complete
+&32 constant USI_STARTAddr \ USI Start Condition
+&34 constant USI_OVERFLOWAddr \ USI Overflow
+&36 constant ANALOG_COMPAddr \ Analog Comparator
+&38 constant ADCAddr \ ADC Conversion Complete
+&40 constant EE_READYAddr \ EEPROM Ready
+&42 constant SPM_READYAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/atmega325p/device.asm b/amforth-6.5/avr8/devices/atmega325p/device.asm
new file mode 100644
index 0000000..245c2de
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega325p/device.asm
@@ -0,0 +1,106 @@
+; Partname: ATmega325P
+; generated automatically, do not edit
+
+.nolist
+ .include "m325Pdef.inc"
+.list
+
+.equ ramstart = 256
+.equ CELLSIZE = 2
+.macro readflashcell
+ lsl zl
+ rol zh
+ lpm @0, Z+
+ lpm @1, Z+
+.endmacro
+.macro writeflashcell
+ lsl zl
+ rol zh
+.endmacro
+.set WANT_AD_CONVERTER = 0
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_USART0 = 0
+.set WANT_USI = 0
+.set WANT_SPI = 0
+.set WANT_BOOT_LOAD = 0
+.set WANT_JTAG = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_EEPROM = 0
+.set WANT_PORTA = 0
+.set WANT_PORTB = 0
+.set WANT_PORTC = 0
+.set WANT_PORTD = 0
+.set WANT_PORTE = 0
+.set WANT_PORTF = 0
+.set WANT_PORTG = 0
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_TIMER_COUNTER_2 = 0
+.set WANT_WATCHDOG = 0
+.set WANT_CPU = 0
+.equ intvecsize = 2 ; please verify; flash size: 32768 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.org 2
+ rcall isr ; External Interrupt Request 0
+.org 4
+ rcall isr ; Pin Change Interrupt Request 0
+.org 6
+ rcall isr ; Pin Change Interrupt Request 1
+.org 8
+ rcall isr ; Timer/Counter2 Compare Match
+.org 10
+ rcall isr ; Timer/Counter2 Overflow
+.org 12
+ rcall isr ; Timer/Counter1 Capture Event
+.org 14
+ rcall isr ; Timer/Counter1 Compare Match A
+.org 16
+ rcall isr ; Timer/Counter Compare Match B
+.org 18
+ rcall isr ; Timer/Counter1 Overflow
+.org 20
+ rcall isr ; Timer/Counter0 Compare Match
+.org 22
+ rcall isr ; Timer/Counter0 Overflow
+.org 24
+ rcall isr ; SPI Serial Transfer Complete
+.org 26
+ rcall isr ; USART0, Rx Complete
+.org 28
+ rcall isr ; USART0 Data register Empty
+.org 30
+ rcall isr ; USART0, Tx Complete
+.org 32
+ rcall isr ; USI Start Condition
+.org 34
+ rcall isr ; USI Overflow
+.org 36
+ rcall isr ; Analog Comparator
+.org 38
+ rcall isr ; ADC Conversion Complete
+.org 40
+ rcall isr ; EEPROM Ready
+.org 42
+ rcall isr ; Store Program Memory Read
+.equ INTVECTORS = 22
+.nooverlap
+
+; compatability layer (maybe empty)
+.equ EEPE = EEWE
+.equ EEMPE = EEMWE
+
+; controller data area, environment query mcu-info
+mcu_info:
+mcu_ramsize:
+ .dw 2048
+mcu_eepromsize:
+ .dw 1024
+mcu_maxdp:
+ .dw 28672
+mcu_numints:
+ .dw 22
+mcu_name:
+ .dw 10
+ .db "ATmega325P"
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega325p/device.inc b/amforth-6.5/avr8/devices/atmega325p/device.inc
new file mode 100644
index 0000000..84233a9
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega325p/device.inc
@@ -0,0 +1,1050 @@
+; Partname: ATmega325P
+; generated automatically, no not edit
+
+.if WANT_AD_CONVERTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC multiplexer Selection Register
+VE_ADMUX:
+ .dw $ff05
+ .db "ADMUX",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADMUX
+XT_ADMUX:
+ .dw PFA_DOVARIABLE
+PFA_ADMUX:
+ .dw 124
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register
+VE_ADCSRA:
+ .dw $ff06
+ .db "ADCSRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRA
+XT_ADCSRA:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRA:
+ .dw 122
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register Bytes
+VE_ADC:
+ .dw $ff03
+ .db "ADC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADC
+XT_ADC:
+ .dw PFA_DOVARIABLE
+PFA_ADC:
+ .dw 120
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Control and Status Register B
+VE_ADCSRB:
+ .dw $ff06
+ .db "ADCSRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRB
+XT_ADCSRB:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRB:
+ .dw 123
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 0
+VE_DIDR0:
+ .dw $ff05
+ .db "DIDR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR0
+XT_DIDR0:
+ .dw PFA_DOVARIABLE
+PFA_DIDR0:
+ .dw 126
+
+.endif
+.if WANT_ANALOG_COMPARATOR == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Control And Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw 80
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 1
+VE_DIDR1:
+ .dw $ff05
+ .db "DIDR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR1
+XT_DIDR1:
+ .dw PFA_DOVARIABLE
+PFA_DIDR1:
+ .dw 127
+
+.endif
+.if WANT_USART0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR0:
+ .dw $ff04
+ .db "UDR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR0
+XT_UDR0:
+ .dw PFA_DOVARIABLE
+PFA_UDR0:
+ .dw 198
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR0A:
+ .dw $ff06
+ .db "UCSR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0A
+XT_UCSR0A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0A:
+ .dw 192
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR0B:
+ .dw $ff06
+ .db "UCSR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0B
+XT_UCSR0B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0B:
+ .dw 193
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR0C:
+ .dw $ff06
+ .db "UCSR0C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0C
+XT_UCSR0C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0C:
+ .dw 194
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Bytes
+VE_UBRR0:
+ .dw $ff05
+ .db "UBRR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR0
+XT_UBRR0:
+ .dw PFA_DOVARIABLE
+PFA_UBRR0:
+ .dw 196
+
+.endif
+.if WANT_USI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USI Data Register
+VE_USIDR:
+ .dw $ff05
+ .db "USIDR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USIDR
+XT_USIDR:
+ .dw PFA_DOVARIABLE
+PFA_USIDR:
+ .dw 186
+; ( -- addr ) System Constant
+; R( -- )
+; USI Status Register
+VE_USISR:
+ .dw $ff05
+ .db "USISR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USISR
+XT_USISR:
+ .dw PFA_DOVARIABLE
+PFA_USISR:
+ .dw 185
+; ( -- addr ) System Constant
+; R( -- )
+; USI Control Register
+VE_USICR:
+ .dw $ff05
+ .db "USICR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USICR
+XT_USICR:
+ .dw PFA_DOVARIABLE
+PFA_USICR:
+ .dw 184
+
+.endif
+.if WANT_SPI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR:
+ .dw $ff04
+ .db "SPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR
+XT_SPCR:
+ .dw PFA_DOVARIABLE
+PFA_SPCR:
+ .dw 76
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR:
+ .dw $ff04
+ .db "SPSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR
+XT_SPSR:
+ .dw PFA_DOVARIABLE
+PFA_SPSR:
+ .dw 77
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR:
+ .dw $ff04
+ .db "SPDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR
+XT_SPDR:
+ .dw PFA_DOVARIABLE
+PFA_SPDR:
+ .dw 78
+
+.endif
+.if WANT_BOOT_LOAD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control Register
+VE_SPMCSR:
+ .dw $ff06
+ .db "SPMCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCSR
+XT_SPMCSR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCSR:
+ .dw 87
+
+.endif
+.if WANT_JTAG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; On-Chip Debug Related Register in I/O Memory
+VE_OCDR:
+ .dw $ff04
+ .db "OCDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCDR
+XT_OCDR:
+ .dw PFA_DOVARIABLE
+PFA_OCDR:
+ .dw 81
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw 85
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Status Register
+VE_MCUSR:
+ .dw $ff05
+ .db "MCUSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUSR
+XT_MCUSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUSR:
+ .dw 84
+
+.endif
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register A
+VE_EICRA:
+ .dw $ff05
+ .db "EICRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRA
+XT_EICRA:
+ .dw PFA_DOVARIABLE
+PFA_EICRA:
+ .dw 105
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Mask Register
+VE_EIMSK:
+ .dw $ff05
+ .db "EIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIMSK
+XT_EIMSK:
+ .dw PFA_DOVARIABLE
+PFA_EIMSK:
+ .dw 61
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Flag Register
+VE_EIFR:
+ .dw $ff04
+ .db "EIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIFR
+XT_EIFR:
+ .dw PFA_DOVARIABLE
+PFA_EIFR:
+ .dw 60
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 1
+VE_PCMSK1:
+ .dw $ff06
+ .db "PCMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK1
+XT_PCMSK1:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK1:
+ .dw 108
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 0
+VE_PCMSK0:
+ .dw $ff06
+ .db "PCMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK0
+XT_PCMSK0:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK0:
+ .dw 107
+
+.endif
+.if WANT_EEPROM == 1
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Read/Write Access Bytes
+VE_EEAR:
+ .dw $ff04
+ .db "EEAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEAR
+XT_EEAR:
+ .dw PFA_DOVARIABLE
+PFA_EEAR:
+ .dw 65
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw 64
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw 63
+
+.endif
+.if WANT_PORTA == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Register
+VE_PORTA:
+ .dw $ff05
+ .db "PORTA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTA
+XT_PORTA:
+ .dw PFA_DOVARIABLE
+PFA_PORTA:
+ .dw 34
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Direction Register
+VE_DDRA:
+ .dw $ff04
+ .db "DDRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRA
+XT_DDRA:
+ .dw PFA_DOVARIABLE
+PFA_DDRA:
+ .dw 33
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Input Pins
+VE_PINA:
+ .dw $ff04
+ .db "PINA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINA
+XT_PINA:
+ .dw PFA_DOVARIABLE
+PFA_PINA:
+ .dw 32
+
+.endif
+.if WANT_PORTB == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw 37
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw 36
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw 35
+
+.endif
+.if WANT_PORTC == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Register
+VE_PORTC:
+ .dw $ff05
+ .db "PORTC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTC
+XT_PORTC:
+ .dw PFA_DOVARIABLE
+PFA_PORTC:
+ .dw 40
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Direction Register
+VE_DDRC:
+ .dw $ff04
+ .db "DDRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRC
+XT_DDRC:
+ .dw PFA_DOVARIABLE
+PFA_DDRC:
+ .dw 39
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Input Pins
+VE_PINC:
+ .dw $ff04
+ .db "PINC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINC
+XT_PINC:
+ .dw PFA_DOVARIABLE
+PFA_PINC:
+ .dw 38
+
+.endif
+.if WANT_PORTD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw 43
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw 42
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw 41
+
+.endif
+.if WANT_PORTE == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port E
+VE_PORTE:
+ .dw $ff05
+ .db "PORTE",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTE
+XT_PORTE:
+ .dw PFA_DOVARIABLE
+PFA_PORTE:
+ .dw 46
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port E
+VE_DDRE:
+ .dw $ff04
+ .db "DDRE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRE
+XT_DDRE:
+ .dw PFA_DOVARIABLE
+PFA_DDRE:
+ .dw 45
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port E
+VE_PINE:
+ .dw $ff04
+ .db "PINE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINE
+XT_PINE:
+ .dw PFA_DOVARIABLE
+PFA_PINE:
+ .dw 44
+
+.endif
+.if WANT_PORTF == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port F
+VE_PORTF:
+ .dw $ff05
+ .db "PORTF",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTF
+XT_PORTF:
+ .dw PFA_DOVARIABLE
+PFA_PORTF:
+ .dw 49
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port F
+VE_DDRF:
+ .dw $ff04
+ .db "DDRF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRF
+XT_DDRF:
+ .dw PFA_DOVARIABLE
+PFA_DDRF:
+ .dw 48
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port F
+VE_PINF:
+ .dw $ff04
+ .db "PINF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINF
+XT_PINF:
+ .dw PFA_DOVARIABLE
+PFA_PINF:
+ .dw 47
+
+.endif
+.if WANT_PORTG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Data Register
+VE_PORTG:
+ .dw $ff05
+ .db "PORTG",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTG
+XT_PORTG:
+ .dw PFA_DOVARIABLE
+PFA_PORTG:
+ .dw 52
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Data Direction Register
+VE_DDRG:
+ .dw $ff04
+ .db "DDRG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRG
+XT_DDRG:
+ .dw PFA_DOVARIABLE
+PFA_DDRG:
+ .dw 51
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Input Pins
+VE_PING:
+ .dw $ff04
+ .db "PING"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PING
+XT_PING:
+ .dw PFA_DOVARIABLE
+PFA_PING:
+ .dw 50
+
+.endif
+.if WANT_TIMER_COUNTER_0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Control Register
+VE_TCCR0A:
+ .dw $ff06
+ .db "TCCR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0A
+XT_TCCR0A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0A:
+ .dw 68
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw 70
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0A:
+ .dw $ff05
+ .db "OCR0A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0A
+XT_OCR0A:
+ .dw PFA_DOVARIABLE
+PFA_OCR0A:
+ .dw 71
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Mask Register
+VE_TIMSK0:
+ .dw $ff06
+ .db "TIMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK0
+XT_TIMSK0:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK0:
+ .dw 110
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Flag register
+VE_TIFR0:
+ .dw $ff05
+ .db "TIFR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR0
+XT_TIFR0:
+ .dw PFA_DOVARIABLE
+PFA_TIFR0:
+ .dw 53
+; ( -- addr ) System Constant
+; R( -- )
+; General Timer/Control Register
+VE_GTCCR:
+ .dw $ff05
+ .db "GTCCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GTCCR
+XT_GTCCR:
+ .dw PFA_DOVARIABLE
+PFA_GTCCR:
+ .dw 67
+
+.endif
+.if WANT_TIMER_COUNTER_1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw 128
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw 129
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter 1 Control Register C
+VE_TCCR1C:
+ .dw $ff06
+ .db "TCCR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1C
+XT_TCCR1C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1C:
+ .dw 130
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Bytes
+VE_TCNT1:
+ .dw $ff05
+ .db "TCNT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1
+XT_TCNT1:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1:
+ .dw 132
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register A Bytes
+VE_OCR1A:
+ .dw $ff05
+ .db "OCR1A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1A
+XT_OCR1A:
+ .dw PFA_DOVARIABLE
+PFA_OCR1A:
+ .dw 136
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register B Bytes
+VE_OCR1B:
+ .dw $ff05
+ .db "OCR1B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1B
+XT_OCR1B:
+ .dw PFA_DOVARIABLE
+PFA_OCR1B:
+ .dw 138
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Bytes
+VE_ICR1:
+ .dw $ff04
+ .db "ICR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1
+XT_ICR1:
+ .dw PFA_DOVARIABLE
+PFA_ICR1:
+ .dw 134
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Mask Register
+VE_TIMSK1:
+ .dw $ff06
+ .db "TIMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK1
+XT_TIMSK1:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK1:
+ .dw 111
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Flag register
+VE_TIFR1:
+ .dw $ff05
+ .db "TIFR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR1
+XT_TIFR1:
+ .dw PFA_DOVARIABLE
+PFA_TIFR1:
+ .dw 54
+
+.endif
+.if WANT_TIMER_COUNTER_2 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register
+VE_TCCR2A:
+ .dw $ff06
+ .db "TCCR2A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2A
+XT_TCCR2A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2A:
+ .dw 176
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2
+VE_TCNT2:
+ .dw $ff05
+ .db "TCNT2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT2
+XT_TCNT2:
+ .dw PFA_DOVARIABLE
+PFA_TCNT2:
+ .dw 178
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register
+VE_OCR2A:
+ .dw $ff05
+ .db "OCR2A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2A
+XT_OCR2A:
+ .dw PFA_DOVARIABLE
+PFA_OCR2A:
+ .dw 179
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Interrupt Mask register
+VE_TIMSK2:
+ .dw $ff06
+ .db "TIMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK2
+XT_TIMSK2:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK2:
+ .dw 112
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Interrupt Flag Register
+VE_TIFR2:
+ .dw $ff05
+ .db "TIFR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR2
+XT_TIFR2:
+ .dw PFA_DOVARIABLE
+PFA_TIFR2:
+ .dw 55
+; ( -- addr ) System Constant
+; R( -- )
+; Asynchronous Status Register
+VE_ASSR:
+ .dw $ff04
+ .db "ASSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ASSR
+XT_ASSR:
+ .dw PFA_DOVARIABLE
+PFA_ASSR:
+ .dw 182
+
+.endif
+.if WANT_WATCHDOG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCR:
+ .dw $ff05
+ .db "WDTCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCR
+XT_WDTCR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCR:
+ .dw 96
+
+.endif
+.if WANT_CPU == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw 95
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer
+VE_SP:
+ .dw $ff02
+ .db "SP"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SP
+XT_SP:
+ .dw PFA_DOVARIABLE
+PFA_SP:
+ .dw 93
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Calibration Value
+VE_OSCCAL:
+ .dw $ff06
+ .db "OSCCAL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSCCAL
+XT_OSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_OSCCAL:
+ .dw 102
+; ( -- addr ) System Constant
+; R( -- )
+; Clock Prescale Register
+VE_CLKPR:
+ .dw $ff05
+ .db "CLKPR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKPR
+XT_CLKPR:
+ .dw PFA_DOVARIABLE
+PFA_CLKPR:
+ .dw 97
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register
+VE_PRR:
+ .dw $ff03
+ .db "PRR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR
+XT_PRR:
+ .dw PFA_DOVARIABLE
+PFA_PRR:
+ .dw 100
+; ( -- addr ) System Constant
+; R( -- )
+; Sleep Mode Control Register
+VE_SMCR:
+ .dw $ff04
+ .db "SMCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SMCR
+XT_SMCR:
+ .dw PFA_DOVARIABLE
+PFA_SMCR:
+ .dw 83
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 2
+VE_GPIOR2:
+ .dw $ff06
+ .db "GPIOR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR2
+XT_GPIOR2:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR2:
+ .dw 75
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 1
+VE_GPIOR1:
+ .dw $ff06
+ .db "GPIOR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR1
+XT_GPIOR1:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR1:
+ .dw 74
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 0
+VE_GPIOR0:
+ .dw $ff06
+ .db "GPIOR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR0
+XT_GPIOR0:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR0:
+ .dw 62
+
+.endif
diff --git a/amforth-6.5/avr8/devices/atmega325p/device.py b/amforth-6.5/avr8/devices/atmega325p/device.py
new file mode 100644
index 0000000..1e1ca9c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega325p/device.py
@@ -0,0 +1,321 @@
+# Generated Automatically
+
+# Partname ATmega325P
+
+MCUREGS = {
+# Interrupt Vectors
+ 'INT0Addr' : '#2', # External Interrupt Request 0
+ 'PCINT0Addr' : '#4', # Pin Change Interrupt Request 0
+ 'PCINT1Addr' : '#6', # Pin Change Interrupt Request 1
+ 'TIMER2_COMPAddr' : '#8', # Timer/Counter2 Compare Match
+ 'TIMER2_OVFAddr' : '#10', # Timer/Counter2 Overflow
+ 'TIMER1_CAPTAddr' : '#12', # Timer/Counter1 Capture Event
+ 'TIMER1_COMPAAddr' : '#14', # Timer/Counter1 Compare Match A
+ 'TIMER1_COMPBAddr' : '#16', # Timer/Counter Compare Match B
+ 'TIMER1_OVFAddr' : '#18', # Timer/Counter1 Overflow
+ 'TIMER0_COMPAddr' : '#20', # Timer/Counter0 Compare Match
+ 'TIMER0_OVFAddr' : '#22', # Timer/Counter0 Overflow
+ 'SPI_STCAddr' : '#24', # SPI Serial Transfer Complete
+ 'USART0_RXAddr' : '#26', # USART0, Rx Complete
+ 'USART0_UDREAddr' : '#28', # USART0 Data register Empty
+ 'USART0_TXAddr' : '#30', # USART0, Tx Complete
+ 'USI_STARTAddr' : '#32', # USI Start Condition
+ 'USI_OVERFLOWAddr' : '#34', # USI Overflow
+ 'ANALOG_COMPAddr' : '#36', # Analog Comparator
+ 'ADCAddr' : '#38', # ADC Conversion Complete
+ 'EE_READYAddr' : '#40', # EEPROM Ready
+ 'SPM_READYAddr' : '#42', # Store Program Memory Read
+
+# Module AD_CONVERTER
+ 'ADMUX' : '$7c', # The ADC multiplexer Selection
+ 'ADMUX_REFS': '$c0', # Reference Selection Bits
+ 'ADMUX_ADLAR': '$20', # Left Adjust Result
+ 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
+ 'ADCSRA' : '$7a', # The ADC Control and Status reg
+ 'ADCSRA_ADEN': '$80', # ADC Enable
+ 'ADCSRA_ADSC': '$40', # ADC Start Conversion
+ 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
+ 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
+ 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
+ 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
+ 'ADC' : '$78', # ADC Data Register Bytes
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Sources
+ 'DIDR0' : '$7e', # Digital Input Disable Register
+ 'DIDR0_ADC7D': '$80', # ADC7 Digital input Disable
+ 'DIDR0_ADC6D': '$40', # ADC6 Digital input Disable
+ 'DIDR0_ADC5D': '$20', # ADC5 Digital input Disable
+ 'DIDR0_ADC4D': '$10', # ADC4 Digital input Disable
+ 'DIDR0_ADC3D': '$8', # ADC3 Digital input Disable
+ 'DIDR0_ADC2D': '$4', # ADC2 Digital input Disable
+ 'DIDR0_ADC1D': '$2', # ADC1 Digital input Disable
+ 'DIDR0_ADC0D': '$1', # ADC0 Digital input Disable
+
+# Module ANALOG_COMPARATOR
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
+ 'ACSR' : '$50', # Analog Comparator Control And
+ 'ACSR_ACD': '$80', # Analog Comparator Disable
+ 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
+ 'ACSR_ACO': '$20', # Analog Compare Output
+ 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
+ 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
+ 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
+ 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
+ 'DIDR1' : '$7f', # Digital Input Disable Register
+ 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
+ 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
+
+# Module USART0
+ 'UDR0' : '$c6', # USART I/O Data Register
+ 'UCSR0A' : '$c0', # USART Control and Status Regis
+ 'UCSR0A_RXC0': '$80', # USART Receive Complete
+ 'UCSR0A_TXC0': '$40', # USART Transmit Complete
+ 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
+ 'UCSR0A_FE0': '$10', # Framing Error
+ 'UCSR0A_DOR0': '$8', # Data OverRun
+ 'UCSR0A_UPE0': '$4', # USART Parity Error
+ 'UCSR0A_U2X0': '$2', # Double the USART Transmission
+ 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
+ 'UCSR0B' : '$c1', # USART Control and Status Regis
+ 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
+ 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
+ 'UCSR0B_UDRIE0': '$20', # USART Data Register Empty Inte
+ 'UCSR0B_RXEN0': '$10', # Receiver Enable
+ 'UCSR0B_TXEN0': '$8', # Transmitter Enable
+ 'UCSR0B_UCSZ02': '$4', # Character Size
+ 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
+ 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
+ 'UCSR0C' : '$c2', # USART Control and Status Regis
+ 'UCSR0C_UMSEL0': '$40', # USART Mode Select
+ 'UCSR0C_UPM0': '$30', # Parity Mode Bits
+ 'UCSR0C_USBS0': '$8', # Stop Bit Select
+ 'UCSR0C_UCSZ0': '$6', # Character Size
+ 'UCSR0C_UCPOL0': '$1', # Clock Polarity
+ 'UBRR0' : '$c4', # USART Baud Rate Register Byte
+
+# Module USI
+ 'USIDR' : '$ba', # USI Data Register
+ 'USISR' : '$b9', # USI Status Register
+ 'USISR_USISIF': '$80', # Start Condition Interrupt Flag
+ 'USISR_USIOIF': '$40', # Counter Overflow Interrupt Fla
+ 'USISR_USIPF': '$20', # Stop Condition Flag
+ 'USISR_USIDC': '$10', # Data Output Collision
+ 'USISR_USICNT': '$f', # USI Counter Value Bits
+ 'USICR' : '$b8', # USI Control Register
+ 'USICR_USISIE': '$80', # Start Condition Interrupt Enab
+ 'USICR_USIOIE': '$40', # Counter Overflow Interrupt Ena
+ 'USICR_USIWM': '$30', # USI Wire Mode Bits
+ 'USICR_USICS': '$c', # USI Clock Source Select Bits
+ 'USICR_USICLK': '$2', # Clock Strobe
+ 'USICR_USITC': '$1', # Toggle Clock Port Pin
+
+# Module SPI
+ 'SPCR' : '$4c', # SPI Control Register
+ 'SPCR_SPIE': '$80', # SPI Interrupt Enable
+ 'SPCR_SPE': '$40', # SPI Enable
+ 'SPCR_DORD': '$20', # Data Order
+ 'SPCR_MSTR': '$10', # Master/Slave Select
+ 'SPCR_CPOL': '$8', # Clock polarity
+ 'SPCR_CPHA': '$4', # Clock Phase
+ 'SPCR_SPR': '$3', # SPI Clock Rate Selects
+ 'SPSR' : '$4d', # SPI Status Register
+ 'SPSR_SPIF': '$80', # SPI Interrupt Flag
+ 'SPSR_WCOL': '$40', # Write Collision Flag
+ 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
+ 'SPDR' : '$4e', # SPI Data Register
+
+# Module BOOT_LOAD
+ 'SPMCSR' : '$57', # Store Program Memory Control R
+ 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
+ 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
+ 'SPMCSR_RWWSRE': '$10', # Read While Write section read
+ 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
+ 'SPMCSR_PGWRT': '$4', # Page Write
+ 'SPMCSR_PGERS': '$2', # Page Erase
+ 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
+
+# Module JTAG
+ 'OCDR' : '$51', # On-Chip Debug Related Register
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_JTD': '$80', # JTAG Interface Disable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+
+# Module EXTERNAL_INTERRUPT
+ 'EICRA' : '$69', # External Interrupt Control Reg
+ 'EICRA_ISC01': '$2', # External Interrupt Sense Contr
+ 'EICRA_ISC00': '$1', # External Interrupt Sense Contr
+ 'EIMSK' : '$3d', # External Interrupt Mask Regist
+ 'EIMSK_PCIE': '$f0', # Pin Change Interrupt Enables
+ 'EIMSK_INT0': '$1', # External Interrupt Request 0 E
+ 'EIFR' : '$3c', # External Interrupt Flag Regist
+ 'EIFR_PCIF': '$f0', # Pin Change Interrupt Flags
+ 'EIFR_INTF0': '$1', # External Interrupt Flag 0
+ 'PCMSK1' : '$6c', # Pin Change Mask Register 1
+ 'PCMSK0' : '$6b', # Pin Change Mask Register 0
+
+# Module EEPROM
+ 'EEAR' : '$41', # EEPROM Read/Write Access Byte
+ 'EEDR' : '$40', # EEPROM Data Register
+ 'EECR' : '$3f', # EEPROM Control Register
+ 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
+ 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
+ 'EECR_EEWE': '$2', # EEPROM Write Enable
+ 'EECR_EERE': '$1', # EEPROM Read Enable
+
+# Module PORTA
+ 'PORTA' : '$22', # Port A Data Register
+ 'DDRA' : '$21', # Port A Data Direction Register
+ 'PINA' : '$20', # Port A Input Pins
+
+# Module PORTB
+ 'PORTB' : '$25', # Port B Data Register
+ 'DDRB' : '$24', # Port B Data Direction Register
+ 'PINB' : '$23', # Port B Input Pins
+
+# Module PORTC
+ 'PORTC' : '$28', # Port C Data Register
+ 'DDRC' : '$27', # Port C Data Direction Register
+ 'PINC' : '$26', # Port C Input Pins
+
+# Module PORTD
+ 'PORTD' : '$2b', # Port D Data Register
+ 'DDRD' : '$2a', # Port D Data Direction Register
+ 'PIND' : '$29', # Port D Input Pins
+
+# Module PORTE
+ 'PORTE' : '$2e', # Data Register, Port E
+ 'DDRE' : '$2d', # Data Direction Register, Port
+ 'PINE' : '$2c', # Input Pins, Port E
+
+# Module PORTF
+ 'PORTF' : '$31', # Data Register, Port F
+ 'DDRF' : '$30', # Data Direction Register, Port
+ 'PINF' : '$2f', # Input Pins, Port F
+
+# Module PORTG
+ 'PORTG' : '$34', # Port G Data Register
+ 'DDRG' : '$33', # Port G Data Direction Register
+ 'PING' : '$32', # Port G Input Pins
+
+# Module TIMER_COUNTER_0
+ 'TCCR0A' : '$44', # Timer/Counter0 Control Registe
+ 'TCCR0A_FOC0A': '$80', # Force Output Compare
+ 'TCCR0A_WGM00': '$40', # Waveform Generation Mode 0
+ 'TCCR0A_COM0A': '$30', # Compare Match Output Modes
+ 'TCCR0A_WGM01': '$8', # Waveform Generation Mode 1
+ 'TCCR0A_CS0': '$7', # Clock Selects
+ 'TCNT0' : '$46', # Timer/Counter0
+ 'OCR0A' : '$47', # Timer/Counter0 Output Compare
+ 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
+ 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
+ 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
+ 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
+ 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
+ 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Control Register
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSR310': '$1', # Prescaler Reset Timer/Counter1
+
+# Module TIMER_COUNTER_1
+ 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
+ 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
+ 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
+ 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
+ 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
+ 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
+ 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
+ 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
+ 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
+ 'TCCR1C' : '$82', # Timer/Counter 1 Control Regist
+ 'TCCR1C_FOC1A': '$80', # Force Output Compare 1A
+ 'TCCR1C_FOC1B': '$40', # Force Output Compare 1B
+ 'TCNT1' : '$84', # Timer/Counter1 Bytes
+ 'OCR1A' : '$88', # Timer/Counter1 Output Compare
+ 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
+ 'ICR1' : '$86', # Timer/Counter1 Input Capture R
+ 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
+ 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
+ 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
+ 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
+ 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
+ 'TIFR1' : '$36', # Timer/Counter1 Interrupt Flag
+ 'TIFR1_ICF1': '$20', # Input Capture Flag 1
+ 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
+ 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
+ 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
+
+# Module TIMER_COUNTER_2
+ 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
+ 'TCCR2A_FOC2A': '$80', # Force Output Compare A
+ 'TCCR2A_WGM20': '$40', # Waveform Generation Mode
+ 'TCCR2A_COM2A': '$30', # Compare Output Mode bits
+ 'TCCR2A_WGM21': '$8', # Waveform Generation Mode
+ 'TCCR2A_CS2': '$7', # Clock Select bits
+ 'TCNT2' : '$b2', # Timer/Counter2
+ 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
+ 'TIMSK2' : '$70', # Timer/Counter2 Interrupt Mask
+ 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
+ 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
+ 'TIFR2' : '$37', # Timer/Counter2 Interrupt Flag
+ 'TIFR2_OCF2A': '$2', # Timer/Counter2 Output Compare
+ 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_PSR2': '$2', # Prescaler Reset Timer/Counter2
+ 'ASSR' : '$b6', # Asynchronous Status Register
+ 'ASSR_EXCLK': '$10', # Enable External Clock Interrup
+ 'ASSR_AS2': '$8', # AS2: Asynchronous Timer/Counte
+ 'ASSR_TCN2UB': '$4', # TCN2UB: Timer/Counter2 Update
+ 'ASSR_OCR2UB': '$2', # Output Compare Register2 Updat
+ 'ASSR_TCR2UB': '$1', # TCR2UB: Timer/Counter Control
+
+# Module WATCHDOG
+ 'WDTCR' : '$60', # Watchdog Timer Control Registe
+ 'WDTCR_WDCE': '$10', # Watchdog Change Enable
+ 'WDTCR_WDE': '$8', # Watch Dog Enable
+ 'WDTCR_WDP': '$7', # Watch Dog Timer Prescaler bits
+
+# Module CPU
+ 'SREG' : '$5f', # Status Register
+ 'SREG_I': '$80', # Global Interrupt Enable
+ 'SREG_T': '$40', # Bit Copy Storage
+ 'SREG_H': '$20', # Half Carry Flag
+ 'SREG_S': '$10', # Sign Bit
+ 'SREG_V': '$8', # Two's Complement Overflow Flag
+ 'SREG_N': '$4', # Negative Flag
+ 'SREG_Z': '$2', # Zero Flag
+ 'SREG_C': '$1', # Carry Flag
+ 'SP' : '$5d', # Stack Pointer
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_JTD': '$80', # JTAG Interface Disable
+ 'MCUCR_BODS': '$40', # BOD Sleep
+ 'MCUCR_BODSE': '$20', # BOD Sleep Enable
+ 'MCUCR_PUD': '$10', # Pull-up disable
+ 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
+ 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+ 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
+ 'MCUSR_BORF': '$4', # Brown-out Reset Flag
+ 'MCUSR_EXTRF': '$2', # External Reset Flag
+ 'MCUSR_PORF': '$1', # Power-on reset flag
+ 'OSCCAL' : '$66', # Oscillator Calibration Value
+ 'CLKPR' : '$61', # Clock Prescale Register
+ 'CLKPR_CLKPCE': '$80', # Clock Prescaler Change Enable
+ 'CLKPR_CLKPS': '$f', # Clock Prescaler Select Bits
+ 'PRR' : '$64', # Power Reduction Register
+ 'PRR_PRLCD': '$10', # Power Reduction LCD
+ 'PRR_PRTIM1': '$8', # Power Reduction Timer/Counter1
+ 'PRR_PRSPI': '$4', # Power Reduction Serial Periphe
+ 'PRR_PRUSART0': '$2', # Power Reduction USART
+ 'PRR_PRADC': '$1', # Power Reduction ADC
+ 'SMCR' : '$53', # Sleep Mode Control Register
+ 'SMCR_SM': '$e', # Sleep Mode Select bits
+ 'SMCR_SE': '$1', # Sleep Enable
+ 'GPIOR2' : '$4b', # General Purpose IO Register 2
+ 'GPIOR1' : '$4a', # General Purpose IO Register 1
+ 'GPIOR0' : '$3e', # General Purpose IO Register 0
+
+ '__amforth_dummy':'0'
+}
diff --git a/amforth-6.5/avr8/devices/atmega325p/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega325p/words/no-jtag.asm
new file mode 100644
index 0000000..352a4bb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega325p/words/no-jtag.asm
@@ -0,0 +1,14 @@
+; ( -- )
+; ( -- )
+; MCU
+; disable jtag at runtime
+VE_NOJTAG:
+ .dw $FF05
+ .db "-jtag",0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOJTAG
+XT_NOJTAG:
+ .dw PFA_NOJTAG
+PFA_NOJTAG:
+
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega325p/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega325p/words/no-wdt.asm
new file mode 100644
index 0000000..4a12261
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega325p/words/no-wdt.asm
@@ -0,0 +1,22 @@
+; ( -- )
+; MCU
+; disable watch dog timer at runtime
+VE_NOWDT:
+ .dw $ff04
+ .db "-wdt"
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOWDT
+XT_NOWDT:
+ .dw PFA_NOWDT
+PFA_NOWDT:
+
+; Reset WDT
+ wdr
+; Write logical one to WDTOE and WDE
+ in_ temp1, WDTCR
+ ori temp1, (1<<WDTOE)|(1<<WDE)
+ out WDTCR, temp1
+; Turn off WDT
+ ldi temp1, (0<<WDE)
+ out_ WDTCR, temp1
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega325p/words/sleep.asm b/amforth-6.5/avr8/devices/atmega325p/words/sleep.asm
new file mode 100644
index 0000000..256249c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega325p/words/sleep.asm
@@ -0,0 +1,19 @@
+; ( mode -- )
+; MCU
+; put the controller into the specified sleep mode
+VE_SLEEP:
+ .dw $ff05
+ .db "sleep", 0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_SLEEP
+XT_SLEEP:
+ .dw PFA_SLEEP
+PFA_SLEEP:
+ andi tosl, 7 ; leave only legal mode bits
+ lsl tosl ; move to correct location (bits 3-1)
+ ori tosl, 1 ; set the SE bit
+ out_ SMCR, tosl ; set the sleep config
+ sleep ; nighty-night
+ out_ SMCR, zerol ; 0 protects against accidental sleeps
+ loadtos ; pop argument from stack
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega325pa/atmega325pa.frt b/amforth-6.5/avr8/devices/atmega325pa/atmega325pa.frt
new file mode 100644
index 0000000..a50b001
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega325pa/atmega325pa.frt
@@ -0,0 +1,279 @@
+\ Partname: ATmega325PA
+\ generated automatically
+
+\ AD_CONVERTER
+&124 constant ADMUX \ The ADC multiplexer Selection Register
+ $C0 constant ADMUX_REFS \ Reference Selection Bits
+ $20 constant ADMUX_ADLAR \ Left Adjust Result
+ $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
+&122 constant ADCSRA \ The ADC Control and Status register
+ $80 constant ADCSRA_ADEN \ ADC Enable
+ $40 constant ADCSRA_ADSC \ ADC Start Conversion
+ $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
+ $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
+ $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
+ $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
+&120 constant ADC \ ADC Data Register Bytes
+&123 constant ADCSRB \ ADC Control and Status Register B
+ $07 constant ADCSRB_ADTS \ ADC Auto Trigger Sources
+&126 constant DIDR0 \ Digital Input Disable Register 0
+ $80 constant DIDR0_ADC7D \ ADC7 Digital input Disable
+ $40 constant DIDR0_ADC6D \ ADC6 Digital input Disable
+ $20 constant DIDR0_ADC5D \ ADC5 Digital input Disable
+ $10 constant DIDR0_ADC4D \ ADC4 Digital input Disable
+ $08 constant DIDR0_ADC3D \ ADC3 Digital input Disable
+ $04 constant DIDR0_ADC2D \ ADC2 Digital input Disable
+ $02 constant DIDR0_ADC1D \ ADC1 Digital input Disable
+ $01 constant DIDR0_ADC0D \ ADC0 Digital input Disable
+\ ANALOG_COMPARATOR
+&80 constant ACSR \ Analog Comparator Control And Status Register
+ $80 constant ACSR_ACD \ Analog Comparator Disable
+ $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
+ $20 constant ACSR_ACO \ Analog Compare Output
+ $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
+ $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
+ $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
+ $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
+&127 constant DIDR1 \ Digital Input Disable Register 1
+ $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
+ $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
+\ USART0
+&198 constant UDR0 \ USART I/O Data Register
+&192 constant UCSR0A \ USART Control and Status Register A
+ $80 constant UCSR0A_RXC0 \ USART Receive Complete
+ $40 constant UCSR0A_TXC0 \ USART Transmit Complete
+ $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
+ $10 constant UCSR0A_FE0 \ Framing Error
+ $08 constant UCSR0A_DOR0 \ Data OverRun
+ $04 constant UCSR0A_UPE0 \ USART Parity Error
+ $02 constant UCSR0A_U2X0 \ Double the USART Transmission Speed
+ $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
+&193 constant UCSR0B \ USART Control and Status Register B
+ $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
+ $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
+ $20 constant UCSR0B_UDRIE0 \ USART Data Register Empty Interrupt Enable
+ $10 constant UCSR0B_RXEN0 \ Receiver Enable
+ $08 constant UCSR0B_TXEN0 \ Transmitter Enable
+ $04 constant UCSR0B_UCSZ02 \ Character Size
+ $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
+ $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
+&194 constant UCSR0C \ USART Control and Status Register C
+ $40 constant UCSR0C_UMSEL0 \ USART Mode Select
+ $30 constant UCSR0C_UPM0 \ Parity Mode Bits
+ $08 constant UCSR0C_USBS0 \ Stop Bit Select
+ $06 constant UCSR0C_UCSZ0 \ Character Size
+ $01 constant UCSR0C_UCPOL0 \ Clock Polarity
+&196 constant UBRR0 \ USART Baud Rate Register Bytes
+\ USI
+&186 constant USIDR \ USI Data Register
+&185 constant USISR \ USI Status Register
+ $80 constant USISR_USISIF \ Start Condition Interrupt Flag
+ $40 constant USISR_USIOIF \ Counter Overflow Interrupt Flag
+ $20 constant USISR_USIPF \ Stop Condition Flag
+ $10 constant USISR_USIDC \ Data Output Collision
+ $0F constant USISR_USICNT \ USI Counter Value Bits
+&184 constant USICR \ USI Control Register
+ $80 constant USICR_USISIE \ Start Condition Interrupt Enable
+ $40 constant USICR_USIOIE \ Counter Overflow Interrupt Enable
+ $30 constant USICR_USIWM \ USI Wire Mode Bits
+ $0C constant USICR_USICS \ USI Clock Source Select Bits
+ $02 constant USICR_USICLK \ Clock Strobe
+ $01 constant USICR_USITC \ Toggle Clock Port Pin
+\ SPI
+&76 constant SPCR \ SPI Control Register
+ $80 constant SPCR_SPIE \ SPI Interrupt Enable
+ $40 constant SPCR_SPE \ SPI Enable
+ $20 constant SPCR_DORD \ Data Order
+ $10 constant SPCR_MSTR \ Master/Slave Select
+ $08 constant SPCR_CPOL \ Clock polarity
+ $04 constant SPCR_CPHA \ Clock Phase
+ $03 constant SPCR_SPR \ SPI Clock Rate Selects
+&77 constant SPSR \ SPI Status Register
+ $80 constant SPSR_SPIF \ SPI Interrupt Flag
+ $40 constant SPSR_WCOL \ Write Collision Flag
+ $01 constant SPSR_SPI2X \ Double SPI Speed Bit
+&78 constant SPDR \ SPI Data Register
+\ BOOT_LOAD
+&87 constant SPMCSR \ Store Program Memory Control Register
+ $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
+ $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
+ $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
+ $04 constant SPMCSR_PGWRT \ Page Write
+ $02 constant SPMCSR_PGERS \ Page Erase
+ $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
+\ JTAG
+&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
+&85 constant MCUCR \ MCU Control Register
+ $80 constant MCUCR_JTD \ JTAG Interface Disable
+&84 constant MCUSR \ MCU Status Register
+ $10 constant MCUSR_JTRF \ JTAG Reset Flag
+\ EXTERNAL_INTERRUPT
+&105 constant EICRA \ External Interrupt Control Register A
+ $02 constant EICRA_ISC01 \ External Interrupt Sense Control 0 Bit 1
+ $01 constant EICRA_ISC00 \ External Interrupt Sense Control 0 Bit 0
+&61 constant EIMSK \ External Interrupt Mask Register
+ $F0 constant EIMSK_PCIE \ Pin Change Interrupt Enables
+ $01 constant EIMSK_INT0 \ External Interrupt Request 0 Enable
+&60 constant EIFR \ External Interrupt Flag Register
+ $F0 constant EIFR_PCIF \ Pin Change Interrupt Flags
+ $01 constant EIFR_INTF0 \ External Interrupt Flag 0
+&108 constant PCMSK1 \ Pin Change Mask Register 1
+&107 constant PCMSK0 \ Pin Change Mask Register 0
+\ EEPROM
+&65 constant EEAR \ EEPROM Read/Write Access Bytes
+&64 constant EEDR \ EEPROM Data Register
+&63 constant EECR \ EEPROM Control Register
+ $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
+ $04 constant EECR_EEMWE \ EEPROM Master Write Enable
+ $02 constant EECR_EEWE \ EEPROM Write Enable
+ $01 constant EECR_EERE \ EEPROM Read Enable
+\ PORTA
+&34 constant PORTA \ Port A Data Register
+&33 constant DDRA \ Port A Data Direction Register
+&32 constant PINA \ Port A Input Pins
+\ PORTB
+&37 constant PORTB \ Port B Data Register
+&36 constant DDRB \ Port B Data Direction Register
+&35 constant PINB \ Port B Input Pins
+\ PORTC
+&40 constant PORTC \ Port C Data Register
+&39 constant DDRC \ Port C Data Direction Register
+&38 constant PINC \ Port C Input Pins
+\ PORTD
+&43 constant PORTD \ Port D Data Register
+&42 constant DDRD \ Port D Data Direction Register
+&41 constant PIND \ Port D Input Pins
+\ PORTE
+&46 constant PORTE \ Data Register, Port E
+&45 constant DDRE \ Data Direction Register, Port E
+&44 constant PINE \ Input Pins, Port E
+\ PORTF
+&49 constant PORTF \ Data Register, Port F
+&48 constant DDRF \ Data Direction Register, Port F
+&47 constant PINF \ Input Pins, Port F
+\ PORTG
+&52 constant PORTG \ Port G Data Register
+&51 constant DDRG \ Port G Data Direction Register
+&50 constant PING \ Port G Input Pins
+\ TIMER_COUNTER_0
+&68 constant TCCR0A \ Timer/Counter0 Control Register
+ $80 constant TCCR0A_FOC0A \ Force Output Compare
+ $40 constant TCCR0A_WGM00 \ Waveform Generation Mode 0
+ $30 constant TCCR0A_COM0A \ Compare Match Output Modes
+ $08 constant TCCR0A_WGM01 \ Waveform Generation Mode 1
+ $07 constant TCCR0A_CS0 \ Clock Selects
+&70 constant TCNT0 \ Timer/Counter0
+&71 constant OCR0A \ Timer/Counter0 Output Compare Register
+&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
+ $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match Interrupt Enable
+ $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
+&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
+ $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0
+ $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
+&67 constant GTCCR \ General Timer/Control Register
+ $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
+ $01 constant GTCCR_PSR310 \ Prescaler Reset Timer/Counter1 and Timer/Counter0
+\ TIMER_COUNTER_1
+&128 constant TCCR1A \ Timer/Counter1 Control Register A
+ $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
+ $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
+ $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
+&129 constant TCCR1B \ Timer/Counter1 Control Register B
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
+ $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
+&130 constant TCCR1C \ Timer/Counter 1 Control Register C
+ $80 constant TCCR1C_FOC1A \ Force Output Compare 1A
+ $40 constant TCCR1C_FOC1B \ Force Output Compare 1B
+&132 constant TCNT1 \ Timer/Counter1 Bytes
+&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
+&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
+&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
+&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
+ $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
+ $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
+ $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
+ $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
+&54 constant TIFR1 \ Timer/Counter1 Interrupt Flag register
+ $20 constant TIFR1_ICF1 \ Input Capture Flag 1
+ $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
+ $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
+ $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
+\ TIMER_COUNTER_2
+&176 constant TCCR2A \ Timer/Counter2 Control Register
+ $80 constant TCCR2A_FOC2A \ Force Output Compare A
+ $40 constant TCCR2A_WGM20 \ Waveform Generation Mode
+ $30 constant TCCR2A_COM2A \ Compare Output Mode bits
+ $08 constant TCCR2A_WGM21 \ Waveform Generation Mode
+ $07 constant TCCR2A_CS2 \ Clock Select bits
+&178 constant TCNT2 \ Timer/Counter2
+&179 constant OCR2A \ Timer/Counter2 Output Compare Register
+&112 constant TIMSK2 \ Timer/Counter2 Interrupt Mask register
+ $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match Interrupt Enable
+ $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
+&55 constant TIFR2 \ Timer/Counter2 Interrupt Flag Register
+ $02 constant TIFR2_OCF2A \ Timer/Counter2 Output Compare Flag 2
+ $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
+&182 constant ASSR \ Asynchronous Status Register
+ $10 constant ASSR_EXCLK \ Enable External Clock Interrupt
+ $08 constant ASSR_AS2 \ AS2: Asynchronous Timer/Counter2
+ $04 constant ASSR_TCN2UB \ TCN2UB: Timer/Counter2 Update Busy
+ $02 constant ASSR_OCR2UB \ Output Compare Register2 Update Busy
+ $01 constant ASSR_TCR2UB \ TCR2UB: Timer/Counter Control Register2 Update Busy
+\ WATCHDOG
+&96 constant WDTCR \ Watchdog Timer Control Register
+ $10 constant WDTCR_WDCE \ Watchdog Change Enable
+ $08 constant WDTCR_WDE \ Watch Dog Enable
+ $07 constant WDTCR_WDP \ Watch Dog Timer Prescaler bits
+\ CPU
+&95 constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ $08 constant SREG_V \ Two's Complement Overflow Flag
+ $04 constant SREG_N \ Negative Flag
+ $02 constant SREG_Z \ Zero Flag
+ $01 constant SREG_C \ Carry Flag
+&93 constant SP \ Stack Pointer
+&102 constant OSCCAL \ Oscillator Calibration Value
+&97 constant CLKPR \ Clock Prescale Register
+ $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable
+ $0F constant CLKPR_CLKPS \ Clock Prescaler Select Bits
+&100 constant PRR \ Power Reduction Register
+ $10 constant PRR_PRLCD \ Power Reduction LCD
+ $08 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
+ $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
+ $02 constant PRR_PRUSART0 \ Power Reduction USART
+ $01 constant PRR_PRADC \ Power Reduction ADC
+&83 constant SMCR \ Sleep Mode Control Register
+ $0E constant SMCR_SM \ Sleep Mode Select bits
+ $01 constant SMCR_SE \ Sleep Enable
+&75 constant GPIOR2 \ General Purpose IO Register 2
+&74 constant GPIOR1 \ General Purpose IO Register 1
+&62 constant GPIOR0 \ General Purpose IO Register 0
+
+\ Interrupts
+&2 constant INT0Addr \ External Interrupt Request 0
+&4 constant PCINT0Addr \ Pin Change Interrupt Request 0
+&6 constant PCINT1Addr \ Pin Change Interrupt Request 1
+&8 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
+&10 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
+&12 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+&14 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
+&16 constant TIMER1_COMPBAddr \ Timer/Counter Compare Match B
+&18 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+&20 constant TIMER0_COMPAddr \ Timer/Counter0 Compare Match
+&22 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
+&24 constant SPI__STCAddr \ SPI Serial Transfer Complete
+&26 constant USART0__RXAddr \ USART0, Rx Complete
+&28 constant USART0__UDREAddr \ USART0 Data register Empty
+&30 constant USART0__TXAddr \ USART0, Tx Complete
+&32 constant USI_STARTAddr \ USI Start Condition
+&34 constant USI_OVERFLOWAddr \ USI Overflow
+&36 constant ANALOG_COMPAddr \ Analog Comparator
+&38 constant ADCAddr \ ADC Conversion Complete
+&40 constant EE_READYAddr \ EEPROM Ready
+&42 constant SPM_READYAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/atmega325pa/device.asm b/amforth-6.5/avr8/devices/atmega325pa/device.asm
new file mode 100644
index 0000000..9a3a3ff
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega325pa/device.asm
@@ -0,0 +1,106 @@
+; Partname: ATmega325PA
+; generated automatically, do not edit
+
+.nolist
+ .include "m325PAdef.inc"
+.list
+
+.equ ramstart = 256
+.equ CELLSIZE = 2
+.macro readflashcell
+ lsl zl
+ rol zh
+ lpm @0, Z+
+ lpm @1, Z+
+.endmacro
+.macro writeflashcell
+ lsl zl
+ rol zh
+.endmacro
+.set WANT_AD_CONVERTER = 0
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_USART0 = 0
+.set WANT_USI = 0
+.set WANT_SPI = 0
+.set WANT_BOOT_LOAD = 0
+.set WANT_JTAG = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_EEPROM = 0
+.set WANT_PORTA = 0
+.set WANT_PORTB = 0
+.set WANT_PORTC = 0
+.set WANT_PORTD = 0
+.set WANT_PORTE = 0
+.set WANT_PORTF = 0
+.set WANT_PORTG = 0
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_TIMER_COUNTER_2 = 0
+.set WANT_WATCHDOG = 0
+.set WANT_CPU = 0
+.equ intvecsize = 2 ; please verify; flash size: 32768 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.org 2
+ rcall isr ; External Interrupt Request 0
+.org 4
+ rcall isr ; Pin Change Interrupt Request 0
+.org 6
+ rcall isr ; Pin Change Interrupt Request 1
+.org 8
+ rcall isr ; Timer/Counter2 Compare Match
+.org 10
+ rcall isr ; Timer/Counter2 Overflow
+.org 12
+ rcall isr ; Timer/Counter1 Capture Event
+.org 14
+ rcall isr ; Timer/Counter1 Compare Match A
+.org 16
+ rcall isr ; Timer/Counter Compare Match B
+.org 18
+ rcall isr ; Timer/Counter1 Overflow
+.org 20
+ rcall isr ; Timer/Counter0 Compare Match
+.org 22
+ rcall isr ; Timer/Counter0 Overflow
+.org 24
+ rcall isr ; SPI Serial Transfer Complete
+.org 26
+ rcall isr ; USART0, Rx Complete
+.org 28
+ rcall isr ; USART0 Data register Empty
+.org 30
+ rcall isr ; USART0, Tx Complete
+.org 32
+ rcall isr ; USI Start Condition
+.org 34
+ rcall isr ; USI Overflow
+.org 36
+ rcall isr ; Analog Comparator
+.org 38
+ rcall isr ; ADC Conversion Complete
+.org 40
+ rcall isr ; EEPROM Ready
+.org 42
+ rcall isr ; Store Program Memory Read
+.equ INTVECTORS = 22
+.nooverlap
+
+; compatability layer (maybe empty)
+.equ EEPE = EEWE
+.equ EEMPE = EEMWE
+
+; controller data area, environment query mcu-info
+mcu_info:
+mcu_ramsize:
+ .dw 2048
+mcu_eepromsize:
+ .dw 1024
+mcu_maxdp:
+ .dw 28672
+mcu_numints:
+ .dw 22
+mcu_name:
+ .dw 11
+ .db "ATmega325PA",0
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega325pa/device.inc b/amforth-6.5/avr8/devices/atmega325pa/device.inc
new file mode 100644
index 0000000..c699c12
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega325pa/device.inc
@@ -0,0 +1,1050 @@
+; Partname: ATmega325PA
+; generated automatically, no not edit
+
+.if WANT_AD_CONVERTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC multiplexer Selection Register
+VE_ADMUX:
+ .dw $ff05
+ .db "ADMUX",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADMUX
+XT_ADMUX:
+ .dw PFA_DOVARIABLE
+PFA_ADMUX:
+ .dw 124
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register
+VE_ADCSRA:
+ .dw $ff06
+ .db "ADCSRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRA
+XT_ADCSRA:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRA:
+ .dw 122
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register Bytes
+VE_ADC:
+ .dw $ff03
+ .db "ADC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADC
+XT_ADC:
+ .dw PFA_DOVARIABLE
+PFA_ADC:
+ .dw 120
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Control and Status Register B
+VE_ADCSRB:
+ .dw $ff06
+ .db "ADCSRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRB
+XT_ADCSRB:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRB:
+ .dw 123
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 0
+VE_DIDR0:
+ .dw $ff05
+ .db "DIDR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR0
+XT_DIDR0:
+ .dw PFA_DOVARIABLE
+PFA_DIDR0:
+ .dw 126
+
+.endif
+.if WANT_ANALOG_COMPARATOR == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Control And Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw 80
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 1
+VE_DIDR1:
+ .dw $ff05
+ .db "DIDR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR1
+XT_DIDR1:
+ .dw PFA_DOVARIABLE
+PFA_DIDR1:
+ .dw 127
+
+.endif
+.if WANT_USART0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR0:
+ .dw $ff04
+ .db "UDR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR0
+XT_UDR0:
+ .dw PFA_DOVARIABLE
+PFA_UDR0:
+ .dw 198
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR0A:
+ .dw $ff06
+ .db "UCSR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0A
+XT_UCSR0A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0A:
+ .dw 192
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR0B:
+ .dw $ff06
+ .db "UCSR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0B
+XT_UCSR0B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0B:
+ .dw 193
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR0C:
+ .dw $ff06
+ .db "UCSR0C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0C
+XT_UCSR0C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0C:
+ .dw 194
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Bytes
+VE_UBRR0:
+ .dw $ff05
+ .db "UBRR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR0
+XT_UBRR0:
+ .dw PFA_DOVARIABLE
+PFA_UBRR0:
+ .dw 196
+
+.endif
+.if WANT_USI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USI Data Register
+VE_USIDR:
+ .dw $ff05
+ .db "USIDR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USIDR
+XT_USIDR:
+ .dw PFA_DOVARIABLE
+PFA_USIDR:
+ .dw 186
+; ( -- addr ) System Constant
+; R( -- )
+; USI Status Register
+VE_USISR:
+ .dw $ff05
+ .db "USISR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USISR
+XT_USISR:
+ .dw PFA_DOVARIABLE
+PFA_USISR:
+ .dw 185
+; ( -- addr ) System Constant
+; R( -- )
+; USI Control Register
+VE_USICR:
+ .dw $ff05
+ .db "USICR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USICR
+XT_USICR:
+ .dw PFA_DOVARIABLE
+PFA_USICR:
+ .dw 184
+
+.endif
+.if WANT_SPI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR:
+ .dw $ff04
+ .db "SPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR
+XT_SPCR:
+ .dw PFA_DOVARIABLE
+PFA_SPCR:
+ .dw 76
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR:
+ .dw $ff04
+ .db "SPSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR
+XT_SPSR:
+ .dw PFA_DOVARIABLE
+PFA_SPSR:
+ .dw 77
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR:
+ .dw $ff04
+ .db "SPDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR
+XT_SPDR:
+ .dw PFA_DOVARIABLE
+PFA_SPDR:
+ .dw 78
+
+.endif
+.if WANT_BOOT_LOAD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control Register
+VE_SPMCSR:
+ .dw $ff06
+ .db "SPMCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCSR
+XT_SPMCSR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCSR:
+ .dw 87
+
+.endif
+.if WANT_JTAG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; On-Chip Debug Related Register in I/O Memory
+VE_OCDR:
+ .dw $ff04
+ .db "OCDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCDR
+XT_OCDR:
+ .dw PFA_DOVARIABLE
+PFA_OCDR:
+ .dw 81
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw 85
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Status Register
+VE_MCUSR:
+ .dw $ff05
+ .db "MCUSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUSR
+XT_MCUSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUSR:
+ .dw 84
+
+.endif
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register A
+VE_EICRA:
+ .dw $ff05
+ .db "EICRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRA
+XT_EICRA:
+ .dw PFA_DOVARIABLE
+PFA_EICRA:
+ .dw 105
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Mask Register
+VE_EIMSK:
+ .dw $ff05
+ .db "EIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIMSK
+XT_EIMSK:
+ .dw PFA_DOVARIABLE
+PFA_EIMSK:
+ .dw 61
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Flag Register
+VE_EIFR:
+ .dw $ff04
+ .db "EIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIFR
+XT_EIFR:
+ .dw PFA_DOVARIABLE
+PFA_EIFR:
+ .dw 60
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 1
+VE_PCMSK1:
+ .dw $ff06
+ .db "PCMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK1
+XT_PCMSK1:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK1:
+ .dw 108
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 0
+VE_PCMSK0:
+ .dw $ff06
+ .db "PCMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK0
+XT_PCMSK0:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK0:
+ .dw 107
+
+.endif
+.if WANT_EEPROM == 1
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Read/Write Access Bytes
+VE_EEAR:
+ .dw $ff04
+ .db "EEAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEAR
+XT_EEAR:
+ .dw PFA_DOVARIABLE
+PFA_EEAR:
+ .dw 65
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw 64
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw 63
+
+.endif
+.if WANT_PORTA == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Register
+VE_PORTA:
+ .dw $ff05
+ .db "PORTA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTA
+XT_PORTA:
+ .dw PFA_DOVARIABLE
+PFA_PORTA:
+ .dw 34
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Direction Register
+VE_DDRA:
+ .dw $ff04
+ .db "DDRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRA
+XT_DDRA:
+ .dw PFA_DOVARIABLE
+PFA_DDRA:
+ .dw 33
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Input Pins
+VE_PINA:
+ .dw $ff04
+ .db "PINA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINA
+XT_PINA:
+ .dw PFA_DOVARIABLE
+PFA_PINA:
+ .dw 32
+
+.endif
+.if WANT_PORTB == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw 37
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw 36
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw 35
+
+.endif
+.if WANT_PORTC == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Register
+VE_PORTC:
+ .dw $ff05
+ .db "PORTC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTC
+XT_PORTC:
+ .dw PFA_DOVARIABLE
+PFA_PORTC:
+ .dw 40
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Direction Register
+VE_DDRC:
+ .dw $ff04
+ .db "DDRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRC
+XT_DDRC:
+ .dw PFA_DOVARIABLE
+PFA_DDRC:
+ .dw 39
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Input Pins
+VE_PINC:
+ .dw $ff04
+ .db "PINC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINC
+XT_PINC:
+ .dw PFA_DOVARIABLE
+PFA_PINC:
+ .dw 38
+
+.endif
+.if WANT_PORTD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw 43
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw 42
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw 41
+
+.endif
+.if WANT_PORTE == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port E
+VE_PORTE:
+ .dw $ff05
+ .db "PORTE",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTE
+XT_PORTE:
+ .dw PFA_DOVARIABLE
+PFA_PORTE:
+ .dw 46
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port E
+VE_DDRE:
+ .dw $ff04
+ .db "DDRE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRE
+XT_DDRE:
+ .dw PFA_DOVARIABLE
+PFA_DDRE:
+ .dw 45
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port E
+VE_PINE:
+ .dw $ff04
+ .db "PINE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINE
+XT_PINE:
+ .dw PFA_DOVARIABLE
+PFA_PINE:
+ .dw 44
+
+.endif
+.if WANT_PORTF == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port F
+VE_PORTF:
+ .dw $ff05
+ .db "PORTF",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTF
+XT_PORTF:
+ .dw PFA_DOVARIABLE
+PFA_PORTF:
+ .dw 49
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port F
+VE_DDRF:
+ .dw $ff04
+ .db "DDRF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRF
+XT_DDRF:
+ .dw PFA_DOVARIABLE
+PFA_DDRF:
+ .dw 48
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port F
+VE_PINF:
+ .dw $ff04
+ .db "PINF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINF
+XT_PINF:
+ .dw PFA_DOVARIABLE
+PFA_PINF:
+ .dw 47
+
+.endif
+.if WANT_PORTG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Data Register
+VE_PORTG:
+ .dw $ff05
+ .db "PORTG",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTG
+XT_PORTG:
+ .dw PFA_DOVARIABLE
+PFA_PORTG:
+ .dw 52
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Data Direction Register
+VE_DDRG:
+ .dw $ff04
+ .db "DDRG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRG
+XT_DDRG:
+ .dw PFA_DOVARIABLE
+PFA_DDRG:
+ .dw 51
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Input Pins
+VE_PING:
+ .dw $ff04
+ .db "PING"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PING
+XT_PING:
+ .dw PFA_DOVARIABLE
+PFA_PING:
+ .dw 50
+
+.endif
+.if WANT_TIMER_COUNTER_0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Control Register
+VE_TCCR0A:
+ .dw $ff06
+ .db "TCCR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0A
+XT_TCCR0A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0A:
+ .dw 68
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw 70
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0A:
+ .dw $ff05
+ .db "OCR0A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0A
+XT_OCR0A:
+ .dw PFA_DOVARIABLE
+PFA_OCR0A:
+ .dw 71
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Mask Register
+VE_TIMSK0:
+ .dw $ff06
+ .db "TIMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK0
+XT_TIMSK0:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK0:
+ .dw 110
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Flag register
+VE_TIFR0:
+ .dw $ff05
+ .db "TIFR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR0
+XT_TIFR0:
+ .dw PFA_DOVARIABLE
+PFA_TIFR0:
+ .dw 53
+; ( -- addr ) System Constant
+; R( -- )
+; General Timer/Control Register
+VE_GTCCR:
+ .dw $ff05
+ .db "GTCCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GTCCR
+XT_GTCCR:
+ .dw PFA_DOVARIABLE
+PFA_GTCCR:
+ .dw 67
+
+.endif
+.if WANT_TIMER_COUNTER_1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw 128
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw 129
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter 1 Control Register C
+VE_TCCR1C:
+ .dw $ff06
+ .db "TCCR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1C
+XT_TCCR1C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1C:
+ .dw 130
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Bytes
+VE_TCNT1:
+ .dw $ff05
+ .db "TCNT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1
+XT_TCNT1:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1:
+ .dw 132
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register A Bytes
+VE_OCR1A:
+ .dw $ff05
+ .db "OCR1A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1A
+XT_OCR1A:
+ .dw PFA_DOVARIABLE
+PFA_OCR1A:
+ .dw 136
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register B Bytes
+VE_OCR1B:
+ .dw $ff05
+ .db "OCR1B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1B
+XT_OCR1B:
+ .dw PFA_DOVARIABLE
+PFA_OCR1B:
+ .dw 138
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Bytes
+VE_ICR1:
+ .dw $ff04
+ .db "ICR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1
+XT_ICR1:
+ .dw PFA_DOVARIABLE
+PFA_ICR1:
+ .dw 134
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Mask Register
+VE_TIMSK1:
+ .dw $ff06
+ .db "TIMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK1
+XT_TIMSK1:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK1:
+ .dw 111
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Flag register
+VE_TIFR1:
+ .dw $ff05
+ .db "TIFR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR1
+XT_TIFR1:
+ .dw PFA_DOVARIABLE
+PFA_TIFR1:
+ .dw 54
+
+.endif
+.if WANT_TIMER_COUNTER_2 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register
+VE_TCCR2A:
+ .dw $ff06
+ .db "TCCR2A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2A
+XT_TCCR2A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2A:
+ .dw 176
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2
+VE_TCNT2:
+ .dw $ff05
+ .db "TCNT2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT2
+XT_TCNT2:
+ .dw PFA_DOVARIABLE
+PFA_TCNT2:
+ .dw 178
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register
+VE_OCR2A:
+ .dw $ff05
+ .db "OCR2A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2A
+XT_OCR2A:
+ .dw PFA_DOVARIABLE
+PFA_OCR2A:
+ .dw 179
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Interrupt Mask register
+VE_TIMSK2:
+ .dw $ff06
+ .db "TIMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK2
+XT_TIMSK2:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK2:
+ .dw 112
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Interrupt Flag Register
+VE_TIFR2:
+ .dw $ff05
+ .db "TIFR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR2
+XT_TIFR2:
+ .dw PFA_DOVARIABLE
+PFA_TIFR2:
+ .dw 55
+; ( -- addr ) System Constant
+; R( -- )
+; Asynchronous Status Register
+VE_ASSR:
+ .dw $ff04
+ .db "ASSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ASSR
+XT_ASSR:
+ .dw PFA_DOVARIABLE
+PFA_ASSR:
+ .dw 182
+
+.endif
+.if WANT_WATCHDOG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCR:
+ .dw $ff05
+ .db "WDTCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCR
+XT_WDTCR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCR:
+ .dw 96
+
+.endif
+.if WANT_CPU == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw 95
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer
+VE_SP:
+ .dw $ff02
+ .db "SP"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SP
+XT_SP:
+ .dw PFA_DOVARIABLE
+PFA_SP:
+ .dw 93
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Calibration Value
+VE_OSCCAL:
+ .dw $ff06
+ .db "OSCCAL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSCCAL
+XT_OSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_OSCCAL:
+ .dw 102
+; ( -- addr ) System Constant
+; R( -- )
+; Clock Prescale Register
+VE_CLKPR:
+ .dw $ff05
+ .db "CLKPR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKPR
+XT_CLKPR:
+ .dw PFA_DOVARIABLE
+PFA_CLKPR:
+ .dw 97
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register
+VE_PRR:
+ .dw $ff03
+ .db "PRR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR
+XT_PRR:
+ .dw PFA_DOVARIABLE
+PFA_PRR:
+ .dw 100
+; ( -- addr ) System Constant
+; R( -- )
+; Sleep Mode Control Register
+VE_SMCR:
+ .dw $ff04
+ .db "SMCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SMCR
+XT_SMCR:
+ .dw PFA_DOVARIABLE
+PFA_SMCR:
+ .dw 83
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 2
+VE_GPIOR2:
+ .dw $ff06
+ .db "GPIOR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR2
+XT_GPIOR2:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR2:
+ .dw 75
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 1
+VE_GPIOR1:
+ .dw $ff06
+ .db "GPIOR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR1
+XT_GPIOR1:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR1:
+ .dw 74
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 0
+VE_GPIOR0:
+ .dw $ff06
+ .db "GPIOR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR0
+XT_GPIOR0:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR0:
+ .dw 62
+
+.endif
diff --git a/amforth-6.5/avr8/devices/atmega325pa/device.py b/amforth-6.5/avr8/devices/atmega325pa/device.py
new file mode 100644
index 0000000..43db5ea
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega325pa/device.py
@@ -0,0 +1,321 @@
+# Generated Automatically
+
+# Partname ATmega325PA
+
+MCUREGS = {
+# Interrupt Vectors
+ 'INT0Addr' : '#2', # External Interrupt Request 0
+ 'PCINT0Addr' : '#4', # Pin Change Interrupt Request 0
+ 'PCINT1Addr' : '#6', # Pin Change Interrupt Request 1
+ 'TIMER2_COMPAddr' : '#8', # Timer/Counter2 Compare Match
+ 'TIMER2_OVFAddr' : '#10', # Timer/Counter2 Overflow
+ 'TIMER1_CAPTAddr' : '#12', # Timer/Counter1 Capture Event
+ 'TIMER1_COMPAAddr' : '#14', # Timer/Counter1 Compare Match A
+ 'TIMER1_COMPBAddr' : '#16', # Timer/Counter Compare Match B
+ 'TIMER1_OVFAddr' : '#18', # Timer/Counter1 Overflow
+ 'TIMER0_COMPAddr' : '#20', # Timer/Counter0 Compare Match
+ 'TIMER0_OVFAddr' : '#22', # Timer/Counter0 Overflow
+ 'SPI_STCAddr' : '#24', # SPI Serial Transfer Complete
+ 'USART0_RXAddr' : '#26', # USART0, Rx Complete
+ 'USART0_UDREAddr' : '#28', # USART0 Data register Empty
+ 'USART0_TXAddr' : '#30', # USART0, Tx Complete
+ 'USI_STARTAddr' : '#32', # USI Start Condition
+ 'USI_OVERFLOWAddr' : '#34', # USI Overflow
+ 'ANALOG_COMPAddr' : '#36', # Analog Comparator
+ 'ADCAddr' : '#38', # ADC Conversion Complete
+ 'EE_READYAddr' : '#40', # EEPROM Ready
+ 'SPM_READYAddr' : '#42', # Store Program Memory Read
+
+# Module AD_CONVERTER
+ 'ADMUX' : '$7c', # The ADC multiplexer Selection
+ 'ADMUX_REFS': '$c0', # Reference Selection Bits
+ 'ADMUX_ADLAR': '$20', # Left Adjust Result
+ 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
+ 'ADCSRA' : '$7a', # The ADC Control and Status reg
+ 'ADCSRA_ADEN': '$80', # ADC Enable
+ 'ADCSRA_ADSC': '$40', # ADC Start Conversion
+ 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
+ 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
+ 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
+ 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
+ 'ADC' : '$78', # ADC Data Register Bytes
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Sources
+ 'DIDR0' : '$7e', # Digital Input Disable Register
+ 'DIDR0_ADC7D': '$80', # ADC7 Digital input Disable
+ 'DIDR0_ADC6D': '$40', # ADC6 Digital input Disable
+ 'DIDR0_ADC5D': '$20', # ADC5 Digital input Disable
+ 'DIDR0_ADC4D': '$10', # ADC4 Digital input Disable
+ 'DIDR0_ADC3D': '$8', # ADC3 Digital input Disable
+ 'DIDR0_ADC2D': '$4', # ADC2 Digital input Disable
+ 'DIDR0_ADC1D': '$2', # ADC1 Digital input Disable
+ 'DIDR0_ADC0D': '$1', # ADC0 Digital input Disable
+
+# Module ANALOG_COMPARATOR
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
+ 'ACSR' : '$50', # Analog Comparator Control And
+ 'ACSR_ACD': '$80', # Analog Comparator Disable
+ 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
+ 'ACSR_ACO': '$20', # Analog Compare Output
+ 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
+ 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
+ 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
+ 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
+ 'DIDR1' : '$7f', # Digital Input Disable Register
+ 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
+ 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
+
+# Module USART0
+ 'UDR0' : '$c6', # USART I/O Data Register
+ 'UCSR0A' : '$c0', # USART Control and Status Regis
+ 'UCSR0A_RXC0': '$80', # USART Receive Complete
+ 'UCSR0A_TXC0': '$40', # USART Transmit Complete
+ 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
+ 'UCSR0A_FE0': '$10', # Framing Error
+ 'UCSR0A_DOR0': '$8', # Data OverRun
+ 'UCSR0A_UPE0': '$4', # USART Parity Error
+ 'UCSR0A_U2X0': '$2', # Double the USART Transmission
+ 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
+ 'UCSR0B' : '$c1', # USART Control and Status Regis
+ 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
+ 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
+ 'UCSR0B_UDRIE0': '$20', # USART Data Register Empty Inte
+ 'UCSR0B_RXEN0': '$10', # Receiver Enable
+ 'UCSR0B_TXEN0': '$8', # Transmitter Enable
+ 'UCSR0B_UCSZ02': '$4', # Character Size
+ 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
+ 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
+ 'UCSR0C' : '$c2', # USART Control and Status Regis
+ 'UCSR0C_UMSEL0': '$40', # USART Mode Select
+ 'UCSR0C_UPM0': '$30', # Parity Mode Bits
+ 'UCSR0C_USBS0': '$8', # Stop Bit Select
+ 'UCSR0C_UCSZ0': '$6', # Character Size
+ 'UCSR0C_UCPOL0': '$1', # Clock Polarity
+ 'UBRR0' : '$c4', # USART Baud Rate Register Byte
+
+# Module USI
+ 'USIDR' : '$ba', # USI Data Register
+ 'USISR' : '$b9', # USI Status Register
+ 'USISR_USISIF': '$80', # Start Condition Interrupt Flag
+ 'USISR_USIOIF': '$40', # Counter Overflow Interrupt Fla
+ 'USISR_USIPF': '$20', # Stop Condition Flag
+ 'USISR_USIDC': '$10', # Data Output Collision
+ 'USISR_USICNT': '$f', # USI Counter Value Bits
+ 'USICR' : '$b8', # USI Control Register
+ 'USICR_USISIE': '$80', # Start Condition Interrupt Enab
+ 'USICR_USIOIE': '$40', # Counter Overflow Interrupt Ena
+ 'USICR_USIWM': '$30', # USI Wire Mode Bits
+ 'USICR_USICS': '$c', # USI Clock Source Select Bits
+ 'USICR_USICLK': '$2', # Clock Strobe
+ 'USICR_USITC': '$1', # Toggle Clock Port Pin
+
+# Module SPI
+ 'SPCR' : '$4c', # SPI Control Register
+ 'SPCR_SPIE': '$80', # SPI Interrupt Enable
+ 'SPCR_SPE': '$40', # SPI Enable
+ 'SPCR_DORD': '$20', # Data Order
+ 'SPCR_MSTR': '$10', # Master/Slave Select
+ 'SPCR_CPOL': '$8', # Clock polarity
+ 'SPCR_CPHA': '$4', # Clock Phase
+ 'SPCR_SPR': '$3', # SPI Clock Rate Selects
+ 'SPSR' : '$4d', # SPI Status Register
+ 'SPSR_SPIF': '$80', # SPI Interrupt Flag
+ 'SPSR_WCOL': '$40', # Write Collision Flag
+ 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
+ 'SPDR' : '$4e', # SPI Data Register
+
+# Module BOOT_LOAD
+ 'SPMCSR' : '$57', # Store Program Memory Control R
+ 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
+ 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
+ 'SPMCSR_RWWSRE': '$10', # Read While Write section read
+ 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
+ 'SPMCSR_PGWRT': '$4', # Page Write
+ 'SPMCSR_PGERS': '$2', # Page Erase
+ 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
+
+# Module JTAG
+ 'OCDR' : '$51', # On-Chip Debug Related Register
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_JTD': '$80', # JTAG Interface Disable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+
+# Module EXTERNAL_INTERRUPT
+ 'EICRA' : '$69', # External Interrupt Control Reg
+ 'EICRA_ISC01': '$2', # External Interrupt Sense Contr
+ 'EICRA_ISC00': '$1', # External Interrupt Sense Contr
+ 'EIMSK' : '$3d', # External Interrupt Mask Regist
+ 'EIMSK_PCIE': '$f0', # Pin Change Interrupt Enables
+ 'EIMSK_INT0': '$1', # External Interrupt Request 0 E
+ 'EIFR' : '$3c', # External Interrupt Flag Regist
+ 'EIFR_PCIF': '$f0', # Pin Change Interrupt Flags
+ 'EIFR_INTF0': '$1', # External Interrupt Flag 0
+ 'PCMSK1' : '$6c', # Pin Change Mask Register 1
+ 'PCMSK0' : '$6b', # Pin Change Mask Register 0
+
+# Module EEPROM
+ 'EEAR' : '$41', # EEPROM Read/Write Access Byte
+ 'EEDR' : '$40', # EEPROM Data Register
+ 'EECR' : '$3f', # EEPROM Control Register
+ 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
+ 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
+ 'EECR_EEWE': '$2', # EEPROM Write Enable
+ 'EECR_EERE': '$1', # EEPROM Read Enable
+
+# Module PORTA
+ 'PORTA' : '$22', # Port A Data Register
+ 'DDRA' : '$21', # Port A Data Direction Register
+ 'PINA' : '$20', # Port A Input Pins
+
+# Module PORTB
+ 'PORTB' : '$25', # Port B Data Register
+ 'DDRB' : '$24', # Port B Data Direction Register
+ 'PINB' : '$23', # Port B Input Pins
+
+# Module PORTC
+ 'PORTC' : '$28', # Port C Data Register
+ 'DDRC' : '$27', # Port C Data Direction Register
+ 'PINC' : '$26', # Port C Input Pins
+
+# Module PORTD
+ 'PORTD' : '$2b', # Port D Data Register
+ 'DDRD' : '$2a', # Port D Data Direction Register
+ 'PIND' : '$29', # Port D Input Pins
+
+# Module PORTE
+ 'PORTE' : '$2e', # Data Register, Port E
+ 'DDRE' : '$2d', # Data Direction Register, Port
+ 'PINE' : '$2c', # Input Pins, Port E
+
+# Module PORTF
+ 'PORTF' : '$31', # Data Register, Port F
+ 'DDRF' : '$30', # Data Direction Register, Port
+ 'PINF' : '$2f', # Input Pins, Port F
+
+# Module PORTG
+ 'PORTG' : '$34', # Port G Data Register
+ 'DDRG' : '$33', # Port G Data Direction Register
+ 'PING' : '$32', # Port G Input Pins
+
+# Module TIMER_COUNTER_0
+ 'TCCR0A' : '$44', # Timer/Counter0 Control Registe
+ 'TCCR0A_FOC0A': '$80', # Force Output Compare
+ 'TCCR0A_WGM00': '$40', # Waveform Generation Mode 0
+ 'TCCR0A_COM0A': '$30', # Compare Match Output Modes
+ 'TCCR0A_WGM01': '$8', # Waveform Generation Mode 1
+ 'TCCR0A_CS0': '$7', # Clock Selects
+ 'TCNT0' : '$46', # Timer/Counter0
+ 'OCR0A' : '$47', # Timer/Counter0 Output Compare
+ 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
+ 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
+ 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
+ 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
+ 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
+ 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Control Register
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSR310': '$1', # Prescaler Reset Timer/Counter1
+
+# Module TIMER_COUNTER_1
+ 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
+ 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
+ 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
+ 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
+ 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
+ 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
+ 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
+ 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
+ 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
+ 'TCCR1C' : '$82', # Timer/Counter 1 Control Regist
+ 'TCCR1C_FOC1A': '$80', # Force Output Compare 1A
+ 'TCCR1C_FOC1B': '$40', # Force Output Compare 1B
+ 'TCNT1' : '$84', # Timer/Counter1 Bytes
+ 'OCR1A' : '$88', # Timer/Counter1 Output Compare
+ 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
+ 'ICR1' : '$86', # Timer/Counter1 Input Capture R
+ 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
+ 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
+ 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
+ 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
+ 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
+ 'TIFR1' : '$36', # Timer/Counter1 Interrupt Flag
+ 'TIFR1_ICF1': '$20', # Input Capture Flag 1
+ 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
+ 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
+ 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
+
+# Module TIMER_COUNTER_2
+ 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
+ 'TCCR2A_FOC2A': '$80', # Force Output Compare A
+ 'TCCR2A_WGM20': '$40', # Waveform Generation Mode
+ 'TCCR2A_COM2A': '$30', # Compare Output Mode bits
+ 'TCCR2A_WGM21': '$8', # Waveform Generation Mode
+ 'TCCR2A_CS2': '$7', # Clock Select bits
+ 'TCNT2' : '$b2', # Timer/Counter2
+ 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
+ 'TIMSK2' : '$70', # Timer/Counter2 Interrupt Mask
+ 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
+ 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
+ 'TIFR2' : '$37', # Timer/Counter2 Interrupt Flag
+ 'TIFR2_OCF2A': '$2', # Timer/Counter2 Output Compare
+ 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_PSR2': '$2', # Prescaler Reset Timer/Counter2
+ 'ASSR' : '$b6', # Asynchronous Status Register
+ 'ASSR_EXCLK': '$10', # Enable External Clock Interrup
+ 'ASSR_AS2': '$8', # AS2: Asynchronous Timer/Counte
+ 'ASSR_TCN2UB': '$4', # TCN2UB: Timer/Counter2 Update
+ 'ASSR_OCR2UB': '$2', # Output Compare Register2 Updat
+ 'ASSR_TCR2UB': '$1', # TCR2UB: Timer/Counter Control
+
+# Module WATCHDOG
+ 'WDTCR' : '$60', # Watchdog Timer Control Registe
+ 'WDTCR_WDCE': '$10', # Watchdog Change Enable
+ 'WDTCR_WDE': '$8', # Watch Dog Enable
+ 'WDTCR_WDP': '$7', # Watch Dog Timer Prescaler bits
+
+# Module CPU
+ 'SREG' : '$5f', # Status Register
+ 'SREG_I': '$80', # Global Interrupt Enable
+ 'SREG_T': '$40', # Bit Copy Storage
+ 'SREG_H': '$20', # Half Carry Flag
+ 'SREG_S': '$10', # Sign Bit
+ 'SREG_V': '$8', # Two's Complement Overflow Flag
+ 'SREG_N': '$4', # Negative Flag
+ 'SREG_Z': '$2', # Zero Flag
+ 'SREG_C': '$1', # Carry Flag
+ 'SP' : '$5d', # Stack Pointer
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_JTD': '$80', # JTAG Interface Disable
+ 'MCUCR_BODS': '$40', # BOD Sleep
+ 'MCUCR_BODSE': '$20', # BOD Sleep Enable
+ 'MCUCR_PUD': '$10', # Pull-up disable
+ 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
+ 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+ 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
+ 'MCUSR_BORF': '$4', # Brown-out Reset Flag
+ 'MCUSR_EXTRF': '$2', # External Reset Flag
+ 'MCUSR_PORF': '$1', # Power-on reset flag
+ 'OSCCAL' : '$66', # Oscillator Calibration Value
+ 'CLKPR' : '$61', # Clock Prescale Register
+ 'CLKPR_CLKPCE': '$80', # Clock Prescaler Change Enable
+ 'CLKPR_CLKPS': '$f', # Clock Prescaler Select Bits
+ 'PRR' : '$64', # Power Reduction Register
+ 'PRR_PRLCD': '$10', # Power Reduction LCD
+ 'PRR_PRTIM1': '$8', # Power Reduction Timer/Counter1
+ 'PRR_PRSPI': '$4', # Power Reduction Serial Periphe
+ 'PRR_PRUSART0': '$2', # Power Reduction USART
+ 'PRR_PRADC': '$1', # Power Reduction ADC
+ 'SMCR' : '$53', # Sleep Mode Control Register
+ 'SMCR_SM': '$e', # Sleep Mode Select bits
+ 'SMCR_SE': '$1', # Sleep Enable
+ 'GPIOR2' : '$4b', # General Purpose IO Register 2
+ 'GPIOR1' : '$4a', # General Purpose IO Register 1
+ 'GPIOR0' : '$3e', # General Purpose IO Register 0
+
+ '__amforth_dummy':'0'
+}
diff --git a/amforth-6.5/avr8/devices/atmega325pa/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega325pa/words/no-jtag.asm
new file mode 100644
index 0000000..352a4bb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega325pa/words/no-jtag.asm
@@ -0,0 +1,14 @@
+; ( -- )
+; ( -- )
+; MCU
+; disable jtag at runtime
+VE_NOJTAG:
+ .dw $FF05
+ .db "-jtag",0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOJTAG
+XT_NOJTAG:
+ .dw PFA_NOJTAG
+PFA_NOJTAG:
+
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega325pa/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega325pa/words/no-wdt.asm
new file mode 100644
index 0000000..4a12261
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega325pa/words/no-wdt.asm
@@ -0,0 +1,22 @@
+; ( -- )
+; MCU
+; disable watch dog timer at runtime
+VE_NOWDT:
+ .dw $ff04
+ .db "-wdt"
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOWDT
+XT_NOWDT:
+ .dw PFA_NOWDT
+PFA_NOWDT:
+
+; Reset WDT
+ wdr
+; Write logical one to WDTOE and WDE
+ in_ temp1, WDTCR
+ ori temp1, (1<<WDTOE)|(1<<WDE)
+ out WDTCR, temp1
+; Turn off WDT
+ ldi temp1, (0<<WDE)
+ out_ WDTCR, temp1
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega325pa/words/sleep.asm b/amforth-6.5/avr8/devices/atmega325pa/words/sleep.asm
new file mode 100644
index 0000000..256249c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega325pa/words/sleep.asm
@@ -0,0 +1,19 @@
+; ( mode -- )
+; MCU
+; put the controller into the specified sleep mode
+VE_SLEEP:
+ .dw $ff05
+ .db "sleep", 0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_SLEEP
+XT_SLEEP:
+ .dw PFA_SLEEP
+PFA_SLEEP:
+ andi tosl, 7 ; leave only legal mode bits
+ lsl tosl ; move to correct location (bits 3-1)
+ ori tosl, 1 ; set the SE bit
+ out_ SMCR, tosl ; set the sleep config
+ sleep ; nighty-night
+ out_ SMCR, zerol ; 0 protects against accidental sleeps
+ loadtos ; pop argument from stack
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega328/atmega328.frt b/amforth-6.5/avr8/devices/atmega328/atmega328.frt
new file mode 100644
index 0000000..ce047a9
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega328/atmega328.frt
@@ -0,0 +1,297 @@
+\ Partname: ATmega328
+\ generated automatically
+
+\ USART0
+&198 constant UDR0 \ USART I/O Data Register
+&192 constant UCSR0A \ USART Control and Status Register A
+ $80 constant UCSR0A_RXC0 \ USART Receive Complete
+ $40 constant UCSR0A_TXC0 \ USART Transmitt Complete
+ $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
+ $10 constant UCSR0A_FE0 \ Framing Error
+ $08 constant UCSR0A_DOR0 \ Data overRun
+ $04 constant UCSR0A_UPE0 \ Parity Error
+ $02 constant UCSR0A_U2X0 \ Double the USART transmission speed
+ $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
+&193 constant UCSR0B \ USART Control and Status Register B
+ $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
+ $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
+ $20 constant UCSR0B_UDRIE0 \ USART Data register Empty Interrupt Enable
+ $10 constant UCSR0B_RXEN0 \ Receiver Enable
+ $08 constant UCSR0B_TXEN0 \ Transmitter Enable
+ $04 constant UCSR0B_UCSZ02 \ Character Size
+ $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
+ $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
+&194 constant UCSR0C \ USART Control and Status Register C
+ $C0 constant UCSR0C_UMSEL0 \ USART Mode Select
+ $30 constant UCSR0C_UPM0 \ Parity Mode Bits
+ $08 constant UCSR0C_USBS0 \ Stop Bit Select
+ $06 constant UCSR0C_UCSZ0 \ Character Size
+ $01 constant UCSR0C_UCPOL0 \ Clock Polarity
+&196 constant UBRR0 \ USART Baud Rate Register Bytes
+\ TWI
+&189 constant TWAMR \ TWI (Slave) Address Mask Register
+ $FE constant TWAMR_TWAM \
+&184 constant TWBR \ TWI Bit Rate register
+&188 constant TWCR \ TWI Control Register
+ $80 constant TWCR_TWINT \ TWI Interrupt Flag
+ $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
+ $20 constant TWCR_TWSTA \ TWI Start Condition Bit
+ $10 constant TWCR_TWSTO \ TWI Stop Condition Bit
+ $08 constant TWCR_TWWC \ TWI Write Collition Flag
+ $04 constant TWCR_TWEN \ TWI Enable Bit
+ $01 constant TWCR_TWIE \ TWI Interrupt Enable
+&185 constant TWSR \ TWI Status Register
+ $F8 constant TWSR_TWS \ TWI Status
+ $03 constant TWSR_TWPS \ TWI Prescaler
+&187 constant TWDR \ TWI Data register
+&186 constant TWAR \ TWI (Slave) Address register
+ $FE constant TWAR_TWA \ TWI (Slave) Address register Bits
+ $01 constant TWAR_TWGCE \ TWI General Call Recognition Enable Bit
+\ TIMER_COUNTER_1
+&111 constant TIMSK1 \ Timer/Counter Interrupt Mask Register
+ $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
+ $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output CompareB Match Interrupt Enable
+ $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output CompareA Match Interrupt Enable
+ $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
+&54 constant TIFR1 \ Timer/Counter Interrupt Flag register
+ $20 constant TIFR1_ICF1 \ Input Capture Flag 1
+ $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
+ $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
+ $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
+&128 constant TCCR1A \ Timer/Counter1 Control Register A
+ $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
+ $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
+ $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
+&129 constant TCCR1B \ Timer/Counter1 Control Register B
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
+ $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
+&130 constant TCCR1C \ Timer/Counter1 Control Register C
+ $80 constant TCCR1C_FOC1A \
+ $40 constant TCCR1C_FOC1B \
+&132 constant TCNT1 \ Timer/Counter1 Bytes
+&136 constant OCR1A \ Timer/Counter1 Output Compare Register Bytes
+&138 constant OCR1B \ Timer/Counter1 Output Compare Register Bytes
+&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
+&67 constant GTCCR \ General Timer/Counter Control Register
+ $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
+ $01 constant GTCCR_PSRSYNC \ Prescaler Reset Timer/Counter1 and Timer/Counter0
+\ TIMER_COUNTER_2
+&112 constant TIMSK2 \ Timer/Counter Interrupt Mask register
+ $04 constant TIMSK2_OCIE2B \ Timer/Counter2 Output Compare Match B Interrupt Enable
+ $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match A Interrupt Enable
+ $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
+&55 constant TIFR2 \ Timer/Counter Interrupt Flag Register
+ $04 constant TIFR2_OCF2B \ Output Compare Flag 2B
+ $02 constant TIFR2_OCF2A \ Output Compare Flag 2A
+ $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
+&176 constant TCCR2A \ Timer/Counter2 Control Register A
+ $C0 constant TCCR2A_COM2A \ Compare Output Mode bits
+ $30 constant TCCR2A_COM2B \ Compare Output Mode bits
+ $03 constant TCCR2A_WGM2 \ Waveform Genration Mode
+&177 constant TCCR2B \ Timer/Counter2 Control Register B
+ $80 constant TCCR2B_FOC2A \ Force Output Compare A
+ $40 constant TCCR2B_FOC2B \ Force Output Compare B
+ $08 constant TCCR2B_WGM22 \ Waveform Generation Mode
+ $07 constant TCCR2B_CS2 \ Clock Select bits
+&178 constant TCNT2 \ Timer/Counter2
+&180 constant OCR2B \ Timer/Counter2 Output Compare Register B
+&179 constant OCR2A \ Timer/Counter2 Output Compare Register A
+&182 constant ASSR \ Asynchronous Status Register
+ $40 constant ASSR_EXCLK \ Enable External Clock Input
+ $20 constant ASSR_AS2 \ Asynchronous Timer/Counter2
+ $10 constant ASSR_TCN2UB \ Timer/Counter2 Update Busy
+ $08 constant ASSR_OCR2AUB \ Output Compare Register2 Update Busy
+ $04 constant ASSR_OCR2BUB \ Output Compare Register 2 Update Busy
+ $02 constant ASSR_TCR2AUB \ Timer/Counter Control Register2 Update Busy
+ $01 constant ASSR_TCR2BUB \ Timer/Counter Control Register2 Update Busy
+\ AD_CONVERTER
+&124 constant ADMUX \ The ADC multiplexer Selection Register
+ $C0 constant ADMUX_REFS \ Reference Selection Bits
+ $20 constant ADMUX_ADLAR \ Left Adjust Result
+ $0F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
+&120 constant ADC \ ADC Data Register Bytes
+&122 constant ADCSRA \ The ADC Control and Status register A
+ $80 constant ADCSRA_ADEN \ ADC Enable
+ $40 constant ADCSRA_ADSC \ ADC Start Conversion
+ $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
+ $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
+ $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
+ $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
+&123 constant ADCSRB \ The ADC Control and Status register B
+ $40 constant ADCSRB_ACME \
+ $07 constant ADCSRB_ADTS \ ADC Auto Trigger Source bits
+&126 constant DIDR0 \ Digital Input Disable Register
+ $20 constant DIDR0_ADC5D \
+ $10 constant DIDR0_ADC4D \
+ $08 constant DIDR0_ADC3D \
+ $04 constant DIDR0_ADC2D \
+ $02 constant DIDR0_ADC1D \
+ $01 constant DIDR0_ADC0D \
+\ ANALOG_COMPARATOR
+&80 constant ACSR \ Analog Comparator Control And Status Register
+ $80 constant ACSR_ACD \ Analog Comparator Disable
+ $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
+ $20 constant ACSR_ACO \ Analog Compare Output
+ $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
+ $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
+ $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
+ $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
+&127 constant DIDR1 \ Digital Input Disable Register 1
+ $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
+ $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
+\ PORTB
+&37 constant PORTB \ Port B Data Register
+&36 constant DDRB \ Port B Data Direction Register
+&35 constant PINB \ Port B Input Pins
+\ PORTC
+&40 constant PORTC \ Port C Data Register
+&39 constant DDRC \ Port C Data Direction Register
+&38 constant PINC \ Port C Input Pins
+\ PORTD
+&43 constant PORTD \ Port D Data Register
+&42 constant DDRD \ Port D Data Direction Register
+&41 constant PIND \ Port D Input Pins
+\ TIMER_COUNTER_0
+&72 constant OCR0B \ Timer/Counter0 Output Compare Register
+&71 constant OCR0A \ Timer/Counter0 Output Compare Register
+&70 constant TCNT0 \ Timer/Counter0
+&69 constant TCCR0B \ Timer/Counter Control Register B
+ $80 constant TCCR0B_FOC0A \ Force Output Compare A
+ $40 constant TCCR0B_FOC0B \ Force Output Compare B
+ $08 constant TCCR0B_WGM02 \
+ $07 constant TCCR0B_CS0 \ Clock Select
+&68 constant TCCR0A \ Timer/Counter Control Register A
+ $C0 constant TCCR0A_COM0A \ Compare Output Mode, Phase Correct PWM Mode
+ $30 constant TCCR0A_COM0B \ Compare Output Mode, Fast PWm
+ $03 constant TCCR0A_WGM0 \ Waveform Generation Mode
+&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
+ $04 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare Match B Interrupt Enable
+ $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match A Interrupt Enable
+ $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
+&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
+ $04 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare Flag 0B
+ $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0A
+ $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
+\ EXTERNAL_INTERRUPT
+&105 constant EICRA \ External Interrupt Control Register
+ $0C constant EICRA_ISC1 \ External Interrupt Sense Control 1 Bits
+ $03 constant EICRA_ISC0 \ External Interrupt Sense Control 0 Bits
+&61 constant EIMSK \ External Interrupt Mask Register
+ $03 constant EIMSK_INT \ External Interrupt Request 1 Enable
+&60 constant EIFR \ External Interrupt Flag Register
+ $03 constant EIFR_INTF \ External Interrupt Flags
+&104 constant PCICR \ Pin Change Interrupt Control Register
+ $07 constant PCICR_PCIE \ Pin Change Interrupt Enables
+&109 constant PCMSK2 \ Pin Change Mask Register 2
+ $FF constant PCMSK2_PCINT \ Pin Change Enable Masks
+&108 constant PCMSK1 \ Pin Change Mask Register 1
+ $7F constant PCMSK1_PCINT \ Pin Change Enable Masks
+&107 constant PCMSK0 \ Pin Change Mask Register 0
+ $FF constant PCMSK0_PCINT \ Pin Change Enable Masks
+&59 constant PCIFR \ Pin Change Interrupt Flag Register
+ $07 constant PCIFR_PCIF \ Pin Change Interrupt Flags
+\ SPI
+&78 constant SPDR \ SPI Data Register
+&77 constant SPSR \ SPI Status Register
+ $80 constant SPSR_SPIF \ SPI Interrupt Flag
+ $40 constant SPSR_WCOL \ Write Collision Flag
+ $01 constant SPSR_SPI2X \ Double SPI Speed Bit
+&76 constant SPCR \ SPI Control Register
+ $80 constant SPCR_SPIE \ SPI Interrupt Enable
+ $40 constant SPCR_SPE \ SPI Enable
+ $20 constant SPCR_DORD \ Data Order
+ $10 constant SPCR_MSTR \ Master/Slave Select
+ $08 constant SPCR_CPOL \ Clock polarity
+ $04 constant SPCR_CPHA \ Clock Phase
+ $03 constant SPCR_SPR \ SPI Clock Rate Selects
+\ WATCHDOG
+&96 constant WDTCSR \ Watchdog Timer Control Register
+ $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Flag
+ $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Enable
+ $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
+ $10 constant WDTCSR_WDCE \ Watchdog Change Enable
+ $08 constant WDTCSR_WDE \ Watch Dog Enable
+\ EEPROM
+&65 constant EEAR \ EEPROM Address Register Bytes
+&64 constant EEDR \ EEPROM Data Register
+&63 constant EECR \ EEPROM Control Register
+ $30 constant EECR_EEPM \ EEPROM Programming Mode Bits
+ $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
+ $04 constant EECR_EEMPE \ EEPROM Master Write Enable
+ $02 constant EECR_EEPE \ EEPROM Write Enable
+ $01 constant EECR_EERE \ EEPROM Read Enable
+\ CPU
+&100 constant PRR \ Power Reduction Register
+ $80 constant PRR_PRTWI \ Power Reduction TWI
+ $40 constant PRR_PRTIM2 \ Power Reduction Timer/Counter2
+ $20 constant PRR_PRTIM0 \ Power Reduction Timer/Counter0
+ $08 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
+ $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
+ $02 constant PRR_PRUSART0 \ Power Reduction USART
+ $01 constant PRR_PRADC \ Power Reduction ADC
+&102 constant OSCCAL \ Oscillator Calibration Value
+&97 constant CLKPR \ Clock Prescale Register
+ $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable
+ $0F constant CLKPR_CLKPS \ Clock Prescaler Select Bits
+&95 constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ $08 constant SREG_V \ Two's Complement Overflow Flag
+ $04 constant SREG_N \ Negative Flag
+ $02 constant SREG_Z \ Zero Flag
+ $01 constant SREG_C \ Carry Flag
+&93 constant SP \ Stack Pointer
+&87 constant SPMCSR \ Store Program Memory Control and Status Register
+ $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCSR_RWWSB \ Read-While-Write Section Busy
+ $10 constant SPMCSR_RWWSRE \ Read-While-Write section read enable
+ $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
+ $04 constant SPMCSR_PGWRT \ Page Write
+ $02 constant SPMCSR_PGERS \ Page Erase
+ $01 constant SPMCSR_SELFPRGEN \ Self Programming Enable
+&85 constant MCUCR \ MCU Control Register
+ $10 constant MCUCR_PUD \
+ $02 constant MCUCR_IVSEL \
+ $01 constant MCUCR_IVCE \
+&84 constant MCUSR \ MCU Status Register
+ $08 constant MCUSR_WDRF \ Watchdog Reset Flag
+ $04 constant MCUSR_BORF \ Brown-out Reset Flag
+ $02 constant MCUSR_EXTRF \ External Reset Flag
+ $01 constant MCUSR_PORF \ Power-on reset flag
+&83 constant SMCR \ Sleep Mode Control Register
+ $0E constant SMCR_SM \ Sleep Mode Select Bits
+ $01 constant SMCR_SE \ Sleep Enable
+&75 constant GPIOR2 \ General Purpose I/O Register 2
+&74 constant GPIOR1 \ General Purpose I/O Register 1
+&62 constant GPIOR0 \ General Purpose I/O Register 0
+
+\ Interrupts
+&2 constant INT0Addr \ External Interrupt Request 0
+&4 constant INT1Addr \ External Interrupt Request 1
+&6 constant PCINT0Addr \ Pin Change Interrupt Request 0
+&8 constant PCINT1Addr \ Pin Change Interrupt Request 0
+&10 constant PCINT2Addr \ Pin Change Interrupt Request 1
+&12 constant WDTAddr \ Watchdog Time-out Interrupt
+&14 constant TIMER2_COMPAAddr \ Timer/Counter2 Compare Match A
+&16 constant TIMER2_COMPBAddr \ Timer/Counter2 Compare Match A
+&18 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
+&20 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+&22 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
+&24 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
+&26 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+&28 constant TIMER0_COMPAAddr \ TimerCounter0 Compare Match A
+&30 constant TIMER0_COMPBAddr \ TimerCounter0 Compare Match B
+&32 constant TIMER0_OVFAddr \ Timer/Couner0 Overflow
+&34 constant SPI__STCAddr \ SPI Serial Transfer Complete
+&36 constant USART__RXAddr \ USART Rx Complete
+&38 constant USART__UDREAddr \ USART, Data Register Empty
+&40 constant USART__TXAddr \ USART Tx Complete
+&42 constant ADCAddr \ ADC Conversion Complete
+&44 constant EE_READYAddr \ EEPROM Ready
+&46 constant ANALOG_COMPAddr \ Analog Comparator
+&48 constant TWIAddr \ Two-wire Serial Interface
+&50 constant SPM_ReadyAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/atmega328/device.asm b/amforth-6.5/avr8/devices/atmega328/device.asm
new file mode 100644
index 0000000..3ff142d
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega328/device.asm
@@ -0,0 +1,107 @@
+; Partname: ATmega328
+; generated automatically, do not edit
+
+.nolist
+ .include "m328def.inc"
+.list
+
+.equ ramstart = 256
+.equ CELLSIZE = 2
+.macro readflashcell
+ lsl zl
+ rol zh
+ lpm @0, Z+
+ lpm @1, Z+
+.endmacro
+.macro writeflashcell
+ lsl zl
+ rol zh
+.endmacro
+.set WANT_USART0 = 0
+.set WANT_TWI = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_TIMER_COUNTER_2 = 0
+.set WANT_AD_CONVERTER = 0
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_PORTB = 0
+.set WANT_PORTC = 0
+.set WANT_PORTD = 0
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_SPI = 0
+.set WANT_WATCHDOG = 0
+.set WANT_EEPROM = 0
+.set WANT_CPU = 0
+.equ intvecsize = 2 ; please verify; flash size: 32768 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.org 2
+ rcall isr ; External Interrupt Request 0
+.org 4
+ rcall isr ; External Interrupt Request 1
+.org 6
+ rcall isr ; Pin Change Interrupt Request 0
+.org 8
+ rcall isr ; Pin Change Interrupt Request 0
+.org 10
+ rcall isr ; Pin Change Interrupt Request 1
+.org 12
+ rcall isr ; Watchdog Time-out Interrupt
+.org 14
+ rcall isr ; Timer/Counter2 Compare Match A
+.org 16
+ rcall isr ; Timer/Counter2 Compare Match A
+.org 18
+ rcall isr ; Timer/Counter2 Overflow
+.org 20
+ rcall isr ; Timer/Counter1 Capture Event
+.org 22
+ rcall isr ; Timer/Counter1 Compare Match A
+.org 24
+ rcall isr ; Timer/Counter1 Compare Match B
+.org 26
+ rcall isr ; Timer/Counter1 Overflow
+.org 28
+ rcall isr ; TimerCounter0 Compare Match A
+.org 30
+ rcall isr ; TimerCounter0 Compare Match B
+.org 32
+ rcall isr ; Timer/Couner0 Overflow
+.org 34
+ rcall isr ; SPI Serial Transfer Complete
+.org 36
+ rcall isr ; USART Rx Complete
+.org 38
+ rcall isr ; USART, Data Register Empty
+.org 40
+ rcall isr ; USART Tx Complete
+.org 42
+ rcall isr ; ADC Conversion Complete
+.org 44
+ rcall isr ; EEPROM Ready
+.org 46
+ rcall isr ; Analog Comparator
+.org 48
+ rcall isr ; Two-wire Serial Interface
+.org 50
+ rcall isr ; Store Program Memory Read
+.equ INTVECTORS = 26
+.nooverlap
+
+; compatability layer (maybe empty)
+.equ SPMEN = SELFPRGEN
+
+; controller data area, environment query mcu-info
+mcu_info:
+mcu_ramsize:
+ .dw 2048
+mcu_eepromsize:
+ .dw 1024
+mcu_maxdp:
+ .dw 28672
+mcu_numints:
+ .dw 26
+mcu_name:
+ .dw 9
+ .db "ATmega328",0
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega328/device.inc b/amforth-6.5/avr8/devices/atmega328/device.inc
new file mode 100644
index 0000000..8a2b191
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega328/device.inc
@@ -0,0 +1,996 @@
+; Partname: ATmega328
+; generated automatically, no not edit
+
+.if WANT_USART0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR0:
+ .dw $ff04
+ .db "UDR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR0
+XT_UDR0:
+ .dw PFA_DOVARIABLE
+PFA_UDR0:
+ .dw 198
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR0A:
+ .dw $ff06
+ .db "UCSR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0A
+XT_UCSR0A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0A:
+ .dw 192
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR0B:
+ .dw $ff06
+ .db "UCSR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0B
+XT_UCSR0B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0B:
+ .dw 193
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR0C:
+ .dw $ff06
+ .db "UCSR0C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0C
+XT_UCSR0C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0C:
+ .dw 194
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Bytes
+VE_UBRR0:
+ .dw $ff05
+ .db "UBRR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR0
+XT_UBRR0:
+ .dw PFA_DOVARIABLE
+PFA_UBRR0:
+ .dw 196
+
+.endif
+.if WANT_TWI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; TWI (Slave) Address Mask Register
+VE_TWAMR:
+ .dw $ff05
+ .db "TWAMR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWAMR
+XT_TWAMR:
+ .dw PFA_DOVARIABLE
+PFA_TWAMR:
+ .dw 189
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Bit Rate register
+VE_TWBR:
+ .dw $ff04
+ .db "TWBR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWBR
+XT_TWBR:
+ .dw PFA_DOVARIABLE
+PFA_TWBR:
+ .dw 184
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Control Register
+VE_TWCR:
+ .dw $ff04
+ .db "TWCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWCR
+XT_TWCR:
+ .dw PFA_DOVARIABLE
+PFA_TWCR:
+ .dw 188
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Status Register
+VE_TWSR:
+ .dw $ff04
+ .db "TWSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWSR
+XT_TWSR:
+ .dw PFA_DOVARIABLE
+PFA_TWSR:
+ .dw 185
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Data register
+VE_TWDR:
+ .dw $ff04
+ .db "TWDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWDR
+XT_TWDR:
+ .dw PFA_DOVARIABLE
+PFA_TWDR:
+ .dw 187
+; ( -- addr ) System Constant
+; R( -- )
+; TWI (Slave) Address register
+VE_TWAR:
+ .dw $ff04
+ .db "TWAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWAR
+XT_TWAR:
+ .dw PFA_DOVARIABLE
+PFA_TWAR:
+ .dw 186
+
+.endif
+.if WANT_TIMER_COUNTER_1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Mask Register
+VE_TIMSK1:
+ .dw $ff06
+ .db "TIMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK1
+XT_TIMSK1:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK1:
+ .dw 111
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Flag register
+VE_TIFR1:
+ .dw $ff05
+ .db "TIFR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR1
+XT_TIFR1:
+ .dw PFA_DOVARIABLE
+PFA_TIFR1:
+ .dw 54
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw 128
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw 129
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register C
+VE_TCCR1C:
+ .dw $ff06
+ .db "TCCR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1C
+XT_TCCR1C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1C:
+ .dw 130
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Bytes
+VE_TCNT1:
+ .dw $ff05
+ .db "TCNT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1
+XT_TCNT1:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1:
+ .dw 132
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register Bytes
+VE_OCR1A:
+ .dw $ff05
+ .db "OCR1A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1A
+XT_OCR1A:
+ .dw PFA_DOVARIABLE
+PFA_OCR1A:
+ .dw 136
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register Bytes
+VE_OCR1B:
+ .dw $ff05
+ .db "OCR1B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1B
+XT_OCR1B:
+ .dw PFA_DOVARIABLE
+PFA_OCR1B:
+ .dw 138
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Bytes
+VE_ICR1:
+ .dw $ff04
+ .db "ICR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1
+XT_ICR1:
+ .dw PFA_DOVARIABLE
+PFA_ICR1:
+ .dw 134
+; ( -- addr ) System Constant
+; R( -- )
+; General Timer/Counter Control Register
+VE_GTCCR:
+ .dw $ff05
+ .db "GTCCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GTCCR
+XT_GTCCR:
+ .dw PFA_DOVARIABLE
+PFA_GTCCR:
+ .dw 67
+
+.endif
+.if WANT_TIMER_COUNTER_2 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Mask register
+VE_TIMSK2:
+ .dw $ff06
+ .db "TIMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK2
+XT_TIMSK2:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK2:
+ .dw 112
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Flag Register
+VE_TIFR2:
+ .dw $ff05
+ .db "TIFR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR2
+XT_TIFR2:
+ .dw PFA_DOVARIABLE
+PFA_TIFR2:
+ .dw 55
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register A
+VE_TCCR2A:
+ .dw $ff06
+ .db "TCCR2A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2A
+XT_TCCR2A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2A:
+ .dw 176
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register B
+VE_TCCR2B:
+ .dw $ff06
+ .db "TCCR2B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2B
+XT_TCCR2B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2B:
+ .dw 177
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2
+VE_TCNT2:
+ .dw $ff05
+ .db "TCNT2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT2
+XT_TCNT2:
+ .dw PFA_DOVARIABLE
+PFA_TCNT2:
+ .dw 178
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register B
+VE_OCR2B:
+ .dw $ff05
+ .db "OCR2B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2B
+XT_OCR2B:
+ .dw PFA_DOVARIABLE
+PFA_OCR2B:
+ .dw 180
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register A
+VE_OCR2A:
+ .dw $ff05
+ .db "OCR2A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2A
+XT_OCR2A:
+ .dw PFA_DOVARIABLE
+PFA_OCR2A:
+ .dw 179
+; ( -- addr ) System Constant
+; R( -- )
+; Asynchronous Status Register
+VE_ASSR:
+ .dw $ff04
+ .db "ASSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ASSR
+XT_ASSR:
+ .dw PFA_DOVARIABLE
+PFA_ASSR:
+ .dw 182
+
+.endif
+.if WANT_AD_CONVERTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC multiplexer Selection Register
+VE_ADMUX:
+ .dw $ff05
+ .db "ADMUX",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADMUX
+XT_ADMUX:
+ .dw PFA_DOVARIABLE
+PFA_ADMUX:
+ .dw 124
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register Bytes
+VE_ADC:
+ .dw $ff03
+ .db "ADC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADC
+XT_ADC:
+ .dw PFA_DOVARIABLE
+PFA_ADC:
+ .dw 120
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register A
+VE_ADCSRA:
+ .dw $ff06
+ .db "ADCSRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRA
+XT_ADCSRA:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRA:
+ .dw 122
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register B
+VE_ADCSRB:
+ .dw $ff06
+ .db "ADCSRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRB
+XT_ADCSRB:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRB:
+ .dw 123
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register
+VE_DIDR0:
+ .dw $ff05
+ .db "DIDR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR0
+XT_DIDR0:
+ .dw PFA_DOVARIABLE
+PFA_DIDR0:
+ .dw 126
+
+.endif
+.if WANT_ANALOG_COMPARATOR == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Control And Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw 80
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 1
+VE_DIDR1:
+ .dw $ff05
+ .db "DIDR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR1
+XT_DIDR1:
+ .dw PFA_DOVARIABLE
+PFA_DIDR1:
+ .dw 127
+
+.endif
+.if WANT_PORTB == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw 37
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw 36
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw 35
+
+.endif
+.if WANT_PORTC == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Register
+VE_PORTC:
+ .dw $ff05
+ .db "PORTC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTC
+XT_PORTC:
+ .dw PFA_DOVARIABLE
+PFA_PORTC:
+ .dw 40
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Direction Register
+VE_DDRC:
+ .dw $ff04
+ .db "DDRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRC
+XT_DDRC:
+ .dw PFA_DOVARIABLE
+PFA_DDRC:
+ .dw 39
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Input Pins
+VE_PINC:
+ .dw $ff04
+ .db "PINC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINC
+XT_PINC:
+ .dw PFA_DOVARIABLE
+PFA_PINC:
+ .dw 38
+
+.endif
+.if WANT_PORTD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw 43
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw 42
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw 41
+
+.endif
+.if WANT_TIMER_COUNTER_0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0B:
+ .dw $ff05
+ .db "OCR0B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0B
+XT_OCR0B:
+ .dw PFA_DOVARIABLE
+PFA_OCR0B:
+ .dw 72
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0A:
+ .dw $ff05
+ .db "OCR0A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0A
+XT_OCR0A:
+ .dw PFA_DOVARIABLE
+PFA_OCR0A:
+ .dw 71
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw 70
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register B
+VE_TCCR0B:
+ .dw $ff06
+ .db "TCCR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0B
+XT_TCCR0B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0B:
+ .dw 69
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register A
+VE_TCCR0A:
+ .dw $ff06
+ .db "TCCR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0A
+XT_TCCR0A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0A:
+ .dw 68
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Mask Register
+VE_TIMSK0:
+ .dw $ff06
+ .db "TIMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK0
+XT_TIMSK0:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK0:
+ .dw 110
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Flag register
+VE_TIFR0:
+ .dw $ff05
+ .db "TIFR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR0
+XT_TIFR0:
+ .dw PFA_DOVARIABLE
+PFA_TIFR0:
+ .dw 53
+
+.endif
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register
+VE_EICRA:
+ .dw $ff05
+ .db "EICRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRA
+XT_EICRA:
+ .dw PFA_DOVARIABLE
+PFA_EICRA:
+ .dw 105
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Mask Register
+VE_EIMSK:
+ .dw $ff05
+ .db "EIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIMSK
+XT_EIMSK:
+ .dw PFA_DOVARIABLE
+PFA_EIMSK:
+ .dw 61
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Flag Register
+VE_EIFR:
+ .dw $ff04
+ .db "EIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIFR
+XT_EIFR:
+ .dw PFA_DOVARIABLE
+PFA_EIFR:
+ .dw 60
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Interrupt Control Register
+VE_PCICR:
+ .dw $ff05
+ .db "PCICR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCICR
+XT_PCICR:
+ .dw PFA_DOVARIABLE
+PFA_PCICR:
+ .dw 104
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 2
+VE_PCMSK2:
+ .dw $ff06
+ .db "PCMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK2
+XT_PCMSK2:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK2:
+ .dw 109
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 1
+VE_PCMSK1:
+ .dw $ff06
+ .db "PCMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK1
+XT_PCMSK1:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK1:
+ .dw 108
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 0
+VE_PCMSK0:
+ .dw $ff06
+ .db "PCMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK0
+XT_PCMSK0:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK0:
+ .dw 107
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Interrupt Flag Register
+VE_PCIFR:
+ .dw $ff05
+ .db "PCIFR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCIFR
+XT_PCIFR:
+ .dw PFA_DOVARIABLE
+PFA_PCIFR:
+ .dw 59
+
+.endif
+.if WANT_SPI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR:
+ .dw $ff04
+ .db "SPDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR
+XT_SPDR:
+ .dw PFA_DOVARIABLE
+PFA_SPDR:
+ .dw 78
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR:
+ .dw $ff04
+ .db "SPSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR
+XT_SPSR:
+ .dw PFA_DOVARIABLE
+PFA_SPSR:
+ .dw 77
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR:
+ .dw $ff04
+ .db "SPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR
+XT_SPCR:
+ .dw PFA_DOVARIABLE
+PFA_SPCR:
+ .dw 76
+
+.endif
+.if WANT_WATCHDOG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCSR:
+ .dw $ff06
+ .db "WDTCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCSR
+XT_WDTCSR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCSR:
+ .dw 96
+
+.endif
+.if WANT_EEPROM == 1
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Address Register Bytes
+VE_EEAR:
+ .dw $ff04
+ .db "EEAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEAR
+XT_EEAR:
+ .dw PFA_DOVARIABLE
+PFA_EEAR:
+ .dw 65
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw 64
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw 63
+
+.endif
+.if WANT_CPU == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register
+VE_PRR:
+ .dw $ff03
+ .db "PRR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR
+XT_PRR:
+ .dw PFA_DOVARIABLE
+PFA_PRR:
+ .dw 100
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Calibration Value
+VE_OSCCAL:
+ .dw $ff06
+ .db "OSCCAL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSCCAL
+XT_OSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_OSCCAL:
+ .dw 102
+; ( -- addr ) System Constant
+; R( -- )
+; Clock Prescale Register
+VE_CLKPR:
+ .dw $ff05
+ .db "CLKPR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKPR
+XT_CLKPR:
+ .dw PFA_DOVARIABLE
+PFA_CLKPR:
+ .dw 97
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw 95
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer
+VE_SP:
+ .dw $ff02
+ .db "SP"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SP
+XT_SP:
+ .dw PFA_DOVARIABLE
+PFA_SP:
+ .dw 93
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control and Status Register
+VE_SPMCSR:
+ .dw $ff06
+ .db "SPMCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCSR
+XT_SPMCSR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCSR:
+ .dw 87
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw 85
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Status Register
+VE_MCUSR:
+ .dw $ff05
+ .db "MCUSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUSR
+XT_MCUSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUSR:
+ .dw 84
+; ( -- addr ) System Constant
+; R( -- )
+; Sleep Mode Control Register
+VE_SMCR:
+ .dw $ff04
+ .db "SMCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SMCR
+XT_SMCR:
+ .dw PFA_DOVARIABLE
+PFA_SMCR:
+ .dw 83
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose I/O Register 2
+VE_GPIOR2:
+ .dw $ff06
+ .db "GPIOR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR2
+XT_GPIOR2:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR2:
+ .dw 75
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose I/O Register 1
+VE_GPIOR1:
+ .dw $ff06
+ .db "GPIOR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR1
+XT_GPIOR1:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR1:
+ .dw 74
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose I/O Register 0
+VE_GPIOR0:
+ .dw $ff06
+ .db "GPIOR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR0
+XT_GPIOR0:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR0:
+ .dw 62
+
+.endif
diff --git a/amforth-6.5/avr8/devices/atmega328/device.py b/amforth-6.5/avr8/devices/atmega328/device.py
new file mode 100644
index 0000000..776a2d7
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega328/device.py
@@ -0,0 +1,322 @@
+# Generated Automatically
+
+# Partname ATmega328
+
+MCUREGS = {
+# Interrupt Vectors
+ 'INT0Addr' : '#2', # External Interrupt Request 0
+ 'INT1Addr' : '#4', # External Interrupt Request 1
+ 'PCINT0Addr' : '#6', # Pin Change Interrupt Request 0
+ 'PCINT1Addr' : '#8', # Pin Change Interrupt Request 0
+ 'PCINT2Addr' : '#10', # Pin Change Interrupt Request 1
+ 'WDTAddr' : '#12', # Watchdog Time-out Interrupt
+ 'TIMER2_COMPAAddr' : '#14', # Timer/Counter2 Compare Match A
+ 'TIMER2_COMPBAddr' : '#16', # Timer/Counter2 Compare Match A
+ 'TIMER2_OVFAddr' : '#18', # Timer/Counter2 Overflow
+ 'TIMER1_CAPTAddr' : '#20', # Timer/Counter1 Capture Event
+ 'TIMER1_COMPAAddr' : '#22', # Timer/Counter1 Compare Match A
+ 'TIMER1_COMPBAddr' : '#24', # Timer/Counter1 Compare Match B
+ 'TIMER1_OVFAddr' : '#26', # Timer/Counter1 Overflow
+ 'TIMER0_COMPAAddr' : '#28', # TimerCounter0 Compare Match A
+ 'TIMER0_COMPBAddr' : '#30', # TimerCounter0 Compare Match B
+ 'TIMER0_OVFAddr' : '#32', # Timer/Couner0 Overflow
+ 'SPI_STCAddr' : '#34', # SPI Serial Transfer Complete
+ 'USART_RXAddr' : '#36', # USART Rx Complete
+ 'USART_UDREAddr' : '#38', # USART, Data Register Empty
+ 'USART_TXAddr' : '#40', # USART Tx Complete
+ 'ADCAddr' : '#42', # ADC Conversion Complete
+ 'EE_READYAddr' : '#44', # EEPROM Ready
+ 'ANALOG_COMPAddr' : '#46', # Analog Comparator
+ 'TWIAddr' : '#48', # Two-wire Serial Interface
+ 'SPM_ReadyAddr' : '#50', # Store Program Memory Read
+
+# Module USART0
+ 'UDR0' : '$c6', # USART I/O Data Register
+ 'UCSR0A' : '$c0', # USART Control and Status Regis
+ 'UCSR0A_RXC0': '$80', # USART Receive Complete
+ 'UCSR0A_TXC0': '$40', # USART Transmitt Complete
+ 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
+ 'UCSR0A_FE0': '$10', # Framing Error
+ 'UCSR0A_DOR0': '$8', # Data overRun
+ 'UCSR0A_UPE0': '$4', # Parity Error
+ 'UCSR0A_U2X0': '$2', # Double the USART transmission
+ 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
+ 'UCSR0B' : '$c1', # USART Control and Status Regis
+ 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
+ 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
+ 'UCSR0B_UDRIE0': '$20', # USART Data register Empty Inte
+ 'UCSR0B_RXEN0': '$10', # Receiver Enable
+ 'UCSR0B_TXEN0': '$8', # Transmitter Enable
+ 'UCSR0B_UCSZ02': '$4', # Character Size
+ 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
+ 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
+ 'UCSR0C' : '$c2', # USART Control and Status Regis
+ 'UCSR0C_UMSEL0': '$c0', # USART Mode Select
+ 'UCSR0C_UPM0': '$30', # Parity Mode Bits
+ 'UCSR0C_USBS0': '$8', # Stop Bit Select
+ 'UCSR0C_UCSZ0': '$6', # Character Size
+ 'UCSR0C_UCPOL0': '$1', # Clock Polarity
+ 'UBRR0' : '$c4', # USART Baud Rate Register Byte
+
+# Module TWI
+ 'TWAMR' : '$bd', # TWI (Slave) Address Mask Regis
+ 'TWAMR_TWAM': '$fe', #
+ 'TWBR' : '$b8', # TWI Bit Rate register
+ 'TWCR' : '$bc', # TWI Control Register
+ 'TWCR_TWINT': '$80', # TWI Interrupt Flag
+ 'TWCR_TWEA': '$40', # TWI Enable Acknowledge Bit
+ 'TWCR_TWSTA': '$20', # TWI Start Condition Bit
+ 'TWCR_TWSTO': '$10', # TWI Stop Condition Bit
+ 'TWCR_TWWC': '$8', # TWI Write Collition Flag
+ 'TWCR_TWEN': '$4', # TWI Enable Bit
+ 'TWCR_TWIE': '$1', # TWI Interrupt Enable
+ 'TWSR' : '$b9', # TWI Status Register
+ 'TWSR_TWS': '$f8', # TWI Status
+ 'TWSR_TWPS': '$3', # TWI Prescaler
+ 'TWDR' : '$bb', # TWI Data register
+ 'TWAR' : '$ba', # TWI (Slave) Address register
+ 'TWAR_TWA': '$fe', # TWI (Slave) Address register B
+ 'TWAR_TWGCE': '$1', # TWI General Call Recognition E
+
+# Module TIMER_COUNTER_1
+ 'TIMSK1' : '$6f', # Timer/Counter Interrupt Mask R
+ 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
+ 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output CompareB
+ 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output CompareA
+ 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
+ 'TIFR1' : '$36', # Timer/Counter Interrupt Flag r
+ 'TIFR1_ICF1': '$20', # Input Capture Flag 1
+ 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
+ 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
+ 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
+ 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
+ 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
+ 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
+ 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
+ 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
+ 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
+ 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
+ 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
+ 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
+ 'TCCR1C' : '$82', # Timer/Counter1 Control Registe
+ 'TCCR1C_FOC1A': '$80', #
+ 'TCCR1C_FOC1B': '$40', #
+ 'TCNT1' : '$84', # Timer/Counter1 Bytes
+ 'OCR1A' : '$88', # Timer/Counter1 Output Compare
+ 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
+ 'ICR1' : '$86', # Timer/Counter1 Input Capture R
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSRSYNC': '$1', # Prescaler Reset Timer/Counter1
+
+# Module TIMER_COUNTER_2
+ 'TIMSK2' : '$70', # Timer/Counter Interrupt Mask r
+ 'TIMSK2_OCIE2B': '$4', # Timer/Counter2 Output Compare
+ 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
+ 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
+ 'TIFR2' : '$37', # Timer/Counter Interrupt Flag R
+ 'TIFR2_OCF2B': '$4', # Output Compare Flag 2B
+ 'TIFR2_OCF2A': '$2', # Output Compare Flag 2A
+ 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
+ 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
+ 'TCCR2A_COM2A': '$c0', # Compare Output Mode bits
+ 'TCCR2A_COM2B': '$30', # Compare Output Mode bits
+ 'TCCR2A_WGM2': '$3', # Waveform Genration Mode
+ 'TCCR2B' : '$b1', # Timer/Counter2 Control Registe
+ 'TCCR2B_FOC2A': '$80', # Force Output Compare A
+ 'TCCR2B_FOC2B': '$40', # Force Output Compare B
+ 'TCCR2B_WGM22': '$8', # Waveform Generation Mode
+ 'TCCR2B_CS2': '$7', # Clock Select bits
+ 'TCNT2' : '$b2', # Timer/Counter2
+ 'OCR2B' : '$b4', # Timer/Counter2 Output Compare
+ 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
+ 'ASSR' : '$b6', # Asynchronous Status Register
+ 'ASSR_EXCLK': '$40', # Enable External Clock Input
+ 'ASSR_AS2': '$20', # Asynchronous Timer/Counter2
+ 'ASSR_TCN2UB': '$10', # Timer/Counter2 Update Busy
+ 'ASSR_OCR2AUB': '$8', # Output Compare Register2 Updat
+ 'ASSR_OCR2BUB': '$4', # Output Compare Register 2 Upda
+ 'ASSR_TCR2AUB': '$2', # Timer/Counter Control Register
+ 'ASSR_TCR2BUB': '$1', # Timer/Counter Control Register
+ 'GTCCR' : '$43', # General Timer Counter Control
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSRASY': '$2', # Prescaler Reset Timer/Counter2
+
+# Module AD_CONVERTER
+ 'ADMUX' : '$7c', # The ADC multiplexer Selection
+ 'ADMUX_REFS': '$c0', # Reference Selection Bits
+ 'ADMUX_ADLAR': '$20', # Left Adjust Result
+ 'ADMUX_MUX': '$f', # Analog Channel and Gain Select
+ 'ADC' : '$78', # ADC Data Register Bytes
+ 'ADCSRA' : '$7a', # The ADC Control and Status reg
+ 'ADCSRA_ADEN': '$80', # ADC Enable
+ 'ADCSRA_ADSC': '$40', # ADC Start Conversion
+ 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
+ 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
+ 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
+ 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
+ 'ADCSRB' : '$7b', # The ADC Control and Status reg
+ 'ADCSRB_ACME': '$40', #
+ 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Source bits
+ 'DIDR0' : '$7e', # Digital Input Disable Register
+ 'DIDR0_ADC5D': '$20', #
+ 'DIDR0_ADC4D': '$10', #
+ 'DIDR0_ADC3D': '$8', #
+ 'DIDR0_ADC2D': '$4', #
+ 'DIDR0_ADC1D': '$2', #
+ 'DIDR0_ADC0D': '$1', #
+
+# Module ANALOG_COMPARATOR
+ 'ACSR' : '$50', # Analog Comparator Control And
+ 'ACSR_ACD': '$80', # Analog Comparator Disable
+ 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
+ 'ACSR_ACO': '$20', # Analog Compare Output
+ 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
+ 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
+ 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
+ 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
+ 'DIDR1' : '$7f', # Digital Input Disable Register
+ 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
+ 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
+
+# Module PORTB
+ 'PORTB' : '$25', # Port B Data Register
+ 'DDRB' : '$24', # Port B Data Direction Register
+ 'PINB' : '$23', # Port B Input Pins
+
+# Module PORTC
+ 'PORTC' : '$28', # Port C Data Register
+ 'DDRC' : '$27', # Port C Data Direction Register
+ 'PINC' : '$26', # Port C Input Pins
+
+# Module PORTD
+ 'PORTD' : '$2b', # Port D Data Register
+ 'DDRD' : '$2a', # Port D Data Direction Register
+ 'PIND' : '$29', # Port D Input Pins
+
+# Module TIMER_COUNTER_0
+ 'OCR0B' : '$48', # Timer/Counter0 Output Compare
+ 'OCR0A' : '$47', # Timer/Counter0 Output Compare
+ 'TCNT0' : '$46', # Timer/Counter0
+ 'TCCR0B' : '$45', # Timer/Counter Control Register
+ 'TCCR0B_FOC0A': '$80', # Force Output Compare A
+ 'TCCR0B_FOC0B': '$40', # Force Output Compare B
+ 'TCCR0B_WGM02': '$8', #
+ 'TCCR0B_CS0': '$7', # Clock Select
+ 'TCCR0A' : '$44', # Timer/Counter Control Registe
+ 'TCCR0A_COM0A': '$c0', # Compare Output Mode, Phase Cor
+ 'TCCR0A_COM0B': '$30', # Compare Output Mode, Fast PWm
+ 'TCCR0A_WGM0': '$3', # Waveform Generation Mode
+ 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
+ 'TIMSK0_OCIE0B': '$4', # Timer/Counter0 Output Compare
+ 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
+ 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
+ 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
+ 'TIFR0_OCF0B': '$4', # Timer/Counter0 Output Compare
+ 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
+ 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSRSYNC': '$1', # Prescaler Reset Timer/Counter1
+
+# Module EXTERNAL_INTERRUPT
+ 'EICRA' : '$69', # External Interrupt Control Reg
+ 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
+ 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
+ 'EIMSK' : '$3d', # External Interrupt Mask Regist
+ 'EIMSK_INT': '$3', # External Interrupt Request 1 E
+ 'EIFR' : '$3c', # External Interrupt Flag Regist
+ 'EIFR_INTF': '$3', # External Interrupt Flags
+ 'PCICR' : '$68', # Pin Change Interrupt Control R
+ 'PCICR_PCIE': '$7', # Pin Change Interrupt Enables
+ 'PCMSK2' : '$6d', # Pin Change Mask Register 2
+ 'PCMSK2_PCINT': '$ff', # Pin Change Enable Masks
+ 'PCMSK1' : '$6c', # Pin Change Mask Register 1
+ 'PCMSK1_PCINT': '$7f', # Pin Change Enable Masks
+ 'PCMSK0' : '$6b', # Pin Change Mask Register 0
+ 'PCMSK0_PCINT': '$ff', # Pin Change Enable Masks
+ 'PCIFR' : '$3b', # Pin Change Interrupt Flag Regi
+ 'PCIFR_PCIF': '$7', # Pin Change Interrupt Flags
+
+# Module SPI
+ 'SPDR' : '$4e', # SPI Data Register
+ 'SPSR' : '$4d', # SPI Status Register
+ 'SPSR_SPIF': '$80', # SPI Interrupt Flag
+ 'SPSR_WCOL': '$40', # Write Collision Flag
+ 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
+ 'SPCR' : '$4c', # SPI Control Register
+ 'SPCR_SPIE': '$80', # SPI Interrupt Enable
+ 'SPCR_SPE': '$40', # SPI Enable
+ 'SPCR_DORD': '$20', # Data Order
+ 'SPCR_MSTR': '$10', # Master/Slave Select
+ 'SPCR_CPOL': '$8', # Clock polarity
+ 'SPCR_CPHA': '$4', # Clock Phase
+ 'SPCR_SPR': '$3', # SPI Clock Rate Selects
+
+# Module WATCHDOG
+ 'WDTCSR' : '$60', # Watchdog Timer Control Registe
+ 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
+ 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
+ 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
+ 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
+ 'WDTCSR_WDE': '$8', # Watch Dog Enable
+
+# Module EEPROM
+ 'EEAR' : '$41', # EEPROM Address Register Bytes
+ 'EEDR' : '$40', # EEPROM Data Register
+ 'EECR' : '$3f', # EEPROM Control Register
+ 'EECR_EEPM': '$30', # EEPROM Programming Mode Bits
+ 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
+ 'EECR_EEMPE': '$4', # EEPROM Master Write Enable
+ 'EECR_EEPE': '$2', # EEPROM Write Enable
+ 'EECR_EERE': '$1', # EEPROM Read Enable
+
+# Module CPU
+ 'PRR' : '$64', # Power Reduction Register
+ 'PRR_PRTWI': '$80', # Power Reduction TWI
+ 'PRR_PRTIM2': '$40', # Power Reduction Timer/Counter2
+ 'PRR_PRTIM0': '$20', # Power Reduction Timer/Counter0
+ 'PRR_PRTIM1': '$8', # Power Reduction Timer/Counter1
+ 'PRR_PRSPI': '$4', # Power Reduction Serial Periphe
+ 'PRR_PRUSART0': '$2', # Power Reduction USART
+ 'PRR_PRADC': '$1', # Power Reduction ADC
+ 'OSCCAL' : '$66', # Oscillator Calibration Value
+ 'CLKPR' : '$61', # Clock Prescale Register
+ 'CLKPR_CLKPCE': '$80', # Clock Prescaler Change Enable
+ 'CLKPR_CLKPS': '$f', # Clock Prescaler Select Bits
+ 'SREG' : '$5f', # Status Register
+ 'SREG_I': '$80', # Global Interrupt Enable
+ 'SREG_T': '$40', # Bit Copy Storage
+ 'SREG_H': '$20', # Half Carry Flag
+ 'SREG_S': '$10', # Sign Bit
+ 'SREG_V': '$8', # Two's Complement Overflow Flag
+ 'SREG_N': '$4', # Negative Flag
+ 'SREG_Z': '$2', # Zero Flag
+ 'SREG_C': '$1', # Carry Flag
+ 'SP' : '$5d', # Stack Pointer
+ 'SPMCSR' : '$57', # Store Program Memory Control a
+ 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
+ 'SPMCSR_RWWSB': '$40', # Read-While-Write Section Busy
+ 'SPMCSR_RWWSRE': '$10', # Read-While-Write section read
+ 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
+ 'SPMCSR_PGWRT': '$4', # Page Write
+ 'SPMCSR_PGERS': '$2', # Page Erase
+ 'SPMCSR_SELFPRGEN': '$1', # Self Programming Enable
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_PUD': '$10', #
+ 'MCUCR_IVSEL': '$2', #
+ 'MCUCR_IVCE': '$1', #
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
+ 'MCUSR_BORF': '$4', # Brown-out Reset Flag
+ 'MCUSR_EXTRF': '$2', # External Reset Flag
+ 'MCUSR_PORF': '$1', # Power-on reset flag
+ 'SMCR' : '$53', # Sleep Mode Control Register
+ 'SMCR_SM': '$e', # Sleep Mode Select Bits
+ 'SMCR_SE': '$1', # Sleep Enable
+ 'GPIOR2' : '$4b', # General Purpose I/O Register 2
+ 'GPIOR1' : '$4a', # General Purpose I/O Register 1
+ 'GPIOR0' : '$3e', # General Purpose I/O Register 0
+
+ '__amforth_dummy':'0'
+}
diff --git a/amforth-6.5/avr8/devices/atmega328/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega328/words/no-jtag.asm
new file mode 100644
index 0000000..352a4bb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega328/words/no-jtag.asm
@@ -0,0 +1,14 @@
+; ( -- )
+; ( -- )
+; MCU
+; disable jtag at runtime
+VE_NOJTAG:
+ .dw $FF05
+ .db "-jtag",0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOJTAG
+XT_NOJTAG:
+ .dw PFA_NOJTAG
+PFA_NOJTAG:
+
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega328/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega328/words/no-wdt.asm
new file mode 100644
index 0000000..ff6ddd1
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega328/words/no-wdt.asm
@@ -0,0 +1,34 @@
+; ( -- )
+; MCU
+; disable watch dog timer at runtime
+VE_NOWDT:
+ .dw $ff04
+ .db "-wdt"
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOWDT
+XT_NOWDT:
+ .dw PFA_NOWDT
+PFA_NOWDT:
+
+ in temp1,SREG
+ push temp1
+ ; Turn always off global interrupt.
+ cli
+ ; Reset Watchdog Timer
+ wdr
+ ; Clear WDRF in MCUSR
+ in temp1, MCUSR
+ andi temp1, (0xff & (0<<WDRF))
+ out MCUSR, temp1
+ ; Write logical one to WDCE and WDE
+ ; Keep old prescaler setting to prevent unintentional time-out
+ in_ temp1, WDTCSR
+ ori temp1, (1<<WDCE) | (1<<WDE)
+ out_ WDTCSR, temp1
+ ; Turn off WDT
+ ldi temp1, (0<<WDE)
+ out_ WDTCSR, temp1
+ ; restore status register
+ pop temp1
+ out SREG,temp1
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega328/words/sleep.asm b/amforth-6.5/avr8/devices/atmega328/words/sleep.asm
new file mode 100644
index 0000000..256249c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega328/words/sleep.asm
@@ -0,0 +1,19 @@
+; ( mode -- )
+; MCU
+; put the controller into the specified sleep mode
+VE_SLEEP:
+ .dw $ff05
+ .db "sleep", 0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_SLEEP
+XT_SLEEP:
+ .dw PFA_SLEEP
+PFA_SLEEP:
+ andi tosl, 7 ; leave only legal mode bits
+ lsl tosl ; move to correct location (bits 3-1)
+ ori tosl, 1 ; set the SE bit
+ out_ SMCR, tosl ; set the sleep config
+ sleep ; nighty-night
+ out_ SMCR, zerol ; 0 protects against accidental sleeps
+ loadtos ; pop argument from stack
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega328p/atmega328p.frt b/amforth-6.5/avr8/devices/atmega328p/atmega328p.frt
new file mode 100644
index 0000000..27fb70f
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega328p/atmega328p.frt
@@ -0,0 +1,299 @@
+\ Partname: ATmega328P
+\ generated automatically
+
+\ USART0
+&198 constant UDR0 \ USART I/O Data Register
+&192 constant UCSR0A \ USART Control and Status Register A
+ $80 constant UCSR0A_RXC0 \ USART Receive Complete
+ $40 constant UCSR0A_TXC0 \ USART Transmitt Complete
+ $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
+ $10 constant UCSR0A_FE0 \ Framing Error
+ $08 constant UCSR0A_DOR0 \ Data overRun
+ $04 constant UCSR0A_UPE0 \ Parity Error
+ $02 constant UCSR0A_U2X0 \ Double the USART transmission speed
+ $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
+&193 constant UCSR0B \ USART Control and Status Register B
+ $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
+ $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
+ $20 constant UCSR0B_UDRIE0 \ USART Data register Empty Interrupt Enable
+ $10 constant UCSR0B_RXEN0 \ Receiver Enable
+ $08 constant UCSR0B_TXEN0 \ Transmitter Enable
+ $04 constant UCSR0B_UCSZ02 \ Character Size
+ $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
+ $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
+&194 constant UCSR0C \ USART Control and Status Register C
+ $C0 constant UCSR0C_UMSEL0 \ USART Mode Select
+ $30 constant UCSR0C_UPM0 \ Parity Mode Bits
+ $08 constant UCSR0C_USBS0 \ Stop Bit Select
+ $06 constant UCSR0C_UCSZ0 \ Character Size
+ $01 constant UCSR0C_UCPOL0 \ Clock Polarity
+&196 constant UBRR0 \ USART Baud Rate Register Bytes
+\ TWI
+&189 constant TWAMR \ TWI (Slave) Address Mask Register
+ $FE constant TWAMR_TWAM \
+&184 constant TWBR \ TWI Bit Rate register
+&188 constant TWCR \ TWI Control Register
+ $80 constant TWCR_TWINT \ TWI Interrupt Flag
+ $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
+ $20 constant TWCR_TWSTA \ TWI Start Condition Bit
+ $10 constant TWCR_TWSTO \ TWI Stop Condition Bit
+ $08 constant TWCR_TWWC \ TWI Write Collition Flag
+ $04 constant TWCR_TWEN \ TWI Enable Bit
+ $01 constant TWCR_TWIE \ TWI Interrupt Enable
+&185 constant TWSR \ TWI Status Register
+ $F8 constant TWSR_TWS \ TWI Status
+ $03 constant TWSR_TWPS \ TWI Prescaler
+&187 constant TWDR \ TWI Data register
+&186 constant TWAR \ TWI (Slave) Address register
+ $FE constant TWAR_TWA \ TWI (Slave) Address register Bits
+ $01 constant TWAR_TWGCE \ TWI General Call Recognition Enable Bit
+\ TIMER_COUNTER_1
+&111 constant TIMSK1 \ Timer/Counter Interrupt Mask Register
+ $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
+ $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output CompareB Match Interrupt Enable
+ $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output CompareA Match Interrupt Enable
+ $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
+&54 constant TIFR1 \ Timer/Counter Interrupt Flag register
+ $20 constant TIFR1_ICF1 \ Input Capture Flag 1
+ $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
+ $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
+ $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
+&128 constant TCCR1A \ Timer/Counter1 Control Register A
+ $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
+ $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
+ $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
+&129 constant TCCR1B \ Timer/Counter1 Control Register B
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
+ $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
+&130 constant TCCR1C \ Timer/Counter1 Control Register C
+ $80 constant TCCR1C_FOC1A \
+ $40 constant TCCR1C_FOC1B \
+&132 constant TCNT1 \ Timer/Counter1 Bytes
+&136 constant OCR1A \ Timer/Counter1 Output Compare Register Bytes
+&138 constant OCR1B \ Timer/Counter1 Output Compare Register Bytes
+&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
+&67 constant GTCCR \ General Timer/Counter Control Register
+ $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
+ $01 constant GTCCR_PSRSYNC \ Prescaler Reset Timer/Counter1 and Timer/Counter0
+\ TIMER_COUNTER_2
+&112 constant TIMSK2 \ Timer/Counter Interrupt Mask register
+ $04 constant TIMSK2_OCIE2B \ Timer/Counter2 Output Compare Match B Interrupt Enable
+ $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match A Interrupt Enable
+ $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
+&55 constant TIFR2 \ Timer/Counter Interrupt Flag Register
+ $04 constant TIFR2_OCF2B \ Output Compare Flag 2B
+ $02 constant TIFR2_OCF2A \ Output Compare Flag 2A
+ $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
+&176 constant TCCR2A \ Timer/Counter2 Control Register A
+ $C0 constant TCCR2A_COM2A \ Compare Output Mode bits
+ $30 constant TCCR2A_COM2B \ Compare Output Mode bits
+ $03 constant TCCR2A_WGM2 \ Waveform Genration Mode
+&177 constant TCCR2B \ Timer/Counter2 Control Register B
+ $80 constant TCCR2B_FOC2A \ Force Output Compare A
+ $40 constant TCCR2B_FOC2B \ Force Output Compare B
+ $08 constant TCCR2B_WGM22 \ Waveform Generation Mode
+ $07 constant TCCR2B_CS2 \ Clock Select bits
+&178 constant TCNT2 \ Timer/Counter2
+&180 constant OCR2B \ Timer/Counter2 Output Compare Register B
+&179 constant OCR2A \ Timer/Counter2 Output Compare Register A
+&182 constant ASSR \ Asynchronous Status Register
+ $40 constant ASSR_EXCLK \ Enable External Clock Input
+ $20 constant ASSR_AS2 \ Asynchronous Timer/Counter2
+ $10 constant ASSR_TCN2UB \ Timer/Counter2 Update Busy
+ $08 constant ASSR_OCR2AUB \ Output Compare Register2 Update Busy
+ $04 constant ASSR_OCR2BUB \ Output Compare Register 2 Update Busy
+ $02 constant ASSR_TCR2AUB \ Timer/Counter Control Register2 Update Busy
+ $01 constant ASSR_TCR2BUB \ Timer/Counter Control Register2 Update Busy
+\ AD_CONVERTER
+&124 constant ADMUX \ The ADC multiplexer Selection Register
+ $C0 constant ADMUX_REFS \ Reference Selection Bits
+ $20 constant ADMUX_ADLAR \ Left Adjust Result
+ $0F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
+&120 constant ADC \ ADC Data Register Bytes
+&122 constant ADCSRA \ The ADC Control and Status register A
+ $80 constant ADCSRA_ADEN \ ADC Enable
+ $40 constant ADCSRA_ADSC \ ADC Start Conversion
+ $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
+ $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
+ $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
+ $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
+&123 constant ADCSRB \ The ADC Control and Status register B
+ $40 constant ADCSRB_ACME \
+ $07 constant ADCSRB_ADTS \ ADC Auto Trigger Source bits
+&126 constant DIDR0 \ Digital Input Disable Register
+ $20 constant DIDR0_ADC5D \
+ $10 constant DIDR0_ADC4D \
+ $08 constant DIDR0_ADC3D \
+ $04 constant DIDR0_ADC2D \
+ $02 constant DIDR0_ADC1D \
+ $01 constant DIDR0_ADC0D \
+\ ANALOG_COMPARATOR
+&80 constant ACSR \ Analog Comparator Control And Status Register
+ $80 constant ACSR_ACD \ Analog Comparator Disable
+ $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
+ $20 constant ACSR_ACO \ Analog Compare Output
+ $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
+ $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
+ $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
+ $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
+&127 constant DIDR1 \ Digital Input Disable Register 1
+ $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
+ $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
+\ PORTB
+&37 constant PORTB \ Port B Data Register
+&36 constant DDRB \ Port B Data Direction Register
+&35 constant PINB \ Port B Input Pins
+\ PORTC
+&40 constant PORTC \ Port C Data Register
+&39 constant DDRC \ Port C Data Direction Register
+&38 constant PINC \ Port C Input Pins
+\ PORTD
+&43 constant PORTD \ Port D Data Register
+&42 constant DDRD \ Port D Data Direction Register
+&41 constant PIND \ Port D Input Pins
+\ TIMER_COUNTER_0
+&72 constant OCR0B \ Timer/Counter0 Output Compare Register
+&71 constant OCR0A \ Timer/Counter0 Output Compare Register
+&70 constant TCNT0 \ Timer/Counter0
+&69 constant TCCR0B \ Timer/Counter Control Register B
+ $80 constant TCCR0B_FOC0A \ Force Output Compare A
+ $40 constant TCCR0B_FOC0B \ Force Output Compare B
+ $08 constant TCCR0B_WGM02 \
+ $07 constant TCCR0B_CS0 \ Clock Select
+&68 constant TCCR0A \ Timer/Counter Control Register A
+ $C0 constant TCCR0A_COM0A \ Compare Output Mode, Phase Correct PWM Mode
+ $30 constant TCCR0A_COM0B \ Compare Output Mode, Fast PWm
+ $03 constant TCCR0A_WGM0 \ Waveform Generation Mode
+&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
+ $04 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare Match B Interrupt Enable
+ $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match A Interrupt Enable
+ $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
+&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
+ $04 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare Flag 0B
+ $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0A
+ $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
+\ EXTERNAL_INTERRUPT
+&105 constant EICRA \ External Interrupt Control Register
+ $0C constant EICRA_ISC1 \ External Interrupt Sense Control 1 Bits
+ $03 constant EICRA_ISC0 \ External Interrupt Sense Control 0 Bits
+&61 constant EIMSK \ External Interrupt Mask Register
+ $03 constant EIMSK_INT \ External Interrupt Request 1 Enable
+&60 constant EIFR \ External Interrupt Flag Register
+ $03 constant EIFR_INTF \ External Interrupt Flags
+&104 constant PCICR \ Pin Change Interrupt Control Register
+ $07 constant PCICR_PCIE \ Pin Change Interrupt Enables
+&109 constant PCMSK2 \ Pin Change Mask Register 2
+ $FF constant PCMSK2_PCINT \ Pin Change Enable Masks
+&108 constant PCMSK1 \ Pin Change Mask Register 1
+ $7F constant PCMSK1_PCINT \ Pin Change Enable Masks
+&107 constant PCMSK0 \ Pin Change Mask Register 0
+ $FF constant PCMSK0_PCINT \ Pin Change Enable Masks
+&59 constant PCIFR \ Pin Change Interrupt Flag Register
+ $07 constant PCIFR_PCIF \ Pin Change Interrupt Flags
+\ SPI
+&78 constant SPDR \ SPI Data Register
+&77 constant SPSR \ SPI Status Register
+ $80 constant SPSR_SPIF \ SPI Interrupt Flag
+ $40 constant SPSR_WCOL \ Write Collision Flag
+ $01 constant SPSR_SPI2X \ Double SPI Speed Bit
+&76 constant SPCR \ SPI Control Register
+ $80 constant SPCR_SPIE \ SPI Interrupt Enable
+ $40 constant SPCR_SPE \ SPI Enable
+ $20 constant SPCR_DORD \ Data Order
+ $10 constant SPCR_MSTR \ Master/Slave Select
+ $08 constant SPCR_CPOL \ Clock polarity
+ $04 constant SPCR_CPHA \ Clock Phase
+ $03 constant SPCR_SPR \ SPI Clock Rate Selects
+\ WATCHDOG
+&96 constant WDTCSR \ Watchdog Timer Control Register
+ $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Flag
+ $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Enable
+ $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
+ $10 constant WDTCSR_WDCE \ Watchdog Change Enable
+ $08 constant WDTCSR_WDE \ Watch Dog Enable
+\ CPU
+&100 constant PRR \ Power Reduction Register
+ $80 constant PRR_PRTWI \ Power Reduction TWI
+ $40 constant PRR_PRTIM2 \ Power Reduction Timer/Counter2
+ $20 constant PRR_PRTIM0 \ Power Reduction Timer/Counter0
+ $08 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
+ $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
+ $02 constant PRR_PRUSART0 \ Power Reduction USART
+ $01 constant PRR_PRADC \ Power Reduction ADC
+&102 constant OSCCAL \ Oscillator Calibration Value
+&97 constant CLKPR \ Clock Prescale Register
+ $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable
+ $0F constant CLKPR_CLKPS \ Clock Prescaler Select Bits
+&95 constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ $08 constant SREG_V \ Two's Complement Overflow Flag
+ $04 constant SREG_N \ Negative Flag
+ $02 constant SREG_Z \ Zero Flag
+ $01 constant SREG_C \ Carry Flag
+&93 constant SP \ Stack Pointer
+&87 constant SPMCSR \ Store Program Memory Control and Status Register
+ $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCSR_RWWSB \ Read-While-Write Section Busy
+ $10 constant SPMCSR_RWWSRE \ Read-While-Write section read enable
+ $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
+ $04 constant SPMCSR_PGWRT \ Page Write
+ $02 constant SPMCSR_PGERS \ Page Erase
+ $01 constant SPMCSR_SELFPRGEN \ Self Programming Enable
+&85 constant MCUCR \ MCU Control Register
+ $40 constant MCUCR_BODS \ BOD Sleep
+ $20 constant MCUCR_BODSE \ BOD Sleep Enable
+ $10 constant MCUCR_PUD \
+ $02 constant MCUCR_IVSEL \
+ $01 constant MCUCR_IVCE \
+&84 constant MCUSR \ MCU Status Register
+ $08 constant MCUSR_WDRF \ Watchdog Reset Flag
+ $04 constant MCUSR_BORF \ Brown-out Reset Flag
+ $02 constant MCUSR_EXTRF \ External Reset Flag
+ $01 constant MCUSR_PORF \ Power-on reset flag
+&83 constant SMCR \ Sleep Mode Control Register
+ $0E constant SMCR_SM \ Sleep Mode Select Bits
+ $01 constant SMCR_SE \ Sleep Enable
+&75 constant GPIOR2 \ General Purpose I/O Register 2
+&74 constant GPIOR1 \ General Purpose I/O Register 1
+&62 constant GPIOR0 \ General Purpose I/O Register 0
+\ EEPROM
+&65 constant EEAR \ EEPROM Address Register Bytes
+&64 constant EEDR \ EEPROM Data Register
+&63 constant EECR \ EEPROM Control Register
+ $30 constant EECR_EEPM \ EEPROM Programming Mode Bits
+ $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
+ $04 constant EECR_EEMPE \ EEPROM Master Write Enable
+ $02 constant EECR_EEPE \ EEPROM Write Enable
+ $01 constant EECR_EERE \ EEPROM Read Enable
+
+\ Interrupts
+&2 constant INT0Addr \ External Interrupt Request 0
+&4 constant INT1Addr \ External Interrupt Request 1
+&6 constant PCINT0Addr \ Pin Change Interrupt Request 0
+&8 constant PCINT1Addr \ Pin Change Interrupt Request 0
+&10 constant PCINT2Addr \ Pin Change Interrupt Request 1
+&12 constant WDTAddr \ Watchdog Time-out Interrupt
+&14 constant TIMER2_COMPAAddr \ Timer/Counter2 Compare Match A
+&16 constant TIMER2_COMPBAddr \ Timer/Counter2 Compare Match A
+&18 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
+&20 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+&22 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
+&24 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
+&26 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+&28 constant TIMER0_COMPAAddr \ TimerCounter0 Compare Match A
+&30 constant TIMER0_COMPBAddr \ TimerCounter0 Compare Match B
+&32 constant TIMER0_OVFAddr \ Timer/Couner0 Overflow
+&34 constant SPI__STCAddr \ SPI Serial Transfer Complete
+&36 constant USART__RXAddr \ USART Rx Complete
+&38 constant USART__UDREAddr \ USART, Data Register Empty
+&40 constant USART__TXAddr \ USART Tx Complete
+&42 constant ADCAddr \ ADC Conversion Complete
+&44 constant EE_READYAddr \ EEPROM Ready
+&46 constant ANALOG_COMPAddr \ Analog Comparator
+&48 constant TWIAddr \ Two-wire Serial Interface
+&50 constant SPM_ReadyAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/atmega328p/device.asm b/amforth-6.5/avr8/devices/atmega328p/device.asm
new file mode 100644
index 0000000..a13fda6
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega328p/device.asm
@@ -0,0 +1,107 @@
+; Partname: ATmega328P
+; generated automatically, do not edit
+
+.nolist
+ .include "m328Pdef.inc"
+.list
+
+.equ ramstart = 256
+.equ CELLSIZE = 2
+.macro readflashcell
+ lsl zl
+ rol zh
+ lpm @0, Z+
+ lpm @1, Z+
+.endmacro
+.macro writeflashcell
+ lsl zl
+ rol zh
+.endmacro
+.set WANT_USART0 = 0
+.set WANT_TWI = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_TIMER_COUNTER_2 = 0
+.set WANT_AD_CONVERTER = 0
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_PORTB = 0
+.set WANT_PORTC = 0
+.set WANT_PORTD = 0
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_SPI = 0
+.set WANT_WATCHDOG = 0
+.set WANT_CPU = 0
+.set WANT_EEPROM = 0
+.equ intvecsize = 2 ; please verify; flash size: 32768 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.org 2
+ rcall isr ; External Interrupt Request 0
+.org 4
+ rcall isr ; External Interrupt Request 1
+.org 6
+ rcall isr ; Pin Change Interrupt Request 0
+.org 8
+ rcall isr ; Pin Change Interrupt Request 0
+.org 10
+ rcall isr ; Pin Change Interrupt Request 1
+.org 12
+ rcall isr ; Watchdog Time-out Interrupt
+.org 14
+ rcall isr ; Timer/Counter2 Compare Match A
+.org 16
+ rcall isr ; Timer/Counter2 Compare Match A
+.org 18
+ rcall isr ; Timer/Counter2 Overflow
+.org 20
+ rcall isr ; Timer/Counter1 Capture Event
+.org 22
+ rcall isr ; Timer/Counter1 Compare Match A
+.org 24
+ rcall isr ; Timer/Counter1 Compare Match B
+.org 26
+ rcall isr ; Timer/Counter1 Overflow
+.org 28
+ rcall isr ; TimerCounter0 Compare Match A
+.org 30
+ rcall isr ; TimerCounter0 Compare Match B
+.org 32
+ rcall isr ; Timer/Couner0 Overflow
+.org 34
+ rcall isr ; SPI Serial Transfer Complete
+.org 36
+ rcall isr ; USART Rx Complete
+.org 38
+ rcall isr ; USART, Data Register Empty
+.org 40
+ rcall isr ; USART Tx Complete
+.org 42
+ rcall isr ; ADC Conversion Complete
+.org 44
+ rcall isr ; EEPROM Ready
+.org 46
+ rcall isr ; Analog Comparator
+.org 48
+ rcall isr ; Two-wire Serial Interface
+.org 50
+ rcall isr ; Store Program Memory Read
+.equ INTVECTORS = 26
+.nooverlap
+
+; compatability layer (maybe empty)
+.equ SPMEN = SELFPRGEN
+
+; controller data area, environment query mcu-info
+mcu_info:
+mcu_ramsize:
+ .dw 2048
+mcu_eepromsize:
+ .dw 1024
+mcu_maxdp:
+ .dw 28672
+mcu_numints:
+ .dw 26
+mcu_name:
+ .dw 10
+ .db "ATmega328P"
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega328p/device.inc b/amforth-6.5/avr8/devices/atmega328p/device.inc
new file mode 100644
index 0000000..4e99429
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega328p/device.inc
@@ -0,0 +1,996 @@
+; Partname: ATmega328P
+; generated automatically, no not edit
+
+.if WANT_USART0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR0:
+ .dw $ff04
+ .db "UDR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR0
+XT_UDR0:
+ .dw PFA_DOVARIABLE
+PFA_UDR0:
+ .dw 198
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR0A:
+ .dw $ff06
+ .db "UCSR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0A
+XT_UCSR0A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0A:
+ .dw 192
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR0B:
+ .dw $ff06
+ .db "UCSR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0B
+XT_UCSR0B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0B:
+ .dw 193
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR0C:
+ .dw $ff06
+ .db "UCSR0C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0C
+XT_UCSR0C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0C:
+ .dw 194
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Bytes
+VE_UBRR0:
+ .dw $ff05
+ .db "UBRR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR0
+XT_UBRR0:
+ .dw PFA_DOVARIABLE
+PFA_UBRR0:
+ .dw 196
+
+.endif
+.if WANT_TWI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; TWI (Slave) Address Mask Register
+VE_TWAMR:
+ .dw $ff05
+ .db "TWAMR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWAMR
+XT_TWAMR:
+ .dw PFA_DOVARIABLE
+PFA_TWAMR:
+ .dw 189
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Bit Rate register
+VE_TWBR:
+ .dw $ff04
+ .db "TWBR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWBR
+XT_TWBR:
+ .dw PFA_DOVARIABLE
+PFA_TWBR:
+ .dw 184
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Control Register
+VE_TWCR:
+ .dw $ff04
+ .db "TWCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWCR
+XT_TWCR:
+ .dw PFA_DOVARIABLE
+PFA_TWCR:
+ .dw 188
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Status Register
+VE_TWSR:
+ .dw $ff04
+ .db "TWSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWSR
+XT_TWSR:
+ .dw PFA_DOVARIABLE
+PFA_TWSR:
+ .dw 185
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Data register
+VE_TWDR:
+ .dw $ff04
+ .db "TWDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWDR
+XT_TWDR:
+ .dw PFA_DOVARIABLE
+PFA_TWDR:
+ .dw 187
+; ( -- addr ) System Constant
+; R( -- )
+; TWI (Slave) Address register
+VE_TWAR:
+ .dw $ff04
+ .db "TWAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWAR
+XT_TWAR:
+ .dw PFA_DOVARIABLE
+PFA_TWAR:
+ .dw 186
+
+.endif
+.if WANT_TIMER_COUNTER_1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Mask Register
+VE_TIMSK1:
+ .dw $ff06
+ .db "TIMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK1
+XT_TIMSK1:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK1:
+ .dw 111
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Flag register
+VE_TIFR1:
+ .dw $ff05
+ .db "TIFR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR1
+XT_TIFR1:
+ .dw PFA_DOVARIABLE
+PFA_TIFR1:
+ .dw 54
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw 128
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw 129
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register C
+VE_TCCR1C:
+ .dw $ff06
+ .db "TCCR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1C
+XT_TCCR1C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1C:
+ .dw 130
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Bytes
+VE_TCNT1:
+ .dw $ff05
+ .db "TCNT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1
+XT_TCNT1:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1:
+ .dw 132
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register Bytes
+VE_OCR1A:
+ .dw $ff05
+ .db "OCR1A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1A
+XT_OCR1A:
+ .dw PFA_DOVARIABLE
+PFA_OCR1A:
+ .dw 136
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register Bytes
+VE_OCR1B:
+ .dw $ff05
+ .db "OCR1B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1B
+XT_OCR1B:
+ .dw PFA_DOVARIABLE
+PFA_OCR1B:
+ .dw 138
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Bytes
+VE_ICR1:
+ .dw $ff04
+ .db "ICR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1
+XT_ICR1:
+ .dw PFA_DOVARIABLE
+PFA_ICR1:
+ .dw 134
+; ( -- addr ) System Constant
+; R( -- )
+; General Timer/Counter Control Register
+VE_GTCCR:
+ .dw $ff05
+ .db "GTCCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GTCCR
+XT_GTCCR:
+ .dw PFA_DOVARIABLE
+PFA_GTCCR:
+ .dw 67
+
+.endif
+.if WANT_TIMER_COUNTER_2 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Mask register
+VE_TIMSK2:
+ .dw $ff06
+ .db "TIMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK2
+XT_TIMSK2:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK2:
+ .dw 112
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Flag Register
+VE_TIFR2:
+ .dw $ff05
+ .db "TIFR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR2
+XT_TIFR2:
+ .dw PFA_DOVARIABLE
+PFA_TIFR2:
+ .dw 55
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register A
+VE_TCCR2A:
+ .dw $ff06
+ .db "TCCR2A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2A
+XT_TCCR2A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2A:
+ .dw 176
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register B
+VE_TCCR2B:
+ .dw $ff06
+ .db "TCCR2B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2B
+XT_TCCR2B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2B:
+ .dw 177
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2
+VE_TCNT2:
+ .dw $ff05
+ .db "TCNT2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT2
+XT_TCNT2:
+ .dw PFA_DOVARIABLE
+PFA_TCNT2:
+ .dw 178
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register B
+VE_OCR2B:
+ .dw $ff05
+ .db "OCR2B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2B
+XT_OCR2B:
+ .dw PFA_DOVARIABLE
+PFA_OCR2B:
+ .dw 180
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register A
+VE_OCR2A:
+ .dw $ff05
+ .db "OCR2A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2A
+XT_OCR2A:
+ .dw PFA_DOVARIABLE
+PFA_OCR2A:
+ .dw 179
+; ( -- addr ) System Constant
+; R( -- )
+; Asynchronous Status Register
+VE_ASSR:
+ .dw $ff04
+ .db "ASSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ASSR
+XT_ASSR:
+ .dw PFA_DOVARIABLE
+PFA_ASSR:
+ .dw 182
+
+.endif
+.if WANT_AD_CONVERTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC multiplexer Selection Register
+VE_ADMUX:
+ .dw $ff05
+ .db "ADMUX",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADMUX
+XT_ADMUX:
+ .dw PFA_DOVARIABLE
+PFA_ADMUX:
+ .dw 124
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register Bytes
+VE_ADC:
+ .dw $ff03
+ .db "ADC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADC
+XT_ADC:
+ .dw PFA_DOVARIABLE
+PFA_ADC:
+ .dw 120
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register A
+VE_ADCSRA:
+ .dw $ff06
+ .db "ADCSRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRA
+XT_ADCSRA:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRA:
+ .dw 122
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register B
+VE_ADCSRB:
+ .dw $ff06
+ .db "ADCSRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRB
+XT_ADCSRB:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRB:
+ .dw 123
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register
+VE_DIDR0:
+ .dw $ff05
+ .db "DIDR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR0
+XT_DIDR0:
+ .dw PFA_DOVARIABLE
+PFA_DIDR0:
+ .dw 126
+
+.endif
+.if WANT_ANALOG_COMPARATOR == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Control And Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw 80
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 1
+VE_DIDR1:
+ .dw $ff05
+ .db "DIDR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR1
+XT_DIDR1:
+ .dw PFA_DOVARIABLE
+PFA_DIDR1:
+ .dw 127
+
+.endif
+.if WANT_PORTB == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw 37
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw 36
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw 35
+
+.endif
+.if WANT_PORTC == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Register
+VE_PORTC:
+ .dw $ff05
+ .db "PORTC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTC
+XT_PORTC:
+ .dw PFA_DOVARIABLE
+PFA_PORTC:
+ .dw 40
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Direction Register
+VE_DDRC:
+ .dw $ff04
+ .db "DDRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRC
+XT_DDRC:
+ .dw PFA_DOVARIABLE
+PFA_DDRC:
+ .dw 39
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Input Pins
+VE_PINC:
+ .dw $ff04
+ .db "PINC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINC
+XT_PINC:
+ .dw PFA_DOVARIABLE
+PFA_PINC:
+ .dw 38
+
+.endif
+.if WANT_PORTD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw 43
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw 42
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw 41
+
+.endif
+.if WANT_TIMER_COUNTER_0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0B:
+ .dw $ff05
+ .db "OCR0B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0B
+XT_OCR0B:
+ .dw PFA_DOVARIABLE
+PFA_OCR0B:
+ .dw 72
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0A:
+ .dw $ff05
+ .db "OCR0A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0A
+XT_OCR0A:
+ .dw PFA_DOVARIABLE
+PFA_OCR0A:
+ .dw 71
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw 70
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register B
+VE_TCCR0B:
+ .dw $ff06
+ .db "TCCR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0B
+XT_TCCR0B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0B:
+ .dw 69
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register A
+VE_TCCR0A:
+ .dw $ff06
+ .db "TCCR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0A
+XT_TCCR0A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0A:
+ .dw 68
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Mask Register
+VE_TIMSK0:
+ .dw $ff06
+ .db "TIMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK0
+XT_TIMSK0:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK0:
+ .dw 110
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Flag register
+VE_TIFR0:
+ .dw $ff05
+ .db "TIFR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR0
+XT_TIFR0:
+ .dw PFA_DOVARIABLE
+PFA_TIFR0:
+ .dw 53
+
+.endif
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register
+VE_EICRA:
+ .dw $ff05
+ .db "EICRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRA
+XT_EICRA:
+ .dw PFA_DOVARIABLE
+PFA_EICRA:
+ .dw 105
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Mask Register
+VE_EIMSK:
+ .dw $ff05
+ .db "EIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIMSK
+XT_EIMSK:
+ .dw PFA_DOVARIABLE
+PFA_EIMSK:
+ .dw 61
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Flag Register
+VE_EIFR:
+ .dw $ff04
+ .db "EIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIFR
+XT_EIFR:
+ .dw PFA_DOVARIABLE
+PFA_EIFR:
+ .dw 60
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Interrupt Control Register
+VE_PCICR:
+ .dw $ff05
+ .db "PCICR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCICR
+XT_PCICR:
+ .dw PFA_DOVARIABLE
+PFA_PCICR:
+ .dw 104
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 2
+VE_PCMSK2:
+ .dw $ff06
+ .db "PCMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK2
+XT_PCMSK2:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK2:
+ .dw 109
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 1
+VE_PCMSK1:
+ .dw $ff06
+ .db "PCMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK1
+XT_PCMSK1:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK1:
+ .dw 108
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 0
+VE_PCMSK0:
+ .dw $ff06
+ .db "PCMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK0
+XT_PCMSK0:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK0:
+ .dw 107
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Interrupt Flag Register
+VE_PCIFR:
+ .dw $ff05
+ .db "PCIFR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCIFR
+XT_PCIFR:
+ .dw PFA_DOVARIABLE
+PFA_PCIFR:
+ .dw 59
+
+.endif
+.if WANT_SPI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR:
+ .dw $ff04
+ .db "SPDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR
+XT_SPDR:
+ .dw PFA_DOVARIABLE
+PFA_SPDR:
+ .dw 78
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR:
+ .dw $ff04
+ .db "SPSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR
+XT_SPSR:
+ .dw PFA_DOVARIABLE
+PFA_SPSR:
+ .dw 77
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR:
+ .dw $ff04
+ .db "SPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR
+XT_SPCR:
+ .dw PFA_DOVARIABLE
+PFA_SPCR:
+ .dw 76
+
+.endif
+.if WANT_WATCHDOG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCSR:
+ .dw $ff06
+ .db "WDTCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCSR
+XT_WDTCSR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCSR:
+ .dw 96
+
+.endif
+.if WANT_CPU == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register
+VE_PRR:
+ .dw $ff03
+ .db "PRR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR
+XT_PRR:
+ .dw PFA_DOVARIABLE
+PFA_PRR:
+ .dw 100
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Calibration Value
+VE_OSCCAL:
+ .dw $ff06
+ .db "OSCCAL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSCCAL
+XT_OSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_OSCCAL:
+ .dw 102
+; ( -- addr ) System Constant
+; R( -- )
+; Clock Prescale Register
+VE_CLKPR:
+ .dw $ff05
+ .db "CLKPR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKPR
+XT_CLKPR:
+ .dw PFA_DOVARIABLE
+PFA_CLKPR:
+ .dw 97
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw 95
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer
+VE_SP:
+ .dw $ff02
+ .db "SP"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SP
+XT_SP:
+ .dw PFA_DOVARIABLE
+PFA_SP:
+ .dw 93
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control and Status Register
+VE_SPMCSR:
+ .dw $ff06
+ .db "SPMCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCSR
+XT_SPMCSR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCSR:
+ .dw 87
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw 85
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Status Register
+VE_MCUSR:
+ .dw $ff05
+ .db "MCUSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUSR
+XT_MCUSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUSR:
+ .dw 84
+; ( -- addr ) System Constant
+; R( -- )
+; Sleep Mode Control Register
+VE_SMCR:
+ .dw $ff04
+ .db "SMCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SMCR
+XT_SMCR:
+ .dw PFA_DOVARIABLE
+PFA_SMCR:
+ .dw 83
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose I/O Register 2
+VE_GPIOR2:
+ .dw $ff06
+ .db "GPIOR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR2
+XT_GPIOR2:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR2:
+ .dw 75
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose I/O Register 1
+VE_GPIOR1:
+ .dw $ff06
+ .db "GPIOR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR1
+XT_GPIOR1:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR1:
+ .dw 74
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose I/O Register 0
+VE_GPIOR0:
+ .dw $ff06
+ .db "GPIOR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR0
+XT_GPIOR0:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR0:
+ .dw 62
+
+.endif
+.if WANT_EEPROM == 1
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Address Register Bytes
+VE_EEAR:
+ .dw $ff04
+ .db "EEAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEAR
+XT_EEAR:
+ .dw PFA_DOVARIABLE
+PFA_EEAR:
+ .dw 65
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw 64
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw 63
+
+.endif
diff --git a/amforth-6.5/avr8/devices/atmega328p/device.py b/amforth-6.5/avr8/devices/atmega328p/device.py
new file mode 100644
index 0000000..cd93cb9
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega328p/device.py
@@ -0,0 +1,324 @@
+# Generated Automatically
+
+# Partname ATmega328P
+
+MCUREGS = {
+# Interrupt Vectors
+ 'INT0Addr' : '#2', # External Interrupt Request 0
+ 'INT1Addr' : '#4', # External Interrupt Request 1
+ 'PCINT0Addr' : '#6', # Pin Change Interrupt Request 0
+ 'PCINT1Addr' : '#8', # Pin Change Interrupt Request 0
+ 'PCINT2Addr' : '#10', # Pin Change Interrupt Request 1
+ 'WDTAddr' : '#12', # Watchdog Time-out Interrupt
+ 'TIMER2_COMPAAddr' : '#14', # Timer/Counter2 Compare Match A
+ 'TIMER2_COMPBAddr' : '#16', # Timer/Counter2 Compare Match A
+ 'TIMER2_OVFAddr' : '#18', # Timer/Counter2 Overflow
+ 'TIMER1_CAPTAddr' : '#20', # Timer/Counter1 Capture Event
+ 'TIMER1_COMPAAddr' : '#22', # Timer/Counter1 Compare Match A
+ 'TIMER1_COMPBAddr' : '#24', # Timer/Counter1 Compare Match B
+ 'TIMER1_OVFAddr' : '#26', # Timer/Counter1 Overflow
+ 'TIMER0_COMPAAddr' : '#28', # TimerCounter0 Compare Match A
+ 'TIMER0_COMPBAddr' : '#30', # TimerCounter0 Compare Match B
+ 'TIMER0_OVFAddr' : '#32', # Timer/Couner0 Overflow
+ 'SPI_STCAddr' : '#34', # SPI Serial Transfer Complete
+ 'USART_RXAddr' : '#36', # USART Rx Complete
+ 'USART_UDREAddr' : '#38', # USART, Data Register Empty
+ 'USART_TXAddr' : '#40', # USART Tx Complete
+ 'ADCAddr' : '#42', # ADC Conversion Complete
+ 'EE_READYAddr' : '#44', # EEPROM Ready
+ 'ANALOG_COMPAddr' : '#46', # Analog Comparator
+ 'TWIAddr' : '#48', # Two-wire Serial Interface
+ 'SPM_ReadyAddr' : '#50', # Store Program Memory Read
+
+# Module USART0
+ 'UDR0' : '$c6', # USART I/O Data Register
+ 'UCSR0A' : '$c0', # USART Control and Status Regis
+ 'UCSR0A_RXC0': '$80', # USART Receive Complete
+ 'UCSR0A_TXC0': '$40', # USART Transmitt Complete
+ 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
+ 'UCSR0A_FE0': '$10', # Framing Error
+ 'UCSR0A_DOR0': '$8', # Data overRun
+ 'UCSR0A_UPE0': '$4', # Parity Error
+ 'UCSR0A_U2X0': '$2', # Double the USART transmission
+ 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
+ 'UCSR0B' : '$c1', # USART Control and Status Regis
+ 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
+ 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
+ 'UCSR0B_UDRIE0': '$20', # USART Data register Empty Inte
+ 'UCSR0B_RXEN0': '$10', # Receiver Enable
+ 'UCSR0B_TXEN0': '$8', # Transmitter Enable
+ 'UCSR0B_UCSZ02': '$4', # Character Size
+ 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
+ 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
+ 'UCSR0C' : '$c2', # USART Control and Status Regis
+ 'UCSR0C_UMSEL0': '$c0', # USART Mode Select
+ 'UCSR0C_UPM0': '$30', # Parity Mode Bits
+ 'UCSR0C_USBS0': '$8', # Stop Bit Select
+ 'UCSR0C_UCSZ0': '$6', # Character Size
+ 'UCSR0C_UCPOL0': '$1', # Clock Polarity
+ 'UBRR0' : '$c4', # USART Baud Rate Register Byte
+
+# Module TWI
+ 'TWAMR' : '$bd', # TWI (Slave) Address Mask Regis
+ 'TWAMR_TWAM': '$fe', #
+ 'TWBR' : '$b8', # TWI Bit Rate register
+ 'TWCR' : '$bc', # TWI Control Register
+ 'TWCR_TWINT': '$80', # TWI Interrupt Flag
+ 'TWCR_TWEA': '$40', # TWI Enable Acknowledge Bit
+ 'TWCR_TWSTA': '$20', # TWI Start Condition Bit
+ 'TWCR_TWSTO': '$10', # TWI Stop Condition Bit
+ 'TWCR_TWWC': '$8', # TWI Write Collition Flag
+ 'TWCR_TWEN': '$4', # TWI Enable Bit
+ 'TWCR_TWIE': '$1', # TWI Interrupt Enable
+ 'TWSR' : '$b9', # TWI Status Register
+ 'TWSR_TWS': '$f8', # TWI Status
+ 'TWSR_TWPS': '$3', # TWI Prescaler
+ 'TWDR' : '$bb', # TWI Data register
+ 'TWAR' : '$ba', # TWI (Slave) Address register
+ 'TWAR_TWA': '$fe', # TWI (Slave) Address register B
+ 'TWAR_TWGCE': '$1', # TWI General Call Recognition E
+
+# Module TIMER_COUNTER_1
+ 'TIMSK1' : '$6f', # Timer/Counter Interrupt Mask R
+ 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
+ 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output CompareB
+ 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output CompareA
+ 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
+ 'TIFR1' : '$36', # Timer/Counter Interrupt Flag r
+ 'TIFR1_ICF1': '$20', # Input Capture Flag 1
+ 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
+ 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
+ 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
+ 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
+ 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
+ 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
+ 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
+ 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
+ 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
+ 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
+ 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
+ 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
+ 'TCCR1C' : '$82', # Timer/Counter1 Control Registe
+ 'TCCR1C_FOC1A': '$80', #
+ 'TCCR1C_FOC1B': '$40', #
+ 'TCNT1' : '$84', # Timer/Counter1 Bytes
+ 'OCR1A' : '$88', # Timer/Counter1 Output Compare
+ 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
+ 'ICR1' : '$86', # Timer/Counter1 Input Capture R
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSRSYNC': '$1', # Prescaler Reset Timer/Counter1
+
+# Module TIMER_COUNTER_2
+ 'TIMSK2' : '$70', # Timer/Counter Interrupt Mask r
+ 'TIMSK2_OCIE2B': '$4', # Timer/Counter2 Output Compare
+ 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
+ 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
+ 'TIFR2' : '$37', # Timer/Counter Interrupt Flag R
+ 'TIFR2_OCF2B': '$4', # Output Compare Flag 2B
+ 'TIFR2_OCF2A': '$2', # Output Compare Flag 2A
+ 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
+ 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
+ 'TCCR2A_COM2A': '$c0', # Compare Output Mode bits
+ 'TCCR2A_COM2B': '$30', # Compare Output Mode bits
+ 'TCCR2A_WGM2': '$3', # Waveform Genration Mode
+ 'TCCR2B' : '$b1', # Timer/Counter2 Control Registe
+ 'TCCR2B_FOC2A': '$80', # Force Output Compare A
+ 'TCCR2B_FOC2B': '$40', # Force Output Compare B
+ 'TCCR2B_WGM22': '$8', # Waveform Generation Mode
+ 'TCCR2B_CS2': '$7', # Clock Select bits
+ 'TCNT2' : '$b2', # Timer/Counter2
+ 'OCR2B' : '$b4', # Timer/Counter2 Output Compare
+ 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
+ 'ASSR' : '$b6', # Asynchronous Status Register
+ 'ASSR_EXCLK': '$40', # Enable External Clock Input
+ 'ASSR_AS2': '$20', # Asynchronous Timer/Counter2
+ 'ASSR_TCN2UB': '$10', # Timer/Counter2 Update Busy
+ 'ASSR_OCR2AUB': '$8', # Output Compare Register2 Updat
+ 'ASSR_OCR2BUB': '$4', # Output Compare Register 2 Upda
+ 'ASSR_TCR2AUB': '$2', # Timer/Counter Control Register
+ 'ASSR_TCR2BUB': '$1', # Timer/Counter Control Register
+ 'GTCCR' : '$43', # General Timer Counter Control
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSRASY': '$2', # Prescaler Reset Timer/Counter2
+
+# Module AD_CONVERTER
+ 'ADMUX' : '$7c', # The ADC multiplexer Selection
+ 'ADMUX_REFS': '$c0', # Reference Selection Bits
+ 'ADMUX_ADLAR': '$20', # Left Adjust Result
+ 'ADMUX_MUX': '$f', # Analog Channel and Gain Select
+ 'ADC' : '$78', # ADC Data Register Bytes
+ 'ADCSRA' : '$7a', # The ADC Control and Status reg
+ 'ADCSRA_ADEN': '$80', # ADC Enable
+ 'ADCSRA_ADSC': '$40', # ADC Start Conversion
+ 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
+ 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
+ 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
+ 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
+ 'ADCSRB' : '$7b', # The ADC Control and Status reg
+ 'ADCSRB_ACME': '$40', #
+ 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Source bits
+ 'DIDR0' : '$7e', # Digital Input Disable Register
+ 'DIDR0_ADC5D': '$20', #
+ 'DIDR0_ADC4D': '$10', #
+ 'DIDR0_ADC3D': '$8', #
+ 'DIDR0_ADC2D': '$4', #
+ 'DIDR0_ADC1D': '$2', #
+ 'DIDR0_ADC0D': '$1', #
+
+# Module ANALOG_COMPARATOR
+ 'ACSR' : '$50', # Analog Comparator Control And
+ 'ACSR_ACD': '$80', # Analog Comparator Disable
+ 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
+ 'ACSR_ACO': '$20', # Analog Compare Output
+ 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
+ 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
+ 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
+ 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
+ 'DIDR1' : '$7f', # Digital Input Disable Register
+ 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
+ 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
+
+# Module PORTB
+ 'PORTB' : '$25', # Port B Data Register
+ 'DDRB' : '$24', # Port B Data Direction Register
+ 'PINB' : '$23', # Port B Input Pins
+
+# Module PORTC
+ 'PORTC' : '$28', # Port C Data Register
+ 'DDRC' : '$27', # Port C Data Direction Register
+ 'PINC' : '$26', # Port C Input Pins
+
+# Module PORTD
+ 'PORTD' : '$2b', # Port D Data Register
+ 'DDRD' : '$2a', # Port D Data Direction Register
+ 'PIND' : '$29', # Port D Input Pins
+
+# Module TIMER_COUNTER_0
+ 'OCR0B' : '$48', # Timer/Counter0 Output Compare
+ 'OCR0A' : '$47', # Timer/Counter0 Output Compare
+ 'TCNT0' : '$46', # Timer/Counter0
+ 'TCCR0B' : '$45', # Timer/Counter Control Register
+ 'TCCR0B_FOC0A': '$80', # Force Output Compare A
+ 'TCCR0B_FOC0B': '$40', # Force Output Compare B
+ 'TCCR0B_WGM02': '$8', #
+ 'TCCR0B_CS0': '$7', # Clock Select
+ 'TCCR0A' : '$44', # Timer/Counter Control Registe
+ 'TCCR0A_COM0A': '$c0', # Compare Output Mode, Phase Cor
+ 'TCCR0A_COM0B': '$30', # Compare Output Mode, Fast PWm
+ 'TCCR0A_WGM0': '$3', # Waveform Generation Mode
+ 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
+ 'TIMSK0_OCIE0B': '$4', # Timer/Counter0 Output Compare
+ 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
+ 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
+ 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
+ 'TIFR0_OCF0B': '$4', # Timer/Counter0 Output Compare
+ 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
+ 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSRSYNC': '$1', # Prescaler Reset Timer/Counter1
+
+# Module EXTERNAL_INTERRUPT
+ 'EICRA' : '$69', # External Interrupt Control Reg
+ 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
+ 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
+ 'EIMSK' : '$3d', # External Interrupt Mask Regist
+ 'EIMSK_INT': '$3', # External Interrupt Request 1 E
+ 'EIFR' : '$3c', # External Interrupt Flag Regist
+ 'EIFR_INTF': '$3', # External Interrupt Flags
+ 'PCICR' : '$68', # Pin Change Interrupt Control R
+ 'PCICR_PCIE': '$7', # Pin Change Interrupt Enables
+ 'PCMSK2' : '$6d', # Pin Change Mask Register 2
+ 'PCMSK2_PCINT': '$ff', # Pin Change Enable Masks
+ 'PCMSK1' : '$6c', # Pin Change Mask Register 1
+ 'PCMSK1_PCINT': '$7f', # Pin Change Enable Masks
+ 'PCMSK0' : '$6b', # Pin Change Mask Register 0
+ 'PCMSK0_PCINT': '$ff', # Pin Change Enable Masks
+ 'PCIFR' : '$3b', # Pin Change Interrupt Flag Regi
+ 'PCIFR_PCIF': '$7', # Pin Change Interrupt Flags
+
+# Module SPI
+ 'SPDR' : '$4e', # SPI Data Register
+ 'SPSR' : '$4d', # SPI Status Register
+ 'SPSR_SPIF': '$80', # SPI Interrupt Flag
+ 'SPSR_WCOL': '$40', # Write Collision Flag
+ 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
+ 'SPCR' : '$4c', # SPI Control Register
+ 'SPCR_SPIE': '$80', # SPI Interrupt Enable
+ 'SPCR_SPE': '$40', # SPI Enable
+ 'SPCR_DORD': '$20', # Data Order
+ 'SPCR_MSTR': '$10', # Master/Slave Select
+ 'SPCR_CPOL': '$8', # Clock polarity
+ 'SPCR_CPHA': '$4', # Clock Phase
+ 'SPCR_SPR': '$3', # SPI Clock Rate Selects
+
+# Module WATCHDOG
+ 'WDTCSR' : '$60', # Watchdog Timer Control Registe
+ 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
+ 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
+ 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
+ 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
+ 'WDTCSR_WDE': '$8', # Watch Dog Enable
+
+# Module CPU
+ 'PRR' : '$64', # Power Reduction Register
+ 'PRR_PRTWI': '$80', # Power Reduction TWI
+ 'PRR_PRTIM2': '$40', # Power Reduction Timer/Counter2
+ 'PRR_PRTIM0': '$20', # Power Reduction Timer/Counter0
+ 'PRR_PRTIM1': '$8', # Power Reduction Timer/Counter1
+ 'PRR_PRSPI': '$4', # Power Reduction Serial Periphe
+ 'PRR_PRUSART0': '$2', # Power Reduction USART
+ 'PRR_PRADC': '$1', # Power Reduction ADC
+ 'OSCCAL' : '$66', # Oscillator Calibration Value
+ 'CLKPR' : '$61', # Clock Prescale Register
+ 'CLKPR_CLKPCE': '$80', # Clock Prescaler Change Enable
+ 'CLKPR_CLKPS': '$f', # Clock Prescaler Select Bits
+ 'SREG' : '$5f', # Status Register
+ 'SREG_I': '$80', # Global Interrupt Enable
+ 'SREG_T': '$40', # Bit Copy Storage
+ 'SREG_H': '$20', # Half Carry Flag
+ 'SREG_S': '$10', # Sign Bit
+ 'SREG_V': '$8', # Two's Complement Overflow Flag
+ 'SREG_N': '$4', # Negative Flag
+ 'SREG_Z': '$2', # Zero Flag
+ 'SREG_C': '$1', # Carry Flag
+ 'SP' : '$5d', # Stack Pointer
+ 'SPMCSR' : '$57', # Store Program Memory Control a
+ 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
+ 'SPMCSR_RWWSB': '$40', # Read-While-Write Section Busy
+ 'SPMCSR_RWWSRE': '$10', # Read-While-Write section read
+ 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
+ 'SPMCSR_PGWRT': '$4', # Page Write
+ 'SPMCSR_PGERS': '$2', # Page Erase
+ 'SPMCSR_SELFPRGEN': '$1', # Self Programming Enable
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_BODS': '$40', # BOD Sleep
+ 'MCUCR_BODSE': '$20', # BOD Sleep Enable
+ 'MCUCR_PUD': '$10', #
+ 'MCUCR_IVSEL': '$2', #
+ 'MCUCR_IVCE': '$1', #
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
+ 'MCUSR_BORF': '$4', # Brown-out Reset Flag
+ 'MCUSR_EXTRF': '$2', # External Reset Flag
+ 'MCUSR_PORF': '$1', # Power-on reset flag
+ 'SMCR' : '$53', # Sleep Mode Control Register
+ 'SMCR_SM': '$e', # Sleep Mode Select Bits
+ 'SMCR_SE': '$1', # Sleep Enable
+ 'GPIOR2' : '$4b', # General Purpose I/O Register 2
+ 'GPIOR1' : '$4a', # General Purpose I/O Register 1
+ 'GPIOR0' : '$3e', # General Purpose I/O Register 0
+
+# Module EEPROM
+ 'EEAR' : '$41', # EEPROM Address Register Bytes
+ 'EEDR' : '$40', # EEPROM Data Register
+ 'EECR' : '$3f', # EEPROM Control Register
+ 'EECR_EEPM': '$30', # EEPROM Programming Mode Bits
+ 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
+ 'EECR_EEMPE': '$4', # EEPROM Master Write Enable
+ 'EECR_EEPE': '$2', # EEPROM Write Enable
+ 'EECR_EERE': '$1', # EEPROM Read Enable
+
+ '__amforth_dummy':'0'
+}
diff --git a/amforth-6.5/avr8/devices/atmega328p/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega328p/words/no-jtag.asm
new file mode 100644
index 0000000..352a4bb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega328p/words/no-jtag.asm
@@ -0,0 +1,14 @@
+; ( -- )
+; ( -- )
+; MCU
+; disable jtag at runtime
+VE_NOJTAG:
+ .dw $FF05
+ .db "-jtag",0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOJTAG
+XT_NOJTAG:
+ .dw PFA_NOJTAG
+PFA_NOJTAG:
+
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega328p/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega328p/words/no-wdt.asm
new file mode 100644
index 0000000..ff6ddd1
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega328p/words/no-wdt.asm
@@ -0,0 +1,34 @@
+; ( -- )
+; MCU
+; disable watch dog timer at runtime
+VE_NOWDT:
+ .dw $ff04
+ .db "-wdt"
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOWDT
+XT_NOWDT:
+ .dw PFA_NOWDT
+PFA_NOWDT:
+
+ in temp1,SREG
+ push temp1
+ ; Turn always off global interrupt.
+ cli
+ ; Reset Watchdog Timer
+ wdr
+ ; Clear WDRF in MCUSR
+ in temp1, MCUSR
+ andi temp1, (0xff & (0<<WDRF))
+ out MCUSR, temp1
+ ; Write logical one to WDCE and WDE
+ ; Keep old prescaler setting to prevent unintentional time-out
+ in_ temp1, WDTCSR
+ ori temp1, (1<<WDCE) | (1<<WDE)
+ out_ WDTCSR, temp1
+ ; Turn off WDT
+ ldi temp1, (0<<WDE)
+ out_ WDTCSR, temp1
+ ; restore status register
+ pop temp1
+ out SREG,temp1
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega328p/words/sleep.asm b/amforth-6.5/avr8/devices/atmega328p/words/sleep.asm
new file mode 100644
index 0000000..256249c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega328p/words/sleep.asm
@@ -0,0 +1,19 @@
+; ( mode -- )
+; MCU
+; put the controller into the specified sleep mode
+VE_SLEEP:
+ .dw $ff05
+ .db "sleep", 0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_SLEEP
+XT_SLEEP:
+ .dw PFA_SLEEP
+PFA_SLEEP:
+ andi tosl, 7 ; leave only legal mode bits
+ lsl tosl ; move to correct location (bits 3-1)
+ ori tosl, 1 ; set the SE bit
+ out_ SMCR, tosl ; set the sleep config
+ sleep ; nighty-night
+ out_ SMCR, zerol ; 0 protects against accidental sleeps
+ loadtos ; pop argument from stack
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega329/atmega329.frt b/amforth-6.5/avr8/devices/atmega329/atmega329.frt
new file mode 100644
index 0000000..08ccb3e
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega329/atmega329.frt
@@ -0,0 +1,312 @@
+\ Partname: ATmega329
+\ generated automatically
+
+\ TIMER_COUNTER_0
+&68 constant TCCR0A \ Timer/Counter0 Control Register
+ $80 constant TCCR0A_FOC0A \ Force Output Compare
+ $40 constant TCCR0A_WGM00 \ Waveform Generation Mode 0
+ $30 constant TCCR0A_COM0A \ Compare Match Output Modes
+ $08 constant TCCR0A_WGM01 \ Waveform Generation Mode 1
+ $07 constant TCCR0A_CS0 \ Clock Selects
+&70 constant TCNT0 \ Timer/Counter0
+&71 constant OCR0A \ Timer/Counter0 Output Compare Register
+&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
+ $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match Interrupt Enable
+ $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
+&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
+ $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0
+ $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
+&67 constant GTCCR \ General Timer/Control Register
+ $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
+ $01 constant GTCCR_PSR310 \ Prescaler Reset Timer/Counter1 and Timer/Counter0
+\ TIMER_COUNTER_1
+&128 constant TCCR1A \ Timer/Counter1 Control Register A
+ $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
+ $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
+ $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
+&129 constant TCCR1B \ Timer/Counter1 Control Register B
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
+ $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
+&130 constant TCCR1C \ Timer/Counter 1 Control Register C
+ $80 constant TCCR1C_FOC1A \ Force Output Compare 1A
+ $40 constant TCCR1C_FOC1B \ Force Output Compare 1B
+&132 constant TCNT1 \ Timer/Counter1 Bytes
+&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
+&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
+&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
+&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
+ $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
+ $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
+ $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
+ $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
+&54 constant TIFR1 \ Timer/Counter1 Interrupt Flag register
+ $20 constant TIFR1_ICF1 \ Input Capture Flag 1
+ $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
+ $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
+ $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
+\ TIMER_COUNTER_2
+&176 constant TCCR2A \ Timer/Counter2 Control Register
+ $80 constant TCCR2A_FOC2A \ Force Output Compare A
+ $40 constant TCCR2A_WGM20 \ Waveform Generation Mode
+ $30 constant TCCR2A_COM2A \ Compare Output Mode bits
+ $08 constant TCCR2A_WGM21 \ Waveform Generation Mode
+ $07 constant TCCR2A_CS2 \ Clock Select bits
+&178 constant TCNT2 \ Timer/Counter2
+&179 constant OCR2A \ Timer/Counter2 Output Compare Register
+&112 constant TIMSK2 \ Timer/Counter2 Interrupt Mask register
+ $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match Interrupt Enable
+ $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
+&55 constant TIFR2 \ Timer/Counter2 Interrupt Flag Register
+ $02 constant TIFR2_OCF2A \ Timer/Counter2 Output Compare Flag 2
+ $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
+&182 constant ASSR \ Asynchronous Status Register
+ $10 constant ASSR_EXCLK \ Enable External Clock Interrupt
+ $08 constant ASSR_AS2 \ AS2: Asynchronous Timer/Counter2
+ $04 constant ASSR_TCN2UB \ TCN2UB: Timer/Counter2 Update Busy
+ $02 constant ASSR_OCR2UB \ Output Compare Register2 Update Busy
+ $01 constant ASSR_TCR2UB \ TCR2UB: Timer/Counter Control Register2 Update Busy
+\ WATCHDOG
+&96 constant WDTCR \ Watchdog Timer Control Register
+ $10 constant WDTCR_WDCE \ Watchdog Change Enable
+ $08 constant WDTCR_WDE \ Watch Dog Enable
+ $07 constant WDTCR_WDP \ Watch Dog Timer Prescaler bits
+\ EEPROM
+&65 constant EEAR \ EEPROM Read/Write Access Bytes
+&64 constant EEDR \ EEPROM Data Register
+&63 constant EECR \ EEPROM Control Register
+ $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
+ $04 constant EECR_EEMWE \ EEPROM Master Write Enable
+ $02 constant EECR_EEWE \ EEPROM Write Enable
+ $01 constant EECR_EERE \ EEPROM Read Enable
+\ SPI
+&76 constant SPCR \ SPI Control Register
+ $80 constant SPCR_SPIE \ SPI Interrupt Enable
+ $40 constant SPCR_SPE \ SPI Enable
+ $20 constant SPCR_DORD \ Data Order
+ $10 constant SPCR_MSTR \ Master/Slave Select
+ $08 constant SPCR_CPOL \ Clock polarity
+ $04 constant SPCR_CPHA \ Clock Phase
+ $03 constant SPCR_SPR \ SPI Clock Rate Selects
+&77 constant SPSR \ SPI Status Register
+ $80 constant SPSR_SPIF \ SPI Interrupt Flag
+ $40 constant SPSR_WCOL \ Write Collision Flag
+ $01 constant SPSR_SPI2X \ Double SPI Speed Bit
+&78 constant SPDR \ SPI Data Register
+\ PORTA
+&34 constant PORTA \ Port A Data Register
+&33 constant DDRA \ Port A Data Direction Register
+&32 constant PINA \ Port A Input Pins
+\ PORTB
+&37 constant PORTB \ Port B Data Register
+&36 constant DDRB \ Port B Data Direction Register
+&35 constant PINB \ Port B Input Pins
+\ PORTC
+&40 constant PORTC \ Port C Data Register
+&39 constant DDRC \ Port C Data Direction Register
+&38 constant PINC \ Port C Input Pins
+\ PORTD
+&43 constant PORTD \ Port D Data Register
+&42 constant DDRD \ Port D Data Direction Register
+&41 constant PIND \ Port D Input Pins
+\ ANALOG_COMPARATOR
+&123 constant ADCSRB \ ADC Control and Status Register B
+ $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer Enable
+&80 constant ACSR \ Analog Comparator Control And Status Register
+ $80 constant ACSR_ACD \ Analog Comparator Disable
+ $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
+ $20 constant ACSR_ACO \ Analog Compare Output
+ $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
+ $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
+ $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
+ $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
+&127 constant DIDR1 \ Digital Input Disable Register 1
+ $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
+ $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
+\ PORTE
+&46 constant PORTE \ Data Register, Port E
+&45 constant DDRE \ Data Direction Register, Port E
+&44 constant PINE \ Input Pins, Port E
+\ PORTF
+&49 constant PORTF \ Data Register, Port F
+&48 constant DDRF \ Data Direction Register, Port F
+&47 constant PINF \ Input Pins, Port F
+\ PORTG
+&52 constant PORTG \ Port G Data Register
+&51 constant DDRG \ Port G Data Direction Register
+&50 constant PING \ Port G Input Pins
+\ JTAG
+&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
+&85 constant MCUCR \ MCU Control Register
+ $80 constant MCUCR_JTD \ JTAG Interface Disable
+&84 constant MCUSR \ MCU Status Register
+ $10 constant MCUSR_JTRF \ JTAG Reset Flag
+\ LCD
+&254 constant LCDDR18 \ LCD Data Register 18
+&253 constant LCDDR17 \ LCD Data Register 17
+&252 constant LCDDR16 \ LCD Data Register 16
+&251 constant LCDDR15 \ LCD Data Register 15
+&249 constant LCDDR13 \ LCD Data Register 13
+&248 constant LCDDR12 \ LCD Data Register 12
+&247 constant LCDDR11 \ LCD Data Register 11
+&246 constant LCDDR10 \ LCD Data Register 10
+&244 constant LCDDR8 \ LCD Data Register 8
+&243 constant LCDDR7 \ LCD Data Register 7
+&242 constant LCDDR6 \ LCD Data Register 6
+&241 constant LCDDR5 \ LCD Data Register 5
+&239 constant LCDDR3 \ LCD Data Register 3
+&238 constant LCDDR2 \ LCD Data Register 2
+&237 constant LCDDR1 \ LCD Data Register 1
+&236 constant LCDDR0 \ LCD Data Register 0
+&231 constant LCDCCR \ LCD Contrast Control Register
+&230 constant LCDFRR \ LCD Frame Rate Register
+ $70 constant LCDFRR_LCDPS \ LCD Prescaler Selects
+ $07 constant LCDFRR_LCDCD \ LCD Clock Dividers
+&229 constant LCDCRB \ LCD Control and Status Register B
+ $80 constant LCDCRB_LCDCS \ LCD CLock Select
+ $40 constant LCDCRB_LCD2B \ LCD 1/2 Bias Select
+ $30 constant LCDCRB_LCDMUX \ LCD Mux Selects
+ $0F constant LCDCRB_LCDPM \ LCD Port Masks
+&228 constant LCDCRA \ LCD Control Register A
+ $80 constant LCDCRA_LCDEN \ LCD Enable
+ $40 constant LCDCRA_LCDAB \ LCD A or B waveform
+ $10 constant LCDCRA_LCDIF \ LCD Interrupt Flag
+ $08 constant LCDCRA_LCDIE \ LCD Interrupt Enable
+ $01 constant LCDCRA_LCDBL \ LCD Blanking
+\ EXTERNAL_INTERRUPT
+&105 constant EICRA \ External Interrupt Control Register A
+ $02 constant EICRA_ISC01 \ External Interrupt Sense Control 0 Bit 1
+ $01 constant EICRA_ISC00 \ External Interrupt Sense Control 0 Bit 0
+&61 constant EIMSK \ External Interrupt Mask Register
+ $F0 constant EIMSK_PCIE \ Pin Change Interrupt Enables
+ $01 constant EIMSK_INT0 \ External Interrupt Request 0 Enable
+&60 constant EIFR \ External Interrupt Flag Register
+ $F0 constant EIFR_PCIF \ Pin Change Interrupt Flags
+ $01 constant EIFR_INTF0 \ External Interrupt Flag 0
+&108 constant PCMSK1 \ Pin Change Mask Register 1
+&107 constant PCMSK0 \ Pin Change Mask Register 0
+\ CPU
+&95 constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ $08 constant SREG_V \ Two's Complement Overflow Flag
+ $04 constant SREG_N \ Negative Flag
+ $02 constant SREG_Z \ Zero Flag
+ $01 constant SREG_C \ Carry Flag
+&93 constant SP \ Stack Pointer
+&102 constant OSCCAL \ Oscillator Calibration Value
+&97 constant CLKPR \ Clock Prescale Register
+ $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable
+ $0F constant CLKPR_CLKPS \ Clock Prescaler Select Bits
+&100 constant PRR \ Power Reduction Register
+ $10 constant PRR_PRLCD \ Power Reduction LCD
+ $08 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
+ $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
+ $02 constant PRR_PRUSART0 \ Power Reduction USART
+ $01 constant PRR_PRADC \ Power Reduction ADC
+&83 constant SMCR \ Sleep Mode Control Register
+ $0E constant SMCR_SM \ Sleep Mode Select bits
+ $01 constant SMCR_SE \ Sleep Enable
+&75 constant GPIOR2 \ General Purpose IO Register 2
+&74 constant GPIOR1 \ General Purpose IO Register 1
+&62 constant GPIOR0 \ General Purpose IO Register 0
+\ USI
+&186 constant USIDR \ USI Data Register
+&185 constant USISR \ USI Status Register
+ $80 constant USISR_USISIF \ Start Condition Interrupt Flag
+ $40 constant USISR_USIOIF \ Counter Overflow Interrupt Flag
+ $20 constant USISR_USIPF \ Stop Condition Flag
+ $10 constant USISR_USIDC \ Data Output Collision
+ $0F constant USISR_USICNT \ USI Counter Value Bits
+&184 constant USICR \ USI Control Register
+ $80 constant USICR_USISIE \ Start Condition Interrupt Enable
+ $40 constant USICR_USIOIE \ Counter Overflow Interrupt Enable
+ $30 constant USICR_USIWM \ USI Wire Mode Bits
+ $0C constant USICR_USICS \ USI Clock Source Select Bits
+ $02 constant USICR_USICLK \ Clock Strobe
+ $01 constant USICR_USITC \ Toggle Clock Port Pin
+\ AD_CONVERTER
+&124 constant ADMUX \ The ADC multiplexer Selection Register
+ $C0 constant ADMUX_REFS \ Reference Selection Bits
+ $20 constant ADMUX_ADLAR \ Left Adjust Result
+ $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
+&122 constant ADCSRA \ The ADC Control and Status register
+ $80 constant ADCSRA_ADEN \ ADC Enable
+ $40 constant ADCSRA_ADSC \ ADC Start Conversion
+ $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
+ $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
+ $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
+ $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
+&120 constant ADC \ ADC Data Register Bytes
+&126 constant DIDR0 \ Digital Input Disable Register 0
+ $80 constant DIDR0_ADC7D \ ADC7 Digital input Disable
+ $40 constant DIDR0_ADC6D \ ADC6 Digital input Disable
+ $20 constant DIDR0_ADC5D \ ADC5 Digital input Disable
+ $10 constant DIDR0_ADC4D \ ADC4 Digital input Disable
+ $08 constant DIDR0_ADC3D \ ADC3 Digital input Disable
+ $04 constant DIDR0_ADC2D \ ADC2 Digital input Disable
+ $02 constant DIDR0_ADC1D \ ADC1 Digital input Disable
+ $01 constant DIDR0_ADC0D \ ADC0 Digital input Disable
+\ BOOT_LOAD
+&87 constant SPMCSR \ Store Program Memory Control Register
+ $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
+ $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
+ $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
+ $04 constant SPMCSR_PGWRT \ Page Write
+ $02 constant SPMCSR_PGERS \ Page Erase
+ $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
+\ USART0
+&198 constant UDR0 \ USART I/O Data Register
+&192 constant UCSR0A \ USART Control and Status Register A
+ $80 constant UCSR0A_RXC0 \ USART Receive Complete
+ $40 constant UCSR0A_TXC0 \ USART Transmit Complete
+ $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
+ $10 constant UCSR0A_FE0 \ Framing Error
+ $08 constant UCSR0A_DOR0 \ Data OverRun
+ $04 constant UCSR0A_UPE0 \ USART Parity Error
+ $02 constant UCSR0A_U2X0 \ Double the USART Transmission Speed
+ $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
+&193 constant UCSR0B \ USART Control and Status Register B
+ $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
+ $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
+ $20 constant UCSR0B_UDRIE0 \ USART Data Register Empty Interrupt Enable
+ $10 constant UCSR0B_RXEN0 \ Receiver Enable
+ $08 constant UCSR0B_TXEN0 \ Transmitter Enable
+ $04 constant UCSR0B_UCSZ02 \ Character Size
+ $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
+ $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
+&194 constant UCSR0C \ USART Control and Status Register C
+ $40 constant UCSR0C_UMSEL0 \ USART Mode Select
+ $30 constant UCSR0C_UPM0 \ Parity Mode Bits
+ $08 constant UCSR0C_USBS0 \ Stop Bit Select
+ $06 constant UCSR0C_UCSZ0 \ Character Size
+ $01 constant UCSR0C_UCPOL0 \ Clock Polarity
+&196 constant UBRR0 \ USART Baud Rate Register Bytes
+
+\ Interrupts
+&2 constant INT0Addr \ External Interrupt Request 0
+&4 constant PCINT0Addr \ Pin Change Interrupt Request 0
+&6 constant PCINT1Addr \ Pin Change Interrupt Request 1
+&8 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
+&10 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
+&12 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+&14 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
+&16 constant TIMER1_COMPBAddr \ Timer/Counter Compare Match B
+&18 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+&20 constant TIMER0_COMPAddr \ Timer/Counter0 Compare Match
+&22 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
+&24 constant SPI__STCAddr \ SPI Serial Transfer Complete
+&26 constant USART0__RXAddr \ USART0, Rx Complete
+&28 constant USART0__UDREAddr \ USART0 Data register Empty
+&30 constant USART0__TXAddr \ USART0, Tx Complete
+&32 constant USI_STARTAddr \ USI Start Condition
+&34 constant USI_OVERFLOWAddr \ USI Overflow
+&36 constant ANALOG_COMPAddr \ Analog Comparator
+&38 constant ADCAddr \ ADC Conversion Complete
+&40 constant EE_READYAddr \ EEPROM Ready
+&42 constant SPM_READYAddr \ Store Program Memory Read
+&44 constant LCDAddr \ LCD Start of Frame
diff --git a/amforth-6.5/avr8/devices/atmega329/device.asm b/amforth-6.5/avr8/devices/atmega329/device.asm
new file mode 100644
index 0000000..cf02ccb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega329/device.asm
@@ -0,0 +1,109 @@
+; Partname: ATmega329
+; generated automatically, do not edit
+
+.nolist
+ .include "m329def.inc"
+.list
+
+.equ ramstart = 256
+.equ CELLSIZE = 2
+.macro readflashcell
+ lsl zl
+ rol zh
+ lpm @0, Z+
+ lpm @1, Z+
+.endmacro
+.macro writeflashcell
+ lsl zl
+ rol zh
+.endmacro
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_TIMER_COUNTER_2 = 0
+.set WANT_WATCHDOG = 0
+.set WANT_EEPROM = 0
+.set WANT_SPI = 0
+.set WANT_PORTA = 0
+.set WANT_PORTB = 0
+.set WANT_PORTC = 0
+.set WANT_PORTD = 0
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_PORTE = 0
+.set WANT_PORTF = 0
+.set WANT_PORTG = 0
+.set WANT_JTAG = 0
+.set WANT_LCD = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_CPU = 0
+.set WANT_USI = 0
+.set WANT_AD_CONVERTER = 0
+.set WANT_BOOT_LOAD = 0
+.set WANT_USART0 = 0
+.equ intvecsize = 2 ; please verify; flash size: 32768 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.org 2
+ rcall isr ; External Interrupt Request 0
+.org 4
+ rcall isr ; Pin Change Interrupt Request 0
+.org 6
+ rcall isr ; Pin Change Interrupt Request 1
+.org 8
+ rcall isr ; Timer/Counter2 Compare Match
+.org 10
+ rcall isr ; Timer/Counter2 Overflow
+.org 12
+ rcall isr ; Timer/Counter1 Capture Event
+.org 14
+ rcall isr ; Timer/Counter1 Compare Match A
+.org 16
+ rcall isr ; Timer/Counter Compare Match B
+.org 18
+ rcall isr ; Timer/Counter1 Overflow
+.org 20
+ rcall isr ; Timer/Counter0 Compare Match
+.org 22
+ rcall isr ; Timer/Counter0 Overflow
+.org 24
+ rcall isr ; SPI Serial Transfer Complete
+.org 26
+ rcall isr ; USART0, Rx Complete
+.org 28
+ rcall isr ; USART0 Data register Empty
+.org 30
+ rcall isr ; USART0, Tx Complete
+.org 32
+ rcall isr ; USI Start Condition
+.org 34
+ rcall isr ; USI Overflow
+.org 36
+ rcall isr ; Analog Comparator
+.org 38
+ rcall isr ; ADC Conversion Complete
+.org 40
+ rcall isr ; EEPROM Ready
+.org 42
+ rcall isr ; Store Program Memory Read
+.org 44
+ rcall isr ; LCD Start of Frame
+.equ INTVECTORS = 23
+.nooverlap
+
+; compatability layer (maybe empty)
+.equ EEPE = EEWE
+.equ EEMPE = EEMWE
+
+; controller data area, environment query mcu-info
+mcu_info:
+mcu_ramsize:
+ .dw 2048
+mcu_eepromsize:
+ .dw 1024
+mcu_maxdp:
+ .dw 28672
+mcu_numints:
+ .dw 23
+mcu_name:
+ .dw 9
+ .db "ATmega329",0
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega329/device.inc b/amforth-6.5/avr8/devices/atmega329/device.inc
new file mode 100644
index 0000000..707042f
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega329/device.inc
@@ -0,0 +1,1293 @@
+; Partname: ATmega329
+; generated automatically, no not edit
+
+.if WANT_TIMER_COUNTER_0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Control Register
+VE_TCCR0A:
+ .dw $ff06
+ .db "TCCR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0A
+XT_TCCR0A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0A:
+ .dw 68
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw 70
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0A:
+ .dw $ff05
+ .db "OCR0A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0A
+XT_OCR0A:
+ .dw PFA_DOVARIABLE
+PFA_OCR0A:
+ .dw 71
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Mask Register
+VE_TIMSK0:
+ .dw $ff06
+ .db "TIMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK0
+XT_TIMSK0:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK0:
+ .dw 110
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Flag register
+VE_TIFR0:
+ .dw $ff05
+ .db "TIFR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR0
+XT_TIFR0:
+ .dw PFA_DOVARIABLE
+PFA_TIFR0:
+ .dw 53
+; ( -- addr ) System Constant
+; R( -- )
+; General Timer/Control Register
+VE_GTCCR:
+ .dw $ff05
+ .db "GTCCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GTCCR
+XT_GTCCR:
+ .dw PFA_DOVARIABLE
+PFA_GTCCR:
+ .dw 67
+
+.endif
+.if WANT_TIMER_COUNTER_1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw 128
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw 129
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter 1 Control Register C
+VE_TCCR1C:
+ .dw $ff06
+ .db "TCCR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1C
+XT_TCCR1C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1C:
+ .dw 130
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Bytes
+VE_TCNT1:
+ .dw $ff05
+ .db "TCNT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1
+XT_TCNT1:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1:
+ .dw 132
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register A Bytes
+VE_OCR1A:
+ .dw $ff05
+ .db "OCR1A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1A
+XT_OCR1A:
+ .dw PFA_DOVARIABLE
+PFA_OCR1A:
+ .dw 136
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register B Bytes
+VE_OCR1B:
+ .dw $ff05
+ .db "OCR1B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1B
+XT_OCR1B:
+ .dw PFA_DOVARIABLE
+PFA_OCR1B:
+ .dw 138
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Bytes
+VE_ICR1:
+ .dw $ff04
+ .db "ICR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1
+XT_ICR1:
+ .dw PFA_DOVARIABLE
+PFA_ICR1:
+ .dw 134
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Mask Register
+VE_TIMSK1:
+ .dw $ff06
+ .db "TIMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK1
+XT_TIMSK1:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK1:
+ .dw 111
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Flag register
+VE_TIFR1:
+ .dw $ff05
+ .db "TIFR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR1
+XT_TIFR1:
+ .dw PFA_DOVARIABLE
+PFA_TIFR1:
+ .dw 54
+
+.endif
+.if WANT_TIMER_COUNTER_2 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register
+VE_TCCR2A:
+ .dw $ff06
+ .db "TCCR2A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2A
+XT_TCCR2A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2A:
+ .dw 176
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2
+VE_TCNT2:
+ .dw $ff05
+ .db "TCNT2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT2
+XT_TCNT2:
+ .dw PFA_DOVARIABLE
+PFA_TCNT2:
+ .dw 178
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register
+VE_OCR2A:
+ .dw $ff05
+ .db "OCR2A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2A
+XT_OCR2A:
+ .dw PFA_DOVARIABLE
+PFA_OCR2A:
+ .dw 179
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Interrupt Mask register
+VE_TIMSK2:
+ .dw $ff06
+ .db "TIMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK2
+XT_TIMSK2:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK2:
+ .dw 112
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Interrupt Flag Register
+VE_TIFR2:
+ .dw $ff05
+ .db "TIFR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR2
+XT_TIFR2:
+ .dw PFA_DOVARIABLE
+PFA_TIFR2:
+ .dw 55
+; ( -- addr ) System Constant
+; R( -- )
+; Asynchronous Status Register
+VE_ASSR:
+ .dw $ff04
+ .db "ASSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ASSR
+XT_ASSR:
+ .dw PFA_DOVARIABLE
+PFA_ASSR:
+ .dw 182
+
+.endif
+.if WANT_WATCHDOG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCR:
+ .dw $ff05
+ .db "WDTCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCR
+XT_WDTCR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCR:
+ .dw 96
+
+.endif
+.if WANT_EEPROM == 1
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Read/Write Access Bytes
+VE_EEAR:
+ .dw $ff04
+ .db "EEAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEAR
+XT_EEAR:
+ .dw PFA_DOVARIABLE
+PFA_EEAR:
+ .dw 65
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw 64
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw 63
+
+.endif
+.if WANT_SPI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR:
+ .dw $ff04
+ .db "SPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR
+XT_SPCR:
+ .dw PFA_DOVARIABLE
+PFA_SPCR:
+ .dw 76
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR:
+ .dw $ff04
+ .db "SPSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR
+XT_SPSR:
+ .dw PFA_DOVARIABLE
+PFA_SPSR:
+ .dw 77
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR:
+ .dw $ff04
+ .db "SPDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR
+XT_SPDR:
+ .dw PFA_DOVARIABLE
+PFA_SPDR:
+ .dw 78
+
+.endif
+.if WANT_PORTA == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Register
+VE_PORTA:
+ .dw $ff05
+ .db "PORTA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTA
+XT_PORTA:
+ .dw PFA_DOVARIABLE
+PFA_PORTA:
+ .dw 34
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Direction Register
+VE_DDRA:
+ .dw $ff04
+ .db "DDRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRA
+XT_DDRA:
+ .dw PFA_DOVARIABLE
+PFA_DDRA:
+ .dw 33
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Input Pins
+VE_PINA:
+ .dw $ff04
+ .db "PINA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINA
+XT_PINA:
+ .dw PFA_DOVARIABLE
+PFA_PINA:
+ .dw 32
+
+.endif
+.if WANT_PORTB == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw 37
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw 36
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw 35
+
+.endif
+.if WANT_PORTC == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Register
+VE_PORTC:
+ .dw $ff05
+ .db "PORTC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTC
+XT_PORTC:
+ .dw PFA_DOVARIABLE
+PFA_PORTC:
+ .dw 40
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Direction Register
+VE_DDRC:
+ .dw $ff04
+ .db "DDRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRC
+XT_DDRC:
+ .dw PFA_DOVARIABLE
+PFA_DDRC:
+ .dw 39
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Input Pins
+VE_PINC:
+ .dw $ff04
+ .db "PINC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINC
+XT_PINC:
+ .dw PFA_DOVARIABLE
+PFA_PINC:
+ .dw 38
+
+.endif
+.if WANT_PORTD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw 43
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw 42
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw 41
+
+.endif
+.if WANT_ANALOG_COMPARATOR == 1
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Control and Status Register B
+VE_ADCSRB:
+ .dw $ff06
+ .db "ADCSRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRB
+XT_ADCSRB:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRB:
+ .dw 123
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Control And Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw 80
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 1
+VE_DIDR1:
+ .dw $ff05
+ .db "DIDR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR1
+XT_DIDR1:
+ .dw PFA_DOVARIABLE
+PFA_DIDR1:
+ .dw 127
+
+.endif
+.if WANT_PORTE == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port E
+VE_PORTE:
+ .dw $ff05
+ .db "PORTE",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTE
+XT_PORTE:
+ .dw PFA_DOVARIABLE
+PFA_PORTE:
+ .dw 46
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port E
+VE_DDRE:
+ .dw $ff04
+ .db "DDRE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRE
+XT_DDRE:
+ .dw PFA_DOVARIABLE
+PFA_DDRE:
+ .dw 45
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port E
+VE_PINE:
+ .dw $ff04
+ .db "PINE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINE
+XT_PINE:
+ .dw PFA_DOVARIABLE
+PFA_PINE:
+ .dw 44
+
+.endif
+.if WANT_PORTF == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port F
+VE_PORTF:
+ .dw $ff05
+ .db "PORTF",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTF
+XT_PORTF:
+ .dw PFA_DOVARIABLE
+PFA_PORTF:
+ .dw 49
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port F
+VE_DDRF:
+ .dw $ff04
+ .db "DDRF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRF
+XT_DDRF:
+ .dw PFA_DOVARIABLE
+PFA_DDRF:
+ .dw 48
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port F
+VE_PINF:
+ .dw $ff04
+ .db "PINF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINF
+XT_PINF:
+ .dw PFA_DOVARIABLE
+PFA_PINF:
+ .dw 47
+
+.endif
+.if WANT_PORTG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Data Register
+VE_PORTG:
+ .dw $ff05
+ .db "PORTG",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTG
+XT_PORTG:
+ .dw PFA_DOVARIABLE
+PFA_PORTG:
+ .dw 52
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Data Direction Register
+VE_DDRG:
+ .dw $ff04
+ .db "DDRG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRG
+XT_DDRG:
+ .dw PFA_DOVARIABLE
+PFA_DDRG:
+ .dw 51
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Input Pins
+VE_PING:
+ .dw $ff04
+ .db "PING"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PING
+XT_PING:
+ .dw PFA_DOVARIABLE
+PFA_PING:
+ .dw 50
+
+.endif
+.if WANT_JTAG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; On-Chip Debug Related Register in I/O Memory
+VE_OCDR:
+ .dw $ff04
+ .db "OCDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCDR
+XT_OCDR:
+ .dw PFA_DOVARIABLE
+PFA_OCDR:
+ .dw 81
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw 85
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Status Register
+VE_MCUSR:
+ .dw $ff05
+ .db "MCUSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUSR
+XT_MCUSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUSR:
+ .dw 84
+
+.endif
+.if WANT_LCD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 18
+VE_LCDDR18:
+ .dw $ff07
+ .db "LCDDR18",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR18
+XT_LCDDR18:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR18:
+ .dw 254
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 17
+VE_LCDDR17:
+ .dw $ff07
+ .db "LCDDR17",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR17
+XT_LCDDR17:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR17:
+ .dw 253
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 16
+VE_LCDDR16:
+ .dw $ff07
+ .db "LCDDR16",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR16
+XT_LCDDR16:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR16:
+ .dw 252
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 15
+VE_LCDDR15:
+ .dw $ff07
+ .db "LCDDR15",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR15
+XT_LCDDR15:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR15:
+ .dw 251
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 13
+VE_LCDDR13:
+ .dw $ff07
+ .db "LCDDR13",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR13
+XT_LCDDR13:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR13:
+ .dw 249
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 12
+VE_LCDDR12:
+ .dw $ff07
+ .db "LCDDR12",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR12
+XT_LCDDR12:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR12:
+ .dw 248
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 11
+VE_LCDDR11:
+ .dw $ff07
+ .db "LCDDR11",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR11
+XT_LCDDR11:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR11:
+ .dw 247
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 10
+VE_LCDDR10:
+ .dw $ff07
+ .db "LCDDR10",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR10
+XT_LCDDR10:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR10:
+ .dw 246
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 8
+VE_LCDDR8:
+ .dw $ff06
+ .db "LCDDR8"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR8
+XT_LCDDR8:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR8:
+ .dw 244
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 7
+VE_LCDDR7:
+ .dw $ff06
+ .db "LCDDR7"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR7
+XT_LCDDR7:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR7:
+ .dw 243
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 6
+VE_LCDDR6:
+ .dw $ff06
+ .db "LCDDR6"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR6
+XT_LCDDR6:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR6:
+ .dw 242
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 5
+VE_LCDDR5:
+ .dw $ff06
+ .db "LCDDR5"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR5
+XT_LCDDR5:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR5:
+ .dw 241
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 3
+VE_LCDDR3:
+ .dw $ff06
+ .db "LCDDR3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR3
+XT_LCDDR3:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR3:
+ .dw 239
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 2
+VE_LCDDR2:
+ .dw $ff06
+ .db "LCDDR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR2
+XT_LCDDR2:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR2:
+ .dw 238
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 1
+VE_LCDDR1:
+ .dw $ff06
+ .db "LCDDR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR1
+XT_LCDDR1:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR1:
+ .dw 237
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 0
+VE_LCDDR0:
+ .dw $ff06
+ .db "LCDDR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR0
+XT_LCDDR0:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR0:
+ .dw 236
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Contrast Control Register
+VE_LCDCCR:
+ .dw $ff06
+ .db "LCDCCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDCCR
+XT_LCDCCR:
+ .dw PFA_DOVARIABLE
+PFA_LCDCCR:
+ .dw 231
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Frame Rate Register
+VE_LCDFRR:
+ .dw $ff06
+ .db "LCDFRR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDFRR
+XT_LCDFRR:
+ .dw PFA_DOVARIABLE
+PFA_LCDFRR:
+ .dw 230
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Control and Status Register B
+VE_LCDCRB:
+ .dw $ff06
+ .db "LCDCRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDCRB
+XT_LCDCRB:
+ .dw PFA_DOVARIABLE
+PFA_LCDCRB:
+ .dw 229
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Control Register A
+VE_LCDCRA:
+ .dw $ff06
+ .db "LCDCRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDCRA
+XT_LCDCRA:
+ .dw PFA_DOVARIABLE
+PFA_LCDCRA:
+ .dw 228
+
+.endif
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register A
+VE_EICRA:
+ .dw $ff05
+ .db "EICRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRA
+XT_EICRA:
+ .dw PFA_DOVARIABLE
+PFA_EICRA:
+ .dw 105
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Mask Register
+VE_EIMSK:
+ .dw $ff05
+ .db "EIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIMSK
+XT_EIMSK:
+ .dw PFA_DOVARIABLE
+PFA_EIMSK:
+ .dw 61
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Flag Register
+VE_EIFR:
+ .dw $ff04
+ .db "EIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIFR
+XT_EIFR:
+ .dw PFA_DOVARIABLE
+PFA_EIFR:
+ .dw 60
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 1
+VE_PCMSK1:
+ .dw $ff06
+ .db "PCMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK1
+XT_PCMSK1:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK1:
+ .dw 108
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 0
+VE_PCMSK0:
+ .dw $ff06
+ .db "PCMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK0
+XT_PCMSK0:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK0:
+ .dw 107
+
+.endif
+.if WANT_CPU == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw 95
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer
+VE_SP:
+ .dw $ff02
+ .db "SP"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SP
+XT_SP:
+ .dw PFA_DOVARIABLE
+PFA_SP:
+ .dw 93
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Calibration Value
+VE_OSCCAL:
+ .dw $ff06
+ .db "OSCCAL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSCCAL
+XT_OSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_OSCCAL:
+ .dw 102
+; ( -- addr ) System Constant
+; R( -- )
+; Clock Prescale Register
+VE_CLKPR:
+ .dw $ff05
+ .db "CLKPR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKPR
+XT_CLKPR:
+ .dw PFA_DOVARIABLE
+PFA_CLKPR:
+ .dw 97
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register
+VE_PRR:
+ .dw $ff03
+ .db "PRR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR
+XT_PRR:
+ .dw PFA_DOVARIABLE
+PFA_PRR:
+ .dw 100
+; ( -- addr ) System Constant
+; R( -- )
+; Sleep Mode Control Register
+VE_SMCR:
+ .dw $ff04
+ .db "SMCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SMCR
+XT_SMCR:
+ .dw PFA_DOVARIABLE
+PFA_SMCR:
+ .dw 83
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 2
+VE_GPIOR2:
+ .dw $ff06
+ .db "GPIOR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR2
+XT_GPIOR2:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR2:
+ .dw 75
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 1
+VE_GPIOR1:
+ .dw $ff06
+ .db "GPIOR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR1
+XT_GPIOR1:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR1:
+ .dw 74
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 0
+VE_GPIOR0:
+ .dw $ff06
+ .db "GPIOR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR0
+XT_GPIOR0:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR0:
+ .dw 62
+
+.endif
+.if WANT_USI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USI Data Register
+VE_USIDR:
+ .dw $ff05
+ .db "USIDR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USIDR
+XT_USIDR:
+ .dw PFA_DOVARIABLE
+PFA_USIDR:
+ .dw 186
+; ( -- addr ) System Constant
+; R( -- )
+; USI Status Register
+VE_USISR:
+ .dw $ff05
+ .db "USISR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USISR
+XT_USISR:
+ .dw PFA_DOVARIABLE
+PFA_USISR:
+ .dw 185
+; ( -- addr ) System Constant
+; R( -- )
+; USI Control Register
+VE_USICR:
+ .dw $ff05
+ .db "USICR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USICR
+XT_USICR:
+ .dw PFA_DOVARIABLE
+PFA_USICR:
+ .dw 184
+
+.endif
+.if WANT_AD_CONVERTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC multiplexer Selection Register
+VE_ADMUX:
+ .dw $ff05
+ .db "ADMUX",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADMUX
+XT_ADMUX:
+ .dw PFA_DOVARIABLE
+PFA_ADMUX:
+ .dw 124
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register
+VE_ADCSRA:
+ .dw $ff06
+ .db "ADCSRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRA
+XT_ADCSRA:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRA:
+ .dw 122
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register Bytes
+VE_ADC:
+ .dw $ff03
+ .db "ADC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADC
+XT_ADC:
+ .dw PFA_DOVARIABLE
+PFA_ADC:
+ .dw 120
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 0
+VE_DIDR0:
+ .dw $ff05
+ .db "DIDR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR0
+XT_DIDR0:
+ .dw PFA_DOVARIABLE
+PFA_DIDR0:
+ .dw 126
+
+.endif
+.if WANT_BOOT_LOAD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control Register
+VE_SPMCSR:
+ .dw $ff06
+ .db "SPMCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCSR
+XT_SPMCSR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCSR:
+ .dw 87
+
+.endif
+.if WANT_USART0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR0:
+ .dw $ff04
+ .db "UDR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR0
+XT_UDR0:
+ .dw PFA_DOVARIABLE
+PFA_UDR0:
+ .dw 198
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR0A:
+ .dw $ff06
+ .db "UCSR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0A
+XT_UCSR0A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0A:
+ .dw 192
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR0B:
+ .dw $ff06
+ .db "UCSR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0B
+XT_UCSR0B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0B:
+ .dw 193
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR0C:
+ .dw $ff06
+ .db "UCSR0C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0C
+XT_UCSR0C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0C:
+ .dw 194
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Bytes
+VE_UBRR0:
+ .dw $ff05
+ .db "UBRR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR0
+XT_UBRR0:
+ .dw PFA_DOVARIABLE
+PFA_UBRR0:
+ .dw 196
+
+.endif
diff --git a/amforth-6.5/avr8/devices/atmega329/device.py b/amforth-6.5/avr8/devices/atmega329/device.py
new file mode 100644
index 0000000..c898aea
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega329/device.py
@@ -0,0 +1,352 @@
+# Generated Automatically
+
+# Partname ATmega329
+
+MCUREGS = {
+# Interrupt Vectors
+ 'INT0Addr' : '#2', # External Interrupt Request 0
+ 'PCINT0Addr' : '#4', # Pin Change Interrupt Request 0
+ 'PCINT1Addr' : '#6', # Pin Change Interrupt Request 1
+ 'TIMER2_COMPAddr' : '#8', # Timer/Counter2 Compare Match
+ 'TIMER2_OVFAddr' : '#10', # Timer/Counter2 Overflow
+ 'TIMER1_CAPTAddr' : '#12', # Timer/Counter1 Capture Event
+ 'TIMER1_COMPAAddr' : '#14', # Timer/Counter1 Compare Match A
+ 'TIMER1_COMPBAddr' : '#16', # Timer/Counter Compare Match B
+ 'TIMER1_OVFAddr' : '#18', # Timer/Counter1 Overflow
+ 'TIMER0_COMPAddr' : '#20', # Timer/Counter0 Compare Match
+ 'TIMER0_OVFAddr' : '#22', # Timer/Counter0 Overflow
+ 'SPI_STCAddr' : '#24', # SPI Serial Transfer Complete
+ 'USART0_RXAddr' : '#26', # USART0, Rx Complete
+ 'USART0_UDREAddr' : '#28', # USART0 Data register Empty
+ 'USART0_TXAddr' : '#30', # USART0, Tx Complete
+ 'USI_STARTAddr' : '#32', # USI Start Condition
+ 'USI_OVERFLOWAddr' : '#34', # USI Overflow
+ 'ANALOG_COMPAddr' : '#36', # Analog Comparator
+ 'ADCAddr' : '#38', # ADC Conversion Complete
+ 'EE_READYAddr' : '#40', # EEPROM Ready
+ 'SPM_READYAddr' : '#42', # Store Program Memory Read
+ 'LCDAddr' : '#44', # LCD Start of Frame
+
+# Module TIMER_COUNTER_0
+ 'TCCR0A' : '$44', # Timer/Counter0 Control Registe
+ 'TCCR0A_FOC0A': '$80', # Force Output Compare
+ 'TCCR0A_WGM00': '$40', # Waveform Generation Mode 0
+ 'TCCR0A_COM0A': '$30', # Compare Match Output Modes
+ 'TCCR0A_WGM01': '$8', # Waveform Generation Mode 1
+ 'TCCR0A_CS0': '$7', # Clock Selects
+ 'TCNT0' : '$46', # Timer/Counter0
+ 'OCR0A' : '$47', # Timer/Counter0 Output Compare
+ 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
+ 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
+ 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
+ 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
+ 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
+ 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Control Register
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSR310': '$1', # Prescaler Reset Timer/Counter1
+
+# Module TIMER_COUNTER_1
+ 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
+ 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
+ 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
+ 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
+ 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
+ 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
+ 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
+ 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
+ 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
+ 'TCCR1C' : '$82', # Timer/Counter 1 Control Regist
+ 'TCCR1C_FOC1A': '$80', # Force Output Compare 1A
+ 'TCCR1C_FOC1B': '$40', # Force Output Compare 1B
+ 'TCNT1' : '$84', # Timer/Counter1 Bytes
+ 'OCR1A' : '$88', # Timer/Counter1 Output Compare
+ 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
+ 'ICR1' : '$86', # Timer/Counter1 Input Capture R
+ 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
+ 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
+ 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
+ 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
+ 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
+ 'TIFR1' : '$36', # Timer/Counter1 Interrupt Flag
+ 'TIFR1_ICF1': '$20', # Input Capture Flag 1
+ 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
+ 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
+ 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
+
+# Module TIMER_COUNTER_2
+ 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
+ 'TCCR2A_FOC2A': '$80', # Force Output Compare A
+ 'TCCR2A_WGM20': '$40', # Waveform Generation Mode
+ 'TCCR2A_COM2A': '$30', # Compare Output Mode bits
+ 'TCCR2A_WGM21': '$8', # Waveform Generation Mode
+ 'TCCR2A_CS2': '$7', # Clock Select bits
+ 'TCNT2' : '$b2', # Timer/Counter2
+ 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
+ 'TIMSK2' : '$70', # Timer/Counter2 Interrupt Mask
+ 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
+ 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
+ 'TIFR2' : '$37', # Timer/Counter2 Interrupt Flag
+ 'TIFR2_OCF2A': '$2', # Timer/Counter2 Output Compare
+ 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_PSR2': '$2', # Prescaler Reset Timer/Counter2
+ 'ASSR' : '$b6', # Asynchronous Status Register
+ 'ASSR_EXCLK': '$10', # Enable External Clock Interrup
+ 'ASSR_AS2': '$8', # AS2: Asynchronous Timer/Counte
+ 'ASSR_TCN2UB': '$4', # TCN2UB: Timer/Counter2 Update
+ 'ASSR_OCR2UB': '$2', # Output Compare Register2 Updat
+ 'ASSR_TCR2UB': '$1', # TCR2UB: Timer/Counter Control
+
+# Module WATCHDOG
+ 'WDTCR' : '$60', # Watchdog Timer Control Registe
+ 'WDTCR_WDCE': '$10', # Watchdog Change Enable
+ 'WDTCR_WDE': '$8', # Watch Dog Enable
+ 'WDTCR_WDP': '$7', # Watch Dog Timer Prescaler bits
+
+# Module EEPROM
+ 'EEAR' : '$41', # EEPROM Read/Write Access Byte
+ 'EEDR' : '$40', # EEPROM Data Register
+ 'EECR' : '$3f', # EEPROM Control Register
+ 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
+ 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
+ 'EECR_EEWE': '$2', # EEPROM Write Enable
+ 'EECR_EERE': '$1', # EEPROM Read Enable
+
+# Module SPI
+ 'SPCR' : '$4c', # SPI Control Register
+ 'SPCR_SPIE': '$80', # SPI Interrupt Enable
+ 'SPCR_SPE': '$40', # SPI Enable
+ 'SPCR_DORD': '$20', # Data Order
+ 'SPCR_MSTR': '$10', # Master/Slave Select
+ 'SPCR_CPOL': '$8', # Clock polarity
+ 'SPCR_CPHA': '$4', # Clock Phase
+ 'SPCR_SPR': '$3', # SPI Clock Rate Selects
+ 'SPSR' : '$4d', # SPI Status Register
+ 'SPSR_SPIF': '$80', # SPI Interrupt Flag
+ 'SPSR_WCOL': '$40', # Write Collision Flag
+ 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
+ 'SPDR' : '$4e', # SPI Data Register
+
+# Module PORTA
+ 'PORTA' : '$22', # Port A Data Register
+ 'DDRA' : '$21', # Port A Data Direction Register
+ 'PINA' : '$20', # Port A Input Pins
+
+# Module PORTB
+ 'PORTB' : '$25', # Port B Data Register
+ 'DDRB' : '$24', # Port B Data Direction Register
+ 'PINB' : '$23', # Port B Input Pins
+
+# Module PORTC
+ 'PORTC' : '$28', # Port C Data Register
+ 'DDRC' : '$27', # Port C Data Direction Register
+ 'PINC' : '$26', # Port C Input Pins
+
+# Module PORTD
+ 'PORTD' : '$2b', # Port D Data Register
+ 'DDRD' : '$2a', # Port D Data Direction Register
+ 'PIND' : '$29', # Port D Input Pins
+
+# Module ANALOG_COMPARATOR
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
+ 'ACSR' : '$50', # Analog Comparator Control And
+ 'ACSR_ACD': '$80', # Analog Comparator Disable
+ 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
+ 'ACSR_ACO': '$20', # Analog Compare Output
+ 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
+ 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
+ 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
+ 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
+ 'DIDR1' : '$7f', # Digital Input Disable Register
+ 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
+ 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
+
+# Module PORTE
+ 'PORTE' : '$2e', # Data Register, Port E
+ 'DDRE' : '$2d', # Data Direction Register, Port
+ 'PINE' : '$2c', # Input Pins, Port E
+
+# Module PORTF
+ 'PORTF' : '$31', # Data Register, Port F
+ 'DDRF' : '$30', # Data Direction Register, Port
+ 'PINF' : '$2f', # Input Pins, Port F
+
+# Module PORTG
+ 'PORTG' : '$34', # Port G Data Register
+ 'DDRG' : '$33', # Port G Data Direction Register
+ 'PING' : '$32', # Port G Input Pins
+
+# Module JTAG
+ 'OCDR' : '$51', # On-Chip Debug Related Register
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_JTD': '$80', # JTAG Interface Disable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+
+# Module LCD
+ 'LCDDR18' : '$fe', # LCD Data Register 18
+ 'LCDDR17' : '$fd', # LCD Data Register 17
+ 'LCDDR16' : '$fc', # LCD Data Register 16
+ 'LCDDR15' : '$fb', # LCD Data Register 15
+ 'LCDDR13' : '$f9', # LCD Data Register 13
+ 'LCDDR12' : '$f8', # LCD Data Register 12
+ 'LCDDR11' : '$f7', # LCD Data Register 11
+ 'LCDDR10' : '$f6', # LCD Data Register 10
+ 'LCDDR8' : '$f4', # LCD Data Register 8
+ 'LCDDR7' : '$f3', # LCD Data Register 7
+ 'LCDDR6' : '$f2', # LCD Data Register 6
+ 'LCDDR5' : '$f1', # LCD Data Register 5
+ 'LCDDR3' : '$ef', # LCD Data Register 3
+ 'LCDDR2' : '$ee', # LCD Data Register 2
+ 'LCDDR1' : '$ed', # LCD Data Register 1
+ 'LCDDR0' : '$ec', # LCD Data Register 0
+ 'LCDCCR' : '$e7', # LCD Contrast Control Register
+ 'LCDFRR' : '$e6', # LCD Frame Rate Register
+ 'LCDFRR_LCDPS': '$70', # LCD Prescaler Selects
+ 'LCDFRR_LCDCD': '$7', # LCD Clock Dividers
+ 'LCDCRB' : '$e5', # LCD Control and Status Registe
+ 'LCDCRB_LCDCS': '$80', # LCD CLock Select
+ 'LCDCRB_LCD2B': '$40', # LCD 1/2 Bias Select
+ 'LCDCRB_LCDMUX': '$30', # LCD Mux Selects
+ 'LCDCRB_LCDPM': '$f', # LCD Port Masks
+ 'LCDCRA' : '$e4', # LCD Control Register A
+ 'LCDCRA_LCDEN': '$80', # LCD Enable
+ 'LCDCRA_LCDAB': '$40', # LCD A or B waveform
+ 'LCDCRA_LCDIF': '$10', # LCD Interrupt Flag
+ 'LCDCRA_LCDIE': '$8', # LCD Interrupt Enable
+ 'LCDCRA_LCDBL': '$1', # LCD Blanking
+
+# Module EXTERNAL_INTERRUPT
+ 'EICRA' : '$69', # External Interrupt Control Reg
+ 'EICRA_ISC01': '$2', # External Interrupt Sense Contr
+ 'EICRA_ISC00': '$1', # External Interrupt Sense Contr
+ 'EIMSK' : '$3d', # External Interrupt Mask Regist
+ 'EIMSK_PCIE': '$f0', # Pin Change Interrupt Enables
+ 'EIMSK_INT0': '$1', # External Interrupt Request 0 E
+ 'EIFR' : '$3c', # External Interrupt Flag Regist
+ 'EIFR_PCIF': '$f0', # Pin Change Interrupt Flags
+ 'EIFR_INTF0': '$1', # External Interrupt Flag 0
+ 'PCMSK1' : '$6c', # Pin Change Mask Register 1
+ 'PCMSK0' : '$6b', # Pin Change Mask Register 0
+
+# Module CPU
+ 'SREG' : '$5f', # Status Register
+ 'SREG_I': '$80', # Global Interrupt Enable
+ 'SREG_T': '$40', # Bit Copy Storage
+ 'SREG_H': '$20', # Half Carry Flag
+ 'SREG_S': '$10', # Sign Bit
+ 'SREG_V': '$8', # Two's Complement Overflow Flag
+ 'SREG_N': '$4', # Negative Flag
+ 'SREG_Z': '$2', # Zero Flag
+ 'SREG_C': '$1', # Carry Flag
+ 'SP' : '$5d', # Stack Pointer
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_PUD': '$10', # Pull-up disable
+ 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
+ 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+ 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
+ 'MCUSR_BORF': '$4', # Brown-out Reset Flag
+ 'MCUSR_EXTRF': '$2', # External Reset Flag
+ 'MCUSR_PORF': '$1', # Power-on reset flag
+ 'OSCCAL' : '$66', # Oscillator Calibration Value
+ 'CLKPR' : '$61', # Clock Prescale Register
+ 'CLKPR_CLKPCE': '$80', # Clock Prescaler Change Enable
+ 'CLKPR_CLKPS': '$f', # Clock Prescaler Select Bits
+ 'PRR' : '$64', # Power Reduction Register
+ 'PRR_PRLCD': '$10', # Power Reduction LCD
+ 'PRR_PRTIM1': '$8', # Power Reduction Timer/Counter1
+ 'PRR_PRSPI': '$4', # Power Reduction Serial Periphe
+ 'PRR_PRUSART0': '$2', # Power Reduction USART
+ 'PRR_PRADC': '$1', # Power Reduction ADC
+ 'SMCR' : '$53', # Sleep Mode Control Register
+ 'SMCR_SM': '$e', # Sleep Mode Select bits
+ 'SMCR_SE': '$1', # Sleep Enable
+ 'GPIOR2' : '$4b', # General Purpose IO Register 2
+ 'GPIOR1' : '$4a', # General Purpose IO Register 1
+ 'GPIOR0' : '$3e', # General Purpose IO Register 0
+
+# Module USI
+ 'USIDR' : '$ba', # USI Data Register
+ 'USISR' : '$b9', # USI Status Register
+ 'USISR_USISIF': '$80', # Start Condition Interrupt Flag
+ 'USISR_USIOIF': '$40', # Counter Overflow Interrupt Fla
+ 'USISR_USIPF': '$20', # Stop Condition Flag
+ 'USISR_USIDC': '$10', # Data Output Collision
+ 'USISR_USICNT': '$f', # USI Counter Value Bits
+ 'USICR' : '$b8', # USI Control Register
+ 'USICR_USISIE': '$80', # Start Condition Interrupt Enab
+ 'USICR_USIOIE': '$40', # Counter Overflow Interrupt Ena
+ 'USICR_USIWM': '$30', # USI Wire Mode Bits
+ 'USICR_USICS': '$c', # USI Clock Source Select Bits
+ 'USICR_USICLK': '$2', # Clock Strobe
+ 'USICR_USITC': '$1', # Toggle Clock Port Pin
+
+# Module AD_CONVERTER
+ 'ADMUX' : '$7c', # The ADC multiplexer Selection
+ 'ADMUX_REFS': '$c0', # Reference Selection Bits
+ 'ADMUX_ADLAR': '$20', # Left Adjust Result
+ 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
+ 'ADCSRA' : '$7a', # The ADC Control and Status reg
+ 'ADCSRA_ADEN': '$80', # ADC Enable
+ 'ADCSRA_ADSC': '$40', # ADC Start Conversion
+ 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
+ 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
+ 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
+ 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
+ 'ADC' : '$78', # ADC Data Register Bytes
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Sources
+ 'DIDR0' : '$7e', # Digital Input Disable Register
+ 'DIDR0_ADC7D': '$80', # ADC7 Digital input Disable
+ 'DIDR0_ADC6D': '$40', # ADC6 Digital input Disable
+ 'DIDR0_ADC5D': '$20', # ADC5 Digital input Disable
+ 'DIDR0_ADC4D': '$10', # ADC4 Digital input Disable
+ 'DIDR0_ADC3D': '$8', # ADC3 Digital input Disable
+ 'DIDR0_ADC2D': '$4', # ADC2 Digital input Disable
+ 'DIDR0_ADC1D': '$2', # ADC1 Digital input Disable
+ 'DIDR0_ADC0D': '$1', # ADC0 Digital input Disable
+
+# Module BOOT_LOAD
+ 'SPMCSR' : '$57', # Store Program Memory Control R
+ 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
+ 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
+ 'SPMCSR_RWWSRE': '$10', # Read While Write section read
+ 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
+ 'SPMCSR_PGWRT': '$4', # Page Write
+ 'SPMCSR_PGERS': '$2', # Page Erase
+ 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
+
+# Module USART0
+ 'UDR0' : '$c6', # USART I/O Data Register
+ 'UCSR0A' : '$c0', # USART Control and Status Regis
+ 'UCSR0A_RXC0': '$80', # USART Receive Complete
+ 'UCSR0A_TXC0': '$40', # USART Transmit Complete
+ 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
+ 'UCSR0A_FE0': '$10', # Framing Error
+ 'UCSR0A_DOR0': '$8', # Data OverRun
+ 'UCSR0A_UPE0': '$4', # USART Parity Error
+ 'UCSR0A_U2X0': '$2', # Double the USART Transmission
+ 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
+ 'UCSR0B' : '$c1', # USART Control and Status Regis
+ 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
+ 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
+ 'UCSR0B_UDRIE0': '$20', # USART Data Register Empty Inte
+ 'UCSR0B_RXEN0': '$10', # Receiver Enable
+ 'UCSR0B_TXEN0': '$8', # Transmitter Enable
+ 'UCSR0B_UCSZ02': '$4', # Character Size
+ 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
+ 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
+ 'UCSR0C' : '$c2', # USART Control and Status Regis
+ 'UCSR0C_UMSEL0': '$40', # USART Mode Select
+ 'UCSR0C_UPM0': '$30', # Parity Mode Bits
+ 'UCSR0C_USBS0': '$8', # Stop Bit Select
+ 'UCSR0C_UCSZ0': '$6', # Character Size
+ 'UCSR0C_UCPOL0': '$1', # Clock Polarity
+ 'UBRR0' : '$c4', # USART Baud Rate Register Byte
+
+ '__amforth_dummy':'0'
+}
diff --git a/amforth-6.5/avr8/devices/atmega329/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega329/words/no-jtag.asm
new file mode 100644
index 0000000..352a4bb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega329/words/no-jtag.asm
@@ -0,0 +1,14 @@
+; ( -- )
+; ( -- )
+; MCU
+; disable jtag at runtime
+VE_NOJTAG:
+ .dw $FF05
+ .db "-jtag",0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOJTAG
+XT_NOJTAG:
+ .dw PFA_NOJTAG
+PFA_NOJTAG:
+
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega329/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega329/words/no-wdt.asm
new file mode 100644
index 0000000..4a12261
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega329/words/no-wdt.asm
@@ -0,0 +1,22 @@
+; ( -- )
+; MCU
+; disable watch dog timer at runtime
+VE_NOWDT:
+ .dw $ff04
+ .db "-wdt"
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOWDT
+XT_NOWDT:
+ .dw PFA_NOWDT
+PFA_NOWDT:
+
+; Reset WDT
+ wdr
+; Write logical one to WDTOE and WDE
+ in_ temp1, WDTCR
+ ori temp1, (1<<WDTOE)|(1<<WDE)
+ out WDTCR, temp1
+; Turn off WDT
+ ldi temp1, (0<<WDE)
+ out_ WDTCR, temp1
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega329/words/sleep.asm b/amforth-6.5/avr8/devices/atmega329/words/sleep.asm
new file mode 100644
index 0000000..256249c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega329/words/sleep.asm
@@ -0,0 +1,19 @@
+; ( mode -- )
+; MCU
+; put the controller into the specified sleep mode
+VE_SLEEP:
+ .dw $ff05
+ .db "sleep", 0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_SLEEP
+XT_SLEEP:
+ .dw PFA_SLEEP
+PFA_SLEEP:
+ andi tosl, 7 ; leave only legal mode bits
+ lsl tosl ; move to correct location (bits 3-1)
+ ori tosl, 1 ; set the SE bit
+ out_ SMCR, tosl ; set the sleep config
+ sleep ; nighty-night
+ out_ SMCR, zerol ; 0 protects against accidental sleeps
+ loadtos ; pop argument from stack
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega3290/atmega3290.frt b/amforth-6.5/avr8/devices/atmega3290/atmega3290.frt
new file mode 100644
index 0000000..087c43d
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega3290/atmega3290.frt
@@ -0,0 +1,328 @@
+\ Partname: ATmega3290
+\ generated automatically
+
+\ TIMER_COUNTER_0
+&68 constant TCCR0A \ Timer/Counter0 Control Register
+ $80 constant TCCR0A_FOC0A \ Force Output Compare
+ $40 constant TCCR0A_WGM00 \ Waveform Generation Mode 0
+ $30 constant TCCR0A_COM0A \ Compare Match Output Modes
+ $08 constant TCCR0A_WGM01 \ Waveform Generation Mode 1
+ $07 constant TCCR0A_CS0 \ Clock Selects
+&70 constant TCNT0 \ Timer/Counter0
+&71 constant OCR0A \ Timer/Counter0 Output Compare Register
+&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
+ $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match Interrupt Enable
+ $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
+&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
+ $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0
+ $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
+&67 constant GTCCR \ General Timer/Control Register
+ $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
+ $01 constant GTCCR_PSR310 \ Prescaler Reset Timer/Counter1 and Timer/Counter0
+\ TIMER_COUNTER_1
+&128 constant TCCR1A \ Timer/Counter1 Control Register A
+ $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
+ $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
+ $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
+&129 constant TCCR1B \ Timer/Counter1 Control Register B
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
+ $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
+&130 constant TCCR1C \ Timer/Counter 1 Control Register C
+ $80 constant TCCR1C_FOC1A \ Force Output Compare 1A
+ $40 constant TCCR1C_FOC1B \ Force Output Compare 1B
+&132 constant TCNT1 \ Timer/Counter1 Bytes
+&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
+&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
+&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
+&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
+ $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
+ $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
+ $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
+ $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
+&54 constant TIFR1 \ Timer/Counter1 Interrupt Flag register
+ $20 constant TIFR1_ICF1 \ Input Capture Flag 1
+ $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
+ $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
+ $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
+\ TIMER_COUNTER_2
+&176 constant TCCR2A \ Timer/Counter2 Control Register
+ $80 constant TCCR2A_FOC2A \ Force Output Compare A
+ $40 constant TCCR2A_WGM20 \ Waveform Generation Mode
+ $30 constant TCCR2A_COM2A \ Compare Output Mode bits
+ $08 constant TCCR2A_WGM21 \ Waveform Generation Mode
+ $07 constant TCCR2A_CS2 \ Clock Select bits
+&178 constant TCNT2 \ Timer/Counter2
+&179 constant OCR2A \ Timer/Counter2 Output Compare Register
+&112 constant TIMSK2 \ Timer/Counter2 Interrupt Mask register
+ $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match Interrupt Enable
+ $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
+&55 constant TIFR2 \ Timer/Counter2 Interrupt Flag Register
+ $02 constant TIFR2_OCF2A \ Timer/Counter2 Output Compare Flag 2
+ $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
+&182 constant ASSR \ Asynchronous Status Register
+ $10 constant ASSR_EXCLK \ Enable External Clock Interrupt
+ $08 constant ASSR_AS2 \ AS2: Asynchronous Timer/Counter2
+ $04 constant ASSR_TCN2UB \ TCN2UB: Timer/Counter2 Update Busy
+ $02 constant ASSR_OCR2UB \ Output Compare Register2 Update Busy
+ $01 constant ASSR_TCR2UB \ TCR2UB: Timer/Counter Control Register2 Update Busy
+\ WATCHDOG
+&96 constant WDTCR \ Watchdog Timer Control Register
+ $10 constant WDTCR_WDCE \ Watchdog Change Enable
+ $08 constant WDTCR_WDE \ Watch Dog Enable
+ $07 constant WDTCR_WDP \ Watch Dog Timer Prescaler bits
+\ EEPROM
+&65 constant EEAR \ EEPROM Read/Write Access Bytes
+&64 constant EEDR \ EEPROM Data Register
+&63 constant EECR \ EEPROM Control Register
+ $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
+ $04 constant EECR_EEMWE \ EEPROM Master Write Enable
+ $02 constant EECR_EEWE \ EEPROM Write Enable
+ $01 constant EECR_EERE \ EEPROM Read Enable
+\ SPI
+&76 constant SPCR \ SPI Control Register
+ $80 constant SPCR_SPIE \ SPI Interrupt Enable
+ $40 constant SPCR_SPE \ SPI Enable
+ $20 constant SPCR_DORD \ Data Order
+ $10 constant SPCR_MSTR \ Master/Slave Select
+ $08 constant SPCR_CPOL \ Clock polarity
+ $04 constant SPCR_CPHA \ Clock Phase
+ $03 constant SPCR_SPR \ SPI Clock Rate Selects
+&77 constant SPSR \ SPI Status Register
+ $80 constant SPSR_SPIF \ SPI Interrupt Flag
+ $40 constant SPSR_WCOL \ Write Collision Flag
+ $01 constant SPSR_SPI2X \ Double SPI Speed Bit
+&78 constant SPDR \ SPI Data Register
+\ PORTA
+&34 constant PORTA \ Port A Data Register
+&33 constant DDRA \ Port A Data Direction Register
+&32 constant PINA \ Port A Input Pins
+\ PORTB
+&37 constant PORTB \ Port B Data Register
+&36 constant DDRB \ Port B Data Direction Register
+&35 constant PINB \ Port B Input Pins
+\ PORTC
+&40 constant PORTC \ Port C Data Register
+&39 constant DDRC \ Port C Data Direction Register
+&38 constant PINC \ Port C Input Pins
+\ PORTD
+&43 constant PORTD \ Port D Data Register
+&42 constant DDRD \ Port D Data Direction Register
+&41 constant PIND \ Port D Input Pins
+\ ANALOG_COMPARATOR
+&123 constant ADCSRB \ ADC Control and Status Register B
+ $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer Enable
+&80 constant ACSR \ Analog Comparator Control And Status Register
+ $80 constant ACSR_ACD \ Analog Comparator Disable
+ $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
+ $20 constant ACSR_ACO \ Analog Compare Output
+ $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
+ $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
+ $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
+ $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
+&127 constant DIDR1 \ Digital Input Disable Register 1
+ $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
+ $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
+\ PORTE
+&46 constant PORTE \ Data Register, Port E
+&45 constant DDRE \ Data Direction Register, Port E
+&44 constant PINE \ Input Pins, Port E
+\ PORTF
+&49 constant PORTF \ Data Register, Port F
+&48 constant DDRF \ Data Direction Register, Port F
+&47 constant PINF \ Input Pins, Port F
+\ PORTG
+&52 constant PORTG \ Port G Data Register
+&51 constant DDRG \ Port G Data Direction Register
+&50 constant PING \ Port G Input Pins
+\ JTAG
+&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
+&85 constant MCUCR \ MCU Control Register
+ $80 constant MCUCR_JTD \ JTAG Interface Disable
+&84 constant MCUSR \ MCU Status Register
+ $10 constant MCUSR_JTRF \ JTAG Reset Flag
+\ LCD
+&255 constant LCDDR19 \ LCD Data Register 19
+&254 constant LCDDR18 \ LCD Data Register 18
+&253 constant LCDDR17 \ LCD Data Register 17
+&252 constant LCDDR16 \ LCD Data Register 16
+&251 constant LCDDR15 \ LCD Data Register 15
+&250 constant LCDDR14 \ LCD Data Register 14
+&249 constant LCDDR13 \ LCD Data Register 13
+&248 constant LCDDR12 \ LCD Data Register 12
+&247 constant LCDDR11 \ LCD Data Register 11
+&246 constant LCDDR10 \ LCD Data Register 10
+&245 constant LCDDR9 \ LCD Data Register 9
+&244 constant LCDDR8 \ LCD Data Register 8
+&243 constant LCDDR7 \ LCD Data Register 7
+&242 constant LCDDR6 \ LCD Data Register 6
+&241 constant LCDDR5 \ LCD Data Register 5
+&240 constant LCDDR4 \ LCD Data Register 4
+&239 constant LCDDR3 \ LCD Data Register 3
+&238 constant LCDDR2 \ LCD Data Register 2
+&237 constant LCDDR1 \ LCD Data Register 1
+&236 constant LCDDR0 \ LCD Data Register 0
+&231 constant LCDCCR \ LCD Contrast Control Register
+&230 constant LCDFRR \ LCD Frame Rate Register
+ $70 constant LCDFRR_LCDPS \ LCD Prescaler Selects
+ $07 constant LCDFRR_LCDCD \ LCD Clock Dividers
+&229 constant LCDCRB \ LCD Control and Status Register B
+ $80 constant LCDCRB_LCDCS \ LCD CLock Select
+ $40 constant LCDCRB_LCD2B \ LCD 1/2 Bias Select
+ $30 constant LCDCRB_LCDMUX \ LCD Mux Selects
+ $0F constant LCDCRB_LCDPM \ LCD Port Masks
+&228 constant LCDCRA \ LCD Control and Status Register A
+ $80 constant LCDCRA_LCDEN \ LCD Enable
+ $40 constant LCDCRA_LCDAB \ LCD A or B waveform
+ $10 constant LCDCRA_LCDIF \ LCD Interrupt Flag
+ $08 constant LCDCRA_LCDIE \ LCD Interrupt Enable
+ $01 constant LCDCRA_LCDBL \ LCD Blanking
+\ EXTERNAL_INTERRUPT
+&105 constant EICRA \ External Interrupt Control Register A
+ $02 constant EICRA_ISC01 \ External Interrupt Sense Control 0 Bit 1
+ $01 constant EICRA_ISC00 \ External Interrupt Sense Control 0 Bit 0
+&61 constant EIMSK \ External Interrupt Mask Register
+ $F0 constant EIMSK_PCIE \ Pin Change Interrupt Enables
+ $01 constant EIMSK_INT0 \ External Interrupt Request 0 Enable
+&60 constant EIFR \ External Interrupt Flag Register
+ $F0 constant EIFR_PCIF \ Pin Change Interrupt Flags
+ $01 constant EIFR_INTF0 \ External Interrupt Flag 0
+&115 constant PCMSK3 \ Pin Change Mask Register 3
+&109 constant PCMSK2 \ Pin Change Mask Register 2
+&108 constant PCMSK1 \ Pin Change Mask Register 1
+&107 constant PCMSK0 \ Pin Change Mask Register 0
+\ CPU
+&95 constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ $08 constant SREG_V \ Two's Complement Overflow Flag
+ $04 constant SREG_N \ Negative Flag
+ $02 constant SREG_Z \ Zero Flag
+ $01 constant SREG_C \ Carry Flag
+&93 constant SP \ Stack Pointer
+&102 constant OSCCAL \ Oscillator Calibration Value
+&97 constant CLKPR \ Clock Prescale Register
+ $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable
+ $0F constant CLKPR_CLKPS \ Clock Prescaler Select Bits
+&100 constant PRR \ Power Reduction Register
+ $10 constant PRR_PRLCD \ Power Reduction LCD
+ $08 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
+ $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
+ $02 constant PRR_PRUSART0 \ Power Reduction USART
+ $01 constant PRR_PRADC \ Power Reduction ADC
+&83 constant SMCR \ Sleep Mode Control Register
+ $0E constant SMCR_SM \ Sleep Mode Select bits
+ $01 constant SMCR_SE \ Sleep Enable
+&75 constant GPIOR2 \ General Purpose IO Register 2
+&74 constant GPIOR1 \ General Purpose IO Register 1
+&62 constant GPIOR0 \ General Purpose IO Register 0
+\ USI
+&186 constant USIDR \ USI Data Register
+&185 constant USISR \ USI Status Register
+ $80 constant USISR_USISIF \ Start Condition Interrupt Flag
+ $40 constant USISR_USIOIF \ Counter Overflow Interrupt Flag
+ $20 constant USISR_USIPF \ Stop Condition Flag
+ $10 constant USISR_USIDC \ Data Output Collision
+ $0F constant USISR_USICNT \ USI Counter Value Bits
+&184 constant USICR \ USI Control Register
+ $80 constant USICR_USISIE \ Start Condition Interrupt Enable
+ $40 constant USICR_USIOIE \ Counter Overflow Interrupt Enable
+ $30 constant USICR_USIWM \ USI Wire Mode Bits
+ $0C constant USICR_USICS \ USI Clock Source Select Bits
+ $02 constant USICR_USICLK \ Clock Strobe
+ $01 constant USICR_USITC \ Toggle Clock Port Pin
+\ AD_CONVERTER
+&124 constant ADMUX \ The ADC multiplexer Selection Register
+ $C0 constant ADMUX_REFS \ Reference Selection Bits
+ $20 constant ADMUX_ADLAR \ Left Adjust Result
+ $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
+&122 constant ADCSRA \ The ADC Control and Status register
+ $80 constant ADCSRA_ADEN \ ADC Enable
+ $40 constant ADCSRA_ADSC \ ADC Start Conversion
+ $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
+ $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
+ $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
+ $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
+&120 constant ADC \ ADC Data Register Bytes
+&126 constant DIDR0 \ Digital Input Disable Register 0
+ $80 constant DIDR0_ADC7D \ ADC7 Digital input Disable
+ $40 constant DIDR0_ADC6D \ ADC6 Digital input Disable
+ $20 constant DIDR0_ADC5D \ ADC5 Digital input Disable
+ $10 constant DIDR0_ADC4D \ ADC4 Digital input Disable
+ $08 constant DIDR0_ADC3D \ ADC3 Digital input Disable
+ $04 constant DIDR0_ADC2D \ ADC2 Digital input Disable
+ $02 constant DIDR0_ADC1D \ ADC1 Digital input Disable
+ $01 constant DIDR0_ADC0D \ ADC0 Digital input Disable
+\ BOOT_LOAD
+&87 constant SPMCSR \ Store Program Memory Control Register
+ $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
+ $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
+ $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
+ $04 constant SPMCSR_PGWRT \ Page Write
+ $02 constant SPMCSR_PGERS \ Page Erase
+ $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
+\ USART0
+&198 constant UDR0 \ USART I/O Data Register
+&192 constant UCSR0A \ USART Control and Status Register A
+ $80 constant UCSR0A_RXC0 \ USART Receive Complete
+ $40 constant UCSR0A_TXC0 \ USART Transmit Complete
+ $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
+ $10 constant UCSR0A_FE0 \ Framing Error
+ $08 constant UCSR0A_DOR0 \ Data OverRun
+ $04 constant UCSR0A_UPE0 \ USART Parity Error
+ $02 constant UCSR0A_U2X0 \ Double the USART Transmission Speed
+ $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
+&193 constant UCSR0B \ USART Control and Status Register B
+ $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
+ $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
+ $20 constant UCSR0B_UDRIE0 \ USART Data Register Empty Interrupt Enable
+ $10 constant UCSR0B_RXEN0 \ Receiver Enable
+ $08 constant UCSR0B_TXEN0 \ Transmitter Enable
+ $04 constant UCSR0B_UCSZ02 \ Character Size
+ $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
+ $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
+&194 constant UCSR0C \ USART Control and Status Register C
+ $40 constant UCSR0C_UMSEL0 \ USART Mode Select
+ $30 constant UCSR0C_UPM0 \ Parity Mode Bits
+ $08 constant UCSR0C_USBS0 \ Stop Bit Select
+ $06 constant UCSR0C_UCSZ0 \ Character Size
+ $01 constant UCSR0C_UCPOL0 \ Clock Polarity
+&196 constant UBRR0 \ USART Baud Rate Register Bytes
+\ PORTH
+&218 constant PORTH \ PORT H Data Register
+&217 constant DDRH \ PORT H Data Direction Register
+&216 constant PINH \ PORT H Input Pins
+\ PORTJ
+&221 constant PORTJ \ PORT J Data Register
+&220 constant DDRJ \ PORT J Data Direction Register
+&219 constant PINJ \ PORT J Input Pins
+
+\ Interrupts
+&2 constant INT0Addr \ External Interrupt Request 0
+&4 constant PCINT0Addr \ Pin Change Interrupt Request 0
+&6 constant PCINT1Addr \ Pin Change Interrupt Request 1
+&8 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
+&10 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
+&12 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+&14 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
+&16 constant TIMER1_COMPBAddr \ Timer/Counter Compare Match B
+&18 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+&20 constant TIMER0_COMPAddr \ Timer/Counter0 Compare Match
+&22 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
+&24 constant SPI__STCAddr \ SPI Serial Transfer Complete
+&26 constant USART__RXAddr \ USART, Rx Complete
+&28 constant USART__UDREAddr \ USART Data register Empty
+&30 constant USART0__TXAddr \ USART0, Tx Complete
+&32 constant USI_STARTAddr \ USI Start Condition
+&34 constant USI_OVERFLOWAddr \ USI Overflow
+&36 constant ANALOG_COMPAddr \ Analog Comparator
+&38 constant ADCAddr \ ADC Conversion Complete
+&40 constant EE_READYAddr \ EEPROM Ready
+&42 constant SPM_READYAddr \ Store Program Memory Read
+&44 constant LCDAddr \ LCD Start of Frame
+&46 constant PCINT2Addr \ Pin Change Interrupt Request 2
+&48 constant PCINT3Addr \ Pin Change Interrupt Request 3
diff --git a/amforth-6.5/avr8/devices/atmega3290/device.asm b/amforth-6.5/avr8/devices/atmega3290/device.asm
new file mode 100644
index 0000000..08426f4
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega3290/device.asm
@@ -0,0 +1,115 @@
+; Partname: ATmega3290
+; generated automatically, do not edit
+
+.nolist
+ .include "m3290def.inc"
+.list
+
+.equ ramstart = 256
+.equ CELLSIZE = 2
+.macro readflashcell
+ lsl zl
+ rol zh
+ lpm @0, Z+
+ lpm @1, Z+
+.endmacro
+.macro writeflashcell
+ lsl zl
+ rol zh
+.endmacro
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_TIMER_COUNTER_2 = 0
+.set WANT_WATCHDOG = 0
+.set WANT_EEPROM = 0
+.set WANT_SPI = 0
+.set WANT_PORTA = 0
+.set WANT_PORTB = 0
+.set WANT_PORTC = 0
+.set WANT_PORTD = 0
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_PORTE = 0
+.set WANT_PORTF = 0
+.set WANT_PORTG = 0
+.set WANT_JTAG = 0
+.set WANT_LCD = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_CPU = 0
+.set WANT_USI = 0
+.set WANT_AD_CONVERTER = 0
+.set WANT_BOOT_LOAD = 0
+.set WANT_USART0 = 0
+.set WANT_PORTH = 0
+.set WANT_PORTJ = 0
+.equ intvecsize = 2 ; please verify; flash size: 32768 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.org 2
+ rcall isr ; External Interrupt Request 0
+.org 4
+ rcall isr ; Pin Change Interrupt Request 0
+.org 6
+ rcall isr ; Pin Change Interrupt Request 1
+.org 8
+ rcall isr ; Timer/Counter2 Compare Match
+.org 10
+ rcall isr ; Timer/Counter2 Overflow
+.org 12
+ rcall isr ; Timer/Counter1 Capture Event
+.org 14
+ rcall isr ; Timer/Counter1 Compare Match A
+.org 16
+ rcall isr ; Timer/Counter Compare Match B
+.org 18
+ rcall isr ; Timer/Counter1 Overflow
+.org 20
+ rcall isr ; Timer/Counter0 Compare Match
+.org 22
+ rcall isr ; Timer/Counter0 Overflow
+.org 24
+ rcall isr ; SPI Serial Transfer Complete
+.org 26
+ rcall isr ; USART, Rx Complete
+.org 28
+ rcall isr ; USART Data register Empty
+.org 30
+ rcall isr ; USART0, Tx Complete
+.org 32
+ rcall isr ; USI Start Condition
+.org 34
+ rcall isr ; USI Overflow
+.org 36
+ rcall isr ; Analog Comparator
+.org 38
+ rcall isr ; ADC Conversion Complete
+.org 40
+ rcall isr ; EEPROM Ready
+.org 42
+ rcall isr ; Store Program Memory Read
+.org 44
+ rcall isr ; LCD Start of Frame
+.org 46
+ rcall isr ; Pin Change Interrupt Request 2
+.org 48
+ rcall isr ; Pin Change Interrupt Request 3
+.equ INTVECTORS = 25
+.nooverlap
+
+; compatability layer (maybe empty)
+.equ EEPE = EEWE
+.equ EEMPE = EEMWE
+
+; controller data area, environment query mcu-info
+mcu_info:
+mcu_ramsize:
+ .dw 2048
+mcu_eepromsize:
+ .dw 1024
+mcu_maxdp:
+ .dw 28672
+mcu_numints:
+ .dw 25
+mcu_name:
+ .dw 10
+ .db "ATmega3290"
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega3290/device.inc b/amforth-6.5/avr8/devices/atmega3290/device.inc
new file mode 100644
index 0000000..ac2eebd
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega3290/device.inc
@@ -0,0 +1,1443 @@
+; Partname: ATmega3290
+; generated automatically, no not edit
+
+.if WANT_TIMER_COUNTER_0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Control Register
+VE_TCCR0A:
+ .dw $ff06
+ .db "TCCR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0A
+XT_TCCR0A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0A:
+ .dw 68
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw 70
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0A:
+ .dw $ff05
+ .db "OCR0A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0A
+XT_OCR0A:
+ .dw PFA_DOVARIABLE
+PFA_OCR0A:
+ .dw 71
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Mask Register
+VE_TIMSK0:
+ .dw $ff06
+ .db "TIMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK0
+XT_TIMSK0:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK0:
+ .dw 110
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Flag register
+VE_TIFR0:
+ .dw $ff05
+ .db "TIFR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR0
+XT_TIFR0:
+ .dw PFA_DOVARIABLE
+PFA_TIFR0:
+ .dw 53
+; ( -- addr ) System Constant
+; R( -- )
+; General Timer/Control Register
+VE_GTCCR:
+ .dw $ff05
+ .db "GTCCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GTCCR
+XT_GTCCR:
+ .dw PFA_DOVARIABLE
+PFA_GTCCR:
+ .dw 67
+
+.endif
+.if WANT_TIMER_COUNTER_1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw 128
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw 129
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter 1 Control Register C
+VE_TCCR1C:
+ .dw $ff06
+ .db "TCCR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1C
+XT_TCCR1C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1C:
+ .dw 130
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Bytes
+VE_TCNT1:
+ .dw $ff05
+ .db "TCNT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1
+XT_TCNT1:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1:
+ .dw 132
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register A Bytes
+VE_OCR1A:
+ .dw $ff05
+ .db "OCR1A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1A
+XT_OCR1A:
+ .dw PFA_DOVARIABLE
+PFA_OCR1A:
+ .dw 136
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register B Bytes
+VE_OCR1B:
+ .dw $ff05
+ .db "OCR1B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1B
+XT_OCR1B:
+ .dw PFA_DOVARIABLE
+PFA_OCR1B:
+ .dw 138
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Bytes
+VE_ICR1:
+ .dw $ff04
+ .db "ICR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1
+XT_ICR1:
+ .dw PFA_DOVARIABLE
+PFA_ICR1:
+ .dw 134
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Mask Register
+VE_TIMSK1:
+ .dw $ff06
+ .db "TIMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK1
+XT_TIMSK1:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK1:
+ .dw 111
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Flag register
+VE_TIFR1:
+ .dw $ff05
+ .db "TIFR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR1
+XT_TIFR1:
+ .dw PFA_DOVARIABLE
+PFA_TIFR1:
+ .dw 54
+
+.endif
+.if WANT_TIMER_COUNTER_2 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register
+VE_TCCR2A:
+ .dw $ff06
+ .db "TCCR2A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2A
+XT_TCCR2A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2A:
+ .dw 176
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2
+VE_TCNT2:
+ .dw $ff05
+ .db "TCNT2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT2
+XT_TCNT2:
+ .dw PFA_DOVARIABLE
+PFA_TCNT2:
+ .dw 178
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register
+VE_OCR2A:
+ .dw $ff05
+ .db "OCR2A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2A
+XT_OCR2A:
+ .dw PFA_DOVARIABLE
+PFA_OCR2A:
+ .dw 179
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Interrupt Mask register
+VE_TIMSK2:
+ .dw $ff06
+ .db "TIMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK2
+XT_TIMSK2:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK2:
+ .dw 112
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Interrupt Flag Register
+VE_TIFR2:
+ .dw $ff05
+ .db "TIFR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR2
+XT_TIFR2:
+ .dw PFA_DOVARIABLE
+PFA_TIFR2:
+ .dw 55
+; ( -- addr ) System Constant
+; R( -- )
+; Asynchronous Status Register
+VE_ASSR:
+ .dw $ff04
+ .db "ASSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ASSR
+XT_ASSR:
+ .dw PFA_DOVARIABLE
+PFA_ASSR:
+ .dw 182
+
+.endif
+.if WANT_WATCHDOG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCR:
+ .dw $ff05
+ .db "WDTCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCR
+XT_WDTCR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCR:
+ .dw 96
+
+.endif
+.if WANT_EEPROM == 1
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Read/Write Access Bytes
+VE_EEAR:
+ .dw $ff04
+ .db "EEAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEAR
+XT_EEAR:
+ .dw PFA_DOVARIABLE
+PFA_EEAR:
+ .dw 65
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw 64
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw 63
+
+.endif
+.if WANT_SPI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR:
+ .dw $ff04
+ .db "SPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR
+XT_SPCR:
+ .dw PFA_DOVARIABLE
+PFA_SPCR:
+ .dw 76
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR:
+ .dw $ff04
+ .db "SPSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR
+XT_SPSR:
+ .dw PFA_DOVARIABLE
+PFA_SPSR:
+ .dw 77
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR:
+ .dw $ff04
+ .db "SPDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR
+XT_SPDR:
+ .dw PFA_DOVARIABLE
+PFA_SPDR:
+ .dw 78
+
+.endif
+.if WANT_PORTA == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Register
+VE_PORTA:
+ .dw $ff05
+ .db "PORTA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTA
+XT_PORTA:
+ .dw PFA_DOVARIABLE
+PFA_PORTA:
+ .dw 34
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Direction Register
+VE_DDRA:
+ .dw $ff04
+ .db "DDRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRA
+XT_DDRA:
+ .dw PFA_DOVARIABLE
+PFA_DDRA:
+ .dw 33
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Input Pins
+VE_PINA:
+ .dw $ff04
+ .db "PINA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINA
+XT_PINA:
+ .dw PFA_DOVARIABLE
+PFA_PINA:
+ .dw 32
+
+.endif
+.if WANT_PORTB == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw 37
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw 36
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw 35
+
+.endif
+.if WANT_PORTC == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Register
+VE_PORTC:
+ .dw $ff05
+ .db "PORTC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTC
+XT_PORTC:
+ .dw PFA_DOVARIABLE
+PFA_PORTC:
+ .dw 40
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Direction Register
+VE_DDRC:
+ .dw $ff04
+ .db "DDRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRC
+XT_DDRC:
+ .dw PFA_DOVARIABLE
+PFA_DDRC:
+ .dw 39
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Input Pins
+VE_PINC:
+ .dw $ff04
+ .db "PINC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINC
+XT_PINC:
+ .dw PFA_DOVARIABLE
+PFA_PINC:
+ .dw 38
+
+.endif
+.if WANT_PORTD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw 43
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw 42
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw 41
+
+.endif
+.if WANT_ANALOG_COMPARATOR == 1
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Control and Status Register B
+VE_ADCSRB:
+ .dw $ff06
+ .db "ADCSRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRB
+XT_ADCSRB:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRB:
+ .dw 123
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Control And Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw 80
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 1
+VE_DIDR1:
+ .dw $ff05
+ .db "DIDR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR1
+XT_DIDR1:
+ .dw PFA_DOVARIABLE
+PFA_DIDR1:
+ .dw 127
+
+.endif
+.if WANT_PORTE == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port E
+VE_PORTE:
+ .dw $ff05
+ .db "PORTE",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTE
+XT_PORTE:
+ .dw PFA_DOVARIABLE
+PFA_PORTE:
+ .dw 46
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port E
+VE_DDRE:
+ .dw $ff04
+ .db "DDRE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRE
+XT_DDRE:
+ .dw PFA_DOVARIABLE
+PFA_DDRE:
+ .dw 45
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port E
+VE_PINE:
+ .dw $ff04
+ .db "PINE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINE
+XT_PINE:
+ .dw PFA_DOVARIABLE
+PFA_PINE:
+ .dw 44
+
+.endif
+.if WANT_PORTF == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port F
+VE_PORTF:
+ .dw $ff05
+ .db "PORTF",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTF
+XT_PORTF:
+ .dw PFA_DOVARIABLE
+PFA_PORTF:
+ .dw 49
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port F
+VE_DDRF:
+ .dw $ff04
+ .db "DDRF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRF
+XT_DDRF:
+ .dw PFA_DOVARIABLE
+PFA_DDRF:
+ .dw 48
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port F
+VE_PINF:
+ .dw $ff04
+ .db "PINF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINF
+XT_PINF:
+ .dw PFA_DOVARIABLE
+PFA_PINF:
+ .dw 47
+
+.endif
+.if WANT_PORTG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Data Register
+VE_PORTG:
+ .dw $ff05
+ .db "PORTG",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTG
+XT_PORTG:
+ .dw PFA_DOVARIABLE
+PFA_PORTG:
+ .dw 52
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Data Direction Register
+VE_DDRG:
+ .dw $ff04
+ .db "DDRG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRG
+XT_DDRG:
+ .dw PFA_DOVARIABLE
+PFA_DDRG:
+ .dw 51
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Input Pins
+VE_PING:
+ .dw $ff04
+ .db "PING"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PING
+XT_PING:
+ .dw PFA_DOVARIABLE
+PFA_PING:
+ .dw 50
+
+.endif
+.if WANT_JTAG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; On-Chip Debug Related Register in I/O Memory
+VE_OCDR:
+ .dw $ff04
+ .db "OCDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCDR
+XT_OCDR:
+ .dw PFA_DOVARIABLE
+PFA_OCDR:
+ .dw 81
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw 85
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Status Register
+VE_MCUSR:
+ .dw $ff05
+ .db "MCUSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUSR
+XT_MCUSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUSR:
+ .dw 84
+
+.endif
+.if WANT_LCD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 19
+VE_LCDDR19:
+ .dw $ff07
+ .db "LCDDR19",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR19
+XT_LCDDR19:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR19:
+ .dw 255
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 18
+VE_LCDDR18:
+ .dw $ff07
+ .db "LCDDR18",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR18
+XT_LCDDR18:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR18:
+ .dw 254
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 17
+VE_LCDDR17:
+ .dw $ff07
+ .db "LCDDR17",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR17
+XT_LCDDR17:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR17:
+ .dw 253
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 16
+VE_LCDDR16:
+ .dw $ff07
+ .db "LCDDR16",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR16
+XT_LCDDR16:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR16:
+ .dw 252
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 15
+VE_LCDDR15:
+ .dw $ff07
+ .db "LCDDR15",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR15
+XT_LCDDR15:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR15:
+ .dw 251
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 14
+VE_LCDDR14:
+ .dw $ff07
+ .db "LCDDR14",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR14
+XT_LCDDR14:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR14:
+ .dw 250
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 13
+VE_LCDDR13:
+ .dw $ff07
+ .db "LCDDR13",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR13
+XT_LCDDR13:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR13:
+ .dw 249
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 12
+VE_LCDDR12:
+ .dw $ff07
+ .db "LCDDR12",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR12
+XT_LCDDR12:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR12:
+ .dw 248
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 11
+VE_LCDDR11:
+ .dw $ff07
+ .db "LCDDR11",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR11
+XT_LCDDR11:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR11:
+ .dw 247
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 10
+VE_LCDDR10:
+ .dw $ff07
+ .db "LCDDR10",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR10
+XT_LCDDR10:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR10:
+ .dw 246
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 9
+VE_LCDDR9:
+ .dw $ff06
+ .db "LCDDR9"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR9
+XT_LCDDR9:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR9:
+ .dw 245
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 8
+VE_LCDDR8:
+ .dw $ff06
+ .db "LCDDR8"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR8
+XT_LCDDR8:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR8:
+ .dw 244
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 7
+VE_LCDDR7:
+ .dw $ff06
+ .db "LCDDR7"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR7
+XT_LCDDR7:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR7:
+ .dw 243
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 6
+VE_LCDDR6:
+ .dw $ff06
+ .db "LCDDR6"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR6
+XT_LCDDR6:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR6:
+ .dw 242
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 5
+VE_LCDDR5:
+ .dw $ff06
+ .db "LCDDR5"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR5
+XT_LCDDR5:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR5:
+ .dw 241
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 4
+VE_LCDDR4:
+ .dw $ff06
+ .db "LCDDR4"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR4
+XT_LCDDR4:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR4:
+ .dw 240
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 3
+VE_LCDDR3:
+ .dw $ff06
+ .db "LCDDR3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR3
+XT_LCDDR3:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR3:
+ .dw 239
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 2
+VE_LCDDR2:
+ .dw $ff06
+ .db "LCDDR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR2
+XT_LCDDR2:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR2:
+ .dw 238
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 1
+VE_LCDDR1:
+ .dw $ff06
+ .db "LCDDR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR1
+XT_LCDDR1:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR1:
+ .dw 237
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 0
+VE_LCDDR0:
+ .dw $ff06
+ .db "LCDDR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR0
+XT_LCDDR0:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR0:
+ .dw 236
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Contrast Control Register
+VE_LCDCCR:
+ .dw $ff06
+ .db "LCDCCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDCCR
+XT_LCDCCR:
+ .dw PFA_DOVARIABLE
+PFA_LCDCCR:
+ .dw 231
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Frame Rate Register
+VE_LCDFRR:
+ .dw $ff06
+ .db "LCDFRR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDFRR
+XT_LCDFRR:
+ .dw PFA_DOVARIABLE
+PFA_LCDFRR:
+ .dw 230
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Control and Status Register B
+VE_LCDCRB:
+ .dw $ff06
+ .db "LCDCRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDCRB
+XT_LCDCRB:
+ .dw PFA_DOVARIABLE
+PFA_LCDCRB:
+ .dw 229
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Control and Status Register A
+VE_LCDCRA:
+ .dw $ff06
+ .db "LCDCRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDCRA
+XT_LCDCRA:
+ .dw PFA_DOVARIABLE
+PFA_LCDCRA:
+ .dw 228
+
+.endif
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register A
+VE_EICRA:
+ .dw $ff05
+ .db "EICRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRA
+XT_EICRA:
+ .dw PFA_DOVARIABLE
+PFA_EICRA:
+ .dw 105
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Mask Register
+VE_EIMSK:
+ .dw $ff05
+ .db "EIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIMSK
+XT_EIMSK:
+ .dw PFA_DOVARIABLE
+PFA_EIMSK:
+ .dw 61
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Flag Register
+VE_EIFR:
+ .dw $ff04
+ .db "EIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIFR
+XT_EIFR:
+ .dw PFA_DOVARIABLE
+PFA_EIFR:
+ .dw 60
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 3
+VE_PCMSK3:
+ .dw $ff06
+ .db "PCMSK3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK3
+XT_PCMSK3:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK3:
+ .dw 115
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 2
+VE_PCMSK2:
+ .dw $ff06
+ .db "PCMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK2
+XT_PCMSK2:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK2:
+ .dw 109
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 1
+VE_PCMSK1:
+ .dw $ff06
+ .db "PCMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK1
+XT_PCMSK1:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK1:
+ .dw 108
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 0
+VE_PCMSK0:
+ .dw $ff06
+ .db "PCMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK0
+XT_PCMSK0:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK0:
+ .dw 107
+
+.endif
+.if WANT_CPU == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw 95
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer
+VE_SP:
+ .dw $ff02
+ .db "SP"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SP
+XT_SP:
+ .dw PFA_DOVARIABLE
+PFA_SP:
+ .dw 93
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Calibration Value
+VE_OSCCAL:
+ .dw $ff06
+ .db "OSCCAL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSCCAL
+XT_OSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_OSCCAL:
+ .dw 102
+; ( -- addr ) System Constant
+; R( -- )
+; Clock Prescale Register
+VE_CLKPR:
+ .dw $ff05
+ .db "CLKPR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKPR
+XT_CLKPR:
+ .dw PFA_DOVARIABLE
+PFA_CLKPR:
+ .dw 97
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register
+VE_PRR:
+ .dw $ff03
+ .db "PRR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR
+XT_PRR:
+ .dw PFA_DOVARIABLE
+PFA_PRR:
+ .dw 100
+; ( -- addr ) System Constant
+; R( -- )
+; Sleep Mode Control Register
+VE_SMCR:
+ .dw $ff04
+ .db "SMCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SMCR
+XT_SMCR:
+ .dw PFA_DOVARIABLE
+PFA_SMCR:
+ .dw 83
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 2
+VE_GPIOR2:
+ .dw $ff06
+ .db "GPIOR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR2
+XT_GPIOR2:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR2:
+ .dw 75
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 1
+VE_GPIOR1:
+ .dw $ff06
+ .db "GPIOR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR1
+XT_GPIOR1:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR1:
+ .dw 74
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 0
+VE_GPIOR0:
+ .dw $ff06
+ .db "GPIOR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR0
+XT_GPIOR0:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR0:
+ .dw 62
+
+.endif
+.if WANT_USI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USI Data Register
+VE_USIDR:
+ .dw $ff05
+ .db "USIDR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USIDR
+XT_USIDR:
+ .dw PFA_DOVARIABLE
+PFA_USIDR:
+ .dw 186
+; ( -- addr ) System Constant
+; R( -- )
+; USI Status Register
+VE_USISR:
+ .dw $ff05
+ .db "USISR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USISR
+XT_USISR:
+ .dw PFA_DOVARIABLE
+PFA_USISR:
+ .dw 185
+; ( -- addr ) System Constant
+; R( -- )
+; USI Control Register
+VE_USICR:
+ .dw $ff05
+ .db "USICR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USICR
+XT_USICR:
+ .dw PFA_DOVARIABLE
+PFA_USICR:
+ .dw 184
+
+.endif
+.if WANT_AD_CONVERTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC multiplexer Selection Register
+VE_ADMUX:
+ .dw $ff05
+ .db "ADMUX",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADMUX
+XT_ADMUX:
+ .dw PFA_DOVARIABLE
+PFA_ADMUX:
+ .dw 124
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register
+VE_ADCSRA:
+ .dw $ff06
+ .db "ADCSRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRA
+XT_ADCSRA:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRA:
+ .dw 122
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register Bytes
+VE_ADC:
+ .dw $ff03
+ .db "ADC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADC
+XT_ADC:
+ .dw PFA_DOVARIABLE
+PFA_ADC:
+ .dw 120
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 0
+VE_DIDR0:
+ .dw $ff05
+ .db "DIDR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR0
+XT_DIDR0:
+ .dw PFA_DOVARIABLE
+PFA_DIDR0:
+ .dw 126
+
+.endif
+.if WANT_BOOT_LOAD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control Register
+VE_SPMCSR:
+ .dw $ff06
+ .db "SPMCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCSR
+XT_SPMCSR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCSR:
+ .dw 87
+
+.endif
+.if WANT_USART0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR0:
+ .dw $ff04
+ .db "UDR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR0
+XT_UDR0:
+ .dw PFA_DOVARIABLE
+PFA_UDR0:
+ .dw 198
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR0A:
+ .dw $ff06
+ .db "UCSR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0A
+XT_UCSR0A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0A:
+ .dw 192
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR0B:
+ .dw $ff06
+ .db "UCSR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0B
+XT_UCSR0B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0B:
+ .dw 193
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR0C:
+ .dw $ff06
+ .db "UCSR0C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0C
+XT_UCSR0C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0C:
+ .dw 194
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Bytes
+VE_UBRR0:
+ .dw $ff05
+ .db "UBRR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR0
+XT_UBRR0:
+ .dw PFA_DOVARIABLE
+PFA_UBRR0:
+ .dw 196
+
+.endif
+.if WANT_PORTH == 1
+; ( -- addr ) System Constant
+; R( -- )
+; PORT H Data Register
+VE_PORTH:
+ .dw $ff05
+ .db "PORTH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTH
+XT_PORTH:
+ .dw PFA_DOVARIABLE
+PFA_PORTH:
+ .dw 218
+; ( -- addr ) System Constant
+; R( -- )
+; PORT H Data Direction Register
+VE_DDRH:
+ .dw $ff04
+ .db "DDRH"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRH
+XT_DDRH:
+ .dw PFA_DOVARIABLE
+PFA_DDRH:
+ .dw 217
+; ( -- addr ) System Constant
+; R( -- )
+; PORT H Input Pins
+VE_PINH:
+ .dw $ff04
+ .db "PINH"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINH
+XT_PINH:
+ .dw PFA_DOVARIABLE
+PFA_PINH:
+ .dw 216
+
+.endif
+.if WANT_PORTJ == 1
+; ( -- addr ) System Constant
+; R( -- )
+; PORT J Data Register
+VE_PORTJ:
+ .dw $ff05
+ .db "PORTJ",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTJ
+XT_PORTJ:
+ .dw PFA_DOVARIABLE
+PFA_PORTJ:
+ .dw 221
+; ( -- addr ) System Constant
+; R( -- )
+; PORT J Data Direction Register
+VE_DDRJ:
+ .dw $ff04
+ .db "DDRJ"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRJ
+XT_DDRJ:
+ .dw PFA_DOVARIABLE
+PFA_DDRJ:
+ .dw 220
+; ( -- addr ) System Constant
+; R( -- )
+; PORT J Input Pins
+VE_PINJ:
+ .dw $ff04
+ .db "PINJ"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINJ
+XT_PINJ:
+ .dw PFA_DOVARIABLE
+PFA_PINJ:
+ .dw 219
+
+.endif
diff --git a/amforth-6.5/avr8/devices/atmega3290/device.py b/amforth-6.5/avr8/devices/atmega3290/device.py
new file mode 100644
index 0000000..f65657b
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega3290/device.py
@@ -0,0 +1,370 @@
+# Generated Automatically
+
+# Partname ATmega3290
+
+MCUREGS = {
+# Interrupt Vectors
+ 'INT0Addr' : '#2', # External Interrupt Request 0
+ 'PCINT0Addr' : '#4', # Pin Change Interrupt Request 0
+ 'PCINT1Addr' : '#6', # Pin Change Interrupt Request 1
+ 'TIMER2_COMPAddr' : '#8', # Timer/Counter2 Compare Match
+ 'TIMER2_OVFAddr' : '#10', # Timer/Counter2 Overflow
+ 'TIMER1_CAPTAddr' : '#12', # Timer/Counter1 Capture Event
+ 'TIMER1_COMPAAddr' : '#14', # Timer/Counter1 Compare Match A
+ 'TIMER1_COMPBAddr' : '#16', # Timer/Counter Compare Match B
+ 'TIMER1_OVFAddr' : '#18', # Timer/Counter1 Overflow
+ 'TIMER0_COMPAddr' : '#20', # Timer/Counter0 Compare Match
+ 'TIMER0_OVFAddr' : '#22', # Timer/Counter0 Overflow
+ 'SPI_STCAddr' : '#24', # SPI Serial Transfer Complete
+ 'USART_RXAddr' : '#26', # USART, Rx Complete
+ 'USART_UDREAddr' : '#28', # USART Data register Empty
+ 'USART0_TXAddr' : '#30', # USART0, Tx Complete
+ 'USI_STARTAddr' : '#32', # USI Start Condition
+ 'USI_OVERFLOWAddr' : '#34', # USI Overflow
+ 'ANALOG_COMPAddr' : '#36', # Analog Comparator
+ 'ADCAddr' : '#38', # ADC Conversion Complete
+ 'EE_READYAddr' : '#40', # EEPROM Ready
+ 'SPM_READYAddr' : '#42', # Store Program Memory Read
+ 'LCDAddr' : '#44', # LCD Start of Frame
+ 'PCINT2Addr' : '#46', # Pin Change Interrupt Request 2
+ 'PCINT3Addr' : '#48', # Pin Change Interrupt Request 3
+
+# Module TIMER_COUNTER_0
+ 'TCCR0A' : '$44', # Timer/Counter0 Control Registe
+ 'TCCR0A_FOC0A': '$80', # Force Output Compare
+ 'TCCR0A_WGM00': '$40', # Waveform Generation Mode 0
+ 'TCCR0A_COM0A': '$30', # Compare Match Output Modes
+ 'TCCR0A_WGM01': '$8', # Waveform Generation Mode 1
+ 'TCCR0A_CS0': '$7', # Clock Selects
+ 'TCNT0' : '$46', # Timer/Counter0
+ 'OCR0A' : '$47', # Timer/Counter0 Output Compare
+ 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
+ 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
+ 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
+ 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
+ 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
+ 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Control Register
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSR310': '$1', # Prescaler Reset Timer/Counter1
+
+# Module TIMER_COUNTER_1
+ 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
+ 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
+ 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
+ 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
+ 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
+ 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
+ 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
+ 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
+ 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
+ 'TCCR1C' : '$82', # Timer/Counter 1 Control Regist
+ 'TCCR1C_FOC1A': '$80', # Force Output Compare 1A
+ 'TCCR1C_FOC1B': '$40', # Force Output Compare 1B
+ 'TCNT1' : '$84', # Timer/Counter1 Bytes
+ 'OCR1A' : '$88', # Timer/Counter1 Output Compare
+ 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
+ 'ICR1' : '$86', # Timer/Counter1 Input Capture R
+ 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
+ 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
+ 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
+ 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
+ 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
+ 'TIFR1' : '$36', # Timer/Counter1 Interrupt Flag
+ 'TIFR1_ICF1': '$20', # Input Capture Flag 1
+ 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
+ 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
+ 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
+
+# Module TIMER_COUNTER_2
+ 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
+ 'TCCR2A_FOC2A': '$80', # Force Output Compare A
+ 'TCCR2A_WGM20': '$40', # Waveform Generation Mode
+ 'TCCR2A_COM2A': '$30', # Compare Output Mode bits
+ 'TCCR2A_WGM21': '$8', # Waveform Generation Mode
+ 'TCCR2A_CS2': '$7', # Clock Select bits
+ 'TCNT2' : '$b2', # Timer/Counter2
+ 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
+ 'TIMSK2' : '$70', # Timer/Counter2 Interrupt Mask
+ 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
+ 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
+ 'TIFR2' : '$37', # Timer/Counter2 Interrupt Flag
+ 'TIFR2_OCF2A': '$2', # Timer/Counter2 Output Compare
+ 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_PSR2': '$2', # Prescaler Reset Timer/Counter2
+ 'ASSR' : '$b6', # Asynchronous Status Register
+ 'ASSR_EXCLK': '$10', # Enable External Clock Interrup
+ 'ASSR_AS2': '$8', # AS2: Asynchronous Timer/Counte
+ 'ASSR_TCN2UB': '$4', # TCN2UB: Timer/Counter2 Update
+ 'ASSR_OCR2UB': '$2', # Output Compare Register2 Updat
+ 'ASSR_TCR2UB': '$1', # TCR2UB: Timer/Counter Control
+
+# Module WATCHDOG
+ 'WDTCR' : '$60', # Watchdog Timer Control Registe
+ 'WDTCR_WDCE': '$10', # Watchdog Change Enable
+ 'WDTCR_WDE': '$8', # Watch Dog Enable
+ 'WDTCR_WDP': '$7', # Watch Dog Timer Prescaler bits
+
+# Module EEPROM
+ 'EEAR' : '$41', # EEPROM Read/Write Access Byte
+ 'EEDR' : '$40', # EEPROM Data Register
+ 'EECR' : '$3f', # EEPROM Control Register
+ 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
+ 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
+ 'EECR_EEWE': '$2', # EEPROM Write Enable
+ 'EECR_EERE': '$1', # EEPROM Read Enable
+
+# Module SPI
+ 'SPCR' : '$4c', # SPI Control Register
+ 'SPCR_SPIE': '$80', # SPI Interrupt Enable
+ 'SPCR_SPE': '$40', # SPI Enable
+ 'SPCR_DORD': '$20', # Data Order
+ 'SPCR_MSTR': '$10', # Master/Slave Select
+ 'SPCR_CPOL': '$8', # Clock polarity
+ 'SPCR_CPHA': '$4', # Clock Phase
+ 'SPCR_SPR': '$3', # SPI Clock Rate Selects
+ 'SPSR' : '$4d', # SPI Status Register
+ 'SPSR_SPIF': '$80', # SPI Interrupt Flag
+ 'SPSR_WCOL': '$40', # Write Collision Flag
+ 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
+ 'SPDR' : '$4e', # SPI Data Register
+
+# Module PORTA
+ 'PORTA' : '$22', # Port A Data Register
+ 'DDRA' : '$21', # Port A Data Direction Register
+ 'PINA' : '$20', # Port A Input Pins
+
+# Module PORTB
+ 'PORTB' : '$25', # Port B Data Register
+ 'DDRB' : '$24', # Port B Data Direction Register
+ 'PINB' : '$23', # Port B Input Pins
+
+# Module PORTC
+ 'PORTC' : '$28', # Port C Data Register
+ 'DDRC' : '$27', # Port C Data Direction Register
+ 'PINC' : '$26', # Port C Input Pins
+
+# Module PORTD
+ 'PORTD' : '$2b', # Port D Data Register
+ 'DDRD' : '$2a', # Port D Data Direction Register
+ 'PIND' : '$29', # Port D Input Pins
+
+# Module ANALOG_COMPARATOR
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
+ 'ACSR' : '$50', # Analog Comparator Control And
+ 'ACSR_ACD': '$80', # Analog Comparator Disable
+ 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
+ 'ACSR_ACO': '$20', # Analog Compare Output
+ 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
+ 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
+ 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
+ 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
+ 'DIDR1' : '$7f', # Digital Input Disable Register
+ 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
+ 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
+
+# Module PORTE
+ 'PORTE' : '$2e', # Data Register, Port E
+ 'DDRE' : '$2d', # Data Direction Register, Port
+ 'PINE' : '$2c', # Input Pins, Port E
+
+# Module PORTF
+ 'PORTF' : '$31', # Data Register, Port F
+ 'DDRF' : '$30', # Data Direction Register, Port
+ 'PINF' : '$2f', # Input Pins, Port F
+
+# Module PORTG
+ 'PORTG' : '$34', # Port G Data Register
+ 'DDRG' : '$33', # Port G Data Direction Register
+ 'PING' : '$32', # Port G Input Pins
+
+# Module JTAG
+ 'OCDR' : '$51', # On-Chip Debug Related Register
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_JTD': '$80', # JTAG Interface Disable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+
+# Module LCD
+ 'LCDDR19' : '$ff', # LCD Data Register 19
+ 'LCDDR18' : '$fe', # LCD Data Register 18
+ 'LCDDR17' : '$fd', # LCD Data Register 17
+ 'LCDDR16' : '$fc', # LCD Data Register 16
+ 'LCDDR15' : '$fb', # LCD Data Register 15
+ 'LCDDR14' : '$fa', # LCD Data Register 14
+ 'LCDDR13' : '$f9', # LCD Data Register 13
+ 'LCDDR12' : '$f8', # LCD Data Register 12
+ 'LCDDR11' : '$f7', # LCD Data Register 11
+ 'LCDDR10' : '$f6', # LCD Data Register 10
+ 'LCDDR9' : '$f5', # LCD Data Register 9
+ 'LCDDR8' : '$f4', # LCD Data Register 8
+ 'LCDDR7' : '$f3', # LCD Data Register 7
+ 'LCDDR6' : '$f2', # LCD Data Register 6
+ 'LCDDR5' : '$f1', # LCD Data Register 5
+ 'LCDDR4' : '$f0', # LCD Data Register 4
+ 'LCDDR3' : '$ef', # LCD Data Register 3
+ 'LCDDR2' : '$ee', # LCD Data Register 2
+ 'LCDDR1' : '$ed', # LCD Data Register 1
+ 'LCDDR0' : '$ec', # LCD Data Register 0
+ 'LCDCCR' : '$e7', # LCD Contrast Control Register
+ 'LCDFRR' : '$e6', # LCD Frame Rate Register
+ 'LCDFRR_LCDPS': '$70', # LCD Prescaler Selects
+ 'LCDFRR_LCDCD': '$7', # LCD Clock Dividers
+ 'LCDCRB' : '$e5', # LCD Control and Status Registe
+ 'LCDCRB_LCDCS': '$80', # LCD CLock Select
+ 'LCDCRB_LCD2B': '$40', # LCD 1/2 Bias Select
+ 'LCDCRB_LCDMUX': '$30', # LCD Mux Selects
+ 'LCDCRB_LCDPM': '$f', # LCD Port Masks
+ 'LCDCRA' : '$e4', # LCD Control and Status Registe
+ 'LCDCRA_LCDEN': '$80', # LCD Enable
+ 'LCDCRA_LCDAB': '$40', # LCD A or B waveform
+ 'LCDCRA_LCDIF': '$10', # LCD Interrupt Flag
+ 'LCDCRA_LCDIE': '$8', # LCD Interrupt Enable
+ 'LCDCRA_LCDBL': '$1', # LCD Blanking
+
+# Module EXTERNAL_INTERRUPT
+ 'EICRA' : '$69', # External Interrupt Control Reg
+ 'EICRA_ISC01': '$2', # External Interrupt Sense Contr
+ 'EICRA_ISC00': '$1', # External Interrupt Sense Contr
+ 'EIMSK' : '$3d', # External Interrupt Mask Regist
+ 'EIMSK_PCIE': '$f0', # Pin Change Interrupt Enables
+ 'EIMSK_INT0': '$1', # External Interrupt Request 0 E
+ 'EIFR' : '$3c', # External Interrupt Flag Regist
+ 'EIFR_PCIF': '$f0', # Pin Change Interrupt Flags
+ 'EIFR_INTF0': '$1', # External Interrupt Flag 0
+ 'PCMSK3' : '$73', # Pin Change Mask Register 3
+ 'PCMSK2' : '$6d', # Pin Change Mask Register 2
+ 'PCMSK1' : '$6c', # Pin Change Mask Register 1
+ 'PCMSK0' : '$6b', # Pin Change Mask Register 0
+
+# Module CPU
+ 'SREG' : '$5f', # Status Register
+ 'SREG_I': '$80', # Global Interrupt Enable
+ 'SREG_T': '$40', # Bit Copy Storage
+ 'SREG_H': '$20', # Half Carry Flag
+ 'SREG_S': '$10', # Sign Bit
+ 'SREG_V': '$8', # Two's Complement Overflow Flag
+ 'SREG_N': '$4', # Negative Flag
+ 'SREG_Z': '$2', # Zero Flag
+ 'SREG_C': '$1', # Carry Flag
+ 'SP' : '$5d', # Stack Pointer
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_PUD': '$10', # Pull-up disable
+ 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
+ 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+ 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
+ 'MCUSR_BORF': '$4', # Brown-out Reset Flag
+ 'MCUSR_EXTRF': '$2', # External Reset Flag
+ 'MCUSR_PORF': '$1', # Power-on reset flag
+ 'OSCCAL' : '$66', # Oscillator Calibration Value
+ 'CLKPR' : '$61', # Clock Prescale Register
+ 'CLKPR_CLKPCE': '$80', # Clock Prescaler Change Enable
+ 'CLKPR_CLKPS': '$f', # Clock Prescaler Select Bits
+ 'PRR' : '$64', # Power Reduction Register
+ 'PRR_PRLCD': '$10', # Power Reduction LCD
+ 'PRR_PRTIM1': '$8', # Power Reduction Timer/Counter1
+ 'PRR_PRSPI': '$4', # Power Reduction Serial Periphe
+ 'PRR_PRUSART0': '$2', # Power Reduction USART
+ 'PRR_PRADC': '$1', # Power Reduction ADC
+ 'SMCR' : '$53', # Sleep Mode Control Register
+ 'SMCR_SM': '$e', # Sleep Mode Select bits
+ 'SMCR_SE': '$1', # Sleep Enable
+ 'GPIOR2' : '$4b', # General Purpose IO Register 2
+ 'GPIOR1' : '$4a', # General Purpose IO Register 1
+ 'GPIOR0' : '$3e', # General Purpose IO Register 0
+
+# Module USI
+ 'USIDR' : '$ba', # USI Data Register
+ 'USISR' : '$b9', # USI Status Register
+ 'USISR_USISIF': '$80', # Start Condition Interrupt Flag
+ 'USISR_USIOIF': '$40', # Counter Overflow Interrupt Fla
+ 'USISR_USIPF': '$20', # Stop Condition Flag
+ 'USISR_USIDC': '$10', # Data Output Collision
+ 'USISR_USICNT': '$f', # USI Counter Value Bits
+ 'USICR' : '$b8', # USI Control Register
+ 'USICR_USISIE': '$80', # Start Condition Interrupt Enab
+ 'USICR_USIOIE': '$40', # Counter Overflow Interrupt Ena
+ 'USICR_USIWM': '$30', # USI Wire Mode Bits
+ 'USICR_USICS': '$c', # USI Clock Source Select Bits
+ 'USICR_USICLK': '$2', # Clock Strobe
+ 'USICR_USITC': '$1', # Toggle Clock Port Pin
+
+# Module AD_CONVERTER
+ 'ADMUX' : '$7c', # The ADC multiplexer Selection
+ 'ADMUX_REFS': '$c0', # Reference Selection Bits
+ 'ADMUX_ADLAR': '$20', # Left Adjust Result
+ 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
+ 'ADCSRA' : '$7a', # The ADC Control and Status reg
+ 'ADCSRA_ADEN': '$80', # ADC Enable
+ 'ADCSRA_ADSC': '$40', # ADC Start Conversion
+ 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
+ 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
+ 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
+ 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
+ 'ADC' : '$78', # ADC Data Register Bytes
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Sources
+ 'DIDR0' : '$7e', # Digital Input Disable Register
+ 'DIDR0_ADC7D': '$80', # ADC7 Digital input Disable
+ 'DIDR0_ADC6D': '$40', # ADC6 Digital input Disable
+ 'DIDR0_ADC5D': '$20', # ADC5 Digital input Disable
+ 'DIDR0_ADC4D': '$10', # ADC4 Digital input Disable
+ 'DIDR0_ADC3D': '$8', # ADC3 Digital input Disable
+ 'DIDR0_ADC2D': '$4', # ADC2 Digital input Disable
+ 'DIDR0_ADC1D': '$2', # ADC1 Digital input Disable
+ 'DIDR0_ADC0D': '$1', # ADC0 Digital input Disable
+
+# Module BOOT_LOAD
+ 'SPMCSR' : '$57', # Store Program Memory Control R
+ 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
+ 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
+ 'SPMCSR_RWWSRE': '$10', # Read While Write section read
+ 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
+ 'SPMCSR_PGWRT': '$4', # Page Write
+ 'SPMCSR_PGERS': '$2', # Page Erase
+ 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
+
+# Module USART0
+ 'UDR0' : '$c6', # USART I/O Data Register
+ 'UCSR0A' : '$c0', # USART Control and Status Regis
+ 'UCSR0A_RXC0': '$80', # USART Receive Complete
+ 'UCSR0A_TXC0': '$40', # USART Transmit Complete
+ 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
+ 'UCSR0A_FE0': '$10', # Framing Error
+ 'UCSR0A_DOR0': '$8', # Data OverRun
+ 'UCSR0A_UPE0': '$4', # USART Parity Error
+ 'UCSR0A_U2X0': '$2', # Double the USART Transmission
+ 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
+ 'UCSR0B' : '$c1', # USART Control and Status Regis
+ 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
+ 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
+ 'UCSR0B_UDRIE0': '$20', # USART Data Register Empty Inte
+ 'UCSR0B_RXEN0': '$10', # Receiver Enable
+ 'UCSR0B_TXEN0': '$8', # Transmitter Enable
+ 'UCSR0B_UCSZ02': '$4', # Character Size
+ 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
+ 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
+ 'UCSR0C' : '$c2', # USART Control and Status Regis
+ 'UCSR0C_UMSEL0': '$40', # USART Mode Select
+ 'UCSR0C_UPM0': '$30', # Parity Mode Bits
+ 'UCSR0C_USBS0': '$8', # Stop Bit Select
+ 'UCSR0C_UCSZ0': '$6', # Character Size
+ 'UCSR0C_UCPOL0': '$1', # Clock Polarity
+ 'UBRR0' : '$c4', # USART Baud Rate Register Byte
+
+# Module PORTH
+ 'PORTH' : '$da', # PORT H Data Register
+ 'DDRH' : '$d9', # PORT H Data Direction Register
+ 'PINH' : '$d8', # PORT H Input Pins
+
+# Module PORTJ
+ 'PORTJ' : '$dd', # PORT J Data Register
+ 'DDRJ' : '$dc', # PORT J Data Direction Register
+ 'PINJ' : '$db', # PORT J Input Pins
+
+ '__amforth_dummy':'0'
+}
diff --git a/amforth-6.5/avr8/devices/atmega3290/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega3290/words/no-jtag.asm
new file mode 100644
index 0000000..352a4bb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega3290/words/no-jtag.asm
@@ -0,0 +1,14 @@
+; ( -- )
+; ( -- )
+; MCU
+; disable jtag at runtime
+VE_NOJTAG:
+ .dw $FF05
+ .db "-jtag",0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOJTAG
+XT_NOJTAG:
+ .dw PFA_NOJTAG
+PFA_NOJTAG:
+
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega3290/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega3290/words/no-wdt.asm
new file mode 100644
index 0000000..4a12261
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega3290/words/no-wdt.asm
@@ -0,0 +1,22 @@
+; ( -- )
+; MCU
+; disable watch dog timer at runtime
+VE_NOWDT:
+ .dw $ff04
+ .db "-wdt"
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOWDT
+XT_NOWDT:
+ .dw PFA_NOWDT
+PFA_NOWDT:
+
+; Reset WDT
+ wdr
+; Write logical one to WDTOE and WDE
+ in_ temp1, WDTCR
+ ori temp1, (1<<WDTOE)|(1<<WDE)
+ out WDTCR, temp1
+; Turn off WDT
+ ldi temp1, (0<<WDE)
+ out_ WDTCR, temp1
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega3290/words/sleep.asm b/amforth-6.5/avr8/devices/atmega3290/words/sleep.asm
new file mode 100644
index 0000000..256249c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega3290/words/sleep.asm
@@ -0,0 +1,19 @@
+; ( mode -- )
+; MCU
+; put the controller into the specified sleep mode
+VE_SLEEP:
+ .dw $ff05
+ .db "sleep", 0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_SLEEP
+XT_SLEEP:
+ .dw PFA_SLEEP
+PFA_SLEEP:
+ andi tosl, 7 ; leave only legal mode bits
+ lsl tosl ; move to correct location (bits 3-1)
+ ori tosl, 1 ; set the SE bit
+ out_ SMCR, tosl ; set the sleep config
+ sleep ; nighty-night
+ out_ SMCR, zerol ; 0 protects against accidental sleeps
+ loadtos ; pop argument from stack
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega3290a/atmega3290a.frt b/amforth-6.5/avr8/devices/atmega3290a/atmega3290a.frt
new file mode 100644
index 0000000..e88b4a9
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega3290a/atmega3290a.frt
@@ -0,0 +1,333 @@
+\ Partname: ATmega3290A
+\ generated automatically
+
+\ TIMER_COUNTER_0
+&68 constant TCCR0A \ Timer/Counter0 Control Register
+ $80 constant TCCR0A_FOC0A \ Force Output Compare
+ $40 constant TCCR0A_WGM00 \ Waveform Generation Mode 0
+ $30 constant TCCR0A_COM0A \ Compare Match Output Modes
+ $08 constant TCCR0A_WGM01 \ Waveform Generation Mode 1
+ $07 constant TCCR0A_CS0 \ Clock Selects
+&70 constant TCNT0 \ Timer/Counter0
+&71 constant OCR0A \ Timer/Counter0 Output Compare Register
+&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
+ $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match Interrupt Enable
+ $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
+&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
+ $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0
+ $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
+&67 constant GTCCR \ General Timer/Control Register
+ $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
+ $01 constant GTCCR_PSR310 \ Prescaler Reset Timer/Counter1 and Timer/Counter0
+\ TIMER_COUNTER_1
+&128 constant TCCR1A \ Timer/Counter1 Control Register A
+ $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
+ $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
+ $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
+&129 constant TCCR1B \ Timer/Counter1 Control Register B
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
+ $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
+&130 constant TCCR1C \ Timer/Counter 1 Control Register C
+ $80 constant TCCR1C_FOC1A \ Force Output Compare 1A
+ $40 constant TCCR1C_FOC1B \ Force Output Compare 1B
+&132 constant TCNT1 \ Timer/Counter1 Bytes
+&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
+&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
+&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
+&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
+ $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
+ $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
+ $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
+ $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
+&54 constant TIFR1 \ Timer/Counter1 Interrupt Flag register
+ $20 constant TIFR1_ICF1 \ Input Capture Flag 1
+ $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
+ $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
+ $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
+\ TIMER_COUNTER_2
+&176 constant TCCR2A \ Timer/Counter2 Control Register
+ $80 constant TCCR2A_FOC2A \ Force Output Compare A
+ $40 constant TCCR2A_WGM20 \ Waveform Generation Mode
+ $30 constant TCCR2A_COM2A \ Compare Output Mode bits
+ $08 constant TCCR2A_WGM21 \ Waveform Generation Mode
+ $07 constant TCCR2A_CS2 \ Clock Select bits
+&178 constant TCNT2 \ Timer/Counter2
+&179 constant OCR2A \ Timer/Counter2 Output Compare Register
+&112 constant TIMSK2 \ Timer/Counter2 Interrupt Mask register
+ $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match Interrupt Enable
+ $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
+&55 constant TIFR2 \ Timer/Counter2 Interrupt Flag Register
+ $02 constant TIFR2_OCF2A \ Timer/Counter2 Output Compare Flag 2
+ $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
+&182 constant ASSR \ Asynchronous Status Register
+ $10 constant ASSR_EXCLK \ Enable External Clock Interrupt
+ $08 constant ASSR_AS2 \ AS2: Asynchronous Timer/Counter2
+ $04 constant ASSR_TCN2UB \ TCN2UB: Timer/Counter2 Update Busy
+ $02 constant ASSR_OCR2UB \ Output Compare Register2 Update Busy
+ $01 constant ASSR_TCR2UB \ TCR2UB: Timer/Counter Control Register2 Update Busy
+\ WATCHDOG
+&96 constant WDTCR \ Watchdog Timer Control Register
+ $10 constant WDTCR_WDCE \ Watchdog Change Enable
+ $08 constant WDTCR_WDE \ Watch Dog Enable
+ $07 constant WDTCR_WDP \ Watch Dog Timer Prescaler bits
+\ EEPROM
+&65 constant EEAR \ EEPROM Read/Write Access Bytes
+&64 constant EEDR \ EEPROM Data Register
+&63 constant EECR \ EEPROM Control Register
+ $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
+ $04 constant EECR_EEMWE \ EEPROM Master Write Enable
+ $02 constant EECR_EEWE \ EEPROM Write Enable
+ $01 constant EECR_EERE \ EEPROM Read Enable
+\ SPI
+&76 constant SPCR \ SPI Control Register
+ $80 constant SPCR_SPIE \ SPI Interrupt Enable
+ $40 constant SPCR_SPE \ SPI Enable
+ $20 constant SPCR_DORD \ Data Order
+ $10 constant SPCR_MSTR \ Master/Slave Select
+ $08 constant SPCR_CPOL \ Clock polarity
+ $04 constant SPCR_CPHA \ Clock Phase
+ $03 constant SPCR_SPR \ SPI Clock Rate Selects
+&77 constant SPSR \ SPI Status Register
+ $80 constant SPSR_SPIF \ SPI Interrupt Flag
+ $40 constant SPSR_WCOL \ Write Collision Flag
+ $01 constant SPSR_SPI2X \ Double SPI Speed Bit
+&78 constant SPDR \ SPI Data Register
+\ PORTA
+&34 constant PORTA \ Port A Data Register
+&33 constant DDRA \ Port A Data Direction Register
+&32 constant PINA \ Port A Input Pins
+\ PORTB
+&37 constant PORTB \ Port B Data Register
+&36 constant DDRB \ Port B Data Direction Register
+&35 constant PINB \ Port B Input Pins
+\ PORTC
+&40 constant PORTC \ Port C Data Register
+&39 constant DDRC \ Port C Data Direction Register
+&38 constant PINC \ Port C Input Pins
+\ PORTD
+&43 constant PORTD \ Port D Data Register
+&42 constant DDRD \ Port D Data Direction Register
+&41 constant PIND \ Port D Input Pins
+\ ANALOG_COMPARATOR
+&123 constant ADCSRB \ ADC Control and Status Register B
+ $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer Enable
+&80 constant ACSR \ Analog Comparator Control And Status Register
+ $80 constant ACSR_ACD \ Analog Comparator Disable
+ $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
+ $20 constant ACSR_ACO \ Analog Compare Output
+ $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
+ $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
+ $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
+ $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
+&127 constant DIDR1 \ Digital Input Disable Register 1
+ $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
+ $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
+\ PORTE
+&46 constant PORTE \ Data Register, Port E
+&45 constant DDRE \ Data Direction Register, Port E
+&44 constant PINE \ Input Pins, Port E
+\ PORTF
+&49 constant PORTF \ Data Register, Port F
+&48 constant DDRF \ Data Direction Register, Port F
+&47 constant PINF \ Input Pins, Port F
+\ PORTG
+&52 constant PORTG \ Port G Data Register
+&51 constant DDRG \ Port G Data Direction Register
+&50 constant PING \ Port G Input Pins
+\ JTAG
+&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
+&85 constant MCUCR \ MCU Control Register
+ $80 constant MCUCR_JTD \ JTAG Interface Disable
+&84 constant MCUSR \ MCU Status Register
+ $10 constant MCUSR_JTRF \ JTAG Reset Flag
+\ EXTERNAL_INTERRUPT
+&105 constant EICRA \ External Interrupt Control Register A
+ $02 constant EICRA_ISC01 \ External Interrupt Sense Control 0 Bit 1
+ $01 constant EICRA_ISC00 \ External Interrupt Sense Control 0 Bit 0
+&61 constant EIMSK \ External Interrupt Mask Register
+ $F0 constant EIMSK_PCIE \ Pin Change Interrupt Enables
+ $01 constant EIMSK_INT0 \ External Interrupt Request 0 Enable
+&60 constant EIFR \ External Interrupt Flag Register
+ $F0 constant EIFR_PCIF \ Pin Change Interrupt Flags
+ $01 constant EIFR_INTF0 \ External Interrupt Flag 0
+&115 constant PCMSK3 \ Pin Change Mask Register 3
+&109 constant PCMSK2 \ Pin Change Mask Register 2
+&108 constant PCMSK1 \ Pin Change Mask Register 1
+&107 constant PCMSK0 \ Pin Change Mask Register 0
+\ USI
+&186 constant USIDR \ USI Data Register
+&185 constant USISR \ USI Status Register
+ $80 constant USISR_USISIF \ Start Condition Interrupt Flag
+ $40 constant USISR_USIOIF \ Counter Overflow Interrupt Flag
+ $20 constant USISR_USIPF \ Stop Condition Flag
+ $10 constant USISR_USIDC \ Data Output Collision
+ $0F constant USISR_USICNT \ USI Counter Value Bits
+&184 constant USICR \ USI Control Register
+ $80 constant USICR_USISIE \ Start Condition Interrupt Enable
+ $40 constant USICR_USIOIE \ Counter Overflow Interrupt Enable
+ $30 constant USICR_USIWM \ USI Wire Mode Bits
+ $0C constant USICR_USICS \ USI Clock Source Select Bits
+ $02 constant USICR_USICLK \ Clock Strobe
+ $01 constant USICR_USITC \ Toggle Clock Port Pin
+\ AD_CONVERTER
+&124 constant ADMUX \ The ADC multiplexer Selection Register
+ $C0 constant ADMUX_REFS \ Reference Selection Bits
+ $20 constant ADMUX_ADLAR \ Left Adjust Result
+ $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
+&122 constant ADCSRA \ The ADC Control and Status register
+ $80 constant ADCSRA_ADEN \ ADC Enable
+ $40 constant ADCSRA_ADSC \ ADC Start Conversion
+ $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
+ $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
+ $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
+ $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
+&120 constant ADC \ ADC Data Register Bytes
+&126 constant DIDR0 \ Digital Input Disable Register 0
+ $80 constant DIDR0_ADC7D \ ADC7 Digital input Disable
+ $40 constant DIDR0_ADC6D \ ADC6 Digital input Disable
+ $20 constant DIDR0_ADC5D \ ADC5 Digital input Disable
+ $10 constant DIDR0_ADC4D \ ADC4 Digital input Disable
+ $08 constant DIDR0_ADC3D \ ADC3 Digital input Disable
+ $04 constant DIDR0_ADC2D \ ADC2 Digital input Disable
+ $02 constant DIDR0_ADC1D \ ADC1 Digital input Disable
+ $01 constant DIDR0_ADC0D \ ADC0 Digital input Disable
+\ BOOT_LOAD
+&87 constant SPMCSR \ Store Program Memory Control Register
+ $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
+ $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
+ $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
+ $04 constant SPMCSR_PGWRT \ Page Write
+ $02 constant SPMCSR_PGERS \ Page Erase
+ $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
+\ USART0
+&198 constant UDR0 \ USART I/O Data Register
+&192 constant UCSR0A \ USART Control and Status Register A
+ $80 constant UCSR0A_RXC0 \ USART Receive Complete
+ $40 constant UCSR0A_TXC0 \ USART Transmit Complete
+ $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
+ $10 constant UCSR0A_FE0 \ Framing Error
+ $08 constant UCSR0A_DOR0 \ Data OverRun
+ $04 constant UCSR0A_UPE0 \ USART Parity Error
+ $02 constant UCSR0A_U2X0 \ Double the USART Transmission Speed
+ $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
+&193 constant UCSR0B \ USART Control and Status Register B
+ $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
+ $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
+ $20 constant UCSR0B_UDRIE0 \ USART Data Register Empty Interrupt Enable
+ $10 constant UCSR0B_RXEN0 \ Receiver Enable
+ $08 constant UCSR0B_TXEN0 \ Transmitter Enable
+ $04 constant UCSR0B_UCSZ02 \ Character Size
+ $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
+ $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
+&194 constant UCSR0C \ USART Control and Status Register C
+ $40 constant UCSR0C_UMSEL0 \ USART Mode Select
+ $30 constant UCSR0C_UPM0 \ Parity Mode Bits
+ $08 constant UCSR0C_USBS0 \ Stop Bit Select
+ $06 constant UCSR0C_UCSZ0 \ Character Size
+ $01 constant UCSR0C_UCPOL0 \ Clock Polarity
+&196 constant UBRR0 \ USART Baud Rate Register Bytes
+\ PORTH
+&218 constant PORTH \ PORT H Data Register
+&217 constant DDRH \ PORT H Data Direction Register
+&216 constant PINH \ PORT H Input Pins
+\ PORTJ
+&221 constant PORTJ \ PORT J Data Register
+&220 constant DDRJ \ PORT J Data Direction Register
+&219 constant PINJ \ PORT J Input Pins
+\ LCD
+&255 constant LCDDR19 \ LCD Data Register 19
+&254 constant LCDDR18 \ LCD Data Register 18
+&253 constant LCDDR17 \ LCD Data Register 17
+&252 constant LCDDR16 \ LCD Data Register 16
+&251 constant LCDDR15 \ LCD Data Register 15
+&250 constant LCDDR14 \ LCD Data Register 14
+&249 constant LCDDR13 \ LCD Data Register 13
+&248 constant LCDDR12 \ LCD Data Register 12
+&247 constant LCDDR11 \ LCD Data Register 11
+&246 constant LCDDR10 \ LCD Data Register 10
+&245 constant LCDDR9 \ LCD Data Register 9
+&244 constant LCDDR8 \ LCD Data Register 8
+&243 constant LCDDR7 \ LCD Data Register 7
+&242 constant LCDDR6 \ LCD Data Register 6
+&241 constant LCDDR5 \ LCD Data Register 5
+&240 constant LCDDR4 \ LCD Data Register 4
+&239 constant LCDDR3 \ LCD Data Register 3
+&238 constant LCDDR2 \ LCD Data Register 2
+&237 constant LCDDR1 \ LCD Data Register 1
+&236 constant LCDDR0 \ LCD Data Register 0
+&231 constant LCDCCR \ LCD Contrast Control Register
+ $E0 constant LCDCCR_LCDDC \ LCD Display Configurations
+ $10 constant LCDCCR_LCDMDT \ LCD Maximum Drive Time
+ $0F constant LCDCCR_LCDCC \ LCD Contrast Controls
+&230 constant LCDFRR \ LCD Frame Rate Register
+ $70 constant LCDFRR_LCDPS \ LCD Prescaler Selects
+ $07 constant LCDFRR_LCDCD \ LCD Clock Dividers
+&229 constant LCDCRB \ LCD Control and Status Register B
+ $80 constant LCDCRB_LCDCS \ LCD CLock Select
+ $40 constant LCDCRB_LCD2B \ LCD 1/2 Bias Select
+ $30 constant LCDCRB_LCDMUX \ LCD Mux Selects
+ $0F constant LCDCRB_LCDPM \ LCD Port Masks
+&228 constant LCDCRA \ LCD Control and Status Register A
+ $80 constant LCDCRA_LCDEN \ LCD Enable
+ $40 constant LCDCRA_LCDAB \ LCD A or B waveform
+ $10 constant LCDCRA_LCDIF \ LCD Interrupt Flag
+ $08 constant LCDCRA_LCDIE \ LCD Interrupt Enable
+ $04 constant LCDCRA_LCDBD \ LCD Buffer Disable
+ $02 constant LCDCRA_LCDCCD \ LCD Contrast Control Disable
+ $01 constant LCDCRA_LCDBL \ LCD Blanking
+\ CPU
+&95 constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ $08 constant SREG_V \ Two's Complement Overflow Flag
+ $04 constant SREG_N \ Negative Flag
+ $02 constant SREG_Z \ Zero Flag
+ $01 constant SREG_C \ Carry Flag
+&93 constant SP \ Stack Pointer
+&102 constant OSCCAL \ Oscillator Calibration Value
+&97 constant CLKPR \ Clock Prescale Register
+ $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable
+ $0F constant CLKPR_CLKPS \ Clock Prescaler Select Bits
+&100 constant PRR \ Power Reduction Register
+ $10 constant PRR_PRLCD \ Power Reduction LCD
+ $08 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
+ $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
+ $02 constant PRR_PRUSART0 \ Power Reduction USART
+ $01 constant PRR_PRADC \ Power Reduction ADC
+&83 constant SMCR \ Sleep Mode Control Register
+ $0E constant SMCR_SM \ Sleep Mode Select bits
+ $01 constant SMCR_SE \ Sleep Enable
+&75 constant GPIOR2 \ General Purpose IO Register 2
+&74 constant GPIOR1 \ General Purpose IO Register 1
+&62 constant GPIOR0 \ General Purpose IO Register 0
+
+\ Interrupts
+&2 constant INT0Addr \ External Interrupt Request 0
+&4 constant PCINT0Addr \ Pin Change Interrupt Request 0
+&6 constant PCINT1Addr \ Pin Change Interrupt Request 1
+&8 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
+&10 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
+&12 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+&14 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
+&16 constant TIMER1_COMPBAddr \ Timer/Counter Compare Match B
+&18 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+&20 constant TIMER0_COMPAddr \ Timer/Counter0 Compare Match
+&22 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
+&24 constant SPI__STCAddr \ SPI Serial Transfer Complete
+&26 constant USART__RXAddr \ USART, Rx Complete
+&28 constant USART__UDREAddr \ USART Data register Empty
+&30 constant USART0__TXAddr \ USART0, Tx Complete
+&32 constant USI_STARTAddr \ USI Start Condition
+&34 constant USI_OVERFLOWAddr \ USI Overflow
+&36 constant ANALOG_COMPAddr \ Analog Comparator
+&38 constant ADCAddr \ ADC Conversion Complete
+&40 constant EE_READYAddr \ EEPROM Ready
+&42 constant SPM_READYAddr \ Store Program Memory Read
+&44 constant LCDAddr \ LCD Start of Frame
+&46 constant PCINT2Addr \ Pin Change Interrupt Request 2
+&48 constant PCINT3Addr \ Pin Change Interrupt Request 3
diff --git a/amforth-6.5/avr8/devices/atmega3290a/device.asm b/amforth-6.5/avr8/devices/atmega3290a/device.asm
new file mode 100644
index 0000000..6ffbf86
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega3290a/device.asm
@@ -0,0 +1,115 @@
+; Partname: ATmega3290A
+; generated automatically, do not edit
+
+.nolist
+ .include "m3290Adef.inc"
+.list
+
+.equ ramstart = 256
+.equ CELLSIZE = 2
+.macro readflashcell
+ lsl zl
+ rol zh
+ lpm @0, Z+
+ lpm @1, Z+
+.endmacro
+.macro writeflashcell
+ lsl zl
+ rol zh
+.endmacro
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_TIMER_COUNTER_2 = 0
+.set WANT_WATCHDOG = 0
+.set WANT_EEPROM = 0
+.set WANT_SPI = 0
+.set WANT_PORTA = 0
+.set WANT_PORTB = 0
+.set WANT_PORTC = 0
+.set WANT_PORTD = 0
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_PORTE = 0
+.set WANT_PORTF = 0
+.set WANT_PORTG = 0
+.set WANT_JTAG = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_USI = 0
+.set WANT_AD_CONVERTER = 0
+.set WANT_BOOT_LOAD = 0
+.set WANT_USART0 = 0
+.set WANT_PORTH = 0
+.set WANT_PORTJ = 0
+.set WANT_LCD = 0
+.set WANT_CPU = 0
+.equ intvecsize = 2 ; please verify; flash size: 32768 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.org 2
+ rcall isr ; External Interrupt Request 0
+.org 4
+ rcall isr ; Pin Change Interrupt Request 0
+.org 6
+ rcall isr ; Pin Change Interrupt Request 1
+.org 8
+ rcall isr ; Timer/Counter2 Compare Match
+.org 10
+ rcall isr ; Timer/Counter2 Overflow
+.org 12
+ rcall isr ; Timer/Counter1 Capture Event
+.org 14
+ rcall isr ; Timer/Counter1 Compare Match A
+.org 16
+ rcall isr ; Timer/Counter Compare Match B
+.org 18
+ rcall isr ; Timer/Counter1 Overflow
+.org 20
+ rcall isr ; Timer/Counter0 Compare Match
+.org 22
+ rcall isr ; Timer/Counter0 Overflow
+.org 24
+ rcall isr ; SPI Serial Transfer Complete
+.org 26
+ rcall isr ; USART, Rx Complete
+.org 28
+ rcall isr ; USART Data register Empty
+.org 30
+ rcall isr ; USART0, Tx Complete
+.org 32
+ rcall isr ; USI Start Condition
+.org 34
+ rcall isr ; USI Overflow
+.org 36
+ rcall isr ; Analog Comparator
+.org 38
+ rcall isr ; ADC Conversion Complete
+.org 40
+ rcall isr ; EEPROM Ready
+.org 42
+ rcall isr ; Store Program Memory Read
+.org 44
+ rcall isr ; LCD Start of Frame
+.org 46
+ rcall isr ; Pin Change Interrupt Request 2
+.org 48
+ rcall isr ; Pin Change Interrupt Request 3
+.equ INTVECTORS = 25
+.nooverlap
+
+; compatability layer (maybe empty)
+.equ EEPE = EEWE
+.equ EEMPE = EEMWE
+
+; controller data area, environment query mcu-info
+mcu_info:
+mcu_ramsize:
+ .dw 2048
+mcu_eepromsize:
+ .dw 1024
+mcu_maxdp:
+ .dw 28672
+mcu_numints:
+ .dw 25
+mcu_name:
+ .dw 11
+ .db "ATmega3290A",0
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega3290a/device.inc b/amforth-6.5/avr8/devices/atmega3290a/device.inc
new file mode 100644
index 0000000..3b7f25f
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega3290a/device.inc
@@ -0,0 +1,1443 @@
+; Partname: ATmega3290A
+; generated automatically, no not edit
+
+.if WANT_TIMER_COUNTER_0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Control Register
+VE_TCCR0A:
+ .dw $ff06
+ .db "TCCR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0A
+XT_TCCR0A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0A:
+ .dw 68
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw 70
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0A:
+ .dw $ff05
+ .db "OCR0A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0A
+XT_OCR0A:
+ .dw PFA_DOVARIABLE
+PFA_OCR0A:
+ .dw 71
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Mask Register
+VE_TIMSK0:
+ .dw $ff06
+ .db "TIMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK0
+XT_TIMSK0:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK0:
+ .dw 110
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Flag register
+VE_TIFR0:
+ .dw $ff05
+ .db "TIFR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR0
+XT_TIFR0:
+ .dw PFA_DOVARIABLE
+PFA_TIFR0:
+ .dw 53
+; ( -- addr ) System Constant
+; R( -- )
+; General Timer/Control Register
+VE_GTCCR:
+ .dw $ff05
+ .db "GTCCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GTCCR
+XT_GTCCR:
+ .dw PFA_DOVARIABLE
+PFA_GTCCR:
+ .dw 67
+
+.endif
+.if WANT_TIMER_COUNTER_1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw 128
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw 129
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter 1 Control Register C
+VE_TCCR1C:
+ .dw $ff06
+ .db "TCCR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1C
+XT_TCCR1C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1C:
+ .dw 130
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Bytes
+VE_TCNT1:
+ .dw $ff05
+ .db "TCNT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1
+XT_TCNT1:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1:
+ .dw 132
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register A Bytes
+VE_OCR1A:
+ .dw $ff05
+ .db "OCR1A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1A
+XT_OCR1A:
+ .dw PFA_DOVARIABLE
+PFA_OCR1A:
+ .dw 136
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register B Bytes
+VE_OCR1B:
+ .dw $ff05
+ .db "OCR1B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1B
+XT_OCR1B:
+ .dw PFA_DOVARIABLE
+PFA_OCR1B:
+ .dw 138
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Bytes
+VE_ICR1:
+ .dw $ff04
+ .db "ICR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1
+XT_ICR1:
+ .dw PFA_DOVARIABLE
+PFA_ICR1:
+ .dw 134
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Mask Register
+VE_TIMSK1:
+ .dw $ff06
+ .db "TIMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK1
+XT_TIMSK1:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK1:
+ .dw 111
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Flag register
+VE_TIFR1:
+ .dw $ff05
+ .db "TIFR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR1
+XT_TIFR1:
+ .dw PFA_DOVARIABLE
+PFA_TIFR1:
+ .dw 54
+
+.endif
+.if WANT_TIMER_COUNTER_2 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register
+VE_TCCR2A:
+ .dw $ff06
+ .db "TCCR2A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2A
+XT_TCCR2A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2A:
+ .dw 176
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2
+VE_TCNT2:
+ .dw $ff05
+ .db "TCNT2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT2
+XT_TCNT2:
+ .dw PFA_DOVARIABLE
+PFA_TCNT2:
+ .dw 178
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register
+VE_OCR2A:
+ .dw $ff05
+ .db "OCR2A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2A
+XT_OCR2A:
+ .dw PFA_DOVARIABLE
+PFA_OCR2A:
+ .dw 179
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Interrupt Mask register
+VE_TIMSK2:
+ .dw $ff06
+ .db "TIMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK2
+XT_TIMSK2:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK2:
+ .dw 112
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Interrupt Flag Register
+VE_TIFR2:
+ .dw $ff05
+ .db "TIFR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR2
+XT_TIFR2:
+ .dw PFA_DOVARIABLE
+PFA_TIFR2:
+ .dw 55
+; ( -- addr ) System Constant
+; R( -- )
+; Asynchronous Status Register
+VE_ASSR:
+ .dw $ff04
+ .db "ASSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ASSR
+XT_ASSR:
+ .dw PFA_DOVARIABLE
+PFA_ASSR:
+ .dw 182
+
+.endif
+.if WANT_WATCHDOG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCR:
+ .dw $ff05
+ .db "WDTCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCR
+XT_WDTCR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCR:
+ .dw 96
+
+.endif
+.if WANT_EEPROM == 1
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Read/Write Access Bytes
+VE_EEAR:
+ .dw $ff04
+ .db "EEAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEAR
+XT_EEAR:
+ .dw PFA_DOVARIABLE
+PFA_EEAR:
+ .dw 65
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw 64
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw 63
+
+.endif
+.if WANT_SPI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR:
+ .dw $ff04
+ .db "SPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR
+XT_SPCR:
+ .dw PFA_DOVARIABLE
+PFA_SPCR:
+ .dw 76
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR:
+ .dw $ff04
+ .db "SPSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR
+XT_SPSR:
+ .dw PFA_DOVARIABLE
+PFA_SPSR:
+ .dw 77
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR:
+ .dw $ff04
+ .db "SPDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR
+XT_SPDR:
+ .dw PFA_DOVARIABLE
+PFA_SPDR:
+ .dw 78
+
+.endif
+.if WANT_PORTA == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Register
+VE_PORTA:
+ .dw $ff05
+ .db "PORTA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTA
+XT_PORTA:
+ .dw PFA_DOVARIABLE
+PFA_PORTA:
+ .dw 34
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Direction Register
+VE_DDRA:
+ .dw $ff04
+ .db "DDRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRA
+XT_DDRA:
+ .dw PFA_DOVARIABLE
+PFA_DDRA:
+ .dw 33
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Input Pins
+VE_PINA:
+ .dw $ff04
+ .db "PINA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINA
+XT_PINA:
+ .dw PFA_DOVARIABLE
+PFA_PINA:
+ .dw 32
+
+.endif
+.if WANT_PORTB == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw 37
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw 36
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw 35
+
+.endif
+.if WANT_PORTC == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Register
+VE_PORTC:
+ .dw $ff05
+ .db "PORTC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTC
+XT_PORTC:
+ .dw PFA_DOVARIABLE
+PFA_PORTC:
+ .dw 40
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Direction Register
+VE_DDRC:
+ .dw $ff04
+ .db "DDRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRC
+XT_DDRC:
+ .dw PFA_DOVARIABLE
+PFA_DDRC:
+ .dw 39
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Input Pins
+VE_PINC:
+ .dw $ff04
+ .db "PINC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINC
+XT_PINC:
+ .dw PFA_DOVARIABLE
+PFA_PINC:
+ .dw 38
+
+.endif
+.if WANT_PORTD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw 43
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw 42
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw 41
+
+.endif
+.if WANT_ANALOG_COMPARATOR == 1
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Control and Status Register B
+VE_ADCSRB:
+ .dw $ff06
+ .db "ADCSRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRB
+XT_ADCSRB:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRB:
+ .dw 123
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Control And Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw 80
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 1
+VE_DIDR1:
+ .dw $ff05
+ .db "DIDR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR1
+XT_DIDR1:
+ .dw PFA_DOVARIABLE
+PFA_DIDR1:
+ .dw 127
+
+.endif
+.if WANT_PORTE == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port E
+VE_PORTE:
+ .dw $ff05
+ .db "PORTE",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTE
+XT_PORTE:
+ .dw PFA_DOVARIABLE
+PFA_PORTE:
+ .dw 46
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port E
+VE_DDRE:
+ .dw $ff04
+ .db "DDRE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRE
+XT_DDRE:
+ .dw PFA_DOVARIABLE
+PFA_DDRE:
+ .dw 45
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port E
+VE_PINE:
+ .dw $ff04
+ .db "PINE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINE
+XT_PINE:
+ .dw PFA_DOVARIABLE
+PFA_PINE:
+ .dw 44
+
+.endif
+.if WANT_PORTF == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port F
+VE_PORTF:
+ .dw $ff05
+ .db "PORTF",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTF
+XT_PORTF:
+ .dw PFA_DOVARIABLE
+PFA_PORTF:
+ .dw 49
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port F
+VE_DDRF:
+ .dw $ff04
+ .db "DDRF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRF
+XT_DDRF:
+ .dw PFA_DOVARIABLE
+PFA_DDRF:
+ .dw 48
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port F
+VE_PINF:
+ .dw $ff04
+ .db "PINF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINF
+XT_PINF:
+ .dw PFA_DOVARIABLE
+PFA_PINF:
+ .dw 47
+
+.endif
+.if WANT_PORTG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Data Register
+VE_PORTG:
+ .dw $ff05
+ .db "PORTG",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTG
+XT_PORTG:
+ .dw PFA_DOVARIABLE
+PFA_PORTG:
+ .dw 52
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Data Direction Register
+VE_DDRG:
+ .dw $ff04
+ .db "DDRG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRG
+XT_DDRG:
+ .dw PFA_DOVARIABLE
+PFA_DDRG:
+ .dw 51
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Input Pins
+VE_PING:
+ .dw $ff04
+ .db "PING"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PING
+XT_PING:
+ .dw PFA_DOVARIABLE
+PFA_PING:
+ .dw 50
+
+.endif
+.if WANT_JTAG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; On-Chip Debug Related Register in I/O Memory
+VE_OCDR:
+ .dw $ff04
+ .db "OCDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCDR
+XT_OCDR:
+ .dw PFA_DOVARIABLE
+PFA_OCDR:
+ .dw 81
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw 85
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Status Register
+VE_MCUSR:
+ .dw $ff05
+ .db "MCUSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUSR
+XT_MCUSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUSR:
+ .dw 84
+
+.endif
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register A
+VE_EICRA:
+ .dw $ff05
+ .db "EICRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRA
+XT_EICRA:
+ .dw PFA_DOVARIABLE
+PFA_EICRA:
+ .dw 105
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Mask Register
+VE_EIMSK:
+ .dw $ff05
+ .db "EIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIMSK
+XT_EIMSK:
+ .dw PFA_DOVARIABLE
+PFA_EIMSK:
+ .dw 61
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Flag Register
+VE_EIFR:
+ .dw $ff04
+ .db "EIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIFR
+XT_EIFR:
+ .dw PFA_DOVARIABLE
+PFA_EIFR:
+ .dw 60
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 3
+VE_PCMSK3:
+ .dw $ff06
+ .db "PCMSK3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK3
+XT_PCMSK3:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK3:
+ .dw 115
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 2
+VE_PCMSK2:
+ .dw $ff06
+ .db "PCMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK2
+XT_PCMSK2:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK2:
+ .dw 109
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 1
+VE_PCMSK1:
+ .dw $ff06
+ .db "PCMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK1
+XT_PCMSK1:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK1:
+ .dw 108
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 0
+VE_PCMSK0:
+ .dw $ff06
+ .db "PCMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK0
+XT_PCMSK0:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK0:
+ .dw 107
+
+.endif
+.if WANT_USI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USI Data Register
+VE_USIDR:
+ .dw $ff05
+ .db "USIDR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USIDR
+XT_USIDR:
+ .dw PFA_DOVARIABLE
+PFA_USIDR:
+ .dw 186
+; ( -- addr ) System Constant
+; R( -- )
+; USI Status Register
+VE_USISR:
+ .dw $ff05
+ .db "USISR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USISR
+XT_USISR:
+ .dw PFA_DOVARIABLE
+PFA_USISR:
+ .dw 185
+; ( -- addr ) System Constant
+; R( -- )
+; USI Control Register
+VE_USICR:
+ .dw $ff05
+ .db "USICR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USICR
+XT_USICR:
+ .dw PFA_DOVARIABLE
+PFA_USICR:
+ .dw 184
+
+.endif
+.if WANT_AD_CONVERTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC multiplexer Selection Register
+VE_ADMUX:
+ .dw $ff05
+ .db "ADMUX",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADMUX
+XT_ADMUX:
+ .dw PFA_DOVARIABLE
+PFA_ADMUX:
+ .dw 124
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register
+VE_ADCSRA:
+ .dw $ff06
+ .db "ADCSRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRA
+XT_ADCSRA:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRA:
+ .dw 122
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register Bytes
+VE_ADC:
+ .dw $ff03
+ .db "ADC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADC
+XT_ADC:
+ .dw PFA_DOVARIABLE
+PFA_ADC:
+ .dw 120
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 0
+VE_DIDR0:
+ .dw $ff05
+ .db "DIDR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR0
+XT_DIDR0:
+ .dw PFA_DOVARIABLE
+PFA_DIDR0:
+ .dw 126
+
+.endif
+.if WANT_BOOT_LOAD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control Register
+VE_SPMCSR:
+ .dw $ff06
+ .db "SPMCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCSR
+XT_SPMCSR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCSR:
+ .dw 87
+
+.endif
+.if WANT_USART0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR0:
+ .dw $ff04
+ .db "UDR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR0
+XT_UDR0:
+ .dw PFA_DOVARIABLE
+PFA_UDR0:
+ .dw 198
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR0A:
+ .dw $ff06
+ .db "UCSR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0A
+XT_UCSR0A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0A:
+ .dw 192
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR0B:
+ .dw $ff06
+ .db "UCSR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0B
+XT_UCSR0B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0B:
+ .dw 193
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR0C:
+ .dw $ff06
+ .db "UCSR0C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0C
+XT_UCSR0C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0C:
+ .dw 194
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Bytes
+VE_UBRR0:
+ .dw $ff05
+ .db "UBRR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR0
+XT_UBRR0:
+ .dw PFA_DOVARIABLE
+PFA_UBRR0:
+ .dw 196
+
+.endif
+.if WANT_PORTH == 1
+; ( -- addr ) System Constant
+; R( -- )
+; PORT H Data Register
+VE_PORTH:
+ .dw $ff05
+ .db "PORTH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTH
+XT_PORTH:
+ .dw PFA_DOVARIABLE
+PFA_PORTH:
+ .dw 218
+; ( -- addr ) System Constant
+; R( -- )
+; PORT H Data Direction Register
+VE_DDRH:
+ .dw $ff04
+ .db "DDRH"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRH
+XT_DDRH:
+ .dw PFA_DOVARIABLE
+PFA_DDRH:
+ .dw 217
+; ( -- addr ) System Constant
+; R( -- )
+; PORT H Input Pins
+VE_PINH:
+ .dw $ff04
+ .db "PINH"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINH
+XT_PINH:
+ .dw PFA_DOVARIABLE
+PFA_PINH:
+ .dw 216
+
+.endif
+.if WANT_PORTJ == 1
+; ( -- addr ) System Constant
+; R( -- )
+; PORT J Data Register
+VE_PORTJ:
+ .dw $ff05
+ .db "PORTJ",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTJ
+XT_PORTJ:
+ .dw PFA_DOVARIABLE
+PFA_PORTJ:
+ .dw 221
+; ( -- addr ) System Constant
+; R( -- )
+; PORT J Data Direction Register
+VE_DDRJ:
+ .dw $ff04
+ .db "DDRJ"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRJ
+XT_DDRJ:
+ .dw PFA_DOVARIABLE
+PFA_DDRJ:
+ .dw 220
+; ( -- addr ) System Constant
+; R( -- )
+; PORT J Input Pins
+VE_PINJ:
+ .dw $ff04
+ .db "PINJ"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINJ
+XT_PINJ:
+ .dw PFA_DOVARIABLE
+PFA_PINJ:
+ .dw 219
+
+.endif
+.if WANT_LCD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 19
+VE_LCDDR19:
+ .dw $ff07
+ .db "LCDDR19",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR19
+XT_LCDDR19:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR19:
+ .dw 255
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 18
+VE_LCDDR18:
+ .dw $ff07
+ .db "LCDDR18",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR18
+XT_LCDDR18:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR18:
+ .dw 254
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 17
+VE_LCDDR17:
+ .dw $ff07
+ .db "LCDDR17",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR17
+XT_LCDDR17:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR17:
+ .dw 253
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 16
+VE_LCDDR16:
+ .dw $ff07
+ .db "LCDDR16",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR16
+XT_LCDDR16:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR16:
+ .dw 252
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 15
+VE_LCDDR15:
+ .dw $ff07
+ .db "LCDDR15",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR15
+XT_LCDDR15:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR15:
+ .dw 251
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 14
+VE_LCDDR14:
+ .dw $ff07
+ .db "LCDDR14",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR14
+XT_LCDDR14:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR14:
+ .dw 250
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 13
+VE_LCDDR13:
+ .dw $ff07
+ .db "LCDDR13",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR13
+XT_LCDDR13:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR13:
+ .dw 249
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 12
+VE_LCDDR12:
+ .dw $ff07
+ .db "LCDDR12",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR12
+XT_LCDDR12:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR12:
+ .dw 248
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 11
+VE_LCDDR11:
+ .dw $ff07
+ .db "LCDDR11",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR11
+XT_LCDDR11:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR11:
+ .dw 247
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 10
+VE_LCDDR10:
+ .dw $ff07
+ .db "LCDDR10",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR10
+XT_LCDDR10:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR10:
+ .dw 246
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 9
+VE_LCDDR9:
+ .dw $ff06
+ .db "LCDDR9"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR9
+XT_LCDDR9:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR9:
+ .dw 245
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 8
+VE_LCDDR8:
+ .dw $ff06
+ .db "LCDDR8"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR8
+XT_LCDDR8:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR8:
+ .dw 244
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 7
+VE_LCDDR7:
+ .dw $ff06
+ .db "LCDDR7"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR7
+XT_LCDDR7:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR7:
+ .dw 243
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 6
+VE_LCDDR6:
+ .dw $ff06
+ .db "LCDDR6"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR6
+XT_LCDDR6:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR6:
+ .dw 242
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 5
+VE_LCDDR5:
+ .dw $ff06
+ .db "LCDDR5"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR5
+XT_LCDDR5:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR5:
+ .dw 241
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 4
+VE_LCDDR4:
+ .dw $ff06
+ .db "LCDDR4"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR4
+XT_LCDDR4:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR4:
+ .dw 240
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 3
+VE_LCDDR3:
+ .dw $ff06
+ .db "LCDDR3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR3
+XT_LCDDR3:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR3:
+ .dw 239
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 2
+VE_LCDDR2:
+ .dw $ff06
+ .db "LCDDR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR2
+XT_LCDDR2:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR2:
+ .dw 238
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 1
+VE_LCDDR1:
+ .dw $ff06
+ .db "LCDDR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR1
+XT_LCDDR1:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR1:
+ .dw 237
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 0
+VE_LCDDR0:
+ .dw $ff06
+ .db "LCDDR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR0
+XT_LCDDR0:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR0:
+ .dw 236
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Contrast Control Register
+VE_LCDCCR:
+ .dw $ff06
+ .db "LCDCCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDCCR
+XT_LCDCCR:
+ .dw PFA_DOVARIABLE
+PFA_LCDCCR:
+ .dw 231
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Frame Rate Register
+VE_LCDFRR:
+ .dw $ff06
+ .db "LCDFRR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDFRR
+XT_LCDFRR:
+ .dw PFA_DOVARIABLE
+PFA_LCDFRR:
+ .dw 230
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Control and Status Register B
+VE_LCDCRB:
+ .dw $ff06
+ .db "LCDCRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDCRB
+XT_LCDCRB:
+ .dw PFA_DOVARIABLE
+PFA_LCDCRB:
+ .dw 229
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Control and Status Register A
+VE_LCDCRA:
+ .dw $ff06
+ .db "LCDCRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDCRA
+XT_LCDCRA:
+ .dw PFA_DOVARIABLE
+PFA_LCDCRA:
+ .dw 228
+
+.endif
+.if WANT_CPU == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw 95
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer
+VE_SP:
+ .dw $ff02
+ .db "SP"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SP
+XT_SP:
+ .dw PFA_DOVARIABLE
+PFA_SP:
+ .dw 93
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Calibration Value
+VE_OSCCAL:
+ .dw $ff06
+ .db "OSCCAL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSCCAL
+XT_OSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_OSCCAL:
+ .dw 102
+; ( -- addr ) System Constant
+; R( -- )
+; Clock Prescale Register
+VE_CLKPR:
+ .dw $ff05
+ .db "CLKPR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKPR
+XT_CLKPR:
+ .dw PFA_DOVARIABLE
+PFA_CLKPR:
+ .dw 97
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register
+VE_PRR:
+ .dw $ff03
+ .db "PRR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR
+XT_PRR:
+ .dw PFA_DOVARIABLE
+PFA_PRR:
+ .dw 100
+; ( -- addr ) System Constant
+; R( -- )
+; Sleep Mode Control Register
+VE_SMCR:
+ .dw $ff04
+ .db "SMCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SMCR
+XT_SMCR:
+ .dw PFA_DOVARIABLE
+PFA_SMCR:
+ .dw 83
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 2
+VE_GPIOR2:
+ .dw $ff06
+ .db "GPIOR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR2
+XT_GPIOR2:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR2:
+ .dw 75
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 1
+VE_GPIOR1:
+ .dw $ff06
+ .db "GPIOR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR1
+XT_GPIOR1:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR1:
+ .dw 74
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 0
+VE_GPIOR0:
+ .dw $ff06
+ .db "GPIOR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR0
+XT_GPIOR0:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR0:
+ .dw 62
+
+.endif
diff --git a/amforth-6.5/avr8/devices/atmega3290a/device.py b/amforth-6.5/avr8/devices/atmega3290a/device.py
new file mode 100644
index 0000000..e02b422
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega3290a/device.py
@@ -0,0 +1,378 @@
+# Generated Automatically
+
+# Partname ATmega3290A
+
+MCUREGS = {
+# Interrupt Vectors
+ 'INT0Addr' : '#2', # External Interrupt Request 0
+ 'PCINT0Addr' : '#4', # Pin Change Interrupt Request 0
+ 'PCINT1Addr' : '#6', # Pin Change Interrupt Request 1
+ 'TIMER2_COMPAddr' : '#8', # Timer/Counter2 Compare Match
+ 'TIMER2_OVFAddr' : '#10', # Timer/Counter2 Overflow
+ 'TIMER1_CAPTAddr' : '#12', # Timer/Counter1 Capture Event
+ 'TIMER1_COMPAAddr' : '#14', # Timer/Counter1 Compare Match A
+ 'TIMER1_COMPBAddr' : '#16', # Timer/Counter Compare Match B
+ 'TIMER1_OVFAddr' : '#18', # Timer/Counter1 Overflow
+ 'TIMER0_COMPAddr' : '#20', # Timer/Counter0 Compare Match
+ 'TIMER0_OVFAddr' : '#22', # Timer/Counter0 Overflow
+ 'SPI_STCAddr' : '#24', # SPI Serial Transfer Complete
+ 'USART_RXAddr' : '#26', # USART, Rx Complete
+ 'USART_UDREAddr' : '#28', # USART Data register Empty
+ 'USART0_TXAddr' : '#30', # USART0, Tx Complete
+ 'USI_STARTAddr' : '#32', # USI Start Condition
+ 'USI_OVERFLOWAddr' : '#34', # USI Overflow
+ 'ANALOG_COMPAddr' : '#36', # Analog Comparator
+ 'ADCAddr' : '#38', # ADC Conversion Complete
+ 'EE_READYAddr' : '#40', # EEPROM Ready
+ 'SPM_READYAddr' : '#42', # Store Program Memory Read
+ 'LCDAddr' : '#44', # LCD Start of Frame
+ 'PCINT2Addr' : '#46', # Pin Change Interrupt Request 2
+ 'PCINT3Addr' : '#48', # Pin Change Interrupt Request 3
+
+# Module TIMER_COUNTER_0
+ 'TCCR0A' : '$44', # Timer/Counter0 Control Registe
+ 'TCCR0A_FOC0A': '$80', # Force Output Compare
+ 'TCCR0A_WGM00': '$40', # Waveform Generation Mode 0
+ 'TCCR0A_COM0A': '$30', # Compare Match Output Modes
+ 'TCCR0A_WGM01': '$8', # Waveform Generation Mode 1
+ 'TCCR0A_CS0': '$7', # Clock Selects
+ 'TCNT0' : '$46', # Timer/Counter0
+ 'OCR0A' : '$47', # Timer/Counter0 Output Compare
+ 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
+ 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
+ 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
+ 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
+ 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
+ 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Control Register
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSR310': '$1', # Prescaler Reset Timer/Counter1
+
+# Module TIMER_COUNTER_1
+ 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
+ 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
+ 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
+ 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
+ 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
+ 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
+ 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
+ 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
+ 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
+ 'TCCR1C' : '$82', # Timer/Counter 1 Control Regist
+ 'TCCR1C_FOC1A': '$80', # Force Output Compare 1A
+ 'TCCR1C_FOC1B': '$40', # Force Output Compare 1B
+ 'TCNT1' : '$84', # Timer/Counter1 Bytes
+ 'OCR1A' : '$88', # Timer/Counter1 Output Compare
+ 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
+ 'ICR1' : '$86', # Timer/Counter1 Input Capture R
+ 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
+ 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
+ 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
+ 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
+ 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
+ 'TIFR1' : '$36', # Timer/Counter1 Interrupt Flag
+ 'TIFR1_ICF1': '$20', # Input Capture Flag 1
+ 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
+ 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
+ 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
+
+# Module TIMER_COUNTER_2
+ 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
+ 'TCCR2A_FOC2A': '$80', # Force Output Compare A
+ 'TCCR2A_WGM20': '$40', # Waveform Generation Mode
+ 'TCCR2A_COM2A': '$30', # Compare Output Mode bits
+ 'TCCR2A_WGM21': '$8', # Waveform Generation Mode
+ 'TCCR2A_CS2': '$7', # Clock Select bits
+ 'TCNT2' : '$b2', # Timer/Counter2
+ 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
+ 'TIMSK2' : '$70', # Timer/Counter2 Interrupt Mask
+ 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
+ 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
+ 'TIFR2' : '$37', # Timer/Counter2 Interrupt Flag
+ 'TIFR2_OCF2A': '$2', # Timer/Counter2 Output Compare
+ 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_PSR2': '$2', # Prescaler Reset Timer/Counter2
+ 'ASSR' : '$b6', # Asynchronous Status Register
+ 'ASSR_EXCLK': '$10', # Enable External Clock Interrup
+ 'ASSR_AS2': '$8', # AS2: Asynchronous Timer/Counte
+ 'ASSR_TCN2UB': '$4', # TCN2UB: Timer/Counter2 Update
+ 'ASSR_OCR2UB': '$2', # Output Compare Register2 Updat
+ 'ASSR_TCR2UB': '$1', # TCR2UB: Timer/Counter Control
+
+# Module WATCHDOG
+ 'WDTCR' : '$60', # Watchdog Timer Control Registe
+ 'WDTCR_WDCE': '$10', # Watchdog Change Enable
+ 'WDTCR_WDE': '$8', # Watch Dog Enable
+ 'WDTCR_WDP': '$7', # Watch Dog Timer Prescaler bits
+
+# Module EEPROM
+ 'EEAR' : '$41', # EEPROM Read/Write Access Byte
+ 'EEDR' : '$40', # EEPROM Data Register
+ 'EECR' : '$3f', # EEPROM Control Register
+ 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
+ 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
+ 'EECR_EEWE': '$2', # EEPROM Write Enable
+ 'EECR_EERE': '$1', # EEPROM Read Enable
+
+# Module SPI
+ 'SPCR' : '$4c', # SPI Control Register
+ 'SPCR_SPIE': '$80', # SPI Interrupt Enable
+ 'SPCR_SPE': '$40', # SPI Enable
+ 'SPCR_DORD': '$20', # Data Order
+ 'SPCR_MSTR': '$10', # Master/Slave Select
+ 'SPCR_CPOL': '$8', # Clock polarity
+ 'SPCR_CPHA': '$4', # Clock Phase
+ 'SPCR_SPR': '$3', # SPI Clock Rate Selects
+ 'SPSR' : '$4d', # SPI Status Register
+ 'SPSR_SPIF': '$80', # SPI Interrupt Flag
+ 'SPSR_WCOL': '$40', # Write Collision Flag
+ 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
+ 'SPDR' : '$4e', # SPI Data Register
+
+# Module PORTA
+ 'PORTA' : '$22', # Port A Data Register
+ 'DDRA' : '$21', # Port A Data Direction Register
+ 'PINA' : '$20', # Port A Input Pins
+
+# Module PORTB
+ 'PORTB' : '$25', # Port B Data Register
+ 'DDRB' : '$24', # Port B Data Direction Register
+ 'PINB' : '$23', # Port B Input Pins
+
+# Module PORTC
+ 'PORTC' : '$28', # Port C Data Register
+ 'DDRC' : '$27', # Port C Data Direction Register
+ 'PINC' : '$26', # Port C Input Pins
+
+# Module PORTD
+ 'PORTD' : '$2b', # Port D Data Register
+ 'DDRD' : '$2a', # Port D Data Direction Register
+ 'PIND' : '$29', # Port D Input Pins
+
+# Module ANALOG_COMPARATOR
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
+ 'ACSR' : '$50', # Analog Comparator Control And
+ 'ACSR_ACD': '$80', # Analog Comparator Disable
+ 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
+ 'ACSR_ACO': '$20', # Analog Compare Output
+ 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
+ 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
+ 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
+ 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
+ 'DIDR1' : '$7f', # Digital Input Disable Register
+ 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
+ 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
+
+# Module PORTE
+ 'PORTE' : '$2e', # Data Register, Port E
+ 'DDRE' : '$2d', # Data Direction Register, Port
+ 'PINE' : '$2c', # Input Pins, Port E
+
+# Module PORTF
+ 'PORTF' : '$31', # Data Register, Port F
+ 'DDRF' : '$30', # Data Direction Register, Port
+ 'PINF' : '$2f', # Input Pins, Port F
+
+# Module PORTG
+ 'PORTG' : '$34', # Port G Data Register
+ 'DDRG' : '$33', # Port G Data Direction Register
+ 'PING' : '$32', # Port G Input Pins
+
+# Module JTAG
+ 'OCDR' : '$51', # On-Chip Debug Related Register
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_JTD': '$80', # JTAG Interface Disable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+
+# Module EXTERNAL_INTERRUPT
+ 'EICRA' : '$69', # External Interrupt Control Reg
+ 'EICRA_ISC01': '$2', # External Interrupt Sense Contr
+ 'EICRA_ISC00': '$1', # External Interrupt Sense Contr
+ 'EIMSK' : '$3d', # External Interrupt Mask Regist
+ 'EIMSK_PCIE': '$f0', # Pin Change Interrupt Enables
+ 'EIMSK_INT0': '$1', # External Interrupt Request 0 E
+ 'EIFR' : '$3c', # External Interrupt Flag Regist
+ 'EIFR_PCIF': '$f0', # Pin Change Interrupt Flags
+ 'EIFR_INTF0': '$1', # External Interrupt Flag 0
+ 'PCMSK3' : '$73', # Pin Change Mask Register 3
+ 'PCMSK2' : '$6d', # Pin Change Mask Register 2
+ 'PCMSK1' : '$6c', # Pin Change Mask Register 1
+ 'PCMSK0' : '$6b', # Pin Change Mask Register 0
+
+# Module USI
+ 'USIDR' : '$ba', # USI Data Register
+ 'USISR' : '$b9', # USI Status Register
+ 'USISR_USISIF': '$80', # Start Condition Interrupt Flag
+ 'USISR_USIOIF': '$40', # Counter Overflow Interrupt Fla
+ 'USISR_USIPF': '$20', # Stop Condition Flag
+ 'USISR_USIDC': '$10', # Data Output Collision
+ 'USISR_USICNT': '$f', # USI Counter Value Bits
+ 'USICR' : '$b8', # USI Control Register
+ 'USICR_USISIE': '$80', # Start Condition Interrupt Enab
+ 'USICR_USIOIE': '$40', # Counter Overflow Interrupt Ena
+ 'USICR_USIWM': '$30', # USI Wire Mode Bits
+ 'USICR_USICS': '$c', # USI Clock Source Select Bits
+ 'USICR_USICLK': '$2', # Clock Strobe
+ 'USICR_USITC': '$1', # Toggle Clock Port Pin
+
+# Module AD_CONVERTER
+ 'ADMUX' : '$7c', # The ADC multiplexer Selection
+ 'ADMUX_REFS': '$c0', # Reference Selection Bits
+ 'ADMUX_ADLAR': '$20', # Left Adjust Result
+ 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
+ 'ADCSRA' : '$7a', # The ADC Control and Status reg
+ 'ADCSRA_ADEN': '$80', # ADC Enable
+ 'ADCSRA_ADSC': '$40', # ADC Start Conversion
+ 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
+ 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
+ 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
+ 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
+ 'ADC' : '$78', # ADC Data Register Bytes
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Sources
+ 'DIDR0' : '$7e', # Digital Input Disable Register
+ 'DIDR0_ADC7D': '$80', # ADC7 Digital input Disable
+ 'DIDR0_ADC6D': '$40', # ADC6 Digital input Disable
+ 'DIDR0_ADC5D': '$20', # ADC5 Digital input Disable
+ 'DIDR0_ADC4D': '$10', # ADC4 Digital input Disable
+ 'DIDR0_ADC3D': '$8', # ADC3 Digital input Disable
+ 'DIDR0_ADC2D': '$4', # ADC2 Digital input Disable
+ 'DIDR0_ADC1D': '$2', # ADC1 Digital input Disable
+ 'DIDR0_ADC0D': '$1', # ADC0 Digital input Disable
+
+# Module BOOT_LOAD
+ 'SPMCSR' : '$57', # Store Program Memory Control R
+ 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
+ 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
+ 'SPMCSR_RWWSRE': '$10', # Read While Write section read
+ 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
+ 'SPMCSR_PGWRT': '$4', # Page Write
+ 'SPMCSR_PGERS': '$2', # Page Erase
+ 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
+
+# Module USART0
+ 'UDR0' : '$c6', # USART I/O Data Register
+ 'UCSR0A' : '$c0', # USART Control and Status Regis
+ 'UCSR0A_RXC0': '$80', # USART Receive Complete
+ 'UCSR0A_TXC0': '$40', # USART Transmit Complete
+ 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
+ 'UCSR0A_FE0': '$10', # Framing Error
+ 'UCSR0A_DOR0': '$8', # Data OverRun
+ 'UCSR0A_UPE0': '$4', # USART Parity Error
+ 'UCSR0A_U2X0': '$2', # Double the USART Transmission
+ 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
+ 'UCSR0B' : '$c1', # USART Control and Status Regis
+ 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
+ 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
+ 'UCSR0B_UDRIE0': '$20', # USART Data Register Empty Inte
+ 'UCSR0B_RXEN0': '$10', # Receiver Enable
+ 'UCSR0B_TXEN0': '$8', # Transmitter Enable
+ 'UCSR0B_UCSZ02': '$4', # Character Size
+ 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
+ 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
+ 'UCSR0C' : '$c2', # USART Control and Status Regis
+ 'UCSR0C_UMSEL0': '$40', # USART Mode Select
+ 'UCSR0C_UPM0': '$30', # Parity Mode Bits
+ 'UCSR0C_USBS0': '$8', # Stop Bit Select
+ 'UCSR0C_UCSZ0': '$6', # Character Size
+ 'UCSR0C_UCPOL0': '$1', # Clock Polarity
+ 'UBRR0' : '$c4', # USART Baud Rate Register Byte
+
+# Module PORTH
+ 'PORTH' : '$da', # PORT H Data Register
+ 'DDRH' : '$d9', # PORT H Data Direction Register
+ 'PINH' : '$d8', # PORT H Input Pins
+
+# Module PORTJ
+ 'PORTJ' : '$dd', # PORT J Data Register
+ 'DDRJ' : '$dc', # PORT J Data Direction Register
+ 'PINJ' : '$db', # PORT J Input Pins
+
+# Module LCD
+ 'LCDDR19' : '$ff', # LCD Data Register 19
+ 'LCDDR18' : '$fe', # LCD Data Register 18
+ 'LCDDR17' : '$fd', # LCD Data Register 17
+ 'LCDDR16' : '$fc', # LCD Data Register 16
+ 'LCDDR15' : '$fb', # LCD Data Register 15
+ 'LCDDR14' : '$fa', # LCD Data Register 14
+ 'LCDDR13' : '$f9', # LCD Data Register 13
+ 'LCDDR12' : '$f8', # LCD Data Register 12
+ 'LCDDR11' : '$f7', # LCD Data Register 11
+ 'LCDDR10' : '$f6', # LCD Data Register 10
+ 'LCDDR9' : '$f5', # LCD Data Register 9
+ 'LCDDR8' : '$f4', # LCD Data Register 8
+ 'LCDDR7' : '$f3', # LCD Data Register 7
+ 'LCDDR6' : '$f2', # LCD Data Register 6
+ 'LCDDR5' : '$f1', # LCD Data Register 5
+ 'LCDDR4' : '$f0', # LCD Data Register 4
+ 'LCDDR3' : '$ef', # LCD Data Register 3
+ 'LCDDR2' : '$ee', # LCD Data Register 2
+ 'LCDDR1' : '$ed', # LCD Data Register 1
+ 'LCDDR0' : '$ec', # LCD Data Register 0
+ 'LCDCCR' : '$e7', # LCD Contrast Control Register
+ 'LCDCCR_LCDDC': '$e0', # LCD Display Configurations
+ 'LCDCCR_LCDMDT': '$10', # LCD Maximum Drive Time
+ 'LCDCCR_LCDCC': '$f', # LCD Contrast Controls
+ 'LCDFRR' : '$e6', # LCD Frame Rate Register
+ 'LCDFRR_LCDPS': '$70', # LCD Prescaler Selects
+ 'LCDFRR_LCDCD': '$7', # LCD Clock Dividers
+ 'LCDCRB' : '$e5', # LCD Control and Status Registe
+ 'LCDCRB_LCDCS': '$80', # LCD CLock Select
+ 'LCDCRB_LCD2B': '$40', # LCD 1/2 Bias Select
+ 'LCDCRB_LCDMUX': '$30', # LCD Mux Selects
+ 'LCDCRB_LCDPM': '$f', # LCD Port Masks
+ 'LCDCRA' : '$e4', # LCD Control and Status Registe
+ 'LCDCRA_LCDEN': '$80', # LCD Enable
+ 'LCDCRA_LCDAB': '$40', # LCD A or B waveform
+ 'LCDCRA_LCDIF': '$10', # LCD Interrupt Flag
+ 'LCDCRA_LCDIE': '$8', # LCD Interrupt Enable
+ 'LCDCRA_LCDBD': '$4', # LCD Buffer Disable
+ 'LCDCRA_LCDCCD': '$2', # LCD Contrast Control Disable
+ 'LCDCRA_LCDBL': '$1', # LCD Blanking
+
+# Module CPU
+ 'SREG' : '$5f', # Status Register
+ 'SREG_I': '$80', # Global Interrupt Enable
+ 'SREG_T': '$40', # Bit Copy Storage
+ 'SREG_H': '$20', # Half Carry Flag
+ 'SREG_S': '$10', # Sign Bit
+ 'SREG_V': '$8', # Two's Complement Overflow Flag
+ 'SREG_N': '$4', # Negative Flag
+ 'SREG_Z': '$2', # Zero Flag
+ 'SREG_C': '$1', # Carry Flag
+ 'SP' : '$5d', # Stack Pointer
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_JTD': '$80', # JTAG Interface Disable
+ 'MCUCR_BODS': '$40', # BOD Sleep
+ 'MCUCR_BODSE': '$20', # BOD Sleep Enable
+ 'MCUCR_PUD': '$10', # Pull-up disable
+ 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
+ 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+ 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
+ 'MCUSR_BORF': '$4', # Brown-out Reset Flag
+ 'MCUSR_EXTRF': '$2', # External Reset Flag
+ 'MCUSR_PORF': '$1', # Power-on reset flag
+ 'OSCCAL' : '$66', # Oscillator Calibration Value
+ 'CLKPR' : '$61', # Clock Prescale Register
+ 'CLKPR_CLKPCE': '$80', # Clock Prescaler Change Enable
+ 'CLKPR_CLKPS': '$f', # Clock Prescaler Select Bits
+ 'PRR' : '$64', # Power Reduction Register
+ 'PRR_PRLCD': '$10', # Power Reduction LCD
+ 'PRR_PRTIM1': '$8', # Power Reduction Timer/Counter1
+ 'PRR_PRSPI': '$4', # Power Reduction Serial Periphe
+ 'PRR_PRUSART0': '$2', # Power Reduction USART
+ 'PRR_PRADC': '$1', # Power Reduction ADC
+ 'SMCR' : '$53', # Sleep Mode Control Register
+ 'SMCR_SM': '$e', # Sleep Mode Select bits
+ 'SMCR_SE': '$1', # Sleep Enable
+ 'GPIOR2' : '$4b', # General Purpose IO Register 2
+ 'GPIOR1' : '$4a', # General Purpose IO Register 1
+ 'GPIOR0' : '$3e', # General Purpose IO Register 0
+
+ '__amforth_dummy':'0'
+}
diff --git a/amforth-6.5/avr8/devices/atmega3290a/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega3290a/words/no-jtag.asm
new file mode 100644
index 0000000..352a4bb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega3290a/words/no-jtag.asm
@@ -0,0 +1,14 @@
+; ( -- )
+; ( -- )
+; MCU
+; disable jtag at runtime
+VE_NOJTAG:
+ .dw $FF05
+ .db "-jtag",0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOJTAG
+XT_NOJTAG:
+ .dw PFA_NOJTAG
+PFA_NOJTAG:
+
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega3290a/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega3290a/words/no-wdt.asm
new file mode 100644
index 0000000..4a12261
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega3290a/words/no-wdt.asm
@@ -0,0 +1,22 @@
+; ( -- )
+; MCU
+; disable watch dog timer at runtime
+VE_NOWDT:
+ .dw $ff04
+ .db "-wdt"
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOWDT
+XT_NOWDT:
+ .dw PFA_NOWDT
+PFA_NOWDT:
+
+; Reset WDT
+ wdr
+; Write logical one to WDTOE and WDE
+ in_ temp1, WDTCR
+ ori temp1, (1<<WDTOE)|(1<<WDE)
+ out WDTCR, temp1
+; Turn off WDT
+ ldi temp1, (0<<WDE)
+ out_ WDTCR, temp1
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega3290a/words/sleep.asm b/amforth-6.5/avr8/devices/atmega3290a/words/sleep.asm
new file mode 100644
index 0000000..256249c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega3290a/words/sleep.asm
@@ -0,0 +1,19 @@
+; ( mode -- )
+; MCU
+; put the controller into the specified sleep mode
+VE_SLEEP:
+ .dw $ff05
+ .db "sleep", 0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_SLEEP
+XT_SLEEP:
+ .dw PFA_SLEEP
+PFA_SLEEP:
+ andi tosl, 7 ; leave only legal mode bits
+ lsl tosl ; move to correct location (bits 3-1)
+ ori tosl, 1 ; set the SE bit
+ out_ SMCR, tosl ; set the sleep config
+ sleep ; nighty-night
+ out_ SMCR, zerol ; 0 protects against accidental sleeps
+ loadtos ; pop argument from stack
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega3290p/atmega3290p.frt b/amforth-6.5/avr8/devices/atmega3290p/atmega3290p.frt
new file mode 100644
index 0000000..09c1c14
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega3290p/atmega3290p.frt
@@ -0,0 +1,333 @@
+\ Partname: ATmega3290P
+\ generated automatically
+
+\ TIMER_COUNTER_0
+&68 constant TCCR0A \ Timer/Counter0 Control Register
+ $80 constant TCCR0A_FOC0A \ Force Output Compare
+ $40 constant TCCR0A_WGM00 \ Waveform Generation Mode 0
+ $30 constant TCCR0A_COM0A \ Compare Match Output Modes
+ $08 constant TCCR0A_WGM01 \ Waveform Generation Mode 1
+ $07 constant TCCR0A_CS0 \ Clock Selects
+&70 constant TCNT0 \ Timer/Counter0
+&71 constant OCR0A \ Timer/Counter0 Output Compare Register
+&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
+ $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match Interrupt Enable
+ $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
+&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
+ $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0
+ $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
+&67 constant GTCCR \ General Timer/Control Register
+ $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
+ $01 constant GTCCR_PSR310 \ Prescaler Reset Timer/Counter1 and Timer/Counter0
+\ TIMER_COUNTER_1
+&128 constant TCCR1A \ Timer/Counter1 Control Register A
+ $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
+ $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
+ $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
+&129 constant TCCR1B \ Timer/Counter1 Control Register B
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
+ $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
+&130 constant TCCR1C \ Timer/Counter 1 Control Register C
+ $80 constant TCCR1C_FOC1A \ Force Output Compare 1A
+ $40 constant TCCR1C_FOC1B \ Force Output Compare 1B
+&132 constant TCNT1 \ Timer/Counter1 Bytes
+&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
+&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
+&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
+&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
+ $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
+ $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
+ $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
+ $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
+&54 constant TIFR1 \ Timer/Counter1 Interrupt Flag register
+ $20 constant TIFR1_ICF1 \ Input Capture Flag 1
+ $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
+ $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
+ $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
+\ TIMER_COUNTER_2
+&176 constant TCCR2A \ Timer/Counter2 Control Register
+ $80 constant TCCR2A_FOC2A \ Force Output Compare A
+ $40 constant TCCR2A_WGM20 \ Waveform Generation Mode
+ $30 constant TCCR2A_COM2A \ Compare Output Mode bits
+ $08 constant TCCR2A_WGM21 \ Waveform Generation Mode
+ $07 constant TCCR2A_CS2 \ Clock Select bits
+&178 constant TCNT2 \ Timer/Counter2
+&179 constant OCR2A \ Timer/Counter2 Output Compare Register
+&112 constant TIMSK2 \ Timer/Counter2 Interrupt Mask register
+ $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match Interrupt Enable
+ $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
+&55 constant TIFR2 \ Timer/Counter2 Interrupt Flag Register
+ $02 constant TIFR2_OCF2A \ Timer/Counter2 Output Compare Flag 2
+ $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
+&182 constant ASSR \ Asynchronous Status Register
+ $10 constant ASSR_EXCLK \ Enable External Clock Interrupt
+ $08 constant ASSR_AS2 \ AS2: Asynchronous Timer/Counter2
+ $04 constant ASSR_TCN2UB \ TCN2UB: Timer/Counter2 Update Busy
+ $02 constant ASSR_OCR2UB \ Output Compare Register2 Update Busy
+ $01 constant ASSR_TCR2UB \ TCR2UB: Timer/Counter Control Register2 Update Busy
+\ WATCHDOG
+&96 constant WDTCR \ Watchdog Timer Control Register
+ $10 constant WDTCR_WDCE \ Watchdog Change Enable
+ $08 constant WDTCR_WDE \ Watch Dog Enable
+ $07 constant WDTCR_WDP \ Watch Dog Timer Prescaler bits
+\ EEPROM
+&65 constant EEAR \ EEPROM Read/Write Access Bytes
+&64 constant EEDR \ EEPROM Data Register
+&63 constant EECR \ EEPROM Control Register
+ $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
+ $04 constant EECR_EEMWE \ EEPROM Master Write Enable
+ $02 constant EECR_EEWE \ EEPROM Write Enable
+ $01 constant EECR_EERE \ EEPROM Read Enable
+\ SPI
+&76 constant SPCR \ SPI Control Register
+ $80 constant SPCR_SPIE \ SPI Interrupt Enable
+ $40 constant SPCR_SPE \ SPI Enable
+ $20 constant SPCR_DORD \ Data Order
+ $10 constant SPCR_MSTR \ Master/Slave Select
+ $08 constant SPCR_CPOL \ Clock polarity
+ $04 constant SPCR_CPHA \ Clock Phase
+ $03 constant SPCR_SPR \ SPI Clock Rate Selects
+&77 constant SPSR \ SPI Status Register
+ $80 constant SPSR_SPIF \ SPI Interrupt Flag
+ $40 constant SPSR_WCOL \ Write Collision Flag
+ $01 constant SPSR_SPI2X \ Double SPI Speed Bit
+&78 constant SPDR \ SPI Data Register
+\ PORTA
+&34 constant PORTA \ Port A Data Register
+&33 constant DDRA \ Port A Data Direction Register
+&32 constant PINA \ Port A Input Pins
+\ PORTB
+&37 constant PORTB \ Port B Data Register
+&36 constant DDRB \ Port B Data Direction Register
+&35 constant PINB \ Port B Input Pins
+\ PORTC
+&40 constant PORTC \ Port C Data Register
+&39 constant DDRC \ Port C Data Direction Register
+&38 constant PINC \ Port C Input Pins
+\ PORTD
+&43 constant PORTD \ Port D Data Register
+&42 constant DDRD \ Port D Data Direction Register
+&41 constant PIND \ Port D Input Pins
+\ ANALOG_COMPARATOR
+&123 constant ADCSRB \ ADC Control and Status Register B
+ $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer Enable
+&80 constant ACSR \ Analog Comparator Control And Status Register
+ $80 constant ACSR_ACD \ Analog Comparator Disable
+ $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
+ $20 constant ACSR_ACO \ Analog Compare Output
+ $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
+ $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
+ $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
+ $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
+&127 constant DIDR1 \ Digital Input Disable Register 1
+ $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
+ $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
+\ PORTE
+&46 constant PORTE \ Data Register, Port E
+&45 constant DDRE \ Data Direction Register, Port E
+&44 constant PINE \ Input Pins, Port E
+\ PORTF
+&49 constant PORTF \ Data Register, Port F
+&48 constant DDRF \ Data Direction Register, Port F
+&47 constant PINF \ Input Pins, Port F
+\ PORTG
+&52 constant PORTG \ Port G Data Register
+&51 constant DDRG \ Port G Data Direction Register
+&50 constant PING \ Port G Input Pins
+\ JTAG
+&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
+&85 constant MCUCR \ MCU Control Register
+ $80 constant MCUCR_JTD \ JTAG Interface Disable
+&84 constant MCUSR \ MCU Status Register
+ $10 constant MCUSR_JTRF \ JTAG Reset Flag
+\ EXTERNAL_INTERRUPT
+&105 constant EICRA \ External Interrupt Control Register A
+ $02 constant EICRA_ISC01 \ External Interrupt Sense Control 0 Bit 1
+ $01 constant EICRA_ISC00 \ External Interrupt Sense Control 0 Bit 0
+&61 constant EIMSK \ External Interrupt Mask Register
+ $F0 constant EIMSK_PCIE \ Pin Change Interrupt Enables
+ $01 constant EIMSK_INT0 \ External Interrupt Request 0 Enable
+&60 constant EIFR \ External Interrupt Flag Register
+ $F0 constant EIFR_PCIF \ Pin Change Interrupt Flags
+ $01 constant EIFR_INTF0 \ External Interrupt Flag 0
+&115 constant PCMSK3 \ Pin Change Mask Register 3
+&109 constant PCMSK2 \ Pin Change Mask Register 2
+&108 constant PCMSK1 \ Pin Change Mask Register 1
+&107 constant PCMSK0 \ Pin Change Mask Register 0
+\ USI
+&186 constant USIDR \ USI Data Register
+&185 constant USISR \ USI Status Register
+ $80 constant USISR_USISIF \ Start Condition Interrupt Flag
+ $40 constant USISR_USIOIF \ Counter Overflow Interrupt Flag
+ $20 constant USISR_USIPF \ Stop Condition Flag
+ $10 constant USISR_USIDC \ Data Output Collision
+ $0F constant USISR_USICNT \ USI Counter Value Bits
+&184 constant USICR \ USI Control Register
+ $80 constant USICR_USISIE \ Start Condition Interrupt Enable
+ $40 constant USICR_USIOIE \ Counter Overflow Interrupt Enable
+ $30 constant USICR_USIWM \ USI Wire Mode Bits
+ $0C constant USICR_USICS \ USI Clock Source Select Bits
+ $02 constant USICR_USICLK \ Clock Strobe
+ $01 constant USICR_USITC \ Toggle Clock Port Pin
+\ AD_CONVERTER
+&124 constant ADMUX \ The ADC multiplexer Selection Register
+ $C0 constant ADMUX_REFS \ Reference Selection Bits
+ $20 constant ADMUX_ADLAR \ Left Adjust Result
+ $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
+&122 constant ADCSRA \ The ADC Control and Status register
+ $80 constant ADCSRA_ADEN \ ADC Enable
+ $40 constant ADCSRA_ADSC \ ADC Start Conversion
+ $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
+ $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
+ $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
+ $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
+&120 constant ADC \ ADC Data Register Bytes
+&126 constant DIDR0 \ Digital Input Disable Register 0
+ $80 constant DIDR0_ADC7D \ ADC7 Digital input Disable
+ $40 constant DIDR0_ADC6D \ ADC6 Digital input Disable
+ $20 constant DIDR0_ADC5D \ ADC5 Digital input Disable
+ $10 constant DIDR0_ADC4D \ ADC4 Digital input Disable
+ $08 constant DIDR0_ADC3D \ ADC3 Digital input Disable
+ $04 constant DIDR0_ADC2D \ ADC2 Digital input Disable
+ $02 constant DIDR0_ADC1D \ ADC1 Digital input Disable
+ $01 constant DIDR0_ADC0D \ ADC0 Digital input Disable
+\ BOOT_LOAD
+&87 constant SPMCSR \ Store Program Memory Control Register
+ $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
+ $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
+ $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
+ $04 constant SPMCSR_PGWRT \ Page Write
+ $02 constant SPMCSR_PGERS \ Page Erase
+ $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
+\ USART0
+&198 constant UDR0 \ USART I/O Data Register
+&192 constant UCSR0A \ USART Control and Status Register A
+ $80 constant UCSR0A_RXC0 \ USART Receive Complete
+ $40 constant UCSR0A_TXC0 \ USART Transmit Complete
+ $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
+ $10 constant UCSR0A_FE0 \ Framing Error
+ $08 constant UCSR0A_DOR0 \ Data OverRun
+ $04 constant UCSR0A_UPE0 \ USART Parity Error
+ $02 constant UCSR0A_U2X0 \ Double the USART Transmission Speed
+ $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
+&193 constant UCSR0B \ USART Control and Status Register B
+ $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
+ $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
+ $20 constant UCSR0B_UDRIE0 \ USART Data Register Empty Interrupt Enable
+ $10 constant UCSR0B_RXEN0 \ Receiver Enable
+ $08 constant UCSR0B_TXEN0 \ Transmitter Enable
+ $04 constant UCSR0B_UCSZ02 \ Character Size
+ $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
+ $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
+&194 constant UCSR0C \ USART Control and Status Register C
+ $40 constant UCSR0C_UMSEL0 \ USART Mode Select
+ $30 constant UCSR0C_UPM0 \ Parity Mode Bits
+ $08 constant UCSR0C_USBS0 \ Stop Bit Select
+ $06 constant UCSR0C_UCSZ0 \ Character Size
+ $01 constant UCSR0C_UCPOL0 \ Clock Polarity
+&196 constant UBRR0 \ USART Baud Rate Register Bytes
+\ PORTH
+&218 constant PORTH \ PORT H Data Register
+&217 constant DDRH \ PORT H Data Direction Register
+&216 constant PINH \ PORT H Input Pins
+\ PORTJ
+&221 constant PORTJ \ PORT J Data Register
+&220 constant DDRJ \ PORT J Data Direction Register
+&219 constant PINJ \ PORT J Input Pins
+\ LCD
+&255 constant LCDDR19 \ LCD Data Register 19
+&254 constant LCDDR18 \ LCD Data Register 18
+&253 constant LCDDR17 \ LCD Data Register 17
+&252 constant LCDDR16 \ LCD Data Register 16
+&251 constant LCDDR15 \ LCD Data Register 15
+&250 constant LCDDR14 \ LCD Data Register 14
+&249 constant LCDDR13 \ LCD Data Register 13
+&248 constant LCDDR12 \ LCD Data Register 12
+&247 constant LCDDR11 \ LCD Data Register 11
+&246 constant LCDDR10 \ LCD Data Register 10
+&245 constant LCDDR9 \ LCD Data Register 9
+&244 constant LCDDR8 \ LCD Data Register 8
+&243 constant LCDDR7 \ LCD Data Register 7
+&242 constant LCDDR6 \ LCD Data Register 6
+&241 constant LCDDR5 \ LCD Data Register 5
+&240 constant LCDDR4 \ LCD Data Register 4
+&239 constant LCDDR3 \ LCD Data Register 3
+&238 constant LCDDR2 \ LCD Data Register 2
+&237 constant LCDDR1 \ LCD Data Register 1
+&236 constant LCDDR0 \ LCD Data Register 0
+&231 constant LCDCCR \ LCD Contrast Control Register
+ $E0 constant LCDCCR_LCDDC \ LCD Display Configurations
+ $10 constant LCDCCR_LCDMDT \ LCD Maximum Drive Time
+ $0F constant LCDCCR_LCDCC \ LCD Contrast Controls
+&230 constant LCDFRR \ LCD Frame Rate Register
+ $70 constant LCDFRR_LCDPS \ LCD Prescaler Selects
+ $07 constant LCDFRR_LCDCD \ LCD Clock Dividers
+&229 constant LCDCRB \ LCD Control and Status Register B
+ $80 constant LCDCRB_LCDCS \ LCD CLock Select
+ $40 constant LCDCRB_LCD2B \ LCD 1/2 Bias Select
+ $30 constant LCDCRB_LCDMUX \ LCD Mux Selects
+ $0F constant LCDCRB_LCDPM \ LCD Port Masks
+&228 constant LCDCRA \ LCD Control and Status Register A
+ $80 constant LCDCRA_LCDEN \ LCD Enable
+ $40 constant LCDCRA_LCDAB \ LCD A or B waveform
+ $10 constant LCDCRA_LCDIF \ LCD Interrupt Flag
+ $08 constant LCDCRA_LCDIE \ LCD Interrupt Enable
+ $04 constant LCDCRA_LCDBD \ LCD Buffer Disable
+ $02 constant LCDCRA_LCDCCD \ LCD Contrast Control Disable
+ $01 constant LCDCRA_LCDBL \ LCD Blanking
+\ CPU
+&95 constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ $08 constant SREG_V \ Two's Complement Overflow Flag
+ $04 constant SREG_N \ Negative Flag
+ $02 constant SREG_Z \ Zero Flag
+ $01 constant SREG_C \ Carry Flag
+&93 constant SP \ Stack Pointer
+&102 constant OSCCAL \ Oscillator Calibration Value
+&97 constant CLKPR \ Clock Prescale Register
+ $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable
+ $0F constant CLKPR_CLKPS \ Clock Prescaler Select Bits
+&100 constant PRR \ Power Reduction Register
+ $10 constant PRR_PRLCD \ Power Reduction LCD
+ $08 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
+ $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
+ $02 constant PRR_PRUSART0 \ Power Reduction USART
+ $01 constant PRR_PRADC \ Power Reduction ADC
+&83 constant SMCR \ Sleep Mode Control Register
+ $0E constant SMCR_SM \ Sleep Mode Select bits
+ $01 constant SMCR_SE \ Sleep Enable
+&75 constant GPIOR2 \ General Purpose IO Register 2
+&74 constant GPIOR1 \ General Purpose IO Register 1
+&62 constant GPIOR0 \ General Purpose IO Register 0
+
+\ Interrupts
+&2 constant INT0Addr \ External Interrupt Request 0
+&4 constant PCINT0Addr \ Pin Change Interrupt Request 0
+&6 constant PCINT1Addr \ Pin Change Interrupt Request 1
+&8 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
+&10 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
+&12 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+&14 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
+&16 constant TIMER1_COMPBAddr \ Timer/Counter Compare Match B
+&18 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+&20 constant TIMER0_COMPAddr \ Timer/Counter0 Compare Match
+&22 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
+&24 constant SPI__STCAddr \ SPI Serial Transfer Complete
+&26 constant USART__RXAddr \ USART, Rx Complete
+&28 constant USART__UDREAddr \ USART Data register Empty
+&30 constant USART0__TXAddr \ USART0, Tx Complete
+&32 constant USI_STARTAddr \ USI Start Condition
+&34 constant USI_OVERFLOWAddr \ USI Overflow
+&36 constant ANALOG_COMPAddr \ Analog Comparator
+&38 constant ADCAddr \ ADC Conversion Complete
+&40 constant EE_READYAddr \ EEPROM Ready
+&42 constant SPM_READYAddr \ Store Program Memory Read
+&44 constant LCDAddr \ LCD Start of Frame
+&46 constant PCINT2Addr \ Pin Change Interrupt Request 2
+&48 constant PCINT3Addr \ Pin Change Interrupt Request 3
diff --git a/amforth-6.5/avr8/devices/atmega3290p/device.asm b/amforth-6.5/avr8/devices/atmega3290p/device.asm
new file mode 100644
index 0000000..7019d09
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega3290p/device.asm
@@ -0,0 +1,115 @@
+; Partname: ATmega3290P
+; generated automatically, do not edit
+
+.nolist
+ .include "m3290Pdef.inc"
+.list
+
+.equ ramstart = 256
+.equ CELLSIZE = 2
+.macro readflashcell
+ lsl zl
+ rol zh
+ lpm @0, Z+
+ lpm @1, Z+
+.endmacro
+.macro writeflashcell
+ lsl zl
+ rol zh
+.endmacro
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_TIMER_COUNTER_2 = 0
+.set WANT_WATCHDOG = 0
+.set WANT_EEPROM = 0
+.set WANT_SPI = 0
+.set WANT_PORTA = 0
+.set WANT_PORTB = 0
+.set WANT_PORTC = 0
+.set WANT_PORTD = 0
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_PORTE = 0
+.set WANT_PORTF = 0
+.set WANT_PORTG = 0
+.set WANT_JTAG = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_USI = 0
+.set WANT_AD_CONVERTER = 0
+.set WANT_BOOT_LOAD = 0
+.set WANT_USART0 = 0
+.set WANT_PORTH = 0
+.set WANT_PORTJ = 0
+.set WANT_LCD = 0
+.set WANT_CPU = 0
+.equ intvecsize = 2 ; please verify; flash size: 32768 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.org 2
+ rcall isr ; External Interrupt Request 0
+.org 4
+ rcall isr ; Pin Change Interrupt Request 0
+.org 6
+ rcall isr ; Pin Change Interrupt Request 1
+.org 8
+ rcall isr ; Timer/Counter2 Compare Match
+.org 10
+ rcall isr ; Timer/Counter2 Overflow
+.org 12
+ rcall isr ; Timer/Counter1 Capture Event
+.org 14
+ rcall isr ; Timer/Counter1 Compare Match A
+.org 16
+ rcall isr ; Timer/Counter Compare Match B
+.org 18
+ rcall isr ; Timer/Counter1 Overflow
+.org 20
+ rcall isr ; Timer/Counter0 Compare Match
+.org 22
+ rcall isr ; Timer/Counter0 Overflow
+.org 24
+ rcall isr ; SPI Serial Transfer Complete
+.org 26
+ rcall isr ; USART, Rx Complete
+.org 28
+ rcall isr ; USART Data register Empty
+.org 30
+ rcall isr ; USART0, Tx Complete
+.org 32
+ rcall isr ; USI Start Condition
+.org 34
+ rcall isr ; USI Overflow
+.org 36
+ rcall isr ; Analog Comparator
+.org 38
+ rcall isr ; ADC Conversion Complete
+.org 40
+ rcall isr ; EEPROM Ready
+.org 42
+ rcall isr ; Store Program Memory Read
+.org 44
+ rcall isr ; LCD Start of Frame
+.org 46
+ rcall isr ; Pin Change Interrupt Request 2
+.org 48
+ rcall isr ; Pin Change Interrupt Request 3
+.equ INTVECTORS = 25
+.nooverlap
+
+; compatability layer (maybe empty)
+.equ EEPE = EEWE
+.equ EEMPE = EEMWE
+
+; controller data area, environment query mcu-info
+mcu_info:
+mcu_ramsize:
+ .dw 2048
+mcu_eepromsize:
+ .dw 1024
+mcu_maxdp:
+ .dw 28672
+mcu_numints:
+ .dw 25
+mcu_name:
+ .dw 11
+ .db "ATmega3290P",0
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega3290p/device.inc b/amforth-6.5/avr8/devices/atmega3290p/device.inc
new file mode 100644
index 0000000..824661b
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega3290p/device.inc
@@ -0,0 +1,1443 @@
+; Partname: ATmega3290P
+; generated automatically, no not edit
+
+.if WANT_TIMER_COUNTER_0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Control Register
+VE_TCCR0A:
+ .dw $ff06
+ .db "TCCR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0A
+XT_TCCR0A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0A:
+ .dw 68
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw 70
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0A:
+ .dw $ff05
+ .db "OCR0A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0A
+XT_OCR0A:
+ .dw PFA_DOVARIABLE
+PFA_OCR0A:
+ .dw 71
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Mask Register
+VE_TIMSK0:
+ .dw $ff06
+ .db "TIMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK0
+XT_TIMSK0:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK0:
+ .dw 110
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Flag register
+VE_TIFR0:
+ .dw $ff05
+ .db "TIFR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR0
+XT_TIFR0:
+ .dw PFA_DOVARIABLE
+PFA_TIFR0:
+ .dw 53
+; ( -- addr ) System Constant
+; R( -- )
+; General Timer/Control Register
+VE_GTCCR:
+ .dw $ff05
+ .db "GTCCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GTCCR
+XT_GTCCR:
+ .dw PFA_DOVARIABLE
+PFA_GTCCR:
+ .dw 67
+
+.endif
+.if WANT_TIMER_COUNTER_1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw 128
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw 129
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter 1 Control Register C
+VE_TCCR1C:
+ .dw $ff06
+ .db "TCCR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1C
+XT_TCCR1C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1C:
+ .dw 130
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Bytes
+VE_TCNT1:
+ .dw $ff05
+ .db "TCNT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1
+XT_TCNT1:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1:
+ .dw 132
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register A Bytes
+VE_OCR1A:
+ .dw $ff05
+ .db "OCR1A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1A
+XT_OCR1A:
+ .dw PFA_DOVARIABLE
+PFA_OCR1A:
+ .dw 136
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register B Bytes
+VE_OCR1B:
+ .dw $ff05
+ .db "OCR1B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1B
+XT_OCR1B:
+ .dw PFA_DOVARIABLE
+PFA_OCR1B:
+ .dw 138
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Bytes
+VE_ICR1:
+ .dw $ff04
+ .db "ICR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1
+XT_ICR1:
+ .dw PFA_DOVARIABLE
+PFA_ICR1:
+ .dw 134
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Mask Register
+VE_TIMSK1:
+ .dw $ff06
+ .db "TIMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK1
+XT_TIMSK1:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK1:
+ .dw 111
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Flag register
+VE_TIFR1:
+ .dw $ff05
+ .db "TIFR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR1
+XT_TIFR1:
+ .dw PFA_DOVARIABLE
+PFA_TIFR1:
+ .dw 54
+
+.endif
+.if WANT_TIMER_COUNTER_2 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register
+VE_TCCR2A:
+ .dw $ff06
+ .db "TCCR2A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2A
+XT_TCCR2A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2A:
+ .dw 176
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2
+VE_TCNT2:
+ .dw $ff05
+ .db "TCNT2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT2
+XT_TCNT2:
+ .dw PFA_DOVARIABLE
+PFA_TCNT2:
+ .dw 178
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register
+VE_OCR2A:
+ .dw $ff05
+ .db "OCR2A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2A
+XT_OCR2A:
+ .dw PFA_DOVARIABLE
+PFA_OCR2A:
+ .dw 179
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Interrupt Mask register
+VE_TIMSK2:
+ .dw $ff06
+ .db "TIMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK2
+XT_TIMSK2:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK2:
+ .dw 112
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Interrupt Flag Register
+VE_TIFR2:
+ .dw $ff05
+ .db "TIFR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR2
+XT_TIFR2:
+ .dw PFA_DOVARIABLE
+PFA_TIFR2:
+ .dw 55
+; ( -- addr ) System Constant
+; R( -- )
+; Asynchronous Status Register
+VE_ASSR:
+ .dw $ff04
+ .db "ASSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ASSR
+XT_ASSR:
+ .dw PFA_DOVARIABLE
+PFA_ASSR:
+ .dw 182
+
+.endif
+.if WANT_WATCHDOG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCR:
+ .dw $ff05
+ .db "WDTCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCR
+XT_WDTCR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCR:
+ .dw 96
+
+.endif
+.if WANT_EEPROM == 1
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Read/Write Access Bytes
+VE_EEAR:
+ .dw $ff04
+ .db "EEAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEAR
+XT_EEAR:
+ .dw PFA_DOVARIABLE
+PFA_EEAR:
+ .dw 65
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw 64
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw 63
+
+.endif
+.if WANT_SPI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR:
+ .dw $ff04
+ .db "SPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR
+XT_SPCR:
+ .dw PFA_DOVARIABLE
+PFA_SPCR:
+ .dw 76
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR:
+ .dw $ff04
+ .db "SPSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR
+XT_SPSR:
+ .dw PFA_DOVARIABLE
+PFA_SPSR:
+ .dw 77
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR:
+ .dw $ff04
+ .db "SPDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR
+XT_SPDR:
+ .dw PFA_DOVARIABLE
+PFA_SPDR:
+ .dw 78
+
+.endif
+.if WANT_PORTA == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Register
+VE_PORTA:
+ .dw $ff05
+ .db "PORTA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTA
+XT_PORTA:
+ .dw PFA_DOVARIABLE
+PFA_PORTA:
+ .dw 34
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Direction Register
+VE_DDRA:
+ .dw $ff04
+ .db "DDRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRA
+XT_DDRA:
+ .dw PFA_DOVARIABLE
+PFA_DDRA:
+ .dw 33
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Input Pins
+VE_PINA:
+ .dw $ff04
+ .db "PINA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINA
+XT_PINA:
+ .dw PFA_DOVARIABLE
+PFA_PINA:
+ .dw 32
+
+.endif
+.if WANT_PORTB == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw 37
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw 36
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw 35
+
+.endif
+.if WANT_PORTC == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Register
+VE_PORTC:
+ .dw $ff05
+ .db "PORTC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTC
+XT_PORTC:
+ .dw PFA_DOVARIABLE
+PFA_PORTC:
+ .dw 40
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Direction Register
+VE_DDRC:
+ .dw $ff04
+ .db "DDRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRC
+XT_DDRC:
+ .dw PFA_DOVARIABLE
+PFA_DDRC:
+ .dw 39
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Input Pins
+VE_PINC:
+ .dw $ff04
+ .db "PINC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINC
+XT_PINC:
+ .dw PFA_DOVARIABLE
+PFA_PINC:
+ .dw 38
+
+.endif
+.if WANT_PORTD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw 43
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw 42
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw 41
+
+.endif
+.if WANT_ANALOG_COMPARATOR == 1
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Control and Status Register B
+VE_ADCSRB:
+ .dw $ff06
+ .db "ADCSRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRB
+XT_ADCSRB:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRB:
+ .dw 123
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Control And Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw 80
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 1
+VE_DIDR1:
+ .dw $ff05
+ .db "DIDR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR1
+XT_DIDR1:
+ .dw PFA_DOVARIABLE
+PFA_DIDR1:
+ .dw 127
+
+.endif
+.if WANT_PORTE == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port E
+VE_PORTE:
+ .dw $ff05
+ .db "PORTE",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTE
+XT_PORTE:
+ .dw PFA_DOVARIABLE
+PFA_PORTE:
+ .dw 46
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port E
+VE_DDRE:
+ .dw $ff04
+ .db "DDRE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRE
+XT_DDRE:
+ .dw PFA_DOVARIABLE
+PFA_DDRE:
+ .dw 45
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port E
+VE_PINE:
+ .dw $ff04
+ .db "PINE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINE
+XT_PINE:
+ .dw PFA_DOVARIABLE
+PFA_PINE:
+ .dw 44
+
+.endif
+.if WANT_PORTF == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port F
+VE_PORTF:
+ .dw $ff05
+ .db "PORTF",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTF
+XT_PORTF:
+ .dw PFA_DOVARIABLE
+PFA_PORTF:
+ .dw 49
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port F
+VE_DDRF:
+ .dw $ff04
+ .db "DDRF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRF
+XT_DDRF:
+ .dw PFA_DOVARIABLE
+PFA_DDRF:
+ .dw 48
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port F
+VE_PINF:
+ .dw $ff04
+ .db "PINF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINF
+XT_PINF:
+ .dw PFA_DOVARIABLE
+PFA_PINF:
+ .dw 47
+
+.endif
+.if WANT_PORTG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Data Register
+VE_PORTG:
+ .dw $ff05
+ .db "PORTG",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTG
+XT_PORTG:
+ .dw PFA_DOVARIABLE
+PFA_PORTG:
+ .dw 52
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Data Direction Register
+VE_DDRG:
+ .dw $ff04
+ .db "DDRG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRG
+XT_DDRG:
+ .dw PFA_DOVARIABLE
+PFA_DDRG:
+ .dw 51
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Input Pins
+VE_PING:
+ .dw $ff04
+ .db "PING"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PING
+XT_PING:
+ .dw PFA_DOVARIABLE
+PFA_PING:
+ .dw 50
+
+.endif
+.if WANT_JTAG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; On-Chip Debug Related Register in I/O Memory
+VE_OCDR:
+ .dw $ff04
+ .db "OCDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCDR
+XT_OCDR:
+ .dw PFA_DOVARIABLE
+PFA_OCDR:
+ .dw 81
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw 85
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Status Register
+VE_MCUSR:
+ .dw $ff05
+ .db "MCUSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUSR
+XT_MCUSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUSR:
+ .dw 84
+
+.endif
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register A
+VE_EICRA:
+ .dw $ff05
+ .db "EICRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRA
+XT_EICRA:
+ .dw PFA_DOVARIABLE
+PFA_EICRA:
+ .dw 105
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Mask Register
+VE_EIMSK:
+ .dw $ff05
+ .db "EIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIMSK
+XT_EIMSK:
+ .dw PFA_DOVARIABLE
+PFA_EIMSK:
+ .dw 61
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Flag Register
+VE_EIFR:
+ .dw $ff04
+ .db "EIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIFR
+XT_EIFR:
+ .dw PFA_DOVARIABLE
+PFA_EIFR:
+ .dw 60
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 3
+VE_PCMSK3:
+ .dw $ff06
+ .db "PCMSK3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK3
+XT_PCMSK3:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK3:
+ .dw 115
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 2
+VE_PCMSK2:
+ .dw $ff06
+ .db "PCMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK2
+XT_PCMSK2:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK2:
+ .dw 109
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 1
+VE_PCMSK1:
+ .dw $ff06
+ .db "PCMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK1
+XT_PCMSK1:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK1:
+ .dw 108
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 0
+VE_PCMSK0:
+ .dw $ff06
+ .db "PCMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK0
+XT_PCMSK0:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK0:
+ .dw 107
+
+.endif
+.if WANT_USI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USI Data Register
+VE_USIDR:
+ .dw $ff05
+ .db "USIDR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USIDR
+XT_USIDR:
+ .dw PFA_DOVARIABLE
+PFA_USIDR:
+ .dw 186
+; ( -- addr ) System Constant
+; R( -- )
+; USI Status Register
+VE_USISR:
+ .dw $ff05
+ .db "USISR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USISR
+XT_USISR:
+ .dw PFA_DOVARIABLE
+PFA_USISR:
+ .dw 185
+; ( -- addr ) System Constant
+; R( -- )
+; USI Control Register
+VE_USICR:
+ .dw $ff05
+ .db "USICR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USICR
+XT_USICR:
+ .dw PFA_DOVARIABLE
+PFA_USICR:
+ .dw 184
+
+.endif
+.if WANT_AD_CONVERTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC multiplexer Selection Register
+VE_ADMUX:
+ .dw $ff05
+ .db "ADMUX",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADMUX
+XT_ADMUX:
+ .dw PFA_DOVARIABLE
+PFA_ADMUX:
+ .dw 124
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register
+VE_ADCSRA:
+ .dw $ff06
+ .db "ADCSRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRA
+XT_ADCSRA:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRA:
+ .dw 122
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register Bytes
+VE_ADC:
+ .dw $ff03
+ .db "ADC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADC
+XT_ADC:
+ .dw PFA_DOVARIABLE
+PFA_ADC:
+ .dw 120
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 0
+VE_DIDR0:
+ .dw $ff05
+ .db "DIDR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR0
+XT_DIDR0:
+ .dw PFA_DOVARIABLE
+PFA_DIDR0:
+ .dw 126
+
+.endif
+.if WANT_BOOT_LOAD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control Register
+VE_SPMCSR:
+ .dw $ff06
+ .db "SPMCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCSR
+XT_SPMCSR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCSR:
+ .dw 87
+
+.endif
+.if WANT_USART0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR0:
+ .dw $ff04
+ .db "UDR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR0
+XT_UDR0:
+ .dw PFA_DOVARIABLE
+PFA_UDR0:
+ .dw 198
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR0A:
+ .dw $ff06
+ .db "UCSR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0A
+XT_UCSR0A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0A:
+ .dw 192
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR0B:
+ .dw $ff06
+ .db "UCSR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0B
+XT_UCSR0B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0B:
+ .dw 193
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR0C:
+ .dw $ff06
+ .db "UCSR0C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0C
+XT_UCSR0C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0C:
+ .dw 194
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Bytes
+VE_UBRR0:
+ .dw $ff05
+ .db "UBRR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR0
+XT_UBRR0:
+ .dw PFA_DOVARIABLE
+PFA_UBRR0:
+ .dw 196
+
+.endif
+.if WANT_PORTH == 1
+; ( -- addr ) System Constant
+; R( -- )
+; PORT H Data Register
+VE_PORTH:
+ .dw $ff05
+ .db "PORTH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTH
+XT_PORTH:
+ .dw PFA_DOVARIABLE
+PFA_PORTH:
+ .dw 218
+; ( -- addr ) System Constant
+; R( -- )
+; PORT H Data Direction Register
+VE_DDRH:
+ .dw $ff04
+ .db "DDRH"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRH
+XT_DDRH:
+ .dw PFA_DOVARIABLE
+PFA_DDRH:
+ .dw 217
+; ( -- addr ) System Constant
+; R( -- )
+; PORT H Input Pins
+VE_PINH:
+ .dw $ff04
+ .db "PINH"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINH
+XT_PINH:
+ .dw PFA_DOVARIABLE
+PFA_PINH:
+ .dw 216
+
+.endif
+.if WANT_PORTJ == 1
+; ( -- addr ) System Constant
+; R( -- )
+; PORT J Data Register
+VE_PORTJ:
+ .dw $ff05
+ .db "PORTJ",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTJ
+XT_PORTJ:
+ .dw PFA_DOVARIABLE
+PFA_PORTJ:
+ .dw 221
+; ( -- addr ) System Constant
+; R( -- )
+; PORT J Data Direction Register
+VE_DDRJ:
+ .dw $ff04
+ .db "DDRJ"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRJ
+XT_DDRJ:
+ .dw PFA_DOVARIABLE
+PFA_DDRJ:
+ .dw 220
+; ( -- addr ) System Constant
+; R( -- )
+; PORT J Input Pins
+VE_PINJ:
+ .dw $ff04
+ .db "PINJ"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINJ
+XT_PINJ:
+ .dw PFA_DOVARIABLE
+PFA_PINJ:
+ .dw 219
+
+.endif
+.if WANT_LCD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 19
+VE_LCDDR19:
+ .dw $ff07
+ .db "LCDDR19",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR19
+XT_LCDDR19:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR19:
+ .dw 255
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 18
+VE_LCDDR18:
+ .dw $ff07
+ .db "LCDDR18",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR18
+XT_LCDDR18:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR18:
+ .dw 254
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 17
+VE_LCDDR17:
+ .dw $ff07
+ .db "LCDDR17",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR17
+XT_LCDDR17:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR17:
+ .dw 253
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 16
+VE_LCDDR16:
+ .dw $ff07
+ .db "LCDDR16",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR16
+XT_LCDDR16:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR16:
+ .dw 252
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 15
+VE_LCDDR15:
+ .dw $ff07
+ .db "LCDDR15",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR15
+XT_LCDDR15:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR15:
+ .dw 251
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 14
+VE_LCDDR14:
+ .dw $ff07
+ .db "LCDDR14",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR14
+XT_LCDDR14:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR14:
+ .dw 250
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 13
+VE_LCDDR13:
+ .dw $ff07
+ .db "LCDDR13",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR13
+XT_LCDDR13:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR13:
+ .dw 249
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 12
+VE_LCDDR12:
+ .dw $ff07
+ .db "LCDDR12",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR12
+XT_LCDDR12:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR12:
+ .dw 248
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 11
+VE_LCDDR11:
+ .dw $ff07
+ .db "LCDDR11",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR11
+XT_LCDDR11:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR11:
+ .dw 247
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 10
+VE_LCDDR10:
+ .dw $ff07
+ .db "LCDDR10",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR10
+XT_LCDDR10:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR10:
+ .dw 246
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 9
+VE_LCDDR9:
+ .dw $ff06
+ .db "LCDDR9"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR9
+XT_LCDDR9:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR9:
+ .dw 245
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 8
+VE_LCDDR8:
+ .dw $ff06
+ .db "LCDDR8"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR8
+XT_LCDDR8:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR8:
+ .dw 244
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 7
+VE_LCDDR7:
+ .dw $ff06
+ .db "LCDDR7"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR7
+XT_LCDDR7:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR7:
+ .dw 243
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 6
+VE_LCDDR6:
+ .dw $ff06
+ .db "LCDDR6"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR6
+XT_LCDDR6:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR6:
+ .dw 242
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 5
+VE_LCDDR5:
+ .dw $ff06
+ .db "LCDDR5"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR5
+XT_LCDDR5:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR5:
+ .dw 241
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 4
+VE_LCDDR4:
+ .dw $ff06
+ .db "LCDDR4"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR4
+XT_LCDDR4:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR4:
+ .dw 240
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 3
+VE_LCDDR3:
+ .dw $ff06
+ .db "LCDDR3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR3
+XT_LCDDR3:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR3:
+ .dw 239
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 2
+VE_LCDDR2:
+ .dw $ff06
+ .db "LCDDR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR2
+XT_LCDDR2:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR2:
+ .dw 238
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 1
+VE_LCDDR1:
+ .dw $ff06
+ .db "LCDDR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR1
+XT_LCDDR1:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR1:
+ .dw 237
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 0
+VE_LCDDR0:
+ .dw $ff06
+ .db "LCDDR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR0
+XT_LCDDR0:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR0:
+ .dw 236
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Contrast Control Register
+VE_LCDCCR:
+ .dw $ff06
+ .db "LCDCCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDCCR
+XT_LCDCCR:
+ .dw PFA_DOVARIABLE
+PFA_LCDCCR:
+ .dw 231
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Frame Rate Register
+VE_LCDFRR:
+ .dw $ff06
+ .db "LCDFRR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDFRR
+XT_LCDFRR:
+ .dw PFA_DOVARIABLE
+PFA_LCDFRR:
+ .dw 230
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Control and Status Register B
+VE_LCDCRB:
+ .dw $ff06
+ .db "LCDCRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDCRB
+XT_LCDCRB:
+ .dw PFA_DOVARIABLE
+PFA_LCDCRB:
+ .dw 229
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Control and Status Register A
+VE_LCDCRA:
+ .dw $ff06
+ .db "LCDCRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDCRA
+XT_LCDCRA:
+ .dw PFA_DOVARIABLE
+PFA_LCDCRA:
+ .dw 228
+
+.endif
+.if WANT_CPU == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw 95
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer
+VE_SP:
+ .dw $ff02
+ .db "SP"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SP
+XT_SP:
+ .dw PFA_DOVARIABLE
+PFA_SP:
+ .dw 93
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Calibration Value
+VE_OSCCAL:
+ .dw $ff06
+ .db "OSCCAL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSCCAL
+XT_OSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_OSCCAL:
+ .dw 102
+; ( -- addr ) System Constant
+; R( -- )
+; Clock Prescale Register
+VE_CLKPR:
+ .dw $ff05
+ .db "CLKPR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKPR
+XT_CLKPR:
+ .dw PFA_DOVARIABLE
+PFA_CLKPR:
+ .dw 97
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register
+VE_PRR:
+ .dw $ff03
+ .db "PRR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR
+XT_PRR:
+ .dw PFA_DOVARIABLE
+PFA_PRR:
+ .dw 100
+; ( -- addr ) System Constant
+; R( -- )
+; Sleep Mode Control Register
+VE_SMCR:
+ .dw $ff04
+ .db "SMCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SMCR
+XT_SMCR:
+ .dw PFA_DOVARIABLE
+PFA_SMCR:
+ .dw 83
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 2
+VE_GPIOR2:
+ .dw $ff06
+ .db "GPIOR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR2
+XT_GPIOR2:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR2:
+ .dw 75
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 1
+VE_GPIOR1:
+ .dw $ff06
+ .db "GPIOR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR1
+XT_GPIOR1:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR1:
+ .dw 74
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 0
+VE_GPIOR0:
+ .dw $ff06
+ .db "GPIOR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR0
+XT_GPIOR0:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR0:
+ .dw 62
+
+.endif
diff --git a/amforth-6.5/avr8/devices/atmega3290p/device.py b/amforth-6.5/avr8/devices/atmega3290p/device.py
new file mode 100644
index 0000000..5ebd3d7
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega3290p/device.py
@@ -0,0 +1,378 @@
+# Generated Automatically
+
+# Partname ATmega3290P
+
+MCUREGS = {
+# Interrupt Vectors
+ 'INT0Addr' : '#2', # External Interrupt Request 0
+ 'PCINT0Addr' : '#4', # Pin Change Interrupt Request 0
+ 'PCINT1Addr' : '#6', # Pin Change Interrupt Request 1
+ 'TIMER2_COMPAddr' : '#8', # Timer/Counter2 Compare Match
+ 'TIMER2_OVFAddr' : '#10', # Timer/Counter2 Overflow
+ 'TIMER1_CAPTAddr' : '#12', # Timer/Counter1 Capture Event
+ 'TIMER1_COMPAAddr' : '#14', # Timer/Counter1 Compare Match A
+ 'TIMER1_COMPBAddr' : '#16', # Timer/Counter Compare Match B
+ 'TIMER1_OVFAddr' : '#18', # Timer/Counter1 Overflow
+ 'TIMER0_COMPAddr' : '#20', # Timer/Counter0 Compare Match
+ 'TIMER0_OVFAddr' : '#22', # Timer/Counter0 Overflow
+ 'SPI_STCAddr' : '#24', # SPI Serial Transfer Complete
+ 'USART_RXAddr' : '#26', # USART, Rx Complete
+ 'USART_UDREAddr' : '#28', # USART Data register Empty
+ 'USART0_TXAddr' : '#30', # USART0, Tx Complete
+ 'USI_STARTAddr' : '#32', # USI Start Condition
+ 'USI_OVERFLOWAddr' : '#34', # USI Overflow
+ 'ANALOG_COMPAddr' : '#36', # Analog Comparator
+ 'ADCAddr' : '#38', # ADC Conversion Complete
+ 'EE_READYAddr' : '#40', # EEPROM Ready
+ 'SPM_READYAddr' : '#42', # Store Program Memory Read
+ 'LCDAddr' : '#44', # LCD Start of Frame
+ 'PCINT2Addr' : '#46', # Pin Change Interrupt Request 2
+ 'PCINT3Addr' : '#48', # Pin Change Interrupt Request 3
+
+# Module TIMER_COUNTER_0
+ 'TCCR0A' : '$44', # Timer/Counter0 Control Registe
+ 'TCCR0A_FOC0A': '$80', # Force Output Compare
+ 'TCCR0A_WGM00': '$40', # Waveform Generation Mode 0
+ 'TCCR0A_COM0A': '$30', # Compare Match Output Modes
+ 'TCCR0A_WGM01': '$8', # Waveform Generation Mode 1
+ 'TCCR0A_CS0': '$7', # Clock Selects
+ 'TCNT0' : '$46', # Timer/Counter0
+ 'OCR0A' : '$47', # Timer/Counter0 Output Compare
+ 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
+ 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
+ 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
+ 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
+ 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
+ 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Control Register
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSR310': '$1', # Prescaler Reset Timer/Counter1
+
+# Module TIMER_COUNTER_1
+ 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
+ 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
+ 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
+ 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
+ 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
+ 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
+ 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
+ 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
+ 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
+ 'TCCR1C' : '$82', # Timer/Counter 1 Control Regist
+ 'TCCR1C_FOC1A': '$80', # Force Output Compare 1A
+ 'TCCR1C_FOC1B': '$40', # Force Output Compare 1B
+ 'TCNT1' : '$84', # Timer/Counter1 Bytes
+ 'OCR1A' : '$88', # Timer/Counter1 Output Compare
+ 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
+ 'ICR1' : '$86', # Timer/Counter1 Input Capture R
+ 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
+ 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
+ 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
+ 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
+ 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
+ 'TIFR1' : '$36', # Timer/Counter1 Interrupt Flag
+ 'TIFR1_ICF1': '$20', # Input Capture Flag 1
+ 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
+ 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
+ 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
+
+# Module TIMER_COUNTER_2
+ 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
+ 'TCCR2A_FOC2A': '$80', # Force Output Compare A
+ 'TCCR2A_WGM20': '$40', # Waveform Generation Mode
+ 'TCCR2A_COM2A': '$30', # Compare Output Mode bits
+ 'TCCR2A_WGM21': '$8', # Waveform Generation Mode
+ 'TCCR2A_CS2': '$7', # Clock Select bits
+ 'TCNT2' : '$b2', # Timer/Counter2
+ 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
+ 'TIMSK2' : '$70', # Timer/Counter2 Interrupt Mask
+ 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
+ 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
+ 'TIFR2' : '$37', # Timer/Counter2 Interrupt Flag
+ 'TIFR2_OCF2A': '$2', # Timer/Counter2 Output Compare
+ 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_PSR2': '$2', # Prescaler Reset Timer/Counter2
+ 'ASSR' : '$b6', # Asynchronous Status Register
+ 'ASSR_EXCLK': '$10', # Enable External Clock Interrup
+ 'ASSR_AS2': '$8', # AS2: Asynchronous Timer/Counte
+ 'ASSR_TCN2UB': '$4', # TCN2UB: Timer/Counter2 Update
+ 'ASSR_OCR2UB': '$2', # Output Compare Register2 Updat
+ 'ASSR_TCR2UB': '$1', # TCR2UB: Timer/Counter Control
+
+# Module WATCHDOG
+ 'WDTCR' : '$60', # Watchdog Timer Control Registe
+ 'WDTCR_WDCE': '$10', # Watchdog Change Enable
+ 'WDTCR_WDE': '$8', # Watch Dog Enable
+ 'WDTCR_WDP': '$7', # Watch Dog Timer Prescaler bits
+
+# Module EEPROM
+ 'EEAR' : '$41', # EEPROM Read/Write Access Byte
+ 'EEDR' : '$40', # EEPROM Data Register
+ 'EECR' : '$3f', # EEPROM Control Register
+ 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
+ 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
+ 'EECR_EEWE': '$2', # EEPROM Write Enable
+ 'EECR_EERE': '$1', # EEPROM Read Enable
+
+# Module SPI
+ 'SPCR' : '$4c', # SPI Control Register
+ 'SPCR_SPIE': '$80', # SPI Interrupt Enable
+ 'SPCR_SPE': '$40', # SPI Enable
+ 'SPCR_DORD': '$20', # Data Order
+ 'SPCR_MSTR': '$10', # Master/Slave Select
+ 'SPCR_CPOL': '$8', # Clock polarity
+ 'SPCR_CPHA': '$4', # Clock Phase
+ 'SPCR_SPR': '$3', # SPI Clock Rate Selects
+ 'SPSR' : '$4d', # SPI Status Register
+ 'SPSR_SPIF': '$80', # SPI Interrupt Flag
+ 'SPSR_WCOL': '$40', # Write Collision Flag
+ 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
+ 'SPDR' : '$4e', # SPI Data Register
+
+# Module PORTA
+ 'PORTA' : '$22', # Port A Data Register
+ 'DDRA' : '$21', # Port A Data Direction Register
+ 'PINA' : '$20', # Port A Input Pins
+
+# Module PORTB
+ 'PORTB' : '$25', # Port B Data Register
+ 'DDRB' : '$24', # Port B Data Direction Register
+ 'PINB' : '$23', # Port B Input Pins
+
+# Module PORTC
+ 'PORTC' : '$28', # Port C Data Register
+ 'DDRC' : '$27', # Port C Data Direction Register
+ 'PINC' : '$26', # Port C Input Pins
+
+# Module PORTD
+ 'PORTD' : '$2b', # Port D Data Register
+ 'DDRD' : '$2a', # Port D Data Direction Register
+ 'PIND' : '$29', # Port D Input Pins
+
+# Module ANALOG_COMPARATOR
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
+ 'ACSR' : '$50', # Analog Comparator Control And
+ 'ACSR_ACD': '$80', # Analog Comparator Disable
+ 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
+ 'ACSR_ACO': '$20', # Analog Compare Output
+ 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
+ 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
+ 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
+ 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
+ 'DIDR1' : '$7f', # Digital Input Disable Register
+ 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
+ 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
+
+# Module PORTE
+ 'PORTE' : '$2e', # Data Register, Port E
+ 'DDRE' : '$2d', # Data Direction Register, Port
+ 'PINE' : '$2c', # Input Pins, Port E
+
+# Module PORTF
+ 'PORTF' : '$31', # Data Register, Port F
+ 'DDRF' : '$30', # Data Direction Register, Port
+ 'PINF' : '$2f', # Input Pins, Port F
+
+# Module PORTG
+ 'PORTG' : '$34', # Port G Data Register
+ 'DDRG' : '$33', # Port G Data Direction Register
+ 'PING' : '$32', # Port G Input Pins
+
+# Module JTAG
+ 'OCDR' : '$51', # On-Chip Debug Related Register
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_JTD': '$80', # JTAG Interface Disable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+
+# Module EXTERNAL_INTERRUPT
+ 'EICRA' : '$69', # External Interrupt Control Reg
+ 'EICRA_ISC01': '$2', # External Interrupt Sense Contr
+ 'EICRA_ISC00': '$1', # External Interrupt Sense Contr
+ 'EIMSK' : '$3d', # External Interrupt Mask Regist
+ 'EIMSK_PCIE': '$f0', # Pin Change Interrupt Enables
+ 'EIMSK_INT0': '$1', # External Interrupt Request 0 E
+ 'EIFR' : '$3c', # External Interrupt Flag Regist
+ 'EIFR_PCIF': '$f0', # Pin Change Interrupt Flags
+ 'EIFR_INTF0': '$1', # External Interrupt Flag 0
+ 'PCMSK3' : '$73', # Pin Change Mask Register 3
+ 'PCMSK2' : '$6d', # Pin Change Mask Register 2
+ 'PCMSK1' : '$6c', # Pin Change Mask Register 1
+ 'PCMSK0' : '$6b', # Pin Change Mask Register 0
+
+# Module USI
+ 'USIDR' : '$ba', # USI Data Register
+ 'USISR' : '$b9', # USI Status Register
+ 'USISR_USISIF': '$80', # Start Condition Interrupt Flag
+ 'USISR_USIOIF': '$40', # Counter Overflow Interrupt Fla
+ 'USISR_USIPF': '$20', # Stop Condition Flag
+ 'USISR_USIDC': '$10', # Data Output Collision
+ 'USISR_USICNT': '$f', # USI Counter Value Bits
+ 'USICR' : '$b8', # USI Control Register
+ 'USICR_USISIE': '$80', # Start Condition Interrupt Enab
+ 'USICR_USIOIE': '$40', # Counter Overflow Interrupt Ena
+ 'USICR_USIWM': '$30', # USI Wire Mode Bits
+ 'USICR_USICS': '$c', # USI Clock Source Select Bits
+ 'USICR_USICLK': '$2', # Clock Strobe
+ 'USICR_USITC': '$1', # Toggle Clock Port Pin
+
+# Module AD_CONVERTER
+ 'ADMUX' : '$7c', # The ADC multiplexer Selection
+ 'ADMUX_REFS': '$c0', # Reference Selection Bits
+ 'ADMUX_ADLAR': '$20', # Left Adjust Result
+ 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
+ 'ADCSRA' : '$7a', # The ADC Control and Status reg
+ 'ADCSRA_ADEN': '$80', # ADC Enable
+ 'ADCSRA_ADSC': '$40', # ADC Start Conversion
+ 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
+ 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
+ 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
+ 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
+ 'ADC' : '$78', # ADC Data Register Bytes
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Sources
+ 'DIDR0' : '$7e', # Digital Input Disable Register
+ 'DIDR0_ADC7D': '$80', # ADC7 Digital input Disable
+ 'DIDR0_ADC6D': '$40', # ADC6 Digital input Disable
+ 'DIDR0_ADC5D': '$20', # ADC5 Digital input Disable
+ 'DIDR0_ADC4D': '$10', # ADC4 Digital input Disable
+ 'DIDR0_ADC3D': '$8', # ADC3 Digital input Disable
+ 'DIDR0_ADC2D': '$4', # ADC2 Digital input Disable
+ 'DIDR0_ADC1D': '$2', # ADC1 Digital input Disable
+ 'DIDR0_ADC0D': '$1', # ADC0 Digital input Disable
+
+# Module BOOT_LOAD
+ 'SPMCSR' : '$57', # Store Program Memory Control R
+ 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
+ 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
+ 'SPMCSR_RWWSRE': '$10', # Read While Write section read
+ 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
+ 'SPMCSR_PGWRT': '$4', # Page Write
+ 'SPMCSR_PGERS': '$2', # Page Erase
+ 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
+
+# Module USART0
+ 'UDR0' : '$c6', # USART I/O Data Register
+ 'UCSR0A' : '$c0', # USART Control and Status Regis
+ 'UCSR0A_RXC0': '$80', # USART Receive Complete
+ 'UCSR0A_TXC0': '$40', # USART Transmit Complete
+ 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
+ 'UCSR0A_FE0': '$10', # Framing Error
+ 'UCSR0A_DOR0': '$8', # Data OverRun
+ 'UCSR0A_UPE0': '$4', # USART Parity Error
+ 'UCSR0A_U2X0': '$2', # Double the USART Transmission
+ 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
+ 'UCSR0B' : '$c1', # USART Control and Status Regis
+ 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
+ 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
+ 'UCSR0B_UDRIE0': '$20', # USART Data Register Empty Inte
+ 'UCSR0B_RXEN0': '$10', # Receiver Enable
+ 'UCSR0B_TXEN0': '$8', # Transmitter Enable
+ 'UCSR0B_UCSZ02': '$4', # Character Size
+ 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
+ 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
+ 'UCSR0C' : '$c2', # USART Control and Status Regis
+ 'UCSR0C_UMSEL0': '$40', # USART Mode Select
+ 'UCSR0C_UPM0': '$30', # Parity Mode Bits
+ 'UCSR0C_USBS0': '$8', # Stop Bit Select
+ 'UCSR0C_UCSZ0': '$6', # Character Size
+ 'UCSR0C_UCPOL0': '$1', # Clock Polarity
+ 'UBRR0' : '$c4', # USART Baud Rate Register Byte
+
+# Module PORTH
+ 'PORTH' : '$da', # PORT H Data Register
+ 'DDRH' : '$d9', # PORT H Data Direction Register
+ 'PINH' : '$d8', # PORT H Input Pins
+
+# Module PORTJ
+ 'PORTJ' : '$dd', # PORT J Data Register
+ 'DDRJ' : '$dc', # PORT J Data Direction Register
+ 'PINJ' : '$db', # PORT J Input Pins
+
+# Module LCD
+ 'LCDDR19' : '$ff', # LCD Data Register 19
+ 'LCDDR18' : '$fe', # LCD Data Register 18
+ 'LCDDR17' : '$fd', # LCD Data Register 17
+ 'LCDDR16' : '$fc', # LCD Data Register 16
+ 'LCDDR15' : '$fb', # LCD Data Register 15
+ 'LCDDR14' : '$fa', # LCD Data Register 14
+ 'LCDDR13' : '$f9', # LCD Data Register 13
+ 'LCDDR12' : '$f8', # LCD Data Register 12
+ 'LCDDR11' : '$f7', # LCD Data Register 11
+ 'LCDDR10' : '$f6', # LCD Data Register 10
+ 'LCDDR9' : '$f5', # LCD Data Register 9
+ 'LCDDR8' : '$f4', # LCD Data Register 8
+ 'LCDDR7' : '$f3', # LCD Data Register 7
+ 'LCDDR6' : '$f2', # LCD Data Register 6
+ 'LCDDR5' : '$f1', # LCD Data Register 5
+ 'LCDDR4' : '$f0', # LCD Data Register 4
+ 'LCDDR3' : '$ef', # LCD Data Register 3
+ 'LCDDR2' : '$ee', # LCD Data Register 2
+ 'LCDDR1' : '$ed', # LCD Data Register 1
+ 'LCDDR0' : '$ec', # LCD Data Register 0
+ 'LCDCCR' : '$e7', # LCD Contrast Control Register
+ 'LCDCCR_LCDDC': '$e0', # LCD Display Configurations
+ 'LCDCCR_LCDMDT': '$10', # LCD Maximum Drive Time
+ 'LCDCCR_LCDCC': '$f', # LCD Contrast Controls
+ 'LCDFRR' : '$e6', # LCD Frame Rate Register
+ 'LCDFRR_LCDPS': '$70', # LCD Prescaler Selects
+ 'LCDFRR_LCDCD': '$7', # LCD Clock Dividers
+ 'LCDCRB' : '$e5', # LCD Control and Status Registe
+ 'LCDCRB_LCDCS': '$80', # LCD CLock Select
+ 'LCDCRB_LCD2B': '$40', # LCD 1/2 Bias Select
+ 'LCDCRB_LCDMUX': '$30', # LCD Mux Selects
+ 'LCDCRB_LCDPM': '$f', # LCD Port Masks
+ 'LCDCRA' : '$e4', # LCD Control and Status Registe
+ 'LCDCRA_LCDEN': '$80', # LCD Enable
+ 'LCDCRA_LCDAB': '$40', # LCD A or B waveform
+ 'LCDCRA_LCDIF': '$10', # LCD Interrupt Flag
+ 'LCDCRA_LCDIE': '$8', # LCD Interrupt Enable
+ 'LCDCRA_LCDBD': '$4', # LCD Buffer Disable
+ 'LCDCRA_LCDCCD': '$2', # LCD Contrast Control Disable
+ 'LCDCRA_LCDBL': '$1', # LCD Blanking
+
+# Module CPU
+ 'SREG' : '$5f', # Status Register
+ 'SREG_I': '$80', # Global Interrupt Enable
+ 'SREG_T': '$40', # Bit Copy Storage
+ 'SREG_H': '$20', # Half Carry Flag
+ 'SREG_S': '$10', # Sign Bit
+ 'SREG_V': '$8', # Two's Complement Overflow Flag
+ 'SREG_N': '$4', # Negative Flag
+ 'SREG_Z': '$2', # Zero Flag
+ 'SREG_C': '$1', # Carry Flag
+ 'SP' : '$5d', # Stack Pointer
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_JTD': '$80', # JTAG Interface Disable
+ 'MCUCR_BODS': '$40', # BOD Sleep
+ 'MCUCR_BODSE': '$20', # BOD Sleep Enable
+ 'MCUCR_PUD': '$10', # Pull-up disable
+ 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
+ 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+ 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
+ 'MCUSR_BORF': '$4', # Brown-out Reset Flag
+ 'MCUSR_EXTRF': '$2', # External Reset Flag
+ 'MCUSR_PORF': '$1', # Power-on reset flag
+ 'OSCCAL' : '$66', # Oscillator Calibration Value
+ 'CLKPR' : '$61', # Clock Prescale Register
+ 'CLKPR_CLKPCE': '$80', # Clock Prescaler Change Enable
+ 'CLKPR_CLKPS': '$f', # Clock Prescaler Select Bits
+ 'PRR' : '$64', # Power Reduction Register
+ 'PRR_PRLCD': '$10', # Power Reduction LCD
+ 'PRR_PRTIM1': '$8', # Power Reduction Timer/Counter1
+ 'PRR_PRSPI': '$4', # Power Reduction Serial Periphe
+ 'PRR_PRUSART0': '$2', # Power Reduction USART
+ 'PRR_PRADC': '$1', # Power Reduction ADC
+ 'SMCR' : '$53', # Sleep Mode Control Register
+ 'SMCR_SM': '$e', # Sleep Mode Select bits
+ 'SMCR_SE': '$1', # Sleep Enable
+ 'GPIOR2' : '$4b', # General Purpose IO Register 2
+ 'GPIOR1' : '$4a', # General Purpose IO Register 1
+ 'GPIOR0' : '$3e', # General Purpose IO Register 0
+
+ '__amforth_dummy':'0'
+}
diff --git a/amforth-6.5/avr8/devices/atmega3290p/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega3290p/words/no-jtag.asm
new file mode 100644
index 0000000..352a4bb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega3290p/words/no-jtag.asm
@@ -0,0 +1,14 @@
+; ( -- )
+; ( -- )
+; MCU
+; disable jtag at runtime
+VE_NOJTAG:
+ .dw $FF05
+ .db "-jtag",0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOJTAG
+XT_NOJTAG:
+ .dw PFA_NOJTAG
+PFA_NOJTAG:
+
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega3290p/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega3290p/words/no-wdt.asm
new file mode 100644
index 0000000..4a12261
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega3290p/words/no-wdt.asm
@@ -0,0 +1,22 @@
+; ( -- )
+; MCU
+; disable watch dog timer at runtime
+VE_NOWDT:
+ .dw $ff04
+ .db "-wdt"
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOWDT
+XT_NOWDT:
+ .dw PFA_NOWDT
+PFA_NOWDT:
+
+; Reset WDT
+ wdr
+; Write logical one to WDTOE and WDE
+ in_ temp1, WDTCR
+ ori temp1, (1<<WDTOE)|(1<<WDE)
+ out WDTCR, temp1
+; Turn off WDT
+ ldi temp1, (0<<WDE)
+ out_ WDTCR, temp1
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega3290p/words/sleep.asm b/amforth-6.5/avr8/devices/atmega3290p/words/sleep.asm
new file mode 100644
index 0000000..256249c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega3290p/words/sleep.asm
@@ -0,0 +1,19 @@
+; ( mode -- )
+; MCU
+; put the controller into the specified sleep mode
+VE_SLEEP:
+ .dw $ff05
+ .db "sleep", 0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_SLEEP
+XT_SLEEP:
+ .dw PFA_SLEEP
+PFA_SLEEP:
+ andi tosl, 7 ; leave only legal mode bits
+ lsl tosl ; move to correct location (bits 3-1)
+ ori tosl, 1 ; set the SE bit
+ out_ SMCR, tosl ; set the sleep config
+ sleep ; nighty-night
+ out_ SMCR, zerol ; 0 protects against accidental sleeps
+ loadtos ; pop argument from stack
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega3290pa/atmega3290pa.frt b/amforth-6.5/avr8/devices/atmega3290pa/atmega3290pa.frt
new file mode 100644
index 0000000..add7cf2
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega3290pa/atmega3290pa.frt
@@ -0,0 +1,333 @@
+\ Partname: ATmega3290PA
+\ generated automatically
+
+\ TIMER_COUNTER_0
+&68 constant TCCR0A \ Timer/Counter0 Control Register
+ $80 constant TCCR0A_FOC0A \ Force Output Compare
+ $40 constant TCCR0A_WGM00 \ Waveform Generation Mode 0
+ $30 constant TCCR0A_COM0A \ Compare Match Output Modes
+ $08 constant TCCR0A_WGM01 \ Waveform Generation Mode 1
+ $07 constant TCCR0A_CS0 \ Clock Selects
+&70 constant TCNT0 \ Timer/Counter0
+&71 constant OCR0A \ Timer/Counter0 Output Compare Register
+&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
+ $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match Interrupt Enable
+ $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
+&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
+ $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0
+ $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
+&67 constant GTCCR \ General Timer/Control Register
+ $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
+ $01 constant GTCCR_PSR310 \ Prescaler Reset Timer/Counter1 and Timer/Counter0
+\ TIMER_COUNTER_1
+&128 constant TCCR1A \ Timer/Counter1 Control Register A
+ $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
+ $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
+ $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
+&129 constant TCCR1B \ Timer/Counter1 Control Register B
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
+ $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
+&130 constant TCCR1C \ Timer/Counter 1 Control Register C
+ $80 constant TCCR1C_FOC1A \ Force Output Compare 1A
+ $40 constant TCCR1C_FOC1B \ Force Output Compare 1B
+&132 constant TCNT1 \ Timer/Counter1 Bytes
+&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
+&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
+&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
+&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
+ $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
+ $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
+ $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
+ $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
+&54 constant TIFR1 \ Timer/Counter1 Interrupt Flag register
+ $20 constant TIFR1_ICF1 \ Input Capture Flag 1
+ $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
+ $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
+ $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
+\ TIMER_COUNTER_2
+&176 constant TCCR2A \ Timer/Counter2 Control Register
+ $80 constant TCCR2A_FOC2A \ Force Output Compare A
+ $40 constant TCCR2A_WGM20 \ Waveform Generation Mode
+ $30 constant TCCR2A_COM2A \ Compare Output Mode bits
+ $08 constant TCCR2A_WGM21 \ Waveform Generation Mode
+ $07 constant TCCR2A_CS2 \ Clock Select bits
+&178 constant TCNT2 \ Timer/Counter2
+&179 constant OCR2A \ Timer/Counter2 Output Compare Register
+&112 constant TIMSK2 \ Timer/Counter2 Interrupt Mask register
+ $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match Interrupt Enable
+ $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
+&55 constant TIFR2 \ Timer/Counter2 Interrupt Flag Register
+ $02 constant TIFR2_OCF2A \ Timer/Counter2 Output Compare Flag 2
+ $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
+&182 constant ASSR \ Asynchronous Status Register
+ $10 constant ASSR_EXCLK \ Enable External Clock Interrupt
+ $08 constant ASSR_AS2 \ AS2: Asynchronous Timer/Counter2
+ $04 constant ASSR_TCN2UB \ TCN2UB: Timer/Counter2 Update Busy
+ $02 constant ASSR_OCR2UB \ Output Compare Register2 Update Busy
+ $01 constant ASSR_TCR2UB \ TCR2UB: Timer/Counter Control Register2 Update Busy
+\ WATCHDOG
+&96 constant WDTCR \ Watchdog Timer Control Register
+ $10 constant WDTCR_WDCE \ Watchdog Change Enable
+ $08 constant WDTCR_WDE \ Watch Dog Enable
+ $07 constant WDTCR_WDP \ Watch Dog Timer Prescaler bits
+\ EEPROM
+&65 constant EEAR \ EEPROM Read/Write Access Bytes
+&64 constant EEDR \ EEPROM Data Register
+&63 constant EECR \ EEPROM Control Register
+ $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
+ $04 constant EECR_EEMWE \ EEPROM Master Write Enable
+ $02 constant EECR_EEWE \ EEPROM Write Enable
+ $01 constant EECR_EERE \ EEPROM Read Enable
+\ SPI
+&76 constant SPCR \ SPI Control Register
+ $80 constant SPCR_SPIE \ SPI Interrupt Enable
+ $40 constant SPCR_SPE \ SPI Enable
+ $20 constant SPCR_DORD \ Data Order
+ $10 constant SPCR_MSTR \ Master/Slave Select
+ $08 constant SPCR_CPOL \ Clock polarity
+ $04 constant SPCR_CPHA \ Clock Phase
+ $03 constant SPCR_SPR \ SPI Clock Rate Selects
+&77 constant SPSR \ SPI Status Register
+ $80 constant SPSR_SPIF \ SPI Interrupt Flag
+ $40 constant SPSR_WCOL \ Write Collision Flag
+ $01 constant SPSR_SPI2X \ Double SPI Speed Bit
+&78 constant SPDR \ SPI Data Register
+\ PORTA
+&34 constant PORTA \ Port A Data Register
+&33 constant DDRA \ Port A Data Direction Register
+&32 constant PINA \ Port A Input Pins
+\ PORTB
+&37 constant PORTB \ Port B Data Register
+&36 constant DDRB \ Port B Data Direction Register
+&35 constant PINB \ Port B Input Pins
+\ PORTC
+&40 constant PORTC \ Port C Data Register
+&39 constant DDRC \ Port C Data Direction Register
+&38 constant PINC \ Port C Input Pins
+\ PORTD
+&43 constant PORTD \ Port D Data Register
+&42 constant DDRD \ Port D Data Direction Register
+&41 constant PIND \ Port D Input Pins
+\ ANALOG_COMPARATOR
+&123 constant ADCSRB \ ADC Control and Status Register B
+ $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer Enable
+&80 constant ACSR \ Analog Comparator Control And Status Register
+ $80 constant ACSR_ACD \ Analog Comparator Disable
+ $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
+ $20 constant ACSR_ACO \ Analog Compare Output
+ $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
+ $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
+ $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
+ $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
+&127 constant DIDR1 \ Digital Input Disable Register 1
+ $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
+ $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
+\ PORTE
+&46 constant PORTE \ Data Register, Port E
+&45 constant DDRE \ Data Direction Register, Port E
+&44 constant PINE \ Input Pins, Port E
+\ PORTF
+&49 constant PORTF \ Data Register, Port F
+&48 constant DDRF \ Data Direction Register, Port F
+&47 constant PINF \ Input Pins, Port F
+\ PORTG
+&52 constant PORTG \ Port G Data Register
+&51 constant DDRG \ Port G Data Direction Register
+&50 constant PING \ Port G Input Pins
+\ JTAG
+&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
+&85 constant MCUCR \ MCU Control Register
+ $80 constant MCUCR_JTD \ JTAG Interface Disable
+&84 constant MCUSR \ MCU Status Register
+ $10 constant MCUSR_JTRF \ JTAG Reset Flag
+\ EXTERNAL_INTERRUPT
+&105 constant EICRA \ External Interrupt Control Register A
+ $02 constant EICRA_ISC01 \ External Interrupt Sense Control 0 Bit 1
+ $01 constant EICRA_ISC00 \ External Interrupt Sense Control 0 Bit 0
+&61 constant EIMSK \ External Interrupt Mask Register
+ $F0 constant EIMSK_PCIE \ Pin Change Interrupt Enables
+ $01 constant EIMSK_INT0 \ External Interrupt Request 0 Enable
+&60 constant EIFR \ External Interrupt Flag Register
+ $F0 constant EIFR_PCIF \ Pin Change Interrupt Flags
+ $01 constant EIFR_INTF0 \ External Interrupt Flag 0
+&115 constant PCMSK3 \ Pin Change Mask Register 3
+&109 constant PCMSK2 \ Pin Change Mask Register 2
+&108 constant PCMSK1 \ Pin Change Mask Register 1
+&107 constant PCMSK0 \ Pin Change Mask Register 0
+\ USI
+&186 constant USIDR \ USI Data Register
+&185 constant USISR \ USI Status Register
+ $80 constant USISR_USISIF \ Start Condition Interrupt Flag
+ $40 constant USISR_USIOIF \ Counter Overflow Interrupt Flag
+ $20 constant USISR_USIPF \ Stop Condition Flag
+ $10 constant USISR_USIDC \ Data Output Collision
+ $0F constant USISR_USICNT \ USI Counter Value Bits
+&184 constant USICR \ USI Control Register
+ $80 constant USICR_USISIE \ Start Condition Interrupt Enable
+ $40 constant USICR_USIOIE \ Counter Overflow Interrupt Enable
+ $30 constant USICR_USIWM \ USI Wire Mode Bits
+ $0C constant USICR_USICS \ USI Clock Source Select Bits
+ $02 constant USICR_USICLK \ Clock Strobe
+ $01 constant USICR_USITC \ Toggle Clock Port Pin
+\ AD_CONVERTER
+&124 constant ADMUX \ The ADC multiplexer Selection Register
+ $C0 constant ADMUX_REFS \ Reference Selection Bits
+ $20 constant ADMUX_ADLAR \ Left Adjust Result
+ $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
+&122 constant ADCSRA \ The ADC Control and Status register
+ $80 constant ADCSRA_ADEN \ ADC Enable
+ $40 constant ADCSRA_ADSC \ ADC Start Conversion
+ $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
+ $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
+ $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
+ $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
+&120 constant ADC \ ADC Data Register Bytes
+&126 constant DIDR0 \ Digital Input Disable Register 0
+ $80 constant DIDR0_ADC7D \ ADC7 Digital input Disable
+ $40 constant DIDR0_ADC6D \ ADC6 Digital input Disable
+ $20 constant DIDR0_ADC5D \ ADC5 Digital input Disable
+ $10 constant DIDR0_ADC4D \ ADC4 Digital input Disable
+ $08 constant DIDR0_ADC3D \ ADC3 Digital input Disable
+ $04 constant DIDR0_ADC2D \ ADC2 Digital input Disable
+ $02 constant DIDR0_ADC1D \ ADC1 Digital input Disable
+ $01 constant DIDR0_ADC0D \ ADC0 Digital input Disable
+\ BOOT_LOAD
+&87 constant SPMCSR \ Store Program Memory Control Register
+ $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
+ $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
+ $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
+ $04 constant SPMCSR_PGWRT \ Page Write
+ $02 constant SPMCSR_PGERS \ Page Erase
+ $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
+\ USART0
+&198 constant UDR0 \ USART I/O Data Register
+&192 constant UCSR0A \ USART Control and Status Register A
+ $80 constant UCSR0A_RXC0 \ USART Receive Complete
+ $40 constant UCSR0A_TXC0 \ USART Transmit Complete
+ $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
+ $10 constant UCSR0A_FE0 \ Framing Error
+ $08 constant UCSR0A_DOR0 \ Data OverRun
+ $04 constant UCSR0A_UPE0 \ USART Parity Error
+ $02 constant UCSR0A_U2X0 \ Double the USART Transmission Speed
+ $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
+&193 constant UCSR0B \ USART Control and Status Register B
+ $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
+ $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
+ $20 constant UCSR0B_UDRIE0 \ USART Data Register Empty Interrupt Enable
+ $10 constant UCSR0B_RXEN0 \ Receiver Enable
+ $08 constant UCSR0B_TXEN0 \ Transmitter Enable
+ $04 constant UCSR0B_UCSZ02 \ Character Size
+ $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
+ $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
+&194 constant UCSR0C \ USART Control and Status Register C
+ $40 constant UCSR0C_UMSEL0 \ USART Mode Select
+ $30 constant UCSR0C_UPM0 \ Parity Mode Bits
+ $08 constant UCSR0C_USBS0 \ Stop Bit Select
+ $06 constant UCSR0C_UCSZ0 \ Character Size
+ $01 constant UCSR0C_UCPOL0 \ Clock Polarity
+&196 constant UBRR0 \ USART Baud Rate Register Bytes
+\ PORTH
+&218 constant PORTH \ PORT H Data Register
+&217 constant DDRH \ PORT H Data Direction Register
+&216 constant PINH \ PORT H Input Pins
+\ PORTJ
+&221 constant PORTJ \ PORT J Data Register
+&220 constant DDRJ \ PORT J Data Direction Register
+&219 constant PINJ \ PORT J Input Pins
+\ LCD
+&255 constant LCDDR19 \ LCD Data Register 19
+&254 constant LCDDR18 \ LCD Data Register 18
+&253 constant LCDDR17 \ LCD Data Register 17
+&252 constant LCDDR16 \ LCD Data Register 16
+&251 constant LCDDR15 \ LCD Data Register 15
+&250 constant LCDDR14 \ LCD Data Register 14
+&249 constant LCDDR13 \ LCD Data Register 13
+&248 constant LCDDR12 \ LCD Data Register 12
+&247 constant LCDDR11 \ LCD Data Register 11
+&246 constant LCDDR10 \ LCD Data Register 10
+&245 constant LCDDR9 \ LCD Data Register 9
+&244 constant LCDDR8 \ LCD Data Register 8
+&243 constant LCDDR7 \ LCD Data Register 7
+&242 constant LCDDR6 \ LCD Data Register 6
+&241 constant LCDDR5 \ LCD Data Register 5
+&240 constant LCDDR4 \ LCD Data Register 4
+&239 constant LCDDR3 \ LCD Data Register 3
+&238 constant LCDDR2 \ LCD Data Register 2
+&237 constant LCDDR1 \ LCD Data Register 1
+&236 constant LCDDR0 \ LCD Data Register 0
+&231 constant LCDCCR \ LCD Contrast Control Register
+ $E0 constant LCDCCR_LCDDC \ LCD Display Configurations
+ $10 constant LCDCCR_LCDMDT \ LCD Maximum Drive Time
+ $0F constant LCDCCR_LCDCC \ LCD Contrast Controls
+&230 constant LCDFRR \ LCD Frame Rate Register
+ $70 constant LCDFRR_LCDPS \ LCD Prescaler Selects
+ $07 constant LCDFRR_LCDCD \ LCD Clock Dividers
+&229 constant LCDCRB \ LCD Control and Status Register B
+ $80 constant LCDCRB_LCDCS \ LCD CLock Select
+ $40 constant LCDCRB_LCD2B \ LCD 1/2 Bias Select
+ $30 constant LCDCRB_LCDMUX \ LCD Mux Selects
+ $0F constant LCDCRB_LCDPM \ LCD Port Masks
+&228 constant LCDCRA \ LCD Control and Status Register A
+ $80 constant LCDCRA_LCDEN \ LCD Enable
+ $40 constant LCDCRA_LCDAB \ LCD A or B waveform
+ $10 constant LCDCRA_LCDIF \ LCD Interrupt Flag
+ $08 constant LCDCRA_LCDIE \ LCD Interrupt Enable
+ $04 constant LCDCRA_LCDBD \ LCD Buffer Disable
+ $02 constant LCDCRA_LCDCCD \ LCD Contrast Control Disable
+ $01 constant LCDCRA_LCDBL \ LCD Blanking
+\ CPU
+&95 constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ $08 constant SREG_V \ Two's Complement Overflow Flag
+ $04 constant SREG_N \ Negative Flag
+ $02 constant SREG_Z \ Zero Flag
+ $01 constant SREG_C \ Carry Flag
+&93 constant SP \ Stack Pointer
+&102 constant OSCCAL \ Oscillator Calibration Value
+&97 constant CLKPR \ Clock Prescale Register
+ $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable
+ $0F constant CLKPR_CLKPS \ Clock Prescaler Select Bits
+&100 constant PRR \ Power Reduction Register
+ $10 constant PRR_PRLCD \ Power Reduction LCD
+ $08 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
+ $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
+ $02 constant PRR_PRUSART0 \ Power Reduction USART
+ $01 constant PRR_PRADC \ Power Reduction ADC
+&83 constant SMCR \ Sleep Mode Control Register
+ $0E constant SMCR_SM \ Sleep Mode Select bits
+ $01 constant SMCR_SE \ Sleep Enable
+&75 constant GPIOR2 \ General Purpose IO Register 2
+&74 constant GPIOR1 \ General Purpose IO Register 1
+&62 constant GPIOR0 \ General Purpose IO Register 0
+
+\ Interrupts
+&2 constant INT0Addr \ External Interrupt Request 0
+&4 constant PCINT0Addr \ Pin Change Interrupt Request 0
+&6 constant PCINT1Addr \ Pin Change Interrupt Request 1
+&8 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
+&10 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
+&12 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+&14 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
+&16 constant TIMER1_COMPBAddr \ Timer/Counter Compare Match B
+&18 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+&20 constant TIMER0_COMPAddr \ Timer/Counter0 Compare Match
+&22 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
+&24 constant SPI__STCAddr \ SPI Serial Transfer Complete
+&26 constant USART__RXAddr \ USART, Rx Complete
+&28 constant USART__UDREAddr \ USART Data register Empty
+&30 constant USART0__TXAddr \ USART0, Tx Complete
+&32 constant USI_STARTAddr \ USI Start Condition
+&34 constant USI_OVERFLOWAddr \ USI Overflow
+&36 constant ANALOG_COMPAddr \ Analog Comparator
+&38 constant ADCAddr \ ADC Conversion Complete
+&40 constant EE_READYAddr \ EEPROM Ready
+&42 constant SPM_READYAddr \ Store Program Memory Read
+&44 constant LCDAddr \ LCD Start of Frame
+&46 constant PCINT2Addr \ Pin Change Interrupt Request 2
+&48 constant PCINT3Addr \ Pin Change Interrupt Request 3
diff --git a/amforth-6.5/avr8/devices/atmega3290pa/device.asm b/amforth-6.5/avr8/devices/atmega3290pa/device.asm
new file mode 100644
index 0000000..06ae50e
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega3290pa/device.asm
@@ -0,0 +1,115 @@
+; Partname: ATmega3290PA
+; generated automatically, do not edit
+
+.nolist
+ .include "m3290PAdef.inc"
+.list
+
+.equ ramstart = 256
+.equ CELLSIZE = 2
+.macro readflashcell
+ lsl zl
+ rol zh
+ lpm @0, Z+
+ lpm @1, Z+
+.endmacro
+.macro writeflashcell
+ lsl zl
+ rol zh
+.endmacro
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_TIMER_COUNTER_2 = 0
+.set WANT_WATCHDOG = 0
+.set WANT_EEPROM = 0
+.set WANT_SPI = 0
+.set WANT_PORTA = 0
+.set WANT_PORTB = 0
+.set WANT_PORTC = 0
+.set WANT_PORTD = 0
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_PORTE = 0
+.set WANT_PORTF = 0
+.set WANT_PORTG = 0
+.set WANT_JTAG = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_USI = 0
+.set WANT_AD_CONVERTER = 0
+.set WANT_BOOT_LOAD = 0
+.set WANT_USART0 = 0
+.set WANT_PORTH = 0
+.set WANT_PORTJ = 0
+.set WANT_LCD = 0
+.set WANT_CPU = 0
+.equ intvecsize = 2 ; please verify; flash size: 32768 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.org 2
+ rcall isr ; External Interrupt Request 0
+.org 4
+ rcall isr ; Pin Change Interrupt Request 0
+.org 6
+ rcall isr ; Pin Change Interrupt Request 1
+.org 8
+ rcall isr ; Timer/Counter2 Compare Match
+.org 10
+ rcall isr ; Timer/Counter2 Overflow
+.org 12
+ rcall isr ; Timer/Counter1 Capture Event
+.org 14
+ rcall isr ; Timer/Counter1 Compare Match A
+.org 16
+ rcall isr ; Timer/Counter Compare Match B
+.org 18
+ rcall isr ; Timer/Counter1 Overflow
+.org 20
+ rcall isr ; Timer/Counter0 Compare Match
+.org 22
+ rcall isr ; Timer/Counter0 Overflow
+.org 24
+ rcall isr ; SPI Serial Transfer Complete
+.org 26
+ rcall isr ; USART, Rx Complete
+.org 28
+ rcall isr ; USART Data register Empty
+.org 30
+ rcall isr ; USART0, Tx Complete
+.org 32
+ rcall isr ; USI Start Condition
+.org 34
+ rcall isr ; USI Overflow
+.org 36
+ rcall isr ; Analog Comparator
+.org 38
+ rcall isr ; ADC Conversion Complete
+.org 40
+ rcall isr ; EEPROM Ready
+.org 42
+ rcall isr ; Store Program Memory Read
+.org 44
+ rcall isr ; LCD Start of Frame
+.org 46
+ rcall isr ; Pin Change Interrupt Request 2
+.org 48
+ rcall isr ; Pin Change Interrupt Request 3
+.equ INTVECTORS = 25
+.nooverlap
+
+; compatability layer (maybe empty)
+.equ EEPE = EEWE
+.equ EEMPE = EEMWE
+
+; controller data area, environment query mcu-info
+mcu_info:
+mcu_ramsize:
+ .dw 2048
+mcu_eepromsize:
+ .dw 1024
+mcu_maxdp:
+ .dw 28672
+mcu_numints:
+ .dw 25
+mcu_name:
+ .dw 12
+ .db "ATmega3290PA"
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega3290pa/device.inc b/amforth-6.5/avr8/devices/atmega3290pa/device.inc
new file mode 100644
index 0000000..3d403da
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega3290pa/device.inc
@@ -0,0 +1,1443 @@
+; Partname: ATmega3290PA
+; generated automatically, no not edit
+
+.if WANT_TIMER_COUNTER_0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Control Register
+VE_TCCR0A:
+ .dw $ff06
+ .db "TCCR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0A
+XT_TCCR0A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0A:
+ .dw 68
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw 70
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0A:
+ .dw $ff05
+ .db "OCR0A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0A
+XT_OCR0A:
+ .dw PFA_DOVARIABLE
+PFA_OCR0A:
+ .dw 71
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Mask Register
+VE_TIMSK0:
+ .dw $ff06
+ .db "TIMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK0
+XT_TIMSK0:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK0:
+ .dw 110
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Flag register
+VE_TIFR0:
+ .dw $ff05
+ .db "TIFR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR0
+XT_TIFR0:
+ .dw PFA_DOVARIABLE
+PFA_TIFR0:
+ .dw 53
+; ( -- addr ) System Constant
+; R( -- )
+; General Timer/Control Register
+VE_GTCCR:
+ .dw $ff05
+ .db "GTCCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GTCCR
+XT_GTCCR:
+ .dw PFA_DOVARIABLE
+PFA_GTCCR:
+ .dw 67
+
+.endif
+.if WANT_TIMER_COUNTER_1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw 128
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw 129
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter 1 Control Register C
+VE_TCCR1C:
+ .dw $ff06
+ .db "TCCR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1C
+XT_TCCR1C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1C:
+ .dw 130
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Bytes
+VE_TCNT1:
+ .dw $ff05
+ .db "TCNT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1
+XT_TCNT1:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1:
+ .dw 132
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register A Bytes
+VE_OCR1A:
+ .dw $ff05
+ .db "OCR1A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1A
+XT_OCR1A:
+ .dw PFA_DOVARIABLE
+PFA_OCR1A:
+ .dw 136
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register B Bytes
+VE_OCR1B:
+ .dw $ff05
+ .db "OCR1B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1B
+XT_OCR1B:
+ .dw PFA_DOVARIABLE
+PFA_OCR1B:
+ .dw 138
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Bytes
+VE_ICR1:
+ .dw $ff04
+ .db "ICR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1
+XT_ICR1:
+ .dw PFA_DOVARIABLE
+PFA_ICR1:
+ .dw 134
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Mask Register
+VE_TIMSK1:
+ .dw $ff06
+ .db "TIMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK1
+XT_TIMSK1:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK1:
+ .dw 111
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Flag register
+VE_TIFR1:
+ .dw $ff05
+ .db "TIFR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR1
+XT_TIFR1:
+ .dw PFA_DOVARIABLE
+PFA_TIFR1:
+ .dw 54
+
+.endif
+.if WANT_TIMER_COUNTER_2 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register
+VE_TCCR2A:
+ .dw $ff06
+ .db "TCCR2A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2A
+XT_TCCR2A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2A:
+ .dw 176
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2
+VE_TCNT2:
+ .dw $ff05
+ .db "TCNT2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT2
+XT_TCNT2:
+ .dw PFA_DOVARIABLE
+PFA_TCNT2:
+ .dw 178
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register
+VE_OCR2A:
+ .dw $ff05
+ .db "OCR2A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2A
+XT_OCR2A:
+ .dw PFA_DOVARIABLE
+PFA_OCR2A:
+ .dw 179
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Interrupt Mask register
+VE_TIMSK2:
+ .dw $ff06
+ .db "TIMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK2
+XT_TIMSK2:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK2:
+ .dw 112
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Interrupt Flag Register
+VE_TIFR2:
+ .dw $ff05
+ .db "TIFR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR2
+XT_TIFR2:
+ .dw PFA_DOVARIABLE
+PFA_TIFR2:
+ .dw 55
+; ( -- addr ) System Constant
+; R( -- )
+; Asynchronous Status Register
+VE_ASSR:
+ .dw $ff04
+ .db "ASSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ASSR
+XT_ASSR:
+ .dw PFA_DOVARIABLE
+PFA_ASSR:
+ .dw 182
+
+.endif
+.if WANT_WATCHDOG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCR:
+ .dw $ff05
+ .db "WDTCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCR
+XT_WDTCR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCR:
+ .dw 96
+
+.endif
+.if WANT_EEPROM == 1
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Read/Write Access Bytes
+VE_EEAR:
+ .dw $ff04
+ .db "EEAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEAR
+XT_EEAR:
+ .dw PFA_DOVARIABLE
+PFA_EEAR:
+ .dw 65
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw 64
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw 63
+
+.endif
+.if WANT_SPI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR:
+ .dw $ff04
+ .db "SPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR
+XT_SPCR:
+ .dw PFA_DOVARIABLE
+PFA_SPCR:
+ .dw 76
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR:
+ .dw $ff04
+ .db "SPSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR
+XT_SPSR:
+ .dw PFA_DOVARIABLE
+PFA_SPSR:
+ .dw 77
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR:
+ .dw $ff04
+ .db "SPDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR
+XT_SPDR:
+ .dw PFA_DOVARIABLE
+PFA_SPDR:
+ .dw 78
+
+.endif
+.if WANT_PORTA == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Register
+VE_PORTA:
+ .dw $ff05
+ .db "PORTA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTA
+XT_PORTA:
+ .dw PFA_DOVARIABLE
+PFA_PORTA:
+ .dw 34
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Direction Register
+VE_DDRA:
+ .dw $ff04
+ .db "DDRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRA
+XT_DDRA:
+ .dw PFA_DOVARIABLE
+PFA_DDRA:
+ .dw 33
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Input Pins
+VE_PINA:
+ .dw $ff04
+ .db "PINA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINA
+XT_PINA:
+ .dw PFA_DOVARIABLE
+PFA_PINA:
+ .dw 32
+
+.endif
+.if WANT_PORTB == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw 37
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw 36
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw 35
+
+.endif
+.if WANT_PORTC == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Register
+VE_PORTC:
+ .dw $ff05
+ .db "PORTC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTC
+XT_PORTC:
+ .dw PFA_DOVARIABLE
+PFA_PORTC:
+ .dw 40
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Direction Register
+VE_DDRC:
+ .dw $ff04
+ .db "DDRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRC
+XT_DDRC:
+ .dw PFA_DOVARIABLE
+PFA_DDRC:
+ .dw 39
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Input Pins
+VE_PINC:
+ .dw $ff04
+ .db "PINC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINC
+XT_PINC:
+ .dw PFA_DOVARIABLE
+PFA_PINC:
+ .dw 38
+
+.endif
+.if WANT_PORTD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw 43
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw 42
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw 41
+
+.endif
+.if WANT_ANALOG_COMPARATOR == 1
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Control and Status Register B
+VE_ADCSRB:
+ .dw $ff06
+ .db "ADCSRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRB
+XT_ADCSRB:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRB:
+ .dw 123
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Control And Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw 80
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 1
+VE_DIDR1:
+ .dw $ff05
+ .db "DIDR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR1
+XT_DIDR1:
+ .dw PFA_DOVARIABLE
+PFA_DIDR1:
+ .dw 127
+
+.endif
+.if WANT_PORTE == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port E
+VE_PORTE:
+ .dw $ff05
+ .db "PORTE",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTE
+XT_PORTE:
+ .dw PFA_DOVARIABLE
+PFA_PORTE:
+ .dw 46
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port E
+VE_DDRE:
+ .dw $ff04
+ .db "DDRE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRE
+XT_DDRE:
+ .dw PFA_DOVARIABLE
+PFA_DDRE:
+ .dw 45
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port E
+VE_PINE:
+ .dw $ff04
+ .db "PINE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINE
+XT_PINE:
+ .dw PFA_DOVARIABLE
+PFA_PINE:
+ .dw 44
+
+.endif
+.if WANT_PORTF == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port F
+VE_PORTF:
+ .dw $ff05
+ .db "PORTF",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTF
+XT_PORTF:
+ .dw PFA_DOVARIABLE
+PFA_PORTF:
+ .dw 49
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port F
+VE_DDRF:
+ .dw $ff04
+ .db "DDRF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRF
+XT_DDRF:
+ .dw PFA_DOVARIABLE
+PFA_DDRF:
+ .dw 48
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port F
+VE_PINF:
+ .dw $ff04
+ .db "PINF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINF
+XT_PINF:
+ .dw PFA_DOVARIABLE
+PFA_PINF:
+ .dw 47
+
+.endif
+.if WANT_PORTG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Data Register
+VE_PORTG:
+ .dw $ff05
+ .db "PORTG",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTG
+XT_PORTG:
+ .dw PFA_DOVARIABLE
+PFA_PORTG:
+ .dw 52
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Data Direction Register
+VE_DDRG:
+ .dw $ff04
+ .db "DDRG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRG
+XT_DDRG:
+ .dw PFA_DOVARIABLE
+PFA_DDRG:
+ .dw 51
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Input Pins
+VE_PING:
+ .dw $ff04
+ .db "PING"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PING
+XT_PING:
+ .dw PFA_DOVARIABLE
+PFA_PING:
+ .dw 50
+
+.endif
+.if WANT_JTAG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; On-Chip Debug Related Register in I/O Memory
+VE_OCDR:
+ .dw $ff04
+ .db "OCDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCDR
+XT_OCDR:
+ .dw PFA_DOVARIABLE
+PFA_OCDR:
+ .dw 81
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw 85
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Status Register
+VE_MCUSR:
+ .dw $ff05
+ .db "MCUSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUSR
+XT_MCUSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUSR:
+ .dw 84
+
+.endif
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register A
+VE_EICRA:
+ .dw $ff05
+ .db "EICRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRA
+XT_EICRA:
+ .dw PFA_DOVARIABLE
+PFA_EICRA:
+ .dw 105
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Mask Register
+VE_EIMSK:
+ .dw $ff05
+ .db "EIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIMSK
+XT_EIMSK:
+ .dw PFA_DOVARIABLE
+PFA_EIMSK:
+ .dw 61
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Flag Register
+VE_EIFR:
+ .dw $ff04
+ .db "EIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIFR
+XT_EIFR:
+ .dw PFA_DOVARIABLE
+PFA_EIFR:
+ .dw 60
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 3
+VE_PCMSK3:
+ .dw $ff06
+ .db "PCMSK3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK3
+XT_PCMSK3:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK3:
+ .dw 115
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 2
+VE_PCMSK2:
+ .dw $ff06
+ .db "PCMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK2
+XT_PCMSK2:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK2:
+ .dw 109
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 1
+VE_PCMSK1:
+ .dw $ff06
+ .db "PCMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK1
+XT_PCMSK1:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK1:
+ .dw 108
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 0
+VE_PCMSK0:
+ .dw $ff06
+ .db "PCMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK0
+XT_PCMSK0:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK0:
+ .dw 107
+
+.endif
+.if WANT_USI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USI Data Register
+VE_USIDR:
+ .dw $ff05
+ .db "USIDR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USIDR
+XT_USIDR:
+ .dw PFA_DOVARIABLE
+PFA_USIDR:
+ .dw 186
+; ( -- addr ) System Constant
+; R( -- )
+; USI Status Register
+VE_USISR:
+ .dw $ff05
+ .db "USISR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USISR
+XT_USISR:
+ .dw PFA_DOVARIABLE
+PFA_USISR:
+ .dw 185
+; ( -- addr ) System Constant
+; R( -- )
+; USI Control Register
+VE_USICR:
+ .dw $ff05
+ .db "USICR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USICR
+XT_USICR:
+ .dw PFA_DOVARIABLE
+PFA_USICR:
+ .dw 184
+
+.endif
+.if WANT_AD_CONVERTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC multiplexer Selection Register
+VE_ADMUX:
+ .dw $ff05
+ .db "ADMUX",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADMUX
+XT_ADMUX:
+ .dw PFA_DOVARIABLE
+PFA_ADMUX:
+ .dw 124
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register
+VE_ADCSRA:
+ .dw $ff06
+ .db "ADCSRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRA
+XT_ADCSRA:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRA:
+ .dw 122
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register Bytes
+VE_ADC:
+ .dw $ff03
+ .db "ADC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADC
+XT_ADC:
+ .dw PFA_DOVARIABLE
+PFA_ADC:
+ .dw 120
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 0
+VE_DIDR0:
+ .dw $ff05
+ .db "DIDR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR0
+XT_DIDR0:
+ .dw PFA_DOVARIABLE
+PFA_DIDR0:
+ .dw 126
+
+.endif
+.if WANT_BOOT_LOAD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control Register
+VE_SPMCSR:
+ .dw $ff06
+ .db "SPMCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCSR
+XT_SPMCSR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCSR:
+ .dw 87
+
+.endif
+.if WANT_USART0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR0:
+ .dw $ff04
+ .db "UDR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR0
+XT_UDR0:
+ .dw PFA_DOVARIABLE
+PFA_UDR0:
+ .dw 198
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR0A:
+ .dw $ff06
+ .db "UCSR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0A
+XT_UCSR0A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0A:
+ .dw 192
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR0B:
+ .dw $ff06
+ .db "UCSR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0B
+XT_UCSR0B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0B:
+ .dw 193
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR0C:
+ .dw $ff06
+ .db "UCSR0C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0C
+XT_UCSR0C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0C:
+ .dw 194
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Bytes
+VE_UBRR0:
+ .dw $ff05
+ .db "UBRR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR0
+XT_UBRR0:
+ .dw PFA_DOVARIABLE
+PFA_UBRR0:
+ .dw 196
+
+.endif
+.if WANT_PORTH == 1
+; ( -- addr ) System Constant
+; R( -- )
+; PORT H Data Register
+VE_PORTH:
+ .dw $ff05
+ .db "PORTH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTH
+XT_PORTH:
+ .dw PFA_DOVARIABLE
+PFA_PORTH:
+ .dw 218
+; ( -- addr ) System Constant
+; R( -- )
+; PORT H Data Direction Register
+VE_DDRH:
+ .dw $ff04
+ .db "DDRH"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRH
+XT_DDRH:
+ .dw PFA_DOVARIABLE
+PFA_DDRH:
+ .dw 217
+; ( -- addr ) System Constant
+; R( -- )
+; PORT H Input Pins
+VE_PINH:
+ .dw $ff04
+ .db "PINH"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINH
+XT_PINH:
+ .dw PFA_DOVARIABLE
+PFA_PINH:
+ .dw 216
+
+.endif
+.if WANT_PORTJ == 1
+; ( -- addr ) System Constant
+; R( -- )
+; PORT J Data Register
+VE_PORTJ:
+ .dw $ff05
+ .db "PORTJ",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTJ
+XT_PORTJ:
+ .dw PFA_DOVARIABLE
+PFA_PORTJ:
+ .dw 221
+; ( -- addr ) System Constant
+; R( -- )
+; PORT J Data Direction Register
+VE_DDRJ:
+ .dw $ff04
+ .db "DDRJ"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRJ
+XT_DDRJ:
+ .dw PFA_DOVARIABLE
+PFA_DDRJ:
+ .dw 220
+; ( -- addr ) System Constant
+; R( -- )
+; PORT J Input Pins
+VE_PINJ:
+ .dw $ff04
+ .db "PINJ"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINJ
+XT_PINJ:
+ .dw PFA_DOVARIABLE
+PFA_PINJ:
+ .dw 219
+
+.endif
+.if WANT_LCD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 19
+VE_LCDDR19:
+ .dw $ff07
+ .db "LCDDR19",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR19
+XT_LCDDR19:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR19:
+ .dw 255
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 18
+VE_LCDDR18:
+ .dw $ff07
+ .db "LCDDR18",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR18
+XT_LCDDR18:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR18:
+ .dw 254
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 17
+VE_LCDDR17:
+ .dw $ff07
+ .db "LCDDR17",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR17
+XT_LCDDR17:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR17:
+ .dw 253
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 16
+VE_LCDDR16:
+ .dw $ff07
+ .db "LCDDR16",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR16
+XT_LCDDR16:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR16:
+ .dw 252
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 15
+VE_LCDDR15:
+ .dw $ff07
+ .db "LCDDR15",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR15
+XT_LCDDR15:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR15:
+ .dw 251
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 14
+VE_LCDDR14:
+ .dw $ff07
+ .db "LCDDR14",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR14
+XT_LCDDR14:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR14:
+ .dw 250
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 13
+VE_LCDDR13:
+ .dw $ff07
+ .db "LCDDR13",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR13
+XT_LCDDR13:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR13:
+ .dw 249
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 12
+VE_LCDDR12:
+ .dw $ff07
+ .db "LCDDR12",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR12
+XT_LCDDR12:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR12:
+ .dw 248
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 11
+VE_LCDDR11:
+ .dw $ff07
+ .db "LCDDR11",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR11
+XT_LCDDR11:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR11:
+ .dw 247
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 10
+VE_LCDDR10:
+ .dw $ff07
+ .db "LCDDR10",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR10
+XT_LCDDR10:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR10:
+ .dw 246
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 9
+VE_LCDDR9:
+ .dw $ff06
+ .db "LCDDR9"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR9
+XT_LCDDR9:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR9:
+ .dw 245
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 8
+VE_LCDDR8:
+ .dw $ff06
+ .db "LCDDR8"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR8
+XT_LCDDR8:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR8:
+ .dw 244
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 7
+VE_LCDDR7:
+ .dw $ff06
+ .db "LCDDR7"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR7
+XT_LCDDR7:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR7:
+ .dw 243
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 6
+VE_LCDDR6:
+ .dw $ff06
+ .db "LCDDR6"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR6
+XT_LCDDR6:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR6:
+ .dw 242
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 5
+VE_LCDDR5:
+ .dw $ff06
+ .db "LCDDR5"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR5
+XT_LCDDR5:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR5:
+ .dw 241
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 4
+VE_LCDDR4:
+ .dw $ff06
+ .db "LCDDR4"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR4
+XT_LCDDR4:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR4:
+ .dw 240
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 3
+VE_LCDDR3:
+ .dw $ff06
+ .db "LCDDR3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR3
+XT_LCDDR3:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR3:
+ .dw 239
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 2
+VE_LCDDR2:
+ .dw $ff06
+ .db "LCDDR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR2
+XT_LCDDR2:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR2:
+ .dw 238
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 1
+VE_LCDDR1:
+ .dw $ff06
+ .db "LCDDR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR1
+XT_LCDDR1:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR1:
+ .dw 237
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 0
+VE_LCDDR0:
+ .dw $ff06
+ .db "LCDDR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR0
+XT_LCDDR0:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR0:
+ .dw 236
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Contrast Control Register
+VE_LCDCCR:
+ .dw $ff06
+ .db "LCDCCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDCCR
+XT_LCDCCR:
+ .dw PFA_DOVARIABLE
+PFA_LCDCCR:
+ .dw 231
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Frame Rate Register
+VE_LCDFRR:
+ .dw $ff06
+ .db "LCDFRR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDFRR
+XT_LCDFRR:
+ .dw PFA_DOVARIABLE
+PFA_LCDFRR:
+ .dw 230
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Control and Status Register B
+VE_LCDCRB:
+ .dw $ff06
+ .db "LCDCRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDCRB
+XT_LCDCRB:
+ .dw PFA_DOVARIABLE
+PFA_LCDCRB:
+ .dw 229
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Control and Status Register A
+VE_LCDCRA:
+ .dw $ff06
+ .db "LCDCRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDCRA
+XT_LCDCRA:
+ .dw PFA_DOVARIABLE
+PFA_LCDCRA:
+ .dw 228
+
+.endif
+.if WANT_CPU == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw 95
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer
+VE_SP:
+ .dw $ff02
+ .db "SP"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SP
+XT_SP:
+ .dw PFA_DOVARIABLE
+PFA_SP:
+ .dw 93
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Calibration Value
+VE_OSCCAL:
+ .dw $ff06
+ .db "OSCCAL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSCCAL
+XT_OSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_OSCCAL:
+ .dw 102
+; ( -- addr ) System Constant
+; R( -- )
+; Clock Prescale Register
+VE_CLKPR:
+ .dw $ff05
+ .db "CLKPR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKPR
+XT_CLKPR:
+ .dw PFA_DOVARIABLE
+PFA_CLKPR:
+ .dw 97
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register
+VE_PRR:
+ .dw $ff03
+ .db "PRR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR
+XT_PRR:
+ .dw PFA_DOVARIABLE
+PFA_PRR:
+ .dw 100
+; ( -- addr ) System Constant
+; R( -- )
+; Sleep Mode Control Register
+VE_SMCR:
+ .dw $ff04
+ .db "SMCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SMCR
+XT_SMCR:
+ .dw PFA_DOVARIABLE
+PFA_SMCR:
+ .dw 83
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 2
+VE_GPIOR2:
+ .dw $ff06
+ .db "GPIOR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR2
+XT_GPIOR2:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR2:
+ .dw 75
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 1
+VE_GPIOR1:
+ .dw $ff06
+ .db "GPIOR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR1
+XT_GPIOR1:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR1:
+ .dw 74
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 0
+VE_GPIOR0:
+ .dw $ff06
+ .db "GPIOR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR0
+XT_GPIOR0:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR0:
+ .dw 62
+
+.endif
diff --git a/amforth-6.5/avr8/devices/atmega3290pa/device.py b/amforth-6.5/avr8/devices/atmega3290pa/device.py
new file mode 100644
index 0000000..9604244
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega3290pa/device.py
@@ -0,0 +1,378 @@
+# Generated Automatically
+
+# Partname ATmega3290PA
+
+MCUREGS = {
+# Interrupt Vectors
+ 'INT0Addr' : '#2', # External Interrupt Request 0
+ 'PCINT0Addr' : '#4', # Pin Change Interrupt Request 0
+ 'PCINT1Addr' : '#6', # Pin Change Interrupt Request 1
+ 'TIMER2_COMPAddr' : '#8', # Timer/Counter2 Compare Match
+ 'TIMER2_OVFAddr' : '#10', # Timer/Counter2 Overflow
+ 'TIMER1_CAPTAddr' : '#12', # Timer/Counter1 Capture Event
+ 'TIMER1_COMPAAddr' : '#14', # Timer/Counter1 Compare Match A
+ 'TIMER1_COMPBAddr' : '#16', # Timer/Counter Compare Match B
+ 'TIMER1_OVFAddr' : '#18', # Timer/Counter1 Overflow
+ 'TIMER0_COMPAddr' : '#20', # Timer/Counter0 Compare Match
+ 'TIMER0_OVFAddr' : '#22', # Timer/Counter0 Overflow
+ 'SPI_STCAddr' : '#24', # SPI Serial Transfer Complete
+ 'USART_RXAddr' : '#26', # USART, Rx Complete
+ 'USART_UDREAddr' : '#28', # USART Data register Empty
+ 'USART0_TXAddr' : '#30', # USART0, Tx Complete
+ 'USI_STARTAddr' : '#32', # USI Start Condition
+ 'USI_OVERFLOWAddr' : '#34', # USI Overflow
+ 'ANALOG_COMPAddr' : '#36', # Analog Comparator
+ 'ADCAddr' : '#38', # ADC Conversion Complete
+ 'EE_READYAddr' : '#40', # EEPROM Ready
+ 'SPM_READYAddr' : '#42', # Store Program Memory Read
+ 'LCDAddr' : '#44', # LCD Start of Frame
+ 'PCINT2Addr' : '#46', # Pin Change Interrupt Request 2
+ 'PCINT3Addr' : '#48', # Pin Change Interrupt Request 3
+
+# Module TIMER_COUNTER_0
+ 'TCCR0A' : '$44', # Timer/Counter0 Control Registe
+ 'TCCR0A_FOC0A': '$80', # Force Output Compare
+ 'TCCR0A_WGM00': '$40', # Waveform Generation Mode 0
+ 'TCCR0A_COM0A': '$30', # Compare Match Output Modes
+ 'TCCR0A_WGM01': '$8', # Waveform Generation Mode 1
+ 'TCCR0A_CS0': '$7', # Clock Selects
+ 'TCNT0' : '$46', # Timer/Counter0
+ 'OCR0A' : '$47', # Timer/Counter0 Output Compare
+ 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
+ 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
+ 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
+ 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
+ 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
+ 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Control Register
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSR310': '$1', # Prescaler Reset Timer/Counter1
+
+# Module TIMER_COUNTER_1
+ 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
+ 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
+ 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
+ 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
+ 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
+ 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
+ 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
+ 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
+ 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
+ 'TCCR1C' : '$82', # Timer/Counter 1 Control Regist
+ 'TCCR1C_FOC1A': '$80', # Force Output Compare 1A
+ 'TCCR1C_FOC1B': '$40', # Force Output Compare 1B
+ 'TCNT1' : '$84', # Timer/Counter1 Bytes
+ 'OCR1A' : '$88', # Timer/Counter1 Output Compare
+ 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
+ 'ICR1' : '$86', # Timer/Counter1 Input Capture R
+ 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
+ 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
+ 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
+ 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
+ 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
+ 'TIFR1' : '$36', # Timer/Counter1 Interrupt Flag
+ 'TIFR1_ICF1': '$20', # Input Capture Flag 1
+ 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
+ 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
+ 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
+
+# Module TIMER_COUNTER_2
+ 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
+ 'TCCR2A_FOC2A': '$80', # Force Output Compare A
+ 'TCCR2A_WGM20': '$40', # Waveform Generation Mode
+ 'TCCR2A_COM2A': '$30', # Compare Output Mode bits
+ 'TCCR2A_WGM21': '$8', # Waveform Generation Mode
+ 'TCCR2A_CS2': '$7', # Clock Select bits
+ 'TCNT2' : '$b2', # Timer/Counter2
+ 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
+ 'TIMSK2' : '$70', # Timer/Counter2 Interrupt Mask
+ 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
+ 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
+ 'TIFR2' : '$37', # Timer/Counter2 Interrupt Flag
+ 'TIFR2_OCF2A': '$2', # Timer/Counter2 Output Compare
+ 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_PSR2': '$2', # Prescaler Reset Timer/Counter2
+ 'ASSR' : '$b6', # Asynchronous Status Register
+ 'ASSR_EXCLK': '$10', # Enable External Clock Interrup
+ 'ASSR_AS2': '$8', # AS2: Asynchronous Timer/Counte
+ 'ASSR_TCN2UB': '$4', # TCN2UB: Timer/Counter2 Update
+ 'ASSR_OCR2UB': '$2', # Output Compare Register2 Updat
+ 'ASSR_TCR2UB': '$1', # TCR2UB: Timer/Counter Control
+
+# Module WATCHDOG
+ 'WDTCR' : '$60', # Watchdog Timer Control Registe
+ 'WDTCR_WDCE': '$10', # Watchdog Change Enable
+ 'WDTCR_WDE': '$8', # Watch Dog Enable
+ 'WDTCR_WDP': '$7', # Watch Dog Timer Prescaler bits
+
+# Module EEPROM
+ 'EEAR' : '$41', # EEPROM Read/Write Access Byte
+ 'EEDR' : '$40', # EEPROM Data Register
+ 'EECR' : '$3f', # EEPROM Control Register
+ 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
+ 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
+ 'EECR_EEWE': '$2', # EEPROM Write Enable
+ 'EECR_EERE': '$1', # EEPROM Read Enable
+
+# Module SPI
+ 'SPCR' : '$4c', # SPI Control Register
+ 'SPCR_SPIE': '$80', # SPI Interrupt Enable
+ 'SPCR_SPE': '$40', # SPI Enable
+ 'SPCR_DORD': '$20', # Data Order
+ 'SPCR_MSTR': '$10', # Master/Slave Select
+ 'SPCR_CPOL': '$8', # Clock polarity
+ 'SPCR_CPHA': '$4', # Clock Phase
+ 'SPCR_SPR': '$3', # SPI Clock Rate Selects
+ 'SPSR' : '$4d', # SPI Status Register
+ 'SPSR_SPIF': '$80', # SPI Interrupt Flag
+ 'SPSR_WCOL': '$40', # Write Collision Flag
+ 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
+ 'SPDR' : '$4e', # SPI Data Register
+
+# Module PORTA
+ 'PORTA' : '$22', # Port A Data Register
+ 'DDRA' : '$21', # Port A Data Direction Register
+ 'PINA' : '$20', # Port A Input Pins
+
+# Module PORTB
+ 'PORTB' : '$25', # Port B Data Register
+ 'DDRB' : '$24', # Port B Data Direction Register
+ 'PINB' : '$23', # Port B Input Pins
+
+# Module PORTC
+ 'PORTC' : '$28', # Port C Data Register
+ 'DDRC' : '$27', # Port C Data Direction Register
+ 'PINC' : '$26', # Port C Input Pins
+
+# Module PORTD
+ 'PORTD' : '$2b', # Port D Data Register
+ 'DDRD' : '$2a', # Port D Data Direction Register
+ 'PIND' : '$29', # Port D Input Pins
+
+# Module ANALOG_COMPARATOR
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
+ 'ACSR' : '$50', # Analog Comparator Control And
+ 'ACSR_ACD': '$80', # Analog Comparator Disable
+ 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
+ 'ACSR_ACO': '$20', # Analog Compare Output
+ 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
+ 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
+ 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
+ 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
+ 'DIDR1' : '$7f', # Digital Input Disable Register
+ 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
+ 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
+
+# Module PORTE
+ 'PORTE' : '$2e', # Data Register, Port E
+ 'DDRE' : '$2d', # Data Direction Register, Port
+ 'PINE' : '$2c', # Input Pins, Port E
+
+# Module PORTF
+ 'PORTF' : '$31', # Data Register, Port F
+ 'DDRF' : '$30', # Data Direction Register, Port
+ 'PINF' : '$2f', # Input Pins, Port F
+
+# Module PORTG
+ 'PORTG' : '$34', # Port G Data Register
+ 'DDRG' : '$33', # Port G Data Direction Register
+ 'PING' : '$32', # Port G Input Pins
+
+# Module JTAG
+ 'OCDR' : '$51', # On-Chip Debug Related Register
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_JTD': '$80', # JTAG Interface Disable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+
+# Module EXTERNAL_INTERRUPT
+ 'EICRA' : '$69', # External Interrupt Control Reg
+ 'EICRA_ISC01': '$2', # External Interrupt Sense Contr
+ 'EICRA_ISC00': '$1', # External Interrupt Sense Contr
+ 'EIMSK' : '$3d', # External Interrupt Mask Regist
+ 'EIMSK_PCIE': '$f0', # Pin Change Interrupt Enables
+ 'EIMSK_INT0': '$1', # External Interrupt Request 0 E
+ 'EIFR' : '$3c', # External Interrupt Flag Regist
+ 'EIFR_PCIF': '$f0', # Pin Change Interrupt Flags
+ 'EIFR_INTF0': '$1', # External Interrupt Flag 0
+ 'PCMSK3' : '$73', # Pin Change Mask Register 3
+ 'PCMSK2' : '$6d', # Pin Change Mask Register 2
+ 'PCMSK1' : '$6c', # Pin Change Mask Register 1
+ 'PCMSK0' : '$6b', # Pin Change Mask Register 0
+
+# Module USI
+ 'USIDR' : '$ba', # USI Data Register
+ 'USISR' : '$b9', # USI Status Register
+ 'USISR_USISIF': '$80', # Start Condition Interrupt Flag
+ 'USISR_USIOIF': '$40', # Counter Overflow Interrupt Fla
+ 'USISR_USIPF': '$20', # Stop Condition Flag
+ 'USISR_USIDC': '$10', # Data Output Collision
+ 'USISR_USICNT': '$f', # USI Counter Value Bits
+ 'USICR' : '$b8', # USI Control Register
+ 'USICR_USISIE': '$80', # Start Condition Interrupt Enab
+ 'USICR_USIOIE': '$40', # Counter Overflow Interrupt Ena
+ 'USICR_USIWM': '$30', # USI Wire Mode Bits
+ 'USICR_USICS': '$c', # USI Clock Source Select Bits
+ 'USICR_USICLK': '$2', # Clock Strobe
+ 'USICR_USITC': '$1', # Toggle Clock Port Pin
+
+# Module AD_CONVERTER
+ 'ADMUX' : '$7c', # The ADC multiplexer Selection
+ 'ADMUX_REFS': '$c0', # Reference Selection Bits
+ 'ADMUX_ADLAR': '$20', # Left Adjust Result
+ 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
+ 'ADCSRA' : '$7a', # The ADC Control and Status reg
+ 'ADCSRA_ADEN': '$80', # ADC Enable
+ 'ADCSRA_ADSC': '$40', # ADC Start Conversion
+ 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
+ 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
+ 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
+ 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
+ 'ADC' : '$78', # ADC Data Register Bytes
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Sources
+ 'DIDR0' : '$7e', # Digital Input Disable Register
+ 'DIDR0_ADC7D': '$80', # ADC7 Digital input Disable
+ 'DIDR0_ADC6D': '$40', # ADC6 Digital input Disable
+ 'DIDR0_ADC5D': '$20', # ADC5 Digital input Disable
+ 'DIDR0_ADC4D': '$10', # ADC4 Digital input Disable
+ 'DIDR0_ADC3D': '$8', # ADC3 Digital input Disable
+ 'DIDR0_ADC2D': '$4', # ADC2 Digital input Disable
+ 'DIDR0_ADC1D': '$2', # ADC1 Digital input Disable
+ 'DIDR0_ADC0D': '$1', # ADC0 Digital input Disable
+
+# Module BOOT_LOAD
+ 'SPMCSR' : '$57', # Store Program Memory Control R
+ 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
+ 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
+ 'SPMCSR_RWWSRE': '$10', # Read While Write section read
+ 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
+ 'SPMCSR_PGWRT': '$4', # Page Write
+ 'SPMCSR_PGERS': '$2', # Page Erase
+ 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
+
+# Module USART0
+ 'UDR0' : '$c6', # USART I/O Data Register
+ 'UCSR0A' : '$c0', # USART Control and Status Regis
+ 'UCSR0A_RXC0': '$80', # USART Receive Complete
+ 'UCSR0A_TXC0': '$40', # USART Transmit Complete
+ 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
+ 'UCSR0A_FE0': '$10', # Framing Error
+ 'UCSR0A_DOR0': '$8', # Data OverRun
+ 'UCSR0A_UPE0': '$4', # USART Parity Error
+ 'UCSR0A_U2X0': '$2', # Double the USART Transmission
+ 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
+ 'UCSR0B' : '$c1', # USART Control and Status Regis
+ 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
+ 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
+ 'UCSR0B_UDRIE0': '$20', # USART Data Register Empty Inte
+ 'UCSR0B_RXEN0': '$10', # Receiver Enable
+ 'UCSR0B_TXEN0': '$8', # Transmitter Enable
+ 'UCSR0B_UCSZ02': '$4', # Character Size
+ 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
+ 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
+ 'UCSR0C' : '$c2', # USART Control and Status Regis
+ 'UCSR0C_UMSEL0': '$40', # USART Mode Select
+ 'UCSR0C_UPM0': '$30', # Parity Mode Bits
+ 'UCSR0C_USBS0': '$8', # Stop Bit Select
+ 'UCSR0C_UCSZ0': '$6', # Character Size
+ 'UCSR0C_UCPOL0': '$1', # Clock Polarity
+ 'UBRR0' : '$c4', # USART Baud Rate Register Byte
+
+# Module PORTH
+ 'PORTH' : '$da', # PORT H Data Register
+ 'DDRH' : '$d9', # PORT H Data Direction Register
+ 'PINH' : '$d8', # PORT H Input Pins
+
+# Module PORTJ
+ 'PORTJ' : '$dd', # PORT J Data Register
+ 'DDRJ' : '$dc', # PORT J Data Direction Register
+ 'PINJ' : '$db', # PORT J Input Pins
+
+# Module LCD
+ 'LCDDR19' : '$ff', # LCD Data Register 19
+ 'LCDDR18' : '$fe', # LCD Data Register 18
+ 'LCDDR17' : '$fd', # LCD Data Register 17
+ 'LCDDR16' : '$fc', # LCD Data Register 16
+ 'LCDDR15' : '$fb', # LCD Data Register 15
+ 'LCDDR14' : '$fa', # LCD Data Register 14
+ 'LCDDR13' : '$f9', # LCD Data Register 13
+ 'LCDDR12' : '$f8', # LCD Data Register 12
+ 'LCDDR11' : '$f7', # LCD Data Register 11
+ 'LCDDR10' : '$f6', # LCD Data Register 10
+ 'LCDDR9' : '$f5', # LCD Data Register 9
+ 'LCDDR8' : '$f4', # LCD Data Register 8
+ 'LCDDR7' : '$f3', # LCD Data Register 7
+ 'LCDDR6' : '$f2', # LCD Data Register 6
+ 'LCDDR5' : '$f1', # LCD Data Register 5
+ 'LCDDR4' : '$f0', # LCD Data Register 4
+ 'LCDDR3' : '$ef', # LCD Data Register 3
+ 'LCDDR2' : '$ee', # LCD Data Register 2
+ 'LCDDR1' : '$ed', # LCD Data Register 1
+ 'LCDDR0' : '$ec', # LCD Data Register 0
+ 'LCDCCR' : '$e7', # LCD Contrast Control Register
+ 'LCDCCR_LCDDC': '$e0', # LCD Display Configurations
+ 'LCDCCR_LCDMDT': '$10', # LCD Maximum Drive Time
+ 'LCDCCR_LCDCC': '$f', # LCD Contrast Controls
+ 'LCDFRR' : '$e6', # LCD Frame Rate Register
+ 'LCDFRR_LCDPS': '$70', # LCD Prescaler Selects
+ 'LCDFRR_LCDCD': '$7', # LCD Clock Dividers
+ 'LCDCRB' : '$e5', # LCD Control and Status Registe
+ 'LCDCRB_LCDCS': '$80', # LCD CLock Select
+ 'LCDCRB_LCD2B': '$40', # LCD 1/2 Bias Select
+ 'LCDCRB_LCDMUX': '$30', # LCD Mux Selects
+ 'LCDCRB_LCDPM': '$f', # LCD Port Masks
+ 'LCDCRA' : '$e4', # LCD Control and Status Registe
+ 'LCDCRA_LCDEN': '$80', # LCD Enable
+ 'LCDCRA_LCDAB': '$40', # LCD A or B waveform
+ 'LCDCRA_LCDIF': '$10', # LCD Interrupt Flag
+ 'LCDCRA_LCDIE': '$8', # LCD Interrupt Enable
+ 'LCDCRA_LCDBD': '$4', # LCD Buffer Disable
+ 'LCDCRA_LCDCCD': '$2', # LCD Contrast Control Disable
+ 'LCDCRA_LCDBL': '$1', # LCD Blanking
+
+# Module CPU
+ 'SREG' : '$5f', # Status Register
+ 'SREG_I': '$80', # Global Interrupt Enable
+ 'SREG_T': '$40', # Bit Copy Storage
+ 'SREG_H': '$20', # Half Carry Flag
+ 'SREG_S': '$10', # Sign Bit
+ 'SREG_V': '$8', # Two's Complement Overflow Flag
+ 'SREG_N': '$4', # Negative Flag
+ 'SREG_Z': '$2', # Zero Flag
+ 'SREG_C': '$1', # Carry Flag
+ 'SP' : '$5d', # Stack Pointer
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_JTD': '$80', # JTAG Interface Disable
+ 'MCUCR_BODS': '$40', # BOD Sleep
+ 'MCUCR_BODSE': '$20', # BOD Sleep Enable
+ 'MCUCR_PUD': '$10', # Pull-up disable
+ 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
+ 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+ 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
+ 'MCUSR_BORF': '$4', # Brown-out Reset Flag
+ 'MCUSR_EXTRF': '$2', # External Reset Flag
+ 'MCUSR_PORF': '$1', # Power-on reset flag
+ 'OSCCAL' : '$66', # Oscillator Calibration Value
+ 'CLKPR' : '$61', # Clock Prescale Register
+ 'CLKPR_CLKPCE': '$80', # Clock Prescaler Change Enable
+ 'CLKPR_CLKPS': '$f', # Clock Prescaler Select Bits
+ 'PRR' : '$64', # Power Reduction Register
+ 'PRR_PRLCD': '$10', # Power Reduction LCD
+ 'PRR_PRTIM1': '$8', # Power Reduction Timer/Counter1
+ 'PRR_PRSPI': '$4', # Power Reduction Serial Periphe
+ 'PRR_PRUSART0': '$2', # Power Reduction USART
+ 'PRR_PRADC': '$1', # Power Reduction ADC
+ 'SMCR' : '$53', # Sleep Mode Control Register
+ 'SMCR_SM': '$e', # Sleep Mode Select bits
+ 'SMCR_SE': '$1', # Sleep Enable
+ 'GPIOR2' : '$4b', # General Purpose IO Register 2
+ 'GPIOR1' : '$4a', # General Purpose IO Register 1
+ 'GPIOR0' : '$3e', # General Purpose IO Register 0
+
+ '__amforth_dummy':'0'
+}
diff --git a/amforth-6.5/avr8/devices/atmega3290pa/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega3290pa/words/no-jtag.asm
new file mode 100644
index 0000000..352a4bb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega3290pa/words/no-jtag.asm
@@ -0,0 +1,14 @@
+; ( -- )
+; ( -- )
+; MCU
+; disable jtag at runtime
+VE_NOJTAG:
+ .dw $FF05
+ .db "-jtag",0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOJTAG
+XT_NOJTAG:
+ .dw PFA_NOJTAG
+PFA_NOJTAG:
+
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega3290pa/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega3290pa/words/no-wdt.asm
new file mode 100644
index 0000000..4a12261
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega3290pa/words/no-wdt.asm
@@ -0,0 +1,22 @@
+; ( -- )
+; MCU
+; disable watch dog timer at runtime
+VE_NOWDT:
+ .dw $ff04
+ .db "-wdt"
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOWDT
+XT_NOWDT:
+ .dw PFA_NOWDT
+PFA_NOWDT:
+
+; Reset WDT
+ wdr
+; Write logical one to WDTOE and WDE
+ in_ temp1, WDTCR
+ ori temp1, (1<<WDTOE)|(1<<WDE)
+ out WDTCR, temp1
+; Turn off WDT
+ ldi temp1, (0<<WDE)
+ out_ WDTCR, temp1
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega3290pa/words/sleep.asm b/amforth-6.5/avr8/devices/atmega3290pa/words/sleep.asm
new file mode 100644
index 0000000..256249c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega3290pa/words/sleep.asm
@@ -0,0 +1,19 @@
+; ( mode -- )
+; MCU
+; put the controller into the specified sleep mode
+VE_SLEEP:
+ .dw $ff05
+ .db "sleep", 0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_SLEEP
+XT_SLEEP:
+ .dw PFA_SLEEP
+PFA_SLEEP:
+ andi tosl, 7 ; leave only legal mode bits
+ lsl tosl ; move to correct location (bits 3-1)
+ ori tosl, 1 ; set the SE bit
+ out_ SMCR, tosl ; set the sleep config
+ sleep ; nighty-night
+ out_ SMCR, zerol ; 0 protects against accidental sleeps
+ loadtos ; pop argument from stack
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega329a/atmega329a.frt b/amforth-6.5/avr8/devices/atmega329a/atmega329a.frt
new file mode 100644
index 0000000..15882a6
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega329a/atmega329a.frt
@@ -0,0 +1,461 @@
+\ Partname: ATmega329A
+\ generated automatically
+
+\ TIMER_COUNTER_0
+&68 constant TCCR0A \ Timer/Counter0 Control Register
+ $80 constant TCCR0A_FOC0A \ Force Output Compare
+ $40 constant TCCR0A_WGM00 \ Waveform Generation Mode 0
+ $30 constant TCCR0A_COM0A \ Compare Match Output Modes
+ $08 constant TCCR0A_WGM01 \ Waveform Generation Mode 1
+ $07 constant TCCR0A_CS0 \ Clock Selects
+&70 constant TCNT0 \ Timer/Counter0
+&71 constant OCR0A \ Timer/Counter0 Output Compare Register
+&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
+ $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match Interrupt Enable
+ $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
+&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
+ $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0
+ $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
+&67 constant GTCCR \ General Timer/Control Register
+ $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
+ $01 constant GTCCR_PSR310 \ Prescaler Reset Timer/Counter1 and Timer/Counter0
+\ TIMER_COUNTER_1
+&128 constant TCCR1A \ Timer/Counter1 Control Register A
+ $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
+ $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
+ $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
+&129 constant TCCR1B \ Timer/Counter1 Control Register B
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
+ $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
+&130 constant TCCR1C \ Timer/Counter 1 Control Register C
+ $80 constant TCCR1C_FOC1A \ Force Output Compare 1A
+ $40 constant TCCR1C_FOC1B \ Force Output Compare 1B
+&132 constant TCNT1 \ Timer/Counter1 Bytes
+&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
+&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
+&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
+&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
+ $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
+ $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
+ $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
+ $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
+&54 constant TIFR1 \ Timer/Counter1 Interrupt Flag register
+ $20 constant TIFR1_ICF1 \ Input Capture Flag 1
+ $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
+ $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
+ $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
+\ TIMER_COUNTER_2
+&176 constant TCCR2A \ Timer/Counter2 Control Register
+ $80 constant TCCR2A_FOC2A \ Force Output Compare A
+ $40 constant TCCR2A_WGM20 \ Waveform Generation Mode
+ $30 constant TCCR2A_COM2A \ Compare Output Mode bits
+ $08 constant TCCR2A_WGM21 \ Waveform Generation Mode
+ $07 constant TCCR2A_CS2 \ Clock Select bits
+&178 constant TCNT2 \ Timer/Counter2
+&179 constant OCR2A \ Timer/Counter2 Output Compare Register
+&112 constant TIMSK2 \ Timer/Counter2 Interrupt Mask register
+ $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match Interrupt Enable
+ $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
+&55 constant TIFR2 \ Timer/Counter2 Interrupt Flag Register
+ $02 constant TIFR2_OCF2A \ Timer/Counter2 Output Compare Flag 2
+ $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
+&182 constant ASSR \ Asynchronous Status Register
+ $10 constant ASSR_EXCLK \ Enable External Clock Interrupt
+ $08 constant ASSR_AS2 \ AS2: Asynchronous Timer/Counter2
+ $04 constant ASSR_TCN2UB \ TCN2UB: Timer/Counter2 Update Busy
+ $02 constant ASSR_OCR2UB \ Output Compare Register2 Update Busy
+ $01 constant ASSR_TCR2UB \ TCR2UB: Timer/Counter Control Register2 Update Busy
+\ WATCHDOG
+&96 constant WDTCR \ Watchdog Timer Control Register
+ $10 constant WDTCR_WDCE \ Watchdog Change Enable
+ $08 constant WDTCR_WDE \ Watch Dog Enable
+ $07 constant WDTCR_WDP \ Watch Dog Timer Prescaler bits
+\ EEPROM
+&65 constant EEAR \ EEPROM Read/Write Access Bytes
+&64 constant EEDR \ EEPROM Data Register
+&63 constant EECR \ EEPROM Control Register
+ $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
+ $04 constant EECR_EEMWE \ EEPROM Master Write Enable
+ $02 constant EECR_EEWE \ EEPROM Write Enable
+ $01 constant EECR_EERE \ EEPROM Read Enable
+\ SPI
+&76 constant SPCR \ SPI Control Register
+ $80 constant SPCR_SPIE \ SPI Interrupt Enable
+ $40 constant SPCR_SPE \ SPI Enable
+ $20 constant SPCR_DORD \ Data Order
+ $10 constant SPCR_MSTR \ Master/Slave Select
+ $08 constant SPCR_CPOL \ Clock polarity
+ $04 constant SPCR_CPHA \ Clock Phase
+ $03 constant SPCR_SPR \ SPI Clock Rate Selects
+&77 constant SPSR \ SPI Status Register
+ $80 constant SPSR_SPIF \ SPI Interrupt Flag
+ $40 constant SPSR_WCOL \ Write Collision Flag
+ $01 constant SPSR_SPI2X \ Double SPI Speed Bit
+&78 constant SPDR \ SPI Data Register
+\ PORTA
+&34 constant PORTA \ Port A Data Register
+&33 constant DDRA \ Port A Data Direction Register
+&32 constant PINA \ Port A Input Pins
+\ PORTB
+&37 constant PORTB \ Port B Data Register
+&36 constant DDRB \ Port B Data Direction Register
+&35 constant PINB \ Port B Input Pins
+\ PORTC
+&40 constant PORTC \ Port C Data Register
+&39 constant DDRC \ Port C Data Direction Register
+&38 constant PINC \ Port C Input Pins
+\ PORTD
+&43 constant PORTD \ Port D Data Register
+&42 constant DDRD \ Port D Data Direction Register
+&41 constant PIND \ Port D Input Pins
+\ ANALOG_COMPARATOR
+&123 constant ADCSRB \ ADC Control and Status Register B
+ $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer Enable
+&80 constant ACSR \ Analog Comparator Control And Status Register
+ $80 constant ACSR_ACD \ Analog Comparator Disable
+ $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
+ $20 constant ACSR_ACO \ Analog Compare Output
+ $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
+ $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
+ $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
+ $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
+&127 constant DIDR1 \ Digital Input Disable Register 1
+ $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
+ $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
+\ PORTE
+&46 constant PORTE \ Data Register, Port E
+&45 constant DDRE \ Data Direction Register, Port E
+&44 constant PINE \ Input Pins, Port E
+\ PORTF
+&49 constant PORTF \ Data Register, Port F
+&48 constant DDRF \ Data Direction Register, Port F
+&47 constant PINF \ Input Pins, Port F
+\ PORTG
+&52 constant PORTG \ Port G Data Register
+&51 constant DDRG \ Port G Data Direction Register
+&50 constant PING \ Port G Input Pins
+\ JTAG
+&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
+&85 constant MCUCR \ MCU Control Register
+ $80 constant MCUCR_JTD \ JTAG Interface Disable
+&84 constant MCUSR \ MCU Status Register
+ $10 constant MCUSR_JTRF \ JTAG Reset Flag
+\ EXTERNAL_INTERRUPT
+&105 constant EICRA \ External Interrupt Control Register A
+ $02 constant EICRA_ISC01 \ External Interrupt Sense Control 0 Bit 1
+ $01 constant EICRA_ISC00 \ External Interrupt Sense Control 0 Bit 0
+&61 constant EIMSK \ External Interrupt Mask Register
+ $F0 constant EIMSK_PCIE \ Pin Change Interrupt Enables
+ $01 constant EIMSK_INT0 \ External Interrupt Request 0 Enable
+&60 constant EIFR \ External Interrupt Flag Register
+ $F0 constant EIFR_PCIF \ Pin Change Interrupt Flags
+ $01 constant EIFR_INTF0 \ External Interrupt Flag 0
+&108 constant PCMSK1 \ Pin Change Mask Register 1
+ $01 constant PCMSK1_PCINT8 \ Pin Change Mask Register pin 8
+ $02 constant PCMSK1_PCINT9 \ Pin Change Mask Register pin 9
+ $04 constant PCMSK1_PCINT10 \ Pin Change Mask Register pin 10
+ $08 constant PCMSK1_PCINT11 \ Pin Change Mask Register pin 11
+ $10 constant PCMSK1_PCINT12 \ Pin Change Mask Register pin 12
+ $20 constant PCMSK1_PCINT13 \ Pin Change Mask Register pin 13
+ $40 constant PCMSK1_PCINT14 \ Pin Change Mask Register pin 14
+ $80 constant PCMSK1_PCINT15 \ Pin Change Mask Register pin 15
+&107 constant PCMSK0 \ Pin Change Mask Register 0
+ $01 constant PCMSK0_PCINT0 \ Pin Change Mask Register pin 0
+ $02 constant PCMSK0_PCINT1 \ Pin Change Mask Register pin 1
+ $04 constant PCMSK0_PCINT2 \ Pin Change Mask Register pin 2
+ $08 constant PCMSK0_PCINT3 \ Pin Change Mask Register pin 3
+ $10 constant PCMSK0_PCINT4 \ Pin Change Mask Register pin 4
+ $20 constant PCMSK0_PCINT5 \ Pin Change Mask Register pin 5
+ $40 constant PCMSK0_PCINT6 \ Pin Change Mask Register pin 6
+ $80 constant PCMSK0_PCINT7 \ Pin Change Mask Register pin 7
+\ USI
+&186 constant USIDR \ USI Data Register
+&185 constant USISR \ USI Status Register
+ $80 constant USISR_USISIF \ Start Condition Interrupt Flag
+ $40 constant USISR_USIOIF \ Counter Overflow Interrupt Flag
+ $20 constant USISR_USIPF \ Stop Condition Flag
+ $10 constant USISR_USIDC \ Data Output Collision
+ $0F constant USISR_USICNT \ USI Counter Value Bits
+&184 constant USICR \ USI Control Register
+ $80 constant USICR_USISIE \ Start Condition Interrupt Enable
+ $40 constant USICR_USIOIE \ Counter Overflow Interrupt Enable
+ $30 constant USICR_USIWM \ USI Wire Mode Bits
+ $0C constant USICR_USICS \ USI Clock Source Select Bits
+ $02 constant USICR_USICLK \ Clock Strobe
+ $01 constant USICR_USITC \ Toggle Clock Port Pin
+\ AD_CONVERTER
+&124 constant ADMUX \ The ADC multiplexer Selection Register
+ $C0 constant ADMUX_REFS \ Reference Selection Bits
+ $20 constant ADMUX_ADLAR \ Left Adjust Result
+ $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
+&122 constant ADCSRA \ The ADC Control and Status register
+ $80 constant ADCSRA_ADEN \ ADC Enable
+ $40 constant ADCSRA_ADSC \ ADC Start Conversion
+ $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
+ $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
+ $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
+ $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
+&120 constant ADC \ ADC Data Register Bytes
+&126 constant DIDR0 \ Digital Input Disable Register 0
+ $80 constant DIDR0_ADC7D \ ADC7 Digital input Disable
+ $40 constant DIDR0_ADC6D \ ADC6 Digital input Disable
+ $20 constant DIDR0_ADC5D \ ADC5 Digital input Disable
+ $10 constant DIDR0_ADC4D \ ADC4 Digital input Disable
+ $08 constant DIDR0_ADC3D \ ADC3 Digital input Disable
+ $04 constant DIDR0_ADC2D \ ADC2 Digital input Disable
+ $02 constant DIDR0_ADC1D \ ADC1 Digital input Disable
+ $01 constant DIDR0_ADC0D \ ADC0 Digital input Disable
+\ BOOT_LOAD
+&87 constant SPMCSR \ Store Program Memory Control Register
+ $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
+ $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
+ $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
+ $04 constant SPMCSR_PGWRT \ Page Write
+ $02 constant SPMCSR_PGERS \ Page Erase
+ $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
+\ USART0
+&198 constant UDR0 \ USART I/O Data Register
+&192 constant UCSR0A \ USART Control and Status Register A
+ $80 constant UCSR0A_RXC0 \ USART Receive Complete
+ $40 constant UCSR0A_TXC0 \ USART Transmit Complete
+ $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
+ $10 constant UCSR0A_FE0 \ Framing Error
+ $08 constant UCSR0A_DOR0 \ Data OverRun
+ $04 constant UCSR0A_UPE0 \ USART Parity Error
+ $02 constant UCSR0A_U2X0 \ Double the USART Transmission Speed
+ $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
+&193 constant UCSR0B \ USART Control and Status Register B
+ $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
+ $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
+ $20 constant UCSR0B_UDRIE0 \ USART Data Register Empty Interrupt Enable
+ $10 constant UCSR0B_RXEN0 \ Receiver Enable
+ $08 constant UCSR0B_TXEN0 \ Transmitter Enable
+ $04 constant UCSR0B_UCSZ02 \ Character Size
+ $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
+ $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
+&194 constant UCSR0C \ USART Control and Status Register C
+ $40 constant UCSR0C_UMSEL0 \ USART Mode Select
+ $30 constant UCSR0C_UPM0 \ Parity Mode Bits
+ $08 constant UCSR0C_USBS0 \ Stop Bit Select
+ $06 constant UCSR0C_UCSZ0 \ Character Size
+ $01 constant UCSR0C_UCPOL0 \ Clock Polarity
+&196 constant UBRR0 \ USART Baud Rate Register Bytes
+\ LCD
+&254 constant LCDDR18 \ LCD Data Register 18
+ $01 constant LCDDR18_SEG324 \ LCD memory bit segment
+ $02 constant LCDDR18_SEG325 \ LCD memory bit segment
+ $04 constant LCDDR18_SEG326 \ LCD memory bit segment
+ $08 constant LCDDR18_SEG327 \ LCD memory bit segment
+ $10 constant LCDDR18_SEG328 \ LCD memory bit segment
+ $20 constant LCDDR18_SEG329 \ LCD memory bit segment
+ $40 constant LCDDR18_SEG330 \ LCD memory bit segment
+ $80 constant LCDDR18_SEG331 \ LCD memory bit segment
+&253 constant LCDDR17 \ LCD Data Register 17
+ $01 constant LCDDR17_SEG316 \ LCD memory bit segment
+ $02 constant LCDDR17_SEG317 \ LCD memory bit segment
+ $04 constant LCDDR17_SEG318 \ LCD memory bit segment
+ $08 constant LCDDR17_SEG319 \ LCD memory bit segment
+ $10 constant LCDDR17_SEG320 \ LCD memory bit segment
+ $20 constant LCDDR17_SEG321 \ LCD memory bit segment
+ $40 constant LCDDR17_SEG322 \ LCD memory bit segment
+ $80 constant LCDDR17_SEG323 \ LCD memory bit segment
+&252 constant LCDDR16 \ LCD Data Register 16
+ $01 constant LCDDR16_SEG308 \ LCD memory bit segment
+ $02 constant LCDDR16_SEG309 \ LCD memory bit segment
+ $04 constant LCDDR16_SEG310 \ LCD memory bit segment
+ $08 constant LCDDR16_SEG311 \ LCD memory bit segment
+ $10 constant LCDDR16_SEG312 \ LCD memory bit segment
+ $20 constant LCDDR16_SEG313 \ LCD memory bit segment
+ $40 constant LCDDR16_SEG314 \ LCD memory bit segment
+ $80 constant LCDDR16_SEG315 \ LCD memory bit segment
+&251 constant LCDDR15 \ LCD Data Register 15
+ $01 constant LCDDR15_SEG300 \ LCD memory bit segment
+ $02 constant LCDDR15_SEG301 \ LCD memory bit segment
+ $04 constant LCDDR15_SEG302 \ LCD memory bit segment
+ $08 constant LCDDR15_SEG302 \ LCD memory bit segment
+ $10 constant LCDDR15_SEG304 \ LCD memory bit segment
+ $20 constant LCDDR15_SEG305 \ LCD memory bit segment
+ $40 constant LCDDR15_SEG306 \ LCD memory bit segment
+ $80 constant LCDDR15_SEG307 \ LCD memory bit segment
+&249 constant LCDDR13 \ LCD Data Register 13
+ $01 constant LCDDR13_SEG224 \ LCD memory bit segment
+ $02 constant LCDDR13_SEG225 \ LCD memory bit segment
+ $04 constant LCDDR13_SEG226 \ LCD memory bit segment
+ $08 constant LCDDR13_SEG227 \ LCD memory bit segment
+ $10 constant LCDDR13_SEG228 \ LCD memory bit segment
+ $20 constant LCDDR13_SEG229 \ LCD memory bit segment
+ $40 constant LCDDR13_SEG230 \ LCD memory bit segment
+ $80 constant LCDDR13_SEG231 \ LCD memory bit segment
+&248 constant LCDDR12 \ LCD Data Register 12
+ $01 constant LCDDR12_SEG216 \ LCD memory bit segment
+ $02 constant LCDDR12_SEG217 \ LCD memory bit segment
+ $04 constant LCDDR12_SEG218 \ LCD memory bit segment
+ $08 constant LCDDR12_SEG219 \ LCD memory bit segment
+ $10 constant LCDDR12_SEG220 \ LCD memory bit segment
+ $20 constant LCDDR12_SEG221 \ LCD memory bit segment
+ $40 constant LCDDR12_SEG222 \ LCD memory bit segment
+ $80 constant LCDDR12_SEG223 \ LCD memory bit segment
+&247 constant LCDDR11 \ LCD Data Register 11
+ $01 constant LCDDR11_SEG208 \ LCD memory bit segment
+ $02 constant LCDDR11_SEG209 \ LCD memory bit segment
+ $04 constant LCDDR11_SEG210 \ LCD memory bit segment
+ $08 constant LCDDR11_SEG211 \ LCD memory bit segment
+ $10 constant LCDDR11_SEG212 \ LCD memory bit segment
+ $20 constant LCDDR11_SEG213 \ LCD memory bit segment
+ $40 constant LCDDR11_SEG214 \ LCD memory bit segment
+ $80 constant LCDDR11_SEG215 \ LCD memory bit segment
+&246 constant LCDDR10 \ LCD Data Register 10
+ $01 constant LCDDR10_SEG200 \ LCD memory bit segment
+ $02 constant LCDDR10_SEG201 \ LCD memory bit segment
+ $04 constant LCDDR10_SEG202 \ LCD memory bit segment
+ $08 constant LCDDR10_SEG203 \ LCD memory bit segment
+ $10 constant LCDDR10_SEG204 \ LCD memory bit segment
+ $20 constant LCDDR10_SEG205 \ LCD memory bit segment
+ $40 constant LCDDR10_SEG206 \ LCD memory bit segment
+ $80 constant LCDDR10_SEG207 \ LCD memory bit segment
+&244 constant LCDDR8 \ LCD Data Register 8
+ $01 constant LCDDR8_SEG124 \ LCD memory bit segment
+ $02 constant LCDDR8_SEG125 \ LCD memory bit segment
+ $04 constant LCDDR8_SEG126 \ LCD memory bit segment
+ $08 constant LCDDR8_SEG127 \ LCD memory bit segment
+ $10 constant LCDDR8_SEG128 \ LCD memory bit segment
+ $20 constant LCDDR8_SEG129 \ LCD memory bit segment
+ $40 constant LCDDR8_SEG130 \ LCD memory bit segment
+ $80 constant LCDDR8_SEG131 \ LCD memory bit segment
+&243 constant LCDDR7 \ LCD Data Register 7
+ $01 constant LCDDR7_SEG116 \ LCD memory bit segment
+ $02 constant LCDDR7_SEG117 \ LCD memory bit segment
+ $04 constant LCDDR7_SEG118 \ LCD memory bit segment
+ $08 constant LCDDR7_SEG119 \ LCD memory bit segment
+ $10 constant LCDDR7_SEG120 \ LCD memory bit segment
+ $20 constant LCDDR7_SEG121 \ LCD memory bit segment
+ $40 constant LCDDR7_SEG122 \ LCD memory bit segment
+ $80 constant LCDDR7_SEG123 \ LCD memory bit segment
+&242 constant LCDDR6 \ LCD Data Register 6
+ $01 constant LCDDR6_SEG108 \ LCD memory bit segment
+ $02 constant LCDDR6_SEG109 \ LCD memory bit segment
+ $04 constant LCDDR6_SEG110 \ LCD memory bit segment
+ $08 constant LCDDR6_SEG111 \ LCD memory bit segment
+ $10 constant LCDDR6_SEG112 \ LCD memory bit segment
+ $20 constant LCDDR6_SEG113 \ LCD memory bit segment
+ $40 constant LCDDR6_SEG114 \ LCD memory bit segment
+ $80 constant LCDDR6_SEG115 \ LCD memory bit segment
+&241 constant LCDDR5 \ LCD Data Register 5
+ $01 constant LCDDR5_SEG100 \ LCD memory bit segment
+ $02 constant LCDDR5_SEG101 \ LCD memory bit segment
+ $04 constant LCDDR5_SEG102 \ LCD memory bit segment
+ $08 constant LCDDR5_SEG103 \ LCD memory bit segment
+ $10 constant LCDDR5_SEG104 \ LCD memory bit segment
+ $20 constant LCDDR5_SEG105 \ LCD memory bit segment
+ $40 constant LCDDR5_SEG106 \ LCD memory bit segment
+ $80 constant LCDDR5_SEG107 \ LCD memory bit segment
+&239 constant LCDDR3 \ LCD Data Register 3
+ $01 constant LCDDR3_SEG024 \ LCD memory bit segment
+ $02 constant LCDDR3_SEG025 \ LCD memory bit segment
+ $04 constant LCDDR3_SEG026 \ LCD memory bit segment
+ $08 constant LCDDR3_SEG027 \ LCD memory bit segment
+ $10 constant LCDDR3_SEG028 \ LCD memory bit segment
+ $20 constant LCDDR3_SEG029 \ LCD memory bit segment
+ $40 constant LCDDR3_SEG030 \ LCD memory bit segment
+ $80 constant LCDDR3_SEG031 \ LCD memory bit segment
+&238 constant LCDDR2 \ LCD Data Register 2
+ $01 constant LCDDR2_SEG016 \ LCD memory bit segment
+ $02 constant LCDDR2_SEG017 \ LCD memory bit segment
+ $04 constant LCDDR2_SEG018 \ LCD memory bit segment
+ $08 constant LCDDR2_SEG019 \ LCD memory bit segment
+ $10 constant LCDDR2_SEG020 \ LCD memory bit segment
+ $20 constant LCDDR2_SEG021 \ LCD memory bit segment
+ $40 constant LCDDR2_SEG022 \ LCD memory bit segment
+ $80 constant LCDDR2_SEG023 \ LCD memory bit segment
+&237 constant LCDDR1 \ LCD Data Register 1
+ $01 constant LCDDR1_SEG008 \ LCD memory bit segment
+ $02 constant LCDDR1_SEG009 \ LCD memory bit segment
+ $04 constant LCDDR1_SEG010 \ LCD memory bit segment
+ $08 constant LCDDR1_SEG011 \ LCD memory bit segment
+ $10 constant LCDDR1_SEG012 \ LCD memory bit segment
+ $20 constant LCDDR1_SEG013 \ LCD memory bit segment
+ $40 constant LCDDR1_SEG014 \ LCD memory bit segment
+ $80 constant LCDDR1_SEG015 \ LCD memory bit segment
+&236 constant LCDDR0 \ LCD Data Register 0
+ $01 constant LCDDR0_SEG000 \ LCD memory bit segment
+ $02 constant LCDDR0_SEG001 \ LCD memory bit segment
+ $04 constant LCDDR0_SEG002 \ LCD memory bit segment
+ $08 constant LCDDR0_SEG003 \ LCD memory bit segment
+ $10 constant LCDDR0_SEG004 \ LCD memory bit segment
+ $20 constant LCDDR0_SEG005 \ LCD memory bit segment
+ $40 constant LCDDR0_SEG006 \ LCD memory bit segment
+ $80 constant LCDDR0_SEG007 \ LCD memory bit segment
+&231 constant LCDCCR \ LCD Contrast Control Register
+ $E0 constant LCDCCR_LCDDC \
+ $10 constant LCDCCR_LCDMDT \ LCD Maximum Drive Time
+ $0F constant LCDCCR_LCDCC \ LCD Contrast Controls
+&230 constant LCDFRR \ LCD Frame Rate Register
+ $70 constant LCDFRR_LCDPS \ LCD Prescaler Selects
+ $07 constant LCDFRR_LCDCD \ LCD Clock Dividers
+&229 constant LCDCRB \ LCD Control and Status Register B
+ $80 constant LCDCRB_LCDCS \ LCD CLock Select
+ $40 constant LCDCRB_LCD2B \ LCD 1/2 Bias Select
+ $30 constant LCDCRB_LCDMUX \ LCD Mux Selects
+ $0F constant LCDCRB_LCDPM \ LCD Port Masks
+&228 constant LCDCRA \ LCD Control Register A
+ $80 constant LCDCRA_LCDEN \ LCD Enable
+ $40 constant LCDCRA_LCDAB \ LCD A or B waveform
+ $10 constant LCDCRA_LCDIF \ LCD Interrupt Flag
+ $08 constant LCDCRA_LCDIE \ LCD Interrupt Enable
+ $04 constant LCDCRA_LCDBD \ LCD Buffer Disable
+ $02 constant LCDCRA_LCDCCD \ LCD Contrast Control Disable
+ $01 constant LCDCRA_LCDBL \ LCD Blanking
+\ CPU
+&95 constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ $08 constant SREG_V \ Two's Complement Overflow Flag
+ $04 constant SREG_N \ Negative Flag
+ $02 constant SREG_Z \ Zero Flag
+ $01 constant SREG_C \ Carry Flag
+&93 constant SP \ Stack Pointer
+&102 constant OSCCAL \ Oscillator Calibration Value
+&97 constant CLKPR \ Clock Prescale Register
+ $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable
+ $0F constant CLKPR_CLKPS \ Clock Prescaler Select Bits
+&100 constant PRR \ Power Reduction Register
+ $10 constant PRR_PRLCD \ Power Reduction LCD
+ $08 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
+ $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
+ $02 constant PRR_PRUSART0 \ Power Reduction USART
+ $01 constant PRR_PRADC \ Power Reduction ADC
+&83 constant SMCR \ Sleep Mode Control Register
+ $0E constant SMCR_SM \ Sleep Mode Select bits
+ $01 constant SMCR_SE \ Sleep Enable
+&75 constant GPIOR2 \ General Purpose IO Register 2
+&74 constant GPIOR1 \ General Purpose IO Register 1
+&62 constant GPIOR0 \ General Purpose IO Register 0
+
+\ Interrupts
+&2 constant INT0Addr \ External Interrupt Request 0
+&4 constant PCINT0Addr \ Pin Change Interrupt Request 0
+&6 constant PCINT1Addr \ Pin Change Interrupt Request 1
+&8 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
+&10 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
+&12 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+&14 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
+&16 constant TIMER1_COMPBAddr \ Timer/Counter Compare Match B
+&18 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+&20 constant TIMER0_COMPAddr \ Timer/Counter0 Compare Match
+&22 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
+&24 constant SPI__STCAddr \ SPI Serial Transfer Complete
+&26 constant USART0__RXAddr \ USART0, Rx Complete
+&28 constant USART0__UDREAddr \ USART0 Data register Empty
+&30 constant USART0__TXAddr \ USART0, Tx Complete
+&32 constant USI_STARTAddr \ USI Start Condition
+&34 constant USI_OVERFLOWAddr \ USI Overflow
+&36 constant ANALOG_COMPAddr \ Analog Comparator
+&38 constant ADCAddr \ ADC Conversion Complete
+&40 constant EE_READYAddr \ EEPROM Ready
+&42 constant SPM_READYAddr \ Store Program Memory Read
+&44 constant LCDAddr \ LCD Start of Frame
diff --git a/amforth-6.5/avr8/devices/atmega329a/device.asm b/amforth-6.5/avr8/devices/atmega329a/device.asm
new file mode 100644
index 0000000..feb1134
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega329a/device.asm
@@ -0,0 +1,109 @@
+; Partname: ATmega329A
+; generated automatically, do not edit
+
+.nolist
+ .include "m329Adef.inc"
+.list
+
+.equ ramstart = 256
+.equ CELLSIZE = 2
+.macro readflashcell
+ lsl zl
+ rol zh
+ lpm @0, Z+
+ lpm @1, Z+
+.endmacro
+.macro writeflashcell
+ lsl zl
+ rol zh
+.endmacro
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_TIMER_COUNTER_2 = 0
+.set WANT_WATCHDOG = 0
+.set WANT_EEPROM = 0
+.set WANT_SPI = 0
+.set WANT_PORTA = 0
+.set WANT_PORTB = 0
+.set WANT_PORTC = 0
+.set WANT_PORTD = 0
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_PORTE = 0
+.set WANT_PORTF = 0
+.set WANT_PORTG = 0
+.set WANT_JTAG = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_USI = 0
+.set WANT_AD_CONVERTER = 0
+.set WANT_BOOT_LOAD = 0
+.set WANT_USART0 = 0
+.set WANT_LCD = 0
+.set WANT_CPU = 0
+.equ intvecsize = 2 ; please verify; flash size: 32768 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.org 2
+ rcall isr ; External Interrupt Request 0
+.org 4
+ rcall isr ; Pin Change Interrupt Request 0
+.org 6
+ rcall isr ; Pin Change Interrupt Request 1
+.org 8
+ rcall isr ; Timer/Counter2 Compare Match
+.org 10
+ rcall isr ; Timer/Counter2 Overflow
+.org 12
+ rcall isr ; Timer/Counter1 Capture Event
+.org 14
+ rcall isr ; Timer/Counter1 Compare Match A
+.org 16
+ rcall isr ; Timer/Counter Compare Match B
+.org 18
+ rcall isr ; Timer/Counter1 Overflow
+.org 20
+ rcall isr ; Timer/Counter0 Compare Match
+.org 22
+ rcall isr ; Timer/Counter0 Overflow
+.org 24
+ rcall isr ; SPI Serial Transfer Complete
+.org 26
+ rcall isr ; USART0, Rx Complete
+.org 28
+ rcall isr ; USART0 Data register Empty
+.org 30
+ rcall isr ; USART0, Tx Complete
+.org 32
+ rcall isr ; USI Start Condition
+.org 34
+ rcall isr ; USI Overflow
+.org 36
+ rcall isr ; Analog Comparator
+.org 38
+ rcall isr ; ADC Conversion Complete
+.org 40
+ rcall isr ; EEPROM Ready
+.org 42
+ rcall isr ; Store Program Memory Read
+.org 44
+ rcall isr ; LCD Start of Frame
+.equ INTVECTORS = 23
+.nooverlap
+
+; compatability layer (maybe empty)
+.equ EEPE = EEWE
+.equ EEMPE = EEMWE
+
+; controller data area, environment query mcu-info
+mcu_info:
+mcu_ramsize:
+ .dw 2048
+mcu_eepromsize:
+ .dw 1024
+mcu_maxdp:
+ .dw 28672
+mcu_numints:
+ .dw 23
+mcu_name:
+ .dw 10
+ .db "ATmega329A"
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega329a/device.inc b/amforth-6.5/avr8/devices/atmega329a/device.inc
new file mode 100644
index 0000000..ddbcf67
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega329a/device.inc
@@ -0,0 +1,1293 @@
+; Partname: ATmega329A
+; generated automatically, no not edit
+
+.if WANT_TIMER_COUNTER_0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Control Register
+VE_TCCR0A:
+ .dw $ff06
+ .db "TCCR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0A
+XT_TCCR0A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0A:
+ .dw 68
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw 70
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0A:
+ .dw $ff05
+ .db "OCR0A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0A
+XT_OCR0A:
+ .dw PFA_DOVARIABLE
+PFA_OCR0A:
+ .dw 71
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Mask Register
+VE_TIMSK0:
+ .dw $ff06
+ .db "TIMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK0
+XT_TIMSK0:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK0:
+ .dw 110
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Flag register
+VE_TIFR0:
+ .dw $ff05
+ .db "TIFR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR0
+XT_TIFR0:
+ .dw PFA_DOVARIABLE
+PFA_TIFR0:
+ .dw 53
+; ( -- addr ) System Constant
+; R( -- )
+; General Timer/Control Register
+VE_GTCCR:
+ .dw $ff05
+ .db "GTCCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GTCCR
+XT_GTCCR:
+ .dw PFA_DOVARIABLE
+PFA_GTCCR:
+ .dw 67
+
+.endif
+.if WANT_TIMER_COUNTER_1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw 128
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw 129
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter 1 Control Register C
+VE_TCCR1C:
+ .dw $ff06
+ .db "TCCR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1C
+XT_TCCR1C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1C:
+ .dw 130
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Bytes
+VE_TCNT1:
+ .dw $ff05
+ .db "TCNT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1
+XT_TCNT1:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1:
+ .dw 132
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register A Bytes
+VE_OCR1A:
+ .dw $ff05
+ .db "OCR1A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1A
+XT_OCR1A:
+ .dw PFA_DOVARIABLE
+PFA_OCR1A:
+ .dw 136
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register B Bytes
+VE_OCR1B:
+ .dw $ff05
+ .db "OCR1B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1B
+XT_OCR1B:
+ .dw PFA_DOVARIABLE
+PFA_OCR1B:
+ .dw 138
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Bytes
+VE_ICR1:
+ .dw $ff04
+ .db "ICR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1
+XT_ICR1:
+ .dw PFA_DOVARIABLE
+PFA_ICR1:
+ .dw 134
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Mask Register
+VE_TIMSK1:
+ .dw $ff06
+ .db "TIMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK1
+XT_TIMSK1:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK1:
+ .dw 111
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Flag register
+VE_TIFR1:
+ .dw $ff05
+ .db "TIFR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR1
+XT_TIFR1:
+ .dw PFA_DOVARIABLE
+PFA_TIFR1:
+ .dw 54
+
+.endif
+.if WANT_TIMER_COUNTER_2 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register
+VE_TCCR2A:
+ .dw $ff06
+ .db "TCCR2A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2A
+XT_TCCR2A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2A:
+ .dw 176
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2
+VE_TCNT2:
+ .dw $ff05
+ .db "TCNT2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT2
+XT_TCNT2:
+ .dw PFA_DOVARIABLE
+PFA_TCNT2:
+ .dw 178
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register
+VE_OCR2A:
+ .dw $ff05
+ .db "OCR2A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2A
+XT_OCR2A:
+ .dw PFA_DOVARIABLE
+PFA_OCR2A:
+ .dw 179
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Interrupt Mask register
+VE_TIMSK2:
+ .dw $ff06
+ .db "TIMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK2
+XT_TIMSK2:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK2:
+ .dw 112
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Interrupt Flag Register
+VE_TIFR2:
+ .dw $ff05
+ .db "TIFR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR2
+XT_TIFR2:
+ .dw PFA_DOVARIABLE
+PFA_TIFR2:
+ .dw 55
+; ( -- addr ) System Constant
+; R( -- )
+; Asynchronous Status Register
+VE_ASSR:
+ .dw $ff04
+ .db "ASSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ASSR
+XT_ASSR:
+ .dw PFA_DOVARIABLE
+PFA_ASSR:
+ .dw 182
+
+.endif
+.if WANT_WATCHDOG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCR:
+ .dw $ff05
+ .db "WDTCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCR
+XT_WDTCR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCR:
+ .dw 96
+
+.endif
+.if WANT_EEPROM == 1
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Read/Write Access Bytes
+VE_EEAR:
+ .dw $ff04
+ .db "EEAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEAR
+XT_EEAR:
+ .dw PFA_DOVARIABLE
+PFA_EEAR:
+ .dw 65
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw 64
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw 63
+
+.endif
+.if WANT_SPI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR:
+ .dw $ff04
+ .db "SPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR
+XT_SPCR:
+ .dw PFA_DOVARIABLE
+PFA_SPCR:
+ .dw 76
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR:
+ .dw $ff04
+ .db "SPSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR
+XT_SPSR:
+ .dw PFA_DOVARIABLE
+PFA_SPSR:
+ .dw 77
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR:
+ .dw $ff04
+ .db "SPDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR
+XT_SPDR:
+ .dw PFA_DOVARIABLE
+PFA_SPDR:
+ .dw 78
+
+.endif
+.if WANT_PORTA == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Register
+VE_PORTA:
+ .dw $ff05
+ .db "PORTA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTA
+XT_PORTA:
+ .dw PFA_DOVARIABLE
+PFA_PORTA:
+ .dw 34
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Direction Register
+VE_DDRA:
+ .dw $ff04
+ .db "DDRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRA
+XT_DDRA:
+ .dw PFA_DOVARIABLE
+PFA_DDRA:
+ .dw 33
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Input Pins
+VE_PINA:
+ .dw $ff04
+ .db "PINA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINA
+XT_PINA:
+ .dw PFA_DOVARIABLE
+PFA_PINA:
+ .dw 32
+
+.endif
+.if WANT_PORTB == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw 37
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw 36
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw 35
+
+.endif
+.if WANT_PORTC == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Register
+VE_PORTC:
+ .dw $ff05
+ .db "PORTC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTC
+XT_PORTC:
+ .dw PFA_DOVARIABLE
+PFA_PORTC:
+ .dw 40
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Direction Register
+VE_DDRC:
+ .dw $ff04
+ .db "DDRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRC
+XT_DDRC:
+ .dw PFA_DOVARIABLE
+PFA_DDRC:
+ .dw 39
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Input Pins
+VE_PINC:
+ .dw $ff04
+ .db "PINC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINC
+XT_PINC:
+ .dw PFA_DOVARIABLE
+PFA_PINC:
+ .dw 38
+
+.endif
+.if WANT_PORTD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw 43
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw 42
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw 41
+
+.endif
+.if WANT_ANALOG_COMPARATOR == 1
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Control and Status Register B
+VE_ADCSRB:
+ .dw $ff06
+ .db "ADCSRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRB
+XT_ADCSRB:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRB:
+ .dw 123
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Control And Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw 80
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 1
+VE_DIDR1:
+ .dw $ff05
+ .db "DIDR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR1
+XT_DIDR1:
+ .dw PFA_DOVARIABLE
+PFA_DIDR1:
+ .dw 127
+
+.endif
+.if WANT_PORTE == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port E
+VE_PORTE:
+ .dw $ff05
+ .db "PORTE",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTE
+XT_PORTE:
+ .dw PFA_DOVARIABLE
+PFA_PORTE:
+ .dw 46
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port E
+VE_DDRE:
+ .dw $ff04
+ .db "DDRE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRE
+XT_DDRE:
+ .dw PFA_DOVARIABLE
+PFA_DDRE:
+ .dw 45
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port E
+VE_PINE:
+ .dw $ff04
+ .db "PINE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINE
+XT_PINE:
+ .dw PFA_DOVARIABLE
+PFA_PINE:
+ .dw 44
+
+.endif
+.if WANT_PORTF == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port F
+VE_PORTF:
+ .dw $ff05
+ .db "PORTF",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTF
+XT_PORTF:
+ .dw PFA_DOVARIABLE
+PFA_PORTF:
+ .dw 49
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port F
+VE_DDRF:
+ .dw $ff04
+ .db "DDRF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRF
+XT_DDRF:
+ .dw PFA_DOVARIABLE
+PFA_DDRF:
+ .dw 48
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port F
+VE_PINF:
+ .dw $ff04
+ .db "PINF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINF
+XT_PINF:
+ .dw PFA_DOVARIABLE
+PFA_PINF:
+ .dw 47
+
+.endif
+.if WANT_PORTG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Data Register
+VE_PORTG:
+ .dw $ff05
+ .db "PORTG",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTG
+XT_PORTG:
+ .dw PFA_DOVARIABLE
+PFA_PORTG:
+ .dw 52
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Data Direction Register
+VE_DDRG:
+ .dw $ff04
+ .db "DDRG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRG
+XT_DDRG:
+ .dw PFA_DOVARIABLE
+PFA_DDRG:
+ .dw 51
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Input Pins
+VE_PING:
+ .dw $ff04
+ .db "PING"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PING
+XT_PING:
+ .dw PFA_DOVARIABLE
+PFA_PING:
+ .dw 50
+
+.endif
+.if WANT_JTAG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; On-Chip Debug Related Register in I/O Memory
+VE_OCDR:
+ .dw $ff04
+ .db "OCDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCDR
+XT_OCDR:
+ .dw PFA_DOVARIABLE
+PFA_OCDR:
+ .dw 81
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw 85
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Status Register
+VE_MCUSR:
+ .dw $ff05
+ .db "MCUSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUSR
+XT_MCUSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUSR:
+ .dw 84
+
+.endif
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register A
+VE_EICRA:
+ .dw $ff05
+ .db "EICRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRA
+XT_EICRA:
+ .dw PFA_DOVARIABLE
+PFA_EICRA:
+ .dw 105
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Mask Register
+VE_EIMSK:
+ .dw $ff05
+ .db "EIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIMSK
+XT_EIMSK:
+ .dw PFA_DOVARIABLE
+PFA_EIMSK:
+ .dw 61
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Flag Register
+VE_EIFR:
+ .dw $ff04
+ .db "EIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIFR
+XT_EIFR:
+ .dw PFA_DOVARIABLE
+PFA_EIFR:
+ .dw 60
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 1
+VE_PCMSK1:
+ .dw $ff06
+ .db "PCMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK1
+XT_PCMSK1:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK1:
+ .dw 108
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 0
+VE_PCMSK0:
+ .dw $ff06
+ .db "PCMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK0
+XT_PCMSK0:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK0:
+ .dw 107
+
+.endif
+.if WANT_USI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USI Data Register
+VE_USIDR:
+ .dw $ff05
+ .db "USIDR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USIDR
+XT_USIDR:
+ .dw PFA_DOVARIABLE
+PFA_USIDR:
+ .dw 186
+; ( -- addr ) System Constant
+; R( -- )
+; USI Status Register
+VE_USISR:
+ .dw $ff05
+ .db "USISR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USISR
+XT_USISR:
+ .dw PFA_DOVARIABLE
+PFA_USISR:
+ .dw 185
+; ( -- addr ) System Constant
+; R( -- )
+; USI Control Register
+VE_USICR:
+ .dw $ff05
+ .db "USICR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USICR
+XT_USICR:
+ .dw PFA_DOVARIABLE
+PFA_USICR:
+ .dw 184
+
+.endif
+.if WANT_AD_CONVERTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC multiplexer Selection Register
+VE_ADMUX:
+ .dw $ff05
+ .db "ADMUX",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADMUX
+XT_ADMUX:
+ .dw PFA_DOVARIABLE
+PFA_ADMUX:
+ .dw 124
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register
+VE_ADCSRA:
+ .dw $ff06
+ .db "ADCSRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRA
+XT_ADCSRA:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRA:
+ .dw 122
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register Bytes
+VE_ADC:
+ .dw $ff03
+ .db "ADC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADC
+XT_ADC:
+ .dw PFA_DOVARIABLE
+PFA_ADC:
+ .dw 120
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 0
+VE_DIDR0:
+ .dw $ff05
+ .db "DIDR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR0
+XT_DIDR0:
+ .dw PFA_DOVARIABLE
+PFA_DIDR0:
+ .dw 126
+
+.endif
+.if WANT_BOOT_LOAD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control Register
+VE_SPMCSR:
+ .dw $ff06
+ .db "SPMCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCSR
+XT_SPMCSR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCSR:
+ .dw 87
+
+.endif
+.if WANT_USART0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR0:
+ .dw $ff04
+ .db "UDR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR0
+XT_UDR0:
+ .dw PFA_DOVARIABLE
+PFA_UDR0:
+ .dw 198
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR0A:
+ .dw $ff06
+ .db "UCSR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0A
+XT_UCSR0A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0A:
+ .dw 192
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR0B:
+ .dw $ff06
+ .db "UCSR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0B
+XT_UCSR0B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0B:
+ .dw 193
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR0C:
+ .dw $ff06
+ .db "UCSR0C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0C
+XT_UCSR0C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0C:
+ .dw 194
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Bytes
+VE_UBRR0:
+ .dw $ff05
+ .db "UBRR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR0
+XT_UBRR0:
+ .dw PFA_DOVARIABLE
+PFA_UBRR0:
+ .dw 196
+
+.endif
+.if WANT_LCD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 18
+VE_LCDDR18:
+ .dw $ff07
+ .db "LCDDR18",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR18
+XT_LCDDR18:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR18:
+ .dw 254
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 17
+VE_LCDDR17:
+ .dw $ff07
+ .db "LCDDR17",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR17
+XT_LCDDR17:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR17:
+ .dw 253
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 16
+VE_LCDDR16:
+ .dw $ff07
+ .db "LCDDR16",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR16
+XT_LCDDR16:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR16:
+ .dw 252
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 15
+VE_LCDDR15:
+ .dw $ff07
+ .db "LCDDR15",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR15
+XT_LCDDR15:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR15:
+ .dw 251
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 13
+VE_LCDDR13:
+ .dw $ff07
+ .db "LCDDR13",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR13
+XT_LCDDR13:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR13:
+ .dw 249
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 12
+VE_LCDDR12:
+ .dw $ff07
+ .db "LCDDR12",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR12
+XT_LCDDR12:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR12:
+ .dw 248
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 11
+VE_LCDDR11:
+ .dw $ff07
+ .db "LCDDR11",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR11
+XT_LCDDR11:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR11:
+ .dw 247
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 10
+VE_LCDDR10:
+ .dw $ff07
+ .db "LCDDR10",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR10
+XT_LCDDR10:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR10:
+ .dw 246
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 8
+VE_LCDDR8:
+ .dw $ff06
+ .db "LCDDR8"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR8
+XT_LCDDR8:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR8:
+ .dw 244
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 7
+VE_LCDDR7:
+ .dw $ff06
+ .db "LCDDR7"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR7
+XT_LCDDR7:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR7:
+ .dw 243
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 6
+VE_LCDDR6:
+ .dw $ff06
+ .db "LCDDR6"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR6
+XT_LCDDR6:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR6:
+ .dw 242
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 5
+VE_LCDDR5:
+ .dw $ff06
+ .db "LCDDR5"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR5
+XT_LCDDR5:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR5:
+ .dw 241
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 3
+VE_LCDDR3:
+ .dw $ff06
+ .db "LCDDR3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR3
+XT_LCDDR3:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR3:
+ .dw 239
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 2
+VE_LCDDR2:
+ .dw $ff06
+ .db "LCDDR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR2
+XT_LCDDR2:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR2:
+ .dw 238
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 1
+VE_LCDDR1:
+ .dw $ff06
+ .db "LCDDR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR1
+XT_LCDDR1:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR1:
+ .dw 237
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 0
+VE_LCDDR0:
+ .dw $ff06
+ .db "LCDDR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR0
+XT_LCDDR0:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR0:
+ .dw 236
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Contrast Control Register
+VE_LCDCCR:
+ .dw $ff06
+ .db "LCDCCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDCCR
+XT_LCDCCR:
+ .dw PFA_DOVARIABLE
+PFA_LCDCCR:
+ .dw 231
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Frame Rate Register
+VE_LCDFRR:
+ .dw $ff06
+ .db "LCDFRR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDFRR
+XT_LCDFRR:
+ .dw PFA_DOVARIABLE
+PFA_LCDFRR:
+ .dw 230
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Control and Status Register B
+VE_LCDCRB:
+ .dw $ff06
+ .db "LCDCRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDCRB
+XT_LCDCRB:
+ .dw PFA_DOVARIABLE
+PFA_LCDCRB:
+ .dw 229
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Control Register A
+VE_LCDCRA:
+ .dw $ff06
+ .db "LCDCRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDCRA
+XT_LCDCRA:
+ .dw PFA_DOVARIABLE
+PFA_LCDCRA:
+ .dw 228
+
+.endif
+.if WANT_CPU == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw 95
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer
+VE_SP:
+ .dw $ff02
+ .db "SP"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SP
+XT_SP:
+ .dw PFA_DOVARIABLE
+PFA_SP:
+ .dw 93
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Calibration Value
+VE_OSCCAL:
+ .dw $ff06
+ .db "OSCCAL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSCCAL
+XT_OSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_OSCCAL:
+ .dw 102
+; ( -- addr ) System Constant
+; R( -- )
+; Clock Prescale Register
+VE_CLKPR:
+ .dw $ff05
+ .db "CLKPR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKPR
+XT_CLKPR:
+ .dw PFA_DOVARIABLE
+PFA_CLKPR:
+ .dw 97
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register
+VE_PRR:
+ .dw $ff03
+ .db "PRR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR
+XT_PRR:
+ .dw PFA_DOVARIABLE
+PFA_PRR:
+ .dw 100
+; ( -- addr ) System Constant
+; R( -- )
+; Sleep Mode Control Register
+VE_SMCR:
+ .dw $ff04
+ .db "SMCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SMCR
+XT_SMCR:
+ .dw PFA_DOVARIABLE
+PFA_SMCR:
+ .dw 83
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 2
+VE_GPIOR2:
+ .dw $ff06
+ .db "GPIOR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR2
+XT_GPIOR2:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR2:
+ .dw 75
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 1
+VE_GPIOR1:
+ .dw $ff06
+ .db "GPIOR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR1
+XT_GPIOR1:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR1:
+ .dw 74
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 0
+VE_GPIOR0:
+ .dw $ff06
+ .db "GPIOR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR0
+XT_GPIOR0:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR0:
+ .dw 62
+
+.endif
diff --git a/amforth-6.5/avr8/devices/atmega329a/device.py b/amforth-6.5/avr8/devices/atmega329a/device.py
new file mode 100644
index 0000000..df0c33c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega329a/device.py
@@ -0,0 +1,502 @@
+# Generated Automatically
+
+# Partname ATmega329A
+
+MCUREGS = {
+# Interrupt Vectors
+ 'INT0Addr' : '#2', # External Interrupt Request 0
+ 'PCINT0Addr' : '#4', # Pin Change Interrupt Request 0
+ 'PCINT1Addr' : '#6', # Pin Change Interrupt Request 1
+ 'TIMER2_COMPAddr' : '#8', # Timer/Counter2 Compare Match
+ 'TIMER2_OVFAddr' : '#10', # Timer/Counter2 Overflow
+ 'TIMER1_CAPTAddr' : '#12', # Timer/Counter1 Capture Event
+ 'TIMER1_COMPAAddr' : '#14', # Timer/Counter1 Compare Match A
+ 'TIMER1_COMPBAddr' : '#16', # Timer/Counter Compare Match B
+ 'TIMER1_OVFAddr' : '#18', # Timer/Counter1 Overflow
+ 'TIMER0_COMPAddr' : '#20', # Timer/Counter0 Compare Match
+ 'TIMER0_OVFAddr' : '#22', # Timer/Counter0 Overflow
+ 'SPI_STCAddr' : '#24', # SPI Serial Transfer Complete
+ 'USART0_RXAddr' : '#26', # USART0, Rx Complete
+ 'USART0_UDREAddr' : '#28', # USART0 Data register Empty
+ 'USART0_TXAddr' : '#30', # USART0, Tx Complete
+ 'USI_STARTAddr' : '#32', # USI Start Condition
+ 'USI_OVERFLOWAddr' : '#34', # USI Overflow
+ 'ANALOG_COMPAddr' : '#36', # Analog Comparator
+ 'ADCAddr' : '#38', # ADC Conversion Complete
+ 'EE_READYAddr' : '#40', # EEPROM Ready
+ 'SPM_READYAddr' : '#42', # Store Program Memory Read
+ 'LCDAddr' : '#44', # LCD Start of Frame
+
+# Module TIMER_COUNTER_0
+ 'TCCR0A' : '$44', # Timer/Counter0 Control Registe
+ 'TCCR0A_FOC0A': '$80', # Force Output Compare
+ 'TCCR0A_WGM00': '$40', # Waveform Generation Mode 0
+ 'TCCR0A_COM0A': '$30', # Compare Match Output Modes
+ 'TCCR0A_WGM01': '$8', # Waveform Generation Mode 1
+ 'TCCR0A_CS0': '$7', # Clock Selects
+ 'TCNT0' : '$46', # Timer/Counter0
+ 'OCR0A' : '$47', # Timer/Counter0 Output Compare
+ 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
+ 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
+ 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
+ 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
+ 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
+ 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Control Register
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSR310': '$1', # Prescaler Reset Timer/Counter1
+
+# Module TIMER_COUNTER_1
+ 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
+ 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
+ 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
+ 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
+ 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
+ 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
+ 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
+ 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
+ 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
+ 'TCCR1C' : '$82', # Timer/Counter 1 Control Regist
+ 'TCCR1C_FOC1A': '$80', # Force Output Compare 1A
+ 'TCCR1C_FOC1B': '$40', # Force Output Compare 1B
+ 'TCNT1' : '$84', # Timer/Counter1 Bytes
+ 'OCR1A' : '$88', # Timer/Counter1 Output Compare
+ 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
+ 'ICR1' : '$86', # Timer/Counter1 Input Capture R
+ 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
+ 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
+ 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
+ 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
+ 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
+ 'TIFR1' : '$36', # Timer/Counter1 Interrupt Flag
+ 'TIFR1_ICF1': '$20', # Input Capture Flag 1
+ 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
+ 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
+ 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
+
+# Module TIMER_COUNTER_2
+ 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
+ 'TCCR2A_FOC2A': '$80', # Force Output Compare A
+ 'TCCR2A_WGM20': '$40', # Waveform Generation Mode
+ 'TCCR2A_COM2A': '$30', # Compare Output Mode bits
+ 'TCCR2A_WGM21': '$8', # Waveform Generation Mode
+ 'TCCR2A_CS2': '$7', # Clock Select bits
+ 'TCNT2' : '$b2', # Timer/Counter2
+ 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
+ 'TIMSK2' : '$70', # Timer/Counter2 Interrupt Mask
+ 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
+ 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
+ 'TIFR2' : '$37', # Timer/Counter2 Interrupt Flag
+ 'TIFR2_OCF2A': '$2', # Timer/Counter2 Output Compare
+ 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_PSR2': '$2', # Prescaler Reset Timer/Counter2
+ 'ASSR' : '$b6', # Asynchronous Status Register
+ 'ASSR_EXCLK': '$10', # Enable External Clock Interrup
+ 'ASSR_AS2': '$8', # AS2: Asynchronous Timer/Counte
+ 'ASSR_TCN2UB': '$4', # TCN2UB: Timer/Counter2 Update
+ 'ASSR_OCR2UB': '$2', # Output Compare Register2 Updat
+ 'ASSR_TCR2UB': '$1', # TCR2UB: Timer/Counter Control
+
+# Module WATCHDOG
+ 'WDTCR' : '$60', # Watchdog Timer Control Registe
+ 'WDTCR_WDCE': '$10', # Watchdog Change Enable
+ 'WDTCR_WDE': '$8', # Watch Dog Enable
+ 'WDTCR_WDP': '$7', # Watch Dog Timer Prescaler bits
+
+# Module EEPROM
+ 'EEAR' : '$41', # EEPROM Read/Write Access Byte
+ 'EEDR' : '$40', # EEPROM Data Register
+ 'EECR' : '$3f', # EEPROM Control Register
+ 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
+ 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
+ 'EECR_EEWE': '$2', # EEPROM Write Enable
+ 'EECR_EERE': '$1', # EEPROM Read Enable
+
+# Module SPI
+ 'SPCR' : '$4c', # SPI Control Register
+ 'SPCR_SPIE': '$80', # SPI Interrupt Enable
+ 'SPCR_SPE': '$40', # SPI Enable
+ 'SPCR_DORD': '$20', # Data Order
+ 'SPCR_MSTR': '$10', # Master/Slave Select
+ 'SPCR_CPOL': '$8', # Clock polarity
+ 'SPCR_CPHA': '$4', # Clock Phase
+ 'SPCR_SPR': '$3', # SPI Clock Rate Selects
+ 'SPSR' : '$4d', # SPI Status Register
+ 'SPSR_SPIF': '$80', # SPI Interrupt Flag
+ 'SPSR_WCOL': '$40', # Write Collision Flag
+ 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
+ 'SPDR' : '$4e', # SPI Data Register
+
+# Module PORTA
+ 'PORTA' : '$22', # Port A Data Register
+ 'DDRA' : '$21', # Port A Data Direction Register
+ 'PINA' : '$20', # Port A Input Pins
+
+# Module PORTB
+ 'PORTB' : '$25', # Port B Data Register
+ 'DDRB' : '$24', # Port B Data Direction Register
+ 'PINB' : '$23', # Port B Input Pins
+
+# Module PORTC
+ 'PORTC' : '$28', # Port C Data Register
+ 'DDRC' : '$27', # Port C Data Direction Register
+ 'PINC' : '$26', # Port C Input Pins
+
+# Module PORTD
+ 'PORTD' : '$2b', # Port D Data Register
+ 'DDRD' : '$2a', # Port D Data Direction Register
+ 'PIND' : '$29', # Port D Input Pins
+
+# Module ANALOG_COMPARATOR
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
+ 'ACSR' : '$50', # Analog Comparator Control And
+ 'ACSR_ACD': '$80', # Analog Comparator Disable
+ 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
+ 'ACSR_ACO': '$20', # Analog Compare Output
+ 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
+ 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
+ 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
+ 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
+ 'DIDR1' : '$7f', # Digital Input Disable Register
+ 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
+ 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
+
+# Module PORTE
+ 'PORTE' : '$2e', # Data Register, Port E
+ 'DDRE' : '$2d', # Data Direction Register, Port
+ 'PINE' : '$2c', # Input Pins, Port E
+
+# Module PORTF
+ 'PORTF' : '$31', # Data Register, Port F
+ 'DDRF' : '$30', # Data Direction Register, Port
+ 'PINF' : '$2f', # Input Pins, Port F
+
+# Module PORTG
+ 'PORTG' : '$34', # Port G Data Register
+ 'DDRG' : '$33', # Port G Data Direction Register
+ 'PING' : '$32', # Port G Input Pins
+
+# Module JTAG
+ 'OCDR' : '$51', # On-Chip Debug Related Register
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_JTD': '$80', # JTAG Interface Disable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+
+# Module EXTERNAL_INTERRUPT
+ 'EICRA' : '$69', # External Interrupt Control Reg
+ 'EICRA_ISC01': '$2', # External Interrupt Sense Contr
+ 'EICRA_ISC00': '$1', # External Interrupt Sense Contr
+ 'EIMSK' : '$3d', # External Interrupt Mask Regist
+ 'EIMSK_PCIE': '$f0', # Pin Change Interrupt Enables
+ 'EIMSK_INT0': '$1', # External Interrupt Request 0 E
+ 'EIFR' : '$3c', # External Interrupt Flag Regist
+ 'EIFR_PCIF': '$f0', # Pin Change Interrupt Flags
+ 'EIFR_INTF0': '$1', # External Interrupt Flag 0
+ 'PCMSK1' : '$6c', # Pin Change Mask Register 1
+ 'PCMSK1_PCINT8': '$1', # Pin Change Mask Register pin 8
+ 'PCMSK1_PCINT9': '$2', # Pin Change Mask Register pin 9
+ 'PCMSK1_PCINT10': '$4', # Pin Change Mask Register pin 1
+ 'PCMSK1_PCINT11': '$8', # Pin Change Mask Register pin 1
+ 'PCMSK1_PCINT12': '$10', # Pin Change Mask Register pin 1
+ 'PCMSK1_PCINT13': '$20', # Pin Change Mask Register pin 1
+ 'PCMSK1_PCINT14': '$40', # Pin Change Mask Register pin 1
+ 'PCMSK1_PCINT15': '$80', # Pin Change Mask Register pin 1
+ 'PCMSK0' : '$6b', # Pin Change Mask Register 0
+ 'PCMSK0_PCINT0': '$1', # Pin Change Mask Register pin 0
+ 'PCMSK0_PCINT1': '$2', # Pin Change Mask Register pin 1
+ 'PCMSK0_PCINT2': '$4', # Pin Change Mask Register pin 2
+ 'PCMSK0_PCINT3': '$8', # Pin Change Mask Register pin 3
+ 'PCMSK0_PCINT4': '$10', # Pin Change Mask Register pin 4
+ 'PCMSK0_PCINT5': '$20', # Pin Change Mask Register pin 5
+ 'PCMSK0_PCINT6': '$40', # Pin Change Mask Register pin 6
+ 'PCMSK0_PCINT7': '$80', # Pin Change Mask Register pin 7
+
+# Module USI
+ 'USIDR' : '$ba', # USI Data Register
+ 'USISR' : '$b9', # USI Status Register
+ 'USISR_USISIF': '$80', # Start Condition Interrupt Flag
+ 'USISR_USIOIF': '$40', # Counter Overflow Interrupt Fla
+ 'USISR_USIPF': '$20', # Stop Condition Flag
+ 'USISR_USIDC': '$10', # Data Output Collision
+ 'USISR_USICNT': '$f', # USI Counter Value Bits
+ 'USICR' : '$b8', # USI Control Register
+ 'USICR_USISIE': '$80', # Start Condition Interrupt Enab
+ 'USICR_USIOIE': '$40', # Counter Overflow Interrupt Ena
+ 'USICR_USIWM': '$30', # USI Wire Mode Bits
+ 'USICR_USICS': '$c', # USI Clock Source Select Bits
+ 'USICR_USICLK': '$2', # Clock Strobe
+ 'USICR_USITC': '$1', # Toggle Clock Port Pin
+
+# Module AD_CONVERTER
+ 'ADMUX' : '$7c', # The ADC multiplexer Selection
+ 'ADMUX_REFS': '$c0', # Reference Selection Bits
+ 'ADMUX_ADLAR': '$20', # Left Adjust Result
+ 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
+ 'ADCSRA' : '$7a', # The ADC Control and Status reg
+ 'ADCSRA_ADEN': '$80', # ADC Enable
+ 'ADCSRA_ADSC': '$40', # ADC Start Conversion
+ 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
+ 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
+ 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
+ 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
+ 'ADC' : '$78', # ADC Data Register Bytes
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Sources
+ 'DIDR0' : '$7e', # Digital Input Disable Register
+ 'DIDR0_ADC7D': '$80', # ADC7 Digital input Disable
+ 'DIDR0_ADC6D': '$40', # ADC6 Digital input Disable
+ 'DIDR0_ADC5D': '$20', # ADC5 Digital input Disable
+ 'DIDR0_ADC4D': '$10', # ADC4 Digital input Disable
+ 'DIDR0_ADC3D': '$8', # ADC3 Digital input Disable
+ 'DIDR0_ADC2D': '$4', # ADC2 Digital input Disable
+ 'DIDR0_ADC1D': '$2', # ADC1 Digital input Disable
+ 'DIDR0_ADC0D': '$1', # ADC0 Digital input Disable
+
+# Module BOOT_LOAD
+ 'SPMCSR' : '$57', # Store Program Memory Control R
+ 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
+ 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
+ 'SPMCSR_RWWSRE': '$10', # Read While Write section read
+ 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
+ 'SPMCSR_PGWRT': '$4', # Page Write
+ 'SPMCSR_PGERS': '$2', # Page Erase
+ 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
+
+# Module USART0
+ 'UDR0' : '$c6', # USART I/O Data Register
+ 'UCSR0A' : '$c0', # USART Control and Status Regis
+ 'UCSR0A_RXC0': '$80', # USART Receive Complete
+ 'UCSR0A_TXC0': '$40', # USART Transmit Complete
+ 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
+ 'UCSR0A_FE0': '$10', # Framing Error
+ 'UCSR0A_DOR0': '$8', # Data OverRun
+ 'UCSR0A_UPE0': '$4', # USART Parity Error
+ 'UCSR0A_U2X0': '$2', # Double the USART Transmission
+ 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
+ 'UCSR0B' : '$c1', # USART Control and Status Regis
+ 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
+ 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
+ 'UCSR0B_UDRIE0': '$20', # USART Data Register Empty Inte
+ 'UCSR0B_RXEN0': '$10', # Receiver Enable
+ 'UCSR0B_TXEN0': '$8', # Transmitter Enable
+ 'UCSR0B_UCSZ02': '$4', # Character Size
+ 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
+ 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
+ 'UCSR0C' : '$c2', # USART Control and Status Regis
+ 'UCSR0C_UMSEL0': '$40', # USART Mode Select
+ 'UCSR0C_UPM0': '$30', # Parity Mode Bits
+ 'UCSR0C_USBS0': '$8', # Stop Bit Select
+ 'UCSR0C_UCSZ0': '$6', # Character Size
+ 'UCSR0C_UCPOL0': '$1', # Clock Polarity
+ 'UBRR0' : '$c4', # USART Baud Rate Register Byte
+
+# Module LCD
+ 'LCDDR18' : '$fe', # LCD Data Register 18
+ 'LCDDR18_SEG324': '$1', # LCD memory bit segment
+ 'LCDDR18_SEG325': '$2', # LCD memory bit segment
+ 'LCDDR18_SEG326': '$4', # LCD memory bit segment
+ 'LCDDR18_SEG327': '$8', # LCD memory bit segment
+ 'LCDDR18_SEG328': '$10', # LCD memory bit segment
+ 'LCDDR18_SEG329': '$20', # LCD memory bit segment
+ 'LCDDR18_SEG330': '$40', # LCD memory bit segment
+ 'LCDDR18_SEG331': '$80', # LCD memory bit segment
+ 'LCDDR17' : '$fd', # LCD Data Register 17
+ 'LCDDR17_SEG316': '$1', # LCD memory bit segment
+ 'LCDDR17_SEG317': '$2', # LCD memory bit segment
+ 'LCDDR17_SEG318': '$4', # LCD memory bit segment
+ 'LCDDR17_SEG319': '$8', # LCD memory bit segment
+ 'LCDDR17_SEG320': '$10', # LCD memory bit segment
+ 'LCDDR17_SEG321': '$20', # LCD memory bit segment
+ 'LCDDR17_SEG322': '$40', # LCD memory bit segment
+ 'LCDDR17_SEG323': '$80', # LCD memory bit segment
+ 'LCDDR16' : '$fc', # LCD Data Register 16
+ 'LCDDR16_SEG308': '$1', # LCD memory bit segment
+ 'LCDDR16_SEG309': '$2', # LCD memory bit segment
+ 'LCDDR16_SEG310': '$4', # LCD memory bit segment
+ 'LCDDR16_SEG311': '$8', # LCD memory bit segment
+ 'LCDDR16_SEG312': '$10', # LCD memory bit segment
+ 'LCDDR16_SEG313': '$20', # LCD memory bit segment
+ 'LCDDR16_SEG314': '$40', # LCD memory bit segment
+ 'LCDDR16_SEG315': '$80', # LCD memory bit segment
+ 'LCDDR15' : '$fb', # LCD Data Register 15
+ 'LCDDR15_SEG300': '$1', # LCD memory bit segment
+ 'LCDDR15_SEG301': '$2', # LCD memory bit segment
+ 'LCDDR15_SEG302': '$4', # LCD memory bit segment
+ 'LCDDR15_SEG302': '$8', # LCD memory bit segment
+ 'LCDDR15_SEG304': '$10', # LCD memory bit segment
+ 'LCDDR15_SEG305': '$20', # LCD memory bit segment
+ 'LCDDR15_SEG306': '$40', # LCD memory bit segment
+ 'LCDDR15_SEG307': '$80', # LCD memory bit segment
+ 'LCDDR13' : '$f9', # LCD Data Register 13
+ 'LCDDR13_SEG224': '$1', # LCD memory bit segment
+ 'LCDDR13_SEG225': '$2', # LCD memory bit segment
+ 'LCDDR13_SEG226': '$4', # LCD memory bit segment
+ 'LCDDR13_SEG227': '$8', # LCD memory bit segment
+ 'LCDDR13_SEG228': '$10', # LCD memory bit segment
+ 'LCDDR13_SEG229': '$20', # LCD memory bit segment
+ 'LCDDR13_SEG230': '$40', # LCD memory bit segment
+ 'LCDDR13_SEG231': '$80', # LCD memory bit segment
+ 'LCDDR12' : '$f8', # LCD Data Register 12
+ 'LCDDR12_SEG216': '$1', # LCD memory bit segment
+ 'LCDDR12_SEG217': '$2', # LCD memory bit segment
+ 'LCDDR12_SEG218': '$4', # LCD memory bit segment
+ 'LCDDR12_SEG219': '$8', # LCD memory bit segment
+ 'LCDDR12_SEG220': '$10', # LCD memory bit segment
+ 'LCDDR12_SEG221': '$20', # LCD memory bit segment
+ 'LCDDR12_SEG222': '$40', # LCD memory bit segment
+ 'LCDDR12_SEG223': '$80', # LCD memory bit segment
+ 'LCDDR11' : '$f7', # LCD Data Register 11
+ 'LCDDR11_SEG208': '$1', # LCD memory bit segment
+ 'LCDDR11_SEG209': '$2', # LCD memory bit segment
+ 'LCDDR11_SEG210': '$4', # LCD memory bit segment
+ 'LCDDR11_SEG211': '$8', # LCD memory bit segment
+ 'LCDDR11_SEG212': '$10', # LCD memory bit segment
+ 'LCDDR11_SEG213': '$20', # LCD memory bit segment
+ 'LCDDR11_SEG214': '$40', # LCD memory bit segment
+ 'LCDDR11_SEG215': '$80', # LCD memory bit segment
+ 'LCDDR10' : '$f6', # LCD Data Register 10
+ 'LCDDR10_SEG200': '$1', # LCD memory bit segment
+ 'LCDDR10_SEG201': '$2', # LCD memory bit segment
+ 'LCDDR10_SEG202': '$4', # LCD memory bit segment
+ 'LCDDR10_SEG203': '$8', # LCD memory bit segment
+ 'LCDDR10_SEG204': '$10', # LCD memory bit segment
+ 'LCDDR10_SEG205': '$20', # LCD memory bit segment
+ 'LCDDR10_SEG206': '$40', # LCD memory bit segment
+ 'LCDDR10_SEG207': '$80', # LCD memory bit segment
+ 'LCDDR8' : '$f4', # LCD Data Register 8
+ 'LCDDR8_SEG124': '$1', # LCD memory bit segment
+ 'LCDDR8_SEG125': '$2', # LCD memory bit segment
+ 'LCDDR8_SEG126': '$4', # LCD memory bit segment
+ 'LCDDR8_SEG127': '$8', # LCD memory bit segment
+ 'LCDDR8_SEG128': '$10', # LCD memory bit segment
+ 'LCDDR8_SEG129': '$20', # LCD memory bit segment
+ 'LCDDR8_SEG130': '$40', # LCD memory bit segment
+ 'LCDDR8_SEG131': '$80', # LCD memory bit segment
+ 'LCDDR7' : '$f3', # LCD Data Register 7
+ 'LCDDR7_SEG116': '$1', # LCD memory bit segment
+ 'LCDDR7_SEG117': '$2', # LCD memory bit segment
+ 'LCDDR7_SEG118': '$4', # LCD memory bit segment
+ 'LCDDR7_SEG119': '$8', # LCD memory bit segment
+ 'LCDDR7_SEG120': '$10', # LCD memory bit segment
+ 'LCDDR7_SEG121': '$20', # LCD memory bit segment
+ 'LCDDR7_SEG122': '$40', # LCD memory bit segment
+ 'LCDDR7_SEG123': '$80', # LCD memory bit segment
+ 'LCDDR6' : '$f2', # LCD Data Register 6
+ 'LCDDR6_SEG108': '$1', # LCD memory bit segment
+ 'LCDDR6_SEG109': '$2', # LCD memory bit segment
+ 'LCDDR6_SEG110': '$4', # LCD memory bit segment
+ 'LCDDR6_SEG111': '$8', # LCD memory bit segment
+ 'LCDDR6_SEG112': '$10', # LCD memory bit segment
+ 'LCDDR6_SEG113': '$20', # LCD memory bit segment
+ 'LCDDR6_SEG114': '$40', # LCD memory bit segment
+ 'LCDDR6_SEG115': '$80', # LCD memory bit segment
+ 'LCDDR5' : '$f1', # LCD Data Register 5
+ 'LCDDR5_SEG100': '$1', # LCD memory bit segment
+ 'LCDDR5_SEG101': '$2', # LCD memory bit segment
+ 'LCDDR5_SEG102': '$4', # LCD memory bit segment
+ 'LCDDR5_SEG103': '$8', # LCD memory bit segment
+ 'LCDDR5_SEG104': '$10', # LCD memory bit segment
+ 'LCDDR5_SEG105': '$20', # LCD memory bit segment
+ 'LCDDR5_SEG106': '$40', # LCD memory bit segment
+ 'LCDDR5_SEG107': '$80', # LCD memory bit segment
+ 'LCDDR3' : '$ef', # LCD Data Register 3
+ 'LCDDR3_SEG024': '$1', # LCD memory bit segment
+ 'LCDDR3_SEG025': '$2', # LCD memory bit segment
+ 'LCDDR3_SEG026': '$4', # LCD memory bit segment
+ 'LCDDR3_SEG027': '$8', # LCD memory bit segment
+ 'LCDDR3_SEG028': '$10', # LCD memory bit segment
+ 'LCDDR3_SEG029': '$20', # LCD memory bit segment
+ 'LCDDR3_SEG030': '$40', # LCD memory bit segment
+ 'LCDDR3_SEG031': '$80', # LCD memory bit segment
+ 'LCDDR2' : '$ee', # LCD Data Register 2
+ 'LCDDR2_SEG016': '$1', # LCD memory bit segment
+ 'LCDDR2_SEG017': '$2', # LCD memory bit segment
+ 'LCDDR2_SEG018': '$4', # LCD memory bit segment
+ 'LCDDR2_SEG019': '$8', # LCD memory bit segment
+ 'LCDDR2_SEG020': '$10', # LCD memory bit segment
+ 'LCDDR2_SEG021': '$20', # LCD memory bit segment
+ 'LCDDR2_SEG022': '$40', # LCD memory bit segment
+ 'LCDDR2_SEG023': '$80', # LCD memory bit segment
+ 'LCDDR1' : '$ed', # LCD Data Register 1
+ 'LCDDR1_SEG008': '$1', # LCD memory bit segment
+ 'LCDDR1_SEG009': '$2', # LCD memory bit segment
+ 'LCDDR1_SEG010': '$4', # LCD memory bit segment
+ 'LCDDR1_SEG011': '$8', # LCD memory bit segment
+ 'LCDDR1_SEG012': '$10', # LCD memory bit segment
+ 'LCDDR1_SEG013': '$20', # LCD memory bit segment
+ 'LCDDR1_SEG014': '$40', # LCD memory bit segment
+ 'LCDDR1_SEG015': '$80', # LCD memory bit segment
+ 'LCDDR0' : '$ec', # LCD Data Register 0
+ 'LCDDR0_SEG000': '$1', # LCD memory bit segment
+ 'LCDDR0_SEG001': '$2', # LCD memory bit segment
+ 'LCDDR0_SEG002': '$4', # LCD memory bit segment
+ 'LCDDR0_SEG003': '$8', # LCD memory bit segment
+ 'LCDDR0_SEG004': '$10', # LCD memory bit segment
+ 'LCDDR0_SEG005': '$20', # LCD memory bit segment
+ 'LCDDR0_SEG006': '$40', # LCD memory bit segment
+ 'LCDDR0_SEG007': '$80', # LCD memory bit segment
+ 'LCDCCR' : '$e7', # LCD Contrast Control Register
+ 'LCDCCR_LCDDC': '$e0', #
+ 'LCDCCR_LCDMDT': '$10', # LCD Maximum Drive Time
+ 'LCDCCR_LCDCC': '$f', # LCD Contrast Controls
+ 'LCDFRR' : '$e6', # LCD Frame Rate Register
+ 'LCDFRR_LCDPS': '$70', # LCD Prescaler Selects
+ 'LCDFRR_LCDCD': '$7', # LCD Clock Dividers
+ 'LCDCRB' : '$e5', # LCD Control and Status Registe
+ 'LCDCRB_LCDCS': '$80', # LCD CLock Select
+ 'LCDCRB_LCD2B': '$40', # LCD 1/2 Bias Select
+ 'LCDCRB_LCDMUX': '$30', # LCD Mux Selects
+ 'LCDCRB_LCDPM': '$f', # LCD Port Masks
+ 'LCDCRA' : '$e4', # LCD Control Register A
+ 'LCDCRA_LCDEN': '$80', # LCD Enable
+ 'LCDCRA_LCDAB': '$40', # LCD A or B waveform
+ 'LCDCRA_LCDIF': '$10', # LCD Interrupt Flag
+ 'LCDCRA_LCDIE': '$8', # LCD Interrupt Enable
+ 'LCDCRA_LCDBD': '$4', # LCD Buffer Disable
+ 'LCDCRA_LCDCCD': '$2', # LCD Contrast Control Disable
+ 'LCDCRA_LCDBL': '$1', # LCD Blanking
+
+# Module CPU
+ 'SREG' : '$5f', # Status Register
+ 'SREG_I': '$80', # Global Interrupt Enable
+ 'SREG_T': '$40', # Bit Copy Storage
+ 'SREG_H': '$20', # Half Carry Flag
+ 'SREG_S': '$10', # Sign Bit
+ 'SREG_V': '$8', # Two's Complement Overflow Flag
+ 'SREG_N': '$4', # Negative Flag
+ 'SREG_Z': '$2', # Zero Flag
+ 'SREG_C': '$1', # Carry Flag
+ 'SP' : '$5d', # Stack Pointer
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_JTD': '$80', # JTAG Interface Disable
+ 'MCUCR_PUD': '$10', # Pull-up disable
+ 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
+ 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+ 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
+ 'MCUSR_BORF': '$4', # Brown-out Reset Flag
+ 'MCUSR_EXTRF': '$2', # External Reset Flag
+ 'MCUSR_PORF': '$1', # Power-on reset flag
+ 'OSCCAL' : '$66', # Oscillator Calibration Value
+ 'CLKPR' : '$61', # Clock Prescale Register
+ 'CLKPR_CLKPCE': '$80', # Clock Prescaler Change Enable
+ 'CLKPR_CLKPS': '$f', # Clock Prescaler Select Bits
+ 'PRR' : '$64', # Power Reduction Register
+ 'PRR_PRLCD': '$10', # Power Reduction LCD
+ 'PRR_PRTIM1': '$8', # Power Reduction Timer/Counter1
+ 'PRR_PRSPI': '$4', # Power Reduction Serial Periphe
+ 'PRR_PRUSART0': '$2', # Power Reduction USART
+ 'PRR_PRADC': '$1', # Power Reduction ADC
+ 'SMCR' : '$53', # Sleep Mode Control Register
+ 'SMCR_SM': '$e', # Sleep Mode Select bits
+ 'SMCR_SE': '$1', # Sleep Enable
+ 'GPIOR2' : '$4b', # General Purpose IO Register 2
+ 'GPIOR1' : '$4a', # General Purpose IO Register 1
+ 'GPIOR0' : '$3e', # General Purpose IO Register 0
+
+ '__amforth_dummy':'0'
+}
diff --git a/amforth-6.5/avr8/devices/atmega329a/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega329a/words/no-jtag.asm
new file mode 100644
index 0000000..352a4bb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega329a/words/no-jtag.asm
@@ -0,0 +1,14 @@
+; ( -- )
+; ( -- )
+; MCU
+; disable jtag at runtime
+VE_NOJTAG:
+ .dw $FF05
+ .db "-jtag",0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOJTAG
+XT_NOJTAG:
+ .dw PFA_NOJTAG
+PFA_NOJTAG:
+
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega329a/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega329a/words/no-wdt.asm
new file mode 100644
index 0000000..4a12261
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega329a/words/no-wdt.asm
@@ -0,0 +1,22 @@
+; ( -- )
+; MCU
+; disable watch dog timer at runtime
+VE_NOWDT:
+ .dw $ff04
+ .db "-wdt"
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOWDT
+XT_NOWDT:
+ .dw PFA_NOWDT
+PFA_NOWDT:
+
+; Reset WDT
+ wdr
+; Write logical one to WDTOE and WDE
+ in_ temp1, WDTCR
+ ori temp1, (1<<WDTOE)|(1<<WDE)
+ out WDTCR, temp1
+; Turn off WDT
+ ldi temp1, (0<<WDE)
+ out_ WDTCR, temp1
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega329a/words/sleep.asm b/amforth-6.5/avr8/devices/atmega329a/words/sleep.asm
new file mode 100644
index 0000000..256249c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega329a/words/sleep.asm
@@ -0,0 +1,19 @@
+; ( mode -- )
+; MCU
+; put the controller into the specified sleep mode
+VE_SLEEP:
+ .dw $ff05
+ .db "sleep", 0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_SLEEP
+XT_SLEEP:
+ .dw PFA_SLEEP
+PFA_SLEEP:
+ andi tosl, 7 ; leave only legal mode bits
+ lsl tosl ; move to correct location (bits 3-1)
+ ori tosl, 1 ; set the SE bit
+ out_ SMCR, tosl ; set the sleep config
+ sleep ; nighty-night
+ out_ SMCR, zerol ; 0 protects against accidental sleeps
+ loadtos ; pop argument from stack
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega329p/atmega329p.frt b/amforth-6.5/avr8/devices/atmega329p/atmega329p.frt
new file mode 100644
index 0000000..b5bdf7d
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega329p/atmega329p.frt
@@ -0,0 +1,461 @@
+\ Partname: ATmega329P
+\ generated automatically
+
+\ TIMER_COUNTER_0
+&68 constant TCCR0A \ Timer/Counter0 Control Register
+ $80 constant TCCR0A_FOC0A \ Force Output Compare
+ $40 constant TCCR0A_WGM00 \ Waveform Generation Mode 0
+ $30 constant TCCR0A_COM0A \ Compare Match Output Modes
+ $08 constant TCCR0A_WGM01 \ Waveform Generation Mode 1
+ $07 constant TCCR0A_CS0 \ Clock Selects
+&70 constant TCNT0 \ Timer/Counter0
+&71 constant OCR0A \ Timer/Counter0 Output Compare Register
+&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
+ $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match Interrupt Enable
+ $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
+&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
+ $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0
+ $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
+&67 constant GTCCR \ General Timer/Control Register
+ $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
+ $01 constant GTCCR_PSR310 \ Prescaler Reset Timer/Counter1 and Timer/Counter0
+\ TIMER_COUNTER_1
+&128 constant TCCR1A \ Timer/Counter1 Control Register A
+ $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
+ $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
+ $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
+&129 constant TCCR1B \ Timer/Counter1 Control Register B
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
+ $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
+&130 constant TCCR1C \ Timer/Counter 1 Control Register C
+ $80 constant TCCR1C_FOC1A \ Force Output Compare 1A
+ $40 constant TCCR1C_FOC1B \ Force Output Compare 1B
+&132 constant TCNT1 \ Timer/Counter1 Bytes
+&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
+&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
+&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
+&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
+ $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
+ $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
+ $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
+ $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
+&54 constant TIFR1 \ Timer/Counter1 Interrupt Flag register
+ $20 constant TIFR1_ICF1 \ Input Capture Flag 1
+ $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
+ $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
+ $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
+\ TIMER_COUNTER_2
+&176 constant TCCR2A \ Timer/Counter2 Control Register
+ $80 constant TCCR2A_FOC2A \ Force Output Compare A
+ $40 constant TCCR2A_WGM20 \ Waveform Generation Mode
+ $30 constant TCCR2A_COM2A \ Compare Output Mode bits
+ $08 constant TCCR2A_WGM21 \ Waveform Generation Mode
+ $07 constant TCCR2A_CS2 \ Clock Select bits
+&178 constant TCNT2 \ Timer/Counter2
+&179 constant OCR2A \ Timer/Counter2 Output Compare Register
+&112 constant TIMSK2 \ Timer/Counter2 Interrupt Mask register
+ $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match Interrupt Enable
+ $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
+&55 constant TIFR2 \ Timer/Counter2 Interrupt Flag Register
+ $02 constant TIFR2_OCF2A \ Timer/Counter2 Output Compare Flag 2
+ $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
+&182 constant ASSR \ Asynchronous Status Register
+ $10 constant ASSR_EXCLK \ Enable External Clock Interrupt
+ $08 constant ASSR_AS2 \ AS2: Asynchronous Timer/Counter2
+ $04 constant ASSR_TCN2UB \ TCN2UB: Timer/Counter2 Update Busy
+ $02 constant ASSR_OCR2UB \ Output Compare Register2 Update Busy
+ $01 constant ASSR_TCR2UB \ TCR2UB: Timer/Counter Control Register2 Update Busy
+\ WATCHDOG
+&96 constant WDTCR \ Watchdog Timer Control Register
+ $10 constant WDTCR_WDCE \ Watchdog Change Enable
+ $08 constant WDTCR_WDE \ Watch Dog Enable
+ $07 constant WDTCR_WDP \ Watch Dog Timer Prescaler bits
+\ EEPROM
+&65 constant EEAR \ EEPROM Read/Write Access Bytes
+&64 constant EEDR \ EEPROM Data Register
+&63 constant EECR \ EEPROM Control Register
+ $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
+ $04 constant EECR_EEMWE \ EEPROM Master Write Enable
+ $02 constant EECR_EEWE \ EEPROM Write Enable
+ $01 constant EECR_EERE \ EEPROM Read Enable
+\ SPI
+&76 constant SPCR \ SPI Control Register
+ $80 constant SPCR_SPIE \ SPI Interrupt Enable
+ $40 constant SPCR_SPE \ SPI Enable
+ $20 constant SPCR_DORD \ Data Order
+ $10 constant SPCR_MSTR \ Master/Slave Select
+ $08 constant SPCR_CPOL \ Clock polarity
+ $04 constant SPCR_CPHA \ Clock Phase
+ $03 constant SPCR_SPR \ SPI Clock Rate Selects
+&77 constant SPSR \ SPI Status Register
+ $80 constant SPSR_SPIF \ SPI Interrupt Flag
+ $40 constant SPSR_WCOL \ Write Collision Flag
+ $01 constant SPSR_SPI2X \ Double SPI Speed Bit
+&78 constant SPDR \ SPI Data Register
+\ PORTA
+&34 constant PORTA \ Port A Data Register
+&33 constant DDRA \ Port A Data Direction Register
+&32 constant PINA \ Port A Input Pins
+\ PORTB
+&37 constant PORTB \ Port B Data Register
+&36 constant DDRB \ Port B Data Direction Register
+&35 constant PINB \ Port B Input Pins
+\ PORTC
+&40 constant PORTC \ Port C Data Register
+&39 constant DDRC \ Port C Data Direction Register
+&38 constant PINC \ Port C Input Pins
+\ PORTD
+&43 constant PORTD \ Port D Data Register
+&42 constant DDRD \ Port D Data Direction Register
+&41 constant PIND \ Port D Input Pins
+\ ANALOG_COMPARATOR
+&123 constant ADCSRB \ ADC Control and Status Register B
+ $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer Enable
+&80 constant ACSR \ Analog Comparator Control And Status Register
+ $80 constant ACSR_ACD \ Analog Comparator Disable
+ $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
+ $20 constant ACSR_ACO \ Analog Compare Output
+ $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
+ $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
+ $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
+ $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
+&127 constant DIDR1 \ Digital Input Disable Register 1
+ $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
+ $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
+\ PORTE
+&46 constant PORTE \ Data Register, Port E
+&45 constant DDRE \ Data Direction Register, Port E
+&44 constant PINE \ Input Pins, Port E
+\ PORTF
+&49 constant PORTF \ Data Register, Port F
+&48 constant DDRF \ Data Direction Register, Port F
+&47 constant PINF \ Input Pins, Port F
+\ PORTG
+&52 constant PORTG \ Port G Data Register
+&51 constant DDRG \ Port G Data Direction Register
+&50 constant PING \ Port G Input Pins
+\ JTAG
+&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
+&85 constant MCUCR \ MCU Control Register
+ $80 constant MCUCR_JTD \ JTAG Interface Disable
+&84 constant MCUSR \ MCU Status Register
+ $10 constant MCUSR_JTRF \ JTAG Reset Flag
+\ EXTERNAL_INTERRUPT
+&105 constant EICRA \ External Interrupt Control Register A
+ $02 constant EICRA_ISC01 \ External Interrupt Sense Control 0 Bit 1
+ $01 constant EICRA_ISC00 \ External Interrupt Sense Control 0 Bit 0
+&61 constant EIMSK \ External Interrupt Mask Register
+ $F0 constant EIMSK_PCIE \ Pin Change Interrupt Enables
+ $01 constant EIMSK_INT0 \ External Interrupt Request 0 Enable
+&60 constant EIFR \ External Interrupt Flag Register
+ $F0 constant EIFR_PCIF \ Pin Change Interrupt Flags
+ $01 constant EIFR_INTF0 \ External Interrupt Flag 0
+&108 constant PCMSK1 \ Pin Change Mask Register 1
+ $01 constant PCMSK1_PCINT8 \ Pin Change Mask Register pin 8
+ $02 constant PCMSK1_PCINT9 \ Pin Change Mask Register pin 9
+ $04 constant PCMSK1_PCINT10 \ Pin Change Mask Register pin 10
+ $08 constant PCMSK1_PCINT11 \ Pin Change Mask Register pin 11
+ $10 constant PCMSK1_PCINT12 \ Pin Change Mask Register pin 12
+ $20 constant PCMSK1_PCINT13 \ Pin Change Mask Register pin 13
+ $40 constant PCMSK1_PCINT14 \ Pin Change Mask Register pin 14
+ $80 constant PCMSK1_PCINT15 \ Pin Change Mask Register pin 15
+&107 constant PCMSK0 \ Pin Change Mask Register 0
+ $01 constant PCMSK0_PCINT0 \ Pin Change Mask Register pin 0
+ $02 constant PCMSK0_PCINT1 \ Pin Change Mask Register pin 1
+ $04 constant PCMSK0_PCINT2 \ Pin Change Mask Register pin 2
+ $08 constant PCMSK0_PCINT3 \ Pin Change Mask Register pin 3
+ $10 constant PCMSK0_PCINT4 \ Pin Change Mask Register pin 4
+ $20 constant PCMSK0_PCINT5 \ Pin Change Mask Register pin 5
+ $40 constant PCMSK0_PCINT6 \ Pin Change Mask Register pin 6
+ $80 constant PCMSK0_PCINT7 \ Pin Change Mask Register pin 7
+\ USI
+&186 constant USIDR \ USI Data Register
+&185 constant USISR \ USI Status Register
+ $80 constant USISR_USISIF \ Start Condition Interrupt Flag
+ $40 constant USISR_USIOIF \ Counter Overflow Interrupt Flag
+ $20 constant USISR_USIPF \ Stop Condition Flag
+ $10 constant USISR_USIDC \ Data Output Collision
+ $0F constant USISR_USICNT \ USI Counter Value Bits
+&184 constant USICR \ USI Control Register
+ $80 constant USICR_USISIE \ Start Condition Interrupt Enable
+ $40 constant USICR_USIOIE \ Counter Overflow Interrupt Enable
+ $30 constant USICR_USIWM \ USI Wire Mode Bits
+ $0C constant USICR_USICS \ USI Clock Source Select Bits
+ $02 constant USICR_USICLK \ Clock Strobe
+ $01 constant USICR_USITC \ Toggle Clock Port Pin
+\ AD_CONVERTER
+&124 constant ADMUX \ The ADC multiplexer Selection Register
+ $C0 constant ADMUX_REFS \ Reference Selection Bits
+ $20 constant ADMUX_ADLAR \ Left Adjust Result
+ $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
+&122 constant ADCSRA \ The ADC Control and Status register
+ $80 constant ADCSRA_ADEN \ ADC Enable
+ $40 constant ADCSRA_ADSC \ ADC Start Conversion
+ $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
+ $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
+ $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
+ $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
+&120 constant ADC \ ADC Data Register Bytes
+&126 constant DIDR0 \ Digital Input Disable Register 0
+ $80 constant DIDR0_ADC7D \ ADC7 Digital input Disable
+ $40 constant DIDR0_ADC6D \ ADC6 Digital input Disable
+ $20 constant DIDR0_ADC5D \ ADC5 Digital input Disable
+ $10 constant DIDR0_ADC4D \ ADC4 Digital input Disable
+ $08 constant DIDR0_ADC3D \ ADC3 Digital input Disable
+ $04 constant DIDR0_ADC2D \ ADC2 Digital input Disable
+ $02 constant DIDR0_ADC1D \ ADC1 Digital input Disable
+ $01 constant DIDR0_ADC0D \ ADC0 Digital input Disable
+\ BOOT_LOAD
+&87 constant SPMCSR \ Store Program Memory Control Register
+ $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
+ $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
+ $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
+ $04 constant SPMCSR_PGWRT \ Page Write
+ $02 constant SPMCSR_PGERS \ Page Erase
+ $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
+\ USART0
+&198 constant UDR0 \ USART I/O Data Register
+&192 constant UCSR0A \ USART Control and Status Register A
+ $80 constant UCSR0A_RXC0 \ USART Receive Complete
+ $40 constant UCSR0A_TXC0 \ USART Transmit Complete
+ $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
+ $10 constant UCSR0A_FE0 \ Framing Error
+ $08 constant UCSR0A_DOR0 \ Data OverRun
+ $04 constant UCSR0A_UPE0 \ USART Parity Error
+ $02 constant UCSR0A_U2X0 \ Double the USART Transmission Speed
+ $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
+&193 constant UCSR0B \ USART Control and Status Register B
+ $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
+ $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
+ $20 constant UCSR0B_UDRIE0 \ USART Data Register Empty Interrupt Enable
+ $10 constant UCSR0B_RXEN0 \ Receiver Enable
+ $08 constant UCSR0B_TXEN0 \ Transmitter Enable
+ $04 constant UCSR0B_UCSZ02 \ Character Size
+ $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
+ $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
+&194 constant UCSR0C \ USART Control and Status Register C
+ $40 constant UCSR0C_UMSEL0 \ USART Mode Select
+ $30 constant UCSR0C_UPM0 \ Parity Mode Bits
+ $08 constant UCSR0C_USBS0 \ Stop Bit Select
+ $06 constant UCSR0C_UCSZ0 \ Character Size
+ $01 constant UCSR0C_UCPOL0 \ Clock Polarity
+&196 constant UBRR0 \ USART Baud Rate Register Bytes
+\ LCD
+&254 constant LCDDR18 \ LCD Data Register 18
+ $01 constant LCDDR18_SEG324 \ LCD memory bit segment
+ $02 constant LCDDR18_SEG325 \ LCD memory bit segment
+ $04 constant LCDDR18_SEG326 \ LCD memory bit segment
+ $08 constant LCDDR18_SEG327 \ LCD memory bit segment
+ $10 constant LCDDR18_SEG328 \ LCD memory bit segment
+ $20 constant LCDDR18_SEG329 \ LCD memory bit segment
+ $40 constant LCDDR18_SEG330 \ LCD memory bit segment
+ $80 constant LCDDR18_SEG331 \ LCD memory bit segment
+&253 constant LCDDR17 \ LCD Data Register 17
+ $01 constant LCDDR17_SEG316 \ LCD memory bit segment
+ $02 constant LCDDR17_SEG317 \ LCD memory bit segment
+ $04 constant LCDDR17_SEG318 \ LCD memory bit segment
+ $08 constant LCDDR17_SEG319 \ LCD memory bit segment
+ $10 constant LCDDR17_SEG320 \ LCD memory bit segment
+ $20 constant LCDDR17_SEG321 \ LCD memory bit segment
+ $40 constant LCDDR17_SEG322 \ LCD memory bit segment
+ $80 constant LCDDR17_SEG323 \ LCD memory bit segment
+&252 constant LCDDR16 \ LCD Data Register 16
+ $01 constant LCDDR16_SEG308 \ LCD memory bit segment
+ $02 constant LCDDR16_SEG309 \ LCD memory bit segment
+ $04 constant LCDDR16_SEG310 \ LCD memory bit segment
+ $08 constant LCDDR16_SEG311 \ LCD memory bit segment
+ $10 constant LCDDR16_SEG312 \ LCD memory bit segment
+ $20 constant LCDDR16_SEG313 \ LCD memory bit segment
+ $40 constant LCDDR16_SEG314 \ LCD memory bit segment
+ $80 constant LCDDR16_SEG315 \ LCD memory bit segment
+&251 constant LCDDR15 \ LCD Data Register 15
+ $01 constant LCDDR15_SEG300 \ LCD memory bit segment
+ $02 constant LCDDR15_SEG301 \ LCD memory bit segment
+ $04 constant LCDDR15_SEG302 \ LCD memory bit segment
+ $08 constant LCDDR15_SEG302 \ LCD memory bit segment
+ $10 constant LCDDR15_SEG304 \ LCD memory bit segment
+ $20 constant LCDDR15_SEG305 \ LCD memory bit segment
+ $40 constant LCDDR15_SEG306 \ LCD memory bit segment
+ $80 constant LCDDR15_SEG307 \ LCD memory bit segment
+&249 constant LCDDR13 \ LCD Data Register 13
+ $01 constant LCDDR13_SEG224 \ LCD memory bit segment
+ $02 constant LCDDR13_SEG225 \ LCD memory bit segment
+ $04 constant LCDDR13_SEG226 \ LCD memory bit segment
+ $08 constant LCDDR13_SEG227 \ LCD memory bit segment
+ $10 constant LCDDR13_SEG228 \ LCD memory bit segment
+ $20 constant LCDDR13_SEG229 \ LCD memory bit segment
+ $40 constant LCDDR13_SEG230 \ LCD memory bit segment
+ $80 constant LCDDR13_SEG231 \ LCD memory bit segment
+&248 constant LCDDR12 \ LCD Data Register 12
+ $01 constant LCDDR12_SEG216 \ LCD memory bit segment
+ $02 constant LCDDR12_SEG217 \ LCD memory bit segment
+ $04 constant LCDDR12_SEG218 \ LCD memory bit segment
+ $08 constant LCDDR12_SEG219 \ LCD memory bit segment
+ $10 constant LCDDR12_SEG220 \ LCD memory bit segment
+ $20 constant LCDDR12_SEG221 \ LCD memory bit segment
+ $40 constant LCDDR12_SEG222 \ LCD memory bit segment
+ $80 constant LCDDR12_SEG223 \ LCD memory bit segment
+&247 constant LCDDR11 \ LCD Data Register 11
+ $01 constant LCDDR11_SEG208 \ LCD memory bit segment
+ $02 constant LCDDR11_SEG209 \ LCD memory bit segment
+ $04 constant LCDDR11_SEG210 \ LCD memory bit segment
+ $08 constant LCDDR11_SEG211 \ LCD memory bit segment
+ $10 constant LCDDR11_SEG212 \ LCD memory bit segment
+ $20 constant LCDDR11_SEG213 \ LCD memory bit segment
+ $40 constant LCDDR11_SEG214 \ LCD memory bit segment
+ $80 constant LCDDR11_SEG215 \ LCD memory bit segment
+&246 constant LCDDR10 \ LCD Data Register 10
+ $01 constant LCDDR10_SEG200 \ LCD memory bit segment
+ $02 constant LCDDR10_SEG201 \ LCD memory bit segment
+ $04 constant LCDDR10_SEG202 \ LCD memory bit segment
+ $08 constant LCDDR10_SEG203 \ LCD memory bit segment
+ $10 constant LCDDR10_SEG204 \ LCD memory bit segment
+ $20 constant LCDDR10_SEG205 \ LCD memory bit segment
+ $40 constant LCDDR10_SEG206 \ LCD memory bit segment
+ $80 constant LCDDR10_SEG207 \ LCD memory bit segment
+&244 constant LCDDR8 \ LCD Data Register 8
+ $01 constant LCDDR8_SEG124 \ LCD memory bit segment
+ $02 constant LCDDR8_SEG125 \ LCD memory bit segment
+ $04 constant LCDDR8_SEG126 \ LCD memory bit segment
+ $08 constant LCDDR8_SEG127 \ LCD memory bit segment
+ $10 constant LCDDR8_SEG128 \ LCD memory bit segment
+ $20 constant LCDDR8_SEG129 \ LCD memory bit segment
+ $40 constant LCDDR8_SEG130 \ LCD memory bit segment
+ $80 constant LCDDR8_SEG131 \ LCD memory bit segment
+&243 constant LCDDR7 \ LCD Data Register 7
+ $01 constant LCDDR7_SEG116 \ LCD memory bit segment
+ $02 constant LCDDR7_SEG117 \ LCD memory bit segment
+ $04 constant LCDDR7_SEG118 \ LCD memory bit segment
+ $08 constant LCDDR7_SEG119 \ LCD memory bit segment
+ $10 constant LCDDR7_SEG120 \ LCD memory bit segment
+ $20 constant LCDDR7_SEG121 \ LCD memory bit segment
+ $40 constant LCDDR7_SEG122 \ LCD memory bit segment
+ $80 constant LCDDR7_SEG123 \ LCD memory bit segment
+&242 constant LCDDR6 \ LCD Data Register 6
+ $01 constant LCDDR6_SEG108 \ LCD memory bit segment
+ $02 constant LCDDR6_SEG109 \ LCD memory bit segment
+ $04 constant LCDDR6_SEG110 \ LCD memory bit segment
+ $08 constant LCDDR6_SEG111 \ LCD memory bit segment
+ $10 constant LCDDR6_SEG112 \ LCD memory bit segment
+ $20 constant LCDDR6_SEG113 \ LCD memory bit segment
+ $40 constant LCDDR6_SEG114 \ LCD memory bit segment
+ $80 constant LCDDR6_SEG115 \ LCD memory bit segment
+&241 constant LCDDR5 \ LCD Data Register 5
+ $01 constant LCDDR5_SEG100 \ LCD memory bit segment
+ $02 constant LCDDR5_SEG101 \ LCD memory bit segment
+ $04 constant LCDDR5_SEG102 \ LCD memory bit segment
+ $08 constant LCDDR5_SEG103 \ LCD memory bit segment
+ $10 constant LCDDR5_SEG104 \ LCD memory bit segment
+ $20 constant LCDDR5_SEG105 \ LCD memory bit segment
+ $40 constant LCDDR5_SEG106 \ LCD memory bit segment
+ $80 constant LCDDR5_SEG107 \ LCD memory bit segment
+&239 constant LCDDR3 \ LCD Data Register 3
+ $01 constant LCDDR3_SEG024 \ LCD memory bit segment
+ $02 constant LCDDR3_SEG025 \ LCD memory bit segment
+ $04 constant LCDDR3_SEG026 \ LCD memory bit segment
+ $08 constant LCDDR3_SEG027 \ LCD memory bit segment
+ $10 constant LCDDR3_SEG028 \ LCD memory bit segment
+ $20 constant LCDDR3_SEG029 \ LCD memory bit segment
+ $40 constant LCDDR3_SEG030 \ LCD memory bit segment
+ $80 constant LCDDR3_SEG031 \ LCD memory bit segment
+&238 constant LCDDR2 \ LCD Data Register 2
+ $01 constant LCDDR2_SEG016 \ LCD memory bit segment
+ $02 constant LCDDR2_SEG017 \ LCD memory bit segment
+ $04 constant LCDDR2_SEG018 \ LCD memory bit segment
+ $08 constant LCDDR2_SEG019 \ LCD memory bit segment
+ $10 constant LCDDR2_SEG020 \ LCD memory bit segment
+ $20 constant LCDDR2_SEG021 \ LCD memory bit segment
+ $40 constant LCDDR2_SEG022 \ LCD memory bit segment
+ $80 constant LCDDR2_SEG023 \ LCD memory bit segment
+&237 constant LCDDR1 \ LCD Data Register 1
+ $01 constant LCDDR1_SEG008 \ LCD memory bit segment
+ $02 constant LCDDR1_SEG009 \ LCD memory bit segment
+ $04 constant LCDDR1_SEG010 \ LCD memory bit segment
+ $08 constant LCDDR1_SEG011 \ LCD memory bit segment
+ $10 constant LCDDR1_SEG012 \ LCD memory bit segment
+ $20 constant LCDDR1_SEG013 \ LCD memory bit segment
+ $40 constant LCDDR1_SEG014 \ LCD memory bit segment
+ $80 constant LCDDR1_SEG015 \ LCD memory bit segment
+&236 constant LCDDR0 \ LCD Data Register 0
+ $01 constant LCDDR0_SEG000 \ LCD memory bit segment
+ $02 constant LCDDR0_SEG001 \ LCD memory bit segment
+ $04 constant LCDDR0_SEG002 \ LCD memory bit segment
+ $08 constant LCDDR0_SEG003 \ LCD memory bit segment
+ $10 constant LCDDR0_SEG004 \ LCD memory bit segment
+ $20 constant LCDDR0_SEG005 \ LCD memory bit segment
+ $40 constant LCDDR0_SEG006 \ LCD memory bit segment
+ $80 constant LCDDR0_SEG007 \ LCD memory bit segment
+&231 constant LCDCCR \ LCD Contrast Control Register
+ $E0 constant LCDCCR_LCDDC \
+ $10 constant LCDCCR_LCDMDT \ LCD Maximum Drive Time
+ $0F constant LCDCCR_LCDCC \ LCD Contrast Controls
+&230 constant LCDFRR \ LCD Frame Rate Register
+ $70 constant LCDFRR_LCDPS \ LCD Prescaler Selects
+ $07 constant LCDFRR_LCDCD \ LCD Clock Dividers
+&229 constant LCDCRB \ LCD Control and Status Register B
+ $80 constant LCDCRB_LCDCS \ LCD CLock Select
+ $40 constant LCDCRB_LCD2B \ LCD 1/2 Bias Select
+ $30 constant LCDCRB_LCDMUX \ LCD Mux Selects
+ $0F constant LCDCRB_LCDPM \ LCD Port Masks
+&228 constant LCDCRA \ LCD Control Register A
+ $80 constant LCDCRA_LCDEN \ LCD Enable
+ $40 constant LCDCRA_LCDAB \ LCD A or B waveform
+ $10 constant LCDCRA_LCDIF \ LCD Interrupt Flag
+ $08 constant LCDCRA_LCDIE \ LCD Interrupt Enable
+ $04 constant LCDCRA_LCDBD \ LCD Buffer Disable
+ $02 constant LCDCRA_LCDCCD \ LCD Contrast Control Disable
+ $01 constant LCDCRA_LCDBL \ LCD Blanking
+\ CPU
+&95 constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ $08 constant SREG_V \ Two's Complement Overflow Flag
+ $04 constant SREG_N \ Negative Flag
+ $02 constant SREG_Z \ Zero Flag
+ $01 constant SREG_C \ Carry Flag
+&93 constant SP \ Stack Pointer
+&102 constant OSCCAL \ Oscillator Calibration Value
+&97 constant CLKPR \ Clock Prescale Register
+ $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable
+ $0F constant CLKPR_CLKPS \ Clock Prescaler Select Bits
+&100 constant PRR \ Power Reduction Register
+ $10 constant PRR_PRLCD \ Power Reduction LCD
+ $08 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
+ $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
+ $02 constant PRR_PRUSART0 \ Power Reduction USART
+ $01 constant PRR_PRADC \ Power Reduction ADC
+&83 constant SMCR \ Sleep Mode Control Register
+ $0E constant SMCR_SM \ Sleep Mode Select bits
+ $01 constant SMCR_SE \ Sleep Enable
+&75 constant GPIOR2 \ General Purpose IO Register 2
+&74 constant GPIOR1 \ General Purpose IO Register 1
+&62 constant GPIOR0 \ General Purpose IO Register 0
+
+\ Interrupts
+&2 constant INT0Addr \ External Interrupt Request 0
+&4 constant PCINT0Addr \ Pin Change Interrupt Request 0
+&6 constant PCINT1Addr \ Pin Change Interrupt Request 1
+&8 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
+&10 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
+&12 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+&14 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
+&16 constant TIMER1_COMPBAddr \ Timer/Counter Compare Match B
+&18 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+&20 constant TIMER0_COMPAddr \ Timer/Counter0 Compare Match
+&22 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
+&24 constant SPI__STCAddr \ SPI Serial Transfer Complete
+&26 constant USART0__RXAddr \ USART0, Rx Complete
+&28 constant USART0__UDREAddr \ USART0 Data register Empty
+&30 constant USART0__TXAddr \ USART0, Tx Complete
+&32 constant USI_STARTAddr \ USI Start Condition
+&34 constant USI_OVERFLOWAddr \ USI Overflow
+&36 constant ANALOG_COMPAddr \ Analog Comparator
+&38 constant ADCAddr \ ADC Conversion Complete
+&40 constant EE_READYAddr \ EEPROM Ready
+&42 constant SPM_READYAddr \ Store Program Memory Read
+&44 constant LCDAddr \ LCD Start of Frame
diff --git a/amforth-6.5/avr8/devices/atmega329p/device.asm b/amforth-6.5/avr8/devices/atmega329p/device.asm
new file mode 100644
index 0000000..30d7f84
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega329p/device.asm
@@ -0,0 +1,109 @@
+; Partname: ATmega329P
+; generated automatically, do not edit
+
+.nolist
+ .include "m329Pdef.inc"
+.list
+
+.equ ramstart = 256
+.equ CELLSIZE = 2
+.macro readflashcell
+ lsl zl
+ rol zh
+ lpm @0, Z+
+ lpm @1, Z+
+.endmacro
+.macro writeflashcell
+ lsl zl
+ rol zh
+.endmacro
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_TIMER_COUNTER_2 = 0
+.set WANT_WATCHDOG = 0
+.set WANT_EEPROM = 0
+.set WANT_SPI = 0
+.set WANT_PORTA = 0
+.set WANT_PORTB = 0
+.set WANT_PORTC = 0
+.set WANT_PORTD = 0
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_PORTE = 0
+.set WANT_PORTF = 0
+.set WANT_PORTG = 0
+.set WANT_JTAG = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_USI = 0
+.set WANT_AD_CONVERTER = 0
+.set WANT_BOOT_LOAD = 0
+.set WANT_USART0 = 0
+.set WANT_LCD = 0
+.set WANT_CPU = 0
+.equ intvecsize = 2 ; please verify; flash size: 32768 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.org 2
+ rcall isr ; External Interrupt Request 0
+.org 4
+ rcall isr ; Pin Change Interrupt Request 0
+.org 6
+ rcall isr ; Pin Change Interrupt Request 1
+.org 8
+ rcall isr ; Timer/Counter2 Compare Match
+.org 10
+ rcall isr ; Timer/Counter2 Overflow
+.org 12
+ rcall isr ; Timer/Counter1 Capture Event
+.org 14
+ rcall isr ; Timer/Counter1 Compare Match A
+.org 16
+ rcall isr ; Timer/Counter Compare Match B
+.org 18
+ rcall isr ; Timer/Counter1 Overflow
+.org 20
+ rcall isr ; Timer/Counter0 Compare Match
+.org 22
+ rcall isr ; Timer/Counter0 Overflow
+.org 24
+ rcall isr ; SPI Serial Transfer Complete
+.org 26
+ rcall isr ; USART0, Rx Complete
+.org 28
+ rcall isr ; USART0 Data register Empty
+.org 30
+ rcall isr ; USART0, Tx Complete
+.org 32
+ rcall isr ; USI Start Condition
+.org 34
+ rcall isr ; USI Overflow
+.org 36
+ rcall isr ; Analog Comparator
+.org 38
+ rcall isr ; ADC Conversion Complete
+.org 40
+ rcall isr ; EEPROM Ready
+.org 42
+ rcall isr ; Store Program Memory Read
+.org 44
+ rcall isr ; LCD Start of Frame
+.equ INTVECTORS = 23
+.nooverlap
+
+; compatability layer (maybe empty)
+.equ EEPE = EEWE
+.equ EEMPE = EEMWE
+
+; controller data area, environment query mcu-info
+mcu_info:
+mcu_ramsize:
+ .dw 2048
+mcu_eepromsize:
+ .dw 1024
+mcu_maxdp:
+ .dw 28672
+mcu_numints:
+ .dw 23
+mcu_name:
+ .dw 10
+ .db "ATmega329P"
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega329p/device.inc b/amforth-6.5/avr8/devices/atmega329p/device.inc
new file mode 100644
index 0000000..3e941bb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega329p/device.inc
@@ -0,0 +1,1293 @@
+; Partname: ATmega329P
+; generated automatically, no not edit
+
+.if WANT_TIMER_COUNTER_0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Control Register
+VE_TCCR0A:
+ .dw $ff06
+ .db "TCCR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0A
+XT_TCCR0A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0A:
+ .dw 68
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw 70
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0A:
+ .dw $ff05
+ .db "OCR0A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0A
+XT_OCR0A:
+ .dw PFA_DOVARIABLE
+PFA_OCR0A:
+ .dw 71
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Mask Register
+VE_TIMSK0:
+ .dw $ff06
+ .db "TIMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK0
+XT_TIMSK0:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK0:
+ .dw 110
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Flag register
+VE_TIFR0:
+ .dw $ff05
+ .db "TIFR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR0
+XT_TIFR0:
+ .dw PFA_DOVARIABLE
+PFA_TIFR0:
+ .dw 53
+; ( -- addr ) System Constant
+; R( -- )
+; General Timer/Control Register
+VE_GTCCR:
+ .dw $ff05
+ .db "GTCCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GTCCR
+XT_GTCCR:
+ .dw PFA_DOVARIABLE
+PFA_GTCCR:
+ .dw 67
+
+.endif
+.if WANT_TIMER_COUNTER_1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw 128
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw 129
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter 1 Control Register C
+VE_TCCR1C:
+ .dw $ff06
+ .db "TCCR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1C
+XT_TCCR1C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1C:
+ .dw 130
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Bytes
+VE_TCNT1:
+ .dw $ff05
+ .db "TCNT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1
+XT_TCNT1:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1:
+ .dw 132
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register A Bytes
+VE_OCR1A:
+ .dw $ff05
+ .db "OCR1A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1A
+XT_OCR1A:
+ .dw PFA_DOVARIABLE
+PFA_OCR1A:
+ .dw 136
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register B Bytes
+VE_OCR1B:
+ .dw $ff05
+ .db "OCR1B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1B
+XT_OCR1B:
+ .dw PFA_DOVARIABLE
+PFA_OCR1B:
+ .dw 138
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Bytes
+VE_ICR1:
+ .dw $ff04
+ .db "ICR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1
+XT_ICR1:
+ .dw PFA_DOVARIABLE
+PFA_ICR1:
+ .dw 134
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Mask Register
+VE_TIMSK1:
+ .dw $ff06
+ .db "TIMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK1
+XT_TIMSK1:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK1:
+ .dw 111
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Flag register
+VE_TIFR1:
+ .dw $ff05
+ .db "TIFR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR1
+XT_TIFR1:
+ .dw PFA_DOVARIABLE
+PFA_TIFR1:
+ .dw 54
+
+.endif
+.if WANT_TIMER_COUNTER_2 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register
+VE_TCCR2A:
+ .dw $ff06
+ .db "TCCR2A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2A
+XT_TCCR2A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2A:
+ .dw 176
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2
+VE_TCNT2:
+ .dw $ff05
+ .db "TCNT2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT2
+XT_TCNT2:
+ .dw PFA_DOVARIABLE
+PFA_TCNT2:
+ .dw 178
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register
+VE_OCR2A:
+ .dw $ff05
+ .db "OCR2A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2A
+XT_OCR2A:
+ .dw PFA_DOVARIABLE
+PFA_OCR2A:
+ .dw 179
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Interrupt Mask register
+VE_TIMSK2:
+ .dw $ff06
+ .db "TIMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK2
+XT_TIMSK2:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK2:
+ .dw 112
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Interrupt Flag Register
+VE_TIFR2:
+ .dw $ff05
+ .db "TIFR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR2
+XT_TIFR2:
+ .dw PFA_DOVARIABLE
+PFA_TIFR2:
+ .dw 55
+; ( -- addr ) System Constant
+; R( -- )
+; Asynchronous Status Register
+VE_ASSR:
+ .dw $ff04
+ .db "ASSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ASSR
+XT_ASSR:
+ .dw PFA_DOVARIABLE
+PFA_ASSR:
+ .dw 182
+
+.endif
+.if WANT_WATCHDOG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCR:
+ .dw $ff05
+ .db "WDTCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCR
+XT_WDTCR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCR:
+ .dw 96
+
+.endif
+.if WANT_EEPROM == 1
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Read/Write Access Bytes
+VE_EEAR:
+ .dw $ff04
+ .db "EEAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEAR
+XT_EEAR:
+ .dw PFA_DOVARIABLE
+PFA_EEAR:
+ .dw 65
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw 64
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw 63
+
+.endif
+.if WANT_SPI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR:
+ .dw $ff04
+ .db "SPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR
+XT_SPCR:
+ .dw PFA_DOVARIABLE
+PFA_SPCR:
+ .dw 76
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR:
+ .dw $ff04
+ .db "SPSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR
+XT_SPSR:
+ .dw PFA_DOVARIABLE
+PFA_SPSR:
+ .dw 77
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR:
+ .dw $ff04
+ .db "SPDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR
+XT_SPDR:
+ .dw PFA_DOVARIABLE
+PFA_SPDR:
+ .dw 78
+
+.endif
+.if WANT_PORTA == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Register
+VE_PORTA:
+ .dw $ff05
+ .db "PORTA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTA
+XT_PORTA:
+ .dw PFA_DOVARIABLE
+PFA_PORTA:
+ .dw 34
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Direction Register
+VE_DDRA:
+ .dw $ff04
+ .db "DDRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRA
+XT_DDRA:
+ .dw PFA_DOVARIABLE
+PFA_DDRA:
+ .dw 33
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Input Pins
+VE_PINA:
+ .dw $ff04
+ .db "PINA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINA
+XT_PINA:
+ .dw PFA_DOVARIABLE
+PFA_PINA:
+ .dw 32
+
+.endif
+.if WANT_PORTB == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw 37
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw 36
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw 35
+
+.endif
+.if WANT_PORTC == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Register
+VE_PORTC:
+ .dw $ff05
+ .db "PORTC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTC
+XT_PORTC:
+ .dw PFA_DOVARIABLE
+PFA_PORTC:
+ .dw 40
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Direction Register
+VE_DDRC:
+ .dw $ff04
+ .db "DDRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRC
+XT_DDRC:
+ .dw PFA_DOVARIABLE
+PFA_DDRC:
+ .dw 39
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Input Pins
+VE_PINC:
+ .dw $ff04
+ .db "PINC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINC
+XT_PINC:
+ .dw PFA_DOVARIABLE
+PFA_PINC:
+ .dw 38
+
+.endif
+.if WANT_PORTD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw 43
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw 42
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw 41
+
+.endif
+.if WANT_ANALOG_COMPARATOR == 1
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Control and Status Register B
+VE_ADCSRB:
+ .dw $ff06
+ .db "ADCSRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRB
+XT_ADCSRB:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRB:
+ .dw 123
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Control And Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw 80
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 1
+VE_DIDR1:
+ .dw $ff05
+ .db "DIDR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR1
+XT_DIDR1:
+ .dw PFA_DOVARIABLE
+PFA_DIDR1:
+ .dw 127
+
+.endif
+.if WANT_PORTE == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port E
+VE_PORTE:
+ .dw $ff05
+ .db "PORTE",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTE
+XT_PORTE:
+ .dw PFA_DOVARIABLE
+PFA_PORTE:
+ .dw 46
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port E
+VE_DDRE:
+ .dw $ff04
+ .db "DDRE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRE
+XT_DDRE:
+ .dw PFA_DOVARIABLE
+PFA_DDRE:
+ .dw 45
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port E
+VE_PINE:
+ .dw $ff04
+ .db "PINE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINE
+XT_PINE:
+ .dw PFA_DOVARIABLE
+PFA_PINE:
+ .dw 44
+
+.endif
+.if WANT_PORTF == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port F
+VE_PORTF:
+ .dw $ff05
+ .db "PORTF",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTF
+XT_PORTF:
+ .dw PFA_DOVARIABLE
+PFA_PORTF:
+ .dw 49
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port F
+VE_DDRF:
+ .dw $ff04
+ .db "DDRF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRF
+XT_DDRF:
+ .dw PFA_DOVARIABLE
+PFA_DDRF:
+ .dw 48
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port F
+VE_PINF:
+ .dw $ff04
+ .db "PINF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINF
+XT_PINF:
+ .dw PFA_DOVARIABLE
+PFA_PINF:
+ .dw 47
+
+.endif
+.if WANT_PORTG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Data Register
+VE_PORTG:
+ .dw $ff05
+ .db "PORTG",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTG
+XT_PORTG:
+ .dw PFA_DOVARIABLE
+PFA_PORTG:
+ .dw 52
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Data Direction Register
+VE_DDRG:
+ .dw $ff04
+ .db "DDRG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRG
+XT_DDRG:
+ .dw PFA_DOVARIABLE
+PFA_DDRG:
+ .dw 51
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Input Pins
+VE_PING:
+ .dw $ff04
+ .db "PING"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PING
+XT_PING:
+ .dw PFA_DOVARIABLE
+PFA_PING:
+ .dw 50
+
+.endif
+.if WANT_JTAG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; On-Chip Debug Related Register in I/O Memory
+VE_OCDR:
+ .dw $ff04
+ .db "OCDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCDR
+XT_OCDR:
+ .dw PFA_DOVARIABLE
+PFA_OCDR:
+ .dw 81
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw 85
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Status Register
+VE_MCUSR:
+ .dw $ff05
+ .db "MCUSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUSR
+XT_MCUSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUSR:
+ .dw 84
+
+.endif
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register A
+VE_EICRA:
+ .dw $ff05
+ .db "EICRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRA
+XT_EICRA:
+ .dw PFA_DOVARIABLE
+PFA_EICRA:
+ .dw 105
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Mask Register
+VE_EIMSK:
+ .dw $ff05
+ .db "EIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIMSK
+XT_EIMSK:
+ .dw PFA_DOVARIABLE
+PFA_EIMSK:
+ .dw 61
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Flag Register
+VE_EIFR:
+ .dw $ff04
+ .db "EIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIFR
+XT_EIFR:
+ .dw PFA_DOVARIABLE
+PFA_EIFR:
+ .dw 60
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 1
+VE_PCMSK1:
+ .dw $ff06
+ .db "PCMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK1
+XT_PCMSK1:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK1:
+ .dw 108
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 0
+VE_PCMSK0:
+ .dw $ff06
+ .db "PCMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK0
+XT_PCMSK0:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK0:
+ .dw 107
+
+.endif
+.if WANT_USI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USI Data Register
+VE_USIDR:
+ .dw $ff05
+ .db "USIDR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USIDR
+XT_USIDR:
+ .dw PFA_DOVARIABLE
+PFA_USIDR:
+ .dw 186
+; ( -- addr ) System Constant
+; R( -- )
+; USI Status Register
+VE_USISR:
+ .dw $ff05
+ .db "USISR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USISR
+XT_USISR:
+ .dw PFA_DOVARIABLE
+PFA_USISR:
+ .dw 185
+; ( -- addr ) System Constant
+; R( -- )
+; USI Control Register
+VE_USICR:
+ .dw $ff05
+ .db "USICR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USICR
+XT_USICR:
+ .dw PFA_DOVARIABLE
+PFA_USICR:
+ .dw 184
+
+.endif
+.if WANT_AD_CONVERTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC multiplexer Selection Register
+VE_ADMUX:
+ .dw $ff05
+ .db "ADMUX",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADMUX
+XT_ADMUX:
+ .dw PFA_DOVARIABLE
+PFA_ADMUX:
+ .dw 124
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register
+VE_ADCSRA:
+ .dw $ff06
+ .db "ADCSRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRA
+XT_ADCSRA:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRA:
+ .dw 122
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register Bytes
+VE_ADC:
+ .dw $ff03
+ .db "ADC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADC
+XT_ADC:
+ .dw PFA_DOVARIABLE
+PFA_ADC:
+ .dw 120
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 0
+VE_DIDR0:
+ .dw $ff05
+ .db "DIDR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR0
+XT_DIDR0:
+ .dw PFA_DOVARIABLE
+PFA_DIDR0:
+ .dw 126
+
+.endif
+.if WANT_BOOT_LOAD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control Register
+VE_SPMCSR:
+ .dw $ff06
+ .db "SPMCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCSR
+XT_SPMCSR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCSR:
+ .dw 87
+
+.endif
+.if WANT_USART0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR0:
+ .dw $ff04
+ .db "UDR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR0
+XT_UDR0:
+ .dw PFA_DOVARIABLE
+PFA_UDR0:
+ .dw 198
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR0A:
+ .dw $ff06
+ .db "UCSR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0A
+XT_UCSR0A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0A:
+ .dw 192
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR0B:
+ .dw $ff06
+ .db "UCSR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0B
+XT_UCSR0B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0B:
+ .dw 193
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR0C:
+ .dw $ff06
+ .db "UCSR0C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0C
+XT_UCSR0C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0C:
+ .dw 194
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Bytes
+VE_UBRR0:
+ .dw $ff05
+ .db "UBRR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR0
+XT_UBRR0:
+ .dw PFA_DOVARIABLE
+PFA_UBRR0:
+ .dw 196
+
+.endif
+.if WANT_LCD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 18
+VE_LCDDR18:
+ .dw $ff07
+ .db "LCDDR18",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR18
+XT_LCDDR18:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR18:
+ .dw 254
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 17
+VE_LCDDR17:
+ .dw $ff07
+ .db "LCDDR17",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR17
+XT_LCDDR17:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR17:
+ .dw 253
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 16
+VE_LCDDR16:
+ .dw $ff07
+ .db "LCDDR16",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR16
+XT_LCDDR16:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR16:
+ .dw 252
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 15
+VE_LCDDR15:
+ .dw $ff07
+ .db "LCDDR15",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR15
+XT_LCDDR15:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR15:
+ .dw 251
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 13
+VE_LCDDR13:
+ .dw $ff07
+ .db "LCDDR13",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR13
+XT_LCDDR13:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR13:
+ .dw 249
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 12
+VE_LCDDR12:
+ .dw $ff07
+ .db "LCDDR12",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR12
+XT_LCDDR12:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR12:
+ .dw 248
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 11
+VE_LCDDR11:
+ .dw $ff07
+ .db "LCDDR11",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR11
+XT_LCDDR11:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR11:
+ .dw 247
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 10
+VE_LCDDR10:
+ .dw $ff07
+ .db "LCDDR10",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR10
+XT_LCDDR10:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR10:
+ .dw 246
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 8
+VE_LCDDR8:
+ .dw $ff06
+ .db "LCDDR8"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR8
+XT_LCDDR8:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR8:
+ .dw 244
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 7
+VE_LCDDR7:
+ .dw $ff06
+ .db "LCDDR7"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR7
+XT_LCDDR7:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR7:
+ .dw 243
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 6
+VE_LCDDR6:
+ .dw $ff06
+ .db "LCDDR6"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR6
+XT_LCDDR6:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR6:
+ .dw 242
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 5
+VE_LCDDR5:
+ .dw $ff06
+ .db "LCDDR5"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR5
+XT_LCDDR5:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR5:
+ .dw 241
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 3
+VE_LCDDR3:
+ .dw $ff06
+ .db "LCDDR3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR3
+XT_LCDDR3:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR3:
+ .dw 239
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 2
+VE_LCDDR2:
+ .dw $ff06
+ .db "LCDDR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR2
+XT_LCDDR2:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR2:
+ .dw 238
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 1
+VE_LCDDR1:
+ .dw $ff06
+ .db "LCDDR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR1
+XT_LCDDR1:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR1:
+ .dw 237
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 0
+VE_LCDDR0:
+ .dw $ff06
+ .db "LCDDR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR0
+XT_LCDDR0:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR0:
+ .dw 236
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Contrast Control Register
+VE_LCDCCR:
+ .dw $ff06
+ .db "LCDCCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDCCR
+XT_LCDCCR:
+ .dw PFA_DOVARIABLE
+PFA_LCDCCR:
+ .dw 231
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Frame Rate Register
+VE_LCDFRR:
+ .dw $ff06
+ .db "LCDFRR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDFRR
+XT_LCDFRR:
+ .dw PFA_DOVARIABLE
+PFA_LCDFRR:
+ .dw 230
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Control and Status Register B
+VE_LCDCRB:
+ .dw $ff06
+ .db "LCDCRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDCRB
+XT_LCDCRB:
+ .dw PFA_DOVARIABLE
+PFA_LCDCRB:
+ .dw 229
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Control Register A
+VE_LCDCRA:
+ .dw $ff06
+ .db "LCDCRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDCRA
+XT_LCDCRA:
+ .dw PFA_DOVARIABLE
+PFA_LCDCRA:
+ .dw 228
+
+.endif
+.if WANT_CPU == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw 95
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer
+VE_SP:
+ .dw $ff02
+ .db "SP"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SP
+XT_SP:
+ .dw PFA_DOVARIABLE
+PFA_SP:
+ .dw 93
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Calibration Value
+VE_OSCCAL:
+ .dw $ff06
+ .db "OSCCAL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSCCAL
+XT_OSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_OSCCAL:
+ .dw 102
+; ( -- addr ) System Constant
+; R( -- )
+; Clock Prescale Register
+VE_CLKPR:
+ .dw $ff05
+ .db "CLKPR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKPR
+XT_CLKPR:
+ .dw PFA_DOVARIABLE
+PFA_CLKPR:
+ .dw 97
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register
+VE_PRR:
+ .dw $ff03
+ .db "PRR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR
+XT_PRR:
+ .dw PFA_DOVARIABLE
+PFA_PRR:
+ .dw 100
+; ( -- addr ) System Constant
+; R( -- )
+; Sleep Mode Control Register
+VE_SMCR:
+ .dw $ff04
+ .db "SMCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SMCR
+XT_SMCR:
+ .dw PFA_DOVARIABLE
+PFA_SMCR:
+ .dw 83
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 2
+VE_GPIOR2:
+ .dw $ff06
+ .db "GPIOR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR2
+XT_GPIOR2:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR2:
+ .dw 75
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 1
+VE_GPIOR1:
+ .dw $ff06
+ .db "GPIOR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR1
+XT_GPIOR1:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR1:
+ .dw 74
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 0
+VE_GPIOR0:
+ .dw $ff06
+ .db "GPIOR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR0
+XT_GPIOR0:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR0:
+ .dw 62
+
+.endif
diff --git a/amforth-6.5/avr8/devices/atmega329p/device.py b/amforth-6.5/avr8/devices/atmega329p/device.py
new file mode 100644
index 0000000..2fdfee0
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega329p/device.py
@@ -0,0 +1,504 @@
+# Generated Automatically
+
+# Partname ATmega329P
+
+MCUREGS = {
+# Interrupt Vectors
+ 'INT0Addr' : '#2', # External Interrupt Request 0
+ 'PCINT0Addr' : '#4', # Pin Change Interrupt Request 0
+ 'PCINT1Addr' : '#6', # Pin Change Interrupt Request 1
+ 'TIMER2_COMPAddr' : '#8', # Timer/Counter2 Compare Match
+ 'TIMER2_OVFAddr' : '#10', # Timer/Counter2 Overflow
+ 'TIMER1_CAPTAddr' : '#12', # Timer/Counter1 Capture Event
+ 'TIMER1_COMPAAddr' : '#14', # Timer/Counter1 Compare Match A
+ 'TIMER1_COMPBAddr' : '#16', # Timer/Counter Compare Match B
+ 'TIMER1_OVFAddr' : '#18', # Timer/Counter1 Overflow
+ 'TIMER0_COMPAddr' : '#20', # Timer/Counter0 Compare Match
+ 'TIMER0_OVFAddr' : '#22', # Timer/Counter0 Overflow
+ 'SPI_STCAddr' : '#24', # SPI Serial Transfer Complete
+ 'USART0_RXAddr' : '#26', # USART0, Rx Complete
+ 'USART0_UDREAddr' : '#28', # USART0 Data register Empty
+ 'USART0_TXAddr' : '#30', # USART0, Tx Complete
+ 'USI_STARTAddr' : '#32', # USI Start Condition
+ 'USI_OVERFLOWAddr' : '#34', # USI Overflow
+ 'ANALOG_COMPAddr' : '#36', # Analog Comparator
+ 'ADCAddr' : '#38', # ADC Conversion Complete
+ 'EE_READYAddr' : '#40', # EEPROM Ready
+ 'SPM_READYAddr' : '#42', # Store Program Memory Read
+ 'LCDAddr' : '#44', # LCD Start of Frame
+
+# Module TIMER_COUNTER_0
+ 'TCCR0A' : '$44', # Timer/Counter0 Control Registe
+ 'TCCR0A_FOC0A': '$80', # Force Output Compare
+ 'TCCR0A_WGM00': '$40', # Waveform Generation Mode 0
+ 'TCCR0A_COM0A': '$30', # Compare Match Output Modes
+ 'TCCR0A_WGM01': '$8', # Waveform Generation Mode 1
+ 'TCCR0A_CS0': '$7', # Clock Selects
+ 'TCNT0' : '$46', # Timer/Counter0
+ 'OCR0A' : '$47', # Timer/Counter0 Output Compare
+ 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
+ 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
+ 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
+ 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
+ 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
+ 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Control Register
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSR310': '$1', # Prescaler Reset Timer/Counter1
+
+# Module TIMER_COUNTER_1
+ 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
+ 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
+ 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
+ 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
+ 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
+ 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
+ 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
+ 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
+ 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
+ 'TCCR1C' : '$82', # Timer/Counter 1 Control Regist
+ 'TCCR1C_FOC1A': '$80', # Force Output Compare 1A
+ 'TCCR1C_FOC1B': '$40', # Force Output Compare 1B
+ 'TCNT1' : '$84', # Timer/Counter1 Bytes
+ 'OCR1A' : '$88', # Timer/Counter1 Output Compare
+ 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
+ 'ICR1' : '$86', # Timer/Counter1 Input Capture R
+ 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
+ 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
+ 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
+ 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
+ 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
+ 'TIFR1' : '$36', # Timer/Counter1 Interrupt Flag
+ 'TIFR1_ICF1': '$20', # Input Capture Flag 1
+ 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
+ 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
+ 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
+
+# Module TIMER_COUNTER_2
+ 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
+ 'TCCR2A_FOC2A': '$80', # Force Output Compare A
+ 'TCCR2A_WGM20': '$40', # Waveform Generation Mode
+ 'TCCR2A_COM2A': '$30', # Compare Output Mode bits
+ 'TCCR2A_WGM21': '$8', # Waveform Generation Mode
+ 'TCCR2A_CS2': '$7', # Clock Select bits
+ 'TCNT2' : '$b2', # Timer/Counter2
+ 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
+ 'TIMSK2' : '$70', # Timer/Counter2 Interrupt Mask
+ 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
+ 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
+ 'TIFR2' : '$37', # Timer/Counter2 Interrupt Flag
+ 'TIFR2_OCF2A': '$2', # Timer/Counter2 Output Compare
+ 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_PSR2': '$2', # Prescaler Reset Timer/Counter2
+ 'ASSR' : '$b6', # Asynchronous Status Register
+ 'ASSR_EXCLK': '$10', # Enable External Clock Interrup
+ 'ASSR_AS2': '$8', # AS2: Asynchronous Timer/Counte
+ 'ASSR_TCN2UB': '$4', # TCN2UB: Timer/Counter2 Update
+ 'ASSR_OCR2UB': '$2', # Output Compare Register2 Updat
+ 'ASSR_TCR2UB': '$1', # TCR2UB: Timer/Counter Control
+
+# Module WATCHDOG
+ 'WDTCR' : '$60', # Watchdog Timer Control Registe
+ 'WDTCR_WDCE': '$10', # Watchdog Change Enable
+ 'WDTCR_WDE': '$8', # Watch Dog Enable
+ 'WDTCR_WDP': '$7', # Watch Dog Timer Prescaler bits
+
+# Module EEPROM
+ 'EEAR' : '$41', # EEPROM Read/Write Access Byte
+ 'EEDR' : '$40', # EEPROM Data Register
+ 'EECR' : '$3f', # EEPROM Control Register
+ 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
+ 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
+ 'EECR_EEWE': '$2', # EEPROM Write Enable
+ 'EECR_EERE': '$1', # EEPROM Read Enable
+
+# Module SPI
+ 'SPCR' : '$4c', # SPI Control Register
+ 'SPCR_SPIE': '$80', # SPI Interrupt Enable
+ 'SPCR_SPE': '$40', # SPI Enable
+ 'SPCR_DORD': '$20', # Data Order
+ 'SPCR_MSTR': '$10', # Master/Slave Select
+ 'SPCR_CPOL': '$8', # Clock polarity
+ 'SPCR_CPHA': '$4', # Clock Phase
+ 'SPCR_SPR': '$3', # SPI Clock Rate Selects
+ 'SPSR' : '$4d', # SPI Status Register
+ 'SPSR_SPIF': '$80', # SPI Interrupt Flag
+ 'SPSR_WCOL': '$40', # Write Collision Flag
+ 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
+ 'SPDR' : '$4e', # SPI Data Register
+
+# Module PORTA
+ 'PORTA' : '$22', # Port A Data Register
+ 'DDRA' : '$21', # Port A Data Direction Register
+ 'PINA' : '$20', # Port A Input Pins
+
+# Module PORTB
+ 'PORTB' : '$25', # Port B Data Register
+ 'DDRB' : '$24', # Port B Data Direction Register
+ 'PINB' : '$23', # Port B Input Pins
+
+# Module PORTC
+ 'PORTC' : '$28', # Port C Data Register
+ 'DDRC' : '$27', # Port C Data Direction Register
+ 'PINC' : '$26', # Port C Input Pins
+
+# Module PORTD
+ 'PORTD' : '$2b', # Port D Data Register
+ 'DDRD' : '$2a', # Port D Data Direction Register
+ 'PIND' : '$29', # Port D Input Pins
+
+# Module ANALOG_COMPARATOR
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
+ 'ACSR' : '$50', # Analog Comparator Control And
+ 'ACSR_ACD': '$80', # Analog Comparator Disable
+ 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
+ 'ACSR_ACO': '$20', # Analog Compare Output
+ 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
+ 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
+ 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
+ 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
+ 'DIDR1' : '$7f', # Digital Input Disable Register
+ 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
+ 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
+
+# Module PORTE
+ 'PORTE' : '$2e', # Data Register, Port E
+ 'DDRE' : '$2d', # Data Direction Register, Port
+ 'PINE' : '$2c', # Input Pins, Port E
+
+# Module PORTF
+ 'PORTF' : '$31', # Data Register, Port F
+ 'DDRF' : '$30', # Data Direction Register, Port
+ 'PINF' : '$2f', # Input Pins, Port F
+
+# Module PORTG
+ 'PORTG' : '$34', # Port G Data Register
+ 'DDRG' : '$33', # Port G Data Direction Register
+ 'PING' : '$32', # Port G Input Pins
+
+# Module JTAG
+ 'OCDR' : '$51', # On-Chip Debug Related Register
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_JTD': '$80', # JTAG Interface Disable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+
+# Module EXTERNAL_INTERRUPT
+ 'EICRA' : '$69', # External Interrupt Control Reg
+ 'EICRA_ISC01': '$2', # External Interrupt Sense Contr
+ 'EICRA_ISC00': '$1', # External Interrupt Sense Contr
+ 'EIMSK' : '$3d', # External Interrupt Mask Regist
+ 'EIMSK_PCIE': '$f0', # Pin Change Interrupt Enables
+ 'EIMSK_INT0': '$1', # External Interrupt Request 0 E
+ 'EIFR' : '$3c', # External Interrupt Flag Regist
+ 'EIFR_PCIF': '$f0', # Pin Change Interrupt Flags
+ 'EIFR_INTF0': '$1', # External Interrupt Flag 0
+ 'PCMSK1' : '$6c', # Pin Change Mask Register 1
+ 'PCMSK1_PCINT8': '$1', # Pin Change Mask Register pin 8
+ 'PCMSK1_PCINT9': '$2', # Pin Change Mask Register pin 9
+ 'PCMSK1_PCINT10': '$4', # Pin Change Mask Register pin 1
+ 'PCMSK1_PCINT11': '$8', # Pin Change Mask Register pin 1
+ 'PCMSK1_PCINT12': '$10', # Pin Change Mask Register pin 1
+ 'PCMSK1_PCINT13': '$20', # Pin Change Mask Register pin 1
+ 'PCMSK1_PCINT14': '$40', # Pin Change Mask Register pin 1
+ 'PCMSK1_PCINT15': '$80', # Pin Change Mask Register pin 1
+ 'PCMSK0' : '$6b', # Pin Change Mask Register 0
+ 'PCMSK0_PCINT0': '$1', # Pin Change Mask Register pin 0
+ 'PCMSK0_PCINT1': '$2', # Pin Change Mask Register pin 1
+ 'PCMSK0_PCINT2': '$4', # Pin Change Mask Register pin 2
+ 'PCMSK0_PCINT3': '$8', # Pin Change Mask Register pin 3
+ 'PCMSK0_PCINT4': '$10', # Pin Change Mask Register pin 4
+ 'PCMSK0_PCINT5': '$20', # Pin Change Mask Register pin 5
+ 'PCMSK0_PCINT6': '$40', # Pin Change Mask Register pin 6
+ 'PCMSK0_PCINT7': '$80', # Pin Change Mask Register pin 7
+
+# Module USI
+ 'USIDR' : '$ba', # USI Data Register
+ 'USISR' : '$b9', # USI Status Register
+ 'USISR_USISIF': '$80', # Start Condition Interrupt Flag
+ 'USISR_USIOIF': '$40', # Counter Overflow Interrupt Fla
+ 'USISR_USIPF': '$20', # Stop Condition Flag
+ 'USISR_USIDC': '$10', # Data Output Collision
+ 'USISR_USICNT': '$f', # USI Counter Value Bits
+ 'USICR' : '$b8', # USI Control Register
+ 'USICR_USISIE': '$80', # Start Condition Interrupt Enab
+ 'USICR_USIOIE': '$40', # Counter Overflow Interrupt Ena
+ 'USICR_USIWM': '$30', # USI Wire Mode Bits
+ 'USICR_USICS': '$c', # USI Clock Source Select Bits
+ 'USICR_USICLK': '$2', # Clock Strobe
+ 'USICR_USITC': '$1', # Toggle Clock Port Pin
+
+# Module AD_CONVERTER
+ 'ADMUX' : '$7c', # The ADC multiplexer Selection
+ 'ADMUX_REFS': '$c0', # Reference Selection Bits
+ 'ADMUX_ADLAR': '$20', # Left Adjust Result
+ 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
+ 'ADCSRA' : '$7a', # The ADC Control and Status reg
+ 'ADCSRA_ADEN': '$80', # ADC Enable
+ 'ADCSRA_ADSC': '$40', # ADC Start Conversion
+ 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
+ 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
+ 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
+ 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
+ 'ADC' : '$78', # ADC Data Register Bytes
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Sources
+ 'DIDR0' : '$7e', # Digital Input Disable Register
+ 'DIDR0_ADC7D': '$80', # ADC7 Digital input Disable
+ 'DIDR0_ADC6D': '$40', # ADC6 Digital input Disable
+ 'DIDR0_ADC5D': '$20', # ADC5 Digital input Disable
+ 'DIDR0_ADC4D': '$10', # ADC4 Digital input Disable
+ 'DIDR0_ADC3D': '$8', # ADC3 Digital input Disable
+ 'DIDR0_ADC2D': '$4', # ADC2 Digital input Disable
+ 'DIDR0_ADC1D': '$2', # ADC1 Digital input Disable
+ 'DIDR0_ADC0D': '$1', # ADC0 Digital input Disable
+
+# Module BOOT_LOAD
+ 'SPMCSR' : '$57', # Store Program Memory Control R
+ 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
+ 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
+ 'SPMCSR_RWWSRE': '$10', # Read While Write section read
+ 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
+ 'SPMCSR_PGWRT': '$4', # Page Write
+ 'SPMCSR_PGERS': '$2', # Page Erase
+ 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
+
+# Module USART0
+ 'UDR0' : '$c6', # USART I/O Data Register
+ 'UCSR0A' : '$c0', # USART Control and Status Regis
+ 'UCSR0A_RXC0': '$80', # USART Receive Complete
+ 'UCSR0A_TXC0': '$40', # USART Transmit Complete
+ 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
+ 'UCSR0A_FE0': '$10', # Framing Error
+ 'UCSR0A_DOR0': '$8', # Data OverRun
+ 'UCSR0A_UPE0': '$4', # USART Parity Error
+ 'UCSR0A_U2X0': '$2', # Double the USART Transmission
+ 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
+ 'UCSR0B' : '$c1', # USART Control and Status Regis
+ 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
+ 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
+ 'UCSR0B_UDRIE0': '$20', # USART Data Register Empty Inte
+ 'UCSR0B_RXEN0': '$10', # Receiver Enable
+ 'UCSR0B_TXEN0': '$8', # Transmitter Enable
+ 'UCSR0B_UCSZ02': '$4', # Character Size
+ 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
+ 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
+ 'UCSR0C' : '$c2', # USART Control and Status Regis
+ 'UCSR0C_UMSEL0': '$40', # USART Mode Select
+ 'UCSR0C_UPM0': '$30', # Parity Mode Bits
+ 'UCSR0C_USBS0': '$8', # Stop Bit Select
+ 'UCSR0C_UCSZ0': '$6', # Character Size
+ 'UCSR0C_UCPOL0': '$1', # Clock Polarity
+ 'UBRR0' : '$c4', # USART Baud Rate Register Byte
+
+# Module LCD
+ 'LCDDR18' : '$fe', # LCD Data Register 18
+ 'LCDDR18_SEG324': '$1', # LCD memory bit segment
+ 'LCDDR18_SEG325': '$2', # LCD memory bit segment
+ 'LCDDR18_SEG326': '$4', # LCD memory bit segment
+ 'LCDDR18_SEG327': '$8', # LCD memory bit segment
+ 'LCDDR18_SEG328': '$10', # LCD memory bit segment
+ 'LCDDR18_SEG329': '$20', # LCD memory bit segment
+ 'LCDDR18_SEG330': '$40', # LCD memory bit segment
+ 'LCDDR18_SEG331': '$80', # LCD memory bit segment
+ 'LCDDR17' : '$fd', # LCD Data Register 17
+ 'LCDDR17_SEG316': '$1', # LCD memory bit segment
+ 'LCDDR17_SEG317': '$2', # LCD memory bit segment
+ 'LCDDR17_SEG318': '$4', # LCD memory bit segment
+ 'LCDDR17_SEG319': '$8', # LCD memory bit segment
+ 'LCDDR17_SEG320': '$10', # LCD memory bit segment
+ 'LCDDR17_SEG321': '$20', # LCD memory bit segment
+ 'LCDDR17_SEG322': '$40', # LCD memory bit segment
+ 'LCDDR17_SEG323': '$80', # LCD memory bit segment
+ 'LCDDR16' : '$fc', # LCD Data Register 16
+ 'LCDDR16_SEG308': '$1', # LCD memory bit segment
+ 'LCDDR16_SEG309': '$2', # LCD memory bit segment
+ 'LCDDR16_SEG310': '$4', # LCD memory bit segment
+ 'LCDDR16_SEG311': '$8', # LCD memory bit segment
+ 'LCDDR16_SEG312': '$10', # LCD memory bit segment
+ 'LCDDR16_SEG313': '$20', # LCD memory bit segment
+ 'LCDDR16_SEG314': '$40', # LCD memory bit segment
+ 'LCDDR16_SEG315': '$80', # LCD memory bit segment
+ 'LCDDR15' : '$fb', # LCD Data Register 15
+ 'LCDDR15_SEG300': '$1', # LCD memory bit segment
+ 'LCDDR15_SEG301': '$2', # LCD memory bit segment
+ 'LCDDR15_SEG302': '$4', # LCD memory bit segment
+ 'LCDDR15_SEG302': '$8', # LCD memory bit segment
+ 'LCDDR15_SEG304': '$10', # LCD memory bit segment
+ 'LCDDR15_SEG305': '$20', # LCD memory bit segment
+ 'LCDDR15_SEG306': '$40', # LCD memory bit segment
+ 'LCDDR15_SEG307': '$80', # LCD memory bit segment
+ 'LCDDR13' : '$f9', # LCD Data Register 13
+ 'LCDDR13_SEG224': '$1', # LCD memory bit segment
+ 'LCDDR13_SEG225': '$2', # LCD memory bit segment
+ 'LCDDR13_SEG226': '$4', # LCD memory bit segment
+ 'LCDDR13_SEG227': '$8', # LCD memory bit segment
+ 'LCDDR13_SEG228': '$10', # LCD memory bit segment
+ 'LCDDR13_SEG229': '$20', # LCD memory bit segment
+ 'LCDDR13_SEG230': '$40', # LCD memory bit segment
+ 'LCDDR13_SEG231': '$80', # LCD memory bit segment
+ 'LCDDR12' : '$f8', # LCD Data Register 12
+ 'LCDDR12_SEG216': '$1', # LCD memory bit segment
+ 'LCDDR12_SEG217': '$2', # LCD memory bit segment
+ 'LCDDR12_SEG218': '$4', # LCD memory bit segment
+ 'LCDDR12_SEG219': '$8', # LCD memory bit segment
+ 'LCDDR12_SEG220': '$10', # LCD memory bit segment
+ 'LCDDR12_SEG221': '$20', # LCD memory bit segment
+ 'LCDDR12_SEG222': '$40', # LCD memory bit segment
+ 'LCDDR12_SEG223': '$80', # LCD memory bit segment
+ 'LCDDR11' : '$f7', # LCD Data Register 11
+ 'LCDDR11_SEG208': '$1', # LCD memory bit segment
+ 'LCDDR11_SEG209': '$2', # LCD memory bit segment
+ 'LCDDR11_SEG210': '$4', # LCD memory bit segment
+ 'LCDDR11_SEG211': '$8', # LCD memory bit segment
+ 'LCDDR11_SEG212': '$10', # LCD memory bit segment
+ 'LCDDR11_SEG213': '$20', # LCD memory bit segment
+ 'LCDDR11_SEG214': '$40', # LCD memory bit segment
+ 'LCDDR11_SEG215': '$80', # LCD memory bit segment
+ 'LCDDR10' : '$f6', # LCD Data Register 10
+ 'LCDDR10_SEG200': '$1', # LCD memory bit segment
+ 'LCDDR10_SEG201': '$2', # LCD memory bit segment
+ 'LCDDR10_SEG202': '$4', # LCD memory bit segment
+ 'LCDDR10_SEG203': '$8', # LCD memory bit segment
+ 'LCDDR10_SEG204': '$10', # LCD memory bit segment
+ 'LCDDR10_SEG205': '$20', # LCD memory bit segment
+ 'LCDDR10_SEG206': '$40', # LCD memory bit segment
+ 'LCDDR10_SEG207': '$80', # LCD memory bit segment
+ 'LCDDR8' : '$f4', # LCD Data Register 8
+ 'LCDDR8_SEG124': '$1', # LCD memory bit segment
+ 'LCDDR8_SEG125': '$2', # LCD memory bit segment
+ 'LCDDR8_SEG126': '$4', # LCD memory bit segment
+ 'LCDDR8_SEG127': '$8', # LCD memory bit segment
+ 'LCDDR8_SEG128': '$10', # LCD memory bit segment
+ 'LCDDR8_SEG129': '$20', # LCD memory bit segment
+ 'LCDDR8_SEG130': '$40', # LCD memory bit segment
+ 'LCDDR8_SEG131': '$80', # LCD memory bit segment
+ 'LCDDR7' : '$f3', # LCD Data Register 7
+ 'LCDDR7_SEG116': '$1', # LCD memory bit segment
+ 'LCDDR7_SEG117': '$2', # LCD memory bit segment
+ 'LCDDR7_SEG118': '$4', # LCD memory bit segment
+ 'LCDDR7_SEG119': '$8', # LCD memory bit segment
+ 'LCDDR7_SEG120': '$10', # LCD memory bit segment
+ 'LCDDR7_SEG121': '$20', # LCD memory bit segment
+ 'LCDDR7_SEG122': '$40', # LCD memory bit segment
+ 'LCDDR7_SEG123': '$80', # LCD memory bit segment
+ 'LCDDR6' : '$f2', # LCD Data Register 6
+ 'LCDDR6_SEG108': '$1', # LCD memory bit segment
+ 'LCDDR6_SEG109': '$2', # LCD memory bit segment
+ 'LCDDR6_SEG110': '$4', # LCD memory bit segment
+ 'LCDDR6_SEG111': '$8', # LCD memory bit segment
+ 'LCDDR6_SEG112': '$10', # LCD memory bit segment
+ 'LCDDR6_SEG113': '$20', # LCD memory bit segment
+ 'LCDDR6_SEG114': '$40', # LCD memory bit segment
+ 'LCDDR6_SEG115': '$80', # LCD memory bit segment
+ 'LCDDR5' : '$f1', # LCD Data Register 5
+ 'LCDDR5_SEG100': '$1', # LCD memory bit segment
+ 'LCDDR5_SEG101': '$2', # LCD memory bit segment
+ 'LCDDR5_SEG102': '$4', # LCD memory bit segment
+ 'LCDDR5_SEG103': '$8', # LCD memory bit segment
+ 'LCDDR5_SEG104': '$10', # LCD memory bit segment
+ 'LCDDR5_SEG105': '$20', # LCD memory bit segment
+ 'LCDDR5_SEG106': '$40', # LCD memory bit segment
+ 'LCDDR5_SEG107': '$80', # LCD memory bit segment
+ 'LCDDR3' : '$ef', # LCD Data Register 3
+ 'LCDDR3_SEG024': '$1', # LCD memory bit segment
+ 'LCDDR3_SEG025': '$2', # LCD memory bit segment
+ 'LCDDR3_SEG026': '$4', # LCD memory bit segment
+ 'LCDDR3_SEG027': '$8', # LCD memory bit segment
+ 'LCDDR3_SEG028': '$10', # LCD memory bit segment
+ 'LCDDR3_SEG029': '$20', # LCD memory bit segment
+ 'LCDDR3_SEG030': '$40', # LCD memory bit segment
+ 'LCDDR3_SEG031': '$80', # LCD memory bit segment
+ 'LCDDR2' : '$ee', # LCD Data Register 2
+ 'LCDDR2_SEG016': '$1', # LCD memory bit segment
+ 'LCDDR2_SEG017': '$2', # LCD memory bit segment
+ 'LCDDR2_SEG018': '$4', # LCD memory bit segment
+ 'LCDDR2_SEG019': '$8', # LCD memory bit segment
+ 'LCDDR2_SEG020': '$10', # LCD memory bit segment
+ 'LCDDR2_SEG021': '$20', # LCD memory bit segment
+ 'LCDDR2_SEG022': '$40', # LCD memory bit segment
+ 'LCDDR2_SEG023': '$80', # LCD memory bit segment
+ 'LCDDR1' : '$ed', # LCD Data Register 1
+ 'LCDDR1_SEG008': '$1', # LCD memory bit segment
+ 'LCDDR1_SEG009': '$2', # LCD memory bit segment
+ 'LCDDR1_SEG010': '$4', # LCD memory bit segment
+ 'LCDDR1_SEG011': '$8', # LCD memory bit segment
+ 'LCDDR1_SEG012': '$10', # LCD memory bit segment
+ 'LCDDR1_SEG013': '$20', # LCD memory bit segment
+ 'LCDDR1_SEG014': '$40', # LCD memory bit segment
+ 'LCDDR1_SEG015': '$80', # LCD memory bit segment
+ 'LCDDR0' : '$ec', # LCD Data Register 0
+ 'LCDDR0_SEG000': '$1', # LCD memory bit segment
+ 'LCDDR0_SEG001': '$2', # LCD memory bit segment
+ 'LCDDR0_SEG002': '$4', # LCD memory bit segment
+ 'LCDDR0_SEG003': '$8', # LCD memory bit segment
+ 'LCDDR0_SEG004': '$10', # LCD memory bit segment
+ 'LCDDR0_SEG005': '$20', # LCD memory bit segment
+ 'LCDDR0_SEG006': '$40', # LCD memory bit segment
+ 'LCDDR0_SEG007': '$80', # LCD memory bit segment
+ 'LCDCCR' : '$e7', # LCD Contrast Control Register
+ 'LCDCCR_LCDDC': '$e0', #
+ 'LCDCCR_LCDMDT': '$10', # LCD Maximum Drive Time
+ 'LCDCCR_LCDCC': '$f', # LCD Contrast Controls
+ 'LCDFRR' : '$e6', # LCD Frame Rate Register
+ 'LCDFRR_LCDPS': '$70', # LCD Prescaler Selects
+ 'LCDFRR_LCDCD': '$7', # LCD Clock Dividers
+ 'LCDCRB' : '$e5', # LCD Control and Status Registe
+ 'LCDCRB_LCDCS': '$80', # LCD CLock Select
+ 'LCDCRB_LCD2B': '$40', # LCD 1/2 Bias Select
+ 'LCDCRB_LCDMUX': '$30', # LCD Mux Selects
+ 'LCDCRB_LCDPM': '$f', # LCD Port Masks
+ 'LCDCRA' : '$e4', # LCD Control Register A
+ 'LCDCRA_LCDEN': '$80', # LCD Enable
+ 'LCDCRA_LCDAB': '$40', # LCD A or B waveform
+ 'LCDCRA_LCDIF': '$10', # LCD Interrupt Flag
+ 'LCDCRA_LCDIE': '$8', # LCD Interrupt Enable
+ 'LCDCRA_LCDBD': '$4', # LCD Buffer Disable
+ 'LCDCRA_LCDCCD': '$2', # LCD Contrast Control Disable
+ 'LCDCRA_LCDBL': '$1', # LCD Blanking
+
+# Module CPU
+ 'SREG' : '$5f', # Status Register
+ 'SREG_I': '$80', # Global Interrupt Enable
+ 'SREG_T': '$40', # Bit Copy Storage
+ 'SREG_H': '$20', # Half Carry Flag
+ 'SREG_S': '$10', # Sign Bit
+ 'SREG_V': '$8', # Two's Complement Overflow Flag
+ 'SREG_N': '$4', # Negative Flag
+ 'SREG_Z': '$2', # Zero Flag
+ 'SREG_C': '$1', # Carry Flag
+ 'SP' : '$5d', # Stack Pointer
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_JTD': '$80', # JTAG Interface Disable
+ 'MCUCR_BODS': '$40', # BOD Sleep
+ 'MCUCR_BODSE': '$20', # BOD Sleep Enable
+ 'MCUCR_PUD': '$10', # Pull-up disable
+ 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
+ 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+ 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
+ 'MCUSR_BORF': '$4', # Brown-out Reset Flag
+ 'MCUSR_EXTRF': '$2', # External Reset Flag
+ 'MCUSR_PORF': '$1', # Power-on reset flag
+ 'OSCCAL' : '$66', # Oscillator Calibration Value
+ 'CLKPR' : '$61', # Clock Prescale Register
+ 'CLKPR_CLKPCE': '$80', # Clock Prescaler Change Enable
+ 'CLKPR_CLKPS': '$f', # Clock Prescaler Select Bits
+ 'PRR' : '$64', # Power Reduction Register
+ 'PRR_PRLCD': '$10', # Power Reduction LCD
+ 'PRR_PRTIM1': '$8', # Power Reduction Timer/Counter1
+ 'PRR_PRSPI': '$4', # Power Reduction Serial Periphe
+ 'PRR_PRUSART0': '$2', # Power Reduction USART
+ 'PRR_PRADC': '$1', # Power Reduction ADC
+ 'SMCR' : '$53', # Sleep Mode Control Register
+ 'SMCR_SM': '$e', # Sleep Mode Select bits
+ 'SMCR_SE': '$1', # Sleep Enable
+ 'GPIOR2' : '$4b', # General Purpose IO Register 2
+ 'GPIOR1' : '$4a', # General Purpose IO Register 1
+ 'GPIOR0' : '$3e', # General Purpose IO Register 0
+
+ '__amforth_dummy':'0'
+}
diff --git a/amforth-6.5/avr8/devices/atmega329p/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega329p/words/no-jtag.asm
new file mode 100644
index 0000000..352a4bb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega329p/words/no-jtag.asm
@@ -0,0 +1,14 @@
+; ( -- )
+; ( -- )
+; MCU
+; disable jtag at runtime
+VE_NOJTAG:
+ .dw $FF05
+ .db "-jtag",0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOJTAG
+XT_NOJTAG:
+ .dw PFA_NOJTAG
+PFA_NOJTAG:
+
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega329p/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega329p/words/no-wdt.asm
new file mode 100644
index 0000000..4a12261
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega329p/words/no-wdt.asm
@@ -0,0 +1,22 @@
+; ( -- )
+; MCU
+; disable watch dog timer at runtime
+VE_NOWDT:
+ .dw $ff04
+ .db "-wdt"
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOWDT
+XT_NOWDT:
+ .dw PFA_NOWDT
+PFA_NOWDT:
+
+; Reset WDT
+ wdr
+; Write logical one to WDTOE and WDE
+ in_ temp1, WDTCR
+ ori temp1, (1<<WDTOE)|(1<<WDE)
+ out WDTCR, temp1
+; Turn off WDT
+ ldi temp1, (0<<WDE)
+ out_ WDTCR, temp1
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega329p/words/sleep.asm b/amforth-6.5/avr8/devices/atmega329p/words/sleep.asm
new file mode 100644
index 0000000..256249c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega329p/words/sleep.asm
@@ -0,0 +1,19 @@
+; ( mode -- )
+; MCU
+; put the controller into the specified sleep mode
+VE_SLEEP:
+ .dw $ff05
+ .db "sleep", 0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_SLEEP
+XT_SLEEP:
+ .dw PFA_SLEEP
+PFA_SLEEP:
+ andi tosl, 7 ; leave only legal mode bits
+ lsl tosl ; move to correct location (bits 3-1)
+ ori tosl, 1 ; set the SE bit
+ out_ SMCR, tosl ; set the sleep config
+ sleep ; nighty-night
+ out_ SMCR, zerol ; 0 protects against accidental sleeps
+ loadtos ; pop argument from stack
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega329pa/atmega329pa.frt b/amforth-6.5/avr8/devices/atmega329pa/atmega329pa.frt
new file mode 100644
index 0000000..e93cfa7
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega329pa/atmega329pa.frt
@@ -0,0 +1,461 @@
+\ Partname: ATmega329PA
+\ generated automatically
+
+\ TIMER_COUNTER_0
+&68 constant TCCR0A \ Timer/Counter0 Control Register
+ $80 constant TCCR0A_FOC0A \ Force Output Compare
+ $40 constant TCCR0A_WGM00 \ Waveform Generation Mode 0
+ $30 constant TCCR0A_COM0A \ Compare Match Output Modes
+ $08 constant TCCR0A_WGM01 \ Waveform Generation Mode 1
+ $07 constant TCCR0A_CS0 \ Clock Selects
+&70 constant TCNT0 \ Timer/Counter0
+&71 constant OCR0A \ Timer/Counter0 Output Compare Register
+&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
+ $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match Interrupt Enable
+ $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
+&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
+ $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0
+ $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
+&67 constant GTCCR \ General Timer/Control Register
+ $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
+ $01 constant GTCCR_PSR310 \ Prescaler Reset Timer/Counter1 and Timer/Counter0
+\ TIMER_COUNTER_1
+&128 constant TCCR1A \ Timer/Counter1 Control Register A
+ $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
+ $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
+ $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
+&129 constant TCCR1B \ Timer/Counter1 Control Register B
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
+ $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
+&130 constant TCCR1C \ Timer/Counter 1 Control Register C
+ $80 constant TCCR1C_FOC1A \ Force Output Compare 1A
+ $40 constant TCCR1C_FOC1B \ Force Output Compare 1B
+&132 constant TCNT1 \ Timer/Counter1 Bytes
+&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
+&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
+&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
+&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
+ $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
+ $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
+ $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
+ $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
+&54 constant TIFR1 \ Timer/Counter1 Interrupt Flag register
+ $20 constant TIFR1_ICF1 \ Input Capture Flag 1
+ $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
+ $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
+ $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
+\ TIMER_COUNTER_2
+&176 constant TCCR2A \ Timer/Counter2 Control Register
+ $80 constant TCCR2A_FOC2A \ Force Output Compare A
+ $40 constant TCCR2A_WGM20 \ Waveform Generation Mode
+ $30 constant TCCR2A_COM2A \ Compare Output Mode bits
+ $08 constant TCCR2A_WGM21 \ Waveform Generation Mode
+ $07 constant TCCR2A_CS2 \ Clock Select bits
+&178 constant TCNT2 \ Timer/Counter2
+&179 constant OCR2A \ Timer/Counter2 Output Compare Register
+&112 constant TIMSK2 \ Timer/Counter2 Interrupt Mask register
+ $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match Interrupt Enable
+ $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
+&55 constant TIFR2 \ Timer/Counter2 Interrupt Flag Register
+ $02 constant TIFR2_OCF2A \ Timer/Counter2 Output Compare Flag 2
+ $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
+&182 constant ASSR \ Asynchronous Status Register
+ $10 constant ASSR_EXCLK \ Enable External Clock Interrupt
+ $08 constant ASSR_AS2 \ AS2: Asynchronous Timer/Counter2
+ $04 constant ASSR_TCN2UB \ TCN2UB: Timer/Counter2 Update Busy
+ $02 constant ASSR_OCR2UB \ Output Compare Register2 Update Busy
+ $01 constant ASSR_TCR2UB \ TCR2UB: Timer/Counter Control Register2 Update Busy
+\ WATCHDOG
+&96 constant WDTCR \ Watchdog Timer Control Register
+ $10 constant WDTCR_WDCE \ Watchdog Change Enable
+ $08 constant WDTCR_WDE \ Watch Dog Enable
+ $07 constant WDTCR_WDP \ Watch Dog Timer Prescaler bits
+\ EEPROM
+&65 constant EEAR \ EEPROM Read/Write Access Bytes
+&64 constant EEDR \ EEPROM Data Register
+&63 constant EECR \ EEPROM Control Register
+ $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
+ $04 constant EECR_EEMWE \ EEPROM Master Write Enable
+ $02 constant EECR_EEWE \ EEPROM Write Enable
+ $01 constant EECR_EERE \ EEPROM Read Enable
+\ SPI
+&76 constant SPCR \ SPI Control Register
+ $80 constant SPCR_SPIE \ SPI Interrupt Enable
+ $40 constant SPCR_SPE \ SPI Enable
+ $20 constant SPCR_DORD \ Data Order
+ $10 constant SPCR_MSTR \ Master/Slave Select
+ $08 constant SPCR_CPOL \ Clock polarity
+ $04 constant SPCR_CPHA \ Clock Phase
+ $03 constant SPCR_SPR \ SPI Clock Rate Selects
+&77 constant SPSR \ SPI Status Register
+ $80 constant SPSR_SPIF \ SPI Interrupt Flag
+ $40 constant SPSR_WCOL \ Write Collision Flag
+ $01 constant SPSR_SPI2X \ Double SPI Speed Bit
+&78 constant SPDR \ SPI Data Register
+\ PORTA
+&34 constant PORTA \ Port A Data Register
+&33 constant DDRA \ Port A Data Direction Register
+&32 constant PINA \ Port A Input Pins
+\ PORTB
+&37 constant PORTB \ Port B Data Register
+&36 constant DDRB \ Port B Data Direction Register
+&35 constant PINB \ Port B Input Pins
+\ PORTC
+&40 constant PORTC \ Port C Data Register
+&39 constant DDRC \ Port C Data Direction Register
+&38 constant PINC \ Port C Input Pins
+\ PORTD
+&43 constant PORTD \ Port D Data Register
+&42 constant DDRD \ Port D Data Direction Register
+&41 constant PIND \ Port D Input Pins
+\ ANALOG_COMPARATOR
+&123 constant ADCSRB \ ADC Control and Status Register B
+ $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer Enable
+&80 constant ACSR \ Analog Comparator Control And Status Register
+ $80 constant ACSR_ACD \ Analog Comparator Disable
+ $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
+ $20 constant ACSR_ACO \ Analog Compare Output
+ $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
+ $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
+ $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
+ $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
+&127 constant DIDR1 \ Digital Input Disable Register 1
+ $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
+ $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
+\ PORTE
+&46 constant PORTE \ Data Register, Port E
+&45 constant DDRE \ Data Direction Register, Port E
+&44 constant PINE \ Input Pins, Port E
+\ PORTF
+&49 constant PORTF \ Data Register, Port F
+&48 constant DDRF \ Data Direction Register, Port F
+&47 constant PINF \ Input Pins, Port F
+\ PORTG
+&52 constant PORTG \ Port G Data Register
+&51 constant DDRG \ Port G Data Direction Register
+&50 constant PING \ Port G Input Pins
+\ JTAG
+&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
+&85 constant MCUCR \ MCU Control Register
+ $80 constant MCUCR_JTD \ JTAG Interface Disable
+&84 constant MCUSR \ MCU Status Register
+ $10 constant MCUSR_JTRF \ JTAG Reset Flag
+\ EXTERNAL_INTERRUPT
+&105 constant EICRA \ External Interrupt Control Register A
+ $02 constant EICRA_ISC01 \ External Interrupt Sense Control 0 Bit 1
+ $01 constant EICRA_ISC00 \ External Interrupt Sense Control 0 Bit 0
+&61 constant EIMSK \ External Interrupt Mask Register
+ $F0 constant EIMSK_PCIE \ Pin Change Interrupt Enables
+ $01 constant EIMSK_INT0 \ External Interrupt Request 0 Enable
+&60 constant EIFR \ External Interrupt Flag Register
+ $F0 constant EIFR_PCIF \ Pin Change Interrupt Flags
+ $01 constant EIFR_INTF0 \ External Interrupt Flag 0
+&108 constant PCMSK1 \ Pin Change Mask Register 1
+ $01 constant PCMSK1_PCINT8 \ Pin Change Mask Register pin 8
+ $02 constant PCMSK1_PCINT9 \ Pin Change Mask Register pin 9
+ $04 constant PCMSK1_PCINT10 \ Pin Change Mask Register pin 10
+ $08 constant PCMSK1_PCINT11 \ Pin Change Mask Register pin 11
+ $10 constant PCMSK1_PCINT12 \ Pin Change Mask Register pin 12
+ $20 constant PCMSK1_PCINT13 \ Pin Change Mask Register pin 13
+ $40 constant PCMSK1_PCINT14 \ Pin Change Mask Register pin 14
+ $80 constant PCMSK1_PCINT15 \ Pin Change Mask Register pin 15
+&107 constant PCMSK0 \ Pin Change Mask Register 0
+ $01 constant PCMSK0_PCINT0 \ Pin Change Mask Register pin 0
+ $02 constant PCMSK0_PCINT1 \ Pin Change Mask Register pin 1
+ $04 constant PCMSK0_PCINT2 \ Pin Change Mask Register pin 2
+ $08 constant PCMSK0_PCINT3 \ Pin Change Mask Register pin 3
+ $10 constant PCMSK0_PCINT4 \ Pin Change Mask Register pin 4
+ $20 constant PCMSK0_PCINT5 \ Pin Change Mask Register pin 5
+ $40 constant PCMSK0_PCINT6 \ Pin Change Mask Register pin 6
+ $80 constant PCMSK0_PCINT7 \ Pin Change Mask Register pin 7
+\ USI
+&186 constant USIDR \ USI Data Register
+&185 constant USISR \ USI Status Register
+ $80 constant USISR_USISIF \ Start Condition Interrupt Flag
+ $40 constant USISR_USIOIF \ Counter Overflow Interrupt Flag
+ $20 constant USISR_USIPF \ Stop Condition Flag
+ $10 constant USISR_USIDC \ Data Output Collision
+ $0F constant USISR_USICNT \ USI Counter Value Bits
+&184 constant USICR \ USI Control Register
+ $80 constant USICR_USISIE \ Start Condition Interrupt Enable
+ $40 constant USICR_USIOIE \ Counter Overflow Interrupt Enable
+ $30 constant USICR_USIWM \ USI Wire Mode Bits
+ $0C constant USICR_USICS \ USI Clock Source Select Bits
+ $02 constant USICR_USICLK \ Clock Strobe
+ $01 constant USICR_USITC \ Toggle Clock Port Pin
+\ AD_CONVERTER
+&124 constant ADMUX \ The ADC multiplexer Selection Register
+ $C0 constant ADMUX_REFS \ Reference Selection Bits
+ $20 constant ADMUX_ADLAR \ Left Adjust Result
+ $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
+&122 constant ADCSRA \ The ADC Control and Status register
+ $80 constant ADCSRA_ADEN \ ADC Enable
+ $40 constant ADCSRA_ADSC \ ADC Start Conversion
+ $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
+ $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
+ $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
+ $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
+&120 constant ADC \ ADC Data Register Bytes
+&126 constant DIDR0 \ Digital Input Disable Register 0
+ $80 constant DIDR0_ADC7D \ ADC7 Digital input Disable
+ $40 constant DIDR0_ADC6D \ ADC6 Digital input Disable
+ $20 constant DIDR0_ADC5D \ ADC5 Digital input Disable
+ $10 constant DIDR0_ADC4D \ ADC4 Digital input Disable
+ $08 constant DIDR0_ADC3D \ ADC3 Digital input Disable
+ $04 constant DIDR0_ADC2D \ ADC2 Digital input Disable
+ $02 constant DIDR0_ADC1D \ ADC1 Digital input Disable
+ $01 constant DIDR0_ADC0D \ ADC0 Digital input Disable
+\ BOOT_LOAD
+&87 constant SPMCSR \ Store Program Memory Control Register
+ $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
+ $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
+ $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
+ $04 constant SPMCSR_PGWRT \ Page Write
+ $02 constant SPMCSR_PGERS \ Page Erase
+ $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
+\ USART0
+&198 constant UDR0 \ USART I/O Data Register
+&192 constant UCSR0A \ USART Control and Status Register A
+ $80 constant UCSR0A_RXC0 \ USART Receive Complete
+ $40 constant UCSR0A_TXC0 \ USART Transmit Complete
+ $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
+ $10 constant UCSR0A_FE0 \ Framing Error
+ $08 constant UCSR0A_DOR0 \ Data OverRun
+ $04 constant UCSR0A_UPE0 \ USART Parity Error
+ $02 constant UCSR0A_U2X0 \ Double the USART Transmission Speed
+ $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
+&193 constant UCSR0B \ USART Control and Status Register B
+ $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
+ $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
+ $20 constant UCSR0B_UDRIE0 \ USART Data Register Empty Interrupt Enable
+ $10 constant UCSR0B_RXEN0 \ Receiver Enable
+ $08 constant UCSR0B_TXEN0 \ Transmitter Enable
+ $04 constant UCSR0B_UCSZ02 \ Character Size
+ $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
+ $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
+&194 constant UCSR0C \ USART Control and Status Register C
+ $40 constant UCSR0C_UMSEL0 \ USART Mode Select
+ $30 constant UCSR0C_UPM0 \ Parity Mode Bits
+ $08 constant UCSR0C_USBS0 \ Stop Bit Select
+ $06 constant UCSR0C_UCSZ0 \ Character Size
+ $01 constant UCSR0C_UCPOL0 \ Clock Polarity
+&196 constant UBRR0 \ USART Baud Rate Register Bytes
+\ LCD
+&254 constant LCDDR18 \ LCD Data Register 18
+ $01 constant LCDDR18_SEG324 \ LCD memory bit segment
+ $02 constant LCDDR18_SEG325 \ LCD memory bit segment
+ $04 constant LCDDR18_SEG326 \ LCD memory bit segment
+ $08 constant LCDDR18_SEG327 \ LCD memory bit segment
+ $10 constant LCDDR18_SEG328 \ LCD memory bit segment
+ $20 constant LCDDR18_SEG329 \ LCD memory bit segment
+ $40 constant LCDDR18_SEG330 \ LCD memory bit segment
+ $80 constant LCDDR18_SEG331 \ LCD memory bit segment
+&253 constant LCDDR17 \ LCD Data Register 17
+ $01 constant LCDDR17_SEG316 \ LCD memory bit segment
+ $02 constant LCDDR17_SEG317 \ LCD memory bit segment
+ $04 constant LCDDR17_SEG318 \ LCD memory bit segment
+ $08 constant LCDDR17_SEG319 \ LCD memory bit segment
+ $10 constant LCDDR17_SEG320 \ LCD memory bit segment
+ $20 constant LCDDR17_SEG321 \ LCD memory bit segment
+ $40 constant LCDDR17_SEG322 \ LCD memory bit segment
+ $80 constant LCDDR17_SEG323 \ LCD memory bit segment
+&252 constant LCDDR16 \ LCD Data Register 16
+ $01 constant LCDDR16_SEG308 \ LCD memory bit segment
+ $02 constant LCDDR16_SEG309 \ LCD memory bit segment
+ $04 constant LCDDR16_SEG310 \ LCD memory bit segment
+ $08 constant LCDDR16_SEG311 \ LCD memory bit segment
+ $10 constant LCDDR16_SEG312 \ LCD memory bit segment
+ $20 constant LCDDR16_SEG313 \ LCD memory bit segment
+ $40 constant LCDDR16_SEG314 \ LCD memory bit segment
+ $80 constant LCDDR16_SEG315 \ LCD memory bit segment
+&251 constant LCDDR15 \ LCD Data Register 15
+ $01 constant LCDDR15_SEG300 \ LCD memory bit segment
+ $02 constant LCDDR15_SEG301 \ LCD memory bit segment
+ $04 constant LCDDR15_SEG302 \ LCD memory bit segment
+ $08 constant LCDDR15_SEG302 \ LCD memory bit segment
+ $10 constant LCDDR15_SEG304 \ LCD memory bit segment
+ $20 constant LCDDR15_SEG305 \ LCD memory bit segment
+ $40 constant LCDDR15_SEG306 \ LCD memory bit segment
+ $80 constant LCDDR15_SEG307 \ LCD memory bit segment
+&249 constant LCDDR13 \ LCD Data Register 13
+ $01 constant LCDDR13_SEG224 \ LCD memory bit segment
+ $02 constant LCDDR13_SEG225 \ LCD memory bit segment
+ $04 constant LCDDR13_SEG226 \ LCD memory bit segment
+ $08 constant LCDDR13_SEG227 \ LCD memory bit segment
+ $10 constant LCDDR13_SEG228 \ LCD memory bit segment
+ $20 constant LCDDR13_SEG229 \ LCD memory bit segment
+ $40 constant LCDDR13_SEG230 \ LCD memory bit segment
+ $80 constant LCDDR13_SEG231 \ LCD memory bit segment
+&248 constant LCDDR12 \ LCD Data Register 12
+ $01 constant LCDDR12_SEG216 \ LCD memory bit segment
+ $02 constant LCDDR12_SEG217 \ LCD memory bit segment
+ $04 constant LCDDR12_SEG218 \ LCD memory bit segment
+ $08 constant LCDDR12_SEG219 \ LCD memory bit segment
+ $10 constant LCDDR12_SEG220 \ LCD memory bit segment
+ $20 constant LCDDR12_SEG221 \ LCD memory bit segment
+ $40 constant LCDDR12_SEG222 \ LCD memory bit segment
+ $80 constant LCDDR12_SEG223 \ LCD memory bit segment
+&247 constant LCDDR11 \ LCD Data Register 11
+ $01 constant LCDDR11_SEG208 \ LCD memory bit segment
+ $02 constant LCDDR11_SEG209 \ LCD memory bit segment
+ $04 constant LCDDR11_SEG210 \ LCD memory bit segment
+ $08 constant LCDDR11_SEG211 \ LCD memory bit segment
+ $10 constant LCDDR11_SEG212 \ LCD memory bit segment
+ $20 constant LCDDR11_SEG213 \ LCD memory bit segment
+ $40 constant LCDDR11_SEG214 \ LCD memory bit segment
+ $80 constant LCDDR11_SEG215 \ LCD memory bit segment
+&246 constant LCDDR10 \ LCD Data Register 10
+ $01 constant LCDDR10_SEG200 \ LCD memory bit segment
+ $02 constant LCDDR10_SEG201 \ LCD memory bit segment
+ $04 constant LCDDR10_SEG202 \ LCD memory bit segment
+ $08 constant LCDDR10_SEG203 \ LCD memory bit segment
+ $10 constant LCDDR10_SEG204 \ LCD memory bit segment
+ $20 constant LCDDR10_SEG205 \ LCD memory bit segment
+ $40 constant LCDDR10_SEG206 \ LCD memory bit segment
+ $80 constant LCDDR10_SEG207 \ LCD memory bit segment
+&244 constant LCDDR8 \ LCD Data Register 8
+ $01 constant LCDDR8_SEG124 \ LCD memory bit segment
+ $02 constant LCDDR8_SEG125 \ LCD memory bit segment
+ $04 constant LCDDR8_SEG126 \ LCD memory bit segment
+ $08 constant LCDDR8_SEG127 \ LCD memory bit segment
+ $10 constant LCDDR8_SEG128 \ LCD memory bit segment
+ $20 constant LCDDR8_SEG129 \ LCD memory bit segment
+ $40 constant LCDDR8_SEG130 \ LCD memory bit segment
+ $80 constant LCDDR8_SEG131 \ LCD memory bit segment
+&243 constant LCDDR7 \ LCD Data Register 7
+ $01 constant LCDDR7_SEG116 \ LCD memory bit segment
+ $02 constant LCDDR7_SEG117 \ LCD memory bit segment
+ $04 constant LCDDR7_SEG118 \ LCD memory bit segment
+ $08 constant LCDDR7_SEG119 \ LCD memory bit segment
+ $10 constant LCDDR7_SEG120 \ LCD memory bit segment
+ $20 constant LCDDR7_SEG121 \ LCD memory bit segment
+ $40 constant LCDDR7_SEG122 \ LCD memory bit segment
+ $80 constant LCDDR7_SEG123 \ LCD memory bit segment
+&242 constant LCDDR6 \ LCD Data Register 6
+ $01 constant LCDDR6_SEG108 \ LCD memory bit segment
+ $02 constant LCDDR6_SEG109 \ LCD memory bit segment
+ $04 constant LCDDR6_SEG110 \ LCD memory bit segment
+ $08 constant LCDDR6_SEG111 \ LCD memory bit segment
+ $10 constant LCDDR6_SEG112 \ LCD memory bit segment
+ $20 constant LCDDR6_SEG113 \ LCD memory bit segment
+ $40 constant LCDDR6_SEG114 \ LCD memory bit segment
+ $80 constant LCDDR6_SEG115 \ LCD memory bit segment
+&241 constant LCDDR5 \ LCD Data Register 5
+ $01 constant LCDDR5_SEG100 \ LCD memory bit segment
+ $02 constant LCDDR5_SEG101 \ LCD memory bit segment
+ $04 constant LCDDR5_SEG102 \ LCD memory bit segment
+ $08 constant LCDDR5_SEG103 \ LCD memory bit segment
+ $10 constant LCDDR5_SEG104 \ LCD memory bit segment
+ $20 constant LCDDR5_SEG105 \ LCD memory bit segment
+ $40 constant LCDDR5_SEG106 \ LCD memory bit segment
+ $80 constant LCDDR5_SEG107 \ LCD memory bit segment
+&239 constant LCDDR3 \ LCD Data Register 3
+ $01 constant LCDDR3_SEG024 \ LCD memory bit segment
+ $02 constant LCDDR3_SEG025 \ LCD memory bit segment
+ $04 constant LCDDR3_SEG026 \ LCD memory bit segment
+ $08 constant LCDDR3_SEG027 \ LCD memory bit segment
+ $10 constant LCDDR3_SEG028 \ LCD memory bit segment
+ $20 constant LCDDR3_SEG029 \ LCD memory bit segment
+ $40 constant LCDDR3_SEG030 \ LCD memory bit segment
+ $80 constant LCDDR3_SEG031 \ LCD memory bit segment
+&238 constant LCDDR2 \ LCD Data Register 2
+ $01 constant LCDDR2_SEG016 \ LCD memory bit segment
+ $02 constant LCDDR2_SEG017 \ LCD memory bit segment
+ $04 constant LCDDR2_SEG018 \ LCD memory bit segment
+ $08 constant LCDDR2_SEG019 \ LCD memory bit segment
+ $10 constant LCDDR2_SEG020 \ LCD memory bit segment
+ $20 constant LCDDR2_SEG021 \ LCD memory bit segment
+ $40 constant LCDDR2_SEG022 \ LCD memory bit segment
+ $80 constant LCDDR2_SEG023 \ LCD memory bit segment
+&237 constant LCDDR1 \ LCD Data Register 1
+ $01 constant LCDDR1_SEG008 \ LCD memory bit segment
+ $02 constant LCDDR1_SEG009 \ LCD memory bit segment
+ $04 constant LCDDR1_SEG010 \ LCD memory bit segment
+ $08 constant LCDDR1_SEG011 \ LCD memory bit segment
+ $10 constant LCDDR1_SEG012 \ LCD memory bit segment
+ $20 constant LCDDR1_SEG013 \ LCD memory bit segment
+ $40 constant LCDDR1_SEG014 \ LCD memory bit segment
+ $80 constant LCDDR1_SEG015 \ LCD memory bit segment
+&236 constant LCDDR0 \ LCD Data Register 0
+ $01 constant LCDDR0_SEG000 \ LCD memory bit segment
+ $02 constant LCDDR0_SEG001 \ LCD memory bit segment
+ $04 constant LCDDR0_SEG002 \ LCD memory bit segment
+ $08 constant LCDDR0_SEG003 \ LCD memory bit segment
+ $10 constant LCDDR0_SEG004 \ LCD memory bit segment
+ $20 constant LCDDR0_SEG005 \ LCD memory bit segment
+ $40 constant LCDDR0_SEG006 \ LCD memory bit segment
+ $80 constant LCDDR0_SEG007 \ LCD memory bit segment
+&231 constant LCDCCR \ LCD Contrast Control Register
+ $E0 constant LCDCCR_LCDDC \
+ $10 constant LCDCCR_LCDMDT \ LCD Maximum Drive Time
+ $0F constant LCDCCR_LCDCC \ LCD Contrast Controls
+&230 constant LCDFRR \ LCD Frame Rate Register
+ $70 constant LCDFRR_LCDPS \ LCD Prescaler Selects
+ $07 constant LCDFRR_LCDCD \ LCD Clock Dividers
+&229 constant LCDCRB \ LCD Control and Status Register B
+ $80 constant LCDCRB_LCDCS \ LCD CLock Select
+ $40 constant LCDCRB_LCD2B \ LCD 1/2 Bias Select
+ $30 constant LCDCRB_LCDMUX \ LCD Mux Selects
+ $0F constant LCDCRB_LCDPM \ LCD Port Masks
+&228 constant LCDCRA \ LCD Control Register A
+ $80 constant LCDCRA_LCDEN \ LCD Enable
+ $40 constant LCDCRA_LCDAB \ LCD A or B waveform
+ $10 constant LCDCRA_LCDIF \ LCD Interrupt Flag
+ $08 constant LCDCRA_LCDIE \ LCD Interrupt Enable
+ $04 constant LCDCRA_LCDBD \ LCD Buffer Disable
+ $02 constant LCDCRA_LCDCCD \ LCD Contrast Control Disable
+ $01 constant LCDCRA_LCDBL \ LCD Blanking
+\ CPU
+&95 constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ $08 constant SREG_V \ Two's Complement Overflow Flag
+ $04 constant SREG_N \ Negative Flag
+ $02 constant SREG_Z \ Zero Flag
+ $01 constant SREG_C \ Carry Flag
+&93 constant SP \ Stack Pointer
+&102 constant OSCCAL \ Oscillator Calibration Value
+&97 constant CLKPR \ Clock Prescale Register
+ $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable
+ $0F constant CLKPR_CLKPS \ Clock Prescaler Select Bits
+&100 constant PRR \ Power Reduction Register
+ $10 constant PRR_PRLCD \ Power Reduction LCD
+ $08 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
+ $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
+ $02 constant PRR_PRUSART0 \ Power Reduction USART
+ $01 constant PRR_PRADC \ Power Reduction ADC
+&83 constant SMCR \ Sleep Mode Control Register
+ $0E constant SMCR_SM \ Sleep Mode Select bits
+ $01 constant SMCR_SE \ Sleep Enable
+&75 constant GPIOR2 \ General Purpose IO Register 2
+&74 constant GPIOR1 \ General Purpose IO Register 1
+&62 constant GPIOR0 \ General Purpose IO Register 0
+
+\ Interrupts
+&2 constant INT0Addr \ External Interrupt Request 0
+&4 constant PCINT0Addr \ Pin Change Interrupt Request 0
+&6 constant PCINT1Addr \ Pin Change Interrupt Request 1
+&8 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
+&10 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
+&12 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+&14 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
+&16 constant TIMER1_COMPBAddr \ Timer/Counter Compare Match B
+&18 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+&20 constant TIMER0_COMPAddr \ Timer/Counter0 Compare Match
+&22 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
+&24 constant SPI__STCAddr \ SPI Serial Transfer Complete
+&26 constant USART0__RXAddr \ USART0, Rx Complete
+&28 constant USART0__UDREAddr \ USART0 Data register Empty
+&30 constant USART0__TXAddr \ USART0, Tx Complete
+&32 constant USI_STARTAddr \ USI Start Condition
+&34 constant USI_OVERFLOWAddr \ USI Overflow
+&36 constant ANALOG_COMPAddr \ Analog Comparator
+&38 constant ADCAddr \ ADC Conversion Complete
+&40 constant EE_READYAddr \ EEPROM Ready
+&42 constant SPM_READYAddr \ Store Program Memory Read
+&44 constant LCDAddr \ LCD Start of Frame
diff --git a/amforth-6.5/avr8/devices/atmega329pa/device.asm b/amforth-6.5/avr8/devices/atmega329pa/device.asm
new file mode 100644
index 0000000..68258ab
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega329pa/device.asm
@@ -0,0 +1,109 @@
+; Partname: ATmega329PA
+; generated automatically, do not edit
+
+.nolist
+ .include "m329PAdef.inc"
+.list
+
+.equ ramstart = 256
+.equ CELLSIZE = 2
+.macro readflashcell
+ lsl zl
+ rol zh
+ lpm @0, Z+
+ lpm @1, Z+
+.endmacro
+.macro writeflashcell
+ lsl zl
+ rol zh
+.endmacro
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_TIMER_COUNTER_2 = 0
+.set WANT_WATCHDOG = 0
+.set WANT_EEPROM = 0
+.set WANT_SPI = 0
+.set WANT_PORTA = 0
+.set WANT_PORTB = 0
+.set WANT_PORTC = 0
+.set WANT_PORTD = 0
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_PORTE = 0
+.set WANT_PORTF = 0
+.set WANT_PORTG = 0
+.set WANT_JTAG = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_USI = 0
+.set WANT_AD_CONVERTER = 0
+.set WANT_BOOT_LOAD = 0
+.set WANT_USART0 = 0
+.set WANT_LCD = 0
+.set WANT_CPU = 0
+.equ intvecsize = 2 ; please verify; flash size: 32768 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.org 2
+ rcall isr ; External Interrupt Request 0
+.org 4
+ rcall isr ; Pin Change Interrupt Request 0
+.org 6
+ rcall isr ; Pin Change Interrupt Request 1
+.org 8
+ rcall isr ; Timer/Counter2 Compare Match
+.org 10
+ rcall isr ; Timer/Counter2 Overflow
+.org 12
+ rcall isr ; Timer/Counter1 Capture Event
+.org 14
+ rcall isr ; Timer/Counter1 Compare Match A
+.org 16
+ rcall isr ; Timer/Counter Compare Match B
+.org 18
+ rcall isr ; Timer/Counter1 Overflow
+.org 20
+ rcall isr ; Timer/Counter0 Compare Match
+.org 22
+ rcall isr ; Timer/Counter0 Overflow
+.org 24
+ rcall isr ; SPI Serial Transfer Complete
+.org 26
+ rcall isr ; USART0, Rx Complete
+.org 28
+ rcall isr ; USART0 Data register Empty
+.org 30
+ rcall isr ; USART0, Tx Complete
+.org 32
+ rcall isr ; USI Start Condition
+.org 34
+ rcall isr ; USI Overflow
+.org 36
+ rcall isr ; Analog Comparator
+.org 38
+ rcall isr ; ADC Conversion Complete
+.org 40
+ rcall isr ; EEPROM Ready
+.org 42
+ rcall isr ; Store Program Memory Read
+.org 44
+ rcall isr ; LCD Start of Frame
+.equ INTVECTORS = 23
+.nooverlap
+
+; compatability layer (maybe empty)
+.equ EEPE = EEWE
+.equ EEMPE = EEMWE
+
+; controller data area, environment query mcu-info
+mcu_info:
+mcu_ramsize:
+ .dw 2048
+mcu_eepromsize:
+ .dw 1024
+mcu_maxdp:
+ .dw 28672
+mcu_numints:
+ .dw 23
+mcu_name:
+ .dw 11
+ .db "ATmega329PA",0
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega329pa/device.inc b/amforth-6.5/avr8/devices/atmega329pa/device.inc
new file mode 100644
index 0000000..a37dea9
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega329pa/device.inc
@@ -0,0 +1,1293 @@
+; Partname: ATmega329PA
+; generated automatically, no not edit
+
+.if WANT_TIMER_COUNTER_0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Control Register
+VE_TCCR0A:
+ .dw $ff06
+ .db "TCCR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0A
+XT_TCCR0A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0A:
+ .dw 68
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw 70
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0A:
+ .dw $ff05
+ .db "OCR0A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0A
+XT_OCR0A:
+ .dw PFA_DOVARIABLE
+PFA_OCR0A:
+ .dw 71
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Mask Register
+VE_TIMSK0:
+ .dw $ff06
+ .db "TIMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK0
+XT_TIMSK0:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK0:
+ .dw 110
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Flag register
+VE_TIFR0:
+ .dw $ff05
+ .db "TIFR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR0
+XT_TIFR0:
+ .dw PFA_DOVARIABLE
+PFA_TIFR0:
+ .dw 53
+; ( -- addr ) System Constant
+; R( -- )
+; General Timer/Control Register
+VE_GTCCR:
+ .dw $ff05
+ .db "GTCCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GTCCR
+XT_GTCCR:
+ .dw PFA_DOVARIABLE
+PFA_GTCCR:
+ .dw 67
+
+.endif
+.if WANT_TIMER_COUNTER_1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw 128
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw 129
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter 1 Control Register C
+VE_TCCR1C:
+ .dw $ff06
+ .db "TCCR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1C
+XT_TCCR1C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1C:
+ .dw 130
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Bytes
+VE_TCNT1:
+ .dw $ff05
+ .db "TCNT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1
+XT_TCNT1:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1:
+ .dw 132
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register A Bytes
+VE_OCR1A:
+ .dw $ff05
+ .db "OCR1A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1A
+XT_OCR1A:
+ .dw PFA_DOVARIABLE
+PFA_OCR1A:
+ .dw 136
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register B Bytes
+VE_OCR1B:
+ .dw $ff05
+ .db "OCR1B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1B
+XT_OCR1B:
+ .dw PFA_DOVARIABLE
+PFA_OCR1B:
+ .dw 138
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Bytes
+VE_ICR1:
+ .dw $ff04
+ .db "ICR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1
+XT_ICR1:
+ .dw PFA_DOVARIABLE
+PFA_ICR1:
+ .dw 134
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Mask Register
+VE_TIMSK1:
+ .dw $ff06
+ .db "TIMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK1
+XT_TIMSK1:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK1:
+ .dw 111
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Flag register
+VE_TIFR1:
+ .dw $ff05
+ .db "TIFR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR1
+XT_TIFR1:
+ .dw PFA_DOVARIABLE
+PFA_TIFR1:
+ .dw 54
+
+.endif
+.if WANT_TIMER_COUNTER_2 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register
+VE_TCCR2A:
+ .dw $ff06
+ .db "TCCR2A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2A
+XT_TCCR2A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2A:
+ .dw 176
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2
+VE_TCNT2:
+ .dw $ff05
+ .db "TCNT2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT2
+XT_TCNT2:
+ .dw PFA_DOVARIABLE
+PFA_TCNT2:
+ .dw 178
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register
+VE_OCR2A:
+ .dw $ff05
+ .db "OCR2A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2A
+XT_OCR2A:
+ .dw PFA_DOVARIABLE
+PFA_OCR2A:
+ .dw 179
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Interrupt Mask register
+VE_TIMSK2:
+ .dw $ff06
+ .db "TIMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK2
+XT_TIMSK2:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK2:
+ .dw 112
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Interrupt Flag Register
+VE_TIFR2:
+ .dw $ff05
+ .db "TIFR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR2
+XT_TIFR2:
+ .dw PFA_DOVARIABLE
+PFA_TIFR2:
+ .dw 55
+; ( -- addr ) System Constant
+; R( -- )
+; Asynchronous Status Register
+VE_ASSR:
+ .dw $ff04
+ .db "ASSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ASSR
+XT_ASSR:
+ .dw PFA_DOVARIABLE
+PFA_ASSR:
+ .dw 182
+
+.endif
+.if WANT_WATCHDOG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCR:
+ .dw $ff05
+ .db "WDTCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCR
+XT_WDTCR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCR:
+ .dw 96
+
+.endif
+.if WANT_EEPROM == 1
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Read/Write Access Bytes
+VE_EEAR:
+ .dw $ff04
+ .db "EEAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEAR
+XT_EEAR:
+ .dw PFA_DOVARIABLE
+PFA_EEAR:
+ .dw 65
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw 64
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw 63
+
+.endif
+.if WANT_SPI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR:
+ .dw $ff04
+ .db "SPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR
+XT_SPCR:
+ .dw PFA_DOVARIABLE
+PFA_SPCR:
+ .dw 76
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR:
+ .dw $ff04
+ .db "SPSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR
+XT_SPSR:
+ .dw PFA_DOVARIABLE
+PFA_SPSR:
+ .dw 77
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR:
+ .dw $ff04
+ .db "SPDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR
+XT_SPDR:
+ .dw PFA_DOVARIABLE
+PFA_SPDR:
+ .dw 78
+
+.endif
+.if WANT_PORTA == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Register
+VE_PORTA:
+ .dw $ff05
+ .db "PORTA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTA
+XT_PORTA:
+ .dw PFA_DOVARIABLE
+PFA_PORTA:
+ .dw 34
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Direction Register
+VE_DDRA:
+ .dw $ff04
+ .db "DDRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRA
+XT_DDRA:
+ .dw PFA_DOVARIABLE
+PFA_DDRA:
+ .dw 33
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Input Pins
+VE_PINA:
+ .dw $ff04
+ .db "PINA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINA
+XT_PINA:
+ .dw PFA_DOVARIABLE
+PFA_PINA:
+ .dw 32
+
+.endif
+.if WANT_PORTB == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw 37
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw 36
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw 35
+
+.endif
+.if WANT_PORTC == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Register
+VE_PORTC:
+ .dw $ff05
+ .db "PORTC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTC
+XT_PORTC:
+ .dw PFA_DOVARIABLE
+PFA_PORTC:
+ .dw 40
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Direction Register
+VE_DDRC:
+ .dw $ff04
+ .db "DDRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRC
+XT_DDRC:
+ .dw PFA_DOVARIABLE
+PFA_DDRC:
+ .dw 39
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Input Pins
+VE_PINC:
+ .dw $ff04
+ .db "PINC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINC
+XT_PINC:
+ .dw PFA_DOVARIABLE
+PFA_PINC:
+ .dw 38
+
+.endif
+.if WANT_PORTD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw 43
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw 42
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw 41
+
+.endif
+.if WANT_ANALOG_COMPARATOR == 1
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Control and Status Register B
+VE_ADCSRB:
+ .dw $ff06
+ .db "ADCSRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRB
+XT_ADCSRB:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRB:
+ .dw 123
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Control And Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw 80
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 1
+VE_DIDR1:
+ .dw $ff05
+ .db "DIDR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR1
+XT_DIDR1:
+ .dw PFA_DOVARIABLE
+PFA_DIDR1:
+ .dw 127
+
+.endif
+.if WANT_PORTE == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port E
+VE_PORTE:
+ .dw $ff05
+ .db "PORTE",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTE
+XT_PORTE:
+ .dw PFA_DOVARIABLE
+PFA_PORTE:
+ .dw 46
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port E
+VE_DDRE:
+ .dw $ff04
+ .db "DDRE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRE
+XT_DDRE:
+ .dw PFA_DOVARIABLE
+PFA_DDRE:
+ .dw 45
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port E
+VE_PINE:
+ .dw $ff04
+ .db "PINE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINE
+XT_PINE:
+ .dw PFA_DOVARIABLE
+PFA_PINE:
+ .dw 44
+
+.endif
+.if WANT_PORTF == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port F
+VE_PORTF:
+ .dw $ff05
+ .db "PORTF",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTF
+XT_PORTF:
+ .dw PFA_DOVARIABLE
+PFA_PORTF:
+ .dw 49
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port F
+VE_DDRF:
+ .dw $ff04
+ .db "DDRF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRF
+XT_DDRF:
+ .dw PFA_DOVARIABLE
+PFA_DDRF:
+ .dw 48
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port F
+VE_PINF:
+ .dw $ff04
+ .db "PINF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINF
+XT_PINF:
+ .dw PFA_DOVARIABLE
+PFA_PINF:
+ .dw 47
+
+.endif
+.if WANT_PORTG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Data Register
+VE_PORTG:
+ .dw $ff05
+ .db "PORTG",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTG
+XT_PORTG:
+ .dw PFA_DOVARIABLE
+PFA_PORTG:
+ .dw 52
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Data Direction Register
+VE_DDRG:
+ .dw $ff04
+ .db "DDRG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRG
+XT_DDRG:
+ .dw PFA_DOVARIABLE
+PFA_DDRG:
+ .dw 51
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Input Pins
+VE_PING:
+ .dw $ff04
+ .db "PING"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PING
+XT_PING:
+ .dw PFA_DOVARIABLE
+PFA_PING:
+ .dw 50
+
+.endif
+.if WANT_JTAG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; On-Chip Debug Related Register in I/O Memory
+VE_OCDR:
+ .dw $ff04
+ .db "OCDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCDR
+XT_OCDR:
+ .dw PFA_DOVARIABLE
+PFA_OCDR:
+ .dw 81
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw 85
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Status Register
+VE_MCUSR:
+ .dw $ff05
+ .db "MCUSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUSR
+XT_MCUSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUSR:
+ .dw 84
+
+.endif
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register A
+VE_EICRA:
+ .dw $ff05
+ .db "EICRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRA
+XT_EICRA:
+ .dw PFA_DOVARIABLE
+PFA_EICRA:
+ .dw 105
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Mask Register
+VE_EIMSK:
+ .dw $ff05
+ .db "EIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIMSK
+XT_EIMSK:
+ .dw PFA_DOVARIABLE
+PFA_EIMSK:
+ .dw 61
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Flag Register
+VE_EIFR:
+ .dw $ff04
+ .db "EIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIFR
+XT_EIFR:
+ .dw PFA_DOVARIABLE
+PFA_EIFR:
+ .dw 60
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 1
+VE_PCMSK1:
+ .dw $ff06
+ .db "PCMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK1
+XT_PCMSK1:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK1:
+ .dw 108
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 0
+VE_PCMSK0:
+ .dw $ff06
+ .db "PCMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK0
+XT_PCMSK0:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK0:
+ .dw 107
+
+.endif
+.if WANT_USI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USI Data Register
+VE_USIDR:
+ .dw $ff05
+ .db "USIDR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USIDR
+XT_USIDR:
+ .dw PFA_DOVARIABLE
+PFA_USIDR:
+ .dw 186
+; ( -- addr ) System Constant
+; R( -- )
+; USI Status Register
+VE_USISR:
+ .dw $ff05
+ .db "USISR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USISR
+XT_USISR:
+ .dw PFA_DOVARIABLE
+PFA_USISR:
+ .dw 185
+; ( -- addr ) System Constant
+; R( -- )
+; USI Control Register
+VE_USICR:
+ .dw $ff05
+ .db "USICR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USICR
+XT_USICR:
+ .dw PFA_DOVARIABLE
+PFA_USICR:
+ .dw 184
+
+.endif
+.if WANT_AD_CONVERTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC multiplexer Selection Register
+VE_ADMUX:
+ .dw $ff05
+ .db "ADMUX",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADMUX
+XT_ADMUX:
+ .dw PFA_DOVARIABLE
+PFA_ADMUX:
+ .dw 124
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register
+VE_ADCSRA:
+ .dw $ff06
+ .db "ADCSRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRA
+XT_ADCSRA:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRA:
+ .dw 122
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register Bytes
+VE_ADC:
+ .dw $ff03
+ .db "ADC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADC
+XT_ADC:
+ .dw PFA_DOVARIABLE
+PFA_ADC:
+ .dw 120
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 0
+VE_DIDR0:
+ .dw $ff05
+ .db "DIDR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR0
+XT_DIDR0:
+ .dw PFA_DOVARIABLE
+PFA_DIDR0:
+ .dw 126
+
+.endif
+.if WANT_BOOT_LOAD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control Register
+VE_SPMCSR:
+ .dw $ff06
+ .db "SPMCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCSR
+XT_SPMCSR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCSR:
+ .dw 87
+
+.endif
+.if WANT_USART0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR0:
+ .dw $ff04
+ .db "UDR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR0
+XT_UDR0:
+ .dw PFA_DOVARIABLE
+PFA_UDR0:
+ .dw 198
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR0A:
+ .dw $ff06
+ .db "UCSR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0A
+XT_UCSR0A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0A:
+ .dw 192
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR0B:
+ .dw $ff06
+ .db "UCSR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0B
+XT_UCSR0B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0B:
+ .dw 193
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR0C:
+ .dw $ff06
+ .db "UCSR0C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0C
+XT_UCSR0C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0C:
+ .dw 194
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Bytes
+VE_UBRR0:
+ .dw $ff05
+ .db "UBRR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR0
+XT_UBRR0:
+ .dw PFA_DOVARIABLE
+PFA_UBRR0:
+ .dw 196
+
+.endif
+.if WANT_LCD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 18
+VE_LCDDR18:
+ .dw $ff07
+ .db "LCDDR18",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR18
+XT_LCDDR18:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR18:
+ .dw 254
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 17
+VE_LCDDR17:
+ .dw $ff07
+ .db "LCDDR17",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR17
+XT_LCDDR17:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR17:
+ .dw 253
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 16
+VE_LCDDR16:
+ .dw $ff07
+ .db "LCDDR16",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR16
+XT_LCDDR16:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR16:
+ .dw 252
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 15
+VE_LCDDR15:
+ .dw $ff07
+ .db "LCDDR15",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR15
+XT_LCDDR15:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR15:
+ .dw 251
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 13
+VE_LCDDR13:
+ .dw $ff07
+ .db "LCDDR13",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR13
+XT_LCDDR13:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR13:
+ .dw 249
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 12
+VE_LCDDR12:
+ .dw $ff07
+ .db "LCDDR12",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR12
+XT_LCDDR12:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR12:
+ .dw 248
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 11
+VE_LCDDR11:
+ .dw $ff07
+ .db "LCDDR11",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR11
+XT_LCDDR11:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR11:
+ .dw 247
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 10
+VE_LCDDR10:
+ .dw $ff07
+ .db "LCDDR10",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR10
+XT_LCDDR10:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR10:
+ .dw 246
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 8
+VE_LCDDR8:
+ .dw $ff06
+ .db "LCDDR8"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR8
+XT_LCDDR8:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR8:
+ .dw 244
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 7
+VE_LCDDR7:
+ .dw $ff06
+ .db "LCDDR7"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR7
+XT_LCDDR7:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR7:
+ .dw 243
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 6
+VE_LCDDR6:
+ .dw $ff06
+ .db "LCDDR6"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR6
+XT_LCDDR6:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR6:
+ .dw 242
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 5
+VE_LCDDR5:
+ .dw $ff06
+ .db "LCDDR5"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR5
+XT_LCDDR5:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR5:
+ .dw 241
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 3
+VE_LCDDR3:
+ .dw $ff06
+ .db "LCDDR3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR3
+XT_LCDDR3:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR3:
+ .dw 239
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 2
+VE_LCDDR2:
+ .dw $ff06
+ .db "LCDDR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR2
+XT_LCDDR2:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR2:
+ .dw 238
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 1
+VE_LCDDR1:
+ .dw $ff06
+ .db "LCDDR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR1
+XT_LCDDR1:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR1:
+ .dw 237
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 0
+VE_LCDDR0:
+ .dw $ff06
+ .db "LCDDR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR0
+XT_LCDDR0:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR0:
+ .dw 236
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Contrast Control Register
+VE_LCDCCR:
+ .dw $ff06
+ .db "LCDCCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDCCR
+XT_LCDCCR:
+ .dw PFA_DOVARIABLE
+PFA_LCDCCR:
+ .dw 231
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Frame Rate Register
+VE_LCDFRR:
+ .dw $ff06
+ .db "LCDFRR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDFRR
+XT_LCDFRR:
+ .dw PFA_DOVARIABLE
+PFA_LCDFRR:
+ .dw 230
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Control and Status Register B
+VE_LCDCRB:
+ .dw $ff06
+ .db "LCDCRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDCRB
+XT_LCDCRB:
+ .dw PFA_DOVARIABLE
+PFA_LCDCRB:
+ .dw 229
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Control Register A
+VE_LCDCRA:
+ .dw $ff06
+ .db "LCDCRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDCRA
+XT_LCDCRA:
+ .dw PFA_DOVARIABLE
+PFA_LCDCRA:
+ .dw 228
+
+.endif
+.if WANT_CPU == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw 95
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer
+VE_SP:
+ .dw $ff02
+ .db "SP"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SP
+XT_SP:
+ .dw PFA_DOVARIABLE
+PFA_SP:
+ .dw 93
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Calibration Value
+VE_OSCCAL:
+ .dw $ff06
+ .db "OSCCAL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSCCAL
+XT_OSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_OSCCAL:
+ .dw 102
+; ( -- addr ) System Constant
+; R( -- )
+; Clock Prescale Register
+VE_CLKPR:
+ .dw $ff05
+ .db "CLKPR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKPR
+XT_CLKPR:
+ .dw PFA_DOVARIABLE
+PFA_CLKPR:
+ .dw 97
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register
+VE_PRR:
+ .dw $ff03
+ .db "PRR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR
+XT_PRR:
+ .dw PFA_DOVARIABLE
+PFA_PRR:
+ .dw 100
+; ( -- addr ) System Constant
+; R( -- )
+; Sleep Mode Control Register
+VE_SMCR:
+ .dw $ff04
+ .db "SMCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SMCR
+XT_SMCR:
+ .dw PFA_DOVARIABLE
+PFA_SMCR:
+ .dw 83
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 2
+VE_GPIOR2:
+ .dw $ff06
+ .db "GPIOR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR2
+XT_GPIOR2:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR2:
+ .dw 75
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 1
+VE_GPIOR1:
+ .dw $ff06
+ .db "GPIOR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR1
+XT_GPIOR1:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR1:
+ .dw 74
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 0
+VE_GPIOR0:
+ .dw $ff06
+ .db "GPIOR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR0
+XT_GPIOR0:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR0:
+ .dw 62
+
+.endif
diff --git a/amforth-6.5/avr8/devices/atmega329pa/device.py b/amforth-6.5/avr8/devices/atmega329pa/device.py
new file mode 100644
index 0000000..2b36098
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega329pa/device.py
@@ -0,0 +1,504 @@
+# Generated Automatically
+
+# Partname ATmega329PA
+
+MCUREGS = {
+# Interrupt Vectors
+ 'INT0Addr' : '#2', # External Interrupt Request 0
+ 'PCINT0Addr' : '#4', # Pin Change Interrupt Request 0
+ 'PCINT1Addr' : '#6', # Pin Change Interrupt Request 1
+ 'TIMER2_COMPAddr' : '#8', # Timer/Counter2 Compare Match
+ 'TIMER2_OVFAddr' : '#10', # Timer/Counter2 Overflow
+ 'TIMER1_CAPTAddr' : '#12', # Timer/Counter1 Capture Event
+ 'TIMER1_COMPAAddr' : '#14', # Timer/Counter1 Compare Match A
+ 'TIMER1_COMPBAddr' : '#16', # Timer/Counter Compare Match B
+ 'TIMER1_OVFAddr' : '#18', # Timer/Counter1 Overflow
+ 'TIMER0_COMPAddr' : '#20', # Timer/Counter0 Compare Match
+ 'TIMER0_OVFAddr' : '#22', # Timer/Counter0 Overflow
+ 'SPI_STCAddr' : '#24', # SPI Serial Transfer Complete
+ 'USART0_RXAddr' : '#26', # USART0, Rx Complete
+ 'USART0_UDREAddr' : '#28', # USART0 Data register Empty
+ 'USART0_TXAddr' : '#30', # USART0, Tx Complete
+ 'USI_STARTAddr' : '#32', # USI Start Condition
+ 'USI_OVERFLOWAddr' : '#34', # USI Overflow
+ 'ANALOG_COMPAddr' : '#36', # Analog Comparator
+ 'ADCAddr' : '#38', # ADC Conversion Complete
+ 'EE_READYAddr' : '#40', # EEPROM Ready
+ 'SPM_READYAddr' : '#42', # Store Program Memory Read
+ 'LCDAddr' : '#44', # LCD Start of Frame
+
+# Module TIMER_COUNTER_0
+ 'TCCR0A' : '$44', # Timer/Counter0 Control Registe
+ 'TCCR0A_FOC0A': '$80', # Force Output Compare
+ 'TCCR0A_WGM00': '$40', # Waveform Generation Mode 0
+ 'TCCR0A_COM0A': '$30', # Compare Match Output Modes
+ 'TCCR0A_WGM01': '$8', # Waveform Generation Mode 1
+ 'TCCR0A_CS0': '$7', # Clock Selects
+ 'TCNT0' : '$46', # Timer/Counter0
+ 'OCR0A' : '$47', # Timer/Counter0 Output Compare
+ 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
+ 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
+ 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
+ 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
+ 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
+ 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Control Register
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSR310': '$1', # Prescaler Reset Timer/Counter1
+
+# Module TIMER_COUNTER_1
+ 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
+ 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
+ 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
+ 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
+ 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
+ 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
+ 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
+ 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
+ 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
+ 'TCCR1C' : '$82', # Timer/Counter 1 Control Regist
+ 'TCCR1C_FOC1A': '$80', # Force Output Compare 1A
+ 'TCCR1C_FOC1B': '$40', # Force Output Compare 1B
+ 'TCNT1' : '$84', # Timer/Counter1 Bytes
+ 'OCR1A' : '$88', # Timer/Counter1 Output Compare
+ 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
+ 'ICR1' : '$86', # Timer/Counter1 Input Capture R
+ 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
+ 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
+ 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
+ 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
+ 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
+ 'TIFR1' : '$36', # Timer/Counter1 Interrupt Flag
+ 'TIFR1_ICF1': '$20', # Input Capture Flag 1
+ 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
+ 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
+ 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
+
+# Module TIMER_COUNTER_2
+ 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
+ 'TCCR2A_FOC2A': '$80', # Force Output Compare A
+ 'TCCR2A_WGM20': '$40', # Waveform Generation Mode
+ 'TCCR2A_COM2A': '$30', # Compare Output Mode bits
+ 'TCCR2A_WGM21': '$8', # Waveform Generation Mode
+ 'TCCR2A_CS2': '$7', # Clock Select bits
+ 'TCNT2' : '$b2', # Timer/Counter2
+ 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
+ 'TIMSK2' : '$70', # Timer/Counter2 Interrupt Mask
+ 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
+ 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
+ 'TIFR2' : '$37', # Timer/Counter2 Interrupt Flag
+ 'TIFR2_OCF2A': '$2', # Timer/Counter2 Output Compare
+ 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_PSR2': '$2', # Prescaler Reset Timer/Counter2
+ 'ASSR' : '$b6', # Asynchronous Status Register
+ 'ASSR_EXCLK': '$10', # Enable External Clock Interrup
+ 'ASSR_AS2': '$8', # AS2: Asynchronous Timer/Counte
+ 'ASSR_TCN2UB': '$4', # TCN2UB: Timer/Counter2 Update
+ 'ASSR_OCR2UB': '$2', # Output Compare Register2 Updat
+ 'ASSR_TCR2UB': '$1', # TCR2UB: Timer/Counter Control
+
+# Module WATCHDOG
+ 'WDTCR' : '$60', # Watchdog Timer Control Registe
+ 'WDTCR_WDCE': '$10', # Watchdog Change Enable
+ 'WDTCR_WDE': '$8', # Watch Dog Enable
+ 'WDTCR_WDP': '$7', # Watch Dog Timer Prescaler bits
+
+# Module EEPROM
+ 'EEAR' : '$41', # EEPROM Read/Write Access Byte
+ 'EEDR' : '$40', # EEPROM Data Register
+ 'EECR' : '$3f', # EEPROM Control Register
+ 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
+ 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
+ 'EECR_EEWE': '$2', # EEPROM Write Enable
+ 'EECR_EERE': '$1', # EEPROM Read Enable
+
+# Module SPI
+ 'SPCR' : '$4c', # SPI Control Register
+ 'SPCR_SPIE': '$80', # SPI Interrupt Enable
+ 'SPCR_SPE': '$40', # SPI Enable
+ 'SPCR_DORD': '$20', # Data Order
+ 'SPCR_MSTR': '$10', # Master/Slave Select
+ 'SPCR_CPOL': '$8', # Clock polarity
+ 'SPCR_CPHA': '$4', # Clock Phase
+ 'SPCR_SPR': '$3', # SPI Clock Rate Selects
+ 'SPSR' : '$4d', # SPI Status Register
+ 'SPSR_SPIF': '$80', # SPI Interrupt Flag
+ 'SPSR_WCOL': '$40', # Write Collision Flag
+ 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
+ 'SPDR' : '$4e', # SPI Data Register
+
+# Module PORTA
+ 'PORTA' : '$22', # Port A Data Register
+ 'DDRA' : '$21', # Port A Data Direction Register
+ 'PINA' : '$20', # Port A Input Pins
+
+# Module PORTB
+ 'PORTB' : '$25', # Port B Data Register
+ 'DDRB' : '$24', # Port B Data Direction Register
+ 'PINB' : '$23', # Port B Input Pins
+
+# Module PORTC
+ 'PORTC' : '$28', # Port C Data Register
+ 'DDRC' : '$27', # Port C Data Direction Register
+ 'PINC' : '$26', # Port C Input Pins
+
+# Module PORTD
+ 'PORTD' : '$2b', # Port D Data Register
+ 'DDRD' : '$2a', # Port D Data Direction Register
+ 'PIND' : '$29', # Port D Input Pins
+
+# Module ANALOG_COMPARATOR
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
+ 'ACSR' : '$50', # Analog Comparator Control And
+ 'ACSR_ACD': '$80', # Analog Comparator Disable
+ 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
+ 'ACSR_ACO': '$20', # Analog Compare Output
+ 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
+ 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
+ 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
+ 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
+ 'DIDR1' : '$7f', # Digital Input Disable Register
+ 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
+ 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
+
+# Module PORTE
+ 'PORTE' : '$2e', # Data Register, Port E
+ 'DDRE' : '$2d', # Data Direction Register, Port
+ 'PINE' : '$2c', # Input Pins, Port E
+
+# Module PORTF
+ 'PORTF' : '$31', # Data Register, Port F
+ 'DDRF' : '$30', # Data Direction Register, Port
+ 'PINF' : '$2f', # Input Pins, Port F
+
+# Module PORTG
+ 'PORTG' : '$34', # Port G Data Register
+ 'DDRG' : '$33', # Port G Data Direction Register
+ 'PING' : '$32', # Port G Input Pins
+
+# Module JTAG
+ 'OCDR' : '$51', # On-Chip Debug Related Register
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_JTD': '$80', # JTAG Interface Disable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+
+# Module EXTERNAL_INTERRUPT
+ 'EICRA' : '$69', # External Interrupt Control Reg
+ 'EICRA_ISC01': '$2', # External Interrupt Sense Contr
+ 'EICRA_ISC00': '$1', # External Interrupt Sense Contr
+ 'EIMSK' : '$3d', # External Interrupt Mask Regist
+ 'EIMSK_PCIE': '$f0', # Pin Change Interrupt Enables
+ 'EIMSK_INT0': '$1', # External Interrupt Request 0 E
+ 'EIFR' : '$3c', # External Interrupt Flag Regist
+ 'EIFR_PCIF': '$f0', # Pin Change Interrupt Flags
+ 'EIFR_INTF0': '$1', # External Interrupt Flag 0
+ 'PCMSK1' : '$6c', # Pin Change Mask Register 1
+ 'PCMSK1_PCINT8': '$1', # Pin Change Mask Register pin 8
+ 'PCMSK1_PCINT9': '$2', # Pin Change Mask Register pin 9
+ 'PCMSK1_PCINT10': '$4', # Pin Change Mask Register pin 1
+ 'PCMSK1_PCINT11': '$8', # Pin Change Mask Register pin 1
+ 'PCMSK1_PCINT12': '$10', # Pin Change Mask Register pin 1
+ 'PCMSK1_PCINT13': '$20', # Pin Change Mask Register pin 1
+ 'PCMSK1_PCINT14': '$40', # Pin Change Mask Register pin 1
+ 'PCMSK1_PCINT15': '$80', # Pin Change Mask Register pin 1
+ 'PCMSK0' : '$6b', # Pin Change Mask Register 0
+ 'PCMSK0_PCINT0': '$1', # Pin Change Mask Register pin 0
+ 'PCMSK0_PCINT1': '$2', # Pin Change Mask Register pin 1
+ 'PCMSK0_PCINT2': '$4', # Pin Change Mask Register pin 2
+ 'PCMSK0_PCINT3': '$8', # Pin Change Mask Register pin 3
+ 'PCMSK0_PCINT4': '$10', # Pin Change Mask Register pin 4
+ 'PCMSK0_PCINT5': '$20', # Pin Change Mask Register pin 5
+ 'PCMSK0_PCINT6': '$40', # Pin Change Mask Register pin 6
+ 'PCMSK0_PCINT7': '$80', # Pin Change Mask Register pin 7
+
+# Module USI
+ 'USIDR' : '$ba', # USI Data Register
+ 'USISR' : '$b9', # USI Status Register
+ 'USISR_USISIF': '$80', # Start Condition Interrupt Flag
+ 'USISR_USIOIF': '$40', # Counter Overflow Interrupt Fla
+ 'USISR_USIPF': '$20', # Stop Condition Flag
+ 'USISR_USIDC': '$10', # Data Output Collision
+ 'USISR_USICNT': '$f', # USI Counter Value Bits
+ 'USICR' : '$b8', # USI Control Register
+ 'USICR_USISIE': '$80', # Start Condition Interrupt Enab
+ 'USICR_USIOIE': '$40', # Counter Overflow Interrupt Ena
+ 'USICR_USIWM': '$30', # USI Wire Mode Bits
+ 'USICR_USICS': '$c', # USI Clock Source Select Bits
+ 'USICR_USICLK': '$2', # Clock Strobe
+ 'USICR_USITC': '$1', # Toggle Clock Port Pin
+
+# Module AD_CONVERTER
+ 'ADMUX' : '$7c', # The ADC multiplexer Selection
+ 'ADMUX_REFS': '$c0', # Reference Selection Bits
+ 'ADMUX_ADLAR': '$20', # Left Adjust Result
+ 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
+ 'ADCSRA' : '$7a', # The ADC Control and Status reg
+ 'ADCSRA_ADEN': '$80', # ADC Enable
+ 'ADCSRA_ADSC': '$40', # ADC Start Conversion
+ 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
+ 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
+ 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
+ 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
+ 'ADC' : '$78', # ADC Data Register Bytes
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Sources
+ 'DIDR0' : '$7e', # Digital Input Disable Register
+ 'DIDR0_ADC7D': '$80', # ADC7 Digital input Disable
+ 'DIDR0_ADC6D': '$40', # ADC6 Digital input Disable
+ 'DIDR0_ADC5D': '$20', # ADC5 Digital input Disable
+ 'DIDR0_ADC4D': '$10', # ADC4 Digital input Disable
+ 'DIDR0_ADC3D': '$8', # ADC3 Digital input Disable
+ 'DIDR0_ADC2D': '$4', # ADC2 Digital input Disable
+ 'DIDR0_ADC1D': '$2', # ADC1 Digital input Disable
+ 'DIDR0_ADC0D': '$1', # ADC0 Digital input Disable
+
+# Module BOOT_LOAD
+ 'SPMCSR' : '$57', # Store Program Memory Control R
+ 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
+ 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
+ 'SPMCSR_RWWSRE': '$10', # Read While Write section read
+ 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
+ 'SPMCSR_PGWRT': '$4', # Page Write
+ 'SPMCSR_PGERS': '$2', # Page Erase
+ 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
+
+# Module USART0
+ 'UDR0' : '$c6', # USART I/O Data Register
+ 'UCSR0A' : '$c0', # USART Control and Status Regis
+ 'UCSR0A_RXC0': '$80', # USART Receive Complete
+ 'UCSR0A_TXC0': '$40', # USART Transmit Complete
+ 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
+ 'UCSR0A_FE0': '$10', # Framing Error
+ 'UCSR0A_DOR0': '$8', # Data OverRun
+ 'UCSR0A_UPE0': '$4', # USART Parity Error
+ 'UCSR0A_U2X0': '$2', # Double the USART Transmission
+ 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
+ 'UCSR0B' : '$c1', # USART Control and Status Regis
+ 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
+ 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
+ 'UCSR0B_UDRIE0': '$20', # USART Data Register Empty Inte
+ 'UCSR0B_RXEN0': '$10', # Receiver Enable
+ 'UCSR0B_TXEN0': '$8', # Transmitter Enable
+ 'UCSR0B_UCSZ02': '$4', # Character Size
+ 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
+ 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
+ 'UCSR0C' : '$c2', # USART Control and Status Regis
+ 'UCSR0C_UMSEL0': '$40', # USART Mode Select
+ 'UCSR0C_UPM0': '$30', # Parity Mode Bits
+ 'UCSR0C_USBS0': '$8', # Stop Bit Select
+ 'UCSR0C_UCSZ0': '$6', # Character Size
+ 'UCSR0C_UCPOL0': '$1', # Clock Polarity
+ 'UBRR0' : '$c4', # USART Baud Rate Register Byte
+
+# Module LCD
+ 'LCDDR18' : '$fe', # LCD Data Register 18
+ 'LCDDR18_SEG324': '$1', # LCD memory bit segment
+ 'LCDDR18_SEG325': '$2', # LCD memory bit segment
+ 'LCDDR18_SEG326': '$4', # LCD memory bit segment
+ 'LCDDR18_SEG327': '$8', # LCD memory bit segment
+ 'LCDDR18_SEG328': '$10', # LCD memory bit segment
+ 'LCDDR18_SEG329': '$20', # LCD memory bit segment
+ 'LCDDR18_SEG330': '$40', # LCD memory bit segment
+ 'LCDDR18_SEG331': '$80', # LCD memory bit segment
+ 'LCDDR17' : '$fd', # LCD Data Register 17
+ 'LCDDR17_SEG316': '$1', # LCD memory bit segment
+ 'LCDDR17_SEG317': '$2', # LCD memory bit segment
+ 'LCDDR17_SEG318': '$4', # LCD memory bit segment
+ 'LCDDR17_SEG319': '$8', # LCD memory bit segment
+ 'LCDDR17_SEG320': '$10', # LCD memory bit segment
+ 'LCDDR17_SEG321': '$20', # LCD memory bit segment
+ 'LCDDR17_SEG322': '$40', # LCD memory bit segment
+ 'LCDDR17_SEG323': '$80', # LCD memory bit segment
+ 'LCDDR16' : '$fc', # LCD Data Register 16
+ 'LCDDR16_SEG308': '$1', # LCD memory bit segment
+ 'LCDDR16_SEG309': '$2', # LCD memory bit segment
+ 'LCDDR16_SEG310': '$4', # LCD memory bit segment
+ 'LCDDR16_SEG311': '$8', # LCD memory bit segment
+ 'LCDDR16_SEG312': '$10', # LCD memory bit segment
+ 'LCDDR16_SEG313': '$20', # LCD memory bit segment
+ 'LCDDR16_SEG314': '$40', # LCD memory bit segment
+ 'LCDDR16_SEG315': '$80', # LCD memory bit segment
+ 'LCDDR15' : '$fb', # LCD Data Register 15
+ 'LCDDR15_SEG300': '$1', # LCD memory bit segment
+ 'LCDDR15_SEG301': '$2', # LCD memory bit segment
+ 'LCDDR15_SEG302': '$4', # LCD memory bit segment
+ 'LCDDR15_SEG302': '$8', # LCD memory bit segment
+ 'LCDDR15_SEG304': '$10', # LCD memory bit segment
+ 'LCDDR15_SEG305': '$20', # LCD memory bit segment
+ 'LCDDR15_SEG306': '$40', # LCD memory bit segment
+ 'LCDDR15_SEG307': '$80', # LCD memory bit segment
+ 'LCDDR13' : '$f9', # LCD Data Register 13
+ 'LCDDR13_SEG224': '$1', # LCD memory bit segment
+ 'LCDDR13_SEG225': '$2', # LCD memory bit segment
+ 'LCDDR13_SEG226': '$4', # LCD memory bit segment
+ 'LCDDR13_SEG227': '$8', # LCD memory bit segment
+ 'LCDDR13_SEG228': '$10', # LCD memory bit segment
+ 'LCDDR13_SEG229': '$20', # LCD memory bit segment
+ 'LCDDR13_SEG230': '$40', # LCD memory bit segment
+ 'LCDDR13_SEG231': '$80', # LCD memory bit segment
+ 'LCDDR12' : '$f8', # LCD Data Register 12
+ 'LCDDR12_SEG216': '$1', # LCD memory bit segment
+ 'LCDDR12_SEG217': '$2', # LCD memory bit segment
+ 'LCDDR12_SEG218': '$4', # LCD memory bit segment
+ 'LCDDR12_SEG219': '$8', # LCD memory bit segment
+ 'LCDDR12_SEG220': '$10', # LCD memory bit segment
+ 'LCDDR12_SEG221': '$20', # LCD memory bit segment
+ 'LCDDR12_SEG222': '$40', # LCD memory bit segment
+ 'LCDDR12_SEG223': '$80', # LCD memory bit segment
+ 'LCDDR11' : '$f7', # LCD Data Register 11
+ 'LCDDR11_SEG208': '$1', # LCD memory bit segment
+ 'LCDDR11_SEG209': '$2', # LCD memory bit segment
+ 'LCDDR11_SEG210': '$4', # LCD memory bit segment
+ 'LCDDR11_SEG211': '$8', # LCD memory bit segment
+ 'LCDDR11_SEG212': '$10', # LCD memory bit segment
+ 'LCDDR11_SEG213': '$20', # LCD memory bit segment
+ 'LCDDR11_SEG214': '$40', # LCD memory bit segment
+ 'LCDDR11_SEG215': '$80', # LCD memory bit segment
+ 'LCDDR10' : '$f6', # LCD Data Register 10
+ 'LCDDR10_SEG200': '$1', # LCD memory bit segment
+ 'LCDDR10_SEG201': '$2', # LCD memory bit segment
+ 'LCDDR10_SEG202': '$4', # LCD memory bit segment
+ 'LCDDR10_SEG203': '$8', # LCD memory bit segment
+ 'LCDDR10_SEG204': '$10', # LCD memory bit segment
+ 'LCDDR10_SEG205': '$20', # LCD memory bit segment
+ 'LCDDR10_SEG206': '$40', # LCD memory bit segment
+ 'LCDDR10_SEG207': '$80', # LCD memory bit segment
+ 'LCDDR8' : '$f4', # LCD Data Register 8
+ 'LCDDR8_SEG124': '$1', # LCD memory bit segment
+ 'LCDDR8_SEG125': '$2', # LCD memory bit segment
+ 'LCDDR8_SEG126': '$4', # LCD memory bit segment
+ 'LCDDR8_SEG127': '$8', # LCD memory bit segment
+ 'LCDDR8_SEG128': '$10', # LCD memory bit segment
+ 'LCDDR8_SEG129': '$20', # LCD memory bit segment
+ 'LCDDR8_SEG130': '$40', # LCD memory bit segment
+ 'LCDDR8_SEG131': '$80', # LCD memory bit segment
+ 'LCDDR7' : '$f3', # LCD Data Register 7
+ 'LCDDR7_SEG116': '$1', # LCD memory bit segment
+ 'LCDDR7_SEG117': '$2', # LCD memory bit segment
+ 'LCDDR7_SEG118': '$4', # LCD memory bit segment
+ 'LCDDR7_SEG119': '$8', # LCD memory bit segment
+ 'LCDDR7_SEG120': '$10', # LCD memory bit segment
+ 'LCDDR7_SEG121': '$20', # LCD memory bit segment
+ 'LCDDR7_SEG122': '$40', # LCD memory bit segment
+ 'LCDDR7_SEG123': '$80', # LCD memory bit segment
+ 'LCDDR6' : '$f2', # LCD Data Register 6
+ 'LCDDR6_SEG108': '$1', # LCD memory bit segment
+ 'LCDDR6_SEG109': '$2', # LCD memory bit segment
+ 'LCDDR6_SEG110': '$4', # LCD memory bit segment
+ 'LCDDR6_SEG111': '$8', # LCD memory bit segment
+ 'LCDDR6_SEG112': '$10', # LCD memory bit segment
+ 'LCDDR6_SEG113': '$20', # LCD memory bit segment
+ 'LCDDR6_SEG114': '$40', # LCD memory bit segment
+ 'LCDDR6_SEG115': '$80', # LCD memory bit segment
+ 'LCDDR5' : '$f1', # LCD Data Register 5
+ 'LCDDR5_SEG100': '$1', # LCD memory bit segment
+ 'LCDDR5_SEG101': '$2', # LCD memory bit segment
+ 'LCDDR5_SEG102': '$4', # LCD memory bit segment
+ 'LCDDR5_SEG103': '$8', # LCD memory bit segment
+ 'LCDDR5_SEG104': '$10', # LCD memory bit segment
+ 'LCDDR5_SEG105': '$20', # LCD memory bit segment
+ 'LCDDR5_SEG106': '$40', # LCD memory bit segment
+ 'LCDDR5_SEG107': '$80', # LCD memory bit segment
+ 'LCDDR3' : '$ef', # LCD Data Register 3
+ 'LCDDR3_SEG024': '$1', # LCD memory bit segment
+ 'LCDDR3_SEG025': '$2', # LCD memory bit segment
+ 'LCDDR3_SEG026': '$4', # LCD memory bit segment
+ 'LCDDR3_SEG027': '$8', # LCD memory bit segment
+ 'LCDDR3_SEG028': '$10', # LCD memory bit segment
+ 'LCDDR3_SEG029': '$20', # LCD memory bit segment
+ 'LCDDR3_SEG030': '$40', # LCD memory bit segment
+ 'LCDDR3_SEG031': '$80', # LCD memory bit segment
+ 'LCDDR2' : '$ee', # LCD Data Register 2
+ 'LCDDR2_SEG016': '$1', # LCD memory bit segment
+ 'LCDDR2_SEG017': '$2', # LCD memory bit segment
+ 'LCDDR2_SEG018': '$4', # LCD memory bit segment
+ 'LCDDR2_SEG019': '$8', # LCD memory bit segment
+ 'LCDDR2_SEG020': '$10', # LCD memory bit segment
+ 'LCDDR2_SEG021': '$20', # LCD memory bit segment
+ 'LCDDR2_SEG022': '$40', # LCD memory bit segment
+ 'LCDDR2_SEG023': '$80', # LCD memory bit segment
+ 'LCDDR1' : '$ed', # LCD Data Register 1
+ 'LCDDR1_SEG008': '$1', # LCD memory bit segment
+ 'LCDDR1_SEG009': '$2', # LCD memory bit segment
+ 'LCDDR1_SEG010': '$4', # LCD memory bit segment
+ 'LCDDR1_SEG011': '$8', # LCD memory bit segment
+ 'LCDDR1_SEG012': '$10', # LCD memory bit segment
+ 'LCDDR1_SEG013': '$20', # LCD memory bit segment
+ 'LCDDR1_SEG014': '$40', # LCD memory bit segment
+ 'LCDDR1_SEG015': '$80', # LCD memory bit segment
+ 'LCDDR0' : '$ec', # LCD Data Register 0
+ 'LCDDR0_SEG000': '$1', # LCD memory bit segment
+ 'LCDDR0_SEG001': '$2', # LCD memory bit segment
+ 'LCDDR0_SEG002': '$4', # LCD memory bit segment
+ 'LCDDR0_SEG003': '$8', # LCD memory bit segment
+ 'LCDDR0_SEG004': '$10', # LCD memory bit segment
+ 'LCDDR0_SEG005': '$20', # LCD memory bit segment
+ 'LCDDR0_SEG006': '$40', # LCD memory bit segment
+ 'LCDDR0_SEG007': '$80', # LCD memory bit segment
+ 'LCDCCR' : '$e7', # LCD Contrast Control Register
+ 'LCDCCR_LCDDC': '$e0', #
+ 'LCDCCR_LCDMDT': '$10', # LCD Maximum Drive Time
+ 'LCDCCR_LCDCC': '$f', # LCD Contrast Controls
+ 'LCDFRR' : '$e6', # LCD Frame Rate Register
+ 'LCDFRR_LCDPS': '$70', # LCD Prescaler Selects
+ 'LCDFRR_LCDCD': '$7', # LCD Clock Dividers
+ 'LCDCRB' : '$e5', # LCD Control and Status Registe
+ 'LCDCRB_LCDCS': '$80', # LCD CLock Select
+ 'LCDCRB_LCD2B': '$40', # LCD 1/2 Bias Select
+ 'LCDCRB_LCDMUX': '$30', # LCD Mux Selects
+ 'LCDCRB_LCDPM': '$f', # LCD Port Masks
+ 'LCDCRA' : '$e4', # LCD Control Register A
+ 'LCDCRA_LCDEN': '$80', # LCD Enable
+ 'LCDCRA_LCDAB': '$40', # LCD A or B waveform
+ 'LCDCRA_LCDIF': '$10', # LCD Interrupt Flag
+ 'LCDCRA_LCDIE': '$8', # LCD Interrupt Enable
+ 'LCDCRA_LCDBD': '$4', # LCD Buffer Disable
+ 'LCDCRA_LCDCCD': '$2', # LCD Contrast Control Disable
+ 'LCDCRA_LCDBL': '$1', # LCD Blanking
+
+# Module CPU
+ 'SREG' : '$5f', # Status Register
+ 'SREG_I': '$80', # Global Interrupt Enable
+ 'SREG_T': '$40', # Bit Copy Storage
+ 'SREG_H': '$20', # Half Carry Flag
+ 'SREG_S': '$10', # Sign Bit
+ 'SREG_V': '$8', # Two's Complement Overflow Flag
+ 'SREG_N': '$4', # Negative Flag
+ 'SREG_Z': '$2', # Zero Flag
+ 'SREG_C': '$1', # Carry Flag
+ 'SP' : '$5d', # Stack Pointer
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_JTD': '$80', # JTAG Interface Disable
+ 'MCUCR_BODS': '$40', # BOD Sleep
+ 'MCUCR_BODSE': '$20', # BOD Sleep Enable
+ 'MCUCR_PUD': '$10', # Pull-up disable
+ 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
+ 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+ 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
+ 'MCUSR_BORF': '$4', # Brown-out Reset Flag
+ 'MCUSR_EXTRF': '$2', # External Reset Flag
+ 'MCUSR_PORF': '$1', # Power-on reset flag
+ 'OSCCAL' : '$66', # Oscillator Calibration Value
+ 'CLKPR' : '$61', # Clock Prescale Register
+ 'CLKPR_CLKPCE': '$80', # Clock Prescaler Change Enable
+ 'CLKPR_CLKPS': '$f', # Clock Prescaler Select Bits
+ 'PRR' : '$64', # Power Reduction Register
+ 'PRR_PRLCD': '$10', # Power Reduction LCD
+ 'PRR_PRTIM1': '$8', # Power Reduction Timer/Counter1
+ 'PRR_PRSPI': '$4', # Power Reduction Serial Periphe
+ 'PRR_PRUSART0': '$2', # Power Reduction USART
+ 'PRR_PRADC': '$1', # Power Reduction ADC
+ 'SMCR' : '$53', # Sleep Mode Control Register
+ 'SMCR_SM': '$e', # Sleep Mode Select bits
+ 'SMCR_SE': '$1', # Sleep Enable
+ 'GPIOR2' : '$4b', # General Purpose IO Register 2
+ 'GPIOR1' : '$4a', # General Purpose IO Register 1
+ 'GPIOR0' : '$3e', # General Purpose IO Register 0
+
+ '__amforth_dummy':'0'
+}
diff --git a/amforth-6.5/avr8/devices/atmega329pa/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega329pa/words/no-jtag.asm
new file mode 100644
index 0000000..352a4bb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega329pa/words/no-jtag.asm
@@ -0,0 +1,14 @@
+; ( -- )
+; ( -- )
+; MCU
+; disable jtag at runtime
+VE_NOJTAG:
+ .dw $FF05
+ .db "-jtag",0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOJTAG
+XT_NOJTAG:
+ .dw PFA_NOJTAG
+PFA_NOJTAG:
+
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega329pa/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega329pa/words/no-wdt.asm
new file mode 100644
index 0000000..4a12261
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega329pa/words/no-wdt.asm
@@ -0,0 +1,22 @@
+; ( -- )
+; MCU
+; disable watch dog timer at runtime
+VE_NOWDT:
+ .dw $ff04
+ .db "-wdt"
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOWDT
+XT_NOWDT:
+ .dw PFA_NOWDT
+PFA_NOWDT:
+
+; Reset WDT
+ wdr
+; Write logical one to WDTOE and WDE
+ in_ temp1, WDTCR
+ ori temp1, (1<<WDTOE)|(1<<WDE)
+ out WDTCR, temp1
+; Turn off WDT
+ ldi temp1, (0<<WDE)
+ out_ WDTCR, temp1
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega329pa/words/sleep.asm b/amforth-6.5/avr8/devices/atmega329pa/words/sleep.asm
new file mode 100644
index 0000000..256249c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega329pa/words/sleep.asm
@@ -0,0 +1,19 @@
+; ( mode -- )
+; MCU
+; put the controller into the specified sleep mode
+VE_SLEEP:
+ .dw $ff05
+ .db "sleep", 0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_SLEEP
+XT_SLEEP:
+ .dw PFA_SLEEP
+PFA_SLEEP:
+ andi tosl, 7 ; leave only legal mode bits
+ lsl tosl ; move to correct location (bits 3-1)
+ ori tosl, 1 ; set the SE bit
+ out_ SMCR, tosl ; set the sleep config
+ sleep ; nighty-night
+ out_ SMCR, zerol ; 0 protects against accidental sleeps
+ loadtos ; pop argument from stack
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega32a/atmega32a.frt b/amforth-6.5/avr8/devices/atmega32a/atmega32a.frt
new file mode 100644
index 0000000..d904f82
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega32a/atmega32a.frt
@@ -0,0 +1,216 @@
+\ Partname: ATmega32A
+\ generated automatically
+
+\ EEPROM
+&62 constant EEAR \ EEPROM Read/Write Access Bytes
+&61 constant EEDR \ EEPROM Data Register
+&60 constant EECR \ EEPROM Control Register
+ $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
+ $04 constant EECR_EEMWE \ EEPROM Master Write Enable
+ $02 constant EECR_EEWE \ EEPROM Write Enable
+ $01 constant EECR_EERE \ EEPROM Read Enable
+\ WATCHDOG
+&65 constant WDTCR \ Watchdog Timer Control Register
+ $10 constant WDTCR_WDTOE \ RW
+ $08 constant WDTCR_WDE \ Watch Dog Enable
+ $07 constant WDTCR_WDP \ Watch Dog Timer Prescaler bits
+\ EXTERNAL_INTERRUPT
+&91 constant GICR \ General Interrupt Control Register
+ $C0 constant GICR_INT \ External Interrupt Request 1 Enable
+ $20 constant GICR_INT2 \ External Interrupt Request 2 Enable
+ $02 constant GICR_IVSEL \ Interrupt Vector Select
+ $01 constant GICR_IVCE \ Interrupt Vector Change Enable
+&90 constant GIFR \ General Interrupt Flag Register
+ $C0 constant GIFR_INTF \ External Interrupt Flags
+ $20 constant GIFR_INTF2 \ External Interrupt Flag 2
+&85 constant MCUCR \ General Interrupt Control Register
+ $0C constant MCUCR_ISC1 \ Interrupt Sense Control 1 Bits
+ $03 constant MCUCR_ISC0 \ Interrupt Sense Control 0 Bits
+&84 constant MCUCSR \ MCU Control And Status Register
+ $40 constant MCUCSR_ISC2 \ Interrupt Sense Control 2
+\ TIMER_COUNTER_0
+&83 constant TCCR0 \ Timer/Counter Control Register
+ $80 constant TCCR0_FOC0 \ Force Output Compare
+ $40 constant TCCR0_WGM00 \ Waveform Generation Mode
+ $30 constant TCCR0_COM0 \ Compare Match Output Modes
+ $08 constant TCCR0_WGM01 \ Waveform Generation Mode 1
+ $07 constant TCCR0_CS0 \ Clock Selects
+&82 constant TCNT0 \ Timer/Counter Register
+&92 constant OCR0 \ Output Compare Register
+&89 constant TIMSK \ Timer/Counter Interrupt Mask Register
+ $02 constant TIMSK_OCIE0 \ Timer/Counter0 Output Compare Match Interrupt register
+ $01 constant TIMSK_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
+&88 constant TIFR \ Timer/Counter Interrupt Flag register
+ $02 constant TIFR_OCF0 \ Output Compare Flag 0
+ $01 constant TIFR_TOV0 \ Timer/Counter0 Overflow Flag
+\ TIMER_COUNTER_2
+&69 constant TCCR2 \ Timer/Counter2 Control Register
+ $80 constant TCCR2_FOC2 \ Force Output Compare
+ $40 constant TCCR2_WGM20 \ Pulse Width Modulator Enable
+ $30 constant TCCR2_COM2 \ Compare Output Mode bits
+ $08 constant TCCR2_WGM21 \ Clear Timer/Counter2 on Compare Match
+ $07 constant TCCR2_CS2 \ Clock Select bits
+&68 constant TCNT2 \ Timer/Counter2
+&67 constant OCR2 \ Timer/Counter2 Output Compare Register
+&66 constant ASSR \ Asynchronous Status Register
+ $08 constant ASSR_AS2 \ Asynchronous Timer/counter2
+ $04 constant ASSR_TCN2UB \ Timer/Counter2 Update Busy
+ $02 constant ASSR_OCR2UB \ Output Compare Register2 Update Busy
+ $01 constant ASSR_TCR2UB \ Timer/counter Control Register2 Update Busy
+\ TIMER_COUNTER_1
+&79 constant TCCR1A \ Timer/Counter1 Control Register A
+ $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
+ $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
+ $08 constant TCCR1A_FOC1A \ Force Output Compare 1A
+ $04 constant TCCR1A_FOC1B \ Force Output Compare 1B
+ $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
+&78 constant TCCR1B \ Timer/Counter1 Control Register B
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
+ $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
+&76 constant TCNT1 \ Timer/Counter1 Bytes
+&74 constant OCR1A \ Timer/Counter1 Output Compare Register Bytes
+&72 constant OCR1B \ Timer/Counter1 Output Compare Register Bytes
+&70 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
+\ SPI
+&47 constant SPDR \ SPI Data Register
+&46 constant SPSR \ SPI Status Register
+ $80 constant SPSR_SPIF \ SPI Interrupt Flag
+ $40 constant SPSR_WCOL \ Write Collision Flag
+ $01 constant SPSR_SPI2X \ Double SPI Speed Bit
+&45 constant SPCR \ SPI Control Register
+ $80 constant SPCR_SPIE \ SPI Interrupt Enable
+ $40 constant SPCR_SPE \ SPI Enable
+ $20 constant SPCR_DORD \ Data Order
+ $10 constant SPCR_MSTR \ Master/Slave Select
+ $08 constant SPCR_CPOL \ Clock polarity
+ $04 constant SPCR_CPHA \ Clock Phase
+ $03 constant SPCR_SPR \ SPI Clock Rate Selects
+\ USART
+&44 constant UDR \ USART I/O Data Register
+&43 constant UCSRA \ USART Control and Status Register A
+ $80 constant UCSRA_RXC \ USART Receive Complete
+ $40 constant UCSRA_TXC \ USART Transmitt Complete
+ $20 constant UCSRA_UDRE \ USART Data Register Empty
+ $10 constant UCSRA_FE \ Framing Error
+ $08 constant UCSRA_DOR \ Data overRun
+ $04 constant UCSRA_UPE \ Parity Error
+ $02 constant UCSRA_U2X \ Double the USART transmission speed
+ $01 constant UCSRA_MPCM \ Multi-processor Communication Mode
+&42 constant UCSRB \ USART Control and Status Register B
+ $80 constant UCSRB_RXCIE \ RX Complete Interrupt Enable
+ $40 constant UCSRB_TXCIE \ TX Complete Interrupt Enable
+ $20 constant UCSRB_UDRIE \ USART Data register Empty Interrupt Enable
+ $10 constant UCSRB_RXEN \ Receiver Enable
+ $08 constant UCSRB_TXEN \ Transmitter Enable
+ $04 constant UCSRB_UCSZ2 \ Character Size
+ $02 constant UCSRB_RXB8 \ Receive Data Bit 8
+ $01 constant UCSRB_TXB8 \ Transmit Data Bit 8
+&64 constant UCSRC \ USART Control and Status Register C
+ $80 constant UCSRC_URSEL \ Register Select
+ $40 constant UCSRC_UMSEL \ USART Mode Select
+ $30 constant UCSRC_UPM \ Parity Mode Bits
+ $08 constant UCSRC_USBS \ Stop Bit Select
+ $06 constant UCSRC_UCSZ \ Character Size
+ $01 constant UCSRC_UCPOL \ Clock Polarity
+&64 constant UBRRH \ USART Baud Rate Register Hight Byte
+&41 constant UBRRL \ USART Baud Rate Register Low Byte
+\ ANALOG_COMPARATOR
+&80 constant SFIOR \ Special Function IO Register
+ $08 constant SFIOR_ACME \ Analog Comparator Multiplexer Enable
+&40 constant ACSR \ Analog Comparator Control And Status Register
+ $80 constant ACSR_ACD \ Analog Comparator Disable
+ $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
+ $20 constant ACSR_ACO \ Analog Compare Output
+ $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
+ $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
+ $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
+ $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
+\ AD_CONVERTER
+&39 constant ADMUX \ The ADC multiplexer Selection Register
+ $C0 constant ADMUX_REFS \ Reference Selection Bits
+ $20 constant ADMUX_ADLAR \ Left Adjust Result
+ $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
+&38 constant ADCSRA \ The ADC Control and Status register
+ $80 constant ADCSRA_ADEN \ ADC Enable
+ $40 constant ADCSRA_ADSC \ ADC Start Conversion
+ $20 constant ADCSRA_ADATE \ When this bit is written to one,the Timer/Counter2 prescaler will be reset.The bit will be cleared by hardware after the operation is performed.Writing a zero to this bit will have no effect.This bit will always be read as zero if Timer/Counter2 is clocked by the internal CPU clock.If this bit is written when Timer/Counter2 is operating in asynchronous mode,the bit will remain one until the prescaler has been reset.
+ $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
+ $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
+ $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
+&36 constant ADC \ ADC Data Register Bytes
+\ PORTA
+&59 constant PORTA \ Port A Data Register
+&58 constant DDRA \ Port A Data Direction Register
+&57 constant PINA \ Port A Input Pins
+\ PORTB
+&56 constant PORTB \ Port B Data Register
+&55 constant DDRB \ Port B Data Direction Register
+&54 constant PINB \ Port B Input Pins
+\ PORTC
+&53 constant PORTC \ Port C Data Register
+&52 constant DDRC \ Port C Data Direction Register
+&51 constant PINC \ Port C Input Pins
+\ PORTD
+&50 constant PORTD \ Port D Data Register
+&49 constant DDRD \ Port D Data Direction Register
+&48 constant PIND \ Port D Input Pins
+\ CPU
+&95 constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ $08 constant SREG_V \ Two's Complement Overflow Flag
+ $04 constant SREG_N \ Negative Flag
+ $02 constant SREG_Z \ Zero Flag
+ $01 constant SREG_C \ Carry Flag
+&93 constant SP \ Stack Pointer
+&81 constant OSCCAL \ Oscillator Calibration Value
+\ BOOT_LOAD
+&87 constant SPMCR \ Store Program Memory Control Register
+ $80 constant SPMCR_SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCR_RWWSB \ Read While Write Section Busy
+ $10 constant SPMCR_RWWSRE \ Read While Write secion read enable
+ $08 constant SPMCR_BLBSET \ Boot Lock Bit Set
+ $04 constant SPMCR_PGWRT \ Page Write
+ $02 constant SPMCR_PGERS \ Page Erase
+ $01 constant SPMCR_SPMEN \ Store Program Memory Enable
+\ TWI
+&32 constant TWBR \ TWI Bit Rate register
+&86 constant TWCR \ TWI Control Register
+ $80 constant TWCR_TWINT \ TWI Interrupt Flag
+ $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
+ $20 constant TWCR_TWSTA \ TWI Start Condition Bit
+ $10 constant TWCR_TWSTO \ TWI Stop Condition Bit
+ $08 constant TWCR_TWWC \ TWI Write Collition Flag
+ $04 constant TWCR_TWEN \ TWI Enable Bit
+ $01 constant TWCR_TWIE \ TWI Interrupt Enable
+&33 constant TWSR \ TWI Status Register
+ $F8 constant TWSR_TWS \ TWI Status
+ $03 constant TWSR_TWPS \ TWI Prescaler bits
+&35 constant TWDR \ TWI Data register
+&34 constant TWAR \ TWI (Slave) Address register
+
+\ Interrupts
+&2 constant INT0Addr \ External Interrupt Request 0
+&4 constant INT1Addr \ External Interrupt Request 1
+&6 constant INT2Addr \ External Interrupt Request 2
+&8 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
+&10 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
+&12 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+&14 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
+&16 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
+&18 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+&20 constant TIMER0_COMPAddr \ Timer/Counter0 Compare Match
+&22 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
+&24 constant SPI__STCAddr \ Serial Transfer Complete
+&26 constant USART__RXCAddr \ USART, Rx Complete
+&28 constant USART__UDREAddr \ USART Data Register Empty
+&30 constant USART__TXCAddr \ USART, Tx Complete
+&32 constant ADCAddr \ ADC Conversion Complete
+&34 constant EE_RDYAddr \ EEPROM Ready
+&36 constant ANA_COMPAddr \ Analog Comparator
+&38 constant TWIAddr \ 2-wire Serial Interface
+&40 constant SPM_RDYAddr \ Store Program Memory Ready
diff --git a/amforth-6.5/avr8/devices/atmega32a/device.asm b/amforth-6.5/avr8/devices/atmega32a/device.asm
new file mode 100644
index 0000000..3b8ea38
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega32a/device.asm
@@ -0,0 +1,101 @@
+; Partname: ATmega32A
+; generated automatically, do not edit
+
+.nolist
+ .include "m32Adef.inc"
+.list
+
+.equ ramstart = 96
+.equ CELLSIZE = 2
+.macro readflashcell
+ lsl zl
+ rol zh
+ lpm @0, Z+
+ lpm @1, Z+
+.endmacro
+.macro writeflashcell
+ lsl zl
+ rol zh
+.endmacro
+.set WANT_EEPROM = 0
+.set WANT_WATCHDOG = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_TIMER_COUNTER_2 = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_SPI = 0
+.set WANT_USART = 0
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_AD_CONVERTER = 0
+.set WANT_PORTA = 0
+.set WANT_PORTB = 0
+.set WANT_PORTC = 0
+.set WANT_PORTD = 0
+.set WANT_CPU = 0
+.set WANT_BOOT_LOAD = 0
+.set WANT_TWI = 0
+.equ intvecsize = 2 ; please verify; flash size: 32768 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.org 2
+ rcall isr ; External Interrupt Request 0
+.org 4
+ rcall isr ; External Interrupt Request 1
+.org 6
+ rcall isr ; External Interrupt Request 2
+.org 8
+ rcall isr ; Timer/Counter2 Compare Match
+.org 10
+ rcall isr ; Timer/Counter2 Overflow
+.org 12
+ rcall isr ; Timer/Counter1 Capture Event
+.org 14
+ rcall isr ; Timer/Counter1 Compare Match A
+.org 16
+ rcall isr ; Timer/Counter1 Compare Match B
+.org 18
+ rcall isr ; Timer/Counter1 Overflow
+.org 20
+ rcall isr ; Timer/Counter0 Compare Match
+.org 22
+ rcall isr ; Timer/Counter0 Overflow
+.org 24
+ rcall isr ; Serial Transfer Complete
+.org 26
+ rcall isr ; USART, Rx Complete
+.org 28
+ rcall isr ; USART Data Register Empty
+.org 30
+ rcall isr ; USART, Tx Complete
+.org 32
+ rcall isr ; ADC Conversion Complete
+.org 34
+ rcall isr ; EEPROM Ready
+.org 36
+ rcall isr ; Analog Comparator
+.org 38
+ rcall isr ; 2-wire Serial Interface
+.org 40
+ rcall isr ; Store Program Memory Ready
+.equ INTVECTORS = 21
+.nooverlap
+
+; compatability layer (maybe empty)
+.equ SPMCSR = SPMCR
+.equ EEPE = EEWE
+.equ EEMPE = EEMWE
+
+; controller data area, environment query mcu-info
+mcu_info:
+mcu_ramsize:
+ .dw 2048
+mcu_eepromsize:
+ .dw 1024
+mcu_maxdp:
+ .dw 28672
+mcu_numints:
+ .dw 21
+mcu_name:
+ .dw 9
+ .db "ATmega32A",0
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega32a/device.inc b/amforth-6.5/avr8/devices/atmega32a/device.inc
new file mode 100644
index 0000000..2098148
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega32a/device.inc
@@ -0,0 +1,750 @@
+; Partname: ATmega32A
+; generated automatically, no not edit
+
+.if WANT_EEPROM == 1
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Read/Write Access Bytes
+VE_EEAR:
+ .dw $ff04
+ .db "EEAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEAR
+XT_EEAR:
+ .dw PFA_DOVARIABLE
+PFA_EEAR:
+ .dw 62
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw 61
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw 60
+
+.endif
+.if WANT_WATCHDOG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCR:
+ .dw $ff05
+ .db "WDTCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCR
+XT_WDTCR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCR:
+ .dw 65
+
+.endif
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ( -- addr ) System Constant
+; R( -- )
+; General Interrupt Control Register
+VE_GICR:
+ .dw $ff04
+ .db "GICR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GICR
+XT_GICR:
+ .dw PFA_DOVARIABLE
+PFA_GICR:
+ .dw 91
+; ( -- addr ) System Constant
+; R( -- )
+; General Interrupt Flag Register
+VE_GIFR:
+ .dw $ff04
+ .db "GIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GIFR
+XT_GIFR:
+ .dw PFA_DOVARIABLE
+PFA_GIFR:
+ .dw 90
+; ( -- addr ) System Constant
+; R( -- )
+; General Interrupt Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw 85
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control And Status Register
+VE_MCUCSR:
+ .dw $ff06
+ .db "MCUCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCSR
+XT_MCUCSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCSR:
+ .dw 84
+
+.endif
+.if WANT_TIMER_COUNTER_0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register
+VE_TCCR0:
+ .dw $ff05
+ .db "TCCR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0
+XT_TCCR0:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0:
+ .dw 83
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Register
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw 82
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare Register
+VE_OCR0:
+ .dw $ff04
+ .db "OCR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0
+XT_OCR0:
+ .dw PFA_DOVARIABLE
+PFA_OCR0:
+ .dw 92
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Mask Register
+VE_TIMSK:
+ .dw $ff05
+ .db "TIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK
+XT_TIMSK:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK:
+ .dw 89
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Flag register
+VE_TIFR:
+ .dw $ff04
+ .db "TIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR
+XT_TIFR:
+ .dw PFA_DOVARIABLE
+PFA_TIFR:
+ .dw 88
+
+.endif
+.if WANT_TIMER_COUNTER_2 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register
+VE_TCCR2:
+ .dw $ff05
+ .db "TCCR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2
+XT_TCCR2:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2:
+ .dw 69
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2
+VE_TCNT2:
+ .dw $ff05
+ .db "TCNT2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT2
+XT_TCNT2:
+ .dw PFA_DOVARIABLE
+PFA_TCNT2:
+ .dw 68
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register
+VE_OCR2:
+ .dw $ff04
+ .db "OCR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2
+XT_OCR2:
+ .dw PFA_DOVARIABLE
+PFA_OCR2:
+ .dw 67
+; ( -- addr ) System Constant
+; R( -- )
+; Asynchronous Status Register
+VE_ASSR:
+ .dw $ff04
+ .db "ASSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ASSR
+XT_ASSR:
+ .dw PFA_DOVARIABLE
+PFA_ASSR:
+ .dw 66
+
+.endif
+.if WANT_TIMER_COUNTER_1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw 79
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw 78
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Bytes
+VE_TCNT1:
+ .dw $ff05
+ .db "TCNT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1
+XT_TCNT1:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1:
+ .dw 76
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register Bytes
+VE_OCR1A:
+ .dw $ff05
+ .db "OCR1A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1A
+XT_OCR1A:
+ .dw PFA_DOVARIABLE
+PFA_OCR1A:
+ .dw 74
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register Bytes
+VE_OCR1B:
+ .dw $ff05
+ .db "OCR1B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1B
+XT_OCR1B:
+ .dw PFA_DOVARIABLE
+PFA_OCR1B:
+ .dw 72
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Bytes
+VE_ICR1:
+ .dw $ff04
+ .db "ICR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1
+XT_ICR1:
+ .dw PFA_DOVARIABLE
+PFA_ICR1:
+ .dw 70
+
+.endif
+.if WANT_SPI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR:
+ .dw $ff04
+ .db "SPDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR
+XT_SPDR:
+ .dw PFA_DOVARIABLE
+PFA_SPDR:
+ .dw 47
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR:
+ .dw $ff04
+ .db "SPSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR
+XT_SPSR:
+ .dw PFA_DOVARIABLE
+PFA_SPSR:
+ .dw 46
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR:
+ .dw $ff04
+ .db "SPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR
+XT_SPCR:
+ .dw PFA_DOVARIABLE
+PFA_SPCR:
+ .dw 45
+
+.endif
+.if WANT_USART == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR:
+ .dw $ff03
+ .db "UDR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR
+XT_UDR:
+ .dw PFA_DOVARIABLE
+PFA_UDR:
+ .dw 44
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSRA:
+ .dw $ff05
+ .db "UCSRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSRA
+XT_UCSRA:
+ .dw PFA_DOVARIABLE
+PFA_UCSRA:
+ .dw 43
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSRB:
+ .dw $ff05
+ .db "UCSRB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSRB
+XT_UCSRB:
+ .dw PFA_DOVARIABLE
+PFA_UCSRB:
+ .dw 42
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSRC:
+ .dw $ff05
+ .db "UCSRC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSRC
+XT_UCSRC:
+ .dw PFA_DOVARIABLE
+PFA_UCSRC:
+ .dw 64
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Hight Byte
+VE_UBRRH:
+ .dw $ff05
+ .db "UBRRH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRRH
+XT_UBRRH:
+ .dw PFA_DOVARIABLE
+PFA_UBRRH:
+ .dw 64
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Low Byte
+VE_UBRRL:
+ .dw $ff05
+ .db "UBRRL",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRRL
+XT_UBRRL:
+ .dw PFA_DOVARIABLE
+PFA_UBRRL:
+ .dw 41
+
+.endif
+.if WANT_ANALOG_COMPARATOR == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Special Function IO Register
+VE_SFIOR:
+ .dw $ff05
+ .db "SFIOR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SFIOR
+XT_SFIOR:
+ .dw PFA_DOVARIABLE
+PFA_SFIOR:
+ .dw 80
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Control And Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw 40
+
+.endif
+.if WANT_AD_CONVERTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC multiplexer Selection Register
+VE_ADMUX:
+ .dw $ff05
+ .db "ADMUX",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADMUX
+XT_ADMUX:
+ .dw PFA_DOVARIABLE
+PFA_ADMUX:
+ .dw 39
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register
+VE_ADCSRA:
+ .dw $ff06
+ .db "ADCSRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRA
+XT_ADCSRA:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRA:
+ .dw 38
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register Bytes
+VE_ADC:
+ .dw $ff03
+ .db "ADC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADC
+XT_ADC:
+ .dw PFA_DOVARIABLE
+PFA_ADC:
+ .dw 36
+
+.endif
+.if WANT_PORTA == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Register
+VE_PORTA:
+ .dw $ff05
+ .db "PORTA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTA
+XT_PORTA:
+ .dw PFA_DOVARIABLE
+PFA_PORTA:
+ .dw 59
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Direction Register
+VE_DDRA:
+ .dw $ff04
+ .db "DDRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRA
+XT_DDRA:
+ .dw PFA_DOVARIABLE
+PFA_DDRA:
+ .dw 58
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Input Pins
+VE_PINA:
+ .dw $ff04
+ .db "PINA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINA
+XT_PINA:
+ .dw PFA_DOVARIABLE
+PFA_PINA:
+ .dw 57
+
+.endif
+.if WANT_PORTB == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw 56
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw 55
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw 54
+
+.endif
+.if WANT_PORTC == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Register
+VE_PORTC:
+ .dw $ff05
+ .db "PORTC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTC
+XT_PORTC:
+ .dw PFA_DOVARIABLE
+PFA_PORTC:
+ .dw 53
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Direction Register
+VE_DDRC:
+ .dw $ff04
+ .db "DDRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRC
+XT_DDRC:
+ .dw PFA_DOVARIABLE
+PFA_DDRC:
+ .dw 52
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Input Pins
+VE_PINC:
+ .dw $ff04
+ .db "PINC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINC
+XT_PINC:
+ .dw PFA_DOVARIABLE
+PFA_PINC:
+ .dw 51
+
+.endif
+.if WANT_PORTD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw 50
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw 49
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw 48
+
+.endif
+.if WANT_CPU == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw 95
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer
+VE_SP:
+ .dw $ff02
+ .db "SP"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SP
+XT_SP:
+ .dw PFA_DOVARIABLE
+PFA_SP:
+ .dw 93
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Calibration Value
+VE_OSCCAL:
+ .dw $ff06
+ .db "OSCCAL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSCCAL
+XT_OSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_OSCCAL:
+ .dw 81
+
+.endif
+.if WANT_BOOT_LOAD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control Register
+VE_SPMCR:
+ .dw $ff05
+ .db "SPMCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCR
+XT_SPMCR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCR:
+ .dw 87
+
+.endif
+.if WANT_TWI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Bit Rate register
+VE_TWBR:
+ .dw $ff04
+ .db "TWBR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWBR
+XT_TWBR:
+ .dw PFA_DOVARIABLE
+PFA_TWBR:
+ .dw 32
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Control Register
+VE_TWCR:
+ .dw $ff04
+ .db "TWCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWCR
+XT_TWCR:
+ .dw PFA_DOVARIABLE
+PFA_TWCR:
+ .dw 86
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Status Register
+VE_TWSR:
+ .dw $ff04
+ .db "TWSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWSR
+XT_TWSR:
+ .dw PFA_DOVARIABLE
+PFA_TWSR:
+ .dw 33
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Data register
+VE_TWDR:
+ .dw $ff04
+ .db "TWDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWDR
+XT_TWDR:
+ .dw PFA_DOVARIABLE
+PFA_TWDR:
+ .dw 35
+; ( -- addr ) System Constant
+; R( -- )
+; TWI (Slave) Address register
+VE_TWAR:
+ .dw $ff04
+ .db "TWAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWAR
+XT_TWAR:
+ .dw PFA_DOVARIABLE
+PFA_TWAR:
+ .dw 34
+
+.endif
diff --git a/amforth-6.5/avr8/devices/atmega32a/device.py b/amforth-6.5/avr8/devices/atmega32a/device.py
new file mode 100644
index 0000000..f6913ba
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega32a/device.py
@@ -0,0 +1,268 @@
+# Generated Automatically
+
+# Partname ATmega32A
+
+MCUREGS = {
+# Interrupt Vectors
+ 'INT0Addr' : '#2', # External Interrupt Request 0
+ 'INT1Addr' : '#4', # External Interrupt Request 1
+ 'INT2Addr' : '#6', # External Interrupt Request 2
+ 'TIMER2_COMPAddr' : '#8', # Timer/Counter2 Compare Match
+ 'TIMER2_OVFAddr' : '#10', # Timer/Counter2 Overflow
+ 'TIMER1_CAPTAddr' : '#12', # Timer/Counter1 Capture Event
+ 'TIMER1_COMPAAddr' : '#14', # Timer/Counter1 Compare Match A
+ 'TIMER1_COMPBAddr' : '#16', # Timer/Counter1 Compare Match B
+ 'TIMER1_OVFAddr' : '#18', # Timer/Counter1 Overflow
+ 'TIMER0_COMPAddr' : '#20', # Timer/Counter0 Compare Match
+ 'TIMER0_OVFAddr' : '#22', # Timer/Counter0 Overflow
+ 'SPI_STCAddr' : '#24', # Serial Transfer Complete
+ 'USART_RXCAddr' : '#26', # USART, Rx Complete
+ 'USART_UDREAddr' : '#28', # USART Data Register Empty
+ 'USART_TXCAddr' : '#30', # USART, Tx Complete
+ 'ADCAddr' : '#32', # ADC Conversion Complete
+ 'EE_RDYAddr' : '#34', # EEPROM Ready
+ 'ANA_COMPAddr' : '#36', # Analog Comparator
+ 'TWIAddr' : '#38', # 2-wire Serial Interface
+ 'SPM_RDYAddr' : '#40', # Store Program Memory Ready
+
+# Module EEPROM
+ 'EEAR' : '$3e', # EEPROM Read/Write Access Byte
+ 'EEDR' : '$3d', # EEPROM Data Register
+ 'EECR' : '$3c', # EEPROM Control Register
+ 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
+ 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
+ 'EECR_EEWE': '$2', # EEPROM Write Enable
+ 'EECR_EERE': '$1', # EEPROM Read Enable
+
+# Module WATCHDOG
+ 'WDTCR' : '$41', # Watchdog Timer Control Registe
+ 'WDTCR_WDTOE': '$10', # RW
+ 'WDTCR_WDE': '$8', # Watch Dog Enable
+ 'WDTCR_WDP': '$7', # Watch Dog Timer Prescaler bits
+
+# Module EXTERNAL_INTERRUPT
+ 'GICR' : '$5b', # General Interrupt Control Regi
+ 'GICR_INT': '$c0', # External Interrupt Request 1 E
+ 'GICR_INT2': '$20', # External Interrupt Request 2 E
+ 'GICR_IVSEL': '$2', # Interrupt Vector Select
+ 'GICR_IVCE': '$1', # Interrupt Vector Change Enable
+ 'GIFR' : '$5a', # General Interrupt Flag Registe
+ 'GIFR_INTF': '$c0', # External Interrupt Flags
+ 'GIFR_INTF2': '$20', # External Interrupt Flag 2
+ 'MCUCR' : '$55', # General Interrupt Control Regi
+ 'MCUCR_ISC1': '$c', # Interrupt Sense Control 1 Bits
+ 'MCUCR_ISC0': '$3', # Interrupt Sense Control 0 Bits
+ 'MCUCSR' : '$54', # MCU Control And Status Registe
+ 'MCUCSR_ISC2': '$40', # Interrupt Sense Control 2
+
+# Module TIMER_COUNTER_0
+ 'TCCR0' : '$53', # Timer/Counter Control Register
+ 'TCCR0_FOC0': '$80', # Force Output Compare
+ 'TCCR0_WGM00': '$40', # Waveform Generation Mode
+ 'TCCR0_COM0': '$30', # Compare Match Output Modes
+ 'TCCR0_WGM01': '$8', # Waveform Generation Mode 1
+ 'TCCR0_CS0': '$7', # Clock Selects
+ 'TCNT0' : '$52', # Timer/Counter Register
+ 'OCR0' : '$5c', # Output Compare Register
+ 'TIMSK' : '$59', # Timer/Counter Interrupt Mask R
+ 'TIMSK_OCIE0': '$2', # Timer/Counter0 Output Compare
+ 'TIMSK_TOIE0': '$1', # Timer/Counter0 Overflow Interr
+ 'TIFR' : '$58', # Timer/Counter Interrupt Flag r
+ 'TIFR_OCF0': '$2', # Output Compare Flag 0
+ 'TIFR_TOV0': '$1', # Timer/Counter0 Overflow Flag
+
+# Module TIMER_COUNTER_2
+ 'TIMSK' : '$59', # Timer/Counter Interrupt Mask r
+ 'TIMSK_OCIE2': '$80', # Timer/Counter2 Output Compare
+ 'TIMSK_TOIE2': '$40', # Timer/Counter2 Overflow Interr
+ 'TIFR' : '$58', # Timer/Counter Interrupt Flag R
+ 'TIFR_OCF2': '$80', # Output Compare Flag 2
+ 'TIFR_TOV2': '$40', # Timer/Counter2 Overflow Flag
+ 'TCCR2' : '$45', # Timer/Counter2 Control Registe
+ 'TCCR2_FOC2': '$80', # Force Output Compare
+ 'TCCR2_WGM20': '$40', # Pulse Width Modulator Enable
+ 'TCCR2_COM2': '$30', # Compare Output Mode bits
+ 'TCCR2_WGM21': '$8', # Clear Timer/Counter2 on Compar
+ 'TCCR2_CS2': '$7', # Clock Select bits
+ 'TCNT2' : '$44', # Timer/Counter2
+ 'OCR2' : '$43', # Timer/Counter2 Output Compare
+ 'ASSR' : '$42', # Asynchronous Status Register
+ 'ASSR_AS2': '$8', # Asynchronous Timer/counter2
+ 'ASSR_TCN2UB': '$4', # Timer/Counter2 Update Busy
+ 'ASSR_OCR2UB': '$2', # Output Compare Register2 Updat
+ 'ASSR_TCR2UB': '$1', # Timer/counter Control Register
+
+# Module TIMER_COUNTER_1
+ 'TIMSK' : '$59', # Timer/Counter Interrupt Mask R
+ 'TIMSK_TICIE1': '$20', # Timer/Counter1 Input Capture I
+ 'TIMSK_OCIE1A': '$10', # Timer/Counter1 Output CompareA
+ 'TIMSK_OCIE1B': '$8', # Timer/Counter1 Output CompareB
+ 'TIMSK_TOIE1': '$4', # Timer/Counter1 Overflow Interr
+ 'TIFR' : '$58', # Timer/Counter Interrupt Flag r
+ 'TIFR_ICF1': '$20', # Input Capture Flag 1
+ 'TIFR_OCF1A': '$10', # Output Compare Flag 1A
+ 'TIFR_OCF1B': '$8', # Output Compare Flag 1B
+ 'TIFR_TOV1': '$4', # Timer/Counter1 Overflow Flag
+ 'TCCR1A' : '$4f', # Timer/Counter1 Control Registe
+ 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
+ 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
+ 'TCCR1A_FOC1A': '$8', # Force Output Compare 1A
+ 'TCCR1A_FOC1B': '$4', # Force Output Compare 1B
+ 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
+ 'TCCR1B' : '$4e', # Timer/Counter1 Control Registe
+ 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
+ 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
+ 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
+ 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
+ 'TCNT1' : '$4c', # Timer/Counter1 Bytes
+ 'OCR1A' : '$4a', # Timer/Counter1 Output Compare
+ 'OCR1B' : '$48', # Timer/Counter1 Output Compare
+ 'ICR1' : '$46', # Timer/Counter1 Input Capture R
+
+# Module SPI
+ 'SPDR' : '$2f', # SPI Data Register
+ 'SPSR' : '$2e', # SPI Status Register
+ 'SPSR_SPIF': '$80', # SPI Interrupt Flag
+ 'SPSR_WCOL': '$40', # Write Collision Flag
+ 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
+ 'SPCR' : '$2d', # SPI Control Register
+ 'SPCR_SPIE': '$80', # SPI Interrupt Enable
+ 'SPCR_SPE': '$40', # SPI Enable
+ 'SPCR_DORD': '$20', # Data Order
+ 'SPCR_MSTR': '$10', # Master/Slave Select
+ 'SPCR_CPOL': '$8', # Clock polarity
+ 'SPCR_CPHA': '$4', # Clock Phase
+ 'SPCR_SPR': '$3', # SPI Clock Rate Selects
+
+# Module USART
+ 'UDR' : '$2c', # USART I/O Data Register
+ 'UCSRA' : '$2b', # USART Control and Status Regis
+ 'UCSRA_RXC': '$80', # USART Receive Complete
+ 'UCSRA_TXC': '$40', # USART Transmitt Complete
+ 'UCSRA_UDRE': '$20', # USART Data Register Empty
+ 'UCSRA_FE': '$10', # Framing Error
+ 'UCSRA_DOR': '$8', # Data overRun
+ 'UCSRA_UPE': '$4', # Parity Error
+ 'UCSRA_U2X': '$2', # Double the USART transmission
+ 'UCSRA_MPCM': '$1', # Multi-processor Communication
+ 'UCSRB' : '$2a', # USART Control and Status Regis
+ 'UCSRB_RXCIE': '$80', # RX Complete Interrupt Enable
+ 'UCSRB_TXCIE': '$40', # TX Complete Interrupt Enable
+ 'UCSRB_UDRIE': '$20', # USART Data register Empty Inte
+ 'UCSRB_RXEN': '$10', # Receiver Enable
+ 'UCSRB_TXEN': '$8', # Transmitter Enable
+ 'UCSRB_UCSZ2': '$4', # Character Size
+ 'UCSRB_RXB8': '$2', # Receive Data Bit 8
+ 'UCSRB_TXB8': '$1', # Transmit Data Bit 8
+ 'UCSRC' : '$40', # USART Control and Status Regis
+ 'UCSRC_URSEL': '$80', # Register Select
+ 'UCSRC_UMSEL': '$40', # USART Mode Select
+ 'UCSRC_UPM': '$30', # Parity Mode Bits
+ 'UCSRC_USBS': '$8', # Stop Bit Select
+ 'UCSRC_UCSZ': '$6', # Character Size
+ 'UCSRC_UCPOL': '$1', # Clock Polarity
+ 'UBRRH' : '$40', # USART Baud Rate Register Hight
+ 'UBRRL' : '$29', # USART Baud Rate Register Low B
+
+# Module ANALOG_COMPARATOR
+ 'SFIOR' : '$50', # Special Function IO Register
+ 'SFIOR_ACME': '$8', # Analog Comparator Multiplexer
+ 'ACSR' : '$28', # Analog Comparator Control And
+ 'ACSR_ACD': '$80', # Analog Comparator Disable
+ 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
+ 'ACSR_ACO': '$20', # Analog Compare Output
+ 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
+ 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
+ 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
+ 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
+
+# Module AD_CONVERTER
+ 'ADMUX' : '$27', # The ADC multiplexer Selection
+ 'ADMUX_REFS': '$c0', # Reference Selection Bits
+ 'ADMUX_ADLAR': '$20', # Left Adjust Result
+ 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
+ 'ADCSRA' : '$26', # The ADC Control and Status reg
+ 'ADCSRA_ADEN': '$80', # ADC Enable
+ 'ADCSRA_ADSC': '$40', # ADC Start Conversion
+ 'ADCSRA_ADATE': '$20', # When this bit is written to on
+ 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
+ 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
+ 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
+ 'ADC' : '$24', # ADC Data Register Bytes
+ 'SFIOR' : '$50', # Special Function IO Register
+ 'SFIOR_ADTS': '$e0', # ADC Auto Trigger Sources
+
+# Module PORTA
+ 'PORTA' : '$3b', # Port A Data Register
+ 'DDRA' : '$3a', # Port A Data Direction Register
+ 'PINA' : '$39', # Port A Input Pins
+
+# Module PORTB
+ 'PORTB' : '$38', # Port B Data Register
+ 'DDRB' : '$37', # Port B Data Direction Register
+ 'PINB' : '$36', # Port B Input Pins
+
+# Module PORTC
+ 'PORTC' : '$35', # Port C Data Register
+ 'DDRC' : '$34', # Port C Data Direction Register
+ 'PINC' : '$33', # Port C Input Pins
+
+# Module PORTD
+ 'PORTD' : '$32', # Port D Data Register
+ 'DDRD' : '$31', # Port D Data Direction Register
+ 'PIND' : '$30', # Port D Input Pins
+
+# Module CPU
+ 'SREG' : '$5f', # Status Register
+ 'SREG_I': '$80', # Global Interrupt Enable
+ 'SREG_T': '$40', # Bit Copy Storage
+ 'SREG_H': '$20', # Half Carry Flag
+ 'SREG_S': '$10', # Sign Bit
+ 'SREG_V': '$8', # Two's Complement Overflow Flag
+ 'SREG_N': '$4', # Negative Flag
+ 'SREG_Z': '$2', # Zero Flag
+ 'SREG_C': '$1', # Carry Flag
+ 'SP' : '$5d', # Stack Pointer
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_SE': '$80', # Sleep Enable
+ 'MCUCR_SM': '$70', # Sleep Mode Select
+ 'MCUCR_ISC1': '$c', # Interrupt Sense Control 1 Bits
+ 'MCUCR_ISC0': '$3', # Interrupt Sense Control 0 Bits
+ 'MCUCSR' : '$54', # MCU Control And Status Registe
+ 'MCUCSR_JTD': '$80', # JTAG Interface Disable
+ 'MCUCSR_JTRF': '$10', # JTAG Reset Flag
+ 'MCUCSR_WDRF': '$8', # Watchdog Reset Flag
+ 'MCUCSR_BORF': '$4', # Brown-out Reset Flag
+ 'MCUCSR_EXTRF': '$2', # External Reset Flag
+ 'MCUCSR_PORF': '$1', # Power-on reset flag
+ 'OSCCAL' : '$51', # Oscillator Calibration Value
+ 'SFIOR' : '$50', # Special Function IO Register
+
+# Module BOOT_LOAD
+ 'SPMCR' : '$57', # Store Program Memory Control R
+ 'SPMCR_SPMIE': '$80', # SPM Interrupt Enable
+ 'SPMCR_RWWSB': '$40', # Read While Write Section Busy
+ 'SPMCR_RWWSRE': '$10', # Read While Write secion read e
+ 'SPMCR_BLBSET': '$8', # Boot Lock Bit Set
+ 'SPMCR_PGWRT': '$4', # Page Write
+ 'SPMCR_PGERS': '$2', # Page Erase
+ 'SPMCR_SPMEN': '$1', # Store Program Memory Enable
+
+# Module TWI
+ 'TWBR' : '$20', # TWI Bit Rate register
+ 'TWCR' : '$56', # TWI Control Register
+ 'TWCR_TWINT': '$80', # TWI Interrupt Flag
+ 'TWCR_TWEA': '$40', # TWI Enable Acknowledge Bit
+ 'TWCR_TWSTA': '$20', # TWI Start Condition Bit
+ 'TWCR_TWSTO': '$10', # TWI Stop Condition Bit
+ 'TWCR_TWWC': '$8', # TWI Write Collition Flag
+ 'TWCR_TWEN': '$4', # TWI Enable Bit
+ 'TWCR_TWIE': '$1', # TWI Interrupt Enable
+ 'TWSR' : '$21', # TWI Status Register
+ 'TWSR_TWS': '$f8', # TWI Status
+ 'TWSR_TWPS': '$3', # TWI Prescaler bits
+ 'TWDR' : '$23', # TWI Data register
+ 'TWAR' : '$22', # TWI (Slave) Address register
+
+ '__amforth_dummy':'0'
+}
diff --git a/amforth-6.5/avr8/devices/atmega32a/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega32a/words/no-jtag.asm
new file mode 100644
index 0000000..352a4bb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega32a/words/no-jtag.asm
@@ -0,0 +1,14 @@
+; ( -- )
+; ( -- )
+; MCU
+; disable jtag at runtime
+VE_NOJTAG:
+ .dw $FF05
+ .db "-jtag",0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOJTAG
+XT_NOJTAG:
+ .dw PFA_NOJTAG
+PFA_NOJTAG:
+
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega32a/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega32a/words/no-wdt.asm
new file mode 100644
index 0000000..4a12261
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega32a/words/no-wdt.asm
@@ -0,0 +1,22 @@
+; ( -- )
+; MCU
+; disable watch dog timer at runtime
+VE_NOWDT:
+ .dw $ff04
+ .db "-wdt"
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOWDT
+XT_NOWDT:
+ .dw PFA_NOWDT
+PFA_NOWDT:
+
+; Reset WDT
+ wdr
+; Write logical one to WDTOE and WDE
+ in_ temp1, WDTCR
+ ori temp1, (1<<WDTOE)|(1<<WDE)
+ out WDTCR, temp1
+; Turn off WDT
+ ldi temp1, (0<<WDE)
+ out_ WDTCR, temp1
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega32a/words/sleep.asm b/amforth-6.5/avr8/devices/atmega32a/words/sleep.asm
new file mode 100644
index 0000000..778fa32
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega32a/words/sleep.asm
@@ -0,0 +1,24 @@
+; ( mode -- )
+; MCU
+; put the controller into the specified sleep mode
+VE_SLEEP:
+ .dw $ff05
+ .db "sleep", 0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_SLEEP
+XT_SLEEP:
+ .dw PFA_SLEEP
+PFA_SLEEP:
+ andi tosl, 7 ; leave only legal mode bits
+ swap tosl ; move to correct location (bits 6-4, atmega32)
+ ori tosl, $80 ; set the SE bit (atmega32: bit 7, not bit 0)
+ out_ MCUCR, tosl ; set the sleep config (atmega32: MCUCR not SMCR)
+ sleep ; nighty-night
+;; the 4 lower bits of MCUCR should not be touched
+ in_ tosl, MCUCR
+ andi tosl, $0F
+ out_ MCUCR, tosl
+ ;clr tosl ; need to clean up the SMCR reg before we leave
+ ;out SMCR, tosl ; 0 protects against accidental sleeps
+ loadtos ; pop argument from stack
+ jmp DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega32c1/atmega32c1.frt b/amforth-6.5/avr8/devices/atmega32c1/atmega32c1.frt
new file mode 100644
index 0000000..118eaba
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega32c1/atmega32c1.frt
@@ -0,0 +1,454 @@
+\ Partname: ATmega32C1
+\ generated automatically
+
+\ PORTB
+&37 constant PORTB \ Port B Data Register
+&36 constant DDRB \ Port B Data Direction Register
+&35 constant PINB \ Port B Input Pins
+\ PORTC
+&40 constant PORTC \ Port C Data Register
+&39 constant DDRC \ Port C Data Direction Register
+&38 constant PINC \ Port C Input Pins
+\ PORTD
+&43 constant PORTD \ Port D Data Register
+&42 constant DDRD \ Port D Data Direction Register
+&41 constant PIND \ Port D Input Pins
+\ CAN
+&216 constant CANGCON \ CAN General Control Register
+ $80 constant CANGCON_ABRQ \ Abort Request
+ $40 constant CANGCON_OVRQ \ Overload Frame Request
+ $20 constant CANGCON_TTC \ Time Trigger Communication
+ $10 constant CANGCON_SYNTTC \ Synchronization of TTC
+ $08 constant CANGCON_LISTEN \ Listening Mode
+ $04 constant CANGCON_TEST \ Test Mode
+ $02 constant CANGCON_ENASTB \ Enable / Standby
+ $01 constant CANGCON_SWRES \ Software Reset Request
+&217 constant CANGSTA \ CAN General Status Register
+ $40 constant CANGSTA_OVFG \ Overload Frame Flag
+ $10 constant CANGSTA_TXBSY \ Transmitter Busy
+ $08 constant CANGSTA_RXBSY \ Receiver Busy
+ $04 constant CANGSTA_ENFG \ Enable Flag
+ $02 constant CANGSTA_BOFF \ Bus Off Mode
+ $01 constant CANGSTA_ERRP \ Error Passive Mode
+&218 constant CANGIT \ CAN General Interrupt Register Flags
+ $80 constant CANGIT_CANIT \ General Interrupt Flag
+ $40 constant CANGIT_BOFFIT \ Bus Off Interrupt Flag
+ $20 constant CANGIT_OVRTIM \ Overrun CAN Timer Flag
+ $10 constant CANGIT_BXOK \ Burst Receive Interrupt Flag
+ $08 constant CANGIT_SERG \ Stuff Error General Flag
+ $04 constant CANGIT_CERG \ CRC Error General Flag
+ $02 constant CANGIT_FERG \ Form Error General Flag
+ $01 constant CANGIT_AERG \ Ackknowledgement Error General Flag
+&219 constant CANGIE \ CAN General Interrupt Enable Register
+ $80 constant CANGIE_ENIT \ Enable all Interrupts
+ $40 constant CANGIE_ENBOFF \ Enable Bus Off Interrupt
+ $20 constant CANGIE_ENRX \ Enable Receive Interrupt
+ $10 constant CANGIE_ENTX \ Enable Transmitt Interrupt
+ $08 constant CANGIE_ENERR \ Enable MOb Error Interrupt
+ $04 constant CANGIE_ENBX \ Enable Burst Receive Interrupt
+ $02 constant CANGIE_ENERG \ Enable General Error Interrupt
+ $01 constant CANGIE_ENOVRT \ Enable CAN Timer Overrun Interrupt
+&220 constant CANEN2 \ Enable MOb Register 2
+ $3F constant CANEN2_ENMOB \ Enable MObs
+&221 constant CANEN1 \ Enable MOb Register 1(empty)
+&222 constant CANIE2 \ Enable Interrupt MOb Register 2
+ $3F constant CANIE2_IEMOB \ Interrupt Enable MObs
+&223 constant CANIE1 \ Enable Interrupt MOb Register 1 (empty)
+&224 constant CANSIT2 \ CAN Status Interrupt MOb Register 2
+ $3F constant CANSIT2_SIT \ Status of Interrupt MObs
+&225 constant CANSIT1 \ CAN Status Interrupt MOb Register 1 (empty)
+&226 constant CANBT1 \ CAN Bit Timing Register 1
+ $7E constant CANBT1_BRP \ Baud Rate Prescaler bits
+&227 constant CANBT2 \ CAN Bit Timing Register 2
+ $60 constant CANBT2_SJW \ Re-Sync Jump Width bits
+ $0E constant CANBT2_PRS \ Propagation Time Segment bits
+&228 constant CANBT3 \ CAN Bit Timing Register 3
+ $70 constant CANBT3_PHS2 \ Phase Segment 2 bits
+ $0E constant CANBT3_PHS1 \ Phase Segment 1 bits
+ $01 constant CANBT3_SMP \ Sample Type
+&229 constant CANTCON \ Timer Control Register
+&230 constant CANTIML \ Timer Register Low
+&231 constant CANTIMH \ Timer Register High
+&232 constant CANTTCL \ TTC Timer Register Low
+&233 constant CANTTCH \ TTC Timer Register High
+&234 constant CANTEC \ Transmit Error Counter Register
+&235 constant CANREC \ Receive Error Counter Register
+&236 constant CANHPMOB \ Highest Priority MOb Register
+ $F0 constant CANHPMOB_HPMOB \ Highest Priority MOb Number bits
+ $0F constant CANHPMOB_CGP \ CAN General Purpose bits
+&237 constant CANPAGE \ Page MOb Register
+ $F0 constant CANPAGE_MOBNB \ MOb Number bits
+ $08 constant CANPAGE_AINC \ MOb Data Buffer Auto Increment (Active Low)
+ $07 constant CANPAGE_INDX \ Data Buffer Index bits
+&238 constant CANSTMOB \ MOb Status Register
+ $80 constant CANSTMOB_DLCW \ Data Length Code Warning on MOb
+ $40 constant CANSTMOB_TXOK \ Transmit OK on MOb
+ $20 constant CANSTMOB_RXOK \ Receive OK on MOb
+ $10 constant CANSTMOB_BERR \ Bit Error on MOb
+ $08 constant CANSTMOB_SERR \ Stuff Error on MOb
+ $04 constant CANSTMOB_CERR \ CRC Error on MOb
+ $02 constant CANSTMOB_FERR \ Form Error on MOb
+ $01 constant CANSTMOB_AERR \ Ackknowledgement Error on MOb
+&239 constant CANCDMOB \ MOb Control and DLC Register
+ $C0 constant CANCDMOB_CONMOB \ MOb Config bits
+ $20 constant CANCDMOB_RPLV \ Reply Valid
+ $10 constant CANCDMOB_IDE \ Identifier Extension
+ $0F constant CANCDMOB_DLC \ Data Length Code bits
+&240 constant CANIDT4 \ Identifier Tag Register 4
+ $F8 constant CANIDT4_IDT \
+ $04 constant CANIDT4_RTRTAG \
+ $02 constant CANIDT4_RB1TAG \
+ $01 constant CANIDT4_RB0TAG \
+&241 constant CANIDT3 \ Identifier Tag Register 3
+&242 constant CANIDT2 \ Identifier Tag Register 2
+&243 constant CANIDT1 \ Identifier Tag Register 1
+&244 constant CANIDM4 \ Identifier Mask Register 4
+&245 constant CANIDM3 \ Identifier Mask Register 3
+&246 constant CANIDM2 \ Identifier Mask Register 2
+&247 constant CANIDM1 \ Identifier Mask Register 1
+&248 constant CANSTML \ Time Stamp Register Low
+&249 constant CANSTMH \ Time Stamp Register High
+&250 constant CANMSG \ Message Data Register
+\ ANALOG_COMPARATOR
+&148 constant AC0CON \ Analog Comparator 0 Control Register
+ $80 constant AC0CON_AC0EN \ Analog Comparator 0 Enable Bit
+ $40 constant AC0CON_AC0IE \ Analog Comparator 0 Interrupt Enable Bit
+ $30 constant AC0CON_AC0IS \ Analog Comparator 0 Interrupt Select Bits
+ $08 constant AC0CON_ACCKSEL \ Analog Comparator Clock Select
+ $07 constant AC0CON_AC0M \ Analog Comparator 0 Multiplexer Register
+&149 constant AC1CON \ Analog Comparator 1 Control Register
+ $80 constant AC1CON_AC1EN \ Analog Comparator 1 Enable Bit
+ $40 constant AC1CON_AC1IE \ Analog Comparator 1 Interrupt Enable Bit
+ $30 constant AC1CON_AC1IS \ Analog Comparator 1 Interrupt Select Bit
+ $08 constant AC1CON_AC1ICE \ Analog Comparator 1 Interrupt Capture Enable Bit
+ $07 constant AC1CON_AC1M \ Analog Comparator 1 Multiplexer Register
+&150 constant AC2CON \ Analog Comparator 2 Control Register
+ $80 constant AC2CON_AC2EN \ Analog Comparator 2 Enable Bit
+ $40 constant AC2CON_AC2IE \ Analog Comparator 2 Interrupt Enable Bit
+ $30 constant AC2CON_AC2IS \ Analog Comparator 2 Interrupt Select Bit
+ $07 constant AC2CON_AC2M \ Analog Comparator 2 Multiplexer Register
+&151 constant AC3CON \ Analog Comparator 3 Control Register
+ $80 constant AC3CON_AC3EN \ Analog Comparator 3 Enable Bit
+ $40 constant AC3CON_AC3IE \ Analog Comparator 3 Interrupt Enable Bit
+ $30 constant AC3CON_AC3IS \ Analog Comparator 3 Interrupt Select Bit
+ $07 constant AC3CON_AC3M \ Analog Comparator 3 Multiplexer Register
+&80 constant ACSR \ Analog Comparator Status Register
+ $80 constant ACSR_AC3IF \ Analog Comparator 3 Interrupt Flag Bit
+ $40 constant ACSR_AC2IF \ Analog Comparator 2 Interrupt Flag Bit
+ $20 constant ACSR_AC1IF \ Analog Comparator 1 Interrupt Flag Bit
+ $10 constant ACSR_AC0IF \ Analog Comparator 0 Interrupt Flag Bit
+ $08 constant ACSR_AC3O \ Analog Comparator 3 Output Bit
+ $04 constant ACSR_AC2O \ Analog Comparator 2 Output Bit
+ $02 constant ACSR_AC1O \ Analog Comparator 1 Output Bit
+ $01 constant ACSR_AC0O \ Analog Comparator 0 Output Bit
+\ DA_CONVERTER
+&146 constant DACH \ DAC Data Register High Byte
+ $FF constant DACH_DACH \ DAC Data Register High Byte Bits
+&145 constant DACL \ DAC Data Register Low Byte
+ $FF constant DACL_DACL \ DAC Data Register Low Byte Bits
+&144 constant DACON \ DAC Control Register
+ $80 constant DACON_DAATE \ DAC Auto Trigger Enable Bit
+ $70 constant DACON_DATS \ DAC Trigger Selection Bits
+ $04 constant DACON_DALA \ DAC Left Adjust
+ $01 constant DACON_DAEN \ DAC Enable Bit
+\ CPU
+&87 constant SPMCSR \ Store Program Memory Control Register
+ $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
+ $20 constant SPMCSR_SIGRD \ Signature Row Read
+ $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
+ $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
+ $04 constant SPMCSR_PGWRT \ Page Write
+ $02 constant SPMCSR_PGERS \ Page Erase
+ $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
+&95 constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ $08 constant SREG_V \ Two's Complement Overflow Flag
+ $04 constant SREG_N \ Negative Flag
+ $02 constant SREG_Z \ Zero Flag
+ $01 constant SREG_C \ Carry Flag
+&93 constant SP \ Stack Pointer
+&85 constant MCUCR \ MCU Control Register
+ $80 constant MCUCR_SPIPS \ SPI Pin Select
+ $10 constant MCUCR_PUD \ Pull-up disable
+ $02 constant MCUCR_IVSEL \ Interrupt Vector Select
+ $01 constant MCUCR_IVCE \ Interrupt Vector Change Enable
+&84 constant MCUSR \ MCU Status Register
+ $08 constant MCUSR_WDRF \ Watchdog Reset Flag
+ $04 constant MCUSR_BORF \ Brown-out Reset Flag
+ $02 constant MCUSR_EXTRF \ External Reset Flag
+ $01 constant MCUSR_PORF \ Power-on reset flag
+&102 constant OSCCAL \ Oscillator Calibration Value
+&97 constant CLKPR \
+ $80 constant CLKPR_CLKPCE \
+ $0F constant CLKPR_CLKPS \
+&83 constant SMCR \ Sleep Mode Control Register
+ $0E constant SMCR_SM \ Sleep Mode Select bits
+ $01 constant SMCR_SE \ Sleep Enable
+&58 constant GPIOR2 \ General Purpose IO Register 2
+ $FF constant GPIOR2_GPIOR \ General Purpose IO Register 2 bis
+&57 constant GPIOR1 \ General Purpose IO Register 1
+ $FF constant GPIOR1_GPIOR \ General Purpose IO Register 1 bis
+&62 constant GPIOR0 \ General Purpose IO Register 0
+ $80 constant GPIOR0_GPIOR07 \ General Purpose IO Register 0 bit 7
+ $40 constant GPIOR0_GPIOR06 \ General Purpose IO Register 0 bit 6
+ $20 constant GPIOR0_GPIOR05 \ General Purpose IO Register 0 bit 5
+ $10 constant GPIOR0_GPIOR04 \ General Purpose IO Register 0 bit 4
+ $08 constant GPIOR0_GPIOR03 \ General Purpose IO Register 0 bit 3
+ $04 constant GPIOR0_GPIOR02 \ General Purpose IO Register 0 bit 2
+ $02 constant GPIOR0_GPIOR01 \ General Purpose IO Register 0 bit 1
+ $01 constant GPIOR0_GPIOR00 \ General Purpose IO Register 0 bit 0
+&73 constant PLLCSR \ PLL Control And Status Register
+ $04 constant PLLCSR_PLLF \ PLL Factor
+ $02 constant PLLCSR_PLLE \ PLL Enable
+ $01 constant PLLCSR_PLOCK \ PLL Lock Detector
+&100 constant PRR \ Power Reduction Register
+ $40 constant PRR_PRCAN \ Power Reduction CAN
+ $20 constant PRR_PRPSC \ Power Reduction PSC
+ $10 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
+ $08 constant PRR_PRTIM0 \ Power Reduction Timer/Counter0
+ $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
+ $02 constant PRR_PRLIN \ Power Reduction LIN UART
+ $01 constant PRR_PRADC \ Power Reduction ADC
+\ PORTE
+&46 constant PORTE \ Port E Data Register
+&45 constant DDRE \ Port E Data Direction Register
+&44 constant PINE \ Port E Input Pins
+\ TIMER_COUNTER_0
+&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
+ $04 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare Match B Interrupt Enable
+ $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match A Interrupt Enable
+ $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
+&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
+ $04 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare Flag 0B
+ $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0A
+ $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
+&68 constant TCCR0A \ Timer/Counter Control Register A
+ $C0 constant TCCR0A_COM0A \ Compare Output Mode, Phase Correct PWM Mode
+ $30 constant TCCR0A_COM0B \ Compare Output Mode, Fast PWm
+ $03 constant TCCR0A_WGM0 \ Waveform Generation Mode
+&69 constant TCCR0B \ Timer/Counter Control Register B
+ $80 constant TCCR0B_FOC0A \ Force Output Compare A
+ $40 constant TCCR0B_FOC0B \ Force Output Compare B
+ $08 constant TCCR0B_WGM02 \
+ $07 constant TCCR0B_CS0 \ Clock Select
+&70 constant TCNT0 \ Timer/Counter0
+&71 constant OCR0A \ Timer/Counter0 Output Compare Register
+&72 constant OCR0B \ Timer/Counter0 Output Compare Register
+&67 constant GTCCR \ General Timer/Counter Control Register
+ $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
+ $40 constant GTCCR_ICPSEL1 \ Timer1 Input Capture Selection Bit
+ $01 constant GTCCR_PSR10 \ Prescaler Reset Timer/Counter1 and Timer/Counter0
+\ TIMER_COUNTER_1
+&111 constant TIMSK1 \ Timer/Counter Interrupt Mask Register
+ $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
+ $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output CompareB Match Interrupt Enable
+ $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output CompareA Match Interrupt Enable
+ $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
+&54 constant TIFR1 \ Timer/Counter Interrupt Flag register
+ $20 constant TIFR1_ICF1 \ Input Capture Flag 1
+ $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
+ $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
+ $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
+&128 constant TCCR1A \ Timer/Counter1 Control Register A
+ $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
+ $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
+ $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
+&129 constant TCCR1B \ Timer/Counter1 Control Register B
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
+ $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
+&130 constant TCCR1C \ Timer/Counter1 Control Register C
+ $80 constant TCCR1C_FOC1A \
+ $40 constant TCCR1C_FOC1B \
+&132 constant TCNT1 \ Timer/Counter1 Bytes
+&136 constant OCR1A \ Timer/Counter1 Output Compare Register Bytes
+&138 constant OCR1B \ Timer/Counter1 Output Compare Register Bytes
+&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
+\ AD_CONVERTER
+&124 constant ADMUX \ The ADC multiplexer Selection Register
+ $C0 constant ADMUX_REFS \ Reference Selection Bits
+ $20 constant ADMUX_ADLAR \ Left Adjust Result
+ $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
+&122 constant ADCSRA \ The ADC Control and Status register
+ $80 constant ADCSRA_ADEN \ ADC Enable
+ $40 constant ADCSRA_ADSC \ ADC Start Conversion
+ $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
+ $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
+ $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
+ $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
+&120 constant ADC \ ADC Data Register Bytes
+&123 constant ADCSRB \ ADC Control and Status Register B
+ $80 constant ADCSRB_ADHSM \ ADC High Speed Mode
+ $40 constant ADCSRB_ISRCEN \ Current Source Enable
+ $20 constant ADCSRB_AREFEN \ Analog Reference pin Enable
+ $0F constant ADCSRB_ADTS \ ADC Auto Trigger Sources
+&126 constant DIDR0 \ Digital Input Disable Register 0
+ $80 constant DIDR0_ADC7D \ ADC7 Digital input Disable
+ $40 constant DIDR0_ADC6D \ ADC6 Digital input Disable
+ $20 constant DIDR0_ADC5D \ ADC5 Digital input Disable
+ $10 constant DIDR0_ADC4D \ ADC4 Digital input Disable
+ $08 constant DIDR0_ADC3D \ ADC3 Digital input Disable
+ $04 constant DIDR0_ADC2D \ ADC2 Digital input Disable
+ $02 constant DIDR0_ADC1D \ ADC1 Digital input Disable
+ $01 constant DIDR0_ADC0D \ ADC0 Digital input Disable
+&127 constant DIDR1 \ Digital Input Disable Register 0
+ $40 constant DIDR1_AMP2PD \ AMP2P Pin Digital input Disable
+ $20 constant DIDR1_ACMP0D \ ACMP0 Pin Digital input Disable
+ $10 constant DIDR1_AMP0PD \ AMP0P Pin Digital input Disable
+ $08 constant DIDR1_AMP0ND \ AMP0N Pin Digital input Disable
+ $04 constant DIDR1_ADC10D \ ADC10 Pin Digital input Disable
+ $02 constant DIDR1_ADC9D \ ADC9 Pin Digital input Disable
+ $01 constant DIDR1_ADC8D \ ADC8 Pin Digital input Disable
+&117 constant AMP0CSR \
+ $80 constant AMP0CSR_AMP0EN \
+ $40 constant AMP0CSR_AMP0IS \
+ $30 constant AMP0CSR_AMP0G \
+ $08 constant AMP0CSR_AMPCMP0 \ Amplifier 0 - Comparator 0 Connection
+ $07 constant AMP0CSR_AMP0TS \
+&118 constant AMP1CSR \
+ $80 constant AMP1CSR_AMP1EN \
+ $40 constant AMP1CSR_AMP1IS \
+ $30 constant AMP1CSR_AMP1G \
+ $08 constant AMP1CSR_AMPCMP1 \ Amplifier 1 - Comparator 1 Connection
+ $07 constant AMP1CSR_AMP1TS \
+&119 constant AMP2CSR \
+ $80 constant AMP2CSR_AMP2EN \
+ $40 constant AMP2CSR_AMP2IS \
+ $30 constant AMP2CSR_AMP2G \
+ $08 constant AMP2CSR_AMPCMP2 \ Amplifier 2 - Comparator 2 Connection
+ $07 constant AMP2CSR_AMP2TS \
+\ LINUART
+&200 constant LINCR \ LIN Control Register
+ $80 constant LINCR_LSWRES \ Software Reset
+ $40 constant LINCR_LIN13 \ LIN Standard
+ $30 constant LINCR_LCONF \ LIN Configuration bits
+ $08 constant LINCR_LENA \ LIN or UART Enable
+ $07 constant LINCR_LCMD \ LIN Command and Mode bits
+&201 constant LINSIR \ LIN Status and Interrupt Register
+ $E0 constant LINSIR_LIDST \ Identifier Status bits
+ $10 constant LINSIR_LBUSY \ Busy Signal
+ $08 constant LINSIR_LERR \ Error Interrupt
+ $04 constant LINSIR_LIDOK \ Identifier Interrupt
+ $02 constant LINSIR_LTXOK \ Transmit Performed Interrupt
+ $01 constant LINSIR_LRXOK \ Receive Performed Interrupt
+&202 constant LINENIR \ LIN Enable Interrupt Register
+ $08 constant LINENIR_LENERR \ Enable Error Interrupt
+ $04 constant LINENIR_LENIDOK \ Enable Identifier Interrupt
+ $02 constant LINENIR_LENTXOK \ Enable Transmit Performed Interrupt
+ $01 constant LINENIR_LENRXOK \ Enable Receive Performed Interrupt
+&203 constant LINERR \ LIN Error Register
+ $80 constant LINERR_LABORT \ Abort Flag
+ $40 constant LINERR_LTOERR \ Frame Time Out Error Flag
+ $20 constant LINERR_LOVERR \ Overrun Error Flag
+ $10 constant LINERR_LFERR \ Framing Error Flag
+ $08 constant LINERR_LSERR \ Synchronization Error Flag
+ $04 constant LINERR_LPERR \ Parity Error Flag
+ $02 constant LINERR_LCERR \ Checksum Error Flag
+ $01 constant LINERR_LBERR \ Bit Error Flag
+&204 constant LINBTR \ LIN Bit Timing Register
+ $80 constant LINBTR_LDISR \ Disable Bit Timing Resynchronization
+ $3F constant LINBTR_LBT \ LIN Bit Timing bits
+&205 constant LINBRRL \ LIN Baud Rate Low Register
+ $FF constant LINBRRL_LDIV \
+&206 constant LINBRRH \ LIN Baud Rate High Register
+ $0F constant LINBRRH_LDIV \
+&207 constant LINDLR \ LIN Data Length Register
+ $F0 constant LINDLR_LTXDL \ LIN Transmit Data Length bits
+ $0F constant LINDLR_LRXDL \ LIN Receive Data Length bits
+&208 constant LINIDR \ LIN Identifier Register
+ $C0 constant LINIDR_LP \ Parity bits
+ $3F constant LINIDR_LID \ Identifier bit 5 or Data Length bits
+&209 constant LINSEL \ LIN Data Buffer Selection Register
+ $08 constant LINSEL_LAINC \ Auto Increment of Data Buffer Index (Active Low)
+ $07 constant LINSEL_LINDX \ FIFO LIN Data Buffer Index bits
+&210 constant LINDAT \ LIN Data Register
+ $FF constant LINDAT_LDATA \
+\ SPI
+&76 constant SPCR \ SPI Control Register
+ $80 constant SPCR_SPIE \ SPI Interrupt Enable
+ $40 constant SPCR_SPE \ SPI Enable
+ $20 constant SPCR_DORD \ Data Order
+ $10 constant SPCR_MSTR \ Master/Slave Select
+ $08 constant SPCR_CPOL \ Clock polarity
+ $04 constant SPCR_CPHA \ Clock Phase
+ $03 constant SPCR_SPR \ SPI Clock Rate Selects
+&77 constant SPSR \ SPI Status Register
+ $80 constant SPSR_SPIF \ SPI Interrupt Flag
+ $40 constant SPSR_WCOL \ Write Collision Flag
+ $01 constant SPSR_SPI2X \ Double SPI Speed Bit
+&78 constant SPDR \ SPI Data Register
+\ WATCHDOG
+&96 constant WDTCSR \ Watchdog Timer Control Register
+ $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Flag
+ $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Enable
+ $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
+ $10 constant WDTCSR_WDCE \ Watchdog Change Enable
+ $08 constant WDTCSR_WDE \ Watch Dog Enable
+\ EXTERNAL_INTERRUPT
+&105 constant EICRA \ External Interrupt Control Register
+ $C0 constant EICRA_ISC3 \ External Interrupt Sense Control Bit
+ $30 constant EICRA_ISC2 \ External Interrupt Sense Control Bit
+ $0C constant EICRA_ISC1 \ External Interrupt Sense Control 1 Bits
+ $03 constant EICRA_ISC0 \ External Interrupt Sense Control 0 Bits
+&61 constant EIMSK \ External Interrupt Mask Register
+ $0F constant EIMSK_INT \ External Interrupt Request 3 Enable
+&60 constant EIFR \ External Interrupt Flag Register
+ $0F constant EIFR_INTF \ External Interrupt Flags
+&104 constant PCICR \ Pin Change Interrupt Control Register
+ $0F constant PCICR_PCIE \ Pin Change Interrupt Enables
+&109 constant PCMSK3 \ Pin Change Mask Register 3
+ $07 constant PCMSK3_PCINT \ Pin Change Enable Masks
+&108 constant PCMSK2 \ Pin Change Mask Register 2
+ $FF constant PCMSK2_PCINT \ Pin Change Enable Masks
+&107 constant PCMSK1 \ Pin Change Mask Register 1
+ $FF constant PCMSK1_PCINT \ Pin Change Enable Masks
+&106 constant PCMSK0 \ Pin Change Mask Register 0
+ $FF constant PCMSK0_PCINT \ Pin Change Enable Masks
+&59 constant PCIFR \ Pin Change Interrupt Flag Register
+ $0F constant PCIFR_PCIF \ Pin Change Interrupt Flags
+\ EEPROM
+&65 constant EEAR \ EEPROM Read/Write Access
+&64 constant EEDR \ EEPROM Data Register
+&63 constant EECR \ EEPROM Control Register
+ $30 constant EECR_EEPM \
+ $08 constant EECR_EERIE \ EEProm Ready Interrupt Enable
+ $04 constant EECR_EEMWE \ EEPROM Master Write Enable
+ $02 constant EECR_EEWE \ EEPROM Write Enable
+ $01 constant EECR_EERE \ EEPROM Read Enable
+
+\ Interrupts
+&2 constant ANACOMP0Addr \ Analog Comparator 0
+&4 constant ANACOMP1Addr \ Analog Comparator 1
+&6 constant ANACOMP2Addr \ Analog Comparator 2
+&8 constant ANACOMP3Addr \ Analog Comparator 3
+&10 constant PSC_FAULTAddr \ PSC Fault
+&12 constant PSC_ECAddr \ PSC End of Cycle
+&14 constant INT0Addr \ External Interrupt Request 0
+&16 constant INT1Addr \ External Interrupt Request 1
+&18 constant INT2Addr \ External Interrupt Request 2
+&20 constant INT3Addr \ External Interrupt Request 3
+&22 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+&24 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
+&26 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
+&28 constant TIMER1_OVFAddr \ Timer1/Counter1 Overflow
+&30 constant TIMER0_COMPAAddr \ Timer/Counter0 Compare Match A
+&32 constant TIMER0_COMPBAddr \ Timer/Counter0 Compare Match B
+&34 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
+&36 constant CAN_INTAddr \ CAN MOB, Burst, General Errors
+&38 constant CAN_TOVFAddr \ CAN Timer Overflow
+&40 constant LIN_TCAddr \ LIN Transfer Complete
+&42 constant LIN_ERRAddr \ LIN Error
+&44 constant PCINT0Addr \ Pin Change Interrupt Request 0
+&46 constant PCINT1Addr \ Pin Change Interrupt Request 1
+&48 constant PCINT2Addr \ Pin Change Interrupt Request 2
+&50 constant PCINT3Addr \ Pin Change Interrupt Request 3
+&52 constant SPI__STCAddr \ SPI Serial Transfer Complete
+&54 constant ADCAddr \ ADC Conversion Complete
+&56 constant WDTAddr \ Watchdog Time-Out Interrupt
+&58 constant EE_READYAddr \ EEPROM Ready
+&60 constant SPM_READYAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/atmega32c1/device.asm b/amforth-6.5/avr8/devices/atmega32c1/device.asm
new file mode 100644
index 0000000..b43163d
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega32c1/device.asm
@@ -0,0 +1,119 @@
+; Partname: ATmega32C1
+; generated automatically, do not edit
+
+.nolist
+ .include "m32C1def.inc"
+.list
+
+.equ ramstart = 256
+.equ CELLSIZE = 2
+.macro readflashcell
+ lsl zl
+ rol zh
+ lpm @0, Z+
+ lpm @1, Z+
+.endmacro
+.macro writeflashcell
+ lsl zl
+ rol zh
+.endmacro
+.set WANT_PORTB = 0
+.set WANT_PORTC = 0
+.set WANT_PORTD = 0
+.set WANT_CAN = 0
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_DA_CONVERTER = 0
+.set WANT_CPU = 0
+.set WANT_PORTE = 0
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_AD_CONVERTER = 0
+.set WANT_LINUART = 0
+.set WANT_SPI = 0
+.set WANT_WATCHDOG = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_EEPROM = 0
+.equ intvecsize = 2 ; please verify; flash size: 32768 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.org 2
+ rcall isr ; Analog Comparator 0
+.org 4
+ rcall isr ; Analog Comparator 1
+.org 6
+ rcall isr ; Analog Comparator 2
+.org 8
+ rcall isr ; Analog Comparator 3
+.org 10
+ rcall isr ; PSC Fault
+.org 12
+ rcall isr ; PSC End of Cycle
+.org 14
+ rcall isr ; External Interrupt Request 0
+.org 16
+ rcall isr ; External Interrupt Request 1
+.org 18
+ rcall isr ; External Interrupt Request 2
+.org 20
+ rcall isr ; External Interrupt Request 3
+.org 22
+ rcall isr ; Timer/Counter1 Capture Event
+.org 24
+ rcall isr ; Timer/Counter1 Compare Match A
+.org 26
+ rcall isr ; Timer/Counter1 Compare Match B
+.org 28
+ rcall isr ; Timer1/Counter1 Overflow
+.org 30
+ rcall isr ; Timer/Counter0 Compare Match A
+.org 32
+ rcall isr ; Timer/Counter0 Compare Match B
+.org 34
+ rcall isr ; Timer/Counter0 Overflow
+.org 36
+ rcall isr ; CAN MOB, Burst, General Errors
+.org 38
+ rcall isr ; CAN Timer Overflow
+.org 40
+ rcall isr ; LIN Transfer Complete
+.org 42
+ rcall isr ; LIN Error
+.org 44
+ rcall isr ; Pin Change Interrupt Request 0
+.org 46
+ rcall isr ; Pin Change Interrupt Request 1
+.org 48
+ rcall isr ; Pin Change Interrupt Request 2
+.org 50
+ rcall isr ; Pin Change Interrupt Request 3
+.org 52
+ rcall isr ; SPI Serial Transfer Complete
+.org 54
+ rcall isr ; ADC Conversion Complete
+.org 56
+ rcall isr ; Watchdog Time-Out Interrupt
+.org 58
+ rcall isr ; EEPROM Ready
+.org 60
+ rcall isr ; Store Program Memory Read
+.equ INTVECTORS = 31
+.nooverlap
+
+; compatability layer (maybe empty)
+.equ EEPE = EEWE
+.equ EEMPE = EEMWE
+
+; controller data area, environment query mcu-info
+mcu_info:
+mcu_ramsize:
+ .dw 2048
+mcu_eepromsize:
+ .dw 1024
+mcu_maxdp:
+ .dw 28672
+mcu_numints:
+ .dw 31
+mcu_name:
+ .dw 10
+ .db "ATmega32C1"
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega32c1/device.inc b/amforth-6.5/avr8/devices/atmega32c1/device.inc
new file mode 100644
index 0000000..c2891e4
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega32c1/device.inc
@@ -0,0 +1,1503 @@
+; Partname: ATmega32C1
+; generated automatically, no not edit
+
+.if WANT_PORTB == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw 37
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw 36
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw 35
+
+.endif
+.if WANT_PORTC == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Register
+VE_PORTC:
+ .dw $ff05
+ .db "PORTC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTC
+XT_PORTC:
+ .dw PFA_DOVARIABLE
+PFA_PORTC:
+ .dw 40
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Direction Register
+VE_DDRC:
+ .dw $ff04
+ .db "DDRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRC
+XT_DDRC:
+ .dw PFA_DOVARIABLE
+PFA_DDRC:
+ .dw 39
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Input Pins
+VE_PINC:
+ .dw $ff04
+ .db "PINC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINC
+XT_PINC:
+ .dw PFA_DOVARIABLE
+PFA_PINC:
+ .dw 38
+
+.endif
+.if WANT_PORTD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw 43
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw 42
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw 41
+
+.endif
+.if WANT_CAN == 1
+; ( -- addr ) System Constant
+; R( -- )
+; CAN General Control Register
+VE_CANGCON:
+ .dw $ff07
+ .db "CANGCON",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANGCON
+XT_CANGCON:
+ .dw PFA_DOVARIABLE
+PFA_CANGCON:
+ .dw 216
+; ( -- addr ) System Constant
+; R( -- )
+; CAN General Status Register
+VE_CANGSTA:
+ .dw $ff07
+ .db "CANGSTA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANGSTA
+XT_CANGSTA:
+ .dw PFA_DOVARIABLE
+PFA_CANGSTA:
+ .dw 217
+; ( -- addr ) System Constant
+; R( -- )
+; CAN General Interrupt Register Flags
+VE_CANGIT:
+ .dw $ff06
+ .db "CANGIT"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANGIT
+XT_CANGIT:
+ .dw PFA_DOVARIABLE
+PFA_CANGIT:
+ .dw 218
+; ( -- addr ) System Constant
+; R( -- )
+; CAN General Interrupt Enable Register
+VE_CANGIE:
+ .dw $ff06
+ .db "CANGIE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANGIE
+XT_CANGIE:
+ .dw PFA_DOVARIABLE
+PFA_CANGIE:
+ .dw 219
+; ( -- addr ) System Constant
+; R( -- )
+; Enable MOb Register 2
+VE_CANEN2:
+ .dw $ff06
+ .db "CANEN2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANEN2
+XT_CANEN2:
+ .dw PFA_DOVARIABLE
+PFA_CANEN2:
+ .dw 220
+; ( -- addr ) System Constant
+; R( -- )
+; Enable MOb Register 1(empty)
+VE_CANEN1:
+ .dw $ff06
+ .db "CANEN1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANEN1
+XT_CANEN1:
+ .dw PFA_DOVARIABLE
+PFA_CANEN1:
+ .dw 221
+; ( -- addr ) System Constant
+; R( -- )
+; Enable Interrupt MOb Register 2
+VE_CANIE2:
+ .dw $ff06
+ .db "CANIE2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANIE2
+XT_CANIE2:
+ .dw PFA_DOVARIABLE
+PFA_CANIE2:
+ .dw 222
+; ( -- addr ) System Constant
+; R( -- )
+; Enable Interrupt MOb Register 1 (empty)
+VE_CANIE1:
+ .dw $ff06
+ .db "CANIE1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANIE1
+XT_CANIE1:
+ .dw PFA_DOVARIABLE
+PFA_CANIE1:
+ .dw 223
+; ( -- addr ) System Constant
+; R( -- )
+; CAN Status Interrupt MOb Register 2
+VE_CANSIT2:
+ .dw $ff07
+ .db "CANSIT2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANSIT2
+XT_CANSIT2:
+ .dw PFA_DOVARIABLE
+PFA_CANSIT2:
+ .dw 224
+; ( -- addr ) System Constant
+; R( -- )
+; CAN Status Interrupt MOb Register 1 (empty)
+VE_CANSIT1:
+ .dw $ff07
+ .db "CANSIT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANSIT1
+XT_CANSIT1:
+ .dw PFA_DOVARIABLE
+PFA_CANSIT1:
+ .dw 225
+; ( -- addr ) System Constant
+; R( -- )
+; CAN Bit Timing Register 1
+VE_CANBT1:
+ .dw $ff06
+ .db "CANBT1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANBT1
+XT_CANBT1:
+ .dw PFA_DOVARIABLE
+PFA_CANBT1:
+ .dw 226
+; ( -- addr ) System Constant
+; R( -- )
+; CAN Bit Timing Register 2
+VE_CANBT2:
+ .dw $ff06
+ .db "CANBT2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANBT2
+XT_CANBT2:
+ .dw PFA_DOVARIABLE
+PFA_CANBT2:
+ .dw 227
+; ( -- addr ) System Constant
+; R( -- )
+; CAN Bit Timing Register 3
+VE_CANBT3:
+ .dw $ff06
+ .db "CANBT3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANBT3
+XT_CANBT3:
+ .dw PFA_DOVARIABLE
+PFA_CANBT3:
+ .dw 228
+; ( -- addr ) System Constant
+; R( -- )
+; Timer Control Register
+VE_CANTCON:
+ .dw $ff07
+ .db "CANTCON",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANTCON
+XT_CANTCON:
+ .dw PFA_DOVARIABLE
+PFA_CANTCON:
+ .dw 229
+; ( -- addr ) System Constant
+; R( -- )
+; Timer Register Low
+VE_CANTIML:
+ .dw $ff07
+ .db "CANTIML",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANTIML
+XT_CANTIML:
+ .dw PFA_DOVARIABLE
+PFA_CANTIML:
+ .dw 230
+; ( -- addr ) System Constant
+; R( -- )
+; Timer Register High
+VE_CANTIMH:
+ .dw $ff07
+ .db "CANTIMH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANTIMH
+XT_CANTIMH:
+ .dw PFA_DOVARIABLE
+PFA_CANTIMH:
+ .dw 231
+; ( -- addr ) System Constant
+; R( -- )
+; TTC Timer Register Low
+VE_CANTTCL:
+ .dw $ff07
+ .db "CANTTCL",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANTTCL
+XT_CANTTCL:
+ .dw PFA_DOVARIABLE
+PFA_CANTTCL:
+ .dw 232
+; ( -- addr ) System Constant
+; R( -- )
+; TTC Timer Register High
+VE_CANTTCH:
+ .dw $ff07
+ .db "CANTTCH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANTTCH
+XT_CANTTCH:
+ .dw PFA_DOVARIABLE
+PFA_CANTTCH:
+ .dw 233
+; ( -- addr ) System Constant
+; R( -- )
+; Transmit Error Counter Register
+VE_CANTEC:
+ .dw $ff06
+ .db "CANTEC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANTEC
+XT_CANTEC:
+ .dw PFA_DOVARIABLE
+PFA_CANTEC:
+ .dw 234
+; ( -- addr ) System Constant
+; R( -- )
+; Receive Error Counter Register
+VE_CANREC:
+ .dw $ff06
+ .db "CANREC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANREC
+XT_CANREC:
+ .dw PFA_DOVARIABLE
+PFA_CANREC:
+ .dw 235
+; ( -- addr ) System Constant
+; R( -- )
+; Highest Priority MOb Register
+VE_CANHPMOB:
+ .dw $ff08
+ .db "CANHPMOB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANHPMOB
+XT_CANHPMOB:
+ .dw PFA_DOVARIABLE
+PFA_CANHPMOB:
+ .dw 236
+; ( -- addr ) System Constant
+; R( -- )
+; Page MOb Register
+VE_CANPAGE:
+ .dw $ff07
+ .db "CANPAGE",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANPAGE
+XT_CANPAGE:
+ .dw PFA_DOVARIABLE
+PFA_CANPAGE:
+ .dw 237
+; ( -- addr ) System Constant
+; R( -- )
+; MOb Status Register
+VE_CANSTMOB:
+ .dw $ff08
+ .db "CANSTMOB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANSTMOB
+XT_CANSTMOB:
+ .dw PFA_DOVARIABLE
+PFA_CANSTMOB:
+ .dw 238
+; ( -- addr ) System Constant
+; R( -- )
+; MOb Control and DLC Register
+VE_CANCDMOB:
+ .dw $ff08
+ .db "CANCDMOB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANCDMOB
+XT_CANCDMOB:
+ .dw PFA_DOVARIABLE
+PFA_CANCDMOB:
+ .dw 239
+; ( -- addr ) System Constant
+; R( -- )
+; Identifier Tag Register 4
+VE_CANIDT4:
+ .dw $ff07
+ .db "CANIDT4",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANIDT4
+XT_CANIDT4:
+ .dw PFA_DOVARIABLE
+PFA_CANIDT4:
+ .dw 240
+; ( -- addr ) System Constant
+; R( -- )
+; Identifier Tag Register 3
+VE_CANIDT3:
+ .dw $ff07
+ .db "CANIDT3",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANIDT3
+XT_CANIDT3:
+ .dw PFA_DOVARIABLE
+PFA_CANIDT3:
+ .dw 241
+; ( -- addr ) System Constant
+; R( -- )
+; Identifier Tag Register 2
+VE_CANIDT2:
+ .dw $ff07
+ .db "CANIDT2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANIDT2
+XT_CANIDT2:
+ .dw PFA_DOVARIABLE
+PFA_CANIDT2:
+ .dw 242
+; ( -- addr ) System Constant
+; R( -- )
+; Identifier Tag Register 1
+VE_CANIDT1:
+ .dw $ff07
+ .db "CANIDT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANIDT1
+XT_CANIDT1:
+ .dw PFA_DOVARIABLE
+PFA_CANIDT1:
+ .dw 243
+; ( -- addr ) System Constant
+; R( -- )
+; Identifier Mask Register 4
+VE_CANIDM4:
+ .dw $ff07
+ .db "CANIDM4",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANIDM4
+XT_CANIDM4:
+ .dw PFA_DOVARIABLE
+PFA_CANIDM4:
+ .dw 244
+; ( -- addr ) System Constant
+; R( -- )
+; Identifier Mask Register 3
+VE_CANIDM3:
+ .dw $ff07
+ .db "CANIDM3",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANIDM3
+XT_CANIDM3:
+ .dw PFA_DOVARIABLE
+PFA_CANIDM3:
+ .dw 245
+; ( -- addr ) System Constant
+; R( -- )
+; Identifier Mask Register 2
+VE_CANIDM2:
+ .dw $ff07
+ .db "CANIDM2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANIDM2
+XT_CANIDM2:
+ .dw PFA_DOVARIABLE
+PFA_CANIDM2:
+ .dw 246
+; ( -- addr ) System Constant
+; R( -- )
+; Identifier Mask Register 1
+VE_CANIDM1:
+ .dw $ff07
+ .db "CANIDM1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANIDM1
+XT_CANIDM1:
+ .dw PFA_DOVARIABLE
+PFA_CANIDM1:
+ .dw 247
+; ( -- addr ) System Constant
+; R( -- )
+; Time Stamp Register Low
+VE_CANSTML:
+ .dw $ff07
+ .db "CANSTML",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANSTML
+XT_CANSTML:
+ .dw PFA_DOVARIABLE
+PFA_CANSTML:
+ .dw 248
+; ( -- addr ) System Constant
+; R( -- )
+; Time Stamp Register High
+VE_CANSTMH:
+ .dw $ff07
+ .db "CANSTMH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANSTMH
+XT_CANSTMH:
+ .dw PFA_DOVARIABLE
+PFA_CANSTMH:
+ .dw 249
+; ( -- addr ) System Constant
+; R( -- )
+; Message Data Register
+VE_CANMSG:
+ .dw $ff06
+ .db "CANMSG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANMSG
+XT_CANMSG:
+ .dw PFA_DOVARIABLE
+PFA_CANMSG:
+ .dw 250
+
+.endif
+.if WANT_ANALOG_COMPARATOR == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator 0 Control Register
+VE_AC0CON:
+ .dw $ff06
+ .db "AC0CON"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_AC0CON
+XT_AC0CON:
+ .dw PFA_DOVARIABLE
+PFA_AC0CON:
+ .dw 148
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator 1 Control Register
+VE_AC1CON:
+ .dw $ff06
+ .db "AC1CON"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_AC1CON
+XT_AC1CON:
+ .dw PFA_DOVARIABLE
+PFA_AC1CON:
+ .dw 149
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator 2 Control Register
+VE_AC2CON:
+ .dw $ff06
+ .db "AC2CON"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_AC2CON
+XT_AC2CON:
+ .dw PFA_DOVARIABLE
+PFA_AC2CON:
+ .dw 150
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator 3 Control Register
+VE_AC3CON:
+ .dw $ff06
+ .db "AC3CON"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_AC3CON
+XT_AC3CON:
+ .dw PFA_DOVARIABLE
+PFA_AC3CON:
+ .dw 151
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw 80
+
+.endif
+.if WANT_DA_CONVERTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; DAC Data Register High Byte
+VE_DACH:
+ .dw $ff04
+ .db "DACH"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DACH
+XT_DACH:
+ .dw PFA_DOVARIABLE
+PFA_DACH:
+ .dw 146
+; ( -- addr ) System Constant
+; R( -- )
+; DAC Data Register Low Byte
+VE_DACL:
+ .dw $ff04
+ .db "DACL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DACL
+XT_DACL:
+ .dw PFA_DOVARIABLE
+PFA_DACL:
+ .dw 145
+; ( -- addr ) System Constant
+; R( -- )
+; DAC Control Register
+VE_DACON:
+ .dw $ff05
+ .db "DACON",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DACON
+XT_DACON:
+ .dw PFA_DOVARIABLE
+PFA_DACON:
+ .dw 144
+
+.endif
+.if WANT_CPU == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control Register
+VE_SPMCSR:
+ .dw $ff06
+ .db "SPMCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCSR
+XT_SPMCSR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCSR:
+ .dw 87
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw 95
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer
+VE_SP:
+ .dw $ff02
+ .db "SP"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SP
+XT_SP:
+ .dw PFA_DOVARIABLE
+PFA_SP:
+ .dw 93
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw 85
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Status Register
+VE_MCUSR:
+ .dw $ff05
+ .db "MCUSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUSR
+XT_MCUSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUSR:
+ .dw 84
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Calibration Value
+VE_OSCCAL:
+ .dw $ff06
+ .db "OSCCAL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSCCAL
+XT_OSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_OSCCAL:
+ .dw 102
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_CLKPR:
+ .dw $ff05
+ .db "CLKPR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKPR
+XT_CLKPR:
+ .dw PFA_DOVARIABLE
+PFA_CLKPR:
+ .dw 97
+; ( -- addr ) System Constant
+; R( -- )
+; Sleep Mode Control Register
+VE_SMCR:
+ .dw $ff04
+ .db "SMCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SMCR
+XT_SMCR:
+ .dw PFA_DOVARIABLE
+PFA_SMCR:
+ .dw 83
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 2
+VE_GPIOR2:
+ .dw $ff06
+ .db "GPIOR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR2
+XT_GPIOR2:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR2:
+ .dw 58
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 1
+VE_GPIOR1:
+ .dw $ff06
+ .db "GPIOR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR1
+XT_GPIOR1:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR1:
+ .dw 57
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 0
+VE_GPIOR0:
+ .dw $ff06
+ .db "GPIOR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR0
+XT_GPIOR0:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR0:
+ .dw 62
+; ( -- addr ) System Constant
+; R( -- )
+; PLL Control And Status Register
+VE_PLLCSR:
+ .dw $ff06
+ .db "PLLCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PLLCSR
+XT_PLLCSR:
+ .dw PFA_DOVARIABLE
+PFA_PLLCSR:
+ .dw 73
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register
+VE_PRR:
+ .dw $ff03
+ .db "PRR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR
+XT_PRR:
+ .dw PFA_DOVARIABLE
+PFA_PRR:
+ .dw 100
+
+.endif
+.if WANT_PORTE == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port E Data Register
+VE_PORTE:
+ .dw $ff05
+ .db "PORTE",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTE
+XT_PORTE:
+ .dw PFA_DOVARIABLE
+PFA_PORTE:
+ .dw 46
+; ( -- addr ) System Constant
+; R( -- )
+; Port E Data Direction Register
+VE_DDRE:
+ .dw $ff04
+ .db "DDRE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRE
+XT_DDRE:
+ .dw PFA_DOVARIABLE
+PFA_DDRE:
+ .dw 45
+; ( -- addr ) System Constant
+; R( -- )
+; Port E Input Pins
+VE_PINE:
+ .dw $ff04
+ .db "PINE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINE
+XT_PINE:
+ .dw PFA_DOVARIABLE
+PFA_PINE:
+ .dw 44
+
+.endif
+.if WANT_TIMER_COUNTER_0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Mask Register
+VE_TIMSK0:
+ .dw $ff06
+ .db "TIMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK0
+XT_TIMSK0:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK0:
+ .dw 110
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Flag register
+VE_TIFR0:
+ .dw $ff05
+ .db "TIFR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR0
+XT_TIFR0:
+ .dw PFA_DOVARIABLE
+PFA_TIFR0:
+ .dw 53
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register A
+VE_TCCR0A:
+ .dw $ff06
+ .db "TCCR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0A
+XT_TCCR0A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0A:
+ .dw 68
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register B
+VE_TCCR0B:
+ .dw $ff06
+ .db "TCCR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0B
+XT_TCCR0B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0B:
+ .dw 69
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw 70
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0A:
+ .dw $ff05
+ .db "OCR0A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0A
+XT_OCR0A:
+ .dw PFA_DOVARIABLE
+PFA_OCR0A:
+ .dw 71
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0B:
+ .dw $ff05
+ .db "OCR0B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0B
+XT_OCR0B:
+ .dw PFA_DOVARIABLE
+PFA_OCR0B:
+ .dw 72
+; ( -- addr ) System Constant
+; R( -- )
+; General Timer/Counter Control Register
+VE_GTCCR:
+ .dw $ff05
+ .db "GTCCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GTCCR
+XT_GTCCR:
+ .dw PFA_DOVARIABLE
+PFA_GTCCR:
+ .dw 67
+
+.endif
+.if WANT_TIMER_COUNTER_1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Mask Register
+VE_TIMSK1:
+ .dw $ff06
+ .db "TIMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK1
+XT_TIMSK1:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK1:
+ .dw 111
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Flag register
+VE_TIFR1:
+ .dw $ff05
+ .db "TIFR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR1
+XT_TIFR1:
+ .dw PFA_DOVARIABLE
+PFA_TIFR1:
+ .dw 54
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw 128
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw 129
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register C
+VE_TCCR1C:
+ .dw $ff06
+ .db "TCCR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1C
+XT_TCCR1C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1C:
+ .dw 130
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Bytes
+VE_TCNT1:
+ .dw $ff05
+ .db "TCNT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1
+XT_TCNT1:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1:
+ .dw 132
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register Bytes
+VE_OCR1A:
+ .dw $ff05
+ .db "OCR1A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1A
+XT_OCR1A:
+ .dw PFA_DOVARIABLE
+PFA_OCR1A:
+ .dw 136
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register Bytes
+VE_OCR1B:
+ .dw $ff05
+ .db "OCR1B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1B
+XT_OCR1B:
+ .dw PFA_DOVARIABLE
+PFA_OCR1B:
+ .dw 138
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Bytes
+VE_ICR1:
+ .dw $ff04
+ .db "ICR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1
+XT_ICR1:
+ .dw PFA_DOVARIABLE
+PFA_ICR1:
+ .dw 134
+
+.endif
+.if WANT_AD_CONVERTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC multiplexer Selection Register
+VE_ADMUX:
+ .dw $ff05
+ .db "ADMUX",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADMUX
+XT_ADMUX:
+ .dw PFA_DOVARIABLE
+PFA_ADMUX:
+ .dw 124
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register
+VE_ADCSRA:
+ .dw $ff06
+ .db "ADCSRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRA
+XT_ADCSRA:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRA:
+ .dw 122
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register Bytes
+VE_ADC:
+ .dw $ff03
+ .db "ADC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADC
+XT_ADC:
+ .dw PFA_DOVARIABLE
+PFA_ADC:
+ .dw 120
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Control and Status Register B
+VE_ADCSRB:
+ .dw $ff06
+ .db "ADCSRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRB
+XT_ADCSRB:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRB:
+ .dw 123
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 0
+VE_DIDR0:
+ .dw $ff05
+ .db "DIDR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR0
+XT_DIDR0:
+ .dw PFA_DOVARIABLE
+PFA_DIDR0:
+ .dw 126
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 0
+VE_DIDR1:
+ .dw $ff05
+ .db "DIDR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR1
+XT_DIDR1:
+ .dw PFA_DOVARIABLE
+PFA_DIDR1:
+ .dw 127
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_AMP0CSR:
+ .dw $ff07
+ .db "AMP0CSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_AMP0CSR
+XT_AMP0CSR:
+ .dw PFA_DOVARIABLE
+PFA_AMP0CSR:
+ .dw 117
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_AMP1CSR:
+ .dw $ff07
+ .db "AMP1CSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_AMP1CSR
+XT_AMP1CSR:
+ .dw PFA_DOVARIABLE
+PFA_AMP1CSR:
+ .dw 118
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_AMP2CSR:
+ .dw $ff07
+ .db "AMP2CSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_AMP2CSR
+XT_AMP2CSR:
+ .dw PFA_DOVARIABLE
+PFA_AMP2CSR:
+ .dw 119
+
+.endif
+.if WANT_LINUART == 1
+; ( -- addr ) System Constant
+; R( -- )
+; LIN Control Register
+VE_LINCR:
+ .dw $ff05
+ .db "LINCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LINCR
+XT_LINCR:
+ .dw PFA_DOVARIABLE
+PFA_LINCR:
+ .dw 200
+; ( -- addr ) System Constant
+; R( -- )
+; LIN Status and Interrupt Register
+VE_LINSIR:
+ .dw $ff06
+ .db "LINSIR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LINSIR
+XT_LINSIR:
+ .dw PFA_DOVARIABLE
+PFA_LINSIR:
+ .dw 201
+; ( -- addr ) System Constant
+; R( -- )
+; LIN Enable Interrupt Register
+VE_LINENIR:
+ .dw $ff07
+ .db "LINENIR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LINENIR
+XT_LINENIR:
+ .dw PFA_DOVARIABLE
+PFA_LINENIR:
+ .dw 202
+; ( -- addr ) System Constant
+; R( -- )
+; LIN Error Register
+VE_LINERR:
+ .dw $ff06
+ .db "LINERR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LINERR
+XT_LINERR:
+ .dw PFA_DOVARIABLE
+PFA_LINERR:
+ .dw 203
+; ( -- addr ) System Constant
+; R( -- )
+; LIN Bit Timing Register
+VE_LINBTR:
+ .dw $ff06
+ .db "LINBTR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LINBTR
+XT_LINBTR:
+ .dw PFA_DOVARIABLE
+PFA_LINBTR:
+ .dw 204
+; ( -- addr ) System Constant
+; R( -- )
+; LIN Baud Rate Low Register
+VE_LINBRRL:
+ .dw $ff07
+ .db "LINBRRL",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LINBRRL
+XT_LINBRRL:
+ .dw PFA_DOVARIABLE
+PFA_LINBRRL:
+ .dw 205
+; ( -- addr ) System Constant
+; R( -- )
+; LIN Baud Rate High Register
+VE_LINBRRH:
+ .dw $ff07
+ .db "LINBRRH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LINBRRH
+XT_LINBRRH:
+ .dw PFA_DOVARIABLE
+PFA_LINBRRH:
+ .dw 206
+; ( -- addr ) System Constant
+; R( -- )
+; LIN Data Length Register
+VE_LINDLR:
+ .dw $ff06
+ .db "LINDLR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LINDLR
+XT_LINDLR:
+ .dw PFA_DOVARIABLE
+PFA_LINDLR:
+ .dw 207
+; ( -- addr ) System Constant
+; R( -- )
+; LIN Identifier Register
+VE_LINIDR:
+ .dw $ff06
+ .db "LINIDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LINIDR
+XT_LINIDR:
+ .dw PFA_DOVARIABLE
+PFA_LINIDR:
+ .dw 208
+; ( -- addr ) System Constant
+; R( -- )
+; LIN Data Buffer Selection Register
+VE_LINSEL:
+ .dw $ff06
+ .db "LINSEL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LINSEL
+XT_LINSEL:
+ .dw PFA_DOVARIABLE
+PFA_LINSEL:
+ .dw 209
+; ( -- addr ) System Constant
+; R( -- )
+; LIN Data Register
+VE_LINDAT:
+ .dw $ff06
+ .db "LINDAT"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LINDAT
+XT_LINDAT:
+ .dw PFA_DOVARIABLE
+PFA_LINDAT:
+ .dw 210
+
+.endif
+.if WANT_SPI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR:
+ .dw $ff04
+ .db "SPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR
+XT_SPCR:
+ .dw PFA_DOVARIABLE
+PFA_SPCR:
+ .dw 76
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR:
+ .dw $ff04
+ .db "SPSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR
+XT_SPSR:
+ .dw PFA_DOVARIABLE
+PFA_SPSR:
+ .dw 77
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR:
+ .dw $ff04
+ .db "SPDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR
+XT_SPDR:
+ .dw PFA_DOVARIABLE
+PFA_SPDR:
+ .dw 78
+
+.endif
+.if WANT_WATCHDOG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCSR:
+ .dw $ff06
+ .db "WDTCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCSR
+XT_WDTCSR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCSR:
+ .dw 96
+
+.endif
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register
+VE_EICRA:
+ .dw $ff05
+ .db "EICRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRA
+XT_EICRA:
+ .dw PFA_DOVARIABLE
+PFA_EICRA:
+ .dw 105
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Mask Register
+VE_EIMSK:
+ .dw $ff05
+ .db "EIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIMSK
+XT_EIMSK:
+ .dw PFA_DOVARIABLE
+PFA_EIMSK:
+ .dw 61
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Flag Register
+VE_EIFR:
+ .dw $ff04
+ .db "EIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIFR
+XT_EIFR:
+ .dw PFA_DOVARIABLE
+PFA_EIFR:
+ .dw 60
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Interrupt Control Register
+VE_PCICR:
+ .dw $ff05
+ .db "PCICR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCICR
+XT_PCICR:
+ .dw PFA_DOVARIABLE
+PFA_PCICR:
+ .dw 104
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 3
+VE_PCMSK3:
+ .dw $ff06
+ .db "PCMSK3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK3
+XT_PCMSK3:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK3:
+ .dw 109
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 2
+VE_PCMSK2:
+ .dw $ff06
+ .db "PCMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK2
+XT_PCMSK2:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK2:
+ .dw 108
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 1
+VE_PCMSK1:
+ .dw $ff06
+ .db "PCMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK1
+XT_PCMSK1:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK1:
+ .dw 107
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 0
+VE_PCMSK0:
+ .dw $ff06
+ .db "PCMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK0
+XT_PCMSK0:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK0:
+ .dw 106
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Interrupt Flag Register
+VE_PCIFR:
+ .dw $ff05
+ .db "PCIFR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCIFR
+XT_PCIFR:
+ .dw PFA_DOVARIABLE
+PFA_PCIFR:
+ .dw 59
+
+.endif
+.if WANT_EEPROM == 1
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Read/Write Access
+VE_EEAR:
+ .dw $ff04
+ .db "EEAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEAR
+XT_EEAR:
+ .dw PFA_DOVARIABLE
+PFA_EEAR:
+ .dw 65
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw 64
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw 63
+
+.endif
diff --git a/amforth-6.5/avr8/devices/atmega32c1/device.py b/amforth-6.5/avr8/devices/atmega32c1/device.py
new file mode 100644
index 0000000..fe62918
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega32c1/device.py
@@ -0,0 +1,477 @@
+# Generated Automatically
+
+# Partname ATmega32C1
+
+MCUREGS = {
+# Interrupt Vectors
+ 'ANACOMP0Addr' : '#2', # Analog Comparator 0
+ 'ANACOMP1Addr' : '#4', # Analog Comparator 1
+ 'ANACOMP2Addr' : '#6', # Analog Comparator 2
+ 'ANACOMP3Addr' : '#8', # Analog Comparator 3
+ 'PSC_FAULTAddr' : '#10', # PSC Fault
+ 'PSC_ECAddr' : '#12', # PSC End of Cycle
+ 'INT0Addr' : '#14', # External Interrupt Request 0
+ 'INT1Addr' : '#16', # External Interrupt Request 1
+ 'INT2Addr' : '#18', # External Interrupt Request 2
+ 'INT3Addr' : '#20', # External Interrupt Request 3
+ 'TIMER1_CAPTAddr' : '#22', # Timer/Counter1 Capture Event
+ 'TIMER1_COMPAAddr' : '#24', # Timer/Counter1 Compare Match A
+ 'TIMER1_COMPBAddr' : '#26', # Timer/Counter1 Compare Match B
+ 'TIMER1_OVFAddr' : '#28', # Timer1/Counter1 Overflow
+ 'TIMER0_COMPAAddr' : '#30', # Timer/Counter0 Compare Match A
+ 'TIMER0_COMPBAddr' : '#32', # Timer/Counter0 Compare Match B
+ 'TIMER0_OVFAddr' : '#34', # Timer/Counter0 Overflow
+ 'CAN_INTAddr' : '#36', # CAN MOB, Burst, General Errors
+ 'CAN_TOVFAddr' : '#38', # CAN Timer Overflow
+ 'LIN_TCAddr' : '#40', # LIN Transfer Complete
+ 'LIN_ERRAddr' : '#42', # LIN Error
+ 'PCINT0Addr' : '#44', # Pin Change Interrupt Request 0
+ 'PCINT1Addr' : '#46', # Pin Change Interrupt Request 1
+ 'PCINT2Addr' : '#48', # Pin Change Interrupt Request 2
+ 'PCINT3Addr' : '#50', # Pin Change Interrupt Request 3
+ 'SPI_STCAddr' : '#52', # SPI Serial Transfer Complete
+ 'ADCAddr' : '#54', # ADC Conversion Complete
+ 'WDTAddr' : '#56', # Watchdog Time-Out Interrupt
+ 'EE_READYAddr' : '#58', # EEPROM Ready
+ 'SPM_READYAddr' : '#60', # Store Program Memory Read
+
+# Module PORTB
+ 'PORTB' : '$25', # Port B Data Register
+ 'DDRB' : '$24', # Port B Data Direction Register
+ 'PINB' : '$23', # Port B Input Pins
+
+# Module PORTC
+ 'PORTC' : '$28', # Port C Data Register
+ 'DDRC' : '$27', # Port C Data Direction Register
+ 'PINC' : '$26', # Port C Input Pins
+
+# Module PORTD
+ 'PORTD' : '$2b', # Port D Data Register
+ 'DDRD' : '$2a', # Port D Data Direction Register
+ 'PIND' : '$29', # Port D Input Pins
+
+# Module CAN
+ 'CANGCON' : '$d8', # CAN General Control Register
+ 'CANGCON_ABRQ': '$80', # Abort Request
+ 'CANGCON_OVRQ': '$40', # Overload Frame Request
+ 'CANGCON_TTC': '$20', # Time Trigger Communication
+ 'CANGCON_SYNTTC': '$10', # Synchronization of TTC
+ 'CANGCON_LISTEN': '$8', # Listening Mode
+ 'CANGCON_TEST': '$4', # Test Mode
+ 'CANGCON_ENASTB': '$2', # Enable / Standby
+ 'CANGCON_SWRES': '$1', # Software Reset Request
+ 'CANGSTA' : '$d9', # CAN General Status Register
+ 'CANGSTA_OVFG': '$40', # Overload Frame Flag
+ 'CANGSTA_TXBSY': '$10', # Transmitter Busy
+ 'CANGSTA_RXBSY': '$8', # Receiver Busy
+ 'CANGSTA_ENFG': '$4', # Enable Flag
+ 'CANGSTA_BOFF': '$2', # Bus Off Mode
+ 'CANGSTA_ERRP': '$1', # Error Passive Mode
+ 'CANGIT' : '$da', # CAN General Interrupt Register
+ 'CANGIT_CANIT': '$80', # General Interrupt Flag
+ 'CANGIT_BOFFIT': '$40', # Bus Off Interrupt Flag
+ 'CANGIT_OVRTIM': '$20', # Overrun CAN Timer Flag
+ 'CANGIT_BXOK': '$10', # Burst Receive Interrupt Flag
+ 'CANGIT_SERG': '$8', # Stuff Error General Flag
+ 'CANGIT_CERG': '$4', # CRC Error General Flag
+ 'CANGIT_FERG': '$2', # Form Error General Flag
+ 'CANGIT_AERG': '$1', # Ackknowledgement Error General
+ 'CANGIE' : '$db', # CAN General Interrupt Enable R
+ 'CANGIE_ENIT': '$80', # Enable all Interrupts
+ 'CANGIE_ENBOFF': '$40', # Enable Bus Off Interrupt
+ 'CANGIE_ENRX': '$20', # Enable Receive Interrupt
+ 'CANGIE_ENTX': '$10', # Enable Transmitt Interrupt
+ 'CANGIE_ENERR': '$8', # Enable MOb Error Interrupt
+ 'CANGIE_ENBX': '$4', # Enable Burst Receive Interrupt
+ 'CANGIE_ENERG': '$2', # Enable General Error Interrupt
+ 'CANGIE_ENOVRT': '$1', # Enable CAN Timer Overrun Inter
+ 'CANEN2' : '$dc', # Enable MOb Register 2
+ 'CANEN2_ENMOB': '$3f', # Enable MObs
+ 'CANEN1' : '$dd', # Enable MOb Register 1(empty)
+ 'CANIE2' : '$de', # Enable Interrupt MOb Register
+ 'CANIE2_IEMOB': '$3f', # Interrupt Enable MObs
+ 'CANIE1' : '$df', # Enable Interrupt MOb Register
+ 'CANSIT2' : '$e0', # CAN Status Interrupt MOb Regis
+ 'CANSIT2_SIT': '$3f', # Status of Interrupt MObs
+ 'CANSIT1' : '$e1', # CAN Status Interrupt MOb Regis
+ 'CANBT1' : '$e2', # CAN Bit Timing Register 1
+ 'CANBT1_BRP': '$7e', # Baud Rate Prescaler bits
+ 'CANBT2' : '$e3', # CAN Bit Timing Register 2
+ 'CANBT2_SJW': '$60', # Re-Sync Jump Width bits
+ 'CANBT2_PRS': '$e', # Propagation Time Segment bits
+ 'CANBT3' : '$e4', # CAN Bit Timing Register 3
+ 'CANBT3_PHS2': '$70', # Phase Segment 2 bits
+ 'CANBT3_PHS1': '$e', # Phase Segment 1 bits
+ 'CANBT3_SMP': '$1', # Sample Type
+ 'CANTCON' : '$e5', # Timer Control Register
+ 'CANTIML' : '$e6', # Timer Register Low
+ 'CANTIMH' : '$e7', # Timer Register High
+ 'CANTTCL' : '$e8', # TTC Timer Register Low
+ 'CANTTCH' : '$e9', # TTC Timer Register High
+ 'CANTEC' : '$ea', # Transmit Error Counter Registe
+ 'CANREC' : '$eb', # Receive Error Counter Register
+ 'CANHPMOB' : '$ec', # Highest Priority MOb Register
+ 'CANHPMOB_HPMOB': '$f0', # Highest Priority MOb Number bi
+ 'CANHPMOB_CGP': '$f', # CAN General Purpose bits
+ 'CANPAGE' : '$ed', # Page MOb Register
+ 'CANPAGE_MOBNB': '$f0', # MOb Number bits
+ 'CANPAGE_AINC': '$8', # MOb Data Buffer Auto Increment
+ 'CANPAGE_INDX': '$7', # Data Buffer Index bits
+ 'CANSTMOB' : '$ee', # MOb Status Register
+ 'CANSTMOB_DLCW': '$80', # Data Length Code Warning on MO
+ 'CANSTMOB_TXOK': '$40', # Transmit OK on MOb
+ 'CANSTMOB_RXOK': '$20', # Receive OK on MOb
+ 'CANSTMOB_BERR': '$10', # Bit Error on MOb
+ 'CANSTMOB_SERR': '$8', # Stuff Error on MOb
+ 'CANSTMOB_CERR': '$4', # CRC Error on MOb
+ 'CANSTMOB_FERR': '$2', # Form Error on MOb
+ 'CANSTMOB_AERR': '$1', # Ackknowledgement Error on MOb
+ 'CANCDMOB' : '$ef', # MOb Control and DLC Register
+ 'CANCDMOB_CONMOB': '$c0', # MOb Config bits
+ 'CANCDMOB_RPLV': '$20', # Reply Valid
+ 'CANCDMOB_IDE': '$10', # Identifier Extension
+ 'CANCDMOB_DLC': '$f', # Data Length Code bits
+ 'CANIDT4' : '$f0', # Identifier Tag Register 4
+ 'CANIDT4_IDT': '$f8', #
+ 'CANIDT4_RTRTAG': '$4', #
+ 'CANIDT4_RB1TAG': '$2', #
+ 'CANIDT4_RB0TAG': '$1', #
+ 'CANIDT3' : '$f1', # Identifier Tag Register 3
+ 'CANIDT2' : '$f2', # Identifier Tag Register 2
+ 'CANIDT1' : '$f3', # Identifier Tag Register 1
+ 'CANIDM4' : '$f4', # Identifier Mask Register 4
+ 'CANIDM3' : '$f5', # Identifier Mask Register 3
+ 'CANIDM2' : '$f6', # Identifier Mask Register 2
+ 'CANIDM1' : '$f7', # Identifier Mask Register 1
+ 'CANSTML' : '$f8', # Time Stamp Register Low
+ 'CANSTMH' : '$f9', # Time Stamp Register High
+ 'CANMSG' : '$fa', # Message Data Register
+
+# Module ANALOG_COMPARATOR
+ 'AC0CON' : '$94', # Analog Comparator 0 Control Re
+ 'AC0CON_AC0EN': '$80', # Analog Comparator 0 Enable Bit
+ 'AC0CON_AC0IE': '$40', # Analog Comparator 0 Interrupt
+ 'AC0CON_AC0IS': '$30', # Analog Comparator 0 Interrupt
+ 'AC0CON_ACCKSEL': '$8', # Analog Comparator Clock Select
+ 'AC0CON_AC0M': '$7', # Analog Comparator 0 Multiplexe
+ 'AC1CON' : '$95', # Analog Comparator 1 Control Re
+ 'AC1CON_AC1EN': '$80', # Analog Comparator 1 Enable Bit
+ 'AC1CON_AC1IE': '$40', # Analog Comparator 1 Interrupt
+ 'AC1CON_AC1IS': '$30', # Analog Comparator 1 Interrupt
+ 'AC1CON_AC1ICE': '$8', # Analog Comparator 1 Interrupt
+ 'AC1CON_AC1M': '$7', # Analog Comparator 1 Multiplexe
+ 'AC2CON' : '$96', # Analog Comparator 2 Control Re
+ 'AC2CON_AC2EN': '$80', # Analog Comparator 2 Enable Bit
+ 'AC2CON_AC2IE': '$40', # Analog Comparator 2 Interrupt
+ 'AC2CON_AC2IS': '$30', # Analog Comparator 2 Interrupt
+ 'AC2CON_AC2M': '$7', # Analog Comparator 2 Multiplexe
+ 'AC3CON' : '$97', # Analog Comparator 3 Control Re
+ 'AC3CON_AC3EN': '$80', # Analog Comparator 3 Enable Bit
+ 'AC3CON_AC3IE': '$40', # Analog Comparator 3 Interrupt
+ 'AC3CON_AC3IS': '$30', # Analog Comparator 3 Interrupt
+ 'AC3CON_AC3M': '$7', # Analog Comparator 3 Multiplexe
+ 'ACSR' : '$50', # Analog Comparator Status Regis
+ 'ACSR_AC3IF': '$80', # Analog Comparator 3 Interrupt
+ 'ACSR_AC2IF': '$40', # Analog Comparator 2 Interrupt
+ 'ACSR_AC1IF': '$20', # Analog Comparator 1 Interrupt
+ 'ACSR_AC0IF': '$10', # Analog Comparator 0 Interrupt
+ 'ACSR_AC3O': '$8', # Analog Comparator 3 Output Bit
+ 'ACSR_AC2O': '$4', # Analog Comparator 2 Output Bit
+ 'ACSR_AC1O': '$2', # Analog Comparator 1 Output Bit
+ 'ACSR_AC0O': '$1', # Analog Comparator 0 Output Bit
+
+# Module DA_CONVERTER
+ 'DACH' : '$92', # DAC Data Register High Byte
+ 'DACH_DACH': '$ff', # DAC Data Register High Byte Bi
+ 'DACL' : '$91', # DAC Data Register Low Byte
+ 'DACL_DACL': '$ff', # DAC Data Register Low Byte Bit
+ 'DACON' : '$90', # DAC Control Register
+ 'DACON_DAATE': '$80', # DAC Auto Trigger Enable Bit
+ 'DACON_DATS': '$70', # DAC Trigger Selection Bits
+ 'DACON_DALA': '$4', # DAC Left Adjust
+ 'DACON_DAEN': '$1', # DAC Enable Bit
+
+# Module CPU
+ 'SPMCSR' : '$57', # Store Program Memory Control R
+ 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
+ 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
+ 'SPMCSR_SIGRD': '$20', # Signature Row Read
+ 'SPMCSR_RWWSRE': '$10', # Read While Write section read
+ 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
+ 'SPMCSR_PGWRT': '$4', # Page Write
+ 'SPMCSR_PGERS': '$2', # Page Erase
+ 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
+ 'SREG' : '$5f', # Status Register
+ 'SREG_I': '$80', # Global Interrupt Enable
+ 'SREG_T': '$40', # Bit Copy Storage
+ 'SREG_H': '$20', # Half Carry Flag
+ 'SREG_S': '$10', # Sign Bit
+ 'SREG_V': '$8', # Two's Complement Overflow Flag
+ 'SREG_N': '$4', # Negative Flag
+ 'SREG_Z': '$2', # Zero Flag
+ 'SREG_C': '$1', # Carry Flag
+ 'SP' : '$5d', # Stack Pointer
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_SPIPS': '$80', # SPI Pin Select
+ 'MCUCR_PUD': '$10', # Pull-up disable
+ 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
+ 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
+ 'MCUSR_BORF': '$4', # Brown-out Reset Flag
+ 'MCUSR_EXTRF': '$2', # External Reset Flag
+ 'MCUSR_PORF': '$1', # Power-on reset flag
+ 'OSCCAL' : '$66', # Oscillator Calibration Value
+ 'CLKPR' : '$61', #
+ 'CLKPR_CLKPCE': '$80', #
+ 'CLKPR_CLKPS': '$f', #
+ 'SMCR' : '$53', # Sleep Mode Control Register
+ 'SMCR_SM': '$e', # Sleep Mode Select bits
+ 'SMCR_SE': '$1', # Sleep Enable
+ 'GPIOR2' : '$3a', # General Purpose IO Register 2
+ 'GPIOR2_GPIOR': '$ff', # General Purpose IO Register 2
+ 'GPIOR1' : '$39', # General Purpose IO Register 1
+ 'GPIOR1_GPIOR': '$ff', # General Purpose IO Register 1
+ 'GPIOR0' : '$3e', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR07': '$80', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR06': '$40', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR05': '$20', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR04': '$10', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR03': '$8', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR02': '$4', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR01': '$2', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR00': '$1', # General Purpose IO Register 0
+ 'PLLCSR' : '$49', # PLL Control And Status Registe
+ 'PLLCSR_PLLF': '$4', # PLL Factor
+ 'PLLCSR_PLLE': '$2', # PLL Enable
+ 'PLLCSR_PLOCK': '$1', # PLL Lock Detector
+ 'PRR' : '$64', # Power Reduction Register
+ 'PRR_PRCAN': '$40', # Power Reduction CAN
+ 'PRR_PRPSC': '$20', # Power Reduction PSC
+ 'PRR_PRTIM1': '$10', # Power Reduction Timer/Counter1
+ 'PRR_PRTIM0': '$8', # Power Reduction Timer/Counter0
+ 'PRR_PRSPI': '$4', # Power Reduction Serial Periphe
+ 'PRR_PRLIN': '$2', # Power Reduction LIN UART
+ 'PRR_PRADC': '$1', # Power Reduction ADC
+
+# Module PORTE
+ 'PORTE' : '$2e', # Port E Data Register
+ 'DDRE' : '$2d', # Port E Data Direction Register
+ 'PINE' : '$2c', # Port E Input Pins
+
+# Module TIMER_COUNTER_0
+ 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
+ 'TIMSK0_OCIE0B': '$4', # Timer/Counter0 Output Compare
+ 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
+ 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
+ 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
+ 'TIFR0_OCF0B': '$4', # Timer/Counter0 Output Compare
+ 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
+ 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
+ 'TCCR0A' : '$44', # Timer/Counter Control Registe
+ 'TCCR0A_COM0A': '$c0', # Compare Output Mode, Phase Cor
+ 'TCCR0A_COM0B': '$30', # Compare Output Mode, Fast PWm
+ 'TCCR0A_WGM0': '$3', # Waveform Generation Mode
+ 'TCCR0B' : '$45', # Timer/Counter Control Register
+ 'TCCR0B_FOC0A': '$80', # Force Output Compare A
+ 'TCCR0B_FOC0B': '$40', # Force Output Compare B
+ 'TCCR0B_WGM02': '$8', #
+ 'TCCR0B_CS0': '$7', # Clock Select
+ 'TCNT0' : '$46', # Timer/Counter0
+ 'OCR0A' : '$47', # Timer/Counter0 Output Compare
+ 'OCR0B' : '$48', # Timer/Counter0 Output Compare
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_ICPSEL1': '$40', # Timer1 Input Capture Selection
+ 'GTCCR_PSR10': '$1', # Prescaler Reset Timer/Counter1
+
+# Module TIMER_COUNTER_1
+ 'TIMSK1' : '$6f', # Timer/Counter Interrupt Mask R
+ 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
+ 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output CompareB
+ 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output CompareA
+ 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
+ 'TIFR1' : '$36', # Timer/Counter Interrupt Flag r
+ 'TIFR1_ICF1': '$20', # Input Capture Flag 1
+ 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
+ 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
+ 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
+ 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
+ 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
+ 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
+ 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
+ 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
+ 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
+ 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
+ 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
+ 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
+ 'TCCR1C' : '$82', # Timer/Counter1 Control Registe
+ 'TCCR1C_FOC1A': '$80', #
+ 'TCCR1C_FOC1B': '$40', #
+ 'TCNT1' : '$84', # Timer/Counter1 Bytes
+ 'OCR1A' : '$88', # Timer/Counter1 Output Compare
+ 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
+ 'ICR1' : '$86', # Timer/Counter1 Input Capture R
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSRSYNC': '$1', # Prescaler Reset Timer/Counter1
+
+# Module AD_CONVERTER
+ 'ADMUX' : '$7c', # The ADC multiplexer Selection
+ 'ADMUX_REFS': '$c0', # Reference Selection Bits
+ 'ADMUX_ADLAR': '$20', # Left Adjust Result
+ 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
+ 'ADCSRA' : '$7a', # The ADC Control and Status reg
+ 'ADCSRA_ADEN': '$80', # ADC Enable
+ 'ADCSRA_ADSC': '$40', # ADC Start Conversion
+ 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
+ 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
+ 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
+ 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
+ 'ADC' : '$78', # ADC Data Register Bytes
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ADHSM': '$80', # ADC High Speed Mode
+ 'ADCSRB_ISRCEN': '$40', # Current Source Enable
+ 'ADCSRB_AREFEN': '$20', # Analog Reference pin Enable
+ 'ADCSRB_ADTS': '$f', # ADC Auto Trigger Sources
+ 'DIDR0' : '$7e', # Digital Input Disable Register
+ 'DIDR0_ADC7D': '$80', # ADC7 Digital input Disable
+ 'DIDR0_ADC6D': '$40', # ADC6 Digital input Disable
+ 'DIDR0_ADC5D': '$20', # ADC5 Digital input Disable
+ 'DIDR0_ADC4D': '$10', # ADC4 Digital input Disable
+ 'DIDR0_ADC3D': '$8', # ADC3 Digital input Disable
+ 'DIDR0_ADC2D': '$4', # ADC2 Digital input Disable
+ 'DIDR0_ADC1D': '$2', # ADC1 Digital input Disable
+ 'DIDR0_ADC0D': '$1', # ADC0 Digital input Disable
+ 'DIDR1' : '$7f', # Digital Input Disable Register
+ 'DIDR1_AMP2PD': '$40', # AMP2P Pin Digital input Disabl
+ 'DIDR1_ACMP0D': '$20', # ACMP0 Pin Digital input Disabl
+ 'DIDR1_AMP0PD': '$10', # AMP0P Pin Digital input Disabl
+ 'DIDR1_AMP0ND': '$8', # AMP0N Pin Digital input Disabl
+ 'DIDR1_ADC10D': '$4', # ADC10 Pin Digital input Disabl
+ 'DIDR1_ADC9D': '$2', # ADC9 Pin Digital input Disable
+ 'DIDR1_ADC8D': '$1', # ADC8 Pin Digital input Disable
+ 'AMP0CSR' : '$75', #
+ 'AMP0CSR_AMP0EN': '$80', #
+ 'AMP0CSR_AMP0IS': '$40', #
+ 'AMP0CSR_AMP0G': '$30', #
+ 'AMP0CSR_AMPCMP0': '$8', # Amplifier 0 - Comparator 0 Con
+ 'AMP0CSR_AMP0TS': '$7', #
+ 'AMP1CSR' : '$76', #
+ 'AMP1CSR_AMP1EN': '$80', #
+ 'AMP1CSR_AMP1IS': '$40', #
+ 'AMP1CSR_AMP1G': '$30', #
+ 'AMP1CSR_AMPCMP1': '$8', # Amplifier 1 - Comparator 1 Con
+ 'AMP1CSR_AMP1TS': '$7', #
+ 'AMP2CSR' : '$77', #
+ 'AMP2CSR_AMP2EN': '$80', #
+ 'AMP2CSR_AMP2IS': '$40', #
+ 'AMP2CSR_AMP2G': '$30', #
+ 'AMP2CSR_AMPCMP2': '$8', # Amplifier 2 - Comparator 2 Con
+ 'AMP2CSR_AMP2TS': '$7', #
+
+# Module LINUART
+ 'LINCR' : '$c8', # LIN Control Register
+ 'LINCR_LSWRES': '$80', # Software Reset
+ 'LINCR_LIN13': '$40', # LIN Standard
+ 'LINCR_LCONF': '$30', # LIN Configuration bits
+ 'LINCR_LENA': '$8', # LIN or UART Enable
+ 'LINCR_LCMD': '$7', # LIN Command and Mode bits
+ 'LINSIR' : '$c9', # LIN Status and Interrupt Regis
+ 'LINSIR_LIDST': '$e0', # Identifier Status bits
+ 'LINSIR_LBUSY': '$10', # Busy Signal
+ 'LINSIR_LERR': '$8', # Error Interrupt
+ 'LINSIR_LIDOK': '$4', # Identifier Interrupt
+ 'LINSIR_LTXOK': '$2', # Transmit Performed Interrupt
+ 'LINSIR_LRXOK': '$1', # Receive Performed Interrupt
+ 'LINENIR' : '$ca', # LIN Enable Interrupt Register
+ 'LINENIR_LENERR': '$8', # Enable Error Interrupt
+ 'LINENIR_LENIDOK': '$4', # Enable Identifier Interrupt
+ 'LINENIR_LENTXOK': '$2', # Enable Transmit Performed Inte
+ 'LINENIR_LENRXOK': '$1', # Enable Receive Performed Inter
+ 'LINERR' : '$cb', # LIN Error Register
+ 'LINERR_LABORT': '$80', # Abort Flag
+ 'LINERR_LTOERR': '$40', # Frame Time Out Error Flag
+ 'LINERR_LOVERR': '$20', # Overrun Error Flag
+ 'LINERR_LFERR': '$10', # Framing Error Flag
+ 'LINERR_LSERR': '$8', # Synchronization Error Flag
+ 'LINERR_LPERR': '$4', # Parity Error Flag
+ 'LINERR_LCERR': '$2', # Checksum Error Flag
+ 'LINERR_LBERR': '$1', # Bit Error Flag
+ 'LINBTR' : '$cc', # LIN Bit Timing Register
+ 'LINBTR_LDISR': '$80', # Disable Bit Timing Resynchroni
+ 'LINBTR_LBT': '$3f', # LIN Bit Timing bits
+ 'LINBRRL' : '$cd', # LIN Baud Rate Low Register
+ 'LINBRRL_LDIV': '$ff', #
+ 'LINBRRH' : '$ce', # LIN Baud Rate High Register
+ 'LINBRRH_LDIV': '$f', #
+ 'LINDLR' : '$cf', # LIN Data Length Register
+ 'LINDLR_LTXDL': '$f0', # LIN Transmit Data Length bits
+ 'LINDLR_LRXDL': '$f', # LIN Receive Data Length bits
+ 'LINIDR' : '$d0', # LIN Identifier Register
+ 'LINIDR_LP': '$c0', # Parity bits
+ 'LINIDR_LID': '$3f', # Identifier bit 5 or Data Lengt
+ 'LINSEL' : '$d1', # LIN Data Buffer Selection Regi
+ 'LINSEL_LAINC': '$8', # Auto Increment of Data Buffer
+ 'LINSEL_LINDX': '$7', # FIFO LIN Data Buffer Index bit
+ 'LINDAT' : '$d2', # LIN Data Register
+ 'LINDAT_LDATA': '$ff', #
+
+# Module SPI
+ 'SPCR' : '$4c', # SPI Control Register
+ 'SPCR_SPIE': '$80', # SPI Interrupt Enable
+ 'SPCR_SPE': '$40', # SPI Enable
+ 'SPCR_DORD': '$20', # Data Order
+ 'SPCR_MSTR': '$10', # Master/Slave Select
+ 'SPCR_CPOL': '$8', # Clock polarity
+ 'SPCR_CPHA': '$4', # Clock Phase
+ 'SPCR_SPR': '$3', # SPI Clock Rate Selects
+ 'SPSR' : '$4d', # SPI Status Register
+ 'SPSR_SPIF': '$80', # SPI Interrupt Flag
+ 'SPSR_WCOL': '$40', # Write Collision Flag
+ 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
+ 'SPDR' : '$4e', # SPI Data Register
+
+# Module WATCHDOG
+ 'WDTCSR' : '$60', # Watchdog Timer Control Registe
+ 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
+ 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
+ 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
+ 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
+ 'WDTCSR_WDE': '$8', # Watch Dog Enable
+
+# Module EXTERNAL_INTERRUPT
+ 'EICRA' : '$69', # External Interrupt Control Reg
+ 'EICRA_ISC3': '$c0', # External Interrupt Sense Contr
+ 'EICRA_ISC2': '$30', # External Interrupt Sense Contr
+ 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
+ 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
+ 'EIMSK' : '$3d', # External Interrupt Mask Regist
+ 'EIMSK_INT': '$f', # External Interrupt Request 3 E
+ 'EIFR' : '$3c', # External Interrupt Flag Regist
+ 'EIFR_INTF': '$f', # External Interrupt Flags
+ 'PCICR' : '$68', # Pin Change Interrupt Control R
+ 'PCICR_PCIE': '$f', # Pin Change Interrupt Enables
+ 'PCMSK3' : '$6d', # Pin Change Mask Register 3
+ 'PCMSK3_PCINT': '$7', # Pin Change Enable Masks
+ 'PCMSK2' : '$6c', # Pin Change Mask Register 2
+ 'PCMSK2_PCINT': '$ff', # Pin Change Enable Masks
+ 'PCMSK1' : '$6b', # Pin Change Mask Register 1
+ 'PCMSK1_PCINT': '$ff', # Pin Change Enable Masks
+ 'PCMSK0' : '$6a', # Pin Change Mask Register 0
+ 'PCMSK0_PCINT': '$ff', # Pin Change Enable Masks
+ 'PCIFR' : '$3b', # Pin Change Interrupt Flag Regi
+ 'PCIFR_PCIF': '$f', # Pin Change Interrupt Flags
+
+# Module EEPROM
+ 'EEAR' : '$41', # EEPROM Read/Write Access
+ 'EEDR' : '$40', # EEPROM Data Register
+ 'EECR' : '$3f', # EEPROM Control Register
+ 'EECR_EEPM': '$30', #
+ 'EECR_EERIE': '$8', # EEProm Ready Interrupt Enable
+ 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
+ 'EECR_EEWE': '$2', # EEPROM Write Enable
+ 'EECR_EERE': '$1', # EEPROM Read Enable
+
+ '__amforth_dummy':'0'
+}
diff --git a/amforth-6.5/avr8/devices/atmega32c1/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega32c1/words/no-jtag.asm
new file mode 100644
index 0000000..352a4bb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega32c1/words/no-jtag.asm
@@ -0,0 +1,14 @@
+; ( -- )
+; ( -- )
+; MCU
+; disable jtag at runtime
+VE_NOJTAG:
+ .dw $FF05
+ .db "-jtag",0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOJTAG
+XT_NOJTAG:
+ .dw PFA_NOJTAG
+PFA_NOJTAG:
+
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega32c1/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega32c1/words/no-wdt.asm
new file mode 100644
index 0000000..ff6ddd1
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega32c1/words/no-wdt.asm
@@ -0,0 +1,34 @@
+; ( -- )
+; MCU
+; disable watch dog timer at runtime
+VE_NOWDT:
+ .dw $ff04
+ .db "-wdt"
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOWDT
+XT_NOWDT:
+ .dw PFA_NOWDT
+PFA_NOWDT:
+
+ in temp1,SREG
+ push temp1
+ ; Turn always off global interrupt.
+ cli
+ ; Reset Watchdog Timer
+ wdr
+ ; Clear WDRF in MCUSR
+ in temp1, MCUSR
+ andi temp1, (0xff & (0<<WDRF))
+ out MCUSR, temp1
+ ; Write logical one to WDCE and WDE
+ ; Keep old prescaler setting to prevent unintentional time-out
+ in_ temp1, WDTCSR
+ ori temp1, (1<<WDCE) | (1<<WDE)
+ out_ WDTCSR, temp1
+ ; Turn off WDT
+ ldi temp1, (0<<WDE)
+ out_ WDTCSR, temp1
+ ; restore status register
+ pop temp1
+ out SREG,temp1
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega32c1/words/sleep.asm b/amforth-6.5/avr8/devices/atmega32c1/words/sleep.asm
new file mode 100644
index 0000000..256249c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega32c1/words/sleep.asm
@@ -0,0 +1,19 @@
+; ( mode -- )
+; MCU
+; put the controller into the specified sleep mode
+VE_SLEEP:
+ .dw $ff05
+ .db "sleep", 0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_SLEEP
+XT_SLEEP:
+ .dw PFA_SLEEP
+PFA_SLEEP:
+ andi tosl, 7 ; leave only legal mode bits
+ lsl tosl ; move to correct location (bits 3-1)
+ ori tosl, 1 ; set the SE bit
+ out_ SMCR, tosl ; set the sleep config
+ sleep ; nighty-night
+ out_ SMCR, zerol ; 0 protects against accidental sleeps
+ loadtos ; pop argument from stack
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega32hvb/atmega32hvb.frt b/amforth-6.5/avr8/devices/atmega32hvb/atmega32hvb.frt
new file mode 100644
index 0000000..5a117ed
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega32hvb/atmega32hvb.frt
@@ -0,0 +1,33 @@
+\ Partname: ATmega32HVB
+\ generated automatically
+
+
+\ Interrupts
+&2 constant BPINTAddr \ Battery Protection Interrupt
+&4 constant VREGMONAddr \ Voltage regulator monitor interrupt
+&6 constant INT0Addr \ External Interrupt Request 0
+&8 constant INT1Addr \ External Interrupt Request 1
+&10 constant INT2Addr \ External Interrupt Request 2
+&12 constant INT3Addr \ External Interrupt Request 3
+&14 constant PCINT0Addr \ Pin Change Interrupt 0
+&16 constant PCINT1Addr \ Pin Change Interrupt 1
+&18 constant WDTAddr \ Watchdog Timeout Interrupt
+&20 constant BGSCDAddr \ Bandgap Buffer Short Circuit Detected
+&22 constant CHDETAddr \ Charger Detect
+&24 constant TIMER1_ICAddr \ Timer 1 Input capture
+&26 constant TIMER1_COMPAAddr \ Timer 1 Compare Match A
+&28 constant TIMER1_COMPBAddr \ Timer 1 Compare Match B
+&30 constant TIMER1_OVFAddr \ Timer 1 overflow
+&32 constant TIMER0_ICAddr \ Timer 0 Input Capture
+&34 constant TIMER0_COMPAAddr \ Timer 0 Comapre Match A
+&36 constant TIMER0_COMPBAddr \ Timer 0 Compare Match B
+&38 constant TIMER0_OVFAddr \ Timer 0 Overflow
+&40 constant TWIBUSCDAddr \ Two-Wire Bus Connect/Disconnect
+&42 constant TWIAddr \ Two-Wire Serial Interface
+&44 constant SPI_STCAddr \ SPI Serial transfer complete
+&46 constant VADCAddr \ Voltage ADC Conversion Complete
+&48 constant CCADC_CONVAddr \ Coulomb Counter ADC Conversion Complete
+&50 constant CCADC_REG_CURAddr \ Coloumb Counter ADC Regular Current
+&52 constant CCADC_ACCAddr \ Coloumb Counter ADC Accumulator
+&54 constant EE_READYAddr \ EEPROM Ready
+&56 constant SPMAddr \ SPM Ready
diff --git a/amforth-6.5/avr8/devices/atmega32hvb/device.asm b/amforth-6.5/avr8/devices/atmega32hvb/device.asm
new file mode 100644
index 0000000..310e3e7
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega32hvb/device.asm
@@ -0,0 +1,101 @@
+; Partname: ATmega32HVB
+; generated automatically, do not edit
+
+.nolist
+ .include "m32HVBdef.inc"
+.list
+
+.equ ramstart = 256
+.equ CELLSIZE = 2
+.macro readflashcell
+ lsl zl
+ rol zh
+ lpm @0, Z+
+ lpm @1, Z+
+.endmacro
+.macro writeflashcell
+ lsl zl
+ rol zh
+.endmacro
+.equ intvecsize = 2 ; please verify; flash size: 32768 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.org 2
+ rcall isr ; Battery Protection Interrupt
+.org 4
+ rcall isr ; Voltage regulator monitor interrupt
+.org 6
+ rcall isr ; External Interrupt Request 0
+.org 8
+ rcall isr ; External Interrupt Request 1
+.org 10
+ rcall isr ; External Interrupt Request 2
+.org 12
+ rcall isr ; External Interrupt Request 3
+.org 14
+ rcall isr ; Pin Change Interrupt 0
+.org 16
+ rcall isr ; Pin Change Interrupt 1
+.org 18
+ rcall isr ; Watchdog Timeout Interrupt
+.org 20
+ rcall isr ; Bandgap Buffer Short Circuit Detected
+.org 22
+ rcall isr ; Charger Detect
+.org 24
+ rcall isr ; Timer 1 Input capture
+.org 26
+ rcall isr ; Timer 1 Compare Match A
+.org 28
+ rcall isr ; Timer 1 Compare Match B
+.org 30
+ rcall isr ; Timer 1 overflow
+.org 32
+ rcall isr ; Timer 0 Input Capture
+.org 34
+ rcall isr ; Timer 0 Comapre Match A
+.org 36
+ rcall isr ; Timer 0 Compare Match B
+.org 38
+ rcall isr ; Timer 0 Overflow
+.org 40
+ rcall isr ; Two-Wire Bus Connect/Disconnect
+.org 42
+ rcall isr ; Two-Wire Serial Interface
+.org 44
+ rcall isr ; SPI Serial transfer complete
+.org 46
+ rcall isr ; Voltage ADC Conversion Complete
+.org 48
+ rcall isr ; Coulomb Counter ADC Conversion Complete
+.org 50
+ rcall isr ; Coloumb Counter ADC Regular Current
+.org 52
+ rcall isr ; Coloumb Counter ADC Accumulator
+.org 54
+ rcall isr ; EEPROM Ready
+.org 56
+ rcall isr ; SPM Ready
+.equ INTVECTORS = 29
+.nooverlap
+
+; compatability layer (maybe empty)
+.equ SPMEN = SELFPRGEN
+.equ SPMCSR = SPMCR
+.equ EEPE = EEWE
+.equ EEMPE = EEMWE
+
+; controller data area, environment query mcu-info
+mcu_info:
+mcu_ramsize:
+ .dw 2048
+mcu_eepromsize:
+ .dw 1024
+mcu_maxdp:
+ .dw 28672
+mcu_numints:
+ .dw 29
+mcu_name:
+ .dw 11
+ .db "ATmega32HVB",0
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega32hvb/device.inc b/amforth-6.5/avr8/devices/atmega32hvb/device.inc
new file mode 100644
index 0000000..9ea3b65
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega32hvb/device.inc
@@ -0,0 +1,3 @@
+; Partname: ATmega32HVB
+; generated automatically, no not edit
+
diff --git a/amforth-6.5/avr8/devices/atmega32hvb/device.py b/amforth-6.5/avr8/devices/atmega32hvb/device.py
new file mode 100644
index 0000000..0c72334
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega32hvb/device.py
@@ -0,0 +1,342 @@
+# Generated Automatically
+
+# Partname ATmega32HVB
+
+MCUREGS = {
+# Interrupt Vectors
+ 'BPINTAddr' : '#2', # Battery Protection Interrupt
+ 'VREGMONAddr' : '#4', # Voltage regulator monitor interrupt
+ 'INT0Addr' : '#6', # External Interrupt Request 0
+ 'INT1Addr' : '#8', # External Interrupt Request 1
+ 'INT2Addr' : '#10', # External Interrupt Request 2
+ 'INT3Addr' : '#12', # External Interrupt Request 3
+ 'PCINT0Addr' : '#14', # Pin Change Interrupt 0
+ 'PCINT1Addr' : '#16', # Pin Change Interrupt 1
+ 'WDTAddr' : '#18', # Watchdog Timeout Interrupt
+ 'BGSCDAddr' : '#20', # Bandgap Buffer Short Circuit Detected
+ 'CHDETAddr' : '#22', # Charger Detect
+ 'TIMER1_ICAddr' : '#24', # Timer 1 Input capture
+ 'TIMER1_COMPAAddr' : '#26', # Timer 1 Compare Match A
+ 'TIMER1_COMPBAddr' : '#28', # Timer 1 Compare Match B
+ 'TIMER1_OVFAddr' : '#30', # Timer 1 overflow
+ 'TIMER0_ICAddr' : '#32', # Timer 0 Input Capture
+ 'TIMER0_COMPAAddr' : '#34', # Timer 0 Comapre Match A
+ 'TIMER0_COMPBAddr' : '#36', # Timer 0 Compare Match B
+ 'TIMER0_OVFAddr' : '#38', # Timer 0 Overflow
+ 'TWIBUSCDAddr' : '#40', # Two-Wire Bus Connect/Disconnect
+ 'TWIAddr' : '#42', # Two-Wire Serial Interface
+ 'SPI_STCAddr' : '#44', # SPI Serial transfer complete
+ 'VADCAddr' : '#46', # Voltage ADC Conversion Complete
+ 'CCADC_CONVAddr' : '#48', # Coulomb Counter ADC Conversion Complete
+ 'CCADC_REG_CURAddr' : '#50', # Coloumb Counter ADC Regular Current
+ 'CCADC_ACCAddr' : '#52', # Coloumb Counter ADC Accumulator
+ 'EE_READYAddr' : '#54', # EEPROM Ready
+ 'SPMAddr' : '#56', # SPM Ready
+
+# Module AD_CONVERTER
+ 'VADMUX' : '$7c', # The VADC multiplexer Selection
+ 'VADMUX_VADMUX': '$f', # Analog Channel and Gain Select
+ 'VADC' : '$78', # VADC Data Register Bytes
+ 'VADCSR' : '$7a', # The VADC Control and Status re
+ 'VADCSR_VADEN': '$8', # VADC Enable
+ 'VADCSR_VADSC': '$4', # VADC Satrt Conversion
+ 'VADCSR_VADCCIF': '$2', # VADC Conversion Complete Inter
+ 'VADCSR_VADCCIE': '$1', # VADC Conversion Complete Inter
+
+# Module WATCHDOG
+ 'WDTCSR' : '$60', # Watchdog Timer Control Registe
+ 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
+ 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
+ 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
+ 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
+ 'WDTCSR_WDE': '$8', # Watch Dog Enable
+
+# Module FET
+ 'FCSR' : '$f0', # FET Control and Status Registe
+ 'FCSR_DUVRD': '$8', # Deep Under-Voltage Recovery Di
+ 'FCSR_CPS': '$4', # Current Protection Status
+ 'FCSR_DFE': '$2', # Discharge FET Enable
+ 'FCSR_CFE': '$1', # Charge FET Enable
+
+# Module SPI
+ 'SPCR' : '$4c', # SPI Control Register
+ 'SPCR_SPIE': '$80', # SPI Interrupt Enable
+ 'SPCR_SPE': '$40', # SPI Enable
+ 'SPCR_DORD': '$20', # Data Order
+ 'SPCR_MSTR': '$10', # Master/Slave Select
+ 'SPCR_CPOL': '$8', # Clock polarity
+ 'SPCR_CPHA': '$4', # Clock Phase
+ 'SPCR_SPR': '$3', # SPI Clock Rate Selects
+ 'SPSR' : '$4d', # SPI Status Register
+ 'SPSR_SPIF': '$80', # SPI Interrupt Flag
+ 'SPSR_WCOL': '$40', # Write Collision Flag
+ 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
+ 'SPDR' : '$4e', # SPI Data Register
+
+# Module EEPROM
+ 'EEAR' : '$41', # EEPROM Read/Write Access
+ 'EEDR' : '$40', # EEPROM Data Register
+ 'EECR' : '$3f', # EEPROM Control Register
+ 'EECR_EEPM': '$30', #
+ 'EECR_EERIE': '$8', # EEProm Ready Interrupt Enable
+ 'EECR_EEMPE': '$4', # EEPROM Master Write Enable
+ 'EECR_EEPE': '$2', # EEPROM Write Enable
+ 'EECR_EERE': '$1', # EEPROM Read Enable
+
+# Module COULOMB_COUNTER
+ 'CADCSRA' : '$e6', # CC-ADC Control and Status Regi
+ 'CADCSRA_CADEN': '$80', # When the CADEN bit is cleared
+ 'CADCSRA_CADPOL': '$40', #
+ 'CADCSRA_CADUB': '$20', # CC_ADC Update Busy
+ 'CADCSRA_CADAS': '$18', # CC_ADC Accumulate Current Sele
+ 'CADCSRA_CADSI': '$6', # The CADSI bits determine the c
+ 'CADCSRA_CADSE': '$1', # When the CADSE bit is written
+ 'CADCSRB' : '$e7', # CC-ADC Control and Status Regi
+ 'CADCSRB_CADACIE': '$40', #
+ 'CADCSRB_CADRCIE': '$20', # Regular Current Interrupt Enab
+ 'CADCSRB_CADICIE': '$10', # CAD Instantenous Current Inter
+ 'CADCSRB_CADACIF': '$4', # CC-ADC Accumulate Current Inte
+ 'CADCSRB_CADRCIF': '$2', # CC-ADC Accumulate Current Inte
+ 'CADCSRB_CADICIF': '$1', # CC-ADC Instantaneous Current I
+ 'CADCSRC' : '$e8', # CC-ADC Control and Status Regi
+ 'CADCSRC_CADVSE': '$1', # CC-ADC Voltage Scaling Enable
+ 'CADIC' : '$e4', # CC-ADC Instantaneous Current
+ 'CADAC3' : '$e3', # ADC Accumulate Current
+ 'CADAC2' : '$e2', # ADC Accumulate Current
+ 'CADAC1' : '$e1', # ADC Accumulate Current
+ 'CADAC0' : '$e0', # ADC Accumulate Current
+ 'CADRCC' : '$e9', # CC-ADC Regular Charge Current
+ 'CADRDC' : '$ea', # CC-ADC Regular Discharge Curre
+
+# Module TWI
+ 'TWBCSR' : '$be', # TWI Bus Control and Status Reg
+ 'TWBCSR_TWBCIF': '$80', # TWI Bus Connect/Disconnect Int
+ 'TWBCSR_TWBCIE': '$40', # TWI Bus Connect/Disconnect Int
+ 'TWBCSR_TWBDT': '$6', # TWI Bus Disconnect Time-out Pe
+ 'TWBCSR_TWBCIP': '$1', # TWI Bus Connect/Disconnect Int
+ 'TWAMR' : '$bd', # TWI (Slave) Address Mask Regis
+ 'TWAMR_TWAM': '$fe', #
+ 'TWBR' : '$b8', # TWI Bit Rate register
+ 'TWCR' : '$bc', # TWI Control Register
+ 'TWCR_TWINT': '$80', # TWI Interrupt Flag
+ 'TWCR_TWEA': '$40', # TWI Enable Acknowledge Bit
+ 'TWCR_TWSTA': '$20', # TWI Start Condition Bit
+ 'TWCR_TWSTO': '$10', # TWI Stop Condition Bit
+ 'TWCR_TWWC': '$8', # TWI Write Collition Flag
+ 'TWCR_TWEN': '$4', # TWI Enable Bit
+ 'TWCR_TWIE': '$1', # TWI Interrupt Enable
+ 'TWSR' : '$b9', # TWI Status Register
+ 'TWSR_TWS': '$f8', # TWI Status
+ 'TWSR_TWPS': '$3', # TWI Prescaler
+ 'TWDR' : '$bb', # TWI Data register
+ 'TWAR' : '$ba', # TWI (Slave) Address register
+ 'TWAR_TWA': '$fe', # TWI (Slave) Address register B
+ 'TWAR_TWGCE': '$1', # TWI General Call Recognition E
+
+# Module EXTERNAL_INTERRUPT
+ 'EICRA' : '$69', # External Interrupt Control Reg
+ 'EICRA_ISC3': '$c0', # External Interrupt Sense Contr
+ 'EICRA_ISC2': '$30', # External Interrupt Sense Contr
+ 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
+ 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
+ 'EIMSK' : '$3d', # External Interrupt Mask Regist
+ 'EIMSK_INT': '$f', # External Interrupt Request 3 E
+ 'EIFR' : '$3c', # External Interrupt Flag Regist
+ 'EIFR_INTF': '$f', # External Interrupt Flags
+ 'PCICR' : '$68', # Pin Change Interrupt Control R
+ 'PCICR_PCIE': '$3', # Pin Change Interrupt Enables
+ 'PCIFR' : '$3b', # Pin Change Interrupt Flag Regi
+ 'PCIFR_PCIF': '$3', # Pin Change Interrupt Flags
+ 'PCMSK1' : '$6c', # Pin Change Enable Mask Registe
+ 'PCMSK0' : '$6b', # Pin Change Enable Mask Registe
+
+# Module TIMER_COUNTER_1
+ 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
+ 'TCCR1B_CS': '$7', # Clock Select1 bis
+ 'TCCR1A' : '$80', # Timer/Counter 1 Control Regist
+ 'TCCR1A_TCW1': '$80', # Timer/Counter Width
+ 'TCCR1A_ICEN1': '$40', # Input Capture Mode Enable
+ 'TCCR1A_ICNC1': '$20', # Input Capture Noise Canceler
+ 'TCCR1A_ICES1': '$10', # Input Capture Edge Select
+ 'TCCR1A_ICS1': '$8', # Input Capture Select
+ 'TCCR1A_WGM10': '$1', # Waveform Generation Mode
+ 'TCNT1' : '$84', # Timer Counter 1 Bytes
+ 'OCR1A' : '$88', # Output Compare Register 1A
+ 'OCR1B' : '$89', # Output Compare Register B
+ 'TIMSK1' : '$6f', # Timer/Counter Interrupt Mask R
+ 'TIMSK1_ICIE1': '$8', # Timer/Counter n Input Capture
+ 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
+ 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
+ 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
+ 'TIFR1' : '$36', # Timer/Counter Interrupt Flag r
+ 'TIFR1_ICF1': '$8', # Timer/Counter 1 Input Capture
+ 'TIFR1_OCF1B': '$4', # Timer/Counter1 Output Compare
+ 'TIFR1_OCF1A': '$2', # Timer/Counter1 Output Compare
+ 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSRSYNC': '$1', # Prescaler Reset
+
+# Module CELL_BALANCING
+ 'CBCR' : '$f1', # Cell Balancing Control Registe
+ 'CBCR_CBE': '$f', # Cell Balancing Enables
+
+# Module BATTERY_PROTECTION
+ 'BPPLR' : '$fe', # Battery Protection Parameter L
+ 'BPPLR_BPPLE': '$2', # Battery Protection Parameter L
+ 'BPPLR_BPPL': '$1', # Battery Protection Parameter L
+ 'BPCR' : '$fd', # Battery Protection Control Reg
+ 'BPCR_EPID': '$20', # External Protection Input Disa
+ 'BPCR_SCD': '$10', # Short Circuit Protection Disab
+ 'BPCR_DOCD': '$8', # Discharge Over-current Protect
+ 'BPCR_COCD': '$4', # Charge Over-current Protection
+ 'BPCR_DHCD': '$2', # Discharge High-current Protect
+ 'BPCR_CHCD': '$1', # Charge High-current Protection
+ 'BPHCTR' : '$fc', # Battery Protection Short-curre
+ 'BPOCTR' : '$fb', # Battery Protection Over-curren
+ 'BPSCTR' : '$fa', # Battery Protection Short-curre
+ 'BPCHCD' : '$f9', # Battery Protection Charge-High
+ 'BPDHCD' : '$f8', # Battery Protection Discharge-H
+ 'BPCOCD' : '$f7', # Battery Protection Charge-Over
+ 'BPDOCD' : '$f6', # Battery Protection Discharge-O
+ 'BPSCD' : '$f5', # Battery Protection Short-Circu
+ 'BPIFR' : '$f3', # Battery Protection Interrupt F
+ 'BPIFR_SCIF': '$10', # Short-circuit Protection Activ
+ 'BPIFR_DOCIF': '$8', # Discharge Over-current Protect
+ 'BPIFR_COCIF': '$4', # Charge Over-current Protection
+ 'BPIFR_DHCIF': '$2', # Disharge High-current Protecti
+ 'BPIFR_CHCIF': '$1', # Charge High-current Protection
+ 'BPIMSK' : '$f2', # Battery Protection Interrupt M
+ 'BPIMSK_SCIE': '$10', # Short-circuit Protection Activ
+ 'BPIMSK_DOCIE': '$8', # Discharge Over-current Protect
+ 'BPIMSK_COCIE': '$4', # Charge Over-current Protection
+ 'BPIMSK_DHCIE': '$2', # Discharger High-current Protec
+ 'BPIMSK_CHCIE': '$1', # Charger High-current Protectio
+
+# Module CHARGER_DETECT
+ 'CHGDCSR' : '$d4', # Charger Detect Control and Sta
+ 'CHGDCSR_BATTPVL': '$10', # BATT Pin Voltage Level
+ 'CHGDCSR_CHGDISC': '$c', # Charger Detect Interrupt Sense
+ 'CHGDCSR_CHGDIF': '$2', # Charger Detect Interrupt Flag
+ 'CHGDCSR_CHGDIE': '$1', # Charger Detect Interrupt Enabl
+
+# Module VOLTAGE_REGULATOR
+ 'ROCR' : '$c8', # Regulator Operating Condition
+ 'ROCR_ROCS': '$80', # ROC Status
+ 'ROCR_ROCD': '$10', # ROC Disable
+ 'ROCR_ROCWIF': '$2', # ROC Warning Interrupt Flag
+ 'ROCR_ROCWIE': '$1', # ROC Warning Interrupt Enable
+
+# Module BANDGAP
+ 'BGCSR' : '$d2', # Bandgap Control and Status Reg
+ 'BGCSR_BGD': '$20', # Bandgap Disable
+ 'BGCSR_BGSCDE': '$10', # Bandgap Short Circuit Detectio
+ 'BGCSR_BGSCDIF': '$2', # Bandgap Short Circuit Detectio
+ 'BGCSR_BGSCDIE': '$1', # Bandgap Short Circuit Detectio
+ 'BGCRR' : '$d1', # Bandgap Calibration of Resisto
+ 'BGCCR' : '$d0', # Bandgap Calibration Register
+ 'BGCCR_BGCC': '$3f', # BG Calibration of PTAT Current
+
+# Module CPU
+ 'SREG' : '$5f', # Status Register
+ 'SREG_I': '$80', # Global Interrupt Enable
+ 'SREG_T': '$40', # Bit Copy Storage
+ 'SREG_H': '$20', # Half Carry Flag
+ 'SREG_S': '$10', # Sign Bit
+ 'SREG_V': '$8', # Two's Complement Overflow Flag
+ 'SREG_N': '$4', # Negative Flag
+ 'SREG_Z': '$2', # Zero Flag
+ 'SREG_C': '$1', # Carry Flag
+ 'SP' : '$5d', # Stack Pointer
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_CKOE': '$20', # Clock Output Enable
+ 'MCUCR_PUD': '$10', # Pull-up disable
+ 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
+ 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_OCDRF': '$10', # OCD Reset Flag
+ 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
+ 'MCUSR_BODRF': '$4', # Brown-out Reset Flag
+ 'MCUSR_EXTRF': '$2', # External Reset Flag
+ 'MCUSR_PORF': '$1', # Power-on reset flag
+ 'FOSCCAL' : '$66', # Fast Oscillator Calibration Va
+ 'OSICSR' : '$37', # Oscillator Sampling Interface
+ 'OSICSR_OSISEL0': '$10', # Oscillator Sampling Interface
+ 'OSICSR_OSIST': '$2', # Oscillator Sampling Interface
+ 'OSICSR_OSIEN': '$1', # Oscillator Sampling Interface
+ 'SMCR' : '$53', # Sleep Mode Control Register
+ 'SMCR_SM': '$e', # Sleep Mode Select bits
+ 'SMCR_SE': '$1', # Sleep Enable
+ 'GPIOR2' : '$4b', # General Purpose IO Register 2
+ 'GPIOR1' : '$4a', # General Purpose IO Register 1
+ 'GPIOR0' : '$3e', # General Purpose IO Register 0
+ 'DIDR0' : '$7e', # Digital Input Disable Register
+ 'DIDR0_PA1DID': '$2', # When this bit is written logic
+ 'DIDR0_PA0DID': '$1', # When this bit is written logic
+ 'PRR0' : '$64', # Power Reduction Register 0
+ 'PRR0_PRTWI': '$40', # Power Reduction TWI
+ 'PRR0_PRVRM': '$20', # Power Reduction Voltage Regula
+ 'PRR0_PRSPI': '$8', # Power reduction SPI
+ 'PRR0_PRTIM1': '$4', # Power Reduction Timer/Counter1
+ 'PRR0_PRTIM0': '$2', # Power Reduction Timer/Counter0
+ 'PRR0_PRVADC': '$1', # Power Reduction V-ADC
+ 'CLKPR' : '$61', # Clock Prescale Register
+ 'CLKPR_CLKPCE': '$80', # Clock Prescaler Change Enable
+ 'CLKPR_CLKPS': '$3', # Clock Prescaler Select Bits
+
+# Module PORTA
+ 'PORTA' : '$22', # Port A Data Register
+ 'DDRA' : '$21', # Port A Data Direction Register
+ 'PINA' : '$20', # Port A Input Pins
+
+# Module PORTB
+ 'PORTB' : '$25', # Port B Data Register
+ 'DDRB' : '$24', # Port B Data Direction Register
+ 'PINB' : '$23', # Port B Input Pins
+
+# Module PORTC
+ 'PORTC' : '$28', # Port C Data Register
+ 'PINC' : '$26', # Port C Input Pins
+
+# Module TIMER_COUNTER_0
+ 'TCCR0B' : '$45', # Timer/Counter0 Control Registe
+ 'TCCR0B_CS02': '$4', # Clock Select0 bit 2
+ 'TCCR0B_CS01': '$2', # Clock Select0 bit 1
+ 'TCCR0B_CS00': '$1', # Clock Select0 bit 0
+ 'TCCR0A' : '$44', # Timer/Counter 0 Control Regist
+ 'TCCR0A_TCW0': '$80', # Timer/Counter Width
+ 'TCCR0A_ICEN0': '$40', # Input Capture Mode Enable
+ 'TCCR0A_ICNC0': '$20', # Input Capture Noise Canceler
+ 'TCCR0A_ICES0': '$10', # Input Capture Edge Select
+ 'TCCR0A_ICS0': '$8', # Input Capture Select
+ 'TCCR0A_WGM00': '$1', # Waveform Generation Mode
+ 'TCNT0' : '$46', # Timer Counter 0 Bytes
+ 'OCR0A' : '$48', # Output Compare Register 0A
+ 'OCR0B' : '$49', # Output Compare Register B
+ 'TIMSK0' : '$6e', # Timer/Counter Interrupt Mask R
+ 'TIMSK0_ICIE0': '$8', # Timer/Counter n Input Capture
+ 'TIMSK0_OCIE0B': '$4', # Timer/Counter0 Output Compare
+ 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
+ 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
+ 'TIFR0' : '$35', # Timer/Counter Interrupt Flag r
+ 'TIFR0_ICF0': '$8', # Timer/Counter 0 Input Capture
+ 'TIFR0_OCF0B': '$4', # Timer/Counter0 Output Compare
+ 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
+ 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSRSYNC': '$1', # Prescaler Reset
+
+# Module BOOT_LOAD
+ 'SPMCSR' : '$57', # Store Program Memory Control a
+ 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
+ 'SPMCSR_RWWSB': '$40', # Read-While-Write Section Busy
+ 'SPMCSR_SIGRD': '$20', # Signature Row Read
+ 'SPMCSR_RWWSRE': '$10', # Read-While-Write Section Read
+ 'SPMCSR_LBSET': '$8', # Lock Bit Set
+ 'SPMCSR_PGWRT': '$4', # Page Write
+ 'SPMCSR_PGERS': '$2', # Page Erase
+ 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
+
+ '__amforth_dummy':'0'
+}
diff --git a/amforth-6.5/avr8/devices/atmega32hvb/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega32hvb/words/no-jtag.asm
new file mode 100644
index 0000000..352a4bb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega32hvb/words/no-jtag.asm
@@ -0,0 +1,14 @@
+; ( -- )
+; ( -- )
+; MCU
+; disable jtag at runtime
+VE_NOJTAG:
+ .dw $FF05
+ .db "-jtag",0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOJTAG
+XT_NOJTAG:
+ .dw PFA_NOJTAG
+PFA_NOJTAG:
+
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega32hvb/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega32hvb/words/no-wdt.asm
new file mode 100644
index 0000000..4a12261
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega32hvb/words/no-wdt.asm
@@ -0,0 +1,22 @@
+; ( -- )
+; MCU
+; disable watch dog timer at runtime
+VE_NOWDT:
+ .dw $ff04
+ .db "-wdt"
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOWDT
+XT_NOWDT:
+ .dw PFA_NOWDT
+PFA_NOWDT:
+
+; Reset WDT
+ wdr
+; Write logical one to WDTOE and WDE
+ in_ temp1, WDTCR
+ ori temp1, (1<<WDTOE)|(1<<WDE)
+ out WDTCR, temp1
+; Turn off WDT
+ ldi temp1, (0<<WDE)
+ out_ WDTCR, temp1
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega32hvb/words/sleep.asm b/amforth-6.5/avr8/devices/atmega32hvb/words/sleep.asm
new file mode 100644
index 0000000..778fa32
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega32hvb/words/sleep.asm
@@ -0,0 +1,24 @@
+; ( mode -- )
+; MCU
+; put the controller into the specified sleep mode
+VE_SLEEP:
+ .dw $ff05
+ .db "sleep", 0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_SLEEP
+XT_SLEEP:
+ .dw PFA_SLEEP
+PFA_SLEEP:
+ andi tosl, 7 ; leave only legal mode bits
+ swap tosl ; move to correct location (bits 6-4, atmega32)
+ ori tosl, $80 ; set the SE bit (atmega32: bit 7, not bit 0)
+ out_ MCUCR, tosl ; set the sleep config (atmega32: MCUCR not SMCR)
+ sleep ; nighty-night
+;; the 4 lower bits of MCUCR should not be touched
+ in_ tosl, MCUCR
+ andi tosl, $0F
+ out_ MCUCR, tosl
+ ;clr tosl ; need to clean up the SMCR reg before we leave
+ ;out SMCR, tosl ; 0 protects against accidental sleeps
+ loadtos ; pop argument from stack
+ jmp DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega32hvbrevb/atmega32hvbrevb.frt b/amforth-6.5/avr8/devices/atmega32hvbrevb/atmega32hvbrevb.frt
new file mode 100644
index 0000000..ebba295
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega32hvbrevb/atmega32hvbrevb.frt
@@ -0,0 +1,33 @@
+\ Partname: ATmega32HVBrevB
+\ generated automatically
+
+
+\ Interrupts
+&2 constant BPINTAddr \ Battery Protection Interrupt
+&4 constant VREGMONAddr \ Voltage regulator monitor interrupt
+&6 constant INT0Addr \ External Interrupt Request 0
+&8 constant INT1Addr \ External Interrupt Request 1
+&10 constant INT2Addr \ External Interrupt Request 2
+&12 constant INT3Addr \ External Interrupt Request 3
+&14 constant PCINT0Addr \ Pin Change Interrupt 0
+&16 constant PCINT1Addr \ Pin Change Interrupt 1
+&18 constant WDTAddr \ Watchdog Timeout Interrupt
+&20 constant BGSCDAddr \ Bandgap Buffer Short Circuit Detected
+&22 constant CHDETAddr \ Charger Detect
+&24 constant TIMER1_ICAddr \ Timer 1 Input capture
+&26 constant TIMER1_COMPAAddr \ Timer 1 Compare Match A
+&28 constant TIMER1_COMPBAddr \ Timer 1 Compare Match B
+&30 constant TIMER1_OVFAddr \ Timer 1 overflow
+&32 constant TIMER0_ICAddr \ Timer 0 Input Capture
+&34 constant TIMER0_COMPAAddr \ Timer 0 Comapre Match A
+&36 constant TIMER0_COMPBAddr \ Timer 0 Compare Match B
+&38 constant TIMER0_OVFAddr \ Timer 0 Overflow
+&40 constant TWIBUSCDAddr \ Two-Wire Bus Connect/Disconnect
+&42 constant TWIAddr \ Two-Wire Serial Interface
+&44 constant SPI_STCAddr \ SPI Serial transfer complete
+&46 constant VADCAddr \ Voltage ADC Conversion Complete
+&48 constant CCADC_CONVAddr \ Coulomb Counter ADC Conversion Complete
+&50 constant CCADC_REG_CURAddr \ Coloumb Counter ADC Regular Current
+&52 constant CCADC_ACCAddr \ Coloumb Counter ADC Accumulator
+&54 constant EE_READYAddr \ EEPROM Ready
+&56 constant SPMAddr \ SPM Ready
diff --git a/amforth-6.5/avr8/devices/atmega32hvbrevb/device.asm b/amforth-6.5/avr8/devices/atmega32hvbrevb/device.asm
new file mode 100644
index 0000000..ebf0278
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega32hvbrevb/device.asm
@@ -0,0 +1,101 @@
+; Partname: ATmega32HVBrevB
+; generated automatically, do not edit
+
+.nolist
+ .include "m32HVBrevBdef.inc"
+.list
+
+.equ ramstart = 256
+.equ CELLSIZE = 2
+.macro readflashcell
+ lsl zl
+ rol zh
+ lpm @0, Z+
+ lpm @1, Z+
+.endmacro
+.macro writeflashcell
+ lsl zl
+ rol zh
+.endmacro
+.equ intvecsize = 2 ; please verify; flash size: 32768 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.org 2
+ rcall isr ; Battery Protection Interrupt
+.org 4
+ rcall isr ; Voltage regulator monitor interrupt
+.org 6
+ rcall isr ; External Interrupt Request 0
+.org 8
+ rcall isr ; External Interrupt Request 1
+.org 10
+ rcall isr ; External Interrupt Request 2
+.org 12
+ rcall isr ; External Interrupt Request 3
+.org 14
+ rcall isr ; Pin Change Interrupt 0
+.org 16
+ rcall isr ; Pin Change Interrupt 1
+.org 18
+ rcall isr ; Watchdog Timeout Interrupt
+.org 20
+ rcall isr ; Bandgap Buffer Short Circuit Detected
+.org 22
+ rcall isr ; Charger Detect
+.org 24
+ rcall isr ; Timer 1 Input capture
+.org 26
+ rcall isr ; Timer 1 Compare Match A
+.org 28
+ rcall isr ; Timer 1 Compare Match B
+.org 30
+ rcall isr ; Timer 1 overflow
+.org 32
+ rcall isr ; Timer 0 Input Capture
+.org 34
+ rcall isr ; Timer 0 Comapre Match A
+.org 36
+ rcall isr ; Timer 0 Compare Match B
+.org 38
+ rcall isr ; Timer 0 Overflow
+.org 40
+ rcall isr ; Two-Wire Bus Connect/Disconnect
+.org 42
+ rcall isr ; Two-Wire Serial Interface
+.org 44
+ rcall isr ; SPI Serial transfer complete
+.org 46
+ rcall isr ; Voltage ADC Conversion Complete
+.org 48
+ rcall isr ; Coulomb Counter ADC Conversion Complete
+.org 50
+ rcall isr ; Coloumb Counter ADC Regular Current
+.org 52
+ rcall isr ; Coloumb Counter ADC Accumulator
+.org 54
+ rcall isr ; EEPROM Ready
+.org 56
+ rcall isr ; SPM Ready
+.equ INTVECTORS = 29
+.nooverlap
+
+; compatability layer (maybe empty)
+.equ SPMEN = SELFPRGEN
+.equ SPMCSR = SPMCR
+.equ EEPE = EEWE
+.equ EEMPE = EEMWE
+
+; controller data area, environment query mcu-info
+mcu_info:
+mcu_ramsize:
+ .dw 2048
+mcu_eepromsize:
+ .dw 1024
+mcu_maxdp:
+ .dw 28672
+mcu_numints:
+ .dw 29
+mcu_name:
+ .dw 15
+ .db "ATmega32HVBrevB",0
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega32hvbrevb/device.inc b/amforth-6.5/avr8/devices/atmega32hvbrevb/device.inc
new file mode 100644
index 0000000..ce47e87
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega32hvbrevb/device.inc
@@ -0,0 +1,3 @@
+; Partname: ATmega32HVBrevB
+; generated automatically, no not edit
+
diff --git a/amforth-6.5/avr8/devices/atmega32hvbrevb/device.py b/amforth-6.5/avr8/devices/atmega32hvbrevb/device.py
new file mode 100644
index 0000000..f50682a
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega32hvbrevb/device.py
@@ -0,0 +1,342 @@
+# Generated Automatically
+
+# Partname ATmega32HVBrevB
+
+MCUREGS = {
+# Interrupt Vectors
+ 'BPINTAddr' : '#2', # Battery Protection Interrupt
+ 'VREGMONAddr' : '#4', # Voltage regulator monitor interrupt
+ 'INT0Addr' : '#6', # External Interrupt Request 0
+ 'INT1Addr' : '#8', # External Interrupt Request 1
+ 'INT2Addr' : '#10', # External Interrupt Request 2
+ 'INT3Addr' : '#12', # External Interrupt Request 3
+ 'PCINT0Addr' : '#14', # Pin Change Interrupt 0
+ 'PCINT1Addr' : '#16', # Pin Change Interrupt 1
+ 'WDTAddr' : '#18', # Watchdog Timeout Interrupt
+ 'BGSCDAddr' : '#20', # Bandgap Buffer Short Circuit Detected
+ 'CHDETAddr' : '#22', # Charger Detect
+ 'TIMER1_ICAddr' : '#24', # Timer 1 Input capture
+ 'TIMER1_COMPAAddr' : '#26', # Timer 1 Compare Match A
+ 'TIMER1_COMPBAddr' : '#28', # Timer 1 Compare Match B
+ 'TIMER1_OVFAddr' : '#30', # Timer 1 overflow
+ 'TIMER0_ICAddr' : '#32', # Timer 0 Input Capture
+ 'TIMER0_COMPAAddr' : '#34', # Timer 0 Comapre Match A
+ 'TIMER0_COMPBAddr' : '#36', # Timer 0 Compare Match B
+ 'TIMER0_OVFAddr' : '#38', # Timer 0 Overflow
+ 'TWIBUSCDAddr' : '#40', # Two-Wire Bus Connect/Disconnect
+ 'TWIAddr' : '#42', # Two-Wire Serial Interface
+ 'SPI_STCAddr' : '#44', # SPI Serial transfer complete
+ 'VADCAddr' : '#46', # Voltage ADC Conversion Complete
+ 'CCADC_CONVAddr' : '#48', # Coulomb Counter ADC Conversion Complete
+ 'CCADC_REG_CURAddr' : '#50', # Coloumb Counter ADC Regular Current
+ 'CCADC_ACCAddr' : '#52', # Coloumb Counter ADC Accumulator
+ 'EE_READYAddr' : '#54', # EEPROM Ready
+ 'SPMAddr' : '#56', # SPM Ready
+
+# Module AD_CONVERTER
+ 'VADMUX' : '$7c', # The VADC multiplexer Selection
+ 'VADMUX_VADMUX': '$f', # Analog Channel and Gain Select
+ 'VADC' : '$78', # VADC Data Register Bytes
+ 'VADCSR' : '$7a', # The VADC Control and Status re
+ 'VADCSR_VADEN': '$8', # VADC Enable
+ 'VADCSR_VADSC': '$4', # VADC Satrt Conversion
+ 'VADCSR_VADCCIF': '$2', # VADC Conversion Complete Inter
+ 'VADCSR_VADCCIE': '$1', # VADC Conversion Complete Inter
+
+# Module WATCHDOG
+ 'WDTCSR' : '$60', # Watchdog Timer Control Registe
+ 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
+ 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
+ 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
+ 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
+ 'WDTCSR_WDE': '$8', # Watch Dog Enable
+
+# Module FET
+ 'FCSR' : '$f0', # FET Control and Status Registe
+ 'FCSR_DUVRD': '$8', # Deep Under-Voltage Recovery Di
+ 'FCSR_CPS': '$4', # Current Protection Status
+ 'FCSR_DFE': '$2', # Discharge FET Enable
+ 'FCSR_CFE': '$1', # Charge FET Enable
+
+# Module SPI
+ 'SPCR' : '$4c', # SPI Control Register
+ 'SPCR_SPIE': '$80', # SPI Interrupt Enable
+ 'SPCR_SPE': '$40', # SPI Enable
+ 'SPCR_DORD': '$20', # Data Order
+ 'SPCR_MSTR': '$10', # Master/Slave Select
+ 'SPCR_CPOL': '$8', # Clock polarity
+ 'SPCR_CPHA': '$4', # Clock Phase
+ 'SPCR_SPR': '$3', # SPI Clock Rate Selects
+ 'SPSR' : '$4d', # SPI Status Register
+ 'SPSR_SPIF': '$80', # SPI Interrupt Flag
+ 'SPSR_WCOL': '$40', # Write Collision Flag
+ 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
+ 'SPDR' : '$4e', # SPI Data Register
+
+# Module EEPROM
+ 'EEAR' : '$41', # EEPROM Read/Write Access
+ 'EEDR' : '$40', # EEPROM Data Register
+ 'EECR' : '$3f', # EEPROM Control Register
+ 'EECR_EEPM': '$30', #
+ 'EECR_EERIE': '$8', # EEProm Ready Interrupt Enable
+ 'EECR_EEMPE': '$4', # EEPROM Master Write Enable
+ 'EECR_EEPE': '$2', # EEPROM Write Enable
+ 'EECR_EERE': '$1', # EEPROM Read Enable
+
+# Module COULOMB_COUNTER
+ 'CADCSRA' : '$e6', # CC-ADC Control and Status Regi
+ 'CADCSRA_CADEN': '$80', # When the CADEN bit is cleared
+ 'CADCSRA_CADPOL': '$40', #
+ 'CADCSRA_CADUB': '$20', # CC_ADC Update Busy
+ 'CADCSRA_CADAS': '$18', # CC_ADC Accumulate Current Sele
+ 'CADCSRA_CADSI': '$6', # The CADSI bits determine the c
+ 'CADCSRA_CADSE': '$1', # When the CADSE bit is written
+ 'CADCSRB' : '$e7', # CC-ADC Control and Status Regi
+ 'CADCSRB_CADACIE': '$40', #
+ 'CADCSRB_CADRCIE': '$20', # Regular Current Interrupt Enab
+ 'CADCSRB_CADICIE': '$10', # CAD Instantenous Current Inter
+ 'CADCSRB_CADACIF': '$4', # CC-ADC Accumulate Current Inte
+ 'CADCSRB_CADRCIF': '$2', # CC-ADC Accumulate Current Inte
+ 'CADCSRB_CADICIF': '$1', # CC-ADC Instantaneous Current I
+ 'CADCSRC' : '$e8', # CC-ADC Control and Status Regi
+ 'CADCSRC_CADVSE': '$1', # CC-ADC Voltage Scaling Enable
+ 'CADIC' : '$e4', # CC-ADC Instantaneous Current
+ 'CADAC3' : '$e3', # ADC Accumulate Current
+ 'CADAC2' : '$e2', # ADC Accumulate Current
+ 'CADAC1' : '$e1', # ADC Accumulate Current
+ 'CADAC0' : '$e0', # ADC Accumulate Current
+ 'CADRCC' : '$e9', # CC-ADC Regular Charge Current
+ 'CADRDC' : '$ea', # CC-ADC Regular Discharge Curre
+
+# Module TWI
+ 'TWBCSR' : '$be', # TWI Bus Control and Status Reg
+ 'TWBCSR_TWBCIF': '$80', # TWI Bus Connect/Disconnect Int
+ 'TWBCSR_TWBCIE': '$40', # TWI Bus Connect/Disconnect Int
+ 'TWBCSR_TWBDT': '$6', # TWI Bus Disconnect Time-out Pe
+ 'TWBCSR_TWBCIP': '$1', # TWI Bus Connect/Disconnect Int
+ 'TWAMR' : '$bd', # TWI (Slave) Address Mask Regis
+ 'TWAMR_TWAM': '$fe', #
+ 'TWBR' : '$b8', # TWI Bit Rate register
+ 'TWCR' : '$bc', # TWI Control Register
+ 'TWCR_TWINT': '$80', # TWI Interrupt Flag
+ 'TWCR_TWEA': '$40', # TWI Enable Acknowledge Bit
+ 'TWCR_TWSTA': '$20', # TWI Start Condition Bit
+ 'TWCR_TWSTO': '$10', # TWI Stop Condition Bit
+ 'TWCR_TWWC': '$8', # TWI Write Collition Flag
+ 'TWCR_TWEN': '$4', # TWI Enable Bit
+ 'TWCR_TWIE': '$1', # TWI Interrupt Enable
+ 'TWSR' : '$b9', # TWI Status Register
+ 'TWSR_TWS': '$f8', # TWI Status
+ 'TWSR_TWPS': '$3', # TWI Prescaler
+ 'TWDR' : '$bb', # TWI Data register
+ 'TWAR' : '$ba', # TWI (Slave) Address register
+ 'TWAR_TWA': '$fe', # TWI (Slave) Address register B
+ 'TWAR_TWGCE': '$1', # TWI General Call Recognition E
+
+# Module EXTERNAL_INTERRUPT
+ 'EICRA' : '$69', # External Interrupt Control Reg
+ 'EICRA_ISC3': '$c0', # External Interrupt Sense Contr
+ 'EICRA_ISC2': '$30', # External Interrupt Sense Contr
+ 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
+ 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
+ 'EIMSK' : '$3d', # External Interrupt Mask Regist
+ 'EIMSK_INT': '$f', # External Interrupt Request 3 E
+ 'EIFR' : '$3c', # External Interrupt Flag Regist
+ 'EIFR_INTF': '$f', # External Interrupt Flags
+ 'PCICR' : '$68', # Pin Change Interrupt Control R
+ 'PCICR_PCIE': '$3', # Pin Change Interrupt Enables
+ 'PCIFR' : '$3b', # Pin Change Interrupt Flag Regi
+ 'PCIFR_PCIF': '$3', # Pin Change Interrupt Flags
+ 'PCMSK1' : '$6c', # Pin Change Enable Mask Registe
+ 'PCMSK0' : '$6b', # Pin Change Enable Mask Registe
+
+# Module TIMER_COUNTER_1
+ 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
+ 'TCCR1B_CS': '$7', # Clock Select1 bis
+ 'TCCR1A' : '$80', # Timer/Counter 1 Control Regist
+ 'TCCR1A_TCW1': '$80', # Timer/Counter Width
+ 'TCCR1A_ICEN1': '$40', # Input Capture Mode Enable
+ 'TCCR1A_ICNC1': '$20', # Input Capture Noise Canceler
+ 'TCCR1A_ICES1': '$10', # Input Capture Edge Select
+ 'TCCR1A_ICS1': '$8', # Input Capture Select
+ 'TCCR1A_WGM10': '$1', # Waveform Generation Mode
+ 'TCNT1' : '$84', # Timer Counter 1 Bytes
+ 'OCR1A' : '$88', # Output Compare Register 1A
+ 'OCR1B' : '$89', # Output Compare Register B
+ 'TIMSK1' : '$6f', # Timer/Counter Interrupt Mask R
+ 'TIMSK1_ICIE1': '$8', # Timer/Counter n Input Capture
+ 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
+ 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
+ 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
+ 'TIFR1' : '$36', # Timer/Counter Interrupt Flag r
+ 'TIFR1_ICF1': '$8', # Timer/Counter 1 Input Capture
+ 'TIFR1_OCF1B': '$4', # Timer/Counter1 Output Compare
+ 'TIFR1_OCF1A': '$2', # Timer/Counter1 Output Compare
+ 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSRSYNC': '$1', # Prescaler Reset
+
+# Module CELL_BALANCING
+ 'CBCR' : '$f1', # Cell Balancing Control Registe
+ 'CBCR_CBE': '$f', # Cell Balancing Enables
+
+# Module BATTERY_PROTECTION
+ 'BPPLR' : '$fe', # Battery Protection Parameter L
+ 'BPPLR_BPPLE': '$2', # Battery Protection Parameter L
+ 'BPPLR_BPPL': '$1', # Battery Protection Parameter L
+ 'BPCR' : '$fd', # Battery Protection Control Reg
+ 'BPCR_EPID': '$20', # External Protection Input Disa
+ 'BPCR_SCD': '$10', # Short Circuit Protection Disab
+ 'BPCR_DOCD': '$8', # Discharge Over-current Protect
+ 'BPCR_COCD': '$4', # Charge Over-current Protection
+ 'BPCR_DHCD': '$2', # Discharge High-current Protect
+ 'BPCR_CHCD': '$1', # Charge High-current Protection
+ 'BPHCTR' : '$fc', # Battery Protection Short-curre
+ 'BPOCTR' : '$fb', # Battery Protection Over-curren
+ 'BPSCTR' : '$fa', # Battery Protection Short-curre
+ 'BPCHCD' : '$f9', # Battery Protection Charge-High
+ 'BPDHCD' : '$f8', # Battery Protection Discharge-H
+ 'BPCOCD' : '$f7', # Battery Protection Charge-Over
+ 'BPDOCD' : '$f6', # Battery Protection Discharge-O
+ 'BPSCD' : '$f5', # Battery Protection Short-Circu
+ 'BPIFR' : '$f3', # Battery Protection Interrupt F
+ 'BPIFR_SCIF': '$10', # Short-circuit Protection Activ
+ 'BPIFR_DOCIF': '$8', # Discharge Over-current Protect
+ 'BPIFR_COCIF': '$4', # Charge Over-current Protection
+ 'BPIFR_DHCIF': '$2', # Disharge High-current Protecti
+ 'BPIFR_CHCIF': '$1', # Charge High-current Protection
+ 'BPIMSK' : '$f2', # Battery Protection Interrupt M
+ 'BPIMSK_SCIE': '$10', # Short-circuit Protection Activ
+ 'BPIMSK_DOCIE': '$8', # Discharge Over-current Protect
+ 'BPIMSK_COCIE': '$4', # Charge Over-current Protection
+ 'BPIMSK_DHCIE': '$2', # Discharger High-current Protec
+ 'BPIMSK_CHCIE': '$1', # Charger High-current Protectio
+
+# Module CHARGER_DETECT
+ 'CHGDCSR' : '$d4', # Charger Detect Control and Sta
+ 'CHGDCSR_BATTPVL': '$10', # BATT Pin Voltage Level
+ 'CHGDCSR_CHGDISC': '$c', # Charger Detect Interrupt Sense
+ 'CHGDCSR_CHGDIF': '$2', # Charger Detect Interrupt Flag
+ 'CHGDCSR_CHGDIE': '$1', # Charger Detect Interrupt Enabl
+
+# Module VOLTAGE_REGULATOR
+ 'ROCR' : '$c8', # Regulator Operating Condition
+ 'ROCR_ROCS': '$80', # ROC Status
+ 'ROCR_ROCD': '$10', # ROC Disable
+ 'ROCR_ROCWIF': '$2', # ROC Warning Interrupt Flag
+ 'ROCR_ROCWIE': '$1', # ROC Warning Interrupt Enable
+
+# Module BANDGAP
+ 'BGCSR' : '$d2', # Bandgap Control and Status Reg
+ 'BGCSR_BGD': '$20', # Bandgap Disable
+ 'BGCSR_BGSCDE': '$10', # Bandgap Short Circuit Detectio
+ 'BGCSR_BGSCDIF': '$2', # Bandgap Short Circuit Detectio
+ 'BGCSR_BGSCDIE': '$1', # Bandgap Short Circuit Detectio
+ 'BGCRR' : '$d1', # Bandgap Calibration of Resisto
+ 'BGCCR' : '$d0', # Bandgap Calibration Register
+ 'BGCCR_BGCC': '$3f', # BG Calibration of PTAT Current
+
+# Module CPU
+ 'SREG' : '$5f', # Status Register
+ 'SREG_I': '$80', # Global Interrupt Enable
+ 'SREG_T': '$40', # Bit Copy Storage
+ 'SREG_H': '$20', # Half Carry Flag
+ 'SREG_S': '$10', # Sign Bit
+ 'SREG_V': '$8', # Two's Complement Overflow Flag
+ 'SREG_N': '$4', # Negative Flag
+ 'SREG_Z': '$2', # Zero Flag
+ 'SREG_C': '$1', # Carry Flag
+ 'SP' : '$5d', # Stack Pointer
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_CKOE': '$20', # Clock Output Enable
+ 'MCUCR_PUD': '$10', # Pull-up disable
+ 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
+ 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_OCDRF': '$10', # OCD Reset Flag
+ 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
+ 'MCUSR_BODRF': '$4', # Brown-out Reset Flag
+ 'MCUSR_EXTRF': '$2', # External Reset Flag
+ 'MCUSR_PORF': '$1', # Power-on reset flag
+ 'FOSCCAL' : '$66', # Fast Oscillator Calibration Va
+ 'OSICSR' : '$37', # Oscillator Sampling Interface
+ 'OSICSR_OSISEL0': '$10', # Oscillator Sampling Interface
+ 'OSICSR_OSIST': '$2', # Oscillator Sampling Interface
+ 'OSICSR_OSIEN': '$1', # Oscillator Sampling Interface
+ 'SMCR' : '$53', # Sleep Mode Control Register
+ 'SMCR_SM': '$e', # Sleep Mode Select bits
+ 'SMCR_SE': '$1', # Sleep Enable
+ 'GPIOR2' : '$4b', # General Purpose IO Register 2
+ 'GPIOR1' : '$4a', # General Purpose IO Register 1
+ 'GPIOR0' : '$3e', # General Purpose IO Register 0
+ 'DIDR0' : '$7e', # Digital Input Disable Register
+ 'DIDR0_PA1DID': '$2', # When this bit is written logic
+ 'DIDR0_PA0DID': '$1', # When this bit is written logic
+ 'PRR0' : '$64', # Power Reduction Register 0
+ 'PRR0_PRTWI': '$40', # Power Reduction TWI
+ 'PRR0_PRVRM': '$20', # Power Reduction Voltage Regula
+ 'PRR0_PRSPI': '$8', # Power reduction SPI
+ 'PRR0_PRTIM1': '$4', # Power Reduction Timer/Counter1
+ 'PRR0_PRTIM0': '$2', # Power Reduction Timer/Counter0
+ 'PRR0_PRVADC': '$1', # Power Reduction V-ADC
+ 'CLKPR' : '$61', # Clock Prescale Register
+ 'CLKPR_CLKPCE': '$80', # Clock Prescaler Change Enable
+ 'CLKPR_CLKPS': '$3', # Clock Prescaler Select Bits
+
+# Module PORTA
+ 'PORTA' : '$22', # Port A Data Register
+ 'DDRA' : '$21', # Port A Data Direction Register
+ 'PINA' : '$20', # Port A Input Pins
+
+# Module PORTB
+ 'PORTB' : '$25', # Port B Data Register
+ 'DDRB' : '$24', # Port B Data Direction Register
+ 'PINB' : '$23', # Port B Input Pins
+
+# Module PORTC
+ 'PORTC' : '$28', # Port C Data Register
+ 'PINC' : '$26', # Port C Input Pins
+
+# Module TIMER_COUNTER_0
+ 'TCCR0B' : '$45', # Timer/Counter0 Control Registe
+ 'TCCR0B_CS02': '$4', # Clock Select0 bit 2
+ 'TCCR0B_CS01': '$2', # Clock Select0 bit 1
+ 'TCCR0B_CS00': '$1', # Clock Select0 bit 0
+ 'TCCR0A' : '$44', # Timer/Counter 0 Control Regist
+ 'TCCR0A_TCW0': '$80', # Timer/Counter Width
+ 'TCCR0A_ICEN0': '$40', # Input Capture Mode Enable
+ 'TCCR0A_ICNC0': '$20', # Input Capture Noise Canceler
+ 'TCCR0A_ICES0': '$10', # Input Capture Edge Select
+ 'TCCR0A_ICS0': '$8', # Input Capture Select
+ 'TCCR0A_WGM00': '$1', # Waveform Generation Mode
+ 'TCNT0' : '$46', # Timer Counter 0 Bytes
+ 'OCR0A' : '$48', # Output Compare Register 0A
+ 'OCR0B' : '$49', # Output Compare Register B
+ 'TIMSK0' : '$6e', # Timer/Counter Interrupt Mask R
+ 'TIMSK0_ICIE0': '$8', # Timer/Counter n Input Capture
+ 'TIMSK0_OCIE0B': '$4', # Timer/Counter0 Output Compare
+ 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
+ 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
+ 'TIFR0' : '$35', # Timer/Counter Interrupt Flag r
+ 'TIFR0_ICF0': '$8', # Timer/Counter 0 Input Capture
+ 'TIFR0_OCF0B': '$4', # Timer/Counter0 Output Compare
+ 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
+ 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSRSYNC': '$1', # Prescaler Reset
+
+# Module BOOT_LOAD
+ 'SPMCSR' : '$57', # Store Program Memory Control a
+ 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
+ 'SPMCSR_RWWSB': '$40', # Read-While-Write Section Busy
+ 'SPMCSR_SIGRD': '$20', # Signature Row Read
+ 'SPMCSR_RWWSRE': '$10', # Read-While-Write Section Read
+ 'SPMCSR_LBSET': '$8', # Lock Bit Set
+ 'SPMCSR_PGWRT': '$4', # Page Write
+ 'SPMCSR_PGERS': '$2', # Page Erase
+ 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
+
+ '__amforth_dummy':'0'
+}
diff --git a/amforth-6.5/avr8/devices/atmega32hvbrevb/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega32hvbrevb/words/no-jtag.asm
new file mode 100644
index 0000000..352a4bb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega32hvbrevb/words/no-jtag.asm
@@ -0,0 +1,14 @@
+; ( -- )
+; ( -- )
+; MCU
+; disable jtag at runtime
+VE_NOJTAG:
+ .dw $FF05
+ .db "-jtag",0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOJTAG
+XT_NOJTAG:
+ .dw PFA_NOJTAG
+PFA_NOJTAG:
+
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega32hvbrevb/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega32hvbrevb/words/no-wdt.asm
new file mode 100644
index 0000000..4a12261
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega32hvbrevb/words/no-wdt.asm
@@ -0,0 +1,22 @@
+; ( -- )
+; MCU
+; disable watch dog timer at runtime
+VE_NOWDT:
+ .dw $ff04
+ .db "-wdt"
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOWDT
+XT_NOWDT:
+ .dw PFA_NOWDT
+PFA_NOWDT:
+
+; Reset WDT
+ wdr
+; Write logical one to WDTOE and WDE
+ in_ temp1, WDTCR
+ ori temp1, (1<<WDTOE)|(1<<WDE)
+ out WDTCR, temp1
+; Turn off WDT
+ ldi temp1, (0<<WDE)
+ out_ WDTCR, temp1
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega32hvbrevb/words/sleep.asm b/amforth-6.5/avr8/devices/atmega32hvbrevb/words/sleep.asm
new file mode 100644
index 0000000..778fa32
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega32hvbrevb/words/sleep.asm
@@ -0,0 +1,24 @@
+; ( mode -- )
+; MCU
+; put the controller into the specified sleep mode
+VE_SLEEP:
+ .dw $ff05
+ .db "sleep", 0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_SLEEP
+XT_SLEEP:
+ .dw PFA_SLEEP
+PFA_SLEEP:
+ andi tosl, 7 ; leave only legal mode bits
+ swap tosl ; move to correct location (bits 6-4, atmega32)
+ ori tosl, $80 ; set the SE bit (atmega32: bit 7, not bit 0)
+ out_ MCUCR, tosl ; set the sleep config (atmega32: MCUCR not SMCR)
+ sleep ; nighty-night
+;; the 4 lower bits of MCUCR should not be touched
+ in_ tosl, MCUCR
+ andi tosl, $0F
+ out_ MCUCR, tosl
+ ;clr tosl ; need to clean up the SMCR reg before we leave
+ ;out SMCR, tosl ; 0 protects against accidental sleeps
+ loadtos ; pop argument from stack
+ jmp DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega32m1/atmega32m1.frt b/amforth-6.5/avr8/devices/atmega32m1/atmega32m1.frt
new file mode 100644
index 0000000..b6c0e2e
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega32m1/atmega32m1.frt
@@ -0,0 +1,513 @@
+\ Partname: ATmega32M1
+\ generated automatically
+
+\ PORTB
+&37 constant PORTB \ Port B Data Register
+&36 constant DDRB \ Port B Data Direction Register
+&35 constant PINB \ Port B Input Pins
+\ PORTC
+&40 constant PORTC \ Port C Data Register
+&39 constant DDRC \ Port C Data Direction Register
+&38 constant PINC \ Port C Input Pins
+\ PORTD
+&43 constant PORTD \ Port D Data Register
+&42 constant DDRD \ Port D Data Direction Register
+&41 constant PIND \ Port D Input Pins
+\ CAN
+&216 constant CANGCON \ CAN General Control Register
+ $80 constant CANGCON_ABRQ \ Abort Request
+ $40 constant CANGCON_OVRQ \ Overload Frame Request
+ $20 constant CANGCON_TTC \ Time Trigger Communication
+ $10 constant CANGCON_SYNTTC \ Synchronization of TTC
+ $08 constant CANGCON_LISTEN \ Listening Mode
+ $04 constant CANGCON_TEST \ Test Mode
+ $02 constant CANGCON_ENASTB \ Enable / Standby
+ $01 constant CANGCON_SWRES \ Software Reset Request
+&217 constant CANGSTA \ CAN General Status Register
+ $40 constant CANGSTA_OVFG \ Overload Frame Flag
+ $10 constant CANGSTA_TXBSY \ Transmitter Busy
+ $08 constant CANGSTA_RXBSY \ Receiver Busy
+ $04 constant CANGSTA_ENFG \ Enable Flag
+ $02 constant CANGSTA_BOFF \ Bus Off Mode
+ $01 constant CANGSTA_ERRP \ Error Passive Mode
+&218 constant CANGIT \ CAN General Interrupt Register Flags
+ $80 constant CANGIT_CANIT \ General Interrupt Flag
+ $40 constant CANGIT_BOFFIT \ Bus Off Interrupt Flag
+ $20 constant CANGIT_OVRTIM \ Overrun CAN Timer Flag
+ $10 constant CANGIT_BXOK \ Burst Receive Interrupt Flag
+ $08 constant CANGIT_SERG \ Stuff Error General Flag
+ $04 constant CANGIT_CERG \ CRC Error General Flag
+ $02 constant CANGIT_FERG \ Form Error General Flag
+ $01 constant CANGIT_AERG \ Ackknowledgement Error General Flag
+&219 constant CANGIE \ CAN General Interrupt Enable Register
+ $80 constant CANGIE_ENIT \ Enable all Interrupts
+ $40 constant CANGIE_ENBOFF \ Enable Bus Off Interrupt
+ $20 constant CANGIE_ENRX \ Enable Receive Interrupt
+ $10 constant CANGIE_ENTX \ Enable Transmitt Interrupt
+ $08 constant CANGIE_ENERR \ Enable MOb Error Interrupt
+ $04 constant CANGIE_ENBX \ Enable Burst Receive Interrupt
+ $02 constant CANGIE_ENERG \ Enable General Error Interrupt
+ $01 constant CANGIE_ENOVRT \ Enable CAN Timer Overrun Interrupt
+&220 constant CANEN2 \ Enable MOb Register 2
+ $3F constant CANEN2_ENMOB \ Enable MObs
+&221 constant CANEN1 \ Enable MOb Register 1(empty)
+&222 constant CANIE2 \ Enable Interrupt MOb Register 2
+ $3F constant CANIE2_IEMOB \ Interrupt Enable MObs
+&223 constant CANIE1 \ Enable Interrupt MOb Register 1 (empty)
+&224 constant CANSIT2 \ CAN Status Interrupt MOb Register 2
+ $3F constant CANSIT2_SIT \ Status of Interrupt MObs
+&225 constant CANSIT1 \ CAN Status Interrupt MOb Register 1 (empty)
+&226 constant CANBT1 \ CAN Bit Timing Register 1
+ $7E constant CANBT1_BRP \ Baud Rate Prescaler bits
+&227 constant CANBT2 \ CAN Bit Timing Register 2
+ $60 constant CANBT2_SJW \ Re-Sync Jump Width bits
+ $0E constant CANBT2_PRS \ Propagation Time Segment bits
+&228 constant CANBT3 \ CAN Bit Timing Register 3
+ $70 constant CANBT3_PHS2 \ Phase Segment 2 bits
+ $0E constant CANBT3_PHS1 \ Phase Segment 1 bits
+ $01 constant CANBT3_SMP \ Sample Type
+&229 constant CANTCON \ Timer Control Register
+&230 constant CANTIML \ Timer Register Low
+&231 constant CANTIMH \ Timer Register High
+&232 constant CANTTCL \ TTC Timer Register Low
+&233 constant CANTTCH \ TTC Timer Register High
+&234 constant CANTEC \ Transmit Error Counter Register
+&235 constant CANREC \ Receive Error Counter Register
+&236 constant CANHPMOB \ Highest Priority MOb Register
+ $F0 constant CANHPMOB_HPMOB \ Highest Priority MOb Number bits
+ $0F constant CANHPMOB_CGP \ CAN General Purpose bits
+&237 constant CANPAGE \ Page MOb Register
+ $F0 constant CANPAGE_MOBNB \ MOb Number bits
+ $08 constant CANPAGE_AINC \ MOb Data Buffer Auto Increment (Active Low)
+ $07 constant CANPAGE_INDX \ Data Buffer Index bits
+&238 constant CANSTMOB \ MOb Status Register
+ $80 constant CANSTMOB_DLCW \ Data Length Code Warning on MOb
+ $40 constant CANSTMOB_TXOK \ Transmit OK on MOb
+ $20 constant CANSTMOB_RXOK \ Receive OK on MOb
+ $10 constant CANSTMOB_BERR \ Bit Error on MOb
+ $08 constant CANSTMOB_SERR \ Stuff Error on MOb
+ $04 constant CANSTMOB_CERR \ CRC Error on MOb
+ $02 constant CANSTMOB_FERR \ Form Error on MOb
+ $01 constant CANSTMOB_AERR \ Ackknowledgement Error on MOb
+&239 constant CANCDMOB \ MOb Control and DLC Register
+ $C0 constant CANCDMOB_CONMOB \ MOb Config bits
+ $20 constant CANCDMOB_RPLV \ Reply Valid
+ $10 constant CANCDMOB_IDE \ Identifier Extension
+ $0F constant CANCDMOB_DLC \ Data Length Code bits
+&240 constant CANIDT4 \ Identifier Tag Register 4
+ $F8 constant CANIDT4_IDT \
+ $04 constant CANIDT4_RTRTAG \
+ $02 constant CANIDT4_RB1TAG \
+ $01 constant CANIDT4_RB0TAG \
+&241 constant CANIDT3 \ Identifier Tag Register 3
+&242 constant CANIDT2 \ Identifier Tag Register 2
+&243 constant CANIDT1 \ Identifier Tag Register 1
+&244 constant CANIDM4 \ Identifier Mask Register 4
+&245 constant CANIDM3 \ Identifier Mask Register 3
+&246 constant CANIDM2 \ Identifier Mask Register 2
+&247 constant CANIDM1 \ Identifier Mask Register 1
+&248 constant CANSTML \ Time Stamp Register Low
+&249 constant CANSTMH \ Time Stamp Register High
+&250 constant CANMSG \ Message Data Register
+\ ANALOG_COMPARATOR
+&148 constant AC0CON \ Analog Comparator 0 Control Register
+ $80 constant AC0CON_AC0EN \ Analog Comparator 0 Enable Bit
+ $40 constant AC0CON_AC0IE \ Analog Comparator 0 Interrupt Enable Bit
+ $30 constant AC0CON_AC0IS \ Analog Comparator 0 Interrupt Select Bits
+ $08 constant AC0CON_ACCKSEL \ Analog Comparator Clock Select
+ $07 constant AC0CON_AC0M \ Analog Comparator 0 Multiplexer Register
+&149 constant AC1CON \ Analog Comparator 1 Control Register
+ $80 constant AC1CON_AC1EN \ Analog Comparator 1 Enable Bit
+ $40 constant AC1CON_AC1IE \ Analog Comparator 1 Interrupt Enable Bit
+ $30 constant AC1CON_AC1IS \ Analog Comparator 1 Interrupt Select Bit
+ $08 constant AC1CON_AC1ICE \ Analog Comparator 1 Interrupt Capture Enable Bit
+ $07 constant AC1CON_AC1M \ Analog Comparator 1 Multiplexer Register
+&150 constant AC2CON \ Analog Comparator 2 Control Register
+ $80 constant AC2CON_AC2EN \ Analog Comparator 2 Enable Bit
+ $40 constant AC2CON_AC2IE \ Analog Comparator 2 Interrupt Enable Bit
+ $30 constant AC2CON_AC2IS \ Analog Comparator 2 Interrupt Select Bit
+ $07 constant AC2CON_AC2M \ Analog Comparator 2 Multiplexer Register
+&151 constant AC3CON \ Analog Comparator 3 Control Register
+ $80 constant AC3CON_AC3EN \ Analog Comparator 3 Enable Bit
+ $40 constant AC3CON_AC3IE \ Analog Comparator 3 Interrupt Enable Bit
+ $30 constant AC3CON_AC3IS \ Analog Comparator 3 Interrupt Select Bit
+ $07 constant AC3CON_AC3M \ Analog Comparator 3 Multiplexer Register
+&80 constant ACSR \ Analog Comparator Status Register
+ $80 constant ACSR_AC3IF \ Analog Comparator 3 Interrupt Flag Bit
+ $40 constant ACSR_AC2IF \ Analog Comparator 2 Interrupt Flag Bit
+ $20 constant ACSR_AC1IF \ Analog Comparator 1 Interrupt Flag Bit
+ $10 constant ACSR_AC0IF \ Analog Comparator 0 Interrupt Flag Bit
+ $08 constant ACSR_AC3O \ Analog Comparator 3 Output Bit
+ $04 constant ACSR_AC2O \ Analog Comparator 2 Output Bit
+ $02 constant ACSR_AC1O \ Analog Comparator 1 Output Bit
+ $01 constant ACSR_AC0O \ Analog Comparator 0 Output Bit
+\ DA_CONVERTER
+&146 constant DACH \ DAC Data Register High Byte
+ $FF constant DACH_DACH \ DAC Data Register High Byte Bits
+&145 constant DACL \ DAC Data Register Low Byte
+ $FF constant DACL_DACL \ DAC Data Register Low Byte Bits
+&144 constant DACON \ DAC Control Register
+ $80 constant DACON_DAATE \ DAC Auto Trigger Enable Bit
+ $70 constant DACON_DATS \ DAC Trigger Selection Bits
+ $04 constant DACON_DALA \ DAC Left Adjust
+ $01 constant DACON_DAEN \ DAC Enable Bit
+\ CPU
+&87 constant SPMCSR \ Store Program Memory Control Register
+ $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
+ $20 constant SPMCSR_SIGRD \ Signature Row Read
+ $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
+ $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
+ $04 constant SPMCSR_PGWRT \ Page Write
+ $02 constant SPMCSR_PGERS \ Page Erase
+ $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
+&95 constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ $08 constant SREG_V \ Two's Complement Overflow Flag
+ $04 constant SREG_N \ Negative Flag
+ $02 constant SREG_Z \ Zero Flag
+ $01 constant SREG_C \ Carry Flag
+&93 constant SP \ Stack Pointer
+&85 constant MCUCR \ MCU Control Register
+ $80 constant MCUCR_SPIPS \ SPI Pin Select
+ $10 constant MCUCR_PUD \ Pull-up disable
+ $02 constant MCUCR_IVSEL \ Interrupt Vector Select
+ $01 constant MCUCR_IVCE \ Interrupt Vector Change Enable
+&84 constant MCUSR \ MCU Status Register
+ $08 constant MCUSR_WDRF \ Watchdog Reset Flag
+ $04 constant MCUSR_BORF \ Brown-out Reset Flag
+ $02 constant MCUSR_EXTRF \ External Reset Flag
+ $01 constant MCUSR_PORF \ Power-on reset flag
+&102 constant OSCCAL \ Oscillator Calibration Value
+&97 constant CLKPR \
+ $80 constant CLKPR_CLKPCE \
+ $0F constant CLKPR_CLKPS \
+&83 constant SMCR \ Sleep Mode Control Register
+ $0E constant SMCR_SM \ Sleep Mode Select bits
+ $01 constant SMCR_SE \ Sleep Enable
+&58 constant GPIOR2 \ General Purpose IO Register 2
+ $FF constant GPIOR2_GPIOR \ General Purpose IO Register 2 bis
+&57 constant GPIOR1 \ General Purpose IO Register 1
+ $FF constant GPIOR1_GPIOR \ General Purpose IO Register 1 bis
+&62 constant GPIOR0 \ General Purpose IO Register 0
+ $80 constant GPIOR0_GPIOR07 \ General Purpose IO Register 0 bit 7
+ $40 constant GPIOR0_GPIOR06 \ General Purpose IO Register 0 bit 6
+ $20 constant GPIOR0_GPIOR05 \ General Purpose IO Register 0 bit 5
+ $10 constant GPIOR0_GPIOR04 \ General Purpose IO Register 0 bit 4
+ $08 constant GPIOR0_GPIOR03 \ General Purpose IO Register 0 bit 3
+ $04 constant GPIOR0_GPIOR02 \ General Purpose IO Register 0 bit 2
+ $02 constant GPIOR0_GPIOR01 \ General Purpose IO Register 0 bit 1
+ $01 constant GPIOR0_GPIOR00 \ General Purpose IO Register 0 bit 0
+&73 constant PLLCSR \ PLL Control And Status Register
+ $04 constant PLLCSR_PLLF \ PLL Factor
+ $02 constant PLLCSR_PLLE \ PLL Enable
+ $01 constant PLLCSR_PLOCK \ PLL Lock Detector
+&100 constant PRR \ Power Reduction Register
+ $40 constant PRR_PRCAN \ Power Reduction CAN
+ $20 constant PRR_PRPSC \ Power Reduction PSC
+ $10 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
+ $08 constant PRR_PRTIM0 \ Power Reduction Timer/Counter0
+ $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
+ $02 constant PRR_PRLIN \ Power Reduction LIN UART
+ $01 constant PRR_PRADC \ Power Reduction ADC
+\ PORTE
+&46 constant PORTE \ Port E Data Register
+&45 constant DDRE \ Port E Data Direction Register
+&44 constant PINE \ Port E Input Pins
+\ TIMER_COUNTER_0
+&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
+ $04 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare Match B Interrupt Enable
+ $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match A Interrupt Enable
+ $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
+&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
+ $04 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare Flag 0B
+ $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0A
+ $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
+&68 constant TCCR0A \ Timer/Counter Control Register A
+ $C0 constant TCCR0A_COM0A \ Compare Output Mode, Phase Correct PWM Mode
+ $30 constant TCCR0A_COM0B \ Compare Output Mode, Fast PWm
+ $03 constant TCCR0A_WGM0 \ Waveform Generation Mode
+&69 constant TCCR0B \ Timer/Counter Control Register B
+ $80 constant TCCR0B_FOC0A \ Force Output Compare A
+ $40 constant TCCR0B_FOC0B \ Force Output Compare B
+ $08 constant TCCR0B_WGM02 \
+ $07 constant TCCR0B_CS0 \ Clock Select
+&70 constant TCNT0 \ Timer/Counter0
+&71 constant OCR0A \ Timer/Counter0 Output Compare Register
+&72 constant OCR0B \ Timer/Counter0 Output Compare Register
+&67 constant GTCCR \ General Timer/Counter Control Register
+ $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
+ $40 constant GTCCR_ICPSEL1 \ Timer1 Input Capture Selection Bit
+ $01 constant GTCCR_PSR10 \ Prescaler Reset Timer/Counter1 and Timer/Counter0
+\ TIMER_COUNTER_1
+&111 constant TIMSK1 \ Timer/Counter Interrupt Mask Register
+ $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
+ $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output CompareB Match Interrupt Enable
+ $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output CompareA Match Interrupt Enable
+ $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
+&54 constant TIFR1 \ Timer/Counter Interrupt Flag register
+ $20 constant TIFR1_ICF1 \ Input Capture Flag 1
+ $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
+ $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
+ $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
+&128 constant TCCR1A \ Timer/Counter1 Control Register A
+ $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
+ $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
+ $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
+&129 constant TCCR1B \ Timer/Counter1 Control Register B
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
+ $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
+&130 constant TCCR1C \ Timer/Counter1 Control Register C
+ $80 constant TCCR1C_FOC1A \
+ $40 constant TCCR1C_FOC1B \
+&132 constant TCNT1 \ Timer/Counter1 Bytes
+&136 constant OCR1A \ Timer/Counter1 Output Compare Register Bytes
+&138 constant OCR1B \ Timer/Counter1 Output Compare Register Bytes
+&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
+\ AD_CONVERTER
+&124 constant ADMUX \ The ADC multiplexer Selection Register
+ $C0 constant ADMUX_REFS \ Reference Selection Bits
+ $20 constant ADMUX_ADLAR \ Left Adjust Result
+ $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
+&122 constant ADCSRA \ The ADC Control and Status register
+ $80 constant ADCSRA_ADEN \ ADC Enable
+ $40 constant ADCSRA_ADSC \ ADC Start Conversion
+ $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
+ $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
+ $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
+ $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
+&120 constant ADC \ ADC Data Register Bytes
+&123 constant ADCSRB \ ADC Control and Status Register B
+ $80 constant ADCSRB_ADHSM \ ADC High Speed Mode
+ $40 constant ADCSRB_ISRCEN \ Current Source Enable
+ $20 constant ADCSRB_AREFEN \ Analog Reference pin Enable
+ $0F constant ADCSRB_ADTS \ ADC Auto Trigger Sources
+&126 constant DIDR0 \ Digital Input Disable Register 0
+ $80 constant DIDR0_ADC7D \ ADC7 Digital input Disable
+ $40 constant DIDR0_ADC6D \ ADC6 Digital input Disable
+ $20 constant DIDR0_ADC5D \ ADC5 Digital input Disable
+ $10 constant DIDR0_ADC4D \ ADC4 Digital input Disable
+ $08 constant DIDR0_ADC3D \ ADC3 Digital input Disable
+ $04 constant DIDR0_ADC2D \ ADC2 Digital input Disable
+ $02 constant DIDR0_ADC1D \ ADC1 Digital input Disable
+ $01 constant DIDR0_ADC0D \ ADC0 Digital input Disable
+&127 constant DIDR1 \ Digital Input Disable Register 0
+ $40 constant DIDR1_AMP2PD \ AMP2P Pin Digital input Disable
+ $20 constant DIDR1_ACMP0D \ ACMP0 Pin Digital input Disable
+ $10 constant DIDR1_AMP0PD \ AMP0P Pin Digital input Disable
+ $08 constant DIDR1_AMP0ND \ AMP0N Pin Digital input Disable
+ $04 constant DIDR1_ADC10D \ ADC10 Pin Digital input Disable
+ $02 constant DIDR1_ADC9D \ ADC9 Pin Digital input Disable
+ $01 constant DIDR1_ADC8D \ ADC8 Pin Digital input Disable
+&117 constant AMP0CSR \
+ $80 constant AMP0CSR_AMP0EN \
+ $40 constant AMP0CSR_AMP0IS \
+ $30 constant AMP0CSR_AMP0G \
+ $08 constant AMP0CSR_AMPCMP0 \ Amplifier 0 - Comparator 0 Connection
+ $07 constant AMP0CSR_AMP0TS \
+&118 constant AMP1CSR \
+ $80 constant AMP1CSR_AMP1EN \
+ $40 constant AMP1CSR_AMP1IS \
+ $30 constant AMP1CSR_AMP1G \
+ $08 constant AMP1CSR_AMPCMP1 \ Amplifier 1 - Comparator 1 Connection
+ $07 constant AMP1CSR_AMP1TS \
+&119 constant AMP2CSR \
+ $80 constant AMP2CSR_AMP2EN \
+ $40 constant AMP2CSR_AMP2IS \
+ $30 constant AMP2CSR_AMP2G \
+ $08 constant AMP2CSR_AMPCMP2 \ Amplifier 2 - Comparator 2 Connection
+ $07 constant AMP2CSR_AMP2TS \
+\ LINUART
+&200 constant LINCR \ LIN Control Register
+ $80 constant LINCR_LSWRES \ Software Reset
+ $40 constant LINCR_LIN13 \ LIN Standard
+ $30 constant LINCR_LCONF \ LIN Configuration bits
+ $08 constant LINCR_LENA \ LIN or UART Enable
+ $07 constant LINCR_LCMD \ LIN Command and Mode bits
+&201 constant LINSIR \ LIN Status and Interrupt Register
+ $E0 constant LINSIR_LIDST \ Identifier Status bits
+ $10 constant LINSIR_LBUSY \ Busy Signal
+ $08 constant LINSIR_LERR \ Error Interrupt
+ $04 constant LINSIR_LIDOK \ Identifier Interrupt
+ $02 constant LINSIR_LTXOK \ Transmit Performed Interrupt
+ $01 constant LINSIR_LRXOK \ Receive Performed Interrupt
+&202 constant LINENIR \ LIN Enable Interrupt Register
+ $08 constant LINENIR_LENERR \ Enable Error Interrupt
+ $04 constant LINENIR_LENIDOK \ Enable Identifier Interrupt
+ $02 constant LINENIR_LENTXOK \ Enable Transmit Performed Interrupt
+ $01 constant LINENIR_LENRXOK \ Enable Receive Performed Interrupt
+&203 constant LINERR \ LIN Error Register
+ $80 constant LINERR_LABORT \ Abort Flag
+ $40 constant LINERR_LTOERR \ Frame Time Out Error Flag
+ $20 constant LINERR_LOVERR \ Overrun Error Flag
+ $10 constant LINERR_LFERR \ Framing Error Flag
+ $08 constant LINERR_LSERR \ Synchronization Error Flag
+ $04 constant LINERR_LPERR \ Parity Error Flag
+ $02 constant LINERR_LCERR \ Checksum Error Flag
+ $01 constant LINERR_LBERR \ Bit Error Flag
+&204 constant LINBTR \ LIN Bit Timing Register
+ $80 constant LINBTR_LDISR \ Disable Bit Timing Resynchronization
+ $3F constant LINBTR_LBT \ LIN Bit Timing bits
+&205 constant LINBRRL \ LIN Baud Rate Low Register
+ $FF constant LINBRRL_LDIV \
+&206 constant LINBRRH \ LIN Baud Rate High Register
+ $0F constant LINBRRH_LDIV \
+&207 constant LINDLR \ LIN Data Length Register
+ $F0 constant LINDLR_LTXDL \ LIN Transmit Data Length bits
+ $0F constant LINDLR_LRXDL \ LIN Receive Data Length bits
+&208 constant LINIDR \ LIN Identifier Register
+ $C0 constant LINIDR_LP \ Parity bits
+ $3F constant LINIDR_LID \ Identifier bit 5 or Data Length bits
+&209 constant LINSEL \ LIN Data Buffer Selection Register
+ $08 constant LINSEL_LAINC \ Auto Increment of Data Buffer Index (Active Low)
+ $07 constant LINSEL_LINDX \ FIFO LIN Data Buffer Index bits
+&210 constant LINDAT \ LIN Data Register
+ $FF constant LINDAT_LDATA \
+\ SPI
+&76 constant SPCR \ SPI Control Register
+ $80 constant SPCR_SPIE \ SPI Interrupt Enable
+ $40 constant SPCR_SPE \ SPI Enable
+ $20 constant SPCR_DORD \ Data Order
+ $10 constant SPCR_MSTR \ Master/Slave Select
+ $08 constant SPCR_CPOL \ Clock polarity
+ $04 constant SPCR_CPHA \ Clock Phase
+ $03 constant SPCR_SPR \ SPI Clock Rate Selects
+&77 constant SPSR \ SPI Status Register
+ $80 constant SPSR_SPIF \ SPI Interrupt Flag
+ $40 constant SPSR_WCOL \ Write Collision Flag
+ $01 constant SPSR_SPI2X \ Double SPI Speed Bit
+&78 constant SPDR \ SPI Data Register
+\ WATCHDOG
+&96 constant WDTCSR \ Watchdog Timer Control Register
+ $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Flag
+ $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Enable
+ $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
+ $10 constant WDTCSR_WDCE \ Watchdog Change Enable
+ $08 constant WDTCSR_WDE \ Watch Dog Enable
+\ EXTERNAL_INTERRUPT
+&105 constant EICRA \ External Interrupt Control Register
+ $C0 constant EICRA_ISC3 \ External Interrupt Sense Control Bit
+ $30 constant EICRA_ISC2 \ External Interrupt Sense Control Bit
+ $0C constant EICRA_ISC1 \ External Interrupt Sense Control 1 Bits
+ $03 constant EICRA_ISC0 \ External Interrupt Sense Control 0 Bits
+&61 constant EIMSK \ External Interrupt Mask Register
+ $0F constant EIMSK_INT \ External Interrupt Request 3 Enable
+&60 constant EIFR \ External Interrupt Flag Register
+ $0F constant EIFR_INTF \ External Interrupt Flags
+&104 constant PCICR \ Pin Change Interrupt Control Register
+ $0F constant PCICR_PCIE \ Pin Change Interrupt Enables
+&109 constant PCMSK3 \ Pin Change Mask Register 3
+ $07 constant PCMSK3_PCINT \ Pin Change Enable Masks
+&108 constant PCMSK2 \ Pin Change Mask Register 2
+ $FF constant PCMSK2_PCINT \ Pin Change Enable Masks
+&107 constant PCMSK1 \ Pin Change Mask Register 1
+ $FF constant PCMSK1_PCINT \ Pin Change Enable Masks
+&106 constant PCMSK0 \ Pin Change Mask Register 0
+ $FF constant PCMSK0_PCINT \ Pin Change Enable Masks
+&59 constant PCIFR \ Pin Change Interrupt Flag Register
+ $0F constant PCIFR_PCIF \ Pin Change Interrupt Flags
+\ EEPROM
+&65 constant EEAR \ EEPROM Read/Write Access
+&64 constant EEDR \ EEPROM Data Register
+&63 constant EECR \ EEPROM Control Register
+ $30 constant EECR_EEPM \
+ $08 constant EECR_EERIE \ EEProm Ready Interrupt Enable
+ $04 constant EECR_EEMWE \ EEPROM Master Write Enable
+ $02 constant EECR_EEWE \ EEPROM Write Enable
+ $01 constant EECR_EERE \ EEPROM Read Enable
+\ PSC
+&188 constant PIFR \ PSC Interrupt Flag Register
+ $0E constant PIFR_PEV \ PSC External Event 2 Interrupt
+ $01 constant PIFR_PEOP \ PSC End of Cycle Interrupt
+&187 constant PIM \ PSC Interrupt Mask Register
+ $0E constant PIM_PEVE \ External Event 2 Interrupt Enable
+ $01 constant PIM_PEOPE \ PSC End of Cycle Interrupt Enable
+&186 constant PMIC2 \ PSC Module 2 Input Control Register
+ $80 constant PMIC2_POVEN2 \ PSC Module 2 Overlap Enable
+ $40 constant PMIC2_PISEL2 \ PSC Module 2 Input Select
+ $20 constant PMIC2_PELEV2 \ PSC Module 2 Input Level Selector
+ $10 constant PMIC2_PFLTE2 \ PSC Module 2 Input Filter Enable
+ $08 constant PMIC2_PAOC2 \ PSC Module 2 Asynchronous Output Control
+ $07 constant PMIC2_PRFM2 \ PSC Module 2 Input Mode bits
+&185 constant PMIC1 \ PSC Module 1 Input Control Register
+ $80 constant PMIC1_POVEN1 \ PSC Module 1 Overlap Enable
+ $40 constant PMIC1_PISEL1 \ PSC Module 1 Input Select
+ $20 constant PMIC1_PELEV1 \ PSC Module 1 Input Level Selector
+ $10 constant PMIC1_PFLTE1 \ PSC Module 1 Input Filter Enable
+ $08 constant PMIC1_PAOC1 \ PSC Module 1 Asynchronous Output Control
+ $07 constant PMIC1_PRFM1 \ PSC Module 1 Input Mode bits
+&184 constant PMIC0 \ PSC Module 0 Input Control Register
+ $80 constant PMIC0_POVEN0 \ PSC Module 0 Overlap Enable
+ $40 constant PMIC0_PISEL0 \ PSC Module 0 Input Select
+ $20 constant PMIC0_PELEV0 \ PSC Module 0 Input Level Selector
+ $10 constant PMIC0_PFLTE0 \ PSC Module 0 Input Filter Enable
+ $08 constant PMIC0_PAOC0 \ PSC Module 0 Asynchronous Output Control
+ $07 constant PMIC0_PRFM0 \ PSC Module 0 Input Mode bits
+&183 constant PCTL \ PSC Control Register
+ $C0 constant PCTL_PPRE \ PSC Prescaler Select bits
+ $20 constant PCTL_PCLKSEL \ PSC Input Clock Select
+ $02 constant PCTL_PCCYC \ PSC Complete Cycle
+ $01 constant PCTL_PRUN \ PSC Run
+&182 constant POC \ PSC Output Configuration
+ $20 constant POC_POEN2B \ PSC Output 2B Enable
+ $10 constant POC_POEN2A \ PSC Output 2A Enable
+ $08 constant POC_POEN1B \ PSC Output 1B Enable
+ $04 constant POC_POEN1A \ PSC Output 1A Enable
+ $02 constant POC_POEN0B \ PSC Output 0B Enable
+ $01 constant POC_POEN0A \ PSC Output 0A Enable
+&181 constant PCNF \ PSC Configuration Register
+ $20 constant PCNF_PULOCK \ PSC Update Lock
+ $10 constant PCNF_PMODE \ PSC Mode
+ $08 constant PCNF_POPB \ PSC Output B Polarity
+ $04 constant PCNF_POPA \ PSC Output A Polarity
+&180 constant PSYNC \ PSC Synchro Configuration
+ $30 constant PSYNC_PSYNC2 \ Selection of Synchronization Out for ADC
+ $0C constant PSYNC_PSYNC1 \ Selection of Synchronization Out for ADC
+ $03 constant PSYNC_PSYNC0 \ Selection of Synchronization Out for ADC
+&178 constant POCR_RB \ PSC Output Compare RB Register
+&176 constant POCR2SB \ PSC Module 2 Output Compare SB Register
+&174 constant POCR2RA \ PSC Module 2 Output Compare RA Register
+&172 constant POCR2SA \ PSC Module 2 Output Compare SA Register
+&170 constant POCR1SB \ PSC Module 1 Output Compare SB Register
+&168 constant POCR1RA \ PSC Module 1 Output Compare RA Register
+&166 constant POCR1SA \ PSC Output Compare SA Register
+&164 constant POCR0SB \ PSC Output Compare SB Register
+&162 constant POCR0RA \ PSC Module 0 Output Compare RA Register
+&160 constant POCR0SA \ PSC Module 0 Output Compare SA Register
+
+\ Interrupts
+&2 constant ANACOMP0Addr \ Analog Comparator 0
+&4 constant ANACOMP1Addr \ Analog Comparator 1
+&6 constant ANACOMP2Addr \ Analog Comparator 2
+&8 constant ANACOMP3Addr \ Analog Comparator 3
+&10 constant PSC_FAULTAddr \ PSC Fault
+&12 constant PSC_ECAddr \ PSC End of Cycle
+&14 constant INT0Addr \ External Interrupt Request 0
+&16 constant INT1Addr \ External Interrupt Request 1
+&18 constant INT2Addr \ External Interrupt Request 2
+&20 constant INT3Addr \ External Interrupt Request 3
+&22 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+&24 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
+&26 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
+&28 constant TIMER1_OVFAddr \ Timer1/Counter1 Overflow
+&30 constant TIMER0_COMPAAddr \ Timer/Counter0 Compare Match A
+&32 constant TIMER0_COMPBAddr \ Timer/Counter0 Compare Match B
+&34 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
+&36 constant CAN_INTAddr \ CAN MOB, Burst, General Errors
+&38 constant CAN_TOVFAddr \ CAN Timer Overflow
+&40 constant LIN_TCAddr \ LIN Transfer Complete
+&42 constant LIN_ERRAddr \ LIN Error
+&44 constant PCINT0Addr \ Pin Change Interrupt Request 0
+&46 constant PCINT1Addr \ Pin Change Interrupt Request 1
+&48 constant PCINT2Addr \ Pin Change Interrupt Request 2
+&50 constant PCINT3Addr \ Pin Change Interrupt Request 3
+&52 constant SPI__STCAddr \ SPI Serial Transfer Complete
+&54 constant ADCAddr \ ADC Conversion Complete
+&56 constant WDTAddr \ Watchdog Time-Out Interrupt
+&58 constant EE_READYAddr \ EEPROM Ready
+&60 constant SPM_READYAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/atmega32m1/device.asm b/amforth-6.5/avr8/devices/atmega32m1/device.asm
new file mode 100644
index 0000000..cd6365a
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega32m1/device.asm
@@ -0,0 +1,120 @@
+; Partname: ATmega32M1
+; generated automatically, do not edit
+
+.nolist
+ .include "m32M1def.inc"
+.list
+
+.equ ramstart = 256
+.equ CELLSIZE = 2
+.macro readflashcell
+ lsl zl
+ rol zh
+ lpm @0, Z+
+ lpm @1, Z+
+.endmacro
+.macro writeflashcell
+ lsl zl
+ rol zh
+.endmacro
+.set WANT_PORTB = 0
+.set WANT_PORTC = 0
+.set WANT_PORTD = 0
+.set WANT_CAN = 0
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_DA_CONVERTER = 0
+.set WANT_CPU = 0
+.set WANT_PORTE = 0
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_AD_CONVERTER = 0
+.set WANT_LINUART = 0
+.set WANT_SPI = 0
+.set WANT_WATCHDOG = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_EEPROM = 0
+.set WANT_PSC = 0
+.equ intvecsize = 2 ; please verify; flash size: 32768 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.org 2
+ rcall isr ; Analog Comparator 0
+.org 4
+ rcall isr ; Analog Comparator 1
+.org 6
+ rcall isr ; Analog Comparator 2
+.org 8
+ rcall isr ; Analog Comparator 3
+.org 10
+ rcall isr ; PSC Fault
+.org 12
+ rcall isr ; PSC End of Cycle
+.org 14
+ rcall isr ; External Interrupt Request 0
+.org 16
+ rcall isr ; External Interrupt Request 1
+.org 18
+ rcall isr ; External Interrupt Request 2
+.org 20
+ rcall isr ; External Interrupt Request 3
+.org 22
+ rcall isr ; Timer/Counter1 Capture Event
+.org 24
+ rcall isr ; Timer/Counter1 Compare Match A
+.org 26
+ rcall isr ; Timer/Counter1 Compare Match B
+.org 28
+ rcall isr ; Timer1/Counter1 Overflow
+.org 30
+ rcall isr ; Timer/Counter0 Compare Match A
+.org 32
+ rcall isr ; Timer/Counter0 Compare Match B
+.org 34
+ rcall isr ; Timer/Counter0 Overflow
+.org 36
+ rcall isr ; CAN MOB, Burst, General Errors
+.org 38
+ rcall isr ; CAN Timer Overflow
+.org 40
+ rcall isr ; LIN Transfer Complete
+.org 42
+ rcall isr ; LIN Error
+.org 44
+ rcall isr ; Pin Change Interrupt Request 0
+.org 46
+ rcall isr ; Pin Change Interrupt Request 1
+.org 48
+ rcall isr ; Pin Change Interrupt Request 2
+.org 50
+ rcall isr ; Pin Change Interrupt Request 3
+.org 52
+ rcall isr ; SPI Serial Transfer Complete
+.org 54
+ rcall isr ; ADC Conversion Complete
+.org 56
+ rcall isr ; Watchdog Time-Out Interrupt
+.org 58
+ rcall isr ; EEPROM Ready
+.org 60
+ rcall isr ; Store Program Memory Read
+.equ INTVECTORS = 31
+.nooverlap
+
+; compatability layer (maybe empty)
+.equ EEPE = EEWE
+.equ EEMPE = EEMWE
+
+; controller data area, environment query mcu-info
+mcu_info:
+mcu_ramsize:
+ .dw 2048
+mcu_eepromsize:
+ .dw 1024
+mcu_maxdp:
+ .dw 28672
+mcu_numints:
+ .dw 31
+mcu_name:
+ .dw 10
+ .db "ATmega32M1"
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega32m1/device.inc b/amforth-6.5/avr8/devices/atmega32m1/device.inc
new file mode 100644
index 0000000..a2d9764
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega32m1/device.inc
@@ -0,0 +1,1734 @@
+; Partname: ATmega32M1
+; generated automatically, no not edit
+
+.if WANT_PORTB == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw 37
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw 36
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw 35
+
+.endif
+.if WANT_PORTC == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Register
+VE_PORTC:
+ .dw $ff05
+ .db "PORTC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTC
+XT_PORTC:
+ .dw PFA_DOVARIABLE
+PFA_PORTC:
+ .dw 40
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Direction Register
+VE_DDRC:
+ .dw $ff04
+ .db "DDRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRC
+XT_DDRC:
+ .dw PFA_DOVARIABLE
+PFA_DDRC:
+ .dw 39
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Input Pins
+VE_PINC:
+ .dw $ff04
+ .db "PINC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINC
+XT_PINC:
+ .dw PFA_DOVARIABLE
+PFA_PINC:
+ .dw 38
+
+.endif
+.if WANT_PORTD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw 43
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw 42
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw 41
+
+.endif
+.if WANT_CAN == 1
+; ( -- addr ) System Constant
+; R( -- )
+; CAN General Control Register
+VE_CANGCON:
+ .dw $ff07
+ .db "CANGCON",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANGCON
+XT_CANGCON:
+ .dw PFA_DOVARIABLE
+PFA_CANGCON:
+ .dw 216
+; ( -- addr ) System Constant
+; R( -- )
+; CAN General Status Register
+VE_CANGSTA:
+ .dw $ff07
+ .db "CANGSTA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANGSTA
+XT_CANGSTA:
+ .dw PFA_DOVARIABLE
+PFA_CANGSTA:
+ .dw 217
+; ( -- addr ) System Constant
+; R( -- )
+; CAN General Interrupt Register Flags
+VE_CANGIT:
+ .dw $ff06
+ .db "CANGIT"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANGIT
+XT_CANGIT:
+ .dw PFA_DOVARIABLE
+PFA_CANGIT:
+ .dw 218
+; ( -- addr ) System Constant
+; R( -- )
+; CAN General Interrupt Enable Register
+VE_CANGIE:
+ .dw $ff06
+ .db "CANGIE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANGIE
+XT_CANGIE:
+ .dw PFA_DOVARIABLE
+PFA_CANGIE:
+ .dw 219
+; ( -- addr ) System Constant
+; R( -- )
+; Enable MOb Register 2
+VE_CANEN2:
+ .dw $ff06
+ .db "CANEN2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANEN2
+XT_CANEN2:
+ .dw PFA_DOVARIABLE
+PFA_CANEN2:
+ .dw 220
+; ( -- addr ) System Constant
+; R( -- )
+; Enable MOb Register 1(empty)
+VE_CANEN1:
+ .dw $ff06
+ .db "CANEN1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANEN1
+XT_CANEN1:
+ .dw PFA_DOVARIABLE
+PFA_CANEN1:
+ .dw 221
+; ( -- addr ) System Constant
+; R( -- )
+; Enable Interrupt MOb Register 2
+VE_CANIE2:
+ .dw $ff06
+ .db "CANIE2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANIE2
+XT_CANIE2:
+ .dw PFA_DOVARIABLE
+PFA_CANIE2:
+ .dw 222
+; ( -- addr ) System Constant
+; R( -- )
+; Enable Interrupt MOb Register 1 (empty)
+VE_CANIE1:
+ .dw $ff06
+ .db "CANIE1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANIE1
+XT_CANIE1:
+ .dw PFA_DOVARIABLE
+PFA_CANIE1:
+ .dw 223
+; ( -- addr ) System Constant
+; R( -- )
+; CAN Status Interrupt MOb Register 2
+VE_CANSIT2:
+ .dw $ff07
+ .db "CANSIT2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANSIT2
+XT_CANSIT2:
+ .dw PFA_DOVARIABLE
+PFA_CANSIT2:
+ .dw 224
+; ( -- addr ) System Constant
+; R( -- )
+; CAN Status Interrupt MOb Register 1 (empty)
+VE_CANSIT1:
+ .dw $ff07
+ .db "CANSIT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANSIT1
+XT_CANSIT1:
+ .dw PFA_DOVARIABLE
+PFA_CANSIT1:
+ .dw 225
+; ( -- addr ) System Constant
+; R( -- )
+; CAN Bit Timing Register 1
+VE_CANBT1:
+ .dw $ff06
+ .db "CANBT1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANBT1
+XT_CANBT1:
+ .dw PFA_DOVARIABLE
+PFA_CANBT1:
+ .dw 226
+; ( -- addr ) System Constant
+; R( -- )
+; CAN Bit Timing Register 2
+VE_CANBT2:
+ .dw $ff06
+ .db "CANBT2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANBT2
+XT_CANBT2:
+ .dw PFA_DOVARIABLE
+PFA_CANBT2:
+ .dw 227
+; ( -- addr ) System Constant
+; R( -- )
+; CAN Bit Timing Register 3
+VE_CANBT3:
+ .dw $ff06
+ .db "CANBT3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANBT3
+XT_CANBT3:
+ .dw PFA_DOVARIABLE
+PFA_CANBT3:
+ .dw 228
+; ( -- addr ) System Constant
+; R( -- )
+; Timer Control Register
+VE_CANTCON:
+ .dw $ff07
+ .db "CANTCON",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANTCON
+XT_CANTCON:
+ .dw PFA_DOVARIABLE
+PFA_CANTCON:
+ .dw 229
+; ( -- addr ) System Constant
+; R( -- )
+; Timer Register Low
+VE_CANTIML:
+ .dw $ff07
+ .db "CANTIML",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANTIML
+XT_CANTIML:
+ .dw PFA_DOVARIABLE
+PFA_CANTIML:
+ .dw 230
+; ( -- addr ) System Constant
+; R( -- )
+; Timer Register High
+VE_CANTIMH:
+ .dw $ff07
+ .db "CANTIMH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANTIMH
+XT_CANTIMH:
+ .dw PFA_DOVARIABLE
+PFA_CANTIMH:
+ .dw 231
+; ( -- addr ) System Constant
+; R( -- )
+; TTC Timer Register Low
+VE_CANTTCL:
+ .dw $ff07
+ .db "CANTTCL",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANTTCL
+XT_CANTTCL:
+ .dw PFA_DOVARIABLE
+PFA_CANTTCL:
+ .dw 232
+; ( -- addr ) System Constant
+; R( -- )
+; TTC Timer Register High
+VE_CANTTCH:
+ .dw $ff07
+ .db "CANTTCH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANTTCH
+XT_CANTTCH:
+ .dw PFA_DOVARIABLE
+PFA_CANTTCH:
+ .dw 233
+; ( -- addr ) System Constant
+; R( -- )
+; Transmit Error Counter Register
+VE_CANTEC:
+ .dw $ff06
+ .db "CANTEC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANTEC
+XT_CANTEC:
+ .dw PFA_DOVARIABLE
+PFA_CANTEC:
+ .dw 234
+; ( -- addr ) System Constant
+; R( -- )
+; Receive Error Counter Register
+VE_CANREC:
+ .dw $ff06
+ .db "CANREC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANREC
+XT_CANREC:
+ .dw PFA_DOVARIABLE
+PFA_CANREC:
+ .dw 235
+; ( -- addr ) System Constant
+; R( -- )
+; Highest Priority MOb Register
+VE_CANHPMOB:
+ .dw $ff08
+ .db "CANHPMOB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANHPMOB
+XT_CANHPMOB:
+ .dw PFA_DOVARIABLE
+PFA_CANHPMOB:
+ .dw 236
+; ( -- addr ) System Constant
+; R( -- )
+; Page MOb Register
+VE_CANPAGE:
+ .dw $ff07
+ .db "CANPAGE",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANPAGE
+XT_CANPAGE:
+ .dw PFA_DOVARIABLE
+PFA_CANPAGE:
+ .dw 237
+; ( -- addr ) System Constant
+; R( -- )
+; MOb Status Register
+VE_CANSTMOB:
+ .dw $ff08
+ .db "CANSTMOB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANSTMOB
+XT_CANSTMOB:
+ .dw PFA_DOVARIABLE
+PFA_CANSTMOB:
+ .dw 238
+; ( -- addr ) System Constant
+; R( -- )
+; MOb Control and DLC Register
+VE_CANCDMOB:
+ .dw $ff08
+ .db "CANCDMOB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANCDMOB
+XT_CANCDMOB:
+ .dw PFA_DOVARIABLE
+PFA_CANCDMOB:
+ .dw 239
+; ( -- addr ) System Constant
+; R( -- )
+; Identifier Tag Register 4
+VE_CANIDT4:
+ .dw $ff07
+ .db "CANIDT4",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANIDT4
+XT_CANIDT4:
+ .dw PFA_DOVARIABLE
+PFA_CANIDT4:
+ .dw 240
+; ( -- addr ) System Constant
+; R( -- )
+; Identifier Tag Register 3
+VE_CANIDT3:
+ .dw $ff07
+ .db "CANIDT3",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANIDT3
+XT_CANIDT3:
+ .dw PFA_DOVARIABLE
+PFA_CANIDT3:
+ .dw 241
+; ( -- addr ) System Constant
+; R( -- )
+; Identifier Tag Register 2
+VE_CANIDT2:
+ .dw $ff07
+ .db "CANIDT2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANIDT2
+XT_CANIDT2:
+ .dw PFA_DOVARIABLE
+PFA_CANIDT2:
+ .dw 242
+; ( -- addr ) System Constant
+; R( -- )
+; Identifier Tag Register 1
+VE_CANIDT1:
+ .dw $ff07
+ .db "CANIDT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANIDT1
+XT_CANIDT1:
+ .dw PFA_DOVARIABLE
+PFA_CANIDT1:
+ .dw 243
+; ( -- addr ) System Constant
+; R( -- )
+; Identifier Mask Register 4
+VE_CANIDM4:
+ .dw $ff07
+ .db "CANIDM4",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANIDM4
+XT_CANIDM4:
+ .dw PFA_DOVARIABLE
+PFA_CANIDM4:
+ .dw 244
+; ( -- addr ) System Constant
+; R( -- )
+; Identifier Mask Register 3
+VE_CANIDM3:
+ .dw $ff07
+ .db "CANIDM3",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANIDM3
+XT_CANIDM3:
+ .dw PFA_DOVARIABLE
+PFA_CANIDM3:
+ .dw 245
+; ( -- addr ) System Constant
+; R( -- )
+; Identifier Mask Register 2
+VE_CANIDM2:
+ .dw $ff07
+ .db "CANIDM2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANIDM2
+XT_CANIDM2:
+ .dw PFA_DOVARIABLE
+PFA_CANIDM2:
+ .dw 246
+; ( -- addr ) System Constant
+; R( -- )
+; Identifier Mask Register 1
+VE_CANIDM1:
+ .dw $ff07
+ .db "CANIDM1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANIDM1
+XT_CANIDM1:
+ .dw PFA_DOVARIABLE
+PFA_CANIDM1:
+ .dw 247
+; ( -- addr ) System Constant
+; R( -- )
+; Time Stamp Register Low
+VE_CANSTML:
+ .dw $ff07
+ .db "CANSTML",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANSTML
+XT_CANSTML:
+ .dw PFA_DOVARIABLE
+PFA_CANSTML:
+ .dw 248
+; ( -- addr ) System Constant
+; R( -- )
+; Time Stamp Register High
+VE_CANSTMH:
+ .dw $ff07
+ .db "CANSTMH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANSTMH
+XT_CANSTMH:
+ .dw PFA_DOVARIABLE
+PFA_CANSTMH:
+ .dw 249
+; ( -- addr ) System Constant
+; R( -- )
+; Message Data Register
+VE_CANMSG:
+ .dw $ff06
+ .db "CANMSG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANMSG
+XT_CANMSG:
+ .dw PFA_DOVARIABLE
+PFA_CANMSG:
+ .dw 250
+
+.endif
+.if WANT_ANALOG_COMPARATOR == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator 0 Control Register
+VE_AC0CON:
+ .dw $ff06
+ .db "AC0CON"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_AC0CON
+XT_AC0CON:
+ .dw PFA_DOVARIABLE
+PFA_AC0CON:
+ .dw 148
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator 1 Control Register
+VE_AC1CON:
+ .dw $ff06
+ .db "AC1CON"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_AC1CON
+XT_AC1CON:
+ .dw PFA_DOVARIABLE
+PFA_AC1CON:
+ .dw 149
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator 2 Control Register
+VE_AC2CON:
+ .dw $ff06
+ .db "AC2CON"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_AC2CON
+XT_AC2CON:
+ .dw PFA_DOVARIABLE
+PFA_AC2CON:
+ .dw 150
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator 3 Control Register
+VE_AC3CON:
+ .dw $ff06
+ .db "AC3CON"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_AC3CON
+XT_AC3CON:
+ .dw PFA_DOVARIABLE
+PFA_AC3CON:
+ .dw 151
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw 80
+
+.endif
+.if WANT_DA_CONVERTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; DAC Data Register High Byte
+VE_DACH:
+ .dw $ff04
+ .db "DACH"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DACH
+XT_DACH:
+ .dw PFA_DOVARIABLE
+PFA_DACH:
+ .dw 146
+; ( -- addr ) System Constant
+; R( -- )
+; DAC Data Register Low Byte
+VE_DACL:
+ .dw $ff04
+ .db "DACL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DACL
+XT_DACL:
+ .dw PFA_DOVARIABLE
+PFA_DACL:
+ .dw 145
+; ( -- addr ) System Constant
+; R( -- )
+; DAC Control Register
+VE_DACON:
+ .dw $ff05
+ .db "DACON",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DACON
+XT_DACON:
+ .dw PFA_DOVARIABLE
+PFA_DACON:
+ .dw 144
+
+.endif
+.if WANT_CPU == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control Register
+VE_SPMCSR:
+ .dw $ff06
+ .db "SPMCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCSR
+XT_SPMCSR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCSR:
+ .dw 87
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw 95
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer
+VE_SP:
+ .dw $ff02
+ .db "SP"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SP
+XT_SP:
+ .dw PFA_DOVARIABLE
+PFA_SP:
+ .dw 93
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw 85
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Status Register
+VE_MCUSR:
+ .dw $ff05
+ .db "MCUSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUSR
+XT_MCUSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUSR:
+ .dw 84
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Calibration Value
+VE_OSCCAL:
+ .dw $ff06
+ .db "OSCCAL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSCCAL
+XT_OSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_OSCCAL:
+ .dw 102
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_CLKPR:
+ .dw $ff05
+ .db "CLKPR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKPR
+XT_CLKPR:
+ .dw PFA_DOVARIABLE
+PFA_CLKPR:
+ .dw 97
+; ( -- addr ) System Constant
+; R( -- )
+; Sleep Mode Control Register
+VE_SMCR:
+ .dw $ff04
+ .db "SMCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SMCR
+XT_SMCR:
+ .dw PFA_DOVARIABLE
+PFA_SMCR:
+ .dw 83
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 2
+VE_GPIOR2:
+ .dw $ff06
+ .db "GPIOR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR2
+XT_GPIOR2:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR2:
+ .dw 58
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 1
+VE_GPIOR1:
+ .dw $ff06
+ .db "GPIOR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR1
+XT_GPIOR1:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR1:
+ .dw 57
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 0
+VE_GPIOR0:
+ .dw $ff06
+ .db "GPIOR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR0
+XT_GPIOR0:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR0:
+ .dw 62
+; ( -- addr ) System Constant
+; R( -- )
+; PLL Control And Status Register
+VE_PLLCSR:
+ .dw $ff06
+ .db "PLLCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PLLCSR
+XT_PLLCSR:
+ .dw PFA_DOVARIABLE
+PFA_PLLCSR:
+ .dw 73
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register
+VE_PRR:
+ .dw $ff03
+ .db "PRR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR
+XT_PRR:
+ .dw PFA_DOVARIABLE
+PFA_PRR:
+ .dw 100
+
+.endif
+.if WANT_PORTE == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port E Data Register
+VE_PORTE:
+ .dw $ff05
+ .db "PORTE",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTE
+XT_PORTE:
+ .dw PFA_DOVARIABLE
+PFA_PORTE:
+ .dw 46
+; ( -- addr ) System Constant
+; R( -- )
+; Port E Data Direction Register
+VE_DDRE:
+ .dw $ff04
+ .db "DDRE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRE
+XT_DDRE:
+ .dw PFA_DOVARIABLE
+PFA_DDRE:
+ .dw 45
+; ( -- addr ) System Constant
+; R( -- )
+; Port E Input Pins
+VE_PINE:
+ .dw $ff04
+ .db "PINE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINE
+XT_PINE:
+ .dw PFA_DOVARIABLE
+PFA_PINE:
+ .dw 44
+
+.endif
+.if WANT_TIMER_COUNTER_0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Mask Register
+VE_TIMSK0:
+ .dw $ff06
+ .db "TIMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK0
+XT_TIMSK0:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK0:
+ .dw 110
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Flag register
+VE_TIFR0:
+ .dw $ff05
+ .db "TIFR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR0
+XT_TIFR0:
+ .dw PFA_DOVARIABLE
+PFA_TIFR0:
+ .dw 53
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register A
+VE_TCCR0A:
+ .dw $ff06
+ .db "TCCR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0A
+XT_TCCR0A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0A:
+ .dw 68
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register B
+VE_TCCR0B:
+ .dw $ff06
+ .db "TCCR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0B
+XT_TCCR0B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0B:
+ .dw 69
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw 70
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0A:
+ .dw $ff05
+ .db "OCR0A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0A
+XT_OCR0A:
+ .dw PFA_DOVARIABLE
+PFA_OCR0A:
+ .dw 71
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0B:
+ .dw $ff05
+ .db "OCR0B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0B
+XT_OCR0B:
+ .dw PFA_DOVARIABLE
+PFA_OCR0B:
+ .dw 72
+; ( -- addr ) System Constant
+; R( -- )
+; General Timer/Counter Control Register
+VE_GTCCR:
+ .dw $ff05
+ .db "GTCCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GTCCR
+XT_GTCCR:
+ .dw PFA_DOVARIABLE
+PFA_GTCCR:
+ .dw 67
+
+.endif
+.if WANT_TIMER_COUNTER_1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Mask Register
+VE_TIMSK1:
+ .dw $ff06
+ .db "TIMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK1
+XT_TIMSK1:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK1:
+ .dw 111
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Flag register
+VE_TIFR1:
+ .dw $ff05
+ .db "TIFR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR1
+XT_TIFR1:
+ .dw PFA_DOVARIABLE
+PFA_TIFR1:
+ .dw 54
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw 128
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw 129
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register C
+VE_TCCR1C:
+ .dw $ff06
+ .db "TCCR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1C
+XT_TCCR1C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1C:
+ .dw 130
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Bytes
+VE_TCNT1:
+ .dw $ff05
+ .db "TCNT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1
+XT_TCNT1:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1:
+ .dw 132
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register Bytes
+VE_OCR1A:
+ .dw $ff05
+ .db "OCR1A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1A
+XT_OCR1A:
+ .dw PFA_DOVARIABLE
+PFA_OCR1A:
+ .dw 136
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register Bytes
+VE_OCR1B:
+ .dw $ff05
+ .db "OCR1B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1B
+XT_OCR1B:
+ .dw PFA_DOVARIABLE
+PFA_OCR1B:
+ .dw 138
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Bytes
+VE_ICR1:
+ .dw $ff04
+ .db "ICR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1
+XT_ICR1:
+ .dw PFA_DOVARIABLE
+PFA_ICR1:
+ .dw 134
+
+.endif
+.if WANT_AD_CONVERTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC multiplexer Selection Register
+VE_ADMUX:
+ .dw $ff05
+ .db "ADMUX",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADMUX
+XT_ADMUX:
+ .dw PFA_DOVARIABLE
+PFA_ADMUX:
+ .dw 124
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register
+VE_ADCSRA:
+ .dw $ff06
+ .db "ADCSRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRA
+XT_ADCSRA:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRA:
+ .dw 122
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register Bytes
+VE_ADC:
+ .dw $ff03
+ .db "ADC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADC
+XT_ADC:
+ .dw PFA_DOVARIABLE
+PFA_ADC:
+ .dw 120
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Control and Status Register B
+VE_ADCSRB:
+ .dw $ff06
+ .db "ADCSRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRB
+XT_ADCSRB:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRB:
+ .dw 123
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 0
+VE_DIDR0:
+ .dw $ff05
+ .db "DIDR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR0
+XT_DIDR0:
+ .dw PFA_DOVARIABLE
+PFA_DIDR0:
+ .dw 126
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 0
+VE_DIDR1:
+ .dw $ff05
+ .db "DIDR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR1
+XT_DIDR1:
+ .dw PFA_DOVARIABLE
+PFA_DIDR1:
+ .dw 127
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_AMP0CSR:
+ .dw $ff07
+ .db "AMP0CSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_AMP0CSR
+XT_AMP0CSR:
+ .dw PFA_DOVARIABLE
+PFA_AMP0CSR:
+ .dw 117
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_AMP1CSR:
+ .dw $ff07
+ .db "AMP1CSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_AMP1CSR
+XT_AMP1CSR:
+ .dw PFA_DOVARIABLE
+PFA_AMP1CSR:
+ .dw 118
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_AMP2CSR:
+ .dw $ff07
+ .db "AMP2CSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_AMP2CSR
+XT_AMP2CSR:
+ .dw PFA_DOVARIABLE
+PFA_AMP2CSR:
+ .dw 119
+
+.endif
+.if WANT_LINUART == 1
+; ( -- addr ) System Constant
+; R( -- )
+; LIN Control Register
+VE_LINCR:
+ .dw $ff05
+ .db "LINCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LINCR
+XT_LINCR:
+ .dw PFA_DOVARIABLE
+PFA_LINCR:
+ .dw 200
+; ( -- addr ) System Constant
+; R( -- )
+; LIN Status and Interrupt Register
+VE_LINSIR:
+ .dw $ff06
+ .db "LINSIR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LINSIR
+XT_LINSIR:
+ .dw PFA_DOVARIABLE
+PFA_LINSIR:
+ .dw 201
+; ( -- addr ) System Constant
+; R( -- )
+; LIN Enable Interrupt Register
+VE_LINENIR:
+ .dw $ff07
+ .db "LINENIR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LINENIR
+XT_LINENIR:
+ .dw PFA_DOVARIABLE
+PFA_LINENIR:
+ .dw 202
+; ( -- addr ) System Constant
+; R( -- )
+; LIN Error Register
+VE_LINERR:
+ .dw $ff06
+ .db "LINERR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LINERR
+XT_LINERR:
+ .dw PFA_DOVARIABLE
+PFA_LINERR:
+ .dw 203
+; ( -- addr ) System Constant
+; R( -- )
+; LIN Bit Timing Register
+VE_LINBTR:
+ .dw $ff06
+ .db "LINBTR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LINBTR
+XT_LINBTR:
+ .dw PFA_DOVARIABLE
+PFA_LINBTR:
+ .dw 204
+; ( -- addr ) System Constant
+; R( -- )
+; LIN Baud Rate Low Register
+VE_LINBRRL:
+ .dw $ff07
+ .db "LINBRRL",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LINBRRL
+XT_LINBRRL:
+ .dw PFA_DOVARIABLE
+PFA_LINBRRL:
+ .dw 205
+; ( -- addr ) System Constant
+; R( -- )
+; LIN Baud Rate High Register
+VE_LINBRRH:
+ .dw $ff07
+ .db "LINBRRH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LINBRRH
+XT_LINBRRH:
+ .dw PFA_DOVARIABLE
+PFA_LINBRRH:
+ .dw 206
+; ( -- addr ) System Constant
+; R( -- )
+; LIN Data Length Register
+VE_LINDLR:
+ .dw $ff06
+ .db "LINDLR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LINDLR
+XT_LINDLR:
+ .dw PFA_DOVARIABLE
+PFA_LINDLR:
+ .dw 207
+; ( -- addr ) System Constant
+; R( -- )
+; LIN Identifier Register
+VE_LINIDR:
+ .dw $ff06
+ .db "LINIDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LINIDR
+XT_LINIDR:
+ .dw PFA_DOVARIABLE
+PFA_LINIDR:
+ .dw 208
+; ( -- addr ) System Constant
+; R( -- )
+; LIN Data Buffer Selection Register
+VE_LINSEL:
+ .dw $ff06
+ .db "LINSEL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LINSEL
+XT_LINSEL:
+ .dw PFA_DOVARIABLE
+PFA_LINSEL:
+ .dw 209
+; ( -- addr ) System Constant
+; R( -- )
+; LIN Data Register
+VE_LINDAT:
+ .dw $ff06
+ .db "LINDAT"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LINDAT
+XT_LINDAT:
+ .dw PFA_DOVARIABLE
+PFA_LINDAT:
+ .dw 210
+
+.endif
+.if WANT_SPI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR:
+ .dw $ff04
+ .db "SPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR
+XT_SPCR:
+ .dw PFA_DOVARIABLE
+PFA_SPCR:
+ .dw 76
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR:
+ .dw $ff04
+ .db "SPSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR
+XT_SPSR:
+ .dw PFA_DOVARIABLE
+PFA_SPSR:
+ .dw 77
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR:
+ .dw $ff04
+ .db "SPDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR
+XT_SPDR:
+ .dw PFA_DOVARIABLE
+PFA_SPDR:
+ .dw 78
+
+.endif
+.if WANT_WATCHDOG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCSR:
+ .dw $ff06
+ .db "WDTCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCSR
+XT_WDTCSR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCSR:
+ .dw 96
+
+.endif
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register
+VE_EICRA:
+ .dw $ff05
+ .db "EICRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRA
+XT_EICRA:
+ .dw PFA_DOVARIABLE
+PFA_EICRA:
+ .dw 105
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Mask Register
+VE_EIMSK:
+ .dw $ff05
+ .db "EIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIMSK
+XT_EIMSK:
+ .dw PFA_DOVARIABLE
+PFA_EIMSK:
+ .dw 61
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Flag Register
+VE_EIFR:
+ .dw $ff04
+ .db "EIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIFR
+XT_EIFR:
+ .dw PFA_DOVARIABLE
+PFA_EIFR:
+ .dw 60
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Interrupt Control Register
+VE_PCICR:
+ .dw $ff05
+ .db "PCICR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCICR
+XT_PCICR:
+ .dw PFA_DOVARIABLE
+PFA_PCICR:
+ .dw 104
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 3
+VE_PCMSK3:
+ .dw $ff06
+ .db "PCMSK3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK3
+XT_PCMSK3:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK3:
+ .dw 109
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 2
+VE_PCMSK2:
+ .dw $ff06
+ .db "PCMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK2
+XT_PCMSK2:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK2:
+ .dw 108
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 1
+VE_PCMSK1:
+ .dw $ff06
+ .db "PCMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK1
+XT_PCMSK1:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK1:
+ .dw 107
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 0
+VE_PCMSK0:
+ .dw $ff06
+ .db "PCMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK0
+XT_PCMSK0:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK0:
+ .dw 106
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Interrupt Flag Register
+VE_PCIFR:
+ .dw $ff05
+ .db "PCIFR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCIFR
+XT_PCIFR:
+ .dw PFA_DOVARIABLE
+PFA_PCIFR:
+ .dw 59
+
+.endif
+.if WANT_EEPROM == 1
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Read/Write Access
+VE_EEAR:
+ .dw $ff04
+ .db "EEAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEAR
+XT_EEAR:
+ .dw PFA_DOVARIABLE
+PFA_EEAR:
+ .dw 65
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw 64
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw 63
+
+.endif
+.if WANT_PSC == 1
+; ( -- addr ) System Constant
+; R( -- )
+; PSC Interrupt Flag Register
+VE_PIFR:
+ .dw $ff04
+ .db "PIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIFR
+XT_PIFR:
+ .dw PFA_DOVARIABLE
+PFA_PIFR:
+ .dw 188
+; ( -- addr ) System Constant
+; R( -- )
+; PSC Interrupt Mask Register
+VE_PIM:
+ .dw $ff03
+ .db "PIM",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIM
+XT_PIM:
+ .dw PFA_DOVARIABLE
+PFA_PIM:
+ .dw 187
+; ( -- addr ) System Constant
+; R( -- )
+; PSC Module 2 Input Control Register
+VE_PMIC2:
+ .dw $ff05
+ .db "PMIC2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PMIC2
+XT_PMIC2:
+ .dw PFA_DOVARIABLE
+PFA_PMIC2:
+ .dw 186
+; ( -- addr ) System Constant
+; R( -- )
+; PSC Module 1 Input Control Register
+VE_PMIC1:
+ .dw $ff05
+ .db "PMIC1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PMIC1
+XT_PMIC1:
+ .dw PFA_DOVARIABLE
+PFA_PMIC1:
+ .dw 185
+; ( -- addr ) System Constant
+; R( -- )
+; PSC Module 0 Input Control Register
+VE_PMIC0:
+ .dw $ff05
+ .db "PMIC0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PMIC0
+XT_PMIC0:
+ .dw PFA_DOVARIABLE
+PFA_PMIC0:
+ .dw 184
+; ( -- addr ) System Constant
+; R( -- )
+; PSC Control Register
+VE_PCTL:
+ .dw $ff04
+ .db "PCTL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCTL
+XT_PCTL:
+ .dw PFA_DOVARIABLE
+PFA_PCTL:
+ .dw 183
+; ( -- addr ) System Constant
+; R( -- )
+; PSC Output Configuration
+VE_POC:
+ .dw $ff03
+ .db "POC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_POC
+XT_POC:
+ .dw PFA_DOVARIABLE
+PFA_POC:
+ .dw 182
+; ( -- addr ) System Constant
+; R( -- )
+; PSC Configuration Register
+VE_PCNF:
+ .dw $ff04
+ .db "PCNF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCNF
+XT_PCNF:
+ .dw PFA_DOVARIABLE
+PFA_PCNF:
+ .dw 181
+; ( -- addr ) System Constant
+; R( -- )
+; PSC Synchro Configuration
+VE_PSYNC:
+ .dw $ff05
+ .db "PSYNC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PSYNC
+XT_PSYNC:
+ .dw PFA_DOVARIABLE
+PFA_PSYNC:
+ .dw 180
+; ( -- addr ) System Constant
+; R( -- )
+; PSC Output Compare RB Register
+VE_POCR_RB:
+ .dw $ff07
+ .db "POCR_RB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_POCR_RB
+XT_POCR_RB:
+ .dw PFA_DOVARIABLE
+PFA_POCR_RB:
+ .dw 178
+; ( -- addr ) System Constant
+; R( -- )
+; PSC Module 2 Output Compare SB Register
+VE_POCR2SB:
+ .dw $ff07
+ .db "POCR2SB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_POCR2SB
+XT_POCR2SB:
+ .dw PFA_DOVARIABLE
+PFA_POCR2SB:
+ .dw 176
+; ( -- addr ) System Constant
+; R( -- )
+; PSC Module 2 Output Compare RA Register
+VE_POCR2RA:
+ .dw $ff07
+ .db "POCR2RA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_POCR2RA
+XT_POCR2RA:
+ .dw PFA_DOVARIABLE
+PFA_POCR2RA:
+ .dw 174
+; ( -- addr ) System Constant
+; R( -- )
+; PSC Module 2 Output Compare SA Register
+VE_POCR2SA:
+ .dw $ff07
+ .db "POCR2SA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_POCR2SA
+XT_POCR2SA:
+ .dw PFA_DOVARIABLE
+PFA_POCR2SA:
+ .dw 172
+; ( -- addr ) System Constant
+; R( -- )
+; PSC Module 1 Output Compare SB Register
+VE_POCR1SB:
+ .dw $ff07
+ .db "POCR1SB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_POCR1SB
+XT_POCR1SB:
+ .dw PFA_DOVARIABLE
+PFA_POCR1SB:
+ .dw 170
+; ( -- addr ) System Constant
+; R( -- )
+; PSC Module 1 Output Compare RA Register
+VE_POCR1RA:
+ .dw $ff07
+ .db "POCR1RA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_POCR1RA
+XT_POCR1RA:
+ .dw PFA_DOVARIABLE
+PFA_POCR1RA:
+ .dw 168
+; ( -- addr ) System Constant
+; R( -- )
+; PSC Output Compare SA Register
+VE_POCR1SA:
+ .dw $ff07
+ .db "POCR1SA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_POCR1SA
+XT_POCR1SA:
+ .dw PFA_DOVARIABLE
+PFA_POCR1SA:
+ .dw 166
+; ( -- addr ) System Constant
+; R( -- )
+; PSC Output Compare SB Register
+VE_POCR0SB:
+ .dw $ff07
+ .db "POCR0SB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_POCR0SB
+XT_POCR0SB:
+ .dw PFA_DOVARIABLE
+PFA_POCR0SB:
+ .dw 164
+; ( -- addr ) System Constant
+; R( -- )
+; PSC Module 0 Output Compare RA Register
+VE_POCR0RA:
+ .dw $ff07
+ .db "POCR0RA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_POCR0RA
+XT_POCR0RA:
+ .dw PFA_DOVARIABLE
+PFA_POCR0RA:
+ .dw 162
+; ( -- addr ) System Constant
+; R( -- )
+; PSC Module 0 Output Compare SA Register
+VE_POCR0SA:
+ .dw $ff07
+ .db "POCR0SA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_POCR0SA
+XT_POCR0SA:
+ .dw PFA_DOVARIABLE
+PFA_POCR0SA:
+ .dw 160
+
+.endif
diff --git a/amforth-6.5/avr8/devices/atmega32m1/device.py b/amforth-6.5/avr8/devices/atmega32m1/device.py
new file mode 100644
index 0000000..dcee998
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega32m1/device.py
@@ -0,0 +1,537 @@
+# Generated Automatically
+
+# Partname ATmega32M1
+
+MCUREGS = {
+# Interrupt Vectors
+ 'ANACOMP0Addr' : '#2', # Analog Comparator 0
+ 'ANACOMP1Addr' : '#4', # Analog Comparator 1
+ 'ANACOMP2Addr' : '#6', # Analog Comparator 2
+ 'ANACOMP3Addr' : '#8', # Analog Comparator 3
+ 'PSC_FAULTAddr' : '#10', # PSC Fault
+ 'PSC_ECAddr' : '#12', # PSC End of Cycle
+ 'INT0Addr' : '#14', # External Interrupt Request 0
+ 'INT1Addr' : '#16', # External Interrupt Request 1
+ 'INT2Addr' : '#18', # External Interrupt Request 2
+ 'INT3Addr' : '#20', # External Interrupt Request 3
+ 'TIMER1_CAPTAddr' : '#22', # Timer/Counter1 Capture Event
+ 'TIMER1_COMPAAddr' : '#24', # Timer/Counter1 Compare Match A
+ 'TIMER1_COMPBAddr' : '#26', # Timer/Counter1 Compare Match B
+ 'TIMER1_OVFAddr' : '#28', # Timer1/Counter1 Overflow
+ 'TIMER0_COMPAAddr' : '#30', # Timer/Counter0 Compare Match A
+ 'TIMER0_COMPBAddr' : '#32', # Timer/Counter0 Compare Match B
+ 'TIMER0_OVFAddr' : '#34', # Timer/Counter0 Overflow
+ 'CAN_INTAddr' : '#36', # CAN MOB, Burst, General Errors
+ 'CAN_TOVFAddr' : '#38', # CAN Timer Overflow
+ 'LIN_TCAddr' : '#40', # LIN Transfer Complete
+ 'LIN_ERRAddr' : '#42', # LIN Error
+ 'PCINT0Addr' : '#44', # Pin Change Interrupt Request 0
+ 'PCINT1Addr' : '#46', # Pin Change Interrupt Request 1
+ 'PCINT2Addr' : '#48', # Pin Change Interrupt Request 2
+ 'PCINT3Addr' : '#50', # Pin Change Interrupt Request 3
+ 'SPI_STCAddr' : '#52', # SPI Serial Transfer Complete
+ 'ADCAddr' : '#54', # ADC Conversion Complete
+ 'WDTAddr' : '#56', # Watchdog Time-Out Interrupt
+ 'EE_READYAddr' : '#58', # EEPROM Ready
+ 'SPM_READYAddr' : '#60', # Store Program Memory Read
+
+# Module PORTB
+ 'PORTB' : '$25', # Port B Data Register
+ 'DDRB' : '$24', # Port B Data Direction Register
+ 'PINB' : '$23', # Port B Input Pins
+
+# Module PORTC
+ 'PORTC' : '$28', # Port C Data Register
+ 'DDRC' : '$27', # Port C Data Direction Register
+ 'PINC' : '$26', # Port C Input Pins
+
+# Module PORTD
+ 'PORTD' : '$2b', # Port D Data Register
+ 'DDRD' : '$2a', # Port D Data Direction Register
+ 'PIND' : '$29', # Port D Input Pins
+
+# Module CAN
+ 'CANGCON' : '$d8', # CAN General Control Register
+ 'CANGCON_ABRQ': '$80', # Abort Request
+ 'CANGCON_OVRQ': '$40', # Overload Frame Request
+ 'CANGCON_TTC': '$20', # Time Trigger Communication
+ 'CANGCON_SYNTTC': '$10', # Synchronization of TTC
+ 'CANGCON_LISTEN': '$8', # Listening Mode
+ 'CANGCON_TEST': '$4', # Test Mode
+ 'CANGCON_ENASTB': '$2', # Enable / Standby
+ 'CANGCON_SWRES': '$1', # Software Reset Request
+ 'CANGSTA' : '$d9', # CAN General Status Register
+ 'CANGSTA_OVFG': '$40', # Overload Frame Flag
+ 'CANGSTA_TXBSY': '$10', # Transmitter Busy
+ 'CANGSTA_RXBSY': '$8', # Receiver Busy
+ 'CANGSTA_ENFG': '$4', # Enable Flag
+ 'CANGSTA_BOFF': '$2', # Bus Off Mode
+ 'CANGSTA_ERRP': '$1', # Error Passive Mode
+ 'CANGIT' : '$da', # CAN General Interrupt Register
+ 'CANGIT_CANIT': '$80', # General Interrupt Flag
+ 'CANGIT_BOFFIT': '$40', # Bus Off Interrupt Flag
+ 'CANGIT_OVRTIM': '$20', # Overrun CAN Timer Flag
+ 'CANGIT_BXOK': '$10', # Burst Receive Interrupt Flag
+ 'CANGIT_SERG': '$8', # Stuff Error General Flag
+ 'CANGIT_CERG': '$4', # CRC Error General Flag
+ 'CANGIT_FERG': '$2', # Form Error General Flag
+ 'CANGIT_AERG': '$1', # Ackknowledgement Error General
+ 'CANGIE' : '$db', # CAN General Interrupt Enable R
+ 'CANGIE_ENIT': '$80', # Enable all Interrupts
+ 'CANGIE_ENBOFF': '$40', # Enable Bus Off Interrupt
+ 'CANGIE_ENRX': '$20', # Enable Receive Interrupt
+ 'CANGIE_ENTX': '$10', # Enable Transmitt Interrupt
+ 'CANGIE_ENERR': '$8', # Enable MOb Error Interrupt
+ 'CANGIE_ENBX': '$4', # Enable Burst Receive Interrupt
+ 'CANGIE_ENERG': '$2', # Enable General Error Interrupt
+ 'CANGIE_ENOVRT': '$1', # Enable CAN Timer Overrun Inter
+ 'CANEN2' : '$dc', # Enable MOb Register 2
+ 'CANEN2_ENMOB': '$3f', # Enable MObs
+ 'CANEN1' : '$dd', # Enable MOb Register 1(empty)
+ 'CANIE2' : '$de', # Enable Interrupt MOb Register
+ 'CANIE2_IEMOB': '$3f', # Interrupt Enable MObs
+ 'CANIE1' : '$df', # Enable Interrupt MOb Register
+ 'CANSIT2' : '$e0', # CAN Status Interrupt MOb Regis
+ 'CANSIT2_SIT': '$3f', # Status of Interrupt MObs
+ 'CANSIT1' : '$e1', # CAN Status Interrupt MOb Regis
+ 'CANBT1' : '$e2', # CAN Bit Timing Register 1
+ 'CANBT1_BRP': '$7e', # Baud Rate Prescaler bits
+ 'CANBT2' : '$e3', # CAN Bit Timing Register 2
+ 'CANBT2_SJW': '$60', # Re-Sync Jump Width bits
+ 'CANBT2_PRS': '$e', # Propagation Time Segment bits
+ 'CANBT3' : '$e4', # CAN Bit Timing Register 3
+ 'CANBT3_PHS2': '$70', # Phase Segment 2 bits
+ 'CANBT3_PHS1': '$e', # Phase Segment 1 bits
+ 'CANBT3_SMP': '$1', # Sample Type
+ 'CANTCON' : '$e5', # Timer Control Register
+ 'CANTIML' : '$e6', # Timer Register Low
+ 'CANTIMH' : '$e7', # Timer Register High
+ 'CANTTCL' : '$e8', # TTC Timer Register Low
+ 'CANTTCH' : '$e9', # TTC Timer Register High
+ 'CANTEC' : '$ea', # Transmit Error Counter Registe
+ 'CANREC' : '$eb', # Receive Error Counter Register
+ 'CANHPMOB' : '$ec', # Highest Priority MOb Register
+ 'CANHPMOB_HPMOB': '$f0', # Highest Priority MOb Number bi
+ 'CANHPMOB_CGP': '$f', # CAN General Purpose bits
+ 'CANPAGE' : '$ed', # Page MOb Register
+ 'CANPAGE_MOBNB': '$f0', # MOb Number bits
+ 'CANPAGE_AINC': '$8', # MOb Data Buffer Auto Increment
+ 'CANPAGE_INDX': '$7', # Data Buffer Index bits
+ 'CANSTMOB' : '$ee', # MOb Status Register
+ 'CANSTMOB_DLCW': '$80', # Data Length Code Warning on MO
+ 'CANSTMOB_TXOK': '$40', # Transmit OK on MOb
+ 'CANSTMOB_RXOK': '$20', # Receive OK on MOb
+ 'CANSTMOB_BERR': '$10', # Bit Error on MOb
+ 'CANSTMOB_SERR': '$8', # Stuff Error on MOb
+ 'CANSTMOB_CERR': '$4', # CRC Error on MOb
+ 'CANSTMOB_FERR': '$2', # Form Error on MOb
+ 'CANSTMOB_AERR': '$1', # Ackknowledgement Error on MOb
+ 'CANCDMOB' : '$ef', # MOb Control and DLC Register
+ 'CANCDMOB_CONMOB': '$c0', # MOb Config bits
+ 'CANCDMOB_RPLV': '$20', # Reply Valid
+ 'CANCDMOB_IDE': '$10', # Identifier Extension
+ 'CANCDMOB_DLC': '$f', # Data Length Code bits
+ 'CANIDT4' : '$f0', # Identifier Tag Register 4
+ 'CANIDT4_IDT': '$f8', #
+ 'CANIDT4_RTRTAG': '$4', #
+ 'CANIDT4_RB1TAG': '$2', #
+ 'CANIDT4_RB0TAG': '$1', #
+ 'CANIDT3' : '$f1', # Identifier Tag Register 3
+ 'CANIDT2' : '$f2', # Identifier Tag Register 2
+ 'CANIDT1' : '$f3', # Identifier Tag Register 1
+ 'CANIDM4' : '$f4', # Identifier Mask Register 4
+ 'CANIDM3' : '$f5', # Identifier Mask Register 3
+ 'CANIDM2' : '$f6', # Identifier Mask Register 2
+ 'CANIDM1' : '$f7', # Identifier Mask Register 1
+ 'CANSTML' : '$f8', # Time Stamp Register Low
+ 'CANSTMH' : '$f9', # Time Stamp Register High
+ 'CANMSG' : '$fa', # Message Data Register
+
+# Module ANALOG_COMPARATOR
+ 'AC0CON' : '$94', # Analog Comparator 0 Control Re
+ 'AC0CON_AC0EN': '$80', # Analog Comparator 0 Enable Bit
+ 'AC0CON_AC0IE': '$40', # Analog Comparator 0 Interrupt
+ 'AC0CON_AC0IS': '$30', # Analog Comparator 0 Interrupt
+ 'AC0CON_ACCKSEL': '$8', # Analog Comparator Clock Select
+ 'AC0CON_AC0M': '$7', # Analog Comparator 0 Multiplexe
+ 'AC1CON' : '$95', # Analog Comparator 1 Control Re
+ 'AC1CON_AC1EN': '$80', # Analog Comparator 1 Enable Bit
+ 'AC1CON_AC1IE': '$40', # Analog Comparator 1 Interrupt
+ 'AC1CON_AC1IS': '$30', # Analog Comparator 1 Interrupt
+ 'AC1CON_AC1ICE': '$8', # Analog Comparator 1 Interrupt
+ 'AC1CON_AC1M': '$7', # Analog Comparator 1 Multiplexe
+ 'AC2CON' : '$96', # Analog Comparator 2 Control Re
+ 'AC2CON_AC2EN': '$80', # Analog Comparator 2 Enable Bit
+ 'AC2CON_AC2IE': '$40', # Analog Comparator 2 Interrupt
+ 'AC2CON_AC2IS': '$30', # Analog Comparator 2 Interrupt
+ 'AC2CON_AC2M': '$7', # Analog Comparator 2 Multiplexe
+ 'AC3CON' : '$97', # Analog Comparator 3 Control Re
+ 'AC3CON_AC3EN': '$80', # Analog Comparator 3 Enable Bit
+ 'AC3CON_AC3IE': '$40', # Analog Comparator 3 Interrupt
+ 'AC3CON_AC3IS': '$30', # Analog Comparator 3 Interrupt
+ 'AC3CON_AC3M': '$7', # Analog Comparator 3 Multiplexe
+ 'ACSR' : '$50', # Analog Comparator Status Regis
+ 'ACSR_AC3IF': '$80', # Analog Comparator 3 Interrupt
+ 'ACSR_AC2IF': '$40', # Analog Comparator 2 Interrupt
+ 'ACSR_AC1IF': '$20', # Analog Comparator 1 Interrupt
+ 'ACSR_AC0IF': '$10', # Analog Comparator 0 Interrupt
+ 'ACSR_AC3O': '$8', # Analog Comparator 3 Output Bit
+ 'ACSR_AC2O': '$4', # Analog Comparator 2 Output Bit
+ 'ACSR_AC1O': '$2', # Analog Comparator 1 Output Bit
+ 'ACSR_AC0O': '$1', # Analog Comparator 0 Output Bit
+
+# Module DA_CONVERTER
+ 'DACH' : '$92', # DAC Data Register High Byte
+ 'DACH_DACH': '$ff', # DAC Data Register High Byte Bi
+ 'DACL' : '$91', # DAC Data Register Low Byte
+ 'DACL_DACL': '$ff', # DAC Data Register Low Byte Bit
+ 'DACON' : '$90', # DAC Control Register
+ 'DACON_DAATE': '$80', # DAC Auto Trigger Enable Bit
+ 'DACON_DATS': '$70', # DAC Trigger Selection Bits
+ 'DACON_DALA': '$4', # DAC Left Adjust
+ 'DACON_DAEN': '$1', # DAC Enable Bit
+
+# Module CPU
+ 'SPMCSR' : '$57', # Store Program Memory Control R
+ 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
+ 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
+ 'SPMCSR_SIGRD': '$20', # Signature Row Read
+ 'SPMCSR_RWWSRE': '$10', # Read While Write section read
+ 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
+ 'SPMCSR_PGWRT': '$4', # Page Write
+ 'SPMCSR_PGERS': '$2', # Page Erase
+ 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
+ 'SREG' : '$5f', # Status Register
+ 'SREG_I': '$80', # Global Interrupt Enable
+ 'SREG_T': '$40', # Bit Copy Storage
+ 'SREG_H': '$20', # Half Carry Flag
+ 'SREG_S': '$10', # Sign Bit
+ 'SREG_V': '$8', # Two's Complement Overflow Flag
+ 'SREG_N': '$4', # Negative Flag
+ 'SREG_Z': '$2', # Zero Flag
+ 'SREG_C': '$1', # Carry Flag
+ 'SP' : '$5d', # Stack Pointer
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_SPIPS': '$80', # SPI Pin Select
+ 'MCUCR_PUD': '$10', # Pull-up disable
+ 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
+ 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
+ 'MCUSR_BORF': '$4', # Brown-out Reset Flag
+ 'MCUSR_EXTRF': '$2', # External Reset Flag
+ 'MCUSR_PORF': '$1', # Power-on reset flag
+ 'OSCCAL' : '$66', # Oscillator Calibration Value
+ 'CLKPR' : '$61', #
+ 'CLKPR_CLKPCE': '$80', #
+ 'CLKPR_CLKPS': '$f', #
+ 'SMCR' : '$53', # Sleep Mode Control Register
+ 'SMCR_SM': '$e', # Sleep Mode Select bits
+ 'SMCR_SE': '$1', # Sleep Enable
+ 'GPIOR2' : '$3a', # General Purpose IO Register 2
+ 'GPIOR2_GPIOR': '$ff', # General Purpose IO Register 2
+ 'GPIOR1' : '$39', # General Purpose IO Register 1
+ 'GPIOR1_GPIOR': '$ff', # General Purpose IO Register 1
+ 'GPIOR0' : '$3e', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR07': '$80', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR06': '$40', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR05': '$20', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR04': '$10', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR03': '$8', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR02': '$4', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR01': '$2', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR00': '$1', # General Purpose IO Register 0
+ 'PLLCSR' : '$49', # PLL Control And Status Registe
+ 'PLLCSR_PLLF': '$4', # PLL Factor
+ 'PLLCSR_PLLE': '$2', # PLL Enable
+ 'PLLCSR_PLOCK': '$1', # PLL Lock Detector
+ 'PRR' : '$64', # Power Reduction Register
+ 'PRR_PRCAN': '$40', # Power Reduction CAN
+ 'PRR_PRPSC': '$20', # Power Reduction PSC
+ 'PRR_PRTIM1': '$10', # Power Reduction Timer/Counter1
+ 'PRR_PRTIM0': '$8', # Power Reduction Timer/Counter0
+ 'PRR_PRSPI': '$4', # Power Reduction Serial Periphe
+ 'PRR_PRLIN': '$2', # Power Reduction LIN UART
+ 'PRR_PRADC': '$1', # Power Reduction ADC
+
+# Module PORTE
+ 'PORTE' : '$2e', # Port E Data Register
+ 'DDRE' : '$2d', # Port E Data Direction Register
+ 'PINE' : '$2c', # Port E Input Pins
+
+# Module TIMER_COUNTER_0
+ 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
+ 'TIMSK0_OCIE0B': '$4', # Timer/Counter0 Output Compare
+ 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
+ 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
+ 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
+ 'TIFR0_OCF0B': '$4', # Timer/Counter0 Output Compare
+ 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
+ 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
+ 'TCCR0A' : '$44', # Timer/Counter Control Registe
+ 'TCCR0A_COM0A': '$c0', # Compare Output Mode, Phase Cor
+ 'TCCR0A_COM0B': '$30', # Compare Output Mode, Fast PWm
+ 'TCCR0A_WGM0': '$3', # Waveform Generation Mode
+ 'TCCR0B' : '$45', # Timer/Counter Control Register
+ 'TCCR0B_FOC0A': '$80', # Force Output Compare A
+ 'TCCR0B_FOC0B': '$40', # Force Output Compare B
+ 'TCCR0B_WGM02': '$8', #
+ 'TCCR0B_CS0': '$7', # Clock Select
+ 'TCNT0' : '$46', # Timer/Counter0
+ 'OCR0A' : '$47', # Timer/Counter0 Output Compare
+ 'OCR0B' : '$48', # Timer/Counter0 Output Compare
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_ICPSEL1': '$40', # Timer1 Input Capture Selection
+ 'GTCCR_PSR10': '$1', # Prescaler Reset Timer/Counter1
+
+# Module TIMER_COUNTER_1
+ 'TIMSK1' : '$6f', # Timer/Counter Interrupt Mask R
+ 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
+ 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output CompareB
+ 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output CompareA
+ 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
+ 'TIFR1' : '$36', # Timer/Counter Interrupt Flag r
+ 'TIFR1_ICF1': '$20', # Input Capture Flag 1
+ 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
+ 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
+ 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
+ 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
+ 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
+ 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
+ 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
+ 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
+ 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
+ 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
+ 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
+ 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
+ 'TCCR1C' : '$82', # Timer/Counter1 Control Registe
+ 'TCCR1C_FOC1A': '$80', #
+ 'TCCR1C_FOC1B': '$40', #
+ 'TCNT1' : '$84', # Timer/Counter1 Bytes
+ 'OCR1A' : '$88', # Timer/Counter1 Output Compare
+ 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
+ 'ICR1' : '$86', # Timer/Counter1 Input Capture R
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSRSYNC': '$1', # Prescaler Reset Timer/Counter1
+
+# Module AD_CONVERTER
+ 'ADMUX' : '$7c', # The ADC multiplexer Selection
+ 'ADMUX_REFS': '$c0', # Reference Selection Bits
+ 'ADMUX_ADLAR': '$20', # Left Adjust Result
+ 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
+ 'ADCSRA' : '$7a', # The ADC Control and Status reg
+ 'ADCSRA_ADEN': '$80', # ADC Enable
+ 'ADCSRA_ADSC': '$40', # ADC Start Conversion
+ 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
+ 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
+ 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
+ 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
+ 'ADC' : '$78', # ADC Data Register Bytes
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ADHSM': '$80', # ADC High Speed Mode
+ 'ADCSRB_ISRCEN': '$40', # Current Source Enable
+ 'ADCSRB_AREFEN': '$20', # Analog Reference pin Enable
+ 'ADCSRB_ADTS': '$f', # ADC Auto Trigger Sources
+ 'DIDR0' : '$7e', # Digital Input Disable Register
+ 'DIDR0_ADC7D': '$80', # ADC7 Digital input Disable
+ 'DIDR0_ADC6D': '$40', # ADC6 Digital input Disable
+ 'DIDR0_ADC5D': '$20', # ADC5 Digital input Disable
+ 'DIDR0_ADC4D': '$10', # ADC4 Digital input Disable
+ 'DIDR0_ADC3D': '$8', # ADC3 Digital input Disable
+ 'DIDR0_ADC2D': '$4', # ADC2 Digital input Disable
+ 'DIDR0_ADC1D': '$2', # ADC1 Digital input Disable
+ 'DIDR0_ADC0D': '$1', # ADC0 Digital input Disable
+ 'DIDR1' : '$7f', # Digital Input Disable Register
+ 'DIDR1_AMP2PD': '$40', # AMP2P Pin Digital input Disabl
+ 'DIDR1_ACMP0D': '$20', # ACMP0 Pin Digital input Disabl
+ 'DIDR1_AMP0PD': '$10', # AMP0P Pin Digital input Disabl
+ 'DIDR1_AMP0ND': '$8', # AMP0N Pin Digital input Disabl
+ 'DIDR1_ADC10D': '$4', # ADC10 Pin Digital input Disabl
+ 'DIDR1_ADC9D': '$2', # ADC9 Pin Digital input Disable
+ 'DIDR1_ADC8D': '$1', # ADC8 Pin Digital input Disable
+ 'AMP0CSR' : '$75', #
+ 'AMP0CSR_AMP0EN': '$80', #
+ 'AMP0CSR_AMP0IS': '$40', #
+ 'AMP0CSR_AMP0G': '$30', #
+ 'AMP0CSR_AMPCMP0': '$8', # Amplifier 0 - Comparator 0 Con
+ 'AMP0CSR_AMP0TS': '$7', #
+ 'AMP1CSR' : '$76', #
+ 'AMP1CSR_AMP1EN': '$80', #
+ 'AMP1CSR_AMP1IS': '$40', #
+ 'AMP1CSR_AMP1G': '$30', #
+ 'AMP1CSR_AMPCMP1': '$8', # Amplifier 1 - Comparator 1 Con
+ 'AMP1CSR_AMP1TS': '$7', #
+ 'AMP2CSR' : '$77', #
+ 'AMP2CSR_AMP2EN': '$80', #
+ 'AMP2CSR_AMP2IS': '$40', #
+ 'AMP2CSR_AMP2G': '$30', #
+ 'AMP2CSR_AMPCMP2': '$8', # Amplifier 2 - Comparator 2 Con
+ 'AMP2CSR_AMP2TS': '$7', #
+
+# Module LINUART
+ 'LINCR' : '$c8', # LIN Control Register
+ 'LINCR_LSWRES': '$80', # Software Reset
+ 'LINCR_LIN13': '$40', # LIN Standard
+ 'LINCR_LCONF': '$30', # LIN Configuration bits
+ 'LINCR_LENA': '$8', # LIN or UART Enable
+ 'LINCR_LCMD': '$7', # LIN Command and Mode bits
+ 'LINSIR' : '$c9', # LIN Status and Interrupt Regis
+ 'LINSIR_LIDST': '$e0', # Identifier Status bits
+ 'LINSIR_LBUSY': '$10', # Busy Signal
+ 'LINSIR_LERR': '$8', # Error Interrupt
+ 'LINSIR_LIDOK': '$4', # Identifier Interrupt
+ 'LINSIR_LTXOK': '$2', # Transmit Performed Interrupt
+ 'LINSIR_LRXOK': '$1', # Receive Performed Interrupt
+ 'LINENIR' : '$ca', # LIN Enable Interrupt Register
+ 'LINENIR_LENERR': '$8', # Enable Error Interrupt
+ 'LINENIR_LENIDOK': '$4', # Enable Identifier Interrupt
+ 'LINENIR_LENTXOK': '$2', # Enable Transmit Performed Inte
+ 'LINENIR_LENRXOK': '$1', # Enable Receive Performed Inter
+ 'LINERR' : '$cb', # LIN Error Register
+ 'LINERR_LABORT': '$80', # Abort Flag
+ 'LINERR_LTOERR': '$40', # Frame Time Out Error Flag
+ 'LINERR_LOVERR': '$20', # Overrun Error Flag
+ 'LINERR_LFERR': '$10', # Framing Error Flag
+ 'LINERR_LSERR': '$8', # Synchronization Error Flag
+ 'LINERR_LPERR': '$4', # Parity Error Flag
+ 'LINERR_LCERR': '$2', # Checksum Error Flag
+ 'LINERR_LBERR': '$1', # Bit Error Flag
+ 'LINBTR' : '$cc', # LIN Bit Timing Register
+ 'LINBTR_LDISR': '$80', # Disable Bit Timing Resynchroni
+ 'LINBTR_LBT': '$3f', # LIN Bit Timing bits
+ 'LINBRRL' : '$cd', # LIN Baud Rate Low Register
+ 'LINBRRL_LDIV': '$ff', #
+ 'LINBRRH' : '$ce', # LIN Baud Rate High Register
+ 'LINBRRH_LDIV': '$f', #
+ 'LINDLR' : '$cf', # LIN Data Length Register
+ 'LINDLR_LTXDL': '$f0', # LIN Transmit Data Length bits
+ 'LINDLR_LRXDL': '$f', # LIN Receive Data Length bits
+ 'LINIDR' : '$d0', # LIN Identifier Register
+ 'LINIDR_LP': '$c0', # Parity bits
+ 'LINIDR_LID': '$3f', # Identifier bit 5 or Data Lengt
+ 'LINSEL' : '$d1', # LIN Data Buffer Selection Regi
+ 'LINSEL_LAINC': '$8', # Auto Increment of Data Buffer
+ 'LINSEL_LINDX': '$7', # FIFO LIN Data Buffer Index bit
+ 'LINDAT' : '$d2', # LIN Data Register
+ 'LINDAT_LDATA': '$ff', #
+
+# Module SPI
+ 'SPCR' : '$4c', # SPI Control Register
+ 'SPCR_SPIE': '$80', # SPI Interrupt Enable
+ 'SPCR_SPE': '$40', # SPI Enable
+ 'SPCR_DORD': '$20', # Data Order
+ 'SPCR_MSTR': '$10', # Master/Slave Select
+ 'SPCR_CPOL': '$8', # Clock polarity
+ 'SPCR_CPHA': '$4', # Clock Phase
+ 'SPCR_SPR': '$3', # SPI Clock Rate Selects
+ 'SPSR' : '$4d', # SPI Status Register
+ 'SPSR_SPIF': '$80', # SPI Interrupt Flag
+ 'SPSR_WCOL': '$40', # Write Collision Flag
+ 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
+ 'SPDR' : '$4e', # SPI Data Register
+
+# Module WATCHDOG
+ 'WDTCSR' : '$60', # Watchdog Timer Control Registe
+ 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
+ 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
+ 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
+ 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
+ 'WDTCSR_WDE': '$8', # Watch Dog Enable
+
+# Module EXTERNAL_INTERRUPT
+ 'EICRA' : '$69', # External Interrupt Control Reg
+ 'EICRA_ISC3': '$c0', # External Interrupt Sense Contr
+ 'EICRA_ISC2': '$30', # External Interrupt Sense Contr
+ 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
+ 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
+ 'EIMSK' : '$3d', # External Interrupt Mask Regist
+ 'EIMSK_INT': '$f', # External Interrupt Request 3 E
+ 'EIFR' : '$3c', # External Interrupt Flag Regist
+ 'EIFR_INTF': '$f', # External Interrupt Flags
+ 'PCICR' : '$68', # Pin Change Interrupt Control R
+ 'PCICR_PCIE': '$f', # Pin Change Interrupt Enables
+ 'PCMSK3' : '$6d', # Pin Change Mask Register 3
+ 'PCMSK3_PCINT': '$7', # Pin Change Enable Masks
+ 'PCMSK2' : '$6c', # Pin Change Mask Register 2
+ 'PCMSK2_PCINT': '$ff', # Pin Change Enable Masks
+ 'PCMSK1' : '$6b', # Pin Change Mask Register 1
+ 'PCMSK1_PCINT': '$ff', # Pin Change Enable Masks
+ 'PCMSK0' : '$6a', # Pin Change Mask Register 0
+ 'PCMSK0_PCINT': '$ff', # Pin Change Enable Masks
+ 'PCIFR' : '$3b', # Pin Change Interrupt Flag Regi
+ 'PCIFR_PCIF': '$f', # Pin Change Interrupt Flags
+
+# Module EEPROM
+ 'EEAR' : '$41', # EEPROM Read/Write Access
+ 'EEDR' : '$40', # EEPROM Data Register
+ 'EECR' : '$3f', # EEPROM Control Register
+ 'EECR_EEPM': '$30', #
+ 'EECR_EERIE': '$8', # EEProm Ready Interrupt Enable
+ 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
+ 'EECR_EEWE': '$2', # EEPROM Write Enable
+ 'EECR_EERE': '$1', # EEPROM Read Enable
+
+# Module PSC
+ 'PIFR' : '$bc', # PSC Interrupt Flag Register
+ 'PIFR_PEV': '$e', # PSC External Event 2 Interrupt
+ 'PIFR_PEOP': '$1', # PSC End of Cycle Interrupt
+ 'PIM' : '$bb', # PSC Interrupt Mask Register
+ 'PIM_PEVE': '$e', # External Event 2 Interrupt Ena
+ 'PIM_PEOPE': '$1', # PSC End of Cycle Interrupt Ena
+ 'PMIC2' : '$ba', # PSC Module 2 Input Control Reg
+ 'PMIC2_POVEN2': '$80', # PSC Module 2 Overlap Enable
+ 'PMIC2_PISEL2': '$40', # PSC Module 2 Input Select
+ 'PMIC2_PELEV2': '$20', # PSC Module 2 Input Level Selec
+ 'PMIC2_PFLTE2': '$10', # PSC Module 2 Input Filter Enab
+ 'PMIC2_PAOC2': '$8', # PSC Module 2 Asynchronous Outp
+ 'PMIC2_PRFM2': '$7', # PSC Module 2 Input Mode bits
+ 'PMIC1' : '$b9', # PSC Module 1 Input Control Reg
+ 'PMIC1_POVEN1': '$80', # PSC Module 1 Overlap Enable
+ 'PMIC1_PISEL1': '$40', # PSC Module 1 Input Select
+ 'PMIC1_PELEV1': '$20', # PSC Module 1 Input Level Selec
+ 'PMIC1_PFLTE1': '$10', # PSC Module 1 Input Filter Enab
+ 'PMIC1_PAOC1': '$8', # PSC Module 1 Asynchronous Outp
+ 'PMIC1_PRFM1': '$7', # PSC Module 1 Input Mode bits
+ 'PMIC0' : '$b8', # PSC Module 0 Input Control Reg
+ 'PMIC0_POVEN0': '$80', # PSC Module 0 Overlap Enable
+ 'PMIC0_PISEL0': '$40', # PSC Module 0 Input Select
+ 'PMIC0_PELEV0': '$20', # PSC Module 0 Input Level Selec
+ 'PMIC0_PFLTE0': '$10', # PSC Module 0 Input Filter Enab
+ 'PMIC0_PAOC0': '$8', # PSC Module 0 Asynchronous Outp
+ 'PMIC0_PRFM0': '$7', # PSC Module 0 Input Mode bits
+ 'PCTL' : '$b7', # PSC Control Register
+ 'PCTL_PPRE': '$c0', # PSC Prescaler Select bits
+ 'PCTL_PCLKSEL': '$20', # PSC Input Clock Select
+ 'PCTL_PCCYC': '$2', # PSC Complete Cycle
+ 'PCTL_PRUN': '$1', # PSC Run
+ 'POC' : '$b6', # PSC Output Configuration
+ 'POC_POEN2B': '$20', # PSC Output 2B Enable
+ 'POC_POEN2A': '$10', # PSC Output 2A Enable
+ 'POC_POEN1B': '$8', # PSC Output 1B Enable
+ 'POC_POEN1A': '$4', # PSC Output 1A Enable
+ 'POC_POEN0B': '$2', # PSC Output 0B Enable
+ 'POC_POEN0A': '$1', # PSC Output 0A Enable
+ 'PCNF' : '$b5', # PSC Configuration Register
+ 'PCNF_PULOCK': '$20', # PSC Update Lock
+ 'PCNF_PMODE': '$10', # PSC Mode
+ 'PCNF_POPB': '$8', # PSC Output B Polarity
+ 'PCNF_POPA': '$4', # PSC Output A Polarity
+ 'PSYNC' : '$b4', # PSC Synchro Configuration
+ 'PSYNC_PSYNC2': '$30', # Selection of Synchronization O
+ 'PSYNC_PSYNC1': '$c', # Selection of Synchronization O
+ 'PSYNC_PSYNC0': '$3', # Selection of Synchronization O
+ 'POCR_RB' : '$b2', # PSC Output Compare RB Register
+ 'POCR2SB' : '$b0', # PSC Module 2 Output Compare SB
+ 'POCR2RA' : '$ae', # PSC Module 2 Output Compare RA
+ 'POCR2SA' : '$ac', # PSC Module 2 Output Compare SA
+ 'POCR1SB' : '$aa', # PSC Module 1 Output Compare SB
+ 'POCR1RA' : '$a8', # PSC Module 1 Output Compare RA
+ 'POCR1SA' : '$a6', # PSC Output Compare SA Register
+ 'POCR0SB' : '$a4', # PSC Output Compare SB Register
+ 'POCR0RA' : '$a2', # PSC Module 0 Output Compare RA
+ 'POCR0SA' : '$a0', # PSC Module 0 Output Compare SA
+
+ '__amforth_dummy':'0'
+}
diff --git a/amforth-6.5/avr8/devices/atmega32m1/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega32m1/words/no-jtag.asm
new file mode 100644
index 0000000..352a4bb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega32m1/words/no-jtag.asm
@@ -0,0 +1,14 @@
+; ( -- )
+; ( -- )
+; MCU
+; disable jtag at runtime
+VE_NOJTAG:
+ .dw $FF05
+ .db "-jtag",0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOJTAG
+XT_NOJTAG:
+ .dw PFA_NOJTAG
+PFA_NOJTAG:
+
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega32m1/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega32m1/words/no-wdt.asm
new file mode 100644
index 0000000..ff6ddd1
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega32m1/words/no-wdt.asm
@@ -0,0 +1,34 @@
+; ( -- )
+; MCU
+; disable watch dog timer at runtime
+VE_NOWDT:
+ .dw $ff04
+ .db "-wdt"
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOWDT
+XT_NOWDT:
+ .dw PFA_NOWDT
+PFA_NOWDT:
+
+ in temp1,SREG
+ push temp1
+ ; Turn always off global interrupt.
+ cli
+ ; Reset Watchdog Timer
+ wdr
+ ; Clear WDRF in MCUSR
+ in temp1, MCUSR
+ andi temp1, (0xff & (0<<WDRF))
+ out MCUSR, temp1
+ ; Write logical one to WDCE and WDE
+ ; Keep old prescaler setting to prevent unintentional time-out
+ in_ temp1, WDTCSR
+ ori temp1, (1<<WDCE) | (1<<WDE)
+ out_ WDTCSR, temp1
+ ; Turn off WDT
+ ldi temp1, (0<<WDE)
+ out_ WDTCSR, temp1
+ ; restore status register
+ pop temp1
+ out SREG,temp1
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega32m1/words/sleep.asm b/amforth-6.5/avr8/devices/atmega32m1/words/sleep.asm
new file mode 100644
index 0000000..256249c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega32m1/words/sleep.asm
@@ -0,0 +1,19 @@
+; ( mode -- )
+; MCU
+; put the controller into the specified sleep mode
+VE_SLEEP:
+ .dw $ff05
+ .db "sleep", 0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_SLEEP
+XT_SLEEP:
+ .dw PFA_SLEEP
+PFA_SLEEP:
+ andi tosl, 7 ; leave only legal mode bits
+ lsl tosl ; move to correct location (bits 3-1)
+ ori tosl, 1 ; set the SE bit
+ out_ SMCR, tosl ; set the sleep config
+ sleep ; nighty-night
+ out_ SMCR, zerol ; 0 protects against accidental sleeps
+ loadtos ; pop argument from stack
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega32u2/atmega32u2.frt b/amforth-6.5/avr8/devices/atmega32u2/atmega32u2.frt
new file mode 100644
index 0000000..05038dd
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega32u2/atmega32u2.frt
@@ -0,0 +1,367 @@
+\ Partname: ATmega32U2
+\ generated automatically
+
+\ PORTB
+&37 constant PORTB \ Port B Data Register
+&36 constant DDRB \ Port B Data Direction Register
+&35 constant PINB \ Port B Input Pins
+\ PORTD
+&43 constant PORTD \ Port D Data Register
+&42 constant DDRD \ Port D Data Direction Register
+&41 constant PIND \ Port D Input Pins
+\ SPI
+&76 constant SPCR \ SPI Control Register
+ $80 constant SPCR_SPIE \ SPI Interrupt Enable
+ $40 constant SPCR_SPE \ SPI Enable
+ $20 constant SPCR_DORD \ Data Order
+ $10 constant SPCR_MSTR \ Master/Slave Select
+ $08 constant SPCR_CPOL \ Clock polarity
+ $04 constant SPCR_CPHA \ Clock Phase
+ $03 constant SPCR_SPR \ SPI Clock Rate Selects
+&77 constant SPSR \ SPI Status Register
+ $80 constant SPSR_SPIF \ SPI Interrupt Flag
+ $40 constant SPSR_WCOL \ Write Collision Flag
+ $01 constant SPSR_SPI2X \ Double SPI Speed Bit
+&78 constant SPDR \ SPI Data Register
+\ BOOT_LOAD
+&87 constant SPMCSR \ Store Program Memory Control Register
+ $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
+ $20 constant SPMCSR_SIGRD \ Signature Row Read
+ $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
+ $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
+ $04 constant SPMCSR_PGWRT \ Page Write
+ $02 constant SPMCSR_PGERS \ Page Erase
+ $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
+\ EEPROM
+&65 constant EEAR \ EEPROM Address Register Low Bytes
+&64 constant EEDR \ EEPROM Data Register
+&63 constant EECR \ EEPROM Control Register
+ $30 constant EECR_EEPM \ EEPROM Programming Mode Bits
+ $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
+ $04 constant EECR_EEMPE \ EEPROM Master Write Enable
+ $02 constant EECR_EEPE \ EEPROM Write Enable
+ $01 constant EECR_EERE \ EEPROM Read Enable
+\ TIMER_COUNTER_0
+&72 constant OCR0B \ Timer/Counter0 Output Compare Register
+&71 constant OCR0A \ Timer/Counter0 Output Compare Register
+&70 constant TCNT0 \ Timer/Counter0
+&69 constant TCCR0B \ Timer/Counter Control Register B
+ $80 constant TCCR0B_FOC0A \ Force Output Compare A
+ $40 constant TCCR0B_FOC0B \ Force Output Compare B
+ $08 constant TCCR0B_WGM02 \
+ $07 constant TCCR0B_CS0 \ Clock Select
+&68 constant TCCR0A \ Timer/Counter Control Register A
+ $C0 constant TCCR0A_COM0A \ Compare Output Mode, Phase Correct PWM Mode
+ $30 constant TCCR0A_COM0B \ Compare Output Mode, Fast PWm
+ $03 constant TCCR0A_WGM0 \ Waveform Generation Mode
+&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
+ $04 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare Match B Interrupt Enable
+ $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match A Interrupt Enable
+ $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
+&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
+ $04 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare Flag 0B
+ $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0A
+ $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
+&67 constant GTCCR \ General Timer/Counter Control Register
+ $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
+ $01 constant GTCCR_PSRSYNC \ Prescaler Reset Timer/Counter1 and Timer/Counter0
+\ TIMER_COUNTER_1
+&128 constant TCCR1A \ Timer/Counter1 Control Register A
+ $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
+ $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
+ $0C constant TCCR1A_COM1C \ Compare Output Mode 1C, bits
+ $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
+&129 constant TCCR1B \ Timer/Counter1 Control Register B
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
+ $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
+&130 constant TCCR1C \ Timer/Counter 1 Control Register C
+ $80 constant TCCR1C_FOC1A \ Force Output Compare 1A
+ $40 constant TCCR1C_FOC1B \ Force Output Compare 1B
+ $20 constant TCCR1C_FOC1C \ Force Output Compare 1C
+&132 constant TCNT1 \ Timer/Counter1 Bytes
+&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
+&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
+&140 constant OCR1C \ Timer/Counter1 Output Compare Register C Bytes
+&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
+&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
+ $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
+ $08 constant TIMSK1_OCIE1C \ Timer/Counter1 Output Compare C Match Interrupt Enable
+ $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
+ $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
+ $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
+&54 constant TIFR1 \ Timer/Counter1 Interrupt Flag register
+ $20 constant TIFR1_ICF1 \ Input Capture Flag 1
+ $08 constant TIFR1_OCF1C \ Output Compare Flag 1C
+ $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
+ $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
+ $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
+\ PLL
+&73 constant PLLCSR \ PLL Status and Control register
+ $1C constant PLLCSR_PLLP \ PLL prescaler Bits
+ $02 constant PLLCSR_PLLE \ PLL Enable Bit
+ $01 constant PLLCSR_PLOCK \ PLL Lock Status Bit
+\ USB_DEVICE
+&244 constant UEINT \
+&242 constant UEBCLX \
+&241 constant UEDATX \
+&240 constant UEIENX \
+ $80 constant UEIENX_FLERRE \
+ $40 constant UEIENX_NAKINE \
+ $10 constant UEIENX_NAKOUTE \
+ $08 constant UEIENX_RXSTPE \
+ $04 constant UEIENX_RXOUTE \
+ $02 constant UEIENX_STALLEDE \
+ $01 constant UEIENX_TXINE \
+&239 constant UESTA1X \
+ $04 constant UESTA1X_CTRLDIR \
+ $03 constant UESTA1X_CURRBK \
+&238 constant UESTA0X \
+ $80 constant UESTA0X_CFGOK \
+ $40 constant UESTA0X_OVERFI \
+ $20 constant UESTA0X_UNDERFI \
+ $0C constant UESTA0X_DTSEQ \
+ $03 constant UESTA0X_NBUSYBK \
+&237 constant UECFG1X \
+ $70 constant UECFG1X_EPSIZE \
+ $0C constant UECFG1X_EPBK \
+ $02 constant UECFG1X_ALLOC \
+&236 constant UECFG0X \
+ $C0 constant UECFG0X_EPTYPE \
+ $01 constant UECFG0X_EPDIR \
+&235 constant UECONX \
+ $20 constant UECONX_STALLRQ \
+ $10 constant UECONX_STALLRQC \
+ $08 constant UECONX_RSTDT \
+ $01 constant UECONX_EPEN \
+&234 constant UERST \
+ $1F constant UERST_EPRST \
+&233 constant UENUM \
+&232 constant UEINTX \
+ $80 constant UEINTX_FIFOCON \
+ $40 constant UEINTX_NAKINI \
+ $20 constant UEINTX_RWAL \
+ $10 constant UEINTX_NAKOUTI \
+ $08 constant UEINTX_RXSTPI \
+ $04 constant UEINTX_RXOUTI \
+ $02 constant UEINTX_STALLEDI \
+ $01 constant UEINTX_TXINI \
+&230 constant UDMFN \
+ $10 constant UDMFN_FNCERR \
+&228 constant UDFNUM \
+&227 constant UDADDR \
+ $80 constant UDADDR_ADDEN \
+ $7F constant UDADDR_UADD \
+&226 constant UDIEN \
+ $40 constant UDIEN_UPRSME \
+ $20 constant UDIEN_EORSME \
+ $10 constant UDIEN_WAKEUPE \
+ $08 constant UDIEN_EORSTE \
+ $04 constant UDIEN_SOFE \
+ $01 constant UDIEN_SUSPE \
+&225 constant UDINT \
+ $40 constant UDINT_UPRSMI \
+ $20 constant UDINT_EORSMI \
+ $10 constant UDINT_WAKEUPI \
+ $08 constant UDINT_EORSTI \
+ $04 constant UDINT_SOFI \
+ $01 constant UDINT_SUSPI \
+&224 constant UDCON \
+ $04 constant UDCON_RSTCPU \
+ $02 constant UDCON_RMWKUP \
+ $01 constant UDCON_DETACH \
+&216 constant USBCON \ USB General Control Register
+ $80 constant USBCON_USBE \
+ $20 constant USBCON_FRZCLK \
+&99 constant REGCR \ Regulator Control Register
+ $01 constant REGCR_REGDIS \
+\ PS2
+&251 constant UPOE \
+ $C0 constant UPOE_UPWE \
+ $30 constant UPOE_UPDRV \
+ $08 constant UPOE_SCKI \
+ $04 constant UPOE_DATAI \
+ $02 constant UPOE_DPI \
+ $01 constant UPOE_DMI \
+&250 constant PS2CON \ PS2 Pad Enable register
+ $01 constant PS2CON_PS2EN \ Enable
+\ CPU
+&95 constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ $08 constant SREG_V \ Two's Complement Overflow Flag
+ $04 constant SREG_N \ Negative Flag
+ $02 constant SREG_Z \ Zero Flag
+ $01 constant SREG_C \ Carry Flag
+&93 constant SP \ Stack Pointer
+&85 constant MCUCR \ MCU Control Register
+ $10 constant MCUCR_PUD \ Pull-up disable
+ $02 constant MCUCR_IVSEL \ Interrupt Vector Select
+ $01 constant MCUCR_IVCE \ Interrupt Vector Change Enable
+&84 constant MCUSR \ MCU Status Register
+ $20 constant MCUSR_USBRF \ USB reset flag
+ $08 constant MCUSR_WDRF \ Watchdog Reset Flag
+ $04 constant MCUSR_BORF \ Brown-out Reset Flag
+ $02 constant MCUSR_EXTRF \ External Reset Flag
+ $01 constant MCUSR_PORF \ Power-on reset flag
+&102 constant OSCCAL \ Oscillator Calibration Value
+&97 constant CLKPR \
+ $80 constant CLKPR_CLKPCE \
+ $0F constant CLKPR_CLKPS \
+&83 constant SMCR \ Sleep Mode Control Register
+ $0E constant SMCR_SM \ Sleep Mode Select bits
+ $01 constant SMCR_SE \ Sleep Enable
+&92 constant EIND \ Extended Indirect Register
+&75 constant GPIOR2 \ General Purpose IO Register 2
+ $FF constant GPIOR2_GPIOR \ General Purpose IO Register 2 bis
+&74 constant GPIOR1 \ General Purpose IO Register 1
+ $FF constant GPIOR1_GPIOR \ General Purpose IO Register 1 bis
+&62 constant GPIOR0 \ General Purpose IO Register 0
+ $80 constant GPIOR0_GPIOR07 \ General Purpose IO Register 0 bit 7
+ $40 constant GPIOR0_GPIOR06 \ General Purpose IO Register 0 bit 6
+ $20 constant GPIOR0_GPIOR05 \ General Purpose IO Register 0 bit 5
+ $10 constant GPIOR0_GPIOR04 \ General Purpose IO Register 0 bit 4
+ $08 constant GPIOR0_GPIOR03 \ General Purpose IO Register 0 bit 3
+ $04 constant GPIOR0_GPIOR02 \ General Purpose IO Register 0 bit 2
+ $02 constant GPIOR0_GPIOR01 \ General Purpose IO Register 0 bit 1
+ $01 constant GPIOR0_GPIOR00 \ General Purpose IO Register 0 bit 0
+&101 constant PRR1 \ Power Reduction Register1
+ $80 constant PRR1_PRUSB \ Power Reduction USB
+ $01 constant PRR1_PRUSART1 \ Power Reduction USART1
+&100 constant PRR0 \ Power Reduction Register0
+ $20 constant PRR0_PRTIM0 \ Power Reduction Timer/Counter0
+ $08 constant PRR0_PRTIM1 \ Power Reduction Timer/Counter1
+ $04 constant PRR0_PRSPI \ Power Reduction Serial Peripheral Interface
+&210 constant CLKSTA \
+ $02 constant CLKSTA_RCON \
+ $01 constant CLKSTA_EXTON \
+&209 constant CLKSEL1 \
+ $F0 constant CLKSEL1_RCCKSEL \
+ $0F constant CLKSEL1_EXCKSEL \
+&208 constant CLKSEL0 \
+ $C0 constant CLKSEL0_RCSUT \
+ $30 constant CLKSEL0_EXSUT \
+ $08 constant CLKSEL0_RCE \
+ $04 constant CLKSEL0_EXTE \
+ $01 constant CLKSEL0_CLKS \
+&81 constant DWDR \ debugWire communication register
+\ EXTERNAL_INTERRUPT
+&105 constant EICRA \ External Interrupt Control Register A
+ $C0 constant EICRA_ISC3 \ External Interrupt Sense Control Bit
+ $30 constant EICRA_ISC2 \ External Interrupt Sense Control Bit
+ $0C constant EICRA_ISC1 \ External Interrupt Sense Control Bit
+ $03 constant EICRA_ISC0 \ External Interrupt Sense Control Bit
+&106 constant EICRB \ External Interrupt Control Register B
+ $C0 constant EICRB_ISC7 \ External Interrupt 7-4 Sense Control Bit
+ $30 constant EICRB_ISC6 \ External Interrupt 7-4 Sense Control Bit
+ $0C constant EICRB_ISC5 \ External Interrupt 7-4 Sense Control Bit
+ $03 constant EICRB_ISC4 \ External Interrupt 7-4 Sense Control Bit
+&61 constant EIMSK \ External Interrupt Mask Register
+ $FF constant EIMSK_INT \ External Interrupt Request 7 Enable
+&60 constant EIFR \ External Interrupt Flag Register
+ $FF constant EIFR_INTF \ External Interrupt Flags
+&107 constant PCMSK0 \ Pin Change Mask Register 0
+ $FF constant PCMSK0_PCINT \ Pin Change Enable Masks
+&108 constant PCMSK1 \ Pin Change Mask Register 1
+ $1F constant PCMSK1_PCINT \
+&59 constant PCIFR \ Pin Change Interrupt Flag Register
+ $03 constant PCIFR_PCIF \ Pin Change Interrupt Flags
+&104 constant PCICR \ Pin Change Interrupt Control Register
+ $03 constant PCICR_PCIE \ Pin Change Interrupt Enables
+\ USART1
+&206 constant UDR1 \ USART I/O Data Register
+&200 constant UCSR1A \ USART Control and Status Register A
+ $80 constant UCSR1A_RXC1 \ USART Receive Complete
+ $40 constant UCSR1A_TXC1 \ USART Transmitt Complete
+ $20 constant UCSR1A_UDRE1 \ USART Data Register Empty
+ $10 constant UCSR1A_FE1 \ Framing Error
+ $08 constant UCSR1A_DOR1 \ Data overRun
+ $04 constant UCSR1A_UPE1 \ Parity Error
+ $02 constant UCSR1A_U2X1 \ Double the USART transmission speed
+ $01 constant UCSR1A_MPCM1 \ Multi-processor Communication Mode
+&201 constant UCSR1B \ USART Control and Status Register B
+ $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable
+ $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable
+ $20 constant UCSR1B_UDRIE1 \ USART Data register Empty Interrupt Enable
+ $10 constant UCSR1B_RXEN1 \ Receiver Enable
+ $08 constant UCSR1B_TXEN1 \ Transmitter Enable
+ $04 constant UCSR1B_UCSZ12 \ Character Size
+ $02 constant UCSR1B_RXB81 \ Receive Data Bit 8
+ $01 constant UCSR1B_TXB81 \ Transmit Data Bit 8
+&202 constant UCSR1C \ USART Control and Status Register C
+ $C0 constant UCSR1C_UMSEL1 \ USART Mode Select
+ $30 constant UCSR1C_UPM1 \ Parity Mode Bits
+ $08 constant UCSR1C_USBS1 \ Stop Bit Select
+ $06 constant UCSR1C_UCSZ1 \ Character Size
+ $01 constant UCSR1C_UCPOL1 \ Clock Polarity
+&203 constant UCSR1D \ USART Control and Status Register D
+ $02 constant UCSR1D_CTSEN \ CTS Enable
+ $01 constant UCSR1D_RTSEN \ RTS Enable
+&204 constant UBRR1 \ USART Baud Rate Register Bytes
+\ WATCHDOG
+&96 constant WDTCSR \ Watchdog Timer Control Register
+ $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Flag
+ $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Enable
+ $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
+ $10 constant WDTCSR_WDCE \ Watchdog Change Enable
+ $08 constant WDTCSR_WDE \ Watch Dog Enable
+&98 constant WDTCKD \ Watchdog Timer Clock Divider
+ $08 constant WDTCKD_WDEWIF \ Watchdog Early Warning Interrupt Flag
+ $04 constant WDTCKD_WDEWIE \ Watchdog Early Warning Interrupt Enable
+ $03 constant WDTCKD_WCLKD \ Watchdog Timer Clock Dividers
+\ ANALOG_COMPARATOR
+&80 constant ACSR \ Analog Comparator Control And Status Register
+ $80 constant ACSR_ACD \ Analog Comparator Disable
+ $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
+ $20 constant ACSR_ACO \ Analog Compare Output
+ $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
+ $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
+ $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
+ $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
+&127 constant DIDR1 \
+ $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
+ $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
+\ PORTC
+&40 constant PORTC \ Port C Data Register
+ $F0 constant PORTC_PORTC \ Port C Data Register bits
+ $07 constant PORTC_PORTC \ Port C Data Register bits
+&39 constant DDRC \ Port C Data Direction Register
+ $F0 constant DDRC_DDC \ Port C Data Direction Register bits
+ $07 constant DDRC_DDC \ Port C Data Direction Register bits
+&38 constant PINC \ Port C Input Pins
+ $F0 constant PINC_PINC \ Port C Input Pins bits
+ $07 constant PINC_PINC \ Port C Input Pins bits
+
+\ Interrupts
+&2 constant INT0Addr \ External Interrupt Request 0
+&4 constant INT1Addr \ External Interrupt Request 1
+&6 constant INT2Addr \ External Interrupt Request 2
+&8 constant INT3Addr \ External Interrupt Request 3
+&10 constant INT4Addr \ External Interrupt Request 4
+&12 constant INT5Addr \ External Interrupt Request 5
+&14 constant INT6Addr \ External Interrupt Request 6
+&16 constant INT7Addr \ External Interrupt Request 7
+&18 constant PCINT0Addr \ Pin Change Interrupt Request 0
+&20 constant PCINT1Addr \ Pin Change Interrupt Request 1
+&22 constant USB_GENAddr \ USB General Interrupt Request
+&24 constant USB_COMAddr \ USB Endpoint/Pipe Interrupt Communication Reque
+&26 constant WDTAddr \ Watchdog Time-out Interrupt
+&28 constant TIMER1_CAPTAddr \ Timer/Counter2 Capture Event
+&30 constant TIMER1_COMPAAddr \ Timer/Counter2 Compare Match B
+&32 constant TIMER1_COMPBAddr \ Timer/Counter2 Compare Match B
+&34 constant TIMER1_COMPCAddr \ Timer/Counter2 Compare Match C
+&36 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+&38 constant TIMER0_COMPAAddr \ Timer/Counter0 Compare Match A
+&40 constant TIMER0_COMPBAddr \ Timer/Counter0 Compare Match B
+&42 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
+&44 constant SPI__STCAddr \ SPI Serial Transfer Complete
+&46 constant USART1__RXAddr \ USART1, Rx Complete
+&48 constant USART1__UDREAddr \ USART1 Data register Empty
+&50 constant USART1__TXAddr \ USART1, Tx Complete
+&52 constant ANALOG_COMPAddr \ Analog Comparator
+&54 constant EE_READYAddr \ EEPROM Ready
+&56 constant SPM_READYAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/atmega32u2/device.asm b/amforth-6.5/avr8/devices/atmega32u2/device.asm
new file mode 100644
index 0000000..b2164f2
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega32u2/device.asm
@@ -0,0 +1,113 @@
+; Partname: ATmega32U2
+; generated automatically, do not edit
+
+.nolist
+ .include "m32U2def.inc"
+.list
+
+.equ ramstart = 256
+.equ CELLSIZE = 2
+.macro readflashcell
+ lsl zl
+ rol zh
+ lpm @0, Z+
+ lpm @1, Z+
+.endmacro
+.macro writeflashcell
+ lsl zl
+ rol zh
+.endmacro
+.set WANT_PORTB = 0
+.set WANT_PORTD = 0
+.set WANT_SPI = 0
+.set WANT_BOOT_LOAD = 0
+.set WANT_EEPROM = 0
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_PLL = 0
+.set WANT_USB_DEVICE = 0
+.set WANT_PS2 = 0
+.set WANT_CPU = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_USART1 = 0
+.set WANT_WATCHDOG = 0
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_PORTC = 0
+.equ intvecsize = 2 ; please verify; flash size: 32768 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.org 2
+ rcall isr ; External Interrupt Request 0
+.org 4
+ rcall isr ; External Interrupt Request 1
+.org 6
+ rcall isr ; External Interrupt Request 2
+.org 8
+ rcall isr ; External Interrupt Request 3
+.org 10
+ rcall isr ; External Interrupt Request 4
+.org 12
+ rcall isr ; External Interrupt Request 5
+.org 14
+ rcall isr ; External Interrupt Request 6
+.org 16
+ rcall isr ; External Interrupt Request 7
+.org 18
+ rcall isr ; Pin Change Interrupt Request 0
+.org 20
+ rcall isr ; Pin Change Interrupt Request 1
+.org 22
+ rcall isr ; USB General Interrupt Request
+.org 24
+ rcall isr ; USB Endpoint/Pipe Interrupt Communication Request
+.org 26
+ rcall isr ; Watchdog Time-out Interrupt
+.org 28
+ rcall isr ; Timer/Counter2 Capture Event
+.org 30
+ rcall isr ; Timer/Counter2 Compare Match B
+.org 32
+ rcall isr ; Timer/Counter2 Compare Match B
+.org 34
+ rcall isr ; Timer/Counter2 Compare Match C
+.org 36
+ rcall isr ; Timer/Counter1 Overflow
+.org 38
+ rcall isr ; Timer/Counter0 Compare Match A
+.org 40
+ rcall isr ; Timer/Counter0 Compare Match B
+.org 42
+ rcall isr ; Timer/Counter0 Overflow
+.org 44
+ rcall isr ; SPI Serial Transfer Complete
+.org 46
+ rcall isr ; USART1, Rx Complete
+.org 48
+ rcall isr ; USART1 Data register Empty
+.org 50
+ rcall isr ; USART1, Tx Complete
+.org 52
+ rcall isr ; Analog Comparator
+.org 54
+ rcall isr ; EEPROM Ready
+.org 56
+ rcall isr ; Store Program Memory Read
+.equ INTVECTORS = 29
+.nooverlap
+
+; compatability layer (maybe empty)
+
+; controller data area, environment query mcu-info
+mcu_info:
+mcu_ramsize:
+ .dw 1024
+mcu_eepromsize:
+ .dw 1024
+mcu_maxdp:
+ .dw 28672
+mcu_numints:
+ .dw 29
+mcu_name:
+ .dw 10
+ .db "ATmega32U2"
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega32u2/device.inc b/amforth-6.5/avr8/devices/atmega32u2/device.inc
new file mode 100644
index 0000000..a40b3a2
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega32u2/device.inc
@@ -0,0 +1,1155 @@
+; Partname: ATmega32U2
+; generated automatically, no not edit
+
+.if WANT_PORTB == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw 37
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw 36
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw 35
+
+.endif
+.if WANT_PORTD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw 43
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw 42
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw 41
+
+.endif
+.if WANT_SPI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR:
+ .dw $ff04
+ .db "SPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR
+XT_SPCR:
+ .dw PFA_DOVARIABLE
+PFA_SPCR:
+ .dw 76
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR:
+ .dw $ff04
+ .db "SPSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR
+XT_SPSR:
+ .dw PFA_DOVARIABLE
+PFA_SPSR:
+ .dw 77
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR:
+ .dw $ff04
+ .db "SPDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR
+XT_SPDR:
+ .dw PFA_DOVARIABLE
+PFA_SPDR:
+ .dw 78
+
+.endif
+.if WANT_BOOT_LOAD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control Register
+VE_SPMCSR:
+ .dw $ff06
+ .db "SPMCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCSR
+XT_SPMCSR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCSR:
+ .dw 87
+
+.endif
+.if WANT_EEPROM == 1
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Address Register Low Bytes
+VE_EEAR:
+ .dw $ff04
+ .db "EEAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEAR
+XT_EEAR:
+ .dw PFA_DOVARIABLE
+PFA_EEAR:
+ .dw 65
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw 64
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw 63
+
+.endif
+.if WANT_TIMER_COUNTER_0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0B:
+ .dw $ff05
+ .db "OCR0B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0B
+XT_OCR0B:
+ .dw PFA_DOVARIABLE
+PFA_OCR0B:
+ .dw 72
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0A:
+ .dw $ff05
+ .db "OCR0A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0A
+XT_OCR0A:
+ .dw PFA_DOVARIABLE
+PFA_OCR0A:
+ .dw 71
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw 70
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register B
+VE_TCCR0B:
+ .dw $ff06
+ .db "TCCR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0B
+XT_TCCR0B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0B:
+ .dw 69
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register A
+VE_TCCR0A:
+ .dw $ff06
+ .db "TCCR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0A
+XT_TCCR0A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0A:
+ .dw 68
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Mask Register
+VE_TIMSK0:
+ .dw $ff06
+ .db "TIMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK0
+XT_TIMSK0:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK0:
+ .dw 110
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Flag register
+VE_TIFR0:
+ .dw $ff05
+ .db "TIFR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR0
+XT_TIFR0:
+ .dw PFA_DOVARIABLE
+PFA_TIFR0:
+ .dw 53
+; ( -- addr ) System Constant
+; R( -- )
+; General Timer/Counter Control Register
+VE_GTCCR:
+ .dw $ff05
+ .db "GTCCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GTCCR
+XT_GTCCR:
+ .dw PFA_DOVARIABLE
+PFA_GTCCR:
+ .dw 67
+
+.endif
+.if WANT_TIMER_COUNTER_1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw 128
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw 129
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter 1 Control Register C
+VE_TCCR1C:
+ .dw $ff06
+ .db "TCCR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1C
+XT_TCCR1C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1C:
+ .dw 130
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Bytes
+VE_TCNT1:
+ .dw $ff05
+ .db "TCNT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1
+XT_TCNT1:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1:
+ .dw 132
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register A Bytes
+VE_OCR1A:
+ .dw $ff05
+ .db "OCR1A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1A
+XT_OCR1A:
+ .dw PFA_DOVARIABLE
+PFA_OCR1A:
+ .dw 136
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register B Bytes
+VE_OCR1B:
+ .dw $ff05
+ .db "OCR1B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1B
+XT_OCR1B:
+ .dw PFA_DOVARIABLE
+PFA_OCR1B:
+ .dw 138
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register C Bytes
+VE_OCR1C:
+ .dw $ff05
+ .db "OCR1C",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1C
+XT_OCR1C:
+ .dw PFA_DOVARIABLE
+PFA_OCR1C:
+ .dw 140
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Bytes
+VE_ICR1:
+ .dw $ff04
+ .db "ICR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1
+XT_ICR1:
+ .dw PFA_DOVARIABLE
+PFA_ICR1:
+ .dw 134
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Mask Register
+VE_TIMSK1:
+ .dw $ff06
+ .db "TIMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK1
+XT_TIMSK1:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK1:
+ .dw 111
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Flag register
+VE_TIFR1:
+ .dw $ff05
+ .db "TIFR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR1
+XT_TIFR1:
+ .dw PFA_DOVARIABLE
+PFA_TIFR1:
+ .dw 54
+
+.endif
+.if WANT_PLL == 1
+; ( -- addr ) System Constant
+; R( -- )
+; PLL Status and Control register
+VE_PLLCSR:
+ .dw $ff06
+ .db "PLLCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PLLCSR
+XT_PLLCSR:
+ .dw PFA_DOVARIABLE
+PFA_PLLCSR:
+ .dw 73
+
+.endif
+.if WANT_USB_DEVICE == 1
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UEINT:
+ .dw $ff05
+ .db "UEINT",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UEINT
+XT_UEINT:
+ .dw PFA_DOVARIABLE
+PFA_UEINT:
+ .dw 244
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UEBCLX:
+ .dw $ff06
+ .db "UEBCLX"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UEBCLX
+XT_UEBCLX:
+ .dw PFA_DOVARIABLE
+PFA_UEBCLX:
+ .dw 242
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UEDATX:
+ .dw $ff06
+ .db "UEDATX"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UEDATX
+XT_UEDATX:
+ .dw PFA_DOVARIABLE
+PFA_UEDATX:
+ .dw 241
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UEIENX:
+ .dw $ff06
+ .db "UEIENX"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UEIENX
+XT_UEIENX:
+ .dw PFA_DOVARIABLE
+PFA_UEIENX:
+ .dw 240
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UESTA1X:
+ .dw $ff07
+ .db "UESTA1X",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UESTA1X
+XT_UESTA1X:
+ .dw PFA_DOVARIABLE
+PFA_UESTA1X:
+ .dw 239
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UESTA0X:
+ .dw $ff07
+ .db "UESTA0X",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UESTA0X
+XT_UESTA0X:
+ .dw PFA_DOVARIABLE
+PFA_UESTA0X:
+ .dw 238
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UECFG1X:
+ .dw $ff07
+ .db "UECFG1X",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UECFG1X
+XT_UECFG1X:
+ .dw PFA_DOVARIABLE
+PFA_UECFG1X:
+ .dw 237
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UECFG0X:
+ .dw $ff07
+ .db "UECFG0X",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UECFG0X
+XT_UECFG0X:
+ .dw PFA_DOVARIABLE
+PFA_UECFG0X:
+ .dw 236
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UECONX:
+ .dw $ff06
+ .db "UECONX"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UECONX
+XT_UECONX:
+ .dw PFA_DOVARIABLE
+PFA_UECONX:
+ .dw 235
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UERST:
+ .dw $ff05
+ .db "UERST",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UERST
+XT_UERST:
+ .dw PFA_DOVARIABLE
+PFA_UERST:
+ .dw 234
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UENUM:
+ .dw $ff05
+ .db "UENUM",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UENUM
+XT_UENUM:
+ .dw PFA_DOVARIABLE
+PFA_UENUM:
+ .dw 233
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UEINTX:
+ .dw $ff06
+ .db "UEINTX"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UEINTX
+XT_UEINTX:
+ .dw PFA_DOVARIABLE
+PFA_UEINTX:
+ .dw 232
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UDMFN:
+ .dw $ff05
+ .db "UDMFN",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDMFN
+XT_UDMFN:
+ .dw PFA_DOVARIABLE
+PFA_UDMFN:
+ .dw 230
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UDFNUM:
+ .dw $ff06
+ .db "UDFNUM"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDFNUM
+XT_UDFNUM:
+ .dw PFA_DOVARIABLE
+PFA_UDFNUM:
+ .dw 228
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UDADDR:
+ .dw $ff06
+ .db "UDADDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDADDR
+XT_UDADDR:
+ .dw PFA_DOVARIABLE
+PFA_UDADDR:
+ .dw 227
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UDIEN:
+ .dw $ff05
+ .db "UDIEN",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDIEN
+XT_UDIEN:
+ .dw PFA_DOVARIABLE
+PFA_UDIEN:
+ .dw 226
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UDINT:
+ .dw $ff05
+ .db "UDINT",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDINT
+XT_UDINT:
+ .dw PFA_DOVARIABLE
+PFA_UDINT:
+ .dw 225
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UDCON:
+ .dw $ff05
+ .db "UDCON",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDCON
+XT_UDCON:
+ .dw PFA_DOVARIABLE
+PFA_UDCON:
+ .dw 224
+; ( -- addr ) System Constant
+; R( -- )
+; USB General Control Register
+VE_USBCON:
+ .dw $ff06
+ .db "USBCON"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USBCON
+XT_USBCON:
+ .dw PFA_DOVARIABLE
+PFA_USBCON:
+ .dw 216
+; ( -- addr ) System Constant
+; R( -- )
+; Regulator Control Register
+VE_REGCR:
+ .dw $ff05
+ .db "REGCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_REGCR
+XT_REGCR:
+ .dw PFA_DOVARIABLE
+PFA_REGCR:
+ .dw 99
+
+.endif
+.if WANT_PS2 == 1
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UPOE:
+ .dw $ff04
+ .db "UPOE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UPOE
+XT_UPOE:
+ .dw PFA_DOVARIABLE
+PFA_UPOE:
+ .dw 251
+; ( -- addr ) System Constant
+; R( -- )
+; PS2 Pad Enable register
+VE_PS2CON:
+ .dw $ff06
+ .db "PS2CON"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PS2CON
+XT_PS2CON:
+ .dw PFA_DOVARIABLE
+PFA_PS2CON:
+ .dw 250
+
+.endif
+.if WANT_CPU == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw 95
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer
+VE_SP:
+ .dw $ff02
+ .db "SP"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SP
+XT_SP:
+ .dw PFA_DOVARIABLE
+PFA_SP:
+ .dw 93
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw 85
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Status Register
+VE_MCUSR:
+ .dw $ff05
+ .db "MCUSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUSR
+XT_MCUSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUSR:
+ .dw 84
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Calibration Value
+VE_OSCCAL:
+ .dw $ff06
+ .db "OSCCAL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSCCAL
+XT_OSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_OSCCAL:
+ .dw 102
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_CLKPR:
+ .dw $ff05
+ .db "CLKPR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKPR
+XT_CLKPR:
+ .dw PFA_DOVARIABLE
+PFA_CLKPR:
+ .dw 97
+; ( -- addr ) System Constant
+; R( -- )
+; Sleep Mode Control Register
+VE_SMCR:
+ .dw $ff04
+ .db "SMCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SMCR
+XT_SMCR:
+ .dw PFA_DOVARIABLE
+PFA_SMCR:
+ .dw 83
+; ( -- addr ) System Constant
+; R( -- )
+; Extended Indirect Register
+VE_EIND:
+ .dw $ff04
+ .db "EIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIND
+XT_EIND:
+ .dw PFA_DOVARIABLE
+PFA_EIND:
+ .dw 92
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 2
+VE_GPIOR2:
+ .dw $ff06
+ .db "GPIOR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR2
+XT_GPIOR2:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR2:
+ .dw 75
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 1
+VE_GPIOR1:
+ .dw $ff06
+ .db "GPIOR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR1
+XT_GPIOR1:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR1:
+ .dw 74
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 0
+VE_GPIOR0:
+ .dw $ff06
+ .db "GPIOR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR0
+XT_GPIOR0:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR0:
+ .dw 62
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register1
+VE_PRR1:
+ .dw $ff04
+ .db "PRR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR1
+XT_PRR1:
+ .dw PFA_DOVARIABLE
+PFA_PRR1:
+ .dw 101
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register0
+VE_PRR0:
+ .dw $ff04
+ .db "PRR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR0
+XT_PRR0:
+ .dw PFA_DOVARIABLE
+PFA_PRR0:
+ .dw 100
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_CLKSTA:
+ .dw $ff06
+ .db "CLKSTA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKSTA
+XT_CLKSTA:
+ .dw PFA_DOVARIABLE
+PFA_CLKSTA:
+ .dw 210
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_CLKSEL1:
+ .dw $ff07
+ .db "CLKSEL1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKSEL1
+XT_CLKSEL1:
+ .dw PFA_DOVARIABLE
+PFA_CLKSEL1:
+ .dw 209
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_CLKSEL0:
+ .dw $ff07
+ .db "CLKSEL0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKSEL0
+XT_CLKSEL0:
+ .dw PFA_DOVARIABLE
+PFA_CLKSEL0:
+ .dw 208
+; ( -- addr ) System Constant
+; R( -- )
+; debugWire communication register
+VE_DWDR:
+ .dw $ff04
+ .db "DWDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DWDR
+XT_DWDR:
+ .dw PFA_DOVARIABLE
+PFA_DWDR:
+ .dw 81
+
+.endif
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register A
+VE_EICRA:
+ .dw $ff05
+ .db "EICRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRA
+XT_EICRA:
+ .dw PFA_DOVARIABLE
+PFA_EICRA:
+ .dw 105
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register B
+VE_EICRB:
+ .dw $ff05
+ .db "EICRB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRB
+XT_EICRB:
+ .dw PFA_DOVARIABLE
+PFA_EICRB:
+ .dw 106
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Mask Register
+VE_EIMSK:
+ .dw $ff05
+ .db "EIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIMSK
+XT_EIMSK:
+ .dw PFA_DOVARIABLE
+PFA_EIMSK:
+ .dw 61
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Flag Register
+VE_EIFR:
+ .dw $ff04
+ .db "EIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIFR
+XT_EIFR:
+ .dw PFA_DOVARIABLE
+PFA_EIFR:
+ .dw 60
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 0
+VE_PCMSK0:
+ .dw $ff06
+ .db "PCMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK0
+XT_PCMSK0:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK0:
+ .dw 107
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 1
+VE_PCMSK1:
+ .dw $ff06
+ .db "PCMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK1
+XT_PCMSK1:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK1:
+ .dw 108
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Interrupt Flag Register
+VE_PCIFR:
+ .dw $ff05
+ .db "PCIFR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCIFR
+XT_PCIFR:
+ .dw PFA_DOVARIABLE
+PFA_PCIFR:
+ .dw 59
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Interrupt Control Register
+VE_PCICR:
+ .dw $ff05
+ .db "PCICR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCICR
+XT_PCICR:
+ .dw PFA_DOVARIABLE
+PFA_PCICR:
+ .dw 104
+
+.endif
+.if WANT_USART1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR1:
+ .dw $ff04
+ .db "UDR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR1
+XT_UDR1:
+ .dw PFA_DOVARIABLE
+PFA_UDR1:
+ .dw 206
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR1A:
+ .dw $ff06
+ .db "UCSR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1A
+XT_UCSR1A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1A:
+ .dw 200
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR1B:
+ .dw $ff06
+ .db "UCSR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1B
+XT_UCSR1B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1B:
+ .dw 201
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR1C:
+ .dw $ff06
+ .db "UCSR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1C
+XT_UCSR1C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1C:
+ .dw 202
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register D
+VE_UCSR1D:
+ .dw $ff06
+ .db "UCSR1D"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1D
+XT_UCSR1D:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1D:
+ .dw 203
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Bytes
+VE_UBRR1:
+ .dw $ff05
+ .db "UBRR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR1
+XT_UBRR1:
+ .dw PFA_DOVARIABLE
+PFA_UBRR1:
+ .dw 204
+
+.endif
+.if WANT_WATCHDOG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCSR:
+ .dw $ff06
+ .db "WDTCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCSR
+XT_WDTCSR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCSR:
+ .dw 96
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Clock Divider
+VE_WDTCKD:
+ .dw $ff06
+ .db "WDTCKD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCKD
+XT_WDTCKD:
+ .dw PFA_DOVARIABLE
+PFA_WDTCKD:
+ .dw 98
+
+.endif
+.if WANT_ANALOG_COMPARATOR == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Control And Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw 80
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_DIDR1:
+ .dw $ff05
+ .db "DIDR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR1
+XT_DIDR1:
+ .dw PFA_DOVARIABLE
+PFA_DIDR1:
+ .dw 127
+
+.endif
+.if WANT_PORTC == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Register
+VE_PORTC:
+ .dw $ff05
+ .db "PORTC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTC
+XT_PORTC:
+ .dw PFA_DOVARIABLE
+PFA_PORTC:
+ .dw 40
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Direction Register
+VE_DDRC:
+ .dw $ff04
+ .db "DDRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRC
+XT_DDRC:
+ .dw PFA_DOVARIABLE
+PFA_DDRC:
+ .dw 39
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Input Pins
+VE_PINC:
+ .dw $ff04
+ .db "PINC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINC
+XT_PINC:
+ .dw PFA_DOVARIABLE
+PFA_PINC:
+ .dw 38
+
+.endif
diff --git a/amforth-6.5/avr8/devices/atmega32u2/device.py b/amforth-6.5/avr8/devices/atmega32u2/device.py
new file mode 100644
index 0000000..20a1998
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega32u2/device.py
@@ -0,0 +1,387 @@
+# Generated Automatically
+
+# Partname ATmega32U2
+
+MCUREGS = {
+# Interrupt Vectors
+ 'INT0Addr' : '#2', # External Interrupt Request 0
+ 'INT1Addr' : '#4', # External Interrupt Request 1
+ 'INT2Addr' : '#6', # External Interrupt Request 2
+ 'INT3Addr' : '#8', # External Interrupt Request 3
+ 'INT4Addr' : '#10', # External Interrupt Request 4
+ 'INT5Addr' : '#12', # External Interrupt Request 5
+ 'INT6Addr' : '#14', # External Interrupt Request 6
+ 'INT7Addr' : '#16', # External Interrupt Request 7
+ 'PCINT0Addr' : '#18', # Pin Change Interrupt Request 0
+ 'PCINT1Addr' : '#20', # Pin Change Interrupt Request 1
+ 'USB_GENAddr' : '#22', # USB General Interrupt Request
+ 'USB_COMAddr' : '#24', # USB Endpoint/Pipe Interrupt Communication Request
+ 'WDTAddr' : '#26', # Watchdog Time-out Interrupt
+ 'TIMER1_CAPTAddr' : '#28', # Timer/Counter2 Capture Event
+ 'TIMER1_COMPAAddr' : '#30', # Timer/Counter2 Compare Match B
+ 'TIMER1_COMPBAddr' : '#32', # Timer/Counter2 Compare Match B
+ 'TIMER1_COMPCAddr' : '#34', # Timer/Counter2 Compare Match C
+ 'TIMER1_OVFAddr' : '#36', # Timer/Counter1 Overflow
+ 'TIMER0_COMPAAddr' : '#38', # Timer/Counter0 Compare Match A
+ 'TIMER0_COMPBAddr' : '#40', # Timer/Counter0 Compare Match B
+ 'TIMER0_OVFAddr' : '#42', # Timer/Counter0 Overflow
+ 'SPI_STCAddr' : '#44', # SPI Serial Transfer Complete
+ 'USART1_RXAddr' : '#46', # USART1, Rx Complete
+ 'USART1_UDREAddr' : '#48', # USART1 Data register Empty
+ 'USART1_TXAddr' : '#50', # USART1, Tx Complete
+ 'ANALOG_COMPAddr' : '#52', # Analog Comparator
+ 'EE_READYAddr' : '#54', # EEPROM Ready
+ 'SPM_READYAddr' : '#56', # Store Program Memory Read
+
+# Module PORTB
+ 'PORTB' : '$25', # Port B Data Register
+ 'DDRB' : '$24', # Port B Data Direction Register
+ 'PINB' : '$23', # Port B Input Pins
+
+# Module PORTD
+ 'PORTD' : '$2b', # Port D Data Register
+ 'DDRD' : '$2a', # Port D Data Direction Register
+ 'PIND' : '$29', # Port D Input Pins
+
+# Module SPI
+ 'SPCR' : '$4c', # SPI Control Register
+ 'SPCR_SPIE': '$80', # SPI Interrupt Enable
+ 'SPCR_SPE': '$40', # SPI Enable
+ 'SPCR_DORD': '$20', # Data Order
+ 'SPCR_MSTR': '$10', # Master/Slave Select
+ 'SPCR_CPOL': '$8', # Clock polarity
+ 'SPCR_CPHA': '$4', # Clock Phase
+ 'SPCR_SPR': '$3', # SPI Clock Rate Selects
+ 'SPSR' : '$4d', # SPI Status Register
+ 'SPSR_SPIF': '$80', # SPI Interrupt Flag
+ 'SPSR_WCOL': '$40', # Write Collision Flag
+ 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
+ 'SPDR' : '$4e', # SPI Data Register
+
+# Module BOOT_LOAD
+ 'SPMCSR' : '$57', # Store Program Memory Control R
+ 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
+ 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
+ 'SPMCSR_SIGRD': '$20', # Signature Row Read
+ 'SPMCSR_RWWSRE': '$10', # Read While Write section read
+ 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
+ 'SPMCSR_PGWRT': '$4', # Page Write
+ 'SPMCSR_PGERS': '$2', # Page Erase
+ 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
+
+# Module EEPROM
+ 'EEAR' : '$41', # EEPROM Address Register Low By
+ 'EEDR' : '$40', # EEPROM Data Register
+ 'EECR' : '$3f', # EEPROM Control Register
+ 'EECR_EEPM': '$30', # EEPROM Programming Mode Bits
+ 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
+ 'EECR_EEMPE': '$4', # EEPROM Master Write Enable
+ 'EECR_EEPE': '$2', # EEPROM Write Enable
+ 'EECR_EERE': '$1', # EEPROM Read Enable
+
+# Module TIMER_COUNTER_0
+ 'OCR0B' : '$48', # Timer/Counter0 Output Compare
+ 'OCR0A' : '$47', # Timer/Counter0 Output Compare
+ 'TCNT0' : '$46', # Timer/Counter0
+ 'TCCR0B' : '$45', # Timer/Counter Control Register
+ 'TCCR0B_FOC0A': '$80', # Force Output Compare A
+ 'TCCR0B_FOC0B': '$40', # Force Output Compare B
+ 'TCCR0B_WGM02': '$8', #
+ 'TCCR0B_CS0': '$7', # Clock Select
+ 'TCCR0A' : '$44', # Timer/Counter Control Registe
+ 'TCCR0A_COM0A': '$c0', # Compare Output Mode, Phase Cor
+ 'TCCR0A_COM0B': '$30', # Compare Output Mode, Fast PWm
+ 'TCCR0A_WGM0': '$3', # Waveform Generation Mode
+ 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
+ 'TIMSK0_OCIE0B': '$4', # Timer/Counter0 Output Compare
+ 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
+ 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
+ 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
+ 'TIFR0_OCF0B': '$4', # Timer/Counter0 Output Compare
+ 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
+ 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSRSYNC': '$1', # Prescaler Reset Timer/Counter1
+
+# Module TIMER_COUNTER_1
+ 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
+ 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
+ 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
+ 'TCCR1A_COM1C': '$c', # Compare Output Mode 1C, bits
+ 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
+ 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
+ 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
+ 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
+ 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
+ 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
+ 'TCCR1C' : '$82', # Timer/Counter 1 Control Regist
+ 'TCCR1C_FOC1A': '$80', # Force Output Compare 1A
+ 'TCCR1C_FOC1B': '$40', # Force Output Compare 1B
+ 'TCCR1C_FOC1C': '$20', # Force Output Compare 1C
+ 'TCNT1' : '$84', # Timer/Counter1 Bytes
+ 'OCR1A' : '$88', # Timer/Counter1 Output Compare
+ 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
+ 'OCR1C' : '$8c', # Timer/Counter1 Output Compare
+ 'ICR1' : '$86', # Timer/Counter1 Input Capture R
+ 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
+ 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
+ 'TIMSK1_OCIE1C': '$8', # Timer/Counter1 Output Compare
+ 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
+ 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
+ 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
+ 'TIFR1' : '$36', # Timer/Counter1 Interrupt Flag
+ 'TIFR1_ICF1': '$20', # Input Capture Flag 1
+ 'TIFR1_OCF1C': '$8', # Output Compare Flag 1C
+ 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
+ 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
+ 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
+
+# Module PLL
+ 'PLLCSR' : '$49', # PLL Status and Control registe
+ 'PLLCSR_PLLP': '$1c', # PLL prescaler Bits
+ 'PLLCSR_PLLE': '$2', # PLL Enable Bit
+ 'PLLCSR_PLOCK': '$1', # PLL Lock Status Bit
+
+# Module USB_DEVICE
+ 'UEINT' : '$f4', #
+ 'UEBCLX' : '$f2', #
+ 'UEDATX' : '$f1', #
+ 'UEIENX' : '$f0', #
+ 'UEIENX_FLERRE': '$80', #
+ 'UEIENX_NAKINE': '$40', #
+ 'UEIENX_NAKOUTE': '$10', #
+ 'UEIENX_RXSTPE': '$8', #
+ 'UEIENX_RXOUTE': '$4', #
+ 'UEIENX_STALLEDE': '$2', #
+ 'UEIENX_TXINE': '$1', #
+ 'UESTA1X' : '$ef', #
+ 'UESTA1X_CTRLDIR': '$4', #
+ 'UESTA1X_CURRBK': '$3', #
+ 'UESTA0X' : '$ee', #
+ 'UESTA0X_CFGOK': '$80', #
+ 'UESTA0X_OVERFI': '$40', #
+ 'UESTA0X_UNDERFI': '$20', #
+ 'UESTA0X_DTSEQ': '$c', #
+ 'UESTA0X_NBUSYBK': '$3', #
+ 'UECFG1X' : '$ed', #
+ 'UECFG1X_EPSIZE': '$70', #
+ 'UECFG1X_EPBK': '$c', #
+ 'UECFG1X_ALLOC': '$2', #
+ 'UECFG0X' : '$ec', #
+ 'UECFG0X_EPTYPE': '$c0', #
+ 'UECFG0X_EPDIR': '$1', #
+ 'UECONX' : '$eb', #
+ 'UECONX_STALLRQ': '$20', #
+ 'UECONX_STALLRQC': '$10', #
+ 'UECONX_RSTDT': '$8', #
+ 'UECONX_EPEN': '$1', #
+ 'UERST' : '$ea', #
+ 'UERST_EPRST': '$1f', #
+ 'UENUM' : '$e9', #
+ 'UEINTX' : '$e8', #
+ 'UEINTX_FIFOCON': '$80', #
+ 'UEINTX_NAKINI': '$40', #
+ 'UEINTX_RWAL': '$20', #
+ 'UEINTX_NAKOUTI': '$10', #
+ 'UEINTX_RXSTPI': '$8', #
+ 'UEINTX_RXOUTI': '$4', #
+ 'UEINTX_STALLEDI': '$2', #
+ 'UEINTX_TXINI': '$1', #
+ 'UDMFN' : '$e6', #
+ 'UDMFN_FNCERR': '$10', #
+ 'UDFNUM' : '$e4', #
+ 'UDADDR' : '$e3', #
+ 'UDADDR_ADDEN': '$80', #
+ 'UDADDR_UADD': '$7f', #
+ 'UDIEN' : '$e2', #
+ 'UDIEN_UPRSME': '$40', #
+ 'UDIEN_EORSME': '$20', #
+ 'UDIEN_WAKEUPE': '$10', #
+ 'UDIEN_EORSTE': '$8', #
+ 'UDIEN_SOFE': '$4', #
+ 'UDIEN_SUSPE': '$1', #
+ 'UDINT' : '$e1', #
+ 'UDINT_UPRSMI': '$40', #
+ 'UDINT_EORSMI': '$20', #
+ 'UDINT_WAKEUPI': '$10', #
+ 'UDINT_EORSTI': '$8', #
+ 'UDINT_SOFI': '$4', #
+ 'UDINT_SUSPI': '$1', #
+ 'UDCON' : '$e0', #
+ 'UDCON_RSTCPU': '$4', #
+ 'UDCON_RMWKUP': '$2', #
+ 'UDCON_DETACH': '$1', #
+ 'USBCON' : '$d8', # USB General Control Register
+ 'USBCON_USBE': '$80', #
+ 'USBCON_FRZCLK': '$20', #
+ 'REGCR' : '$63', # Regulator Control Register
+ 'REGCR_REGDIS': '$1', #
+
+# Module PS2
+ 'UPOE' : '$fb', #
+ 'UPOE_UPWE': '$c0', #
+ 'UPOE_UPDRV': '$30', #
+ 'UPOE_SCKI': '$8', #
+ 'UPOE_DATAI': '$4', #
+ 'UPOE_DPI': '$2', #
+ 'UPOE_DMI': '$1', #
+ 'PS2CON' : '$fa', # PS2 Pad Enable register
+ 'PS2CON_PS2EN': '$1', # Enable
+
+# Module CPU
+ 'SREG' : '$5f', # Status Register
+ 'SREG_I': '$80', # Global Interrupt Enable
+ 'SREG_T': '$40', # Bit Copy Storage
+ 'SREG_H': '$20', # Half Carry Flag
+ 'SREG_S': '$10', # Sign Bit
+ 'SREG_V': '$8', # Two's Complement Overflow Flag
+ 'SREG_N': '$4', # Negative Flag
+ 'SREG_Z': '$2', # Zero Flag
+ 'SREG_C': '$1', # Carry Flag
+ 'SP' : '$5d', # Stack Pointer
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_PUD': '$10', # Pull-up disable
+ 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
+ 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_USBRF': '$20', # USB reset flag
+ 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
+ 'MCUSR_BORF': '$4', # Brown-out Reset Flag
+ 'MCUSR_EXTRF': '$2', # External Reset Flag
+ 'MCUSR_PORF': '$1', # Power-on reset flag
+ 'OSCCAL' : '$66', # Oscillator Calibration Value
+ 'CLKPR' : '$61', #
+ 'CLKPR_CLKPCE': '$80', #
+ 'CLKPR_CLKPS': '$f', #
+ 'SMCR' : '$53', # Sleep Mode Control Register
+ 'SMCR_SM': '$e', # Sleep Mode Select bits
+ 'SMCR_SE': '$1', # Sleep Enable
+ 'EIND' : '$5c', # Extended Indirect Register
+ 'GPIOR2' : '$4b', # General Purpose IO Register 2
+ 'GPIOR2_GPIOR': '$ff', # General Purpose IO Register 2
+ 'GPIOR1' : '$4a', # General Purpose IO Register 1
+ 'GPIOR1_GPIOR': '$ff', # General Purpose IO Register 1
+ 'GPIOR0' : '$3e', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR07': '$80', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR06': '$40', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR05': '$20', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR04': '$10', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR03': '$8', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR02': '$4', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR01': '$2', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR00': '$1', # General Purpose IO Register 0
+ 'PRR1' : '$65', # Power Reduction Register1
+ 'PRR1_PRUSB': '$80', # Power Reduction USB
+ 'PRR1_PRUSART1': '$1', # Power Reduction USART1
+ 'PRR0' : '$64', # Power Reduction Register0
+ 'PRR0_PRTIM0': '$20', # Power Reduction Timer/Counter0
+ 'PRR0_PRTIM1': '$8', # Power Reduction Timer/Counter1
+ 'PRR0_PRSPI': '$4', # Power Reduction Serial Periphe
+ 'CLKSTA' : '$d2', #
+ 'CLKSTA_RCON': '$2', #
+ 'CLKSTA_EXTON': '$1', #
+ 'CLKSEL1' : '$d1', #
+ 'CLKSEL1_RCCKSEL': '$f0', #
+ 'CLKSEL1_EXCKSEL': '$f', #
+ 'CLKSEL0' : '$d0', #
+ 'CLKSEL0_RCSUT': '$c0', #
+ 'CLKSEL0_EXSUT': '$30', #
+ 'CLKSEL0_RCE': '$8', #
+ 'CLKSEL0_EXTE': '$4', #
+ 'CLKSEL0_CLKS': '$1', #
+ 'DWDR' : '$51', # debugWire communication regist
+
+# Module EXTERNAL_INTERRUPT
+ 'EICRA' : '$69', # External Interrupt Control Reg
+ 'EICRA_ISC3': '$c0', # External Interrupt Sense Contr
+ 'EICRA_ISC2': '$30', # External Interrupt Sense Contr
+ 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
+ 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
+ 'EICRB' : '$6a', # External Interrupt Control Reg
+ 'EICRB_ISC7': '$c0', # External Interrupt 7-4 Sense C
+ 'EICRB_ISC6': '$30', # External Interrupt 7-4 Sense C
+ 'EICRB_ISC5': '$c', # External Interrupt 7-4 Sense C
+ 'EICRB_ISC4': '$3', # External Interrupt 7-4 Sense C
+ 'EIMSK' : '$3d', # External Interrupt Mask Regist
+ 'EIMSK_INT': '$ff', # External Interrupt Request 7 E
+ 'EIFR' : '$3c', # External Interrupt Flag Regist
+ 'EIFR_INTF': '$ff', # External Interrupt Flags
+ 'PCMSK0' : '$6b', # Pin Change Mask Register 0
+ 'PCMSK0_PCINT': '$ff', # Pin Change Enable Masks
+ 'PCMSK1' : '$6c', # Pin Change Mask Register 1
+ 'PCMSK1_PCINT': '$1f', #
+ 'PCIFR' : '$3b', # Pin Change Interrupt Flag Regi
+ 'PCIFR_PCIF': '$3', # Pin Change Interrupt Flags
+ 'PCICR' : '$68', # Pin Change Interrupt Control R
+ 'PCICR_PCIE': '$3', # Pin Change Interrupt Enables
+
+# Module USART1
+ 'UDR1' : '$ce', # USART I/O Data Register
+ 'UCSR1A' : '$c8', # USART Control and Status Regis
+ 'UCSR1A_RXC1': '$80', # USART Receive Complete
+ 'UCSR1A_TXC1': '$40', # USART Transmitt Complete
+ 'UCSR1A_UDRE1': '$20', # USART Data Register Empty
+ 'UCSR1A_FE1': '$10', # Framing Error
+ 'UCSR1A_DOR1': '$8', # Data overRun
+ 'UCSR1A_UPE1': '$4', # Parity Error
+ 'UCSR1A_U2X1': '$2', # Double the USART transmission
+ 'UCSR1A_MPCM1': '$1', # Multi-processor Communication
+ 'UCSR1B' : '$c9', # USART Control and Status Regis
+ 'UCSR1B_RXCIE1': '$80', # RX Complete Interrupt Enable
+ 'UCSR1B_TXCIE1': '$40', # TX Complete Interrupt Enable
+ 'UCSR1B_UDRIE1': '$20', # USART Data register Empty Inte
+ 'UCSR1B_RXEN1': '$10', # Receiver Enable
+ 'UCSR1B_TXEN1': '$8', # Transmitter Enable
+ 'UCSR1B_UCSZ12': '$4', # Character Size
+ 'UCSR1B_RXB81': '$2', # Receive Data Bit 8
+ 'UCSR1B_TXB81': '$1', # Transmit Data Bit 8
+ 'UCSR1C' : '$ca', # USART Control and Status Regis
+ 'UCSR1C_UMSEL1': '$c0', # USART Mode Select
+ 'UCSR1C_UPM1': '$30', # Parity Mode Bits
+ 'UCSR1C_USBS1': '$8', # Stop Bit Select
+ 'UCSR1C_UCSZ1': '$6', # Character Size
+ 'UCSR1C_UCPOL1': '$1', # Clock Polarity
+ 'UCSR1D' : '$cb', # USART Control and Status Regis
+ 'UCSR1D_CTSEN': '$2', # CTS Enable
+ 'UCSR1D_RTSEN': '$1', # RTS Enable
+ 'UBRR1' : '$cc', # USART Baud Rate Register Byte
+
+# Module WATCHDOG
+ 'WDTCSR' : '$60', # Watchdog Timer Control Registe
+ 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
+ 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
+ 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
+ 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
+ 'WDTCSR_WDE': '$8', # Watch Dog Enable
+ 'WDTCKD' : '$62', # Watchdog Timer Clock Divider
+ 'WDTCKD_WDEWIF': '$8', # Watchdog Early Warning Interru
+ 'WDTCKD_WDEWIE': '$4', # Watchdog Early Warning Interru
+ 'WDTCKD_WCLKD': '$3', # Watchdog Timer Clock Dividers
+
+# Module ANALOG_COMPARATOR
+ 'ACSR' : '$50', # Analog Comparator Control And
+ 'ACSR_ACD': '$80', # Analog Comparator Disable
+ 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
+ 'ACSR_ACO': '$20', # Analog Compare Output
+ 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
+ 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
+ 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
+ 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
+ 'DIDR1' : '$7f', #
+ 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
+ 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
+
+# Module PORTC
+ 'PORTC' : '$28', # Port C Data Register
+ 'PORTC_PORTC': '$f0', # Port C Data Register bits
+ 'PORTC_PORTC': '$7', # Port C Data Register bits
+ 'DDRC' : '$27', # Port C Data Direction Register
+ 'DDRC_DDC': '$f0', # Port C Data Direction Register
+ 'DDRC_DDC': '$7', # Port C Data Direction Register
+ 'PINC' : '$26', # Port C Input Pins
+ 'PINC_PINC': '$f0', # Port C Input Pins bits
+ 'PINC_PINC': '$7', # Port C Input Pins bits
+
+ '__amforth_dummy':'0'
+}
diff --git a/amforth-6.5/avr8/devices/atmega32u2/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega32u2/words/no-jtag.asm
new file mode 100644
index 0000000..352a4bb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega32u2/words/no-jtag.asm
@@ -0,0 +1,14 @@
+; ( -- )
+; ( -- )
+; MCU
+; disable jtag at runtime
+VE_NOJTAG:
+ .dw $FF05
+ .db "-jtag",0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOJTAG
+XT_NOJTAG:
+ .dw PFA_NOJTAG
+PFA_NOJTAG:
+
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega32u2/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega32u2/words/no-wdt.asm
new file mode 100644
index 0000000..ff6ddd1
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega32u2/words/no-wdt.asm
@@ -0,0 +1,34 @@
+; ( -- )
+; MCU
+; disable watch dog timer at runtime
+VE_NOWDT:
+ .dw $ff04
+ .db "-wdt"
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOWDT
+XT_NOWDT:
+ .dw PFA_NOWDT
+PFA_NOWDT:
+
+ in temp1,SREG
+ push temp1
+ ; Turn always off global interrupt.
+ cli
+ ; Reset Watchdog Timer
+ wdr
+ ; Clear WDRF in MCUSR
+ in temp1, MCUSR
+ andi temp1, (0xff & (0<<WDRF))
+ out MCUSR, temp1
+ ; Write logical one to WDCE and WDE
+ ; Keep old prescaler setting to prevent unintentional time-out
+ in_ temp1, WDTCSR
+ ori temp1, (1<<WDCE) | (1<<WDE)
+ out_ WDTCSR, temp1
+ ; Turn off WDT
+ ldi temp1, (0<<WDE)
+ out_ WDTCSR, temp1
+ ; restore status register
+ pop temp1
+ out SREG,temp1
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega32u2/words/sleep.asm b/amforth-6.5/avr8/devices/atmega32u2/words/sleep.asm
new file mode 100644
index 0000000..256249c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega32u2/words/sleep.asm
@@ -0,0 +1,19 @@
+; ( mode -- )
+; MCU
+; put the controller into the specified sleep mode
+VE_SLEEP:
+ .dw $ff05
+ .db "sleep", 0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_SLEEP
+XT_SLEEP:
+ .dw PFA_SLEEP
+PFA_SLEEP:
+ andi tosl, 7 ; leave only legal mode bits
+ lsl tosl ; move to correct location (bits 3-1)
+ ori tosl, 1 ; set the SE bit
+ out_ SMCR, tosl ; set the sleep config
+ sleep ; nighty-night
+ out_ SMCR, zerol ; 0 protects against accidental sleeps
+ loadtos ; pop argument from stack
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega32u4/atmega32u4.frt b/amforth-6.5/avr8/devices/atmega32u4/atmega32u4.frt
new file mode 100644
index 0000000..8636a4e
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega32u4/atmega32u4.frt
@@ -0,0 +1,496 @@
+\ Partname: ATmega32U4
+\ generated automatically
+
+\ WATCHDOG
+&96 constant WDTCSR \ Watchdog Timer Control Register
+ $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Flag
+ $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Enable
+ $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
+ $10 constant WDTCSR_WDCE \ Watchdog Change Enable
+ $08 constant WDTCSR_WDE \ Watch Dog Enable
+\ PORTD
+&43 constant PORTD \ Port D Data Register
+&42 constant DDRD \ Port D Data Direction Register
+&41 constant PIND \ Port D Input Pins
+\ SPI
+&76 constant SPCR \ SPI Control Register
+ $80 constant SPCR_SPIE \ SPI Interrupt Enable
+ $40 constant SPCR_SPE \ SPI Enable
+ $20 constant SPCR_DORD \ Data Order
+ $10 constant SPCR_MSTR \ Master/Slave Select
+ $08 constant SPCR_CPOL \ Clock polarity
+ $04 constant SPCR_CPHA \ Clock Phase
+ $03 constant SPCR_SPR \ SPI Clock Rate Selects
+&77 constant SPSR \ SPI Status Register
+ $80 constant SPSR_SPIF \ SPI Interrupt Flag
+ $40 constant SPSR_WCOL \ Write Collision Flag
+ $01 constant SPSR_SPI2X \ Double SPI Speed Bit
+&78 constant SPDR \ SPI Data Register
+\ USART1
+&206 constant UDR1 \ USART I/O Data Register
+&200 constant UCSR1A \ USART Control and Status Register A
+ $80 constant UCSR1A_RXC1 \ USART Receive Complete
+ $40 constant UCSR1A_TXC1 \ USART Transmitt Complete
+ $20 constant UCSR1A_UDRE1 \ USART Data Register Empty
+ $10 constant UCSR1A_FE1 \ Framing Error
+ $08 constant UCSR1A_DOR1 \ Data overRun
+ $04 constant UCSR1A_UPE1 \ Parity Error
+ $02 constant UCSR1A_U2X1 \ Double the USART transmission speed
+ $01 constant UCSR1A_MPCM1 \ Multi-processor Communication Mode
+&201 constant UCSR1B \ USART Control and Status Register B
+ $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable
+ $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable
+ $20 constant UCSR1B_UDRIE1 \ USART Data register Empty Interrupt Enable
+ $10 constant UCSR1B_RXEN1 \ Receiver Enable
+ $08 constant UCSR1B_TXEN1 \ Transmitter Enable
+ $04 constant UCSR1B_UCSZ12 \ Character Size
+ $02 constant UCSR1B_RXB81 \ Receive Data Bit 8
+ $01 constant UCSR1B_TXB81 \ Transmit Data Bit 8
+&202 constant UCSR1C \ USART Control and Status Register C
+ $C0 constant UCSR1C_UMSEL1 \ USART Mode Select
+ $30 constant UCSR1C_UPM1 \ Parity Mode Bits
+ $08 constant UCSR1C_USBS1 \ Stop Bit Select
+ $06 constant UCSR1C_UCSZ1 \ Character Size
+ $01 constant UCSR1C_UCPOL1 \ Clock Polarity
+&204 constant UBRR1 \ USART Baud Rate Register Bytes
+\ BOOT_LOAD
+&87 constant SPMCSR \ Store Program Memory Control Register
+ $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
+ $20 constant SPMCSR_SIGRD \ Signature Row Read
+ $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
+ $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
+ $04 constant SPMCSR_PGWRT \ Page Write
+ $02 constant SPMCSR_PGERS \ Page Erase
+ $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
+\ EEPROM
+&65 constant EEAR \ EEPROM Address Register Low Bytes
+&64 constant EEDR \ EEPROM Data Register
+&63 constant EECR \ EEPROM Control Register
+ $30 constant EECR_EEPM \ EEPROM Programming Mode Bits
+ $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
+ $04 constant EECR_EEMPE \ EEPROM Master Write Enable
+ $02 constant EECR_EEPE \ EEPROM Write Enable
+ $01 constant EECR_EERE \ EEPROM Read Enable
+\ TIMER_COUNTER_0
+&72 constant OCR0B \ Timer/Counter0 Output Compare Register
+&71 constant OCR0A \ Timer/Counter0 Output Compare Register
+&70 constant TCNT0 \ Timer/Counter0
+&69 constant TCCR0B \ Timer/Counter Control Register B
+ $80 constant TCCR0B_FOC0A \ Force Output Compare A
+ $40 constant TCCR0B_FOC0B \ Force Output Compare B
+ $08 constant TCCR0B_WGM02 \
+ $07 constant TCCR0B_CS0 \ Clock Select
+&68 constant TCCR0A \ Timer/Counter Control Register A
+ $C0 constant TCCR0A_COM0A \ Compare Output Mode, Phase Correct PWM Mode
+ $30 constant TCCR0A_COM0B \ Compare Output Mode, Fast PWm
+ $03 constant TCCR0A_WGM0 \ Waveform Generation Mode
+&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
+ $04 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare Match B Interrupt Enable
+ $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match A Interrupt Enable
+ $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
+&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
+ $04 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare Flag 0B
+ $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0A
+ $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
+&67 constant GTCCR \ General Timer/Counter Control Register
+ $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
+ $01 constant GTCCR_PSRSYNC \ Prescaler Reset Timer/Counter1 and Timer/Counter0
+\ TIMER_COUNTER_3
+&144 constant TCCR3A \ Timer/Counter3 Control Register A
+ $C0 constant TCCR3A_COM3A \ Compare Output Mode 1A, bits
+ $30 constant TCCR3A_COM3B \ Compare Output Mode 3B, bits
+ $0C constant TCCR3A_COM3C \ Compare Output Mode 3C, bits
+ $03 constant TCCR3A_WGM3 \ Waveform Generation Mode
+&145 constant TCCR3B \ Timer/Counter3 Control Register B
+ $80 constant TCCR3B_ICNC3 \ Input Capture 3 Noise Canceler
+ $40 constant TCCR3B_ICES3 \ Input Capture 3 Edge Select
+ $18 constant TCCR3B_WGM3 \ Waveform Generation Mode
+ $07 constant TCCR3B_CS3 \ Prescaler source of Timer/Counter 3
+&146 constant TCCR3C \ Timer/Counter 3 Control Register C
+ $80 constant TCCR3C_FOC3A \ Force Output Compare 3A
+ $40 constant TCCR3C_FOC3B \ Force Output Compare 3B
+ $20 constant TCCR3C_FOC3C \ Force Output Compare 3C
+&148 constant TCNT3 \ Timer/Counter3 Bytes
+&152 constant OCR3A \ Timer/Counter3 Output Compare Register A Bytes
+&154 constant OCR3B \ Timer/Counter3 Output Compare Register B Bytes
+&156 constant OCR3C \ Timer/Counter3 Output Compare Register B Bytes
+&150 constant ICR3 \ Timer/Counter3 Input Capture Register Bytes
+&113 constant TIMSK3 \ Timer/Counter3 Interrupt Mask Register
+ $20 constant TIMSK3_ICIE3 \ Timer/Counter3 Input Capture Interrupt Enable
+ $08 constant TIMSK3_OCIE3C \ Timer/Counter3 Output Compare C Match Interrupt Enable
+ $04 constant TIMSK3_OCIE3B \ Timer/Counter3 Output Compare B Match Interrupt Enable
+ $02 constant TIMSK3_OCIE3A \ Timer/Counter3 Output Compare A Match Interrupt Enable
+ $01 constant TIMSK3_TOIE3 \ Timer/Counter3 Overflow Interrupt Enable
+&56 constant TIFR3 \ Timer/Counter3 Interrupt Flag register
+ $20 constant TIFR3_ICF3 \ Input Capture Flag 3
+ $08 constant TIFR3_OCF3C \ Output Compare Flag 3C
+ $04 constant TIFR3_OCF3B \ Output Compare Flag 3B
+ $02 constant TIFR3_OCF3A \ Output Compare Flag 3A
+ $01 constant TIFR3_TOV3 \ Timer/Counter3 Overflow Flag
+\ TIMER_COUNTER_1
+&128 constant TCCR1A \ Timer/Counter1 Control Register A
+ $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
+ $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
+ $0C constant TCCR1A_COM1C \ Compare Output Mode 1C, bits
+ $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
+&129 constant TCCR1B \ Timer/Counter1 Control Register B
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
+ $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
+&130 constant TCCR1C \ Timer/Counter 1 Control Register C
+ $80 constant TCCR1C_FOC1A \ Force Output Compare 1A
+ $40 constant TCCR1C_FOC1B \ Force Output Compare 1B
+ $20 constant TCCR1C_FOC1C \ Force Output Compare 1C
+&132 constant TCNT1 \ Timer/Counter1 Bytes
+&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
+&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
+&140 constant OCR1C \ Timer/Counter1 Output Compare Register C Bytes
+&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
+&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
+ $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
+ $08 constant TIMSK1_OCIE1C \ Timer/Counter1 Output Compare C Match Interrupt Enable
+ $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
+ $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
+ $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
+&54 constant TIFR1 \ Timer/Counter1 Interrupt Flag register
+ $20 constant TIFR1_ICF1 \ Input Capture Flag 1
+ $08 constant TIFR1_OCF1C \ Output Compare Flag 1C
+ $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
+ $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
+ $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
+\ JTAG
+&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
+&85 constant MCUCR \ MCU Control Register
+ $80 constant MCUCR_JTD \ JTAG Interface Disable
+&84 constant MCUSR \ MCU Status Register
+ $10 constant MCUSR_JTRF \ JTAG Reset Flag
+\ EXTERNAL_INTERRUPT
+&105 constant EICRA \ External Interrupt Control Register A
+ $C0 constant EICRA_ISC3 \ External Interrupt Sense Control Bit
+ $30 constant EICRA_ISC2 \ External Interrupt Sense Control Bit
+ $0C constant EICRA_ISC1 \ External Interrupt Sense Control Bit
+ $03 constant EICRA_ISC0 \ External Interrupt Sense Control Bit
+&106 constant EICRB \ External Interrupt Control Register B
+ $C0 constant EICRB_ISC7 \ External Interrupt 7-4 Sense Control Bit
+ $30 constant EICRB_ISC6 \ External Interrupt 7-4 Sense Control Bit
+ $0C constant EICRB_ISC5 \ External Interrupt 7-4 Sense Control Bit
+ $03 constant EICRB_ISC4 \ External Interrupt 7-4 Sense Control Bit
+&61 constant EIMSK \ External Interrupt Mask Register
+ $FF constant EIMSK_INT \ External Interrupt Request 7 Enable
+&60 constant EIFR \ External Interrupt Flag Register
+ $FF constant EIFR_INTF \ External Interrupt Flags
+&107 constant PCMSK0 \ Pin Change Mask Register 0
+&59 constant PCIFR \ Pin Change Interrupt Flag Register
+ $01 constant PCIFR_PCIF0 \ Pin Change Interrupt Flag 0
+&104 constant PCICR \ Pin Change Interrupt Control Register
+ $01 constant PCICR_PCIE0 \ Pin Change Interrupt Enable 0
+\ TIMER_COUNTER_4
+&192 constant TCCR4A \ Timer/Counter4 Control Register A
+ $C0 constant TCCR4A_COM4A \ Compare Output Mode 1A, bits
+ $30 constant TCCR4A_COM4B \ Compare Output Mode 4B, bits
+ $08 constant TCCR4A_FOC4A \ Force Output Compare Match 4A
+ $04 constant TCCR4A_FOC4B \ Force Output Compare Match 4B
+ $02 constant TCCR4A_PWM4A \
+ $01 constant TCCR4A_PWM4B \
+&193 constant TCCR4B \ Timer/Counter4 Control Register B
+ $80 constant TCCR4B_PWM4X \ PWM Inversion Mode
+ $40 constant TCCR4B_PSR4 \ Prescaler Reset Timer/Counter 4
+ $30 constant TCCR4B_DTPS4 \ Dead Time Prescaler Bits
+ $0F constant TCCR4B_CS4 \ Clock Select Bits
+&194 constant TCCR4C \ Timer/Counter 4 Control Register C
+ $80 constant TCCR4C_COM4A1S \ Comparator A Output Mode
+ $40 constant TCCR4C_COM4A0S \ Comparator A Output Mode
+ $20 constant TCCR4C_COM4B1S \ Comparator B Output Mode
+ $10 constant TCCR4C_COM4B0S \ Comparator B Output Mode
+ $0C constant TCCR4C_COM4D \ Comparator D Output Mode
+ $02 constant TCCR4C_FOC4D \ Force Output Compare Match 4D
+ $01 constant TCCR4C_PWM4D \ Pulse Width Modulator D Enable
+&195 constant TCCR4D \ Timer/Counter 4 Control Register D
+ $80 constant TCCR4D_FPIE4 \ Fault Protection Interrupt Enable
+ $40 constant TCCR4D_FPEN4 \ Fault Protection Mode Enable
+ $20 constant TCCR4D_FPNC4 \ Fault Protection Noise Canceler
+ $10 constant TCCR4D_FPES4 \ Fault Protection Edge Select
+ $08 constant TCCR4D_FPAC4 \ Fault Protection Analog Comparator Enable
+ $04 constant TCCR4D_FPF4 \ Fault Protection Interrupt Flag
+ $03 constant TCCR4D_WGM4 \ Waveform Generation Mode bits
+&196 constant TCCR4E \ Timer/Counter 4 Control Register E
+ $80 constant TCCR4E_TLOCK4 \ Register Update Lock
+ $40 constant TCCR4E_ENHC4 \ Enhanced Compare/PWM Mode
+ $3F constant TCCR4E_OC4OE \ Output Compare Override Enable bit
+&190 constant TCNT4 \ Timer/Counter4 Low Bytes
+&191 constant TC4H \ Timer/Counter4
+&207 constant OCR4A \ Timer/Counter4 Output Compare Register A
+&208 constant OCR4B \ Timer/Counter4 Output Compare Register B
+&209 constant OCR4C \ Timer/Counter4 Output Compare Register C
+&210 constant OCR4D \ Timer/Counter4 Output Compare Register D
+&114 constant TIMSK4 \ Timer/Counter4 Interrupt Mask Register
+ $80 constant TIMSK4_OCIE4D \ Timer/Counter4 Output Compare D Match Interrupt Enable
+ $40 constant TIMSK4_OCIE4A \ Timer/Counter4 Output Compare A Match Interrupt Enable
+ $20 constant TIMSK4_OCIE4B \ Timer/Counter4 Output Compare B Match Interrupt Enable
+ $04 constant TIMSK4_TOIE4 \ Timer/Counter4 Overflow Interrupt Enable
+&57 constant TIFR4 \ Timer/Counter4 Interrupt Flag register
+ $80 constant TIFR4_OCF4D \ Output Compare Flag 4D
+ $40 constant TIFR4_OCF4A \ Output Compare Flag 4A
+ $20 constant TIFR4_OCF4B \ Output Compare Flag 4B
+ $04 constant TIFR4_TOV4 \ Timer/Counter4 Overflow Flag
+&212 constant DT4 \ Timer/Counter 4 Dead Time Value
+ $FF constant DT4_DT4L \ Timer/Counter 4 Dead Time Value Bits
+\ PORTB
+&37 constant PORTB \ Port B Data Register
+&36 constant DDRB \ Port B Data Direction Register
+&35 constant PINB \ Port B Input Pins
+\ PORTC
+&40 constant PORTC \ Port C Data Register
+&39 constant DDRC \ Port C Data Direction Register
+&38 constant PINC \ Port C Input Pins
+\ PORTE
+&46 constant PORTE \ Data Register, Port E
+&45 constant DDRE \ Data Direction Register, Port E
+&44 constant PINE \ Input Pins, Port E
+\ PORTF
+&49 constant PORTF \ Data Register, Port F
+&48 constant DDRF \ Data Direction Register, Port F
+&47 constant PINF \ Input Pins, Port F
+\ AD_CONVERTER
+&124 constant ADMUX \ The ADC multiplexer Selection Register
+ $C0 constant ADMUX_REFS \ Reference Selection Bits
+ $20 constant ADMUX_ADLAR \ Left Adjust Result
+ $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
+&122 constant ADCSRA \ The ADC Control and Status register
+ $80 constant ADCSRA_ADEN \ ADC Enable
+ $40 constant ADCSRA_ADSC \ ADC Start Conversion
+ $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
+ $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
+ $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
+ $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
+&120 constant ADC \ ADC Data Register Bytes
+&123 constant ADCSRB \ ADC Control and Status Register B
+ $80 constant ADCSRB_ADHSM \ ADC High Speed Mode
+ $20 constant ADCSRB_MUX5 \ Analog Channel and Gain Selection Bits
+ $17 constant ADCSRB_ADTS \ ADC Auto Trigger Sources
+&126 constant DIDR0 \ Digital Input Disable Register 1
+ $80 constant DIDR0_ADC7D \ ADC7 Digital input Disable
+ $40 constant DIDR0_ADC6D \ ADC6 Digital input Disable
+ $20 constant DIDR0_ADC5D \ ADC5 Digital input Disable
+ $10 constant DIDR0_ADC4D \ ADC4 Digital input Disable
+ $08 constant DIDR0_ADC3D \ ADC3 Digital input Disable
+ $04 constant DIDR0_ADC2D \ ADC2 Digital input Disable
+ $02 constant DIDR0_ADC1D \ ADC1 Digital input Disable
+ $01 constant DIDR0_ADC0D \ ADC0 Digital input Disable
+&125 constant DIDR2 \ Digital Input Disable Register 1
+ $20 constant DIDR2_ADC13D \ ADC13 Digital input Disable
+ $10 constant DIDR2_ADC12D \ ADC12 Digital input Disable
+ $08 constant DIDR2_ADC11D \ ADC11 Digital input Disable
+ $04 constant DIDR2_ADC10D \ ADC10 Digital input Disable
+ $02 constant DIDR2_ADC9D \ ADC9 Digital input Disable
+ $01 constant DIDR2_ADC8D \ ADC8 Digital input Disable
+\ ANALOG_COMPARATOR
+&80 constant ACSR \ Analog Comparator Control And Status Register
+ $80 constant ACSR_ACD \ Analog Comparator Disable
+ $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
+ $20 constant ACSR_ACO \ Analog Compare Output
+ $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
+ $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
+ $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
+ $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
+&127 constant DIDR1 \
+ $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
+ $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
+\ CPU
+&95 constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ $08 constant SREG_V \ Two's Complement Overflow Flag
+ $04 constant SREG_N \ Negative Flag
+ $02 constant SREG_Z \ Zero Flag
+ $01 constant SREG_C \ Carry Flag
+&93 constant SP \ Stack Pointer
+&102 constant OSCCAL \ Oscillator Calibration Value
+&103 constant RCCTRL \ Oscillator Control Register
+ $01 constant RCCTRL_RCFREQ \
+&97 constant CLKPR \
+ $80 constant CLKPR_CLKPCE \
+ $0F constant CLKPR_CLKPS \
+&83 constant SMCR \ Sleep Mode Control Register
+ $0E constant SMCR_SM \ Sleep Mode Select bits
+ $01 constant SMCR_SE \ Sleep Enable
+&92 constant EIND \ Extended Indirect Register
+&75 constant GPIOR2 \ General Purpose IO Register 2
+ $FF constant GPIOR2_GPIOR \ General Purpose IO Register 2 bis
+&74 constant GPIOR1 \ General Purpose IO Register 1
+ $FF constant GPIOR1_GPIOR \ General Purpose IO Register 1 bis
+&62 constant GPIOR0 \ General Purpose IO Register 0
+ $80 constant GPIOR0_GPIOR07 \ General Purpose IO Register 0 bit 7
+ $40 constant GPIOR0_GPIOR06 \ General Purpose IO Register 0 bit 6
+ $20 constant GPIOR0_GPIOR05 \ General Purpose IO Register 0 bit 5
+ $10 constant GPIOR0_GPIOR04 \ General Purpose IO Register 0 bit 4
+ $08 constant GPIOR0_GPIOR03 \ General Purpose IO Register 0 bit 3
+ $04 constant GPIOR0_GPIOR02 \ General Purpose IO Register 0 bit 2
+ $02 constant GPIOR0_GPIOR01 \ General Purpose IO Register 0 bit 1
+ $01 constant GPIOR0_GPIOR00 \ General Purpose IO Register 0 bit 0
+&101 constant PRR1 \ Power Reduction Register1
+ $80 constant PRR1_PRUSB \ Power Reduction USB
+ $08 constant PRR1_PRTIM3 \ Power Reduction Timer/Counter3
+ $01 constant PRR1_PRUSART1 \ Power Reduction USART1
+&100 constant PRR0 \ Power Reduction Register0
+ $80 constant PRR0_PRTWI \ Power Reduction TWI
+ $40 constant PRR0_PRTIM2 \ Power Reduction Timer/Counter2
+ $20 constant PRR0_PRTIM0 \ Power Reduction Timer/Counter0
+ $08 constant PRR0_PRTIM1 \ Power Reduction Timer/Counter1
+ $04 constant PRR0_PRSPI \ Power Reduction Serial Peripheral Interface
+ $02 constant PRR0_PRUSART0 \ Power Reduction USART
+ $01 constant PRR0_PRADC \ Power Reduction ADC
+&199 constant CLKSTA \
+ $02 constant CLKSTA_RCON \
+ $01 constant CLKSTA_EXTON \
+&198 constant CLKSEL1 \
+ $F0 constant CLKSEL1_RCCKSEL \
+ $0F constant CLKSEL1_EXCKSEL \
+&197 constant CLKSEL0 \
+ $C0 constant CLKSEL0_RCSUT \
+ $30 constant CLKSEL0_EXSUT \
+ $08 constant CLKSEL0_RCE \
+ $04 constant CLKSEL0_EXTE \
+ $01 constant CLKSEL0_CLKS \
+\ PLL
+&73 constant PLLCSR \ PLL Status and Control register
+ $10 constant PLLCSR_PINDIV \ PLL prescaler Bit 2
+ $02 constant PLLCSR_PLLE \ PLL Enable Bit
+ $01 constant PLLCSR_PLOCK \ PLL Lock Status Bit
+&82 constant PLLFRQ \ PLL Frequency Control Register
+ $80 constant PLLFRQ_PINMUX \
+ $40 constant PLLFRQ_PLLUSB \
+ $30 constant PLLFRQ_PLLTM \
+ $0F constant PLLFRQ_PDIV \
+\ USB_DEVICE
+&244 constant UEINT \
+&243 constant UEBCHX \
+&242 constant UEBCLX \
+&241 constant UEDATX \
+ $FF constant UEDATX_DAT \
+&240 constant UEIENX \
+ $80 constant UEIENX_FLERRE \
+ $40 constant UEIENX_NAKINE \
+ $10 constant UEIENX_NAKOUTE \
+ $08 constant UEIENX_RXSTPE \
+ $04 constant UEIENX_RXOUTE \
+ $02 constant UEIENX_STALLEDE \
+ $01 constant UEIENX_TXINE \
+&239 constant UESTA1X \
+ $04 constant UESTA1X_CTRLDIR \
+ $03 constant UESTA1X_CURRBK \
+&238 constant UESTA0X \
+ $80 constant UESTA0X_CFGOK \
+ $40 constant UESTA0X_OVERFI \
+ $20 constant UESTA0X_UNDERFI \
+ $0C constant UESTA0X_DTSEQ \
+ $03 constant UESTA0X_NBUSYBK \
+&237 constant UECFG1X \
+ $70 constant UECFG1X_EPSIZE \
+ $0C constant UECFG1X_EPBK \
+ $02 constant UECFG1X_ALLOC \
+&236 constant UECFG0X \
+ $C0 constant UECFG0X_EPTYPE \
+ $01 constant UECFG0X_EPDIR \
+&235 constant UECONX \
+ $20 constant UECONX_STALLRQ \
+ $10 constant UECONX_STALLRQC \
+ $08 constant UECONX_RSTDT \
+ $01 constant UECONX_EPEN \
+&234 constant UERST \
+ $7F constant UERST_EPRST \
+&233 constant UENUM \
+&232 constant UEINTX \
+ $80 constant UEINTX_FIFOCON \
+ $40 constant UEINTX_NAKINI \
+ $20 constant UEINTX_RWAL \
+ $10 constant UEINTX_NAKOUTI \
+ $08 constant UEINTX_RXSTPI \
+ $04 constant UEINTX_RXOUTI \
+ $02 constant UEINTX_STALLEDI \
+ $01 constant UEINTX_TXINI \
+&230 constant UDMFN \
+ $10 constant UDMFN_FNCERR \
+&228 constant UDFNUM \
+&227 constant UDADDR \
+ $80 constant UDADDR_ADDEN \
+ $7F constant UDADDR_UADD \
+&226 constant UDIEN \
+ $40 constant UDIEN_UPRSME \
+ $20 constant UDIEN_EORSME \
+ $10 constant UDIEN_WAKEUPE \
+ $08 constant UDIEN_EORSTE \
+ $04 constant UDIEN_SOFE \
+ $01 constant UDIEN_SUSPE \
+&225 constant UDINT \
+ $40 constant UDINT_UPRSMI \
+ $20 constant UDINT_EORSMI \
+ $10 constant UDINT_WAKEUPI \
+ $08 constant UDINT_EORSTI \
+ $04 constant UDINT_SOFI \
+ $01 constant UDINT_SUSPI \
+&224 constant UDCON \
+ $04 constant UDCON_LSM \ USB low speed mode
+ $08 constant UDCON_RSTCPU \
+ $02 constant UDCON_RMWKUP \
+ $01 constant UDCON_DETACH \
+&216 constant USBCON \ USB General Control Register
+ $80 constant USBCON_USBE \
+ $20 constant USBCON_FRZCLK \
+ $10 constant USBCON_OTGPADE \
+ $01 constant USBCON_VBUSTE \
+&218 constant USBINT \
+ $01 constant USBINT_VBUSTI \
+&217 constant USBSTA \
+ $08 constant USBSTA_SPEED \
+ $01 constant USBSTA_VBUS \
+&215 constant UHWCON \
+ $01 constant UHWCON_UVREGE \
+
+\ Interrupts
+&2 constant INT0Addr \ External Interrupt Request 0
+&4 constant INT1Addr \ External Interrupt Request 1
+&6 constant INT2Addr \ External Interrupt Request 2
+&8 constant INT3Addr \ External Interrupt Request 3
+&10 constant Reserved1Addr \ Reserved1
+&12 constant Reserved2Addr \ Reserved2
+&14 constant INT6Addr \ External Interrupt Request 6
+&16 constant Reserved3Addr \ Reserved3
+&18 constant PCINT0Addr \ Pin Change Interrupt Request 0
+&20 constant USB_GENAddr \ USB General Interrupt Request
+&22 constant USB_COMAddr \ USB Endpoint/Pipe Interrupt Communication Reque
+&24 constant WDTAddr \ Watchdog Time-out Interrupt
+&26 constant Reserved4Addr \ Reserved4
+&28 constant Reserved5Addr \ Reserved5
+&30 constant Reserved6Addr \ Reserved6
+&32 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+&34 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
+&36 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
+&38 constant TIMER1_COMPCAddr \ Timer/Counter1 Compare Match C
+&40 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+&42 constant TIMER0_COMPAAddr \ Timer/Counter0 Compare Match A
+&44 constant TIMER0_COMPBAddr \ Timer/Counter0 Compare Match B
+&46 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
+&48 constant SPI__STCAddr \ SPI Serial Transfer Complete
+&50 constant USART1__RXAddr \ USART1, Rx Complete
+&52 constant USART1__UDREAddr \ USART1 Data register Empty
+&54 constant USART1__TXAddr \ USART1, Tx Complete
+&56 constant ANALOG_COMPAddr \ Analog Comparator
+&58 constant ADCAddr \ ADC Conversion Complete
+&60 constant EE_READYAddr \ EEPROM Ready
+&62 constant TIMER3_CAPTAddr \ Timer/Counter3 Capture Event
+&64 constant TIMER3_COMPAAddr \ Timer/Counter3 Compare Match A
+&66 constant TIMER3_COMPBAddr \ Timer/Counter3 Compare Match B
+&68 constant TIMER3_COMPCAddr \ Timer/Counter3 Compare Match C
+&70 constant TIMER3_OVFAddr \ Timer/Counter3 Overflow
+&72 constant TWIAddr \ 2-wire Serial Interface
+&74 constant SPM_READYAddr \ Store Program Memory Read
+&76 constant TIMER4_COMPAAddr \ Timer/Counter4 Compare Match A
+&78 constant TIMER4_COMPBAddr \ Timer/Counter4 Compare Match B
+&80 constant TIMER4_COMPDAddr \ Timer/Counter4 Compare Match D
+&82 constant TIMER4_OVFAddr \ Timer/Counter4 Overflow
+&84 constant TIMER4_FPFAddr \ Timer/Counter4 Fault Protection Interrupt
diff --git a/amforth-6.5/avr8/devices/atmega32u4/device.asm b/amforth-6.5/avr8/devices/atmega32u4/device.asm
new file mode 100644
index 0000000..f722b8e
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega32u4/device.asm
@@ -0,0 +1,146 @@
+; Partname: ATmega32U4
+; generated automatically, do not edit
+
+.nolist
+ .include "m32U4def.inc"
+.list
+
+.equ ramstart = 256
+.equ CELLSIZE = 2
+.macro readflashcell
+ lsl zl
+ rol zh
+ lpm @0, Z+
+ lpm @1, Z+
+.endmacro
+.macro writeflashcell
+ lsl zl
+ rol zh
+.endmacro
+.set WANT_WATCHDOG = 0
+.set WANT_PORTD = 0
+.set WANT_SPI = 0
+.set WANT_USART1 = 0
+.set WANT_BOOT_LOAD = 0
+.set WANT_EEPROM = 0
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_TIMER_COUNTER_3 = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_JTAG = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_TIMER_COUNTER_4 = 0
+.set WANT_PORTB = 0
+.set WANT_PORTC = 0
+.set WANT_PORTE = 0
+.set WANT_PORTF = 0
+.set WANT_AD_CONVERTER = 0
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_CPU = 0
+.set WANT_PLL = 0
+.set WANT_USB_DEVICE = 0
+.equ intvecsize = 2 ; please verify; flash size: 32768 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.org 2
+ rcall isr ; External Interrupt Request 0
+.org 4
+ rcall isr ; External Interrupt Request 1
+.org 6
+ rcall isr ; External Interrupt Request 2
+.org 8
+ rcall isr ; External Interrupt Request 3
+.org 10
+ rcall isr ; Reserved1
+.org 12
+ rcall isr ; Reserved2
+.org 14
+ rcall isr ; External Interrupt Request 6
+.org 16
+ rcall isr ; Reserved3
+.org 18
+ rcall isr ; Pin Change Interrupt Request 0
+.org 20
+ rcall isr ; USB General Interrupt Request
+.org 22
+ rcall isr ; USB Endpoint/Pipe Interrupt Communication Request
+.org 24
+ rcall isr ; Watchdog Time-out Interrupt
+.org 26
+ rcall isr ; Reserved4
+.org 28
+ rcall isr ; Reserved5
+.org 30
+ rcall isr ; Reserved6
+.org 32
+ rcall isr ; Timer/Counter1 Capture Event
+.org 34
+ rcall isr ; Timer/Counter1 Compare Match A
+.org 36
+ rcall isr ; Timer/Counter1 Compare Match B
+.org 38
+ rcall isr ; Timer/Counter1 Compare Match C
+.org 40
+ rcall isr ; Timer/Counter1 Overflow
+.org 42
+ rcall isr ; Timer/Counter0 Compare Match A
+.org 44
+ rcall isr ; Timer/Counter0 Compare Match B
+.org 46
+ rcall isr ; Timer/Counter0 Overflow
+.org 48
+ rcall isr ; SPI Serial Transfer Complete
+.org 50
+ rcall isr ; USART1, Rx Complete
+.org 52
+ rcall isr ; USART1 Data register Empty
+.org 54
+ rcall isr ; USART1, Tx Complete
+.org 56
+ rcall isr ; Analog Comparator
+.org 58
+ rcall isr ; ADC Conversion Complete
+.org 60
+ rcall isr ; EEPROM Ready
+.org 62
+ rcall isr ; Timer/Counter3 Capture Event
+.org 64
+ rcall isr ; Timer/Counter3 Compare Match A
+.org 66
+ rcall isr ; Timer/Counter3 Compare Match B
+.org 68
+ rcall isr ; Timer/Counter3 Compare Match C
+.org 70
+ rcall isr ; Timer/Counter3 Overflow
+.org 72
+ rcall isr ; 2-wire Serial Interface
+.org 74
+ rcall isr ; Store Program Memory Read
+.org 76
+ rcall isr ; Timer/Counter4 Compare Match A
+.org 78
+ rcall isr ; Timer/Counter4 Compare Match B
+.org 80
+ rcall isr ; Timer/Counter4 Compare Match D
+.org 82
+ rcall isr ; Timer/Counter4 Overflow
+.org 84
+ rcall isr ; Timer/Counter4 Fault Protection Interrupt
+.equ INTVECTORS = 43
+.nooverlap
+
+; compatability layer (maybe empty)
+
+; controller data area, environment query mcu-info
+mcu_info:
+mcu_ramsize:
+ .dw 2560
+mcu_eepromsize:
+ .dw 1024
+mcu_maxdp:
+ .dw 28672
+mcu_numints:
+ .dw 43
+mcu_name:
+ .dw 10
+ .db "ATmega32U4"
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega32u4/device.inc b/amforth-6.5/avr8/devices/atmega32u4/device.inc
new file mode 100644
index 0000000..4d0f09c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega32u4/device.inc
@@ -0,0 +1,1602 @@
+; Partname: ATmega32U4
+; generated automatically, no not edit
+
+.if WANT_WATCHDOG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCSR:
+ .dw $ff06
+ .db "WDTCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCSR
+XT_WDTCSR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCSR:
+ .dw 96
+
+.endif
+.if WANT_PORTD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw 43
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw 42
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw 41
+
+.endif
+.if WANT_SPI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR:
+ .dw $ff04
+ .db "SPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR
+XT_SPCR:
+ .dw PFA_DOVARIABLE
+PFA_SPCR:
+ .dw 76
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR:
+ .dw $ff04
+ .db "SPSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR
+XT_SPSR:
+ .dw PFA_DOVARIABLE
+PFA_SPSR:
+ .dw 77
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR:
+ .dw $ff04
+ .db "SPDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR
+XT_SPDR:
+ .dw PFA_DOVARIABLE
+PFA_SPDR:
+ .dw 78
+
+.endif
+.if WANT_USART1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR1:
+ .dw $ff04
+ .db "UDR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR1
+XT_UDR1:
+ .dw PFA_DOVARIABLE
+PFA_UDR1:
+ .dw 206
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR1A:
+ .dw $ff06
+ .db "UCSR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1A
+XT_UCSR1A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1A:
+ .dw 200
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR1B:
+ .dw $ff06
+ .db "UCSR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1B
+XT_UCSR1B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1B:
+ .dw 201
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR1C:
+ .dw $ff06
+ .db "UCSR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1C
+XT_UCSR1C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1C:
+ .dw 202
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Bytes
+VE_UBRR1:
+ .dw $ff05
+ .db "UBRR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR1
+XT_UBRR1:
+ .dw PFA_DOVARIABLE
+PFA_UBRR1:
+ .dw 204
+
+.endif
+.if WANT_BOOT_LOAD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control Register
+VE_SPMCSR:
+ .dw $ff06
+ .db "SPMCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCSR
+XT_SPMCSR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCSR:
+ .dw 87
+
+.endif
+.if WANT_EEPROM == 1
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Address Register Low Bytes
+VE_EEAR:
+ .dw $ff04
+ .db "EEAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEAR
+XT_EEAR:
+ .dw PFA_DOVARIABLE
+PFA_EEAR:
+ .dw 65
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw 64
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw 63
+
+.endif
+.if WANT_TIMER_COUNTER_0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0B:
+ .dw $ff05
+ .db "OCR0B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0B
+XT_OCR0B:
+ .dw PFA_DOVARIABLE
+PFA_OCR0B:
+ .dw 72
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0A:
+ .dw $ff05
+ .db "OCR0A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0A
+XT_OCR0A:
+ .dw PFA_DOVARIABLE
+PFA_OCR0A:
+ .dw 71
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw 70
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register B
+VE_TCCR0B:
+ .dw $ff06
+ .db "TCCR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0B
+XT_TCCR0B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0B:
+ .dw 69
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register A
+VE_TCCR0A:
+ .dw $ff06
+ .db "TCCR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0A
+XT_TCCR0A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0A:
+ .dw 68
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Mask Register
+VE_TIMSK0:
+ .dw $ff06
+ .db "TIMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK0
+XT_TIMSK0:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK0:
+ .dw 110
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Flag register
+VE_TIFR0:
+ .dw $ff05
+ .db "TIFR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR0
+XT_TIFR0:
+ .dw PFA_DOVARIABLE
+PFA_TIFR0:
+ .dw 53
+; ( -- addr ) System Constant
+; R( -- )
+; General Timer/Counter Control Register
+VE_GTCCR:
+ .dw $ff05
+ .db "GTCCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GTCCR
+XT_GTCCR:
+ .dw PFA_DOVARIABLE
+PFA_GTCCR:
+ .dw 67
+
+.endif
+.if WANT_TIMER_COUNTER_3 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Control Register A
+VE_TCCR3A:
+ .dw $ff06
+ .db "TCCR3A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR3A
+XT_TCCR3A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR3A:
+ .dw 144
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Control Register B
+VE_TCCR3B:
+ .dw $ff06
+ .db "TCCR3B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR3B
+XT_TCCR3B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR3B:
+ .dw 145
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter 3 Control Register C
+VE_TCCR3C:
+ .dw $ff06
+ .db "TCCR3C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR3C
+XT_TCCR3C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR3C:
+ .dw 146
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Bytes
+VE_TCNT3:
+ .dw $ff05
+ .db "TCNT3",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT3
+XT_TCNT3:
+ .dw PFA_DOVARIABLE
+PFA_TCNT3:
+ .dw 148
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Output Compare Register A Bytes
+VE_OCR3A:
+ .dw $ff05
+ .db "OCR3A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR3A
+XT_OCR3A:
+ .dw PFA_DOVARIABLE
+PFA_OCR3A:
+ .dw 152
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Output Compare Register B Bytes
+VE_OCR3B:
+ .dw $ff05
+ .db "OCR3B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR3B
+XT_OCR3B:
+ .dw PFA_DOVARIABLE
+PFA_OCR3B:
+ .dw 154
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Output Compare Register B Bytes
+VE_OCR3C:
+ .dw $ff05
+ .db "OCR3C",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR3C
+XT_OCR3C:
+ .dw PFA_DOVARIABLE
+PFA_OCR3C:
+ .dw 156
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Input Capture Register Bytes
+VE_ICR3:
+ .dw $ff04
+ .db "ICR3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR3
+XT_ICR3:
+ .dw PFA_DOVARIABLE
+PFA_ICR3:
+ .dw 150
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Interrupt Mask Register
+VE_TIMSK3:
+ .dw $ff06
+ .db "TIMSK3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK3
+XT_TIMSK3:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK3:
+ .dw 113
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Interrupt Flag register
+VE_TIFR3:
+ .dw $ff05
+ .db "TIFR3",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR3
+XT_TIFR3:
+ .dw PFA_DOVARIABLE
+PFA_TIFR3:
+ .dw 56
+
+.endif
+.if WANT_TIMER_COUNTER_1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw 128
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw 129
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter 1 Control Register C
+VE_TCCR1C:
+ .dw $ff06
+ .db "TCCR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1C
+XT_TCCR1C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1C:
+ .dw 130
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Bytes
+VE_TCNT1:
+ .dw $ff05
+ .db "TCNT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1
+XT_TCNT1:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1:
+ .dw 132
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register A Bytes
+VE_OCR1A:
+ .dw $ff05
+ .db "OCR1A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1A
+XT_OCR1A:
+ .dw PFA_DOVARIABLE
+PFA_OCR1A:
+ .dw 136
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register B Bytes
+VE_OCR1B:
+ .dw $ff05
+ .db "OCR1B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1B
+XT_OCR1B:
+ .dw PFA_DOVARIABLE
+PFA_OCR1B:
+ .dw 138
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register C Bytes
+VE_OCR1C:
+ .dw $ff05
+ .db "OCR1C",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1C
+XT_OCR1C:
+ .dw PFA_DOVARIABLE
+PFA_OCR1C:
+ .dw 140
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Bytes
+VE_ICR1:
+ .dw $ff04
+ .db "ICR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1
+XT_ICR1:
+ .dw PFA_DOVARIABLE
+PFA_ICR1:
+ .dw 134
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Mask Register
+VE_TIMSK1:
+ .dw $ff06
+ .db "TIMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK1
+XT_TIMSK1:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK1:
+ .dw 111
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Flag register
+VE_TIFR1:
+ .dw $ff05
+ .db "TIFR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR1
+XT_TIFR1:
+ .dw PFA_DOVARIABLE
+PFA_TIFR1:
+ .dw 54
+
+.endif
+.if WANT_JTAG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; On-Chip Debug Related Register in I/O Memory
+VE_OCDR:
+ .dw $ff04
+ .db "OCDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCDR
+XT_OCDR:
+ .dw PFA_DOVARIABLE
+PFA_OCDR:
+ .dw 81
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw 85
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Status Register
+VE_MCUSR:
+ .dw $ff05
+ .db "MCUSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUSR
+XT_MCUSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUSR:
+ .dw 84
+
+.endif
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register A
+VE_EICRA:
+ .dw $ff05
+ .db "EICRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRA
+XT_EICRA:
+ .dw PFA_DOVARIABLE
+PFA_EICRA:
+ .dw 105
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register B
+VE_EICRB:
+ .dw $ff05
+ .db "EICRB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRB
+XT_EICRB:
+ .dw PFA_DOVARIABLE
+PFA_EICRB:
+ .dw 106
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Mask Register
+VE_EIMSK:
+ .dw $ff05
+ .db "EIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIMSK
+XT_EIMSK:
+ .dw PFA_DOVARIABLE
+PFA_EIMSK:
+ .dw 61
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Flag Register
+VE_EIFR:
+ .dw $ff04
+ .db "EIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIFR
+XT_EIFR:
+ .dw PFA_DOVARIABLE
+PFA_EIFR:
+ .dw 60
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 0
+VE_PCMSK0:
+ .dw $ff06
+ .db "PCMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK0
+XT_PCMSK0:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK0:
+ .dw 107
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Interrupt Flag Register
+VE_PCIFR:
+ .dw $ff05
+ .db "PCIFR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCIFR
+XT_PCIFR:
+ .dw PFA_DOVARIABLE
+PFA_PCIFR:
+ .dw 59
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Interrupt Control Register
+VE_PCICR:
+ .dw $ff05
+ .db "PCICR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCICR
+XT_PCICR:
+ .dw PFA_DOVARIABLE
+PFA_PCICR:
+ .dw 104
+
+.endif
+.if WANT_TIMER_COUNTER_4 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter4 Control Register A
+VE_TCCR4A:
+ .dw $ff06
+ .db "TCCR4A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR4A
+XT_TCCR4A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR4A:
+ .dw 192
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter4 Control Register B
+VE_TCCR4B:
+ .dw $ff06
+ .db "TCCR4B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR4B
+XT_TCCR4B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR4B:
+ .dw 193
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter 4 Control Register C
+VE_TCCR4C:
+ .dw $ff06
+ .db "TCCR4C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR4C
+XT_TCCR4C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR4C:
+ .dw 194
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter 4 Control Register D
+VE_TCCR4D:
+ .dw $ff06
+ .db "TCCR4D"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR4D
+XT_TCCR4D:
+ .dw PFA_DOVARIABLE
+PFA_TCCR4D:
+ .dw 195
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter 4 Control Register E
+VE_TCCR4E:
+ .dw $ff06
+ .db "TCCR4E"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR4E
+XT_TCCR4E:
+ .dw PFA_DOVARIABLE
+PFA_TCCR4E:
+ .dw 196
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter4 Low Bytes
+VE_TCNT4:
+ .dw $ff05
+ .db "TCNT4",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT4
+XT_TCNT4:
+ .dw PFA_DOVARIABLE
+PFA_TCNT4:
+ .dw 190
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter4
+VE_TC4H:
+ .dw $ff04
+ .db "TC4H"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TC4H
+XT_TC4H:
+ .dw PFA_DOVARIABLE
+PFA_TC4H:
+ .dw 191
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter4 Output Compare Register A
+VE_OCR4A:
+ .dw $ff05
+ .db "OCR4A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR4A
+XT_OCR4A:
+ .dw PFA_DOVARIABLE
+PFA_OCR4A:
+ .dw 207
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter4 Output Compare Register B
+VE_OCR4B:
+ .dw $ff05
+ .db "OCR4B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR4B
+XT_OCR4B:
+ .dw PFA_DOVARIABLE
+PFA_OCR4B:
+ .dw 208
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter4 Output Compare Register C
+VE_OCR4C:
+ .dw $ff05
+ .db "OCR4C",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR4C
+XT_OCR4C:
+ .dw PFA_DOVARIABLE
+PFA_OCR4C:
+ .dw 209
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter4 Output Compare Register D
+VE_OCR4D:
+ .dw $ff05
+ .db "OCR4D",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR4D
+XT_OCR4D:
+ .dw PFA_DOVARIABLE
+PFA_OCR4D:
+ .dw 210
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter4 Interrupt Mask Register
+VE_TIMSK4:
+ .dw $ff06
+ .db "TIMSK4"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK4
+XT_TIMSK4:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK4:
+ .dw 114
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter4 Interrupt Flag register
+VE_TIFR4:
+ .dw $ff05
+ .db "TIFR4",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR4
+XT_TIFR4:
+ .dw PFA_DOVARIABLE
+PFA_TIFR4:
+ .dw 57
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter 4 Dead Time Value
+VE_DT4:
+ .dw $ff03
+ .db "DT4",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DT4
+XT_DT4:
+ .dw PFA_DOVARIABLE
+PFA_DT4:
+ .dw 212
+
+.endif
+.if WANT_PORTB == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw 37
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw 36
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw 35
+
+.endif
+.if WANT_PORTC == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Register
+VE_PORTC:
+ .dw $ff05
+ .db "PORTC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTC
+XT_PORTC:
+ .dw PFA_DOVARIABLE
+PFA_PORTC:
+ .dw 40
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Direction Register
+VE_DDRC:
+ .dw $ff04
+ .db "DDRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRC
+XT_DDRC:
+ .dw PFA_DOVARIABLE
+PFA_DDRC:
+ .dw 39
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Input Pins
+VE_PINC:
+ .dw $ff04
+ .db "PINC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINC
+XT_PINC:
+ .dw PFA_DOVARIABLE
+PFA_PINC:
+ .dw 38
+
+.endif
+.if WANT_PORTE == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port E
+VE_PORTE:
+ .dw $ff05
+ .db "PORTE",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTE
+XT_PORTE:
+ .dw PFA_DOVARIABLE
+PFA_PORTE:
+ .dw 46
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port E
+VE_DDRE:
+ .dw $ff04
+ .db "DDRE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRE
+XT_DDRE:
+ .dw PFA_DOVARIABLE
+PFA_DDRE:
+ .dw 45
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port E
+VE_PINE:
+ .dw $ff04
+ .db "PINE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINE
+XT_PINE:
+ .dw PFA_DOVARIABLE
+PFA_PINE:
+ .dw 44
+
+.endif
+.if WANT_PORTF == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port F
+VE_PORTF:
+ .dw $ff05
+ .db "PORTF",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTF
+XT_PORTF:
+ .dw PFA_DOVARIABLE
+PFA_PORTF:
+ .dw 49
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port F
+VE_DDRF:
+ .dw $ff04
+ .db "DDRF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRF
+XT_DDRF:
+ .dw PFA_DOVARIABLE
+PFA_DDRF:
+ .dw 48
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port F
+VE_PINF:
+ .dw $ff04
+ .db "PINF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINF
+XT_PINF:
+ .dw PFA_DOVARIABLE
+PFA_PINF:
+ .dw 47
+
+.endif
+.if WANT_AD_CONVERTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC multiplexer Selection Register
+VE_ADMUX:
+ .dw $ff05
+ .db "ADMUX",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADMUX
+XT_ADMUX:
+ .dw PFA_DOVARIABLE
+PFA_ADMUX:
+ .dw 124
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register
+VE_ADCSRA:
+ .dw $ff06
+ .db "ADCSRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRA
+XT_ADCSRA:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRA:
+ .dw 122
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register Bytes
+VE_ADC:
+ .dw $ff03
+ .db "ADC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADC
+XT_ADC:
+ .dw PFA_DOVARIABLE
+PFA_ADC:
+ .dw 120
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Control and Status Register B
+VE_ADCSRB:
+ .dw $ff06
+ .db "ADCSRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRB
+XT_ADCSRB:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRB:
+ .dw 123
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 1
+VE_DIDR0:
+ .dw $ff05
+ .db "DIDR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR0
+XT_DIDR0:
+ .dw PFA_DOVARIABLE
+PFA_DIDR0:
+ .dw 126
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 1
+VE_DIDR2:
+ .dw $ff05
+ .db "DIDR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR2
+XT_DIDR2:
+ .dw PFA_DOVARIABLE
+PFA_DIDR2:
+ .dw 125
+
+.endif
+.if WANT_ANALOG_COMPARATOR == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Control And Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw 80
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_DIDR1:
+ .dw $ff05
+ .db "DIDR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR1
+XT_DIDR1:
+ .dw PFA_DOVARIABLE
+PFA_DIDR1:
+ .dw 127
+
+.endif
+.if WANT_CPU == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw 95
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer
+VE_SP:
+ .dw $ff02
+ .db "SP"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SP
+XT_SP:
+ .dw PFA_DOVARIABLE
+PFA_SP:
+ .dw 93
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Calibration Value
+VE_OSCCAL:
+ .dw $ff06
+ .db "OSCCAL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSCCAL
+XT_OSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_OSCCAL:
+ .dw 102
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Control Register
+VE_RCCTRL:
+ .dw $ff06
+ .db "RCCTRL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_RCCTRL
+XT_RCCTRL:
+ .dw PFA_DOVARIABLE
+PFA_RCCTRL:
+ .dw 103
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_CLKPR:
+ .dw $ff05
+ .db "CLKPR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKPR
+XT_CLKPR:
+ .dw PFA_DOVARIABLE
+PFA_CLKPR:
+ .dw 97
+; ( -- addr ) System Constant
+; R( -- )
+; Sleep Mode Control Register
+VE_SMCR:
+ .dw $ff04
+ .db "SMCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SMCR
+XT_SMCR:
+ .dw PFA_DOVARIABLE
+PFA_SMCR:
+ .dw 83
+; ( -- addr ) System Constant
+; R( -- )
+; Extended Indirect Register
+VE_EIND:
+ .dw $ff04
+ .db "EIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIND
+XT_EIND:
+ .dw PFA_DOVARIABLE
+PFA_EIND:
+ .dw 92
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 2
+VE_GPIOR2:
+ .dw $ff06
+ .db "GPIOR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR2
+XT_GPIOR2:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR2:
+ .dw 75
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 1
+VE_GPIOR1:
+ .dw $ff06
+ .db "GPIOR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR1
+XT_GPIOR1:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR1:
+ .dw 74
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 0
+VE_GPIOR0:
+ .dw $ff06
+ .db "GPIOR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR0
+XT_GPIOR0:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR0:
+ .dw 62
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register1
+VE_PRR1:
+ .dw $ff04
+ .db "PRR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR1
+XT_PRR1:
+ .dw PFA_DOVARIABLE
+PFA_PRR1:
+ .dw 101
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register0
+VE_PRR0:
+ .dw $ff04
+ .db "PRR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR0
+XT_PRR0:
+ .dw PFA_DOVARIABLE
+PFA_PRR0:
+ .dw 100
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_CLKSTA:
+ .dw $ff06
+ .db "CLKSTA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKSTA
+XT_CLKSTA:
+ .dw PFA_DOVARIABLE
+PFA_CLKSTA:
+ .dw 199
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_CLKSEL1:
+ .dw $ff07
+ .db "CLKSEL1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKSEL1
+XT_CLKSEL1:
+ .dw PFA_DOVARIABLE
+PFA_CLKSEL1:
+ .dw 198
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_CLKSEL0:
+ .dw $ff07
+ .db "CLKSEL0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKSEL0
+XT_CLKSEL0:
+ .dw PFA_DOVARIABLE
+PFA_CLKSEL0:
+ .dw 197
+
+.endif
+.if WANT_PLL == 1
+; ( -- addr ) System Constant
+; R( -- )
+; PLL Status and Control register
+VE_PLLCSR:
+ .dw $ff06
+ .db "PLLCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PLLCSR
+XT_PLLCSR:
+ .dw PFA_DOVARIABLE
+PFA_PLLCSR:
+ .dw 73
+; ( -- addr ) System Constant
+; R( -- )
+; PLL Frequency Control Register
+VE_PLLFRQ:
+ .dw $ff06
+ .db "PLLFRQ"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PLLFRQ
+XT_PLLFRQ:
+ .dw PFA_DOVARIABLE
+PFA_PLLFRQ:
+ .dw 82
+
+.endif
+.if WANT_USB_DEVICE == 1
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UEINT:
+ .dw $ff05
+ .db "UEINT",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UEINT
+XT_UEINT:
+ .dw PFA_DOVARIABLE
+PFA_UEINT:
+ .dw 244
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UEBCHX:
+ .dw $ff06
+ .db "UEBCHX"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UEBCHX
+XT_UEBCHX:
+ .dw PFA_DOVARIABLE
+PFA_UEBCHX:
+ .dw 243
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UEBCLX:
+ .dw $ff06
+ .db "UEBCLX"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UEBCLX
+XT_UEBCLX:
+ .dw PFA_DOVARIABLE
+PFA_UEBCLX:
+ .dw 242
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UEDATX:
+ .dw $ff06
+ .db "UEDATX"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UEDATX
+XT_UEDATX:
+ .dw PFA_DOVARIABLE
+PFA_UEDATX:
+ .dw 241
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UEIENX:
+ .dw $ff06
+ .db "UEIENX"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UEIENX
+XT_UEIENX:
+ .dw PFA_DOVARIABLE
+PFA_UEIENX:
+ .dw 240
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UESTA1X:
+ .dw $ff07
+ .db "UESTA1X",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UESTA1X
+XT_UESTA1X:
+ .dw PFA_DOVARIABLE
+PFA_UESTA1X:
+ .dw 239
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UESTA0X:
+ .dw $ff07
+ .db "UESTA0X",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UESTA0X
+XT_UESTA0X:
+ .dw PFA_DOVARIABLE
+PFA_UESTA0X:
+ .dw 238
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UECFG1X:
+ .dw $ff07
+ .db "UECFG1X",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UECFG1X
+XT_UECFG1X:
+ .dw PFA_DOVARIABLE
+PFA_UECFG1X:
+ .dw 237
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UECFG0X:
+ .dw $ff07
+ .db "UECFG0X",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UECFG0X
+XT_UECFG0X:
+ .dw PFA_DOVARIABLE
+PFA_UECFG0X:
+ .dw 236
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UECONX:
+ .dw $ff06
+ .db "UECONX"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UECONX
+XT_UECONX:
+ .dw PFA_DOVARIABLE
+PFA_UECONX:
+ .dw 235
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UERST:
+ .dw $ff05
+ .db "UERST",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UERST
+XT_UERST:
+ .dw PFA_DOVARIABLE
+PFA_UERST:
+ .dw 234
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UENUM:
+ .dw $ff05
+ .db "UENUM",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UENUM
+XT_UENUM:
+ .dw PFA_DOVARIABLE
+PFA_UENUM:
+ .dw 233
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UEINTX:
+ .dw $ff06
+ .db "UEINTX"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UEINTX
+XT_UEINTX:
+ .dw PFA_DOVARIABLE
+PFA_UEINTX:
+ .dw 232
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UDMFN:
+ .dw $ff05
+ .db "UDMFN",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDMFN
+XT_UDMFN:
+ .dw PFA_DOVARIABLE
+PFA_UDMFN:
+ .dw 230
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UDFNUM:
+ .dw $ff06
+ .db "UDFNUM"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDFNUM
+XT_UDFNUM:
+ .dw PFA_DOVARIABLE
+PFA_UDFNUM:
+ .dw 228
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UDADDR:
+ .dw $ff06
+ .db "UDADDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDADDR
+XT_UDADDR:
+ .dw PFA_DOVARIABLE
+PFA_UDADDR:
+ .dw 227
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UDIEN:
+ .dw $ff05
+ .db "UDIEN",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDIEN
+XT_UDIEN:
+ .dw PFA_DOVARIABLE
+PFA_UDIEN:
+ .dw 226
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UDINT:
+ .dw $ff05
+ .db "UDINT",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDINT
+XT_UDINT:
+ .dw PFA_DOVARIABLE
+PFA_UDINT:
+ .dw 225
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UDCON:
+ .dw $ff05
+ .db "UDCON",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDCON
+XT_UDCON:
+ .dw PFA_DOVARIABLE
+PFA_UDCON:
+ .dw 224
+; ( -- addr ) System Constant
+; R( -- )
+; USB General Control Register
+VE_USBCON:
+ .dw $ff06
+ .db "USBCON"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USBCON
+XT_USBCON:
+ .dw PFA_DOVARIABLE
+PFA_USBCON:
+ .dw 216
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_USBINT:
+ .dw $ff06
+ .db "USBINT"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USBINT
+XT_USBINT:
+ .dw PFA_DOVARIABLE
+PFA_USBINT:
+ .dw 218
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_USBSTA:
+ .dw $ff06
+ .db "USBSTA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USBSTA
+XT_USBSTA:
+ .dw PFA_DOVARIABLE
+PFA_USBSTA:
+ .dw 217
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UHWCON:
+ .dw $ff06
+ .db "UHWCON"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UHWCON
+XT_UHWCON:
+ .dw PFA_DOVARIABLE
+PFA_UHWCON:
+ .dw 215
+
+.endif
diff --git a/amforth-6.5/avr8/devices/atmega32u4/device.py b/amforth-6.5/avr8/devices/atmega32u4/device.py
new file mode 100644
index 0000000..ef93719
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega32u4/device.py
@@ -0,0 +1,554 @@
+# Generated Automatically
+
+# Partname ATmega32U4
+
+MCUREGS = {
+# Interrupt Vectors
+ 'INT0Addr' : '#2', # External Interrupt Request 0
+ 'INT1Addr' : '#4', # External Interrupt Request 1
+ 'INT2Addr' : '#6', # External Interrupt Request 2
+ 'INT3Addr' : '#8', # External Interrupt Request 3
+ 'Reserved1Addr' : '#10', # Reserved1
+ 'Reserved2Addr' : '#12', # Reserved2
+ 'INT6Addr' : '#14', # External Interrupt Request 6
+ 'Reserved3Addr' : '#16', # Reserved3
+ 'PCINT0Addr' : '#18', # Pin Change Interrupt Request 0
+ 'USB_GENAddr' : '#20', # USB General Interrupt Request
+ 'USB_COMAddr' : '#22', # USB Endpoint/Pipe Interrupt Communication Request
+ 'WDTAddr' : '#24', # Watchdog Time-out Interrupt
+ 'Reserved4Addr' : '#26', # Reserved4
+ 'Reserved5Addr' : '#28', # Reserved5
+ 'Reserved6Addr' : '#30', # Reserved6
+ 'TIMER1_CAPTAddr' : '#32', # Timer/Counter1 Capture Event
+ 'TIMER1_COMPAAddr' : '#34', # Timer/Counter1 Compare Match A
+ 'TIMER1_COMPBAddr' : '#36', # Timer/Counter1 Compare Match B
+ 'TIMER1_COMPCAddr' : '#38', # Timer/Counter1 Compare Match C
+ 'TIMER1_OVFAddr' : '#40', # Timer/Counter1 Overflow
+ 'TIMER0_COMPAAddr' : '#42', # Timer/Counter0 Compare Match A
+ 'TIMER0_COMPBAddr' : '#44', # Timer/Counter0 Compare Match B
+ 'TIMER0_OVFAddr' : '#46', # Timer/Counter0 Overflow
+ 'SPI_STCAddr' : '#48', # SPI Serial Transfer Complete
+ 'USART1_RXAddr' : '#50', # USART1, Rx Complete
+ 'USART1_UDREAddr' : '#52', # USART1 Data register Empty
+ 'USART1_TXAddr' : '#54', # USART1, Tx Complete
+ 'ANALOG_COMPAddr' : '#56', # Analog Comparator
+ 'ADCAddr' : '#58', # ADC Conversion Complete
+ 'EE_READYAddr' : '#60', # EEPROM Ready
+ 'TIMER3_CAPTAddr' : '#62', # Timer/Counter3 Capture Event
+ 'TIMER3_COMPAAddr' : '#64', # Timer/Counter3 Compare Match A
+ 'TIMER3_COMPBAddr' : '#66', # Timer/Counter3 Compare Match B
+ 'TIMER3_COMPCAddr' : '#68', # Timer/Counter3 Compare Match C
+ 'TIMER3_OVFAddr' : '#70', # Timer/Counter3 Overflow
+ 'TWIAddr' : '#72', # 2-wire Serial Interface
+ 'SPM_READYAddr' : '#74', # Store Program Memory Read
+ 'TIMER4_COMPAAddr' : '#76', # Timer/Counter4 Compare Match A
+ 'TIMER4_COMPBAddr' : '#78', # Timer/Counter4 Compare Match B
+ 'TIMER4_COMPDAddr' : '#80', # Timer/Counter4 Compare Match D
+ 'TIMER4_OVFAddr' : '#82', # Timer/Counter4 Overflow
+ 'TIMER4_FPFAddr' : '#84', # Timer/Counter4 Fault Protection Interrupt
+
+# Module WATCHDOG
+ 'WDTCSR' : '$60', # Watchdog Timer Control Registe
+ 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
+ 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
+ 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
+ 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
+ 'WDTCSR_WDE': '$8', # Watch Dog Enable
+
+# Module PORTD
+ 'PORTD' : '$2b', # Port D Data Register
+ 'DDRD' : '$2a', # Port D Data Direction Register
+ 'PIND' : '$29', # Port D Input Pins
+
+# Module SPI
+ 'SPCR' : '$4c', # SPI Control Register
+ 'SPCR_SPIE': '$80', # SPI Interrupt Enable
+ 'SPCR_SPE': '$40', # SPI Enable
+ 'SPCR_DORD': '$20', # Data Order
+ 'SPCR_MSTR': '$10', # Master/Slave Select
+ 'SPCR_CPOL': '$8', # Clock polarity
+ 'SPCR_CPHA': '$4', # Clock Phase
+ 'SPCR_SPR': '$3', # SPI Clock Rate Selects
+ 'SPSR' : '$4d', # SPI Status Register
+ 'SPSR_SPIF': '$80', # SPI Interrupt Flag
+ 'SPSR_WCOL': '$40', # Write Collision Flag
+ 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
+ 'SPDR' : '$4e', # SPI Data Register
+
+# Module USART1
+ 'UDR1' : '$ce', # USART I/O Data Register
+ 'UCSR1A' : '$c8', # USART Control and Status Regis
+ 'UCSR1A_RXC1': '$80', # USART Receive Complete
+ 'UCSR1A_TXC1': '$40', # USART Transmitt Complete
+ 'UCSR1A_UDRE1': '$20', # USART Data Register Empty
+ 'UCSR1A_FE1': '$10', # Framing Error
+ 'UCSR1A_DOR1': '$8', # Data overRun
+ 'UCSR1A_UPE1': '$4', # Parity Error
+ 'UCSR1A_U2X1': '$2', # Double the USART transmission
+ 'UCSR1A_MPCM1': '$1', # Multi-processor Communication
+ 'UCSR1B' : '$c9', # USART Control and Status Regis
+ 'UCSR1B_RXCIE1': '$80', # RX Complete Interrupt Enable
+ 'UCSR1B_TXCIE1': '$40', # TX Complete Interrupt Enable
+ 'UCSR1B_UDRIE1': '$20', # USART Data register Empty Inte
+ 'UCSR1B_RXEN1': '$10', # Receiver Enable
+ 'UCSR1B_TXEN1': '$8', # Transmitter Enable
+ 'UCSR1B_UCSZ12': '$4', # Character Size
+ 'UCSR1B_RXB81': '$2', # Receive Data Bit 8
+ 'UCSR1B_TXB81': '$1', # Transmit Data Bit 8
+ 'UCSR1C' : '$ca', # USART Control and Status Regis
+ 'UCSR1C_UMSEL1': '$c0', # USART Mode Select
+ 'UCSR1C_UPM1': '$30', # Parity Mode Bits
+ 'UCSR1C_USBS1': '$8', # Stop Bit Select
+ 'UCSR1C_UCSZ1': '$6', # Character Size
+ 'UCSR1C_UCPOL1': '$1', # Clock Polarity
+ 'UBRR1' : '$cc', # USART Baud Rate Register Byte
+
+# Module BOOT_LOAD
+ 'SPMCSR' : '$57', # Store Program Memory Control R
+ 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
+ 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
+ 'SPMCSR_SIGRD': '$20', # Signature Row Read
+ 'SPMCSR_RWWSRE': '$10', # Read While Write section read
+ 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
+ 'SPMCSR_PGWRT': '$4', # Page Write
+ 'SPMCSR_PGERS': '$2', # Page Erase
+ 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
+
+# Module EEPROM
+ 'EEAR' : '$41', # EEPROM Address Register Low By
+ 'EEDR' : '$40', # EEPROM Data Register
+ 'EECR' : '$3f', # EEPROM Control Register
+ 'EECR_EEPM': '$30', # EEPROM Programming Mode Bits
+ 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
+ 'EECR_EEMPE': '$4', # EEPROM Master Write Enable
+ 'EECR_EEPE': '$2', # EEPROM Write Enable
+ 'EECR_EERE': '$1', # EEPROM Read Enable
+
+# Module TIMER_COUNTER_0
+ 'OCR0B' : '$48', # Timer/Counter0 Output Compare
+ 'OCR0A' : '$47', # Timer/Counter0 Output Compare
+ 'TCNT0' : '$46', # Timer/Counter0
+ 'TCCR0B' : '$45', # Timer/Counter Control Register
+ 'TCCR0B_FOC0A': '$80', # Force Output Compare A
+ 'TCCR0B_FOC0B': '$40', # Force Output Compare B
+ 'TCCR0B_WGM02': '$8', #
+ 'TCCR0B_CS0': '$7', # Clock Select
+ 'TCCR0A' : '$44', # Timer/Counter Control Registe
+ 'TCCR0A_COM0A': '$c0', # Compare Output Mode, Phase Cor
+ 'TCCR0A_COM0B': '$30', # Compare Output Mode, Fast PWm
+ 'TCCR0A_WGM0': '$3', # Waveform Generation Mode
+ 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
+ 'TIMSK0_OCIE0B': '$4', # Timer/Counter0 Output Compare
+ 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
+ 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
+ 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
+ 'TIFR0_OCF0B': '$4', # Timer/Counter0 Output Compare
+ 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
+ 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSRSYNC': '$1', # Prescaler Reset Timer/Counter1
+
+# Module TIMER_COUNTER_3
+ 'TCCR3A' : '$90', # Timer/Counter3 Control Registe
+ 'TCCR3A_COM3A': '$c0', # Compare Output Mode 1A, bits
+ 'TCCR3A_COM3B': '$30', # Compare Output Mode 3B, bits
+ 'TCCR3A_COM3C': '$c', # Compare Output Mode 3C, bits
+ 'TCCR3A_WGM3': '$3', # Waveform Generation Mode
+ 'TCCR3B' : '$91', # Timer/Counter3 Control Registe
+ 'TCCR3B_ICNC3': '$80', # Input Capture 3 Noise Canceler
+ 'TCCR3B_ICES3': '$40', # Input Capture 3 Edge Select
+ 'TCCR3B_WGM3': '$18', # Waveform Generation Mode
+ 'TCCR3B_CS3': '$7', # Prescaler source of Timer/Coun
+ 'TCCR3C' : '$92', # Timer/Counter 3 Control Regist
+ 'TCCR3C_FOC3A': '$80', # Force Output Compare 3A
+ 'TCCR3C_FOC3B': '$40', # Force Output Compare 3B
+ 'TCCR3C_FOC3C': '$20', # Force Output Compare 3C
+ 'TCNT3' : '$94', # Timer/Counter3 Bytes
+ 'OCR3A' : '$98', # Timer/Counter3 Output Compare
+ 'OCR3B' : '$9a', # Timer/Counter3 Output Compare
+ 'OCR3C' : '$9c', # Timer/Counter3 Output Compare
+ 'ICR3' : '$96', # Timer/Counter3 Input Capture R
+ 'TIMSK3' : '$71', # Timer/Counter3 Interrupt Mask
+ 'TIMSK3_ICIE3': '$20', # Timer/Counter3 Input Capture I
+ 'TIMSK3_OCIE3C': '$8', # Timer/Counter3 Output Compare
+ 'TIMSK3_OCIE3B': '$4', # Timer/Counter3 Output Compare
+ 'TIMSK3_OCIE3A': '$2', # Timer/Counter3 Output Compare
+ 'TIMSK3_TOIE3': '$1', # Timer/Counter3 Overflow Interr
+ 'TIFR3' : '$38', # Timer/Counter3 Interrupt Flag
+ 'TIFR3_ICF3': '$20', # Input Capture Flag 3
+ 'TIFR3_OCF3C': '$8', # Output Compare Flag 3C
+ 'TIFR3_OCF3B': '$4', # Output Compare Flag 3B
+ 'TIFR3_OCF3A': '$2', # Output Compare Flag 3A
+ 'TIFR3_TOV3': '$1', # Timer/Counter3 Overflow Flag
+
+# Module TIMER_COUNTER_1
+ 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
+ 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
+ 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
+ 'TCCR1A_COM1C': '$c', # Compare Output Mode 1C, bits
+ 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
+ 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
+ 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
+ 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
+ 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
+ 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
+ 'TCCR1C' : '$82', # Timer/Counter 1 Control Regist
+ 'TCCR1C_FOC1A': '$80', # Force Output Compare 1A
+ 'TCCR1C_FOC1B': '$40', # Force Output Compare 1B
+ 'TCCR1C_FOC1C': '$20', # Force Output Compare 1C
+ 'TCNT1' : '$84', # Timer/Counter1 Bytes
+ 'OCR1A' : '$88', # Timer/Counter1 Output Compare
+ 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
+ 'OCR1C' : '$8c', # Timer/Counter1 Output Compare
+ 'ICR1' : '$86', # Timer/Counter1 Input Capture R
+ 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
+ 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
+ 'TIMSK1_OCIE1C': '$8', # Timer/Counter1 Output Compare
+ 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
+ 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
+ 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
+ 'TIFR1' : '$36', # Timer/Counter1 Interrupt Flag
+ 'TIFR1_ICF1': '$20', # Input Capture Flag 1
+ 'TIFR1_OCF1C': '$8', # Output Compare Flag 1C
+ 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
+ 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
+ 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
+
+# Module JTAG
+ 'OCDR' : '$51', # On-Chip Debug Related Register
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_JTD': '$80', # JTAG Interface Disable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+
+# Module EXTERNAL_INTERRUPT
+ 'EICRA' : '$69', # External Interrupt Control Reg
+ 'EICRA_ISC3': '$c0', # External Interrupt Sense Contr
+ 'EICRA_ISC2': '$30', # External Interrupt Sense Contr
+ 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
+ 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
+ 'EICRB' : '$6a', # External Interrupt Control Reg
+ 'EICRB_ISC7': '$c0', # External Interrupt 7-4 Sense C
+ 'EICRB_ISC6': '$30', # External Interrupt 7-4 Sense C
+ 'EICRB_ISC5': '$c', # External Interrupt 7-4 Sense C
+ 'EICRB_ISC4': '$3', # External Interrupt 7-4 Sense C
+ 'EIMSK' : '$3d', # External Interrupt Mask Regist
+ 'EIMSK_INT': '$ff', # External Interrupt Request 7 E
+ 'EIFR' : '$3c', # External Interrupt Flag Regist
+ 'EIFR_INTF': '$ff', # External Interrupt Flags
+ 'PCMSK0' : '$6b', # Pin Change Mask Register 0
+ 'PCIFR' : '$3b', # Pin Change Interrupt Flag Regi
+ 'PCIFR_PCIF0': '$1', # Pin Change Interrupt Flag 0
+ 'PCICR' : '$68', # Pin Change Interrupt Control R
+ 'PCICR_PCIE0': '$1', # Pin Change Interrupt Enable 0
+
+# Module TIMER_COUNTER_4
+ 'TCCR4A' : '$c0', # Timer/Counter4 Control Registe
+ 'TCCR4A_COM4A': '$c0', # Compare Output Mode 1A, bits
+ 'TCCR4A_COM4B': '$30', # Compare Output Mode 4B, bits
+ 'TCCR4A_FOC4A': '$8', # Force Output Compare Match 4A
+ 'TCCR4A_FOC4B': '$4', # Force Output Compare Match 4B
+ 'TCCR4A_PWM4A': '$2', #
+ 'TCCR4A_PWM4B': '$1', #
+ 'TCCR4B' : '$c1', # Timer/Counter4 Control Registe
+ 'TCCR4B_PWM4X': '$80', # PWM Inversion Mode
+ 'TCCR4B_PSR4': '$40', # Prescaler Reset Timer/Counter
+ 'TCCR4B_DTPS4': '$30', # Dead Time Prescaler Bits
+ 'TCCR4B_CS4': '$f', # Clock Select Bits
+ 'TCCR4C' : '$c2', # Timer/Counter 4 Control Regist
+ 'TCCR4C_COM4A1S': '$80', # Comparator A Output Mode
+ 'TCCR4C_COM4A0S': '$40', # Comparator A Output Mode
+ 'TCCR4C_COM4B1S': '$20', # Comparator B Output Mode
+ 'TCCR4C_COM4B0S': '$10', # Comparator B Output Mode
+ 'TCCR4C_COM4D': '$c', # Comparator D Output Mode
+ 'TCCR4C_FOC4D': '$2', # Force Output Compare Match 4D
+ 'TCCR4C_PWM4D': '$1', # Pulse Width Modulator D Enable
+ 'TCCR4D' : '$c3', # Timer/Counter 4 Control Regist
+ 'TCCR4D_FPIE4': '$80', # Fault Protection Interrupt Ena
+ 'TCCR4D_FPEN4': '$40', # Fault Protection Mode Enable
+ 'TCCR4D_FPNC4': '$20', # Fault Protection Noise Cancele
+ 'TCCR4D_FPES4': '$10', # Fault Protection Edge Select
+ 'TCCR4D_FPAC4': '$8', # Fault Protection Analog Compar
+ 'TCCR4D_FPF4': '$4', # Fault Protection Interrupt Fla
+ 'TCCR4D_WGM4': '$3', # Waveform Generation Mode bits
+ 'TCCR4E' : '$c4', # Timer/Counter 4 Control Regist
+ 'TCCR4E_TLOCK4': '$80', # Register Update Lock
+ 'TCCR4E_ENHC4': '$40', # Enhanced Compare/PWM Mode
+ 'TCCR4E_OC4OE': '$3f', # Output Compare Override Enable
+ 'TCNT4' : '$be', # Timer/Counter4 Low Bytes
+ 'TC4H' : '$bf', # Timer/Counter4
+ 'OCR4A' : '$cf', # Timer/Counter4 Output Compare
+ 'OCR4B' : '$d0', # Timer/Counter4 Output Compare
+ 'OCR4C' : '$d1', # Timer/Counter4 Output Compare
+ 'OCR4D' : '$d2', # Timer/Counter4 Output Compare
+ 'TIMSK4' : '$72', # Timer/Counter4 Interrupt Mask
+ 'TIMSK4_OCIE4D': '$80', # Timer/Counter4 Output Compare
+ 'TIMSK4_OCIE4A': '$40', # Timer/Counter4 Output Compare
+ 'TIMSK4_OCIE4B': '$20', # Timer/Counter4 Output Compare
+ 'TIMSK4_TOIE4': '$4', # Timer/Counter4 Overflow Interr
+ 'TIFR4' : '$39', # Timer/Counter4 Interrupt Flag
+ 'TIFR4_OCF4D': '$80', # Output Compare Flag 4D
+ 'TIFR4_OCF4A': '$40', # Output Compare Flag 4A
+ 'TIFR4_OCF4B': '$20', # Output Compare Flag 4B
+ 'TIFR4_TOV4': '$4', # Timer/Counter4 Overflow Flag
+ 'DT4' : '$d4', # Timer/Counter 4 Dead Time Valu
+ 'DT4_DT4L': '$ff', # Timer/Counter 4 Dead Time Valu
+
+# Module PORTB
+ 'PORTB' : '$25', # Port B Data Register
+ 'DDRB' : '$24', # Port B Data Direction Register
+ 'PINB' : '$23', # Port B Input Pins
+
+# Module PORTC
+ 'PORTC' : '$28', # Port C Data Register
+ 'DDRC' : '$27', # Port C Data Direction Register
+ 'PINC' : '$26', # Port C Input Pins
+
+# Module PORTE
+ 'PORTE' : '$2e', # Data Register, Port E
+ 'DDRE' : '$2d', # Data Direction Register, Port
+ 'PINE' : '$2c', # Input Pins, Port E
+
+# Module PORTF
+ 'PORTF' : '$31', # Data Register, Port F
+ 'DDRF' : '$30', # Data Direction Register, Port
+ 'PINF' : '$2f', # Input Pins, Port F
+
+# Module TWI
+ 'TWAMR' : '$bd', # TWI (Slave) Address Mask Regis
+ 'TWAMR_TWAM': '$fe', #
+ 'TWBR' : '$b8', # TWI Bit Rate register
+ 'TWCR' : '$bc', # TWI Control Register
+ 'TWCR_TWINT': '$80', # TWI Interrupt Flag
+ 'TWCR_TWEA': '$40', # TWI Enable Acknowledge Bit
+ 'TWCR_TWSTA': '$20', # TWI Start Condition Bit
+ 'TWCR_TWSTO': '$10', # TWI Stop Condition Bit
+ 'TWCR_TWWC': '$8', # TWI Write Collition Flag
+ 'TWCR_TWEN': '$4', # TWI Enable Bit
+ 'TWCR_TWIE': '$1', # TWI Interrupt Enable
+ 'TWSR' : '$b9', # TWI Status Register
+ 'TWSR_TWS': '$f8', # TWI Status
+ 'TWSR_TWPS': '$3', # TWI Prescaler
+ 'TWDR' : '$bb', # TWI Data register
+ 'TWAR' : '$ba', # TWI (Slave) Address register
+ 'TWAR_TWA': '$fe', # TWI (Slave) Address register B
+ 'TWAR_TWGCE': '$1', # TWI General Call Recognition E
+
+# Module AD_CONVERTER
+ 'ADMUX' : '$7c', # The ADC multiplexer Selection
+ 'ADMUX_REFS': '$c0', # Reference Selection Bits
+ 'ADMUX_ADLAR': '$20', # Left Adjust Result
+ 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
+ 'ADCSRA' : '$7a', # The ADC Control and Status reg
+ 'ADCSRA_ADEN': '$80', # ADC Enable
+ 'ADCSRA_ADSC': '$40', # ADC Start Conversion
+ 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
+ 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
+ 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
+ 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
+ 'ADC' : '$78', # ADC Data Register Bytes
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ADHSM': '$80', # ADC High Speed Mode
+ 'ADCSRB_MUX5': '$20', # Analog Channel and Gain Select
+ 'ADCSRB_ADTS': '$17', # ADC Auto Trigger Sources
+ 'DIDR0' : '$7e', # Digital Input Disable Register
+ 'DIDR0_ADC7D': '$80', # ADC7 Digital input Disable
+ 'DIDR0_ADC6D': '$40', # ADC6 Digital input Disable
+ 'DIDR0_ADC5D': '$20', # ADC5 Digital input Disable
+ 'DIDR0_ADC4D': '$10', # ADC4 Digital input Disable
+ 'DIDR0_ADC3D': '$8', # ADC3 Digital input Disable
+ 'DIDR0_ADC2D': '$4', # ADC2 Digital input Disable
+ 'DIDR0_ADC1D': '$2', # ADC1 Digital input Disable
+ 'DIDR0_ADC0D': '$1', # ADC0 Digital input Disable
+ 'DIDR2' : '$7d', # Digital Input Disable Register
+ 'DIDR2_ADC13D': '$20', # ADC13 Digital input Disable
+ 'DIDR2_ADC12D': '$10', # ADC12 Digital input Disable
+ 'DIDR2_ADC11D': '$8', # ADC11 Digital input Disable
+ 'DIDR2_ADC10D': '$4', # ADC10 Digital input Disable
+ 'DIDR2_ADC9D': '$2', # ADC9 Digital input Disable
+ 'DIDR2_ADC8D': '$1', # ADC8 Digital input Disable
+
+# Module ANALOG_COMPARATOR
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
+ 'ACSR' : '$50', # Analog Comparator Control And
+ 'ACSR_ACD': '$80', # Analog Comparator Disable
+ 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
+ 'ACSR_ACO': '$20', # Analog Compare Output
+ 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
+ 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
+ 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
+ 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
+ 'DIDR1' : '$7f', #
+ 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
+ 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
+
+# Module CPU
+ 'SREG' : '$5f', # Status Register
+ 'SREG_I': '$80', # Global Interrupt Enable
+ 'SREG_T': '$40', # Bit Copy Storage
+ 'SREG_H': '$20', # Half Carry Flag
+ 'SREG_S': '$10', # Sign Bit
+ 'SREG_V': '$8', # Two's Complement Overflow Flag
+ 'SREG_N': '$4', # Negative Flag
+ 'SREG_Z': '$2', # Zero Flag
+ 'SREG_C': '$1', # Carry Flag
+ 'SP' : '$5d', # Stack Pointer
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_JTD': '$80', # JTAG Interface Disable
+ 'MCUCR_PUD': '$10', # Pull-up disable
+ 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
+ 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+ 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
+ 'MCUSR_BORF': '$4', # Brown-out Reset Flag
+ 'MCUSR_EXTRF': '$2', # External Reset Flag
+ 'MCUSR_PORF': '$1', # Power-on reset flag
+ 'OSCCAL' : '$66', # Oscillator Calibration Value
+ 'RCCTRL' : '$67', # Oscillator Control Register
+ 'RCCTRL_RCFREQ': '$1', #
+ 'CLKPR' : '$61', #
+ 'CLKPR_CLKPCE': '$80', #
+ 'CLKPR_CLKPS': '$f', #
+ 'SMCR' : '$53', # Sleep Mode Control Register
+ 'SMCR_SM': '$e', # Sleep Mode Select bits
+ 'SMCR_SE': '$1', # Sleep Enable
+ 'EIND' : '$5c', # Extended Indirect Register
+ 'GPIOR2' : '$4b', # General Purpose IO Register 2
+ 'GPIOR2_GPIOR': '$ff', # General Purpose IO Register 2
+ 'GPIOR1' : '$4a', # General Purpose IO Register 1
+ 'GPIOR1_GPIOR': '$ff', # General Purpose IO Register 1
+ 'GPIOR0' : '$3e', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR07': '$80', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR06': '$40', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR05': '$20', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR04': '$10', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR03': '$8', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR02': '$4', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR01': '$2', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR00': '$1', # General Purpose IO Register 0
+ 'PRR1' : '$65', # Power Reduction Register1
+ 'PRR1_PRUSB': '$80', # Power Reduction USB
+ 'PRR1_PRTIM3': '$8', # Power Reduction Timer/Counter3
+ 'PRR1_PRUSART1': '$1', # Power Reduction USART1
+ 'PRR0' : '$64', # Power Reduction Register0
+ 'PRR0_PRTWI': '$80', # Power Reduction TWI
+ 'PRR0_PRTIM2': '$40', # Power Reduction Timer/Counter2
+ 'PRR0_PRTIM0': '$20', # Power Reduction Timer/Counter0
+ 'PRR0_PRTIM1': '$8', # Power Reduction Timer/Counter1
+ 'PRR0_PRSPI': '$4', # Power Reduction Serial Periphe
+ 'PRR0_PRUSART0': '$2', # Power Reduction USART
+ 'PRR0_PRADC': '$1', # Power Reduction ADC
+ 'CLKSTA' : '$c7', #
+ 'CLKSTA_RCON': '$2', #
+ 'CLKSTA_EXTON': '$1', #
+ 'CLKSEL1' : '$c6', #
+ 'CLKSEL1_RCCKSEL': '$f0', #
+ 'CLKSEL1_EXCKSEL': '$f', #
+ 'CLKSEL0' : '$c5', #
+ 'CLKSEL0_RCSUT': '$c0', #
+ 'CLKSEL0_EXSUT': '$30', #
+ 'CLKSEL0_RCE': '$8', #
+ 'CLKSEL0_EXTE': '$4', #
+ 'CLKSEL0_CLKS': '$1', #
+
+# Module PLL
+ 'PLLCSR' : '$49', # PLL Status and Control registe
+ 'PLLCSR_PINDIV': '$10', # PLL prescaler Bit 2
+ 'PLLCSR_PLLE': '$2', # PLL Enable Bit
+ 'PLLCSR_PLOCK': '$1', # PLL Lock Status Bit
+ 'PLLFRQ' : '$52', # PLL Frequency Control Register
+ 'PLLFRQ_PINMUX': '$80', #
+ 'PLLFRQ_PLLUSB': '$40', #
+ 'PLLFRQ_PLLTM': '$30', #
+ 'PLLFRQ_PDIV': '$f', #
+
+# Module USB_DEVICE
+ 'UEINT' : '$f4', #
+ 'UEBCHX' : '$f3', #
+ 'UEBCLX' : '$f2', #
+ 'UEDATX' : '$f1', #
+ 'UEDATX_DAT': '$ff', #
+ 'UEIENX' : '$f0', #
+ 'UEIENX_FLERRE': '$80', #
+ 'UEIENX_NAKINE': '$40', #
+ 'UEIENX_NAKOUTE': '$10', #
+ 'UEIENX_RXSTPE': '$8', #
+ 'UEIENX_RXOUTE': '$4', #
+ 'UEIENX_STALLEDE': '$2', #
+ 'UEIENX_TXINE': '$1', #
+ 'UESTA1X' : '$ef', #
+ 'UESTA1X_CTRLDIR': '$4', #
+ 'UESTA1X_CURRBK': '$3', #
+ 'UESTA0X' : '$ee', #
+ 'UESTA0X_CFGOK': '$80', #
+ 'UESTA0X_OVERFI': '$40', #
+ 'UESTA0X_UNDERFI': '$20', #
+ 'UESTA0X_DTSEQ': '$c', #
+ 'UESTA0X_NBUSYBK': '$3', #
+ 'UECFG1X' : '$ed', #
+ 'UECFG1X_EPSIZE': '$70', #
+ 'UECFG1X_EPBK': '$c', #
+ 'UECFG1X_ALLOC': '$2', #
+ 'UECFG0X' : '$ec', #
+ 'UECFG0X_EPTYPE': '$c0', #
+ 'UECFG0X_EPDIR': '$1', #
+ 'UECONX' : '$eb', #
+ 'UECONX_STALLRQ': '$20', #
+ 'UECONX_STALLRQC': '$10', #
+ 'UECONX_RSTDT': '$8', #
+ 'UECONX_EPEN': '$1', #
+ 'UERST' : '$ea', #
+ 'UERST_EPRST': '$7f', #
+ 'UENUM' : '$e9', #
+ 'UEINTX' : '$e8', #
+ 'UEINTX_FIFOCON': '$80', #
+ 'UEINTX_NAKINI': '$40', #
+ 'UEINTX_RWAL': '$20', #
+ 'UEINTX_NAKOUTI': '$10', #
+ 'UEINTX_RXSTPI': '$8', #
+ 'UEINTX_RXOUTI': '$4', #
+ 'UEINTX_STALLEDI': '$2', #
+ 'UEINTX_TXINI': '$1', #
+ 'UDMFN' : '$e6', #
+ 'UDMFN_FNCERR': '$10', #
+ 'UDFNUM' : '$e4', #
+ 'UDADDR' : '$e3', #
+ 'UDADDR_ADDEN': '$80', #
+ 'UDADDR_UADD': '$7f', #
+ 'UDIEN' : '$e2', #
+ 'UDIEN_UPRSME': '$40', #
+ 'UDIEN_EORSME': '$20', #
+ 'UDIEN_WAKEUPE': '$10', #
+ 'UDIEN_EORSTE': '$8', #
+ 'UDIEN_SOFE': '$4', #
+ 'UDIEN_SUSPE': '$1', #
+ 'UDINT' : '$e1', #
+ 'UDINT_UPRSMI': '$40', #
+ 'UDINT_EORSMI': '$20', #
+ 'UDINT_WAKEUPI': '$10', #
+ 'UDINT_EORSTI': '$8', #
+ 'UDINT_SOFI': '$4', #
+ 'UDINT_SUSPI': '$1', #
+ 'UDCON' : '$e0', #
+ 'UDCON_LSM': '$4', # USB low speed mode
+ 'UDCON_RSTCPU': '$8', #
+ 'UDCON_RMWKUP': '$2', #
+ 'UDCON_DETACH': '$1', #
+ 'USBCON' : '$d8', # USB General Control Register
+ 'USBCON_USBE': '$80', #
+ 'USBCON_FRZCLK': '$20', #
+ 'USBCON_OTGPADE': '$10', #
+ 'USBCON_VBUSTE': '$1', #
+ 'USBINT' : '$da', #
+ 'USBINT_VBUSTI': '$1', #
+ 'USBSTA' : '$d9', #
+ 'USBSTA_SPEED': '$8', #
+ 'USBSTA_VBUS': '$1', #
+ 'UHWCON' : '$d7', #
+ 'UHWCON_UVREGE': '$1', #
+
+ '__amforth_dummy':'0'
+}
diff --git a/amforth-6.5/avr8/devices/atmega32u4/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega32u4/words/no-jtag.asm
new file mode 100644
index 0000000..352a4bb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega32u4/words/no-jtag.asm
@@ -0,0 +1,14 @@
+; ( -- )
+; ( -- )
+; MCU
+; disable jtag at runtime
+VE_NOJTAG:
+ .dw $FF05
+ .db "-jtag",0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOJTAG
+XT_NOJTAG:
+ .dw PFA_NOJTAG
+PFA_NOJTAG:
+
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega32u4/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega32u4/words/no-wdt.asm
new file mode 100644
index 0000000..ff6ddd1
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega32u4/words/no-wdt.asm
@@ -0,0 +1,34 @@
+; ( -- )
+; MCU
+; disable watch dog timer at runtime
+VE_NOWDT:
+ .dw $ff04
+ .db "-wdt"
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOWDT
+XT_NOWDT:
+ .dw PFA_NOWDT
+PFA_NOWDT:
+
+ in temp1,SREG
+ push temp1
+ ; Turn always off global interrupt.
+ cli
+ ; Reset Watchdog Timer
+ wdr
+ ; Clear WDRF in MCUSR
+ in temp1, MCUSR
+ andi temp1, (0xff & (0<<WDRF))
+ out MCUSR, temp1
+ ; Write logical one to WDCE and WDE
+ ; Keep old prescaler setting to prevent unintentional time-out
+ in_ temp1, WDTCSR
+ ori temp1, (1<<WDCE) | (1<<WDE)
+ out_ WDTCSR, temp1
+ ; Turn off WDT
+ ldi temp1, (0<<WDE)
+ out_ WDTCSR, temp1
+ ; restore status register
+ pop temp1
+ out SREG,temp1
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega32u4/words/sleep.asm b/amforth-6.5/avr8/devices/atmega32u4/words/sleep.asm
new file mode 100644
index 0000000..256249c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega32u4/words/sleep.asm
@@ -0,0 +1,19 @@
+; ( mode -- )
+; MCU
+; put the controller into the specified sleep mode
+VE_SLEEP:
+ .dw $ff05
+ .db "sleep", 0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_SLEEP
+XT_SLEEP:
+ .dw PFA_SLEEP
+PFA_SLEEP:
+ andi tosl, 7 ; leave only legal mode bits
+ lsl tosl ; move to correct location (bits 3-1)
+ ori tosl, 1 ; set the SE bit
+ out_ SMCR, tosl ; set the sleep config
+ sleep ; nighty-night
+ out_ SMCR, zerol ; 0 protects against accidental sleeps
+ loadtos ; pop argument from stack
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega32u6/atmega32u6.frt b/amforth-6.5/avr8/devices/atmega32u6/atmega32u6.frt
new file mode 100644
index 0000000..2040dc3
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega32u6/atmega32u6.frt
@@ -0,0 +1,233 @@
+\ Partname: ATmega32U6
+\ Built using part description XML file version 1
+\ generated automatically
+
+hex
+
+\ AD_CONVERTER
+79 constant ADCH \ ADC Data Register High Byte
+78 constant ADCL \ ADC Data Register Low Byte
+7A constant ADCSRA \ The ADC Control and Status register
+7B constant ADCSRB \ ADC Control and Status Register B
+7C constant ADMUX \ The ADC multiplexer Selection Register
+7E constant DIDR0 \ Digital Input Disable Register 1
+
+\ ANALOG_COMPARATOR
+50 constant ACSR \ Analog Comparator Control And Status Register
+7F constant DIDR1 \
+
+\ BOOT_LOAD
+57 constant SPMCSR \ Store Program Memory Control Register
+
+\ CPU
+61 constant CLKPR \
+3E constant GPIOR0 \ General Purpose IO Register 0
+4A constant GPIOR1 \ General Purpose IO Register 1
+4B constant GPIOR2 \ General Purpose IO Register 2
+55 constant MCUCR \ MCU Control Register
+54 constant MCUSR \ MCU Status Register
+66 constant OSCCAL \ Oscillator Calibration Value
+64 constant PRR0 \ Power Reduction Register0
+65 constant PRR1 \ Power Reduction Register1
+53 constant SMCR \ Sleep Mode Control Register
+5E constant SPH \ Stack Pointer High
+5D constant SPL \ Stack Pointer Low
+5F constant SREG \ Status Register
+74 constant XMCRA \ External Memory Control Register A
+75 constant XMCRB \ External Memory Control Register B
+
+\ EEPROM
+42 constant EEARH \ EEPROM Address Register Low Byte
+41 constant EEARL \ EEPROM Address Register Low Byte
+3F constant EECR \ EEPROM Control Register
+40 constant EEDR \ EEPROM Data Register
+
+\ EXTERNAL_INTERRUPT
+69 constant EICRA \ External Interrupt Control Register A
+6A constant EICRB \ External Interrupt Control Register B
+3C constant EIFR \ External Interrupt Flag Register
+3D constant EIMSK \ External Interrupt Mask Register
+68 constant PCICR \ Pin Change Interrupt Control Register
+3B constant PCIFR \ Pin Change Interrupt Flag Register
+6B constant PCMSK0 \ Pin Change Mask Register 0
+
+\ JTAG
+51 constant OCDR \ On-Chip Debug Related Register in I/O Memory
+
+\ PLL
+49 constant PLLCSR \ PLL Status and Control register
+
+\ PORTA
+21 constant DDRA \ Port A Data Direction Register
+20 constant PINA \ Port A Input Pins
+22 constant PORTA \ Port A Data Register
+
+\ PORTB
+24 constant DDRB \ Port B Data Direction Register
+23 constant PINB \ Port B Input Pins
+25 constant PORTB \ Port B Data Register
+
+\ PORTC
+27 constant DDRC \ Port C Data Direction Register
+26 constant PINC \ Port C Input Pins
+28 constant PORTC \ Port C Data Register
+
+\ PORTD
+2A constant DDRD \ Port D Data Direction Register
+29 constant PIND \ Port D Input Pins
+2B constant PORTD \ Port D Data Register
+
+\ PORTE
+2D constant DDRE \ Data Direction Register, Port E
+2C constant PINE \ Input Pins, Port E
+2E constant PORTE \ Data Register, Port E
+
+\ PORTF
+30 constant DDRF \ Data Direction Register, Port F
+2F constant PINF \ Input Pins, Port F
+31 constant PORTF \ Data Register, Port F
+
+\ SPI
+4C constant SPCR \ SPI Control Register
+4E constant SPDR \ SPI Data Register
+4D constant SPSR \ SPI Status Register
+
+\ TIMER_COUNTER_0
+43 constant GTCCR \ General Timer/Counter Control Register
+47 constant OCR0A \ Timer/Counter0 Output Compare Register
+48 constant OCR0B \ Timer/Counter0 Output Compare Register
+44 constant TCCR0A \ Timer/Counter Control Register A
+45 constant TCCR0B \ Timer/Counter Control Register B
+46 constant TCNT0 \ Timer/Counter0
+35 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
+6E constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
+
+\ TIMER_COUNTER_1
+87 constant ICR1H \ Timer/Counter1 Input Capture Register High Byte
+86 constant ICR1L \ Timer/Counter1 Input Capture Register Low Byte
+89 constant OCR1AH \ Timer/Counter1 Output Compare Register A High Byte
+88 constant OCR1AL \ Timer/Counter1 Output Compare Register A Low Byte
+8B constant OCR1BH \ Timer/Counter1 Output Compare Register B High Byte
+8A constant OCR1BL \ Timer/Counter1 Output Compare Register B Low Byte
+8D constant OCR1CH \ Timer/Counter1 Output Compare Register C High Byte
+8C constant OCR1CL \ Timer/Counter1 Output Compare Register C Low Byte
+80 constant TCCR1A \ Timer/Counter1 Control Register A
+81 constant TCCR1B \ Timer/Counter1 Control Register B
+82 constant TCCR1C \ Timer/Counter 1 Control Register C
+85 constant TCNT1H \ Timer/Counter1 High Byte
+84 constant TCNT1L \ Timer/Counter1 Low Byte
+36 constant TIFR1 \ Timer/Counter1 Interrupt Flag register
+6F constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
+
+\ TIMER_COUNTER_2
+B6 constant ASSR \ Asynchronous Status Register
+B3 constant OCR2A \ Timer/Counter2 Output Compare Register A
+B4 constant OCR2B \ Timer/Counter2 Output Compare Register B
+B0 constant TCCR2A \ Timer/Counter2 Control Register A
+B1 constant TCCR2B \ Timer/Counter2 Control Register B
+B2 constant TCNT2 \ Timer/Counter2
+37 constant TIFR2 \ Timer/Counter Interrupt Flag Register
+70 constant TIMSK2 \ Timer/Counter Interrupt Mask register
+
+\ TIMER_COUNTER_3
+97 constant ICR3H \ Timer/Counter3 Input Capture Register High Byte
+96 constant ICR3L \ Timer/Counter3 Input Capture Register Low Byte
+99 constant OCR3AH \ Timer/Counter3 Output Compare Register A High Byte
+98 constant OCR3AL \ Timer/Counter3 Output Compare Register A Low Byte
+9B constant OCR3BH \ Timer/Counter3 Output Compare Register B High Byte
+9A constant OCR3BL \ Timer/Counter3 Output Compare Register B Low Byte
+9D constant OCR3CH \ Timer/Counter3 Output Compare Register B High Byte
+9C constant OCR3CL \ Timer/Counter3 Output Compare Register B Low Byte
+90 constant TCCR3A \ Timer/Counter3 Control Register A
+91 constant TCCR3B \ Timer/Counter3 Control Register B
+92 constant TCCR3C \ Timer/Counter 3 Control Register C
+95 constant TCNT3H \ Timer/Counter3 High Byte
+94 constant TCNT3L \ Timer/Counter3 Low Byte
+38 constant TIFR3 \ Timer/Counter3 Interrupt Flag register
+71 constant TIMSK3 \ Timer/Counter3 Interrupt Mask Register
+
+\ TWI
+BD constant TWAMR \ TWI (Slave) Address Mask Register
+BA constant TWAR \ TWI (Slave) Address register
+B8 constant TWBR \ TWI Bit Rate register
+BC constant TWCR \ TWI Control Register
+BB constant TWDR \ TWI Data register
+B9 constant TWSR \ TWI Status Register
+
+\ USART1
+CD constant UBRR1H \ USART Baud Rate Register High Byte
+CC constant UBRR1L \ USART Baud Rate Register Low Byte
+C8 constant UCSR1A \ USART Control and Status Register A
+C9 constant UCSR1B \ USART Control and Status Register B
+CA constant UCSR1C \ USART Control and Status Register C
+CE constant UDR1 \ USART I/O Data Register
+
+\ USB_DEVICE
+E3 constant UDADDR \
+E0 constant UDCON \
+E5 constant UDFNUMH \
+E4 constant UDFNUML \
+E2 constant UDIEN \
+E1 constant UDINT \
+E6 constant UDMFN \
+F3 constant UEBCHX \
+F2 constant UEBCLX \
+EC constant UECFG0X \
+ED constant UECFG1X \
+EB constant UECONX \
+F1 constant UEDATX \
+F0 constant UEIENX \
+F4 constant UEINT \
+E8 constant UEINTX \
+E9 constant UENUM \
+EA constant UERST \
+EE constant UESTA0X \
+EF constant UESTA1X \
+
+\ USB_GLOBAL
+D7 constant UHWCON \ USB Hardware Configuration Register
+D8 constant USBCON \ USB General Control Register
+DA constant USBINT \
+D9 constant USBSTA \
+
+\ WATCHDOG
+60 constant WDTCSR \ Watchdog Timer Control Register
+
+\ Interrupts
+002 constant INT0Addr \ External Interrupt Request 0
+004 constant INT1Addr \ External Interrupt Request 1
+006 constant INT2Addr \ External Interrupt Request 2
+008 constant INT3Addr \ External Interrupt Request 3
+00A constant INT4Addr \ External Interrupt Request 4
+00C constant INT5Addr \ External Interrupt Request 5
+00E constant INT6Addr \ External Interrupt Request 6
+010 constant INT7Addr \ External Interrupt Request 7
+012 constant PCINT0Addr \ Pin Change Interrupt Request 0
+014 constant USB_GENAddr \ USB General Interrupt Request
+016 constant USB_COMAddr \ USB Endpoint/Pipe Interrupt Communication Reque
+018 constant WDTAddr \ Watchdog Time-out Interrupt
+01A constant TIMER2_COMPAAddr \ Timer/Counter2 Compare Match A
+01C constant TIMER2_COMPBAddr \ Timer/Counter2 Compare Match B
+01E constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
+020 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+022 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
+024 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
+026 constant TIMER1_COMPCAddr \ Timer/Counter1 Compare Match C
+028 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+02A constant TIMER0_COMPAAddr \ Timer/Counter0 Compare Match A
+02C constant TIMER0_COMPBAddr \ Timer/Counter0 Compare Match B
+02E constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
+030 constant SPI_STCAddr \ SPI Serial Transfer Complete
+032 constant USART1_RXAddr \ USART1, Rx Complete
+034 constant USART1_UDREAddr \ USART1 Data register Empty
+036 constant USART1_TXAddr \ USART1, Tx Complete
+038 constant ANALOG_COMPAddr \ Analog Comparator
+03A constant ADCAddr \ ADC Conversion Complete
+03C constant EE_READYAddr \ EEPROM Ready
+03E constant TIMER3_CAPTAddr \ Timer/Counter3 Capture Event
+040 constant TIMER3_COMPAAddr \ Timer/Counter3 Compare Match A
+042 constant TIMER3_COMPBAddr \ Timer/Counter3 Compare Match B
+044 constant TIMER3_COMPCAddr \ Timer/Counter3 Compare Match C
+046 constant TIMER3_OVFAddr \ Timer/Counter3 Overflow
+048 constant TWIAddr \ 2-wire Serial Interface
+04A constant SPM_READYAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/atmega32u6/device.asm b/amforth-6.5/avr8/devices/atmega32u6/device.asm
new file mode 100644
index 0000000..851ac95
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega32u6/device.asm
@@ -0,0 +1,155 @@
+; Partname: ATmega32U6
+; Built using part description XML file version 1
+; generated automatically, do not edit
+
+.nolist
+ .include "m32U6def.inc"
+.list
+
+.equ ramstart = $100
+.equ CELLSIZE = 2
+.macro readflashcell
+ lsl zl
+ rol zh
+ lpm @0, Z+
+ lpm @1, Z+
+.endmacro
+.macro writeflashcell
+ lsl zl
+ rol zh
+.endmacro
+
+; the following definitions are shortcuts for the respective forth source segments if set to 1
+.set WANT_AD_CONVERTER = 0
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_BOOT_LOAD = 0
+.set WANT_CPU = 0
+.set WANT_EEPROM = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_JTAG = 0
+.set WANT_PLL = 0
+.set WANT_PORTA = 0
+.set WANT_PORTB = 0
+.set WANT_PORTC = 0
+.set WANT_PORTD = 0
+.set WANT_PORTE = 0
+.set WANT_PORTF = 0
+.set WANT_SPI = 0
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_TIMER_COUNTER_2 = 0
+.set WANT_TIMER_COUNTER_3 = 0
+.set WANT_TWI = 0
+.set WANT_USART1 = 0
+.set WANT_USB_DEVICE = 0
+.set WANT_USB_GLOBAL = 0
+.set WANT_WATCHDOG = 0
+
+
+.ifndef SPMEN
+ .equ SPMEN = SELFPRGEN
+.endif
+
+.ifndef SPMCSR
+ .equ SPMCSR = SPMCR
+.endif
+
+.ifndef EEPE
+ .equ EEPE = EEWE
+.endif
+
+.ifndef EEMPE
+ .equ EEMPE = EEMWE
+.endif
+.equ intvecsize = 2 ; please verify; flash size: 32768 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.equ INTVECTORS = 38
+.org $002
+ rcall isr ; External Interrupt Request 0
+.org $004
+ rcall isr ; External Interrupt Request 1
+.org $006
+ rcall isr ; External Interrupt Request 2
+.org $008
+ rcall isr ; External Interrupt Request 3
+.org $00A
+ rcall isr ; External Interrupt Request 4
+.org $00C
+ rcall isr ; External Interrupt Request 5
+.org $00E
+ rcall isr ; External Interrupt Request 6
+.org $010
+ rcall isr ; External Interrupt Request 7
+.org $012
+ rcall isr ; Pin Change Interrupt Request 0
+.org $014
+ rcall isr ; USB General Interrupt Request
+.org $016
+ rcall isr ; USB Endpoint/Pipe Interrupt Communication Request
+.org $018
+ rcall isr ; Watchdog Time-out Interrupt
+.org $01A
+ rcall isr ; Timer/Counter2 Compare Match A
+.org $01C
+ rcall isr ; Timer/Counter2 Compare Match B
+.org $01E
+ rcall isr ; Timer/Counter2 Overflow
+.org $020
+ rcall isr ; Timer/Counter1 Capture Event
+.org $022
+ rcall isr ; Timer/Counter1 Compare Match A
+.org $024
+ rcall isr ; Timer/Counter1 Compare Match B
+.org $026
+ rcall isr ; Timer/Counter1 Compare Match C
+.org $028
+ rcall isr ; Timer/Counter1 Overflow
+.org $02A
+ rcall isr ; Timer/Counter0 Compare Match A
+.org $02C
+ rcall isr ; Timer/Counter0 Compare Match B
+.org $02E
+ rcall isr ; Timer/Counter0 Overflow
+.org $030
+ rcall isr ; SPI Serial Transfer Complete
+.org $032
+ rcall isr ; USART1, Rx Complete
+.org $034
+ rcall isr ; USART1 Data register Empty
+.org $036
+ rcall isr ; USART1, Tx Complete
+.org $038
+ rcall isr ; Analog Comparator
+.org $03A
+ rcall isr ; ADC Conversion Complete
+.org $03C
+ rcall isr ; EEPROM Ready
+.org $03E
+ rcall isr ; Timer/Counter3 Capture Event
+.org $040
+ rcall isr ; Timer/Counter3 Compare Match A
+.org $042
+ rcall isr ; Timer/Counter3 Compare Match B
+.org $044
+ rcall isr ; Timer/Counter3 Compare Match C
+.org $046
+ rcall isr ; Timer/Counter3 Overflow
+.org $048
+ rcall isr ; 2-wire Serial Interface
+.org $04A
+ rcall isr ; Store Program Memory Read
+.nooverlap
+mcu_info:
+mcu_ramsize:
+ .dw 2560
+mcu_eepromsize:
+ .dw 1024
+mcu_maxdp:
+ .dw 14336 ; minimum of 0x3800 (from XML) and 0xffff
+mcu_numints:
+ .dw 38
+mcu_name:
+ .dw 10
+ .db "ATmega32U6"
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega32u6/device.inc b/amforth-6.5/avr8/devices/atmega32u6/device.inc
new file mode 100644
index 0000000..3944355
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega32u6/device.inc
@@ -0,0 +1,1839 @@
+; Partname: ATmega32U6
+; Built using part description XML file version 1
+; generated automatically, no not edit
+
+; ********
+.if WANT_AD_CONVERTER == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register High Byte
+VE_ADCH:
+ .dw $ff04
+ .db "ADCH"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCH
+XT_ADCH:
+ .dw PFA_DOVARIABLE
+PFA_ADCH:
+ .dw $79
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register Low Byte
+VE_ADCL:
+ .dw $ff04
+ .db "ADCL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCL
+XT_ADCL:
+ .dw PFA_DOVARIABLE
+PFA_ADCL:
+ .dw $78
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register
+VE_ADCSRA:
+ .dw $ff06
+ .db "ADCSRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRA
+XT_ADCSRA:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRA:
+ .dw $7A
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Control and Status Register B
+VE_ADCSRB:
+ .dw $ff06
+ .db "ADCSRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRB
+XT_ADCSRB:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRB:
+ .dw $7B
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC multiplexer Selection Register
+VE_ADMUX:
+ .dw $ff05
+ .db "ADMUX",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADMUX
+XT_ADMUX:
+ .dw PFA_DOVARIABLE
+PFA_ADMUX:
+ .dw $7C
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 1
+VE_DIDR0:
+ .dw $ff05
+ .db "DIDR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR0
+XT_DIDR0:
+ .dw PFA_DOVARIABLE
+PFA_DIDR0:
+ .dw $7E
+
+.endif
+
+; ********
+.if WANT_ANALOG_COMPARATOR == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Control And Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw $50
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_DIDR1:
+ .dw $ff05
+ .db "DIDR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR1
+XT_DIDR1:
+ .dw PFA_DOVARIABLE
+PFA_DIDR1:
+ .dw $7F
+
+.endif
+
+; ********
+.if WANT_BOOT_LOAD == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control Register
+VE_SPMCSR:
+ .dw $ff06
+ .db "SPMCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCSR
+XT_SPMCSR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCSR:
+ .dw $57
+
+.endif
+
+; ********
+.if WANT_CPU == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_CLKPR:
+ .dw $ff05
+ .db "CLKPR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKPR
+XT_CLKPR:
+ .dw PFA_DOVARIABLE
+PFA_CLKPR:
+ .dw $61
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 0
+VE_GPIOR0:
+ .dw $ff06
+ .db "GPIOR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR0
+XT_GPIOR0:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR0:
+ .dw $3E
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 1
+VE_GPIOR1:
+ .dw $ff06
+ .db "GPIOR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR1
+XT_GPIOR1:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR1:
+ .dw $4A
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 2
+VE_GPIOR2:
+ .dw $ff06
+ .db "GPIOR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR2
+XT_GPIOR2:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR2:
+ .dw $4B
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw $55
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Status Register
+VE_MCUSR:
+ .dw $ff05
+ .db "MCUSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUSR
+XT_MCUSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUSR:
+ .dw $54
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Calibration Value
+VE_OSCCAL:
+ .dw $ff06
+ .db "OSCCAL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSCCAL
+XT_OSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_OSCCAL:
+ .dw $66
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register0
+VE_PRR0:
+ .dw $ff04
+ .db "PRR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR0
+XT_PRR0:
+ .dw PFA_DOVARIABLE
+PFA_PRR0:
+ .dw $64
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register1
+VE_PRR1:
+ .dw $ff04
+ .db "PRR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR1
+XT_PRR1:
+ .dw PFA_DOVARIABLE
+PFA_PRR1:
+ .dw $65
+; ( -- addr ) System Constant
+; R( -- )
+; Sleep Mode Control Register
+VE_SMCR:
+ .dw $ff04
+ .db "SMCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SMCR
+XT_SMCR:
+ .dw PFA_DOVARIABLE
+PFA_SMCR:
+ .dw $53
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer High
+VE_SPH:
+ .dw $ff03
+ .db "SPH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPH
+XT_SPH:
+ .dw PFA_DOVARIABLE
+PFA_SPH:
+ .dw $5E
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer Low
+VE_SPL:
+ .dw $ff03
+ .db "SPL",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPL
+XT_SPL:
+ .dw PFA_DOVARIABLE
+PFA_SPL:
+ .dw $5D
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw $5F
+; ( -- addr ) System Constant
+; R( -- )
+; External Memory Control Register A
+VE_XMCRA:
+ .dw $ff05
+ .db "XMCRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_XMCRA
+XT_XMCRA:
+ .dw PFA_DOVARIABLE
+PFA_XMCRA:
+ .dw $74
+; ( -- addr ) System Constant
+; R( -- )
+; External Memory Control Register B
+VE_XMCRB:
+ .dw $ff05
+ .db "XMCRB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_XMCRB
+XT_XMCRB:
+ .dw PFA_DOVARIABLE
+PFA_XMCRB:
+ .dw $75
+
+.endif
+
+; ********
+.if WANT_EEPROM == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Address Register Low Byte
+VE_EEARH:
+ .dw $ff05
+ .db "EEARH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEARH
+XT_EEARH:
+ .dw PFA_DOVARIABLE
+PFA_EEARH:
+ .dw $42
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Address Register Low Byte
+VE_EEARL:
+ .dw $ff05
+ .db "EEARL",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEARL
+XT_EEARL:
+ .dw PFA_DOVARIABLE
+PFA_EEARL:
+ .dw $41
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw $3F
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw $40
+
+.endif
+
+; ********
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register A
+VE_EICRA:
+ .dw $ff05
+ .db "EICRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRA
+XT_EICRA:
+ .dw PFA_DOVARIABLE
+PFA_EICRA:
+ .dw $69
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register B
+VE_EICRB:
+ .dw $ff05
+ .db "EICRB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRB
+XT_EICRB:
+ .dw PFA_DOVARIABLE
+PFA_EICRB:
+ .dw $6A
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Flag Register
+VE_EIFR:
+ .dw $ff04
+ .db "EIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIFR
+XT_EIFR:
+ .dw PFA_DOVARIABLE
+PFA_EIFR:
+ .dw $3C
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Mask Register
+VE_EIMSK:
+ .dw $ff05
+ .db "EIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIMSK
+XT_EIMSK:
+ .dw PFA_DOVARIABLE
+PFA_EIMSK:
+ .dw $3D
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Interrupt Control Register
+VE_PCICR:
+ .dw $ff05
+ .db "PCICR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCICR
+XT_PCICR:
+ .dw PFA_DOVARIABLE
+PFA_PCICR:
+ .dw $68
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Interrupt Flag Register
+VE_PCIFR:
+ .dw $ff05
+ .db "PCIFR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCIFR
+XT_PCIFR:
+ .dw PFA_DOVARIABLE
+PFA_PCIFR:
+ .dw $3B
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 0
+VE_PCMSK0:
+ .dw $ff06
+ .db "PCMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK0
+XT_PCMSK0:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK0:
+ .dw $6B
+
+.endif
+
+; ********
+.if WANT_JTAG == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; On-Chip Debug Related Register in I/O Memory
+VE_OCDR:
+ .dw $ff04
+ .db "OCDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCDR
+XT_OCDR:
+ .dw PFA_DOVARIABLE
+PFA_OCDR:
+ .dw $51
+
+.endif
+
+; ********
+.if WANT_PLL == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; PLL Status and Control register
+VE_PLLCSR:
+ .dw $ff06
+ .db "PLLCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PLLCSR
+XT_PLLCSR:
+ .dw PFA_DOVARIABLE
+PFA_PLLCSR:
+ .dw $49
+
+.endif
+
+; ********
+.if WANT_PORTA == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Direction Register
+VE_DDRA:
+ .dw $ff04
+ .db "DDRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRA
+XT_DDRA:
+ .dw PFA_DOVARIABLE
+PFA_DDRA:
+ .dw $21
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Input Pins
+VE_PINA:
+ .dw $ff04
+ .db "PINA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINA
+XT_PINA:
+ .dw PFA_DOVARIABLE
+PFA_PINA:
+ .dw $20
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Register
+VE_PORTA:
+ .dw $ff05
+ .db "PORTA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTA
+XT_PORTA:
+ .dw PFA_DOVARIABLE
+PFA_PORTA:
+ .dw $22
+
+.endif
+
+; ********
+.if WANT_PORTB == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw $24
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw $23
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw $25
+
+.endif
+
+; ********
+.if WANT_PORTC == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Direction Register
+VE_DDRC:
+ .dw $ff04
+ .db "DDRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRC
+XT_DDRC:
+ .dw PFA_DOVARIABLE
+PFA_DDRC:
+ .dw $27
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Input Pins
+VE_PINC:
+ .dw $ff04
+ .db "PINC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINC
+XT_PINC:
+ .dw PFA_DOVARIABLE
+PFA_PINC:
+ .dw $26
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Register
+VE_PORTC:
+ .dw $ff05
+ .db "PORTC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTC
+XT_PORTC:
+ .dw PFA_DOVARIABLE
+PFA_PORTC:
+ .dw $28
+
+.endif
+
+; ********
+.if WANT_PORTD == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw $2A
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw $29
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw $2B
+
+.endif
+
+; ********
+.if WANT_PORTE == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port E
+VE_DDRE:
+ .dw $ff04
+ .db "DDRE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRE
+XT_DDRE:
+ .dw PFA_DOVARIABLE
+PFA_DDRE:
+ .dw $2D
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port E
+VE_PINE:
+ .dw $ff04
+ .db "PINE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINE
+XT_PINE:
+ .dw PFA_DOVARIABLE
+PFA_PINE:
+ .dw $2C
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port E
+VE_PORTE:
+ .dw $ff05
+ .db "PORTE",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTE
+XT_PORTE:
+ .dw PFA_DOVARIABLE
+PFA_PORTE:
+ .dw $2E
+
+.endif
+
+; ********
+.if WANT_PORTF == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port F
+VE_DDRF:
+ .dw $ff04
+ .db "DDRF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRF
+XT_DDRF:
+ .dw PFA_DOVARIABLE
+PFA_DDRF:
+ .dw $30
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port F
+VE_PINF:
+ .dw $ff04
+ .db "PINF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINF
+XT_PINF:
+ .dw PFA_DOVARIABLE
+PFA_PINF:
+ .dw $2F
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port F
+VE_PORTF:
+ .dw $ff05
+ .db "PORTF",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTF
+XT_PORTF:
+ .dw PFA_DOVARIABLE
+PFA_PORTF:
+ .dw $31
+
+.endif
+
+; ********
+.if WANT_SPI == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR:
+ .dw $ff04
+ .db "SPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR
+XT_SPCR:
+ .dw PFA_DOVARIABLE
+PFA_SPCR:
+ .dw $4C
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR:
+ .dw $ff04
+ .db "SPDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR
+XT_SPDR:
+ .dw PFA_DOVARIABLE
+PFA_SPDR:
+ .dw $4E
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR:
+ .dw $ff04
+ .db "SPSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR
+XT_SPSR:
+ .dw PFA_DOVARIABLE
+PFA_SPSR:
+ .dw $4D
+
+.endif
+
+; ********
+.if WANT_TIMER_COUNTER_0 == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; General Timer/Counter Control Register
+VE_GTCCR:
+ .dw $ff05
+ .db "GTCCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GTCCR
+XT_GTCCR:
+ .dw PFA_DOVARIABLE
+PFA_GTCCR:
+ .dw $43
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0A:
+ .dw $ff05
+ .db "OCR0A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0A
+XT_OCR0A:
+ .dw PFA_DOVARIABLE
+PFA_OCR0A:
+ .dw $47
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0B:
+ .dw $ff05
+ .db "OCR0B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0B
+XT_OCR0B:
+ .dw PFA_DOVARIABLE
+PFA_OCR0B:
+ .dw $48
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register A
+VE_TCCR0A:
+ .dw $ff06
+ .db "TCCR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0A
+XT_TCCR0A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0A:
+ .dw $44
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register B
+VE_TCCR0B:
+ .dw $ff06
+ .db "TCCR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0B
+XT_TCCR0B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0B:
+ .dw $45
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw $46
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Flag register
+VE_TIFR0:
+ .dw $ff05
+ .db "TIFR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR0
+XT_TIFR0:
+ .dw PFA_DOVARIABLE
+PFA_TIFR0:
+ .dw $35
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Mask Register
+VE_TIMSK0:
+ .dw $ff06
+ .db "TIMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK0
+XT_TIMSK0:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK0:
+ .dw $6E
+
+.endif
+
+; ********
+.if WANT_TIMER_COUNTER_1 == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register High Byte
+VE_ICR1H:
+ .dw $ff05
+ .db "ICR1H",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1H
+XT_ICR1H:
+ .dw PFA_DOVARIABLE
+PFA_ICR1H:
+ .dw $87
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Low Byte
+VE_ICR1L:
+ .dw $ff05
+ .db "ICR1L",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1L
+XT_ICR1L:
+ .dw PFA_DOVARIABLE
+PFA_ICR1L:
+ .dw $86
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register A High Byte
+VE_OCR1AH:
+ .dw $ff06
+ .db "OCR1AH"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1AH
+XT_OCR1AH:
+ .dw PFA_DOVARIABLE
+PFA_OCR1AH:
+ .dw $89
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register A Low Byte
+VE_OCR1AL:
+ .dw $ff06
+ .db "OCR1AL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1AL
+XT_OCR1AL:
+ .dw PFA_DOVARIABLE
+PFA_OCR1AL:
+ .dw $88
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register B High Byte
+VE_OCR1BH:
+ .dw $ff06
+ .db "OCR1BH"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1BH
+XT_OCR1BH:
+ .dw PFA_DOVARIABLE
+PFA_OCR1BH:
+ .dw $8B
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register B Low Byte
+VE_OCR1BL:
+ .dw $ff06
+ .db "OCR1BL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1BL
+XT_OCR1BL:
+ .dw PFA_DOVARIABLE
+PFA_OCR1BL:
+ .dw $8A
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register C High Byte
+VE_OCR1CH:
+ .dw $ff06
+ .db "OCR1CH"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1CH
+XT_OCR1CH:
+ .dw PFA_DOVARIABLE
+PFA_OCR1CH:
+ .dw $8D
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register C Low Byte
+VE_OCR1CL:
+ .dw $ff06
+ .db "OCR1CL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1CL
+XT_OCR1CL:
+ .dw PFA_DOVARIABLE
+PFA_OCR1CL:
+ .dw $8C
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw $80
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw $81
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter 1 Control Register C
+VE_TCCR1C:
+ .dw $ff06
+ .db "TCCR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1C
+XT_TCCR1C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1C:
+ .dw $82
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 High Byte
+VE_TCNT1H:
+ .dw $ff06
+ .db "TCNT1H"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1H
+XT_TCNT1H:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1H:
+ .dw $85
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Low Byte
+VE_TCNT1L:
+ .dw $ff06
+ .db "TCNT1L"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1L
+XT_TCNT1L:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1L:
+ .dw $84
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Flag register
+VE_TIFR1:
+ .dw $ff05
+ .db "TIFR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR1
+XT_TIFR1:
+ .dw PFA_DOVARIABLE
+PFA_TIFR1:
+ .dw $36
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Mask Register
+VE_TIMSK1:
+ .dw $ff06
+ .db "TIMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK1
+XT_TIMSK1:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK1:
+ .dw $6F
+
+.endif
+
+; ********
+.if WANT_TIMER_COUNTER_2 == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Asynchronous Status Register
+VE_ASSR:
+ .dw $ff04
+ .db "ASSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ASSR
+XT_ASSR:
+ .dw PFA_DOVARIABLE
+PFA_ASSR:
+ .dw $B6
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register A
+VE_OCR2A:
+ .dw $ff05
+ .db "OCR2A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2A
+XT_OCR2A:
+ .dw PFA_DOVARIABLE
+PFA_OCR2A:
+ .dw $B3
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register B
+VE_OCR2B:
+ .dw $ff05
+ .db "OCR2B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2B
+XT_OCR2B:
+ .dw PFA_DOVARIABLE
+PFA_OCR2B:
+ .dw $B4
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register A
+VE_TCCR2A:
+ .dw $ff06
+ .db "TCCR2A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2A
+XT_TCCR2A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2A:
+ .dw $B0
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register B
+VE_TCCR2B:
+ .dw $ff06
+ .db "TCCR2B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2B
+XT_TCCR2B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2B:
+ .dw $B1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2
+VE_TCNT2:
+ .dw $ff05
+ .db "TCNT2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT2
+XT_TCNT2:
+ .dw PFA_DOVARIABLE
+PFA_TCNT2:
+ .dw $B2
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Flag Register
+VE_TIFR2:
+ .dw $ff05
+ .db "TIFR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR2
+XT_TIFR2:
+ .dw PFA_DOVARIABLE
+PFA_TIFR2:
+ .dw $37
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Mask register
+VE_TIMSK2:
+ .dw $ff06
+ .db "TIMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK2
+XT_TIMSK2:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK2:
+ .dw $70
+
+.endif
+
+; ********
+.if WANT_TIMER_COUNTER_3 == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Input Capture Register High Byte
+VE_ICR3H:
+ .dw $ff05
+ .db "ICR3H",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR3H
+XT_ICR3H:
+ .dw PFA_DOVARIABLE
+PFA_ICR3H:
+ .dw $97
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Input Capture Register Low Byte
+VE_ICR3L:
+ .dw $ff05
+ .db "ICR3L",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR3L
+XT_ICR3L:
+ .dw PFA_DOVARIABLE
+PFA_ICR3L:
+ .dw $96
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Output Compare Register A High Byte
+VE_OCR3AH:
+ .dw $ff06
+ .db "OCR3AH"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR3AH
+XT_OCR3AH:
+ .dw PFA_DOVARIABLE
+PFA_OCR3AH:
+ .dw $99
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Output Compare Register A Low Byte
+VE_OCR3AL:
+ .dw $ff06
+ .db "OCR3AL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR3AL
+XT_OCR3AL:
+ .dw PFA_DOVARIABLE
+PFA_OCR3AL:
+ .dw $98
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Output Compare Register B High Byte
+VE_OCR3BH:
+ .dw $ff06
+ .db "OCR3BH"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR3BH
+XT_OCR3BH:
+ .dw PFA_DOVARIABLE
+PFA_OCR3BH:
+ .dw $9B
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Output Compare Register B Low Byte
+VE_OCR3BL:
+ .dw $ff06
+ .db "OCR3BL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR3BL
+XT_OCR3BL:
+ .dw PFA_DOVARIABLE
+PFA_OCR3BL:
+ .dw $9A
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Output Compare Register B High Byte
+VE_OCR3CH:
+ .dw $ff06
+ .db "OCR3CH"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR3CH
+XT_OCR3CH:
+ .dw PFA_DOVARIABLE
+PFA_OCR3CH:
+ .dw $9D
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Output Compare Register B Low Byte
+VE_OCR3CL:
+ .dw $ff06
+ .db "OCR3CL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR3CL
+XT_OCR3CL:
+ .dw PFA_DOVARIABLE
+PFA_OCR3CL:
+ .dw $9C
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Control Register A
+VE_TCCR3A:
+ .dw $ff06
+ .db "TCCR3A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR3A
+XT_TCCR3A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR3A:
+ .dw $90
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Control Register B
+VE_TCCR3B:
+ .dw $ff06
+ .db "TCCR3B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR3B
+XT_TCCR3B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR3B:
+ .dw $91
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter 3 Control Register C
+VE_TCCR3C:
+ .dw $ff06
+ .db "TCCR3C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR3C
+XT_TCCR3C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR3C:
+ .dw $92
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 High Byte
+VE_TCNT3H:
+ .dw $ff06
+ .db "TCNT3H"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT3H
+XT_TCNT3H:
+ .dw PFA_DOVARIABLE
+PFA_TCNT3H:
+ .dw $95
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Low Byte
+VE_TCNT3L:
+ .dw $ff06
+ .db "TCNT3L"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT3L
+XT_TCNT3L:
+ .dw PFA_DOVARIABLE
+PFA_TCNT3L:
+ .dw $94
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Interrupt Flag register
+VE_TIFR3:
+ .dw $ff05
+ .db "TIFR3",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR3
+XT_TIFR3:
+ .dw PFA_DOVARIABLE
+PFA_TIFR3:
+ .dw $38
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Interrupt Mask Register
+VE_TIMSK3:
+ .dw $ff06
+ .db "TIMSK3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK3
+XT_TIMSK3:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK3:
+ .dw $71
+
+.endif
+
+; ********
+.if WANT_TWI == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; TWI (Slave) Address Mask Register
+VE_TWAMR:
+ .dw $ff05
+ .db "TWAMR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWAMR
+XT_TWAMR:
+ .dw PFA_DOVARIABLE
+PFA_TWAMR:
+ .dw $BD
+; ( -- addr ) System Constant
+; R( -- )
+; TWI (Slave) Address register
+VE_TWAR:
+ .dw $ff04
+ .db "TWAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWAR
+XT_TWAR:
+ .dw PFA_DOVARIABLE
+PFA_TWAR:
+ .dw $BA
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Bit Rate register
+VE_TWBR:
+ .dw $ff04
+ .db "TWBR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWBR
+XT_TWBR:
+ .dw PFA_DOVARIABLE
+PFA_TWBR:
+ .dw $B8
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Control Register
+VE_TWCR:
+ .dw $ff04
+ .db "TWCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWCR
+XT_TWCR:
+ .dw PFA_DOVARIABLE
+PFA_TWCR:
+ .dw $BC
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Data register
+VE_TWDR:
+ .dw $ff04
+ .db "TWDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWDR
+XT_TWDR:
+ .dw PFA_DOVARIABLE
+PFA_TWDR:
+ .dw $BB
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Status Register
+VE_TWSR:
+ .dw $ff04
+ .db "TWSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWSR
+XT_TWSR:
+ .dw PFA_DOVARIABLE
+PFA_TWSR:
+ .dw $B9
+
+.endif
+
+; ********
+.if WANT_USART1 == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register High Byte
+VE_UBRR1H:
+ .dw $ff06
+ .db "UBRR1H"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR1H
+XT_UBRR1H:
+ .dw PFA_DOVARIABLE
+PFA_UBRR1H:
+ .dw $CD
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Low Byte
+VE_UBRR1L:
+ .dw $ff06
+ .db "UBRR1L"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR1L
+XT_UBRR1L:
+ .dw PFA_DOVARIABLE
+PFA_UBRR1L:
+ .dw $CC
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR1A:
+ .dw $ff06
+ .db "UCSR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1A
+XT_UCSR1A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1A:
+ .dw $C8
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR1B:
+ .dw $ff06
+ .db "UCSR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1B
+XT_UCSR1B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1B:
+ .dw $C9
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR1C:
+ .dw $ff06
+ .db "UCSR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1C
+XT_UCSR1C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1C:
+ .dw $CA
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR1:
+ .dw $ff04
+ .db "UDR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR1
+XT_UDR1:
+ .dw PFA_DOVARIABLE
+PFA_UDR1:
+ .dw $CE
+
+.endif
+
+; ********
+.if WANT_USB_DEVICE == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UDADDR:
+ .dw $ff06
+ .db "UDADDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDADDR
+XT_UDADDR:
+ .dw PFA_DOVARIABLE
+PFA_UDADDR:
+ .dw $E3
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UDCON:
+ .dw $ff05
+ .db "UDCON",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDCON
+XT_UDCON:
+ .dw PFA_DOVARIABLE
+PFA_UDCON:
+ .dw $E0
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UDFNUMH:
+ .dw $ff07
+ .db "UDFNUMH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDFNUMH
+XT_UDFNUMH:
+ .dw PFA_DOVARIABLE
+PFA_UDFNUMH:
+ .dw $E5
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UDFNUML:
+ .dw $ff07
+ .db "UDFNUML",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDFNUML
+XT_UDFNUML:
+ .dw PFA_DOVARIABLE
+PFA_UDFNUML:
+ .dw $E4
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UDIEN:
+ .dw $ff05
+ .db "UDIEN",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDIEN
+XT_UDIEN:
+ .dw PFA_DOVARIABLE
+PFA_UDIEN:
+ .dw $E2
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UDINT:
+ .dw $ff05
+ .db "UDINT",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDINT
+XT_UDINT:
+ .dw PFA_DOVARIABLE
+PFA_UDINT:
+ .dw $E1
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UDMFN:
+ .dw $ff05
+ .db "UDMFN",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDMFN
+XT_UDMFN:
+ .dw PFA_DOVARIABLE
+PFA_UDMFN:
+ .dw $E6
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UEBCHX:
+ .dw $ff06
+ .db "UEBCHX"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UEBCHX
+XT_UEBCHX:
+ .dw PFA_DOVARIABLE
+PFA_UEBCHX:
+ .dw $F3
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UEBCLX:
+ .dw $ff06
+ .db "UEBCLX"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UEBCLX
+XT_UEBCLX:
+ .dw PFA_DOVARIABLE
+PFA_UEBCLX:
+ .dw $F2
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UECFG0X:
+ .dw $ff07
+ .db "UECFG0X",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UECFG0X
+XT_UECFG0X:
+ .dw PFA_DOVARIABLE
+PFA_UECFG0X:
+ .dw $EC
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UECFG1X:
+ .dw $ff07
+ .db "UECFG1X",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UECFG1X
+XT_UECFG1X:
+ .dw PFA_DOVARIABLE
+PFA_UECFG1X:
+ .dw $ED
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UECONX:
+ .dw $ff06
+ .db "UECONX"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UECONX
+XT_UECONX:
+ .dw PFA_DOVARIABLE
+PFA_UECONX:
+ .dw $EB
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UEDATX:
+ .dw $ff06
+ .db "UEDATX"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UEDATX
+XT_UEDATX:
+ .dw PFA_DOVARIABLE
+PFA_UEDATX:
+ .dw $F1
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UEIENX:
+ .dw $ff06
+ .db "UEIENX"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UEIENX
+XT_UEIENX:
+ .dw PFA_DOVARIABLE
+PFA_UEIENX:
+ .dw $F0
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UEINT:
+ .dw $ff05
+ .db "UEINT",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UEINT
+XT_UEINT:
+ .dw PFA_DOVARIABLE
+PFA_UEINT:
+ .dw $F4
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UEINTX:
+ .dw $ff06
+ .db "UEINTX"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UEINTX
+XT_UEINTX:
+ .dw PFA_DOVARIABLE
+PFA_UEINTX:
+ .dw $E8
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UENUM:
+ .dw $ff05
+ .db "UENUM",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UENUM
+XT_UENUM:
+ .dw PFA_DOVARIABLE
+PFA_UENUM:
+ .dw $E9
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UERST:
+ .dw $ff05
+ .db "UERST",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UERST
+XT_UERST:
+ .dw PFA_DOVARIABLE
+PFA_UERST:
+ .dw $EA
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UESTA0X:
+ .dw $ff07
+ .db "UESTA0X",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UESTA0X
+XT_UESTA0X:
+ .dw PFA_DOVARIABLE
+PFA_UESTA0X:
+ .dw $EE
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UESTA1X:
+ .dw $ff07
+ .db "UESTA1X",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UESTA1X
+XT_UESTA1X:
+ .dw PFA_DOVARIABLE
+PFA_UESTA1X:
+ .dw $EF
+
+.endif
+
+; ********
+.if WANT_USB_GLOBAL == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; USB Hardware Configuration Register
+VE_UHWCON:
+ .dw $ff06
+ .db "UHWCON"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UHWCON
+XT_UHWCON:
+ .dw PFA_DOVARIABLE
+PFA_UHWCON:
+ .dw $D7
+; ( -- addr ) System Constant
+; R( -- )
+; USB General Control Register
+VE_USBCON:
+ .dw $ff06
+ .db "USBCON"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USBCON
+XT_USBCON:
+ .dw PFA_DOVARIABLE
+PFA_USBCON:
+ .dw $D8
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_USBINT:
+ .dw $ff06
+ .db "USBINT"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USBINT
+XT_USBINT:
+ .dw PFA_DOVARIABLE
+PFA_USBINT:
+ .dw $DA
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_USBSTA:
+ .dw $ff06
+ .db "USBSTA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USBSTA
+XT_USBSTA:
+ .dw PFA_DOVARIABLE
+PFA_USBSTA:
+ .dw $D9
+
+.endif
+
+; ********
+.if WANT_WATCHDOG == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCSR:
+ .dw $ff06
+ .db "WDTCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCSR
+XT_WDTCSR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCSR:
+ .dw $60
+
+.endif
diff --git a/amforth-6.5/avr8/devices/atmega32u6/device.py b/amforth-6.5/avr8/devices/atmega32u6/device.py
new file mode 100644
index 0000000..7a32001
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega32u6/device.py
@@ -0,0 +1,183 @@
+# Partname: ATmega32U6
+# Built using part description XML file version 1
+# generated automatically, do not edit
+MCUREGS = {
+ 'ADCH': '$79',
+ 'ADCL': '$78',
+ 'ADCSRA': '$7A',
+ 'ADCSRB': '$7B',
+ 'ADMUX': '$7C',
+ 'DIDR0': '$7E',
+ 'ACSR': '$50',
+ 'DIDR1': '$7F',
+ 'SPMCSR': '$57',
+ 'CLKPR': '$61',
+ 'GPIOR0': '$3E',
+ 'GPIOR1': '$4A',
+ 'GPIOR2': '$4B',
+ 'MCUCR': '$55',
+ 'MCUSR': '$54',
+ 'OSCCAL': '$66',
+ 'PRR0': '$64',
+ 'PRR1': '$65',
+ 'SMCR': '$53',
+ 'SPH': '$5E',
+ 'SPL': '$5D',
+ 'SREG': '$5F',
+ 'XMCRA': '$74',
+ 'XMCRB': '$75',
+ 'EEARH': '$42',
+ 'EEARL': '$41',
+ 'EECR': '$3F',
+ 'EEDR': '$40',
+ 'EICRA': '$69',
+ 'EICRB': '$6A',
+ 'EIFR': '$3C',
+ 'EIMSK': '$3D',
+ 'PCICR': '$68',
+ 'PCIFR': '$3B',
+ 'PCMSK0': '$6B',
+ 'OCDR': '$51',
+ 'PLLCSR': '$49',
+ 'DDRA': '$21',
+ 'PINA': '$20',
+ 'PORTA': '$22',
+ 'DDRB': '$24',
+ 'PINB': '$23',
+ 'PORTB': '$25',
+ 'DDRC': '$27',
+ 'PINC': '$26',
+ 'PORTC': '$28',
+ 'DDRD': '$2A',
+ 'PIND': '$29',
+ 'PORTD': '$2B',
+ 'DDRE': '$2D',
+ 'PINE': '$2C',
+ 'PORTE': '$2E',
+ 'DDRF': '$30',
+ 'PINF': '$2F',
+ 'PORTF': '$31',
+ 'SPCR': '$4C',
+ 'SPDR': '$4E',
+ 'SPSR': '$4D',
+ 'GTCCR': '$43',
+ 'OCR0A': '$47',
+ 'OCR0B': '$48',
+ 'TCCR0A': '$44',
+ 'TCCR0B': '$45',
+ 'TCNT0': '$46',
+ 'TIFR0': '$35',
+ 'TIMSK0': '$6E',
+ 'ICR1H': '$87',
+ 'ICR1L': '$86',
+ 'OCR1AH': '$89',
+ 'OCR1AL': '$88',
+ 'OCR1BH': '$8B',
+ 'OCR1BL': '$8A',
+ 'OCR1CH': '$8D',
+ 'OCR1CL': '$8C',
+ 'TCCR1A': '$80',
+ 'TCCR1B': '$81',
+ 'TCCR1C': '$82',
+ 'TCNT1H': '$85',
+ 'TCNT1L': '$84',
+ 'TIFR1': '$36',
+ 'TIMSK1': '$6F',
+ 'ASSR': '$B6',
+ 'OCR2A': '$B3',
+ 'OCR2B': '$B4',
+ 'TCCR2A': '$B0',
+ 'TCCR2B': '$B1',
+ 'TCNT2': '$B2',
+ 'TIFR2': '$37',
+ 'TIMSK2': '$70',
+ 'ICR3H': '$97',
+ 'ICR3L': '$96',
+ 'OCR3AH': '$99',
+ 'OCR3AL': '$98',
+ 'OCR3BH': '$9B',
+ 'OCR3BL': '$9A',
+ 'OCR3CH': '$9D',
+ 'OCR3CL': '$9C',
+ 'TCCR3A': '$90',
+ 'TCCR3B': '$91',
+ 'TCCR3C': '$92',
+ 'TCNT3H': '$95',
+ 'TCNT3L': '$94',
+ 'TIFR3': '$38',
+ 'TIMSK3': '$71',
+ 'TWAMR': '$BD',
+ 'TWAR': '$BA',
+ 'TWBR': '$B8',
+ 'TWCR': '$BC',
+ 'TWDR': '$BB',
+ 'TWSR': '$B9',
+ 'UBRR1H': '$CD',
+ 'UBRR1L': '$CC',
+ 'UCSR1A': '$C8',
+ 'UCSR1B': '$C9',
+ 'UCSR1C': '$CA',
+ 'UDR1': '$CE',
+ 'UDADDR': '$E3',
+ 'UDCON': '$E0',
+ 'UDFNUMH': '$E5',
+ 'UDFNUML': '$E4',
+ 'UDIEN': '$E2',
+ 'UDINT': '$E1',
+ 'UDMFN': '$E6',
+ 'UEBCHX': '$F3',
+ 'UEBCLX': '$F2',
+ 'UECFG0X': '$EC',
+ 'UECFG1X': '$ED',
+ 'UECONX': '$EB',
+ 'UEDATX': '$F1',
+ 'UEIENX': '$F0',
+ 'UEINT': '$F4',
+ 'UEINTX': '$E8',
+ 'UENUM': '$E9',
+ 'UERST': '$EA',
+ 'UESTA0X': '$EE',
+ 'UESTA1X': '$EF',
+ 'UHWCON': '$D7',
+ 'USBCON': '$D8',
+ 'USBINT': '$DA',
+ 'USBSTA': '$D9',
+ 'WDTCSR': '$60',
+ 'INT0Addr': '$002',
+ 'INT1Addr': '$004',
+ 'INT2Addr': '$006',
+ 'INT3Addr': '$008',
+ 'INT4Addr': '$00A',
+ 'INT5Addr': '$00C',
+ 'INT6Addr': '$00E',
+ 'INT7Addr': '$010',
+ 'PCINT0Addr': '$012',
+ 'USB_GENAddr': '$014',
+ 'USB_COMAddr': '$016',
+ 'WDTAddr': '$018',
+ 'TIMER2_COMPAAddr': '$01A',
+ 'TIMER2_COMPBAddr': '$01C',
+ 'TIMER2_OVFAddr': '$01E',
+ 'TIMER1_CAPTAddr': '$020',
+ 'TIMER1_COMPAAddr': '$022',
+ 'TIMER1_COMPBAddr': '$024',
+ 'TIMER1_COMPCAddr': '$026',
+ 'TIMER1_OVFAddr': '$028',
+ 'TIMER0_COMPAAddr': '$02A',
+ 'TIMER0_COMPBAddr': '$02C',
+ 'TIMER0_OVFAddr': '$02E',
+ 'SPI_STCAddr': '$030',
+ 'USART1_RXAddr': '$032',
+ 'USART1_UDREAddr': '$034',
+ 'USART1_TXAddr': '$036',
+ 'ANALOG_COMPAddr': '$038',
+ 'ADCAddr': '$03A',
+ 'EE_READYAddr': '$03C',
+ 'TIMER3_CAPTAddr': '$03E',
+ 'TIMER3_COMPAAddr': '$040',
+ 'TIMER3_COMPBAddr': '$042',
+ 'TIMER3_COMPCAddr': '$044',
+ 'TIMER3_OVFAddr': '$046',
+ 'TWIAddr': '$048',
+ 'SPM_READYAddr': '$04A'
+} \ No newline at end of file
diff --git a/amforth-6.5/avr8/devices/atmega406/atmega406.frt b/amforth-6.5/avr8/devices/atmega406/atmega406.frt
new file mode 100644
index 0000000..82320fb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega406/atmega406.frt
@@ -0,0 +1,267 @@
+\ Partname: ATmega406
+\ generated automatically
+
+\ AD_CONVERTER
+&124 constant VADMUX \ The VADC multiplexer Selection Register
+ $0F constant VADMUX_VADMUX \ Analog Channel and Gain Selection Bits
+&120 constant VADC \ VADC Data Register Bytes
+&122 constant VADCSR \ The VADC Control and Status register
+ $08 constant VADCSR_VADEN \ VADC Enable
+ $04 constant VADCSR_VADSC \ VADC Satrt Conversion
+ $02 constant VADCSR_VADCCIF \ VADC Conversion Complete Interrupt Flag
+ $01 constant VADCSR_VADCCIE \ VADC Conversion Complete Interrupt Enable
+\ EXTERNAL_INTERRUPT
+&105 constant EICRA \ External Interrupt Control Register
+ $C0 constant EICRA_ISC3 \ External Interrupt Sense Control 3 Bits
+ $30 constant EICRA_ISC2 \ External Interrupt Sense Control 2 Bits
+ $0C constant EICRA_ISC1 \ External Interrupt Sense Control 1 Bits
+ $03 constant EICRA_ISC0 \ External Interrupt Sense Control 0 Bits
+&61 constant EIMSK \ External Interrupt Mask Register
+ $0F constant EIMSK_INT \ External Interrupt Request 1 Enable
+&60 constant EIFR \ External Interrupt Flag Register
+ $0F constant EIFR_INTF \ External Interrupt Flags
+&104 constant PCICR \ Pin Change Interrupt Control Register
+ $03 constant PCICR_PCIE \ Pin Change Interrupt Enables
+&59 constant PCIFR \ Pin Change Interrupt Flag Register
+ $03 constant PCIFR_PCIF \ Pin Change Interrupt Flags
+&108 constant PCMSK1 \ Pin Change Enable Mask Register 1
+&107 constant PCMSK0 \ Pin Change Enable Mask Register 0
+\ TIMER_COUNTER_1
+&129 constant TCCR1B \ Timer/Counter1 Control Register B
+ $08 constant TCCR1B_CTC1 \ Clear Timer/Counter on Compare Match
+ $07 constant TCCR1B_CS1 \ Clock Select1 bits
+&132 constant TCNT1 \ Timer Counter 1 Bytes
+&136 constant OCR1AL \ Output Compare Register 1A Low byte
+&137 constant OCR1AH \ Output Compare Register 1A High byte
+&111 constant TIMSK1 \ Timer/Counter Interrupt Mask Register
+ $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare Interrupt Enable
+ $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
+&54 constant TIFR1 \ Timer/Counter Interrupt Flag register
+ $02 constant TIFR1_OCF1A \ Timer/Counter1 Output Compare Flag A
+ $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
+&67 constant GTCCR \ General Timer/Counter Control Register
+ $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
+ $01 constant GTCCR_PSRSYNC \ Prescaler Reset
+\ WAKEUP_TIMER
+&98 constant WUTCSR \ Wake-up Timer Control Register
+ $80 constant WUTCSR_WUTIF \ Wake-up Timer Interrupt Flag
+ $40 constant WUTCSR_WUTIE \ Wake-up Timer Interrupt Enable
+ $20 constant WUTCSR_WUTCF \ Wake-up timer Calibration Flag
+ $10 constant WUTCSR_WUTR \ Wake-up Timer Reset
+ $08 constant WUTCSR_WUTE \ Wake-up Timer Enable
+ $07 constant WUTCSR_WUTP \ Wake-up Timer Prescaler Bits
+\ BATTERY_PROTECTION
+&248 constant BPPLR \ Battery Protection Parameter Lock Register
+ $02 constant BPPLR_BPPLE \ Battery Protection Parameter Lock Enable
+ $01 constant BPPLR_BPPL \ Battery Protection Parameter Lock
+&247 constant BPCR \ Battery Protection Control Register
+ $08 constant BPCR_DUVD \
+ $04 constant BPCR_SCD \
+ $02 constant BPCR_DCD \
+ $01 constant BPCR_CCD \
+&246 constant CBPTR \ Current Battery Protection Timing Register
+ $F0 constant CBPTR_SCPT \
+ $0F constant CBPTR_OCPT \
+&245 constant BPOCD \ Battery Protection OverCurrent Detection Level Register
+ $F0 constant BPOCD_DCDL \
+ $0F constant BPOCD_CCDL \
+&244 constant BPSCD \ Battery Protection Short-Circuit Detection Level Register
+ $0F constant BPSCD_SCDL \
+&243 constant BPDUV \ Battery Protection Deep Under Voltage Register
+ $30 constant BPDUV_DUVT \
+ $0F constant BPDUV_DUDL \
+&242 constant BPIR \ Battery Protection Interrupt Register
+ $80 constant BPIR_DUVIF \ Deep Under-voltage Early Warning Interrupt Flag
+ $40 constant BPIR_COCIF \ Charge Over-current Protection Activated Interrupt Flag
+ $20 constant BPIR_DOCIF \
+ $10 constant BPIR_SCIF \
+ $08 constant BPIR_DUVIE \ Deep Under-voltage Early Warning Interrupt Enable
+ $04 constant BPIR_COCIE \
+ $02 constant BPIR_DOCIE \
+ $01 constant BPIR_SCIE \
+\ FET
+&240 constant FCSR \
+ $20 constant FCSR_PWMOC \ Pulse Width Modulation of OC output
+ $10 constant FCSR_PWMOPC \ Pulse Width Modulation Modulation of OPC output
+ $08 constant FCSR_CPS \ Current Protection Status
+ $04 constant FCSR_DFE \ Discharge FET Enable
+ $02 constant FCSR_CFE \ Charge FET Enable
+ $01 constant FCSR_PFD \ Precharge FET disable
+\ COULOMB_COUNTER
+&228 constant CADCSRA \ CC-ADC Control and Status Register A
+ $80 constant CADCSRA_CADEN \ When the CADEN bit is cleared (zero), the CC-ADC is disabled. When the CADEN bit is set (one), the CC-ADC will continuously measure the voltage drop over the external sense resistor RSENSE. In Power-down, only the Regular Current detection is active. In Power-off, the CC-ADC is always disabled.
+ $20 constant CADCSRA_CADUB \ CC_ADC Update Busy
+ $18 constant CADCSRA_CADAS \ CC_ADC Accumulate Current Select Bits
+ $06 constant CADCSRA_CADSI \ The CADSI bits determine the current sampling interval for the Regular Current detection in Power-down mode. The actual settings remain to be determined.
+ $01 constant CADCSRA_CADSE \ When the CADSE bit is written to one, the ongoing CC-ADC conversion is aborted, and the CC-ADC enters Regular Current detection mode.
+&229 constant CADCSRB \ CC-ADC Control and Status Register B
+ $40 constant CADCSRB_CADACIE \
+ $20 constant CADCSRB_CADRCIE \ Regular Current Interrupt Enable
+ $10 constant CADCSRB_CADICIE \ CAD Instantenous Current Interrupt Enable
+ $04 constant CADCSRB_CADACIF \ CC-ADC Accumulate Current Interrupt Flag
+ $02 constant CADCSRB_CADRCIF \ CC-ADC Accumulate Current Interrupt Flag
+ $01 constant CADCSRB_CADICIF \ CC-ADC Instantaneous Current Interrupt Flag
+&232 constant CADIC \ CC-ADC Instantaneous Current
+&227 constant CADAC3 \ ADC Accumulate Current
+&226 constant CADAC2 \ ADC Accumulate Current
+&225 constant CADAC1 \ ADC Accumulate Current
+&224 constant CADAC0 \ ADC Accumulate Current
+&230 constant CADRCC \ CC-ADC Regular Charge Current
+&231 constant CADRDC \ CC-ADC Regular Discharge Current
+\ CELL_BALANCING
+&241 constant CBCR \ Cell Balancing Control Register
+ $0F constant CBCR_CBE \ Cell Balancing Enables
+\ CPU
+&95 constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ $08 constant SREG_V \ Two's Complement Overflow Flag
+ $04 constant SREG_N \ Negative Flag
+ $02 constant SREG_Z \ Zero Flag
+ $01 constant SREG_C \ Carry Flag
+&93 constant SP \ Stack Pointer
+&85 constant MCUCR \ MCU Control Register
+ $80 constant MCUCR_JTD \ JTAG Disable
+ $10 constant MCUCR_PUD \ Pull-up disable
+ $02 constant MCUCR_IVSEL \ Interrupt Vector Select
+ $01 constant MCUCR_IVCE \ Interrupt Vector Change Enable
+&84 constant MCUSR \ MCU Status Register
+ $10 constant MCUSR_JTRF \ JTAG Reset Flag
+ $08 constant MCUSR_WDRF \ Watchdog Reset Flag
+ $04 constant MCUSR_BODRF \ Brown-out Reset Flag
+ $02 constant MCUSR_EXTRF \ External Reset Flag
+ $01 constant MCUSR_PORF \ Power-on reset flag
+&102 constant FOSCCAL \ Fast Oscillator Calibration Value
+&83 constant SMCR \ Sleep Mode Control Register
+ $0E constant SMCR_SM \ Sleep Mode Select bits
+ $01 constant SMCR_SE \ Sleep Enable
+&75 constant GPIOR2 \ General Purpose IO Register 2
+&74 constant GPIOR1 \ General Purpose IO Register 1
+&62 constant GPIOR0 \ General Purpose IO Register 0
+&192 constant CCSR \ Clock Control and Status Register
+ $02 constant CCSR_XOE \ 32 kHz Crystal Oscillator Enable
+ $01 constant CCSR_ACS \ Asynchronous Clock Select
+&126 constant DIDR0 \ Digital Input Disable Register
+&100 constant PRR0 \ Power Reduction Register 0
+ $08 constant PRR0_PRTWI \ Power Reduction TWI
+ $04 constant PRR0_PRTIM1 \ Power Reduction Timer/Counter1
+ $02 constant PRR0_PRTIM0 \ Power Reduction Timer/Counter0
+ $01 constant PRR0_PRVADC \ Power Reduction V-ADC
+\ WATCHDOG
+&96 constant WDTCSR \ Watchdog Timer Control Register
+ $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Flag
+ $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Enable
+ $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
+ $10 constant WDTCSR_WDCE \ Watchdog Change Enable
+ $08 constant WDTCSR_WDE \ Watch Dog Enable
+\ TIMER_COUNTER_0
+&68 constant TCCR0A \ Timer/Counter0 Control Register
+ $C0 constant TCCR0A_COM0A \ Force Output Compare
+ $30 constant TCCR0A_COM0B \
+ $03 constant TCCR0A_WGM0 \ Clock Select0 bits
+&69 constant TCCR0B \ Timer/Counter0 Control Register
+ $80 constant TCCR0B_FOC0A \ Force Output Compare
+ $40 constant TCCR0B_FOC0B \ Waveform Generation Mode
+ $08 constant TCCR0B_WGM02 \
+ $07 constant TCCR0B_CS0 \ Clock Select0 bits
+&70 constant TCNT0 \ Timer Counter 0
+&71 constant OCR0A \ Output compare Register A
+ $FF constant OCR0A_OCR0A \
+&72 constant OCR0B \ Output compare Register B
+ $FF constant OCR0B_OCR0B \
+&110 constant TIMSK0 \ Timer/Counter Interrupt Mask Register
+ $04 constant TIMSK0_OCIE0B \ Output Compare Interrupt Enable
+ $02 constant TIMSK0_OCIE0A \ Output Compare Interrupt Enable
+ $01 constant TIMSK0_TOIE0 \ Overflow Interrupt Enable
+&53 constant TIFR0 \ Timer/Counter Interrupt Flag register
+ $04 constant TIFR0_OCF0B \ Output Compare Flag
+ $02 constant TIFR0_OCF0A \ Output Compare Flag
+ $01 constant TIFR0_TOV0 \ Overflow Flag
+\ PORTA
+&34 constant PORTA \ Port A Data Register
+&33 constant DDRA \ Port A Data Direction Register
+&32 constant PINA \ Port A Input Pins
+\ PORTB
+&37 constant PORTB \ Port B Data Register
+&36 constant DDRB \ Port B Data Direction Register
+&35 constant PINB \ Port B Input Pins
+\ PORTC
+&40 constant PORTC \ Port C Data Register
+\ PORTD
+&43 constant PORTD \ Data Register, Port D
+&42 constant DDRD \ Data Direction Register, Port D
+&41 constant PIND \ Input Pins, Port D
+\ BOOT_LOAD
+&87 constant SPMCSR \ Store Program Memory Control Register
+ $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
+ $20 constant SPMCSR_SIGRD \ Signature Row Read
+ $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
+ $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
+ $04 constant SPMCSR_PGWRT \ Page Write
+ $02 constant SPMCSR_PGERS \ Page Erase
+ $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
+\ TWI
+&190 constant TWBCSR \ TWI Bus Control and Status Register
+ $80 constant TWBCSR_TWBCIF \ TWI Bus Connect/Disconnect Interrupt Flag
+ $40 constant TWBCSR_TWBCIE \ TWI Bus Connect/Disconnect Interrupt Enable
+ $06 constant TWBCSR_TWBDT \ TWI Bus Disconnect Time-out Period
+ $01 constant TWBCSR_TWBCIP \ TWI Bus Connect/Disconnect Interrupt Polarity
+&189 constant TWAMR \ TWI (Slave) Address Mask Register
+ $FE constant TWAMR_TWAM \
+&184 constant TWBR \ TWI Bit Rate register
+&188 constant TWCR \ TWI Control Register
+ $80 constant TWCR_TWINT \ TWI Interrupt Flag
+ $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
+ $20 constant TWCR_TWSTA \ TWI Start Condition Bit
+ $10 constant TWCR_TWSTO \ TWI Stop Condition Bit
+ $08 constant TWCR_TWWC \ TWI Write Collition Flag
+ $04 constant TWCR_TWEN \ TWI Enable Bit
+ $01 constant TWCR_TWIE \ TWI Interrupt Enable
+&185 constant TWSR \ TWI Status Register
+ $F8 constant TWSR_TWS \ TWI Status
+ $03 constant TWSR_TWPS \ TWI Prescaler
+&187 constant TWDR \ TWI Data register
+&186 constant TWAR \ TWI (Slave) Address register
+ $FE constant TWAR_TWA \ TWI (Slave) Address register Bits
+ $01 constant TWAR_TWGCE \ TWI General Call Recognition Enable Bit
+\ BANDGAP
+&209 constant BGCRR \ Bandgap Calibration of Resistor Ladder
+&208 constant BGCCR \ Bandgap Calibration Register
+ $80 constant BGCCR_BGD \ Setting the BGD bit to one will disable the bandgap voltage reference. This bit must be cleared before enabling CC-ADC or V-ADC, and must remain unset while either ADC is enabled.
+ $3F constant BGCCR_BGCC \ BG Calibration of PTAT Current Bits
+\ EEPROM
+&65 constant EEAR \ EEPROM Address Register Bytes
+&64 constant EEDR \ EEPROM Data Register
+&63 constant EECR \ EEPROM Control Register
+ $30 constant EECR_EEPM \ EEPROM Programming Mode Bits
+ $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
+ $04 constant EECR_EEMPE \ EEPROM Master Programming Enable
+ $02 constant EECR_EEPE \ EEPROM Programming Enable
+ $01 constant EECR_EERE \ EEPROM Read Enable
+
+\ Interrupts
+&2 constant BPINTAddr \ Battery Protection Interrupt
+&4 constant INT0Addr \ External Interrupt Request 0
+&6 constant INT1Addr \ External Interrupt Request 1
+&8 constant INT2Addr \ External Interrupt Request 2
+&10 constant INT3Addr \ External Interrupt Request 3
+&12 constant PCINT0Addr \ Pin Change Interrupt 0
+&14 constant PCINT1Addr \ Pin Change Interrupt 1
+&16 constant WDTAddr \ Watchdog Timeout Interrupt
+&18 constant WAKE_UPAddr \ Wakeup timer overflow
+&20 constant TIM1_COMPAddr \ Timer/Counter 1 Compare Match
+&22 constant TIM1_OVFAddr \ Timer/Counter 1 Overflow
+&24 constant TIM0_COMPAAddr \ Timer/Counter0 Compare A Match
+&26 constant TIM0_COMPBAddr \ Timer/Counter0 Compare B Match
+&28 constant TIM0_OVFAddr \ Timer/Counter0 Overflow
+&30 constant TWI_BUS_CDAddr \ Two-Wire Bus Connect/Disconnect
+&32 constant TWIAddr \ Two-Wire Serial Interface
+&34 constant VADCAddr \ Voltage ADC Conversion Complete
+&36 constant CCADC_CONVAddr \ Coulomb Counter ADC Conversion Complete
+&38 constant CCADC_REG_CURAddr \ Coloumb Counter ADC Regular Current
+&40 constant CCADC_ACCAddr \ Coloumb Counter ADC Accumulator
+&42 constant EE_READYAddr \ EEPROM Ready
+&44 constant SPM_READYAddr \ Store Program Memory Ready
diff --git a/amforth-6.5/avr8/devices/atmega406/device.asm b/amforth-6.5/avr8/devices/atmega406/device.asm
new file mode 100644
index 0000000..bce90e4
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega406/device.asm
@@ -0,0 +1,104 @@
+; Partname: ATmega406
+; generated automatically, do not edit
+
+.nolist
+ .include "m406def.inc"
+.list
+
+.equ ramstart = 256
+.equ CELLSIZE = 2
+.macro readflashcell
+ lsl zl
+ rol zh
+ lpm @0, Z+
+ lpm @1, Z+
+.endmacro
+.macro writeflashcell
+ lsl zl
+ rol zh
+.endmacro
+.set WANT_AD_CONVERTER = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_WAKEUP_TIMER = 0
+.set WANT_BATTERY_PROTECTION = 0
+.set WANT_FET = 0
+.set WANT_COULOMB_COUNTER = 0
+.set WANT_CELL_BALANCING = 0
+.set WANT_CPU = 0
+.set WANT_WATCHDOG = 0
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_PORTA = 0
+.set WANT_PORTB = 0
+.set WANT_PORTC = 0
+.set WANT_PORTD = 0
+.set WANT_BOOT_LOAD = 0
+.set WANT_TWI = 0
+.set WANT_BANDGAP = 0
+.set WANT_EEPROM = 0
+.equ intvecsize = 2 ; please verify; flash size: 40960 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.org 2
+ rcall isr ; Battery Protection Interrupt
+.org 4
+ rcall isr ; External Interrupt Request 0
+.org 6
+ rcall isr ; External Interrupt Request 1
+.org 8
+ rcall isr ; External Interrupt Request 2
+.org 10
+ rcall isr ; External Interrupt Request 3
+.org 12
+ rcall isr ; Pin Change Interrupt 0
+.org 14
+ rcall isr ; Pin Change Interrupt 1
+.org 16
+ rcall isr ; Watchdog Timeout Interrupt
+.org 18
+ rcall isr ; Wakeup timer overflow
+.org 20
+ rcall isr ; Timer/Counter 1 Compare Match
+.org 22
+ rcall isr ; Timer/Counter 1 Overflow
+.org 24
+ rcall isr ; Timer/Counter0 Compare A Match
+.org 26
+ rcall isr ; Timer/Counter0 Compare B Match
+.org 28
+ rcall isr ; Timer/Counter0 Overflow
+.org 30
+ rcall isr ; Two-Wire Bus Connect/Disconnect
+.org 32
+ rcall isr ; Two-Wire Serial Interface
+.org 34
+ rcall isr ; Voltage ADC Conversion Complete
+.org 36
+ rcall isr ; Coulomb Counter ADC Conversion Complete
+.org 38
+ rcall isr ; Coloumb Counter ADC Regular Current
+.org 40
+ rcall isr ; Coloumb Counter ADC Accumulator
+.org 42
+ rcall isr ; EEPROM Ready
+.org 44
+ rcall isr ; Store Program Memory Ready
+.equ INTVECTORS = 23
+.nooverlap
+
+; compatability layer (maybe empty)
+
+; controller data area, environment query mcu-info
+mcu_info:
+mcu_ramsize:
+ .dw 2048
+mcu_eepromsize:
+ .dw 512
+mcu_maxdp:
+ .dw 36864
+mcu_numints:
+ .dw 23
+mcu_name:
+ .dw 9
+ .db "ATmega406",0
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega406/device.inc b/amforth-6.5/avr8/devices/atmega406/device.inc
new file mode 100644
index 0000000..aa01e8d
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega406/device.inc
@@ -0,0 +1,1008 @@
+; Partname: ATmega406
+; generated automatically, no not edit
+
+.if WANT_AD_CONVERTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; The VADC multiplexer Selection Register
+VE_VADMUX:
+ .dw $ff06
+ .db "VADMUX"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_VADMUX
+XT_VADMUX:
+ .dw PFA_DOVARIABLE
+PFA_VADMUX:
+ .dw 124
+; ( -- addr ) System Constant
+; R( -- )
+; VADC Data Register Bytes
+VE_VADC:
+ .dw $ff04
+ .db "VADC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_VADC
+XT_VADC:
+ .dw PFA_DOVARIABLE
+PFA_VADC:
+ .dw 120
+; ( -- addr ) System Constant
+; R( -- )
+; The VADC Control and Status register
+VE_VADCSR:
+ .dw $ff06
+ .db "VADCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_VADCSR
+XT_VADCSR:
+ .dw PFA_DOVARIABLE
+PFA_VADCSR:
+ .dw 122
+
+.endif
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register
+VE_EICRA:
+ .dw $ff05
+ .db "EICRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRA
+XT_EICRA:
+ .dw PFA_DOVARIABLE
+PFA_EICRA:
+ .dw 105
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Mask Register
+VE_EIMSK:
+ .dw $ff05
+ .db "EIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIMSK
+XT_EIMSK:
+ .dw PFA_DOVARIABLE
+PFA_EIMSK:
+ .dw 61
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Flag Register
+VE_EIFR:
+ .dw $ff04
+ .db "EIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIFR
+XT_EIFR:
+ .dw PFA_DOVARIABLE
+PFA_EIFR:
+ .dw 60
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Interrupt Control Register
+VE_PCICR:
+ .dw $ff05
+ .db "PCICR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCICR
+XT_PCICR:
+ .dw PFA_DOVARIABLE
+PFA_PCICR:
+ .dw 104
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Interrupt Flag Register
+VE_PCIFR:
+ .dw $ff05
+ .db "PCIFR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCIFR
+XT_PCIFR:
+ .dw PFA_DOVARIABLE
+PFA_PCIFR:
+ .dw 59
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Enable Mask Register 1
+VE_PCMSK1:
+ .dw $ff06
+ .db "PCMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK1
+XT_PCMSK1:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK1:
+ .dw 108
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Enable Mask Register 0
+VE_PCMSK0:
+ .dw $ff06
+ .db "PCMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK0
+XT_PCMSK0:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK0:
+ .dw 107
+
+.endif
+.if WANT_TIMER_COUNTER_1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw 129
+; ( -- addr ) System Constant
+; R( -- )
+; Timer Counter 1 Bytes
+VE_TCNT1:
+ .dw $ff05
+ .db "TCNT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1
+XT_TCNT1:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1:
+ .dw 132
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare Register 1A Low byte
+VE_OCR1AL:
+ .dw $ff06
+ .db "OCR1AL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1AL
+XT_OCR1AL:
+ .dw PFA_DOVARIABLE
+PFA_OCR1AL:
+ .dw 136
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare Register 1A High byte
+VE_OCR1AH:
+ .dw $ff06
+ .db "OCR1AH"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1AH
+XT_OCR1AH:
+ .dw PFA_DOVARIABLE
+PFA_OCR1AH:
+ .dw 137
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Mask Register
+VE_TIMSK1:
+ .dw $ff06
+ .db "TIMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK1
+XT_TIMSK1:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK1:
+ .dw 111
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Flag register
+VE_TIFR1:
+ .dw $ff05
+ .db "TIFR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR1
+XT_TIFR1:
+ .dw PFA_DOVARIABLE
+PFA_TIFR1:
+ .dw 54
+; ( -- addr ) System Constant
+; R( -- )
+; General Timer/Counter Control Register
+VE_GTCCR:
+ .dw $ff05
+ .db "GTCCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GTCCR
+XT_GTCCR:
+ .dw PFA_DOVARIABLE
+PFA_GTCCR:
+ .dw 67
+
+.endif
+.if WANT_WAKEUP_TIMER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Wake-up Timer Control Register
+VE_WUTCSR:
+ .dw $ff06
+ .db "WUTCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WUTCSR
+XT_WUTCSR:
+ .dw PFA_DOVARIABLE
+PFA_WUTCSR:
+ .dw 98
+
+.endif
+.if WANT_BATTERY_PROTECTION == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Battery Protection Parameter Lock Register
+VE_BPPLR:
+ .dw $ff05
+ .db "BPPLR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_BPPLR
+XT_BPPLR:
+ .dw PFA_DOVARIABLE
+PFA_BPPLR:
+ .dw 248
+; ( -- addr ) System Constant
+; R( -- )
+; Battery Protection Control Register
+VE_BPCR:
+ .dw $ff04
+ .db "BPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_BPCR
+XT_BPCR:
+ .dw PFA_DOVARIABLE
+PFA_BPCR:
+ .dw 247
+; ( -- addr ) System Constant
+; R( -- )
+; Current Battery Protection Timing Register
+VE_CBPTR:
+ .dw $ff05
+ .db "CBPTR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CBPTR
+XT_CBPTR:
+ .dw PFA_DOVARIABLE
+PFA_CBPTR:
+ .dw 246
+; ( -- addr ) System Constant
+; R( -- )
+; Battery Protection OverCurrent Detection Level Register
+VE_BPOCD:
+ .dw $ff05
+ .db "BPOCD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_BPOCD
+XT_BPOCD:
+ .dw PFA_DOVARIABLE
+PFA_BPOCD:
+ .dw 245
+; ( -- addr ) System Constant
+; R( -- )
+; Battery Protection Short-Circuit Detection Level Register
+VE_BPSCD:
+ .dw $ff05
+ .db "BPSCD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_BPSCD
+XT_BPSCD:
+ .dw PFA_DOVARIABLE
+PFA_BPSCD:
+ .dw 244
+; ( -- addr ) System Constant
+; R( -- )
+; Battery Protection Deep Under Voltage Register
+VE_BPDUV:
+ .dw $ff05
+ .db "BPDUV",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_BPDUV
+XT_BPDUV:
+ .dw PFA_DOVARIABLE
+PFA_BPDUV:
+ .dw 243
+; ( -- addr ) System Constant
+; R( -- )
+; Battery Protection Interrupt Register
+VE_BPIR:
+ .dw $ff04
+ .db "BPIR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_BPIR
+XT_BPIR:
+ .dw PFA_DOVARIABLE
+PFA_BPIR:
+ .dw 242
+
+.endif
+.if WANT_FET == 1
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_FCSR:
+ .dw $ff04
+ .db "FCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_FCSR
+XT_FCSR:
+ .dw PFA_DOVARIABLE
+PFA_FCSR:
+ .dw 240
+
+.endif
+.if WANT_COULOMB_COUNTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; CC-ADC Control and Status Register A
+VE_CADCSRA:
+ .dw $ff07
+ .db "CADCSRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CADCSRA
+XT_CADCSRA:
+ .dw PFA_DOVARIABLE
+PFA_CADCSRA:
+ .dw 228
+; ( -- addr ) System Constant
+; R( -- )
+; CC-ADC Control and Status Register B
+VE_CADCSRB:
+ .dw $ff07
+ .db "CADCSRB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CADCSRB
+XT_CADCSRB:
+ .dw PFA_DOVARIABLE
+PFA_CADCSRB:
+ .dw 229
+; ( -- addr ) System Constant
+; R( -- )
+; CC-ADC Instantaneous Current
+VE_CADIC:
+ .dw $ff05
+ .db "CADIC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CADIC
+XT_CADIC:
+ .dw PFA_DOVARIABLE
+PFA_CADIC:
+ .dw 232
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Accumulate Current
+VE_CADAC3:
+ .dw $ff06
+ .db "CADAC3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CADAC3
+XT_CADAC3:
+ .dw PFA_DOVARIABLE
+PFA_CADAC3:
+ .dw 227
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Accumulate Current
+VE_CADAC2:
+ .dw $ff06
+ .db "CADAC2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CADAC2
+XT_CADAC2:
+ .dw PFA_DOVARIABLE
+PFA_CADAC2:
+ .dw 226
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Accumulate Current
+VE_CADAC1:
+ .dw $ff06
+ .db "CADAC1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CADAC1
+XT_CADAC1:
+ .dw PFA_DOVARIABLE
+PFA_CADAC1:
+ .dw 225
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Accumulate Current
+VE_CADAC0:
+ .dw $ff06
+ .db "CADAC0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CADAC0
+XT_CADAC0:
+ .dw PFA_DOVARIABLE
+PFA_CADAC0:
+ .dw 224
+; ( -- addr ) System Constant
+; R( -- )
+; CC-ADC Regular Charge Current
+VE_CADRCC:
+ .dw $ff06
+ .db "CADRCC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CADRCC
+XT_CADRCC:
+ .dw PFA_DOVARIABLE
+PFA_CADRCC:
+ .dw 230
+; ( -- addr ) System Constant
+; R( -- )
+; CC-ADC Regular Discharge Current
+VE_CADRDC:
+ .dw $ff06
+ .db "CADRDC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CADRDC
+XT_CADRDC:
+ .dw PFA_DOVARIABLE
+PFA_CADRDC:
+ .dw 231
+
+.endif
+.if WANT_CELL_BALANCING == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Cell Balancing Control Register
+VE_CBCR:
+ .dw $ff04
+ .db "CBCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CBCR
+XT_CBCR:
+ .dw PFA_DOVARIABLE
+PFA_CBCR:
+ .dw 241
+
+.endif
+.if WANT_CPU == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw 95
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer
+VE_SP:
+ .dw $ff02
+ .db "SP"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SP
+XT_SP:
+ .dw PFA_DOVARIABLE
+PFA_SP:
+ .dw 93
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw 85
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Status Register
+VE_MCUSR:
+ .dw $ff05
+ .db "MCUSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUSR
+XT_MCUSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUSR:
+ .dw 84
+; ( -- addr ) System Constant
+; R( -- )
+; Fast Oscillator Calibration Value
+VE_FOSCCAL:
+ .dw $ff07
+ .db "FOSCCAL",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_FOSCCAL
+XT_FOSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_FOSCCAL:
+ .dw 102
+; ( -- addr ) System Constant
+; R( -- )
+; Sleep Mode Control Register
+VE_SMCR:
+ .dw $ff04
+ .db "SMCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SMCR
+XT_SMCR:
+ .dw PFA_DOVARIABLE
+PFA_SMCR:
+ .dw 83
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 2
+VE_GPIOR2:
+ .dw $ff06
+ .db "GPIOR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR2
+XT_GPIOR2:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR2:
+ .dw 75
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 1
+VE_GPIOR1:
+ .dw $ff06
+ .db "GPIOR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR1
+XT_GPIOR1:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR1:
+ .dw 74
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 0
+VE_GPIOR0:
+ .dw $ff06
+ .db "GPIOR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR0
+XT_GPIOR0:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR0:
+ .dw 62
+; ( -- addr ) System Constant
+; R( -- )
+; Clock Control and Status Register
+VE_CCSR:
+ .dw $ff04
+ .db "CCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CCSR
+XT_CCSR:
+ .dw PFA_DOVARIABLE
+PFA_CCSR:
+ .dw 192
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register
+VE_DIDR0:
+ .dw $ff05
+ .db "DIDR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR0
+XT_DIDR0:
+ .dw PFA_DOVARIABLE
+PFA_DIDR0:
+ .dw 126
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register 0
+VE_PRR0:
+ .dw $ff04
+ .db "PRR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR0
+XT_PRR0:
+ .dw PFA_DOVARIABLE
+PFA_PRR0:
+ .dw 100
+
+.endif
+.if WANT_WATCHDOG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCSR:
+ .dw $ff06
+ .db "WDTCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCSR
+XT_WDTCSR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCSR:
+ .dw 96
+
+.endif
+.if WANT_TIMER_COUNTER_0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Control Register
+VE_TCCR0A:
+ .dw $ff06
+ .db "TCCR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0A
+XT_TCCR0A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0A:
+ .dw 68
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Control Register
+VE_TCCR0B:
+ .dw $ff06
+ .db "TCCR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0B
+XT_TCCR0B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0B:
+ .dw 69
+; ( -- addr ) System Constant
+; R( -- )
+; Timer Counter 0
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw 70
+; ( -- addr ) System Constant
+; R( -- )
+; Output compare Register A
+VE_OCR0A:
+ .dw $ff05
+ .db "OCR0A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0A
+XT_OCR0A:
+ .dw PFA_DOVARIABLE
+PFA_OCR0A:
+ .dw 71
+; ( -- addr ) System Constant
+; R( -- )
+; Output compare Register B
+VE_OCR0B:
+ .dw $ff05
+ .db "OCR0B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0B
+XT_OCR0B:
+ .dw PFA_DOVARIABLE
+PFA_OCR0B:
+ .dw 72
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Mask Register
+VE_TIMSK0:
+ .dw $ff06
+ .db "TIMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK0
+XT_TIMSK0:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK0:
+ .dw 110
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Flag register
+VE_TIFR0:
+ .dw $ff05
+ .db "TIFR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR0
+XT_TIFR0:
+ .dw PFA_DOVARIABLE
+PFA_TIFR0:
+ .dw 53
+
+.endif
+.if WANT_PORTA == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Register
+VE_PORTA:
+ .dw $ff05
+ .db "PORTA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTA
+XT_PORTA:
+ .dw PFA_DOVARIABLE
+PFA_PORTA:
+ .dw 34
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Direction Register
+VE_DDRA:
+ .dw $ff04
+ .db "DDRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRA
+XT_DDRA:
+ .dw PFA_DOVARIABLE
+PFA_DDRA:
+ .dw 33
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Input Pins
+VE_PINA:
+ .dw $ff04
+ .db "PINA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINA
+XT_PINA:
+ .dw PFA_DOVARIABLE
+PFA_PINA:
+ .dw 32
+
+.endif
+.if WANT_PORTB == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw 37
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw 36
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw 35
+
+.endif
+.if WANT_PORTC == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Register
+VE_PORTC:
+ .dw $ff05
+ .db "PORTC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTC
+XT_PORTC:
+ .dw PFA_DOVARIABLE
+PFA_PORTC:
+ .dw 40
+
+.endif
+.if WANT_PORTD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port D
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw 43
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port D
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw 42
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port D
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw 41
+
+.endif
+.if WANT_BOOT_LOAD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control Register
+VE_SPMCSR:
+ .dw $ff06
+ .db "SPMCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCSR
+XT_SPMCSR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCSR:
+ .dw 87
+
+.endif
+.if WANT_TWI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Bus Control and Status Register
+VE_TWBCSR:
+ .dw $ff06
+ .db "TWBCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWBCSR
+XT_TWBCSR:
+ .dw PFA_DOVARIABLE
+PFA_TWBCSR:
+ .dw 190
+; ( -- addr ) System Constant
+; R( -- )
+; TWI (Slave) Address Mask Register
+VE_TWAMR:
+ .dw $ff05
+ .db "TWAMR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWAMR
+XT_TWAMR:
+ .dw PFA_DOVARIABLE
+PFA_TWAMR:
+ .dw 189
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Bit Rate register
+VE_TWBR:
+ .dw $ff04
+ .db "TWBR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWBR
+XT_TWBR:
+ .dw PFA_DOVARIABLE
+PFA_TWBR:
+ .dw 184
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Control Register
+VE_TWCR:
+ .dw $ff04
+ .db "TWCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWCR
+XT_TWCR:
+ .dw PFA_DOVARIABLE
+PFA_TWCR:
+ .dw 188
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Status Register
+VE_TWSR:
+ .dw $ff04
+ .db "TWSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWSR
+XT_TWSR:
+ .dw PFA_DOVARIABLE
+PFA_TWSR:
+ .dw 185
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Data register
+VE_TWDR:
+ .dw $ff04
+ .db "TWDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWDR
+XT_TWDR:
+ .dw PFA_DOVARIABLE
+PFA_TWDR:
+ .dw 187
+; ( -- addr ) System Constant
+; R( -- )
+; TWI (Slave) Address register
+VE_TWAR:
+ .dw $ff04
+ .db "TWAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWAR
+XT_TWAR:
+ .dw PFA_DOVARIABLE
+PFA_TWAR:
+ .dw 186
+
+.endif
+.if WANT_BANDGAP == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Bandgap Calibration of Resistor Ladder
+VE_BGCRR:
+ .dw $ff05
+ .db "BGCRR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_BGCRR
+XT_BGCRR:
+ .dw PFA_DOVARIABLE
+PFA_BGCRR:
+ .dw 209
+; ( -- addr ) System Constant
+; R( -- )
+; Bandgap Calibration Register
+VE_BGCCR:
+ .dw $ff05
+ .db "BGCCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_BGCCR
+XT_BGCCR:
+ .dw PFA_DOVARIABLE
+PFA_BGCCR:
+ .dw 208
+
+.endif
+.if WANT_EEPROM == 1
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Address Register Bytes
+VE_EEAR:
+ .dw $ff04
+ .db "EEAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEAR
+XT_EEAR:
+ .dw PFA_DOVARIABLE
+PFA_EEAR:
+ .dw 65
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw 64
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw 63
+
+.endif
diff --git a/amforth-6.5/avr8/devices/atmega406/device.py b/amforth-6.5/avr8/devices/atmega406/device.py
new file mode 100644
index 0000000..46fb5f3
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega406/device.py
@@ -0,0 +1,290 @@
+# Generated Automatically
+
+# Partname ATmega406
+
+MCUREGS = {
+# Interrupt Vectors
+ 'BPINTAddr' : '#2', # Battery Protection Interrupt
+ 'INT0Addr' : '#4', # External Interrupt Request 0
+ 'INT1Addr' : '#6', # External Interrupt Request 1
+ 'INT2Addr' : '#8', # External Interrupt Request 2
+ 'INT3Addr' : '#10', # External Interrupt Request 3
+ 'PCINT0Addr' : '#12', # Pin Change Interrupt 0
+ 'PCINT1Addr' : '#14', # Pin Change Interrupt 1
+ 'WDTAddr' : '#16', # Watchdog Timeout Interrupt
+ 'WAKE_UPAddr' : '#18', # Wakeup timer overflow
+ 'TIM1_COMPAddr' : '#20', # Timer/Counter 1 Compare Match
+ 'TIM1_OVFAddr' : '#22', # Timer/Counter 1 Overflow
+ 'TIM0_COMPAAddr' : '#24', # Timer/Counter0 Compare A Match
+ 'TIM0_COMPBAddr' : '#26', # Timer/Counter0 Compare B Match
+ 'TIM0_OVFAddr' : '#28', # Timer/Counter0 Overflow
+ 'TWI_BUS_CDAddr' : '#30', # Two-Wire Bus Connect/Disconnect
+ 'TWIAddr' : '#32', # Two-Wire Serial Interface
+ 'VADCAddr' : '#34', # Voltage ADC Conversion Complete
+ 'CCADC_CONVAddr' : '#36', # Coulomb Counter ADC Conversion Complete
+ 'CCADC_REG_CURAddr' : '#38', # Coloumb Counter ADC Regular Current
+ 'CCADC_ACCAddr' : '#40', # Coloumb Counter ADC Accumulator
+ 'EE_READYAddr' : '#42', # EEPROM Ready
+ 'SPM_READYAddr' : '#44', # Store Program Memory Ready
+
+# Module AD_CONVERTER
+ 'VADMUX' : '$7c', # The VADC multiplexer Selection
+ 'VADMUX_VADMUX': '$f', # Analog Channel and Gain Select
+ 'VADC' : '$78', # VADC Data Register Bytes
+ 'VADCSR' : '$7a', # The VADC Control and Status re
+ 'VADCSR_VADEN': '$8', # VADC Enable
+ 'VADCSR_VADSC': '$4', # VADC Satrt Conversion
+ 'VADCSR_VADCCIF': '$2', # VADC Conversion Complete Inter
+ 'VADCSR_VADCCIE': '$1', # VADC Conversion Complete Inter
+
+# Module EXTERNAL_INTERRUPT
+ 'EICRA' : '$69', # External Interrupt Control Reg
+ 'EICRA_ISC3': '$c0', # External Interrupt Sense Contr
+ 'EICRA_ISC2': '$30', # External Interrupt Sense Contr
+ 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
+ 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
+ 'EIMSK' : '$3d', # External Interrupt Mask Regist
+ 'EIMSK_INT': '$f', # External Interrupt Request 1 E
+ 'EIFR' : '$3c', # External Interrupt Flag Regist
+ 'EIFR_INTF': '$f', # External Interrupt Flags
+ 'PCICR' : '$68', # Pin Change Interrupt Control R
+ 'PCICR_PCIE': '$3', # Pin Change Interrupt Enables
+ 'PCIFR' : '$3b', # Pin Change Interrupt Flag Regi
+ 'PCIFR_PCIF': '$3', # Pin Change Interrupt Flags
+ 'PCMSK1' : '$6c', # Pin Change Enable Mask Registe
+ 'PCMSK0' : '$6b', # Pin Change Enable Mask Registe
+
+# Module TIMER_COUNTER_1
+ 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
+ 'TCCR1B_CTC1': '$8', # Clear Timer/Counter on Compare
+ 'TCCR1B_CS1': '$7', # Clock Select1 bits
+ 'TCNT1' : '$84', # Timer Counter 1 Bytes
+ 'OCR1AL' : '$88', # Output Compare Register 1A Low
+ 'OCR1AH' : '$89', # Output Compare Register 1A Hig
+ 'TIMSK1' : '$6f', # Timer/Counter Interrupt Mask R
+ 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
+ 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
+ 'TIFR1' : '$36', # Timer/Counter Interrupt Flag r
+ 'TIFR1_OCF1A': '$2', # Timer/Counter1 Output Compare
+ 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSRSYNC': '$1', # Prescaler Reset
+
+# Module WAKEUP_TIMER
+ 'WUTCSR' : '$62', # Wake-up Timer Control Register
+ 'WUTCSR_WUTIF': '$80', # Wake-up Timer Interrupt Flag
+ 'WUTCSR_WUTIE': '$40', # Wake-up Timer Interrupt Enable
+ 'WUTCSR_WUTCF': '$20', # Wake-up timer Calibration Flag
+ 'WUTCSR_WUTR': '$10', # Wake-up Timer Reset
+ 'WUTCSR_WUTE': '$8', # Wake-up Timer Enable
+ 'WUTCSR_WUTP': '$7', # Wake-up Timer Prescaler Bits
+
+# Module BATTERY_PROTECTION
+ 'BPPLR' : '$f8', # Battery Protection Parameter L
+ 'BPPLR_BPPLE': '$2', # Battery Protection Parameter L
+ 'BPPLR_BPPL': '$1', # Battery Protection Parameter L
+ 'BPCR' : '$f7', # Battery Protection Control Reg
+ 'BPCR_DUVD': '$8', #
+ 'BPCR_SCD': '$4', #
+ 'BPCR_DCD': '$2', #
+ 'BPCR_CCD': '$1', #
+ 'CBPTR' : '$f6', # Current Battery Protection Tim
+ 'CBPTR_SCPT': '$f0', #
+ 'CBPTR_OCPT': '$f', #
+ 'BPOCD' : '$f5', # Battery Protection OverCurrent
+ 'BPOCD_DCDL': '$f0', #
+ 'BPOCD_CCDL': '$f', #
+ 'BPSCD' : '$f4', # Battery Protection Short-Circu
+ 'BPSCD_SCDL': '$f', #
+ 'BPDUV' : '$f3', # Battery Protection Deep Under
+ 'BPDUV_DUVT': '$30', #
+ 'BPDUV_DUDL': '$f', #
+ 'BPIR' : '$f2', # Battery Protection Interrupt R
+ 'BPIR_DUVIF': '$80', # Deep Under-voltage Early Warni
+ 'BPIR_COCIF': '$40', # Charge Over-current Protection
+ 'BPIR_DOCIF': '$20', #
+ 'BPIR_SCIF': '$10', #
+ 'BPIR_DUVIE': '$8', # Deep Under-voltage Early Warni
+ 'BPIR_COCIE': '$4', #
+ 'BPIR_DOCIE': '$2', #
+ 'BPIR_SCIE': '$1', #
+
+# Module FET
+ 'FCSR' : '$f0', #
+ 'FCSR_PWMOC': '$20', # Pulse Width Modulation of OC o
+ 'FCSR_PWMOPC': '$10', # Pulse Width Modulation Modulat
+ 'FCSR_CPS': '$8', # Current Protection Status
+ 'FCSR_DFE': '$4', # Discharge FET Enable
+ 'FCSR_CFE': '$2', # Charge FET Enable
+ 'FCSR_PFD': '$1', # Precharge FET disable
+
+# Module COULOMB_COUNTER
+ 'CADCSRA' : '$e4', # CC-ADC Control and Status Regi
+ 'CADCSRA_CADEN': '$80', # When the CADEN bit is cleared
+ 'CADCSRA_CADUB': '$20', # CC_ADC Update Busy
+ 'CADCSRA_CADAS': '$18', # CC_ADC Accumulate Current Sele
+ 'CADCSRA_CADSI': '$6', # The CADSI bits determine the c
+ 'CADCSRA_CADSE': '$1', # When the CADSE bit is written
+ 'CADCSRB' : '$e5', # CC-ADC Control and Status Regi
+ 'CADCSRB_CADACIE': '$40', #
+ 'CADCSRB_CADRCIE': '$20', # Regular Current Interrupt Enab
+ 'CADCSRB_CADICIE': '$10', # CAD Instantenous Current Inter
+ 'CADCSRB_CADACIF': '$4', # CC-ADC Accumulate Current Inte
+ 'CADCSRB_CADRCIF': '$2', # CC-ADC Accumulate Current Inte
+ 'CADCSRB_CADICIF': '$1', # CC-ADC Instantaneous Current I
+ 'CADIC' : '$e8', # CC-ADC Instantaneous Current
+ 'CADAC3' : '$e3', # ADC Accumulate Current
+ 'CADAC2' : '$e2', # ADC Accumulate Current
+ 'CADAC1' : '$e1', # ADC Accumulate Current
+ 'CADAC0' : '$e0', # ADC Accumulate Current
+ 'CADRCC' : '$e6', # CC-ADC Regular Charge Current
+ 'CADRDC' : '$e7', # CC-ADC Regular Discharge Curre
+
+# Module CELL_BALANCING
+ 'CBCR' : '$f1', # Cell Balancing Control Registe
+ 'CBCR_CBE': '$f', # Cell Balancing Enables
+
+# Module CPU
+ 'SREG' : '$5f', # Status Register
+ 'SREG_I': '$80', # Global Interrupt Enable
+ 'SREG_T': '$40', # Bit Copy Storage
+ 'SREG_H': '$20', # Half Carry Flag
+ 'SREG_S': '$10', # Sign Bit
+ 'SREG_V': '$8', # Two's Complement Overflow Flag
+ 'SREG_N': '$4', # Negative Flag
+ 'SREG_Z': '$2', # Zero Flag
+ 'SREG_C': '$1', # Carry Flag
+ 'SP' : '$5d', # Stack Pointer
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_JTD': '$80', # JTAG Disable
+ 'MCUCR_PUD': '$10', # Pull-up disable
+ 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
+ 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+ 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
+ 'MCUSR_BODRF': '$4', # Brown-out Reset Flag
+ 'MCUSR_EXTRF': '$2', # External Reset Flag
+ 'MCUSR_PORF': '$1', # Power-on reset flag
+ 'FOSCCAL' : '$66', # Fast Oscillator Calibration Va
+ 'SMCR' : '$53', # Sleep Mode Control Register
+ 'SMCR_SM': '$e', # Sleep Mode Select bits
+ 'SMCR_SE': '$1', # Sleep Enable
+ 'GPIOR2' : '$4b', # General Purpose IO Register 2
+ 'GPIOR1' : '$4a', # General Purpose IO Register 1
+ 'GPIOR0' : '$3e', # General Purpose IO Register 0
+ 'CCSR' : '$c0', # Clock Control and Status Regis
+ 'CCSR_XOE': '$2', # 32 kHz Crystal Oscillator Enab
+ 'CCSR_ACS': '$1', # Asynchronous Clock Select
+ 'DIDR0' : '$7e', # Digital Input Disable Register
+ 'PRR0' : '$64', # Power Reduction Register 0
+ 'PRR0_PRTWI': '$8', # Power Reduction TWI
+ 'PRR0_PRTIM1': '$4', # Power Reduction Timer/Counter1
+ 'PRR0_PRTIM0': '$2', # Power Reduction Timer/Counter0
+ 'PRR0_PRVADC': '$1', # Power Reduction V-ADC
+
+# Module WATCHDOG
+ 'WDTCSR' : '$60', # Watchdog Timer Control Registe
+ 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
+ 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
+ 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
+ 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
+ 'WDTCSR_WDE': '$8', # Watch Dog Enable
+
+# Module TIMER_COUNTER_0
+ 'TCCR0A' : '$44', # Timer/Counter0 Control Registe
+ 'TCCR0A_COM0A': '$c0', # Force Output Compare
+ 'TCCR0A_COM0B': '$30', #
+ 'TCCR0A_WGM0': '$3', # Clock Select0 bits
+ 'TCCR0B' : '$45', # Timer/Counter0 Control Registe
+ 'TCCR0B_FOC0A': '$80', # Force Output Compare
+ 'TCCR0B_FOC0B': '$40', # Waveform Generation Mode
+ 'TCCR0B_WGM02': '$8', #
+ 'TCCR0B_CS0': '$7', # Clock Select0 bits
+ 'TCNT0' : '$46', # Timer Counter 0
+ 'OCR0A' : '$47', # Output compare Register A
+ 'OCR0A_OCR0A': '$ff', #
+ 'OCR0B' : '$48', # Output compare Register B
+ 'OCR0B_OCR0B': '$ff', #
+ 'TIMSK0' : '$6e', # Timer/Counter Interrupt Mask R
+ 'TIMSK0_OCIE0B': '$4', # Output Compare Interrupt Enabl
+ 'TIMSK0_OCIE0A': '$2', # Output Compare Interrupt Enabl
+ 'TIMSK0_TOIE0': '$1', # Overflow Interrupt Enable
+ 'TIFR0' : '$35', # Timer/Counter Interrupt Flag r
+ 'TIFR0_OCF0B': '$4', # Output Compare Flag
+ 'TIFR0_OCF0A': '$2', # Output Compare Flag
+ 'TIFR0_TOV0': '$1', # Overflow Flag
+
+# Module PORTA
+ 'PORTA' : '$22', # Port A Data Register
+ 'DDRA' : '$21', # Port A Data Direction Register
+ 'PINA' : '$20', # Port A Input Pins
+
+# Module PORTB
+ 'PORTB' : '$25', # Port B Data Register
+ 'DDRB' : '$24', # Port B Data Direction Register
+ 'PINB' : '$23', # Port B Input Pins
+
+# Module PORTC
+ 'PORTC' : '$28', # Port C Data Register
+
+# Module PORTD
+ 'PORTD' : '$2b', # Data Register, Port D
+ 'DDRD' : '$2a', # Data Direction Register, Port
+ 'PIND' : '$29', # Input Pins, Port D
+
+# Module BOOT_LOAD
+ 'SPMCSR' : '$57', # Store Program Memory Control R
+ 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
+ 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
+ 'SPMCSR_SIGRD': '$20', # Signature Row Read
+ 'SPMCSR_RWWSRE': '$10', # Read While Write section read
+ 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
+ 'SPMCSR_PGWRT': '$4', # Page Write
+ 'SPMCSR_PGERS': '$2', # Page Erase
+ 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
+
+# Module TWI
+ 'TWBCSR' : '$be', # TWI Bus Control and Status Reg
+ 'TWBCSR_TWBCIF': '$80', # TWI Bus Connect/Disconnect Int
+ 'TWBCSR_TWBCIE': '$40', # TWI Bus Connect/Disconnect Int
+ 'TWBCSR_TWBDT': '$6', # TWI Bus Disconnect Time-out Pe
+ 'TWBCSR_TWBCIP': '$1', # TWI Bus Connect/Disconnect Int
+ 'TWAMR' : '$bd', # TWI (Slave) Address Mask Regis
+ 'TWAMR_TWAM': '$fe', #
+ 'TWBR' : '$b8', # TWI Bit Rate register
+ 'TWCR' : '$bc', # TWI Control Register
+ 'TWCR_TWINT': '$80', # TWI Interrupt Flag
+ 'TWCR_TWEA': '$40', # TWI Enable Acknowledge Bit
+ 'TWCR_TWSTA': '$20', # TWI Start Condition Bit
+ 'TWCR_TWSTO': '$10', # TWI Stop Condition Bit
+ 'TWCR_TWWC': '$8', # TWI Write Collition Flag
+ 'TWCR_TWEN': '$4', # TWI Enable Bit
+ 'TWCR_TWIE': '$1', # TWI Interrupt Enable
+ 'TWSR' : '$b9', # TWI Status Register
+ 'TWSR_TWS': '$f8', # TWI Status
+ 'TWSR_TWPS': '$3', # TWI Prescaler
+ 'TWDR' : '$bb', # TWI Data register
+ 'TWAR' : '$ba', # TWI (Slave) Address register
+ 'TWAR_TWA': '$fe', # TWI (Slave) Address register B
+ 'TWAR_TWGCE': '$1', # TWI General Call Recognition E
+
+# Module BANDGAP
+ 'BGCRR' : '$d1', # Bandgap Calibration of Resisto
+ 'BGCCR' : '$d0', # Bandgap Calibration Register
+ 'BGCCR_BGD': '$80', # Setting the BGD bit to one wil
+ 'BGCCR_BGCC': '$3f', # BG Calibration of PTAT Current
+
+# Module EEPROM
+ 'EEAR' : '$41', # EEPROM Address Register Bytes
+ 'EEDR' : '$40', # EEPROM Data Register
+ 'EECR' : '$3f', # EEPROM Control Register
+ 'EECR_EEPM': '$30', # EEPROM Programming Mode Bits
+ 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
+ 'EECR_EEMPE': '$4', # EEPROM Master Programming Enab
+ 'EECR_EEPE': '$2', # EEPROM Programming Enable
+ 'EECR_EERE': '$1', # EEPROM Read Enable
+
+ '__amforth_dummy':'0'
+}
diff --git a/amforth-6.5/avr8/devices/atmega406/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega406/words/no-jtag.asm
new file mode 100644
index 0000000..352a4bb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega406/words/no-jtag.asm
@@ -0,0 +1,14 @@
+; ( -- )
+; ( -- )
+; MCU
+; disable jtag at runtime
+VE_NOJTAG:
+ .dw $FF05
+ .db "-jtag",0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOJTAG
+XT_NOJTAG:
+ .dw PFA_NOJTAG
+PFA_NOJTAG:
+
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega406/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega406/words/no-wdt.asm
new file mode 100644
index 0000000..ff6ddd1
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega406/words/no-wdt.asm
@@ -0,0 +1,34 @@
+; ( -- )
+; MCU
+; disable watch dog timer at runtime
+VE_NOWDT:
+ .dw $ff04
+ .db "-wdt"
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOWDT
+XT_NOWDT:
+ .dw PFA_NOWDT
+PFA_NOWDT:
+
+ in temp1,SREG
+ push temp1
+ ; Turn always off global interrupt.
+ cli
+ ; Reset Watchdog Timer
+ wdr
+ ; Clear WDRF in MCUSR
+ in temp1, MCUSR
+ andi temp1, (0xff & (0<<WDRF))
+ out MCUSR, temp1
+ ; Write logical one to WDCE and WDE
+ ; Keep old prescaler setting to prevent unintentional time-out
+ in_ temp1, WDTCSR
+ ori temp1, (1<<WDCE) | (1<<WDE)
+ out_ WDTCSR, temp1
+ ; Turn off WDT
+ ldi temp1, (0<<WDE)
+ out_ WDTCSR, temp1
+ ; restore status register
+ pop temp1
+ out SREG,temp1
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega406/words/sleep.asm b/amforth-6.5/avr8/devices/atmega406/words/sleep.asm
new file mode 100644
index 0000000..256249c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega406/words/sleep.asm
@@ -0,0 +1,19 @@
+; ( mode -- )
+; MCU
+; put the controller into the specified sleep mode
+VE_SLEEP:
+ .dw $ff05
+ .db "sleep", 0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_SLEEP
+XT_SLEEP:
+ .dw PFA_SLEEP
+PFA_SLEEP:
+ andi tosl, 7 ; leave only legal mode bits
+ lsl tosl ; move to correct location (bits 3-1)
+ ori tosl, 1 ; set the SE bit
+ out_ SMCR, tosl ; set the sleep config
+ sleep ; nighty-night
+ out_ SMCR, zerol ; 0 protects against accidental sleeps
+ loadtos ; pop argument from stack
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega64/atmega64.frt b/amforth-6.5/avr8/devices/atmega64/atmega64.frt
new file mode 100644
index 0000000..1cc51f1
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega64/atmega64.frt
@@ -0,0 +1,331 @@
+\ Partname: ATmega64
+\ generated automatically
+
+\ ANALOG_COMPARATOR
+&64 constant SFIOR \ Special Function IO Register
+ $08 constant SFIOR_ACME \ Analog Comparator Multiplexer Enable
+&40 constant ACSR \ Analog Comparator Control And Status Register
+ $80 constant ACSR_ACD \ Analog Comparator Disable
+ $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
+ $20 constant ACSR_ACO \ Analog Compare Output
+ $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
+ $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
+ $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
+ $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
+\ AD_CONVERTER
+&39 constant ADMUX \ The ADC multiplexer Selection Register
+ $C0 constant ADMUX_REFS \ Reference Selection Bits
+ $20 constant ADMUX_ADLAR \ Left Adjust Result
+ $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
+&36 constant ADC \ ADC Data Register Bytes
+&38 constant ADCSRA \ The ADC Control and Status register A
+ $80 constant ADCSRA_ADEN \ ADC Enable
+ $40 constant ADCSRA_ADSC \ ADC Start Conversion
+ $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
+ $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
+ $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
+ $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
+&142 constant ADCSRB \ The ADC Control and Status register B
+ $07 constant ADCSRB_ADTS \ ADC Auto Trigger Source bits
+\ SPI
+&47 constant SPDR \ SPI Data Register
+&46 constant SPSR \ SPI Status Register
+ $80 constant SPSR_SPIF \ SPI Interrupt Flag
+ $40 constant SPSR_WCOL \ Write Collision Flag
+ $01 constant SPSR_SPI2X \ Double SPI Speed Bit
+&45 constant SPCR \ SPI Control Register
+ $80 constant SPCR_SPIE \ SPI Interrupt Enable
+ $40 constant SPCR_SPE \ SPI Enable
+ $20 constant SPCR_DORD \ Data Order
+ $10 constant SPCR_MSTR \ Master/Slave Select
+ $08 constant SPCR_CPOL \ Clock polarity
+ $04 constant SPCR_CPHA \ Clock Phase
+ $03 constant SPCR_SPR \ SPI Clock Rate Selects
+\ TWI
+&112 constant TWBR \ TWI Bit Rate register
+&116 constant TWCR \ TWI Control Register
+ $80 constant TWCR_TWINT \ TWI Interrupt Flag
+ $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
+ $20 constant TWCR_TWSTA \ TWI Start Condition Bit
+ $10 constant TWCR_TWSTO \ TWI Stop Condition Bit
+ $08 constant TWCR_TWWC \ TWI Write Collition Flag
+ $04 constant TWCR_TWEN \ TWI Enable Bit
+ $01 constant TWCR_TWIE \ TWI Interrupt Enable
+&113 constant TWSR \ TWI Status Register
+ $F8 constant TWSR_TWS \ TWI Status
+ $03 constant TWSR_TWPS \ TWI Prescaler
+&115 constant TWDR \ TWI Data register
+&114 constant TWAR \ TWI (Slave) Address register
+ $FE constant TWAR_TWA \ TWI (Slave) Address register Bits
+ $01 constant TWAR_TWGCE \ TWI General Call Recognition Enable Bit
+\ USART0
+&44 constant UDR0 \ USART I/O Data Register
+&43 constant UCSR0A \ USART Control and Status Register A
+ $80 constant UCSR0A_RXC0 \ USART Receive Complete
+ $40 constant UCSR0A_TXC0 \ USART Transmitt Complete
+ $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
+ $10 constant UCSR0A_FE0 \ Framing Error
+ $08 constant UCSR0A_DOR0 \ Data overRun
+ $04 constant UCSR0A_UPE0 \ Parity Error
+ $02 constant UCSR0A_U2X0 \ Double the USART transmission speed
+ $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
+&42 constant UCSR0B \ USART Control and Status Register B
+ $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
+ $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
+ $20 constant UCSR0B_UDRIE0 \ USART Data register Empty Interrupt Enable
+ $10 constant UCSR0B_RXEN0 \ Receiver Enable
+ $08 constant UCSR0B_TXEN0 \ Transmitter Enable
+ $04 constant UCSR0B_UCSZ02 \ Character Size
+ $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
+ $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
+&149 constant UCSR0C \ USART Control and Status Register C
+ $40 constant UCSR0C_UMSEL0 \ USART Mode Select
+ $30 constant UCSR0C_UPM0 \ Parity Mode Bits
+ $08 constant UCSR0C_USBS0 \ Stop Bit Select
+ $06 constant UCSR0C_UCSZ0 \ Character Size
+ $01 constant UCSR0C_UCPOL0 \ Clock Polarity
+&144 constant UBRR0H \ USART Baud Rate Register Hight Byte
+&41 constant UBRR0L \ USART Baud Rate Register Low Byte
+\ USART1
+&156 constant UDR1 \ USART I/O Data Register
+&155 constant UCSR1A \ USART Control and Status Register A
+ $80 constant UCSR1A_RXC1 \ USART Receive Complete
+ $40 constant UCSR1A_TXC1 \ USART Transmitt Complete
+ $20 constant UCSR1A_UDRE1 \ USART Data Register Empty
+ $10 constant UCSR1A_FE1 \ Framing Error
+ $08 constant UCSR1A_DOR1 \ Data overRun
+ $04 constant UCSR1A_UPE1 \ Parity Error
+ $02 constant UCSR1A_U2X1 \ Double the USART transmission speed
+ $01 constant UCSR1A_MPCM1 \ Multi-processor Communication Mode
+&154 constant UCSR1B \ USART Control and Status Register B
+ $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable
+ $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable
+ $20 constant UCSR1B_UDRIE1 \ USART Data register Empty Interrupt Enable
+ $10 constant UCSR1B_RXEN1 \ Receiver Enable
+ $08 constant UCSR1B_TXEN1 \ Transmitter Enable
+ $04 constant UCSR1B_UCSZ12 \ Character Size
+ $02 constant UCSR1B_RXB81 \ Receive Data Bit 8
+ $01 constant UCSR1B_TXB81 \ Transmit Data Bit 8
+&157 constant UCSR1C \ USART Control and Status Register C
+ $40 constant UCSR1C_UMSEL1 \ USART Mode Select
+ $30 constant UCSR1C_UPM1 \ Parity Mode Bits
+ $08 constant UCSR1C_USBS1 \ Stop Bit Select
+ $06 constant UCSR1C_UCSZ1 \ Character Size
+ $01 constant UCSR1C_UCPOL1 \ Clock Polarity
+&152 constant UBRR1H \ USART Baud Rate Register Hight Byte
+&153 constant UBRR1L \ USART Baud Rate Register Low Byte
+\ CPU
+&95 constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ $08 constant SREG_V \ Two's Complement Overflow Flag
+ $04 constant SREG_N \ Negative Flag
+ $02 constant SREG_Z \ Zero Flag
+ $01 constant SREG_C \ Carry Flag
+&93 constant SP \ Stack Pointer
+&85 constant MCUCR \ MCU Control Register
+ $80 constant MCUCR_SRE \ External SRAM Enable
+ $40 constant MCUCR_SRW10 \ External SRAM Wait State Select
+ $20 constant MCUCR_SE \ Sleep Enable
+ $18 constant MCUCR_SM \ Sleep Mode Select
+ $04 constant MCUCR_SM2 \ Sleep Mode Select
+ $02 constant MCUCR_IVSEL \ Interrupt Vector Select
+ $01 constant MCUCR_IVCE \ Interrupt Vector Change Enable
+&84 constant MCUCSR \ MCU Control And Status Register
+ $80 constant MCUCSR_JTD \ JTAG Interface Disable
+ $10 constant MCUCSR_JTRF \ JTAG Reset Flag
+ $08 constant MCUCSR_WDRF \ Watchdog Reset Flag
+ $04 constant MCUCSR_BORF \ Brown-out Reset Flag
+ $02 constant MCUCSR_EXTRF \ External Reset Flag
+ $01 constant MCUCSR_PORF \ Power-on reset flag
+&109 constant XMCRA \ External Memory Control Register A
+ $70 constant XMCRA_SRL \ Wait state page limit
+ $0C constant XMCRA_SRW0 \ Wait state select bit lower page
+ $02 constant XMCRA_SRW11 \ Wait state select bit upper page
+&108 constant XMCRB \ External Memory Control Register B
+ $80 constant XMCRB_XMBK \ External Memory Bus Keeper Enable
+ $07 constant XMCRB_XMM \ External Memory High Mask
+&111 constant OSCCAL \ Oscillator Calibration Value
+&92 constant XDIV \ XTAL Divide Control Register
+ $80 constant XDIV_XDIVEN \ XTAL Divide Enable
+ $7F constant XDIV_XDIV \ XTAl Divide Select Bits
+\ BOOT_LOAD
+&104 constant SPMCSR \ Store Program Memory Control Register
+ $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
+ $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
+ $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
+ $04 constant SPMCSR_PGWRT \ Page Write
+ $02 constant SPMCSR_PGERS \ Page Erase
+ $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
+\ JTAG
+&66 constant OCDR \ On-Chip Debug Related Register in I/O Memory
+ $FF constant OCDR_OCDR \ On-Chip Debug Register Bits
+\ MISC
+\ EXTERNAL_INTERRUPT
+&106 constant EICRA \ External Interrupt Control Register A
+ $C0 constant EICRA_ISC3 \ External Interrupt Sense Control Bit
+ $30 constant EICRA_ISC2 \ External Interrupt Sense Control Bit
+ $0C constant EICRA_ISC1 \ External Interrupt Sense Control Bit
+ $03 constant EICRA_ISC0 \ External Interrupt Sense Control Bit
+&90 constant EICRB \ External Interrupt Control Register B
+ $C0 constant EICRB_ISC7 \ External Interrupt 7-4 Sense Control Bit
+ $30 constant EICRB_ISC6 \ External Interrupt 7-4 Sense Control Bit
+ $0C constant EICRB_ISC5 \ External Interrupt 7-4 Sense Control Bit
+ $03 constant EICRB_ISC4 \ External Interrupt 7-4 Sense Control Bit
+&89 constant EIMSK \ External Interrupt Mask Register
+ $FF constant EIMSK_INT \ External Interrupt Request 7 Enable
+&88 constant EIFR \ External Interrupt Flag Register
+ $FF constant EIFR_INTF \ External Interrupt Flags
+\ EEPROM
+&62 constant EEAR \ EEPROM Read/Write Access Bytes
+&61 constant EEDR \ EEPROM Data Register
+&60 constant EECR \ EEPROM Control Register
+ $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
+ $04 constant EECR_EEMWE \ EEPROM Master Write Enable
+ $02 constant EECR_EEWE \ EEPROM Write Enable
+ $01 constant EECR_EERE \ EEPROM Read Enable
+\ PORTA
+&59 constant PORTA \ Port A Data Register
+&58 constant DDRA \ Port A Data Direction Register
+&57 constant PINA \ Port A Input Pins
+\ PORTB
+&56 constant PORTB \ Port B Data Register
+&55 constant DDRB \ Port B Data Direction Register
+&54 constant PINB \ Port B Input Pins
+\ PORTC
+&53 constant PORTC \ Port C Data Register
+&52 constant DDRC \ Port C Data Direction Register
+&51 constant PINC \ Port C Input Pins
+\ PORTD
+&50 constant PORTD \ Port D Data Register
+&49 constant DDRD \ Port D Data Direction Register
+&48 constant PIND \ Port D Input Pins
+\ PORTE
+&35 constant PORTE \ Data Register, Port E
+&34 constant DDRE \ Data Direction Register, Port E
+&33 constant PINE \ Input Pins, Port E
+\ PORTF
+&98 constant PORTF \ Data Register, Port F
+&97 constant DDRF \ Data Direction Register, Port F
+&32 constant PINF \ Input Pins, Port F
+\ PORTG
+&101 constant PORTG \ Data Register, Port G
+&100 constant DDRG \ Data Direction Register, Port G
+&99 constant PING \ Input Pins, Port G
+\ TIMER_COUNTER_0
+&83 constant TCCR0 \ Timer/Counter Control Register
+ $80 constant TCCR0_FOC0 \ Force Output Compare
+ $40 constant TCCR0_WGM00 \ Waveform Generation Mode 0
+ $30 constant TCCR0_COM0 \ Compare Match Output Modes
+ $08 constant TCCR0_WGM01 \ Waveform Generation Mode 1
+ $07 constant TCCR0_CS0 \ Clock Selects
+&82 constant TCNT0 \ Timer/Counter Register
+&81 constant OCR0 \ Output Compare Register
+&80 constant ASSR \ Asynchronus Status Register
+ $08 constant ASSR_AS0 \ Asynchronus Timer/Counter 0
+ $04 constant ASSR_TCN0UB \ Timer/Counter0 Update Busy
+ $02 constant ASSR_OCR0UB \ Output Compare register 0 Busy
+ $01 constant ASSR_TCR0UB \ Timer/Counter Control Register 0 Update Busy
+&87 constant TIMSK \ Timer/Counter Interrupt Mask Register
+ $02 constant TIMSK_OCIE0 \ Timer/Counter0 Output Compare Match Interrupt register
+ $01 constant TIMSK_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
+&86 constant TIFR \ Timer/Counter Interrupt Flag register
+ $02 constant TIFR_OCF0 \ Output Compare Flag 0
+ $01 constant TIFR_TOV0 \ Timer/Counter0 Overflow Flag
+\ TIMER_COUNTER_1
+&125 constant ETIMSK \ Extended Timer/Counter Interrupt Mask Register
+ $01 constant ETIMSK_OCIE1C \ Timer/Counter 1, Output Compare Match C Interrupt Enable
+&124 constant ETIFR \ Extended Timer/Counter Interrupt Flag register
+ $01 constant ETIFR_OCF1C \ Timer/Counter 1, Output Compare C Match Flag
+&79 constant TCCR1A \ Timer/Counter1 Control Register A
+ $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
+ $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
+ $0C constant TCCR1A_COM1C \ Compare Output Mode 1C, bits
+ $03 constant TCCR1A_WGM1 \ Waveform Generation Mode Bits
+&78 constant TCCR1B \ Timer/Counter1 Control Register B
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
+ $07 constant TCCR1B_CS1 \ Clock Select1 bits
+&122 constant TCCR1C \ Timer/Counter1 Control Register C
+ $80 constant TCCR1C_FOC1A \ Force Output Compare for channel A
+ $40 constant TCCR1C_FOC1B \ Force Output Compare for channel B
+ $20 constant TCCR1C_FOC1C \ Force Output Compare for channel C
+&76 constant TCNT1 \ Timer/Counter1 Bytes
+&74 constant OCR1A \ Timer/Counter1 Output Compare Register Bytes
+&72 constant OCR1B \ Timer/Counter1 Output Compare Register Bytes
+&120 constant OCR1C \ Timer/Counter1 Output Compare Register Bytes
+&70 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
+\ TIMER_COUNTER_2
+&69 constant TCCR2 \ Timer/Counter Control Register
+ $80 constant TCCR2_FOC2 \ Force Output Compare
+ $40 constant TCCR2_WGM20 \ Wafeform Generation Mode
+ $30 constant TCCR2_COM2 \ Compare Match Output Mode
+ $08 constant TCCR2_WGM21 \ Waveform Generation Mode
+ $07 constant TCCR2_CS2 \ Clock Select
+&68 constant TCNT2 \ Timer/Counter Register
+&67 constant OCR2 \ Output Compare Register
+\ TIMER_COUNTER_3
+&139 constant TCCR3A \ Timer/Counter3 Control Register A
+ $C0 constant TCCR3A_COM3A \ Compare Output Mode 3A, bits
+ $30 constant TCCR3A_COM3B \ Compare Output Mode 3B, bits
+ $0C constant TCCR3A_COM3C \ Compare Output Mode 3C, bits
+ $03 constant TCCR3A_WGM3 \ Waveform Generation Mode Bits
+&138 constant TCCR3B \ Timer/Counter3 Control Register B
+ $80 constant TCCR3B_ICNC3 \ Input Capture 3 Noise Canceler
+ $40 constant TCCR3B_ICES3 \ Input Capture 3 Edge Select
+ $18 constant TCCR3B_WGM3 \ Waveform Generation Mode
+ $07 constant TCCR3B_CS3 \ Clock Select3 bits
+&140 constant TCCR3C \ Timer/Counter3 Control Register C
+ $80 constant TCCR3C_FOC3A \ Force Output Compare for channel A
+ $40 constant TCCR3C_FOC3B \ Force Output Compare for channel B
+ $20 constant TCCR3C_FOC3C \ Force Output Compare for channel C
+&136 constant TCNT3 \ Timer/Counter3 Bytes
+&134 constant OCR3A \ Timer/Counter3 Output Compare Register A Bytes
+&132 constant OCR3B \ Timer/Counter3 Output Compare Register B Bytes
+&130 constant OCR3C \ Timer/Counter3 Output compare Register C Bytes
+&128 constant ICR3 \ Timer/Counter3 Input Capture Register Bytes
+\ WATCHDOG
+&65 constant WDTCR \ Watchdog Timer Control Register
+ $10 constant WDTCR_WDCE \ Watchdog Change Enable
+ $08 constant WDTCR_WDE \ Watch Dog Enable
+ $07 constant WDTCR_WDP \ Watch Dog Timer Prescaler bits
+
+\ Interrupts
+&2 constant INT0Addr \ External Interrupt Request 0
+&4 constant INT1Addr \ External Interrupt Request 1
+&6 constant INT2Addr \ External Interrupt Request 2
+&8 constant INT3Addr \ External Interrupt Request 3
+&10 constant INT4Addr \ External Interrupt Request 4
+&12 constant INT5Addr \ External Interrupt Request 5
+&14 constant INT6Addr \ External Interrupt Request 6
+&16 constant INT7Addr \ External Interrupt Request 7
+&18 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
+&20 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
+&22 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+&24 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
+&26 constant TIMER1_COMPBAddr \ Timer/Counter Compare Match B
+&28 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+&30 constant TIMER0_COMPAddr \ Timer/Counter0 Compare Match
+&32 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
+&34 constant SPI__STCAddr \ SPI Serial Transfer Complete
+&36 constant USART0__RXAddr \ USART0, Rx Complete
+&38 constant USART0__UDREAddr \ USART0 Data Register Empty
+&40 constant USART0__TXAddr \ USART0, Tx Complete
+&42 constant ADCAddr \ ADC Conversion Complete
+&44 constant EE_READYAddr \ EEPROM Ready
+&46 constant ANALOG_COMPAddr \ Analog Comparator
+&48 constant TIMER1_COMPCAddr \ Timer/Counter1 Compare Match C
+&50 constant TIMER3_CAPTAddr \ Timer/Counter3 Capture Event
+&52 constant TIMER3_COMPAAddr \ Timer/Counter3 Compare Match A
+&54 constant TIMER3_COMPBAddr \ Timer/Counter3 Compare Match B
+&56 constant TIMER3_COMPCAddr \ Timer/Counter3 Compare Match C
+&58 constant TIMER3_OVFAddr \ Timer/Counter3 Overflow
+&60 constant USART1__RXAddr \ USART1, Rx Complete
+&62 constant USART1__UDREAddr \ USART1, Data Register Empty
+&64 constant USART1__TXAddr \ USART1, Tx Complete
+&66 constant TWIAddr \ 2-wire Serial Interface
+&68 constant SPM_READYAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/atmega64/device.asm b/amforth-6.5/avr8/devices/atmega64/device.asm
new file mode 100644
index 0000000..1bfc5bb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega64/device.asm
@@ -0,0 +1,135 @@
+; Partname: ATmega64
+; generated automatically, do not edit
+
+.nolist
+ .include "m64def.inc"
+.list
+
+.equ ramstart = 256
+.equ CELLSIZE = 2
+.macro readflashcell
+ lsl zl
+ rol zh
+ lpm @0, Z+
+ lpm @1, Z+
+.endmacro
+.macro writeflashcell
+ lsl zl
+ rol zh
+.endmacro
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_AD_CONVERTER = 0
+.set WANT_SPI = 0
+.set WANT_TWI = 0
+.set WANT_USART0 = 0
+.set WANT_USART1 = 0
+.set WANT_CPU = 0
+.set WANT_BOOT_LOAD = 0
+.set WANT_JTAG = 0
+.set WANT_MISC = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_EEPROM = 0
+.set WANT_PORTA = 0
+.set WANT_PORTB = 0
+.set WANT_PORTC = 0
+.set WANT_PORTD = 0
+.set WANT_PORTE = 0
+.set WANT_PORTF = 0
+.set WANT_PORTG = 0
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_TIMER_COUNTER_2 = 0
+.set WANT_TIMER_COUNTER_3 = 0
+.set WANT_WATCHDOG = 0
+.equ intvecsize = 2 ; please verify; flash size: 65536 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.org 2
+ rcall isr ; External Interrupt Request 0
+.org 4
+ rcall isr ; External Interrupt Request 1
+.org 6
+ rcall isr ; External Interrupt Request 2
+.org 8
+ rcall isr ; External Interrupt Request 3
+.org 10
+ rcall isr ; External Interrupt Request 4
+.org 12
+ rcall isr ; External Interrupt Request 5
+.org 14
+ rcall isr ; External Interrupt Request 6
+.org 16
+ rcall isr ; External Interrupt Request 7
+.org 18
+ rcall isr ; Timer/Counter2 Compare Match
+.org 20
+ rcall isr ; Timer/Counter2 Overflow
+.org 22
+ rcall isr ; Timer/Counter1 Capture Event
+.org 24
+ rcall isr ; Timer/Counter1 Compare Match A
+.org 26
+ rcall isr ; Timer/Counter Compare Match B
+.org 28
+ rcall isr ; Timer/Counter1 Overflow
+.org 30
+ rcall isr ; Timer/Counter0 Compare Match
+.org 32
+ rcall isr ; Timer/Counter0 Overflow
+.org 34
+ rcall isr ; SPI Serial Transfer Complete
+.org 36
+ rcall isr ; USART0, Rx Complete
+.org 38
+ rcall isr ; USART0 Data Register Empty
+.org 40
+ rcall isr ; USART0, Tx Complete
+.org 42
+ rcall isr ; ADC Conversion Complete
+.org 44
+ rcall isr ; EEPROM Ready
+.org 46
+ rcall isr ; Analog Comparator
+.org 48
+ rcall isr ; Timer/Counter1 Compare Match C
+.org 50
+ rcall isr ; Timer/Counter3 Capture Event
+.org 52
+ rcall isr ; Timer/Counter3 Compare Match A
+.org 54
+ rcall isr ; Timer/Counter3 Compare Match B
+.org 56
+ rcall isr ; Timer/Counter3 Compare Match C
+.org 58
+ rcall isr ; Timer/Counter3 Overflow
+.org 60
+ rcall isr ; USART1, Rx Complete
+.org 62
+ rcall isr ; USART1, Data Register Empty
+.org 64
+ rcall isr ; USART1, Tx Complete
+.org 66
+ rcall isr ; 2-wire Serial Interface
+.org 68
+ rcall isr ; Store Program Memory Read
+.equ INTVECTORS = 35
+.nooverlap
+
+; compatability layer (maybe empty)
+.equ EEPE = EEWE
+.equ EEMPE = EEMWE
+
+; controller data area, environment query mcu-info
+mcu_info:
+mcu_ramsize:
+ .dw 4096
+mcu_eepromsize:
+ .dw 2048
+mcu_maxdp:
+ .dw 57344
+mcu_numints:
+ .dw 35
+mcu_name:
+ .dw 8
+ .db "ATmega64"
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega64/device.inc b/amforth-6.5/avr8/devices/atmega64/device.inc
new file mode 100644
index 0000000..ca671b9
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega64/device.inc
@@ -0,0 +1,1179 @@
+; Partname: ATmega64
+; generated automatically, no not edit
+
+.if WANT_ANALOG_COMPARATOR == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Special Function IO Register
+VE_SFIOR:
+ .dw $ff05
+ .db "SFIOR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SFIOR
+XT_SFIOR:
+ .dw PFA_DOVARIABLE
+PFA_SFIOR:
+ .dw 64
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Control And Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw 40
+
+.endif
+.if WANT_AD_CONVERTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC multiplexer Selection Register
+VE_ADMUX:
+ .dw $ff05
+ .db "ADMUX",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADMUX
+XT_ADMUX:
+ .dw PFA_DOVARIABLE
+PFA_ADMUX:
+ .dw 39
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register Bytes
+VE_ADC:
+ .dw $ff03
+ .db "ADC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADC
+XT_ADC:
+ .dw PFA_DOVARIABLE
+PFA_ADC:
+ .dw 36
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register A
+VE_ADCSRA:
+ .dw $ff06
+ .db "ADCSRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRA
+XT_ADCSRA:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRA:
+ .dw 38
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register B
+VE_ADCSRB:
+ .dw $ff06
+ .db "ADCSRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRB
+XT_ADCSRB:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRB:
+ .dw 142
+
+.endif
+.if WANT_SPI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR:
+ .dw $ff04
+ .db "SPDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR
+XT_SPDR:
+ .dw PFA_DOVARIABLE
+PFA_SPDR:
+ .dw 47
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR:
+ .dw $ff04
+ .db "SPSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR
+XT_SPSR:
+ .dw PFA_DOVARIABLE
+PFA_SPSR:
+ .dw 46
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR:
+ .dw $ff04
+ .db "SPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR
+XT_SPCR:
+ .dw PFA_DOVARIABLE
+PFA_SPCR:
+ .dw 45
+
+.endif
+.if WANT_TWI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Bit Rate register
+VE_TWBR:
+ .dw $ff04
+ .db "TWBR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWBR
+XT_TWBR:
+ .dw PFA_DOVARIABLE
+PFA_TWBR:
+ .dw 112
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Control Register
+VE_TWCR:
+ .dw $ff04
+ .db "TWCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWCR
+XT_TWCR:
+ .dw PFA_DOVARIABLE
+PFA_TWCR:
+ .dw 116
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Status Register
+VE_TWSR:
+ .dw $ff04
+ .db "TWSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWSR
+XT_TWSR:
+ .dw PFA_DOVARIABLE
+PFA_TWSR:
+ .dw 113
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Data register
+VE_TWDR:
+ .dw $ff04
+ .db "TWDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWDR
+XT_TWDR:
+ .dw PFA_DOVARIABLE
+PFA_TWDR:
+ .dw 115
+; ( -- addr ) System Constant
+; R( -- )
+; TWI (Slave) Address register
+VE_TWAR:
+ .dw $ff04
+ .db "TWAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWAR
+XT_TWAR:
+ .dw PFA_DOVARIABLE
+PFA_TWAR:
+ .dw 114
+
+.endif
+.if WANT_USART0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR0:
+ .dw $ff04
+ .db "UDR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR0
+XT_UDR0:
+ .dw PFA_DOVARIABLE
+PFA_UDR0:
+ .dw 44
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR0A:
+ .dw $ff06
+ .db "UCSR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0A
+XT_UCSR0A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0A:
+ .dw 43
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR0B:
+ .dw $ff06
+ .db "UCSR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0B
+XT_UCSR0B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0B:
+ .dw 42
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR0C:
+ .dw $ff06
+ .db "UCSR0C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0C
+XT_UCSR0C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0C:
+ .dw 149
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Hight Byte
+VE_UBRR0H:
+ .dw $ff06
+ .db "UBRR0H"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR0H
+XT_UBRR0H:
+ .dw PFA_DOVARIABLE
+PFA_UBRR0H:
+ .dw 144
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Low Byte
+VE_UBRR0L:
+ .dw $ff06
+ .db "UBRR0L"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR0L
+XT_UBRR0L:
+ .dw PFA_DOVARIABLE
+PFA_UBRR0L:
+ .dw 41
+
+.endif
+.if WANT_USART1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR1:
+ .dw $ff04
+ .db "UDR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR1
+XT_UDR1:
+ .dw PFA_DOVARIABLE
+PFA_UDR1:
+ .dw 156
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR1A:
+ .dw $ff06
+ .db "UCSR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1A
+XT_UCSR1A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1A:
+ .dw 155
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR1B:
+ .dw $ff06
+ .db "UCSR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1B
+XT_UCSR1B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1B:
+ .dw 154
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR1C:
+ .dw $ff06
+ .db "UCSR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1C
+XT_UCSR1C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1C:
+ .dw 157
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Hight Byte
+VE_UBRR1H:
+ .dw $ff06
+ .db "UBRR1H"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR1H
+XT_UBRR1H:
+ .dw PFA_DOVARIABLE
+PFA_UBRR1H:
+ .dw 152
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Low Byte
+VE_UBRR1L:
+ .dw $ff06
+ .db "UBRR1L"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR1L
+XT_UBRR1L:
+ .dw PFA_DOVARIABLE
+PFA_UBRR1L:
+ .dw 153
+
+.endif
+.if WANT_CPU == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw 95
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer
+VE_SP:
+ .dw $ff02
+ .db "SP"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SP
+XT_SP:
+ .dw PFA_DOVARIABLE
+PFA_SP:
+ .dw 93
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw 85
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control And Status Register
+VE_MCUCSR:
+ .dw $ff06
+ .db "MCUCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCSR
+XT_MCUCSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCSR:
+ .dw 84
+; ( -- addr ) System Constant
+; R( -- )
+; External Memory Control Register A
+VE_XMCRA:
+ .dw $ff05
+ .db "XMCRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_XMCRA
+XT_XMCRA:
+ .dw PFA_DOVARIABLE
+PFA_XMCRA:
+ .dw 109
+; ( -- addr ) System Constant
+; R( -- )
+; External Memory Control Register B
+VE_XMCRB:
+ .dw $ff05
+ .db "XMCRB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_XMCRB
+XT_XMCRB:
+ .dw PFA_DOVARIABLE
+PFA_XMCRB:
+ .dw 108
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Calibration Value
+VE_OSCCAL:
+ .dw $ff06
+ .db "OSCCAL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSCCAL
+XT_OSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_OSCCAL:
+ .dw 111
+; ( -- addr ) System Constant
+; R( -- )
+; XTAL Divide Control Register
+VE_XDIV:
+ .dw $ff04
+ .db "XDIV"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_XDIV
+XT_XDIV:
+ .dw PFA_DOVARIABLE
+PFA_XDIV:
+ .dw 92
+
+.endif
+.if WANT_BOOT_LOAD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control Register
+VE_SPMCSR:
+ .dw $ff06
+ .db "SPMCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCSR
+XT_SPMCSR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCSR:
+ .dw 104
+
+.endif
+.if WANT_JTAG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; On-Chip Debug Related Register in I/O Memory
+VE_OCDR:
+ .dw $ff04
+ .db "OCDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCDR
+XT_OCDR:
+ .dw PFA_DOVARIABLE
+PFA_OCDR:
+ .dw 66
+
+.endif
+.if WANT_MISC == 1
+
+.endif
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register A
+VE_EICRA:
+ .dw $ff05
+ .db "EICRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRA
+XT_EICRA:
+ .dw PFA_DOVARIABLE
+PFA_EICRA:
+ .dw 106
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register B
+VE_EICRB:
+ .dw $ff05
+ .db "EICRB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRB
+XT_EICRB:
+ .dw PFA_DOVARIABLE
+PFA_EICRB:
+ .dw 90
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Mask Register
+VE_EIMSK:
+ .dw $ff05
+ .db "EIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIMSK
+XT_EIMSK:
+ .dw PFA_DOVARIABLE
+PFA_EIMSK:
+ .dw 89
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Flag Register
+VE_EIFR:
+ .dw $ff04
+ .db "EIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIFR
+XT_EIFR:
+ .dw PFA_DOVARIABLE
+PFA_EIFR:
+ .dw 88
+
+.endif
+.if WANT_EEPROM == 1
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Read/Write Access Bytes
+VE_EEAR:
+ .dw $ff04
+ .db "EEAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEAR
+XT_EEAR:
+ .dw PFA_DOVARIABLE
+PFA_EEAR:
+ .dw 62
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw 61
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw 60
+
+.endif
+.if WANT_PORTA == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Register
+VE_PORTA:
+ .dw $ff05
+ .db "PORTA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTA
+XT_PORTA:
+ .dw PFA_DOVARIABLE
+PFA_PORTA:
+ .dw 59
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Direction Register
+VE_DDRA:
+ .dw $ff04
+ .db "DDRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRA
+XT_DDRA:
+ .dw PFA_DOVARIABLE
+PFA_DDRA:
+ .dw 58
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Input Pins
+VE_PINA:
+ .dw $ff04
+ .db "PINA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINA
+XT_PINA:
+ .dw PFA_DOVARIABLE
+PFA_PINA:
+ .dw 57
+
+.endif
+.if WANT_PORTB == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw 56
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw 55
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw 54
+
+.endif
+.if WANT_PORTC == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Register
+VE_PORTC:
+ .dw $ff05
+ .db "PORTC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTC
+XT_PORTC:
+ .dw PFA_DOVARIABLE
+PFA_PORTC:
+ .dw 53
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Direction Register
+VE_DDRC:
+ .dw $ff04
+ .db "DDRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRC
+XT_DDRC:
+ .dw PFA_DOVARIABLE
+PFA_DDRC:
+ .dw 52
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Input Pins
+VE_PINC:
+ .dw $ff04
+ .db "PINC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINC
+XT_PINC:
+ .dw PFA_DOVARIABLE
+PFA_PINC:
+ .dw 51
+
+.endif
+.if WANT_PORTD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw 50
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw 49
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw 48
+
+.endif
+.if WANT_PORTE == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port E
+VE_PORTE:
+ .dw $ff05
+ .db "PORTE",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTE
+XT_PORTE:
+ .dw PFA_DOVARIABLE
+PFA_PORTE:
+ .dw 35
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port E
+VE_DDRE:
+ .dw $ff04
+ .db "DDRE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRE
+XT_DDRE:
+ .dw PFA_DOVARIABLE
+PFA_DDRE:
+ .dw 34
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port E
+VE_PINE:
+ .dw $ff04
+ .db "PINE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINE
+XT_PINE:
+ .dw PFA_DOVARIABLE
+PFA_PINE:
+ .dw 33
+
+.endif
+.if WANT_PORTF == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port F
+VE_PORTF:
+ .dw $ff05
+ .db "PORTF",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTF
+XT_PORTF:
+ .dw PFA_DOVARIABLE
+PFA_PORTF:
+ .dw 98
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port F
+VE_DDRF:
+ .dw $ff04
+ .db "DDRF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRF
+XT_DDRF:
+ .dw PFA_DOVARIABLE
+PFA_DDRF:
+ .dw 97
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port F
+VE_PINF:
+ .dw $ff04
+ .db "PINF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINF
+XT_PINF:
+ .dw PFA_DOVARIABLE
+PFA_PINF:
+ .dw 32
+
+.endif
+.if WANT_PORTG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port G
+VE_PORTG:
+ .dw $ff05
+ .db "PORTG",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTG
+XT_PORTG:
+ .dw PFA_DOVARIABLE
+PFA_PORTG:
+ .dw 101
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port G
+VE_DDRG:
+ .dw $ff04
+ .db "DDRG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRG
+XT_DDRG:
+ .dw PFA_DOVARIABLE
+PFA_DDRG:
+ .dw 100
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port G
+VE_PING:
+ .dw $ff04
+ .db "PING"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PING
+XT_PING:
+ .dw PFA_DOVARIABLE
+PFA_PING:
+ .dw 99
+
+.endif
+.if WANT_TIMER_COUNTER_0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register
+VE_TCCR0:
+ .dw $ff05
+ .db "TCCR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0
+XT_TCCR0:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0:
+ .dw 83
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Register
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw 82
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare Register
+VE_OCR0:
+ .dw $ff04
+ .db "OCR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0
+XT_OCR0:
+ .dw PFA_DOVARIABLE
+PFA_OCR0:
+ .dw 81
+; ( -- addr ) System Constant
+; R( -- )
+; Asynchronus Status Register
+VE_ASSR:
+ .dw $ff04
+ .db "ASSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ASSR
+XT_ASSR:
+ .dw PFA_DOVARIABLE
+PFA_ASSR:
+ .dw 80
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Mask Register
+VE_TIMSK:
+ .dw $ff05
+ .db "TIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK
+XT_TIMSK:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK:
+ .dw 87
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Flag register
+VE_TIFR:
+ .dw $ff04
+ .db "TIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR
+XT_TIFR:
+ .dw PFA_DOVARIABLE
+PFA_TIFR:
+ .dw 86
+
+.endif
+.if WANT_TIMER_COUNTER_1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Extended Timer/Counter Interrupt Mask Register
+VE_ETIMSK:
+ .dw $ff06
+ .db "ETIMSK"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ETIMSK
+XT_ETIMSK:
+ .dw PFA_DOVARIABLE
+PFA_ETIMSK:
+ .dw 125
+; ( -- addr ) System Constant
+; R( -- )
+; Extended Timer/Counter Interrupt Flag register
+VE_ETIFR:
+ .dw $ff05
+ .db "ETIFR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ETIFR
+XT_ETIFR:
+ .dw PFA_DOVARIABLE
+PFA_ETIFR:
+ .dw 124
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw 79
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw 78
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register C
+VE_TCCR1C:
+ .dw $ff06
+ .db "TCCR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1C
+XT_TCCR1C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1C:
+ .dw 122
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Bytes
+VE_TCNT1:
+ .dw $ff05
+ .db "TCNT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1
+XT_TCNT1:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1:
+ .dw 76
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register Bytes
+VE_OCR1A:
+ .dw $ff05
+ .db "OCR1A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1A
+XT_OCR1A:
+ .dw PFA_DOVARIABLE
+PFA_OCR1A:
+ .dw 74
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register Bytes
+VE_OCR1B:
+ .dw $ff05
+ .db "OCR1B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1B
+XT_OCR1B:
+ .dw PFA_DOVARIABLE
+PFA_OCR1B:
+ .dw 72
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register Bytes
+VE_OCR1C:
+ .dw $ff05
+ .db "OCR1C",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1C
+XT_OCR1C:
+ .dw PFA_DOVARIABLE
+PFA_OCR1C:
+ .dw 120
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Bytes
+VE_ICR1:
+ .dw $ff04
+ .db "ICR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1
+XT_ICR1:
+ .dw PFA_DOVARIABLE
+PFA_ICR1:
+ .dw 70
+
+.endif
+.if WANT_TIMER_COUNTER_2 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register
+VE_TCCR2:
+ .dw $ff05
+ .db "TCCR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2
+XT_TCCR2:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2:
+ .dw 69
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Register
+VE_TCNT2:
+ .dw $ff05
+ .db "TCNT2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT2
+XT_TCNT2:
+ .dw PFA_DOVARIABLE
+PFA_TCNT2:
+ .dw 68
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare Register
+VE_OCR2:
+ .dw $ff04
+ .db "OCR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2
+XT_OCR2:
+ .dw PFA_DOVARIABLE
+PFA_OCR2:
+ .dw 67
+
+.endif
+.if WANT_TIMER_COUNTER_3 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Control Register A
+VE_TCCR3A:
+ .dw $ff06
+ .db "TCCR3A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR3A
+XT_TCCR3A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR3A:
+ .dw 139
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Control Register B
+VE_TCCR3B:
+ .dw $ff06
+ .db "TCCR3B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR3B
+XT_TCCR3B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR3B:
+ .dw 138
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Control Register C
+VE_TCCR3C:
+ .dw $ff06
+ .db "TCCR3C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR3C
+XT_TCCR3C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR3C:
+ .dw 140
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Bytes
+VE_TCNT3:
+ .dw $ff05
+ .db "TCNT3",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT3
+XT_TCNT3:
+ .dw PFA_DOVARIABLE
+PFA_TCNT3:
+ .dw 136
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Output Compare Register A Bytes
+VE_OCR3A:
+ .dw $ff05
+ .db "OCR3A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR3A
+XT_OCR3A:
+ .dw PFA_DOVARIABLE
+PFA_OCR3A:
+ .dw 134
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Output Compare Register B Bytes
+VE_OCR3B:
+ .dw $ff05
+ .db "OCR3B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR3B
+XT_OCR3B:
+ .dw PFA_DOVARIABLE
+PFA_OCR3B:
+ .dw 132
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Output compare Register C Bytes
+VE_OCR3C:
+ .dw $ff05
+ .db "OCR3C",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR3C
+XT_OCR3C:
+ .dw PFA_DOVARIABLE
+PFA_OCR3C:
+ .dw 130
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Input Capture Register Bytes
+VE_ICR3:
+ .dw $ff04
+ .db "ICR3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR3
+XT_ICR3:
+ .dw PFA_DOVARIABLE
+PFA_ICR3:
+ .dw 128
+
+.endif
+.if WANT_WATCHDOG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCR:
+ .dw $ff05
+ .db "WDTCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCR
+XT_WDTCR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCR:
+ .dw 65
+
+.endif
diff --git a/amforth-6.5/avr8/devices/atmega64/device.py b/amforth-6.5/avr8/devices/atmega64/device.py
new file mode 100644
index 0000000..dc1f517
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega64/device.py
@@ -0,0 +1,405 @@
+# Generated Automatically
+
+# Partname ATmega64
+
+MCUREGS = {
+# Interrupt Vectors
+ 'INT0Addr' : '#2', # External Interrupt Request 0
+ 'INT1Addr' : '#4', # External Interrupt Request 1
+ 'INT2Addr' : '#6', # External Interrupt Request 2
+ 'INT3Addr' : '#8', # External Interrupt Request 3
+ 'INT4Addr' : '#10', # External Interrupt Request 4
+ 'INT5Addr' : '#12', # External Interrupt Request 5
+ 'INT6Addr' : '#14', # External Interrupt Request 6
+ 'INT7Addr' : '#16', # External Interrupt Request 7
+ 'TIMER2_COMPAddr' : '#18', # Timer/Counter2 Compare Match
+ 'TIMER2_OVFAddr' : '#20', # Timer/Counter2 Overflow
+ 'TIMER1_CAPTAddr' : '#22', # Timer/Counter1 Capture Event
+ 'TIMER1_COMPAAddr' : '#24', # Timer/Counter1 Compare Match A
+ 'TIMER1_COMPBAddr' : '#26', # Timer/Counter Compare Match B
+ 'TIMER1_OVFAddr' : '#28', # Timer/Counter1 Overflow
+ 'TIMER0_COMPAddr' : '#30', # Timer/Counter0 Compare Match
+ 'TIMER0_OVFAddr' : '#32', # Timer/Counter0 Overflow
+ 'SPI_STCAddr' : '#34', # SPI Serial Transfer Complete
+ 'USART0_RXAddr' : '#36', # USART0, Rx Complete
+ 'USART0_UDREAddr' : '#38', # USART0 Data Register Empty
+ 'USART0_TXAddr' : '#40', # USART0, Tx Complete
+ 'ADCAddr' : '#42', # ADC Conversion Complete
+ 'EE_READYAddr' : '#44', # EEPROM Ready
+ 'ANALOG_COMPAddr' : '#46', # Analog Comparator
+ 'TIMER1_COMPCAddr' : '#48', # Timer/Counter1 Compare Match C
+ 'TIMER3_CAPTAddr' : '#50', # Timer/Counter3 Capture Event
+ 'TIMER3_COMPAAddr' : '#52', # Timer/Counter3 Compare Match A
+ 'TIMER3_COMPBAddr' : '#54', # Timer/Counter3 Compare Match B
+ 'TIMER3_COMPCAddr' : '#56', # Timer/Counter3 Compare Match C
+ 'TIMER3_OVFAddr' : '#58', # Timer/Counter3 Overflow
+ 'USART1_RXAddr' : '#60', # USART1, Rx Complete
+ 'USART1_UDREAddr' : '#62', # USART1, Data Register Empty
+ 'USART1_TXAddr' : '#64', # USART1, Tx Complete
+ 'TWIAddr' : '#66', # 2-wire Serial Interface
+ 'SPM_READYAddr' : '#68', # Store Program Memory Read
+
+# Module ANALOG_COMPARATOR
+ 'SFIOR' : '$40', # Special Function IO Register
+ 'SFIOR_ACME': '$8', # Analog Comparator Multiplexer
+ 'ACSR' : '$28', # Analog Comparator Control And
+ 'ACSR_ACD': '$80', # Analog Comparator Disable
+ 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
+ 'ACSR_ACO': '$20', # Analog Compare Output
+ 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
+ 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
+ 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
+ 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
+
+# Module AD_CONVERTER
+ 'ADMUX' : '$27', # The ADC multiplexer Selection
+ 'ADMUX_REFS': '$c0', # Reference Selection Bits
+ 'ADMUX_ADLAR': '$20', # Left Adjust Result
+ 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
+ 'ADC' : '$24', # ADC Data Register Bytes
+ 'ADCSRA' : '$26', # The ADC Control and Status reg
+ 'ADCSRA_ADEN': '$80', # ADC Enable
+ 'ADCSRA_ADSC': '$40', # ADC Start Conversion
+ 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
+ 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
+ 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
+ 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
+ 'ADCSRB' : '$8e', # The ADC Control and Status reg
+ 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Source bits
+
+# Module SPI
+ 'SPDR' : '$2f', # SPI Data Register
+ 'SPSR' : '$2e', # SPI Status Register
+ 'SPSR_SPIF': '$80', # SPI Interrupt Flag
+ 'SPSR_WCOL': '$40', # Write Collision Flag
+ 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
+ 'SPCR' : '$2d', # SPI Control Register
+ 'SPCR_SPIE': '$80', # SPI Interrupt Enable
+ 'SPCR_SPE': '$40', # SPI Enable
+ 'SPCR_DORD': '$20', # Data Order
+ 'SPCR_MSTR': '$10', # Master/Slave Select
+ 'SPCR_CPOL': '$8', # Clock polarity
+ 'SPCR_CPHA': '$4', # Clock Phase
+ 'SPCR_SPR': '$3', # SPI Clock Rate Selects
+
+# Module TWI
+ 'TWBR' : '$70', # TWI Bit Rate register
+ 'TWCR' : '$74', # TWI Control Register
+ 'TWCR_TWINT': '$80', # TWI Interrupt Flag
+ 'TWCR_TWEA': '$40', # TWI Enable Acknowledge Bit
+ 'TWCR_TWSTA': '$20', # TWI Start Condition Bit
+ 'TWCR_TWSTO': '$10', # TWI Stop Condition Bit
+ 'TWCR_TWWC': '$8', # TWI Write Collition Flag
+ 'TWCR_TWEN': '$4', # TWI Enable Bit
+ 'TWCR_TWIE': '$1', # TWI Interrupt Enable
+ 'TWSR' : '$71', # TWI Status Register
+ 'TWSR_TWS': '$f8', # TWI Status
+ 'TWSR_TWPS': '$3', # TWI Prescaler
+ 'TWDR' : '$73', # TWI Data register
+ 'TWAR' : '$72', # TWI (Slave) Address register
+ 'TWAR_TWA': '$fe', # TWI (Slave) Address register B
+ 'TWAR_TWGCE': '$1', # TWI General Call Recognition E
+
+# Module USART0
+ 'UDR0' : '$2c', # USART I/O Data Register
+ 'UCSR0A' : '$2b', # USART Control and Status Regis
+ 'UCSR0A_RXC0': '$80', # USART Receive Complete
+ 'UCSR0A_TXC0': '$40', # USART Transmitt Complete
+ 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
+ 'UCSR0A_FE0': '$10', # Framing Error
+ 'UCSR0A_DOR0': '$8', # Data overRun
+ 'UCSR0A_UPE0': '$4', # Parity Error
+ 'UCSR0A_U2X0': '$2', # Double the USART transmission
+ 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
+ 'UCSR0B' : '$2a', # USART Control and Status Regis
+ 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
+ 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
+ 'UCSR0B_UDRIE0': '$20', # USART Data register Empty Inte
+ 'UCSR0B_RXEN0': '$10', # Receiver Enable
+ 'UCSR0B_TXEN0': '$8', # Transmitter Enable
+ 'UCSR0B_UCSZ02': '$4', # Character Size
+ 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
+ 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
+ 'UCSR0C' : '$95', # USART Control and Status Regis
+ 'UCSR0C_UMSEL0': '$40', # USART Mode Select
+ 'UCSR0C_UPM0': '$30', # Parity Mode Bits
+ 'UCSR0C_USBS0': '$8', # Stop Bit Select
+ 'UCSR0C_UCSZ0': '$6', # Character Size
+ 'UCSR0C_UCPOL0': '$1', # Clock Polarity
+ 'UBRR0H' : '$90', # USART Baud Rate Register Hight
+ 'UBRR0L' : '$29', # USART Baud Rate Register Low B
+
+# Module USART1
+ 'UDR1' : '$9c', # USART I/O Data Register
+ 'UCSR1A' : '$9b', # USART Control and Status Regis
+ 'UCSR1A_RXC1': '$80', # USART Receive Complete
+ 'UCSR1A_TXC1': '$40', # USART Transmitt Complete
+ 'UCSR1A_UDRE1': '$20', # USART Data Register Empty
+ 'UCSR1A_FE1': '$10', # Framing Error
+ 'UCSR1A_DOR1': '$8', # Data overRun
+ 'UCSR1A_UPE1': '$4', # Parity Error
+ 'UCSR1A_U2X1': '$2', # Double the USART transmission
+ 'UCSR1A_MPCM1': '$1', # Multi-processor Communication
+ 'UCSR1B' : '$9a', # USART Control and Status Regis
+ 'UCSR1B_RXCIE1': '$80', # RX Complete Interrupt Enable
+ 'UCSR1B_TXCIE1': '$40', # TX Complete Interrupt Enable
+ 'UCSR1B_UDRIE1': '$20', # USART Data register Empty Inte
+ 'UCSR1B_RXEN1': '$10', # Receiver Enable
+ 'UCSR1B_TXEN1': '$8', # Transmitter Enable
+ 'UCSR1B_UCSZ12': '$4', # Character Size
+ 'UCSR1B_RXB81': '$2', # Receive Data Bit 8
+ 'UCSR1B_TXB81': '$1', # Transmit Data Bit 8
+ 'UCSR1C' : '$9d', # USART Control and Status Regis
+ 'UCSR1C_UMSEL1': '$40', # USART Mode Select
+ 'UCSR1C_UPM1': '$30', # Parity Mode Bits
+ 'UCSR1C_USBS1': '$8', # Stop Bit Select
+ 'UCSR1C_UCSZ1': '$6', # Character Size
+ 'UCSR1C_UCPOL1': '$1', # Clock Polarity
+ 'UBRR1H' : '$98', # USART Baud Rate Register Hight
+ 'UBRR1L' : '$99', # USART Baud Rate Register Low B
+
+# Module CPU
+ 'SREG' : '$5f', # Status Register
+ 'SREG_I': '$80', # Global Interrupt Enable
+ 'SREG_T': '$40', # Bit Copy Storage
+ 'SREG_H': '$20', # Half Carry Flag
+ 'SREG_S': '$10', # Sign Bit
+ 'SREG_V': '$8', # Two's Complement Overflow Flag
+ 'SREG_N': '$4', # Negative Flag
+ 'SREG_Z': '$2', # Zero Flag
+ 'SREG_C': '$1', # Carry Flag
+ 'SP' : '$5d', # Stack Pointer
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_SRE': '$80', # External SRAM Enable
+ 'MCUCR_SRW10': '$40', # External SRAM Wait State Selec
+ 'MCUCR_SE': '$20', # Sleep Enable
+ 'MCUCR_SM': '$18', # Sleep Mode Select
+ 'MCUCR_SM2': '$4', # Sleep Mode Select
+ 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
+ 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
+ 'MCUCSR' : '$54', # MCU Control And Status Registe
+ 'MCUCSR_JTD': '$80', # JTAG Interface Disable
+ 'MCUCSR_JTRF': '$10', # JTAG Reset Flag
+ 'MCUCSR_WDRF': '$8', # Watchdog Reset Flag
+ 'MCUCSR_BORF': '$4', # Brown-out Reset Flag
+ 'MCUCSR_EXTRF': '$2', # External Reset Flag
+ 'MCUCSR_PORF': '$1', # Power-on reset flag
+ 'XMCRA' : '$6d', # External Memory Control Regist
+ 'XMCRA_SRL': '$70', # Wait state page limit
+ 'XMCRA_SRW0': '$c', # Wait state select bit lower pa
+ 'XMCRA_SRW11': '$2', # Wait state select bit upper pa
+ 'XMCRB' : '$6c', # External Memory Control Regist
+ 'XMCRB_XMBK': '$80', # External Memory Bus Keeper Ena
+ 'XMCRB_XMM': '$7', # External Memory High Mask
+ 'OSCCAL' : '$6f', # Oscillator Calibration Value
+ 'XDIV' : '$5c', # XTAL Divide Control Register
+ 'XDIV_XDIVEN': '$80', # XTAL Divide Enable
+ 'XDIV_XDIV': '$7f', # XTAl Divide Select Bits
+
+# Module BOOT_LOAD
+ 'SPMCSR' : '$68', # Store Program Memory Control R
+ 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
+ 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
+ 'SPMCSR_RWWSRE': '$10', # Read While Write section read
+ 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
+ 'SPMCSR_PGWRT': '$4', # Page Write
+ 'SPMCSR_PGERS': '$2', # Page Erase
+ 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
+
+# Module JTAG
+ 'OCDR' : '$42', # On-Chip Debug Related Register
+ 'OCDR_OCDR': '$ff', # On-Chip Debug Register Bits
+ 'MCUCSR' : '$54', # MCU Control And Status Registe
+ 'MCUCSR_JTD': '$80', # JTAG Interface Disable
+ 'MCUCSR_JTRF': '$10', # JTAG Reset Flag
+
+# Module MISC
+ 'SFIOR' : '$40', # Special Function IO Register
+ 'SFIOR_TSM': '$80', # Timer/Counter Synchronization
+ 'SFIOR_ACME': '$8', # Analog Comparator Multiplexer
+ 'SFIOR_PUD': '$4', # Pull Up Disable
+ 'SFIOR_PSR0': '$2', # Prescaler Reset Timer/Counter0
+ 'SFIOR_PSR321': '$1', # Prescaler Reset Timer/Counter3
+
+# Module EXTERNAL_INTERRUPT
+ 'EICRA' : '$6a', # External Interrupt Control Reg
+ 'EICRA_ISC3': '$c0', # External Interrupt Sense Contr
+ 'EICRA_ISC2': '$30', # External Interrupt Sense Contr
+ 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
+ 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
+ 'EICRB' : '$5a', # External Interrupt Control Reg
+ 'EICRB_ISC7': '$c0', # External Interrupt 7-4 Sense C
+ 'EICRB_ISC6': '$30', # External Interrupt 7-4 Sense C
+ 'EICRB_ISC5': '$c', # External Interrupt 7-4 Sense C
+ 'EICRB_ISC4': '$3', # External Interrupt 7-4 Sense C
+ 'EIMSK' : '$59', # External Interrupt Mask Regist
+ 'EIMSK_INT': '$ff', # External Interrupt Request 7 E
+ 'EIFR' : '$58', # External Interrupt Flag Regist
+ 'EIFR_INTF': '$ff', # External Interrupt Flags
+
+# Module EEPROM
+ 'EEAR' : '$3e', # EEPROM Read/Write Access Byte
+ 'EEDR' : '$3d', # EEPROM Data Register
+ 'EECR' : '$3c', # EEPROM Control Register
+ 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
+ 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
+ 'EECR_EEWE': '$2', # EEPROM Write Enable
+ 'EECR_EERE': '$1', # EEPROM Read Enable
+
+# Module PORTA
+ 'PORTA' : '$3b', # Port A Data Register
+ 'DDRA' : '$3a', # Port A Data Direction Register
+ 'PINA' : '$39', # Port A Input Pins
+
+# Module PORTB
+ 'PORTB' : '$38', # Port B Data Register
+ 'DDRB' : '$37', # Port B Data Direction Register
+ 'PINB' : '$36', # Port B Input Pins
+
+# Module PORTC
+ 'PORTC' : '$35', # Port C Data Register
+ 'DDRC' : '$34', # Port C Data Direction Register
+ 'PINC' : '$33', # Port C Input Pins
+
+# Module PORTD
+ 'PORTD' : '$32', # Port D Data Register
+ 'DDRD' : '$31', # Port D Data Direction Register
+ 'PIND' : '$30', # Port D Input Pins
+
+# Module PORTE
+ 'PORTE' : '$23', # Data Register, Port E
+ 'DDRE' : '$22', # Data Direction Register, Port
+ 'PINE' : '$21', # Input Pins, Port E
+
+# Module PORTF
+ 'PORTF' : '$62', # Data Register, Port F
+ 'DDRF' : '$61', # Data Direction Register, Port
+ 'PINF' : '$20', # Input Pins, Port F
+
+# Module PORTG
+ 'PORTG' : '$65', # Data Register, Port G
+ 'DDRG' : '$64', # Data Direction Register, Port
+ 'PING' : '$63', # Input Pins, Port G
+
+# Module TIMER_COUNTER_0
+ 'TCCR0' : '$53', # Timer/Counter Control Register
+ 'TCCR0_FOC0': '$80', # Force Output Compare
+ 'TCCR0_WGM00': '$40', # Waveform Generation Mode 0
+ 'TCCR0_COM0': '$30', # Compare Match Output Modes
+ 'TCCR0_WGM01': '$8', # Waveform Generation Mode 1
+ 'TCCR0_CS0': '$7', # Clock Selects
+ 'TCNT0' : '$52', # Timer/Counter Register
+ 'OCR0' : '$51', # Output Compare Register
+ 'ASSR' : '$50', # Asynchronus Status Register
+ 'ASSR_AS0': '$8', # Asynchronus Timer/Counter 0
+ 'ASSR_TCN0UB': '$4', # Timer/Counter0 Update Busy
+ 'ASSR_OCR0UB': '$2', # Output Compare register 0 Busy
+ 'ASSR_TCR0UB': '$1', # Timer/Counter Control Register
+ 'TIMSK' : '$57', # Timer/Counter Interrupt Mask R
+ 'TIMSK_OCIE0': '$2', # Timer/Counter0 Output Compare
+ 'TIMSK_TOIE0': '$1', # Timer/Counter0 Overflow Interr
+ 'TIFR' : '$56', # Timer/Counter Interrupt Flag r
+ 'TIFR_OCF0': '$2', # Output Compare Flag 0
+ 'TIFR_TOV0': '$1', # Timer/Counter0 Overflow Flag
+ 'SFIOR' : '$40', # Special Function IO Register
+ 'SFIOR_TSM': '$80', # Timer/Counter Synchronization
+ 'SFIOR_PSR0': '$2', # Prescaler Reset Timer/Counter0
+
+# Module TIMER_COUNTER_1
+ 'TIMSK' : '$57', # Timer/Counter Interrupt Mask R
+ 'TIMSK_TICIE1': '$20', # Timer/Counter1 Input Capture I
+ 'TIMSK_OCIE1A': '$10', # Timer/Counter1 Output CompareA
+ 'TIMSK_OCIE1B': '$8', # Timer/Counter1 Output CompareB
+ 'TIMSK_TOIE1': '$4', # Timer/Counter1 Overflow Interr
+ 'ETIMSK' : '$7d', # Extended Timer/Counter Interru
+ 'ETIMSK_OCIE1C': '$1', # Timer/Counter 1, Output Compar
+ 'TIFR' : '$56', # Timer/Counter Interrupt Flag r
+ 'TIFR_ICF1': '$20', # Input Capture Flag 1
+ 'TIFR_OCF1A': '$10', # Output Compare Flag 1A
+ 'TIFR_OCF1B': '$8', # Output Compare Flag 1B
+ 'TIFR_TOV1': '$4', # Timer/Counter1 Overflow Flag
+ 'ETIFR' : '$7c', # Extended Timer/Counter Interru
+ 'ETIFR_OCF1C': '$1', # Timer/Counter 1, Output Compar
+ 'SFIOR' : '$40', # Special Function IO Register
+ 'SFIOR_TSM': '$80', # Timer/Counter Synchronization
+ 'SFIOR_PSR321': '$1', # Prescaler Reset, T/C3, T/C2, T
+ 'TCCR1A' : '$4f', # Timer/Counter1 Control Registe
+ 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
+ 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
+ 'TCCR1A_COM1C': '$c', # Compare Output Mode 1C, bits
+ 'TCCR1A_WGM1': '$3', # Waveform Generation Mode Bits
+ 'TCCR1B' : '$4e', # Timer/Counter1 Control Registe
+ 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
+ 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
+ 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
+ 'TCCR1B_CS1': '$7', # Clock Select1 bits
+ 'TCCR1C' : '$7a', # Timer/Counter1 Control Registe
+ 'TCCR1C_FOC1A': '$80', # Force Output Compare for chann
+ 'TCCR1C_FOC1B': '$40', # Force Output Compare for chann
+ 'TCCR1C_FOC1C': '$20', # Force Output Compare for chann
+ 'TCNT1' : '$4c', # Timer/Counter1 Bytes
+ 'OCR1A' : '$4a', # Timer/Counter1 Output Compare
+ 'OCR1B' : '$48', # Timer/Counter1 Output Compare
+ 'OCR1C' : '$78', # Timer/Counter1 Output Compare
+ 'ICR1' : '$46', # Timer/Counter1 Input Capture R
+
+# Module TIMER_COUNTER_2
+ 'TCCR2' : '$45', # Timer/Counter Control Register
+ 'TCCR2_FOC2': '$80', # Force Output Compare
+ 'TCCR2_WGM20': '$40', # Wafeform Generation Mode
+ 'TCCR2_COM2': '$30', # Compare Match Output Mode
+ 'TCCR2_WGM21': '$8', # Waveform Generation Mode
+ 'TCCR2_CS2': '$7', # Clock Select
+ 'TCNT2' : '$44', # Timer/Counter Register
+ 'OCR2' : '$43', # Output Compare Register
+ 'TIFR' : '$56', # Timer/Counter Interrupt Flag R
+ 'TIFR_OCF2': '$80', # Output Compare Flag 2
+ 'TIFR_TOV2': '$40', # Timer/Counter2 Overflow Flag
+ 'TIMSK' : '$57', #
+ 'TIMSK_OCIE2': '$80', #
+ 'TIMSK_TOIE2': '$40', #
+
+# Module TIMER_COUNTER_3
+ 'ETIMSK' : '$7d', # Extended Timer/Counter Interru
+ 'ETIMSK_TICIE3': '$20', # Timer/Counter3 Input Capture I
+ 'ETIMSK_OCIE3A': '$10', # Timer/Counter3 Output CompareA
+ 'ETIMSK_OCIE3B': '$8', # Timer/Counter3 Output CompareB
+ 'ETIMSK_TOIE3': '$4', # Timer/Counter3 Overflow Interr
+ 'ETIMSK_OCIE3C': '$2', # Timer/Counter3, Output Compare
+ 'ETIFR' : '$7c', # Extended Timer/Counter Interru
+ 'ETIFR_ICF3': '$20', # Input Capture Flag 1
+ 'ETIFR_OCF3A': '$10', # Output Compare Flag 1A
+ 'ETIFR_OCF3B': '$8', # Output Compare Flag 1B
+ 'ETIFR_TOV3': '$4', # Timer/Counter3 Overflow Flag
+ 'ETIFR_OCF3C': '$2', # Timer/Counter3 Output Compare
+ 'SFIOR' : '$40', # Special Function IO Register
+ 'SFIOR_TSM': '$80', # Timer/Counter Synchronization
+ 'SFIOR_PSR321': '$1', # Prescaler Reset, T/C3, T/C2, T
+ 'TCCR3A' : '$8b', # Timer/Counter3 Control Registe
+ 'TCCR3A_COM3A': '$c0', # Compare Output Mode 3A, bits
+ 'TCCR3A_COM3B': '$30', # Compare Output Mode 3B, bits
+ 'TCCR3A_COM3C': '$c', # Compare Output Mode 3C, bits
+ 'TCCR3A_WGM3': '$3', # Waveform Generation Mode Bits
+ 'TCCR3B' : '$8a', # Timer/Counter3 Control Registe
+ 'TCCR3B_ICNC3': '$80', # Input Capture 3 Noise Cancele
+ 'TCCR3B_ICES3': '$40', # Input Capture 3 Edge Select
+ 'TCCR3B_WGM3': '$18', # Waveform Generation Mode
+ 'TCCR3B_CS3': '$7', # Clock Select3 bits
+ 'TCCR3C' : '$8c', # Timer/Counter3 Control Registe
+ 'TCCR3C_FOC3A': '$80', # Force Output Compare for chann
+ 'TCCR3C_FOC3B': '$40', # Force Output Compare for chann
+ 'TCCR3C_FOC3C': '$20', # Force Output Compare for chann
+ 'TCNT3' : '$88', # Timer/Counter3 Bytes
+ 'OCR3A' : '$86', # Timer/Counter3 Output Compare
+ 'OCR3B' : '$84', # Timer/Counter3 Output Compare
+ 'OCR3C' : '$82', # Timer/Counter3 Output compare
+ 'ICR3' : '$80', # Timer/Counter3 Input Capture R
+
+# Module WATCHDOG
+ 'WDTCR' : '$41', # Watchdog Timer Control Registe
+ 'WDTCR_WDCE': '$10', # Watchdog Change Enable
+ 'WDTCR_WDE': '$8', # Watch Dog Enable
+ 'WDTCR_WDP': '$7', # Watch Dog Timer Prescaler bits
+
+ '__amforth_dummy':'0'
+}
diff --git a/amforth-6.5/avr8/devices/atmega64/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega64/words/no-jtag.asm
new file mode 100644
index 0000000..352a4bb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega64/words/no-jtag.asm
@@ -0,0 +1,14 @@
+; ( -- )
+; ( -- )
+; MCU
+; disable jtag at runtime
+VE_NOJTAG:
+ .dw $FF05
+ .db "-jtag",0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOJTAG
+XT_NOJTAG:
+ .dw PFA_NOJTAG
+PFA_NOJTAG:
+
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega64/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega64/words/no-wdt.asm
new file mode 100644
index 0000000..4a12261
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega64/words/no-wdt.asm
@@ -0,0 +1,22 @@
+; ( -- )
+; MCU
+; disable watch dog timer at runtime
+VE_NOWDT:
+ .dw $ff04
+ .db "-wdt"
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOWDT
+XT_NOWDT:
+ .dw PFA_NOWDT
+PFA_NOWDT:
+
+; Reset WDT
+ wdr
+; Write logical one to WDTOE and WDE
+ in_ temp1, WDTCR
+ ori temp1, (1<<WDTOE)|(1<<WDE)
+ out WDTCR, temp1
+; Turn off WDT
+ ldi temp1, (0<<WDE)
+ out_ WDTCR, temp1
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega64/words/sleep.asm b/amforth-6.5/avr8/devices/atmega64/words/sleep.asm
new file mode 100644
index 0000000..778fa32
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega64/words/sleep.asm
@@ -0,0 +1,24 @@
+; ( mode -- )
+; MCU
+; put the controller into the specified sleep mode
+VE_SLEEP:
+ .dw $ff05
+ .db "sleep", 0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_SLEEP
+XT_SLEEP:
+ .dw PFA_SLEEP
+PFA_SLEEP:
+ andi tosl, 7 ; leave only legal mode bits
+ swap tosl ; move to correct location (bits 6-4, atmega32)
+ ori tosl, $80 ; set the SE bit (atmega32: bit 7, not bit 0)
+ out_ MCUCR, tosl ; set the sleep config (atmega32: MCUCR not SMCR)
+ sleep ; nighty-night
+;; the 4 lower bits of MCUCR should not be touched
+ in_ tosl, MCUCR
+ andi tosl, $0F
+ out_ MCUCR, tosl
+ ;clr tosl ; need to clean up the SMCR reg before we leave
+ ;out SMCR, tosl ; 0 protects against accidental sleeps
+ loadtos ; pop argument from stack
+ jmp DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega640/atmega640.frt b/amforth-6.5/avr8/devices/atmega640/atmega640.frt
new file mode 100644
index 0000000..2432b5b
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega640/atmega640.frt
@@ -0,0 +1,579 @@
+\ Partname: ATmega640
+\ generated automatically
+
+\ ANALOG_COMPARATOR
+&123 constant ADCSRB \ ADC Control and Status Register B
+ $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer Enable
+&80 constant ACSR \ Analog Comparator Control And Status Register
+ $80 constant ACSR_ACD \ Analog Comparator Disable
+ $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
+ $20 constant ACSR_ACO \ Analog Compare Output
+ $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
+ $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
+ $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
+ $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
+&127 constant DIDR1 \ Digital Input Disable Register 1
+ $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
+ $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
+\ USART0
+&198 constant UDR0 \ USART I/O Data Register
+&192 constant UCSR0A \ USART Control and Status Register A
+ $80 constant UCSR0A_RXC0 \ USART Receive Complete
+ $40 constant UCSR0A_TXC0 \ USART Transmitt Complete
+ $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
+ $10 constant UCSR0A_FE0 \ Framing Error
+ $08 constant UCSR0A_DOR0 \ Data overRun
+ $04 constant UCSR0A_UPE0 \ Parity Error
+ $02 constant UCSR0A_U2X0 \ Double the USART transmission speed
+ $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
+&193 constant UCSR0B \ USART Control and Status Register B
+ $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
+ $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
+ $20 constant UCSR0B_UDRIE0 \ USART Data register Empty Interrupt Enable
+ $10 constant UCSR0B_RXEN0 \ Receiver Enable
+ $08 constant UCSR0B_TXEN0 \ Transmitter Enable
+ $04 constant UCSR0B_UCSZ02 \ Character Size
+ $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
+ $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
+&194 constant UCSR0C \ USART Control and Status Register C
+ $C0 constant UCSR0C_UMSEL0 \ USART Mode Select
+ $30 constant UCSR0C_UPM0 \ Parity Mode Bits
+ $08 constant UCSR0C_USBS0 \ Stop Bit Select
+ $06 constant UCSR0C_UCSZ0 \ Character Size
+ $01 constant UCSR0C_UCPOL0 \ Clock Polarity
+&196 constant UBRR0 \ USART Baud Rate Register Bytes
+\ TWI
+&189 constant TWAMR \ TWI (Slave) Address Mask Register
+ $FE constant TWAMR_TWAM \
+&184 constant TWBR \ TWI Bit Rate register
+&188 constant TWCR \ TWI Control Register
+ $80 constant TWCR_TWINT \ TWI Interrupt Flag
+ $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
+ $20 constant TWCR_TWSTA \ TWI Start Condition Bit
+ $10 constant TWCR_TWSTO \ TWI Stop Condition Bit
+ $08 constant TWCR_TWWC \ TWI Write Collition Flag
+ $04 constant TWCR_TWEN \ TWI Enable Bit
+ $01 constant TWCR_TWIE \ TWI Interrupt Enable
+&185 constant TWSR \ TWI Status Register
+ $F8 constant TWSR_TWS \ TWI Status
+ $03 constant TWSR_TWPS \ TWI Prescaler
+&187 constant TWDR \ TWI Data register
+&186 constant TWAR \ TWI (Slave) Address register
+ $FE constant TWAR_TWA \ TWI (Slave) Address register Bits
+ $01 constant TWAR_TWGCE \ TWI General Call Recognition Enable Bit
+\ SPI
+&76 constant SPCR \ SPI Control Register
+ $80 constant SPCR_SPIE \ SPI Interrupt Enable
+ $40 constant SPCR_SPE \ SPI Enable
+ $20 constant SPCR_DORD \ Data Order
+ $10 constant SPCR_MSTR \ Master/Slave Select
+ $08 constant SPCR_CPOL \ Clock polarity
+ $04 constant SPCR_CPHA \ Clock Phase
+ $03 constant SPCR_SPR \ SPI Clock Rate Selects
+&77 constant SPSR \ SPI Status Register
+ $80 constant SPSR_SPIF \ SPI Interrupt Flag
+ $40 constant SPSR_WCOL \ Write Collision Flag
+ $01 constant SPSR_SPI2X \ Double SPI Speed Bit
+&78 constant SPDR \ SPI Data Register
+\ PORTA
+&34 constant PORTA \ Port A Data Register
+&33 constant DDRA \ Port A Data Direction Register
+&32 constant PINA \ Port A Input Pins
+\ PORTB
+&37 constant PORTB \ Port B Data Register
+&36 constant DDRB \ Port B Data Direction Register
+&35 constant PINB \ Port B Input Pins
+\ PORTC
+&40 constant PORTC \ Port C Data Register
+&39 constant DDRC \ Port C Data Direction Register
+&38 constant PINC \ Port C Input Pins
+\ PORTD
+&43 constant PORTD \ Port D Data Register
+&42 constant DDRD \ Port D Data Direction Register
+&41 constant PIND \ Port D Input Pins
+\ PORTE
+&46 constant PORTE \ Data Register, Port E
+&45 constant DDRE \ Data Direction Register, Port E
+&44 constant PINE \ Input Pins, Port E
+\ PORTF
+&49 constant PORTF \ Data Register, Port F
+&48 constant DDRF \ Data Direction Register, Port F
+&47 constant PINF \ Input Pins, Port F
+\ PORTG
+&52 constant PORTG \ Data Register, Port G
+&51 constant DDRG \ Data Direction Register, Port G
+&50 constant PING \ Input Pins, Port G
+\ PORTH
+&258 constant PORTH \ PORT H Data Register
+&257 constant DDRH \ PORT H Data Direction Register
+&256 constant PINH \ PORT H Input Pins
+\ PORTJ
+&261 constant PORTJ \ PORT J Data Register
+&260 constant DDRJ \ PORT J Data Direction Register
+&259 constant PINJ \ PORT J Input Pins
+\ PORTK
+&264 constant PORTK \ PORT K Data Register
+&263 constant DDRK \ PORT K Data Direction Register
+&262 constant PINK \ PORT K Input Pins
+\ PORTL
+&267 constant PORTL \ PORT L Data Register
+&266 constant DDRL \ PORT L Data Direction Register
+&265 constant PINL \ PORT L Input Pins
+\ TIMER_COUNTER_0
+&72 constant OCR0B \ Timer/Counter0 Output Compare Register
+&71 constant OCR0A \ Timer/Counter0 Output Compare Register
+&70 constant TCNT0 \ Timer/Counter0
+&69 constant TCCR0B \ Timer/Counter Control Register B
+ $80 constant TCCR0B_FOC0A \ Force Output Compare A
+ $40 constant TCCR0B_FOC0B \ Force Output Compare B
+ $08 constant TCCR0B_WGM02 \
+ $07 constant TCCR0B_CS0 \ Clock Select
+&68 constant TCCR0A \ Timer/Counter Control Register A
+ $C0 constant TCCR0A_COM0A \ Compare Output Mode, Phase Correct PWM Mode
+ $30 constant TCCR0A_COM0B \ Compare Output Mode, Fast PWm
+ $03 constant TCCR0A_WGM0 \ Waveform Generation Mode
+&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
+ $04 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare Match B Interrupt Enable
+ $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match A Interrupt Enable
+ $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
+&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
+ $04 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare Flag 0B
+ $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0A
+ $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
+&67 constant GTCCR \ General Timer/Counter Control Register
+ $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
+ $01 constant GTCCR_PSRSYNC \ Prescaler Reset Timer/Counter1 and Timer/Counter0
+\ TIMER_COUNTER_2
+&112 constant TIMSK2 \ Timer/Counter Interrupt Mask register
+ $04 constant TIMSK2_OCIE2B \ Timer/Counter2 Output Compare Match B Interrupt Enable
+ $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match A Interrupt Enable
+ $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
+&55 constant TIFR2 \ Timer/Counter Interrupt Flag Register
+ $04 constant TIFR2_OCF2B \ Output Compare Flag 2B
+ $02 constant TIFR2_OCF2A \ Output Compare Flag 2A
+ $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
+&176 constant TCCR2A \ Timer/Counter2 Control Register A
+ $C0 constant TCCR2A_COM2A \ Compare Output Mode bits
+ $30 constant TCCR2A_COM2B \ Compare Output Mode bits
+ $03 constant TCCR2A_WGM2 \ Waveform Genration Mode
+&177 constant TCCR2B \ Timer/Counter2 Control Register B
+ $80 constant TCCR2B_FOC2A \ Force Output Compare A
+ $40 constant TCCR2B_FOC2B \ Force Output Compare B
+ $08 constant TCCR2B_WGM22 \ Waveform Generation Mode
+ $07 constant TCCR2B_CS2 \ Clock Select bits
+&178 constant TCNT2 \ Timer/Counter2
+&180 constant OCR2B \ Timer/Counter2 Output Compare Register B
+&179 constant OCR2A \ Timer/Counter2 Output Compare Register A
+&182 constant ASSR \ Asynchronous Status Register
+ $40 constant ASSR_EXCLK \ Enable External Clock Input
+ $20 constant ASSR_AS2 \ Asynchronous Timer/Counter2
+ $10 constant ASSR_TCN2UB \ Timer/Counter2 Update Busy
+ $08 constant ASSR_OCR2AUB \ Output Compare Register2 Update Busy
+ $04 constant ASSR_OCR2BUB \ Output Compare Register 2 Update Busy
+ $02 constant ASSR_TCR2AUB \ Timer/Counter Control Register2 Update Busy
+ $01 constant ASSR_TCR2BUB \ Timer/Counter Control Register2 Update Busy
+\ WATCHDOG
+&96 constant WDTCSR \ Watchdog Timer Control Register
+ $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Flag
+ $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Enable
+ $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
+ $10 constant WDTCSR_WDCE \ Watchdog Change Enable
+ $08 constant WDTCSR_WDE \ Watch Dog Enable
+\ USART1
+&206 constant UDR1 \ USART I/O Data Register
+&200 constant UCSR1A \ USART Control and Status Register A
+ $80 constant UCSR1A_RXC1 \ USART Receive Complete
+ $40 constant UCSR1A_TXC1 \ USART Transmitt Complete
+ $20 constant UCSR1A_UDRE1 \ USART Data Register Empty
+ $10 constant UCSR1A_FE1 \ Framing Error
+ $08 constant UCSR1A_DOR1 \ Data overRun
+ $04 constant UCSR1A_UPE1 \ Parity Error
+ $02 constant UCSR1A_U2X1 \ Double the USART transmission speed
+ $01 constant UCSR1A_MPCM1 \ Multi-processor Communication Mode
+&201 constant UCSR1B \ USART Control and Status Register B
+ $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable
+ $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable
+ $20 constant UCSR1B_UDRIE1 \ USART Data register Empty Interrupt Enable
+ $10 constant UCSR1B_RXEN1 \ Receiver Enable
+ $08 constant UCSR1B_TXEN1 \ Transmitter Enable
+ $04 constant UCSR1B_UCSZ12 \ Character Size
+ $02 constant UCSR1B_RXB81 \ Receive Data Bit 8
+ $01 constant UCSR1B_TXB81 \ Transmit Data Bit 8
+&202 constant UCSR1C \ USART Control and Status Register C
+ $C0 constant UCSR1C_UMSEL1 \ USART Mode Select
+ $30 constant UCSR1C_UPM1 \ Parity Mode Bits
+ $08 constant UCSR1C_USBS1 \ Stop Bit Select
+ $06 constant UCSR1C_UCSZ1 \ Character Size
+ $01 constant UCSR1C_UCPOL1 \ Clock Polarity
+&204 constant UBRR1 \ USART Baud Rate Register Bytes
+\ EEPROM
+&65 constant EEAR \ EEPROM Address Register Low Bytes
+&64 constant EEDR \ EEPROM Data Register
+&63 constant EECR \ EEPROM Control Register
+ $30 constant EECR_EEPM \ EEPROM Programming Mode Bits
+ $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
+ $04 constant EECR_EEMPE \ EEPROM Master Write Enable
+ $02 constant EECR_EEPE \ EEPROM Write Enable
+ $01 constant EECR_EERE \ EEPROM Read Enable
+\ TIMER_COUNTER_5
+&288 constant TCCR5A \ Timer/Counter5 Control Register A
+ $C0 constant TCCR5A_COM5A \ Compare Output Mode 1A, bits
+ $30 constant TCCR5A_COM5B \ Compare Output Mode 5B, bits
+ $0C constant TCCR5A_COM5C \ Compare Output Mode 5C, bits
+ $03 constant TCCR5A_WGM5 \ Waveform Generation Mode
+&289 constant TCCR5B \ Timer/Counter5 Control Register B
+ $80 constant TCCR5B_ICNC5 \ Input Capture 5 Noise Canceler
+ $40 constant TCCR5B_ICES5 \ Input Capture 5 Edge Select
+ $18 constant TCCR5B_WGM5 \ Waveform Generation Mode
+ $07 constant TCCR5B_CS5 \ Prescaler source of Timer/Counter 5
+&290 constant TCCR5C \ Timer/Counter 5 Control Register C
+ $80 constant TCCR5C_FOC5A \ Force Output Compare 5A
+ $40 constant TCCR5C_FOC5B \ Force Output Compare 5B
+ $20 constant TCCR5C_FOC5C \ Force Output Compare 5C
+&292 constant TCNT5 \ Timer/Counter5 Bytes
+&296 constant OCR5A \ Timer/Counter5 Output Compare Register A Bytes
+&298 constant OCR5B \ Timer/Counter5 Output Compare Register B Bytes
+&300 constant OCR5C \ Timer/Counter5 Output Compare Register B Bytes
+&294 constant ICR5 \ Timer/Counter5 Input Capture Register Bytes
+&115 constant TIMSK5 \ Timer/Counter5 Interrupt Mask Register
+ $20 constant TIMSK5_ICIE5 \ Timer/Counter5 Input Capture Interrupt Enable
+ $08 constant TIMSK5_OCIE5C \ Timer/Counter5 Output Compare C Match Interrupt Enable
+ $04 constant TIMSK5_OCIE5B \ Timer/Counter5 Output Compare B Match Interrupt Enable
+ $02 constant TIMSK5_OCIE5A \ Timer/Counter5 Output Compare A Match Interrupt Enable
+ $01 constant TIMSK5_TOIE5 \ Timer/Counter5 Overflow Interrupt Enable
+&58 constant TIFR5 \ Timer/Counter5 Interrupt Flag register
+ $20 constant TIFR5_ICF5 \ Input Capture Flag 5
+ $08 constant TIFR5_OCF5C \ Output Compare Flag 5C
+ $04 constant TIFR5_OCF5B \ Output Compare Flag 5B
+ $02 constant TIFR5_OCF5A \ Output Compare Flag 5A
+ $01 constant TIFR5_TOV5 \ Timer/Counter5 Overflow Flag
+\ TIMER_COUNTER_4
+&160 constant TCCR4A \ Timer/Counter4 Control Register A
+ $C0 constant TCCR4A_COM4A \ Compare Output Mode 1A, bits
+ $30 constant TCCR4A_COM4B \ Compare Output Mode 4B, bits
+ $0C constant TCCR4A_COM4C \ Compare Output Mode 4C, bits
+ $03 constant TCCR4A_WGM4 \ Waveform Generation Mode
+&161 constant TCCR4B \ Timer/Counter4 Control Register B
+ $80 constant TCCR4B_ICNC4 \ Input Capture 4 Noise Canceler
+ $40 constant TCCR4B_ICES4 \ Input Capture 4 Edge Select
+ $18 constant TCCR4B_WGM4 \ Waveform Generation Mode
+ $07 constant TCCR4B_CS4 \ Prescaler source of Timer/Counter 4
+&162 constant TCCR4C \ Timer/Counter 4 Control Register C
+ $80 constant TCCR4C_FOC4A \ Force Output Compare 4A
+ $40 constant TCCR4C_FOC4B \ Force Output Compare 4B
+ $20 constant TCCR4C_FOC4C \ Force Output Compare 4C
+&164 constant TCNT4 \ Timer/Counter4 Bytes
+&168 constant OCR4A \ Timer/Counter4 Output Compare Register A Bytes
+&170 constant OCR4B \ Timer/Counter4 Output Compare Register B Bytes
+&172 constant OCR4C \ Timer/Counter4 Output Compare Register B Bytes
+&166 constant ICR4 \ Timer/Counter4 Input Capture Register Bytes
+&114 constant TIMSK4 \ Timer/Counter4 Interrupt Mask Register
+ $20 constant TIMSK4_ICIE4 \ Timer/Counter4 Input Capture Interrupt Enable
+ $08 constant TIMSK4_OCIE4C \ Timer/Counter4 Output Compare C Match Interrupt Enable
+ $04 constant TIMSK4_OCIE4B \ Timer/Counter4 Output Compare B Match Interrupt Enable
+ $02 constant TIMSK4_OCIE4A \ Timer/Counter4 Output Compare A Match Interrupt Enable
+ $01 constant TIMSK4_TOIE4 \ Timer/Counter4 Overflow Interrupt Enable
+&57 constant TIFR4 \ Timer/Counter4 Interrupt Flag register
+ $20 constant TIFR4_ICF4 \ Input Capture Flag 4
+ $08 constant TIFR4_OCF4C \ Output Compare Flag 4C
+ $04 constant TIFR4_OCF4B \ Output Compare Flag 4B
+ $02 constant TIFR4_OCF4A \ Output Compare Flag 4A
+ $01 constant TIFR4_TOV4 \ Timer/Counter4 Overflow Flag
+\ TIMER_COUNTER_3
+&144 constant TCCR3A \ Timer/Counter3 Control Register A
+ $C0 constant TCCR3A_COM3A \ Compare Output Mode 1A, bits
+ $30 constant TCCR3A_COM3B \ Compare Output Mode 3B, bits
+ $0C constant TCCR3A_COM3C \ Compare Output Mode 3C, bits
+ $03 constant TCCR3A_WGM3 \ Waveform Generation Mode
+&145 constant TCCR3B \ Timer/Counter3 Control Register B
+ $80 constant TCCR3B_ICNC3 \ Input Capture 3 Noise Canceler
+ $40 constant TCCR3B_ICES3 \ Input Capture 3 Edge Select
+ $18 constant TCCR3B_WGM3 \ Waveform Generation Mode
+ $07 constant TCCR3B_CS3 \ Prescaler source of Timer/Counter 3
+&146 constant TCCR3C \ Timer/Counter 3 Control Register C
+ $80 constant TCCR3C_FOC3A \ Force Output Compare 3A
+ $40 constant TCCR3C_FOC3B \ Force Output Compare 3B
+ $20 constant TCCR3C_FOC3C \ Force Output Compare 3C
+&148 constant TCNT3 \ Timer/Counter3 Bytes
+&152 constant OCR3A \ Timer/Counter3 Output Compare Register A Bytes
+&154 constant OCR3B \ Timer/Counter3 Output Compare Register B Bytes
+&156 constant OCR3C \ Timer/Counter3 Output Compare Register B Bytes
+&150 constant ICR3 \ Timer/Counter3 Input Capture Register Bytes
+&113 constant TIMSK3 \ Timer/Counter3 Interrupt Mask Register
+ $20 constant TIMSK3_ICIE3 \ Timer/Counter3 Input Capture Interrupt Enable
+ $08 constant TIMSK3_OCIE3C \ Timer/Counter3 Output Compare C Match Interrupt Enable
+ $04 constant TIMSK3_OCIE3B \ Timer/Counter3 Output Compare B Match Interrupt Enable
+ $02 constant TIMSK3_OCIE3A \ Timer/Counter3 Output Compare A Match Interrupt Enable
+ $01 constant TIMSK3_TOIE3 \ Timer/Counter3 Overflow Interrupt Enable
+&56 constant TIFR3 \ Timer/Counter3 Interrupt Flag register
+ $20 constant TIFR3_ICF3 \ Input Capture Flag 3
+ $08 constant TIFR3_OCF3C \ Output Compare Flag 3C
+ $04 constant TIFR3_OCF3B \ Output Compare Flag 3B
+ $02 constant TIFR3_OCF3A \ Output Compare Flag 3A
+ $01 constant TIFR3_TOV3 \ Timer/Counter3 Overflow Flag
+\ TIMER_COUNTER_1
+&128 constant TCCR1A \ Timer/Counter1 Control Register A
+ $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
+ $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
+ $0C constant TCCR1A_COM1C \ Compare Output Mode 1C, bits
+ $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
+&129 constant TCCR1B \ Timer/Counter1 Control Register B
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
+ $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
+&130 constant TCCR1C \ Timer/Counter 1 Control Register C
+ $80 constant TCCR1C_FOC1A \ Force Output Compare 1A
+ $40 constant TCCR1C_FOC1B \ Force Output Compare 1B
+ $20 constant TCCR1C_FOC1C \ Force Output Compare 1C
+&132 constant TCNT1 \ Timer/Counter1 Bytes
+&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
+&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
+&140 constant OCR1C \ Timer/Counter1 Output Compare Register C Bytes
+&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
+&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
+ $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
+ $08 constant TIMSK1_OCIE1C \ Timer/Counter1 Output Compare C Match Interrupt Enable
+ $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
+ $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
+ $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
+&54 constant TIFR1 \ Timer/Counter1 Interrupt Flag register
+ $20 constant TIFR1_ICF1 \ Input Capture Flag 1
+ $08 constant TIFR1_OCF1C \ Output Compare Flag 1C
+ $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
+ $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
+ $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
+\ JTAG
+&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
+&85 constant MCUCR \ MCU Control Register
+ $80 constant MCUCR_JTD \ JTAG Interface Disable
+&84 constant MCUSR \ MCU Status Register
+ $10 constant MCUSR_JTRF \ JTAG Reset Flag
+\ EXTERNAL_INTERRUPT
+&105 constant EICRA \ External Interrupt Control Register A
+ $C0 constant EICRA_ISC3 \ External Interrupt Sense Control Bit
+ $30 constant EICRA_ISC2 \ External Interrupt Sense Control Bit
+ $0C constant EICRA_ISC1 \ External Interrupt Sense Control Bit
+ $03 constant EICRA_ISC0 \ External Interrupt Sense Control Bit
+&106 constant EICRB \ External Interrupt Control Register B
+ $C0 constant EICRB_ISC7 \ External Interrupt 7-4 Sense Control Bit
+ $30 constant EICRB_ISC6 \ External Interrupt 7-4 Sense Control Bit
+ $0C constant EICRB_ISC5 \ External Interrupt 7-4 Sense Control Bit
+ $03 constant EICRB_ISC4 \ External Interrupt 7-4 Sense Control Bit
+&61 constant EIMSK \ External Interrupt Mask Register
+ $FF constant EIMSK_INT \ External Interrupt Request 7 Enable
+&60 constant EIFR \ External Interrupt Flag Register
+ $FF constant EIFR_INTF \ External Interrupt Flags
+&109 constant PCMSK2 \ Pin Change Mask Register 2
+&108 constant PCMSK1 \ Pin Change Mask Register 1
+&107 constant PCMSK0 \ Pin Change Mask Register 0
+&59 constant PCIFR \ Pin Change Interrupt Flag Register
+ $07 constant PCIFR_PCIF \ Pin Change Interrupt Flags
+&104 constant PCICR \ Pin Change Interrupt Control Register
+ $07 constant PCICR_PCIE \ Pin Change Interrupt Enables
+\ CPU
+&95 constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ $08 constant SREG_V \ Two's Complement Overflow Flag
+ $04 constant SREG_N \ Negative Flag
+ $02 constant SREG_Z \ Zero Flag
+ $01 constant SREG_C \ Carry Flag
+&93 constant SP \ Stack Pointer
+&116 constant XMCRA \ External Memory Control Register A
+ $80 constant XMCRA_SRE \ External SRAM Enable
+ $70 constant XMCRA_SRL \ Wait state page limit
+ $0C constant XMCRA_SRW1 \ Wait state select bit upper page
+ $03 constant XMCRA_SRW0 \ Wait state select bit lower page
+&117 constant XMCRB \ External Memory Control Register B
+ $80 constant XMCRB_XMBK \ External Memory Bus Keeper Enable
+ $07 constant XMCRB_XMM \ External Memory High Mask
+&102 constant OSCCAL \ Oscillator Calibration Value
+&97 constant CLKPR \
+ $80 constant CLKPR_CLKPCE \
+ $0F constant CLKPR_CLKPS \
+&83 constant SMCR \ Sleep Mode Control Register
+ $0E constant SMCR_SM \ Sleep Mode Select bits
+ $01 constant SMCR_SE \ Sleep Enable
+&92 constant EIND \ Extended Indirect Register
+&75 constant GPIOR2 \ General Purpose IO Register 2
+ $FF constant GPIOR2_GPIOR \ General Purpose IO Register 2 bis
+&74 constant GPIOR1 \ General Purpose IO Register 1
+ $FF constant GPIOR1_GPIOR \ General Purpose IO Register 1 bis
+&62 constant GPIOR0 \ General Purpose IO Register 0
+ $80 constant GPIOR0_GPIOR07 \ General Purpose IO Register 0 bit 7
+ $40 constant GPIOR0_GPIOR06 \ General Purpose IO Register 0 bit 6
+ $20 constant GPIOR0_GPIOR05 \ General Purpose IO Register 0 bit 5
+ $10 constant GPIOR0_GPIOR04 \ General Purpose IO Register 0 bit 4
+ $08 constant GPIOR0_GPIOR03 \ General Purpose IO Register 0 bit 3
+ $04 constant GPIOR0_GPIOR02 \ General Purpose IO Register 0 bit 2
+ $02 constant GPIOR0_GPIOR01 \ General Purpose IO Register 0 bit 1
+ $01 constant GPIOR0_GPIOR00 \ General Purpose IO Register 0 bit 0
+&101 constant PRR1 \ Power Reduction Register1
+ $20 constant PRR1_PRTIM5 \ Power Reduction Timer/Counter5
+ $10 constant PRR1_PRTIM4 \ Power Reduction Timer/Counter4
+ $08 constant PRR1_PRTIM3 \ Power Reduction Timer/Counter3
+ $07 constant PRR1_PRUSART \ Power Reduction USART3
+&100 constant PRR0 \ Power Reduction Register0
+ $80 constant PRR0_PRTWI \ Power Reduction TWI
+ $40 constant PRR0_PRTIM2 \ Power Reduction Timer/Counter2
+ $20 constant PRR0_PRTIM0 \ Power Reduction Timer/Counter0
+ $08 constant PRR0_PRTIM1 \ Power Reduction Timer/Counter1
+ $04 constant PRR0_PRSPI \ Power Reduction Serial Peripheral Interface
+ $02 constant PRR0_PRUSART0 \ Power Reduction USART
+ $01 constant PRR0_PRADC \ Power Reduction ADC
+\ AD_CONVERTER
+&124 constant ADMUX \ The ADC multiplexer Selection Register
+ $C0 constant ADMUX_REFS \ Reference Selection Bits
+ $20 constant ADMUX_ADLAR \ Left Adjust Result
+ $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
+&120 constant ADC \ ADC Data Register Bytes
+&122 constant ADCSRA \ The ADC Control and Status register A
+ $80 constant ADCSRA_ADEN \ ADC Enable
+ $40 constant ADCSRA_ADSC \ ADC Start Conversion
+ $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
+ $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
+ $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
+ $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
+&125 constant DIDR2 \ Digital Input Disable Register
+ $80 constant DIDR2_ADC15D \
+ $40 constant DIDR2_ADC14D \
+ $20 constant DIDR2_ADC13D \
+ $10 constant DIDR2_ADC12D \
+ $08 constant DIDR2_ADC11D \
+ $04 constant DIDR2_ADC10D \
+ $02 constant DIDR2_ADC9D \
+ $01 constant DIDR2_ADC8D \
+&126 constant DIDR0 \ Digital Input Disable Register
+ $80 constant DIDR0_ADC7D \
+ $40 constant DIDR0_ADC6D \
+ $20 constant DIDR0_ADC5D \
+ $10 constant DIDR0_ADC4D \
+ $08 constant DIDR0_ADC3D \
+ $04 constant DIDR0_ADC2D \
+ $02 constant DIDR0_ADC1D \
+ $01 constant DIDR0_ADC0D \
+\ BOOT_LOAD
+&87 constant SPMCSR \ Store Program Memory Control Register
+ $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
+ $20 constant SPMCSR_SIGRD \ Signature Row Read
+ $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
+ $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
+ $04 constant SPMCSR_PGWRT \ Page Write
+ $02 constant SPMCSR_PGERS \ Page Erase
+ $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
+\ USART2
+&214 constant UDR2 \ USART I/O Data Register
+&208 constant UCSR2A \ USART Control and Status Register A
+ $80 constant UCSR2A_RXC2 \ USART Receive Complete
+ $40 constant UCSR2A_TXC2 \ USART Transmitt Complete
+ $20 constant UCSR2A_UDRE2 \ USART Data Register Empty
+ $10 constant UCSR2A_FE2 \ Framing Error
+ $08 constant UCSR2A_DOR2 \ Data overRun
+ $04 constant UCSR2A_UPE2 \ Parity Error
+ $02 constant UCSR2A_U2X2 \ Double the USART transmission speed
+ $01 constant UCSR2A_MPCM2 \ Multi-processor Communication Mode
+&209 constant UCSR2B \ USART Control and Status Register B
+ $80 constant UCSR2B_RXCIE2 \ RX Complete Interrupt Enable
+ $40 constant UCSR2B_TXCIE2 \ TX Complete Interrupt Enable
+ $20 constant UCSR2B_UDRIE2 \ USART Data register Empty Interrupt Enable
+ $10 constant UCSR2B_RXEN2 \ Receiver Enable
+ $08 constant UCSR2B_TXEN2 \ Transmitter Enable
+ $04 constant UCSR2B_UCSZ22 \ Character Size
+ $02 constant UCSR2B_RXB82 \ Receive Data Bit 8
+ $01 constant UCSR2B_TXB82 \ Transmit Data Bit 8
+&210 constant UCSR2C \ USART Control and Status Register C
+ $C0 constant UCSR2C_UMSEL2 \ USART Mode Select
+ $30 constant UCSR2C_UPM2 \ Parity Mode Bits
+ $08 constant UCSR2C_USBS2 \ Stop Bit Select
+ $06 constant UCSR2C_UCSZ2 \ Character Size
+ $01 constant UCSR2C_UCPOL2 \ Clock Polarity
+&212 constant UBRR2 \ USART Baud Rate Register Bytes
+\ USART3
+&310 constant UDR3 \ USART I/O Data Register
+&304 constant UCSR3A \ USART Control and Status Register A
+ $80 constant UCSR3A_RXC3 \ USART Receive Complete
+ $40 constant UCSR3A_TXC3 \ USART Transmitt Complete
+ $20 constant UCSR3A_UDRE3 \ USART Data Register Empty
+ $10 constant UCSR3A_FE3 \ Framing Error
+ $08 constant UCSR3A_DOR3 \ Data overRun
+ $04 constant UCSR3A_UPE3 \ Parity Error
+ $02 constant UCSR3A_U2X3 \ Double the USART transmission speed
+ $01 constant UCSR3A_MPCM3 \ Multi-processor Communication Mode
+&305 constant UCSR3B \ USART Control and Status Register B
+ $80 constant UCSR3B_RXCIE3 \ RX Complete Interrupt Enable
+ $40 constant UCSR3B_TXCIE3 \ TX Complete Interrupt Enable
+ $20 constant UCSR3B_UDRIE3 \ USART Data register Empty Interrupt Enable
+ $10 constant UCSR3B_RXEN3 \ Receiver Enable
+ $08 constant UCSR3B_TXEN3 \ Transmitter Enable
+ $04 constant UCSR3B_UCSZ32 \ Character Size
+ $02 constant UCSR3B_RXB83 \ Receive Data Bit 8
+ $01 constant UCSR3B_TXB83 \ Transmit Data Bit 8
+&306 constant UCSR3C \ USART Control and Status Register C
+ $C0 constant UCSR3C_UMSEL3 \ USART Mode Select
+ $30 constant UCSR3C_UPM3 \ Parity Mode Bits
+ $08 constant UCSR3C_USBS3 \ Stop Bit Select
+ $06 constant UCSR3C_UCSZ3 \ Character Size
+ $01 constant UCSR3C_UCPOL3 \ Clock Polarity
+&308 constant UBRR3 \ USART Baud Rate Register Bytes
+
+\ Interrupts
+&2 constant INT0Addr \ External Interrupt Request 0
+&4 constant INT1Addr \ External Interrupt Request 1
+&6 constant INT2Addr \ External Interrupt Request 2
+&8 constant INT3Addr \ External Interrupt Request 3
+&10 constant INT4Addr \ External Interrupt Request 4
+&12 constant INT5Addr \ External Interrupt Request 5
+&14 constant INT6Addr \ External Interrupt Request 6
+&16 constant INT7Addr \ External Interrupt Request 7
+&18 constant PCINT0Addr \ Pin Change Interrupt Request 0
+&20 constant PCINT1Addr \ Pin Change Interrupt Request 1
+&22 constant PCINT2Addr \ Pin Change Interrupt Request 2
+&24 constant WDTAddr \ Watchdog Time-out Interrupt
+&26 constant TIMER2_COMPAAddr \ Timer/Counter2 Compare Match A
+&28 constant TIMER2_COMPBAddr \ Timer/Counter2 Compare Match B
+&30 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
+&32 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+&34 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
+&36 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
+&38 constant TIMER1_COMPCAddr \ Timer/Counter1 Compare Match C
+&40 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+&42 constant TIMER0_COMPAAddr \ Timer/Counter0 Compare Match A
+&44 constant TIMER0_COMPBAddr \ Timer/Counter0 Compare Match B
+&46 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
+&48 constant SPI__STCAddr \ SPI Serial Transfer Complete
+&50 constant USART0__RXAddr \ USART0, Rx Complete
+&52 constant USART0__UDREAddr \ USART0 Data register Empty
+&54 constant USART0__TXAddr \ USART0, Tx Complete
+&56 constant ANALOG_COMPAddr \ Analog Comparator
+&58 constant ADCAddr \ ADC Conversion Complete
+&60 constant EE_READYAddr \ EEPROM Ready
+&62 constant TIMER3_CAPTAddr \ Timer/Counter3 Capture Event
+&64 constant TIMER3_COMPAAddr \ Timer/Counter3 Compare Match A
+&66 constant TIMER3_COMPBAddr \ Timer/Counter3 Compare Match B
+&68 constant TIMER3_COMPCAddr \ Timer/Counter3 Compare Match C
+&70 constant TIMER3_OVFAddr \ Timer/Counter3 Overflow
+&72 constant USART1__RXAddr \ USART1, Rx Complete
+&74 constant USART1__UDREAddr \ USART1 Data register Empty
+&76 constant USART1__TXAddr \ USART1, Tx Complete
+&78 constant TWIAddr \ 2-wire Serial Interface
+&80 constant SPM_READYAddr \ Store Program Memory Read
+&82 constant TIMER4_CAPTAddr \ Timer/Counter4 Capture Event
+&84 constant TIMER4_COMPAAddr \ Timer/Counter4 Compare Match A
+&86 constant TIMER4_COMPBAddr \ Timer/Counter4 Compare Match B
+&88 constant TIMER4_COMPCAddr \ Timer/Counter4 Compare Match C
+&90 constant TIMER4_OVFAddr \ Timer/Counter4 Overflow
+&92 constant TIMER5_CAPTAddr \ Timer/Counter5 Capture Event
+&94 constant TIMER5_COMPAAddr \ Timer/Counter5 Compare Match A
+&96 constant TIMER5_COMPBAddr \ Timer/Counter5 Compare Match B
+&98 constant TIMER5_COMPCAddr \ Timer/Counter5 Compare Match C
+&100 constant TIMER5_OVFAddr \ Timer/Counter5 Overflow
+&102 constant USART2__RXAddr \ USART2, Rx Complete
+&104 constant USART2__UDREAddr \ USART2 Data register Empty
+&106 constant USART2__TXAddr \ USART2, Tx Complete
+&108 constant USART3__RXAddr \ USART3, Rx Complete
+&110 constant USART3__UDREAddr \ USART3 Data register Empty
+&112 constant USART3__TXAddr \ USART3, Tx Complete
diff --git a/amforth-6.5/avr8/devices/atmega640/device.asm b/amforth-6.5/avr8/devices/atmega640/device.asm
new file mode 100644
index 0000000..32d7b10
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega640/device.asm
@@ -0,0 +1,184 @@
+; Partname: ATmega640
+; generated automatically, do not edit
+
+.nolist
+ .include "m640def.inc"
+.list
+
+.equ ramstart = 512
+.equ CELLSIZE = 2
+.macro readflashcell
+ lsl zl
+ rol zh
+ lpm @0, Z+
+ lpm @1, Z+
+.endmacro
+.macro writeflashcell
+ lsl zl
+ rol zh
+.endmacro
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_USART0 = 0
+.set WANT_TWI = 0
+.set WANT_SPI = 0
+.set WANT_PORTA = 0
+.set WANT_PORTB = 0
+.set WANT_PORTC = 0
+.set WANT_PORTD = 0
+.set WANT_PORTE = 0
+.set WANT_PORTF = 0
+.set WANT_PORTG = 0
+.set WANT_PORTH = 0
+.set WANT_PORTJ = 0
+.set WANT_PORTK = 0
+.set WANT_PORTL = 0
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_TIMER_COUNTER_2 = 0
+.set WANT_WATCHDOG = 0
+.set WANT_USART1 = 0
+.set WANT_EEPROM = 0
+.set WANT_TIMER_COUNTER_5 = 0
+.set WANT_TIMER_COUNTER_4 = 0
+.set WANT_TIMER_COUNTER_3 = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_JTAG = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_CPU = 0
+.set WANT_AD_CONVERTER = 0
+.set WANT_BOOT_LOAD = 0
+.set WANT_USART2 = 0
+.set WANT_USART3 = 0
+.equ intvecsize = 2 ; please verify; flash size: 65536 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.org 2
+ rcall isr ; External Interrupt Request 0
+.org 4
+ rcall isr ; External Interrupt Request 1
+.org 6
+ rcall isr ; External Interrupt Request 2
+.org 8
+ rcall isr ; External Interrupt Request 3
+.org 10
+ rcall isr ; External Interrupt Request 4
+.org 12
+ rcall isr ; External Interrupt Request 5
+.org 14
+ rcall isr ; External Interrupt Request 6
+.org 16
+ rcall isr ; External Interrupt Request 7
+.org 18
+ rcall isr ; Pin Change Interrupt Request 0
+.org 20
+ rcall isr ; Pin Change Interrupt Request 1
+.org 22
+ rcall isr ; Pin Change Interrupt Request 2
+.org 24
+ rcall isr ; Watchdog Time-out Interrupt
+.org 26
+ rcall isr ; Timer/Counter2 Compare Match A
+.org 28
+ rcall isr ; Timer/Counter2 Compare Match B
+.org 30
+ rcall isr ; Timer/Counter2 Overflow
+.org 32
+ rcall isr ; Timer/Counter1 Capture Event
+.org 34
+ rcall isr ; Timer/Counter1 Compare Match A
+.org 36
+ rcall isr ; Timer/Counter1 Compare Match B
+.org 38
+ rcall isr ; Timer/Counter1 Compare Match C
+.org 40
+ rcall isr ; Timer/Counter1 Overflow
+.org 42
+ rcall isr ; Timer/Counter0 Compare Match A
+.org 44
+ rcall isr ; Timer/Counter0 Compare Match B
+.org 46
+ rcall isr ; Timer/Counter0 Overflow
+.org 48
+ rcall isr ; SPI Serial Transfer Complete
+.org 50
+ rcall isr ; USART0, Rx Complete
+.org 52
+ rcall isr ; USART0 Data register Empty
+.org 54
+ rcall isr ; USART0, Tx Complete
+.org 56
+ rcall isr ; Analog Comparator
+.org 58
+ rcall isr ; ADC Conversion Complete
+.org 60
+ rcall isr ; EEPROM Ready
+.org 62
+ rcall isr ; Timer/Counter3 Capture Event
+.org 64
+ rcall isr ; Timer/Counter3 Compare Match A
+.org 66
+ rcall isr ; Timer/Counter3 Compare Match B
+.org 68
+ rcall isr ; Timer/Counter3 Compare Match C
+.org 70
+ rcall isr ; Timer/Counter3 Overflow
+.org 72
+ rcall isr ; USART1, Rx Complete
+.org 74
+ rcall isr ; USART1 Data register Empty
+.org 76
+ rcall isr ; USART1, Tx Complete
+.org 78
+ rcall isr ; 2-wire Serial Interface
+.org 80
+ rcall isr ; Store Program Memory Read
+.org 82
+ rcall isr ; Timer/Counter4 Capture Event
+.org 84
+ rcall isr ; Timer/Counter4 Compare Match A
+.org 86
+ rcall isr ; Timer/Counter4 Compare Match B
+.org 88
+ rcall isr ; Timer/Counter4 Compare Match C
+.org 90
+ rcall isr ; Timer/Counter4 Overflow
+.org 92
+ rcall isr ; Timer/Counter5 Capture Event
+.org 94
+ rcall isr ; Timer/Counter5 Compare Match A
+.org 96
+ rcall isr ; Timer/Counter5 Compare Match B
+.org 98
+ rcall isr ; Timer/Counter5 Compare Match C
+.org 100
+ rcall isr ; Timer/Counter5 Overflow
+.org 102
+ rcall isr ; USART2, Rx Complete
+.org 104
+ rcall isr ; USART2 Data register Empty
+.org 106
+ rcall isr ; USART2, Tx Complete
+.org 108
+ rcall isr ; USART3, Rx Complete
+.org 110
+ rcall isr ; USART3 Data register Empty
+.org 112
+ rcall isr ; USART3, Tx Complete
+.equ INTVECTORS = 57
+.nooverlap
+
+; compatability layer (maybe empty)
+
+; controller data area, environment query mcu-info
+mcu_info:
+mcu_ramsize:
+ .dw 8192
+mcu_eepromsize:
+ .dw 4096
+mcu_maxdp:
+ .dw 57344
+mcu_numints:
+ .dw 57
+mcu_name:
+ .dw 9
+ .db "ATmega640",0
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega640/device.inc b/amforth-6.5/avr8/devices/atmega640/device.inc
new file mode 100644
index 0000000..5c15876
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega640/device.inc
@@ -0,0 +1,1968 @@
+; Partname: ATmega640
+; generated automatically, no not edit
+
+.if WANT_ANALOG_COMPARATOR == 1
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Control and Status Register B
+VE_ADCSRB:
+ .dw $ff06
+ .db "ADCSRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRB
+XT_ADCSRB:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRB:
+ .dw 123
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Control And Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw 80
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 1
+VE_DIDR1:
+ .dw $ff05
+ .db "DIDR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR1
+XT_DIDR1:
+ .dw PFA_DOVARIABLE
+PFA_DIDR1:
+ .dw 127
+
+.endif
+.if WANT_USART0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR0:
+ .dw $ff04
+ .db "UDR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR0
+XT_UDR0:
+ .dw PFA_DOVARIABLE
+PFA_UDR0:
+ .dw 198
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR0A:
+ .dw $ff06
+ .db "UCSR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0A
+XT_UCSR0A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0A:
+ .dw 192
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR0B:
+ .dw $ff06
+ .db "UCSR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0B
+XT_UCSR0B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0B:
+ .dw 193
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR0C:
+ .dw $ff06
+ .db "UCSR0C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0C
+XT_UCSR0C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0C:
+ .dw 194
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Bytes
+VE_UBRR0:
+ .dw $ff05
+ .db "UBRR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR0
+XT_UBRR0:
+ .dw PFA_DOVARIABLE
+PFA_UBRR0:
+ .dw 196
+
+.endif
+.if WANT_TWI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; TWI (Slave) Address Mask Register
+VE_TWAMR:
+ .dw $ff05
+ .db "TWAMR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWAMR
+XT_TWAMR:
+ .dw PFA_DOVARIABLE
+PFA_TWAMR:
+ .dw 189
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Bit Rate register
+VE_TWBR:
+ .dw $ff04
+ .db "TWBR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWBR
+XT_TWBR:
+ .dw PFA_DOVARIABLE
+PFA_TWBR:
+ .dw 184
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Control Register
+VE_TWCR:
+ .dw $ff04
+ .db "TWCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWCR
+XT_TWCR:
+ .dw PFA_DOVARIABLE
+PFA_TWCR:
+ .dw 188
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Status Register
+VE_TWSR:
+ .dw $ff04
+ .db "TWSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWSR
+XT_TWSR:
+ .dw PFA_DOVARIABLE
+PFA_TWSR:
+ .dw 185
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Data register
+VE_TWDR:
+ .dw $ff04
+ .db "TWDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWDR
+XT_TWDR:
+ .dw PFA_DOVARIABLE
+PFA_TWDR:
+ .dw 187
+; ( -- addr ) System Constant
+; R( -- )
+; TWI (Slave) Address register
+VE_TWAR:
+ .dw $ff04
+ .db "TWAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWAR
+XT_TWAR:
+ .dw PFA_DOVARIABLE
+PFA_TWAR:
+ .dw 186
+
+.endif
+.if WANT_SPI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR:
+ .dw $ff04
+ .db "SPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR
+XT_SPCR:
+ .dw PFA_DOVARIABLE
+PFA_SPCR:
+ .dw 76
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR:
+ .dw $ff04
+ .db "SPSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR
+XT_SPSR:
+ .dw PFA_DOVARIABLE
+PFA_SPSR:
+ .dw 77
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR:
+ .dw $ff04
+ .db "SPDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR
+XT_SPDR:
+ .dw PFA_DOVARIABLE
+PFA_SPDR:
+ .dw 78
+
+.endif
+.if WANT_PORTA == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Register
+VE_PORTA:
+ .dw $ff05
+ .db "PORTA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTA
+XT_PORTA:
+ .dw PFA_DOVARIABLE
+PFA_PORTA:
+ .dw 34
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Direction Register
+VE_DDRA:
+ .dw $ff04
+ .db "DDRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRA
+XT_DDRA:
+ .dw PFA_DOVARIABLE
+PFA_DDRA:
+ .dw 33
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Input Pins
+VE_PINA:
+ .dw $ff04
+ .db "PINA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINA
+XT_PINA:
+ .dw PFA_DOVARIABLE
+PFA_PINA:
+ .dw 32
+
+.endif
+.if WANT_PORTB == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw 37
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw 36
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw 35
+
+.endif
+.if WANT_PORTC == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Register
+VE_PORTC:
+ .dw $ff05
+ .db "PORTC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTC
+XT_PORTC:
+ .dw PFA_DOVARIABLE
+PFA_PORTC:
+ .dw 40
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Direction Register
+VE_DDRC:
+ .dw $ff04
+ .db "DDRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRC
+XT_DDRC:
+ .dw PFA_DOVARIABLE
+PFA_DDRC:
+ .dw 39
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Input Pins
+VE_PINC:
+ .dw $ff04
+ .db "PINC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINC
+XT_PINC:
+ .dw PFA_DOVARIABLE
+PFA_PINC:
+ .dw 38
+
+.endif
+.if WANT_PORTD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw 43
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw 42
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw 41
+
+.endif
+.if WANT_PORTE == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port E
+VE_PORTE:
+ .dw $ff05
+ .db "PORTE",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTE
+XT_PORTE:
+ .dw PFA_DOVARIABLE
+PFA_PORTE:
+ .dw 46
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port E
+VE_DDRE:
+ .dw $ff04
+ .db "DDRE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRE
+XT_DDRE:
+ .dw PFA_DOVARIABLE
+PFA_DDRE:
+ .dw 45
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port E
+VE_PINE:
+ .dw $ff04
+ .db "PINE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINE
+XT_PINE:
+ .dw PFA_DOVARIABLE
+PFA_PINE:
+ .dw 44
+
+.endif
+.if WANT_PORTF == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port F
+VE_PORTF:
+ .dw $ff05
+ .db "PORTF",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTF
+XT_PORTF:
+ .dw PFA_DOVARIABLE
+PFA_PORTF:
+ .dw 49
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port F
+VE_DDRF:
+ .dw $ff04
+ .db "DDRF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRF
+XT_DDRF:
+ .dw PFA_DOVARIABLE
+PFA_DDRF:
+ .dw 48
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port F
+VE_PINF:
+ .dw $ff04
+ .db "PINF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINF
+XT_PINF:
+ .dw PFA_DOVARIABLE
+PFA_PINF:
+ .dw 47
+
+.endif
+.if WANT_PORTG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port G
+VE_PORTG:
+ .dw $ff05
+ .db "PORTG",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTG
+XT_PORTG:
+ .dw PFA_DOVARIABLE
+PFA_PORTG:
+ .dw 52
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port G
+VE_DDRG:
+ .dw $ff04
+ .db "DDRG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRG
+XT_DDRG:
+ .dw PFA_DOVARIABLE
+PFA_DDRG:
+ .dw 51
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port G
+VE_PING:
+ .dw $ff04
+ .db "PING"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PING
+XT_PING:
+ .dw PFA_DOVARIABLE
+PFA_PING:
+ .dw 50
+
+.endif
+.if WANT_PORTH == 1
+; ( -- addr ) System Constant
+; R( -- )
+; PORT H Data Register
+VE_PORTH:
+ .dw $ff05
+ .db "PORTH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTH
+XT_PORTH:
+ .dw PFA_DOVARIABLE
+PFA_PORTH:
+ .dw 258
+; ( -- addr ) System Constant
+; R( -- )
+; PORT H Data Direction Register
+VE_DDRH:
+ .dw $ff04
+ .db "DDRH"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRH
+XT_DDRH:
+ .dw PFA_DOVARIABLE
+PFA_DDRH:
+ .dw 257
+; ( -- addr ) System Constant
+; R( -- )
+; PORT H Input Pins
+VE_PINH:
+ .dw $ff04
+ .db "PINH"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINH
+XT_PINH:
+ .dw PFA_DOVARIABLE
+PFA_PINH:
+ .dw 256
+
+.endif
+.if WANT_PORTJ == 1
+; ( -- addr ) System Constant
+; R( -- )
+; PORT J Data Register
+VE_PORTJ:
+ .dw $ff05
+ .db "PORTJ",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTJ
+XT_PORTJ:
+ .dw PFA_DOVARIABLE
+PFA_PORTJ:
+ .dw 261
+; ( -- addr ) System Constant
+; R( -- )
+; PORT J Data Direction Register
+VE_DDRJ:
+ .dw $ff04
+ .db "DDRJ"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRJ
+XT_DDRJ:
+ .dw PFA_DOVARIABLE
+PFA_DDRJ:
+ .dw 260
+; ( -- addr ) System Constant
+; R( -- )
+; PORT J Input Pins
+VE_PINJ:
+ .dw $ff04
+ .db "PINJ"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINJ
+XT_PINJ:
+ .dw PFA_DOVARIABLE
+PFA_PINJ:
+ .dw 259
+
+.endif
+.if WANT_PORTK == 1
+; ( -- addr ) System Constant
+; R( -- )
+; PORT K Data Register
+VE_PORTK:
+ .dw $ff05
+ .db "PORTK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTK
+XT_PORTK:
+ .dw PFA_DOVARIABLE
+PFA_PORTK:
+ .dw 264
+; ( -- addr ) System Constant
+; R( -- )
+; PORT K Data Direction Register
+VE_DDRK:
+ .dw $ff04
+ .db "DDRK"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRK
+XT_DDRK:
+ .dw PFA_DOVARIABLE
+PFA_DDRK:
+ .dw 263
+; ( -- addr ) System Constant
+; R( -- )
+; PORT K Input Pins
+VE_PINK:
+ .dw $ff04
+ .db "PINK"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINK
+XT_PINK:
+ .dw PFA_DOVARIABLE
+PFA_PINK:
+ .dw 262
+
+.endif
+.if WANT_PORTL == 1
+; ( -- addr ) System Constant
+; R( -- )
+; PORT L Data Register
+VE_PORTL:
+ .dw $ff05
+ .db "PORTL",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTL
+XT_PORTL:
+ .dw PFA_DOVARIABLE
+PFA_PORTL:
+ .dw 267
+; ( -- addr ) System Constant
+; R( -- )
+; PORT L Data Direction Register
+VE_DDRL:
+ .dw $ff04
+ .db "DDRL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRL
+XT_DDRL:
+ .dw PFA_DOVARIABLE
+PFA_DDRL:
+ .dw 266
+; ( -- addr ) System Constant
+; R( -- )
+; PORT L Input Pins
+VE_PINL:
+ .dw $ff04
+ .db "PINL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINL
+XT_PINL:
+ .dw PFA_DOVARIABLE
+PFA_PINL:
+ .dw 265
+
+.endif
+.if WANT_TIMER_COUNTER_0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0B:
+ .dw $ff05
+ .db "OCR0B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0B
+XT_OCR0B:
+ .dw PFA_DOVARIABLE
+PFA_OCR0B:
+ .dw 72
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0A:
+ .dw $ff05
+ .db "OCR0A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0A
+XT_OCR0A:
+ .dw PFA_DOVARIABLE
+PFA_OCR0A:
+ .dw 71
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw 70
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register B
+VE_TCCR0B:
+ .dw $ff06
+ .db "TCCR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0B
+XT_TCCR0B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0B:
+ .dw 69
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register A
+VE_TCCR0A:
+ .dw $ff06
+ .db "TCCR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0A
+XT_TCCR0A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0A:
+ .dw 68
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Mask Register
+VE_TIMSK0:
+ .dw $ff06
+ .db "TIMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK0
+XT_TIMSK0:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK0:
+ .dw 110
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Flag register
+VE_TIFR0:
+ .dw $ff05
+ .db "TIFR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR0
+XT_TIFR0:
+ .dw PFA_DOVARIABLE
+PFA_TIFR0:
+ .dw 53
+; ( -- addr ) System Constant
+; R( -- )
+; General Timer/Counter Control Register
+VE_GTCCR:
+ .dw $ff05
+ .db "GTCCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GTCCR
+XT_GTCCR:
+ .dw PFA_DOVARIABLE
+PFA_GTCCR:
+ .dw 67
+
+.endif
+.if WANT_TIMER_COUNTER_2 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Mask register
+VE_TIMSK2:
+ .dw $ff06
+ .db "TIMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK2
+XT_TIMSK2:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK2:
+ .dw 112
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Flag Register
+VE_TIFR2:
+ .dw $ff05
+ .db "TIFR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR2
+XT_TIFR2:
+ .dw PFA_DOVARIABLE
+PFA_TIFR2:
+ .dw 55
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register A
+VE_TCCR2A:
+ .dw $ff06
+ .db "TCCR2A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2A
+XT_TCCR2A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2A:
+ .dw 176
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register B
+VE_TCCR2B:
+ .dw $ff06
+ .db "TCCR2B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2B
+XT_TCCR2B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2B:
+ .dw 177
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2
+VE_TCNT2:
+ .dw $ff05
+ .db "TCNT2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT2
+XT_TCNT2:
+ .dw PFA_DOVARIABLE
+PFA_TCNT2:
+ .dw 178
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register B
+VE_OCR2B:
+ .dw $ff05
+ .db "OCR2B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2B
+XT_OCR2B:
+ .dw PFA_DOVARIABLE
+PFA_OCR2B:
+ .dw 180
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register A
+VE_OCR2A:
+ .dw $ff05
+ .db "OCR2A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2A
+XT_OCR2A:
+ .dw PFA_DOVARIABLE
+PFA_OCR2A:
+ .dw 179
+; ( -- addr ) System Constant
+; R( -- )
+; Asynchronous Status Register
+VE_ASSR:
+ .dw $ff04
+ .db "ASSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ASSR
+XT_ASSR:
+ .dw PFA_DOVARIABLE
+PFA_ASSR:
+ .dw 182
+
+.endif
+.if WANT_WATCHDOG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCSR:
+ .dw $ff06
+ .db "WDTCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCSR
+XT_WDTCSR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCSR:
+ .dw 96
+
+.endif
+.if WANT_USART1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR1:
+ .dw $ff04
+ .db "UDR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR1
+XT_UDR1:
+ .dw PFA_DOVARIABLE
+PFA_UDR1:
+ .dw 206
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR1A:
+ .dw $ff06
+ .db "UCSR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1A
+XT_UCSR1A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1A:
+ .dw 200
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR1B:
+ .dw $ff06
+ .db "UCSR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1B
+XT_UCSR1B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1B:
+ .dw 201
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR1C:
+ .dw $ff06
+ .db "UCSR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1C
+XT_UCSR1C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1C:
+ .dw 202
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Bytes
+VE_UBRR1:
+ .dw $ff05
+ .db "UBRR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR1
+XT_UBRR1:
+ .dw PFA_DOVARIABLE
+PFA_UBRR1:
+ .dw 204
+
+.endif
+.if WANT_EEPROM == 1
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Address Register Low Bytes
+VE_EEAR:
+ .dw $ff04
+ .db "EEAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEAR
+XT_EEAR:
+ .dw PFA_DOVARIABLE
+PFA_EEAR:
+ .dw 65
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw 64
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw 63
+
+.endif
+.if WANT_TIMER_COUNTER_5 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter5 Control Register A
+VE_TCCR5A:
+ .dw $ff06
+ .db "TCCR5A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR5A
+XT_TCCR5A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR5A:
+ .dw 288
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter5 Control Register B
+VE_TCCR5B:
+ .dw $ff06
+ .db "TCCR5B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR5B
+XT_TCCR5B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR5B:
+ .dw 289
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter 5 Control Register C
+VE_TCCR5C:
+ .dw $ff06
+ .db "TCCR5C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR5C
+XT_TCCR5C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR5C:
+ .dw 290
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter5 Bytes
+VE_TCNT5:
+ .dw $ff05
+ .db "TCNT5",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT5
+XT_TCNT5:
+ .dw PFA_DOVARIABLE
+PFA_TCNT5:
+ .dw 292
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter5 Output Compare Register A Bytes
+VE_OCR5A:
+ .dw $ff05
+ .db "OCR5A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR5A
+XT_OCR5A:
+ .dw PFA_DOVARIABLE
+PFA_OCR5A:
+ .dw 296
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter5 Output Compare Register B Bytes
+VE_OCR5B:
+ .dw $ff05
+ .db "OCR5B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR5B
+XT_OCR5B:
+ .dw PFA_DOVARIABLE
+PFA_OCR5B:
+ .dw 298
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter5 Output Compare Register B Bytes
+VE_OCR5C:
+ .dw $ff05
+ .db "OCR5C",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR5C
+XT_OCR5C:
+ .dw PFA_DOVARIABLE
+PFA_OCR5C:
+ .dw 300
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter5 Input Capture Register Bytes
+VE_ICR5:
+ .dw $ff04
+ .db "ICR5"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR5
+XT_ICR5:
+ .dw PFA_DOVARIABLE
+PFA_ICR5:
+ .dw 294
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter5 Interrupt Mask Register
+VE_TIMSK5:
+ .dw $ff06
+ .db "TIMSK5"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK5
+XT_TIMSK5:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK5:
+ .dw 115
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter5 Interrupt Flag register
+VE_TIFR5:
+ .dw $ff05
+ .db "TIFR5",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR5
+XT_TIFR5:
+ .dw PFA_DOVARIABLE
+PFA_TIFR5:
+ .dw 58
+
+.endif
+.if WANT_TIMER_COUNTER_4 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter4 Control Register A
+VE_TCCR4A:
+ .dw $ff06
+ .db "TCCR4A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR4A
+XT_TCCR4A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR4A:
+ .dw 160
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter4 Control Register B
+VE_TCCR4B:
+ .dw $ff06
+ .db "TCCR4B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR4B
+XT_TCCR4B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR4B:
+ .dw 161
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter 4 Control Register C
+VE_TCCR4C:
+ .dw $ff06
+ .db "TCCR4C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR4C
+XT_TCCR4C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR4C:
+ .dw 162
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter4 Bytes
+VE_TCNT4:
+ .dw $ff05
+ .db "TCNT4",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT4
+XT_TCNT4:
+ .dw PFA_DOVARIABLE
+PFA_TCNT4:
+ .dw 164
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter4 Output Compare Register A Bytes
+VE_OCR4A:
+ .dw $ff05
+ .db "OCR4A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR4A
+XT_OCR4A:
+ .dw PFA_DOVARIABLE
+PFA_OCR4A:
+ .dw 168
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter4 Output Compare Register B Bytes
+VE_OCR4B:
+ .dw $ff05
+ .db "OCR4B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR4B
+XT_OCR4B:
+ .dw PFA_DOVARIABLE
+PFA_OCR4B:
+ .dw 170
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter4 Output Compare Register B Bytes
+VE_OCR4C:
+ .dw $ff05
+ .db "OCR4C",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR4C
+XT_OCR4C:
+ .dw PFA_DOVARIABLE
+PFA_OCR4C:
+ .dw 172
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter4 Input Capture Register Bytes
+VE_ICR4:
+ .dw $ff04
+ .db "ICR4"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR4
+XT_ICR4:
+ .dw PFA_DOVARIABLE
+PFA_ICR4:
+ .dw 166
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter4 Interrupt Mask Register
+VE_TIMSK4:
+ .dw $ff06
+ .db "TIMSK4"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK4
+XT_TIMSK4:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK4:
+ .dw 114
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter4 Interrupt Flag register
+VE_TIFR4:
+ .dw $ff05
+ .db "TIFR4",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR4
+XT_TIFR4:
+ .dw PFA_DOVARIABLE
+PFA_TIFR4:
+ .dw 57
+
+.endif
+.if WANT_TIMER_COUNTER_3 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Control Register A
+VE_TCCR3A:
+ .dw $ff06
+ .db "TCCR3A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR3A
+XT_TCCR3A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR3A:
+ .dw 144
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Control Register B
+VE_TCCR3B:
+ .dw $ff06
+ .db "TCCR3B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR3B
+XT_TCCR3B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR3B:
+ .dw 145
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter 3 Control Register C
+VE_TCCR3C:
+ .dw $ff06
+ .db "TCCR3C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR3C
+XT_TCCR3C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR3C:
+ .dw 146
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Bytes
+VE_TCNT3:
+ .dw $ff05
+ .db "TCNT3",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT3
+XT_TCNT3:
+ .dw PFA_DOVARIABLE
+PFA_TCNT3:
+ .dw 148
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Output Compare Register A Bytes
+VE_OCR3A:
+ .dw $ff05
+ .db "OCR3A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR3A
+XT_OCR3A:
+ .dw PFA_DOVARIABLE
+PFA_OCR3A:
+ .dw 152
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Output Compare Register B Bytes
+VE_OCR3B:
+ .dw $ff05
+ .db "OCR3B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR3B
+XT_OCR3B:
+ .dw PFA_DOVARIABLE
+PFA_OCR3B:
+ .dw 154
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Output Compare Register B Bytes
+VE_OCR3C:
+ .dw $ff05
+ .db "OCR3C",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR3C
+XT_OCR3C:
+ .dw PFA_DOVARIABLE
+PFA_OCR3C:
+ .dw 156
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Input Capture Register Bytes
+VE_ICR3:
+ .dw $ff04
+ .db "ICR3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR3
+XT_ICR3:
+ .dw PFA_DOVARIABLE
+PFA_ICR3:
+ .dw 150
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Interrupt Mask Register
+VE_TIMSK3:
+ .dw $ff06
+ .db "TIMSK3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK3
+XT_TIMSK3:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK3:
+ .dw 113
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Interrupt Flag register
+VE_TIFR3:
+ .dw $ff05
+ .db "TIFR3",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR3
+XT_TIFR3:
+ .dw PFA_DOVARIABLE
+PFA_TIFR3:
+ .dw 56
+
+.endif
+.if WANT_TIMER_COUNTER_1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw 128
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw 129
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter 1 Control Register C
+VE_TCCR1C:
+ .dw $ff06
+ .db "TCCR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1C
+XT_TCCR1C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1C:
+ .dw 130
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Bytes
+VE_TCNT1:
+ .dw $ff05
+ .db "TCNT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1
+XT_TCNT1:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1:
+ .dw 132
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register A Bytes
+VE_OCR1A:
+ .dw $ff05
+ .db "OCR1A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1A
+XT_OCR1A:
+ .dw PFA_DOVARIABLE
+PFA_OCR1A:
+ .dw 136
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register B Bytes
+VE_OCR1B:
+ .dw $ff05
+ .db "OCR1B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1B
+XT_OCR1B:
+ .dw PFA_DOVARIABLE
+PFA_OCR1B:
+ .dw 138
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register C Bytes
+VE_OCR1C:
+ .dw $ff05
+ .db "OCR1C",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1C
+XT_OCR1C:
+ .dw PFA_DOVARIABLE
+PFA_OCR1C:
+ .dw 140
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Bytes
+VE_ICR1:
+ .dw $ff04
+ .db "ICR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1
+XT_ICR1:
+ .dw PFA_DOVARIABLE
+PFA_ICR1:
+ .dw 134
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Mask Register
+VE_TIMSK1:
+ .dw $ff06
+ .db "TIMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK1
+XT_TIMSK1:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK1:
+ .dw 111
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Flag register
+VE_TIFR1:
+ .dw $ff05
+ .db "TIFR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR1
+XT_TIFR1:
+ .dw PFA_DOVARIABLE
+PFA_TIFR1:
+ .dw 54
+
+.endif
+.if WANT_JTAG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; On-Chip Debug Related Register in I/O Memory
+VE_OCDR:
+ .dw $ff04
+ .db "OCDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCDR
+XT_OCDR:
+ .dw PFA_DOVARIABLE
+PFA_OCDR:
+ .dw 81
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw 85
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Status Register
+VE_MCUSR:
+ .dw $ff05
+ .db "MCUSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUSR
+XT_MCUSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUSR:
+ .dw 84
+
+.endif
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register A
+VE_EICRA:
+ .dw $ff05
+ .db "EICRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRA
+XT_EICRA:
+ .dw PFA_DOVARIABLE
+PFA_EICRA:
+ .dw 105
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register B
+VE_EICRB:
+ .dw $ff05
+ .db "EICRB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRB
+XT_EICRB:
+ .dw PFA_DOVARIABLE
+PFA_EICRB:
+ .dw 106
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Mask Register
+VE_EIMSK:
+ .dw $ff05
+ .db "EIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIMSK
+XT_EIMSK:
+ .dw PFA_DOVARIABLE
+PFA_EIMSK:
+ .dw 61
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Flag Register
+VE_EIFR:
+ .dw $ff04
+ .db "EIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIFR
+XT_EIFR:
+ .dw PFA_DOVARIABLE
+PFA_EIFR:
+ .dw 60
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 2
+VE_PCMSK2:
+ .dw $ff06
+ .db "PCMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK2
+XT_PCMSK2:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK2:
+ .dw 109
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 1
+VE_PCMSK1:
+ .dw $ff06
+ .db "PCMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK1
+XT_PCMSK1:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK1:
+ .dw 108
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 0
+VE_PCMSK0:
+ .dw $ff06
+ .db "PCMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK0
+XT_PCMSK0:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK0:
+ .dw 107
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Interrupt Flag Register
+VE_PCIFR:
+ .dw $ff05
+ .db "PCIFR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCIFR
+XT_PCIFR:
+ .dw PFA_DOVARIABLE
+PFA_PCIFR:
+ .dw 59
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Interrupt Control Register
+VE_PCICR:
+ .dw $ff05
+ .db "PCICR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCICR
+XT_PCICR:
+ .dw PFA_DOVARIABLE
+PFA_PCICR:
+ .dw 104
+
+.endif
+.if WANT_CPU == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw 95
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer
+VE_SP:
+ .dw $ff02
+ .db "SP"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SP
+XT_SP:
+ .dw PFA_DOVARIABLE
+PFA_SP:
+ .dw 93
+; ( -- addr ) System Constant
+; R( -- )
+; External Memory Control Register A
+VE_XMCRA:
+ .dw $ff05
+ .db "XMCRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_XMCRA
+XT_XMCRA:
+ .dw PFA_DOVARIABLE
+PFA_XMCRA:
+ .dw 116
+; ( -- addr ) System Constant
+; R( -- )
+; External Memory Control Register B
+VE_XMCRB:
+ .dw $ff05
+ .db "XMCRB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_XMCRB
+XT_XMCRB:
+ .dw PFA_DOVARIABLE
+PFA_XMCRB:
+ .dw 117
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Calibration Value
+VE_OSCCAL:
+ .dw $ff06
+ .db "OSCCAL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSCCAL
+XT_OSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_OSCCAL:
+ .dw 102
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_CLKPR:
+ .dw $ff05
+ .db "CLKPR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKPR
+XT_CLKPR:
+ .dw PFA_DOVARIABLE
+PFA_CLKPR:
+ .dw 97
+; ( -- addr ) System Constant
+; R( -- )
+; Sleep Mode Control Register
+VE_SMCR:
+ .dw $ff04
+ .db "SMCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SMCR
+XT_SMCR:
+ .dw PFA_DOVARIABLE
+PFA_SMCR:
+ .dw 83
+; ( -- addr ) System Constant
+; R( -- )
+; Extended Indirect Register
+VE_EIND:
+ .dw $ff04
+ .db "EIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIND
+XT_EIND:
+ .dw PFA_DOVARIABLE
+PFA_EIND:
+ .dw 92
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 2
+VE_GPIOR2:
+ .dw $ff06
+ .db "GPIOR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR2
+XT_GPIOR2:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR2:
+ .dw 75
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 1
+VE_GPIOR1:
+ .dw $ff06
+ .db "GPIOR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR1
+XT_GPIOR1:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR1:
+ .dw 74
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 0
+VE_GPIOR0:
+ .dw $ff06
+ .db "GPIOR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR0
+XT_GPIOR0:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR0:
+ .dw 62
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register1
+VE_PRR1:
+ .dw $ff04
+ .db "PRR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR1
+XT_PRR1:
+ .dw PFA_DOVARIABLE
+PFA_PRR1:
+ .dw 101
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register0
+VE_PRR0:
+ .dw $ff04
+ .db "PRR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR0
+XT_PRR0:
+ .dw PFA_DOVARIABLE
+PFA_PRR0:
+ .dw 100
+
+.endif
+.if WANT_AD_CONVERTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC multiplexer Selection Register
+VE_ADMUX:
+ .dw $ff05
+ .db "ADMUX",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADMUX
+XT_ADMUX:
+ .dw PFA_DOVARIABLE
+PFA_ADMUX:
+ .dw 124
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register Bytes
+VE_ADC:
+ .dw $ff03
+ .db "ADC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADC
+XT_ADC:
+ .dw PFA_DOVARIABLE
+PFA_ADC:
+ .dw 120
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register A
+VE_ADCSRA:
+ .dw $ff06
+ .db "ADCSRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRA
+XT_ADCSRA:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRA:
+ .dw 122
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register
+VE_DIDR2:
+ .dw $ff05
+ .db "DIDR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR2
+XT_DIDR2:
+ .dw PFA_DOVARIABLE
+PFA_DIDR2:
+ .dw 125
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register
+VE_DIDR0:
+ .dw $ff05
+ .db "DIDR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR0
+XT_DIDR0:
+ .dw PFA_DOVARIABLE
+PFA_DIDR0:
+ .dw 126
+
+.endif
+.if WANT_BOOT_LOAD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control Register
+VE_SPMCSR:
+ .dw $ff06
+ .db "SPMCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCSR
+XT_SPMCSR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCSR:
+ .dw 87
+
+.endif
+.if WANT_USART2 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR2:
+ .dw $ff04
+ .db "UDR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR2
+XT_UDR2:
+ .dw PFA_DOVARIABLE
+PFA_UDR2:
+ .dw 214
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR2A:
+ .dw $ff06
+ .db "UCSR2A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR2A
+XT_UCSR2A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR2A:
+ .dw 208
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR2B:
+ .dw $ff06
+ .db "UCSR2B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR2B
+XT_UCSR2B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR2B:
+ .dw 209
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR2C:
+ .dw $ff06
+ .db "UCSR2C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR2C
+XT_UCSR2C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR2C:
+ .dw 210
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Bytes
+VE_UBRR2:
+ .dw $ff05
+ .db "UBRR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR2
+XT_UBRR2:
+ .dw PFA_DOVARIABLE
+PFA_UBRR2:
+ .dw 212
+
+.endif
+.if WANT_USART3 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR3:
+ .dw $ff04
+ .db "UDR3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR3
+XT_UDR3:
+ .dw PFA_DOVARIABLE
+PFA_UDR3:
+ .dw 310
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR3A:
+ .dw $ff06
+ .db "UCSR3A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR3A
+XT_UCSR3A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR3A:
+ .dw 304
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR3B:
+ .dw $ff06
+ .db "UCSR3B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR3B
+XT_UCSR3B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR3B:
+ .dw 305
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR3C:
+ .dw $ff06
+ .db "UCSR3C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR3C
+XT_UCSR3C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR3C:
+ .dw 306
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Bytes
+VE_UBRR3:
+ .dw $ff05
+ .db "UBRR3",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR3
+XT_UBRR3:
+ .dw PFA_DOVARIABLE
+PFA_UBRR3:
+ .dw 308
+
+.endif
diff --git a/amforth-6.5/avr8/devices/atmega640/device.py b/amforth-6.5/avr8/devices/atmega640/device.py
new file mode 100644
index 0000000..526b8ed
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega640/device.py
@@ -0,0 +1,632 @@
+# Generated Automatically
+
+# Partname ATmega640
+
+MCUREGS = {
+# Interrupt Vectors
+ 'INT0Addr' : '#2', # External Interrupt Request 0
+ 'INT1Addr' : '#4', # External Interrupt Request 1
+ 'INT2Addr' : '#6', # External Interrupt Request 2
+ 'INT3Addr' : '#8', # External Interrupt Request 3
+ 'INT4Addr' : '#10', # External Interrupt Request 4
+ 'INT5Addr' : '#12', # External Interrupt Request 5
+ 'INT6Addr' : '#14', # External Interrupt Request 6
+ 'INT7Addr' : '#16', # External Interrupt Request 7
+ 'PCINT0Addr' : '#18', # Pin Change Interrupt Request 0
+ 'PCINT1Addr' : '#20', # Pin Change Interrupt Request 1
+ 'PCINT2Addr' : '#22', # Pin Change Interrupt Request 2
+ 'WDTAddr' : '#24', # Watchdog Time-out Interrupt
+ 'TIMER2_COMPAAddr' : '#26', # Timer/Counter2 Compare Match A
+ 'TIMER2_COMPBAddr' : '#28', # Timer/Counter2 Compare Match B
+ 'TIMER2_OVFAddr' : '#30', # Timer/Counter2 Overflow
+ 'TIMER1_CAPTAddr' : '#32', # Timer/Counter1 Capture Event
+ 'TIMER1_COMPAAddr' : '#34', # Timer/Counter1 Compare Match A
+ 'TIMER1_COMPBAddr' : '#36', # Timer/Counter1 Compare Match B
+ 'TIMER1_COMPCAddr' : '#38', # Timer/Counter1 Compare Match C
+ 'TIMER1_OVFAddr' : '#40', # Timer/Counter1 Overflow
+ 'TIMER0_COMPAAddr' : '#42', # Timer/Counter0 Compare Match A
+ 'TIMER0_COMPBAddr' : '#44', # Timer/Counter0 Compare Match B
+ 'TIMER0_OVFAddr' : '#46', # Timer/Counter0 Overflow
+ 'SPI_STCAddr' : '#48', # SPI Serial Transfer Complete
+ 'USART0_RXAddr' : '#50', # USART0, Rx Complete
+ 'USART0_UDREAddr' : '#52', # USART0 Data register Empty
+ 'USART0_TXAddr' : '#54', # USART0, Tx Complete
+ 'ANALOG_COMPAddr' : '#56', # Analog Comparator
+ 'ADCAddr' : '#58', # ADC Conversion Complete
+ 'EE_READYAddr' : '#60', # EEPROM Ready
+ 'TIMER3_CAPTAddr' : '#62', # Timer/Counter3 Capture Event
+ 'TIMER3_COMPAAddr' : '#64', # Timer/Counter3 Compare Match A
+ 'TIMER3_COMPBAddr' : '#66', # Timer/Counter3 Compare Match B
+ 'TIMER3_COMPCAddr' : '#68', # Timer/Counter3 Compare Match C
+ 'TIMER3_OVFAddr' : '#70', # Timer/Counter3 Overflow
+ 'USART1_RXAddr' : '#72', # USART1, Rx Complete
+ 'USART1_UDREAddr' : '#74', # USART1 Data register Empty
+ 'USART1_TXAddr' : '#76', # USART1, Tx Complete
+ 'TWIAddr' : '#78', # 2-wire Serial Interface
+ 'SPM_READYAddr' : '#80', # Store Program Memory Read
+ 'TIMER4_CAPTAddr' : '#82', # Timer/Counter4 Capture Event
+ 'TIMER4_COMPAAddr' : '#84', # Timer/Counter4 Compare Match A
+ 'TIMER4_COMPBAddr' : '#86', # Timer/Counter4 Compare Match B
+ 'TIMER4_COMPCAddr' : '#88', # Timer/Counter4 Compare Match C
+ 'TIMER4_OVFAddr' : '#90', # Timer/Counter4 Overflow
+ 'TIMER5_CAPTAddr' : '#92', # Timer/Counter5 Capture Event
+ 'TIMER5_COMPAAddr' : '#94', # Timer/Counter5 Compare Match A
+ 'TIMER5_COMPBAddr' : '#96', # Timer/Counter5 Compare Match B
+ 'TIMER5_COMPCAddr' : '#98', # Timer/Counter5 Compare Match C
+ 'TIMER5_OVFAddr' : '#100', # Timer/Counter5 Overflow
+ 'USART2_RXAddr' : '#102', # USART2, Rx Complete
+ 'USART2_UDREAddr' : '#104', # USART2 Data register Empty
+ 'USART2_TXAddr' : '#106', # USART2, Tx Complete
+ 'USART3_RXAddr' : '#108', # USART3, Rx Complete
+ 'USART3_UDREAddr' : '#110', # USART3 Data register Empty
+ 'USART3_TXAddr' : '#112', # USART3, Tx Complete
+
+# Module ANALOG_COMPARATOR
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
+ 'ACSR' : '$50', # Analog Comparator Control And
+ 'ACSR_ACD': '$80', # Analog Comparator Disable
+ 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
+ 'ACSR_ACO': '$20', # Analog Compare Output
+ 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
+ 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
+ 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
+ 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
+ 'DIDR1' : '$7f', # Digital Input Disable Register
+ 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
+ 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
+
+# Module USART0
+ 'UDR0' : '$c6', # USART I/O Data Register
+ 'UCSR0A' : '$c0', # USART Control and Status Regis
+ 'UCSR0A_RXC0': '$80', # USART Receive Complete
+ 'UCSR0A_TXC0': '$40', # USART Transmitt Complete
+ 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
+ 'UCSR0A_FE0': '$10', # Framing Error
+ 'UCSR0A_DOR0': '$8', # Data overRun
+ 'UCSR0A_UPE0': '$4', # Parity Error
+ 'UCSR0A_U2X0': '$2', # Double the USART transmission
+ 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
+ 'UCSR0B' : '$c1', # USART Control and Status Regis
+ 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
+ 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
+ 'UCSR0B_UDRIE0': '$20', # USART Data register Empty Inte
+ 'UCSR0B_RXEN0': '$10', # Receiver Enable
+ 'UCSR0B_TXEN0': '$8', # Transmitter Enable
+ 'UCSR0B_UCSZ02': '$4', # Character Size
+ 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
+ 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
+ 'UCSR0C' : '$c2', # USART Control and Status Regis
+ 'UCSR0C_UMSEL0': '$c0', # USART Mode Select
+ 'UCSR0C_UPM0': '$30', # Parity Mode Bits
+ 'UCSR0C_USBS0': '$8', # Stop Bit Select
+ 'UCSR0C_UCSZ0': '$6', # Character Size
+ 'UCSR0C_UCPOL0': '$1', # Clock Polarity
+ 'UBRR0' : '$c4', # USART Baud Rate Register Byte
+
+# Module TWI
+ 'TWAMR' : '$bd', # TWI (Slave) Address Mask Regis
+ 'TWAMR_TWAM': '$fe', #
+ 'TWBR' : '$b8', # TWI Bit Rate register
+ 'TWCR' : '$bc', # TWI Control Register
+ 'TWCR_TWINT': '$80', # TWI Interrupt Flag
+ 'TWCR_TWEA': '$40', # TWI Enable Acknowledge Bit
+ 'TWCR_TWSTA': '$20', # TWI Start Condition Bit
+ 'TWCR_TWSTO': '$10', # TWI Stop Condition Bit
+ 'TWCR_TWWC': '$8', # TWI Write Collition Flag
+ 'TWCR_TWEN': '$4', # TWI Enable Bit
+ 'TWCR_TWIE': '$1', # TWI Interrupt Enable
+ 'TWSR' : '$b9', # TWI Status Register
+ 'TWSR_TWS': '$f8', # TWI Status
+ 'TWSR_TWPS': '$3', # TWI Prescaler
+ 'TWDR' : '$bb', # TWI Data register
+ 'TWAR' : '$ba', # TWI (Slave) Address register
+ 'TWAR_TWA': '$fe', # TWI (Slave) Address register B
+ 'TWAR_TWGCE': '$1', # TWI General Call Recognition E
+
+# Module SPI
+ 'SPCR' : '$4c', # SPI Control Register
+ 'SPCR_SPIE': '$80', # SPI Interrupt Enable
+ 'SPCR_SPE': '$40', # SPI Enable
+ 'SPCR_DORD': '$20', # Data Order
+ 'SPCR_MSTR': '$10', # Master/Slave Select
+ 'SPCR_CPOL': '$8', # Clock polarity
+ 'SPCR_CPHA': '$4', # Clock Phase
+ 'SPCR_SPR': '$3', # SPI Clock Rate Selects
+ 'SPSR' : '$4d', # SPI Status Register
+ 'SPSR_SPIF': '$80', # SPI Interrupt Flag
+ 'SPSR_WCOL': '$40', # Write Collision Flag
+ 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
+ 'SPDR' : '$4e', # SPI Data Register
+
+# Module PORTA
+ 'PORTA' : '$22', # Port A Data Register
+ 'DDRA' : '$21', # Port A Data Direction Register
+ 'PINA' : '$20', # Port A Input Pins
+
+# Module PORTB
+ 'PORTB' : '$25', # Port B Data Register
+ 'DDRB' : '$24', # Port B Data Direction Register
+ 'PINB' : '$23', # Port B Input Pins
+
+# Module PORTC
+ 'PORTC' : '$28', # Port C Data Register
+ 'DDRC' : '$27', # Port C Data Direction Register
+ 'PINC' : '$26', # Port C Input Pins
+
+# Module PORTD
+ 'PORTD' : '$2b', # Port D Data Register
+ 'DDRD' : '$2a', # Port D Data Direction Register
+ 'PIND' : '$29', # Port D Input Pins
+
+# Module PORTE
+ 'PORTE' : '$2e', # Data Register, Port E
+ 'DDRE' : '$2d', # Data Direction Register, Port
+ 'PINE' : '$2c', # Input Pins, Port E
+
+# Module PORTF
+ 'PORTF' : '$31', # Data Register, Port F
+ 'DDRF' : '$30', # Data Direction Register, Port
+ 'PINF' : '$2f', # Input Pins, Port F
+
+# Module PORTG
+ 'PORTG' : '$34', # Data Register, Port G
+ 'DDRG' : '$33', # Data Direction Register, Port
+ 'PING' : '$32', # Input Pins, Port G
+
+# Module PORTH
+ 'PORTH' : '$102', # PORT H Data Register
+ 'DDRH' : '$101', # PORT H Data Direction Register
+ 'PINH' : '$100', # PORT H Input Pins
+
+# Module PORTJ
+ 'PORTJ' : '$105', # PORT J Data Register
+ 'DDRJ' : '$104', # PORT J Data Direction Register
+ 'PINJ' : '$103', # PORT J Input Pins
+
+# Module PORTK
+ 'PORTK' : '$108', # PORT K Data Register
+ 'DDRK' : '$107', # PORT K Data Direction Register
+ 'PINK' : '$106', # PORT K Input Pins
+
+# Module PORTL
+ 'PORTL' : '$10b', # PORT L Data Register
+ 'DDRL' : '$10a', # PORT L Data Direction Register
+ 'PINL' : '$109', # PORT L Input Pins
+
+# Module TIMER_COUNTER_0
+ 'OCR0B' : '$48', # Timer/Counter0 Output Compare
+ 'OCR0A' : '$47', # Timer/Counter0 Output Compare
+ 'TCNT0' : '$46', # Timer/Counter0
+ 'TCCR0B' : '$45', # Timer/Counter Control Register
+ 'TCCR0B_FOC0A': '$80', # Force Output Compare A
+ 'TCCR0B_FOC0B': '$40', # Force Output Compare B
+ 'TCCR0B_WGM02': '$8', #
+ 'TCCR0B_CS0': '$7', # Clock Select
+ 'TCCR0A' : '$44', # Timer/Counter Control Registe
+ 'TCCR0A_COM0A': '$c0', # Compare Output Mode, Phase Cor
+ 'TCCR0A_COM0B': '$30', # Compare Output Mode, Fast PWm
+ 'TCCR0A_WGM0': '$3', # Waveform Generation Mode
+ 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
+ 'TIMSK0_OCIE0B': '$4', # Timer/Counter0 Output Compare
+ 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
+ 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
+ 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
+ 'TIFR0_OCF0B': '$4', # Timer/Counter0 Output Compare
+ 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
+ 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSRSYNC': '$1', # Prescaler Reset Timer/Counter1
+
+# Module TIMER_COUNTER_2
+ 'TIMSK2' : '$70', # Timer/Counter Interrupt Mask r
+ 'TIMSK2_OCIE2B': '$4', # Timer/Counter2 Output Compare
+ 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
+ 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
+ 'TIFR2' : '$37', # Timer/Counter Interrupt Flag R
+ 'TIFR2_OCF2B': '$4', # Output Compare Flag 2B
+ 'TIFR2_OCF2A': '$2', # Output Compare Flag 2A
+ 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
+ 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
+ 'TCCR2A_COM2A': '$c0', # Compare Output Mode bits
+ 'TCCR2A_COM2B': '$30', # Compare Output Mode bits
+ 'TCCR2A_WGM2': '$3', # Waveform Genration Mode
+ 'TCCR2B' : '$b1', # Timer/Counter2 Control Registe
+ 'TCCR2B_FOC2A': '$80', # Force Output Compare A
+ 'TCCR2B_FOC2B': '$40', # Force Output Compare B
+ 'TCCR2B_WGM22': '$8', # Waveform Generation Mode
+ 'TCCR2B_CS2': '$7', # Clock Select bits
+ 'TCNT2' : '$b2', # Timer/Counter2
+ 'OCR2B' : '$b4', # Timer/Counter2 Output Compare
+ 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
+ 'ASSR' : '$b6', # Asynchronous Status Register
+ 'ASSR_EXCLK': '$40', # Enable External Clock Input
+ 'ASSR_AS2': '$20', # Asynchronous Timer/Counter2
+ 'ASSR_TCN2UB': '$10', # Timer/Counter2 Update Busy
+ 'ASSR_OCR2AUB': '$8', # Output Compare Register2 Updat
+ 'ASSR_OCR2BUB': '$4', # Output Compare Register 2 Upda
+ 'ASSR_TCR2AUB': '$2', # Timer/Counter Control Register
+ 'ASSR_TCR2BUB': '$1', # Timer/Counter Control Register
+ 'GTCCR' : '$43', # General Timer Counter Control
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSRASY': '$2', # Prescaler Reset Timer/Counter2
+
+# Module WATCHDOG
+ 'WDTCSR' : '$60', # Watchdog Timer Control Registe
+ 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
+ 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
+ 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
+ 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
+ 'WDTCSR_WDE': '$8', # Watch Dog Enable
+
+# Module USART1
+ 'UDR1' : '$ce', # USART I/O Data Register
+ 'UCSR1A' : '$c8', # USART Control and Status Regis
+ 'UCSR1A_RXC1': '$80', # USART Receive Complete
+ 'UCSR1A_TXC1': '$40', # USART Transmitt Complete
+ 'UCSR1A_UDRE1': '$20', # USART Data Register Empty
+ 'UCSR1A_FE1': '$10', # Framing Error
+ 'UCSR1A_DOR1': '$8', # Data overRun
+ 'UCSR1A_UPE1': '$4', # Parity Error
+ 'UCSR1A_U2X1': '$2', # Double the USART transmission
+ 'UCSR1A_MPCM1': '$1', # Multi-processor Communication
+ 'UCSR1B' : '$c9', # USART Control and Status Regis
+ 'UCSR1B_RXCIE1': '$80', # RX Complete Interrupt Enable
+ 'UCSR1B_TXCIE1': '$40', # TX Complete Interrupt Enable
+ 'UCSR1B_UDRIE1': '$20', # USART Data register Empty Inte
+ 'UCSR1B_RXEN1': '$10', # Receiver Enable
+ 'UCSR1B_TXEN1': '$8', # Transmitter Enable
+ 'UCSR1B_UCSZ12': '$4', # Character Size
+ 'UCSR1B_RXB81': '$2', # Receive Data Bit 8
+ 'UCSR1B_TXB81': '$1', # Transmit Data Bit 8
+ 'UCSR1C' : '$ca', # USART Control and Status Regis
+ 'UCSR1C_UMSEL1': '$c0', # USART Mode Select
+ 'UCSR1C_UPM1': '$30', # Parity Mode Bits
+ 'UCSR1C_USBS1': '$8', # Stop Bit Select
+ 'UCSR1C_UCSZ1': '$6', # Character Size
+ 'UCSR1C_UCPOL1': '$1', # Clock Polarity
+ 'UBRR1' : '$cc', # USART Baud Rate Register Byte
+
+# Module EEPROM
+ 'EEAR' : '$41', # EEPROM Address Register Low By
+ 'EEDR' : '$40', # EEPROM Data Register
+ 'EECR' : '$3f', # EEPROM Control Register
+ 'EECR_EEPM': '$30', # EEPROM Programming Mode Bits
+ 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
+ 'EECR_EEMPE': '$4', # EEPROM Master Write Enable
+ 'EECR_EEPE': '$2', # EEPROM Write Enable
+ 'EECR_EERE': '$1', # EEPROM Read Enable
+
+# Module TIMER_COUNTER_5
+ 'TCCR5A' : '$120', # Timer/Counter5 Control Registe
+ 'TCCR5A_COM5A': '$c0', # Compare Output Mode 1A, bits
+ 'TCCR5A_COM5B': '$30', # Compare Output Mode 5B, bits
+ 'TCCR5A_COM5C': '$c', # Compare Output Mode 5C, bits
+ 'TCCR5A_WGM5': '$3', # Waveform Generation Mode
+ 'TCCR5B' : '$121', # Timer/Counter5 Control Registe
+ 'TCCR5B_ICNC5': '$80', # Input Capture 5 Noise Canceler
+ 'TCCR5B_ICES5': '$40', # Input Capture 5 Edge Select
+ 'TCCR5B_WGM5': '$18', # Waveform Generation Mode
+ 'TCCR5B_CS5': '$7', # Prescaler source of Timer/Coun
+ 'TCCR5C' : '$122', # Timer/Counter 5 Control Regist
+ 'TCCR5C_FOC5A': '$80', # Force Output Compare 5A
+ 'TCCR5C_FOC5B': '$40', # Force Output Compare 5B
+ 'TCCR5C_FOC5C': '$20', # Force Output Compare 5C
+ 'TCNT5' : '$124', # Timer/Counter5 Bytes
+ 'OCR5A' : '$128', # Timer/Counter5 Output Compare
+ 'OCR5B' : '$12a', # Timer/Counter5 Output Compare
+ 'OCR5C' : '$12c', # Timer/Counter5 Output Compare
+ 'ICR5' : '$126', # Timer/Counter5 Input Capture R
+ 'TIMSK5' : '$73', # Timer/Counter5 Interrupt Mask
+ 'TIMSK5_ICIE5': '$20', # Timer/Counter5 Input Capture I
+ 'TIMSK5_OCIE5C': '$8', # Timer/Counter5 Output Compare
+ 'TIMSK5_OCIE5B': '$4', # Timer/Counter5 Output Compare
+ 'TIMSK5_OCIE5A': '$2', # Timer/Counter5 Output Compare
+ 'TIMSK5_TOIE5': '$1', # Timer/Counter5 Overflow Interr
+ 'TIFR5' : '$3a', # Timer/Counter5 Interrupt Flag
+ 'TIFR5_ICF5': '$20', # Input Capture Flag 5
+ 'TIFR5_OCF5C': '$8', # Output Compare Flag 5C
+ 'TIFR5_OCF5B': '$4', # Output Compare Flag 5B
+ 'TIFR5_OCF5A': '$2', # Output Compare Flag 5A
+ 'TIFR5_TOV5': '$1', # Timer/Counter5 Overflow Flag
+
+# Module TIMER_COUNTER_4
+ 'TCCR4A' : '$a0', # Timer/Counter4 Control Registe
+ 'TCCR4A_COM4A': '$c0', # Compare Output Mode 1A, bits
+ 'TCCR4A_COM4B': '$30', # Compare Output Mode 4B, bits
+ 'TCCR4A_COM4C': '$c', # Compare Output Mode 4C, bits
+ 'TCCR4A_WGM4': '$3', # Waveform Generation Mode
+ 'TCCR4B' : '$a1', # Timer/Counter4 Control Registe
+ 'TCCR4B_ICNC4': '$80', # Input Capture 4 Noise Canceler
+ 'TCCR4B_ICES4': '$40', # Input Capture 4 Edge Select
+ 'TCCR4B_WGM4': '$18', # Waveform Generation Mode
+ 'TCCR4B_CS4': '$7', # Prescaler source of Timer/Coun
+ 'TCCR4C' : '$a2', # Timer/Counter 4 Control Regist
+ 'TCCR4C_FOC4A': '$80', # Force Output Compare 4A
+ 'TCCR4C_FOC4B': '$40', # Force Output Compare 4B
+ 'TCCR4C_FOC4C': '$20', # Force Output Compare 4C
+ 'TCNT4' : '$a4', # Timer/Counter4 Bytes
+ 'OCR4A' : '$a8', # Timer/Counter4 Output Compare
+ 'OCR4B' : '$aa', # Timer/Counter4 Output Compare
+ 'OCR4C' : '$ac', # Timer/Counter4 Output Compare
+ 'ICR4' : '$a6', # Timer/Counter4 Input Capture R
+ 'TIMSK4' : '$72', # Timer/Counter4 Interrupt Mask
+ 'TIMSK4_ICIE4': '$20', # Timer/Counter4 Input Capture I
+ 'TIMSK4_OCIE4C': '$8', # Timer/Counter4 Output Compare
+ 'TIMSK4_OCIE4B': '$4', # Timer/Counter4 Output Compare
+ 'TIMSK4_OCIE4A': '$2', # Timer/Counter4 Output Compare
+ 'TIMSK4_TOIE4': '$1', # Timer/Counter4 Overflow Interr
+ 'TIFR4' : '$39', # Timer/Counter4 Interrupt Flag
+ 'TIFR4_ICF4': '$20', # Input Capture Flag 4
+ 'TIFR4_OCF4C': '$8', # Output Compare Flag 4C
+ 'TIFR4_OCF4B': '$4', # Output Compare Flag 4B
+ 'TIFR4_OCF4A': '$2', # Output Compare Flag 4A
+ 'TIFR4_TOV4': '$1', # Timer/Counter4 Overflow Flag
+
+# Module TIMER_COUNTER_3
+ 'TCCR3A' : '$90', # Timer/Counter3 Control Registe
+ 'TCCR3A_COM3A': '$c0', # Compare Output Mode 1A, bits
+ 'TCCR3A_COM3B': '$30', # Compare Output Mode 3B, bits
+ 'TCCR3A_COM3C': '$c', # Compare Output Mode 3C, bits
+ 'TCCR3A_WGM3': '$3', # Waveform Generation Mode
+ 'TCCR3B' : '$91', # Timer/Counter3 Control Registe
+ 'TCCR3B_ICNC3': '$80', # Input Capture 3 Noise Canceler
+ 'TCCR3B_ICES3': '$40', # Input Capture 3 Edge Select
+ 'TCCR3B_WGM3': '$18', # Waveform Generation Mode
+ 'TCCR3B_CS3': '$7', # Prescaler source of Timer/Coun
+ 'TCCR3C' : '$92', # Timer/Counter 3 Control Regist
+ 'TCCR3C_FOC3A': '$80', # Force Output Compare 3A
+ 'TCCR3C_FOC3B': '$40', # Force Output Compare 3B
+ 'TCCR3C_FOC3C': '$20', # Force Output Compare 3C
+ 'TCNT3' : '$94', # Timer/Counter3 Bytes
+ 'OCR3A' : '$98', # Timer/Counter3 Output Compare
+ 'OCR3B' : '$9a', # Timer/Counter3 Output Compare
+ 'OCR3C' : '$9c', # Timer/Counter3 Output Compare
+ 'ICR3' : '$96', # Timer/Counter3 Input Capture R
+ 'TIMSK3' : '$71', # Timer/Counter3 Interrupt Mask
+ 'TIMSK3_ICIE3': '$20', # Timer/Counter3 Input Capture I
+ 'TIMSK3_OCIE3C': '$8', # Timer/Counter3 Output Compare
+ 'TIMSK3_OCIE3B': '$4', # Timer/Counter3 Output Compare
+ 'TIMSK3_OCIE3A': '$2', # Timer/Counter3 Output Compare
+ 'TIMSK3_TOIE3': '$1', # Timer/Counter3 Overflow Interr
+ 'TIFR3' : '$38', # Timer/Counter3 Interrupt Flag
+ 'TIFR3_ICF3': '$20', # Input Capture Flag 3
+ 'TIFR3_OCF3C': '$8', # Output Compare Flag 3C
+ 'TIFR3_OCF3B': '$4', # Output Compare Flag 3B
+ 'TIFR3_OCF3A': '$2', # Output Compare Flag 3A
+ 'TIFR3_TOV3': '$1', # Timer/Counter3 Overflow Flag
+
+# Module TIMER_COUNTER_1
+ 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
+ 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
+ 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
+ 'TCCR1A_COM1C': '$c', # Compare Output Mode 1C, bits
+ 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
+ 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
+ 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
+ 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
+ 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
+ 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
+ 'TCCR1C' : '$82', # Timer/Counter 1 Control Regist
+ 'TCCR1C_FOC1A': '$80', # Force Output Compare 1A
+ 'TCCR1C_FOC1B': '$40', # Force Output Compare 1B
+ 'TCCR1C_FOC1C': '$20', # Force Output Compare 1C
+ 'TCNT1' : '$84', # Timer/Counter1 Bytes
+ 'OCR1A' : '$88', # Timer/Counter1 Output Compare
+ 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
+ 'OCR1C' : '$8c', # Timer/Counter1 Output Compare
+ 'ICR1' : '$86', # Timer/Counter1 Input Capture R
+ 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
+ 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
+ 'TIMSK1_OCIE1C': '$8', # Timer/Counter1 Output Compare
+ 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
+ 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
+ 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
+ 'TIFR1' : '$36', # Timer/Counter1 Interrupt Flag
+ 'TIFR1_ICF1': '$20', # Input Capture Flag 1
+ 'TIFR1_OCF1C': '$8', # Output Compare Flag 1C
+ 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
+ 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
+ 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
+
+# Module JTAG
+ 'OCDR' : '$51', # On-Chip Debug Related Register
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_JTD': '$80', # JTAG Interface Disable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+
+# Module EXTERNAL_INTERRUPT
+ 'EICRA' : '$69', # External Interrupt Control Reg
+ 'EICRA_ISC3': '$c0', # External Interrupt Sense Contr
+ 'EICRA_ISC2': '$30', # External Interrupt Sense Contr
+ 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
+ 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
+ 'EICRB' : '$6a', # External Interrupt Control Reg
+ 'EICRB_ISC7': '$c0', # External Interrupt 7-4 Sense C
+ 'EICRB_ISC6': '$30', # External Interrupt 7-4 Sense C
+ 'EICRB_ISC5': '$c', # External Interrupt 7-4 Sense C
+ 'EICRB_ISC4': '$3', # External Interrupt 7-4 Sense C
+ 'EIMSK' : '$3d', # External Interrupt Mask Regist
+ 'EIMSK_INT': '$ff', # External Interrupt Request 7 E
+ 'EIFR' : '$3c', # External Interrupt Flag Regist
+ 'EIFR_INTF': '$ff', # External Interrupt Flags
+ 'PCMSK2' : '$6d', # Pin Change Mask Register 2
+ 'PCMSK1' : '$6c', # Pin Change Mask Register 1
+ 'PCMSK0' : '$6b', # Pin Change Mask Register 0
+ 'PCIFR' : '$3b', # Pin Change Interrupt Flag Regi
+ 'PCIFR_PCIF': '$7', # Pin Change Interrupt Flags
+ 'PCICR' : '$68', # Pin Change Interrupt Control R
+ 'PCICR_PCIE': '$7', # Pin Change Interrupt Enables
+
+# Module CPU
+ 'SREG' : '$5f', # Status Register
+ 'SREG_I': '$80', # Global Interrupt Enable
+ 'SREG_T': '$40', # Bit Copy Storage
+ 'SREG_H': '$20', # Half Carry Flag
+ 'SREG_S': '$10', # Sign Bit
+ 'SREG_V': '$8', # Two's Complement Overflow Flag
+ 'SREG_N': '$4', # Negative Flag
+ 'SREG_Z': '$2', # Zero Flag
+ 'SREG_C': '$1', # Carry Flag
+ 'SP' : '$5d', # Stack Pointer
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_JTD': '$80', # JTAG Interface Disable
+ 'MCUCR_PUD': '$10', # Pull-up disable
+ 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
+ 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+ 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
+ 'MCUSR_BORF': '$4', # Brown-out Reset Flag
+ 'MCUSR_EXTRF': '$2', # External Reset Flag
+ 'MCUSR_PORF': '$1', # Power-on reset flag
+ 'XMCRA' : '$74', # External Memory Control Regist
+ 'XMCRA_SRE': '$80', # External SRAM Enable
+ 'XMCRA_SRL': '$70', # Wait state page limit
+ 'XMCRA_SRW1': '$c', # Wait state select bit upper pa
+ 'XMCRA_SRW0': '$3', # Wait state select bit lower pa
+ 'XMCRB' : '$75', # External Memory Control Regist
+ 'XMCRB_XMBK': '$80', # External Memory Bus Keeper Ena
+ 'XMCRB_XMM': '$7', # External Memory High Mask
+ 'OSCCAL' : '$66', # Oscillator Calibration Value
+ 'CLKPR' : '$61', #
+ 'CLKPR_CLKPCE': '$80', #
+ 'CLKPR_CLKPS': '$f', #
+ 'SMCR' : '$53', # Sleep Mode Control Register
+ 'SMCR_SM': '$e', # Sleep Mode Select bits
+ 'SMCR_SE': '$1', # Sleep Enable
+ 'EIND' : '$5c', # Extended Indirect Register
+ 'GPIOR2' : '$4b', # General Purpose IO Register 2
+ 'GPIOR2_GPIOR': '$ff', # General Purpose IO Register 2
+ 'GPIOR1' : '$4a', # General Purpose IO Register 1
+ 'GPIOR1_GPIOR': '$ff', # General Purpose IO Register 1
+ 'GPIOR0' : '$3e', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR07': '$80', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR06': '$40', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR05': '$20', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR04': '$10', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR03': '$8', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR02': '$4', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR01': '$2', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR00': '$1', # General Purpose IO Register 0
+ 'PRR1' : '$65', # Power Reduction Register1
+ 'PRR1_PRTIM5': '$20', # Power Reduction Timer/Counter5
+ 'PRR1_PRTIM4': '$10', # Power Reduction Timer/Counter4
+ 'PRR1_PRTIM3': '$8', # Power Reduction Timer/Counter3
+ 'PRR1_PRUSART': '$7', # Power Reduction USART3
+ 'PRR0' : '$64', # Power Reduction Register0
+ 'PRR0_PRTWI': '$80', # Power Reduction TWI
+ 'PRR0_PRTIM2': '$40', # Power Reduction Timer/Counter2
+ 'PRR0_PRTIM0': '$20', # Power Reduction Timer/Counter0
+ 'PRR0_PRTIM1': '$8', # Power Reduction Timer/Counter1
+ 'PRR0_PRSPI': '$4', # Power Reduction Serial Periphe
+ 'PRR0_PRUSART0': '$2', # Power Reduction USART
+ 'PRR0_PRADC': '$1', # Power Reduction ADC
+
+# Module AD_CONVERTER
+ 'ADMUX' : '$7c', # The ADC multiplexer Selection
+ 'ADMUX_REFS': '$c0', # Reference Selection Bits
+ 'ADMUX_ADLAR': '$20', # Left Adjust Result
+ 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
+ 'ADC' : '$78', # ADC Data Register Bytes
+ 'ADCSRA' : '$7a', # The ADC Control and Status reg
+ 'ADCSRA_ADEN': '$80', # ADC Enable
+ 'ADCSRA_ADSC': '$40', # ADC Start Conversion
+ 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
+ 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
+ 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
+ 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
+ 'ADCSRB' : '$7b', # The ADC Control and Status reg
+ 'ADCSRB_ACME': '$40', #
+ 'ADCSRB_MUX5': '$8', # Analog Channel and Gain Select
+ 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Source bits
+ 'DIDR2' : '$7d', # Digital Input Disable Register
+ 'DIDR2_ADC15D': '$80', #
+ 'DIDR2_ADC14D': '$40', #
+ 'DIDR2_ADC13D': '$20', #
+ 'DIDR2_ADC12D': '$10', #
+ 'DIDR2_ADC11D': '$8', #
+ 'DIDR2_ADC10D': '$4', #
+ 'DIDR2_ADC9D': '$2', #
+ 'DIDR2_ADC8D': '$1', #
+ 'DIDR0' : '$7e', # Digital Input Disable Register
+ 'DIDR0_ADC7D': '$80', #
+ 'DIDR0_ADC6D': '$40', #
+ 'DIDR0_ADC5D': '$20', #
+ 'DIDR0_ADC4D': '$10', #
+ 'DIDR0_ADC3D': '$8', #
+ 'DIDR0_ADC2D': '$4', #
+ 'DIDR0_ADC1D': '$2', #
+ 'DIDR0_ADC0D': '$1', #
+
+# Module BOOT_LOAD
+ 'SPMCSR' : '$57', # Store Program Memory Control R
+ 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
+ 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
+ 'SPMCSR_SIGRD': '$20', # Signature Row Read
+ 'SPMCSR_RWWSRE': '$10', # Read While Write section read
+ 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
+ 'SPMCSR_PGWRT': '$4', # Page Write
+ 'SPMCSR_PGERS': '$2', # Page Erase
+ 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
+
+# Module USART2
+ 'UDR2' : '$d6', # USART I/O Data Register
+ 'UCSR2A' : '$d0', # USART Control and Status Regis
+ 'UCSR2A_RXC2': '$80', # USART Receive Complete
+ 'UCSR2A_TXC2': '$40', # USART Transmitt Complete
+ 'UCSR2A_UDRE2': '$20', # USART Data Register Empty
+ 'UCSR2A_FE2': '$10', # Framing Error
+ 'UCSR2A_DOR2': '$8', # Data overRun
+ 'UCSR2A_UPE2': '$4', # Parity Error
+ 'UCSR2A_U2X2': '$2', # Double the USART transmission
+ 'UCSR2A_MPCM2': '$1', # Multi-processor Communication
+ 'UCSR2B' : '$d1', # USART Control and Status Regis
+ 'UCSR2B_RXCIE2': '$80', # RX Complete Interrupt Enable
+ 'UCSR2B_TXCIE2': '$40', # TX Complete Interrupt Enable
+ 'UCSR2B_UDRIE2': '$20', # USART Data register Empty Inte
+ 'UCSR2B_RXEN2': '$10', # Receiver Enable
+ 'UCSR2B_TXEN2': '$8', # Transmitter Enable
+ 'UCSR2B_UCSZ22': '$4', # Character Size
+ 'UCSR2B_RXB82': '$2', # Receive Data Bit 8
+ 'UCSR2B_TXB82': '$1', # Transmit Data Bit 8
+ 'UCSR2C' : '$d2', # USART Control and Status Regis
+ 'UCSR2C_UMSEL2': '$c0', # USART Mode Select
+ 'UCSR2C_UPM2': '$30', # Parity Mode Bits
+ 'UCSR2C_USBS2': '$8', # Stop Bit Select
+ 'UCSR2C_UCSZ2': '$6', # Character Size
+ 'UCSR2C_UCPOL2': '$1', # Clock Polarity
+ 'UBRR2' : '$d4', # USART Baud Rate Register Byte
+
+# Module USART3
+ 'UDR3' : '$136', # USART I/O Data Register
+ 'UCSR3A' : '$130', # USART Control and Status Regis
+ 'UCSR3A_RXC3': '$80', # USART Receive Complete
+ 'UCSR3A_TXC3': '$40', # USART Transmitt Complete
+ 'UCSR3A_UDRE3': '$20', # USART Data Register Empty
+ 'UCSR3A_FE3': '$10', # Framing Error
+ 'UCSR3A_DOR3': '$8', # Data overRun
+ 'UCSR3A_UPE3': '$4', # Parity Error
+ 'UCSR3A_U2X3': '$2', # Double the USART transmission
+ 'UCSR3A_MPCM3': '$1', # Multi-processor Communication
+ 'UCSR3B' : '$131', # USART Control and Status Regis
+ 'UCSR3B_RXCIE3': '$80', # RX Complete Interrupt Enable
+ 'UCSR3B_TXCIE3': '$40', # TX Complete Interrupt Enable
+ 'UCSR3B_UDRIE3': '$20', # USART Data register Empty Inte
+ 'UCSR3B_RXEN3': '$10', # Receiver Enable
+ 'UCSR3B_TXEN3': '$8', # Transmitter Enable
+ 'UCSR3B_UCSZ32': '$4', # Character Size
+ 'UCSR3B_RXB83': '$2', # Receive Data Bit 8
+ 'UCSR3B_TXB83': '$1', # Transmit Data Bit 8
+ 'UCSR3C' : '$132', # USART Control and Status Regis
+ 'UCSR3C_UMSEL3': '$c0', # USART Mode Select
+ 'UCSR3C_UPM3': '$30', # Parity Mode Bits
+ 'UCSR3C_USBS3': '$8', # Stop Bit Select
+ 'UCSR3C_UCSZ3': '$6', # Character Size
+ 'UCSR3C_UCPOL3': '$1', # Clock Polarity
+ 'UBRR3' : '$134', # USART Baud Rate Register Byte
+
+ '__amforth_dummy':'0'
+}
diff --git a/amforth-6.5/avr8/devices/atmega640/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega640/words/no-jtag.asm
new file mode 100644
index 0000000..352a4bb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega640/words/no-jtag.asm
@@ -0,0 +1,14 @@
+; ( -- )
+; ( -- )
+; MCU
+; disable jtag at runtime
+VE_NOJTAG:
+ .dw $FF05
+ .db "-jtag",0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOJTAG
+XT_NOJTAG:
+ .dw PFA_NOJTAG
+PFA_NOJTAG:
+
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega640/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega640/words/no-wdt.asm
new file mode 100644
index 0000000..ff6ddd1
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega640/words/no-wdt.asm
@@ -0,0 +1,34 @@
+; ( -- )
+; MCU
+; disable watch dog timer at runtime
+VE_NOWDT:
+ .dw $ff04
+ .db "-wdt"
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOWDT
+XT_NOWDT:
+ .dw PFA_NOWDT
+PFA_NOWDT:
+
+ in temp1,SREG
+ push temp1
+ ; Turn always off global interrupt.
+ cli
+ ; Reset Watchdog Timer
+ wdr
+ ; Clear WDRF in MCUSR
+ in temp1, MCUSR
+ andi temp1, (0xff & (0<<WDRF))
+ out MCUSR, temp1
+ ; Write logical one to WDCE and WDE
+ ; Keep old prescaler setting to prevent unintentional time-out
+ in_ temp1, WDTCSR
+ ori temp1, (1<<WDCE) | (1<<WDE)
+ out_ WDTCSR, temp1
+ ; Turn off WDT
+ ldi temp1, (0<<WDE)
+ out_ WDTCSR, temp1
+ ; restore status register
+ pop temp1
+ out SREG,temp1
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega640/words/sleep.asm b/amforth-6.5/avr8/devices/atmega640/words/sleep.asm
new file mode 100644
index 0000000..256249c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega640/words/sleep.asm
@@ -0,0 +1,19 @@
+; ( mode -- )
+; MCU
+; put the controller into the specified sleep mode
+VE_SLEEP:
+ .dw $ff05
+ .db "sleep", 0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_SLEEP
+XT_SLEEP:
+ .dw PFA_SLEEP
+PFA_SLEEP:
+ andi tosl, 7 ; leave only legal mode bits
+ lsl tosl ; move to correct location (bits 3-1)
+ ori tosl, 1 ; set the SE bit
+ out_ SMCR, tosl ; set the sleep config
+ sleep ; nighty-night
+ out_ SMCR, zerol ; 0 protects against accidental sleeps
+ loadtos ; pop argument from stack
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega644/atmega644.frt b/amforth-6.5/avr8/devices/atmega644/atmega644.frt
new file mode 100644
index 0000000..65858f6
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega644/atmega644.frt
@@ -0,0 +1,316 @@
+\ Partname: ATmega644
+\ generated automatically
+
+\ ANALOG_COMPARATOR
+&123 constant ADCSRB \ ADC Control and Status Register B
+ $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer Enable
+&80 constant ACSR \ Analog Comparator Control And Status Register
+ $80 constant ACSR_ACD \ Analog Comparator Disable
+ $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
+ $20 constant ACSR_ACO \ Analog Compare Output
+ $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
+ $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
+ $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
+ $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
+&127 constant DIDR1 \ Digital Input Disable Register 1
+ $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
+ $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
+\ USART0
+&198 constant UDR0 \ USART I/O Data Register
+&192 constant UCSR0A \ USART Control and Status Register A
+ $80 constant UCSR0A_RXC0 \ USART Receive Complete
+ $40 constant UCSR0A_TXC0 \ USART Transmitt Complete
+ $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
+ $10 constant UCSR0A_FE0 \ Framing Error
+ $08 constant UCSR0A_DOR0 \ Data overRun
+ $04 constant UCSR0A_UPE0 \ Parity Error
+ $02 constant UCSR0A_U2X0 \ Double the USART transmission speed
+ $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
+&193 constant UCSR0B \ USART Control and Status Register B
+ $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
+ $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
+ $20 constant UCSR0B_UDRIE0 \ USART Data register Empty Interrupt Enable
+ $10 constant UCSR0B_RXEN0 \ Receiver Enable
+ $08 constant UCSR0B_TXEN0 \ Transmitter Enable
+ $04 constant UCSR0B_UCSZ02 \ Character Size
+ $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
+ $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
+&194 constant UCSR0C \ USART Control and Status Register C
+ $C0 constant UCSR0C_UMSEL0 \ USART Mode Select
+ $30 constant UCSR0C_UPM0 \ Parity Mode Bits
+ $08 constant UCSR0C_USBS0 \ Stop Bit Select
+ $06 constant UCSR0C_UCSZ0 \ Character Size
+ $01 constant UCSR0C_UCPOL0 \ Clock Polarity
+&196 constant UBRR0 \ USART Baud Rate Register Bytes
+\ PORTA
+&34 constant PORTA \ Port A Data Register
+&33 constant DDRA \ Port A Data Direction Register
+&32 constant PINA \ Port A Input Pins
+\ PORTB
+&37 constant PORTB \ Port B Data Register
+&36 constant DDRB \ Port B Data Direction Register
+&35 constant PINB \ Port B Input Pins
+\ PORTC
+&40 constant PORTC \ Port C Data Register
+&39 constant DDRC \ Port C Data Direction Register
+&38 constant PINC \ Port C Input Pins
+\ PORTD
+&43 constant PORTD \ Port D Data Register
+&42 constant DDRD \ Port D Data Direction Register
+&41 constant PIND \ Port D Input Pins
+\ TIMER_COUNTER_0
+&72 constant OCR0B \ Timer/Counter0 Output Compare Register
+&71 constant OCR0A \ Timer/Counter0 Output Compare Register
+&70 constant TCNT0 \ Timer/Counter0
+&69 constant TCCR0B \ Timer/Counter Control Register B
+ $80 constant TCCR0B_FOC0A \ Force Output Compare A
+ $40 constant TCCR0B_FOC0B \ Force Output Compare B
+ $08 constant TCCR0B_WGM02 \
+ $07 constant TCCR0B_CS0 \ Clock Select
+&68 constant TCCR0A \ Timer/Counter Control Register A
+ $C0 constant TCCR0A_COM0A \ Compare Output Mode, Phase Correct PWM Mode
+ $30 constant TCCR0A_COM0B \ Compare Output Mode, Fast PWm
+ $03 constant TCCR0A_WGM0 \ Waveform Generation Mode
+&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
+ $04 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare Match B Interrupt Enable
+ $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match A Interrupt Enable
+ $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
+&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
+ $04 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare Flag 0B
+ $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0A
+ $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
+&67 constant GTCCR \ General Timer/Counter Control Register
+ $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
+ $01 constant GTCCR_PSRSYNC \ Prescaler Reset Timer/Counter1 and Timer/Counter0
+\ TIMER_COUNTER_2
+&112 constant TIMSK2 \ Timer/Counter Interrupt Mask register
+ $04 constant TIMSK2_OCIE2B \ Timer/Counter2 Output Compare Match B Interrupt Enable
+ $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match A Interrupt Enable
+ $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
+&55 constant TIFR2 \ Timer/Counter Interrupt Flag Register
+ $04 constant TIFR2_OCF2B \ Output Compare Flag 2B
+ $02 constant TIFR2_OCF2A \ Output Compare Flag 2A
+ $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
+&176 constant TCCR2A \ Timer/Counter2 Control Register A
+ $C0 constant TCCR2A_COM2A \ Compare Output Mode bits
+ $30 constant TCCR2A_COM2B \ Compare Output Mode bits
+ $03 constant TCCR2A_WGM2 \ Waveform Genration Mode
+&177 constant TCCR2B \ Timer/Counter2 Control Register B
+ $80 constant TCCR2B_FOC2A \ Force Output Compare A
+ $40 constant TCCR2B_FOC2B \ Force Output Compare B
+ $08 constant TCCR2B_WGM22 \ Waveform Generation Mode
+ $07 constant TCCR2B_CS2 \ Clock Select bits
+&178 constant TCNT2 \ Timer/Counter2
+&180 constant OCR2B \ Timer/Counter2 Output Compare Register B
+&179 constant OCR2A \ Timer/Counter2 Output Compare Register A
+&182 constant ASSR \ Asynchronous Status Register
+ $40 constant ASSR_EXCLK \ Enable External Clock Input
+ $20 constant ASSR_AS2 \ Asynchronous Timer/Counter2
+ $10 constant ASSR_TCN2UB \ Timer/Counter2 Update Busy
+ $08 constant ASSR_OCR2AUB \ Output Compare Register2 Update Busy
+ $04 constant ASSR_OCR2BUB \ Output Compare Register 2 Update Busy
+ $02 constant ASSR_TCR2AUB \ Timer/Counter Control Register2 Update Busy
+ $01 constant ASSR_TCR2BUB \ Timer/Counter Control Register2 Update Busy
+\ WATCHDOG
+&96 constant WDTCSR \ Watchdog Timer Control Register
+ $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Flag
+ $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Enable
+ $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
+ $10 constant WDTCSR_WDCE \ Watchdog Change Enable
+ $08 constant WDTCSR_WDE \ Watch Dog Enable
+\ JTAG
+&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
+&85 constant MCUCR \ MCU Control Register
+ $80 constant MCUCR_JTD \ JTAG Interface Disable
+&84 constant MCUSR \ MCU Status Register
+ $10 constant MCUSR_JTRF \ JTAG Reset Flag
+\ BOOT_LOAD
+&87 constant SPMCSR \ Store Program Memory Control Register
+ $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
+ $20 constant SPMCSR_SIGRD \ Signature Row Read
+ $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
+ $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
+ $04 constant SPMCSR_PGWRT \ Page Write
+ $02 constant SPMCSR_PGERS \ Page Erase
+ $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
+\ EXTERNAL_INTERRUPT
+&105 constant EICRA \ External Interrupt Control Register A
+ $30 constant EICRA_ISC2 \ External Interrupt Sense Control Bit
+ $0C constant EICRA_ISC1 \ External Interrupt Sense Control Bit
+ $03 constant EICRA_ISC0 \ External Interrupt Sense Control Bit
+&61 constant EIMSK \ External Interrupt Mask Register
+ $07 constant EIMSK_INT \ External Interrupt Request 2 Enable
+&60 constant EIFR \ External Interrupt Flag Register
+ $07 constant EIFR_INTF \ External Interrupt Flags
+&115 constant PCMSK3 \ Pin Change Mask Register 3
+ $FF constant PCMSK3_PCINT \ Pin Change Enable Masks
+&109 constant PCMSK2 \ Pin Change Mask Register 2
+ $FF constant PCMSK2_PCINT \ Pin Change Enable Masks
+&108 constant PCMSK1 \ Pin Change Mask Register 1
+ $FF constant PCMSK1_PCINT \ Pin Change Enable Masks
+&107 constant PCMSK0 \ Pin Change Mask Register 0
+ $FF constant PCMSK0_PCINT \ Pin Change Enable Masks
+&59 constant PCIFR \ Pin Change Interrupt Flag Register
+ $0F constant PCIFR_PCIF \ Pin Change Interrupt Flags
+&104 constant PCICR \ Pin Change Interrupt Control Register
+ $0F constant PCICR_PCIE \ Pin Change Interrupt Enables
+\ AD_CONVERTER
+&124 constant ADMUX \ The ADC multiplexer Selection Register
+ $C0 constant ADMUX_REFS \ Reference Selection Bits
+ $20 constant ADMUX_ADLAR \ Left Adjust Result
+ $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
+&120 constant ADC \ ADC Data Register Bytes
+&122 constant ADCSRA \ The ADC Control and Status register A
+ $80 constant ADCSRA_ADEN \ ADC Enable
+ $40 constant ADCSRA_ADSC \ ADC Start Conversion
+ $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
+ $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
+ $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
+ $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
+&126 constant DIDR0 \ Digital Input Disable Register
+ $80 constant DIDR0_ADC7D \
+ $40 constant DIDR0_ADC6D \
+ $20 constant DIDR0_ADC5D \
+ $10 constant DIDR0_ADC4D \
+ $08 constant DIDR0_ADC3D \
+ $04 constant DIDR0_ADC2D \
+ $02 constant DIDR0_ADC1D \
+ $01 constant DIDR0_ADC0D \
+\ TIMER_COUNTER_1
+&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
+ $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
+ $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
+ $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
+ $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
+&54 constant TIFR1 \ Timer/Counter Interrupt Flag register
+ $20 constant TIFR1_ICF1 \ Timer/Counter1 Input Capture Flag
+ $04 constant TIFR1_OCF1B \ Timer/Counter1 Output Compare B Match Flag
+ $02 constant TIFR1_OCF1A \ Timer/Counter1 Output Compare A Match Flag
+ $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
+&128 constant TCCR1A \ Timer/Counter1 Control Register A
+ $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
+ $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
+ $03 constant TCCR1A_WGM1 \ Pulse Width Modulator Select Bits
+&129 constant TCCR1B \ Timer/Counter1 Control Register B
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ $18 constant TCCR1B_WGM1 \ Waveform Generation Mode Bits
+ $07 constant TCCR1B_CS1 \ Clock Select1 bits
+&130 constant TCCR1C \ Timer/Counter1 Control Register C
+ $80 constant TCCR1C_FOC1A \ Force Output Compare for Channel A
+ $40 constant TCCR1C_FOC1B \ Force Output Compare for Channel B
+&132 constant TCNT1 \ Timer/Counter1 Bytes
+&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
+&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
+&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
+\ EEPROM
+&65 constant EEAR \ EEPROM Address Register Low Bytes
+&64 constant EEDR \ EEPROM Data Register
+&63 constant EECR \ EEPROM Control Register
+ $30 constant EECR_EEPM \ EEPROM Programming Mode Bits
+ $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
+ $04 constant EECR_EEMPE \ EEPROM Master Write Enable
+ $02 constant EECR_EEPE \ EEPROM Write Enable
+ $01 constant EECR_EERE \ EEPROM Read Enable
+\ TWI
+&189 constant TWAMR \ TWI (Slave) Address Mask Register
+ $FE constant TWAMR_TWAM \
+&184 constant TWBR \ TWI Bit Rate register
+&188 constant TWCR \ TWI Control Register
+ $80 constant TWCR_TWINT \ TWI Interrupt Flag
+ $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
+ $20 constant TWCR_TWSTA \ TWI Start Condition Bit
+ $10 constant TWCR_TWSTO \ TWI Stop Condition Bit
+ $08 constant TWCR_TWWC \ TWI Write Collition Flag
+ $04 constant TWCR_TWEN \ TWI Enable Bit
+ $01 constant TWCR_TWIE \ TWI Interrupt Enable
+&185 constant TWSR \ TWI Status Register
+ $F8 constant TWSR_TWS \ TWI Status
+ $03 constant TWSR_TWPS \ TWI Prescaler
+&187 constant TWDR \ TWI Data register
+&186 constant TWAR \ TWI (Slave) Address register
+ $FE constant TWAR_TWA \ TWI (Slave) Address register Bits
+ $01 constant TWAR_TWGCE \ TWI General Call Recognition Enable Bit
+\ SPI
+&78 constant SPDR \ SPI Data Register
+&77 constant SPSR \ SPI Status Register
+ $80 constant SPSR_SPIF \ SPI Interrupt Flag
+ $40 constant SPSR_WCOL \ Write Collision Flag
+ $01 constant SPSR_SPI2X \ Double SPI Speed Bit
+&76 constant SPCR \ SPI Control Register
+ $80 constant SPCR_SPIE \ SPI Interrupt Enable
+ $40 constant SPCR_SPE \ SPI Enable
+ $20 constant SPCR_DORD \ Data Order
+ $10 constant SPCR_MSTR \ Master/Slave Select
+ $08 constant SPCR_CPOL \ Clock polarity
+ $04 constant SPCR_CPHA \ Clock Phase
+ $03 constant SPCR_SPR \ SPI Clock Rate Selects
+\ CPU
+&95 constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ $08 constant SREG_V \ Two's Complement Overflow Flag
+ $04 constant SREG_N \ Negative Flag
+ $02 constant SREG_Z \ Zero Flag
+ $01 constant SREG_C \ Carry Flag
+&93 constant SP \ Stack Pointer
+&102 constant OSCCAL \ Oscillator Calibration Value
+&97 constant CLKPR \
+ $80 constant CLKPR_CLKPCE \
+ $0F constant CLKPR_CLKPS \
+&83 constant SMCR \ Sleep Mode Control Register
+ $0E constant SMCR_SM \ Sleep Mode Select bits
+ $01 constant SMCR_SE \ Sleep Enable
+&75 constant GPIOR2 \ General Purpose IO Register 2
+ $FF constant GPIOR2_GPIOR \ General Purpose IO Register 2 bis
+&74 constant GPIOR1 \ General Purpose IO Register 1
+ $FF constant GPIOR1_GPIOR \ General Purpose IO Register 1 bis
+&62 constant GPIOR0 \ General Purpose IO Register 0
+ $80 constant GPIOR0_GPIOR07 \ General Purpose IO Register 0 bit 7
+ $40 constant GPIOR0_GPIOR06 \ General Purpose IO Register 0 bit 6
+ $20 constant GPIOR0_GPIOR05 \ General Purpose IO Register 0 bit 5
+ $10 constant GPIOR0_GPIOR04 \ General Purpose IO Register 0 bit 4
+ $08 constant GPIOR0_GPIOR03 \ General Purpose IO Register 0 bit 3
+ $04 constant GPIOR0_GPIOR02 \ General Purpose IO Register 0 bit 2
+ $02 constant GPIOR0_GPIOR01 \ General Purpose IO Register 0 bit 1
+ $01 constant GPIOR0_GPIOR00 \ General Purpose IO Register 0 bit 0
+&100 constant PRR \ Power Reduction Register
+ $80 constant PRR_PRTWI \ Power Reduction TWI
+ $40 constant PRR_PRTIM2 \ Power Reduction Timer/Counter2
+ $20 constant PRR_PRTIM0 \ Power Reduction Timer/Counter0
+ $08 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
+ $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
+ $02 constant PRR_PRUSART0 \ Power Reduction USART
+ $01 constant PRR_PRADC \ Power Reduction ADC
+
+\ Interrupts
+&2 constant INT0Addr \ External Interrupt Request 0
+&4 constant INT1Addr \ External Interrupt Request 1
+&6 constant INT2Addr \ External Interrupt Request 2
+&8 constant PCINT0Addr \ Pin Change Interrupt Request 0
+&10 constant PCINT1Addr \ Pin Change Interrupt Request 1
+&12 constant PCINT2Addr \ Pin Change Interrupt Request 2
+&14 constant PCINT3Addr \ Pin Change Interrupt Request 3
+&16 constant WDTAddr \ Watchdog Time-out Interrupt
+&18 constant TIMER2_COMPAAddr \ Timer/Counter2 Compare Match A
+&20 constant TIMER2_COMPBAddr \ Timer/Counter2 Compare Match B
+&22 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
+&24 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+&26 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
+&28 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
+&30 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+&32 constant TIMER0_COMPAAddr \ Timer/Counter0 Compare Match A
+&34 constant TIMER0_COMPBAddr \ Timer/Counter0 Compare Match B
+&36 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
+&38 constant SPI__STCAddr \ SPI Serial Transfer Complete
+&40 constant USART0__RXAddr \ USART0, Rx Complete
+&42 constant USART0__UDREAddr \ USART0 Data register Empty
+&44 constant USART0__TXAddr \ USART0, Tx Complete
+&46 constant ANALOG_COMPAddr \ Analog Comparator
+&48 constant ADCAddr \ ADC Conversion Complete
+&50 constant EE_READYAddr \ EEPROM Ready
+&52 constant TWIAddr \ 2-wire Serial Interface
+&54 constant SPM_READYAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/atmega644/device.asm b/amforth-6.5/avr8/devices/atmega644/device.asm
new file mode 100644
index 0000000..c58fe56
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega644/device.asm
@@ -0,0 +1,113 @@
+; Partname: ATmega644
+; generated automatically, do not edit
+
+.nolist
+ .include "m644def.inc"
+.list
+
+.equ ramstart = 256
+.equ CELLSIZE = 2
+.macro readflashcell
+ lsl zl
+ rol zh
+ lpm @0, Z+
+ lpm @1, Z+
+.endmacro
+.macro writeflashcell
+ lsl zl
+ rol zh
+.endmacro
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_USART0 = 0
+.set WANT_PORTA = 0
+.set WANT_PORTB = 0
+.set WANT_PORTC = 0
+.set WANT_PORTD = 0
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_TIMER_COUNTER_2 = 0
+.set WANT_WATCHDOG = 0
+.set WANT_JTAG = 0
+.set WANT_BOOT_LOAD = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_AD_CONVERTER = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_EEPROM = 0
+.set WANT_TWI = 0
+.set WANT_SPI = 0
+.set WANT_CPU = 0
+.equ intvecsize = 2 ; please verify; flash size: 65536 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.org 2
+ rcall isr ; External Interrupt Request 0
+.org 4
+ rcall isr ; External Interrupt Request 1
+.org 6
+ rcall isr ; External Interrupt Request 2
+.org 8
+ rcall isr ; Pin Change Interrupt Request 0
+.org 10
+ rcall isr ; Pin Change Interrupt Request 1
+.org 12
+ rcall isr ; Pin Change Interrupt Request 2
+.org 14
+ rcall isr ; Pin Change Interrupt Request 3
+.org 16
+ rcall isr ; Watchdog Time-out Interrupt
+.org 18
+ rcall isr ; Timer/Counter2 Compare Match A
+.org 20
+ rcall isr ; Timer/Counter2 Compare Match B
+.org 22
+ rcall isr ; Timer/Counter2 Overflow
+.org 24
+ rcall isr ; Timer/Counter1 Capture Event
+.org 26
+ rcall isr ; Timer/Counter1 Compare Match A
+.org 28
+ rcall isr ; Timer/Counter1 Compare Match B
+.org 30
+ rcall isr ; Timer/Counter1 Overflow
+.org 32
+ rcall isr ; Timer/Counter0 Compare Match A
+.org 34
+ rcall isr ; Timer/Counter0 Compare Match B
+.org 36
+ rcall isr ; Timer/Counter0 Overflow
+.org 38
+ rcall isr ; SPI Serial Transfer Complete
+.org 40
+ rcall isr ; USART0, Rx Complete
+.org 42
+ rcall isr ; USART0 Data register Empty
+.org 44
+ rcall isr ; USART0, Tx Complete
+.org 46
+ rcall isr ; Analog Comparator
+.org 48
+ rcall isr ; ADC Conversion Complete
+.org 50
+ rcall isr ; EEPROM Ready
+.org 52
+ rcall isr ; 2-wire Serial Interface
+.org 54
+ rcall isr ; Store Program Memory Read
+.equ INTVECTORS = 28
+.nooverlap
+
+; compatability layer (maybe empty)
+
+; controller data area, environment query mcu-info
+mcu_info:
+mcu_ramsize:
+ .dw 4096
+mcu_eepromsize:
+ .dw 2048
+mcu_maxdp:
+ .dw 57344
+mcu_numints:
+ .dw 28
+mcu_name:
+ .dw 9
+ .db "ATmega644",0
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega644/device.inc b/amforth-6.5/avr8/devices/atmega644/device.inc
new file mode 100644
index 0000000..d28946f
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega644/device.inc
@@ -0,0 +1,1065 @@
+; Partname: ATmega644
+; generated automatically, no not edit
+
+.if WANT_ANALOG_COMPARATOR == 1
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Control and Status Register B
+VE_ADCSRB:
+ .dw $ff06
+ .db "ADCSRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRB
+XT_ADCSRB:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRB:
+ .dw 123
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Control And Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw 80
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 1
+VE_DIDR1:
+ .dw $ff05
+ .db "DIDR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR1
+XT_DIDR1:
+ .dw PFA_DOVARIABLE
+PFA_DIDR1:
+ .dw 127
+
+.endif
+.if WANT_USART0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR0:
+ .dw $ff04
+ .db "UDR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR0
+XT_UDR0:
+ .dw PFA_DOVARIABLE
+PFA_UDR0:
+ .dw 198
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR0A:
+ .dw $ff06
+ .db "UCSR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0A
+XT_UCSR0A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0A:
+ .dw 192
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR0B:
+ .dw $ff06
+ .db "UCSR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0B
+XT_UCSR0B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0B:
+ .dw 193
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR0C:
+ .dw $ff06
+ .db "UCSR0C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0C
+XT_UCSR0C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0C:
+ .dw 194
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Bytes
+VE_UBRR0:
+ .dw $ff05
+ .db "UBRR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR0
+XT_UBRR0:
+ .dw PFA_DOVARIABLE
+PFA_UBRR0:
+ .dw 196
+
+.endif
+.if WANT_PORTA == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Register
+VE_PORTA:
+ .dw $ff05
+ .db "PORTA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTA
+XT_PORTA:
+ .dw PFA_DOVARIABLE
+PFA_PORTA:
+ .dw 34
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Direction Register
+VE_DDRA:
+ .dw $ff04
+ .db "DDRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRA
+XT_DDRA:
+ .dw PFA_DOVARIABLE
+PFA_DDRA:
+ .dw 33
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Input Pins
+VE_PINA:
+ .dw $ff04
+ .db "PINA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINA
+XT_PINA:
+ .dw PFA_DOVARIABLE
+PFA_PINA:
+ .dw 32
+
+.endif
+.if WANT_PORTB == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw 37
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw 36
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw 35
+
+.endif
+.if WANT_PORTC == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Register
+VE_PORTC:
+ .dw $ff05
+ .db "PORTC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTC
+XT_PORTC:
+ .dw PFA_DOVARIABLE
+PFA_PORTC:
+ .dw 40
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Direction Register
+VE_DDRC:
+ .dw $ff04
+ .db "DDRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRC
+XT_DDRC:
+ .dw PFA_DOVARIABLE
+PFA_DDRC:
+ .dw 39
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Input Pins
+VE_PINC:
+ .dw $ff04
+ .db "PINC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINC
+XT_PINC:
+ .dw PFA_DOVARIABLE
+PFA_PINC:
+ .dw 38
+
+.endif
+.if WANT_PORTD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw 43
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw 42
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw 41
+
+.endif
+.if WANT_TIMER_COUNTER_0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0B:
+ .dw $ff05
+ .db "OCR0B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0B
+XT_OCR0B:
+ .dw PFA_DOVARIABLE
+PFA_OCR0B:
+ .dw 72
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0A:
+ .dw $ff05
+ .db "OCR0A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0A
+XT_OCR0A:
+ .dw PFA_DOVARIABLE
+PFA_OCR0A:
+ .dw 71
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw 70
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register B
+VE_TCCR0B:
+ .dw $ff06
+ .db "TCCR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0B
+XT_TCCR0B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0B:
+ .dw 69
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register A
+VE_TCCR0A:
+ .dw $ff06
+ .db "TCCR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0A
+XT_TCCR0A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0A:
+ .dw 68
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Mask Register
+VE_TIMSK0:
+ .dw $ff06
+ .db "TIMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK0
+XT_TIMSK0:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK0:
+ .dw 110
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Flag register
+VE_TIFR0:
+ .dw $ff05
+ .db "TIFR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR0
+XT_TIFR0:
+ .dw PFA_DOVARIABLE
+PFA_TIFR0:
+ .dw 53
+; ( -- addr ) System Constant
+; R( -- )
+; General Timer/Counter Control Register
+VE_GTCCR:
+ .dw $ff05
+ .db "GTCCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GTCCR
+XT_GTCCR:
+ .dw PFA_DOVARIABLE
+PFA_GTCCR:
+ .dw 67
+
+.endif
+.if WANT_TIMER_COUNTER_2 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Mask register
+VE_TIMSK2:
+ .dw $ff06
+ .db "TIMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK2
+XT_TIMSK2:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK2:
+ .dw 112
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Flag Register
+VE_TIFR2:
+ .dw $ff05
+ .db "TIFR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR2
+XT_TIFR2:
+ .dw PFA_DOVARIABLE
+PFA_TIFR2:
+ .dw 55
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register A
+VE_TCCR2A:
+ .dw $ff06
+ .db "TCCR2A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2A
+XT_TCCR2A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2A:
+ .dw 176
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register B
+VE_TCCR2B:
+ .dw $ff06
+ .db "TCCR2B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2B
+XT_TCCR2B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2B:
+ .dw 177
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2
+VE_TCNT2:
+ .dw $ff05
+ .db "TCNT2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT2
+XT_TCNT2:
+ .dw PFA_DOVARIABLE
+PFA_TCNT2:
+ .dw 178
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register B
+VE_OCR2B:
+ .dw $ff05
+ .db "OCR2B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2B
+XT_OCR2B:
+ .dw PFA_DOVARIABLE
+PFA_OCR2B:
+ .dw 180
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register A
+VE_OCR2A:
+ .dw $ff05
+ .db "OCR2A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2A
+XT_OCR2A:
+ .dw PFA_DOVARIABLE
+PFA_OCR2A:
+ .dw 179
+; ( -- addr ) System Constant
+; R( -- )
+; Asynchronous Status Register
+VE_ASSR:
+ .dw $ff04
+ .db "ASSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ASSR
+XT_ASSR:
+ .dw PFA_DOVARIABLE
+PFA_ASSR:
+ .dw 182
+
+.endif
+.if WANT_WATCHDOG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCSR:
+ .dw $ff06
+ .db "WDTCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCSR
+XT_WDTCSR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCSR:
+ .dw 96
+
+.endif
+.if WANT_JTAG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; On-Chip Debug Related Register in I/O Memory
+VE_OCDR:
+ .dw $ff04
+ .db "OCDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCDR
+XT_OCDR:
+ .dw PFA_DOVARIABLE
+PFA_OCDR:
+ .dw 81
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw 85
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Status Register
+VE_MCUSR:
+ .dw $ff05
+ .db "MCUSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUSR
+XT_MCUSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUSR:
+ .dw 84
+
+.endif
+.if WANT_BOOT_LOAD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control Register
+VE_SPMCSR:
+ .dw $ff06
+ .db "SPMCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCSR
+XT_SPMCSR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCSR:
+ .dw 87
+
+.endif
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register A
+VE_EICRA:
+ .dw $ff05
+ .db "EICRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRA
+XT_EICRA:
+ .dw PFA_DOVARIABLE
+PFA_EICRA:
+ .dw 105
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Mask Register
+VE_EIMSK:
+ .dw $ff05
+ .db "EIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIMSK
+XT_EIMSK:
+ .dw PFA_DOVARIABLE
+PFA_EIMSK:
+ .dw 61
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Flag Register
+VE_EIFR:
+ .dw $ff04
+ .db "EIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIFR
+XT_EIFR:
+ .dw PFA_DOVARIABLE
+PFA_EIFR:
+ .dw 60
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 3
+VE_PCMSK3:
+ .dw $ff06
+ .db "PCMSK3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK3
+XT_PCMSK3:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK3:
+ .dw 115
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 2
+VE_PCMSK2:
+ .dw $ff06
+ .db "PCMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK2
+XT_PCMSK2:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK2:
+ .dw 109
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 1
+VE_PCMSK1:
+ .dw $ff06
+ .db "PCMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK1
+XT_PCMSK1:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK1:
+ .dw 108
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 0
+VE_PCMSK0:
+ .dw $ff06
+ .db "PCMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK0
+XT_PCMSK0:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK0:
+ .dw 107
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Interrupt Flag Register
+VE_PCIFR:
+ .dw $ff05
+ .db "PCIFR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCIFR
+XT_PCIFR:
+ .dw PFA_DOVARIABLE
+PFA_PCIFR:
+ .dw 59
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Interrupt Control Register
+VE_PCICR:
+ .dw $ff05
+ .db "PCICR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCICR
+XT_PCICR:
+ .dw PFA_DOVARIABLE
+PFA_PCICR:
+ .dw 104
+
+.endif
+.if WANT_AD_CONVERTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC multiplexer Selection Register
+VE_ADMUX:
+ .dw $ff05
+ .db "ADMUX",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADMUX
+XT_ADMUX:
+ .dw PFA_DOVARIABLE
+PFA_ADMUX:
+ .dw 124
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register Bytes
+VE_ADC:
+ .dw $ff03
+ .db "ADC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADC
+XT_ADC:
+ .dw PFA_DOVARIABLE
+PFA_ADC:
+ .dw 120
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register A
+VE_ADCSRA:
+ .dw $ff06
+ .db "ADCSRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRA
+XT_ADCSRA:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRA:
+ .dw 122
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register
+VE_DIDR0:
+ .dw $ff05
+ .db "DIDR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR0
+XT_DIDR0:
+ .dw PFA_DOVARIABLE
+PFA_DIDR0:
+ .dw 126
+
+.endif
+.if WANT_TIMER_COUNTER_1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Mask Register
+VE_TIMSK1:
+ .dw $ff06
+ .db "TIMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK1
+XT_TIMSK1:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK1:
+ .dw 111
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Flag register
+VE_TIFR1:
+ .dw $ff05
+ .db "TIFR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR1
+XT_TIFR1:
+ .dw PFA_DOVARIABLE
+PFA_TIFR1:
+ .dw 54
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw 128
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw 129
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register C
+VE_TCCR1C:
+ .dw $ff06
+ .db "TCCR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1C
+XT_TCCR1C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1C:
+ .dw 130
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Bytes
+VE_TCNT1:
+ .dw $ff05
+ .db "TCNT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1
+XT_TCNT1:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1:
+ .dw 132
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register A Bytes
+VE_OCR1A:
+ .dw $ff05
+ .db "OCR1A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1A
+XT_OCR1A:
+ .dw PFA_DOVARIABLE
+PFA_OCR1A:
+ .dw 136
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register B Bytes
+VE_OCR1B:
+ .dw $ff05
+ .db "OCR1B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1B
+XT_OCR1B:
+ .dw PFA_DOVARIABLE
+PFA_OCR1B:
+ .dw 138
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Bytes
+VE_ICR1:
+ .dw $ff04
+ .db "ICR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1
+XT_ICR1:
+ .dw PFA_DOVARIABLE
+PFA_ICR1:
+ .dw 134
+
+.endif
+.if WANT_EEPROM == 1
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Address Register Low Bytes
+VE_EEAR:
+ .dw $ff04
+ .db "EEAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEAR
+XT_EEAR:
+ .dw PFA_DOVARIABLE
+PFA_EEAR:
+ .dw 65
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw 64
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw 63
+
+.endif
+.if WANT_TWI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; TWI (Slave) Address Mask Register
+VE_TWAMR:
+ .dw $ff05
+ .db "TWAMR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWAMR
+XT_TWAMR:
+ .dw PFA_DOVARIABLE
+PFA_TWAMR:
+ .dw 189
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Bit Rate register
+VE_TWBR:
+ .dw $ff04
+ .db "TWBR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWBR
+XT_TWBR:
+ .dw PFA_DOVARIABLE
+PFA_TWBR:
+ .dw 184
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Control Register
+VE_TWCR:
+ .dw $ff04
+ .db "TWCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWCR
+XT_TWCR:
+ .dw PFA_DOVARIABLE
+PFA_TWCR:
+ .dw 188
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Status Register
+VE_TWSR:
+ .dw $ff04
+ .db "TWSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWSR
+XT_TWSR:
+ .dw PFA_DOVARIABLE
+PFA_TWSR:
+ .dw 185
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Data register
+VE_TWDR:
+ .dw $ff04
+ .db "TWDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWDR
+XT_TWDR:
+ .dw PFA_DOVARIABLE
+PFA_TWDR:
+ .dw 187
+; ( -- addr ) System Constant
+; R( -- )
+; TWI (Slave) Address register
+VE_TWAR:
+ .dw $ff04
+ .db "TWAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWAR
+XT_TWAR:
+ .dw PFA_DOVARIABLE
+PFA_TWAR:
+ .dw 186
+
+.endif
+.if WANT_SPI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR:
+ .dw $ff04
+ .db "SPDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR
+XT_SPDR:
+ .dw PFA_DOVARIABLE
+PFA_SPDR:
+ .dw 78
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR:
+ .dw $ff04
+ .db "SPSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR
+XT_SPSR:
+ .dw PFA_DOVARIABLE
+PFA_SPSR:
+ .dw 77
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR:
+ .dw $ff04
+ .db "SPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR
+XT_SPCR:
+ .dw PFA_DOVARIABLE
+PFA_SPCR:
+ .dw 76
+
+.endif
+.if WANT_CPU == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw 95
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer
+VE_SP:
+ .dw $ff02
+ .db "SP"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SP
+XT_SP:
+ .dw PFA_DOVARIABLE
+PFA_SP:
+ .dw 93
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Calibration Value
+VE_OSCCAL:
+ .dw $ff06
+ .db "OSCCAL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSCCAL
+XT_OSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_OSCCAL:
+ .dw 102
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_CLKPR:
+ .dw $ff05
+ .db "CLKPR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKPR
+XT_CLKPR:
+ .dw PFA_DOVARIABLE
+PFA_CLKPR:
+ .dw 97
+; ( -- addr ) System Constant
+; R( -- )
+; Sleep Mode Control Register
+VE_SMCR:
+ .dw $ff04
+ .db "SMCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SMCR
+XT_SMCR:
+ .dw PFA_DOVARIABLE
+PFA_SMCR:
+ .dw 83
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 2
+VE_GPIOR2:
+ .dw $ff06
+ .db "GPIOR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR2
+XT_GPIOR2:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR2:
+ .dw 75
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 1
+VE_GPIOR1:
+ .dw $ff06
+ .db "GPIOR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR1
+XT_GPIOR1:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR1:
+ .dw 74
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 0
+VE_GPIOR0:
+ .dw $ff06
+ .db "GPIOR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR0
+XT_GPIOR0:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR0:
+ .dw 62
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register
+VE_PRR:
+ .dw $ff03
+ .db "PRR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR
+XT_PRR:
+ .dw PFA_DOVARIABLE
+PFA_PRR:
+ .dw 100
+
+.endif
diff --git a/amforth-6.5/avr8/devices/atmega644/device.py b/amforth-6.5/avr8/devices/atmega644/device.py
new file mode 100644
index 0000000..21ccfb1
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega644/device.py
@@ -0,0 +1,355 @@
+# Generated Automatically
+
+# Partname ATmega644
+
+MCUREGS = {
+# Interrupt Vectors
+ 'INT0Addr' : '#2', # External Interrupt Request 0
+ 'INT1Addr' : '#4', # External Interrupt Request 1
+ 'INT2Addr' : '#6', # External Interrupt Request 2
+ 'PCINT0Addr' : '#8', # Pin Change Interrupt Request 0
+ 'PCINT1Addr' : '#10', # Pin Change Interrupt Request 1
+ 'PCINT2Addr' : '#12', # Pin Change Interrupt Request 2
+ 'PCINT3Addr' : '#14', # Pin Change Interrupt Request 3
+ 'WDTAddr' : '#16', # Watchdog Time-out Interrupt
+ 'TIMER2_COMPAAddr' : '#18', # Timer/Counter2 Compare Match A
+ 'TIMER2_COMPBAddr' : '#20', # Timer/Counter2 Compare Match B
+ 'TIMER2_OVFAddr' : '#22', # Timer/Counter2 Overflow
+ 'TIMER1_CAPTAddr' : '#24', # Timer/Counter1 Capture Event
+ 'TIMER1_COMPAAddr' : '#26', # Timer/Counter1 Compare Match A
+ 'TIMER1_COMPBAddr' : '#28', # Timer/Counter1 Compare Match B
+ 'TIMER1_OVFAddr' : '#30', # Timer/Counter1 Overflow
+ 'TIMER0_COMPAAddr' : '#32', # Timer/Counter0 Compare Match A
+ 'TIMER0_COMPBAddr' : '#34', # Timer/Counter0 Compare Match B
+ 'TIMER0_OVFAddr' : '#36', # Timer/Counter0 Overflow
+ 'SPI_STCAddr' : '#38', # SPI Serial Transfer Complete
+ 'USART0_RXAddr' : '#40', # USART0, Rx Complete
+ 'USART0_UDREAddr' : '#42', # USART0 Data register Empty
+ 'USART0_TXAddr' : '#44', # USART0, Tx Complete
+ 'ANALOG_COMPAddr' : '#46', # Analog Comparator
+ 'ADCAddr' : '#48', # ADC Conversion Complete
+ 'EE_READYAddr' : '#50', # EEPROM Ready
+ 'TWIAddr' : '#52', # 2-wire Serial Interface
+ 'SPM_READYAddr' : '#54', # Store Program Memory Read
+
+# Module ANALOG_COMPARATOR
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
+ 'ACSR' : '$50', # Analog Comparator Control And
+ 'ACSR_ACD': '$80', # Analog Comparator Disable
+ 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
+ 'ACSR_ACO': '$20', # Analog Compare Output
+ 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
+ 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
+ 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
+ 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
+ 'DIDR1' : '$7f', # Digital Input Disable Register
+ 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
+ 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
+
+# Module USART0
+ 'UDR0' : '$c6', # USART I/O Data Register
+ 'UCSR0A' : '$c0', # USART Control and Status Regis
+ 'UCSR0A_RXC0': '$80', # USART Receive Complete
+ 'UCSR0A_TXC0': '$40', # USART Transmitt Complete
+ 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
+ 'UCSR0A_FE0': '$10', # Framing Error
+ 'UCSR0A_DOR0': '$8', # Data overRun
+ 'UCSR0A_UPE0': '$4', # Parity Error
+ 'UCSR0A_U2X0': '$2', # Double the USART transmission
+ 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
+ 'UCSR0B' : '$c1', # USART Control and Status Regis
+ 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
+ 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
+ 'UCSR0B_UDRIE0': '$20', # USART Data register Empty Inte
+ 'UCSR0B_RXEN0': '$10', # Receiver Enable
+ 'UCSR0B_TXEN0': '$8', # Transmitter Enable
+ 'UCSR0B_UCSZ02': '$4', # Character Size
+ 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
+ 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
+ 'UCSR0C' : '$c2', # USART Control and Status Regis
+ 'UCSR0C_UMSEL0': '$c0', # USART Mode Select
+ 'UCSR0C_UPM0': '$30', # Parity Mode Bits
+ 'UCSR0C_USBS0': '$8', # Stop Bit Select
+ 'UCSR0C_UCSZ0': '$6', # Character Size
+ 'UCSR0C_UCPOL0': '$1', # Clock Polarity
+ 'UBRR0' : '$c4', # USART Baud Rate Register Byte
+
+# Module PORTA
+ 'PORTA' : '$22', # Port A Data Register
+ 'DDRA' : '$21', # Port A Data Direction Register
+ 'PINA' : '$20', # Port A Input Pins
+
+# Module PORTB
+ 'PORTB' : '$25', # Port B Data Register
+ 'DDRB' : '$24', # Port B Data Direction Register
+ 'PINB' : '$23', # Port B Input Pins
+
+# Module PORTC
+ 'PORTC' : '$28', # Port C Data Register
+ 'DDRC' : '$27', # Port C Data Direction Register
+ 'PINC' : '$26', # Port C Input Pins
+
+# Module PORTD
+ 'PORTD' : '$2b', # Port D Data Register
+ 'DDRD' : '$2a', # Port D Data Direction Register
+ 'PIND' : '$29', # Port D Input Pins
+
+# Module TIMER_COUNTER_0
+ 'OCR0B' : '$48', # Timer/Counter0 Output Compare
+ 'OCR0A' : '$47', # Timer/Counter0 Output Compare
+ 'TCNT0' : '$46', # Timer/Counter0
+ 'TCCR0B' : '$45', # Timer/Counter Control Register
+ 'TCCR0B_FOC0A': '$80', # Force Output Compare A
+ 'TCCR0B_FOC0B': '$40', # Force Output Compare B
+ 'TCCR0B_WGM02': '$8', #
+ 'TCCR0B_CS0': '$7', # Clock Select
+ 'TCCR0A' : '$44', # Timer/Counter Control Registe
+ 'TCCR0A_COM0A': '$c0', # Compare Output Mode, Phase Cor
+ 'TCCR0A_COM0B': '$30', # Compare Output Mode, Fast PWm
+ 'TCCR0A_WGM0': '$3', # Waveform Generation Mode
+ 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
+ 'TIMSK0_OCIE0B': '$4', # Timer/Counter0 Output Compare
+ 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
+ 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
+ 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
+ 'TIFR0_OCF0B': '$4', # Timer/Counter0 Output Compare
+ 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
+ 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSRSYNC': '$1', # Prescaler Reset Timer/Counter1
+
+# Module TIMER_COUNTER_2
+ 'TIMSK2' : '$70', # Timer/Counter Interrupt Mask r
+ 'TIMSK2_OCIE2B': '$4', # Timer/Counter2 Output Compare
+ 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
+ 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
+ 'TIFR2' : '$37', # Timer/Counter Interrupt Flag R
+ 'TIFR2_OCF2B': '$4', # Output Compare Flag 2B
+ 'TIFR2_OCF2A': '$2', # Output Compare Flag 2A
+ 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
+ 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
+ 'TCCR2A_COM2A': '$c0', # Compare Output Mode bits
+ 'TCCR2A_COM2B': '$30', # Compare Output Mode bits
+ 'TCCR2A_WGM2': '$3', # Waveform Genration Mode
+ 'TCCR2B' : '$b1', # Timer/Counter2 Control Registe
+ 'TCCR2B_FOC2A': '$80', # Force Output Compare A
+ 'TCCR2B_FOC2B': '$40', # Force Output Compare B
+ 'TCCR2B_WGM22': '$8', # Waveform Generation Mode
+ 'TCCR2B_CS2': '$7', # Clock Select bits
+ 'TCNT2' : '$b2', # Timer/Counter2
+ 'OCR2B' : '$b4', # Timer/Counter2 Output Compare
+ 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
+ 'ASSR' : '$b6', # Asynchronous Status Register
+ 'ASSR_EXCLK': '$40', # Enable External Clock Input
+ 'ASSR_AS2': '$20', # Asynchronous Timer/Counter2
+ 'ASSR_TCN2UB': '$10', # Timer/Counter2 Update Busy
+ 'ASSR_OCR2AUB': '$8', # Output Compare Register2 Updat
+ 'ASSR_OCR2BUB': '$4', # Output Compare Register 2 Upda
+ 'ASSR_TCR2AUB': '$2', # Timer/Counter Control Register
+ 'ASSR_TCR2BUB': '$1', # Timer/Counter Control Register
+ 'GTCCR' : '$43', # General Timer Counter Control
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSRASY': '$2', # Prescaler Reset Timer/Counter2
+
+# Module WATCHDOG
+ 'WDTCSR' : '$60', # Watchdog Timer Control Registe
+ 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
+ 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
+ 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
+ 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
+ 'WDTCSR_WDE': '$8', # Watch Dog Enable
+
+# Module JTAG
+ 'OCDR' : '$51', # On-Chip Debug Related Register
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_JTD': '$80', # JTAG Interface Disable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+
+# Module BOOT_LOAD
+ 'SPMCSR' : '$57', # Store Program Memory Control R
+ 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
+ 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
+ 'SPMCSR_SIGRD': '$20', # Signature Row Read
+ 'SPMCSR_RWWSRE': '$10', # Read While Write section read
+ 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
+ 'SPMCSR_PGWRT': '$4', # Page Write
+ 'SPMCSR_PGERS': '$2', # Page Erase
+ 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
+
+# Module EXTERNAL_INTERRUPT
+ 'EICRA' : '$69', # External Interrupt Control Reg
+ 'EICRA_ISC2': '$30', # External Interrupt Sense Contr
+ 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
+ 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
+ 'EIMSK' : '$3d', # External Interrupt Mask Regist
+ 'EIMSK_INT': '$7', # External Interrupt Request 2 E
+ 'EIFR' : '$3c', # External Interrupt Flag Regist
+ 'EIFR_INTF': '$7', # External Interrupt Flags
+ 'PCMSK3' : '$73', # Pin Change Mask Register 3
+ 'PCMSK3_PCINT': '$ff', # Pin Change Enable Masks
+ 'PCMSK2' : '$6d', # Pin Change Mask Register 2
+ 'PCMSK2_PCINT': '$ff', # Pin Change Enable Masks
+ 'PCMSK1' : '$6c', # Pin Change Mask Register 1
+ 'PCMSK1_PCINT': '$ff', # Pin Change Enable Masks
+ 'PCMSK0' : '$6b', # Pin Change Mask Register 0
+ 'PCMSK0_PCINT': '$ff', # Pin Change Enable Masks
+ 'PCIFR' : '$3b', # Pin Change Interrupt Flag Regi
+ 'PCIFR_PCIF': '$f', # Pin Change Interrupt Flags
+ 'PCICR' : '$68', # Pin Change Interrupt Control R
+ 'PCICR_PCIE': '$f', # Pin Change Interrupt Enables
+
+# Module AD_CONVERTER
+ 'ADMUX' : '$7c', # The ADC multiplexer Selection
+ 'ADMUX_REFS': '$c0', # Reference Selection Bits
+ 'ADMUX_ADLAR': '$20', # Left Adjust Result
+ 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
+ 'ADC' : '$78', # ADC Data Register Bytes
+ 'ADCSRA' : '$7a', # The ADC Control and Status reg
+ 'ADCSRA_ADEN': '$80', # ADC Enable
+ 'ADCSRA_ADSC': '$40', # ADC Start Conversion
+ 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
+ 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
+ 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
+ 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
+ 'ADCSRB' : '$7b', # The ADC Control and Status reg
+ 'ADCSRB_ACME': '$40', #
+ 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Source bits
+ 'DIDR0' : '$7e', # Digital Input Disable Register
+ 'DIDR0_ADC7D': '$80', #
+ 'DIDR0_ADC6D': '$40', #
+ 'DIDR0_ADC5D': '$20', #
+ 'DIDR0_ADC4D': '$10', #
+ 'DIDR0_ADC3D': '$8', #
+ 'DIDR0_ADC2D': '$4', #
+ 'DIDR0_ADC1D': '$2', #
+ 'DIDR0_ADC0D': '$1', #
+
+# Module TIMER_COUNTER_1
+ 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
+ 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
+ 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
+ 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
+ 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
+ 'TIFR1' : '$36', # Timer/Counter Interrupt Flag r
+ 'TIFR1_ICF1': '$20', # Timer/Counter1 Input Capture F
+ 'TIFR1_OCF1B': '$4', # Timer/Counter1 Output Compare
+ 'TIFR1_OCF1A': '$2', # Timer/Counter1 Output Compare
+ 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
+ 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
+ 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
+ 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
+ 'TCCR1A_WGM1': '$3', # Pulse Width Modulator Select B
+ 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
+ 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
+ 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
+ 'TCCR1B_WGM1': '$18', # Waveform Generation Mode Bits
+ 'TCCR1B_CS1': '$7', # Clock Select1 bits
+ 'TCCR1C' : '$82', # Timer/Counter1 Control Registe
+ 'TCCR1C_FOC1A': '$80', # Force Output Compare for Chann
+ 'TCCR1C_FOC1B': '$40', # Force Output Compare for Chann
+ 'TCNT1' : '$84', # Timer/Counter1 Bytes
+ 'OCR1A' : '$88', # Timer/Counter1 Output Compare
+ 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
+ 'ICR1' : '$86', # Timer/Counter1 Input Capture R
+
+# Module EEPROM
+ 'EEAR' : '$41', # EEPROM Address Register Low By
+ 'EEDR' : '$40', # EEPROM Data Register
+ 'EECR' : '$3f', # EEPROM Control Register
+ 'EECR_EEPM': '$30', # EEPROM Programming Mode Bits
+ 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
+ 'EECR_EEMPE': '$4', # EEPROM Master Write Enable
+ 'EECR_EEPE': '$2', # EEPROM Write Enable
+ 'EECR_EERE': '$1', # EEPROM Read Enable
+
+# Module TWI
+ 'TWAMR' : '$bd', # TWI (Slave) Address Mask Regis
+ 'TWAMR_TWAM': '$fe', #
+ 'TWBR' : '$b8', # TWI Bit Rate register
+ 'TWCR' : '$bc', # TWI Control Register
+ 'TWCR_TWINT': '$80', # TWI Interrupt Flag
+ 'TWCR_TWEA': '$40', # TWI Enable Acknowledge Bit
+ 'TWCR_TWSTA': '$20', # TWI Start Condition Bit
+ 'TWCR_TWSTO': '$10', # TWI Stop Condition Bit
+ 'TWCR_TWWC': '$8', # TWI Write Collition Flag
+ 'TWCR_TWEN': '$4', # TWI Enable Bit
+ 'TWCR_TWIE': '$1', # TWI Interrupt Enable
+ 'TWSR' : '$b9', # TWI Status Register
+ 'TWSR_TWS': '$f8', # TWI Status
+ 'TWSR_TWPS': '$3', # TWI Prescaler
+ 'TWDR' : '$bb', # TWI Data register
+ 'TWAR' : '$ba', # TWI (Slave) Address register
+ 'TWAR_TWA': '$fe', # TWI (Slave) Address register B
+ 'TWAR_TWGCE': '$1', # TWI General Call Recognition E
+
+# Module SPI
+ 'SPDR' : '$4e', # SPI Data Register
+ 'SPSR' : '$4d', # SPI Status Register
+ 'SPSR_SPIF': '$80', # SPI Interrupt Flag
+ 'SPSR_WCOL': '$40', # Write Collision Flag
+ 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
+ 'SPCR' : '$4c', # SPI Control Register
+ 'SPCR_SPIE': '$80', # SPI Interrupt Enable
+ 'SPCR_SPE': '$40', # SPI Enable
+ 'SPCR_DORD': '$20', # Data Order
+ 'SPCR_MSTR': '$10', # Master/Slave Select
+ 'SPCR_CPOL': '$8', # Clock polarity
+ 'SPCR_CPHA': '$4', # Clock Phase
+ 'SPCR_SPR': '$3', # SPI Clock Rate Selects
+
+# Module CPU
+ 'SREG' : '$5f', # Status Register
+ 'SREG_I': '$80', # Global Interrupt Enable
+ 'SREG_T': '$40', # Bit Copy Storage
+ 'SREG_H': '$20', # Half Carry Flag
+ 'SREG_S': '$10', # Sign Bit
+ 'SREG_V': '$8', # Two's Complement Overflow Flag
+ 'SREG_N': '$4', # Negative Flag
+ 'SREG_Z': '$2', # Zero Flag
+ 'SREG_C': '$1', # Carry Flag
+ 'SP' : '$5d', # Stack Pointer
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_JTD': '$80', # JTAG Interface Disable
+ 'MCUCR_PUD': '$10', # Pull-up disable
+ 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
+ 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+ 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
+ 'MCUSR_BORF': '$4', # Brown-out Reset Flag
+ 'MCUSR_EXTRF': '$2', # External Reset Flag
+ 'MCUSR_PORF': '$1', # Power-on reset flag
+ 'OSCCAL' : '$66', # Oscillator Calibration Value
+ 'CLKPR' : '$61', #
+ 'CLKPR_CLKPCE': '$80', #
+ 'CLKPR_CLKPS': '$f', #
+ 'SMCR' : '$53', # Sleep Mode Control Register
+ 'SMCR_SM': '$e', # Sleep Mode Select bits
+ 'SMCR_SE': '$1', # Sleep Enable
+ 'GPIOR2' : '$4b', # General Purpose IO Register 2
+ 'GPIOR2_GPIOR': '$ff', # General Purpose IO Register 2
+ 'GPIOR1' : '$4a', # General Purpose IO Register 1
+ 'GPIOR1_GPIOR': '$ff', # General Purpose IO Register 1
+ 'GPIOR0' : '$3e', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR07': '$80', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR06': '$40', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR05': '$20', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR04': '$10', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR03': '$8', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR02': '$4', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR01': '$2', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR00': '$1', # General Purpose IO Register 0
+ 'PRR' : '$64', # Power Reduction Register
+ 'PRR_PRTWI': '$80', # Power Reduction TWI
+ 'PRR_PRTIM2': '$40', # Power Reduction Timer/Counter2
+ 'PRR_PRTIM0': '$20', # Power Reduction Timer/Counter0
+ 'PRR_PRTIM1': '$8', # Power Reduction Timer/Counter1
+ 'PRR_PRSPI': '$4', # Power Reduction Serial Periphe
+ 'PRR_PRUSART0': '$2', # Power Reduction USART
+ 'PRR_PRADC': '$1', # Power Reduction ADC
+
+ '__amforth_dummy':'0'
+}
diff --git a/amforth-6.5/avr8/devices/atmega644/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega644/words/no-jtag.asm
new file mode 100644
index 0000000..352a4bb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega644/words/no-jtag.asm
@@ -0,0 +1,14 @@
+; ( -- )
+; ( -- )
+; MCU
+; disable jtag at runtime
+VE_NOJTAG:
+ .dw $FF05
+ .db "-jtag",0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOJTAG
+XT_NOJTAG:
+ .dw PFA_NOJTAG
+PFA_NOJTAG:
+
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega644/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega644/words/no-wdt.asm
new file mode 100644
index 0000000..ff6ddd1
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega644/words/no-wdt.asm
@@ -0,0 +1,34 @@
+; ( -- )
+; MCU
+; disable watch dog timer at runtime
+VE_NOWDT:
+ .dw $ff04
+ .db "-wdt"
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOWDT
+XT_NOWDT:
+ .dw PFA_NOWDT
+PFA_NOWDT:
+
+ in temp1,SREG
+ push temp1
+ ; Turn always off global interrupt.
+ cli
+ ; Reset Watchdog Timer
+ wdr
+ ; Clear WDRF in MCUSR
+ in temp1, MCUSR
+ andi temp1, (0xff & (0<<WDRF))
+ out MCUSR, temp1
+ ; Write logical one to WDCE and WDE
+ ; Keep old prescaler setting to prevent unintentional time-out
+ in_ temp1, WDTCSR
+ ori temp1, (1<<WDCE) | (1<<WDE)
+ out_ WDTCSR, temp1
+ ; Turn off WDT
+ ldi temp1, (0<<WDE)
+ out_ WDTCSR, temp1
+ ; restore status register
+ pop temp1
+ out SREG,temp1
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega644/words/sleep.asm b/amforth-6.5/avr8/devices/atmega644/words/sleep.asm
new file mode 100644
index 0000000..256249c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega644/words/sleep.asm
@@ -0,0 +1,19 @@
+; ( mode -- )
+; MCU
+; put the controller into the specified sleep mode
+VE_SLEEP:
+ .dw $ff05
+ .db "sleep", 0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_SLEEP
+XT_SLEEP:
+ .dw PFA_SLEEP
+PFA_SLEEP:
+ andi tosl, 7 ; leave only legal mode bits
+ lsl tosl ; move to correct location (bits 3-1)
+ ori tosl, 1 ; set the SE bit
+ out_ SMCR, tosl ; set the sleep config
+ sleep ; nighty-night
+ out_ SMCR, zerol ; 0 protects against accidental sleeps
+ loadtos ; pop argument from stack
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega644a/atmega644a.frt b/amforth-6.5/avr8/devices/atmega644a/atmega644a.frt
new file mode 100644
index 0000000..ad7a908
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega644a/atmega644a.frt
@@ -0,0 +1,346 @@
+\ Partname: ATmega644A
+\ generated automatically
+
+\ ANALOG_COMPARATOR
+&123 constant ADCSRB \ ADC Control and Status Register B
+ $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer Enable
+&80 constant ACSR \ Analog Comparator Control And Status Register
+ $80 constant ACSR_ACD \ Analog Comparator Disable
+ $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
+ $20 constant ACSR_ACO \ Analog Compare Output
+ $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
+ $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
+ $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
+ $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
+&127 constant DIDR1 \ Digital Input Disable Register 1
+ $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
+ $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
+\ USART0
+&198 constant UDR0 \ USART I/O Data Register
+&192 constant UCSR0A \ USART Control and Status Register A
+ $80 constant UCSR0A_RXC0 \ USART Receive Complete
+ $40 constant UCSR0A_TXC0 \ USART Transmitt Complete
+ $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
+ $10 constant UCSR0A_FE0 \ Framing Error
+ $08 constant UCSR0A_DOR0 \ Data overRun
+ $04 constant UCSR0A_UPE0 \ Parity Error
+ $02 constant UCSR0A_U2X0 \ Double the USART transmission speed
+ $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
+&193 constant UCSR0B \ USART Control and Status Register B
+ $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
+ $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
+ $20 constant UCSR0B_UDRIE0 \ USART Data register Empty Interrupt Enable
+ $10 constant UCSR0B_RXEN0 \ Receiver Enable
+ $08 constant UCSR0B_TXEN0 \ Transmitter Enable
+ $04 constant UCSR0B_UCSZ02 \ Character Size
+ $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
+ $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
+&194 constant UCSR0C \ USART Control and Status Register C
+ $C0 constant UCSR0C_UMSEL0 \ USART Mode Select
+ $30 constant UCSR0C_UPM0 \ Parity Mode Bits
+ $08 constant UCSR0C_USBS0 \ Stop Bit Select
+ $06 constant UCSR0C_UCSZ0 \ Character Size
+ $01 constant UCSR0C_UCPOL0 \ Clock Polarity
+&196 constant UBRR0 \ USART Baud Rate Register Bytes
+\ PORTA
+&34 constant PORTA \ Port A Data Register
+&33 constant DDRA \ Port A Data Direction Register
+&32 constant PINA \ Port A Input Pins
+\ PORTB
+&37 constant PORTB \ Port B Data Register
+&36 constant DDRB \ Port B Data Direction Register
+&35 constant PINB \ Port B Input Pins
+\ PORTC
+&40 constant PORTC \ Port C Data Register
+&39 constant DDRC \ Port C Data Direction Register
+&38 constant PINC \ Port C Input Pins
+\ PORTD
+&43 constant PORTD \ Port D Data Register
+&42 constant DDRD \ Port D Data Direction Register
+&41 constant PIND \ Port D Input Pins
+\ TIMER_COUNTER_0
+&72 constant OCR0B \ Timer/Counter0 Output Compare Register
+&71 constant OCR0A \ Timer/Counter0 Output Compare Register
+&70 constant TCNT0 \ Timer/Counter0
+&69 constant TCCR0B \ Timer/Counter Control Register B
+ $80 constant TCCR0B_FOC0A \ Force Output Compare A
+ $40 constant TCCR0B_FOC0B \ Force Output Compare B
+ $08 constant TCCR0B_WGM02 \
+ $07 constant TCCR0B_CS0 \ Clock Select
+&68 constant TCCR0A \ Timer/Counter Control Register A
+ $C0 constant TCCR0A_COM0A \ Compare Output Mode, Phase Correct PWM Mode
+ $30 constant TCCR0A_COM0B \ Compare Output Mode, Fast PWm
+ $03 constant TCCR0A_WGM0 \ Waveform Generation Mode
+&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
+ $04 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare Match B Interrupt Enable
+ $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match A Interrupt Enable
+ $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
+&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
+ $04 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare Flag 0B
+ $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0A
+ $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
+&67 constant GTCCR \ General Timer/Counter Control Register
+ $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
+ $01 constant GTCCR_PSRSYNC \ Prescaler Reset Timer/Counter1 and Timer/Counter0
+\ TIMER_COUNTER_2
+&112 constant TIMSK2 \ Timer/Counter Interrupt Mask register
+ $04 constant TIMSK2_OCIE2B \ Timer/Counter2 Output Compare Match B Interrupt Enable
+ $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match A Interrupt Enable
+ $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
+&55 constant TIFR2 \ Timer/Counter Interrupt Flag Register
+ $04 constant TIFR2_OCF2B \ Output Compare Flag 2B
+ $02 constant TIFR2_OCF2A \ Output Compare Flag 2A
+ $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
+&176 constant TCCR2A \ Timer/Counter2 Control Register A
+ $C0 constant TCCR2A_COM2A \ Compare Output Mode bits
+ $30 constant TCCR2A_COM2B \ Compare Output Mode bits
+ $03 constant TCCR2A_WGM2 \ Waveform Genration Mode
+&177 constant TCCR2B \ Timer/Counter2 Control Register B
+ $80 constant TCCR2B_FOC2A \ Force Output Compare A
+ $40 constant TCCR2B_FOC2B \ Force Output Compare B
+ $08 constant TCCR2B_WGM22 \ Waveform Generation Mode
+ $07 constant TCCR2B_CS2 \ Clock Select bits
+&178 constant TCNT2 \ Timer/Counter2
+&180 constant OCR2B \ Timer/Counter2 Output Compare Register B
+&179 constant OCR2A \ Timer/Counter2 Output Compare Register A
+&182 constant ASSR \ Asynchronous Status Register
+ $40 constant ASSR_EXCLK \ Enable External Clock Input
+ $20 constant ASSR_AS2 \ Asynchronous Timer/Counter2
+ $10 constant ASSR_TCN2UB \ Timer/Counter2 Update Busy
+ $08 constant ASSR_OCR2AUB \ Output Compare Register2 Update Busy
+ $04 constant ASSR_OCR2BUB \ Output Compare Register 2 Update Busy
+ $02 constant ASSR_TCR2AUB \ Timer/Counter Control Register2 Update Busy
+ $01 constant ASSR_TCR2BUB \ Timer/Counter Control Register2 Update Busy
+\ WATCHDOG
+&96 constant WDTCSR \ Watchdog Timer Control Register
+ $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Flag
+ $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Enable
+ $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
+ $10 constant WDTCSR_WDCE \ Watchdog Change Enable
+ $08 constant WDTCSR_WDE \ Watch Dog Enable
+\ JTAG
+&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
+&85 constant MCUCR \ MCU Control Register
+ $80 constant MCUCR_JTD \ JTAG Interface Disable
+&84 constant MCUSR \ MCU Status Register
+ $10 constant MCUSR_JTRF \ JTAG Reset Flag
+\ BOOT_LOAD
+&87 constant SPMCSR \ Store Program Memory Control Register
+ $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
+ $20 constant SPMCSR_SIGRD \ Signature Row Read
+ $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
+ $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
+ $04 constant SPMCSR_PGWRT \ Page Write
+ $02 constant SPMCSR_PGERS \ Page Erase
+ $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
+\ EXTERNAL_INTERRUPT
+&105 constant EICRA \ External Interrupt Control Register A
+ $30 constant EICRA_ISC2 \ External Interrupt Sense Control Bit
+ $0C constant EICRA_ISC1 \ External Interrupt Sense Control Bit
+ $03 constant EICRA_ISC0 \ External Interrupt Sense Control Bit
+&61 constant EIMSK \ External Interrupt Mask Register
+ $07 constant EIMSK_INT \ External Interrupt Request 2 Enable
+&60 constant EIFR \ External Interrupt Flag Register
+ $07 constant EIFR_INTF \ External Interrupt Flags
+&115 constant PCMSK3 \ Pin Change Mask Register 3
+ $FF constant PCMSK3_PCINT \ Pin Change Enable Masks
+&109 constant PCMSK2 \ Pin Change Mask Register 2
+ $FF constant PCMSK2_PCINT \ Pin Change Enable Masks
+&108 constant PCMSK1 \ Pin Change Mask Register 1
+ $FF constant PCMSK1_PCINT \ Pin Change Enable Masks
+&107 constant PCMSK0 \ Pin Change Mask Register 0
+ $FF constant PCMSK0_PCINT \ Pin Change Enable Masks
+&59 constant PCIFR \ Pin Change Interrupt Flag Register
+ $0F constant PCIFR_PCIF \ Pin Change Interrupt Flags
+&104 constant PCICR \ Pin Change Interrupt Control Register
+ $0F constant PCICR_PCIE \ Pin Change Interrupt Enables
+\ AD_CONVERTER
+&124 constant ADMUX \ The ADC multiplexer Selection Register
+ $C0 constant ADMUX_REFS \ Reference Selection Bits
+ $20 constant ADMUX_ADLAR \ Left Adjust Result
+ $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
+&120 constant ADC \ ADC Data Register Bytes
+&122 constant ADCSRA \ The ADC Control and Status register A
+ $80 constant ADCSRA_ADEN \ ADC Enable
+ $40 constant ADCSRA_ADSC \ ADC Start Conversion
+ $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
+ $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
+ $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
+ $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
+&126 constant DIDR0 \ Digital Input Disable Register
+ $80 constant DIDR0_ADC7D \
+ $40 constant DIDR0_ADC6D \
+ $20 constant DIDR0_ADC5D \
+ $10 constant DIDR0_ADC4D \
+ $08 constant DIDR0_ADC3D \
+ $04 constant DIDR0_ADC2D \
+ $02 constant DIDR0_ADC1D \
+ $01 constant DIDR0_ADC0D \
+\ TIMER_COUNTER_1
+&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
+ $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
+ $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
+ $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
+ $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
+&54 constant TIFR1 \ Timer/Counter Interrupt Flag register
+ $20 constant TIFR1_ICF1 \ Timer/Counter1 Input Capture Flag
+ $04 constant TIFR1_OCF1B \ Timer/Counter1 Output Compare B Match Flag
+ $02 constant TIFR1_OCF1A \ Timer/Counter1 Output Compare A Match Flag
+ $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
+&128 constant TCCR1A \ Timer/Counter1 Control Register A
+ $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
+ $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
+ $03 constant TCCR1A_WGM1 \ Pulse Width Modulator Select Bits
+&129 constant TCCR1B \ Timer/Counter1 Control Register B
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ $18 constant TCCR1B_WGM1 \ Waveform Generation Mode Bits
+ $07 constant TCCR1B_CS1 \ Clock Select1 bits
+&130 constant TCCR1C \ Timer/Counter1 Control Register C
+ $80 constant TCCR1C_FOC1A \ Force Output Compare for Channel A
+ $40 constant TCCR1C_FOC1B \ Force Output Compare for Channel B
+&132 constant TCNT1 \ Timer/Counter1 Bytes
+&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
+&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
+&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
+\ EEPROM
+&65 constant EEAR \ EEPROM Address Register Low Bytes
+&64 constant EEDR \ EEPROM Data Register
+&63 constant EECR \ EEPROM Control Register
+ $30 constant EECR_EEPM \ EEPROM Programming Mode Bits
+ $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
+ $04 constant EECR_EEMPE \ EEPROM Master Write Enable
+ $02 constant EECR_EEPE \ EEPROM Write Enable
+ $01 constant EECR_EERE \ EEPROM Read Enable
+\ TWI
+&189 constant TWAMR \ TWI (Slave) Address Mask Register
+ $FE constant TWAMR_TWAM \
+&184 constant TWBR \ TWI Bit Rate register
+&188 constant TWCR \ TWI Control Register
+ $80 constant TWCR_TWINT \ TWI Interrupt Flag
+ $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
+ $20 constant TWCR_TWSTA \ TWI Start Condition Bit
+ $10 constant TWCR_TWSTO \ TWI Stop Condition Bit
+ $08 constant TWCR_TWWC \ TWI Write Collition Flag
+ $04 constant TWCR_TWEN \ TWI Enable Bit
+ $01 constant TWCR_TWIE \ TWI Interrupt Enable
+&185 constant TWSR \ TWI Status Register
+ $F8 constant TWSR_TWS \ TWI Status
+ $03 constant TWSR_TWPS \ TWI Prescaler
+&187 constant TWDR \ TWI Data register
+&186 constant TWAR \ TWI (Slave) Address register
+ $FE constant TWAR_TWA \ TWI (Slave) Address register Bits
+ $01 constant TWAR_TWGCE \ TWI General Call Recognition Enable Bit
+\ USART1
+&206 constant UDR1 \ USART I/O Data Register
+&200 constant UCSR1A \ USART Control and Status Register A
+ $80 constant UCSR1A_RXC1 \ USART Receive Complete
+ $40 constant UCSR1A_TXC1 \ USART Transmitt Complete
+ $20 constant UCSR1A_UDRE1 \ USART Data Register Empty
+ $10 constant UCSR1A_FE1 \ Framing Error
+ $08 constant UCSR1A_DOR1 \ Data overRun
+ $04 constant UCSR1A_UPE1 \ Parity Error
+ $02 constant UCSR1A_U2X1 \ Double the USART transmission speed
+ $01 constant UCSR1A_MPCM1 \ Multi-processor Communication Mode
+&201 constant UCSR1B \ USART Control and Status Register B
+ $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable
+ $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable
+ $20 constant UCSR1B_UDRIE1 \ USART Data register Empty Interrupt Enable
+ $10 constant UCSR1B_RXEN1 \ Receiver Enable
+ $08 constant UCSR1B_TXEN1 \ Transmitter Enable
+ $04 constant UCSR1B_UCSZ12 \ Character Size
+ $02 constant UCSR1B_RXB81 \ Receive Data Bit 8
+ $01 constant UCSR1B_TXB81 \ Transmit Data Bit 8
+&202 constant UCSR1C \ USART Control and Status Register C
+ $C0 constant UCSR1C_UMSEL1 \ USART Mode Select
+ $30 constant UCSR1C_UPM1 \ Parity Mode Bits
+ $08 constant UCSR1C_USBS1 \ Stop Bit Select
+ $06 constant UCSR1C_UCSZ1 \ Character Size
+ $01 constant UCSR1C_UCPOL1 \ Clock Polarity
+&204 constant UBRR1 \ USART Baud Rate Register Bytes
+\ SPI
+&78 constant SPDR \ SPI Data Register
+&77 constant SPSR \ SPI Status Register
+ $80 constant SPSR_SPIF \ SPI Interrupt Flag
+ $40 constant SPSR_WCOL \ Write Collision Flag
+ $01 constant SPSR_SPI2X \ Double SPI Speed Bit
+&76 constant SPCR \ SPI Control Register
+ $80 constant SPCR_SPIE \ SPI Interrupt Enable
+ $40 constant SPCR_SPE \ SPI Enable
+ $20 constant SPCR_DORD \ Data Order
+ $10 constant SPCR_MSTR \ Master/Slave Select
+ $08 constant SPCR_CPOL \ Clock polarity
+ $04 constant SPCR_CPHA \ Clock Phase
+ $03 constant SPCR_SPR \ SPI Clock Rate Selects
+\ CPU
+&95 constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ $08 constant SREG_V \ Two's Complement Overflow Flag
+ $04 constant SREG_N \ Negative Flag
+ $02 constant SREG_Z \ Zero Flag
+ $01 constant SREG_C \ Carry Flag
+&93 constant SP \ Stack Pointer
+&102 constant OSCCAL \ Oscillator Calibration Value
+&97 constant CLKPR \
+ $80 constant CLKPR_CLKPCE \
+ $0F constant CLKPR_CLKPS \
+&83 constant SMCR \ Sleep Mode Control Register
+ $0E constant SMCR_SM \ Sleep Mode Select bits
+ $01 constant SMCR_SE \ Sleep Enable
+&75 constant GPIOR2 \ General Purpose IO Register 2
+ $FF constant GPIOR2_GPIOR \ General Purpose IO Register 2 bis
+&74 constant GPIOR1 \ General Purpose IO Register 1
+ $FF constant GPIOR1_GPIOR \ General Purpose IO Register 1 bis
+&62 constant GPIOR0 \ General Purpose IO Register 0
+ $80 constant GPIOR0_GPIOR07 \ General Purpose IO Register 0 bit 7
+ $40 constant GPIOR0_GPIOR06 \ General Purpose IO Register 0 bit 6
+ $20 constant GPIOR0_GPIOR05 \ General Purpose IO Register 0 bit 5
+ $10 constant GPIOR0_GPIOR04 \ General Purpose IO Register 0 bit 4
+ $08 constant GPIOR0_GPIOR03 \ General Purpose IO Register 0 bit 3
+ $04 constant GPIOR0_GPIOR02 \ General Purpose IO Register 0 bit 2
+ $02 constant GPIOR0_GPIOR01 \ General Purpose IO Register 0 bit 1
+ $01 constant GPIOR0_GPIOR00 \ General Purpose IO Register 0 bit 0
+&100 constant PRR0 \ Power Reduction Register0
+ $80 constant PRR0_PRTWI \ Power Reduction TWI
+ $40 constant PRR0_PRTIM2 \ Power Reduction Timer/Counter2
+ $20 constant PRR0_PRTIM0 \ Power Reduction Timer/Counter0
+ $12 constant PRR0_PRUSART \ Power Reduction USARTs
+ $08 constant PRR0_PRTIM1 \ Power Reduction Timer/Counter1
+ $04 constant PRR0_PRSPI \ Power Reduction Serial Peripheral Interface
+ $01 constant PRR0_PRADC \ Power Reduction ADC
+
+\ Interrupts
+&2 constant INT0Addr \ External Interrupt Request 0
+&4 constant INT1Addr \ External Interrupt Request 1
+&6 constant INT2Addr \ External Interrupt Request 2
+&8 constant PCINT0Addr \ Pin Change Interrupt Request 0
+&10 constant PCINT1Addr \ Pin Change Interrupt Request 1
+&12 constant PCINT2Addr \ Pin Change Interrupt Request 2
+&14 constant PCINT3Addr \ Pin Change Interrupt Request 3
+&16 constant WDTAddr \ Watchdog Time-out Interrupt
+&18 constant TIMER2_COMPAAddr \ Timer/Counter2 Compare Match A
+&20 constant TIMER2_COMPBAddr \ Timer/Counter2 Compare Match B
+&22 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
+&24 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+&26 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
+&28 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
+&30 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+&32 constant TIMER0_COMPAAddr \ Timer/Counter0 Compare Match A
+&34 constant TIMER0_COMPBAddr \ Timer/Counter0 Compare Match B
+&36 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
+&38 constant SPI__STCAddr \ SPI Serial Transfer Complete
+&40 constant USART0__RXAddr \ USART0, Rx Complete
+&42 constant USART0__UDREAddr \ USART0 Data register Empty
+&44 constant USART0__TXAddr \ USART0, Tx Complete
+&46 constant ANALOG_COMPAddr \ Analog Comparator
+&48 constant ADCAddr \ ADC Conversion Complete
+&50 constant EE_READYAddr \ EEPROM Ready
+&52 constant TWIAddr \ 2-wire Serial Interface
+&54 constant SPM_READYAddr \ Store Program Memory Read
+&56 constant USART1_RXAddr \ USART1 RX complete
+&58 constant USART1_UDREAddr \ USART1 Data Register Empty
+&60 constant USART1_TXAddr \ USART1 TX complete
diff --git a/amforth-6.5/avr8/devices/atmega644a/device.asm b/amforth-6.5/avr8/devices/atmega644a/device.asm
new file mode 100644
index 0000000..e07e06e
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega644a/device.asm
@@ -0,0 +1,120 @@
+; Partname: ATmega644A
+; generated automatically, do not edit
+
+.nolist
+ .include "m644Adef.inc"
+.list
+
+.equ ramstart = 256
+.equ CELLSIZE = 2
+.macro readflashcell
+ lsl zl
+ rol zh
+ lpm @0, Z+
+ lpm @1, Z+
+.endmacro
+.macro writeflashcell
+ lsl zl
+ rol zh
+.endmacro
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_USART0 = 0
+.set WANT_PORTA = 0
+.set WANT_PORTB = 0
+.set WANT_PORTC = 0
+.set WANT_PORTD = 0
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_TIMER_COUNTER_2 = 0
+.set WANT_WATCHDOG = 0
+.set WANT_JTAG = 0
+.set WANT_BOOT_LOAD = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_AD_CONVERTER = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_EEPROM = 0
+.set WANT_TWI = 0
+.set WANT_USART1 = 0
+.set WANT_SPI = 0
+.set WANT_CPU = 0
+.equ intvecsize = 2 ; please verify; flash size: 65536 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.org 2
+ rcall isr ; External Interrupt Request 0
+.org 4
+ rcall isr ; External Interrupt Request 1
+.org 6
+ rcall isr ; External Interrupt Request 2
+.org 8
+ rcall isr ; Pin Change Interrupt Request 0
+.org 10
+ rcall isr ; Pin Change Interrupt Request 1
+.org 12
+ rcall isr ; Pin Change Interrupt Request 2
+.org 14
+ rcall isr ; Pin Change Interrupt Request 3
+.org 16
+ rcall isr ; Watchdog Time-out Interrupt
+.org 18
+ rcall isr ; Timer/Counter2 Compare Match A
+.org 20
+ rcall isr ; Timer/Counter2 Compare Match B
+.org 22
+ rcall isr ; Timer/Counter2 Overflow
+.org 24
+ rcall isr ; Timer/Counter1 Capture Event
+.org 26
+ rcall isr ; Timer/Counter1 Compare Match A
+.org 28
+ rcall isr ; Timer/Counter1 Compare Match B
+.org 30
+ rcall isr ; Timer/Counter1 Overflow
+.org 32
+ rcall isr ; Timer/Counter0 Compare Match A
+.org 34
+ rcall isr ; Timer/Counter0 Compare Match B
+.org 36
+ rcall isr ; Timer/Counter0 Overflow
+.org 38
+ rcall isr ; SPI Serial Transfer Complete
+.org 40
+ rcall isr ; USART0, Rx Complete
+.org 42
+ rcall isr ; USART0 Data register Empty
+.org 44
+ rcall isr ; USART0, Tx Complete
+.org 46
+ rcall isr ; Analog Comparator
+.org 48
+ rcall isr ; ADC Conversion Complete
+.org 50
+ rcall isr ; EEPROM Ready
+.org 52
+ rcall isr ; 2-wire Serial Interface
+.org 54
+ rcall isr ; Store Program Memory Read
+.org 56
+ rcall isr ; USART1 RX complete
+.org 58
+ rcall isr ; USART1 Data Register Empty
+.org 60
+ rcall isr ; USART1 TX complete
+.equ INTVECTORS = 31
+.nooverlap
+
+; compatability layer (maybe empty)
+
+; controller data area, environment query mcu-info
+mcu_info:
+mcu_ramsize:
+ .dw 4096
+mcu_eepromsize:
+ .dw 2048
+mcu_maxdp:
+ .dw 57344
+mcu_numints:
+ .dw 31
+mcu_name:
+ .dw 10
+ .db "ATmega644A"
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega644a/device.inc b/amforth-6.5/avr8/devices/atmega644a/device.inc
new file mode 100644
index 0000000..c267ebf
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega644a/device.inc
@@ -0,0 +1,1128 @@
+; Partname: ATmega644A
+; generated automatically, no not edit
+
+.if WANT_ANALOG_COMPARATOR == 1
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Control and Status Register B
+VE_ADCSRB:
+ .dw $ff06
+ .db "ADCSRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRB
+XT_ADCSRB:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRB:
+ .dw 123
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Control And Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw 80
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 1
+VE_DIDR1:
+ .dw $ff05
+ .db "DIDR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR1
+XT_DIDR1:
+ .dw PFA_DOVARIABLE
+PFA_DIDR1:
+ .dw 127
+
+.endif
+.if WANT_USART0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR0:
+ .dw $ff04
+ .db "UDR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR0
+XT_UDR0:
+ .dw PFA_DOVARIABLE
+PFA_UDR0:
+ .dw 198
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR0A:
+ .dw $ff06
+ .db "UCSR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0A
+XT_UCSR0A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0A:
+ .dw 192
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR0B:
+ .dw $ff06
+ .db "UCSR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0B
+XT_UCSR0B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0B:
+ .dw 193
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR0C:
+ .dw $ff06
+ .db "UCSR0C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0C
+XT_UCSR0C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0C:
+ .dw 194
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Bytes
+VE_UBRR0:
+ .dw $ff05
+ .db "UBRR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR0
+XT_UBRR0:
+ .dw PFA_DOVARIABLE
+PFA_UBRR0:
+ .dw 196
+
+.endif
+.if WANT_PORTA == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Register
+VE_PORTA:
+ .dw $ff05
+ .db "PORTA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTA
+XT_PORTA:
+ .dw PFA_DOVARIABLE
+PFA_PORTA:
+ .dw 34
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Direction Register
+VE_DDRA:
+ .dw $ff04
+ .db "DDRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRA
+XT_DDRA:
+ .dw PFA_DOVARIABLE
+PFA_DDRA:
+ .dw 33
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Input Pins
+VE_PINA:
+ .dw $ff04
+ .db "PINA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINA
+XT_PINA:
+ .dw PFA_DOVARIABLE
+PFA_PINA:
+ .dw 32
+
+.endif
+.if WANT_PORTB == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw 37
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw 36
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw 35
+
+.endif
+.if WANT_PORTC == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Register
+VE_PORTC:
+ .dw $ff05
+ .db "PORTC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTC
+XT_PORTC:
+ .dw PFA_DOVARIABLE
+PFA_PORTC:
+ .dw 40
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Direction Register
+VE_DDRC:
+ .dw $ff04
+ .db "DDRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRC
+XT_DDRC:
+ .dw PFA_DOVARIABLE
+PFA_DDRC:
+ .dw 39
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Input Pins
+VE_PINC:
+ .dw $ff04
+ .db "PINC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINC
+XT_PINC:
+ .dw PFA_DOVARIABLE
+PFA_PINC:
+ .dw 38
+
+.endif
+.if WANT_PORTD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw 43
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw 42
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw 41
+
+.endif
+.if WANT_TIMER_COUNTER_0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0B:
+ .dw $ff05
+ .db "OCR0B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0B
+XT_OCR0B:
+ .dw PFA_DOVARIABLE
+PFA_OCR0B:
+ .dw 72
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0A:
+ .dw $ff05
+ .db "OCR0A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0A
+XT_OCR0A:
+ .dw PFA_DOVARIABLE
+PFA_OCR0A:
+ .dw 71
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw 70
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register B
+VE_TCCR0B:
+ .dw $ff06
+ .db "TCCR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0B
+XT_TCCR0B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0B:
+ .dw 69
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register A
+VE_TCCR0A:
+ .dw $ff06
+ .db "TCCR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0A
+XT_TCCR0A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0A:
+ .dw 68
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Mask Register
+VE_TIMSK0:
+ .dw $ff06
+ .db "TIMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK0
+XT_TIMSK0:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK0:
+ .dw 110
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Flag register
+VE_TIFR0:
+ .dw $ff05
+ .db "TIFR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR0
+XT_TIFR0:
+ .dw PFA_DOVARIABLE
+PFA_TIFR0:
+ .dw 53
+; ( -- addr ) System Constant
+; R( -- )
+; General Timer/Counter Control Register
+VE_GTCCR:
+ .dw $ff05
+ .db "GTCCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GTCCR
+XT_GTCCR:
+ .dw PFA_DOVARIABLE
+PFA_GTCCR:
+ .dw 67
+
+.endif
+.if WANT_TIMER_COUNTER_2 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Mask register
+VE_TIMSK2:
+ .dw $ff06
+ .db "TIMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK2
+XT_TIMSK2:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK2:
+ .dw 112
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Flag Register
+VE_TIFR2:
+ .dw $ff05
+ .db "TIFR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR2
+XT_TIFR2:
+ .dw PFA_DOVARIABLE
+PFA_TIFR2:
+ .dw 55
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register A
+VE_TCCR2A:
+ .dw $ff06
+ .db "TCCR2A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2A
+XT_TCCR2A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2A:
+ .dw 176
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register B
+VE_TCCR2B:
+ .dw $ff06
+ .db "TCCR2B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2B
+XT_TCCR2B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2B:
+ .dw 177
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2
+VE_TCNT2:
+ .dw $ff05
+ .db "TCNT2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT2
+XT_TCNT2:
+ .dw PFA_DOVARIABLE
+PFA_TCNT2:
+ .dw 178
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register B
+VE_OCR2B:
+ .dw $ff05
+ .db "OCR2B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2B
+XT_OCR2B:
+ .dw PFA_DOVARIABLE
+PFA_OCR2B:
+ .dw 180
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register A
+VE_OCR2A:
+ .dw $ff05
+ .db "OCR2A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2A
+XT_OCR2A:
+ .dw PFA_DOVARIABLE
+PFA_OCR2A:
+ .dw 179
+; ( -- addr ) System Constant
+; R( -- )
+; Asynchronous Status Register
+VE_ASSR:
+ .dw $ff04
+ .db "ASSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ASSR
+XT_ASSR:
+ .dw PFA_DOVARIABLE
+PFA_ASSR:
+ .dw 182
+
+.endif
+.if WANT_WATCHDOG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCSR:
+ .dw $ff06
+ .db "WDTCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCSR
+XT_WDTCSR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCSR:
+ .dw 96
+
+.endif
+.if WANT_JTAG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; On-Chip Debug Related Register in I/O Memory
+VE_OCDR:
+ .dw $ff04
+ .db "OCDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCDR
+XT_OCDR:
+ .dw PFA_DOVARIABLE
+PFA_OCDR:
+ .dw 81
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw 85
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Status Register
+VE_MCUSR:
+ .dw $ff05
+ .db "MCUSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUSR
+XT_MCUSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUSR:
+ .dw 84
+
+.endif
+.if WANT_BOOT_LOAD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control Register
+VE_SPMCSR:
+ .dw $ff06
+ .db "SPMCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCSR
+XT_SPMCSR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCSR:
+ .dw 87
+
+.endif
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register A
+VE_EICRA:
+ .dw $ff05
+ .db "EICRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRA
+XT_EICRA:
+ .dw PFA_DOVARIABLE
+PFA_EICRA:
+ .dw 105
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Mask Register
+VE_EIMSK:
+ .dw $ff05
+ .db "EIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIMSK
+XT_EIMSK:
+ .dw PFA_DOVARIABLE
+PFA_EIMSK:
+ .dw 61
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Flag Register
+VE_EIFR:
+ .dw $ff04
+ .db "EIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIFR
+XT_EIFR:
+ .dw PFA_DOVARIABLE
+PFA_EIFR:
+ .dw 60
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 3
+VE_PCMSK3:
+ .dw $ff06
+ .db "PCMSK3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK3
+XT_PCMSK3:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK3:
+ .dw 115
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 2
+VE_PCMSK2:
+ .dw $ff06
+ .db "PCMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK2
+XT_PCMSK2:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK2:
+ .dw 109
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 1
+VE_PCMSK1:
+ .dw $ff06
+ .db "PCMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK1
+XT_PCMSK1:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK1:
+ .dw 108
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 0
+VE_PCMSK0:
+ .dw $ff06
+ .db "PCMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK0
+XT_PCMSK0:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK0:
+ .dw 107
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Interrupt Flag Register
+VE_PCIFR:
+ .dw $ff05
+ .db "PCIFR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCIFR
+XT_PCIFR:
+ .dw PFA_DOVARIABLE
+PFA_PCIFR:
+ .dw 59
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Interrupt Control Register
+VE_PCICR:
+ .dw $ff05
+ .db "PCICR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCICR
+XT_PCICR:
+ .dw PFA_DOVARIABLE
+PFA_PCICR:
+ .dw 104
+
+.endif
+.if WANT_AD_CONVERTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC multiplexer Selection Register
+VE_ADMUX:
+ .dw $ff05
+ .db "ADMUX",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADMUX
+XT_ADMUX:
+ .dw PFA_DOVARIABLE
+PFA_ADMUX:
+ .dw 124
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register Bytes
+VE_ADC:
+ .dw $ff03
+ .db "ADC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADC
+XT_ADC:
+ .dw PFA_DOVARIABLE
+PFA_ADC:
+ .dw 120
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register A
+VE_ADCSRA:
+ .dw $ff06
+ .db "ADCSRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRA
+XT_ADCSRA:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRA:
+ .dw 122
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register
+VE_DIDR0:
+ .dw $ff05
+ .db "DIDR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR0
+XT_DIDR0:
+ .dw PFA_DOVARIABLE
+PFA_DIDR0:
+ .dw 126
+
+.endif
+.if WANT_TIMER_COUNTER_1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Mask Register
+VE_TIMSK1:
+ .dw $ff06
+ .db "TIMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK1
+XT_TIMSK1:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK1:
+ .dw 111
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Flag register
+VE_TIFR1:
+ .dw $ff05
+ .db "TIFR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR1
+XT_TIFR1:
+ .dw PFA_DOVARIABLE
+PFA_TIFR1:
+ .dw 54
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw 128
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw 129
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register C
+VE_TCCR1C:
+ .dw $ff06
+ .db "TCCR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1C
+XT_TCCR1C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1C:
+ .dw 130
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Bytes
+VE_TCNT1:
+ .dw $ff05
+ .db "TCNT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1
+XT_TCNT1:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1:
+ .dw 132
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register A Bytes
+VE_OCR1A:
+ .dw $ff05
+ .db "OCR1A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1A
+XT_OCR1A:
+ .dw PFA_DOVARIABLE
+PFA_OCR1A:
+ .dw 136
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register B Bytes
+VE_OCR1B:
+ .dw $ff05
+ .db "OCR1B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1B
+XT_OCR1B:
+ .dw PFA_DOVARIABLE
+PFA_OCR1B:
+ .dw 138
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Bytes
+VE_ICR1:
+ .dw $ff04
+ .db "ICR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1
+XT_ICR1:
+ .dw PFA_DOVARIABLE
+PFA_ICR1:
+ .dw 134
+
+.endif
+.if WANT_EEPROM == 1
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Address Register Low Bytes
+VE_EEAR:
+ .dw $ff04
+ .db "EEAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEAR
+XT_EEAR:
+ .dw PFA_DOVARIABLE
+PFA_EEAR:
+ .dw 65
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw 64
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw 63
+
+.endif
+.if WANT_TWI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; TWI (Slave) Address Mask Register
+VE_TWAMR:
+ .dw $ff05
+ .db "TWAMR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWAMR
+XT_TWAMR:
+ .dw PFA_DOVARIABLE
+PFA_TWAMR:
+ .dw 189
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Bit Rate register
+VE_TWBR:
+ .dw $ff04
+ .db "TWBR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWBR
+XT_TWBR:
+ .dw PFA_DOVARIABLE
+PFA_TWBR:
+ .dw 184
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Control Register
+VE_TWCR:
+ .dw $ff04
+ .db "TWCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWCR
+XT_TWCR:
+ .dw PFA_DOVARIABLE
+PFA_TWCR:
+ .dw 188
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Status Register
+VE_TWSR:
+ .dw $ff04
+ .db "TWSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWSR
+XT_TWSR:
+ .dw PFA_DOVARIABLE
+PFA_TWSR:
+ .dw 185
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Data register
+VE_TWDR:
+ .dw $ff04
+ .db "TWDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWDR
+XT_TWDR:
+ .dw PFA_DOVARIABLE
+PFA_TWDR:
+ .dw 187
+; ( -- addr ) System Constant
+; R( -- )
+; TWI (Slave) Address register
+VE_TWAR:
+ .dw $ff04
+ .db "TWAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWAR
+XT_TWAR:
+ .dw PFA_DOVARIABLE
+PFA_TWAR:
+ .dw 186
+
+.endif
+.if WANT_USART1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR1:
+ .dw $ff04
+ .db "UDR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR1
+XT_UDR1:
+ .dw PFA_DOVARIABLE
+PFA_UDR1:
+ .dw 206
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR1A:
+ .dw $ff06
+ .db "UCSR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1A
+XT_UCSR1A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1A:
+ .dw 200
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR1B:
+ .dw $ff06
+ .db "UCSR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1B
+XT_UCSR1B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1B:
+ .dw 201
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR1C:
+ .dw $ff06
+ .db "UCSR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1C
+XT_UCSR1C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1C:
+ .dw 202
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Bytes
+VE_UBRR1:
+ .dw $ff05
+ .db "UBRR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR1
+XT_UBRR1:
+ .dw PFA_DOVARIABLE
+PFA_UBRR1:
+ .dw 204
+
+.endif
+.if WANT_SPI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR:
+ .dw $ff04
+ .db "SPDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR
+XT_SPDR:
+ .dw PFA_DOVARIABLE
+PFA_SPDR:
+ .dw 78
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR:
+ .dw $ff04
+ .db "SPSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR
+XT_SPSR:
+ .dw PFA_DOVARIABLE
+PFA_SPSR:
+ .dw 77
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR:
+ .dw $ff04
+ .db "SPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR
+XT_SPCR:
+ .dw PFA_DOVARIABLE
+PFA_SPCR:
+ .dw 76
+
+.endif
+.if WANT_CPU == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw 95
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer
+VE_SP:
+ .dw $ff02
+ .db "SP"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SP
+XT_SP:
+ .dw PFA_DOVARIABLE
+PFA_SP:
+ .dw 93
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Calibration Value
+VE_OSCCAL:
+ .dw $ff06
+ .db "OSCCAL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSCCAL
+XT_OSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_OSCCAL:
+ .dw 102
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_CLKPR:
+ .dw $ff05
+ .db "CLKPR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKPR
+XT_CLKPR:
+ .dw PFA_DOVARIABLE
+PFA_CLKPR:
+ .dw 97
+; ( -- addr ) System Constant
+; R( -- )
+; Sleep Mode Control Register
+VE_SMCR:
+ .dw $ff04
+ .db "SMCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SMCR
+XT_SMCR:
+ .dw PFA_DOVARIABLE
+PFA_SMCR:
+ .dw 83
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 2
+VE_GPIOR2:
+ .dw $ff06
+ .db "GPIOR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR2
+XT_GPIOR2:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR2:
+ .dw 75
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 1
+VE_GPIOR1:
+ .dw $ff06
+ .db "GPIOR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR1
+XT_GPIOR1:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR1:
+ .dw 74
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 0
+VE_GPIOR0:
+ .dw $ff06
+ .db "GPIOR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR0
+XT_GPIOR0:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR0:
+ .dw 62
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register0
+VE_PRR0:
+ .dw $ff04
+ .db "PRR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR0
+XT_PRR0:
+ .dw PFA_DOVARIABLE
+PFA_PRR0:
+ .dw 100
+
+.endif
diff --git a/amforth-6.5/avr8/devices/atmega644a/device.py b/amforth-6.5/avr8/devices/atmega644a/device.py
new file mode 100644
index 0000000..3d2079d
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega644a/device.py
@@ -0,0 +1,386 @@
+# Generated Automatically
+
+# Partname ATmega644A
+
+MCUREGS = {
+# Interrupt Vectors
+ 'INT0Addr' : '#2', # External Interrupt Request 0
+ 'INT1Addr' : '#4', # External Interrupt Request 1
+ 'INT2Addr' : '#6', # External Interrupt Request 2
+ 'PCINT0Addr' : '#8', # Pin Change Interrupt Request 0
+ 'PCINT1Addr' : '#10', # Pin Change Interrupt Request 1
+ 'PCINT2Addr' : '#12', # Pin Change Interrupt Request 2
+ 'PCINT3Addr' : '#14', # Pin Change Interrupt Request 3
+ 'WDTAddr' : '#16', # Watchdog Time-out Interrupt
+ 'TIMER2_COMPAAddr' : '#18', # Timer/Counter2 Compare Match A
+ 'TIMER2_COMPBAddr' : '#20', # Timer/Counter2 Compare Match B
+ 'TIMER2_OVFAddr' : '#22', # Timer/Counter2 Overflow
+ 'TIMER1_CAPTAddr' : '#24', # Timer/Counter1 Capture Event
+ 'TIMER1_COMPAAddr' : '#26', # Timer/Counter1 Compare Match A
+ 'TIMER1_COMPBAddr' : '#28', # Timer/Counter1 Compare Match B
+ 'TIMER1_OVFAddr' : '#30', # Timer/Counter1 Overflow
+ 'TIMER0_COMPAAddr' : '#32', # Timer/Counter0 Compare Match A
+ 'TIMER0_COMPBAddr' : '#34', # Timer/Counter0 Compare Match B
+ 'TIMER0_OVFAddr' : '#36', # Timer/Counter0 Overflow
+ 'SPI_STCAddr' : '#38', # SPI Serial Transfer Complete
+ 'USART0_RXAddr' : '#40', # USART0, Rx Complete
+ 'USART0_UDREAddr' : '#42', # USART0 Data register Empty
+ 'USART0_TXAddr' : '#44', # USART0, Tx Complete
+ 'ANALOG_COMPAddr' : '#46', # Analog Comparator
+ 'ADCAddr' : '#48', # ADC Conversion Complete
+ 'EE_READYAddr' : '#50', # EEPROM Ready
+ 'TWIAddr' : '#52', # 2-wire Serial Interface
+ 'SPM_READYAddr' : '#54', # Store Program Memory Read
+ 'USART1_RXAddr' : '#56', # USART1 RX complete
+ 'USART1_UDREAddr' : '#58', # USART1 Data Register Empty
+ 'USART1_TXAddr' : '#60', # USART1 TX complete
+
+# Module ANALOG_COMPARATOR
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
+ 'ACSR' : '$50', # Analog Comparator Control And
+ 'ACSR_ACD': '$80', # Analog Comparator Disable
+ 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
+ 'ACSR_ACO': '$20', # Analog Compare Output
+ 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
+ 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
+ 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
+ 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
+ 'DIDR1' : '$7f', # Digital Input Disable Register
+ 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
+ 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
+
+# Module USART0
+ 'UDR0' : '$c6', # USART I/O Data Register
+ 'UCSR0A' : '$c0', # USART Control and Status Regis
+ 'UCSR0A_RXC0': '$80', # USART Receive Complete
+ 'UCSR0A_TXC0': '$40', # USART Transmitt Complete
+ 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
+ 'UCSR0A_FE0': '$10', # Framing Error
+ 'UCSR0A_DOR0': '$8', # Data overRun
+ 'UCSR0A_UPE0': '$4', # Parity Error
+ 'UCSR0A_U2X0': '$2', # Double the USART transmission
+ 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
+ 'UCSR0B' : '$c1', # USART Control and Status Regis
+ 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
+ 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
+ 'UCSR0B_UDRIE0': '$20', # USART Data register Empty Inte
+ 'UCSR0B_RXEN0': '$10', # Receiver Enable
+ 'UCSR0B_TXEN0': '$8', # Transmitter Enable
+ 'UCSR0B_UCSZ02': '$4', # Character Size
+ 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
+ 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
+ 'UCSR0C' : '$c2', # USART Control and Status Regis
+ 'UCSR0C_UMSEL0': '$c0', # USART Mode Select
+ 'UCSR0C_UPM0': '$30', # Parity Mode Bits
+ 'UCSR0C_USBS0': '$8', # Stop Bit Select
+ 'UCSR0C_UCSZ0': '$6', # Character Size
+ 'UCSR0C_UCPOL0': '$1', # Clock Polarity
+ 'UBRR0' : '$c4', # USART Baud Rate Register Byte
+
+# Module PORTA
+ 'PORTA' : '$22', # Port A Data Register
+ 'DDRA' : '$21', # Port A Data Direction Register
+ 'PINA' : '$20', # Port A Input Pins
+
+# Module PORTB
+ 'PORTB' : '$25', # Port B Data Register
+ 'DDRB' : '$24', # Port B Data Direction Register
+ 'PINB' : '$23', # Port B Input Pins
+
+# Module PORTC
+ 'PORTC' : '$28', # Port C Data Register
+ 'DDRC' : '$27', # Port C Data Direction Register
+ 'PINC' : '$26', # Port C Input Pins
+
+# Module PORTD
+ 'PORTD' : '$2b', # Port D Data Register
+ 'DDRD' : '$2a', # Port D Data Direction Register
+ 'PIND' : '$29', # Port D Input Pins
+
+# Module TIMER_COUNTER_0
+ 'OCR0B' : '$48', # Timer/Counter0 Output Compare
+ 'OCR0A' : '$47', # Timer/Counter0 Output Compare
+ 'TCNT0' : '$46', # Timer/Counter0
+ 'TCCR0B' : '$45', # Timer/Counter Control Register
+ 'TCCR0B_FOC0A': '$80', # Force Output Compare A
+ 'TCCR0B_FOC0B': '$40', # Force Output Compare B
+ 'TCCR0B_WGM02': '$8', #
+ 'TCCR0B_CS0': '$7', # Clock Select
+ 'TCCR0A' : '$44', # Timer/Counter Control Registe
+ 'TCCR0A_COM0A': '$c0', # Compare Output Mode, Phase Cor
+ 'TCCR0A_COM0B': '$30', # Compare Output Mode, Fast PWm
+ 'TCCR0A_WGM0': '$3', # Waveform Generation Mode
+ 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
+ 'TIMSK0_OCIE0B': '$4', # Timer/Counter0 Output Compare
+ 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
+ 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
+ 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
+ 'TIFR0_OCF0B': '$4', # Timer/Counter0 Output Compare
+ 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
+ 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSRSYNC': '$1', # Prescaler Reset Timer/Counter1
+
+# Module TIMER_COUNTER_2
+ 'TIMSK2' : '$70', # Timer/Counter Interrupt Mask r
+ 'TIMSK2_OCIE2B': '$4', # Timer/Counter2 Output Compare
+ 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
+ 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
+ 'TIFR2' : '$37', # Timer/Counter Interrupt Flag R
+ 'TIFR2_OCF2B': '$4', # Output Compare Flag 2B
+ 'TIFR2_OCF2A': '$2', # Output Compare Flag 2A
+ 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
+ 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
+ 'TCCR2A_COM2A': '$c0', # Compare Output Mode bits
+ 'TCCR2A_COM2B': '$30', # Compare Output Mode bits
+ 'TCCR2A_WGM2': '$3', # Waveform Genration Mode
+ 'TCCR2B' : '$b1', # Timer/Counter2 Control Registe
+ 'TCCR2B_FOC2A': '$80', # Force Output Compare A
+ 'TCCR2B_FOC2B': '$40', # Force Output Compare B
+ 'TCCR2B_WGM22': '$8', # Waveform Generation Mode
+ 'TCCR2B_CS2': '$7', # Clock Select bits
+ 'TCNT2' : '$b2', # Timer/Counter2
+ 'OCR2B' : '$b4', # Timer/Counter2 Output Compare
+ 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
+ 'ASSR' : '$b6', # Asynchronous Status Register
+ 'ASSR_EXCLK': '$40', # Enable External Clock Input
+ 'ASSR_AS2': '$20', # Asynchronous Timer/Counter2
+ 'ASSR_TCN2UB': '$10', # Timer/Counter2 Update Busy
+ 'ASSR_OCR2AUB': '$8', # Output Compare Register2 Updat
+ 'ASSR_OCR2BUB': '$4', # Output Compare Register 2 Upda
+ 'ASSR_TCR2AUB': '$2', # Timer/Counter Control Register
+ 'ASSR_TCR2BUB': '$1', # Timer/Counter Control Register
+ 'GTCCR' : '$43', # General Timer Counter Control
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSRASY': '$2', # Prescaler Reset Timer/Counter2
+
+# Module WATCHDOG
+ 'WDTCSR' : '$60', # Watchdog Timer Control Registe
+ 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
+ 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
+ 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
+ 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
+ 'WDTCSR_WDE': '$8', # Watch Dog Enable
+
+# Module JTAG
+ 'OCDR' : '$51', # On-Chip Debug Related Register
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_JTD': '$80', # JTAG Interface Disable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+
+# Module BOOT_LOAD
+ 'SPMCSR' : '$57', # Store Program Memory Control R
+ 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
+ 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
+ 'SPMCSR_SIGRD': '$20', # Signature Row Read
+ 'SPMCSR_RWWSRE': '$10', # Read While Write section read
+ 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
+ 'SPMCSR_PGWRT': '$4', # Page Write
+ 'SPMCSR_PGERS': '$2', # Page Erase
+ 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
+
+# Module EXTERNAL_INTERRUPT
+ 'EICRA' : '$69', # External Interrupt Control Reg
+ 'EICRA_ISC2': '$30', # External Interrupt Sense Contr
+ 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
+ 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
+ 'EIMSK' : '$3d', # External Interrupt Mask Regist
+ 'EIMSK_INT': '$7', # External Interrupt Request 2 E
+ 'EIFR' : '$3c', # External Interrupt Flag Regist
+ 'EIFR_INTF': '$7', # External Interrupt Flags
+ 'PCMSK3' : '$73', # Pin Change Mask Register 3
+ 'PCMSK3_PCINT': '$ff', # Pin Change Enable Masks
+ 'PCMSK2' : '$6d', # Pin Change Mask Register 2
+ 'PCMSK2_PCINT': '$ff', # Pin Change Enable Masks
+ 'PCMSK1' : '$6c', # Pin Change Mask Register 1
+ 'PCMSK1_PCINT': '$ff', # Pin Change Enable Masks
+ 'PCMSK0' : '$6b', # Pin Change Mask Register 0
+ 'PCMSK0_PCINT': '$ff', # Pin Change Enable Masks
+ 'PCIFR' : '$3b', # Pin Change Interrupt Flag Regi
+ 'PCIFR_PCIF': '$f', # Pin Change Interrupt Flags
+ 'PCICR' : '$68', # Pin Change Interrupt Control R
+ 'PCICR_PCIE': '$f', # Pin Change Interrupt Enables
+
+# Module AD_CONVERTER
+ 'ADMUX' : '$7c', # The ADC multiplexer Selection
+ 'ADMUX_REFS': '$c0', # Reference Selection Bits
+ 'ADMUX_ADLAR': '$20', # Left Adjust Result
+ 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
+ 'ADC' : '$78', # ADC Data Register Bytes
+ 'ADCSRA' : '$7a', # The ADC Control and Status reg
+ 'ADCSRA_ADEN': '$80', # ADC Enable
+ 'ADCSRA_ADSC': '$40', # ADC Start Conversion
+ 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
+ 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
+ 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
+ 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
+ 'ADCSRB' : '$7b', # The ADC Control and Status reg
+ 'ADCSRB_ACME': '$40', #
+ 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Source bits
+ 'DIDR0' : '$7e', # Digital Input Disable Register
+ 'DIDR0_ADC7D': '$80', #
+ 'DIDR0_ADC6D': '$40', #
+ 'DIDR0_ADC5D': '$20', #
+ 'DIDR0_ADC4D': '$10', #
+ 'DIDR0_ADC3D': '$8', #
+ 'DIDR0_ADC2D': '$4', #
+ 'DIDR0_ADC1D': '$2', #
+ 'DIDR0_ADC0D': '$1', #
+
+# Module TIMER_COUNTER_1
+ 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
+ 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
+ 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
+ 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
+ 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
+ 'TIFR1' : '$36', # Timer/Counter Interrupt Flag r
+ 'TIFR1_ICF1': '$20', # Timer/Counter1 Input Capture F
+ 'TIFR1_OCF1B': '$4', # Timer/Counter1 Output Compare
+ 'TIFR1_OCF1A': '$2', # Timer/Counter1 Output Compare
+ 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
+ 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
+ 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
+ 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
+ 'TCCR1A_WGM1': '$3', # Pulse Width Modulator Select B
+ 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
+ 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
+ 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
+ 'TCCR1B_WGM1': '$18', # Waveform Generation Mode Bits
+ 'TCCR1B_CS1': '$7', # Clock Select1 bits
+ 'TCCR1C' : '$82', # Timer/Counter1 Control Registe
+ 'TCCR1C_FOC1A': '$80', # Force Output Compare for Chann
+ 'TCCR1C_FOC1B': '$40', # Force Output Compare for Chann
+ 'TCNT1' : '$84', # Timer/Counter1 Bytes
+ 'OCR1A' : '$88', # Timer/Counter1 Output Compare
+ 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
+ 'ICR1' : '$86', # Timer/Counter1 Input Capture R
+
+# Module EEPROM
+ 'EEAR' : '$41', # EEPROM Address Register Low By
+ 'EEDR' : '$40', # EEPROM Data Register
+ 'EECR' : '$3f', # EEPROM Control Register
+ 'EECR_EEPM': '$30', # EEPROM Programming Mode Bits
+ 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
+ 'EECR_EEMPE': '$4', # EEPROM Master Write Enable
+ 'EECR_EEPE': '$2', # EEPROM Write Enable
+ 'EECR_EERE': '$1', # EEPROM Read Enable
+
+# Module TWI
+ 'TWAMR' : '$bd', # TWI (Slave) Address Mask Regis
+ 'TWAMR_TWAM': '$fe', #
+ 'TWBR' : '$b8', # TWI Bit Rate register
+ 'TWCR' : '$bc', # TWI Control Register
+ 'TWCR_TWINT': '$80', # TWI Interrupt Flag
+ 'TWCR_TWEA': '$40', # TWI Enable Acknowledge Bit
+ 'TWCR_TWSTA': '$20', # TWI Start Condition Bit
+ 'TWCR_TWSTO': '$10', # TWI Stop Condition Bit
+ 'TWCR_TWWC': '$8', # TWI Write Collition Flag
+ 'TWCR_TWEN': '$4', # TWI Enable Bit
+ 'TWCR_TWIE': '$1', # TWI Interrupt Enable
+ 'TWSR' : '$b9', # TWI Status Register
+ 'TWSR_TWS': '$f8', # TWI Status
+ 'TWSR_TWPS': '$3', # TWI Prescaler
+ 'TWDR' : '$bb', # TWI Data register
+ 'TWAR' : '$ba', # TWI (Slave) Address register
+ 'TWAR_TWA': '$fe', # TWI (Slave) Address register B
+ 'TWAR_TWGCE': '$1', # TWI General Call Recognition E
+
+# Module USART1
+ 'UDR1' : '$ce', # USART I/O Data Register
+ 'UCSR1A' : '$c8', # USART Control and Status Regis
+ 'UCSR1A_RXC1': '$80', # USART Receive Complete
+ 'UCSR1A_TXC1': '$40', # USART Transmitt Complete
+ 'UCSR1A_UDRE1': '$20', # USART Data Register Empty
+ 'UCSR1A_FE1': '$10', # Framing Error
+ 'UCSR1A_DOR1': '$8', # Data overRun
+ 'UCSR1A_UPE1': '$4', # Parity Error
+ 'UCSR1A_U2X1': '$2', # Double the USART transmission
+ 'UCSR1A_MPCM1': '$1', # Multi-processor Communication
+ 'UCSR1B' : '$c9', # USART Control and Status Regis
+ 'UCSR1B_RXCIE1': '$80', # RX Complete Interrupt Enable
+ 'UCSR1B_TXCIE1': '$40', # TX Complete Interrupt Enable
+ 'UCSR1B_UDRIE1': '$20', # USART Data register Empty Inte
+ 'UCSR1B_RXEN1': '$10', # Receiver Enable
+ 'UCSR1B_TXEN1': '$8', # Transmitter Enable
+ 'UCSR1B_UCSZ12': '$4', # Character Size
+ 'UCSR1B_RXB81': '$2', # Receive Data Bit 8
+ 'UCSR1B_TXB81': '$1', # Transmit Data Bit 8
+ 'UCSR1C' : '$ca', # USART Control and Status Regis
+ 'UCSR1C_UMSEL1': '$c0', # USART Mode Select
+ 'UCSR1C_UPM1': '$30', # Parity Mode Bits
+ 'UCSR1C_USBS1': '$8', # Stop Bit Select
+ 'UCSR1C_UCSZ1': '$6', # Character Size
+ 'UCSR1C_UCPOL1': '$1', # Clock Polarity
+ 'UBRR1' : '$cc', # USART Baud Rate Register Byte
+
+# Module SPI
+ 'SPDR' : '$4e', # SPI Data Register
+ 'SPSR' : '$4d', # SPI Status Register
+ 'SPSR_SPIF': '$80', # SPI Interrupt Flag
+ 'SPSR_WCOL': '$40', # Write Collision Flag
+ 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
+ 'SPCR' : '$4c', # SPI Control Register
+ 'SPCR_SPIE': '$80', # SPI Interrupt Enable
+ 'SPCR_SPE': '$40', # SPI Enable
+ 'SPCR_DORD': '$20', # Data Order
+ 'SPCR_MSTR': '$10', # Master/Slave Select
+ 'SPCR_CPOL': '$8', # Clock polarity
+ 'SPCR_CPHA': '$4', # Clock Phase
+ 'SPCR_SPR': '$3', # SPI Clock Rate Selects
+
+# Module CPU
+ 'SREG' : '$5f', # Status Register
+ 'SREG_I': '$80', # Global Interrupt Enable
+ 'SREG_T': '$40', # Bit Copy Storage
+ 'SREG_H': '$20', # Half Carry Flag
+ 'SREG_S': '$10', # Sign Bit
+ 'SREG_V': '$8', # Two's Complement Overflow Flag
+ 'SREG_N': '$4', # Negative Flag
+ 'SREG_Z': '$2', # Zero Flag
+ 'SREG_C': '$1', # Carry Flag
+ 'SP' : '$5d', # Stack Pointer
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_JTD': '$80', # JTAG Interface Disable
+ 'MCUCR_PUD': '$10', # Pull-up disable
+ 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
+ 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+ 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
+ 'MCUSR_BORF': '$4', # Brown-out Reset Flag
+ 'MCUSR_EXTRF': '$2', # External Reset Flag
+ 'MCUSR_PORF': '$1', # Power-on reset flag
+ 'OSCCAL' : '$66', # Oscillator Calibration Value
+ 'CLKPR' : '$61', #
+ 'CLKPR_CLKPCE': '$80', #
+ 'CLKPR_CLKPS': '$f', #
+ 'SMCR' : '$53', # Sleep Mode Control Register
+ 'SMCR_SM': '$e', # Sleep Mode Select bits
+ 'SMCR_SE': '$1', # Sleep Enable
+ 'GPIOR2' : '$4b', # General Purpose IO Register 2
+ 'GPIOR2_GPIOR': '$ff', # General Purpose IO Register 2
+ 'GPIOR1' : '$4a', # General Purpose IO Register 1
+ 'GPIOR1_GPIOR': '$ff', # General Purpose IO Register 1
+ 'GPIOR0' : '$3e', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR07': '$80', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR06': '$40', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR05': '$20', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR04': '$10', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR03': '$8', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR02': '$4', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR01': '$2', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR00': '$1', # General Purpose IO Register 0
+ 'PRR0' : '$64', # Power Reduction Register0
+ 'PRR0_PRTWI': '$80', # Power Reduction TWI
+ 'PRR0_PRTIM2': '$40', # Power Reduction Timer/Counter2
+ 'PRR0_PRTIM0': '$20', # Power Reduction Timer/Counter0
+ 'PRR0_PRUSART': '$12', # Power Reduction USARTs
+ 'PRR0_PRTIM1': '$8', # Power Reduction Timer/Counter1
+ 'PRR0_PRSPI': '$4', # Power Reduction Serial Periphe
+ 'PRR0_PRADC': '$1', # Power Reduction ADC
+
+ '__amforth_dummy':'0'
+}
diff --git a/amforth-6.5/avr8/devices/atmega644a/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega644a/words/no-jtag.asm
new file mode 100644
index 0000000..352a4bb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega644a/words/no-jtag.asm
@@ -0,0 +1,14 @@
+; ( -- )
+; ( -- )
+; MCU
+; disable jtag at runtime
+VE_NOJTAG:
+ .dw $FF05
+ .db "-jtag",0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOJTAG
+XT_NOJTAG:
+ .dw PFA_NOJTAG
+PFA_NOJTAG:
+
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega644a/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega644a/words/no-wdt.asm
new file mode 100644
index 0000000..ff6ddd1
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega644a/words/no-wdt.asm
@@ -0,0 +1,34 @@
+; ( -- )
+; MCU
+; disable watch dog timer at runtime
+VE_NOWDT:
+ .dw $ff04
+ .db "-wdt"
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOWDT
+XT_NOWDT:
+ .dw PFA_NOWDT
+PFA_NOWDT:
+
+ in temp1,SREG
+ push temp1
+ ; Turn always off global interrupt.
+ cli
+ ; Reset Watchdog Timer
+ wdr
+ ; Clear WDRF in MCUSR
+ in temp1, MCUSR
+ andi temp1, (0xff & (0<<WDRF))
+ out MCUSR, temp1
+ ; Write logical one to WDCE and WDE
+ ; Keep old prescaler setting to prevent unintentional time-out
+ in_ temp1, WDTCSR
+ ori temp1, (1<<WDCE) | (1<<WDE)
+ out_ WDTCSR, temp1
+ ; Turn off WDT
+ ldi temp1, (0<<WDE)
+ out_ WDTCSR, temp1
+ ; restore status register
+ pop temp1
+ out SREG,temp1
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega644a/words/sleep.asm b/amforth-6.5/avr8/devices/atmega644a/words/sleep.asm
new file mode 100644
index 0000000..256249c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega644a/words/sleep.asm
@@ -0,0 +1,19 @@
+; ( mode -- )
+; MCU
+; put the controller into the specified sleep mode
+VE_SLEEP:
+ .dw $ff05
+ .db "sleep", 0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_SLEEP
+XT_SLEEP:
+ .dw PFA_SLEEP
+PFA_SLEEP:
+ andi tosl, 7 ; leave only legal mode bits
+ lsl tosl ; move to correct location (bits 3-1)
+ ori tosl, 1 ; set the SE bit
+ out_ SMCR, tosl ; set the sleep config
+ sleep ; nighty-night
+ out_ SMCR, zerol ; 0 protects against accidental sleeps
+ loadtos ; pop argument from stack
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega644p/atmega644p.frt b/amforth-6.5/avr8/devices/atmega644p/atmega644p.frt
new file mode 100644
index 0000000..8bc29af
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega644p/atmega644p.frt
@@ -0,0 +1,346 @@
+\ Partname: ATmega644P
+\ generated automatically
+
+\ ANALOG_COMPARATOR
+&123 constant ADCSRB \ ADC Control and Status Register B
+ $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer Enable
+&80 constant ACSR \ Analog Comparator Control And Status Register
+ $80 constant ACSR_ACD \ Analog Comparator Disable
+ $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
+ $20 constant ACSR_ACO \ Analog Compare Output
+ $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
+ $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
+ $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
+ $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
+&127 constant DIDR1 \ Digital Input Disable Register 1
+ $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
+ $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
+\ USART0
+&198 constant UDR0 \ USART I/O Data Register
+&192 constant UCSR0A \ USART Control and Status Register A
+ $80 constant UCSR0A_RXC0 \ USART Receive Complete
+ $40 constant UCSR0A_TXC0 \ USART Transmitt Complete
+ $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
+ $10 constant UCSR0A_FE0 \ Framing Error
+ $08 constant UCSR0A_DOR0 \ Data overRun
+ $04 constant UCSR0A_UPE0 \ Parity Error
+ $02 constant UCSR0A_U2X0 \ Double the USART transmission speed
+ $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
+&193 constant UCSR0B \ USART Control and Status Register B
+ $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
+ $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
+ $20 constant UCSR0B_UDRIE0 \ USART Data register Empty Interrupt Enable
+ $10 constant UCSR0B_RXEN0 \ Receiver Enable
+ $08 constant UCSR0B_TXEN0 \ Transmitter Enable
+ $04 constant UCSR0B_UCSZ02 \ Character Size
+ $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
+ $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
+&194 constant UCSR0C \ USART Control and Status Register C
+ $C0 constant UCSR0C_UMSEL0 \ USART Mode Select
+ $30 constant UCSR0C_UPM0 \ Parity Mode Bits
+ $08 constant UCSR0C_USBS0 \ Stop Bit Select
+ $06 constant UCSR0C_UCSZ0 \ Character Size
+ $01 constant UCSR0C_UCPOL0 \ Clock Polarity
+&196 constant UBRR0 \ USART Baud Rate Register Bytes
+\ PORTA
+&34 constant PORTA \ Port A Data Register
+&33 constant DDRA \ Port A Data Direction Register
+&32 constant PINA \ Port A Input Pins
+\ PORTB
+&37 constant PORTB \ Port B Data Register
+&36 constant DDRB \ Port B Data Direction Register
+&35 constant PINB \ Port B Input Pins
+\ PORTC
+&40 constant PORTC \ Port C Data Register
+&39 constant DDRC \ Port C Data Direction Register
+&38 constant PINC \ Port C Input Pins
+\ PORTD
+&43 constant PORTD \ Port D Data Register
+&42 constant DDRD \ Port D Data Direction Register
+&41 constant PIND \ Port D Input Pins
+\ TIMER_COUNTER_0
+&72 constant OCR0B \ Timer/Counter0 Output Compare Register
+&71 constant OCR0A \ Timer/Counter0 Output Compare Register
+&70 constant TCNT0 \ Timer/Counter0
+&69 constant TCCR0B \ Timer/Counter Control Register B
+ $80 constant TCCR0B_FOC0A \ Force Output Compare A
+ $40 constant TCCR0B_FOC0B \ Force Output Compare B
+ $08 constant TCCR0B_WGM02 \
+ $07 constant TCCR0B_CS0 \ Clock Select
+&68 constant TCCR0A \ Timer/Counter Control Register A
+ $C0 constant TCCR0A_COM0A \ Compare Output Mode, Phase Correct PWM Mode
+ $30 constant TCCR0A_COM0B \ Compare Output Mode, Fast PWm
+ $03 constant TCCR0A_WGM0 \ Waveform Generation Mode
+&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
+ $04 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare Match B Interrupt Enable
+ $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match A Interrupt Enable
+ $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
+&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
+ $04 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare Flag 0B
+ $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0A
+ $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
+&67 constant GTCCR \ General Timer/Counter Control Register
+ $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
+ $01 constant GTCCR_PSRSYNC \ Prescaler Reset Timer/Counter1 and Timer/Counter0
+\ TIMER_COUNTER_2
+&112 constant TIMSK2 \ Timer/Counter Interrupt Mask register
+ $04 constant TIMSK2_OCIE2B \ Timer/Counter2 Output Compare Match B Interrupt Enable
+ $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match A Interrupt Enable
+ $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
+&55 constant TIFR2 \ Timer/Counter Interrupt Flag Register
+ $04 constant TIFR2_OCF2B \ Output Compare Flag 2B
+ $02 constant TIFR2_OCF2A \ Output Compare Flag 2A
+ $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
+&176 constant TCCR2A \ Timer/Counter2 Control Register A
+ $C0 constant TCCR2A_COM2A \ Compare Output Mode bits
+ $30 constant TCCR2A_COM2B \ Compare Output Mode bits
+ $03 constant TCCR2A_WGM2 \ Waveform Genration Mode
+&177 constant TCCR2B \ Timer/Counter2 Control Register B
+ $80 constant TCCR2B_FOC2A \ Force Output Compare A
+ $40 constant TCCR2B_FOC2B \ Force Output Compare B
+ $08 constant TCCR2B_WGM22 \ Waveform Generation Mode
+ $07 constant TCCR2B_CS2 \ Clock Select bits
+&178 constant TCNT2 \ Timer/Counter2
+&180 constant OCR2B \ Timer/Counter2 Output Compare Register B
+&179 constant OCR2A \ Timer/Counter2 Output Compare Register A
+&182 constant ASSR \ Asynchronous Status Register
+ $40 constant ASSR_EXCLK \ Enable External Clock Input
+ $20 constant ASSR_AS2 \ Asynchronous Timer/Counter2
+ $10 constant ASSR_TCN2UB \ Timer/Counter2 Update Busy
+ $08 constant ASSR_OCR2AUB \ Output Compare Register2 Update Busy
+ $04 constant ASSR_OCR2BUB \ Output Compare Register 2 Update Busy
+ $02 constant ASSR_TCR2AUB \ Timer/Counter Control Register2 Update Busy
+ $01 constant ASSR_TCR2BUB \ Timer/Counter Control Register2 Update Busy
+\ WATCHDOG
+&96 constant WDTCSR \ Watchdog Timer Control Register
+ $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Flag
+ $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Enable
+ $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
+ $10 constant WDTCSR_WDCE \ Watchdog Change Enable
+ $08 constant WDTCSR_WDE \ Watch Dog Enable
+\ JTAG
+&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
+&85 constant MCUCR \ MCU Control Register
+ $80 constant MCUCR_JTD \ JTAG Interface Disable
+&84 constant MCUSR \ MCU Status Register
+ $10 constant MCUSR_JTRF \ JTAG Reset Flag
+\ BOOT_LOAD
+&87 constant SPMCSR \ Store Program Memory Control Register
+ $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
+ $20 constant SPMCSR_SIGRD \ Signature Row Read
+ $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
+ $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
+ $04 constant SPMCSR_PGWRT \ Page Write
+ $02 constant SPMCSR_PGERS \ Page Erase
+ $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
+\ EXTERNAL_INTERRUPT
+&105 constant EICRA \ External Interrupt Control Register A
+ $30 constant EICRA_ISC2 \ External Interrupt Sense Control Bit
+ $0C constant EICRA_ISC1 \ External Interrupt Sense Control Bit
+ $03 constant EICRA_ISC0 \ External Interrupt Sense Control Bit
+&61 constant EIMSK \ External Interrupt Mask Register
+ $07 constant EIMSK_INT \ External Interrupt Request 2 Enable
+&60 constant EIFR \ External Interrupt Flag Register
+ $07 constant EIFR_INTF \ External Interrupt Flags
+&115 constant PCMSK3 \ Pin Change Mask Register 3
+ $FF constant PCMSK3_PCINT \ Pin Change Enable Masks
+&109 constant PCMSK2 \ Pin Change Mask Register 2
+ $FF constant PCMSK2_PCINT \ Pin Change Enable Masks
+&108 constant PCMSK1 \ Pin Change Mask Register 1
+ $FF constant PCMSK1_PCINT \ Pin Change Enable Masks
+&107 constant PCMSK0 \ Pin Change Mask Register 0
+ $FF constant PCMSK0_PCINT \ Pin Change Enable Masks
+&59 constant PCIFR \ Pin Change Interrupt Flag Register
+ $0F constant PCIFR_PCIF \ Pin Change Interrupt Flags
+&104 constant PCICR \ Pin Change Interrupt Control Register
+ $0F constant PCICR_PCIE \ Pin Change Interrupt Enables
+\ AD_CONVERTER
+&124 constant ADMUX \ The ADC multiplexer Selection Register
+ $C0 constant ADMUX_REFS \ Reference Selection Bits
+ $20 constant ADMUX_ADLAR \ Left Adjust Result
+ $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
+&120 constant ADC \ ADC Data Register Bytes
+&122 constant ADCSRA \ The ADC Control and Status register A
+ $80 constant ADCSRA_ADEN \ ADC Enable
+ $40 constant ADCSRA_ADSC \ ADC Start Conversion
+ $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
+ $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
+ $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
+ $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
+&126 constant DIDR0 \ Digital Input Disable Register
+ $80 constant DIDR0_ADC7D \
+ $40 constant DIDR0_ADC6D \
+ $20 constant DIDR0_ADC5D \
+ $10 constant DIDR0_ADC4D \
+ $08 constant DIDR0_ADC3D \
+ $04 constant DIDR0_ADC2D \
+ $02 constant DIDR0_ADC1D \
+ $01 constant DIDR0_ADC0D \
+\ TIMER_COUNTER_1
+&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
+ $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
+ $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
+ $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
+ $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
+&54 constant TIFR1 \ Timer/Counter Interrupt Flag register
+ $20 constant TIFR1_ICF1 \ Timer/Counter1 Input Capture Flag
+ $04 constant TIFR1_OCF1B \ Timer/Counter1 Output Compare B Match Flag
+ $02 constant TIFR1_OCF1A \ Timer/Counter1 Output Compare A Match Flag
+ $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
+&128 constant TCCR1A \ Timer/Counter1 Control Register A
+ $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
+ $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
+ $03 constant TCCR1A_WGM1 \ Pulse Width Modulator Select Bits
+&129 constant TCCR1B \ Timer/Counter1 Control Register B
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ $18 constant TCCR1B_WGM1 \ Waveform Generation Mode Bits
+ $07 constant TCCR1B_CS1 \ Clock Select1 bits
+&130 constant TCCR1C \ Timer/Counter1 Control Register C
+ $80 constant TCCR1C_FOC1A \ Force Output Compare for Channel A
+ $40 constant TCCR1C_FOC1B \ Force Output Compare for Channel B
+&132 constant TCNT1 \ Timer/Counter1 Bytes
+&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
+&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
+&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
+\ EEPROM
+&65 constant EEAR \ EEPROM Address Register Low Bytes
+&64 constant EEDR \ EEPROM Data Register
+&63 constant EECR \ EEPROM Control Register
+ $30 constant EECR_EEPM \ EEPROM Programming Mode Bits
+ $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
+ $04 constant EECR_EEMPE \ EEPROM Master Write Enable
+ $02 constant EECR_EEPE \ EEPROM Write Enable
+ $01 constant EECR_EERE \ EEPROM Read Enable
+\ TWI
+&189 constant TWAMR \ TWI (Slave) Address Mask Register
+ $FE constant TWAMR_TWAM \
+&184 constant TWBR \ TWI Bit Rate register
+&188 constant TWCR \ TWI Control Register
+ $80 constant TWCR_TWINT \ TWI Interrupt Flag
+ $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
+ $20 constant TWCR_TWSTA \ TWI Start Condition Bit
+ $10 constant TWCR_TWSTO \ TWI Stop Condition Bit
+ $08 constant TWCR_TWWC \ TWI Write Collition Flag
+ $04 constant TWCR_TWEN \ TWI Enable Bit
+ $01 constant TWCR_TWIE \ TWI Interrupt Enable
+&185 constant TWSR \ TWI Status Register
+ $F8 constant TWSR_TWS \ TWI Status
+ $03 constant TWSR_TWPS \ TWI Prescaler
+&187 constant TWDR \ TWI Data register
+&186 constant TWAR \ TWI (Slave) Address register
+ $FE constant TWAR_TWA \ TWI (Slave) Address register Bits
+ $01 constant TWAR_TWGCE \ TWI General Call Recognition Enable Bit
+\ USART1
+&206 constant UDR1 \ USART I/O Data Register
+&200 constant UCSR1A \ USART Control and Status Register A
+ $80 constant UCSR1A_RXC1 \ USART Receive Complete
+ $40 constant UCSR1A_TXC1 \ USART Transmitt Complete
+ $20 constant UCSR1A_UDRE1 \ USART Data Register Empty
+ $10 constant UCSR1A_FE1 \ Framing Error
+ $08 constant UCSR1A_DOR1 \ Data overRun
+ $04 constant UCSR1A_UPE1 \ Parity Error
+ $02 constant UCSR1A_U2X1 \ Double the USART transmission speed
+ $01 constant UCSR1A_MPCM1 \ Multi-processor Communication Mode
+&201 constant UCSR1B \ USART Control and Status Register B
+ $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable
+ $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable
+ $20 constant UCSR1B_UDRIE1 \ USART Data register Empty Interrupt Enable
+ $10 constant UCSR1B_RXEN1 \ Receiver Enable
+ $08 constant UCSR1B_TXEN1 \ Transmitter Enable
+ $04 constant UCSR1B_UCSZ12 \ Character Size
+ $02 constant UCSR1B_RXB81 \ Receive Data Bit 8
+ $01 constant UCSR1B_TXB81 \ Transmit Data Bit 8
+&202 constant UCSR1C \ USART Control and Status Register C
+ $C0 constant UCSR1C_UMSEL1 \ USART Mode Select
+ $30 constant UCSR1C_UPM1 \ Parity Mode Bits
+ $08 constant UCSR1C_USBS1 \ Stop Bit Select
+ $06 constant UCSR1C_UCSZ1 \ Character Size
+ $01 constant UCSR1C_UCPOL1 \ Clock Polarity
+&204 constant UBRR1 \ USART Baud Rate Register Bytes
+\ CPU
+&95 constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ $08 constant SREG_V \ Two's Complement Overflow Flag
+ $04 constant SREG_N \ Negative Flag
+ $02 constant SREG_Z \ Zero Flag
+ $01 constant SREG_C \ Carry Flag
+&93 constant SP \ Stack Pointer
+&102 constant OSCCAL \ Oscillator Calibration Value
+&97 constant CLKPR \
+ $80 constant CLKPR_CLKPCE \
+ $0F constant CLKPR_CLKPS \
+&83 constant SMCR \ Sleep Mode Control Register
+ $0E constant SMCR_SM \ Sleep Mode Select bits
+ $01 constant SMCR_SE \ Sleep Enable
+&75 constant GPIOR2 \ General Purpose IO Register 2
+ $FF constant GPIOR2_GPIOR \ General Purpose IO Register 2 bis
+&74 constant GPIOR1 \ General Purpose IO Register 1
+ $FF constant GPIOR1_GPIOR \ General Purpose IO Register 1 bis
+&62 constant GPIOR0 \ General Purpose IO Register 0
+ $80 constant GPIOR0_GPIOR07 \ General Purpose IO Register 0 bit 7
+ $40 constant GPIOR0_GPIOR06 \ General Purpose IO Register 0 bit 6
+ $20 constant GPIOR0_GPIOR05 \ General Purpose IO Register 0 bit 5
+ $10 constant GPIOR0_GPIOR04 \ General Purpose IO Register 0 bit 4
+ $08 constant GPIOR0_GPIOR03 \ General Purpose IO Register 0 bit 3
+ $04 constant GPIOR0_GPIOR02 \ General Purpose IO Register 0 bit 2
+ $02 constant GPIOR0_GPIOR01 \ General Purpose IO Register 0 bit 1
+ $01 constant GPIOR0_GPIOR00 \ General Purpose IO Register 0 bit 0
+&100 constant PRR0 \ Power Reduction Register0
+ $80 constant PRR0_PRTWI \ Power Reduction TWI
+ $40 constant PRR0_PRTIM2 \ Power Reduction Timer/Counter2
+ $20 constant PRR0_PRTIM0 \ Power Reduction Timer/Counter0
+ $12 constant PRR0_PRUSART \ Power Reduction USARTs
+ $08 constant PRR0_PRTIM1 \ Power Reduction Timer/Counter1
+ $04 constant PRR0_PRSPI \ Power Reduction Serial Peripheral Interface
+ $01 constant PRR0_PRADC \ Power Reduction ADC
+\ SPI
+&78 constant SPDR \ SPI Data Register
+&77 constant SPSR \ SPI Status Register
+ $80 constant SPSR_SPIF \ SPI Interrupt Flag
+ $40 constant SPSR_WCOL \ Write Collision Flag
+ $01 constant SPSR_SPI2X \ Double SPI Speed Bit
+&76 constant SPCR \ SPI Control Register
+ $80 constant SPCR_SPIE \ SPI Interrupt Enable
+ $40 constant SPCR_SPE \ SPI Enable
+ $20 constant SPCR_DORD \ Data Order
+ $10 constant SPCR_MSTR \ Master/Slave Select
+ $08 constant SPCR_CPOL \ Clock polarity
+ $04 constant SPCR_CPHA \ Clock Phase
+ $03 constant SPCR_SPR \ SPI Clock Rate Selects
+
+\ Interrupts
+&2 constant INT0Addr \ External Interrupt Request 0
+&4 constant INT1Addr \ External Interrupt Request 1
+&6 constant INT2Addr \ External Interrupt Request 2
+&8 constant PCINT0Addr \ Pin Change Interrupt Request 0
+&10 constant PCINT1Addr \ Pin Change Interrupt Request 1
+&12 constant PCINT2Addr \ Pin Change Interrupt Request 2
+&14 constant PCINT3Addr \ Pin Change Interrupt Request 3
+&16 constant WDTAddr \ Watchdog Time-out Interrupt
+&18 constant TIMER2_COMPAAddr \ Timer/Counter2 Compare Match A
+&20 constant TIMER2_COMPBAddr \ Timer/Counter2 Compare Match B
+&22 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
+&24 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+&26 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
+&28 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
+&30 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+&32 constant TIMER0_COMPAAddr \ Timer/Counter0 Compare Match A
+&34 constant TIMER0_COMPBAddr \ Timer/Counter0 Compare Match B
+&36 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
+&38 constant SPI__STCAddr \ SPI Serial Transfer Complete
+&40 constant USART0__RXAddr \ USART0, Rx Complete
+&42 constant USART0__UDREAddr \ USART0 Data register Empty
+&44 constant USART0__TXAddr \ USART0, Tx Complete
+&46 constant ANALOG_COMPAddr \ Analog Comparator
+&48 constant ADCAddr \ ADC Conversion Complete
+&50 constant EE_READYAddr \ EEPROM Ready
+&52 constant TWIAddr \ 2-wire Serial Interface
+&54 constant SPM_READYAddr \ Store Program Memory Read
+&56 constant USART1_RXAddr \ USART1 RX complete
+&58 constant USART1_UDREAddr \ USART1 Data Register Empty
+&60 constant USART1_TXAddr \ USART1 TX complete
diff --git a/amforth-6.5/avr8/devices/atmega644p/device.asm b/amforth-6.5/avr8/devices/atmega644p/device.asm
new file mode 100644
index 0000000..0385a8b
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega644p/device.asm
@@ -0,0 +1,120 @@
+; Partname: ATmega644P
+; generated automatically, do not edit
+
+.nolist
+ .include "m644Pdef.inc"
+.list
+
+.equ ramstart = 256
+.equ CELLSIZE = 2
+.macro readflashcell
+ lsl zl
+ rol zh
+ lpm @0, Z+
+ lpm @1, Z+
+.endmacro
+.macro writeflashcell
+ lsl zl
+ rol zh
+.endmacro
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_USART0 = 0
+.set WANT_PORTA = 0
+.set WANT_PORTB = 0
+.set WANT_PORTC = 0
+.set WANT_PORTD = 0
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_TIMER_COUNTER_2 = 0
+.set WANT_WATCHDOG = 0
+.set WANT_JTAG = 0
+.set WANT_BOOT_LOAD = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_AD_CONVERTER = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_EEPROM = 0
+.set WANT_TWI = 0
+.set WANT_USART1 = 0
+.set WANT_CPU = 0
+.set WANT_SPI = 0
+.equ intvecsize = 2 ; please verify; flash size: 65536 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.org 2
+ rcall isr ; External Interrupt Request 0
+.org 4
+ rcall isr ; External Interrupt Request 1
+.org 6
+ rcall isr ; External Interrupt Request 2
+.org 8
+ rcall isr ; Pin Change Interrupt Request 0
+.org 10
+ rcall isr ; Pin Change Interrupt Request 1
+.org 12
+ rcall isr ; Pin Change Interrupt Request 2
+.org 14
+ rcall isr ; Pin Change Interrupt Request 3
+.org 16
+ rcall isr ; Watchdog Time-out Interrupt
+.org 18
+ rcall isr ; Timer/Counter2 Compare Match A
+.org 20
+ rcall isr ; Timer/Counter2 Compare Match B
+.org 22
+ rcall isr ; Timer/Counter2 Overflow
+.org 24
+ rcall isr ; Timer/Counter1 Capture Event
+.org 26
+ rcall isr ; Timer/Counter1 Compare Match A
+.org 28
+ rcall isr ; Timer/Counter1 Compare Match B
+.org 30
+ rcall isr ; Timer/Counter1 Overflow
+.org 32
+ rcall isr ; Timer/Counter0 Compare Match A
+.org 34
+ rcall isr ; Timer/Counter0 Compare Match B
+.org 36
+ rcall isr ; Timer/Counter0 Overflow
+.org 38
+ rcall isr ; SPI Serial Transfer Complete
+.org 40
+ rcall isr ; USART0, Rx Complete
+.org 42
+ rcall isr ; USART0 Data register Empty
+.org 44
+ rcall isr ; USART0, Tx Complete
+.org 46
+ rcall isr ; Analog Comparator
+.org 48
+ rcall isr ; ADC Conversion Complete
+.org 50
+ rcall isr ; EEPROM Ready
+.org 52
+ rcall isr ; 2-wire Serial Interface
+.org 54
+ rcall isr ; Store Program Memory Read
+.org 56
+ rcall isr ; USART1 RX complete
+.org 58
+ rcall isr ; USART1 Data Register Empty
+.org 60
+ rcall isr ; USART1 TX complete
+.equ INTVECTORS = 31
+.nooverlap
+
+; compatability layer (maybe empty)
+
+; controller data area, environment query mcu-info
+mcu_info:
+mcu_ramsize:
+ .dw 4096
+mcu_eepromsize:
+ .dw 2048
+mcu_maxdp:
+ .dw 57344
+mcu_numints:
+ .dw 31
+mcu_name:
+ .dw 10
+ .db "ATmega644P"
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega644p/device.inc b/amforth-6.5/avr8/devices/atmega644p/device.inc
new file mode 100644
index 0000000..4a3b68a
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega644p/device.inc
@@ -0,0 +1,1128 @@
+; Partname: ATmega644P
+; generated automatically, no not edit
+
+.if WANT_ANALOG_COMPARATOR == 1
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Control and Status Register B
+VE_ADCSRB:
+ .dw $ff06
+ .db "ADCSRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRB
+XT_ADCSRB:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRB:
+ .dw 123
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Control And Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw 80
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 1
+VE_DIDR1:
+ .dw $ff05
+ .db "DIDR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR1
+XT_DIDR1:
+ .dw PFA_DOVARIABLE
+PFA_DIDR1:
+ .dw 127
+
+.endif
+.if WANT_USART0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR0:
+ .dw $ff04
+ .db "UDR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR0
+XT_UDR0:
+ .dw PFA_DOVARIABLE
+PFA_UDR0:
+ .dw 198
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR0A:
+ .dw $ff06
+ .db "UCSR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0A
+XT_UCSR0A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0A:
+ .dw 192
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR0B:
+ .dw $ff06
+ .db "UCSR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0B
+XT_UCSR0B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0B:
+ .dw 193
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR0C:
+ .dw $ff06
+ .db "UCSR0C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0C
+XT_UCSR0C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0C:
+ .dw 194
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Bytes
+VE_UBRR0:
+ .dw $ff05
+ .db "UBRR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR0
+XT_UBRR0:
+ .dw PFA_DOVARIABLE
+PFA_UBRR0:
+ .dw 196
+
+.endif
+.if WANT_PORTA == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Register
+VE_PORTA:
+ .dw $ff05
+ .db "PORTA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTA
+XT_PORTA:
+ .dw PFA_DOVARIABLE
+PFA_PORTA:
+ .dw 34
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Direction Register
+VE_DDRA:
+ .dw $ff04
+ .db "DDRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRA
+XT_DDRA:
+ .dw PFA_DOVARIABLE
+PFA_DDRA:
+ .dw 33
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Input Pins
+VE_PINA:
+ .dw $ff04
+ .db "PINA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINA
+XT_PINA:
+ .dw PFA_DOVARIABLE
+PFA_PINA:
+ .dw 32
+
+.endif
+.if WANT_PORTB == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw 37
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw 36
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw 35
+
+.endif
+.if WANT_PORTC == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Register
+VE_PORTC:
+ .dw $ff05
+ .db "PORTC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTC
+XT_PORTC:
+ .dw PFA_DOVARIABLE
+PFA_PORTC:
+ .dw 40
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Direction Register
+VE_DDRC:
+ .dw $ff04
+ .db "DDRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRC
+XT_DDRC:
+ .dw PFA_DOVARIABLE
+PFA_DDRC:
+ .dw 39
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Input Pins
+VE_PINC:
+ .dw $ff04
+ .db "PINC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINC
+XT_PINC:
+ .dw PFA_DOVARIABLE
+PFA_PINC:
+ .dw 38
+
+.endif
+.if WANT_PORTD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw 43
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw 42
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw 41
+
+.endif
+.if WANT_TIMER_COUNTER_0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0B:
+ .dw $ff05
+ .db "OCR0B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0B
+XT_OCR0B:
+ .dw PFA_DOVARIABLE
+PFA_OCR0B:
+ .dw 72
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0A:
+ .dw $ff05
+ .db "OCR0A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0A
+XT_OCR0A:
+ .dw PFA_DOVARIABLE
+PFA_OCR0A:
+ .dw 71
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw 70
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register B
+VE_TCCR0B:
+ .dw $ff06
+ .db "TCCR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0B
+XT_TCCR0B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0B:
+ .dw 69
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register A
+VE_TCCR0A:
+ .dw $ff06
+ .db "TCCR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0A
+XT_TCCR0A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0A:
+ .dw 68
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Mask Register
+VE_TIMSK0:
+ .dw $ff06
+ .db "TIMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK0
+XT_TIMSK0:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK0:
+ .dw 110
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Flag register
+VE_TIFR0:
+ .dw $ff05
+ .db "TIFR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR0
+XT_TIFR0:
+ .dw PFA_DOVARIABLE
+PFA_TIFR0:
+ .dw 53
+; ( -- addr ) System Constant
+; R( -- )
+; General Timer/Counter Control Register
+VE_GTCCR:
+ .dw $ff05
+ .db "GTCCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GTCCR
+XT_GTCCR:
+ .dw PFA_DOVARIABLE
+PFA_GTCCR:
+ .dw 67
+
+.endif
+.if WANT_TIMER_COUNTER_2 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Mask register
+VE_TIMSK2:
+ .dw $ff06
+ .db "TIMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK2
+XT_TIMSK2:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK2:
+ .dw 112
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Flag Register
+VE_TIFR2:
+ .dw $ff05
+ .db "TIFR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR2
+XT_TIFR2:
+ .dw PFA_DOVARIABLE
+PFA_TIFR2:
+ .dw 55
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register A
+VE_TCCR2A:
+ .dw $ff06
+ .db "TCCR2A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2A
+XT_TCCR2A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2A:
+ .dw 176
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register B
+VE_TCCR2B:
+ .dw $ff06
+ .db "TCCR2B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2B
+XT_TCCR2B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2B:
+ .dw 177
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2
+VE_TCNT2:
+ .dw $ff05
+ .db "TCNT2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT2
+XT_TCNT2:
+ .dw PFA_DOVARIABLE
+PFA_TCNT2:
+ .dw 178
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register B
+VE_OCR2B:
+ .dw $ff05
+ .db "OCR2B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2B
+XT_OCR2B:
+ .dw PFA_DOVARIABLE
+PFA_OCR2B:
+ .dw 180
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register A
+VE_OCR2A:
+ .dw $ff05
+ .db "OCR2A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2A
+XT_OCR2A:
+ .dw PFA_DOVARIABLE
+PFA_OCR2A:
+ .dw 179
+; ( -- addr ) System Constant
+; R( -- )
+; Asynchronous Status Register
+VE_ASSR:
+ .dw $ff04
+ .db "ASSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ASSR
+XT_ASSR:
+ .dw PFA_DOVARIABLE
+PFA_ASSR:
+ .dw 182
+
+.endif
+.if WANT_WATCHDOG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCSR:
+ .dw $ff06
+ .db "WDTCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCSR
+XT_WDTCSR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCSR:
+ .dw 96
+
+.endif
+.if WANT_JTAG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; On-Chip Debug Related Register in I/O Memory
+VE_OCDR:
+ .dw $ff04
+ .db "OCDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCDR
+XT_OCDR:
+ .dw PFA_DOVARIABLE
+PFA_OCDR:
+ .dw 81
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw 85
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Status Register
+VE_MCUSR:
+ .dw $ff05
+ .db "MCUSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUSR
+XT_MCUSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUSR:
+ .dw 84
+
+.endif
+.if WANT_BOOT_LOAD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control Register
+VE_SPMCSR:
+ .dw $ff06
+ .db "SPMCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCSR
+XT_SPMCSR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCSR:
+ .dw 87
+
+.endif
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register A
+VE_EICRA:
+ .dw $ff05
+ .db "EICRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRA
+XT_EICRA:
+ .dw PFA_DOVARIABLE
+PFA_EICRA:
+ .dw 105
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Mask Register
+VE_EIMSK:
+ .dw $ff05
+ .db "EIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIMSK
+XT_EIMSK:
+ .dw PFA_DOVARIABLE
+PFA_EIMSK:
+ .dw 61
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Flag Register
+VE_EIFR:
+ .dw $ff04
+ .db "EIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIFR
+XT_EIFR:
+ .dw PFA_DOVARIABLE
+PFA_EIFR:
+ .dw 60
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 3
+VE_PCMSK3:
+ .dw $ff06
+ .db "PCMSK3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK3
+XT_PCMSK3:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK3:
+ .dw 115
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 2
+VE_PCMSK2:
+ .dw $ff06
+ .db "PCMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK2
+XT_PCMSK2:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK2:
+ .dw 109
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 1
+VE_PCMSK1:
+ .dw $ff06
+ .db "PCMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK1
+XT_PCMSK1:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK1:
+ .dw 108
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 0
+VE_PCMSK0:
+ .dw $ff06
+ .db "PCMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK0
+XT_PCMSK0:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK0:
+ .dw 107
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Interrupt Flag Register
+VE_PCIFR:
+ .dw $ff05
+ .db "PCIFR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCIFR
+XT_PCIFR:
+ .dw PFA_DOVARIABLE
+PFA_PCIFR:
+ .dw 59
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Interrupt Control Register
+VE_PCICR:
+ .dw $ff05
+ .db "PCICR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCICR
+XT_PCICR:
+ .dw PFA_DOVARIABLE
+PFA_PCICR:
+ .dw 104
+
+.endif
+.if WANT_AD_CONVERTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC multiplexer Selection Register
+VE_ADMUX:
+ .dw $ff05
+ .db "ADMUX",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADMUX
+XT_ADMUX:
+ .dw PFA_DOVARIABLE
+PFA_ADMUX:
+ .dw 124
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register Bytes
+VE_ADC:
+ .dw $ff03
+ .db "ADC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADC
+XT_ADC:
+ .dw PFA_DOVARIABLE
+PFA_ADC:
+ .dw 120
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register A
+VE_ADCSRA:
+ .dw $ff06
+ .db "ADCSRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRA
+XT_ADCSRA:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRA:
+ .dw 122
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register
+VE_DIDR0:
+ .dw $ff05
+ .db "DIDR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR0
+XT_DIDR0:
+ .dw PFA_DOVARIABLE
+PFA_DIDR0:
+ .dw 126
+
+.endif
+.if WANT_TIMER_COUNTER_1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Mask Register
+VE_TIMSK1:
+ .dw $ff06
+ .db "TIMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK1
+XT_TIMSK1:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK1:
+ .dw 111
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Flag register
+VE_TIFR1:
+ .dw $ff05
+ .db "TIFR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR1
+XT_TIFR1:
+ .dw PFA_DOVARIABLE
+PFA_TIFR1:
+ .dw 54
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw 128
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw 129
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register C
+VE_TCCR1C:
+ .dw $ff06
+ .db "TCCR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1C
+XT_TCCR1C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1C:
+ .dw 130
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Bytes
+VE_TCNT1:
+ .dw $ff05
+ .db "TCNT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1
+XT_TCNT1:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1:
+ .dw 132
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register A Bytes
+VE_OCR1A:
+ .dw $ff05
+ .db "OCR1A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1A
+XT_OCR1A:
+ .dw PFA_DOVARIABLE
+PFA_OCR1A:
+ .dw 136
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register B Bytes
+VE_OCR1B:
+ .dw $ff05
+ .db "OCR1B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1B
+XT_OCR1B:
+ .dw PFA_DOVARIABLE
+PFA_OCR1B:
+ .dw 138
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Bytes
+VE_ICR1:
+ .dw $ff04
+ .db "ICR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1
+XT_ICR1:
+ .dw PFA_DOVARIABLE
+PFA_ICR1:
+ .dw 134
+
+.endif
+.if WANT_EEPROM == 1
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Address Register Low Bytes
+VE_EEAR:
+ .dw $ff04
+ .db "EEAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEAR
+XT_EEAR:
+ .dw PFA_DOVARIABLE
+PFA_EEAR:
+ .dw 65
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw 64
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw 63
+
+.endif
+.if WANT_TWI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; TWI (Slave) Address Mask Register
+VE_TWAMR:
+ .dw $ff05
+ .db "TWAMR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWAMR
+XT_TWAMR:
+ .dw PFA_DOVARIABLE
+PFA_TWAMR:
+ .dw 189
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Bit Rate register
+VE_TWBR:
+ .dw $ff04
+ .db "TWBR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWBR
+XT_TWBR:
+ .dw PFA_DOVARIABLE
+PFA_TWBR:
+ .dw 184
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Control Register
+VE_TWCR:
+ .dw $ff04
+ .db "TWCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWCR
+XT_TWCR:
+ .dw PFA_DOVARIABLE
+PFA_TWCR:
+ .dw 188
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Status Register
+VE_TWSR:
+ .dw $ff04
+ .db "TWSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWSR
+XT_TWSR:
+ .dw PFA_DOVARIABLE
+PFA_TWSR:
+ .dw 185
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Data register
+VE_TWDR:
+ .dw $ff04
+ .db "TWDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWDR
+XT_TWDR:
+ .dw PFA_DOVARIABLE
+PFA_TWDR:
+ .dw 187
+; ( -- addr ) System Constant
+; R( -- )
+; TWI (Slave) Address register
+VE_TWAR:
+ .dw $ff04
+ .db "TWAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWAR
+XT_TWAR:
+ .dw PFA_DOVARIABLE
+PFA_TWAR:
+ .dw 186
+
+.endif
+.if WANT_USART1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR1:
+ .dw $ff04
+ .db "UDR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR1
+XT_UDR1:
+ .dw PFA_DOVARIABLE
+PFA_UDR1:
+ .dw 206
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR1A:
+ .dw $ff06
+ .db "UCSR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1A
+XT_UCSR1A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1A:
+ .dw 200
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR1B:
+ .dw $ff06
+ .db "UCSR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1B
+XT_UCSR1B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1B:
+ .dw 201
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR1C:
+ .dw $ff06
+ .db "UCSR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1C
+XT_UCSR1C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1C:
+ .dw 202
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Bytes
+VE_UBRR1:
+ .dw $ff05
+ .db "UBRR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR1
+XT_UBRR1:
+ .dw PFA_DOVARIABLE
+PFA_UBRR1:
+ .dw 204
+
+.endif
+.if WANT_CPU == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw 95
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer
+VE_SP:
+ .dw $ff02
+ .db "SP"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SP
+XT_SP:
+ .dw PFA_DOVARIABLE
+PFA_SP:
+ .dw 93
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Calibration Value
+VE_OSCCAL:
+ .dw $ff06
+ .db "OSCCAL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSCCAL
+XT_OSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_OSCCAL:
+ .dw 102
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_CLKPR:
+ .dw $ff05
+ .db "CLKPR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKPR
+XT_CLKPR:
+ .dw PFA_DOVARIABLE
+PFA_CLKPR:
+ .dw 97
+; ( -- addr ) System Constant
+; R( -- )
+; Sleep Mode Control Register
+VE_SMCR:
+ .dw $ff04
+ .db "SMCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SMCR
+XT_SMCR:
+ .dw PFA_DOVARIABLE
+PFA_SMCR:
+ .dw 83
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 2
+VE_GPIOR2:
+ .dw $ff06
+ .db "GPIOR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR2
+XT_GPIOR2:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR2:
+ .dw 75
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 1
+VE_GPIOR1:
+ .dw $ff06
+ .db "GPIOR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR1
+XT_GPIOR1:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR1:
+ .dw 74
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 0
+VE_GPIOR0:
+ .dw $ff06
+ .db "GPIOR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR0
+XT_GPIOR0:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR0:
+ .dw 62
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register0
+VE_PRR0:
+ .dw $ff04
+ .db "PRR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR0
+XT_PRR0:
+ .dw PFA_DOVARIABLE
+PFA_PRR0:
+ .dw 100
+
+.endif
+.if WANT_SPI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR:
+ .dw $ff04
+ .db "SPDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR
+XT_SPDR:
+ .dw PFA_DOVARIABLE
+PFA_SPDR:
+ .dw 78
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR:
+ .dw $ff04
+ .db "SPSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR
+XT_SPSR:
+ .dw PFA_DOVARIABLE
+PFA_SPSR:
+ .dw 77
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR:
+ .dw $ff04
+ .db "SPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR
+XT_SPCR:
+ .dw PFA_DOVARIABLE
+PFA_SPCR:
+ .dw 76
+
+.endif
diff --git a/amforth-6.5/avr8/devices/atmega644p/device.py b/amforth-6.5/avr8/devices/atmega644p/device.py
new file mode 100644
index 0000000..aee7322
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega644p/device.py
@@ -0,0 +1,388 @@
+# Generated Automatically
+
+# Partname ATmega644P
+
+MCUREGS = {
+# Interrupt Vectors
+ 'INT0Addr' : '#2', # External Interrupt Request 0
+ 'INT1Addr' : '#4', # External Interrupt Request 1
+ 'INT2Addr' : '#6', # External Interrupt Request 2
+ 'PCINT0Addr' : '#8', # Pin Change Interrupt Request 0
+ 'PCINT1Addr' : '#10', # Pin Change Interrupt Request 1
+ 'PCINT2Addr' : '#12', # Pin Change Interrupt Request 2
+ 'PCINT3Addr' : '#14', # Pin Change Interrupt Request 3
+ 'WDTAddr' : '#16', # Watchdog Time-out Interrupt
+ 'TIMER2_COMPAAddr' : '#18', # Timer/Counter2 Compare Match A
+ 'TIMER2_COMPBAddr' : '#20', # Timer/Counter2 Compare Match B
+ 'TIMER2_OVFAddr' : '#22', # Timer/Counter2 Overflow
+ 'TIMER1_CAPTAddr' : '#24', # Timer/Counter1 Capture Event
+ 'TIMER1_COMPAAddr' : '#26', # Timer/Counter1 Compare Match A
+ 'TIMER1_COMPBAddr' : '#28', # Timer/Counter1 Compare Match B
+ 'TIMER1_OVFAddr' : '#30', # Timer/Counter1 Overflow
+ 'TIMER0_COMPAAddr' : '#32', # Timer/Counter0 Compare Match A
+ 'TIMER0_COMPBAddr' : '#34', # Timer/Counter0 Compare Match B
+ 'TIMER0_OVFAddr' : '#36', # Timer/Counter0 Overflow
+ 'SPI_STCAddr' : '#38', # SPI Serial Transfer Complete
+ 'USART0_RXAddr' : '#40', # USART0, Rx Complete
+ 'USART0_UDREAddr' : '#42', # USART0 Data register Empty
+ 'USART0_TXAddr' : '#44', # USART0, Tx Complete
+ 'ANALOG_COMPAddr' : '#46', # Analog Comparator
+ 'ADCAddr' : '#48', # ADC Conversion Complete
+ 'EE_READYAddr' : '#50', # EEPROM Ready
+ 'TWIAddr' : '#52', # 2-wire Serial Interface
+ 'SPM_READYAddr' : '#54', # Store Program Memory Read
+ 'USART1_RXAddr' : '#56', # USART1 RX complete
+ 'USART1_UDREAddr' : '#58', # USART1 Data Register Empty
+ 'USART1_TXAddr' : '#60', # USART1 TX complete
+
+# Module ANALOG_COMPARATOR
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
+ 'ACSR' : '$50', # Analog Comparator Control And
+ 'ACSR_ACD': '$80', # Analog Comparator Disable
+ 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
+ 'ACSR_ACO': '$20', # Analog Compare Output
+ 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
+ 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
+ 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
+ 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
+ 'DIDR1' : '$7f', # Digital Input Disable Register
+ 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
+ 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
+
+# Module USART0
+ 'UDR0' : '$c6', # USART I/O Data Register
+ 'UCSR0A' : '$c0', # USART Control and Status Regis
+ 'UCSR0A_RXC0': '$80', # USART Receive Complete
+ 'UCSR0A_TXC0': '$40', # USART Transmitt Complete
+ 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
+ 'UCSR0A_FE0': '$10', # Framing Error
+ 'UCSR0A_DOR0': '$8', # Data overRun
+ 'UCSR0A_UPE0': '$4', # Parity Error
+ 'UCSR0A_U2X0': '$2', # Double the USART transmission
+ 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
+ 'UCSR0B' : '$c1', # USART Control and Status Regis
+ 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
+ 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
+ 'UCSR0B_UDRIE0': '$20', # USART Data register Empty Inte
+ 'UCSR0B_RXEN0': '$10', # Receiver Enable
+ 'UCSR0B_TXEN0': '$8', # Transmitter Enable
+ 'UCSR0B_UCSZ02': '$4', # Character Size
+ 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
+ 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
+ 'UCSR0C' : '$c2', # USART Control and Status Regis
+ 'UCSR0C_UMSEL0': '$c0', # USART Mode Select
+ 'UCSR0C_UPM0': '$30', # Parity Mode Bits
+ 'UCSR0C_USBS0': '$8', # Stop Bit Select
+ 'UCSR0C_UCSZ0': '$6', # Character Size
+ 'UCSR0C_UCPOL0': '$1', # Clock Polarity
+ 'UBRR0' : '$c4', # USART Baud Rate Register Byte
+
+# Module PORTA
+ 'PORTA' : '$22', # Port A Data Register
+ 'DDRA' : '$21', # Port A Data Direction Register
+ 'PINA' : '$20', # Port A Input Pins
+
+# Module PORTB
+ 'PORTB' : '$25', # Port B Data Register
+ 'DDRB' : '$24', # Port B Data Direction Register
+ 'PINB' : '$23', # Port B Input Pins
+
+# Module PORTC
+ 'PORTC' : '$28', # Port C Data Register
+ 'DDRC' : '$27', # Port C Data Direction Register
+ 'PINC' : '$26', # Port C Input Pins
+
+# Module PORTD
+ 'PORTD' : '$2b', # Port D Data Register
+ 'DDRD' : '$2a', # Port D Data Direction Register
+ 'PIND' : '$29', # Port D Input Pins
+
+# Module TIMER_COUNTER_0
+ 'OCR0B' : '$48', # Timer/Counter0 Output Compare
+ 'OCR0A' : '$47', # Timer/Counter0 Output Compare
+ 'TCNT0' : '$46', # Timer/Counter0
+ 'TCCR0B' : '$45', # Timer/Counter Control Register
+ 'TCCR0B_FOC0A': '$80', # Force Output Compare A
+ 'TCCR0B_FOC0B': '$40', # Force Output Compare B
+ 'TCCR0B_WGM02': '$8', #
+ 'TCCR0B_CS0': '$7', # Clock Select
+ 'TCCR0A' : '$44', # Timer/Counter Control Registe
+ 'TCCR0A_COM0A': '$c0', # Compare Output Mode, Phase Cor
+ 'TCCR0A_COM0B': '$30', # Compare Output Mode, Fast PWm
+ 'TCCR0A_WGM0': '$3', # Waveform Generation Mode
+ 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
+ 'TIMSK0_OCIE0B': '$4', # Timer/Counter0 Output Compare
+ 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
+ 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
+ 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
+ 'TIFR0_OCF0B': '$4', # Timer/Counter0 Output Compare
+ 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
+ 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSRSYNC': '$1', # Prescaler Reset Timer/Counter1
+
+# Module TIMER_COUNTER_2
+ 'TIMSK2' : '$70', # Timer/Counter Interrupt Mask r
+ 'TIMSK2_OCIE2B': '$4', # Timer/Counter2 Output Compare
+ 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
+ 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
+ 'TIFR2' : '$37', # Timer/Counter Interrupt Flag R
+ 'TIFR2_OCF2B': '$4', # Output Compare Flag 2B
+ 'TIFR2_OCF2A': '$2', # Output Compare Flag 2A
+ 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
+ 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
+ 'TCCR2A_COM2A': '$c0', # Compare Output Mode bits
+ 'TCCR2A_COM2B': '$30', # Compare Output Mode bits
+ 'TCCR2A_WGM2': '$3', # Waveform Genration Mode
+ 'TCCR2B' : '$b1', # Timer/Counter2 Control Registe
+ 'TCCR2B_FOC2A': '$80', # Force Output Compare A
+ 'TCCR2B_FOC2B': '$40', # Force Output Compare B
+ 'TCCR2B_WGM22': '$8', # Waveform Generation Mode
+ 'TCCR2B_CS2': '$7', # Clock Select bits
+ 'TCNT2' : '$b2', # Timer/Counter2
+ 'OCR2B' : '$b4', # Timer/Counter2 Output Compare
+ 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
+ 'ASSR' : '$b6', # Asynchronous Status Register
+ 'ASSR_EXCLK': '$40', # Enable External Clock Input
+ 'ASSR_AS2': '$20', # Asynchronous Timer/Counter2
+ 'ASSR_TCN2UB': '$10', # Timer/Counter2 Update Busy
+ 'ASSR_OCR2AUB': '$8', # Output Compare Register2 Updat
+ 'ASSR_OCR2BUB': '$4', # Output Compare Register 2 Upda
+ 'ASSR_TCR2AUB': '$2', # Timer/Counter Control Register
+ 'ASSR_TCR2BUB': '$1', # Timer/Counter Control Register
+ 'GTCCR' : '$43', # General Timer Counter Control
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSRASY': '$2', # Prescaler Reset Timer/Counter2
+
+# Module WATCHDOG
+ 'WDTCSR' : '$60', # Watchdog Timer Control Registe
+ 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
+ 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
+ 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
+ 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
+ 'WDTCSR_WDE': '$8', # Watch Dog Enable
+
+# Module JTAG
+ 'OCDR' : '$51', # On-Chip Debug Related Register
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_JTD': '$80', # JTAG Interface Disable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+
+# Module BOOT_LOAD
+ 'SPMCSR' : '$57', # Store Program Memory Control R
+ 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
+ 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
+ 'SPMCSR_SIGRD': '$20', # Signature Row Read
+ 'SPMCSR_RWWSRE': '$10', # Read While Write section read
+ 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
+ 'SPMCSR_PGWRT': '$4', # Page Write
+ 'SPMCSR_PGERS': '$2', # Page Erase
+ 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
+
+# Module EXTERNAL_INTERRUPT
+ 'EICRA' : '$69', # External Interrupt Control Reg
+ 'EICRA_ISC2': '$30', # External Interrupt Sense Contr
+ 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
+ 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
+ 'EIMSK' : '$3d', # External Interrupt Mask Regist
+ 'EIMSK_INT': '$7', # External Interrupt Request 2 E
+ 'EIFR' : '$3c', # External Interrupt Flag Regist
+ 'EIFR_INTF': '$7', # External Interrupt Flags
+ 'PCMSK3' : '$73', # Pin Change Mask Register 3
+ 'PCMSK3_PCINT': '$ff', # Pin Change Enable Masks
+ 'PCMSK2' : '$6d', # Pin Change Mask Register 2
+ 'PCMSK2_PCINT': '$ff', # Pin Change Enable Masks
+ 'PCMSK1' : '$6c', # Pin Change Mask Register 1
+ 'PCMSK1_PCINT': '$ff', # Pin Change Enable Masks
+ 'PCMSK0' : '$6b', # Pin Change Mask Register 0
+ 'PCMSK0_PCINT': '$ff', # Pin Change Enable Masks
+ 'PCIFR' : '$3b', # Pin Change Interrupt Flag Regi
+ 'PCIFR_PCIF': '$f', # Pin Change Interrupt Flags
+ 'PCICR' : '$68', # Pin Change Interrupt Control R
+ 'PCICR_PCIE': '$f', # Pin Change Interrupt Enables
+
+# Module AD_CONVERTER
+ 'ADMUX' : '$7c', # The ADC multiplexer Selection
+ 'ADMUX_REFS': '$c0', # Reference Selection Bits
+ 'ADMUX_ADLAR': '$20', # Left Adjust Result
+ 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
+ 'ADC' : '$78', # ADC Data Register Bytes
+ 'ADCSRA' : '$7a', # The ADC Control and Status reg
+ 'ADCSRA_ADEN': '$80', # ADC Enable
+ 'ADCSRA_ADSC': '$40', # ADC Start Conversion
+ 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
+ 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
+ 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
+ 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
+ 'ADCSRB' : '$7b', # The ADC Control and Status reg
+ 'ADCSRB_ACME': '$40', #
+ 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Source bits
+ 'DIDR0' : '$7e', # Digital Input Disable Register
+ 'DIDR0_ADC7D': '$80', #
+ 'DIDR0_ADC6D': '$40', #
+ 'DIDR0_ADC5D': '$20', #
+ 'DIDR0_ADC4D': '$10', #
+ 'DIDR0_ADC3D': '$8', #
+ 'DIDR0_ADC2D': '$4', #
+ 'DIDR0_ADC1D': '$2', #
+ 'DIDR0_ADC0D': '$1', #
+
+# Module TIMER_COUNTER_1
+ 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
+ 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
+ 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
+ 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
+ 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
+ 'TIFR1' : '$36', # Timer/Counter Interrupt Flag r
+ 'TIFR1_ICF1': '$20', # Timer/Counter1 Input Capture F
+ 'TIFR1_OCF1B': '$4', # Timer/Counter1 Output Compare
+ 'TIFR1_OCF1A': '$2', # Timer/Counter1 Output Compare
+ 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
+ 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
+ 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
+ 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
+ 'TCCR1A_WGM1': '$3', # Pulse Width Modulator Select B
+ 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
+ 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
+ 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
+ 'TCCR1B_WGM1': '$18', # Waveform Generation Mode Bits
+ 'TCCR1B_CS1': '$7', # Clock Select1 bits
+ 'TCCR1C' : '$82', # Timer/Counter1 Control Registe
+ 'TCCR1C_FOC1A': '$80', # Force Output Compare for Chann
+ 'TCCR1C_FOC1B': '$40', # Force Output Compare for Chann
+ 'TCNT1' : '$84', # Timer/Counter1 Bytes
+ 'OCR1A' : '$88', # Timer/Counter1 Output Compare
+ 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
+ 'ICR1' : '$86', # Timer/Counter1 Input Capture R
+
+# Module EEPROM
+ 'EEAR' : '$41', # EEPROM Address Register Low By
+ 'EEDR' : '$40', # EEPROM Data Register
+ 'EECR' : '$3f', # EEPROM Control Register
+ 'EECR_EEPM': '$30', # EEPROM Programming Mode Bits
+ 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
+ 'EECR_EEMPE': '$4', # EEPROM Master Write Enable
+ 'EECR_EEPE': '$2', # EEPROM Write Enable
+ 'EECR_EERE': '$1', # EEPROM Read Enable
+
+# Module TWI
+ 'TWAMR' : '$bd', # TWI (Slave) Address Mask Regis
+ 'TWAMR_TWAM': '$fe', #
+ 'TWBR' : '$b8', # TWI Bit Rate register
+ 'TWCR' : '$bc', # TWI Control Register
+ 'TWCR_TWINT': '$80', # TWI Interrupt Flag
+ 'TWCR_TWEA': '$40', # TWI Enable Acknowledge Bit
+ 'TWCR_TWSTA': '$20', # TWI Start Condition Bit
+ 'TWCR_TWSTO': '$10', # TWI Stop Condition Bit
+ 'TWCR_TWWC': '$8', # TWI Write Collition Flag
+ 'TWCR_TWEN': '$4', # TWI Enable Bit
+ 'TWCR_TWIE': '$1', # TWI Interrupt Enable
+ 'TWSR' : '$b9', # TWI Status Register
+ 'TWSR_TWS': '$f8', # TWI Status
+ 'TWSR_TWPS': '$3', # TWI Prescaler
+ 'TWDR' : '$bb', # TWI Data register
+ 'TWAR' : '$ba', # TWI (Slave) Address register
+ 'TWAR_TWA': '$fe', # TWI (Slave) Address register B
+ 'TWAR_TWGCE': '$1', # TWI General Call Recognition E
+
+# Module USART1
+ 'UDR1' : '$ce', # USART I/O Data Register
+ 'UCSR1A' : '$c8', # USART Control and Status Regis
+ 'UCSR1A_RXC1': '$80', # USART Receive Complete
+ 'UCSR1A_TXC1': '$40', # USART Transmitt Complete
+ 'UCSR1A_UDRE1': '$20', # USART Data Register Empty
+ 'UCSR1A_FE1': '$10', # Framing Error
+ 'UCSR1A_DOR1': '$8', # Data overRun
+ 'UCSR1A_UPE1': '$4', # Parity Error
+ 'UCSR1A_U2X1': '$2', # Double the USART transmission
+ 'UCSR1A_MPCM1': '$1', # Multi-processor Communication
+ 'UCSR1B' : '$c9', # USART Control and Status Regis
+ 'UCSR1B_RXCIE1': '$80', # RX Complete Interrupt Enable
+ 'UCSR1B_TXCIE1': '$40', # TX Complete Interrupt Enable
+ 'UCSR1B_UDRIE1': '$20', # USART Data register Empty Inte
+ 'UCSR1B_RXEN1': '$10', # Receiver Enable
+ 'UCSR1B_TXEN1': '$8', # Transmitter Enable
+ 'UCSR1B_UCSZ12': '$4', # Character Size
+ 'UCSR1B_RXB81': '$2', # Receive Data Bit 8
+ 'UCSR1B_TXB81': '$1', # Transmit Data Bit 8
+ 'UCSR1C' : '$ca', # USART Control and Status Regis
+ 'UCSR1C_UMSEL1': '$c0', # USART Mode Select
+ 'UCSR1C_UPM1': '$30', # Parity Mode Bits
+ 'UCSR1C_USBS1': '$8', # Stop Bit Select
+ 'UCSR1C_UCSZ1': '$6', # Character Size
+ 'UCSR1C_UCPOL1': '$1', # Clock Polarity
+ 'UBRR1' : '$cc', # USART Baud Rate Register Byte
+
+# Module CPU
+ 'SREG' : '$5f', # Status Register
+ 'SREG_I': '$80', # Global Interrupt Enable
+ 'SREG_T': '$40', # Bit Copy Storage
+ 'SREG_H': '$20', # Half Carry Flag
+ 'SREG_S': '$10', # Sign Bit
+ 'SREG_V': '$8', # Two's Complement Overflow Flag
+ 'SREG_N': '$4', # Negative Flag
+ 'SREG_Z': '$2', # Zero Flag
+ 'SREG_C': '$1', # Carry Flag
+ 'SP' : '$5d', # Stack Pointer
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_JTD': '$80', # JTAG Interface Disable
+ 'MCUCR_BODS': '$40', # BOD Power Down in Sleep
+ 'MCUCR_BODSE': '$20', # BOD Power Down in Sleep Enable
+ 'MCUCR_PUD': '$10', # Pull-up disable
+ 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
+ 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+ 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
+ 'MCUSR_BORF': '$4', # Brown-out Reset Flag
+ 'MCUSR_EXTRF': '$2', # External Reset Flag
+ 'MCUSR_PORF': '$1', # Power-on reset flag
+ 'OSCCAL' : '$66', # Oscillator Calibration Value
+ 'CLKPR' : '$61', #
+ 'CLKPR_CLKPCE': '$80', #
+ 'CLKPR_CLKPS': '$f', #
+ 'SMCR' : '$53', # Sleep Mode Control Register
+ 'SMCR_SM': '$e', # Sleep Mode Select bits
+ 'SMCR_SE': '$1', # Sleep Enable
+ 'GPIOR2' : '$4b', # General Purpose IO Register 2
+ 'GPIOR2_GPIOR': '$ff', # General Purpose IO Register 2
+ 'GPIOR1' : '$4a', # General Purpose IO Register 1
+ 'GPIOR1_GPIOR': '$ff', # General Purpose IO Register 1
+ 'GPIOR0' : '$3e', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR07': '$80', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR06': '$40', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR05': '$20', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR04': '$10', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR03': '$8', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR02': '$4', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR01': '$2', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR00': '$1', # General Purpose IO Register 0
+ 'PRR0' : '$64', # Power Reduction Register0
+ 'PRR0_PRTWI': '$80', # Power Reduction TWI
+ 'PRR0_PRTIM2': '$40', # Power Reduction Timer/Counter2
+ 'PRR0_PRTIM0': '$20', # Power Reduction Timer/Counter0
+ 'PRR0_PRUSART': '$12', # Power Reduction USARTs
+ 'PRR0_PRTIM1': '$8', # Power Reduction Timer/Counter1
+ 'PRR0_PRSPI': '$4', # Power Reduction Serial Periphe
+ 'PRR0_PRADC': '$1', # Power Reduction ADC
+
+# Module SPI
+ 'SPDR' : '$4e', # SPI Data Register
+ 'SPSR' : '$4d', # SPI Status Register
+ 'SPSR_SPIF': '$80', # SPI Interrupt Flag
+ 'SPSR_WCOL': '$40', # Write Collision Flag
+ 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
+ 'SPCR' : '$4c', # SPI Control Register
+ 'SPCR_SPIE': '$80', # SPI Interrupt Enable
+ 'SPCR_SPE': '$40', # SPI Enable
+ 'SPCR_DORD': '$20', # Data Order
+ 'SPCR_MSTR': '$10', # Master/Slave Select
+ 'SPCR_CPOL': '$8', # Clock polarity
+ 'SPCR_CPHA': '$4', # Clock Phase
+ 'SPCR_SPR': '$3', # SPI Clock Rate Selects
+
+ '__amforth_dummy':'0'
+}
diff --git a/amforth-6.5/avr8/devices/atmega644p/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega644p/words/no-jtag.asm
new file mode 100644
index 0000000..352a4bb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega644p/words/no-jtag.asm
@@ -0,0 +1,14 @@
+; ( -- )
+; ( -- )
+; MCU
+; disable jtag at runtime
+VE_NOJTAG:
+ .dw $FF05
+ .db "-jtag",0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOJTAG
+XT_NOJTAG:
+ .dw PFA_NOJTAG
+PFA_NOJTAG:
+
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega644p/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega644p/words/no-wdt.asm
new file mode 100644
index 0000000..ff6ddd1
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega644p/words/no-wdt.asm
@@ -0,0 +1,34 @@
+; ( -- )
+; MCU
+; disable watch dog timer at runtime
+VE_NOWDT:
+ .dw $ff04
+ .db "-wdt"
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOWDT
+XT_NOWDT:
+ .dw PFA_NOWDT
+PFA_NOWDT:
+
+ in temp1,SREG
+ push temp1
+ ; Turn always off global interrupt.
+ cli
+ ; Reset Watchdog Timer
+ wdr
+ ; Clear WDRF in MCUSR
+ in temp1, MCUSR
+ andi temp1, (0xff & (0<<WDRF))
+ out MCUSR, temp1
+ ; Write logical one to WDCE and WDE
+ ; Keep old prescaler setting to prevent unintentional time-out
+ in_ temp1, WDTCSR
+ ori temp1, (1<<WDCE) | (1<<WDE)
+ out_ WDTCSR, temp1
+ ; Turn off WDT
+ ldi temp1, (0<<WDE)
+ out_ WDTCSR, temp1
+ ; restore status register
+ pop temp1
+ out SREG,temp1
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega644p/words/sleep.asm b/amforth-6.5/avr8/devices/atmega644p/words/sleep.asm
new file mode 100644
index 0000000..256249c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega644p/words/sleep.asm
@@ -0,0 +1,19 @@
+; ( mode -- )
+; MCU
+; put the controller into the specified sleep mode
+VE_SLEEP:
+ .dw $ff05
+ .db "sleep", 0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_SLEEP
+XT_SLEEP:
+ .dw PFA_SLEEP
+PFA_SLEEP:
+ andi tosl, 7 ; leave only legal mode bits
+ lsl tosl ; move to correct location (bits 3-1)
+ ori tosl, 1 ; set the SE bit
+ out_ SMCR, tosl ; set the sleep config
+ sleep ; nighty-night
+ out_ SMCR, zerol ; 0 protects against accidental sleeps
+ loadtos ; pop argument from stack
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega644pa/atmega644pa.frt b/amforth-6.5/avr8/devices/atmega644pa/atmega644pa.frt
new file mode 100644
index 0000000..8d0ec9c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega644pa/atmega644pa.frt
@@ -0,0 +1,346 @@
+\ Partname: ATmega644PA
+\ generated automatically
+
+\ ANALOG_COMPARATOR
+&123 constant ADCSRB \ ADC Control and Status Register B
+ $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer Enable
+&80 constant ACSR \ Analog Comparator Control And Status Register
+ $80 constant ACSR_ACD \ Analog Comparator Disable
+ $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
+ $20 constant ACSR_ACO \ Analog Compare Output
+ $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
+ $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
+ $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
+ $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
+&127 constant DIDR1 \ Digital Input Disable Register 1
+ $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
+ $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
+\ USART0
+&198 constant UDR0 \ USART I/O Data Register
+&192 constant UCSR0A \ USART Control and Status Register A
+ $80 constant UCSR0A_RXC0 \ USART Receive Complete
+ $40 constant UCSR0A_TXC0 \ USART Transmitt Complete
+ $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
+ $10 constant UCSR0A_FE0 \ Framing Error
+ $08 constant UCSR0A_DOR0 \ Data overRun
+ $04 constant UCSR0A_UPE0 \ Parity Error
+ $02 constant UCSR0A_U2X0 \ Double the USART transmission speed
+ $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
+&193 constant UCSR0B \ USART Control and Status Register B
+ $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
+ $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
+ $20 constant UCSR0B_UDRIE0 \ USART Data register Empty Interrupt Enable
+ $10 constant UCSR0B_RXEN0 \ Receiver Enable
+ $08 constant UCSR0B_TXEN0 \ Transmitter Enable
+ $04 constant UCSR0B_UCSZ02 \ Character Size
+ $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
+ $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
+&194 constant UCSR0C \ USART Control and Status Register C
+ $C0 constant UCSR0C_UMSEL0 \ USART Mode Select
+ $30 constant UCSR0C_UPM0 \ Parity Mode Bits
+ $08 constant UCSR0C_USBS0 \ Stop Bit Select
+ $06 constant UCSR0C_UCSZ0 \ Character Size
+ $01 constant UCSR0C_UCPOL0 \ Clock Polarity
+&196 constant UBRR0 \ USART Baud Rate Register Bytes
+\ PORTA
+&34 constant PORTA \ Port A Data Register
+&33 constant DDRA \ Port A Data Direction Register
+&32 constant PINA \ Port A Input Pins
+\ PORTB
+&37 constant PORTB \ Port B Data Register
+&36 constant DDRB \ Port B Data Direction Register
+&35 constant PINB \ Port B Input Pins
+\ PORTC
+&40 constant PORTC \ Port C Data Register
+&39 constant DDRC \ Port C Data Direction Register
+&38 constant PINC \ Port C Input Pins
+\ PORTD
+&43 constant PORTD \ Port D Data Register
+&42 constant DDRD \ Port D Data Direction Register
+&41 constant PIND \ Port D Input Pins
+\ TIMER_COUNTER_0
+&72 constant OCR0B \ Timer/Counter0 Output Compare Register
+&71 constant OCR0A \ Timer/Counter0 Output Compare Register
+&70 constant TCNT0 \ Timer/Counter0
+&69 constant TCCR0B \ Timer/Counter Control Register B
+ $80 constant TCCR0B_FOC0A \ Force Output Compare A
+ $40 constant TCCR0B_FOC0B \ Force Output Compare B
+ $08 constant TCCR0B_WGM02 \
+ $07 constant TCCR0B_CS0 \ Clock Select
+&68 constant TCCR0A \ Timer/Counter Control Register A
+ $C0 constant TCCR0A_COM0A \ Compare Output Mode, Phase Correct PWM Mode
+ $30 constant TCCR0A_COM0B \ Compare Output Mode, Fast PWm
+ $03 constant TCCR0A_WGM0 \ Waveform Generation Mode
+&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
+ $04 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare Match B Interrupt Enable
+ $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match A Interrupt Enable
+ $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
+&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
+ $04 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare Flag 0B
+ $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0A
+ $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
+&67 constant GTCCR \ General Timer/Counter Control Register
+ $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
+ $01 constant GTCCR_PSRSYNC \ Prescaler Reset Timer/Counter1 and Timer/Counter0
+\ TIMER_COUNTER_2
+&112 constant TIMSK2 \ Timer/Counter Interrupt Mask register
+ $04 constant TIMSK2_OCIE2B \ Timer/Counter2 Output Compare Match B Interrupt Enable
+ $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match A Interrupt Enable
+ $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
+&55 constant TIFR2 \ Timer/Counter Interrupt Flag Register
+ $04 constant TIFR2_OCF2B \ Output Compare Flag 2B
+ $02 constant TIFR2_OCF2A \ Output Compare Flag 2A
+ $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
+&176 constant TCCR2A \ Timer/Counter2 Control Register A
+ $C0 constant TCCR2A_COM2A \ Compare Output Mode bits
+ $30 constant TCCR2A_COM2B \ Compare Output Mode bits
+ $03 constant TCCR2A_WGM2 \ Waveform Genration Mode
+&177 constant TCCR2B \ Timer/Counter2 Control Register B
+ $80 constant TCCR2B_FOC2A \ Force Output Compare A
+ $40 constant TCCR2B_FOC2B \ Force Output Compare B
+ $08 constant TCCR2B_WGM22 \ Waveform Generation Mode
+ $07 constant TCCR2B_CS2 \ Clock Select bits
+&178 constant TCNT2 \ Timer/Counter2
+&180 constant OCR2B \ Timer/Counter2 Output Compare Register B
+&179 constant OCR2A \ Timer/Counter2 Output Compare Register A
+&182 constant ASSR \ Asynchronous Status Register
+ $40 constant ASSR_EXCLK \ Enable External Clock Input
+ $20 constant ASSR_AS2 \ Asynchronous Timer/Counter2
+ $10 constant ASSR_TCN2UB \ Timer/Counter2 Update Busy
+ $08 constant ASSR_OCR2AUB \ Output Compare Register2 Update Busy
+ $04 constant ASSR_OCR2BUB \ Output Compare Register 2 Update Busy
+ $02 constant ASSR_TCR2AUB \ Timer/Counter Control Register2 Update Busy
+ $01 constant ASSR_TCR2BUB \ Timer/Counter Control Register2 Update Busy
+\ WATCHDOG
+&96 constant WDTCSR \ Watchdog Timer Control Register
+ $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Flag
+ $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Enable
+ $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
+ $10 constant WDTCSR_WDCE \ Watchdog Change Enable
+ $08 constant WDTCSR_WDE \ Watch Dog Enable
+\ JTAG
+&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
+&85 constant MCUCR \ MCU Control Register
+ $80 constant MCUCR_JTD \ JTAG Interface Disable
+&84 constant MCUSR \ MCU Status Register
+ $10 constant MCUSR_JTRF \ JTAG Reset Flag
+\ BOOT_LOAD
+&87 constant SPMCSR \ Store Program Memory Control Register
+ $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
+ $20 constant SPMCSR_SIGRD \ Signature Row Read
+ $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
+ $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
+ $04 constant SPMCSR_PGWRT \ Page Write
+ $02 constant SPMCSR_PGERS \ Page Erase
+ $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
+\ EXTERNAL_INTERRUPT
+&105 constant EICRA \ External Interrupt Control Register A
+ $30 constant EICRA_ISC2 \ External Interrupt Sense Control Bit
+ $0C constant EICRA_ISC1 \ External Interrupt Sense Control Bit
+ $03 constant EICRA_ISC0 \ External Interrupt Sense Control Bit
+&61 constant EIMSK \ External Interrupt Mask Register
+ $07 constant EIMSK_INT \ External Interrupt Request 2 Enable
+&60 constant EIFR \ External Interrupt Flag Register
+ $07 constant EIFR_INTF \ External Interrupt Flags
+&115 constant PCMSK3 \ Pin Change Mask Register 3
+ $FF constant PCMSK3_PCINT \ Pin Change Enable Masks
+&109 constant PCMSK2 \ Pin Change Mask Register 2
+ $FF constant PCMSK2_PCINT \ Pin Change Enable Masks
+&108 constant PCMSK1 \ Pin Change Mask Register 1
+ $FF constant PCMSK1_PCINT \ Pin Change Enable Masks
+&107 constant PCMSK0 \ Pin Change Mask Register 0
+ $FF constant PCMSK0_PCINT \ Pin Change Enable Masks
+&59 constant PCIFR \ Pin Change Interrupt Flag Register
+ $0F constant PCIFR_PCIF \ Pin Change Interrupt Flags
+&104 constant PCICR \ Pin Change Interrupt Control Register
+ $0F constant PCICR_PCIE \ Pin Change Interrupt Enables
+\ AD_CONVERTER
+&124 constant ADMUX \ The ADC multiplexer Selection Register
+ $C0 constant ADMUX_REFS \ Reference Selection Bits
+ $20 constant ADMUX_ADLAR \ Left Adjust Result
+ $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
+&120 constant ADC \ ADC Data Register Bytes
+&122 constant ADCSRA \ The ADC Control and Status register A
+ $80 constant ADCSRA_ADEN \ ADC Enable
+ $40 constant ADCSRA_ADSC \ ADC Start Conversion
+ $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
+ $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
+ $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
+ $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
+&126 constant DIDR0 \ Digital Input Disable Register
+ $80 constant DIDR0_ADC7D \
+ $40 constant DIDR0_ADC6D \
+ $20 constant DIDR0_ADC5D \
+ $10 constant DIDR0_ADC4D \
+ $08 constant DIDR0_ADC3D \
+ $04 constant DIDR0_ADC2D \
+ $02 constant DIDR0_ADC1D \
+ $01 constant DIDR0_ADC0D \
+\ TIMER_COUNTER_1
+&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
+ $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
+ $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
+ $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
+ $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
+&54 constant TIFR1 \ Timer/Counter Interrupt Flag register
+ $20 constant TIFR1_ICF1 \ Timer/Counter1 Input Capture Flag
+ $04 constant TIFR1_OCF1B \ Timer/Counter1 Output Compare B Match Flag
+ $02 constant TIFR1_OCF1A \ Timer/Counter1 Output Compare A Match Flag
+ $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
+&128 constant TCCR1A \ Timer/Counter1 Control Register A
+ $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
+ $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
+ $03 constant TCCR1A_WGM1 \ Pulse Width Modulator Select Bits
+&129 constant TCCR1B \ Timer/Counter1 Control Register B
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ $18 constant TCCR1B_WGM1 \ Waveform Generation Mode Bits
+ $07 constant TCCR1B_CS1 \ Clock Select1 bits
+&130 constant TCCR1C \ Timer/Counter1 Control Register C
+ $80 constant TCCR1C_FOC1A \ Force Output Compare for Channel A
+ $40 constant TCCR1C_FOC1B \ Force Output Compare for Channel B
+&132 constant TCNT1 \ Timer/Counter1 Bytes
+&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
+&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
+&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
+\ EEPROM
+&65 constant EEAR \ EEPROM Address Register Low Bytes
+&64 constant EEDR \ EEPROM Data Register
+&63 constant EECR \ EEPROM Control Register
+ $30 constant EECR_EEPM \ EEPROM Programming Mode Bits
+ $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
+ $04 constant EECR_EEMPE \ EEPROM Master Write Enable
+ $02 constant EECR_EEPE \ EEPROM Write Enable
+ $01 constant EECR_EERE \ EEPROM Read Enable
+\ TWI
+&189 constant TWAMR \ TWI (Slave) Address Mask Register
+ $FE constant TWAMR_TWAM \
+&184 constant TWBR \ TWI Bit Rate register
+&188 constant TWCR \ TWI Control Register
+ $80 constant TWCR_TWINT \ TWI Interrupt Flag
+ $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
+ $20 constant TWCR_TWSTA \ TWI Start Condition Bit
+ $10 constant TWCR_TWSTO \ TWI Stop Condition Bit
+ $08 constant TWCR_TWWC \ TWI Write Collition Flag
+ $04 constant TWCR_TWEN \ TWI Enable Bit
+ $01 constant TWCR_TWIE \ TWI Interrupt Enable
+&185 constant TWSR \ TWI Status Register
+ $F8 constant TWSR_TWS \ TWI Status
+ $03 constant TWSR_TWPS \ TWI Prescaler
+&187 constant TWDR \ TWI Data register
+&186 constant TWAR \ TWI (Slave) Address register
+ $FE constant TWAR_TWA \ TWI (Slave) Address register Bits
+ $01 constant TWAR_TWGCE \ TWI General Call Recognition Enable Bit
+\ USART1
+&206 constant UDR1 \ USART I/O Data Register
+&200 constant UCSR1A \ USART Control and Status Register A
+ $80 constant UCSR1A_RXC1 \ USART Receive Complete
+ $40 constant UCSR1A_TXC1 \ USART Transmitt Complete
+ $20 constant UCSR1A_UDRE1 \ USART Data Register Empty
+ $10 constant UCSR1A_FE1 \ Framing Error
+ $08 constant UCSR1A_DOR1 \ Data overRun
+ $04 constant UCSR1A_UPE1 \ Parity Error
+ $02 constant UCSR1A_U2X1 \ Double the USART transmission speed
+ $01 constant UCSR1A_MPCM1 \ Multi-processor Communication Mode
+&201 constant UCSR1B \ USART Control and Status Register B
+ $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable
+ $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable
+ $20 constant UCSR1B_UDRIE1 \ USART Data register Empty Interrupt Enable
+ $10 constant UCSR1B_RXEN1 \ Receiver Enable
+ $08 constant UCSR1B_TXEN1 \ Transmitter Enable
+ $04 constant UCSR1B_UCSZ12 \ Character Size
+ $02 constant UCSR1B_RXB81 \ Receive Data Bit 8
+ $01 constant UCSR1B_TXB81 \ Transmit Data Bit 8
+&202 constant UCSR1C \ USART Control and Status Register C
+ $C0 constant UCSR1C_UMSEL1 \ USART Mode Select
+ $30 constant UCSR1C_UPM1 \ Parity Mode Bits
+ $08 constant UCSR1C_USBS1 \ Stop Bit Select
+ $06 constant UCSR1C_UCSZ1 \ Character Size
+ $01 constant UCSR1C_UCPOL1 \ Clock Polarity
+&204 constant UBRR1 \ USART Baud Rate Register Bytes
+\ CPU
+&95 constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ $08 constant SREG_V \ Two's Complement Overflow Flag
+ $04 constant SREG_N \ Negative Flag
+ $02 constant SREG_Z \ Zero Flag
+ $01 constant SREG_C \ Carry Flag
+&93 constant SP \ Stack Pointer
+&102 constant OSCCAL \ Oscillator Calibration Value
+&97 constant CLKPR \
+ $80 constant CLKPR_CLKPCE \
+ $0F constant CLKPR_CLKPS \
+&83 constant SMCR \ Sleep Mode Control Register
+ $0E constant SMCR_SM \ Sleep Mode Select bits
+ $01 constant SMCR_SE \ Sleep Enable
+&75 constant GPIOR2 \ General Purpose IO Register 2
+ $FF constant GPIOR2_GPIOR \ General Purpose IO Register 2 bis
+&74 constant GPIOR1 \ General Purpose IO Register 1
+ $FF constant GPIOR1_GPIOR \ General Purpose IO Register 1 bis
+&62 constant GPIOR0 \ General Purpose IO Register 0
+ $80 constant GPIOR0_GPIOR07 \ General Purpose IO Register 0 bit 7
+ $40 constant GPIOR0_GPIOR06 \ General Purpose IO Register 0 bit 6
+ $20 constant GPIOR0_GPIOR05 \ General Purpose IO Register 0 bit 5
+ $10 constant GPIOR0_GPIOR04 \ General Purpose IO Register 0 bit 4
+ $08 constant GPIOR0_GPIOR03 \ General Purpose IO Register 0 bit 3
+ $04 constant GPIOR0_GPIOR02 \ General Purpose IO Register 0 bit 2
+ $02 constant GPIOR0_GPIOR01 \ General Purpose IO Register 0 bit 1
+ $01 constant GPIOR0_GPIOR00 \ General Purpose IO Register 0 bit 0
+&100 constant PRR0 \ Power Reduction Register0
+ $80 constant PRR0_PRTWI \ Power Reduction TWI
+ $40 constant PRR0_PRTIM2 \ Power Reduction Timer/Counter2
+ $20 constant PRR0_PRTIM0 \ Power Reduction Timer/Counter0
+ $12 constant PRR0_PRUSART \ Power Reduction USARTs
+ $08 constant PRR0_PRTIM1 \ Power Reduction Timer/Counter1
+ $04 constant PRR0_PRSPI \ Power Reduction Serial Peripheral Interface
+ $01 constant PRR0_PRADC \ Power Reduction ADC
+\ SPI
+&78 constant SPDR \ SPI Data Register
+&77 constant SPSR \ SPI Status Register
+ $80 constant SPSR_SPIF \ SPI Interrupt Flag
+ $40 constant SPSR_WCOL \ Write Collision Flag
+ $01 constant SPSR_SPI2X \ Double SPI Speed Bit
+&76 constant SPCR \ SPI Control Register
+ $80 constant SPCR_SPIE \ SPI Interrupt Enable
+ $40 constant SPCR_SPE \ SPI Enable
+ $20 constant SPCR_DORD \ Data Order
+ $10 constant SPCR_MSTR \ Master/Slave Select
+ $08 constant SPCR_CPOL \ Clock polarity
+ $04 constant SPCR_CPHA \ Clock Phase
+ $03 constant SPCR_SPR \ SPI Clock Rate Selects
+
+\ Interrupts
+&2 constant INT0Addr \ External Interrupt Request 0
+&4 constant INT1Addr \ External Interrupt Request 1
+&6 constant INT2Addr \ External Interrupt Request 2
+&8 constant PCINT0Addr \ Pin Change Interrupt Request 0
+&10 constant PCINT1Addr \ Pin Change Interrupt Request 1
+&12 constant PCINT2Addr \ Pin Change Interrupt Request 2
+&14 constant PCINT3Addr \ Pin Change Interrupt Request 3
+&16 constant WDTAddr \ Watchdog Time-out Interrupt
+&18 constant TIMER2_COMPAAddr \ Timer/Counter2 Compare Match A
+&20 constant TIMER2_COMPBAddr \ Timer/Counter2 Compare Match B
+&22 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
+&24 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+&26 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
+&28 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
+&30 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+&32 constant TIMER0_COMPAAddr \ Timer/Counter0 Compare Match A
+&34 constant TIMER0_COMPBAddr \ Timer/Counter0 Compare Match B
+&36 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
+&38 constant SPI__STCAddr \ SPI Serial Transfer Complete
+&40 constant USART0__RXAddr \ USART0, Rx Complete
+&42 constant USART0__UDREAddr \ USART0 Data register Empty
+&44 constant USART0__TXAddr \ USART0, Tx Complete
+&46 constant ANALOG_COMPAddr \ Analog Comparator
+&48 constant ADCAddr \ ADC Conversion Complete
+&50 constant EE_READYAddr \ EEPROM Ready
+&52 constant TWIAddr \ 2-wire Serial Interface
+&54 constant SPM_READYAddr \ Store Program Memory Read
+&56 constant USART1_RXAddr \ USART1 RX complete
+&58 constant USART1_UDREAddr \ USART1 Data Register Empty
+&60 constant USART1_TXAddr \ USART1 TX complete
diff --git a/amforth-6.5/avr8/devices/atmega644pa/device.asm b/amforth-6.5/avr8/devices/atmega644pa/device.asm
new file mode 100644
index 0000000..7a4bc5f
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega644pa/device.asm
@@ -0,0 +1,120 @@
+; Partname: ATmega644PA
+; generated automatically, do not edit
+
+.nolist
+ .include "m644PAdef.inc"
+.list
+
+.equ ramstart = 256
+.equ CELLSIZE = 2
+.macro readflashcell
+ lsl zl
+ rol zh
+ lpm @0, Z+
+ lpm @1, Z+
+.endmacro
+.macro writeflashcell
+ lsl zl
+ rol zh
+.endmacro
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_USART0 = 0
+.set WANT_PORTA = 0
+.set WANT_PORTB = 0
+.set WANT_PORTC = 0
+.set WANT_PORTD = 0
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_TIMER_COUNTER_2 = 0
+.set WANT_WATCHDOG = 0
+.set WANT_JTAG = 0
+.set WANT_BOOT_LOAD = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_AD_CONVERTER = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_EEPROM = 0
+.set WANT_TWI = 0
+.set WANT_USART1 = 0
+.set WANT_CPU = 0
+.set WANT_SPI = 0
+.equ intvecsize = 2 ; please verify; flash size: 65536 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.org 2
+ rcall isr ; External Interrupt Request 0
+.org 4
+ rcall isr ; External Interrupt Request 1
+.org 6
+ rcall isr ; External Interrupt Request 2
+.org 8
+ rcall isr ; Pin Change Interrupt Request 0
+.org 10
+ rcall isr ; Pin Change Interrupt Request 1
+.org 12
+ rcall isr ; Pin Change Interrupt Request 2
+.org 14
+ rcall isr ; Pin Change Interrupt Request 3
+.org 16
+ rcall isr ; Watchdog Time-out Interrupt
+.org 18
+ rcall isr ; Timer/Counter2 Compare Match A
+.org 20
+ rcall isr ; Timer/Counter2 Compare Match B
+.org 22
+ rcall isr ; Timer/Counter2 Overflow
+.org 24
+ rcall isr ; Timer/Counter1 Capture Event
+.org 26
+ rcall isr ; Timer/Counter1 Compare Match A
+.org 28
+ rcall isr ; Timer/Counter1 Compare Match B
+.org 30
+ rcall isr ; Timer/Counter1 Overflow
+.org 32
+ rcall isr ; Timer/Counter0 Compare Match A
+.org 34
+ rcall isr ; Timer/Counter0 Compare Match B
+.org 36
+ rcall isr ; Timer/Counter0 Overflow
+.org 38
+ rcall isr ; SPI Serial Transfer Complete
+.org 40
+ rcall isr ; USART0, Rx Complete
+.org 42
+ rcall isr ; USART0 Data register Empty
+.org 44
+ rcall isr ; USART0, Tx Complete
+.org 46
+ rcall isr ; Analog Comparator
+.org 48
+ rcall isr ; ADC Conversion Complete
+.org 50
+ rcall isr ; EEPROM Ready
+.org 52
+ rcall isr ; 2-wire Serial Interface
+.org 54
+ rcall isr ; Store Program Memory Read
+.org 56
+ rcall isr ; USART1 RX complete
+.org 58
+ rcall isr ; USART1 Data Register Empty
+.org 60
+ rcall isr ; USART1 TX complete
+.equ INTVECTORS = 31
+.nooverlap
+
+; compatability layer (maybe empty)
+
+; controller data area, environment query mcu-info
+mcu_info:
+mcu_ramsize:
+ .dw 4096
+mcu_eepromsize:
+ .dw 2048
+mcu_maxdp:
+ .dw 57344
+mcu_numints:
+ .dw 31
+mcu_name:
+ .dw 11
+ .db "ATmega644PA",0
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega644pa/device.inc b/amforth-6.5/avr8/devices/atmega644pa/device.inc
new file mode 100644
index 0000000..3d60f55
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega644pa/device.inc
@@ -0,0 +1,1128 @@
+; Partname: ATmega644PA
+; generated automatically, no not edit
+
+.if WANT_ANALOG_COMPARATOR == 1
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Control and Status Register B
+VE_ADCSRB:
+ .dw $ff06
+ .db "ADCSRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRB
+XT_ADCSRB:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRB:
+ .dw 123
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Control And Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw 80
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 1
+VE_DIDR1:
+ .dw $ff05
+ .db "DIDR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR1
+XT_DIDR1:
+ .dw PFA_DOVARIABLE
+PFA_DIDR1:
+ .dw 127
+
+.endif
+.if WANT_USART0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR0:
+ .dw $ff04
+ .db "UDR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR0
+XT_UDR0:
+ .dw PFA_DOVARIABLE
+PFA_UDR0:
+ .dw 198
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR0A:
+ .dw $ff06
+ .db "UCSR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0A
+XT_UCSR0A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0A:
+ .dw 192
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR0B:
+ .dw $ff06
+ .db "UCSR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0B
+XT_UCSR0B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0B:
+ .dw 193
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR0C:
+ .dw $ff06
+ .db "UCSR0C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0C
+XT_UCSR0C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0C:
+ .dw 194
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Bytes
+VE_UBRR0:
+ .dw $ff05
+ .db "UBRR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR0
+XT_UBRR0:
+ .dw PFA_DOVARIABLE
+PFA_UBRR0:
+ .dw 196
+
+.endif
+.if WANT_PORTA == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Register
+VE_PORTA:
+ .dw $ff05
+ .db "PORTA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTA
+XT_PORTA:
+ .dw PFA_DOVARIABLE
+PFA_PORTA:
+ .dw 34
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Direction Register
+VE_DDRA:
+ .dw $ff04
+ .db "DDRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRA
+XT_DDRA:
+ .dw PFA_DOVARIABLE
+PFA_DDRA:
+ .dw 33
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Input Pins
+VE_PINA:
+ .dw $ff04
+ .db "PINA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINA
+XT_PINA:
+ .dw PFA_DOVARIABLE
+PFA_PINA:
+ .dw 32
+
+.endif
+.if WANT_PORTB == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw 37
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw 36
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw 35
+
+.endif
+.if WANT_PORTC == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Register
+VE_PORTC:
+ .dw $ff05
+ .db "PORTC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTC
+XT_PORTC:
+ .dw PFA_DOVARIABLE
+PFA_PORTC:
+ .dw 40
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Direction Register
+VE_DDRC:
+ .dw $ff04
+ .db "DDRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRC
+XT_DDRC:
+ .dw PFA_DOVARIABLE
+PFA_DDRC:
+ .dw 39
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Input Pins
+VE_PINC:
+ .dw $ff04
+ .db "PINC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINC
+XT_PINC:
+ .dw PFA_DOVARIABLE
+PFA_PINC:
+ .dw 38
+
+.endif
+.if WANT_PORTD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw 43
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw 42
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw 41
+
+.endif
+.if WANT_TIMER_COUNTER_0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0B:
+ .dw $ff05
+ .db "OCR0B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0B
+XT_OCR0B:
+ .dw PFA_DOVARIABLE
+PFA_OCR0B:
+ .dw 72
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0A:
+ .dw $ff05
+ .db "OCR0A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0A
+XT_OCR0A:
+ .dw PFA_DOVARIABLE
+PFA_OCR0A:
+ .dw 71
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw 70
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register B
+VE_TCCR0B:
+ .dw $ff06
+ .db "TCCR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0B
+XT_TCCR0B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0B:
+ .dw 69
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register A
+VE_TCCR0A:
+ .dw $ff06
+ .db "TCCR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0A
+XT_TCCR0A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0A:
+ .dw 68
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Mask Register
+VE_TIMSK0:
+ .dw $ff06
+ .db "TIMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK0
+XT_TIMSK0:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK0:
+ .dw 110
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Flag register
+VE_TIFR0:
+ .dw $ff05
+ .db "TIFR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR0
+XT_TIFR0:
+ .dw PFA_DOVARIABLE
+PFA_TIFR0:
+ .dw 53
+; ( -- addr ) System Constant
+; R( -- )
+; General Timer/Counter Control Register
+VE_GTCCR:
+ .dw $ff05
+ .db "GTCCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GTCCR
+XT_GTCCR:
+ .dw PFA_DOVARIABLE
+PFA_GTCCR:
+ .dw 67
+
+.endif
+.if WANT_TIMER_COUNTER_2 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Mask register
+VE_TIMSK2:
+ .dw $ff06
+ .db "TIMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK2
+XT_TIMSK2:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK2:
+ .dw 112
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Flag Register
+VE_TIFR2:
+ .dw $ff05
+ .db "TIFR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR2
+XT_TIFR2:
+ .dw PFA_DOVARIABLE
+PFA_TIFR2:
+ .dw 55
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register A
+VE_TCCR2A:
+ .dw $ff06
+ .db "TCCR2A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2A
+XT_TCCR2A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2A:
+ .dw 176
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register B
+VE_TCCR2B:
+ .dw $ff06
+ .db "TCCR2B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2B
+XT_TCCR2B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2B:
+ .dw 177
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2
+VE_TCNT2:
+ .dw $ff05
+ .db "TCNT2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT2
+XT_TCNT2:
+ .dw PFA_DOVARIABLE
+PFA_TCNT2:
+ .dw 178
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register B
+VE_OCR2B:
+ .dw $ff05
+ .db "OCR2B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2B
+XT_OCR2B:
+ .dw PFA_DOVARIABLE
+PFA_OCR2B:
+ .dw 180
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register A
+VE_OCR2A:
+ .dw $ff05
+ .db "OCR2A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2A
+XT_OCR2A:
+ .dw PFA_DOVARIABLE
+PFA_OCR2A:
+ .dw 179
+; ( -- addr ) System Constant
+; R( -- )
+; Asynchronous Status Register
+VE_ASSR:
+ .dw $ff04
+ .db "ASSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ASSR
+XT_ASSR:
+ .dw PFA_DOVARIABLE
+PFA_ASSR:
+ .dw 182
+
+.endif
+.if WANT_WATCHDOG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCSR:
+ .dw $ff06
+ .db "WDTCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCSR
+XT_WDTCSR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCSR:
+ .dw 96
+
+.endif
+.if WANT_JTAG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; On-Chip Debug Related Register in I/O Memory
+VE_OCDR:
+ .dw $ff04
+ .db "OCDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCDR
+XT_OCDR:
+ .dw PFA_DOVARIABLE
+PFA_OCDR:
+ .dw 81
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw 85
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Status Register
+VE_MCUSR:
+ .dw $ff05
+ .db "MCUSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUSR
+XT_MCUSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUSR:
+ .dw 84
+
+.endif
+.if WANT_BOOT_LOAD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control Register
+VE_SPMCSR:
+ .dw $ff06
+ .db "SPMCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCSR
+XT_SPMCSR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCSR:
+ .dw 87
+
+.endif
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register A
+VE_EICRA:
+ .dw $ff05
+ .db "EICRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRA
+XT_EICRA:
+ .dw PFA_DOVARIABLE
+PFA_EICRA:
+ .dw 105
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Mask Register
+VE_EIMSK:
+ .dw $ff05
+ .db "EIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIMSK
+XT_EIMSK:
+ .dw PFA_DOVARIABLE
+PFA_EIMSK:
+ .dw 61
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Flag Register
+VE_EIFR:
+ .dw $ff04
+ .db "EIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIFR
+XT_EIFR:
+ .dw PFA_DOVARIABLE
+PFA_EIFR:
+ .dw 60
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 3
+VE_PCMSK3:
+ .dw $ff06
+ .db "PCMSK3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK3
+XT_PCMSK3:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK3:
+ .dw 115
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 2
+VE_PCMSK2:
+ .dw $ff06
+ .db "PCMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK2
+XT_PCMSK2:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK2:
+ .dw 109
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 1
+VE_PCMSK1:
+ .dw $ff06
+ .db "PCMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK1
+XT_PCMSK1:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK1:
+ .dw 108
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 0
+VE_PCMSK0:
+ .dw $ff06
+ .db "PCMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK0
+XT_PCMSK0:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK0:
+ .dw 107
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Interrupt Flag Register
+VE_PCIFR:
+ .dw $ff05
+ .db "PCIFR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCIFR
+XT_PCIFR:
+ .dw PFA_DOVARIABLE
+PFA_PCIFR:
+ .dw 59
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Interrupt Control Register
+VE_PCICR:
+ .dw $ff05
+ .db "PCICR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCICR
+XT_PCICR:
+ .dw PFA_DOVARIABLE
+PFA_PCICR:
+ .dw 104
+
+.endif
+.if WANT_AD_CONVERTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC multiplexer Selection Register
+VE_ADMUX:
+ .dw $ff05
+ .db "ADMUX",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADMUX
+XT_ADMUX:
+ .dw PFA_DOVARIABLE
+PFA_ADMUX:
+ .dw 124
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register Bytes
+VE_ADC:
+ .dw $ff03
+ .db "ADC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADC
+XT_ADC:
+ .dw PFA_DOVARIABLE
+PFA_ADC:
+ .dw 120
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register A
+VE_ADCSRA:
+ .dw $ff06
+ .db "ADCSRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRA
+XT_ADCSRA:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRA:
+ .dw 122
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register
+VE_DIDR0:
+ .dw $ff05
+ .db "DIDR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR0
+XT_DIDR0:
+ .dw PFA_DOVARIABLE
+PFA_DIDR0:
+ .dw 126
+
+.endif
+.if WANT_TIMER_COUNTER_1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Mask Register
+VE_TIMSK1:
+ .dw $ff06
+ .db "TIMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK1
+XT_TIMSK1:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK1:
+ .dw 111
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Flag register
+VE_TIFR1:
+ .dw $ff05
+ .db "TIFR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR1
+XT_TIFR1:
+ .dw PFA_DOVARIABLE
+PFA_TIFR1:
+ .dw 54
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw 128
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw 129
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register C
+VE_TCCR1C:
+ .dw $ff06
+ .db "TCCR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1C
+XT_TCCR1C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1C:
+ .dw 130
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Bytes
+VE_TCNT1:
+ .dw $ff05
+ .db "TCNT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1
+XT_TCNT1:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1:
+ .dw 132
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register A Bytes
+VE_OCR1A:
+ .dw $ff05
+ .db "OCR1A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1A
+XT_OCR1A:
+ .dw PFA_DOVARIABLE
+PFA_OCR1A:
+ .dw 136
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register B Bytes
+VE_OCR1B:
+ .dw $ff05
+ .db "OCR1B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1B
+XT_OCR1B:
+ .dw PFA_DOVARIABLE
+PFA_OCR1B:
+ .dw 138
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Bytes
+VE_ICR1:
+ .dw $ff04
+ .db "ICR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1
+XT_ICR1:
+ .dw PFA_DOVARIABLE
+PFA_ICR1:
+ .dw 134
+
+.endif
+.if WANT_EEPROM == 1
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Address Register Low Bytes
+VE_EEAR:
+ .dw $ff04
+ .db "EEAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEAR
+XT_EEAR:
+ .dw PFA_DOVARIABLE
+PFA_EEAR:
+ .dw 65
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw 64
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw 63
+
+.endif
+.if WANT_TWI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; TWI (Slave) Address Mask Register
+VE_TWAMR:
+ .dw $ff05
+ .db "TWAMR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWAMR
+XT_TWAMR:
+ .dw PFA_DOVARIABLE
+PFA_TWAMR:
+ .dw 189
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Bit Rate register
+VE_TWBR:
+ .dw $ff04
+ .db "TWBR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWBR
+XT_TWBR:
+ .dw PFA_DOVARIABLE
+PFA_TWBR:
+ .dw 184
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Control Register
+VE_TWCR:
+ .dw $ff04
+ .db "TWCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWCR
+XT_TWCR:
+ .dw PFA_DOVARIABLE
+PFA_TWCR:
+ .dw 188
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Status Register
+VE_TWSR:
+ .dw $ff04
+ .db "TWSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWSR
+XT_TWSR:
+ .dw PFA_DOVARIABLE
+PFA_TWSR:
+ .dw 185
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Data register
+VE_TWDR:
+ .dw $ff04
+ .db "TWDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWDR
+XT_TWDR:
+ .dw PFA_DOVARIABLE
+PFA_TWDR:
+ .dw 187
+; ( -- addr ) System Constant
+; R( -- )
+; TWI (Slave) Address register
+VE_TWAR:
+ .dw $ff04
+ .db "TWAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWAR
+XT_TWAR:
+ .dw PFA_DOVARIABLE
+PFA_TWAR:
+ .dw 186
+
+.endif
+.if WANT_USART1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR1:
+ .dw $ff04
+ .db "UDR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR1
+XT_UDR1:
+ .dw PFA_DOVARIABLE
+PFA_UDR1:
+ .dw 206
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR1A:
+ .dw $ff06
+ .db "UCSR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1A
+XT_UCSR1A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1A:
+ .dw 200
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR1B:
+ .dw $ff06
+ .db "UCSR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1B
+XT_UCSR1B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1B:
+ .dw 201
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR1C:
+ .dw $ff06
+ .db "UCSR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1C
+XT_UCSR1C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1C:
+ .dw 202
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Bytes
+VE_UBRR1:
+ .dw $ff05
+ .db "UBRR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR1
+XT_UBRR1:
+ .dw PFA_DOVARIABLE
+PFA_UBRR1:
+ .dw 204
+
+.endif
+.if WANT_CPU == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw 95
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer
+VE_SP:
+ .dw $ff02
+ .db "SP"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SP
+XT_SP:
+ .dw PFA_DOVARIABLE
+PFA_SP:
+ .dw 93
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Calibration Value
+VE_OSCCAL:
+ .dw $ff06
+ .db "OSCCAL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSCCAL
+XT_OSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_OSCCAL:
+ .dw 102
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_CLKPR:
+ .dw $ff05
+ .db "CLKPR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKPR
+XT_CLKPR:
+ .dw PFA_DOVARIABLE
+PFA_CLKPR:
+ .dw 97
+; ( -- addr ) System Constant
+; R( -- )
+; Sleep Mode Control Register
+VE_SMCR:
+ .dw $ff04
+ .db "SMCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SMCR
+XT_SMCR:
+ .dw PFA_DOVARIABLE
+PFA_SMCR:
+ .dw 83
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 2
+VE_GPIOR2:
+ .dw $ff06
+ .db "GPIOR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR2
+XT_GPIOR2:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR2:
+ .dw 75
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 1
+VE_GPIOR1:
+ .dw $ff06
+ .db "GPIOR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR1
+XT_GPIOR1:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR1:
+ .dw 74
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 0
+VE_GPIOR0:
+ .dw $ff06
+ .db "GPIOR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR0
+XT_GPIOR0:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR0:
+ .dw 62
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register0
+VE_PRR0:
+ .dw $ff04
+ .db "PRR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR0
+XT_PRR0:
+ .dw PFA_DOVARIABLE
+PFA_PRR0:
+ .dw 100
+
+.endif
+.if WANT_SPI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR:
+ .dw $ff04
+ .db "SPDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR
+XT_SPDR:
+ .dw PFA_DOVARIABLE
+PFA_SPDR:
+ .dw 78
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR:
+ .dw $ff04
+ .db "SPSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR
+XT_SPSR:
+ .dw PFA_DOVARIABLE
+PFA_SPSR:
+ .dw 77
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR:
+ .dw $ff04
+ .db "SPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR
+XT_SPCR:
+ .dw PFA_DOVARIABLE
+PFA_SPCR:
+ .dw 76
+
+.endif
diff --git a/amforth-6.5/avr8/devices/atmega644pa/device.py b/amforth-6.5/avr8/devices/atmega644pa/device.py
new file mode 100644
index 0000000..f71af9a
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega644pa/device.py
@@ -0,0 +1,388 @@
+# Generated Automatically
+
+# Partname ATmega644PA
+
+MCUREGS = {
+# Interrupt Vectors
+ 'INT0Addr' : '#2', # External Interrupt Request 0
+ 'INT1Addr' : '#4', # External Interrupt Request 1
+ 'INT2Addr' : '#6', # External Interrupt Request 2
+ 'PCINT0Addr' : '#8', # Pin Change Interrupt Request 0
+ 'PCINT1Addr' : '#10', # Pin Change Interrupt Request 1
+ 'PCINT2Addr' : '#12', # Pin Change Interrupt Request 2
+ 'PCINT3Addr' : '#14', # Pin Change Interrupt Request 3
+ 'WDTAddr' : '#16', # Watchdog Time-out Interrupt
+ 'TIMER2_COMPAAddr' : '#18', # Timer/Counter2 Compare Match A
+ 'TIMER2_COMPBAddr' : '#20', # Timer/Counter2 Compare Match B
+ 'TIMER2_OVFAddr' : '#22', # Timer/Counter2 Overflow
+ 'TIMER1_CAPTAddr' : '#24', # Timer/Counter1 Capture Event
+ 'TIMER1_COMPAAddr' : '#26', # Timer/Counter1 Compare Match A
+ 'TIMER1_COMPBAddr' : '#28', # Timer/Counter1 Compare Match B
+ 'TIMER1_OVFAddr' : '#30', # Timer/Counter1 Overflow
+ 'TIMER0_COMPAAddr' : '#32', # Timer/Counter0 Compare Match A
+ 'TIMER0_COMPBAddr' : '#34', # Timer/Counter0 Compare Match B
+ 'TIMER0_OVFAddr' : '#36', # Timer/Counter0 Overflow
+ 'SPI_STCAddr' : '#38', # SPI Serial Transfer Complete
+ 'USART0_RXAddr' : '#40', # USART0, Rx Complete
+ 'USART0_UDREAddr' : '#42', # USART0 Data register Empty
+ 'USART0_TXAddr' : '#44', # USART0, Tx Complete
+ 'ANALOG_COMPAddr' : '#46', # Analog Comparator
+ 'ADCAddr' : '#48', # ADC Conversion Complete
+ 'EE_READYAddr' : '#50', # EEPROM Ready
+ 'TWIAddr' : '#52', # 2-wire Serial Interface
+ 'SPM_READYAddr' : '#54', # Store Program Memory Read
+ 'USART1_RXAddr' : '#56', # USART1 RX complete
+ 'USART1_UDREAddr' : '#58', # USART1 Data Register Empty
+ 'USART1_TXAddr' : '#60', # USART1 TX complete
+
+# Module ANALOG_COMPARATOR
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
+ 'ACSR' : '$50', # Analog Comparator Control And
+ 'ACSR_ACD': '$80', # Analog Comparator Disable
+ 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
+ 'ACSR_ACO': '$20', # Analog Compare Output
+ 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
+ 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
+ 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
+ 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
+ 'DIDR1' : '$7f', # Digital Input Disable Register
+ 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
+ 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
+
+# Module USART0
+ 'UDR0' : '$c6', # USART I/O Data Register
+ 'UCSR0A' : '$c0', # USART Control and Status Regis
+ 'UCSR0A_RXC0': '$80', # USART Receive Complete
+ 'UCSR0A_TXC0': '$40', # USART Transmitt Complete
+ 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
+ 'UCSR0A_FE0': '$10', # Framing Error
+ 'UCSR0A_DOR0': '$8', # Data overRun
+ 'UCSR0A_UPE0': '$4', # Parity Error
+ 'UCSR0A_U2X0': '$2', # Double the USART transmission
+ 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
+ 'UCSR0B' : '$c1', # USART Control and Status Regis
+ 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
+ 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
+ 'UCSR0B_UDRIE0': '$20', # USART Data register Empty Inte
+ 'UCSR0B_RXEN0': '$10', # Receiver Enable
+ 'UCSR0B_TXEN0': '$8', # Transmitter Enable
+ 'UCSR0B_UCSZ02': '$4', # Character Size
+ 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
+ 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
+ 'UCSR0C' : '$c2', # USART Control and Status Regis
+ 'UCSR0C_UMSEL0': '$c0', # USART Mode Select
+ 'UCSR0C_UPM0': '$30', # Parity Mode Bits
+ 'UCSR0C_USBS0': '$8', # Stop Bit Select
+ 'UCSR0C_UCSZ0': '$6', # Character Size
+ 'UCSR0C_UCPOL0': '$1', # Clock Polarity
+ 'UBRR0' : '$c4', # USART Baud Rate Register Byte
+
+# Module PORTA
+ 'PORTA' : '$22', # Port A Data Register
+ 'DDRA' : '$21', # Port A Data Direction Register
+ 'PINA' : '$20', # Port A Input Pins
+
+# Module PORTB
+ 'PORTB' : '$25', # Port B Data Register
+ 'DDRB' : '$24', # Port B Data Direction Register
+ 'PINB' : '$23', # Port B Input Pins
+
+# Module PORTC
+ 'PORTC' : '$28', # Port C Data Register
+ 'DDRC' : '$27', # Port C Data Direction Register
+ 'PINC' : '$26', # Port C Input Pins
+
+# Module PORTD
+ 'PORTD' : '$2b', # Port D Data Register
+ 'DDRD' : '$2a', # Port D Data Direction Register
+ 'PIND' : '$29', # Port D Input Pins
+
+# Module TIMER_COUNTER_0
+ 'OCR0B' : '$48', # Timer/Counter0 Output Compare
+ 'OCR0A' : '$47', # Timer/Counter0 Output Compare
+ 'TCNT0' : '$46', # Timer/Counter0
+ 'TCCR0B' : '$45', # Timer/Counter Control Register
+ 'TCCR0B_FOC0A': '$80', # Force Output Compare A
+ 'TCCR0B_FOC0B': '$40', # Force Output Compare B
+ 'TCCR0B_WGM02': '$8', #
+ 'TCCR0B_CS0': '$7', # Clock Select
+ 'TCCR0A' : '$44', # Timer/Counter Control Registe
+ 'TCCR0A_COM0A': '$c0', # Compare Output Mode, Phase Cor
+ 'TCCR0A_COM0B': '$30', # Compare Output Mode, Fast PWm
+ 'TCCR0A_WGM0': '$3', # Waveform Generation Mode
+ 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
+ 'TIMSK0_OCIE0B': '$4', # Timer/Counter0 Output Compare
+ 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
+ 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
+ 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
+ 'TIFR0_OCF0B': '$4', # Timer/Counter0 Output Compare
+ 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
+ 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSRSYNC': '$1', # Prescaler Reset Timer/Counter1
+
+# Module TIMER_COUNTER_2
+ 'TIMSK2' : '$70', # Timer/Counter Interrupt Mask r
+ 'TIMSK2_OCIE2B': '$4', # Timer/Counter2 Output Compare
+ 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
+ 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
+ 'TIFR2' : '$37', # Timer/Counter Interrupt Flag R
+ 'TIFR2_OCF2B': '$4', # Output Compare Flag 2B
+ 'TIFR2_OCF2A': '$2', # Output Compare Flag 2A
+ 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
+ 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
+ 'TCCR2A_COM2A': '$c0', # Compare Output Mode bits
+ 'TCCR2A_COM2B': '$30', # Compare Output Mode bits
+ 'TCCR2A_WGM2': '$3', # Waveform Genration Mode
+ 'TCCR2B' : '$b1', # Timer/Counter2 Control Registe
+ 'TCCR2B_FOC2A': '$80', # Force Output Compare A
+ 'TCCR2B_FOC2B': '$40', # Force Output Compare B
+ 'TCCR2B_WGM22': '$8', # Waveform Generation Mode
+ 'TCCR2B_CS2': '$7', # Clock Select bits
+ 'TCNT2' : '$b2', # Timer/Counter2
+ 'OCR2B' : '$b4', # Timer/Counter2 Output Compare
+ 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
+ 'ASSR' : '$b6', # Asynchronous Status Register
+ 'ASSR_EXCLK': '$40', # Enable External Clock Input
+ 'ASSR_AS2': '$20', # Asynchronous Timer/Counter2
+ 'ASSR_TCN2UB': '$10', # Timer/Counter2 Update Busy
+ 'ASSR_OCR2AUB': '$8', # Output Compare Register2 Updat
+ 'ASSR_OCR2BUB': '$4', # Output Compare Register 2 Upda
+ 'ASSR_TCR2AUB': '$2', # Timer/Counter Control Register
+ 'ASSR_TCR2BUB': '$1', # Timer/Counter Control Register
+ 'GTCCR' : '$43', # General Timer Counter Control
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSRASY': '$2', # Prescaler Reset Timer/Counter2
+
+# Module WATCHDOG
+ 'WDTCSR' : '$60', # Watchdog Timer Control Registe
+ 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
+ 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
+ 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
+ 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
+ 'WDTCSR_WDE': '$8', # Watch Dog Enable
+
+# Module JTAG
+ 'OCDR' : '$51', # On-Chip Debug Related Register
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_JTD': '$80', # JTAG Interface Disable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+
+# Module BOOT_LOAD
+ 'SPMCSR' : '$57', # Store Program Memory Control R
+ 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
+ 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
+ 'SPMCSR_SIGRD': '$20', # Signature Row Read
+ 'SPMCSR_RWWSRE': '$10', # Read While Write section read
+ 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
+ 'SPMCSR_PGWRT': '$4', # Page Write
+ 'SPMCSR_PGERS': '$2', # Page Erase
+ 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
+
+# Module EXTERNAL_INTERRUPT
+ 'EICRA' : '$69', # External Interrupt Control Reg
+ 'EICRA_ISC2': '$30', # External Interrupt Sense Contr
+ 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
+ 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
+ 'EIMSK' : '$3d', # External Interrupt Mask Regist
+ 'EIMSK_INT': '$7', # External Interrupt Request 2 E
+ 'EIFR' : '$3c', # External Interrupt Flag Regist
+ 'EIFR_INTF': '$7', # External Interrupt Flags
+ 'PCMSK3' : '$73', # Pin Change Mask Register 3
+ 'PCMSK3_PCINT': '$ff', # Pin Change Enable Masks
+ 'PCMSK2' : '$6d', # Pin Change Mask Register 2
+ 'PCMSK2_PCINT': '$ff', # Pin Change Enable Masks
+ 'PCMSK1' : '$6c', # Pin Change Mask Register 1
+ 'PCMSK1_PCINT': '$ff', # Pin Change Enable Masks
+ 'PCMSK0' : '$6b', # Pin Change Mask Register 0
+ 'PCMSK0_PCINT': '$ff', # Pin Change Enable Masks
+ 'PCIFR' : '$3b', # Pin Change Interrupt Flag Regi
+ 'PCIFR_PCIF': '$f', # Pin Change Interrupt Flags
+ 'PCICR' : '$68', # Pin Change Interrupt Control R
+ 'PCICR_PCIE': '$f', # Pin Change Interrupt Enables
+
+# Module AD_CONVERTER
+ 'ADMUX' : '$7c', # The ADC multiplexer Selection
+ 'ADMUX_REFS': '$c0', # Reference Selection Bits
+ 'ADMUX_ADLAR': '$20', # Left Adjust Result
+ 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
+ 'ADC' : '$78', # ADC Data Register Bytes
+ 'ADCSRA' : '$7a', # The ADC Control and Status reg
+ 'ADCSRA_ADEN': '$80', # ADC Enable
+ 'ADCSRA_ADSC': '$40', # ADC Start Conversion
+ 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
+ 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
+ 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
+ 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
+ 'ADCSRB' : '$7b', # The ADC Control and Status reg
+ 'ADCSRB_ACME': '$40', #
+ 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Source bits
+ 'DIDR0' : '$7e', # Digital Input Disable Register
+ 'DIDR0_ADC7D': '$80', #
+ 'DIDR0_ADC6D': '$40', #
+ 'DIDR0_ADC5D': '$20', #
+ 'DIDR0_ADC4D': '$10', #
+ 'DIDR0_ADC3D': '$8', #
+ 'DIDR0_ADC2D': '$4', #
+ 'DIDR0_ADC1D': '$2', #
+ 'DIDR0_ADC0D': '$1', #
+
+# Module TIMER_COUNTER_1
+ 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
+ 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
+ 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
+ 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
+ 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
+ 'TIFR1' : '$36', # Timer/Counter Interrupt Flag r
+ 'TIFR1_ICF1': '$20', # Timer/Counter1 Input Capture F
+ 'TIFR1_OCF1B': '$4', # Timer/Counter1 Output Compare
+ 'TIFR1_OCF1A': '$2', # Timer/Counter1 Output Compare
+ 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
+ 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
+ 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
+ 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
+ 'TCCR1A_WGM1': '$3', # Pulse Width Modulator Select B
+ 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
+ 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
+ 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
+ 'TCCR1B_WGM1': '$18', # Waveform Generation Mode Bits
+ 'TCCR1B_CS1': '$7', # Clock Select1 bits
+ 'TCCR1C' : '$82', # Timer/Counter1 Control Registe
+ 'TCCR1C_FOC1A': '$80', # Force Output Compare for Chann
+ 'TCCR1C_FOC1B': '$40', # Force Output Compare for Chann
+ 'TCNT1' : '$84', # Timer/Counter1 Bytes
+ 'OCR1A' : '$88', # Timer/Counter1 Output Compare
+ 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
+ 'ICR1' : '$86', # Timer/Counter1 Input Capture R
+
+# Module EEPROM
+ 'EEAR' : '$41', # EEPROM Address Register Low By
+ 'EEDR' : '$40', # EEPROM Data Register
+ 'EECR' : '$3f', # EEPROM Control Register
+ 'EECR_EEPM': '$30', # EEPROM Programming Mode Bits
+ 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
+ 'EECR_EEMPE': '$4', # EEPROM Master Write Enable
+ 'EECR_EEPE': '$2', # EEPROM Write Enable
+ 'EECR_EERE': '$1', # EEPROM Read Enable
+
+# Module TWI
+ 'TWAMR' : '$bd', # TWI (Slave) Address Mask Regis
+ 'TWAMR_TWAM': '$fe', #
+ 'TWBR' : '$b8', # TWI Bit Rate register
+ 'TWCR' : '$bc', # TWI Control Register
+ 'TWCR_TWINT': '$80', # TWI Interrupt Flag
+ 'TWCR_TWEA': '$40', # TWI Enable Acknowledge Bit
+ 'TWCR_TWSTA': '$20', # TWI Start Condition Bit
+ 'TWCR_TWSTO': '$10', # TWI Stop Condition Bit
+ 'TWCR_TWWC': '$8', # TWI Write Collition Flag
+ 'TWCR_TWEN': '$4', # TWI Enable Bit
+ 'TWCR_TWIE': '$1', # TWI Interrupt Enable
+ 'TWSR' : '$b9', # TWI Status Register
+ 'TWSR_TWS': '$f8', # TWI Status
+ 'TWSR_TWPS': '$3', # TWI Prescaler
+ 'TWDR' : '$bb', # TWI Data register
+ 'TWAR' : '$ba', # TWI (Slave) Address register
+ 'TWAR_TWA': '$fe', # TWI (Slave) Address register B
+ 'TWAR_TWGCE': '$1', # TWI General Call Recognition E
+
+# Module USART1
+ 'UDR1' : '$ce', # USART I/O Data Register
+ 'UCSR1A' : '$c8', # USART Control and Status Regis
+ 'UCSR1A_RXC1': '$80', # USART Receive Complete
+ 'UCSR1A_TXC1': '$40', # USART Transmitt Complete
+ 'UCSR1A_UDRE1': '$20', # USART Data Register Empty
+ 'UCSR1A_FE1': '$10', # Framing Error
+ 'UCSR1A_DOR1': '$8', # Data overRun
+ 'UCSR1A_UPE1': '$4', # Parity Error
+ 'UCSR1A_U2X1': '$2', # Double the USART transmission
+ 'UCSR1A_MPCM1': '$1', # Multi-processor Communication
+ 'UCSR1B' : '$c9', # USART Control and Status Regis
+ 'UCSR1B_RXCIE1': '$80', # RX Complete Interrupt Enable
+ 'UCSR1B_TXCIE1': '$40', # TX Complete Interrupt Enable
+ 'UCSR1B_UDRIE1': '$20', # USART Data register Empty Inte
+ 'UCSR1B_RXEN1': '$10', # Receiver Enable
+ 'UCSR1B_TXEN1': '$8', # Transmitter Enable
+ 'UCSR1B_UCSZ12': '$4', # Character Size
+ 'UCSR1B_RXB81': '$2', # Receive Data Bit 8
+ 'UCSR1B_TXB81': '$1', # Transmit Data Bit 8
+ 'UCSR1C' : '$ca', # USART Control and Status Regis
+ 'UCSR1C_UMSEL1': '$c0', # USART Mode Select
+ 'UCSR1C_UPM1': '$30', # Parity Mode Bits
+ 'UCSR1C_USBS1': '$8', # Stop Bit Select
+ 'UCSR1C_UCSZ1': '$6', # Character Size
+ 'UCSR1C_UCPOL1': '$1', # Clock Polarity
+ 'UBRR1' : '$cc', # USART Baud Rate Register Byte
+
+# Module CPU
+ 'SREG' : '$5f', # Status Register
+ 'SREG_I': '$80', # Global Interrupt Enable
+ 'SREG_T': '$40', # Bit Copy Storage
+ 'SREG_H': '$20', # Half Carry Flag
+ 'SREG_S': '$10', # Sign Bit
+ 'SREG_V': '$8', # Two's Complement Overflow Flag
+ 'SREG_N': '$4', # Negative Flag
+ 'SREG_Z': '$2', # Zero Flag
+ 'SREG_C': '$1', # Carry Flag
+ 'SP' : '$5d', # Stack Pointer
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_JTD': '$80', # JTAG Interface Disable
+ 'MCUCR_BODS': '$40', # BOD Power Down in Sleep
+ 'MCUCR_BODSE': '$20', # BOD Power Down in Sleep Enable
+ 'MCUCR_PUD': '$10', # Pull-up disable
+ 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
+ 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+ 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
+ 'MCUSR_BORF': '$4', # Brown-out Reset Flag
+ 'MCUSR_EXTRF': '$2', # External Reset Flag
+ 'MCUSR_PORF': '$1', # Power-on reset flag
+ 'OSCCAL' : '$66', # Oscillator Calibration Value
+ 'CLKPR' : '$61', #
+ 'CLKPR_CLKPCE': '$80', #
+ 'CLKPR_CLKPS': '$f', #
+ 'SMCR' : '$53', # Sleep Mode Control Register
+ 'SMCR_SM': '$e', # Sleep Mode Select bits
+ 'SMCR_SE': '$1', # Sleep Enable
+ 'GPIOR2' : '$4b', # General Purpose IO Register 2
+ 'GPIOR2_GPIOR': '$ff', # General Purpose IO Register 2
+ 'GPIOR1' : '$4a', # General Purpose IO Register 1
+ 'GPIOR1_GPIOR': '$ff', # General Purpose IO Register 1
+ 'GPIOR0' : '$3e', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR07': '$80', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR06': '$40', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR05': '$20', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR04': '$10', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR03': '$8', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR02': '$4', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR01': '$2', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR00': '$1', # General Purpose IO Register 0
+ 'PRR0' : '$64', # Power Reduction Register0
+ 'PRR0_PRTWI': '$80', # Power Reduction TWI
+ 'PRR0_PRTIM2': '$40', # Power Reduction Timer/Counter2
+ 'PRR0_PRTIM0': '$20', # Power Reduction Timer/Counter0
+ 'PRR0_PRUSART': '$12', # Power Reduction USARTs
+ 'PRR0_PRTIM1': '$8', # Power Reduction Timer/Counter1
+ 'PRR0_PRSPI': '$4', # Power Reduction Serial Periphe
+ 'PRR0_PRADC': '$1', # Power Reduction ADC
+
+# Module SPI
+ 'SPDR' : '$4e', # SPI Data Register
+ 'SPSR' : '$4d', # SPI Status Register
+ 'SPSR_SPIF': '$80', # SPI Interrupt Flag
+ 'SPSR_WCOL': '$40', # Write Collision Flag
+ 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
+ 'SPCR' : '$4c', # SPI Control Register
+ 'SPCR_SPIE': '$80', # SPI Interrupt Enable
+ 'SPCR_SPE': '$40', # SPI Enable
+ 'SPCR_DORD': '$20', # Data Order
+ 'SPCR_MSTR': '$10', # Master/Slave Select
+ 'SPCR_CPOL': '$8', # Clock polarity
+ 'SPCR_CPHA': '$4', # Clock Phase
+ 'SPCR_SPR': '$3', # SPI Clock Rate Selects
+
+ '__amforth_dummy':'0'
+}
diff --git a/amforth-6.5/avr8/devices/atmega644pa/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega644pa/words/no-jtag.asm
new file mode 100644
index 0000000..352a4bb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega644pa/words/no-jtag.asm
@@ -0,0 +1,14 @@
+; ( -- )
+; ( -- )
+; MCU
+; disable jtag at runtime
+VE_NOJTAG:
+ .dw $FF05
+ .db "-jtag",0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOJTAG
+XT_NOJTAG:
+ .dw PFA_NOJTAG
+PFA_NOJTAG:
+
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega644pa/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega644pa/words/no-wdt.asm
new file mode 100644
index 0000000..ff6ddd1
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega644pa/words/no-wdt.asm
@@ -0,0 +1,34 @@
+; ( -- )
+; MCU
+; disable watch dog timer at runtime
+VE_NOWDT:
+ .dw $ff04
+ .db "-wdt"
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOWDT
+XT_NOWDT:
+ .dw PFA_NOWDT
+PFA_NOWDT:
+
+ in temp1,SREG
+ push temp1
+ ; Turn always off global interrupt.
+ cli
+ ; Reset Watchdog Timer
+ wdr
+ ; Clear WDRF in MCUSR
+ in temp1, MCUSR
+ andi temp1, (0xff & (0<<WDRF))
+ out MCUSR, temp1
+ ; Write logical one to WDCE and WDE
+ ; Keep old prescaler setting to prevent unintentional time-out
+ in_ temp1, WDTCSR
+ ori temp1, (1<<WDCE) | (1<<WDE)
+ out_ WDTCSR, temp1
+ ; Turn off WDT
+ ldi temp1, (0<<WDE)
+ out_ WDTCSR, temp1
+ ; restore status register
+ pop temp1
+ out SREG,temp1
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega644pa/words/sleep.asm b/amforth-6.5/avr8/devices/atmega644pa/words/sleep.asm
new file mode 100644
index 0000000..256249c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega644pa/words/sleep.asm
@@ -0,0 +1,19 @@
+; ( mode -- )
+; MCU
+; put the controller into the specified sleep mode
+VE_SLEEP:
+ .dw $ff05
+ .db "sleep", 0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_SLEEP
+XT_SLEEP:
+ .dw PFA_SLEEP
+PFA_SLEEP:
+ andi tosl, 7 ; leave only legal mode bits
+ lsl tosl ; move to correct location (bits 3-1)
+ ori tosl, 1 ; set the SE bit
+ out_ SMCR, tosl ; set the sleep config
+ sleep ; nighty-night
+ out_ SMCR, zerol ; 0 protects against accidental sleeps
+ loadtos ; pop argument from stack
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega645/atmega645.frt b/amforth-6.5/avr8/devices/atmega645/atmega645.frt
new file mode 100644
index 0000000..b9d8cbc
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega645/atmega645.frt
@@ -0,0 +1,285 @@
+\ Partname: ATmega645
+\ generated automatically
+
+\ AD_CONVERTER
+&124 constant ADMUX \ The ADC multiplexer Selection Register
+ $C0 constant ADMUX_REFS \ Reference Selection Bits
+ $20 constant ADMUX_ADLAR \ Left Adjust Result
+ $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
+&122 constant ADCSRA \ The ADC Control and Status register
+ $80 constant ADCSRA_ADEN \ ADC Enable
+ $40 constant ADCSRA_ADSC \ ADC Start Conversion
+ $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
+ $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
+ $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
+ $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
+&120 constant ADC \ ADC Data Register Bytes
+&123 constant ADCSRB \ ADC Control and Status Register B
+ $07 constant ADCSRB_ADTS \ ADC Auto Trigger Sources
+&126 constant DIDR0 \ Digital Input Disable Register 0
+ $80 constant DIDR0_ADC7D \ ADC7 Digital input Disable
+ $40 constant DIDR0_ADC6D \ ADC6 Digital input Disable
+ $20 constant DIDR0_ADC5D \ ADC5 Digital input Disable
+ $10 constant DIDR0_ADC4D \ ADC4 Digital input Disable
+ $08 constant DIDR0_ADC3D \ ADC3 Digital input Disable
+ $04 constant DIDR0_ADC2D \ ADC2 Digital input Disable
+ $02 constant DIDR0_ADC1D \ ADC1 Digital input Disable
+ $01 constant DIDR0_ADC0D \ ADC0 Digital input Disable
+\ ANALOG_COMPARATOR
+&80 constant ACSR \ Analog Comparator Control And Status Register
+ $80 constant ACSR_ACD \ Analog Comparator Disable
+ $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
+ $20 constant ACSR_ACO \ Analog Compare Output
+ $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
+ $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
+ $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
+ $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
+&127 constant DIDR1 \ Digital Input Disable Register 1
+ $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
+ $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
+\ SPI
+&76 constant SPCR \ SPI Control Register
+ $80 constant SPCR_SPIE \ SPI Interrupt Enable
+ $40 constant SPCR_SPE \ SPI Enable
+ $20 constant SPCR_DORD \ Data Order
+ $10 constant SPCR_MSTR \ Master/Slave Select
+ $08 constant SPCR_CPOL \ Clock polarity
+ $04 constant SPCR_CPHA \ Clock Phase
+ $03 constant SPCR_SPR \ SPI Clock Rate Selects
+&77 constant SPSR \ SPI Status Register
+ $80 constant SPSR_SPIF \ SPI Interrupt Flag
+ $40 constant SPSR_WCOL \ Write Collision Flag
+ $01 constant SPSR_SPI2X \ Double SPI Speed Bit
+&78 constant SPDR \ SPI Data Register
+\ USI
+&186 constant USIDR \ USI Data Register
+&185 constant USISR \ USI Status Register
+ $80 constant USISR_USISIF \ Start Condition Interrupt Flag
+ $40 constant USISR_USIOIF \ Counter Overflow Interrupt Flag
+ $20 constant USISR_USIPF \ Stop Condition Flag
+ $10 constant USISR_USIDC \ Data Output Collision
+ $0F constant USISR_USICNT \ USI Counter Value Bits
+&184 constant USICR \ USI Control Register
+ $80 constant USICR_USISIE \ Start Condition Interrupt Enable
+ $40 constant USICR_USIOIE \ Counter Overflow Interrupt Enable
+ $30 constant USICR_USIWM \ USI Wire Mode Bits
+ $0C constant USICR_USICS \ USI Clock Source Select Bits
+ $02 constant USICR_USICLK \ Clock Strobe
+ $01 constant USICR_USITC \ Toggle Clock Port Pin
+\ CPU
+&95 constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ $08 constant SREG_V \ Two's Complement Overflow Flag
+ $04 constant SREG_N \ Negative Flag
+ $02 constant SREG_Z \ Zero Flag
+ $01 constant SREG_C \ Carry Flag
+&93 constant SP \ Stack Pointer
+&85 constant MCUCR \ MCU Control Register
+ $10 constant MCUCR_PUD \ Pull-up disable
+ $02 constant MCUCR_IVSEL \ Interrupt Vector Select
+ $01 constant MCUCR_IVCE \ Interrupt Vector Change Enable
+&84 constant MCUSR \ MCU Status Register
+ $10 constant MCUSR_JTRF \ JTAG Reset Flag
+ $08 constant MCUSR_WDRF \ Watchdog Reset Flag
+ $04 constant MCUSR_BORF \ Brown-out Reset Flag
+ $02 constant MCUSR_EXTRF \ External Reset Flag
+ $01 constant MCUSR_PORF \ Power-on reset flag
+&102 constant OSCCAL \ Oscillator Calibration Value
+&97 constant CLKPR \ Clock Prescale Register
+ $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable
+ $0F constant CLKPR_CLKPS \ Clock Prescaler Select Bits
+&100 constant PRR \ Power Reduction Register
+ $10 constant PRR_PRLCD \ Power Reduction LCD
+ $08 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
+ $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
+ $02 constant PRR_PRUSART0 \ Power Reduction USART
+ $01 constant PRR_PRADC \ Power Reduction ADC
+&83 constant SMCR \ Sleep Mode Control Register
+ $0E constant SMCR_SM \ Sleep Mode Select bits
+ $01 constant SMCR_SE \ Sleep Enable
+&75 constant GPIOR2 \ General Purpose IO Register 2
+&74 constant GPIOR1 \ General Purpose IO Register 1
+&62 constant GPIOR0 \ General Purpose IO Register 0
+\ JTAG
+&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
+\ EXTERNAL_INTERRUPT
+&105 constant EICRA \ External Interrupt Control Register A
+ $02 constant EICRA_ISC01 \ External Interrupt Sense Control 0 Bit 1
+ $01 constant EICRA_ISC00 \ External Interrupt Sense Control 0 Bit 0
+&61 constant EIMSK \ External Interrupt Mask Register
+ $F0 constant EIMSK_PCIE \ Pin Change Interrupt Enables
+ $01 constant EIMSK_INT0 \ External Interrupt Request 0 Enable
+&60 constant EIFR \ External Interrupt Flag Register
+ $F0 constant EIFR_PCIF \ Pin Change Interrupt Flags
+ $01 constant EIFR_INTF0 \ External Interrupt Flag 0
+&108 constant PCMSK1 \ Pin Change Mask Register 1
+&107 constant PCMSK0 \ Pin Change Mask Register 0
+\ EEPROM
+&65 constant EEAR \ EEPROM Read/Write Access Bytes
+&64 constant EEDR \ EEPROM Data Register
+&63 constant EECR \ EEPROM Control Register
+ $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
+ $04 constant EECR_EEMWE \ EEPROM Master Write Enable
+ $02 constant EECR_EEWE \ EEPROM Write Enable
+ $01 constant EECR_EERE \ EEPROM Read Enable
+\ PORTA
+&34 constant PORTA \ Port A Data Register
+&33 constant DDRA \ Port A Data Direction Register
+&32 constant PINA \ Port A Input Pins
+\ PORTB
+&37 constant PORTB \ Port B Data Register
+&36 constant DDRB \ Port B Data Direction Register
+&35 constant PINB \ Port B Input Pins
+\ PORTC
+&40 constant PORTC \ Port C Data Register
+&39 constant DDRC \ Port C Data Direction Register
+&38 constant PINC \ Port C Input Pins
+\ PORTD
+&43 constant PORTD \ Port D Data Register
+&42 constant DDRD \ Port D Data Direction Register
+&41 constant PIND \ Port D Input Pins
+\ PORTE
+&46 constant PORTE \ Data Register, Port E
+&45 constant DDRE \ Data Direction Register, Port E
+&44 constant PINE \ Input Pins, Port E
+\ PORTF
+&49 constant PORTF \ Data Register, Port F
+&48 constant DDRF \ Data Direction Register, Port F
+&47 constant PINF \ Input Pins, Port F
+\ PORTG
+&52 constant PORTG \ Port G Data Register
+&51 constant DDRG \ Port G Data Direction Register
+&50 constant PING \ Port G Input Pins
+\ TIMER_COUNTER_0
+&68 constant TCCR0A \ Timer/Counter0 Control Register
+ $80 constant TCCR0A_FOC0A \ Force Output Compare
+ $40 constant TCCR0A_WGM00 \ Waveform Generation Mode 0
+ $30 constant TCCR0A_COM0A \ Compare Match Output Modes
+ $08 constant TCCR0A_WGM01 \ Waveform Generation Mode 1
+ $07 constant TCCR0A_CS0 \ Clock Selects
+&70 constant TCNT0 \ Timer/Counter0
+&71 constant OCR0A \ Timer/Counter0 Output Compare Register
+&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
+ $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match Interrupt Enable
+ $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
+&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
+ $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0
+ $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
+&67 constant GTCCR \ General Timer/Control Register
+ $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
+ $01 constant GTCCR_PSR310 \ Prescaler Reset Timer/Counter1 and Timer/Counter0
+\ TIMER_COUNTER_2
+&176 constant TCCR2A \ Timer/Counter2 Control Register
+ $80 constant TCCR2A_FOC2A \ Force Output Compare A
+ $40 constant TCCR2A_WGM20 \ Waveform Generation Mode
+ $30 constant TCCR2A_COM2A \ Compare Output Mode bits
+ $08 constant TCCR2A_WGM21 \ Waveform Generation Mode
+ $07 constant TCCR2A_CS2 \ Clock Select bits
+&178 constant TCNT2 \ Timer/Counter2
+&179 constant OCR2A \ Timer/Counter2 Output Compare Register
+&112 constant TIMSK2 \ Timer/Counter2 Interrupt Mask register
+ $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match Interrupt Enable
+ $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
+&55 constant TIFR2 \ Timer/Counter2 Interrupt Flag Register
+ $02 constant TIFR2_OCF2A \ Timer/Counter2 Output Compare Flag 2
+ $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
+&182 constant ASSR \ Asynchronous Status Register
+ $10 constant ASSR_EXCLK \ Enable External Clock Interrupt
+ $08 constant ASSR_AS2 \ AS2: Asynchronous Timer/Counter2
+ $04 constant ASSR_TCN2UB \ TCN2UB: Timer/Counter2 Update Busy
+ $02 constant ASSR_OCR2UB \ Output Compare Register2 Update Busy
+ $01 constant ASSR_TCR2UB \ TCR2UB: Timer/Counter Control Register2 Update Busy
+\ TIMER_COUNTER_1
+&128 constant TCCR1A \ Timer/Counter1 Control Register A
+ $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
+ $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
+ $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
+&129 constant TCCR1B \ Timer/Counter1 Control Register B
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
+ $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
+&130 constant TCCR1C \ Timer/Counter 1 Control Register C
+ $80 constant TCCR1C_FOC1A \ Force Output Compare 1A
+ $40 constant TCCR1C_FOC1B \ Force Output Compare 1B
+&132 constant TCNT1 \ Timer/Counter1 Bytes
+&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
+&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
+&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
+&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
+ $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
+ $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
+ $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
+ $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
+&54 constant TIFR1 \ Timer/Counter1 Interrupt Flag register
+ $20 constant TIFR1_ICF1 \ Input Capture Flag 1
+ $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
+ $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
+ $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
+\ WATCHDOG
+&96 constant WDTCR \ Watchdog Timer Control Register
+ $10 constant WDTCR_WDCE \ Watchdog Change Enable
+ $08 constant WDTCR_WDE \ Watch Dog Enable
+ $07 constant WDTCR_WDP \ Watch Dog Timer Prescaler bits
+\ BOOT_LOAD
+&87 constant SPMCSR \ Store Program Memory Control Register
+ $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
+ $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
+ $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
+ $04 constant SPMCSR_PGWRT \ Page Write
+ $02 constant SPMCSR_PGERS \ Page Erase
+ $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
+\ USART0
+&198 constant UDR0 \ USART I/O Data Register
+&192 constant UCSR0A \ USART Control and Status Register A
+ $80 constant UCSR0A_RXC0 \ USART Receive Complete
+ $40 constant UCSR0A_TXC0 \ USART Transmit Complete
+ $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
+ $10 constant UCSR0A_FE0 \ Framing Error
+ $08 constant UCSR0A_DOR0 \ Data OverRun
+ $04 constant UCSR0A_UPE0 \ USART Parity Error
+ $02 constant UCSR0A_U2X0 \ Double the USART Transmission Speed
+ $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
+&193 constant UCSR0B \ USART Control and Status Register B
+ $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
+ $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
+ $20 constant UCSR0B_UDRIE0 \ USART Data Register Empty Interrupt Enable
+ $10 constant UCSR0B_RXEN0 \ Receiver Enable
+ $08 constant UCSR0B_TXEN0 \ Transmitter Enable
+ $04 constant UCSR0B_UCSZ02 \ Character Size
+ $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
+ $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
+&194 constant UCSR0C \ USART Control and Status Register C
+ $40 constant UCSR0C_UMSEL0 \ USART Mode Select
+ $30 constant UCSR0C_UPM0 \ Parity Mode Bits
+ $08 constant UCSR0C_USBS0 \ Stop Bit Select
+ $06 constant UCSR0C_UCSZ0 \ Character Size
+ $01 constant UCSR0C_UCPOL0 \ Clock Polarity
+&196 constant UBRR0 \ USART Baud Rate Register Bytes
+
+\ Interrupts
+&2 constant INT0Addr \ External Interrupt Request 0
+&4 constant PCINT0Addr \ Pin Change Interrupt Request 0
+&6 constant PCINT1Addr \ Pin Change Interrupt Request 1
+&8 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
+&10 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
+&12 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+&14 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
+&16 constant TIMER1_COMPBAddr \ Timer/Counter Compare Match B
+&18 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+&20 constant TIMER0_COMPAddr \ Timer/Counter0 Compare Match
+&22 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
+&24 constant SPI__STCAddr \ SPI Serial Transfer Complete
+&26 constant USART0__RXAddr \ USART0, Rx Complete
+&28 constant USART0__UDREAddr \ USART0 Data register Empty
+&30 constant USART0__TXAddr \ USART0, Tx Complete
+&32 constant USI_STARTAddr \ USI Start Condition
+&34 constant USI_OVERFLOWAddr \ USI Overflow
+&36 constant ANALOG_COMPAddr \ Analog Comparator
+&38 constant ADCAddr \ ADC Conversion Complete
+&40 constant EE_READYAddr \ EEPROM Ready
+&42 constant SPM_READYAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/atmega645/device.asm b/amforth-6.5/avr8/devices/atmega645/device.asm
new file mode 100644
index 0000000..6fa9eb6
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega645/device.asm
@@ -0,0 +1,106 @@
+; Partname: ATmega645
+; generated automatically, do not edit
+
+.nolist
+ .include "m645def.inc"
+.list
+
+.equ ramstart = 256
+.equ CELLSIZE = 2
+.macro readflashcell
+ lsl zl
+ rol zh
+ lpm @0, Z+
+ lpm @1, Z+
+.endmacro
+.macro writeflashcell
+ lsl zl
+ rol zh
+.endmacro
+.set WANT_AD_CONVERTER = 0
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_SPI = 0
+.set WANT_USI = 0
+.set WANT_CPU = 0
+.set WANT_JTAG = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_EEPROM = 0
+.set WANT_PORTA = 0
+.set WANT_PORTB = 0
+.set WANT_PORTC = 0
+.set WANT_PORTD = 0
+.set WANT_PORTE = 0
+.set WANT_PORTF = 0
+.set WANT_PORTG = 0
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_TIMER_COUNTER_2 = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_WATCHDOG = 0
+.set WANT_BOOT_LOAD = 0
+.set WANT_USART0 = 0
+.equ intvecsize = 2 ; please verify; flash size: 65536 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.org 2
+ rcall isr ; External Interrupt Request 0
+.org 4
+ rcall isr ; Pin Change Interrupt Request 0
+.org 6
+ rcall isr ; Pin Change Interrupt Request 1
+.org 8
+ rcall isr ; Timer/Counter2 Compare Match
+.org 10
+ rcall isr ; Timer/Counter2 Overflow
+.org 12
+ rcall isr ; Timer/Counter1 Capture Event
+.org 14
+ rcall isr ; Timer/Counter1 Compare Match A
+.org 16
+ rcall isr ; Timer/Counter Compare Match B
+.org 18
+ rcall isr ; Timer/Counter1 Overflow
+.org 20
+ rcall isr ; Timer/Counter0 Compare Match
+.org 22
+ rcall isr ; Timer/Counter0 Overflow
+.org 24
+ rcall isr ; SPI Serial Transfer Complete
+.org 26
+ rcall isr ; USART0, Rx Complete
+.org 28
+ rcall isr ; USART0 Data register Empty
+.org 30
+ rcall isr ; USART0, Tx Complete
+.org 32
+ rcall isr ; USI Start Condition
+.org 34
+ rcall isr ; USI Overflow
+.org 36
+ rcall isr ; Analog Comparator
+.org 38
+ rcall isr ; ADC Conversion Complete
+.org 40
+ rcall isr ; EEPROM Ready
+.org 42
+ rcall isr ; Store Program Memory Read
+.equ INTVECTORS = 22
+.nooverlap
+
+; compatability layer (maybe empty)
+.equ EEPE = EEWE
+.equ EEMPE = EEMWE
+
+; controller data area, environment query mcu-info
+mcu_info:
+mcu_ramsize:
+ .dw 4096
+mcu_eepromsize:
+ .dw 2048
+mcu_maxdp:
+ .dw 57344
+mcu_numints:
+ .dw 22
+mcu_name:
+ .dw 9
+ .db "ATmega645",0
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega645/device.inc b/amforth-6.5/avr8/devices/atmega645/device.inc
new file mode 100644
index 0000000..3882309
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega645/device.inc
@@ -0,0 +1,1050 @@
+; Partname: ATmega645
+; generated automatically, no not edit
+
+.if WANT_AD_CONVERTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC multiplexer Selection Register
+VE_ADMUX:
+ .dw $ff05
+ .db "ADMUX",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADMUX
+XT_ADMUX:
+ .dw PFA_DOVARIABLE
+PFA_ADMUX:
+ .dw 124
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register
+VE_ADCSRA:
+ .dw $ff06
+ .db "ADCSRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRA
+XT_ADCSRA:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRA:
+ .dw 122
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register Bytes
+VE_ADC:
+ .dw $ff03
+ .db "ADC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADC
+XT_ADC:
+ .dw PFA_DOVARIABLE
+PFA_ADC:
+ .dw 120
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Control and Status Register B
+VE_ADCSRB:
+ .dw $ff06
+ .db "ADCSRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRB
+XT_ADCSRB:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRB:
+ .dw 123
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 0
+VE_DIDR0:
+ .dw $ff05
+ .db "DIDR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR0
+XT_DIDR0:
+ .dw PFA_DOVARIABLE
+PFA_DIDR0:
+ .dw 126
+
+.endif
+.if WANT_ANALOG_COMPARATOR == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Control And Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw 80
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 1
+VE_DIDR1:
+ .dw $ff05
+ .db "DIDR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR1
+XT_DIDR1:
+ .dw PFA_DOVARIABLE
+PFA_DIDR1:
+ .dw 127
+
+.endif
+.if WANT_SPI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR:
+ .dw $ff04
+ .db "SPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR
+XT_SPCR:
+ .dw PFA_DOVARIABLE
+PFA_SPCR:
+ .dw 76
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR:
+ .dw $ff04
+ .db "SPSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR
+XT_SPSR:
+ .dw PFA_DOVARIABLE
+PFA_SPSR:
+ .dw 77
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR:
+ .dw $ff04
+ .db "SPDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR
+XT_SPDR:
+ .dw PFA_DOVARIABLE
+PFA_SPDR:
+ .dw 78
+
+.endif
+.if WANT_USI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USI Data Register
+VE_USIDR:
+ .dw $ff05
+ .db "USIDR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USIDR
+XT_USIDR:
+ .dw PFA_DOVARIABLE
+PFA_USIDR:
+ .dw 186
+; ( -- addr ) System Constant
+; R( -- )
+; USI Status Register
+VE_USISR:
+ .dw $ff05
+ .db "USISR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USISR
+XT_USISR:
+ .dw PFA_DOVARIABLE
+PFA_USISR:
+ .dw 185
+; ( -- addr ) System Constant
+; R( -- )
+; USI Control Register
+VE_USICR:
+ .dw $ff05
+ .db "USICR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USICR
+XT_USICR:
+ .dw PFA_DOVARIABLE
+PFA_USICR:
+ .dw 184
+
+.endif
+.if WANT_CPU == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw 95
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer
+VE_SP:
+ .dw $ff02
+ .db "SP"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SP
+XT_SP:
+ .dw PFA_DOVARIABLE
+PFA_SP:
+ .dw 93
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw 85
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Status Register
+VE_MCUSR:
+ .dw $ff05
+ .db "MCUSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUSR
+XT_MCUSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUSR:
+ .dw 84
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Calibration Value
+VE_OSCCAL:
+ .dw $ff06
+ .db "OSCCAL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSCCAL
+XT_OSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_OSCCAL:
+ .dw 102
+; ( -- addr ) System Constant
+; R( -- )
+; Clock Prescale Register
+VE_CLKPR:
+ .dw $ff05
+ .db "CLKPR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKPR
+XT_CLKPR:
+ .dw PFA_DOVARIABLE
+PFA_CLKPR:
+ .dw 97
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register
+VE_PRR:
+ .dw $ff03
+ .db "PRR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR
+XT_PRR:
+ .dw PFA_DOVARIABLE
+PFA_PRR:
+ .dw 100
+; ( -- addr ) System Constant
+; R( -- )
+; Sleep Mode Control Register
+VE_SMCR:
+ .dw $ff04
+ .db "SMCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SMCR
+XT_SMCR:
+ .dw PFA_DOVARIABLE
+PFA_SMCR:
+ .dw 83
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 2
+VE_GPIOR2:
+ .dw $ff06
+ .db "GPIOR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR2
+XT_GPIOR2:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR2:
+ .dw 75
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 1
+VE_GPIOR1:
+ .dw $ff06
+ .db "GPIOR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR1
+XT_GPIOR1:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR1:
+ .dw 74
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 0
+VE_GPIOR0:
+ .dw $ff06
+ .db "GPIOR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR0
+XT_GPIOR0:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR0:
+ .dw 62
+
+.endif
+.if WANT_JTAG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; On-Chip Debug Related Register in I/O Memory
+VE_OCDR:
+ .dw $ff04
+ .db "OCDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCDR
+XT_OCDR:
+ .dw PFA_DOVARIABLE
+PFA_OCDR:
+ .dw 81
+
+.endif
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register A
+VE_EICRA:
+ .dw $ff05
+ .db "EICRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRA
+XT_EICRA:
+ .dw PFA_DOVARIABLE
+PFA_EICRA:
+ .dw 105
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Mask Register
+VE_EIMSK:
+ .dw $ff05
+ .db "EIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIMSK
+XT_EIMSK:
+ .dw PFA_DOVARIABLE
+PFA_EIMSK:
+ .dw 61
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Flag Register
+VE_EIFR:
+ .dw $ff04
+ .db "EIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIFR
+XT_EIFR:
+ .dw PFA_DOVARIABLE
+PFA_EIFR:
+ .dw 60
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 1
+VE_PCMSK1:
+ .dw $ff06
+ .db "PCMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK1
+XT_PCMSK1:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK1:
+ .dw 108
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 0
+VE_PCMSK0:
+ .dw $ff06
+ .db "PCMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK0
+XT_PCMSK0:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK0:
+ .dw 107
+
+.endif
+.if WANT_EEPROM == 1
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Read/Write Access Bytes
+VE_EEAR:
+ .dw $ff04
+ .db "EEAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEAR
+XT_EEAR:
+ .dw PFA_DOVARIABLE
+PFA_EEAR:
+ .dw 65
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw 64
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw 63
+
+.endif
+.if WANT_PORTA == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Register
+VE_PORTA:
+ .dw $ff05
+ .db "PORTA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTA
+XT_PORTA:
+ .dw PFA_DOVARIABLE
+PFA_PORTA:
+ .dw 34
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Direction Register
+VE_DDRA:
+ .dw $ff04
+ .db "DDRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRA
+XT_DDRA:
+ .dw PFA_DOVARIABLE
+PFA_DDRA:
+ .dw 33
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Input Pins
+VE_PINA:
+ .dw $ff04
+ .db "PINA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINA
+XT_PINA:
+ .dw PFA_DOVARIABLE
+PFA_PINA:
+ .dw 32
+
+.endif
+.if WANT_PORTB == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw 37
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw 36
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw 35
+
+.endif
+.if WANT_PORTC == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Register
+VE_PORTC:
+ .dw $ff05
+ .db "PORTC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTC
+XT_PORTC:
+ .dw PFA_DOVARIABLE
+PFA_PORTC:
+ .dw 40
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Direction Register
+VE_DDRC:
+ .dw $ff04
+ .db "DDRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRC
+XT_DDRC:
+ .dw PFA_DOVARIABLE
+PFA_DDRC:
+ .dw 39
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Input Pins
+VE_PINC:
+ .dw $ff04
+ .db "PINC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINC
+XT_PINC:
+ .dw PFA_DOVARIABLE
+PFA_PINC:
+ .dw 38
+
+.endif
+.if WANT_PORTD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw 43
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw 42
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw 41
+
+.endif
+.if WANT_PORTE == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port E
+VE_PORTE:
+ .dw $ff05
+ .db "PORTE",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTE
+XT_PORTE:
+ .dw PFA_DOVARIABLE
+PFA_PORTE:
+ .dw 46
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port E
+VE_DDRE:
+ .dw $ff04
+ .db "DDRE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRE
+XT_DDRE:
+ .dw PFA_DOVARIABLE
+PFA_DDRE:
+ .dw 45
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port E
+VE_PINE:
+ .dw $ff04
+ .db "PINE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINE
+XT_PINE:
+ .dw PFA_DOVARIABLE
+PFA_PINE:
+ .dw 44
+
+.endif
+.if WANT_PORTF == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port F
+VE_PORTF:
+ .dw $ff05
+ .db "PORTF",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTF
+XT_PORTF:
+ .dw PFA_DOVARIABLE
+PFA_PORTF:
+ .dw 49
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port F
+VE_DDRF:
+ .dw $ff04
+ .db "DDRF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRF
+XT_DDRF:
+ .dw PFA_DOVARIABLE
+PFA_DDRF:
+ .dw 48
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port F
+VE_PINF:
+ .dw $ff04
+ .db "PINF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINF
+XT_PINF:
+ .dw PFA_DOVARIABLE
+PFA_PINF:
+ .dw 47
+
+.endif
+.if WANT_PORTG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Data Register
+VE_PORTG:
+ .dw $ff05
+ .db "PORTG",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTG
+XT_PORTG:
+ .dw PFA_DOVARIABLE
+PFA_PORTG:
+ .dw 52
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Data Direction Register
+VE_DDRG:
+ .dw $ff04
+ .db "DDRG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRG
+XT_DDRG:
+ .dw PFA_DOVARIABLE
+PFA_DDRG:
+ .dw 51
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Input Pins
+VE_PING:
+ .dw $ff04
+ .db "PING"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PING
+XT_PING:
+ .dw PFA_DOVARIABLE
+PFA_PING:
+ .dw 50
+
+.endif
+.if WANT_TIMER_COUNTER_0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Control Register
+VE_TCCR0A:
+ .dw $ff06
+ .db "TCCR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0A
+XT_TCCR0A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0A:
+ .dw 68
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw 70
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0A:
+ .dw $ff05
+ .db "OCR0A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0A
+XT_OCR0A:
+ .dw PFA_DOVARIABLE
+PFA_OCR0A:
+ .dw 71
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Mask Register
+VE_TIMSK0:
+ .dw $ff06
+ .db "TIMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK0
+XT_TIMSK0:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK0:
+ .dw 110
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Flag register
+VE_TIFR0:
+ .dw $ff05
+ .db "TIFR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR0
+XT_TIFR0:
+ .dw PFA_DOVARIABLE
+PFA_TIFR0:
+ .dw 53
+; ( -- addr ) System Constant
+; R( -- )
+; General Timer/Control Register
+VE_GTCCR:
+ .dw $ff05
+ .db "GTCCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GTCCR
+XT_GTCCR:
+ .dw PFA_DOVARIABLE
+PFA_GTCCR:
+ .dw 67
+
+.endif
+.if WANT_TIMER_COUNTER_2 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register
+VE_TCCR2A:
+ .dw $ff06
+ .db "TCCR2A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2A
+XT_TCCR2A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2A:
+ .dw 176
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2
+VE_TCNT2:
+ .dw $ff05
+ .db "TCNT2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT2
+XT_TCNT2:
+ .dw PFA_DOVARIABLE
+PFA_TCNT2:
+ .dw 178
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register
+VE_OCR2A:
+ .dw $ff05
+ .db "OCR2A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2A
+XT_OCR2A:
+ .dw PFA_DOVARIABLE
+PFA_OCR2A:
+ .dw 179
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Interrupt Mask register
+VE_TIMSK2:
+ .dw $ff06
+ .db "TIMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK2
+XT_TIMSK2:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK2:
+ .dw 112
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Interrupt Flag Register
+VE_TIFR2:
+ .dw $ff05
+ .db "TIFR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR2
+XT_TIFR2:
+ .dw PFA_DOVARIABLE
+PFA_TIFR2:
+ .dw 55
+; ( -- addr ) System Constant
+; R( -- )
+; Asynchronous Status Register
+VE_ASSR:
+ .dw $ff04
+ .db "ASSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ASSR
+XT_ASSR:
+ .dw PFA_DOVARIABLE
+PFA_ASSR:
+ .dw 182
+
+.endif
+.if WANT_TIMER_COUNTER_1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw 128
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw 129
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter 1 Control Register C
+VE_TCCR1C:
+ .dw $ff06
+ .db "TCCR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1C
+XT_TCCR1C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1C:
+ .dw 130
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Bytes
+VE_TCNT1:
+ .dw $ff05
+ .db "TCNT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1
+XT_TCNT1:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1:
+ .dw 132
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register A Bytes
+VE_OCR1A:
+ .dw $ff05
+ .db "OCR1A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1A
+XT_OCR1A:
+ .dw PFA_DOVARIABLE
+PFA_OCR1A:
+ .dw 136
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register B Bytes
+VE_OCR1B:
+ .dw $ff05
+ .db "OCR1B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1B
+XT_OCR1B:
+ .dw PFA_DOVARIABLE
+PFA_OCR1B:
+ .dw 138
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Bytes
+VE_ICR1:
+ .dw $ff04
+ .db "ICR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1
+XT_ICR1:
+ .dw PFA_DOVARIABLE
+PFA_ICR1:
+ .dw 134
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Mask Register
+VE_TIMSK1:
+ .dw $ff06
+ .db "TIMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK1
+XT_TIMSK1:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK1:
+ .dw 111
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Flag register
+VE_TIFR1:
+ .dw $ff05
+ .db "TIFR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR1
+XT_TIFR1:
+ .dw PFA_DOVARIABLE
+PFA_TIFR1:
+ .dw 54
+
+.endif
+.if WANT_WATCHDOG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCR:
+ .dw $ff05
+ .db "WDTCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCR
+XT_WDTCR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCR:
+ .dw 96
+
+.endif
+.if WANT_BOOT_LOAD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control Register
+VE_SPMCSR:
+ .dw $ff06
+ .db "SPMCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCSR
+XT_SPMCSR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCSR:
+ .dw 87
+
+.endif
+.if WANT_USART0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR0:
+ .dw $ff04
+ .db "UDR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR0
+XT_UDR0:
+ .dw PFA_DOVARIABLE
+PFA_UDR0:
+ .dw 198
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR0A:
+ .dw $ff06
+ .db "UCSR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0A
+XT_UCSR0A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0A:
+ .dw 192
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR0B:
+ .dw $ff06
+ .db "UCSR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0B
+XT_UCSR0B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0B:
+ .dw 193
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR0C:
+ .dw $ff06
+ .db "UCSR0C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0C
+XT_UCSR0C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0C:
+ .dw 194
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Bytes
+VE_UBRR0:
+ .dw $ff05
+ .db "UBRR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR0
+XT_UBRR0:
+ .dw PFA_DOVARIABLE
+PFA_UBRR0:
+ .dw 196
+
+.endif
diff --git a/amforth-6.5/avr8/devices/atmega645/device.py b/amforth-6.5/avr8/devices/atmega645/device.py
new file mode 100644
index 0000000..e890093
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega645/device.py
@@ -0,0 +1,318 @@
+# Generated Automatically
+
+# Partname ATmega645
+
+MCUREGS = {
+# Interrupt Vectors
+ 'INT0Addr' : '#2', # External Interrupt Request 0
+ 'PCINT0Addr' : '#4', # Pin Change Interrupt Request 0
+ 'PCINT1Addr' : '#6', # Pin Change Interrupt Request 1
+ 'TIMER2_COMPAddr' : '#8', # Timer/Counter2 Compare Match
+ 'TIMER2_OVFAddr' : '#10', # Timer/Counter2 Overflow
+ 'TIMER1_CAPTAddr' : '#12', # Timer/Counter1 Capture Event
+ 'TIMER1_COMPAAddr' : '#14', # Timer/Counter1 Compare Match A
+ 'TIMER1_COMPBAddr' : '#16', # Timer/Counter Compare Match B
+ 'TIMER1_OVFAddr' : '#18', # Timer/Counter1 Overflow
+ 'TIMER0_COMPAddr' : '#20', # Timer/Counter0 Compare Match
+ 'TIMER0_OVFAddr' : '#22', # Timer/Counter0 Overflow
+ 'SPI_STCAddr' : '#24', # SPI Serial Transfer Complete
+ 'USART0_RXAddr' : '#26', # USART0, Rx Complete
+ 'USART0_UDREAddr' : '#28', # USART0 Data register Empty
+ 'USART0_TXAddr' : '#30', # USART0, Tx Complete
+ 'USI_STARTAddr' : '#32', # USI Start Condition
+ 'USI_OVERFLOWAddr' : '#34', # USI Overflow
+ 'ANALOG_COMPAddr' : '#36', # Analog Comparator
+ 'ADCAddr' : '#38', # ADC Conversion Complete
+ 'EE_READYAddr' : '#40', # EEPROM Ready
+ 'SPM_READYAddr' : '#42', # Store Program Memory Read
+
+# Module AD_CONVERTER
+ 'ADMUX' : '$7c', # The ADC multiplexer Selection
+ 'ADMUX_REFS': '$c0', # Reference Selection Bits
+ 'ADMUX_ADLAR': '$20', # Left Adjust Result
+ 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
+ 'ADCSRA' : '$7a', # The ADC Control and Status reg
+ 'ADCSRA_ADEN': '$80', # ADC Enable
+ 'ADCSRA_ADSC': '$40', # ADC Start Conversion
+ 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
+ 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
+ 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
+ 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
+ 'ADC' : '$78', # ADC Data Register Bytes
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Sources
+ 'DIDR0' : '$7e', # Digital Input Disable Register
+ 'DIDR0_ADC7D': '$80', # ADC7 Digital input Disable
+ 'DIDR0_ADC6D': '$40', # ADC6 Digital input Disable
+ 'DIDR0_ADC5D': '$20', # ADC5 Digital input Disable
+ 'DIDR0_ADC4D': '$10', # ADC4 Digital input Disable
+ 'DIDR0_ADC3D': '$8', # ADC3 Digital input Disable
+ 'DIDR0_ADC2D': '$4', # ADC2 Digital input Disable
+ 'DIDR0_ADC1D': '$2', # ADC1 Digital input Disable
+ 'DIDR0_ADC0D': '$1', # ADC0 Digital input Disable
+
+# Module ANALOG_COMPARATOR
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
+ 'ACSR' : '$50', # Analog Comparator Control And
+ 'ACSR_ACD': '$80', # Analog Comparator Disable
+ 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
+ 'ACSR_ACO': '$20', # Analog Compare Output
+ 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
+ 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
+ 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
+ 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
+ 'DIDR1' : '$7f', # Digital Input Disable Register
+ 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
+ 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
+
+# Module SPI
+ 'SPCR' : '$4c', # SPI Control Register
+ 'SPCR_SPIE': '$80', # SPI Interrupt Enable
+ 'SPCR_SPE': '$40', # SPI Enable
+ 'SPCR_DORD': '$20', # Data Order
+ 'SPCR_MSTR': '$10', # Master/Slave Select
+ 'SPCR_CPOL': '$8', # Clock polarity
+ 'SPCR_CPHA': '$4', # Clock Phase
+ 'SPCR_SPR': '$3', # SPI Clock Rate Selects
+ 'SPSR' : '$4d', # SPI Status Register
+ 'SPSR_SPIF': '$80', # SPI Interrupt Flag
+ 'SPSR_WCOL': '$40', # Write Collision Flag
+ 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
+ 'SPDR' : '$4e', # SPI Data Register
+
+# Module USI
+ 'USIDR' : '$ba', # USI Data Register
+ 'USISR' : '$b9', # USI Status Register
+ 'USISR_USISIF': '$80', # Start Condition Interrupt Flag
+ 'USISR_USIOIF': '$40', # Counter Overflow Interrupt Fla
+ 'USISR_USIPF': '$20', # Stop Condition Flag
+ 'USISR_USIDC': '$10', # Data Output Collision
+ 'USISR_USICNT': '$f', # USI Counter Value Bits
+ 'USICR' : '$b8', # USI Control Register
+ 'USICR_USISIE': '$80', # Start Condition Interrupt Enab
+ 'USICR_USIOIE': '$40', # Counter Overflow Interrupt Ena
+ 'USICR_USIWM': '$30', # USI Wire Mode Bits
+ 'USICR_USICS': '$c', # USI Clock Source Select Bits
+ 'USICR_USICLK': '$2', # Clock Strobe
+ 'USICR_USITC': '$1', # Toggle Clock Port Pin
+
+# Module CPU
+ 'SREG' : '$5f', # Status Register
+ 'SREG_I': '$80', # Global Interrupt Enable
+ 'SREG_T': '$40', # Bit Copy Storage
+ 'SREG_H': '$20', # Half Carry Flag
+ 'SREG_S': '$10', # Sign Bit
+ 'SREG_V': '$8', # Two's Complement Overflow Flag
+ 'SREG_N': '$4', # Negative Flag
+ 'SREG_Z': '$2', # Zero Flag
+ 'SREG_C': '$1', # Carry Flag
+ 'SP' : '$5d', # Stack Pointer
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_PUD': '$10', # Pull-up disable
+ 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
+ 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+ 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
+ 'MCUSR_BORF': '$4', # Brown-out Reset Flag
+ 'MCUSR_EXTRF': '$2', # External Reset Flag
+ 'MCUSR_PORF': '$1', # Power-on reset flag
+ 'OSCCAL' : '$66', # Oscillator Calibration Value
+ 'CLKPR' : '$61', # Clock Prescale Register
+ 'CLKPR_CLKPCE': '$80', # Clock Prescaler Change Enable
+ 'CLKPR_CLKPS': '$f', # Clock Prescaler Select Bits
+ 'PRR' : '$64', # Power Reduction Register
+ 'PRR_PRLCD': '$10', # Power Reduction LCD
+ 'PRR_PRTIM1': '$8', # Power Reduction Timer/Counter1
+ 'PRR_PRSPI': '$4', # Power Reduction Serial Periphe
+ 'PRR_PRUSART0': '$2', # Power Reduction USART
+ 'PRR_PRADC': '$1', # Power Reduction ADC
+ 'SMCR' : '$53', # Sleep Mode Control Register
+ 'SMCR_SM': '$e', # Sleep Mode Select bits
+ 'SMCR_SE': '$1', # Sleep Enable
+ 'GPIOR2' : '$4b', # General Purpose IO Register 2
+ 'GPIOR1' : '$4a', # General Purpose IO Register 1
+ 'GPIOR0' : '$3e', # General Purpose IO Register 0
+
+# Module JTAG
+ 'OCDR' : '$51', # On-Chip Debug Related Register
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_JTD': '$80', # JTAG Interface Disable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+
+# Module EXTERNAL_INTERRUPT
+ 'EICRA' : '$69', # External Interrupt Control Reg
+ 'EICRA_ISC01': '$2', # External Interrupt Sense Contr
+ 'EICRA_ISC00': '$1', # External Interrupt Sense Contr
+ 'EIMSK' : '$3d', # External Interrupt Mask Regist
+ 'EIMSK_PCIE': '$f0', # Pin Change Interrupt Enables
+ 'EIMSK_INT0': '$1', # External Interrupt Request 0 E
+ 'EIFR' : '$3c', # External Interrupt Flag Regist
+ 'EIFR_PCIF': '$f0', # Pin Change Interrupt Flags
+ 'EIFR_INTF0': '$1', # External Interrupt Flag 0
+ 'PCMSK1' : '$6c', # Pin Change Mask Register 1
+ 'PCMSK0' : '$6b', # Pin Change Mask Register 0
+
+# Module EEPROM
+ 'EEAR' : '$41', # EEPROM Read/Write Access Byte
+ 'EEDR' : '$40', # EEPROM Data Register
+ 'EECR' : '$3f', # EEPROM Control Register
+ 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
+ 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
+ 'EECR_EEWE': '$2', # EEPROM Write Enable
+ 'EECR_EERE': '$1', # EEPROM Read Enable
+
+# Module PORTA
+ 'PORTA' : '$22', # Port A Data Register
+ 'DDRA' : '$21', # Port A Data Direction Register
+ 'PINA' : '$20', # Port A Input Pins
+
+# Module PORTB
+ 'PORTB' : '$25', # Port B Data Register
+ 'DDRB' : '$24', # Port B Data Direction Register
+ 'PINB' : '$23', # Port B Input Pins
+
+# Module PORTC
+ 'PORTC' : '$28', # Port C Data Register
+ 'DDRC' : '$27', # Port C Data Direction Register
+ 'PINC' : '$26', # Port C Input Pins
+
+# Module PORTD
+ 'PORTD' : '$2b', # Port D Data Register
+ 'DDRD' : '$2a', # Port D Data Direction Register
+ 'PIND' : '$29', # Port D Input Pins
+
+# Module PORTE
+ 'PORTE' : '$2e', # Data Register, Port E
+ 'DDRE' : '$2d', # Data Direction Register, Port
+ 'PINE' : '$2c', # Input Pins, Port E
+
+# Module PORTF
+ 'PORTF' : '$31', # Data Register, Port F
+ 'DDRF' : '$30', # Data Direction Register, Port
+ 'PINF' : '$2f', # Input Pins, Port F
+
+# Module PORTG
+ 'PORTG' : '$34', # Port G Data Register
+ 'DDRG' : '$33', # Port G Data Direction Register
+ 'PING' : '$32', # Port G Input Pins
+
+# Module TIMER_COUNTER_0
+ 'TCCR0A' : '$44', # Timer/Counter0 Control Registe
+ 'TCCR0A_FOC0A': '$80', # Force Output Compare
+ 'TCCR0A_WGM00': '$40', # Waveform Generation Mode 0
+ 'TCCR0A_COM0A': '$30', # Compare Match Output Modes
+ 'TCCR0A_WGM01': '$8', # Waveform Generation Mode 1
+ 'TCCR0A_CS0': '$7', # Clock Selects
+ 'TCNT0' : '$46', # Timer/Counter0
+ 'OCR0A' : '$47', # Timer/Counter0 Output Compare
+ 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
+ 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
+ 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
+ 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
+ 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
+ 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Control Register
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSR310': '$1', # Prescaler Reset Timer/Counter1
+
+# Module TIMER_COUNTER_2
+ 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
+ 'TCCR2A_FOC2A': '$80', # Force Output Compare A
+ 'TCCR2A_WGM20': '$40', # Waveform Generation Mode
+ 'TCCR2A_COM2A': '$30', # Compare Output Mode bits
+ 'TCCR2A_WGM21': '$8', # Waveform Generation Mode
+ 'TCCR2A_CS2': '$7', # Clock Select bits
+ 'TCNT2' : '$b2', # Timer/Counter2
+ 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
+ 'TIMSK2' : '$70', # Timer/Counter2 Interrupt Mask
+ 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
+ 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
+ 'TIFR2' : '$37', # Timer/Counter2 Interrupt Flag
+ 'TIFR2_OCF2A': '$2', # Timer/Counter2 Output Compare
+ 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_PSR2': '$2', # Prescaler Reset Timer/Counter2
+ 'ASSR' : '$b6', # Asynchronous Status Register
+ 'ASSR_EXCLK': '$10', # Enable External Clock Interrup
+ 'ASSR_AS2': '$8', # AS2: Asynchronous Timer/Counte
+ 'ASSR_TCN2UB': '$4', # TCN2UB: Timer/Counter2 Update
+ 'ASSR_OCR2UB': '$2', # Output Compare Register2 Updat
+ 'ASSR_TCR2UB': '$1', # TCR2UB: Timer/Counter Control
+
+# Module TIMER_COUNTER_1
+ 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
+ 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
+ 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
+ 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
+ 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
+ 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
+ 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
+ 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
+ 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
+ 'TCCR1C' : '$82', # Timer/Counter 1 Control Regist
+ 'TCCR1C_FOC1A': '$80', # Force Output Compare 1A
+ 'TCCR1C_FOC1B': '$40', # Force Output Compare 1B
+ 'TCNT1' : '$84', # Timer/Counter1 Bytes
+ 'OCR1A' : '$88', # Timer/Counter1 Output Compare
+ 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
+ 'ICR1' : '$86', # Timer/Counter1 Input Capture R
+ 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
+ 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
+ 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
+ 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
+ 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
+ 'TIFR1' : '$36', # Timer/Counter1 Interrupt Flag
+ 'TIFR1_ICF1': '$20', # Input Capture Flag 1
+ 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
+ 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
+ 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
+
+# Module WATCHDOG
+ 'WDTCR' : '$60', # Watchdog Timer Control Registe
+ 'WDTCR_WDCE': '$10', # Watchdog Change Enable
+ 'WDTCR_WDE': '$8', # Watch Dog Enable
+ 'WDTCR_WDP': '$7', # Watch Dog Timer Prescaler bits
+
+# Module BOOT_LOAD
+ 'SPMCSR' : '$57', # Store Program Memory Control R
+ 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
+ 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
+ 'SPMCSR_RWWSRE': '$10', # Read While Write section read
+ 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
+ 'SPMCSR_PGWRT': '$4', # Page Write
+ 'SPMCSR_PGERS': '$2', # Page Erase
+ 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
+
+# Module USART0
+ 'UDR0' : '$c6', # USART I/O Data Register
+ 'UCSR0A' : '$c0', # USART Control and Status Regis
+ 'UCSR0A_RXC0': '$80', # USART Receive Complete
+ 'UCSR0A_TXC0': '$40', # USART Transmit Complete
+ 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
+ 'UCSR0A_FE0': '$10', # Framing Error
+ 'UCSR0A_DOR0': '$8', # Data OverRun
+ 'UCSR0A_UPE0': '$4', # USART Parity Error
+ 'UCSR0A_U2X0': '$2', # Double the USART Transmission
+ 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
+ 'UCSR0B' : '$c1', # USART Control and Status Regis
+ 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
+ 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
+ 'UCSR0B_UDRIE0': '$20', # USART Data Register Empty Inte
+ 'UCSR0B_RXEN0': '$10', # Receiver Enable
+ 'UCSR0B_TXEN0': '$8', # Transmitter Enable
+ 'UCSR0B_UCSZ02': '$4', # Character Size
+ 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
+ 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
+ 'UCSR0C' : '$c2', # USART Control and Status Regis
+ 'UCSR0C_UMSEL0': '$40', # USART Mode Select
+ 'UCSR0C_UPM0': '$30', # Parity Mode Bits
+ 'UCSR0C_USBS0': '$8', # Stop Bit Select
+ 'UCSR0C_UCSZ0': '$6', # Character Size
+ 'UCSR0C_UCPOL0': '$1', # Clock Polarity
+ 'UBRR0' : '$c4', # USART Baud Rate Register Byte
+
+ '__amforth_dummy':'0'
+}
diff --git a/amforth-6.5/avr8/devices/atmega645/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega645/words/no-jtag.asm
new file mode 100644
index 0000000..352a4bb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega645/words/no-jtag.asm
@@ -0,0 +1,14 @@
+; ( -- )
+; ( -- )
+; MCU
+; disable jtag at runtime
+VE_NOJTAG:
+ .dw $FF05
+ .db "-jtag",0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOJTAG
+XT_NOJTAG:
+ .dw PFA_NOJTAG
+PFA_NOJTAG:
+
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega645/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega645/words/no-wdt.asm
new file mode 100644
index 0000000..4a12261
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega645/words/no-wdt.asm
@@ -0,0 +1,22 @@
+; ( -- )
+; MCU
+; disable watch dog timer at runtime
+VE_NOWDT:
+ .dw $ff04
+ .db "-wdt"
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOWDT
+XT_NOWDT:
+ .dw PFA_NOWDT
+PFA_NOWDT:
+
+; Reset WDT
+ wdr
+; Write logical one to WDTOE and WDE
+ in_ temp1, WDTCR
+ ori temp1, (1<<WDTOE)|(1<<WDE)
+ out WDTCR, temp1
+; Turn off WDT
+ ldi temp1, (0<<WDE)
+ out_ WDTCR, temp1
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega645/words/sleep.asm b/amforth-6.5/avr8/devices/atmega645/words/sleep.asm
new file mode 100644
index 0000000..256249c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega645/words/sleep.asm
@@ -0,0 +1,19 @@
+; ( mode -- )
+; MCU
+; put the controller into the specified sleep mode
+VE_SLEEP:
+ .dw $ff05
+ .db "sleep", 0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_SLEEP
+XT_SLEEP:
+ .dw PFA_SLEEP
+PFA_SLEEP:
+ andi tosl, 7 ; leave only legal mode bits
+ lsl tosl ; move to correct location (bits 3-1)
+ ori tosl, 1 ; set the SE bit
+ out_ SMCR, tosl ; set the sleep config
+ sleep ; nighty-night
+ out_ SMCR, zerol ; 0 protects against accidental sleeps
+ loadtos ; pop argument from stack
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega6450/atmega6450.frt b/amforth-6.5/avr8/devices/atmega6450/atmega6450.frt
new file mode 100644
index 0000000..98e3bbb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega6450/atmega6450.frt
@@ -0,0 +1,298 @@
+\ Partname: ATmega6450
+\ generated automatically
+
+\ AD_CONVERTER
+&124 constant ADMUX \ The ADC multiplexer Selection Register
+ $C0 constant ADMUX_REFS \ Reference Selection Bits
+ $20 constant ADMUX_ADLAR \ Left Adjust Result
+ $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
+&122 constant ADCSRA \ The ADC Control and Status register
+ $80 constant ADCSRA_ADEN \ ADC Enable
+ $40 constant ADCSRA_ADSC \ ADC Start Conversion
+ $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
+ $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
+ $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
+ $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
+&120 constant ADC \ ADC Data Register Bytes
+&123 constant ADCSRB \ ADC Control and Status Register B
+ $07 constant ADCSRB_ADTS \ ADC Auto Trigger Sources
+&126 constant DIDR0 \ Digital Input Disable Register 0
+ $80 constant DIDR0_ADC7D \ ADC7 Digital input Disable
+ $40 constant DIDR0_ADC6D \ ADC6 Digital input Disable
+ $20 constant DIDR0_ADC5D \ ADC5 Digital input Disable
+ $10 constant DIDR0_ADC4D \ ADC4 Digital input Disable
+ $08 constant DIDR0_ADC3D \ ADC3 Digital input Disable
+ $04 constant DIDR0_ADC2D \ ADC2 Digital input Disable
+ $02 constant DIDR0_ADC1D \ ADC1 Digital input Disable
+ $01 constant DIDR0_ADC0D \ ADC0 Digital input Disable
+\ ANALOG_COMPARATOR
+&80 constant ACSR \ Analog Comparator Control And Status Register
+ $80 constant ACSR_ACD \ Analog Comparator Disable
+ $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
+ $20 constant ACSR_ACO \ Analog Compare Output
+ $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
+ $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
+ $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
+ $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
+&127 constant DIDR1 \ Digital Input Disable Register 1
+ $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
+ $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
+\ SPI
+&76 constant SPCR \ SPI Control Register
+ $80 constant SPCR_SPIE \ SPI Interrupt Enable
+ $40 constant SPCR_SPE \ SPI Enable
+ $20 constant SPCR_DORD \ Data Order
+ $10 constant SPCR_MSTR \ Master/Slave Select
+ $08 constant SPCR_CPOL \ Clock polarity
+ $04 constant SPCR_CPHA \ Clock Phase
+ $03 constant SPCR_SPR \ SPI Clock Rate Selects
+&77 constant SPSR \ SPI Status Register
+ $80 constant SPSR_SPIF \ SPI Interrupt Flag
+ $40 constant SPSR_WCOL \ Write Collision Flag
+ $01 constant SPSR_SPI2X \ Double SPI Speed Bit
+&78 constant SPDR \ SPI Data Register
+\ USI
+&186 constant USIDR \ USI Data Register
+&185 constant USISR \ USI Status Register
+ $80 constant USISR_USISIF \ Start Condition Interrupt Flag
+ $40 constant USISR_USIOIF \ Counter Overflow Interrupt Flag
+ $20 constant USISR_USIPF \ Stop Condition Flag
+ $10 constant USISR_USIDC \ Data Output Collision
+ $0F constant USISR_USICNT \ USI Counter Value Bits
+&184 constant USICR \ USI Control Register
+ $80 constant USICR_USISIE \ Start Condition Interrupt Enable
+ $40 constant USICR_USIOIE \ Counter Overflow Interrupt Enable
+ $30 constant USICR_USIWM \ USI Wire Mode Bits
+ $0C constant USICR_USICS \ USI Clock Source Select Bits
+ $02 constant USICR_USICLK \ Clock Strobe
+ $01 constant USICR_USITC \ Toggle Clock Port Pin
+\ USART0
+&198 constant UDR0 \ USART I/O Data Register
+&192 constant UCSR0A \ USART Control and Status Register A
+ $80 constant UCSR0A_RXC0 \ USART Receive Complete
+ $40 constant UCSR0A_TXC0 \ USART Transmit Complete
+ $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
+ $10 constant UCSR0A_FE0 \ Framing Error
+ $08 constant UCSR0A_DOR0 \ Data OverRun
+ $04 constant UCSR0A_UPE0 \ USART Parity Error
+ $02 constant UCSR0A_U2X0 \ Double the USART Transmission Speed
+ $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
+&193 constant UCSR0B \ USART Control and Status Register B
+ $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
+ $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
+ $20 constant UCSR0B_UDRIE0 \ USART Data Register Empty Interrupt Enable
+ $10 constant UCSR0B_RXEN0 \ Receiver Enable
+ $08 constant UCSR0B_TXEN0 \ Transmitter Enable
+ $04 constant UCSR0B_UCSZ02 \ Character Size
+ $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
+ $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
+&194 constant UCSR0C \ USART Control and Status Register C
+ $40 constant UCSR0C_UMSEL0 \ USART Mode Select
+ $30 constant UCSR0C_UPM0 \ Parity Mode Bits
+ $08 constant UCSR0C_USBS0 \ Stop Bit Select
+ $06 constant UCSR0C_UCSZ0 \ Character Size
+ $01 constant UCSR0C_UCPOL0 \ Clock Polarity
+&196 constant UBRR0 \ USART Baud Rate Register Bytes
+\ CPU
+&95 constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ $08 constant SREG_V \ Two's Complement Overflow Flag
+ $04 constant SREG_N \ Negative Flag
+ $02 constant SREG_Z \ Zero Flag
+ $01 constant SREG_C \ Carry Flag
+&93 constant SP \ Stack Pointer
+&85 constant MCUCR \ MCU Control Register
+ $10 constant MCUCR_PUD \ Pull-up disable
+ $02 constant MCUCR_IVSEL \ Interrupt Vector Select
+ $01 constant MCUCR_IVCE \ Interrupt Vector Change Enable
+&84 constant MCUSR \ MCU Status Register
+ $10 constant MCUSR_JTRF \ JTAG Reset Flag
+ $08 constant MCUSR_WDRF \ Watchdog Reset Flag
+ $04 constant MCUSR_BORF \ Brown-out Reset Flag
+ $02 constant MCUSR_EXTRF \ External Reset Flag
+ $01 constant MCUSR_PORF \ Power-on reset flag
+&102 constant OSCCAL \ Oscillator Calibration Value
+&97 constant CLKPR \ Clock Prescale Register
+ $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable
+ $0F constant CLKPR_CLKPS \ Clock Prescaler Select Bits
+&100 constant PRR \ Power Reduction Register
+ $10 constant PRR_PRLCD \ Power Reduction LCD
+ $08 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
+ $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
+ $02 constant PRR_PRUSART0 \ Power Reduction USART
+ $01 constant PRR_PRADC \ Power Reduction ADC
+&83 constant SMCR \ Sleep Mode Control Register
+ $0E constant SMCR_SM \ Sleep Mode Select bits
+ $01 constant SMCR_SE \ Sleep Enable
+&75 constant GPIOR2 \ General Purpose IO Register 2
+&74 constant GPIOR1 \ General Purpose IO Register 1
+&62 constant GPIOR0 \ General Purpose IO Register 0
+\ JTAG
+&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
+\ EEPROM
+&65 constant EEAR \ EEPROM Read/Write Access Bytes
+&64 constant EEDR \ EEPROM Data Register
+&63 constant EECR \ EEPROM Control Register
+ $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
+ $04 constant EECR_EEMWE \ EEPROM Master Write Enable
+ $02 constant EECR_EEWE \ EEPROM Write Enable
+ $01 constant EECR_EERE \ EEPROM Read Enable
+\ PORTA
+&34 constant PORTA \ Port A Data Register
+&33 constant DDRA \ Port A Data Direction Register
+&32 constant PINA \ Port A Input Pins
+\ PORTB
+&37 constant PORTB \ Port B Data Register
+&36 constant DDRB \ Port B Data Direction Register
+&35 constant PINB \ Port B Input Pins
+\ PORTC
+&40 constant PORTC \ Port C Data Register
+&39 constant DDRC \ Port C Data Direction Register
+&38 constant PINC \ Port C Input Pins
+\ PORTD
+&43 constant PORTD \ Port D Data Register
+&42 constant DDRD \ Port D Data Direction Register
+&41 constant PIND \ Port D Input Pins
+\ PORTE
+&46 constant PORTE \ Data Register, Port E
+&45 constant DDRE \ Data Direction Register, Port E
+&44 constant PINE \ Input Pins, Port E
+\ PORTF
+&49 constant PORTF \ Data Register, Port F
+&48 constant DDRF \ Data Direction Register, Port F
+&47 constant PINF \ Input Pins, Port F
+\ PORTG
+&52 constant PORTG \ Port G Data Register
+&51 constant DDRG \ Port G Data Direction Register
+&50 constant PING \ Port G Input Pins
+\ TIMER_COUNTER_0
+&68 constant TCCR0A \ Timer/Counter0 Control Register
+ $80 constant TCCR0A_FOC0A \ Force Output Compare
+ $40 constant TCCR0A_WGM00 \ Waveform Generation Mode 0
+ $30 constant TCCR0A_COM0A \ Compare Match Output Modes
+ $08 constant TCCR0A_WGM01 \ Waveform Generation Mode 1
+ $07 constant TCCR0A_CS0 \ Clock Selects
+&70 constant TCNT0 \ Timer/Counter0
+&71 constant OCR0A \ Timer/Counter0 Output Compare Register
+&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
+ $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match Interrupt Enable
+ $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
+&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
+ $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0
+ $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
+&67 constant GTCCR \ General Timer/Control Register
+ $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
+ $01 constant GTCCR_PSR310 \ Prescaler Reset Timer/Counter1 and Timer/Counter0
+\ TIMER_COUNTER_2
+&176 constant TCCR2A \ Timer/Counter2 Control Register
+ $80 constant TCCR2A_FOC2A \ Force Output Compare A
+ $40 constant TCCR2A_WGM20 \ Waveform Generation Mode
+ $30 constant TCCR2A_COM2A \ Compare Output Mode bits
+ $08 constant TCCR2A_WGM21 \ Waveform Generation Mode
+ $07 constant TCCR2A_CS2 \ Clock Select bits
+&178 constant TCNT2 \ Timer/Counter2
+&179 constant OCR2A \ Timer/Counter2 Output Compare Register
+&112 constant TIMSK2 \ Timer/Counter2 Interrupt Mask register
+ $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match Interrupt Enable
+ $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
+&55 constant TIFR2 \ Timer/Counter2 Interrupt Flag Register
+ $02 constant TIFR2_OCF2A \ Timer/Counter2 Output Compare Flag 2
+ $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
+&182 constant ASSR \ Asynchronous Status Register
+ $10 constant ASSR_EXCLK \ Enable External Clock Interrupt
+ $08 constant ASSR_AS2 \ AS2: Asynchronous Timer/Counter2
+ $04 constant ASSR_TCN2UB \ TCN2UB: Timer/Counter2 Update Busy
+ $02 constant ASSR_OCR2UB \ Output Compare Register2 Update Busy
+ $01 constant ASSR_TCR2UB \ TCR2UB: Timer/Counter Control Register2 Update Busy
+\ TIMER_COUNTER_1
+&128 constant TCCR1A \ Timer/Counter1 Control Register A
+ $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
+ $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
+ $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
+&129 constant TCCR1B \ Timer/Counter1 Control Register B
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
+ $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
+&130 constant TCCR1C \ Timer/Counter 1 Control Register C
+ $80 constant TCCR1C_FOC1A \ Force Output Compare 1A
+ $40 constant TCCR1C_FOC1B \ Force Output Compare 1B
+&132 constant TCNT1 \ Timer/Counter1 Bytes
+&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
+&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
+&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
+&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
+ $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
+ $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
+ $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
+ $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
+&54 constant TIFR1 \ Timer/Counter1 Interrupt Flag register
+ $20 constant TIFR1_ICF1 \ Input Capture Flag 1
+ $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
+ $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
+ $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
+\ WATCHDOG
+&96 constant WDTCR \ Watchdog Timer Control Register
+ $10 constant WDTCR_WDCE \ Watchdog Change Enable
+ $08 constant WDTCR_WDE \ Watch Dog Enable
+ $07 constant WDTCR_WDP \ Watch Dog Timer Prescaler bits
+\ BOOT_LOAD
+&87 constant SPMCSR \ Store Program Memory Control Register
+ $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
+ $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
+ $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
+ $04 constant SPMCSR_PGWRT \ Page Write
+ $02 constant SPMCSR_PGERS \ Page Erase
+ $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
+\ PORTH
+&218 constant PORTH \ PORT H Data Register
+&217 constant DDRH \ PORT H Data Direction Register
+&216 constant PINH \ PORT H Input Pins
+\ PORTJ
+&221 constant PORTJ \ PORT J Data Register
+&220 constant DDRJ \ PORT J Data Direction Register
+&219 constant PINJ \ PORT J Input Pins
+\ EXTERNAL_INTERRUPT
+&105 constant EICRA \ External Interrupt Control Register A
+ $02 constant EICRA_ISC01 \ External Interrupt Sense Control 0 Bit 1
+ $01 constant EICRA_ISC00 \ External Interrupt Sense Control 0 Bit 0
+&61 constant EIMSK \ External Interrupt Mask Register
+ $F0 constant EIMSK_PCIE \ Pin Change Interrupt Enables
+ $01 constant EIMSK_INT0 \ External Interrupt Request 0 Enable
+&60 constant EIFR \ External Interrupt Flag Register
+ $F0 constant EIFR_PCIF \ Pin Change Interrupt Flags
+ $01 constant EIFR_INTF0 \ External Interrupt Flag 0
+&115 constant PCMSK3 \ Pin Change Mask Register 3
+&109 constant PCMSK2 \ Pin Change Mask Register 2
+&108 constant PCMSK1 \ Pin Change Mask Register 1
+&107 constant PCMSK0 \ Pin Change Mask Register 0
+
+\ Interrupts
+&2 constant INT0Addr \ External Interrupt Request 0
+&4 constant PCINT0Addr \ Pin Change Interrupt Request 0
+&6 constant PCINT1Addr \ Pin Change Interrupt Request 1
+&8 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
+&10 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
+&12 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+&14 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
+&16 constant TIMER1_COMPBAddr \ Timer/Counter Compare Match B
+&18 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+&20 constant TIMER0_COMPAddr \ Timer/Counter0 Compare Match
+&22 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
+&24 constant SPI__STCAddr \ SPI Serial Transfer Complete
+&26 constant USART__RXAddr \ USART, Rx Complete
+&28 constant USART__UDREAddr \ USART Data register Empty
+&30 constant USART0__TXAddr \ USART0, Tx Complete
+&32 constant USI_STARTAddr \ USI Start Condition
+&34 constant USI_OVERFLOWAddr \ USI Overflow
+&36 constant ANALOG_COMPAddr \ Analog Comparator
+&38 constant ADCAddr \ ADC Conversion Complete
+&40 constant EE_READYAddr \ EEPROM Ready
+&42 constant SPM_READYAddr \ Store Program Memory Read
+&44 constant NOT_USEDAddr \ RESERVED
+&46 constant PCINT2Addr \ Pin Change Interrupt Request 2
+&48 constant PCINT3Addr \ Pin Change Interrupt Request 3
diff --git a/amforth-6.5/avr8/devices/atmega6450/device.asm b/amforth-6.5/avr8/devices/atmega6450/device.asm
new file mode 100644
index 0000000..39d52bd
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega6450/device.asm
@@ -0,0 +1,114 @@
+; Partname: ATmega6450
+; generated automatically, do not edit
+
+.nolist
+ .include "m6450def.inc"
+.list
+
+.equ ramstart = 256
+.equ CELLSIZE = 2
+.macro readflashcell
+ lsl zl
+ rol zh
+ lpm @0, Z+
+ lpm @1, Z+
+.endmacro
+.macro writeflashcell
+ lsl zl
+ rol zh
+.endmacro
+.set WANT_AD_CONVERTER = 0
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_SPI = 0
+.set WANT_USI = 0
+.set WANT_USART0 = 0
+.set WANT_CPU = 0
+.set WANT_JTAG = 0
+.set WANT_EEPROM = 0
+.set WANT_PORTA = 0
+.set WANT_PORTB = 0
+.set WANT_PORTC = 0
+.set WANT_PORTD = 0
+.set WANT_PORTE = 0
+.set WANT_PORTF = 0
+.set WANT_PORTG = 0
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_TIMER_COUNTER_2 = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_WATCHDOG = 0
+.set WANT_BOOT_LOAD = 0
+.set WANT_PORTH = 0
+.set WANT_PORTJ = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.equ intvecsize = 2 ; please verify; flash size: 65536 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.org 2
+ rcall isr ; External Interrupt Request 0
+.org 4
+ rcall isr ; Pin Change Interrupt Request 0
+.org 6
+ rcall isr ; Pin Change Interrupt Request 1
+.org 8
+ rcall isr ; Timer/Counter2 Compare Match
+.org 10
+ rcall isr ; Timer/Counter2 Overflow
+.org 12
+ rcall isr ; Timer/Counter1 Capture Event
+.org 14
+ rcall isr ; Timer/Counter1 Compare Match A
+.org 16
+ rcall isr ; Timer/Counter Compare Match B
+.org 18
+ rcall isr ; Timer/Counter1 Overflow
+.org 20
+ rcall isr ; Timer/Counter0 Compare Match
+.org 22
+ rcall isr ; Timer/Counter0 Overflow
+.org 24
+ rcall isr ; SPI Serial Transfer Complete
+.org 26
+ rcall isr ; USART, Rx Complete
+.org 28
+ rcall isr ; USART Data register Empty
+.org 30
+ rcall isr ; USART0, Tx Complete
+.org 32
+ rcall isr ; USI Start Condition
+.org 34
+ rcall isr ; USI Overflow
+.org 36
+ rcall isr ; Analog Comparator
+.org 38
+ rcall isr ; ADC Conversion Complete
+.org 40
+ rcall isr ; EEPROM Ready
+.org 42
+ rcall isr ; Store Program Memory Read
+.org 44
+ rcall isr ; RESERVED
+.org 46
+ rcall isr ; Pin Change Interrupt Request 2
+.org 48
+ rcall isr ; Pin Change Interrupt Request 3
+.equ INTVECTORS = 25
+.nooverlap
+
+; compatability layer (maybe empty)
+.equ EEPE = EEWE
+.equ EEMPE = EEMWE
+
+; controller data area, environment query mcu-info
+mcu_info:
+mcu_ramsize:
+ .dw 4096
+mcu_eepromsize:
+ .dw 2048
+mcu_maxdp:
+ .dw 57344
+mcu_numints:
+ .dw 25
+mcu_name:
+ .dw 10
+ .db "ATmega6450"
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega6450/device.inc b/amforth-6.5/avr8/devices/atmega6450/device.inc
new file mode 100644
index 0000000..8b44ba6
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega6450/device.inc
@@ -0,0 +1,1152 @@
+; Partname: ATmega6450
+; generated automatically, no not edit
+
+.if WANT_AD_CONVERTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC multiplexer Selection Register
+VE_ADMUX:
+ .dw $ff05
+ .db "ADMUX",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADMUX
+XT_ADMUX:
+ .dw PFA_DOVARIABLE
+PFA_ADMUX:
+ .dw 124
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register
+VE_ADCSRA:
+ .dw $ff06
+ .db "ADCSRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRA
+XT_ADCSRA:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRA:
+ .dw 122
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register Bytes
+VE_ADC:
+ .dw $ff03
+ .db "ADC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADC
+XT_ADC:
+ .dw PFA_DOVARIABLE
+PFA_ADC:
+ .dw 120
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Control and Status Register B
+VE_ADCSRB:
+ .dw $ff06
+ .db "ADCSRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRB
+XT_ADCSRB:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRB:
+ .dw 123
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 0
+VE_DIDR0:
+ .dw $ff05
+ .db "DIDR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR0
+XT_DIDR0:
+ .dw PFA_DOVARIABLE
+PFA_DIDR0:
+ .dw 126
+
+.endif
+.if WANT_ANALOG_COMPARATOR == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Control And Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw 80
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 1
+VE_DIDR1:
+ .dw $ff05
+ .db "DIDR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR1
+XT_DIDR1:
+ .dw PFA_DOVARIABLE
+PFA_DIDR1:
+ .dw 127
+
+.endif
+.if WANT_SPI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR:
+ .dw $ff04
+ .db "SPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR
+XT_SPCR:
+ .dw PFA_DOVARIABLE
+PFA_SPCR:
+ .dw 76
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR:
+ .dw $ff04
+ .db "SPSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR
+XT_SPSR:
+ .dw PFA_DOVARIABLE
+PFA_SPSR:
+ .dw 77
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR:
+ .dw $ff04
+ .db "SPDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR
+XT_SPDR:
+ .dw PFA_DOVARIABLE
+PFA_SPDR:
+ .dw 78
+
+.endif
+.if WANT_USI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USI Data Register
+VE_USIDR:
+ .dw $ff05
+ .db "USIDR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USIDR
+XT_USIDR:
+ .dw PFA_DOVARIABLE
+PFA_USIDR:
+ .dw 186
+; ( -- addr ) System Constant
+; R( -- )
+; USI Status Register
+VE_USISR:
+ .dw $ff05
+ .db "USISR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USISR
+XT_USISR:
+ .dw PFA_DOVARIABLE
+PFA_USISR:
+ .dw 185
+; ( -- addr ) System Constant
+; R( -- )
+; USI Control Register
+VE_USICR:
+ .dw $ff05
+ .db "USICR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USICR
+XT_USICR:
+ .dw PFA_DOVARIABLE
+PFA_USICR:
+ .dw 184
+
+.endif
+.if WANT_USART0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR0:
+ .dw $ff04
+ .db "UDR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR0
+XT_UDR0:
+ .dw PFA_DOVARIABLE
+PFA_UDR0:
+ .dw 198
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR0A:
+ .dw $ff06
+ .db "UCSR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0A
+XT_UCSR0A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0A:
+ .dw 192
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR0B:
+ .dw $ff06
+ .db "UCSR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0B
+XT_UCSR0B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0B:
+ .dw 193
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR0C:
+ .dw $ff06
+ .db "UCSR0C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0C
+XT_UCSR0C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0C:
+ .dw 194
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Bytes
+VE_UBRR0:
+ .dw $ff05
+ .db "UBRR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR0
+XT_UBRR0:
+ .dw PFA_DOVARIABLE
+PFA_UBRR0:
+ .dw 196
+
+.endif
+.if WANT_CPU == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw 95
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer
+VE_SP:
+ .dw $ff02
+ .db "SP"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SP
+XT_SP:
+ .dw PFA_DOVARIABLE
+PFA_SP:
+ .dw 93
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw 85
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Status Register
+VE_MCUSR:
+ .dw $ff05
+ .db "MCUSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUSR
+XT_MCUSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUSR:
+ .dw 84
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Calibration Value
+VE_OSCCAL:
+ .dw $ff06
+ .db "OSCCAL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSCCAL
+XT_OSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_OSCCAL:
+ .dw 102
+; ( -- addr ) System Constant
+; R( -- )
+; Clock Prescale Register
+VE_CLKPR:
+ .dw $ff05
+ .db "CLKPR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKPR
+XT_CLKPR:
+ .dw PFA_DOVARIABLE
+PFA_CLKPR:
+ .dw 97
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register
+VE_PRR:
+ .dw $ff03
+ .db "PRR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR
+XT_PRR:
+ .dw PFA_DOVARIABLE
+PFA_PRR:
+ .dw 100
+; ( -- addr ) System Constant
+; R( -- )
+; Sleep Mode Control Register
+VE_SMCR:
+ .dw $ff04
+ .db "SMCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SMCR
+XT_SMCR:
+ .dw PFA_DOVARIABLE
+PFA_SMCR:
+ .dw 83
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 2
+VE_GPIOR2:
+ .dw $ff06
+ .db "GPIOR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR2
+XT_GPIOR2:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR2:
+ .dw 75
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 1
+VE_GPIOR1:
+ .dw $ff06
+ .db "GPIOR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR1
+XT_GPIOR1:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR1:
+ .dw 74
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 0
+VE_GPIOR0:
+ .dw $ff06
+ .db "GPIOR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR0
+XT_GPIOR0:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR0:
+ .dw 62
+
+.endif
+.if WANT_JTAG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; On-Chip Debug Related Register in I/O Memory
+VE_OCDR:
+ .dw $ff04
+ .db "OCDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCDR
+XT_OCDR:
+ .dw PFA_DOVARIABLE
+PFA_OCDR:
+ .dw 81
+
+.endif
+.if WANT_EEPROM == 1
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Read/Write Access Bytes
+VE_EEAR:
+ .dw $ff04
+ .db "EEAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEAR
+XT_EEAR:
+ .dw PFA_DOVARIABLE
+PFA_EEAR:
+ .dw 65
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw 64
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw 63
+
+.endif
+.if WANT_PORTA == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Register
+VE_PORTA:
+ .dw $ff05
+ .db "PORTA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTA
+XT_PORTA:
+ .dw PFA_DOVARIABLE
+PFA_PORTA:
+ .dw 34
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Direction Register
+VE_DDRA:
+ .dw $ff04
+ .db "DDRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRA
+XT_DDRA:
+ .dw PFA_DOVARIABLE
+PFA_DDRA:
+ .dw 33
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Input Pins
+VE_PINA:
+ .dw $ff04
+ .db "PINA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINA
+XT_PINA:
+ .dw PFA_DOVARIABLE
+PFA_PINA:
+ .dw 32
+
+.endif
+.if WANT_PORTB == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw 37
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw 36
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw 35
+
+.endif
+.if WANT_PORTC == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Register
+VE_PORTC:
+ .dw $ff05
+ .db "PORTC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTC
+XT_PORTC:
+ .dw PFA_DOVARIABLE
+PFA_PORTC:
+ .dw 40
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Direction Register
+VE_DDRC:
+ .dw $ff04
+ .db "DDRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRC
+XT_DDRC:
+ .dw PFA_DOVARIABLE
+PFA_DDRC:
+ .dw 39
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Input Pins
+VE_PINC:
+ .dw $ff04
+ .db "PINC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINC
+XT_PINC:
+ .dw PFA_DOVARIABLE
+PFA_PINC:
+ .dw 38
+
+.endif
+.if WANT_PORTD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw 43
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw 42
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw 41
+
+.endif
+.if WANT_PORTE == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port E
+VE_PORTE:
+ .dw $ff05
+ .db "PORTE",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTE
+XT_PORTE:
+ .dw PFA_DOVARIABLE
+PFA_PORTE:
+ .dw 46
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port E
+VE_DDRE:
+ .dw $ff04
+ .db "DDRE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRE
+XT_DDRE:
+ .dw PFA_DOVARIABLE
+PFA_DDRE:
+ .dw 45
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port E
+VE_PINE:
+ .dw $ff04
+ .db "PINE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINE
+XT_PINE:
+ .dw PFA_DOVARIABLE
+PFA_PINE:
+ .dw 44
+
+.endif
+.if WANT_PORTF == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port F
+VE_PORTF:
+ .dw $ff05
+ .db "PORTF",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTF
+XT_PORTF:
+ .dw PFA_DOVARIABLE
+PFA_PORTF:
+ .dw 49
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port F
+VE_DDRF:
+ .dw $ff04
+ .db "DDRF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRF
+XT_DDRF:
+ .dw PFA_DOVARIABLE
+PFA_DDRF:
+ .dw 48
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port F
+VE_PINF:
+ .dw $ff04
+ .db "PINF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINF
+XT_PINF:
+ .dw PFA_DOVARIABLE
+PFA_PINF:
+ .dw 47
+
+.endif
+.if WANT_PORTG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Data Register
+VE_PORTG:
+ .dw $ff05
+ .db "PORTG",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTG
+XT_PORTG:
+ .dw PFA_DOVARIABLE
+PFA_PORTG:
+ .dw 52
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Data Direction Register
+VE_DDRG:
+ .dw $ff04
+ .db "DDRG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRG
+XT_DDRG:
+ .dw PFA_DOVARIABLE
+PFA_DDRG:
+ .dw 51
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Input Pins
+VE_PING:
+ .dw $ff04
+ .db "PING"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PING
+XT_PING:
+ .dw PFA_DOVARIABLE
+PFA_PING:
+ .dw 50
+
+.endif
+.if WANT_TIMER_COUNTER_0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Control Register
+VE_TCCR0A:
+ .dw $ff06
+ .db "TCCR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0A
+XT_TCCR0A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0A:
+ .dw 68
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw 70
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0A:
+ .dw $ff05
+ .db "OCR0A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0A
+XT_OCR0A:
+ .dw PFA_DOVARIABLE
+PFA_OCR0A:
+ .dw 71
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Mask Register
+VE_TIMSK0:
+ .dw $ff06
+ .db "TIMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK0
+XT_TIMSK0:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK0:
+ .dw 110
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Flag register
+VE_TIFR0:
+ .dw $ff05
+ .db "TIFR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR0
+XT_TIFR0:
+ .dw PFA_DOVARIABLE
+PFA_TIFR0:
+ .dw 53
+; ( -- addr ) System Constant
+; R( -- )
+; General Timer/Control Register
+VE_GTCCR:
+ .dw $ff05
+ .db "GTCCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GTCCR
+XT_GTCCR:
+ .dw PFA_DOVARIABLE
+PFA_GTCCR:
+ .dw 67
+
+.endif
+.if WANT_TIMER_COUNTER_2 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register
+VE_TCCR2A:
+ .dw $ff06
+ .db "TCCR2A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2A
+XT_TCCR2A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2A:
+ .dw 176
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2
+VE_TCNT2:
+ .dw $ff05
+ .db "TCNT2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT2
+XT_TCNT2:
+ .dw PFA_DOVARIABLE
+PFA_TCNT2:
+ .dw 178
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register
+VE_OCR2A:
+ .dw $ff05
+ .db "OCR2A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2A
+XT_OCR2A:
+ .dw PFA_DOVARIABLE
+PFA_OCR2A:
+ .dw 179
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Interrupt Mask register
+VE_TIMSK2:
+ .dw $ff06
+ .db "TIMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK2
+XT_TIMSK2:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK2:
+ .dw 112
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Interrupt Flag Register
+VE_TIFR2:
+ .dw $ff05
+ .db "TIFR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR2
+XT_TIFR2:
+ .dw PFA_DOVARIABLE
+PFA_TIFR2:
+ .dw 55
+; ( -- addr ) System Constant
+; R( -- )
+; Asynchronous Status Register
+VE_ASSR:
+ .dw $ff04
+ .db "ASSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ASSR
+XT_ASSR:
+ .dw PFA_DOVARIABLE
+PFA_ASSR:
+ .dw 182
+
+.endif
+.if WANT_TIMER_COUNTER_1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw 128
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw 129
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter 1 Control Register C
+VE_TCCR1C:
+ .dw $ff06
+ .db "TCCR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1C
+XT_TCCR1C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1C:
+ .dw 130
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Bytes
+VE_TCNT1:
+ .dw $ff05
+ .db "TCNT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1
+XT_TCNT1:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1:
+ .dw 132
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register A Bytes
+VE_OCR1A:
+ .dw $ff05
+ .db "OCR1A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1A
+XT_OCR1A:
+ .dw PFA_DOVARIABLE
+PFA_OCR1A:
+ .dw 136
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register B Bytes
+VE_OCR1B:
+ .dw $ff05
+ .db "OCR1B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1B
+XT_OCR1B:
+ .dw PFA_DOVARIABLE
+PFA_OCR1B:
+ .dw 138
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Bytes
+VE_ICR1:
+ .dw $ff04
+ .db "ICR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1
+XT_ICR1:
+ .dw PFA_DOVARIABLE
+PFA_ICR1:
+ .dw 134
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Mask Register
+VE_TIMSK1:
+ .dw $ff06
+ .db "TIMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK1
+XT_TIMSK1:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK1:
+ .dw 111
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Flag register
+VE_TIFR1:
+ .dw $ff05
+ .db "TIFR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR1
+XT_TIFR1:
+ .dw PFA_DOVARIABLE
+PFA_TIFR1:
+ .dw 54
+
+.endif
+.if WANT_WATCHDOG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCR:
+ .dw $ff05
+ .db "WDTCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCR
+XT_WDTCR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCR:
+ .dw 96
+
+.endif
+.if WANT_BOOT_LOAD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control Register
+VE_SPMCSR:
+ .dw $ff06
+ .db "SPMCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCSR
+XT_SPMCSR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCSR:
+ .dw 87
+
+.endif
+.if WANT_PORTH == 1
+; ( -- addr ) System Constant
+; R( -- )
+; PORT H Data Register
+VE_PORTH:
+ .dw $ff05
+ .db "PORTH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTH
+XT_PORTH:
+ .dw PFA_DOVARIABLE
+PFA_PORTH:
+ .dw 218
+; ( -- addr ) System Constant
+; R( -- )
+; PORT H Data Direction Register
+VE_DDRH:
+ .dw $ff04
+ .db "DDRH"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRH
+XT_DDRH:
+ .dw PFA_DOVARIABLE
+PFA_DDRH:
+ .dw 217
+; ( -- addr ) System Constant
+; R( -- )
+; PORT H Input Pins
+VE_PINH:
+ .dw $ff04
+ .db "PINH"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINH
+XT_PINH:
+ .dw PFA_DOVARIABLE
+PFA_PINH:
+ .dw 216
+
+.endif
+.if WANT_PORTJ == 1
+; ( -- addr ) System Constant
+; R( -- )
+; PORT J Data Register
+VE_PORTJ:
+ .dw $ff05
+ .db "PORTJ",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTJ
+XT_PORTJ:
+ .dw PFA_DOVARIABLE
+PFA_PORTJ:
+ .dw 221
+; ( -- addr ) System Constant
+; R( -- )
+; PORT J Data Direction Register
+VE_DDRJ:
+ .dw $ff04
+ .db "DDRJ"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRJ
+XT_DDRJ:
+ .dw PFA_DOVARIABLE
+PFA_DDRJ:
+ .dw 220
+; ( -- addr ) System Constant
+; R( -- )
+; PORT J Input Pins
+VE_PINJ:
+ .dw $ff04
+ .db "PINJ"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINJ
+XT_PINJ:
+ .dw PFA_DOVARIABLE
+PFA_PINJ:
+ .dw 219
+
+.endif
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register A
+VE_EICRA:
+ .dw $ff05
+ .db "EICRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRA
+XT_EICRA:
+ .dw PFA_DOVARIABLE
+PFA_EICRA:
+ .dw 105
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Mask Register
+VE_EIMSK:
+ .dw $ff05
+ .db "EIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIMSK
+XT_EIMSK:
+ .dw PFA_DOVARIABLE
+PFA_EIMSK:
+ .dw 61
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Flag Register
+VE_EIFR:
+ .dw $ff04
+ .db "EIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIFR
+XT_EIFR:
+ .dw PFA_DOVARIABLE
+PFA_EIFR:
+ .dw 60
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 3
+VE_PCMSK3:
+ .dw $ff06
+ .db "PCMSK3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK3
+XT_PCMSK3:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK3:
+ .dw 115
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 2
+VE_PCMSK2:
+ .dw $ff06
+ .db "PCMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK2
+XT_PCMSK2:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK2:
+ .dw 109
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 1
+VE_PCMSK1:
+ .dw $ff06
+ .db "PCMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK1
+XT_PCMSK1:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK1:
+ .dw 108
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 0
+VE_PCMSK0:
+ .dw $ff06
+ .db "PCMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK0
+XT_PCMSK0:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK0:
+ .dw 107
+
+.endif
diff --git a/amforth-6.5/avr8/devices/atmega6450/device.py b/amforth-6.5/avr8/devices/atmega6450/device.py
new file mode 100644
index 0000000..b1ca149
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega6450/device.py
@@ -0,0 +1,333 @@
+# Generated Automatically
+
+# Partname ATmega6450
+
+MCUREGS = {
+# Interrupt Vectors
+ 'INT0Addr' : '#2', # External Interrupt Request 0
+ 'PCINT0Addr' : '#4', # Pin Change Interrupt Request 0
+ 'PCINT1Addr' : '#6', # Pin Change Interrupt Request 1
+ 'TIMER2_COMPAddr' : '#8', # Timer/Counter2 Compare Match
+ 'TIMER2_OVFAddr' : '#10', # Timer/Counter2 Overflow
+ 'TIMER1_CAPTAddr' : '#12', # Timer/Counter1 Capture Event
+ 'TIMER1_COMPAAddr' : '#14', # Timer/Counter1 Compare Match A
+ 'TIMER1_COMPBAddr' : '#16', # Timer/Counter Compare Match B
+ 'TIMER1_OVFAddr' : '#18', # Timer/Counter1 Overflow
+ 'TIMER0_COMPAddr' : '#20', # Timer/Counter0 Compare Match
+ 'TIMER0_OVFAddr' : '#22', # Timer/Counter0 Overflow
+ 'SPI_STCAddr' : '#24', # SPI Serial Transfer Complete
+ 'USART_RXAddr' : '#26', # USART, Rx Complete
+ 'USART_UDREAddr' : '#28', # USART Data register Empty
+ 'USART0_TXAddr' : '#30', # USART0, Tx Complete
+ 'USI_STARTAddr' : '#32', # USI Start Condition
+ 'USI_OVERFLOWAddr' : '#34', # USI Overflow
+ 'ANALOG_COMPAddr' : '#36', # Analog Comparator
+ 'ADCAddr' : '#38', # ADC Conversion Complete
+ 'EE_READYAddr' : '#40', # EEPROM Ready
+ 'SPM_READYAddr' : '#42', # Store Program Memory Read
+ 'NOT_USEDAddr' : '#44', # RESERVED
+ 'PCINT2Addr' : '#46', # Pin Change Interrupt Request 2
+ 'PCINT3Addr' : '#48', # Pin Change Interrupt Request 3
+
+# Module AD_CONVERTER
+ 'ADMUX' : '$7c', # The ADC multiplexer Selection
+ 'ADMUX_REFS': '$c0', # Reference Selection Bits
+ 'ADMUX_ADLAR': '$20', # Left Adjust Result
+ 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
+ 'ADCSRA' : '$7a', # The ADC Control and Status reg
+ 'ADCSRA_ADEN': '$80', # ADC Enable
+ 'ADCSRA_ADSC': '$40', # ADC Start Conversion
+ 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
+ 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
+ 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
+ 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
+ 'ADC' : '$78', # ADC Data Register Bytes
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Sources
+ 'DIDR0' : '$7e', # Digital Input Disable Register
+ 'DIDR0_ADC7D': '$80', # ADC7 Digital input Disable
+ 'DIDR0_ADC6D': '$40', # ADC6 Digital input Disable
+ 'DIDR0_ADC5D': '$20', # ADC5 Digital input Disable
+ 'DIDR0_ADC4D': '$10', # ADC4 Digital input Disable
+ 'DIDR0_ADC3D': '$8', # ADC3 Digital input Disable
+ 'DIDR0_ADC2D': '$4', # ADC2 Digital input Disable
+ 'DIDR0_ADC1D': '$2', # ADC1 Digital input Disable
+ 'DIDR0_ADC0D': '$1', # ADC0 Digital input Disable
+
+# Module ANALOG_COMPARATOR
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
+ 'ACSR' : '$50', # Analog Comparator Control And
+ 'ACSR_ACD': '$80', # Analog Comparator Disable
+ 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
+ 'ACSR_ACO': '$20', # Analog Compare Output
+ 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
+ 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
+ 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
+ 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
+ 'DIDR1' : '$7f', # Digital Input Disable Register
+ 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
+ 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
+
+# Module SPI
+ 'SPCR' : '$4c', # SPI Control Register
+ 'SPCR_SPIE': '$80', # SPI Interrupt Enable
+ 'SPCR_SPE': '$40', # SPI Enable
+ 'SPCR_DORD': '$20', # Data Order
+ 'SPCR_MSTR': '$10', # Master/Slave Select
+ 'SPCR_CPOL': '$8', # Clock polarity
+ 'SPCR_CPHA': '$4', # Clock Phase
+ 'SPCR_SPR': '$3', # SPI Clock Rate Selects
+ 'SPSR' : '$4d', # SPI Status Register
+ 'SPSR_SPIF': '$80', # SPI Interrupt Flag
+ 'SPSR_WCOL': '$40', # Write Collision Flag
+ 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
+ 'SPDR' : '$4e', # SPI Data Register
+
+# Module USI
+ 'USIDR' : '$ba', # USI Data Register
+ 'USISR' : '$b9', # USI Status Register
+ 'USISR_USISIF': '$80', # Start Condition Interrupt Flag
+ 'USISR_USIOIF': '$40', # Counter Overflow Interrupt Fla
+ 'USISR_USIPF': '$20', # Stop Condition Flag
+ 'USISR_USIDC': '$10', # Data Output Collision
+ 'USISR_USICNT': '$f', # USI Counter Value Bits
+ 'USICR' : '$b8', # USI Control Register
+ 'USICR_USISIE': '$80', # Start Condition Interrupt Enab
+ 'USICR_USIOIE': '$40', # Counter Overflow Interrupt Ena
+ 'USICR_USIWM': '$30', # USI Wire Mode Bits
+ 'USICR_USICS': '$c', # USI Clock Source Select Bits
+ 'USICR_USICLK': '$2', # Clock Strobe
+ 'USICR_USITC': '$1', # Toggle Clock Port Pin
+
+# Module USART0
+ 'UDR0' : '$c6', # USART I/O Data Register
+ 'UCSR0A' : '$c0', # USART Control and Status Regis
+ 'UCSR0A_RXC0': '$80', # USART Receive Complete
+ 'UCSR0A_TXC0': '$40', # USART Transmit Complete
+ 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
+ 'UCSR0A_FE0': '$10', # Framing Error
+ 'UCSR0A_DOR0': '$8', # Data OverRun
+ 'UCSR0A_UPE0': '$4', # USART Parity Error
+ 'UCSR0A_U2X0': '$2', # Double the USART Transmission
+ 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
+ 'UCSR0B' : '$c1', # USART Control and Status Regis
+ 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
+ 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
+ 'UCSR0B_UDRIE0': '$20', # USART Data Register Empty Inte
+ 'UCSR0B_RXEN0': '$10', # Receiver Enable
+ 'UCSR0B_TXEN0': '$8', # Transmitter Enable
+ 'UCSR0B_UCSZ02': '$4', # Character Size
+ 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
+ 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
+ 'UCSR0C' : '$c2', # USART Control and Status Regis
+ 'UCSR0C_UMSEL0': '$40', # USART Mode Select
+ 'UCSR0C_UPM0': '$30', # Parity Mode Bits
+ 'UCSR0C_USBS0': '$8', # Stop Bit Select
+ 'UCSR0C_UCSZ0': '$6', # Character Size
+ 'UCSR0C_UCPOL0': '$1', # Clock Polarity
+ 'UBRR0' : '$c4', # USART Baud Rate Register Byte
+
+# Module CPU
+ 'SREG' : '$5f', # Status Register
+ 'SREG_I': '$80', # Global Interrupt Enable
+ 'SREG_T': '$40', # Bit Copy Storage
+ 'SREG_H': '$20', # Half Carry Flag
+ 'SREG_S': '$10', # Sign Bit
+ 'SREG_V': '$8', # Two's Complement Overflow Flag
+ 'SREG_N': '$4', # Negative Flag
+ 'SREG_Z': '$2', # Zero Flag
+ 'SREG_C': '$1', # Carry Flag
+ 'SP' : '$5d', # Stack Pointer
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_PUD': '$10', # Pull-up disable
+ 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
+ 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+ 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
+ 'MCUSR_BORF': '$4', # Brown-out Reset Flag
+ 'MCUSR_EXTRF': '$2', # External Reset Flag
+ 'MCUSR_PORF': '$1', # Power-on reset flag
+ 'OSCCAL' : '$66', # Oscillator Calibration Value
+ 'CLKPR' : '$61', # Clock Prescale Register
+ 'CLKPR_CLKPCE': '$80', # Clock Prescaler Change Enable
+ 'CLKPR_CLKPS': '$f', # Clock Prescaler Select Bits
+ 'PRR' : '$64', # Power Reduction Register
+ 'PRR_PRLCD': '$10', # Power Reduction LCD
+ 'PRR_PRTIM1': '$8', # Power Reduction Timer/Counter1
+ 'PRR_PRSPI': '$4', # Power Reduction Serial Periphe
+ 'PRR_PRUSART0': '$2', # Power Reduction USART
+ 'PRR_PRADC': '$1', # Power Reduction ADC
+ 'SMCR' : '$53', # Sleep Mode Control Register
+ 'SMCR_SM': '$e', # Sleep Mode Select bits
+ 'SMCR_SE': '$1', # Sleep Enable
+ 'GPIOR2' : '$4b', # General Purpose IO Register 2
+ 'GPIOR1' : '$4a', # General Purpose IO Register 1
+ 'GPIOR0' : '$3e', # General Purpose IO Register 0
+
+# Module JTAG
+ 'OCDR' : '$51', # On-Chip Debug Related Register
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_JTD': '$80', # JTAG Interface Disable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+
+# Module EEPROM
+ 'EEAR' : '$41', # EEPROM Read/Write Access Byte
+ 'EEDR' : '$40', # EEPROM Data Register
+ 'EECR' : '$3f', # EEPROM Control Register
+ 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
+ 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
+ 'EECR_EEWE': '$2', # EEPROM Write Enable
+ 'EECR_EERE': '$1', # EEPROM Read Enable
+
+# Module PORTA
+ 'PORTA' : '$22', # Port A Data Register
+ 'DDRA' : '$21', # Port A Data Direction Register
+ 'PINA' : '$20', # Port A Input Pins
+
+# Module PORTB
+ 'PORTB' : '$25', # Port B Data Register
+ 'DDRB' : '$24', # Port B Data Direction Register
+ 'PINB' : '$23', # Port B Input Pins
+
+# Module PORTC
+ 'PORTC' : '$28', # Port C Data Register
+ 'DDRC' : '$27', # Port C Data Direction Register
+ 'PINC' : '$26', # Port C Input Pins
+
+# Module PORTD
+ 'PORTD' : '$2b', # Port D Data Register
+ 'DDRD' : '$2a', # Port D Data Direction Register
+ 'PIND' : '$29', # Port D Input Pins
+
+# Module PORTE
+ 'PORTE' : '$2e', # Data Register, Port E
+ 'DDRE' : '$2d', # Data Direction Register, Port
+ 'PINE' : '$2c', # Input Pins, Port E
+
+# Module PORTF
+ 'PORTF' : '$31', # Data Register, Port F
+ 'DDRF' : '$30', # Data Direction Register, Port
+ 'PINF' : '$2f', # Input Pins, Port F
+
+# Module PORTG
+ 'PORTG' : '$34', # Port G Data Register
+ 'DDRG' : '$33', # Port G Data Direction Register
+ 'PING' : '$32', # Port G Input Pins
+
+# Module TIMER_COUNTER_0
+ 'TCCR0A' : '$44', # Timer/Counter0 Control Registe
+ 'TCCR0A_FOC0A': '$80', # Force Output Compare
+ 'TCCR0A_WGM00': '$40', # Waveform Generation Mode 0
+ 'TCCR0A_COM0A': '$30', # Compare Match Output Modes
+ 'TCCR0A_WGM01': '$8', # Waveform Generation Mode 1
+ 'TCCR0A_CS0': '$7', # Clock Selects
+ 'TCNT0' : '$46', # Timer/Counter0
+ 'OCR0A' : '$47', # Timer/Counter0 Output Compare
+ 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
+ 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
+ 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
+ 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
+ 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
+ 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Control Register
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSR310': '$1', # Prescaler Reset Timer/Counter1
+
+# Module TIMER_COUNTER_2
+ 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
+ 'TCCR2A_FOC2A': '$80', # Force Output Compare A
+ 'TCCR2A_WGM20': '$40', # Waveform Generation Mode
+ 'TCCR2A_COM2A': '$30', # Compare Output Mode bits
+ 'TCCR2A_WGM21': '$8', # Waveform Generation Mode
+ 'TCCR2A_CS2': '$7', # Clock Select bits
+ 'TCNT2' : '$b2', # Timer/Counter2
+ 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
+ 'TIMSK2' : '$70', # Timer/Counter2 Interrupt Mask
+ 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
+ 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
+ 'TIFR2' : '$37', # Timer/Counter2 Interrupt Flag
+ 'TIFR2_OCF2A': '$2', # Timer/Counter2 Output Compare
+ 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_PSR2': '$2', # Prescaler Reset Timer/Counter2
+ 'ASSR' : '$b6', # Asynchronous Status Register
+ 'ASSR_EXCLK': '$10', # Enable External Clock Interrup
+ 'ASSR_AS2': '$8', # AS2: Asynchronous Timer/Counte
+ 'ASSR_TCN2UB': '$4', # TCN2UB: Timer/Counter2 Update
+ 'ASSR_OCR2UB': '$2', # Output Compare Register2 Updat
+ 'ASSR_TCR2UB': '$1', # TCR2UB: Timer/Counter Control
+
+# Module TIMER_COUNTER_1
+ 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
+ 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
+ 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
+ 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
+ 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
+ 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
+ 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
+ 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
+ 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
+ 'TCCR1C' : '$82', # Timer/Counter 1 Control Regist
+ 'TCCR1C_FOC1A': '$80', # Force Output Compare 1A
+ 'TCCR1C_FOC1B': '$40', # Force Output Compare 1B
+ 'TCNT1' : '$84', # Timer/Counter1 Bytes
+ 'OCR1A' : '$88', # Timer/Counter1 Output Compare
+ 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
+ 'ICR1' : '$86', # Timer/Counter1 Input Capture R
+ 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
+ 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
+ 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
+ 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
+ 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
+ 'TIFR1' : '$36', # Timer/Counter1 Interrupt Flag
+ 'TIFR1_ICF1': '$20', # Input Capture Flag 1
+ 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
+ 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
+ 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
+
+# Module WATCHDOG
+ 'WDTCR' : '$60', # Watchdog Timer Control Registe
+ 'WDTCR_WDCE': '$10', # Watchdog Change Enable
+ 'WDTCR_WDE': '$8', # Watch Dog Enable
+ 'WDTCR_WDP': '$7', # Watch Dog Timer Prescaler bits
+
+# Module BOOT_LOAD
+ 'SPMCSR' : '$57', # Store Program Memory Control R
+ 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
+ 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
+ 'SPMCSR_RWWSRE': '$10', # Read While Write section read
+ 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
+ 'SPMCSR_PGWRT': '$4', # Page Write
+ 'SPMCSR_PGERS': '$2', # Page Erase
+ 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
+
+# Module PORTH
+ 'PORTH' : '$da', # PORT H Data Register
+ 'DDRH' : '$d9', # PORT H Data Direction Register
+ 'PINH' : '$d8', # PORT H Input Pins
+
+# Module PORTJ
+ 'PORTJ' : '$dd', # PORT J Data Register
+ 'DDRJ' : '$dc', # PORT J Data Direction Register
+ 'PINJ' : '$db', # PORT J Input Pins
+
+# Module EXTERNAL_INTERRUPT
+ 'EICRA' : '$69', # External Interrupt Control Reg
+ 'EICRA_ISC01': '$2', # External Interrupt Sense Contr
+ 'EICRA_ISC00': '$1', # External Interrupt Sense Contr
+ 'EIMSK' : '$3d', # External Interrupt Mask Regist
+ 'EIMSK_PCIE': '$f0', # Pin Change Interrupt Enables
+ 'EIMSK_INT0': '$1', # External Interrupt Request 0 E
+ 'EIFR' : '$3c', # External Interrupt Flag Regist
+ 'EIFR_PCIF': '$f0', # Pin Change Interrupt Flags
+ 'EIFR_INTF0': '$1', # External Interrupt Flag 0
+ 'PCMSK3' : '$73', # Pin Change Mask Register 3
+ 'PCMSK2' : '$6d', # Pin Change Mask Register 2
+ 'PCMSK1' : '$6c', # Pin Change Mask Register 1
+ 'PCMSK0' : '$6b', # Pin Change Mask Register 0
+
+ '__amforth_dummy':'0'
+}
diff --git a/amforth-6.5/avr8/devices/atmega6450/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega6450/words/no-jtag.asm
new file mode 100644
index 0000000..352a4bb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega6450/words/no-jtag.asm
@@ -0,0 +1,14 @@
+; ( -- )
+; ( -- )
+; MCU
+; disable jtag at runtime
+VE_NOJTAG:
+ .dw $FF05
+ .db "-jtag",0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOJTAG
+XT_NOJTAG:
+ .dw PFA_NOJTAG
+PFA_NOJTAG:
+
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega6450/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega6450/words/no-wdt.asm
new file mode 100644
index 0000000..4a12261
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega6450/words/no-wdt.asm
@@ -0,0 +1,22 @@
+; ( -- )
+; MCU
+; disable watch dog timer at runtime
+VE_NOWDT:
+ .dw $ff04
+ .db "-wdt"
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOWDT
+XT_NOWDT:
+ .dw PFA_NOWDT
+PFA_NOWDT:
+
+; Reset WDT
+ wdr
+; Write logical one to WDTOE and WDE
+ in_ temp1, WDTCR
+ ori temp1, (1<<WDTOE)|(1<<WDE)
+ out WDTCR, temp1
+; Turn off WDT
+ ldi temp1, (0<<WDE)
+ out_ WDTCR, temp1
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega6450/words/sleep.asm b/amforth-6.5/avr8/devices/atmega6450/words/sleep.asm
new file mode 100644
index 0000000..256249c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega6450/words/sleep.asm
@@ -0,0 +1,19 @@
+; ( mode -- )
+; MCU
+; put the controller into the specified sleep mode
+VE_SLEEP:
+ .dw $ff05
+ .db "sleep", 0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_SLEEP
+XT_SLEEP:
+ .dw PFA_SLEEP
+PFA_SLEEP:
+ andi tosl, 7 ; leave only legal mode bits
+ lsl tosl ; move to correct location (bits 3-1)
+ ori tosl, 1 ; set the SE bit
+ out_ SMCR, tosl ; set the sleep config
+ sleep ; nighty-night
+ out_ SMCR, zerol ; 0 protects against accidental sleeps
+ loadtos ; pop argument from stack
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega6450a/atmega6450a.frt b/amforth-6.5/avr8/devices/atmega6450a/atmega6450a.frt
new file mode 100644
index 0000000..23b981b
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega6450a/atmega6450a.frt
@@ -0,0 +1,298 @@
+\ Partname: ATmega6450A
+\ generated automatically
+
+\ AD_CONVERTER
+&124 constant ADMUX \ The ADC multiplexer Selection Register
+ $C0 constant ADMUX_REFS \ Reference Selection Bits
+ $20 constant ADMUX_ADLAR \ Left Adjust Result
+ $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
+&122 constant ADCSRA \ The ADC Control and Status register
+ $80 constant ADCSRA_ADEN \ ADC Enable
+ $40 constant ADCSRA_ADSC \ ADC Start Conversion
+ $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
+ $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
+ $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
+ $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
+&120 constant ADC \ ADC Data Register Bytes
+&123 constant ADCSRB \ ADC Control and Status Register B
+ $07 constant ADCSRB_ADTS \ ADC Auto Trigger Sources
+&126 constant DIDR0 \ Digital Input Disable Register 0
+ $80 constant DIDR0_ADC7D \ ADC7 Digital input Disable
+ $40 constant DIDR0_ADC6D \ ADC6 Digital input Disable
+ $20 constant DIDR0_ADC5D \ ADC5 Digital input Disable
+ $10 constant DIDR0_ADC4D \ ADC4 Digital input Disable
+ $08 constant DIDR0_ADC3D \ ADC3 Digital input Disable
+ $04 constant DIDR0_ADC2D \ ADC2 Digital input Disable
+ $02 constant DIDR0_ADC1D \ ADC1 Digital input Disable
+ $01 constant DIDR0_ADC0D \ ADC0 Digital input Disable
+\ ANALOG_COMPARATOR
+&80 constant ACSR \ Analog Comparator Control And Status Register
+ $80 constant ACSR_ACD \ Analog Comparator Disable
+ $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
+ $20 constant ACSR_ACO \ Analog Compare Output
+ $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
+ $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
+ $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
+ $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
+&127 constant DIDR1 \ Digital Input Disable Register 1
+ $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
+ $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
+\ SPI
+&76 constant SPCR \ SPI Control Register
+ $80 constant SPCR_SPIE \ SPI Interrupt Enable
+ $40 constant SPCR_SPE \ SPI Enable
+ $20 constant SPCR_DORD \ Data Order
+ $10 constant SPCR_MSTR \ Master/Slave Select
+ $08 constant SPCR_CPOL \ Clock polarity
+ $04 constant SPCR_CPHA \ Clock Phase
+ $03 constant SPCR_SPR \ SPI Clock Rate Selects
+&77 constant SPSR \ SPI Status Register
+ $80 constant SPSR_SPIF \ SPI Interrupt Flag
+ $40 constant SPSR_WCOL \ Write Collision Flag
+ $01 constant SPSR_SPI2X \ Double SPI Speed Bit
+&78 constant SPDR \ SPI Data Register
+\ USI
+&186 constant USIDR \ USI Data Register
+&185 constant USISR \ USI Status Register
+ $80 constant USISR_USISIF \ Start Condition Interrupt Flag
+ $40 constant USISR_USIOIF \ Counter Overflow Interrupt Flag
+ $20 constant USISR_USIPF \ Stop Condition Flag
+ $10 constant USISR_USIDC \ Data Output Collision
+ $0F constant USISR_USICNT \ USI Counter Value Bits
+&184 constant USICR \ USI Control Register
+ $80 constant USICR_USISIE \ Start Condition Interrupt Enable
+ $40 constant USICR_USIOIE \ Counter Overflow Interrupt Enable
+ $30 constant USICR_USIWM \ USI Wire Mode Bits
+ $0C constant USICR_USICS \ USI Clock Source Select Bits
+ $02 constant USICR_USICLK \ Clock Strobe
+ $01 constant USICR_USITC \ Toggle Clock Port Pin
+\ USART0
+&198 constant UDR0 \ USART I/O Data Register
+&192 constant UCSR0A \ USART Control and Status Register A
+ $80 constant UCSR0A_RXC0 \ USART Receive Complete
+ $40 constant UCSR0A_TXC0 \ USART Transmit Complete
+ $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
+ $10 constant UCSR0A_FE0 \ Framing Error
+ $08 constant UCSR0A_DOR0 \ Data OverRun
+ $04 constant UCSR0A_UPE0 \ USART Parity Error
+ $02 constant UCSR0A_U2X0 \ Double the USART Transmission Speed
+ $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
+&193 constant UCSR0B \ USART Control and Status Register B
+ $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
+ $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
+ $20 constant UCSR0B_UDRIE0 \ USART Data Register Empty Interrupt Enable
+ $10 constant UCSR0B_RXEN0 \ Receiver Enable
+ $08 constant UCSR0B_TXEN0 \ Transmitter Enable
+ $04 constant UCSR0B_UCSZ02 \ Character Size
+ $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
+ $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
+&194 constant UCSR0C \ USART Control and Status Register C
+ $40 constant UCSR0C_UMSEL0 \ USART Mode Select
+ $30 constant UCSR0C_UPM0 \ Parity Mode Bits
+ $08 constant UCSR0C_USBS0 \ Stop Bit Select
+ $06 constant UCSR0C_UCSZ0 \ Character Size
+ $01 constant UCSR0C_UCPOL0 \ Clock Polarity
+&196 constant UBRR0 \ USART Baud Rate Register Bytes
+\ CPU
+&95 constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ $08 constant SREG_V \ Two's Complement Overflow Flag
+ $04 constant SREG_N \ Negative Flag
+ $02 constant SREG_Z \ Zero Flag
+ $01 constant SREG_C \ Carry Flag
+&93 constant SP \ Stack Pointer
+&85 constant MCUCR \ MCU Control Register
+ $10 constant MCUCR_PUD \ Pull-up disable
+ $02 constant MCUCR_IVSEL \ Interrupt Vector Select
+ $01 constant MCUCR_IVCE \ Interrupt Vector Change Enable
+&84 constant MCUSR \ MCU Status Register
+ $10 constant MCUSR_JTRF \ JTAG Reset Flag
+ $08 constant MCUSR_WDRF \ Watchdog Reset Flag
+ $04 constant MCUSR_BORF \ Brown-out Reset Flag
+ $02 constant MCUSR_EXTRF \ External Reset Flag
+ $01 constant MCUSR_PORF \ Power-on reset flag
+&102 constant OSCCAL \ Oscillator Calibration Value
+&97 constant CLKPR \ Clock Prescale Register
+ $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable
+ $0F constant CLKPR_CLKPS \ Clock Prescaler Select Bits
+&100 constant PRR \ Power Reduction Register
+ $10 constant PRR_PRLCD \ Power Reduction LCD
+ $08 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
+ $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
+ $02 constant PRR_PRUSART0 \ Power Reduction USART
+ $01 constant PRR_PRADC \ Power Reduction ADC
+&83 constant SMCR \ Sleep Mode Control Register
+ $0E constant SMCR_SM \ Sleep Mode Select bits
+ $01 constant SMCR_SE \ Sleep Enable
+&75 constant GPIOR2 \ General Purpose IO Register 2
+&74 constant GPIOR1 \ General Purpose IO Register 1
+&62 constant GPIOR0 \ General Purpose IO Register 0
+\ JTAG
+&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
+\ EEPROM
+&65 constant EEAR \ EEPROM Read/Write Access Bytes
+&64 constant EEDR \ EEPROM Data Register
+&63 constant EECR \ EEPROM Control Register
+ $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
+ $04 constant EECR_EEMWE \ EEPROM Master Write Enable
+ $02 constant EECR_EEWE \ EEPROM Write Enable
+ $01 constant EECR_EERE \ EEPROM Read Enable
+\ PORTA
+&34 constant PORTA \ Port A Data Register
+&33 constant DDRA \ Port A Data Direction Register
+&32 constant PINA \ Port A Input Pins
+\ PORTB
+&37 constant PORTB \ Port B Data Register
+&36 constant DDRB \ Port B Data Direction Register
+&35 constant PINB \ Port B Input Pins
+\ PORTC
+&40 constant PORTC \ Port C Data Register
+&39 constant DDRC \ Port C Data Direction Register
+&38 constant PINC \ Port C Input Pins
+\ PORTD
+&43 constant PORTD \ Port D Data Register
+&42 constant DDRD \ Port D Data Direction Register
+&41 constant PIND \ Port D Input Pins
+\ PORTE
+&46 constant PORTE \ Data Register, Port E
+&45 constant DDRE \ Data Direction Register, Port E
+&44 constant PINE \ Input Pins, Port E
+\ PORTF
+&49 constant PORTF \ Data Register, Port F
+&48 constant DDRF \ Data Direction Register, Port F
+&47 constant PINF \ Input Pins, Port F
+\ PORTG
+&52 constant PORTG \ Port G Data Register
+&51 constant DDRG \ Port G Data Direction Register
+&50 constant PING \ Port G Input Pins
+\ TIMER_COUNTER_0
+&68 constant TCCR0A \ Timer/Counter0 Control Register
+ $80 constant TCCR0A_FOC0A \ Force Output Compare
+ $40 constant TCCR0A_WGM00 \ Waveform Generation Mode 0
+ $30 constant TCCR0A_COM0A \ Compare Match Output Modes
+ $08 constant TCCR0A_WGM01 \ Waveform Generation Mode 1
+ $07 constant TCCR0A_CS0 \ Clock Selects
+&70 constant TCNT0 \ Timer/Counter0
+&71 constant OCR0A \ Timer/Counter0 Output Compare Register
+&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
+ $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match Interrupt Enable
+ $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
+&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
+ $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0
+ $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
+&67 constant GTCCR \ General Timer/Control Register
+ $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
+ $01 constant GTCCR_PSR310 \ Prescaler Reset Timer/Counter1 and Timer/Counter0
+\ TIMER_COUNTER_2
+&176 constant TCCR2A \ Timer/Counter2 Control Register
+ $80 constant TCCR2A_FOC2A \ Force Output Compare A
+ $40 constant TCCR2A_WGM20 \ Waveform Generation Mode
+ $30 constant TCCR2A_COM2A \ Compare Output Mode bits
+ $08 constant TCCR2A_WGM21 \ Waveform Generation Mode
+ $07 constant TCCR2A_CS2 \ Clock Select bits
+&178 constant TCNT2 \ Timer/Counter2
+&179 constant OCR2A \ Timer/Counter2 Output Compare Register
+&112 constant TIMSK2 \ Timer/Counter2 Interrupt Mask register
+ $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match Interrupt Enable
+ $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
+&55 constant TIFR2 \ Timer/Counter2 Interrupt Flag Register
+ $02 constant TIFR2_OCF2A \ Timer/Counter2 Output Compare Flag 2
+ $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
+&182 constant ASSR \ Asynchronous Status Register
+ $10 constant ASSR_EXCLK \ Enable External Clock Interrupt
+ $08 constant ASSR_AS2 \ AS2: Asynchronous Timer/Counter2
+ $04 constant ASSR_TCN2UB \ TCN2UB: Timer/Counter2 Update Busy
+ $02 constant ASSR_OCR2UB \ Output Compare Register2 Update Busy
+ $01 constant ASSR_TCR2UB \ TCR2UB: Timer/Counter Control Register2 Update Busy
+\ TIMER_COUNTER_1
+&128 constant TCCR1A \ Timer/Counter1 Control Register A
+ $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
+ $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
+ $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
+&129 constant TCCR1B \ Timer/Counter1 Control Register B
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
+ $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
+&130 constant TCCR1C \ Timer/Counter 1 Control Register C
+ $80 constant TCCR1C_FOC1A \ Force Output Compare 1A
+ $40 constant TCCR1C_FOC1B \ Force Output Compare 1B
+&132 constant TCNT1 \ Timer/Counter1 Bytes
+&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
+&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
+&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
+&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
+ $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
+ $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
+ $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
+ $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
+&54 constant TIFR1 \ Timer/Counter1 Interrupt Flag register
+ $20 constant TIFR1_ICF1 \ Input Capture Flag 1
+ $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
+ $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
+ $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
+\ WATCHDOG
+&96 constant WDTCR \ Watchdog Timer Control Register
+ $10 constant WDTCR_WDCE \ Watchdog Change Enable
+ $08 constant WDTCR_WDE \ Watch Dog Enable
+ $07 constant WDTCR_WDP \ Watch Dog Timer Prescaler bits
+\ BOOT_LOAD
+&87 constant SPMCSR \ Store Program Memory Control Register
+ $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
+ $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
+ $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
+ $04 constant SPMCSR_PGWRT \ Page Write
+ $02 constant SPMCSR_PGERS \ Page Erase
+ $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
+\ PORTH
+&218 constant PORTH \ PORT H Data Register
+&217 constant DDRH \ PORT H Data Direction Register
+&216 constant PINH \ PORT H Input Pins
+\ PORTJ
+&221 constant PORTJ \ PORT J Data Register
+&220 constant DDRJ \ PORT J Data Direction Register
+&219 constant PINJ \ PORT J Input Pins
+\ EXTERNAL_INTERRUPT
+&105 constant EICRA \ External Interrupt Control Register A
+ $02 constant EICRA_ISC01 \ External Interrupt Sense Control 0 Bit 1
+ $01 constant EICRA_ISC00 \ External Interrupt Sense Control 0 Bit 0
+&61 constant EIMSK \ External Interrupt Mask Register
+ $F0 constant EIMSK_PCIE \ Pin Change Interrupt Enables
+ $01 constant EIMSK_INT0 \ External Interrupt Request 0 Enable
+&60 constant EIFR \ External Interrupt Flag Register
+ $F0 constant EIFR_PCIF \ Pin Change Interrupt Flags
+ $01 constant EIFR_INTF0 \ External Interrupt Flag 0
+&115 constant PCMSK3 \ Pin Change Mask Register 3
+&109 constant PCMSK2 \ Pin Change Mask Register 2
+&108 constant PCMSK1 \ Pin Change Mask Register 1
+&107 constant PCMSK0 \ Pin Change Mask Register 0
+
+\ Interrupts
+&2 constant INT0Addr \ External Interrupt Request 0
+&4 constant PCINT0Addr \ Pin Change Interrupt Request 0
+&6 constant PCINT1Addr \ Pin Change Interrupt Request 1
+&8 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
+&10 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
+&12 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+&14 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
+&16 constant TIMER1_COMPBAddr \ Timer/Counter Compare Match B
+&18 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+&20 constant TIMER0_COMPAddr \ Timer/Counter0 Compare Match
+&22 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
+&24 constant SPI__STCAddr \ SPI Serial Transfer Complete
+&26 constant USART__RXAddr \ USART, Rx Complete
+&28 constant USART__UDREAddr \ USART Data register Empty
+&30 constant USART0__TXAddr \ USART0, Tx Complete
+&32 constant USI_STARTAddr \ USI Start Condition
+&34 constant USI_OVERFLOWAddr \ USI Overflow
+&36 constant ANALOG_COMPAddr \ Analog Comparator
+&38 constant ADCAddr \ ADC Conversion Complete
+&40 constant EE_READYAddr \ EEPROM Ready
+&42 constant SPM_READYAddr \ Store Program Memory Read
+&44 constant NOT_USEDAddr \ RESERVED
+&46 constant PCINT2Addr \ Pin Change Interrupt Request 2
+&48 constant PCINT3Addr \ Pin Change Interrupt Request 3
diff --git a/amforth-6.5/avr8/devices/atmega6450a/device.asm b/amforth-6.5/avr8/devices/atmega6450a/device.asm
new file mode 100644
index 0000000..5d2225b
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega6450a/device.asm
@@ -0,0 +1,114 @@
+; Partname: ATmega6450A
+; generated automatically, do not edit
+
+.nolist
+ .include "m6450Adef.inc"
+.list
+
+.equ ramstart = 256
+.equ CELLSIZE = 2
+.macro readflashcell
+ lsl zl
+ rol zh
+ lpm @0, Z+
+ lpm @1, Z+
+.endmacro
+.macro writeflashcell
+ lsl zl
+ rol zh
+.endmacro
+.set WANT_AD_CONVERTER = 0
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_SPI = 0
+.set WANT_USI = 0
+.set WANT_USART0 = 0
+.set WANT_CPU = 0
+.set WANT_JTAG = 0
+.set WANT_EEPROM = 0
+.set WANT_PORTA = 0
+.set WANT_PORTB = 0
+.set WANT_PORTC = 0
+.set WANT_PORTD = 0
+.set WANT_PORTE = 0
+.set WANT_PORTF = 0
+.set WANT_PORTG = 0
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_TIMER_COUNTER_2 = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_WATCHDOG = 0
+.set WANT_BOOT_LOAD = 0
+.set WANT_PORTH = 0
+.set WANT_PORTJ = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.equ intvecsize = 2 ; please verify; flash size: 65536 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.org 2
+ rcall isr ; External Interrupt Request 0
+.org 4
+ rcall isr ; Pin Change Interrupt Request 0
+.org 6
+ rcall isr ; Pin Change Interrupt Request 1
+.org 8
+ rcall isr ; Timer/Counter2 Compare Match
+.org 10
+ rcall isr ; Timer/Counter2 Overflow
+.org 12
+ rcall isr ; Timer/Counter1 Capture Event
+.org 14
+ rcall isr ; Timer/Counter1 Compare Match A
+.org 16
+ rcall isr ; Timer/Counter Compare Match B
+.org 18
+ rcall isr ; Timer/Counter1 Overflow
+.org 20
+ rcall isr ; Timer/Counter0 Compare Match
+.org 22
+ rcall isr ; Timer/Counter0 Overflow
+.org 24
+ rcall isr ; SPI Serial Transfer Complete
+.org 26
+ rcall isr ; USART, Rx Complete
+.org 28
+ rcall isr ; USART Data register Empty
+.org 30
+ rcall isr ; USART0, Tx Complete
+.org 32
+ rcall isr ; USI Start Condition
+.org 34
+ rcall isr ; USI Overflow
+.org 36
+ rcall isr ; Analog Comparator
+.org 38
+ rcall isr ; ADC Conversion Complete
+.org 40
+ rcall isr ; EEPROM Ready
+.org 42
+ rcall isr ; Store Program Memory Read
+.org 44
+ rcall isr ; RESERVED
+.org 46
+ rcall isr ; Pin Change Interrupt Request 2
+.org 48
+ rcall isr ; Pin Change Interrupt Request 3
+.equ INTVECTORS = 25
+.nooverlap
+
+; compatability layer (maybe empty)
+.equ EEPE = EEWE
+.equ EEMPE = EEMWE
+
+; controller data area, environment query mcu-info
+mcu_info:
+mcu_ramsize:
+ .dw 4096
+mcu_eepromsize:
+ .dw 2048
+mcu_maxdp:
+ .dw 57344
+mcu_numints:
+ .dw 25
+mcu_name:
+ .dw 11
+ .db "ATmega6450A",0
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega6450a/device.inc b/amforth-6.5/avr8/devices/atmega6450a/device.inc
new file mode 100644
index 0000000..b71ce1b
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega6450a/device.inc
@@ -0,0 +1,1152 @@
+; Partname: ATmega6450A
+; generated automatically, no not edit
+
+.if WANT_AD_CONVERTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC multiplexer Selection Register
+VE_ADMUX:
+ .dw $ff05
+ .db "ADMUX",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADMUX
+XT_ADMUX:
+ .dw PFA_DOVARIABLE
+PFA_ADMUX:
+ .dw 124
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register
+VE_ADCSRA:
+ .dw $ff06
+ .db "ADCSRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRA
+XT_ADCSRA:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRA:
+ .dw 122
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register Bytes
+VE_ADC:
+ .dw $ff03
+ .db "ADC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADC
+XT_ADC:
+ .dw PFA_DOVARIABLE
+PFA_ADC:
+ .dw 120
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Control and Status Register B
+VE_ADCSRB:
+ .dw $ff06
+ .db "ADCSRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRB
+XT_ADCSRB:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRB:
+ .dw 123
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 0
+VE_DIDR0:
+ .dw $ff05
+ .db "DIDR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR0
+XT_DIDR0:
+ .dw PFA_DOVARIABLE
+PFA_DIDR0:
+ .dw 126
+
+.endif
+.if WANT_ANALOG_COMPARATOR == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Control And Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw 80
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 1
+VE_DIDR1:
+ .dw $ff05
+ .db "DIDR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR1
+XT_DIDR1:
+ .dw PFA_DOVARIABLE
+PFA_DIDR1:
+ .dw 127
+
+.endif
+.if WANT_SPI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR:
+ .dw $ff04
+ .db "SPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR
+XT_SPCR:
+ .dw PFA_DOVARIABLE
+PFA_SPCR:
+ .dw 76
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR:
+ .dw $ff04
+ .db "SPSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR
+XT_SPSR:
+ .dw PFA_DOVARIABLE
+PFA_SPSR:
+ .dw 77
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR:
+ .dw $ff04
+ .db "SPDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR
+XT_SPDR:
+ .dw PFA_DOVARIABLE
+PFA_SPDR:
+ .dw 78
+
+.endif
+.if WANT_USI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USI Data Register
+VE_USIDR:
+ .dw $ff05
+ .db "USIDR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USIDR
+XT_USIDR:
+ .dw PFA_DOVARIABLE
+PFA_USIDR:
+ .dw 186
+; ( -- addr ) System Constant
+; R( -- )
+; USI Status Register
+VE_USISR:
+ .dw $ff05
+ .db "USISR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USISR
+XT_USISR:
+ .dw PFA_DOVARIABLE
+PFA_USISR:
+ .dw 185
+; ( -- addr ) System Constant
+; R( -- )
+; USI Control Register
+VE_USICR:
+ .dw $ff05
+ .db "USICR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USICR
+XT_USICR:
+ .dw PFA_DOVARIABLE
+PFA_USICR:
+ .dw 184
+
+.endif
+.if WANT_USART0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR0:
+ .dw $ff04
+ .db "UDR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR0
+XT_UDR0:
+ .dw PFA_DOVARIABLE
+PFA_UDR0:
+ .dw 198
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR0A:
+ .dw $ff06
+ .db "UCSR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0A
+XT_UCSR0A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0A:
+ .dw 192
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR0B:
+ .dw $ff06
+ .db "UCSR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0B
+XT_UCSR0B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0B:
+ .dw 193
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR0C:
+ .dw $ff06
+ .db "UCSR0C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0C
+XT_UCSR0C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0C:
+ .dw 194
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Bytes
+VE_UBRR0:
+ .dw $ff05
+ .db "UBRR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR0
+XT_UBRR0:
+ .dw PFA_DOVARIABLE
+PFA_UBRR0:
+ .dw 196
+
+.endif
+.if WANT_CPU == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw 95
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer
+VE_SP:
+ .dw $ff02
+ .db "SP"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SP
+XT_SP:
+ .dw PFA_DOVARIABLE
+PFA_SP:
+ .dw 93
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw 85
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Status Register
+VE_MCUSR:
+ .dw $ff05
+ .db "MCUSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUSR
+XT_MCUSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUSR:
+ .dw 84
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Calibration Value
+VE_OSCCAL:
+ .dw $ff06
+ .db "OSCCAL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSCCAL
+XT_OSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_OSCCAL:
+ .dw 102
+; ( -- addr ) System Constant
+; R( -- )
+; Clock Prescale Register
+VE_CLKPR:
+ .dw $ff05
+ .db "CLKPR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKPR
+XT_CLKPR:
+ .dw PFA_DOVARIABLE
+PFA_CLKPR:
+ .dw 97
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register
+VE_PRR:
+ .dw $ff03
+ .db "PRR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR
+XT_PRR:
+ .dw PFA_DOVARIABLE
+PFA_PRR:
+ .dw 100
+; ( -- addr ) System Constant
+; R( -- )
+; Sleep Mode Control Register
+VE_SMCR:
+ .dw $ff04
+ .db "SMCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SMCR
+XT_SMCR:
+ .dw PFA_DOVARIABLE
+PFA_SMCR:
+ .dw 83
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 2
+VE_GPIOR2:
+ .dw $ff06
+ .db "GPIOR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR2
+XT_GPIOR2:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR2:
+ .dw 75
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 1
+VE_GPIOR1:
+ .dw $ff06
+ .db "GPIOR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR1
+XT_GPIOR1:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR1:
+ .dw 74
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 0
+VE_GPIOR0:
+ .dw $ff06
+ .db "GPIOR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR0
+XT_GPIOR0:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR0:
+ .dw 62
+
+.endif
+.if WANT_JTAG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; On-Chip Debug Related Register in I/O Memory
+VE_OCDR:
+ .dw $ff04
+ .db "OCDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCDR
+XT_OCDR:
+ .dw PFA_DOVARIABLE
+PFA_OCDR:
+ .dw 81
+
+.endif
+.if WANT_EEPROM == 1
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Read/Write Access Bytes
+VE_EEAR:
+ .dw $ff04
+ .db "EEAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEAR
+XT_EEAR:
+ .dw PFA_DOVARIABLE
+PFA_EEAR:
+ .dw 65
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw 64
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw 63
+
+.endif
+.if WANT_PORTA == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Register
+VE_PORTA:
+ .dw $ff05
+ .db "PORTA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTA
+XT_PORTA:
+ .dw PFA_DOVARIABLE
+PFA_PORTA:
+ .dw 34
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Direction Register
+VE_DDRA:
+ .dw $ff04
+ .db "DDRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRA
+XT_DDRA:
+ .dw PFA_DOVARIABLE
+PFA_DDRA:
+ .dw 33
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Input Pins
+VE_PINA:
+ .dw $ff04
+ .db "PINA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINA
+XT_PINA:
+ .dw PFA_DOVARIABLE
+PFA_PINA:
+ .dw 32
+
+.endif
+.if WANT_PORTB == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw 37
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw 36
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw 35
+
+.endif
+.if WANT_PORTC == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Register
+VE_PORTC:
+ .dw $ff05
+ .db "PORTC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTC
+XT_PORTC:
+ .dw PFA_DOVARIABLE
+PFA_PORTC:
+ .dw 40
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Direction Register
+VE_DDRC:
+ .dw $ff04
+ .db "DDRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRC
+XT_DDRC:
+ .dw PFA_DOVARIABLE
+PFA_DDRC:
+ .dw 39
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Input Pins
+VE_PINC:
+ .dw $ff04
+ .db "PINC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINC
+XT_PINC:
+ .dw PFA_DOVARIABLE
+PFA_PINC:
+ .dw 38
+
+.endif
+.if WANT_PORTD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw 43
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw 42
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw 41
+
+.endif
+.if WANT_PORTE == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port E
+VE_PORTE:
+ .dw $ff05
+ .db "PORTE",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTE
+XT_PORTE:
+ .dw PFA_DOVARIABLE
+PFA_PORTE:
+ .dw 46
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port E
+VE_DDRE:
+ .dw $ff04
+ .db "DDRE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRE
+XT_DDRE:
+ .dw PFA_DOVARIABLE
+PFA_DDRE:
+ .dw 45
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port E
+VE_PINE:
+ .dw $ff04
+ .db "PINE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINE
+XT_PINE:
+ .dw PFA_DOVARIABLE
+PFA_PINE:
+ .dw 44
+
+.endif
+.if WANT_PORTF == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port F
+VE_PORTF:
+ .dw $ff05
+ .db "PORTF",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTF
+XT_PORTF:
+ .dw PFA_DOVARIABLE
+PFA_PORTF:
+ .dw 49
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port F
+VE_DDRF:
+ .dw $ff04
+ .db "DDRF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRF
+XT_DDRF:
+ .dw PFA_DOVARIABLE
+PFA_DDRF:
+ .dw 48
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port F
+VE_PINF:
+ .dw $ff04
+ .db "PINF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINF
+XT_PINF:
+ .dw PFA_DOVARIABLE
+PFA_PINF:
+ .dw 47
+
+.endif
+.if WANT_PORTG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Data Register
+VE_PORTG:
+ .dw $ff05
+ .db "PORTG",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTG
+XT_PORTG:
+ .dw PFA_DOVARIABLE
+PFA_PORTG:
+ .dw 52
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Data Direction Register
+VE_DDRG:
+ .dw $ff04
+ .db "DDRG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRG
+XT_DDRG:
+ .dw PFA_DOVARIABLE
+PFA_DDRG:
+ .dw 51
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Input Pins
+VE_PING:
+ .dw $ff04
+ .db "PING"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PING
+XT_PING:
+ .dw PFA_DOVARIABLE
+PFA_PING:
+ .dw 50
+
+.endif
+.if WANT_TIMER_COUNTER_0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Control Register
+VE_TCCR0A:
+ .dw $ff06
+ .db "TCCR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0A
+XT_TCCR0A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0A:
+ .dw 68
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw 70
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0A:
+ .dw $ff05
+ .db "OCR0A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0A
+XT_OCR0A:
+ .dw PFA_DOVARIABLE
+PFA_OCR0A:
+ .dw 71
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Mask Register
+VE_TIMSK0:
+ .dw $ff06
+ .db "TIMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK0
+XT_TIMSK0:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK0:
+ .dw 110
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Flag register
+VE_TIFR0:
+ .dw $ff05
+ .db "TIFR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR0
+XT_TIFR0:
+ .dw PFA_DOVARIABLE
+PFA_TIFR0:
+ .dw 53
+; ( -- addr ) System Constant
+; R( -- )
+; General Timer/Control Register
+VE_GTCCR:
+ .dw $ff05
+ .db "GTCCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GTCCR
+XT_GTCCR:
+ .dw PFA_DOVARIABLE
+PFA_GTCCR:
+ .dw 67
+
+.endif
+.if WANT_TIMER_COUNTER_2 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register
+VE_TCCR2A:
+ .dw $ff06
+ .db "TCCR2A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2A
+XT_TCCR2A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2A:
+ .dw 176
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2
+VE_TCNT2:
+ .dw $ff05
+ .db "TCNT2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT2
+XT_TCNT2:
+ .dw PFA_DOVARIABLE
+PFA_TCNT2:
+ .dw 178
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register
+VE_OCR2A:
+ .dw $ff05
+ .db "OCR2A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2A
+XT_OCR2A:
+ .dw PFA_DOVARIABLE
+PFA_OCR2A:
+ .dw 179
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Interrupt Mask register
+VE_TIMSK2:
+ .dw $ff06
+ .db "TIMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK2
+XT_TIMSK2:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK2:
+ .dw 112
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Interrupt Flag Register
+VE_TIFR2:
+ .dw $ff05
+ .db "TIFR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR2
+XT_TIFR2:
+ .dw PFA_DOVARIABLE
+PFA_TIFR2:
+ .dw 55
+; ( -- addr ) System Constant
+; R( -- )
+; Asynchronous Status Register
+VE_ASSR:
+ .dw $ff04
+ .db "ASSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ASSR
+XT_ASSR:
+ .dw PFA_DOVARIABLE
+PFA_ASSR:
+ .dw 182
+
+.endif
+.if WANT_TIMER_COUNTER_1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw 128
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw 129
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter 1 Control Register C
+VE_TCCR1C:
+ .dw $ff06
+ .db "TCCR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1C
+XT_TCCR1C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1C:
+ .dw 130
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Bytes
+VE_TCNT1:
+ .dw $ff05
+ .db "TCNT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1
+XT_TCNT1:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1:
+ .dw 132
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register A Bytes
+VE_OCR1A:
+ .dw $ff05
+ .db "OCR1A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1A
+XT_OCR1A:
+ .dw PFA_DOVARIABLE
+PFA_OCR1A:
+ .dw 136
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register B Bytes
+VE_OCR1B:
+ .dw $ff05
+ .db "OCR1B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1B
+XT_OCR1B:
+ .dw PFA_DOVARIABLE
+PFA_OCR1B:
+ .dw 138
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Bytes
+VE_ICR1:
+ .dw $ff04
+ .db "ICR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1
+XT_ICR1:
+ .dw PFA_DOVARIABLE
+PFA_ICR1:
+ .dw 134
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Mask Register
+VE_TIMSK1:
+ .dw $ff06
+ .db "TIMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK1
+XT_TIMSK1:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK1:
+ .dw 111
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Flag register
+VE_TIFR1:
+ .dw $ff05
+ .db "TIFR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR1
+XT_TIFR1:
+ .dw PFA_DOVARIABLE
+PFA_TIFR1:
+ .dw 54
+
+.endif
+.if WANT_WATCHDOG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCR:
+ .dw $ff05
+ .db "WDTCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCR
+XT_WDTCR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCR:
+ .dw 96
+
+.endif
+.if WANT_BOOT_LOAD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control Register
+VE_SPMCSR:
+ .dw $ff06
+ .db "SPMCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCSR
+XT_SPMCSR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCSR:
+ .dw 87
+
+.endif
+.if WANT_PORTH == 1
+; ( -- addr ) System Constant
+; R( -- )
+; PORT H Data Register
+VE_PORTH:
+ .dw $ff05
+ .db "PORTH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTH
+XT_PORTH:
+ .dw PFA_DOVARIABLE
+PFA_PORTH:
+ .dw 218
+; ( -- addr ) System Constant
+; R( -- )
+; PORT H Data Direction Register
+VE_DDRH:
+ .dw $ff04
+ .db "DDRH"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRH
+XT_DDRH:
+ .dw PFA_DOVARIABLE
+PFA_DDRH:
+ .dw 217
+; ( -- addr ) System Constant
+; R( -- )
+; PORT H Input Pins
+VE_PINH:
+ .dw $ff04
+ .db "PINH"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINH
+XT_PINH:
+ .dw PFA_DOVARIABLE
+PFA_PINH:
+ .dw 216
+
+.endif
+.if WANT_PORTJ == 1
+; ( -- addr ) System Constant
+; R( -- )
+; PORT J Data Register
+VE_PORTJ:
+ .dw $ff05
+ .db "PORTJ",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTJ
+XT_PORTJ:
+ .dw PFA_DOVARIABLE
+PFA_PORTJ:
+ .dw 221
+; ( -- addr ) System Constant
+; R( -- )
+; PORT J Data Direction Register
+VE_DDRJ:
+ .dw $ff04
+ .db "DDRJ"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRJ
+XT_DDRJ:
+ .dw PFA_DOVARIABLE
+PFA_DDRJ:
+ .dw 220
+; ( -- addr ) System Constant
+; R( -- )
+; PORT J Input Pins
+VE_PINJ:
+ .dw $ff04
+ .db "PINJ"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINJ
+XT_PINJ:
+ .dw PFA_DOVARIABLE
+PFA_PINJ:
+ .dw 219
+
+.endif
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register A
+VE_EICRA:
+ .dw $ff05
+ .db "EICRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRA
+XT_EICRA:
+ .dw PFA_DOVARIABLE
+PFA_EICRA:
+ .dw 105
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Mask Register
+VE_EIMSK:
+ .dw $ff05
+ .db "EIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIMSK
+XT_EIMSK:
+ .dw PFA_DOVARIABLE
+PFA_EIMSK:
+ .dw 61
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Flag Register
+VE_EIFR:
+ .dw $ff04
+ .db "EIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIFR
+XT_EIFR:
+ .dw PFA_DOVARIABLE
+PFA_EIFR:
+ .dw 60
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 3
+VE_PCMSK3:
+ .dw $ff06
+ .db "PCMSK3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK3
+XT_PCMSK3:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK3:
+ .dw 115
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 2
+VE_PCMSK2:
+ .dw $ff06
+ .db "PCMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK2
+XT_PCMSK2:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK2:
+ .dw 109
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 1
+VE_PCMSK1:
+ .dw $ff06
+ .db "PCMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK1
+XT_PCMSK1:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK1:
+ .dw 108
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 0
+VE_PCMSK0:
+ .dw $ff06
+ .db "PCMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK0
+XT_PCMSK0:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK0:
+ .dw 107
+
+.endif
diff --git a/amforth-6.5/avr8/devices/atmega6450a/device.py b/amforth-6.5/avr8/devices/atmega6450a/device.py
new file mode 100644
index 0000000..bea6252
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega6450a/device.py
@@ -0,0 +1,333 @@
+# Generated Automatically
+
+# Partname ATmega6450A
+
+MCUREGS = {
+# Interrupt Vectors
+ 'INT0Addr' : '#2', # External Interrupt Request 0
+ 'PCINT0Addr' : '#4', # Pin Change Interrupt Request 0
+ 'PCINT1Addr' : '#6', # Pin Change Interrupt Request 1
+ 'TIMER2_COMPAddr' : '#8', # Timer/Counter2 Compare Match
+ 'TIMER2_OVFAddr' : '#10', # Timer/Counter2 Overflow
+ 'TIMER1_CAPTAddr' : '#12', # Timer/Counter1 Capture Event
+ 'TIMER1_COMPAAddr' : '#14', # Timer/Counter1 Compare Match A
+ 'TIMER1_COMPBAddr' : '#16', # Timer/Counter Compare Match B
+ 'TIMER1_OVFAddr' : '#18', # Timer/Counter1 Overflow
+ 'TIMER0_COMPAddr' : '#20', # Timer/Counter0 Compare Match
+ 'TIMER0_OVFAddr' : '#22', # Timer/Counter0 Overflow
+ 'SPI_STCAddr' : '#24', # SPI Serial Transfer Complete
+ 'USART_RXAddr' : '#26', # USART, Rx Complete
+ 'USART_UDREAddr' : '#28', # USART Data register Empty
+ 'USART0_TXAddr' : '#30', # USART0, Tx Complete
+ 'USI_STARTAddr' : '#32', # USI Start Condition
+ 'USI_OVERFLOWAddr' : '#34', # USI Overflow
+ 'ANALOG_COMPAddr' : '#36', # Analog Comparator
+ 'ADCAddr' : '#38', # ADC Conversion Complete
+ 'EE_READYAddr' : '#40', # EEPROM Ready
+ 'SPM_READYAddr' : '#42', # Store Program Memory Read
+ 'NOT_USEDAddr' : '#44', # RESERVED
+ 'PCINT2Addr' : '#46', # Pin Change Interrupt Request 2
+ 'PCINT3Addr' : '#48', # Pin Change Interrupt Request 3
+
+# Module AD_CONVERTER
+ 'ADMUX' : '$7c', # The ADC multiplexer Selection
+ 'ADMUX_REFS': '$c0', # Reference Selection Bits
+ 'ADMUX_ADLAR': '$20', # Left Adjust Result
+ 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
+ 'ADCSRA' : '$7a', # The ADC Control and Status reg
+ 'ADCSRA_ADEN': '$80', # ADC Enable
+ 'ADCSRA_ADSC': '$40', # ADC Start Conversion
+ 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
+ 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
+ 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
+ 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
+ 'ADC' : '$78', # ADC Data Register Bytes
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Sources
+ 'DIDR0' : '$7e', # Digital Input Disable Register
+ 'DIDR0_ADC7D': '$80', # ADC7 Digital input Disable
+ 'DIDR0_ADC6D': '$40', # ADC6 Digital input Disable
+ 'DIDR0_ADC5D': '$20', # ADC5 Digital input Disable
+ 'DIDR0_ADC4D': '$10', # ADC4 Digital input Disable
+ 'DIDR0_ADC3D': '$8', # ADC3 Digital input Disable
+ 'DIDR0_ADC2D': '$4', # ADC2 Digital input Disable
+ 'DIDR0_ADC1D': '$2', # ADC1 Digital input Disable
+ 'DIDR0_ADC0D': '$1', # ADC0 Digital input Disable
+
+# Module ANALOG_COMPARATOR
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
+ 'ACSR' : '$50', # Analog Comparator Control And
+ 'ACSR_ACD': '$80', # Analog Comparator Disable
+ 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
+ 'ACSR_ACO': '$20', # Analog Compare Output
+ 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
+ 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
+ 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
+ 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
+ 'DIDR1' : '$7f', # Digital Input Disable Register
+ 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
+ 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
+
+# Module SPI
+ 'SPCR' : '$4c', # SPI Control Register
+ 'SPCR_SPIE': '$80', # SPI Interrupt Enable
+ 'SPCR_SPE': '$40', # SPI Enable
+ 'SPCR_DORD': '$20', # Data Order
+ 'SPCR_MSTR': '$10', # Master/Slave Select
+ 'SPCR_CPOL': '$8', # Clock polarity
+ 'SPCR_CPHA': '$4', # Clock Phase
+ 'SPCR_SPR': '$3', # SPI Clock Rate Selects
+ 'SPSR' : '$4d', # SPI Status Register
+ 'SPSR_SPIF': '$80', # SPI Interrupt Flag
+ 'SPSR_WCOL': '$40', # Write Collision Flag
+ 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
+ 'SPDR' : '$4e', # SPI Data Register
+
+# Module USI
+ 'USIDR' : '$ba', # USI Data Register
+ 'USISR' : '$b9', # USI Status Register
+ 'USISR_USISIF': '$80', # Start Condition Interrupt Flag
+ 'USISR_USIOIF': '$40', # Counter Overflow Interrupt Fla
+ 'USISR_USIPF': '$20', # Stop Condition Flag
+ 'USISR_USIDC': '$10', # Data Output Collision
+ 'USISR_USICNT': '$f', # USI Counter Value Bits
+ 'USICR' : '$b8', # USI Control Register
+ 'USICR_USISIE': '$80', # Start Condition Interrupt Enab
+ 'USICR_USIOIE': '$40', # Counter Overflow Interrupt Ena
+ 'USICR_USIWM': '$30', # USI Wire Mode Bits
+ 'USICR_USICS': '$c', # USI Clock Source Select Bits
+ 'USICR_USICLK': '$2', # Clock Strobe
+ 'USICR_USITC': '$1', # Toggle Clock Port Pin
+
+# Module USART0
+ 'UDR0' : '$c6', # USART I/O Data Register
+ 'UCSR0A' : '$c0', # USART Control and Status Regis
+ 'UCSR0A_RXC0': '$80', # USART Receive Complete
+ 'UCSR0A_TXC0': '$40', # USART Transmit Complete
+ 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
+ 'UCSR0A_FE0': '$10', # Framing Error
+ 'UCSR0A_DOR0': '$8', # Data OverRun
+ 'UCSR0A_UPE0': '$4', # USART Parity Error
+ 'UCSR0A_U2X0': '$2', # Double the USART Transmission
+ 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
+ 'UCSR0B' : '$c1', # USART Control and Status Regis
+ 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
+ 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
+ 'UCSR0B_UDRIE0': '$20', # USART Data Register Empty Inte
+ 'UCSR0B_RXEN0': '$10', # Receiver Enable
+ 'UCSR0B_TXEN0': '$8', # Transmitter Enable
+ 'UCSR0B_UCSZ02': '$4', # Character Size
+ 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
+ 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
+ 'UCSR0C' : '$c2', # USART Control and Status Regis
+ 'UCSR0C_UMSEL0': '$40', # USART Mode Select
+ 'UCSR0C_UPM0': '$30', # Parity Mode Bits
+ 'UCSR0C_USBS0': '$8', # Stop Bit Select
+ 'UCSR0C_UCSZ0': '$6', # Character Size
+ 'UCSR0C_UCPOL0': '$1', # Clock Polarity
+ 'UBRR0' : '$c4', # USART Baud Rate Register Byte
+
+# Module CPU
+ 'SREG' : '$5f', # Status Register
+ 'SREG_I': '$80', # Global Interrupt Enable
+ 'SREG_T': '$40', # Bit Copy Storage
+ 'SREG_H': '$20', # Half Carry Flag
+ 'SREG_S': '$10', # Sign Bit
+ 'SREG_V': '$8', # Two's Complement Overflow Flag
+ 'SREG_N': '$4', # Negative Flag
+ 'SREG_Z': '$2', # Zero Flag
+ 'SREG_C': '$1', # Carry Flag
+ 'SP' : '$5d', # Stack Pointer
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_PUD': '$10', # Pull-up disable
+ 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
+ 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+ 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
+ 'MCUSR_BORF': '$4', # Brown-out Reset Flag
+ 'MCUSR_EXTRF': '$2', # External Reset Flag
+ 'MCUSR_PORF': '$1', # Power-on reset flag
+ 'OSCCAL' : '$66', # Oscillator Calibration Value
+ 'CLKPR' : '$61', # Clock Prescale Register
+ 'CLKPR_CLKPCE': '$80', # Clock Prescaler Change Enable
+ 'CLKPR_CLKPS': '$f', # Clock Prescaler Select Bits
+ 'PRR' : '$64', # Power Reduction Register
+ 'PRR_PRLCD': '$10', # Power Reduction LCD
+ 'PRR_PRTIM1': '$8', # Power Reduction Timer/Counter1
+ 'PRR_PRSPI': '$4', # Power Reduction Serial Periphe
+ 'PRR_PRUSART0': '$2', # Power Reduction USART
+ 'PRR_PRADC': '$1', # Power Reduction ADC
+ 'SMCR' : '$53', # Sleep Mode Control Register
+ 'SMCR_SM': '$e', # Sleep Mode Select bits
+ 'SMCR_SE': '$1', # Sleep Enable
+ 'GPIOR2' : '$4b', # General Purpose IO Register 2
+ 'GPIOR1' : '$4a', # General Purpose IO Register 1
+ 'GPIOR0' : '$3e', # General Purpose IO Register 0
+
+# Module JTAG
+ 'OCDR' : '$51', # On-Chip Debug Related Register
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_JTD': '$80', # JTAG Interface Disable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+
+# Module EEPROM
+ 'EEAR' : '$41', # EEPROM Read/Write Access Byte
+ 'EEDR' : '$40', # EEPROM Data Register
+ 'EECR' : '$3f', # EEPROM Control Register
+ 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
+ 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
+ 'EECR_EEWE': '$2', # EEPROM Write Enable
+ 'EECR_EERE': '$1', # EEPROM Read Enable
+
+# Module PORTA
+ 'PORTA' : '$22', # Port A Data Register
+ 'DDRA' : '$21', # Port A Data Direction Register
+ 'PINA' : '$20', # Port A Input Pins
+
+# Module PORTB
+ 'PORTB' : '$25', # Port B Data Register
+ 'DDRB' : '$24', # Port B Data Direction Register
+ 'PINB' : '$23', # Port B Input Pins
+
+# Module PORTC
+ 'PORTC' : '$28', # Port C Data Register
+ 'DDRC' : '$27', # Port C Data Direction Register
+ 'PINC' : '$26', # Port C Input Pins
+
+# Module PORTD
+ 'PORTD' : '$2b', # Port D Data Register
+ 'DDRD' : '$2a', # Port D Data Direction Register
+ 'PIND' : '$29', # Port D Input Pins
+
+# Module PORTE
+ 'PORTE' : '$2e', # Data Register, Port E
+ 'DDRE' : '$2d', # Data Direction Register, Port
+ 'PINE' : '$2c', # Input Pins, Port E
+
+# Module PORTF
+ 'PORTF' : '$31', # Data Register, Port F
+ 'DDRF' : '$30', # Data Direction Register, Port
+ 'PINF' : '$2f', # Input Pins, Port F
+
+# Module PORTG
+ 'PORTG' : '$34', # Port G Data Register
+ 'DDRG' : '$33', # Port G Data Direction Register
+ 'PING' : '$32', # Port G Input Pins
+
+# Module TIMER_COUNTER_0
+ 'TCCR0A' : '$44', # Timer/Counter0 Control Registe
+ 'TCCR0A_FOC0A': '$80', # Force Output Compare
+ 'TCCR0A_WGM00': '$40', # Waveform Generation Mode 0
+ 'TCCR0A_COM0A': '$30', # Compare Match Output Modes
+ 'TCCR0A_WGM01': '$8', # Waveform Generation Mode 1
+ 'TCCR0A_CS0': '$7', # Clock Selects
+ 'TCNT0' : '$46', # Timer/Counter0
+ 'OCR0A' : '$47', # Timer/Counter0 Output Compare
+ 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
+ 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
+ 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
+ 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
+ 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
+ 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Control Register
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSR310': '$1', # Prescaler Reset Timer/Counter1
+
+# Module TIMER_COUNTER_2
+ 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
+ 'TCCR2A_FOC2A': '$80', # Force Output Compare A
+ 'TCCR2A_WGM20': '$40', # Waveform Generation Mode
+ 'TCCR2A_COM2A': '$30', # Compare Output Mode bits
+ 'TCCR2A_WGM21': '$8', # Waveform Generation Mode
+ 'TCCR2A_CS2': '$7', # Clock Select bits
+ 'TCNT2' : '$b2', # Timer/Counter2
+ 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
+ 'TIMSK2' : '$70', # Timer/Counter2 Interrupt Mask
+ 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
+ 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
+ 'TIFR2' : '$37', # Timer/Counter2 Interrupt Flag
+ 'TIFR2_OCF2A': '$2', # Timer/Counter2 Output Compare
+ 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_PSR2': '$2', # Prescaler Reset Timer/Counter2
+ 'ASSR' : '$b6', # Asynchronous Status Register
+ 'ASSR_EXCLK': '$10', # Enable External Clock Interrup
+ 'ASSR_AS2': '$8', # AS2: Asynchronous Timer/Counte
+ 'ASSR_TCN2UB': '$4', # TCN2UB: Timer/Counter2 Update
+ 'ASSR_OCR2UB': '$2', # Output Compare Register2 Updat
+ 'ASSR_TCR2UB': '$1', # TCR2UB: Timer/Counter Control
+
+# Module TIMER_COUNTER_1
+ 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
+ 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
+ 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
+ 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
+ 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
+ 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
+ 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
+ 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
+ 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
+ 'TCCR1C' : '$82', # Timer/Counter 1 Control Regist
+ 'TCCR1C_FOC1A': '$80', # Force Output Compare 1A
+ 'TCCR1C_FOC1B': '$40', # Force Output Compare 1B
+ 'TCNT1' : '$84', # Timer/Counter1 Bytes
+ 'OCR1A' : '$88', # Timer/Counter1 Output Compare
+ 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
+ 'ICR1' : '$86', # Timer/Counter1 Input Capture R
+ 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
+ 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
+ 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
+ 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
+ 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
+ 'TIFR1' : '$36', # Timer/Counter1 Interrupt Flag
+ 'TIFR1_ICF1': '$20', # Input Capture Flag 1
+ 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
+ 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
+ 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
+
+# Module WATCHDOG
+ 'WDTCR' : '$60', # Watchdog Timer Control Registe
+ 'WDTCR_WDCE': '$10', # Watchdog Change Enable
+ 'WDTCR_WDE': '$8', # Watch Dog Enable
+ 'WDTCR_WDP': '$7', # Watch Dog Timer Prescaler bits
+
+# Module BOOT_LOAD
+ 'SPMCSR' : '$57', # Store Program Memory Control R
+ 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
+ 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
+ 'SPMCSR_RWWSRE': '$10', # Read While Write section read
+ 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
+ 'SPMCSR_PGWRT': '$4', # Page Write
+ 'SPMCSR_PGERS': '$2', # Page Erase
+ 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
+
+# Module PORTH
+ 'PORTH' : '$da', # PORT H Data Register
+ 'DDRH' : '$d9', # PORT H Data Direction Register
+ 'PINH' : '$d8', # PORT H Input Pins
+
+# Module PORTJ
+ 'PORTJ' : '$dd', # PORT J Data Register
+ 'DDRJ' : '$dc', # PORT J Data Direction Register
+ 'PINJ' : '$db', # PORT J Input Pins
+
+# Module EXTERNAL_INTERRUPT
+ 'EICRA' : '$69', # External Interrupt Control Reg
+ 'EICRA_ISC01': '$2', # External Interrupt Sense Contr
+ 'EICRA_ISC00': '$1', # External Interrupt Sense Contr
+ 'EIMSK' : '$3d', # External Interrupt Mask Regist
+ 'EIMSK_PCIE': '$f0', # Pin Change Interrupt Enables
+ 'EIMSK_INT0': '$1', # External Interrupt Request 0 E
+ 'EIFR' : '$3c', # External Interrupt Flag Regist
+ 'EIFR_PCIF': '$f0', # Pin Change Interrupt Flags
+ 'EIFR_INTF0': '$1', # External Interrupt Flag 0
+ 'PCMSK3' : '$73', # Pin Change Mask Register 3
+ 'PCMSK2' : '$6d', # Pin Change Mask Register 2
+ 'PCMSK1' : '$6c', # Pin Change Mask Register 1
+ 'PCMSK0' : '$6b', # Pin Change Mask Register 0
+
+ '__amforth_dummy':'0'
+}
diff --git a/amforth-6.5/avr8/devices/atmega6450a/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega6450a/words/no-jtag.asm
new file mode 100644
index 0000000..352a4bb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega6450a/words/no-jtag.asm
@@ -0,0 +1,14 @@
+; ( -- )
+; ( -- )
+; MCU
+; disable jtag at runtime
+VE_NOJTAG:
+ .dw $FF05
+ .db "-jtag",0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOJTAG
+XT_NOJTAG:
+ .dw PFA_NOJTAG
+PFA_NOJTAG:
+
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega6450a/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega6450a/words/no-wdt.asm
new file mode 100644
index 0000000..4a12261
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega6450a/words/no-wdt.asm
@@ -0,0 +1,22 @@
+; ( -- )
+; MCU
+; disable watch dog timer at runtime
+VE_NOWDT:
+ .dw $ff04
+ .db "-wdt"
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOWDT
+XT_NOWDT:
+ .dw PFA_NOWDT
+PFA_NOWDT:
+
+; Reset WDT
+ wdr
+; Write logical one to WDTOE and WDE
+ in_ temp1, WDTCR
+ ori temp1, (1<<WDTOE)|(1<<WDE)
+ out WDTCR, temp1
+; Turn off WDT
+ ldi temp1, (0<<WDE)
+ out_ WDTCR, temp1
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega6450a/words/sleep.asm b/amforth-6.5/avr8/devices/atmega6450a/words/sleep.asm
new file mode 100644
index 0000000..256249c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega6450a/words/sleep.asm
@@ -0,0 +1,19 @@
+; ( mode -- )
+; MCU
+; put the controller into the specified sleep mode
+VE_SLEEP:
+ .dw $ff05
+ .db "sleep", 0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_SLEEP
+XT_SLEEP:
+ .dw PFA_SLEEP
+PFA_SLEEP:
+ andi tosl, 7 ; leave only legal mode bits
+ lsl tosl ; move to correct location (bits 3-1)
+ ori tosl, 1 ; set the SE bit
+ out_ SMCR, tosl ; set the sleep config
+ sleep ; nighty-night
+ out_ SMCR, zerol ; 0 protects against accidental sleeps
+ loadtos ; pop argument from stack
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega6450p/atmega6450p.frt b/amforth-6.5/avr8/devices/atmega6450p/atmega6450p.frt
new file mode 100644
index 0000000..6051089
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega6450p/atmega6450p.frt
@@ -0,0 +1,298 @@
+\ Partname: ATmega6450P
+\ generated automatically
+
+\ AD_CONVERTER
+&124 constant ADMUX \ The ADC multiplexer Selection Register
+ $C0 constant ADMUX_REFS \ Reference Selection Bits
+ $20 constant ADMUX_ADLAR \ Left Adjust Result
+ $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
+&122 constant ADCSRA \ The ADC Control and Status register
+ $80 constant ADCSRA_ADEN \ ADC Enable
+ $40 constant ADCSRA_ADSC \ ADC Start Conversion
+ $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
+ $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
+ $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
+ $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
+&120 constant ADC \ ADC Data Register Bytes
+&123 constant ADCSRB \ ADC Control and Status Register B
+ $07 constant ADCSRB_ADTS \ ADC Auto Trigger Sources
+&126 constant DIDR0 \ Digital Input Disable Register 0
+ $80 constant DIDR0_ADC7D \ ADC7 Digital input Disable
+ $40 constant DIDR0_ADC6D \ ADC6 Digital input Disable
+ $20 constant DIDR0_ADC5D \ ADC5 Digital input Disable
+ $10 constant DIDR0_ADC4D \ ADC4 Digital input Disable
+ $08 constant DIDR0_ADC3D \ ADC3 Digital input Disable
+ $04 constant DIDR0_ADC2D \ ADC2 Digital input Disable
+ $02 constant DIDR0_ADC1D \ ADC1 Digital input Disable
+ $01 constant DIDR0_ADC0D \ ADC0 Digital input Disable
+\ ANALOG_COMPARATOR
+&80 constant ACSR \ Analog Comparator Control And Status Register
+ $80 constant ACSR_ACD \ Analog Comparator Disable
+ $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
+ $20 constant ACSR_ACO \ Analog Compare Output
+ $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
+ $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
+ $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
+ $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
+&127 constant DIDR1 \ Digital Input Disable Register 1
+ $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
+ $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
+\ SPI
+&76 constant SPCR \ SPI Control Register
+ $80 constant SPCR_SPIE \ SPI Interrupt Enable
+ $40 constant SPCR_SPE \ SPI Enable
+ $20 constant SPCR_DORD \ Data Order
+ $10 constant SPCR_MSTR \ Master/Slave Select
+ $08 constant SPCR_CPOL \ Clock polarity
+ $04 constant SPCR_CPHA \ Clock Phase
+ $03 constant SPCR_SPR \ SPI Clock Rate Selects
+&77 constant SPSR \ SPI Status Register
+ $80 constant SPSR_SPIF \ SPI Interrupt Flag
+ $40 constant SPSR_WCOL \ Write Collision Flag
+ $01 constant SPSR_SPI2X \ Double SPI Speed Bit
+&78 constant SPDR \ SPI Data Register
+\ USI
+&186 constant USIDR \ USI Data Register
+&185 constant USISR \ USI Status Register
+ $80 constant USISR_USISIF \ Start Condition Interrupt Flag
+ $40 constant USISR_USIOIF \ Counter Overflow Interrupt Flag
+ $20 constant USISR_USIPF \ Stop Condition Flag
+ $10 constant USISR_USIDC \ Data Output Collision
+ $0F constant USISR_USICNT \ USI Counter Value Bits
+&184 constant USICR \ USI Control Register
+ $80 constant USICR_USISIE \ Start Condition Interrupt Enable
+ $40 constant USICR_USIOIE \ Counter Overflow Interrupt Enable
+ $30 constant USICR_USIWM \ USI Wire Mode Bits
+ $0C constant USICR_USICS \ USI Clock Source Select Bits
+ $02 constant USICR_USICLK \ Clock Strobe
+ $01 constant USICR_USITC \ Toggle Clock Port Pin
+\ USART0
+&198 constant UDR0 \ USART I/O Data Register
+&192 constant UCSR0A \ USART Control and Status Register A
+ $80 constant UCSR0A_RXC0 \ USART Receive Complete
+ $40 constant UCSR0A_TXC0 \ USART Transmit Complete
+ $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
+ $10 constant UCSR0A_FE0 \ Framing Error
+ $08 constant UCSR0A_DOR0 \ Data OverRun
+ $04 constant UCSR0A_UPE0 \ USART Parity Error
+ $02 constant UCSR0A_U2X0 \ Double the USART Transmission Speed
+ $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
+&193 constant UCSR0B \ USART Control and Status Register B
+ $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
+ $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
+ $20 constant UCSR0B_UDRIE0 \ USART Data Register Empty Interrupt Enable
+ $10 constant UCSR0B_RXEN0 \ Receiver Enable
+ $08 constant UCSR0B_TXEN0 \ Transmitter Enable
+ $04 constant UCSR0B_UCSZ02 \ Character Size
+ $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
+ $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
+&194 constant UCSR0C \ USART Control and Status Register C
+ $40 constant UCSR0C_UMSEL0 \ USART Mode Select
+ $30 constant UCSR0C_UPM0 \ Parity Mode Bits
+ $08 constant UCSR0C_USBS0 \ Stop Bit Select
+ $06 constant UCSR0C_UCSZ0 \ Character Size
+ $01 constant UCSR0C_UCPOL0 \ Clock Polarity
+&196 constant UBRR0 \ USART Baud Rate Register Bytes
+\ CPU
+&95 constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ $08 constant SREG_V \ Two's Complement Overflow Flag
+ $04 constant SREG_N \ Negative Flag
+ $02 constant SREG_Z \ Zero Flag
+ $01 constant SREG_C \ Carry Flag
+&93 constant SP \ Stack Pointer
+&85 constant MCUCR \ MCU Control Register
+ $10 constant MCUCR_PUD \ Pull-up disable
+ $02 constant MCUCR_IVSEL \ Interrupt Vector Select
+ $01 constant MCUCR_IVCE \ Interrupt Vector Change Enable
+&84 constant MCUSR \ MCU Status Register
+ $10 constant MCUSR_JTRF \ JTAG Reset Flag
+ $08 constant MCUSR_WDRF \ Watchdog Reset Flag
+ $04 constant MCUSR_BORF \ Brown-out Reset Flag
+ $02 constant MCUSR_EXTRF \ External Reset Flag
+ $01 constant MCUSR_PORF \ Power-on reset flag
+&102 constant OSCCAL \ Oscillator Calibration Value
+&97 constant CLKPR \ Clock Prescale Register
+ $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable
+ $0F constant CLKPR_CLKPS \ Clock Prescaler Select Bits
+&100 constant PRR \ Power Reduction Register
+ $10 constant PRR_PRLCD \ Power Reduction LCD
+ $08 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
+ $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
+ $02 constant PRR_PRUSART0 \ Power Reduction USART
+ $01 constant PRR_PRADC \ Power Reduction ADC
+&83 constant SMCR \ Sleep Mode Control Register
+ $0E constant SMCR_SM \ Sleep Mode Select bits
+ $01 constant SMCR_SE \ Sleep Enable
+&75 constant GPIOR2 \ General Purpose IO Register 2
+&74 constant GPIOR1 \ General Purpose IO Register 1
+&62 constant GPIOR0 \ General Purpose IO Register 0
+\ JTAG
+&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
+\ EEPROM
+&65 constant EEAR \ EEPROM Read/Write Access Bytes
+&64 constant EEDR \ EEPROM Data Register
+&63 constant EECR \ EEPROM Control Register
+ $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
+ $04 constant EECR_EEMWE \ EEPROM Master Write Enable
+ $02 constant EECR_EEWE \ EEPROM Write Enable
+ $01 constant EECR_EERE \ EEPROM Read Enable
+\ PORTA
+&34 constant PORTA \ Port A Data Register
+&33 constant DDRA \ Port A Data Direction Register
+&32 constant PINA \ Port A Input Pins
+\ PORTB
+&37 constant PORTB \ Port B Data Register
+&36 constant DDRB \ Port B Data Direction Register
+&35 constant PINB \ Port B Input Pins
+\ PORTC
+&40 constant PORTC \ Port C Data Register
+&39 constant DDRC \ Port C Data Direction Register
+&38 constant PINC \ Port C Input Pins
+\ PORTD
+&43 constant PORTD \ Port D Data Register
+&42 constant DDRD \ Port D Data Direction Register
+&41 constant PIND \ Port D Input Pins
+\ PORTE
+&46 constant PORTE \ Data Register, Port E
+&45 constant DDRE \ Data Direction Register, Port E
+&44 constant PINE \ Input Pins, Port E
+\ PORTF
+&49 constant PORTF \ Data Register, Port F
+&48 constant DDRF \ Data Direction Register, Port F
+&47 constant PINF \ Input Pins, Port F
+\ PORTG
+&52 constant PORTG \ Port G Data Register
+&51 constant DDRG \ Port G Data Direction Register
+&50 constant PING \ Port G Input Pins
+\ TIMER_COUNTER_0
+&68 constant TCCR0A \ Timer/Counter0 Control Register
+ $80 constant TCCR0A_FOC0A \ Force Output Compare
+ $40 constant TCCR0A_WGM00 \ Waveform Generation Mode 0
+ $30 constant TCCR0A_COM0A \ Compare Match Output Modes
+ $08 constant TCCR0A_WGM01 \ Waveform Generation Mode 1
+ $07 constant TCCR0A_CS0 \ Clock Selects
+&70 constant TCNT0 \ Timer/Counter0
+&71 constant OCR0A \ Timer/Counter0 Output Compare Register
+&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
+ $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match Interrupt Enable
+ $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
+&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
+ $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0
+ $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
+&67 constant GTCCR \ General Timer/Control Register
+ $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
+ $01 constant GTCCR_PSR310 \ Prescaler Reset Timer/Counter1 and Timer/Counter0
+\ TIMER_COUNTER_2
+&176 constant TCCR2A \ Timer/Counter2 Control Register
+ $80 constant TCCR2A_FOC2A \ Force Output Compare A
+ $40 constant TCCR2A_WGM20 \ Waveform Generation Mode
+ $30 constant TCCR2A_COM2A \ Compare Output Mode bits
+ $08 constant TCCR2A_WGM21 \ Waveform Generation Mode
+ $07 constant TCCR2A_CS2 \ Clock Select bits
+&178 constant TCNT2 \ Timer/Counter2
+&179 constant OCR2A \ Timer/Counter2 Output Compare Register
+&112 constant TIMSK2 \ Timer/Counter2 Interrupt Mask register
+ $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match Interrupt Enable
+ $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
+&55 constant TIFR2 \ Timer/Counter2 Interrupt Flag Register
+ $02 constant TIFR2_OCF2A \ Timer/Counter2 Output Compare Flag 2
+ $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
+&182 constant ASSR \ Asynchronous Status Register
+ $10 constant ASSR_EXCLK \ Enable External Clock Interrupt
+ $08 constant ASSR_AS2 \ AS2: Asynchronous Timer/Counter2
+ $04 constant ASSR_TCN2UB \ TCN2UB: Timer/Counter2 Update Busy
+ $02 constant ASSR_OCR2UB \ Output Compare Register2 Update Busy
+ $01 constant ASSR_TCR2UB \ TCR2UB: Timer/Counter Control Register2 Update Busy
+\ TIMER_COUNTER_1
+&128 constant TCCR1A \ Timer/Counter1 Control Register A
+ $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
+ $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
+ $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
+&129 constant TCCR1B \ Timer/Counter1 Control Register B
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
+ $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
+&130 constant TCCR1C \ Timer/Counter 1 Control Register C
+ $80 constant TCCR1C_FOC1A \ Force Output Compare 1A
+ $40 constant TCCR1C_FOC1B \ Force Output Compare 1B
+&132 constant TCNT1 \ Timer/Counter1 Bytes
+&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
+&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
+&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
+&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
+ $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
+ $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
+ $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
+ $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
+&54 constant TIFR1 \ Timer/Counter1 Interrupt Flag register
+ $20 constant TIFR1_ICF1 \ Input Capture Flag 1
+ $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
+ $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
+ $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
+\ WATCHDOG
+&96 constant WDTCR \ Watchdog Timer Control Register
+ $10 constant WDTCR_WDCE \ Watchdog Change Enable
+ $08 constant WDTCR_WDE \ Watch Dog Enable
+ $07 constant WDTCR_WDP \ Watch Dog Timer Prescaler bits
+\ BOOT_LOAD
+&87 constant SPMCSR \ Store Program Memory Control Register
+ $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
+ $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
+ $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
+ $04 constant SPMCSR_PGWRT \ Page Write
+ $02 constant SPMCSR_PGERS \ Page Erase
+ $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
+\ PORTH
+&218 constant PORTH \ PORT H Data Register
+&217 constant DDRH \ PORT H Data Direction Register
+&216 constant PINH \ PORT H Input Pins
+\ PORTJ
+&221 constant PORTJ \ PORT J Data Register
+&220 constant DDRJ \ PORT J Data Direction Register
+&219 constant PINJ \ PORT J Input Pins
+\ EXTERNAL_INTERRUPT
+&105 constant EICRA \ External Interrupt Control Register A
+ $02 constant EICRA_ISC01 \ External Interrupt Sense Control 0 Bit 1
+ $01 constant EICRA_ISC00 \ External Interrupt Sense Control 0 Bit 0
+&61 constant EIMSK \ External Interrupt Mask Register
+ $F0 constant EIMSK_PCIE \ Pin Change Interrupt Enables
+ $01 constant EIMSK_INT0 \ External Interrupt Request 0 Enable
+&60 constant EIFR \ External Interrupt Flag Register
+ $F0 constant EIFR_PCIF \ Pin Change Interrupt Flags
+ $01 constant EIFR_INTF0 \ External Interrupt Flag 0
+&115 constant PCMSK3 \ Pin Change Mask Register 3
+&109 constant PCMSK2 \ Pin Change Mask Register 2
+&108 constant PCMSK1 \ Pin Change Mask Register 1
+&107 constant PCMSK0 \ Pin Change Mask Register 0
+
+\ Interrupts
+&2 constant INT0Addr \ External Interrupt Request 0
+&4 constant PCINT0Addr \ Pin Change Interrupt Request 0
+&6 constant PCINT1Addr \ Pin Change Interrupt Request 1
+&8 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
+&10 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
+&12 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+&14 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
+&16 constant TIMER1_COMPBAddr \ Timer/Counter Compare Match B
+&18 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+&20 constant TIMER0_COMPAddr \ Timer/Counter0 Compare Match
+&22 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
+&24 constant SPI__STCAddr \ SPI Serial Transfer Complete
+&26 constant USART__RXAddr \ USART, Rx Complete
+&28 constant USART__UDREAddr \ USART Data register Empty
+&30 constant USART0__TXAddr \ USART0, Tx Complete
+&32 constant USI_STARTAddr \ USI Start Condition
+&34 constant USI_OVERFLOWAddr \ USI Overflow
+&36 constant ANALOG_COMPAddr \ Analog Comparator
+&38 constant ADCAddr \ ADC Conversion Complete
+&40 constant EE_READYAddr \ EEPROM Ready
+&42 constant SPM_READYAddr \ Store Program Memory Read
+&44 constant NOT_USEDAddr \ RESERVED
+&46 constant PCINT2Addr \ Pin Change Interrupt Request 2
+&48 constant PCINT3Addr \ Pin Change Interrupt Request 3
diff --git a/amforth-6.5/avr8/devices/atmega6450p/device.asm b/amforth-6.5/avr8/devices/atmega6450p/device.asm
new file mode 100644
index 0000000..235783e
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega6450p/device.asm
@@ -0,0 +1,114 @@
+; Partname: ATmega6450P
+; generated automatically, do not edit
+
+.nolist
+ .include "m6450Pdef.inc"
+.list
+
+.equ ramstart = 256
+.equ CELLSIZE = 2
+.macro readflashcell
+ lsl zl
+ rol zh
+ lpm @0, Z+
+ lpm @1, Z+
+.endmacro
+.macro writeflashcell
+ lsl zl
+ rol zh
+.endmacro
+.set WANT_AD_CONVERTER = 0
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_SPI = 0
+.set WANT_USI = 0
+.set WANT_USART0 = 0
+.set WANT_CPU = 0
+.set WANT_JTAG = 0
+.set WANT_EEPROM = 0
+.set WANT_PORTA = 0
+.set WANT_PORTB = 0
+.set WANT_PORTC = 0
+.set WANT_PORTD = 0
+.set WANT_PORTE = 0
+.set WANT_PORTF = 0
+.set WANT_PORTG = 0
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_TIMER_COUNTER_2 = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_WATCHDOG = 0
+.set WANT_BOOT_LOAD = 0
+.set WANT_PORTH = 0
+.set WANT_PORTJ = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.equ intvecsize = 2 ; please verify; flash size: 65536 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.org 2
+ rcall isr ; External Interrupt Request 0
+.org 4
+ rcall isr ; Pin Change Interrupt Request 0
+.org 6
+ rcall isr ; Pin Change Interrupt Request 1
+.org 8
+ rcall isr ; Timer/Counter2 Compare Match
+.org 10
+ rcall isr ; Timer/Counter2 Overflow
+.org 12
+ rcall isr ; Timer/Counter1 Capture Event
+.org 14
+ rcall isr ; Timer/Counter1 Compare Match A
+.org 16
+ rcall isr ; Timer/Counter Compare Match B
+.org 18
+ rcall isr ; Timer/Counter1 Overflow
+.org 20
+ rcall isr ; Timer/Counter0 Compare Match
+.org 22
+ rcall isr ; Timer/Counter0 Overflow
+.org 24
+ rcall isr ; SPI Serial Transfer Complete
+.org 26
+ rcall isr ; USART, Rx Complete
+.org 28
+ rcall isr ; USART Data register Empty
+.org 30
+ rcall isr ; USART0, Tx Complete
+.org 32
+ rcall isr ; USI Start Condition
+.org 34
+ rcall isr ; USI Overflow
+.org 36
+ rcall isr ; Analog Comparator
+.org 38
+ rcall isr ; ADC Conversion Complete
+.org 40
+ rcall isr ; EEPROM Ready
+.org 42
+ rcall isr ; Store Program Memory Read
+.org 44
+ rcall isr ; RESERVED
+.org 46
+ rcall isr ; Pin Change Interrupt Request 2
+.org 48
+ rcall isr ; Pin Change Interrupt Request 3
+.equ INTVECTORS = 25
+.nooverlap
+
+; compatability layer (maybe empty)
+.equ EEPE = EEWE
+.equ EEMPE = EEMWE
+
+; controller data area, environment query mcu-info
+mcu_info:
+mcu_ramsize:
+ .dw 4096
+mcu_eepromsize:
+ .dw 2048
+mcu_maxdp:
+ .dw 57344
+mcu_numints:
+ .dw 25
+mcu_name:
+ .dw 11
+ .db "ATmega6450P",0
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega6450p/device.inc b/amforth-6.5/avr8/devices/atmega6450p/device.inc
new file mode 100644
index 0000000..1d056aa
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega6450p/device.inc
@@ -0,0 +1,1152 @@
+; Partname: ATmega6450P
+; generated automatically, no not edit
+
+.if WANT_AD_CONVERTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC multiplexer Selection Register
+VE_ADMUX:
+ .dw $ff05
+ .db "ADMUX",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADMUX
+XT_ADMUX:
+ .dw PFA_DOVARIABLE
+PFA_ADMUX:
+ .dw 124
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register
+VE_ADCSRA:
+ .dw $ff06
+ .db "ADCSRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRA
+XT_ADCSRA:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRA:
+ .dw 122
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register Bytes
+VE_ADC:
+ .dw $ff03
+ .db "ADC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADC
+XT_ADC:
+ .dw PFA_DOVARIABLE
+PFA_ADC:
+ .dw 120
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Control and Status Register B
+VE_ADCSRB:
+ .dw $ff06
+ .db "ADCSRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRB
+XT_ADCSRB:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRB:
+ .dw 123
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 0
+VE_DIDR0:
+ .dw $ff05
+ .db "DIDR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR0
+XT_DIDR0:
+ .dw PFA_DOVARIABLE
+PFA_DIDR0:
+ .dw 126
+
+.endif
+.if WANT_ANALOG_COMPARATOR == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Control And Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw 80
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 1
+VE_DIDR1:
+ .dw $ff05
+ .db "DIDR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR1
+XT_DIDR1:
+ .dw PFA_DOVARIABLE
+PFA_DIDR1:
+ .dw 127
+
+.endif
+.if WANT_SPI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR:
+ .dw $ff04
+ .db "SPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR
+XT_SPCR:
+ .dw PFA_DOVARIABLE
+PFA_SPCR:
+ .dw 76
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR:
+ .dw $ff04
+ .db "SPSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR
+XT_SPSR:
+ .dw PFA_DOVARIABLE
+PFA_SPSR:
+ .dw 77
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR:
+ .dw $ff04
+ .db "SPDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR
+XT_SPDR:
+ .dw PFA_DOVARIABLE
+PFA_SPDR:
+ .dw 78
+
+.endif
+.if WANT_USI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USI Data Register
+VE_USIDR:
+ .dw $ff05
+ .db "USIDR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USIDR
+XT_USIDR:
+ .dw PFA_DOVARIABLE
+PFA_USIDR:
+ .dw 186
+; ( -- addr ) System Constant
+; R( -- )
+; USI Status Register
+VE_USISR:
+ .dw $ff05
+ .db "USISR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USISR
+XT_USISR:
+ .dw PFA_DOVARIABLE
+PFA_USISR:
+ .dw 185
+; ( -- addr ) System Constant
+; R( -- )
+; USI Control Register
+VE_USICR:
+ .dw $ff05
+ .db "USICR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USICR
+XT_USICR:
+ .dw PFA_DOVARIABLE
+PFA_USICR:
+ .dw 184
+
+.endif
+.if WANT_USART0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR0:
+ .dw $ff04
+ .db "UDR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR0
+XT_UDR0:
+ .dw PFA_DOVARIABLE
+PFA_UDR0:
+ .dw 198
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR0A:
+ .dw $ff06
+ .db "UCSR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0A
+XT_UCSR0A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0A:
+ .dw 192
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR0B:
+ .dw $ff06
+ .db "UCSR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0B
+XT_UCSR0B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0B:
+ .dw 193
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR0C:
+ .dw $ff06
+ .db "UCSR0C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0C
+XT_UCSR0C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0C:
+ .dw 194
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Bytes
+VE_UBRR0:
+ .dw $ff05
+ .db "UBRR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR0
+XT_UBRR0:
+ .dw PFA_DOVARIABLE
+PFA_UBRR0:
+ .dw 196
+
+.endif
+.if WANT_CPU == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw 95
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer
+VE_SP:
+ .dw $ff02
+ .db "SP"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SP
+XT_SP:
+ .dw PFA_DOVARIABLE
+PFA_SP:
+ .dw 93
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw 85
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Status Register
+VE_MCUSR:
+ .dw $ff05
+ .db "MCUSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUSR
+XT_MCUSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUSR:
+ .dw 84
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Calibration Value
+VE_OSCCAL:
+ .dw $ff06
+ .db "OSCCAL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSCCAL
+XT_OSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_OSCCAL:
+ .dw 102
+; ( -- addr ) System Constant
+; R( -- )
+; Clock Prescale Register
+VE_CLKPR:
+ .dw $ff05
+ .db "CLKPR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKPR
+XT_CLKPR:
+ .dw PFA_DOVARIABLE
+PFA_CLKPR:
+ .dw 97
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register
+VE_PRR:
+ .dw $ff03
+ .db "PRR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR
+XT_PRR:
+ .dw PFA_DOVARIABLE
+PFA_PRR:
+ .dw 100
+; ( -- addr ) System Constant
+; R( -- )
+; Sleep Mode Control Register
+VE_SMCR:
+ .dw $ff04
+ .db "SMCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SMCR
+XT_SMCR:
+ .dw PFA_DOVARIABLE
+PFA_SMCR:
+ .dw 83
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 2
+VE_GPIOR2:
+ .dw $ff06
+ .db "GPIOR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR2
+XT_GPIOR2:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR2:
+ .dw 75
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 1
+VE_GPIOR1:
+ .dw $ff06
+ .db "GPIOR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR1
+XT_GPIOR1:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR1:
+ .dw 74
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 0
+VE_GPIOR0:
+ .dw $ff06
+ .db "GPIOR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR0
+XT_GPIOR0:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR0:
+ .dw 62
+
+.endif
+.if WANT_JTAG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; On-Chip Debug Related Register in I/O Memory
+VE_OCDR:
+ .dw $ff04
+ .db "OCDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCDR
+XT_OCDR:
+ .dw PFA_DOVARIABLE
+PFA_OCDR:
+ .dw 81
+
+.endif
+.if WANT_EEPROM == 1
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Read/Write Access Bytes
+VE_EEAR:
+ .dw $ff04
+ .db "EEAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEAR
+XT_EEAR:
+ .dw PFA_DOVARIABLE
+PFA_EEAR:
+ .dw 65
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw 64
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw 63
+
+.endif
+.if WANT_PORTA == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Register
+VE_PORTA:
+ .dw $ff05
+ .db "PORTA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTA
+XT_PORTA:
+ .dw PFA_DOVARIABLE
+PFA_PORTA:
+ .dw 34
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Direction Register
+VE_DDRA:
+ .dw $ff04
+ .db "DDRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRA
+XT_DDRA:
+ .dw PFA_DOVARIABLE
+PFA_DDRA:
+ .dw 33
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Input Pins
+VE_PINA:
+ .dw $ff04
+ .db "PINA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINA
+XT_PINA:
+ .dw PFA_DOVARIABLE
+PFA_PINA:
+ .dw 32
+
+.endif
+.if WANT_PORTB == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw 37
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw 36
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw 35
+
+.endif
+.if WANT_PORTC == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Register
+VE_PORTC:
+ .dw $ff05
+ .db "PORTC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTC
+XT_PORTC:
+ .dw PFA_DOVARIABLE
+PFA_PORTC:
+ .dw 40
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Direction Register
+VE_DDRC:
+ .dw $ff04
+ .db "DDRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRC
+XT_DDRC:
+ .dw PFA_DOVARIABLE
+PFA_DDRC:
+ .dw 39
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Input Pins
+VE_PINC:
+ .dw $ff04
+ .db "PINC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINC
+XT_PINC:
+ .dw PFA_DOVARIABLE
+PFA_PINC:
+ .dw 38
+
+.endif
+.if WANT_PORTD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw 43
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw 42
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw 41
+
+.endif
+.if WANT_PORTE == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port E
+VE_PORTE:
+ .dw $ff05
+ .db "PORTE",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTE
+XT_PORTE:
+ .dw PFA_DOVARIABLE
+PFA_PORTE:
+ .dw 46
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port E
+VE_DDRE:
+ .dw $ff04
+ .db "DDRE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRE
+XT_DDRE:
+ .dw PFA_DOVARIABLE
+PFA_DDRE:
+ .dw 45
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port E
+VE_PINE:
+ .dw $ff04
+ .db "PINE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINE
+XT_PINE:
+ .dw PFA_DOVARIABLE
+PFA_PINE:
+ .dw 44
+
+.endif
+.if WANT_PORTF == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port F
+VE_PORTF:
+ .dw $ff05
+ .db "PORTF",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTF
+XT_PORTF:
+ .dw PFA_DOVARIABLE
+PFA_PORTF:
+ .dw 49
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port F
+VE_DDRF:
+ .dw $ff04
+ .db "DDRF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRF
+XT_DDRF:
+ .dw PFA_DOVARIABLE
+PFA_DDRF:
+ .dw 48
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port F
+VE_PINF:
+ .dw $ff04
+ .db "PINF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINF
+XT_PINF:
+ .dw PFA_DOVARIABLE
+PFA_PINF:
+ .dw 47
+
+.endif
+.if WANT_PORTG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Data Register
+VE_PORTG:
+ .dw $ff05
+ .db "PORTG",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTG
+XT_PORTG:
+ .dw PFA_DOVARIABLE
+PFA_PORTG:
+ .dw 52
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Data Direction Register
+VE_DDRG:
+ .dw $ff04
+ .db "DDRG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRG
+XT_DDRG:
+ .dw PFA_DOVARIABLE
+PFA_DDRG:
+ .dw 51
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Input Pins
+VE_PING:
+ .dw $ff04
+ .db "PING"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PING
+XT_PING:
+ .dw PFA_DOVARIABLE
+PFA_PING:
+ .dw 50
+
+.endif
+.if WANT_TIMER_COUNTER_0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Control Register
+VE_TCCR0A:
+ .dw $ff06
+ .db "TCCR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0A
+XT_TCCR0A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0A:
+ .dw 68
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw 70
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0A:
+ .dw $ff05
+ .db "OCR0A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0A
+XT_OCR0A:
+ .dw PFA_DOVARIABLE
+PFA_OCR0A:
+ .dw 71
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Mask Register
+VE_TIMSK0:
+ .dw $ff06
+ .db "TIMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK0
+XT_TIMSK0:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK0:
+ .dw 110
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Flag register
+VE_TIFR0:
+ .dw $ff05
+ .db "TIFR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR0
+XT_TIFR0:
+ .dw PFA_DOVARIABLE
+PFA_TIFR0:
+ .dw 53
+; ( -- addr ) System Constant
+; R( -- )
+; General Timer/Control Register
+VE_GTCCR:
+ .dw $ff05
+ .db "GTCCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GTCCR
+XT_GTCCR:
+ .dw PFA_DOVARIABLE
+PFA_GTCCR:
+ .dw 67
+
+.endif
+.if WANT_TIMER_COUNTER_2 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register
+VE_TCCR2A:
+ .dw $ff06
+ .db "TCCR2A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2A
+XT_TCCR2A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2A:
+ .dw 176
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2
+VE_TCNT2:
+ .dw $ff05
+ .db "TCNT2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT2
+XT_TCNT2:
+ .dw PFA_DOVARIABLE
+PFA_TCNT2:
+ .dw 178
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register
+VE_OCR2A:
+ .dw $ff05
+ .db "OCR2A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2A
+XT_OCR2A:
+ .dw PFA_DOVARIABLE
+PFA_OCR2A:
+ .dw 179
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Interrupt Mask register
+VE_TIMSK2:
+ .dw $ff06
+ .db "TIMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK2
+XT_TIMSK2:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK2:
+ .dw 112
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Interrupt Flag Register
+VE_TIFR2:
+ .dw $ff05
+ .db "TIFR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR2
+XT_TIFR2:
+ .dw PFA_DOVARIABLE
+PFA_TIFR2:
+ .dw 55
+; ( -- addr ) System Constant
+; R( -- )
+; Asynchronous Status Register
+VE_ASSR:
+ .dw $ff04
+ .db "ASSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ASSR
+XT_ASSR:
+ .dw PFA_DOVARIABLE
+PFA_ASSR:
+ .dw 182
+
+.endif
+.if WANT_TIMER_COUNTER_1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw 128
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw 129
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter 1 Control Register C
+VE_TCCR1C:
+ .dw $ff06
+ .db "TCCR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1C
+XT_TCCR1C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1C:
+ .dw 130
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Bytes
+VE_TCNT1:
+ .dw $ff05
+ .db "TCNT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1
+XT_TCNT1:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1:
+ .dw 132
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register A Bytes
+VE_OCR1A:
+ .dw $ff05
+ .db "OCR1A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1A
+XT_OCR1A:
+ .dw PFA_DOVARIABLE
+PFA_OCR1A:
+ .dw 136
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register B Bytes
+VE_OCR1B:
+ .dw $ff05
+ .db "OCR1B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1B
+XT_OCR1B:
+ .dw PFA_DOVARIABLE
+PFA_OCR1B:
+ .dw 138
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Bytes
+VE_ICR1:
+ .dw $ff04
+ .db "ICR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1
+XT_ICR1:
+ .dw PFA_DOVARIABLE
+PFA_ICR1:
+ .dw 134
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Mask Register
+VE_TIMSK1:
+ .dw $ff06
+ .db "TIMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK1
+XT_TIMSK1:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK1:
+ .dw 111
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Flag register
+VE_TIFR1:
+ .dw $ff05
+ .db "TIFR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR1
+XT_TIFR1:
+ .dw PFA_DOVARIABLE
+PFA_TIFR1:
+ .dw 54
+
+.endif
+.if WANT_WATCHDOG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCR:
+ .dw $ff05
+ .db "WDTCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCR
+XT_WDTCR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCR:
+ .dw 96
+
+.endif
+.if WANT_BOOT_LOAD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control Register
+VE_SPMCSR:
+ .dw $ff06
+ .db "SPMCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCSR
+XT_SPMCSR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCSR:
+ .dw 87
+
+.endif
+.if WANT_PORTH == 1
+; ( -- addr ) System Constant
+; R( -- )
+; PORT H Data Register
+VE_PORTH:
+ .dw $ff05
+ .db "PORTH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTH
+XT_PORTH:
+ .dw PFA_DOVARIABLE
+PFA_PORTH:
+ .dw 218
+; ( -- addr ) System Constant
+; R( -- )
+; PORT H Data Direction Register
+VE_DDRH:
+ .dw $ff04
+ .db "DDRH"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRH
+XT_DDRH:
+ .dw PFA_DOVARIABLE
+PFA_DDRH:
+ .dw 217
+; ( -- addr ) System Constant
+; R( -- )
+; PORT H Input Pins
+VE_PINH:
+ .dw $ff04
+ .db "PINH"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINH
+XT_PINH:
+ .dw PFA_DOVARIABLE
+PFA_PINH:
+ .dw 216
+
+.endif
+.if WANT_PORTJ == 1
+; ( -- addr ) System Constant
+; R( -- )
+; PORT J Data Register
+VE_PORTJ:
+ .dw $ff05
+ .db "PORTJ",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTJ
+XT_PORTJ:
+ .dw PFA_DOVARIABLE
+PFA_PORTJ:
+ .dw 221
+; ( -- addr ) System Constant
+; R( -- )
+; PORT J Data Direction Register
+VE_DDRJ:
+ .dw $ff04
+ .db "DDRJ"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRJ
+XT_DDRJ:
+ .dw PFA_DOVARIABLE
+PFA_DDRJ:
+ .dw 220
+; ( -- addr ) System Constant
+; R( -- )
+; PORT J Input Pins
+VE_PINJ:
+ .dw $ff04
+ .db "PINJ"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINJ
+XT_PINJ:
+ .dw PFA_DOVARIABLE
+PFA_PINJ:
+ .dw 219
+
+.endif
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register A
+VE_EICRA:
+ .dw $ff05
+ .db "EICRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRA
+XT_EICRA:
+ .dw PFA_DOVARIABLE
+PFA_EICRA:
+ .dw 105
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Mask Register
+VE_EIMSK:
+ .dw $ff05
+ .db "EIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIMSK
+XT_EIMSK:
+ .dw PFA_DOVARIABLE
+PFA_EIMSK:
+ .dw 61
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Flag Register
+VE_EIFR:
+ .dw $ff04
+ .db "EIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIFR
+XT_EIFR:
+ .dw PFA_DOVARIABLE
+PFA_EIFR:
+ .dw 60
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 3
+VE_PCMSK3:
+ .dw $ff06
+ .db "PCMSK3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK3
+XT_PCMSK3:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK3:
+ .dw 115
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 2
+VE_PCMSK2:
+ .dw $ff06
+ .db "PCMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK2
+XT_PCMSK2:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK2:
+ .dw 109
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 1
+VE_PCMSK1:
+ .dw $ff06
+ .db "PCMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK1
+XT_PCMSK1:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK1:
+ .dw 108
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 0
+VE_PCMSK0:
+ .dw $ff06
+ .db "PCMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK0
+XT_PCMSK0:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK0:
+ .dw 107
+
+.endif
diff --git a/amforth-6.5/avr8/devices/atmega6450p/device.py b/amforth-6.5/avr8/devices/atmega6450p/device.py
new file mode 100644
index 0000000..d034f86
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega6450p/device.py
@@ -0,0 +1,333 @@
+# Generated Automatically
+
+# Partname ATmega6450P
+
+MCUREGS = {
+# Interrupt Vectors
+ 'INT0Addr' : '#2', # External Interrupt Request 0
+ 'PCINT0Addr' : '#4', # Pin Change Interrupt Request 0
+ 'PCINT1Addr' : '#6', # Pin Change Interrupt Request 1
+ 'TIMER2_COMPAddr' : '#8', # Timer/Counter2 Compare Match
+ 'TIMER2_OVFAddr' : '#10', # Timer/Counter2 Overflow
+ 'TIMER1_CAPTAddr' : '#12', # Timer/Counter1 Capture Event
+ 'TIMER1_COMPAAddr' : '#14', # Timer/Counter1 Compare Match A
+ 'TIMER1_COMPBAddr' : '#16', # Timer/Counter Compare Match B
+ 'TIMER1_OVFAddr' : '#18', # Timer/Counter1 Overflow
+ 'TIMER0_COMPAddr' : '#20', # Timer/Counter0 Compare Match
+ 'TIMER0_OVFAddr' : '#22', # Timer/Counter0 Overflow
+ 'SPI_STCAddr' : '#24', # SPI Serial Transfer Complete
+ 'USART_RXAddr' : '#26', # USART, Rx Complete
+ 'USART_UDREAddr' : '#28', # USART Data register Empty
+ 'USART0_TXAddr' : '#30', # USART0, Tx Complete
+ 'USI_STARTAddr' : '#32', # USI Start Condition
+ 'USI_OVERFLOWAddr' : '#34', # USI Overflow
+ 'ANALOG_COMPAddr' : '#36', # Analog Comparator
+ 'ADCAddr' : '#38', # ADC Conversion Complete
+ 'EE_READYAddr' : '#40', # EEPROM Ready
+ 'SPM_READYAddr' : '#42', # Store Program Memory Read
+ 'NOT_USEDAddr' : '#44', # RESERVED
+ 'PCINT2Addr' : '#46', # Pin Change Interrupt Request 2
+ 'PCINT3Addr' : '#48', # Pin Change Interrupt Request 3
+
+# Module AD_CONVERTER
+ 'ADMUX' : '$7c', # The ADC multiplexer Selection
+ 'ADMUX_REFS': '$c0', # Reference Selection Bits
+ 'ADMUX_ADLAR': '$20', # Left Adjust Result
+ 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
+ 'ADCSRA' : '$7a', # The ADC Control and Status reg
+ 'ADCSRA_ADEN': '$80', # ADC Enable
+ 'ADCSRA_ADSC': '$40', # ADC Start Conversion
+ 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
+ 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
+ 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
+ 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
+ 'ADC' : '$78', # ADC Data Register Bytes
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Sources
+ 'DIDR0' : '$7e', # Digital Input Disable Register
+ 'DIDR0_ADC7D': '$80', # ADC7 Digital input Disable
+ 'DIDR0_ADC6D': '$40', # ADC6 Digital input Disable
+ 'DIDR0_ADC5D': '$20', # ADC5 Digital input Disable
+ 'DIDR0_ADC4D': '$10', # ADC4 Digital input Disable
+ 'DIDR0_ADC3D': '$8', # ADC3 Digital input Disable
+ 'DIDR0_ADC2D': '$4', # ADC2 Digital input Disable
+ 'DIDR0_ADC1D': '$2', # ADC1 Digital input Disable
+ 'DIDR0_ADC0D': '$1', # ADC0 Digital input Disable
+
+# Module ANALOG_COMPARATOR
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
+ 'ACSR' : '$50', # Analog Comparator Control And
+ 'ACSR_ACD': '$80', # Analog Comparator Disable
+ 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
+ 'ACSR_ACO': '$20', # Analog Compare Output
+ 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
+ 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
+ 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
+ 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
+ 'DIDR1' : '$7f', # Digital Input Disable Register
+ 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
+ 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
+
+# Module SPI
+ 'SPCR' : '$4c', # SPI Control Register
+ 'SPCR_SPIE': '$80', # SPI Interrupt Enable
+ 'SPCR_SPE': '$40', # SPI Enable
+ 'SPCR_DORD': '$20', # Data Order
+ 'SPCR_MSTR': '$10', # Master/Slave Select
+ 'SPCR_CPOL': '$8', # Clock polarity
+ 'SPCR_CPHA': '$4', # Clock Phase
+ 'SPCR_SPR': '$3', # SPI Clock Rate Selects
+ 'SPSR' : '$4d', # SPI Status Register
+ 'SPSR_SPIF': '$80', # SPI Interrupt Flag
+ 'SPSR_WCOL': '$40', # Write Collision Flag
+ 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
+ 'SPDR' : '$4e', # SPI Data Register
+
+# Module USI
+ 'USIDR' : '$ba', # USI Data Register
+ 'USISR' : '$b9', # USI Status Register
+ 'USISR_USISIF': '$80', # Start Condition Interrupt Flag
+ 'USISR_USIOIF': '$40', # Counter Overflow Interrupt Fla
+ 'USISR_USIPF': '$20', # Stop Condition Flag
+ 'USISR_USIDC': '$10', # Data Output Collision
+ 'USISR_USICNT': '$f', # USI Counter Value Bits
+ 'USICR' : '$b8', # USI Control Register
+ 'USICR_USISIE': '$80', # Start Condition Interrupt Enab
+ 'USICR_USIOIE': '$40', # Counter Overflow Interrupt Ena
+ 'USICR_USIWM': '$30', # USI Wire Mode Bits
+ 'USICR_USICS': '$c', # USI Clock Source Select Bits
+ 'USICR_USICLK': '$2', # Clock Strobe
+ 'USICR_USITC': '$1', # Toggle Clock Port Pin
+
+# Module USART0
+ 'UDR0' : '$c6', # USART I/O Data Register
+ 'UCSR0A' : '$c0', # USART Control and Status Regis
+ 'UCSR0A_RXC0': '$80', # USART Receive Complete
+ 'UCSR0A_TXC0': '$40', # USART Transmit Complete
+ 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
+ 'UCSR0A_FE0': '$10', # Framing Error
+ 'UCSR0A_DOR0': '$8', # Data OverRun
+ 'UCSR0A_UPE0': '$4', # USART Parity Error
+ 'UCSR0A_U2X0': '$2', # Double the USART Transmission
+ 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
+ 'UCSR0B' : '$c1', # USART Control and Status Regis
+ 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
+ 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
+ 'UCSR0B_UDRIE0': '$20', # USART Data Register Empty Inte
+ 'UCSR0B_RXEN0': '$10', # Receiver Enable
+ 'UCSR0B_TXEN0': '$8', # Transmitter Enable
+ 'UCSR0B_UCSZ02': '$4', # Character Size
+ 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
+ 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
+ 'UCSR0C' : '$c2', # USART Control and Status Regis
+ 'UCSR0C_UMSEL0': '$40', # USART Mode Select
+ 'UCSR0C_UPM0': '$30', # Parity Mode Bits
+ 'UCSR0C_USBS0': '$8', # Stop Bit Select
+ 'UCSR0C_UCSZ0': '$6', # Character Size
+ 'UCSR0C_UCPOL0': '$1', # Clock Polarity
+ 'UBRR0' : '$c4', # USART Baud Rate Register Byte
+
+# Module CPU
+ 'SREG' : '$5f', # Status Register
+ 'SREG_I': '$80', # Global Interrupt Enable
+ 'SREG_T': '$40', # Bit Copy Storage
+ 'SREG_H': '$20', # Half Carry Flag
+ 'SREG_S': '$10', # Sign Bit
+ 'SREG_V': '$8', # Two's Complement Overflow Flag
+ 'SREG_N': '$4', # Negative Flag
+ 'SREG_Z': '$2', # Zero Flag
+ 'SREG_C': '$1', # Carry Flag
+ 'SP' : '$5d', # Stack Pointer
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_PUD': '$10', # Pull-up disable
+ 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
+ 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+ 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
+ 'MCUSR_BORF': '$4', # Brown-out Reset Flag
+ 'MCUSR_EXTRF': '$2', # External Reset Flag
+ 'MCUSR_PORF': '$1', # Power-on reset flag
+ 'OSCCAL' : '$66', # Oscillator Calibration Value
+ 'CLKPR' : '$61', # Clock Prescale Register
+ 'CLKPR_CLKPCE': '$80', # Clock Prescaler Change Enable
+ 'CLKPR_CLKPS': '$f', # Clock Prescaler Select Bits
+ 'PRR' : '$64', # Power Reduction Register
+ 'PRR_PRLCD': '$10', # Power Reduction LCD
+ 'PRR_PRTIM1': '$8', # Power Reduction Timer/Counter1
+ 'PRR_PRSPI': '$4', # Power Reduction Serial Periphe
+ 'PRR_PRUSART0': '$2', # Power Reduction USART
+ 'PRR_PRADC': '$1', # Power Reduction ADC
+ 'SMCR' : '$53', # Sleep Mode Control Register
+ 'SMCR_SM': '$e', # Sleep Mode Select bits
+ 'SMCR_SE': '$1', # Sleep Enable
+ 'GPIOR2' : '$4b', # General Purpose IO Register 2
+ 'GPIOR1' : '$4a', # General Purpose IO Register 1
+ 'GPIOR0' : '$3e', # General Purpose IO Register 0
+
+# Module JTAG
+ 'OCDR' : '$51', # On-Chip Debug Related Register
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_JTD': '$80', # JTAG Interface Disable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+
+# Module EEPROM
+ 'EEAR' : '$41', # EEPROM Read/Write Access Byte
+ 'EEDR' : '$40', # EEPROM Data Register
+ 'EECR' : '$3f', # EEPROM Control Register
+ 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
+ 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
+ 'EECR_EEWE': '$2', # EEPROM Write Enable
+ 'EECR_EERE': '$1', # EEPROM Read Enable
+
+# Module PORTA
+ 'PORTA' : '$22', # Port A Data Register
+ 'DDRA' : '$21', # Port A Data Direction Register
+ 'PINA' : '$20', # Port A Input Pins
+
+# Module PORTB
+ 'PORTB' : '$25', # Port B Data Register
+ 'DDRB' : '$24', # Port B Data Direction Register
+ 'PINB' : '$23', # Port B Input Pins
+
+# Module PORTC
+ 'PORTC' : '$28', # Port C Data Register
+ 'DDRC' : '$27', # Port C Data Direction Register
+ 'PINC' : '$26', # Port C Input Pins
+
+# Module PORTD
+ 'PORTD' : '$2b', # Port D Data Register
+ 'DDRD' : '$2a', # Port D Data Direction Register
+ 'PIND' : '$29', # Port D Input Pins
+
+# Module PORTE
+ 'PORTE' : '$2e', # Data Register, Port E
+ 'DDRE' : '$2d', # Data Direction Register, Port
+ 'PINE' : '$2c', # Input Pins, Port E
+
+# Module PORTF
+ 'PORTF' : '$31', # Data Register, Port F
+ 'DDRF' : '$30', # Data Direction Register, Port
+ 'PINF' : '$2f', # Input Pins, Port F
+
+# Module PORTG
+ 'PORTG' : '$34', # Port G Data Register
+ 'DDRG' : '$33', # Port G Data Direction Register
+ 'PING' : '$32', # Port G Input Pins
+
+# Module TIMER_COUNTER_0
+ 'TCCR0A' : '$44', # Timer/Counter0 Control Registe
+ 'TCCR0A_FOC0A': '$80', # Force Output Compare
+ 'TCCR0A_WGM00': '$40', # Waveform Generation Mode 0
+ 'TCCR0A_COM0A': '$30', # Compare Match Output Modes
+ 'TCCR0A_WGM01': '$8', # Waveform Generation Mode 1
+ 'TCCR0A_CS0': '$7', # Clock Selects
+ 'TCNT0' : '$46', # Timer/Counter0
+ 'OCR0A' : '$47', # Timer/Counter0 Output Compare
+ 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
+ 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
+ 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
+ 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
+ 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
+ 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Control Register
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSR310': '$1', # Prescaler Reset Timer/Counter1
+
+# Module TIMER_COUNTER_2
+ 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
+ 'TCCR2A_FOC2A': '$80', # Force Output Compare A
+ 'TCCR2A_WGM20': '$40', # Waveform Generation Mode
+ 'TCCR2A_COM2A': '$30', # Compare Output Mode bits
+ 'TCCR2A_WGM21': '$8', # Waveform Generation Mode
+ 'TCCR2A_CS2': '$7', # Clock Select bits
+ 'TCNT2' : '$b2', # Timer/Counter2
+ 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
+ 'TIMSK2' : '$70', # Timer/Counter2 Interrupt Mask
+ 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
+ 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
+ 'TIFR2' : '$37', # Timer/Counter2 Interrupt Flag
+ 'TIFR2_OCF2A': '$2', # Timer/Counter2 Output Compare
+ 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_PSR2': '$2', # Prescaler Reset Timer/Counter2
+ 'ASSR' : '$b6', # Asynchronous Status Register
+ 'ASSR_EXCLK': '$10', # Enable External Clock Interrup
+ 'ASSR_AS2': '$8', # AS2: Asynchronous Timer/Counte
+ 'ASSR_TCN2UB': '$4', # TCN2UB: Timer/Counter2 Update
+ 'ASSR_OCR2UB': '$2', # Output Compare Register2 Updat
+ 'ASSR_TCR2UB': '$1', # TCR2UB: Timer/Counter Control
+
+# Module TIMER_COUNTER_1
+ 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
+ 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
+ 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
+ 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
+ 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
+ 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
+ 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
+ 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
+ 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
+ 'TCCR1C' : '$82', # Timer/Counter 1 Control Regist
+ 'TCCR1C_FOC1A': '$80', # Force Output Compare 1A
+ 'TCCR1C_FOC1B': '$40', # Force Output Compare 1B
+ 'TCNT1' : '$84', # Timer/Counter1 Bytes
+ 'OCR1A' : '$88', # Timer/Counter1 Output Compare
+ 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
+ 'ICR1' : '$86', # Timer/Counter1 Input Capture R
+ 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
+ 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
+ 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
+ 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
+ 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
+ 'TIFR1' : '$36', # Timer/Counter1 Interrupt Flag
+ 'TIFR1_ICF1': '$20', # Input Capture Flag 1
+ 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
+ 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
+ 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
+
+# Module WATCHDOG
+ 'WDTCR' : '$60', # Watchdog Timer Control Registe
+ 'WDTCR_WDCE': '$10', # Watchdog Change Enable
+ 'WDTCR_WDE': '$8', # Watch Dog Enable
+ 'WDTCR_WDP': '$7', # Watch Dog Timer Prescaler bits
+
+# Module BOOT_LOAD
+ 'SPMCSR' : '$57', # Store Program Memory Control R
+ 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
+ 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
+ 'SPMCSR_RWWSRE': '$10', # Read While Write section read
+ 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
+ 'SPMCSR_PGWRT': '$4', # Page Write
+ 'SPMCSR_PGERS': '$2', # Page Erase
+ 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
+
+# Module PORTH
+ 'PORTH' : '$da', # PORT H Data Register
+ 'DDRH' : '$d9', # PORT H Data Direction Register
+ 'PINH' : '$d8', # PORT H Input Pins
+
+# Module PORTJ
+ 'PORTJ' : '$dd', # PORT J Data Register
+ 'DDRJ' : '$dc', # PORT J Data Direction Register
+ 'PINJ' : '$db', # PORT J Input Pins
+
+# Module EXTERNAL_INTERRUPT
+ 'EICRA' : '$69', # External Interrupt Control Reg
+ 'EICRA_ISC01': '$2', # External Interrupt Sense Contr
+ 'EICRA_ISC00': '$1', # External Interrupt Sense Contr
+ 'EIMSK' : '$3d', # External Interrupt Mask Regist
+ 'EIMSK_PCIE': '$f0', # Pin Change Interrupt Enables
+ 'EIMSK_INT0': '$1', # External Interrupt Request 0 E
+ 'EIFR' : '$3c', # External Interrupt Flag Regist
+ 'EIFR_PCIF': '$f0', # Pin Change Interrupt Flags
+ 'EIFR_INTF0': '$1', # External Interrupt Flag 0
+ 'PCMSK3' : '$73', # Pin Change Mask Register 3
+ 'PCMSK2' : '$6d', # Pin Change Mask Register 2
+ 'PCMSK1' : '$6c', # Pin Change Mask Register 1
+ 'PCMSK0' : '$6b', # Pin Change Mask Register 0
+
+ '__amforth_dummy':'0'
+}
diff --git a/amforth-6.5/avr8/devices/atmega6450p/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega6450p/words/no-jtag.asm
new file mode 100644
index 0000000..352a4bb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega6450p/words/no-jtag.asm
@@ -0,0 +1,14 @@
+; ( -- )
+; ( -- )
+; MCU
+; disable jtag at runtime
+VE_NOJTAG:
+ .dw $FF05
+ .db "-jtag",0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOJTAG
+XT_NOJTAG:
+ .dw PFA_NOJTAG
+PFA_NOJTAG:
+
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega6450p/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega6450p/words/no-wdt.asm
new file mode 100644
index 0000000..4a12261
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega6450p/words/no-wdt.asm
@@ -0,0 +1,22 @@
+; ( -- )
+; MCU
+; disable watch dog timer at runtime
+VE_NOWDT:
+ .dw $ff04
+ .db "-wdt"
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOWDT
+XT_NOWDT:
+ .dw PFA_NOWDT
+PFA_NOWDT:
+
+; Reset WDT
+ wdr
+; Write logical one to WDTOE and WDE
+ in_ temp1, WDTCR
+ ori temp1, (1<<WDTOE)|(1<<WDE)
+ out WDTCR, temp1
+; Turn off WDT
+ ldi temp1, (0<<WDE)
+ out_ WDTCR, temp1
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega6450p/words/sleep.asm b/amforth-6.5/avr8/devices/atmega6450p/words/sleep.asm
new file mode 100644
index 0000000..256249c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega6450p/words/sleep.asm
@@ -0,0 +1,19 @@
+; ( mode -- )
+; MCU
+; put the controller into the specified sleep mode
+VE_SLEEP:
+ .dw $ff05
+ .db "sleep", 0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_SLEEP
+XT_SLEEP:
+ .dw PFA_SLEEP
+PFA_SLEEP:
+ andi tosl, 7 ; leave only legal mode bits
+ lsl tosl ; move to correct location (bits 3-1)
+ ori tosl, 1 ; set the SE bit
+ out_ SMCR, tosl ; set the sleep config
+ sleep ; nighty-night
+ out_ SMCR, zerol ; 0 protects against accidental sleeps
+ loadtos ; pop argument from stack
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega645a/atmega645a.frt b/amforth-6.5/avr8/devices/atmega645a/atmega645a.frt
new file mode 100644
index 0000000..de54e91
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega645a/atmega645a.frt
@@ -0,0 +1,285 @@
+\ Partname: ATmega645A
+\ generated automatically
+
+\ AD_CONVERTER
+&124 constant ADMUX \ The ADC multiplexer Selection Register
+ $C0 constant ADMUX_REFS \ Reference Selection Bits
+ $20 constant ADMUX_ADLAR \ Left Adjust Result
+ $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
+&122 constant ADCSRA \ The ADC Control and Status register
+ $80 constant ADCSRA_ADEN \ ADC Enable
+ $40 constant ADCSRA_ADSC \ ADC Start Conversion
+ $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
+ $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
+ $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
+ $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
+&120 constant ADC \ ADC Data Register Bytes
+&123 constant ADCSRB \ ADC Control and Status Register B
+ $07 constant ADCSRB_ADTS \ ADC Auto Trigger Sources
+&126 constant DIDR0 \ Digital Input Disable Register 0
+ $80 constant DIDR0_ADC7D \ ADC7 Digital input Disable
+ $40 constant DIDR0_ADC6D \ ADC6 Digital input Disable
+ $20 constant DIDR0_ADC5D \ ADC5 Digital input Disable
+ $10 constant DIDR0_ADC4D \ ADC4 Digital input Disable
+ $08 constant DIDR0_ADC3D \ ADC3 Digital input Disable
+ $04 constant DIDR0_ADC2D \ ADC2 Digital input Disable
+ $02 constant DIDR0_ADC1D \ ADC1 Digital input Disable
+ $01 constant DIDR0_ADC0D \ ADC0 Digital input Disable
+\ ANALOG_COMPARATOR
+&80 constant ACSR \ Analog Comparator Control And Status Register
+ $80 constant ACSR_ACD \ Analog Comparator Disable
+ $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
+ $20 constant ACSR_ACO \ Analog Compare Output
+ $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
+ $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
+ $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
+ $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
+&127 constant DIDR1 \ Digital Input Disable Register 1
+ $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
+ $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
+\ SPI
+&76 constant SPCR \ SPI Control Register
+ $80 constant SPCR_SPIE \ SPI Interrupt Enable
+ $40 constant SPCR_SPE \ SPI Enable
+ $20 constant SPCR_DORD \ Data Order
+ $10 constant SPCR_MSTR \ Master/Slave Select
+ $08 constant SPCR_CPOL \ Clock polarity
+ $04 constant SPCR_CPHA \ Clock Phase
+ $03 constant SPCR_SPR \ SPI Clock Rate Selects
+&77 constant SPSR \ SPI Status Register
+ $80 constant SPSR_SPIF \ SPI Interrupt Flag
+ $40 constant SPSR_WCOL \ Write Collision Flag
+ $01 constant SPSR_SPI2X \ Double SPI Speed Bit
+&78 constant SPDR \ SPI Data Register
+\ USI
+&186 constant USIDR \ USI Data Register
+&185 constant USISR \ USI Status Register
+ $80 constant USISR_USISIF \ Start Condition Interrupt Flag
+ $40 constant USISR_USIOIF \ Counter Overflow Interrupt Flag
+ $20 constant USISR_USIPF \ Stop Condition Flag
+ $10 constant USISR_USIDC \ Data Output Collision
+ $0F constant USISR_USICNT \ USI Counter Value Bits
+&184 constant USICR \ USI Control Register
+ $80 constant USICR_USISIE \ Start Condition Interrupt Enable
+ $40 constant USICR_USIOIE \ Counter Overflow Interrupt Enable
+ $30 constant USICR_USIWM \ USI Wire Mode Bits
+ $0C constant USICR_USICS \ USI Clock Source Select Bits
+ $02 constant USICR_USICLK \ Clock Strobe
+ $01 constant USICR_USITC \ Toggle Clock Port Pin
+\ CPU
+&95 constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ $08 constant SREG_V \ Two's Complement Overflow Flag
+ $04 constant SREG_N \ Negative Flag
+ $02 constant SREG_Z \ Zero Flag
+ $01 constant SREG_C \ Carry Flag
+&93 constant SP \ Stack Pointer
+&85 constant MCUCR \ MCU Control Register
+ $10 constant MCUCR_PUD \ Pull-up disable
+ $02 constant MCUCR_IVSEL \ Interrupt Vector Select
+ $01 constant MCUCR_IVCE \ Interrupt Vector Change Enable
+&84 constant MCUSR \ MCU Status Register
+ $10 constant MCUSR_JTRF \ JTAG Reset Flag
+ $08 constant MCUSR_WDRF \ Watchdog Reset Flag
+ $04 constant MCUSR_BORF \ Brown-out Reset Flag
+ $02 constant MCUSR_EXTRF \ External Reset Flag
+ $01 constant MCUSR_PORF \ Power-on reset flag
+&102 constant OSCCAL \ Oscillator Calibration Value
+&97 constant CLKPR \ Clock Prescale Register
+ $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable
+ $0F constant CLKPR_CLKPS \ Clock Prescaler Select Bits
+&100 constant PRR \ Power Reduction Register
+ $10 constant PRR_PRLCD \ Power Reduction LCD
+ $08 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
+ $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
+ $02 constant PRR_PRUSART0 \ Power Reduction USART
+ $01 constant PRR_PRADC \ Power Reduction ADC
+&83 constant SMCR \ Sleep Mode Control Register
+ $0E constant SMCR_SM \ Sleep Mode Select bits
+ $01 constant SMCR_SE \ Sleep Enable
+&75 constant GPIOR2 \ General Purpose IO Register 2
+&74 constant GPIOR1 \ General Purpose IO Register 1
+&62 constant GPIOR0 \ General Purpose IO Register 0
+\ JTAG
+&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
+\ EXTERNAL_INTERRUPT
+&105 constant EICRA \ External Interrupt Control Register A
+ $02 constant EICRA_ISC01 \ External Interrupt Sense Control 0 Bit 1
+ $01 constant EICRA_ISC00 \ External Interrupt Sense Control 0 Bit 0
+&61 constant EIMSK \ External Interrupt Mask Register
+ $F0 constant EIMSK_PCIE \ Pin Change Interrupt Enables
+ $01 constant EIMSK_INT0 \ External Interrupt Request 0 Enable
+&60 constant EIFR \ External Interrupt Flag Register
+ $F0 constant EIFR_PCIF \ Pin Change Interrupt Flags
+ $01 constant EIFR_INTF0 \ External Interrupt Flag 0
+&108 constant PCMSK1 \ Pin Change Mask Register 1
+&107 constant PCMSK0 \ Pin Change Mask Register 0
+\ EEPROM
+&65 constant EEAR \ EEPROM Read/Write Access Bytes
+&64 constant EEDR \ EEPROM Data Register
+&63 constant EECR \ EEPROM Control Register
+ $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
+ $04 constant EECR_EEMWE \ EEPROM Master Write Enable
+ $02 constant EECR_EEWE \ EEPROM Write Enable
+ $01 constant EECR_EERE \ EEPROM Read Enable
+\ PORTA
+&34 constant PORTA \ Port A Data Register
+&33 constant DDRA \ Port A Data Direction Register
+&32 constant PINA \ Port A Input Pins
+\ PORTB
+&37 constant PORTB \ Port B Data Register
+&36 constant DDRB \ Port B Data Direction Register
+&35 constant PINB \ Port B Input Pins
+\ PORTC
+&40 constant PORTC \ Port C Data Register
+&39 constant DDRC \ Port C Data Direction Register
+&38 constant PINC \ Port C Input Pins
+\ PORTD
+&43 constant PORTD \ Port D Data Register
+&42 constant DDRD \ Port D Data Direction Register
+&41 constant PIND \ Port D Input Pins
+\ PORTE
+&46 constant PORTE \ Data Register, Port E
+&45 constant DDRE \ Data Direction Register, Port E
+&44 constant PINE \ Input Pins, Port E
+\ PORTF
+&49 constant PORTF \ Data Register, Port F
+&48 constant DDRF \ Data Direction Register, Port F
+&47 constant PINF \ Input Pins, Port F
+\ PORTG
+&52 constant PORTG \ Port G Data Register
+&51 constant DDRG \ Port G Data Direction Register
+&50 constant PING \ Port G Input Pins
+\ TIMER_COUNTER_0
+&68 constant TCCR0A \ Timer/Counter0 Control Register
+ $80 constant TCCR0A_FOC0A \ Force Output Compare
+ $40 constant TCCR0A_WGM00 \ Waveform Generation Mode 0
+ $30 constant TCCR0A_COM0A \ Compare Match Output Modes
+ $08 constant TCCR0A_WGM01 \ Waveform Generation Mode 1
+ $07 constant TCCR0A_CS0 \ Clock Selects
+&70 constant TCNT0 \ Timer/Counter0
+&71 constant OCR0A \ Timer/Counter0 Output Compare Register
+&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
+ $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match Interrupt Enable
+ $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
+&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
+ $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0
+ $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
+&67 constant GTCCR \ General Timer/Control Register
+ $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
+ $01 constant GTCCR_PSR310 \ Prescaler Reset Timer/Counter1 and Timer/Counter0
+\ TIMER_COUNTER_2
+&176 constant TCCR2A \ Timer/Counter2 Control Register
+ $80 constant TCCR2A_FOC2A \ Force Output Compare A
+ $40 constant TCCR2A_WGM20 \ Waveform Generation Mode
+ $30 constant TCCR2A_COM2A \ Compare Output Mode bits
+ $08 constant TCCR2A_WGM21 \ Waveform Generation Mode
+ $07 constant TCCR2A_CS2 \ Clock Select bits
+&178 constant TCNT2 \ Timer/Counter2
+&179 constant OCR2A \ Timer/Counter2 Output Compare Register
+&112 constant TIMSK2 \ Timer/Counter2 Interrupt Mask register
+ $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match Interrupt Enable
+ $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
+&55 constant TIFR2 \ Timer/Counter2 Interrupt Flag Register
+ $02 constant TIFR2_OCF2A \ Timer/Counter2 Output Compare Flag 2
+ $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
+&182 constant ASSR \ Asynchronous Status Register
+ $10 constant ASSR_EXCLK \ Enable External Clock Interrupt
+ $08 constant ASSR_AS2 \ AS2: Asynchronous Timer/Counter2
+ $04 constant ASSR_TCN2UB \ TCN2UB: Timer/Counter2 Update Busy
+ $02 constant ASSR_OCR2UB \ Output Compare Register2 Update Busy
+ $01 constant ASSR_TCR2UB \ TCR2UB: Timer/Counter Control Register2 Update Busy
+\ TIMER_COUNTER_1
+&128 constant TCCR1A \ Timer/Counter1 Control Register A
+ $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
+ $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
+ $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
+&129 constant TCCR1B \ Timer/Counter1 Control Register B
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
+ $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
+&130 constant TCCR1C \ Timer/Counter 1 Control Register C
+ $80 constant TCCR1C_FOC1A \ Force Output Compare 1A
+ $40 constant TCCR1C_FOC1B \ Force Output Compare 1B
+&132 constant TCNT1 \ Timer/Counter1 Bytes
+&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
+&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
+&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
+&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
+ $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
+ $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
+ $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
+ $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
+&54 constant TIFR1 \ Timer/Counter1 Interrupt Flag register
+ $20 constant TIFR1_ICF1 \ Input Capture Flag 1
+ $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
+ $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
+ $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
+\ WATCHDOG
+&96 constant WDTCR \ Watchdog Timer Control Register
+ $10 constant WDTCR_WDCE \ Watchdog Change Enable
+ $08 constant WDTCR_WDE \ Watch Dog Enable
+ $07 constant WDTCR_WDP \ Watch Dog Timer Prescaler bits
+\ BOOT_LOAD
+&87 constant SPMCSR \ Store Program Memory Control Register
+ $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
+ $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
+ $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
+ $04 constant SPMCSR_PGWRT \ Page Write
+ $02 constant SPMCSR_PGERS \ Page Erase
+ $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
+\ USART0
+&198 constant UDR0 \ USART I/O Data Register
+&192 constant UCSR0A \ USART Control and Status Register A
+ $80 constant UCSR0A_RXC0 \ USART Receive Complete
+ $40 constant UCSR0A_TXC0 \ USART Transmit Complete
+ $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
+ $10 constant UCSR0A_FE0 \ Framing Error
+ $08 constant UCSR0A_DOR0 \ Data OverRun
+ $04 constant UCSR0A_UPE0 \ USART Parity Error
+ $02 constant UCSR0A_U2X0 \ Double the USART Transmission Speed
+ $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
+&193 constant UCSR0B \ USART Control and Status Register B
+ $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
+ $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
+ $20 constant UCSR0B_UDRIE0 \ USART Data Register Empty Interrupt Enable
+ $10 constant UCSR0B_RXEN0 \ Receiver Enable
+ $08 constant UCSR0B_TXEN0 \ Transmitter Enable
+ $04 constant UCSR0B_UCSZ02 \ Character Size
+ $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
+ $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
+&194 constant UCSR0C \ USART Control and Status Register C
+ $40 constant UCSR0C_UMSEL0 \ USART Mode Select
+ $30 constant UCSR0C_UPM0 \ Parity Mode Bits
+ $08 constant UCSR0C_USBS0 \ Stop Bit Select
+ $06 constant UCSR0C_UCSZ0 \ Character Size
+ $01 constant UCSR0C_UCPOL0 \ Clock Polarity
+&196 constant UBRR0 \ USART Baud Rate Register Bytes
+
+\ Interrupts
+&2 constant INT0Addr \ External Interrupt Request 0
+&4 constant PCINT0Addr \ Pin Change Interrupt Request 0
+&6 constant PCINT1Addr \ Pin Change Interrupt Request 1
+&8 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
+&10 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
+&12 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+&14 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
+&16 constant TIMER1_COMPBAddr \ Timer/Counter Compare Match B
+&18 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+&20 constant TIMER0_COMPAddr \ Timer/Counter0 Compare Match
+&22 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
+&24 constant SPI__STCAddr \ SPI Serial Transfer Complete
+&26 constant USART0__RXAddr \ USART0, Rx Complete
+&28 constant USART0__UDREAddr \ USART0 Data register Empty
+&30 constant USART0__TXAddr \ USART0, Tx Complete
+&32 constant USI_STARTAddr \ USI Start Condition
+&34 constant USI_OVERFLOWAddr \ USI Overflow
+&36 constant ANALOG_COMPAddr \ Analog Comparator
+&38 constant ADCAddr \ ADC Conversion Complete
+&40 constant EE_READYAddr \ EEPROM Ready
+&42 constant SPM_READYAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/atmega645a/device.asm b/amforth-6.5/avr8/devices/atmega645a/device.asm
new file mode 100644
index 0000000..687babf
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega645a/device.asm
@@ -0,0 +1,106 @@
+; Partname: ATmega645A
+; generated automatically, do not edit
+
+.nolist
+ .include "m645Adef.inc"
+.list
+
+.equ ramstart = 256
+.equ CELLSIZE = 2
+.macro readflashcell
+ lsl zl
+ rol zh
+ lpm @0, Z+
+ lpm @1, Z+
+.endmacro
+.macro writeflashcell
+ lsl zl
+ rol zh
+.endmacro
+.set WANT_AD_CONVERTER = 0
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_SPI = 0
+.set WANT_USI = 0
+.set WANT_CPU = 0
+.set WANT_JTAG = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_EEPROM = 0
+.set WANT_PORTA = 0
+.set WANT_PORTB = 0
+.set WANT_PORTC = 0
+.set WANT_PORTD = 0
+.set WANT_PORTE = 0
+.set WANT_PORTF = 0
+.set WANT_PORTG = 0
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_TIMER_COUNTER_2 = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_WATCHDOG = 0
+.set WANT_BOOT_LOAD = 0
+.set WANT_USART0 = 0
+.equ intvecsize = 2 ; please verify; flash size: 65536 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.org 2
+ rcall isr ; External Interrupt Request 0
+.org 4
+ rcall isr ; Pin Change Interrupt Request 0
+.org 6
+ rcall isr ; Pin Change Interrupt Request 1
+.org 8
+ rcall isr ; Timer/Counter2 Compare Match
+.org 10
+ rcall isr ; Timer/Counter2 Overflow
+.org 12
+ rcall isr ; Timer/Counter1 Capture Event
+.org 14
+ rcall isr ; Timer/Counter1 Compare Match A
+.org 16
+ rcall isr ; Timer/Counter Compare Match B
+.org 18
+ rcall isr ; Timer/Counter1 Overflow
+.org 20
+ rcall isr ; Timer/Counter0 Compare Match
+.org 22
+ rcall isr ; Timer/Counter0 Overflow
+.org 24
+ rcall isr ; SPI Serial Transfer Complete
+.org 26
+ rcall isr ; USART0, Rx Complete
+.org 28
+ rcall isr ; USART0 Data register Empty
+.org 30
+ rcall isr ; USART0, Tx Complete
+.org 32
+ rcall isr ; USI Start Condition
+.org 34
+ rcall isr ; USI Overflow
+.org 36
+ rcall isr ; Analog Comparator
+.org 38
+ rcall isr ; ADC Conversion Complete
+.org 40
+ rcall isr ; EEPROM Ready
+.org 42
+ rcall isr ; Store Program Memory Read
+.equ INTVECTORS = 22
+.nooverlap
+
+; compatability layer (maybe empty)
+.equ EEPE = EEWE
+.equ EEMPE = EEMWE
+
+; controller data area, environment query mcu-info
+mcu_info:
+mcu_ramsize:
+ .dw 4096
+mcu_eepromsize:
+ .dw 2048
+mcu_maxdp:
+ .dw 57344
+mcu_numints:
+ .dw 22
+mcu_name:
+ .dw 10
+ .db "ATmega645A"
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega645a/device.inc b/amforth-6.5/avr8/devices/atmega645a/device.inc
new file mode 100644
index 0000000..f6c0423
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega645a/device.inc
@@ -0,0 +1,1050 @@
+; Partname: ATmega645A
+; generated automatically, no not edit
+
+.if WANT_AD_CONVERTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC multiplexer Selection Register
+VE_ADMUX:
+ .dw $ff05
+ .db "ADMUX",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADMUX
+XT_ADMUX:
+ .dw PFA_DOVARIABLE
+PFA_ADMUX:
+ .dw 124
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register
+VE_ADCSRA:
+ .dw $ff06
+ .db "ADCSRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRA
+XT_ADCSRA:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRA:
+ .dw 122
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register Bytes
+VE_ADC:
+ .dw $ff03
+ .db "ADC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADC
+XT_ADC:
+ .dw PFA_DOVARIABLE
+PFA_ADC:
+ .dw 120
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Control and Status Register B
+VE_ADCSRB:
+ .dw $ff06
+ .db "ADCSRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRB
+XT_ADCSRB:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRB:
+ .dw 123
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 0
+VE_DIDR0:
+ .dw $ff05
+ .db "DIDR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR0
+XT_DIDR0:
+ .dw PFA_DOVARIABLE
+PFA_DIDR0:
+ .dw 126
+
+.endif
+.if WANT_ANALOG_COMPARATOR == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Control And Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw 80
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 1
+VE_DIDR1:
+ .dw $ff05
+ .db "DIDR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR1
+XT_DIDR1:
+ .dw PFA_DOVARIABLE
+PFA_DIDR1:
+ .dw 127
+
+.endif
+.if WANT_SPI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR:
+ .dw $ff04
+ .db "SPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR
+XT_SPCR:
+ .dw PFA_DOVARIABLE
+PFA_SPCR:
+ .dw 76
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR:
+ .dw $ff04
+ .db "SPSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR
+XT_SPSR:
+ .dw PFA_DOVARIABLE
+PFA_SPSR:
+ .dw 77
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR:
+ .dw $ff04
+ .db "SPDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR
+XT_SPDR:
+ .dw PFA_DOVARIABLE
+PFA_SPDR:
+ .dw 78
+
+.endif
+.if WANT_USI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USI Data Register
+VE_USIDR:
+ .dw $ff05
+ .db "USIDR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USIDR
+XT_USIDR:
+ .dw PFA_DOVARIABLE
+PFA_USIDR:
+ .dw 186
+; ( -- addr ) System Constant
+; R( -- )
+; USI Status Register
+VE_USISR:
+ .dw $ff05
+ .db "USISR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USISR
+XT_USISR:
+ .dw PFA_DOVARIABLE
+PFA_USISR:
+ .dw 185
+; ( -- addr ) System Constant
+; R( -- )
+; USI Control Register
+VE_USICR:
+ .dw $ff05
+ .db "USICR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USICR
+XT_USICR:
+ .dw PFA_DOVARIABLE
+PFA_USICR:
+ .dw 184
+
+.endif
+.if WANT_CPU == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw 95
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer
+VE_SP:
+ .dw $ff02
+ .db "SP"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SP
+XT_SP:
+ .dw PFA_DOVARIABLE
+PFA_SP:
+ .dw 93
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw 85
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Status Register
+VE_MCUSR:
+ .dw $ff05
+ .db "MCUSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUSR
+XT_MCUSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUSR:
+ .dw 84
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Calibration Value
+VE_OSCCAL:
+ .dw $ff06
+ .db "OSCCAL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSCCAL
+XT_OSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_OSCCAL:
+ .dw 102
+; ( -- addr ) System Constant
+; R( -- )
+; Clock Prescale Register
+VE_CLKPR:
+ .dw $ff05
+ .db "CLKPR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKPR
+XT_CLKPR:
+ .dw PFA_DOVARIABLE
+PFA_CLKPR:
+ .dw 97
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register
+VE_PRR:
+ .dw $ff03
+ .db "PRR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR
+XT_PRR:
+ .dw PFA_DOVARIABLE
+PFA_PRR:
+ .dw 100
+; ( -- addr ) System Constant
+; R( -- )
+; Sleep Mode Control Register
+VE_SMCR:
+ .dw $ff04
+ .db "SMCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SMCR
+XT_SMCR:
+ .dw PFA_DOVARIABLE
+PFA_SMCR:
+ .dw 83
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 2
+VE_GPIOR2:
+ .dw $ff06
+ .db "GPIOR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR2
+XT_GPIOR2:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR2:
+ .dw 75
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 1
+VE_GPIOR1:
+ .dw $ff06
+ .db "GPIOR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR1
+XT_GPIOR1:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR1:
+ .dw 74
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 0
+VE_GPIOR0:
+ .dw $ff06
+ .db "GPIOR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR0
+XT_GPIOR0:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR0:
+ .dw 62
+
+.endif
+.if WANT_JTAG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; On-Chip Debug Related Register in I/O Memory
+VE_OCDR:
+ .dw $ff04
+ .db "OCDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCDR
+XT_OCDR:
+ .dw PFA_DOVARIABLE
+PFA_OCDR:
+ .dw 81
+
+.endif
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register A
+VE_EICRA:
+ .dw $ff05
+ .db "EICRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRA
+XT_EICRA:
+ .dw PFA_DOVARIABLE
+PFA_EICRA:
+ .dw 105
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Mask Register
+VE_EIMSK:
+ .dw $ff05
+ .db "EIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIMSK
+XT_EIMSK:
+ .dw PFA_DOVARIABLE
+PFA_EIMSK:
+ .dw 61
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Flag Register
+VE_EIFR:
+ .dw $ff04
+ .db "EIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIFR
+XT_EIFR:
+ .dw PFA_DOVARIABLE
+PFA_EIFR:
+ .dw 60
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 1
+VE_PCMSK1:
+ .dw $ff06
+ .db "PCMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK1
+XT_PCMSK1:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK1:
+ .dw 108
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 0
+VE_PCMSK0:
+ .dw $ff06
+ .db "PCMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK0
+XT_PCMSK0:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK0:
+ .dw 107
+
+.endif
+.if WANT_EEPROM == 1
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Read/Write Access Bytes
+VE_EEAR:
+ .dw $ff04
+ .db "EEAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEAR
+XT_EEAR:
+ .dw PFA_DOVARIABLE
+PFA_EEAR:
+ .dw 65
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw 64
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw 63
+
+.endif
+.if WANT_PORTA == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Register
+VE_PORTA:
+ .dw $ff05
+ .db "PORTA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTA
+XT_PORTA:
+ .dw PFA_DOVARIABLE
+PFA_PORTA:
+ .dw 34
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Direction Register
+VE_DDRA:
+ .dw $ff04
+ .db "DDRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRA
+XT_DDRA:
+ .dw PFA_DOVARIABLE
+PFA_DDRA:
+ .dw 33
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Input Pins
+VE_PINA:
+ .dw $ff04
+ .db "PINA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINA
+XT_PINA:
+ .dw PFA_DOVARIABLE
+PFA_PINA:
+ .dw 32
+
+.endif
+.if WANT_PORTB == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw 37
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw 36
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw 35
+
+.endif
+.if WANT_PORTC == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Register
+VE_PORTC:
+ .dw $ff05
+ .db "PORTC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTC
+XT_PORTC:
+ .dw PFA_DOVARIABLE
+PFA_PORTC:
+ .dw 40
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Direction Register
+VE_DDRC:
+ .dw $ff04
+ .db "DDRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRC
+XT_DDRC:
+ .dw PFA_DOVARIABLE
+PFA_DDRC:
+ .dw 39
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Input Pins
+VE_PINC:
+ .dw $ff04
+ .db "PINC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINC
+XT_PINC:
+ .dw PFA_DOVARIABLE
+PFA_PINC:
+ .dw 38
+
+.endif
+.if WANT_PORTD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw 43
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw 42
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw 41
+
+.endif
+.if WANT_PORTE == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port E
+VE_PORTE:
+ .dw $ff05
+ .db "PORTE",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTE
+XT_PORTE:
+ .dw PFA_DOVARIABLE
+PFA_PORTE:
+ .dw 46
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port E
+VE_DDRE:
+ .dw $ff04
+ .db "DDRE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRE
+XT_DDRE:
+ .dw PFA_DOVARIABLE
+PFA_DDRE:
+ .dw 45
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port E
+VE_PINE:
+ .dw $ff04
+ .db "PINE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINE
+XT_PINE:
+ .dw PFA_DOVARIABLE
+PFA_PINE:
+ .dw 44
+
+.endif
+.if WANT_PORTF == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port F
+VE_PORTF:
+ .dw $ff05
+ .db "PORTF",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTF
+XT_PORTF:
+ .dw PFA_DOVARIABLE
+PFA_PORTF:
+ .dw 49
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port F
+VE_DDRF:
+ .dw $ff04
+ .db "DDRF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRF
+XT_DDRF:
+ .dw PFA_DOVARIABLE
+PFA_DDRF:
+ .dw 48
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port F
+VE_PINF:
+ .dw $ff04
+ .db "PINF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINF
+XT_PINF:
+ .dw PFA_DOVARIABLE
+PFA_PINF:
+ .dw 47
+
+.endif
+.if WANT_PORTG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Data Register
+VE_PORTG:
+ .dw $ff05
+ .db "PORTG",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTG
+XT_PORTG:
+ .dw PFA_DOVARIABLE
+PFA_PORTG:
+ .dw 52
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Data Direction Register
+VE_DDRG:
+ .dw $ff04
+ .db "DDRG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRG
+XT_DDRG:
+ .dw PFA_DOVARIABLE
+PFA_DDRG:
+ .dw 51
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Input Pins
+VE_PING:
+ .dw $ff04
+ .db "PING"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PING
+XT_PING:
+ .dw PFA_DOVARIABLE
+PFA_PING:
+ .dw 50
+
+.endif
+.if WANT_TIMER_COUNTER_0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Control Register
+VE_TCCR0A:
+ .dw $ff06
+ .db "TCCR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0A
+XT_TCCR0A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0A:
+ .dw 68
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw 70
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0A:
+ .dw $ff05
+ .db "OCR0A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0A
+XT_OCR0A:
+ .dw PFA_DOVARIABLE
+PFA_OCR0A:
+ .dw 71
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Mask Register
+VE_TIMSK0:
+ .dw $ff06
+ .db "TIMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK0
+XT_TIMSK0:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK0:
+ .dw 110
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Flag register
+VE_TIFR0:
+ .dw $ff05
+ .db "TIFR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR0
+XT_TIFR0:
+ .dw PFA_DOVARIABLE
+PFA_TIFR0:
+ .dw 53
+; ( -- addr ) System Constant
+; R( -- )
+; General Timer/Control Register
+VE_GTCCR:
+ .dw $ff05
+ .db "GTCCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GTCCR
+XT_GTCCR:
+ .dw PFA_DOVARIABLE
+PFA_GTCCR:
+ .dw 67
+
+.endif
+.if WANT_TIMER_COUNTER_2 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register
+VE_TCCR2A:
+ .dw $ff06
+ .db "TCCR2A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2A
+XT_TCCR2A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2A:
+ .dw 176
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2
+VE_TCNT2:
+ .dw $ff05
+ .db "TCNT2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT2
+XT_TCNT2:
+ .dw PFA_DOVARIABLE
+PFA_TCNT2:
+ .dw 178
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register
+VE_OCR2A:
+ .dw $ff05
+ .db "OCR2A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2A
+XT_OCR2A:
+ .dw PFA_DOVARIABLE
+PFA_OCR2A:
+ .dw 179
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Interrupt Mask register
+VE_TIMSK2:
+ .dw $ff06
+ .db "TIMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK2
+XT_TIMSK2:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK2:
+ .dw 112
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Interrupt Flag Register
+VE_TIFR2:
+ .dw $ff05
+ .db "TIFR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR2
+XT_TIFR2:
+ .dw PFA_DOVARIABLE
+PFA_TIFR2:
+ .dw 55
+; ( -- addr ) System Constant
+; R( -- )
+; Asynchronous Status Register
+VE_ASSR:
+ .dw $ff04
+ .db "ASSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ASSR
+XT_ASSR:
+ .dw PFA_DOVARIABLE
+PFA_ASSR:
+ .dw 182
+
+.endif
+.if WANT_TIMER_COUNTER_1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw 128
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw 129
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter 1 Control Register C
+VE_TCCR1C:
+ .dw $ff06
+ .db "TCCR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1C
+XT_TCCR1C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1C:
+ .dw 130
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Bytes
+VE_TCNT1:
+ .dw $ff05
+ .db "TCNT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1
+XT_TCNT1:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1:
+ .dw 132
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register A Bytes
+VE_OCR1A:
+ .dw $ff05
+ .db "OCR1A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1A
+XT_OCR1A:
+ .dw PFA_DOVARIABLE
+PFA_OCR1A:
+ .dw 136
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register B Bytes
+VE_OCR1B:
+ .dw $ff05
+ .db "OCR1B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1B
+XT_OCR1B:
+ .dw PFA_DOVARIABLE
+PFA_OCR1B:
+ .dw 138
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Bytes
+VE_ICR1:
+ .dw $ff04
+ .db "ICR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1
+XT_ICR1:
+ .dw PFA_DOVARIABLE
+PFA_ICR1:
+ .dw 134
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Mask Register
+VE_TIMSK1:
+ .dw $ff06
+ .db "TIMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK1
+XT_TIMSK1:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK1:
+ .dw 111
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Flag register
+VE_TIFR1:
+ .dw $ff05
+ .db "TIFR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR1
+XT_TIFR1:
+ .dw PFA_DOVARIABLE
+PFA_TIFR1:
+ .dw 54
+
+.endif
+.if WANT_WATCHDOG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCR:
+ .dw $ff05
+ .db "WDTCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCR
+XT_WDTCR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCR:
+ .dw 96
+
+.endif
+.if WANT_BOOT_LOAD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control Register
+VE_SPMCSR:
+ .dw $ff06
+ .db "SPMCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCSR
+XT_SPMCSR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCSR:
+ .dw 87
+
+.endif
+.if WANT_USART0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR0:
+ .dw $ff04
+ .db "UDR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR0
+XT_UDR0:
+ .dw PFA_DOVARIABLE
+PFA_UDR0:
+ .dw 198
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR0A:
+ .dw $ff06
+ .db "UCSR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0A
+XT_UCSR0A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0A:
+ .dw 192
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR0B:
+ .dw $ff06
+ .db "UCSR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0B
+XT_UCSR0B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0B:
+ .dw 193
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR0C:
+ .dw $ff06
+ .db "UCSR0C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0C
+XT_UCSR0C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0C:
+ .dw 194
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Bytes
+VE_UBRR0:
+ .dw $ff05
+ .db "UBRR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR0
+XT_UBRR0:
+ .dw PFA_DOVARIABLE
+PFA_UBRR0:
+ .dw 196
+
+.endif
diff --git a/amforth-6.5/avr8/devices/atmega645a/device.py b/amforth-6.5/avr8/devices/atmega645a/device.py
new file mode 100644
index 0000000..e1ba808
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega645a/device.py
@@ -0,0 +1,318 @@
+# Generated Automatically
+
+# Partname ATmega645A
+
+MCUREGS = {
+# Interrupt Vectors
+ 'INT0Addr' : '#2', # External Interrupt Request 0
+ 'PCINT0Addr' : '#4', # Pin Change Interrupt Request 0
+ 'PCINT1Addr' : '#6', # Pin Change Interrupt Request 1
+ 'TIMER2_COMPAddr' : '#8', # Timer/Counter2 Compare Match
+ 'TIMER2_OVFAddr' : '#10', # Timer/Counter2 Overflow
+ 'TIMER1_CAPTAddr' : '#12', # Timer/Counter1 Capture Event
+ 'TIMER1_COMPAAddr' : '#14', # Timer/Counter1 Compare Match A
+ 'TIMER1_COMPBAddr' : '#16', # Timer/Counter Compare Match B
+ 'TIMER1_OVFAddr' : '#18', # Timer/Counter1 Overflow
+ 'TIMER0_COMPAddr' : '#20', # Timer/Counter0 Compare Match
+ 'TIMER0_OVFAddr' : '#22', # Timer/Counter0 Overflow
+ 'SPI_STCAddr' : '#24', # SPI Serial Transfer Complete
+ 'USART0_RXAddr' : '#26', # USART0, Rx Complete
+ 'USART0_UDREAddr' : '#28', # USART0 Data register Empty
+ 'USART0_TXAddr' : '#30', # USART0, Tx Complete
+ 'USI_STARTAddr' : '#32', # USI Start Condition
+ 'USI_OVERFLOWAddr' : '#34', # USI Overflow
+ 'ANALOG_COMPAddr' : '#36', # Analog Comparator
+ 'ADCAddr' : '#38', # ADC Conversion Complete
+ 'EE_READYAddr' : '#40', # EEPROM Ready
+ 'SPM_READYAddr' : '#42', # Store Program Memory Read
+
+# Module AD_CONVERTER
+ 'ADMUX' : '$7c', # The ADC multiplexer Selection
+ 'ADMUX_REFS': '$c0', # Reference Selection Bits
+ 'ADMUX_ADLAR': '$20', # Left Adjust Result
+ 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
+ 'ADCSRA' : '$7a', # The ADC Control and Status reg
+ 'ADCSRA_ADEN': '$80', # ADC Enable
+ 'ADCSRA_ADSC': '$40', # ADC Start Conversion
+ 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
+ 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
+ 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
+ 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
+ 'ADC' : '$78', # ADC Data Register Bytes
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Sources
+ 'DIDR0' : '$7e', # Digital Input Disable Register
+ 'DIDR0_ADC7D': '$80', # ADC7 Digital input Disable
+ 'DIDR0_ADC6D': '$40', # ADC6 Digital input Disable
+ 'DIDR0_ADC5D': '$20', # ADC5 Digital input Disable
+ 'DIDR0_ADC4D': '$10', # ADC4 Digital input Disable
+ 'DIDR0_ADC3D': '$8', # ADC3 Digital input Disable
+ 'DIDR0_ADC2D': '$4', # ADC2 Digital input Disable
+ 'DIDR0_ADC1D': '$2', # ADC1 Digital input Disable
+ 'DIDR0_ADC0D': '$1', # ADC0 Digital input Disable
+
+# Module ANALOG_COMPARATOR
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
+ 'ACSR' : '$50', # Analog Comparator Control And
+ 'ACSR_ACD': '$80', # Analog Comparator Disable
+ 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
+ 'ACSR_ACO': '$20', # Analog Compare Output
+ 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
+ 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
+ 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
+ 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
+ 'DIDR1' : '$7f', # Digital Input Disable Register
+ 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
+ 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
+
+# Module SPI
+ 'SPCR' : '$4c', # SPI Control Register
+ 'SPCR_SPIE': '$80', # SPI Interrupt Enable
+ 'SPCR_SPE': '$40', # SPI Enable
+ 'SPCR_DORD': '$20', # Data Order
+ 'SPCR_MSTR': '$10', # Master/Slave Select
+ 'SPCR_CPOL': '$8', # Clock polarity
+ 'SPCR_CPHA': '$4', # Clock Phase
+ 'SPCR_SPR': '$3', # SPI Clock Rate Selects
+ 'SPSR' : '$4d', # SPI Status Register
+ 'SPSR_SPIF': '$80', # SPI Interrupt Flag
+ 'SPSR_WCOL': '$40', # Write Collision Flag
+ 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
+ 'SPDR' : '$4e', # SPI Data Register
+
+# Module USI
+ 'USIDR' : '$ba', # USI Data Register
+ 'USISR' : '$b9', # USI Status Register
+ 'USISR_USISIF': '$80', # Start Condition Interrupt Flag
+ 'USISR_USIOIF': '$40', # Counter Overflow Interrupt Fla
+ 'USISR_USIPF': '$20', # Stop Condition Flag
+ 'USISR_USIDC': '$10', # Data Output Collision
+ 'USISR_USICNT': '$f', # USI Counter Value Bits
+ 'USICR' : '$b8', # USI Control Register
+ 'USICR_USISIE': '$80', # Start Condition Interrupt Enab
+ 'USICR_USIOIE': '$40', # Counter Overflow Interrupt Ena
+ 'USICR_USIWM': '$30', # USI Wire Mode Bits
+ 'USICR_USICS': '$c', # USI Clock Source Select Bits
+ 'USICR_USICLK': '$2', # Clock Strobe
+ 'USICR_USITC': '$1', # Toggle Clock Port Pin
+
+# Module CPU
+ 'SREG' : '$5f', # Status Register
+ 'SREG_I': '$80', # Global Interrupt Enable
+ 'SREG_T': '$40', # Bit Copy Storage
+ 'SREG_H': '$20', # Half Carry Flag
+ 'SREG_S': '$10', # Sign Bit
+ 'SREG_V': '$8', # Two's Complement Overflow Flag
+ 'SREG_N': '$4', # Negative Flag
+ 'SREG_Z': '$2', # Zero Flag
+ 'SREG_C': '$1', # Carry Flag
+ 'SP' : '$5d', # Stack Pointer
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_PUD': '$10', # Pull-up disable
+ 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
+ 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+ 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
+ 'MCUSR_BORF': '$4', # Brown-out Reset Flag
+ 'MCUSR_EXTRF': '$2', # External Reset Flag
+ 'MCUSR_PORF': '$1', # Power-on reset flag
+ 'OSCCAL' : '$66', # Oscillator Calibration Value
+ 'CLKPR' : '$61', # Clock Prescale Register
+ 'CLKPR_CLKPCE': '$80', # Clock Prescaler Change Enable
+ 'CLKPR_CLKPS': '$f', # Clock Prescaler Select Bits
+ 'PRR' : '$64', # Power Reduction Register
+ 'PRR_PRLCD': '$10', # Power Reduction LCD
+ 'PRR_PRTIM1': '$8', # Power Reduction Timer/Counter1
+ 'PRR_PRSPI': '$4', # Power Reduction Serial Periphe
+ 'PRR_PRUSART0': '$2', # Power Reduction USART
+ 'PRR_PRADC': '$1', # Power Reduction ADC
+ 'SMCR' : '$53', # Sleep Mode Control Register
+ 'SMCR_SM': '$e', # Sleep Mode Select bits
+ 'SMCR_SE': '$1', # Sleep Enable
+ 'GPIOR2' : '$4b', # General Purpose IO Register 2
+ 'GPIOR1' : '$4a', # General Purpose IO Register 1
+ 'GPIOR0' : '$3e', # General Purpose IO Register 0
+
+# Module JTAG
+ 'OCDR' : '$51', # On-Chip Debug Related Register
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_JTD': '$80', # JTAG Interface Disable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+
+# Module EXTERNAL_INTERRUPT
+ 'EICRA' : '$69', # External Interrupt Control Reg
+ 'EICRA_ISC01': '$2', # External Interrupt Sense Contr
+ 'EICRA_ISC00': '$1', # External Interrupt Sense Contr
+ 'EIMSK' : '$3d', # External Interrupt Mask Regist
+ 'EIMSK_PCIE': '$f0', # Pin Change Interrupt Enables
+ 'EIMSK_INT0': '$1', # External Interrupt Request 0 E
+ 'EIFR' : '$3c', # External Interrupt Flag Regist
+ 'EIFR_PCIF': '$f0', # Pin Change Interrupt Flags
+ 'EIFR_INTF0': '$1', # External Interrupt Flag 0
+ 'PCMSK1' : '$6c', # Pin Change Mask Register 1
+ 'PCMSK0' : '$6b', # Pin Change Mask Register 0
+
+# Module EEPROM
+ 'EEAR' : '$41', # EEPROM Read/Write Access Byte
+ 'EEDR' : '$40', # EEPROM Data Register
+ 'EECR' : '$3f', # EEPROM Control Register
+ 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
+ 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
+ 'EECR_EEWE': '$2', # EEPROM Write Enable
+ 'EECR_EERE': '$1', # EEPROM Read Enable
+
+# Module PORTA
+ 'PORTA' : '$22', # Port A Data Register
+ 'DDRA' : '$21', # Port A Data Direction Register
+ 'PINA' : '$20', # Port A Input Pins
+
+# Module PORTB
+ 'PORTB' : '$25', # Port B Data Register
+ 'DDRB' : '$24', # Port B Data Direction Register
+ 'PINB' : '$23', # Port B Input Pins
+
+# Module PORTC
+ 'PORTC' : '$28', # Port C Data Register
+ 'DDRC' : '$27', # Port C Data Direction Register
+ 'PINC' : '$26', # Port C Input Pins
+
+# Module PORTD
+ 'PORTD' : '$2b', # Port D Data Register
+ 'DDRD' : '$2a', # Port D Data Direction Register
+ 'PIND' : '$29', # Port D Input Pins
+
+# Module PORTE
+ 'PORTE' : '$2e', # Data Register, Port E
+ 'DDRE' : '$2d', # Data Direction Register, Port
+ 'PINE' : '$2c', # Input Pins, Port E
+
+# Module PORTF
+ 'PORTF' : '$31', # Data Register, Port F
+ 'DDRF' : '$30', # Data Direction Register, Port
+ 'PINF' : '$2f', # Input Pins, Port F
+
+# Module PORTG
+ 'PORTG' : '$34', # Port G Data Register
+ 'DDRG' : '$33', # Port G Data Direction Register
+ 'PING' : '$32', # Port G Input Pins
+
+# Module TIMER_COUNTER_0
+ 'TCCR0A' : '$44', # Timer/Counter0 Control Registe
+ 'TCCR0A_FOC0A': '$80', # Force Output Compare
+ 'TCCR0A_WGM00': '$40', # Waveform Generation Mode 0
+ 'TCCR0A_COM0A': '$30', # Compare Match Output Modes
+ 'TCCR0A_WGM01': '$8', # Waveform Generation Mode 1
+ 'TCCR0A_CS0': '$7', # Clock Selects
+ 'TCNT0' : '$46', # Timer/Counter0
+ 'OCR0A' : '$47', # Timer/Counter0 Output Compare
+ 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
+ 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
+ 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
+ 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
+ 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
+ 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Control Register
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSR310': '$1', # Prescaler Reset Timer/Counter1
+
+# Module TIMER_COUNTER_2
+ 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
+ 'TCCR2A_FOC2A': '$80', # Force Output Compare A
+ 'TCCR2A_WGM20': '$40', # Waveform Generation Mode
+ 'TCCR2A_COM2A': '$30', # Compare Output Mode bits
+ 'TCCR2A_WGM21': '$8', # Waveform Generation Mode
+ 'TCCR2A_CS2': '$7', # Clock Select bits
+ 'TCNT2' : '$b2', # Timer/Counter2
+ 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
+ 'TIMSK2' : '$70', # Timer/Counter2 Interrupt Mask
+ 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
+ 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
+ 'TIFR2' : '$37', # Timer/Counter2 Interrupt Flag
+ 'TIFR2_OCF2A': '$2', # Timer/Counter2 Output Compare
+ 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_PSR2': '$2', # Prescaler Reset Timer/Counter2
+ 'ASSR' : '$b6', # Asynchronous Status Register
+ 'ASSR_EXCLK': '$10', # Enable External Clock Interrup
+ 'ASSR_AS2': '$8', # AS2: Asynchronous Timer/Counte
+ 'ASSR_TCN2UB': '$4', # TCN2UB: Timer/Counter2 Update
+ 'ASSR_OCR2UB': '$2', # Output Compare Register2 Updat
+ 'ASSR_TCR2UB': '$1', # TCR2UB: Timer/Counter Control
+
+# Module TIMER_COUNTER_1
+ 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
+ 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
+ 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
+ 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
+ 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
+ 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
+ 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
+ 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
+ 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
+ 'TCCR1C' : '$82', # Timer/Counter 1 Control Regist
+ 'TCCR1C_FOC1A': '$80', # Force Output Compare 1A
+ 'TCCR1C_FOC1B': '$40', # Force Output Compare 1B
+ 'TCNT1' : '$84', # Timer/Counter1 Bytes
+ 'OCR1A' : '$88', # Timer/Counter1 Output Compare
+ 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
+ 'ICR1' : '$86', # Timer/Counter1 Input Capture R
+ 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
+ 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
+ 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
+ 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
+ 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
+ 'TIFR1' : '$36', # Timer/Counter1 Interrupt Flag
+ 'TIFR1_ICF1': '$20', # Input Capture Flag 1
+ 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
+ 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
+ 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
+
+# Module WATCHDOG
+ 'WDTCR' : '$60', # Watchdog Timer Control Registe
+ 'WDTCR_WDCE': '$10', # Watchdog Change Enable
+ 'WDTCR_WDE': '$8', # Watch Dog Enable
+ 'WDTCR_WDP': '$7', # Watch Dog Timer Prescaler bits
+
+# Module BOOT_LOAD
+ 'SPMCSR' : '$57', # Store Program Memory Control R
+ 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
+ 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
+ 'SPMCSR_RWWSRE': '$10', # Read While Write section read
+ 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
+ 'SPMCSR_PGWRT': '$4', # Page Write
+ 'SPMCSR_PGERS': '$2', # Page Erase
+ 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
+
+# Module USART0
+ 'UDR0' : '$c6', # USART I/O Data Register
+ 'UCSR0A' : '$c0', # USART Control and Status Regis
+ 'UCSR0A_RXC0': '$80', # USART Receive Complete
+ 'UCSR0A_TXC0': '$40', # USART Transmit Complete
+ 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
+ 'UCSR0A_FE0': '$10', # Framing Error
+ 'UCSR0A_DOR0': '$8', # Data OverRun
+ 'UCSR0A_UPE0': '$4', # USART Parity Error
+ 'UCSR0A_U2X0': '$2', # Double the USART Transmission
+ 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
+ 'UCSR0B' : '$c1', # USART Control and Status Regis
+ 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
+ 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
+ 'UCSR0B_UDRIE0': '$20', # USART Data Register Empty Inte
+ 'UCSR0B_RXEN0': '$10', # Receiver Enable
+ 'UCSR0B_TXEN0': '$8', # Transmitter Enable
+ 'UCSR0B_UCSZ02': '$4', # Character Size
+ 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
+ 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
+ 'UCSR0C' : '$c2', # USART Control and Status Regis
+ 'UCSR0C_UMSEL0': '$40', # USART Mode Select
+ 'UCSR0C_UPM0': '$30', # Parity Mode Bits
+ 'UCSR0C_USBS0': '$8', # Stop Bit Select
+ 'UCSR0C_UCSZ0': '$6', # Character Size
+ 'UCSR0C_UCPOL0': '$1', # Clock Polarity
+ 'UBRR0' : '$c4', # USART Baud Rate Register Byte
+
+ '__amforth_dummy':'0'
+}
diff --git a/amforth-6.5/avr8/devices/atmega645a/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega645a/words/no-jtag.asm
new file mode 100644
index 0000000..352a4bb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega645a/words/no-jtag.asm
@@ -0,0 +1,14 @@
+; ( -- )
+; ( -- )
+; MCU
+; disable jtag at runtime
+VE_NOJTAG:
+ .dw $FF05
+ .db "-jtag",0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOJTAG
+XT_NOJTAG:
+ .dw PFA_NOJTAG
+PFA_NOJTAG:
+
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega645a/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega645a/words/no-wdt.asm
new file mode 100644
index 0000000..4a12261
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega645a/words/no-wdt.asm
@@ -0,0 +1,22 @@
+; ( -- )
+; MCU
+; disable watch dog timer at runtime
+VE_NOWDT:
+ .dw $ff04
+ .db "-wdt"
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOWDT
+XT_NOWDT:
+ .dw PFA_NOWDT
+PFA_NOWDT:
+
+; Reset WDT
+ wdr
+; Write logical one to WDTOE and WDE
+ in_ temp1, WDTCR
+ ori temp1, (1<<WDTOE)|(1<<WDE)
+ out WDTCR, temp1
+; Turn off WDT
+ ldi temp1, (0<<WDE)
+ out_ WDTCR, temp1
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega645a/words/sleep.asm b/amforth-6.5/avr8/devices/atmega645a/words/sleep.asm
new file mode 100644
index 0000000..256249c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega645a/words/sleep.asm
@@ -0,0 +1,19 @@
+; ( mode -- )
+; MCU
+; put the controller into the specified sleep mode
+VE_SLEEP:
+ .dw $ff05
+ .db "sleep", 0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_SLEEP
+XT_SLEEP:
+ .dw PFA_SLEEP
+PFA_SLEEP:
+ andi tosl, 7 ; leave only legal mode bits
+ lsl tosl ; move to correct location (bits 3-1)
+ ori tosl, 1 ; set the SE bit
+ out_ SMCR, tosl ; set the sleep config
+ sleep ; nighty-night
+ out_ SMCR, zerol ; 0 protects against accidental sleeps
+ loadtos ; pop argument from stack
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega645p/atmega645p.frt b/amforth-6.5/avr8/devices/atmega645p/atmega645p.frt
new file mode 100644
index 0000000..bfffd11
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega645p/atmega645p.frt
@@ -0,0 +1,285 @@
+\ Partname: ATmega645P
+\ generated automatically
+
+\ AD_CONVERTER
+&124 constant ADMUX \ The ADC multiplexer Selection Register
+ $C0 constant ADMUX_REFS \ Reference Selection Bits
+ $20 constant ADMUX_ADLAR \ Left Adjust Result
+ $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
+&122 constant ADCSRA \ The ADC Control and Status register
+ $80 constant ADCSRA_ADEN \ ADC Enable
+ $40 constant ADCSRA_ADSC \ ADC Start Conversion
+ $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
+ $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
+ $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
+ $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
+&120 constant ADC \ ADC Data Register Bytes
+&123 constant ADCSRB \ ADC Control and Status Register B
+ $07 constant ADCSRB_ADTS \ ADC Auto Trigger Sources
+&126 constant DIDR0 \ Digital Input Disable Register 0
+ $80 constant DIDR0_ADC7D \ ADC7 Digital input Disable
+ $40 constant DIDR0_ADC6D \ ADC6 Digital input Disable
+ $20 constant DIDR0_ADC5D \ ADC5 Digital input Disable
+ $10 constant DIDR0_ADC4D \ ADC4 Digital input Disable
+ $08 constant DIDR0_ADC3D \ ADC3 Digital input Disable
+ $04 constant DIDR0_ADC2D \ ADC2 Digital input Disable
+ $02 constant DIDR0_ADC1D \ ADC1 Digital input Disable
+ $01 constant DIDR0_ADC0D \ ADC0 Digital input Disable
+\ ANALOG_COMPARATOR
+&80 constant ACSR \ Analog Comparator Control And Status Register
+ $80 constant ACSR_ACD \ Analog Comparator Disable
+ $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
+ $20 constant ACSR_ACO \ Analog Compare Output
+ $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
+ $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
+ $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
+ $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
+&127 constant DIDR1 \ Digital Input Disable Register 1
+ $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
+ $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
+\ SPI
+&76 constant SPCR \ SPI Control Register
+ $80 constant SPCR_SPIE \ SPI Interrupt Enable
+ $40 constant SPCR_SPE \ SPI Enable
+ $20 constant SPCR_DORD \ Data Order
+ $10 constant SPCR_MSTR \ Master/Slave Select
+ $08 constant SPCR_CPOL \ Clock polarity
+ $04 constant SPCR_CPHA \ Clock Phase
+ $03 constant SPCR_SPR \ SPI Clock Rate Selects
+&77 constant SPSR \ SPI Status Register
+ $80 constant SPSR_SPIF \ SPI Interrupt Flag
+ $40 constant SPSR_WCOL \ Write Collision Flag
+ $01 constant SPSR_SPI2X \ Double SPI Speed Bit
+&78 constant SPDR \ SPI Data Register
+\ USI
+&186 constant USIDR \ USI Data Register
+&185 constant USISR \ USI Status Register
+ $80 constant USISR_USISIF \ Start Condition Interrupt Flag
+ $40 constant USISR_USIOIF \ Counter Overflow Interrupt Flag
+ $20 constant USISR_USIPF \ Stop Condition Flag
+ $10 constant USISR_USIDC \ Data Output Collision
+ $0F constant USISR_USICNT \ USI Counter Value Bits
+&184 constant USICR \ USI Control Register
+ $80 constant USICR_USISIE \ Start Condition Interrupt Enable
+ $40 constant USICR_USIOIE \ Counter Overflow Interrupt Enable
+ $30 constant USICR_USIWM \ USI Wire Mode Bits
+ $0C constant USICR_USICS \ USI Clock Source Select Bits
+ $02 constant USICR_USICLK \ Clock Strobe
+ $01 constant USICR_USITC \ Toggle Clock Port Pin
+\ CPU
+&95 constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ $08 constant SREG_V \ Two's Complement Overflow Flag
+ $04 constant SREG_N \ Negative Flag
+ $02 constant SREG_Z \ Zero Flag
+ $01 constant SREG_C \ Carry Flag
+&93 constant SP \ Stack Pointer
+&85 constant MCUCR \ MCU Control Register
+ $10 constant MCUCR_PUD \ Pull-up disable
+ $02 constant MCUCR_IVSEL \ Interrupt Vector Select
+ $01 constant MCUCR_IVCE \ Interrupt Vector Change Enable
+&84 constant MCUSR \ MCU Status Register
+ $10 constant MCUSR_JTRF \ JTAG Reset Flag
+ $08 constant MCUSR_WDRF \ Watchdog Reset Flag
+ $04 constant MCUSR_BORF \ Brown-out Reset Flag
+ $02 constant MCUSR_EXTRF \ External Reset Flag
+ $01 constant MCUSR_PORF \ Power-on reset flag
+&102 constant OSCCAL \ Oscillator Calibration Value
+&97 constant CLKPR \ Clock Prescale Register
+ $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable
+ $0F constant CLKPR_CLKPS \ Clock Prescaler Select Bits
+&100 constant PRR \ Power Reduction Register
+ $10 constant PRR_PRLCD \ Power Reduction LCD
+ $08 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
+ $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
+ $02 constant PRR_PRUSART0 \ Power Reduction USART
+ $01 constant PRR_PRADC \ Power Reduction ADC
+&83 constant SMCR \ Sleep Mode Control Register
+ $0E constant SMCR_SM \ Sleep Mode Select bits
+ $01 constant SMCR_SE \ Sleep Enable
+&75 constant GPIOR2 \ General Purpose IO Register 2
+&74 constant GPIOR1 \ General Purpose IO Register 1
+&62 constant GPIOR0 \ General Purpose IO Register 0
+\ JTAG
+&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
+\ EXTERNAL_INTERRUPT
+&105 constant EICRA \ External Interrupt Control Register A
+ $02 constant EICRA_ISC01 \ External Interrupt Sense Control 0 Bit 1
+ $01 constant EICRA_ISC00 \ External Interrupt Sense Control 0 Bit 0
+&61 constant EIMSK \ External Interrupt Mask Register
+ $F0 constant EIMSK_PCIE \ Pin Change Interrupt Enables
+ $01 constant EIMSK_INT0 \ External Interrupt Request 0 Enable
+&60 constant EIFR \ External Interrupt Flag Register
+ $F0 constant EIFR_PCIF \ Pin Change Interrupt Flags
+ $01 constant EIFR_INTF0 \ External Interrupt Flag 0
+&108 constant PCMSK1 \ Pin Change Mask Register 1
+&107 constant PCMSK0 \ Pin Change Mask Register 0
+\ EEPROM
+&65 constant EEAR \ EEPROM Read/Write Access Bytes
+&64 constant EEDR \ EEPROM Data Register
+&63 constant EECR \ EEPROM Control Register
+ $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
+ $04 constant EECR_EEMWE \ EEPROM Master Write Enable
+ $02 constant EECR_EEWE \ EEPROM Write Enable
+ $01 constant EECR_EERE \ EEPROM Read Enable
+\ PORTA
+&34 constant PORTA \ Port A Data Register
+&33 constant DDRA \ Port A Data Direction Register
+&32 constant PINA \ Port A Input Pins
+\ PORTB
+&37 constant PORTB \ Port B Data Register
+&36 constant DDRB \ Port B Data Direction Register
+&35 constant PINB \ Port B Input Pins
+\ PORTC
+&40 constant PORTC \ Port C Data Register
+&39 constant DDRC \ Port C Data Direction Register
+&38 constant PINC \ Port C Input Pins
+\ PORTD
+&43 constant PORTD \ Port D Data Register
+&42 constant DDRD \ Port D Data Direction Register
+&41 constant PIND \ Port D Input Pins
+\ PORTE
+&46 constant PORTE \ Data Register, Port E
+&45 constant DDRE \ Data Direction Register, Port E
+&44 constant PINE \ Input Pins, Port E
+\ PORTF
+&49 constant PORTF \ Data Register, Port F
+&48 constant DDRF \ Data Direction Register, Port F
+&47 constant PINF \ Input Pins, Port F
+\ PORTG
+&52 constant PORTG \ Port G Data Register
+&51 constant DDRG \ Port G Data Direction Register
+&50 constant PING \ Port G Input Pins
+\ TIMER_COUNTER_0
+&68 constant TCCR0A \ Timer/Counter0 Control Register
+ $80 constant TCCR0A_FOC0A \ Force Output Compare
+ $40 constant TCCR0A_WGM00 \ Waveform Generation Mode 0
+ $30 constant TCCR0A_COM0A \ Compare Match Output Modes
+ $08 constant TCCR0A_WGM01 \ Waveform Generation Mode 1
+ $07 constant TCCR0A_CS0 \ Clock Selects
+&70 constant TCNT0 \ Timer/Counter0
+&71 constant OCR0A \ Timer/Counter0 Output Compare Register
+&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
+ $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match Interrupt Enable
+ $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
+&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
+ $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0
+ $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
+&67 constant GTCCR \ General Timer/Control Register
+ $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
+ $01 constant GTCCR_PSR310 \ Prescaler Reset Timer/Counter1 and Timer/Counter0
+\ TIMER_COUNTER_2
+&176 constant TCCR2A \ Timer/Counter2 Control Register
+ $80 constant TCCR2A_FOC2A \ Force Output Compare A
+ $40 constant TCCR2A_WGM20 \ Waveform Generation Mode
+ $30 constant TCCR2A_COM2A \ Compare Output Mode bits
+ $08 constant TCCR2A_WGM21 \ Waveform Generation Mode
+ $07 constant TCCR2A_CS2 \ Clock Select bits
+&178 constant TCNT2 \ Timer/Counter2
+&179 constant OCR2A \ Timer/Counter2 Output Compare Register
+&112 constant TIMSK2 \ Timer/Counter2 Interrupt Mask register
+ $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match Interrupt Enable
+ $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
+&55 constant TIFR2 \ Timer/Counter2 Interrupt Flag Register
+ $02 constant TIFR2_OCF2A \ Timer/Counter2 Output Compare Flag 2
+ $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
+&182 constant ASSR \ Asynchronous Status Register
+ $10 constant ASSR_EXCLK \ Enable External Clock Interrupt
+ $08 constant ASSR_AS2 \ AS2: Asynchronous Timer/Counter2
+ $04 constant ASSR_TCN2UB \ TCN2UB: Timer/Counter2 Update Busy
+ $02 constant ASSR_OCR2UB \ Output Compare Register2 Update Busy
+ $01 constant ASSR_TCR2UB \ TCR2UB: Timer/Counter Control Register2 Update Busy
+\ TIMER_COUNTER_1
+&128 constant TCCR1A \ Timer/Counter1 Control Register A
+ $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
+ $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
+ $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
+&129 constant TCCR1B \ Timer/Counter1 Control Register B
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
+ $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
+&130 constant TCCR1C \ Timer/Counter 1 Control Register C
+ $80 constant TCCR1C_FOC1A \ Force Output Compare 1A
+ $40 constant TCCR1C_FOC1B \ Force Output Compare 1B
+&132 constant TCNT1 \ Timer/Counter1 Bytes
+&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
+&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
+&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
+&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
+ $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
+ $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
+ $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
+ $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
+&54 constant TIFR1 \ Timer/Counter1 Interrupt Flag register
+ $20 constant TIFR1_ICF1 \ Input Capture Flag 1
+ $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
+ $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
+ $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
+\ WATCHDOG
+&96 constant WDTCR \ Watchdog Timer Control Register
+ $10 constant WDTCR_WDCE \ Watchdog Change Enable
+ $08 constant WDTCR_WDE \ Watch Dog Enable
+ $07 constant WDTCR_WDP \ Watch Dog Timer Prescaler bits
+\ BOOT_LOAD
+&87 constant SPMCSR \ Store Program Memory Control Register
+ $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
+ $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
+ $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
+ $04 constant SPMCSR_PGWRT \ Page Write
+ $02 constant SPMCSR_PGERS \ Page Erase
+ $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
+\ USART0
+&198 constant UDR0 \ USART I/O Data Register
+&192 constant UCSR0A \ USART Control and Status Register A
+ $80 constant UCSR0A_RXC0 \ USART Receive Complete
+ $40 constant UCSR0A_TXC0 \ USART Transmit Complete
+ $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
+ $10 constant UCSR0A_FE0 \ Framing Error
+ $08 constant UCSR0A_DOR0 \ Data OverRun
+ $04 constant UCSR0A_UPE0 \ USART Parity Error
+ $02 constant UCSR0A_U2X0 \ Double the USART Transmission Speed
+ $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
+&193 constant UCSR0B \ USART Control and Status Register B
+ $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
+ $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
+ $20 constant UCSR0B_UDRIE0 \ USART Data Register Empty Interrupt Enable
+ $10 constant UCSR0B_RXEN0 \ Receiver Enable
+ $08 constant UCSR0B_TXEN0 \ Transmitter Enable
+ $04 constant UCSR0B_UCSZ02 \ Character Size
+ $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
+ $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
+&194 constant UCSR0C \ USART Control and Status Register C
+ $40 constant UCSR0C_UMSEL0 \ USART Mode Select
+ $30 constant UCSR0C_UPM0 \ Parity Mode Bits
+ $08 constant UCSR0C_USBS0 \ Stop Bit Select
+ $06 constant UCSR0C_UCSZ0 \ Character Size
+ $01 constant UCSR0C_UCPOL0 \ Clock Polarity
+&196 constant UBRR0 \ USART Baud Rate Register Bytes
+
+\ Interrupts
+&2 constant INT0Addr \ External Interrupt Request 0
+&4 constant PCINT0Addr \ Pin Change Interrupt Request 0
+&6 constant PCINT1Addr \ Pin Change Interrupt Request 1
+&8 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
+&10 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
+&12 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+&14 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
+&16 constant TIMER1_COMPBAddr \ Timer/Counter Compare Match B
+&18 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+&20 constant TIMER0_COMPAddr \ Timer/Counter0 Compare Match
+&22 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
+&24 constant SPI__STCAddr \ SPI Serial Transfer Complete
+&26 constant USART0__RXAddr \ USART0, Rx Complete
+&28 constant USART0__UDREAddr \ USART0 Data register Empty
+&30 constant USART0__TXAddr \ USART0, Tx Complete
+&32 constant USI_STARTAddr \ USI Start Condition
+&34 constant USI_OVERFLOWAddr \ USI Overflow
+&36 constant ANALOG_COMPAddr \ Analog Comparator
+&38 constant ADCAddr \ ADC Conversion Complete
+&40 constant EE_READYAddr \ EEPROM Ready
+&42 constant SPM_READYAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/atmega645p/device.asm b/amforth-6.5/avr8/devices/atmega645p/device.asm
new file mode 100644
index 0000000..781e099
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega645p/device.asm
@@ -0,0 +1,106 @@
+; Partname: ATmega645P
+; generated automatically, do not edit
+
+.nolist
+ .include "m645Pdef.inc"
+.list
+
+.equ ramstart = 256
+.equ CELLSIZE = 2
+.macro readflashcell
+ lsl zl
+ rol zh
+ lpm @0, Z+
+ lpm @1, Z+
+.endmacro
+.macro writeflashcell
+ lsl zl
+ rol zh
+.endmacro
+.set WANT_AD_CONVERTER = 0
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_SPI = 0
+.set WANT_USI = 0
+.set WANT_CPU = 0
+.set WANT_JTAG = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_EEPROM = 0
+.set WANT_PORTA = 0
+.set WANT_PORTB = 0
+.set WANT_PORTC = 0
+.set WANT_PORTD = 0
+.set WANT_PORTE = 0
+.set WANT_PORTF = 0
+.set WANT_PORTG = 0
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_TIMER_COUNTER_2 = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_WATCHDOG = 0
+.set WANT_BOOT_LOAD = 0
+.set WANT_USART0 = 0
+.equ intvecsize = 2 ; please verify; flash size: 65536 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.org 2
+ rcall isr ; External Interrupt Request 0
+.org 4
+ rcall isr ; Pin Change Interrupt Request 0
+.org 6
+ rcall isr ; Pin Change Interrupt Request 1
+.org 8
+ rcall isr ; Timer/Counter2 Compare Match
+.org 10
+ rcall isr ; Timer/Counter2 Overflow
+.org 12
+ rcall isr ; Timer/Counter1 Capture Event
+.org 14
+ rcall isr ; Timer/Counter1 Compare Match A
+.org 16
+ rcall isr ; Timer/Counter Compare Match B
+.org 18
+ rcall isr ; Timer/Counter1 Overflow
+.org 20
+ rcall isr ; Timer/Counter0 Compare Match
+.org 22
+ rcall isr ; Timer/Counter0 Overflow
+.org 24
+ rcall isr ; SPI Serial Transfer Complete
+.org 26
+ rcall isr ; USART0, Rx Complete
+.org 28
+ rcall isr ; USART0 Data register Empty
+.org 30
+ rcall isr ; USART0, Tx Complete
+.org 32
+ rcall isr ; USI Start Condition
+.org 34
+ rcall isr ; USI Overflow
+.org 36
+ rcall isr ; Analog Comparator
+.org 38
+ rcall isr ; ADC Conversion Complete
+.org 40
+ rcall isr ; EEPROM Ready
+.org 42
+ rcall isr ; Store Program Memory Read
+.equ INTVECTORS = 22
+.nooverlap
+
+; compatability layer (maybe empty)
+.equ EEPE = EEWE
+.equ EEMPE = EEMWE
+
+; controller data area, environment query mcu-info
+mcu_info:
+mcu_ramsize:
+ .dw 4096
+mcu_eepromsize:
+ .dw 2048
+mcu_maxdp:
+ .dw 57344
+mcu_numints:
+ .dw 22
+mcu_name:
+ .dw 10
+ .db "ATmega645P"
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega645p/device.inc b/amforth-6.5/avr8/devices/atmega645p/device.inc
new file mode 100644
index 0000000..582f84a
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega645p/device.inc
@@ -0,0 +1,1050 @@
+; Partname: ATmega645P
+; generated automatically, no not edit
+
+.if WANT_AD_CONVERTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC multiplexer Selection Register
+VE_ADMUX:
+ .dw $ff05
+ .db "ADMUX",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADMUX
+XT_ADMUX:
+ .dw PFA_DOVARIABLE
+PFA_ADMUX:
+ .dw 124
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register
+VE_ADCSRA:
+ .dw $ff06
+ .db "ADCSRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRA
+XT_ADCSRA:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRA:
+ .dw 122
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register Bytes
+VE_ADC:
+ .dw $ff03
+ .db "ADC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADC
+XT_ADC:
+ .dw PFA_DOVARIABLE
+PFA_ADC:
+ .dw 120
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Control and Status Register B
+VE_ADCSRB:
+ .dw $ff06
+ .db "ADCSRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRB
+XT_ADCSRB:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRB:
+ .dw 123
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 0
+VE_DIDR0:
+ .dw $ff05
+ .db "DIDR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR0
+XT_DIDR0:
+ .dw PFA_DOVARIABLE
+PFA_DIDR0:
+ .dw 126
+
+.endif
+.if WANT_ANALOG_COMPARATOR == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Control And Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw 80
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 1
+VE_DIDR1:
+ .dw $ff05
+ .db "DIDR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR1
+XT_DIDR1:
+ .dw PFA_DOVARIABLE
+PFA_DIDR1:
+ .dw 127
+
+.endif
+.if WANT_SPI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR:
+ .dw $ff04
+ .db "SPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR
+XT_SPCR:
+ .dw PFA_DOVARIABLE
+PFA_SPCR:
+ .dw 76
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR:
+ .dw $ff04
+ .db "SPSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR
+XT_SPSR:
+ .dw PFA_DOVARIABLE
+PFA_SPSR:
+ .dw 77
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR:
+ .dw $ff04
+ .db "SPDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR
+XT_SPDR:
+ .dw PFA_DOVARIABLE
+PFA_SPDR:
+ .dw 78
+
+.endif
+.if WANT_USI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USI Data Register
+VE_USIDR:
+ .dw $ff05
+ .db "USIDR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USIDR
+XT_USIDR:
+ .dw PFA_DOVARIABLE
+PFA_USIDR:
+ .dw 186
+; ( -- addr ) System Constant
+; R( -- )
+; USI Status Register
+VE_USISR:
+ .dw $ff05
+ .db "USISR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USISR
+XT_USISR:
+ .dw PFA_DOVARIABLE
+PFA_USISR:
+ .dw 185
+; ( -- addr ) System Constant
+; R( -- )
+; USI Control Register
+VE_USICR:
+ .dw $ff05
+ .db "USICR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USICR
+XT_USICR:
+ .dw PFA_DOVARIABLE
+PFA_USICR:
+ .dw 184
+
+.endif
+.if WANT_CPU == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw 95
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer
+VE_SP:
+ .dw $ff02
+ .db "SP"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SP
+XT_SP:
+ .dw PFA_DOVARIABLE
+PFA_SP:
+ .dw 93
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw 85
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Status Register
+VE_MCUSR:
+ .dw $ff05
+ .db "MCUSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUSR
+XT_MCUSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUSR:
+ .dw 84
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Calibration Value
+VE_OSCCAL:
+ .dw $ff06
+ .db "OSCCAL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSCCAL
+XT_OSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_OSCCAL:
+ .dw 102
+; ( -- addr ) System Constant
+; R( -- )
+; Clock Prescale Register
+VE_CLKPR:
+ .dw $ff05
+ .db "CLKPR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKPR
+XT_CLKPR:
+ .dw PFA_DOVARIABLE
+PFA_CLKPR:
+ .dw 97
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register
+VE_PRR:
+ .dw $ff03
+ .db "PRR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR
+XT_PRR:
+ .dw PFA_DOVARIABLE
+PFA_PRR:
+ .dw 100
+; ( -- addr ) System Constant
+; R( -- )
+; Sleep Mode Control Register
+VE_SMCR:
+ .dw $ff04
+ .db "SMCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SMCR
+XT_SMCR:
+ .dw PFA_DOVARIABLE
+PFA_SMCR:
+ .dw 83
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 2
+VE_GPIOR2:
+ .dw $ff06
+ .db "GPIOR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR2
+XT_GPIOR2:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR2:
+ .dw 75
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 1
+VE_GPIOR1:
+ .dw $ff06
+ .db "GPIOR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR1
+XT_GPIOR1:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR1:
+ .dw 74
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 0
+VE_GPIOR0:
+ .dw $ff06
+ .db "GPIOR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR0
+XT_GPIOR0:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR0:
+ .dw 62
+
+.endif
+.if WANT_JTAG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; On-Chip Debug Related Register in I/O Memory
+VE_OCDR:
+ .dw $ff04
+ .db "OCDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCDR
+XT_OCDR:
+ .dw PFA_DOVARIABLE
+PFA_OCDR:
+ .dw 81
+
+.endif
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register A
+VE_EICRA:
+ .dw $ff05
+ .db "EICRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRA
+XT_EICRA:
+ .dw PFA_DOVARIABLE
+PFA_EICRA:
+ .dw 105
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Mask Register
+VE_EIMSK:
+ .dw $ff05
+ .db "EIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIMSK
+XT_EIMSK:
+ .dw PFA_DOVARIABLE
+PFA_EIMSK:
+ .dw 61
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Flag Register
+VE_EIFR:
+ .dw $ff04
+ .db "EIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIFR
+XT_EIFR:
+ .dw PFA_DOVARIABLE
+PFA_EIFR:
+ .dw 60
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 1
+VE_PCMSK1:
+ .dw $ff06
+ .db "PCMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK1
+XT_PCMSK1:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK1:
+ .dw 108
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 0
+VE_PCMSK0:
+ .dw $ff06
+ .db "PCMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK0
+XT_PCMSK0:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK0:
+ .dw 107
+
+.endif
+.if WANT_EEPROM == 1
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Read/Write Access Bytes
+VE_EEAR:
+ .dw $ff04
+ .db "EEAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEAR
+XT_EEAR:
+ .dw PFA_DOVARIABLE
+PFA_EEAR:
+ .dw 65
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw 64
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw 63
+
+.endif
+.if WANT_PORTA == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Register
+VE_PORTA:
+ .dw $ff05
+ .db "PORTA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTA
+XT_PORTA:
+ .dw PFA_DOVARIABLE
+PFA_PORTA:
+ .dw 34
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Direction Register
+VE_DDRA:
+ .dw $ff04
+ .db "DDRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRA
+XT_DDRA:
+ .dw PFA_DOVARIABLE
+PFA_DDRA:
+ .dw 33
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Input Pins
+VE_PINA:
+ .dw $ff04
+ .db "PINA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINA
+XT_PINA:
+ .dw PFA_DOVARIABLE
+PFA_PINA:
+ .dw 32
+
+.endif
+.if WANT_PORTB == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw 37
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw 36
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw 35
+
+.endif
+.if WANT_PORTC == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Register
+VE_PORTC:
+ .dw $ff05
+ .db "PORTC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTC
+XT_PORTC:
+ .dw PFA_DOVARIABLE
+PFA_PORTC:
+ .dw 40
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Direction Register
+VE_DDRC:
+ .dw $ff04
+ .db "DDRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRC
+XT_DDRC:
+ .dw PFA_DOVARIABLE
+PFA_DDRC:
+ .dw 39
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Input Pins
+VE_PINC:
+ .dw $ff04
+ .db "PINC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINC
+XT_PINC:
+ .dw PFA_DOVARIABLE
+PFA_PINC:
+ .dw 38
+
+.endif
+.if WANT_PORTD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw 43
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw 42
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw 41
+
+.endif
+.if WANT_PORTE == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port E
+VE_PORTE:
+ .dw $ff05
+ .db "PORTE",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTE
+XT_PORTE:
+ .dw PFA_DOVARIABLE
+PFA_PORTE:
+ .dw 46
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port E
+VE_DDRE:
+ .dw $ff04
+ .db "DDRE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRE
+XT_DDRE:
+ .dw PFA_DOVARIABLE
+PFA_DDRE:
+ .dw 45
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port E
+VE_PINE:
+ .dw $ff04
+ .db "PINE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINE
+XT_PINE:
+ .dw PFA_DOVARIABLE
+PFA_PINE:
+ .dw 44
+
+.endif
+.if WANT_PORTF == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port F
+VE_PORTF:
+ .dw $ff05
+ .db "PORTF",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTF
+XT_PORTF:
+ .dw PFA_DOVARIABLE
+PFA_PORTF:
+ .dw 49
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port F
+VE_DDRF:
+ .dw $ff04
+ .db "DDRF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRF
+XT_DDRF:
+ .dw PFA_DOVARIABLE
+PFA_DDRF:
+ .dw 48
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port F
+VE_PINF:
+ .dw $ff04
+ .db "PINF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINF
+XT_PINF:
+ .dw PFA_DOVARIABLE
+PFA_PINF:
+ .dw 47
+
+.endif
+.if WANT_PORTG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Data Register
+VE_PORTG:
+ .dw $ff05
+ .db "PORTG",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTG
+XT_PORTG:
+ .dw PFA_DOVARIABLE
+PFA_PORTG:
+ .dw 52
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Data Direction Register
+VE_DDRG:
+ .dw $ff04
+ .db "DDRG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRG
+XT_DDRG:
+ .dw PFA_DOVARIABLE
+PFA_DDRG:
+ .dw 51
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Input Pins
+VE_PING:
+ .dw $ff04
+ .db "PING"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PING
+XT_PING:
+ .dw PFA_DOVARIABLE
+PFA_PING:
+ .dw 50
+
+.endif
+.if WANT_TIMER_COUNTER_0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Control Register
+VE_TCCR0A:
+ .dw $ff06
+ .db "TCCR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0A
+XT_TCCR0A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0A:
+ .dw 68
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw 70
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0A:
+ .dw $ff05
+ .db "OCR0A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0A
+XT_OCR0A:
+ .dw PFA_DOVARIABLE
+PFA_OCR0A:
+ .dw 71
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Mask Register
+VE_TIMSK0:
+ .dw $ff06
+ .db "TIMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK0
+XT_TIMSK0:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK0:
+ .dw 110
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Flag register
+VE_TIFR0:
+ .dw $ff05
+ .db "TIFR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR0
+XT_TIFR0:
+ .dw PFA_DOVARIABLE
+PFA_TIFR0:
+ .dw 53
+; ( -- addr ) System Constant
+; R( -- )
+; General Timer/Control Register
+VE_GTCCR:
+ .dw $ff05
+ .db "GTCCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GTCCR
+XT_GTCCR:
+ .dw PFA_DOVARIABLE
+PFA_GTCCR:
+ .dw 67
+
+.endif
+.if WANT_TIMER_COUNTER_2 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register
+VE_TCCR2A:
+ .dw $ff06
+ .db "TCCR2A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2A
+XT_TCCR2A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2A:
+ .dw 176
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2
+VE_TCNT2:
+ .dw $ff05
+ .db "TCNT2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT2
+XT_TCNT2:
+ .dw PFA_DOVARIABLE
+PFA_TCNT2:
+ .dw 178
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register
+VE_OCR2A:
+ .dw $ff05
+ .db "OCR2A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2A
+XT_OCR2A:
+ .dw PFA_DOVARIABLE
+PFA_OCR2A:
+ .dw 179
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Interrupt Mask register
+VE_TIMSK2:
+ .dw $ff06
+ .db "TIMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK2
+XT_TIMSK2:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK2:
+ .dw 112
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Interrupt Flag Register
+VE_TIFR2:
+ .dw $ff05
+ .db "TIFR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR2
+XT_TIFR2:
+ .dw PFA_DOVARIABLE
+PFA_TIFR2:
+ .dw 55
+; ( -- addr ) System Constant
+; R( -- )
+; Asynchronous Status Register
+VE_ASSR:
+ .dw $ff04
+ .db "ASSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ASSR
+XT_ASSR:
+ .dw PFA_DOVARIABLE
+PFA_ASSR:
+ .dw 182
+
+.endif
+.if WANT_TIMER_COUNTER_1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw 128
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw 129
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter 1 Control Register C
+VE_TCCR1C:
+ .dw $ff06
+ .db "TCCR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1C
+XT_TCCR1C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1C:
+ .dw 130
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Bytes
+VE_TCNT1:
+ .dw $ff05
+ .db "TCNT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1
+XT_TCNT1:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1:
+ .dw 132
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register A Bytes
+VE_OCR1A:
+ .dw $ff05
+ .db "OCR1A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1A
+XT_OCR1A:
+ .dw PFA_DOVARIABLE
+PFA_OCR1A:
+ .dw 136
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register B Bytes
+VE_OCR1B:
+ .dw $ff05
+ .db "OCR1B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1B
+XT_OCR1B:
+ .dw PFA_DOVARIABLE
+PFA_OCR1B:
+ .dw 138
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Bytes
+VE_ICR1:
+ .dw $ff04
+ .db "ICR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1
+XT_ICR1:
+ .dw PFA_DOVARIABLE
+PFA_ICR1:
+ .dw 134
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Mask Register
+VE_TIMSK1:
+ .dw $ff06
+ .db "TIMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK1
+XT_TIMSK1:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK1:
+ .dw 111
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Flag register
+VE_TIFR1:
+ .dw $ff05
+ .db "TIFR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR1
+XT_TIFR1:
+ .dw PFA_DOVARIABLE
+PFA_TIFR1:
+ .dw 54
+
+.endif
+.if WANT_WATCHDOG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCR:
+ .dw $ff05
+ .db "WDTCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCR
+XT_WDTCR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCR:
+ .dw 96
+
+.endif
+.if WANT_BOOT_LOAD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control Register
+VE_SPMCSR:
+ .dw $ff06
+ .db "SPMCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCSR
+XT_SPMCSR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCSR:
+ .dw 87
+
+.endif
+.if WANT_USART0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR0:
+ .dw $ff04
+ .db "UDR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR0
+XT_UDR0:
+ .dw PFA_DOVARIABLE
+PFA_UDR0:
+ .dw 198
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR0A:
+ .dw $ff06
+ .db "UCSR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0A
+XT_UCSR0A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0A:
+ .dw 192
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR0B:
+ .dw $ff06
+ .db "UCSR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0B
+XT_UCSR0B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0B:
+ .dw 193
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR0C:
+ .dw $ff06
+ .db "UCSR0C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0C
+XT_UCSR0C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0C:
+ .dw 194
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Bytes
+VE_UBRR0:
+ .dw $ff05
+ .db "UBRR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR0
+XT_UBRR0:
+ .dw PFA_DOVARIABLE
+PFA_UBRR0:
+ .dw 196
+
+.endif
diff --git a/amforth-6.5/avr8/devices/atmega645p/device.py b/amforth-6.5/avr8/devices/atmega645p/device.py
new file mode 100644
index 0000000..30061eb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega645p/device.py
@@ -0,0 +1,318 @@
+# Generated Automatically
+
+# Partname ATmega645P
+
+MCUREGS = {
+# Interrupt Vectors
+ 'INT0Addr' : '#2', # External Interrupt Request 0
+ 'PCINT0Addr' : '#4', # Pin Change Interrupt Request 0
+ 'PCINT1Addr' : '#6', # Pin Change Interrupt Request 1
+ 'TIMER2_COMPAddr' : '#8', # Timer/Counter2 Compare Match
+ 'TIMER2_OVFAddr' : '#10', # Timer/Counter2 Overflow
+ 'TIMER1_CAPTAddr' : '#12', # Timer/Counter1 Capture Event
+ 'TIMER1_COMPAAddr' : '#14', # Timer/Counter1 Compare Match A
+ 'TIMER1_COMPBAddr' : '#16', # Timer/Counter Compare Match B
+ 'TIMER1_OVFAddr' : '#18', # Timer/Counter1 Overflow
+ 'TIMER0_COMPAddr' : '#20', # Timer/Counter0 Compare Match
+ 'TIMER0_OVFAddr' : '#22', # Timer/Counter0 Overflow
+ 'SPI_STCAddr' : '#24', # SPI Serial Transfer Complete
+ 'USART0_RXAddr' : '#26', # USART0, Rx Complete
+ 'USART0_UDREAddr' : '#28', # USART0 Data register Empty
+ 'USART0_TXAddr' : '#30', # USART0, Tx Complete
+ 'USI_STARTAddr' : '#32', # USI Start Condition
+ 'USI_OVERFLOWAddr' : '#34', # USI Overflow
+ 'ANALOG_COMPAddr' : '#36', # Analog Comparator
+ 'ADCAddr' : '#38', # ADC Conversion Complete
+ 'EE_READYAddr' : '#40', # EEPROM Ready
+ 'SPM_READYAddr' : '#42', # Store Program Memory Read
+
+# Module AD_CONVERTER
+ 'ADMUX' : '$7c', # The ADC multiplexer Selection
+ 'ADMUX_REFS': '$c0', # Reference Selection Bits
+ 'ADMUX_ADLAR': '$20', # Left Adjust Result
+ 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
+ 'ADCSRA' : '$7a', # The ADC Control and Status reg
+ 'ADCSRA_ADEN': '$80', # ADC Enable
+ 'ADCSRA_ADSC': '$40', # ADC Start Conversion
+ 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
+ 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
+ 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
+ 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
+ 'ADC' : '$78', # ADC Data Register Bytes
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Sources
+ 'DIDR0' : '$7e', # Digital Input Disable Register
+ 'DIDR0_ADC7D': '$80', # ADC7 Digital input Disable
+ 'DIDR0_ADC6D': '$40', # ADC6 Digital input Disable
+ 'DIDR0_ADC5D': '$20', # ADC5 Digital input Disable
+ 'DIDR0_ADC4D': '$10', # ADC4 Digital input Disable
+ 'DIDR0_ADC3D': '$8', # ADC3 Digital input Disable
+ 'DIDR0_ADC2D': '$4', # ADC2 Digital input Disable
+ 'DIDR0_ADC1D': '$2', # ADC1 Digital input Disable
+ 'DIDR0_ADC0D': '$1', # ADC0 Digital input Disable
+
+# Module ANALOG_COMPARATOR
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
+ 'ACSR' : '$50', # Analog Comparator Control And
+ 'ACSR_ACD': '$80', # Analog Comparator Disable
+ 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
+ 'ACSR_ACO': '$20', # Analog Compare Output
+ 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
+ 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
+ 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
+ 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
+ 'DIDR1' : '$7f', # Digital Input Disable Register
+ 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
+ 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
+
+# Module SPI
+ 'SPCR' : '$4c', # SPI Control Register
+ 'SPCR_SPIE': '$80', # SPI Interrupt Enable
+ 'SPCR_SPE': '$40', # SPI Enable
+ 'SPCR_DORD': '$20', # Data Order
+ 'SPCR_MSTR': '$10', # Master/Slave Select
+ 'SPCR_CPOL': '$8', # Clock polarity
+ 'SPCR_CPHA': '$4', # Clock Phase
+ 'SPCR_SPR': '$3', # SPI Clock Rate Selects
+ 'SPSR' : '$4d', # SPI Status Register
+ 'SPSR_SPIF': '$80', # SPI Interrupt Flag
+ 'SPSR_WCOL': '$40', # Write Collision Flag
+ 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
+ 'SPDR' : '$4e', # SPI Data Register
+
+# Module USI
+ 'USIDR' : '$ba', # USI Data Register
+ 'USISR' : '$b9', # USI Status Register
+ 'USISR_USISIF': '$80', # Start Condition Interrupt Flag
+ 'USISR_USIOIF': '$40', # Counter Overflow Interrupt Fla
+ 'USISR_USIPF': '$20', # Stop Condition Flag
+ 'USISR_USIDC': '$10', # Data Output Collision
+ 'USISR_USICNT': '$f', # USI Counter Value Bits
+ 'USICR' : '$b8', # USI Control Register
+ 'USICR_USISIE': '$80', # Start Condition Interrupt Enab
+ 'USICR_USIOIE': '$40', # Counter Overflow Interrupt Ena
+ 'USICR_USIWM': '$30', # USI Wire Mode Bits
+ 'USICR_USICS': '$c', # USI Clock Source Select Bits
+ 'USICR_USICLK': '$2', # Clock Strobe
+ 'USICR_USITC': '$1', # Toggle Clock Port Pin
+
+# Module CPU
+ 'SREG' : '$5f', # Status Register
+ 'SREG_I': '$80', # Global Interrupt Enable
+ 'SREG_T': '$40', # Bit Copy Storage
+ 'SREG_H': '$20', # Half Carry Flag
+ 'SREG_S': '$10', # Sign Bit
+ 'SREG_V': '$8', # Two's Complement Overflow Flag
+ 'SREG_N': '$4', # Negative Flag
+ 'SREG_Z': '$2', # Zero Flag
+ 'SREG_C': '$1', # Carry Flag
+ 'SP' : '$5d', # Stack Pointer
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_PUD': '$10', # Pull-up disable
+ 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
+ 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+ 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
+ 'MCUSR_BORF': '$4', # Brown-out Reset Flag
+ 'MCUSR_EXTRF': '$2', # External Reset Flag
+ 'MCUSR_PORF': '$1', # Power-on reset flag
+ 'OSCCAL' : '$66', # Oscillator Calibration Value
+ 'CLKPR' : '$61', # Clock Prescale Register
+ 'CLKPR_CLKPCE': '$80', # Clock Prescaler Change Enable
+ 'CLKPR_CLKPS': '$f', # Clock Prescaler Select Bits
+ 'PRR' : '$64', # Power Reduction Register
+ 'PRR_PRLCD': '$10', # Power Reduction LCD
+ 'PRR_PRTIM1': '$8', # Power Reduction Timer/Counter1
+ 'PRR_PRSPI': '$4', # Power Reduction Serial Periphe
+ 'PRR_PRUSART0': '$2', # Power Reduction USART
+ 'PRR_PRADC': '$1', # Power Reduction ADC
+ 'SMCR' : '$53', # Sleep Mode Control Register
+ 'SMCR_SM': '$e', # Sleep Mode Select bits
+ 'SMCR_SE': '$1', # Sleep Enable
+ 'GPIOR2' : '$4b', # General Purpose IO Register 2
+ 'GPIOR1' : '$4a', # General Purpose IO Register 1
+ 'GPIOR0' : '$3e', # General Purpose IO Register 0
+
+# Module JTAG
+ 'OCDR' : '$51', # On-Chip Debug Related Register
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_JTD': '$80', # JTAG Interface Disable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+
+# Module EXTERNAL_INTERRUPT
+ 'EICRA' : '$69', # External Interrupt Control Reg
+ 'EICRA_ISC01': '$2', # External Interrupt Sense Contr
+ 'EICRA_ISC00': '$1', # External Interrupt Sense Contr
+ 'EIMSK' : '$3d', # External Interrupt Mask Regist
+ 'EIMSK_PCIE': '$f0', # Pin Change Interrupt Enables
+ 'EIMSK_INT0': '$1', # External Interrupt Request 0 E
+ 'EIFR' : '$3c', # External Interrupt Flag Regist
+ 'EIFR_PCIF': '$f0', # Pin Change Interrupt Flags
+ 'EIFR_INTF0': '$1', # External Interrupt Flag 0
+ 'PCMSK1' : '$6c', # Pin Change Mask Register 1
+ 'PCMSK0' : '$6b', # Pin Change Mask Register 0
+
+# Module EEPROM
+ 'EEAR' : '$41', # EEPROM Read/Write Access Byte
+ 'EEDR' : '$40', # EEPROM Data Register
+ 'EECR' : '$3f', # EEPROM Control Register
+ 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
+ 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
+ 'EECR_EEWE': '$2', # EEPROM Write Enable
+ 'EECR_EERE': '$1', # EEPROM Read Enable
+
+# Module PORTA
+ 'PORTA' : '$22', # Port A Data Register
+ 'DDRA' : '$21', # Port A Data Direction Register
+ 'PINA' : '$20', # Port A Input Pins
+
+# Module PORTB
+ 'PORTB' : '$25', # Port B Data Register
+ 'DDRB' : '$24', # Port B Data Direction Register
+ 'PINB' : '$23', # Port B Input Pins
+
+# Module PORTC
+ 'PORTC' : '$28', # Port C Data Register
+ 'DDRC' : '$27', # Port C Data Direction Register
+ 'PINC' : '$26', # Port C Input Pins
+
+# Module PORTD
+ 'PORTD' : '$2b', # Port D Data Register
+ 'DDRD' : '$2a', # Port D Data Direction Register
+ 'PIND' : '$29', # Port D Input Pins
+
+# Module PORTE
+ 'PORTE' : '$2e', # Data Register, Port E
+ 'DDRE' : '$2d', # Data Direction Register, Port
+ 'PINE' : '$2c', # Input Pins, Port E
+
+# Module PORTF
+ 'PORTF' : '$31', # Data Register, Port F
+ 'DDRF' : '$30', # Data Direction Register, Port
+ 'PINF' : '$2f', # Input Pins, Port F
+
+# Module PORTG
+ 'PORTG' : '$34', # Port G Data Register
+ 'DDRG' : '$33', # Port G Data Direction Register
+ 'PING' : '$32', # Port G Input Pins
+
+# Module TIMER_COUNTER_0
+ 'TCCR0A' : '$44', # Timer/Counter0 Control Registe
+ 'TCCR0A_FOC0A': '$80', # Force Output Compare
+ 'TCCR0A_WGM00': '$40', # Waveform Generation Mode 0
+ 'TCCR0A_COM0A': '$30', # Compare Match Output Modes
+ 'TCCR0A_WGM01': '$8', # Waveform Generation Mode 1
+ 'TCCR0A_CS0': '$7', # Clock Selects
+ 'TCNT0' : '$46', # Timer/Counter0
+ 'OCR0A' : '$47', # Timer/Counter0 Output Compare
+ 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
+ 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
+ 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
+ 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
+ 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
+ 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Control Register
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSR310': '$1', # Prescaler Reset Timer/Counter1
+
+# Module TIMER_COUNTER_2
+ 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
+ 'TCCR2A_FOC2A': '$80', # Force Output Compare A
+ 'TCCR2A_WGM20': '$40', # Waveform Generation Mode
+ 'TCCR2A_COM2A': '$30', # Compare Output Mode bits
+ 'TCCR2A_WGM21': '$8', # Waveform Generation Mode
+ 'TCCR2A_CS2': '$7', # Clock Select bits
+ 'TCNT2' : '$b2', # Timer/Counter2
+ 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
+ 'TIMSK2' : '$70', # Timer/Counter2 Interrupt Mask
+ 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
+ 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
+ 'TIFR2' : '$37', # Timer/Counter2 Interrupt Flag
+ 'TIFR2_OCF2A': '$2', # Timer/Counter2 Output Compare
+ 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_PSR2': '$2', # Prescaler Reset Timer/Counter2
+ 'ASSR' : '$b6', # Asynchronous Status Register
+ 'ASSR_EXCLK': '$10', # Enable External Clock Interrup
+ 'ASSR_AS2': '$8', # AS2: Asynchronous Timer/Counte
+ 'ASSR_TCN2UB': '$4', # TCN2UB: Timer/Counter2 Update
+ 'ASSR_OCR2UB': '$2', # Output Compare Register2 Updat
+ 'ASSR_TCR2UB': '$1', # TCR2UB: Timer/Counter Control
+
+# Module TIMER_COUNTER_1
+ 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
+ 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
+ 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
+ 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
+ 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
+ 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
+ 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
+ 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
+ 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
+ 'TCCR1C' : '$82', # Timer/Counter 1 Control Regist
+ 'TCCR1C_FOC1A': '$80', # Force Output Compare 1A
+ 'TCCR1C_FOC1B': '$40', # Force Output Compare 1B
+ 'TCNT1' : '$84', # Timer/Counter1 Bytes
+ 'OCR1A' : '$88', # Timer/Counter1 Output Compare
+ 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
+ 'ICR1' : '$86', # Timer/Counter1 Input Capture R
+ 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
+ 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
+ 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
+ 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
+ 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
+ 'TIFR1' : '$36', # Timer/Counter1 Interrupt Flag
+ 'TIFR1_ICF1': '$20', # Input Capture Flag 1
+ 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
+ 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
+ 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
+
+# Module WATCHDOG
+ 'WDTCR' : '$60', # Watchdog Timer Control Registe
+ 'WDTCR_WDCE': '$10', # Watchdog Change Enable
+ 'WDTCR_WDE': '$8', # Watch Dog Enable
+ 'WDTCR_WDP': '$7', # Watch Dog Timer Prescaler bits
+
+# Module BOOT_LOAD
+ 'SPMCSR' : '$57', # Store Program Memory Control R
+ 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
+ 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
+ 'SPMCSR_RWWSRE': '$10', # Read While Write section read
+ 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
+ 'SPMCSR_PGWRT': '$4', # Page Write
+ 'SPMCSR_PGERS': '$2', # Page Erase
+ 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
+
+# Module USART0
+ 'UDR0' : '$c6', # USART I/O Data Register
+ 'UCSR0A' : '$c0', # USART Control and Status Regis
+ 'UCSR0A_RXC0': '$80', # USART Receive Complete
+ 'UCSR0A_TXC0': '$40', # USART Transmit Complete
+ 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
+ 'UCSR0A_FE0': '$10', # Framing Error
+ 'UCSR0A_DOR0': '$8', # Data OverRun
+ 'UCSR0A_UPE0': '$4', # USART Parity Error
+ 'UCSR0A_U2X0': '$2', # Double the USART Transmission
+ 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
+ 'UCSR0B' : '$c1', # USART Control and Status Regis
+ 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
+ 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
+ 'UCSR0B_UDRIE0': '$20', # USART Data Register Empty Inte
+ 'UCSR0B_RXEN0': '$10', # Receiver Enable
+ 'UCSR0B_TXEN0': '$8', # Transmitter Enable
+ 'UCSR0B_UCSZ02': '$4', # Character Size
+ 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
+ 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
+ 'UCSR0C' : '$c2', # USART Control and Status Regis
+ 'UCSR0C_UMSEL0': '$40', # USART Mode Select
+ 'UCSR0C_UPM0': '$30', # Parity Mode Bits
+ 'UCSR0C_USBS0': '$8', # Stop Bit Select
+ 'UCSR0C_UCSZ0': '$6', # Character Size
+ 'UCSR0C_UCPOL0': '$1', # Clock Polarity
+ 'UBRR0' : '$c4', # USART Baud Rate Register Byte
+
+ '__amforth_dummy':'0'
+}
diff --git a/amforth-6.5/avr8/devices/atmega645p/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega645p/words/no-jtag.asm
new file mode 100644
index 0000000..352a4bb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega645p/words/no-jtag.asm
@@ -0,0 +1,14 @@
+; ( -- )
+; ( -- )
+; MCU
+; disable jtag at runtime
+VE_NOJTAG:
+ .dw $FF05
+ .db "-jtag",0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOJTAG
+XT_NOJTAG:
+ .dw PFA_NOJTAG
+PFA_NOJTAG:
+
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega645p/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega645p/words/no-wdt.asm
new file mode 100644
index 0000000..4a12261
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega645p/words/no-wdt.asm
@@ -0,0 +1,22 @@
+; ( -- )
+; MCU
+; disable watch dog timer at runtime
+VE_NOWDT:
+ .dw $ff04
+ .db "-wdt"
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOWDT
+XT_NOWDT:
+ .dw PFA_NOWDT
+PFA_NOWDT:
+
+; Reset WDT
+ wdr
+; Write logical one to WDTOE and WDE
+ in_ temp1, WDTCR
+ ori temp1, (1<<WDTOE)|(1<<WDE)
+ out WDTCR, temp1
+; Turn off WDT
+ ldi temp1, (0<<WDE)
+ out_ WDTCR, temp1
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega645p/words/sleep.asm b/amforth-6.5/avr8/devices/atmega645p/words/sleep.asm
new file mode 100644
index 0000000..256249c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega645p/words/sleep.asm
@@ -0,0 +1,19 @@
+; ( mode -- )
+; MCU
+; put the controller into the specified sleep mode
+VE_SLEEP:
+ .dw $ff05
+ .db "sleep", 0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_SLEEP
+XT_SLEEP:
+ .dw PFA_SLEEP
+PFA_SLEEP:
+ andi tosl, 7 ; leave only legal mode bits
+ lsl tosl ; move to correct location (bits 3-1)
+ ori tosl, 1 ; set the SE bit
+ out_ SMCR, tosl ; set the sleep config
+ sleep ; nighty-night
+ out_ SMCR, zerol ; 0 protects against accidental sleeps
+ loadtos ; pop argument from stack
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega649/atmega649.frt b/amforth-6.5/avr8/devices/atmega649/atmega649.frt
new file mode 100644
index 0000000..56b7691
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega649/atmega649.frt
@@ -0,0 +1,318 @@
+\ Partname: ATmega649
+\ generated automatically
+
+\ AD_CONVERTER
+&124 constant ADMUX \ The ADC multiplexer Selection Register
+ $C0 constant ADMUX_REFS \ Reference Selection Bits
+ $20 constant ADMUX_ADLAR \ Left Adjust Result
+ $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
+&122 constant ADCSRA \ The ADC Control and Status register
+ $80 constant ADCSRA_ADEN \ ADC Enable
+ $40 constant ADCSRA_ADSC \ ADC Start Conversion
+ $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
+ $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
+ $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
+ $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
+&120 constant ADC \ ADC Data Register Bytes
+&123 constant ADCSRB \ ADC Control and Status Register B
+ $07 constant ADCSRB_ADTS \ ADC Auto Trigger Sources
+&126 constant DIDR0 \ Digital Input Disable Register 0
+ $80 constant DIDR0_ADC7D \ ADC7 Digital input Disable
+ $40 constant DIDR0_ADC6D \ ADC6 Digital input Disable
+ $20 constant DIDR0_ADC5D \ ADC5 Digital input Disable
+ $10 constant DIDR0_ADC4D \ ADC4 Digital input Disable
+ $08 constant DIDR0_ADC3D \ ADC3 Digital input Disable
+ $04 constant DIDR0_ADC2D \ ADC2 Digital input Disable
+ $02 constant DIDR0_ADC1D \ ADC1 Digital input Disable
+ $01 constant DIDR0_ADC0D \ ADC0 Digital input Disable
+\ ANALOG_COMPARATOR
+&80 constant ACSR \ Analog Comparator Control And Status Register
+ $80 constant ACSR_ACD \ Analog Comparator Disable
+ $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
+ $20 constant ACSR_ACO \ Analog Compare Output
+ $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
+ $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
+ $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
+ $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
+&127 constant DIDR1 \ Digital Input Disable Register 1
+ $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
+ $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
+\ SPI
+&76 constant SPCR \ SPI Control Register
+ $80 constant SPCR_SPIE \ SPI Interrupt Enable
+ $40 constant SPCR_SPE \ SPI Enable
+ $20 constant SPCR_DORD \ Data Order
+ $10 constant SPCR_MSTR \ Master/Slave Select
+ $08 constant SPCR_CPOL \ Clock polarity
+ $04 constant SPCR_CPHA \ Clock Phase
+ $03 constant SPCR_SPR \ SPI Clock Rate Selects
+&77 constant SPSR \ SPI Status Register
+ $80 constant SPSR_SPIF \ SPI Interrupt Flag
+ $40 constant SPSR_WCOL \ Write Collision Flag
+ $01 constant SPSR_SPI2X \ Double SPI Speed Bit
+&78 constant SPDR \ SPI Data Register
+\ USI
+&186 constant USIDR \ USI Data Register
+&185 constant USISR \ USI Status Register
+ $80 constant USISR_USISIF \ Start Condition Interrupt Flag
+ $40 constant USISR_USIOIF \ Counter Overflow Interrupt Flag
+ $20 constant USISR_USIPF \ Stop Condition Flag
+ $10 constant USISR_USIDC \ Data Output Collision
+ $0F constant USISR_USICNT \ USI Counter Value Bits
+&184 constant USICR \ USI Control Register
+ $80 constant USICR_USISIE \ Start Condition Interrupt Enable
+ $40 constant USICR_USIOIE \ Counter Overflow Interrupt Enable
+ $30 constant USICR_USIWM \ USI Wire Mode Bits
+ $0C constant USICR_USICS \ USI Clock Source Select Bits
+ $02 constant USICR_USICLK \ Clock Strobe
+ $01 constant USICR_USITC \ Toggle Clock Port Pin
+\ USART0
+&198 constant UDR0 \ USART I/O Data Register
+&192 constant UCSR0A \ USART Control and Status Register A
+ $80 constant UCSR0A_RXC0 \ USART Receive Complete
+ $40 constant UCSR0A_TXC0 \ USART Transmit Complete
+ $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
+ $10 constant UCSR0A_FE0 \ Framing Error
+ $08 constant UCSR0A_DOR0 \ Data OverRun
+ $04 constant UCSR0A_UPE0 \ USART Parity Error
+ $02 constant UCSR0A_U2X0 \ Double the USART Transmission Speed
+ $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
+&193 constant UCSR0B \ USART Control and Status Register B
+ $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
+ $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
+ $20 constant UCSR0B_UDRIE0 \ USART Data Register Empty Interrupt Enable
+ $10 constant UCSR0B_RXEN0 \ Receiver Enable
+ $08 constant UCSR0B_TXEN0 \ Transmitter Enable
+ $04 constant UCSR0B_UCSZ02 \ Character Size
+ $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
+ $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
+&194 constant UCSR0C \ USART Control and Status Register C
+ $40 constant UCSR0C_UMSEL0 \ USART Mode Select
+ $30 constant UCSR0C_UPM0 \ Parity Mode Bits
+ $08 constant UCSR0C_USBS0 \ Stop Bit Select
+ $06 constant UCSR0C_UCSZ0 \ Character Size
+ $01 constant UCSR0C_UCPOL0 \ Clock Polarity
+&196 constant UBRR0 \ USART Baud Rate Register Bytes
+\ CPU
+&95 constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ $08 constant SREG_V \ Two's Complement Overflow Flag
+ $04 constant SREG_N \ Negative Flag
+ $02 constant SREG_Z \ Zero Flag
+ $01 constant SREG_C \ Carry Flag
+&93 constant SP \ Stack Pointer
+&85 constant MCUCR \ MCU Control Register
+ $10 constant MCUCR_PUD \ Pull-up disable
+ $02 constant MCUCR_IVSEL \ Interrupt Vector Select
+ $01 constant MCUCR_IVCE \ Interrupt Vector Change Enable
+&84 constant MCUSR \ MCU Status Register
+ $10 constant MCUSR_JTRF \ JTAG Reset Flag
+ $08 constant MCUSR_WDRF \ Watchdog Reset Flag
+ $04 constant MCUSR_BORF \ Brown-out Reset Flag
+ $02 constant MCUSR_EXTRF \ External Reset Flag
+ $01 constant MCUSR_PORF \ Power-on reset flag
+&102 constant OSCCAL \ Oscillator Calibration Value
+&97 constant CLKPR \ Clock Prescale Register
+ $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable
+ $0F constant CLKPR_CLKPS \ Clock Prescaler Select Bits
+&100 constant PRR \ Power Reduction Register
+ $10 constant PRR_PRLCD \ Power Reduction LCD
+ $08 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
+ $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
+ $02 constant PRR_PRUSART0 \ Power Reduction USART
+ $01 constant PRR_PRADC \ Power Reduction ADC
+&83 constant SMCR \ Sleep Mode Control Register
+ $0E constant SMCR_SM \ Sleep Mode Select bits
+ $01 constant SMCR_SE \ Sleep Enable
+&75 constant GPIOR2 \ General Purpose IO Register 2
+&74 constant GPIOR1 \ General Purpose IO Register 1
+&62 constant GPIOR0 \ General Purpose IO Register 0
+\ JTAG
+&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
+\ LCD
+&254 constant LCDDR18 \ LCD Data Register 18
+&253 constant LCDDR17 \ LCD Data Register 17
+&252 constant LCDDR16 \ LCD Data Register 16
+&251 constant LCDDR15 \ LCD Data Register 15
+&249 constant LCDDR13 \ LCD Data Register 13
+&248 constant LCDDR12 \ LCD Data Register 12
+&247 constant LCDDR11 \ LCD Data Register 11
+&246 constant LCDDR10 \ LCD Data Register 10
+&244 constant LCDDR8 \ LCD Data Register 8
+&243 constant LCDDR7 \ LCD Data Register 7
+&242 constant LCDDR6 \ LCD Data Register 6
+&241 constant LCDDR5 \ LCD Data Register 5
+&239 constant LCDDR3 \ LCD Data Register 3
+&238 constant LCDDR2 \ LCD Data Register 2
+&237 constant LCDDR1 \ LCD Data Register 1
+&236 constant LCDDR0 \ LCD Data Register 0
+&231 constant LCDCCR \ LCD Contrast Control Register
+&230 constant LCDFRR \ LCD Frame Rate Register
+ $70 constant LCDFRR_LCDPS \ LCD Prescaler Selects
+ $07 constant LCDFRR_LCDCD \ LCD Clock Dividers
+&229 constant LCDCRB \ LCD Control and Status Register B
+ $80 constant LCDCRB_LCDCS \ LCD CLock Select
+ $40 constant LCDCRB_LCD2B \ LCD 1/2 Bias Select
+ $30 constant LCDCRB_LCDMUX \ LCD Mux Selects
+ $0F constant LCDCRB_LCDPM \ LCD Port Masks
+&228 constant LCDCRA \ LCD Control Register A
+ $80 constant LCDCRA_LCDEN \ LCD Enable
+ $40 constant LCDCRA_LCDAB \ LCD A or B waveform
+ $10 constant LCDCRA_LCDIF \ LCD Interrupt Flag
+ $08 constant LCDCRA_LCDIE \ LCD Interrupt Enable
+ $01 constant LCDCRA_LCDBL \ LCD Blanking
+\ EXTERNAL_INTERRUPT
+&105 constant EICRA \ External Interrupt Control Register A
+ $02 constant EICRA_ISC01 \ External Interrupt Sense Control 0 Bit 1
+ $01 constant EICRA_ISC00 \ External Interrupt Sense Control 0 Bit 0
+&61 constant EIMSK \ External Interrupt Mask Register
+ $F0 constant EIMSK_PCIE \ Pin Change Interrupt Enables
+ $01 constant EIMSK_INT0 \ External Interrupt Request 0 Enable
+&60 constant EIFR \ External Interrupt Flag Register
+ $F0 constant EIFR_PCIF \ Pin Change Interrupt Flags
+ $01 constant EIFR_INTF0 \ External Interrupt Flag 0
+&108 constant PCMSK1 \ Pin Change Mask Register 1
+&107 constant PCMSK0 \ Pin Change Mask Register 0
+\ EEPROM
+&65 constant EEAR \ EEPROM Read/Write Access Bytes
+&64 constant EEDR \ EEPROM Data Register
+&63 constant EECR \ EEPROM Control Register
+ $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
+ $04 constant EECR_EEMWE \ EEPROM Master Write Enable
+ $02 constant EECR_EEWE \ EEPROM Write Enable
+ $01 constant EECR_EERE \ EEPROM Read Enable
+\ PORTA
+&34 constant PORTA \ Port A Data Register
+&33 constant DDRA \ Port A Data Direction Register
+&32 constant PINA \ Port A Input Pins
+\ PORTB
+&37 constant PORTB \ Port B Data Register
+&36 constant DDRB \ Port B Data Direction Register
+&35 constant PINB \ Port B Input Pins
+\ PORTC
+&40 constant PORTC \ Port C Data Register
+&39 constant DDRC \ Port C Data Direction Register
+&38 constant PINC \ Port C Input Pins
+\ PORTD
+&43 constant PORTD \ Port D Data Register
+&42 constant DDRD \ Port D Data Direction Register
+&41 constant PIND \ Port D Input Pins
+\ PORTE
+&46 constant PORTE \ Data Register, Port E
+&45 constant DDRE \ Data Direction Register, Port E
+&44 constant PINE \ Input Pins, Port E
+\ PORTF
+&49 constant PORTF \ Data Register, Port F
+&48 constant DDRF \ Data Direction Register, Port F
+&47 constant PINF \ Input Pins, Port F
+\ PORTG
+&52 constant PORTG \ Port G Data Register
+&51 constant DDRG \ Port G Data Direction Register
+&50 constant PING \ Port G Input Pins
+\ TIMER_COUNTER_0
+&68 constant TCCR0A \ Timer/Counter0 Control Register
+ $80 constant TCCR0A_FOC0A \ Force Output Compare
+ $40 constant TCCR0A_WGM00 \ Waveform Generation Mode 0
+ $30 constant TCCR0A_COM0A \ Compare Match Output Modes
+ $08 constant TCCR0A_WGM01 \ Waveform Generation Mode 1
+ $07 constant TCCR0A_CS0 \ Clock Selects
+&70 constant TCNT0 \ Timer/Counter0
+&71 constant OCR0A \ Timer/Counter0 Output Compare Register
+&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
+ $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match Interrupt Enable
+ $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
+&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
+ $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0
+ $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
+&67 constant GTCCR \ General Timer/Control Register
+ $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
+ $01 constant GTCCR_PSR310 \ Prescaler Reset Timer/Counter1 and Timer/Counter0
+\ TIMER_COUNTER_1
+&128 constant TCCR1A \ Timer/Counter1 Control Register A
+ $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
+ $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
+ $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
+&129 constant TCCR1B \ Timer/Counter1 Control Register B
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
+ $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
+&130 constant TCCR1C \ Timer/Counter 1 Control Register C
+ $80 constant TCCR1C_FOC1A \ Force Output Compare 1A
+ $40 constant TCCR1C_FOC1B \ Force Output Compare 1B
+&132 constant TCNT1 \ Timer/Counter1 Bytes
+&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
+&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
+&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
+&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
+ $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
+ $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
+ $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
+ $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
+&54 constant TIFR1 \ Timer/Counter1 Interrupt Flag register
+ $20 constant TIFR1_ICF1 \ Input Capture Flag 1
+ $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
+ $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
+ $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
+\ TIMER_COUNTER_2
+&176 constant TCCR2A \ Timer/Counter2 Control Register
+ $80 constant TCCR2A_FOC2A \ Force Output Compare A
+ $40 constant TCCR2A_WGM20 \ Waveform Generation Mode
+ $30 constant TCCR2A_COM2A \ Compare Output Mode bits
+ $08 constant TCCR2A_WGM21 \ Waveform Generation Mode
+ $07 constant TCCR2A_CS2 \ Clock Select bits
+&178 constant TCNT2 \ Timer/Counter2
+&179 constant OCR2A \ Timer/Counter2 Output Compare Register
+&112 constant TIMSK2 \ Timer/Counter2 Interrupt Mask register
+ $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match Interrupt Enable
+ $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
+&55 constant TIFR2 \ Timer/Counter2 Interrupt Flag Register
+ $02 constant TIFR2_OCF2A \ Timer/Counter2 Output Compare Flag 2
+ $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
+&182 constant ASSR \ Asynchronous Status Register
+ $10 constant ASSR_EXCLK \ Enable External Clock Interrupt
+ $08 constant ASSR_AS2 \ AS2: Asynchronous Timer/Counter2
+ $04 constant ASSR_TCN2UB \ TCN2UB: Timer/Counter2 Update Busy
+ $02 constant ASSR_OCR2UB \ Output Compare Register2 Update Busy
+ $01 constant ASSR_TCR2UB \ TCR2UB: Timer/Counter Control Register2 Update Busy
+\ WATCHDOG
+&96 constant WDTCR \ Watchdog Timer Control Register
+ $10 constant WDTCR_WDCE \ Watchdog Change Enable
+ $08 constant WDTCR_WDE \ Watch Dog Enable
+ $07 constant WDTCR_WDP \ Watch Dog Timer Prescaler bits
+\ BOOT_LOAD
+&87 constant SPMCSR \ Store Program Memory Control Register
+ $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
+ $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
+ $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
+ $04 constant SPMCSR_PGWRT \ Page Write
+ $02 constant SPMCSR_PGERS \ Page Erase
+ $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
+
+\ Interrupts
+&2 constant INT0Addr \ External Interrupt Request 0
+&4 constant PCINT0Addr \ Pin Change Interrupt Request 0
+&6 constant PCINT1Addr \ Pin Change Interrupt Request 1
+&8 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
+&10 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
+&12 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+&14 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
+&16 constant TIMER1_COMPBAddr \ Timer/Counter Compare Match B
+&18 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+&20 constant TIMER0_COMPAddr \ Timer/Counter0 Compare Match
+&22 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
+&24 constant SPI__STCAddr \ SPI Serial Transfer Complete
+&26 constant USART0__RXAddr \ USART0, Rx Complete
+&28 constant USART0__UDREAddr \ USART0 Data register Empty
+&30 constant USART0__TXAddr \ USART0, Tx Complete
+&32 constant USI_STARTAddr \ USI Start Condition
+&34 constant USI_OVERFLOWAddr \ USI Overflow
+&36 constant ANALOG_COMPAddr \ Analog Comparator
+&38 constant ADCAddr \ ADC Conversion Complete
+&40 constant EE_READYAddr \ EEPROM Ready
+&42 constant SPM_READYAddr \ Store Program Memory Read
+&44 constant LCDAddr \ LCD Start of Frame
diff --git a/amforth-6.5/avr8/devices/atmega649/device.asm b/amforth-6.5/avr8/devices/atmega649/device.asm
new file mode 100644
index 0000000..0fb67ee
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega649/device.asm
@@ -0,0 +1,109 @@
+; Partname: ATmega649
+; generated automatically, do not edit
+
+.nolist
+ .include "m649def.inc"
+.list
+
+.equ ramstart = 256
+.equ CELLSIZE = 2
+.macro readflashcell
+ lsl zl
+ rol zh
+ lpm @0, Z+
+ lpm @1, Z+
+.endmacro
+.macro writeflashcell
+ lsl zl
+ rol zh
+.endmacro
+.set WANT_AD_CONVERTER = 0
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_SPI = 0
+.set WANT_USI = 0
+.set WANT_USART0 = 0
+.set WANT_CPU = 0
+.set WANT_JTAG = 0
+.set WANT_LCD = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_EEPROM = 0
+.set WANT_PORTA = 0
+.set WANT_PORTB = 0
+.set WANT_PORTC = 0
+.set WANT_PORTD = 0
+.set WANT_PORTE = 0
+.set WANT_PORTF = 0
+.set WANT_PORTG = 0
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_TIMER_COUNTER_2 = 0
+.set WANT_WATCHDOG = 0
+.set WANT_BOOT_LOAD = 0
+.equ intvecsize = 2 ; please verify; flash size: 65536 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.org 2
+ rcall isr ; External Interrupt Request 0
+.org 4
+ rcall isr ; Pin Change Interrupt Request 0
+.org 6
+ rcall isr ; Pin Change Interrupt Request 1
+.org 8
+ rcall isr ; Timer/Counter2 Compare Match
+.org 10
+ rcall isr ; Timer/Counter2 Overflow
+.org 12
+ rcall isr ; Timer/Counter1 Capture Event
+.org 14
+ rcall isr ; Timer/Counter1 Compare Match A
+.org 16
+ rcall isr ; Timer/Counter Compare Match B
+.org 18
+ rcall isr ; Timer/Counter1 Overflow
+.org 20
+ rcall isr ; Timer/Counter0 Compare Match
+.org 22
+ rcall isr ; Timer/Counter0 Overflow
+.org 24
+ rcall isr ; SPI Serial Transfer Complete
+.org 26
+ rcall isr ; USART0, Rx Complete
+.org 28
+ rcall isr ; USART0 Data register Empty
+.org 30
+ rcall isr ; USART0, Tx Complete
+.org 32
+ rcall isr ; USI Start Condition
+.org 34
+ rcall isr ; USI Overflow
+.org 36
+ rcall isr ; Analog Comparator
+.org 38
+ rcall isr ; ADC Conversion Complete
+.org 40
+ rcall isr ; EEPROM Ready
+.org 42
+ rcall isr ; Store Program Memory Read
+.org 44
+ rcall isr ; LCD Start of Frame
+.equ INTVECTORS = 23
+.nooverlap
+
+; compatability layer (maybe empty)
+.equ EEPE = EEWE
+.equ EEMPE = EEMWE
+
+; controller data area, environment query mcu-info
+mcu_info:
+mcu_ramsize:
+ .dw 4096
+mcu_eepromsize:
+ .dw 2048
+mcu_maxdp:
+ .dw 57344
+mcu_numints:
+ .dw 23
+mcu_name:
+ .dw 9
+ .db "ATmega649",0
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega649/device.inc b/amforth-6.5/avr8/devices/atmega649/device.inc
new file mode 100644
index 0000000..23e59f3
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega649/device.inc
@@ -0,0 +1,1293 @@
+; Partname: ATmega649
+; generated automatically, no not edit
+
+.if WANT_AD_CONVERTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC multiplexer Selection Register
+VE_ADMUX:
+ .dw $ff05
+ .db "ADMUX",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADMUX
+XT_ADMUX:
+ .dw PFA_DOVARIABLE
+PFA_ADMUX:
+ .dw 124
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register
+VE_ADCSRA:
+ .dw $ff06
+ .db "ADCSRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRA
+XT_ADCSRA:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRA:
+ .dw 122
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register Bytes
+VE_ADC:
+ .dw $ff03
+ .db "ADC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADC
+XT_ADC:
+ .dw PFA_DOVARIABLE
+PFA_ADC:
+ .dw 120
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Control and Status Register B
+VE_ADCSRB:
+ .dw $ff06
+ .db "ADCSRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRB
+XT_ADCSRB:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRB:
+ .dw 123
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 0
+VE_DIDR0:
+ .dw $ff05
+ .db "DIDR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR0
+XT_DIDR0:
+ .dw PFA_DOVARIABLE
+PFA_DIDR0:
+ .dw 126
+
+.endif
+.if WANT_ANALOG_COMPARATOR == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Control And Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw 80
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 1
+VE_DIDR1:
+ .dw $ff05
+ .db "DIDR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR1
+XT_DIDR1:
+ .dw PFA_DOVARIABLE
+PFA_DIDR1:
+ .dw 127
+
+.endif
+.if WANT_SPI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR:
+ .dw $ff04
+ .db "SPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR
+XT_SPCR:
+ .dw PFA_DOVARIABLE
+PFA_SPCR:
+ .dw 76
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR:
+ .dw $ff04
+ .db "SPSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR
+XT_SPSR:
+ .dw PFA_DOVARIABLE
+PFA_SPSR:
+ .dw 77
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR:
+ .dw $ff04
+ .db "SPDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR
+XT_SPDR:
+ .dw PFA_DOVARIABLE
+PFA_SPDR:
+ .dw 78
+
+.endif
+.if WANT_USI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USI Data Register
+VE_USIDR:
+ .dw $ff05
+ .db "USIDR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USIDR
+XT_USIDR:
+ .dw PFA_DOVARIABLE
+PFA_USIDR:
+ .dw 186
+; ( -- addr ) System Constant
+; R( -- )
+; USI Status Register
+VE_USISR:
+ .dw $ff05
+ .db "USISR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USISR
+XT_USISR:
+ .dw PFA_DOVARIABLE
+PFA_USISR:
+ .dw 185
+; ( -- addr ) System Constant
+; R( -- )
+; USI Control Register
+VE_USICR:
+ .dw $ff05
+ .db "USICR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USICR
+XT_USICR:
+ .dw PFA_DOVARIABLE
+PFA_USICR:
+ .dw 184
+
+.endif
+.if WANT_USART0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR0:
+ .dw $ff04
+ .db "UDR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR0
+XT_UDR0:
+ .dw PFA_DOVARIABLE
+PFA_UDR0:
+ .dw 198
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR0A:
+ .dw $ff06
+ .db "UCSR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0A
+XT_UCSR0A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0A:
+ .dw 192
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR0B:
+ .dw $ff06
+ .db "UCSR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0B
+XT_UCSR0B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0B:
+ .dw 193
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR0C:
+ .dw $ff06
+ .db "UCSR0C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0C
+XT_UCSR0C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0C:
+ .dw 194
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Bytes
+VE_UBRR0:
+ .dw $ff05
+ .db "UBRR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR0
+XT_UBRR0:
+ .dw PFA_DOVARIABLE
+PFA_UBRR0:
+ .dw 196
+
+.endif
+.if WANT_CPU == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw 95
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer
+VE_SP:
+ .dw $ff02
+ .db "SP"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SP
+XT_SP:
+ .dw PFA_DOVARIABLE
+PFA_SP:
+ .dw 93
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw 85
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Status Register
+VE_MCUSR:
+ .dw $ff05
+ .db "MCUSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUSR
+XT_MCUSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUSR:
+ .dw 84
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Calibration Value
+VE_OSCCAL:
+ .dw $ff06
+ .db "OSCCAL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSCCAL
+XT_OSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_OSCCAL:
+ .dw 102
+; ( -- addr ) System Constant
+; R( -- )
+; Clock Prescale Register
+VE_CLKPR:
+ .dw $ff05
+ .db "CLKPR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKPR
+XT_CLKPR:
+ .dw PFA_DOVARIABLE
+PFA_CLKPR:
+ .dw 97
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register
+VE_PRR:
+ .dw $ff03
+ .db "PRR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR
+XT_PRR:
+ .dw PFA_DOVARIABLE
+PFA_PRR:
+ .dw 100
+; ( -- addr ) System Constant
+; R( -- )
+; Sleep Mode Control Register
+VE_SMCR:
+ .dw $ff04
+ .db "SMCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SMCR
+XT_SMCR:
+ .dw PFA_DOVARIABLE
+PFA_SMCR:
+ .dw 83
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 2
+VE_GPIOR2:
+ .dw $ff06
+ .db "GPIOR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR2
+XT_GPIOR2:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR2:
+ .dw 75
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 1
+VE_GPIOR1:
+ .dw $ff06
+ .db "GPIOR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR1
+XT_GPIOR1:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR1:
+ .dw 74
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 0
+VE_GPIOR0:
+ .dw $ff06
+ .db "GPIOR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR0
+XT_GPIOR0:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR0:
+ .dw 62
+
+.endif
+.if WANT_JTAG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; On-Chip Debug Related Register in I/O Memory
+VE_OCDR:
+ .dw $ff04
+ .db "OCDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCDR
+XT_OCDR:
+ .dw PFA_DOVARIABLE
+PFA_OCDR:
+ .dw 81
+
+.endif
+.if WANT_LCD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 18
+VE_LCDDR18:
+ .dw $ff07
+ .db "LCDDR18",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR18
+XT_LCDDR18:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR18:
+ .dw 254
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 17
+VE_LCDDR17:
+ .dw $ff07
+ .db "LCDDR17",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR17
+XT_LCDDR17:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR17:
+ .dw 253
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 16
+VE_LCDDR16:
+ .dw $ff07
+ .db "LCDDR16",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR16
+XT_LCDDR16:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR16:
+ .dw 252
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 15
+VE_LCDDR15:
+ .dw $ff07
+ .db "LCDDR15",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR15
+XT_LCDDR15:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR15:
+ .dw 251
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 13
+VE_LCDDR13:
+ .dw $ff07
+ .db "LCDDR13",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR13
+XT_LCDDR13:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR13:
+ .dw 249
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 12
+VE_LCDDR12:
+ .dw $ff07
+ .db "LCDDR12",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR12
+XT_LCDDR12:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR12:
+ .dw 248
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 11
+VE_LCDDR11:
+ .dw $ff07
+ .db "LCDDR11",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR11
+XT_LCDDR11:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR11:
+ .dw 247
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 10
+VE_LCDDR10:
+ .dw $ff07
+ .db "LCDDR10",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR10
+XT_LCDDR10:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR10:
+ .dw 246
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 8
+VE_LCDDR8:
+ .dw $ff06
+ .db "LCDDR8"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR8
+XT_LCDDR8:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR8:
+ .dw 244
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 7
+VE_LCDDR7:
+ .dw $ff06
+ .db "LCDDR7"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR7
+XT_LCDDR7:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR7:
+ .dw 243
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 6
+VE_LCDDR6:
+ .dw $ff06
+ .db "LCDDR6"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR6
+XT_LCDDR6:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR6:
+ .dw 242
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 5
+VE_LCDDR5:
+ .dw $ff06
+ .db "LCDDR5"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR5
+XT_LCDDR5:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR5:
+ .dw 241
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 3
+VE_LCDDR3:
+ .dw $ff06
+ .db "LCDDR3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR3
+XT_LCDDR3:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR3:
+ .dw 239
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 2
+VE_LCDDR2:
+ .dw $ff06
+ .db "LCDDR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR2
+XT_LCDDR2:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR2:
+ .dw 238
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 1
+VE_LCDDR1:
+ .dw $ff06
+ .db "LCDDR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR1
+XT_LCDDR1:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR1:
+ .dw 237
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 0
+VE_LCDDR0:
+ .dw $ff06
+ .db "LCDDR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR0
+XT_LCDDR0:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR0:
+ .dw 236
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Contrast Control Register
+VE_LCDCCR:
+ .dw $ff06
+ .db "LCDCCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDCCR
+XT_LCDCCR:
+ .dw PFA_DOVARIABLE
+PFA_LCDCCR:
+ .dw 231
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Frame Rate Register
+VE_LCDFRR:
+ .dw $ff06
+ .db "LCDFRR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDFRR
+XT_LCDFRR:
+ .dw PFA_DOVARIABLE
+PFA_LCDFRR:
+ .dw 230
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Control and Status Register B
+VE_LCDCRB:
+ .dw $ff06
+ .db "LCDCRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDCRB
+XT_LCDCRB:
+ .dw PFA_DOVARIABLE
+PFA_LCDCRB:
+ .dw 229
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Control Register A
+VE_LCDCRA:
+ .dw $ff06
+ .db "LCDCRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDCRA
+XT_LCDCRA:
+ .dw PFA_DOVARIABLE
+PFA_LCDCRA:
+ .dw 228
+
+.endif
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register A
+VE_EICRA:
+ .dw $ff05
+ .db "EICRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRA
+XT_EICRA:
+ .dw PFA_DOVARIABLE
+PFA_EICRA:
+ .dw 105
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Mask Register
+VE_EIMSK:
+ .dw $ff05
+ .db "EIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIMSK
+XT_EIMSK:
+ .dw PFA_DOVARIABLE
+PFA_EIMSK:
+ .dw 61
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Flag Register
+VE_EIFR:
+ .dw $ff04
+ .db "EIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIFR
+XT_EIFR:
+ .dw PFA_DOVARIABLE
+PFA_EIFR:
+ .dw 60
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 1
+VE_PCMSK1:
+ .dw $ff06
+ .db "PCMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK1
+XT_PCMSK1:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK1:
+ .dw 108
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 0
+VE_PCMSK0:
+ .dw $ff06
+ .db "PCMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK0
+XT_PCMSK0:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK0:
+ .dw 107
+
+.endif
+.if WANT_EEPROM == 1
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Read/Write Access Bytes
+VE_EEAR:
+ .dw $ff04
+ .db "EEAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEAR
+XT_EEAR:
+ .dw PFA_DOVARIABLE
+PFA_EEAR:
+ .dw 65
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw 64
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw 63
+
+.endif
+.if WANT_PORTA == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Register
+VE_PORTA:
+ .dw $ff05
+ .db "PORTA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTA
+XT_PORTA:
+ .dw PFA_DOVARIABLE
+PFA_PORTA:
+ .dw 34
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Direction Register
+VE_DDRA:
+ .dw $ff04
+ .db "DDRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRA
+XT_DDRA:
+ .dw PFA_DOVARIABLE
+PFA_DDRA:
+ .dw 33
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Input Pins
+VE_PINA:
+ .dw $ff04
+ .db "PINA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINA
+XT_PINA:
+ .dw PFA_DOVARIABLE
+PFA_PINA:
+ .dw 32
+
+.endif
+.if WANT_PORTB == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw 37
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw 36
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw 35
+
+.endif
+.if WANT_PORTC == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Register
+VE_PORTC:
+ .dw $ff05
+ .db "PORTC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTC
+XT_PORTC:
+ .dw PFA_DOVARIABLE
+PFA_PORTC:
+ .dw 40
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Direction Register
+VE_DDRC:
+ .dw $ff04
+ .db "DDRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRC
+XT_DDRC:
+ .dw PFA_DOVARIABLE
+PFA_DDRC:
+ .dw 39
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Input Pins
+VE_PINC:
+ .dw $ff04
+ .db "PINC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINC
+XT_PINC:
+ .dw PFA_DOVARIABLE
+PFA_PINC:
+ .dw 38
+
+.endif
+.if WANT_PORTD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw 43
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw 42
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw 41
+
+.endif
+.if WANT_PORTE == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port E
+VE_PORTE:
+ .dw $ff05
+ .db "PORTE",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTE
+XT_PORTE:
+ .dw PFA_DOVARIABLE
+PFA_PORTE:
+ .dw 46
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port E
+VE_DDRE:
+ .dw $ff04
+ .db "DDRE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRE
+XT_DDRE:
+ .dw PFA_DOVARIABLE
+PFA_DDRE:
+ .dw 45
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port E
+VE_PINE:
+ .dw $ff04
+ .db "PINE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINE
+XT_PINE:
+ .dw PFA_DOVARIABLE
+PFA_PINE:
+ .dw 44
+
+.endif
+.if WANT_PORTF == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port F
+VE_PORTF:
+ .dw $ff05
+ .db "PORTF",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTF
+XT_PORTF:
+ .dw PFA_DOVARIABLE
+PFA_PORTF:
+ .dw 49
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port F
+VE_DDRF:
+ .dw $ff04
+ .db "DDRF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRF
+XT_DDRF:
+ .dw PFA_DOVARIABLE
+PFA_DDRF:
+ .dw 48
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port F
+VE_PINF:
+ .dw $ff04
+ .db "PINF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINF
+XT_PINF:
+ .dw PFA_DOVARIABLE
+PFA_PINF:
+ .dw 47
+
+.endif
+.if WANT_PORTG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Data Register
+VE_PORTG:
+ .dw $ff05
+ .db "PORTG",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTG
+XT_PORTG:
+ .dw PFA_DOVARIABLE
+PFA_PORTG:
+ .dw 52
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Data Direction Register
+VE_DDRG:
+ .dw $ff04
+ .db "DDRG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRG
+XT_DDRG:
+ .dw PFA_DOVARIABLE
+PFA_DDRG:
+ .dw 51
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Input Pins
+VE_PING:
+ .dw $ff04
+ .db "PING"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PING
+XT_PING:
+ .dw PFA_DOVARIABLE
+PFA_PING:
+ .dw 50
+
+.endif
+.if WANT_TIMER_COUNTER_0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Control Register
+VE_TCCR0A:
+ .dw $ff06
+ .db "TCCR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0A
+XT_TCCR0A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0A:
+ .dw 68
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw 70
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0A:
+ .dw $ff05
+ .db "OCR0A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0A
+XT_OCR0A:
+ .dw PFA_DOVARIABLE
+PFA_OCR0A:
+ .dw 71
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Mask Register
+VE_TIMSK0:
+ .dw $ff06
+ .db "TIMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK0
+XT_TIMSK0:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK0:
+ .dw 110
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Flag register
+VE_TIFR0:
+ .dw $ff05
+ .db "TIFR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR0
+XT_TIFR0:
+ .dw PFA_DOVARIABLE
+PFA_TIFR0:
+ .dw 53
+; ( -- addr ) System Constant
+; R( -- )
+; General Timer/Control Register
+VE_GTCCR:
+ .dw $ff05
+ .db "GTCCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GTCCR
+XT_GTCCR:
+ .dw PFA_DOVARIABLE
+PFA_GTCCR:
+ .dw 67
+
+.endif
+.if WANT_TIMER_COUNTER_1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw 128
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw 129
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter 1 Control Register C
+VE_TCCR1C:
+ .dw $ff06
+ .db "TCCR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1C
+XT_TCCR1C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1C:
+ .dw 130
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Bytes
+VE_TCNT1:
+ .dw $ff05
+ .db "TCNT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1
+XT_TCNT1:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1:
+ .dw 132
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register A Bytes
+VE_OCR1A:
+ .dw $ff05
+ .db "OCR1A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1A
+XT_OCR1A:
+ .dw PFA_DOVARIABLE
+PFA_OCR1A:
+ .dw 136
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register B Bytes
+VE_OCR1B:
+ .dw $ff05
+ .db "OCR1B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1B
+XT_OCR1B:
+ .dw PFA_DOVARIABLE
+PFA_OCR1B:
+ .dw 138
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Bytes
+VE_ICR1:
+ .dw $ff04
+ .db "ICR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1
+XT_ICR1:
+ .dw PFA_DOVARIABLE
+PFA_ICR1:
+ .dw 134
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Mask Register
+VE_TIMSK1:
+ .dw $ff06
+ .db "TIMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK1
+XT_TIMSK1:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK1:
+ .dw 111
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Flag register
+VE_TIFR1:
+ .dw $ff05
+ .db "TIFR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR1
+XT_TIFR1:
+ .dw PFA_DOVARIABLE
+PFA_TIFR1:
+ .dw 54
+
+.endif
+.if WANT_TIMER_COUNTER_2 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register
+VE_TCCR2A:
+ .dw $ff06
+ .db "TCCR2A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2A
+XT_TCCR2A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2A:
+ .dw 176
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2
+VE_TCNT2:
+ .dw $ff05
+ .db "TCNT2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT2
+XT_TCNT2:
+ .dw PFA_DOVARIABLE
+PFA_TCNT2:
+ .dw 178
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register
+VE_OCR2A:
+ .dw $ff05
+ .db "OCR2A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2A
+XT_OCR2A:
+ .dw PFA_DOVARIABLE
+PFA_OCR2A:
+ .dw 179
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Interrupt Mask register
+VE_TIMSK2:
+ .dw $ff06
+ .db "TIMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK2
+XT_TIMSK2:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK2:
+ .dw 112
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Interrupt Flag Register
+VE_TIFR2:
+ .dw $ff05
+ .db "TIFR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR2
+XT_TIFR2:
+ .dw PFA_DOVARIABLE
+PFA_TIFR2:
+ .dw 55
+; ( -- addr ) System Constant
+; R( -- )
+; Asynchronous Status Register
+VE_ASSR:
+ .dw $ff04
+ .db "ASSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ASSR
+XT_ASSR:
+ .dw PFA_DOVARIABLE
+PFA_ASSR:
+ .dw 182
+
+.endif
+.if WANT_WATCHDOG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCR:
+ .dw $ff05
+ .db "WDTCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCR
+XT_WDTCR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCR:
+ .dw 96
+
+.endif
+.if WANT_BOOT_LOAD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control Register
+VE_SPMCSR:
+ .dw $ff06
+ .db "SPMCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCSR
+XT_SPMCSR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCSR:
+ .dw 87
+
+.endif
diff --git a/amforth-6.5/avr8/devices/atmega649/device.py b/amforth-6.5/avr8/devices/atmega649/device.py
new file mode 100644
index 0000000..07a25b0
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega649/device.py
@@ -0,0 +1,352 @@
+# Generated Automatically
+
+# Partname ATmega649
+
+MCUREGS = {
+# Interrupt Vectors
+ 'INT0Addr' : '#2', # External Interrupt Request 0
+ 'PCINT0Addr' : '#4', # Pin Change Interrupt Request 0
+ 'PCINT1Addr' : '#6', # Pin Change Interrupt Request 1
+ 'TIMER2_COMPAddr' : '#8', # Timer/Counter2 Compare Match
+ 'TIMER2_OVFAddr' : '#10', # Timer/Counter2 Overflow
+ 'TIMER1_CAPTAddr' : '#12', # Timer/Counter1 Capture Event
+ 'TIMER1_COMPAAddr' : '#14', # Timer/Counter1 Compare Match A
+ 'TIMER1_COMPBAddr' : '#16', # Timer/Counter Compare Match B
+ 'TIMER1_OVFAddr' : '#18', # Timer/Counter1 Overflow
+ 'TIMER0_COMPAddr' : '#20', # Timer/Counter0 Compare Match
+ 'TIMER0_OVFAddr' : '#22', # Timer/Counter0 Overflow
+ 'SPI_STCAddr' : '#24', # SPI Serial Transfer Complete
+ 'USART0_RXAddr' : '#26', # USART0, Rx Complete
+ 'USART0_UDREAddr' : '#28', # USART0 Data register Empty
+ 'USART0_TXAddr' : '#30', # USART0, Tx Complete
+ 'USI_STARTAddr' : '#32', # USI Start Condition
+ 'USI_OVERFLOWAddr' : '#34', # USI Overflow
+ 'ANALOG_COMPAddr' : '#36', # Analog Comparator
+ 'ADCAddr' : '#38', # ADC Conversion Complete
+ 'EE_READYAddr' : '#40', # EEPROM Ready
+ 'SPM_READYAddr' : '#42', # Store Program Memory Read
+ 'LCDAddr' : '#44', # LCD Start of Frame
+
+# Module AD_CONVERTER
+ 'ADMUX' : '$7c', # The ADC multiplexer Selection
+ 'ADMUX_REFS': '$c0', # Reference Selection Bits
+ 'ADMUX_ADLAR': '$20', # Left Adjust Result
+ 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
+ 'ADCSRA' : '$7a', # The ADC Control and Status reg
+ 'ADCSRA_ADEN': '$80', # ADC Enable
+ 'ADCSRA_ADSC': '$40', # ADC Start Conversion
+ 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
+ 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
+ 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
+ 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
+ 'ADC' : '$78', # ADC Data Register Bytes
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Sources
+ 'DIDR0' : '$7e', # Digital Input Disable Register
+ 'DIDR0_ADC7D': '$80', # ADC7 Digital input Disable
+ 'DIDR0_ADC6D': '$40', # ADC6 Digital input Disable
+ 'DIDR0_ADC5D': '$20', # ADC5 Digital input Disable
+ 'DIDR0_ADC4D': '$10', # ADC4 Digital input Disable
+ 'DIDR0_ADC3D': '$8', # ADC3 Digital input Disable
+ 'DIDR0_ADC2D': '$4', # ADC2 Digital input Disable
+ 'DIDR0_ADC1D': '$2', # ADC1 Digital input Disable
+ 'DIDR0_ADC0D': '$1', # ADC0 Digital input Disable
+
+# Module ANALOG_COMPARATOR
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
+ 'ACSR' : '$50', # Analog Comparator Control And
+ 'ACSR_ACD': '$80', # Analog Comparator Disable
+ 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
+ 'ACSR_ACO': '$20', # Analog Compare Output
+ 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
+ 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
+ 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
+ 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
+ 'DIDR1' : '$7f', # Digital Input Disable Register
+ 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
+ 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
+
+# Module SPI
+ 'SPCR' : '$4c', # SPI Control Register
+ 'SPCR_SPIE': '$80', # SPI Interrupt Enable
+ 'SPCR_SPE': '$40', # SPI Enable
+ 'SPCR_DORD': '$20', # Data Order
+ 'SPCR_MSTR': '$10', # Master/Slave Select
+ 'SPCR_CPOL': '$8', # Clock polarity
+ 'SPCR_CPHA': '$4', # Clock Phase
+ 'SPCR_SPR': '$3', # SPI Clock Rate Selects
+ 'SPSR' : '$4d', # SPI Status Register
+ 'SPSR_SPIF': '$80', # SPI Interrupt Flag
+ 'SPSR_WCOL': '$40', # Write Collision Flag
+ 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
+ 'SPDR' : '$4e', # SPI Data Register
+
+# Module USI
+ 'USIDR' : '$ba', # USI Data Register
+ 'USISR' : '$b9', # USI Status Register
+ 'USISR_USISIF': '$80', # Start Condition Interrupt Flag
+ 'USISR_USIOIF': '$40', # Counter Overflow Interrupt Fla
+ 'USISR_USIPF': '$20', # Stop Condition Flag
+ 'USISR_USIDC': '$10', # Data Output Collision
+ 'USISR_USICNT': '$f', # USI Counter Value Bits
+ 'USICR' : '$b8', # USI Control Register
+ 'USICR_USISIE': '$80', # Start Condition Interrupt Enab
+ 'USICR_USIOIE': '$40', # Counter Overflow Interrupt Ena
+ 'USICR_USIWM': '$30', # USI Wire Mode Bits
+ 'USICR_USICS': '$c', # USI Clock Source Select Bits
+ 'USICR_USICLK': '$2', # Clock Strobe
+ 'USICR_USITC': '$1', # Toggle Clock Port Pin
+
+# Module USART0
+ 'UDR0' : '$c6', # USART I/O Data Register
+ 'UCSR0A' : '$c0', # USART Control and Status Regis
+ 'UCSR0A_RXC0': '$80', # USART Receive Complete
+ 'UCSR0A_TXC0': '$40', # USART Transmit Complete
+ 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
+ 'UCSR0A_FE0': '$10', # Framing Error
+ 'UCSR0A_DOR0': '$8', # Data OverRun
+ 'UCSR0A_UPE0': '$4', # USART Parity Error
+ 'UCSR0A_U2X0': '$2', # Double the USART Transmission
+ 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
+ 'UCSR0B' : '$c1', # USART Control and Status Regis
+ 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
+ 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
+ 'UCSR0B_UDRIE0': '$20', # USART Data Register Empty Inte
+ 'UCSR0B_RXEN0': '$10', # Receiver Enable
+ 'UCSR0B_TXEN0': '$8', # Transmitter Enable
+ 'UCSR0B_UCSZ02': '$4', # Character Size
+ 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
+ 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
+ 'UCSR0C' : '$c2', # USART Control and Status Regis
+ 'UCSR0C_UMSEL0': '$40', # USART Mode Select
+ 'UCSR0C_UPM0': '$30', # Parity Mode Bits
+ 'UCSR0C_USBS0': '$8', # Stop Bit Select
+ 'UCSR0C_UCSZ0': '$6', # Character Size
+ 'UCSR0C_UCPOL0': '$1', # Clock Polarity
+ 'UBRR0' : '$c4', # USART Baud Rate Register Byte
+
+# Module CPU
+ 'SREG' : '$5f', # Status Register
+ 'SREG_I': '$80', # Global Interrupt Enable
+ 'SREG_T': '$40', # Bit Copy Storage
+ 'SREG_H': '$20', # Half Carry Flag
+ 'SREG_S': '$10', # Sign Bit
+ 'SREG_V': '$8', # Two's Complement Overflow Flag
+ 'SREG_N': '$4', # Negative Flag
+ 'SREG_Z': '$2', # Zero Flag
+ 'SREG_C': '$1', # Carry Flag
+ 'SP' : '$5d', # Stack Pointer
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_PUD': '$10', # Pull-up disable
+ 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
+ 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+ 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
+ 'MCUSR_BORF': '$4', # Brown-out Reset Flag
+ 'MCUSR_EXTRF': '$2', # External Reset Flag
+ 'MCUSR_PORF': '$1', # Power-on reset flag
+ 'OSCCAL' : '$66', # Oscillator Calibration Value
+ 'CLKPR' : '$61', # Clock Prescale Register
+ 'CLKPR_CLKPCE': '$80', # Clock Prescaler Change Enable
+ 'CLKPR_CLKPS': '$f', # Clock Prescaler Select Bits
+ 'PRR' : '$64', # Power Reduction Register
+ 'PRR_PRLCD': '$10', # Power Reduction LCD
+ 'PRR_PRTIM1': '$8', # Power Reduction Timer/Counter1
+ 'PRR_PRSPI': '$4', # Power Reduction Serial Periphe
+ 'PRR_PRUSART0': '$2', # Power Reduction USART
+ 'PRR_PRADC': '$1', # Power Reduction ADC
+ 'SMCR' : '$53', # Sleep Mode Control Register
+ 'SMCR_SM': '$e', # Sleep Mode Select bits
+ 'SMCR_SE': '$1', # Sleep Enable
+ 'GPIOR2' : '$4b', # General Purpose IO Register 2
+ 'GPIOR1' : '$4a', # General Purpose IO Register 1
+ 'GPIOR0' : '$3e', # General Purpose IO Register 0
+
+# Module JTAG
+ 'OCDR' : '$51', # On-Chip Debug Related Register
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_JTD': '$80', # JTAG Interface Disable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+
+# Module LCD
+ 'LCDDR18' : '$fe', # LCD Data Register 18
+ 'LCDDR17' : '$fd', # LCD Data Register 17
+ 'LCDDR16' : '$fc', # LCD Data Register 16
+ 'LCDDR15' : '$fb', # LCD Data Register 15
+ 'LCDDR13' : '$f9', # LCD Data Register 13
+ 'LCDDR12' : '$f8', # LCD Data Register 12
+ 'LCDDR11' : '$f7', # LCD Data Register 11
+ 'LCDDR10' : '$f6', # LCD Data Register 10
+ 'LCDDR8' : '$f4', # LCD Data Register 8
+ 'LCDDR7' : '$f3', # LCD Data Register 7
+ 'LCDDR6' : '$f2', # LCD Data Register 6
+ 'LCDDR5' : '$f1', # LCD Data Register 5
+ 'LCDDR3' : '$ef', # LCD Data Register 3
+ 'LCDDR2' : '$ee', # LCD Data Register 2
+ 'LCDDR1' : '$ed', # LCD Data Register 1
+ 'LCDDR0' : '$ec', # LCD Data Register 0
+ 'LCDCCR' : '$e7', # LCD Contrast Control Register
+ 'LCDFRR' : '$e6', # LCD Frame Rate Register
+ 'LCDFRR_LCDPS': '$70', # LCD Prescaler Selects
+ 'LCDFRR_LCDCD': '$7', # LCD Clock Dividers
+ 'LCDCRB' : '$e5', # LCD Control and Status Registe
+ 'LCDCRB_LCDCS': '$80', # LCD CLock Select
+ 'LCDCRB_LCD2B': '$40', # LCD 1/2 Bias Select
+ 'LCDCRB_LCDMUX': '$30', # LCD Mux Selects
+ 'LCDCRB_LCDPM': '$f', # LCD Port Masks
+ 'LCDCRA' : '$e4', # LCD Control Register A
+ 'LCDCRA_LCDEN': '$80', # LCD Enable
+ 'LCDCRA_LCDAB': '$40', # LCD A or B waveform
+ 'LCDCRA_LCDIF': '$10', # LCD Interrupt Flag
+ 'LCDCRA_LCDIE': '$8', # LCD Interrupt Enable
+ 'LCDCRA_LCDBL': '$1', # LCD Blanking
+
+# Module EXTERNAL_INTERRUPT
+ 'EICRA' : '$69', # External Interrupt Control Reg
+ 'EICRA_ISC01': '$2', # External Interrupt Sense Contr
+ 'EICRA_ISC00': '$1', # External Interrupt Sense Contr
+ 'EIMSK' : '$3d', # External Interrupt Mask Regist
+ 'EIMSK_PCIE': '$f0', # Pin Change Interrupt Enables
+ 'EIMSK_INT0': '$1', # External Interrupt Request 0 E
+ 'EIFR' : '$3c', # External Interrupt Flag Regist
+ 'EIFR_PCIF': '$f0', # Pin Change Interrupt Flags
+ 'EIFR_INTF0': '$1', # External Interrupt Flag 0
+ 'PCMSK1' : '$6c', # Pin Change Mask Register 1
+ 'PCMSK0' : '$6b', # Pin Change Mask Register 0
+
+# Module EEPROM
+ 'EEAR' : '$41', # EEPROM Read/Write Access Byte
+ 'EEDR' : '$40', # EEPROM Data Register
+ 'EECR' : '$3f', # EEPROM Control Register
+ 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
+ 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
+ 'EECR_EEWE': '$2', # EEPROM Write Enable
+ 'EECR_EERE': '$1', # EEPROM Read Enable
+
+# Module PORTA
+ 'PORTA' : '$22', # Port A Data Register
+ 'DDRA' : '$21', # Port A Data Direction Register
+ 'PINA' : '$20', # Port A Input Pins
+
+# Module PORTB
+ 'PORTB' : '$25', # Port B Data Register
+ 'DDRB' : '$24', # Port B Data Direction Register
+ 'PINB' : '$23', # Port B Input Pins
+
+# Module PORTC
+ 'PORTC' : '$28', # Port C Data Register
+ 'DDRC' : '$27', # Port C Data Direction Register
+ 'PINC' : '$26', # Port C Input Pins
+
+# Module PORTD
+ 'PORTD' : '$2b', # Port D Data Register
+ 'DDRD' : '$2a', # Port D Data Direction Register
+ 'PIND' : '$29', # Port D Input Pins
+
+# Module PORTE
+ 'PORTE' : '$2e', # Data Register, Port E
+ 'DDRE' : '$2d', # Data Direction Register, Port
+ 'PINE' : '$2c', # Input Pins, Port E
+
+# Module PORTF
+ 'PORTF' : '$31', # Data Register, Port F
+ 'DDRF' : '$30', # Data Direction Register, Port
+ 'PINF' : '$2f', # Input Pins, Port F
+
+# Module PORTG
+ 'PORTG' : '$34', # Port G Data Register
+ 'DDRG' : '$33', # Port G Data Direction Register
+ 'PING' : '$32', # Port G Input Pins
+
+# Module TIMER_COUNTER_0
+ 'TCCR0A' : '$44', # Timer/Counter0 Control Registe
+ 'TCCR0A_FOC0A': '$80', # Force Output Compare
+ 'TCCR0A_WGM00': '$40', # Waveform Generation Mode 0
+ 'TCCR0A_COM0A': '$30', # Compare Match Output Modes
+ 'TCCR0A_WGM01': '$8', # Waveform Generation Mode 1
+ 'TCCR0A_CS0': '$7', # Clock Selects
+ 'TCNT0' : '$46', # Timer/Counter0
+ 'OCR0A' : '$47', # Timer/Counter0 Output Compare
+ 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
+ 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
+ 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
+ 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
+ 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
+ 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Control Register
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSR310': '$1', # Prescaler Reset Timer/Counter1
+
+# Module TIMER_COUNTER_1
+ 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
+ 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
+ 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
+ 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
+ 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
+ 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
+ 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
+ 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
+ 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
+ 'TCCR1C' : '$82', # Timer/Counter 1 Control Regist
+ 'TCCR1C_FOC1A': '$80', # Force Output Compare 1A
+ 'TCCR1C_FOC1B': '$40', # Force Output Compare 1B
+ 'TCNT1' : '$84', # Timer/Counter1 Bytes
+ 'OCR1A' : '$88', # Timer/Counter1 Output Compare
+ 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
+ 'ICR1' : '$86', # Timer/Counter1 Input Capture R
+ 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
+ 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
+ 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
+ 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
+ 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
+ 'TIFR1' : '$36', # Timer/Counter1 Interrupt Flag
+ 'TIFR1_ICF1': '$20', # Input Capture Flag 1
+ 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
+ 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
+ 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
+
+# Module TIMER_COUNTER_2
+ 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
+ 'TCCR2A_FOC2A': '$80', # Force Output Compare A
+ 'TCCR2A_WGM20': '$40', # Waveform Generation Mode
+ 'TCCR2A_COM2A': '$30', # Compare Output Mode bits
+ 'TCCR2A_WGM21': '$8', # Waveform Generation Mode
+ 'TCCR2A_CS2': '$7', # Clock Select bits
+ 'TCNT2' : '$b2', # Timer/Counter2
+ 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
+ 'TIMSK2' : '$70', # Timer/Counter2 Interrupt Mask
+ 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
+ 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
+ 'TIFR2' : '$37', # Timer/Counter2 Interrupt Flag
+ 'TIFR2_OCF2A': '$2', # Timer/Counter2 Output Compare
+ 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_PSR2': '$2', # Prescaler Reset Timer/Counter2
+ 'ASSR' : '$b6', # Asynchronous Status Register
+ 'ASSR_EXCLK': '$10', # Enable External Clock Interrup
+ 'ASSR_AS2': '$8', # AS2: Asynchronous Timer/Counte
+ 'ASSR_TCN2UB': '$4', # TCN2UB: Timer/Counter2 Update
+ 'ASSR_OCR2UB': '$2', # Output Compare Register2 Updat
+ 'ASSR_TCR2UB': '$1', # TCR2UB: Timer/Counter Control
+
+# Module WATCHDOG
+ 'WDTCR' : '$60', # Watchdog Timer Control Registe
+ 'WDTCR_WDCE': '$10', # Watchdog Change Enable
+ 'WDTCR_WDE': '$8', # Watch Dog Enable
+ 'WDTCR_WDP': '$7', # Watch Dog Timer Prescaler bits
+
+# Module BOOT_LOAD
+ 'SPMCSR' : '$57', # Store Program Memory Control R
+ 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
+ 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
+ 'SPMCSR_RWWSRE': '$10', # Read While Write section read
+ 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
+ 'SPMCSR_PGWRT': '$4', # Page Write
+ 'SPMCSR_PGERS': '$2', # Page Erase
+ 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
+
+ '__amforth_dummy':'0'
+}
diff --git a/amforth-6.5/avr8/devices/atmega649/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega649/words/no-jtag.asm
new file mode 100644
index 0000000..352a4bb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega649/words/no-jtag.asm
@@ -0,0 +1,14 @@
+; ( -- )
+; ( -- )
+; MCU
+; disable jtag at runtime
+VE_NOJTAG:
+ .dw $FF05
+ .db "-jtag",0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOJTAG
+XT_NOJTAG:
+ .dw PFA_NOJTAG
+PFA_NOJTAG:
+
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega649/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega649/words/no-wdt.asm
new file mode 100644
index 0000000..4a12261
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega649/words/no-wdt.asm
@@ -0,0 +1,22 @@
+; ( -- )
+; MCU
+; disable watch dog timer at runtime
+VE_NOWDT:
+ .dw $ff04
+ .db "-wdt"
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOWDT
+XT_NOWDT:
+ .dw PFA_NOWDT
+PFA_NOWDT:
+
+; Reset WDT
+ wdr
+; Write logical one to WDTOE and WDE
+ in_ temp1, WDTCR
+ ori temp1, (1<<WDTOE)|(1<<WDE)
+ out WDTCR, temp1
+; Turn off WDT
+ ldi temp1, (0<<WDE)
+ out_ WDTCR, temp1
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega649/words/sleep.asm b/amforth-6.5/avr8/devices/atmega649/words/sleep.asm
new file mode 100644
index 0000000..256249c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega649/words/sleep.asm
@@ -0,0 +1,19 @@
+; ( mode -- )
+; MCU
+; put the controller into the specified sleep mode
+VE_SLEEP:
+ .dw $ff05
+ .db "sleep", 0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_SLEEP
+XT_SLEEP:
+ .dw PFA_SLEEP
+PFA_SLEEP:
+ andi tosl, 7 ; leave only legal mode bits
+ lsl tosl ; move to correct location (bits 3-1)
+ ori tosl, 1 ; set the SE bit
+ out_ SMCR, tosl ; set the sleep config
+ sleep ; nighty-night
+ out_ SMCR, zerol ; 0 protects against accidental sleeps
+ loadtos ; pop argument from stack
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega6490/atmega6490.frt b/amforth-6.5/avr8/devices/atmega6490/atmega6490.frt
new file mode 100644
index 0000000..33e440a
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega6490/atmega6490.frt
@@ -0,0 +1,334 @@
+\ Partname: ATmega6490
+\ generated automatically
+
+\ AD_CONVERTER
+&124 constant ADMUX \ The ADC multiplexer Selection Register
+ $C0 constant ADMUX_REFS \ Reference Selection Bits
+ $20 constant ADMUX_ADLAR \ Left Adjust Result
+ $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
+&122 constant ADCSRA \ The ADC Control and Status register
+ $80 constant ADCSRA_ADEN \ ADC Enable
+ $40 constant ADCSRA_ADSC \ ADC Start Conversion
+ $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
+ $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
+ $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
+ $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
+&120 constant ADC \ ADC Data Register Bytes
+&123 constant ADCSRB \ ADC Control and Status Register B
+ $07 constant ADCSRB_ADTS \ ADC Auto Trigger Sources
+&126 constant DIDR0 \ Digital Input Disable Register 0
+ $80 constant DIDR0_ADC7D \ ADC7 Digital input Disable
+ $40 constant DIDR0_ADC6D \ ADC6 Digital input Disable
+ $20 constant DIDR0_ADC5D \ ADC5 Digital input Disable
+ $10 constant DIDR0_ADC4D \ ADC4 Digital input Disable
+ $08 constant DIDR0_ADC3D \ ADC3 Digital input Disable
+ $04 constant DIDR0_ADC2D \ ADC2 Digital input Disable
+ $02 constant DIDR0_ADC1D \ ADC1 Digital input Disable
+ $01 constant DIDR0_ADC0D \ ADC0 Digital input Disable
+\ ANALOG_COMPARATOR
+&80 constant ACSR \ Analog Comparator Control And Status Register
+ $80 constant ACSR_ACD \ Analog Comparator Disable
+ $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
+ $20 constant ACSR_ACO \ Analog Compare Output
+ $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
+ $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
+ $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
+ $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
+&127 constant DIDR1 \ Digital Input Disable Register 1
+ $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
+ $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
+\ SPI
+&76 constant SPCR \ SPI Control Register
+ $80 constant SPCR_SPIE \ SPI Interrupt Enable
+ $40 constant SPCR_SPE \ SPI Enable
+ $20 constant SPCR_DORD \ Data Order
+ $10 constant SPCR_MSTR \ Master/Slave Select
+ $08 constant SPCR_CPOL \ Clock polarity
+ $04 constant SPCR_CPHA \ Clock Phase
+ $03 constant SPCR_SPR \ SPI Clock Rate Selects
+&77 constant SPSR \ SPI Status Register
+ $80 constant SPSR_SPIF \ SPI Interrupt Flag
+ $40 constant SPSR_WCOL \ Write Collision Flag
+ $01 constant SPSR_SPI2X \ Double SPI Speed Bit
+&78 constant SPDR \ SPI Data Register
+\ USI
+&186 constant USIDR \ USI Data Register
+&185 constant USISR \ USI Status Register
+ $80 constant USISR_USISIF \ Start Condition Interrupt Flag
+ $40 constant USISR_USIOIF \ Counter Overflow Interrupt Flag
+ $20 constant USISR_USIPF \ Stop Condition Flag
+ $10 constant USISR_USIDC \ Data Output Collision
+ $0F constant USISR_USICNT \ USI Counter Value Bits
+&184 constant USICR \ USI Control Register
+ $80 constant USICR_USISIE \ Start Condition Interrupt Enable
+ $40 constant USICR_USIOIE \ Counter Overflow Interrupt Enable
+ $30 constant USICR_USIWM \ USI Wire Mode Bits
+ $0C constant USICR_USICS \ USI Clock Source Select Bits
+ $02 constant USICR_USICLK \ Clock Strobe
+ $01 constant USICR_USITC \ Toggle Clock Port Pin
+\ USART0
+&198 constant UDR0 \ USART I/O Data Register
+&192 constant UCSR0A \ USART Control and Status Register A
+ $80 constant UCSR0A_RXC0 \ USART Receive Complete
+ $40 constant UCSR0A_TXC0 \ USART Transmit Complete
+ $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
+ $10 constant UCSR0A_FE0 \ Framing Error
+ $08 constant UCSR0A_DOR0 \ Data OverRun
+ $04 constant UCSR0A_UPE0 \ USART Parity Error
+ $02 constant UCSR0A_U2X0 \ Double the USART Transmission Speed
+ $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
+&193 constant UCSR0B \ USART Control and Status Register B
+ $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
+ $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
+ $20 constant UCSR0B_UDRIE0 \ USART Data Register Empty Interrupt Enable
+ $10 constant UCSR0B_RXEN0 \ Receiver Enable
+ $08 constant UCSR0B_TXEN0 \ Transmitter Enable
+ $04 constant UCSR0B_UCSZ02 \ Character Size
+ $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
+ $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
+&194 constant UCSR0C \ USART Control and Status Register C
+ $40 constant UCSR0C_UMSEL0 \ USART Mode Select
+ $30 constant UCSR0C_UPM0 \ Parity Mode Bits
+ $08 constant UCSR0C_USBS0 \ Stop Bit Select
+ $06 constant UCSR0C_UCSZ0 \ Character Size
+ $01 constant UCSR0C_UCPOL0 \ Clock Polarity
+&196 constant UBRR0 \ USART Baud Rate Register Bytes
+\ CPU
+&95 constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ $08 constant SREG_V \ Two's Complement Overflow Flag
+ $04 constant SREG_N \ Negative Flag
+ $02 constant SREG_Z \ Zero Flag
+ $01 constant SREG_C \ Carry Flag
+&93 constant SP \ Stack Pointer
+&85 constant MCUCR \ MCU Control Register
+ $10 constant MCUCR_PUD \ Pull-up disable
+ $02 constant MCUCR_IVSEL \ Interrupt Vector Select
+ $01 constant MCUCR_IVCE \ Interrupt Vector Change Enable
+&84 constant MCUSR \ MCU Status Register
+ $10 constant MCUSR_JTRF \ JTAG Reset Flag
+ $08 constant MCUSR_WDRF \ Watchdog Reset Flag
+ $04 constant MCUSR_BORF \ Brown-out Reset Flag
+ $02 constant MCUSR_EXTRF \ External Reset Flag
+ $01 constant MCUSR_PORF \ Power-on reset flag
+&102 constant OSCCAL \ Oscillator Calibration Value
+&97 constant CLKPR \ Clock Prescale Register
+ $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable
+ $0F constant CLKPR_CLKPS \ Clock Prescaler Select Bits
+&100 constant PRR \ Power Reduction Register
+ $10 constant PRR_PRLCD \ Power Reduction LCD
+ $08 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
+ $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
+ $02 constant PRR_PRUSART0 \ Power Reduction USART
+ $01 constant PRR_PRADC \ Power Reduction ADC
+&83 constant SMCR \ Sleep Mode Control Register
+ $0E constant SMCR_SM \ Sleep Mode Select bits
+ $01 constant SMCR_SE \ Sleep Enable
+&75 constant GPIOR2 \ General Purpose IO Register 2
+&74 constant GPIOR1 \ General Purpose IO Register 1
+&62 constant GPIOR0 \ General Purpose IO Register 0
+\ JTAG
+&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
+\ EEPROM
+&65 constant EEAR \ EEPROM Read/Write Access Bytes
+&64 constant EEDR \ EEPROM Data Register
+&63 constant EECR \ EEPROM Control Register
+ $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
+ $04 constant EECR_EEMWE \ EEPROM Master Write Enable
+ $02 constant EECR_EEWE \ EEPROM Write Enable
+ $01 constant EECR_EERE \ EEPROM Read Enable
+\ PORTA
+&34 constant PORTA \ Port A Data Register
+&33 constant DDRA \ Port A Data Direction Register
+&32 constant PINA \ Port A Input Pins
+\ PORTB
+&37 constant PORTB \ Port B Data Register
+&36 constant DDRB \ Port B Data Direction Register
+&35 constant PINB \ Port B Input Pins
+\ PORTC
+&40 constant PORTC \ Port C Data Register
+&39 constant DDRC \ Port C Data Direction Register
+&38 constant PINC \ Port C Input Pins
+\ PORTD
+&43 constant PORTD \ Port D Data Register
+&42 constant DDRD \ Port D Data Direction Register
+&41 constant PIND \ Port D Input Pins
+\ PORTE
+&46 constant PORTE \ Data Register, Port E
+&45 constant DDRE \ Data Direction Register, Port E
+&44 constant PINE \ Input Pins, Port E
+\ PORTF
+&49 constant PORTF \ Data Register, Port F
+&48 constant DDRF \ Data Direction Register, Port F
+&47 constant PINF \ Input Pins, Port F
+\ PORTG
+&52 constant PORTG \ Port G Data Register
+&51 constant DDRG \ Port G Data Direction Register
+&50 constant PING \ Port G Input Pins
+\ TIMER_COUNTER_0
+&68 constant TCCR0A \ Timer/Counter0 Control Register
+ $80 constant TCCR0A_FOC0A \ Force Output Compare
+ $40 constant TCCR0A_WGM00 \ Waveform Generation Mode 0
+ $30 constant TCCR0A_COM0A \ Compare Match Output Modes
+ $08 constant TCCR0A_WGM01 \ Waveform Generation Mode 1
+ $07 constant TCCR0A_CS0 \ Clock Selects
+&70 constant TCNT0 \ Timer/Counter0
+&71 constant OCR0A \ Timer/Counter0 Output Compare Register
+&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
+ $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match Interrupt Enable
+ $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
+&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
+ $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0
+ $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
+&67 constant GTCCR \ General Timer/Control Register
+ $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
+ $01 constant GTCCR_PSR310 \ Prescaler Reset Timer/Counter1 and Timer/Counter0
+\ TIMER_COUNTER_1
+&128 constant TCCR1A \ Timer/Counter1 Control Register A
+ $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
+ $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
+ $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
+&129 constant TCCR1B \ Timer/Counter1 Control Register B
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
+ $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
+&130 constant TCCR1C \ Timer/Counter 1 Control Register C
+ $80 constant TCCR1C_FOC1A \ Force Output Compare 1A
+ $40 constant TCCR1C_FOC1B \ Force Output Compare 1B
+&132 constant TCNT1 \ Timer/Counter1 Bytes
+&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
+&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
+&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
+&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
+ $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
+ $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
+ $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
+ $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
+&54 constant TIFR1 \ Timer/Counter1 Interrupt Flag register
+ $20 constant TIFR1_ICF1 \ Input Capture Flag 1
+ $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
+ $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
+ $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
+\ TIMER_COUNTER_2
+&176 constant TCCR2A \ Timer/Counter2 Control Register
+ $80 constant TCCR2A_FOC2A \ Force Output Compare A
+ $40 constant TCCR2A_WGM20 \ Waveform Generation Mode
+ $30 constant TCCR2A_COM2A \ Compare Output Mode bits
+ $08 constant TCCR2A_WGM21 \ Waveform Generation Mode
+ $07 constant TCCR2A_CS2 \ Clock Select bits
+&178 constant TCNT2 \ Timer/Counter2
+&179 constant OCR2A \ Timer/Counter2 Output Compare Register
+&112 constant TIMSK2 \ Timer/Counter2 Interrupt Mask register
+ $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match Interrupt Enable
+ $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
+&55 constant TIFR2 \ Timer/Counter2 Interrupt Flag Register
+ $02 constant TIFR2_OCF2A \ Timer/Counter2 Output Compare Flag 2
+ $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
+&182 constant ASSR \ Asynchronous Status Register
+ $10 constant ASSR_EXCLK \ Enable External Clock Interrupt
+ $08 constant ASSR_AS2 \ AS2: Asynchronous Timer/Counter2
+ $04 constant ASSR_TCN2UB \ TCN2UB: Timer/Counter2 Update Busy
+ $02 constant ASSR_OCR2UB \ Output Compare Register2 Update Busy
+ $01 constant ASSR_TCR2UB \ TCR2UB: Timer/Counter Control Register2 Update Busy
+\ WATCHDOG
+&96 constant WDTCR \ Watchdog Timer Control Register
+ $10 constant WDTCR_WDCE \ Watchdog Change Enable
+ $08 constant WDTCR_WDE \ Watch Dog Enable
+ $07 constant WDTCR_WDP \ Watch Dog Timer Prescaler bits
+\ BOOT_LOAD
+&87 constant SPMCSR \ Store Program Memory Control Register
+ $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
+ $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
+ $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
+ $04 constant SPMCSR_PGWRT \ Page Write
+ $02 constant SPMCSR_PGERS \ Page Erase
+ $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
+\ PORTH
+&218 constant PORTH \ PORT H Data Register
+&217 constant DDRH \ PORT H Data Direction Register
+&216 constant PINH \ PORT H Input Pins
+\ PORTJ
+&221 constant PORTJ \ PORT J Data Register
+&220 constant DDRJ \ PORT J Data Direction Register
+&219 constant PINJ \ PORT J Input Pins
+\ LCD
+&255 constant LCDDR19 \ LCD Data Register 19
+&254 constant LCDDR18 \ LCD Data Register 18
+&253 constant LCDDR17 \ LCD Data Register 17
+&252 constant LCDDR16 \ LCD Data Register 16
+&251 constant LCDDR15 \ LCD Data Register 15
+&250 constant LCDDR14 \ LCD Data Register 14
+&249 constant LCDDR13 \ LCD Data Register 13
+&248 constant LCDDR12 \ LCD Data Register 12
+&247 constant LCDDR11 \ LCD Data Register 11
+&246 constant LCDDR10 \ LCD Data Register 10
+&245 constant LCDDR9 \ LCD Data Register 9
+&244 constant LCDDR8 \ LCD Data Register 8
+&243 constant LCDDR7 \ LCD Data Register 7
+&242 constant LCDDR6 \ LCD Data Register 6
+&241 constant LCDDR5 \ LCD Data Register 5
+&240 constant LCDDR4 \ LCD Data Register 4
+&239 constant LCDDR3 \ LCD Data Register 3
+&238 constant LCDDR2 \ LCD Data Register 2
+&237 constant LCDDR1 \ LCD Data Register 1
+&236 constant LCDDR0 \ LCD Data Register 0
+&231 constant LCDCCR \ LCD Contrast Control Register
+&230 constant LCDFRR \ LCD Frame Rate Register
+ $70 constant LCDFRR_LCDPS \ LCD Prescaler Selects
+ $07 constant LCDFRR_LCDCD \ LCD Clock Dividers
+&229 constant LCDCRB \ LCD Control and Status Register B
+ $80 constant LCDCRB_LCDCS \ LCD CLock Select
+ $40 constant LCDCRB_LCD2B \ LCD 1/2 Bias Select
+ $30 constant LCDCRB_LCDMUX \ LCD Mux Selects
+ $0F constant LCDCRB_LCDPM \ LCD Port Masks
+&228 constant LCDCRA \ LCD Control and Status Register A
+ $80 constant LCDCRA_LCDEN \ LCD Enable
+ $40 constant LCDCRA_LCDAB \ LCD A or B waveform
+ $10 constant LCDCRA_LCDIF \ LCD Interrupt Flag
+ $08 constant LCDCRA_LCDIE \ LCD Interrupt Enable
+ $01 constant LCDCRA_LCDBL \ LCD Blanking
+\ EXTERNAL_INTERRUPT
+&105 constant EICRA \ External Interrupt Control Register A
+ $02 constant EICRA_ISC01 \ External Interrupt Sense Control 0 Bit 1
+ $01 constant EICRA_ISC00 \ External Interrupt Sense Control 0 Bit 0
+&61 constant EIMSK \ External Interrupt Mask Register
+ $F0 constant EIMSK_PCIE \ Pin Change Interrupt Enables
+ $01 constant EIMSK_INT0 \ External Interrupt Request 0 Enable
+&60 constant EIFR \ External Interrupt Flag Register
+ $F0 constant EIFR_PCIF \ Pin Change Interrupt Flags
+ $01 constant EIFR_INTF0 \ External Interrupt Flag 0
+&115 constant PCMSK3 \ Pin Change Mask Register 3
+&109 constant PCMSK2 \ Pin Change Mask Register 2
+&108 constant PCMSK1 \ Pin Change Mask Register 1
+&107 constant PCMSK0 \ Pin Change Mask Register 0
+
+\ Interrupts
+&2 constant INT0Addr \ External Interrupt Request 0
+&4 constant PCINT0Addr \ Pin Change Interrupt Request 0
+&6 constant PCINT1Addr \ Pin Change Interrupt Request 1
+&8 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
+&10 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
+&12 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+&14 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
+&16 constant TIMER1_COMPBAddr \ Timer/Counter Compare Match B
+&18 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+&20 constant TIMER0_COMPAddr \ Timer/Counter0 Compare Match
+&22 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
+&24 constant SPI__STCAddr \ SPI Serial Transfer Complete
+&26 constant USART__RXAddr \ USART, Rx Complete
+&28 constant USART__UDREAddr \ USART Data register Empty
+&30 constant USART0__TXAddr \ USART0, Tx Complete
+&32 constant USI_STARTAddr \ USI Start Condition
+&34 constant USI_OVERFLOWAddr \ USI Overflow
+&36 constant ANALOG_COMPAddr \ Analog Comparator
+&38 constant ADCAddr \ ADC Conversion Complete
+&40 constant EE_READYAddr \ EEPROM Ready
+&42 constant SPM_READYAddr \ Store Program Memory Read
+&44 constant LCDAddr \ LCD Start of Frame
+&46 constant PCINT2Addr \ Pin Change Interrupt Request 2
+&48 constant PCINT3Addr \ Pin Change Interrupt Request 3
diff --git a/amforth-6.5/avr8/devices/atmega6490/device.asm b/amforth-6.5/avr8/devices/atmega6490/device.asm
new file mode 100644
index 0000000..02a743f
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega6490/device.asm
@@ -0,0 +1,115 @@
+; Partname: ATmega6490
+; generated automatically, do not edit
+
+.nolist
+ .include "m6490def.inc"
+.list
+
+.equ ramstart = 256
+.equ CELLSIZE = 2
+.macro readflashcell
+ lsl zl
+ rol zh
+ lpm @0, Z+
+ lpm @1, Z+
+.endmacro
+.macro writeflashcell
+ lsl zl
+ rol zh
+.endmacro
+.set WANT_AD_CONVERTER = 0
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_SPI = 0
+.set WANT_USI = 0
+.set WANT_USART0 = 0
+.set WANT_CPU = 0
+.set WANT_JTAG = 0
+.set WANT_EEPROM = 0
+.set WANT_PORTA = 0
+.set WANT_PORTB = 0
+.set WANT_PORTC = 0
+.set WANT_PORTD = 0
+.set WANT_PORTE = 0
+.set WANT_PORTF = 0
+.set WANT_PORTG = 0
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_TIMER_COUNTER_2 = 0
+.set WANT_WATCHDOG = 0
+.set WANT_BOOT_LOAD = 0
+.set WANT_PORTH = 0
+.set WANT_PORTJ = 0
+.set WANT_LCD = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.equ intvecsize = 2 ; please verify; flash size: 65536 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.org 2
+ rcall isr ; External Interrupt Request 0
+.org 4
+ rcall isr ; Pin Change Interrupt Request 0
+.org 6
+ rcall isr ; Pin Change Interrupt Request 1
+.org 8
+ rcall isr ; Timer/Counter2 Compare Match
+.org 10
+ rcall isr ; Timer/Counter2 Overflow
+.org 12
+ rcall isr ; Timer/Counter1 Capture Event
+.org 14
+ rcall isr ; Timer/Counter1 Compare Match A
+.org 16
+ rcall isr ; Timer/Counter Compare Match B
+.org 18
+ rcall isr ; Timer/Counter1 Overflow
+.org 20
+ rcall isr ; Timer/Counter0 Compare Match
+.org 22
+ rcall isr ; Timer/Counter0 Overflow
+.org 24
+ rcall isr ; SPI Serial Transfer Complete
+.org 26
+ rcall isr ; USART, Rx Complete
+.org 28
+ rcall isr ; USART Data register Empty
+.org 30
+ rcall isr ; USART0, Tx Complete
+.org 32
+ rcall isr ; USI Start Condition
+.org 34
+ rcall isr ; USI Overflow
+.org 36
+ rcall isr ; Analog Comparator
+.org 38
+ rcall isr ; ADC Conversion Complete
+.org 40
+ rcall isr ; EEPROM Ready
+.org 42
+ rcall isr ; Store Program Memory Read
+.org 44
+ rcall isr ; LCD Start of Frame
+.org 46
+ rcall isr ; Pin Change Interrupt Request 2
+.org 48
+ rcall isr ; Pin Change Interrupt Request 3
+.equ INTVECTORS = 25
+.nooverlap
+
+; compatability layer (maybe empty)
+.equ EEPE = EEWE
+.equ EEMPE = EEMWE
+
+; controller data area, environment query mcu-info
+mcu_info:
+mcu_ramsize:
+ .dw 4096
+mcu_eepromsize:
+ .dw 2048
+mcu_maxdp:
+ .dw 57344
+mcu_numints:
+ .dw 25
+mcu_name:
+ .dw 10
+ .db "ATmega6490"
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega6490/device.inc b/amforth-6.5/avr8/devices/atmega6490/device.inc
new file mode 100644
index 0000000..896b218
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega6490/device.inc
@@ -0,0 +1,1443 @@
+; Partname: ATmega6490
+; generated automatically, no not edit
+
+.if WANT_AD_CONVERTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC multiplexer Selection Register
+VE_ADMUX:
+ .dw $ff05
+ .db "ADMUX",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADMUX
+XT_ADMUX:
+ .dw PFA_DOVARIABLE
+PFA_ADMUX:
+ .dw 124
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register
+VE_ADCSRA:
+ .dw $ff06
+ .db "ADCSRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRA
+XT_ADCSRA:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRA:
+ .dw 122
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register Bytes
+VE_ADC:
+ .dw $ff03
+ .db "ADC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADC
+XT_ADC:
+ .dw PFA_DOVARIABLE
+PFA_ADC:
+ .dw 120
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Control and Status Register B
+VE_ADCSRB:
+ .dw $ff06
+ .db "ADCSRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRB
+XT_ADCSRB:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRB:
+ .dw 123
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 0
+VE_DIDR0:
+ .dw $ff05
+ .db "DIDR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR0
+XT_DIDR0:
+ .dw PFA_DOVARIABLE
+PFA_DIDR0:
+ .dw 126
+
+.endif
+.if WANT_ANALOG_COMPARATOR == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Control And Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw 80
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 1
+VE_DIDR1:
+ .dw $ff05
+ .db "DIDR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR1
+XT_DIDR1:
+ .dw PFA_DOVARIABLE
+PFA_DIDR1:
+ .dw 127
+
+.endif
+.if WANT_SPI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR:
+ .dw $ff04
+ .db "SPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR
+XT_SPCR:
+ .dw PFA_DOVARIABLE
+PFA_SPCR:
+ .dw 76
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR:
+ .dw $ff04
+ .db "SPSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR
+XT_SPSR:
+ .dw PFA_DOVARIABLE
+PFA_SPSR:
+ .dw 77
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR:
+ .dw $ff04
+ .db "SPDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR
+XT_SPDR:
+ .dw PFA_DOVARIABLE
+PFA_SPDR:
+ .dw 78
+
+.endif
+.if WANT_USI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USI Data Register
+VE_USIDR:
+ .dw $ff05
+ .db "USIDR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USIDR
+XT_USIDR:
+ .dw PFA_DOVARIABLE
+PFA_USIDR:
+ .dw 186
+; ( -- addr ) System Constant
+; R( -- )
+; USI Status Register
+VE_USISR:
+ .dw $ff05
+ .db "USISR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USISR
+XT_USISR:
+ .dw PFA_DOVARIABLE
+PFA_USISR:
+ .dw 185
+; ( -- addr ) System Constant
+; R( -- )
+; USI Control Register
+VE_USICR:
+ .dw $ff05
+ .db "USICR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USICR
+XT_USICR:
+ .dw PFA_DOVARIABLE
+PFA_USICR:
+ .dw 184
+
+.endif
+.if WANT_USART0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR0:
+ .dw $ff04
+ .db "UDR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR0
+XT_UDR0:
+ .dw PFA_DOVARIABLE
+PFA_UDR0:
+ .dw 198
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR0A:
+ .dw $ff06
+ .db "UCSR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0A
+XT_UCSR0A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0A:
+ .dw 192
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR0B:
+ .dw $ff06
+ .db "UCSR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0B
+XT_UCSR0B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0B:
+ .dw 193
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR0C:
+ .dw $ff06
+ .db "UCSR0C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0C
+XT_UCSR0C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0C:
+ .dw 194
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Bytes
+VE_UBRR0:
+ .dw $ff05
+ .db "UBRR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR0
+XT_UBRR0:
+ .dw PFA_DOVARIABLE
+PFA_UBRR0:
+ .dw 196
+
+.endif
+.if WANT_CPU == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw 95
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer
+VE_SP:
+ .dw $ff02
+ .db "SP"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SP
+XT_SP:
+ .dw PFA_DOVARIABLE
+PFA_SP:
+ .dw 93
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw 85
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Status Register
+VE_MCUSR:
+ .dw $ff05
+ .db "MCUSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUSR
+XT_MCUSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUSR:
+ .dw 84
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Calibration Value
+VE_OSCCAL:
+ .dw $ff06
+ .db "OSCCAL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSCCAL
+XT_OSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_OSCCAL:
+ .dw 102
+; ( -- addr ) System Constant
+; R( -- )
+; Clock Prescale Register
+VE_CLKPR:
+ .dw $ff05
+ .db "CLKPR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKPR
+XT_CLKPR:
+ .dw PFA_DOVARIABLE
+PFA_CLKPR:
+ .dw 97
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register
+VE_PRR:
+ .dw $ff03
+ .db "PRR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR
+XT_PRR:
+ .dw PFA_DOVARIABLE
+PFA_PRR:
+ .dw 100
+; ( -- addr ) System Constant
+; R( -- )
+; Sleep Mode Control Register
+VE_SMCR:
+ .dw $ff04
+ .db "SMCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SMCR
+XT_SMCR:
+ .dw PFA_DOVARIABLE
+PFA_SMCR:
+ .dw 83
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 2
+VE_GPIOR2:
+ .dw $ff06
+ .db "GPIOR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR2
+XT_GPIOR2:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR2:
+ .dw 75
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 1
+VE_GPIOR1:
+ .dw $ff06
+ .db "GPIOR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR1
+XT_GPIOR1:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR1:
+ .dw 74
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 0
+VE_GPIOR0:
+ .dw $ff06
+ .db "GPIOR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR0
+XT_GPIOR0:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR0:
+ .dw 62
+
+.endif
+.if WANT_JTAG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; On-Chip Debug Related Register in I/O Memory
+VE_OCDR:
+ .dw $ff04
+ .db "OCDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCDR
+XT_OCDR:
+ .dw PFA_DOVARIABLE
+PFA_OCDR:
+ .dw 81
+
+.endif
+.if WANT_EEPROM == 1
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Read/Write Access Bytes
+VE_EEAR:
+ .dw $ff04
+ .db "EEAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEAR
+XT_EEAR:
+ .dw PFA_DOVARIABLE
+PFA_EEAR:
+ .dw 65
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw 64
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw 63
+
+.endif
+.if WANT_PORTA == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Register
+VE_PORTA:
+ .dw $ff05
+ .db "PORTA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTA
+XT_PORTA:
+ .dw PFA_DOVARIABLE
+PFA_PORTA:
+ .dw 34
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Direction Register
+VE_DDRA:
+ .dw $ff04
+ .db "DDRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRA
+XT_DDRA:
+ .dw PFA_DOVARIABLE
+PFA_DDRA:
+ .dw 33
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Input Pins
+VE_PINA:
+ .dw $ff04
+ .db "PINA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINA
+XT_PINA:
+ .dw PFA_DOVARIABLE
+PFA_PINA:
+ .dw 32
+
+.endif
+.if WANT_PORTB == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw 37
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw 36
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw 35
+
+.endif
+.if WANT_PORTC == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Register
+VE_PORTC:
+ .dw $ff05
+ .db "PORTC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTC
+XT_PORTC:
+ .dw PFA_DOVARIABLE
+PFA_PORTC:
+ .dw 40
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Direction Register
+VE_DDRC:
+ .dw $ff04
+ .db "DDRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRC
+XT_DDRC:
+ .dw PFA_DOVARIABLE
+PFA_DDRC:
+ .dw 39
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Input Pins
+VE_PINC:
+ .dw $ff04
+ .db "PINC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINC
+XT_PINC:
+ .dw PFA_DOVARIABLE
+PFA_PINC:
+ .dw 38
+
+.endif
+.if WANT_PORTD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw 43
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw 42
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw 41
+
+.endif
+.if WANT_PORTE == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port E
+VE_PORTE:
+ .dw $ff05
+ .db "PORTE",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTE
+XT_PORTE:
+ .dw PFA_DOVARIABLE
+PFA_PORTE:
+ .dw 46
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port E
+VE_DDRE:
+ .dw $ff04
+ .db "DDRE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRE
+XT_DDRE:
+ .dw PFA_DOVARIABLE
+PFA_DDRE:
+ .dw 45
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port E
+VE_PINE:
+ .dw $ff04
+ .db "PINE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINE
+XT_PINE:
+ .dw PFA_DOVARIABLE
+PFA_PINE:
+ .dw 44
+
+.endif
+.if WANT_PORTF == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port F
+VE_PORTF:
+ .dw $ff05
+ .db "PORTF",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTF
+XT_PORTF:
+ .dw PFA_DOVARIABLE
+PFA_PORTF:
+ .dw 49
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port F
+VE_DDRF:
+ .dw $ff04
+ .db "DDRF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRF
+XT_DDRF:
+ .dw PFA_DOVARIABLE
+PFA_DDRF:
+ .dw 48
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port F
+VE_PINF:
+ .dw $ff04
+ .db "PINF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINF
+XT_PINF:
+ .dw PFA_DOVARIABLE
+PFA_PINF:
+ .dw 47
+
+.endif
+.if WANT_PORTG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Data Register
+VE_PORTG:
+ .dw $ff05
+ .db "PORTG",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTG
+XT_PORTG:
+ .dw PFA_DOVARIABLE
+PFA_PORTG:
+ .dw 52
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Data Direction Register
+VE_DDRG:
+ .dw $ff04
+ .db "DDRG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRG
+XT_DDRG:
+ .dw PFA_DOVARIABLE
+PFA_DDRG:
+ .dw 51
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Input Pins
+VE_PING:
+ .dw $ff04
+ .db "PING"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PING
+XT_PING:
+ .dw PFA_DOVARIABLE
+PFA_PING:
+ .dw 50
+
+.endif
+.if WANT_TIMER_COUNTER_0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Control Register
+VE_TCCR0A:
+ .dw $ff06
+ .db "TCCR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0A
+XT_TCCR0A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0A:
+ .dw 68
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw 70
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0A:
+ .dw $ff05
+ .db "OCR0A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0A
+XT_OCR0A:
+ .dw PFA_DOVARIABLE
+PFA_OCR0A:
+ .dw 71
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Mask Register
+VE_TIMSK0:
+ .dw $ff06
+ .db "TIMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK0
+XT_TIMSK0:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK0:
+ .dw 110
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Flag register
+VE_TIFR0:
+ .dw $ff05
+ .db "TIFR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR0
+XT_TIFR0:
+ .dw PFA_DOVARIABLE
+PFA_TIFR0:
+ .dw 53
+; ( -- addr ) System Constant
+; R( -- )
+; General Timer/Control Register
+VE_GTCCR:
+ .dw $ff05
+ .db "GTCCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GTCCR
+XT_GTCCR:
+ .dw PFA_DOVARIABLE
+PFA_GTCCR:
+ .dw 67
+
+.endif
+.if WANT_TIMER_COUNTER_1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw 128
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw 129
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter 1 Control Register C
+VE_TCCR1C:
+ .dw $ff06
+ .db "TCCR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1C
+XT_TCCR1C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1C:
+ .dw 130
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Bytes
+VE_TCNT1:
+ .dw $ff05
+ .db "TCNT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1
+XT_TCNT1:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1:
+ .dw 132
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register A Bytes
+VE_OCR1A:
+ .dw $ff05
+ .db "OCR1A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1A
+XT_OCR1A:
+ .dw PFA_DOVARIABLE
+PFA_OCR1A:
+ .dw 136
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register B Bytes
+VE_OCR1B:
+ .dw $ff05
+ .db "OCR1B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1B
+XT_OCR1B:
+ .dw PFA_DOVARIABLE
+PFA_OCR1B:
+ .dw 138
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Bytes
+VE_ICR1:
+ .dw $ff04
+ .db "ICR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1
+XT_ICR1:
+ .dw PFA_DOVARIABLE
+PFA_ICR1:
+ .dw 134
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Mask Register
+VE_TIMSK1:
+ .dw $ff06
+ .db "TIMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK1
+XT_TIMSK1:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK1:
+ .dw 111
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Flag register
+VE_TIFR1:
+ .dw $ff05
+ .db "TIFR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR1
+XT_TIFR1:
+ .dw PFA_DOVARIABLE
+PFA_TIFR1:
+ .dw 54
+
+.endif
+.if WANT_TIMER_COUNTER_2 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register
+VE_TCCR2A:
+ .dw $ff06
+ .db "TCCR2A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2A
+XT_TCCR2A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2A:
+ .dw 176
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2
+VE_TCNT2:
+ .dw $ff05
+ .db "TCNT2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT2
+XT_TCNT2:
+ .dw PFA_DOVARIABLE
+PFA_TCNT2:
+ .dw 178
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register
+VE_OCR2A:
+ .dw $ff05
+ .db "OCR2A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2A
+XT_OCR2A:
+ .dw PFA_DOVARIABLE
+PFA_OCR2A:
+ .dw 179
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Interrupt Mask register
+VE_TIMSK2:
+ .dw $ff06
+ .db "TIMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK2
+XT_TIMSK2:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK2:
+ .dw 112
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Interrupt Flag Register
+VE_TIFR2:
+ .dw $ff05
+ .db "TIFR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR2
+XT_TIFR2:
+ .dw PFA_DOVARIABLE
+PFA_TIFR2:
+ .dw 55
+; ( -- addr ) System Constant
+; R( -- )
+; Asynchronous Status Register
+VE_ASSR:
+ .dw $ff04
+ .db "ASSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ASSR
+XT_ASSR:
+ .dw PFA_DOVARIABLE
+PFA_ASSR:
+ .dw 182
+
+.endif
+.if WANT_WATCHDOG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCR:
+ .dw $ff05
+ .db "WDTCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCR
+XT_WDTCR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCR:
+ .dw 96
+
+.endif
+.if WANT_BOOT_LOAD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control Register
+VE_SPMCSR:
+ .dw $ff06
+ .db "SPMCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCSR
+XT_SPMCSR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCSR:
+ .dw 87
+
+.endif
+.if WANT_PORTH == 1
+; ( -- addr ) System Constant
+; R( -- )
+; PORT H Data Register
+VE_PORTH:
+ .dw $ff05
+ .db "PORTH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTH
+XT_PORTH:
+ .dw PFA_DOVARIABLE
+PFA_PORTH:
+ .dw 218
+; ( -- addr ) System Constant
+; R( -- )
+; PORT H Data Direction Register
+VE_DDRH:
+ .dw $ff04
+ .db "DDRH"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRH
+XT_DDRH:
+ .dw PFA_DOVARIABLE
+PFA_DDRH:
+ .dw 217
+; ( -- addr ) System Constant
+; R( -- )
+; PORT H Input Pins
+VE_PINH:
+ .dw $ff04
+ .db "PINH"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINH
+XT_PINH:
+ .dw PFA_DOVARIABLE
+PFA_PINH:
+ .dw 216
+
+.endif
+.if WANT_PORTJ == 1
+; ( -- addr ) System Constant
+; R( -- )
+; PORT J Data Register
+VE_PORTJ:
+ .dw $ff05
+ .db "PORTJ",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTJ
+XT_PORTJ:
+ .dw PFA_DOVARIABLE
+PFA_PORTJ:
+ .dw 221
+; ( -- addr ) System Constant
+; R( -- )
+; PORT J Data Direction Register
+VE_DDRJ:
+ .dw $ff04
+ .db "DDRJ"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRJ
+XT_DDRJ:
+ .dw PFA_DOVARIABLE
+PFA_DDRJ:
+ .dw 220
+; ( -- addr ) System Constant
+; R( -- )
+; PORT J Input Pins
+VE_PINJ:
+ .dw $ff04
+ .db "PINJ"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINJ
+XT_PINJ:
+ .dw PFA_DOVARIABLE
+PFA_PINJ:
+ .dw 219
+
+.endif
+.if WANT_LCD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 19
+VE_LCDDR19:
+ .dw $ff07
+ .db "LCDDR19",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR19
+XT_LCDDR19:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR19:
+ .dw 255
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 18
+VE_LCDDR18:
+ .dw $ff07
+ .db "LCDDR18",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR18
+XT_LCDDR18:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR18:
+ .dw 254
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 17
+VE_LCDDR17:
+ .dw $ff07
+ .db "LCDDR17",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR17
+XT_LCDDR17:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR17:
+ .dw 253
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 16
+VE_LCDDR16:
+ .dw $ff07
+ .db "LCDDR16",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR16
+XT_LCDDR16:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR16:
+ .dw 252
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 15
+VE_LCDDR15:
+ .dw $ff07
+ .db "LCDDR15",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR15
+XT_LCDDR15:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR15:
+ .dw 251
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 14
+VE_LCDDR14:
+ .dw $ff07
+ .db "LCDDR14",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR14
+XT_LCDDR14:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR14:
+ .dw 250
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 13
+VE_LCDDR13:
+ .dw $ff07
+ .db "LCDDR13",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR13
+XT_LCDDR13:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR13:
+ .dw 249
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 12
+VE_LCDDR12:
+ .dw $ff07
+ .db "LCDDR12",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR12
+XT_LCDDR12:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR12:
+ .dw 248
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 11
+VE_LCDDR11:
+ .dw $ff07
+ .db "LCDDR11",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR11
+XT_LCDDR11:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR11:
+ .dw 247
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 10
+VE_LCDDR10:
+ .dw $ff07
+ .db "LCDDR10",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR10
+XT_LCDDR10:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR10:
+ .dw 246
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 9
+VE_LCDDR9:
+ .dw $ff06
+ .db "LCDDR9"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR9
+XT_LCDDR9:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR9:
+ .dw 245
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 8
+VE_LCDDR8:
+ .dw $ff06
+ .db "LCDDR8"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR8
+XT_LCDDR8:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR8:
+ .dw 244
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 7
+VE_LCDDR7:
+ .dw $ff06
+ .db "LCDDR7"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR7
+XT_LCDDR7:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR7:
+ .dw 243
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 6
+VE_LCDDR6:
+ .dw $ff06
+ .db "LCDDR6"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR6
+XT_LCDDR6:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR6:
+ .dw 242
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 5
+VE_LCDDR5:
+ .dw $ff06
+ .db "LCDDR5"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR5
+XT_LCDDR5:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR5:
+ .dw 241
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 4
+VE_LCDDR4:
+ .dw $ff06
+ .db "LCDDR4"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR4
+XT_LCDDR4:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR4:
+ .dw 240
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 3
+VE_LCDDR3:
+ .dw $ff06
+ .db "LCDDR3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR3
+XT_LCDDR3:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR3:
+ .dw 239
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 2
+VE_LCDDR2:
+ .dw $ff06
+ .db "LCDDR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR2
+XT_LCDDR2:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR2:
+ .dw 238
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 1
+VE_LCDDR1:
+ .dw $ff06
+ .db "LCDDR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR1
+XT_LCDDR1:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR1:
+ .dw 237
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 0
+VE_LCDDR0:
+ .dw $ff06
+ .db "LCDDR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR0
+XT_LCDDR0:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR0:
+ .dw 236
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Contrast Control Register
+VE_LCDCCR:
+ .dw $ff06
+ .db "LCDCCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDCCR
+XT_LCDCCR:
+ .dw PFA_DOVARIABLE
+PFA_LCDCCR:
+ .dw 231
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Frame Rate Register
+VE_LCDFRR:
+ .dw $ff06
+ .db "LCDFRR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDFRR
+XT_LCDFRR:
+ .dw PFA_DOVARIABLE
+PFA_LCDFRR:
+ .dw 230
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Control and Status Register B
+VE_LCDCRB:
+ .dw $ff06
+ .db "LCDCRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDCRB
+XT_LCDCRB:
+ .dw PFA_DOVARIABLE
+PFA_LCDCRB:
+ .dw 229
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Control and Status Register A
+VE_LCDCRA:
+ .dw $ff06
+ .db "LCDCRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDCRA
+XT_LCDCRA:
+ .dw PFA_DOVARIABLE
+PFA_LCDCRA:
+ .dw 228
+
+.endif
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register A
+VE_EICRA:
+ .dw $ff05
+ .db "EICRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRA
+XT_EICRA:
+ .dw PFA_DOVARIABLE
+PFA_EICRA:
+ .dw 105
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Mask Register
+VE_EIMSK:
+ .dw $ff05
+ .db "EIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIMSK
+XT_EIMSK:
+ .dw PFA_DOVARIABLE
+PFA_EIMSK:
+ .dw 61
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Flag Register
+VE_EIFR:
+ .dw $ff04
+ .db "EIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIFR
+XT_EIFR:
+ .dw PFA_DOVARIABLE
+PFA_EIFR:
+ .dw 60
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 3
+VE_PCMSK3:
+ .dw $ff06
+ .db "PCMSK3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK3
+XT_PCMSK3:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK3:
+ .dw 115
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 2
+VE_PCMSK2:
+ .dw $ff06
+ .db "PCMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK2
+XT_PCMSK2:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK2:
+ .dw 109
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 1
+VE_PCMSK1:
+ .dw $ff06
+ .db "PCMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK1
+XT_PCMSK1:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK1:
+ .dw 108
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 0
+VE_PCMSK0:
+ .dw $ff06
+ .db "PCMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK0
+XT_PCMSK0:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK0:
+ .dw 107
+
+.endif
diff --git a/amforth-6.5/avr8/devices/atmega6490/device.py b/amforth-6.5/avr8/devices/atmega6490/device.py
new file mode 100644
index 0000000..ba47702
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega6490/device.py
@@ -0,0 +1,370 @@
+# Generated Automatically
+
+# Partname ATmega6490
+
+MCUREGS = {
+# Interrupt Vectors
+ 'INT0Addr' : '#2', # External Interrupt Request 0
+ 'PCINT0Addr' : '#4', # Pin Change Interrupt Request 0
+ 'PCINT1Addr' : '#6', # Pin Change Interrupt Request 1
+ 'TIMER2_COMPAddr' : '#8', # Timer/Counter2 Compare Match
+ 'TIMER2_OVFAddr' : '#10', # Timer/Counter2 Overflow
+ 'TIMER1_CAPTAddr' : '#12', # Timer/Counter1 Capture Event
+ 'TIMER1_COMPAAddr' : '#14', # Timer/Counter1 Compare Match A
+ 'TIMER1_COMPBAddr' : '#16', # Timer/Counter Compare Match B
+ 'TIMER1_OVFAddr' : '#18', # Timer/Counter1 Overflow
+ 'TIMER0_COMPAddr' : '#20', # Timer/Counter0 Compare Match
+ 'TIMER0_OVFAddr' : '#22', # Timer/Counter0 Overflow
+ 'SPI_STCAddr' : '#24', # SPI Serial Transfer Complete
+ 'USART_RXAddr' : '#26', # USART, Rx Complete
+ 'USART_UDREAddr' : '#28', # USART Data register Empty
+ 'USART0_TXAddr' : '#30', # USART0, Tx Complete
+ 'USI_STARTAddr' : '#32', # USI Start Condition
+ 'USI_OVERFLOWAddr' : '#34', # USI Overflow
+ 'ANALOG_COMPAddr' : '#36', # Analog Comparator
+ 'ADCAddr' : '#38', # ADC Conversion Complete
+ 'EE_READYAddr' : '#40', # EEPROM Ready
+ 'SPM_READYAddr' : '#42', # Store Program Memory Read
+ 'LCDAddr' : '#44', # LCD Start of Frame
+ 'PCINT2Addr' : '#46', # Pin Change Interrupt Request 2
+ 'PCINT3Addr' : '#48', # Pin Change Interrupt Request 3
+
+# Module AD_CONVERTER
+ 'ADMUX' : '$7c', # The ADC multiplexer Selection
+ 'ADMUX_REFS': '$c0', # Reference Selection Bits
+ 'ADMUX_ADLAR': '$20', # Left Adjust Result
+ 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
+ 'ADCSRA' : '$7a', # The ADC Control and Status reg
+ 'ADCSRA_ADEN': '$80', # ADC Enable
+ 'ADCSRA_ADSC': '$40', # ADC Start Conversion
+ 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
+ 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
+ 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
+ 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
+ 'ADC' : '$78', # ADC Data Register Bytes
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Sources
+ 'DIDR0' : '$7e', # Digital Input Disable Register
+ 'DIDR0_ADC7D': '$80', # ADC7 Digital input Disable
+ 'DIDR0_ADC6D': '$40', # ADC6 Digital input Disable
+ 'DIDR0_ADC5D': '$20', # ADC5 Digital input Disable
+ 'DIDR0_ADC4D': '$10', # ADC4 Digital input Disable
+ 'DIDR0_ADC3D': '$8', # ADC3 Digital input Disable
+ 'DIDR0_ADC2D': '$4', # ADC2 Digital input Disable
+ 'DIDR0_ADC1D': '$2', # ADC1 Digital input Disable
+ 'DIDR0_ADC0D': '$1', # ADC0 Digital input Disable
+
+# Module ANALOG_COMPARATOR
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
+ 'ACSR' : '$50', # Analog Comparator Control And
+ 'ACSR_ACD': '$80', # Analog Comparator Disable
+ 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
+ 'ACSR_ACO': '$20', # Analog Compare Output
+ 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
+ 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
+ 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
+ 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
+ 'DIDR1' : '$7f', # Digital Input Disable Register
+ 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
+ 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
+
+# Module SPI
+ 'SPCR' : '$4c', # SPI Control Register
+ 'SPCR_SPIE': '$80', # SPI Interrupt Enable
+ 'SPCR_SPE': '$40', # SPI Enable
+ 'SPCR_DORD': '$20', # Data Order
+ 'SPCR_MSTR': '$10', # Master/Slave Select
+ 'SPCR_CPOL': '$8', # Clock polarity
+ 'SPCR_CPHA': '$4', # Clock Phase
+ 'SPCR_SPR': '$3', # SPI Clock Rate Selects
+ 'SPSR' : '$4d', # SPI Status Register
+ 'SPSR_SPIF': '$80', # SPI Interrupt Flag
+ 'SPSR_WCOL': '$40', # Write Collision Flag
+ 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
+ 'SPDR' : '$4e', # SPI Data Register
+
+# Module USI
+ 'USIDR' : '$ba', # USI Data Register
+ 'USISR' : '$b9', # USI Status Register
+ 'USISR_USISIF': '$80', # Start Condition Interrupt Flag
+ 'USISR_USIOIF': '$40', # Counter Overflow Interrupt Fla
+ 'USISR_USIPF': '$20', # Stop Condition Flag
+ 'USISR_USIDC': '$10', # Data Output Collision
+ 'USISR_USICNT': '$f', # USI Counter Value Bits
+ 'USICR' : '$b8', # USI Control Register
+ 'USICR_USISIE': '$80', # Start Condition Interrupt Enab
+ 'USICR_USIOIE': '$40', # Counter Overflow Interrupt Ena
+ 'USICR_USIWM': '$30', # USI Wire Mode Bits
+ 'USICR_USICS': '$c', # USI Clock Source Select Bits
+ 'USICR_USICLK': '$2', # Clock Strobe
+ 'USICR_USITC': '$1', # Toggle Clock Port Pin
+
+# Module USART0
+ 'UDR0' : '$c6', # USART I/O Data Register
+ 'UCSR0A' : '$c0', # USART Control and Status Regis
+ 'UCSR0A_RXC0': '$80', # USART Receive Complete
+ 'UCSR0A_TXC0': '$40', # USART Transmit Complete
+ 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
+ 'UCSR0A_FE0': '$10', # Framing Error
+ 'UCSR0A_DOR0': '$8', # Data OverRun
+ 'UCSR0A_UPE0': '$4', # USART Parity Error
+ 'UCSR0A_U2X0': '$2', # Double the USART Transmission
+ 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
+ 'UCSR0B' : '$c1', # USART Control and Status Regis
+ 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
+ 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
+ 'UCSR0B_UDRIE0': '$20', # USART Data Register Empty Inte
+ 'UCSR0B_RXEN0': '$10', # Receiver Enable
+ 'UCSR0B_TXEN0': '$8', # Transmitter Enable
+ 'UCSR0B_UCSZ02': '$4', # Character Size
+ 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
+ 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
+ 'UCSR0C' : '$c2', # USART Control and Status Regis
+ 'UCSR0C_UMSEL0': '$40', # USART Mode Select
+ 'UCSR0C_UPM0': '$30', # Parity Mode Bits
+ 'UCSR0C_USBS0': '$8', # Stop Bit Select
+ 'UCSR0C_UCSZ0': '$6', # Character Size
+ 'UCSR0C_UCPOL0': '$1', # Clock Polarity
+ 'UBRR0' : '$c4', # USART Baud Rate Register Byte
+
+# Module CPU
+ 'SREG' : '$5f', # Status Register
+ 'SREG_I': '$80', # Global Interrupt Enable
+ 'SREG_T': '$40', # Bit Copy Storage
+ 'SREG_H': '$20', # Half Carry Flag
+ 'SREG_S': '$10', # Sign Bit
+ 'SREG_V': '$8', # Two's Complement Overflow Flag
+ 'SREG_N': '$4', # Negative Flag
+ 'SREG_Z': '$2', # Zero Flag
+ 'SREG_C': '$1', # Carry Flag
+ 'SP' : '$5d', # Stack Pointer
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_PUD': '$10', # Pull-up disable
+ 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
+ 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+ 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
+ 'MCUSR_BORF': '$4', # Brown-out Reset Flag
+ 'MCUSR_EXTRF': '$2', # External Reset Flag
+ 'MCUSR_PORF': '$1', # Power-on reset flag
+ 'OSCCAL' : '$66', # Oscillator Calibration Value
+ 'CLKPR' : '$61', # Clock Prescale Register
+ 'CLKPR_CLKPCE': '$80', # Clock Prescaler Change Enable
+ 'CLKPR_CLKPS': '$f', # Clock Prescaler Select Bits
+ 'PRR' : '$64', # Power Reduction Register
+ 'PRR_PRLCD': '$10', # Power Reduction LCD
+ 'PRR_PRTIM1': '$8', # Power Reduction Timer/Counter1
+ 'PRR_PRSPI': '$4', # Power Reduction Serial Periphe
+ 'PRR_PRUSART0': '$2', # Power Reduction USART
+ 'PRR_PRADC': '$1', # Power Reduction ADC
+ 'SMCR' : '$53', # Sleep Mode Control Register
+ 'SMCR_SM': '$e', # Sleep Mode Select bits
+ 'SMCR_SE': '$1', # Sleep Enable
+ 'GPIOR2' : '$4b', # General Purpose IO Register 2
+ 'GPIOR1' : '$4a', # General Purpose IO Register 1
+ 'GPIOR0' : '$3e', # General Purpose IO Register 0
+
+# Module JTAG
+ 'OCDR' : '$51', # On-Chip Debug Related Register
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_JTD': '$80', # JTAG Interface Disable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+
+# Module EEPROM
+ 'EEAR' : '$41', # EEPROM Read/Write Access Byte
+ 'EEDR' : '$40', # EEPROM Data Register
+ 'EECR' : '$3f', # EEPROM Control Register
+ 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
+ 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
+ 'EECR_EEWE': '$2', # EEPROM Write Enable
+ 'EECR_EERE': '$1', # EEPROM Read Enable
+
+# Module PORTA
+ 'PORTA' : '$22', # Port A Data Register
+ 'DDRA' : '$21', # Port A Data Direction Register
+ 'PINA' : '$20', # Port A Input Pins
+
+# Module PORTB
+ 'PORTB' : '$25', # Port B Data Register
+ 'DDRB' : '$24', # Port B Data Direction Register
+ 'PINB' : '$23', # Port B Input Pins
+
+# Module PORTC
+ 'PORTC' : '$28', # Port C Data Register
+ 'DDRC' : '$27', # Port C Data Direction Register
+ 'PINC' : '$26', # Port C Input Pins
+
+# Module PORTD
+ 'PORTD' : '$2b', # Port D Data Register
+ 'DDRD' : '$2a', # Port D Data Direction Register
+ 'PIND' : '$29', # Port D Input Pins
+
+# Module PORTE
+ 'PORTE' : '$2e', # Data Register, Port E
+ 'DDRE' : '$2d', # Data Direction Register, Port
+ 'PINE' : '$2c', # Input Pins, Port E
+
+# Module PORTF
+ 'PORTF' : '$31', # Data Register, Port F
+ 'DDRF' : '$30', # Data Direction Register, Port
+ 'PINF' : '$2f', # Input Pins, Port F
+
+# Module PORTG
+ 'PORTG' : '$34', # Port G Data Register
+ 'DDRG' : '$33', # Port G Data Direction Register
+ 'PING' : '$32', # Port G Input Pins
+
+# Module TIMER_COUNTER_0
+ 'TCCR0A' : '$44', # Timer/Counter0 Control Registe
+ 'TCCR0A_FOC0A': '$80', # Force Output Compare
+ 'TCCR0A_WGM00': '$40', # Waveform Generation Mode 0
+ 'TCCR0A_COM0A': '$30', # Compare Match Output Modes
+ 'TCCR0A_WGM01': '$8', # Waveform Generation Mode 1
+ 'TCCR0A_CS0': '$7', # Clock Selects
+ 'TCNT0' : '$46', # Timer/Counter0
+ 'OCR0A' : '$47', # Timer/Counter0 Output Compare
+ 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
+ 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
+ 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
+ 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
+ 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
+ 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Control Register
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSR310': '$1', # Prescaler Reset Timer/Counter1
+
+# Module TIMER_COUNTER_1
+ 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
+ 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
+ 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
+ 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
+ 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
+ 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
+ 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
+ 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
+ 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
+ 'TCCR1C' : '$82', # Timer/Counter 1 Control Regist
+ 'TCCR1C_FOC1A': '$80', # Force Output Compare 1A
+ 'TCCR1C_FOC1B': '$40', # Force Output Compare 1B
+ 'TCNT1' : '$84', # Timer/Counter1 Bytes
+ 'OCR1A' : '$88', # Timer/Counter1 Output Compare
+ 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
+ 'ICR1' : '$86', # Timer/Counter1 Input Capture R
+ 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
+ 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
+ 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
+ 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
+ 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
+ 'TIFR1' : '$36', # Timer/Counter1 Interrupt Flag
+ 'TIFR1_ICF1': '$20', # Input Capture Flag 1
+ 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
+ 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
+ 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
+
+# Module TIMER_COUNTER_2
+ 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
+ 'TCCR2A_FOC2A': '$80', # Force Output Compare A
+ 'TCCR2A_WGM20': '$40', # Waveform Generation Mode
+ 'TCCR2A_COM2A': '$30', # Compare Output Mode bits
+ 'TCCR2A_WGM21': '$8', # Waveform Generation Mode
+ 'TCCR2A_CS2': '$7', # Clock Select bits
+ 'TCNT2' : '$b2', # Timer/Counter2
+ 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
+ 'TIMSK2' : '$70', # Timer/Counter2 Interrupt Mask
+ 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
+ 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
+ 'TIFR2' : '$37', # Timer/Counter2 Interrupt Flag
+ 'TIFR2_OCF2A': '$2', # Timer/Counter2 Output Compare
+ 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_PSR2': '$2', # Prescaler Reset Timer/Counter2
+ 'ASSR' : '$b6', # Asynchronous Status Register
+ 'ASSR_EXCLK': '$10', # Enable External Clock Interrup
+ 'ASSR_AS2': '$8', # AS2: Asynchronous Timer/Counte
+ 'ASSR_TCN2UB': '$4', # TCN2UB: Timer/Counter2 Update
+ 'ASSR_OCR2UB': '$2', # Output Compare Register2 Updat
+ 'ASSR_TCR2UB': '$1', # TCR2UB: Timer/Counter Control
+
+# Module WATCHDOG
+ 'WDTCR' : '$60', # Watchdog Timer Control Registe
+ 'WDTCR_WDCE': '$10', # Watchdog Change Enable
+ 'WDTCR_WDE': '$8', # Watch Dog Enable
+ 'WDTCR_WDP': '$7', # Watch Dog Timer Prescaler bits
+
+# Module BOOT_LOAD
+ 'SPMCSR' : '$57', # Store Program Memory Control R
+ 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
+ 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
+ 'SPMCSR_RWWSRE': '$10', # Read While Write section read
+ 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
+ 'SPMCSR_PGWRT': '$4', # Page Write
+ 'SPMCSR_PGERS': '$2', # Page Erase
+ 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
+
+# Module PORTH
+ 'PORTH' : '$da', # PORT H Data Register
+ 'DDRH' : '$d9', # PORT H Data Direction Register
+ 'PINH' : '$d8', # PORT H Input Pins
+
+# Module PORTJ
+ 'PORTJ' : '$dd', # PORT J Data Register
+ 'DDRJ' : '$dc', # PORT J Data Direction Register
+ 'PINJ' : '$db', # PORT J Input Pins
+
+# Module LCD
+ 'LCDDR19' : '$ff', # LCD Data Register 19
+ 'LCDDR18' : '$fe', # LCD Data Register 18
+ 'LCDDR17' : '$fd', # LCD Data Register 17
+ 'LCDDR16' : '$fc', # LCD Data Register 16
+ 'LCDDR15' : '$fb', # LCD Data Register 15
+ 'LCDDR14' : '$fa', # LCD Data Register 14
+ 'LCDDR13' : '$f9', # LCD Data Register 13
+ 'LCDDR12' : '$f8', # LCD Data Register 12
+ 'LCDDR11' : '$f7', # LCD Data Register 11
+ 'LCDDR10' : '$f6', # LCD Data Register 10
+ 'LCDDR9' : '$f5', # LCD Data Register 9
+ 'LCDDR8' : '$f4', # LCD Data Register 8
+ 'LCDDR7' : '$f3', # LCD Data Register 7
+ 'LCDDR6' : '$f2', # LCD Data Register 6
+ 'LCDDR5' : '$f1', # LCD Data Register 5
+ 'LCDDR4' : '$f0', # LCD Data Register 4
+ 'LCDDR3' : '$ef', # LCD Data Register 3
+ 'LCDDR2' : '$ee', # LCD Data Register 2
+ 'LCDDR1' : '$ed', # LCD Data Register 1
+ 'LCDDR0' : '$ec', # LCD Data Register 0
+ 'LCDCCR' : '$e7', # LCD Contrast Control Register
+ 'LCDFRR' : '$e6', # LCD Frame Rate Register
+ 'LCDFRR_LCDPS': '$70', # LCD Prescaler Selects
+ 'LCDFRR_LCDCD': '$7', # LCD Clock Dividers
+ 'LCDCRB' : '$e5', # LCD Control and Status Registe
+ 'LCDCRB_LCDCS': '$80', # LCD CLock Select
+ 'LCDCRB_LCD2B': '$40', # LCD 1/2 Bias Select
+ 'LCDCRB_LCDMUX': '$30', # LCD Mux Selects
+ 'LCDCRB_LCDPM': '$f', # LCD Port Masks
+ 'LCDCRA' : '$e4', # LCD Control and Status Registe
+ 'LCDCRA_LCDEN': '$80', # LCD Enable
+ 'LCDCRA_LCDAB': '$40', # LCD A or B waveform
+ 'LCDCRA_LCDIF': '$10', # LCD Interrupt Flag
+ 'LCDCRA_LCDIE': '$8', # LCD Interrupt Enable
+ 'LCDCRA_LCDBL': '$1', # LCD Blanking
+
+# Module EXTERNAL_INTERRUPT
+ 'EICRA' : '$69', # External Interrupt Control Reg
+ 'EICRA_ISC01': '$2', # External Interrupt Sense Contr
+ 'EICRA_ISC00': '$1', # External Interrupt Sense Contr
+ 'EIMSK' : '$3d', # External Interrupt Mask Regist
+ 'EIMSK_PCIE': '$f0', # Pin Change Interrupt Enables
+ 'EIMSK_INT0': '$1', # External Interrupt Request 0 E
+ 'EIFR' : '$3c', # External Interrupt Flag Regist
+ 'EIFR_PCIF': '$f0', # Pin Change Interrupt Flags
+ 'EIFR_INTF0': '$1', # External Interrupt Flag 0
+ 'PCMSK3' : '$73', # Pin Change Mask Register 3
+ 'PCMSK2' : '$6d', # Pin Change Mask Register 2
+ 'PCMSK1' : '$6c', # Pin Change Mask Register 1
+ 'PCMSK0' : '$6b', # Pin Change Mask Register 0
+
+ '__amforth_dummy':'0'
+}
diff --git a/amforth-6.5/avr8/devices/atmega6490/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega6490/words/no-jtag.asm
new file mode 100644
index 0000000..352a4bb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega6490/words/no-jtag.asm
@@ -0,0 +1,14 @@
+; ( -- )
+; ( -- )
+; MCU
+; disable jtag at runtime
+VE_NOJTAG:
+ .dw $FF05
+ .db "-jtag",0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOJTAG
+XT_NOJTAG:
+ .dw PFA_NOJTAG
+PFA_NOJTAG:
+
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega6490/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega6490/words/no-wdt.asm
new file mode 100644
index 0000000..4a12261
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega6490/words/no-wdt.asm
@@ -0,0 +1,22 @@
+; ( -- )
+; MCU
+; disable watch dog timer at runtime
+VE_NOWDT:
+ .dw $ff04
+ .db "-wdt"
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOWDT
+XT_NOWDT:
+ .dw PFA_NOWDT
+PFA_NOWDT:
+
+; Reset WDT
+ wdr
+; Write logical one to WDTOE and WDE
+ in_ temp1, WDTCR
+ ori temp1, (1<<WDTOE)|(1<<WDE)
+ out WDTCR, temp1
+; Turn off WDT
+ ldi temp1, (0<<WDE)
+ out_ WDTCR, temp1
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega6490/words/sleep.asm b/amforth-6.5/avr8/devices/atmega6490/words/sleep.asm
new file mode 100644
index 0000000..256249c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega6490/words/sleep.asm
@@ -0,0 +1,19 @@
+; ( mode -- )
+; MCU
+; put the controller into the specified sleep mode
+VE_SLEEP:
+ .dw $ff05
+ .db "sleep", 0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_SLEEP
+XT_SLEEP:
+ .dw PFA_SLEEP
+PFA_SLEEP:
+ andi tosl, 7 ; leave only legal mode bits
+ lsl tosl ; move to correct location (bits 3-1)
+ ori tosl, 1 ; set the SE bit
+ out_ SMCR, tosl ; set the sleep config
+ sleep ; nighty-night
+ out_ SMCR, zerol ; 0 protects against accidental sleeps
+ loadtos ; pop argument from stack
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega6490a/atmega6490a.frt b/amforth-6.5/avr8/devices/atmega6490a/atmega6490a.frt
new file mode 100644
index 0000000..6522880
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega6490a/atmega6490a.frt
@@ -0,0 +1,334 @@
+\ Partname: ATmega6490A
+\ generated automatically
+
+\ AD_CONVERTER
+&124 constant ADMUX \ The ADC multiplexer Selection Register
+ $C0 constant ADMUX_REFS \ Reference Selection Bits
+ $20 constant ADMUX_ADLAR \ Left Adjust Result
+ $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
+&122 constant ADCSRA \ The ADC Control and Status register
+ $80 constant ADCSRA_ADEN \ ADC Enable
+ $40 constant ADCSRA_ADSC \ ADC Start Conversion
+ $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
+ $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
+ $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
+ $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
+&120 constant ADC \ ADC Data Register Bytes
+&123 constant ADCSRB \ ADC Control and Status Register B
+ $07 constant ADCSRB_ADTS \ ADC Auto Trigger Sources
+&126 constant DIDR0 \ Digital Input Disable Register 0
+ $80 constant DIDR0_ADC7D \ ADC7 Digital input Disable
+ $40 constant DIDR0_ADC6D \ ADC6 Digital input Disable
+ $20 constant DIDR0_ADC5D \ ADC5 Digital input Disable
+ $10 constant DIDR0_ADC4D \ ADC4 Digital input Disable
+ $08 constant DIDR0_ADC3D \ ADC3 Digital input Disable
+ $04 constant DIDR0_ADC2D \ ADC2 Digital input Disable
+ $02 constant DIDR0_ADC1D \ ADC1 Digital input Disable
+ $01 constant DIDR0_ADC0D \ ADC0 Digital input Disable
+\ ANALOG_COMPARATOR
+&80 constant ACSR \ Analog Comparator Control And Status Register
+ $80 constant ACSR_ACD \ Analog Comparator Disable
+ $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
+ $20 constant ACSR_ACO \ Analog Compare Output
+ $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
+ $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
+ $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
+ $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
+&127 constant DIDR1 \ Digital Input Disable Register 1
+ $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
+ $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
+\ SPI
+&76 constant SPCR \ SPI Control Register
+ $80 constant SPCR_SPIE \ SPI Interrupt Enable
+ $40 constant SPCR_SPE \ SPI Enable
+ $20 constant SPCR_DORD \ Data Order
+ $10 constant SPCR_MSTR \ Master/Slave Select
+ $08 constant SPCR_CPOL \ Clock polarity
+ $04 constant SPCR_CPHA \ Clock Phase
+ $03 constant SPCR_SPR \ SPI Clock Rate Selects
+&77 constant SPSR \ SPI Status Register
+ $80 constant SPSR_SPIF \ SPI Interrupt Flag
+ $40 constant SPSR_WCOL \ Write Collision Flag
+ $01 constant SPSR_SPI2X \ Double SPI Speed Bit
+&78 constant SPDR \ SPI Data Register
+\ USI
+&186 constant USIDR \ USI Data Register
+&185 constant USISR \ USI Status Register
+ $80 constant USISR_USISIF \ Start Condition Interrupt Flag
+ $40 constant USISR_USIOIF \ Counter Overflow Interrupt Flag
+ $20 constant USISR_USIPF \ Stop Condition Flag
+ $10 constant USISR_USIDC \ Data Output Collision
+ $0F constant USISR_USICNT \ USI Counter Value Bits
+&184 constant USICR \ USI Control Register
+ $80 constant USICR_USISIE \ Start Condition Interrupt Enable
+ $40 constant USICR_USIOIE \ Counter Overflow Interrupt Enable
+ $30 constant USICR_USIWM \ USI Wire Mode Bits
+ $0C constant USICR_USICS \ USI Clock Source Select Bits
+ $02 constant USICR_USICLK \ Clock Strobe
+ $01 constant USICR_USITC \ Toggle Clock Port Pin
+\ USART0
+&198 constant UDR0 \ USART I/O Data Register
+&192 constant UCSR0A \ USART Control and Status Register A
+ $80 constant UCSR0A_RXC0 \ USART Receive Complete
+ $40 constant UCSR0A_TXC0 \ USART Transmit Complete
+ $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
+ $10 constant UCSR0A_FE0 \ Framing Error
+ $08 constant UCSR0A_DOR0 \ Data OverRun
+ $04 constant UCSR0A_UPE0 \ USART Parity Error
+ $02 constant UCSR0A_U2X0 \ Double the USART Transmission Speed
+ $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
+&193 constant UCSR0B \ USART Control and Status Register B
+ $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
+ $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
+ $20 constant UCSR0B_UDRIE0 \ USART Data Register Empty Interrupt Enable
+ $10 constant UCSR0B_RXEN0 \ Receiver Enable
+ $08 constant UCSR0B_TXEN0 \ Transmitter Enable
+ $04 constant UCSR0B_UCSZ02 \ Character Size
+ $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
+ $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
+&194 constant UCSR0C \ USART Control and Status Register C
+ $40 constant UCSR0C_UMSEL0 \ USART Mode Select
+ $30 constant UCSR0C_UPM0 \ Parity Mode Bits
+ $08 constant UCSR0C_USBS0 \ Stop Bit Select
+ $06 constant UCSR0C_UCSZ0 \ Character Size
+ $01 constant UCSR0C_UCPOL0 \ Clock Polarity
+&196 constant UBRR0 \ USART Baud Rate Register Bytes
+\ CPU
+&95 constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ $08 constant SREG_V \ Two's Complement Overflow Flag
+ $04 constant SREG_N \ Negative Flag
+ $02 constant SREG_Z \ Zero Flag
+ $01 constant SREG_C \ Carry Flag
+&93 constant SP \ Stack Pointer
+&85 constant MCUCR \ MCU Control Register
+ $10 constant MCUCR_PUD \ Pull-up disable
+ $02 constant MCUCR_IVSEL \ Interrupt Vector Select
+ $01 constant MCUCR_IVCE \ Interrupt Vector Change Enable
+&84 constant MCUSR \ MCU Status Register
+ $10 constant MCUSR_JTRF \ JTAG Reset Flag
+ $08 constant MCUSR_WDRF \ Watchdog Reset Flag
+ $04 constant MCUSR_BORF \ Brown-out Reset Flag
+ $02 constant MCUSR_EXTRF \ External Reset Flag
+ $01 constant MCUSR_PORF \ Power-on reset flag
+&102 constant OSCCAL \ Oscillator Calibration Value
+&97 constant CLKPR \ Clock Prescale Register
+ $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable
+ $0F constant CLKPR_CLKPS \ Clock Prescaler Select Bits
+&100 constant PRR \ Power Reduction Register
+ $10 constant PRR_PRLCD \ Power Reduction LCD
+ $08 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
+ $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
+ $02 constant PRR_PRUSART0 \ Power Reduction USART
+ $01 constant PRR_PRADC \ Power Reduction ADC
+&83 constant SMCR \ Sleep Mode Control Register
+ $0E constant SMCR_SM \ Sleep Mode Select bits
+ $01 constant SMCR_SE \ Sleep Enable
+&75 constant GPIOR2 \ General Purpose IO Register 2
+&74 constant GPIOR1 \ General Purpose IO Register 1
+&62 constant GPIOR0 \ General Purpose IO Register 0
+\ JTAG
+&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
+\ EEPROM
+&65 constant EEAR \ EEPROM Read/Write Access Bytes
+&64 constant EEDR \ EEPROM Data Register
+&63 constant EECR \ EEPROM Control Register
+ $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
+ $04 constant EECR_EEMWE \ EEPROM Master Write Enable
+ $02 constant EECR_EEWE \ EEPROM Write Enable
+ $01 constant EECR_EERE \ EEPROM Read Enable
+\ PORTA
+&34 constant PORTA \ Port A Data Register
+&33 constant DDRA \ Port A Data Direction Register
+&32 constant PINA \ Port A Input Pins
+\ PORTB
+&37 constant PORTB \ Port B Data Register
+&36 constant DDRB \ Port B Data Direction Register
+&35 constant PINB \ Port B Input Pins
+\ PORTC
+&40 constant PORTC \ Port C Data Register
+&39 constant DDRC \ Port C Data Direction Register
+&38 constant PINC \ Port C Input Pins
+\ PORTD
+&43 constant PORTD \ Port D Data Register
+&42 constant DDRD \ Port D Data Direction Register
+&41 constant PIND \ Port D Input Pins
+\ PORTE
+&46 constant PORTE \ Data Register, Port E
+&45 constant DDRE \ Data Direction Register, Port E
+&44 constant PINE \ Input Pins, Port E
+\ PORTF
+&49 constant PORTF \ Data Register, Port F
+&48 constant DDRF \ Data Direction Register, Port F
+&47 constant PINF \ Input Pins, Port F
+\ PORTG
+&52 constant PORTG \ Port G Data Register
+&51 constant DDRG \ Port G Data Direction Register
+&50 constant PING \ Port G Input Pins
+\ TIMER_COUNTER_0
+&68 constant TCCR0A \ Timer/Counter0 Control Register
+ $80 constant TCCR0A_FOC0A \ Force Output Compare
+ $40 constant TCCR0A_WGM00 \ Waveform Generation Mode 0
+ $30 constant TCCR0A_COM0A \ Compare Match Output Modes
+ $08 constant TCCR0A_WGM01 \ Waveform Generation Mode 1
+ $07 constant TCCR0A_CS0 \ Clock Selects
+&70 constant TCNT0 \ Timer/Counter0
+&71 constant OCR0A \ Timer/Counter0 Output Compare Register
+&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
+ $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match Interrupt Enable
+ $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
+&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
+ $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0
+ $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
+&67 constant GTCCR \ General Timer/Control Register
+ $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
+ $01 constant GTCCR_PSR310 \ Prescaler Reset Timer/Counter1 and Timer/Counter0
+\ TIMER_COUNTER_1
+&128 constant TCCR1A \ Timer/Counter1 Control Register A
+ $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
+ $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
+ $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
+&129 constant TCCR1B \ Timer/Counter1 Control Register B
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
+ $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
+&130 constant TCCR1C \ Timer/Counter 1 Control Register C
+ $80 constant TCCR1C_FOC1A \ Force Output Compare 1A
+ $40 constant TCCR1C_FOC1B \ Force Output Compare 1B
+&132 constant TCNT1 \ Timer/Counter1 Bytes
+&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
+&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
+&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
+&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
+ $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
+ $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
+ $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
+ $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
+&54 constant TIFR1 \ Timer/Counter1 Interrupt Flag register
+ $20 constant TIFR1_ICF1 \ Input Capture Flag 1
+ $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
+ $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
+ $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
+\ TIMER_COUNTER_2
+&176 constant TCCR2A \ Timer/Counter2 Control Register
+ $80 constant TCCR2A_FOC2A \ Force Output Compare A
+ $40 constant TCCR2A_WGM20 \ Waveform Generation Mode
+ $30 constant TCCR2A_COM2A \ Compare Output Mode bits
+ $08 constant TCCR2A_WGM21 \ Waveform Generation Mode
+ $07 constant TCCR2A_CS2 \ Clock Select bits
+&178 constant TCNT2 \ Timer/Counter2
+&179 constant OCR2A \ Timer/Counter2 Output Compare Register
+&112 constant TIMSK2 \ Timer/Counter2 Interrupt Mask register
+ $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match Interrupt Enable
+ $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
+&55 constant TIFR2 \ Timer/Counter2 Interrupt Flag Register
+ $02 constant TIFR2_OCF2A \ Timer/Counter2 Output Compare Flag 2
+ $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
+&182 constant ASSR \ Asynchronous Status Register
+ $10 constant ASSR_EXCLK \ Enable External Clock Interrupt
+ $08 constant ASSR_AS2 \ AS2: Asynchronous Timer/Counter2
+ $04 constant ASSR_TCN2UB \ TCN2UB: Timer/Counter2 Update Busy
+ $02 constant ASSR_OCR2UB \ Output Compare Register2 Update Busy
+ $01 constant ASSR_TCR2UB \ TCR2UB: Timer/Counter Control Register2 Update Busy
+\ WATCHDOG
+&96 constant WDTCR \ Watchdog Timer Control Register
+ $10 constant WDTCR_WDCE \ Watchdog Change Enable
+ $08 constant WDTCR_WDE \ Watch Dog Enable
+ $07 constant WDTCR_WDP \ Watch Dog Timer Prescaler bits
+\ BOOT_LOAD
+&87 constant SPMCSR \ Store Program Memory Control Register
+ $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
+ $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
+ $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
+ $04 constant SPMCSR_PGWRT \ Page Write
+ $02 constant SPMCSR_PGERS \ Page Erase
+ $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
+\ PORTH
+&218 constant PORTH \ PORT H Data Register
+&217 constant DDRH \ PORT H Data Direction Register
+&216 constant PINH \ PORT H Input Pins
+\ PORTJ
+&221 constant PORTJ \ PORT J Data Register
+&220 constant DDRJ \ PORT J Data Direction Register
+&219 constant PINJ \ PORT J Input Pins
+\ LCD
+&255 constant LCDDR19 \ LCD Data Register 19
+&254 constant LCDDR18 \ LCD Data Register 18
+&253 constant LCDDR17 \ LCD Data Register 17
+&252 constant LCDDR16 \ LCD Data Register 16
+&251 constant LCDDR15 \ LCD Data Register 15
+&250 constant LCDDR14 \ LCD Data Register 14
+&249 constant LCDDR13 \ LCD Data Register 13
+&248 constant LCDDR12 \ LCD Data Register 12
+&247 constant LCDDR11 \ LCD Data Register 11
+&246 constant LCDDR10 \ LCD Data Register 10
+&245 constant LCDDR9 \ LCD Data Register 9
+&244 constant LCDDR8 \ LCD Data Register 8
+&243 constant LCDDR7 \ LCD Data Register 7
+&242 constant LCDDR6 \ LCD Data Register 6
+&241 constant LCDDR5 \ LCD Data Register 5
+&240 constant LCDDR4 \ LCD Data Register 4
+&239 constant LCDDR3 \ LCD Data Register 3
+&238 constant LCDDR2 \ LCD Data Register 2
+&237 constant LCDDR1 \ LCD Data Register 1
+&236 constant LCDDR0 \ LCD Data Register 0
+&231 constant LCDCCR \ LCD Contrast Control Register
+&230 constant LCDFRR \ LCD Frame Rate Register
+ $70 constant LCDFRR_LCDPS \ LCD Prescaler Selects
+ $07 constant LCDFRR_LCDCD \ LCD Clock Dividers
+&229 constant LCDCRB \ LCD Control and Status Register B
+ $80 constant LCDCRB_LCDCS \ LCD CLock Select
+ $40 constant LCDCRB_LCD2B \ LCD 1/2 Bias Select
+ $30 constant LCDCRB_LCDMUX \ LCD Mux Selects
+ $0F constant LCDCRB_LCDPM \ LCD Port Masks
+&228 constant LCDCRA \ LCD Control and Status Register A
+ $80 constant LCDCRA_LCDEN \ LCD Enable
+ $40 constant LCDCRA_LCDAB \ LCD A or B waveform
+ $10 constant LCDCRA_LCDIF \ LCD Interrupt Flag
+ $08 constant LCDCRA_LCDIE \ LCD Interrupt Enable
+ $01 constant LCDCRA_LCDBL \ LCD Blanking
+\ EXTERNAL_INTERRUPT
+&105 constant EICRA \ External Interrupt Control Register A
+ $02 constant EICRA_ISC01 \ External Interrupt Sense Control 0 Bit 1
+ $01 constant EICRA_ISC00 \ External Interrupt Sense Control 0 Bit 0
+&61 constant EIMSK \ External Interrupt Mask Register
+ $F0 constant EIMSK_PCIE \ Pin Change Interrupt Enables
+ $01 constant EIMSK_INT0 \ External Interrupt Request 0 Enable
+&60 constant EIFR \ External Interrupt Flag Register
+ $F0 constant EIFR_PCIF \ Pin Change Interrupt Flags
+ $01 constant EIFR_INTF0 \ External Interrupt Flag 0
+&115 constant PCMSK3 \ Pin Change Mask Register 3
+&109 constant PCMSK2 \ Pin Change Mask Register 2
+&108 constant PCMSK1 \ Pin Change Mask Register 1
+&107 constant PCMSK0 \ Pin Change Mask Register 0
+
+\ Interrupts
+&2 constant INT0Addr \ External Interrupt Request 0
+&4 constant PCINT0Addr \ Pin Change Interrupt Request 0
+&6 constant PCINT1Addr \ Pin Change Interrupt Request 1
+&8 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
+&10 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
+&12 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+&14 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
+&16 constant TIMER1_COMPBAddr \ Timer/Counter Compare Match B
+&18 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+&20 constant TIMER0_COMPAddr \ Timer/Counter0 Compare Match
+&22 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
+&24 constant SPI__STCAddr \ SPI Serial Transfer Complete
+&26 constant USART__RXAddr \ USART, Rx Complete
+&28 constant USART__UDREAddr \ USART Data register Empty
+&30 constant USART0__TXAddr \ USART0, Tx Complete
+&32 constant USI_STARTAddr \ USI Start Condition
+&34 constant USI_OVERFLOWAddr \ USI Overflow
+&36 constant ANALOG_COMPAddr \ Analog Comparator
+&38 constant ADCAddr \ ADC Conversion Complete
+&40 constant EE_READYAddr \ EEPROM Ready
+&42 constant SPM_READYAddr \ Store Program Memory Read
+&44 constant LCDAddr \ LCD Start of Frame
+&46 constant PCINT2Addr \ Pin Change Interrupt Request 2
+&48 constant PCINT3Addr \ Pin Change Interrupt Request 3
diff --git a/amforth-6.5/avr8/devices/atmega6490a/device.asm b/amforth-6.5/avr8/devices/atmega6490a/device.asm
new file mode 100644
index 0000000..9ef601a
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega6490a/device.asm
@@ -0,0 +1,115 @@
+; Partname: ATmega6490A
+; generated automatically, do not edit
+
+.nolist
+ .include "m6490Adef.inc"
+.list
+
+.equ ramstart = 256
+.equ CELLSIZE = 2
+.macro readflashcell
+ lsl zl
+ rol zh
+ lpm @0, Z+
+ lpm @1, Z+
+.endmacro
+.macro writeflashcell
+ lsl zl
+ rol zh
+.endmacro
+.set WANT_AD_CONVERTER = 0
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_SPI = 0
+.set WANT_USI = 0
+.set WANT_USART0 = 0
+.set WANT_CPU = 0
+.set WANT_JTAG = 0
+.set WANT_EEPROM = 0
+.set WANT_PORTA = 0
+.set WANT_PORTB = 0
+.set WANT_PORTC = 0
+.set WANT_PORTD = 0
+.set WANT_PORTE = 0
+.set WANT_PORTF = 0
+.set WANT_PORTG = 0
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_TIMER_COUNTER_2 = 0
+.set WANT_WATCHDOG = 0
+.set WANT_BOOT_LOAD = 0
+.set WANT_PORTH = 0
+.set WANT_PORTJ = 0
+.set WANT_LCD = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.equ intvecsize = 2 ; please verify; flash size: 65536 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.org 2
+ rcall isr ; External Interrupt Request 0
+.org 4
+ rcall isr ; Pin Change Interrupt Request 0
+.org 6
+ rcall isr ; Pin Change Interrupt Request 1
+.org 8
+ rcall isr ; Timer/Counter2 Compare Match
+.org 10
+ rcall isr ; Timer/Counter2 Overflow
+.org 12
+ rcall isr ; Timer/Counter1 Capture Event
+.org 14
+ rcall isr ; Timer/Counter1 Compare Match A
+.org 16
+ rcall isr ; Timer/Counter Compare Match B
+.org 18
+ rcall isr ; Timer/Counter1 Overflow
+.org 20
+ rcall isr ; Timer/Counter0 Compare Match
+.org 22
+ rcall isr ; Timer/Counter0 Overflow
+.org 24
+ rcall isr ; SPI Serial Transfer Complete
+.org 26
+ rcall isr ; USART, Rx Complete
+.org 28
+ rcall isr ; USART Data register Empty
+.org 30
+ rcall isr ; USART0, Tx Complete
+.org 32
+ rcall isr ; USI Start Condition
+.org 34
+ rcall isr ; USI Overflow
+.org 36
+ rcall isr ; Analog Comparator
+.org 38
+ rcall isr ; ADC Conversion Complete
+.org 40
+ rcall isr ; EEPROM Ready
+.org 42
+ rcall isr ; Store Program Memory Read
+.org 44
+ rcall isr ; LCD Start of Frame
+.org 46
+ rcall isr ; Pin Change Interrupt Request 2
+.org 48
+ rcall isr ; Pin Change Interrupt Request 3
+.equ INTVECTORS = 25
+.nooverlap
+
+; compatability layer (maybe empty)
+.equ EEPE = EEWE
+.equ EEMPE = EEMWE
+
+; controller data area, environment query mcu-info
+mcu_info:
+mcu_ramsize:
+ .dw 4096
+mcu_eepromsize:
+ .dw 2048
+mcu_maxdp:
+ .dw 57344
+mcu_numints:
+ .dw 25
+mcu_name:
+ .dw 11
+ .db "ATmega6490A",0
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega6490a/device.inc b/amforth-6.5/avr8/devices/atmega6490a/device.inc
new file mode 100644
index 0000000..0081bb6
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega6490a/device.inc
@@ -0,0 +1,1443 @@
+; Partname: ATmega6490A
+; generated automatically, no not edit
+
+.if WANT_AD_CONVERTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC multiplexer Selection Register
+VE_ADMUX:
+ .dw $ff05
+ .db "ADMUX",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADMUX
+XT_ADMUX:
+ .dw PFA_DOVARIABLE
+PFA_ADMUX:
+ .dw 124
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register
+VE_ADCSRA:
+ .dw $ff06
+ .db "ADCSRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRA
+XT_ADCSRA:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRA:
+ .dw 122
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register Bytes
+VE_ADC:
+ .dw $ff03
+ .db "ADC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADC
+XT_ADC:
+ .dw PFA_DOVARIABLE
+PFA_ADC:
+ .dw 120
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Control and Status Register B
+VE_ADCSRB:
+ .dw $ff06
+ .db "ADCSRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRB
+XT_ADCSRB:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRB:
+ .dw 123
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 0
+VE_DIDR0:
+ .dw $ff05
+ .db "DIDR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR0
+XT_DIDR0:
+ .dw PFA_DOVARIABLE
+PFA_DIDR0:
+ .dw 126
+
+.endif
+.if WANT_ANALOG_COMPARATOR == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Control And Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw 80
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 1
+VE_DIDR1:
+ .dw $ff05
+ .db "DIDR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR1
+XT_DIDR1:
+ .dw PFA_DOVARIABLE
+PFA_DIDR1:
+ .dw 127
+
+.endif
+.if WANT_SPI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR:
+ .dw $ff04
+ .db "SPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR
+XT_SPCR:
+ .dw PFA_DOVARIABLE
+PFA_SPCR:
+ .dw 76
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR:
+ .dw $ff04
+ .db "SPSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR
+XT_SPSR:
+ .dw PFA_DOVARIABLE
+PFA_SPSR:
+ .dw 77
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR:
+ .dw $ff04
+ .db "SPDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR
+XT_SPDR:
+ .dw PFA_DOVARIABLE
+PFA_SPDR:
+ .dw 78
+
+.endif
+.if WANT_USI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USI Data Register
+VE_USIDR:
+ .dw $ff05
+ .db "USIDR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USIDR
+XT_USIDR:
+ .dw PFA_DOVARIABLE
+PFA_USIDR:
+ .dw 186
+; ( -- addr ) System Constant
+; R( -- )
+; USI Status Register
+VE_USISR:
+ .dw $ff05
+ .db "USISR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USISR
+XT_USISR:
+ .dw PFA_DOVARIABLE
+PFA_USISR:
+ .dw 185
+; ( -- addr ) System Constant
+; R( -- )
+; USI Control Register
+VE_USICR:
+ .dw $ff05
+ .db "USICR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USICR
+XT_USICR:
+ .dw PFA_DOVARIABLE
+PFA_USICR:
+ .dw 184
+
+.endif
+.if WANT_USART0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR0:
+ .dw $ff04
+ .db "UDR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR0
+XT_UDR0:
+ .dw PFA_DOVARIABLE
+PFA_UDR0:
+ .dw 198
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR0A:
+ .dw $ff06
+ .db "UCSR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0A
+XT_UCSR0A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0A:
+ .dw 192
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR0B:
+ .dw $ff06
+ .db "UCSR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0B
+XT_UCSR0B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0B:
+ .dw 193
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR0C:
+ .dw $ff06
+ .db "UCSR0C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0C
+XT_UCSR0C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0C:
+ .dw 194
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Bytes
+VE_UBRR0:
+ .dw $ff05
+ .db "UBRR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR0
+XT_UBRR0:
+ .dw PFA_DOVARIABLE
+PFA_UBRR0:
+ .dw 196
+
+.endif
+.if WANT_CPU == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw 95
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer
+VE_SP:
+ .dw $ff02
+ .db "SP"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SP
+XT_SP:
+ .dw PFA_DOVARIABLE
+PFA_SP:
+ .dw 93
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw 85
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Status Register
+VE_MCUSR:
+ .dw $ff05
+ .db "MCUSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUSR
+XT_MCUSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUSR:
+ .dw 84
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Calibration Value
+VE_OSCCAL:
+ .dw $ff06
+ .db "OSCCAL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSCCAL
+XT_OSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_OSCCAL:
+ .dw 102
+; ( -- addr ) System Constant
+; R( -- )
+; Clock Prescale Register
+VE_CLKPR:
+ .dw $ff05
+ .db "CLKPR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKPR
+XT_CLKPR:
+ .dw PFA_DOVARIABLE
+PFA_CLKPR:
+ .dw 97
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register
+VE_PRR:
+ .dw $ff03
+ .db "PRR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR
+XT_PRR:
+ .dw PFA_DOVARIABLE
+PFA_PRR:
+ .dw 100
+; ( -- addr ) System Constant
+; R( -- )
+; Sleep Mode Control Register
+VE_SMCR:
+ .dw $ff04
+ .db "SMCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SMCR
+XT_SMCR:
+ .dw PFA_DOVARIABLE
+PFA_SMCR:
+ .dw 83
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 2
+VE_GPIOR2:
+ .dw $ff06
+ .db "GPIOR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR2
+XT_GPIOR2:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR2:
+ .dw 75
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 1
+VE_GPIOR1:
+ .dw $ff06
+ .db "GPIOR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR1
+XT_GPIOR1:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR1:
+ .dw 74
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 0
+VE_GPIOR0:
+ .dw $ff06
+ .db "GPIOR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR0
+XT_GPIOR0:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR0:
+ .dw 62
+
+.endif
+.if WANT_JTAG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; On-Chip Debug Related Register in I/O Memory
+VE_OCDR:
+ .dw $ff04
+ .db "OCDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCDR
+XT_OCDR:
+ .dw PFA_DOVARIABLE
+PFA_OCDR:
+ .dw 81
+
+.endif
+.if WANT_EEPROM == 1
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Read/Write Access Bytes
+VE_EEAR:
+ .dw $ff04
+ .db "EEAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEAR
+XT_EEAR:
+ .dw PFA_DOVARIABLE
+PFA_EEAR:
+ .dw 65
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw 64
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw 63
+
+.endif
+.if WANT_PORTA == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Register
+VE_PORTA:
+ .dw $ff05
+ .db "PORTA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTA
+XT_PORTA:
+ .dw PFA_DOVARIABLE
+PFA_PORTA:
+ .dw 34
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Direction Register
+VE_DDRA:
+ .dw $ff04
+ .db "DDRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRA
+XT_DDRA:
+ .dw PFA_DOVARIABLE
+PFA_DDRA:
+ .dw 33
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Input Pins
+VE_PINA:
+ .dw $ff04
+ .db "PINA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINA
+XT_PINA:
+ .dw PFA_DOVARIABLE
+PFA_PINA:
+ .dw 32
+
+.endif
+.if WANT_PORTB == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw 37
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw 36
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw 35
+
+.endif
+.if WANT_PORTC == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Register
+VE_PORTC:
+ .dw $ff05
+ .db "PORTC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTC
+XT_PORTC:
+ .dw PFA_DOVARIABLE
+PFA_PORTC:
+ .dw 40
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Direction Register
+VE_DDRC:
+ .dw $ff04
+ .db "DDRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRC
+XT_DDRC:
+ .dw PFA_DOVARIABLE
+PFA_DDRC:
+ .dw 39
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Input Pins
+VE_PINC:
+ .dw $ff04
+ .db "PINC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINC
+XT_PINC:
+ .dw PFA_DOVARIABLE
+PFA_PINC:
+ .dw 38
+
+.endif
+.if WANT_PORTD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw 43
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw 42
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw 41
+
+.endif
+.if WANT_PORTE == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port E
+VE_PORTE:
+ .dw $ff05
+ .db "PORTE",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTE
+XT_PORTE:
+ .dw PFA_DOVARIABLE
+PFA_PORTE:
+ .dw 46
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port E
+VE_DDRE:
+ .dw $ff04
+ .db "DDRE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRE
+XT_DDRE:
+ .dw PFA_DOVARIABLE
+PFA_DDRE:
+ .dw 45
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port E
+VE_PINE:
+ .dw $ff04
+ .db "PINE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINE
+XT_PINE:
+ .dw PFA_DOVARIABLE
+PFA_PINE:
+ .dw 44
+
+.endif
+.if WANT_PORTF == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port F
+VE_PORTF:
+ .dw $ff05
+ .db "PORTF",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTF
+XT_PORTF:
+ .dw PFA_DOVARIABLE
+PFA_PORTF:
+ .dw 49
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port F
+VE_DDRF:
+ .dw $ff04
+ .db "DDRF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRF
+XT_DDRF:
+ .dw PFA_DOVARIABLE
+PFA_DDRF:
+ .dw 48
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port F
+VE_PINF:
+ .dw $ff04
+ .db "PINF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINF
+XT_PINF:
+ .dw PFA_DOVARIABLE
+PFA_PINF:
+ .dw 47
+
+.endif
+.if WANT_PORTG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Data Register
+VE_PORTG:
+ .dw $ff05
+ .db "PORTG",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTG
+XT_PORTG:
+ .dw PFA_DOVARIABLE
+PFA_PORTG:
+ .dw 52
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Data Direction Register
+VE_DDRG:
+ .dw $ff04
+ .db "DDRG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRG
+XT_DDRG:
+ .dw PFA_DOVARIABLE
+PFA_DDRG:
+ .dw 51
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Input Pins
+VE_PING:
+ .dw $ff04
+ .db "PING"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PING
+XT_PING:
+ .dw PFA_DOVARIABLE
+PFA_PING:
+ .dw 50
+
+.endif
+.if WANT_TIMER_COUNTER_0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Control Register
+VE_TCCR0A:
+ .dw $ff06
+ .db "TCCR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0A
+XT_TCCR0A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0A:
+ .dw 68
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw 70
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0A:
+ .dw $ff05
+ .db "OCR0A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0A
+XT_OCR0A:
+ .dw PFA_DOVARIABLE
+PFA_OCR0A:
+ .dw 71
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Mask Register
+VE_TIMSK0:
+ .dw $ff06
+ .db "TIMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK0
+XT_TIMSK0:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK0:
+ .dw 110
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Flag register
+VE_TIFR0:
+ .dw $ff05
+ .db "TIFR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR0
+XT_TIFR0:
+ .dw PFA_DOVARIABLE
+PFA_TIFR0:
+ .dw 53
+; ( -- addr ) System Constant
+; R( -- )
+; General Timer/Control Register
+VE_GTCCR:
+ .dw $ff05
+ .db "GTCCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GTCCR
+XT_GTCCR:
+ .dw PFA_DOVARIABLE
+PFA_GTCCR:
+ .dw 67
+
+.endif
+.if WANT_TIMER_COUNTER_1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw 128
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw 129
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter 1 Control Register C
+VE_TCCR1C:
+ .dw $ff06
+ .db "TCCR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1C
+XT_TCCR1C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1C:
+ .dw 130
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Bytes
+VE_TCNT1:
+ .dw $ff05
+ .db "TCNT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1
+XT_TCNT1:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1:
+ .dw 132
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register A Bytes
+VE_OCR1A:
+ .dw $ff05
+ .db "OCR1A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1A
+XT_OCR1A:
+ .dw PFA_DOVARIABLE
+PFA_OCR1A:
+ .dw 136
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register B Bytes
+VE_OCR1B:
+ .dw $ff05
+ .db "OCR1B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1B
+XT_OCR1B:
+ .dw PFA_DOVARIABLE
+PFA_OCR1B:
+ .dw 138
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Bytes
+VE_ICR1:
+ .dw $ff04
+ .db "ICR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1
+XT_ICR1:
+ .dw PFA_DOVARIABLE
+PFA_ICR1:
+ .dw 134
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Mask Register
+VE_TIMSK1:
+ .dw $ff06
+ .db "TIMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK1
+XT_TIMSK1:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK1:
+ .dw 111
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Flag register
+VE_TIFR1:
+ .dw $ff05
+ .db "TIFR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR1
+XT_TIFR1:
+ .dw PFA_DOVARIABLE
+PFA_TIFR1:
+ .dw 54
+
+.endif
+.if WANT_TIMER_COUNTER_2 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register
+VE_TCCR2A:
+ .dw $ff06
+ .db "TCCR2A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2A
+XT_TCCR2A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2A:
+ .dw 176
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2
+VE_TCNT2:
+ .dw $ff05
+ .db "TCNT2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT2
+XT_TCNT2:
+ .dw PFA_DOVARIABLE
+PFA_TCNT2:
+ .dw 178
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register
+VE_OCR2A:
+ .dw $ff05
+ .db "OCR2A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2A
+XT_OCR2A:
+ .dw PFA_DOVARIABLE
+PFA_OCR2A:
+ .dw 179
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Interrupt Mask register
+VE_TIMSK2:
+ .dw $ff06
+ .db "TIMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK2
+XT_TIMSK2:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK2:
+ .dw 112
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Interrupt Flag Register
+VE_TIFR2:
+ .dw $ff05
+ .db "TIFR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR2
+XT_TIFR2:
+ .dw PFA_DOVARIABLE
+PFA_TIFR2:
+ .dw 55
+; ( -- addr ) System Constant
+; R( -- )
+; Asynchronous Status Register
+VE_ASSR:
+ .dw $ff04
+ .db "ASSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ASSR
+XT_ASSR:
+ .dw PFA_DOVARIABLE
+PFA_ASSR:
+ .dw 182
+
+.endif
+.if WANT_WATCHDOG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCR:
+ .dw $ff05
+ .db "WDTCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCR
+XT_WDTCR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCR:
+ .dw 96
+
+.endif
+.if WANT_BOOT_LOAD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control Register
+VE_SPMCSR:
+ .dw $ff06
+ .db "SPMCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCSR
+XT_SPMCSR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCSR:
+ .dw 87
+
+.endif
+.if WANT_PORTH == 1
+; ( -- addr ) System Constant
+; R( -- )
+; PORT H Data Register
+VE_PORTH:
+ .dw $ff05
+ .db "PORTH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTH
+XT_PORTH:
+ .dw PFA_DOVARIABLE
+PFA_PORTH:
+ .dw 218
+; ( -- addr ) System Constant
+; R( -- )
+; PORT H Data Direction Register
+VE_DDRH:
+ .dw $ff04
+ .db "DDRH"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRH
+XT_DDRH:
+ .dw PFA_DOVARIABLE
+PFA_DDRH:
+ .dw 217
+; ( -- addr ) System Constant
+; R( -- )
+; PORT H Input Pins
+VE_PINH:
+ .dw $ff04
+ .db "PINH"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINH
+XT_PINH:
+ .dw PFA_DOVARIABLE
+PFA_PINH:
+ .dw 216
+
+.endif
+.if WANT_PORTJ == 1
+; ( -- addr ) System Constant
+; R( -- )
+; PORT J Data Register
+VE_PORTJ:
+ .dw $ff05
+ .db "PORTJ",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTJ
+XT_PORTJ:
+ .dw PFA_DOVARIABLE
+PFA_PORTJ:
+ .dw 221
+; ( -- addr ) System Constant
+; R( -- )
+; PORT J Data Direction Register
+VE_DDRJ:
+ .dw $ff04
+ .db "DDRJ"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRJ
+XT_DDRJ:
+ .dw PFA_DOVARIABLE
+PFA_DDRJ:
+ .dw 220
+; ( -- addr ) System Constant
+; R( -- )
+; PORT J Input Pins
+VE_PINJ:
+ .dw $ff04
+ .db "PINJ"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINJ
+XT_PINJ:
+ .dw PFA_DOVARIABLE
+PFA_PINJ:
+ .dw 219
+
+.endif
+.if WANT_LCD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 19
+VE_LCDDR19:
+ .dw $ff07
+ .db "LCDDR19",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR19
+XT_LCDDR19:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR19:
+ .dw 255
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 18
+VE_LCDDR18:
+ .dw $ff07
+ .db "LCDDR18",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR18
+XT_LCDDR18:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR18:
+ .dw 254
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 17
+VE_LCDDR17:
+ .dw $ff07
+ .db "LCDDR17",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR17
+XT_LCDDR17:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR17:
+ .dw 253
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 16
+VE_LCDDR16:
+ .dw $ff07
+ .db "LCDDR16",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR16
+XT_LCDDR16:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR16:
+ .dw 252
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 15
+VE_LCDDR15:
+ .dw $ff07
+ .db "LCDDR15",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR15
+XT_LCDDR15:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR15:
+ .dw 251
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 14
+VE_LCDDR14:
+ .dw $ff07
+ .db "LCDDR14",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR14
+XT_LCDDR14:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR14:
+ .dw 250
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 13
+VE_LCDDR13:
+ .dw $ff07
+ .db "LCDDR13",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR13
+XT_LCDDR13:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR13:
+ .dw 249
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 12
+VE_LCDDR12:
+ .dw $ff07
+ .db "LCDDR12",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR12
+XT_LCDDR12:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR12:
+ .dw 248
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 11
+VE_LCDDR11:
+ .dw $ff07
+ .db "LCDDR11",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR11
+XT_LCDDR11:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR11:
+ .dw 247
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 10
+VE_LCDDR10:
+ .dw $ff07
+ .db "LCDDR10",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR10
+XT_LCDDR10:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR10:
+ .dw 246
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 9
+VE_LCDDR9:
+ .dw $ff06
+ .db "LCDDR9"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR9
+XT_LCDDR9:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR9:
+ .dw 245
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 8
+VE_LCDDR8:
+ .dw $ff06
+ .db "LCDDR8"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR8
+XT_LCDDR8:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR8:
+ .dw 244
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 7
+VE_LCDDR7:
+ .dw $ff06
+ .db "LCDDR7"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR7
+XT_LCDDR7:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR7:
+ .dw 243
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 6
+VE_LCDDR6:
+ .dw $ff06
+ .db "LCDDR6"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR6
+XT_LCDDR6:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR6:
+ .dw 242
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 5
+VE_LCDDR5:
+ .dw $ff06
+ .db "LCDDR5"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR5
+XT_LCDDR5:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR5:
+ .dw 241
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 4
+VE_LCDDR4:
+ .dw $ff06
+ .db "LCDDR4"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR4
+XT_LCDDR4:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR4:
+ .dw 240
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 3
+VE_LCDDR3:
+ .dw $ff06
+ .db "LCDDR3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR3
+XT_LCDDR3:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR3:
+ .dw 239
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 2
+VE_LCDDR2:
+ .dw $ff06
+ .db "LCDDR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR2
+XT_LCDDR2:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR2:
+ .dw 238
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 1
+VE_LCDDR1:
+ .dw $ff06
+ .db "LCDDR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR1
+XT_LCDDR1:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR1:
+ .dw 237
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 0
+VE_LCDDR0:
+ .dw $ff06
+ .db "LCDDR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR0
+XT_LCDDR0:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR0:
+ .dw 236
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Contrast Control Register
+VE_LCDCCR:
+ .dw $ff06
+ .db "LCDCCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDCCR
+XT_LCDCCR:
+ .dw PFA_DOVARIABLE
+PFA_LCDCCR:
+ .dw 231
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Frame Rate Register
+VE_LCDFRR:
+ .dw $ff06
+ .db "LCDFRR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDFRR
+XT_LCDFRR:
+ .dw PFA_DOVARIABLE
+PFA_LCDFRR:
+ .dw 230
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Control and Status Register B
+VE_LCDCRB:
+ .dw $ff06
+ .db "LCDCRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDCRB
+XT_LCDCRB:
+ .dw PFA_DOVARIABLE
+PFA_LCDCRB:
+ .dw 229
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Control and Status Register A
+VE_LCDCRA:
+ .dw $ff06
+ .db "LCDCRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDCRA
+XT_LCDCRA:
+ .dw PFA_DOVARIABLE
+PFA_LCDCRA:
+ .dw 228
+
+.endif
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register A
+VE_EICRA:
+ .dw $ff05
+ .db "EICRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRA
+XT_EICRA:
+ .dw PFA_DOVARIABLE
+PFA_EICRA:
+ .dw 105
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Mask Register
+VE_EIMSK:
+ .dw $ff05
+ .db "EIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIMSK
+XT_EIMSK:
+ .dw PFA_DOVARIABLE
+PFA_EIMSK:
+ .dw 61
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Flag Register
+VE_EIFR:
+ .dw $ff04
+ .db "EIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIFR
+XT_EIFR:
+ .dw PFA_DOVARIABLE
+PFA_EIFR:
+ .dw 60
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 3
+VE_PCMSK3:
+ .dw $ff06
+ .db "PCMSK3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK3
+XT_PCMSK3:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK3:
+ .dw 115
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 2
+VE_PCMSK2:
+ .dw $ff06
+ .db "PCMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK2
+XT_PCMSK2:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK2:
+ .dw 109
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 1
+VE_PCMSK1:
+ .dw $ff06
+ .db "PCMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK1
+XT_PCMSK1:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK1:
+ .dw 108
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 0
+VE_PCMSK0:
+ .dw $ff06
+ .db "PCMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK0
+XT_PCMSK0:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK0:
+ .dw 107
+
+.endif
diff --git a/amforth-6.5/avr8/devices/atmega6490a/device.py b/amforth-6.5/avr8/devices/atmega6490a/device.py
new file mode 100644
index 0000000..de70d9f
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega6490a/device.py
@@ -0,0 +1,370 @@
+# Generated Automatically
+
+# Partname ATmega6490A
+
+MCUREGS = {
+# Interrupt Vectors
+ 'INT0Addr' : '#2', # External Interrupt Request 0
+ 'PCINT0Addr' : '#4', # Pin Change Interrupt Request 0
+ 'PCINT1Addr' : '#6', # Pin Change Interrupt Request 1
+ 'TIMER2_COMPAddr' : '#8', # Timer/Counter2 Compare Match
+ 'TIMER2_OVFAddr' : '#10', # Timer/Counter2 Overflow
+ 'TIMER1_CAPTAddr' : '#12', # Timer/Counter1 Capture Event
+ 'TIMER1_COMPAAddr' : '#14', # Timer/Counter1 Compare Match A
+ 'TIMER1_COMPBAddr' : '#16', # Timer/Counter Compare Match B
+ 'TIMER1_OVFAddr' : '#18', # Timer/Counter1 Overflow
+ 'TIMER0_COMPAddr' : '#20', # Timer/Counter0 Compare Match
+ 'TIMER0_OVFAddr' : '#22', # Timer/Counter0 Overflow
+ 'SPI_STCAddr' : '#24', # SPI Serial Transfer Complete
+ 'USART_RXAddr' : '#26', # USART, Rx Complete
+ 'USART_UDREAddr' : '#28', # USART Data register Empty
+ 'USART0_TXAddr' : '#30', # USART0, Tx Complete
+ 'USI_STARTAddr' : '#32', # USI Start Condition
+ 'USI_OVERFLOWAddr' : '#34', # USI Overflow
+ 'ANALOG_COMPAddr' : '#36', # Analog Comparator
+ 'ADCAddr' : '#38', # ADC Conversion Complete
+ 'EE_READYAddr' : '#40', # EEPROM Ready
+ 'SPM_READYAddr' : '#42', # Store Program Memory Read
+ 'LCDAddr' : '#44', # LCD Start of Frame
+ 'PCINT2Addr' : '#46', # Pin Change Interrupt Request 2
+ 'PCINT3Addr' : '#48', # Pin Change Interrupt Request 3
+
+# Module AD_CONVERTER
+ 'ADMUX' : '$7c', # The ADC multiplexer Selection
+ 'ADMUX_REFS': '$c0', # Reference Selection Bits
+ 'ADMUX_ADLAR': '$20', # Left Adjust Result
+ 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
+ 'ADCSRA' : '$7a', # The ADC Control and Status reg
+ 'ADCSRA_ADEN': '$80', # ADC Enable
+ 'ADCSRA_ADSC': '$40', # ADC Start Conversion
+ 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
+ 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
+ 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
+ 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
+ 'ADC' : '$78', # ADC Data Register Bytes
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Sources
+ 'DIDR0' : '$7e', # Digital Input Disable Register
+ 'DIDR0_ADC7D': '$80', # ADC7 Digital input Disable
+ 'DIDR0_ADC6D': '$40', # ADC6 Digital input Disable
+ 'DIDR0_ADC5D': '$20', # ADC5 Digital input Disable
+ 'DIDR0_ADC4D': '$10', # ADC4 Digital input Disable
+ 'DIDR0_ADC3D': '$8', # ADC3 Digital input Disable
+ 'DIDR0_ADC2D': '$4', # ADC2 Digital input Disable
+ 'DIDR0_ADC1D': '$2', # ADC1 Digital input Disable
+ 'DIDR0_ADC0D': '$1', # ADC0 Digital input Disable
+
+# Module ANALOG_COMPARATOR
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
+ 'ACSR' : '$50', # Analog Comparator Control And
+ 'ACSR_ACD': '$80', # Analog Comparator Disable
+ 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
+ 'ACSR_ACO': '$20', # Analog Compare Output
+ 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
+ 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
+ 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
+ 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
+ 'DIDR1' : '$7f', # Digital Input Disable Register
+ 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
+ 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
+
+# Module SPI
+ 'SPCR' : '$4c', # SPI Control Register
+ 'SPCR_SPIE': '$80', # SPI Interrupt Enable
+ 'SPCR_SPE': '$40', # SPI Enable
+ 'SPCR_DORD': '$20', # Data Order
+ 'SPCR_MSTR': '$10', # Master/Slave Select
+ 'SPCR_CPOL': '$8', # Clock polarity
+ 'SPCR_CPHA': '$4', # Clock Phase
+ 'SPCR_SPR': '$3', # SPI Clock Rate Selects
+ 'SPSR' : '$4d', # SPI Status Register
+ 'SPSR_SPIF': '$80', # SPI Interrupt Flag
+ 'SPSR_WCOL': '$40', # Write Collision Flag
+ 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
+ 'SPDR' : '$4e', # SPI Data Register
+
+# Module USI
+ 'USIDR' : '$ba', # USI Data Register
+ 'USISR' : '$b9', # USI Status Register
+ 'USISR_USISIF': '$80', # Start Condition Interrupt Flag
+ 'USISR_USIOIF': '$40', # Counter Overflow Interrupt Fla
+ 'USISR_USIPF': '$20', # Stop Condition Flag
+ 'USISR_USIDC': '$10', # Data Output Collision
+ 'USISR_USICNT': '$f', # USI Counter Value Bits
+ 'USICR' : '$b8', # USI Control Register
+ 'USICR_USISIE': '$80', # Start Condition Interrupt Enab
+ 'USICR_USIOIE': '$40', # Counter Overflow Interrupt Ena
+ 'USICR_USIWM': '$30', # USI Wire Mode Bits
+ 'USICR_USICS': '$c', # USI Clock Source Select Bits
+ 'USICR_USICLK': '$2', # Clock Strobe
+ 'USICR_USITC': '$1', # Toggle Clock Port Pin
+
+# Module USART0
+ 'UDR0' : '$c6', # USART I/O Data Register
+ 'UCSR0A' : '$c0', # USART Control and Status Regis
+ 'UCSR0A_RXC0': '$80', # USART Receive Complete
+ 'UCSR0A_TXC0': '$40', # USART Transmit Complete
+ 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
+ 'UCSR0A_FE0': '$10', # Framing Error
+ 'UCSR0A_DOR0': '$8', # Data OverRun
+ 'UCSR0A_UPE0': '$4', # USART Parity Error
+ 'UCSR0A_U2X0': '$2', # Double the USART Transmission
+ 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
+ 'UCSR0B' : '$c1', # USART Control and Status Regis
+ 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
+ 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
+ 'UCSR0B_UDRIE0': '$20', # USART Data Register Empty Inte
+ 'UCSR0B_RXEN0': '$10', # Receiver Enable
+ 'UCSR0B_TXEN0': '$8', # Transmitter Enable
+ 'UCSR0B_UCSZ02': '$4', # Character Size
+ 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
+ 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
+ 'UCSR0C' : '$c2', # USART Control and Status Regis
+ 'UCSR0C_UMSEL0': '$40', # USART Mode Select
+ 'UCSR0C_UPM0': '$30', # Parity Mode Bits
+ 'UCSR0C_USBS0': '$8', # Stop Bit Select
+ 'UCSR0C_UCSZ0': '$6', # Character Size
+ 'UCSR0C_UCPOL0': '$1', # Clock Polarity
+ 'UBRR0' : '$c4', # USART Baud Rate Register Byte
+
+# Module CPU
+ 'SREG' : '$5f', # Status Register
+ 'SREG_I': '$80', # Global Interrupt Enable
+ 'SREG_T': '$40', # Bit Copy Storage
+ 'SREG_H': '$20', # Half Carry Flag
+ 'SREG_S': '$10', # Sign Bit
+ 'SREG_V': '$8', # Two's Complement Overflow Flag
+ 'SREG_N': '$4', # Negative Flag
+ 'SREG_Z': '$2', # Zero Flag
+ 'SREG_C': '$1', # Carry Flag
+ 'SP' : '$5d', # Stack Pointer
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_PUD': '$10', # Pull-up disable
+ 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
+ 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+ 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
+ 'MCUSR_BORF': '$4', # Brown-out Reset Flag
+ 'MCUSR_EXTRF': '$2', # External Reset Flag
+ 'MCUSR_PORF': '$1', # Power-on reset flag
+ 'OSCCAL' : '$66', # Oscillator Calibration Value
+ 'CLKPR' : '$61', # Clock Prescale Register
+ 'CLKPR_CLKPCE': '$80', # Clock Prescaler Change Enable
+ 'CLKPR_CLKPS': '$f', # Clock Prescaler Select Bits
+ 'PRR' : '$64', # Power Reduction Register
+ 'PRR_PRLCD': '$10', # Power Reduction LCD
+ 'PRR_PRTIM1': '$8', # Power Reduction Timer/Counter1
+ 'PRR_PRSPI': '$4', # Power Reduction Serial Periphe
+ 'PRR_PRUSART0': '$2', # Power Reduction USART
+ 'PRR_PRADC': '$1', # Power Reduction ADC
+ 'SMCR' : '$53', # Sleep Mode Control Register
+ 'SMCR_SM': '$e', # Sleep Mode Select bits
+ 'SMCR_SE': '$1', # Sleep Enable
+ 'GPIOR2' : '$4b', # General Purpose IO Register 2
+ 'GPIOR1' : '$4a', # General Purpose IO Register 1
+ 'GPIOR0' : '$3e', # General Purpose IO Register 0
+
+# Module JTAG
+ 'OCDR' : '$51', # On-Chip Debug Related Register
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_JTD': '$80', # JTAG Interface Disable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+
+# Module EEPROM
+ 'EEAR' : '$41', # EEPROM Read/Write Access Byte
+ 'EEDR' : '$40', # EEPROM Data Register
+ 'EECR' : '$3f', # EEPROM Control Register
+ 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
+ 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
+ 'EECR_EEWE': '$2', # EEPROM Write Enable
+ 'EECR_EERE': '$1', # EEPROM Read Enable
+
+# Module PORTA
+ 'PORTA' : '$22', # Port A Data Register
+ 'DDRA' : '$21', # Port A Data Direction Register
+ 'PINA' : '$20', # Port A Input Pins
+
+# Module PORTB
+ 'PORTB' : '$25', # Port B Data Register
+ 'DDRB' : '$24', # Port B Data Direction Register
+ 'PINB' : '$23', # Port B Input Pins
+
+# Module PORTC
+ 'PORTC' : '$28', # Port C Data Register
+ 'DDRC' : '$27', # Port C Data Direction Register
+ 'PINC' : '$26', # Port C Input Pins
+
+# Module PORTD
+ 'PORTD' : '$2b', # Port D Data Register
+ 'DDRD' : '$2a', # Port D Data Direction Register
+ 'PIND' : '$29', # Port D Input Pins
+
+# Module PORTE
+ 'PORTE' : '$2e', # Data Register, Port E
+ 'DDRE' : '$2d', # Data Direction Register, Port
+ 'PINE' : '$2c', # Input Pins, Port E
+
+# Module PORTF
+ 'PORTF' : '$31', # Data Register, Port F
+ 'DDRF' : '$30', # Data Direction Register, Port
+ 'PINF' : '$2f', # Input Pins, Port F
+
+# Module PORTG
+ 'PORTG' : '$34', # Port G Data Register
+ 'DDRG' : '$33', # Port G Data Direction Register
+ 'PING' : '$32', # Port G Input Pins
+
+# Module TIMER_COUNTER_0
+ 'TCCR0A' : '$44', # Timer/Counter0 Control Registe
+ 'TCCR0A_FOC0A': '$80', # Force Output Compare
+ 'TCCR0A_WGM00': '$40', # Waveform Generation Mode 0
+ 'TCCR0A_COM0A': '$30', # Compare Match Output Modes
+ 'TCCR0A_WGM01': '$8', # Waveform Generation Mode 1
+ 'TCCR0A_CS0': '$7', # Clock Selects
+ 'TCNT0' : '$46', # Timer/Counter0
+ 'OCR0A' : '$47', # Timer/Counter0 Output Compare
+ 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
+ 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
+ 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
+ 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
+ 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
+ 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Control Register
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSR310': '$1', # Prescaler Reset Timer/Counter1
+
+# Module TIMER_COUNTER_1
+ 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
+ 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
+ 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
+ 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
+ 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
+ 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
+ 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
+ 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
+ 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
+ 'TCCR1C' : '$82', # Timer/Counter 1 Control Regist
+ 'TCCR1C_FOC1A': '$80', # Force Output Compare 1A
+ 'TCCR1C_FOC1B': '$40', # Force Output Compare 1B
+ 'TCNT1' : '$84', # Timer/Counter1 Bytes
+ 'OCR1A' : '$88', # Timer/Counter1 Output Compare
+ 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
+ 'ICR1' : '$86', # Timer/Counter1 Input Capture R
+ 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
+ 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
+ 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
+ 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
+ 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
+ 'TIFR1' : '$36', # Timer/Counter1 Interrupt Flag
+ 'TIFR1_ICF1': '$20', # Input Capture Flag 1
+ 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
+ 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
+ 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
+
+# Module TIMER_COUNTER_2
+ 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
+ 'TCCR2A_FOC2A': '$80', # Force Output Compare A
+ 'TCCR2A_WGM20': '$40', # Waveform Generation Mode
+ 'TCCR2A_COM2A': '$30', # Compare Output Mode bits
+ 'TCCR2A_WGM21': '$8', # Waveform Generation Mode
+ 'TCCR2A_CS2': '$7', # Clock Select bits
+ 'TCNT2' : '$b2', # Timer/Counter2
+ 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
+ 'TIMSK2' : '$70', # Timer/Counter2 Interrupt Mask
+ 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
+ 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
+ 'TIFR2' : '$37', # Timer/Counter2 Interrupt Flag
+ 'TIFR2_OCF2A': '$2', # Timer/Counter2 Output Compare
+ 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_PSR2': '$2', # Prescaler Reset Timer/Counter2
+ 'ASSR' : '$b6', # Asynchronous Status Register
+ 'ASSR_EXCLK': '$10', # Enable External Clock Interrup
+ 'ASSR_AS2': '$8', # AS2: Asynchronous Timer/Counte
+ 'ASSR_TCN2UB': '$4', # TCN2UB: Timer/Counter2 Update
+ 'ASSR_OCR2UB': '$2', # Output Compare Register2 Updat
+ 'ASSR_TCR2UB': '$1', # TCR2UB: Timer/Counter Control
+
+# Module WATCHDOG
+ 'WDTCR' : '$60', # Watchdog Timer Control Registe
+ 'WDTCR_WDCE': '$10', # Watchdog Change Enable
+ 'WDTCR_WDE': '$8', # Watch Dog Enable
+ 'WDTCR_WDP': '$7', # Watch Dog Timer Prescaler bits
+
+# Module BOOT_LOAD
+ 'SPMCSR' : '$57', # Store Program Memory Control R
+ 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
+ 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
+ 'SPMCSR_RWWSRE': '$10', # Read While Write section read
+ 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
+ 'SPMCSR_PGWRT': '$4', # Page Write
+ 'SPMCSR_PGERS': '$2', # Page Erase
+ 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
+
+# Module PORTH
+ 'PORTH' : '$da', # PORT H Data Register
+ 'DDRH' : '$d9', # PORT H Data Direction Register
+ 'PINH' : '$d8', # PORT H Input Pins
+
+# Module PORTJ
+ 'PORTJ' : '$dd', # PORT J Data Register
+ 'DDRJ' : '$dc', # PORT J Data Direction Register
+ 'PINJ' : '$db', # PORT J Input Pins
+
+# Module LCD
+ 'LCDDR19' : '$ff', # LCD Data Register 19
+ 'LCDDR18' : '$fe', # LCD Data Register 18
+ 'LCDDR17' : '$fd', # LCD Data Register 17
+ 'LCDDR16' : '$fc', # LCD Data Register 16
+ 'LCDDR15' : '$fb', # LCD Data Register 15
+ 'LCDDR14' : '$fa', # LCD Data Register 14
+ 'LCDDR13' : '$f9', # LCD Data Register 13
+ 'LCDDR12' : '$f8', # LCD Data Register 12
+ 'LCDDR11' : '$f7', # LCD Data Register 11
+ 'LCDDR10' : '$f6', # LCD Data Register 10
+ 'LCDDR9' : '$f5', # LCD Data Register 9
+ 'LCDDR8' : '$f4', # LCD Data Register 8
+ 'LCDDR7' : '$f3', # LCD Data Register 7
+ 'LCDDR6' : '$f2', # LCD Data Register 6
+ 'LCDDR5' : '$f1', # LCD Data Register 5
+ 'LCDDR4' : '$f0', # LCD Data Register 4
+ 'LCDDR3' : '$ef', # LCD Data Register 3
+ 'LCDDR2' : '$ee', # LCD Data Register 2
+ 'LCDDR1' : '$ed', # LCD Data Register 1
+ 'LCDDR0' : '$ec', # LCD Data Register 0
+ 'LCDCCR' : '$e7', # LCD Contrast Control Register
+ 'LCDFRR' : '$e6', # LCD Frame Rate Register
+ 'LCDFRR_LCDPS': '$70', # LCD Prescaler Selects
+ 'LCDFRR_LCDCD': '$7', # LCD Clock Dividers
+ 'LCDCRB' : '$e5', # LCD Control and Status Registe
+ 'LCDCRB_LCDCS': '$80', # LCD CLock Select
+ 'LCDCRB_LCD2B': '$40', # LCD 1/2 Bias Select
+ 'LCDCRB_LCDMUX': '$30', # LCD Mux Selects
+ 'LCDCRB_LCDPM': '$f', # LCD Port Masks
+ 'LCDCRA' : '$e4', # LCD Control and Status Registe
+ 'LCDCRA_LCDEN': '$80', # LCD Enable
+ 'LCDCRA_LCDAB': '$40', # LCD A or B waveform
+ 'LCDCRA_LCDIF': '$10', # LCD Interrupt Flag
+ 'LCDCRA_LCDIE': '$8', # LCD Interrupt Enable
+ 'LCDCRA_LCDBL': '$1', # LCD Blanking
+
+# Module EXTERNAL_INTERRUPT
+ 'EICRA' : '$69', # External Interrupt Control Reg
+ 'EICRA_ISC01': '$2', # External Interrupt Sense Contr
+ 'EICRA_ISC00': '$1', # External Interrupt Sense Contr
+ 'EIMSK' : '$3d', # External Interrupt Mask Regist
+ 'EIMSK_PCIE': '$f0', # Pin Change Interrupt Enables
+ 'EIMSK_INT0': '$1', # External Interrupt Request 0 E
+ 'EIFR' : '$3c', # External Interrupt Flag Regist
+ 'EIFR_PCIF': '$f0', # Pin Change Interrupt Flags
+ 'EIFR_INTF0': '$1', # External Interrupt Flag 0
+ 'PCMSK3' : '$73', # Pin Change Mask Register 3
+ 'PCMSK2' : '$6d', # Pin Change Mask Register 2
+ 'PCMSK1' : '$6c', # Pin Change Mask Register 1
+ 'PCMSK0' : '$6b', # Pin Change Mask Register 0
+
+ '__amforth_dummy':'0'
+}
diff --git a/amforth-6.5/avr8/devices/atmega6490a/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega6490a/words/no-jtag.asm
new file mode 100644
index 0000000..352a4bb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega6490a/words/no-jtag.asm
@@ -0,0 +1,14 @@
+; ( -- )
+; ( -- )
+; MCU
+; disable jtag at runtime
+VE_NOJTAG:
+ .dw $FF05
+ .db "-jtag",0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOJTAG
+XT_NOJTAG:
+ .dw PFA_NOJTAG
+PFA_NOJTAG:
+
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega6490a/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega6490a/words/no-wdt.asm
new file mode 100644
index 0000000..4a12261
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega6490a/words/no-wdt.asm
@@ -0,0 +1,22 @@
+; ( -- )
+; MCU
+; disable watch dog timer at runtime
+VE_NOWDT:
+ .dw $ff04
+ .db "-wdt"
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOWDT
+XT_NOWDT:
+ .dw PFA_NOWDT
+PFA_NOWDT:
+
+; Reset WDT
+ wdr
+; Write logical one to WDTOE and WDE
+ in_ temp1, WDTCR
+ ori temp1, (1<<WDTOE)|(1<<WDE)
+ out WDTCR, temp1
+; Turn off WDT
+ ldi temp1, (0<<WDE)
+ out_ WDTCR, temp1
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega6490a/words/sleep.asm b/amforth-6.5/avr8/devices/atmega6490a/words/sleep.asm
new file mode 100644
index 0000000..256249c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega6490a/words/sleep.asm
@@ -0,0 +1,19 @@
+; ( mode -- )
+; MCU
+; put the controller into the specified sleep mode
+VE_SLEEP:
+ .dw $ff05
+ .db "sleep", 0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_SLEEP
+XT_SLEEP:
+ .dw PFA_SLEEP
+PFA_SLEEP:
+ andi tosl, 7 ; leave only legal mode bits
+ lsl tosl ; move to correct location (bits 3-1)
+ ori tosl, 1 ; set the SE bit
+ out_ SMCR, tosl ; set the sleep config
+ sleep ; nighty-night
+ out_ SMCR, zerol ; 0 protects against accidental sleeps
+ loadtos ; pop argument from stack
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega6490p/atmega6490p.frt b/amforth-6.5/avr8/devices/atmega6490p/atmega6490p.frt
new file mode 100644
index 0000000..948580b
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega6490p/atmega6490p.frt
@@ -0,0 +1,334 @@
+\ Partname: ATmega6490P
+\ generated automatically
+
+\ AD_CONVERTER
+&124 constant ADMUX \ The ADC multiplexer Selection Register
+ $C0 constant ADMUX_REFS \ Reference Selection Bits
+ $20 constant ADMUX_ADLAR \ Left Adjust Result
+ $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
+&122 constant ADCSRA \ The ADC Control and Status register
+ $80 constant ADCSRA_ADEN \ ADC Enable
+ $40 constant ADCSRA_ADSC \ ADC Start Conversion
+ $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
+ $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
+ $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
+ $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
+&120 constant ADC \ ADC Data Register Bytes
+&123 constant ADCSRB \ ADC Control and Status Register B
+ $07 constant ADCSRB_ADTS \ ADC Auto Trigger Sources
+&126 constant DIDR0 \ Digital Input Disable Register 0
+ $80 constant DIDR0_ADC7D \ ADC7 Digital input Disable
+ $40 constant DIDR0_ADC6D \ ADC6 Digital input Disable
+ $20 constant DIDR0_ADC5D \ ADC5 Digital input Disable
+ $10 constant DIDR0_ADC4D \ ADC4 Digital input Disable
+ $08 constant DIDR0_ADC3D \ ADC3 Digital input Disable
+ $04 constant DIDR0_ADC2D \ ADC2 Digital input Disable
+ $02 constant DIDR0_ADC1D \ ADC1 Digital input Disable
+ $01 constant DIDR0_ADC0D \ ADC0 Digital input Disable
+\ ANALOG_COMPARATOR
+&80 constant ACSR \ Analog Comparator Control And Status Register
+ $80 constant ACSR_ACD \ Analog Comparator Disable
+ $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
+ $20 constant ACSR_ACO \ Analog Compare Output
+ $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
+ $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
+ $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
+ $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
+&127 constant DIDR1 \ Digital Input Disable Register 1
+ $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
+ $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
+\ SPI
+&76 constant SPCR \ SPI Control Register
+ $80 constant SPCR_SPIE \ SPI Interrupt Enable
+ $40 constant SPCR_SPE \ SPI Enable
+ $20 constant SPCR_DORD \ Data Order
+ $10 constant SPCR_MSTR \ Master/Slave Select
+ $08 constant SPCR_CPOL \ Clock polarity
+ $04 constant SPCR_CPHA \ Clock Phase
+ $03 constant SPCR_SPR \ SPI Clock Rate Selects
+&77 constant SPSR \ SPI Status Register
+ $80 constant SPSR_SPIF \ SPI Interrupt Flag
+ $40 constant SPSR_WCOL \ Write Collision Flag
+ $01 constant SPSR_SPI2X \ Double SPI Speed Bit
+&78 constant SPDR \ SPI Data Register
+\ USI
+&186 constant USIDR \ USI Data Register
+&185 constant USISR \ USI Status Register
+ $80 constant USISR_USISIF \ Start Condition Interrupt Flag
+ $40 constant USISR_USIOIF \ Counter Overflow Interrupt Flag
+ $20 constant USISR_USIPF \ Stop Condition Flag
+ $10 constant USISR_USIDC \ Data Output Collision
+ $0F constant USISR_USICNT \ USI Counter Value Bits
+&184 constant USICR \ USI Control Register
+ $80 constant USICR_USISIE \ Start Condition Interrupt Enable
+ $40 constant USICR_USIOIE \ Counter Overflow Interrupt Enable
+ $30 constant USICR_USIWM \ USI Wire Mode Bits
+ $0C constant USICR_USICS \ USI Clock Source Select Bits
+ $02 constant USICR_USICLK \ Clock Strobe
+ $01 constant USICR_USITC \ Toggle Clock Port Pin
+\ USART0
+&198 constant UDR0 \ USART I/O Data Register
+&192 constant UCSR0A \ USART Control and Status Register A
+ $80 constant UCSR0A_RXC0 \ USART Receive Complete
+ $40 constant UCSR0A_TXC0 \ USART Transmit Complete
+ $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
+ $10 constant UCSR0A_FE0 \ Framing Error
+ $08 constant UCSR0A_DOR0 \ Data OverRun
+ $04 constant UCSR0A_UPE0 \ USART Parity Error
+ $02 constant UCSR0A_U2X0 \ Double the USART Transmission Speed
+ $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
+&193 constant UCSR0B \ USART Control and Status Register B
+ $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
+ $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
+ $20 constant UCSR0B_UDRIE0 \ USART Data Register Empty Interrupt Enable
+ $10 constant UCSR0B_RXEN0 \ Receiver Enable
+ $08 constant UCSR0B_TXEN0 \ Transmitter Enable
+ $04 constant UCSR0B_UCSZ02 \ Character Size
+ $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
+ $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
+&194 constant UCSR0C \ USART Control and Status Register C
+ $40 constant UCSR0C_UMSEL0 \ USART Mode Select
+ $30 constant UCSR0C_UPM0 \ Parity Mode Bits
+ $08 constant UCSR0C_USBS0 \ Stop Bit Select
+ $06 constant UCSR0C_UCSZ0 \ Character Size
+ $01 constant UCSR0C_UCPOL0 \ Clock Polarity
+&196 constant UBRR0 \ USART Baud Rate Register Bytes
+\ CPU
+&95 constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ $08 constant SREG_V \ Two's Complement Overflow Flag
+ $04 constant SREG_N \ Negative Flag
+ $02 constant SREG_Z \ Zero Flag
+ $01 constant SREG_C \ Carry Flag
+&93 constant SP \ Stack Pointer
+&85 constant MCUCR \ MCU Control Register
+ $10 constant MCUCR_PUD \ Pull-up disable
+ $02 constant MCUCR_IVSEL \ Interrupt Vector Select
+ $01 constant MCUCR_IVCE \ Interrupt Vector Change Enable
+&84 constant MCUSR \ MCU Status Register
+ $10 constant MCUSR_JTRF \ JTAG Reset Flag
+ $08 constant MCUSR_WDRF \ Watchdog Reset Flag
+ $04 constant MCUSR_BORF \ Brown-out Reset Flag
+ $02 constant MCUSR_EXTRF \ External Reset Flag
+ $01 constant MCUSR_PORF \ Power-on reset flag
+&102 constant OSCCAL \ Oscillator Calibration Value
+&97 constant CLKPR \ Clock Prescale Register
+ $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable
+ $0F constant CLKPR_CLKPS \ Clock Prescaler Select Bits
+&100 constant PRR \ Power Reduction Register
+ $10 constant PRR_PRLCD \ Power Reduction LCD
+ $08 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
+ $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
+ $02 constant PRR_PRUSART0 \ Power Reduction USART
+ $01 constant PRR_PRADC \ Power Reduction ADC
+&83 constant SMCR \ Sleep Mode Control Register
+ $0E constant SMCR_SM \ Sleep Mode Select bits
+ $01 constant SMCR_SE \ Sleep Enable
+&75 constant GPIOR2 \ General Purpose IO Register 2
+&74 constant GPIOR1 \ General Purpose IO Register 1
+&62 constant GPIOR0 \ General Purpose IO Register 0
+\ JTAG
+&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
+\ EEPROM
+&65 constant EEAR \ EEPROM Read/Write Access Bytes
+&64 constant EEDR \ EEPROM Data Register
+&63 constant EECR \ EEPROM Control Register
+ $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
+ $04 constant EECR_EEMWE \ EEPROM Master Write Enable
+ $02 constant EECR_EEWE \ EEPROM Write Enable
+ $01 constant EECR_EERE \ EEPROM Read Enable
+\ PORTA
+&34 constant PORTA \ Port A Data Register
+&33 constant DDRA \ Port A Data Direction Register
+&32 constant PINA \ Port A Input Pins
+\ PORTB
+&37 constant PORTB \ Port B Data Register
+&36 constant DDRB \ Port B Data Direction Register
+&35 constant PINB \ Port B Input Pins
+\ PORTC
+&40 constant PORTC \ Port C Data Register
+&39 constant DDRC \ Port C Data Direction Register
+&38 constant PINC \ Port C Input Pins
+\ PORTD
+&43 constant PORTD \ Port D Data Register
+&42 constant DDRD \ Port D Data Direction Register
+&41 constant PIND \ Port D Input Pins
+\ PORTE
+&46 constant PORTE \ Data Register, Port E
+&45 constant DDRE \ Data Direction Register, Port E
+&44 constant PINE \ Input Pins, Port E
+\ PORTF
+&49 constant PORTF \ Data Register, Port F
+&48 constant DDRF \ Data Direction Register, Port F
+&47 constant PINF \ Input Pins, Port F
+\ PORTG
+&52 constant PORTG \ Port G Data Register
+&51 constant DDRG \ Port G Data Direction Register
+&50 constant PING \ Port G Input Pins
+\ TIMER_COUNTER_0
+&68 constant TCCR0A \ Timer/Counter0 Control Register
+ $80 constant TCCR0A_FOC0A \ Force Output Compare
+ $40 constant TCCR0A_WGM00 \ Waveform Generation Mode 0
+ $30 constant TCCR0A_COM0A \ Compare Match Output Modes
+ $08 constant TCCR0A_WGM01 \ Waveform Generation Mode 1
+ $07 constant TCCR0A_CS0 \ Clock Selects
+&70 constant TCNT0 \ Timer/Counter0
+&71 constant OCR0A \ Timer/Counter0 Output Compare Register
+&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
+ $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match Interrupt Enable
+ $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
+&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
+ $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0
+ $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
+&67 constant GTCCR \ General Timer/Control Register
+ $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
+ $01 constant GTCCR_PSR310 \ Prescaler Reset Timer/Counter1 and Timer/Counter0
+\ TIMER_COUNTER_1
+&128 constant TCCR1A \ Timer/Counter1 Control Register A
+ $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
+ $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
+ $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
+&129 constant TCCR1B \ Timer/Counter1 Control Register B
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
+ $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
+&130 constant TCCR1C \ Timer/Counter 1 Control Register C
+ $80 constant TCCR1C_FOC1A \ Force Output Compare 1A
+ $40 constant TCCR1C_FOC1B \ Force Output Compare 1B
+&132 constant TCNT1 \ Timer/Counter1 Bytes
+&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
+&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
+&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
+&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
+ $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
+ $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
+ $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
+ $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
+&54 constant TIFR1 \ Timer/Counter1 Interrupt Flag register
+ $20 constant TIFR1_ICF1 \ Input Capture Flag 1
+ $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
+ $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
+ $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
+\ TIMER_COUNTER_2
+&176 constant TCCR2A \ Timer/Counter2 Control Register
+ $80 constant TCCR2A_FOC2A \ Force Output Compare A
+ $40 constant TCCR2A_WGM20 \ Waveform Generation Mode
+ $30 constant TCCR2A_COM2A \ Compare Output Mode bits
+ $08 constant TCCR2A_WGM21 \ Waveform Generation Mode
+ $07 constant TCCR2A_CS2 \ Clock Select bits
+&178 constant TCNT2 \ Timer/Counter2
+&179 constant OCR2A \ Timer/Counter2 Output Compare Register
+&112 constant TIMSK2 \ Timer/Counter2 Interrupt Mask register
+ $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match Interrupt Enable
+ $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
+&55 constant TIFR2 \ Timer/Counter2 Interrupt Flag Register
+ $02 constant TIFR2_OCF2A \ Timer/Counter2 Output Compare Flag 2
+ $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
+&182 constant ASSR \ Asynchronous Status Register
+ $10 constant ASSR_EXCLK \ Enable External Clock Interrupt
+ $08 constant ASSR_AS2 \ AS2: Asynchronous Timer/Counter2
+ $04 constant ASSR_TCN2UB \ TCN2UB: Timer/Counter2 Update Busy
+ $02 constant ASSR_OCR2UB \ Output Compare Register2 Update Busy
+ $01 constant ASSR_TCR2UB \ TCR2UB: Timer/Counter Control Register2 Update Busy
+\ WATCHDOG
+&96 constant WDTCR \ Watchdog Timer Control Register
+ $10 constant WDTCR_WDCE \ Watchdog Change Enable
+ $08 constant WDTCR_WDE \ Watch Dog Enable
+ $07 constant WDTCR_WDP \ Watch Dog Timer Prescaler bits
+\ BOOT_LOAD
+&87 constant SPMCSR \ Store Program Memory Control Register
+ $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
+ $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
+ $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
+ $04 constant SPMCSR_PGWRT \ Page Write
+ $02 constant SPMCSR_PGERS \ Page Erase
+ $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
+\ PORTH
+&218 constant PORTH \ PORT H Data Register
+&217 constant DDRH \ PORT H Data Direction Register
+&216 constant PINH \ PORT H Input Pins
+\ PORTJ
+&221 constant PORTJ \ PORT J Data Register
+&220 constant DDRJ \ PORT J Data Direction Register
+&219 constant PINJ \ PORT J Input Pins
+\ LCD
+&255 constant LCDDR19 \ LCD Data Register 19
+&254 constant LCDDR18 \ LCD Data Register 18
+&253 constant LCDDR17 \ LCD Data Register 17
+&252 constant LCDDR16 \ LCD Data Register 16
+&251 constant LCDDR15 \ LCD Data Register 15
+&250 constant LCDDR14 \ LCD Data Register 14
+&249 constant LCDDR13 \ LCD Data Register 13
+&248 constant LCDDR12 \ LCD Data Register 12
+&247 constant LCDDR11 \ LCD Data Register 11
+&246 constant LCDDR10 \ LCD Data Register 10
+&245 constant LCDDR9 \ LCD Data Register 9
+&244 constant LCDDR8 \ LCD Data Register 8
+&243 constant LCDDR7 \ LCD Data Register 7
+&242 constant LCDDR6 \ LCD Data Register 6
+&241 constant LCDDR5 \ LCD Data Register 5
+&240 constant LCDDR4 \ LCD Data Register 4
+&239 constant LCDDR3 \ LCD Data Register 3
+&238 constant LCDDR2 \ LCD Data Register 2
+&237 constant LCDDR1 \ LCD Data Register 1
+&236 constant LCDDR0 \ LCD Data Register 0
+&231 constant LCDCCR \ LCD Contrast Control Register
+&230 constant LCDFRR \ LCD Frame Rate Register
+ $70 constant LCDFRR_LCDPS \ LCD Prescaler Selects
+ $07 constant LCDFRR_LCDCD \ LCD Clock Dividers
+&229 constant LCDCRB \ LCD Control and Status Register B
+ $80 constant LCDCRB_LCDCS \ LCD CLock Select
+ $40 constant LCDCRB_LCD2B \ LCD 1/2 Bias Select
+ $30 constant LCDCRB_LCDMUX \ LCD Mux Selects
+ $0F constant LCDCRB_LCDPM \ LCD Port Masks
+&228 constant LCDCRA \ LCD Control and Status Register A
+ $80 constant LCDCRA_LCDEN \ LCD Enable
+ $40 constant LCDCRA_LCDAB \ LCD A or B waveform
+ $10 constant LCDCRA_LCDIF \ LCD Interrupt Flag
+ $08 constant LCDCRA_LCDIE \ LCD Interrupt Enable
+ $01 constant LCDCRA_LCDBL \ LCD Blanking
+\ EXTERNAL_INTERRUPT
+&105 constant EICRA \ External Interrupt Control Register A
+ $02 constant EICRA_ISC01 \ External Interrupt Sense Control 0 Bit 1
+ $01 constant EICRA_ISC00 \ External Interrupt Sense Control 0 Bit 0
+&61 constant EIMSK \ External Interrupt Mask Register
+ $F0 constant EIMSK_PCIE \ Pin Change Interrupt Enables
+ $01 constant EIMSK_INT0 \ External Interrupt Request 0 Enable
+&60 constant EIFR \ External Interrupt Flag Register
+ $F0 constant EIFR_PCIF \ Pin Change Interrupt Flags
+ $01 constant EIFR_INTF0 \ External Interrupt Flag 0
+&115 constant PCMSK3 \ Pin Change Mask Register 3
+&109 constant PCMSK2 \ Pin Change Mask Register 2
+&108 constant PCMSK1 \ Pin Change Mask Register 1
+&107 constant PCMSK0 \ Pin Change Mask Register 0
+
+\ Interrupts
+&2 constant INT0Addr \ External Interrupt Request 0
+&4 constant PCINT0Addr \ Pin Change Interrupt Request 0
+&6 constant PCINT1Addr \ Pin Change Interrupt Request 1
+&8 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
+&10 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
+&12 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+&14 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
+&16 constant TIMER1_COMPBAddr \ Timer/Counter Compare Match B
+&18 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+&20 constant TIMER0_COMPAddr \ Timer/Counter0 Compare Match
+&22 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
+&24 constant SPI__STCAddr \ SPI Serial Transfer Complete
+&26 constant USART__RXAddr \ USART, Rx Complete
+&28 constant USART__UDREAddr \ USART Data register Empty
+&30 constant USART0__TXAddr \ USART0, Tx Complete
+&32 constant USI_STARTAddr \ USI Start Condition
+&34 constant USI_OVERFLOWAddr \ USI Overflow
+&36 constant ANALOG_COMPAddr \ Analog Comparator
+&38 constant ADCAddr \ ADC Conversion Complete
+&40 constant EE_READYAddr \ EEPROM Ready
+&42 constant SPM_READYAddr \ Store Program Memory Read
+&44 constant LCDAddr \ LCD Start of Frame
+&46 constant PCINT2Addr \ Pin Change Interrupt Request 2
+&48 constant PCINT3Addr \ Pin Change Interrupt Request 3
diff --git a/amforth-6.5/avr8/devices/atmega6490p/device.asm b/amforth-6.5/avr8/devices/atmega6490p/device.asm
new file mode 100644
index 0000000..3f5cb38
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega6490p/device.asm
@@ -0,0 +1,115 @@
+; Partname: ATmega6490P
+; generated automatically, do not edit
+
+.nolist
+ .include "m6490Pdef.inc"
+.list
+
+.equ ramstart = 256
+.equ CELLSIZE = 2
+.macro readflashcell
+ lsl zl
+ rol zh
+ lpm @0, Z+
+ lpm @1, Z+
+.endmacro
+.macro writeflashcell
+ lsl zl
+ rol zh
+.endmacro
+.set WANT_AD_CONVERTER = 0
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_SPI = 0
+.set WANT_USI = 0
+.set WANT_USART0 = 0
+.set WANT_CPU = 0
+.set WANT_JTAG = 0
+.set WANT_EEPROM = 0
+.set WANT_PORTA = 0
+.set WANT_PORTB = 0
+.set WANT_PORTC = 0
+.set WANT_PORTD = 0
+.set WANT_PORTE = 0
+.set WANT_PORTF = 0
+.set WANT_PORTG = 0
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_TIMER_COUNTER_2 = 0
+.set WANT_WATCHDOG = 0
+.set WANT_BOOT_LOAD = 0
+.set WANT_PORTH = 0
+.set WANT_PORTJ = 0
+.set WANT_LCD = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.equ intvecsize = 2 ; please verify; flash size: 65536 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.org 2
+ rcall isr ; External Interrupt Request 0
+.org 4
+ rcall isr ; Pin Change Interrupt Request 0
+.org 6
+ rcall isr ; Pin Change Interrupt Request 1
+.org 8
+ rcall isr ; Timer/Counter2 Compare Match
+.org 10
+ rcall isr ; Timer/Counter2 Overflow
+.org 12
+ rcall isr ; Timer/Counter1 Capture Event
+.org 14
+ rcall isr ; Timer/Counter1 Compare Match A
+.org 16
+ rcall isr ; Timer/Counter Compare Match B
+.org 18
+ rcall isr ; Timer/Counter1 Overflow
+.org 20
+ rcall isr ; Timer/Counter0 Compare Match
+.org 22
+ rcall isr ; Timer/Counter0 Overflow
+.org 24
+ rcall isr ; SPI Serial Transfer Complete
+.org 26
+ rcall isr ; USART, Rx Complete
+.org 28
+ rcall isr ; USART Data register Empty
+.org 30
+ rcall isr ; USART0, Tx Complete
+.org 32
+ rcall isr ; USI Start Condition
+.org 34
+ rcall isr ; USI Overflow
+.org 36
+ rcall isr ; Analog Comparator
+.org 38
+ rcall isr ; ADC Conversion Complete
+.org 40
+ rcall isr ; EEPROM Ready
+.org 42
+ rcall isr ; Store Program Memory Read
+.org 44
+ rcall isr ; LCD Start of Frame
+.org 46
+ rcall isr ; Pin Change Interrupt Request 2
+.org 48
+ rcall isr ; Pin Change Interrupt Request 3
+.equ INTVECTORS = 25
+.nooverlap
+
+; compatability layer (maybe empty)
+.equ EEPE = EEWE
+.equ EEMPE = EEMWE
+
+; controller data area, environment query mcu-info
+mcu_info:
+mcu_ramsize:
+ .dw 4096
+mcu_eepromsize:
+ .dw 2048
+mcu_maxdp:
+ .dw 57344
+mcu_numints:
+ .dw 25
+mcu_name:
+ .dw 11
+ .db "ATmega6490P",0
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega6490p/device.inc b/amforth-6.5/avr8/devices/atmega6490p/device.inc
new file mode 100644
index 0000000..9b78b98
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega6490p/device.inc
@@ -0,0 +1,1443 @@
+; Partname: ATmega6490P
+; generated automatically, no not edit
+
+.if WANT_AD_CONVERTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC multiplexer Selection Register
+VE_ADMUX:
+ .dw $ff05
+ .db "ADMUX",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADMUX
+XT_ADMUX:
+ .dw PFA_DOVARIABLE
+PFA_ADMUX:
+ .dw 124
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register
+VE_ADCSRA:
+ .dw $ff06
+ .db "ADCSRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRA
+XT_ADCSRA:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRA:
+ .dw 122
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register Bytes
+VE_ADC:
+ .dw $ff03
+ .db "ADC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADC
+XT_ADC:
+ .dw PFA_DOVARIABLE
+PFA_ADC:
+ .dw 120
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Control and Status Register B
+VE_ADCSRB:
+ .dw $ff06
+ .db "ADCSRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRB
+XT_ADCSRB:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRB:
+ .dw 123
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 0
+VE_DIDR0:
+ .dw $ff05
+ .db "DIDR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR0
+XT_DIDR0:
+ .dw PFA_DOVARIABLE
+PFA_DIDR0:
+ .dw 126
+
+.endif
+.if WANT_ANALOG_COMPARATOR == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Control And Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw 80
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 1
+VE_DIDR1:
+ .dw $ff05
+ .db "DIDR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR1
+XT_DIDR1:
+ .dw PFA_DOVARIABLE
+PFA_DIDR1:
+ .dw 127
+
+.endif
+.if WANT_SPI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR:
+ .dw $ff04
+ .db "SPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR
+XT_SPCR:
+ .dw PFA_DOVARIABLE
+PFA_SPCR:
+ .dw 76
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR:
+ .dw $ff04
+ .db "SPSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR
+XT_SPSR:
+ .dw PFA_DOVARIABLE
+PFA_SPSR:
+ .dw 77
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR:
+ .dw $ff04
+ .db "SPDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR
+XT_SPDR:
+ .dw PFA_DOVARIABLE
+PFA_SPDR:
+ .dw 78
+
+.endif
+.if WANT_USI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USI Data Register
+VE_USIDR:
+ .dw $ff05
+ .db "USIDR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USIDR
+XT_USIDR:
+ .dw PFA_DOVARIABLE
+PFA_USIDR:
+ .dw 186
+; ( -- addr ) System Constant
+; R( -- )
+; USI Status Register
+VE_USISR:
+ .dw $ff05
+ .db "USISR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USISR
+XT_USISR:
+ .dw PFA_DOVARIABLE
+PFA_USISR:
+ .dw 185
+; ( -- addr ) System Constant
+; R( -- )
+; USI Control Register
+VE_USICR:
+ .dw $ff05
+ .db "USICR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USICR
+XT_USICR:
+ .dw PFA_DOVARIABLE
+PFA_USICR:
+ .dw 184
+
+.endif
+.if WANT_USART0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR0:
+ .dw $ff04
+ .db "UDR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR0
+XT_UDR0:
+ .dw PFA_DOVARIABLE
+PFA_UDR0:
+ .dw 198
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR0A:
+ .dw $ff06
+ .db "UCSR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0A
+XT_UCSR0A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0A:
+ .dw 192
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR0B:
+ .dw $ff06
+ .db "UCSR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0B
+XT_UCSR0B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0B:
+ .dw 193
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR0C:
+ .dw $ff06
+ .db "UCSR0C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0C
+XT_UCSR0C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0C:
+ .dw 194
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Bytes
+VE_UBRR0:
+ .dw $ff05
+ .db "UBRR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR0
+XT_UBRR0:
+ .dw PFA_DOVARIABLE
+PFA_UBRR0:
+ .dw 196
+
+.endif
+.if WANT_CPU == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw 95
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer
+VE_SP:
+ .dw $ff02
+ .db "SP"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SP
+XT_SP:
+ .dw PFA_DOVARIABLE
+PFA_SP:
+ .dw 93
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw 85
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Status Register
+VE_MCUSR:
+ .dw $ff05
+ .db "MCUSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUSR
+XT_MCUSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUSR:
+ .dw 84
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Calibration Value
+VE_OSCCAL:
+ .dw $ff06
+ .db "OSCCAL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSCCAL
+XT_OSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_OSCCAL:
+ .dw 102
+; ( -- addr ) System Constant
+; R( -- )
+; Clock Prescale Register
+VE_CLKPR:
+ .dw $ff05
+ .db "CLKPR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKPR
+XT_CLKPR:
+ .dw PFA_DOVARIABLE
+PFA_CLKPR:
+ .dw 97
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register
+VE_PRR:
+ .dw $ff03
+ .db "PRR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR
+XT_PRR:
+ .dw PFA_DOVARIABLE
+PFA_PRR:
+ .dw 100
+; ( -- addr ) System Constant
+; R( -- )
+; Sleep Mode Control Register
+VE_SMCR:
+ .dw $ff04
+ .db "SMCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SMCR
+XT_SMCR:
+ .dw PFA_DOVARIABLE
+PFA_SMCR:
+ .dw 83
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 2
+VE_GPIOR2:
+ .dw $ff06
+ .db "GPIOR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR2
+XT_GPIOR2:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR2:
+ .dw 75
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 1
+VE_GPIOR1:
+ .dw $ff06
+ .db "GPIOR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR1
+XT_GPIOR1:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR1:
+ .dw 74
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 0
+VE_GPIOR0:
+ .dw $ff06
+ .db "GPIOR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR0
+XT_GPIOR0:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR0:
+ .dw 62
+
+.endif
+.if WANT_JTAG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; On-Chip Debug Related Register in I/O Memory
+VE_OCDR:
+ .dw $ff04
+ .db "OCDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCDR
+XT_OCDR:
+ .dw PFA_DOVARIABLE
+PFA_OCDR:
+ .dw 81
+
+.endif
+.if WANT_EEPROM == 1
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Read/Write Access Bytes
+VE_EEAR:
+ .dw $ff04
+ .db "EEAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEAR
+XT_EEAR:
+ .dw PFA_DOVARIABLE
+PFA_EEAR:
+ .dw 65
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw 64
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw 63
+
+.endif
+.if WANT_PORTA == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Register
+VE_PORTA:
+ .dw $ff05
+ .db "PORTA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTA
+XT_PORTA:
+ .dw PFA_DOVARIABLE
+PFA_PORTA:
+ .dw 34
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Direction Register
+VE_DDRA:
+ .dw $ff04
+ .db "DDRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRA
+XT_DDRA:
+ .dw PFA_DOVARIABLE
+PFA_DDRA:
+ .dw 33
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Input Pins
+VE_PINA:
+ .dw $ff04
+ .db "PINA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINA
+XT_PINA:
+ .dw PFA_DOVARIABLE
+PFA_PINA:
+ .dw 32
+
+.endif
+.if WANT_PORTB == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw 37
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw 36
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw 35
+
+.endif
+.if WANT_PORTC == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Register
+VE_PORTC:
+ .dw $ff05
+ .db "PORTC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTC
+XT_PORTC:
+ .dw PFA_DOVARIABLE
+PFA_PORTC:
+ .dw 40
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Direction Register
+VE_DDRC:
+ .dw $ff04
+ .db "DDRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRC
+XT_DDRC:
+ .dw PFA_DOVARIABLE
+PFA_DDRC:
+ .dw 39
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Input Pins
+VE_PINC:
+ .dw $ff04
+ .db "PINC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINC
+XT_PINC:
+ .dw PFA_DOVARIABLE
+PFA_PINC:
+ .dw 38
+
+.endif
+.if WANT_PORTD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw 43
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw 42
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw 41
+
+.endif
+.if WANT_PORTE == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port E
+VE_PORTE:
+ .dw $ff05
+ .db "PORTE",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTE
+XT_PORTE:
+ .dw PFA_DOVARIABLE
+PFA_PORTE:
+ .dw 46
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port E
+VE_DDRE:
+ .dw $ff04
+ .db "DDRE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRE
+XT_DDRE:
+ .dw PFA_DOVARIABLE
+PFA_DDRE:
+ .dw 45
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port E
+VE_PINE:
+ .dw $ff04
+ .db "PINE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINE
+XT_PINE:
+ .dw PFA_DOVARIABLE
+PFA_PINE:
+ .dw 44
+
+.endif
+.if WANT_PORTF == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port F
+VE_PORTF:
+ .dw $ff05
+ .db "PORTF",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTF
+XT_PORTF:
+ .dw PFA_DOVARIABLE
+PFA_PORTF:
+ .dw 49
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port F
+VE_DDRF:
+ .dw $ff04
+ .db "DDRF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRF
+XT_DDRF:
+ .dw PFA_DOVARIABLE
+PFA_DDRF:
+ .dw 48
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port F
+VE_PINF:
+ .dw $ff04
+ .db "PINF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINF
+XT_PINF:
+ .dw PFA_DOVARIABLE
+PFA_PINF:
+ .dw 47
+
+.endif
+.if WANT_PORTG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Data Register
+VE_PORTG:
+ .dw $ff05
+ .db "PORTG",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTG
+XT_PORTG:
+ .dw PFA_DOVARIABLE
+PFA_PORTG:
+ .dw 52
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Data Direction Register
+VE_DDRG:
+ .dw $ff04
+ .db "DDRG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRG
+XT_DDRG:
+ .dw PFA_DOVARIABLE
+PFA_DDRG:
+ .dw 51
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Input Pins
+VE_PING:
+ .dw $ff04
+ .db "PING"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PING
+XT_PING:
+ .dw PFA_DOVARIABLE
+PFA_PING:
+ .dw 50
+
+.endif
+.if WANT_TIMER_COUNTER_0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Control Register
+VE_TCCR0A:
+ .dw $ff06
+ .db "TCCR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0A
+XT_TCCR0A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0A:
+ .dw 68
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw 70
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0A:
+ .dw $ff05
+ .db "OCR0A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0A
+XT_OCR0A:
+ .dw PFA_DOVARIABLE
+PFA_OCR0A:
+ .dw 71
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Mask Register
+VE_TIMSK0:
+ .dw $ff06
+ .db "TIMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK0
+XT_TIMSK0:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK0:
+ .dw 110
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Flag register
+VE_TIFR0:
+ .dw $ff05
+ .db "TIFR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR0
+XT_TIFR0:
+ .dw PFA_DOVARIABLE
+PFA_TIFR0:
+ .dw 53
+; ( -- addr ) System Constant
+; R( -- )
+; General Timer/Control Register
+VE_GTCCR:
+ .dw $ff05
+ .db "GTCCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GTCCR
+XT_GTCCR:
+ .dw PFA_DOVARIABLE
+PFA_GTCCR:
+ .dw 67
+
+.endif
+.if WANT_TIMER_COUNTER_1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw 128
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw 129
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter 1 Control Register C
+VE_TCCR1C:
+ .dw $ff06
+ .db "TCCR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1C
+XT_TCCR1C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1C:
+ .dw 130
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Bytes
+VE_TCNT1:
+ .dw $ff05
+ .db "TCNT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1
+XT_TCNT1:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1:
+ .dw 132
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register A Bytes
+VE_OCR1A:
+ .dw $ff05
+ .db "OCR1A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1A
+XT_OCR1A:
+ .dw PFA_DOVARIABLE
+PFA_OCR1A:
+ .dw 136
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register B Bytes
+VE_OCR1B:
+ .dw $ff05
+ .db "OCR1B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1B
+XT_OCR1B:
+ .dw PFA_DOVARIABLE
+PFA_OCR1B:
+ .dw 138
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Bytes
+VE_ICR1:
+ .dw $ff04
+ .db "ICR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1
+XT_ICR1:
+ .dw PFA_DOVARIABLE
+PFA_ICR1:
+ .dw 134
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Mask Register
+VE_TIMSK1:
+ .dw $ff06
+ .db "TIMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK1
+XT_TIMSK1:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK1:
+ .dw 111
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Flag register
+VE_TIFR1:
+ .dw $ff05
+ .db "TIFR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR1
+XT_TIFR1:
+ .dw PFA_DOVARIABLE
+PFA_TIFR1:
+ .dw 54
+
+.endif
+.if WANT_TIMER_COUNTER_2 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register
+VE_TCCR2A:
+ .dw $ff06
+ .db "TCCR2A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2A
+XT_TCCR2A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2A:
+ .dw 176
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2
+VE_TCNT2:
+ .dw $ff05
+ .db "TCNT2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT2
+XT_TCNT2:
+ .dw PFA_DOVARIABLE
+PFA_TCNT2:
+ .dw 178
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register
+VE_OCR2A:
+ .dw $ff05
+ .db "OCR2A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2A
+XT_OCR2A:
+ .dw PFA_DOVARIABLE
+PFA_OCR2A:
+ .dw 179
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Interrupt Mask register
+VE_TIMSK2:
+ .dw $ff06
+ .db "TIMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK2
+XT_TIMSK2:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK2:
+ .dw 112
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Interrupt Flag Register
+VE_TIFR2:
+ .dw $ff05
+ .db "TIFR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR2
+XT_TIFR2:
+ .dw PFA_DOVARIABLE
+PFA_TIFR2:
+ .dw 55
+; ( -- addr ) System Constant
+; R( -- )
+; Asynchronous Status Register
+VE_ASSR:
+ .dw $ff04
+ .db "ASSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ASSR
+XT_ASSR:
+ .dw PFA_DOVARIABLE
+PFA_ASSR:
+ .dw 182
+
+.endif
+.if WANT_WATCHDOG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCR:
+ .dw $ff05
+ .db "WDTCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCR
+XT_WDTCR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCR:
+ .dw 96
+
+.endif
+.if WANT_BOOT_LOAD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control Register
+VE_SPMCSR:
+ .dw $ff06
+ .db "SPMCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCSR
+XT_SPMCSR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCSR:
+ .dw 87
+
+.endif
+.if WANT_PORTH == 1
+; ( -- addr ) System Constant
+; R( -- )
+; PORT H Data Register
+VE_PORTH:
+ .dw $ff05
+ .db "PORTH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTH
+XT_PORTH:
+ .dw PFA_DOVARIABLE
+PFA_PORTH:
+ .dw 218
+; ( -- addr ) System Constant
+; R( -- )
+; PORT H Data Direction Register
+VE_DDRH:
+ .dw $ff04
+ .db "DDRH"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRH
+XT_DDRH:
+ .dw PFA_DOVARIABLE
+PFA_DDRH:
+ .dw 217
+; ( -- addr ) System Constant
+; R( -- )
+; PORT H Input Pins
+VE_PINH:
+ .dw $ff04
+ .db "PINH"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINH
+XT_PINH:
+ .dw PFA_DOVARIABLE
+PFA_PINH:
+ .dw 216
+
+.endif
+.if WANT_PORTJ == 1
+; ( -- addr ) System Constant
+; R( -- )
+; PORT J Data Register
+VE_PORTJ:
+ .dw $ff05
+ .db "PORTJ",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTJ
+XT_PORTJ:
+ .dw PFA_DOVARIABLE
+PFA_PORTJ:
+ .dw 221
+; ( -- addr ) System Constant
+; R( -- )
+; PORT J Data Direction Register
+VE_DDRJ:
+ .dw $ff04
+ .db "DDRJ"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRJ
+XT_DDRJ:
+ .dw PFA_DOVARIABLE
+PFA_DDRJ:
+ .dw 220
+; ( -- addr ) System Constant
+; R( -- )
+; PORT J Input Pins
+VE_PINJ:
+ .dw $ff04
+ .db "PINJ"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINJ
+XT_PINJ:
+ .dw PFA_DOVARIABLE
+PFA_PINJ:
+ .dw 219
+
+.endif
+.if WANT_LCD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 19
+VE_LCDDR19:
+ .dw $ff07
+ .db "LCDDR19",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR19
+XT_LCDDR19:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR19:
+ .dw 255
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 18
+VE_LCDDR18:
+ .dw $ff07
+ .db "LCDDR18",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR18
+XT_LCDDR18:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR18:
+ .dw 254
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 17
+VE_LCDDR17:
+ .dw $ff07
+ .db "LCDDR17",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR17
+XT_LCDDR17:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR17:
+ .dw 253
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 16
+VE_LCDDR16:
+ .dw $ff07
+ .db "LCDDR16",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR16
+XT_LCDDR16:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR16:
+ .dw 252
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 15
+VE_LCDDR15:
+ .dw $ff07
+ .db "LCDDR15",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR15
+XT_LCDDR15:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR15:
+ .dw 251
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 14
+VE_LCDDR14:
+ .dw $ff07
+ .db "LCDDR14",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR14
+XT_LCDDR14:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR14:
+ .dw 250
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 13
+VE_LCDDR13:
+ .dw $ff07
+ .db "LCDDR13",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR13
+XT_LCDDR13:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR13:
+ .dw 249
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 12
+VE_LCDDR12:
+ .dw $ff07
+ .db "LCDDR12",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR12
+XT_LCDDR12:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR12:
+ .dw 248
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 11
+VE_LCDDR11:
+ .dw $ff07
+ .db "LCDDR11",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR11
+XT_LCDDR11:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR11:
+ .dw 247
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 10
+VE_LCDDR10:
+ .dw $ff07
+ .db "LCDDR10",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR10
+XT_LCDDR10:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR10:
+ .dw 246
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 9
+VE_LCDDR9:
+ .dw $ff06
+ .db "LCDDR9"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR9
+XT_LCDDR9:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR9:
+ .dw 245
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 8
+VE_LCDDR8:
+ .dw $ff06
+ .db "LCDDR8"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR8
+XT_LCDDR8:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR8:
+ .dw 244
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 7
+VE_LCDDR7:
+ .dw $ff06
+ .db "LCDDR7"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR7
+XT_LCDDR7:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR7:
+ .dw 243
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 6
+VE_LCDDR6:
+ .dw $ff06
+ .db "LCDDR6"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR6
+XT_LCDDR6:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR6:
+ .dw 242
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 5
+VE_LCDDR5:
+ .dw $ff06
+ .db "LCDDR5"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR5
+XT_LCDDR5:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR5:
+ .dw 241
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 4
+VE_LCDDR4:
+ .dw $ff06
+ .db "LCDDR4"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR4
+XT_LCDDR4:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR4:
+ .dw 240
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 3
+VE_LCDDR3:
+ .dw $ff06
+ .db "LCDDR3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR3
+XT_LCDDR3:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR3:
+ .dw 239
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 2
+VE_LCDDR2:
+ .dw $ff06
+ .db "LCDDR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR2
+XT_LCDDR2:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR2:
+ .dw 238
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 1
+VE_LCDDR1:
+ .dw $ff06
+ .db "LCDDR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR1
+XT_LCDDR1:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR1:
+ .dw 237
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 0
+VE_LCDDR0:
+ .dw $ff06
+ .db "LCDDR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR0
+XT_LCDDR0:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR0:
+ .dw 236
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Contrast Control Register
+VE_LCDCCR:
+ .dw $ff06
+ .db "LCDCCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDCCR
+XT_LCDCCR:
+ .dw PFA_DOVARIABLE
+PFA_LCDCCR:
+ .dw 231
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Frame Rate Register
+VE_LCDFRR:
+ .dw $ff06
+ .db "LCDFRR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDFRR
+XT_LCDFRR:
+ .dw PFA_DOVARIABLE
+PFA_LCDFRR:
+ .dw 230
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Control and Status Register B
+VE_LCDCRB:
+ .dw $ff06
+ .db "LCDCRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDCRB
+XT_LCDCRB:
+ .dw PFA_DOVARIABLE
+PFA_LCDCRB:
+ .dw 229
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Control and Status Register A
+VE_LCDCRA:
+ .dw $ff06
+ .db "LCDCRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDCRA
+XT_LCDCRA:
+ .dw PFA_DOVARIABLE
+PFA_LCDCRA:
+ .dw 228
+
+.endif
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register A
+VE_EICRA:
+ .dw $ff05
+ .db "EICRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRA
+XT_EICRA:
+ .dw PFA_DOVARIABLE
+PFA_EICRA:
+ .dw 105
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Mask Register
+VE_EIMSK:
+ .dw $ff05
+ .db "EIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIMSK
+XT_EIMSK:
+ .dw PFA_DOVARIABLE
+PFA_EIMSK:
+ .dw 61
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Flag Register
+VE_EIFR:
+ .dw $ff04
+ .db "EIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIFR
+XT_EIFR:
+ .dw PFA_DOVARIABLE
+PFA_EIFR:
+ .dw 60
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 3
+VE_PCMSK3:
+ .dw $ff06
+ .db "PCMSK3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK3
+XT_PCMSK3:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK3:
+ .dw 115
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 2
+VE_PCMSK2:
+ .dw $ff06
+ .db "PCMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK2
+XT_PCMSK2:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK2:
+ .dw 109
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 1
+VE_PCMSK1:
+ .dw $ff06
+ .db "PCMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK1
+XT_PCMSK1:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK1:
+ .dw 108
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 0
+VE_PCMSK0:
+ .dw $ff06
+ .db "PCMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK0
+XT_PCMSK0:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK0:
+ .dw 107
+
+.endif
diff --git a/amforth-6.5/avr8/devices/atmega6490p/device.py b/amforth-6.5/avr8/devices/atmega6490p/device.py
new file mode 100644
index 0000000..8adff72
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega6490p/device.py
@@ -0,0 +1,370 @@
+# Generated Automatically
+
+# Partname ATmega6490P
+
+MCUREGS = {
+# Interrupt Vectors
+ 'INT0Addr' : '#2', # External Interrupt Request 0
+ 'PCINT0Addr' : '#4', # Pin Change Interrupt Request 0
+ 'PCINT1Addr' : '#6', # Pin Change Interrupt Request 1
+ 'TIMER2_COMPAddr' : '#8', # Timer/Counter2 Compare Match
+ 'TIMER2_OVFAddr' : '#10', # Timer/Counter2 Overflow
+ 'TIMER1_CAPTAddr' : '#12', # Timer/Counter1 Capture Event
+ 'TIMER1_COMPAAddr' : '#14', # Timer/Counter1 Compare Match A
+ 'TIMER1_COMPBAddr' : '#16', # Timer/Counter Compare Match B
+ 'TIMER1_OVFAddr' : '#18', # Timer/Counter1 Overflow
+ 'TIMER0_COMPAddr' : '#20', # Timer/Counter0 Compare Match
+ 'TIMER0_OVFAddr' : '#22', # Timer/Counter0 Overflow
+ 'SPI_STCAddr' : '#24', # SPI Serial Transfer Complete
+ 'USART_RXAddr' : '#26', # USART, Rx Complete
+ 'USART_UDREAddr' : '#28', # USART Data register Empty
+ 'USART0_TXAddr' : '#30', # USART0, Tx Complete
+ 'USI_STARTAddr' : '#32', # USI Start Condition
+ 'USI_OVERFLOWAddr' : '#34', # USI Overflow
+ 'ANALOG_COMPAddr' : '#36', # Analog Comparator
+ 'ADCAddr' : '#38', # ADC Conversion Complete
+ 'EE_READYAddr' : '#40', # EEPROM Ready
+ 'SPM_READYAddr' : '#42', # Store Program Memory Read
+ 'LCDAddr' : '#44', # LCD Start of Frame
+ 'PCINT2Addr' : '#46', # Pin Change Interrupt Request 2
+ 'PCINT3Addr' : '#48', # Pin Change Interrupt Request 3
+
+# Module AD_CONVERTER
+ 'ADMUX' : '$7c', # The ADC multiplexer Selection
+ 'ADMUX_REFS': '$c0', # Reference Selection Bits
+ 'ADMUX_ADLAR': '$20', # Left Adjust Result
+ 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
+ 'ADCSRA' : '$7a', # The ADC Control and Status reg
+ 'ADCSRA_ADEN': '$80', # ADC Enable
+ 'ADCSRA_ADSC': '$40', # ADC Start Conversion
+ 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
+ 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
+ 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
+ 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
+ 'ADC' : '$78', # ADC Data Register Bytes
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Sources
+ 'DIDR0' : '$7e', # Digital Input Disable Register
+ 'DIDR0_ADC7D': '$80', # ADC7 Digital input Disable
+ 'DIDR0_ADC6D': '$40', # ADC6 Digital input Disable
+ 'DIDR0_ADC5D': '$20', # ADC5 Digital input Disable
+ 'DIDR0_ADC4D': '$10', # ADC4 Digital input Disable
+ 'DIDR0_ADC3D': '$8', # ADC3 Digital input Disable
+ 'DIDR0_ADC2D': '$4', # ADC2 Digital input Disable
+ 'DIDR0_ADC1D': '$2', # ADC1 Digital input Disable
+ 'DIDR0_ADC0D': '$1', # ADC0 Digital input Disable
+
+# Module ANALOG_COMPARATOR
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
+ 'ACSR' : '$50', # Analog Comparator Control And
+ 'ACSR_ACD': '$80', # Analog Comparator Disable
+ 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
+ 'ACSR_ACO': '$20', # Analog Compare Output
+ 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
+ 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
+ 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
+ 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
+ 'DIDR1' : '$7f', # Digital Input Disable Register
+ 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
+ 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
+
+# Module SPI
+ 'SPCR' : '$4c', # SPI Control Register
+ 'SPCR_SPIE': '$80', # SPI Interrupt Enable
+ 'SPCR_SPE': '$40', # SPI Enable
+ 'SPCR_DORD': '$20', # Data Order
+ 'SPCR_MSTR': '$10', # Master/Slave Select
+ 'SPCR_CPOL': '$8', # Clock polarity
+ 'SPCR_CPHA': '$4', # Clock Phase
+ 'SPCR_SPR': '$3', # SPI Clock Rate Selects
+ 'SPSR' : '$4d', # SPI Status Register
+ 'SPSR_SPIF': '$80', # SPI Interrupt Flag
+ 'SPSR_WCOL': '$40', # Write Collision Flag
+ 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
+ 'SPDR' : '$4e', # SPI Data Register
+
+# Module USI
+ 'USIDR' : '$ba', # USI Data Register
+ 'USISR' : '$b9', # USI Status Register
+ 'USISR_USISIF': '$80', # Start Condition Interrupt Flag
+ 'USISR_USIOIF': '$40', # Counter Overflow Interrupt Fla
+ 'USISR_USIPF': '$20', # Stop Condition Flag
+ 'USISR_USIDC': '$10', # Data Output Collision
+ 'USISR_USICNT': '$f', # USI Counter Value Bits
+ 'USICR' : '$b8', # USI Control Register
+ 'USICR_USISIE': '$80', # Start Condition Interrupt Enab
+ 'USICR_USIOIE': '$40', # Counter Overflow Interrupt Ena
+ 'USICR_USIWM': '$30', # USI Wire Mode Bits
+ 'USICR_USICS': '$c', # USI Clock Source Select Bits
+ 'USICR_USICLK': '$2', # Clock Strobe
+ 'USICR_USITC': '$1', # Toggle Clock Port Pin
+
+# Module USART0
+ 'UDR0' : '$c6', # USART I/O Data Register
+ 'UCSR0A' : '$c0', # USART Control and Status Regis
+ 'UCSR0A_RXC0': '$80', # USART Receive Complete
+ 'UCSR0A_TXC0': '$40', # USART Transmit Complete
+ 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
+ 'UCSR0A_FE0': '$10', # Framing Error
+ 'UCSR0A_DOR0': '$8', # Data OverRun
+ 'UCSR0A_UPE0': '$4', # USART Parity Error
+ 'UCSR0A_U2X0': '$2', # Double the USART Transmission
+ 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
+ 'UCSR0B' : '$c1', # USART Control and Status Regis
+ 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
+ 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
+ 'UCSR0B_UDRIE0': '$20', # USART Data Register Empty Inte
+ 'UCSR0B_RXEN0': '$10', # Receiver Enable
+ 'UCSR0B_TXEN0': '$8', # Transmitter Enable
+ 'UCSR0B_UCSZ02': '$4', # Character Size
+ 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
+ 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
+ 'UCSR0C' : '$c2', # USART Control and Status Regis
+ 'UCSR0C_UMSEL0': '$40', # USART Mode Select
+ 'UCSR0C_UPM0': '$30', # Parity Mode Bits
+ 'UCSR0C_USBS0': '$8', # Stop Bit Select
+ 'UCSR0C_UCSZ0': '$6', # Character Size
+ 'UCSR0C_UCPOL0': '$1', # Clock Polarity
+ 'UBRR0' : '$c4', # USART Baud Rate Register Byte
+
+# Module CPU
+ 'SREG' : '$5f', # Status Register
+ 'SREG_I': '$80', # Global Interrupt Enable
+ 'SREG_T': '$40', # Bit Copy Storage
+ 'SREG_H': '$20', # Half Carry Flag
+ 'SREG_S': '$10', # Sign Bit
+ 'SREG_V': '$8', # Two's Complement Overflow Flag
+ 'SREG_N': '$4', # Negative Flag
+ 'SREG_Z': '$2', # Zero Flag
+ 'SREG_C': '$1', # Carry Flag
+ 'SP' : '$5d', # Stack Pointer
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_PUD': '$10', # Pull-up disable
+ 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
+ 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+ 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
+ 'MCUSR_BORF': '$4', # Brown-out Reset Flag
+ 'MCUSR_EXTRF': '$2', # External Reset Flag
+ 'MCUSR_PORF': '$1', # Power-on reset flag
+ 'OSCCAL' : '$66', # Oscillator Calibration Value
+ 'CLKPR' : '$61', # Clock Prescale Register
+ 'CLKPR_CLKPCE': '$80', # Clock Prescaler Change Enable
+ 'CLKPR_CLKPS': '$f', # Clock Prescaler Select Bits
+ 'PRR' : '$64', # Power Reduction Register
+ 'PRR_PRLCD': '$10', # Power Reduction LCD
+ 'PRR_PRTIM1': '$8', # Power Reduction Timer/Counter1
+ 'PRR_PRSPI': '$4', # Power Reduction Serial Periphe
+ 'PRR_PRUSART0': '$2', # Power Reduction USART
+ 'PRR_PRADC': '$1', # Power Reduction ADC
+ 'SMCR' : '$53', # Sleep Mode Control Register
+ 'SMCR_SM': '$e', # Sleep Mode Select bits
+ 'SMCR_SE': '$1', # Sleep Enable
+ 'GPIOR2' : '$4b', # General Purpose IO Register 2
+ 'GPIOR1' : '$4a', # General Purpose IO Register 1
+ 'GPIOR0' : '$3e', # General Purpose IO Register 0
+
+# Module JTAG
+ 'OCDR' : '$51', # On-Chip Debug Related Register
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_JTD': '$80', # JTAG Interface Disable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+
+# Module EEPROM
+ 'EEAR' : '$41', # EEPROM Read/Write Access Byte
+ 'EEDR' : '$40', # EEPROM Data Register
+ 'EECR' : '$3f', # EEPROM Control Register
+ 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
+ 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
+ 'EECR_EEWE': '$2', # EEPROM Write Enable
+ 'EECR_EERE': '$1', # EEPROM Read Enable
+
+# Module PORTA
+ 'PORTA' : '$22', # Port A Data Register
+ 'DDRA' : '$21', # Port A Data Direction Register
+ 'PINA' : '$20', # Port A Input Pins
+
+# Module PORTB
+ 'PORTB' : '$25', # Port B Data Register
+ 'DDRB' : '$24', # Port B Data Direction Register
+ 'PINB' : '$23', # Port B Input Pins
+
+# Module PORTC
+ 'PORTC' : '$28', # Port C Data Register
+ 'DDRC' : '$27', # Port C Data Direction Register
+ 'PINC' : '$26', # Port C Input Pins
+
+# Module PORTD
+ 'PORTD' : '$2b', # Port D Data Register
+ 'DDRD' : '$2a', # Port D Data Direction Register
+ 'PIND' : '$29', # Port D Input Pins
+
+# Module PORTE
+ 'PORTE' : '$2e', # Data Register, Port E
+ 'DDRE' : '$2d', # Data Direction Register, Port
+ 'PINE' : '$2c', # Input Pins, Port E
+
+# Module PORTF
+ 'PORTF' : '$31', # Data Register, Port F
+ 'DDRF' : '$30', # Data Direction Register, Port
+ 'PINF' : '$2f', # Input Pins, Port F
+
+# Module PORTG
+ 'PORTG' : '$34', # Port G Data Register
+ 'DDRG' : '$33', # Port G Data Direction Register
+ 'PING' : '$32', # Port G Input Pins
+
+# Module TIMER_COUNTER_0
+ 'TCCR0A' : '$44', # Timer/Counter0 Control Registe
+ 'TCCR0A_FOC0A': '$80', # Force Output Compare
+ 'TCCR0A_WGM00': '$40', # Waveform Generation Mode 0
+ 'TCCR0A_COM0A': '$30', # Compare Match Output Modes
+ 'TCCR0A_WGM01': '$8', # Waveform Generation Mode 1
+ 'TCCR0A_CS0': '$7', # Clock Selects
+ 'TCNT0' : '$46', # Timer/Counter0
+ 'OCR0A' : '$47', # Timer/Counter0 Output Compare
+ 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
+ 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
+ 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
+ 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
+ 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
+ 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Control Register
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSR310': '$1', # Prescaler Reset Timer/Counter1
+
+# Module TIMER_COUNTER_1
+ 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
+ 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
+ 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
+ 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
+ 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
+ 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
+ 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
+ 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
+ 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
+ 'TCCR1C' : '$82', # Timer/Counter 1 Control Regist
+ 'TCCR1C_FOC1A': '$80', # Force Output Compare 1A
+ 'TCCR1C_FOC1B': '$40', # Force Output Compare 1B
+ 'TCNT1' : '$84', # Timer/Counter1 Bytes
+ 'OCR1A' : '$88', # Timer/Counter1 Output Compare
+ 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
+ 'ICR1' : '$86', # Timer/Counter1 Input Capture R
+ 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
+ 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
+ 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
+ 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
+ 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
+ 'TIFR1' : '$36', # Timer/Counter1 Interrupt Flag
+ 'TIFR1_ICF1': '$20', # Input Capture Flag 1
+ 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
+ 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
+ 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
+
+# Module TIMER_COUNTER_2
+ 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
+ 'TCCR2A_FOC2A': '$80', # Force Output Compare A
+ 'TCCR2A_WGM20': '$40', # Waveform Generation Mode
+ 'TCCR2A_COM2A': '$30', # Compare Output Mode bits
+ 'TCCR2A_WGM21': '$8', # Waveform Generation Mode
+ 'TCCR2A_CS2': '$7', # Clock Select bits
+ 'TCNT2' : '$b2', # Timer/Counter2
+ 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
+ 'TIMSK2' : '$70', # Timer/Counter2 Interrupt Mask
+ 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
+ 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
+ 'TIFR2' : '$37', # Timer/Counter2 Interrupt Flag
+ 'TIFR2_OCF2A': '$2', # Timer/Counter2 Output Compare
+ 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_PSR2': '$2', # Prescaler Reset Timer/Counter2
+ 'ASSR' : '$b6', # Asynchronous Status Register
+ 'ASSR_EXCLK': '$10', # Enable External Clock Interrup
+ 'ASSR_AS2': '$8', # AS2: Asynchronous Timer/Counte
+ 'ASSR_TCN2UB': '$4', # TCN2UB: Timer/Counter2 Update
+ 'ASSR_OCR2UB': '$2', # Output Compare Register2 Updat
+ 'ASSR_TCR2UB': '$1', # TCR2UB: Timer/Counter Control
+
+# Module WATCHDOG
+ 'WDTCR' : '$60', # Watchdog Timer Control Registe
+ 'WDTCR_WDCE': '$10', # Watchdog Change Enable
+ 'WDTCR_WDE': '$8', # Watch Dog Enable
+ 'WDTCR_WDP': '$7', # Watch Dog Timer Prescaler bits
+
+# Module BOOT_LOAD
+ 'SPMCSR' : '$57', # Store Program Memory Control R
+ 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
+ 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
+ 'SPMCSR_RWWSRE': '$10', # Read While Write section read
+ 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
+ 'SPMCSR_PGWRT': '$4', # Page Write
+ 'SPMCSR_PGERS': '$2', # Page Erase
+ 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
+
+# Module PORTH
+ 'PORTH' : '$da', # PORT H Data Register
+ 'DDRH' : '$d9', # PORT H Data Direction Register
+ 'PINH' : '$d8', # PORT H Input Pins
+
+# Module PORTJ
+ 'PORTJ' : '$dd', # PORT J Data Register
+ 'DDRJ' : '$dc', # PORT J Data Direction Register
+ 'PINJ' : '$db', # PORT J Input Pins
+
+# Module LCD
+ 'LCDDR19' : '$ff', # LCD Data Register 19
+ 'LCDDR18' : '$fe', # LCD Data Register 18
+ 'LCDDR17' : '$fd', # LCD Data Register 17
+ 'LCDDR16' : '$fc', # LCD Data Register 16
+ 'LCDDR15' : '$fb', # LCD Data Register 15
+ 'LCDDR14' : '$fa', # LCD Data Register 14
+ 'LCDDR13' : '$f9', # LCD Data Register 13
+ 'LCDDR12' : '$f8', # LCD Data Register 12
+ 'LCDDR11' : '$f7', # LCD Data Register 11
+ 'LCDDR10' : '$f6', # LCD Data Register 10
+ 'LCDDR9' : '$f5', # LCD Data Register 9
+ 'LCDDR8' : '$f4', # LCD Data Register 8
+ 'LCDDR7' : '$f3', # LCD Data Register 7
+ 'LCDDR6' : '$f2', # LCD Data Register 6
+ 'LCDDR5' : '$f1', # LCD Data Register 5
+ 'LCDDR4' : '$f0', # LCD Data Register 4
+ 'LCDDR3' : '$ef', # LCD Data Register 3
+ 'LCDDR2' : '$ee', # LCD Data Register 2
+ 'LCDDR1' : '$ed', # LCD Data Register 1
+ 'LCDDR0' : '$ec', # LCD Data Register 0
+ 'LCDCCR' : '$e7', # LCD Contrast Control Register
+ 'LCDFRR' : '$e6', # LCD Frame Rate Register
+ 'LCDFRR_LCDPS': '$70', # LCD Prescaler Selects
+ 'LCDFRR_LCDCD': '$7', # LCD Clock Dividers
+ 'LCDCRB' : '$e5', # LCD Control and Status Registe
+ 'LCDCRB_LCDCS': '$80', # LCD CLock Select
+ 'LCDCRB_LCD2B': '$40', # LCD 1/2 Bias Select
+ 'LCDCRB_LCDMUX': '$30', # LCD Mux Selects
+ 'LCDCRB_LCDPM': '$f', # LCD Port Masks
+ 'LCDCRA' : '$e4', # LCD Control and Status Registe
+ 'LCDCRA_LCDEN': '$80', # LCD Enable
+ 'LCDCRA_LCDAB': '$40', # LCD A or B waveform
+ 'LCDCRA_LCDIF': '$10', # LCD Interrupt Flag
+ 'LCDCRA_LCDIE': '$8', # LCD Interrupt Enable
+ 'LCDCRA_LCDBL': '$1', # LCD Blanking
+
+# Module EXTERNAL_INTERRUPT
+ 'EICRA' : '$69', # External Interrupt Control Reg
+ 'EICRA_ISC01': '$2', # External Interrupt Sense Contr
+ 'EICRA_ISC00': '$1', # External Interrupt Sense Contr
+ 'EIMSK' : '$3d', # External Interrupt Mask Regist
+ 'EIMSK_PCIE': '$f0', # Pin Change Interrupt Enables
+ 'EIMSK_INT0': '$1', # External Interrupt Request 0 E
+ 'EIFR' : '$3c', # External Interrupt Flag Regist
+ 'EIFR_PCIF': '$f0', # Pin Change Interrupt Flags
+ 'EIFR_INTF0': '$1', # External Interrupt Flag 0
+ 'PCMSK3' : '$73', # Pin Change Mask Register 3
+ 'PCMSK2' : '$6d', # Pin Change Mask Register 2
+ 'PCMSK1' : '$6c', # Pin Change Mask Register 1
+ 'PCMSK0' : '$6b', # Pin Change Mask Register 0
+
+ '__amforth_dummy':'0'
+}
diff --git a/amforth-6.5/avr8/devices/atmega6490p/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega6490p/words/no-jtag.asm
new file mode 100644
index 0000000..352a4bb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega6490p/words/no-jtag.asm
@@ -0,0 +1,14 @@
+; ( -- )
+; ( -- )
+; MCU
+; disable jtag at runtime
+VE_NOJTAG:
+ .dw $FF05
+ .db "-jtag",0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOJTAG
+XT_NOJTAG:
+ .dw PFA_NOJTAG
+PFA_NOJTAG:
+
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega6490p/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega6490p/words/no-wdt.asm
new file mode 100644
index 0000000..4a12261
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega6490p/words/no-wdt.asm
@@ -0,0 +1,22 @@
+; ( -- )
+; MCU
+; disable watch dog timer at runtime
+VE_NOWDT:
+ .dw $ff04
+ .db "-wdt"
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOWDT
+XT_NOWDT:
+ .dw PFA_NOWDT
+PFA_NOWDT:
+
+; Reset WDT
+ wdr
+; Write logical one to WDTOE and WDE
+ in_ temp1, WDTCR
+ ori temp1, (1<<WDTOE)|(1<<WDE)
+ out WDTCR, temp1
+; Turn off WDT
+ ldi temp1, (0<<WDE)
+ out_ WDTCR, temp1
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega6490p/words/sleep.asm b/amforth-6.5/avr8/devices/atmega6490p/words/sleep.asm
new file mode 100644
index 0000000..256249c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega6490p/words/sleep.asm
@@ -0,0 +1,19 @@
+; ( mode -- )
+; MCU
+; put the controller into the specified sleep mode
+VE_SLEEP:
+ .dw $ff05
+ .db "sleep", 0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_SLEEP
+XT_SLEEP:
+ .dw PFA_SLEEP
+PFA_SLEEP:
+ andi tosl, 7 ; leave only legal mode bits
+ lsl tosl ; move to correct location (bits 3-1)
+ ori tosl, 1 ; set the SE bit
+ out_ SMCR, tosl ; set the sleep config
+ sleep ; nighty-night
+ out_ SMCR, zerol ; 0 protects against accidental sleeps
+ loadtos ; pop argument from stack
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega649a/atmega649a.frt b/amforth-6.5/avr8/devices/atmega649a/atmega649a.frt
new file mode 100644
index 0000000..43d2d0c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega649a/atmega649a.frt
@@ -0,0 +1,318 @@
+\ Partname: ATmega649A
+\ generated automatically
+
+\ AD_CONVERTER
+&124 constant ADMUX \ The ADC multiplexer Selection Register
+ $C0 constant ADMUX_REFS \ Reference Selection Bits
+ $20 constant ADMUX_ADLAR \ Left Adjust Result
+ $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
+&122 constant ADCSRA \ The ADC Control and Status register
+ $80 constant ADCSRA_ADEN \ ADC Enable
+ $40 constant ADCSRA_ADSC \ ADC Start Conversion
+ $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
+ $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
+ $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
+ $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
+&120 constant ADC \ ADC Data Register Bytes
+&123 constant ADCSRB \ ADC Control and Status Register B
+ $07 constant ADCSRB_ADTS \ ADC Auto Trigger Sources
+&126 constant DIDR0 \ Digital Input Disable Register 0
+ $80 constant DIDR0_ADC7D \ ADC7 Digital input Disable
+ $40 constant DIDR0_ADC6D \ ADC6 Digital input Disable
+ $20 constant DIDR0_ADC5D \ ADC5 Digital input Disable
+ $10 constant DIDR0_ADC4D \ ADC4 Digital input Disable
+ $08 constant DIDR0_ADC3D \ ADC3 Digital input Disable
+ $04 constant DIDR0_ADC2D \ ADC2 Digital input Disable
+ $02 constant DIDR0_ADC1D \ ADC1 Digital input Disable
+ $01 constant DIDR0_ADC0D \ ADC0 Digital input Disable
+\ ANALOG_COMPARATOR
+&80 constant ACSR \ Analog Comparator Control And Status Register
+ $80 constant ACSR_ACD \ Analog Comparator Disable
+ $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
+ $20 constant ACSR_ACO \ Analog Compare Output
+ $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
+ $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
+ $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
+ $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
+&127 constant DIDR1 \ Digital Input Disable Register 1
+ $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
+ $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
+\ SPI
+&76 constant SPCR \ SPI Control Register
+ $80 constant SPCR_SPIE \ SPI Interrupt Enable
+ $40 constant SPCR_SPE \ SPI Enable
+ $20 constant SPCR_DORD \ Data Order
+ $10 constant SPCR_MSTR \ Master/Slave Select
+ $08 constant SPCR_CPOL \ Clock polarity
+ $04 constant SPCR_CPHA \ Clock Phase
+ $03 constant SPCR_SPR \ SPI Clock Rate Selects
+&77 constant SPSR \ SPI Status Register
+ $80 constant SPSR_SPIF \ SPI Interrupt Flag
+ $40 constant SPSR_WCOL \ Write Collision Flag
+ $01 constant SPSR_SPI2X \ Double SPI Speed Bit
+&78 constant SPDR \ SPI Data Register
+\ USI
+&186 constant USIDR \ USI Data Register
+&185 constant USISR \ USI Status Register
+ $80 constant USISR_USISIF \ Start Condition Interrupt Flag
+ $40 constant USISR_USIOIF \ Counter Overflow Interrupt Flag
+ $20 constant USISR_USIPF \ Stop Condition Flag
+ $10 constant USISR_USIDC \ Data Output Collision
+ $0F constant USISR_USICNT \ USI Counter Value Bits
+&184 constant USICR \ USI Control Register
+ $80 constant USICR_USISIE \ Start Condition Interrupt Enable
+ $40 constant USICR_USIOIE \ Counter Overflow Interrupt Enable
+ $30 constant USICR_USIWM \ USI Wire Mode Bits
+ $0C constant USICR_USICS \ USI Clock Source Select Bits
+ $02 constant USICR_USICLK \ Clock Strobe
+ $01 constant USICR_USITC \ Toggle Clock Port Pin
+\ USART0
+&198 constant UDR0 \ USART I/O Data Register
+&192 constant UCSR0A \ USART Control and Status Register A
+ $80 constant UCSR0A_RXC0 \ USART Receive Complete
+ $40 constant UCSR0A_TXC0 \ USART Transmit Complete
+ $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
+ $10 constant UCSR0A_FE0 \ Framing Error
+ $08 constant UCSR0A_DOR0 \ Data OverRun
+ $04 constant UCSR0A_UPE0 \ USART Parity Error
+ $02 constant UCSR0A_U2X0 \ Double the USART Transmission Speed
+ $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
+&193 constant UCSR0B \ USART Control and Status Register B
+ $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
+ $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
+ $20 constant UCSR0B_UDRIE0 \ USART Data Register Empty Interrupt Enable
+ $10 constant UCSR0B_RXEN0 \ Receiver Enable
+ $08 constant UCSR0B_TXEN0 \ Transmitter Enable
+ $04 constant UCSR0B_UCSZ02 \ Character Size
+ $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
+ $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
+&194 constant UCSR0C \ USART Control and Status Register C
+ $40 constant UCSR0C_UMSEL0 \ USART Mode Select
+ $30 constant UCSR0C_UPM0 \ Parity Mode Bits
+ $08 constant UCSR0C_USBS0 \ Stop Bit Select
+ $06 constant UCSR0C_UCSZ0 \ Character Size
+ $01 constant UCSR0C_UCPOL0 \ Clock Polarity
+&196 constant UBRR0 \ USART Baud Rate Register Bytes
+\ CPU
+&95 constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ $08 constant SREG_V \ Two's Complement Overflow Flag
+ $04 constant SREG_N \ Negative Flag
+ $02 constant SREG_Z \ Zero Flag
+ $01 constant SREG_C \ Carry Flag
+&93 constant SP \ Stack Pointer
+&85 constant MCUCR \ MCU Control Register
+ $10 constant MCUCR_PUD \ Pull-up disable
+ $02 constant MCUCR_IVSEL \ Interrupt Vector Select
+ $01 constant MCUCR_IVCE \ Interrupt Vector Change Enable
+&84 constant MCUSR \ MCU Status Register
+ $10 constant MCUSR_JTRF \ JTAG Reset Flag
+ $08 constant MCUSR_WDRF \ Watchdog Reset Flag
+ $04 constant MCUSR_BORF \ Brown-out Reset Flag
+ $02 constant MCUSR_EXTRF \ External Reset Flag
+ $01 constant MCUSR_PORF \ Power-on reset flag
+&102 constant OSCCAL \ Oscillator Calibration Value
+&97 constant CLKPR \ Clock Prescale Register
+ $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable
+ $0F constant CLKPR_CLKPS \ Clock Prescaler Select Bits
+&100 constant PRR \ Power Reduction Register
+ $10 constant PRR_PRLCD \ Power Reduction LCD
+ $08 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
+ $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
+ $02 constant PRR_PRUSART0 \ Power Reduction USART
+ $01 constant PRR_PRADC \ Power Reduction ADC
+&83 constant SMCR \ Sleep Mode Control Register
+ $0E constant SMCR_SM \ Sleep Mode Select bits
+ $01 constant SMCR_SE \ Sleep Enable
+&75 constant GPIOR2 \ General Purpose IO Register 2
+&74 constant GPIOR1 \ General Purpose IO Register 1
+&62 constant GPIOR0 \ General Purpose IO Register 0
+\ JTAG
+&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
+\ LCD
+&254 constant LCDDR18 \ LCD Data Register 18
+&253 constant LCDDR17 \ LCD Data Register 17
+&252 constant LCDDR16 \ LCD Data Register 16
+&251 constant LCDDR15 \ LCD Data Register 15
+&249 constant LCDDR13 \ LCD Data Register 13
+&248 constant LCDDR12 \ LCD Data Register 12
+&247 constant LCDDR11 \ LCD Data Register 11
+&246 constant LCDDR10 \ LCD Data Register 10
+&244 constant LCDDR8 \ LCD Data Register 8
+&243 constant LCDDR7 \ LCD Data Register 7
+&242 constant LCDDR6 \ LCD Data Register 6
+&241 constant LCDDR5 \ LCD Data Register 5
+&239 constant LCDDR3 \ LCD Data Register 3
+&238 constant LCDDR2 \ LCD Data Register 2
+&237 constant LCDDR1 \ LCD Data Register 1
+&236 constant LCDDR0 \ LCD Data Register 0
+&231 constant LCDCCR \ LCD Contrast Control Register
+&230 constant LCDFRR \ LCD Frame Rate Register
+ $70 constant LCDFRR_LCDPS \ LCD Prescaler Selects
+ $07 constant LCDFRR_LCDCD \ LCD Clock Dividers
+&229 constant LCDCRB \ LCD Control and Status Register B
+ $80 constant LCDCRB_LCDCS \ LCD CLock Select
+ $40 constant LCDCRB_LCD2B \ LCD 1/2 Bias Select
+ $30 constant LCDCRB_LCDMUX \ LCD Mux Selects
+ $0F constant LCDCRB_LCDPM \ LCD Port Masks
+&228 constant LCDCRA \ LCD Control Register A
+ $80 constant LCDCRA_LCDEN \ LCD Enable
+ $40 constant LCDCRA_LCDAB \ LCD A or B waveform
+ $10 constant LCDCRA_LCDIF \ LCD Interrupt Flag
+ $08 constant LCDCRA_LCDIE \ LCD Interrupt Enable
+ $01 constant LCDCRA_LCDBL \ LCD Blanking
+\ EXTERNAL_INTERRUPT
+&105 constant EICRA \ External Interrupt Control Register A
+ $02 constant EICRA_ISC01 \ External Interrupt Sense Control 0 Bit 1
+ $01 constant EICRA_ISC00 \ External Interrupt Sense Control 0 Bit 0
+&61 constant EIMSK \ External Interrupt Mask Register
+ $F0 constant EIMSK_PCIE \ Pin Change Interrupt Enables
+ $01 constant EIMSK_INT0 \ External Interrupt Request 0 Enable
+&60 constant EIFR \ External Interrupt Flag Register
+ $F0 constant EIFR_PCIF \ Pin Change Interrupt Flags
+ $01 constant EIFR_INTF0 \ External Interrupt Flag 0
+&108 constant PCMSK1 \ Pin Change Mask Register 1
+&107 constant PCMSK0 \ Pin Change Mask Register 0
+\ EEPROM
+&65 constant EEAR \ EEPROM Read/Write Access Bytes
+&64 constant EEDR \ EEPROM Data Register
+&63 constant EECR \ EEPROM Control Register
+ $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
+ $04 constant EECR_EEMWE \ EEPROM Master Write Enable
+ $02 constant EECR_EEWE \ EEPROM Write Enable
+ $01 constant EECR_EERE \ EEPROM Read Enable
+\ PORTA
+&34 constant PORTA \ Port A Data Register
+&33 constant DDRA \ Port A Data Direction Register
+&32 constant PINA \ Port A Input Pins
+\ PORTB
+&37 constant PORTB \ Port B Data Register
+&36 constant DDRB \ Port B Data Direction Register
+&35 constant PINB \ Port B Input Pins
+\ PORTC
+&40 constant PORTC \ Port C Data Register
+&39 constant DDRC \ Port C Data Direction Register
+&38 constant PINC \ Port C Input Pins
+\ PORTD
+&43 constant PORTD \ Port D Data Register
+&42 constant DDRD \ Port D Data Direction Register
+&41 constant PIND \ Port D Input Pins
+\ PORTE
+&46 constant PORTE \ Data Register, Port E
+&45 constant DDRE \ Data Direction Register, Port E
+&44 constant PINE \ Input Pins, Port E
+\ PORTF
+&49 constant PORTF \ Data Register, Port F
+&48 constant DDRF \ Data Direction Register, Port F
+&47 constant PINF \ Input Pins, Port F
+\ PORTG
+&52 constant PORTG \ Port G Data Register
+&51 constant DDRG \ Port G Data Direction Register
+&50 constant PING \ Port G Input Pins
+\ TIMER_COUNTER_0
+&68 constant TCCR0A \ Timer/Counter0 Control Register
+ $80 constant TCCR0A_FOC0A \ Force Output Compare
+ $40 constant TCCR0A_WGM00 \ Waveform Generation Mode 0
+ $30 constant TCCR0A_COM0A \ Compare Match Output Modes
+ $08 constant TCCR0A_WGM01 \ Waveform Generation Mode 1
+ $07 constant TCCR0A_CS0 \ Clock Selects
+&70 constant TCNT0 \ Timer/Counter0
+&71 constant OCR0A \ Timer/Counter0 Output Compare Register
+&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
+ $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match Interrupt Enable
+ $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
+&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
+ $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0
+ $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
+&67 constant GTCCR \ General Timer/Control Register
+ $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
+ $01 constant GTCCR_PSR310 \ Prescaler Reset Timer/Counter1 and Timer/Counter0
+\ TIMER_COUNTER_1
+&128 constant TCCR1A \ Timer/Counter1 Control Register A
+ $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
+ $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
+ $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
+&129 constant TCCR1B \ Timer/Counter1 Control Register B
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
+ $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
+&130 constant TCCR1C \ Timer/Counter 1 Control Register C
+ $80 constant TCCR1C_FOC1A \ Force Output Compare 1A
+ $40 constant TCCR1C_FOC1B \ Force Output Compare 1B
+&132 constant TCNT1 \ Timer/Counter1 Bytes
+&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
+&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
+&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
+&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
+ $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
+ $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
+ $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
+ $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
+&54 constant TIFR1 \ Timer/Counter1 Interrupt Flag register
+ $20 constant TIFR1_ICF1 \ Input Capture Flag 1
+ $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
+ $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
+ $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
+\ TIMER_COUNTER_2
+&176 constant TCCR2A \ Timer/Counter2 Control Register
+ $80 constant TCCR2A_FOC2A \ Force Output Compare A
+ $40 constant TCCR2A_WGM20 \ Waveform Generation Mode
+ $30 constant TCCR2A_COM2A \ Compare Output Mode bits
+ $08 constant TCCR2A_WGM21 \ Waveform Generation Mode
+ $07 constant TCCR2A_CS2 \ Clock Select bits
+&178 constant TCNT2 \ Timer/Counter2
+&179 constant OCR2A \ Timer/Counter2 Output Compare Register
+&112 constant TIMSK2 \ Timer/Counter2 Interrupt Mask register
+ $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match Interrupt Enable
+ $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
+&55 constant TIFR2 \ Timer/Counter2 Interrupt Flag Register
+ $02 constant TIFR2_OCF2A \ Timer/Counter2 Output Compare Flag 2
+ $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
+&182 constant ASSR \ Asynchronous Status Register
+ $10 constant ASSR_EXCLK \ Enable External Clock Interrupt
+ $08 constant ASSR_AS2 \ AS2: Asynchronous Timer/Counter2
+ $04 constant ASSR_TCN2UB \ TCN2UB: Timer/Counter2 Update Busy
+ $02 constant ASSR_OCR2UB \ Output Compare Register2 Update Busy
+ $01 constant ASSR_TCR2UB \ TCR2UB: Timer/Counter Control Register2 Update Busy
+\ WATCHDOG
+&96 constant WDTCR \ Watchdog Timer Control Register
+ $10 constant WDTCR_WDCE \ Watchdog Change Enable
+ $08 constant WDTCR_WDE \ Watch Dog Enable
+ $07 constant WDTCR_WDP \ Watch Dog Timer Prescaler bits
+\ BOOT_LOAD
+&87 constant SPMCSR \ Store Program Memory Control Register
+ $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
+ $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
+ $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
+ $04 constant SPMCSR_PGWRT \ Page Write
+ $02 constant SPMCSR_PGERS \ Page Erase
+ $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
+
+\ Interrupts
+&2 constant INT0Addr \ External Interrupt Request 0
+&4 constant PCINT0Addr \ Pin Change Interrupt Request 0
+&6 constant PCINT1Addr \ Pin Change Interrupt Request 1
+&8 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
+&10 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
+&12 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+&14 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
+&16 constant TIMER1_COMPBAddr \ Timer/Counter Compare Match B
+&18 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+&20 constant TIMER0_COMPAddr \ Timer/Counter0 Compare Match
+&22 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
+&24 constant SPI__STCAddr \ SPI Serial Transfer Complete
+&26 constant USART0__RXAddr \ USART0, Rx Complete
+&28 constant USART0__UDREAddr \ USART0 Data register Empty
+&30 constant USART0__TXAddr \ USART0, Tx Complete
+&32 constant USI_STARTAddr \ USI Start Condition
+&34 constant USI_OVERFLOWAddr \ USI Overflow
+&36 constant ANALOG_COMPAddr \ Analog Comparator
+&38 constant ADCAddr \ ADC Conversion Complete
+&40 constant EE_READYAddr \ EEPROM Ready
+&42 constant SPM_READYAddr \ Store Program Memory Read
+&44 constant LCDAddr \ LCD Start of Frame
diff --git a/amforth-6.5/avr8/devices/atmega649a/device.asm b/amforth-6.5/avr8/devices/atmega649a/device.asm
new file mode 100644
index 0000000..dffd7fb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega649a/device.asm
@@ -0,0 +1,109 @@
+; Partname: ATmega649A
+; generated automatically, do not edit
+
+.nolist
+ .include "m649Adef.inc"
+.list
+
+.equ ramstart = 256
+.equ CELLSIZE = 2
+.macro readflashcell
+ lsl zl
+ rol zh
+ lpm @0, Z+
+ lpm @1, Z+
+.endmacro
+.macro writeflashcell
+ lsl zl
+ rol zh
+.endmacro
+.set WANT_AD_CONVERTER = 0
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_SPI = 0
+.set WANT_USI = 0
+.set WANT_USART0 = 0
+.set WANT_CPU = 0
+.set WANT_JTAG = 0
+.set WANT_LCD = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_EEPROM = 0
+.set WANT_PORTA = 0
+.set WANT_PORTB = 0
+.set WANT_PORTC = 0
+.set WANT_PORTD = 0
+.set WANT_PORTE = 0
+.set WANT_PORTF = 0
+.set WANT_PORTG = 0
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_TIMER_COUNTER_2 = 0
+.set WANT_WATCHDOG = 0
+.set WANT_BOOT_LOAD = 0
+.equ intvecsize = 2 ; please verify; flash size: 65536 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.org 2
+ rcall isr ; External Interrupt Request 0
+.org 4
+ rcall isr ; Pin Change Interrupt Request 0
+.org 6
+ rcall isr ; Pin Change Interrupt Request 1
+.org 8
+ rcall isr ; Timer/Counter2 Compare Match
+.org 10
+ rcall isr ; Timer/Counter2 Overflow
+.org 12
+ rcall isr ; Timer/Counter1 Capture Event
+.org 14
+ rcall isr ; Timer/Counter1 Compare Match A
+.org 16
+ rcall isr ; Timer/Counter Compare Match B
+.org 18
+ rcall isr ; Timer/Counter1 Overflow
+.org 20
+ rcall isr ; Timer/Counter0 Compare Match
+.org 22
+ rcall isr ; Timer/Counter0 Overflow
+.org 24
+ rcall isr ; SPI Serial Transfer Complete
+.org 26
+ rcall isr ; USART0, Rx Complete
+.org 28
+ rcall isr ; USART0 Data register Empty
+.org 30
+ rcall isr ; USART0, Tx Complete
+.org 32
+ rcall isr ; USI Start Condition
+.org 34
+ rcall isr ; USI Overflow
+.org 36
+ rcall isr ; Analog Comparator
+.org 38
+ rcall isr ; ADC Conversion Complete
+.org 40
+ rcall isr ; EEPROM Ready
+.org 42
+ rcall isr ; Store Program Memory Read
+.org 44
+ rcall isr ; LCD Start of Frame
+.equ INTVECTORS = 23
+.nooverlap
+
+; compatability layer (maybe empty)
+.equ EEPE = EEWE
+.equ EEMPE = EEMWE
+
+; controller data area, environment query mcu-info
+mcu_info:
+mcu_ramsize:
+ .dw 4096
+mcu_eepromsize:
+ .dw 2048
+mcu_maxdp:
+ .dw 57344
+mcu_numints:
+ .dw 23
+mcu_name:
+ .dw 10
+ .db "ATmega649A"
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega649a/device.inc b/amforth-6.5/avr8/devices/atmega649a/device.inc
new file mode 100644
index 0000000..dfebd4b
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega649a/device.inc
@@ -0,0 +1,1293 @@
+; Partname: ATmega649A
+; generated automatically, no not edit
+
+.if WANT_AD_CONVERTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC multiplexer Selection Register
+VE_ADMUX:
+ .dw $ff05
+ .db "ADMUX",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADMUX
+XT_ADMUX:
+ .dw PFA_DOVARIABLE
+PFA_ADMUX:
+ .dw 124
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register
+VE_ADCSRA:
+ .dw $ff06
+ .db "ADCSRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRA
+XT_ADCSRA:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRA:
+ .dw 122
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register Bytes
+VE_ADC:
+ .dw $ff03
+ .db "ADC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADC
+XT_ADC:
+ .dw PFA_DOVARIABLE
+PFA_ADC:
+ .dw 120
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Control and Status Register B
+VE_ADCSRB:
+ .dw $ff06
+ .db "ADCSRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRB
+XT_ADCSRB:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRB:
+ .dw 123
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 0
+VE_DIDR0:
+ .dw $ff05
+ .db "DIDR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR0
+XT_DIDR0:
+ .dw PFA_DOVARIABLE
+PFA_DIDR0:
+ .dw 126
+
+.endif
+.if WANT_ANALOG_COMPARATOR == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Control And Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw 80
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 1
+VE_DIDR1:
+ .dw $ff05
+ .db "DIDR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR1
+XT_DIDR1:
+ .dw PFA_DOVARIABLE
+PFA_DIDR1:
+ .dw 127
+
+.endif
+.if WANT_SPI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR:
+ .dw $ff04
+ .db "SPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR
+XT_SPCR:
+ .dw PFA_DOVARIABLE
+PFA_SPCR:
+ .dw 76
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR:
+ .dw $ff04
+ .db "SPSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR
+XT_SPSR:
+ .dw PFA_DOVARIABLE
+PFA_SPSR:
+ .dw 77
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR:
+ .dw $ff04
+ .db "SPDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR
+XT_SPDR:
+ .dw PFA_DOVARIABLE
+PFA_SPDR:
+ .dw 78
+
+.endif
+.if WANT_USI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USI Data Register
+VE_USIDR:
+ .dw $ff05
+ .db "USIDR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USIDR
+XT_USIDR:
+ .dw PFA_DOVARIABLE
+PFA_USIDR:
+ .dw 186
+; ( -- addr ) System Constant
+; R( -- )
+; USI Status Register
+VE_USISR:
+ .dw $ff05
+ .db "USISR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USISR
+XT_USISR:
+ .dw PFA_DOVARIABLE
+PFA_USISR:
+ .dw 185
+; ( -- addr ) System Constant
+; R( -- )
+; USI Control Register
+VE_USICR:
+ .dw $ff05
+ .db "USICR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USICR
+XT_USICR:
+ .dw PFA_DOVARIABLE
+PFA_USICR:
+ .dw 184
+
+.endif
+.if WANT_USART0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR0:
+ .dw $ff04
+ .db "UDR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR0
+XT_UDR0:
+ .dw PFA_DOVARIABLE
+PFA_UDR0:
+ .dw 198
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR0A:
+ .dw $ff06
+ .db "UCSR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0A
+XT_UCSR0A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0A:
+ .dw 192
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR0B:
+ .dw $ff06
+ .db "UCSR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0B
+XT_UCSR0B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0B:
+ .dw 193
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR0C:
+ .dw $ff06
+ .db "UCSR0C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0C
+XT_UCSR0C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0C:
+ .dw 194
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Bytes
+VE_UBRR0:
+ .dw $ff05
+ .db "UBRR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR0
+XT_UBRR0:
+ .dw PFA_DOVARIABLE
+PFA_UBRR0:
+ .dw 196
+
+.endif
+.if WANT_CPU == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw 95
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer
+VE_SP:
+ .dw $ff02
+ .db "SP"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SP
+XT_SP:
+ .dw PFA_DOVARIABLE
+PFA_SP:
+ .dw 93
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw 85
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Status Register
+VE_MCUSR:
+ .dw $ff05
+ .db "MCUSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUSR
+XT_MCUSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUSR:
+ .dw 84
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Calibration Value
+VE_OSCCAL:
+ .dw $ff06
+ .db "OSCCAL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSCCAL
+XT_OSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_OSCCAL:
+ .dw 102
+; ( -- addr ) System Constant
+; R( -- )
+; Clock Prescale Register
+VE_CLKPR:
+ .dw $ff05
+ .db "CLKPR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKPR
+XT_CLKPR:
+ .dw PFA_DOVARIABLE
+PFA_CLKPR:
+ .dw 97
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register
+VE_PRR:
+ .dw $ff03
+ .db "PRR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR
+XT_PRR:
+ .dw PFA_DOVARIABLE
+PFA_PRR:
+ .dw 100
+; ( -- addr ) System Constant
+; R( -- )
+; Sleep Mode Control Register
+VE_SMCR:
+ .dw $ff04
+ .db "SMCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SMCR
+XT_SMCR:
+ .dw PFA_DOVARIABLE
+PFA_SMCR:
+ .dw 83
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 2
+VE_GPIOR2:
+ .dw $ff06
+ .db "GPIOR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR2
+XT_GPIOR2:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR2:
+ .dw 75
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 1
+VE_GPIOR1:
+ .dw $ff06
+ .db "GPIOR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR1
+XT_GPIOR1:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR1:
+ .dw 74
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 0
+VE_GPIOR0:
+ .dw $ff06
+ .db "GPIOR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR0
+XT_GPIOR0:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR0:
+ .dw 62
+
+.endif
+.if WANT_JTAG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; On-Chip Debug Related Register in I/O Memory
+VE_OCDR:
+ .dw $ff04
+ .db "OCDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCDR
+XT_OCDR:
+ .dw PFA_DOVARIABLE
+PFA_OCDR:
+ .dw 81
+
+.endif
+.if WANT_LCD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 18
+VE_LCDDR18:
+ .dw $ff07
+ .db "LCDDR18",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR18
+XT_LCDDR18:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR18:
+ .dw 254
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 17
+VE_LCDDR17:
+ .dw $ff07
+ .db "LCDDR17",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR17
+XT_LCDDR17:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR17:
+ .dw 253
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 16
+VE_LCDDR16:
+ .dw $ff07
+ .db "LCDDR16",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR16
+XT_LCDDR16:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR16:
+ .dw 252
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 15
+VE_LCDDR15:
+ .dw $ff07
+ .db "LCDDR15",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR15
+XT_LCDDR15:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR15:
+ .dw 251
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 13
+VE_LCDDR13:
+ .dw $ff07
+ .db "LCDDR13",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR13
+XT_LCDDR13:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR13:
+ .dw 249
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 12
+VE_LCDDR12:
+ .dw $ff07
+ .db "LCDDR12",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR12
+XT_LCDDR12:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR12:
+ .dw 248
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 11
+VE_LCDDR11:
+ .dw $ff07
+ .db "LCDDR11",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR11
+XT_LCDDR11:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR11:
+ .dw 247
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 10
+VE_LCDDR10:
+ .dw $ff07
+ .db "LCDDR10",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR10
+XT_LCDDR10:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR10:
+ .dw 246
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 8
+VE_LCDDR8:
+ .dw $ff06
+ .db "LCDDR8"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR8
+XT_LCDDR8:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR8:
+ .dw 244
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 7
+VE_LCDDR7:
+ .dw $ff06
+ .db "LCDDR7"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR7
+XT_LCDDR7:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR7:
+ .dw 243
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 6
+VE_LCDDR6:
+ .dw $ff06
+ .db "LCDDR6"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR6
+XT_LCDDR6:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR6:
+ .dw 242
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 5
+VE_LCDDR5:
+ .dw $ff06
+ .db "LCDDR5"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR5
+XT_LCDDR5:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR5:
+ .dw 241
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 3
+VE_LCDDR3:
+ .dw $ff06
+ .db "LCDDR3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR3
+XT_LCDDR3:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR3:
+ .dw 239
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 2
+VE_LCDDR2:
+ .dw $ff06
+ .db "LCDDR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR2
+XT_LCDDR2:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR2:
+ .dw 238
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 1
+VE_LCDDR1:
+ .dw $ff06
+ .db "LCDDR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR1
+XT_LCDDR1:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR1:
+ .dw 237
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 0
+VE_LCDDR0:
+ .dw $ff06
+ .db "LCDDR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR0
+XT_LCDDR0:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR0:
+ .dw 236
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Contrast Control Register
+VE_LCDCCR:
+ .dw $ff06
+ .db "LCDCCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDCCR
+XT_LCDCCR:
+ .dw PFA_DOVARIABLE
+PFA_LCDCCR:
+ .dw 231
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Frame Rate Register
+VE_LCDFRR:
+ .dw $ff06
+ .db "LCDFRR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDFRR
+XT_LCDFRR:
+ .dw PFA_DOVARIABLE
+PFA_LCDFRR:
+ .dw 230
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Control and Status Register B
+VE_LCDCRB:
+ .dw $ff06
+ .db "LCDCRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDCRB
+XT_LCDCRB:
+ .dw PFA_DOVARIABLE
+PFA_LCDCRB:
+ .dw 229
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Control Register A
+VE_LCDCRA:
+ .dw $ff06
+ .db "LCDCRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDCRA
+XT_LCDCRA:
+ .dw PFA_DOVARIABLE
+PFA_LCDCRA:
+ .dw 228
+
+.endif
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register A
+VE_EICRA:
+ .dw $ff05
+ .db "EICRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRA
+XT_EICRA:
+ .dw PFA_DOVARIABLE
+PFA_EICRA:
+ .dw 105
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Mask Register
+VE_EIMSK:
+ .dw $ff05
+ .db "EIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIMSK
+XT_EIMSK:
+ .dw PFA_DOVARIABLE
+PFA_EIMSK:
+ .dw 61
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Flag Register
+VE_EIFR:
+ .dw $ff04
+ .db "EIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIFR
+XT_EIFR:
+ .dw PFA_DOVARIABLE
+PFA_EIFR:
+ .dw 60
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 1
+VE_PCMSK1:
+ .dw $ff06
+ .db "PCMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK1
+XT_PCMSK1:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK1:
+ .dw 108
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 0
+VE_PCMSK0:
+ .dw $ff06
+ .db "PCMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK0
+XT_PCMSK0:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK0:
+ .dw 107
+
+.endif
+.if WANT_EEPROM == 1
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Read/Write Access Bytes
+VE_EEAR:
+ .dw $ff04
+ .db "EEAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEAR
+XT_EEAR:
+ .dw PFA_DOVARIABLE
+PFA_EEAR:
+ .dw 65
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw 64
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw 63
+
+.endif
+.if WANT_PORTA == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Register
+VE_PORTA:
+ .dw $ff05
+ .db "PORTA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTA
+XT_PORTA:
+ .dw PFA_DOVARIABLE
+PFA_PORTA:
+ .dw 34
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Direction Register
+VE_DDRA:
+ .dw $ff04
+ .db "DDRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRA
+XT_DDRA:
+ .dw PFA_DOVARIABLE
+PFA_DDRA:
+ .dw 33
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Input Pins
+VE_PINA:
+ .dw $ff04
+ .db "PINA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINA
+XT_PINA:
+ .dw PFA_DOVARIABLE
+PFA_PINA:
+ .dw 32
+
+.endif
+.if WANT_PORTB == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw 37
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw 36
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw 35
+
+.endif
+.if WANT_PORTC == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Register
+VE_PORTC:
+ .dw $ff05
+ .db "PORTC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTC
+XT_PORTC:
+ .dw PFA_DOVARIABLE
+PFA_PORTC:
+ .dw 40
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Direction Register
+VE_DDRC:
+ .dw $ff04
+ .db "DDRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRC
+XT_DDRC:
+ .dw PFA_DOVARIABLE
+PFA_DDRC:
+ .dw 39
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Input Pins
+VE_PINC:
+ .dw $ff04
+ .db "PINC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINC
+XT_PINC:
+ .dw PFA_DOVARIABLE
+PFA_PINC:
+ .dw 38
+
+.endif
+.if WANT_PORTD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw 43
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw 42
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw 41
+
+.endif
+.if WANT_PORTE == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port E
+VE_PORTE:
+ .dw $ff05
+ .db "PORTE",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTE
+XT_PORTE:
+ .dw PFA_DOVARIABLE
+PFA_PORTE:
+ .dw 46
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port E
+VE_DDRE:
+ .dw $ff04
+ .db "DDRE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRE
+XT_DDRE:
+ .dw PFA_DOVARIABLE
+PFA_DDRE:
+ .dw 45
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port E
+VE_PINE:
+ .dw $ff04
+ .db "PINE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINE
+XT_PINE:
+ .dw PFA_DOVARIABLE
+PFA_PINE:
+ .dw 44
+
+.endif
+.if WANT_PORTF == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port F
+VE_PORTF:
+ .dw $ff05
+ .db "PORTF",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTF
+XT_PORTF:
+ .dw PFA_DOVARIABLE
+PFA_PORTF:
+ .dw 49
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port F
+VE_DDRF:
+ .dw $ff04
+ .db "DDRF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRF
+XT_DDRF:
+ .dw PFA_DOVARIABLE
+PFA_DDRF:
+ .dw 48
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port F
+VE_PINF:
+ .dw $ff04
+ .db "PINF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINF
+XT_PINF:
+ .dw PFA_DOVARIABLE
+PFA_PINF:
+ .dw 47
+
+.endif
+.if WANT_PORTG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Data Register
+VE_PORTG:
+ .dw $ff05
+ .db "PORTG",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTG
+XT_PORTG:
+ .dw PFA_DOVARIABLE
+PFA_PORTG:
+ .dw 52
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Data Direction Register
+VE_DDRG:
+ .dw $ff04
+ .db "DDRG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRG
+XT_DDRG:
+ .dw PFA_DOVARIABLE
+PFA_DDRG:
+ .dw 51
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Input Pins
+VE_PING:
+ .dw $ff04
+ .db "PING"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PING
+XT_PING:
+ .dw PFA_DOVARIABLE
+PFA_PING:
+ .dw 50
+
+.endif
+.if WANT_TIMER_COUNTER_0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Control Register
+VE_TCCR0A:
+ .dw $ff06
+ .db "TCCR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0A
+XT_TCCR0A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0A:
+ .dw 68
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw 70
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0A:
+ .dw $ff05
+ .db "OCR0A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0A
+XT_OCR0A:
+ .dw PFA_DOVARIABLE
+PFA_OCR0A:
+ .dw 71
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Mask Register
+VE_TIMSK0:
+ .dw $ff06
+ .db "TIMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK0
+XT_TIMSK0:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK0:
+ .dw 110
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Flag register
+VE_TIFR0:
+ .dw $ff05
+ .db "TIFR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR0
+XT_TIFR0:
+ .dw PFA_DOVARIABLE
+PFA_TIFR0:
+ .dw 53
+; ( -- addr ) System Constant
+; R( -- )
+; General Timer/Control Register
+VE_GTCCR:
+ .dw $ff05
+ .db "GTCCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GTCCR
+XT_GTCCR:
+ .dw PFA_DOVARIABLE
+PFA_GTCCR:
+ .dw 67
+
+.endif
+.if WANT_TIMER_COUNTER_1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw 128
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw 129
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter 1 Control Register C
+VE_TCCR1C:
+ .dw $ff06
+ .db "TCCR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1C
+XT_TCCR1C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1C:
+ .dw 130
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Bytes
+VE_TCNT1:
+ .dw $ff05
+ .db "TCNT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1
+XT_TCNT1:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1:
+ .dw 132
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register A Bytes
+VE_OCR1A:
+ .dw $ff05
+ .db "OCR1A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1A
+XT_OCR1A:
+ .dw PFA_DOVARIABLE
+PFA_OCR1A:
+ .dw 136
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register B Bytes
+VE_OCR1B:
+ .dw $ff05
+ .db "OCR1B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1B
+XT_OCR1B:
+ .dw PFA_DOVARIABLE
+PFA_OCR1B:
+ .dw 138
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Bytes
+VE_ICR1:
+ .dw $ff04
+ .db "ICR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1
+XT_ICR1:
+ .dw PFA_DOVARIABLE
+PFA_ICR1:
+ .dw 134
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Mask Register
+VE_TIMSK1:
+ .dw $ff06
+ .db "TIMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK1
+XT_TIMSK1:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK1:
+ .dw 111
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Flag register
+VE_TIFR1:
+ .dw $ff05
+ .db "TIFR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR1
+XT_TIFR1:
+ .dw PFA_DOVARIABLE
+PFA_TIFR1:
+ .dw 54
+
+.endif
+.if WANT_TIMER_COUNTER_2 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register
+VE_TCCR2A:
+ .dw $ff06
+ .db "TCCR2A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2A
+XT_TCCR2A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2A:
+ .dw 176
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2
+VE_TCNT2:
+ .dw $ff05
+ .db "TCNT2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT2
+XT_TCNT2:
+ .dw PFA_DOVARIABLE
+PFA_TCNT2:
+ .dw 178
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register
+VE_OCR2A:
+ .dw $ff05
+ .db "OCR2A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2A
+XT_OCR2A:
+ .dw PFA_DOVARIABLE
+PFA_OCR2A:
+ .dw 179
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Interrupt Mask register
+VE_TIMSK2:
+ .dw $ff06
+ .db "TIMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK2
+XT_TIMSK2:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK2:
+ .dw 112
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Interrupt Flag Register
+VE_TIFR2:
+ .dw $ff05
+ .db "TIFR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR2
+XT_TIFR2:
+ .dw PFA_DOVARIABLE
+PFA_TIFR2:
+ .dw 55
+; ( -- addr ) System Constant
+; R( -- )
+; Asynchronous Status Register
+VE_ASSR:
+ .dw $ff04
+ .db "ASSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ASSR
+XT_ASSR:
+ .dw PFA_DOVARIABLE
+PFA_ASSR:
+ .dw 182
+
+.endif
+.if WANT_WATCHDOG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCR:
+ .dw $ff05
+ .db "WDTCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCR
+XT_WDTCR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCR:
+ .dw 96
+
+.endif
+.if WANT_BOOT_LOAD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control Register
+VE_SPMCSR:
+ .dw $ff06
+ .db "SPMCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCSR
+XT_SPMCSR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCSR:
+ .dw 87
+
+.endif
diff --git a/amforth-6.5/avr8/devices/atmega649a/device.py b/amforth-6.5/avr8/devices/atmega649a/device.py
new file mode 100644
index 0000000..117cda4
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega649a/device.py
@@ -0,0 +1,352 @@
+# Generated Automatically
+
+# Partname ATmega649A
+
+MCUREGS = {
+# Interrupt Vectors
+ 'INT0Addr' : '#2', # External Interrupt Request 0
+ 'PCINT0Addr' : '#4', # Pin Change Interrupt Request 0
+ 'PCINT1Addr' : '#6', # Pin Change Interrupt Request 1
+ 'TIMER2_COMPAddr' : '#8', # Timer/Counter2 Compare Match
+ 'TIMER2_OVFAddr' : '#10', # Timer/Counter2 Overflow
+ 'TIMER1_CAPTAddr' : '#12', # Timer/Counter1 Capture Event
+ 'TIMER1_COMPAAddr' : '#14', # Timer/Counter1 Compare Match A
+ 'TIMER1_COMPBAddr' : '#16', # Timer/Counter Compare Match B
+ 'TIMER1_OVFAddr' : '#18', # Timer/Counter1 Overflow
+ 'TIMER0_COMPAddr' : '#20', # Timer/Counter0 Compare Match
+ 'TIMER0_OVFAddr' : '#22', # Timer/Counter0 Overflow
+ 'SPI_STCAddr' : '#24', # SPI Serial Transfer Complete
+ 'USART0_RXAddr' : '#26', # USART0, Rx Complete
+ 'USART0_UDREAddr' : '#28', # USART0 Data register Empty
+ 'USART0_TXAddr' : '#30', # USART0, Tx Complete
+ 'USI_STARTAddr' : '#32', # USI Start Condition
+ 'USI_OVERFLOWAddr' : '#34', # USI Overflow
+ 'ANALOG_COMPAddr' : '#36', # Analog Comparator
+ 'ADCAddr' : '#38', # ADC Conversion Complete
+ 'EE_READYAddr' : '#40', # EEPROM Ready
+ 'SPM_READYAddr' : '#42', # Store Program Memory Read
+ 'LCDAddr' : '#44', # LCD Start of Frame
+
+# Module AD_CONVERTER
+ 'ADMUX' : '$7c', # The ADC multiplexer Selection
+ 'ADMUX_REFS': '$c0', # Reference Selection Bits
+ 'ADMUX_ADLAR': '$20', # Left Adjust Result
+ 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
+ 'ADCSRA' : '$7a', # The ADC Control and Status reg
+ 'ADCSRA_ADEN': '$80', # ADC Enable
+ 'ADCSRA_ADSC': '$40', # ADC Start Conversion
+ 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
+ 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
+ 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
+ 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
+ 'ADC' : '$78', # ADC Data Register Bytes
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Sources
+ 'DIDR0' : '$7e', # Digital Input Disable Register
+ 'DIDR0_ADC7D': '$80', # ADC7 Digital input Disable
+ 'DIDR0_ADC6D': '$40', # ADC6 Digital input Disable
+ 'DIDR0_ADC5D': '$20', # ADC5 Digital input Disable
+ 'DIDR0_ADC4D': '$10', # ADC4 Digital input Disable
+ 'DIDR0_ADC3D': '$8', # ADC3 Digital input Disable
+ 'DIDR0_ADC2D': '$4', # ADC2 Digital input Disable
+ 'DIDR0_ADC1D': '$2', # ADC1 Digital input Disable
+ 'DIDR0_ADC0D': '$1', # ADC0 Digital input Disable
+
+# Module ANALOG_COMPARATOR
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
+ 'ACSR' : '$50', # Analog Comparator Control And
+ 'ACSR_ACD': '$80', # Analog Comparator Disable
+ 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
+ 'ACSR_ACO': '$20', # Analog Compare Output
+ 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
+ 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
+ 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
+ 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
+ 'DIDR1' : '$7f', # Digital Input Disable Register
+ 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
+ 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
+
+# Module SPI
+ 'SPCR' : '$4c', # SPI Control Register
+ 'SPCR_SPIE': '$80', # SPI Interrupt Enable
+ 'SPCR_SPE': '$40', # SPI Enable
+ 'SPCR_DORD': '$20', # Data Order
+ 'SPCR_MSTR': '$10', # Master/Slave Select
+ 'SPCR_CPOL': '$8', # Clock polarity
+ 'SPCR_CPHA': '$4', # Clock Phase
+ 'SPCR_SPR': '$3', # SPI Clock Rate Selects
+ 'SPSR' : '$4d', # SPI Status Register
+ 'SPSR_SPIF': '$80', # SPI Interrupt Flag
+ 'SPSR_WCOL': '$40', # Write Collision Flag
+ 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
+ 'SPDR' : '$4e', # SPI Data Register
+
+# Module USI
+ 'USIDR' : '$ba', # USI Data Register
+ 'USISR' : '$b9', # USI Status Register
+ 'USISR_USISIF': '$80', # Start Condition Interrupt Flag
+ 'USISR_USIOIF': '$40', # Counter Overflow Interrupt Fla
+ 'USISR_USIPF': '$20', # Stop Condition Flag
+ 'USISR_USIDC': '$10', # Data Output Collision
+ 'USISR_USICNT': '$f', # USI Counter Value Bits
+ 'USICR' : '$b8', # USI Control Register
+ 'USICR_USISIE': '$80', # Start Condition Interrupt Enab
+ 'USICR_USIOIE': '$40', # Counter Overflow Interrupt Ena
+ 'USICR_USIWM': '$30', # USI Wire Mode Bits
+ 'USICR_USICS': '$c', # USI Clock Source Select Bits
+ 'USICR_USICLK': '$2', # Clock Strobe
+ 'USICR_USITC': '$1', # Toggle Clock Port Pin
+
+# Module USART0
+ 'UDR0' : '$c6', # USART I/O Data Register
+ 'UCSR0A' : '$c0', # USART Control and Status Regis
+ 'UCSR0A_RXC0': '$80', # USART Receive Complete
+ 'UCSR0A_TXC0': '$40', # USART Transmit Complete
+ 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
+ 'UCSR0A_FE0': '$10', # Framing Error
+ 'UCSR0A_DOR0': '$8', # Data OverRun
+ 'UCSR0A_UPE0': '$4', # USART Parity Error
+ 'UCSR0A_U2X0': '$2', # Double the USART Transmission
+ 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
+ 'UCSR0B' : '$c1', # USART Control and Status Regis
+ 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
+ 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
+ 'UCSR0B_UDRIE0': '$20', # USART Data Register Empty Inte
+ 'UCSR0B_RXEN0': '$10', # Receiver Enable
+ 'UCSR0B_TXEN0': '$8', # Transmitter Enable
+ 'UCSR0B_UCSZ02': '$4', # Character Size
+ 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
+ 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
+ 'UCSR0C' : '$c2', # USART Control and Status Regis
+ 'UCSR0C_UMSEL0': '$40', # USART Mode Select
+ 'UCSR0C_UPM0': '$30', # Parity Mode Bits
+ 'UCSR0C_USBS0': '$8', # Stop Bit Select
+ 'UCSR0C_UCSZ0': '$6', # Character Size
+ 'UCSR0C_UCPOL0': '$1', # Clock Polarity
+ 'UBRR0' : '$c4', # USART Baud Rate Register Byte
+
+# Module CPU
+ 'SREG' : '$5f', # Status Register
+ 'SREG_I': '$80', # Global Interrupt Enable
+ 'SREG_T': '$40', # Bit Copy Storage
+ 'SREG_H': '$20', # Half Carry Flag
+ 'SREG_S': '$10', # Sign Bit
+ 'SREG_V': '$8', # Two's Complement Overflow Flag
+ 'SREG_N': '$4', # Negative Flag
+ 'SREG_Z': '$2', # Zero Flag
+ 'SREG_C': '$1', # Carry Flag
+ 'SP' : '$5d', # Stack Pointer
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_PUD': '$10', # Pull-up disable
+ 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
+ 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+ 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
+ 'MCUSR_BORF': '$4', # Brown-out Reset Flag
+ 'MCUSR_EXTRF': '$2', # External Reset Flag
+ 'MCUSR_PORF': '$1', # Power-on reset flag
+ 'OSCCAL' : '$66', # Oscillator Calibration Value
+ 'CLKPR' : '$61', # Clock Prescale Register
+ 'CLKPR_CLKPCE': '$80', # Clock Prescaler Change Enable
+ 'CLKPR_CLKPS': '$f', # Clock Prescaler Select Bits
+ 'PRR' : '$64', # Power Reduction Register
+ 'PRR_PRLCD': '$10', # Power Reduction LCD
+ 'PRR_PRTIM1': '$8', # Power Reduction Timer/Counter1
+ 'PRR_PRSPI': '$4', # Power Reduction Serial Periphe
+ 'PRR_PRUSART0': '$2', # Power Reduction USART
+ 'PRR_PRADC': '$1', # Power Reduction ADC
+ 'SMCR' : '$53', # Sleep Mode Control Register
+ 'SMCR_SM': '$e', # Sleep Mode Select bits
+ 'SMCR_SE': '$1', # Sleep Enable
+ 'GPIOR2' : '$4b', # General Purpose IO Register 2
+ 'GPIOR1' : '$4a', # General Purpose IO Register 1
+ 'GPIOR0' : '$3e', # General Purpose IO Register 0
+
+# Module JTAG
+ 'OCDR' : '$51', # On-Chip Debug Related Register
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_JTD': '$80', # JTAG Interface Disable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+
+# Module LCD
+ 'LCDDR18' : '$fe', # LCD Data Register 18
+ 'LCDDR17' : '$fd', # LCD Data Register 17
+ 'LCDDR16' : '$fc', # LCD Data Register 16
+ 'LCDDR15' : '$fb', # LCD Data Register 15
+ 'LCDDR13' : '$f9', # LCD Data Register 13
+ 'LCDDR12' : '$f8', # LCD Data Register 12
+ 'LCDDR11' : '$f7', # LCD Data Register 11
+ 'LCDDR10' : '$f6', # LCD Data Register 10
+ 'LCDDR8' : '$f4', # LCD Data Register 8
+ 'LCDDR7' : '$f3', # LCD Data Register 7
+ 'LCDDR6' : '$f2', # LCD Data Register 6
+ 'LCDDR5' : '$f1', # LCD Data Register 5
+ 'LCDDR3' : '$ef', # LCD Data Register 3
+ 'LCDDR2' : '$ee', # LCD Data Register 2
+ 'LCDDR1' : '$ed', # LCD Data Register 1
+ 'LCDDR0' : '$ec', # LCD Data Register 0
+ 'LCDCCR' : '$e7', # LCD Contrast Control Register
+ 'LCDFRR' : '$e6', # LCD Frame Rate Register
+ 'LCDFRR_LCDPS': '$70', # LCD Prescaler Selects
+ 'LCDFRR_LCDCD': '$7', # LCD Clock Dividers
+ 'LCDCRB' : '$e5', # LCD Control and Status Registe
+ 'LCDCRB_LCDCS': '$80', # LCD CLock Select
+ 'LCDCRB_LCD2B': '$40', # LCD 1/2 Bias Select
+ 'LCDCRB_LCDMUX': '$30', # LCD Mux Selects
+ 'LCDCRB_LCDPM': '$f', # LCD Port Masks
+ 'LCDCRA' : '$e4', # LCD Control Register A
+ 'LCDCRA_LCDEN': '$80', # LCD Enable
+ 'LCDCRA_LCDAB': '$40', # LCD A or B waveform
+ 'LCDCRA_LCDIF': '$10', # LCD Interrupt Flag
+ 'LCDCRA_LCDIE': '$8', # LCD Interrupt Enable
+ 'LCDCRA_LCDBL': '$1', # LCD Blanking
+
+# Module EXTERNAL_INTERRUPT
+ 'EICRA' : '$69', # External Interrupt Control Reg
+ 'EICRA_ISC01': '$2', # External Interrupt Sense Contr
+ 'EICRA_ISC00': '$1', # External Interrupt Sense Contr
+ 'EIMSK' : '$3d', # External Interrupt Mask Regist
+ 'EIMSK_PCIE': '$f0', # Pin Change Interrupt Enables
+ 'EIMSK_INT0': '$1', # External Interrupt Request 0 E
+ 'EIFR' : '$3c', # External Interrupt Flag Regist
+ 'EIFR_PCIF': '$f0', # Pin Change Interrupt Flags
+ 'EIFR_INTF0': '$1', # External Interrupt Flag 0
+ 'PCMSK1' : '$6c', # Pin Change Mask Register 1
+ 'PCMSK0' : '$6b', # Pin Change Mask Register 0
+
+# Module EEPROM
+ 'EEAR' : '$41', # EEPROM Read/Write Access Byte
+ 'EEDR' : '$40', # EEPROM Data Register
+ 'EECR' : '$3f', # EEPROM Control Register
+ 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
+ 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
+ 'EECR_EEWE': '$2', # EEPROM Write Enable
+ 'EECR_EERE': '$1', # EEPROM Read Enable
+
+# Module PORTA
+ 'PORTA' : '$22', # Port A Data Register
+ 'DDRA' : '$21', # Port A Data Direction Register
+ 'PINA' : '$20', # Port A Input Pins
+
+# Module PORTB
+ 'PORTB' : '$25', # Port B Data Register
+ 'DDRB' : '$24', # Port B Data Direction Register
+ 'PINB' : '$23', # Port B Input Pins
+
+# Module PORTC
+ 'PORTC' : '$28', # Port C Data Register
+ 'DDRC' : '$27', # Port C Data Direction Register
+ 'PINC' : '$26', # Port C Input Pins
+
+# Module PORTD
+ 'PORTD' : '$2b', # Port D Data Register
+ 'DDRD' : '$2a', # Port D Data Direction Register
+ 'PIND' : '$29', # Port D Input Pins
+
+# Module PORTE
+ 'PORTE' : '$2e', # Data Register, Port E
+ 'DDRE' : '$2d', # Data Direction Register, Port
+ 'PINE' : '$2c', # Input Pins, Port E
+
+# Module PORTF
+ 'PORTF' : '$31', # Data Register, Port F
+ 'DDRF' : '$30', # Data Direction Register, Port
+ 'PINF' : '$2f', # Input Pins, Port F
+
+# Module PORTG
+ 'PORTG' : '$34', # Port G Data Register
+ 'DDRG' : '$33', # Port G Data Direction Register
+ 'PING' : '$32', # Port G Input Pins
+
+# Module TIMER_COUNTER_0
+ 'TCCR0A' : '$44', # Timer/Counter0 Control Registe
+ 'TCCR0A_FOC0A': '$80', # Force Output Compare
+ 'TCCR0A_WGM00': '$40', # Waveform Generation Mode 0
+ 'TCCR0A_COM0A': '$30', # Compare Match Output Modes
+ 'TCCR0A_WGM01': '$8', # Waveform Generation Mode 1
+ 'TCCR0A_CS0': '$7', # Clock Selects
+ 'TCNT0' : '$46', # Timer/Counter0
+ 'OCR0A' : '$47', # Timer/Counter0 Output Compare
+ 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
+ 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
+ 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
+ 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
+ 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
+ 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Control Register
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSR310': '$1', # Prescaler Reset Timer/Counter1
+
+# Module TIMER_COUNTER_1
+ 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
+ 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
+ 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
+ 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
+ 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
+ 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
+ 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
+ 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
+ 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
+ 'TCCR1C' : '$82', # Timer/Counter 1 Control Regist
+ 'TCCR1C_FOC1A': '$80', # Force Output Compare 1A
+ 'TCCR1C_FOC1B': '$40', # Force Output Compare 1B
+ 'TCNT1' : '$84', # Timer/Counter1 Bytes
+ 'OCR1A' : '$88', # Timer/Counter1 Output Compare
+ 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
+ 'ICR1' : '$86', # Timer/Counter1 Input Capture R
+ 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
+ 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
+ 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
+ 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
+ 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
+ 'TIFR1' : '$36', # Timer/Counter1 Interrupt Flag
+ 'TIFR1_ICF1': '$20', # Input Capture Flag 1
+ 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
+ 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
+ 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
+
+# Module TIMER_COUNTER_2
+ 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
+ 'TCCR2A_FOC2A': '$80', # Force Output Compare A
+ 'TCCR2A_WGM20': '$40', # Waveform Generation Mode
+ 'TCCR2A_COM2A': '$30', # Compare Output Mode bits
+ 'TCCR2A_WGM21': '$8', # Waveform Generation Mode
+ 'TCCR2A_CS2': '$7', # Clock Select bits
+ 'TCNT2' : '$b2', # Timer/Counter2
+ 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
+ 'TIMSK2' : '$70', # Timer/Counter2 Interrupt Mask
+ 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
+ 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
+ 'TIFR2' : '$37', # Timer/Counter2 Interrupt Flag
+ 'TIFR2_OCF2A': '$2', # Timer/Counter2 Output Compare
+ 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_PSR2': '$2', # Prescaler Reset Timer/Counter2
+ 'ASSR' : '$b6', # Asynchronous Status Register
+ 'ASSR_EXCLK': '$10', # Enable External Clock Interrup
+ 'ASSR_AS2': '$8', # AS2: Asynchronous Timer/Counte
+ 'ASSR_TCN2UB': '$4', # TCN2UB: Timer/Counter2 Update
+ 'ASSR_OCR2UB': '$2', # Output Compare Register2 Updat
+ 'ASSR_TCR2UB': '$1', # TCR2UB: Timer/Counter Control
+
+# Module WATCHDOG
+ 'WDTCR' : '$60', # Watchdog Timer Control Registe
+ 'WDTCR_WDCE': '$10', # Watchdog Change Enable
+ 'WDTCR_WDE': '$8', # Watch Dog Enable
+ 'WDTCR_WDP': '$7', # Watch Dog Timer Prescaler bits
+
+# Module BOOT_LOAD
+ 'SPMCSR' : '$57', # Store Program Memory Control R
+ 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
+ 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
+ 'SPMCSR_RWWSRE': '$10', # Read While Write section read
+ 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
+ 'SPMCSR_PGWRT': '$4', # Page Write
+ 'SPMCSR_PGERS': '$2', # Page Erase
+ 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
+
+ '__amforth_dummy':'0'
+}
diff --git a/amforth-6.5/avr8/devices/atmega649a/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega649a/words/no-jtag.asm
new file mode 100644
index 0000000..352a4bb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega649a/words/no-jtag.asm
@@ -0,0 +1,14 @@
+; ( -- )
+; ( -- )
+; MCU
+; disable jtag at runtime
+VE_NOJTAG:
+ .dw $FF05
+ .db "-jtag",0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOJTAG
+XT_NOJTAG:
+ .dw PFA_NOJTAG
+PFA_NOJTAG:
+
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega649a/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega649a/words/no-wdt.asm
new file mode 100644
index 0000000..4a12261
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega649a/words/no-wdt.asm
@@ -0,0 +1,22 @@
+; ( -- )
+; MCU
+; disable watch dog timer at runtime
+VE_NOWDT:
+ .dw $ff04
+ .db "-wdt"
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOWDT
+XT_NOWDT:
+ .dw PFA_NOWDT
+PFA_NOWDT:
+
+; Reset WDT
+ wdr
+; Write logical one to WDTOE and WDE
+ in_ temp1, WDTCR
+ ori temp1, (1<<WDTOE)|(1<<WDE)
+ out WDTCR, temp1
+; Turn off WDT
+ ldi temp1, (0<<WDE)
+ out_ WDTCR, temp1
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega649a/words/sleep.asm b/amforth-6.5/avr8/devices/atmega649a/words/sleep.asm
new file mode 100644
index 0000000..256249c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega649a/words/sleep.asm
@@ -0,0 +1,19 @@
+; ( mode -- )
+; MCU
+; put the controller into the specified sleep mode
+VE_SLEEP:
+ .dw $ff05
+ .db "sleep", 0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_SLEEP
+XT_SLEEP:
+ .dw PFA_SLEEP
+PFA_SLEEP:
+ andi tosl, 7 ; leave only legal mode bits
+ lsl tosl ; move to correct location (bits 3-1)
+ ori tosl, 1 ; set the SE bit
+ out_ SMCR, tosl ; set the sleep config
+ sleep ; nighty-night
+ out_ SMCR, zerol ; 0 protects against accidental sleeps
+ loadtos ; pop argument from stack
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega649p/atmega649p.frt b/amforth-6.5/avr8/devices/atmega649p/atmega649p.frt
new file mode 100644
index 0000000..219388d
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega649p/atmega649p.frt
@@ -0,0 +1,318 @@
+\ Partname: ATmega649P
+\ generated automatically
+
+\ AD_CONVERTER
+&124 constant ADMUX \ The ADC multiplexer Selection Register
+ $C0 constant ADMUX_REFS \ Reference Selection Bits
+ $20 constant ADMUX_ADLAR \ Left Adjust Result
+ $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
+&122 constant ADCSRA \ The ADC Control and Status register
+ $80 constant ADCSRA_ADEN \ ADC Enable
+ $40 constant ADCSRA_ADSC \ ADC Start Conversion
+ $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
+ $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
+ $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
+ $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
+&120 constant ADC \ ADC Data Register Bytes
+&123 constant ADCSRB \ ADC Control and Status Register B
+ $07 constant ADCSRB_ADTS \ ADC Auto Trigger Sources
+&126 constant DIDR0 \ Digital Input Disable Register 0
+ $80 constant DIDR0_ADC7D \ ADC7 Digital input Disable
+ $40 constant DIDR0_ADC6D \ ADC6 Digital input Disable
+ $20 constant DIDR0_ADC5D \ ADC5 Digital input Disable
+ $10 constant DIDR0_ADC4D \ ADC4 Digital input Disable
+ $08 constant DIDR0_ADC3D \ ADC3 Digital input Disable
+ $04 constant DIDR0_ADC2D \ ADC2 Digital input Disable
+ $02 constant DIDR0_ADC1D \ ADC1 Digital input Disable
+ $01 constant DIDR0_ADC0D \ ADC0 Digital input Disable
+\ ANALOG_COMPARATOR
+&80 constant ACSR \ Analog Comparator Control And Status Register
+ $80 constant ACSR_ACD \ Analog Comparator Disable
+ $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
+ $20 constant ACSR_ACO \ Analog Compare Output
+ $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
+ $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
+ $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
+ $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
+&127 constant DIDR1 \ Digital Input Disable Register 1
+ $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
+ $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
+\ SPI
+&76 constant SPCR \ SPI Control Register
+ $80 constant SPCR_SPIE \ SPI Interrupt Enable
+ $40 constant SPCR_SPE \ SPI Enable
+ $20 constant SPCR_DORD \ Data Order
+ $10 constant SPCR_MSTR \ Master/Slave Select
+ $08 constant SPCR_CPOL \ Clock polarity
+ $04 constant SPCR_CPHA \ Clock Phase
+ $03 constant SPCR_SPR \ SPI Clock Rate Selects
+&77 constant SPSR \ SPI Status Register
+ $80 constant SPSR_SPIF \ SPI Interrupt Flag
+ $40 constant SPSR_WCOL \ Write Collision Flag
+ $01 constant SPSR_SPI2X \ Double SPI Speed Bit
+&78 constant SPDR \ SPI Data Register
+\ USI
+&186 constant USIDR \ USI Data Register
+&185 constant USISR \ USI Status Register
+ $80 constant USISR_USISIF \ Start Condition Interrupt Flag
+ $40 constant USISR_USIOIF \ Counter Overflow Interrupt Flag
+ $20 constant USISR_USIPF \ Stop Condition Flag
+ $10 constant USISR_USIDC \ Data Output Collision
+ $0F constant USISR_USICNT \ USI Counter Value Bits
+&184 constant USICR \ USI Control Register
+ $80 constant USICR_USISIE \ Start Condition Interrupt Enable
+ $40 constant USICR_USIOIE \ Counter Overflow Interrupt Enable
+ $30 constant USICR_USIWM \ USI Wire Mode Bits
+ $0C constant USICR_USICS \ USI Clock Source Select Bits
+ $02 constant USICR_USICLK \ Clock Strobe
+ $01 constant USICR_USITC \ Toggle Clock Port Pin
+\ USART0
+&198 constant UDR0 \ USART I/O Data Register
+&192 constant UCSR0A \ USART Control and Status Register A
+ $80 constant UCSR0A_RXC0 \ USART Receive Complete
+ $40 constant UCSR0A_TXC0 \ USART Transmit Complete
+ $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
+ $10 constant UCSR0A_FE0 \ Framing Error
+ $08 constant UCSR0A_DOR0 \ Data OverRun
+ $04 constant UCSR0A_UPE0 \ USART Parity Error
+ $02 constant UCSR0A_U2X0 \ Double the USART Transmission Speed
+ $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
+&193 constant UCSR0B \ USART Control and Status Register B
+ $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
+ $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
+ $20 constant UCSR0B_UDRIE0 \ USART Data Register Empty Interrupt Enable
+ $10 constant UCSR0B_RXEN0 \ Receiver Enable
+ $08 constant UCSR0B_TXEN0 \ Transmitter Enable
+ $04 constant UCSR0B_UCSZ02 \ Character Size
+ $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
+ $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
+&194 constant UCSR0C \ USART Control and Status Register C
+ $40 constant UCSR0C_UMSEL0 \ USART Mode Select
+ $30 constant UCSR0C_UPM0 \ Parity Mode Bits
+ $08 constant UCSR0C_USBS0 \ Stop Bit Select
+ $06 constant UCSR0C_UCSZ0 \ Character Size
+ $01 constant UCSR0C_UCPOL0 \ Clock Polarity
+&196 constant UBRR0 \ USART Baud Rate Register Bytes
+\ CPU
+&95 constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ $08 constant SREG_V \ Two's Complement Overflow Flag
+ $04 constant SREG_N \ Negative Flag
+ $02 constant SREG_Z \ Zero Flag
+ $01 constant SREG_C \ Carry Flag
+&93 constant SP \ Stack Pointer
+&85 constant MCUCR \ MCU Control Register
+ $10 constant MCUCR_PUD \ Pull-up disable
+ $02 constant MCUCR_IVSEL \ Interrupt Vector Select
+ $01 constant MCUCR_IVCE \ Interrupt Vector Change Enable
+&84 constant MCUSR \ MCU Status Register
+ $10 constant MCUSR_JTRF \ JTAG Reset Flag
+ $08 constant MCUSR_WDRF \ Watchdog Reset Flag
+ $04 constant MCUSR_BORF \ Brown-out Reset Flag
+ $02 constant MCUSR_EXTRF \ External Reset Flag
+ $01 constant MCUSR_PORF \ Power-on reset flag
+&102 constant OSCCAL \ Oscillator Calibration Value
+&97 constant CLKPR \ Clock Prescale Register
+ $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable
+ $0F constant CLKPR_CLKPS \ Clock Prescaler Select Bits
+&100 constant PRR \ Power Reduction Register
+ $10 constant PRR_PRLCD \ Power Reduction LCD
+ $08 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
+ $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
+ $02 constant PRR_PRUSART0 \ Power Reduction USART
+ $01 constant PRR_PRADC \ Power Reduction ADC
+&83 constant SMCR \ Sleep Mode Control Register
+ $0E constant SMCR_SM \ Sleep Mode Select bits
+ $01 constant SMCR_SE \ Sleep Enable
+&75 constant GPIOR2 \ General Purpose IO Register 2
+&74 constant GPIOR1 \ General Purpose IO Register 1
+&62 constant GPIOR0 \ General Purpose IO Register 0
+\ JTAG
+&81 constant OCDR \ On-Chip Debug Related Register in I/O Memory
+\ LCD
+&254 constant LCDDR18 \ LCD Data Register 18
+&253 constant LCDDR17 \ LCD Data Register 17
+&252 constant LCDDR16 \ LCD Data Register 16
+&251 constant LCDDR15 \ LCD Data Register 15
+&249 constant LCDDR13 \ LCD Data Register 13
+&248 constant LCDDR12 \ LCD Data Register 12
+&247 constant LCDDR11 \ LCD Data Register 11
+&246 constant LCDDR10 \ LCD Data Register 10
+&244 constant LCDDR8 \ LCD Data Register 8
+&243 constant LCDDR7 \ LCD Data Register 7
+&242 constant LCDDR6 \ LCD Data Register 6
+&241 constant LCDDR5 \ LCD Data Register 5
+&239 constant LCDDR3 \ LCD Data Register 3
+&238 constant LCDDR2 \ LCD Data Register 2
+&237 constant LCDDR1 \ LCD Data Register 1
+&236 constant LCDDR0 \ LCD Data Register 0
+&231 constant LCDCCR \ LCD Contrast Control Register
+&230 constant LCDFRR \ LCD Frame Rate Register
+ $70 constant LCDFRR_LCDPS \ LCD Prescaler Selects
+ $07 constant LCDFRR_LCDCD \ LCD Clock Dividers
+&229 constant LCDCRB \ LCD Control and Status Register B
+ $80 constant LCDCRB_LCDCS \ LCD CLock Select
+ $40 constant LCDCRB_LCD2B \ LCD 1/2 Bias Select
+ $30 constant LCDCRB_LCDMUX \ LCD Mux Selects
+ $0F constant LCDCRB_LCDPM \ LCD Port Masks
+&228 constant LCDCRA \ LCD Control Register A
+ $80 constant LCDCRA_LCDEN \ LCD Enable
+ $40 constant LCDCRA_LCDAB \ LCD A or B waveform
+ $10 constant LCDCRA_LCDIF \ LCD Interrupt Flag
+ $08 constant LCDCRA_LCDIE \ LCD Interrupt Enable
+ $01 constant LCDCRA_LCDBL \ LCD Blanking
+\ EXTERNAL_INTERRUPT
+&105 constant EICRA \ External Interrupt Control Register A
+ $02 constant EICRA_ISC01 \ External Interrupt Sense Control 0 Bit 1
+ $01 constant EICRA_ISC00 \ External Interrupt Sense Control 0 Bit 0
+&61 constant EIMSK \ External Interrupt Mask Register
+ $F0 constant EIMSK_PCIE \ Pin Change Interrupt Enables
+ $01 constant EIMSK_INT0 \ External Interrupt Request 0 Enable
+&60 constant EIFR \ External Interrupt Flag Register
+ $F0 constant EIFR_PCIF \ Pin Change Interrupt Flags
+ $01 constant EIFR_INTF0 \ External Interrupt Flag 0
+&108 constant PCMSK1 \ Pin Change Mask Register 1
+&107 constant PCMSK0 \ Pin Change Mask Register 0
+\ EEPROM
+&65 constant EEAR \ EEPROM Read/Write Access Bytes
+&64 constant EEDR \ EEPROM Data Register
+&63 constant EECR \ EEPROM Control Register
+ $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
+ $04 constant EECR_EEMWE \ EEPROM Master Write Enable
+ $02 constant EECR_EEWE \ EEPROM Write Enable
+ $01 constant EECR_EERE \ EEPROM Read Enable
+\ PORTA
+&34 constant PORTA \ Port A Data Register
+&33 constant DDRA \ Port A Data Direction Register
+&32 constant PINA \ Port A Input Pins
+\ PORTB
+&37 constant PORTB \ Port B Data Register
+&36 constant DDRB \ Port B Data Direction Register
+&35 constant PINB \ Port B Input Pins
+\ PORTC
+&40 constant PORTC \ Port C Data Register
+&39 constant DDRC \ Port C Data Direction Register
+&38 constant PINC \ Port C Input Pins
+\ PORTD
+&43 constant PORTD \ Port D Data Register
+&42 constant DDRD \ Port D Data Direction Register
+&41 constant PIND \ Port D Input Pins
+\ PORTE
+&46 constant PORTE \ Data Register, Port E
+&45 constant DDRE \ Data Direction Register, Port E
+&44 constant PINE \ Input Pins, Port E
+\ PORTF
+&49 constant PORTF \ Data Register, Port F
+&48 constant DDRF \ Data Direction Register, Port F
+&47 constant PINF \ Input Pins, Port F
+\ PORTG
+&52 constant PORTG \ Port G Data Register
+&51 constant DDRG \ Port G Data Direction Register
+&50 constant PING \ Port G Input Pins
+\ TIMER_COUNTER_0
+&68 constant TCCR0A \ Timer/Counter0 Control Register
+ $80 constant TCCR0A_FOC0A \ Force Output Compare
+ $40 constant TCCR0A_WGM00 \ Waveform Generation Mode 0
+ $30 constant TCCR0A_COM0A \ Compare Match Output Modes
+ $08 constant TCCR0A_WGM01 \ Waveform Generation Mode 1
+ $07 constant TCCR0A_CS0 \ Clock Selects
+&70 constant TCNT0 \ Timer/Counter0
+&71 constant OCR0A \ Timer/Counter0 Output Compare Register
+&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
+ $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match Interrupt Enable
+ $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
+&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
+ $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0
+ $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
+&67 constant GTCCR \ General Timer/Control Register
+ $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
+ $01 constant GTCCR_PSR310 \ Prescaler Reset Timer/Counter1 and Timer/Counter0
+\ TIMER_COUNTER_1
+&128 constant TCCR1A \ Timer/Counter1 Control Register A
+ $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
+ $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
+ $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
+&129 constant TCCR1B \ Timer/Counter1 Control Register B
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
+ $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
+&130 constant TCCR1C \ Timer/Counter 1 Control Register C
+ $80 constant TCCR1C_FOC1A \ Force Output Compare 1A
+ $40 constant TCCR1C_FOC1B \ Force Output Compare 1B
+&132 constant TCNT1 \ Timer/Counter1 Bytes
+&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
+&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
+&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
+&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
+ $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
+ $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
+ $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
+ $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
+&54 constant TIFR1 \ Timer/Counter1 Interrupt Flag register
+ $20 constant TIFR1_ICF1 \ Input Capture Flag 1
+ $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
+ $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
+ $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
+\ TIMER_COUNTER_2
+&176 constant TCCR2A \ Timer/Counter2 Control Register
+ $80 constant TCCR2A_FOC2A \ Force Output Compare A
+ $40 constant TCCR2A_WGM20 \ Waveform Generation Mode
+ $30 constant TCCR2A_COM2A \ Compare Output Mode bits
+ $08 constant TCCR2A_WGM21 \ Waveform Generation Mode
+ $07 constant TCCR2A_CS2 \ Clock Select bits
+&178 constant TCNT2 \ Timer/Counter2
+&179 constant OCR2A \ Timer/Counter2 Output Compare Register
+&112 constant TIMSK2 \ Timer/Counter2 Interrupt Mask register
+ $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match Interrupt Enable
+ $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
+&55 constant TIFR2 \ Timer/Counter2 Interrupt Flag Register
+ $02 constant TIFR2_OCF2A \ Timer/Counter2 Output Compare Flag 2
+ $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
+&182 constant ASSR \ Asynchronous Status Register
+ $10 constant ASSR_EXCLK \ Enable External Clock Interrupt
+ $08 constant ASSR_AS2 \ AS2: Asynchronous Timer/Counter2
+ $04 constant ASSR_TCN2UB \ TCN2UB: Timer/Counter2 Update Busy
+ $02 constant ASSR_OCR2UB \ Output Compare Register2 Update Busy
+ $01 constant ASSR_TCR2UB \ TCR2UB: Timer/Counter Control Register2 Update Busy
+\ WATCHDOG
+&96 constant WDTCR \ Watchdog Timer Control Register
+ $10 constant WDTCR_WDCE \ Watchdog Change Enable
+ $08 constant WDTCR_WDE \ Watch Dog Enable
+ $07 constant WDTCR_WDP \ Watch Dog Timer Prescaler bits
+\ BOOT_LOAD
+&87 constant SPMCSR \ Store Program Memory Control Register
+ $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
+ $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
+ $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
+ $04 constant SPMCSR_PGWRT \ Page Write
+ $02 constant SPMCSR_PGERS \ Page Erase
+ $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
+
+\ Interrupts
+&2 constant INT0Addr \ External Interrupt Request 0
+&4 constant PCINT0Addr \ Pin Change Interrupt Request 0
+&6 constant PCINT1Addr \ Pin Change Interrupt Request 1
+&8 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
+&10 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
+&12 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+&14 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
+&16 constant TIMER1_COMPBAddr \ Timer/Counter Compare Match B
+&18 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+&20 constant TIMER0_COMPAddr \ Timer/Counter0 Compare Match
+&22 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
+&24 constant SPI__STCAddr \ SPI Serial Transfer Complete
+&26 constant USART0__RXAddr \ USART0, Rx Complete
+&28 constant USART0__UDREAddr \ USART0 Data register Empty
+&30 constant USART0__TXAddr \ USART0, Tx Complete
+&32 constant USI_STARTAddr \ USI Start Condition
+&34 constant USI_OVERFLOWAddr \ USI Overflow
+&36 constant ANALOG_COMPAddr \ Analog Comparator
+&38 constant ADCAddr \ ADC Conversion Complete
+&40 constant EE_READYAddr \ EEPROM Ready
+&42 constant SPM_READYAddr \ Store Program Memory Read
+&44 constant LCDAddr \ LCD Start of Frame
diff --git a/amforth-6.5/avr8/devices/atmega649p/device.asm b/amforth-6.5/avr8/devices/atmega649p/device.asm
new file mode 100644
index 0000000..7abac95
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega649p/device.asm
@@ -0,0 +1,109 @@
+; Partname: ATmega649P
+; generated automatically, do not edit
+
+.nolist
+ .include "m649Pdef.inc"
+.list
+
+.equ ramstart = 256
+.equ CELLSIZE = 2
+.macro readflashcell
+ lsl zl
+ rol zh
+ lpm @0, Z+
+ lpm @1, Z+
+.endmacro
+.macro writeflashcell
+ lsl zl
+ rol zh
+.endmacro
+.set WANT_AD_CONVERTER = 0
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_SPI = 0
+.set WANT_USI = 0
+.set WANT_USART0 = 0
+.set WANT_CPU = 0
+.set WANT_JTAG = 0
+.set WANT_LCD = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_EEPROM = 0
+.set WANT_PORTA = 0
+.set WANT_PORTB = 0
+.set WANT_PORTC = 0
+.set WANT_PORTD = 0
+.set WANT_PORTE = 0
+.set WANT_PORTF = 0
+.set WANT_PORTG = 0
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_TIMER_COUNTER_2 = 0
+.set WANT_WATCHDOG = 0
+.set WANT_BOOT_LOAD = 0
+.equ intvecsize = 2 ; please verify; flash size: 65536 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.org 2
+ rcall isr ; External Interrupt Request 0
+.org 4
+ rcall isr ; Pin Change Interrupt Request 0
+.org 6
+ rcall isr ; Pin Change Interrupt Request 1
+.org 8
+ rcall isr ; Timer/Counter2 Compare Match
+.org 10
+ rcall isr ; Timer/Counter2 Overflow
+.org 12
+ rcall isr ; Timer/Counter1 Capture Event
+.org 14
+ rcall isr ; Timer/Counter1 Compare Match A
+.org 16
+ rcall isr ; Timer/Counter Compare Match B
+.org 18
+ rcall isr ; Timer/Counter1 Overflow
+.org 20
+ rcall isr ; Timer/Counter0 Compare Match
+.org 22
+ rcall isr ; Timer/Counter0 Overflow
+.org 24
+ rcall isr ; SPI Serial Transfer Complete
+.org 26
+ rcall isr ; USART0, Rx Complete
+.org 28
+ rcall isr ; USART0 Data register Empty
+.org 30
+ rcall isr ; USART0, Tx Complete
+.org 32
+ rcall isr ; USI Start Condition
+.org 34
+ rcall isr ; USI Overflow
+.org 36
+ rcall isr ; Analog Comparator
+.org 38
+ rcall isr ; ADC Conversion Complete
+.org 40
+ rcall isr ; EEPROM Ready
+.org 42
+ rcall isr ; Store Program Memory Read
+.org 44
+ rcall isr ; LCD Start of Frame
+.equ INTVECTORS = 23
+.nooverlap
+
+; compatability layer (maybe empty)
+.equ EEPE = EEWE
+.equ EEMPE = EEMWE
+
+; controller data area, environment query mcu-info
+mcu_info:
+mcu_ramsize:
+ .dw 4096
+mcu_eepromsize:
+ .dw 2048
+mcu_maxdp:
+ .dw 57344
+mcu_numints:
+ .dw 23
+mcu_name:
+ .dw 10
+ .db "ATmega649P"
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega649p/device.inc b/amforth-6.5/avr8/devices/atmega649p/device.inc
new file mode 100644
index 0000000..630f41a
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega649p/device.inc
@@ -0,0 +1,1293 @@
+; Partname: ATmega649P
+; generated automatically, no not edit
+
+.if WANT_AD_CONVERTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC multiplexer Selection Register
+VE_ADMUX:
+ .dw $ff05
+ .db "ADMUX",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADMUX
+XT_ADMUX:
+ .dw PFA_DOVARIABLE
+PFA_ADMUX:
+ .dw 124
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register
+VE_ADCSRA:
+ .dw $ff06
+ .db "ADCSRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRA
+XT_ADCSRA:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRA:
+ .dw 122
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register Bytes
+VE_ADC:
+ .dw $ff03
+ .db "ADC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADC
+XT_ADC:
+ .dw PFA_DOVARIABLE
+PFA_ADC:
+ .dw 120
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Control and Status Register B
+VE_ADCSRB:
+ .dw $ff06
+ .db "ADCSRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRB
+XT_ADCSRB:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRB:
+ .dw 123
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 0
+VE_DIDR0:
+ .dw $ff05
+ .db "DIDR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR0
+XT_DIDR0:
+ .dw PFA_DOVARIABLE
+PFA_DIDR0:
+ .dw 126
+
+.endif
+.if WANT_ANALOG_COMPARATOR == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Control And Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw 80
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 1
+VE_DIDR1:
+ .dw $ff05
+ .db "DIDR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR1
+XT_DIDR1:
+ .dw PFA_DOVARIABLE
+PFA_DIDR1:
+ .dw 127
+
+.endif
+.if WANT_SPI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR:
+ .dw $ff04
+ .db "SPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR
+XT_SPCR:
+ .dw PFA_DOVARIABLE
+PFA_SPCR:
+ .dw 76
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR:
+ .dw $ff04
+ .db "SPSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR
+XT_SPSR:
+ .dw PFA_DOVARIABLE
+PFA_SPSR:
+ .dw 77
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR:
+ .dw $ff04
+ .db "SPDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR
+XT_SPDR:
+ .dw PFA_DOVARIABLE
+PFA_SPDR:
+ .dw 78
+
+.endif
+.if WANT_USI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USI Data Register
+VE_USIDR:
+ .dw $ff05
+ .db "USIDR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USIDR
+XT_USIDR:
+ .dw PFA_DOVARIABLE
+PFA_USIDR:
+ .dw 186
+; ( -- addr ) System Constant
+; R( -- )
+; USI Status Register
+VE_USISR:
+ .dw $ff05
+ .db "USISR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USISR
+XT_USISR:
+ .dw PFA_DOVARIABLE
+PFA_USISR:
+ .dw 185
+; ( -- addr ) System Constant
+; R( -- )
+; USI Control Register
+VE_USICR:
+ .dw $ff05
+ .db "USICR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USICR
+XT_USICR:
+ .dw PFA_DOVARIABLE
+PFA_USICR:
+ .dw 184
+
+.endif
+.if WANT_USART0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR0:
+ .dw $ff04
+ .db "UDR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR0
+XT_UDR0:
+ .dw PFA_DOVARIABLE
+PFA_UDR0:
+ .dw 198
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR0A:
+ .dw $ff06
+ .db "UCSR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0A
+XT_UCSR0A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0A:
+ .dw 192
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR0B:
+ .dw $ff06
+ .db "UCSR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0B
+XT_UCSR0B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0B:
+ .dw 193
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR0C:
+ .dw $ff06
+ .db "UCSR0C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0C
+XT_UCSR0C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0C:
+ .dw 194
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Bytes
+VE_UBRR0:
+ .dw $ff05
+ .db "UBRR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR0
+XT_UBRR0:
+ .dw PFA_DOVARIABLE
+PFA_UBRR0:
+ .dw 196
+
+.endif
+.if WANT_CPU == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw 95
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer
+VE_SP:
+ .dw $ff02
+ .db "SP"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SP
+XT_SP:
+ .dw PFA_DOVARIABLE
+PFA_SP:
+ .dw 93
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw 85
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Status Register
+VE_MCUSR:
+ .dw $ff05
+ .db "MCUSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUSR
+XT_MCUSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUSR:
+ .dw 84
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Calibration Value
+VE_OSCCAL:
+ .dw $ff06
+ .db "OSCCAL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSCCAL
+XT_OSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_OSCCAL:
+ .dw 102
+; ( -- addr ) System Constant
+; R( -- )
+; Clock Prescale Register
+VE_CLKPR:
+ .dw $ff05
+ .db "CLKPR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKPR
+XT_CLKPR:
+ .dw PFA_DOVARIABLE
+PFA_CLKPR:
+ .dw 97
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register
+VE_PRR:
+ .dw $ff03
+ .db "PRR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR
+XT_PRR:
+ .dw PFA_DOVARIABLE
+PFA_PRR:
+ .dw 100
+; ( -- addr ) System Constant
+; R( -- )
+; Sleep Mode Control Register
+VE_SMCR:
+ .dw $ff04
+ .db "SMCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SMCR
+XT_SMCR:
+ .dw PFA_DOVARIABLE
+PFA_SMCR:
+ .dw 83
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 2
+VE_GPIOR2:
+ .dw $ff06
+ .db "GPIOR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR2
+XT_GPIOR2:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR2:
+ .dw 75
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 1
+VE_GPIOR1:
+ .dw $ff06
+ .db "GPIOR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR1
+XT_GPIOR1:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR1:
+ .dw 74
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 0
+VE_GPIOR0:
+ .dw $ff06
+ .db "GPIOR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR0
+XT_GPIOR0:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR0:
+ .dw 62
+
+.endif
+.if WANT_JTAG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; On-Chip Debug Related Register in I/O Memory
+VE_OCDR:
+ .dw $ff04
+ .db "OCDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCDR
+XT_OCDR:
+ .dw PFA_DOVARIABLE
+PFA_OCDR:
+ .dw 81
+
+.endif
+.if WANT_LCD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 18
+VE_LCDDR18:
+ .dw $ff07
+ .db "LCDDR18",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR18
+XT_LCDDR18:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR18:
+ .dw 254
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 17
+VE_LCDDR17:
+ .dw $ff07
+ .db "LCDDR17",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR17
+XT_LCDDR17:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR17:
+ .dw 253
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 16
+VE_LCDDR16:
+ .dw $ff07
+ .db "LCDDR16",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR16
+XT_LCDDR16:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR16:
+ .dw 252
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 15
+VE_LCDDR15:
+ .dw $ff07
+ .db "LCDDR15",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR15
+XT_LCDDR15:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR15:
+ .dw 251
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 13
+VE_LCDDR13:
+ .dw $ff07
+ .db "LCDDR13",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR13
+XT_LCDDR13:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR13:
+ .dw 249
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 12
+VE_LCDDR12:
+ .dw $ff07
+ .db "LCDDR12",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR12
+XT_LCDDR12:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR12:
+ .dw 248
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 11
+VE_LCDDR11:
+ .dw $ff07
+ .db "LCDDR11",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR11
+XT_LCDDR11:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR11:
+ .dw 247
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 10
+VE_LCDDR10:
+ .dw $ff07
+ .db "LCDDR10",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR10
+XT_LCDDR10:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR10:
+ .dw 246
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 8
+VE_LCDDR8:
+ .dw $ff06
+ .db "LCDDR8"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR8
+XT_LCDDR8:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR8:
+ .dw 244
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 7
+VE_LCDDR7:
+ .dw $ff06
+ .db "LCDDR7"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR7
+XT_LCDDR7:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR7:
+ .dw 243
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 6
+VE_LCDDR6:
+ .dw $ff06
+ .db "LCDDR6"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR6
+XT_LCDDR6:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR6:
+ .dw 242
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 5
+VE_LCDDR5:
+ .dw $ff06
+ .db "LCDDR5"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR5
+XT_LCDDR5:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR5:
+ .dw 241
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 3
+VE_LCDDR3:
+ .dw $ff06
+ .db "LCDDR3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR3
+XT_LCDDR3:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR3:
+ .dw 239
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 2
+VE_LCDDR2:
+ .dw $ff06
+ .db "LCDDR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR2
+XT_LCDDR2:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR2:
+ .dw 238
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 1
+VE_LCDDR1:
+ .dw $ff06
+ .db "LCDDR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR1
+XT_LCDDR1:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR1:
+ .dw 237
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 0
+VE_LCDDR0:
+ .dw $ff06
+ .db "LCDDR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR0
+XT_LCDDR0:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR0:
+ .dw 236
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Contrast Control Register
+VE_LCDCCR:
+ .dw $ff06
+ .db "LCDCCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDCCR
+XT_LCDCCR:
+ .dw PFA_DOVARIABLE
+PFA_LCDCCR:
+ .dw 231
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Frame Rate Register
+VE_LCDFRR:
+ .dw $ff06
+ .db "LCDFRR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDFRR
+XT_LCDFRR:
+ .dw PFA_DOVARIABLE
+PFA_LCDFRR:
+ .dw 230
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Control and Status Register B
+VE_LCDCRB:
+ .dw $ff06
+ .db "LCDCRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDCRB
+XT_LCDCRB:
+ .dw PFA_DOVARIABLE
+PFA_LCDCRB:
+ .dw 229
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Control Register A
+VE_LCDCRA:
+ .dw $ff06
+ .db "LCDCRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDCRA
+XT_LCDCRA:
+ .dw PFA_DOVARIABLE
+PFA_LCDCRA:
+ .dw 228
+
+.endif
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register A
+VE_EICRA:
+ .dw $ff05
+ .db "EICRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRA
+XT_EICRA:
+ .dw PFA_DOVARIABLE
+PFA_EICRA:
+ .dw 105
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Mask Register
+VE_EIMSK:
+ .dw $ff05
+ .db "EIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIMSK
+XT_EIMSK:
+ .dw PFA_DOVARIABLE
+PFA_EIMSK:
+ .dw 61
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Flag Register
+VE_EIFR:
+ .dw $ff04
+ .db "EIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIFR
+XT_EIFR:
+ .dw PFA_DOVARIABLE
+PFA_EIFR:
+ .dw 60
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 1
+VE_PCMSK1:
+ .dw $ff06
+ .db "PCMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK1
+XT_PCMSK1:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK1:
+ .dw 108
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 0
+VE_PCMSK0:
+ .dw $ff06
+ .db "PCMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK0
+XT_PCMSK0:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK0:
+ .dw 107
+
+.endif
+.if WANT_EEPROM == 1
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Read/Write Access Bytes
+VE_EEAR:
+ .dw $ff04
+ .db "EEAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEAR
+XT_EEAR:
+ .dw PFA_DOVARIABLE
+PFA_EEAR:
+ .dw 65
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw 64
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw 63
+
+.endif
+.if WANT_PORTA == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Register
+VE_PORTA:
+ .dw $ff05
+ .db "PORTA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTA
+XT_PORTA:
+ .dw PFA_DOVARIABLE
+PFA_PORTA:
+ .dw 34
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Direction Register
+VE_DDRA:
+ .dw $ff04
+ .db "DDRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRA
+XT_DDRA:
+ .dw PFA_DOVARIABLE
+PFA_DDRA:
+ .dw 33
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Input Pins
+VE_PINA:
+ .dw $ff04
+ .db "PINA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINA
+XT_PINA:
+ .dw PFA_DOVARIABLE
+PFA_PINA:
+ .dw 32
+
+.endif
+.if WANT_PORTB == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw 37
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw 36
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw 35
+
+.endif
+.if WANT_PORTC == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Register
+VE_PORTC:
+ .dw $ff05
+ .db "PORTC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTC
+XT_PORTC:
+ .dw PFA_DOVARIABLE
+PFA_PORTC:
+ .dw 40
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Direction Register
+VE_DDRC:
+ .dw $ff04
+ .db "DDRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRC
+XT_DDRC:
+ .dw PFA_DOVARIABLE
+PFA_DDRC:
+ .dw 39
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Input Pins
+VE_PINC:
+ .dw $ff04
+ .db "PINC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINC
+XT_PINC:
+ .dw PFA_DOVARIABLE
+PFA_PINC:
+ .dw 38
+
+.endif
+.if WANT_PORTD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw 43
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw 42
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw 41
+
+.endif
+.if WANT_PORTE == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port E
+VE_PORTE:
+ .dw $ff05
+ .db "PORTE",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTE
+XT_PORTE:
+ .dw PFA_DOVARIABLE
+PFA_PORTE:
+ .dw 46
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port E
+VE_DDRE:
+ .dw $ff04
+ .db "DDRE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRE
+XT_DDRE:
+ .dw PFA_DOVARIABLE
+PFA_DDRE:
+ .dw 45
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port E
+VE_PINE:
+ .dw $ff04
+ .db "PINE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINE
+XT_PINE:
+ .dw PFA_DOVARIABLE
+PFA_PINE:
+ .dw 44
+
+.endif
+.if WANT_PORTF == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port F
+VE_PORTF:
+ .dw $ff05
+ .db "PORTF",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTF
+XT_PORTF:
+ .dw PFA_DOVARIABLE
+PFA_PORTF:
+ .dw 49
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port F
+VE_DDRF:
+ .dw $ff04
+ .db "DDRF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRF
+XT_DDRF:
+ .dw PFA_DOVARIABLE
+PFA_DDRF:
+ .dw 48
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port F
+VE_PINF:
+ .dw $ff04
+ .db "PINF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINF
+XT_PINF:
+ .dw PFA_DOVARIABLE
+PFA_PINF:
+ .dw 47
+
+.endif
+.if WANT_PORTG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Data Register
+VE_PORTG:
+ .dw $ff05
+ .db "PORTG",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTG
+XT_PORTG:
+ .dw PFA_DOVARIABLE
+PFA_PORTG:
+ .dw 52
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Data Direction Register
+VE_DDRG:
+ .dw $ff04
+ .db "DDRG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRG
+XT_DDRG:
+ .dw PFA_DOVARIABLE
+PFA_DDRG:
+ .dw 51
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Input Pins
+VE_PING:
+ .dw $ff04
+ .db "PING"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PING
+XT_PING:
+ .dw PFA_DOVARIABLE
+PFA_PING:
+ .dw 50
+
+.endif
+.if WANT_TIMER_COUNTER_0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Control Register
+VE_TCCR0A:
+ .dw $ff06
+ .db "TCCR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0A
+XT_TCCR0A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0A:
+ .dw 68
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw 70
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0A:
+ .dw $ff05
+ .db "OCR0A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0A
+XT_OCR0A:
+ .dw PFA_DOVARIABLE
+PFA_OCR0A:
+ .dw 71
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Mask Register
+VE_TIMSK0:
+ .dw $ff06
+ .db "TIMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK0
+XT_TIMSK0:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK0:
+ .dw 110
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Flag register
+VE_TIFR0:
+ .dw $ff05
+ .db "TIFR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR0
+XT_TIFR0:
+ .dw PFA_DOVARIABLE
+PFA_TIFR0:
+ .dw 53
+; ( -- addr ) System Constant
+; R( -- )
+; General Timer/Control Register
+VE_GTCCR:
+ .dw $ff05
+ .db "GTCCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GTCCR
+XT_GTCCR:
+ .dw PFA_DOVARIABLE
+PFA_GTCCR:
+ .dw 67
+
+.endif
+.if WANT_TIMER_COUNTER_1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw 128
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw 129
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter 1 Control Register C
+VE_TCCR1C:
+ .dw $ff06
+ .db "TCCR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1C
+XT_TCCR1C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1C:
+ .dw 130
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Bytes
+VE_TCNT1:
+ .dw $ff05
+ .db "TCNT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1
+XT_TCNT1:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1:
+ .dw 132
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register A Bytes
+VE_OCR1A:
+ .dw $ff05
+ .db "OCR1A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1A
+XT_OCR1A:
+ .dw PFA_DOVARIABLE
+PFA_OCR1A:
+ .dw 136
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register B Bytes
+VE_OCR1B:
+ .dw $ff05
+ .db "OCR1B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1B
+XT_OCR1B:
+ .dw PFA_DOVARIABLE
+PFA_OCR1B:
+ .dw 138
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Bytes
+VE_ICR1:
+ .dw $ff04
+ .db "ICR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1
+XT_ICR1:
+ .dw PFA_DOVARIABLE
+PFA_ICR1:
+ .dw 134
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Mask Register
+VE_TIMSK1:
+ .dw $ff06
+ .db "TIMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK1
+XT_TIMSK1:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK1:
+ .dw 111
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Flag register
+VE_TIFR1:
+ .dw $ff05
+ .db "TIFR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR1
+XT_TIFR1:
+ .dw PFA_DOVARIABLE
+PFA_TIFR1:
+ .dw 54
+
+.endif
+.if WANT_TIMER_COUNTER_2 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register
+VE_TCCR2A:
+ .dw $ff06
+ .db "TCCR2A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2A
+XT_TCCR2A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2A:
+ .dw 176
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2
+VE_TCNT2:
+ .dw $ff05
+ .db "TCNT2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT2
+XT_TCNT2:
+ .dw PFA_DOVARIABLE
+PFA_TCNT2:
+ .dw 178
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register
+VE_OCR2A:
+ .dw $ff05
+ .db "OCR2A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2A
+XT_OCR2A:
+ .dw PFA_DOVARIABLE
+PFA_OCR2A:
+ .dw 179
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Interrupt Mask register
+VE_TIMSK2:
+ .dw $ff06
+ .db "TIMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK2
+XT_TIMSK2:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK2:
+ .dw 112
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Interrupt Flag Register
+VE_TIFR2:
+ .dw $ff05
+ .db "TIFR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR2
+XT_TIFR2:
+ .dw PFA_DOVARIABLE
+PFA_TIFR2:
+ .dw 55
+; ( -- addr ) System Constant
+; R( -- )
+; Asynchronous Status Register
+VE_ASSR:
+ .dw $ff04
+ .db "ASSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ASSR
+XT_ASSR:
+ .dw PFA_DOVARIABLE
+PFA_ASSR:
+ .dw 182
+
+.endif
+.if WANT_WATCHDOG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCR:
+ .dw $ff05
+ .db "WDTCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCR
+XT_WDTCR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCR:
+ .dw 96
+
+.endif
+.if WANT_BOOT_LOAD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control Register
+VE_SPMCSR:
+ .dw $ff06
+ .db "SPMCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCSR
+XT_SPMCSR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCSR:
+ .dw 87
+
+.endif
diff --git a/amforth-6.5/avr8/devices/atmega649p/device.py b/amforth-6.5/avr8/devices/atmega649p/device.py
new file mode 100644
index 0000000..d327b8a
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega649p/device.py
@@ -0,0 +1,352 @@
+# Generated Automatically
+
+# Partname ATmega649P
+
+MCUREGS = {
+# Interrupt Vectors
+ 'INT0Addr' : '#2', # External Interrupt Request 0
+ 'PCINT0Addr' : '#4', # Pin Change Interrupt Request 0
+ 'PCINT1Addr' : '#6', # Pin Change Interrupt Request 1
+ 'TIMER2_COMPAddr' : '#8', # Timer/Counter2 Compare Match
+ 'TIMER2_OVFAddr' : '#10', # Timer/Counter2 Overflow
+ 'TIMER1_CAPTAddr' : '#12', # Timer/Counter1 Capture Event
+ 'TIMER1_COMPAAddr' : '#14', # Timer/Counter1 Compare Match A
+ 'TIMER1_COMPBAddr' : '#16', # Timer/Counter Compare Match B
+ 'TIMER1_OVFAddr' : '#18', # Timer/Counter1 Overflow
+ 'TIMER0_COMPAddr' : '#20', # Timer/Counter0 Compare Match
+ 'TIMER0_OVFAddr' : '#22', # Timer/Counter0 Overflow
+ 'SPI_STCAddr' : '#24', # SPI Serial Transfer Complete
+ 'USART0_RXAddr' : '#26', # USART0, Rx Complete
+ 'USART0_UDREAddr' : '#28', # USART0 Data register Empty
+ 'USART0_TXAddr' : '#30', # USART0, Tx Complete
+ 'USI_STARTAddr' : '#32', # USI Start Condition
+ 'USI_OVERFLOWAddr' : '#34', # USI Overflow
+ 'ANALOG_COMPAddr' : '#36', # Analog Comparator
+ 'ADCAddr' : '#38', # ADC Conversion Complete
+ 'EE_READYAddr' : '#40', # EEPROM Ready
+ 'SPM_READYAddr' : '#42', # Store Program Memory Read
+ 'LCDAddr' : '#44', # LCD Start of Frame
+
+# Module AD_CONVERTER
+ 'ADMUX' : '$7c', # The ADC multiplexer Selection
+ 'ADMUX_REFS': '$c0', # Reference Selection Bits
+ 'ADMUX_ADLAR': '$20', # Left Adjust Result
+ 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
+ 'ADCSRA' : '$7a', # The ADC Control and Status reg
+ 'ADCSRA_ADEN': '$80', # ADC Enable
+ 'ADCSRA_ADSC': '$40', # ADC Start Conversion
+ 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
+ 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
+ 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
+ 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
+ 'ADC' : '$78', # ADC Data Register Bytes
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Sources
+ 'DIDR0' : '$7e', # Digital Input Disable Register
+ 'DIDR0_ADC7D': '$80', # ADC7 Digital input Disable
+ 'DIDR0_ADC6D': '$40', # ADC6 Digital input Disable
+ 'DIDR0_ADC5D': '$20', # ADC5 Digital input Disable
+ 'DIDR0_ADC4D': '$10', # ADC4 Digital input Disable
+ 'DIDR0_ADC3D': '$8', # ADC3 Digital input Disable
+ 'DIDR0_ADC2D': '$4', # ADC2 Digital input Disable
+ 'DIDR0_ADC1D': '$2', # ADC1 Digital input Disable
+ 'DIDR0_ADC0D': '$1', # ADC0 Digital input Disable
+
+# Module ANALOG_COMPARATOR
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
+ 'ACSR' : '$50', # Analog Comparator Control And
+ 'ACSR_ACD': '$80', # Analog Comparator Disable
+ 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
+ 'ACSR_ACO': '$20', # Analog Compare Output
+ 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
+ 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
+ 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
+ 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
+ 'DIDR1' : '$7f', # Digital Input Disable Register
+ 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
+ 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
+
+# Module SPI
+ 'SPCR' : '$4c', # SPI Control Register
+ 'SPCR_SPIE': '$80', # SPI Interrupt Enable
+ 'SPCR_SPE': '$40', # SPI Enable
+ 'SPCR_DORD': '$20', # Data Order
+ 'SPCR_MSTR': '$10', # Master/Slave Select
+ 'SPCR_CPOL': '$8', # Clock polarity
+ 'SPCR_CPHA': '$4', # Clock Phase
+ 'SPCR_SPR': '$3', # SPI Clock Rate Selects
+ 'SPSR' : '$4d', # SPI Status Register
+ 'SPSR_SPIF': '$80', # SPI Interrupt Flag
+ 'SPSR_WCOL': '$40', # Write Collision Flag
+ 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
+ 'SPDR' : '$4e', # SPI Data Register
+
+# Module USI
+ 'USIDR' : '$ba', # USI Data Register
+ 'USISR' : '$b9', # USI Status Register
+ 'USISR_USISIF': '$80', # Start Condition Interrupt Flag
+ 'USISR_USIOIF': '$40', # Counter Overflow Interrupt Fla
+ 'USISR_USIPF': '$20', # Stop Condition Flag
+ 'USISR_USIDC': '$10', # Data Output Collision
+ 'USISR_USICNT': '$f', # USI Counter Value Bits
+ 'USICR' : '$b8', # USI Control Register
+ 'USICR_USISIE': '$80', # Start Condition Interrupt Enab
+ 'USICR_USIOIE': '$40', # Counter Overflow Interrupt Ena
+ 'USICR_USIWM': '$30', # USI Wire Mode Bits
+ 'USICR_USICS': '$c', # USI Clock Source Select Bits
+ 'USICR_USICLK': '$2', # Clock Strobe
+ 'USICR_USITC': '$1', # Toggle Clock Port Pin
+
+# Module USART0
+ 'UDR0' : '$c6', # USART I/O Data Register
+ 'UCSR0A' : '$c0', # USART Control and Status Regis
+ 'UCSR0A_RXC0': '$80', # USART Receive Complete
+ 'UCSR0A_TXC0': '$40', # USART Transmit Complete
+ 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
+ 'UCSR0A_FE0': '$10', # Framing Error
+ 'UCSR0A_DOR0': '$8', # Data OverRun
+ 'UCSR0A_UPE0': '$4', # USART Parity Error
+ 'UCSR0A_U2X0': '$2', # Double the USART Transmission
+ 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
+ 'UCSR0B' : '$c1', # USART Control and Status Regis
+ 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
+ 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
+ 'UCSR0B_UDRIE0': '$20', # USART Data Register Empty Inte
+ 'UCSR0B_RXEN0': '$10', # Receiver Enable
+ 'UCSR0B_TXEN0': '$8', # Transmitter Enable
+ 'UCSR0B_UCSZ02': '$4', # Character Size
+ 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
+ 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
+ 'UCSR0C' : '$c2', # USART Control and Status Regis
+ 'UCSR0C_UMSEL0': '$40', # USART Mode Select
+ 'UCSR0C_UPM0': '$30', # Parity Mode Bits
+ 'UCSR0C_USBS0': '$8', # Stop Bit Select
+ 'UCSR0C_UCSZ0': '$6', # Character Size
+ 'UCSR0C_UCPOL0': '$1', # Clock Polarity
+ 'UBRR0' : '$c4', # USART Baud Rate Register Byte
+
+# Module CPU
+ 'SREG' : '$5f', # Status Register
+ 'SREG_I': '$80', # Global Interrupt Enable
+ 'SREG_T': '$40', # Bit Copy Storage
+ 'SREG_H': '$20', # Half Carry Flag
+ 'SREG_S': '$10', # Sign Bit
+ 'SREG_V': '$8', # Two's Complement Overflow Flag
+ 'SREG_N': '$4', # Negative Flag
+ 'SREG_Z': '$2', # Zero Flag
+ 'SREG_C': '$1', # Carry Flag
+ 'SP' : '$5d', # Stack Pointer
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_PUD': '$10', # Pull-up disable
+ 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
+ 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+ 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
+ 'MCUSR_BORF': '$4', # Brown-out Reset Flag
+ 'MCUSR_EXTRF': '$2', # External Reset Flag
+ 'MCUSR_PORF': '$1', # Power-on reset flag
+ 'OSCCAL' : '$66', # Oscillator Calibration Value
+ 'CLKPR' : '$61', # Clock Prescale Register
+ 'CLKPR_CLKPCE': '$80', # Clock Prescaler Change Enable
+ 'CLKPR_CLKPS': '$f', # Clock Prescaler Select Bits
+ 'PRR' : '$64', # Power Reduction Register
+ 'PRR_PRLCD': '$10', # Power Reduction LCD
+ 'PRR_PRTIM1': '$8', # Power Reduction Timer/Counter1
+ 'PRR_PRSPI': '$4', # Power Reduction Serial Periphe
+ 'PRR_PRUSART0': '$2', # Power Reduction USART
+ 'PRR_PRADC': '$1', # Power Reduction ADC
+ 'SMCR' : '$53', # Sleep Mode Control Register
+ 'SMCR_SM': '$e', # Sleep Mode Select bits
+ 'SMCR_SE': '$1', # Sleep Enable
+ 'GPIOR2' : '$4b', # General Purpose IO Register 2
+ 'GPIOR1' : '$4a', # General Purpose IO Register 1
+ 'GPIOR0' : '$3e', # General Purpose IO Register 0
+
+# Module JTAG
+ 'OCDR' : '$51', # On-Chip Debug Related Register
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_JTD': '$80', # JTAG Interface Disable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+
+# Module LCD
+ 'LCDDR18' : '$fe', # LCD Data Register 18
+ 'LCDDR17' : '$fd', # LCD Data Register 17
+ 'LCDDR16' : '$fc', # LCD Data Register 16
+ 'LCDDR15' : '$fb', # LCD Data Register 15
+ 'LCDDR13' : '$f9', # LCD Data Register 13
+ 'LCDDR12' : '$f8', # LCD Data Register 12
+ 'LCDDR11' : '$f7', # LCD Data Register 11
+ 'LCDDR10' : '$f6', # LCD Data Register 10
+ 'LCDDR8' : '$f4', # LCD Data Register 8
+ 'LCDDR7' : '$f3', # LCD Data Register 7
+ 'LCDDR6' : '$f2', # LCD Data Register 6
+ 'LCDDR5' : '$f1', # LCD Data Register 5
+ 'LCDDR3' : '$ef', # LCD Data Register 3
+ 'LCDDR2' : '$ee', # LCD Data Register 2
+ 'LCDDR1' : '$ed', # LCD Data Register 1
+ 'LCDDR0' : '$ec', # LCD Data Register 0
+ 'LCDCCR' : '$e7', # LCD Contrast Control Register
+ 'LCDFRR' : '$e6', # LCD Frame Rate Register
+ 'LCDFRR_LCDPS': '$70', # LCD Prescaler Selects
+ 'LCDFRR_LCDCD': '$7', # LCD Clock Dividers
+ 'LCDCRB' : '$e5', # LCD Control and Status Registe
+ 'LCDCRB_LCDCS': '$80', # LCD CLock Select
+ 'LCDCRB_LCD2B': '$40', # LCD 1/2 Bias Select
+ 'LCDCRB_LCDMUX': '$30', # LCD Mux Selects
+ 'LCDCRB_LCDPM': '$f', # LCD Port Masks
+ 'LCDCRA' : '$e4', # LCD Control Register A
+ 'LCDCRA_LCDEN': '$80', # LCD Enable
+ 'LCDCRA_LCDAB': '$40', # LCD A or B waveform
+ 'LCDCRA_LCDIF': '$10', # LCD Interrupt Flag
+ 'LCDCRA_LCDIE': '$8', # LCD Interrupt Enable
+ 'LCDCRA_LCDBL': '$1', # LCD Blanking
+
+# Module EXTERNAL_INTERRUPT
+ 'EICRA' : '$69', # External Interrupt Control Reg
+ 'EICRA_ISC01': '$2', # External Interrupt Sense Contr
+ 'EICRA_ISC00': '$1', # External Interrupt Sense Contr
+ 'EIMSK' : '$3d', # External Interrupt Mask Regist
+ 'EIMSK_PCIE': '$f0', # Pin Change Interrupt Enables
+ 'EIMSK_INT0': '$1', # External Interrupt Request 0 E
+ 'EIFR' : '$3c', # External Interrupt Flag Regist
+ 'EIFR_PCIF': '$f0', # Pin Change Interrupt Flags
+ 'EIFR_INTF0': '$1', # External Interrupt Flag 0
+ 'PCMSK1' : '$6c', # Pin Change Mask Register 1
+ 'PCMSK0' : '$6b', # Pin Change Mask Register 0
+
+# Module EEPROM
+ 'EEAR' : '$41', # EEPROM Read/Write Access Byte
+ 'EEDR' : '$40', # EEPROM Data Register
+ 'EECR' : '$3f', # EEPROM Control Register
+ 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
+ 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
+ 'EECR_EEWE': '$2', # EEPROM Write Enable
+ 'EECR_EERE': '$1', # EEPROM Read Enable
+
+# Module PORTA
+ 'PORTA' : '$22', # Port A Data Register
+ 'DDRA' : '$21', # Port A Data Direction Register
+ 'PINA' : '$20', # Port A Input Pins
+
+# Module PORTB
+ 'PORTB' : '$25', # Port B Data Register
+ 'DDRB' : '$24', # Port B Data Direction Register
+ 'PINB' : '$23', # Port B Input Pins
+
+# Module PORTC
+ 'PORTC' : '$28', # Port C Data Register
+ 'DDRC' : '$27', # Port C Data Direction Register
+ 'PINC' : '$26', # Port C Input Pins
+
+# Module PORTD
+ 'PORTD' : '$2b', # Port D Data Register
+ 'DDRD' : '$2a', # Port D Data Direction Register
+ 'PIND' : '$29', # Port D Input Pins
+
+# Module PORTE
+ 'PORTE' : '$2e', # Data Register, Port E
+ 'DDRE' : '$2d', # Data Direction Register, Port
+ 'PINE' : '$2c', # Input Pins, Port E
+
+# Module PORTF
+ 'PORTF' : '$31', # Data Register, Port F
+ 'DDRF' : '$30', # Data Direction Register, Port
+ 'PINF' : '$2f', # Input Pins, Port F
+
+# Module PORTG
+ 'PORTG' : '$34', # Port G Data Register
+ 'DDRG' : '$33', # Port G Data Direction Register
+ 'PING' : '$32', # Port G Input Pins
+
+# Module TIMER_COUNTER_0
+ 'TCCR0A' : '$44', # Timer/Counter0 Control Registe
+ 'TCCR0A_FOC0A': '$80', # Force Output Compare
+ 'TCCR0A_WGM00': '$40', # Waveform Generation Mode 0
+ 'TCCR0A_COM0A': '$30', # Compare Match Output Modes
+ 'TCCR0A_WGM01': '$8', # Waveform Generation Mode 1
+ 'TCCR0A_CS0': '$7', # Clock Selects
+ 'TCNT0' : '$46', # Timer/Counter0
+ 'OCR0A' : '$47', # Timer/Counter0 Output Compare
+ 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
+ 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
+ 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
+ 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
+ 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
+ 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Control Register
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSR310': '$1', # Prescaler Reset Timer/Counter1
+
+# Module TIMER_COUNTER_1
+ 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
+ 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
+ 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
+ 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
+ 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
+ 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
+ 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
+ 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
+ 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
+ 'TCCR1C' : '$82', # Timer/Counter 1 Control Regist
+ 'TCCR1C_FOC1A': '$80', # Force Output Compare 1A
+ 'TCCR1C_FOC1B': '$40', # Force Output Compare 1B
+ 'TCNT1' : '$84', # Timer/Counter1 Bytes
+ 'OCR1A' : '$88', # Timer/Counter1 Output Compare
+ 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
+ 'ICR1' : '$86', # Timer/Counter1 Input Capture R
+ 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
+ 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
+ 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
+ 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
+ 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
+ 'TIFR1' : '$36', # Timer/Counter1 Interrupt Flag
+ 'TIFR1_ICF1': '$20', # Input Capture Flag 1
+ 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
+ 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
+ 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
+
+# Module TIMER_COUNTER_2
+ 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
+ 'TCCR2A_FOC2A': '$80', # Force Output Compare A
+ 'TCCR2A_WGM20': '$40', # Waveform Generation Mode
+ 'TCCR2A_COM2A': '$30', # Compare Output Mode bits
+ 'TCCR2A_WGM21': '$8', # Waveform Generation Mode
+ 'TCCR2A_CS2': '$7', # Clock Select bits
+ 'TCNT2' : '$b2', # Timer/Counter2
+ 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
+ 'TIMSK2' : '$70', # Timer/Counter2 Interrupt Mask
+ 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
+ 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
+ 'TIFR2' : '$37', # Timer/Counter2 Interrupt Flag
+ 'TIFR2_OCF2A': '$2', # Timer/Counter2 Output Compare
+ 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_PSR2': '$2', # Prescaler Reset Timer/Counter2
+ 'ASSR' : '$b6', # Asynchronous Status Register
+ 'ASSR_EXCLK': '$10', # Enable External Clock Interrup
+ 'ASSR_AS2': '$8', # AS2: Asynchronous Timer/Counte
+ 'ASSR_TCN2UB': '$4', # TCN2UB: Timer/Counter2 Update
+ 'ASSR_OCR2UB': '$2', # Output Compare Register2 Updat
+ 'ASSR_TCR2UB': '$1', # TCR2UB: Timer/Counter Control
+
+# Module WATCHDOG
+ 'WDTCR' : '$60', # Watchdog Timer Control Registe
+ 'WDTCR_WDCE': '$10', # Watchdog Change Enable
+ 'WDTCR_WDE': '$8', # Watch Dog Enable
+ 'WDTCR_WDP': '$7', # Watch Dog Timer Prescaler bits
+
+# Module BOOT_LOAD
+ 'SPMCSR' : '$57', # Store Program Memory Control R
+ 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
+ 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
+ 'SPMCSR_RWWSRE': '$10', # Read While Write section read
+ 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
+ 'SPMCSR_PGWRT': '$4', # Page Write
+ 'SPMCSR_PGERS': '$2', # Page Erase
+ 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
+
+ '__amforth_dummy':'0'
+}
diff --git a/amforth-6.5/avr8/devices/atmega649p/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega649p/words/no-jtag.asm
new file mode 100644
index 0000000..352a4bb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega649p/words/no-jtag.asm
@@ -0,0 +1,14 @@
+; ( -- )
+; ( -- )
+; MCU
+; disable jtag at runtime
+VE_NOJTAG:
+ .dw $FF05
+ .db "-jtag",0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOJTAG
+XT_NOJTAG:
+ .dw PFA_NOJTAG
+PFA_NOJTAG:
+
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega649p/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega649p/words/no-wdt.asm
new file mode 100644
index 0000000..4a12261
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega649p/words/no-wdt.asm
@@ -0,0 +1,22 @@
+; ( -- )
+; MCU
+; disable watch dog timer at runtime
+VE_NOWDT:
+ .dw $ff04
+ .db "-wdt"
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOWDT
+XT_NOWDT:
+ .dw PFA_NOWDT
+PFA_NOWDT:
+
+; Reset WDT
+ wdr
+; Write logical one to WDTOE and WDE
+ in_ temp1, WDTCR
+ ori temp1, (1<<WDTOE)|(1<<WDE)
+ out WDTCR, temp1
+; Turn off WDT
+ ldi temp1, (0<<WDE)
+ out_ WDTCR, temp1
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega649p/words/sleep.asm b/amforth-6.5/avr8/devices/atmega649p/words/sleep.asm
new file mode 100644
index 0000000..256249c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega649p/words/sleep.asm
@@ -0,0 +1,19 @@
+; ( mode -- )
+; MCU
+; put the controller into the specified sleep mode
+VE_SLEEP:
+ .dw $ff05
+ .db "sleep", 0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_SLEEP
+XT_SLEEP:
+ .dw PFA_SLEEP
+PFA_SLEEP:
+ andi tosl, 7 ; leave only legal mode bits
+ lsl tosl ; move to correct location (bits 3-1)
+ ori tosl, 1 ; set the SE bit
+ out_ SMCR, tosl ; set the sleep config
+ sleep ; nighty-night
+ out_ SMCR, zerol ; 0 protects against accidental sleeps
+ loadtos ; pop argument from stack
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega64a/atmega64a.frt b/amforth-6.5/avr8/devices/atmega64a/atmega64a.frt
new file mode 100644
index 0000000..360771b
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega64a/atmega64a.frt
@@ -0,0 +1,331 @@
+\ Partname: ATmega64A
+\ generated automatically
+
+\ ANALOG_COMPARATOR
+&64 constant SFIOR \ Special Function IO Register
+ $08 constant SFIOR_ACME \ Analog Comparator Multiplexer Enable
+&40 constant ACSR \ Analog Comparator Control And Status Register
+ $80 constant ACSR_ACD \ Analog Comparator Disable
+ $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
+ $20 constant ACSR_ACO \ Analog Compare Output
+ $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
+ $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
+ $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
+ $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
+\ AD_CONVERTER
+&39 constant ADMUX \ The ADC multiplexer Selection Register
+ $C0 constant ADMUX_REFS \ Reference Selection Bits
+ $20 constant ADMUX_ADLAR \ Left Adjust Result
+ $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
+&36 constant ADC \ ADC Data Register Bytes
+&38 constant ADCSRA \ The ADC Control and Status register A
+ $80 constant ADCSRA_ADEN \ ADC Enable
+ $40 constant ADCSRA_ADSC \ ADC Start Conversion
+ $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
+ $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
+ $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
+ $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
+&142 constant ADCSRB \ The ADC Control and Status register B
+ $07 constant ADCSRB_ADTS \ ADC Auto Trigger Source bits
+\ SPI
+&47 constant SPDR \ SPI Data Register
+&46 constant SPSR \ SPI Status Register
+ $80 constant SPSR_SPIF \ SPI Interrupt Flag
+ $40 constant SPSR_WCOL \ Write Collision Flag
+ $01 constant SPSR_SPI2X \ Double SPI Speed Bit
+&45 constant SPCR \ SPI Control Register
+ $80 constant SPCR_SPIE \ SPI Interrupt Enable
+ $40 constant SPCR_SPE \ SPI Enable
+ $20 constant SPCR_DORD \ Data Order
+ $10 constant SPCR_MSTR \ Master/Slave Select
+ $08 constant SPCR_CPOL \ Clock polarity
+ $04 constant SPCR_CPHA \ Clock Phase
+ $03 constant SPCR_SPR \ SPI Clock Rate Selects
+\ TWI
+&112 constant TWBR \ TWI Bit Rate register
+&116 constant TWCR \ TWI Control Register
+ $80 constant TWCR_TWINT \ TWI Interrupt Flag
+ $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
+ $20 constant TWCR_TWSTA \ TWI Start Condition Bit
+ $10 constant TWCR_TWSTO \ TWI Stop Condition Bit
+ $08 constant TWCR_TWWC \ TWI Write Collition Flag
+ $04 constant TWCR_TWEN \ TWI Enable Bit
+ $01 constant TWCR_TWIE \ TWI Interrupt Enable
+&113 constant TWSR \ TWI Status Register
+ $F8 constant TWSR_TWS \ TWI Status
+ $03 constant TWSR_TWPS \ TWI Prescaler
+&115 constant TWDR \ TWI Data register
+&114 constant TWAR \ TWI (Slave) Address register
+ $FE constant TWAR_TWA \ TWI (Slave) Address register Bits
+ $01 constant TWAR_TWGCE \ TWI General Call Recognition Enable Bit
+\ USART0
+&44 constant UDR0 \ USART I/O Data Register
+&43 constant UCSR0A \ USART Control and Status Register A
+ $80 constant UCSR0A_RXC0 \ USART Receive Complete
+ $40 constant UCSR0A_TXC0 \ USART Transmitt Complete
+ $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
+ $10 constant UCSR0A_FE0 \ Framing Error
+ $08 constant UCSR0A_DOR0 \ Data overRun
+ $04 constant UCSR0A_UPE0 \ Parity Error
+ $02 constant UCSR0A_U2X0 \ Double the USART transmission speed
+ $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
+&42 constant UCSR0B \ USART Control and Status Register B
+ $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
+ $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
+ $20 constant UCSR0B_UDRIE0 \ USART Data register Empty Interrupt Enable
+ $10 constant UCSR0B_RXEN0 \ Receiver Enable
+ $08 constant UCSR0B_TXEN0 \ Transmitter Enable
+ $04 constant UCSR0B_UCSZ02 \ Character Size
+ $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
+ $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
+&149 constant UCSR0C \ USART Control and Status Register C
+ $40 constant UCSR0C_UMSEL0 \ USART Mode Select
+ $30 constant UCSR0C_UPM0 \ Parity Mode Bits
+ $08 constant UCSR0C_USBS0 \ Stop Bit Select
+ $06 constant UCSR0C_UCSZ0 \ Character Size
+ $01 constant UCSR0C_UCPOL0 \ Clock Polarity
+&144 constant UBRR0H \ USART Baud Rate Register Hight Byte
+&41 constant UBRR0L \ USART Baud Rate Register Low Byte
+\ USART1
+&156 constant UDR1 \ USART I/O Data Register
+&155 constant UCSR1A \ USART Control and Status Register A
+ $80 constant UCSR1A_RXC1 \ USART Receive Complete
+ $40 constant UCSR1A_TXC1 \ USART Transmitt Complete
+ $20 constant UCSR1A_UDRE1 \ USART Data Register Empty
+ $10 constant UCSR1A_FE1 \ Framing Error
+ $08 constant UCSR1A_DOR1 \ Data overRun
+ $04 constant UCSR1A_UPE1 \ Parity Error
+ $02 constant UCSR1A_U2X1 \ Double the USART transmission speed
+ $01 constant UCSR1A_MPCM1 \ Multi-processor Communication Mode
+&154 constant UCSR1B \ USART Control and Status Register B
+ $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable
+ $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable
+ $20 constant UCSR1B_UDRIE1 \ USART Data register Empty Interrupt Enable
+ $10 constant UCSR1B_RXEN1 \ Receiver Enable
+ $08 constant UCSR1B_TXEN1 \ Transmitter Enable
+ $04 constant UCSR1B_UCSZ12 \ Character Size
+ $02 constant UCSR1B_RXB81 \ Receive Data Bit 8
+ $01 constant UCSR1B_TXB81 \ Transmit Data Bit 8
+&157 constant UCSR1C \ USART Control and Status Register C
+ $40 constant UCSR1C_UMSEL1 \ USART Mode Select
+ $30 constant UCSR1C_UPM1 \ Parity Mode Bits
+ $08 constant UCSR1C_USBS1 \ Stop Bit Select
+ $06 constant UCSR1C_UCSZ1 \ Character Size
+ $01 constant UCSR1C_UCPOL1 \ Clock Polarity
+&152 constant UBRR1H \ USART Baud Rate Register Hight Byte
+&153 constant UBRR1L \ USART Baud Rate Register Low Byte
+\ CPU
+&95 constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ $08 constant SREG_V \ Two's Complement Overflow Flag
+ $04 constant SREG_N \ Negative Flag
+ $02 constant SREG_Z \ Zero Flag
+ $01 constant SREG_C \ Carry Flag
+&93 constant SP \ Stack Pointer
+&85 constant MCUCR \ MCU Control Register
+ $80 constant MCUCR_SRE \ External SRAM Enable
+ $40 constant MCUCR_SRW10 \ External SRAM Wait State Select
+ $20 constant MCUCR_SE \ Sleep Enable
+ $18 constant MCUCR_SM \ Sleep Mode Select
+ $04 constant MCUCR_SM2 \ Sleep Mode Select
+ $02 constant MCUCR_IVSEL \ Interrupt Vector Select
+ $01 constant MCUCR_IVCE \ Interrupt Vector Change Enable
+&84 constant MCUCSR \ MCU Control And Status Register
+ $80 constant MCUCSR_JTD \ JTAG Interface Disable
+ $10 constant MCUCSR_JTRF \ JTAG Reset Flag
+ $08 constant MCUCSR_WDRF \ Watchdog Reset Flag
+ $04 constant MCUCSR_BORF \ Brown-out Reset Flag
+ $02 constant MCUCSR_EXTRF \ External Reset Flag
+ $01 constant MCUCSR_PORF \ Power-on reset flag
+&109 constant XMCRA \ External Memory Control Register A
+ $70 constant XMCRA_SRL \ Wait state page limit
+ $0C constant XMCRA_SRW0 \ Wait state select bit lower page
+ $02 constant XMCRA_SRW11 \ Wait state select bit upper page
+&108 constant XMCRB \ External Memory Control Register B
+ $80 constant XMCRB_XMBK \ External Memory Bus Keeper Enable
+ $07 constant XMCRB_XMM \ External Memory High Mask
+&111 constant OSCCAL \ Oscillator Calibration Value
+&92 constant XDIV \ XTAL Divide Control Register
+ $80 constant XDIV_XDIVEN \ XTAL Divide Enable
+ $7F constant XDIV_XDIV \ XTAl Divide Select Bits
+\ BOOT_LOAD
+&104 constant SPMCSR \ Store Program Memory Control Register
+ $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
+ $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
+ $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
+ $04 constant SPMCSR_PGWRT \ Page Write
+ $02 constant SPMCSR_PGERS \ Page Erase
+ $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
+\ JTAG
+&66 constant OCDR \ On-Chip Debug Related Register in I/O Memory
+ $FF constant OCDR_OCDR \ On-Chip Debug Register Bits
+\ MISC
+\ EXTERNAL_INTERRUPT
+&106 constant EICRA \ External Interrupt Control Register A
+ $C0 constant EICRA_ISC3 \ External Interrupt Sense Control Bit
+ $30 constant EICRA_ISC2 \ External Interrupt Sense Control Bit
+ $0C constant EICRA_ISC1 \ External Interrupt Sense Control Bit
+ $03 constant EICRA_ISC0 \ External Interrupt Sense Control Bit
+&90 constant EICRB \ External Interrupt Control Register B
+ $C0 constant EICRB_ISC7 \ External Interrupt 7-4 Sense Control Bit
+ $30 constant EICRB_ISC6 \ External Interrupt 7-4 Sense Control Bit
+ $0C constant EICRB_ISC5 \ External Interrupt 7-4 Sense Control Bit
+ $03 constant EICRB_ISC4 \ External Interrupt 7-4 Sense Control Bit
+&89 constant EIMSK \ External Interrupt Mask Register
+ $FF constant EIMSK_INT \ External Interrupt Request 7 Enable
+&88 constant EIFR \ External Interrupt Flag Register
+ $FF constant EIFR_INTF \ External Interrupt Flags
+\ EEPROM
+&62 constant EEAR \ EEPROM Read/Write Access Bytes
+&61 constant EEDR \ EEPROM Data Register
+&60 constant EECR \ EEPROM Control Register
+ $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
+ $04 constant EECR_EEMWE \ EEPROM Master Write Enable
+ $02 constant EECR_EEWE \ EEPROM Write Enable
+ $01 constant EECR_EERE \ EEPROM Read Enable
+\ PORTA
+&59 constant PORTA \ Port A Data Register
+&58 constant DDRA \ Port A Data Direction Register
+&57 constant PINA \ Port A Input Pins
+\ PORTB
+&56 constant PORTB \ Port B Data Register
+&55 constant DDRB \ Port B Data Direction Register
+&54 constant PINB \ Port B Input Pins
+\ PORTC
+&53 constant PORTC \ Port C Data Register
+&52 constant DDRC \ Port C Data Direction Register
+&51 constant PINC \ Port C Input Pins
+\ PORTD
+&50 constant PORTD \ Port D Data Register
+&49 constant DDRD \ Port D Data Direction Register
+&48 constant PIND \ Port D Input Pins
+\ PORTE
+&35 constant PORTE \ Data Register, Port E
+&34 constant DDRE \ Data Direction Register, Port E
+&33 constant PINE \ Input Pins, Port E
+\ PORTF
+&98 constant PORTF \ Data Register, Port F
+&97 constant DDRF \ Data Direction Register, Port F
+&32 constant PINF \ Input Pins, Port F
+\ PORTG
+&101 constant PORTG \ Data Register, Port G
+&100 constant DDRG \ Data Direction Register, Port G
+&99 constant PING \ Input Pins, Port G
+\ TIMER_COUNTER_0
+&83 constant TCCR0 \ Timer/Counter Control Register
+ $80 constant TCCR0_FOC0 \ Force Output Compare
+ $40 constant TCCR0_WGM00 \ Waveform Generation Mode 0
+ $30 constant TCCR0_COM0 \ Compare Match Output Modes
+ $08 constant TCCR0_WGM01 \ Waveform Generation Mode 1
+ $07 constant TCCR0_CS0 \ Clock Selects
+&82 constant TCNT0 \ Timer/Counter Register
+&81 constant OCR0 \ Output Compare Register
+&80 constant ASSR \ Asynchronus Status Register
+ $08 constant ASSR_AS0 \ Asynchronus Timer/Counter 0
+ $04 constant ASSR_TCN0UB \ Timer/Counter0 Update Busy
+ $02 constant ASSR_OCR0UB \ Output Compare register 0 Busy
+ $01 constant ASSR_TCR0UB \ Timer/Counter Control Register 0 Update Busy
+&87 constant TIMSK \ Timer/Counter Interrupt Mask Register
+ $02 constant TIMSK_OCIE0 \ Timer/Counter0 Output Compare Match Interrupt register
+ $01 constant TIMSK_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
+&86 constant TIFR \ Timer/Counter Interrupt Flag register
+ $02 constant TIFR_OCF0 \ Output Compare Flag 0
+ $01 constant TIFR_TOV0 \ Timer/Counter0 Overflow Flag
+\ TIMER_COUNTER_1
+&125 constant ETIMSK \ Extended Timer/Counter Interrupt Mask Register
+ $01 constant ETIMSK_OCIE1C \ Timer/Counter 1, Output Compare Match C Interrupt Enable
+&124 constant ETIFR \ Extended Timer/Counter Interrupt Flag register
+ $01 constant ETIFR_OCF1C \ Timer/Counter 1, Output Compare C Match Flag
+&79 constant TCCR1A \ Timer/Counter1 Control Register A
+ $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
+ $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
+ $0C constant TCCR1A_COM1C \ Compare Output Mode 1C, bits
+ $03 constant TCCR1A_WGM1 \ Waveform Generation Mode Bits
+&78 constant TCCR1B \ Timer/Counter1 Control Register B
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
+ $07 constant TCCR1B_CS1 \ Clock Select1 bits
+&122 constant TCCR1C \ Timer/Counter1 Control Register C
+ $80 constant TCCR1C_FOC1A \ Force Output Compare for channel A
+ $40 constant TCCR1C_FOC1B \ Force Output Compare for channel B
+ $20 constant TCCR1C_FOC1C \ Force Output Compare for channel C
+&76 constant TCNT1 \ Timer/Counter1 Bytes
+&74 constant OCR1A \ Timer/Counter1 Output Compare Register Bytes
+&72 constant OCR1B \ Timer/Counter1 Output Compare Register Bytes
+&120 constant OCR1C \ Timer/Counter1 Output Compare Register Bytes
+&70 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
+\ TIMER_COUNTER_2
+&69 constant TCCR2 \ Timer/Counter Control Register
+ $80 constant TCCR2_FOC2 \ Force Output Compare
+ $40 constant TCCR2_WGM20 \ Wafeform Generation Mode
+ $30 constant TCCR2_COM2 \ Compare Match Output Mode
+ $08 constant TCCR2_WGM21 \ Waveform Generation Mode
+ $07 constant TCCR2_CS2 \ Clock Select
+&68 constant TCNT2 \ Timer/Counter Register
+&67 constant OCR2 \ Output Compare Register
+\ TIMER_COUNTER_3
+&139 constant TCCR3A \ Timer/Counter3 Control Register A
+ $C0 constant TCCR3A_COM3A \ Compare Output Mode 3A, bits
+ $30 constant TCCR3A_COM3B \ Compare Output Mode 3B, bits
+ $0C constant TCCR3A_COM3C \ Compare Output Mode 3C, bits
+ $03 constant TCCR3A_WGM3 \ Waveform Generation Mode Bits
+&138 constant TCCR3B \ Timer/Counter3 Control Register B
+ $80 constant TCCR3B_ICNC3 \ Input Capture 3 Noise Canceler
+ $40 constant TCCR3B_ICES3 \ Input Capture 3 Edge Select
+ $18 constant TCCR3B_WGM3 \ Waveform Generation Mode
+ $07 constant TCCR3B_CS3 \ Clock Select3 bits
+&140 constant TCCR3C \ Timer/Counter3 Control Register C
+ $80 constant TCCR3C_FOC3A \ Force Output Compare for channel A
+ $40 constant TCCR3C_FOC3B \ Force Output Compare for channel B
+ $20 constant TCCR3C_FOC3C \ Force Output Compare for channel C
+&136 constant TCNT3 \ Timer/Counter3 Bytes
+&134 constant OCR3A \ Timer/Counter3 Output Compare Register A Bytes
+&132 constant OCR3B \ Timer/Counter3 Output Compare Register B Bytes
+&130 constant OCR3C \ Timer/Counter3 Output compare Register C Bytes
+&128 constant ICR3 \ Timer/Counter3 Input Capture Register Bytes
+\ WATCHDOG
+&65 constant WDTCR \ Watchdog Timer Control Register
+ $10 constant WDTCR_WDCE \ Watchdog Change Enable
+ $08 constant WDTCR_WDE \ Watch Dog Enable
+ $07 constant WDTCR_WDP \ Watch Dog Timer Prescaler bits
+
+\ Interrupts
+&2 constant INT0Addr \ External Interrupt Request 0
+&4 constant INT1Addr \ External Interrupt Request 1
+&6 constant INT2Addr \ External Interrupt Request 2
+&8 constant INT3Addr \ External Interrupt Request 3
+&10 constant INT4Addr \ External Interrupt Request 4
+&12 constant INT5Addr \ External Interrupt Request 5
+&14 constant INT6Addr \ External Interrupt Request 6
+&16 constant INT7Addr \ External Interrupt Request 7
+&18 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
+&20 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
+&22 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+&24 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
+&26 constant TIMER1_COMPBAddr \ Timer/Counter Compare Match B
+&28 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+&30 constant TIMER0_COMPAddr \ Timer/Counter0 Compare Match
+&32 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
+&34 constant SPI__STCAddr \ SPI Serial Transfer Complete
+&36 constant USART0__RXAddr \ USART0, Rx Complete
+&38 constant USART0__UDREAddr \ USART0 Data Register Empty
+&40 constant USART0__TXAddr \ USART0, Tx Complete
+&42 constant ADCAddr \ ADC Conversion Complete
+&44 constant EE_READYAddr \ EEPROM Ready
+&46 constant ANALOG_COMPAddr \ Analog Comparator
+&48 constant TIMER1_COMPCAddr \ Timer/Counter1 Compare Match C
+&50 constant TIMER3_CAPTAddr \ Timer/Counter3 Capture Event
+&52 constant TIMER3_COMPAAddr \ Timer/Counter3 Compare Match A
+&54 constant TIMER3_COMPBAddr \ Timer/Counter3 Compare Match B
+&56 constant TIMER3_COMPCAddr \ Timer/Counter3 Compare Match C
+&58 constant TIMER3_OVFAddr \ Timer/Counter3 Overflow
+&60 constant USART1__RXAddr \ USART1, Rx Complete
+&62 constant USART1__UDREAddr \ USART1, Data Register Empty
+&64 constant USART1__TXAddr \ USART1, Tx Complete
+&66 constant TWIAddr \ 2-wire Serial Interface
+&68 constant SPM_READYAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/atmega64a/device.asm b/amforth-6.5/avr8/devices/atmega64a/device.asm
new file mode 100644
index 0000000..ac325a3
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega64a/device.asm
@@ -0,0 +1,135 @@
+; Partname: ATmega64A
+; generated automatically, do not edit
+
+.nolist
+ .include "m64Adef.inc"
+.list
+
+.equ ramstart = 256
+.equ CELLSIZE = 2
+.macro readflashcell
+ lsl zl
+ rol zh
+ lpm @0, Z+
+ lpm @1, Z+
+.endmacro
+.macro writeflashcell
+ lsl zl
+ rol zh
+.endmacro
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_AD_CONVERTER = 0
+.set WANT_SPI = 0
+.set WANT_TWI = 0
+.set WANT_USART0 = 0
+.set WANT_USART1 = 0
+.set WANT_CPU = 0
+.set WANT_BOOT_LOAD = 0
+.set WANT_JTAG = 0
+.set WANT_MISC = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_EEPROM = 0
+.set WANT_PORTA = 0
+.set WANT_PORTB = 0
+.set WANT_PORTC = 0
+.set WANT_PORTD = 0
+.set WANT_PORTE = 0
+.set WANT_PORTF = 0
+.set WANT_PORTG = 0
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_TIMER_COUNTER_2 = 0
+.set WANT_TIMER_COUNTER_3 = 0
+.set WANT_WATCHDOG = 0
+.equ intvecsize = 2 ; please verify; flash size: 65536 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.org 2
+ rcall isr ; External Interrupt Request 0
+.org 4
+ rcall isr ; External Interrupt Request 1
+.org 6
+ rcall isr ; External Interrupt Request 2
+.org 8
+ rcall isr ; External Interrupt Request 3
+.org 10
+ rcall isr ; External Interrupt Request 4
+.org 12
+ rcall isr ; External Interrupt Request 5
+.org 14
+ rcall isr ; External Interrupt Request 6
+.org 16
+ rcall isr ; External Interrupt Request 7
+.org 18
+ rcall isr ; Timer/Counter2 Compare Match
+.org 20
+ rcall isr ; Timer/Counter2 Overflow
+.org 22
+ rcall isr ; Timer/Counter1 Capture Event
+.org 24
+ rcall isr ; Timer/Counter1 Compare Match A
+.org 26
+ rcall isr ; Timer/Counter Compare Match B
+.org 28
+ rcall isr ; Timer/Counter1 Overflow
+.org 30
+ rcall isr ; Timer/Counter0 Compare Match
+.org 32
+ rcall isr ; Timer/Counter0 Overflow
+.org 34
+ rcall isr ; SPI Serial Transfer Complete
+.org 36
+ rcall isr ; USART0, Rx Complete
+.org 38
+ rcall isr ; USART0 Data Register Empty
+.org 40
+ rcall isr ; USART0, Tx Complete
+.org 42
+ rcall isr ; ADC Conversion Complete
+.org 44
+ rcall isr ; EEPROM Ready
+.org 46
+ rcall isr ; Analog Comparator
+.org 48
+ rcall isr ; Timer/Counter1 Compare Match C
+.org 50
+ rcall isr ; Timer/Counter3 Capture Event
+.org 52
+ rcall isr ; Timer/Counter3 Compare Match A
+.org 54
+ rcall isr ; Timer/Counter3 Compare Match B
+.org 56
+ rcall isr ; Timer/Counter3 Compare Match C
+.org 58
+ rcall isr ; Timer/Counter3 Overflow
+.org 60
+ rcall isr ; USART1, Rx Complete
+.org 62
+ rcall isr ; USART1, Data Register Empty
+.org 64
+ rcall isr ; USART1, Tx Complete
+.org 66
+ rcall isr ; 2-wire Serial Interface
+.org 68
+ rcall isr ; Store Program Memory Read
+.equ INTVECTORS = 35
+.nooverlap
+
+; compatability layer (maybe empty)
+.equ EEPE = EEWE
+.equ EEMPE = EEMWE
+
+; controller data area, environment query mcu-info
+mcu_info:
+mcu_ramsize:
+ .dw 4096
+mcu_eepromsize:
+ .dw 2048
+mcu_maxdp:
+ .dw 57344
+mcu_numints:
+ .dw 35
+mcu_name:
+ .dw 9
+ .db "ATmega64A",0
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega64a/device.inc b/amforth-6.5/avr8/devices/atmega64a/device.inc
new file mode 100644
index 0000000..c18844e
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega64a/device.inc
@@ -0,0 +1,1179 @@
+; Partname: ATmega64A
+; generated automatically, no not edit
+
+.if WANT_ANALOG_COMPARATOR == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Special Function IO Register
+VE_SFIOR:
+ .dw $ff05
+ .db "SFIOR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SFIOR
+XT_SFIOR:
+ .dw PFA_DOVARIABLE
+PFA_SFIOR:
+ .dw 64
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Control And Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw 40
+
+.endif
+.if WANT_AD_CONVERTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC multiplexer Selection Register
+VE_ADMUX:
+ .dw $ff05
+ .db "ADMUX",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADMUX
+XT_ADMUX:
+ .dw PFA_DOVARIABLE
+PFA_ADMUX:
+ .dw 39
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register Bytes
+VE_ADC:
+ .dw $ff03
+ .db "ADC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADC
+XT_ADC:
+ .dw PFA_DOVARIABLE
+PFA_ADC:
+ .dw 36
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register A
+VE_ADCSRA:
+ .dw $ff06
+ .db "ADCSRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRA
+XT_ADCSRA:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRA:
+ .dw 38
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register B
+VE_ADCSRB:
+ .dw $ff06
+ .db "ADCSRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRB
+XT_ADCSRB:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRB:
+ .dw 142
+
+.endif
+.if WANT_SPI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR:
+ .dw $ff04
+ .db "SPDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR
+XT_SPDR:
+ .dw PFA_DOVARIABLE
+PFA_SPDR:
+ .dw 47
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR:
+ .dw $ff04
+ .db "SPSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR
+XT_SPSR:
+ .dw PFA_DOVARIABLE
+PFA_SPSR:
+ .dw 46
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR:
+ .dw $ff04
+ .db "SPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR
+XT_SPCR:
+ .dw PFA_DOVARIABLE
+PFA_SPCR:
+ .dw 45
+
+.endif
+.if WANT_TWI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Bit Rate register
+VE_TWBR:
+ .dw $ff04
+ .db "TWBR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWBR
+XT_TWBR:
+ .dw PFA_DOVARIABLE
+PFA_TWBR:
+ .dw 112
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Control Register
+VE_TWCR:
+ .dw $ff04
+ .db "TWCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWCR
+XT_TWCR:
+ .dw PFA_DOVARIABLE
+PFA_TWCR:
+ .dw 116
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Status Register
+VE_TWSR:
+ .dw $ff04
+ .db "TWSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWSR
+XT_TWSR:
+ .dw PFA_DOVARIABLE
+PFA_TWSR:
+ .dw 113
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Data register
+VE_TWDR:
+ .dw $ff04
+ .db "TWDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWDR
+XT_TWDR:
+ .dw PFA_DOVARIABLE
+PFA_TWDR:
+ .dw 115
+; ( -- addr ) System Constant
+; R( -- )
+; TWI (Slave) Address register
+VE_TWAR:
+ .dw $ff04
+ .db "TWAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWAR
+XT_TWAR:
+ .dw PFA_DOVARIABLE
+PFA_TWAR:
+ .dw 114
+
+.endif
+.if WANT_USART0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR0:
+ .dw $ff04
+ .db "UDR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR0
+XT_UDR0:
+ .dw PFA_DOVARIABLE
+PFA_UDR0:
+ .dw 44
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR0A:
+ .dw $ff06
+ .db "UCSR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0A
+XT_UCSR0A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0A:
+ .dw 43
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR0B:
+ .dw $ff06
+ .db "UCSR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0B
+XT_UCSR0B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0B:
+ .dw 42
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR0C:
+ .dw $ff06
+ .db "UCSR0C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0C
+XT_UCSR0C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0C:
+ .dw 149
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Hight Byte
+VE_UBRR0H:
+ .dw $ff06
+ .db "UBRR0H"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR0H
+XT_UBRR0H:
+ .dw PFA_DOVARIABLE
+PFA_UBRR0H:
+ .dw 144
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Low Byte
+VE_UBRR0L:
+ .dw $ff06
+ .db "UBRR0L"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR0L
+XT_UBRR0L:
+ .dw PFA_DOVARIABLE
+PFA_UBRR0L:
+ .dw 41
+
+.endif
+.if WANT_USART1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR1:
+ .dw $ff04
+ .db "UDR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR1
+XT_UDR1:
+ .dw PFA_DOVARIABLE
+PFA_UDR1:
+ .dw 156
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR1A:
+ .dw $ff06
+ .db "UCSR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1A
+XT_UCSR1A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1A:
+ .dw 155
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR1B:
+ .dw $ff06
+ .db "UCSR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1B
+XT_UCSR1B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1B:
+ .dw 154
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR1C:
+ .dw $ff06
+ .db "UCSR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1C
+XT_UCSR1C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1C:
+ .dw 157
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Hight Byte
+VE_UBRR1H:
+ .dw $ff06
+ .db "UBRR1H"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR1H
+XT_UBRR1H:
+ .dw PFA_DOVARIABLE
+PFA_UBRR1H:
+ .dw 152
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Low Byte
+VE_UBRR1L:
+ .dw $ff06
+ .db "UBRR1L"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR1L
+XT_UBRR1L:
+ .dw PFA_DOVARIABLE
+PFA_UBRR1L:
+ .dw 153
+
+.endif
+.if WANT_CPU == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw 95
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer
+VE_SP:
+ .dw $ff02
+ .db "SP"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SP
+XT_SP:
+ .dw PFA_DOVARIABLE
+PFA_SP:
+ .dw 93
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw 85
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control And Status Register
+VE_MCUCSR:
+ .dw $ff06
+ .db "MCUCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCSR
+XT_MCUCSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCSR:
+ .dw 84
+; ( -- addr ) System Constant
+; R( -- )
+; External Memory Control Register A
+VE_XMCRA:
+ .dw $ff05
+ .db "XMCRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_XMCRA
+XT_XMCRA:
+ .dw PFA_DOVARIABLE
+PFA_XMCRA:
+ .dw 109
+; ( -- addr ) System Constant
+; R( -- )
+; External Memory Control Register B
+VE_XMCRB:
+ .dw $ff05
+ .db "XMCRB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_XMCRB
+XT_XMCRB:
+ .dw PFA_DOVARIABLE
+PFA_XMCRB:
+ .dw 108
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Calibration Value
+VE_OSCCAL:
+ .dw $ff06
+ .db "OSCCAL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSCCAL
+XT_OSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_OSCCAL:
+ .dw 111
+; ( -- addr ) System Constant
+; R( -- )
+; XTAL Divide Control Register
+VE_XDIV:
+ .dw $ff04
+ .db "XDIV"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_XDIV
+XT_XDIV:
+ .dw PFA_DOVARIABLE
+PFA_XDIV:
+ .dw 92
+
+.endif
+.if WANT_BOOT_LOAD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control Register
+VE_SPMCSR:
+ .dw $ff06
+ .db "SPMCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCSR
+XT_SPMCSR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCSR:
+ .dw 104
+
+.endif
+.if WANT_JTAG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; On-Chip Debug Related Register in I/O Memory
+VE_OCDR:
+ .dw $ff04
+ .db "OCDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCDR
+XT_OCDR:
+ .dw PFA_DOVARIABLE
+PFA_OCDR:
+ .dw 66
+
+.endif
+.if WANT_MISC == 1
+
+.endif
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register A
+VE_EICRA:
+ .dw $ff05
+ .db "EICRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRA
+XT_EICRA:
+ .dw PFA_DOVARIABLE
+PFA_EICRA:
+ .dw 106
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register B
+VE_EICRB:
+ .dw $ff05
+ .db "EICRB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRB
+XT_EICRB:
+ .dw PFA_DOVARIABLE
+PFA_EICRB:
+ .dw 90
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Mask Register
+VE_EIMSK:
+ .dw $ff05
+ .db "EIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIMSK
+XT_EIMSK:
+ .dw PFA_DOVARIABLE
+PFA_EIMSK:
+ .dw 89
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Flag Register
+VE_EIFR:
+ .dw $ff04
+ .db "EIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIFR
+XT_EIFR:
+ .dw PFA_DOVARIABLE
+PFA_EIFR:
+ .dw 88
+
+.endif
+.if WANT_EEPROM == 1
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Read/Write Access Bytes
+VE_EEAR:
+ .dw $ff04
+ .db "EEAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEAR
+XT_EEAR:
+ .dw PFA_DOVARIABLE
+PFA_EEAR:
+ .dw 62
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw 61
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw 60
+
+.endif
+.if WANT_PORTA == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Register
+VE_PORTA:
+ .dw $ff05
+ .db "PORTA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTA
+XT_PORTA:
+ .dw PFA_DOVARIABLE
+PFA_PORTA:
+ .dw 59
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Direction Register
+VE_DDRA:
+ .dw $ff04
+ .db "DDRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRA
+XT_DDRA:
+ .dw PFA_DOVARIABLE
+PFA_DDRA:
+ .dw 58
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Input Pins
+VE_PINA:
+ .dw $ff04
+ .db "PINA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINA
+XT_PINA:
+ .dw PFA_DOVARIABLE
+PFA_PINA:
+ .dw 57
+
+.endif
+.if WANT_PORTB == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw 56
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw 55
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw 54
+
+.endif
+.if WANT_PORTC == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Register
+VE_PORTC:
+ .dw $ff05
+ .db "PORTC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTC
+XT_PORTC:
+ .dw PFA_DOVARIABLE
+PFA_PORTC:
+ .dw 53
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Direction Register
+VE_DDRC:
+ .dw $ff04
+ .db "DDRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRC
+XT_DDRC:
+ .dw PFA_DOVARIABLE
+PFA_DDRC:
+ .dw 52
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Input Pins
+VE_PINC:
+ .dw $ff04
+ .db "PINC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINC
+XT_PINC:
+ .dw PFA_DOVARIABLE
+PFA_PINC:
+ .dw 51
+
+.endif
+.if WANT_PORTD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw 50
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw 49
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw 48
+
+.endif
+.if WANT_PORTE == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port E
+VE_PORTE:
+ .dw $ff05
+ .db "PORTE",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTE
+XT_PORTE:
+ .dw PFA_DOVARIABLE
+PFA_PORTE:
+ .dw 35
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port E
+VE_DDRE:
+ .dw $ff04
+ .db "DDRE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRE
+XT_DDRE:
+ .dw PFA_DOVARIABLE
+PFA_DDRE:
+ .dw 34
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port E
+VE_PINE:
+ .dw $ff04
+ .db "PINE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINE
+XT_PINE:
+ .dw PFA_DOVARIABLE
+PFA_PINE:
+ .dw 33
+
+.endif
+.if WANT_PORTF == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port F
+VE_PORTF:
+ .dw $ff05
+ .db "PORTF",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTF
+XT_PORTF:
+ .dw PFA_DOVARIABLE
+PFA_PORTF:
+ .dw 98
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port F
+VE_DDRF:
+ .dw $ff04
+ .db "DDRF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRF
+XT_DDRF:
+ .dw PFA_DOVARIABLE
+PFA_DDRF:
+ .dw 97
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port F
+VE_PINF:
+ .dw $ff04
+ .db "PINF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINF
+XT_PINF:
+ .dw PFA_DOVARIABLE
+PFA_PINF:
+ .dw 32
+
+.endif
+.if WANT_PORTG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port G
+VE_PORTG:
+ .dw $ff05
+ .db "PORTG",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTG
+XT_PORTG:
+ .dw PFA_DOVARIABLE
+PFA_PORTG:
+ .dw 101
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port G
+VE_DDRG:
+ .dw $ff04
+ .db "DDRG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRG
+XT_DDRG:
+ .dw PFA_DOVARIABLE
+PFA_DDRG:
+ .dw 100
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port G
+VE_PING:
+ .dw $ff04
+ .db "PING"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PING
+XT_PING:
+ .dw PFA_DOVARIABLE
+PFA_PING:
+ .dw 99
+
+.endif
+.if WANT_TIMER_COUNTER_0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register
+VE_TCCR0:
+ .dw $ff05
+ .db "TCCR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0
+XT_TCCR0:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0:
+ .dw 83
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Register
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw 82
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare Register
+VE_OCR0:
+ .dw $ff04
+ .db "OCR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0
+XT_OCR0:
+ .dw PFA_DOVARIABLE
+PFA_OCR0:
+ .dw 81
+; ( -- addr ) System Constant
+; R( -- )
+; Asynchronus Status Register
+VE_ASSR:
+ .dw $ff04
+ .db "ASSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ASSR
+XT_ASSR:
+ .dw PFA_DOVARIABLE
+PFA_ASSR:
+ .dw 80
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Mask Register
+VE_TIMSK:
+ .dw $ff05
+ .db "TIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK
+XT_TIMSK:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK:
+ .dw 87
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Flag register
+VE_TIFR:
+ .dw $ff04
+ .db "TIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR
+XT_TIFR:
+ .dw PFA_DOVARIABLE
+PFA_TIFR:
+ .dw 86
+
+.endif
+.if WANT_TIMER_COUNTER_1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Extended Timer/Counter Interrupt Mask Register
+VE_ETIMSK:
+ .dw $ff06
+ .db "ETIMSK"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ETIMSK
+XT_ETIMSK:
+ .dw PFA_DOVARIABLE
+PFA_ETIMSK:
+ .dw 125
+; ( -- addr ) System Constant
+; R( -- )
+; Extended Timer/Counter Interrupt Flag register
+VE_ETIFR:
+ .dw $ff05
+ .db "ETIFR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ETIFR
+XT_ETIFR:
+ .dw PFA_DOVARIABLE
+PFA_ETIFR:
+ .dw 124
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw 79
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw 78
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register C
+VE_TCCR1C:
+ .dw $ff06
+ .db "TCCR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1C
+XT_TCCR1C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1C:
+ .dw 122
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Bytes
+VE_TCNT1:
+ .dw $ff05
+ .db "TCNT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1
+XT_TCNT1:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1:
+ .dw 76
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register Bytes
+VE_OCR1A:
+ .dw $ff05
+ .db "OCR1A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1A
+XT_OCR1A:
+ .dw PFA_DOVARIABLE
+PFA_OCR1A:
+ .dw 74
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register Bytes
+VE_OCR1B:
+ .dw $ff05
+ .db "OCR1B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1B
+XT_OCR1B:
+ .dw PFA_DOVARIABLE
+PFA_OCR1B:
+ .dw 72
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register Bytes
+VE_OCR1C:
+ .dw $ff05
+ .db "OCR1C",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1C
+XT_OCR1C:
+ .dw PFA_DOVARIABLE
+PFA_OCR1C:
+ .dw 120
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Bytes
+VE_ICR1:
+ .dw $ff04
+ .db "ICR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1
+XT_ICR1:
+ .dw PFA_DOVARIABLE
+PFA_ICR1:
+ .dw 70
+
+.endif
+.if WANT_TIMER_COUNTER_2 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register
+VE_TCCR2:
+ .dw $ff05
+ .db "TCCR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2
+XT_TCCR2:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2:
+ .dw 69
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Register
+VE_TCNT2:
+ .dw $ff05
+ .db "TCNT2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT2
+XT_TCNT2:
+ .dw PFA_DOVARIABLE
+PFA_TCNT2:
+ .dw 68
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare Register
+VE_OCR2:
+ .dw $ff04
+ .db "OCR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2
+XT_OCR2:
+ .dw PFA_DOVARIABLE
+PFA_OCR2:
+ .dw 67
+
+.endif
+.if WANT_TIMER_COUNTER_3 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Control Register A
+VE_TCCR3A:
+ .dw $ff06
+ .db "TCCR3A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR3A
+XT_TCCR3A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR3A:
+ .dw 139
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Control Register B
+VE_TCCR3B:
+ .dw $ff06
+ .db "TCCR3B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR3B
+XT_TCCR3B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR3B:
+ .dw 138
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Control Register C
+VE_TCCR3C:
+ .dw $ff06
+ .db "TCCR3C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR3C
+XT_TCCR3C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR3C:
+ .dw 140
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Bytes
+VE_TCNT3:
+ .dw $ff05
+ .db "TCNT3",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT3
+XT_TCNT3:
+ .dw PFA_DOVARIABLE
+PFA_TCNT3:
+ .dw 136
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Output Compare Register A Bytes
+VE_OCR3A:
+ .dw $ff05
+ .db "OCR3A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR3A
+XT_OCR3A:
+ .dw PFA_DOVARIABLE
+PFA_OCR3A:
+ .dw 134
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Output Compare Register B Bytes
+VE_OCR3B:
+ .dw $ff05
+ .db "OCR3B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR3B
+XT_OCR3B:
+ .dw PFA_DOVARIABLE
+PFA_OCR3B:
+ .dw 132
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Output compare Register C Bytes
+VE_OCR3C:
+ .dw $ff05
+ .db "OCR3C",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR3C
+XT_OCR3C:
+ .dw PFA_DOVARIABLE
+PFA_OCR3C:
+ .dw 130
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter3 Input Capture Register Bytes
+VE_ICR3:
+ .dw $ff04
+ .db "ICR3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR3
+XT_ICR3:
+ .dw PFA_DOVARIABLE
+PFA_ICR3:
+ .dw 128
+
+.endif
+.if WANT_WATCHDOG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCR:
+ .dw $ff05
+ .db "WDTCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCR
+XT_WDTCR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCR:
+ .dw 65
+
+.endif
diff --git a/amforth-6.5/avr8/devices/atmega64a/device.py b/amforth-6.5/avr8/devices/atmega64a/device.py
new file mode 100644
index 0000000..b7ab9c9
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega64a/device.py
@@ -0,0 +1,405 @@
+# Generated Automatically
+
+# Partname ATmega64A
+
+MCUREGS = {
+# Interrupt Vectors
+ 'INT0Addr' : '#2', # External Interrupt Request 0
+ 'INT1Addr' : '#4', # External Interrupt Request 1
+ 'INT2Addr' : '#6', # External Interrupt Request 2
+ 'INT3Addr' : '#8', # External Interrupt Request 3
+ 'INT4Addr' : '#10', # External Interrupt Request 4
+ 'INT5Addr' : '#12', # External Interrupt Request 5
+ 'INT6Addr' : '#14', # External Interrupt Request 6
+ 'INT7Addr' : '#16', # External Interrupt Request 7
+ 'TIMER2_COMPAddr' : '#18', # Timer/Counter2 Compare Match
+ 'TIMER2_OVFAddr' : '#20', # Timer/Counter2 Overflow
+ 'TIMER1_CAPTAddr' : '#22', # Timer/Counter1 Capture Event
+ 'TIMER1_COMPAAddr' : '#24', # Timer/Counter1 Compare Match A
+ 'TIMER1_COMPBAddr' : '#26', # Timer/Counter Compare Match B
+ 'TIMER1_OVFAddr' : '#28', # Timer/Counter1 Overflow
+ 'TIMER0_COMPAddr' : '#30', # Timer/Counter0 Compare Match
+ 'TIMER0_OVFAddr' : '#32', # Timer/Counter0 Overflow
+ 'SPI_STCAddr' : '#34', # SPI Serial Transfer Complete
+ 'USART0_RXAddr' : '#36', # USART0, Rx Complete
+ 'USART0_UDREAddr' : '#38', # USART0 Data Register Empty
+ 'USART0_TXAddr' : '#40', # USART0, Tx Complete
+ 'ADCAddr' : '#42', # ADC Conversion Complete
+ 'EE_READYAddr' : '#44', # EEPROM Ready
+ 'ANALOG_COMPAddr' : '#46', # Analog Comparator
+ 'TIMER1_COMPCAddr' : '#48', # Timer/Counter1 Compare Match C
+ 'TIMER3_CAPTAddr' : '#50', # Timer/Counter3 Capture Event
+ 'TIMER3_COMPAAddr' : '#52', # Timer/Counter3 Compare Match A
+ 'TIMER3_COMPBAddr' : '#54', # Timer/Counter3 Compare Match B
+ 'TIMER3_COMPCAddr' : '#56', # Timer/Counter3 Compare Match C
+ 'TIMER3_OVFAddr' : '#58', # Timer/Counter3 Overflow
+ 'USART1_RXAddr' : '#60', # USART1, Rx Complete
+ 'USART1_UDREAddr' : '#62', # USART1, Data Register Empty
+ 'USART1_TXAddr' : '#64', # USART1, Tx Complete
+ 'TWIAddr' : '#66', # 2-wire Serial Interface
+ 'SPM_READYAddr' : '#68', # Store Program Memory Read
+
+# Module ANALOG_COMPARATOR
+ 'SFIOR' : '$40', # Special Function IO Register
+ 'SFIOR_ACME': '$8', # Analog Comparator Multiplexer
+ 'ACSR' : '$28', # Analog Comparator Control And
+ 'ACSR_ACD': '$80', # Analog Comparator Disable
+ 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
+ 'ACSR_ACO': '$20', # Analog Compare Output
+ 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
+ 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
+ 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
+ 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
+
+# Module AD_CONVERTER
+ 'ADMUX' : '$27', # The ADC multiplexer Selection
+ 'ADMUX_REFS': '$c0', # Reference Selection Bits
+ 'ADMUX_ADLAR': '$20', # Left Adjust Result
+ 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
+ 'ADC' : '$24', # ADC Data Register Bytes
+ 'ADCSRA' : '$26', # The ADC Control and Status reg
+ 'ADCSRA_ADEN': '$80', # ADC Enable
+ 'ADCSRA_ADSC': '$40', # ADC Start Conversion
+ 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
+ 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
+ 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
+ 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
+ 'ADCSRB' : '$8e', # The ADC Control and Status reg
+ 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Source bits
+
+# Module SPI
+ 'SPDR' : '$2f', # SPI Data Register
+ 'SPSR' : '$2e', # SPI Status Register
+ 'SPSR_SPIF': '$80', # SPI Interrupt Flag
+ 'SPSR_WCOL': '$40', # Write Collision Flag
+ 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
+ 'SPCR' : '$2d', # SPI Control Register
+ 'SPCR_SPIE': '$80', # SPI Interrupt Enable
+ 'SPCR_SPE': '$40', # SPI Enable
+ 'SPCR_DORD': '$20', # Data Order
+ 'SPCR_MSTR': '$10', # Master/Slave Select
+ 'SPCR_CPOL': '$8', # Clock polarity
+ 'SPCR_CPHA': '$4', # Clock Phase
+ 'SPCR_SPR': '$3', # SPI Clock Rate Selects
+
+# Module TWI
+ 'TWBR' : '$70', # TWI Bit Rate register
+ 'TWCR' : '$74', # TWI Control Register
+ 'TWCR_TWINT': '$80', # TWI Interrupt Flag
+ 'TWCR_TWEA': '$40', # TWI Enable Acknowledge Bit
+ 'TWCR_TWSTA': '$20', # TWI Start Condition Bit
+ 'TWCR_TWSTO': '$10', # TWI Stop Condition Bit
+ 'TWCR_TWWC': '$8', # TWI Write Collition Flag
+ 'TWCR_TWEN': '$4', # TWI Enable Bit
+ 'TWCR_TWIE': '$1', # TWI Interrupt Enable
+ 'TWSR' : '$71', # TWI Status Register
+ 'TWSR_TWS': '$f8', # TWI Status
+ 'TWSR_TWPS': '$3', # TWI Prescaler
+ 'TWDR' : '$73', # TWI Data register
+ 'TWAR' : '$72', # TWI (Slave) Address register
+ 'TWAR_TWA': '$fe', # TWI (Slave) Address register B
+ 'TWAR_TWGCE': '$1', # TWI General Call Recognition E
+
+# Module USART0
+ 'UDR0' : '$2c', # USART I/O Data Register
+ 'UCSR0A' : '$2b', # USART Control and Status Regis
+ 'UCSR0A_RXC0': '$80', # USART Receive Complete
+ 'UCSR0A_TXC0': '$40', # USART Transmitt Complete
+ 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
+ 'UCSR0A_FE0': '$10', # Framing Error
+ 'UCSR0A_DOR0': '$8', # Data overRun
+ 'UCSR0A_UPE0': '$4', # Parity Error
+ 'UCSR0A_U2X0': '$2', # Double the USART transmission
+ 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
+ 'UCSR0B' : '$2a', # USART Control and Status Regis
+ 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
+ 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
+ 'UCSR0B_UDRIE0': '$20', # USART Data register Empty Inte
+ 'UCSR0B_RXEN0': '$10', # Receiver Enable
+ 'UCSR0B_TXEN0': '$8', # Transmitter Enable
+ 'UCSR0B_UCSZ02': '$4', # Character Size
+ 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
+ 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
+ 'UCSR0C' : '$95', # USART Control and Status Regis
+ 'UCSR0C_UMSEL0': '$40', # USART Mode Select
+ 'UCSR0C_UPM0': '$30', # Parity Mode Bits
+ 'UCSR0C_USBS0': '$8', # Stop Bit Select
+ 'UCSR0C_UCSZ0': '$6', # Character Size
+ 'UCSR0C_UCPOL0': '$1', # Clock Polarity
+ 'UBRR0H' : '$90', # USART Baud Rate Register Hight
+ 'UBRR0L' : '$29', # USART Baud Rate Register Low B
+
+# Module USART1
+ 'UDR1' : '$9c', # USART I/O Data Register
+ 'UCSR1A' : '$9b', # USART Control and Status Regis
+ 'UCSR1A_RXC1': '$80', # USART Receive Complete
+ 'UCSR1A_TXC1': '$40', # USART Transmitt Complete
+ 'UCSR1A_UDRE1': '$20', # USART Data Register Empty
+ 'UCSR1A_FE1': '$10', # Framing Error
+ 'UCSR1A_DOR1': '$8', # Data overRun
+ 'UCSR1A_UPE1': '$4', # Parity Error
+ 'UCSR1A_U2X1': '$2', # Double the USART transmission
+ 'UCSR1A_MPCM1': '$1', # Multi-processor Communication
+ 'UCSR1B' : '$9a', # USART Control and Status Regis
+ 'UCSR1B_RXCIE1': '$80', # RX Complete Interrupt Enable
+ 'UCSR1B_TXCIE1': '$40', # TX Complete Interrupt Enable
+ 'UCSR1B_UDRIE1': '$20', # USART Data register Empty Inte
+ 'UCSR1B_RXEN1': '$10', # Receiver Enable
+ 'UCSR1B_TXEN1': '$8', # Transmitter Enable
+ 'UCSR1B_UCSZ12': '$4', # Character Size
+ 'UCSR1B_RXB81': '$2', # Receive Data Bit 8
+ 'UCSR1B_TXB81': '$1', # Transmit Data Bit 8
+ 'UCSR1C' : '$9d', # USART Control and Status Regis
+ 'UCSR1C_UMSEL1': '$40', # USART Mode Select
+ 'UCSR1C_UPM1': '$30', # Parity Mode Bits
+ 'UCSR1C_USBS1': '$8', # Stop Bit Select
+ 'UCSR1C_UCSZ1': '$6', # Character Size
+ 'UCSR1C_UCPOL1': '$1', # Clock Polarity
+ 'UBRR1H' : '$98', # USART Baud Rate Register Hight
+ 'UBRR1L' : '$99', # USART Baud Rate Register Low B
+
+# Module CPU
+ 'SREG' : '$5f', # Status Register
+ 'SREG_I': '$80', # Global Interrupt Enable
+ 'SREG_T': '$40', # Bit Copy Storage
+ 'SREG_H': '$20', # Half Carry Flag
+ 'SREG_S': '$10', # Sign Bit
+ 'SREG_V': '$8', # Two's Complement Overflow Flag
+ 'SREG_N': '$4', # Negative Flag
+ 'SREG_Z': '$2', # Zero Flag
+ 'SREG_C': '$1', # Carry Flag
+ 'SP' : '$5d', # Stack Pointer
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_SRE': '$80', # External SRAM Enable
+ 'MCUCR_SRW10': '$40', # External SRAM Wait State Selec
+ 'MCUCR_SE': '$20', # Sleep Enable
+ 'MCUCR_SM': '$18', # Sleep Mode Select
+ 'MCUCR_SM2': '$4', # Sleep Mode Select
+ 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
+ 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
+ 'MCUCSR' : '$54', # MCU Control And Status Registe
+ 'MCUCSR_JTD': '$80', # JTAG Interface Disable
+ 'MCUCSR_JTRF': '$10', # JTAG Reset Flag
+ 'MCUCSR_WDRF': '$8', # Watchdog Reset Flag
+ 'MCUCSR_BORF': '$4', # Brown-out Reset Flag
+ 'MCUCSR_EXTRF': '$2', # External Reset Flag
+ 'MCUCSR_PORF': '$1', # Power-on reset flag
+ 'XMCRA' : '$6d', # External Memory Control Regist
+ 'XMCRA_SRL': '$70', # Wait state page limit
+ 'XMCRA_SRW0': '$c', # Wait state select bit lower pa
+ 'XMCRA_SRW11': '$2', # Wait state select bit upper pa
+ 'XMCRB' : '$6c', # External Memory Control Regist
+ 'XMCRB_XMBK': '$80', # External Memory Bus Keeper Ena
+ 'XMCRB_XMM': '$7', # External Memory High Mask
+ 'OSCCAL' : '$6f', # Oscillator Calibration Value
+ 'XDIV' : '$5c', # XTAL Divide Control Register
+ 'XDIV_XDIVEN': '$80', # XTAL Divide Enable
+ 'XDIV_XDIV': '$7f', # XTAl Divide Select Bits
+
+# Module BOOT_LOAD
+ 'SPMCSR' : '$68', # Store Program Memory Control R
+ 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
+ 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
+ 'SPMCSR_RWWSRE': '$10', # Read While Write section read
+ 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
+ 'SPMCSR_PGWRT': '$4', # Page Write
+ 'SPMCSR_PGERS': '$2', # Page Erase
+ 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
+
+# Module JTAG
+ 'OCDR' : '$42', # On-Chip Debug Related Register
+ 'OCDR_OCDR': '$ff', # On-Chip Debug Register Bits
+ 'MCUCSR' : '$54', # MCU Control And Status Registe
+ 'MCUCSR_JTD': '$80', # JTAG Interface Disable
+ 'MCUCSR_JTRF': '$10', # JTAG Reset Flag
+
+# Module MISC
+ 'SFIOR' : '$40', # Special Function IO Register
+ 'SFIOR_TSM': '$80', # Timer/Counter Synchronization
+ 'SFIOR_ACME': '$8', # Analog Comparator Multiplexer
+ 'SFIOR_PUD': '$4', # Pull Up Disable
+ 'SFIOR_PSR0': '$2', # Prescaler Reset Timer/Counter0
+ 'SFIOR_PSR321': '$1', # Prescaler Reset Timer/Counter3
+
+# Module EXTERNAL_INTERRUPT
+ 'EICRA' : '$6a', # External Interrupt Control Reg
+ 'EICRA_ISC3': '$c0', # External Interrupt Sense Contr
+ 'EICRA_ISC2': '$30', # External Interrupt Sense Contr
+ 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
+ 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
+ 'EICRB' : '$5a', # External Interrupt Control Reg
+ 'EICRB_ISC7': '$c0', # External Interrupt 7-4 Sense C
+ 'EICRB_ISC6': '$30', # External Interrupt 7-4 Sense C
+ 'EICRB_ISC5': '$c', # External Interrupt 7-4 Sense C
+ 'EICRB_ISC4': '$3', # External Interrupt 7-4 Sense C
+ 'EIMSK' : '$59', # External Interrupt Mask Regist
+ 'EIMSK_INT': '$ff', # External Interrupt Request 7 E
+ 'EIFR' : '$58', # External Interrupt Flag Regist
+ 'EIFR_INTF': '$ff', # External Interrupt Flags
+
+# Module EEPROM
+ 'EEAR' : '$3e', # EEPROM Read/Write Access Byte
+ 'EEDR' : '$3d', # EEPROM Data Register
+ 'EECR' : '$3c', # EEPROM Control Register
+ 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
+ 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
+ 'EECR_EEWE': '$2', # EEPROM Write Enable
+ 'EECR_EERE': '$1', # EEPROM Read Enable
+
+# Module PORTA
+ 'PORTA' : '$3b', # Port A Data Register
+ 'DDRA' : '$3a', # Port A Data Direction Register
+ 'PINA' : '$39', # Port A Input Pins
+
+# Module PORTB
+ 'PORTB' : '$38', # Port B Data Register
+ 'DDRB' : '$37', # Port B Data Direction Register
+ 'PINB' : '$36', # Port B Input Pins
+
+# Module PORTC
+ 'PORTC' : '$35', # Port C Data Register
+ 'DDRC' : '$34', # Port C Data Direction Register
+ 'PINC' : '$33', # Port C Input Pins
+
+# Module PORTD
+ 'PORTD' : '$32', # Port D Data Register
+ 'DDRD' : '$31', # Port D Data Direction Register
+ 'PIND' : '$30', # Port D Input Pins
+
+# Module PORTE
+ 'PORTE' : '$23', # Data Register, Port E
+ 'DDRE' : '$22', # Data Direction Register, Port
+ 'PINE' : '$21', # Input Pins, Port E
+
+# Module PORTF
+ 'PORTF' : '$62', # Data Register, Port F
+ 'DDRF' : '$61', # Data Direction Register, Port
+ 'PINF' : '$20', # Input Pins, Port F
+
+# Module PORTG
+ 'PORTG' : '$65', # Data Register, Port G
+ 'DDRG' : '$64', # Data Direction Register, Port
+ 'PING' : '$63', # Input Pins, Port G
+
+# Module TIMER_COUNTER_0
+ 'TCCR0' : '$53', # Timer/Counter Control Register
+ 'TCCR0_FOC0': '$80', # Force Output Compare
+ 'TCCR0_WGM00': '$40', # Waveform Generation Mode 0
+ 'TCCR0_COM0': '$30', # Compare Match Output Modes
+ 'TCCR0_WGM01': '$8', # Waveform Generation Mode 1
+ 'TCCR0_CS0': '$7', # Clock Selects
+ 'TCNT0' : '$52', # Timer/Counter Register
+ 'OCR0' : '$51', # Output Compare Register
+ 'ASSR' : '$50', # Asynchronus Status Register
+ 'ASSR_AS0': '$8', # Asynchronus Timer/Counter 0
+ 'ASSR_TCN0UB': '$4', # Timer/Counter0 Update Busy
+ 'ASSR_OCR0UB': '$2', # Output Compare register 0 Busy
+ 'ASSR_TCR0UB': '$1', # Timer/Counter Control Register
+ 'TIMSK' : '$57', # Timer/Counter Interrupt Mask R
+ 'TIMSK_OCIE0': '$2', # Timer/Counter0 Output Compare
+ 'TIMSK_TOIE0': '$1', # Timer/Counter0 Overflow Interr
+ 'TIFR' : '$56', # Timer/Counter Interrupt Flag r
+ 'TIFR_OCF0': '$2', # Output Compare Flag 0
+ 'TIFR_TOV0': '$1', # Timer/Counter0 Overflow Flag
+ 'SFIOR' : '$40', # Special Function IO Register
+ 'SFIOR_TSM': '$80', # Timer/Counter Synchronization
+ 'SFIOR_PSR0': '$2', # Prescaler Reset Timer/Counter0
+
+# Module TIMER_COUNTER_1
+ 'TIMSK' : '$57', # Timer/Counter Interrupt Mask R
+ 'TIMSK_TICIE1': '$20', # Timer/Counter1 Input Capture I
+ 'TIMSK_OCIE1A': '$10', # Timer/Counter1 Output CompareA
+ 'TIMSK_OCIE1B': '$8', # Timer/Counter1 Output CompareB
+ 'TIMSK_TOIE1': '$4', # Timer/Counter1 Overflow Interr
+ 'ETIMSK' : '$7d', # Extended Timer/Counter Interru
+ 'ETIMSK_OCIE1C': '$1', # Timer/Counter 1, Output Compar
+ 'TIFR' : '$56', # Timer/Counter Interrupt Flag r
+ 'TIFR_ICF1': '$20', # Input Capture Flag 1
+ 'TIFR_OCF1A': '$10', # Output Compare Flag 1A
+ 'TIFR_OCF1B': '$8', # Output Compare Flag 1B
+ 'TIFR_TOV1': '$4', # Timer/Counter1 Overflow Flag
+ 'ETIFR' : '$7c', # Extended Timer/Counter Interru
+ 'ETIFR_OCF1C': '$1', # Timer/Counter 1, Output Compar
+ 'SFIOR' : '$40', # Special Function IO Register
+ 'SFIOR_TSM': '$80', # Timer/Counter Synchronization
+ 'SFIOR_PSR321': '$1', # Prescaler Reset, T/C3, T/C2, T
+ 'TCCR1A' : '$4f', # Timer/Counter1 Control Registe
+ 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
+ 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
+ 'TCCR1A_COM1C': '$c', # Compare Output Mode 1C, bits
+ 'TCCR1A_WGM1': '$3', # Waveform Generation Mode Bits
+ 'TCCR1B' : '$4e', # Timer/Counter1 Control Registe
+ 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
+ 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
+ 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
+ 'TCCR1B_CS1': '$7', # Clock Select1 bits
+ 'TCCR1C' : '$7a', # Timer/Counter1 Control Registe
+ 'TCCR1C_FOC1A': '$80', # Force Output Compare for chann
+ 'TCCR1C_FOC1B': '$40', # Force Output Compare for chann
+ 'TCCR1C_FOC1C': '$20', # Force Output Compare for chann
+ 'TCNT1' : '$4c', # Timer/Counter1 Bytes
+ 'OCR1A' : '$4a', # Timer/Counter1 Output Compare
+ 'OCR1B' : '$48', # Timer/Counter1 Output Compare
+ 'OCR1C' : '$78', # Timer/Counter1 Output Compare
+ 'ICR1' : '$46', # Timer/Counter1 Input Capture R
+
+# Module TIMER_COUNTER_2
+ 'TCCR2' : '$45', # Timer/Counter Control Register
+ 'TCCR2_FOC2': '$80', # Force Output Compare
+ 'TCCR2_WGM20': '$40', # Wafeform Generation Mode
+ 'TCCR2_COM2': '$30', # Compare Match Output Mode
+ 'TCCR2_WGM21': '$8', # Waveform Generation Mode
+ 'TCCR2_CS2': '$7', # Clock Select
+ 'TCNT2' : '$44', # Timer/Counter Register
+ 'OCR2' : '$43', # Output Compare Register
+ 'TIFR' : '$56', # Timer/Counter Interrupt Flag R
+ 'TIFR_OCF2': '$80', # Output Compare Flag 2
+ 'TIFR_TOV2': '$40', # Timer/Counter2 Overflow Flag
+ 'TIMSK' : '$57', #
+ 'TIMSK_OCIE2': '$80', #
+ 'TIMSK_TOIE2': '$40', #
+
+# Module TIMER_COUNTER_3
+ 'ETIMSK' : '$7d', # Extended Timer/Counter Interru
+ 'ETIMSK_TICIE3': '$20', # Timer/Counter3 Input Capture I
+ 'ETIMSK_OCIE3A': '$10', # Timer/Counter3 Output CompareA
+ 'ETIMSK_OCIE3B': '$8', # Timer/Counter3 Output CompareB
+ 'ETIMSK_TOIE3': '$4', # Timer/Counter3 Overflow Interr
+ 'ETIMSK_OCIE3C': '$2', # Timer/Counter3, Output Compare
+ 'ETIFR' : '$7c', # Extended Timer/Counter Interru
+ 'ETIFR_ICF3': '$20', # Input Capture Flag 1
+ 'ETIFR_OCF3A': '$10', # Output Compare Flag 1A
+ 'ETIFR_OCF3B': '$8', # Output Compare Flag 1B
+ 'ETIFR_TOV3': '$4', # Timer/Counter3 Overflow Flag
+ 'ETIFR_OCF3C': '$2', # Timer/Counter3 Output Compare
+ 'SFIOR' : '$40', # Special Function IO Register
+ 'SFIOR_TSM': '$80', # Timer/Counter Synchronization
+ 'SFIOR_PSR321': '$1', # Prescaler Reset, T/C3, T/C2, T
+ 'TCCR3A' : '$8b', # Timer/Counter3 Control Registe
+ 'TCCR3A_COM3A': '$c0', # Compare Output Mode 3A, bits
+ 'TCCR3A_COM3B': '$30', # Compare Output Mode 3B, bits
+ 'TCCR3A_COM3C': '$c', # Compare Output Mode 3C, bits
+ 'TCCR3A_WGM3': '$3', # Waveform Generation Mode Bits
+ 'TCCR3B' : '$8a', # Timer/Counter3 Control Registe
+ 'TCCR3B_ICNC3': '$80', # Input Capture 3 Noise Cancele
+ 'TCCR3B_ICES3': '$40', # Input Capture 3 Edge Select
+ 'TCCR3B_WGM3': '$18', # Waveform Generation Mode
+ 'TCCR3B_CS3': '$7', # Clock Select3 bits
+ 'TCCR3C' : '$8c', # Timer/Counter3 Control Registe
+ 'TCCR3C_FOC3A': '$80', # Force Output Compare for chann
+ 'TCCR3C_FOC3B': '$40', # Force Output Compare for chann
+ 'TCCR3C_FOC3C': '$20', # Force Output Compare for chann
+ 'TCNT3' : '$88', # Timer/Counter3 Bytes
+ 'OCR3A' : '$86', # Timer/Counter3 Output Compare
+ 'OCR3B' : '$84', # Timer/Counter3 Output Compare
+ 'OCR3C' : '$82', # Timer/Counter3 Output compare
+ 'ICR3' : '$80', # Timer/Counter3 Input Capture R
+
+# Module WATCHDOG
+ 'WDTCR' : '$41', # Watchdog Timer Control Registe
+ 'WDTCR_WDCE': '$10', # Watchdog Change Enable
+ 'WDTCR_WDE': '$8', # Watch Dog Enable
+ 'WDTCR_WDP': '$7', # Watch Dog Timer Prescaler bits
+
+ '__amforth_dummy':'0'
+}
diff --git a/amforth-6.5/avr8/devices/atmega64a/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega64a/words/no-jtag.asm
new file mode 100644
index 0000000..352a4bb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega64a/words/no-jtag.asm
@@ -0,0 +1,14 @@
+; ( -- )
+; ( -- )
+; MCU
+; disable jtag at runtime
+VE_NOJTAG:
+ .dw $FF05
+ .db "-jtag",0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOJTAG
+XT_NOJTAG:
+ .dw PFA_NOJTAG
+PFA_NOJTAG:
+
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega64a/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega64a/words/no-wdt.asm
new file mode 100644
index 0000000..4a12261
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega64a/words/no-wdt.asm
@@ -0,0 +1,22 @@
+; ( -- )
+; MCU
+; disable watch dog timer at runtime
+VE_NOWDT:
+ .dw $ff04
+ .db "-wdt"
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOWDT
+XT_NOWDT:
+ .dw PFA_NOWDT
+PFA_NOWDT:
+
+; Reset WDT
+ wdr
+; Write logical one to WDTOE and WDE
+ in_ temp1, WDTCR
+ ori temp1, (1<<WDTOE)|(1<<WDE)
+ out WDTCR, temp1
+; Turn off WDT
+ ldi temp1, (0<<WDE)
+ out_ WDTCR, temp1
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega64a/words/sleep.asm b/amforth-6.5/avr8/devices/atmega64a/words/sleep.asm
new file mode 100644
index 0000000..778fa32
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega64a/words/sleep.asm
@@ -0,0 +1,24 @@
+; ( mode -- )
+; MCU
+; put the controller into the specified sleep mode
+VE_SLEEP:
+ .dw $ff05
+ .db "sleep", 0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_SLEEP
+XT_SLEEP:
+ .dw PFA_SLEEP
+PFA_SLEEP:
+ andi tosl, 7 ; leave only legal mode bits
+ swap tosl ; move to correct location (bits 6-4, atmega32)
+ ori tosl, $80 ; set the SE bit (atmega32: bit 7, not bit 0)
+ out_ MCUCR, tosl ; set the sleep config (atmega32: MCUCR not SMCR)
+ sleep ; nighty-night
+;; the 4 lower bits of MCUCR should not be touched
+ in_ tosl, MCUCR
+ andi tosl, $0F
+ out_ MCUCR, tosl
+ ;clr tosl ; need to clean up the SMCR reg before we leave
+ ;out SMCR, tosl ; 0 protects against accidental sleeps
+ loadtos ; pop argument from stack
+ jmp DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega64c1/atmega64c1.frt b/amforth-6.5/avr8/devices/atmega64c1/atmega64c1.frt
new file mode 100644
index 0000000..e309d02
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega64c1/atmega64c1.frt
@@ -0,0 +1,454 @@
+\ Partname: ATmega64C1
+\ generated automatically
+
+\ PORTB
+&37 constant PORTB \ Port B Data Register
+&36 constant DDRB \ Port B Data Direction Register
+&35 constant PINB \ Port B Input Pins
+\ PORTC
+&40 constant PORTC \ Port C Data Register
+&39 constant DDRC \ Port C Data Direction Register
+&38 constant PINC \ Port C Input Pins
+\ PORTD
+&43 constant PORTD \ Port D Data Register
+&42 constant DDRD \ Port D Data Direction Register
+&41 constant PIND \ Port D Input Pins
+\ CAN
+&216 constant CANGCON \ CAN General Control Register
+ $80 constant CANGCON_ABRQ \ Abort Request
+ $40 constant CANGCON_OVRQ \ Overload Frame Request
+ $20 constant CANGCON_TTC \ Time Trigger Communication
+ $10 constant CANGCON_SYNTTC \ Synchronization of TTC
+ $08 constant CANGCON_LISTEN \ Listening Mode
+ $04 constant CANGCON_TEST \ Test Mode
+ $02 constant CANGCON_ENASTB \ Enable / Standby
+ $01 constant CANGCON_SWRES \ Software Reset Request
+&217 constant CANGSTA \ CAN General Status Register
+ $40 constant CANGSTA_OVFG \ Overload Frame Flag
+ $10 constant CANGSTA_TXBSY \ Transmitter Busy
+ $08 constant CANGSTA_RXBSY \ Receiver Busy
+ $04 constant CANGSTA_ENFG \ Enable Flag
+ $02 constant CANGSTA_BOFF \ Bus Off Mode
+ $01 constant CANGSTA_ERRP \ Error Passive Mode
+&218 constant CANGIT \ CAN General Interrupt Register Flags
+ $80 constant CANGIT_CANIT \ General Interrupt Flag
+ $40 constant CANGIT_BOFFIT \ Bus Off Interrupt Flag
+ $20 constant CANGIT_OVRTIM \ Overrun CAN Timer Flag
+ $10 constant CANGIT_BXOK \ Burst Receive Interrupt Flag
+ $08 constant CANGIT_SERG \ Stuff Error General Flag
+ $04 constant CANGIT_CERG \ CRC Error General Flag
+ $02 constant CANGIT_FERG \ Form Error General Flag
+ $01 constant CANGIT_AERG \ Ackknowledgement Error General Flag
+&219 constant CANGIE \ CAN General Interrupt Enable Register
+ $80 constant CANGIE_ENIT \ Enable all Interrupts
+ $40 constant CANGIE_ENBOFF \ Enable Bus Off Interrupt
+ $20 constant CANGIE_ENRX \ Enable Receive Interrupt
+ $10 constant CANGIE_ENTX \ Enable Transmitt Interrupt
+ $08 constant CANGIE_ENERR \ Enable MOb Error Interrupt
+ $04 constant CANGIE_ENBX \ Enable Burst Receive Interrupt
+ $02 constant CANGIE_ENERG \ Enable General Error Interrupt
+ $01 constant CANGIE_ENOVRT \ Enable CAN Timer Overrun Interrupt
+&220 constant CANEN2 \ Enable MOb Register 2
+ $3F constant CANEN2_ENMOB \ Enable MObs
+&221 constant CANEN1 \ Enable MOb Register 1(empty)
+&222 constant CANIE2 \ Enable Interrupt MOb Register 2
+ $3F constant CANIE2_IEMOB \ Interrupt Enable MObs
+&223 constant CANIE1 \ Enable Interrupt MOb Register 1 (empty)
+&224 constant CANSIT2 \ CAN Status Interrupt MOb Register 2
+ $3F constant CANSIT2_SIT \ Status of Interrupt MObs
+&225 constant CANSIT1 \ CAN Status Interrupt MOb Register 1 (empty)
+&226 constant CANBT1 \ CAN Bit Timing Register 1
+ $7E constant CANBT1_BRP \ Baud Rate Prescaler bits
+&227 constant CANBT2 \ CAN Bit Timing Register 2
+ $60 constant CANBT2_SJW \ Re-Sync Jump Width bits
+ $0E constant CANBT2_PRS \ Propagation Time Segment bits
+&228 constant CANBT3 \ CAN Bit Timing Register 3
+ $70 constant CANBT3_PHS2 \ Phase Segment 2 bits
+ $0E constant CANBT3_PHS1 \ Phase Segment 1 bits
+ $01 constant CANBT3_SMP \ Sample Type
+&229 constant CANTCON \ Timer Control Register
+&230 constant CANTIML \ Timer Register Low
+&231 constant CANTIMH \ Timer Register High
+&232 constant CANTTCL \ TTC Timer Register Low
+&233 constant CANTTCH \ TTC Timer Register High
+&234 constant CANTEC \ Transmit Error Counter Register
+&235 constant CANREC \ Receive Error Counter Register
+&236 constant CANHPMOB \ Highest Priority MOb Register
+ $F0 constant CANHPMOB_HPMOB \ Highest Priority MOb Number bits
+ $0F constant CANHPMOB_CGP \ CAN General Purpose bits
+&237 constant CANPAGE \ Page MOb Register
+ $F0 constant CANPAGE_MOBNB \ MOb Number bits
+ $08 constant CANPAGE_AINC \ MOb Data Buffer Auto Increment (Active Low)
+ $07 constant CANPAGE_INDX \ Data Buffer Index bits
+&238 constant CANSTMOB \ MOb Status Register
+ $80 constant CANSTMOB_DLCW \ Data Length Code Warning on MOb
+ $40 constant CANSTMOB_TXOK \ Transmit OK on MOb
+ $20 constant CANSTMOB_RXOK \ Receive OK on MOb
+ $10 constant CANSTMOB_BERR \ Bit Error on MOb
+ $08 constant CANSTMOB_SERR \ Stuff Error on MOb
+ $04 constant CANSTMOB_CERR \ CRC Error on MOb
+ $02 constant CANSTMOB_FERR \ Form Error on MOb
+ $01 constant CANSTMOB_AERR \ Ackknowledgement Error on MOb
+&239 constant CANCDMOB \ MOb Control and DLC Register
+ $C0 constant CANCDMOB_CONMOB \ MOb Config bits
+ $20 constant CANCDMOB_RPLV \ Reply Valid
+ $10 constant CANCDMOB_IDE \ Identifier Extension
+ $0F constant CANCDMOB_DLC \ Data Length Code bits
+&240 constant CANIDT4 \ Identifier Tag Register 4
+ $F8 constant CANIDT4_IDT \
+ $04 constant CANIDT4_RTRTAG \
+ $02 constant CANIDT4_RB1TAG \
+ $01 constant CANIDT4_RB0TAG \
+&241 constant CANIDT3 \ Identifier Tag Register 3
+&242 constant CANIDT2 \ Identifier Tag Register 2
+&243 constant CANIDT1 \ Identifier Tag Register 1
+&244 constant CANIDM4 \ Identifier Mask Register 4
+&245 constant CANIDM3 \ Identifier Mask Register 3
+&246 constant CANIDM2 \ Identifier Mask Register 2
+&247 constant CANIDM1 \ Identifier Mask Register 1
+&248 constant CANSTML \ Time Stamp Register Low
+&249 constant CANSTMH \ Time Stamp Register High
+&250 constant CANMSG \ Message Data Register
+\ ANALOG_COMPARATOR
+&148 constant AC0CON \ Analog Comparator 0 Control Register
+ $80 constant AC0CON_AC0EN \ Analog Comparator 0 Enable Bit
+ $40 constant AC0CON_AC0IE \ Analog Comparator 0 Interrupt Enable Bit
+ $30 constant AC0CON_AC0IS \ Analog Comparator 0 Interrupt Select Bits
+ $08 constant AC0CON_ACCKSEL \ Analog Comparator Clock Select
+ $07 constant AC0CON_AC0M \ Analog Comparator 0 Multiplexer Register
+&149 constant AC1CON \ Analog Comparator 1 Control Register
+ $80 constant AC1CON_AC1EN \ Analog Comparator 1 Enable Bit
+ $40 constant AC1CON_AC1IE \ Analog Comparator 1 Interrupt Enable Bit
+ $30 constant AC1CON_AC1IS \ Analog Comparator 1 Interrupt Select Bit
+ $08 constant AC1CON_AC1ICE \ Analog Comparator 1 Interrupt Capture Enable Bit
+ $07 constant AC1CON_AC1M \ Analog Comparator 1 Multiplexer Register
+&150 constant AC2CON \ Analog Comparator 2 Control Register
+ $80 constant AC2CON_AC2EN \ Analog Comparator 2 Enable Bit
+ $40 constant AC2CON_AC2IE \ Analog Comparator 2 Interrupt Enable Bit
+ $30 constant AC2CON_AC2IS \ Analog Comparator 2 Interrupt Select Bit
+ $07 constant AC2CON_AC2M \ Analog Comparator 2 Multiplexer Register
+&151 constant AC3CON \ Analog Comparator 3 Control Register
+ $80 constant AC3CON_AC3EN \ Analog Comparator 3 Enable Bit
+ $40 constant AC3CON_AC3IE \ Analog Comparator 3 Interrupt Enable Bit
+ $30 constant AC3CON_AC3IS \ Analog Comparator 3 Interrupt Select Bit
+ $07 constant AC3CON_AC3M \ Analog Comparator 3 Multiplexer Register
+&80 constant ACSR \ Analog Comparator Status Register
+ $80 constant ACSR_AC3IF \ Analog Comparator 3 Interrupt Flag Bit
+ $40 constant ACSR_AC2IF \ Analog Comparator 2 Interrupt Flag Bit
+ $20 constant ACSR_AC1IF \ Analog Comparator 1 Interrupt Flag Bit
+ $10 constant ACSR_AC0IF \ Analog Comparator 0 Interrupt Flag Bit
+ $08 constant ACSR_AC3O \ Analog Comparator 3 Output Bit
+ $04 constant ACSR_AC2O \ Analog Comparator 2 Output Bit
+ $02 constant ACSR_AC1O \ Analog Comparator 1 Output Bit
+ $01 constant ACSR_AC0O \ Analog Comparator 0 Output Bit
+\ DA_CONVERTER
+&146 constant DACH \ DAC Data Register High Byte
+ $FF constant DACH_DACH \ DAC Data Register High Byte Bits
+&145 constant DACL \ DAC Data Register Low Byte
+ $FF constant DACL_DACL \ DAC Data Register Low Byte Bits
+&144 constant DACON \ DAC Control Register
+ $80 constant DACON_DAATE \ DAC Auto Trigger Enable Bit
+ $70 constant DACON_DATS \ DAC Trigger Selection Bits
+ $04 constant DACON_DALA \ DAC Left Adjust
+ $01 constant DACON_DAEN \ DAC Enable Bit
+\ CPU
+&87 constant SPMCSR \ Store Program Memory Control Register
+ $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
+ $20 constant SPMCSR_SIGRD \ Signature Row Read
+ $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
+ $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
+ $04 constant SPMCSR_PGWRT \ Page Write
+ $02 constant SPMCSR_PGERS \ Page Erase
+ $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
+&95 constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ $08 constant SREG_V \ Two's Complement Overflow Flag
+ $04 constant SREG_N \ Negative Flag
+ $02 constant SREG_Z \ Zero Flag
+ $01 constant SREG_C \ Carry Flag
+&93 constant SP \ Stack Pointer
+&85 constant MCUCR \ MCU Control Register
+ $80 constant MCUCR_SPIPS \ SPI Pin Select
+ $10 constant MCUCR_PUD \ Pull-up disable
+ $02 constant MCUCR_IVSEL \ Interrupt Vector Select
+ $01 constant MCUCR_IVCE \ Interrupt Vector Change Enable
+&84 constant MCUSR \ MCU Status Register
+ $08 constant MCUSR_WDRF \ Watchdog Reset Flag
+ $04 constant MCUSR_BORF \ Brown-out Reset Flag
+ $02 constant MCUSR_EXTRF \ External Reset Flag
+ $01 constant MCUSR_PORF \ Power-on reset flag
+&102 constant OSCCAL \ Oscillator Calibration Value
+&97 constant CLKPR \
+ $80 constant CLKPR_CLKPCE \
+ $0F constant CLKPR_CLKPS \
+&83 constant SMCR \ Sleep Mode Control Register
+ $0E constant SMCR_SM \ Sleep Mode Select bits
+ $01 constant SMCR_SE \ Sleep Enable
+&58 constant GPIOR2 \ General Purpose IO Register 2
+ $FF constant GPIOR2_GPIOR \ General Purpose IO Register 2 bis
+&57 constant GPIOR1 \ General Purpose IO Register 1
+ $FF constant GPIOR1_GPIOR \ General Purpose IO Register 1 bis
+&62 constant GPIOR0 \ General Purpose IO Register 0
+ $80 constant GPIOR0_GPIOR07 \ General Purpose IO Register 0 bit 7
+ $40 constant GPIOR0_GPIOR06 \ General Purpose IO Register 0 bit 6
+ $20 constant GPIOR0_GPIOR05 \ General Purpose IO Register 0 bit 5
+ $10 constant GPIOR0_GPIOR04 \ General Purpose IO Register 0 bit 4
+ $08 constant GPIOR0_GPIOR03 \ General Purpose IO Register 0 bit 3
+ $04 constant GPIOR0_GPIOR02 \ General Purpose IO Register 0 bit 2
+ $02 constant GPIOR0_GPIOR01 \ General Purpose IO Register 0 bit 1
+ $01 constant GPIOR0_GPIOR00 \ General Purpose IO Register 0 bit 0
+&73 constant PLLCSR \ PLL Control And Status Register
+ $04 constant PLLCSR_PLLF \ PLL Factor
+ $02 constant PLLCSR_PLLE \ PLL Enable
+ $01 constant PLLCSR_PLOCK \ PLL Lock Detector
+&100 constant PRR \ Power Reduction Register
+ $40 constant PRR_PRCAN \ Power Reduction CAN
+ $20 constant PRR_PRPSC \ Power Reduction PSC
+ $10 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
+ $08 constant PRR_PRTIM0 \ Power Reduction Timer/Counter0
+ $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
+ $02 constant PRR_PRLIN \ Power Reduction LIN UART
+ $01 constant PRR_PRADC \ Power Reduction ADC
+\ PORTE
+&46 constant PORTE \ Port E Data Register
+&45 constant DDRE \ Port E Data Direction Register
+&44 constant PINE \ Port E Input Pins
+\ TIMER_COUNTER_0
+&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
+ $04 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare Match B Interrupt Enable
+ $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match A Interrupt Enable
+ $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
+&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
+ $04 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare Flag 0B
+ $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0A
+ $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
+&68 constant TCCR0A \ Timer/Counter Control Register A
+ $C0 constant TCCR0A_COM0A \ Compare Output Mode, Phase Correct PWM Mode
+ $30 constant TCCR0A_COM0B \ Compare Output Mode, Fast PWm
+ $03 constant TCCR0A_WGM0 \ Waveform Generation Mode
+&69 constant TCCR0B \ Timer/Counter Control Register B
+ $80 constant TCCR0B_FOC0A \ Force Output Compare A
+ $40 constant TCCR0B_FOC0B \ Force Output Compare B
+ $08 constant TCCR0B_WGM02 \
+ $07 constant TCCR0B_CS0 \ Clock Select
+&70 constant TCNT0 \ Timer/Counter0
+&71 constant OCR0A \ Timer/Counter0 Output Compare Register
+&72 constant OCR0B \ Timer/Counter0 Output Compare Register
+&67 constant GTCCR \ General Timer/Counter Control Register
+ $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
+ $40 constant GTCCR_ICPSEL1 \ Timer1 Input Capture Selection Bit
+ $01 constant GTCCR_PSR10 \ Prescaler Reset Timer/Counter1 and Timer/Counter0
+\ TIMER_COUNTER_1
+&111 constant TIMSK1 \ Timer/Counter Interrupt Mask Register
+ $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
+ $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output CompareB Match Interrupt Enable
+ $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output CompareA Match Interrupt Enable
+ $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
+&54 constant TIFR1 \ Timer/Counter Interrupt Flag register
+ $20 constant TIFR1_ICF1 \ Input Capture Flag 1
+ $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
+ $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
+ $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
+&128 constant TCCR1A \ Timer/Counter1 Control Register A
+ $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
+ $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
+ $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
+&129 constant TCCR1B \ Timer/Counter1 Control Register B
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
+ $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
+&130 constant TCCR1C \ Timer/Counter1 Control Register C
+ $80 constant TCCR1C_FOC1A \
+ $40 constant TCCR1C_FOC1B \
+&132 constant TCNT1 \ Timer/Counter1 Bytes
+&136 constant OCR1A \ Timer/Counter1 Output Compare Register Bytes
+&138 constant OCR1B \ Timer/Counter1 Output Compare Register Bytes
+&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
+\ AD_CONVERTER
+&124 constant ADMUX \ The ADC multiplexer Selection Register
+ $C0 constant ADMUX_REFS \ Reference Selection Bits
+ $20 constant ADMUX_ADLAR \ Left Adjust Result
+ $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
+&122 constant ADCSRA \ The ADC Control and Status register
+ $80 constant ADCSRA_ADEN \ ADC Enable
+ $40 constant ADCSRA_ADSC \ ADC Start Conversion
+ $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
+ $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
+ $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
+ $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
+&120 constant ADC \ ADC Data Register Bytes
+&123 constant ADCSRB \ ADC Control and Status Register B
+ $80 constant ADCSRB_ADHSM \ ADC High Speed Mode
+ $40 constant ADCSRB_ISRCEN \ Current Source Enable
+ $20 constant ADCSRB_AREFEN \ Analog Reference pin Enable
+ $0F constant ADCSRB_ADTS \ ADC Auto Trigger Sources
+&126 constant DIDR0 \ Digital Input Disable Register 0
+ $80 constant DIDR0_ADC7D \ ADC7 Digital input Disable
+ $40 constant DIDR0_ADC6D \ ADC6 Digital input Disable
+ $20 constant DIDR0_ADC5D \ ADC5 Digital input Disable
+ $10 constant DIDR0_ADC4D \ ADC4 Digital input Disable
+ $08 constant DIDR0_ADC3D \ ADC3 Digital input Disable
+ $04 constant DIDR0_ADC2D \ ADC2 Digital input Disable
+ $02 constant DIDR0_ADC1D \ ADC1 Digital input Disable
+ $01 constant DIDR0_ADC0D \ ADC0 Digital input Disable
+&127 constant DIDR1 \ Digital Input Disable Register 0
+ $40 constant DIDR1_AMP2PD \ AMP2P Pin Digital input Disable
+ $20 constant DIDR1_ACMP0D \ ACMP0 Pin Digital input Disable
+ $10 constant DIDR1_AMP0PD \ AMP0P Pin Digital input Disable
+ $08 constant DIDR1_AMP0ND \ AMP0N Pin Digital input Disable
+ $04 constant DIDR1_ADC10D \ ADC10 Pin Digital input Disable
+ $02 constant DIDR1_ADC9D \ ADC9 Pin Digital input Disable
+ $01 constant DIDR1_ADC8D \ ADC8 Pin Digital input Disable
+&117 constant AMP0CSR \
+ $80 constant AMP0CSR_AMP0EN \
+ $40 constant AMP0CSR_AMP0IS \
+ $30 constant AMP0CSR_AMP0G \
+ $08 constant AMP0CSR_AMPCMP0 \ Amplifier 0 - Comparator 0 Connection
+ $07 constant AMP0CSR_AMP0TS \
+&118 constant AMP1CSR \
+ $80 constant AMP1CSR_AMP1EN \
+ $40 constant AMP1CSR_AMP1IS \
+ $30 constant AMP1CSR_AMP1G \
+ $08 constant AMP1CSR_AMPCMP1 \ Amplifier 1 - Comparator 1 Connection
+ $07 constant AMP1CSR_AMP1TS \
+&119 constant AMP2CSR \
+ $80 constant AMP2CSR_AMP2EN \
+ $40 constant AMP2CSR_AMP2IS \
+ $30 constant AMP2CSR_AMP2G \
+ $08 constant AMP2CSR_AMPCMP2 \ Amplifier 2 - Comparator 2 Connection
+ $07 constant AMP2CSR_AMP2TS \
+\ LINUART
+&200 constant LINCR \ LIN Control Register
+ $80 constant LINCR_LSWRES \ Software Reset
+ $40 constant LINCR_LIN13 \ LIN Standard
+ $30 constant LINCR_LCONF \ LIN Configuration bits
+ $08 constant LINCR_LENA \ LIN or UART Enable
+ $07 constant LINCR_LCMD \ LIN Command and Mode bits
+&201 constant LINSIR \ LIN Status and Interrupt Register
+ $E0 constant LINSIR_LIDST \ Identifier Status bits
+ $10 constant LINSIR_LBUSY \ Busy Signal
+ $08 constant LINSIR_LERR \ Error Interrupt
+ $04 constant LINSIR_LIDOK \ Identifier Interrupt
+ $02 constant LINSIR_LTXOK \ Transmit Performed Interrupt
+ $01 constant LINSIR_LRXOK \ Receive Performed Interrupt
+&202 constant LINENIR \ LIN Enable Interrupt Register
+ $08 constant LINENIR_LENERR \ Enable Error Interrupt
+ $04 constant LINENIR_LENIDOK \ Enable Identifier Interrupt
+ $02 constant LINENIR_LENTXOK \ Enable Transmit Performed Interrupt
+ $01 constant LINENIR_LENRXOK \ Enable Receive Performed Interrupt
+&203 constant LINERR \ LIN Error Register
+ $80 constant LINERR_LABORT \ Abort Flag
+ $40 constant LINERR_LTOERR \ Frame Time Out Error Flag
+ $20 constant LINERR_LOVERR \ Overrun Error Flag
+ $10 constant LINERR_LFERR \ Framing Error Flag
+ $08 constant LINERR_LSERR \ Synchronization Error Flag
+ $04 constant LINERR_LPERR \ Parity Error Flag
+ $02 constant LINERR_LCERR \ Checksum Error Flag
+ $01 constant LINERR_LBERR \ Bit Error Flag
+&204 constant LINBTR \ LIN Bit Timing Register
+ $80 constant LINBTR_LDISR \ Disable Bit Timing Resynchronization
+ $3F constant LINBTR_LBT \ LIN Bit Timing bits
+&205 constant LINBRRL \ LIN Baud Rate Low Register
+ $FF constant LINBRRL_LDIV \
+&206 constant LINBRRH \ LIN Baud Rate High Register
+ $0F constant LINBRRH_LDIV \
+&207 constant LINDLR \ LIN Data Length Register
+ $F0 constant LINDLR_LTXDL \ LIN Transmit Data Length bits
+ $0F constant LINDLR_LRXDL \ LIN Receive Data Length bits
+&208 constant LINIDR \ LIN Identifier Register
+ $C0 constant LINIDR_LP \ Parity bits
+ $3F constant LINIDR_LID \ Identifier bit 5 or Data Length bits
+&209 constant LINSEL \ LIN Data Buffer Selection Register
+ $08 constant LINSEL_LAINC \ Auto Increment of Data Buffer Index (Active Low)
+ $07 constant LINSEL_LINDX \ FIFO LIN Data Buffer Index bits
+&210 constant LINDAT \ LIN Data Register
+ $FF constant LINDAT_LDATA \
+\ SPI
+&76 constant SPCR \ SPI Control Register
+ $80 constant SPCR_SPIE \ SPI Interrupt Enable
+ $40 constant SPCR_SPE \ SPI Enable
+ $20 constant SPCR_DORD \ Data Order
+ $10 constant SPCR_MSTR \ Master/Slave Select
+ $08 constant SPCR_CPOL \ Clock polarity
+ $04 constant SPCR_CPHA \ Clock Phase
+ $03 constant SPCR_SPR \ SPI Clock Rate Selects
+&77 constant SPSR \ SPI Status Register
+ $80 constant SPSR_SPIF \ SPI Interrupt Flag
+ $40 constant SPSR_WCOL \ Write Collision Flag
+ $01 constant SPSR_SPI2X \ Double SPI Speed Bit
+&78 constant SPDR \ SPI Data Register
+\ WATCHDOG
+&96 constant WDTCSR \ Watchdog Timer Control Register
+ $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Flag
+ $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Enable
+ $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
+ $10 constant WDTCSR_WDCE \ Watchdog Change Enable
+ $08 constant WDTCSR_WDE \ Watch Dog Enable
+\ EXTERNAL_INTERRUPT
+&105 constant EICRA \ External Interrupt Control Register
+ $C0 constant EICRA_ISC3 \ External Interrupt Sense Control Bit
+ $30 constant EICRA_ISC2 \ External Interrupt Sense Control Bit
+ $0C constant EICRA_ISC1 \ External Interrupt Sense Control 1 Bits
+ $03 constant EICRA_ISC0 \ External Interrupt Sense Control 0 Bits
+&61 constant EIMSK \ External Interrupt Mask Register
+ $0F constant EIMSK_INT \ External Interrupt Request 3 Enable
+&60 constant EIFR \ External Interrupt Flag Register
+ $0F constant EIFR_INTF \ External Interrupt Flags
+&104 constant PCICR \ Pin Change Interrupt Control Register
+ $0F constant PCICR_PCIE \ Pin Change Interrupt Enables
+&109 constant PCMSK3 \ Pin Change Mask Register 3
+ $07 constant PCMSK3_PCINT \ Pin Change Enable Masks
+&108 constant PCMSK2 \ Pin Change Mask Register 2
+ $FF constant PCMSK2_PCINT \ Pin Change Enable Masks
+&107 constant PCMSK1 \ Pin Change Mask Register 1
+ $FF constant PCMSK1_PCINT \ Pin Change Enable Masks
+&106 constant PCMSK0 \ Pin Change Mask Register 0
+ $FF constant PCMSK0_PCINT \ Pin Change Enable Masks
+&59 constant PCIFR \ Pin Change Interrupt Flag Register
+ $0F constant PCIFR_PCIF \ Pin Change Interrupt Flags
+\ EEPROM
+&65 constant EEAR \ EEPROM Read/Write Access
+&64 constant EEDR \ EEPROM Data Register
+&63 constant EECR \ EEPROM Control Register
+ $30 constant EECR_EEPM \
+ $08 constant EECR_EERIE \ EEProm Ready Interrupt Enable
+ $04 constant EECR_EEMWE \ EEPROM Master Write Enable
+ $02 constant EECR_EEWE \ EEPROM Write Enable
+ $01 constant EECR_EERE \ EEPROM Read Enable
+
+\ Interrupts
+&2 constant ANACOMP0Addr \ Analog Comparator 0
+&4 constant ANACOMP1Addr \ Analog Comparator 1
+&6 constant ANACOMP2Addr \ Analog Comparator 2
+&8 constant ANACOMP3Addr \ Analog Comparator 3
+&10 constant PSC_FAULTAddr \ PSC Fault
+&12 constant PSC_ECAddr \ PSC End of Cycle
+&14 constant INT0Addr \ External Interrupt Request 0
+&16 constant INT1Addr \ External Interrupt Request 1
+&18 constant INT2Addr \ External Interrupt Request 2
+&20 constant INT3Addr \ External Interrupt Request 3
+&22 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+&24 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
+&26 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
+&28 constant TIMER1_OVFAddr \ Timer1/Counter1 Overflow
+&30 constant TIMER0_COMPAAddr \ Timer/Counter0 Compare Match A
+&32 constant TIMER0_COMPBAddr \ Timer/Counter0 Compare Match B
+&34 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
+&36 constant CAN_INTAddr \ CAN MOB, Burst, General Errors
+&38 constant CAN_TOVFAddr \ CAN Timer Overflow
+&40 constant LIN_TCAddr \ LIN Transfer Complete
+&42 constant LIN_ERRAddr \ LIN Error
+&44 constant PCINT0Addr \ Pin Change Interrupt Request 0
+&46 constant PCINT1Addr \ Pin Change Interrupt Request 1
+&48 constant PCINT2Addr \ Pin Change Interrupt Request 2
+&50 constant PCINT3Addr \ Pin Change Interrupt Request 3
+&52 constant SPI__STCAddr \ SPI Serial Transfer Complete
+&54 constant ADCAddr \ ADC Conversion Complete
+&56 constant WDTAddr \ Watchdog Time-Out Interrupt
+&58 constant EE_READYAddr \ EEPROM Ready
+&60 constant SPM_READYAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/atmega64c1/device.asm b/amforth-6.5/avr8/devices/atmega64c1/device.asm
new file mode 100644
index 0000000..41f6d97
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega64c1/device.asm
@@ -0,0 +1,119 @@
+; Partname: ATmega64C1
+; generated automatically, do not edit
+
+.nolist
+ .include "m64C1def.inc"
+.list
+
+.equ ramstart = 256
+.equ CELLSIZE = 2
+.macro readflashcell
+ lsl zl
+ rol zh
+ lpm @0, Z+
+ lpm @1, Z+
+.endmacro
+.macro writeflashcell
+ lsl zl
+ rol zh
+.endmacro
+.set WANT_PORTB = 0
+.set WANT_PORTC = 0
+.set WANT_PORTD = 0
+.set WANT_CAN = 0
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_DA_CONVERTER = 0
+.set WANT_CPU = 0
+.set WANT_PORTE = 0
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_AD_CONVERTER = 0
+.set WANT_LINUART = 0
+.set WANT_SPI = 0
+.set WANT_WATCHDOG = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_EEPROM = 0
+.equ intvecsize = 2 ; please verify; flash size: 65536 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.org 2
+ rcall isr ; Analog Comparator 0
+.org 4
+ rcall isr ; Analog Comparator 1
+.org 6
+ rcall isr ; Analog Comparator 2
+.org 8
+ rcall isr ; Analog Comparator 3
+.org 10
+ rcall isr ; PSC Fault
+.org 12
+ rcall isr ; PSC End of Cycle
+.org 14
+ rcall isr ; External Interrupt Request 0
+.org 16
+ rcall isr ; External Interrupt Request 1
+.org 18
+ rcall isr ; External Interrupt Request 2
+.org 20
+ rcall isr ; External Interrupt Request 3
+.org 22
+ rcall isr ; Timer/Counter1 Capture Event
+.org 24
+ rcall isr ; Timer/Counter1 Compare Match A
+.org 26
+ rcall isr ; Timer/Counter1 Compare Match B
+.org 28
+ rcall isr ; Timer1/Counter1 Overflow
+.org 30
+ rcall isr ; Timer/Counter0 Compare Match A
+.org 32
+ rcall isr ; Timer/Counter0 Compare Match B
+.org 34
+ rcall isr ; Timer/Counter0 Overflow
+.org 36
+ rcall isr ; CAN MOB, Burst, General Errors
+.org 38
+ rcall isr ; CAN Timer Overflow
+.org 40
+ rcall isr ; LIN Transfer Complete
+.org 42
+ rcall isr ; LIN Error
+.org 44
+ rcall isr ; Pin Change Interrupt Request 0
+.org 46
+ rcall isr ; Pin Change Interrupt Request 1
+.org 48
+ rcall isr ; Pin Change Interrupt Request 2
+.org 50
+ rcall isr ; Pin Change Interrupt Request 3
+.org 52
+ rcall isr ; SPI Serial Transfer Complete
+.org 54
+ rcall isr ; ADC Conversion Complete
+.org 56
+ rcall isr ; Watchdog Time-Out Interrupt
+.org 58
+ rcall isr ; EEPROM Ready
+.org 60
+ rcall isr ; Store Program Memory Read
+.equ INTVECTORS = 31
+.nooverlap
+
+; compatability layer (maybe empty)
+.equ EEPE = EEWE
+.equ EEMPE = EEMWE
+
+; controller data area, environment query mcu-info
+mcu_info:
+mcu_ramsize:
+ .dw 4096
+mcu_eepromsize:
+ .dw 2048
+mcu_maxdp:
+ .dw 57344
+mcu_numints:
+ .dw 31
+mcu_name:
+ .dw 10
+ .db "ATmega64C1"
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega64c1/device.inc b/amforth-6.5/avr8/devices/atmega64c1/device.inc
new file mode 100644
index 0000000..09b0293
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega64c1/device.inc
@@ -0,0 +1,1503 @@
+; Partname: ATmega64C1
+; generated automatically, no not edit
+
+.if WANT_PORTB == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw 37
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw 36
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw 35
+
+.endif
+.if WANT_PORTC == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Register
+VE_PORTC:
+ .dw $ff05
+ .db "PORTC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTC
+XT_PORTC:
+ .dw PFA_DOVARIABLE
+PFA_PORTC:
+ .dw 40
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Direction Register
+VE_DDRC:
+ .dw $ff04
+ .db "DDRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRC
+XT_DDRC:
+ .dw PFA_DOVARIABLE
+PFA_DDRC:
+ .dw 39
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Input Pins
+VE_PINC:
+ .dw $ff04
+ .db "PINC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINC
+XT_PINC:
+ .dw PFA_DOVARIABLE
+PFA_PINC:
+ .dw 38
+
+.endif
+.if WANT_PORTD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw 43
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw 42
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw 41
+
+.endif
+.if WANT_CAN == 1
+; ( -- addr ) System Constant
+; R( -- )
+; CAN General Control Register
+VE_CANGCON:
+ .dw $ff07
+ .db "CANGCON",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANGCON
+XT_CANGCON:
+ .dw PFA_DOVARIABLE
+PFA_CANGCON:
+ .dw 216
+; ( -- addr ) System Constant
+; R( -- )
+; CAN General Status Register
+VE_CANGSTA:
+ .dw $ff07
+ .db "CANGSTA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANGSTA
+XT_CANGSTA:
+ .dw PFA_DOVARIABLE
+PFA_CANGSTA:
+ .dw 217
+; ( -- addr ) System Constant
+; R( -- )
+; CAN General Interrupt Register Flags
+VE_CANGIT:
+ .dw $ff06
+ .db "CANGIT"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANGIT
+XT_CANGIT:
+ .dw PFA_DOVARIABLE
+PFA_CANGIT:
+ .dw 218
+; ( -- addr ) System Constant
+; R( -- )
+; CAN General Interrupt Enable Register
+VE_CANGIE:
+ .dw $ff06
+ .db "CANGIE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANGIE
+XT_CANGIE:
+ .dw PFA_DOVARIABLE
+PFA_CANGIE:
+ .dw 219
+; ( -- addr ) System Constant
+; R( -- )
+; Enable MOb Register 2
+VE_CANEN2:
+ .dw $ff06
+ .db "CANEN2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANEN2
+XT_CANEN2:
+ .dw PFA_DOVARIABLE
+PFA_CANEN2:
+ .dw 220
+; ( -- addr ) System Constant
+; R( -- )
+; Enable MOb Register 1(empty)
+VE_CANEN1:
+ .dw $ff06
+ .db "CANEN1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANEN1
+XT_CANEN1:
+ .dw PFA_DOVARIABLE
+PFA_CANEN1:
+ .dw 221
+; ( -- addr ) System Constant
+; R( -- )
+; Enable Interrupt MOb Register 2
+VE_CANIE2:
+ .dw $ff06
+ .db "CANIE2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANIE2
+XT_CANIE2:
+ .dw PFA_DOVARIABLE
+PFA_CANIE2:
+ .dw 222
+; ( -- addr ) System Constant
+; R( -- )
+; Enable Interrupt MOb Register 1 (empty)
+VE_CANIE1:
+ .dw $ff06
+ .db "CANIE1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANIE1
+XT_CANIE1:
+ .dw PFA_DOVARIABLE
+PFA_CANIE1:
+ .dw 223
+; ( -- addr ) System Constant
+; R( -- )
+; CAN Status Interrupt MOb Register 2
+VE_CANSIT2:
+ .dw $ff07
+ .db "CANSIT2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANSIT2
+XT_CANSIT2:
+ .dw PFA_DOVARIABLE
+PFA_CANSIT2:
+ .dw 224
+; ( -- addr ) System Constant
+; R( -- )
+; CAN Status Interrupt MOb Register 1 (empty)
+VE_CANSIT1:
+ .dw $ff07
+ .db "CANSIT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANSIT1
+XT_CANSIT1:
+ .dw PFA_DOVARIABLE
+PFA_CANSIT1:
+ .dw 225
+; ( -- addr ) System Constant
+; R( -- )
+; CAN Bit Timing Register 1
+VE_CANBT1:
+ .dw $ff06
+ .db "CANBT1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANBT1
+XT_CANBT1:
+ .dw PFA_DOVARIABLE
+PFA_CANBT1:
+ .dw 226
+; ( -- addr ) System Constant
+; R( -- )
+; CAN Bit Timing Register 2
+VE_CANBT2:
+ .dw $ff06
+ .db "CANBT2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANBT2
+XT_CANBT2:
+ .dw PFA_DOVARIABLE
+PFA_CANBT2:
+ .dw 227
+; ( -- addr ) System Constant
+; R( -- )
+; CAN Bit Timing Register 3
+VE_CANBT3:
+ .dw $ff06
+ .db "CANBT3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANBT3
+XT_CANBT3:
+ .dw PFA_DOVARIABLE
+PFA_CANBT3:
+ .dw 228
+; ( -- addr ) System Constant
+; R( -- )
+; Timer Control Register
+VE_CANTCON:
+ .dw $ff07
+ .db "CANTCON",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANTCON
+XT_CANTCON:
+ .dw PFA_DOVARIABLE
+PFA_CANTCON:
+ .dw 229
+; ( -- addr ) System Constant
+; R( -- )
+; Timer Register Low
+VE_CANTIML:
+ .dw $ff07
+ .db "CANTIML",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANTIML
+XT_CANTIML:
+ .dw PFA_DOVARIABLE
+PFA_CANTIML:
+ .dw 230
+; ( -- addr ) System Constant
+; R( -- )
+; Timer Register High
+VE_CANTIMH:
+ .dw $ff07
+ .db "CANTIMH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANTIMH
+XT_CANTIMH:
+ .dw PFA_DOVARIABLE
+PFA_CANTIMH:
+ .dw 231
+; ( -- addr ) System Constant
+; R( -- )
+; TTC Timer Register Low
+VE_CANTTCL:
+ .dw $ff07
+ .db "CANTTCL",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANTTCL
+XT_CANTTCL:
+ .dw PFA_DOVARIABLE
+PFA_CANTTCL:
+ .dw 232
+; ( -- addr ) System Constant
+; R( -- )
+; TTC Timer Register High
+VE_CANTTCH:
+ .dw $ff07
+ .db "CANTTCH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANTTCH
+XT_CANTTCH:
+ .dw PFA_DOVARIABLE
+PFA_CANTTCH:
+ .dw 233
+; ( -- addr ) System Constant
+; R( -- )
+; Transmit Error Counter Register
+VE_CANTEC:
+ .dw $ff06
+ .db "CANTEC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANTEC
+XT_CANTEC:
+ .dw PFA_DOVARIABLE
+PFA_CANTEC:
+ .dw 234
+; ( -- addr ) System Constant
+; R( -- )
+; Receive Error Counter Register
+VE_CANREC:
+ .dw $ff06
+ .db "CANREC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANREC
+XT_CANREC:
+ .dw PFA_DOVARIABLE
+PFA_CANREC:
+ .dw 235
+; ( -- addr ) System Constant
+; R( -- )
+; Highest Priority MOb Register
+VE_CANHPMOB:
+ .dw $ff08
+ .db "CANHPMOB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANHPMOB
+XT_CANHPMOB:
+ .dw PFA_DOVARIABLE
+PFA_CANHPMOB:
+ .dw 236
+; ( -- addr ) System Constant
+; R( -- )
+; Page MOb Register
+VE_CANPAGE:
+ .dw $ff07
+ .db "CANPAGE",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANPAGE
+XT_CANPAGE:
+ .dw PFA_DOVARIABLE
+PFA_CANPAGE:
+ .dw 237
+; ( -- addr ) System Constant
+; R( -- )
+; MOb Status Register
+VE_CANSTMOB:
+ .dw $ff08
+ .db "CANSTMOB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANSTMOB
+XT_CANSTMOB:
+ .dw PFA_DOVARIABLE
+PFA_CANSTMOB:
+ .dw 238
+; ( -- addr ) System Constant
+; R( -- )
+; MOb Control and DLC Register
+VE_CANCDMOB:
+ .dw $ff08
+ .db "CANCDMOB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANCDMOB
+XT_CANCDMOB:
+ .dw PFA_DOVARIABLE
+PFA_CANCDMOB:
+ .dw 239
+; ( -- addr ) System Constant
+; R( -- )
+; Identifier Tag Register 4
+VE_CANIDT4:
+ .dw $ff07
+ .db "CANIDT4",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANIDT4
+XT_CANIDT4:
+ .dw PFA_DOVARIABLE
+PFA_CANIDT4:
+ .dw 240
+; ( -- addr ) System Constant
+; R( -- )
+; Identifier Tag Register 3
+VE_CANIDT3:
+ .dw $ff07
+ .db "CANIDT3",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANIDT3
+XT_CANIDT3:
+ .dw PFA_DOVARIABLE
+PFA_CANIDT3:
+ .dw 241
+; ( -- addr ) System Constant
+; R( -- )
+; Identifier Tag Register 2
+VE_CANIDT2:
+ .dw $ff07
+ .db "CANIDT2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANIDT2
+XT_CANIDT2:
+ .dw PFA_DOVARIABLE
+PFA_CANIDT2:
+ .dw 242
+; ( -- addr ) System Constant
+; R( -- )
+; Identifier Tag Register 1
+VE_CANIDT1:
+ .dw $ff07
+ .db "CANIDT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANIDT1
+XT_CANIDT1:
+ .dw PFA_DOVARIABLE
+PFA_CANIDT1:
+ .dw 243
+; ( -- addr ) System Constant
+; R( -- )
+; Identifier Mask Register 4
+VE_CANIDM4:
+ .dw $ff07
+ .db "CANIDM4",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANIDM4
+XT_CANIDM4:
+ .dw PFA_DOVARIABLE
+PFA_CANIDM4:
+ .dw 244
+; ( -- addr ) System Constant
+; R( -- )
+; Identifier Mask Register 3
+VE_CANIDM3:
+ .dw $ff07
+ .db "CANIDM3",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANIDM3
+XT_CANIDM3:
+ .dw PFA_DOVARIABLE
+PFA_CANIDM3:
+ .dw 245
+; ( -- addr ) System Constant
+; R( -- )
+; Identifier Mask Register 2
+VE_CANIDM2:
+ .dw $ff07
+ .db "CANIDM2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANIDM2
+XT_CANIDM2:
+ .dw PFA_DOVARIABLE
+PFA_CANIDM2:
+ .dw 246
+; ( -- addr ) System Constant
+; R( -- )
+; Identifier Mask Register 1
+VE_CANIDM1:
+ .dw $ff07
+ .db "CANIDM1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANIDM1
+XT_CANIDM1:
+ .dw PFA_DOVARIABLE
+PFA_CANIDM1:
+ .dw 247
+; ( -- addr ) System Constant
+; R( -- )
+; Time Stamp Register Low
+VE_CANSTML:
+ .dw $ff07
+ .db "CANSTML",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANSTML
+XT_CANSTML:
+ .dw PFA_DOVARIABLE
+PFA_CANSTML:
+ .dw 248
+; ( -- addr ) System Constant
+; R( -- )
+; Time Stamp Register High
+VE_CANSTMH:
+ .dw $ff07
+ .db "CANSTMH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANSTMH
+XT_CANSTMH:
+ .dw PFA_DOVARIABLE
+PFA_CANSTMH:
+ .dw 249
+; ( -- addr ) System Constant
+; R( -- )
+; Message Data Register
+VE_CANMSG:
+ .dw $ff06
+ .db "CANMSG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANMSG
+XT_CANMSG:
+ .dw PFA_DOVARIABLE
+PFA_CANMSG:
+ .dw 250
+
+.endif
+.if WANT_ANALOG_COMPARATOR == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator 0 Control Register
+VE_AC0CON:
+ .dw $ff06
+ .db "AC0CON"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_AC0CON
+XT_AC0CON:
+ .dw PFA_DOVARIABLE
+PFA_AC0CON:
+ .dw 148
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator 1 Control Register
+VE_AC1CON:
+ .dw $ff06
+ .db "AC1CON"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_AC1CON
+XT_AC1CON:
+ .dw PFA_DOVARIABLE
+PFA_AC1CON:
+ .dw 149
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator 2 Control Register
+VE_AC2CON:
+ .dw $ff06
+ .db "AC2CON"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_AC2CON
+XT_AC2CON:
+ .dw PFA_DOVARIABLE
+PFA_AC2CON:
+ .dw 150
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator 3 Control Register
+VE_AC3CON:
+ .dw $ff06
+ .db "AC3CON"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_AC3CON
+XT_AC3CON:
+ .dw PFA_DOVARIABLE
+PFA_AC3CON:
+ .dw 151
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw 80
+
+.endif
+.if WANT_DA_CONVERTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; DAC Data Register High Byte
+VE_DACH:
+ .dw $ff04
+ .db "DACH"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DACH
+XT_DACH:
+ .dw PFA_DOVARIABLE
+PFA_DACH:
+ .dw 146
+; ( -- addr ) System Constant
+; R( -- )
+; DAC Data Register Low Byte
+VE_DACL:
+ .dw $ff04
+ .db "DACL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DACL
+XT_DACL:
+ .dw PFA_DOVARIABLE
+PFA_DACL:
+ .dw 145
+; ( -- addr ) System Constant
+; R( -- )
+; DAC Control Register
+VE_DACON:
+ .dw $ff05
+ .db "DACON",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DACON
+XT_DACON:
+ .dw PFA_DOVARIABLE
+PFA_DACON:
+ .dw 144
+
+.endif
+.if WANT_CPU == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control Register
+VE_SPMCSR:
+ .dw $ff06
+ .db "SPMCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCSR
+XT_SPMCSR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCSR:
+ .dw 87
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw 95
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer
+VE_SP:
+ .dw $ff02
+ .db "SP"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SP
+XT_SP:
+ .dw PFA_DOVARIABLE
+PFA_SP:
+ .dw 93
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw 85
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Status Register
+VE_MCUSR:
+ .dw $ff05
+ .db "MCUSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUSR
+XT_MCUSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUSR:
+ .dw 84
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Calibration Value
+VE_OSCCAL:
+ .dw $ff06
+ .db "OSCCAL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSCCAL
+XT_OSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_OSCCAL:
+ .dw 102
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_CLKPR:
+ .dw $ff05
+ .db "CLKPR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKPR
+XT_CLKPR:
+ .dw PFA_DOVARIABLE
+PFA_CLKPR:
+ .dw 97
+; ( -- addr ) System Constant
+; R( -- )
+; Sleep Mode Control Register
+VE_SMCR:
+ .dw $ff04
+ .db "SMCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SMCR
+XT_SMCR:
+ .dw PFA_DOVARIABLE
+PFA_SMCR:
+ .dw 83
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 2
+VE_GPIOR2:
+ .dw $ff06
+ .db "GPIOR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR2
+XT_GPIOR2:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR2:
+ .dw 58
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 1
+VE_GPIOR1:
+ .dw $ff06
+ .db "GPIOR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR1
+XT_GPIOR1:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR1:
+ .dw 57
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 0
+VE_GPIOR0:
+ .dw $ff06
+ .db "GPIOR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR0
+XT_GPIOR0:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR0:
+ .dw 62
+; ( -- addr ) System Constant
+; R( -- )
+; PLL Control And Status Register
+VE_PLLCSR:
+ .dw $ff06
+ .db "PLLCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PLLCSR
+XT_PLLCSR:
+ .dw PFA_DOVARIABLE
+PFA_PLLCSR:
+ .dw 73
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register
+VE_PRR:
+ .dw $ff03
+ .db "PRR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR
+XT_PRR:
+ .dw PFA_DOVARIABLE
+PFA_PRR:
+ .dw 100
+
+.endif
+.if WANT_PORTE == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port E Data Register
+VE_PORTE:
+ .dw $ff05
+ .db "PORTE",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTE
+XT_PORTE:
+ .dw PFA_DOVARIABLE
+PFA_PORTE:
+ .dw 46
+; ( -- addr ) System Constant
+; R( -- )
+; Port E Data Direction Register
+VE_DDRE:
+ .dw $ff04
+ .db "DDRE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRE
+XT_DDRE:
+ .dw PFA_DOVARIABLE
+PFA_DDRE:
+ .dw 45
+; ( -- addr ) System Constant
+; R( -- )
+; Port E Input Pins
+VE_PINE:
+ .dw $ff04
+ .db "PINE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINE
+XT_PINE:
+ .dw PFA_DOVARIABLE
+PFA_PINE:
+ .dw 44
+
+.endif
+.if WANT_TIMER_COUNTER_0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Mask Register
+VE_TIMSK0:
+ .dw $ff06
+ .db "TIMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK0
+XT_TIMSK0:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK0:
+ .dw 110
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Flag register
+VE_TIFR0:
+ .dw $ff05
+ .db "TIFR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR0
+XT_TIFR0:
+ .dw PFA_DOVARIABLE
+PFA_TIFR0:
+ .dw 53
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register A
+VE_TCCR0A:
+ .dw $ff06
+ .db "TCCR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0A
+XT_TCCR0A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0A:
+ .dw 68
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register B
+VE_TCCR0B:
+ .dw $ff06
+ .db "TCCR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0B
+XT_TCCR0B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0B:
+ .dw 69
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw 70
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0A:
+ .dw $ff05
+ .db "OCR0A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0A
+XT_OCR0A:
+ .dw PFA_DOVARIABLE
+PFA_OCR0A:
+ .dw 71
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0B:
+ .dw $ff05
+ .db "OCR0B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0B
+XT_OCR0B:
+ .dw PFA_DOVARIABLE
+PFA_OCR0B:
+ .dw 72
+; ( -- addr ) System Constant
+; R( -- )
+; General Timer/Counter Control Register
+VE_GTCCR:
+ .dw $ff05
+ .db "GTCCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GTCCR
+XT_GTCCR:
+ .dw PFA_DOVARIABLE
+PFA_GTCCR:
+ .dw 67
+
+.endif
+.if WANT_TIMER_COUNTER_1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Mask Register
+VE_TIMSK1:
+ .dw $ff06
+ .db "TIMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK1
+XT_TIMSK1:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK1:
+ .dw 111
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Flag register
+VE_TIFR1:
+ .dw $ff05
+ .db "TIFR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR1
+XT_TIFR1:
+ .dw PFA_DOVARIABLE
+PFA_TIFR1:
+ .dw 54
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw 128
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw 129
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register C
+VE_TCCR1C:
+ .dw $ff06
+ .db "TCCR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1C
+XT_TCCR1C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1C:
+ .dw 130
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Bytes
+VE_TCNT1:
+ .dw $ff05
+ .db "TCNT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1
+XT_TCNT1:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1:
+ .dw 132
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register Bytes
+VE_OCR1A:
+ .dw $ff05
+ .db "OCR1A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1A
+XT_OCR1A:
+ .dw PFA_DOVARIABLE
+PFA_OCR1A:
+ .dw 136
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register Bytes
+VE_OCR1B:
+ .dw $ff05
+ .db "OCR1B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1B
+XT_OCR1B:
+ .dw PFA_DOVARIABLE
+PFA_OCR1B:
+ .dw 138
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Bytes
+VE_ICR1:
+ .dw $ff04
+ .db "ICR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1
+XT_ICR1:
+ .dw PFA_DOVARIABLE
+PFA_ICR1:
+ .dw 134
+
+.endif
+.if WANT_AD_CONVERTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC multiplexer Selection Register
+VE_ADMUX:
+ .dw $ff05
+ .db "ADMUX",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADMUX
+XT_ADMUX:
+ .dw PFA_DOVARIABLE
+PFA_ADMUX:
+ .dw 124
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register
+VE_ADCSRA:
+ .dw $ff06
+ .db "ADCSRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRA
+XT_ADCSRA:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRA:
+ .dw 122
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register Bytes
+VE_ADC:
+ .dw $ff03
+ .db "ADC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADC
+XT_ADC:
+ .dw PFA_DOVARIABLE
+PFA_ADC:
+ .dw 120
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Control and Status Register B
+VE_ADCSRB:
+ .dw $ff06
+ .db "ADCSRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRB
+XT_ADCSRB:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRB:
+ .dw 123
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 0
+VE_DIDR0:
+ .dw $ff05
+ .db "DIDR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR0
+XT_DIDR0:
+ .dw PFA_DOVARIABLE
+PFA_DIDR0:
+ .dw 126
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 0
+VE_DIDR1:
+ .dw $ff05
+ .db "DIDR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR1
+XT_DIDR1:
+ .dw PFA_DOVARIABLE
+PFA_DIDR1:
+ .dw 127
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_AMP0CSR:
+ .dw $ff07
+ .db "AMP0CSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_AMP0CSR
+XT_AMP0CSR:
+ .dw PFA_DOVARIABLE
+PFA_AMP0CSR:
+ .dw 117
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_AMP1CSR:
+ .dw $ff07
+ .db "AMP1CSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_AMP1CSR
+XT_AMP1CSR:
+ .dw PFA_DOVARIABLE
+PFA_AMP1CSR:
+ .dw 118
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_AMP2CSR:
+ .dw $ff07
+ .db "AMP2CSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_AMP2CSR
+XT_AMP2CSR:
+ .dw PFA_DOVARIABLE
+PFA_AMP2CSR:
+ .dw 119
+
+.endif
+.if WANT_LINUART == 1
+; ( -- addr ) System Constant
+; R( -- )
+; LIN Control Register
+VE_LINCR:
+ .dw $ff05
+ .db "LINCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LINCR
+XT_LINCR:
+ .dw PFA_DOVARIABLE
+PFA_LINCR:
+ .dw 200
+; ( -- addr ) System Constant
+; R( -- )
+; LIN Status and Interrupt Register
+VE_LINSIR:
+ .dw $ff06
+ .db "LINSIR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LINSIR
+XT_LINSIR:
+ .dw PFA_DOVARIABLE
+PFA_LINSIR:
+ .dw 201
+; ( -- addr ) System Constant
+; R( -- )
+; LIN Enable Interrupt Register
+VE_LINENIR:
+ .dw $ff07
+ .db "LINENIR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LINENIR
+XT_LINENIR:
+ .dw PFA_DOVARIABLE
+PFA_LINENIR:
+ .dw 202
+; ( -- addr ) System Constant
+; R( -- )
+; LIN Error Register
+VE_LINERR:
+ .dw $ff06
+ .db "LINERR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LINERR
+XT_LINERR:
+ .dw PFA_DOVARIABLE
+PFA_LINERR:
+ .dw 203
+; ( -- addr ) System Constant
+; R( -- )
+; LIN Bit Timing Register
+VE_LINBTR:
+ .dw $ff06
+ .db "LINBTR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LINBTR
+XT_LINBTR:
+ .dw PFA_DOVARIABLE
+PFA_LINBTR:
+ .dw 204
+; ( -- addr ) System Constant
+; R( -- )
+; LIN Baud Rate Low Register
+VE_LINBRRL:
+ .dw $ff07
+ .db "LINBRRL",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LINBRRL
+XT_LINBRRL:
+ .dw PFA_DOVARIABLE
+PFA_LINBRRL:
+ .dw 205
+; ( -- addr ) System Constant
+; R( -- )
+; LIN Baud Rate High Register
+VE_LINBRRH:
+ .dw $ff07
+ .db "LINBRRH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LINBRRH
+XT_LINBRRH:
+ .dw PFA_DOVARIABLE
+PFA_LINBRRH:
+ .dw 206
+; ( -- addr ) System Constant
+; R( -- )
+; LIN Data Length Register
+VE_LINDLR:
+ .dw $ff06
+ .db "LINDLR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LINDLR
+XT_LINDLR:
+ .dw PFA_DOVARIABLE
+PFA_LINDLR:
+ .dw 207
+; ( -- addr ) System Constant
+; R( -- )
+; LIN Identifier Register
+VE_LINIDR:
+ .dw $ff06
+ .db "LINIDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LINIDR
+XT_LINIDR:
+ .dw PFA_DOVARIABLE
+PFA_LINIDR:
+ .dw 208
+; ( -- addr ) System Constant
+; R( -- )
+; LIN Data Buffer Selection Register
+VE_LINSEL:
+ .dw $ff06
+ .db "LINSEL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LINSEL
+XT_LINSEL:
+ .dw PFA_DOVARIABLE
+PFA_LINSEL:
+ .dw 209
+; ( -- addr ) System Constant
+; R( -- )
+; LIN Data Register
+VE_LINDAT:
+ .dw $ff06
+ .db "LINDAT"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LINDAT
+XT_LINDAT:
+ .dw PFA_DOVARIABLE
+PFA_LINDAT:
+ .dw 210
+
+.endif
+.if WANT_SPI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR:
+ .dw $ff04
+ .db "SPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR
+XT_SPCR:
+ .dw PFA_DOVARIABLE
+PFA_SPCR:
+ .dw 76
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR:
+ .dw $ff04
+ .db "SPSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR
+XT_SPSR:
+ .dw PFA_DOVARIABLE
+PFA_SPSR:
+ .dw 77
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR:
+ .dw $ff04
+ .db "SPDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR
+XT_SPDR:
+ .dw PFA_DOVARIABLE
+PFA_SPDR:
+ .dw 78
+
+.endif
+.if WANT_WATCHDOG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCSR:
+ .dw $ff06
+ .db "WDTCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCSR
+XT_WDTCSR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCSR:
+ .dw 96
+
+.endif
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register
+VE_EICRA:
+ .dw $ff05
+ .db "EICRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRA
+XT_EICRA:
+ .dw PFA_DOVARIABLE
+PFA_EICRA:
+ .dw 105
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Mask Register
+VE_EIMSK:
+ .dw $ff05
+ .db "EIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIMSK
+XT_EIMSK:
+ .dw PFA_DOVARIABLE
+PFA_EIMSK:
+ .dw 61
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Flag Register
+VE_EIFR:
+ .dw $ff04
+ .db "EIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIFR
+XT_EIFR:
+ .dw PFA_DOVARIABLE
+PFA_EIFR:
+ .dw 60
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Interrupt Control Register
+VE_PCICR:
+ .dw $ff05
+ .db "PCICR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCICR
+XT_PCICR:
+ .dw PFA_DOVARIABLE
+PFA_PCICR:
+ .dw 104
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 3
+VE_PCMSK3:
+ .dw $ff06
+ .db "PCMSK3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK3
+XT_PCMSK3:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK3:
+ .dw 109
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 2
+VE_PCMSK2:
+ .dw $ff06
+ .db "PCMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK2
+XT_PCMSK2:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK2:
+ .dw 108
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 1
+VE_PCMSK1:
+ .dw $ff06
+ .db "PCMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK1
+XT_PCMSK1:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK1:
+ .dw 107
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 0
+VE_PCMSK0:
+ .dw $ff06
+ .db "PCMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK0
+XT_PCMSK0:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK0:
+ .dw 106
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Interrupt Flag Register
+VE_PCIFR:
+ .dw $ff05
+ .db "PCIFR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCIFR
+XT_PCIFR:
+ .dw PFA_DOVARIABLE
+PFA_PCIFR:
+ .dw 59
+
+.endif
+.if WANT_EEPROM == 1
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Read/Write Access
+VE_EEAR:
+ .dw $ff04
+ .db "EEAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEAR
+XT_EEAR:
+ .dw PFA_DOVARIABLE
+PFA_EEAR:
+ .dw 65
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw 64
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw 63
+
+.endif
diff --git a/amforth-6.5/avr8/devices/atmega64c1/device.py b/amforth-6.5/avr8/devices/atmega64c1/device.py
new file mode 100644
index 0000000..198a644
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega64c1/device.py
@@ -0,0 +1,477 @@
+# Generated Automatically
+
+# Partname ATmega64C1
+
+MCUREGS = {
+# Interrupt Vectors
+ 'ANACOMP0Addr' : '#2', # Analog Comparator 0
+ 'ANACOMP1Addr' : '#4', # Analog Comparator 1
+ 'ANACOMP2Addr' : '#6', # Analog Comparator 2
+ 'ANACOMP3Addr' : '#8', # Analog Comparator 3
+ 'PSC_FAULTAddr' : '#10', # PSC Fault
+ 'PSC_ECAddr' : '#12', # PSC End of Cycle
+ 'INT0Addr' : '#14', # External Interrupt Request 0
+ 'INT1Addr' : '#16', # External Interrupt Request 1
+ 'INT2Addr' : '#18', # External Interrupt Request 2
+ 'INT3Addr' : '#20', # External Interrupt Request 3
+ 'TIMER1_CAPTAddr' : '#22', # Timer/Counter1 Capture Event
+ 'TIMER1_COMPAAddr' : '#24', # Timer/Counter1 Compare Match A
+ 'TIMER1_COMPBAddr' : '#26', # Timer/Counter1 Compare Match B
+ 'TIMER1_OVFAddr' : '#28', # Timer1/Counter1 Overflow
+ 'TIMER0_COMPAAddr' : '#30', # Timer/Counter0 Compare Match A
+ 'TIMER0_COMPBAddr' : '#32', # Timer/Counter0 Compare Match B
+ 'TIMER0_OVFAddr' : '#34', # Timer/Counter0 Overflow
+ 'CAN_INTAddr' : '#36', # CAN MOB, Burst, General Errors
+ 'CAN_TOVFAddr' : '#38', # CAN Timer Overflow
+ 'LIN_TCAddr' : '#40', # LIN Transfer Complete
+ 'LIN_ERRAddr' : '#42', # LIN Error
+ 'PCINT0Addr' : '#44', # Pin Change Interrupt Request 0
+ 'PCINT1Addr' : '#46', # Pin Change Interrupt Request 1
+ 'PCINT2Addr' : '#48', # Pin Change Interrupt Request 2
+ 'PCINT3Addr' : '#50', # Pin Change Interrupt Request 3
+ 'SPI_STCAddr' : '#52', # SPI Serial Transfer Complete
+ 'ADCAddr' : '#54', # ADC Conversion Complete
+ 'WDTAddr' : '#56', # Watchdog Time-Out Interrupt
+ 'EE_READYAddr' : '#58', # EEPROM Ready
+ 'SPM_READYAddr' : '#60', # Store Program Memory Read
+
+# Module PORTB
+ 'PORTB' : '$25', # Port B Data Register
+ 'DDRB' : '$24', # Port B Data Direction Register
+ 'PINB' : '$23', # Port B Input Pins
+
+# Module PORTC
+ 'PORTC' : '$28', # Port C Data Register
+ 'DDRC' : '$27', # Port C Data Direction Register
+ 'PINC' : '$26', # Port C Input Pins
+
+# Module PORTD
+ 'PORTD' : '$2b', # Port D Data Register
+ 'DDRD' : '$2a', # Port D Data Direction Register
+ 'PIND' : '$29', # Port D Input Pins
+
+# Module CAN
+ 'CANGCON' : '$d8', # CAN General Control Register
+ 'CANGCON_ABRQ': '$80', # Abort Request
+ 'CANGCON_OVRQ': '$40', # Overload Frame Request
+ 'CANGCON_TTC': '$20', # Time Trigger Communication
+ 'CANGCON_SYNTTC': '$10', # Synchronization of TTC
+ 'CANGCON_LISTEN': '$8', # Listening Mode
+ 'CANGCON_TEST': '$4', # Test Mode
+ 'CANGCON_ENASTB': '$2', # Enable / Standby
+ 'CANGCON_SWRES': '$1', # Software Reset Request
+ 'CANGSTA' : '$d9', # CAN General Status Register
+ 'CANGSTA_OVFG': '$40', # Overload Frame Flag
+ 'CANGSTA_TXBSY': '$10', # Transmitter Busy
+ 'CANGSTA_RXBSY': '$8', # Receiver Busy
+ 'CANGSTA_ENFG': '$4', # Enable Flag
+ 'CANGSTA_BOFF': '$2', # Bus Off Mode
+ 'CANGSTA_ERRP': '$1', # Error Passive Mode
+ 'CANGIT' : '$da', # CAN General Interrupt Register
+ 'CANGIT_CANIT': '$80', # General Interrupt Flag
+ 'CANGIT_BOFFIT': '$40', # Bus Off Interrupt Flag
+ 'CANGIT_OVRTIM': '$20', # Overrun CAN Timer Flag
+ 'CANGIT_BXOK': '$10', # Burst Receive Interrupt Flag
+ 'CANGIT_SERG': '$8', # Stuff Error General Flag
+ 'CANGIT_CERG': '$4', # CRC Error General Flag
+ 'CANGIT_FERG': '$2', # Form Error General Flag
+ 'CANGIT_AERG': '$1', # Ackknowledgement Error General
+ 'CANGIE' : '$db', # CAN General Interrupt Enable R
+ 'CANGIE_ENIT': '$80', # Enable all Interrupts
+ 'CANGIE_ENBOFF': '$40', # Enable Bus Off Interrupt
+ 'CANGIE_ENRX': '$20', # Enable Receive Interrupt
+ 'CANGIE_ENTX': '$10', # Enable Transmitt Interrupt
+ 'CANGIE_ENERR': '$8', # Enable MOb Error Interrupt
+ 'CANGIE_ENBX': '$4', # Enable Burst Receive Interrupt
+ 'CANGIE_ENERG': '$2', # Enable General Error Interrupt
+ 'CANGIE_ENOVRT': '$1', # Enable CAN Timer Overrun Inter
+ 'CANEN2' : '$dc', # Enable MOb Register 2
+ 'CANEN2_ENMOB': '$3f', # Enable MObs
+ 'CANEN1' : '$dd', # Enable MOb Register 1(empty)
+ 'CANIE2' : '$de', # Enable Interrupt MOb Register
+ 'CANIE2_IEMOB': '$3f', # Interrupt Enable MObs
+ 'CANIE1' : '$df', # Enable Interrupt MOb Register
+ 'CANSIT2' : '$e0', # CAN Status Interrupt MOb Regis
+ 'CANSIT2_SIT': '$3f', # Status of Interrupt MObs
+ 'CANSIT1' : '$e1', # CAN Status Interrupt MOb Regis
+ 'CANBT1' : '$e2', # CAN Bit Timing Register 1
+ 'CANBT1_BRP': '$7e', # Baud Rate Prescaler bits
+ 'CANBT2' : '$e3', # CAN Bit Timing Register 2
+ 'CANBT2_SJW': '$60', # Re-Sync Jump Width bits
+ 'CANBT2_PRS': '$e', # Propagation Time Segment bits
+ 'CANBT3' : '$e4', # CAN Bit Timing Register 3
+ 'CANBT3_PHS2': '$70', # Phase Segment 2 bits
+ 'CANBT3_PHS1': '$e', # Phase Segment 1 bits
+ 'CANBT3_SMP': '$1', # Sample Type
+ 'CANTCON' : '$e5', # Timer Control Register
+ 'CANTIML' : '$e6', # Timer Register Low
+ 'CANTIMH' : '$e7', # Timer Register High
+ 'CANTTCL' : '$e8', # TTC Timer Register Low
+ 'CANTTCH' : '$e9', # TTC Timer Register High
+ 'CANTEC' : '$ea', # Transmit Error Counter Registe
+ 'CANREC' : '$eb', # Receive Error Counter Register
+ 'CANHPMOB' : '$ec', # Highest Priority MOb Register
+ 'CANHPMOB_HPMOB': '$f0', # Highest Priority MOb Number bi
+ 'CANHPMOB_CGP': '$f', # CAN General Purpose bits
+ 'CANPAGE' : '$ed', # Page MOb Register
+ 'CANPAGE_MOBNB': '$f0', # MOb Number bits
+ 'CANPAGE_AINC': '$8', # MOb Data Buffer Auto Increment
+ 'CANPAGE_INDX': '$7', # Data Buffer Index bits
+ 'CANSTMOB' : '$ee', # MOb Status Register
+ 'CANSTMOB_DLCW': '$80', # Data Length Code Warning on MO
+ 'CANSTMOB_TXOK': '$40', # Transmit OK on MOb
+ 'CANSTMOB_RXOK': '$20', # Receive OK on MOb
+ 'CANSTMOB_BERR': '$10', # Bit Error on MOb
+ 'CANSTMOB_SERR': '$8', # Stuff Error on MOb
+ 'CANSTMOB_CERR': '$4', # CRC Error on MOb
+ 'CANSTMOB_FERR': '$2', # Form Error on MOb
+ 'CANSTMOB_AERR': '$1', # Ackknowledgement Error on MOb
+ 'CANCDMOB' : '$ef', # MOb Control and DLC Register
+ 'CANCDMOB_CONMOB': '$c0', # MOb Config bits
+ 'CANCDMOB_RPLV': '$20', # Reply Valid
+ 'CANCDMOB_IDE': '$10', # Identifier Extension
+ 'CANCDMOB_DLC': '$f', # Data Length Code bits
+ 'CANIDT4' : '$f0', # Identifier Tag Register 4
+ 'CANIDT4_IDT': '$f8', #
+ 'CANIDT4_RTRTAG': '$4', #
+ 'CANIDT4_RB1TAG': '$2', #
+ 'CANIDT4_RB0TAG': '$1', #
+ 'CANIDT3' : '$f1', # Identifier Tag Register 3
+ 'CANIDT2' : '$f2', # Identifier Tag Register 2
+ 'CANIDT1' : '$f3', # Identifier Tag Register 1
+ 'CANIDM4' : '$f4', # Identifier Mask Register 4
+ 'CANIDM3' : '$f5', # Identifier Mask Register 3
+ 'CANIDM2' : '$f6', # Identifier Mask Register 2
+ 'CANIDM1' : '$f7', # Identifier Mask Register 1
+ 'CANSTML' : '$f8', # Time Stamp Register Low
+ 'CANSTMH' : '$f9', # Time Stamp Register High
+ 'CANMSG' : '$fa', # Message Data Register
+
+# Module ANALOG_COMPARATOR
+ 'AC0CON' : '$94', # Analog Comparator 0 Control Re
+ 'AC0CON_AC0EN': '$80', # Analog Comparator 0 Enable Bit
+ 'AC0CON_AC0IE': '$40', # Analog Comparator 0 Interrupt
+ 'AC0CON_AC0IS': '$30', # Analog Comparator 0 Interrupt
+ 'AC0CON_ACCKSEL': '$8', # Analog Comparator Clock Select
+ 'AC0CON_AC0M': '$7', # Analog Comparator 0 Multiplexe
+ 'AC1CON' : '$95', # Analog Comparator 1 Control Re
+ 'AC1CON_AC1EN': '$80', # Analog Comparator 1 Enable Bit
+ 'AC1CON_AC1IE': '$40', # Analog Comparator 1 Interrupt
+ 'AC1CON_AC1IS': '$30', # Analog Comparator 1 Interrupt
+ 'AC1CON_AC1ICE': '$8', # Analog Comparator 1 Interrupt
+ 'AC1CON_AC1M': '$7', # Analog Comparator 1 Multiplexe
+ 'AC2CON' : '$96', # Analog Comparator 2 Control Re
+ 'AC2CON_AC2EN': '$80', # Analog Comparator 2 Enable Bit
+ 'AC2CON_AC2IE': '$40', # Analog Comparator 2 Interrupt
+ 'AC2CON_AC2IS': '$30', # Analog Comparator 2 Interrupt
+ 'AC2CON_AC2M': '$7', # Analog Comparator 2 Multiplexe
+ 'AC3CON' : '$97', # Analog Comparator 3 Control Re
+ 'AC3CON_AC3EN': '$80', # Analog Comparator 3 Enable Bit
+ 'AC3CON_AC3IE': '$40', # Analog Comparator 3 Interrupt
+ 'AC3CON_AC3IS': '$30', # Analog Comparator 3 Interrupt
+ 'AC3CON_AC3M': '$7', # Analog Comparator 3 Multiplexe
+ 'ACSR' : '$50', # Analog Comparator Status Regis
+ 'ACSR_AC3IF': '$80', # Analog Comparator 3 Interrupt
+ 'ACSR_AC2IF': '$40', # Analog Comparator 2 Interrupt
+ 'ACSR_AC1IF': '$20', # Analog Comparator 1 Interrupt
+ 'ACSR_AC0IF': '$10', # Analog Comparator 0 Interrupt
+ 'ACSR_AC3O': '$8', # Analog Comparator 3 Output Bit
+ 'ACSR_AC2O': '$4', # Analog Comparator 2 Output Bit
+ 'ACSR_AC1O': '$2', # Analog Comparator 1 Output Bit
+ 'ACSR_AC0O': '$1', # Analog Comparator 0 Output Bit
+
+# Module DA_CONVERTER
+ 'DACH' : '$92', # DAC Data Register High Byte
+ 'DACH_DACH': '$ff', # DAC Data Register High Byte Bi
+ 'DACL' : '$91', # DAC Data Register Low Byte
+ 'DACL_DACL': '$ff', # DAC Data Register Low Byte Bit
+ 'DACON' : '$90', # DAC Control Register
+ 'DACON_DAATE': '$80', # DAC Auto Trigger Enable Bit
+ 'DACON_DATS': '$70', # DAC Trigger Selection Bits
+ 'DACON_DALA': '$4', # DAC Left Adjust
+ 'DACON_DAEN': '$1', # DAC Enable Bit
+
+# Module CPU
+ 'SPMCSR' : '$57', # Store Program Memory Control R
+ 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
+ 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
+ 'SPMCSR_SIGRD': '$20', # Signature Row Read
+ 'SPMCSR_RWWSRE': '$10', # Read While Write section read
+ 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
+ 'SPMCSR_PGWRT': '$4', # Page Write
+ 'SPMCSR_PGERS': '$2', # Page Erase
+ 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
+ 'SREG' : '$5f', # Status Register
+ 'SREG_I': '$80', # Global Interrupt Enable
+ 'SREG_T': '$40', # Bit Copy Storage
+ 'SREG_H': '$20', # Half Carry Flag
+ 'SREG_S': '$10', # Sign Bit
+ 'SREG_V': '$8', # Two's Complement Overflow Flag
+ 'SREG_N': '$4', # Negative Flag
+ 'SREG_Z': '$2', # Zero Flag
+ 'SREG_C': '$1', # Carry Flag
+ 'SP' : '$5d', # Stack Pointer
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_SPIPS': '$80', # SPI Pin Select
+ 'MCUCR_PUD': '$10', # Pull-up disable
+ 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
+ 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
+ 'MCUSR_BORF': '$4', # Brown-out Reset Flag
+ 'MCUSR_EXTRF': '$2', # External Reset Flag
+ 'MCUSR_PORF': '$1', # Power-on reset flag
+ 'OSCCAL' : '$66', # Oscillator Calibration Value
+ 'CLKPR' : '$61', #
+ 'CLKPR_CLKPCE': '$80', #
+ 'CLKPR_CLKPS': '$f', #
+ 'SMCR' : '$53', # Sleep Mode Control Register
+ 'SMCR_SM': '$e', # Sleep Mode Select bits
+ 'SMCR_SE': '$1', # Sleep Enable
+ 'GPIOR2' : '$3a', # General Purpose IO Register 2
+ 'GPIOR2_GPIOR': '$ff', # General Purpose IO Register 2
+ 'GPIOR1' : '$39', # General Purpose IO Register 1
+ 'GPIOR1_GPIOR': '$ff', # General Purpose IO Register 1
+ 'GPIOR0' : '$3e', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR07': '$80', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR06': '$40', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR05': '$20', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR04': '$10', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR03': '$8', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR02': '$4', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR01': '$2', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR00': '$1', # General Purpose IO Register 0
+ 'PLLCSR' : '$49', # PLL Control And Status Registe
+ 'PLLCSR_PLLF': '$4', # PLL Factor
+ 'PLLCSR_PLLE': '$2', # PLL Enable
+ 'PLLCSR_PLOCK': '$1', # PLL Lock Detector
+ 'PRR' : '$64', # Power Reduction Register
+ 'PRR_PRCAN': '$40', # Power Reduction CAN
+ 'PRR_PRPSC': '$20', # Power Reduction PSC
+ 'PRR_PRTIM1': '$10', # Power Reduction Timer/Counter1
+ 'PRR_PRTIM0': '$8', # Power Reduction Timer/Counter0
+ 'PRR_PRSPI': '$4', # Power Reduction Serial Periphe
+ 'PRR_PRLIN': '$2', # Power Reduction LIN UART
+ 'PRR_PRADC': '$1', # Power Reduction ADC
+
+# Module PORTE
+ 'PORTE' : '$2e', # Port E Data Register
+ 'DDRE' : '$2d', # Port E Data Direction Register
+ 'PINE' : '$2c', # Port E Input Pins
+
+# Module TIMER_COUNTER_0
+ 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
+ 'TIMSK0_OCIE0B': '$4', # Timer/Counter0 Output Compare
+ 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
+ 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
+ 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
+ 'TIFR0_OCF0B': '$4', # Timer/Counter0 Output Compare
+ 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
+ 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
+ 'TCCR0A' : '$44', # Timer/Counter Control Registe
+ 'TCCR0A_COM0A': '$c0', # Compare Output Mode, Phase Cor
+ 'TCCR0A_COM0B': '$30', # Compare Output Mode, Fast PWm
+ 'TCCR0A_WGM0': '$3', # Waveform Generation Mode
+ 'TCCR0B' : '$45', # Timer/Counter Control Register
+ 'TCCR0B_FOC0A': '$80', # Force Output Compare A
+ 'TCCR0B_FOC0B': '$40', # Force Output Compare B
+ 'TCCR0B_WGM02': '$8', #
+ 'TCCR0B_CS0': '$7', # Clock Select
+ 'TCNT0' : '$46', # Timer/Counter0
+ 'OCR0A' : '$47', # Timer/Counter0 Output Compare
+ 'OCR0B' : '$48', # Timer/Counter0 Output Compare
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_ICPSEL1': '$40', # Timer1 Input Capture Selection
+ 'GTCCR_PSR10': '$1', # Prescaler Reset Timer/Counter1
+
+# Module TIMER_COUNTER_1
+ 'TIMSK1' : '$6f', # Timer/Counter Interrupt Mask R
+ 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
+ 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output CompareB
+ 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output CompareA
+ 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
+ 'TIFR1' : '$36', # Timer/Counter Interrupt Flag r
+ 'TIFR1_ICF1': '$20', # Input Capture Flag 1
+ 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
+ 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
+ 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
+ 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
+ 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
+ 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
+ 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
+ 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
+ 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
+ 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
+ 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
+ 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
+ 'TCCR1C' : '$82', # Timer/Counter1 Control Registe
+ 'TCCR1C_FOC1A': '$80', #
+ 'TCCR1C_FOC1B': '$40', #
+ 'TCNT1' : '$84', # Timer/Counter1 Bytes
+ 'OCR1A' : '$88', # Timer/Counter1 Output Compare
+ 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
+ 'ICR1' : '$86', # Timer/Counter1 Input Capture R
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSRSYNC': '$1', # Prescaler Reset Timer/Counter1
+
+# Module AD_CONVERTER
+ 'ADMUX' : '$7c', # The ADC multiplexer Selection
+ 'ADMUX_REFS': '$c0', # Reference Selection Bits
+ 'ADMUX_ADLAR': '$20', # Left Adjust Result
+ 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
+ 'ADCSRA' : '$7a', # The ADC Control and Status reg
+ 'ADCSRA_ADEN': '$80', # ADC Enable
+ 'ADCSRA_ADSC': '$40', # ADC Start Conversion
+ 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
+ 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
+ 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
+ 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
+ 'ADC' : '$78', # ADC Data Register Bytes
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ADHSM': '$80', # ADC High Speed Mode
+ 'ADCSRB_ISRCEN': '$40', # Current Source Enable
+ 'ADCSRB_AREFEN': '$20', # Analog Reference pin Enable
+ 'ADCSRB_ADTS': '$f', # ADC Auto Trigger Sources
+ 'DIDR0' : '$7e', # Digital Input Disable Register
+ 'DIDR0_ADC7D': '$80', # ADC7 Digital input Disable
+ 'DIDR0_ADC6D': '$40', # ADC6 Digital input Disable
+ 'DIDR0_ADC5D': '$20', # ADC5 Digital input Disable
+ 'DIDR0_ADC4D': '$10', # ADC4 Digital input Disable
+ 'DIDR0_ADC3D': '$8', # ADC3 Digital input Disable
+ 'DIDR0_ADC2D': '$4', # ADC2 Digital input Disable
+ 'DIDR0_ADC1D': '$2', # ADC1 Digital input Disable
+ 'DIDR0_ADC0D': '$1', # ADC0 Digital input Disable
+ 'DIDR1' : '$7f', # Digital Input Disable Register
+ 'DIDR1_AMP2PD': '$40', # AMP2P Pin Digital input Disabl
+ 'DIDR1_ACMP0D': '$20', # ACMP0 Pin Digital input Disabl
+ 'DIDR1_AMP0PD': '$10', # AMP0P Pin Digital input Disabl
+ 'DIDR1_AMP0ND': '$8', # AMP0N Pin Digital input Disabl
+ 'DIDR1_ADC10D': '$4', # ADC10 Pin Digital input Disabl
+ 'DIDR1_ADC9D': '$2', # ADC9 Pin Digital input Disable
+ 'DIDR1_ADC8D': '$1', # ADC8 Pin Digital input Disable
+ 'AMP0CSR' : '$75', #
+ 'AMP0CSR_AMP0EN': '$80', #
+ 'AMP0CSR_AMP0IS': '$40', #
+ 'AMP0CSR_AMP0G': '$30', #
+ 'AMP0CSR_AMPCMP0': '$8', # Amplifier 0 - Comparator 0 Con
+ 'AMP0CSR_AMP0TS': '$7', #
+ 'AMP1CSR' : '$76', #
+ 'AMP1CSR_AMP1EN': '$80', #
+ 'AMP1CSR_AMP1IS': '$40', #
+ 'AMP1CSR_AMP1G': '$30', #
+ 'AMP1CSR_AMPCMP1': '$8', # Amplifier 1 - Comparator 1 Con
+ 'AMP1CSR_AMP1TS': '$7', #
+ 'AMP2CSR' : '$77', #
+ 'AMP2CSR_AMP2EN': '$80', #
+ 'AMP2CSR_AMP2IS': '$40', #
+ 'AMP2CSR_AMP2G': '$30', #
+ 'AMP2CSR_AMPCMP2': '$8', # Amplifier 2 - Comparator 2 Con
+ 'AMP2CSR_AMP2TS': '$7', #
+
+# Module LINUART
+ 'LINCR' : '$c8', # LIN Control Register
+ 'LINCR_LSWRES': '$80', # Software Reset
+ 'LINCR_LIN13': '$40', # LIN Standard
+ 'LINCR_LCONF': '$30', # LIN Configuration bits
+ 'LINCR_LENA': '$8', # LIN or UART Enable
+ 'LINCR_LCMD': '$7', # LIN Command and Mode bits
+ 'LINSIR' : '$c9', # LIN Status and Interrupt Regis
+ 'LINSIR_LIDST': '$e0', # Identifier Status bits
+ 'LINSIR_LBUSY': '$10', # Busy Signal
+ 'LINSIR_LERR': '$8', # Error Interrupt
+ 'LINSIR_LIDOK': '$4', # Identifier Interrupt
+ 'LINSIR_LTXOK': '$2', # Transmit Performed Interrupt
+ 'LINSIR_LRXOK': '$1', # Receive Performed Interrupt
+ 'LINENIR' : '$ca', # LIN Enable Interrupt Register
+ 'LINENIR_LENERR': '$8', # Enable Error Interrupt
+ 'LINENIR_LENIDOK': '$4', # Enable Identifier Interrupt
+ 'LINENIR_LENTXOK': '$2', # Enable Transmit Performed Inte
+ 'LINENIR_LENRXOK': '$1', # Enable Receive Performed Inter
+ 'LINERR' : '$cb', # LIN Error Register
+ 'LINERR_LABORT': '$80', # Abort Flag
+ 'LINERR_LTOERR': '$40', # Frame Time Out Error Flag
+ 'LINERR_LOVERR': '$20', # Overrun Error Flag
+ 'LINERR_LFERR': '$10', # Framing Error Flag
+ 'LINERR_LSERR': '$8', # Synchronization Error Flag
+ 'LINERR_LPERR': '$4', # Parity Error Flag
+ 'LINERR_LCERR': '$2', # Checksum Error Flag
+ 'LINERR_LBERR': '$1', # Bit Error Flag
+ 'LINBTR' : '$cc', # LIN Bit Timing Register
+ 'LINBTR_LDISR': '$80', # Disable Bit Timing Resynchroni
+ 'LINBTR_LBT': '$3f', # LIN Bit Timing bits
+ 'LINBRRL' : '$cd', # LIN Baud Rate Low Register
+ 'LINBRRL_LDIV': '$ff', #
+ 'LINBRRH' : '$ce', # LIN Baud Rate High Register
+ 'LINBRRH_LDIV': '$f', #
+ 'LINDLR' : '$cf', # LIN Data Length Register
+ 'LINDLR_LTXDL': '$f0', # LIN Transmit Data Length bits
+ 'LINDLR_LRXDL': '$f', # LIN Receive Data Length bits
+ 'LINIDR' : '$d0', # LIN Identifier Register
+ 'LINIDR_LP': '$c0', # Parity bits
+ 'LINIDR_LID': '$3f', # Identifier bit 5 or Data Lengt
+ 'LINSEL' : '$d1', # LIN Data Buffer Selection Regi
+ 'LINSEL_LAINC': '$8', # Auto Increment of Data Buffer
+ 'LINSEL_LINDX': '$7', # FIFO LIN Data Buffer Index bit
+ 'LINDAT' : '$d2', # LIN Data Register
+ 'LINDAT_LDATA': '$ff', #
+
+# Module SPI
+ 'SPCR' : '$4c', # SPI Control Register
+ 'SPCR_SPIE': '$80', # SPI Interrupt Enable
+ 'SPCR_SPE': '$40', # SPI Enable
+ 'SPCR_DORD': '$20', # Data Order
+ 'SPCR_MSTR': '$10', # Master/Slave Select
+ 'SPCR_CPOL': '$8', # Clock polarity
+ 'SPCR_CPHA': '$4', # Clock Phase
+ 'SPCR_SPR': '$3', # SPI Clock Rate Selects
+ 'SPSR' : '$4d', # SPI Status Register
+ 'SPSR_SPIF': '$80', # SPI Interrupt Flag
+ 'SPSR_WCOL': '$40', # Write Collision Flag
+ 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
+ 'SPDR' : '$4e', # SPI Data Register
+
+# Module WATCHDOG
+ 'WDTCSR' : '$60', # Watchdog Timer Control Registe
+ 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
+ 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
+ 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
+ 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
+ 'WDTCSR_WDE': '$8', # Watch Dog Enable
+
+# Module EXTERNAL_INTERRUPT
+ 'EICRA' : '$69', # External Interrupt Control Reg
+ 'EICRA_ISC3': '$c0', # External Interrupt Sense Contr
+ 'EICRA_ISC2': '$30', # External Interrupt Sense Contr
+ 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
+ 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
+ 'EIMSK' : '$3d', # External Interrupt Mask Regist
+ 'EIMSK_INT': '$f', # External Interrupt Request 3 E
+ 'EIFR' : '$3c', # External Interrupt Flag Regist
+ 'EIFR_INTF': '$f', # External Interrupt Flags
+ 'PCICR' : '$68', # Pin Change Interrupt Control R
+ 'PCICR_PCIE': '$f', # Pin Change Interrupt Enables
+ 'PCMSK3' : '$6d', # Pin Change Mask Register 3
+ 'PCMSK3_PCINT': '$7', # Pin Change Enable Masks
+ 'PCMSK2' : '$6c', # Pin Change Mask Register 2
+ 'PCMSK2_PCINT': '$ff', # Pin Change Enable Masks
+ 'PCMSK1' : '$6b', # Pin Change Mask Register 1
+ 'PCMSK1_PCINT': '$ff', # Pin Change Enable Masks
+ 'PCMSK0' : '$6a', # Pin Change Mask Register 0
+ 'PCMSK0_PCINT': '$ff', # Pin Change Enable Masks
+ 'PCIFR' : '$3b', # Pin Change Interrupt Flag Regi
+ 'PCIFR_PCIF': '$f', # Pin Change Interrupt Flags
+
+# Module EEPROM
+ 'EEAR' : '$41', # EEPROM Read/Write Access
+ 'EEDR' : '$40', # EEPROM Data Register
+ 'EECR' : '$3f', # EEPROM Control Register
+ 'EECR_EEPM': '$30', #
+ 'EECR_EERIE': '$8', # EEProm Ready Interrupt Enable
+ 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
+ 'EECR_EEWE': '$2', # EEPROM Write Enable
+ 'EECR_EERE': '$1', # EEPROM Read Enable
+
+ '__amforth_dummy':'0'
+}
diff --git a/amforth-6.5/avr8/devices/atmega64c1/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega64c1/words/no-jtag.asm
new file mode 100644
index 0000000..352a4bb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega64c1/words/no-jtag.asm
@@ -0,0 +1,14 @@
+; ( -- )
+; ( -- )
+; MCU
+; disable jtag at runtime
+VE_NOJTAG:
+ .dw $FF05
+ .db "-jtag",0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOJTAG
+XT_NOJTAG:
+ .dw PFA_NOJTAG
+PFA_NOJTAG:
+
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega64c1/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega64c1/words/no-wdt.asm
new file mode 100644
index 0000000..ff6ddd1
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega64c1/words/no-wdt.asm
@@ -0,0 +1,34 @@
+; ( -- )
+; MCU
+; disable watch dog timer at runtime
+VE_NOWDT:
+ .dw $ff04
+ .db "-wdt"
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOWDT
+XT_NOWDT:
+ .dw PFA_NOWDT
+PFA_NOWDT:
+
+ in temp1,SREG
+ push temp1
+ ; Turn always off global interrupt.
+ cli
+ ; Reset Watchdog Timer
+ wdr
+ ; Clear WDRF in MCUSR
+ in temp1, MCUSR
+ andi temp1, (0xff & (0<<WDRF))
+ out MCUSR, temp1
+ ; Write logical one to WDCE and WDE
+ ; Keep old prescaler setting to prevent unintentional time-out
+ in_ temp1, WDTCSR
+ ori temp1, (1<<WDCE) | (1<<WDE)
+ out_ WDTCSR, temp1
+ ; Turn off WDT
+ ldi temp1, (0<<WDE)
+ out_ WDTCSR, temp1
+ ; restore status register
+ pop temp1
+ out SREG,temp1
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega64c1/words/sleep.asm b/amforth-6.5/avr8/devices/atmega64c1/words/sleep.asm
new file mode 100644
index 0000000..256249c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega64c1/words/sleep.asm
@@ -0,0 +1,19 @@
+; ( mode -- )
+; MCU
+; put the controller into the specified sleep mode
+VE_SLEEP:
+ .dw $ff05
+ .db "sleep", 0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_SLEEP
+XT_SLEEP:
+ .dw PFA_SLEEP
+PFA_SLEEP:
+ andi tosl, 7 ; leave only legal mode bits
+ lsl tosl ; move to correct location (bits 3-1)
+ ori tosl, 1 ; set the SE bit
+ out_ SMCR, tosl ; set the sleep config
+ sleep ; nighty-night
+ out_ SMCR, zerol ; 0 protects against accidental sleeps
+ loadtos ; pop argument from stack
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega64hve/atmega64hve.frt b/amforth-6.5/avr8/devices/atmega64hve/atmega64hve.frt
new file mode 100644
index 0000000..3150df4
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega64hve/atmega64hve.frt
@@ -0,0 +1,154 @@
+\ Partname: ATmega64HVE
+\ Built using part description XML file version 1
+\ generated automatically
+
+hex
+
+\ AD_CONVERTER
+e2 constant ADCRA \ ADC Control Register A
+e3 constant ADCRB \ ADC Control Register B
+e4 constant ADCRC \ ADC Control Register B
+e5 constant ADCRD \ ADC Control Register D
+e6 constant ADCRE \ ADC Control Register E
+e7 constant ADIFR \ ADC Interrupt Flag Register
+e8 constant ADIMR \ ADC Interrupt Mask Register
+e0 constant ADSCSRA \ ADC Synchronization Control and Status Register
+e1 constant ADSCSRB \ ADC Synchronization Control and Status Register
+ed constant CADAC0 \ C-ADC Accumulated Conversion Result
+ee constant CADAC1 \ C-ADC Accumulated Conversion Result
+ef constant CADAC2 \ C-ADC Accumulated Conversion Result
+f0 constant CADAC3 \ C-ADC Accumulated Conversion Result
+ec constant CADICH \ C-ADC Instantaneous Conversion Result
+eb constant CADICL \ C-ADC Instantaneous Conversion Result
+ea constant CADRCLH \ CC-ADC Regulator Current Comparator Threshold Level
+e9 constant CADRCLL \ CC-ADC Regulator Current Comparator Threshold Level
+f3 constant VADAC0 \ V-ADC Accumulated Conversion Result
+f4 constant VADAC1 \ V-ADC Accumulated Conversion Result
+f5 constant VADAC2 \ V-ADC Accumulated Conversion Result
+f6 constant VADAC3 \ V-ADC Accumulated Conversion Result
+f2 constant VADICH \ V-ADC Instantaneous Conversion Result
+f1 constant VADICL \ V-ADC Instantaneous Conversion Result
+
+\ BANDGAP
+d3 constant BGCRA \ Band Gap Calibration Register A
+d2 constant BGCRB \ Band Gap Calibration Register B
+d1 constant BGCSRA \ Bandgap Control and Status Register A
+d4 constant BGLR \ Band Gap Lock Register
+
+\ BOOT_LOAD
+57 constant SPMCSR \ Store Program Memory Control and Status Register
+
+\ CPU
+61 constant CLKPR \ Clock Prescale Register
+7E constant DIDR0 \ Digital Input Disable Register
+3E constant GPIOR0 \ General Purpose IO Register 0
+4A constant GPIOR1 \ General Purpose IO Register 1
+4B constant GPIOR2 \ General Purpose IO Register 2
+55 constant MCUCR \ MCU Control Register
+54 constant MCUSR \ MCU Status Register
+d8 constant PLLCSR \ PLL Control and Status Register
+64 constant PRR0 \ Power Reduction Register 0
+53 constant SMCR \ Sleep Mode Control Register
+66 constant SOSCCALA \ Slow Oscillator Calibration Register A
+67 constant SOSCCALB \ Oscillator Calibration Register B
+5E constant SPH \ Stack Pointer High
+5D constant SPL \ Stack Pointer Low
+5F constant SREG \ Status Register
+
+\ EEPROM
+42 constant EEARH \ EEPROM Read/Write Access
+41 constant EEARL \ EEPROM Read/Write Access
+3F constant EECR \ EEPROM Control Register
+40 constant EEDR \ EEPROM Data Register
+
+\ EXTERNAL_INTERRUPT
+69 constant EICRA \ External Interrupt Control Register
+3C constant EIFR \ External Interrupt Flag Register
+3D constant EIMSK \ External Interrupt Mask Register
+68 constant PCICR \ Pin Change Interrupt Control Register
+3B constant PCIFR \ Pin Change Interrupt Flag Register
+6B constant PCMSK0 \ Pin Change Enable Mask Register 0
+6C constant PCMSK1 \ Pin Change Enable Mask Register 1
+
+\ LINUART
+c6 constant LINBRRH \ LIN Baud Rate High Register
+c5 constant LINBRRL \ LIN Baud Rate Low Register
+c4 constant LINBTR \ LIN Bit Timing Register
+c0 constant LINCR \ LIN Control Register
+cA constant LINDAT \ LIN Data Register
+c7 constant LINDLR \ LIN Data Length Register
+c2 constant LINENIR \ LIN Enable Interrupt Register
+c3 constant LINERR \ LIN Error Register
+c8 constant LINIDR \ LIN Identifier Register
+c9 constant LINSEL \ LIN Data Buffer Selection Register
+c1 constant LINSIR \ LIN Status and Interrupt Register
+
+\ PORTA
+21 constant DDRA \ Port A Data Direction Register
+20 constant PINA \ Port A Input Pins
+22 constant PORTA \ Port A Data Register
+
+\ PORTB
+24 constant DDRB \ Port B Data Direction Register
+dc constant PBOV \ Port B Override
+23 constant PINB \ Port B Input Pins
+25 constant PORTB \ Port B Data Register
+
+\ SPI
+4c constant SPCR \ SPI Control Register
+4e constant SPDR \ SPI Data Register
+4d constant SPSR \ SPI Status Register
+
+\ TIMER_COUNTER_0
+43 constant GTCCR \ General Timer/Counter Control Register
+48 constant OCR0A \ Output Compare Register 0A
+49 constant OCR0B \ Output Compare Register B
+44 constant TCCR0A \ Timer/Counter 0 Control Register A
+45 constant TCCR0B \ Timer/Counter0 Control Register B
+47 constant TCNT0H \ Timer Counter 0 High Byte
+46 constant TCNT0L \ Timer Counter 0 Low Byte
+35 constant TIFR0 \ Timer/Counter Interrupt Flag register
+6E constant TIMSK0 \ Timer/Counter Interrupt Mask Register
+
+\ TIMER_COUNTER_1
+88 constant OCR1A \ Output Compare Register 1A
+89 constant OCR1B \ Output Compare Register B
+80 constant TCCR1A \ Timer/Counter 1 Control Register A
+81 constant TCCR1B \ Timer/Counter1 Control Register B
+85 constant TCNT1H \ Timer Counter 1 High Byte
+84 constant TCNT1L \ Timer Counter 1 Low Byte
+36 constant TIFR1 \ Timer/Counter Interrupt Flag register
+6F constant TIMSK1 \ Timer/Counter Interrupt Mask Register
+
+\ WAKEUP_TIMER
+62 constant WUTCSR \ Wake-up Timer Control and Status Register
+
+\ WATCHDOG
+63 constant WDTCLR \ Watchdog Timer Configuration Lock Register
+60 constant WDTCSR \ Watchdog Timer Control Register
+
+\ Interrupts
+0002 constant INT0Addr \ External Interrupt 0
+0004 constant PCINT0Addr \ Pin Change Interrupt 0
+0006 constant PCINT1Addr \ Pin Change Interrupt 1
+0008 constant WDTAddr \ Watchdog Timeout Interrupt
+000a constant WAKEUPAddr \ Wakeup Timer Overflow
+000c constant TIMER1_ICAddr \ Timer 1 Input capture
+000e constant TIMER1_COMPAAddr \ Timer 1 Compare Match A
+0010 constant TIMER1_COMPBAddr \ Timer 1 Compare Match B
+0012 constant TIMER1_OVFAddr \ Timer 1 overflow
+0014 constant TIMER0_ICAddr \ Timer 0 Input Capture
+0016 constant TIMER0_COMPAAddr \ Timer 0 Comapre Match A
+0018 constant TIMER0_COMPBAddr \ Timer 0 Compare Match B
+001a constant TIMER0_OVFAddr \ Timer 0 Overflow
+001c constant LIN_STATUSAddr \ LIN Status Interrupt
+001e constant LIN_ERRORAddr \ LIN Error Interrupt
+0020 constant SPI_STCAddr \ SPI Serial transfer complete
+0022 constant VADC_CONVAddr \ Voltage ADC Instantaneous Conversion Complet
+0024 constant VADC_ACCAddr \ Voltage ADC Accumulated Conversion Complete
+0026 constant CADC_CONVAddr \ C-ADC Instantaneous Conversion Complete
+0028 constant CADC_REG_CURAddr \ C-ADC Regular Current
+002a constant CADC_ACCAddr \ C-ADC Accumulated Conversion Complete
+02c constant EE_READYAddr \ EEPROM Ready
+02e constant SPMAddr \ SPM Ready
+030 constant PLLAddr \ PLL Lock Change Interrupt
diff --git a/amforth-6.5/avr8/devices/atmega64hve/device.asm b/amforth-6.5/avr8/devices/atmega64hve/device.asm
new file mode 100644
index 0000000..dc9b9ee
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega64hve/device.asm
@@ -0,0 +1,119 @@
+; Partname: ATmega64HVE
+; Built using part description XML file version 1
+; generated automatically, do not edit
+
+.nolist
+ .include "m64HVEdef.inc"
+.list
+
+.equ ramstart = $100
+.equ CELLSIZE = 2
+.macro readflashcell
+ lsl zl
+ rol zh
+ lpm @0, Z+
+ lpm @1, Z+
+.endmacro
+.macro writeflashcell
+ lsl zl
+ rol zh
+.endmacro
+
+; the following definitions are shortcuts for the respective forth source segments if set to 1
+.set WANT_AD_CONVERTER = 0
+.set WANT_BANDGAP = 0
+.set WANT_BOOT_LOAD = 0
+.set WANT_CPU = 0
+.set WANT_EEPROM = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_LINUART = 0
+.set WANT_PORTA = 0
+.set WANT_PORTB = 0
+.set WANT_SPI = 0
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_WAKEUP_TIMER = 0
+.set WANT_WATCHDOG = 0
+
+
+.ifndef SPMEN
+ .equ SPMEN = SELFPRGEN
+.endif
+
+.ifndef SPMCSR
+ .equ SPMCSR = SPMCR
+.endif
+
+.ifndef EEPE
+ .equ EEPE = EEWE
+.endif
+
+.ifndef EEMPE
+ .equ EEMPE = EEMWE
+.endif
+.equ intvecsize = 2 ; please verify; flash size: 65536 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.equ INTVECTORS = 25
+.org $0002
+ rcall isr ; External Interrupt 0
+.org $0004
+ rcall isr ; Pin Change Interrupt 0
+.org $0006
+ rcall isr ; Pin Change Interrupt 1
+.org $0008
+ rcall isr ; Watchdog Timeout Interrupt
+.org $000a
+ rcall isr ; Wakeup Timer Overflow
+.org $000c
+ rcall isr ; Timer 1 Input capture
+.org $000e
+ rcall isr ; Timer 1 Compare Match A
+.org $0010
+ rcall isr ; Timer 1 Compare Match B
+.org $0012
+ rcall isr ; Timer 1 overflow
+.org $0014
+ rcall isr ; Timer 0 Input Capture
+.org $0016
+ rcall isr ; Timer 0 Comapre Match A
+.org $0018
+ rcall isr ; Timer 0 Compare Match B
+.org $001a
+ rcall isr ; Timer 0 Overflow
+.org $001c
+ rcall isr ; LIN Status Interrupt
+.org $001e
+ rcall isr ; LIN Error Interrupt
+.org $0020
+ rcall isr ; SPI Serial transfer complete
+.org $0022
+ rcall isr ; Voltage ADC Instantaneous Conversion Complete
+.org $0024
+ rcall isr ; Voltage ADC Accumulated Conversion Complete
+.org $0026
+ rcall isr ; C-ADC Instantaneous Conversion Complete
+.org $0028
+ rcall isr ; C-ADC Regular Current
+.org $002a
+ rcall isr ; C-ADC Accumulated Conversion Complete
+.org $02c
+ rcall isr ; EEPROM Ready
+.org $02e
+ rcall isr ; SPM Ready
+.org $030
+ rcall isr ; PLL Lock Change Interrupt
+.nooverlap
+mcu_info:
+mcu_ramsize:
+ .dw 4096
+mcu_eepromsize:
+ .dw 1024
+mcu_maxdp:
+ .dw 28672 ; minimum of 0x7000 (from XML) and 0xffff
+mcu_numints:
+ .dw 25
+mcu_name:
+ .dw 11
+ .db "ATmega64HVE",0
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega64hve/device.inc b/amforth-6.5/avr8/devices/atmega64hve/device.inc
new file mode 100644
index 0000000..749f94a
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega64hve/device.inc
@@ -0,0 +1,1227 @@
+; Partname: ATmega64HVE
+; Built using part description XML file version 1
+; generated automatically, no not edit
+
+; ********
+.if WANT_AD_CONVERTER == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Control Register A
+VE_ADCRA:
+ .dw $ff05
+ .db "ADCRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCRA
+XT_ADCRA:
+ .dw PFA_DOVARIABLE
+PFA_ADCRA:
+ .dw $e2
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Control Register B
+VE_ADCRB:
+ .dw $ff05
+ .db "ADCRB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCRB
+XT_ADCRB:
+ .dw PFA_DOVARIABLE
+PFA_ADCRB:
+ .dw $e3
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Control Register B
+VE_ADCRC:
+ .dw $ff05
+ .db "ADCRC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCRC
+XT_ADCRC:
+ .dw PFA_DOVARIABLE
+PFA_ADCRC:
+ .dw $e4
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Control Register D
+VE_ADCRD:
+ .dw $ff05
+ .db "ADCRD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCRD
+XT_ADCRD:
+ .dw PFA_DOVARIABLE
+PFA_ADCRD:
+ .dw $e5
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Control Register E
+VE_ADCRE:
+ .dw $ff05
+ .db "ADCRE",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCRE
+XT_ADCRE:
+ .dw PFA_DOVARIABLE
+PFA_ADCRE:
+ .dw $e6
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Interrupt Flag Register
+VE_ADIFR:
+ .dw $ff05
+ .db "ADIFR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADIFR
+XT_ADIFR:
+ .dw PFA_DOVARIABLE
+PFA_ADIFR:
+ .dw $e7
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Interrupt Mask Register
+VE_ADIMR:
+ .dw $ff05
+ .db "ADIMR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADIMR
+XT_ADIMR:
+ .dw PFA_DOVARIABLE
+PFA_ADIMR:
+ .dw $e8
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Synchronization Control and Status Register
+VE_ADSCSRA:
+ .dw $ff07
+ .db "ADSCSRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADSCSRA
+XT_ADSCSRA:
+ .dw PFA_DOVARIABLE
+PFA_ADSCSRA:
+ .dw $e0
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Synchronization Control and Status Register
+VE_ADSCSRB:
+ .dw $ff07
+ .db "ADSCSRB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADSCSRB
+XT_ADSCSRB:
+ .dw PFA_DOVARIABLE
+PFA_ADSCSRB:
+ .dw $e1
+; ( -- addr ) System Constant
+; R( -- )
+; C-ADC Accumulated Conversion Result
+VE_CADAC0:
+ .dw $ff06
+ .db "CADAC0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CADAC0
+XT_CADAC0:
+ .dw PFA_DOVARIABLE
+PFA_CADAC0:
+ .dw $ed
+; ( -- addr ) System Constant
+; R( -- )
+; C-ADC Accumulated Conversion Result
+VE_CADAC1:
+ .dw $ff06
+ .db "CADAC1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CADAC1
+XT_CADAC1:
+ .dw PFA_DOVARIABLE
+PFA_CADAC1:
+ .dw $ee
+; ( -- addr ) System Constant
+; R( -- )
+; C-ADC Accumulated Conversion Result
+VE_CADAC2:
+ .dw $ff06
+ .db "CADAC2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CADAC2
+XT_CADAC2:
+ .dw PFA_DOVARIABLE
+PFA_CADAC2:
+ .dw $ef
+; ( -- addr ) System Constant
+; R( -- )
+; C-ADC Accumulated Conversion Result
+VE_CADAC3:
+ .dw $ff06
+ .db "CADAC3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CADAC3
+XT_CADAC3:
+ .dw PFA_DOVARIABLE
+PFA_CADAC3:
+ .dw $f0
+; ( -- addr ) System Constant
+; R( -- )
+; C-ADC Instantaneous Conversion Result
+VE_CADICH:
+ .dw $ff06
+ .db "CADICH"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CADICH
+XT_CADICH:
+ .dw PFA_DOVARIABLE
+PFA_CADICH:
+ .dw $ec
+; ( -- addr ) System Constant
+; R( -- )
+; C-ADC Instantaneous Conversion Result
+VE_CADICL:
+ .dw $ff06
+ .db "CADICL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CADICL
+XT_CADICL:
+ .dw PFA_DOVARIABLE
+PFA_CADICL:
+ .dw $eb
+; ( -- addr ) System Constant
+; R( -- )
+; CC-ADC Regulator Current Comparator Threshold Level
+VE_CADRCLH:
+ .dw $ff07
+ .db "CADRCLH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CADRCLH
+XT_CADRCLH:
+ .dw PFA_DOVARIABLE
+PFA_CADRCLH:
+ .dw $ea
+; ( -- addr ) System Constant
+; R( -- )
+; CC-ADC Regulator Current Comparator Threshold Level
+VE_CADRCLL:
+ .dw $ff07
+ .db "CADRCLL",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CADRCLL
+XT_CADRCLL:
+ .dw PFA_DOVARIABLE
+PFA_CADRCLL:
+ .dw $e9
+; ( -- addr ) System Constant
+; R( -- )
+; V-ADC Accumulated Conversion Result
+VE_VADAC0:
+ .dw $ff06
+ .db "VADAC0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_VADAC0
+XT_VADAC0:
+ .dw PFA_DOVARIABLE
+PFA_VADAC0:
+ .dw $f3
+; ( -- addr ) System Constant
+; R( -- )
+; V-ADC Accumulated Conversion Result
+VE_VADAC1:
+ .dw $ff06
+ .db "VADAC1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_VADAC1
+XT_VADAC1:
+ .dw PFA_DOVARIABLE
+PFA_VADAC1:
+ .dw $f4
+; ( -- addr ) System Constant
+; R( -- )
+; V-ADC Accumulated Conversion Result
+VE_VADAC2:
+ .dw $ff06
+ .db "VADAC2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_VADAC2
+XT_VADAC2:
+ .dw PFA_DOVARIABLE
+PFA_VADAC2:
+ .dw $f5
+; ( -- addr ) System Constant
+; R( -- )
+; V-ADC Accumulated Conversion Result
+VE_VADAC3:
+ .dw $ff06
+ .db "VADAC3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_VADAC3
+XT_VADAC3:
+ .dw PFA_DOVARIABLE
+PFA_VADAC3:
+ .dw $f6
+; ( -- addr ) System Constant
+; R( -- )
+; V-ADC Instantaneous Conversion Result
+VE_VADICH:
+ .dw $ff06
+ .db "VADICH"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_VADICH
+XT_VADICH:
+ .dw PFA_DOVARIABLE
+PFA_VADICH:
+ .dw $f2
+; ( -- addr ) System Constant
+; R( -- )
+; V-ADC Instantaneous Conversion Result
+VE_VADICL:
+ .dw $ff06
+ .db "VADICL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_VADICL
+XT_VADICL:
+ .dw PFA_DOVARIABLE
+PFA_VADICL:
+ .dw $f1
+
+.endif
+
+; ********
+.if WANT_BANDGAP == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Band Gap Calibration Register A
+VE_BGCRA:
+ .dw $ff05
+ .db "BGCRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_BGCRA
+XT_BGCRA:
+ .dw PFA_DOVARIABLE
+PFA_BGCRA:
+ .dw $d3
+; ( -- addr ) System Constant
+; R( -- )
+; Band Gap Calibration Register B
+VE_BGCRB:
+ .dw $ff05
+ .db "BGCRB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_BGCRB
+XT_BGCRB:
+ .dw PFA_DOVARIABLE
+PFA_BGCRB:
+ .dw $d2
+; ( -- addr ) System Constant
+; R( -- )
+; Bandgap Control and Status Register A
+VE_BGCSRA:
+ .dw $ff06
+ .db "BGCSRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_BGCSRA
+XT_BGCSRA:
+ .dw PFA_DOVARIABLE
+PFA_BGCSRA:
+ .dw $d1
+; ( -- addr ) System Constant
+; R( -- )
+; Band Gap Lock Register
+VE_BGLR:
+ .dw $ff04
+ .db "BGLR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_BGLR
+XT_BGLR:
+ .dw PFA_DOVARIABLE
+PFA_BGLR:
+ .dw $d4
+
+.endif
+
+; ********
+.if WANT_BOOT_LOAD == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control and Status Register
+VE_SPMCSR:
+ .dw $ff06
+ .db "SPMCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCSR
+XT_SPMCSR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCSR:
+ .dw $57
+
+.endif
+
+; ********
+.if WANT_CPU == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Clock Prescale Register
+VE_CLKPR:
+ .dw $ff05
+ .db "CLKPR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKPR
+XT_CLKPR:
+ .dw PFA_DOVARIABLE
+PFA_CLKPR:
+ .dw $61
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register
+VE_DIDR0:
+ .dw $ff05
+ .db "DIDR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR0
+XT_DIDR0:
+ .dw PFA_DOVARIABLE
+PFA_DIDR0:
+ .dw $7E
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 0
+VE_GPIOR0:
+ .dw $ff06
+ .db "GPIOR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR0
+XT_GPIOR0:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR0:
+ .dw $3E
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 1
+VE_GPIOR1:
+ .dw $ff06
+ .db "GPIOR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR1
+XT_GPIOR1:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR1:
+ .dw $4A
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 2
+VE_GPIOR2:
+ .dw $ff06
+ .db "GPIOR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR2
+XT_GPIOR2:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR2:
+ .dw $4B
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw $55
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Status Register
+VE_MCUSR:
+ .dw $ff05
+ .db "MCUSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUSR
+XT_MCUSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUSR:
+ .dw $54
+; ( -- addr ) System Constant
+; R( -- )
+; PLL Control and Status Register
+VE_PLLCSR:
+ .dw $ff06
+ .db "PLLCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PLLCSR
+XT_PLLCSR:
+ .dw PFA_DOVARIABLE
+PFA_PLLCSR:
+ .dw $d8
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register 0
+VE_PRR0:
+ .dw $ff04
+ .db "PRR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR0
+XT_PRR0:
+ .dw PFA_DOVARIABLE
+PFA_PRR0:
+ .dw $64
+; ( -- addr ) System Constant
+; R( -- )
+; Sleep Mode Control Register
+VE_SMCR:
+ .dw $ff04
+ .db "SMCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SMCR
+XT_SMCR:
+ .dw PFA_DOVARIABLE
+PFA_SMCR:
+ .dw $53
+; ( -- addr ) System Constant
+; R( -- )
+; Slow Oscillator Calibration Register A
+VE_SOSCCALA:
+ .dw $ff08
+ .db "SOSCCALA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SOSCCALA
+XT_SOSCCALA:
+ .dw PFA_DOVARIABLE
+PFA_SOSCCALA:
+ .dw $66
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Calibration Register B
+VE_SOSCCALB:
+ .dw $ff08
+ .db "SOSCCALB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SOSCCALB
+XT_SOSCCALB:
+ .dw PFA_DOVARIABLE
+PFA_SOSCCALB:
+ .dw $67
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer High
+VE_SPH:
+ .dw $ff03
+ .db "SPH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPH
+XT_SPH:
+ .dw PFA_DOVARIABLE
+PFA_SPH:
+ .dw $5E
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer Low
+VE_SPL:
+ .dw $ff03
+ .db "SPL",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPL
+XT_SPL:
+ .dw PFA_DOVARIABLE
+PFA_SPL:
+ .dw $5D
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw $5F
+
+.endif
+
+; ********
+.if WANT_EEPROM == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Read/Write Access
+VE_EEARH:
+ .dw $ff05
+ .db "EEARH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEARH
+XT_EEARH:
+ .dw PFA_DOVARIABLE
+PFA_EEARH:
+ .dw $42
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Read/Write Access
+VE_EEARL:
+ .dw $ff05
+ .db "EEARL",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEARL
+XT_EEARL:
+ .dw PFA_DOVARIABLE
+PFA_EEARL:
+ .dw $41
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw $3F
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw $40
+
+.endif
+
+; ********
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register
+VE_EICRA:
+ .dw $ff05
+ .db "EICRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRA
+XT_EICRA:
+ .dw PFA_DOVARIABLE
+PFA_EICRA:
+ .dw $69
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Flag Register
+VE_EIFR:
+ .dw $ff04
+ .db "EIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIFR
+XT_EIFR:
+ .dw PFA_DOVARIABLE
+PFA_EIFR:
+ .dw $3C
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Mask Register
+VE_EIMSK:
+ .dw $ff05
+ .db "EIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIMSK
+XT_EIMSK:
+ .dw PFA_DOVARIABLE
+PFA_EIMSK:
+ .dw $3D
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Interrupt Control Register
+VE_PCICR:
+ .dw $ff05
+ .db "PCICR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCICR
+XT_PCICR:
+ .dw PFA_DOVARIABLE
+PFA_PCICR:
+ .dw $68
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Interrupt Flag Register
+VE_PCIFR:
+ .dw $ff05
+ .db "PCIFR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCIFR
+XT_PCIFR:
+ .dw PFA_DOVARIABLE
+PFA_PCIFR:
+ .dw $3B
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Enable Mask Register 0
+VE_PCMSK0:
+ .dw $ff06
+ .db "PCMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK0
+XT_PCMSK0:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK0:
+ .dw $6B
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Enable Mask Register 1
+VE_PCMSK1:
+ .dw $ff06
+ .db "PCMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK1
+XT_PCMSK1:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK1:
+ .dw $6C
+
+.endif
+
+; ********
+.if WANT_LINUART == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; LIN Baud Rate High Register
+VE_LINBRRH:
+ .dw $ff07
+ .db "LINBRRH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LINBRRH
+XT_LINBRRH:
+ .dw PFA_DOVARIABLE
+PFA_LINBRRH:
+ .dw $c6
+; ( -- addr ) System Constant
+; R( -- )
+; LIN Baud Rate Low Register
+VE_LINBRRL:
+ .dw $ff07
+ .db "LINBRRL",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LINBRRL
+XT_LINBRRL:
+ .dw PFA_DOVARIABLE
+PFA_LINBRRL:
+ .dw $c5
+; ( -- addr ) System Constant
+; R( -- )
+; LIN Bit Timing Register
+VE_LINBTR:
+ .dw $ff06
+ .db "LINBTR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LINBTR
+XT_LINBTR:
+ .dw PFA_DOVARIABLE
+PFA_LINBTR:
+ .dw $c4
+; ( -- addr ) System Constant
+; R( -- )
+; LIN Control Register
+VE_LINCR:
+ .dw $ff05
+ .db "LINCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LINCR
+XT_LINCR:
+ .dw PFA_DOVARIABLE
+PFA_LINCR:
+ .dw $c0
+; ( -- addr ) System Constant
+; R( -- )
+; LIN Data Register
+VE_LINDAT:
+ .dw $ff06
+ .db "LINDAT"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LINDAT
+XT_LINDAT:
+ .dw PFA_DOVARIABLE
+PFA_LINDAT:
+ .dw $cA
+; ( -- addr ) System Constant
+; R( -- )
+; LIN Data Length Register
+VE_LINDLR:
+ .dw $ff06
+ .db "LINDLR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LINDLR
+XT_LINDLR:
+ .dw PFA_DOVARIABLE
+PFA_LINDLR:
+ .dw $c7
+; ( -- addr ) System Constant
+; R( -- )
+; LIN Enable Interrupt Register
+VE_LINENIR:
+ .dw $ff07
+ .db "LINENIR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LINENIR
+XT_LINENIR:
+ .dw PFA_DOVARIABLE
+PFA_LINENIR:
+ .dw $c2
+; ( -- addr ) System Constant
+; R( -- )
+; LIN Error Register
+VE_LINERR:
+ .dw $ff06
+ .db "LINERR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LINERR
+XT_LINERR:
+ .dw PFA_DOVARIABLE
+PFA_LINERR:
+ .dw $c3
+; ( -- addr ) System Constant
+; R( -- )
+; LIN Identifier Register
+VE_LINIDR:
+ .dw $ff06
+ .db "LINIDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LINIDR
+XT_LINIDR:
+ .dw PFA_DOVARIABLE
+PFA_LINIDR:
+ .dw $c8
+; ( -- addr ) System Constant
+; R( -- )
+; LIN Data Buffer Selection Register
+VE_LINSEL:
+ .dw $ff06
+ .db "LINSEL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LINSEL
+XT_LINSEL:
+ .dw PFA_DOVARIABLE
+PFA_LINSEL:
+ .dw $c9
+; ( -- addr ) System Constant
+; R( -- )
+; LIN Status and Interrupt Register
+VE_LINSIR:
+ .dw $ff06
+ .db "LINSIR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LINSIR
+XT_LINSIR:
+ .dw PFA_DOVARIABLE
+PFA_LINSIR:
+ .dw $c1
+
+.endif
+
+; ********
+.if WANT_PORTA == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Direction Register
+VE_DDRA:
+ .dw $ff04
+ .db "DDRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRA
+XT_DDRA:
+ .dw PFA_DOVARIABLE
+PFA_DDRA:
+ .dw $21
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Input Pins
+VE_PINA:
+ .dw $ff04
+ .db "PINA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINA
+XT_PINA:
+ .dw PFA_DOVARIABLE
+PFA_PINA:
+ .dw $20
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Register
+VE_PORTA:
+ .dw $ff05
+ .db "PORTA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTA
+XT_PORTA:
+ .dw PFA_DOVARIABLE
+PFA_PORTA:
+ .dw $22
+
+.endif
+
+; ********
+.if WANT_PORTB == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw $24
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Override
+VE_PBOV:
+ .dw $ff04
+ .db "PBOV"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PBOV
+XT_PBOV:
+ .dw PFA_DOVARIABLE
+PFA_PBOV:
+ .dw $dc
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw $23
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw $25
+
+.endif
+
+; ********
+.if WANT_SPI == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR:
+ .dw $ff04
+ .db "SPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR
+XT_SPCR:
+ .dw PFA_DOVARIABLE
+PFA_SPCR:
+ .dw $4c
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR:
+ .dw $ff04
+ .db "SPDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR
+XT_SPDR:
+ .dw PFA_DOVARIABLE
+PFA_SPDR:
+ .dw $4e
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR:
+ .dw $ff04
+ .db "SPSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR
+XT_SPSR:
+ .dw PFA_DOVARIABLE
+PFA_SPSR:
+ .dw $4d
+
+.endif
+
+; ********
+.if WANT_TIMER_COUNTER_0 == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; General Timer/Counter Control Register
+VE_GTCCR:
+ .dw $ff05
+ .db "GTCCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GTCCR
+XT_GTCCR:
+ .dw PFA_DOVARIABLE
+PFA_GTCCR:
+ .dw $43
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare Register 0A
+VE_OCR0A:
+ .dw $ff05
+ .db "OCR0A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0A
+XT_OCR0A:
+ .dw PFA_DOVARIABLE
+PFA_OCR0A:
+ .dw $48
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare Register B
+VE_OCR0B:
+ .dw $ff05
+ .db "OCR0B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0B
+XT_OCR0B:
+ .dw PFA_DOVARIABLE
+PFA_OCR0B:
+ .dw $49
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter 0 Control Register A
+VE_TCCR0A:
+ .dw $ff06
+ .db "TCCR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0A
+XT_TCCR0A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0A:
+ .dw $44
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Control Register B
+VE_TCCR0B:
+ .dw $ff06
+ .db "TCCR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0B
+XT_TCCR0B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0B:
+ .dw $45
+; ( -- addr ) System Constant
+; R( -- )
+; Timer Counter 0 High Byte
+VE_TCNT0H:
+ .dw $ff06
+ .db "TCNT0H"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0H
+XT_TCNT0H:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0H:
+ .dw $47
+; ( -- addr ) System Constant
+; R( -- )
+; Timer Counter 0 Low Byte
+VE_TCNT0L:
+ .dw $ff06
+ .db "TCNT0L"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0L
+XT_TCNT0L:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0L:
+ .dw $46
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Flag register
+VE_TIFR0:
+ .dw $ff05
+ .db "TIFR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR0
+XT_TIFR0:
+ .dw PFA_DOVARIABLE
+PFA_TIFR0:
+ .dw $35
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Mask Register
+VE_TIMSK0:
+ .dw $ff06
+ .db "TIMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK0
+XT_TIMSK0:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK0:
+ .dw $6E
+
+.endif
+
+; ********
+.if WANT_TIMER_COUNTER_1 == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare Register 1A
+VE_OCR1A:
+ .dw $ff05
+ .db "OCR1A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1A
+XT_OCR1A:
+ .dw PFA_DOVARIABLE
+PFA_OCR1A:
+ .dw $88
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare Register B
+VE_OCR1B:
+ .dw $ff05
+ .db "OCR1B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1B
+XT_OCR1B:
+ .dw PFA_DOVARIABLE
+PFA_OCR1B:
+ .dw $89
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter 1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw $80
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw $81
+; ( -- addr ) System Constant
+; R( -- )
+; Timer Counter 1 High Byte
+VE_TCNT1H:
+ .dw $ff06
+ .db "TCNT1H"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1H
+XT_TCNT1H:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1H:
+ .dw $85
+; ( -- addr ) System Constant
+; R( -- )
+; Timer Counter 1 Low Byte
+VE_TCNT1L:
+ .dw $ff06
+ .db "TCNT1L"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1L
+XT_TCNT1L:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1L:
+ .dw $84
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Flag register
+VE_TIFR1:
+ .dw $ff05
+ .db "TIFR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR1
+XT_TIFR1:
+ .dw PFA_DOVARIABLE
+PFA_TIFR1:
+ .dw $36
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Mask Register
+VE_TIMSK1:
+ .dw $ff06
+ .db "TIMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK1
+XT_TIMSK1:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK1:
+ .dw $6F
+
+.endif
+
+; ********
+.if WANT_WAKEUP_TIMER == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Wake-up Timer Control and Status Register
+VE_WUTCSR:
+ .dw $ff06
+ .db "WUTCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WUTCSR
+XT_WUTCSR:
+ .dw PFA_DOVARIABLE
+PFA_WUTCSR:
+ .dw $62
+
+.endif
+
+; ********
+.if WANT_WATCHDOG == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Configuration Lock Register
+VE_WDTCLR:
+ .dw $ff06
+ .db "WDTCLR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCLR
+XT_WDTCLR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCLR:
+ .dw $63
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCSR:
+ .dw $ff06
+ .db "WDTCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCSR
+XT_WDTCSR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCSR:
+ .dw $60
+
+.endif
diff --git a/amforth-6.5/avr8/devices/atmega64hve/device.py b/amforth-6.5/avr8/devices/atmega64hve/device.py
new file mode 100644
index 0000000..6bba39c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega64hve/device.py
@@ -0,0 +1,124 @@
+# Partname: ATmega64HVE
+# Built using part description XML file version 1
+# generated automatically, do not edit
+MCUREGS = {
+ 'ADCRA': '$e2',
+ 'ADCRB': '$e3',
+ 'ADCRC': '$e4',
+ 'ADCRD': '$e5',
+ 'ADCRE': '$e6',
+ 'ADIFR': '$e7',
+ 'ADIMR': '$e8',
+ 'ADSCSRA': '$e0',
+ 'ADSCSRB': '$e1',
+ 'CADAC0': '$ed',
+ 'CADAC1': '$ee',
+ 'CADAC2': '$ef',
+ 'CADAC3': '$f0',
+ 'CADICH': '$ec',
+ 'CADICL': '$eb',
+ 'CADRCLH': '$ea',
+ 'CADRCLL': '$e9',
+ 'VADAC0': '$f3',
+ 'VADAC1': '$f4',
+ 'VADAC2': '$f5',
+ 'VADAC3': '$f6',
+ 'VADICH': '$f2',
+ 'VADICL': '$f1',
+ 'BGCRA': '$d3',
+ 'BGCRB': '$d2',
+ 'BGCSRA': '$d1',
+ 'BGLR': '$d4',
+ 'SPMCSR': '$57',
+ 'CLKPR': '$61',
+ 'DIDR0': '$7E',
+ 'GPIOR0': '$3E',
+ 'GPIOR1': '$4A',
+ 'GPIOR2': '$4B',
+ 'MCUCR': '$55',
+ 'MCUSR': '$54',
+ 'PLLCSR': '$d8',
+ 'PRR0': '$64',
+ 'SMCR': '$53',
+ 'SOSCCALA': '$66',
+ 'SOSCCALB': '$67',
+ 'SPH': '$5E',
+ 'SPL': '$5D',
+ 'SREG': '$5F',
+ 'EEARH': '$42',
+ 'EEARL': '$41',
+ 'EECR': '$3F',
+ 'EEDR': '$40',
+ 'EICRA': '$69',
+ 'EIFR': '$3C',
+ 'EIMSK': '$3D',
+ 'PCICR': '$68',
+ 'PCIFR': '$3B',
+ 'PCMSK0': '$6B',
+ 'PCMSK1': '$6C',
+ 'LINBRRH': '$c6',
+ 'LINBRRL': '$c5',
+ 'LINBTR': '$c4',
+ 'LINCR': '$c0',
+ 'LINDAT': '$cA',
+ 'LINDLR': '$c7',
+ 'LINENIR': '$c2',
+ 'LINERR': '$c3',
+ 'LINIDR': '$c8',
+ 'LINSEL': '$c9',
+ 'LINSIR': '$c1',
+ 'DDRA': '$21',
+ 'PINA': '$20',
+ 'PORTA': '$22',
+ 'DDRB': '$24',
+ 'PBOV': '$dc',
+ 'PINB': '$23',
+ 'PORTB': '$25',
+ 'SPCR': '$4c',
+ 'SPDR': '$4e',
+ 'SPSR': '$4d',
+ 'GTCCR': '$43',
+ 'OCR0A': '$48',
+ 'OCR0B': '$49',
+ 'TCCR0A': '$44',
+ 'TCCR0B': '$45',
+ 'TCNT0H': '$47',
+ 'TCNT0L': '$46',
+ 'TIFR0': '$35',
+ 'TIMSK0': '$6E',
+ 'OCR1A': '$88',
+ 'OCR1B': '$89',
+ 'TCCR1A': '$80',
+ 'TCCR1B': '$81',
+ 'TCNT1H': '$85',
+ 'TCNT1L': '$84',
+ 'TIFR1': '$36',
+ 'TIMSK1': '$6F',
+ 'WUTCSR': '$62',
+ 'WDTCLR': '$63',
+ 'WDTCSR': '$60',
+ 'INT0Addr': '$0002',
+ 'PCINT0Addr': '$0004',
+ 'PCINT1Addr': '$0006',
+ 'WDTAddr': '$0008',
+ 'WAKEUPAddr': '$000a',
+ 'TIMER1_ICAddr': '$000c',
+ 'TIMER1_COMPAAddr': '$000e',
+ 'TIMER1_COMPBAddr': '$0010',
+ 'TIMER1_OVFAddr': '$0012',
+ 'TIMER0_ICAddr': '$0014',
+ 'TIMER0_COMPAAddr': '$0016',
+ 'TIMER0_COMPBAddr': '$0018',
+ 'TIMER0_OVFAddr': '$001a',
+ 'LIN_STATUSAddr': '$001c',
+ 'LIN_ERRORAddr': '$001e',
+ 'SPI_STCAddr': '$0020',
+ 'VADC_CONVAddr': '$0022',
+ 'VADC_ACCAddr': '$0024',
+ 'CADC_CONVAddr': '$0026',
+ 'CADC_REG_CURAddr': '$0028',
+ 'CADC_ACCAddr': '$002a',
+ 'EE_READYAddr': '$02c',
+ 'SPMAddr': '$02e',
+ 'PLLAddr': '$030'
+} \ No newline at end of file
diff --git a/amforth-6.5/avr8/devices/atmega64m1/atmega64m1.frt b/amforth-6.5/avr8/devices/atmega64m1/atmega64m1.frt
new file mode 100644
index 0000000..135e761
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega64m1/atmega64m1.frt
@@ -0,0 +1,513 @@
+\ Partname: ATmega64M1
+\ generated automatically
+
+\ PORTB
+&37 constant PORTB \ Port B Data Register
+&36 constant DDRB \ Port B Data Direction Register
+&35 constant PINB \ Port B Input Pins
+\ PORTC
+&40 constant PORTC \ Port C Data Register
+&39 constant DDRC \ Port C Data Direction Register
+&38 constant PINC \ Port C Input Pins
+\ PORTD
+&43 constant PORTD \ Port D Data Register
+&42 constant DDRD \ Port D Data Direction Register
+&41 constant PIND \ Port D Input Pins
+\ CAN
+&216 constant CANGCON \ CAN General Control Register
+ $80 constant CANGCON_ABRQ \ Abort Request
+ $40 constant CANGCON_OVRQ \ Overload Frame Request
+ $20 constant CANGCON_TTC \ Time Trigger Communication
+ $10 constant CANGCON_SYNTTC \ Synchronization of TTC
+ $08 constant CANGCON_LISTEN \ Listening Mode
+ $04 constant CANGCON_TEST \ Test Mode
+ $02 constant CANGCON_ENASTB \ Enable / Standby
+ $01 constant CANGCON_SWRES \ Software Reset Request
+&217 constant CANGSTA \ CAN General Status Register
+ $40 constant CANGSTA_OVFG \ Overload Frame Flag
+ $10 constant CANGSTA_TXBSY \ Transmitter Busy
+ $08 constant CANGSTA_RXBSY \ Receiver Busy
+ $04 constant CANGSTA_ENFG \ Enable Flag
+ $02 constant CANGSTA_BOFF \ Bus Off Mode
+ $01 constant CANGSTA_ERRP \ Error Passive Mode
+&218 constant CANGIT \ CAN General Interrupt Register Flags
+ $80 constant CANGIT_CANIT \ General Interrupt Flag
+ $40 constant CANGIT_BOFFIT \ Bus Off Interrupt Flag
+ $20 constant CANGIT_OVRTIM \ Overrun CAN Timer Flag
+ $10 constant CANGIT_BXOK \ Burst Receive Interrupt Flag
+ $08 constant CANGIT_SERG \ Stuff Error General Flag
+ $04 constant CANGIT_CERG \ CRC Error General Flag
+ $02 constant CANGIT_FERG \ Form Error General Flag
+ $01 constant CANGIT_AERG \ Ackknowledgement Error General Flag
+&219 constant CANGIE \ CAN General Interrupt Enable Register
+ $80 constant CANGIE_ENIT \ Enable all Interrupts
+ $40 constant CANGIE_ENBOFF \ Enable Bus Off Interrupt
+ $20 constant CANGIE_ENRX \ Enable Receive Interrupt
+ $10 constant CANGIE_ENTX \ Enable Transmitt Interrupt
+ $08 constant CANGIE_ENERR \ Enable MOb Error Interrupt
+ $04 constant CANGIE_ENBX \ Enable Burst Receive Interrupt
+ $02 constant CANGIE_ENERG \ Enable General Error Interrupt
+ $01 constant CANGIE_ENOVRT \ Enable CAN Timer Overrun Interrupt
+&220 constant CANEN2 \ Enable MOb Register 2
+ $3F constant CANEN2_ENMOB \ Enable MObs
+&221 constant CANEN1 \ Enable MOb Register 1(empty)
+&222 constant CANIE2 \ Enable Interrupt MOb Register 2
+ $3F constant CANIE2_IEMOB \ Interrupt Enable MObs
+&223 constant CANIE1 \ Enable Interrupt MOb Register 1 (empty)
+&224 constant CANSIT2 \ CAN Status Interrupt MOb Register 2
+ $3F constant CANSIT2_SIT \ Status of Interrupt MObs
+&225 constant CANSIT1 \ CAN Status Interrupt MOb Register 1 (empty)
+&226 constant CANBT1 \ CAN Bit Timing Register 1
+ $7E constant CANBT1_BRP \ Baud Rate Prescaler bits
+&227 constant CANBT2 \ CAN Bit Timing Register 2
+ $60 constant CANBT2_SJW \ Re-Sync Jump Width bits
+ $0E constant CANBT2_PRS \ Propagation Time Segment bits
+&228 constant CANBT3 \ CAN Bit Timing Register 3
+ $70 constant CANBT3_PHS2 \ Phase Segment 2 bits
+ $0E constant CANBT3_PHS1 \ Phase Segment 1 bits
+ $01 constant CANBT3_SMP \ Sample Type
+&229 constant CANTCON \ Timer Control Register
+&230 constant CANTIML \ Timer Register Low
+&231 constant CANTIMH \ Timer Register High
+&232 constant CANTTCL \ TTC Timer Register Low
+&233 constant CANTTCH \ TTC Timer Register High
+&234 constant CANTEC \ Transmit Error Counter Register
+&235 constant CANREC \ Receive Error Counter Register
+&236 constant CANHPMOB \ Highest Priority MOb Register
+ $F0 constant CANHPMOB_HPMOB \ Highest Priority MOb Number bits
+ $0F constant CANHPMOB_CGP \ CAN General Purpose bits
+&237 constant CANPAGE \ Page MOb Register
+ $F0 constant CANPAGE_MOBNB \ MOb Number bits
+ $08 constant CANPAGE_AINC \ MOb Data Buffer Auto Increment (Active Low)
+ $07 constant CANPAGE_INDX \ Data Buffer Index bits
+&238 constant CANSTMOB \ MOb Status Register
+ $80 constant CANSTMOB_DLCW \ Data Length Code Warning on MOb
+ $40 constant CANSTMOB_TXOK \ Transmit OK on MOb
+ $20 constant CANSTMOB_RXOK \ Receive OK on MOb
+ $10 constant CANSTMOB_BERR \ Bit Error on MOb
+ $08 constant CANSTMOB_SERR \ Stuff Error on MOb
+ $04 constant CANSTMOB_CERR \ CRC Error on MOb
+ $02 constant CANSTMOB_FERR \ Form Error on MOb
+ $01 constant CANSTMOB_AERR \ Ackknowledgement Error on MOb
+&239 constant CANCDMOB \ MOb Control and DLC Register
+ $C0 constant CANCDMOB_CONMOB \ MOb Config bits
+ $20 constant CANCDMOB_RPLV \ Reply Valid
+ $10 constant CANCDMOB_IDE \ Identifier Extension
+ $0F constant CANCDMOB_DLC \ Data Length Code bits
+&240 constant CANIDT4 \ Identifier Tag Register 4
+ $F8 constant CANIDT4_IDT \
+ $04 constant CANIDT4_RTRTAG \
+ $02 constant CANIDT4_RB1TAG \
+ $01 constant CANIDT4_RB0TAG \
+&241 constant CANIDT3 \ Identifier Tag Register 3
+&242 constant CANIDT2 \ Identifier Tag Register 2
+&243 constant CANIDT1 \ Identifier Tag Register 1
+&244 constant CANIDM4 \ Identifier Mask Register 4
+&245 constant CANIDM3 \ Identifier Mask Register 3
+&246 constant CANIDM2 \ Identifier Mask Register 2
+&247 constant CANIDM1 \ Identifier Mask Register 1
+&248 constant CANSTML \ Time Stamp Register Low
+&249 constant CANSTMH \ Time Stamp Register High
+&250 constant CANMSG \ Message Data Register
+\ ANALOG_COMPARATOR
+&148 constant AC0CON \ Analog Comparator 0 Control Register
+ $80 constant AC0CON_AC0EN \ Analog Comparator 0 Enable Bit
+ $40 constant AC0CON_AC0IE \ Analog Comparator 0 Interrupt Enable Bit
+ $30 constant AC0CON_AC0IS \ Analog Comparator 0 Interrupt Select Bits
+ $08 constant AC0CON_ACCKSEL \ Analog Comparator Clock Select
+ $07 constant AC0CON_AC0M \ Analog Comparator 0 Multiplexer Register
+&149 constant AC1CON \ Analog Comparator 1 Control Register
+ $80 constant AC1CON_AC1EN \ Analog Comparator 1 Enable Bit
+ $40 constant AC1CON_AC1IE \ Analog Comparator 1 Interrupt Enable Bit
+ $30 constant AC1CON_AC1IS \ Analog Comparator 1 Interrupt Select Bit
+ $08 constant AC1CON_AC1ICE \ Analog Comparator 1 Interrupt Capture Enable Bit
+ $07 constant AC1CON_AC1M \ Analog Comparator 1 Multiplexer Register
+&150 constant AC2CON \ Analog Comparator 2 Control Register
+ $80 constant AC2CON_AC2EN \ Analog Comparator 2 Enable Bit
+ $40 constant AC2CON_AC2IE \ Analog Comparator 2 Interrupt Enable Bit
+ $30 constant AC2CON_AC2IS \ Analog Comparator 2 Interrupt Select Bit
+ $07 constant AC2CON_AC2M \ Analog Comparator 2 Multiplexer Register
+&151 constant AC3CON \ Analog Comparator 3 Control Register
+ $80 constant AC3CON_AC3EN \ Analog Comparator 3 Enable Bit
+ $40 constant AC3CON_AC3IE \ Analog Comparator 3 Interrupt Enable Bit
+ $30 constant AC3CON_AC3IS \ Analog Comparator 3 Interrupt Select Bit
+ $07 constant AC3CON_AC3M \ Analog Comparator 3 Multiplexer Register
+&80 constant ACSR \ Analog Comparator Status Register
+ $80 constant ACSR_AC3IF \ Analog Comparator 3 Interrupt Flag Bit
+ $40 constant ACSR_AC2IF \ Analog Comparator 2 Interrupt Flag Bit
+ $20 constant ACSR_AC1IF \ Analog Comparator 1 Interrupt Flag Bit
+ $10 constant ACSR_AC0IF \ Analog Comparator 0 Interrupt Flag Bit
+ $08 constant ACSR_AC3O \ Analog Comparator 3 Output Bit
+ $04 constant ACSR_AC2O \ Analog Comparator 2 Output Bit
+ $02 constant ACSR_AC1O \ Analog Comparator 1 Output Bit
+ $01 constant ACSR_AC0O \ Analog Comparator 0 Output Bit
+\ DA_CONVERTER
+&146 constant DACH \ DAC Data Register High Byte
+ $FF constant DACH_DACH \ DAC Data Register High Byte Bits
+&145 constant DACL \ DAC Data Register Low Byte
+ $FF constant DACL_DACL \ DAC Data Register Low Byte Bits
+&144 constant DACON \ DAC Control Register
+ $80 constant DACON_DAATE \ DAC Auto Trigger Enable Bit
+ $70 constant DACON_DATS \ DAC Trigger Selection Bits
+ $04 constant DACON_DALA \ DAC Left Adjust
+ $01 constant DACON_DAEN \ DAC Enable Bit
+\ CPU
+&87 constant SPMCSR \ Store Program Memory Control Register
+ $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
+ $20 constant SPMCSR_SIGRD \ Signature Row Read
+ $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
+ $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
+ $04 constant SPMCSR_PGWRT \ Page Write
+ $02 constant SPMCSR_PGERS \ Page Erase
+ $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
+&95 constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ $08 constant SREG_V \ Two's Complement Overflow Flag
+ $04 constant SREG_N \ Negative Flag
+ $02 constant SREG_Z \ Zero Flag
+ $01 constant SREG_C \ Carry Flag
+&93 constant SP \ Stack Pointer
+&85 constant MCUCR \ MCU Control Register
+ $80 constant MCUCR_SPIPS \ SPI Pin Select
+ $10 constant MCUCR_PUD \ Pull-up disable
+ $02 constant MCUCR_IVSEL \ Interrupt Vector Select
+ $01 constant MCUCR_IVCE \ Interrupt Vector Change Enable
+&84 constant MCUSR \ MCU Status Register
+ $08 constant MCUSR_WDRF \ Watchdog Reset Flag
+ $04 constant MCUSR_BORF \ Brown-out Reset Flag
+ $02 constant MCUSR_EXTRF \ External Reset Flag
+ $01 constant MCUSR_PORF \ Power-on reset flag
+&102 constant OSCCAL \ Oscillator Calibration Value
+&97 constant CLKPR \
+ $80 constant CLKPR_CLKPCE \
+ $0F constant CLKPR_CLKPS \
+&83 constant SMCR \ Sleep Mode Control Register
+ $0E constant SMCR_SM \ Sleep Mode Select bits
+ $01 constant SMCR_SE \ Sleep Enable
+&58 constant GPIOR2 \ General Purpose IO Register 2
+ $FF constant GPIOR2_GPIOR \ General Purpose IO Register 2 bis
+&57 constant GPIOR1 \ General Purpose IO Register 1
+ $FF constant GPIOR1_GPIOR \ General Purpose IO Register 1 bis
+&62 constant GPIOR0 \ General Purpose IO Register 0
+ $80 constant GPIOR0_GPIOR07 \ General Purpose IO Register 0 bit 7
+ $40 constant GPIOR0_GPIOR06 \ General Purpose IO Register 0 bit 6
+ $20 constant GPIOR0_GPIOR05 \ General Purpose IO Register 0 bit 5
+ $10 constant GPIOR0_GPIOR04 \ General Purpose IO Register 0 bit 4
+ $08 constant GPIOR0_GPIOR03 \ General Purpose IO Register 0 bit 3
+ $04 constant GPIOR0_GPIOR02 \ General Purpose IO Register 0 bit 2
+ $02 constant GPIOR0_GPIOR01 \ General Purpose IO Register 0 bit 1
+ $01 constant GPIOR0_GPIOR00 \ General Purpose IO Register 0 bit 0
+&73 constant PLLCSR \ PLL Control And Status Register
+ $04 constant PLLCSR_PLLF \ PLL Factor
+ $02 constant PLLCSR_PLLE \ PLL Enable
+ $01 constant PLLCSR_PLOCK \ PLL Lock Detector
+&100 constant PRR \ Power Reduction Register
+ $40 constant PRR_PRCAN \ Power Reduction CAN
+ $20 constant PRR_PRPSC \ Power Reduction PSC
+ $10 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
+ $08 constant PRR_PRTIM0 \ Power Reduction Timer/Counter0
+ $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
+ $02 constant PRR_PRLIN \ Power Reduction LIN UART
+ $01 constant PRR_PRADC \ Power Reduction ADC
+\ PORTE
+&46 constant PORTE \ Port E Data Register
+&45 constant DDRE \ Port E Data Direction Register
+&44 constant PINE \ Port E Input Pins
+\ TIMER_COUNTER_0
+&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
+ $04 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare Match B Interrupt Enable
+ $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match A Interrupt Enable
+ $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
+&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
+ $04 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare Flag 0B
+ $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0A
+ $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
+&68 constant TCCR0A \ Timer/Counter Control Register A
+ $C0 constant TCCR0A_COM0A \ Compare Output Mode, Phase Correct PWM Mode
+ $30 constant TCCR0A_COM0B \ Compare Output Mode, Fast PWm
+ $03 constant TCCR0A_WGM0 \ Waveform Generation Mode
+&69 constant TCCR0B \ Timer/Counter Control Register B
+ $80 constant TCCR0B_FOC0A \ Force Output Compare A
+ $40 constant TCCR0B_FOC0B \ Force Output Compare B
+ $08 constant TCCR0B_WGM02 \
+ $07 constant TCCR0B_CS0 \ Clock Select
+&70 constant TCNT0 \ Timer/Counter0
+&71 constant OCR0A \ Timer/Counter0 Output Compare Register
+&72 constant OCR0B \ Timer/Counter0 Output Compare Register
+&67 constant GTCCR \ General Timer/Counter Control Register
+ $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
+ $40 constant GTCCR_ICPSEL1 \ Timer1 Input Capture Selection Bit
+ $01 constant GTCCR_PSR10 \ Prescaler Reset Timer/Counter1 and Timer/Counter0
+\ TIMER_COUNTER_1
+&111 constant TIMSK1 \ Timer/Counter Interrupt Mask Register
+ $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
+ $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output CompareB Match Interrupt Enable
+ $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output CompareA Match Interrupt Enable
+ $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
+&54 constant TIFR1 \ Timer/Counter Interrupt Flag register
+ $20 constant TIFR1_ICF1 \ Input Capture Flag 1
+ $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
+ $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
+ $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
+&128 constant TCCR1A \ Timer/Counter1 Control Register A
+ $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
+ $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
+ $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
+&129 constant TCCR1B \ Timer/Counter1 Control Register B
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
+ $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
+&130 constant TCCR1C \ Timer/Counter1 Control Register C
+ $80 constant TCCR1C_FOC1A \
+ $40 constant TCCR1C_FOC1B \
+&132 constant TCNT1 \ Timer/Counter1 Bytes
+&136 constant OCR1A \ Timer/Counter1 Output Compare Register Bytes
+&138 constant OCR1B \ Timer/Counter1 Output Compare Register Bytes
+&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
+\ AD_CONVERTER
+&124 constant ADMUX \ The ADC multiplexer Selection Register
+ $C0 constant ADMUX_REFS \ Reference Selection Bits
+ $20 constant ADMUX_ADLAR \ Left Adjust Result
+ $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
+&122 constant ADCSRA \ The ADC Control and Status register
+ $80 constant ADCSRA_ADEN \ ADC Enable
+ $40 constant ADCSRA_ADSC \ ADC Start Conversion
+ $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
+ $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
+ $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
+ $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
+&120 constant ADC \ ADC Data Register Bytes
+&123 constant ADCSRB \ ADC Control and Status Register B
+ $80 constant ADCSRB_ADHSM \ ADC High Speed Mode
+ $40 constant ADCSRB_ISRCEN \ Current Source Enable
+ $20 constant ADCSRB_AREFEN \ Analog Reference pin Enable
+ $0F constant ADCSRB_ADTS \ ADC Auto Trigger Sources
+&126 constant DIDR0 \ Digital Input Disable Register 0
+ $80 constant DIDR0_ADC7D \ ADC7 Digital input Disable
+ $40 constant DIDR0_ADC6D \ ADC6 Digital input Disable
+ $20 constant DIDR0_ADC5D \ ADC5 Digital input Disable
+ $10 constant DIDR0_ADC4D \ ADC4 Digital input Disable
+ $08 constant DIDR0_ADC3D \ ADC3 Digital input Disable
+ $04 constant DIDR0_ADC2D \ ADC2 Digital input Disable
+ $02 constant DIDR0_ADC1D \ ADC1 Digital input Disable
+ $01 constant DIDR0_ADC0D \ ADC0 Digital input Disable
+&127 constant DIDR1 \ Digital Input Disable Register 0
+ $40 constant DIDR1_AMP2PD \ AMP2P Pin Digital input Disable
+ $20 constant DIDR1_ACMP0D \ ACMP0 Pin Digital input Disable
+ $10 constant DIDR1_AMP0PD \ AMP0P Pin Digital input Disable
+ $08 constant DIDR1_AMP0ND \ AMP0N Pin Digital input Disable
+ $04 constant DIDR1_ADC10D \ ADC10 Pin Digital input Disable
+ $02 constant DIDR1_ADC9D \ ADC9 Pin Digital input Disable
+ $01 constant DIDR1_ADC8D \ ADC8 Pin Digital input Disable
+&117 constant AMP0CSR \
+ $80 constant AMP0CSR_AMP0EN \
+ $40 constant AMP0CSR_AMP0IS \
+ $30 constant AMP0CSR_AMP0G \
+ $08 constant AMP0CSR_AMPCMP0 \ Amplifier 0 - Comparator 0 Connection
+ $07 constant AMP0CSR_AMP0TS \
+&118 constant AMP1CSR \
+ $80 constant AMP1CSR_AMP1EN \
+ $40 constant AMP1CSR_AMP1IS \
+ $30 constant AMP1CSR_AMP1G \
+ $08 constant AMP1CSR_AMPCMP1 \ Amplifier 1 - Comparator 1 Connection
+ $07 constant AMP1CSR_AMP1TS \
+&119 constant AMP2CSR \
+ $80 constant AMP2CSR_AMP2EN \
+ $40 constant AMP2CSR_AMP2IS \
+ $30 constant AMP2CSR_AMP2G \
+ $08 constant AMP2CSR_AMPCMP2 \ Amplifier 2 - Comparator 2 Connection
+ $07 constant AMP2CSR_AMP2TS \
+\ LINUART
+&200 constant LINCR \ LIN Control Register
+ $80 constant LINCR_LSWRES \ Software Reset
+ $40 constant LINCR_LIN13 \ LIN Standard
+ $30 constant LINCR_LCONF \ LIN Configuration bits
+ $08 constant LINCR_LENA \ LIN or UART Enable
+ $07 constant LINCR_LCMD \ LIN Command and Mode bits
+&201 constant LINSIR \ LIN Status and Interrupt Register
+ $E0 constant LINSIR_LIDST \ Identifier Status bits
+ $10 constant LINSIR_LBUSY \ Busy Signal
+ $08 constant LINSIR_LERR \ Error Interrupt
+ $04 constant LINSIR_LIDOK \ Identifier Interrupt
+ $02 constant LINSIR_LTXOK \ Transmit Performed Interrupt
+ $01 constant LINSIR_LRXOK \ Receive Performed Interrupt
+&202 constant LINENIR \ LIN Enable Interrupt Register
+ $08 constant LINENIR_LENERR \ Enable Error Interrupt
+ $04 constant LINENIR_LENIDOK \ Enable Identifier Interrupt
+ $02 constant LINENIR_LENTXOK \ Enable Transmit Performed Interrupt
+ $01 constant LINENIR_LENRXOK \ Enable Receive Performed Interrupt
+&203 constant LINERR \ LIN Error Register
+ $80 constant LINERR_LABORT \ Abort Flag
+ $40 constant LINERR_LTOERR \ Frame Time Out Error Flag
+ $20 constant LINERR_LOVERR \ Overrun Error Flag
+ $10 constant LINERR_LFERR \ Framing Error Flag
+ $08 constant LINERR_LSERR \ Synchronization Error Flag
+ $04 constant LINERR_LPERR \ Parity Error Flag
+ $02 constant LINERR_LCERR \ Checksum Error Flag
+ $01 constant LINERR_LBERR \ Bit Error Flag
+&204 constant LINBTR \ LIN Bit Timing Register
+ $80 constant LINBTR_LDISR \ Disable Bit Timing Resynchronization
+ $3F constant LINBTR_LBT \ LIN Bit Timing bits
+&205 constant LINBRRL \ LIN Baud Rate Low Register
+ $FF constant LINBRRL_LDIV \
+&206 constant LINBRRH \ LIN Baud Rate High Register
+ $0F constant LINBRRH_LDIV \
+&207 constant LINDLR \ LIN Data Length Register
+ $F0 constant LINDLR_LTXDL \ LIN Transmit Data Length bits
+ $0F constant LINDLR_LRXDL \ LIN Receive Data Length bits
+&208 constant LINIDR \ LIN Identifier Register
+ $C0 constant LINIDR_LP \ Parity bits
+ $3F constant LINIDR_LID \ Identifier bit 5 or Data Length bits
+&209 constant LINSEL \ LIN Data Buffer Selection Register
+ $08 constant LINSEL_LAINC \ Auto Increment of Data Buffer Index (Active Low)
+ $07 constant LINSEL_LINDX \ FIFO LIN Data Buffer Index bits
+&210 constant LINDAT \ LIN Data Register
+ $FF constant LINDAT_LDATA \
+\ SPI
+&76 constant SPCR \ SPI Control Register
+ $80 constant SPCR_SPIE \ SPI Interrupt Enable
+ $40 constant SPCR_SPE \ SPI Enable
+ $20 constant SPCR_DORD \ Data Order
+ $10 constant SPCR_MSTR \ Master/Slave Select
+ $08 constant SPCR_CPOL \ Clock polarity
+ $04 constant SPCR_CPHA \ Clock Phase
+ $03 constant SPCR_SPR \ SPI Clock Rate Selects
+&77 constant SPSR \ SPI Status Register
+ $80 constant SPSR_SPIF \ SPI Interrupt Flag
+ $40 constant SPSR_WCOL \ Write Collision Flag
+ $01 constant SPSR_SPI2X \ Double SPI Speed Bit
+&78 constant SPDR \ SPI Data Register
+\ WATCHDOG
+&96 constant WDTCSR \ Watchdog Timer Control Register
+ $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Flag
+ $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Enable
+ $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
+ $10 constant WDTCSR_WDCE \ Watchdog Change Enable
+ $08 constant WDTCSR_WDE \ Watch Dog Enable
+\ EXTERNAL_INTERRUPT
+&105 constant EICRA \ External Interrupt Control Register
+ $C0 constant EICRA_ISC3 \ External Interrupt Sense Control Bit
+ $30 constant EICRA_ISC2 \ External Interrupt Sense Control Bit
+ $0C constant EICRA_ISC1 \ External Interrupt Sense Control 1 Bits
+ $03 constant EICRA_ISC0 \ External Interrupt Sense Control 0 Bits
+&61 constant EIMSK \ External Interrupt Mask Register
+ $0F constant EIMSK_INT \ External Interrupt Request 3 Enable
+&60 constant EIFR \ External Interrupt Flag Register
+ $0F constant EIFR_INTF \ External Interrupt Flags
+&104 constant PCICR \ Pin Change Interrupt Control Register
+ $0F constant PCICR_PCIE \ Pin Change Interrupt Enables
+&109 constant PCMSK3 \ Pin Change Mask Register 3
+ $07 constant PCMSK3_PCINT \ Pin Change Enable Masks
+&108 constant PCMSK2 \ Pin Change Mask Register 2
+ $FF constant PCMSK2_PCINT \ Pin Change Enable Masks
+&107 constant PCMSK1 \ Pin Change Mask Register 1
+ $FF constant PCMSK1_PCINT \ Pin Change Enable Masks
+&106 constant PCMSK0 \ Pin Change Mask Register 0
+ $FF constant PCMSK0_PCINT \ Pin Change Enable Masks
+&59 constant PCIFR \ Pin Change Interrupt Flag Register
+ $0F constant PCIFR_PCIF \ Pin Change Interrupt Flags
+\ EEPROM
+&65 constant EEAR \ EEPROM Read/Write Access
+&64 constant EEDR \ EEPROM Data Register
+&63 constant EECR \ EEPROM Control Register
+ $30 constant EECR_EEPM \
+ $08 constant EECR_EERIE \ EEProm Ready Interrupt Enable
+ $04 constant EECR_EEMWE \ EEPROM Master Write Enable
+ $02 constant EECR_EEWE \ EEPROM Write Enable
+ $01 constant EECR_EERE \ EEPROM Read Enable
+\ PSC
+&188 constant PIFR \ PSC Interrupt Flag Register
+ $0E constant PIFR_PEV \ PSC External Event 2 Interrupt
+ $01 constant PIFR_PEOP \ PSC End of Cycle Interrupt
+&187 constant PIM \ PSC Interrupt Mask Register
+ $0E constant PIM_PEVE \ External Event 2 Interrupt Enable
+ $01 constant PIM_PEOPE \ PSC End of Cycle Interrupt Enable
+&186 constant PMIC2 \ PSC Module 2 Input Control Register
+ $80 constant PMIC2_POVEN2 \ PSC Module 2 Overlap Enable
+ $40 constant PMIC2_PISEL2 \ PSC Module 2 Input Select
+ $20 constant PMIC2_PELEV2 \ PSC Module 2 Input Level Selector
+ $10 constant PMIC2_PFLTE2 \ PSC Module 2 Input Filter Enable
+ $08 constant PMIC2_PAOC2 \ PSC Module 2 Asynchronous Output Control
+ $07 constant PMIC2_PRFM2 \ PSC Module 2 Input Mode bits
+&185 constant PMIC1 \ PSC Module 1 Input Control Register
+ $80 constant PMIC1_POVEN1 \ PSC Module 1 Overlap Enable
+ $40 constant PMIC1_PISEL1 \ PSC Module 1 Input Select
+ $20 constant PMIC1_PELEV1 \ PSC Module 1 Input Level Selector
+ $10 constant PMIC1_PFLTE1 \ PSC Module 1 Input Filter Enable
+ $08 constant PMIC1_PAOC1 \ PSC Module 1 Asynchronous Output Control
+ $07 constant PMIC1_PRFM1 \ PSC Module 1 Input Mode bits
+&184 constant PMIC0 \ PSC Module 0 Input Control Register
+ $80 constant PMIC0_POVEN0 \ PSC Module 0 Overlap Enable
+ $40 constant PMIC0_PISEL0 \ PSC Module 0 Input Select
+ $20 constant PMIC0_PELEV0 \ PSC Module 0 Input Level Selector
+ $10 constant PMIC0_PFLTE0 \ PSC Module 0 Input Filter Enable
+ $08 constant PMIC0_PAOC0 \ PSC Module 0 Asynchronous Output Control
+ $07 constant PMIC0_PRFM0 \ PSC Module 0 Input Mode bits
+&183 constant PCTL \ PSC Control Register
+ $C0 constant PCTL_PPRE \ PSC Prescaler Select bits
+ $20 constant PCTL_PCLKSEL \ PSC Input Clock Select
+ $02 constant PCTL_PCCYC \ PSC Complete Cycle
+ $01 constant PCTL_PRUN \ PSC Run
+&182 constant POC \ PSC Output Configuration
+ $20 constant POC_POEN2B \ PSC Output 2B Enable
+ $10 constant POC_POEN2A \ PSC Output 2A Enable
+ $08 constant POC_POEN1B \ PSC Output 1B Enable
+ $04 constant POC_POEN1A \ PSC Output 1A Enable
+ $02 constant POC_POEN0B \ PSC Output 0B Enable
+ $01 constant POC_POEN0A \ PSC Output 0A Enable
+&181 constant PCNF \ PSC Configuration Register
+ $20 constant PCNF_PULOCK \ PSC Update Lock
+ $10 constant PCNF_PMODE \ PSC Mode
+ $08 constant PCNF_POPB \ PSC Output B Polarity
+ $04 constant PCNF_POPA \ PSC Output A Polarity
+&180 constant PSYNC \ PSC Synchro Configuration
+ $30 constant PSYNC_PSYNC2 \ Selection of Synchronization Out for ADC
+ $0C constant PSYNC_PSYNC1 \ Selection of Synchronization Out for ADC
+ $03 constant PSYNC_PSYNC0 \ Selection of Synchronization Out for ADC
+&178 constant POCR_RB \ PSC Output Compare RB Register
+&176 constant POCR2SB \ PSC Module 2 Output Compare SB Register
+&174 constant POCR2RA \ PSC Module 2 Output Compare RA Register
+&172 constant POCR2SA \ PSC Module 2 Output Compare SA Register
+&170 constant POCR1SB \ PSC Module 1 Output Compare SB Register
+&168 constant POCR1RA \ PSC Module 1 Output Compare RA Register
+&166 constant POCR1SA \ PSC Output Compare SA Register
+&164 constant POCR0SB \ PSC Output Compare SB Register
+&162 constant POCR0RA \ PSC Module 0 Output Compare RA Register
+&160 constant POCR0SA \ PSC Module 0 Output Compare SA Register
+
+\ Interrupts
+&2 constant ANACOMP0Addr \ Analog Comparator 0
+&4 constant ANACOMP1Addr \ Analog Comparator 1
+&6 constant ANACOMP2Addr \ Analog Comparator 2
+&8 constant ANACOMP3Addr \ Analog Comparator 3
+&10 constant PSC_FAULTAddr \ PSC Fault
+&12 constant PSC_ECAddr \ PSC End of Cycle
+&14 constant INT0Addr \ External Interrupt Request 0
+&16 constant INT1Addr \ External Interrupt Request 1
+&18 constant INT2Addr \ External Interrupt Request 2
+&20 constant INT3Addr \ External Interrupt Request 3
+&22 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+&24 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
+&26 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
+&28 constant TIMER1_OVFAddr \ Timer1/Counter1 Overflow
+&30 constant TIMER0_COMPAAddr \ Timer/Counter0 Compare Match A
+&32 constant TIMER0_COMPBAddr \ Timer/Counter0 Compare Match B
+&34 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
+&36 constant CAN_INTAddr \ CAN MOB, Burst, General Errors
+&38 constant CAN_TOVFAddr \ CAN Timer Overflow
+&40 constant LIN_TCAddr \ LIN Transfer Complete
+&42 constant LIN_ERRAddr \ LIN Error
+&44 constant PCINT0Addr \ Pin Change Interrupt Request 0
+&46 constant PCINT1Addr \ Pin Change Interrupt Request 1
+&48 constant PCINT2Addr \ Pin Change Interrupt Request 2
+&50 constant PCINT3Addr \ Pin Change Interrupt Request 3
+&52 constant SPI__STCAddr \ SPI Serial Transfer Complete
+&54 constant ADCAddr \ ADC Conversion Complete
+&56 constant WDTAddr \ Watchdog Time-Out Interrupt
+&58 constant EE_READYAddr \ EEPROM Ready
+&60 constant SPM_READYAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/atmega64m1/device.asm b/amforth-6.5/avr8/devices/atmega64m1/device.asm
new file mode 100644
index 0000000..7441fc3
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega64m1/device.asm
@@ -0,0 +1,120 @@
+; Partname: ATmega64M1
+; generated automatically, do not edit
+
+.nolist
+ .include "m64M1def.inc"
+.list
+
+.equ ramstart = 256
+.equ CELLSIZE = 2
+.macro readflashcell
+ lsl zl
+ rol zh
+ lpm @0, Z+
+ lpm @1, Z+
+.endmacro
+.macro writeflashcell
+ lsl zl
+ rol zh
+.endmacro
+.set WANT_PORTB = 0
+.set WANT_PORTC = 0
+.set WANT_PORTD = 0
+.set WANT_CAN = 0
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_DA_CONVERTER = 0
+.set WANT_CPU = 0
+.set WANT_PORTE = 0
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_AD_CONVERTER = 0
+.set WANT_LINUART = 0
+.set WANT_SPI = 0
+.set WANT_WATCHDOG = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_EEPROM = 0
+.set WANT_PSC = 0
+.equ intvecsize = 2 ; please verify; flash size: 65536 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.org 2
+ rcall isr ; Analog Comparator 0
+.org 4
+ rcall isr ; Analog Comparator 1
+.org 6
+ rcall isr ; Analog Comparator 2
+.org 8
+ rcall isr ; Analog Comparator 3
+.org 10
+ rcall isr ; PSC Fault
+.org 12
+ rcall isr ; PSC End of Cycle
+.org 14
+ rcall isr ; External Interrupt Request 0
+.org 16
+ rcall isr ; External Interrupt Request 1
+.org 18
+ rcall isr ; External Interrupt Request 2
+.org 20
+ rcall isr ; External Interrupt Request 3
+.org 22
+ rcall isr ; Timer/Counter1 Capture Event
+.org 24
+ rcall isr ; Timer/Counter1 Compare Match A
+.org 26
+ rcall isr ; Timer/Counter1 Compare Match B
+.org 28
+ rcall isr ; Timer1/Counter1 Overflow
+.org 30
+ rcall isr ; Timer/Counter0 Compare Match A
+.org 32
+ rcall isr ; Timer/Counter0 Compare Match B
+.org 34
+ rcall isr ; Timer/Counter0 Overflow
+.org 36
+ rcall isr ; CAN MOB, Burst, General Errors
+.org 38
+ rcall isr ; CAN Timer Overflow
+.org 40
+ rcall isr ; LIN Transfer Complete
+.org 42
+ rcall isr ; LIN Error
+.org 44
+ rcall isr ; Pin Change Interrupt Request 0
+.org 46
+ rcall isr ; Pin Change Interrupt Request 1
+.org 48
+ rcall isr ; Pin Change Interrupt Request 2
+.org 50
+ rcall isr ; Pin Change Interrupt Request 3
+.org 52
+ rcall isr ; SPI Serial Transfer Complete
+.org 54
+ rcall isr ; ADC Conversion Complete
+.org 56
+ rcall isr ; Watchdog Time-Out Interrupt
+.org 58
+ rcall isr ; EEPROM Ready
+.org 60
+ rcall isr ; Store Program Memory Read
+.equ INTVECTORS = 31
+.nooverlap
+
+; compatability layer (maybe empty)
+.equ EEPE = EEWE
+.equ EEMPE = EEMWE
+
+; controller data area, environment query mcu-info
+mcu_info:
+mcu_ramsize:
+ .dw 4096
+mcu_eepromsize:
+ .dw 2048
+mcu_maxdp:
+ .dw 57344
+mcu_numints:
+ .dw 31
+mcu_name:
+ .dw 10
+ .db "ATmega64M1"
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega64m1/device.inc b/amforth-6.5/avr8/devices/atmega64m1/device.inc
new file mode 100644
index 0000000..fa67589
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega64m1/device.inc
@@ -0,0 +1,1734 @@
+; Partname: ATmega64M1
+; generated automatically, no not edit
+
+.if WANT_PORTB == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw 37
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw 36
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw 35
+
+.endif
+.if WANT_PORTC == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Register
+VE_PORTC:
+ .dw $ff05
+ .db "PORTC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTC
+XT_PORTC:
+ .dw PFA_DOVARIABLE
+PFA_PORTC:
+ .dw 40
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Direction Register
+VE_DDRC:
+ .dw $ff04
+ .db "DDRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRC
+XT_DDRC:
+ .dw PFA_DOVARIABLE
+PFA_DDRC:
+ .dw 39
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Input Pins
+VE_PINC:
+ .dw $ff04
+ .db "PINC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINC
+XT_PINC:
+ .dw PFA_DOVARIABLE
+PFA_PINC:
+ .dw 38
+
+.endif
+.if WANT_PORTD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw 43
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw 42
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw 41
+
+.endif
+.if WANT_CAN == 1
+; ( -- addr ) System Constant
+; R( -- )
+; CAN General Control Register
+VE_CANGCON:
+ .dw $ff07
+ .db "CANGCON",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANGCON
+XT_CANGCON:
+ .dw PFA_DOVARIABLE
+PFA_CANGCON:
+ .dw 216
+; ( -- addr ) System Constant
+; R( -- )
+; CAN General Status Register
+VE_CANGSTA:
+ .dw $ff07
+ .db "CANGSTA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANGSTA
+XT_CANGSTA:
+ .dw PFA_DOVARIABLE
+PFA_CANGSTA:
+ .dw 217
+; ( -- addr ) System Constant
+; R( -- )
+; CAN General Interrupt Register Flags
+VE_CANGIT:
+ .dw $ff06
+ .db "CANGIT"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANGIT
+XT_CANGIT:
+ .dw PFA_DOVARIABLE
+PFA_CANGIT:
+ .dw 218
+; ( -- addr ) System Constant
+; R( -- )
+; CAN General Interrupt Enable Register
+VE_CANGIE:
+ .dw $ff06
+ .db "CANGIE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANGIE
+XT_CANGIE:
+ .dw PFA_DOVARIABLE
+PFA_CANGIE:
+ .dw 219
+; ( -- addr ) System Constant
+; R( -- )
+; Enable MOb Register 2
+VE_CANEN2:
+ .dw $ff06
+ .db "CANEN2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANEN2
+XT_CANEN2:
+ .dw PFA_DOVARIABLE
+PFA_CANEN2:
+ .dw 220
+; ( -- addr ) System Constant
+; R( -- )
+; Enable MOb Register 1(empty)
+VE_CANEN1:
+ .dw $ff06
+ .db "CANEN1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANEN1
+XT_CANEN1:
+ .dw PFA_DOVARIABLE
+PFA_CANEN1:
+ .dw 221
+; ( -- addr ) System Constant
+; R( -- )
+; Enable Interrupt MOb Register 2
+VE_CANIE2:
+ .dw $ff06
+ .db "CANIE2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANIE2
+XT_CANIE2:
+ .dw PFA_DOVARIABLE
+PFA_CANIE2:
+ .dw 222
+; ( -- addr ) System Constant
+; R( -- )
+; Enable Interrupt MOb Register 1 (empty)
+VE_CANIE1:
+ .dw $ff06
+ .db "CANIE1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANIE1
+XT_CANIE1:
+ .dw PFA_DOVARIABLE
+PFA_CANIE1:
+ .dw 223
+; ( -- addr ) System Constant
+; R( -- )
+; CAN Status Interrupt MOb Register 2
+VE_CANSIT2:
+ .dw $ff07
+ .db "CANSIT2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANSIT2
+XT_CANSIT2:
+ .dw PFA_DOVARIABLE
+PFA_CANSIT2:
+ .dw 224
+; ( -- addr ) System Constant
+; R( -- )
+; CAN Status Interrupt MOb Register 1 (empty)
+VE_CANSIT1:
+ .dw $ff07
+ .db "CANSIT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANSIT1
+XT_CANSIT1:
+ .dw PFA_DOVARIABLE
+PFA_CANSIT1:
+ .dw 225
+; ( -- addr ) System Constant
+; R( -- )
+; CAN Bit Timing Register 1
+VE_CANBT1:
+ .dw $ff06
+ .db "CANBT1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANBT1
+XT_CANBT1:
+ .dw PFA_DOVARIABLE
+PFA_CANBT1:
+ .dw 226
+; ( -- addr ) System Constant
+; R( -- )
+; CAN Bit Timing Register 2
+VE_CANBT2:
+ .dw $ff06
+ .db "CANBT2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANBT2
+XT_CANBT2:
+ .dw PFA_DOVARIABLE
+PFA_CANBT2:
+ .dw 227
+; ( -- addr ) System Constant
+; R( -- )
+; CAN Bit Timing Register 3
+VE_CANBT3:
+ .dw $ff06
+ .db "CANBT3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANBT3
+XT_CANBT3:
+ .dw PFA_DOVARIABLE
+PFA_CANBT3:
+ .dw 228
+; ( -- addr ) System Constant
+; R( -- )
+; Timer Control Register
+VE_CANTCON:
+ .dw $ff07
+ .db "CANTCON",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANTCON
+XT_CANTCON:
+ .dw PFA_DOVARIABLE
+PFA_CANTCON:
+ .dw 229
+; ( -- addr ) System Constant
+; R( -- )
+; Timer Register Low
+VE_CANTIML:
+ .dw $ff07
+ .db "CANTIML",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANTIML
+XT_CANTIML:
+ .dw PFA_DOVARIABLE
+PFA_CANTIML:
+ .dw 230
+; ( -- addr ) System Constant
+; R( -- )
+; Timer Register High
+VE_CANTIMH:
+ .dw $ff07
+ .db "CANTIMH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANTIMH
+XT_CANTIMH:
+ .dw PFA_DOVARIABLE
+PFA_CANTIMH:
+ .dw 231
+; ( -- addr ) System Constant
+; R( -- )
+; TTC Timer Register Low
+VE_CANTTCL:
+ .dw $ff07
+ .db "CANTTCL",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANTTCL
+XT_CANTTCL:
+ .dw PFA_DOVARIABLE
+PFA_CANTTCL:
+ .dw 232
+; ( -- addr ) System Constant
+; R( -- )
+; TTC Timer Register High
+VE_CANTTCH:
+ .dw $ff07
+ .db "CANTTCH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANTTCH
+XT_CANTTCH:
+ .dw PFA_DOVARIABLE
+PFA_CANTTCH:
+ .dw 233
+; ( -- addr ) System Constant
+; R( -- )
+; Transmit Error Counter Register
+VE_CANTEC:
+ .dw $ff06
+ .db "CANTEC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANTEC
+XT_CANTEC:
+ .dw PFA_DOVARIABLE
+PFA_CANTEC:
+ .dw 234
+; ( -- addr ) System Constant
+; R( -- )
+; Receive Error Counter Register
+VE_CANREC:
+ .dw $ff06
+ .db "CANREC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANREC
+XT_CANREC:
+ .dw PFA_DOVARIABLE
+PFA_CANREC:
+ .dw 235
+; ( -- addr ) System Constant
+; R( -- )
+; Highest Priority MOb Register
+VE_CANHPMOB:
+ .dw $ff08
+ .db "CANHPMOB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANHPMOB
+XT_CANHPMOB:
+ .dw PFA_DOVARIABLE
+PFA_CANHPMOB:
+ .dw 236
+; ( -- addr ) System Constant
+; R( -- )
+; Page MOb Register
+VE_CANPAGE:
+ .dw $ff07
+ .db "CANPAGE",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANPAGE
+XT_CANPAGE:
+ .dw PFA_DOVARIABLE
+PFA_CANPAGE:
+ .dw 237
+; ( -- addr ) System Constant
+; R( -- )
+; MOb Status Register
+VE_CANSTMOB:
+ .dw $ff08
+ .db "CANSTMOB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANSTMOB
+XT_CANSTMOB:
+ .dw PFA_DOVARIABLE
+PFA_CANSTMOB:
+ .dw 238
+; ( -- addr ) System Constant
+; R( -- )
+; MOb Control and DLC Register
+VE_CANCDMOB:
+ .dw $ff08
+ .db "CANCDMOB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANCDMOB
+XT_CANCDMOB:
+ .dw PFA_DOVARIABLE
+PFA_CANCDMOB:
+ .dw 239
+; ( -- addr ) System Constant
+; R( -- )
+; Identifier Tag Register 4
+VE_CANIDT4:
+ .dw $ff07
+ .db "CANIDT4",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANIDT4
+XT_CANIDT4:
+ .dw PFA_DOVARIABLE
+PFA_CANIDT4:
+ .dw 240
+; ( -- addr ) System Constant
+; R( -- )
+; Identifier Tag Register 3
+VE_CANIDT3:
+ .dw $ff07
+ .db "CANIDT3",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANIDT3
+XT_CANIDT3:
+ .dw PFA_DOVARIABLE
+PFA_CANIDT3:
+ .dw 241
+; ( -- addr ) System Constant
+; R( -- )
+; Identifier Tag Register 2
+VE_CANIDT2:
+ .dw $ff07
+ .db "CANIDT2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANIDT2
+XT_CANIDT2:
+ .dw PFA_DOVARIABLE
+PFA_CANIDT2:
+ .dw 242
+; ( -- addr ) System Constant
+; R( -- )
+; Identifier Tag Register 1
+VE_CANIDT1:
+ .dw $ff07
+ .db "CANIDT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANIDT1
+XT_CANIDT1:
+ .dw PFA_DOVARIABLE
+PFA_CANIDT1:
+ .dw 243
+; ( -- addr ) System Constant
+; R( -- )
+; Identifier Mask Register 4
+VE_CANIDM4:
+ .dw $ff07
+ .db "CANIDM4",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANIDM4
+XT_CANIDM4:
+ .dw PFA_DOVARIABLE
+PFA_CANIDM4:
+ .dw 244
+; ( -- addr ) System Constant
+; R( -- )
+; Identifier Mask Register 3
+VE_CANIDM3:
+ .dw $ff07
+ .db "CANIDM3",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANIDM3
+XT_CANIDM3:
+ .dw PFA_DOVARIABLE
+PFA_CANIDM3:
+ .dw 245
+; ( -- addr ) System Constant
+; R( -- )
+; Identifier Mask Register 2
+VE_CANIDM2:
+ .dw $ff07
+ .db "CANIDM2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANIDM2
+XT_CANIDM2:
+ .dw PFA_DOVARIABLE
+PFA_CANIDM2:
+ .dw 246
+; ( -- addr ) System Constant
+; R( -- )
+; Identifier Mask Register 1
+VE_CANIDM1:
+ .dw $ff07
+ .db "CANIDM1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANIDM1
+XT_CANIDM1:
+ .dw PFA_DOVARIABLE
+PFA_CANIDM1:
+ .dw 247
+; ( -- addr ) System Constant
+; R( -- )
+; Time Stamp Register Low
+VE_CANSTML:
+ .dw $ff07
+ .db "CANSTML",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANSTML
+XT_CANSTML:
+ .dw PFA_DOVARIABLE
+PFA_CANSTML:
+ .dw 248
+; ( -- addr ) System Constant
+; R( -- )
+; Time Stamp Register High
+VE_CANSTMH:
+ .dw $ff07
+ .db "CANSTMH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANSTMH
+XT_CANSTMH:
+ .dw PFA_DOVARIABLE
+PFA_CANSTMH:
+ .dw 249
+; ( -- addr ) System Constant
+; R( -- )
+; Message Data Register
+VE_CANMSG:
+ .dw $ff06
+ .db "CANMSG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANMSG
+XT_CANMSG:
+ .dw PFA_DOVARIABLE
+PFA_CANMSG:
+ .dw 250
+
+.endif
+.if WANT_ANALOG_COMPARATOR == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator 0 Control Register
+VE_AC0CON:
+ .dw $ff06
+ .db "AC0CON"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_AC0CON
+XT_AC0CON:
+ .dw PFA_DOVARIABLE
+PFA_AC0CON:
+ .dw 148
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator 1 Control Register
+VE_AC1CON:
+ .dw $ff06
+ .db "AC1CON"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_AC1CON
+XT_AC1CON:
+ .dw PFA_DOVARIABLE
+PFA_AC1CON:
+ .dw 149
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator 2 Control Register
+VE_AC2CON:
+ .dw $ff06
+ .db "AC2CON"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_AC2CON
+XT_AC2CON:
+ .dw PFA_DOVARIABLE
+PFA_AC2CON:
+ .dw 150
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator 3 Control Register
+VE_AC3CON:
+ .dw $ff06
+ .db "AC3CON"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_AC3CON
+XT_AC3CON:
+ .dw PFA_DOVARIABLE
+PFA_AC3CON:
+ .dw 151
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw 80
+
+.endif
+.if WANT_DA_CONVERTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; DAC Data Register High Byte
+VE_DACH:
+ .dw $ff04
+ .db "DACH"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DACH
+XT_DACH:
+ .dw PFA_DOVARIABLE
+PFA_DACH:
+ .dw 146
+; ( -- addr ) System Constant
+; R( -- )
+; DAC Data Register Low Byte
+VE_DACL:
+ .dw $ff04
+ .db "DACL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DACL
+XT_DACL:
+ .dw PFA_DOVARIABLE
+PFA_DACL:
+ .dw 145
+; ( -- addr ) System Constant
+; R( -- )
+; DAC Control Register
+VE_DACON:
+ .dw $ff05
+ .db "DACON",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DACON
+XT_DACON:
+ .dw PFA_DOVARIABLE
+PFA_DACON:
+ .dw 144
+
+.endif
+.if WANT_CPU == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control Register
+VE_SPMCSR:
+ .dw $ff06
+ .db "SPMCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCSR
+XT_SPMCSR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCSR:
+ .dw 87
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw 95
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer
+VE_SP:
+ .dw $ff02
+ .db "SP"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SP
+XT_SP:
+ .dw PFA_DOVARIABLE
+PFA_SP:
+ .dw 93
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw 85
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Status Register
+VE_MCUSR:
+ .dw $ff05
+ .db "MCUSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUSR
+XT_MCUSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUSR:
+ .dw 84
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Calibration Value
+VE_OSCCAL:
+ .dw $ff06
+ .db "OSCCAL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSCCAL
+XT_OSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_OSCCAL:
+ .dw 102
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_CLKPR:
+ .dw $ff05
+ .db "CLKPR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKPR
+XT_CLKPR:
+ .dw PFA_DOVARIABLE
+PFA_CLKPR:
+ .dw 97
+; ( -- addr ) System Constant
+; R( -- )
+; Sleep Mode Control Register
+VE_SMCR:
+ .dw $ff04
+ .db "SMCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SMCR
+XT_SMCR:
+ .dw PFA_DOVARIABLE
+PFA_SMCR:
+ .dw 83
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 2
+VE_GPIOR2:
+ .dw $ff06
+ .db "GPIOR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR2
+XT_GPIOR2:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR2:
+ .dw 58
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 1
+VE_GPIOR1:
+ .dw $ff06
+ .db "GPIOR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR1
+XT_GPIOR1:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR1:
+ .dw 57
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 0
+VE_GPIOR0:
+ .dw $ff06
+ .db "GPIOR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR0
+XT_GPIOR0:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR0:
+ .dw 62
+; ( -- addr ) System Constant
+; R( -- )
+; PLL Control And Status Register
+VE_PLLCSR:
+ .dw $ff06
+ .db "PLLCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PLLCSR
+XT_PLLCSR:
+ .dw PFA_DOVARIABLE
+PFA_PLLCSR:
+ .dw 73
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register
+VE_PRR:
+ .dw $ff03
+ .db "PRR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR
+XT_PRR:
+ .dw PFA_DOVARIABLE
+PFA_PRR:
+ .dw 100
+
+.endif
+.if WANT_PORTE == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port E Data Register
+VE_PORTE:
+ .dw $ff05
+ .db "PORTE",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTE
+XT_PORTE:
+ .dw PFA_DOVARIABLE
+PFA_PORTE:
+ .dw 46
+; ( -- addr ) System Constant
+; R( -- )
+; Port E Data Direction Register
+VE_DDRE:
+ .dw $ff04
+ .db "DDRE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRE
+XT_DDRE:
+ .dw PFA_DOVARIABLE
+PFA_DDRE:
+ .dw 45
+; ( -- addr ) System Constant
+; R( -- )
+; Port E Input Pins
+VE_PINE:
+ .dw $ff04
+ .db "PINE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINE
+XT_PINE:
+ .dw PFA_DOVARIABLE
+PFA_PINE:
+ .dw 44
+
+.endif
+.if WANT_TIMER_COUNTER_0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Mask Register
+VE_TIMSK0:
+ .dw $ff06
+ .db "TIMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK0
+XT_TIMSK0:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK0:
+ .dw 110
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Flag register
+VE_TIFR0:
+ .dw $ff05
+ .db "TIFR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR0
+XT_TIFR0:
+ .dw PFA_DOVARIABLE
+PFA_TIFR0:
+ .dw 53
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register A
+VE_TCCR0A:
+ .dw $ff06
+ .db "TCCR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0A
+XT_TCCR0A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0A:
+ .dw 68
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register B
+VE_TCCR0B:
+ .dw $ff06
+ .db "TCCR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0B
+XT_TCCR0B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0B:
+ .dw 69
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw 70
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0A:
+ .dw $ff05
+ .db "OCR0A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0A
+XT_OCR0A:
+ .dw PFA_DOVARIABLE
+PFA_OCR0A:
+ .dw 71
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0B:
+ .dw $ff05
+ .db "OCR0B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0B
+XT_OCR0B:
+ .dw PFA_DOVARIABLE
+PFA_OCR0B:
+ .dw 72
+; ( -- addr ) System Constant
+; R( -- )
+; General Timer/Counter Control Register
+VE_GTCCR:
+ .dw $ff05
+ .db "GTCCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GTCCR
+XT_GTCCR:
+ .dw PFA_DOVARIABLE
+PFA_GTCCR:
+ .dw 67
+
+.endif
+.if WANT_TIMER_COUNTER_1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Mask Register
+VE_TIMSK1:
+ .dw $ff06
+ .db "TIMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK1
+XT_TIMSK1:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK1:
+ .dw 111
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Flag register
+VE_TIFR1:
+ .dw $ff05
+ .db "TIFR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR1
+XT_TIFR1:
+ .dw PFA_DOVARIABLE
+PFA_TIFR1:
+ .dw 54
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw 128
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw 129
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register C
+VE_TCCR1C:
+ .dw $ff06
+ .db "TCCR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1C
+XT_TCCR1C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1C:
+ .dw 130
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Bytes
+VE_TCNT1:
+ .dw $ff05
+ .db "TCNT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1
+XT_TCNT1:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1:
+ .dw 132
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register Bytes
+VE_OCR1A:
+ .dw $ff05
+ .db "OCR1A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1A
+XT_OCR1A:
+ .dw PFA_DOVARIABLE
+PFA_OCR1A:
+ .dw 136
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register Bytes
+VE_OCR1B:
+ .dw $ff05
+ .db "OCR1B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1B
+XT_OCR1B:
+ .dw PFA_DOVARIABLE
+PFA_OCR1B:
+ .dw 138
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Bytes
+VE_ICR1:
+ .dw $ff04
+ .db "ICR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1
+XT_ICR1:
+ .dw PFA_DOVARIABLE
+PFA_ICR1:
+ .dw 134
+
+.endif
+.if WANT_AD_CONVERTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC multiplexer Selection Register
+VE_ADMUX:
+ .dw $ff05
+ .db "ADMUX",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADMUX
+XT_ADMUX:
+ .dw PFA_DOVARIABLE
+PFA_ADMUX:
+ .dw 124
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register
+VE_ADCSRA:
+ .dw $ff06
+ .db "ADCSRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRA
+XT_ADCSRA:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRA:
+ .dw 122
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register Bytes
+VE_ADC:
+ .dw $ff03
+ .db "ADC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADC
+XT_ADC:
+ .dw PFA_DOVARIABLE
+PFA_ADC:
+ .dw 120
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Control and Status Register B
+VE_ADCSRB:
+ .dw $ff06
+ .db "ADCSRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRB
+XT_ADCSRB:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRB:
+ .dw 123
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 0
+VE_DIDR0:
+ .dw $ff05
+ .db "DIDR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR0
+XT_DIDR0:
+ .dw PFA_DOVARIABLE
+PFA_DIDR0:
+ .dw 126
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 0
+VE_DIDR1:
+ .dw $ff05
+ .db "DIDR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR1
+XT_DIDR1:
+ .dw PFA_DOVARIABLE
+PFA_DIDR1:
+ .dw 127
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_AMP0CSR:
+ .dw $ff07
+ .db "AMP0CSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_AMP0CSR
+XT_AMP0CSR:
+ .dw PFA_DOVARIABLE
+PFA_AMP0CSR:
+ .dw 117
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_AMP1CSR:
+ .dw $ff07
+ .db "AMP1CSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_AMP1CSR
+XT_AMP1CSR:
+ .dw PFA_DOVARIABLE
+PFA_AMP1CSR:
+ .dw 118
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_AMP2CSR:
+ .dw $ff07
+ .db "AMP2CSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_AMP2CSR
+XT_AMP2CSR:
+ .dw PFA_DOVARIABLE
+PFA_AMP2CSR:
+ .dw 119
+
+.endif
+.if WANT_LINUART == 1
+; ( -- addr ) System Constant
+; R( -- )
+; LIN Control Register
+VE_LINCR:
+ .dw $ff05
+ .db "LINCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LINCR
+XT_LINCR:
+ .dw PFA_DOVARIABLE
+PFA_LINCR:
+ .dw 200
+; ( -- addr ) System Constant
+; R( -- )
+; LIN Status and Interrupt Register
+VE_LINSIR:
+ .dw $ff06
+ .db "LINSIR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LINSIR
+XT_LINSIR:
+ .dw PFA_DOVARIABLE
+PFA_LINSIR:
+ .dw 201
+; ( -- addr ) System Constant
+; R( -- )
+; LIN Enable Interrupt Register
+VE_LINENIR:
+ .dw $ff07
+ .db "LINENIR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LINENIR
+XT_LINENIR:
+ .dw PFA_DOVARIABLE
+PFA_LINENIR:
+ .dw 202
+; ( -- addr ) System Constant
+; R( -- )
+; LIN Error Register
+VE_LINERR:
+ .dw $ff06
+ .db "LINERR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LINERR
+XT_LINERR:
+ .dw PFA_DOVARIABLE
+PFA_LINERR:
+ .dw 203
+; ( -- addr ) System Constant
+; R( -- )
+; LIN Bit Timing Register
+VE_LINBTR:
+ .dw $ff06
+ .db "LINBTR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LINBTR
+XT_LINBTR:
+ .dw PFA_DOVARIABLE
+PFA_LINBTR:
+ .dw 204
+; ( -- addr ) System Constant
+; R( -- )
+; LIN Baud Rate Low Register
+VE_LINBRRL:
+ .dw $ff07
+ .db "LINBRRL",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LINBRRL
+XT_LINBRRL:
+ .dw PFA_DOVARIABLE
+PFA_LINBRRL:
+ .dw 205
+; ( -- addr ) System Constant
+; R( -- )
+; LIN Baud Rate High Register
+VE_LINBRRH:
+ .dw $ff07
+ .db "LINBRRH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LINBRRH
+XT_LINBRRH:
+ .dw PFA_DOVARIABLE
+PFA_LINBRRH:
+ .dw 206
+; ( -- addr ) System Constant
+; R( -- )
+; LIN Data Length Register
+VE_LINDLR:
+ .dw $ff06
+ .db "LINDLR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LINDLR
+XT_LINDLR:
+ .dw PFA_DOVARIABLE
+PFA_LINDLR:
+ .dw 207
+; ( -- addr ) System Constant
+; R( -- )
+; LIN Identifier Register
+VE_LINIDR:
+ .dw $ff06
+ .db "LINIDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LINIDR
+XT_LINIDR:
+ .dw PFA_DOVARIABLE
+PFA_LINIDR:
+ .dw 208
+; ( -- addr ) System Constant
+; R( -- )
+; LIN Data Buffer Selection Register
+VE_LINSEL:
+ .dw $ff06
+ .db "LINSEL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LINSEL
+XT_LINSEL:
+ .dw PFA_DOVARIABLE
+PFA_LINSEL:
+ .dw 209
+; ( -- addr ) System Constant
+; R( -- )
+; LIN Data Register
+VE_LINDAT:
+ .dw $ff06
+ .db "LINDAT"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LINDAT
+XT_LINDAT:
+ .dw PFA_DOVARIABLE
+PFA_LINDAT:
+ .dw 210
+
+.endif
+.if WANT_SPI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR:
+ .dw $ff04
+ .db "SPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR
+XT_SPCR:
+ .dw PFA_DOVARIABLE
+PFA_SPCR:
+ .dw 76
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR:
+ .dw $ff04
+ .db "SPSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR
+XT_SPSR:
+ .dw PFA_DOVARIABLE
+PFA_SPSR:
+ .dw 77
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR:
+ .dw $ff04
+ .db "SPDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR
+XT_SPDR:
+ .dw PFA_DOVARIABLE
+PFA_SPDR:
+ .dw 78
+
+.endif
+.if WANT_WATCHDOG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCSR:
+ .dw $ff06
+ .db "WDTCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCSR
+XT_WDTCSR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCSR:
+ .dw 96
+
+.endif
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register
+VE_EICRA:
+ .dw $ff05
+ .db "EICRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRA
+XT_EICRA:
+ .dw PFA_DOVARIABLE
+PFA_EICRA:
+ .dw 105
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Mask Register
+VE_EIMSK:
+ .dw $ff05
+ .db "EIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIMSK
+XT_EIMSK:
+ .dw PFA_DOVARIABLE
+PFA_EIMSK:
+ .dw 61
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Flag Register
+VE_EIFR:
+ .dw $ff04
+ .db "EIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIFR
+XT_EIFR:
+ .dw PFA_DOVARIABLE
+PFA_EIFR:
+ .dw 60
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Interrupt Control Register
+VE_PCICR:
+ .dw $ff05
+ .db "PCICR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCICR
+XT_PCICR:
+ .dw PFA_DOVARIABLE
+PFA_PCICR:
+ .dw 104
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 3
+VE_PCMSK3:
+ .dw $ff06
+ .db "PCMSK3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK3
+XT_PCMSK3:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK3:
+ .dw 109
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 2
+VE_PCMSK2:
+ .dw $ff06
+ .db "PCMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK2
+XT_PCMSK2:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK2:
+ .dw 108
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 1
+VE_PCMSK1:
+ .dw $ff06
+ .db "PCMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK1
+XT_PCMSK1:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK1:
+ .dw 107
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 0
+VE_PCMSK0:
+ .dw $ff06
+ .db "PCMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK0
+XT_PCMSK0:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK0:
+ .dw 106
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Interrupt Flag Register
+VE_PCIFR:
+ .dw $ff05
+ .db "PCIFR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCIFR
+XT_PCIFR:
+ .dw PFA_DOVARIABLE
+PFA_PCIFR:
+ .dw 59
+
+.endif
+.if WANT_EEPROM == 1
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Read/Write Access
+VE_EEAR:
+ .dw $ff04
+ .db "EEAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEAR
+XT_EEAR:
+ .dw PFA_DOVARIABLE
+PFA_EEAR:
+ .dw 65
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw 64
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw 63
+
+.endif
+.if WANT_PSC == 1
+; ( -- addr ) System Constant
+; R( -- )
+; PSC Interrupt Flag Register
+VE_PIFR:
+ .dw $ff04
+ .db "PIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIFR
+XT_PIFR:
+ .dw PFA_DOVARIABLE
+PFA_PIFR:
+ .dw 188
+; ( -- addr ) System Constant
+; R( -- )
+; PSC Interrupt Mask Register
+VE_PIM:
+ .dw $ff03
+ .db "PIM",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIM
+XT_PIM:
+ .dw PFA_DOVARIABLE
+PFA_PIM:
+ .dw 187
+; ( -- addr ) System Constant
+; R( -- )
+; PSC Module 2 Input Control Register
+VE_PMIC2:
+ .dw $ff05
+ .db "PMIC2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PMIC2
+XT_PMIC2:
+ .dw PFA_DOVARIABLE
+PFA_PMIC2:
+ .dw 186
+; ( -- addr ) System Constant
+; R( -- )
+; PSC Module 1 Input Control Register
+VE_PMIC1:
+ .dw $ff05
+ .db "PMIC1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PMIC1
+XT_PMIC1:
+ .dw PFA_DOVARIABLE
+PFA_PMIC1:
+ .dw 185
+; ( -- addr ) System Constant
+; R( -- )
+; PSC Module 0 Input Control Register
+VE_PMIC0:
+ .dw $ff05
+ .db "PMIC0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PMIC0
+XT_PMIC0:
+ .dw PFA_DOVARIABLE
+PFA_PMIC0:
+ .dw 184
+; ( -- addr ) System Constant
+; R( -- )
+; PSC Control Register
+VE_PCTL:
+ .dw $ff04
+ .db "PCTL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCTL
+XT_PCTL:
+ .dw PFA_DOVARIABLE
+PFA_PCTL:
+ .dw 183
+; ( -- addr ) System Constant
+; R( -- )
+; PSC Output Configuration
+VE_POC:
+ .dw $ff03
+ .db "POC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_POC
+XT_POC:
+ .dw PFA_DOVARIABLE
+PFA_POC:
+ .dw 182
+; ( -- addr ) System Constant
+; R( -- )
+; PSC Configuration Register
+VE_PCNF:
+ .dw $ff04
+ .db "PCNF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCNF
+XT_PCNF:
+ .dw PFA_DOVARIABLE
+PFA_PCNF:
+ .dw 181
+; ( -- addr ) System Constant
+; R( -- )
+; PSC Synchro Configuration
+VE_PSYNC:
+ .dw $ff05
+ .db "PSYNC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PSYNC
+XT_PSYNC:
+ .dw PFA_DOVARIABLE
+PFA_PSYNC:
+ .dw 180
+; ( -- addr ) System Constant
+; R( -- )
+; PSC Output Compare RB Register
+VE_POCR_RB:
+ .dw $ff07
+ .db "POCR_RB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_POCR_RB
+XT_POCR_RB:
+ .dw PFA_DOVARIABLE
+PFA_POCR_RB:
+ .dw 178
+; ( -- addr ) System Constant
+; R( -- )
+; PSC Module 2 Output Compare SB Register
+VE_POCR2SB:
+ .dw $ff07
+ .db "POCR2SB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_POCR2SB
+XT_POCR2SB:
+ .dw PFA_DOVARIABLE
+PFA_POCR2SB:
+ .dw 176
+; ( -- addr ) System Constant
+; R( -- )
+; PSC Module 2 Output Compare RA Register
+VE_POCR2RA:
+ .dw $ff07
+ .db "POCR2RA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_POCR2RA
+XT_POCR2RA:
+ .dw PFA_DOVARIABLE
+PFA_POCR2RA:
+ .dw 174
+; ( -- addr ) System Constant
+; R( -- )
+; PSC Module 2 Output Compare SA Register
+VE_POCR2SA:
+ .dw $ff07
+ .db "POCR2SA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_POCR2SA
+XT_POCR2SA:
+ .dw PFA_DOVARIABLE
+PFA_POCR2SA:
+ .dw 172
+; ( -- addr ) System Constant
+; R( -- )
+; PSC Module 1 Output Compare SB Register
+VE_POCR1SB:
+ .dw $ff07
+ .db "POCR1SB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_POCR1SB
+XT_POCR1SB:
+ .dw PFA_DOVARIABLE
+PFA_POCR1SB:
+ .dw 170
+; ( -- addr ) System Constant
+; R( -- )
+; PSC Module 1 Output Compare RA Register
+VE_POCR1RA:
+ .dw $ff07
+ .db "POCR1RA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_POCR1RA
+XT_POCR1RA:
+ .dw PFA_DOVARIABLE
+PFA_POCR1RA:
+ .dw 168
+; ( -- addr ) System Constant
+; R( -- )
+; PSC Output Compare SA Register
+VE_POCR1SA:
+ .dw $ff07
+ .db "POCR1SA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_POCR1SA
+XT_POCR1SA:
+ .dw PFA_DOVARIABLE
+PFA_POCR1SA:
+ .dw 166
+; ( -- addr ) System Constant
+; R( -- )
+; PSC Output Compare SB Register
+VE_POCR0SB:
+ .dw $ff07
+ .db "POCR0SB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_POCR0SB
+XT_POCR0SB:
+ .dw PFA_DOVARIABLE
+PFA_POCR0SB:
+ .dw 164
+; ( -- addr ) System Constant
+; R( -- )
+; PSC Module 0 Output Compare RA Register
+VE_POCR0RA:
+ .dw $ff07
+ .db "POCR0RA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_POCR0RA
+XT_POCR0RA:
+ .dw PFA_DOVARIABLE
+PFA_POCR0RA:
+ .dw 162
+; ( -- addr ) System Constant
+; R( -- )
+; PSC Module 0 Output Compare SA Register
+VE_POCR0SA:
+ .dw $ff07
+ .db "POCR0SA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_POCR0SA
+XT_POCR0SA:
+ .dw PFA_DOVARIABLE
+PFA_POCR0SA:
+ .dw 160
+
+.endif
diff --git a/amforth-6.5/avr8/devices/atmega64m1/device.py b/amforth-6.5/avr8/devices/atmega64m1/device.py
new file mode 100644
index 0000000..c6482be
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega64m1/device.py
@@ -0,0 +1,495 @@
+# Partname: ATmega64M1
+# generated automatically, do not edit
+MCUREGS = {
+ 'PORTB': '&37',
+ 'DDRB': '&36',
+ 'PINB': '&35',
+ 'PORTC': '&40',
+ 'DDRC': '&39',
+ 'PINC': '&38',
+ 'PORTD': '&43',
+ 'DDRD': '&42',
+ 'PIND': '&41',
+ 'CANGCON': '&216',
+ 'CANGCON_ABRQ': '$80',
+ 'CANGCON_OVRQ': '$40',
+ 'CANGCON_TTC': '$20',
+ 'CANGCON_SYNTTC': '$10',
+ 'CANGCON_LISTEN': '$08',
+ 'CANGCON_TEST': '$04',
+ 'CANGCON_ENASTB': '$02',
+ 'CANGCON_SWRES': '$01',
+ 'CANGSTA': '&217',
+ 'CANGSTA_OVFG': '$40',
+ 'CANGSTA_TXBSY': '$10',
+ 'CANGSTA_RXBSY': '$08',
+ 'CANGSTA_ENFG': '$04',
+ 'CANGSTA_BOFF': '$02',
+ 'CANGSTA_ERRP': '$01',
+ 'CANGIT': '&218',
+ 'CANGIT_CANIT': '$80',
+ 'CANGIT_BOFFIT': '$40',
+ 'CANGIT_OVRTIM': '$20',
+ 'CANGIT_BXOK': '$10',
+ 'CANGIT_SERG': '$08',
+ 'CANGIT_CERG': '$04',
+ 'CANGIT_FERG': '$02',
+ 'CANGIT_AERG': '$01',
+ 'CANGIE': '&219',
+ 'CANGIE_ENIT': '$80',
+ 'CANGIE_ENBOFF': '$40',
+ 'CANGIE_ENRX': '$20',
+ 'CANGIE_ENTX': '$10',
+ 'CANGIE_ENERR': '$08',
+ 'CANGIE_ENBX': '$04',
+ 'CANGIE_ENERG': '$02',
+ 'CANGIE_ENOVRT': '$01',
+ 'CANEN2': '&220',
+ 'CANEN2_ENMOB': '$3F',
+ 'CANEN1': '&221',
+ 'CANIE2': '&222',
+ 'CANIE2_IEMOB': '$3F',
+ 'CANIE1': '&223',
+ 'CANSIT2': '&224',
+ 'CANSIT2_SIT': '$3F',
+ 'CANSIT1': '&225',
+ 'CANBT1': '&226',
+ 'CANBT1_BRP': '$7E',
+ 'CANBT2': '&227',
+ 'CANBT2_SJW': '$60',
+ 'CANBT2_PRS': '$0E',
+ 'CANBT3': '&228',
+ 'CANBT3_PHS2': '$70',
+ 'CANBT3_PHS1': '$0E',
+ 'CANBT3_SMP': '$01',
+ 'CANTCON': '&229',
+ 'CANTIML': '&230',
+ 'CANTIMH': '&231',
+ 'CANTTCL': '&232',
+ 'CANTTCH': '&233',
+ 'CANTEC': '&234',
+ 'CANREC': '&235',
+ 'CANHPMOB': '&236',
+ 'CANHPMOB_HPMOB': '$F0',
+ 'CANHPMOB_CGP': '$0F',
+ 'CANPAGE': '&237',
+ 'CANPAGE_MOBNB': '$F0',
+ 'CANPAGE_AINC': '$08',
+ 'CANPAGE_INDX': '$07',
+ 'CANSTMOB': '&238',
+ 'CANSTMOB_DLCW': '$80',
+ 'CANSTMOB_TXOK': '$40',
+ 'CANSTMOB_RXOK': '$20',
+ 'CANSTMOB_BERR': '$10',
+ 'CANSTMOB_SERR': '$08',
+ 'CANSTMOB_CERR': '$04',
+ 'CANSTMOB_FERR': '$02',
+ 'CANSTMOB_AERR': '$01',
+ 'CANCDMOB': '&239',
+ 'CANCDMOB_CONMOB': '$C0',
+ 'CANCDMOB_RPLV': '$20',
+ 'CANCDMOB_IDE': '$10',
+ 'CANCDMOB_DLC': '$0F',
+ 'CANIDT4': '&240',
+ 'CANIDT4_IDT': '$F8',
+ 'CANIDT4_RTRTAG': '$04',
+ 'CANIDT4_RB1TAG': '$02',
+ 'CANIDT4_RB0TAG': '$01',
+ 'CANIDT3': '&241',
+ 'CANIDT2': '&242',
+ 'CANIDT1': '&243',
+ 'CANIDM4': '&244',
+ 'CANIDM3': '&245',
+ 'CANIDM2': '&246',
+ 'CANIDM1': '&247',
+ 'CANSTML': '&248',
+ 'CANSTMH': '&249',
+ 'CANMSG': '&250',
+ 'AC0CON': '&148',
+ 'AC0CON_AC0EN': '$80',
+ 'AC0CON_AC0IE': '$40',
+ 'AC0CON_AC0IS': '$30',
+ 'AC0CON_ACCKSEL': '$08',
+ 'AC0CON_AC0M': '$07',
+ 'AC1CON': '&149',
+ 'AC1CON_AC1EN': '$80',
+ 'AC1CON_AC1IE': '$40',
+ 'AC1CON_AC1IS': '$30',
+ 'AC1CON_AC1ICE': '$08',
+ 'AC1CON_AC1M': '$07',
+ 'AC2CON': '&150',
+ 'AC2CON_AC2EN': '$80',
+ 'AC2CON_AC2IE': '$40',
+ 'AC2CON_AC2IS': '$30',
+ 'AC2CON_AC2M': '$07',
+ 'AC3CON': '&151',
+ 'AC3CON_AC3EN': '$80',
+ 'AC3CON_AC3IE': '$40',
+ 'AC3CON_AC3IS': '$30',
+ 'AC3CON_AC3M': '$07',
+ 'ACSR': '&80',
+ 'ACSR_AC3IF': '$80',
+ 'ACSR_AC2IF': '$40',
+ 'ACSR_AC1IF': '$20',
+ 'ACSR_AC0IF': '$10',
+ 'ACSR_AC3O': '$08',
+ 'ACSR_AC2O': '$04',
+ 'ACSR_AC1O': '$02',
+ 'ACSR_AC0O': '$01',
+ 'DACH': '&146',
+ 'DACH_DACH': '$FF',
+ 'DACL': '&145',
+ 'DACL_DACL': '$FF',
+ 'DACON': '&144',
+ 'DACON_DAATE': '$80',
+ 'DACON_DATS': '$70',
+ 'DACON_DALA': '$04',
+ 'DACON_DAEN': '$01',
+ 'SPMCSR': '&87',
+ 'SPMCSR_SPMIE': '$80',
+ 'SPMCSR_RWWSB': '$40',
+ 'SPMCSR_SIGRD': '$20',
+ 'SPMCSR_RWWSRE': '$10',
+ 'SPMCSR_BLBSET': '$08',
+ 'SPMCSR_PGWRT': '$04',
+ 'SPMCSR_PGERS': '$02',
+ 'SPMCSR_SPMEN': '$01',
+ 'SREG': '&95',
+ 'SREG_I': '$80',
+ 'SREG_T': '$40',
+ 'SREG_H': '$20',
+ 'SREG_S': '$10',
+ 'SREG_V': '$08',
+ 'SREG_N': '$04',
+ 'SREG_Z': '$02',
+ 'SREG_C': '$01',
+ 'SP': '&93',
+ 'MCUCR': '&85',
+ 'MCUCR_SPIPS': '$80',
+ 'MCUCR_PUD': '$10',
+ 'MCUCR_IVSEL': '$02',
+ 'MCUCR_IVCE': '$01',
+ 'MCUSR': '&84',
+ 'MCUSR_WDRF': '$08',
+ 'MCUSR_BORF': '$04',
+ 'MCUSR_EXTRF': '$02',
+ 'MCUSR_PORF': '$01',
+ 'OSCCAL': '&102',
+ 'CLKPR': '&97',
+ 'CLKPR_CLKPCE': '$80',
+ 'CLKPR_CLKPS': '$0F',
+ 'SMCR': '&83',
+ 'SMCR_SM': '$0E',
+ 'SMCR_SE': '$01',
+ 'GPIOR2': '&58',
+ 'GPIOR2_GPIOR': '$FF',
+ 'GPIOR1': '&57',
+ 'GPIOR1_GPIOR': '$FF',
+ 'GPIOR0': '&62',
+ 'GPIOR0_GPIOR07': '$80',
+ 'GPIOR0_GPIOR06': '$40',
+ 'GPIOR0_GPIOR05': '$20',
+ 'GPIOR0_GPIOR04': '$10',
+ 'GPIOR0_GPIOR03': '$08',
+ 'GPIOR0_GPIOR02': '$04',
+ 'GPIOR0_GPIOR01': '$02',
+ 'GPIOR0_GPIOR00': '$01',
+ 'PLLCSR': '&73',
+ 'PLLCSR_PLLF': '$04',
+ 'PLLCSR_PLLE': '$02',
+ 'PLLCSR_PLOCK': '$01',
+ 'PRR': '&100',
+ 'PRR_PRCAN': '$40',
+ 'PRR_PRPSC': '$20',
+ 'PRR_PRTIM1': '$10',
+ 'PRR_PRTIM0': '$08',
+ 'PRR_PRSPI': '$04',
+ 'PRR_PRLIN': '$02',
+ 'PRR_PRADC': '$01',
+ 'PORTE': '&46',
+ 'DDRE': '&45',
+ 'PINE': '&44',
+ 'TIMSK0': '&110',
+ 'TIMSK0_OCIE0B': '$04',
+ 'TIMSK0_OCIE0A': '$02',
+ 'TIMSK0_TOIE0': '$01',
+ 'TIFR0': '&53',
+ 'TIFR0_OCF0B': '$04',
+ 'TIFR0_OCF0A': '$02',
+ 'TIFR0_TOV0': '$01',
+ 'TCCR0A': '&68',
+ 'TCCR0A_COM0A': '$C0',
+ 'TCCR0A_COM0B': '$30',
+ 'TCCR0A_WGM0': '$03',
+ 'TCCR0B': '&69',
+ 'TCCR0B_FOC0A': '$80',
+ 'TCCR0B_FOC0B': '$40',
+ 'TCCR0B_WGM02': '$08',
+ 'TCCR0B_CS0': '$07',
+ 'TCNT0': '&70',
+ 'OCR0A': '&71',
+ 'OCR0B': '&72',
+ 'GTCCR': '&67',
+ 'GTCCR_TSM': '$80',
+ 'GTCCR_ICPSEL1': '$40',
+ 'GTCCR_PSR10': '$01',
+ 'TIMSK1': '&111',
+ 'TIMSK1_ICIE1': '$20',
+ 'TIMSK1_OCIE1B': '$04',
+ 'TIMSK1_OCIE1A': '$02',
+ 'TIMSK1_TOIE1': '$01',
+ 'TIFR1': '&54',
+ 'TIFR1_ICF1': '$20',
+ 'TIFR1_OCF1B': '$04',
+ 'TIFR1_OCF1A': '$02',
+ 'TIFR1_TOV1': '$01',
+ 'TCCR1A': '&128',
+ 'TCCR1A_COM1A': '$C0',
+ 'TCCR1A_COM1B': '$30',
+ 'TCCR1A_WGM1': '$03',
+ 'TCCR1B': '&129',
+ 'TCCR1B_ICNC1': '$80',
+ 'TCCR1B_ICES1': '$40',
+ 'TCCR1B_WGM1': '$18',
+ 'TCCR1B_CS1': '$07',
+ 'TCCR1C': '&130',
+ 'TCCR1C_FOC1A': '$80',
+ 'TCCR1C_FOC1B': '$40',
+ 'TCNT1': '&132',
+ 'OCR1A': '&136',
+ 'OCR1B': '&138',
+ 'ICR1': '&134',
+ 'ADMUX': '&124',
+ 'ADMUX_REFS': '$C0',
+ 'ADMUX_ADLAR': '$20',
+ 'ADMUX_MUX': '$1F',
+ 'ADCSRA': '&122',
+ 'ADCSRA_ADEN': '$80',
+ 'ADCSRA_ADSC': '$40',
+ 'ADCSRA_ADATE': '$20',
+ 'ADCSRA_ADIF': '$10',
+ 'ADCSRA_ADIE': '$08',
+ 'ADCSRA_ADPS': '$07',
+ 'ADC': '&120',
+ 'ADCSRB': '&123',
+ 'ADCSRB_ADHSM': '$80',
+ 'ADCSRB_ISRCEN': '$40',
+ 'ADCSRB_AREFEN': '$20',
+ 'ADCSRB_ADTS': '$0F',
+ 'DIDR0': '&126',
+ 'DIDR0_ADC7D': '$80',
+ 'DIDR0_ADC6D': '$40',
+ 'DIDR0_ADC5D': '$20',
+ 'DIDR0_ADC4D': '$10',
+ 'DIDR0_ADC3D': '$08',
+ 'DIDR0_ADC2D': '$04',
+ 'DIDR0_ADC1D': '$02',
+ 'DIDR0_ADC0D': '$01',
+ 'DIDR1': '&127',
+ 'DIDR1_AMP2PD': '$40',
+ 'DIDR1_ACMP0D': '$20',
+ 'DIDR1_AMP0PD': '$10',
+ 'DIDR1_AMP0ND': '$08',
+ 'DIDR1_ADC10D': '$04',
+ 'DIDR1_ADC9D': '$02',
+ 'DIDR1_ADC8D': '$01',
+ 'AMP0CSR': '&117',
+ 'AMP0CSR_AMP0EN': '$80',
+ 'AMP0CSR_AMP0IS': '$40',
+ 'AMP0CSR_AMP0G': '$30',
+ 'AMP0CSR_AMPCMP0': '$08',
+ 'AMP0CSR_AMP0TS': '$07',
+ 'AMP1CSR': '&118',
+ 'AMP1CSR_AMP1EN': '$80',
+ 'AMP1CSR_AMP1IS': '$40',
+ 'AMP1CSR_AMP1G': '$30',
+ 'AMP1CSR_AMPCMP1': '$08',
+ 'AMP1CSR_AMP1TS': '$07',
+ 'AMP2CSR': '&119',
+ 'AMP2CSR_AMP2EN': '$80',
+ 'AMP2CSR_AMP2IS': '$40',
+ 'AMP2CSR_AMP2G': '$30',
+ 'AMP2CSR_AMPCMP2': '$08',
+ 'AMP2CSR_AMP2TS': '$07',
+ 'LINCR': '&200',
+ 'LINCR_LSWRES': '$80',
+ 'LINCR_LIN13': '$40',
+ 'LINCR_LCONF': '$30',
+ 'LINCR_LENA': '$08',
+ 'LINCR_LCMD': '$07',
+ 'LINSIR': '&201',
+ 'LINSIR_LIDST': '$E0',
+ 'LINSIR_LBUSY': '$10',
+ 'LINSIR_LERR': '$08',
+ 'LINSIR_LIDOK': '$04',
+ 'LINSIR_LTXOK': '$02',
+ 'LINSIR_LRXOK': '$01',
+ 'LINENIR': '&202',
+ 'LINENIR_LENERR': '$08',
+ 'LINENIR_LENIDOK': '$04',
+ 'LINENIR_LENTXOK': '$02',
+ 'LINENIR_LENRXOK': '$01',
+ 'LINERR': '&203',
+ 'LINERR_LABORT': '$80',
+ 'LINERR_LTOERR': '$40',
+ 'LINERR_LOVERR': '$20',
+ 'LINERR_LFERR': '$10',
+ 'LINERR_LSERR': '$08',
+ 'LINERR_LPERR': '$04',
+ 'LINERR_LCERR': '$02',
+ 'LINERR_LBERR': '$01',
+ 'LINBTR': '&204',
+ 'LINBTR_LDISR': '$80',
+ 'LINBTR_LBT': '$3F',
+ 'LINBRRL': '&205',
+ 'LINBRRL_LDIV': '$FF',
+ 'LINBRRH': '&206',
+ 'LINBRRH_LDIV': '$0F',
+ 'LINDLR': '&207',
+ 'LINDLR_LTXDL': '$F0',
+ 'LINDLR_LRXDL': '$0F',
+ 'LINIDR': '&208',
+ 'LINIDR_LP': '$C0',
+ 'LINIDR_LID': '$3F',
+ 'LINSEL': '&209',
+ 'LINSEL_LAINC': '$08',
+ 'LINSEL_LINDX': '$07',
+ 'LINDAT': '&210',
+ 'LINDAT_LDATA': '$FF',
+ 'SPCR': '&76',
+ 'SPCR_SPIE': '$80',
+ 'SPCR_SPE': '$40',
+ 'SPCR_DORD': '$20',
+ 'SPCR_MSTR': '$10',
+ 'SPCR_CPOL': '$08',
+ 'SPCR_CPHA': '$04',
+ 'SPCR_SPR': '$03',
+ 'SPSR': '&77',
+ 'SPSR_SPIF': '$80',
+ 'SPSR_WCOL': '$40',
+ 'SPSR_SPI2X': '$01',
+ 'SPDR': '&78',
+ 'WDTCSR': '&96',
+ 'WDTCSR_WDIF': '$80',
+ 'WDTCSR_WDIE': '$40',
+ 'WDTCSR_WDP': '$27',
+ 'WDTCSR_WDCE': '$10',
+ 'WDTCSR_WDE': '$08',
+ 'EICRA': '&105',
+ 'EICRA_ISC3': '$C0',
+ 'EICRA_ISC2': '$30',
+ 'EICRA_ISC1': '$0C',
+ 'EICRA_ISC0': '$03',
+ 'EIMSK': '&61',
+ 'EIMSK_INT': '$0F',
+ 'EIFR': '&60',
+ 'EIFR_INTF': '$0F',
+ 'PCICR': '&104',
+ 'PCICR_PCIE': '$0F',
+ 'PCMSK3': '&109',
+ 'PCMSK3_PCINT': '$07',
+ 'PCMSK2': '&108',
+ 'PCMSK2_PCINT': '$FF',
+ 'PCMSK1': '&107',
+ 'PCMSK1_PCINT': '$FF',
+ 'PCMSK0': '&106',
+ 'PCMSK0_PCINT': '$FF',
+ 'PCIFR': '&59',
+ 'PCIFR_PCIF': '$0F',
+ 'EEAR': '&65',
+ 'EEDR': '&64',
+ 'EECR': '&63',
+ 'EECR_EEPM': '$30',
+ 'EECR_EERIE': '$08',
+ 'EECR_EEMWE': '$04',
+ 'EECR_EEWE': '$02',
+ 'EECR_EERE': '$01',
+ 'PIFR': '&188',
+ 'PIFR_PEV': '$0E',
+ 'PIFR_PEOP': '$01',
+ 'PIM': '&187',
+ 'PIM_PEVE': '$0E',
+ 'PIM_PEOPE': '$01',
+ 'PMIC2': '&186',
+ 'PMIC2_POVEN2': '$80',
+ 'PMIC2_PISEL2': '$40',
+ 'PMIC2_PELEV2': '$20',
+ 'PMIC2_PFLTE2': '$10',
+ 'PMIC2_PAOC2': '$08',
+ 'PMIC2_PRFM2': '$07',
+ 'PMIC1': '&185',
+ 'PMIC1_POVEN1': '$80',
+ 'PMIC1_PISEL1': '$40',
+ 'PMIC1_PELEV1': '$20',
+ 'PMIC1_PFLTE1': '$10',
+ 'PMIC1_PAOC1': '$08',
+ 'PMIC1_PRFM1': '$07',
+ 'PMIC0': '&184',
+ 'PMIC0_POVEN0': '$80',
+ 'PMIC0_PISEL0': '$40',
+ 'PMIC0_PELEV0': '$20',
+ 'PMIC0_PFLTE0': '$10',
+ 'PMIC0_PAOC0': '$08',
+ 'PMIC0_PRFM0': '$07',
+ 'PCTL': '&183',
+ 'PCTL_PPRE': '$C0',
+ 'PCTL_PCLKSEL': '$20',
+ 'PCTL_PCCYC': '$02',
+ 'PCTL_PRUN': '$01',
+ 'POC': '&182',
+ 'POC_POEN2B': '$20',
+ 'POC_POEN2A': '$10',
+ 'POC_POEN1B': '$08',
+ 'POC_POEN1A': '$04',
+ 'POC_POEN0B': '$02',
+ 'POC_POEN0A': '$01',
+ 'PCNF': '&181',
+ 'PCNF_PULOCK': '$20',
+ 'PCNF_PMODE': '$10',
+ 'PCNF_POPB': '$08',
+ 'PCNF_POPA': '$04',
+ 'PSYNC': '&180',
+ 'PSYNC_PSYNC2': '$30',
+ 'PSYNC_PSYNC1': '$0C',
+ 'PSYNC_PSYNC0': '$03',
+ 'POCR_RB': '&178',
+ 'POCR2SB': '&176',
+ 'POCR2RA': '&174',
+ 'POCR2SA': '&172',
+ 'POCR1SB': '&170',
+ 'POCR1RA': '&168',
+ 'POCR1SA': '&166',
+ 'POCR0SB': '&164',
+ 'POCR0RA': '&162',
+ 'POCR0SA': '&160',
+ 'ANACOMP0Addr': '2',
+ 'ANACOMP1Addr': '4',
+ 'ANACOMP2Addr': '6',
+ 'ANACOMP3Addr': '8',
+ 'PSC_FAULTAddr': '10',
+ 'PSC_ECAddr': '12',
+ 'INT0Addr': '14',
+ 'INT1Addr': '16',
+ 'INT2Addr': '18',
+ 'INT3Addr': '20',
+ 'TIMER1_CAPTAddr': '22',
+ 'TIMER1_COMPAAddr': '24',
+ 'TIMER1_COMPBAddr': '26',
+ 'TIMER1_OVFAddr': '28',
+ 'TIMER0_COMPAAddr': '30',
+ 'TIMER0_COMPBAddr': '32',
+ 'TIMER0_OVFAddr': '34',
+ 'CAN_INTAddr': '36',
+ 'CAN_TOVFAddr': '38',
+ 'LIN_TCAddr': '40',
+ 'LIN_ERRAddr': '42',
+ 'PCINT0Addr': '44',
+ 'PCINT1Addr': '46',
+ 'PCINT2Addr': '48',
+ 'PCINT3Addr': '50',
+ 'SPI__STCAddr': '52',
+ 'ADCAddr': '54',
+ 'WDTAddr': '56',
+ 'EE_READYAddr': '58',
+ 'SPM_READYAddr': '60'
+} \ No newline at end of file
diff --git a/amforth-6.5/avr8/devices/atmega64m1/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega64m1/words/no-jtag.asm
new file mode 100644
index 0000000..352a4bb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega64m1/words/no-jtag.asm
@@ -0,0 +1,14 @@
+; ( -- )
+; ( -- )
+; MCU
+; disable jtag at runtime
+VE_NOJTAG:
+ .dw $FF05
+ .db "-jtag",0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOJTAG
+XT_NOJTAG:
+ .dw PFA_NOJTAG
+PFA_NOJTAG:
+
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega64m1/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega64m1/words/no-wdt.asm
new file mode 100644
index 0000000..ff6ddd1
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega64m1/words/no-wdt.asm
@@ -0,0 +1,34 @@
+; ( -- )
+; MCU
+; disable watch dog timer at runtime
+VE_NOWDT:
+ .dw $ff04
+ .db "-wdt"
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOWDT
+XT_NOWDT:
+ .dw PFA_NOWDT
+PFA_NOWDT:
+
+ in temp1,SREG
+ push temp1
+ ; Turn always off global interrupt.
+ cli
+ ; Reset Watchdog Timer
+ wdr
+ ; Clear WDRF in MCUSR
+ in temp1, MCUSR
+ andi temp1, (0xff & (0<<WDRF))
+ out MCUSR, temp1
+ ; Write logical one to WDCE and WDE
+ ; Keep old prescaler setting to prevent unintentional time-out
+ in_ temp1, WDTCSR
+ ori temp1, (1<<WDCE) | (1<<WDE)
+ out_ WDTCSR, temp1
+ ; Turn off WDT
+ ldi temp1, (0<<WDE)
+ out_ WDTCSR, temp1
+ ; restore status register
+ pop temp1
+ out SREG,temp1
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega64m1/words/sleep.asm b/amforth-6.5/avr8/devices/atmega64m1/words/sleep.asm
new file mode 100644
index 0000000..256249c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega64m1/words/sleep.asm
@@ -0,0 +1,19 @@
+; ( mode -- )
+; MCU
+; put the controller into the specified sleep mode
+VE_SLEEP:
+ .dw $ff05
+ .db "sleep", 0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_SLEEP
+XT_SLEEP:
+ .dw PFA_SLEEP
+PFA_SLEEP:
+ andi tosl, 7 ; leave only legal mode bits
+ lsl tosl ; move to correct location (bits 3-1)
+ ori tosl, 1 ; set the SE bit
+ out_ SMCR, tosl ; set the sleep config
+ sleep ; nighty-night
+ out_ SMCR, zerol ; 0 protects against accidental sleeps
+ loadtos ; pop argument from stack
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega8/atmega8.frt b/amforth-6.5/avr8/devices/atmega8/atmega8.frt
new file mode 100644
index 0000000..0149247
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega8/atmega8.frt
@@ -0,0 +1,207 @@
+\ Partname: ATmega8
+\ generated automatically
+
+\ ANALOG_COMPARATOR
+&80 constant SFIOR \ Special Function IO Register
+ $08 constant SFIOR_ACME \ Analog Comparator Multiplexer Enable
+&40 constant ACSR \ Analog Comparator Control And Status Register
+ $80 constant ACSR_ACD \ Analog Comparator Disable
+ $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
+ $20 constant ACSR_ACO \ Analog Compare Output
+ $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
+ $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
+ $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
+ $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
+\ SPI
+&47 constant SPDR \ SPI Data Register
+&46 constant SPSR \ SPI Status Register
+ $80 constant SPSR_SPIF \ SPI Interrupt Flag
+ $40 constant SPSR_WCOL \ Write Collision Flag
+ $01 constant SPSR_SPI2X \ Double SPI Speed Bit
+&45 constant SPCR \ SPI Control Register
+ $80 constant SPCR_SPIE \ SPI Interrupt Enable
+ $40 constant SPCR_SPE \ SPI Enable
+ $20 constant SPCR_DORD \ Data Order
+ $10 constant SPCR_MSTR \ Master/Slave Select
+ $08 constant SPCR_CPOL \ Clock polarity
+ $04 constant SPCR_CPHA \ Clock Phase
+ $03 constant SPCR_SPR \ SPI Clock Rate Selects
+\ EXTERNAL_INTERRUPT
+&91 constant GICR \ General Interrupt Control Register
+ $C0 constant GICR_INT \ External Interrupt Request 1 Enable
+ $02 constant GICR_IVSEL \ Interrupt Vector Select
+ $01 constant GICR_IVCE \ Interrupt Vector Change Enable
+&90 constant GIFR \ General Interrupt Flag Register
+ $C0 constant GIFR_INTF \ External Interrupt Flags
+&85 constant MCUCR \ MCU Control Register
+ $0C constant MCUCR_ISC1 \ Interrupt Sense Control 1 Bits
+ $03 constant MCUCR_ISC0 \ Interrupt Sense Control 0 Bits
+\ TIMER_COUNTER_0
+&89 constant TIMSK \ Timer/Counter Interrupt Mask Register
+ $01 constant TIMSK_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
+&88 constant TIFR \ Timer/Counter Interrupt Flag register
+ $01 constant TIFR_TOV0 \ Timer/Counter0 Overflow Flag
+&83 constant TCCR0 \ Timer/Counter0 Control Register
+ $04 constant TCCR0_CS02 \ Clock Select0 bit 2
+ $02 constant TCCR0_CS01 \ Clock Select0 bit 1
+ $01 constant TCCR0_CS00 \ Clock Select0 bit 0
+&82 constant TCNT0 \ Timer Counter 0
+\ TIMER_COUNTER_1
+&79 constant TCCR1A \ Timer/Counter1 Control Register A
+ $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
+ $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
+ $08 constant TCCR1A_FOC1A \ Force Output Compare 1A
+ $04 constant TCCR1A_FOC1B \ Force Output Compare 1B
+ $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
+&78 constant TCCR1B \ Timer/Counter1 Control Register B
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
+ $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
+&76 constant TCNT1 \ Timer/Counter1 Bytes
+&74 constant OCR1A \ Timer/Counter1 Output Compare Register Bytes
+&72 constant OCR1B \ Timer/Counter1 Output Compare Register Bytes
+&70 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
+\ TIMER_COUNTER_2
+&69 constant TCCR2 \ Timer/Counter2 Control Register
+ $80 constant TCCR2_FOC2 \ Force Output Compare
+ $40 constant TCCR2_WGM20 \ Waveform Genration Mode
+ $30 constant TCCR2_COM2 \ Compare Output Mode bits
+ $08 constant TCCR2_WGM21 \ Waveform Generation Mode
+ $07 constant TCCR2_CS2 \ Clock Select bits
+&68 constant TCNT2 \ Timer/Counter2
+&67 constant OCR2 \ Timer/Counter2 Output Compare Register
+&66 constant ASSR \ Asynchronous Status Register
+ $08 constant ASSR_AS2 \ Asynchronous Timer/counter2
+ $04 constant ASSR_TCN2UB \ Timer/Counter2 Update Busy
+ $02 constant ASSR_OCR2UB \ Output Compare Register2 Update Busy
+ $01 constant ASSR_TCR2UB \ Timer/counter Control Register2 Update Busy
+\ USART
+&44 constant UDR \ USART I/O Data Register
+&43 constant UCSRA \ USART Control and Status Register A
+ $80 constant UCSRA_RXC \ USART Receive Complete
+ $40 constant UCSRA_TXC \ USART Transmitt Complete
+ $20 constant UCSRA_UDRE \ USART Data Register Empty
+ $10 constant UCSRA_FE \ Framing Error
+ $08 constant UCSRA_DOR \ Data overRun
+ $04 constant UCSRA_UPE \ Parity Error
+ $02 constant UCSRA_U2X \ Double the USART transmission speed
+ $01 constant UCSRA_MPCM \ Multi-processor Communication Mode
+&42 constant UCSRB \ USART Control and Status Register B
+ $80 constant UCSRB_RXCIE \ RX Complete Interrupt Enable
+ $40 constant UCSRB_TXCIE \ TX Complete Interrupt Enable
+ $20 constant UCSRB_UDRIE \ USART Data register Empty Interrupt Enable
+ $10 constant UCSRB_RXEN \ Receiver Enable
+ $08 constant UCSRB_TXEN \ Transmitter Enable
+ $04 constant UCSRB_UCSZ2 \ Character Size
+ $02 constant UCSRB_RXB8 \ Receive Data Bit 8
+ $01 constant UCSRB_TXB8 \ Transmit Data Bit 8
+&64 constant UCSRC \ USART Control and Status Register C
+ $80 constant UCSRC_URSEL \ Register Select
+ $40 constant UCSRC_UMSEL \ USART Mode Select
+ $30 constant UCSRC_UPM \ Parity Mode Bits
+ $08 constant UCSRC_USBS \ Stop Bit Select
+ $06 constant UCSRC_UCSZ \ Character Size
+ $01 constant UCSRC_UCPOL \ Clock Polarity
+&64 constant UBRRH \ USART Baud Rate Register Hight Byte
+&41 constant UBRRL \ USART Baud Rate Register Low Byte
+\ TWI
+&32 constant TWBR \ TWI Bit Rate register
+&86 constant TWCR \ TWI Control Register
+ $80 constant TWCR_TWINT \ TWI Interrupt Flag
+ $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
+ $20 constant TWCR_TWSTA \ TWI Start Condition Bit
+ $10 constant TWCR_TWSTO \ TWI Stop Condition Bit
+ $08 constant TWCR_TWWC \ TWI Write Collition Flag
+ $04 constant TWCR_TWEN \ TWI Enable Bit
+ $01 constant TWCR_TWIE \ TWI Interrupt Enable
+&33 constant TWSR \ TWI Status Register
+ $F8 constant TWSR_TWS \ TWI Status
+ $03 constant TWSR_TWPS \ TWI Prescaler
+&35 constant TWDR \ TWI Data register
+&34 constant TWAR \ TWI (Slave) Address register
+ $FE constant TWAR_TWA \ TWI (Slave) Address register Bits
+ $01 constant TWAR_TWGCE \ TWI General Call Recognition Enable Bit
+\ WATCHDOG
+&65 constant WDTCR \ Watchdog Timer Control Register
+ $10 constant WDTCR_WDCE \ Watchdog Change Enable
+ $08 constant WDTCR_WDE \ Watch Dog Enable
+ $07 constant WDTCR_WDP \ Watch Dog Timer Prescaler bits
+\ PORTB
+&56 constant PORTB \ Port B Data Register
+&55 constant DDRB \ Port B Data Direction Register
+&54 constant PINB \ Port B Input Pins
+\ PORTC
+&53 constant PORTC \ Port C Data Register
+&52 constant DDRC \ Port C Data Direction Register
+&51 constant PINC \ Port C Input Pins
+\ PORTD
+&50 constant PORTD \ Port D Data Register
+&49 constant DDRD \ Port D Data Direction Register
+&48 constant PIND \ Port D Input Pins
+\ EEPROM
+&62 constant EEAR \ EEPROM Address Register Bytes
+&61 constant EEDR \ EEPROM Data Register
+&60 constant EECR \ EEPROM Control Register
+ $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
+ $04 constant EECR_EEMWE \ EEPROM Master Write Enable
+ $02 constant EECR_EEWE \ EEPROM Write Enable
+ $01 constant EECR_EERE \ EEPROM Read Enable
+\ CPU
+&95 constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ $08 constant SREG_V \ Two's Complement Overflow Flag
+ $04 constant SREG_N \ Negative Flag
+ $02 constant SREG_Z \ Zero Flag
+ $01 constant SREG_C \ Carry Flag
+&93 constant SP \ Stack Pointer
+&84 constant MCUCSR \ MCU Control And Status Register
+ $08 constant MCUCSR_WDRF \ Watchdog Reset Flag
+ $04 constant MCUCSR_BORF \ Brown-out Reset Flag
+ $02 constant MCUCSR_EXTRF \ External Reset Flag
+ $01 constant MCUCSR_PORF \ Power-on reset flag
+&81 constant OSCCAL \ Oscillator Calibration Value
+&87 constant SPMCR \ Store Program Memory Control Register
+ $80 constant SPMCR_SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCR_RWWSB \ Read-While-Write Section Busy
+ $10 constant SPMCR_RWWSRE \ Read-While-Write Section Read Enable
+ $08 constant SPMCR_BLBSET \ Boot Lock Bit Set
+ $04 constant SPMCR_PGWRT \ Page Write
+ $02 constant SPMCR_PGERS \ Page Erase
+ $01 constant SPMCR_SPMEN \ Store Program Memory Enable
+\ AD_CONVERTER
+&39 constant ADMUX \ The ADC multiplexer Selection Register
+ $C0 constant ADMUX_REFS \ Reference Selection Bits
+ $20 constant ADMUX_ADLAR \ Left Adjust Result
+ $0F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
+&38 constant ADCSRA \ The ADC Control and Status register
+ $80 constant ADCSRA_ADEN \ ADC Enable
+ $40 constant ADCSRA_ADSC \ ADC Start Conversion
+ $20 constant ADCSRA_ADFR \ ADC Free Running Select
+ $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
+ $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
+ $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
+&36 constant ADC \ ADC Data Register Bytes
+
+\ Interrupts
+&1 constant INT0Addr \ External Interrupt Request 0
+&2 constant INT1Addr \ External Interrupt Request 1
+&3 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
+&4 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
+&5 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+&6 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
+&7 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
+&8 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+&9 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
+&10 constant SPI__STCAddr \ Serial Transfer Complete
+&11 constant USART__RXCAddr \ USART, Rx Complete
+&12 constant USART__UDREAddr \ USART Data Register Empty
+&13 constant USART__TXCAddr \ USART, Tx Complete
+&14 constant ADCAddr \ ADC Conversion Complete
+&15 constant EE_RDYAddr \ EEPROM Ready
+&16 constant ANA_COMPAddr \ Analog Comparator
+&17 constant TWIAddr \ 2-wire Serial Interface
+&18 constant SPM_RDYAddr \ Store Program Memory Ready
diff --git a/amforth-6.5/avr8/devices/atmega8/device.asm b/amforth-6.5/avr8/devices/atmega8/device.asm
new file mode 100644
index 0000000..d822d36
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega8/device.asm
@@ -0,0 +1,95 @@
+; Partname: ATmega8
+; generated automatically, do not edit
+
+.nolist
+ .include "m8def.inc"
+.list
+
+.equ ramstart = 96
+.equ CELLSIZE = 2
+.macro readflashcell
+ lsl zl
+ rol zh
+ lpm @0, Z+
+ lpm @1, Z+
+.endmacro
+.macro writeflashcell
+ lsl zl
+ rol zh
+.endmacro
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_SPI = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_TIMER_COUNTER_2 = 0
+.set WANT_USART = 0
+.set WANT_TWI = 0
+.set WANT_WATCHDOG = 0
+.set WANT_PORTB = 0
+.set WANT_PORTC = 0
+.set WANT_PORTD = 0
+.set WANT_EEPROM = 0
+.set WANT_CPU = 0
+.set WANT_AD_CONVERTER = 0
+.equ intvecsize = 1 ; please verify; flash size: 8192 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.org 1
+ rcall isr ; External Interrupt Request 0
+.org 2
+ rcall isr ; External Interrupt Request 1
+.org 3
+ rcall isr ; Timer/Counter2 Compare Match
+.org 4
+ rcall isr ; Timer/Counter2 Overflow
+.org 5
+ rcall isr ; Timer/Counter1 Capture Event
+.org 6
+ rcall isr ; Timer/Counter1 Compare Match A
+.org 7
+ rcall isr ; Timer/Counter1 Compare Match B
+.org 8
+ rcall isr ; Timer/Counter1 Overflow
+.org 9
+ rcall isr ; Timer/Counter0 Overflow
+.org 10
+ rcall isr ; Serial Transfer Complete
+.org 11
+ rcall isr ; USART, Rx Complete
+.org 12
+ rcall isr ; USART Data Register Empty
+.org 13
+ rcall isr ; USART, Tx Complete
+.org 14
+ rcall isr ; ADC Conversion Complete
+.org 15
+ rcall isr ; EEPROM Ready
+.org 16
+ rcall isr ; Analog Comparator
+.org 17
+ rcall isr ; 2-wire Serial Interface
+.org 18
+ rcall isr ; Store Program Memory Ready
+.equ INTVECTORS = 19
+.nooverlap
+
+; compatability layer (maybe empty)
+.equ SPMCSR = SPMCR
+.equ EEPE = EEWE
+.equ EEMPE = EEMWE
+
+; controller data area, environment query mcu-info
+mcu_info:
+mcu_ramsize:
+ .dw 1024
+mcu_eepromsize:
+ .dw 512
+mcu_maxdp:
+ .dw 6144
+mcu_numints:
+ .dw 19
+mcu_name:
+ .dw 7
+ .db "ATmega8",0
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega8/device.inc b/amforth-6.5/avr8/devices/atmega8/device.inc
new file mode 100644
index 0000000..733b5ed
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega8/device.inc
@@ -0,0 +1,696 @@
+; Partname: ATmega8
+; generated automatically, no not edit
+
+.if WANT_ANALOG_COMPARATOR == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Special Function IO Register
+VE_SFIOR:
+ .dw $ff05
+ .db "SFIOR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SFIOR
+XT_SFIOR:
+ .dw PFA_DOVARIABLE
+PFA_SFIOR:
+ .dw 80
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Control And Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw 40
+
+.endif
+.if WANT_SPI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR:
+ .dw $ff04
+ .db "SPDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR
+XT_SPDR:
+ .dw PFA_DOVARIABLE
+PFA_SPDR:
+ .dw 47
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR:
+ .dw $ff04
+ .db "SPSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR
+XT_SPSR:
+ .dw PFA_DOVARIABLE
+PFA_SPSR:
+ .dw 46
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR:
+ .dw $ff04
+ .db "SPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR
+XT_SPCR:
+ .dw PFA_DOVARIABLE
+PFA_SPCR:
+ .dw 45
+
+.endif
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ( -- addr ) System Constant
+; R( -- )
+; General Interrupt Control Register
+VE_GICR:
+ .dw $ff04
+ .db "GICR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GICR
+XT_GICR:
+ .dw PFA_DOVARIABLE
+PFA_GICR:
+ .dw 91
+; ( -- addr ) System Constant
+; R( -- )
+; General Interrupt Flag Register
+VE_GIFR:
+ .dw $ff04
+ .db "GIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GIFR
+XT_GIFR:
+ .dw PFA_DOVARIABLE
+PFA_GIFR:
+ .dw 90
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw 85
+
+.endif
+.if WANT_TIMER_COUNTER_0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Mask Register
+VE_TIMSK:
+ .dw $ff05
+ .db "TIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK
+XT_TIMSK:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK:
+ .dw 89
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Flag register
+VE_TIFR:
+ .dw $ff04
+ .db "TIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR
+XT_TIFR:
+ .dw PFA_DOVARIABLE
+PFA_TIFR:
+ .dw 88
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Control Register
+VE_TCCR0:
+ .dw $ff05
+ .db "TCCR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0
+XT_TCCR0:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0:
+ .dw 83
+; ( -- addr ) System Constant
+; R( -- )
+; Timer Counter 0
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw 82
+
+.endif
+.if WANT_TIMER_COUNTER_1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw 79
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw 78
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Bytes
+VE_TCNT1:
+ .dw $ff05
+ .db "TCNT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1
+XT_TCNT1:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1:
+ .dw 76
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register Bytes
+VE_OCR1A:
+ .dw $ff05
+ .db "OCR1A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1A
+XT_OCR1A:
+ .dw PFA_DOVARIABLE
+PFA_OCR1A:
+ .dw 74
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register Bytes
+VE_OCR1B:
+ .dw $ff05
+ .db "OCR1B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1B
+XT_OCR1B:
+ .dw PFA_DOVARIABLE
+PFA_OCR1B:
+ .dw 72
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Bytes
+VE_ICR1:
+ .dw $ff04
+ .db "ICR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1
+XT_ICR1:
+ .dw PFA_DOVARIABLE
+PFA_ICR1:
+ .dw 70
+
+.endif
+.if WANT_TIMER_COUNTER_2 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register
+VE_TCCR2:
+ .dw $ff05
+ .db "TCCR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2
+XT_TCCR2:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2:
+ .dw 69
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2
+VE_TCNT2:
+ .dw $ff05
+ .db "TCNT2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT2
+XT_TCNT2:
+ .dw PFA_DOVARIABLE
+PFA_TCNT2:
+ .dw 68
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register
+VE_OCR2:
+ .dw $ff04
+ .db "OCR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2
+XT_OCR2:
+ .dw PFA_DOVARIABLE
+PFA_OCR2:
+ .dw 67
+; ( -- addr ) System Constant
+; R( -- )
+; Asynchronous Status Register
+VE_ASSR:
+ .dw $ff04
+ .db "ASSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ASSR
+XT_ASSR:
+ .dw PFA_DOVARIABLE
+PFA_ASSR:
+ .dw 66
+
+.endif
+.if WANT_USART == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR:
+ .dw $ff03
+ .db "UDR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR
+XT_UDR:
+ .dw PFA_DOVARIABLE
+PFA_UDR:
+ .dw 44
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSRA:
+ .dw $ff05
+ .db "UCSRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSRA
+XT_UCSRA:
+ .dw PFA_DOVARIABLE
+PFA_UCSRA:
+ .dw 43
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSRB:
+ .dw $ff05
+ .db "UCSRB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSRB
+XT_UCSRB:
+ .dw PFA_DOVARIABLE
+PFA_UCSRB:
+ .dw 42
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSRC:
+ .dw $ff05
+ .db "UCSRC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSRC
+XT_UCSRC:
+ .dw PFA_DOVARIABLE
+PFA_UCSRC:
+ .dw 64
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Hight Byte
+VE_UBRRH:
+ .dw $ff05
+ .db "UBRRH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRRH
+XT_UBRRH:
+ .dw PFA_DOVARIABLE
+PFA_UBRRH:
+ .dw 64
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Low Byte
+VE_UBRRL:
+ .dw $ff05
+ .db "UBRRL",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRRL
+XT_UBRRL:
+ .dw PFA_DOVARIABLE
+PFA_UBRRL:
+ .dw 41
+
+.endif
+.if WANT_TWI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Bit Rate register
+VE_TWBR:
+ .dw $ff04
+ .db "TWBR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWBR
+XT_TWBR:
+ .dw PFA_DOVARIABLE
+PFA_TWBR:
+ .dw 32
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Control Register
+VE_TWCR:
+ .dw $ff04
+ .db "TWCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWCR
+XT_TWCR:
+ .dw PFA_DOVARIABLE
+PFA_TWCR:
+ .dw 86
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Status Register
+VE_TWSR:
+ .dw $ff04
+ .db "TWSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWSR
+XT_TWSR:
+ .dw PFA_DOVARIABLE
+PFA_TWSR:
+ .dw 33
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Data register
+VE_TWDR:
+ .dw $ff04
+ .db "TWDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWDR
+XT_TWDR:
+ .dw PFA_DOVARIABLE
+PFA_TWDR:
+ .dw 35
+; ( -- addr ) System Constant
+; R( -- )
+; TWI (Slave) Address register
+VE_TWAR:
+ .dw $ff04
+ .db "TWAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWAR
+XT_TWAR:
+ .dw PFA_DOVARIABLE
+PFA_TWAR:
+ .dw 34
+
+.endif
+.if WANT_WATCHDOG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCR:
+ .dw $ff05
+ .db "WDTCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCR
+XT_WDTCR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCR:
+ .dw 65
+
+.endif
+.if WANT_PORTB == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw 56
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw 55
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw 54
+
+.endif
+.if WANT_PORTC == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Register
+VE_PORTC:
+ .dw $ff05
+ .db "PORTC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTC
+XT_PORTC:
+ .dw PFA_DOVARIABLE
+PFA_PORTC:
+ .dw 53
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Direction Register
+VE_DDRC:
+ .dw $ff04
+ .db "DDRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRC
+XT_DDRC:
+ .dw PFA_DOVARIABLE
+PFA_DDRC:
+ .dw 52
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Input Pins
+VE_PINC:
+ .dw $ff04
+ .db "PINC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINC
+XT_PINC:
+ .dw PFA_DOVARIABLE
+PFA_PINC:
+ .dw 51
+
+.endif
+.if WANT_PORTD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw 50
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw 49
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw 48
+
+.endif
+.if WANT_EEPROM == 1
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Address Register Bytes
+VE_EEAR:
+ .dw $ff04
+ .db "EEAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEAR
+XT_EEAR:
+ .dw PFA_DOVARIABLE
+PFA_EEAR:
+ .dw 62
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw 61
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw 60
+
+.endif
+.if WANT_CPU == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw 95
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer
+VE_SP:
+ .dw $ff02
+ .db "SP"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SP
+XT_SP:
+ .dw PFA_DOVARIABLE
+PFA_SP:
+ .dw 93
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control And Status Register
+VE_MCUCSR:
+ .dw $ff06
+ .db "MCUCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCSR
+XT_MCUCSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCSR:
+ .dw 84
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Calibration Value
+VE_OSCCAL:
+ .dw $ff06
+ .db "OSCCAL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSCCAL
+XT_OSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_OSCCAL:
+ .dw 81
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control Register
+VE_SPMCR:
+ .dw $ff05
+ .db "SPMCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCR
+XT_SPMCR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCR:
+ .dw 87
+
+.endif
+.if WANT_AD_CONVERTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC multiplexer Selection Register
+VE_ADMUX:
+ .dw $ff05
+ .db "ADMUX",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADMUX
+XT_ADMUX:
+ .dw PFA_DOVARIABLE
+PFA_ADMUX:
+ .dw 39
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register
+VE_ADCSRA:
+ .dw $ff06
+ .db "ADCSRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRA
+XT_ADCSRA:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRA:
+ .dw 38
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register Bytes
+VE_ADC:
+ .dw $ff03
+ .db "ADC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADC
+XT_ADC:
+ .dw PFA_DOVARIABLE
+PFA_ADC:
+ .dw 36
+
+.endif
diff --git a/amforth-6.5/avr8/devices/atmega8/device.py b/amforth-6.5/avr8/devices/atmega8/device.py
new file mode 100644
index 0000000..9f561f5
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega8/device.py
@@ -0,0 +1,191 @@
+# Partname: ATmega8
+# generated automatically, do not edit
+MCUREGS = {
+ 'SFIOR': '&80',
+ 'SFIOR_ACME': '$08',
+ 'ACSR': '&40',
+ 'ACSR_ACD': '$80',
+ 'ACSR_ACBG': '$40',
+ 'ACSR_ACO': '$20',
+ 'ACSR_ACI': '$10',
+ 'ACSR_ACIE': '$08',
+ 'ACSR_ACIC': '$04',
+ 'ACSR_ACIS': '$03',
+ 'SPDR': '&47',
+ 'SPSR': '&46',
+ 'SPSR_SPIF': '$80',
+ 'SPSR_WCOL': '$40',
+ 'SPSR_SPI2X': '$01',
+ 'SPCR': '&45',
+ 'SPCR_SPIE': '$80',
+ 'SPCR_SPE': '$40',
+ 'SPCR_DORD': '$20',
+ 'SPCR_MSTR': '$10',
+ 'SPCR_CPOL': '$08',
+ 'SPCR_CPHA': '$04',
+ 'SPCR_SPR': '$03',
+ 'GICR': '&91',
+ 'GICR_INT': '$C0',
+ 'GICR_IVSEL': '$02',
+ 'GICR_IVCE': '$01',
+ 'GIFR': '&90',
+ 'GIFR_INTF': '$C0',
+ 'MCUCR': '&85',
+ 'MCUCR_ISC1': '$0C',
+ 'MCUCR_ISC0': '$03',
+ 'TIMSK': '&89',
+ 'TIMSK_TOIE0': '$01',
+ 'TIFR': '&88',
+ 'TIFR_TOV0': '$01',
+ 'TCCR0': '&83',
+ 'TCCR0_CS02': '$04',
+ 'TCCR0_CS01': '$02',
+ 'TCCR0_CS00': '$01',
+ 'TCNT0': '&82',
+ 'TCCR1A': '&79',
+ 'TCCR1A_COM1A': '$C0',
+ 'TCCR1A_COM1B': '$30',
+ 'TCCR1A_FOC1A': '$08',
+ 'TCCR1A_FOC1B': '$04',
+ 'TCCR1A_WGM1': '$03',
+ 'TCCR1B': '&78',
+ 'TCCR1B_ICNC1': '$80',
+ 'TCCR1B_ICES1': '$40',
+ 'TCCR1B_WGM1': '$18',
+ 'TCCR1B_CS1': '$07',
+ 'TCNT1': '&76',
+ 'OCR1A': '&74',
+ 'OCR1B': '&72',
+ 'ICR1': '&70',
+ 'TCCR2': '&69',
+ 'TCCR2_FOC2': '$80',
+ 'TCCR2_WGM20': '$40',
+ 'TCCR2_COM2': '$30',
+ 'TCCR2_WGM21': '$08',
+ 'TCCR2_CS2': '$07',
+ 'TCNT2': '&68',
+ 'OCR2': '&67',
+ 'ASSR': '&66',
+ 'ASSR_AS2': '$08',
+ 'ASSR_TCN2UB': '$04',
+ 'ASSR_OCR2UB': '$02',
+ 'ASSR_TCR2UB': '$01',
+ 'UDR': '&44',
+ 'UCSRA': '&43',
+ 'UCSRA_RXC': '$80',
+ 'UCSRA_TXC': '$40',
+ 'UCSRA_UDRE': '$20',
+ 'UCSRA_FE': '$10',
+ 'UCSRA_DOR': '$08',
+ 'UCSRA_UPE': '$04',
+ 'UCSRA_U2X': '$02',
+ 'UCSRA_MPCM': '$01',
+ 'UCSRB': '&42',
+ 'UCSRB_RXCIE': '$80',
+ 'UCSRB_TXCIE': '$40',
+ 'UCSRB_UDRIE': '$20',
+ 'UCSRB_RXEN': '$10',
+ 'UCSRB_TXEN': '$08',
+ 'UCSRB_UCSZ2': '$04',
+ 'UCSRB_RXB8': '$02',
+ 'UCSRB_TXB8': '$01',
+ 'UCSRC': '&64',
+ 'UCSRC_URSEL': '$80',
+ 'UCSRC_UMSEL': '$40',
+ 'UCSRC_UPM': '$30',
+ 'UCSRC_USBS': '$08',
+ 'UCSRC_UCSZ': '$06',
+ 'UCSRC_UCPOL': '$01',
+ 'UBRRH': '&64',
+ 'UBRRL': '&41',
+ 'TWBR': '&32',
+ 'TWCR': '&86',
+ 'TWCR_TWINT': '$80',
+ 'TWCR_TWEA': '$40',
+ 'TWCR_TWSTA': '$20',
+ 'TWCR_TWSTO': '$10',
+ 'TWCR_TWWC': '$08',
+ 'TWCR_TWEN': '$04',
+ 'TWCR_TWIE': '$01',
+ 'TWSR': '&33',
+ 'TWSR_TWS': '$F8',
+ 'TWSR_TWPS': '$03',
+ 'TWDR': '&35',
+ 'TWAR': '&34',
+ 'TWAR_TWA': '$FE',
+ 'TWAR_TWGCE': '$01',
+ 'WDTCR': '&65',
+ 'WDTCR_WDCE': '$10',
+ 'WDTCR_WDE': '$08',
+ 'WDTCR_WDP': '$07',
+ 'PORTB': '&56',
+ 'DDRB': '&55',
+ 'PINB': '&54',
+ 'PORTC': '&53',
+ 'DDRC': '&52',
+ 'PINC': '&51',
+ 'PORTD': '&50',
+ 'DDRD': '&49',
+ 'PIND': '&48',
+ 'EEAR': '&62',
+ 'EEDR': '&61',
+ 'EECR': '&60',
+ 'EECR_EERIE': '$08',
+ 'EECR_EEMWE': '$04',
+ 'EECR_EEWE': '$02',
+ 'EECR_EERE': '$01',
+ 'SREG': '&95',
+ 'SREG_I': '$80',
+ 'SREG_T': '$40',
+ 'SREG_H': '$20',
+ 'SREG_S': '$10',
+ 'SREG_V': '$08',
+ 'SREG_N': '$04',
+ 'SREG_Z': '$02',
+ 'SREG_C': '$01',
+ 'SP': '&93',
+ 'MCUCSR': '&84',
+ 'MCUCSR_WDRF': '$08',
+ 'MCUCSR_BORF': '$04',
+ 'MCUCSR_EXTRF': '$02',
+ 'MCUCSR_PORF': '$01',
+ 'OSCCAL': '&81',
+ 'SPMCR': '&87',
+ 'SPMCR_SPMIE': '$80',
+ 'SPMCR_RWWSB': '$40',
+ 'SPMCR_RWWSRE': '$10',
+ 'SPMCR_BLBSET': '$08',
+ 'SPMCR_PGWRT': '$04',
+ 'SPMCR_PGERS': '$02',
+ 'SPMCR_SPMEN': '$01',
+ 'ADMUX': '&39',
+ 'ADMUX_REFS': '$C0',
+ 'ADMUX_ADLAR': '$20',
+ 'ADMUX_MUX': '$0F',
+ 'ADCSRA': '&38',
+ 'ADCSRA_ADEN': '$80',
+ 'ADCSRA_ADSC': '$40',
+ 'ADCSRA_ADFR': '$20',
+ 'ADCSRA_ADIF': '$10',
+ 'ADCSRA_ADIE': '$08',
+ 'ADCSRA_ADPS': '$07',
+ 'ADC': '&36',
+ 'INT0Addr': '1',
+ 'INT1Addr': '2',
+ 'TIMER2_COMPAddr': '3',
+ 'TIMER2_OVFAddr': '4',
+ 'TIMER1_CAPTAddr': '5',
+ 'TIMER1_COMPAAddr': '6',
+ 'TIMER1_COMPBAddr': '7',
+ 'TIMER1_OVFAddr': '8',
+ 'TIMER0_OVFAddr': '9',
+ 'SPI__STCAddr': '10',
+ 'USART__RXCAddr': '11',
+ 'USART__UDREAddr': '12',
+ 'USART__TXCAddr': '13',
+ 'ADCAddr': '14',
+ 'EE_RDYAddr': '15',
+ 'ANA_COMPAddr': '16',
+ 'TWIAddr': '17',
+ 'SPM_RDYAddr': '18'
+} \ No newline at end of file
diff --git a/amforth-6.5/avr8/devices/atmega8/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega8/words/no-jtag.asm
new file mode 100644
index 0000000..352a4bb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega8/words/no-jtag.asm
@@ -0,0 +1,14 @@
+; ( -- )
+; ( -- )
+; MCU
+; disable jtag at runtime
+VE_NOJTAG:
+ .dw $FF05
+ .db "-jtag",0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOJTAG
+XT_NOJTAG:
+ .dw PFA_NOJTAG
+PFA_NOJTAG:
+
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega8/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega8/words/no-wdt.asm
new file mode 100644
index 0000000..4a12261
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega8/words/no-wdt.asm
@@ -0,0 +1,22 @@
+; ( -- )
+; MCU
+; disable watch dog timer at runtime
+VE_NOWDT:
+ .dw $ff04
+ .db "-wdt"
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOWDT
+XT_NOWDT:
+ .dw PFA_NOWDT
+PFA_NOWDT:
+
+; Reset WDT
+ wdr
+; Write logical one to WDTOE and WDE
+ in_ temp1, WDTCR
+ ori temp1, (1<<WDTOE)|(1<<WDE)
+ out WDTCR, temp1
+; Turn off WDT
+ ldi temp1, (0<<WDE)
+ out_ WDTCR, temp1
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega8/words/sleep.asm b/amforth-6.5/avr8/devices/atmega8/words/sleep.asm
new file mode 100644
index 0000000..778fa32
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega8/words/sleep.asm
@@ -0,0 +1,24 @@
+; ( mode -- )
+; MCU
+; put the controller into the specified sleep mode
+VE_SLEEP:
+ .dw $ff05
+ .db "sleep", 0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_SLEEP
+XT_SLEEP:
+ .dw PFA_SLEEP
+PFA_SLEEP:
+ andi tosl, 7 ; leave only legal mode bits
+ swap tosl ; move to correct location (bits 6-4, atmega32)
+ ori tosl, $80 ; set the SE bit (atmega32: bit 7, not bit 0)
+ out_ MCUCR, tosl ; set the sleep config (atmega32: MCUCR not SMCR)
+ sleep ; nighty-night
+;; the 4 lower bits of MCUCR should not be touched
+ in_ tosl, MCUCR
+ andi tosl, $0F
+ out_ MCUCR, tosl
+ ;clr tosl ; need to clean up the SMCR reg before we leave
+ ;out SMCR, tosl ; 0 protects against accidental sleeps
+ loadtos ; pop argument from stack
+ jmp DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega8515/atmega8515.frt b/amforth-6.5/avr8/devices/atmega8515/atmega8515.frt
new file mode 100644
index 0000000..576e9e6
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega8515/atmega8515.frt
@@ -0,0 +1,193 @@
+\ Partname: ATmega8515
+\ generated automatically
+
+\ ANALOG_COMPARATOR
+&40 constant ACSR \ Analog Comparator Control And Status Register
+ $80 constant ACSR_ACD \ Analog Comparator Disable
+ $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
+ $20 constant ACSR_ACO \ Analog Compare Output
+ $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
+ $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
+ $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
+ $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
+\ USART
+&44 constant UDR \ USART I/O Data Register
+&43 constant UCSRA \ USART Control and Status Register A
+ $80 constant UCSRA_RXC \ USART Receive Complete
+ $40 constant UCSRA_TXC \ USART Transmitt Complete
+ $20 constant UCSRA_UDRE \ USART Data Register Empty
+ $10 constant UCSRA_FE \ Framing Error
+ $08 constant UCSRA_DOR \ Data overRun
+ $04 constant UCSRA_UPE \ Parity Error
+ $02 constant UCSRA_U2X \ Double the USART transmission speed
+ $01 constant UCSRA_MPCM \ Multi-processor Communication Mode
+&42 constant UCSRB \ USART Control and Status Register B
+ $80 constant UCSRB_RXCIE \ RX Complete Interrupt Enable
+ $40 constant UCSRB_TXCIE \ TX Complete Interrupt Enable
+ $20 constant UCSRB_UDRIE \ USART Data register Empty Interrupt Enable
+ $10 constant UCSRB_RXEN \ Receiver Enable
+ $08 constant UCSRB_TXEN \ Transmitter Enable
+ $04 constant UCSRB_UCSZ2 \ Character Size Bit 2
+ $02 constant UCSRB_RXB8 \ Receive Data Bit 8
+ $01 constant UCSRB_TXB8 \ Transmit Data Bit 8
+&64 constant UCSRC \ USART Control and Status Register C
+ $80 constant UCSRC_URSEL \ Register Select
+ $40 constant UCSRC_UMSEL \ USART Mode Select
+ $30 constant UCSRC_UPM \ Parity Mode Bits
+ $08 constant UCSRC_USBS \ Stop Bit Select
+ $06 constant UCSRC_UCSZ \ Character Size Bits
+ $01 constant UCSRC_UCPOL \ Clock Polarity
+&64 constant UBRRH \ USART Baud Rate Register High Byte
+ $80 constant UBRRH_URSEL \ Register Select
+ $0C constant UBRRH_UBRR1 \ USART Baud Rate Register bit 11
+ $03 constant UBRRH_UBRR \ USART Baud Rate Register bits
+&41 constant UBRRL \ USART Baud Rate Register Low Byte
+\ SPI
+&47 constant SPDR \ SPI Data Register
+&46 constant SPSR \ SPI Status Register
+ $80 constant SPSR_SPIF \ SPI Interrupt Flag
+ $40 constant SPSR_WCOL \ Write Collision Flag
+ $01 constant SPSR_SPI2X \ Double SPI Speed Bit
+&45 constant SPCR \ SPI Control Register
+ $80 constant SPCR_SPIE \ SPI Interrupt Enable
+ $40 constant SPCR_SPE \ SPI Enable
+ $20 constant SPCR_DORD \ Data Order
+ $10 constant SPCR_MSTR \ Master/Slave Select
+ $08 constant SPCR_CPOL \ Clock polarity
+ $04 constant SPCR_CPHA \ Clock Phase
+ $03 constant SPCR_SPR \ SPI Clock Rate Selects
+\ CPU
+&95 constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ $08 constant SREG_V \ Two's Complement Overflow Flag
+ $04 constant SREG_N \ Negative Flag
+ $02 constant SREG_Z \ Zero Flag
+ $01 constant SREG_C \ Carry Flag
+&93 constant SP \ Stack Pointer
+&86 constant EMCUCR \ Extended MCU Control Register
+ $80 constant EMCUCR_SM0 \ Sleep Mode Select Bit 0
+ $70 constant EMCUCR_SRL \ Wait State Selector Limit bits
+ $0C constant EMCUCR_SRW0 \ Wait State Select Bits for Lower Sector, bits
+ $02 constant EMCUCR_SRW11 \ Wait State Select Bits for Upper Sector, bit 1
+ $01 constant EMCUCR_ISC2 \ Interrupt Sense Control 2
+&85 constant MCUCR \ MCU Control Register
+ $80 constant MCUCR_SRE \ External SRAM/XMEM Enable
+ $40 constant MCUCR_SRW10 \ Wait State Select Bits for Upper Sector, bit 0
+ $20 constant MCUCR_SE \ Sleep Enable
+ $10 constant MCUCR_SM1 \ Sleep Mode Select Bit 1
+ $0C constant MCUCR_ISC1 \ Interrupt Sense Control 1 Bits
+ $03 constant MCUCR_ISC0 \ Interrupt Sense Control 0 Bits
+&84 constant MCUCSR \ MCU Control And Status Register
+ $20 constant MCUCSR_SM2 \ Sleep Mode Select Bit 2
+ $08 constant MCUCSR_WDRF \ Watchdog Reset Flag
+ $04 constant MCUCSR_BORF \ Brown-out Reset Flag
+ $02 constant MCUCSR_EXTRF \ External Reset Flag
+ $01 constant MCUCSR_PORF \ Power-on reset flag
+&36 constant OSCCAL \ Oscillator Calibration Value
+&87 constant SPMCR \ Store Program Memory Control Register
+ $80 constant SPMCR_SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCR_RWWSB \ Read-While-Write Section Busy
+ $10 constant SPMCR_RWWSRE \ Read-While-Write Section Read Enable
+ $08 constant SPMCR_BLBSET \ Boot Lock Bit Set
+ $04 constant SPMCR_PGWRT \ Page Write
+ $02 constant SPMCR_PGERS \ Page Erase
+ $01 constant SPMCR_SPMEN \ Store Program Memory Enable
+&80 constant SFIOR \ Special Function IO Register
+ $40 constant SFIOR_XMBK \ External Memory Bus Keeper Enable
+ $38 constant SFIOR_XMM \ External Memory High Mask Bits
+ $04 constant SFIOR_PUD \ Pull-up Disable
+ $01 constant SFIOR_PSR10 \ Prescaler Reset Timer / Counter 1 and Timer / Counter 0
+\ EXTERNAL_INTERRUPT
+&91 constant GICR \ General Interrupt Control Register
+ $C0 constant GICR_INT \ External Interrupt Request 1 Enable
+ $20 constant GICR_INT2 \ External Interrupt Request 2 Enable
+ $02 constant GICR_IVSEL \ Interrupt Vector Select
+ $01 constant GICR_IVCE \ Interrupt Vector Change Enable
+&90 constant GIFR \ General Interrupt Flag Register
+ $C0 constant GIFR_INTF \ External Interrupt Flags
+ $20 constant GIFR_INTF2 \ External Interrupt Flag 2
+\ WATCHDOG
+&65 constant WDTCR \ Watchdog Timer Control Register
+ $10 constant WDTCR_WDCE \ Watchdog Change Enable
+ $08 constant WDTCR_WDE \ Watch Dog Enable
+ $07 constant WDTCR_WDP \ Watch Dog Timer Prescaler bits
+\ TIMER_COUNTER_0
+&83 constant TCCR0 \ Timer/Counter 0 Control Register
+ $80 constant TCCR0_FOC0 \ Force Output Compare
+ $40 constant TCCR0_WGM00 \ Waveform Generation Mode 0
+ $30 constant TCCR0_COM0 \ Compare Match Output Modes
+ $08 constant TCCR0_WGM01 \ Waveform Generation Mode 1
+ $07 constant TCCR0_CS0 \ Clock Selects
+&82 constant TCNT0 \ Timer/Counter 0 Register
+&81 constant OCR0 \ Timer/Counter 0 Output Compare Register
+&89 constant TIMSK \ Timer/Counter Interrupt Mask Register
+ $02 constant TIMSK_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
+ $01 constant TIMSK_OCIE0 \ Timer/Counter0 Output Compare Match Interrupt register
+&88 constant TIFR \ Timer/Counter Interrupt Flag register
+ $02 constant TIFR_TOV0 \ Timer/Counter0 Overflow Flag
+ $01 constant TIFR_OCF0 \ Output Compare Flag 0
+\ TIMER_COUNTER_1
+&79 constant TCCR1A \ Timer/Counter1 Control Register A
+ $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
+ $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
+ $08 constant TCCR1A_FOC1A \ Force Output Compare for Channel A
+ $04 constant TCCR1A_FOC1B \ Force Output Compare for Channel B
+ $03 constant TCCR1A_WGM1 \ Pulse Width Modulator Select Bits
+&78 constant TCCR1B \ Timer/Counter1 Control Register B
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ $18 constant TCCR1B_WGM1 \ Pulse Width Modulator Select Bits
+ $07 constant TCCR1B_CS1 \ Clock Select1 bits
+&76 constant TCNT1 \ Timer/Counter1 Bytes
+&74 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
+&72 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
+&68 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
+\ PORTA
+&59 constant PORTA \ Port A Data Register
+&58 constant DDRA \ Port A Data Direction Register
+&57 constant PINA \ Port A Input Pins
+\ PORTB
+&56 constant PORTB \ Port B Data Register
+&55 constant DDRB \ Port B Data Direction Register
+&54 constant PINB \ Port B Input Pins
+\ PORTC
+&53 constant PORTC \ Port C Data Register
+&52 constant DDRC \ Port C Data Direction Register
+&51 constant PINC \ Port C Input Pins
+\ PORTD
+&50 constant PORTD \ Port D Data Register
+&49 constant DDRD \ Port D Data Direction Register
+&48 constant PIND \ Port D Input Pins
+\ PORTE
+&39 constant PORTE \ Port E Data Register
+&38 constant DDRE \ Port E Data Direction Register
+&37 constant PINE \ Port E Input Pins
+\ EEPROM
+&62 constant EEAR \ EEPROM Address Register Bytes
+&61 constant EEDR \ EEPROM Data Register
+&60 constant EECR \ EEPROM Control Register
+ $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
+ $04 constant EECR_EEMWE \ EEPROM Master Write Enable
+ $02 constant EECR_EEWE \ EEPROM Write Enable
+ $01 constant EECR_EERE \ EEPROM Read Enable
+
+\ Interrupts
+&1 constant INT0Addr \ External Interrupt Request 0
+&2 constant INT1Addr \ External Interrupt Request 1
+&3 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+&4 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
+&5 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare MatchB
+&6 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+&7 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
+&8 constant SPI_STCAddr \ Serial Transfer Complete
+&9 constant USART_RXAddr \ USART, Rx Complete
+&10 constant USART_UDREAddr \ USART Data Register Empty
+&11 constant USART__TXAddr \ USART, Tx Complete
+&12 constant ANA_COMPAddr \ Analog Comparator
+&13 constant INT2Addr \ External Interrupt Request 2
+&14 constant TIMER0_COMPAddr \ Timer 0 Compare Match
+&15 constant EE_RDYAddr \ EEPROM Ready
+&16 constant SPM_RDYAddr \ Store Program Memory Ready
diff --git a/amforth-6.5/avr8/devices/atmega8515/device.asm b/amforth-6.5/avr8/devices/atmega8515/device.asm
new file mode 100644
index 0000000..801e9dc
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega8515/device.asm
@@ -0,0 +1,90 @@
+; Partname: ATmega8515
+; generated automatically, do not edit
+
+.nolist
+ .include "m8515def.inc"
+.list
+
+.equ ramstart = 96
+.equ CELLSIZE = 2
+.macro readflashcell
+ lsl zl
+ rol zh
+ lpm @0, Z+
+ lpm @1, Z+
+.endmacro
+.macro writeflashcell
+ lsl zl
+ rol zh
+.endmacro
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_USART = 0
+.set WANT_SPI = 0
+.set WANT_CPU = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_WATCHDOG = 0
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_PORTA = 0
+.set WANT_PORTB = 0
+.set WANT_PORTC = 0
+.set WANT_PORTD = 0
+.set WANT_PORTE = 0
+.set WANT_EEPROM = 0
+.equ intvecsize = 1 ; please verify; flash size: 8192 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.org 1
+ rcall isr ; External Interrupt Request 0
+.org 2
+ rcall isr ; External Interrupt Request 1
+.org 3
+ rcall isr ; Timer/Counter1 Capture Event
+.org 4
+ rcall isr ; Timer/Counter1 Compare Match A
+.org 5
+ rcall isr ; Timer/Counter1 Compare MatchB
+.org 6
+ rcall isr ; Timer/Counter1 Overflow
+.org 7
+ rcall isr ; Timer/Counter0 Overflow
+.org 8
+ rcall isr ; Serial Transfer Complete
+.org 9
+ rcall isr ; USART, Rx Complete
+.org 10
+ rcall isr ; USART Data Register Empty
+.org 11
+ rcall isr ; USART, Tx Complete
+.org 12
+ rcall isr ; Analog Comparator
+.org 13
+ rcall isr ; External Interrupt Request 2
+.org 14
+ rcall isr ; Timer 0 Compare Match
+.org 15
+ rcall isr ; EEPROM Ready
+.org 16
+ rcall isr ; Store Program Memory Ready
+.equ INTVECTORS = 17
+.nooverlap
+
+; compatability layer (maybe empty)
+.equ SPMCSR = SPMCR
+.equ EEPE = EEWE
+.equ EEMPE = EEMWE
+
+; controller data area, environment query mcu-info
+mcu_info:
+mcu_ramsize:
+ .dw 512
+mcu_eepromsize:
+ .dw 512
+mcu_maxdp:
+ .dw 6144
+mcu_numints:
+ .dw 17
+mcu_name:
+ .dw 10
+ .db "ATmega8515"
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega8515/device.inc b/amforth-6.5/avr8/devices/atmega8515/device.inc
new file mode 100644
index 0000000..a8b7e91
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega8515/device.inc
@@ -0,0 +1,645 @@
+; Partname: ATmega8515
+; generated automatically, no not edit
+
+.if WANT_ANALOG_COMPARATOR == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Control And Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw 40
+
+.endif
+.if WANT_USART == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR:
+ .dw $ff03
+ .db "UDR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR
+XT_UDR:
+ .dw PFA_DOVARIABLE
+PFA_UDR:
+ .dw 44
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSRA:
+ .dw $ff05
+ .db "UCSRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSRA
+XT_UCSRA:
+ .dw PFA_DOVARIABLE
+PFA_UCSRA:
+ .dw 43
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSRB:
+ .dw $ff05
+ .db "UCSRB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSRB
+XT_UCSRB:
+ .dw PFA_DOVARIABLE
+PFA_UCSRB:
+ .dw 42
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSRC:
+ .dw $ff05
+ .db "UCSRC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSRC
+XT_UCSRC:
+ .dw PFA_DOVARIABLE
+PFA_UCSRC:
+ .dw 64
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register High Byte
+VE_UBRRH:
+ .dw $ff05
+ .db "UBRRH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRRH
+XT_UBRRH:
+ .dw PFA_DOVARIABLE
+PFA_UBRRH:
+ .dw 64
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Low Byte
+VE_UBRRL:
+ .dw $ff05
+ .db "UBRRL",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRRL
+XT_UBRRL:
+ .dw PFA_DOVARIABLE
+PFA_UBRRL:
+ .dw 41
+
+.endif
+.if WANT_SPI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR:
+ .dw $ff04
+ .db "SPDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR
+XT_SPDR:
+ .dw PFA_DOVARIABLE
+PFA_SPDR:
+ .dw 47
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR:
+ .dw $ff04
+ .db "SPSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR
+XT_SPSR:
+ .dw PFA_DOVARIABLE
+PFA_SPSR:
+ .dw 46
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR:
+ .dw $ff04
+ .db "SPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR
+XT_SPCR:
+ .dw PFA_DOVARIABLE
+PFA_SPCR:
+ .dw 45
+
+.endif
+.if WANT_CPU == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw 95
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer
+VE_SP:
+ .dw $ff02
+ .db "SP"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SP
+XT_SP:
+ .dw PFA_DOVARIABLE
+PFA_SP:
+ .dw 93
+; ( -- addr ) System Constant
+; R( -- )
+; Extended MCU Control Register
+VE_EMCUCR:
+ .dw $ff06
+ .db "EMCUCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EMCUCR
+XT_EMCUCR:
+ .dw PFA_DOVARIABLE
+PFA_EMCUCR:
+ .dw 86
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw 85
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control And Status Register
+VE_MCUCSR:
+ .dw $ff06
+ .db "MCUCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCSR
+XT_MCUCSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCSR:
+ .dw 84
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Calibration Value
+VE_OSCCAL:
+ .dw $ff06
+ .db "OSCCAL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSCCAL
+XT_OSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_OSCCAL:
+ .dw 36
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control Register
+VE_SPMCR:
+ .dw $ff05
+ .db "SPMCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCR
+XT_SPMCR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCR:
+ .dw 87
+; ( -- addr ) System Constant
+; R( -- )
+; Special Function IO Register
+VE_SFIOR:
+ .dw $ff05
+ .db "SFIOR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SFIOR
+XT_SFIOR:
+ .dw PFA_DOVARIABLE
+PFA_SFIOR:
+ .dw 80
+
+.endif
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ( -- addr ) System Constant
+; R( -- )
+; General Interrupt Control Register
+VE_GICR:
+ .dw $ff04
+ .db "GICR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GICR
+XT_GICR:
+ .dw PFA_DOVARIABLE
+PFA_GICR:
+ .dw 91
+; ( -- addr ) System Constant
+; R( -- )
+; General Interrupt Flag Register
+VE_GIFR:
+ .dw $ff04
+ .db "GIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GIFR
+XT_GIFR:
+ .dw PFA_DOVARIABLE
+PFA_GIFR:
+ .dw 90
+
+.endif
+.if WANT_WATCHDOG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCR:
+ .dw $ff05
+ .db "WDTCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCR
+XT_WDTCR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCR:
+ .dw 65
+
+.endif
+.if WANT_TIMER_COUNTER_0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter 0 Control Register
+VE_TCCR0:
+ .dw $ff05
+ .db "TCCR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0
+XT_TCCR0:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0:
+ .dw 83
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter 0 Register
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw 82
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter 0 Output Compare Register
+VE_OCR0:
+ .dw $ff04
+ .db "OCR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0
+XT_OCR0:
+ .dw PFA_DOVARIABLE
+PFA_OCR0:
+ .dw 81
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Mask Register
+VE_TIMSK:
+ .dw $ff05
+ .db "TIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK
+XT_TIMSK:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK:
+ .dw 89
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Flag register
+VE_TIFR:
+ .dw $ff04
+ .db "TIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR
+XT_TIFR:
+ .dw PFA_DOVARIABLE
+PFA_TIFR:
+ .dw 88
+
+.endif
+.if WANT_TIMER_COUNTER_1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw 79
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw 78
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Bytes
+VE_TCNT1:
+ .dw $ff05
+ .db "TCNT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1
+XT_TCNT1:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1:
+ .dw 76
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register A Bytes
+VE_OCR1A:
+ .dw $ff05
+ .db "OCR1A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1A
+XT_OCR1A:
+ .dw PFA_DOVARIABLE
+PFA_OCR1A:
+ .dw 74
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register B Bytes
+VE_OCR1B:
+ .dw $ff05
+ .db "OCR1B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1B
+XT_OCR1B:
+ .dw PFA_DOVARIABLE
+PFA_OCR1B:
+ .dw 72
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Bytes
+VE_ICR1:
+ .dw $ff04
+ .db "ICR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1
+XT_ICR1:
+ .dw PFA_DOVARIABLE
+PFA_ICR1:
+ .dw 68
+
+.endif
+.if WANT_PORTA == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Register
+VE_PORTA:
+ .dw $ff05
+ .db "PORTA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTA
+XT_PORTA:
+ .dw PFA_DOVARIABLE
+PFA_PORTA:
+ .dw 59
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Direction Register
+VE_DDRA:
+ .dw $ff04
+ .db "DDRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRA
+XT_DDRA:
+ .dw PFA_DOVARIABLE
+PFA_DDRA:
+ .dw 58
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Input Pins
+VE_PINA:
+ .dw $ff04
+ .db "PINA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINA
+XT_PINA:
+ .dw PFA_DOVARIABLE
+PFA_PINA:
+ .dw 57
+
+.endif
+.if WANT_PORTB == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw 56
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw 55
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw 54
+
+.endif
+.if WANT_PORTC == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Register
+VE_PORTC:
+ .dw $ff05
+ .db "PORTC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTC
+XT_PORTC:
+ .dw PFA_DOVARIABLE
+PFA_PORTC:
+ .dw 53
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Direction Register
+VE_DDRC:
+ .dw $ff04
+ .db "DDRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRC
+XT_DDRC:
+ .dw PFA_DOVARIABLE
+PFA_DDRC:
+ .dw 52
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Input Pins
+VE_PINC:
+ .dw $ff04
+ .db "PINC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINC
+XT_PINC:
+ .dw PFA_DOVARIABLE
+PFA_PINC:
+ .dw 51
+
+.endif
+.if WANT_PORTD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw 50
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw 49
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw 48
+
+.endif
+.if WANT_PORTE == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port E Data Register
+VE_PORTE:
+ .dw $ff05
+ .db "PORTE",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTE
+XT_PORTE:
+ .dw PFA_DOVARIABLE
+PFA_PORTE:
+ .dw 39
+; ( -- addr ) System Constant
+; R( -- )
+; Port E Data Direction Register
+VE_DDRE:
+ .dw $ff04
+ .db "DDRE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRE
+XT_DDRE:
+ .dw PFA_DOVARIABLE
+PFA_DDRE:
+ .dw 38
+; ( -- addr ) System Constant
+; R( -- )
+; Port E Input Pins
+VE_PINE:
+ .dw $ff04
+ .db "PINE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINE
+XT_PINE:
+ .dw PFA_DOVARIABLE
+PFA_PINE:
+ .dw 37
+
+.endif
+.if WANT_EEPROM == 1
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Address Register Bytes
+VE_EEAR:
+ .dw $ff04
+ .db "EEAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEAR
+XT_EEAR:
+ .dw PFA_DOVARIABLE
+PFA_EEAR:
+ .dw 62
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw 61
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw 60
+
+.endif
diff --git a/amforth-6.5/avr8/devices/atmega8515/device.py b/amforth-6.5/avr8/devices/atmega8515/device.py
new file mode 100644
index 0000000..463fdb8
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega8515/device.py
@@ -0,0 +1,178 @@
+# Partname: ATmega8515
+# generated automatically, do not edit
+MCUREGS = {
+ 'ACSR': '&40',
+ 'ACSR_ACD': '$80',
+ 'ACSR_ACBG': '$40',
+ 'ACSR_ACO': '$20',
+ 'ACSR_ACI': '$10',
+ 'ACSR_ACIE': '$08',
+ 'ACSR_ACIC': '$04',
+ 'ACSR_ACIS': '$03',
+ 'UDR': '&44',
+ 'UCSRA': '&43',
+ 'UCSRA_RXC': '$80',
+ 'UCSRA_TXC': '$40',
+ 'UCSRA_UDRE': '$20',
+ 'UCSRA_FE': '$10',
+ 'UCSRA_DOR': '$08',
+ 'UCSRA_UPE': '$04',
+ 'UCSRA_U2X': '$02',
+ 'UCSRA_MPCM': '$01',
+ 'UCSRB': '&42',
+ 'UCSRB_RXCIE': '$80',
+ 'UCSRB_TXCIE': '$40',
+ 'UCSRB_UDRIE': '$20',
+ 'UCSRB_RXEN': '$10',
+ 'UCSRB_TXEN': '$08',
+ 'UCSRB_UCSZ2': '$04',
+ 'UCSRB_RXB8': '$02',
+ 'UCSRB_TXB8': '$01',
+ 'UCSRC': '&64',
+ 'UCSRC_URSEL': '$80',
+ 'UCSRC_UMSEL': '$40',
+ 'UCSRC_UPM': '$30',
+ 'UCSRC_USBS': '$08',
+ 'UCSRC_UCSZ': '$06',
+ 'UCSRC_UCPOL': '$01',
+ 'UBRRH': '&64',
+ 'UBRRH_URSEL': '$80',
+ 'UBRRH_UBRR1': '$0C',
+ 'UBRRH_UBRR': '$03',
+ 'UBRRL': '&41',
+ 'SPDR': '&47',
+ 'SPSR': '&46',
+ 'SPSR_SPIF': '$80',
+ 'SPSR_WCOL': '$40',
+ 'SPSR_SPI2X': '$01',
+ 'SPCR': '&45',
+ 'SPCR_SPIE': '$80',
+ 'SPCR_SPE': '$40',
+ 'SPCR_DORD': '$20',
+ 'SPCR_MSTR': '$10',
+ 'SPCR_CPOL': '$08',
+ 'SPCR_CPHA': '$04',
+ 'SPCR_SPR': '$03',
+ 'SREG': '&95',
+ 'SREG_I': '$80',
+ 'SREG_T': '$40',
+ 'SREG_H': '$20',
+ 'SREG_S': '$10',
+ 'SREG_V': '$08',
+ 'SREG_N': '$04',
+ 'SREG_Z': '$02',
+ 'SREG_C': '$01',
+ 'SP': '&93',
+ 'EMCUCR': '&86',
+ 'EMCUCR_SM0': '$80',
+ 'EMCUCR_SRL': '$70',
+ 'EMCUCR_SRW0': '$0C',
+ 'EMCUCR_SRW11': '$02',
+ 'EMCUCR_ISC2': '$01',
+ 'MCUCR': '&85',
+ 'MCUCR_SRE': '$80',
+ 'MCUCR_SRW10': '$40',
+ 'MCUCR_SE': '$20',
+ 'MCUCR_SM1': '$10',
+ 'MCUCR_ISC1': '$0C',
+ 'MCUCR_ISC0': '$03',
+ 'MCUCSR': '&84',
+ 'MCUCSR_SM2': '$20',
+ 'MCUCSR_WDRF': '$08',
+ 'MCUCSR_BORF': '$04',
+ 'MCUCSR_EXTRF': '$02',
+ 'MCUCSR_PORF': '$01',
+ 'OSCCAL': '&36',
+ 'SPMCR': '&87',
+ 'SPMCR_SPMIE': '$80',
+ 'SPMCR_RWWSB': '$40',
+ 'SPMCR_RWWSRE': '$10',
+ 'SPMCR_BLBSET': '$08',
+ 'SPMCR_PGWRT': '$04',
+ 'SPMCR_PGERS': '$02',
+ 'SPMCR_SPMEN': '$01',
+ 'SFIOR': '&80',
+ 'SFIOR_XMBK': '$40',
+ 'SFIOR_XMM': '$38',
+ 'SFIOR_PUD': '$04',
+ 'SFIOR_PSR10': '$01',
+ 'GICR': '&91',
+ 'GICR_INT': '$C0',
+ 'GICR_INT2': '$20',
+ 'GICR_IVSEL': '$02',
+ 'GICR_IVCE': '$01',
+ 'GIFR': '&90',
+ 'GIFR_INTF': '$C0',
+ 'GIFR_INTF2': '$20',
+ 'WDTCR': '&65',
+ 'WDTCR_WDCE': '$10',
+ 'WDTCR_WDE': '$08',
+ 'WDTCR_WDP': '$07',
+ 'TCCR0': '&83',
+ 'TCCR0_FOC0': '$80',
+ 'TCCR0_WGM00': '$40',
+ 'TCCR0_COM0': '$30',
+ 'TCCR0_WGM01': '$08',
+ 'TCCR0_CS0': '$07',
+ 'TCNT0': '&82',
+ 'OCR0': '&81',
+ 'TIMSK': '&89',
+ 'TIMSK_TOIE0': '$02',
+ 'TIMSK_OCIE0': '$01',
+ 'TIFR': '&88',
+ 'TIFR_TOV0': '$02',
+ 'TIFR_OCF0': '$01',
+ 'TCCR1A': '&79',
+ 'TCCR1A_COM1A': '$C0',
+ 'TCCR1A_COM1B': '$30',
+ 'TCCR1A_FOC1A': '$08',
+ 'TCCR1A_FOC1B': '$04',
+ 'TCCR1A_WGM1': '$03',
+ 'TCCR1B': '&78',
+ 'TCCR1B_ICNC1': '$80',
+ 'TCCR1B_ICES1': '$40',
+ 'TCCR1B_WGM1': '$18',
+ 'TCCR1B_CS1': '$07',
+ 'TCNT1': '&76',
+ 'OCR1A': '&74',
+ 'OCR1B': '&72',
+ 'ICR1': '&68',
+ 'PORTA': '&59',
+ 'DDRA': '&58',
+ 'PINA': '&57',
+ 'PORTB': '&56',
+ 'DDRB': '&55',
+ 'PINB': '&54',
+ 'PORTC': '&53',
+ 'DDRC': '&52',
+ 'PINC': '&51',
+ 'PORTD': '&50',
+ 'DDRD': '&49',
+ 'PIND': '&48',
+ 'PORTE': '&39',
+ 'DDRE': '&38',
+ 'PINE': '&37',
+ 'EEAR': '&62',
+ 'EEDR': '&61',
+ 'EECR': '&60',
+ 'EECR_EERIE': '$08',
+ 'EECR_EEMWE': '$04',
+ 'EECR_EEWE': '$02',
+ 'EECR_EERE': '$01',
+ 'INT0Addr': '1',
+ 'INT1Addr': '2',
+ 'TIMER1_CAPTAddr': '3',
+ 'TIMER1_COMPAAddr': '4',
+ 'TIMER1_COMPBAddr': '5',
+ 'TIMER1_OVFAddr': '6',
+ 'TIMER0_OVFAddr': '7',
+ 'SPI_STCAddr': '8',
+ 'USART_RXAddr': '9',
+ 'USART_UDREAddr': '10',
+ 'USART__TXAddr': '11',
+ 'ANA_COMPAddr': '12',
+ 'INT2Addr': '13',
+ 'TIMER0_COMPAddr': '14',
+ 'EE_RDYAddr': '15',
+ 'SPM_RDYAddr': '16'
+} \ No newline at end of file
diff --git a/amforth-6.5/avr8/devices/atmega8515/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega8515/words/no-jtag.asm
new file mode 100644
index 0000000..352a4bb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega8515/words/no-jtag.asm
@@ -0,0 +1,14 @@
+; ( -- )
+; ( -- )
+; MCU
+; disable jtag at runtime
+VE_NOJTAG:
+ .dw $FF05
+ .db "-jtag",0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOJTAG
+XT_NOJTAG:
+ .dw PFA_NOJTAG
+PFA_NOJTAG:
+
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega8515/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega8515/words/no-wdt.asm
new file mode 100644
index 0000000..4a12261
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega8515/words/no-wdt.asm
@@ -0,0 +1,22 @@
+; ( -- )
+; MCU
+; disable watch dog timer at runtime
+VE_NOWDT:
+ .dw $ff04
+ .db "-wdt"
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOWDT
+XT_NOWDT:
+ .dw PFA_NOWDT
+PFA_NOWDT:
+
+; Reset WDT
+ wdr
+; Write logical one to WDTOE and WDE
+ in_ temp1, WDTCR
+ ori temp1, (1<<WDTOE)|(1<<WDE)
+ out WDTCR, temp1
+; Turn off WDT
+ ldi temp1, (0<<WDE)
+ out_ WDTCR, temp1
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega8515/words/sleep.asm b/amforth-6.5/avr8/devices/atmega8515/words/sleep.asm
new file mode 100644
index 0000000..778fa32
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega8515/words/sleep.asm
@@ -0,0 +1,24 @@
+; ( mode -- )
+; MCU
+; put the controller into the specified sleep mode
+VE_SLEEP:
+ .dw $ff05
+ .db "sleep", 0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_SLEEP
+XT_SLEEP:
+ .dw PFA_SLEEP
+PFA_SLEEP:
+ andi tosl, 7 ; leave only legal mode bits
+ swap tosl ; move to correct location (bits 6-4, atmega32)
+ ori tosl, $80 ; set the SE bit (atmega32: bit 7, not bit 0)
+ out_ MCUCR, tosl ; set the sleep config (atmega32: MCUCR not SMCR)
+ sleep ; nighty-night
+;; the 4 lower bits of MCUCR should not be touched
+ in_ tosl, MCUCR
+ andi tosl, $0F
+ out_ MCUCR, tosl
+ ;clr tosl ; need to clean up the SMCR reg before we leave
+ ;out SMCR, tosl ; 0 protects against accidental sleeps
+ loadtos ; pop argument from stack
+ jmp DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega8535/atmega8535.frt b/amforth-6.5/avr8/devices/atmega8535/atmega8535.frt
new file mode 100644
index 0000000..beda947
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega8535/atmega8535.frt
@@ -0,0 +1,220 @@
+\ Partname: ATmega8535
+\ generated automatically
+
+\ AD_CONVERTER
+&39 constant ADMUX \ The ADC multiplexer Selection Register
+ $C0 constant ADMUX_REFS \ Reference Selection Bits
+ $20 constant ADMUX_ADLAR \ Left Adjust Result
+ $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
+&38 constant ADCSRA \ The ADC Control and Status register
+ $80 constant ADCSRA_ADEN \ ADC Enable
+ $40 constant ADCSRA_ADSC \ ADC Start Conversion
+ $20 constant ADCSRA_ADATE \ When this bit is written to one,the Timer/Counter2 prescaler will be reset.The bit will be cleared by hardware after the operation is performed.Writing a zero to this bit will have no effect.This bit will always be read as zero if Timer/Counter2 is clocked by the internal CPU clock.If this bit is written when Timer/Counter2 is operating in asynchronous mode,the bit will remain one until the prescaler has been reset.
+ $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
+ $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
+ $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
+&36 constant ADC \ ADC Data Register Bytes
+&80 constant SFIOR \ Special Function IO Register
+ $E0 constant SFIOR_ADTS \ ADC Auto Trigger Sources
+\ ANALOG_COMPARATOR
+&40 constant ACSR \ Analog Comparator Control And Status Register
+ $80 constant ACSR_ACD \ Analog Comparator Disable
+ $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
+ $20 constant ACSR_ACO \ Analog Compare Output
+ $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
+ $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
+ $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
+ $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
+\ TWI
+&32 constant TWBR \ TWI Bit Rate register
+&86 constant TWCR \ TWI Control Register
+ $80 constant TWCR_TWINT \ TWI Interrupt Flag
+ $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
+ $20 constant TWCR_TWSTA \ TWI Start Condition Bit
+ $10 constant TWCR_TWSTO \ TWI Stop Condition Bit
+ $08 constant TWCR_TWWC \ TWI Write Collition Flag
+ $04 constant TWCR_TWEN \ TWI Enable Bit
+ $01 constant TWCR_TWIE \ TWI Interrupt Enable
+&33 constant TWSR \ TWI Status Register
+ $F8 constant TWSR_TWS \ TWI Status
+ $03 constant TWSR_TWPS \ TWI Prescaler
+&35 constant TWDR \ TWI Data register
+&34 constant TWAR \ TWI (Slave) Address register
+ $FE constant TWAR_TWA \ TWI (Slave) Address register Bits
+ $01 constant TWAR_TWGCE \ TWI General Call Recognition Enable Bit
+\ USART
+&44 constant UDR \ USART I/O Data Register
+&43 constant UCSRA \ USART Control and Status Register A
+ $80 constant UCSRA_RXC \ USART Receive Complete
+ $40 constant UCSRA_TXC \ USART Transmitt Complete
+ $20 constant UCSRA_UDRE \ USART Data Register Empty
+ $10 constant UCSRA_FE \ Framing Error
+ $08 constant UCSRA_DOR \ Data overRun
+ $04 constant UCSRA_UPE \ Parity Error
+ $02 constant UCSRA_U2X \ Double the USART transmission speed
+ $01 constant UCSRA_MPCM \ Multi-processor Communication Mode
+&42 constant UCSRB \ USART Control and Status Register B
+ $80 constant UCSRB_RXCIE \ RX Complete Interrupt Enable
+ $40 constant UCSRB_TXCIE \ TX Complete Interrupt Enable
+ $20 constant UCSRB_UDRIE \ USART Data register Empty Interrupt Enable
+ $10 constant UCSRB_RXEN \ Receiver Enable
+ $08 constant UCSRB_TXEN \ Transmitter Enable
+ $04 constant UCSRB_UCSZ2 \ Character Size Bit 2
+ $02 constant UCSRB_RXB8 \ Receive Data Bit 8
+ $01 constant UCSRB_TXB8 \ Transmit Data Bit 8
+&64 constant UCSRC \ USART Control and Status Register C
+ $80 constant UCSRC_URSEL \ Register Select
+ $40 constant UCSRC_UMSEL \ USART Mode Select
+ $30 constant UCSRC_UPM \ Parity Mode Bits
+ $08 constant UCSRC_USBS \ Stop Bit Select
+ $06 constant UCSRC_UCSZ \ Character Size Bits
+ $01 constant UCSRC_UCPOL \ Clock Polarity
+&64 constant UBRRH \ USART Baud Rate Register High Byte
+ $80 constant UBRRH_URSEL \ Register Select
+ $0C constant UBRRH_UBRR1 \ USART Baud Rate Register bit 11
+ $03 constant UBRRH_UBRR \ USART Baud Rate Register bits
+&41 constant UBRRL \ USART Baud Rate Register Low Byte
+\ PORTA
+&59 constant PORTA \ Port A Data Register
+&58 constant DDRA \ Port A Data Direction Register
+&57 constant PINA \ Port A Input Pins
+\ PORTB
+&56 constant PORTB \ Port B Data Register
+&55 constant DDRB \ Port B Data Direction Register
+&54 constant PINB \ Port B Input Pins
+\ PORTC
+&53 constant PORTC \ Port C Data Register
+&52 constant DDRC \ Port C Data Direction Register
+&51 constant PINC \ Port C Input Pins
+\ PORTD
+&50 constant PORTD \ Port D Data Register
+&49 constant DDRD \ Port D Data Direction Register
+&48 constant PIND \ Port D Input Pins
+\ SPI
+&47 constant SPDR \ SPI Data Register
+&46 constant SPSR \ SPI Status Register
+ $80 constant SPSR_SPIF \ SPI Interrupt Flag
+ $40 constant SPSR_WCOL \ Write Collision Flag
+ $01 constant SPSR_SPI2X \ Double SPI Speed Bit
+&45 constant SPCR \ SPI Control Register
+ $80 constant SPCR_SPIE \ SPI Interrupt Enable
+ $40 constant SPCR_SPE \ SPI Enable
+ $20 constant SPCR_DORD \ Data Order
+ $10 constant SPCR_MSTR \ Master/Slave Select
+ $08 constant SPCR_CPOL \ Clock polarity
+ $04 constant SPCR_CPHA \ Clock Phase
+ $03 constant SPCR_SPR \ SPI Clock Rate Selects
+\ EEPROM
+&62 constant EEAR \ EEPROM Address Register Bytes
+&61 constant EEDR \ EEPROM Data Register
+&60 constant EECR \ EEPROM Control Register
+ $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
+ $04 constant EECR_EEMWE \ EEPROM Master Write Enable
+ $02 constant EECR_EEWE \ EEPROM Write Enable
+ $01 constant EECR_EERE \ EEPROM Read Enable
+\ TIMER_COUNTER_0
+&83 constant TCCR0 \ Timer/Counter Control Register
+ $80 constant TCCR0_FOC0 \ Force Output Compare
+ $40 constant TCCR0_WGM00 \ Waveform Generation Mode 0
+ $30 constant TCCR0_COM0 \ Compare Match Output Modes
+ $08 constant TCCR0_WGM01 \ Waveform Generation Mode 1
+ $07 constant TCCR0_CS0 \ Clock Selects
+&82 constant TCNT0 \ Timer/Counter Register
+&92 constant OCR0 \ Output Compare Register
+&89 constant TIMSK \ Timer/Counter Interrupt Mask Register
+ $02 constant TIMSK_OCIE0 \ Timer/Counter0 Output Compare Match Interrupt register
+ $01 constant TIMSK_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
+&88 constant TIFR \ Timer/Counter Interrupt Flag register
+ $02 constant TIFR_OCF0 \ Output Compare Flag 0
+ $01 constant TIFR_TOV0 \ Timer/Counter0 Overflow Flag
+\ TIMER_COUNTER_1
+&79 constant TCCR1A \ Timer/Counter1 Control Register A
+ $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
+ $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
+ $08 constant TCCR1A_FOC1A \ Force Output Compare 1A
+ $04 constant TCCR1A_FOC1B \ Force Output Compare 1B
+ $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
+&78 constant TCCR1B \ Timer/Counter1 Control Register B
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
+ $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
+&76 constant TCNT1 \ Timer/Counter1 Bytes
+&74 constant OCR1A \ Timer/Counter1 Output Compare Register Bytes
+&72 constant OCR1B \ Timer/Counter1 Output Compare Register Bytes
+&70 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
+\ TIMER_COUNTER_2
+&69 constant TCCR2 \ Timer/Counter2 Control Register
+ $80 constant TCCR2_FOC2 \ Force Output Compare
+ $40 constant TCCR2_WGM20 \ Waveform Genration Mode
+ $30 constant TCCR2_COM2 \ Compare Output Mode bits
+ $08 constant TCCR2_WGM21 \ Waveform Generation Mode
+ $07 constant TCCR2_CS2 \ Clock Select bits
+&68 constant TCNT2 \ Timer/Counter2
+&67 constant OCR2 \ Timer/Counter2 Output Compare Register
+&66 constant ASSR \ Asynchronous Status Register
+ $08 constant ASSR_AS2 \ Asynchronous Timer/counter2
+ $04 constant ASSR_TCN2UB \ Timer/Counter2 Update Busy
+ $02 constant ASSR_OCR2UB \ Output Compare Register2 Update Busy
+ $01 constant ASSR_TCR2UB \ Timer/counter Control Register2 Update Busy
+\ EXTERNAL_INTERRUPT
+&91 constant GICR \ General Interrupt Control Register
+ $C0 constant GICR_INT \ External Interrupt Request 1 Enable
+ $20 constant GICR_INT2 \ External Interrupt Request 2 Enable
+ $02 constant GICR_IVSEL \ Interrupt Vector Select
+ $01 constant GICR_IVCE \ Interrupt Vector Change Enable
+&90 constant GIFR \ General Interrupt Flag Register
+ $C0 constant GIFR_INTF \ External Interrupt Flags
+ $20 constant GIFR_INTF2 \ External Interrupt Flag 2
+&85 constant MCUCR \ General Interrupt Control Register
+ $0C constant MCUCR_ISC1 \ Interrupt Sense Control 1 Bits
+ $03 constant MCUCR_ISC0 \ Interrupt Sense Control 0 Bits
+&84 constant MCUCSR \ MCU Control And Status Register
+ $40 constant MCUCSR_ISC2 \ Interrupt Sense Control 2
+\ WATCHDOG
+&65 constant WDTCR \ Watchdog Timer Control Register
+ $10 constant WDTCR_WDCE \ Watchdog Change Enable
+ $08 constant WDTCR_WDE \ Watch Dog Enable
+ $07 constant WDTCR_WDP \ Watch Dog Timer Prescaler bits
+\ CPU
+&95 constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ $08 constant SREG_V \ Two's Complement Overflow Flag
+ $04 constant SREG_N \ Negative Flag
+ $02 constant SREG_Z \ Zero Flag
+ $01 constant SREG_C \ Carry Flag
+&93 constant SP \ Stack Pointer
+&81 constant OSCCAL \ Oscillator Calibration Value
+&87 constant SPMCR \
+ $80 constant SPMCR_SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCR_RWWSB \ Read-While-Write Section Busy
+ $10 constant SPMCR_RWWSRE \ Read-While-Write Section Read Enable
+ $08 constant SPMCR_BLBSET \ Boot Lock Bit Set
+ $04 constant SPMCR_PGWRT \ Page Write
+ $02 constant SPMCR_PGERS \ Page Erase
+ $01 constant SPMCR_SPMEN \ Store Program Memory Enable
+
+\ Interrupts
+&1 constant INT0Addr \ External Interrupt 0
+&2 constant INT1Addr \ External Interrupt 1
+&3 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
+&4 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
+&5 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+&6 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
+&7 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
+&8 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+&9 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
+&10 constant SPI_STCAddr \ SPI Serial Transfer Complete
+&11 constant USART_RXAddr \ USART, RX Complete
+&12 constant USART_UDREAddr \ USART Data Register Empty
+&13 constant USART_TXAddr \ USART, TX Complete
+&14 constant ADCAddr \ ADC Conversion Complete
+&15 constant EE_RDYAddr \ EEPROM Ready
+&16 constant ANA_COMPAddr \ Analog Comparator
+&17 constant TWIAddr \ Two-wire Serial Interface
+&18 constant INT2Addr \ External Interrupt Request 2
+&19 constant TIMER0_COMPAddr \ TimerCounter0 Compare Match
+&20 constant SPM_RDYAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/atmega8535/device.asm b/amforth-6.5/avr8/devices/atmega8535/device.asm
new file mode 100644
index 0000000..6768f1a
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega8535/device.asm
@@ -0,0 +1,100 @@
+; Partname: ATmega8535
+; generated automatically, do not edit
+
+.nolist
+ .include "m8535def.inc"
+.list
+
+.equ ramstart = 96
+.equ CELLSIZE = 2
+.macro readflashcell
+ lsl zl
+ rol zh
+ lpm @0, Z+
+ lpm @1, Z+
+.endmacro
+.macro writeflashcell
+ lsl zl
+ rol zh
+.endmacro
+.set WANT_AD_CONVERTER = 0
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_TWI = 0
+.set WANT_USART = 0
+.set WANT_PORTA = 0
+.set WANT_PORTB = 0
+.set WANT_PORTC = 0
+.set WANT_PORTD = 0
+.set WANT_SPI = 0
+.set WANT_EEPROM = 0
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_TIMER_COUNTER_2 = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_WATCHDOG = 0
+.set WANT_CPU = 0
+.equ intvecsize = 1 ; please verify; flash size: 8192 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.org 1
+ rcall isr ; External Interrupt 0
+.org 2
+ rcall isr ; External Interrupt 1
+.org 3
+ rcall isr ; Timer/Counter2 Compare Match
+.org 4
+ rcall isr ; Timer/Counter2 Overflow
+.org 5
+ rcall isr ; Timer/Counter1 Capture Event
+.org 6
+ rcall isr ; Timer/Counter1 Compare Match A
+.org 7
+ rcall isr ; Timer/Counter1 Compare Match B
+.org 8
+ rcall isr ; Timer/Counter1 Overflow
+.org 9
+ rcall isr ; Timer/Counter0 Overflow
+.org 10
+ rcall isr ; SPI Serial Transfer Complete
+.org 11
+ rcall isr ; USART, RX Complete
+.org 12
+ rcall isr ; USART Data Register Empty
+.org 13
+ rcall isr ; USART, TX Complete
+.org 14
+ rcall isr ; ADC Conversion Complete
+.org 15
+ rcall isr ; EEPROM Ready
+.org 16
+ rcall isr ; Analog Comparator
+.org 17
+ rcall isr ; Two-wire Serial Interface
+.org 18
+ rcall isr ; External Interrupt Request 2
+.org 19
+ rcall isr ; TimerCounter0 Compare Match
+.org 20
+ rcall isr ; Store Program Memory Read
+.equ INTVECTORS = 21
+.nooverlap
+
+; compatability layer (maybe empty)
+.equ SPMCSR = SPMCR
+.equ EEPE = EEWE
+.equ EEMPE = EEMWE
+
+; controller data area, environment query mcu-info
+mcu_info:
+mcu_ramsize:
+ .dw 512
+mcu_eepromsize:
+ .dw 512
+mcu_maxdp:
+ .dw 6144
+mcu_numints:
+ .dw 21
+mcu_name:
+ .dw 10
+ .db "ATmega8535"
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega8535/device.inc b/amforth-6.5/avr8/devices/atmega8535/device.inc
new file mode 100644
index 0000000..494fb0b
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega8535/device.inc
@@ -0,0 +1,747 @@
+; Partname: ATmega8535
+; generated automatically, no not edit
+
+.if WANT_AD_CONVERTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC multiplexer Selection Register
+VE_ADMUX:
+ .dw $ff05
+ .db "ADMUX",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADMUX
+XT_ADMUX:
+ .dw PFA_DOVARIABLE
+PFA_ADMUX:
+ .dw 39
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register
+VE_ADCSRA:
+ .dw $ff06
+ .db "ADCSRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRA
+XT_ADCSRA:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRA:
+ .dw 38
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register Bytes
+VE_ADC:
+ .dw $ff03
+ .db "ADC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADC
+XT_ADC:
+ .dw PFA_DOVARIABLE
+PFA_ADC:
+ .dw 36
+; ( -- addr ) System Constant
+; R( -- )
+; Special Function IO Register
+VE_SFIOR:
+ .dw $ff05
+ .db "SFIOR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SFIOR
+XT_SFIOR:
+ .dw PFA_DOVARIABLE
+PFA_SFIOR:
+ .dw 80
+
+.endif
+.if WANT_ANALOG_COMPARATOR == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Control And Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw 40
+
+.endif
+.if WANT_TWI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Bit Rate register
+VE_TWBR:
+ .dw $ff04
+ .db "TWBR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWBR
+XT_TWBR:
+ .dw PFA_DOVARIABLE
+PFA_TWBR:
+ .dw 32
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Control Register
+VE_TWCR:
+ .dw $ff04
+ .db "TWCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWCR
+XT_TWCR:
+ .dw PFA_DOVARIABLE
+PFA_TWCR:
+ .dw 86
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Status Register
+VE_TWSR:
+ .dw $ff04
+ .db "TWSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWSR
+XT_TWSR:
+ .dw PFA_DOVARIABLE
+PFA_TWSR:
+ .dw 33
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Data register
+VE_TWDR:
+ .dw $ff04
+ .db "TWDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWDR
+XT_TWDR:
+ .dw PFA_DOVARIABLE
+PFA_TWDR:
+ .dw 35
+; ( -- addr ) System Constant
+; R( -- )
+; TWI (Slave) Address register
+VE_TWAR:
+ .dw $ff04
+ .db "TWAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWAR
+XT_TWAR:
+ .dw PFA_DOVARIABLE
+PFA_TWAR:
+ .dw 34
+
+.endif
+.if WANT_USART == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR:
+ .dw $ff03
+ .db "UDR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR
+XT_UDR:
+ .dw PFA_DOVARIABLE
+PFA_UDR:
+ .dw 44
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSRA:
+ .dw $ff05
+ .db "UCSRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSRA
+XT_UCSRA:
+ .dw PFA_DOVARIABLE
+PFA_UCSRA:
+ .dw 43
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSRB:
+ .dw $ff05
+ .db "UCSRB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSRB
+XT_UCSRB:
+ .dw PFA_DOVARIABLE
+PFA_UCSRB:
+ .dw 42
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSRC:
+ .dw $ff05
+ .db "UCSRC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSRC
+XT_UCSRC:
+ .dw PFA_DOVARIABLE
+PFA_UCSRC:
+ .dw 64
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register High Byte
+VE_UBRRH:
+ .dw $ff05
+ .db "UBRRH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRRH
+XT_UBRRH:
+ .dw PFA_DOVARIABLE
+PFA_UBRRH:
+ .dw 64
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Low Byte
+VE_UBRRL:
+ .dw $ff05
+ .db "UBRRL",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRRL
+XT_UBRRL:
+ .dw PFA_DOVARIABLE
+PFA_UBRRL:
+ .dw 41
+
+.endif
+.if WANT_PORTA == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Register
+VE_PORTA:
+ .dw $ff05
+ .db "PORTA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTA
+XT_PORTA:
+ .dw PFA_DOVARIABLE
+PFA_PORTA:
+ .dw 59
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Direction Register
+VE_DDRA:
+ .dw $ff04
+ .db "DDRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRA
+XT_DDRA:
+ .dw PFA_DOVARIABLE
+PFA_DDRA:
+ .dw 58
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Input Pins
+VE_PINA:
+ .dw $ff04
+ .db "PINA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINA
+XT_PINA:
+ .dw PFA_DOVARIABLE
+PFA_PINA:
+ .dw 57
+
+.endif
+.if WANT_PORTB == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw 56
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw 55
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw 54
+
+.endif
+.if WANT_PORTC == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Register
+VE_PORTC:
+ .dw $ff05
+ .db "PORTC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTC
+XT_PORTC:
+ .dw PFA_DOVARIABLE
+PFA_PORTC:
+ .dw 53
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Direction Register
+VE_DDRC:
+ .dw $ff04
+ .db "DDRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRC
+XT_DDRC:
+ .dw PFA_DOVARIABLE
+PFA_DDRC:
+ .dw 52
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Input Pins
+VE_PINC:
+ .dw $ff04
+ .db "PINC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINC
+XT_PINC:
+ .dw PFA_DOVARIABLE
+PFA_PINC:
+ .dw 51
+
+.endif
+.if WANT_PORTD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw 50
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw 49
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw 48
+
+.endif
+.if WANT_SPI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR:
+ .dw $ff04
+ .db "SPDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR
+XT_SPDR:
+ .dw PFA_DOVARIABLE
+PFA_SPDR:
+ .dw 47
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR:
+ .dw $ff04
+ .db "SPSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR
+XT_SPSR:
+ .dw PFA_DOVARIABLE
+PFA_SPSR:
+ .dw 46
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR:
+ .dw $ff04
+ .db "SPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR
+XT_SPCR:
+ .dw PFA_DOVARIABLE
+PFA_SPCR:
+ .dw 45
+
+.endif
+.if WANT_EEPROM == 1
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Address Register Bytes
+VE_EEAR:
+ .dw $ff04
+ .db "EEAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEAR
+XT_EEAR:
+ .dw PFA_DOVARIABLE
+PFA_EEAR:
+ .dw 62
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw 61
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw 60
+
+.endif
+.if WANT_TIMER_COUNTER_0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register
+VE_TCCR0:
+ .dw $ff05
+ .db "TCCR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0
+XT_TCCR0:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0:
+ .dw 83
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Register
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw 82
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare Register
+VE_OCR0:
+ .dw $ff04
+ .db "OCR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0
+XT_OCR0:
+ .dw PFA_DOVARIABLE
+PFA_OCR0:
+ .dw 92
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Mask Register
+VE_TIMSK:
+ .dw $ff05
+ .db "TIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK
+XT_TIMSK:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK:
+ .dw 89
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Flag register
+VE_TIFR:
+ .dw $ff04
+ .db "TIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR
+XT_TIFR:
+ .dw PFA_DOVARIABLE
+PFA_TIFR:
+ .dw 88
+
+.endif
+.if WANT_TIMER_COUNTER_1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw 79
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw 78
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Bytes
+VE_TCNT1:
+ .dw $ff05
+ .db "TCNT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1
+XT_TCNT1:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1:
+ .dw 76
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register Bytes
+VE_OCR1A:
+ .dw $ff05
+ .db "OCR1A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1A
+XT_OCR1A:
+ .dw PFA_DOVARIABLE
+PFA_OCR1A:
+ .dw 74
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register Bytes
+VE_OCR1B:
+ .dw $ff05
+ .db "OCR1B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1B
+XT_OCR1B:
+ .dw PFA_DOVARIABLE
+PFA_OCR1B:
+ .dw 72
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Bytes
+VE_ICR1:
+ .dw $ff04
+ .db "ICR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1
+XT_ICR1:
+ .dw PFA_DOVARIABLE
+PFA_ICR1:
+ .dw 70
+
+.endif
+.if WANT_TIMER_COUNTER_2 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register
+VE_TCCR2:
+ .dw $ff05
+ .db "TCCR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2
+XT_TCCR2:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2:
+ .dw 69
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2
+VE_TCNT2:
+ .dw $ff05
+ .db "TCNT2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT2
+XT_TCNT2:
+ .dw PFA_DOVARIABLE
+PFA_TCNT2:
+ .dw 68
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register
+VE_OCR2:
+ .dw $ff04
+ .db "OCR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2
+XT_OCR2:
+ .dw PFA_DOVARIABLE
+PFA_OCR2:
+ .dw 67
+; ( -- addr ) System Constant
+; R( -- )
+; Asynchronous Status Register
+VE_ASSR:
+ .dw $ff04
+ .db "ASSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ASSR
+XT_ASSR:
+ .dw PFA_DOVARIABLE
+PFA_ASSR:
+ .dw 66
+
+.endif
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ( -- addr ) System Constant
+; R( -- )
+; General Interrupt Control Register
+VE_GICR:
+ .dw $ff04
+ .db "GICR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GICR
+XT_GICR:
+ .dw PFA_DOVARIABLE
+PFA_GICR:
+ .dw 91
+; ( -- addr ) System Constant
+; R( -- )
+; General Interrupt Flag Register
+VE_GIFR:
+ .dw $ff04
+ .db "GIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GIFR
+XT_GIFR:
+ .dw PFA_DOVARIABLE
+PFA_GIFR:
+ .dw 90
+; ( -- addr ) System Constant
+; R( -- )
+; General Interrupt Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw 85
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control And Status Register
+VE_MCUCSR:
+ .dw $ff06
+ .db "MCUCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCSR
+XT_MCUCSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCSR:
+ .dw 84
+
+.endif
+.if WANT_WATCHDOG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCR:
+ .dw $ff05
+ .db "WDTCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCR
+XT_WDTCR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCR:
+ .dw 65
+
+.endif
+.if WANT_CPU == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw 95
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer
+VE_SP:
+ .dw $ff02
+ .db "SP"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SP
+XT_SP:
+ .dw PFA_DOVARIABLE
+PFA_SP:
+ .dw 93
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Calibration Value
+VE_OSCCAL:
+ .dw $ff06
+ .db "OSCCAL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSCCAL
+XT_OSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_OSCCAL:
+ .dw 81
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_SPMCR:
+ .dw $ff05
+ .db "SPMCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCR
+XT_SPMCR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCR:
+ .dw 87
+
+.endif
diff --git a/amforth-6.5/avr8/devices/atmega8535/device.py b/amforth-6.5/avr8/devices/atmega8535/device.py
new file mode 100644
index 0000000..413668b
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega8535/device.py
@@ -0,0 +1,203 @@
+# Partname: ATmega8535
+# generated automatically, do not edit
+MCUREGS = {
+ 'ADMUX': '&39',
+ 'ADMUX_REFS': '$C0',
+ 'ADMUX_ADLAR': '$20',
+ 'ADMUX_MUX': '$1F',
+ 'ADCSRA': '&38',
+ 'ADCSRA_ADEN': '$80',
+ 'ADCSRA_ADSC': '$40',
+ 'ADCSRA_ADATE': '$20',
+ 'ADCSRA_ADIF': '$10',
+ 'ADCSRA_ADIE': '$08',
+ 'ADCSRA_ADPS': '$07',
+ 'ADC': '&36',
+ 'SFIOR': '&80',
+ 'SFIOR_ADTS': '$E0',
+ 'ACSR': '&40',
+ 'ACSR_ACD': '$80',
+ 'ACSR_ACBG': '$40',
+ 'ACSR_ACO': '$20',
+ 'ACSR_ACI': '$10',
+ 'ACSR_ACIE': '$08',
+ 'ACSR_ACIC': '$04',
+ 'ACSR_ACIS': '$03',
+ 'TWBR': '&32',
+ 'TWCR': '&86',
+ 'TWCR_TWINT': '$80',
+ 'TWCR_TWEA': '$40',
+ 'TWCR_TWSTA': '$20',
+ 'TWCR_TWSTO': '$10',
+ 'TWCR_TWWC': '$08',
+ 'TWCR_TWEN': '$04',
+ 'TWCR_TWIE': '$01',
+ 'TWSR': '&33',
+ 'TWSR_TWS': '$F8',
+ 'TWSR_TWPS': '$03',
+ 'TWDR': '&35',
+ 'TWAR': '&34',
+ 'TWAR_TWA': '$FE',
+ 'TWAR_TWGCE': '$01',
+ 'UDR': '&44',
+ 'UCSRA': '&43',
+ 'UCSRA_RXC': '$80',
+ 'UCSRA_TXC': '$40',
+ 'UCSRA_UDRE': '$20',
+ 'UCSRA_FE': '$10',
+ 'UCSRA_DOR': '$08',
+ 'UCSRA_UPE': '$04',
+ 'UCSRA_U2X': '$02',
+ 'UCSRA_MPCM': '$01',
+ 'UCSRB': '&42',
+ 'UCSRB_RXCIE': '$80',
+ 'UCSRB_TXCIE': '$40',
+ 'UCSRB_UDRIE': '$20',
+ 'UCSRB_RXEN': '$10',
+ 'UCSRB_TXEN': '$08',
+ 'UCSRB_UCSZ2': '$04',
+ 'UCSRB_RXB8': '$02',
+ 'UCSRB_TXB8': '$01',
+ 'UCSRC': '&64',
+ 'UCSRC_URSEL': '$80',
+ 'UCSRC_UMSEL': '$40',
+ 'UCSRC_UPM': '$30',
+ 'UCSRC_USBS': '$08',
+ 'UCSRC_UCSZ': '$06',
+ 'UCSRC_UCPOL': '$01',
+ 'UBRRH': '&64',
+ 'UBRRH_URSEL': '$80',
+ 'UBRRH_UBRR1': '$0C',
+ 'UBRRH_UBRR': '$03',
+ 'UBRRL': '&41',
+ 'PORTA': '&59',
+ 'DDRA': '&58',
+ 'PINA': '&57',
+ 'PORTB': '&56',
+ 'DDRB': '&55',
+ 'PINB': '&54',
+ 'PORTC': '&53',
+ 'DDRC': '&52',
+ 'PINC': '&51',
+ 'PORTD': '&50',
+ 'DDRD': '&49',
+ 'PIND': '&48',
+ 'SPDR': '&47',
+ 'SPSR': '&46',
+ 'SPSR_SPIF': '$80',
+ 'SPSR_WCOL': '$40',
+ 'SPSR_SPI2X': '$01',
+ 'SPCR': '&45',
+ 'SPCR_SPIE': '$80',
+ 'SPCR_SPE': '$40',
+ 'SPCR_DORD': '$20',
+ 'SPCR_MSTR': '$10',
+ 'SPCR_CPOL': '$08',
+ 'SPCR_CPHA': '$04',
+ 'SPCR_SPR': '$03',
+ 'EEAR': '&62',
+ 'EEDR': '&61',
+ 'EECR': '&60',
+ 'EECR_EERIE': '$08',
+ 'EECR_EEMWE': '$04',
+ 'EECR_EEWE': '$02',
+ 'EECR_EERE': '$01',
+ 'TCCR0': '&83',
+ 'TCCR0_FOC0': '$80',
+ 'TCCR0_WGM00': '$40',
+ 'TCCR0_COM0': '$30',
+ 'TCCR0_WGM01': '$08',
+ 'TCCR0_CS0': '$07',
+ 'TCNT0': '&82',
+ 'OCR0': '&92',
+ 'TIMSK': '&89',
+ 'TIMSK_OCIE0': '$02',
+ 'TIMSK_TOIE0': '$01',
+ 'TIFR': '&88',
+ 'TIFR_OCF0': '$02',
+ 'TIFR_TOV0': '$01',
+ 'TCCR1A': '&79',
+ 'TCCR1A_COM1A': '$C0',
+ 'TCCR1A_COM1B': '$30',
+ 'TCCR1A_FOC1A': '$08',
+ 'TCCR1A_FOC1B': '$04',
+ 'TCCR1A_WGM1': '$03',
+ 'TCCR1B': '&78',
+ 'TCCR1B_ICNC1': '$80',
+ 'TCCR1B_ICES1': '$40',
+ 'TCCR1B_WGM1': '$18',
+ 'TCCR1B_CS1': '$07',
+ 'TCNT1': '&76',
+ 'OCR1A': '&74',
+ 'OCR1B': '&72',
+ 'ICR1': '&70',
+ 'TCCR2': '&69',
+ 'TCCR2_FOC2': '$80',
+ 'TCCR2_WGM20': '$40',
+ 'TCCR2_COM2': '$30',
+ 'TCCR2_WGM21': '$08',
+ 'TCCR2_CS2': '$07',
+ 'TCNT2': '&68',
+ 'OCR2': '&67',
+ 'ASSR': '&66',
+ 'ASSR_AS2': '$08',
+ 'ASSR_TCN2UB': '$04',
+ 'ASSR_OCR2UB': '$02',
+ 'ASSR_TCR2UB': '$01',
+ 'GICR': '&91',
+ 'GICR_INT': '$C0',
+ 'GICR_INT2': '$20',
+ 'GICR_IVSEL': '$02',
+ 'GICR_IVCE': '$01',
+ 'GIFR': '&90',
+ 'GIFR_INTF': '$C0',
+ 'GIFR_INTF2': '$20',
+ 'MCUCR': '&85',
+ 'MCUCR_ISC1': '$0C',
+ 'MCUCR_ISC0': '$03',
+ 'MCUCSR': '&84',
+ 'MCUCSR_ISC2': '$40',
+ 'WDTCR': '&65',
+ 'WDTCR_WDCE': '$10',
+ 'WDTCR_WDE': '$08',
+ 'WDTCR_WDP': '$07',
+ 'SREG': '&95',
+ 'SREG_I': '$80',
+ 'SREG_T': '$40',
+ 'SREG_H': '$20',
+ 'SREG_S': '$10',
+ 'SREG_V': '$08',
+ 'SREG_N': '$04',
+ 'SREG_Z': '$02',
+ 'SREG_C': '$01',
+ 'SP': '&93',
+ 'OSCCAL': '&81',
+ 'SPMCR': '&87',
+ 'SPMCR_SPMIE': '$80',
+ 'SPMCR_RWWSB': '$40',
+ 'SPMCR_RWWSRE': '$10',
+ 'SPMCR_BLBSET': '$08',
+ 'SPMCR_PGWRT': '$04',
+ 'SPMCR_PGERS': '$02',
+ 'SPMCR_SPMEN': '$01',
+ 'INT0Addr': '1',
+ 'INT1Addr': '2',
+ 'TIMER2_COMPAddr': '3',
+ 'TIMER2_OVFAddr': '4',
+ 'TIMER1_CAPTAddr': '5',
+ 'TIMER1_COMPAAddr': '6',
+ 'TIMER1_COMPBAddr': '7',
+ 'TIMER1_OVFAddr': '8',
+ 'TIMER0_OVFAddr': '9',
+ 'SPI_STCAddr': '10',
+ 'USART_RXAddr': '11',
+ 'USART_UDREAddr': '12',
+ 'USART_TXAddr': '13',
+ 'ADCAddr': '14',
+ 'EE_RDYAddr': '15',
+ 'ANA_COMPAddr': '16',
+ 'TWIAddr': '17',
+ 'INT2Addr': '18',
+ 'TIMER0_COMPAddr': '19',
+ 'SPM_RDYAddr': '20'
+} \ No newline at end of file
diff --git a/amforth-6.5/avr8/devices/atmega8535/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega8535/words/no-jtag.asm
new file mode 100644
index 0000000..352a4bb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega8535/words/no-jtag.asm
@@ -0,0 +1,14 @@
+; ( -- )
+; ( -- )
+; MCU
+; disable jtag at runtime
+VE_NOJTAG:
+ .dw $FF05
+ .db "-jtag",0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOJTAG
+XT_NOJTAG:
+ .dw PFA_NOJTAG
+PFA_NOJTAG:
+
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega8535/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega8535/words/no-wdt.asm
new file mode 100644
index 0000000..4a12261
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega8535/words/no-wdt.asm
@@ -0,0 +1,22 @@
+; ( -- )
+; MCU
+; disable watch dog timer at runtime
+VE_NOWDT:
+ .dw $ff04
+ .db "-wdt"
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOWDT
+XT_NOWDT:
+ .dw PFA_NOWDT
+PFA_NOWDT:
+
+; Reset WDT
+ wdr
+; Write logical one to WDTOE and WDE
+ in_ temp1, WDTCR
+ ori temp1, (1<<WDTOE)|(1<<WDE)
+ out WDTCR, temp1
+; Turn off WDT
+ ldi temp1, (0<<WDE)
+ out_ WDTCR, temp1
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega8535/words/sleep.asm b/amforth-6.5/avr8/devices/atmega8535/words/sleep.asm
new file mode 100644
index 0000000..778fa32
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega8535/words/sleep.asm
@@ -0,0 +1,24 @@
+; ( mode -- )
+; MCU
+; put the controller into the specified sleep mode
+VE_SLEEP:
+ .dw $ff05
+ .db "sleep", 0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_SLEEP
+XT_SLEEP:
+ .dw PFA_SLEEP
+PFA_SLEEP:
+ andi tosl, 7 ; leave only legal mode bits
+ swap tosl ; move to correct location (bits 6-4, atmega32)
+ ori tosl, $80 ; set the SE bit (atmega32: bit 7, not bit 0)
+ out_ MCUCR, tosl ; set the sleep config (atmega32: MCUCR not SMCR)
+ sleep ; nighty-night
+;; the 4 lower bits of MCUCR should not be touched
+ in_ tosl, MCUCR
+ andi tosl, $0F
+ out_ MCUCR, tosl
+ ;clr tosl ; need to clean up the SMCR reg before we leave
+ ;out SMCR, tosl ; 0 protects against accidental sleeps
+ loadtos ; pop argument from stack
+ jmp DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega88/atmega88.frt b/amforth-6.5/avr8/devices/atmega88/atmega88.frt
new file mode 100644
index 0000000..2034063
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega88/atmega88.frt
@@ -0,0 +1,297 @@
+\ Partname: ATmega88
+\ generated automatically
+
+\ USART0
+&198 constant UDR0 \ USART I/O Data Register
+&192 constant UCSR0A \ USART Control and Status Register A
+ $80 constant UCSR0A_RXC0 \ USART Receive Complete
+ $40 constant UCSR0A_TXC0 \ USART Transmitt Complete
+ $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
+ $10 constant UCSR0A_FE0 \ Framing Error
+ $08 constant UCSR0A_DOR0 \ Data overRun
+ $04 constant UCSR0A_UPE0 \ Parity Error
+ $02 constant UCSR0A_U2X0 \ Double the USART transmission speed
+ $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
+&193 constant UCSR0B \ USART Control and Status Register B
+ $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
+ $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
+ $20 constant UCSR0B_UDRIE0 \ USART Data register Empty Interrupt Enable
+ $10 constant UCSR0B_RXEN0 \ Receiver Enable
+ $08 constant UCSR0B_TXEN0 \ Transmitter Enable
+ $04 constant UCSR0B_UCSZ02 \ Character Size
+ $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
+ $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
+&194 constant UCSR0C \ USART Control and Status Register C
+ $C0 constant UCSR0C_UMSEL0 \ USART Mode Select
+ $30 constant UCSR0C_UPM0 \ Parity Mode Bits
+ $08 constant UCSR0C_USBS0 \ Stop Bit Select
+ $06 constant UCSR0C_UCSZ0 \ Character Size
+ $01 constant UCSR0C_UCPOL0 \ Clock Polarity
+&196 constant UBRR0 \ USART Baud Rate Register Bytes
+\ TWI
+&189 constant TWAMR \ TWI (Slave) Address Mask Register
+ $FE constant TWAMR_TWAM \
+&184 constant TWBR \ TWI Bit Rate register
+&188 constant TWCR \ TWI Control Register
+ $80 constant TWCR_TWINT \ TWI Interrupt Flag
+ $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
+ $20 constant TWCR_TWSTA \ TWI Start Condition Bit
+ $10 constant TWCR_TWSTO \ TWI Stop Condition Bit
+ $08 constant TWCR_TWWC \ TWI Write Collition Flag
+ $04 constant TWCR_TWEN \ TWI Enable Bit
+ $01 constant TWCR_TWIE \ TWI Interrupt Enable
+&185 constant TWSR \ TWI Status Register
+ $F8 constant TWSR_TWS \ TWI Status
+ $03 constant TWSR_TWPS \ TWI Prescaler
+&187 constant TWDR \ TWI Data register
+&186 constant TWAR \ TWI (Slave) Address register
+ $FE constant TWAR_TWA \ TWI (Slave) Address register Bits
+ $01 constant TWAR_TWGCE \ TWI General Call Recognition Enable Bit
+\ TIMER_COUNTER_1
+&111 constant TIMSK1 \ Timer/Counter Interrupt Mask Register
+ $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
+ $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output CompareB Match Interrupt Enable
+ $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output CompareA Match Interrupt Enable
+ $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
+&54 constant TIFR1 \ Timer/Counter Interrupt Flag register
+ $20 constant TIFR1_ICF1 \ Input Capture Flag 1
+ $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
+ $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
+ $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
+&128 constant TCCR1A \ Timer/Counter1 Control Register A
+ $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
+ $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
+ $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
+&129 constant TCCR1B \ Timer/Counter1 Control Register B
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
+ $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
+&130 constant TCCR1C \ Timer/Counter1 Control Register C
+ $80 constant TCCR1C_FOC1A \
+ $40 constant TCCR1C_FOC1B \
+&132 constant TCNT1 \ Timer/Counter1 Bytes
+&136 constant OCR1A \ Timer/Counter1 Output Compare Register Bytes
+&138 constant OCR1B \ Timer/Counter1 Output Compare Register Bytes
+&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
+&67 constant GTCCR \ General Timer/Counter Control Register
+ $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
+ $01 constant GTCCR_PSRSYNC \ Prescaler Reset Timer/Counter1 and Timer/Counter0
+\ TIMER_COUNTER_2
+&112 constant TIMSK2 \ Timer/Counter Interrupt Mask register
+ $04 constant TIMSK2_OCIE2B \ Timer/Counter2 Output Compare Match B Interrupt Enable
+ $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match A Interrupt Enable
+ $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
+&55 constant TIFR2 \ Timer/Counter Interrupt Flag Register
+ $04 constant TIFR2_OCF2B \ Output Compare Flag 2B
+ $02 constant TIFR2_OCF2A \ Output Compare Flag 2A
+ $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
+&176 constant TCCR2A \ Timer/Counter2 Control Register A
+ $C0 constant TCCR2A_COM2A \ Compare Output Mode bits
+ $30 constant TCCR2A_COM2B \ Compare Output Mode bits
+ $03 constant TCCR2A_WGM2 \ Waveform Genration Mode
+&177 constant TCCR2B \ Timer/Counter2 Control Register B
+ $80 constant TCCR2B_FOC2A \ Force Output Compare A
+ $40 constant TCCR2B_FOC2B \ Force Output Compare B
+ $08 constant TCCR2B_WGM22 \ Waveform Generation Mode
+ $07 constant TCCR2B_CS2 \ Clock Select bits
+&178 constant TCNT2 \ Timer/Counter2
+&180 constant OCR2B \ Timer/Counter2 Output Compare Register B
+&179 constant OCR2A \ Timer/Counter2 Output Compare Register A
+&182 constant ASSR \ Asynchronous Status Register
+ $40 constant ASSR_EXCLK \ Enable External Clock Input
+ $20 constant ASSR_AS2 \ Asynchronous Timer/Counter2
+ $10 constant ASSR_TCN2UB \ Timer/Counter2 Update Busy
+ $08 constant ASSR_OCR2AUB \ Output Compare Register2 Update Busy
+ $04 constant ASSR_OCR2BUB \ Output Compare Register 2 Update Busy
+ $02 constant ASSR_TCR2AUB \ Timer/Counter Control Register2 Update Busy
+ $01 constant ASSR_TCR2BUB \ Timer/Counter Control Register2 Update Busy
+\ AD_CONVERTER
+&124 constant ADMUX \ The ADC multiplexer Selection Register
+ $C0 constant ADMUX_REFS \ Reference Selection Bits
+ $20 constant ADMUX_ADLAR \ Left Adjust Result
+ $0F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
+&120 constant ADC \ ADC Data Register Bytes
+&122 constant ADCSRA \ The ADC Control and Status register A
+ $80 constant ADCSRA_ADEN \ ADC Enable
+ $40 constant ADCSRA_ADSC \ ADC Start Conversion
+ $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
+ $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
+ $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
+ $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
+&123 constant ADCSRB \ The ADC Control and Status register B
+ $40 constant ADCSRB_ACME \
+ $07 constant ADCSRB_ADTS \ ADC Auto Trigger Source bits
+&126 constant DIDR0 \ Digital Input Disable Register
+ $20 constant DIDR0_ADC5D \
+ $10 constant DIDR0_ADC4D \
+ $08 constant DIDR0_ADC3D \
+ $04 constant DIDR0_ADC2D \
+ $02 constant DIDR0_ADC1D \
+ $01 constant DIDR0_ADC0D \
+\ ANALOG_COMPARATOR
+&80 constant ACSR \ Analog Comparator Control And Status Register
+ $80 constant ACSR_ACD \ Analog Comparator Disable
+ $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
+ $20 constant ACSR_ACO \ Analog Compare Output
+ $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
+ $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
+ $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
+ $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
+&127 constant DIDR1 \ Digital Input Disable Register 1
+ $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
+ $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
+\ PORTB
+&37 constant PORTB \ Port B Data Register
+&36 constant DDRB \ Port B Data Direction Register
+&35 constant PINB \ Port B Input Pins
+\ PORTC
+&40 constant PORTC \ Port C Data Register
+&39 constant DDRC \ Port C Data Direction Register
+&38 constant PINC \ Port C Input Pins
+\ PORTD
+&43 constant PORTD \ Port D Data Register
+&42 constant DDRD \ Port D Data Direction Register
+&41 constant PIND \ Port D Input Pins
+\ TIMER_COUNTER_0
+&72 constant OCR0B \ Timer/Counter0 Output Compare Register
+&71 constant OCR0A \ Timer/Counter0 Output Compare Register
+&70 constant TCNT0 \ Timer/Counter0
+&69 constant TCCR0B \ Timer/Counter Control Register B
+ $80 constant TCCR0B_FOC0A \ Force Output Compare A
+ $40 constant TCCR0B_FOC0B \ Force Output Compare B
+ $08 constant TCCR0B_WGM02 \
+ $07 constant TCCR0B_CS0 \ Clock Select
+&68 constant TCCR0A \ Timer/Counter Control Register A
+ $C0 constant TCCR0A_COM0A \ Compare Output Mode, Phase Correct PWM Mode
+ $30 constant TCCR0A_COM0B \ Compare Output Mode, Fast PWm
+ $03 constant TCCR0A_WGM0 \ Waveform Generation Mode
+&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
+ $04 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare Match B Interrupt Enable
+ $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match A Interrupt Enable
+ $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
+&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
+ $04 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare Flag 0B
+ $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0A
+ $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
+\ EXTERNAL_INTERRUPT
+&105 constant EICRA \ External Interrupt Control Register
+ $0C constant EICRA_ISC1 \ External Interrupt Sense Control 1 Bits
+ $03 constant EICRA_ISC0 \ External Interrupt Sense Control 0 Bits
+&61 constant EIMSK \ External Interrupt Mask Register
+ $03 constant EIMSK_INT \ External Interrupt Request 1 Enable
+&60 constant EIFR \ External Interrupt Flag Register
+ $03 constant EIFR_INTF \ External Interrupt Flags
+&104 constant PCICR \ Pin Change Interrupt Control Register
+ $07 constant PCICR_PCIE \ Pin Change Interrupt Enables
+&109 constant PCMSK2 \ Pin Change Mask Register 2
+ $FF constant PCMSK2_PCINT \ Pin Change Enable Masks
+&108 constant PCMSK1 \ Pin Change Mask Register 1
+ $7F constant PCMSK1_PCINT \ Pin Change Enable Masks
+&107 constant PCMSK0 \ Pin Change Mask Register 0
+ $FF constant PCMSK0_PCINT \ Pin Change Enable Masks
+&59 constant PCIFR \ Pin Change Interrupt Flag Register
+ $07 constant PCIFR_PCIF \ Pin Change Interrupt Flags
+\ SPI
+&78 constant SPDR \ SPI Data Register
+&77 constant SPSR \ SPI Status Register
+ $80 constant SPSR_SPIF \ SPI Interrupt Flag
+ $40 constant SPSR_WCOL \ Write Collision Flag
+ $01 constant SPSR_SPI2X \ Double SPI Speed Bit
+&76 constant SPCR \ SPI Control Register
+ $80 constant SPCR_SPIE \ SPI Interrupt Enable
+ $40 constant SPCR_SPE \ SPI Enable
+ $20 constant SPCR_DORD \ Data Order
+ $10 constant SPCR_MSTR \ Master/Slave Select
+ $08 constant SPCR_CPOL \ Clock polarity
+ $04 constant SPCR_CPHA \ Clock Phase
+ $03 constant SPCR_SPR \ SPI Clock Rate Selects
+\ CPU
+&100 constant PRR \ Power Reduction Register
+ $80 constant PRR_PRTWI \ Power Reduction TWI
+ $40 constant PRR_PRTIM2 \ Power Reduction Timer/Counter2
+ $20 constant PRR_PRTIM0 \ Power Reduction Timer/Counter0
+ $08 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
+ $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
+ $02 constant PRR_PRUSART0 \ Power Reduction USART
+ $01 constant PRR_PRADC \ Power Reduction ADC
+&102 constant OSCCAL \ Oscillator Calibration Value
+&97 constant CLKPR \ Clock Prescale Register
+ $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable
+ $0F constant CLKPR_CLKPS \ Clock Prescaler Select Bits
+&95 constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ $08 constant SREG_V \ Two's Complement Overflow Flag
+ $04 constant SREG_N \ Negative Flag
+ $02 constant SREG_Z \ Zero Flag
+ $01 constant SREG_C \ Carry Flag
+&93 constant SP \ Stack Pointer
+&87 constant SPMCSR \ Store Program Memory Control and Status Register
+ $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCSR_RWWSB \ Read-While-Write Section Busy
+ $10 constant SPMCSR_RWWSRE \ Read-While-Write section read enable
+ $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
+ $04 constant SPMCSR_PGWRT \ Page Write
+ $02 constant SPMCSR_PGERS \ Page Erase
+ $01 constant SPMCSR_SELFPRGEN \ Self Programming Enable
+&85 constant MCUCR \ MCU Control Register
+ $10 constant MCUCR_PUD \
+ $02 constant MCUCR_IVSEL \
+ $01 constant MCUCR_IVCE \
+&84 constant MCUSR \ MCU Status Register
+ $08 constant MCUSR_WDRF \ Watchdog Reset Flag
+ $04 constant MCUSR_BORF \ Brown-out Reset Flag
+ $02 constant MCUSR_EXTRF \ External Reset Flag
+ $01 constant MCUSR_PORF \ Power-on reset flag
+&83 constant SMCR \
+ $0E constant SMCR_SM \
+ $01 constant SMCR_SE \
+&75 constant GPIOR2 \ General Purpose I/O Register 2
+&74 constant GPIOR1 \ General Purpose I/O Register 1
+&62 constant GPIOR0 \ General Purpose I/O Register 0
+\ WATCHDOG
+&96 constant WDTCSR \ Watchdog Timer Control Register
+ $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Flag
+ $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Enable
+ $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
+ $10 constant WDTCSR_WDCE \ Watchdog Change Enable
+ $08 constant WDTCSR_WDE \ Watch Dog Enable
+\ EEPROM
+&65 constant EEAR \ EEPROM Address Register Bytes
+&64 constant EEDR \ EEPROM Data Register
+&63 constant EECR \ EEPROM Control Register
+ $30 constant EECR_EEPM \ EEPROM Programming Mode Bits
+ $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
+ $04 constant EECR_EEMPE \ EEPROM Master Write Enable
+ $02 constant EECR_EEPE \ EEPROM Write Enable
+ $01 constant EECR_EERE \ EEPROM Read Enable
+
+\ Interrupts
+&1 constant INT0Addr \ External Interrupt Request 0
+&2 constant INT1Addr \ External Interrupt Request 1
+&3 constant PCINT0Addr \ Pin Change Interrupt Request 0
+&4 constant PCINT1Addr \ Pin Change Interrupt Request 0
+&5 constant PCINT2Addr \ Pin Change Interrupt Request 1
+&6 constant WDTAddr \ Watchdog Time-out Interrupt
+&7 constant TIMER2_COMPAAddr \ Timer/Counter2 Compare Match A
+&8 constant TIMER2_COMPBAddr \ Timer/Counter2 Compare Match A
+&9 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
+&10 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+&11 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
+&12 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
+&13 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+&14 constant TIMER0_COMPAAddr \ TimerCounter0 Compare Match A
+&15 constant TIMER0_COMPBAddr \ TimerCounter0 Compare Match B
+&16 constant TIMER0_OVFAddr \ Timer/Couner0 Overflow
+&17 constant SPI__STCAddr \ SPI Serial Transfer Complete
+&18 constant USART__RXAddr \ USART Rx Complete
+&19 constant USART__UDREAddr \ USART, Data Register Empty
+&20 constant USART__TXAddr \ USART Tx Complete
+&21 constant ADCAddr \ ADC Conversion Complete
+&22 constant EE_READYAddr \ EEPROM Ready
+&23 constant ANALOG_COMPAddr \ Analog Comparator
+&24 constant TWIAddr \ Two-wire Serial Interface
+&25 constant SPM_ReadyAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/atmega88/device.asm b/amforth-6.5/avr8/devices/atmega88/device.asm
new file mode 100644
index 0000000..fe6d207
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega88/device.asm
@@ -0,0 +1,107 @@
+; Partname: ATmega88
+; generated automatically, do not edit
+
+.nolist
+ .include "m88def.inc"
+.list
+
+.equ ramstart = 256
+.equ CELLSIZE = 2
+.macro readflashcell
+ lsl zl
+ rol zh
+ lpm @0, Z+
+ lpm @1, Z+
+.endmacro
+.macro writeflashcell
+ lsl zl
+ rol zh
+.endmacro
+.set WANT_USART0 = 0
+.set WANT_TWI = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_TIMER_COUNTER_2 = 0
+.set WANT_AD_CONVERTER = 0
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_PORTB = 0
+.set WANT_PORTC = 0
+.set WANT_PORTD = 0
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_SPI = 0
+.set WANT_CPU = 0
+.set WANT_WATCHDOG = 0
+.set WANT_EEPROM = 0
+.equ intvecsize = 1 ; please verify; flash size: 8192 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.org 1
+ rcall isr ; External Interrupt Request 0
+.org 2
+ rcall isr ; External Interrupt Request 1
+.org 3
+ rcall isr ; Pin Change Interrupt Request 0
+.org 4
+ rcall isr ; Pin Change Interrupt Request 0
+.org 5
+ rcall isr ; Pin Change Interrupt Request 1
+.org 6
+ rcall isr ; Watchdog Time-out Interrupt
+.org 7
+ rcall isr ; Timer/Counter2 Compare Match A
+.org 8
+ rcall isr ; Timer/Counter2 Compare Match A
+.org 9
+ rcall isr ; Timer/Counter2 Overflow
+.org 10
+ rcall isr ; Timer/Counter1 Capture Event
+.org 11
+ rcall isr ; Timer/Counter1 Compare Match A
+.org 12
+ rcall isr ; Timer/Counter1 Compare Match B
+.org 13
+ rcall isr ; Timer/Counter1 Overflow
+.org 14
+ rcall isr ; TimerCounter0 Compare Match A
+.org 15
+ rcall isr ; TimerCounter0 Compare Match B
+.org 16
+ rcall isr ; Timer/Couner0 Overflow
+.org 17
+ rcall isr ; SPI Serial Transfer Complete
+.org 18
+ rcall isr ; USART Rx Complete
+.org 19
+ rcall isr ; USART, Data Register Empty
+.org 20
+ rcall isr ; USART Tx Complete
+.org 21
+ rcall isr ; ADC Conversion Complete
+.org 22
+ rcall isr ; EEPROM Ready
+.org 23
+ rcall isr ; Analog Comparator
+.org 24
+ rcall isr ; Two-wire Serial Interface
+.org 25
+ rcall isr ; Store Program Memory Read
+.equ INTVECTORS = 26
+.nooverlap
+
+; compatability layer (maybe empty)
+.equ SPMEN = SELFPRGEN
+
+; controller data area, environment query mcu-info
+mcu_info:
+mcu_ramsize:
+ .dw 1024
+mcu_eepromsize:
+ .dw 512
+mcu_maxdp:
+ .dw 6144
+mcu_numints:
+ .dw 26
+mcu_name:
+ .dw 8
+ .db "ATmega88"
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega88/device.inc b/amforth-6.5/avr8/devices/atmega88/device.inc
new file mode 100644
index 0000000..32d6fca
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega88/device.inc
@@ -0,0 +1,996 @@
+; Partname: ATmega88
+; generated automatically, no not edit
+
+.if WANT_USART0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR0:
+ .dw $ff04
+ .db "UDR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR0
+XT_UDR0:
+ .dw PFA_DOVARIABLE
+PFA_UDR0:
+ .dw 198
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR0A:
+ .dw $ff06
+ .db "UCSR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0A
+XT_UCSR0A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0A:
+ .dw 192
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR0B:
+ .dw $ff06
+ .db "UCSR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0B
+XT_UCSR0B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0B:
+ .dw 193
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR0C:
+ .dw $ff06
+ .db "UCSR0C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0C
+XT_UCSR0C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0C:
+ .dw 194
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Bytes
+VE_UBRR0:
+ .dw $ff05
+ .db "UBRR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR0
+XT_UBRR0:
+ .dw PFA_DOVARIABLE
+PFA_UBRR0:
+ .dw 196
+
+.endif
+.if WANT_TWI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; TWI (Slave) Address Mask Register
+VE_TWAMR:
+ .dw $ff05
+ .db "TWAMR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWAMR
+XT_TWAMR:
+ .dw PFA_DOVARIABLE
+PFA_TWAMR:
+ .dw 189
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Bit Rate register
+VE_TWBR:
+ .dw $ff04
+ .db "TWBR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWBR
+XT_TWBR:
+ .dw PFA_DOVARIABLE
+PFA_TWBR:
+ .dw 184
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Control Register
+VE_TWCR:
+ .dw $ff04
+ .db "TWCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWCR
+XT_TWCR:
+ .dw PFA_DOVARIABLE
+PFA_TWCR:
+ .dw 188
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Status Register
+VE_TWSR:
+ .dw $ff04
+ .db "TWSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWSR
+XT_TWSR:
+ .dw PFA_DOVARIABLE
+PFA_TWSR:
+ .dw 185
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Data register
+VE_TWDR:
+ .dw $ff04
+ .db "TWDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWDR
+XT_TWDR:
+ .dw PFA_DOVARIABLE
+PFA_TWDR:
+ .dw 187
+; ( -- addr ) System Constant
+; R( -- )
+; TWI (Slave) Address register
+VE_TWAR:
+ .dw $ff04
+ .db "TWAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWAR
+XT_TWAR:
+ .dw PFA_DOVARIABLE
+PFA_TWAR:
+ .dw 186
+
+.endif
+.if WANT_TIMER_COUNTER_1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Mask Register
+VE_TIMSK1:
+ .dw $ff06
+ .db "TIMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK1
+XT_TIMSK1:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK1:
+ .dw 111
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Flag register
+VE_TIFR1:
+ .dw $ff05
+ .db "TIFR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR1
+XT_TIFR1:
+ .dw PFA_DOVARIABLE
+PFA_TIFR1:
+ .dw 54
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw 128
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw 129
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register C
+VE_TCCR1C:
+ .dw $ff06
+ .db "TCCR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1C
+XT_TCCR1C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1C:
+ .dw 130
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Bytes
+VE_TCNT1:
+ .dw $ff05
+ .db "TCNT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1
+XT_TCNT1:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1:
+ .dw 132
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register Bytes
+VE_OCR1A:
+ .dw $ff05
+ .db "OCR1A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1A
+XT_OCR1A:
+ .dw PFA_DOVARIABLE
+PFA_OCR1A:
+ .dw 136
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register Bytes
+VE_OCR1B:
+ .dw $ff05
+ .db "OCR1B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1B
+XT_OCR1B:
+ .dw PFA_DOVARIABLE
+PFA_OCR1B:
+ .dw 138
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Bytes
+VE_ICR1:
+ .dw $ff04
+ .db "ICR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1
+XT_ICR1:
+ .dw PFA_DOVARIABLE
+PFA_ICR1:
+ .dw 134
+; ( -- addr ) System Constant
+; R( -- )
+; General Timer/Counter Control Register
+VE_GTCCR:
+ .dw $ff05
+ .db "GTCCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GTCCR
+XT_GTCCR:
+ .dw PFA_DOVARIABLE
+PFA_GTCCR:
+ .dw 67
+
+.endif
+.if WANT_TIMER_COUNTER_2 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Mask register
+VE_TIMSK2:
+ .dw $ff06
+ .db "TIMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK2
+XT_TIMSK2:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK2:
+ .dw 112
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Flag Register
+VE_TIFR2:
+ .dw $ff05
+ .db "TIFR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR2
+XT_TIFR2:
+ .dw PFA_DOVARIABLE
+PFA_TIFR2:
+ .dw 55
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register A
+VE_TCCR2A:
+ .dw $ff06
+ .db "TCCR2A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2A
+XT_TCCR2A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2A:
+ .dw 176
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register B
+VE_TCCR2B:
+ .dw $ff06
+ .db "TCCR2B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2B
+XT_TCCR2B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2B:
+ .dw 177
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2
+VE_TCNT2:
+ .dw $ff05
+ .db "TCNT2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT2
+XT_TCNT2:
+ .dw PFA_DOVARIABLE
+PFA_TCNT2:
+ .dw 178
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register B
+VE_OCR2B:
+ .dw $ff05
+ .db "OCR2B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2B
+XT_OCR2B:
+ .dw PFA_DOVARIABLE
+PFA_OCR2B:
+ .dw 180
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register A
+VE_OCR2A:
+ .dw $ff05
+ .db "OCR2A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2A
+XT_OCR2A:
+ .dw PFA_DOVARIABLE
+PFA_OCR2A:
+ .dw 179
+; ( -- addr ) System Constant
+; R( -- )
+; Asynchronous Status Register
+VE_ASSR:
+ .dw $ff04
+ .db "ASSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ASSR
+XT_ASSR:
+ .dw PFA_DOVARIABLE
+PFA_ASSR:
+ .dw 182
+
+.endif
+.if WANT_AD_CONVERTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC multiplexer Selection Register
+VE_ADMUX:
+ .dw $ff05
+ .db "ADMUX",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADMUX
+XT_ADMUX:
+ .dw PFA_DOVARIABLE
+PFA_ADMUX:
+ .dw 124
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register Bytes
+VE_ADC:
+ .dw $ff03
+ .db "ADC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADC
+XT_ADC:
+ .dw PFA_DOVARIABLE
+PFA_ADC:
+ .dw 120
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register A
+VE_ADCSRA:
+ .dw $ff06
+ .db "ADCSRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRA
+XT_ADCSRA:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRA:
+ .dw 122
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register B
+VE_ADCSRB:
+ .dw $ff06
+ .db "ADCSRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRB
+XT_ADCSRB:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRB:
+ .dw 123
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register
+VE_DIDR0:
+ .dw $ff05
+ .db "DIDR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR0
+XT_DIDR0:
+ .dw PFA_DOVARIABLE
+PFA_DIDR0:
+ .dw 126
+
+.endif
+.if WANT_ANALOG_COMPARATOR == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Control And Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw 80
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 1
+VE_DIDR1:
+ .dw $ff05
+ .db "DIDR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR1
+XT_DIDR1:
+ .dw PFA_DOVARIABLE
+PFA_DIDR1:
+ .dw 127
+
+.endif
+.if WANT_PORTB == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw 37
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw 36
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw 35
+
+.endif
+.if WANT_PORTC == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Register
+VE_PORTC:
+ .dw $ff05
+ .db "PORTC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTC
+XT_PORTC:
+ .dw PFA_DOVARIABLE
+PFA_PORTC:
+ .dw 40
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Direction Register
+VE_DDRC:
+ .dw $ff04
+ .db "DDRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRC
+XT_DDRC:
+ .dw PFA_DOVARIABLE
+PFA_DDRC:
+ .dw 39
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Input Pins
+VE_PINC:
+ .dw $ff04
+ .db "PINC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINC
+XT_PINC:
+ .dw PFA_DOVARIABLE
+PFA_PINC:
+ .dw 38
+
+.endif
+.if WANT_PORTD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw 43
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw 42
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw 41
+
+.endif
+.if WANT_TIMER_COUNTER_0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0B:
+ .dw $ff05
+ .db "OCR0B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0B
+XT_OCR0B:
+ .dw PFA_DOVARIABLE
+PFA_OCR0B:
+ .dw 72
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0A:
+ .dw $ff05
+ .db "OCR0A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0A
+XT_OCR0A:
+ .dw PFA_DOVARIABLE
+PFA_OCR0A:
+ .dw 71
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw 70
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register B
+VE_TCCR0B:
+ .dw $ff06
+ .db "TCCR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0B
+XT_TCCR0B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0B:
+ .dw 69
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register A
+VE_TCCR0A:
+ .dw $ff06
+ .db "TCCR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0A
+XT_TCCR0A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0A:
+ .dw 68
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Mask Register
+VE_TIMSK0:
+ .dw $ff06
+ .db "TIMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK0
+XT_TIMSK0:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK0:
+ .dw 110
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Flag register
+VE_TIFR0:
+ .dw $ff05
+ .db "TIFR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR0
+XT_TIFR0:
+ .dw PFA_DOVARIABLE
+PFA_TIFR0:
+ .dw 53
+
+.endif
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register
+VE_EICRA:
+ .dw $ff05
+ .db "EICRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRA
+XT_EICRA:
+ .dw PFA_DOVARIABLE
+PFA_EICRA:
+ .dw 105
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Mask Register
+VE_EIMSK:
+ .dw $ff05
+ .db "EIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIMSK
+XT_EIMSK:
+ .dw PFA_DOVARIABLE
+PFA_EIMSK:
+ .dw 61
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Flag Register
+VE_EIFR:
+ .dw $ff04
+ .db "EIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIFR
+XT_EIFR:
+ .dw PFA_DOVARIABLE
+PFA_EIFR:
+ .dw 60
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Interrupt Control Register
+VE_PCICR:
+ .dw $ff05
+ .db "PCICR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCICR
+XT_PCICR:
+ .dw PFA_DOVARIABLE
+PFA_PCICR:
+ .dw 104
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 2
+VE_PCMSK2:
+ .dw $ff06
+ .db "PCMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK2
+XT_PCMSK2:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK2:
+ .dw 109
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 1
+VE_PCMSK1:
+ .dw $ff06
+ .db "PCMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK1
+XT_PCMSK1:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK1:
+ .dw 108
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 0
+VE_PCMSK0:
+ .dw $ff06
+ .db "PCMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK0
+XT_PCMSK0:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK0:
+ .dw 107
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Interrupt Flag Register
+VE_PCIFR:
+ .dw $ff05
+ .db "PCIFR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCIFR
+XT_PCIFR:
+ .dw PFA_DOVARIABLE
+PFA_PCIFR:
+ .dw 59
+
+.endif
+.if WANT_SPI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR:
+ .dw $ff04
+ .db "SPDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR
+XT_SPDR:
+ .dw PFA_DOVARIABLE
+PFA_SPDR:
+ .dw 78
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR:
+ .dw $ff04
+ .db "SPSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR
+XT_SPSR:
+ .dw PFA_DOVARIABLE
+PFA_SPSR:
+ .dw 77
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR:
+ .dw $ff04
+ .db "SPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR
+XT_SPCR:
+ .dw PFA_DOVARIABLE
+PFA_SPCR:
+ .dw 76
+
+.endif
+.if WANT_CPU == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register
+VE_PRR:
+ .dw $ff03
+ .db "PRR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR
+XT_PRR:
+ .dw PFA_DOVARIABLE
+PFA_PRR:
+ .dw 100
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Calibration Value
+VE_OSCCAL:
+ .dw $ff06
+ .db "OSCCAL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSCCAL
+XT_OSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_OSCCAL:
+ .dw 102
+; ( -- addr ) System Constant
+; R( -- )
+; Clock Prescale Register
+VE_CLKPR:
+ .dw $ff05
+ .db "CLKPR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKPR
+XT_CLKPR:
+ .dw PFA_DOVARIABLE
+PFA_CLKPR:
+ .dw 97
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw 95
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer
+VE_SP:
+ .dw $ff02
+ .db "SP"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SP
+XT_SP:
+ .dw PFA_DOVARIABLE
+PFA_SP:
+ .dw 93
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control and Status Register
+VE_SPMCSR:
+ .dw $ff06
+ .db "SPMCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCSR
+XT_SPMCSR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCSR:
+ .dw 87
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw 85
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Status Register
+VE_MCUSR:
+ .dw $ff05
+ .db "MCUSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUSR
+XT_MCUSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUSR:
+ .dw 84
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_SMCR:
+ .dw $ff04
+ .db "SMCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SMCR
+XT_SMCR:
+ .dw PFA_DOVARIABLE
+PFA_SMCR:
+ .dw 83
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose I/O Register 2
+VE_GPIOR2:
+ .dw $ff06
+ .db "GPIOR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR2
+XT_GPIOR2:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR2:
+ .dw 75
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose I/O Register 1
+VE_GPIOR1:
+ .dw $ff06
+ .db "GPIOR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR1
+XT_GPIOR1:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR1:
+ .dw 74
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose I/O Register 0
+VE_GPIOR0:
+ .dw $ff06
+ .db "GPIOR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR0
+XT_GPIOR0:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR0:
+ .dw 62
+
+.endif
+.if WANT_WATCHDOG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCSR:
+ .dw $ff06
+ .db "WDTCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCSR
+XT_WDTCSR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCSR:
+ .dw 96
+
+.endif
+.if WANT_EEPROM == 1
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Address Register Bytes
+VE_EEAR:
+ .dw $ff04
+ .db "EEAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEAR
+XT_EEAR:
+ .dw PFA_DOVARIABLE
+PFA_EEAR:
+ .dw 65
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw 64
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw 63
+
+.endif
diff --git a/amforth-6.5/avr8/devices/atmega88/device.py b/amforth-6.5/avr8/devices/atmega88/device.py
new file mode 100644
index 0000000..7849841
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega88/device.py
@@ -0,0 +1,281 @@
+# Partname: ATmega88
+# generated automatically, do not edit
+MCUREGS = {
+ 'UDR0': '&198',
+ 'UCSR0A': '&192',
+ 'UCSR0A_RXC0': '$80',
+ 'UCSR0A_TXC0': '$40',
+ 'UCSR0A_UDRE0': '$20',
+ 'UCSR0A_FE0': '$10',
+ 'UCSR0A_DOR0': '$08',
+ 'UCSR0A_UPE0': '$04',
+ 'UCSR0A_U2X0': '$02',
+ 'UCSR0A_MPCM0': '$01',
+ 'UCSR0B': '&193',
+ 'UCSR0B_RXCIE0': '$80',
+ 'UCSR0B_TXCIE0': '$40',
+ 'UCSR0B_UDRIE0': '$20',
+ 'UCSR0B_RXEN0': '$10',
+ 'UCSR0B_TXEN0': '$08',
+ 'UCSR0B_UCSZ02': '$04',
+ 'UCSR0B_RXB80': '$02',
+ 'UCSR0B_TXB80': '$01',
+ 'UCSR0C': '&194',
+ 'UCSR0C_UMSEL0': '$C0',
+ 'UCSR0C_UPM0': '$30',
+ 'UCSR0C_USBS0': '$08',
+ 'UCSR0C_UCSZ0': '$06',
+ 'UCSR0C_UCPOL0': '$01',
+ 'UBRR0': '&196',
+ 'TWAMR': '&189',
+ 'TWAMR_TWAM': '$FE',
+ 'TWBR': '&184',
+ 'TWCR': '&188',
+ 'TWCR_TWINT': '$80',
+ 'TWCR_TWEA': '$40',
+ 'TWCR_TWSTA': '$20',
+ 'TWCR_TWSTO': '$10',
+ 'TWCR_TWWC': '$08',
+ 'TWCR_TWEN': '$04',
+ 'TWCR_TWIE': '$01',
+ 'TWSR': '&185',
+ 'TWSR_TWS': '$F8',
+ 'TWSR_TWPS': '$03',
+ 'TWDR': '&187',
+ 'TWAR': '&186',
+ 'TWAR_TWA': '$FE',
+ 'TWAR_TWGCE': '$01',
+ 'TIMSK1': '&111',
+ 'TIMSK1_ICIE1': '$20',
+ 'TIMSK1_OCIE1B': '$04',
+ 'TIMSK1_OCIE1A': '$02',
+ 'TIMSK1_TOIE1': '$01',
+ 'TIFR1': '&54',
+ 'TIFR1_ICF1': '$20',
+ 'TIFR1_OCF1B': '$04',
+ 'TIFR1_OCF1A': '$02',
+ 'TIFR1_TOV1': '$01',
+ 'TCCR1A': '&128',
+ 'TCCR1A_COM1A': '$C0',
+ 'TCCR1A_COM1B': '$30',
+ 'TCCR1A_WGM1': '$03',
+ 'TCCR1B': '&129',
+ 'TCCR1B_ICNC1': '$80',
+ 'TCCR1B_ICES1': '$40',
+ 'TCCR1B_WGM1': '$18',
+ 'TCCR1B_CS1': '$07',
+ 'TCCR1C': '&130',
+ 'TCCR1C_FOC1A': '$80',
+ 'TCCR1C_FOC1B': '$40',
+ 'TCNT1': '&132',
+ 'OCR1A': '&136',
+ 'OCR1B': '&138',
+ 'ICR1': '&134',
+ 'GTCCR': '&67',
+ 'GTCCR_TSM': '$80',
+ 'GTCCR_PSRSYNC': '$01',
+ 'TIMSK2': '&112',
+ 'TIMSK2_OCIE2B': '$04',
+ 'TIMSK2_OCIE2A': '$02',
+ 'TIMSK2_TOIE2': '$01',
+ 'TIFR2': '&55',
+ 'TIFR2_OCF2B': '$04',
+ 'TIFR2_OCF2A': '$02',
+ 'TIFR2_TOV2': '$01',
+ 'TCCR2A': '&176',
+ 'TCCR2A_COM2A': '$C0',
+ 'TCCR2A_COM2B': '$30',
+ 'TCCR2A_WGM2': '$03',
+ 'TCCR2B': '&177',
+ 'TCCR2B_FOC2A': '$80',
+ 'TCCR2B_FOC2B': '$40',
+ 'TCCR2B_WGM22': '$08',
+ 'TCCR2B_CS2': '$07',
+ 'TCNT2': '&178',
+ 'OCR2B': '&180',
+ 'OCR2A': '&179',
+ 'ASSR': '&182',
+ 'ASSR_EXCLK': '$40',
+ 'ASSR_AS2': '$20',
+ 'ASSR_TCN2UB': '$10',
+ 'ASSR_OCR2AUB': '$08',
+ 'ASSR_OCR2BUB': '$04',
+ 'ASSR_TCR2AUB': '$02',
+ 'ASSR_TCR2BUB': '$01',
+ 'ADMUX': '&124',
+ 'ADMUX_REFS': '$C0',
+ 'ADMUX_ADLAR': '$20',
+ 'ADMUX_MUX': '$0F',
+ 'ADC': '&120',
+ 'ADCSRA': '&122',
+ 'ADCSRA_ADEN': '$80',
+ 'ADCSRA_ADSC': '$40',
+ 'ADCSRA_ADATE': '$20',
+ 'ADCSRA_ADIF': '$10',
+ 'ADCSRA_ADIE': '$08',
+ 'ADCSRA_ADPS': '$07',
+ 'ADCSRB': '&123',
+ 'ADCSRB_ACME': '$40',
+ 'ADCSRB_ADTS': '$07',
+ 'DIDR0': '&126',
+ 'DIDR0_ADC5D': '$20',
+ 'DIDR0_ADC4D': '$10',
+ 'DIDR0_ADC3D': '$08',
+ 'DIDR0_ADC2D': '$04',
+ 'DIDR0_ADC1D': '$02',
+ 'DIDR0_ADC0D': '$01',
+ 'ACSR': '&80',
+ 'ACSR_ACD': '$80',
+ 'ACSR_ACBG': '$40',
+ 'ACSR_ACO': '$20',
+ 'ACSR_ACI': '$10',
+ 'ACSR_ACIE': '$08',
+ 'ACSR_ACIC': '$04',
+ 'ACSR_ACIS': '$03',
+ 'DIDR1': '&127',
+ 'DIDR1_AIN1D': '$02',
+ 'DIDR1_AIN0D': '$01',
+ 'PORTB': '&37',
+ 'DDRB': '&36',
+ 'PINB': '&35',
+ 'PORTC': '&40',
+ 'DDRC': '&39',
+ 'PINC': '&38',
+ 'PORTD': '&43',
+ 'DDRD': '&42',
+ 'PIND': '&41',
+ 'OCR0B': '&72',
+ 'OCR0A': '&71',
+ 'TCNT0': '&70',
+ 'TCCR0B': '&69',
+ 'TCCR0B_FOC0A': '$80',
+ 'TCCR0B_FOC0B': '$40',
+ 'TCCR0B_WGM02': '$08',
+ 'TCCR0B_CS0': '$07',
+ 'TCCR0A': '&68',
+ 'TCCR0A_COM0A': '$C0',
+ 'TCCR0A_COM0B': '$30',
+ 'TCCR0A_WGM0': '$03',
+ 'TIMSK0': '&110',
+ 'TIMSK0_OCIE0B': '$04',
+ 'TIMSK0_OCIE0A': '$02',
+ 'TIMSK0_TOIE0': '$01',
+ 'TIFR0': '&53',
+ 'TIFR0_OCF0B': '$04',
+ 'TIFR0_OCF0A': '$02',
+ 'TIFR0_TOV0': '$01',
+ 'EICRA': '&105',
+ 'EICRA_ISC1': '$0C',
+ 'EICRA_ISC0': '$03',
+ 'EIMSK': '&61',
+ 'EIMSK_INT': '$03',
+ 'EIFR': '&60',
+ 'EIFR_INTF': '$03',
+ 'PCICR': '&104',
+ 'PCICR_PCIE': '$07',
+ 'PCMSK2': '&109',
+ 'PCMSK2_PCINT': '$FF',
+ 'PCMSK1': '&108',
+ 'PCMSK1_PCINT': '$7F',
+ 'PCMSK0': '&107',
+ 'PCMSK0_PCINT': '$FF',
+ 'PCIFR': '&59',
+ 'PCIFR_PCIF': '$07',
+ 'SPDR': '&78',
+ 'SPSR': '&77',
+ 'SPSR_SPIF': '$80',
+ 'SPSR_WCOL': '$40',
+ 'SPSR_SPI2X': '$01',
+ 'SPCR': '&76',
+ 'SPCR_SPIE': '$80',
+ 'SPCR_SPE': '$40',
+ 'SPCR_DORD': '$20',
+ 'SPCR_MSTR': '$10',
+ 'SPCR_CPOL': '$08',
+ 'SPCR_CPHA': '$04',
+ 'SPCR_SPR': '$03',
+ 'PRR': '&100',
+ 'PRR_PRTWI': '$80',
+ 'PRR_PRTIM2': '$40',
+ 'PRR_PRTIM0': '$20',
+ 'PRR_PRTIM1': '$08',
+ 'PRR_PRSPI': '$04',
+ 'PRR_PRUSART0': '$02',
+ 'PRR_PRADC': '$01',
+ 'OSCCAL': '&102',
+ 'CLKPR': '&97',
+ 'CLKPR_CLKPCE': '$80',
+ 'CLKPR_CLKPS': '$0F',
+ 'SREG': '&95',
+ 'SREG_I': '$80',
+ 'SREG_T': '$40',
+ 'SREG_H': '$20',
+ 'SREG_S': '$10',
+ 'SREG_V': '$08',
+ 'SREG_N': '$04',
+ 'SREG_Z': '$02',
+ 'SREG_C': '$01',
+ 'SP': '&93',
+ 'SPMCSR': '&87',
+ 'SPMCSR_SPMIE': '$80',
+ 'SPMCSR_RWWSB': '$40',
+ 'SPMCSR_RWWSRE': '$10',
+ 'SPMCSR_BLBSET': '$08',
+ 'SPMCSR_PGWRT': '$04',
+ 'SPMCSR_PGERS': '$02',
+ 'SPMCSR_SELFPRGEN': '$01',
+ 'MCUCR': '&85',
+ 'MCUCR_PUD': '$10',
+ 'MCUCR_IVSEL': '$02',
+ 'MCUCR_IVCE': '$01',
+ 'MCUSR': '&84',
+ 'MCUSR_WDRF': '$08',
+ 'MCUSR_BORF': '$04',
+ 'MCUSR_EXTRF': '$02',
+ 'MCUSR_PORF': '$01',
+ 'SMCR': '&83',
+ 'SMCR_SM': '$0E',
+ 'SMCR_SE': '$01',
+ 'GPIOR2': '&75',
+ 'GPIOR1': '&74',
+ 'GPIOR0': '&62',
+ 'WDTCSR': '&96',
+ 'WDTCSR_WDIF': '$80',
+ 'WDTCSR_WDIE': '$40',
+ 'WDTCSR_WDP': '$27',
+ 'WDTCSR_WDCE': '$10',
+ 'WDTCSR_WDE': '$08',
+ 'EEAR': '&65',
+ 'EEDR': '&64',
+ 'EECR': '&63',
+ 'EECR_EEPM': '$30',
+ 'EECR_EERIE': '$08',
+ 'EECR_EEMPE': '$04',
+ 'EECR_EEPE': '$02',
+ 'EECR_EERE': '$01',
+ 'INT0Addr': '1',
+ 'INT1Addr': '2',
+ 'PCINT0Addr': '3',
+ 'PCINT1Addr': '4',
+ 'PCINT2Addr': '5',
+ 'WDTAddr': '6',
+ 'TIMER2_COMPAAddr': '7',
+ 'TIMER2_COMPBAddr': '8',
+ 'TIMER2_OVFAddr': '9',
+ 'TIMER1_CAPTAddr': '10',
+ 'TIMER1_COMPAAddr': '11',
+ 'TIMER1_COMPBAddr': '12',
+ 'TIMER1_OVFAddr': '13',
+ 'TIMER0_COMPAAddr': '14',
+ 'TIMER0_COMPBAddr': '15',
+ 'TIMER0_OVFAddr': '16',
+ 'SPI__STCAddr': '17',
+ 'USART__RXAddr': '18',
+ 'USART__UDREAddr': '19',
+ 'USART__TXAddr': '20',
+ 'ADCAddr': '21',
+ 'EE_READYAddr': '22',
+ 'ANALOG_COMPAddr': '23',
+ 'TWIAddr': '24',
+ 'SPM_ReadyAddr': '25'
+} \ No newline at end of file
diff --git a/amforth-6.5/avr8/devices/atmega88/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega88/words/no-jtag.asm
new file mode 100644
index 0000000..352a4bb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega88/words/no-jtag.asm
@@ -0,0 +1,14 @@
+; ( -- )
+; ( -- )
+; MCU
+; disable jtag at runtime
+VE_NOJTAG:
+ .dw $FF05
+ .db "-jtag",0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOJTAG
+XT_NOJTAG:
+ .dw PFA_NOJTAG
+PFA_NOJTAG:
+
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega88/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega88/words/no-wdt.asm
new file mode 100644
index 0000000..ff6ddd1
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega88/words/no-wdt.asm
@@ -0,0 +1,34 @@
+; ( -- )
+; MCU
+; disable watch dog timer at runtime
+VE_NOWDT:
+ .dw $ff04
+ .db "-wdt"
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOWDT
+XT_NOWDT:
+ .dw PFA_NOWDT
+PFA_NOWDT:
+
+ in temp1,SREG
+ push temp1
+ ; Turn always off global interrupt.
+ cli
+ ; Reset Watchdog Timer
+ wdr
+ ; Clear WDRF in MCUSR
+ in temp1, MCUSR
+ andi temp1, (0xff & (0<<WDRF))
+ out MCUSR, temp1
+ ; Write logical one to WDCE and WDE
+ ; Keep old prescaler setting to prevent unintentional time-out
+ in_ temp1, WDTCSR
+ ori temp1, (1<<WDCE) | (1<<WDE)
+ out_ WDTCSR, temp1
+ ; Turn off WDT
+ ldi temp1, (0<<WDE)
+ out_ WDTCSR, temp1
+ ; restore status register
+ pop temp1
+ out SREG,temp1
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega88/words/sleep.asm b/amforth-6.5/avr8/devices/atmega88/words/sleep.asm
new file mode 100644
index 0000000..256249c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega88/words/sleep.asm
@@ -0,0 +1,19 @@
+; ( mode -- )
+; MCU
+; put the controller into the specified sleep mode
+VE_SLEEP:
+ .dw $ff05
+ .db "sleep", 0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_SLEEP
+XT_SLEEP:
+ .dw PFA_SLEEP
+PFA_SLEEP:
+ andi tosl, 7 ; leave only legal mode bits
+ lsl tosl ; move to correct location (bits 3-1)
+ ori tosl, 1 ; set the SE bit
+ out_ SMCR, tosl ; set the sleep config
+ sleep ; nighty-night
+ out_ SMCR, zerol ; 0 protects against accidental sleeps
+ loadtos ; pop argument from stack
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega88a/atmega88a.frt b/amforth-6.5/avr8/devices/atmega88a/atmega88a.frt
new file mode 100644
index 0000000..657734d
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega88a/atmega88a.frt
@@ -0,0 +1,297 @@
+\ Partname: ATmega88A
+\ generated automatically
+
+\ USART0
+&198 constant UDR0 \ USART I/O Data Register
+&192 constant UCSR0A \ USART Control and Status Register A
+ $80 constant UCSR0A_RXC0 \ USART Receive Complete
+ $40 constant UCSR0A_TXC0 \ USART Transmitt Complete
+ $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
+ $10 constant UCSR0A_FE0 \ Framing Error
+ $08 constant UCSR0A_DOR0 \ Data overRun
+ $04 constant UCSR0A_UPE0 \ Parity Error
+ $02 constant UCSR0A_U2X0 \ Double the USART transmission speed
+ $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
+&193 constant UCSR0B \ USART Control and Status Register B
+ $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
+ $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
+ $20 constant UCSR0B_UDRIE0 \ USART Data register Empty Interrupt Enable
+ $10 constant UCSR0B_RXEN0 \ Receiver Enable
+ $08 constant UCSR0B_TXEN0 \ Transmitter Enable
+ $04 constant UCSR0B_UCSZ02 \ Character Size
+ $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
+ $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
+&194 constant UCSR0C \ USART Control and Status Register C
+ $C0 constant UCSR0C_UMSEL0 \ USART Mode Select
+ $30 constant UCSR0C_UPM0 \ Parity Mode Bits
+ $08 constant UCSR0C_USBS0 \ Stop Bit Select
+ $06 constant UCSR0C_UCSZ0 \ Character Size
+ $01 constant UCSR0C_UCPOL0 \ Clock Polarity
+&196 constant UBRR0 \ USART Baud Rate Register Bytes
+\ TWI
+&189 constant TWAMR \ TWI (Slave) Address Mask Register
+ $FE constant TWAMR_TWAM \
+&184 constant TWBR \ TWI Bit Rate register
+&188 constant TWCR \ TWI Control Register
+ $80 constant TWCR_TWINT \ TWI Interrupt Flag
+ $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
+ $20 constant TWCR_TWSTA \ TWI Start Condition Bit
+ $10 constant TWCR_TWSTO \ TWI Stop Condition Bit
+ $08 constant TWCR_TWWC \ TWI Write Collition Flag
+ $04 constant TWCR_TWEN \ TWI Enable Bit
+ $01 constant TWCR_TWIE \ TWI Interrupt Enable
+&185 constant TWSR \ TWI Status Register
+ $F8 constant TWSR_TWS \ TWI Status
+ $03 constant TWSR_TWPS \ TWI Prescaler
+&187 constant TWDR \ TWI Data register
+&186 constant TWAR \ TWI (Slave) Address register
+ $FE constant TWAR_TWA \ TWI (Slave) Address register Bits
+ $01 constant TWAR_TWGCE \ TWI General Call Recognition Enable Bit
+\ TIMER_COUNTER_1
+&111 constant TIMSK1 \ Timer/Counter Interrupt Mask Register
+ $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
+ $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output CompareB Match Interrupt Enable
+ $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output CompareA Match Interrupt Enable
+ $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
+&54 constant TIFR1 \ Timer/Counter Interrupt Flag register
+ $20 constant TIFR1_ICF1 \ Input Capture Flag 1
+ $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
+ $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
+ $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
+&128 constant TCCR1A \ Timer/Counter1 Control Register A
+ $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
+ $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
+ $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
+&129 constant TCCR1B \ Timer/Counter1 Control Register B
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
+ $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
+&130 constant TCCR1C \ Timer/Counter1 Control Register C
+ $80 constant TCCR1C_FOC1A \
+ $40 constant TCCR1C_FOC1B \
+&132 constant TCNT1 \ Timer/Counter1 Bytes
+&136 constant OCR1A \ Timer/Counter1 Output Compare Register Bytes
+&138 constant OCR1B \ Timer/Counter1 Output Compare Register Bytes
+&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
+&67 constant GTCCR \ General Timer/Counter Control Register
+ $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
+ $01 constant GTCCR_PSRSYNC \ Prescaler Reset Timer/Counter1 and Timer/Counter0
+\ TIMER_COUNTER_2
+&112 constant TIMSK2 \ Timer/Counter Interrupt Mask register
+ $04 constant TIMSK2_OCIE2B \ Timer/Counter2 Output Compare Match B Interrupt Enable
+ $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match A Interrupt Enable
+ $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
+&55 constant TIFR2 \ Timer/Counter Interrupt Flag Register
+ $04 constant TIFR2_OCF2B \ Output Compare Flag 2B
+ $02 constant TIFR2_OCF2A \ Output Compare Flag 2A
+ $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
+&176 constant TCCR2A \ Timer/Counter2 Control Register A
+ $C0 constant TCCR2A_COM2A \ Compare Output Mode bits
+ $30 constant TCCR2A_COM2B \ Compare Output Mode bits
+ $03 constant TCCR2A_WGM2 \ Waveform Genration Mode
+&177 constant TCCR2B \ Timer/Counter2 Control Register B
+ $80 constant TCCR2B_FOC2A \ Force Output Compare A
+ $40 constant TCCR2B_FOC2B \ Force Output Compare B
+ $08 constant TCCR2B_WGM22 \ Waveform Generation Mode
+ $07 constant TCCR2B_CS2 \ Clock Select bits
+&178 constant TCNT2 \ Timer/Counter2
+&180 constant OCR2B \ Timer/Counter2 Output Compare Register B
+&179 constant OCR2A \ Timer/Counter2 Output Compare Register A
+&182 constant ASSR \ Asynchronous Status Register
+ $40 constant ASSR_EXCLK \ Enable External Clock Input
+ $20 constant ASSR_AS2 \ Asynchronous Timer/Counter2
+ $10 constant ASSR_TCN2UB \ Timer/Counter2 Update Busy
+ $08 constant ASSR_OCR2AUB \ Output Compare Register2 Update Busy
+ $04 constant ASSR_OCR2BUB \ Output Compare Register 2 Update Busy
+ $02 constant ASSR_TCR2AUB \ Timer/Counter Control Register2 Update Busy
+ $01 constant ASSR_TCR2BUB \ Timer/Counter Control Register2 Update Busy
+\ AD_CONVERTER
+&124 constant ADMUX \ The ADC multiplexer Selection Register
+ $C0 constant ADMUX_REFS \ Reference Selection Bits
+ $20 constant ADMUX_ADLAR \ Left Adjust Result
+ $0F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
+&120 constant ADC \ ADC Data Register Bytes
+&122 constant ADCSRA \ The ADC Control and Status register A
+ $80 constant ADCSRA_ADEN \ ADC Enable
+ $40 constant ADCSRA_ADSC \ ADC Start Conversion
+ $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
+ $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
+ $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
+ $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
+&123 constant ADCSRB \ The ADC Control and Status register B
+ $40 constant ADCSRB_ACME \
+ $07 constant ADCSRB_ADTS \ ADC Auto Trigger Source bits
+&126 constant DIDR0 \ Digital Input Disable Register
+ $20 constant DIDR0_ADC5D \
+ $10 constant DIDR0_ADC4D \
+ $08 constant DIDR0_ADC3D \
+ $04 constant DIDR0_ADC2D \
+ $02 constant DIDR0_ADC1D \
+ $01 constant DIDR0_ADC0D \
+\ ANALOG_COMPARATOR
+&80 constant ACSR \ Analog Comparator Control And Status Register
+ $80 constant ACSR_ACD \ Analog Comparator Disable
+ $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
+ $20 constant ACSR_ACO \ Analog Compare Output
+ $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
+ $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
+ $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
+ $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
+&127 constant DIDR1 \ Digital Input Disable Register 1
+ $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
+ $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
+\ PORTB
+&37 constant PORTB \ Port B Data Register
+&36 constant DDRB \ Port B Data Direction Register
+&35 constant PINB \ Port B Input Pins
+\ PORTC
+&40 constant PORTC \ Port C Data Register
+&39 constant DDRC \ Port C Data Direction Register
+&38 constant PINC \ Port C Input Pins
+\ PORTD
+&43 constant PORTD \ Port D Data Register
+&42 constant DDRD \ Port D Data Direction Register
+&41 constant PIND \ Port D Input Pins
+\ TIMER_COUNTER_0
+&72 constant OCR0B \ Timer/Counter0 Output Compare Register
+&71 constant OCR0A \ Timer/Counter0 Output Compare Register
+&70 constant TCNT0 \ Timer/Counter0
+&69 constant TCCR0B \ Timer/Counter Control Register B
+ $80 constant TCCR0B_FOC0A \ Force Output Compare A
+ $40 constant TCCR0B_FOC0B \ Force Output Compare B
+ $08 constant TCCR0B_WGM02 \
+ $07 constant TCCR0B_CS0 \ Clock Select
+&68 constant TCCR0A \ Timer/Counter Control Register A
+ $C0 constant TCCR0A_COM0A \ Compare Output Mode, Phase Correct PWM Mode
+ $30 constant TCCR0A_COM0B \ Compare Output Mode, Fast PWm
+ $03 constant TCCR0A_WGM0 \ Waveform Generation Mode
+&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
+ $04 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare Match B Interrupt Enable
+ $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match A Interrupt Enable
+ $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
+&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
+ $04 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare Flag 0B
+ $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0A
+ $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
+\ EXTERNAL_INTERRUPT
+&105 constant EICRA \ External Interrupt Control Register
+ $0C constant EICRA_ISC1 \ External Interrupt Sense Control 1 Bits
+ $03 constant EICRA_ISC0 \ External Interrupt Sense Control 0 Bits
+&61 constant EIMSK \ External Interrupt Mask Register
+ $03 constant EIMSK_INT \ External Interrupt Request 1 Enable
+&60 constant EIFR \ External Interrupt Flag Register
+ $03 constant EIFR_INTF \ External Interrupt Flags
+&104 constant PCICR \ Pin Change Interrupt Control Register
+ $07 constant PCICR_PCIE \ Pin Change Interrupt Enables
+&109 constant PCMSK2 \ Pin Change Mask Register 2
+ $FF constant PCMSK2_PCINT \ Pin Change Enable Masks
+&108 constant PCMSK1 \ Pin Change Mask Register 1
+ $7F constant PCMSK1_PCINT \ Pin Change Enable Masks
+&107 constant PCMSK0 \ Pin Change Mask Register 0
+ $FF constant PCMSK0_PCINT \ Pin Change Enable Masks
+&59 constant PCIFR \ Pin Change Interrupt Flag Register
+ $07 constant PCIFR_PCIF \ Pin Change Interrupt Flags
+\ SPI
+&78 constant SPDR \ SPI Data Register
+&77 constant SPSR \ SPI Status Register
+ $80 constant SPSR_SPIF \ SPI Interrupt Flag
+ $40 constant SPSR_WCOL \ Write Collision Flag
+ $01 constant SPSR_SPI2X \ Double SPI Speed Bit
+&76 constant SPCR \ SPI Control Register
+ $80 constant SPCR_SPIE \ SPI Interrupt Enable
+ $40 constant SPCR_SPE \ SPI Enable
+ $20 constant SPCR_DORD \ Data Order
+ $10 constant SPCR_MSTR \ Master/Slave Select
+ $08 constant SPCR_CPOL \ Clock polarity
+ $04 constant SPCR_CPHA \ Clock Phase
+ $03 constant SPCR_SPR \ SPI Clock Rate Selects
+\ WATCHDOG
+&96 constant WDTCSR \ Watchdog Timer Control Register
+ $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Flag
+ $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Enable
+ $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
+ $10 constant WDTCSR_WDCE \ Watchdog Change Enable
+ $08 constant WDTCSR_WDE \ Watch Dog Enable
+\ EEPROM
+&65 constant EEAR \ EEPROM Address Register Bytes
+&64 constant EEDR \ EEPROM Data Register
+&63 constant EECR \ EEPROM Control Register
+ $30 constant EECR_EEPM \ EEPROM Programming Mode Bits
+ $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
+ $04 constant EECR_EEMPE \ EEPROM Master Write Enable
+ $02 constant EECR_EEPE \ EEPROM Write Enable
+ $01 constant EECR_EERE \ EEPROM Read Enable
+\ CPU
+&100 constant PRR \ Power Reduction Register
+ $80 constant PRR_PRTWI \ Power Reduction TWI
+ $40 constant PRR_PRTIM2 \ Power Reduction Timer/Counter2
+ $20 constant PRR_PRTIM0 \ Power Reduction Timer/Counter0
+ $08 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
+ $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
+ $02 constant PRR_PRUSART0 \ Power Reduction USART
+ $01 constant PRR_PRADC \ Power Reduction ADC
+&102 constant OSCCAL \ Oscillator Calibration Value
+&97 constant CLKPR \ Clock Prescale Register
+ $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable
+ $0F constant CLKPR_CLKPS \ Clock Prescaler Select Bits
+&95 constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ $08 constant SREG_V \ Two's Complement Overflow Flag
+ $04 constant SREG_N \ Negative Flag
+ $02 constant SREG_Z \ Zero Flag
+ $01 constant SREG_C \ Carry Flag
+&93 constant SP \ Stack Pointer
+&87 constant SPMCSR \ Store Program Memory Control and Status Register
+ $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCSR_RWWSB \ Read-While-Write Section Busy
+ $10 constant SPMCSR_RWWSRE \ Read-While-Write section read enable
+ $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
+ $04 constant SPMCSR_PGWRT \ Page Write
+ $02 constant SPMCSR_PGERS \ Page Erase
+ $01 constant SPMCSR_SELFPRGEN \ Self Programming Enable
+&85 constant MCUCR \ MCU Control Register
+ $10 constant MCUCR_PUD \
+ $02 constant MCUCR_IVSEL \
+ $01 constant MCUCR_IVCE \
+&84 constant MCUSR \ MCU Status Register
+ $08 constant MCUSR_WDRF \ Watchdog Reset Flag
+ $04 constant MCUSR_BORF \ Brown-out Reset Flag
+ $02 constant MCUSR_EXTRF \ External Reset Flag
+ $01 constant MCUSR_PORF \ Power-on reset flag
+&83 constant SMCR \ Sleep Mode Control Register
+ $0E constant SMCR_SM \ Sleep Mode Select Bits
+ $01 constant SMCR_SE \ Sleep Enable
+&75 constant GPIOR2 \ General Purpose I/O Register 2
+&74 constant GPIOR1 \ General Purpose I/O Register 1
+&62 constant GPIOR0 \ General Purpose I/O Register 0
+
+\ Interrupts
+&1 constant INT0Addr \ External Interrupt Request 0
+&2 constant INT1Addr \ External Interrupt Request 1
+&3 constant PCINT0Addr \ Pin Change Interrupt Request 0
+&4 constant PCINT1Addr \ Pin Change Interrupt Request 0
+&5 constant PCINT2Addr \ Pin Change Interrupt Request 1
+&6 constant WDTAddr \ Watchdog Time-out Interrupt
+&7 constant TIMER2_COMPAAddr \ Timer/Counter2 Compare Match A
+&8 constant TIMER2_COMPBAddr \ Timer/Counter2 Compare Match A
+&9 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
+&10 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+&11 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
+&12 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
+&13 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+&14 constant TIMER0_COMPAAddr \ TimerCounter0 Compare Match A
+&15 constant TIMER0_COMPBAddr \ TimerCounter0 Compare Match B
+&16 constant TIMER0_OVFAddr \ Timer/Couner0 Overflow
+&17 constant SPI__STCAddr \ SPI Serial Transfer Complete
+&18 constant USART__RXAddr \ USART Rx Complete
+&19 constant USART__UDREAddr \ USART, Data Register Empty
+&20 constant USART__TXAddr \ USART Tx Complete
+&21 constant ADCAddr \ ADC Conversion Complete
+&22 constant EE_READYAddr \ EEPROM Ready
+&23 constant ANALOG_COMPAddr \ Analog Comparator
+&24 constant TWIAddr \ Two-wire Serial Interface
+&25 constant SPM_ReadyAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/atmega88a/device.asm b/amforth-6.5/avr8/devices/atmega88a/device.asm
new file mode 100644
index 0000000..1195a9c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega88a/device.asm
@@ -0,0 +1,107 @@
+; Partname: ATmega88A
+; generated automatically, do not edit
+
+.nolist
+ .include "m88Adef.inc"
+.list
+
+.equ ramstart = 256
+.equ CELLSIZE = 2
+.macro readflashcell
+ lsl zl
+ rol zh
+ lpm @0, Z+
+ lpm @1, Z+
+.endmacro
+.macro writeflashcell
+ lsl zl
+ rol zh
+.endmacro
+.set WANT_USART0 = 0
+.set WANT_TWI = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_TIMER_COUNTER_2 = 0
+.set WANT_AD_CONVERTER = 0
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_PORTB = 0
+.set WANT_PORTC = 0
+.set WANT_PORTD = 0
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_SPI = 0
+.set WANT_WATCHDOG = 0
+.set WANT_EEPROM = 0
+.set WANT_CPU = 0
+.equ intvecsize = 1 ; please verify; flash size: 8192 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.org 1
+ rcall isr ; External Interrupt Request 0
+.org 2
+ rcall isr ; External Interrupt Request 1
+.org 3
+ rcall isr ; Pin Change Interrupt Request 0
+.org 4
+ rcall isr ; Pin Change Interrupt Request 0
+.org 5
+ rcall isr ; Pin Change Interrupt Request 1
+.org 6
+ rcall isr ; Watchdog Time-out Interrupt
+.org 7
+ rcall isr ; Timer/Counter2 Compare Match A
+.org 8
+ rcall isr ; Timer/Counter2 Compare Match A
+.org 9
+ rcall isr ; Timer/Counter2 Overflow
+.org 10
+ rcall isr ; Timer/Counter1 Capture Event
+.org 11
+ rcall isr ; Timer/Counter1 Compare Match A
+.org 12
+ rcall isr ; Timer/Counter1 Compare Match B
+.org 13
+ rcall isr ; Timer/Counter1 Overflow
+.org 14
+ rcall isr ; TimerCounter0 Compare Match A
+.org 15
+ rcall isr ; TimerCounter0 Compare Match B
+.org 16
+ rcall isr ; Timer/Couner0 Overflow
+.org 17
+ rcall isr ; SPI Serial Transfer Complete
+.org 18
+ rcall isr ; USART Rx Complete
+.org 19
+ rcall isr ; USART, Data Register Empty
+.org 20
+ rcall isr ; USART Tx Complete
+.org 21
+ rcall isr ; ADC Conversion Complete
+.org 22
+ rcall isr ; EEPROM Ready
+.org 23
+ rcall isr ; Analog Comparator
+.org 24
+ rcall isr ; Two-wire Serial Interface
+.org 25
+ rcall isr ; Store Program Memory Read
+.equ INTVECTORS = 26
+.nooverlap
+
+; compatability layer (maybe empty)
+.equ SPMEN = SELFPRGEN
+
+; controller data area, environment query mcu-info
+mcu_info:
+mcu_ramsize:
+ .dw 1024
+mcu_eepromsize:
+ .dw 512
+mcu_maxdp:
+ .dw 6144
+mcu_numints:
+ .dw 26
+mcu_name:
+ .dw 9
+ .db "ATmega88A",0
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega88a/device.inc b/amforth-6.5/avr8/devices/atmega88a/device.inc
new file mode 100644
index 0000000..446e57e
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega88a/device.inc
@@ -0,0 +1,996 @@
+; Partname: ATmega88A
+; generated automatically, no not edit
+
+.if WANT_USART0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR0:
+ .dw $ff04
+ .db "UDR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR0
+XT_UDR0:
+ .dw PFA_DOVARIABLE
+PFA_UDR0:
+ .dw 198
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR0A:
+ .dw $ff06
+ .db "UCSR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0A
+XT_UCSR0A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0A:
+ .dw 192
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR0B:
+ .dw $ff06
+ .db "UCSR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0B
+XT_UCSR0B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0B:
+ .dw 193
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR0C:
+ .dw $ff06
+ .db "UCSR0C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0C
+XT_UCSR0C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0C:
+ .dw 194
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Bytes
+VE_UBRR0:
+ .dw $ff05
+ .db "UBRR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR0
+XT_UBRR0:
+ .dw PFA_DOVARIABLE
+PFA_UBRR0:
+ .dw 196
+
+.endif
+.if WANT_TWI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; TWI (Slave) Address Mask Register
+VE_TWAMR:
+ .dw $ff05
+ .db "TWAMR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWAMR
+XT_TWAMR:
+ .dw PFA_DOVARIABLE
+PFA_TWAMR:
+ .dw 189
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Bit Rate register
+VE_TWBR:
+ .dw $ff04
+ .db "TWBR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWBR
+XT_TWBR:
+ .dw PFA_DOVARIABLE
+PFA_TWBR:
+ .dw 184
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Control Register
+VE_TWCR:
+ .dw $ff04
+ .db "TWCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWCR
+XT_TWCR:
+ .dw PFA_DOVARIABLE
+PFA_TWCR:
+ .dw 188
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Status Register
+VE_TWSR:
+ .dw $ff04
+ .db "TWSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWSR
+XT_TWSR:
+ .dw PFA_DOVARIABLE
+PFA_TWSR:
+ .dw 185
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Data register
+VE_TWDR:
+ .dw $ff04
+ .db "TWDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWDR
+XT_TWDR:
+ .dw PFA_DOVARIABLE
+PFA_TWDR:
+ .dw 187
+; ( -- addr ) System Constant
+; R( -- )
+; TWI (Slave) Address register
+VE_TWAR:
+ .dw $ff04
+ .db "TWAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWAR
+XT_TWAR:
+ .dw PFA_DOVARIABLE
+PFA_TWAR:
+ .dw 186
+
+.endif
+.if WANT_TIMER_COUNTER_1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Mask Register
+VE_TIMSK1:
+ .dw $ff06
+ .db "TIMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK1
+XT_TIMSK1:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK1:
+ .dw 111
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Flag register
+VE_TIFR1:
+ .dw $ff05
+ .db "TIFR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR1
+XT_TIFR1:
+ .dw PFA_DOVARIABLE
+PFA_TIFR1:
+ .dw 54
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw 128
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw 129
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register C
+VE_TCCR1C:
+ .dw $ff06
+ .db "TCCR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1C
+XT_TCCR1C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1C:
+ .dw 130
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Bytes
+VE_TCNT1:
+ .dw $ff05
+ .db "TCNT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1
+XT_TCNT1:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1:
+ .dw 132
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register Bytes
+VE_OCR1A:
+ .dw $ff05
+ .db "OCR1A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1A
+XT_OCR1A:
+ .dw PFA_DOVARIABLE
+PFA_OCR1A:
+ .dw 136
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register Bytes
+VE_OCR1B:
+ .dw $ff05
+ .db "OCR1B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1B
+XT_OCR1B:
+ .dw PFA_DOVARIABLE
+PFA_OCR1B:
+ .dw 138
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Bytes
+VE_ICR1:
+ .dw $ff04
+ .db "ICR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1
+XT_ICR1:
+ .dw PFA_DOVARIABLE
+PFA_ICR1:
+ .dw 134
+; ( -- addr ) System Constant
+; R( -- )
+; General Timer/Counter Control Register
+VE_GTCCR:
+ .dw $ff05
+ .db "GTCCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GTCCR
+XT_GTCCR:
+ .dw PFA_DOVARIABLE
+PFA_GTCCR:
+ .dw 67
+
+.endif
+.if WANT_TIMER_COUNTER_2 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Mask register
+VE_TIMSK2:
+ .dw $ff06
+ .db "TIMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK2
+XT_TIMSK2:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK2:
+ .dw 112
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Flag Register
+VE_TIFR2:
+ .dw $ff05
+ .db "TIFR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR2
+XT_TIFR2:
+ .dw PFA_DOVARIABLE
+PFA_TIFR2:
+ .dw 55
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register A
+VE_TCCR2A:
+ .dw $ff06
+ .db "TCCR2A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2A
+XT_TCCR2A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2A:
+ .dw 176
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register B
+VE_TCCR2B:
+ .dw $ff06
+ .db "TCCR2B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2B
+XT_TCCR2B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2B:
+ .dw 177
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2
+VE_TCNT2:
+ .dw $ff05
+ .db "TCNT2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT2
+XT_TCNT2:
+ .dw PFA_DOVARIABLE
+PFA_TCNT2:
+ .dw 178
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register B
+VE_OCR2B:
+ .dw $ff05
+ .db "OCR2B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2B
+XT_OCR2B:
+ .dw PFA_DOVARIABLE
+PFA_OCR2B:
+ .dw 180
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register A
+VE_OCR2A:
+ .dw $ff05
+ .db "OCR2A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2A
+XT_OCR2A:
+ .dw PFA_DOVARIABLE
+PFA_OCR2A:
+ .dw 179
+; ( -- addr ) System Constant
+; R( -- )
+; Asynchronous Status Register
+VE_ASSR:
+ .dw $ff04
+ .db "ASSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ASSR
+XT_ASSR:
+ .dw PFA_DOVARIABLE
+PFA_ASSR:
+ .dw 182
+
+.endif
+.if WANT_AD_CONVERTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC multiplexer Selection Register
+VE_ADMUX:
+ .dw $ff05
+ .db "ADMUX",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADMUX
+XT_ADMUX:
+ .dw PFA_DOVARIABLE
+PFA_ADMUX:
+ .dw 124
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register Bytes
+VE_ADC:
+ .dw $ff03
+ .db "ADC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADC
+XT_ADC:
+ .dw PFA_DOVARIABLE
+PFA_ADC:
+ .dw 120
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register A
+VE_ADCSRA:
+ .dw $ff06
+ .db "ADCSRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRA
+XT_ADCSRA:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRA:
+ .dw 122
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register B
+VE_ADCSRB:
+ .dw $ff06
+ .db "ADCSRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRB
+XT_ADCSRB:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRB:
+ .dw 123
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register
+VE_DIDR0:
+ .dw $ff05
+ .db "DIDR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR0
+XT_DIDR0:
+ .dw PFA_DOVARIABLE
+PFA_DIDR0:
+ .dw 126
+
+.endif
+.if WANT_ANALOG_COMPARATOR == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Control And Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw 80
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 1
+VE_DIDR1:
+ .dw $ff05
+ .db "DIDR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR1
+XT_DIDR1:
+ .dw PFA_DOVARIABLE
+PFA_DIDR1:
+ .dw 127
+
+.endif
+.if WANT_PORTB == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw 37
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw 36
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw 35
+
+.endif
+.if WANT_PORTC == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Register
+VE_PORTC:
+ .dw $ff05
+ .db "PORTC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTC
+XT_PORTC:
+ .dw PFA_DOVARIABLE
+PFA_PORTC:
+ .dw 40
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Direction Register
+VE_DDRC:
+ .dw $ff04
+ .db "DDRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRC
+XT_DDRC:
+ .dw PFA_DOVARIABLE
+PFA_DDRC:
+ .dw 39
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Input Pins
+VE_PINC:
+ .dw $ff04
+ .db "PINC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINC
+XT_PINC:
+ .dw PFA_DOVARIABLE
+PFA_PINC:
+ .dw 38
+
+.endif
+.if WANT_PORTD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw 43
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw 42
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw 41
+
+.endif
+.if WANT_TIMER_COUNTER_0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0B:
+ .dw $ff05
+ .db "OCR0B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0B
+XT_OCR0B:
+ .dw PFA_DOVARIABLE
+PFA_OCR0B:
+ .dw 72
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0A:
+ .dw $ff05
+ .db "OCR0A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0A
+XT_OCR0A:
+ .dw PFA_DOVARIABLE
+PFA_OCR0A:
+ .dw 71
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw 70
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register B
+VE_TCCR0B:
+ .dw $ff06
+ .db "TCCR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0B
+XT_TCCR0B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0B:
+ .dw 69
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register A
+VE_TCCR0A:
+ .dw $ff06
+ .db "TCCR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0A
+XT_TCCR0A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0A:
+ .dw 68
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Mask Register
+VE_TIMSK0:
+ .dw $ff06
+ .db "TIMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK0
+XT_TIMSK0:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK0:
+ .dw 110
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Flag register
+VE_TIFR0:
+ .dw $ff05
+ .db "TIFR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR0
+XT_TIFR0:
+ .dw PFA_DOVARIABLE
+PFA_TIFR0:
+ .dw 53
+
+.endif
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register
+VE_EICRA:
+ .dw $ff05
+ .db "EICRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRA
+XT_EICRA:
+ .dw PFA_DOVARIABLE
+PFA_EICRA:
+ .dw 105
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Mask Register
+VE_EIMSK:
+ .dw $ff05
+ .db "EIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIMSK
+XT_EIMSK:
+ .dw PFA_DOVARIABLE
+PFA_EIMSK:
+ .dw 61
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Flag Register
+VE_EIFR:
+ .dw $ff04
+ .db "EIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIFR
+XT_EIFR:
+ .dw PFA_DOVARIABLE
+PFA_EIFR:
+ .dw 60
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Interrupt Control Register
+VE_PCICR:
+ .dw $ff05
+ .db "PCICR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCICR
+XT_PCICR:
+ .dw PFA_DOVARIABLE
+PFA_PCICR:
+ .dw 104
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 2
+VE_PCMSK2:
+ .dw $ff06
+ .db "PCMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK2
+XT_PCMSK2:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK2:
+ .dw 109
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 1
+VE_PCMSK1:
+ .dw $ff06
+ .db "PCMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK1
+XT_PCMSK1:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK1:
+ .dw 108
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 0
+VE_PCMSK0:
+ .dw $ff06
+ .db "PCMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK0
+XT_PCMSK0:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK0:
+ .dw 107
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Interrupt Flag Register
+VE_PCIFR:
+ .dw $ff05
+ .db "PCIFR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCIFR
+XT_PCIFR:
+ .dw PFA_DOVARIABLE
+PFA_PCIFR:
+ .dw 59
+
+.endif
+.if WANT_SPI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR:
+ .dw $ff04
+ .db "SPDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR
+XT_SPDR:
+ .dw PFA_DOVARIABLE
+PFA_SPDR:
+ .dw 78
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR:
+ .dw $ff04
+ .db "SPSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR
+XT_SPSR:
+ .dw PFA_DOVARIABLE
+PFA_SPSR:
+ .dw 77
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR:
+ .dw $ff04
+ .db "SPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR
+XT_SPCR:
+ .dw PFA_DOVARIABLE
+PFA_SPCR:
+ .dw 76
+
+.endif
+.if WANT_WATCHDOG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCSR:
+ .dw $ff06
+ .db "WDTCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCSR
+XT_WDTCSR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCSR:
+ .dw 96
+
+.endif
+.if WANT_EEPROM == 1
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Address Register Bytes
+VE_EEAR:
+ .dw $ff04
+ .db "EEAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEAR
+XT_EEAR:
+ .dw PFA_DOVARIABLE
+PFA_EEAR:
+ .dw 65
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw 64
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw 63
+
+.endif
+.if WANT_CPU == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register
+VE_PRR:
+ .dw $ff03
+ .db "PRR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR
+XT_PRR:
+ .dw PFA_DOVARIABLE
+PFA_PRR:
+ .dw 100
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Calibration Value
+VE_OSCCAL:
+ .dw $ff06
+ .db "OSCCAL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSCCAL
+XT_OSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_OSCCAL:
+ .dw 102
+; ( -- addr ) System Constant
+; R( -- )
+; Clock Prescale Register
+VE_CLKPR:
+ .dw $ff05
+ .db "CLKPR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKPR
+XT_CLKPR:
+ .dw PFA_DOVARIABLE
+PFA_CLKPR:
+ .dw 97
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw 95
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer
+VE_SP:
+ .dw $ff02
+ .db "SP"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SP
+XT_SP:
+ .dw PFA_DOVARIABLE
+PFA_SP:
+ .dw 93
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control and Status Register
+VE_SPMCSR:
+ .dw $ff06
+ .db "SPMCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCSR
+XT_SPMCSR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCSR:
+ .dw 87
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw 85
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Status Register
+VE_MCUSR:
+ .dw $ff05
+ .db "MCUSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUSR
+XT_MCUSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUSR:
+ .dw 84
+; ( -- addr ) System Constant
+; R( -- )
+; Sleep Mode Control Register
+VE_SMCR:
+ .dw $ff04
+ .db "SMCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SMCR
+XT_SMCR:
+ .dw PFA_DOVARIABLE
+PFA_SMCR:
+ .dw 83
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose I/O Register 2
+VE_GPIOR2:
+ .dw $ff06
+ .db "GPIOR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR2
+XT_GPIOR2:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR2:
+ .dw 75
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose I/O Register 1
+VE_GPIOR1:
+ .dw $ff06
+ .db "GPIOR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR1
+XT_GPIOR1:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR1:
+ .dw 74
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose I/O Register 0
+VE_GPIOR0:
+ .dw $ff06
+ .db "GPIOR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR0
+XT_GPIOR0:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR0:
+ .dw 62
+
+.endif
diff --git a/amforth-6.5/avr8/devices/atmega88a/device.py b/amforth-6.5/avr8/devices/atmega88a/device.py
new file mode 100644
index 0000000..4c18ee9
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega88a/device.py
@@ -0,0 +1,281 @@
+# Partname: ATmega88A
+# generated automatically, do not edit
+MCUREGS = {
+ 'UDR0': '&198',
+ 'UCSR0A': '&192',
+ 'UCSR0A_RXC0': '$80',
+ 'UCSR0A_TXC0': '$40',
+ 'UCSR0A_UDRE0': '$20',
+ 'UCSR0A_FE0': '$10',
+ 'UCSR0A_DOR0': '$08',
+ 'UCSR0A_UPE0': '$04',
+ 'UCSR0A_U2X0': '$02',
+ 'UCSR0A_MPCM0': '$01',
+ 'UCSR0B': '&193',
+ 'UCSR0B_RXCIE0': '$80',
+ 'UCSR0B_TXCIE0': '$40',
+ 'UCSR0B_UDRIE0': '$20',
+ 'UCSR0B_RXEN0': '$10',
+ 'UCSR0B_TXEN0': '$08',
+ 'UCSR0B_UCSZ02': '$04',
+ 'UCSR0B_RXB80': '$02',
+ 'UCSR0B_TXB80': '$01',
+ 'UCSR0C': '&194',
+ 'UCSR0C_UMSEL0': '$C0',
+ 'UCSR0C_UPM0': '$30',
+ 'UCSR0C_USBS0': '$08',
+ 'UCSR0C_UCSZ0': '$06',
+ 'UCSR0C_UCPOL0': '$01',
+ 'UBRR0': '&196',
+ 'TWAMR': '&189',
+ 'TWAMR_TWAM': '$FE',
+ 'TWBR': '&184',
+ 'TWCR': '&188',
+ 'TWCR_TWINT': '$80',
+ 'TWCR_TWEA': '$40',
+ 'TWCR_TWSTA': '$20',
+ 'TWCR_TWSTO': '$10',
+ 'TWCR_TWWC': '$08',
+ 'TWCR_TWEN': '$04',
+ 'TWCR_TWIE': '$01',
+ 'TWSR': '&185',
+ 'TWSR_TWS': '$F8',
+ 'TWSR_TWPS': '$03',
+ 'TWDR': '&187',
+ 'TWAR': '&186',
+ 'TWAR_TWA': '$FE',
+ 'TWAR_TWGCE': '$01',
+ 'TIMSK1': '&111',
+ 'TIMSK1_ICIE1': '$20',
+ 'TIMSK1_OCIE1B': '$04',
+ 'TIMSK1_OCIE1A': '$02',
+ 'TIMSK1_TOIE1': '$01',
+ 'TIFR1': '&54',
+ 'TIFR1_ICF1': '$20',
+ 'TIFR1_OCF1B': '$04',
+ 'TIFR1_OCF1A': '$02',
+ 'TIFR1_TOV1': '$01',
+ 'TCCR1A': '&128',
+ 'TCCR1A_COM1A': '$C0',
+ 'TCCR1A_COM1B': '$30',
+ 'TCCR1A_WGM1': '$03',
+ 'TCCR1B': '&129',
+ 'TCCR1B_ICNC1': '$80',
+ 'TCCR1B_ICES1': '$40',
+ 'TCCR1B_WGM1': '$18',
+ 'TCCR1B_CS1': '$07',
+ 'TCCR1C': '&130',
+ 'TCCR1C_FOC1A': '$80',
+ 'TCCR1C_FOC1B': '$40',
+ 'TCNT1': '&132',
+ 'OCR1A': '&136',
+ 'OCR1B': '&138',
+ 'ICR1': '&134',
+ 'GTCCR': '&67',
+ 'GTCCR_TSM': '$80',
+ 'GTCCR_PSRSYNC': '$01',
+ 'TIMSK2': '&112',
+ 'TIMSK2_OCIE2B': '$04',
+ 'TIMSK2_OCIE2A': '$02',
+ 'TIMSK2_TOIE2': '$01',
+ 'TIFR2': '&55',
+ 'TIFR2_OCF2B': '$04',
+ 'TIFR2_OCF2A': '$02',
+ 'TIFR2_TOV2': '$01',
+ 'TCCR2A': '&176',
+ 'TCCR2A_COM2A': '$C0',
+ 'TCCR2A_COM2B': '$30',
+ 'TCCR2A_WGM2': '$03',
+ 'TCCR2B': '&177',
+ 'TCCR2B_FOC2A': '$80',
+ 'TCCR2B_FOC2B': '$40',
+ 'TCCR2B_WGM22': '$08',
+ 'TCCR2B_CS2': '$07',
+ 'TCNT2': '&178',
+ 'OCR2B': '&180',
+ 'OCR2A': '&179',
+ 'ASSR': '&182',
+ 'ASSR_EXCLK': '$40',
+ 'ASSR_AS2': '$20',
+ 'ASSR_TCN2UB': '$10',
+ 'ASSR_OCR2AUB': '$08',
+ 'ASSR_OCR2BUB': '$04',
+ 'ASSR_TCR2AUB': '$02',
+ 'ASSR_TCR2BUB': '$01',
+ 'ADMUX': '&124',
+ 'ADMUX_REFS': '$C0',
+ 'ADMUX_ADLAR': '$20',
+ 'ADMUX_MUX': '$0F',
+ 'ADC': '&120',
+ 'ADCSRA': '&122',
+ 'ADCSRA_ADEN': '$80',
+ 'ADCSRA_ADSC': '$40',
+ 'ADCSRA_ADATE': '$20',
+ 'ADCSRA_ADIF': '$10',
+ 'ADCSRA_ADIE': '$08',
+ 'ADCSRA_ADPS': '$07',
+ 'ADCSRB': '&123',
+ 'ADCSRB_ACME': '$40',
+ 'ADCSRB_ADTS': '$07',
+ 'DIDR0': '&126',
+ 'DIDR0_ADC5D': '$20',
+ 'DIDR0_ADC4D': '$10',
+ 'DIDR0_ADC3D': '$08',
+ 'DIDR0_ADC2D': '$04',
+ 'DIDR0_ADC1D': '$02',
+ 'DIDR0_ADC0D': '$01',
+ 'ACSR': '&80',
+ 'ACSR_ACD': '$80',
+ 'ACSR_ACBG': '$40',
+ 'ACSR_ACO': '$20',
+ 'ACSR_ACI': '$10',
+ 'ACSR_ACIE': '$08',
+ 'ACSR_ACIC': '$04',
+ 'ACSR_ACIS': '$03',
+ 'DIDR1': '&127',
+ 'DIDR1_AIN1D': '$02',
+ 'DIDR1_AIN0D': '$01',
+ 'PORTB': '&37',
+ 'DDRB': '&36',
+ 'PINB': '&35',
+ 'PORTC': '&40',
+ 'DDRC': '&39',
+ 'PINC': '&38',
+ 'PORTD': '&43',
+ 'DDRD': '&42',
+ 'PIND': '&41',
+ 'OCR0B': '&72',
+ 'OCR0A': '&71',
+ 'TCNT0': '&70',
+ 'TCCR0B': '&69',
+ 'TCCR0B_FOC0A': '$80',
+ 'TCCR0B_FOC0B': '$40',
+ 'TCCR0B_WGM02': '$08',
+ 'TCCR0B_CS0': '$07',
+ 'TCCR0A': '&68',
+ 'TCCR0A_COM0A': '$C0',
+ 'TCCR0A_COM0B': '$30',
+ 'TCCR0A_WGM0': '$03',
+ 'TIMSK0': '&110',
+ 'TIMSK0_OCIE0B': '$04',
+ 'TIMSK0_OCIE0A': '$02',
+ 'TIMSK0_TOIE0': '$01',
+ 'TIFR0': '&53',
+ 'TIFR0_OCF0B': '$04',
+ 'TIFR0_OCF0A': '$02',
+ 'TIFR0_TOV0': '$01',
+ 'EICRA': '&105',
+ 'EICRA_ISC1': '$0C',
+ 'EICRA_ISC0': '$03',
+ 'EIMSK': '&61',
+ 'EIMSK_INT': '$03',
+ 'EIFR': '&60',
+ 'EIFR_INTF': '$03',
+ 'PCICR': '&104',
+ 'PCICR_PCIE': '$07',
+ 'PCMSK2': '&109',
+ 'PCMSK2_PCINT': '$FF',
+ 'PCMSK1': '&108',
+ 'PCMSK1_PCINT': '$7F',
+ 'PCMSK0': '&107',
+ 'PCMSK0_PCINT': '$FF',
+ 'PCIFR': '&59',
+ 'PCIFR_PCIF': '$07',
+ 'SPDR': '&78',
+ 'SPSR': '&77',
+ 'SPSR_SPIF': '$80',
+ 'SPSR_WCOL': '$40',
+ 'SPSR_SPI2X': '$01',
+ 'SPCR': '&76',
+ 'SPCR_SPIE': '$80',
+ 'SPCR_SPE': '$40',
+ 'SPCR_DORD': '$20',
+ 'SPCR_MSTR': '$10',
+ 'SPCR_CPOL': '$08',
+ 'SPCR_CPHA': '$04',
+ 'SPCR_SPR': '$03',
+ 'WDTCSR': '&96',
+ 'WDTCSR_WDIF': '$80',
+ 'WDTCSR_WDIE': '$40',
+ 'WDTCSR_WDP': '$27',
+ 'WDTCSR_WDCE': '$10',
+ 'WDTCSR_WDE': '$08',
+ 'EEAR': '&65',
+ 'EEDR': '&64',
+ 'EECR': '&63',
+ 'EECR_EEPM': '$30',
+ 'EECR_EERIE': '$08',
+ 'EECR_EEMPE': '$04',
+ 'EECR_EEPE': '$02',
+ 'EECR_EERE': '$01',
+ 'PRR': '&100',
+ 'PRR_PRTWI': '$80',
+ 'PRR_PRTIM2': '$40',
+ 'PRR_PRTIM0': '$20',
+ 'PRR_PRTIM1': '$08',
+ 'PRR_PRSPI': '$04',
+ 'PRR_PRUSART0': '$02',
+ 'PRR_PRADC': '$01',
+ 'OSCCAL': '&102',
+ 'CLKPR': '&97',
+ 'CLKPR_CLKPCE': '$80',
+ 'CLKPR_CLKPS': '$0F',
+ 'SREG': '&95',
+ 'SREG_I': '$80',
+ 'SREG_T': '$40',
+ 'SREG_H': '$20',
+ 'SREG_S': '$10',
+ 'SREG_V': '$08',
+ 'SREG_N': '$04',
+ 'SREG_Z': '$02',
+ 'SREG_C': '$01',
+ 'SP': '&93',
+ 'SPMCSR': '&87',
+ 'SPMCSR_SPMIE': '$80',
+ 'SPMCSR_RWWSB': '$40',
+ 'SPMCSR_RWWSRE': '$10',
+ 'SPMCSR_BLBSET': '$08',
+ 'SPMCSR_PGWRT': '$04',
+ 'SPMCSR_PGERS': '$02',
+ 'SPMCSR_SELFPRGEN': '$01',
+ 'MCUCR': '&85',
+ 'MCUCR_PUD': '$10',
+ 'MCUCR_IVSEL': '$02',
+ 'MCUCR_IVCE': '$01',
+ 'MCUSR': '&84',
+ 'MCUSR_WDRF': '$08',
+ 'MCUSR_BORF': '$04',
+ 'MCUSR_EXTRF': '$02',
+ 'MCUSR_PORF': '$01',
+ 'SMCR': '&83',
+ 'SMCR_SM': '$0E',
+ 'SMCR_SE': '$01',
+ 'GPIOR2': '&75',
+ 'GPIOR1': '&74',
+ 'GPIOR0': '&62',
+ 'INT0Addr': '1',
+ 'INT1Addr': '2',
+ 'PCINT0Addr': '3',
+ 'PCINT1Addr': '4',
+ 'PCINT2Addr': '5',
+ 'WDTAddr': '6',
+ 'TIMER2_COMPAAddr': '7',
+ 'TIMER2_COMPBAddr': '8',
+ 'TIMER2_OVFAddr': '9',
+ 'TIMER1_CAPTAddr': '10',
+ 'TIMER1_COMPAAddr': '11',
+ 'TIMER1_COMPBAddr': '12',
+ 'TIMER1_OVFAddr': '13',
+ 'TIMER0_COMPAAddr': '14',
+ 'TIMER0_COMPBAddr': '15',
+ 'TIMER0_OVFAddr': '16',
+ 'SPI__STCAddr': '17',
+ 'USART__RXAddr': '18',
+ 'USART__UDREAddr': '19',
+ 'USART__TXAddr': '20',
+ 'ADCAddr': '21',
+ 'EE_READYAddr': '22',
+ 'ANALOG_COMPAddr': '23',
+ 'TWIAddr': '24',
+ 'SPM_ReadyAddr': '25'
+} \ No newline at end of file
diff --git a/amforth-6.5/avr8/devices/atmega88a/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega88a/words/no-jtag.asm
new file mode 100644
index 0000000..352a4bb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega88a/words/no-jtag.asm
@@ -0,0 +1,14 @@
+; ( -- )
+; ( -- )
+; MCU
+; disable jtag at runtime
+VE_NOJTAG:
+ .dw $FF05
+ .db "-jtag",0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOJTAG
+XT_NOJTAG:
+ .dw PFA_NOJTAG
+PFA_NOJTAG:
+
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega88a/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega88a/words/no-wdt.asm
new file mode 100644
index 0000000..ff6ddd1
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega88a/words/no-wdt.asm
@@ -0,0 +1,34 @@
+; ( -- )
+; MCU
+; disable watch dog timer at runtime
+VE_NOWDT:
+ .dw $ff04
+ .db "-wdt"
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOWDT
+XT_NOWDT:
+ .dw PFA_NOWDT
+PFA_NOWDT:
+
+ in temp1,SREG
+ push temp1
+ ; Turn always off global interrupt.
+ cli
+ ; Reset Watchdog Timer
+ wdr
+ ; Clear WDRF in MCUSR
+ in temp1, MCUSR
+ andi temp1, (0xff & (0<<WDRF))
+ out MCUSR, temp1
+ ; Write logical one to WDCE and WDE
+ ; Keep old prescaler setting to prevent unintentional time-out
+ in_ temp1, WDTCSR
+ ori temp1, (1<<WDCE) | (1<<WDE)
+ out_ WDTCSR, temp1
+ ; Turn off WDT
+ ldi temp1, (0<<WDE)
+ out_ WDTCSR, temp1
+ ; restore status register
+ pop temp1
+ out SREG,temp1
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega88a/words/sleep.asm b/amforth-6.5/avr8/devices/atmega88a/words/sleep.asm
new file mode 100644
index 0000000..256249c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega88a/words/sleep.asm
@@ -0,0 +1,19 @@
+; ( mode -- )
+; MCU
+; put the controller into the specified sleep mode
+VE_SLEEP:
+ .dw $ff05
+ .db "sleep", 0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_SLEEP
+XT_SLEEP:
+ .dw PFA_SLEEP
+PFA_SLEEP:
+ andi tosl, 7 ; leave only legal mode bits
+ lsl tosl ; move to correct location (bits 3-1)
+ ori tosl, 1 ; set the SE bit
+ out_ SMCR, tosl ; set the sleep config
+ sleep ; nighty-night
+ out_ SMCR, zerol ; 0 protects against accidental sleeps
+ loadtos ; pop argument from stack
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega88p/atmega88p.frt b/amforth-6.5/avr8/devices/atmega88p/atmega88p.frt
new file mode 100644
index 0000000..71d0ca2
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega88p/atmega88p.frt
@@ -0,0 +1,299 @@
+\ Partname: ATmega88P
+\ generated automatically
+
+\ USART0
+&198 constant UDR0 \ USART I/O Data Register
+&192 constant UCSR0A \ USART Control and Status Register A
+ $80 constant UCSR0A_RXC0 \ USART Receive Complete
+ $40 constant UCSR0A_TXC0 \ USART Transmitt Complete
+ $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
+ $10 constant UCSR0A_FE0 \ Framing Error
+ $08 constant UCSR0A_DOR0 \ Data overRun
+ $04 constant UCSR0A_UPE0 \ Parity Error
+ $02 constant UCSR0A_U2X0 \ Double the USART transmission speed
+ $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
+&193 constant UCSR0B \ USART Control and Status Register B
+ $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
+ $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
+ $20 constant UCSR0B_UDRIE0 \ USART Data register Empty Interrupt Enable
+ $10 constant UCSR0B_RXEN0 \ Receiver Enable
+ $08 constant UCSR0B_TXEN0 \ Transmitter Enable
+ $04 constant UCSR0B_UCSZ02 \ Character Size
+ $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
+ $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
+&194 constant UCSR0C \ USART Control and Status Register C
+ $C0 constant UCSR0C_UMSEL0 \ USART Mode Select
+ $30 constant UCSR0C_UPM0 \ Parity Mode Bits
+ $08 constant UCSR0C_USBS0 \ Stop Bit Select
+ $06 constant UCSR0C_UCSZ0 \ Character Size
+ $01 constant UCSR0C_UCPOL0 \ Clock Polarity
+&196 constant UBRR0 \ USART Baud Rate Register Bytes
+\ TWI
+&189 constant TWAMR \ TWI (Slave) Address Mask Register
+ $FE constant TWAMR_TWAM \
+&184 constant TWBR \ TWI Bit Rate register
+&188 constant TWCR \ TWI Control Register
+ $80 constant TWCR_TWINT \ TWI Interrupt Flag
+ $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
+ $20 constant TWCR_TWSTA \ TWI Start Condition Bit
+ $10 constant TWCR_TWSTO \ TWI Stop Condition Bit
+ $08 constant TWCR_TWWC \ TWI Write Collition Flag
+ $04 constant TWCR_TWEN \ TWI Enable Bit
+ $01 constant TWCR_TWIE \ TWI Interrupt Enable
+&185 constant TWSR \ TWI Status Register
+ $F8 constant TWSR_TWS \ TWI Status
+ $03 constant TWSR_TWPS \ TWI Prescaler
+&187 constant TWDR \ TWI Data register
+&186 constant TWAR \ TWI (Slave) Address register
+ $FE constant TWAR_TWA \ TWI (Slave) Address register Bits
+ $01 constant TWAR_TWGCE \ TWI General Call Recognition Enable Bit
+\ TIMER_COUNTER_1
+&111 constant TIMSK1 \ Timer/Counter Interrupt Mask Register
+ $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
+ $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output CompareB Match Interrupt Enable
+ $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output CompareA Match Interrupt Enable
+ $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
+&54 constant TIFR1 \ Timer/Counter Interrupt Flag register
+ $20 constant TIFR1_ICF1 \ Input Capture Flag 1
+ $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
+ $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
+ $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
+&128 constant TCCR1A \ Timer/Counter1 Control Register A
+ $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
+ $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
+ $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
+&129 constant TCCR1B \ Timer/Counter1 Control Register B
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
+ $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
+&130 constant TCCR1C \ Timer/Counter1 Control Register C
+ $80 constant TCCR1C_FOC1A \
+ $40 constant TCCR1C_FOC1B \
+&132 constant TCNT1 \ Timer/Counter1 Bytes
+&136 constant OCR1A \ Timer/Counter1 Output Compare Register Bytes
+&138 constant OCR1B \ Timer/Counter1 Output Compare Register Bytes
+&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
+&67 constant GTCCR \ General Timer/Counter Control Register
+ $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
+ $01 constant GTCCR_PSRSYNC \ Prescaler Reset Timer/Counter1 and Timer/Counter0
+\ TIMER_COUNTER_2
+&112 constant TIMSK2 \ Timer/Counter Interrupt Mask register
+ $04 constant TIMSK2_OCIE2B \ Timer/Counter2 Output Compare Match B Interrupt Enable
+ $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match A Interrupt Enable
+ $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
+&55 constant TIFR2 \ Timer/Counter Interrupt Flag Register
+ $04 constant TIFR2_OCF2B \ Output Compare Flag 2B
+ $02 constant TIFR2_OCF2A \ Output Compare Flag 2A
+ $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
+&176 constant TCCR2A \ Timer/Counter2 Control Register A
+ $C0 constant TCCR2A_COM2A \ Compare Output Mode bits
+ $30 constant TCCR2A_COM2B \ Compare Output Mode bits
+ $03 constant TCCR2A_WGM2 \ Waveform Genration Mode
+&177 constant TCCR2B \ Timer/Counter2 Control Register B
+ $80 constant TCCR2B_FOC2A \ Force Output Compare A
+ $40 constant TCCR2B_FOC2B \ Force Output Compare B
+ $08 constant TCCR2B_WGM22 \ Waveform Generation Mode
+ $07 constant TCCR2B_CS2 \ Clock Select bits
+&178 constant TCNT2 \ Timer/Counter2
+&180 constant OCR2B \ Timer/Counter2 Output Compare Register B
+&179 constant OCR2A \ Timer/Counter2 Output Compare Register A
+&182 constant ASSR \ Asynchronous Status Register
+ $40 constant ASSR_EXCLK \ Enable External Clock Input
+ $20 constant ASSR_AS2 \ Asynchronous Timer/Counter2
+ $10 constant ASSR_TCN2UB \ Timer/Counter2 Update Busy
+ $08 constant ASSR_OCR2AUB \ Output Compare Register2 Update Busy
+ $04 constant ASSR_OCR2BUB \ Output Compare Register 2 Update Busy
+ $02 constant ASSR_TCR2AUB \ Timer/Counter Control Register2 Update Busy
+ $01 constant ASSR_TCR2BUB \ Timer/Counter Control Register2 Update Busy
+\ AD_CONVERTER
+&124 constant ADMUX \ The ADC multiplexer Selection Register
+ $C0 constant ADMUX_REFS \ Reference Selection Bits
+ $20 constant ADMUX_ADLAR \ Left Adjust Result
+ $0F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
+&120 constant ADC \ ADC Data Register Bytes
+&122 constant ADCSRA \ The ADC Control and Status register A
+ $80 constant ADCSRA_ADEN \ ADC Enable
+ $40 constant ADCSRA_ADSC \ ADC Start Conversion
+ $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
+ $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
+ $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
+ $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
+&123 constant ADCSRB \ The ADC Control and Status register B
+ $40 constant ADCSRB_ACME \
+ $07 constant ADCSRB_ADTS \ ADC Auto Trigger Source bits
+&126 constant DIDR0 \ Digital Input Disable Register
+ $20 constant DIDR0_ADC5D \
+ $10 constant DIDR0_ADC4D \
+ $08 constant DIDR0_ADC3D \
+ $04 constant DIDR0_ADC2D \
+ $02 constant DIDR0_ADC1D \
+ $01 constant DIDR0_ADC0D \
+\ ANALOG_COMPARATOR
+&80 constant ACSR \ Analog Comparator Control And Status Register
+ $80 constant ACSR_ACD \ Analog Comparator Disable
+ $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
+ $20 constant ACSR_ACO \ Analog Compare Output
+ $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
+ $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
+ $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
+ $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
+&127 constant DIDR1 \ Digital Input Disable Register 1
+ $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
+ $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
+\ PORTB
+&37 constant PORTB \ Port B Data Register
+&36 constant DDRB \ Port B Data Direction Register
+&35 constant PINB \ Port B Input Pins
+\ PORTC
+&40 constant PORTC \ Port C Data Register
+&39 constant DDRC \ Port C Data Direction Register
+&38 constant PINC \ Port C Input Pins
+\ PORTD
+&43 constant PORTD \ Port D Data Register
+&42 constant DDRD \ Port D Data Direction Register
+&41 constant PIND \ Port D Input Pins
+\ TIMER_COUNTER_0
+&72 constant OCR0B \ Timer/Counter0 Output Compare Register
+&71 constant OCR0A \ Timer/Counter0 Output Compare Register
+&70 constant TCNT0 \ Timer/Counter0
+&69 constant TCCR0B \ Timer/Counter Control Register B
+ $80 constant TCCR0B_FOC0A \ Force Output Compare A
+ $40 constant TCCR0B_FOC0B \ Force Output Compare B
+ $08 constant TCCR0B_WGM02 \
+ $07 constant TCCR0B_CS0 \ Clock Select
+&68 constant TCCR0A \ Timer/Counter Control Register A
+ $C0 constant TCCR0A_COM0A \ Compare Output Mode, Phase Correct PWM Mode
+ $30 constant TCCR0A_COM0B \ Compare Output Mode, Fast PWm
+ $03 constant TCCR0A_WGM0 \ Waveform Generation Mode
+&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
+ $04 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare Match B Interrupt Enable
+ $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match A Interrupt Enable
+ $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
+&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
+ $04 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare Flag 0B
+ $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0A
+ $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
+\ EXTERNAL_INTERRUPT
+&105 constant EICRA \ External Interrupt Control Register
+ $0C constant EICRA_ISC1 \ External Interrupt Sense Control 1 Bits
+ $03 constant EICRA_ISC0 \ External Interrupt Sense Control 0 Bits
+&61 constant EIMSK \ External Interrupt Mask Register
+ $03 constant EIMSK_INT \ External Interrupt Request 1 Enable
+&60 constant EIFR \ External Interrupt Flag Register
+ $03 constant EIFR_INTF \ External Interrupt Flags
+&104 constant PCICR \ Pin Change Interrupt Control Register
+ $07 constant PCICR_PCIE \ Pin Change Interrupt Enables
+&109 constant PCMSK2 \ Pin Change Mask Register 2
+ $FF constant PCMSK2_PCINT \ Pin Change Enable Masks
+&108 constant PCMSK1 \ Pin Change Mask Register 1
+ $7F constant PCMSK1_PCINT \ Pin Change Enable Masks
+&107 constant PCMSK0 \ Pin Change Mask Register 0
+ $FF constant PCMSK0_PCINT \ Pin Change Enable Masks
+&59 constant PCIFR \ Pin Change Interrupt Flag Register
+ $07 constant PCIFR_PCIF \ Pin Change Interrupt Flags
+\ SPI
+&78 constant SPDR \ SPI Data Register
+&77 constant SPSR \ SPI Status Register
+ $80 constant SPSR_SPIF \ SPI Interrupt Flag
+ $40 constant SPSR_WCOL \ Write Collision Flag
+ $01 constant SPSR_SPI2X \ Double SPI Speed Bit
+&76 constant SPCR \ SPI Control Register
+ $80 constant SPCR_SPIE \ SPI Interrupt Enable
+ $40 constant SPCR_SPE \ SPI Enable
+ $20 constant SPCR_DORD \ Data Order
+ $10 constant SPCR_MSTR \ Master/Slave Select
+ $08 constant SPCR_CPOL \ Clock polarity
+ $04 constant SPCR_CPHA \ Clock Phase
+ $03 constant SPCR_SPR \ SPI Clock Rate Selects
+\ WATCHDOG
+&96 constant WDTCSR \ Watchdog Timer Control Register
+ $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Flag
+ $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Enable
+ $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
+ $10 constant WDTCSR_WDCE \ Watchdog Change Enable
+ $08 constant WDTCSR_WDE \ Watch Dog Enable
+\ EEPROM
+&65 constant EEAR \ EEPROM Address Register Bytes
+&64 constant EEDR \ EEPROM Data Register
+&63 constant EECR \ EEPROM Control Register
+ $30 constant EECR_EEPM \ EEPROM Programming Mode Bits
+ $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
+ $04 constant EECR_EEMPE \ EEPROM Master Write Enable
+ $02 constant EECR_EEPE \ EEPROM Write Enable
+ $01 constant EECR_EERE \ EEPROM Read Enable
+\ CPU
+&100 constant PRR \ Power Reduction Register
+ $80 constant PRR_PRTWI \ Power Reduction TWI
+ $40 constant PRR_PRTIM2 \ Power Reduction Timer/Counter2
+ $20 constant PRR_PRTIM0 \ Power Reduction Timer/Counter0
+ $08 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
+ $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
+ $02 constant PRR_PRUSART0 \ Power Reduction USART
+ $01 constant PRR_PRADC \ Power Reduction ADC
+&102 constant OSCCAL \ Oscillator Calibration Value
+&97 constant CLKPR \ Clock Prescale Register
+ $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable
+ $0F constant CLKPR_CLKPS \ Clock Prescaler Select Bits
+&95 constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ $08 constant SREG_V \ Two's Complement Overflow Flag
+ $04 constant SREG_N \ Negative Flag
+ $02 constant SREG_Z \ Zero Flag
+ $01 constant SREG_C \ Carry Flag
+&93 constant SP \ Stack Pointer
+&87 constant SPMCSR \ Store Program Memory Control and Status Register
+ $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCSR_RWWSB \ Read-While-Write Section Busy
+ $10 constant SPMCSR_RWWSRE \ Read-While-Write section read enable
+ $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
+ $04 constant SPMCSR_PGWRT \ Page Write
+ $02 constant SPMCSR_PGERS \ Page Erase
+ $01 constant SPMCSR_SELFPRGEN \ Self Programming Enable
+&85 constant MCUCR \ MCU Control Register
+ $40 constant MCUCR_BODS \ BOD Sleep
+ $20 constant MCUCR_BODSE \ BOD Sleep Enable
+ $10 constant MCUCR_PUD \
+ $02 constant MCUCR_IVSEL \
+ $01 constant MCUCR_IVCE \
+&84 constant MCUSR \ MCU Status Register
+ $08 constant MCUSR_WDRF \ Watchdog Reset Flag
+ $04 constant MCUSR_BORF \ Brown-out Reset Flag
+ $02 constant MCUSR_EXTRF \ External Reset Flag
+ $01 constant MCUSR_PORF \ Power-on reset flag
+&83 constant SMCR \ Sleep Mode Control Register
+ $0E constant SMCR_SM \ Sleep Mode Select Bits
+ $01 constant SMCR_SE \ Sleep Enable
+&75 constant GPIOR2 \ General Purpose I/O Register 2
+&74 constant GPIOR1 \ General Purpose I/O Register 1
+&62 constant GPIOR0 \ General Purpose I/O Register 0
+
+\ Interrupts
+&1 constant INT0Addr \ External Interrupt Request 0
+&2 constant INT1Addr \ External Interrupt Request 1
+&3 constant PCINT0Addr \ Pin Change Interrupt Request 0
+&4 constant PCINT1Addr \ Pin Change Interrupt Request 0
+&5 constant PCINT2Addr \ Pin Change Interrupt Request 1
+&6 constant WDTAddr \ Watchdog Time-out Interrupt
+&7 constant TIMER2_COMPAAddr \ Timer/Counter2 Compare Match A
+&8 constant TIMER2_COMPBAddr \ Timer/Counter2 Compare Match A
+&9 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
+&10 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+&11 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
+&12 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
+&13 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+&14 constant TIMER0_COMPAAddr \ TimerCounter0 Compare Match A
+&15 constant TIMER0_COMPBAddr \ TimerCounter0 Compare Match B
+&16 constant TIMER0_OVFAddr \ Timer/Couner0 Overflow
+&17 constant SPI__STCAddr \ SPI Serial Transfer Complete
+&18 constant USART__RXAddr \ USART Rx Complete
+&19 constant USART__UDREAddr \ USART, Data Register Empty
+&20 constant USART__TXAddr \ USART Tx Complete
+&21 constant ADCAddr \ ADC Conversion Complete
+&22 constant EE_READYAddr \ EEPROM Ready
+&23 constant ANALOG_COMPAddr \ Analog Comparator
+&24 constant TWIAddr \ Two-wire Serial Interface
+&25 constant SPM_ReadyAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/atmega88p/device.asm b/amforth-6.5/avr8/devices/atmega88p/device.asm
new file mode 100644
index 0000000..739b20c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega88p/device.asm
@@ -0,0 +1,107 @@
+; Partname: ATmega88P
+; generated automatically, do not edit
+
+.nolist
+ .include "m88Pdef.inc"
+.list
+
+.equ ramstart = 256
+.equ CELLSIZE = 2
+.macro readflashcell
+ lsl zl
+ rol zh
+ lpm @0, Z+
+ lpm @1, Z+
+.endmacro
+.macro writeflashcell
+ lsl zl
+ rol zh
+.endmacro
+.set WANT_USART0 = 0
+.set WANT_TWI = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_TIMER_COUNTER_2 = 0
+.set WANT_AD_CONVERTER = 0
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_PORTB = 0
+.set WANT_PORTC = 0
+.set WANT_PORTD = 0
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_SPI = 0
+.set WANT_WATCHDOG = 0
+.set WANT_EEPROM = 0
+.set WANT_CPU = 0
+.equ intvecsize = 1 ; please verify; flash size: 8192 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.org 1
+ rcall isr ; External Interrupt Request 0
+.org 2
+ rcall isr ; External Interrupt Request 1
+.org 3
+ rcall isr ; Pin Change Interrupt Request 0
+.org 4
+ rcall isr ; Pin Change Interrupt Request 0
+.org 5
+ rcall isr ; Pin Change Interrupt Request 1
+.org 6
+ rcall isr ; Watchdog Time-out Interrupt
+.org 7
+ rcall isr ; Timer/Counter2 Compare Match A
+.org 8
+ rcall isr ; Timer/Counter2 Compare Match A
+.org 9
+ rcall isr ; Timer/Counter2 Overflow
+.org 10
+ rcall isr ; Timer/Counter1 Capture Event
+.org 11
+ rcall isr ; Timer/Counter1 Compare Match A
+.org 12
+ rcall isr ; Timer/Counter1 Compare Match B
+.org 13
+ rcall isr ; Timer/Counter1 Overflow
+.org 14
+ rcall isr ; TimerCounter0 Compare Match A
+.org 15
+ rcall isr ; TimerCounter0 Compare Match B
+.org 16
+ rcall isr ; Timer/Couner0 Overflow
+.org 17
+ rcall isr ; SPI Serial Transfer Complete
+.org 18
+ rcall isr ; USART Rx Complete
+.org 19
+ rcall isr ; USART, Data Register Empty
+.org 20
+ rcall isr ; USART Tx Complete
+.org 21
+ rcall isr ; ADC Conversion Complete
+.org 22
+ rcall isr ; EEPROM Ready
+.org 23
+ rcall isr ; Analog Comparator
+.org 24
+ rcall isr ; Two-wire Serial Interface
+.org 25
+ rcall isr ; Store Program Memory Read
+.equ INTVECTORS = 26
+.nooverlap
+
+; compatability layer (maybe empty)
+.equ SPMEN = SELFPRGEN
+
+; controller data area, environment query mcu-info
+mcu_info:
+mcu_ramsize:
+ .dw 1024
+mcu_eepromsize:
+ .dw 512
+mcu_maxdp:
+ .dw 6144
+mcu_numints:
+ .dw 26
+mcu_name:
+ .dw 9
+ .db "ATmega88P",0
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega88p/device.inc b/amforth-6.5/avr8/devices/atmega88p/device.inc
new file mode 100644
index 0000000..97494c9
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega88p/device.inc
@@ -0,0 +1,996 @@
+; Partname: ATmega88P
+; generated automatically, no not edit
+
+.if WANT_USART0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR0:
+ .dw $ff04
+ .db "UDR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR0
+XT_UDR0:
+ .dw PFA_DOVARIABLE
+PFA_UDR0:
+ .dw 198
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR0A:
+ .dw $ff06
+ .db "UCSR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0A
+XT_UCSR0A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0A:
+ .dw 192
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR0B:
+ .dw $ff06
+ .db "UCSR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0B
+XT_UCSR0B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0B:
+ .dw 193
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR0C:
+ .dw $ff06
+ .db "UCSR0C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0C
+XT_UCSR0C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0C:
+ .dw 194
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Bytes
+VE_UBRR0:
+ .dw $ff05
+ .db "UBRR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR0
+XT_UBRR0:
+ .dw PFA_DOVARIABLE
+PFA_UBRR0:
+ .dw 196
+
+.endif
+.if WANT_TWI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; TWI (Slave) Address Mask Register
+VE_TWAMR:
+ .dw $ff05
+ .db "TWAMR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWAMR
+XT_TWAMR:
+ .dw PFA_DOVARIABLE
+PFA_TWAMR:
+ .dw 189
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Bit Rate register
+VE_TWBR:
+ .dw $ff04
+ .db "TWBR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWBR
+XT_TWBR:
+ .dw PFA_DOVARIABLE
+PFA_TWBR:
+ .dw 184
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Control Register
+VE_TWCR:
+ .dw $ff04
+ .db "TWCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWCR
+XT_TWCR:
+ .dw PFA_DOVARIABLE
+PFA_TWCR:
+ .dw 188
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Status Register
+VE_TWSR:
+ .dw $ff04
+ .db "TWSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWSR
+XT_TWSR:
+ .dw PFA_DOVARIABLE
+PFA_TWSR:
+ .dw 185
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Data register
+VE_TWDR:
+ .dw $ff04
+ .db "TWDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWDR
+XT_TWDR:
+ .dw PFA_DOVARIABLE
+PFA_TWDR:
+ .dw 187
+; ( -- addr ) System Constant
+; R( -- )
+; TWI (Slave) Address register
+VE_TWAR:
+ .dw $ff04
+ .db "TWAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWAR
+XT_TWAR:
+ .dw PFA_DOVARIABLE
+PFA_TWAR:
+ .dw 186
+
+.endif
+.if WANT_TIMER_COUNTER_1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Mask Register
+VE_TIMSK1:
+ .dw $ff06
+ .db "TIMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK1
+XT_TIMSK1:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK1:
+ .dw 111
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Flag register
+VE_TIFR1:
+ .dw $ff05
+ .db "TIFR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR1
+XT_TIFR1:
+ .dw PFA_DOVARIABLE
+PFA_TIFR1:
+ .dw 54
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw 128
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw 129
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register C
+VE_TCCR1C:
+ .dw $ff06
+ .db "TCCR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1C
+XT_TCCR1C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1C:
+ .dw 130
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Bytes
+VE_TCNT1:
+ .dw $ff05
+ .db "TCNT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1
+XT_TCNT1:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1:
+ .dw 132
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register Bytes
+VE_OCR1A:
+ .dw $ff05
+ .db "OCR1A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1A
+XT_OCR1A:
+ .dw PFA_DOVARIABLE
+PFA_OCR1A:
+ .dw 136
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register Bytes
+VE_OCR1B:
+ .dw $ff05
+ .db "OCR1B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1B
+XT_OCR1B:
+ .dw PFA_DOVARIABLE
+PFA_OCR1B:
+ .dw 138
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Bytes
+VE_ICR1:
+ .dw $ff04
+ .db "ICR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1
+XT_ICR1:
+ .dw PFA_DOVARIABLE
+PFA_ICR1:
+ .dw 134
+; ( -- addr ) System Constant
+; R( -- )
+; General Timer/Counter Control Register
+VE_GTCCR:
+ .dw $ff05
+ .db "GTCCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GTCCR
+XT_GTCCR:
+ .dw PFA_DOVARIABLE
+PFA_GTCCR:
+ .dw 67
+
+.endif
+.if WANT_TIMER_COUNTER_2 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Mask register
+VE_TIMSK2:
+ .dw $ff06
+ .db "TIMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK2
+XT_TIMSK2:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK2:
+ .dw 112
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Flag Register
+VE_TIFR2:
+ .dw $ff05
+ .db "TIFR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR2
+XT_TIFR2:
+ .dw PFA_DOVARIABLE
+PFA_TIFR2:
+ .dw 55
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register A
+VE_TCCR2A:
+ .dw $ff06
+ .db "TCCR2A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2A
+XT_TCCR2A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2A:
+ .dw 176
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register B
+VE_TCCR2B:
+ .dw $ff06
+ .db "TCCR2B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2B
+XT_TCCR2B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2B:
+ .dw 177
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2
+VE_TCNT2:
+ .dw $ff05
+ .db "TCNT2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT2
+XT_TCNT2:
+ .dw PFA_DOVARIABLE
+PFA_TCNT2:
+ .dw 178
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register B
+VE_OCR2B:
+ .dw $ff05
+ .db "OCR2B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2B
+XT_OCR2B:
+ .dw PFA_DOVARIABLE
+PFA_OCR2B:
+ .dw 180
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register A
+VE_OCR2A:
+ .dw $ff05
+ .db "OCR2A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2A
+XT_OCR2A:
+ .dw PFA_DOVARIABLE
+PFA_OCR2A:
+ .dw 179
+; ( -- addr ) System Constant
+; R( -- )
+; Asynchronous Status Register
+VE_ASSR:
+ .dw $ff04
+ .db "ASSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ASSR
+XT_ASSR:
+ .dw PFA_DOVARIABLE
+PFA_ASSR:
+ .dw 182
+
+.endif
+.if WANT_AD_CONVERTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC multiplexer Selection Register
+VE_ADMUX:
+ .dw $ff05
+ .db "ADMUX",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADMUX
+XT_ADMUX:
+ .dw PFA_DOVARIABLE
+PFA_ADMUX:
+ .dw 124
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register Bytes
+VE_ADC:
+ .dw $ff03
+ .db "ADC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADC
+XT_ADC:
+ .dw PFA_DOVARIABLE
+PFA_ADC:
+ .dw 120
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register A
+VE_ADCSRA:
+ .dw $ff06
+ .db "ADCSRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRA
+XT_ADCSRA:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRA:
+ .dw 122
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register B
+VE_ADCSRB:
+ .dw $ff06
+ .db "ADCSRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRB
+XT_ADCSRB:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRB:
+ .dw 123
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register
+VE_DIDR0:
+ .dw $ff05
+ .db "DIDR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR0
+XT_DIDR0:
+ .dw PFA_DOVARIABLE
+PFA_DIDR0:
+ .dw 126
+
+.endif
+.if WANT_ANALOG_COMPARATOR == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Control And Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw 80
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 1
+VE_DIDR1:
+ .dw $ff05
+ .db "DIDR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR1
+XT_DIDR1:
+ .dw PFA_DOVARIABLE
+PFA_DIDR1:
+ .dw 127
+
+.endif
+.if WANT_PORTB == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw 37
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw 36
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw 35
+
+.endif
+.if WANT_PORTC == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Register
+VE_PORTC:
+ .dw $ff05
+ .db "PORTC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTC
+XT_PORTC:
+ .dw PFA_DOVARIABLE
+PFA_PORTC:
+ .dw 40
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Direction Register
+VE_DDRC:
+ .dw $ff04
+ .db "DDRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRC
+XT_DDRC:
+ .dw PFA_DOVARIABLE
+PFA_DDRC:
+ .dw 39
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Input Pins
+VE_PINC:
+ .dw $ff04
+ .db "PINC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINC
+XT_PINC:
+ .dw PFA_DOVARIABLE
+PFA_PINC:
+ .dw 38
+
+.endif
+.if WANT_PORTD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw 43
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw 42
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw 41
+
+.endif
+.if WANT_TIMER_COUNTER_0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0B:
+ .dw $ff05
+ .db "OCR0B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0B
+XT_OCR0B:
+ .dw PFA_DOVARIABLE
+PFA_OCR0B:
+ .dw 72
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0A:
+ .dw $ff05
+ .db "OCR0A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0A
+XT_OCR0A:
+ .dw PFA_DOVARIABLE
+PFA_OCR0A:
+ .dw 71
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw 70
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register B
+VE_TCCR0B:
+ .dw $ff06
+ .db "TCCR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0B
+XT_TCCR0B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0B:
+ .dw 69
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register A
+VE_TCCR0A:
+ .dw $ff06
+ .db "TCCR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0A
+XT_TCCR0A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0A:
+ .dw 68
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Mask Register
+VE_TIMSK0:
+ .dw $ff06
+ .db "TIMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK0
+XT_TIMSK0:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK0:
+ .dw 110
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Flag register
+VE_TIFR0:
+ .dw $ff05
+ .db "TIFR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR0
+XT_TIFR0:
+ .dw PFA_DOVARIABLE
+PFA_TIFR0:
+ .dw 53
+
+.endif
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register
+VE_EICRA:
+ .dw $ff05
+ .db "EICRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRA
+XT_EICRA:
+ .dw PFA_DOVARIABLE
+PFA_EICRA:
+ .dw 105
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Mask Register
+VE_EIMSK:
+ .dw $ff05
+ .db "EIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIMSK
+XT_EIMSK:
+ .dw PFA_DOVARIABLE
+PFA_EIMSK:
+ .dw 61
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Flag Register
+VE_EIFR:
+ .dw $ff04
+ .db "EIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIFR
+XT_EIFR:
+ .dw PFA_DOVARIABLE
+PFA_EIFR:
+ .dw 60
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Interrupt Control Register
+VE_PCICR:
+ .dw $ff05
+ .db "PCICR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCICR
+XT_PCICR:
+ .dw PFA_DOVARIABLE
+PFA_PCICR:
+ .dw 104
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 2
+VE_PCMSK2:
+ .dw $ff06
+ .db "PCMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK2
+XT_PCMSK2:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK2:
+ .dw 109
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 1
+VE_PCMSK1:
+ .dw $ff06
+ .db "PCMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK1
+XT_PCMSK1:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK1:
+ .dw 108
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 0
+VE_PCMSK0:
+ .dw $ff06
+ .db "PCMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK0
+XT_PCMSK0:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK0:
+ .dw 107
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Interrupt Flag Register
+VE_PCIFR:
+ .dw $ff05
+ .db "PCIFR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCIFR
+XT_PCIFR:
+ .dw PFA_DOVARIABLE
+PFA_PCIFR:
+ .dw 59
+
+.endif
+.if WANT_SPI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR:
+ .dw $ff04
+ .db "SPDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR
+XT_SPDR:
+ .dw PFA_DOVARIABLE
+PFA_SPDR:
+ .dw 78
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR:
+ .dw $ff04
+ .db "SPSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR
+XT_SPSR:
+ .dw PFA_DOVARIABLE
+PFA_SPSR:
+ .dw 77
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR:
+ .dw $ff04
+ .db "SPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR
+XT_SPCR:
+ .dw PFA_DOVARIABLE
+PFA_SPCR:
+ .dw 76
+
+.endif
+.if WANT_WATCHDOG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCSR:
+ .dw $ff06
+ .db "WDTCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCSR
+XT_WDTCSR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCSR:
+ .dw 96
+
+.endif
+.if WANT_EEPROM == 1
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Address Register Bytes
+VE_EEAR:
+ .dw $ff04
+ .db "EEAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEAR
+XT_EEAR:
+ .dw PFA_DOVARIABLE
+PFA_EEAR:
+ .dw 65
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw 64
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw 63
+
+.endif
+.if WANT_CPU == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register
+VE_PRR:
+ .dw $ff03
+ .db "PRR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR
+XT_PRR:
+ .dw PFA_DOVARIABLE
+PFA_PRR:
+ .dw 100
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Calibration Value
+VE_OSCCAL:
+ .dw $ff06
+ .db "OSCCAL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSCCAL
+XT_OSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_OSCCAL:
+ .dw 102
+; ( -- addr ) System Constant
+; R( -- )
+; Clock Prescale Register
+VE_CLKPR:
+ .dw $ff05
+ .db "CLKPR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKPR
+XT_CLKPR:
+ .dw PFA_DOVARIABLE
+PFA_CLKPR:
+ .dw 97
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw 95
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer
+VE_SP:
+ .dw $ff02
+ .db "SP"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SP
+XT_SP:
+ .dw PFA_DOVARIABLE
+PFA_SP:
+ .dw 93
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control and Status Register
+VE_SPMCSR:
+ .dw $ff06
+ .db "SPMCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCSR
+XT_SPMCSR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCSR:
+ .dw 87
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw 85
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Status Register
+VE_MCUSR:
+ .dw $ff05
+ .db "MCUSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUSR
+XT_MCUSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUSR:
+ .dw 84
+; ( -- addr ) System Constant
+; R( -- )
+; Sleep Mode Control Register
+VE_SMCR:
+ .dw $ff04
+ .db "SMCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SMCR
+XT_SMCR:
+ .dw PFA_DOVARIABLE
+PFA_SMCR:
+ .dw 83
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose I/O Register 2
+VE_GPIOR2:
+ .dw $ff06
+ .db "GPIOR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR2
+XT_GPIOR2:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR2:
+ .dw 75
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose I/O Register 1
+VE_GPIOR1:
+ .dw $ff06
+ .db "GPIOR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR1
+XT_GPIOR1:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR1:
+ .dw 74
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose I/O Register 0
+VE_GPIOR0:
+ .dw $ff06
+ .db "GPIOR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR0
+XT_GPIOR0:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR0:
+ .dw 62
+
+.endif
diff --git a/amforth-6.5/avr8/devices/atmega88p/device.py b/amforth-6.5/avr8/devices/atmega88p/device.py
new file mode 100644
index 0000000..79aac62
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega88p/device.py
@@ -0,0 +1,283 @@
+# Partname: ATmega88P
+# generated automatically, do not edit
+MCUREGS = {
+ 'UDR0': '&198',
+ 'UCSR0A': '&192',
+ 'UCSR0A_RXC0': '$80',
+ 'UCSR0A_TXC0': '$40',
+ 'UCSR0A_UDRE0': '$20',
+ 'UCSR0A_FE0': '$10',
+ 'UCSR0A_DOR0': '$08',
+ 'UCSR0A_UPE0': '$04',
+ 'UCSR0A_U2X0': '$02',
+ 'UCSR0A_MPCM0': '$01',
+ 'UCSR0B': '&193',
+ 'UCSR0B_RXCIE0': '$80',
+ 'UCSR0B_TXCIE0': '$40',
+ 'UCSR0B_UDRIE0': '$20',
+ 'UCSR0B_RXEN0': '$10',
+ 'UCSR0B_TXEN0': '$08',
+ 'UCSR0B_UCSZ02': '$04',
+ 'UCSR0B_RXB80': '$02',
+ 'UCSR0B_TXB80': '$01',
+ 'UCSR0C': '&194',
+ 'UCSR0C_UMSEL0': '$C0',
+ 'UCSR0C_UPM0': '$30',
+ 'UCSR0C_USBS0': '$08',
+ 'UCSR0C_UCSZ0': '$06',
+ 'UCSR0C_UCPOL0': '$01',
+ 'UBRR0': '&196',
+ 'TWAMR': '&189',
+ 'TWAMR_TWAM': '$FE',
+ 'TWBR': '&184',
+ 'TWCR': '&188',
+ 'TWCR_TWINT': '$80',
+ 'TWCR_TWEA': '$40',
+ 'TWCR_TWSTA': '$20',
+ 'TWCR_TWSTO': '$10',
+ 'TWCR_TWWC': '$08',
+ 'TWCR_TWEN': '$04',
+ 'TWCR_TWIE': '$01',
+ 'TWSR': '&185',
+ 'TWSR_TWS': '$F8',
+ 'TWSR_TWPS': '$03',
+ 'TWDR': '&187',
+ 'TWAR': '&186',
+ 'TWAR_TWA': '$FE',
+ 'TWAR_TWGCE': '$01',
+ 'TIMSK1': '&111',
+ 'TIMSK1_ICIE1': '$20',
+ 'TIMSK1_OCIE1B': '$04',
+ 'TIMSK1_OCIE1A': '$02',
+ 'TIMSK1_TOIE1': '$01',
+ 'TIFR1': '&54',
+ 'TIFR1_ICF1': '$20',
+ 'TIFR1_OCF1B': '$04',
+ 'TIFR1_OCF1A': '$02',
+ 'TIFR1_TOV1': '$01',
+ 'TCCR1A': '&128',
+ 'TCCR1A_COM1A': '$C0',
+ 'TCCR1A_COM1B': '$30',
+ 'TCCR1A_WGM1': '$03',
+ 'TCCR1B': '&129',
+ 'TCCR1B_ICNC1': '$80',
+ 'TCCR1B_ICES1': '$40',
+ 'TCCR1B_WGM1': '$18',
+ 'TCCR1B_CS1': '$07',
+ 'TCCR1C': '&130',
+ 'TCCR1C_FOC1A': '$80',
+ 'TCCR1C_FOC1B': '$40',
+ 'TCNT1': '&132',
+ 'OCR1A': '&136',
+ 'OCR1B': '&138',
+ 'ICR1': '&134',
+ 'GTCCR': '&67',
+ 'GTCCR_TSM': '$80',
+ 'GTCCR_PSRSYNC': '$01',
+ 'TIMSK2': '&112',
+ 'TIMSK2_OCIE2B': '$04',
+ 'TIMSK2_OCIE2A': '$02',
+ 'TIMSK2_TOIE2': '$01',
+ 'TIFR2': '&55',
+ 'TIFR2_OCF2B': '$04',
+ 'TIFR2_OCF2A': '$02',
+ 'TIFR2_TOV2': '$01',
+ 'TCCR2A': '&176',
+ 'TCCR2A_COM2A': '$C0',
+ 'TCCR2A_COM2B': '$30',
+ 'TCCR2A_WGM2': '$03',
+ 'TCCR2B': '&177',
+ 'TCCR2B_FOC2A': '$80',
+ 'TCCR2B_FOC2B': '$40',
+ 'TCCR2B_WGM22': '$08',
+ 'TCCR2B_CS2': '$07',
+ 'TCNT2': '&178',
+ 'OCR2B': '&180',
+ 'OCR2A': '&179',
+ 'ASSR': '&182',
+ 'ASSR_EXCLK': '$40',
+ 'ASSR_AS2': '$20',
+ 'ASSR_TCN2UB': '$10',
+ 'ASSR_OCR2AUB': '$08',
+ 'ASSR_OCR2BUB': '$04',
+ 'ASSR_TCR2AUB': '$02',
+ 'ASSR_TCR2BUB': '$01',
+ 'ADMUX': '&124',
+ 'ADMUX_REFS': '$C0',
+ 'ADMUX_ADLAR': '$20',
+ 'ADMUX_MUX': '$0F',
+ 'ADC': '&120',
+ 'ADCSRA': '&122',
+ 'ADCSRA_ADEN': '$80',
+ 'ADCSRA_ADSC': '$40',
+ 'ADCSRA_ADATE': '$20',
+ 'ADCSRA_ADIF': '$10',
+ 'ADCSRA_ADIE': '$08',
+ 'ADCSRA_ADPS': '$07',
+ 'ADCSRB': '&123',
+ 'ADCSRB_ACME': '$40',
+ 'ADCSRB_ADTS': '$07',
+ 'DIDR0': '&126',
+ 'DIDR0_ADC5D': '$20',
+ 'DIDR0_ADC4D': '$10',
+ 'DIDR0_ADC3D': '$08',
+ 'DIDR0_ADC2D': '$04',
+ 'DIDR0_ADC1D': '$02',
+ 'DIDR0_ADC0D': '$01',
+ 'ACSR': '&80',
+ 'ACSR_ACD': '$80',
+ 'ACSR_ACBG': '$40',
+ 'ACSR_ACO': '$20',
+ 'ACSR_ACI': '$10',
+ 'ACSR_ACIE': '$08',
+ 'ACSR_ACIC': '$04',
+ 'ACSR_ACIS': '$03',
+ 'DIDR1': '&127',
+ 'DIDR1_AIN1D': '$02',
+ 'DIDR1_AIN0D': '$01',
+ 'PORTB': '&37',
+ 'DDRB': '&36',
+ 'PINB': '&35',
+ 'PORTC': '&40',
+ 'DDRC': '&39',
+ 'PINC': '&38',
+ 'PORTD': '&43',
+ 'DDRD': '&42',
+ 'PIND': '&41',
+ 'OCR0B': '&72',
+ 'OCR0A': '&71',
+ 'TCNT0': '&70',
+ 'TCCR0B': '&69',
+ 'TCCR0B_FOC0A': '$80',
+ 'TCCR0B_FOC0B': '$40',
+ 'TCCR0B_WGM02': '$08',
+ 'TCCR0B_CS0': '$07',
+ 'TCCR0A': '&68',
+ 'TCCR0A_COM0A': '$C0',
+ 'TCCR0A_COM0B': '$30',
+ 'TCCR0A_WGM0': '$03',
+ 'TIMSK0': '&110',
+ 'TIMSK0_OCIE0B': '$04',
+ 'TIMSK0_OCIE0A': '$02',
+ 'TIMSK0_TOIE0': '$01',
+ 'TIFR0': '&53',
+ 'TIFR0_OCF0B': '$04',
+ 'TIFR0_OCF0A': '$02',
+ 'TIFR0_TOV0': '$01',
+ 'EICRA': '&105',
+ 'EICRA_ISC1': '$0C',
+ 'EICRA_ISC0': '$03',
+ 'EIMSK': '&61',
+ 'EIMSK_INT': '$03',
+ 'EIFR': '&60',
+ 'EIFR_INTF': '$03',
+ 'PCICR': '&104',
+ 'PCICR_PCIE': '$07',
+ 'PCMSK2': '&109',
+ 'PCMSK2_PCINT': '$FF',
+ 'PCMSK1': '&108',
+ 'PCMSK1_PCINT': '$7F',
+ 'PCMSK0': '&107',
+ 'PCMSK0_PCINT': '$FF',
+ 'PCIFR': '&59',
+ 'PCIFR_PCIF': '$07',
+ 'SPDR': '&78',
+ 'SPSR': '&77',
+ 'SPSR_SPIF': '$80',
+ 'SPSR_WCOL': '$40',
+ 'SPSR_SPI2X': '$01',
+ 'SPCR': '&76',
+ 'SPCR_SPIE': '$80',
+ 'SPCR_SPE': '$40',
+ 'SPCR_DORD': '$20',
+ 'SPCR_MSTR': '$10',
+ 'SPCR_CPOL': '$08',
+ 'SPCR_CPHA': '$04',
+ 'SPCR_SPR': '$03',
+ 'WDTCSR': '&96',
+ 'WDTCSR_WDIF': '$80',
+ 'WDTCSR_WDIE': '$40',
+ 'WDTCSR_WDP': '$27',
+ 'WDTCSR_WDCE': '$10',
+ 'WDTCSR_WDE': '$08',
+ 'EEAR': '&65',
+ 'EEDR': '&64',
+ 'EECR': '&63',
+ 'EECR_EEPM': '$30',
+ 'EECR_EERIE': '$08',
+ 'EECR_EEMPE': '$04',
+ 'EECR_EEPE': '$02',
+ 'EECR_EERE': '$01',
+ 'PRR': '&100',
+ 'PRR_PRTWI': '$80',
+ 'PRR_PRTIM2': '$40',
+ 'PRR_PRTIM0': '$20',
+ 'PRR_PRTIM1': '$08',
+ 'PRR_PRSPI': '$04',
+ 'PRR_PRUSART0': '$02',
+ 'PRR_PRADC': '$01',
+ 'OSCCAL': '&102',
+ 'CLKPR': '&97',
+ 'CLKPR_CLKPCE': '$80',
+ 'CLKPR_CLKPS': '$0F',
+ 'SREG': '&95',
+ 'SREG_I': '$80',
+ 'SREG_T': '$40',
+ 'SREG_H': '$20',
+ 'SREG_S': '$10',
+ 'SREG_V': '$08',
+ 'SREG_N': '$04',
+ 'SREG_Z': '$02',
+ 'SREG_C': '$01',
+ 'SP': '&93',
+ 'SPMCSR': '&87',
+ 'SPMCSR_SPMIE': '$80',
+ 'SPMCSR_RWWSB': '$40',
+ 'SPMCSR_RWWSRE': '$10',
+ 'SPMCSR_BLBSET': '$08',
+ 'SPMCSR_PGWRT': '$04',
+ 'SPMCSR_PGERS': '$02',
+ 'SPMCSR_SELFPRGEN': '$01',
+ 'MCUCR': '&85',
+ 'MCUCR_BODS': '$40',
+ 'MCUCR_BODSE': '$20',
+ 'MCUCR_PUD': '$10',
+ 'MCUCR_IVSEL': '$02',
+ 'MCUCR_IVCE': '$01',
+ 'MCUSR': '&84',
+ 'MCUSR_WDRF': '$08',
+ 'MCUSR_BORF': '$04',
+ 'MCUSR_EXTRF': '$02',
+ 'MCUSR_PORF': '$01',
+ 'SMCR': '&83',
+ 'SMCR_SM': '$0E',
+ 'SMCR_SE': '$01',
+ 'GPIOR2': '&75',
+ 'GPIOR1': '&74',
+ 'GPIOR0': '&62',
+ 'INT0Addr': '1',
+ 'INT1Addr': '2',
+ 'PCINT0Addr': '3',
+ 'PCINT1Addr': '4',
+ 'PCINT2Addr': '5',
+ 'WDTAddr': '6',
+ 'TIMER2_COMPAAddr': '7',
+ 'TIMER2_COMPBAddr': '8',
+ 'TIMER2_OVFAddr': '9',
+ 'TIMER1_CAPTAddr': '10',
+ 'TIMER1_COMPAAddr': '11',
+ 'TIMER1_COMPBAddr': '12',
+ 'TIMER1_OVFAddr': '13',
+ 'TIMER0_COMPAAddr': '14',
+ 'TIMER0_COMPBAddr': '15',
+ 'TIMER0_OVFAddr': '16',
+ 'SPI__STCAddr': '17',
+ 'USART__RXAddr': '18',
+ 'USART__UDREAddr': '19',
+ 'USART__TXAddr': '20',
+ 'ADCAddr': '21',
+ 'EE_READYAddr': '22',
+ 'ANALOG_COMPAddr': '23',
+ 'TWIAddr': '24',
+ 'SPM_ReadyAddr': '25'
+} \ No newline at end of file
diff --git a/amforth-6.5/avr8/devices/atmega88p/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega88p/words/no-jtag.asm
new file mode 100644
index 0000000..352a4bb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega88p/words/no-jtag.asm
@@ -0,0 +1,14 @@
+; ( -- )
+; ( -- )
+; MCU
+; disable jtag at runtime
+VE_NOJTAG:
+ .dw $FF05
+ .db "-jtag",0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOJTAG
+XT_NOJTAG:
+ .dw PFA_NOJTAG
+PFA_NOJTAG:
+
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega88p/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega88p/words/no-wdt.asm
new file mode 100644
index 0000000..ff6ddd1
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega88p/words/no-wdt.asm
@@ -0,0 +1,34 @@
+; ( -- )
+; MCU
+; disable watch dog timer at runtime
+VE_NOWDT:
+ .dw $ff04
+ .db "-wdt"
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOWDT
+XT_NOWDT:
+ .dw PFA_NOWDT
+PFA_NOWDT:
+
+ in temp1,SREG
+ push temp1
+ ; Turn always off global interrupt.
+ cli
+ ; Reset Watchdog Timer
+ wdr
+ ; Clear WDRF in MCUSR
+ in temp1, MCUSR
+ andi temp1, (0xff & (0<<WDRF))
+ out MCUSR, temp1
+ ; Write logical one to WDCE and WDE
+ ; Keep old prescaler setting to prevent unintentional time-out
+ in_ temp1, WDTCSR
+ ori temp1, (1<<WDCE) | (1<<WDE)
+ out_ WDTCSR, temp1
+ ; Turn off WDT
+ ldi temp1, (0<<WDE)
+ out_ WDTCSR, temp1
+ ; restore status register
+ pop temp1
+ out SREG,temp1
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega88p/words/sleep.asm b/amforth-6.5/avr8/devices/atmega88p/words/sleep.asm
new file mode 100644
index 0000000..256249c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega88p/words/sleep.asm
@@ -0,0 +1,19 @@
+; ( mode -- )
+; MCU
+; put the controller into the specified sleep mode
+VE_SLEEP:
+ .dw $ff05
+ .db "sleep", 0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_SLEEP
+XT_SLEEP:
+ .dw PFA_SLEEP
+PFA_SLEEP:
+ andi tosl, 7 ; leave only legal mode bits
+ lsl tosl ; move to correct location (bits 3-1)
+ ori tosl, 1 ; set the SE bit
+ out_ SMCR, tosl ; set the sleep config
+ sleep ; nighty-night
+ out_ SMCR, zerol ; 0 protects against accidental sleeps
+ loadtos ; pop argument from stack
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega88pa/atmega88pa.frt b/amforth-6.5/avr8/devices/atmega88pa/atmega88pa.frt
new file mode 100644
index 0000000..e401789
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega88pa/atmega88pa.frt
@@ -0,0 +1,299 @@
+\ Partname: ATmega88PA
+\ generated automatically
+
+\ USART0
+&198 constant UDR0 \ USART I/O Data Register
+&192 constant UCSR0A \ USART Control and Status Register A
+ $80 constant UCSR0A_RXC0 \ USART Receive Complete
+ $40 constant UCSR0A_TXC0 \ USART Transmitt Complete
+ $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
+ $10 constant UCSR0A_FE0 \ Framing Error
+ $08 constant UCSR0A_DOR0 \ Data overRun
+ $04 constant UCSR0A_UPE0 \ Parity Error
+ $02 constant UCSR0A_U2X0 \ Double the USART transmission speed
+ $01 constant UCSR0A_MPCM0 \ Multi-processor Communication Mode
+&193 constant UCSR0B \ USART Control and Status Register B
+ $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
+ $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
+ $20 constant UCSR0B_UDRIE0 \ USART Data register Empty Interrupt Enable
+ $10 constant UCSR0B_RXEN0 \ Receiver Enable
+ $08 constant UCSR0B_TXEN0 \ Transmitter Enable
+ $04 constant UCSR0B_UCSZ02 \ Character Size
+ $02 constant UCSR0B_RXB80 \ Receive Data Bit 8
+ $01 constant UCSR0B_TXB80 \ Transmit Data Bit 8
+&194 constant UCSR0C \ USART Control and Status Register C
+ $C0 constant UCSR0C_UMSEL0 \ USART Mode Select
+ $30 constant UCSR0C_UPM0 \ Parity Mode Bits
+ $08 constant UCSR0C_USBS0 \ Stop Bit Select
+ $06 constant UCSR0C_UCSZ0 \ Character Size
+ $01 constant UCSR0C_UCPOL0 \ Clock Polarity
+&196 constant UBRR0 \ USART Baud Rate Register Bytes
+\ TWI
+&189 constant TWAMR \ TWI (Slave) Address Mask Register
+ $FE constant TWAMR_TWAM \
+&184 constant TWBR \ TWI Bit Rate register
+&188 constant TWCR \ TWI Control Register
+ $80 constant TWCR_TWINT \ TWI Interrupt Flag
+ $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
+ $20 constant TWCR_TWSTA \ TWI Start Condition Bit
+ $10 constant TWCR_TWSTO \ TWI Stop Condition Bit
+ $08 constant TWCR_TWWC \ TWI Write Collition Flag
+ $04 constant TWCR_TWEN \ TWI Enable Bit
+ $01 constant TWCR_TWIE \ TWI Interrupt Enable
+&185 constant TWSR \ TWI Status Register
+ $F8 constant TWSR_TWS \ TWI Status
+ $03 constant TWSR_TWPS \ TWI Prescaler
+&187 constant TWDR \ TWI Data register
+&186 constant TWAR \ TWI (Slave) Address register
+ $FE constant TWAR_TWA \ TWI (Slave) Address register Bits
+ $01 constant TWAR_TWGCE \ TWI General Call Recognition Enable Bit
+\ TIMER_COUNTER_1
+&111 constant TIMSK1 \ Timer/Counter Interrupt Mask Register
+ $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
+ $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output CompareB Match Interrupt Enable
+ $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output CompareA Match Interrupt Enable
+ $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
+&54 constant TIFR1 \ Timer/Counter Interrupt Flag register
+ $20 constant TIFR1_ICF1 \ Input Capture Flag 1
+ $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
+ $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
+ $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
+&128 constant TCCR1A \ Timer/Counter1 Control Register A
+ $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
+ $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
+ $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
+&129 constant TCCR1B \ Timer/Counter1 Control Register B
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
+ $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
+&130 constant TCCR1C \ Timer/Counter1 Control Register C
+ $80 constant TCCR1C_FOC1A \
+ $40 constant TCCR1C_FOC1B \
+&132 constant TCNT1 \ Timer/Counter1 Bytes
+&136 constant OCR1A \ Timer/Counter1 Output Compare Register Bytes
+&138 constant OCR1B \ Timer/Counter1 Output Compare Register Bytes
+&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
+&67 constant GTCCR \ General Timer/Counter Control Register
+ $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
+ $01 constant GTCCR_PSRSYNC \ Prescaler Reset Timer/Counter1 and Timer/Counter0
+\ TIMER_COUNTER_2
+&112 constant TIMSK2 \ Timer/Counter Interrupt Mask register
+ $04 constant TIMSK2_OCIE2B \ Timer/Counter2 Output Compare Match B Interrupt Enable
+ $02 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare Match A Interrupt Enable
+ $01 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interrupt Enable
+&55 constant TIFR2 \ Timer/Counter Interrupt Flag Register
+ $04 constant TIFR2_OCF2B \ Output Compare Flag 2B
+ $02 constant TIFR2_OCF2A \ Output Compare Flag 2A
+ $01 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
+&176 constant TCCR2A \ Timer/Counter2 Control Register A
+ $C0 constant TCCR2A_COM2A \ Compare Output Mode bits
+ $30 constant TCCR2A_COM2B \ Compare Output Mode bits
+ $03 constant TCCR2A_WGM2 \ Waveform Genration Mode
+&177 constant TCCR2B \ Timer/Counter2 Control Register B
+ $80 constant TCCR2B_FOC2A \ Force Output Compare A
+ $40 constant TCCR2B_FOC2B \ Force Output Compare B
+ $08 constant TCCR2B_WGM22 \ Waveform Generation Mode
+ $07 constant TCCR2B_CS2 \ Clock Select bits
+&178 constant TCNT2 \ Timer/Counter2
+&180 constant OCR2B \ Timer/Counter2 Output Compare Register B
+&179 constant OCR2A \ Timer/Counter2 Output Compare Register A
+&182 constant ASSR \ Asynchronous Status Register
+ $40 constant ASSR_EXCLK \ Enable External Clock Input
+ $20 constant ASSR_AS2 \ Asynchronous Timer/Counter2
+ $10 constant ASSR_TCN2UB \ Timer/Counter2 Update Busy
+ $08 constant ASSR_OCR2AUB \ Output Compare Register2 Update Busy
+ $04 constant ASSR_OCR2BUB \ Output Compare Register 2 Update Busy
+ $02 constant ASSR_TCR2AUB \ Timer/Counter Control Register2 Update Busy
+ $01 constant ASSR_TCR2BUB \ Timer/Counter Control Register2 Update Busy
+\ AD_CONVERTER
+&124 constant ADMUX \ The ADC multiplexer Selection Register
+ $C0 constant ADMUX_REFS \ Reference Selection Bits
+ $20 constant ADMUX_ADLAR \ Left Adjust Result
+ $0F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
+&120 constant ADC \ ADC Data Register Bytes
+&122 constant ADCSRA \ The ADC Control and Status register A
+ $80 constant ADCSRA_ADEN \ ADC Enable
+ $40 constant ADCSRA_ADSC \ ADC Start Conversion
+ $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
+ $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
+ $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
+ $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
+&123 constant ADCSRB \ The ADC Control and Status register B
+ $40 constant ADCSRB_ACME \
+ $07 constant ADCSRB_ADTS \ ADC Auto Trigger Source bits
+&126 constant DIDR0 \ Digital Input Disable Register
+ $20 constant DIDR0_ADC5D \
+ $10 constant DIDR0_ADC4D \
+ $08 constant DIDR0_ADC3D \
+ $04 constant DIDR0_ADC2D \
+ $02 constant DIDR0_ADC1D \
+ $01 constant DIDR0_ADC0D \
+\ ANALOG_COMPARATOR
+&80 constant ACSR \ Analog Comparator Control And Status Register
+ $80 constant ACSR_ACD \ Analog Comparator Disable
+ $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
+ $20 constant ACSR_ACO \ Analog Compare Output
+ $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
+ $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
+ $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
+ $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
+&127 constant DIDR1 \ Digital Input Disable Register 1
+ $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
+ $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
+\ PORTB
+&37 constant PORTB \ Port B Data Register
+&36 constant DDRB \ Port B Data Direction Register
+&35 constant PINB \ Port B Input Pins
+\ PORTC
+&40 constant PORTC \ Port C Data Register
+&39 constant DDRC \ Port C Data Direction Register
+&38 constant PINC \ Port C Input Pins
+\ PORTD
+&43 constant PORTD \ Port D Data Register
+&42 constant DDRD \ Port D Data Direction Register
+&41 constant PIND \ Port D Input Pins
+\ TIMER_COUNTER_0
+&72 constant OCR0B \ Timer/Counter0 Output Compare Register
+&71 constant OCR0A \ Timer/Counter0 Output Compare Register
+&70 constant TCNT0 \ Timer/Counter0
+&69 constant TCCR0B \ Timer/Counter Control Register B
+ $80 constant TCCR0B_FOC0A \ Force Output Compare A
+ $40 constant TCCR0B_FOC0B \ Force Output Compare B
+ $08 constant TCCR0B_WGM02 \
+ $07 constant TCCR0B_CS0 \ Clock Select
+&68 constant TCCR0A \ Timer/Counter Control Register A
+ $C0 constant TCCR0A_COM0A \ Compare Output Mode, Phase Correct PWM Mode
+ $30 constant TCCR0A_COM0B \ Compare Output Mode, Fast PWm
+ $03 constant TCCR0A_WGM0 \ Waveform Generation Mode
+&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
+ $04 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare Match B Interrupt Enable
+ $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match A Interrupt Enable
+ $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
+&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
+ $04 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare Flag 0B
+ $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0A
+ $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
+\ EXTERNAL_INTERRUPT
+&105 constant EICRA \ External Interrupt Control Register
+ $0C constant EICRA_ISC1 \ External Interrupt Sense Control 1 Bits
+ $03 constant EICRA_ISC0 \ External Interrupt Sense Control 0 Bits
+&61 constant EIMSK \ External Interrupt Mask Register
+ $03 constant EIMSK_INT \ External Interrupt Request 1 Enable
+&60 constant EIFR \ External Interrupt Flag Register
+ $03 constant EIFR_INTF \ External Interrupt Flags
+&104 constant PCICR \ Pin Change Interrupt Control Register
+ $07 constant PCICR_PCIE \ Pin Change Interrupt Enables
+&109 constant PCMSK2 \ Pin Change Mask Register 2
+ $FF constant PCMSK2_PCINT \ Pin Change Enable Masks
+&108 constant PCMSK1 \ Pin Change Mask Register 1
+ $7F constant PCMSK1_PCINT \ Pin Change Enable Masks
+&107 constant PCMSK0 \ Pin Change Mask Register 0
+ $FF constant PCMSK0_PCINT \ Pin Change Enable Masks
+&59 constant PCIFR \ Pin Change Interrupt Flag Register
+ $07 constant PCIFR_PCIF \ Pin Change Interrupt Flags
+\ SPI
+&78 constant SPDR \ SPI Data Register
+&77 constant SPSR \ SPI Status Register
+ $80 constant SPSR_SPIF \ SPI Interrupt Flag
+ $40 constant SPSR_WCOL \ Write Collision Flag
+ $01 constant SPSR_SPI2X \ Double SPI Speed Bit
+&76 constant SPCR \ SPI Control Register
+ $80 constant SPCR_SPIE \ SPI Interrupt Enable
+ $40 constant SPCR_SPE \ SPI Enable
+ $20 constant SPCR_DORD \ Data Order
+ $10 constant SPCR_MSTR \ Master/Slave Select
+ $08 constant SPCR_CPOL \ Clock polarity
+ $04 constant SPCR_CPHA \ Clock Phase
+ $03 constant SPCR_SPR \ SPI Clock Rate Selects
+\ WATCHDOG
+&96 constant WDTCSR \ Watchdog Timer Control Register
+ $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Flag
+ $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Enable
+ $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
+ $10 constant WDTCSR_WDCE \ Watchdog Change Enable
+ $08 constant WDTCSR_WDE \ Watch Dog Enable
+\ EEPROM
+&65 constant EEAR \ EEPROM Address Register Bytes
+&64 constant EEDR \ EEPROM Data Register
+&63 constant EECR \ EEPROM Control Register
+ $30 constant EECR_EEPM \ EEPROM Programming Mode Bits
+ $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
+ $04 constant EECR_EEMPE \ EEPROM Master Write Enable
+ $02 constant EECR_EEPE \ EEPROM Write Enable
+ $01 constant EECR_EERE \ EEPROM Read Enable
+\ CPU
+&100 constant PRR \ Power Reduction Register
+ $80 constant PRR_PRTWI \ Power Reduction TWI
+ $40 constant PRR_PRTIM2 \ Power Reduction Timer/Counter2
+ $20 constant PRR_PRTIM0 \ Power Reduction Timer/Counter0
+ $08 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
+ $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
+ $02 constant PRR_PRUSART0 \ Power Reduction USART
+ $01 constant PRR_PRADC \ Power Reduction ADC
+&102 constant OSCCAL \ Oscillator Calibration Value
+&97 constant CLKPR \ Clock Prescale Register
+ $80 constant CLKPR_CLKPCE \ Clock Prescaler Change Enable
+ $0F constant CLKPR_CLKPS \ Clock Prescaler Select Bits
+&95 constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ $08 constant SREG_V \ Two's Complement Overflow Flag
+ $04 constant SREG_N \ Negative Flag
+ $02 constant SREG_Z \ Zero Flag
+ $01 constant SREG_C \ Carry Flag
+&93 constant SP \ Stack Pointer
+&87 constant SPMCSR \ Store Program Memory Control and Status Register
+ $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCSR_RWWSB \ Read-While-Write Section Busy
+ $10 constant SPMCSR_RWWSRE \ Read-While-Write section read enable
+ $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
+ $04 constant SPMCSR_PGWRT \ Page Write
+ $02 constant SPMCSR_PGERS \ Page Erase
+ $01 constant SPMCSR_SELFPRGEN \ Self Programming Enable
+&85 constant MCUCR \ MCU Control Register
+ $40 constant MCUCR_BODS \ BOD Sleep
+ $20 constant MCUCR_BODSE \ BOD Sleep Enable
+ $10 constant MCUCR_PUD \
+ $02 constant MCUCR_IVSEL \
+ $01 constant MCUCR_IVCE \
+&84 constant MCUSR \ MCU Status Register
+ $08 constant MCUSR_WDRF \ Watchdog Reset Flag
+ $04 constant MCUSR_BORF \ Brown-out Reset Flag
+ $02 constant MCUSR_EXTRF \ External Reset Flag
+ $01 constant MCUSR_PORF \ Power-on reset flag
+&83 constant SMCR \ Sleep Mode Control Register
+ $0E constant SMCR_SM \ Sleep Mode Select Bits
+ $01 constant SMCR_SE \ Sleep Enable
+&75 constant GPIOR2 \ General Purpose I/O Register 2
+&74 constant GPIOR1 \ General Purpose I/O Register 1
+&62 constant GPIOR0 \ General Purpose I/O Register 0
+
+\ Interrupts
+&1 constant INT0Addr \ External Interrupt Request 0
+&2 constant INT1Addr \ External Interrupt Request 1
+&3 constant PCINT0Addr \ Pin Change Interrupt Request 0
+&4 constant PCINT1Addr \ Pin Change Interrupt Request 0
+&5 constant PCINT2Addr \ Pin Change Interrupt Request 1
+&6 constant WDTAddr \ Watchdog Time-out Interrupt
+&7 constant TIMER2_COMPAAddr \ Timer/Counter2 Compare Match A
+&8 constant TIMER2_COMPBAddr \ Timer/Counter2 Compare Match A
+&9 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
+&10 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+&11 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
+&12 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
+&13 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+&14 constant TIMER0_COMPAAddr \ TimerCounter0 Compare Match A
+&15 constant TIMER0_COMPBAddr \ TimerCounter0 Compare Match B
+&16 constant TIMER0_OVFAddr \ Timer/Couner0 Overflow
+&17 constant SPI__STCAddr \ SPI Serial Transfer Complete
+&18 constant USART__RXAddr \ USART Rx Complete
+&19 constant USART__UDREAddr \ USART, Data Register Empty
+&20 constant USART__TXAddr \ USART Tx Complete
+&21 constant ADCAddr \ ADC Conversion Complete
+&22 constant EE_READYAddr \ EEPROM Ready
+&23 constant ANALOG_COMPAddr \ Analog Comparator
+&24 constant TWIAddr \ Two-wire Serial Interface
+&25 constant SPM_ReadyAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/atmega88pa/device.asm b/amforth-6.5/avr8/devices/atmega88pa/device.asm
new file mode 100644
index 0000000..5e2d8c3
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega88pa/device.asm
@@ -0,0 +1,107 @@
+; Partname: ATmega88PA
+; generated automatically, do not edit
+
+.nolist
+ .include "m88PAdef.inc"
+.list
+
+.equ ramstart = 256
+.equ CELLSIZE = 2
+.macro readflashcell
+ lsl zl
+ rol zh
+ lpm @0, Z+
+ lpm @1, Z+
+.endmacro
+.macro writeflashcell
+ lsl zl
+ rol zh
+.endmacro
+.set WANT_USART0 = 0
+.set WANT_TWI = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_TIMER_COUNTER_2 = 0
+.set WANT_AD_CONVERTER = 0
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_PORTB = 0
+.set WANT_PORTC = 0
+.set WANT_PORTD = 0
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_SPI = 0
+.set WANT_WATCHDOG = 0
+.set WANT_EEPROM = 0
+.set WANT_CPU = 0
+.equ intvecsize = 1 ; please verify; flash size: 8192 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.org 1
+ rcall isr ; External Interrupt Request 0
+.org 2
+ rcall isr ; External Interrupt Request 1
+.org 3
+ rcall isr ; Pin Change Interrupt Request 0
+.org 4
+ rcall isr ; Pin Change Interrupt Request 0
+.org 5
+ rcall isr ; Pin Change Interrupt Request 1
+.org 6
+ rcall isr ; Watchdog Time-out Interrupt
+.org 7
+ rcall isr ; Timer/Counter2 Compare Match A
+.org 8
+ rcall isr ; Timer/Counter2 Compare Match A
+.org 9
+ rcall isr ; Timer/Counter2 Overflow
+.org 10
+ rcall isr ; Timer/Counter1 Capture Event
+.org 11
+ rcall isr ; Timer/Counter1 Compare Match A
+.org 12
+ rcall isr ; Timer/Counter1 Compare Match B
+.org 13
+ rcall isr ; Timer/Counter1 Overflow
+.org 14
+ rcall isr ; TimerCounter0 Compare Match A
+.org 15
+ rcall isr ; TimerCounter0 Compare Match B
+.org 16
+ rcall isr ; Timer/Couner0 Overflow
+.org 17
+ rcall isr ; SPI Serial Transfer Complete
+.org 18
+ rcall isr ; USART Rx Complete
+.org 19
+ rcall isr ; USART, Data Register Empty
+.org 20
+ rcall isr ; USART Tx Complete
+.org 21
+ rcall isr ; ADC Conversion Complete
+.org 22
+ rcall isr ; EEPROM Ready
+.org 23
+ rcall isr ; Analog Comparator
+.org 24
+ rcall isr ; Two-wire Serial Interface
+.org 25
+ rcall isr ; Store Program Memory Read
+.equ INTVECTORS = 26
+.nooverlap
+
+; compatability layer (maybe empty)
+.equ SPMEN = SELFPRGEN
+
+; controller data area, environment query mcu-info
+mcu_info:
+mcu_ramsize:
+ .dw 1024
+mcu_eepromsize:
+ .dw 512
+mcu_maxdp:
+ .dw 6144
+mcu_numints:
+ .dw 26
+mcu_name:
+ .dw 10
+ .db "ATmega88PA"
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega88pa/device.inc b/amforth-6.5/avr8/devices/atmega88pa/device.inc
new file mode 100644
index 0000000..71a9bf3
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega88pa/device.inc
@@ -0,0 +1,996 @@
+; Partname: ATmega88PA
+; generated automatically, no not edit
+
+.if WANT_USART0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR0:
+ .dw $ff04
+ .db "UDR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR0
+XT_UDR0:
+ .dw PFA_DOVARIABLE
+PFA_UDR0:
+ .dw 198
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR0A:
+ .dw $ff06
+ .db "UCSR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0A
+XT_UCSR0A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0A:
+ .dw 192
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR0B:
+ .dw $ff06
+ .db "UCSR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0B
+XT_UCSR0B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0B:
+ .dw 193
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR0C:
+ .dw $ff06
+ .db "UCSR0C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0C
+XT_UCSR0C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0C:
+ .dw 194
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Bytes
+VE_UBRR0:
+ .dw $ff05
+ .db "UBRR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR0
+XT_UBRR0:
+ .dw PFA_DOVARIABLE
+PFA_UBRR0:
+ .dw 196
+
+.endif
+.if WANT_TWI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; TWI (Slave) Address Mask Register
+VE_TWAMR:
+ .dw $ff05
+ .db "TWAMR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWAMR
+XT_TWAMR:
+ .dw PFA_DOVARIABLE
+PFA_TWAMR:
+ .dw 189
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Bit Rate register
+VE_TWBR:
+ .dw $ff04
+ .db "TWBR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWBR
+XT_TWBR:
+ .dw PFA_DOVARIABLE
+PFA_TWBR:
+ .dw 184
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Control Register
+VE_TWCR:
+ .dw $ff04
+ .db "TWCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWCR
+XT_TWCR:
+ .dw PFA_DOVARIABLE
+PFA_TWCR:
+ .dw 188
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Status Register
+VE_TWSR:
+ .dw $ff04
+ .db "TWSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWSR
+XT_TWSR:
+ .dw PFA_DOVARIABLE
+PFA_TWSR:
+ .dw 185
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Data register
+VE_TWDR:
+ .dw $ff04
+ .db "TWDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWDR
+XT_TWDR:
+ .dw PFA_DOVARIABLE
+PFA_TWDR:
+ .dw 187
+; ( -- addr ) System Constant
+; R( -- )
+; TWI (Slave) Address register
+VE_TWAR:
+ .dw $ff04
+ .db "TWAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWAR
+XT_TWAR:
+ .dw PFA_DOVARIABLE
+PFA_TWAR:
+ .dw 186
+
+.endif
+.if WANT_TIMER_COUNTER_1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Mask Register
+VE_TIMSK1:
+ .dw $ff06
+ .db "TIMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK1
+XT_TIMSK1:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK1:
+ .dw 111
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Flag register
+VE_TIFR1:
+ .dw $ff05
+ .db "TIFR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR1
+XT_TIFR1:
+ .dw PFA_DOVARIABLE
+PFA_TIFR1:
+ .dw 54
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw 128
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw 129
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register C
+VE_TCCR1C:
+ .dw $ff06
+ .db "TCCR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1C
+XT_TCCR1C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1C:
+ .dw 130
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Bytes
+VE_TCNT1:
+ .dw $ff05
+ .db "TCNT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1
+XT_TCNT1:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1:
+ .dw 132
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register Bytes
+VE_OCR1A:
+ .dw $ff05
+ .db "OCR1A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1A
+XT_OCR1A:
+ .dw PFA_DOVARIABLE
+PFA_OCR1A:
+ .dw 136
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register Bytes
+VE_OCR1B:
+ .dw $ff05
+ .db "OCR1B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1B
+XT_OCR1B:
+ .dw PFA_DOVARIABLE
+PFA_OCR1B:
+ .dw 138
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Bytes
+VE_ICR1:
+ .dw $ff04
+ .db "ICR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1
+XT_ICR1:
+ .dw PFA_DOVARIABLE
+PFA_ICR1:
+ .dw 134
+; ( -- addr ) System Constant
+; R( -- )
+; General Timer/Counter Control Register
+VE_GTCCR:
+ .dw $ff05
+ .db "GTCCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GTCCR
+XT_GTCCR:
+ .dw PFA_DOVARIABLE
+PFA_GTCCR:
+ .dw 67
+
+.endif
+.if WANT_TIMER_COUNTER_2 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Mask register
+VE_TIMSK2:
+ .dw $ff06
+ .db "TIMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK2
+XT_TIMSK2:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK2:
+ .dw 112
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Flag Register
+VE_TIFR2:
+ .dw $ff05
+ .db "TIFR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR2
+XT_TIFR2:
+ .dw PFA_DOVARIABLE
+PFA_TIFR2:
+ .dw 55
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register A
+VE_TCCR2A:
+ .dw $ff06
+ .db "TCCR2A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2A
+XT_TCCR2A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2A:
+ .dw 176
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register B
+VE_TCCR2B:
+ .dw $ff06
+ .db "TCCR2B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2B
+XT_TCCR2B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2B:
+ .dw 177
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2
+VE_TCNT2:
+ .dw $ff05
+ .db "TCNT2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT2
+XT_TCNT2:
+ .dw PFA_DOVARIABLE
+PFA_TCNT2:
+ .dw 178
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register B
+VE_OCR2B:
+ .dw $ff05
+ .db "OCR2B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2B
+XT_OCR2B:
+ .dw PFA_DOVARIABLE
+PFA_OCR2B:
+ .dw 180
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register A
+VE_OCR2A:
+ .dw $ff05
+ .db "OCR2A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2A
+XT_OCR2A:
+ .dw PFA_DOVARIABLE
+PFA_OCR2A:
+ .dw 179
+; ( -- addr ) System Constant
+; R( -- )
+; Asynchronous Status Register
+VE_ASSR:
+ .dw $ff04
+ .db "ASSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ASSR
+XT_ASSR:
+ .dw PFA_DOVARIABLE
+PFA_ASSR:
+ .dw 182
+
+.endif
+.if WANT_AD_CONVERTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC multiplexer Selection Register
+VE_ADMUX:
+ .dw $ff05
+ .db "ADMUX",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADMUX
+XT_ADMUX:
+ .dw PFA_DOVARIABLE
+PFA_ADMUX:
+ .dw 124
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register Bytes
+VE_ADC:
+ .dw $ff03
+ .db "ADC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADC
+XT_ADC:
+ .dw PFA_DOVARIABLE
+PFA_ADC:
+ .dw 120
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register A
+VE_ADCSRA:
+ .dw $ff06
+ .db "ADCSRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRA
+XT_ADCSRA:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRA:
+ .dw 122
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register B
+VE_ADCSRB:
+ .dw $ff06
+ .db "ADCSRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRB
+XT_ADCSRB:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRB:
+ .dw 123
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register
+VE_DIDR0:
+ .dw $ff05
+ .db "DIDR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR0
+XT_DIDR0:
+ .dw PFA_DOVARIABLE
+PFA_DIDR0:
+ .dw 126
+
+.endif
+.if WANT_ANALOG_COMPARATOR == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Control And Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw 80
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 1
+VE_DIDR1:
+ .dw $ff05
+ .db "DIDR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR1
+XT_DIDR1:
+ .dw PFA_DOVARIABLE
+PFA_DIDR1:
+ .dw 127
+
+.endif
+.if WANT_PORTB == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw 37
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw 36
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw 35
+
+.endif
+.if WANT_PORTC == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Register
+VE_PORTC:
+ .dw $ff05
+ .db "PORTC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTC
+XT_PORTC:
+ .dw PFA_DOVARIABLE
+PFA_PORTC:
+ .dw 40
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Direction Register
+VE_DDRC:
+ .dw $ff04
+ .db "DDRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRC
+XT_DDRC:
+ .dw PFA_DOVARIABLE
+PFA_DDRC:
+ .dw 39
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Input Pins
+VE_PINC:
+ .dw $ff04
+ .db "PINC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINC
+XT_PINC:
+ .dw PFA_DOVARIABLE
+PFA_PINC:
+ .dw 38
+
+.endif
+.if WANT_PORTD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw 43
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw 42
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw 41
+
+.endif
+.if WANT_TIMER_COUNTER_0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0B:
+ .dw $ff05
+ .db "OCR0B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0B
+XT_OCR0B:
+ .dw PFA_DOVARIABLE
+PFA_OCR0B:
+ .dw 72
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0A:
+ .dw $ff05
+ .db "OCR0A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0A
+XT_OCR0A:
+ .dw PFA_DOVARIABLE
+PFA_OCR0A:
+ .dw 71
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw 70
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register B
+VE_TCCR0B:
+ .dw $ff06
+ .db "TCCR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0B
+XT_TCCR0B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0B:
+ .dw 69
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register A
+VE_TCCR0A:
+ .dw $ff06
+ .db "TCCR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0A
+XT_TCCR0A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0A:
+ .dw 68
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Mask Register
+VE_TIMSK0:
+ .dw $ff06
+ .db "TIMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK0
+XT_TIMSK0:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK0:
+ .dw 110
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Flag register
+VE_TIFR0:
+ .dw $ff05
+ .db "TIFR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR0
+XT_TIFR0:
+ .dw PFA_DOVARIABLE
+PFA_TIFR0:
+ .dw 53
+
+.endif
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register
+VE_EICRA:
+ .dw $ff05
+ .db "EICRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRA
+XT_EICRA:
+ .dw PFA_DOVARIABLE
+PFA_EICRA:
+ .dw 105
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Mask Register
+VE_EIMSK:
+ .dw $ff05
+ .db "EIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIMSK
+XT_EIMSK:
+ .dw PFA_DOVARIABLE
+PFA_EIMSK:
+ .dw 61
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Flag Register
+VE_EIFR:
+ .dw $ff04
+ .db "EIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIFR
+XT_EIFR:
+ .dw PFA_DOVARIABLE
+PFA_EIFR:
+ .dw 60
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Interrupt Control Register
+VE_PCICR:
+ .dw $ff05
+ .db "PCICR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCICR
+XT_PCICR:
+ .dw PFA_DOVARIABLE
+PFA_PCICR:
+ .dw 104
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 2
+VE_PCMSK2:
+ .dw $ff06
+ .db "PCMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK2
+XT_PCMSK2:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK2:
+ .dw 109
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 1
+VE_PCMSK1:
+ .dw $ff06
+ .db "PCMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK1
+XT_PCMSK1:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK1:
+ .dw 108
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 0
+VE_PCMSK0:
+ .dw $ff06
+ .db "PCMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK0
+XT_PCMSK0:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK0:
+ .dw 107
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Interrupt Flag Register
+VE_PCIFR:
+ .dw $ff05
+ .db "PCIFR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCIFR
+XT_PCIFR:
+ .dw PFA_DOVARIABLE
+PFA_PCIFR:
+ .dw 59
+
+.endif
+.if WANT_SPI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR:
+ .dw $ff04
+ .db "SPDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR
+XT_SPDR:
+ .dw PFA_DOVARIABLE
+PFA_SPDR:
+ .dw 78
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR:
+ .dw $ff04
+ .db "SPSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR
+XT_SPSR:
+ .dw PFA_DOVARIABLE
+PFA_SPSR:
+ .dw 77
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR:
+ .dw $ff04
+ .db "SPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR
+XT_SPCR:
+ .dw PFA_DOVARIABLE
+PFA_SPCR:
+ .dw 76
+
+.endif
+.if WANT_WATCHDOG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCSR:
+ .dw $ff06
+ .db "WDTCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCSR
+XT_WDTCSR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCSR:
+ .dw 96
+
+.endif
+.if WANT_EEPROM == 1
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Address Register Bytes
+VE_EEAR:
+ .dw $ff04
+ .db "EEAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEAR
+XT_EEAR:
+ .dw PFA_DOVARIABLE
+PFA_EEAR:
+ .dw 65
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw 64
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw 63
+
+.endif
+.if WANT_CPU == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register
+VE_PRR:
+ .dw $ff03
+ .db "PRR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR
+XT_PRR:
+ .dw PFA_DOVARIABLE
+PFA_PRR:
+ .dw 100
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Calibration Value
+VE_OSCCAL:
+ .dw $ff06
+ .db "OSCCAL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSCCAL
+XT_OSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_OSCCAL:
+ .dw 102
+; ( -- addr ) System Constant
+; R( -- )
+; Clock Prescale Register
+VE_CLKPR:
+ .dw $ff05
+ .db "CLKPR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKPR
+XT_CLKPR:
+ .dw PFA_DOVARIABLE
+PFA_CLKPR:
+ .dw 97
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw 95
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer
+VE_SP:
+ .dw $ff02
+ .db "SP"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SP
+XT_SP:
+ .dw PFA_DOVARIABLE
+PFA_SP:
+ .dw 93
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control and Status Register
+VE_SPMCSR:
+ .dw $ff06
+ .db "SPMCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCSR
+XT_SPMCSR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCSR:
+ .dw 87
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw 85
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Status Register
+VE_MCUSR:
+ .dw $ff05
+ .db "MCUSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUSR
+XT_MCUSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUSR:
+ .dw 84
+; ( -- addr ) System Constant
+; R( -- )
+; Sleep Mode Control Register
+VE_SMCR:
+ .dw $ff04
+ .db "SMCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SMCR
+XT_SMCR:
+ .dw PFA_DOVARIABLE
+PFA_SMCR:
+ .dw 83
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose I/O Register 2
+VE_GPIOR2:
+ .dw $ff06
+ .db "GPIOR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR2
+XT_GPIOR2:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR2:
+ .dw 75
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose I/O Register 1
+VE_GPIOR1:
+ .dw $ff06
+ .db "GPIOR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR1
+XT_GPIOR1:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR1:
+ .dw 74
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose I/O Register 0
+VE_GPIOR0:
+ .dw $ff06
+ .db "GPIOR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR0
+XT_GPIOR0:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR0:
+ .dw 62
+
+.endif
diff --git a/amforth-6.5/avr8/devices/atmega88pa/device.py b/amforth-6.5/avr8/devices/atmega88pa/device.py
new file mode 100644
index 0000000..d814349
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega88pa/device.py
@@ -0,0 +1,283 @@
+# Partname: ATmega88PA
+# generated automatically, do not edit
+MCUREGS = {
+ 'UDR0': '&198',
+ 'UCSR0A': '&192',
+ 'UCSR0A_RXC0': '$80',
+ 'UCSR0A_TXC0': '$40',
+ 'UCSR0A_UDRE0': '$20',
+ 'UCSR0A_FE0': '$10',
+ 'UCSR0A_DOR0': '$08',
+ 'UCSR0A_UPE0': '$04',
+ 'UCSR0A_U2X0': '$02',
+ 'UCSR0A_MPCM0': '$01',
+ 'UCSR0B': '&193',
+ 'UCSR0B_RXCIE0': '$80',
+ 'UCSR0B_TXCIE0': '$40',
+ 'UCSR0B_UDRIE0': '$20',
+ 'UCSR0B_RXEN0': '$10',
+ 'UCSR0B_TXEN0': '$08',
+ 'UCSR0B_UCSZ02': '$04',
+ 'UCSR0B_RXB80': '$02',
+ 'UCSR0B_TXB80': '$01',
+ 'UCSR0C': '&194',
+ 'UCSR0C_UMSEL0': '$C0',
+ 'UCSR0C_UPM0': '$30',
+ 'UCSR0C_USBS0': '$08',
+ 'UCSR0C_UCSZ0': '$06',
+ 'UCSR0C_UCPOL0': '$01',
+ 'UBRR0': '&196',
+ 'TWAMR': '&189',
+ 'TWAMR_TWAM': '$FE',
+ 'TWBR': '&184',
+ 'TWCR': '&188',
+ 'TWCR_TWINT': '$80',
+ 'TWCR_TWEA': '$40',
+ 'TWCR_TWSTA': '$20',
+ 'TWCR_TWSTO': '$10',
+ 'TWCR_TWWC': '$08',
+ 'TWCR_TWEN': '$04',
+ 'TWCR_TWIE': '$01',
+ 'TWSR': '&185',
+ 'TWSR_TWS': '$F8',
+ 'TWSR_TWPS': '$03',
+ 'TWDR': '&187',
+ 'TWAR': '&186',
+ 'TWAR_TWA': '$FE',
+ 'TWAR_TWGCE': '$01',
+ 'TIMSK1': '&111',
+ 'TIMSK1_ICIE1': '$20',
+ 'TIMSK1_OCIE1B': '$04',
+ 'TIMSK1_OCIE1A': '$02',
+ 'TIMSK1_TOIE1': '$01',
+ 'TIFR1': '&54',
+ 'TIFR1_ICF1': '$20',
+ 'TIFR1_OCF1B': '$04',
+ 'TIFR1_OCF1A': '$02',
+ 'TIFR1_TOV1': '$01',
+ 'TCCR1A': '&128',
+ 'TCCR1A_COM1A': '$C0',
+ 'TCCR1A_COM1B': '$30',
+ 'TCCR1A_WGM1': '$03',
+ 'TCCR1B': '&129',
+ 'TCCR1B_ICNC1': '$80',
+ 'TCCR1B_ICES1': '$40',
+ 'TCCR1B_WGM1': '$18',
+ 'TCCR1B_CS1': '$07',
+ 'TCCR1C': '&130',
+ 'TCCR1C_FOC1A': '$80',
+ 'TCCR1C_FOC1B': '$40',
+ 'TCNT1': '&132',
+ 'OCR1A': '&136',
+ 'OCR1B': '&138',
+ 'ICR1': '&134',
+ 'GTCCR': '&67',
+ 'GTCCR_TSM': '$80',
+ 'GTCCR_PSRSYNC': '$01',
+ 'TIMSK2': '&112',
+ 'TIMSK2_OCIE2B': '$04',
+ 'TIMSK2_OCIE2A': '$02',
+ 'TIMSK2_TOIE2': '$01',
+ 'TIFR2': '&55',
+ 'TIFR2_OCF2B': '$04',
+ 'TIFR2_OCF2A': '$02',
+ 'TIFR2_TOV2': '$01',
+ 'TCCR2A': '&176',
+ 'TCCR2A_COM2A': '$C0',
+ 'TCCR2A_COM2B': '$30',
+ 'TCCR2A_WGM2': '$03',
+ 'TCCR2B': '&177',
+ 'TCCR2B_FOC2A': '$80',
+ 'TCCR2B_FOC2B': '$40',
+ 'TCCR2B_WGM22': '$08',
+ 'TCCR2B_CS2': '$07',
+ 'TCNT2': '&178',
+ 'OCR2B': '&180',
+ 'OCR2A': '&179',
+ 'ASSR': '&182',
+ 'ASSR_EXCLK': '$40',
+ 'ASSR_AS2': '$20',
+ 'ASSR_TCN2UB': '$10',
+ 'ASSR_OCR2AUB': '$08',
+ 'ASSR_OCR2BUB': '$04',
+ 'ASSR_TCR2AUB': '$02',
+ 'ASSR_TCR2BUB': '$01',
+ 'ADMUX': '&124',
+ 'ADMUX_REFS': '$C0',
+ 'ADMUX_ADLAR': '$20',
+ 'ADMUX_MUX': '$0F',
+ 'ADC': '&120',
+ 'ADCSRA': '&122',
+ 'ADCSRA_ADEN': '$80',
+ 'ADCSRA_ADSC': '$40',
+ 'ADCSRA_ADATE': '$20',
+ 'ADCSRA_ADIF': '$10',
+ 'ADCSRA_ADIE': '$08',
+ 'ADCSRA_ADPS': '$07',
+ 'ADCSRB': '&123',
+ 'ADCSRB_ACME': '$40',
+ 'ADCSRB_ADTS': '$07',
+ 'DIDR0': '&126',
+ 'DIDR0_ADC5D': '$20',
+ 'DIDR0_ADC4D': '$10',
+ 'DIDR0_ADC3D': '$08',
+ 'DIDR0_ADC2D': '$04',
+ 'DIDR0_ADC1D': '$02',
+ 'DIDR0_ADC0D': '$01',
+ 'ACSR': '&80',
+ 'ACSR_ACD': '$80',
+ 'ACSR_ACBG': '$40',
+ 'ACSR_ACO': '$20',
+ 'ACSR_ACI': '$10',
+ 'ACSR_ACIE': '$08',
+ 'ACSR_ACIC': '$04',
+ 'ACSR_ACIS': '$03',
+ 'DIDR1': '&127',
+ 'DIDR1_AIN1D': '$02',
+ 'DIDR1_AIN0D': '$01',
+ 'PORTB': '&37',
+ 'DDRB': '&36',
+ 'PINB': '&35',
+ 'PORTC': '&40',
+ 'DDRC': '&39',
+ 'PINC': '&38',
+ 'PORTD': '&43',
+ 'DDRD': '&42',
+ 'PIND': '&41',
+ 'OCR0B': '&72',
+ 'OCR0A': '&71',
+ 'TCNT0': '&70',
+ 'TCCR0B': '&69',
+ 'TCCR0B_FOC0A': '$80',
+ 'TCCR0B_FOC0B': '$40',
+ 'TCCR0B_WGM02': '$08',
+ 'TCCR0B_CS0': '$07',
+ 'TCCR0A': '&68',
+ 'TCCR0A_COM0A': '$C0',
+ 'TCCR0A_COM0B': '$30',
+ 'TCCR0A_WGM0': '$03',
+ 'TIMSK0': '&110',
+ 'TIMSK0_OCIE0B': '$04',
+ 'TIMSK0_OCIE0A': '$02',
+ 'TIMSK0_TOIE0': '$01',
+ 'TIFR0': '&53',
+ 'TIFR0_OCF0B': '$04',
+ 'TIFR0_OCF0A': '$02',
+ 'TIFR0_TOV0': '$01',
+ 'EICRA': '&105',
+ 'EICRA_ISC1': '$0C',
+ 'EICRA_ISC0': '$03',
+ 'EIMSK': '&61',
+ 'EIMSK_INT': '$03',
+ 'EIFR': '&60',
+ 'EIFR_INTF': '$03',
+ 'PCICR': '&104',
+ 'PCICR_PCIE': '$07',
+ 'PCMSK2': '&109',
+ 'PCMSK2_PCINT': '$FF',
+ 'PCMSK1': '&108',
+ 'PCMSK1_PCINT': '$7F',
+ 'PCMSK0': '&107',
+ 'PCMSK0_PCINT': '$FF',
+ 'PCIFR': '&59',
+ 'PCIFR_PCIF': '$07',
+ 'SPDR': '&78',
+ 'SPSR': '&77',
+ 'SPSR_SPIF': '$80',
+ 'SPSR_WCOL': '$40',
+ 'SPSR_SPI2X': '$01',
+ 'SPCR': '&76',
+ 'SPCR_SPIE': '$80',
+ 'SPCR_SPE': '$40',
+ 'SPCR_DORD': '$20',
+ 'SPCR_MSTR': '$10',
+ 'SPCR_CPOL': '$08',
+ 'SPCR_CPHA': '$04',
+ 'SPCR_SPR': '$03',
+ 'WDTCSR': '&96',
+ 'WDTCSR_WDIF': '$80',
+ 'WDTCSR_WDIE': '$40',
+ 'WDTCSR_WDP': '$27',
+ 'WDTCSR_WDCE': '$10',
+ 'WDTCSR_WDE': '$08',
+ 'EEAR': '&65',
+ 'EEDR': '&64',
+ 'EECR': '&63',
+ 'EECR_EEPM': '$30',
+ 'EECR_EERIE': '$08',
+ 'EECR_EEMPE': '$04',
+ 'EECR_EEPE': '$02',
+ 'EECR_EERE': '$01',
+ 'PRR': '&100',
+ 'PRR_PRTWI': '$80',
+ 'PRR_PRTIM2': '$40',
+ 'PRR_PRTIM0': '$20',
+ 'PRR_PRTIM1': '$08',
+ 'PRR_PRSPI': '$04',
+ 'PRR_PRUSART0': '$02',
+ 'PRR_PRADC': '$01',
+ 'OSCCAL': '&102',
+ 'CLKPR': '&97',
+ 'CLKPR_CLKPCE': '$80',
+ 'CLKPR_CLKPS': '$0F',
+ 'SREG': '&95',
+ 'SREG_I': '$80',
+ 'SREG_T': '$40',
+ 'SREG_H': '$20',
+ 'SREG_S': '$10',
+ 'SREG_V': '$08',
+ 'SREG_N': '$04',
+ 'SREG_Z': '$02',
+ 'SREG_C': '$01',
+ 'SP': '&93',
+ 'SPMCSR': '&87',
+ 'SPMCSR_SPMIE': '$80',
+ 'SPMCSR_RWWSB': '$40',
+ 'SPMCSR_RWWSRE': '$10',
+ 'SPMCSR_BLBSET': '$08',
+ 'SPMCSR_PGWRT': '$04',
+ 'SPMCSR_PGERS': '$02',
+ 'SPMCSR_SELFPRGEN': '$01',
+ 'MCUCR': '&85',
+ 'MCUCR_BODS': '$40',
+ 'MCUCR_BODSE': '$20',
+ 'MCUCR_PUD': '$10',
+ 'MCUCR_IVSEL': '$02',
+ 'MCUCR_IVCE': '$01',
+ 'MCUSR': '&84',
+ 'MCUSR_WDRF': '$08',
+ 'MCUSR_BORF': '$04',
+ 'MCUSR_EXTRF': '$02',
+ 'MCUSR_PORF': '$01',
+ 'SMCR': '&83',
+ 'SMCR_SM': '$0E',
+ 'SMCR_SE': '$01',
+ 'GPIOR2': '&75',
+ 'GPIOR1': '&74',
+ 'GPIOR0': '&62',
+ 'INT0Addr': '1',
+ 'INT1Addr': '2',
+ 'PCINT0Addr': '3',
+ 'PCINT1Addr': '4',
+ 'PCINT2Addr': '5',
+ 'WDTAddr': '6',
+ 'TIMER2_COMPAAddr': '7',
+ 'TIMER2_COMPBAddr': '8',
+ 'TIMER2_OVFAddr': '9',
+ 'TIMER1_CAPTAddr': '10',
+ 'TIMER1_COMPAAddr': '11',
+ 'TIMER1_COMPBAddr': '12',
+ 'TIMER1_OVFAddr': '13',
+ 'TIMER0_COMPAAddr': '14',
+ 'TIMER0_COMPBAddr': '15',
+ 'TIMER0_OVFAddr': '16',
+ 'SPI__STCAddr': '17',
+ 'USART__RXAddr': '18',
+ 'USART__UDREAddr': '19',
+ 'USART__TXAddr': '20',
+ 'ADCAddr': '21',
+ 'EE_READYAddr': '22',
+ 'ANALOG_COMPAddr': '23',
+ 'TWIAddr': '24',
+ 'SPM_ReadyAddr': '25'
+} \ No newline at end of file
diff --git a/amforth-6.5/avr8/devices/atmega88pa/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega88pa/words/no-jtag.asm
new file mode 100644
index 0000000..352a4bb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega88pa/words/no-jtag.asm
@@ -0,0 +1,14 @@
+; ( -- )
+; ( -- )
+; MCU
+; disable jtag at runtime
+VE_NOJTAG:
+ .dw $FF05
+ .db "-jtag",0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOJTAG
+XT_NOJTAG:
+ .dw PFA_NOJTAG
+PFA_NOJTAG:
+
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega88pa/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega88pa/words/no-wdt.asm
new file mode 100644
index 0000000..ff6ddd1
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega88pa/words/no-wdt.asm
@@ -0,0 +1,34 @@
+; ( -- )
+; MCU
+; disable watch dog timer at runtime
+VE_NOWDT:
+ .dw $ff04
+ .db "-wdt"
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOWDT
+XT_NOWDT:
+ .dw PFA_NOWDT
+PFA_NOWDT:
+
+ in temp1,SREG
+ push temp1
+ ; Turn always off global interrupt.
+ cli
+ ; Reset Watchdog Timer
+ wdr
+ ; Clear WDRF in MCUSR
+ in temp1, MCUSR
+ andi temp1, (0xff & (0<<WDRF))
+ out MCUSR, temp1
+ ; Write logical one to WDCE and WDE
+ ; Keep old prescaler setting to prevent unintentional time-out
+ in_ temp1, WDTCSR
+ ori temp1, (1<<WDCE) | (1<<WDE)
+ out_ WDTCSR, temp1
+ ; Turn off WDT
+ ldi temp1, (0<<WDE)
+ out_ WDTCSR, temp1
+ ; restore status register
+ pop temp1
+ out SREG,temp1
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega88pa/words/sleep.asm b/amforth-6.5/avr8/devices/atmega88pa/words/sleep.asm
new file mode 100644
index 0000000..256249c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega88pa/words/sleep.asm
@@ -0,0 +1,19 @@
+; ( mode -- )
+; MCU
+; put the controller into the specified sleep mode
+VE_SLEEP:
+ .dw $ff05
+ .db "sleep", 0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_SLEEP
+XT_SLEEP:
+ .dw PFA_SLEEP
+PFA_SLEEP:
+ andi tosl, 7 ; leave only legal mode bits
+ lsl tosl ; move to correct location (bits 3-1)
+ ori tosl, 1 ; set the SE bit
+ out_ SMCR, tosl ; set the sleep config
+ sleep ; nighty-night
+ out_ SMCR, zerol ; 0 protects against accidental sleeps
+ loadtos ; pop argument from stack
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega8a/atmega8a.frt b/amforth-6.5/avr8/devices/atmega8a/atmega8a.frt
new file mode 100644
index 0000000..842ccd3
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega8a/atmega8a.frt
@@ -0,0 +1,207 @@
+\ Partname: ATmega8A
+\ generated automatically
+
+\ ANALOG_COMPARATOR
+&80 constant SFIOR \ Special Function IO Register
+ $08 constant SFIOR_ACME \ Analog Comparator Multiplexer Enable
+&40 constant ACSR \ Analog Comparator Control And Status Register
+ $80 constant ACSR_ACD \ Analog Comparator Disable
+ $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
+ $20 constant ACSR_ACO \ Analog Compare Output
+ $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
+ $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
+ $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
+ $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
+\ SPI
+&47 constant SPDR \ SPI Data Register
+&46 constant SPSR \ SPI Status Register
+ $80 constant SPSR_SPIF \ SPI Interrupt Flag
+ $40 constant SPSR_WCOL \ Write Collision Flag
+ $01 constant SPSR_SPI2X \ Double SPI Speed Bit
+&45 constant SPCR \ SPI Control Register
+ $80 constant SPCR_SPIE \ SPI Interrupt Enable
+ $40 constant SPCR_SPE \ SPI Enable
+ $20 constant SPCR_DORD \ Data Order
+ $10 constant SPCR_MSTR \ Master/Slave Select
+ $08 constant SPCR_CPOL \ Clock polarity
+ $04 constant SPCR_CPHA \ Clock Phase
+ $03 constant SPCR_SPR \ SPI Clock Rate Selects
+\ EXTERNAL_INTERRUPT
+&91 constant GICR \ General Interrupt Control Register
+ $C0 constant GICR_INT \ External Interrupt Request 1 Enable
+ $02 constant GICR_IVSEL \ Interrupt Vector Select
+ $01 constant GICR_IVCE \ Interrupt Vector Change Enable
+&90 constant GIFR \ General Interrupt Flag Register
+ $C0 constant GIFR_INTF \ External Interrupt Flags
+&85 constant MCUCR \ MCU Control Register
+ $0C constant MCUCR_ISC1 \ Interrupt Sense Control 1 Bits
+ $03 constant MCUCR_ISC0 \ Interrupt Sense Control 0 Bits
+\ TIMER_COUNTER_0
+&89 constant TIMSK \ Timer/Counter Interrupt Mask Register
+ $01 constant TIMSK_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
+&88 constant TIFR \ Timer/Counter Interrupt Flag register
+ $01 constant TIFR_TOV0 \ Timer/Counter0 Overflow Flag
+&83 constant TCCR0 \ Timer/Counter0 Control Register
+ $04 constant TCCR0_CS02 \ Clock Select0 bit 2
+ $02 constant TCCR0_CS01 \ Clock Select0 bit 1
+ $01 constant TCCR0_CS00 \ Clock Select0 bit 0
+&82 constant TCNT0 \ Timer Counter 0
+\ TIMER_COUNTER_1
+&79 constant TCCR1A \ Timer/Counter1 Control Register A
+ $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
+ $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
+ $08 constant TCCR1A_FOC1A \ Force Output Compare 1A
+ $04 constant TCCR1A_FOC1B \ Force Output Compare 1B
+ $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
+&78 constant TCCR1B \ Timer/Counter1 Control Register B
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
+ $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
+&76 constant TCNT1 \ Timer/Counter1 Bytes
+&74 constant OCR1A \ Timer/Counter1 Output Compare Register Bytes
+&72 constant OCR1B \ Timer/Counter1 Output Compare Register Bytes
+&70 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
+\ TIMER_COUNTER_2
+&69 constant TCCR2 \ Timer/Counter2 Control Register
+ $80 constant TCCR2_FOC2 \ Force Output Compare
+ $40 constant TCCR2_WGM20 \ Waveform Genration Mode
+ $30 constant TCCR2_COM2 \ Compare Output Mode bits
+ $08 constant TCCR2_WGM21 \ Waveform Generation Mode
+ $07 constant TCCR2_CS2 \ Clock Select bits
+&68 constant TCNT2 \ Timer/Counter2
+&67 constant OCR2 \ Timer/Counter2 Output Compare Register
+&66 constant ASSR \ Asynchronous Status Register
+ $08 constant ASSR_AS2 \ Asynchronous Timer/counter2
+ $04 constant ASSR_TCN2UB \ Timer/Counter2 Update Busy
+ $02 constant ASSR_OCR2UB \ Output Compare Register2 Update Busy
+ $01 constant ASSR_TCR2UB \ Timer/counter Control Register2 Update Busy
+\ USART
+&44 constant UDR \ USART I/O Data Register
+&43 constant UCSRA \ USART Control and Status Register A
+ $80 constant UCSRA_RXC \ USART Receive Complete
+ $40 constant UCSRA_TXC \ USART Transmitt Complete
+ $20 constant UCSRA_UDRE \ USART Data Register Empty
+ $10 constant UCSRA_FE \ Framing Error
+ $08 constant UCSRA_DOR \ Data overRun
+ $04 constant UCSRA_UPE \ Parity Error
+ $02 constant UCSRA_U2X \ Double the USART transmission speed
+ $01 constant UCSRA_MPCM \ Multi-processor Communication Mode
+&42 constant UCSRB \ USART Control and Status Register B
+ $80 constant UCSRB_RXCIE \ RX Complete Interrupt Enable
+ $40 constant UCSRB_TXCIE \ TX Complete Interrupt Enable
+ $20 constant UCSRB_UDRIE \ USART Data register Empty Interrupt Enable
+ $10 constant UCSRB_RXEN \ Receiver Enable
+ $08 constant UCSRB_TXEN \ Transmitter Enable
+ $04 constant UCSRB_UCSZ2 \ Character Size
+ $02 constant UCSRB_RXB8 \ Receive Data Bit 8
+ $01 constant UCSRB_TXB8 \ Transmit Data Bit 8
+&64 constant UCSRC \ USART Control and Status Register C
+ $80 constant UCSRC_URSEL \ Register Select
+ $40 constant UCSRC_UMSEL \ USART Mode Select
+ $30 constant UCSRC_UPM \ Parity Mode Bits
+ $08 constant UCSRC_USBS \ Stop Bit Select
+ $06 constant UCSRC_UCSZ \ Character Size
+ $01 constant UCSRC_UCPOL \ Clock Polarity
+&64 constant UBRRH \ USART Baud Rate Register Hight Byte
+&41 constant UBRRL \ USART Baud Rate Register Low Byte
+\ TWI
+&32 constant TWBR \ TWI Bit Rate register
+&86 constant TWCR \ TWI Control Register
+ $80 constant TWCR_TWINT \ TWI Interrupt Flag
+ $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
+ $20 constant TWCR_TWSTA \ TWI Start Condition Bit
+ $10 constant TWCR_TWSTO \ TWI Stop Condition Bit
+ $08 constant TWCR_TWWC \ TWI Write Collition Flag
+ $04 constant TWCR_TWEN \ TWI Enable Bit
+ $01 constant TWCR_TWIE \ TWI Interrupt Enable
+&33 constant TWSR \ TWI Status Register
+ $F8 constant TWSR_TWS \ TWI Status
+ $03 constant TWSR_TWPS \ TWI Prescaler
+&35 constant TWDR \ TWI Data register
+&34 constant TWAR \ TWI (Slave) Address register
+ $FE constant TWAR_TWA \ TWI (Slave) Address register Bits
+ $01 constant TWAR_TWGCE \ TWI General Call Recognition Enable Bit
+\ WATCHDOG
+&65 constant WDTCR \ Watchdog Timer Control Register
+ $10 constant WDTCR_WDCE \ Watchdog Change Enable
+ $08 constant WDTCR_WDE \ Watch Dog Enable
+ $07 constant WDTCR_WDP \ Watch Dog Timer Prescaler bits
+\ PORTB
+&56 constant PORTB \ Port B Data Register
+&55 constant DDRB \ Port B Data Direction Register
+&54 constant PINB \ Port B Input Pins
+\ PORTC
+&53 constant PORTC \ Port C Data Register
+&52 constant DDRC \ Port C Data Direction Register
+&51 constant PINC \ Port C Input Pins
+\ PORTD
+&50 constant PORTD \ Port D Data Register
+&49 constant DDRD \ Port D Data Direction Register
+&48 constant PIND \ Port D Input Pins
+\ EEPROM
+&62 constant EEAR \ EEPROM Address Register Bytes
+&61 constant EEDR \ EEPROM Data Register
+&60 constant EECR \ EEPROM Control Register
+ $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
+ $04 constant EECR_EEMWE \ EEPROM Master Write Enable
+ $02 constant EECR_EEWE \ EEPROM Write Enable
+ $01 constant EECR_EERE \ EEPROM Read Enable
+\ CPU
+&95 constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ $08 constant SREG_V \ Two's Complement Overflow Flag
+ $04 constant SREG_N \ Negative Flag
+ $02 constant SREG_Z \ Zero Flag
+ $01 constant SREG_C \ Carry Flag
+&93 constant SP \ Stack Pointer
+&84 constant MCUCSR \ MCU Control And Status Register
+ $08 constant MCUCSR_WDRF \ Watchdog Reset Flag
+ $04 constant MCUCSR_BORF \ Brown-out Reset Flag
+ $02 constant MCUCSR_EXTRF \ External Reset Flag
+ $01 constant MCUCSR_PORF \ Power-on reset flag
+&81 constant OSCCAL \ Oscillator Calibration Value
+&87 constant SPMCR \ Store Program Memory Control Register
+ $80 constant SPMCR_SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCR_RWWSB \ Read-While-Write Section Busy
+ $10 constant SPMCR_RWWSRE \ Read-While-Write Section Read Enable
+ $08 constant SPMCR_BLBSET \ Boot Lock Bit Set
+ $04 constant SPMCR_PGWRT \ Page Write
+ $02 constant SPMCR_PGERS \ Page Erase
+ $01 constant SPMCR_SPMEN \ Store Program Memory Enable
+\ AD_CONVERTER
+&39 constant ADMUX \ The ADC multiplexer Selection Register
+ $C0 constant ADMUX_REFS \ Reference Selection Bits
+ $20 constant ADMUX_ADLAR \ Left Adjust Result
+ $0F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
+&38 constant ADCSRA \ The ADC Control and Status register
+ $80 constant ADCSRA_ADEN \ ADC Enable
+ $40 constant ADCSRA_ADSC \ ADC Start Conversion
+ $20 constant ADCSRA_ADFR \ ADC Free Running Select
+ $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
+ $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
+ $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
+&36 constant ADC \ ADC Data Register Bytes
+
+\ Interrupts
+&1 constant INT0Addr \ External Interrupt Request 0
+&2 constant INT1Addr \ External Interrupt Request 1
+&3 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
+&4 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
+&5 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+&6 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
+&7 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
+&8 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+&9 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
+&10 constant SPI__STCAddr \ Serial Transfer Complete
+&11 constant USART__RXCAddr \ USART, Rx Complete
+&12 constant USART__UDREAddr \ USART Data Register Empty
+&13 constant USART__TXCAddr \ USART, Tx Complete
+&14 constant ADCAddr \ ADC Conversion Complete
+&15 constant EE_RDYAddr \ EEPROM Ready
+&16 constant ANA_COMPAddr \ Analog Comparator
+&17 constant TWIAddr \ 2-wire Serial Interface
+&18 constant SPM_RDYAddr \ Store Program Memory Ready
diff --git a/amforth-6.5/avr8/devices/atmega8a/device.asm b/amforth-6.5/avr8/devices/atmega8a/device.asm
new file mode 100644
index 0000000..067403d
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega8a/device.asm
@@ -0,0 +1,95 @@
+; Partname: ATmega8A
+; generated automatically, do not edit
+
+.nolist
+ .include "m8Adef.inc"
+.list
+
+.equ ramstart = 96
+.equ CELLSIZE = 2
+.macro readflashcell
+ lsl zl
+ rol zh
+ lpm @0, Z+
+ lpm @1, Z+
+.endmacro
+.macro writeflashcell
+ lsl zl
+ rol zh
+.endmacro
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_SPI = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_TIMER_COUNTER_2 = 0
+.set WANT_USART = 0
+.set WANT_TWI = 0
+.set WANT_WATCHDOG = 0
+.set WANT_PORTB = 0
+.set WANT_PORTC = 0
+.set WANT_PORTD = 0
+.set WANT_EEPROM = 0
+.set WANT_CPU = 0
+.set WANT_AD_CONVERTER = 0
+.equ intvecsize = 1 ; please verify; flash size: 8192 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.org 1
+ rcall isr ; External Interrupt Request 0
+.org 2
+ rcall isr ; External Interrupt Request 1
+.org 3
+ rcall isr ; Timer/Counter2 Compare Match
+.org 4
+ rcall isr ; Timer/Counter2 Overflow
+.org 5
+ rcall isr ; Timer/Counter1 Capture Event
+.org 6
+ rcall isr ; Timer/Counter1 Compare Match A
+.org 7
+ rcall isr ; Timer/Counter1 Compare Match B
+.org 8
+ rcall isr ; Timer/Counter1 Overflow
+.org 9
+ rcall isr ; Timer/Counter0 Overflow
+.org 10
+ rcall isr ; Serial Transfer Complete
+.org 11
+ rcall isr ; USART, Rx Complete
+.org 12
+ rcall isr ; USART Data Register Empty
+.org 13
+ rcall isr ; USART, Tx Complete
+.org 14
+ rcall isr ; ADC Conversion Complete
+.org 15
+ rcall isr ; EEPROM Ready
+.org 16
+ rcall isr ; Analog Comparator
+.org 17
+ rcall isr ; 2-wire Serial Interface
+.org 18
+ rcall isr ; Store Program Memory Ready
+.equ INTVECTORS = 19
+.nooverlap
+
+; compatability layer (maybe empty)
+.equ SPMCSR = SPMCR
+.equ EEPE = EEWE
+.equ EEMPE = EEMWE
+
+; controller data area, environment query mcu-info
+mcu_info:
+mcu_ramsize:
+ .dw 1024
+mcu_eepromsize:
+ .dw 512
+mcu_maxdp:
+ .dw 6144
+mcu_numints:
+ .dw 19
+mcu_name:
+ .dw 8
+ .db "ATmega8A"
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega8a/device.inc b/amforth-6.5/avr8/devices/atmega8a/device.inc
new file mode 100644
index 0000000..ff1f890
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega8a/device.inc
@@ -0,0 +1,696 @@
+; Partname: ATmega8A
+; generated automatically, no not edit
+
+.if WANT_ANALOG_COMPARATOR == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Special Function IO Register
+VE_SFIOR:
+ .dw $ff05
+ .db "SFIOR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SFIOR
+XT_SFIOR:
+ .dw PFA_DOVARIABLE
+PFA_SFIOR:
+ .dw 80
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Control And Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw 40
+
+.endif
+.if WANT_SPI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR:
+ .dw $ff04
+ .db "SPDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR
+XT_SPDR:
+ .dw PFA_DOVARIABLE
+PFA_SPDR:
+ .dw 47
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR:
+ .dw $ff04
+ .db "SPSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR
+XT_SPSR:
+ .dw PFA_DOVARIABLE
+PFA_SPSR:
+ .dw 46
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR:
+ .dw $ff04
+ .db "SPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR
+XT_SPCR:
+ .dw PFA_DOVARIABLE
+PFA_SPCR:
+ .dw 45
+
+.endif
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ( -- addr ) System Constant
+; R( -- )
+; General Interrupt Control Register
+VE_GICR:
+ .dw $ff04
+ .db "GICR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GICR
+XT_GICR:
+ .dw PFA_DOVARIABLE
+PFA_GICR:
+ .dw 91
+; ( -- addr ) System Constant
+; R( -- )
+; General Interrupt Flag Register
+VE_GIFR:
+ .dw $ff04
+ .db "GIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GIFR
+XT_GIFR:
+ .dw PFA_DOVARIABLE
+PFA_GIFR:
+ .dw 90
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw 85
+
+.endif
+.if WANT_TIMER_COUNTER_0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Mask Register
+VE_TIMSK:
+ .dw $ff05
+ .db "TIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK
+XT_TIMSK:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK:
+ .dw 89
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Flag register
+VE_TIFR:
+ .dw $ff04
+ .db "TIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR
+XT_TIFR:
+ .dw PFA_DOVARIABLE
+PFA_TIFR:
+ .dw 88
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Control Register
+VE_TCCR0:
+ .dw $ff05
+ .db "TCCR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0
+XT_TCCR0:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0:
+ .dw 83
+; ( -- addr ) System Constant
+; R( -- )
+; Timer Counter 0
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw 82
+
+.endif
+.if WANT_TIMER_COUNTER_1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw 79
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw 78
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Bytes
+VE_TCNT1:
+ .dw $ff05
+ .db "TCNT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1
+XT_TCNT1:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1:
+ .dw 76
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register Bytes
+VE_OCR1A:
+ .dw $ff05
+ .db "OCR1A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1A
+XT_OCR1A:
+ .dw PFA_DOVARIABLE
+PFA_OCR1A:
+ .dw 74
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register Bytes
+VE_OCR1B:
+ .dw $ff05
+ .db "OCR1B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1B
+XT_OCR1B:
+ .dw PFA_DOVARIABLE
+PFA_OCR1B:
+ .dw 72
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Bytes
+VE_ICR1:
+ .dw $ff04
+ .db "ICR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1
+XT_ICR1:
+ .dw PFA_DOVARIABLE
+PFA_ICR1:
+ .dw 70
+
+.endif
+.if WANT_TIMER_COUNTER_2 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register
+VE_TCCR2:
+ .dw $ff05
+ .db "TCCR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2
+XT_TCCR2:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2:
+ .dw 69
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2
+VE_TCNT2:
+ .dw $ff05
+ .db "TCNT2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT2
+XT_TCNT2:
+ .dw PFA_DOVARIABLE
+PFA_TCNT2:
+ .dw 68
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register
+VE_OCR2:
+ .dw $ff04
+ .db "OCR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2
+XT_OCR2:
+ .dw PFA_DOVARIABLE
+PFA_OCR2:
+ .dw 67
+; ( -- addr ) System Constant
+; R( -- )
+; Asynchronous Status Register
+VE_ASSR:
+ .dw $ff04
+ .db "ASSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ASSR
+XT_ASSR:
+ .dw PFA_DOVARIABLE
+PFA_ASSR:
+ .dw 66
+
+.endif
+.if WANT_USART == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR:
+ .dw $ff03
+ .db "UDR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR
+XT_UDR:
+ .dw PFA_DOVARIABLE
+PFA_UDR:
+ .dw 44
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSRA:
+ .dw $ff05
+ .db "UCSRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSRA
+XT_UCSRA:
+ .dw PFA_DOVARIABLE
+PFA_UCSRA:
+ .dw 43
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSRB:
+ .dw $ff05
+ .db "UCSRB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSRB
+XT_UCSRB:
+ .dw PFA_DOVARIABLE
+PFA_UCSRB:
+ .dw 42
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSRC:
+ .dw $ff05
+ .db "UCSRC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSRC
+XT_UCSRC:
+ .dw PFA_DOVARIABLE
+PFA_UCSRC:
+ .dw 64
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Hight Byte
+VE_UBRRH:
+ .dw $ff05
+ .db "UBRRH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRRH
+XT_UBRRH:
+ .dw PFA_DOVARIABLE
+PFA_UBRRH:
+ .dw 64
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Low Byte
+VE_UBRRL:
+ .dw $ff05
+ .db "UBRRL",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRRL
+XT_UBRRL:
+ .dw PFA_DOVARIABLE
+PFA_UBRRL:
+ .dw 41
+
+.endif
+.if WANT_TWI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Bit Rate register
+VE_TWBR:
+ .dw $ff04
+ .db "TWBR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWBR
+XT_TWBR:
+ .dw PFA_DOVARIABLE
+PFA_TWBR:
+ .dw 32
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Control Register
+VE_TWCR:
+ .dw $ff04
+ .db "TWCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWCR
+XT_TWCR:
+ .dw PFA_DOVARIABLE
+PFA_TWCR:
+ .dw 86
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Status Register
+VE_TWSR:
+ .dw $ff04
+ .db "TWSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWSR
+XT_TWSR:
+ .dw PFA_DOVARIABLE
+PFA_TWSR:
+ .dw 33
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Data register
+VE_TWDR:
+ .dw $ff04
+ .db "TWDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWDR
+XT_TWDR:
+ .dw PFA_DOVARIABLE
+PFA_TWDR:
+ .dw 35
+; ( -- addr ) System Constant
+; R( -- )
+; TWI (Slave) Address register
+VE_TWAR:
+ .dw $ff04
+ .db "TWAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWAR
+XT_TWAR:
+ .dw PFA_DOVARIABLE
+PFA_TWAR:
+ .dw 34
+
+.endif
+.if WANT_WATCHDOG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCR:
+ .dw $ff05
+ .db "WDTCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCR
+XT_WDTCR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCR:
+ .dw 65
+
+.endif
+.if WANT_PORTB == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw 56
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw 55
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw 54
+
+.endif
+.if WANT_PORTC == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Register
+VE_PORTC:
+ .dw $ff05
+ .db "PORTC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTC
+XT_PORTC:
+ .dw PFA_DOVARIABLE
+PFA_PORTC:
+ .dw 53
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Direction Register
+VE_DDRC:
+ .dw $ff04
+ .db "DDRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRC
+XT_DDRC:
+ .dw PFA_DOVARIABLE
+PFA_DDRC:
+ .dw 52
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Input Pins
+VE_PINC:
+ .dw $ff04
+ .db "PINC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINC
+XT_PINC:
+ .dw PFA_DOVARIABLE
+PFA_PINC:
+ .dw 51
+
+.endif
+.if WANT_PORTD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw 50
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw 49
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw 48
+
+.endif
+.if WANT_EEPROM == 1
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Address Register Bytes
+VE_EEAR:
+ .dw $ff04
+ .db "EEAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEAR
+XT_EEAR:
+ .dw PFA_DOVARIABLE
+PFA_EEAR:
+ .dw 62
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw 61
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw 60
+
+.endif
+.if WANT_CPU == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw 95
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer
+VE_SP:
+ .dw $ff02
+ .db "SP"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SP
+XT_SP:
+ .dw PFA_DOVARIABLE
+PFA_SP:
+ .dw 93
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control And Status Register
+VE_MCUCSR:
+ .dw $ff06
+ .db "MCUCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCSR
+XT_MCUCSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCSR:
+ .dw 84
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Calibration Value
+VE_OSCCAL:
+ .dw $ff06
+ .db "OSCCAL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSCCAL
+XT_OSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_OSCCAL:
+ .dw 81
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control Register
+VE_SPMCR:
+ .dw $ff05
+ .db "SPMCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCR
+XT_SPMCR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCR:
+ .dw 87
+
+.endif
+.if WANT_AD_CONVERTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC multiplexer Selection Register
+VE_ADMUX:
+ .dw $ff05
+ .db "ADMUX",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADMUX
+XT_ADMUX:
+ .dw PFA_DOVARIABLE
+PFA_ADMUX:
+ .dw 39
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register
+VE_ADCSRA:
+ .dw $ff06
+ .db "ADCSRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRA
+XT_ADCSRA:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRA:
+ .dw 38
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register Bytes
+VE_ADC:
+ .dw $ff03
+ .db "ADC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADC
+XT_ADC:
+ .dw PFA_DOVARIABLE
+PFA_ADC:
+ .dw 36
+
+.endif
diff --git a/amforth-6.5/avr8/devices/atmega8a/device.py b/amforth-6.5/avr8/devices/atmega8a/device.py
new file mode 100644
index 0000000..bcc03ff
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega8a/device.py
@@ -0,0 +1,191 @@
+# Partname: ATmega8A
+# generated automatically, do not edit
+MCUREGS = {
+ 'SFIOR': '&80',
+ 'SFIOR_ACME': '$08',
+ 'ACSR': '&40',
+ 'ACSR_ACD': '$80',
+ 'ACSR_ACBG': '$40',
+ 'ACSR_ACO': '$20',
+ 'ACSR_ACI': '$10',
+ 'ACSR_ACIE': '$08',
+ 'ACSR_ACIC': '$04',
+ 'ACSR_ACIS': '$03',
+ 'SPDR': '&47',
+ 'SPSR': '&46',
+ 'SPSR_SPIF': '$80',
+ 'SPSR_WCOL': '$40',
+ 'SPSR_SPI2X': '$01',
+ 'SPCR': '&45',
+ 'SPCR_SPIE': '$80',
+ 'SPCR_SPE': '$40',
+ 'SPCR_DORD': '$20',
+ 'SPCR_MSTR': '$10',
+ 'SPCR_CPOL': '$08',
+ 'SPCR_CPHA': '$04',
+ 'SPCR_SPR': '$03',
+ 'GICR': '&91',
+ 'GICR_INT': '$C0',
+ 'GICR_IVSEL': '$02',
+ 'GICR_IVCE': '$01',
+ 'GIFR': '&90',
+ 'GIFR_INTF': '$C0',
+ 'MCUCR': '&85',
+ 'MCUCR_ISC1': '$0C',
+ 'MCUCR_ISC0': '$03',
+ 'TIMSK': '&89',
+ 'TIMSK_TOIE0': '$01',
+ 'TIFR': '&88',
+ 'TIFR_TOV0': '$01',
+ 'TCCR0': '&83',
+ 'TCCR0_CS02': '$04',
+ 'TCCR0_CS01': '$02',
+ 'TCCR0_CS00': '$01',
+ 'TCNT0': '&82',
+ 'TCCR1A': '&79',
+ 'TCCR1A_COM1A': '$C0',
+ 'TCCR1A_COM1B': '$30',
+ 'TCCR1A_FOC1A': '$08',
+ 'TCCR1A_FOC1B': '$04',
+ 'TCCR1A_WGM1': '$03',
+ 'TCCR1B': '&78',
+ 'TCCR1B_ICNC1': '$80',
+ 'TCCR1B_ICES1': '$40',
+ 'TCCR1B_WGM1': '$18',
+ 'TCCR1B_CS1': '$07',
+ 'TCNT1': '&76',
+ 'OCR1A': '&74',
+ 'OCR1B': '&72',
+ 'ICR1': '&70',
+ 'TCCR2': '&69',
+ 'TCCR2_FOC2': '$80',
+ 'TCCR2_WGM20': '$40',
+ 'TCCR2_COM2': '$30',
+ 'TCCR2_WGM21': '$08',
+ 'TCCR2_CS2': '$07',
+ 'TCNT2': '&68',
+ 'OCR2': '&67',
+ 'ASSR': '&66',
+ 'ASSR_AS2': '$08',
+ 'ASSR_TCN2UB': '$04',
+ 'ASSR_OCR2UB': '$02',
+ 'ASSR_TCR2UB': '$01',
+ 'UDR': '&44',
+ 'UCSRA': '&43',
+ 'UCSRA_RXC': '$80',
+ 'UCSRA_TXC': '$40',
+ 'UCSRA_UDRE': '$20',
+ 'UCSRA_FE': '$10',
+ 'UCSRA_DOR': '$08',
+ 'UCSRA_UPE': '$04',
+ 'UCSRA_U2X': '$02',
+ 'UCSRA_MPCM': '$01',
+ 'UCSRB': '&42',
+ 'UCSRB_RXCIE': '$80',
+ 'UCSRB_TXCIE': '$40',
+ 'UCSRB_UDRIE': '$20',
+ 'UCSRB_RXEN': '$10',
+ 'UCSRB_TXEN': '$08',
+ 'UCSRB_UCSZ2': '$04',
+ 'UCSRB_RXB8': '$02',
+ 'UCSRB_TXB8': '$01',
+ 'UCSRC': '&64',
+ 'UCSRC_URSEL': '$80',
+ 'UCSRC_UMSEL': '$40',
+ 'UCSRC_UPM': '$30',
+ 'UCSRC_USBS': '$08',
+ 'UCSRC_UCSZ': '$06',
+ 'UCSRC_UCPOL': '$01',
+ 'UBRRH': '&64',
+ 'UBRRL': '&41',
+ 'TWBR': '&32',
+ 'TWCR': '&86',
+ 'TWCR_TWINT': '$80',
+ 'TWCR_TWEA': '$40',
+ 'TWCR_TWSTA': '$20',
+ 'TWCR_TWSTO': '$10',
+ 'TWCR_TWWC': '$08',
+ 'TWCR_TWEN': '$04',
+ 'TWCR_TWIE': '$01',
+ 'TWSR': '&33',
+ 'TWSR_TWS': '$F8',
+ 'TWSR_TWPS': '$03',
+ 'TWDR': '&35',
+ 'TWAR': '&34',
+ 'TWAR_TWA': '$FE',
+ 'TWAR_TWGCE': '$01',
+ 'WDTCR': '&65',
+ 'WDTCR_WDCE': '$10',
+ 'WDTCR_WDE': '$08',
+ 'WDTCR_WDP': '$07',
+ 'PORTB': '&56',
+ 'DDRB': '&55',
+ 'PINB': '&54',
+ 'PORTC': '&53',
+ 'DDRC': '&52',
+ 'PINC': '&51',
+ 'PORTD': '&50',
+ 'DDRD': '&49',
+ 'PIND': '&48',
+ 'EEAR': '&62',
+ 'EEDR': '&61',
+ 'EECR': '&60',
+ 'EECR_EERIE': '$08',
+ 'EECR_EEMWE': '$04',
+ 'EECR_EEWE': '$02',
+ 'EECR_EERE': '$01',
+ 'SREG': '&95',
+ 'SREG_I': '$80',
+ 'SREG_T': '$40',
+ 'SREG_H': '$20',
+ 'SREG_S': '$10',
+ 'SREG_V': '$08',
+ 'SREG_N': '$04',
+ 'SREG_Z': '$02',
+ 'SREG_C': '$01',
+ 'SP': '&93',
+ 'MCUCSR': '&84',
+ 'MCUCSR_WDRF': '$08',
+ 'MCUCSR_BORF': '$04',
+ 'MCUCSR_EXTRF': '$02',
+ 'MCUCSR_PORF': '$01',
+ 'OSCCAL': '&81',
+ 'SPMCR': '&87',
+ 'SPMCR_SPMIE': '$80',
+ 'SPMCR_RWWSB': '$40',
+ 'SPMCR_RWWSRE': '$10',
+ 'SPMCR_BLBSET': '$08',
+ 'SPMCR_PGWRT': '$04',
+ 'SPMCR_PGERS': '$02',
+ 'SPMCR_SPMEN': '$01',
+ 'ADMUX': '&39',
+ 'ADMUX_REFS': '$C0',
+ 'ADMUX_ADLAR': '$20',
+ 'ADMUX_MUX': '$0F',
+ 'ADCSRA': '&38',
+ 'ADCSRA_ADEN': '$80',
+ 'ADCSRA_ADSC': '$40',
+ 'ADCSRA_ADFR': '$20',
+ 'ADCSRA_ADIF': '$10',
+ 'ADCSRA_ADIE': '$08',
+ 'ADCSRA_ADPS': '$07',
+ 'ADC': '&36',
+ 'INT0Addr': '1',
+ 'INT1Addr': '2',
+ 'TIMER2_COMPAddr': '3',
+ 'TIMER2_OVFAddr': '4',
+ 'TIMER1_CAPTAddr': '5',
+ 'TIMER1_COMPAAddr': '6',
+ 'TIMER1_COMPBAddr': '7',
+ 'TIMER1_OVFAddr': '8',
+ 'TIMER0_OVFAddr': '9',
+ 'SPI__STCAddr': '10',
+ 'USART__RXCAddr': '11',
+ 'USART__UDREAddr': '12',
+ 'USART__TXCAddr': '13',
+ 'ADCAddr': '14',
+ 'EE_RDYAddr': '15',
+ 'ANA_COMPAddr': '16',
+ 'TWIAddr': '17',
+ 'SPM_RDYAddr': '18'
+} \ No newline at end of file
diff --git a/amforth-6.5/avr8/devices/atmega8a/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega8a/words/no-jtag.asm
new file mode 100644
index 0000000..352a4bb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega8a/words/no-jtag.asm
@@ -0,0 +1,14 @@
+; ( -- )
+; ( -- )
+; MCU
+; disable jtag at runtime
+VE_NOJTAG:
+ .dw $FF05
+ .db "-jtag",0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOJTAG
+XT_NOJTAG:
+ .dw PFA_NOJTAG
+PFA_NOJTAG:
+
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega8a/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega8a/words/no-wdt.asm
new file mode 100644
index 0000000..4a12261
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega8a/words/no-wdt.asm
@@ -0,0 +1,22 @@
+; ( -- )
+; MCU
+; disable watch dog timer at runtime
+VE_NOWDT:
+ .dw $ff04
+ .db "-wdt"
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOWDT
+XT_NOWDT:
+ .dw PFA_NOWDT
+PFA_NOWDT:
+
+; Reset WDT
+ wdr
+; Write logical one to WDTOE and WDE
+ in_ temp1, WDTCR
+ ori temp1, (1<<WDTOE)|(1<<WDE)
+ out WDTCR, temp1
+; Turn off WDT
+ ldi temp1, (0<<WDE)
+ out_ WDTCR, temp1
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega8a/words/sleep.asm b/amforth-6.5/avr8/devices/atmega8a/words/sleep.asm
new file mode 100644
index 0000000..778fa32
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega8a/words/sleep.asm
@@ -0,0 +1,24 @@
+; ( mode -- )
+; MCU
+; put the controller into the specified sleep mode
+VE_SLEEP:
+ .dw $ff05
+ .db "sleep", 0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_SLEEP
+XT_SLEEP:
+ .dw PFA_SLEEP
+PFA_SLEEP:
+ andi tosl, 7 ; leave only legal mode bits
+ swap tosl ; move to correct location (bits 6-4, atmega32)
+ ori tosl, $80 ; set the SE bit (atmega32: bit 7, not bit 0)
+ out_ MCUCR, tosl ; set the sleep config (atmega32: MCUCR not SMCR)
+ sleep ; nighty-night
+;; the 4 lower bits of MCUCR should not be touched
+ in_ tosl, MCUCR
+ andi tosl, $0F
+ out_ MCUCR, tosl
+ ;clr tosl ; need to clean up the SMCR reg before we leave
+ ;out SMCR, tosl ; 0 protects against accidental sleeps
+ loadtos ; pop argument from stack
+ jmp DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega8hva/atmega8hva.frt b/amforth-6.5/avr8/devices/atmega8hva/atmega8hva.frt
new file mode 100644
index 0000000..a2b741b
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega8hva/atmega8hva.frt
@@ -0,0 +1,140 @@
+\ Partname: ATmega8HVA
+\ Built using part description XML file version 1
+\ generated automatically
+
+hex
+
+\ AD_CONVERTER
+79 constant VADCH \ VADC Data Register High Byte
+78 constant VADCL \ VADC Data Register Low Byte
+7A constant VADCSR \ The VADC Control and Status register
+7C constant VADMUX \ The VADC multiplexer Selection Register
+
+\ BANDGAP
+D0 constant BGCCR \ Bandgap Calibration Register
+D1 constant BGCRR \ Bandgap Calibration of Resistor Ladder
+
+\ BATTERY_PROTECTION
+F9 constant BPCHCD \ Battery Protection Charge-High-current Detection Level Register
+F7 constant BPCOCD \ Battery Protection Charge-Over-current Detection Level Register
+FD constant BPCR \ Battery Protection Control Register
+F8 constant BPDHCD \ Battery Protection Discharge-High-current Detection Level Register
+F6 constant BPDOCD \ Battery Protection Discharge-Over-current Detection Level Register
+FC constant BPHCTR \ Battery Protection Short-current Timing Register
+F3 constant BPIFR \ Battery Protection Interrupt Flag Register
+F2 constant BPIMSK \ Battery Protection Interrupt Mask Register
+FB constant BPOCTR \ Battery Protection Over-current Timing Register
+FE constant BPPLR \ Battery Protection Parameter Lock Register
+F5 constant BPSCD \ Battery Protection Short-Circuit Detection Level Register
+FA constant BPSCTR \ Battery Protection Short-current Timing Register
+
+\ BOOT_LOAD
+57 constant SPMCSR \ Store Program Memory Control and Status Register
+
+\ COULOMB_COUNTER
+E0 constant CADAC0 \ ADC Accumulate Current
+E1 constant CADAC1 \ ADC Accumulate Current
+E2 constant CADAC2 \ ADC Accumulate Current
+E3 constant CADAC3 \ ADC Accumulate Current
+E4 constant CADCSRA \ CC-ADC Control and Status Register A
+E5 constant CADCSRB \ CC-ADC Control and Status Register B
+E9 constant CADICH \ CC-ADC Instantaneous Current
+E8 constant CADICL \ CC-ADC Instantaneous Current
+E6 constant CADRC \ CC-ADC Regular Current
+
+\ CPU
+61 constant CLKPR \ Clock Prescale Register
+7E constant DIDR0 \ Digital Input Disable Register
+66 constant FOSCCAL \ Fast Oscillator Calibration Value
+3E constant GPIOR0 \ General Purpose IO Register 0
+4A constant GPIOR1 \ General Purpose IO Register 1
+4B constant GPIOR2 \ General Purpose IO Register 2
+55 constant MCUCR \ MCU Control Register
+54 constant MCUSR \ MCU Status Register
+37 constant OSICSR \ Oscillator Sampling Interface Control and Status Register
+64 constant PRR0 \ Power Reduction Register 0
+53 constant SMCR \ Sleep Mode Control Register
+5E constant SPH \ Stack Pointer High
+5D constant SPL \ Stack Pointer Low
+5F constant SREG \ Status Register
+
+\ EEPROM
+41 constant EEAR \ EEPROM Read/Write Access
+3F constant EECR \ EEPROM Control Register
+40 constant EEDR \ EEPROM Data Register
+
+\ EXTERNAL_INTERRUPT
+69 constant EICRA \ External Interrupt Control Register
+3C constant EIFR \ External Interrupt Flag Register
+3D constant EIMSK \ External Interrupt Mask Register
+
+\ FET
+F0 constant FCSR \ FET Control and Status Register
+
+\ PORTA
+21 constant DDRA \ Port A Data Direction Register
+20 constant PINA \ Port A Input Pins
+22 constant PORTA \ Port A Data Register
+
+\ PORTB
+24 constant DDRB \ Data Direction Register, Port B
+23 constant PINB \ Input Pins, Port B
+25 constant PORTB \ Data Register, Port B
+
+\ PORTC
+26 constant PINC \ Port C Input Pins
+28 constant PORTC \ Port C Data Register
+
+\ SPI
+4c constant SPCR \ SPI Control Register
+4e constant SPDR \ SPI Data Register
+4d constant SPSR \ SPI Status Register
+
+\ TIMER_COUNTER_0
+48 constant OCR0A \ Output compare Register A
+49 constant OCR0B \ Output compare Register B
+44 constant TCCR0A \ Timer/Counter0 Control Register
+45 constant TCCR0B \ Timer/Counter0 Control Register
+47 constant TCNT0H \ Timer Counter 0 High Byte
+46 constant TCNT0L \ Timer Counter 0 Low Byte
+35 constant TIFR0 \ Timer/Counter Interrupt Flag register
+6E constant TIMSK0 \ Timer/Counter Interrupt Mask Register
+
+\ TIMER_COUNTER_1
+43 constant GTCCR \ General Timer/Counter Control Register
+88 constant OCR1A \ Output Compare Register 1A
+89 constant OCR1B \ Output Compare Register B
+80 constant TCCR1A \ Timer/Counter 1 Control Register A
+81 constant TCCR1B \ Timer/Counter1 Control Register B
+85 constant TCNT1H \ Timer Counter 1 High Byte
+84 constant TCNT1L \ Timer Counter 1 Low Byte
+36 constant TIFR1 \ Timer/Counter Interrupt Flag register
+6F constant TIMSK1 \ Timer/Counter Interrupt Mask Register
+
+\ VOLTAGE_REGULATOR
+C8 constant ROCR \ Regulator Operating Condition Register
+
+\ WATCHDOG
+60 constant WDTCSR \ Watchdog Timer Control Register
+
+\ Interrupts
+0001 constant BPINTAddr \ Battery Protection Interrupt
+0002 constant VREGMONAddr \ Voltage regulator monitor interrupt
+0003 constant INT0Addr \ External Interrupt Request 0
+0004 constant INT1Addr \ External Interrupt Request 1
+0005 constant INT2Addr \ External Interrupt Request 2
+0006 constant WDTAddr \ Watchdog Timeout Interrupt
+0007 constant TIMER1_ICAddr \ Timer 1 Input capture
+0008 constant TIMER1_COMPAAddr \ Timer 1 Compare Match A
+0009 constant TIMER1_COMPBAddr \ Timer 1 Compare Match B
+000A constant TIMER1_OVFAddr \ Timer 1 overflow
+000B constant TIMER0_ICAddr \ Timer 0 Input Capture
+000C constant TIMER0_COMPAAddr \ Timer 0 Comapre Match A
+000D constant TIMER0_COMPBAddr \ Timer 0 Compare Match B
+000E constant TIMER0_OVFAddr \ Timer 0 Overflow
+000F constant SPI;STCAddr \ SPI Serial transfer complete
+0010 constant VADCAddr \ Voltage ADC Conversion Complete
+0011 constant CCADC_CONVAddr \ Coulomb Counter ADC Conversion Complete
+0012 constant CCADC_REG_CURAddr \ Coloumb Counter ADC Regular Current
+0013 constant CCADC_ACCAddr \ Coloumb Counter ADC Accumulator
+014 constant EE_READYAddr \ EEPROM Ready
diff --git a/amforth-6.5/avr8/devices/atmega8hva/device.asm b/amforth-6.5/avr8/devices/atmega8hva/device.asm
new file mode 100644
index 0000000..c556dc6
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega8hva/device.asm
@@ -0,0 +1,114 @@
+; Partname: ATmega8HVA
+; Built using part description XML file version 1
+; generated automatically, do not edit
+
+.nolist
+ .include "m8HVAdef.inc"
+.list
+
+.equ ramstart = $100
+.equ CELLSIZE = 2
+.macro readflashcell
+ lsl zl
+ rol zh
+ lpm @0, Z+
+ lpm @1, Z+
+.endmacro
+.macro writeflashcell
+ lsl zl
+ rol zh
+.endmacro
+
+; the following definitions are shortcuts for the respective forth source segments if set to 1
+.set WANT_AD_CONVERTER = 0
+.set WANT_BANDGAP = 0
+.set WANT_BATTERY_PROTECTION = 0
+.set WANT_BOOT_LOAD = 0
+.set WANT_COULOMB_COUNTER = 0
+.set WANT_CPU = 0
+.set WANT_EEPROM = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_FET = 0
+.set WANT_PORTA = 0
+.set WANT_PORTB = 0
+.set WANT_PORTC = 0
+.set WANT_SPI = 0
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_VOLTAGE_REGULATOR = 0
+.set WANT_WATCHDOG = 0
+
+
+.ifndef SPMEN
+ .equ SPMEN = SELFPRGEN
+.endif
+
+.ifndef SPMCSR
+ .equ SPMCSR = SPMCR
+.endif
+
+.ifndef EEPE
+ .equ EEPE = EEWE
+.endif
+
+.ifndef EEMPE
+ .equ EEMPE = EEMWE
+.endif
+.equ intvecsize = 1 ; please verify; flash size: 8192 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.equ INTVECTORS = 21
+.org $0001
+ rcall isr ; Battery Protection Interrupt
+.org $0002
+ rcall isr ; Voltage regulator monitor interrupt
+.org $0003
+ rcall isr ; External Interrupt Request 0
+.org $0004
+ rcall isr ; External Interrupt Request 1
+.org $0005
+ rcall isr ; External Interrupt Request 2
+.org $0006
+ rcall isr ; Watchdog Timeout Interrupt
+.org $0007
+ rcall isr ; Timer 1 Input capture
+.org $0008
+ rcall isr ; Timer 1 Compare Match A
+.org $0009
+ rcall isr ; Timer 1 Compare Match B
+.org $000A
+ rcall isr ; Timer 1 overflow
+.org $000B
+ rcall isr ; Timer 0 Input Capture
+.org $000C
+ rcall isr ; Timer 0 Comapre Match A
+.org $000D
+ rcall isr ; Timer 0 Compare Match B
+.org $000E
+ rcall isr ; Timer 0 Overflow
+.org $000F
+ rcall isr ; SPI Serial transfer complete
+.org $0010
+ rcall isr ; Voltage ADC Conversion Complete
+.org $0011
+ rcall isr ; Coulomb Counter ADC Conversion Complete
+.org $0012
+ rcall isr ; Coloumb Counter ADC Regular Current
+.org $0013
+ rcall isr ; Coloumb Counter ADC Accumulator
+.org $014
+ rcall isr ; EEPROM Ready
+.nooverlap
+mcu_info:
+mcu_ramsize:
+ .dw 512
+mcu_eepromsize:
+ .dw 256
+mcu_maxdp:
+ .dw 0 ; minimum of 0 (from XML) and 0xffff
+mcu_numints:
+ .dw 21
+mcu_name:
+ .dw 10
+ .db "ATmega8HVA"
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega8hva/device.inc b/amforth-6.5/avr8/devices/atmega8hva/device.inc
new file mode 100644
index 0000000..0405071
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega8hva/device.inc
@@ -0,0 +1,1053 @@
+; Partname: ATmega8HVA
+; Built using part description XML file version 1
+; generated automatically, no not edit
+
+; ********
+.if WANT_AD_CONVERTER == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; VADC Data Register High Byte
+VE_VADCH:
+ .dw $ff05
+ .db "VADCH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_VADCH
+XT_VADCH:
+ .dw PFA_DOVARIABLE
+PFA_VADCH:
+ .dw $79
+; ( -- addr ) System Constant
+; R( -- )
+; VADC Data Register Low Byte
+VE_VADCL:
+ .dw $ff05
+ .db "VADCL",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_VADCL
+XT_VADCL:
+ .dw PFA_DOVARIABLE
+PFA_VADCL:
+ .dw $78
+; ( -- addr ) System Constant
+; R( -- )
+; The VADC Control and Status register
+VE_VADCSR:
+ .dw $ff06
+ .db "VADCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_VADCSR
+XT_VADCSR:
+ .dw PFA_DOVARIABLE
+PFA_VADCSR:
+ .dw $7A
+; ( -- addr ) System Constant
+; R( -- )
+; The VADC multiplexer Selection Register
+VE_VADMUX:
+ .dw $ff06
+ .db "VADMUX"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_VADMUX
+XT_VADMUX:
+ .dw PFA_DOVARIABLE
+PFA_VADMUX:
+ .dw $7C
+
+.endif
+
+; ********
+.if WANT_BANDGAP == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Bandgap Calibration Register
+VE_BGCCR:
+ .dw $ff05
+ .db "BGCCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_BGCCR
+XT_BGCCR:
+ .dw PFA_DOVARIABLE
+PFA_BGCCR:
+ .dw $D0
+; ( -- addr ) System Constant
+; R( -- )
+; Bandgap Calibration of Resistor Ladder
+VE_BGCRR:
+ .dw $ff05
+ .db "BGCRR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_BGCRR
+XT_BGCRR:
+ .dw PFA_DOVARIABLE
+PFA_BGCRR:
+ .dw $D1
+
+.endif
+
+; ********
+.if WANT_BATTERY_PROTECTION == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Battery Protection Charge-High-current Detection Level Register
+VE_BPCHCD:
+ .dw $ff06
+ .db "BPCHCD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_BPCHCD
+XT_BPCHCD:
+ .dw PFA_DOVARIABLE
+PFA_BPCHCD:
+ .dw $F9
+; ( -- addr ) System Constant
+; R( -- )
+; Battery Protection Charge-Over-current Detection Level Register
+VE_BPCOCD:
+ .dw $ff06
+ .db "BPCOCD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_BPCOCD
+XT_BPCOCD:
+ .dw PFA_DOVARIABLE
+PFA_BPCOCD:
+ .dw $F7
+; ( -- addr ) System Constant
+; R( -- )
+; Battery Protection Control Register
+VE_BPCR:
+ .dw $ff04
+ .db "BPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_BPCR
+XT_BPCR:
+ .dw PFA_DOVARIABLE
+PFA_BPCR:
+ .dw $FD
+; ( -- addr ) System Constant
+; R( -- )
+; Battery Protection Discharge-High-current Detection Level Register
+VE_BPDHCD:
+ .dw $ff06
+ .db "BPDHCD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_BPDHCD
+XT_BPDHCD:
+ .dw PFA_DOVARIABLE
+PFA_BPDHCD:
+ .dw $F8
+; ( -- addr ) System Constant
+; R( -- )
+; Battery Protection Discharge-Over-current Detection Level Register
+VE_BPDOCD:
+ .dw $ff06
+ .db "BPDOCD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_BPDOCD
+XT_BPDOCD:
+ .dw PFA_DOVARIABLE
+PFA_BPDOCD:
+ .dw $F6
+; ( -- addr ) System Constant
+; R( -- )
+; Battery Protection Short-current Timing Register
+VE_BPHCTR:
+ .dw $ff06
+ .db "BPHCTR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_BPHCTR
+XT_BPHCTR:
+ .dw PFA_DOVARIABLE
+PFA_BPHCTR:
+ .dw $FC
+; ( -- addr ) System Constant
+; R( -- )
+; Battery Protection Interrupt Flag Register
+VE_BPIFR:
+ .dw $ff05
+ .db "BPIFR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_BPIFR
+XT_BPIFR:
+ .dw PFA_DOVARIABLE
+PFA_BPIFR:
+ .dw $F3
+; ( -- addr ) System Constant
+; R( -- )
+; Battery Protection Interrupt Mask Register
+VE_BPIMSK:
+ .dw $ff06
+ .db "BPIMSK"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_BPIMSK
+XT_BPIMSK:
+ .dw PFA_DOVARIABLE
+PFA_BPIMSK:
+ .dw $F2
+; ( -- addr ) System Constant
+; R( -- )
+; Battery Protection Over-current Timing Register
+VE_BPOCTR:
+ .dw $ff06
+ .db "BPOCTR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_BPOCTR
+XT_BPOCTR:
+ .dw PFA_DOVARIABLE
+PFA_BPOCTR:
+ .dw $FB
+; ( -- addr ) System Constant
+; R( -- )
+; Battery Protection Parameter Lock Register
+VE_BPPLR:
+ .dw $ff05
+ .db "BPPLR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_BPPLR
+XT_BPPLR:
+ .dw PFA_DOVARIABLE
+PFA_BPPLR:
+ .dw $FE
+; ( -- addr ) System Constant
+; R( -- )
+; Battery Protection Short-Circuit Detection Level Register
+VE_BPSCD:
+ .dw $ff05
+ .db "BPSCD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_BPSCD
+XT_BPSCD:
+ .dw PFA_DOVARIABLE
+PFA_BPSCD:
+ .dw $F5
+; ( -- addr ) System Constant
+; R( -- )
+; Battery Protection Short-current Timing Register
+VE_BPSCTR:
+ .dw $ff06
+ .db "BPSCTR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_BPSCTR
+XT_BPSCTR:
+ .dw PFA_DOVARIABLE
+PFA_BPSCTR:
+ .dw $FA
+
+.endif
+
+; ********
+.if WANT_BOOT_LOAD == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control and Status Register
+VE_SPMCSR:
+ .dw $ff06
+ .db "SPMCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCSR
+XT_SPMCSR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCSR:
+ .dw $57
+
+.endif
+
+; ********
+.if WANT_COULOMB_COUNTER == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Accumulate Current
+VE_CADAC0:
+ .dw $ff06
+ .db "CADAC0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CADAC0
+XT_CADAC0:
+ .dw PFA_DOVARIABLE
+PFA_CADAC0:
+ .dw $E0
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Accumulate Current
+VE_CADAC1:
+ .dw $ff06
+ .db "CADAC1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CADAC1
+XT_CADAC1:
+ .dw PFA_DOVARIABLE
+PFA_CADAC1:
+ .dw $E1
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Accumulate Current
+VE_CADAC2:
+ .dw $ff06
+ .db "CADAC2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CADAC2
+XT_CADAC2:
+ .dw PFA_DOVARIABLE
+PFA_CADAC2:
+ .dw $E2
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Accumulate Current
+VE_CADAC3:
+ .dw $ff06
+ .db "CADAC3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CADAC3
+XT_CADAC3:
+ .dw PFA_DOVARIABLE
+PFA_CADAC3:
+ .dw $E3
+; ( -- addr ) System Constant
+; R( -- )
+; CC-ADC Control and Status Register A
+VE_CADCSRA:
+ .dw $ff07
+ .db "CADCSRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CADCSRA
+XT_CADCSRA:
+ .dw PFA_DOVARIABLE
+PFA_CADCSRA:
+ .dw $E4
+; ( -- addr ) System Constant
+; R( -- )
+; CC-ADC Control and Status Register B
+VE_CADCSRB:
+ .dw $ff07
+ .db "CADCSRB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CADCSRB
+XT_CADCSRB:
+ .dw PFA_DOVARIABLE
+PFA_CADCSRB:
+ .dw $E5
+; ( -- addr ) System Constant
+; R( -- )
+; CC-ADC Instantaneous Current
+VE_CADICH:
+ .dw $ff06
+ .db "CADICH"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CADICH
+XT_CADICH:
+ .dw PFA_DOVARIABLE
+PFA_CADICH:
+ .dw $E9
+; ( -- addr ) System Constant
+; R( -- )
+; CC-ADC Instantaneous Current
+VE_CADICL:
+ .dw $ff06
+ .db "CADICL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CADICL
+XT_CADICL:
+ .dw PFA_DOVARIABLE
+PFA_CADICL:
+ .dw $E8
+; ( -- addr ) System Constant
+; R( -- )
+; CC-ADC Regular Current
+VE_CADRC:
+ .dw $ff05
+ .db "CADRC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CADRC
+XT_CADRC:
+ .dw PFA_DOVARIABLE
+PFA_CADRC:
+ .dw $E6
+
+.endif
+
+; ********
+.if WANT_CPU == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Clock Prescale Register
+VE_CLKPR:
+ .dw $ff05
+ .db "CLKPR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKPR
+XT_CLKPR:
+ .dw PFA_DOVARIABLE
+PFA_CLKPR:
+ .dw $61
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register
+VE_DIDR0:
+ .dw $ff05
+ .db "DIDR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR0
+XT_DIDR0:
+ .dw PFA_DOVARIABLE
+PFA_DIDR0:
+ .dw $7E
+; ( -- addr ) System Constant
+; R( -- )
+; Fast Oscillator Calibration Value
+VE_FOSCCAL:
+ .dw $ff07
+ .db "FOSCCAL",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_FOSCCAL
+XT_FOSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_FOSCCAL:
+ .dw $66
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 0
+VE_GPIOR0:
+ .dw $ff06
+ .db "GPIOR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR0
+XT_GPIOR0:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR0:
+ .dw $3E
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 1
+VE_GPIOR1:
+ .dw $ff06
+ .db "GPIOR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR1
+XT_GPIOR1:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR1:
+ .dw $4A
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 2
+VE_GPIOR2:
+ .dw $ff06
+ .db "GPIOR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR2
+XT_GPIOR2:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR2:
+ .dw $4B
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw $55
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Status Register
+VE_MCUSR:
+ .dw $ff05
+ .db "MCUSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUSR
+XT_MCUSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUSR:
+ .dw $54
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Sampling Interface Control and Status Register
+VE_OSICSR:
+ .dw $ff06
+ .db "OSICSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSICSR
+XT_OSICSR:
+ .dw PFA_DOVARIABLE
+PFA_OSICSR:
+ .dw $37
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register 0
+VE_PRR0:
+ .dw $ff04
+ .db "PRR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR0
+XT_PRR0:
+ .dw PFA_DOVARIABLE
+PFA_PRR0:
+ .dw $64
+; ( -- addr ) System Constant
+; R( -- )
+; Sleep Mode Control Register
+VE_SMCR:
+ .dw $ff04
+ .db "SMCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SMCR
+XT_SMCR:
+ .dw PFA_DOVARIABLE
+PFA_SMCR:
+ .dw $53
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer High
+VE_SPH:
+ .dw $ff03
+ .db "SPH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPH
+XT_SPH:
+ .dw PFA_DOVARIABLE
+PFA_SPH:
+ .dw $5E
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer Low
+VE_SPL:
+ .dw $ff03
+ .db "SPL",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPL
+XT_SPL:
+ .dw PFA_DOVARIABLE
+PFA_SPL:
+ .dw $5D
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw $5F
+
+.endif
+
+; ********
+.if WANT_EEPROM == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Read/Write Access
+VE_EEAR:
+ .dw $ff04
+ .db "EEAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEAR
+XT_EEAR:
+ .dw PFA_DOVARIABLE
+PFA_EEAR:
+ .dw $41
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw $3F
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw $40
+
+.endif
+
+; ********
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register
+VE_EICRA:
+ .dw $ff05
+ .db "EICRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRA
+XT_EICRA:
+ .dw PFA_DOVARIABLE
+PFA_EICRA:
+ .dw $69
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Flag Register
+VE_EIFR:
+ .dw $ff04
+ .db "EIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIFR
+XT_EIFR:
+ .dw PFA_DOVARIABLE
+PFA_EIFR:
+ .dw $3C
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Mask Register
+VE_EIMSK:
+ .dw $ff05
+ .db "EIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIMSK
+XT_EIMSK:
+ .dw PFA_DOVARIABLE
+PFA_EIMSK:
+ .dw $3D
+
+.endif
+
+; ********
+.if WANT_FET == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; FET Control and Status Register
+VE_FCSR:
+ .dw $ff04
+ .db "FCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_FCSR
+XT_FCSR:
+ .dw PFA_DOVARIABLE
+PFA_FCSR:
+ .dw $F0
+
+.endif
+
+; ********
+.if WANT_PORTA == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Direction Register
+VE_DDRA:
+ .dw $ff04
+ .db "DDRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRA
+XT_DDRA:
+ .dw PFA_DOVARIABLE
+PFA_DDRA:
+ .dw $21
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Input Pins
+VE_PINA:
+ .dw $ff04
+ .db "PINA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINA
+XT_PINA:
+ .dw PFA_DOVARIABLE
+PFA_PINA:
+ .dw $20
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Register
+VE_PORTA:
+ .dw $ff05
+ .db "PORTA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTA
+XT_PORTA:
+ .dw PFA_DOVARIABLE
+PFA_PORTA:
+ .dw $22
+
+.endif
+
+; ********
+.if WANT_PORTB == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port B
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw $24
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port B
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw $23
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port B
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw $25
+
+.endif
+
+; ********
+.if WANT_PORTC == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Input Pins
+VE_PINC:
+ .dw $ff04
+ .db "PINC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINC
+XT_PINC:
+ .dw PFA_DOVARIABLE
+PFA_PINC:
+ .dw $26
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Register
+VE_PORTC:
+ .dw $ff05
+ .db "PORTC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTC
+XT_PORTC:
+ .dw PFA_DOVARIABLE
+PFA_PORTC:
+ .dw $28
+
+.endif
+
+; ********
+.if WANT_SPI == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR:
+ .dw $ff04
+ .db "SPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR
+XT_SPCR:
+ .dw PFA_DOVARIABLE
+PFA_SPCR:
+ .dw $4c
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR:
+ .dw $ff04
+ .db "SPDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR
+XT_SPDR:
+ .dw PFA_DOVARIABLE
+PFA_SPDR:
+ .dw $4e
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR:
+ .dw $ff04
+ .db "SPSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR
+XT_SPSR:
+ .dw PFA_DOVARIABLE
+PFA_SPSR:
+ .dw $4d
+
+.endif
+
+; ********
+.if WANT_TIMER_COUNTER_0 == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Output compare Register A
+VE_OCR0A:
+ .dw $ff05
+ .db "OCR0A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0A
+XT_OCR0A:
+ .dw PFA_DOVARIABLE
+PFA_OCR0A:
+ .dw $48
+; ( -- addr ) System Constant
+; R( -- )
+; Output compare Register B
+VE_OCR0B:
+ .dw $ff05
+ .db "OCR0B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0B
+XT_OCR0B:
+ .dw PFA_DOVARIABLE
+PFA_OCR0B:
+ .dw $49
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Control Register
+VE_TCCR0A:
+ .dw $ff06
+ .db "TCCR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0A
+XT_TCCR0A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0A:
+ .dw $44
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Control Register
+VE_TCCR0B:
+ .dw $ff06
+ .db "TCCR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0B
+XT_TCCR0B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0B:
+ .dw $45
+; ( -- addr ) System Constant
+; R( -- )
+; Timer Counter 0 High Byte
+VE_TCNT0H:
+ .dw $ff06
+ .db "TCNT0H"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0H
+XT_TCNT0H:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0H:
+ .dw $47
+; ( -- addr ) System Constant
+; R( -- )
+; Timer Counter 0 Low Byte
+VE_TCNT0L:
+ .dw $ff06
+ .db "TCNT0L"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0L
+XT_TCNT0L:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0L:
+ .dw $46
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Flag register
+VE_TIFR0:
+ .dw $ff05
+ .db "TIFR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR0
+XT_TIFR0:
+ .dw PFA_DOVARIABLE
+PFA_TIFR0:
+ .dw $35
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Mask Register
+VE_TIMSK0:
+ .dw $ff06
+ .db "TIMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK0
+XT_TIMSK0:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK0:
+ .dw $6E
+
+.endif
+
+; ********
+.if WANT_TIMER_COUNTER_1 == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; General Timer/Counter Control Register
+VE_GTCCR:
+ .dw $ff05
+ .db "GTCCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GTCCR
+XT_GTCCR:
+ .dw PFA_DOVARIABLE
+PFA_GTCCR:
+ .dw $43
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare Register 1A
+VE_OCR1A:
+ .dw $ff05
+ .db "OCR1A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1A
+XT_OCR1A:
+ .dw PFA_DOVARIABLE
+PFA_OCR1A:
+ .dw $88
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare Register B
+VE_OCR1B:
+ .dw $ff05
+ .db "OCR1B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1B
+XT_OCR1B:
+ .dw PFA_DOVARIABLE
+PFA_OCR1B:
+ .dw $89
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter 1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw $80
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw $81
+; ( -- addr ) System Constant
+; R( -- )
+; Timer Counter 1 High Byte
+VE_TCNT1H:
+ .dw $ff06
+ .db "TCNT1H"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1H
+XT_TCNT1H:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1H:
+ .dw $85
+; ( -- addr ) System Constant
+; R( -- )
+; Timer Counter 1 Low Byte
+VE_TCNT1L:
+ .dw $ff06
+ .db "TCNT1L"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1L
+XT_TCNT1L:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1L:
+ .dw $84
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Flag register
+VE_TIFR1:
+ .dw $ff05
+ .db "TIFR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR1
+XT_TIFR1:
+ .dw PFA_DOVARIABLE
+PFA_TIFR1:
+ .dw $36
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Mask Register
+VE_TIMSK1:
+ .dw $ff06
+ .db "TIMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK1
+XT_TIMSK1:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK1:
+ .dw $6F
+
+.endif
+
+; ********
+.if WANT_VOLTAGE_REGULATOR == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Regulator Operating Condition Register
+VE_ROCR:
+ .dw $ff04
+ .db "ROCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ROCR
+XT_ROCR:
+ .dw PFA_DOVARIABLE
+PFA_ROCR:
+ .dw $C8
+
+.endif
+
+; ********
+.if WANT_WATCHDOG == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCSR:
+ .dw $ff06
+ .db "WDTCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCSR
+XT_WDTCSR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCSR:
+ .dw $60
+
+.endif
diff --git a/amforth-6.5/avr8/devices/atmega8hva/device.py b/amforth-6.5/avr8/devices/atmega8hva/device.py
new file mode 100644
index 0000000..d16cdad
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega8hva/device.py
@@ -0,0 +1,104 @@
+# Partname: ATmega8HVA
+# Built using part description XML file version 1
+# generated automatically, do not edit
+MCUREGS = {
+ 'VADCH': '$79',
+ 'VADCL': '$78',
+ 'VADCSR': '$7A',
+ 'VADMUX': '$7C',
+ 'BGCCR': '$D0',
+ 'BGCRR': '$D1',
+ 'BPCHCD': '$F9',
+ 'BPCOCD': '$F7',
+ 'BPCR': '$FD',
+ 'BPDHCD': '$F8',
+ 'BPDOCD': '$F6',
+ 'BPHCTR': '$FC',
+ 'BPIFR': '$F3',
+ 'BPIMSK': '$F2',
+ 'BPOCTR': '$FB',
+ 'BPPLR': '$FE',
+ 'BPSCD': '$F5',
+ 'BPSCTR': '$FA',
+ 'SPMCSR': '$57',
+ 'CADAC0': '$E0',
+ 'CADAC1': '$E1',
+ 'CADAC2': '$E2',
+ 'CADAC3': '$E3',
+ 'CADCSRA': '$E4',
+ 'CADCSRB': '$E5',
+ 'CADICH': '$E9',
+ 'CADICL': '$E8',
+ 'CADRC': '$E6',
+ 'CLKPR': '$61',
+ 'DIDR0': '$7E',
+ 'FOSCCAL': '$66',
+ 'GPIOR0': '$3E',
+ 'GPIOR1': '$4A',
+ 'GPIOR2': '$4B',
+ 'MCUCR': '$55',
+ 'MCUSR': '$54',
+ 'OSICSR': '$37',
+ 'PRR0': '$64',
+ 'SMCR': '$53',
+ 'SPH': '$5E',
+ 'SPL': '$5D',
+ 'SREG': '$5F',
+ 'EEAR': '$41',
+ 'EECR': '$3F',
+ 'EEDR': '$40',
+ 'EICRA': '$69',
+ 'EIFR': '$3C',
+ 'EIMSK': '$3D',
+ 'FCSR': '$F0',
+ 'DDRA': '$21',
+ 'PINA': '$20',
+ 'PORTA': '$22',
+ 'DDRB': '$24',
+ 'PINB': '$23',
+ 'PORTB': '$25',
+ 'PINC': '$26',
+ 'PORTC': '$28',
+ 'SPCR': '$4c',
+ 'SPDR': '$4e',
+ 'SPSR': '$4d',
+ 'OCR0A': '$48',
+ 'OCR0B': '$49',
+ 'TCCR0A': '$44',
+ 'TCCR0B': '$45',
+ 'TCNT0H': '$47',
+ 'TCNT0L': '$46',
+ 'TIFR0': '$35',
+ 'TIMSK0': '$6E',
+ 'GTCCR': '$43',
+ 'OCR1A': '$88',
+ 'OCR1B': '$89',
+ 'TCCR1A': '$80',
+ 'TCCR1B': '$81',
+ 'TCNT1H': '$85',
+ 'TCNT1L': '$84',
+ 'TIFR1': '$36',
+ 'TIMSK1': '$6F',
+ 'ROCR': '$C8',
+ 'WDTCSR': '$60',
+ 'BPINTAddr': '$0001',
+ 'VREGMONAddr': '$0002',
+ 'INT0Addr': '$0003',
+ 'INT1Addr': '$0004',
+ 'INT2Addr': '$0005',
+ 'WDTAddr': '$0006',
+ 'TIMER1_ICAddr': '$0007',
+ 'TIMER1_COMPAAddr': '$0008',
+ 'TIMER1_COMPBAddr': '$0009',
+ 'TIMER1_OVFAddr': '$000A',
+ 'TIMER0_ICAddr': '$000B',
+ 'TIMER0_COMPAAddr': '$000C',
+ 'TIMER0_COMPBAddr': '$000D',
+ 'TIMER0_OVFAddr': '$000E',
+ 'SPI;STCAddr': '$000F',
+ 'VADCAddr': '$0010',
+ 'CCADC_CONVAddr': '$0011',
+ 'CCADC_REG_CURAddr': '$0012',
+ 'CCADC_ACCAddr': '$0013',
+ 'EE_READYAddr': '$014'
+} \ No newline at end of file
diff --git a/amforth-6.5/avr8/devices/atmega8u2/atmega8u2.frt b/amforth-6.5/avr8/devices/atmega8u2/atmega8u2.frt
new file mode 100644
index 0000000..5c42559
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega8u2/atmega8u2.frt
@@ -0,0 +1,357 @@
+\ Partname: ATmega8U2
+\ generated automatically
+
+\ PORTB
+&37 constant PORTB \ Port B Data Register
+&36 constant DDRB \ Port B Data Direction Register
+&35 constant PINB \ Port B Input Pins
+\ PORTD
+&43 constant PORTD \ Port D Data Register
+&42 constant DDRD \ Port D Data Direction Register
+&41 constant PIND \ Port D Input Pins
+\ SPI
+&76 constant SPCR \ SPI Control Register
+ $80 constant SPCR_SPIE \ SPI Interrupt Enable
+ $40 constant SPCR_SPE \ SPI Enable
+ $20 constant SPCR_DORD \ Data Order
+ $10 constant SPCR_MSTR \ Master/Slave Select
+ $08 constant SPCR_CPOL \ Clock polarity
+ $04 constant SPCR_CPHA \ Clock Phase
+ $03 constant SPCR_SPR \ SPI Clock Rate Selects
+&77 constant SPSR \ SPI Status Register
+ $80 constant SPSR_SPIF \ SPI Interrupt Flag
+ $40 constant SPSR_WCOL \ Write Collision Flag
+ $01 constant SPSR_SPI2X \ Double SPI Speed Bit
+&78 constant SPDR \ SPI Data Register
+\ BOOT_LOAD
+&87 constant SPMCSR \ Store Program Memory Control Register
+ $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
+ $20 constant SPMCSR_SIGRD \ Signature Row Read
+ $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
+ $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
+ $04 constant SPMCSR_PGWRT \ Page Write
+ $02 constant SPMCSR_PGERS \ Page Erase
+ $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
+\ EEPROM
+&65 constant EEAR \ EEPROM Address Register Low Bytes
+&64 constant EEDR \ EEPROM Data Register
+&63 constant EECR \ EEPROM Control Register
+ $30 constant EECR_EEPM \ EEPROM Programming Mode Bits
+ $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
+ $04 constant EECR_EEMPE \ EEPROM Master Write Enable
+ $02 constant EECR_EEPE \ EEPROM Write Enable
+ $01 constant EECR_EERE \ EEPROM Read Enable
+\ TIMER_COUNTER_0
+&72 constant OCR0B \ Timer/Counter0 Output Compare Register
+&71 constant OCR0A \ Timer/Counter0 Output Compare Register
+&70 constant TCNT0 \ Timer/Counter0
+&69 constant TCCR0B \ Timer/Counter Control Register B
+ $80 constant TCCR0B_FOC0A \ Force Output Compare A
+ $40 constant TCCR0B_FOC0B \ Force Output Compare B
+ $08 constant TCCR0B_WGM02 \
+ $07 constant TCCR0B_CS0 \ Clock Select
+&68 constant TCCR0A \ Timer/Counter Control Register A
+ $C0 constant TCCR0A_COM0A \ Compare Output Mode, Phase Correct PWM Mode
+ $30 constant TCCR0A_COM0B \ Compare Output Mode, Fast PWm
+ $03 constant TCCR0A_WGM0 \ Waveform Generation Mode
+&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
+ $04 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare Match B Interrupt Enable
+ $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match A Interrupt Enable
+ $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
+&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
+ $04 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare Flag 0B
+ $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0A
+ $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
+&67 constant GTCCR \ General Timer/Counter Control Register
+ $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
+ $01 constant GTCCR_PSRSYNC \ Prescaler Reset Timer/Counter1 and Timer/Counter0
+\ TIMER_COUNTER_1
+&128 constant TCCR1A \ Timer/Counter1 Control Register A
+ $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
+ $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
+ $0C constant TCCR1A_COM1C \ Compare Output Mode 1C, bits
+ $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
+&129 constant TCCR1B \ Timer/Counter1 Control Register B
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
+ $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
+&130 constant TCCR1C \ Timer/Counter 1 Control Register C
+ $80 constant TCCR1C_FOC1A \ Force Output Compare 1A
+ $40 constant TCCR1C_FOC1B \ Force Output Compare 1B
+ $20 constant TCCR1C_FOC1C \ Force Output Compare 1C
+&132 constant TCNT1 \ Timer/Counter1 Bytes
+&136 constant OCR1A \ Timer/Counter1 Output Compare Register A Bytes
+&138 constant OCR1B \ Timer/Counter1 Output Compare Register B Bytes
+&140 constant OCR1C \ Timer/Counter1 Output Compare Register C Bytes
+&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
+&111 constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
+ $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
+ $08 constant TIMSK1_OCIE1C \ Timer/Counter1 Output Compare C Match Interrupt Enable
+ $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare B Match Interrupt Enable
+ $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare A Match Interrupt Enable
+ $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
+&54 constant TIFR1 \ Timer/Counter1 Interrupt Flag register
+ $20 constant TIFR1_ICF1 \ Input Capture Flag 1
+ $08 constant TIFR1_OCF1C \ Output Compare Flag 1C
+ $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
+ $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
+ $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
+\ PLL
+&73 constant PLLCSR \ PLL Status and Control register
+ $1C constant PLLCSR_PLLP \ PLL prescaler Bits
+ $02 constant PLLCSR_PLLE \ PLL Enable Bit
+ $01 constant PLLCSR_PLOCK \ PLL Lock Status Bit
+\ USB_DEVICE
+&244 constant UEINT \
+&242 constant UEBCLX \
+&241 constant UEDATX \
+&240 constant UEIENX \
+ $80 constant UEIENX_FLERRE \
+ $40 constant UEIENX_NAKINE \
+ $10 constant UEIENX_NAKOUTE \
+ $08 constant UEIENX_RXSTPE \
+ $04 constant UEIENX_RXOUTE \
+ $02 constant UEIENX_STALLEDE \
+ $01 constant UEIENX_TXINE \
+&239 constant UESTA1X \
+ $04 constant UESTA1X_CTRLDIR \
+ $03 constant UESTA1X_CURRBK \
+&238 constant UESTA0X \
+ $80 constant UESTA0X_CFGOK \
+ $40 constant UESTA0X_OVERFI \
+ $20 constant UESTA0X_UNDERFI \
+ $0C constant UESTA0X_DTSEQ \
+ $03 constant UESTA0X_NBUSYBK \
+&237 constant UECFG1X \
+ $70 constant UECFG1X_EPSIZE \
+ $0C constant UECFG1X_EPBK \
+ $02 constant UECFG1X_ALLOC \
+&236 constant UECFG0X \
+ $C0 constant UECFG0X_EPTYPE \
+ $01 constant UECFG0X_EPDIR \
+&235 constant UECONX \
+ $20 constant UECONX_STALLRQ \
+ $10 constant UECONX_STALLRQC \
+ $08 constant UECONX_RSTDT \
+ $01 constant UECONX_EPEN \
+&234 constant UERST \
+ $1F constant UERST_EPRST \
+&233 constant UENUM \
+&232 constant UEINTX \
+ $80 constant UEINTX_FIFOCON \
+ $40 constant UEINTX_NAKINI \
+ $20 constant UEINTX_RWAL \
+ $10 constant UEINTX_NAKOUTI \
+ $08 constant UEINTX_RXSTPI \
+ $04 constant UEINTX_RXOUTI \
+ $02 constant UEINTX_STALLEDI \
+ $01 constant UEINTX_TXINI \
+&230 constant UDMFN \
+ $10 constant UDMFN_FNCERR \
+&228 constant UDFNUM \
+&227 constant UDADDR \
+ $80 constant UDADDR_ADDEN \
+ $7F constant UDADDR_UADD \
+&226 constant UDIEN \
+ $40 constant UDIEN_UPRSME \
+ $20 constant UDIEN_EORSME \
+ $10 constant UDIEN_WAKEUPE \
+ $08 constant UDIEN_EORSTE \
+ $04 constant UDIEN_SOFE \
+ $01 constant UDIEN_SUSPE \
+&225 constant UDINT \
+ $40 constant UDINT_UPRSMI \
+ $20 constant UDINT_EORSMI \
+ $10 constant UDINT_WAKEUPI \
+ $08 constant UDINT_EORSTI \
+ $04 constant UDINT_SOFI \
+ $01 constant UDINT_SUSPI \
+&224 constant UDCON \
+ $04 constant UDCON_RSTCPU \
+ $02 constant UDCON_RMWKUP \
+ $01 constant UDCON_DETACH \
+&216 constant USBCON \ USB General Control Register
+ $80 constant USBCON_USBE \
+ $20 constant USBCON_FRZCLK \
+&99 constant REGCR \ Regulator Control Register
+ $01 constant REGCR_REGDIS \
+\ CPU
+&95 constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ $08 constant SREG_V \ Two's Complement Overflow Flag
+ $04 constant SREG_N \ Negative Flag
+ $02 constant SREG_Z \ Zero Flag
+ $01 constant SREG_C \ Carry Flag
+&93 constant SP \ Stack Pointer
+&85 constant MCUCR \ MCU Control Register
+ $10 constant MCUCR_PUD \ Pull-up disable
+ $02 constant MCUCR_IVSEL \ Interrupt Vector Select
+ $01 constant MCUCR_IVCE \ Interrupt Vector Change Enable
+&84 constant MCUSR \ MCU Status Register
+ $20 constant MCUSR_USBRF \ USB reset flag
+ $08 constant MCUSR_WDRF \ Watchdog Reset Flag
+ $04 constant MCUSR_BORF \ Brown-out Reset Flag
+ $02 constant MCUSR_EXTRF \ External Reset Flag
+ $01 constant MCUSR_PORF \ Power-on reset flag
+&102 constant OSCCAL \ Oscillator Calibration Value
+&97 constant CLKPR \
+ $80 constant CLKPR_CLKPCE \
+ $0F constant CLKPR_CLKPS \
+&83 constant SMCR \ Sleep Mode Control Register
+ $0E constant SMCR_SM \ Sleep Mode Select bits
+ $01 constant SMCR_SE \ Sleep Enable
+&92 constant EIND \ Extended Indirect Register
+&75 constant GPIOR2 \ General Purpose IO Register 2
+ $FF constant GPIOR2_GPIOR \ General Purpose IO Register 2 bis
+&74 constant GPIOR1 \ General Purpose IO Register 1
+ $FF constant GPIOR1_GPIOR \ General Purpose IO Register 1 bis
+&62 constant GPIOR0 \ General Purpose IO Register 0
+ $80 constant GPIOR0_GPIOR07 \ General Purpose IO Register 0 bit 7
+ $40 constant GPIOR0_GPIOR06 \ General Purpose IO Register 0 bit 6
+ $20 constant GPIOR0_GPIOR05 \ General Purpose IO Register 0 bit 5
+ $10 constant GPIOR0_GPIOR04 \ General Purpose IO Register 0 bit 4
+ $08 constant GPIOR0_GPIOR03 \ General Purpose IO Register 0 bit 3
+ $04 constant GPIOR0_GPIOR02 \ General Purpose IO Register 0 bit 2
+ $02 constant GPIOR0_GPIOR01 \ General Purpose IO Register 0 bit 1
+ $01 constant GPIOR0_GPIOR00 \ General Purpose IO Register 0 bit 0
+&101 constant PRR1 \ Power Reduction Register1
+ $80 constant PRR1_PRUSB \ Power Reduction USB
+ $01 constant PRR1_PRUSART1 \ Power Reduction USART1
+&100 constant PRR0 \ Power Reduction Register0
+ $20 constant PRR0_PRTIM0 \ Power Reduction Timer/Counter0
+ $08 constant PRR0_PRTIM1 \ Power Reduction Timer/Counter1
+ $04 constant PRR0_PRSPI \ Power Reduction Serial Peripheral Interface
+&210 constant CLKSTA \
+ $02 constant CLKSTA_RCON \
+ $01 constant CLKSTA_EXTON \
+&209 constant CLKSEL1 \
+ $F0 constant CLKSEL1_RCCKSEL \
+ $0F constant CLKSEL1_EXCKSEL \
+&208 constant CLKSEL0 \
+ $C0 constant CLKSEL0_RCSUT \
+ $30 constant CLKSEL0_EXSUT \
+ $08 constant CLKSEL0_RCE \
+ $04 constant CLKSEL0_EXTE \
+ $01 constant CLKSEL0_CLKS \
+&81 constant DWDR \ debugWire communication register
+\ EXTERNAL_INTERRUPT
+&105 constant EICRA \ External Interrupt Control Register A
+ $C0 constant EICRA_ISC3 \ External Interrupt Sense Control Bit
+ $30 constant EICRA_ISC2 \ External Interrupt Sense Control Bit
+ $0C constant EICRA_ISC1 \ External Interrupt Sense Control Bit
+ $03 constant EICRA_ISC0 \ External Interrupt Sense Control Bit
+&106 constant EICRB \ External Interrupt Control Register B
+ $C0 constant EICRB_ISC7 \ External Interrupt 7-4 Sense Control Bit
+ $30 constant EICRB_ISC6 \ External Interrupt 7-4 Sense Control Bit
+ $0C constant EICRB_ISC5 \ External Interrupt 7-4 Sense Control Bit
+ $03 constant EICRB_ISC4 \ External Interrupt 7-4 Sense Control Bit
+&61 constant EIMSK \ External Interrupt Mask Register
+ $FF constant EIMSK_INT \ External Interrupt Request 7 Enable
+&60 constant EIFR \ External Interrupt Flag Register
+ $FF constant EIFR_INTF \ External Interrupt Flags
+&107 constant PCMSK0 \ Pin Change Mask Register 0
+ $FF constant PCMSK0_PCINT \ Pin Change Enable Masks
+&108 constant PCMSK1 \ Pin Change Mask Register 1
+ $1F constant PCMSK1_PCINT \
+&59 constant PCIFR \ Pin Change Interrupt Flag Register
+ $03 constant PCIFR_PCIF \ Pin Change Interrupt Flags
+&104 constant PCICR \ Pin Change Interrupt Control Register
+ $03 constant PCICR_PCIE \ Pin Change Interrupt Enables
+\ USART1
+&206 constant UDR1 \ USART I/O Data Register
+&200 constant UCSR1A \ USART Control and Status Register A
+ $80 constant UCSR1A_RXC1 \ USART Receive Complete
+ $40 constant UCSR1A_TXC1 \ USART Transmitt Complete
+ $20 constant UCSR1A_UDRE1 \ USART Data Register Empty
+ $10 constant UCSR1A_FE1 \ Framing Error
+ $08 constant UCSR1A_DOR1 \ Data overRun
+ $04 constant UCSR1A_UPE1 \ Parity Error
+ $02 constant UCSR1A_U2X1 \ Double the USART transmission speed
+ $01 constant UCSR1A_MPCM1 \ Multi-processor Communication Mode
+&201 constant UCSR1B \ USART Control and Status Register B
+ $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable
+ $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable
+ $20 constant UCSR1B_UDRIE1 \ USART Data register Empty Interrupt Enable
+ $10 constant UCSR1B_RXEN1 \ Receiver Enable
+ $08 constant UCSR1B_TXEN1 \ Transmitter Enable
+ $04 constant UCSR1B_UCSZ12 \ Character Size
+ $02 constant UCSR1B_RXB81 \ Receive Data Bit 8
+ $01 constant UCSR1B_TXB81 \ Transmit Data Bit 8
+&202 constant UCSR1C \ USART Control and Status Register C
+ $C0 constant UCSR1C_UMSEL1 \ USART Mode Select
+ $30 constant UCSR1C_UPM1 \ Parity Mode Bits
+ $08 constant UCSR1C_USBS1 \ Stop Bit Select
+ $06 constant UCSR1C_UCSZ1 \ Character Size
+ $01 constant UCSR1C_UCPOL1 \ Clock Polarity
+&203 constant UCSR1D \ USART Control and Status Register D
+ $02 constant UCSR1D_CTSEN \ CTS Enable
+ $01 constant UCSR1D_RTSEN \ RTS Enable
+&204 constant UBRR1 \ USART Baud Rate Register Bytes
+\ WATCHDOG
+&96 constant WDTCSR \ Watchdog Timer Control Register
+ $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Flag
+ $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Enable
+ $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
+ $10 constant WDTCSR_WDCE \ Watchdog Change Enable
+ $08 constant WDTCSR_WDE \ Watch Dog Enable
+&98 constant WDTCKD \ Watchdog Timer Clock Divider
+ $08 constant WDTCKD_WDEWIF \ Watchdog Early Warning Interrupt Flag
+ $04 constant WDTCKD_WDEWIE \ Watchdog Early Warning Interrupt Enable
+ $03 constant WDTCKD_WCLKD \ Watchdog Timer Clock Dividers
+\ ANALOG_COMPARATOR
+&80 constant ACSR \ Analog Comparator Control And Status Register
+ $80 constant ACSR_ACD \ Analog Comparator Disable
+ $40 constant ACSR_ACBG \ Analog Comparator Bandgap Select
+ $20 constant ACSR_ACO \ Analog Compare Output
+ $10 constant ACSR_ACI \ Analog Comparator Interrupt Flag
+ $08 constant ACSR_ACIE \ Analog Comparator Interrupt Enable
+ $04 constant ACSR_ACIC \ Analog Comparator Input Capture Enable
+ $03 constant ACSR_ACIS \ Analog Comparator Interrupt Mode Select bits
+&127 constant DIDR1 \
+ $02 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
+ $01 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
+\ PORTC
+&40 constant PORTC \ Port C Data Register
+ $F0 constant PORTC_PORTC \ Port C Data Register bits
+ $07 constant PORTC_PORTC \ Port C Data Register bits
+&39 constant DDRC \ Port C Data Direction Register
+ $F0 constant DDRC_DDC \ Port C Data Direction Register bits
+ $07 constant DDRC_DDC \ Port C Data Direction Register bits
+&38 constant PINC \ Port C Input Pins
+ $F0 constant PINC_PINC \ Port C Input Pins bits
+ $07 constant PINC_PINC \ Port C Input Pins bits
+
+\ Interrupts
+&2 constant INT0Addr \ External Interrupt Request 0
+&4 constant INT1Addr \ External Interrupt Request 1
+&6 constant INT2Addr \ External Interrupt Request 2
+&8 constant INT3Addr \ External Interrupt Request 3
+&10 constant INT4Addr \ External Interrupt Request 4
+&12 constant INT5Addr \ External Interrupt Request 5
+&14 constant INT6Addr \ External Interrupt Request 6
+&16 constant INT7Addr \ External Interrupt Request 7
+&18 constant PCINT0Addr \ Pin Change Interrupt Request 0
+&20 constant PCINT1Addr \ Pin Change Interrupt Request 1
+&22 constant USB_GENAddr \ USB General Interrupt Request
+&24 constant USB_COMAddr \ USB Endpoint/Pipe Interrupt Communication Reque
+&26 constant WDTAddr \ Watchdog Time-out Interrupt
+&28 constant TIMER1_CAPTAddr \ Timer/Counter2 Capture Event
+&30 constant TIMER1_COMPAAddr \ Timer/Counter2 Compare Match B
+&32 constant TIMER1_COMPBAddr \ Timer/Counter2 Compare Match B
+&34 constant TIMER1_COMPCAddr \ Timer/Counter2 Compare Match C
+&36 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+&38 constant TIMER0_COMPAAddr \ Timer/Counter0 Compare Match A
+&40 constant TIMER0_COMPBAddr \ Timer/Counter0 Compare Match B
+&42 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
+&44 constant SPI__STCAddr \ SPI Serial Transfer Complete
+&46 constant USART1__RXAddr \ USART1, Rx Complete
+&48 constant USART1__UDREAddr \ USART1 Data register Empty
+&50 constant USART1__TXAddr \ USART1, Tx Complete
+&52 constant ANALOG_COMPAddr \ Analog Comparator
+&54 constant EE_READYAddr \ EEPROM Ready
+&56 constant SPM_READYAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/atmega8u2/device.asm b/amforth-6.5/avr8/devices/atmega8u2/device.asm
new file mode 100644
index 0000000..e8040e5
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega8u2/device.asm
@@ -0,0 +1,112 @@
+; Partname: ATmega8U2
+; generated automatically, do not edit
+
+.nolist
+ .include "m8U2def.inc"
+.list
+
+.equ ramstart = 256
+.equ CELLSIZE = 2
+.macro readflashcell
+ lsl zl
+ rol zh
+ lpm @0, Z+
+ lpm @1, Z+
+.endmacro
+.macro writeflashcell
+ lsl zl
+ rol zh
+.endmacro
+.set WANT_PORTB = 0
+.set WANT_PORTD = 0
+.set WANT_SPI = 0
+.set WANT_BOOT_LOAD = 0
+.set WANT_EEPROM = 0
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_PLL = 0
+.set WANT_USB_DEVICE = 0
+.set WANT_CPU = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_USART1 = 0
+.set WANT_WATCHDOG = 0
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_PORTC = 0
+.equ intvecsize = 1 ; please verify; flash size: 8192 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.org 2
+ rcall isr ; External Interrupt Request 0
+.org 4
+ rcall isr ; External Interrupt Request 1
+.org 6
+ rcall isr ; External Interrupt Request 2
+.org 8
+ rcall isr ; External Interrupt Request 3
+.org 10
+ rcall isr ; External Interrupt Request 4
+.org 12
+ rcall isr ; External Interrupt Request 5
+.org 14
+ rcall isr ; External Interrupt Request 6
+.org 16
+ rcall isr ; External Interrupt Request 7
+.org 18
+ rcall isr ; Pin Change Interrupt Request 0
+.org 20
+ rcall isr ; Pin Change Interrupt Request 1
+.org 22
+ rcall isr ; USB General Interrupt Request
+.org 24
+ rcall isr ; USB Endpoint/Pipe Interrupt Communication Request
+.org 26
+ rcall isr ; Watchdog Time-out Interrupt
+.org 28
+ rcall isr ; Timer/Counter2 Capture Event
+.org 30
+ rcall isr ; Timer/Counter2 Compare Match B
+.org 32
+ rcall isr ; Timer/Counter2 Compare Match B
+.org 34
+ rcall isr ; Timer/Counter2 Compare Match C
+.org 36
+ rcall isr ; Timer/Counter1 Overflow
+.org 38
+ rcall isr ; Timer/Counter0 Compare Match A
+.org 40
+ rcall isr ; Timer/Counter0 Compare Match B
+.org 42
+ rcall isr ; Timer/Counter0 Overflow
+.org 44
+ rcall isr ; SPI Serial Transfer Complete
+.org 46
+ rcall isr ; USART1, Rx Complete
+.org 48
+ rcall isr ; USART1 Data register Empty
+.org 50
+ rcall isr ; USART1, Tx Complete
+.org 52
+ rcall isr ; Analog Comparator
+.org 54
+ rcall isr ; EEPROM Ready
+.org 56
+ rcall isr ; Store Program Memory Read
+.equ INTVECTORS = 29
+.nooverlap
+
+; compatability layer (maybe empty)
+
+; controller data area, environment query mcu-info
+mcu_info:
+mcu_ramsize:
+ .dw 512
+mcu_eepromsize:
+ .dw 512
+mcu_maxdp:
+ .dw 4096
+mcu_numints:
+ .dw 29
+mcu_name:
+ .dw 9
+ .db "ATmega8U2",0
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega8u2/device.inc b/amforth-6.5/avr8/devices/atmega8u2/device.inc
new file mode 100644
index 0000000..bee0007
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega8u2/device.inc
@@ -0,0 +1,1128 @@
+; Partname: ATmega8U2
+; generated automatically, no not edit
+
+.if WANT_PORTB == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw 37
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw 36
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw 35
+
+.endif
+.if WANT_PORTD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw 43
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw 42
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw 41
+
+.endif
+.if WANT_SPI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR:
+ .dw $ff04
+ .db "SPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR
+XT_SPCR:
+ .dw PFA_DOVARIABLE
+PFA_SPCR:
+ .dw 76
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR:
+ .dw $ff04
+ .db "SPSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR
+XT_SPSR:
+ .dw PFA_DOVARIABLE
+PFA_SPSR:
+ .dw 77
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR:
+ .dw $ff04
+ .db "SPDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR
+XT_SPDR:
+ .dw PFA_DOVARIABLE
+PFA_SPDR:
+ .dw 78
+
+.endif
+.if WANT_BOOT_LOAD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control Register
+VE_SPMCSR:
+ .dw $ff06
+ .db "SPMCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCSR
+XT_SPMCSR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCSR:
+ .dw 87
+
+.endif
+.if WANT_EEPROM == 1
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Address Register Low Bytes
+VE_EEAR:
+ .dw $ff04
+ .db "EEAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEAR
+XT_EEAR:
+ .dw PFA_DOVARIABLE
+PFA_EEAR:
+ .dw 65
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw 64
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw 63
+
+.endif
+.if WANT_TIMER_COUNTER_0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0B:
+ .dw $ff05
+ .db "OCR0B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0B
+XT_OCR0B:
+ .dw PFA_DOVARIABLE
+PFA_OCR0B:
+ .dw 72
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0A:
+ .dw $ff05
+ .db "OCR0A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0A
+XT_OCR0A:
+ .dw PFA_DOVARIABLE
+PFA_OCR0A:
+ .dw 71
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw 70
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register B
+VE_TCCR0B:
+ .dw $ff06
+ .db "TCCR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0B
+XT_TCCR0B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0B:
+ .dw 69
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register A
+VE_TCCR0A:
+ .dw $ff06
+ .db "TCCR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0A
+XT_TCCR0A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0A:
+ .dw 68
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Mask Register
+VE_TIMSK0:
+ .dw $ff06
+ .db "TIMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK0
+XT_TIMSK0:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK0:
+ .dw 110
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Flag register
+VE_TIFR0:
+ .dw $ff05
+ .db "TIFR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR0
+XT_TIFR0:
+ .dw PFA_DOVARIABLE
+PFA_TIFR0:
+ .dw 53
+; ( -- addr ) System Constant
+; R( -- )
+; General Timer/Counter Control Register
+VE_GTCCR:
+ .dw $ff05
+ .db "GTCCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GTCCR
+XT_GTCCR:
+ .dw PFA_DOVARIABLE
+PFA_GTCCR:
+ .dw 67
+
+.endif
+.if WANT_TIMER_COUNTER_1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw 128
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw 129
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter 1 Control Register C
+VE_TCCR1C:
+ .dw $ff06
+ .db "TCCR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1C
+XT_TCCR1C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1C:
+ .dw 130
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Bytes
+VE_TCNT1:
+ .dw $ff05
+ .db "TCNT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1
+XT_TCNT1:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1:
+ .dw 132
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register A Bytes
+VE_OCR1A:
+ .dw $ff05
+ .db "OCR1A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1A
+XT_OCR1A:
+ .dw PFA_DOVARIABLE
+PFA_OCR1A:
+ .dw 136
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register B Bytes
+VE_OCR1B:
+ .dw $ff05
+ .db "OCR1B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1B
+XT_OCR1B:
+ .dw PFA_DOVARIABLE
+PFA_OCR1B:
+ .dw 138
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register C Bytes
+VE_OCR1C:
+ .dw $ff05
+ .db "OCR1C",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1C
+XT_OCR1C:
+ .dw PFA_DOVARIABLE
+PFA_OCR1C:
+ .dw 140
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Bytes
+VE_ICR1:
+ .dw $ff04
+ .db "ICR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1
+XT_ICR1:
+ .dw PFA_DOVARIABLE
+PFA_ICR1:
+ .dw 134
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Mask Register
+VE_TIMSK1:
+ .dw $ff06
+ .db "TIMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK1
+XT_TIMSK1:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK1:
+ .dw 111
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Flag register
+VE_TIFR1:
+ .dw $ff05
+ .db "TIFR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR1
+XT_TIFR1:
+ .dw PFA_DOVARIABLE
+PFA_TIFR1:
+ .dw 54
+
+.endif
+.if WANT_PLL == 1
+; ( -- addr ) System Constant
+; R( -- )
+; PLL Status and Control register
+VE_PLLCSR:
+ .dw $ff06
+ .db "PLLCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PLLCSR
+XT_PLLCSR:
+ .dw PFA_DOVARIABLE
+PFA_PLLCSR:
+ .dw 73
+
+.endif
+.if WANT_USB_DEVICE == 1
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UEINT:
+ .dw $ff05
+ .db "UEINT",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UEINT
+XT_UEINT:
+ .dw PFA_DOVARIABLE
+PFA_UEINT:
+ .dw 244
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UEBCLX:
+ .dw $ff06
+ .db "UEBCLX"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UEBCLX
+XT_UEBCLX:
+ .dw PFA_DOVARIABLE
+PFA_UEBCLX:
+ .dw 242
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UEDATX:
+ .dw $ff06
+ .db "UEDATX"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UEDATX
+XT_UEDATX:
+ .dw PFA_DOVARIABLE
+PFA_UEDATX:
+ .dw 241
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UEIENX:
+ .dw $ff06
+ .db "UEIENX"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UEIENX
+XT_UEIENX:
+ .dw PFA_DOVARIABLE
+PFA_UEIENX:
+ .dw 240
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UESTA1X:
+ .dw $ff07
+ .db "UESTA1X",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UESTA1X
+XT_UESTA1X:
+ .dw PFA_DOVARIABLE
+PFA_UESTA1X:
+ .dw 239
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UESTA0X:
+ .dw $ff07
+ .db "UESTA0X",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UESTA0X
+XT_UESTA0X:
+ .dw PFA_DOVARIABLE
+PFA_UESTA0X:
+ .dw 238
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UECFG1X:
+ .dw $ff07
+ .db "UECFG1X",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UECFG1X
+XT_UECFG1X:
+ .dw PFA_DOVARIABLE
+PFA_UECFG1X:
+ .dw 237
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UECFG0X:
+ .dw $ff07
+ .db "UECFG0X",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UECFG0X
+XT_UECFG0X:
+ .dw PFA_DOVARIABLE
+PFA_UECFG0X:
+ .dw 236
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UECONX:
+ .dw $ff06
+ .db "UECONX"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UECONX
+XT_UECONX:
+ .dw PFA_DOVARIABLE
+PFA_UECONX:
+ .dw 235
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UERST:
+ .dw $ff05
+ .db "UERST",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UERST
+XT_UERST:
+ .dw PFA_DOVARIABLE
+PFA_UERST:
+ .dw 234
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UENUM:
+ .dw $ff05
+ .db "UENUM",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UENUM
+XT_UENUM:
+ .dw PFA_DOVARIABLE
+PFA_UENUM:
+ .dw 233
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UEINTX:
+ .dw $ff06
+ .db "UEINTX"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UEINTX
+XT_UEINTX:
+ .dw PFA_DOVARIABLE
+PFA_UEINTX:
+ .dw 232
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UDMFN:
+ .dw $ff05
+ .db "UDMFN",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDMFN
+XT_UDMFN:
+ .dw PFA_DOVARIABLE
+PFA_UDMFN:
+ .dw 230
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UDFNUM:
+ .dw $ff06
+ .db "UDFNUM"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDFNUM
+XT_UDFNUM:
+ .dw PFA_DOVARIABLE
+PFA_UDFNUM:
+ .dw 228
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UDADDR:
+ .dw $ff06
+ .db "UDADDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDADDR
+XT_UDADDR:
+ .dw PFA_DOVARIABLE
+PFA_UDADDR:
+ .dw 227
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UDIEN:
+ .dw $ff05
+ .db "UDIEN",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDIEN
+XT_UDIEN:
+ .dw PFA_DOVARIABLE
+PFA_UDIEN:
+ .dw 226
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UDINT:
+ .dw $ff05
+ .db "UDINT",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDINT
+XT_UDINT:
+ .dw PFA_DOVARIABLE
+PFA_UDINT:
+ .dw 225
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_UDCON:
+ .dw $ff05
+ .db "UDCON",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDCON
+XT_UDCON:
+ .dw PFA_DOVARIABLE
+PFA_UDCON:
+ .dw 224
+; ( -- addr ) System Constant
+; R( -- )
+; USB General Control Register
+VE_USBCON:
+ .dw $ff06
+ .db "USBCON"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USBCON
+XT_USBCON:
+ .dw PFA_DOVARIABLE
+PFA_USBCON:
+ .dw 216
+; ( -- addr ) System Constant
+; R( -- )
+; Regulator Control Register
+VE_REGCR:
+ .dw $ff05
+ .db "REGCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_REGCR
+XT_REGCR:
+ .dw PFA_DOVARIABLE
+PFA_REGCR:
+ .dw 99
+
+.endif
+.if WANT_CPU == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw 95
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer
+VE_SP:
+ .dw $ff02
+ .db "SP"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SP
+XT_SP:
+ .dw PFA_DOVARIABLE
+PFA_SP:
+ .dw 93
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw 85
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Status Register
+VE_MCUSR:
+ .dw $ff05
+ .db "MCUSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUSR
+XT_MCUSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUSR:
+ .dw 84
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Calibration Value
+VE_OSCCAL:
+ .dw $ff06
+ .db "OSCCAL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSCCAL
+XT_OSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_OSCCAL:
+ .dw 102
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_CLKPR:
+ .dw $ff05
+ .db "CLKPR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKPR
+XT_CLKPR:
+ .dw PFA_DOVARIABLE
+PFA_CLKPR:
+ .dw 97
+; ( -- addr ) System Constant
+; R( -- )
+; Sleep Mode Control Register
+VE_SMCR:
+ .dw $ff04
+ .db "SMCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SMCR
+XT_SMCR:
+ .dw PFA_DOVARIABLE
+PFA_SMCR:
+ .dw 83
+; ( -- addr ) System Constant
+; R( -- )
+; Extended Indirect Register
+VE_EIND:
+ .dw $ff04
+ .db "EIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIND
+XT_EIND:
+ .dw PFA_DOVARIABLE
+PFA_EIND:
+ .dw 92
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 2
+VE_GPIOR2:
+ .dw $ff06
+ .db "GPIOR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR2
+XT_GPIOR2:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR2:
+ .dw 75
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 1
+VE_GPIOR1:
+ .dw $ff06
+ .db "GPIOR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR1
+XT_GPIOR1:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR1:
+ .dw 74
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 0
+VE_GPIOR0:
+ .dw $ff06
+ .db "GPIOR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR0
+XT_GPIOR0:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR0:
+ .dw 62
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register1
+VE_PRR1:
+ .dw $ff04
+ .db "PRR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR1
+XT_PRR1:
+ .dw PFA_DOVARIABLE
+PFA_PRR1:
+ .dw 101
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register0
+VE_PRR0:
+ .dw $ff04
+ .db "PRR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR0
+XT_PRR0:
+ .dw PFA_DOVARIABLE
+PFA_PRR0:
+ .dw 100
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_CLKSTA:
+ .dw $ff06
+ .db "CLKSTA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKSTA
+XT_CLKSTA:
+ .dw PFA_DOVARIABLE
+PFA_CLKSTA:
+ .dw 210
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_CLKSEL1:
+ .dw $ff07
+ .db "CLKSEL1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKSEL1
+XT_CLKSEL1:
+ .dw PFA_DOVARIABLE
+PFA_CLKSEL1:
+ .dw 209
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_CLKSEL0:
+ .dw $ff07
+ .db "CLKSEL0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKSEL0
+XT_CLKSEL0:
+ .dw PFA_DOVARIABLE
+PFA_CLKSEL0:
+ .dw 208
+; ( -- addr ) System Constant
+; R( -- )
+; debugWire communication register
+VE_DWDR:
+ .dw $ff04
+ .db "DWDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DWDR
+XT_DWDR:
+ .dw PFA_DOVARIABLE
+PFA_DWDR:
+ .dw 81
+
+.endif
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register A
+VE_EICRA:
+ .dw $ff05
+ .db "EICRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRA
+XT_EICRA:
+ .dw PFA_DOVARIABLE
+PFA_EICRA:
+ .dw 105
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register B
+VE_EICRB:
+ .dw $ff05
+ .db "EICRB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRB
+XT_EICRB:
+ .dw PFA_DOVARIABLE
+PFA_EICRB:
+ .dw 106
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Mask Register
+VE_EIMSK:
+ .dw $ff05
+ .db "EIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIMSK
+XT_EIMSK:
+ .dw PFA_DOVARIABLE
+PFA_EIMSK:
+ .dw 61
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Flag Register
+VE_EIFR:
+ .dw $ff04
+ .db "EIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIFR
+XT_EIFR:
+ .dw PFA_DOVARIABLE
+PFA_EIFR:
+ .dw 60
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 0
+VE_PCMSK0:
+ .dw $ff06
+ .db "PCMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK0
+XT_PCMSK0:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK0:
+ .dw 107
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 1
+VE_PCMSK1:
+ .dw $ff06
+ .db "PCMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK1
+XT_PCMSK1:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK1:
+ .dw 108
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Interrupt Flag Register
+VE_PCIFR:
+ .dw $ff05
+ .db "PCIFR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCIFR
+XT_PCIFR:
+ .dw PFA_DOVARIABLE
+PFA_PCIFR:
+ .dw 59
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Interrupt Control Register
+VE_PCICR:
+ .dw $ff05
+ .db "PCICR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCICR
+XT_PCICR:
+ .dw PFA_DOVARIABLE
+PFA_PCICR:
+ .dw 104
+
+.endif
+.if WANT_USART1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR1:
+ .dw $ff04
+ .db "UDR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR1
+XT_UDR1:
+ .dw PFA_DOVARIABLE
+PFA_UDR1:
+ .dw 206
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR1A:
+ .dw $ff06
+ .db "UCSR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1A
+XT_UCSR1A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1A:
+ .dw 200
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR1B:
+ .dw $ff06
+ .db "UCSR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1B
+XT_UCSR1B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1B:
+ .dw 201
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR1C:
+ .dw $ff06
+ .db "UCSR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1C
+XT_UCSR1C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1C:
+ .dw 202
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register D
+VE_UCSR1D:
+ .dw $ff06
+ .db "UCSR1D"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1D
+XT_UCSR1D:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1D:
+ .dw 203
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Bytes
+VE_UBRR1:
+ .dw $ff05
+ .db "UBRR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR1
+XT_UBRR1:
+ .dw PFA_DOVARIABLE
+PFA_UBRR1:
+ .dw 204
+
+.endif
+.if WANT_WATCHDOG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCSR:
+ .dw $ff06
+ .db "WDTCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCSR
+XT_WDTCSR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCSR:
+ .dw 96
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Clock Divider
+VE_WDTCKD:
+ .dw $ff06
+ .db "WDTCKD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCKD
+XT_WDTCKD:
+ .dw PFA_DOVARIABLE
+PFA_WDTCKD:
+ .dw 98
+
+.endif
+.if WANT_ANALOG_COMPARATOR == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Control And Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw 80
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_DIDR1:
+ .dw $ff05
+ .db "DIDR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR1
+XT_DIDR1:
+ .dw PFA_DOVARIABLE
+PFA_DIDR1:
+ .dw 127
+
+.endif
+.if WANT_PORTC == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Register
+VE_PORTC:
+ .dw $ff05
+ .db "PORTC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTC
+XT_PORTC:
+ .dw PFA_DOVARIABLE
+PFA_PORTC:
+ .dw 40
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Direction Register
+VE_DDRC:
+ .dw $ff04
+ .db "DDRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRC
+XT_DDRC:
+ .dw PFA_DOVARIABLE
+PFA_DDRC:
+ .dw 39
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Input Pins
+VE_PINC:
+ .dw $ff04
+ .db "PINC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINC
+XT_PINC:
+ .dw PFA_DOVARIABLE
+PFA_PINC:
+ .dw 38
+
+.endif
diff --git a/amforth-6.5/avr8/devices/atmega8u2/device.py b/amforth-6.5/avr8/devices/atmega8u2/device.py
new file mode 100644
index 0000000..34d5823
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega8u2/device.py
@@ -0,0 +1,341 @@
+# Partname: ATmega8U2
+# generated automatically, do not edit
+MCUREGS = {
+ 'PORTB': '&37',
+ 'DDRB': '&36',
+ 'PINB': '&35',
+ 'PORTD': '&43',
+ 'DDRD': '&42',
+ 'PIND': '&41',
+ 'SPCR': '&76',
+ 'SPCR_SPIE': '$80',
+ 'SPCR_SPE': '$40',
+ 'SPCR_DORD': '$20',
+ 'SPCR_MSTR': '$10',
+ 'SPCR_CPOL': '$08',
+ 'SPCR_CPHA': '$04',
+ 'SPCR_SPR': '$03',
+ 'SPSR': '&77',
+ 'SPSR_SPIF': '$80',
+ 'SPSR_WCOL': '$40',
+ 'SPSR_SPI2X': '$01',
+ 'SPDR': '&78',
+ 'SPMCSR': '&87',
+ 'SPMCSR_SPMIE': '$80',
+ 'SPMCSR_RWWSB': '$40',
+ 'SPMCSR_SIGRD': '$20',
+ 'SPMCSR_RWWSRE': '$10',
+ 'SPMCSR_BLBSET': '$08',
+ 'SPMCSR_PGWRT': '$04',
+ 'SPMCSR_PGERS': '$02',
+ 'SPMCSR_SPMEN': '$01',
+ 'EEAR': '&65',
+ 'EEDR': '&64',
+ 'EECR': '&63',
+ 'EECR_EEPM': '$30',
+ 'EECR_EERIE': '$08',
+ 'EECR_EEMPE': '$04',
+ 'EECR_EEPE': '$02',
+ 'EECR_EERE': '$01',
+ 'OCR0B': '&72',
+ 'OCR0A': '&71',
+ 'TCNT0': '&70',
+ 'TCCR0B': '&69',
+ 'TCCR0B_FOC0A': '$80',
+ 'TCCR0B_FOC0B': '$40',
+ 'TCCR0B_WGM02': '$08',
+ 'TCCR0B_CS0': '$07',
+ 'TCCR0A': '&68',
+ 'TCCR0A_COM0A': '$C0',
+ 'TCCR0A_COM0B': '$30',
+ 'TCCR0A_WGM0': '$03',
+ 'TIMSK0': '&110',
+ 'TIMSK0_OCIE0B': '$04',
+ 'TIMSK0_OCIE0A': '$02',
+ 'TIMSK0_TOIE0': '$01',
+ 'TIFR0': '&53',
+ 'TIFR0_OCF0B': '$04',
+ 'TIFR0_OCF0A': '$02',
+ 'TIFR0_TOV0': '$01',
+ 'GTCCR': '&67',
+ 'GTCCR_TSM': '$80',
+ 'GTCCR_PSRSYNC': '$01',
+ 'TCCR1A': '&128',
+ 'TCCR1A_COM1A': '$C0',
+ 'TCCR1A_COM1B': '$30',
+ 'TCCR1A_COM1C': '$0C',
+ 'TCCR1A_WGM1': '$03',
+ 'TCCR1B': '&129',
+ 'TCCR1B_ICNC1': '$80',
+ 'TCCR1B_ICES1': '$40',
+ 'TCCR1B_WGM1': '$18',
+ 'TCCR1B_CS1': '$07',
+ 'TCCR1C': '&130',
+ 'TCCR1C_FOC1A': '$80',
+ 'TCCR1C_FOC1B': '$40',
+ 'TCCR1C_FOC1C': '$20',
+ 'TCNT1': '&132',
+ 'OCR1A': '&136',
+ 'OCR1B': '&138',
+ 'OCR1C': '&140',
+ 'ICR1': '&134',
+ 'TIMSK1': '&111',
+ 'TIMSK1_ICIE1': '$20',
+ 'TIMSK1_OCIE1C': '$08',
+ 'TIMSK1_OCIE1B': '$04',
+ 'TIMSK1_OCIE1A': '$02',
+ 'TIMSK1_TOIE1': '$01',
+ 'TIFR1': '&54',
+ 'TIFR1_ICF1': '$20',
+ 'TIFR1_OCF1C': '$08',
+ 'TIFR1_OCF1B': '$04',
+ 'TIFR1_OCF1A': '$02',
+ 'TIFR1_TOV1': '$01',
+ 'PLLCSR': '&73',
+ 'PLLCSR_PLLP': '$1C',
+ 'PLLCSR_PLLE': '$02',
+ 'PLLCSR_PLOCK': '$01',
+ 'UEINT': '&244',
+ 'UEBCLX': '&242',
+ 'UEDATX': '&241',
+ 'UEIENX': '&240',
+ 'UEIENX_FLERRE': '$80',
+ 'UEIENX_NAKINE': '$40',
+ 'UEIENX_NAKOUTE': '$10',
+ 'UEIENX_RXSTPE': '$08',
+ 'UEIENX_RXOUTE': '$04',
+ 'UEIENX_STALLEDE': '$02',
+ 'UEIENX_TXINE': '$01',
+ 'UESTA1X': '&239',
+ 'UESTA1X_CTRLDIR': '$04',
+ 'UESTA1X_CURRBK': '$03',
+ 'UESTA0X': '&238',
+ 'UESTA0X_CFGOK': '$80',
+ 'UESTA0X_OVERFI': '$40',
+ 'UESTA0X_UNDERFI': '$20',
+ 'UESTA0X_DTSEQ': '$0C',
+ 'UESTA0X_NBUSYBK': '$03',
+ 'UECFG1X': '&237',
+ 'UECFG1X_EPSIZE': '$70',
+ 'UECFG1X_EPBK': '$0C',
+ 'UECFG1X_ALLOC': '$02',
+ 'UECFG0X': '&236',
+ 'UECFG0X_EPTYPE': '$C0',
+ 'UECFG0X_EPDIR': '$01',
+ 'UECONX': '&235',
+ 'UECONX_STALLRQ': '$20',
+ 'UECONX_STALLRQC': '$10',
+ 'UECONX_RSTDT': '$08',
+ 'UECONX_EPEN': '$01',
+ 'UERST': '&234',
+ 'UERST_EPRST': '$1F',
+ 'UENUM': '&233',
+ 'UEINTX': '&232',
+ 'UEINTX_FIFOCON': '$80',
+ 'UEINTX_NAKINI': '$40',
+ 'UEINTX_RWAL': '$20',
+ 'UEINTX_NAKOUTI': '$10',
+ 'UEINTX_RXSTPI': '$08',
+ 'UEINTX_RXOUTI': '$04',
+ 'UEINTX_STALLEDI': '$02',
+ 'UEINTX_TXINI': '$01',
+ 'UDMFN': '&230',
+ 'UDMFN_FNCERR': '$10',
+ 'UDFNUM': '&228',
+ 'UDADDR': '&227',
+ 'UDADDR_ADDEN': '$80',
+ 'UDADDR_UADD': '$7F',
+ 'UDIEN': '&226',
+ 'UDIEN_UPRSME': '$40',
+ 'UDIEN_EORSME': '$20',
+ 'UDIEN_WAKEUPE': '$10',
+ 'UDIEN_EORSTE': '$08',
+ 'UDIEN_SOFE': '$04',
+ 'UDIEN_SUSPE': '$01',
+ 'UDINT': '&225',
+ 'UDINT_UPRSMI': '$40',
+ 'UDINT_EORSMI': '$20',
+ 'UDINT_WAKEUPI': '$10',
+ 'UDINT_EORSTI': '$08',
+ 'UDINT_SOFI': '$04',
+ 'UDINT_SUSPI': '$01',
+ 'UDCON': '&224',
+ 'UDCON_RSTCPU': '$04',
+ 'UDCON_RMWKUP': '$02',
+ 'UDCON_DETACH': '$01',
+ 'USBCON': '&216',
+ 'USBCON_USBE': '$80',
+ 'USBCON_FRZCLK': '$20',
+ 'REGCR': '&99',
+ 'REGCR_REGDIS': '$01',
+ 'SREG': '&95',
+ 'SREG_I': '$80',
+ 'SREG_T': '$40',
+ 'SREG_H': '$20',
+ 'SREG_S': '$10',
+ 'SREG_V': '$08',
+ 'SREG_N': '$04',
+ 'SREG_Z': '$02',
+ 'SREG_C': '$01',
+ 'SP': '&93',
+ 'MCUCR': '&85',
+ 'MCUCR_PUD': '$10',
+ 'MCUCR_IVSEL': '$02',
+ 'MCUCR_IVCE': '$01',
+ 'MCUSR': '&84',
+ 'MCUSR_USBRF': '$20',
+ 'MCUSR_WDRF': '$08',
+ 'MCUSR_BORF': '$04',
+ 'MCUSR_EXTRF': '$02',
+ 'MCUSR_PORF': '$01',
+ 'OSCCAL': '&102',
+ 'CLKPR': '&97',
+ 'CLKPR_CLKPCE': '$80',
+ 'CLKPR_CLKPS': '$0F',
+ 'SMCR': '&83',
+ 'SMCR_SM': '$0E',
+ 'SMCR_SE': '$01',
+ 'EIND': '&92',
+ 'GPIOR2': '&75',
+ 'GPIOR2_GPIOR': '$FF',
+ 'GPIOR1': '&74',
+ 'GPIOR1_GPIOR': '$FF',
+ 'GPIOR0': '&62',
+ 'GPIOR0_GPIOR07': '$80',
+ 'GPIOR0_GPIOR06': '$40',
+ 'GPIOR0_GPIOR05': '$20',
+ 'GPIOR0_GPIOR04': '$10',
+ 'GPIOR0_GPIOR03': '$08',
+ 'GPIOR0_GPIOR02': '$04',
+ 'GPIOR0_GPIOR01': '$02',
+ 'GPIOR0_GPIOR00': '$01',
+ 'PRR1': '&101',
+ 'PRR1_PRUSB': '$80',
+ 'PRR1_PRUSART1': '$01',
+ 'PRR0': '&100',
+ 'PRR0_PRTIM0': '$20',
+ 'PRR0_PRTIM1': '$08',
+ 'PRR0_PRSPI': '$04',
+ 'CLKSTA': '&210',
+ 'CLKSTA_RCON': '$02',
+ 'CLKSTA_EXTON': '$01',
+ 'CLKSEL1': '&209',
+ 'CLKSEL1_RCCKSEL': '$F0',
+ 'CLKSEL1_EXCKSEL': '$0F',
+ 'CLKSEL0': '&208',
+ 'CLKSEL0_RCSUT': '$C0',
+ 'CLKSEL0_EXSUT': '$30',
+ 'CLKSEL0_RCE': '$08',
+ 'CLKSEL0_EXTE': '$04',
+ 'CLKSEL0_CLKS': '$01',
+ 'DWDR': '&81',
+ 'EICRA': '&105',
+ 'EICRA_ISC3': '$C0',
+ 'EICRA_ISC2': '$30',
+ 'EICRA_ISC1': '$0C',
+ 'EICRA_ISC0': '$03',
+ 'EICRB': '&106',
+ 'EICRB_ISC7': '$C0',
+ 'EICRB_ISC6': '$30',
+ 'EICRB_ISC5': '$0C',
+ 'EICRB_ISC4': '$03',
+ 'EIMSK': '&61',
+ 'EIMSK_INT': '$FF',
+ 'EIFR': '&60',
+ 'EIFR_INTF': '$FF',
+ 'PCMSK0': '&107',
+ 'PCMSK0_PCINT': '$FF',
+ 'PCMSK1': '&108',
+ 'PCMSK1_PCINT': '$1F',
+ 'PCIFR': '&59',
+ 'PCIFR_PCIF': '$03',
+ 'PCICR': '&104',
+ 'PCICR_PCIE': '$03',
+ 'UDR1': '&206',
+ 'UCSR1A': '&200',
+ 'UCSR1A_RXC1': '$80',
+ 'UCSR1A_TXC1': '$40',
+ 'UCSR1A_UDRE1': '$20',
+ 'UCSR1A_FE1': '$10',
+ 'UCSR1A_DOR1': '$08',
+ 'UCSR1A_UPE1': '$04',
+ 'UCSR1A_U2X1': '$02',
+ 'UCSR1A_MPCM1': '$01',
+ 'UCSR1B': '&201',
+ 'UCSR1B_RXCIE1': '$80',
+ 'UCSR1B_TXCIE1': '$40',
+ 'UCSR1B_UDRIE1': '$20',
+ 'UCSR1B_RXEN1': '$10',
+ 'UCSR1B_TXEN1': '$08',
+ 'UCSR1B_UCSZ12': '$04',
+ 'UCSR1B_RXB81': '$02',
+ 'UCSR1B_TXB81': '$01',
+ 'UCSR1C': '&202',
+ 'UCSR1C_UMSEL1': '$C0',
+ 'UCSR1C_UPM1': '$30',
+ 'UCSR1C_USBS1': '$08',
+ 'UCSR1C_UCSZ1': '$06',
+ 'UCSR1C_UCPOL1': '$01',
+ 'UCSR1D': '&203',
+ 'UCSR1D_CTSEN': '$02',
+ 'UCSR1D_RTSEN': '$01',
+ 'UBRR1': '&204',
+ 'WDTCSR': '&96',
+ 'WDTCSR_WDIF': '$80',
+ 'WDTCSR_WDIE': '$40',
+ 'WDTCSR_WDP': '$27',
+ 'WDTCSR_WDCE': '$10',
+ 'WDTCSR_WDE': '$08',
+ 'WDTCKD': '&98',
+ 'WDTCKD_WDEWIF': '$08',
+ 'WDTCKD_WDEWIE': '$04',
+ 'WDTCKD_WCLKD': '$03',
+ 'ACSR': '&80',
+ 'ACSR_ACD': '$80',
+ 'ACSR_ACBG': '$40',
+ 'ACSR_ACO': '$20',
+ 'ACSR_ACI': '$10',
+ 'ACSR_ACIE': '$08',
+ 'ACSR_ACIC': '$04',
+ 'ACSR_ACIS': '$03',
+ 'DIDR1': '&127',
+ 'DIDR1_AIN1D': '$02',
+ 'DIDR1_AIN0D': '$01',
+ 'PORTC': '&40',
+ 'PORTC_PORTC': '$F0',
+ 'PORTC_PORTC': '$07',
+ 'DDRC': '&39',
+ 'DDRC_DDC': '$F0',
+ 'DDRC_DDC': '$07',
+ 'PINC': '&38',
+ 'PINC_PINC': '$F0',
+ 'PINC_PINC': '$07',
+ 'INT0Addr': '2',
+ 'INT1Addr': '4',
+ 'INT2Addr': '6',
+ 'INT3Addr': '8',
+ 'INT4Addr': '10',
+ 'INT5Addr': '12',
+ 'INT6Addr': '14',
+ 'INT7Addr': '16',
+ 'PCINT0Addr': '18',
+ 'PCINT1Addr': '20',
+ 'USB_GENAddr': '22',
+ 'USB_COMAddr': '24',
+ 'WDTAddr': '26',
+ 'TIMER1_CAPTAddr': '28',
+ 'TIMER1_COMPAAddr': '30',
+ 'TIMER1_COMPBAddr': '32',
+ 'TIMER1_COMPCAddr': '34',
+ 'TIMER1_OVFAddr': '36',
+ 'TIMER0_COMPAAddr': '38',
+ 'TIMER0_COMPBAddr': '40',
+ 'TIMER0_OVFAddr': '42',
+ 'SPI__STCAddr': '44',
+ 'USART1__RXAddr': '46',
+ 'USART1__UDREAddr': '48',
+ 'USART1__TXAddr': '50',
+ 'ANALOG_COMPAddr': '52',
+ 'EE_READYAddr': '54',
+ 'SPM_READYAddr': '56'
+} \ No newline at end of file
diff --git a/amforth-6.5/avr8/devices/atmega8u2/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega8u2/words/no-jtag.asm
new file mode 100644
index 0000000..352a4bb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega8u2/words/no-jtag.asm
@@ -0,0 +1,14 @@
+; ( -- )
+; ( -- )
+; MCU
+; disable jtag at runtime
+VE_NOJTAG:
+ .dw $FF05
+ .db "-jtag",0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOJTAG
+XT_NOJTAG:
+ .dw PFA_NOJTAG
+PFA_NOJTAG:
+
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega8u2/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega8u2/words/no-wdt.asm
new file mode 100644
index 0000000..ff6ddd1
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega8u2/words/no-wdt.asm
@@ -0,0 +1,34 @@
+; ( -- )
+; MCU
+; disable watch dog timer at runtime
+VE_NOWDT:
+ .dw $ff04
+ .db "-wdt"
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOWDT
+XT_NOWDT:
+ .dw PFA_NOWDT
+PFA_NOWDT:
+
+ in temp1,SREG
+ push temp1
+ ; Turn always off global interrupt.
+ cli
+ ; Reset Watchdog Timer
+ wdr
+ ; Clear WDRF in MCUSR
+ in temp1, MCUSR
+ andi temp1, (0xff & (0<<WDRF))
+ out MCUSR, temp1
+ ; Write logical one to WDCE and WDE
+ ; Keep old prescaler setting to prevent unintentional time-out
+ in_ temp1, WDTCSR
+ ori temp1, (1<<WDCE) | (1<<WDE)
+ out_ WDTCSR, temp1
+ ; Turn off WDT
+ ldi temp1, (0<<WDE)
+ out_ WDTCSR, temp1
+ ; restore status register
+ pop temp1
+ out SREG,temp1
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega8u2/words/sleep.asm b/amforth-6.5/avr8/devices/atmega8u2/words/sleep.asm
new file mode 100644
index 0000000..256249c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega8u2/words/sleep.asm
@@ -0,0 +1,19 @@
+; ( mode -- )
+; MCU
+; put the controller into the specified sleep mode
+VE_SLEEP:
+ .dw $ff05
+ .db "sleep", 0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_SLEEP
+XT_SLEEP:
+ .dw PFA_SLEEP
+PFA_SLEEP:
+ andi tosl, 7 ; leave only legal mode bits
+ lsl tosl ; move to correct location (bits 3-1)
+ ori tosl, 1 ; set the SE bit
+ out_ SMCR, tosl ; set the sleep config
+ sleep ; nighty-night
+ out_ SMCR, zerol ; 0 protects against accidental sleeps
+ loadtos ; pop argument from stack
+ jmp_ DO_NEXT