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-rw-r--r--amforth-6.5/avr8/devices/at90pwm2b/at90pwm2b.frt423
-rw-r--r--amforth-6.5/avr8/devices/at90pwm2b/device.asm123
-rw-r--r--amforth-6.5/avr8/devices/at90pwm2b/device.inc1281
-rw-r--r--amforth-6.5/avr8/devices/at90pwm2b/device.py448
-rw-r--r--amforth-6.5/avr8/devices/at90pwm2b/words/no-jtag.asm14
-rw-r--r--amforth-6.5/avr8/devices/at90pwm2b/words/no-wdt.asm34
-rw-r--r--amforth-6.5/avr8/devices/at90pwm2b/words/sleep.asm19
7 files changed, 2342 insertions, 0 deletions
diff --git a/amforth-6.5/avr8/devices/at90pwm2b/at90pwm2b.frt b/amforth-6.5/avr8/devices/at90pwm2b/at90pwm2b.frt
new file mode 100644
index 0000000..30d6e54
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90pwm2b/at90pwm2b.frt
@@ -0,0 +1,423 @@
+\ Partname: AT90PWM2B
+\ generated automatically
+
+\ PORTB
+&37 constant PORTB \ Port B Data Register
+&36 constant DDRB \ Port B Data Direction Register
+&35 constant PINB \ Port B Input Pins
+\ PORTD
+&43 constant PORTD \ Port D Data Register
+&42 constant DDRD \ Port D Data Direction Register
+&41 constant PIND \ Port D Input Pins
+\ BOOT_LOAD
+&87 constant SPMCSR \ Store Program Memory Control Register
+ $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
+ $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
+ $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
+ $04 constant SPMCSR_PGWRT \ Page Write
+ $02 constant SPMCSR_PGERS \ Page Erase
+ $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
+\ EUSART
+&206 constant EUDR \ EUSART I/O Data Register
+&200 constant EUCSRA \ EUSART Control and Status Register A
+ $F0 constant EUCSRA_UTxS \ EUSART Control and Status Register A Bits
+ $0F constant EUCSRA_URxS \ EUSART Control and Status Register A Bits
+&201 constant EUCSRB \ EUSART Control Register B
+ $10 constant EUCSRB_EUSART \ EUSART Enable Bit
+ $08 constant EUCSRB_EUSBS \ EUSBS Enable Bit
+ $02 constant EUCSRB_EMCH \ Manchester Mode Bit
+ $01 constant EUCSRB_BODR \ Order Bit
+&202 constant EUCSRC \ EUSART Status Register C
+ $08 constant EUCSRC_FEM \ Frame Error Manchester Bit
+ $04 constant EUCSRC_F1617 \ F1617 Bit
+ $03 constant EUCSRC_STP \ Stop Bits
+&205 constant MUBRRH \ Manchester Receiver Baud Rate Register High Byte
+ $FF constant MUBRRH_MUBRR \ Manchester Receiver Baud Rate Register Bits
+&204 constant MUBRRL \ Manchester Receiver Baud Rate Register Low Byte
+ $FF constant MUBRRL_MUBRR \ Manchester Receiver Baud Rate Register Bits
+\ ANALOG_COMPARATOR
+&173 constant AC0CON \ Analog Comparator 0 Control Register
+ $80 constant AC0CON_AC0EN \ Analog Comparator 0 Enable Bit
+ $40 constant AC0CON_AC0IE \ Analog Comparator 0 Interrupt Enable Bit
+ $30 constant AC0CON_AC0IS \ Analog Comparator 0 Interrupt Select Bit
+ $07 constant AC0CON_AC0M \ Analog Comparator 0 Multiplexer Register
+&174 constant AC1CON \ Analog Comparator 1 Control Register
+ $80 constant AC1CON_AC1EN \ Analog Comparator 1 Enable Bit
+ $40 constant AC1CON_AC1IE \ Analog Comparator 1 Interrupt Enable Bit
+ $30 constant AC1CON_AC1IS \ Analog Comparator 1 Interrupt Select Bit
+ $08 constant AC1CON_AC1ICE \ Analog Comparator 1 Interrupt Capture Enable Bit
+ $07 constant AC1CON_AC1M \ Analog Comparator 1 Multiplexer Register
+&175 constant AC2CON \ Analog Comparator 2 Control Register
+ $80 constant AC2CON_AC2EN \ Analog Comparator 2 Enable Bit
+ $40 constant AC2CON_AC2IE \ Analog Comparator 2 Interrupt Enable Bit
+ $30 constant AC2CON_AC2IS \ Analog Comparator 2 Interrupt Select Bit
+ $07 constant AC2CON_AC2M \ Analog Comparator 2 Multiplexer Register
+&80 constant ACSR \ Analog Comparator Status Register
+ $80 constant ACSR_ACCKDIV \ Analog Comparator Clock Divider
+ $40 constant ACSR_AC2IF \ Analog Comparator 2 Interrupt Flag Bit
+ $20 constant ACSR_AC1IF \ Analog Comparator 1 Interrupt Flag Bit
+ $10 constant ACSR_AC0IF \ Analog Comparator 0 Interrupt Flag Bit
+ $04 constant ACSR_AC2O \ Analog Comparator 2 Output Bit
+ $02 constant ACSR_AC1O \ Analog Comparator 1 Output Bit
+ $01 constant ACSR_AC0O \ Analog Comparator 0 Output Bit
+\ DA_CONVERTER
+&172 constant DACH \ DAC Data Register High Byte
+ $FF constant DACH_DACH \ DAC Data Register High Byte Bits
+&171 constant DACL \ DAC Data Register Low Byte
+ $FF constant DACL_DACL \ DAC Data Register Low Byte Bits
+&170 constant DACON \ DAC Control Register
+ $80 constant DACON_DAATE \ DAC Auto Trigger Enable Bit
+ $70 constant DACON_DATS \ DAC Trigger Selection Bits
+ $04 constant DACON_DALA \ DAC Left Adjust
+ $01 constant DACON_DAEN \ DAC Enable Bit
+\ CPU
+&95 constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ $08 constant SREG_V \ Two's Complement Overflow Flag
+ $04 constant SREG_N \ Negative Flag
+ $02 constant SREG_Z \ Zero Flag
+ $01 constant SREG_C \ Carry Flag
+&93 constant SP \ Stack Pointer
+&85 constant MCUCR \ MCU Control Register
+ $80 constant MCUCR_SPIPS \ SPI Pin Select
+ $10 constant MCUCR_PUD \ Pull-up disable
+ $02 constant MCUCR_IVSEL \ Interrupt Vector Select
+ $01 constant MCUCR_IVCE \ Interrupt Vector Change Enable
+&84 constant MCUSR \ MCU Status Register
+ $08 constant MCUSR_WDRF \ Watchdog Reset Flag
+ $04 constant MCUSR_BORF \ Brown-out Reset Flag
+ $02 constant MCUSR_EXTRF \ External Reset Flag
+ $01 constant MCUSR_PORF \ Power-on reset flag
+&102 constant OSCCAL \ Oscillator Calibration Value
+&97 constant CLKPR \
+ $80 constant CLKPR_CLKPCE \
+ $0F constant CLKPR_CLKPS \
+&83 constant SMCR \ Sleep Mode Control Register
+ $0E constant SMCR_SM \ Sleep Mode Select bits
+ $01 constant SMCR_SE \ Sleep Enable
+&59 constant GPIOR3 \ General Purpose IO Register 3
+ $FF constant GPIOR3_GPIOR \ General Purpose IO Register 3 bis
+&58 constant GPIOR2 \ General Purpose IO Register 2
+ $FF constant GPIOR2_GPIOR \ General Purpose IO Register 2 bis
+&57 constant GPIOR1 \ General Purpose IO Register 1
+ $FF constant GPIOR1_GPIOR \ General Purpose IO Register 1 bis
+&62 constant GPIOR0 \ General Purpose IO Register 0
+ $80 constant GPIOR0_GPIOR07 \ General Purpose IO Register 0 bit 7
+ $40 constant GPIOR0_GPIOR06 \ General Purpose IO Register 0 bit 6
+ $20 constant GPIOR0_GPIOR05 \ General Purpose IO Register 0 bit 5
+ $10 constant GPIOR0_GPIOR04 \ General Purpose IO Register 0 bit 4
+ $08 constant GPIOR0_GPIOR03 \ General Purpose IO Register 0 bit 3
+ $04 constant GPIOR0_GPIOR02 \ General Purpose IO Register 0 bit 2
+ $02 constant GPIOR0_GPIOR01 \ General Purpose IO Register 0 bit 1
+ $01 constant GPIOR0_GPIOR00 \ General Purpose IO Register 0 bit 0
+&73 constant PLLCSR \ PLL Control And Status Register
+ $04 constant PLLCSR_PLLF \ PLL Factor
+ $02 constant PLLCSR_PLLE \ PLL Enable
+ $01 constant PLLCSR_PLOCK \ PLL Lock Detector
+&100 constant PRR \ Power Reduction Register
+ $E0 constant PRR_PRPSC \ Power Reduction PSC2
+ $10 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
+ $08 constant PRR_PRTIM0 \ Power Reduction Timer/Counter0
+ $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
+ $02 constant PRR_PRUSART0 \ Power Reduction USART
+ $01 constant PRR_PRADC \ Power Reduction ADC
+\ PORTE
+&46 constant PORTE \ Port E Data Register
+&45 constant DDRE \ Port E Data Direction Register
+&44 constant PINE \ Port E Input Pins
+\ TIMER_COUNTER_0
+&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
+ $04 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare Match B Interrupt Enable
+ $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match A Interrupt Enable
+ $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
+&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
+ $04 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare Flag 0B
+ $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0A
+ $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
+&68 constant TCCR0A \ Timer/Counter Control Register A
+ $C0 constant TCCR0A_COM0A \ Compare Output Mode, Phase Correct PWM Mode
+ $30 constant TCCR0A_COM0B \ Compare Output Mode, Fast PWm
+ $03 constant TCCR0A_WGM0 \ Waveform Generation Mode
+&69 constant TCCR0B \ Timer/Counter Control Register B
+ $80 constant TCCR0B_FOC0A \ Force Output Compare A
+ $40 constant TCCR0B_FOC0B \ Force Output Compare B
+ $08 constant TCCR0B_WGM02 \
+ $07 constant TCCR0B_CS0 \ Clock Select
+&70 constant TCNT0 \ Timer/Counter0
+&71 constant OCR0A \ Timer/Counter0 Output Compare Register
+&72 constant OCR0B \ Timer/Counter0 Output Compare Register
+&67 constant GTCCR \ General Timer/Counter Control Register
+ $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
+ $40 constant GTCCR_ICPSEL1 \ Timer1 Input Capture Selection Bit
+ $01 constant GTCCR_PSR10 \ Prescaler Reset Timer/Counter1 and Timer/Counter0
+\ TIMER_COUNTER_1
+&111 constant TIMSK1 \ Timer/Counter Interrupt Mask Register
+ $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
+ $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output CompareB Match Interrupt Enable
+ $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output CompareA Match Interrupt Enable
+ $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
+&54 constant TIFR1 \ Timer/Counter Interrupt Flag register
+ $20 constant TIFR1_ICF1 \ Input Capture Flag 1
+ $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
+ $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
+ $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
+&128 constant TCCR1A \ Timer/Counter1 Control Register A
+ $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
+ $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
+ $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
+&129 constant TCCR1B \ Timer/Counter1 Control Register B
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
+ $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
+&130 constant TCCR1C \ Timer/Counter1 Control Register C
+ $80 constant TCCR1C_FOC1A \
+ $40 constant TCCR1C_FOC1B \
+&132 constant TCNT1 \ Timer/Counter1 Bytes
+&136 constant OCR1A \ Timer/Counter1 Output Compare Register Bytes
+&138 constant OCR1B \ Timer/Counter1 Output Compare Register Bytes
+&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
+\ AD_CONVERTER
+&124 constant ADMUX \ The ADC multiplexer Selection Register
+ $C0 constant ADMUX_REFS \ Reference Selection Bits
+ $20 constant ADMUX_ADLAR \ Left Adjust Result
+ $0F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
+&122 constant ADCSRA \ The ADC Control and Status register
+ $80 constant ADCSRA_ADEN \ ADC Enable
+ $40 constant ADCSRA_ADSC \ ADC Start Conversion
+ $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
+ $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
+ $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
+ $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
+&120 constant ADC \ ADC Data Register Bytes
+&123 constant ADCSRB \ ADC Control and Status Register B
+&126 constant DIDR0 \ Digital Input Disable Register 0
+&127 constant DIDR1 \ Digital Input Disable Register 0
+ $20 constant DIDR1_ACMP0D \
+ $10 constant DIDR1_AMP0PD \
+ $08 constant DIDR1_AMP0ND \
+ $04 constant DIDR1_ADC10D \
+ $02 constant DIDR1_ADC9D \
+ $01 constant DIDR1_ADC8D \
+&118 constant AMP0CSR \
+ $80 constant AMP0CSR_AMP0EN \
+ $40 constant AMP0CSR_AMP0IS \
+ $30 constant AMP0CSR_AMP0G \
+ $03 constant AMP0CSR_AMP0TS \
+&119 constant AMP1CSR \
+ $80 constant AMP1CSR_AMP1EN \
+ $40 constant AMP1CSR_AMP1IS \
+ $30 constant AMP1CSR_AMP1G \
+ $03 constant AMP1CSR_AMP1TS \
+\ USART
+&198 constant UDR \ USART I/O Data Register
+&192 constant UCSRA \ USART Control and Status register A
+ $80 constant UCSRA_RXC \ USART Receive Complete
+ $40 constant UCSRA_TXC \ USART Transmitt Complete
+ $20 constant UCSRA_UDRE \ USART Data Register Empty
+ $10 constant UCSRA_FE \ Framing Error
+ $08 constant UCSRA_DOR \ Data Overrun
+ $04 constant UCSRA_UPE \ USART Parity Error
+ $02 constant UCSRA_U2X \ Double USART Transmission Bit
+ $01 constant UCSRA_MPCM \ Multi-processor Communication Mode
+&193 constant UCSRB \ USART Control an Status register B
+ $80 constant UCSRB_RXCIE \ RX Complete Interrupt Enable
+ $40 constant UCSRB_TXCIE \ TX Complete Interrupt Enable
+ $20 constant UCSRB_UDRIE \ USART Data Register Empty Interrupt Enable
+ $10 constant UCSRB_RXEN \ Receiver Enable
+ $08 constant UCSRB_TXEN \ Transmitter Enable
+ $04 constant UCSRB_UCSZ2 \ Character Size
+ $02 constant UCSRB_RXB8 \ Receive Data Bit 8
+ $01 constant UCSRB_TXB8 \ Transmit Data Bit 8
+&194 constant UCSRC \ USART Control an Status register C
+ $40 constant UCSRC_UMSEL0 \ USART Mode Select
+ $30 constant UCSRC_UPM \ Parity Mode Bits
+ $08 constant UCSRC_USBS \ Stop Bit Select
+ $06 constant UCSRC_UCSZ \ Character Size Bits
+ $01 constant UCSRC_UCPOL \ Clock Polarity
+&197 constant UBRRH \ USART Baud Rate Register High Byte
+ $0F constant UBRRH_UBRR \ USART Baud Rate Register Bits
+&196 constant UBRRL \ USART Baud Rate Register Low Byte
+ $FF constant UBRRL_UBRR \ USART Baud Rate Register bits
+\ SPI
+&76 constant SPCR \ SPI Control Register
+ $80 constant SPCR_SPIE \ SPI Interrupt Enable
+ $40 constant SPCR_SPE \ SPI Enable
+ $20 constant SPCR_DORD \ Data Order
+ $10 constant SPCR_MSTR \ Master/Slave Select
+ $08 constant SPCR_CPOL \ Clock polarity
+ $04 constant SPCR_CPHA \ Clock Phase
+ $03 constant SPCR_SPR \ SPI Clock Rate Selects
+&77 constant SPSR \ SPI Status Register
+ $80 constant SPSR_SPIF \ SPI Interrupt Flag
+ $40 constant SPSR_WCOL \ Write Collision Flag
+ $01 constant SPSR_SPI2X \ Double SPI Speed Bit
+&78 constant SPDR \ SPI Data Register
+\ WATCHDOG
+&96 constant WDTCSR \ Watchdog Timer Control Register
+ $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Flag
+ $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Enable
+ $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
+ $10 constant WDTCSR_WDCE \ Watchdog Change Enable
+ $08 constant WDTCSR_WDE \ Watch Dog Enable
+\ EXTERNAL_INTERRUPT
+&105 constant EICRA \ External Interrupt Control Register A
+ $30 constant EICRA_ISC2 \ External Interrupt Sense Control Bit
+ $0C constant EICRA_ISC1 \ External Interrupt Sense Control Bit
+ $03 constant EICRA_ISC0 \ External Interrupt Sense Control Bit
+&61 constant EIMSK \ External Interrupt Mask Register
+ $07 constant EIMSK_INT \ External Interrupt Request 2 Enable
+&60 constant EIFR \ External Interrupt Flag Register
+ $07 constant EIFR_INTF \ External Interrupt Flags
+\ EEPROM
+&65 constant EEAR \ EEPROM Read/Write Access Bytes
+&64 constant EEDR \ EEPROM Data Register
+&63 constant EECR \ EEPROM Control Register
+ $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
+ $04 constant EECR_EEMWE \ EEPROM Master Write Enable
+ $02 constant EECR_EEWE \ EEPROM Write Enable
+ $01 constant EECR_EERE \ EEPROM Read Enable
+\ PSC0
+&222 constant PICR0 \ PSC 0 Input Capture Register
+&221 constant PFRC0B \ PSC 0 Input B Control
+ $80 constant PFRC0B_PCAE0B \ PSC 0 Capture Enable Input Part B
+ $40 constant PFRC0B_PISEL0B \ PSC 0 Input Select for Part B
+ $20 constant PFRC0B_PELEV0B \ PSC 0 Edge Level Selector on Input Part B
+ $10 constant PFRC0B_PFLTE0B \ PSC 0 Filter Enable on Input Part B
+ $0F constant PFRC0B_PRFM0B \ PSC 0 Retrigger and Fault Mode for Part B
+&220 constant PFRC0A \ PSC 0 Input A Control
+ $80 constant PFRC0A_PCAE0A \ PSC 0 Capture Enable Input Part A
+ $40 constant PFRC0A_PISEL0A \ PSC 0 Input Select for Part A
+ $20 constant PFRC0A_PELEV0A \ PSC 0 Edge Level Selector on Input Part A
+ $10 constant PFRC0A_PFLTE0A \ PSC 0 Filter Enable on Input Part A
+ $0F constant PFRC0A_PRFM0A \ PSC 0 Retrigger and Fault Mode for Part A
+&219 constant PCTL0 \ PSC 0 Control Register
+ $C0 constant PCTL0_PPRE0 \ PSC 0 Prescaler Selects
+ $20 constant PCTL0_PBFM0 \ PSC 0 Balance Flank Width Modulation
+ $10 constant PCTL0_PAOC0B \ PSC 0 Asynchronous Output Control B
+ $08 constant PCTL0_PAOC0A \ PSC 0 Asynchronous Output Control A
+ $04 constant PCTL0_PARUN0 \ PSC0 Auto Run
+ $02 constant PCTL0_PCCYC0 \ PSC0 Complete Cycle
+ $01 constant PCTL0_PRUN0 \ PSC 0 Run
+&218 constant PCNF0 \ PSC 0 Configuration Register
+ $80 constant PCNF0_PFIFTY0 \ PSC 0 Fifty
+ $40 constant PCNF0_PALOCK0 \ PSC 0 Autolock
+ $20 constant PCNF0_PLOCK0 \ PSC 0 Lock
+ $18 constant PCNF0_PMODE0 \ PSC 0 Mode
+ $04 constant PCNF0_POP0 \ PSC 0 Output Polarity
+ $02 constant PCNF0_PCLKSEL0 \ PSC 0 Input Clock Select
+&216 constant OCR0RB \ Output Compare RB Register
+&214 constant OCR0SB \ Output Compare SB Register
+&212 constant OCR0RA \ Output Compare RA Register
+&210 constant OCR0SA \ Output Compare SA Register
+&208 constant PSOC0 \ PSC0 Synchro and Output Configuration
+ $30 constant PSOC0_PSYNC0 \ Synchronization Out for ADC Selection
+ $04 constant PSOC0_POEN0B \ PSCOUT01 Output Enable
+ $01 constant PSOC0_POEN0A \ PSCOUT00 Output Enable
+&161 constant PIM0 \ PSC0 Interrupt Mask Register
+ $20 constant PIM0_PSEIE0 \ PSC 0 Synchro Error Interrupt Enable
+ $10 constant PIM0_PEVE0B \ External Event B Interrupt Enable
+ $08 constant PIM0_PEVE0A \ External Event A Interrupt Enable
+ $01 constant PIM0_PEOPE0 \ End of Cycle Interrupt Enable
+&160 constant PIFR0 \ PSC0 Interrupt Flag Register
+ $80 constant PIFR0_POAC0B \ PSC 0 Output A Activity
+ $40 constant PIFR0_POAC0A \ PSC 0 Output A Activity
+ $20 constant PIFR0_PSEI0 \ PSC 0 Synchro Error Interrupt
+ $10 constant PIFR0_PEV0B \ External Event B Interrupt
+ $08 constant PIFR0_PEV0A \ External Event A Interrupt
+ $06 constant PIFR0_PRN0 \ Ramp Number
+ $01 constant PIFR0_PEOP0 \ End of PSC0 Interrupt
+\ PSC2
+&254 constant PICR2 \ PSC 2 Input Capture Register
+&253 constant PFRC2B \ PSC 2 Input B Control
+ $80 constant PFRC2B_PCAE2B \ PSC 2 Capture Enable Input Part B
+ $40 constant PFRC2B_PISEL2B \ PSC 2 Input Select for Part B
+ $20 constant PFRC2B_PELEV2B \ PSC 2 Edge Level Selector on Input Part B
+ $10 constant PFRC2B_PFLTE2B \ PSC 2 Filter Enable on Input Part B
+ $0F constant PFRC2B_PRFM2B \ PSC 2 Retrigger and Fault Mode for Part B
+&252 constant PFRC2A \ PSC 2 Input B Control
+ $80 constant PFRC2A_PCAE2A \ PSC 2 Capture Enable Input Part A
+ $40 constant PFRC2A_PISEL2A \ PSC 2 Input Select for Part A
+ $20 constant PFRC2A_PELEV2A \ PSC 2 Edge Level Selector on Input Part A
+ $10 constant PFRC2A_PFLTE2A \ PSC 2 Filter Enable on Input Part A
+ $0F constant PFRC2A_PRFM2A \ PSC 2 Retrigger and Fault Mode for Part A
+&251 constant PCTL2 \ PSC 2 Control Register
+ $C0 constant PCTL2_PPRE2 \ PSC 2 Prescaler Selects
+ $20 constant PCTL2_PBFM2 \ Balance Flank Width Modulation
+ $10 constant PCTL2_PAOC2B \ PSC 2 Asynchronous Output Control B
+ $08 constant PCTL2_PAOC2A \ PSC 2 Asynchronous Output Control A
+ $04 constant PCTL2_PARUN2 \ PSC2 Auto Run
+ $02 constant PCTL2_PCCYC2 \ PSC2 Complete Cycle
+ $01 constant PCTL2_PRUN2 \ PSC 2 Run
+&250 constant PCNF2 \ PSC 2 Configuration Register
+ $80 constant PCNF2_PFIFTY2 \ PSC 2 Fifty
+ $40 constant PCNF2_PALOCK2 \ PSC 2 Autolock
+ $20 constant PCNF2_PLOCK2 \ PSC 2 Lock
+ $18 constant PCNF2_PMODE2 \ PSC 2 Mode
+ $04 constant PCNF2_POP2 \ PSC 2 Output Polarity
+ $02 constant PCNF2_PCLKSEL2 \ PSC 2 Input Clock Select
+ $01 constant PCNF2_POME2 \ PSC 2 Output Matrix Enable
+&248 constant OCR2RB \ Output Compare RB Register
+&246 constant OCR2SB \ Output Compare SB Register
+&244 constant OCR2RA \ Output Compare RA Register
+&242 constant OCR2SA \ Output Compare SA Register
+&241 constant POM2 \ PSC 2 Output Matrix
+ $F0 constant POM2_POMV2B \ Output Matrix Output B Ramps
+ $0F constant POM2_POMV2A \ Output Matrix Output A Ramps
+&240 constant PSOC2 \ PSC2 Synchro and Output Configuration
+ $C0 constant PSOC2_POS2 \ PSC 2 Output 23 Select
+ $30 constant PSOC2_PSYNC2_ \ Synchronization Out for ADC Selection
+ $08 constant PSOC2_POEN2D \ PSCOUT23 Output Enable
+ $04 constant PSOC2_POEN2B \ PSCOUT21 Output Enable
+ $02 constant PSOC2_POEN2C \ PSCOUT22 Output Enable
+ $01 constant PSOC2_POEN2A \ PSCOUT20 Output Enable
+&165 constant PIM2 \ PSC2 Interrupt Mask Register
+ $20 constant PIM2_PSEIE2 \ PSC 2 Synchro Error Interrupt Enable
+ $10 constant PIM2_PEVE2B \ External Event B Interrupt Enable
+ $08 constant PIM2_PEVE2A \ External Event A Interrupt Enable
+ $01 constant PIM2_PEOPE2 \ End of Cycle Interrupt Enable
+&164 constant PIFR2 \ PSC2 Interrupt Flag Register
+ $80 constant PIFR2_POAC2B \ PSC 2 Output A Activity
+ $40 constant PIFR2_POAC2A \ PSC 2 Output A Activity
+ $20 constant PIFR2_PSEI2 \ PSC 2 Synchro Error Interrupt
+ $10 constant PIFR2_PEV2B \ External Event B Interrupt
+ $08 constant PIFR2_PEV2A \ External Event A Interrupt
+ $06 constant PIFR2_PRN2 \ Ramp Number
+ $01 constant PIFR2_PEOP2 \ End of PSC2 Interrupt
+
+\ Interrupts
+&1 constant PSC2_CAPTAddr \ PSC2 Capture Event
+&2 constant PSC2_ECAddr \ PSC2 End Cycle
+&3 constant PSC1_CAPTAddr \ PSC1 Capture Event
+&4 constant PSC1_ECAddr \ PSC1 End Cycle
+&5 constant PSC0_CAPTAddr \ PSC0 Capture Event
+&6 constant PSC0_ECAddr \ PSC0 End Cycle
+&7 constant ANALOG_COMP_0Addr \ Analog Comparator 0
+&8 constant ANALOG_COMP_1Addr \ Analog Comparator 1
+&9 constant ANALOG_COMP_2Addr \ Analog Comparator 2
+&10 constant INT0Addr \ External Interrupt Request 0
+&11 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+&12 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
+&13 constant TIMER1_COMPBAddr \ Timer/Counter Compare Match B
+&14 constant RESERVED15Addr \
+&15 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+&16 constant TIMER0_COMP_AAddr \ Timer/Counter0 Compare Match A
+&17 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
+&18 constant ADCAddr \ ADC Conversion Complete
+&19 constant INT1Addr \ External Interrupt Request 1
+&20 constant SPI__STCAddr \ SPI Serial Transfer Complete
+&21 constant USART__RXAddr \ USART, Rx Complete
+&22 constant USART__UDREAddr \ USART Data Register Empty
+&23 constant USART__TXAddr \ USART, Tx Complete
+&24 constant INT2Addr \ External Interrupt Request 2
+&25 constant WDTAddr \ Watchdog Timeout Interrupt
+&26 constant EE_READYAddr \ EEPROM Ready
+&27 constant TIMER0_COMPBAddr \ Timer Counter 0 Compare Match B
+&28 constant INT3Addr \ External Interrupt Request 3
+&29 constant RESERVED30Addr \
+&30 constant RESERVED31Addr \
+&31 constant SPM_READYAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/at90pwm2b/device.asm b/amforth-6.5/avr8/devices/at90pwm2b/device.asm
new file mode 100644
index 0000000..6656395
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90pwm2b/device.asm
@@ -0,0 +1,123 @@
+; Partname: AT90PWM2B
+; generated automatically, do not edit
+
+.nolist
+ .include "pwm2Bdef.inc"
+.list
+
+.equ ramstart = 256
+.equ CELLSIZE = 2
+.macro readflashcell
+ lsl zl
+ rol zh
+ lpm @0, Z+
+ lpm @1, Z+
+.endmacro
+.macro writeflashcell
+ lsl zl
+ rol zh
+.endmacro
+.set WANT_PORTB = 0
+.set WANT_PORTD = 0
+.set WANT_BOOT_LOAD = 0
+.set WANT_EUSART = 0
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_DA_CONVERTER = 0
+.set WANT_CPU = 0
+.set WANT_PORTE = 0
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_AD_CONVERTER = 0
+.set WANT_USART = 0
+.set WANT_SPI = 0
+.set WANT_WATCHDOG = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_EEPROM = 0
+.set WANT_PSC0 = 0
+.set WANT_PSC2 = 0
+.equ intvecsize = 1 ; please verify; flash size: 8192 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.org 1
+ rcall isr ; PSC2 Capture Event
+.org 2
+ rcall isr ; PSC2 End Cycle
+.org 3
+ rcall isr ; PSC1 Capture Event
+.org 4
+ rcall isr ; PSC1 End Cycle
+.org 5
+ rcall isr ; PSC0 Capture Event
+.org 6
+ rcall isr ; PSC0 End Cycle
+.org 7
+ rcall isr ; Analog Comparator 0
+.org 8
+ rcall isr ; Analog Comparator 1
+.org 9
+ rcall isr ; Analog Comparator 2
+.org 10
+ rcall isr ; External Interrupt Request 0
+.org 11
+ rcall isr ; Timer/Counter1 Capture Event
+.org 12
+ rcall isr ; Timer/Counter1 Compare Match A
+.org 13
+ rcall isr ; Timer/Counter Compare Match B
+.org 14
+ rcall isr ;
+.org 15
+ rcall isr ; Timer/Counter1 Overflow
+.org 16
+ rcall isr ; Timer/Counter0 Compare Match A
+.org 17
+ rcall isr ; Timer/Counter0 Overflow
+.org 18
+ rcall isr ; ADC Conversion Complete
+.org 19
+ rcall isr ; External Interrupt Request 1
+.org 20
+ rcall isr ; SPI Serial Transfer Complete
+.org 21
+ rcall isr ; USART, Rx Complete
+.org 22
+ rcall isr ; USART Data Register Empty
+.org 23
+ rcall isr ; USART, Tx Complete
+.org 24
+ rcall isr ; External Interrupt Request 2
+.org 25
+ rcall isr ; Watchdog Timeout Interrupt
+.org 26
+ rcall isr ; EEPROM Ready
+.org 27
+ rcall isr ; Timer Counter 0 Compare Match B
+.org 28
+ rcall isr ; External Interrupt Request 3
+.org 29
+ rcall isr ;
+.org 30
+ rcall isr ;
+.org 31
+ rcall isr ; Store Program Memory Read
+.equ INTVECTORS = 32
+.nooverlap
+
+; compatability layer (maybe empty)
+.equ EEPE = EEWE
+.equ EEMPE = EEMWE
+
+; controller data area, environment query mcu-info
+mcu_info:
+mcu_ramsize:
+ .dw 512
+mcu_eepromsize:
+ .dw 512
+mcu_maxdp:
+ .dw 6144
+mcu_numints:
+ .dw 32
+mcu_name:
+ .dw 9
+ .db "AT90PWM2B",0
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/at90pwm2b/device.inc b/amforth-6.5/avr8/devices/at90pwm2b/device.inc
new file mode 100644
index 0000000..3605e6b
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90pwm2b/device.inc
@@ -0,0 +1,1281 @@
+; Partname: AT90PWM2B
+; generated automatically, no not edit
+
+.if WANT_PORTB == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw 37
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw 36
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw 35
+
+.endif
+.if WANT_PORTD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw 43
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw 42
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw 41
+
+.endif
+.if WANT_BOOT_LOAD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control Register
+VE_SPMCSR:
+ .dw $ff06
+ .db "SPMCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCSR
+XT_SPMCSR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCSR:
+ .dw 87
+
+.endif
+.if WANT_EUSART == 1
+; ( -- addr ) System Constant
+; R( -- )
+; EUSART I/O Data Register
+VE_EUDR:
+ .dw $ff04
+ .db "EUDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EUDR
+XT_EUDR:
+ .dw PFA_DOVARIABLE
+PFA_EUDR:
+ .dw 206
+; ( -- addr ) System Constant
+; R( -- )
+; EUSART Control and Status Register A
+VE_EUCSRA:
+ .dw $ff06
+ .db "EUCSRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EUCSRA
+XT_EUCSRA:
+ .dw PFA_DOVARIABLE
+PFA_EUCSRA:
+ .dw 200
+; ( -- addr ) System Constant
+; R( -- )
+; EUSART Control Register B
+VE_EUCSRB:
+ .dw $ff06
+ .db "EUCSRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EUCSRB
+XT_EUCSRB:
+ .dw PFA_DOVARIABLE
+PFA_EUCSRB:
+ .dw 201
+; ( -- addr ) System Constant
+; R( -- )
+; EUSART Status Register C
+VE_EUCSRC:
+ .dw $ff06
+ .db "EUCSRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EUCSRC
+XT_EUCSRC:
+ .dw PFA_DOVARIABLE
+PFA_EUCSRC:
+ .dw 202
+; ( -- addr ) System Constant
+; R( -- )
+; Manchester Receiver Baud Rate Register High Byte
+VE_MUBRRH:
+ .dw $ff06
+ .db "MUBRRH"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MUBRRH
+XT_MUBRRH:
+ .dw PFA_DOVARIABLE
+PFA_MUBRRH:
+ .dw 205
+; ( -- addr ) System Constant
+; R( -- )
+; Manchester Receiver Baud Rate Register Low Byte
+VE_MUBRRL:
+ .dw $ff06
+ .db "MUBRRL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MUBRRL
+XT_MUBRRL:
+ .dw PFA_DOVARIABLE
+PFA_MUBRRL:
+ .dw 204
+
+.endif
+.if WANT_ANALOG_COMPARATOR == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator 0 Control Register
+VE_AC0CON:
+ .dw $ff06
+ .db "AC0CON"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_AC0CON
+XT_AC0CON:
+ .dw PFA_DOVARIABLE
+PFA_AC0CON:
+ .dw 173
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator 1 Control Register
+VE_AC1CON:
+ .dw $ff06
+ .db "AC1CON"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_AC1CON
+XT_AC1CON:
+ .dw PFA_DOVARIABLE
+PFA_AC1CON:
+ .dw 174
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator 2 Control Register
+VE_AC2CON:
+ .dw $ff06
+ .db "AC2CON"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_AC2CON
+XT_AC2CON:
+ .dw PFA_DOVARIABLE
+PFA_AC2CON:
+ .dw 175
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw 80
+
+.endif
+.if WANT_DA_CONVERTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; DAC Data Register High Byte
+VE_DACH:
+ .dw $ff04
+ .db "DACH"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DACH
+XT_DACH:
+ .dw PFA_DOVARIABLE
+PFA_DACH:
+ .dw 172
+; ( -- addr ) System Constant
+; R( -- )
+; DAC Data Register Low Byte
+VE_DACL:
+ .dw $ff04
+ .db "DACL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DACL
+XT_DACL:
+ .dw PFA_DOVARIABLE
+PFA_DACL:
+ .dw 171
+; ( -- addr ) System Constant
+; R( -- )
+; DAC Control Register
+VE_DACON:
+ .dw $ff05
+ .db "DACON",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DACON
+XT_DACON:
+ .dw PFA_DOVARIABLE
+PFA_DACON:
+ .dw 170
+
+.endif
+.if WANT_CPU == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw 95
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer
+VE_SP:
+ .dw $ff02
+ .db "SP"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SP
+XT_SP:
+ .dw PFA_DOVARIABLE
+PFA_SP:
+ .dw 93
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw 85
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Status Register
+VE_MCUSR:
+ .dw $ff05
+ .db "MCUSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUSR
+XT_MCUSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUSR:
+ .dw 84
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Calibration Value
+VE_OSCCAL:
+ .dw $ff06
+ .db "OSCCAL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSCCAL
+XT_OSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_OSCCAL:
+ .dw 102
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_CLKPR:
+ .dw $ff05
+ .db "CLKPR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKPR
+XT_CLKPR:
+ .dw PFA_DOVARIABLE
+PFA_CLKPR:
+ .dw 97
+; ( -- addr ) System Constant
+; R( -- )
+; Sleep Mode Control Register
+VE_SMCR:
+ .dw $ff04
+ .db "SMCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SMCR
+XT_SMCR:
+ .dw PFA_DOVARIABLE
+PFA_SMCR:
+ .dw 83
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 3
+VE_GPIOR3:
+ .dw $ff06
+ .db "GPIOR3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR3
+XT_GPIOR3:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR3:
+ .dw 59
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 2
+VE_GPIOR2:
+ .dw $ff06
+ .db "GPIOR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR2
+XT_GPIOR2:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR2:
+ .dw 58
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 1
+VE_GPIOR1:
+ .dw $ff06
+ .db "GPIOR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR1
+XT_GPIOR1:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR1:
+ .dw 57
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 0
+VE_GPIOR0:
+ .dw $ff06
+ .db "GPIOR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR0
+XT_GPIOR0:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR0:
+ .dw 62
+; ( -- addr ) System Constant
+; R( -- )
+; PLL Control And Status Register
+VE_PLLCSR:
+ .dw $ff06
+ .db "PLLCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PLLCSR
+XT_PLLCSR:
+ .dw PFA_DOVARIABLE
+PFA_PLLCSR:
+ .dw 73
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register
+VE_PRR:
+ .dw $ff03
+ .db "PRR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR
+XT_PRR:
+ .dw PFA_DOVARIABLE
+PFA_PRR:
+ .dw 100
+
+.endif
+.if WANT_PORTE == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port E Data Register
+VE_PORTE:
+ .dw $ff05
+ .db "PORTE",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTE
+XT_PORTE:
+ .dw PFA_DOVARIABLE
+PFA_PORTE:
+ .dw 46
+; ( -- addr ) System Constant
+; R( -- )
+; Port E Data Direction Register
+VE_DDRE:
+ .dw $ff04
+ .db "DDRE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRE
+XT_DDRE:
+ .dw PFA_DOVARIABLE
+PFA_DDRE:
+ .dw 45
+; ( -- addr ) System Constant
+; R( -- )
+; Port E Input Pins
+VE_PINE:
+ .dw $ff04
+ .db "PINE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINE
+XT_PINE:
+ .dw PFA_DOVARIABLE
+PFA_PINE:
+ .dw 44
+
+.endif
+.if WANT_TIMER_COUNTER_0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Mask Register
+VE_TIMSK0:
+ .dw $ff06
+ .db "TIMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK0
+XT_TIMSK0:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK0:
+ .dw 110
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Flag register
+VE_TIFR0:
+ .dw $ff05
+ .db "TIFR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR0
+XT_TIFR0:
+ .dw PFA_DOVARIABLE
+PFA_TIFR0:
+ .dw 53
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register A
+VE_TCCR0A:
+ .dw $ff06
+ .db "TCCR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0A
+XT_TCCR0A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0A:
+ .dw 68
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register B
+VE_TCCR0B:
+ .dw $ff06
+ .db "TCCR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0B
+XT_TCCR0B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0B:
+ .dw 69
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw 70
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0A:
+ .dw $ff05
+ .db "OCR0A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0A
+XT_OCR0A:
+ .dw PFA_DOVARIABLE
+PFA_OCR0A:
+ .dw 71
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0B:
+ .dw $ff05
+ .db "OCR0B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0B
+XT_OCR0B:
+ .dw PFA_DOVARIABLE
+PFA_OCR0B:
+ .dw 72
+; ( -- addr ) System Constant
+; R( -- )
+; General Timer/Counter Control Register
+VE_GTCCR:
+ .dw $ff05
+ .db "GTCCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GTCCR
+XT_GTCCR:
+ .dw PFA_DOVARIABLE
+PFA_GTCCR:
+ .dw 67
+
+.endif
+.if WANT_TIMER_COUNTER_1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Mask Register
+VE_TIMSK1:
+ .dw $ff06
+ .db "TIMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK1
+XT_TIMSK1:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK1:
+ .dw 111
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Flag register
+VE_TIFR1:
+ .dw $ff05
+ .db "TIFR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR1
+XT_TIFR1:
+ .dw PFA_DOVARIABLE
+PFA_TIFR1:
+ .dw 54
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw 128
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw 129
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register C
+VE_TCCR1C:
+ .dw $ff06
+ .db "TCCR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1C
+XT_TCCR1C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1C:
+ .dw 130
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Bytes
+VE_TCNT1:
+ .dw $ff05
+ .db "TCNT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1
+XT_TCNT1:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1:
+ .dw 132
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register Bytes
+VE_OCR1A:
+ .dw $ff05
+ .db "OCR1A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1A
+XT_OCR1A:
+ .dw PFA_DOVARIABLE
+PFA_OCR1A:
+ .dw 136
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register Bytes
+VE_OCR1B:
+ .dw $ff05
+ .db "OCR1B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1B
+XT_OCR1B:
+ .dw PFA_DOVARIABLE
+PFA_OCR1B:
+ .dw 138
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Bytes
+VE_ICR1:
+ .dw $ff04
+ .db "ICR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1
+XT_ICR1:
+ .dw PFA_DOVARIABLE
+PFA_ICR1:
+ .dw 134
+
+.endif
+.if WANT_AD_CONVERTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC multiplexer Selection Register
+VE_ADMUX:
+ .dw $ff05
+ .db "ADMUX",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADMUX
+XT_ADMUX:
+ .dw PFA_DOVARIABLE
+PFA_ADMUX:
+ .dw 124
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register
+VE_ADCSRA:
+ .dw $ff06
+ .db "ADCSRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRA
+XT_ADCSRA:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRA:
+ .dw 122
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register Bytes
+VE_ADC:
+ .dw $ff03
+ .db "ADC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADC
+XT_ADC:
+ .dw PFA_DOVARIABLE
+PFA_ADC:
+ .dw 120
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Control and Status Register B
+VE_ADCSRB:
+ .dw $ff06
+ .db "ADCSRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRB
+XT_ADCSRB:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRB:
+ .dw 123
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 0
+VE_DIDR0:
+ .dw $ff05
+ .db "DIDR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR0
+XT_DIDR0:
+ .dw PFA_DOVARIABLE
+PFA_DIDR0:
+ .dw 126
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 0
+VE_DIDR1:
+ .dw $ff05
+ .db "DIDR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR1
+XT_DIDR1:
+ .dw PFA_DOVARIABLE
+PFA_DIDR1:
+ .dw 127
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_AMP0CSR:
+ .dw $ff07
+ .db "AMP0CSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_AMP0CSR
+XT_AMP0CSR:
+ .dw PFA_DOVARIABLE
+PFA_AMP0CSR:
+ .dw 118
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_AMP1CSR:
+ .dw $ff07
+ .db "AMP1CSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_AMP1CSR
+XT_AMP1CSR:
+ .dw PFA_DOVARIABLE
+PFA_AMP1CSR:
+ .dw 119
+
+.endif
+.if WANT_USART == 1
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR:
+ .dw $ff03
+ .db "UDR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR
+XT_UDR:
+ .dw PFA_DOVARIABLE
+PFA_UDR:
+ .dw 198
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status register A
+VE_UCSRA:
+ .dw $ff05
+ .db "UCSRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSRA
+XT_UCSRA:
+ .dw PFA_DOVARIABLE
+PFA_UCSRA:
+ .dw 192
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control an Status register B
+VE_UCSRB:
+ .dw $ff05
+ .db "UCSRB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSRB
+XT_UCSRB:
+ .dw PFA_DOVARIABLE
+PFA_UCSRB:
+ .dw 193
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control an Status register C
+VE_UCSRC:
+ .dw $ff05
+ .db "UCSRC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSRC
+XT_UCSRC:
+ .dw PFA_DOVARIABLE
+PFA_UCSRC:
+ .dw 194
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register High Byte
+VE_UBRRH:
+ .dw $ff05
+ .db "UBRRH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRRH
+XT_UBRRH:
+ .dw PFA_DOVARIABLE
+PFA_UBRRH:
+ .dw 197
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Low Byte
+VE_UBRRL:
+ .dw $ff05
+ .db "UBRRL",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRRL
+XT_UBRRL:
+ .dw PFA_DOVARIABLE
+PFA_UBRRL:
+ .dw 196
+
+.endif
+.if WANT_SPI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR:
+ .dw $ff04
+ .db "SPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR
+XT_SPCR:
+ .dw PFA_DOVARIABLE
+PFA_SPCR:
+ .dw 76
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR:
+ .dw $ff04
+ .db "SPSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR
+XT_SPSR:
+ .dw PFA_DOVARIABLE
+PFA_SPSR:
+ .dw 77
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR:
+ .dw $ff04
+ .db "SPDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR
+XT_SPDR:
+ .dw PFA_DOVARIABLE
+PFA_SPDR:
+ .dw 78
+
+.endif
+.if WANT_WATCHDOG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCSR:
+ .dw $ff06
+ .db "WDTCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCSR
+XT_WDTCSR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCSR:
+ .dw 96
+
+.endif
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register A
+VE_EICRA:
+ .dw $ff05
+ .db "EICRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRA
+XT_EICRA:
+ .dw PFA_DOVARIABLE
+PFA_EICRA:
+ .dw 105
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Mask Register
+VE_EIMSK:
+ .dw $ff05
+ .db "EIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIMSK
+XT_EIMSK:
+ .dw PFA_DOVARIABLE
+PFA_EIMSK:
+ .dw 61
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Flag Register
+VE_EIFR:
+ .dw $ff04
+ .db "EIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIFR
+XT_EIFR:
+ .dw PFA_DOVARIABLE
+PFA_EIFR:
+ .dw 60
+
+.endif
+.if WANT_EEPROM == 1
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Read/Write Access Bytes
+VE_EEAR:
+ .dw $ff04
+ .db "EEAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEAR
+XT_EEAR:
+ .dw PFA_DOVARIABLE
+PFA_EEAR:
+ .dw 65
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw 64
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw 63
+
+.endif
+.if WANT_PSC0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 0 Input Capture Register
+VE_PICR0:
+ .dw $ff05
+ .db "PICR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PICR0
+XT_PICR0:
+ .dw PFA_DOVARIABLE
+PFA_PICR0:
+ .dw 222
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 0 Input B Control
+VE_PFRC0B:
+ .dw $ff06
+ .db "PFRC0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PFRC0B
+XT_PFRC0B:
+ .dw PFA_DOVARIABLE
+PFA_PFRC0B:
+ .dw 221
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 0 Input A Control
+VE_PFRC0A:
+ .dw $ff06
+ .db "PFRC0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PFRC0A
+XT_PFRC0A:
+ .dw PFA_DOVARIABLE
+PFA_PFRC0A:
+ .dw 220
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 0 Control Register
+VE_PCTL0:
+ .dw $ff05
+ .db "PCTL0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCTL0
+XT_PCTL0:
+ .dw PFA_DOVARIABLE
+PFA_PCTL0:
+ .dw 219
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 0 Configuration Register
+VE_PCNF0:
+ .dw $ff05
+ .db "PCNF0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCNF0
+XT_PCNF0:
+ .dw PFA_DOVARIABLE
+PFA_PCNF0:
+ .dw 218
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare RB Register
+VE_OCR0RB:
+ .dw $ff06
+ .db "OCR0RB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0RB
+XT_OCR0RB:
+ .dw PFA_DOVARIABLE
+PFA_OCR0RB:
+ .dw 216
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare SB Register
+VE_OCR0SB:
+ .dw $ff06
+ .db "OCR0SB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0SB
+XT_OCR0SB:
+ .dw PFA_DOVARIABLE
+PFA_OCR0SB:
+ .dw 214
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare RA Register
+VE_OCR0RA:
+ .dw $ff06
+ .db "OCR0RA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0RA
+XT_OCR0RA:
+ .dw PFA_DOVARIABLE
+PFA_OCR0RA:
+ .dw 212
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare SA Register
+VE_OCR0SA:
+ .dw $ff06
+ .db "OCR0SA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0SA
+XT_OCR0SA:
+ .dw PFA_DOVARIABLE
+PFA_OCR0SA:
+ .dw 210
+; ( -- addr ) System Constant
+; R( -- )
+; PSC0 Synchro and Output Configuration
+VE_PSOC0:
+ .dw $ff05
+ .db "PSOC0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PSOC0
+XT_PSOC0:
+ .dw PFA_DOVARIABLE
+PFA_PSOC0:
+ .dw 208
+; ( -- addr ) System Constant
+; R( -- )
+; PSC0 Interrupt Mask Register
+VE_PIM0:
+ .dw $ff04
+ .db "PIM0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIM0
+XT_PIM0:
+ .dw PFA_DOVARIABLE
+PFA_PIM0:
+ .dw 161
+; ( -- addr ) System Constant
+; R( -- )
+; PSC0 Interrupt Flag Register
+VE_PIFR0:
+ .dw $ff05
+ .db "PIFR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIFR0
+XT_PIFR0:
+ .dw PFA_DOVARIABLE
+PFA_PIFR0:
+ .dw 160
+
+.endif
+.if WANT_PSC2 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 2 Input Capture Register
+VE_PICR2:
+ .dw $ff05
+ .db "PICR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PICR2
+XT_PICR2:
+ .dw PFA_DOVARIABLE
+PFA_PICR2:
+ .dw 254
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 2 Input B Control
+VE_PFRC2B:
+ .dw $ff06
+ .db "PFRC2B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PFRC2B
+XT_PFRC2B:
+ .dw PFA_DOVARIABLE
+PFA_PFRC2B:
+ .dw 253
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 2 Input B Control
+VE_PFRC2A:
+ .dw $ff06
+ .db "PFRC2A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PFRC2A
+XT_PFRC2A:
+ .dw PFA_DOVARIABLE
+PFA_PFRC2A:
+ .dw 252
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 2 Control Register
+VE_PCTL2:
+ .dw $ff05
+ .db "PCTL2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCTL2
+XT_PCTL2:
+ .dw PFA_DOVARIABLE
+PFA_PCTL2:
+ .dw 251
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 2 Configuration Register
+VE_PCNF2:
+ .dw $ff05
+ .db "PCNF2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCNF2
+XT_PCNF2:
+ .dw PFA_DOVARIABLE
+PFA_PCNF2:
+ .dw 250
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare RB Register
+VE_OCR2RB:
+ .dw $ff06
+ .db "OCR2RB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2RB
+XT_OCR2RB:
+ .dw PFA_DOVARIABLE
+PFA_OCR2RB:
+ .dw 248
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare SB Register
+VE_OCR2SB:
+ .dw $ff06
+ .db "OCR2SB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2SB
+XT_OCR2SB:
+ .dw PFA_DOVARIABLE
+PFA_OCR2SB:
+ .dw 246
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare RA Register
+VE_OCR2RA:
+ .dw $ff06
+ .db "OCR2RA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2RA
+XT_OCR2RA:
+ .dw PFA_DOVARIABLE
+PFA_OCR2RA:
+ .dw 244
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare SA Register
+VE_OCR2SA:
+ .dw $ff06
+ .db "OCR2SA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2SA
+XT_OCR2SA:
+ .dw PFA_DOVARIABLE
+PFA_OCR2SA:
+ .dw 242
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 2 Output Matrix
+VE_POM2:
+ .dw $ff04
+ .db "POM2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_POM2
+XT_POM2:
+ .dw PFA_DOVARIABLE
+PFA_POM2:
+ .dw 241
+; ( -- addr ) System Constant
+; R( -- )
+; PSC2 Synchro and Output Configuration
+VE_PSOC2:
+ .dw $ff05
+ .db "PSOC2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PSOC2
+XT_PSOC2:
+ .dw PFA_DOVARIABLE
+PFA_PSOC2:
+ .dw 240
+; ( -- addr ) System Constant
+; R( -- )
+; PSC2 Interrupt Mask Register
+VE_PIM2:
+ .dw $ff04
+ .db "PIM2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIM2
+XT_PIM2:
+ .dw PFA_DOVARIABLE
+PFA_PIM2:
+ .dw 165
+; ( -- addr ) System Constant
+; R( -- )
+; PSC2 Interrupt Flag Register
+VE_PIFR2:
+ .dw $ff05
+ .db "PIFR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIFR2
+XT_PIFR2:
+ .dw PFA_DOVARIABLE
+PFA_PIFR2:
+ .dw 164
+
+.endif
diff --git a/amforth-6.5/avr8/devices/at90pwm2b/device.py b/amforth-6.5/avr8/devices/at90pwm2b/device.py
new file mode 100644
index 0000000..4ef048e
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90pwm2b/device.py
@@ -0,0 +1,448 @@
+# Generated Automatically
+
+# Partname AT90PWM2B
+
+MCUREGS = {
+# Interrupt Vectors
+ 'PSC2_CAPTAddr' : '#2', # PSC2 Capture Event
+ 'PSC2_ECAddr' : '#4', # PSC2 End Cycle
+ 'PSC1_CAPTAddr' : '#6', # PSC1 Capture Event
+ 'PSC1_ECAddr' : '#8', # PSC1 End Cycle
+ 'PSC0_CAPTAddr' : '#10', # PSC0 Capture Event
+ 'PSC0_ECAddr' : '#12', # PSC0 End Cycle
+ 'ANALOG_COMP_0Addr' : '#14', # Analog Comparator 0
+ 'ANALOG_COMP_1Addr' : '#16', # Analog Comparator 1
+ 'ANALOG_COMP_2Addr' : '#18', # Analog Comparator 2
+ 'INT0Addr' : '#20', # External Interrupt Request 0
+ 'TIMER1_CAPTAddr' : '#22', # Timer/Counter1 Capture Event
+ 'TIMER1_COMPAAddr' : '#24', # Timer/Counter1 Compare Match A
+ 'TIMER1_COMPBAddr' : '#26', # Timer/Counter Compare Match B
+ 'RESERVED15Addr' : '#28', #
+ 'TIMER1_OVFAddr' : '#30', # Timer/Counter1 Overflow
+ 'TIMER0_COMP_AAddr' : '#32', # Timer/Counter0 Compare Match A
+ 'TIMER0_OVFAddr' : '#34', # Timer/Counter0 Overflow
+ 'ADCAddr' : '#36', # ADC Conversion Complete
+ 'INT1Addr' : '#38', # External Interrupt Request 1
+ 'SPI_STCAddr' : '#40', # SPI Serial Transfer Complete
+ 'USART_RXAddr' : '#42', # USART, Rx Complete
+ 'USART_UDREAddr' : '#44', # USART Data Register Empty
+ 'USART_TXAddr' : '#46', # USART, Tx Complete
+ 'INT2Addr' : '#48', # External Interrupt Request 2
+ 'WDTAddr' : '#50', # Watchdog Timeout Interrupt
+ 'EE_READYAddr' : '#52', # EEPROM Ready
+ 'TIMER0_COMPBAddr' : '#54', # Timer Counter 0 Compare Match B
+ 'INT3Addr' : '#56', # External Interrupt Request 3
+ 'RESERVED30Addr' : '#58', #
+ 'RESERVED31Addr' : '#60', #
+ 'SPM_READYAddr' : '#62', # Store Program Memory Read
+
+# Module PORTB
+ 'PORTB' : '$25', # Port B Data Register
+ 'DDRB' : '$24', # Port B Data Direction Register
+ 'PINB' : '$23', # Port B Input Pins
+
+# Module PORTD
+ 'PORTD' : '$2b', # Port D Data Register
+ 'DDRD' : '$2a', # Port D Data Direction Register
+ 'PIND' : '$29', # Port D Input Pins
+
+# Module BOOT_LOAD
+ 'SPMCSR' : '$57', # Store Program Memory Control R
+ 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
+ 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
+ 'SPMCSR_RWWSRE': '$10', # Read While Write section read
+ 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
+ 'SPMCSR_PGWRT': '$4', # Page Write
+ 'SPMCSR_PGERS': '$2', # Page Erase
+ 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
+
+# Module EUSART
+ 'EUDR' : '$ce', # EUSART I/O Data Register
+ 'EUCSRA' : '$c8', # EUSART Control and Status Regi
+ 'EUCSRA_UTxS': '$f0', # EUSART Control and Status Regi
+ 'EUCSRA_URxS': '$f', # EUSART Control and Status Regi
+ 'EUCSRB' : '$c9', # EUSART Control Register B
+ 'EUCSRB_EUSART': '$10', # EUSART Enable Bit
+ 'EUCSRB_EUSBS': '$8', # EUSBS Enable Bit
+ 'EUCSRB_EMCH': '$2', # Manchester Mode Bit
+ 'EUCSRB_BODR': '$1', # Order Bit
+ 'EUCSRC' : '$ca', # EUSART Status Register C
+ 'EUCSRC_FEM': '$8', # Frame Error Manchester Bit
+ 'EUCSRC_F1617': '$4', # F1617 Bit
+ 'EUCSRC_STP': '$3', # Stop Bits
+ 'MUBRRH' : '$cd', # Manchester Receiver Baud Rate
+ 'MUBRRH_MUBRR': '$ff', # Manchester Receiver Baud Rate
+ 'MUBRRL' : '$cc', # Manchester Receiver Baud Rate
+ 'MUBRRL_MUBRR': '$ff', # Manchester Receiver Baud Rate
+
+# Module ANALOG_COMPARATOR
+ 'AC0CON' : '$ad', # Analog Comparator 0 Control Re
+ 'AC0CON_AC0EN': '$80', # Analog Comparator 0 Enable Bit
+ 'AC0CON_AC0IE': '$40', # Analog Comparator 0 Interrupt
+ 'AC0CON_AC0IS': '$30', # Analog Comparator 0 Interrupt
+ 'AC0CON_AC0M': '$7', # Analog Comparator 0 Multiplexe
+ 'AC1CON' : '$ae', # Analog Comparator 1 Control Re
+ 'AC1CON_AC1EN': '$80', # Analog Comparator 1 Enable Bit
+ 'AC1CON_AC1IE': '$40', # Analog Comparator 1 Interrupt
+ 'AC1CON_AC1IS': '$30', # Analog Comparator 1 Interrupt
+ 'AC1CON_AC1ICE': '$8', # Analog Comparator 1 Interrupt
+ 'AC1CON_AC1M': '$7', # Analog Comparator 1 Multiplexe
+ 'AC2CON' : '$af', # Analog Comparator 2 Control Re
+ 'AC2CON_AC2EN': '$80', # Analog Comparator 2 Enable Bit
+ 'AC2CON_AC2IE': '$40', # Analog Comparator 2 Interrupt
+ 'AC2CON_AC2IS': '$30', # Analog Comparator 2 Interrupt
+ 'AC2CON_AC2M': '$7', # Analog Comparator 2 Multiplexe
+ 'ACSR' : '$50', # Analog Comparator Status Regis
+ 'ACSR_ACCKDIV': '$80', # Analog Comparator Clock Divide
+ 'ACSR_AC2IF': '$40', # Analog Comparator 2 Interrupt
+ 'ACSR_AC1IF': '$20', # Analog Comparator 1 Interrupt
+ 'ACSR_AC0IF': '$10', # Analog Comparator 0 Interrupt
+ 'ACSR_AC2O': '$4', # Analog Comparator 2 Output Bit
+ 'ACSR_AC1O': '$2', # Analog Comparator 1 Output Bit
+ 'ACSR_AC0O': '$1', # Analog Comparator 0 Output Bit
+
+# Module DA_CONVERTER
+ 'DACH' : '$ac', # DAC Data Register High Byte
+ 'DACH_DACH': '$ff', # DAC Data Register High Byte Bi
+ 'DACL' : '$ab', # DAC Data Register Low Byte
+ 'DACL_DACL': '$ff', # DAC Data Register Low Byte Bit
+ 'DACON' : '$aa', # DAC Control Register
+ 'DACON_DAATE': '$80', # DAC Auto Trigger Enable Bit
+ 'DACON_DATS': '$70', # DAC Trigger Selection Bits
+ 'DACON_DALA': '$4', # DAC Left Adjust
+ 'DACON_DAEN': '$1', # DAC Enable Bit
+
+# Module CPU
+ 'SREG' : '$5f', # Status Register
+ 'SREG_I': '$80', # Global Interrupt Enable
+ 'SREG_T': '$40', # Bit Copy Storage
+ 'SREG_H': '$20', # Half Carry Flag
+ 'SREG_S': '$10', # Sign Bit
+ 'SREG_V': '$8', # Two's Complement Overflow Flag
+ 'SREG_N': '$4', # Negative Flag
+ 'SREG_Z': '$2', # Zero Flag
+ 'SREG_C': '$1', # Carry Flag
+ 'SP' : '$5d', # Stack Pointer
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_SPIPS': '$80', # SPI Pin Select
+ 'MCUCR_PUD': '$10', # Pull-up disable
+ 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
+ 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
+ 'MCUSR_BORF': '$4', # Brown-out Reset Flag
+ 'MCUSR_EXTRF': '$2', # External Reset Flag
+ 'MCUSR_PORF': '$1', # Power-on reset flag
+ 'OSCCAL' : '$66', # Oscillator Calibration Value
+ 'CLKPR' : '$61', #
+ 'CLKPR_CLKPCE': '$80', #
+ 'CLKPR_CLKPS': '$f', #
+ 'SMCR' : '$53', # Sleep Mode Control Register
+ 'SMCR_SM': '$e', # Sleep Mode Select bits
+ 'SMCR_SE': '$1', # Sleep Enable
+ 'GPIOR3' : '$3b', # General Purpose IO Register 3
+ 'GPIOR3_GPIOR': '$ff', # General Purpose IO Register 3
+ 'GPIOR2' : '$3a', # General Purpose IO Register 2
+ 'GPIOR2_GPIOR': '$ff', # General Purpose IO Register 2
+ 'GPIOR1' : '$39', # General Purpose IO Register 1
+ 'GPIOR1_GPIOR': '$ff', # General Purpose IO Register 1
+ 'GPIOR0' : '$3e', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR07': '$80', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR06': '$40', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR05': '$20', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR04': '$10', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR03': '$8', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR02': '$4', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR01': '$2', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR00': '$1', # General Purpose IO Register 0
+ 'PLLCSR' : '$49', # PLL Control And Status Registe
+ 'PLLCSR_PLLF': '$4', # PLL Factor
+ 'PLLCSR_PLLE': '$2', # PLL Enable
+ 'PLLCSR_PLOCK': '$1', # PLL Lock Detector
+ 'PRR' : '$64', # Power Reduction Register
+ 'PRR_PRPSC': '$e0', # Power Reduction PSC2
+ 'PRR_PRTIM1': '$10', # Power Reduction Timer/Counter1
+ 'PRR_PRTIM0': '$8', # Power Reduction Timer/Counter0
+ 'PRR_PRSPI': '$4', # Power Reduction Serial Periphe
+ 'PRR_PRUSART0': '$2', # Power Reduction USART
+ 'PRR_PRADC': '$1', # Power Reduction ADC
+
+# Module PORTE
+ 'PORTE' : '$2e', # Port E Data Register
+ 'DDRE' : '$2d', # Port E Data Direction Register
+ 'PINE' : '$2c', # Port E Input Pins
+
+# Module TIMER_COUNTER_0
+ 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
+ 'TIMSK0_OCIE0B': '$4', # Timer/Counter0 Output Compare
+ 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
+ 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
+ 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
+ 'TIFR0_OCF0B': '$4', # Timer/Counter0 Output Compare
+ 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
+ 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
+ 'TCCR0A' : '$44', # Timer/Counter Control Registe
+ 'TCCR0A_COM0A': '$c0', # Compare Output Mode, Phase Cor
+ 'TCCR0A_COM0B': '$30', # Compare Output Mode, Fast PWm
+ 'TCCR0A_WGM0': '$3', # Waveform Generation Mode
+ 'TCCR0B' : '$45', # Timer/Counter Control Register
+ 'TCCR0B_FOC0A': '$80', # Force Output Compare A
+ 'TCCR0B_FOC0B': '$40', # Force Output Compare B
+ 'TCCR0B_WGM02': '$8', #
+ 'TCCR0B_CS0': '$7', # Clock Select
+ 'TCNT0' : '$46', # Timer/Counter0
+ 'OCR0A' : '$47', # Timer/Counter0 Output Compare
+ 'OCR0B' : '$48', # Timer/Counter0 Output Compare
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_ICPSEL1': '$40', # Timer1 Input Capture Selection
+ 'GTCCR_PSR10': '$1', # Prescaler Reset Timer/Counter1
+
+# Module TIMER_COUNTER_1
+ 'TIMSK1' : '$6f', # Timer/Counter Interrupt Mask R
+ 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
+ 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output CompareB
+ 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output CompareA
+ 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
+ 'TIFR1' : '$36', # Timer/Counter Interrupt Flag r
+ 'TIFR1_ICF1': '$20', # Input Capture Flag 1
+ 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
+ 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
+ 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
+ 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
+ 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
+ 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
+ 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
+ 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
+ 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
+ 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
+ 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
+ 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
+ 'TCCR1C' : '$82', # Timer/Counter1 Control Registe
+ 'TCCR1C_FOC1A': '$80', #
+ 'TCCR1C_FOC1B': '$40', #
+ 'TCNT1' : '$84', # Timer/Counter1 Bytes
+ 'OCR1A' : '$88', # Timer/Counter1 Output Compare
+ 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
+ 'ICR1' : '$86', # Timer/Counter1 Input Capture R
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSRSYNC': '$1', # Prescaler Reset Timer/Counter1
+
+# Module AD_CONVERTER
+ 'ADMUX' : '$7c', # The ADC multiplexer Selection
+ 'ADMUX_REFS': '$c0', # Reference Selection Bits
+ 'ADMUX_ADLAR': '$20', # Left Adjust Result
+ 'ADMUX_MUX': '$f', # Analog Channel and Gain Select
+ 'ADCSRA' : '$7a', # The ADC Control and Status reg
+ 'ADCSRA_ADEN': '$80', # ADC Enable
+ 'ADCSRA_ADSC': '$40', # ADC Start Conversion
+ 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
+ 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
+ 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
+ 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
+ 'ADC' : '$78', # ADC Data Register Bytes
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'DIDR0' : '$7e', # Digital Input Disable Register
+ 'DIDR1' : '$7f', # Digital Input Disable Register
+ 'DIDR1_ACMP0D': '$20', #
+ 'DIDR1_AMP0PD': '$10', #
+ 'DIDR1_AMP0ND': '$8', #
+ 'DIDR1_ADC10D': '$4', #
+ 'DIDR1_ADC9D': '$2', #
+ 'DIDR1_ADC8D': '$1', #
+ 'AMP0CSR' : '$76', #
+ 'AMP0CSR_AMP0EN': '$80', #
+ 'AMP0CSR_AMP0IS': '$40', #
+ 'AMP0CSR_AMP0G': '$30', #
+ 'AMP0CSR_AMP0TS': '$3', #
+ 'AMP1CSR' : '$77', #
+ 'AMP1CSR_AMP1EN': '$80', #
+ 'AMP1CSR_AMP1IS': '$40', #
+ 'AMP1CSR_AMP1G': '$30', #
+ 'AMP1CSR_AMP1TS': '$3', #
+
+# Module USART
+ 'UDR' : '$c6', # USART I/O Data Register
+ 'UCSRA' : '$c0', # USART Control and Status regis
+ 'UCSRA_RXC': '$80', # USART Receive Complete
+ 'UCSRA_TXC': '$40', # USART Transmitt Complete
+ 'UCSRA_UDRE': '$20', # USART Data Register Empty
+ 'UCSRA_FE': '$10', # Framing Error
+ 'UCSRA_DOR': '$8', # Data Overrun
+ 'UCSRA_UPE': '$4', # USART Parity Error
+ 'UCSRA_U2X': '$2', # Double USART Transmission Bit
+ 'UCSRA_MPCM': '$1', # Multi-processor Communication
+ 'UCSRB' : '$c1', # USART Control an Status regist
+ 'UCSRB_RXCIE': '$80', # RX Complete Interrupt Enable
+ 'UCSRB_TXCIE': '$40', # TX Complete Interrupt Enable
+ 'UCSRB_UDRIE': '$20', # USART Data Register Empty Inte
+ 'UCSRB_RXEN': '$10', # Receiver Enable
+ 'UCSRB_TXEN': '$8', # Transmitter Enable
+ 'UCSRB_UCSZ2': '$4', # Character Size
+ 'UCSRB_RXB8': '$2', # Receive Data Bit 8
+ 'UCSRB_TXB8': '$1', # Transmit Data Bit 8
+ 'UCSRC' : '$c2', # USART Control an Status regist
+ 'UCSRC_UMSEL0': '$40', # USART Mode Select
+ 'UCSRC_UPM': '$30', # Parity Mode Bits
+ 'UCSRC_USBS': '$8', # Stop Bit Select
+ 'UCSRC_UCSZ': '$6', # Character Size Bits
+ 'UCSRC_UCPOL': '$1', # Clock Polarity
+ 'UBRRH' : '$c5', # USART Baud Rate Register High
+ 'UBRRH_UBRR': '$f', # USART Baud Rate Register Bits
+ 'UBRRL' : '$c4', # USART Baud Rate Register Low B
+ 'UBRRL_UBRR': '$ff', # USART Baud Rate Register bits
+
+# Module SPI
+ 'SPCR' : '$4c', # SPI Control Register
+ 'SPCR_SPIE': '$80', # SPI Interrupt Enable
+ 'SPCR_SPE': '$40', # SPI Enable
+ 'SPCR_DORD': '$20', # Data Order
+ 'SPCR_MSTR': '$10', # Master/Slave Select
+ 'SPCR_CPOL': '$8', # Clock polarity
+ 'SPCR_CPHA': '$4', # Clock Phase
+ 'SPCR_SPR': '$3', # SPI Clock Rate Selects
+ 'SPSR' : '$4d', # SPI Status Register
+ 'SPSR_SPIF': '$80', # SPI Interrupt Flag
+ 'SPSR_WCOL': '$40', # Write Collision Flag
+ 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
+ 'SPDR' : '$4e', # SPI Data Register
+
+# Module WATCHDOG
+ 'WDTCSR' : '$60', # Watchdog Timer Control Registe
+ 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
+ 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
+ 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
+ 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
+ 'WDTCSR_WDE': '$8', # Watch Dog Enable
+
+# Module EXTERNAL_INTERRUPT
+ 'EICRA' : '$69', # External Interrupt Control Reg
+ 'EICRA_ISC2': '$30', # External Interrupt Sense Contr
+ 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
+ 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
+ 'EIMSK' : '$3d', # External Interrupt Mask Regist
+ 'EIMSK_INT': '$7', # External Interrupt Request 2 E
+ 'EIFR' : '$3c', # External Interrupt Flag Regist
+ 'EIFR_INTF': '$7', # External Interrupt Flags
+
+# Module EEPROM
+ 'EEAR' : '$41', # EEPROM Read/Write Access Byte
+ 'EEDR' : '$40', # EEPROM Data Register
+ 'EECR' : '$3f', # EEPROM Control Register
+ 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
+ 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
+ 'EECR_EEWE': '$2', # EEPROM Write Enable
+ 'EECR_EERE': '$1', # EEPROM Read Enable
+
+# Module PSC0
+ 'PICR0' : '$de', # PSC 0 Input Capture Register
+ 'PFRC0B' : '$dd', # PSC 0 Input B Control
+ 'PFRC0B_PCAE0B': '$80', # PSC 0 Capture Enable Input Par
+ 'PFRC0B_PISEL0B': '$40', # PSC 0 Input Select for Part B
+ 'PFRC0B_PELEV0B': '$20', # PSC 0 Edge Level Selector on I
+ 'PFRC0B_PFLTE0B': '$10', # PSC 0 Filter Enable on Input P
+ 'PFRC0B_PRFM0B': '$f', # PSC 0 Retrigger and Fault Mode
+ 'PFRC0A' : '$dc', # PSC 0 Input A Control
+ 'PFRC0A_PCAE0A': '$80', # PSC 0 Capture Enable Input Par
+ 'PFRC0A_PISEL0A': '$40', # PSC 0 Input Select for Part A
+ 'PFRC0A_PELEV0A': '$20', # PSC 0 Edge Level Selector on I
+ 'PFRC0A_PFLTE0A': '$10', # PSC 0 Filter Enable on Input P
+ 'PFRC0A_PRFM0A': '$f', # PSC 0 Retrigger and Fault Mode
+ 'PCTL0' : '$db', # PSC 0 Control Register
+ 'PCTL0_PPRE0': '$c0', # PSC 0 Prescaler Selects
+ 'PCTL0_PBFM0': '$20', # PSC 0 Balance Flank Width Modu
+ 'PCTL0_PAOC0B': '$10', # PSC 0 Asynchronous Output Cont
+ 'PCTL0_PAOC0A': '$8', # PSC 0 Asynchronous Output Cont
+ 'PCTL0_PARUN0': '$4', # PSC0 Auto Run
+ 'PCTL0_PCCYC0': '$2', # PSC0 Complete Cycle
+ 'PCTL0_PRUN0': '$1', # PSC 0 Run
+ 'PCNF0' : '$da', # PSC 0 Configuration Register
+ 'PCNF0_PFIFTY0': '$80', # PSC 0 Fifty
+ 'PCNF0_PALOCK0': '$40', # PSC 0 Autolock
+ 'PCNF0_PLOCK0': '$20', # PSC 0 Lock
+ 'PCNF0_PMODE0': '$18', # PSC 0 Mode
+ 'PCNF0_POP0': '$4', # PSC 0 Output Polarity
+ 'PCNF0_PCLKSEL0': '$2', # PSC 0 Input Clock Select
+ 'OCR0RB' : '$d8', # Output Compare RB Register
+ 'OCR0SB' : '$d6', # Output Compare SB Register
+ 'OCR0RA' : '$d4', # Output Compare RA Register
+ 'OCR0SA' : '$d2', # Output Compare SA Register
+ 'PSOC0' : '$d0', # PSC0 Synchro and Output Config
+ 'PSOC0_PSYNC0': '$30', # Synchronization Out for ADC Se
+ 'PSOC0_POEN0B': '$4', # PSCOUT01 Output Enable
+ 'PSOC0_POEN0A': '$1', # PSCOUT00 Output Enable
+ 'PIM0' : '$a1', # PSC0 Interrupt Mask Register
+ 'PIM0_PSEIE0': '$20', # PSC 0 Synchro Error Interrupt
+ 'PIM0_PEVE0B': '$10', # External Event B Interrupt Ena
+ 'PIM0_PEVE0A': '$8', # External Event A Interrupt Ena
+ 'PIM0_PEOPE0': '$1', # End of Cycle Interrupt Enable
+ 'PIFR0' : '$a0', # PSC0 Interrupt Flag Register
+ 'PIFR0_POAC0B': '$80', # PSC 0 Output A Activity
+ 'PIFR0_POAC0A': '$40', # PSC 0 Output A Activity
+ 'PIFR0_PSEI0': '$20', # PSC 0 Synchro Error Interrupt
+ 'PIFR0_PEV0B': '$10', # External Event B Interrupt
+ 'PIFR0_PEV0A': '$8', # External Event A Interrupt
+ 'PIFR0_PRN0': '$6', # Ramp Number
+ 'PIFR0_PEOP0': '$1', # End of PSC0 Interrupt
+
+# Module PSC2
+ 'PICR2' : '$fe', # PSC 2 Input Capture Register
+ 'PFRC2B' : '$fd', # PSC 2 Input B Control
+ 'PFRC2B_PCAE2B': '$80', # PSC 2 Capture Enable Input Par
+ 'PFRC2B_PISEL2B': '$40', # PSC 2 Input Select for Part B
+ 'PFRC2B_PELEV2B': '$20', # PSC 2 Edge Level Selector on I
+ 'PFRC2B_PFLTE2B': '$10', # PSC 2 Filter Enable on Input P
+ 'PFRC2B_PRFM2B': '$f', # PSC 2 Retrigger and Fault Mode
+ 'PFRC2A' : '$fc', # PSC 2 Input B Control
+ 'PFRC2A_PCAE2A': '$80', # PSC 2 Capture Enable Input Par
+ 'PFRC2A_PISEL2A': '$40', # PSC 2 Input Select for Part A
+ 'PFRC2A_PELEV2A': '$20', # PSC 2 Edge Level Selector on I
+ 'PFRC2A_PFLTE2A': '$10', # PSC 2 Filter Enable on Input P
+ 'PFRC2A_PRFM2A': '$f', # PSC 2 Retrigger and Fault Mode
+ 'PCTL2' : '$fb', # PSC 2 Control Register
+ 'PCTL2_PPRE2': '$c0', # PSC 2 Prescaler Selects
+ 'PCTL2_PBFM2': '$20', # Balance Flank Width Modulation
+ 'PCTL2_PAOC2B': '$10', # PSC 2 Asynchronous Output Cont
+ 'PCTL2_PAOC2A': '$8', # PSC 2 Asynchronous Output Cont
+ 'PCTL2_PARUN2': '$4', # PSC2 Auto Run
+ 'PCTL2_PCCYC2': '$2', # PSC2 Complete Cycle
+ 'PCTL2_PRUN2': '$1', # PSC 2 Run
+ 'PCNF2' : '$fa', # PSC 2 Configuration Register
+ 'PCNF2_PFIFTY2': '$80', # PSC 2 Fifty
+ 'PCNF2_PALOCK2': '$40', # PSC 2 Autolock
+ 'PCNF2_PLOCK2': '$20', # PSC 2 Lock
+ 'PCNF2_PMODE2': '$18', # PSC 2 Mode
+ 'PCNF2_POP2': '$4', # PSC 2 Output Polarity
+ 'PCNF2_PCLKSEL2': '$2', # PSC 2 Input Clock Select
+ 'PCNF2_POME2': '$1', # PSC 2 Output Matrix Enable
+ 'OCR2RB' : '$f8', # Output Compare RB Register
+ 'OCR2SB' : '$f6', # Output Compare SB Register
+ 'OCR2RA' : '$f4', # Output Compare RA Register
+ 'OCR2SA' : '$f2', # Output Compare SA Register
+ 'POM2' : '$f1', # PSC 2 Output Matrix
+ 'POM2_POMV2B': '$f0', # Output Matrix Output B Ramps
+ 'POM2_POMV2A': '$f', # Output Matrix Output A Ramps
+ 'PSOC2' : '$f0', # PSC2 Synchro and Output Config
+ 'PSOC2_POS2': '$c0', # PSC 2 Output 23 Select
+ 'PSOC2_PSYNC2_': '$30', # Synchronization Out for ADC Se
+ 'PSOC2_POEN2D': '$8', # PSCOUT23 Output Enable
+ 'PSOC2_POEN2B': '$4', # PSCOUT21 Output Enable
+ 'PSOC2_POEN2C': '$2', # PSCOUT22 Output Enable
+ 'PSOC2_POEN2A': '$1', # PSCOUT20 Output Enable
+ 'PIM2' : '$a5', # PSC2 Interrupt Mask Register
+ 'PIM2_PSEIE2': '$20', # PSC 2 Synchro Error Interrupt
+ 'PIM2_PEVE2B': '$10', # External Event B Interrupt Ena
+ 'PIM2_PEVE2A': '$8', # External Event A Interrupt Ena
+ 'PIM2_PEOPE2': '$1', # End of Cycle Interrupt Enable
+ 'PIFR2' : '$a4', # PSC2 Interrupt Flag Register
+ 'PIFR2_POAC2B': '$80', # PSC 2 Output A Activity
+ 'PIFR2_POAC2A': '$40', # PSC 2 Output A Activity
+ 'PIFR2_PSEI2': '$20', # PSC 2 Synchro Error Interrupt
+ 'PIFR2_PEV2B': '$10', # External Event B Interrupt
+ 'PIFR2_PEV2A': '$8', # External Event A Interrupt
+ 'PIFR2_PRN2': '$6', # Ramp Number
+ 'PIFR2_PEOP2': '$1', # End of PSC2 Interrupt
+
+ '__amforth_dummy':'0'
+}
diff --git a/amforth-6.5/avr8/devices/at90pwm2b/words/no-jtag.asm b/amforth-6.5/avr8/devices/at90pwm2b/words/no-jtag.asm
new file mode 100644
index 0000000..352a4bb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90pwm2b/words/no-jtag.asm
@@ -0,0 +1,14 @@
+; ( -- )
+; ( -- )
+; MCU
+; disable jtag at runtime
+VE_NOJTAG:
+ .dw $FF05
+ .db "-jtag",0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOJTAG
+XT_NOJTAG:
+ .dw PFA_NOJTAG
+PFA_NOJTAG:
+
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/at90pwm2b/words/no-wdt.asm b/amforth-6.5/avr8/devices/at90pwm2b/words/no-wdt.asm
new file mode 100644
index 0000000..ff6ddd1
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90pwm2b/words/no-wdt.asm
@@ -0,0 +1,34 @@
+; ( -- )
+; MCU
+; disable watch dog timer at runtime
+VE_NOWDT:
+ .dw $ff04
+ .db "-wdt"
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOWDT
+XT_NOWDT:
+ .dw PFA_NOWDT
+PFA_NOWDT:
+
+ in temp1,SREG
+ push temp1
+ ; Turn always off global interrupt.
+ cli
+ ; Reset Watchdog Timer
+ wdr
+ ; Clear WDRF in MCUSR
+ in temp1, MCUSR
+ andi temp1, (0xff & (0<<WDRF))
+ out MCUSR, temp1
+ ; Write logical one to WDCE and WDE
+ ; Keep old prescaler setting to prevent unintentional time-out
+ in_ temp1, WDTCSR
+ ori temp1, (1<<WDCE) | (1<<WDE)
+ out_ WDTCSR, temp1
+ ; Turn off WDT
+ ldi temp1, (0<<WDE)
+ out_ WDTCSR, temp1
+ ; restore status register
+ pop temp1
+ out SREG,temp1
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/at90pwm2b/words/sleep.asm b/amforth-6.5/avr8/devices/at90pwm2b/words/sleep.asm
new file mode 100644
index 0000000..256249c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90pwm2b/words/sleep.asm
@@ -0,0 +1,19 @@
+; ( mode -- )
+; MCU
+; put the controller into the specified sleep mode
+VE_SLEEP:
+ .dw $ff05
+ .db "sleep", 0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_SLEEP
+XT_SLEEP:
+ .dw PFA_SLEEP
+PFA_SLEEP:
+ andi tosl, 7 ; leave only legal mode bits
+ lsl tosl ; move to correct location (bits 3-1)
+ ori tosl, 1 ; set the SE bit
+ out_ SMCR, tosl ; set the sleep config
+ sleep ; nighty-night
+ out_ SMCR, zerol ; 0 protects against accidental sleeps
+ loadtos ; pop argument from stack
+ jmp_ DO_NEXT