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-rw-r--r--amforth-6.5/avr8/devices/at90pwm81/at90pwm81.frt370
-rw-r--r--amforth-6.5/avr8/devices/at90pwm81/device.asm96
-rw-r--r--amforth-6.5/avr8/devices/at90pwm81/device.inc1080
-rw-r--r--amforth-6.5/avr8/devices/at90pwm81/device.py389
-rw-r--r--amforth-6.5/avr8/devices/at90pwm81/words/no-jtag.asm14
-rw-r--r--amforth-6.5/avr8/devices/at90pwm81/words/no-wdt.asm34
-rw-r--r--amforth-6.5/avr8/devices/at90pwm81/words/sleep.asm19
7 files changed, 2002 insertions, 0 deletions
diff --git a/amforth-6.5/avr8/devices/at90pwm81/at90pwm81.frt b/amforth-6.5/avr8/devices/at90pwm81/at90pwm81.frt
new file mode 100644
index 0000000..a25970a
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90pwm81/at90pwm81.frt
@@ -0,0 +1,370 @@
+\ Partname: AT90PWM81
+\ generated automatically
+
+\ PORTB
+&37 constant PORTB \ Port B Data Register
+&36 constant DDRB \ Port B Data Direction Register
+&35 constant PINB \ Port B Input Pins
+\ PORTD
+&43 constant PORTD \ Port D Data Register
+&42 constant DDRD \ Port D Data Direction Register
+&41 constant PIND \ Port D Input Pins
+\ DA_CONVERTER
+&89 constant DACH \ DAC Data Register High Byte
+ $FF constant DACH_DACH \ DAC Data Register High Byte Bits
+&88 constant DACL \ DAC Data Register Low Byte
+ $FF constant DACL_DACL \ DAC Data Register Low Byte Bits
+&118 constant DACON \ DAC Control Register
+ $80 constant DACON_DAATE \ DAC Auto Trigger Enable Bit
+ $70 constant DACON_DATS \ DAC Trigger Selection Bits
+ $04 constant DACON_DALA \ DAC Left Adjust
+ $01 constant DACON_DAEN \ DAC Enable Bit
+\ PORTE
+&46 constant PORTE \ Port E Data Register
+&45 constant DDRE \ Port E Data Direction Register
+&44 constant PINE \ Port E Input Pins
+\ SPI
+&55 constant SPCR \ SPI Control Register
+ $80 constant SPCR_SPIE \ SPI Interrupt Enable
+ $40 constant SPCR_SPE \ SPI Enable
+ $20 constant SPCR_DORD \ Data Order
+ $10 constant SPCR_MSTR \ Master/Slave Select
+ $08 constant SPCR_CPOL \ Clock polarity
+ $04 constant SPCR_CPHA \ Clock Phase
+ $03 constant SPCR_SPR \ SPI Clock Rate Selects
+&56 constant SPSR \ SPI Status Register
+ $80 constant SPSR_SPIF \ SPI Interrupt Flag
+ $40 constant SPSR_WCOL \ Write Collision Flag
+ $01 constant SPSR_SPI2X \ Double SPI Speed Bit
+&86 constant SPDR \ SPI Data Register
+\ WATCHDOG
+&130 constant WDTCSR \ Watchdog Timer Control Register
+ $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Flag
+ $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Enable
+ $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
+ $10 constant WDTCSR_WDCE \ Watchdog Change Enable
+ $08 constant WDTCSR_WDE \ Watch Dog Enable
+\ EXTERNAL_INTERRUPT
+&137 constant EICRA \ External Interrupt Control Register A
+ $30 constant EICRA_ISC2 \ External Interrupt Sense Control Bit
+ $0C constant EICRA_ISC1 \ External Interrupt Sense Control Bit
+ $03 constant EICRA_ISC0 \ External Interrupt Sense Control Bit
+&65 constant EIMSK \ External Interrupt Mask Register
+ $07 constant EIMSK_INT \ External Interrupt Request 2 Enable
+&64 constant EIFR \ External Interrupt Flag Register
+ $07 constant EIFR_INTF \ External Interrupt Flags
+\ AD_CONVERTER
+&40 constant ADMUX \ The ADC multiplexer Selection Register
+ $C0 constant ADMUX_REFS \ Reference Selection Bits
+ $20 constant ADMUX_ADLAR \ Left Adjust Result
+ $0F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
+&38 constant ADCSRA \ The ADC Control and Status register
+ $80 constant ADCSRA_ADEN \ ADC Enable
+ $40 constant ADCSRA_ADSC \ ADC Start Conversion
+ $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
+ $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
+ $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
+ $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
+&76 constant ADC \ ADC Data Register Bytes
+&39 constant ADCSRB \ ADC Control and Status Register B
+ $80 constant ADCSRB_ADHSM \ ADC High Speed Mode
+ $40 constant ADCSRB_ADNCDIS \ ADC Noise Canceller Disable
+ $10 constant ADCSRB_ADSSEN \ ADC Single Shot Enable on PSC's Synchronisation Signals
+ $0F constant ADCSRB_ADTS \ ADC Auto Trigger Sources
+&119 constant DIDR0 \ Digital Input Disable Register 0
+ $80 constant DIDR0_ADC7D \
+ $40 constant DIDR0_ADC6D \ ADC7 Digital input Disable
+ $20 constant DIDR0_ADC5D \ ADC5 Digital input Disable
+ $10 constant DIDR0_ADC4D \ ADC4 Digital input Disable
+ $08 constant DIDR0_ADC3D \ ADC3 Digital input Disable
+ $04 constant DIDR0_ADC2D \ ADC2 Digital input Disable
+ $02 constant DIDR0_ADC1D \ ADC1 Digital input Disable
+ $01 constant DIDR0_ADC0D \ ADC0 Digital input Disable
+&120 constant DIDR1 \ Digital Input Disable Register 0
+ $08 constant DIDR1_ACMP1MD \
+ $04 constant DIDR1_AMP0POSD \
+ $02 constant DIDR1_ADC10D \
+ $01 constant DIDR1_ADC9D \
+&121 constant AMP0CSR \
+ $80 constant AMP0CSR_AMP0EN \
+ $40 constant AMP0CSR_AMP0IS \
+ $30 constant AMP0CSR_AMP0G \
+ $08 constant AMP0CSR_AMP0GS \
+ $03 constant AMP0CSR_AMP0TS \
+\ ANALOG_COMPARATOR
+&127 constant AC3CON \ Analog Comparator3 Control Register
+ $80 constant AC3CON_AC3EN \ Analog Comparator3 Enable Bit
+ $40 constant AC3CON_AC3IE \ Analog Comparator 3 Interrupt Enable Bit
+ $30 constant AC3CON_AC3IS \ Analog Comparator 3 Interrupt Select Bit
+ $08 constant AC3CON_AC3OEA \ Analog Comparator 3 Alternate Output Enable
+ $07 constant AC3CON_AC3M \ Analog Comparator 3 Multiplexer Register
+&125 constant AC1CON \ Analog Comparator 1 Control Register
+ $80 constant AC1CON_AC1EN \ Analog Comparator 1 Enable Bit
+ $40 constant AC1CON_AC1IE \ Analog Comparator 1 Interrupt Enable Bit
+ $30 constant AC1CON_AC1IS \ Analog Comparator 1 Interrupt Select Bit
+ $07 constant AC1CON_AC1M \ Analog Comparator 1 Multiplexer Register
+&126 constant AC2CON \ Analog Comparator 2 Control Register
+ $80 constant AC2CON_AC2EN \ Analog Comparator 2 Enable Bit
+ $40 constant AC2CON_AC2IE \ Analog Comparator 2 Interrupt Enable Bit
+ $30 constant AC2CON_AC2IS \ Analog Comparator 2 Interrupt Select Bit
+ $07 constant AC2CON_AC2M \ Analog Comparator 2 Multiplexer Register
+&32 constant ACSR \ Analog Comparator Status Register
+ $80 constant ACSR_AC3IF \ Analog Comparator 3 Interrupt Flag Bit
+ $40 constant ACSR_AC2IF \ Analog Comparator 2 Interrupt Flag Bit
+ $20 constant ACSR_AC1IF \ Analog Comparator 1 Interrupt Flag Bit
+ $08 constant ACSR_AC3O \ Analog Comparator 3 Output Bit
+ $04 constant ACSR_AC2O \ Analog Comparator 2 Output Bit
+ $02 constant ACSR_AC1O \ Analog Comparator 1 Output Bit
+&124 constant AC3ECON \
+ $20 constant AC3ECON_AC3OI \ Analog Comparator Ouput Invert
+ $10 constant AC3ECON_AC3OE \ Analog Comparator Ouput Enable
+ $07 constant AC3ECON_AC3H \ Analog Comparator Hysteresis Select
+&123 constant AC2ECON \
+ $20 constant AC2ECON_AC2OI \ Analog Comparator Ouput Invert
+ $10 constant AC2ECON_AC2OE \ Analog Comparator Ouput Enable
+ $07 constant AC2ECON_AC2H \ Analog Comparator Hysteresis Select
+&122 constant AC1ECON \
+ $20 constant AC1ECON_AC1OI \ Analog Comparator Ouput Invert
+ $10 constant AC1ECON_AC1OE \ Analog Comparator Ouput Enable
+ $08 constant AC1ECON_AC1ICE \ Analog Comparator Interrupt Capture Enable
+ $07 constant AC1ECON_AC1H \ Analog Comparator Hysteresis Select
+\ CPU
+&95 constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ $08 constant SREG_V \ Two's Complement Overflow Flag
+ $04 constant SREG_N \ Negative Flag
+ $02 constant SREG_Z \ Zero Flag
+ $01 constant SREG_C \ Carry Flag
+&93 constant SP \ Stack Pointer
+&85 constant MCUCR \ MCU Control Register
+ $10 constant MCUCR_PUD \ Pull-up disable
+ $08 constant MCUCR_RSTDIS \ Reset Pin Disable
+ $04 constant MCUCR_CKRC81 \ Frequency Selection of the Calibrated RC Oscillator
+ $02 constant MCUCR_IVSEL \ Interrupt Vector Select
+ $01 constant MCUCR_IVCE \ Interrupt Vector Change Enable
+&84 constant MCUSR \ MCU Status Register
+ $08 constant MCUSR_WDRF \ Watchdog Reset Flag
+ $04 constant MCUSR_BORF \ Brown-out Reset Flag
+ $02 constant MCUSR_EXTRF \ External Reset Flag
+ $01 constant MCUSR_PORF \ Power-on reset flag
+&136 constant OSCCAL \ Oscillator Calibration Value
+&131 constant CLKPR \
+ $80 constant CLKPR_CLKPCE \
+ $0F constant CLKPR_CLKPS \
+&83 constant SMCR \ Sleep Mode Control Register
+ $0E constant SMCR_SM \ Sleep Mode Select bits
+ $01 constant SMCR_SE \ Sleep Enable
+&59 constant GPIOR2 \ General Purpose IO Register 2
+ $FF constant GPIOR2_GPIOR \ General Purpose IO Register 2 bis
+&58 constant GPIOR1 \ General Purpose IO Register 1
+ $FF constant GPIOR1_GPIOR \ General Purpose IO Register 1 bis
+&57 constant GPIOR0 \ General Purpose IO Register 0
+ $80 constant GPIOR0_GPIOR07 \ General Purpose IO Register 0 bit 7
+ $40 constant GPIOR0_GPIOR06 \ General Purpose IO Register 0 bit 6
+ $20 constant GPIOR0_GPIOR05 \ General Purpose IO Register 0 bit 5
+ $10 constant GPIOR0_GPIOR04 \ General Purpose IO Register 0 bit 4
+ $08 constant GPIOR0_GPIOR03 \ General Purpose IO Register 0 bit 3
+ $04 constant GPIOR0_GPIOR02 \ General Purpose IO Register 0 bit 2
+ $02 constant GPIOR0_GPIOR01 \ General Purpose IO Register 0 bit 1
+ $01 constant GPIOR0_GPIOR00 \ General Purpose IO Register 0 bit 0
+&135 constant PLLCSR \ PLL Control And Status Register
+ $3C constant PLLCSR_PLLF \
+ $02 constant PLLCSR_PLLE \ PLL Enable
+ $01 constant PLLCSR_PLOCK \ PLL Lock Detector
+&134 constant PRR \ Power Reduction Register
+ $80 constant PRR_PRPSC2 \ Power Reduction PSC2
+ $20 constant PRR_PRPSCR \ Power Reduction PSC0
+ $10 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
+ $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
+ $01 constant PRR_PRADC \ Power Reduction ADC
+&132 constant CLKCSR \
+ $80 constant CLKCSR_CLKCCE \ Clock Control Change Enable
+ $10 constant CLKCSR_CLKRDY \ Clock Ready Flag
+ $0F constant CLKCSR_CLKC \ Clock Control
+&133 constant CLKSELR \
+ $40 constant CLKSELR_COUT \ Clock OUT
+ $30 constant CLKSELR_CSUT \ Clock Start up Time
+ $0F constant CLKSELR_CKSEL \ Clock Source Select
+&129 constant BGCCR \ BandGap Current Calibration Register
+ $0F constant BGCCR_BGCC \
+&128 constant BGCRR \ BandGap Resistor Calibration Register
+ $0F constant BGCRR_BGCR \
+\ EEPROM
+&62 constant EEAR \ EEPROM Read/Write Access Bytes
+&61 constant EEDR \ EEPROM Data Register
+&60 constant EECR \ EEPROM Control Register
+ $80 constant EECR_NVMBSY \ None Volatile Busy Memory Busy
+ $40 constant EECR_EEPAGE \ EEPROM Page Access
+ $30 constant EECR_EEPM \ EEPROM Programming Mode
+ $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
+ $04 constant EECR_EEMWE \ EEPROM Master Write Enable
+ $02 constant EECR_EEWE \ EEPROM Write Enable
+ $01 constant EECR_EERE \ EEPROM Read Enable
+\ PSC0
+&104 constant PICR0 \ PSC 0 Input Capture Register
+&99 constant PFRC0B \ PSC 0 Input B Control
+ $80 constant PFRC0B_PCAE0B \ PSC 0 Capture Enable Input Part B
+ $40 constant PFRC0B_PISEL0B \ PSC 0 Input Select for Part B
+ $20 constant PFRC0B_PELEV0B \ PSC 0 Edge Level Selector on Input Part B
+ $10 constant PFRC0B_PFLTE0B \ PSC 0 Filter Enable on Input Part B
+ $0F constant PFRC0B_PRFM0B \ PSC 0 Retrigger and Fault Mode for Part B
+&98 constant PFRC0A \ PSC 0 Input A Control
+ $80 constant PFRC0A_PCAE0A \ PSC 0 Capture Enable Input Part A
+ $40 constant PFRC0A_PISEL0A \ PSC 0 Input Select for Part A
+ $20 constant PFRC0A_PELEV0A \ PSC 0 Edge Level Selector on Input Part A
+ $10 constant PFRC0A_PFLTE0A \ PSC 0 Filter Enable on Input Part A
+ $0F constant PFRC0A_PRFM0A \ PSC 0 Retrigger and Fault Mode for Part A
+&50 constant PCTL0 \ PSC 0 Control Register
+ $C0 constant PCTL0_PPRE0 \ PSC 0 Prescaler Selects
+ $24 constant PCTL0_PBFM0 \ PSC 0 Balance Flank Width Modulation
+ $10 constant PCTL0_PAOC0B \ PSC 0 Asynchronous Output Control B
+ $08 constant PCTL0_PAOC0A \ PSC 0 Asynchronous Output Control A
+ $02 constant PCTL0_PCCYC0 \ PSC0 Complete Cycle
+ $01 constant PCTL0_PRUN0 \ PSC 0 Run
+&49 constant PCNF0 \ PSC 0 Configuration Register
+ $80 constant PCNF0_PFIFTY0 \ PSC 0 Fifty
+ $40 constant PCNF0_PALOCK0 \ PSC 0 Autolock
+ $20 constant PCNF0_PLOCK0 \ PSC 0 Lock
+ $18 constant PCNF0_PMODE0 \ PSC 0 Mode
+ $04 constant PCNF0_POP0 \ PSC 0 Output Polarity
+ $02 constant PCNF0_PCLKSEL0 \ PSC 0 Input Clock Select
+&68 constant OCR0RB \ Output Compare RB Register
+&66 constant OCR0SB \ Output Compare SB Register
+&74 constant OCR0RA \ Output Compare RA Register
+&96 constant OCR0SA \ Output Compare SA Register
+&106 constant PSOC0 \ PSC0 Synchro and Output Configuration
+ $80 constant PSOC0_PISEL0A1 \ PSC Input Select
+ $40 constant PSOC0_PISEL0B1 \ PSC Input Select
+ $30 constant PSOC0_PSYNC0 \ Synchronisation out for ADC selection
+ $04 constant PSOC0_POEN0B \ PSCOUT01 Output Enable
+ $01 constant PSOC0_POEN0A \ PSCOUT00 Output Enable
+&47 constant PIM0 \ PSC0 Interrupt Mask Register
+ $10 constant PIM0_PEVE0B \ External Event B Interrupt Enable
+ $08 constant PIM0_PEVE0A \ External Event A Interrupt Enable
+ $02 constant PIM0_PEOEPE0 \ End of Enhanced Cycle Enable
+ $01 constant PIM0_PEOPE0 \ End of Cycle Interrupt Enable
+&48 constant PIFR0 \ PSC0 Interrupt Flag Register
+ $80 constant PIFR0_POAC0B \ PSC 0 Output A Activity
+ $40 constant PIFR0_POAC0A \ PSC 0 Output A Activity
+ $10 constant PIFR0_PEV0B \ External Event B Interrupt
+ $08 constant PIFR0_PEV0A \ External Event A Interrupt
+ $06 constant PIFR0_PRN0 \ Ramp Number
+ $01 constant PIFR0_PEOP0 \ End of PSC0 Interrupt
+\ PSC2
+&109 constant PICR2H \ PSC 2 Input Capture Register High
+ $80 constant PICR2H_PCST2 \ PSC 2 Capture Software Trigger Bit
+ $0C constant PICR2H_PICR21 \
+ $03 constant PICR2H_PICR2 \
+&108 constant PICR2L \ PSC 2 Input Capture Register Low
+&103 constant PFRC2B \ PSC 2 Input B Control
+ $80 constant PFRC2B_PCAE2B \ PSC 2 Capture Enable Input Part B
+ $40 constant PFRC2B_PISEL2B \ PSC 2 Input Select for Part B
+ $20 constant PFRC2B_PELEV2B \ PSC 2 Edge Level Selector on Input Part B
+ $10 constant PFRC2B_PFLTE2B \ PSC 2 Filter Enable on Input Part B
+ $0F constant PFRC2B_PRFM2B \ PSC 2 Retrigger and Fault Mode for Part B
+&102 constant PFRC2A \ PSC 2 Input B Control
+ $80 constant PFRC2A_PCAE2A \ PSC 2 Capture Enable Input Part A
+ $40 constant PFRC2A_PISEL2A \ PSC 2 Input Select for Part A
+ $20 constant PFRC2A_PELEV2A \ PSC 2 Edge Level Selector on Input Part A
+ $10 constant PFRC2A_PFLTE2A \ PSC 2 Filter Enable on Input Part A
+ $0F constant PFRC2A_PRFM2A \ PSC 2 Retrigger and Fault Mode for Part A
+&54 constant PCTL2 \ PSC 2 Control Register
+ $C0 constant PCTL2_PPRE2 \ PSC 2 Prescaler Selects
+ $20 constant PCTL2_PBFM2 \ Balance Flank Width Modulation
+ $10 constant PCTL2_PAOC2B \ PSC 2 Asynchronous Output Control B
+ $08 constant PCTL2_PAOC2A \ PSC 2 Asynchronous Output Control A
+ $04 constant PCTL2_PARUN2 \ PSC2 Auto Run
+ $02 constant PCTL2_PCCYC2 \ PSC2 Complete Cycle
+ $01 constant PCTL2_PRUN2 \ PSC 2 Run
+&53 constant PCNF2 \ PSC 2 Configuration Register
+ $80 constant PCNF2_PFIFTY2 \ PSC 2 Fifty
+ $40 constant PCNF2_PALOCK2 \ PSC 2 Autolock
+ $20 constant PCNF2_PLOCK2 \ PSC 2 Lock
+ $18 constant PCNF2_PMODE2 \ PSC 2 Mode
+ $04 constant PCNF2_POP2 \ PSC 2 Output Polarity
+ $02 constant PCNF2_PCLKSEL2 \ PSC 2 Input Clock Select
+ $01 constant PCNF2_POME2 \ PSC 2 Output Matrix Enable
+&112 constant PCNFE2 \ PSC 2 Enhanced Configuration Register
+ $E0 constant PCNFE2_PASDLK2 \
+ $10 constant PCNFE2_PBFM21 \
+ $08 constant PCNFE2_PELEV2A1 \
+ $04 constant PCNFE2_PELEV2B1 \
+ $02 constant PCNFE2_PISEL2A1 \
+ $01 constant PCNFE2_PISEL2B1 \
+&72 constant OCR2RB \ Output Compare RB Register
+&70 constant OCR2SB \ Output Compare SB Register
+&78 constant OCR2RA \ Output Compare RA Register
+&100 constant OCR2SA \ Output Compare SA Register
+&111 constant POM2 \ PSC 2 Output Matrix
+ $F0 constant POM2_POMV2B \ Output Matrix Output B Ramps
+ $0F constant POM2_POMV2A \ Output Matrix Output A Ramps
+&110 constant PSOC2 \ PSC2 Synchro and Output Configuration
+ $C0 constant PSOC2_POS2 \ PSC 2 Output 23 Select
+ $30 constant PSOC2_PSYNC2 \ Synchronization Out for ADC Selection
+ $08 constant PSOC2_POEN2D \ PSCOUT23 Output Enable
+ $04 constant PSOC2_POEN2B \ PSCOUT21 Output Enable
+ $02 constant PSOC2_POEN2C \ PSCOUT22 Output Enable
+ $01 constant PSOC2_POEN2A \ PSCOUT20 Output Enable
+&51 constant PIM2 \ PSC2 Interrupt Mask Register
+ $20 constant PIM2_PSEIE2 \ PSC 2 Synchro Error Interrupt Enable
+ $10 constant PIM2_PEVE2B \ External Event B Interrupt Enable
+ $08 constant PIM2_PEVE2A \ External Event A Interrupt Enable
+ $02 constant PIM2_PEOEPE2 \ End of Enhanced Cycle Interrupt Enable
+ $01 constant PIM2_PEOPE2 \ End of Cycle Interrupt Enable
+&52 constant PIFR2 \ PSC2 Interrupt Flag Register
+ $80 constant PIFR2_POAC2B \ PSC 2 Output A Activity
+ $40 constant PIFR2_POAC2A \ PSC 2 Output A Activity
+ $20 constant PIFR2_PSEI2 \ PSC 2 Synchro Error Interrupt
+ $10 constant PIFR2_PEV2B \ External Event B Interrupt
+ $08 constant PIFR2_PEV2A \ External Event A Interrupt
+ $06 constant PIFR2_PRN2 \ Ramp Number
+ $01 constant PIFR2_PEOP2 \ End of PSC2 Interrupt
+&113 constant PASDLY2 \ Analog Synchronization Delay Register
+\ TIMER_COUNTER_1
+&33 constant TIMSK1 \ Timer/Counter Interrupt Mask Register
+ $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
+ $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
+&34 constant TIFR1 \ Timer/Counter Interrupt Flag register
+ $20 constant TIFR1_ICF1 \ Input Capture Flag 1
+ $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
+&138 constant TCCR1B \ Timer/Counter1 Control Register B
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ $10 constant TCCR1B_WGM13 \ Waveform Generation Mode
+ $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
+&90 constant TCNT1 \ Timer/Counter1 Bytes
+&140 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
+\ BOOT_LOAD
+&87 constant SPMCSR \ Store Program Memory Control Register
+ $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
+ $20 constant SPMCSR_SIGRD \ Signature Row Read
+ $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
+ $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
+ $04 constant SPMCSR_PGWRT \ Page Write
+ $02 constant SPMCSR_PGERS \ Page Erase
+ $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
+
+\ Interrupts
+&1 constant PSC2_CAPTAddr \ PSC2 Capture Event
+&2 constant PSC2_ECAddr \ PSC2 End Cycle
+&3 constant PSC2_EECAddr \ PSC2 End Of Enhanced Cycle
+&4 constant PSC0_CAPTAddr \ PSC0 Capture Event
+&5 constant PSC0_ECAddr \ PSC0 End Cycle
+&6 constant PSC0_EECAddr \ PSC0 End Of Enhanced Cycle
+&7 constant ANALOG_COMP_1Addr \ Analog Comparator 1
+&8 constant ANALOG_COMP_2Addr \ Analog Comparator 2
+&9 constant ANALOG_COMP_3Addr \ Analog Comparator 3
+&10 constant INT0Addr \ External Interrupt Request 0
+&11 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+&12 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+&13 constant ADCAddr \ ADC Conversion Complete
+&14 constant INT1Addr \ External Interrupt Request 1
+&15 constant SPI__STCAddr \ SPI Serial Transfer Complet
+&16 constant INT2Addr \ External Interrupt Request 2
+&17 constant WDTAddr \ Watchdog Timeout Interrupt
+&18 constant EE_READYAddr \ EEPROM Ready
+&19 constant SPM_READYAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/at90pwm81/device.asm b/amforth-6.5/avr8/devices/at90pwm81/device.asm
new file mode 100644
index 0000000..b836c8e
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90pwm81/device.asm
@@ -0,0 +1,96 @@
+; Partname: AT90PWM81
+; generated automatically, do not edit
+
+.nolist
+ .include "pwm81def.inc"
+.list
+
+.equ ramstart = 256
+.equ CELLSIZE = 2
+.macro readflashcell
+ lsl zl
+ rol zh
+ lpm @0, Z+
+ lpm @1, Z+
+.endmacro
+.macro writeflashcell
+ lsl zl
+ rol zh
+.endmacro
+.set WANT_PORTB = 0
+.set WANT_PORTD = 0
+.set WANT_DA_CONVERTER = 0
+.set WANT_PORTE = 0
+.set WANT_SPI = 0
+.set WANT_WATCHDOG = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_AD_CONVERTER = 0
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_CPU = 0
+.set WANT_EEPROM = 0
+.set WANT_PSC0 = 0
+.set WANT_PSC2 = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_BOOT_LOAD = 0
+.equ intvecsize = 1 ; please verify; flash size: 8192 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.org 1
+ rcall isr ; PSC2 Capture Event
+.org 2
+ rcall isr ; PSC2 End Cycle
+.org 3
+ rcall isr ; PSC2 End Of Enhanced Cycle
+.org 4
+ rcall isr ; PSC0 Capture Event
+.org 5
+ rcall isr ; PSC0 End Cycle
+.org 6
+ rcall isr ; PSC0 End Of Enhanced Cycle
+.org 7
+ rcall isr ; Analog Comparator 1
+.org 8
+ rcall isr ; Analog Comparator 2
+.org 9
+ rcall isr ; Analog Comparator 3
+.org 10
+ rcall isr ; External Interrupt Request 0
+.org 11
+ rcall isr ; Timer/Counter1 Capture Event
+.org 12
+ rcall isr ; Timer/Counter1 Overflow
+.org 13
+ rcall isr ; ADC Conversion Complete
+.org 14
+ rcall isr ; External Interrupt Request 1
+.org 15
+ rcall isr ; SPI Serial Transfer Complet
+.org 16
+ rcall isr ; External Interrupt Request 2
+.org 17
+ rcall isr ; Watchdog Timeout Interrupt
+.org 18
+ rcall isr ; EEPROM Ready
+.org 19
+ rcall isr ; Store Program Memory Read
+.equ INTVECTORS = 20
+.nooverlap
+
+; compatability layer (maybe empty)
+.equ EEPE = EEWE
+.equ EEMPE = EEMWE
+
+; controller data area, environment query mcu-info
+mcu_info:
+mcu_ramsize:
+ .dw 256
+mcu_eepromsize:
+ .dw 512
+mcu_maxdp:
+ .dw 6144
+mcu_numints:
+ .dw 20
+mcu_name:
+ .dw 9
+ .db "AT90PWM81",0
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/at90pwm81/device.inc b/amforth-6.5/avr8/devices/at90pwm81/device.inc
new file mode 100644
index 0000000..64c1370
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90pwm81/device.inc
@@ -0,0 +1,1080 @@
+; Partname: AT90PWM81
+; generated automatically, no not edit
+
+.if WANT_PORTB == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw 37
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw 36
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw 35
+
+.endif
+.if WANT_PORTD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw 43
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw 42
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw 41
+
+.endif
+.if WANT_DA_CONVERTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; DAC Data Register High Byte
+VE_DACH:
+ .dw $ff04
+ .db "DACH"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DACH
+XT_DACH:
+ .dw PFA_DOVARIABLE
+PFA_DACH:
+ .dw 89
+; ( -- addr ) System Constant
+; R( -- )
+; DAC Data Register Low Byte
+VE_DACL:
+ .dw $ff04
+ .db "DACL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DACL
+XT_DACL:
+ .dw PFA_DOVARIABLE
+PFA_DACL:
+ .dw 88
+; ( -- addr ) System Constant
+; R( -- )
+; DAC Control Register
+VE_DACON:
+ .dw $ff05
+ .db "DACON",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DACON
+XT_DACON:
+ .dw PFA_DOVARIABLE
+PFA_DACON:
+ .dw 118
+
+.endif
+.if WANT_PORTE == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port E Data Register
+VE_PORTE:
+ .dw $ff05
+ .db "PORTE",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTE
+XT_PORTE:
+ .dw PFA_DOVARIABLE
+PFA_PORTE:
+ .dw 46
+; ( -- addr ) System Constant
+; R( -- )
+; Port E Data Direction Register
+VE_DDRE:
+ .dw $ff04
+ .db "DDRE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRE
+XT_DDRE:
+ .dw PFA_DOVARIABLE
+PFA_DDRE:
+ .dw 45
+; ( -- addr ) System Constant
+; R( -- )
+; Port E Input Pins
+VE_PINE:
+ .dw $ff04
+ .db "PINE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINE
+XT_PINE:
+ .dw PFA_DOVARIABLE
+PFA_PINE:
+ .dw 44
+
+.endif
+.if WANT_SPI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR:
+ .dw $ff04
+ .db "SPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR
+XT_SPCR:
+ .dw PFA_DOVARIABLE
+PFA_SPCR:
+ .dw 55
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR:
+ .dw $ff04
+ .db "SPSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR
+XT_SPSR:
+ .dw PFA_DOVARIABLE
+PFA_SPSR:
+ .dw 56
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR:
+ .dw $ff04
+ .db "SPDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR
+XT_SPDR:
+ .dw PFA_DOVARIABLE
+PFA_SPDR:
+ .dw 86
+
+.endif
+.if WANT_WATCHDOG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCSR:
+ .dw $ff06
+ .db "WDTCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCSR
+XT_WDTCSR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCSR:
+ .dw 130
+
+.endif
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register A
+VE_EICRA:
+ .dw $ff05
+ .db "EICRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRA
+XT_EICRA:
+ .dw PFA_DOVARIABLE
+PFA_EICRA:
+ .dw 137
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Mask Register
+VE_EIMSK:
+ .dw $ff05
+ .db "EIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIMSK
+XT_EIMSK:
+ .dw PFA_DOVARIABLE
+PFA_EIMSK:
+ .dw 65
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Flag Register
+VE_EIFR:
+ .dw $ff04
+ .db "EIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIFR
+XT_EIFR:
+ .dw PFA_DOVARIABLE
+PFA_EIFR:
+ .dw 64
+
+.endif
+.if WANT_AD_CONVERTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC multiplexer Selection Register
+VE_ADMUX:
+ .dw $ff05
+ .db "ADMUX",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADMUX
+XT_ADMUX:
+ .dw PFA_DOVARIABLE
+PFA_ADMUX:
+ .dw 40
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register
+VE_ADCSRA:
+ .dw $ff06
+ .db "ADCSRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRA
+XT_ADCSRA:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRA:
+ .dw 38
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register Bytes
+VE_ADC:
+ .dw $ff03
+ .db "ADC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADC
+XT_ADC:
+ .dw PFA_DOVARIABLE
+PFA_ADC:
+ .dw 76
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Control and Status Register B
+VE_ADCSRB:
+ .dw $ff06
+ .db "ADCSRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRB
+XT_ADCSRB:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRB:
+ .dw 39
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 0
+VE_DIDR0:
+ .dw $ff05
+ .db "DIDR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR0
+XT_DIDR0:
+ .dw PFA_DOVARIABLE
+PFA_DIDR0:
+ .dw 119
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 0
+VE_DIDR1:
+ .dw $ff05
+ .db "DIDR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR1
+XT_DIDR1:
+ .dw PFA_DOVARIABLE
+PFA_DIDR1:
+ .dw 120
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_AMP0CSR:
+ .dw $ff07
+ .db "AMP0CSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_AMP0CSR
+XT_AMP0CSR:
+ .dw PFA_DOVARIABLE
+PFA_AMP0CSR:
+ .dw 121
+
+.endif
+.if WANT_ANALOG_COMPARATOR == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator3 Control Register
+VE_AC3CON:
+ .dw $ff06
+ .db "AC3CON"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_AC3CON
+XT_AC3CON:
+ .dw PFA_DOVARIABLE
+PFA_AC3CON:
+ .dw 127
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator 1 Control Register
+VE_AC1CON:
+ .dw $ff06
+ .db "AC1CON"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_AC1CON
+XT_AC1CON:
+ .dw PFA_DOVARIABLE
+PFA_AC1CON:
+ .dw 125
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator 2 Control Register
+VE_AC2CON:
+ .dw $ff06
+ .db "AC2CON"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_AC2CON
+XT_AC2CON:
+ .dw PFA_DOVARIABLE
+PFA_AC2CON:
+ .dw 126
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw 32
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_AC3ECON:
+ .dw $ff07
+ .db "AC3ECON",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_AC3ECON
+XT_AC3ECON:
+ .dw PFA_DOVARIABLE
+PFA_AC3ECON:
+ .dw 124
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_AC2ECON:
+ .dw $ff07
+ .db "AC2ECON",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_AC2ECON
+XT_AC2ECON:
+ .dw PFA_DOVARIABLE
+PFA_AC2ECON:
+ .dw 123
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_AC1ECON:
+ .dw $ff07
+ .db "AC1ECON",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_AC1ECON
+XT_AC1ECON:
+ .dw PFA_DOVARIABLE
+PFA_AC1ECON:
+ .dw 122
+
+.endif
+.if WANT_CPU == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw 95
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer
+VE_SP:
+ .dw $ff02
+ .db "SP"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SP
+XT_SP:
+ .dw PFA_DOVARIABLE
+PFA_SP:
+ .dw 93
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw 85
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Status Register
+VE_MCUSR:
+ .dw $ff05
+ .db "MCUSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUSR
+XT_MCUSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUSR:
+ .dw 84
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Calibration Value
+VE_OSCCAL:
+ .dw $ff06
+ .db "OSCCAL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSCCAL
+XT_OSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_OSCCAL:
+ .dw 136
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_CLKPR:
+ .dw $ff05
+ .db "CLKPR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKPR
+XT_CLKPR:
+ .dw PFA_DOVARIABLE
+PFA_CLKPR:
+ .dw 131
+; ( -- addr ) System Constant
+; R( -- )
+; Sleep Mode Control Register
+VE_SMCR:
+ .dw $ff04
+ .db "SMCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SMCR
+XT_SMCR:
+ .dw PFA_DOVARIABLE
+PFA_SMCR:
+ .dw 83
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 2
+VE_GPIOR2:
+ .dw $ff06
+ .db "GPIOR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR2
+XT_GPIOR2:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR2:
+ .dw 59
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 1
+VE_GPIOR1:
+ .dw $ff06
+ .db "GPIOR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR1
+XT_GPIOR1:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR1:
+ .dw 58
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 0
+VE_GPIOR0:
+ .dw $ff06
+ .db "GPIOR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR0
+XT_GPIOR0:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR0:
+ .dw 57
+; ( -- addr ) System Constant
+; R( -- )
+; PLL Control And Status Register
+VE_PLLCSR:
+ .dw $ff06
+ .db "PLLCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PLLCSR
+XT_PLLCSR:
+ .dw PFA_DOVARIABLE
+PFA_PLLCSR:
+ .dw 135
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register
+VE_PRR:
+ .dw $ff03
+ .db "PRR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR
+XT_PRR:
+ .dw PFA_DOVARIABLE
+PFA_PRR:
+ .dw 134
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_CLKCSR:
+ .dw $ff06
+ .db "CLKCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKCSR
+XT_CLKCSR:
+ .dw PFA_DOVARIABLE
+PFA_CLKCSR:
+ .dw 132
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_CLKSELR:
+ .dw $ff07
+ .db "CLKSELR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKSELR
+XT_CLKSELR:
+ .dw PFA_DOVARIABLE
+PFA_CLKSELR:
+ .dw 133
+; ( -- addr ) System Constant
+; R( -- )
+; BandGap Current Calibration Register
+VE_BGCCR:
+ .dw $ff05
+ .db "BGCCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_BGCCR
+XT_BGCCR:
+ .dw PFA_DOVARIABLE
+PFA_BGCCR:
+ .dw 129
+; ( -- addr ) System Constant
+; R( -- )
+; BandGap Resistor Calibration Register
+VE_BGCRR:
+ .dw $ff05
+ .db "BGCRR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_BGCRR
+XT_BGCRR:
+ .dw PFA_DOVARIABLE
+PFA_BGCRR:
+ .dw 128
+
+.endif
+.if WANT_EEPROM == 1
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Read/Write Access Bytes
+VE_EEAR:
+ .dw $ff04
+ .db "EEAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEAR
+XT_EEAR:
+ .dw PFA_DOVARIABLE
+PFA_EEAR:
+ .dw 62
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw 61
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw 60
+
+.endif
+.if WANT_PSC0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 0 Input Capture Register
+VE_PICR0:
+ .dw $ff05
+ .db "PICR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PICR0
+XT_PICR0:
+ .dw PFA_DOVARIABLE
+PFA_PICR0:
+ .dw 104
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 0 Input B Control
+VE_PFRC0B:
+ .dw $ff06
+ .db "PFRC0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PFRC0B
+XT_PFRC0B:
+ .dw PFA_DOVARIABLE
+PFA_PFRC0B:
+ .dw 99
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 0 Input A Control
+VE_PFRC0A:
+ .dw $ff06
+ .db "PFRC0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PFRC0A
+XT_PFRC0A:
+ .dw PFA_DOVARIABLE
+PFA_PFRC0A:
+ .dw 98
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 0 Control Register
+VE_PCTL0:
+ .dw $ff05
+ .db "PCTL0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCTL0
+XT_PCTL0:
+ .dw PFA_DOVARIABLE
+PFA_PCTL0:
+ .dw 50
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 0 Configuration Register
+VE_PCNF0:
+ .dw $ff05
+ .db "PCNF0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCNF0
+XT_PCNF0:
+ .dw PFA_DOVARIABLE
+PFA_PCNF0:
+ .dw 49
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare RB Register
+VE_OCR0RB:
+ .dw $ff06
+ .db "OCR0RB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0RB
+XT_OCR0RB:
+ .dw PFA_DOVARIABLE
+PFA_OCR0RB:
+ .dw 68
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare SB Register
+VE_OCR0SB:
+ .dw $ff06
+ .db "OCR0SB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0SB
+XT_OCR0SB:
+ .dw PFA_DOVARIABLE
+PFA_OCR0SB:
+ .dw 66
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare RA Register
+VE_OCR0RA:
+ .dw $ff06
+ .db "OCR0RA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0RA
+XT_OCR0RA:
+ .dw PFA_DOVARIABLE
+PFA_OCR0RA:
+ .dw 74
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare SA Register
+VE_OCR0SA:
+ .dw $ff06
+ .db "OCR0SA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0SA
+XT_OCR0SA:
+ .dw PFA_DOVARIABLE
+PFA_OCR0SA:
+ .dw 96
+; ( -- addr ) System Constant
+; R( -- )
+; PSC0 Synchro and Output Configuration
+VE_PSOC0:
+ .dw $ff05
+ .db "PSOC0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PSOC0
+XT_PSOC0:
+ .dw PFA_DOVARIABLE
+PFA_PSOC0:
+ .dw 106
+; ( -- addr ) System Constant
+; R( -- )
+; PSC0 Interrupt Mask Register
+VE_PIM0:
+ .dw $ff04
+ .db "PIM0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIM0
+XT_PIM0:
+ .dw PFA_DOVARIABLE
+PFA_PIM0:
+ .dw 47
+; ( -- addr ) System Constant
+; R( -- )
+; PSC0 Interrupt Flag Register
+VE_PIFR0:
+ .dw $ff05
+ .db "PIFR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIFR0
+XT_PIFR0:
+ .dw PFA_DOVARIABLE
+PFA_PIFR0:
+ .dw 48
+
+.endif
+.if WANT_PSC2 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 2 Input Capture Register High
+VE_PICR2H:
+ .dw $ff06
+ .db "PICR2H"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PICR2H
+XT_PICR2H:
+ .dw PFA_DOVARIABLE
+PFA_PICR2H:
+ .dw 109
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 2 Input Capture Register Low
+VE_PICR2L:
+ .dw $ff06
+ .db "PICR2L"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PICR2L
+XT_PICR2L:
+ .dw PFA_DOVARIABLE
+PFA_PICR2L:
+ .dw 108
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 2 Input B Control
+VE_PFRC2B:
+ .dw $ff06
+ .db "PFRC2B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PFRC2B
+XT_PFRC2B:
+ .dw PFA_DOVARIABLE
+PFA_PFRC2B:
+ .dw 103
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 2 Input B Control
+VE_PFRC2A:
+ .dw $ff06
+ .db "PFRC2A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PFRC2A
+XT_PFRC2A:
+ .dw PFA_DOVARIABLE
+PFA_PFRC2A:
+ .dw 102
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 2 Control Register
+VE_PCTL2:
+ .dw $ff05
+ .db "PCTL2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCTL2
+XT_PCTL2:
+ .dw PFA_DOVARIABLE
+PFA_PCTL2:
+ .dw 54
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 2 Configuration Register
+VE_PCNF2:
+ .dw $ff05
+ .db "PCNF2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCNF2
+XT_PCNF2:
+ .dw PFA_DOVARIABLE
+PFA_PCNF2:
+ .dw 53
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 2 Enhanced Configuration Register
+VE_PCNFE2:
+ .dw $ff06
+ .db "PCNFE2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCNFE2
+XT_PCNFE2:
+ .dw PFA_DOVARIABLE
+PFA_PCNFE2:
+ .dw 112
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare RB Register
+VE_OCR2RB:
+ .dw $ff06
+ .db "OCR2RB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2RB
+XT_OCR2RB:
+ .dw PFA_DOVARIABLE
+PFA_OCR2RB:
+ .dw 72
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare SB Register
+VE_OCR2SB:
+ .dw $ff06
+ .db "OCR2SB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2SB
+XT_OCR2SB:
+ .dw PFA_DOVARIABLE
+PFA_OCR2SB:
+ .dw 70
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare RA Register
+VE_OCR2RA:
+ .dw $ff06
+ .db "OCR2RA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2RA
+XT_OCR2RA:
+ .dw PFA_DOVARIABLE
+PFA_OCR2RA:
+ .dw 78
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare SA Register
+VE_OCR2SA:
+ .dw $ff06
+ .db "OCR2SA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2SA
+XT_OCR2SA:
+ .dw PFA_DOVARIABLE
+PFA_OCR2SA:
+ .dw 100
+; ( -- addr ) System Constant
+; R( -- )
+; PSC 2 Output Matrix
+VE_POM2:
+ .dw $ff04
+ .db "POM2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_POM2
+XT_POM2:
+ .dw PFA_DOVARIABLE
+PFA_POM2:
+ .dw 111
+; ( -- addr ) System Constant
+; R( -- )
+; PSC2 Synchro and Output Configuration
+VE_PSOC2:
+ .dw $ff05
+ .db "PSOC2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PSOC2
+XT_PSOC2:
+ .dw PFA_DOVARIABLE
+PFA_PSOC2:
+ .dw 110
+; ( -- addr ) System Constant
+; R( -- )
+; PSC2 Interrupt Mask Register
+VE_PIM2:
+ .dw $ff04
+ .db "PIM2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIM2
+XT_PIM2:
+ .dw PFA_DOVARIABLE
+PFA_PIM2:
+ .dw 51
+; ( -- addr ) System Constant
+; R( -- )
+; PSC2 Interrupt Flag Register
+VE_PIFR2:
+ .dw $ff05
+ .db "PIFR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIFR2
+XT_PIFR2:
+ .dw PFA_DOVARIABLE
+PFA_PIFR2:
+ .dw 52
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Synchronization Delay Register
+VE_PASDLY2:
+ .dw $ff07
+ .db "PASDLY2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PASDLY2
+XT_PASDLY2:
+ .dw PFA_DOVARIABLE
+PFA_PASDLY2:
+ .dw 113
+
+.endif
+.if WANT_TIMER_COUNTER_1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Mask Register
+VE_TIMSK1:
+ .dw $ff06
+ .db "TIMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK1
+XT_TIMSK1:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK1:
+ .dw 33
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Flag register
+VE_TIFR1:
+ .dw $ff05
+ .db "TIFR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR1
+XT_TIFR1:
+ .dw PFA_DOVARIABLE
+PFA_TIFR1:
+ .dw 34
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw 138
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Bytes
+VE_TCNT1:
+ .dw $ff05
+ .db "TCNT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1
+XT_TCNT1:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1:
+ .dw 90
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Bytes
+VE_ICR1:
+ .dw $ff04
+ .db "ICR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1
+XT_ICR1:
+ .dw PFA_DOVARIABLE
+PFA_ICR1:
+ .dw 140
+
+.endif
+.if WANT_BOOT_LOAD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control Register
+VE_SPMCSR:
+ .dw $ff06
+ .db "SPMCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCSR
+XT_SPMCSR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCSR:
+ .dw 87
+
+.endif
diff --git a/amforth-6.5/avr8/devices/at90pwm81/device.py b/amforth-6.5/avr8/devices/at90pwm81/device.py
new file mode 100644
index 0000000..853ac3a
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90pwm81/device.py
@@ -0,0 +1,389 @@
+# Generated Automatically
+
+# Partname AT90PWM81
+
+MCUREGS = {
+# Interrupt Vectors
+ 'PSC2_CAPTAddr' : '#2', # PSC2 Capture Event
+ 'PSC2_ECAddr' : '#4', # PSC2 End Cycle
+ 'PSC2_EECAddr' : '#6', # PSC2 End Of Enhanced Cycle
+ 'PSC0_CAPTAddr' : '#8', # PSC0 Capture Event
+ 'PSC0_ECAddr' : '#10', # PSC0 End Cycle
+ 'PSC0_EECAddr' : '#12', # PSC0 End Of Enhanced Cycle
+ 'ANALOG_COMP_1Addr' : '#14', # Analog Comparator 1
+ 'ANALOG_COMP_2Addr' : '#16', # Analog Comparator 2
+ 'ANALOG_COMP_3Addr' : '#18', # Analog Comparator 3
+ 'INT0Addr' : '#20', # External Interrupt Request 0
+ 'TIMER1_CAPTAddr' : '#22', # Timer/Counter1 Capture Event
+ 'TIMER1_OVFAddr' : '#24', # Timer/Counter1 Overflow
+ 'ADCAddr' : '#26', # ADC Conversion Complete
+ 'INT1Addr' : '#28', # External Interrupt Request 1
+ 'SPI_STCAddr' : '#30', # SPI Serial Transfer Complet
+ 'INT2Addr' : '#32', # External Interrupt Request 2
+ 'WDTAddr' : '#34', # Watchdog Timeout Interrupt
+ 'EE_READYAddr' : '#36', # EEPROM Ready
+ 'SPM_READYAddr' : '#38', # Store Program Memory Read
+
+# Module PORTB
+ 'PORTB' : '$25', # Port B Data Register
+ 'DDRB' : '$24', # Port B Data Direction Register
+ 'PINB' : '$23', # Port B Input Pins
+
+# Module PORTD
+ 'PORTD' : '$2b', # Port D Data Register
+ 'DDRD' : '$2a', # Port D Data Direction Register
+ 'PIND' : '$29', # Port D Input Pins
+
+# Module DA_CONVERTER
+ 'DACH' : '$59', # DAC Data Register High Byte
+ 'DACH_DACH': '$ff', # DAC Data Register High Byte Bi
+ 'DACL' : '$58', # DAC Data Register Low Byte
+ 'DACL_DACL': '$ff', # DAC Data Register Low Byte Bit
+ 'DACON' : '$76', # DAC Control Register
+ 'DACON_DAATE': '$80', # DAC Auto Trigger Enable Bit
+ 'DACON_DATS': '$70', # DAC Trigger Selection Bits
+ 'DACON_DALA': '$4', # DAC Left Adjust
+ 'DACON_DAEN': '$1', # DAC Enable Bit
+
+# Module PORTE
+ 'PORTE' : '$2e', # Port E Data Register
+ 'DDRE' : '$2d', # Port E Data Direction Register
+ 'PINE' : '$2c', # Port E Input Pins
+
+# Module SPI
+ 'SPCR' : '$37', # SPI Control Register
+ 'SPCR_SPIE': '$80', # SPI Interrupt Enable
+ 'SPCR_SPE': '$40', # SPI Enable
+ 'SPCR_DORD': '$20', # Data Order
+ 'SPCR_MSTR': '$10', # Master/Slave Select
+ 'SPCR_CPOL': '$8', # Clock polarity
+ 'SPCR_CPHA': '$4', # Clock Phase
+ 'SPCR_SPR': '$3', # SPI Clock Rate Selects
+ 'SPSR' : '$38', # SPI Status Register
+ 'SPSR_SPIF': '$80', # SPI Interrupt Flag
+ 'SPSR_WCOL': '$40', # Write Collision Flag
+ 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
+ 'SPDR' : '$56', # SPI Data Register
+
+# Module WATCHDOG
+ 'WDTCSR' : '$82', # Watchdog Timer Control Registe
+ 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
+ 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
+ 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
+ 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
+ 'WDTCSR_WDE': '$8', # Watch Dog Enable
+
+# Module EXTERNAL_INTERRUPT
+ 'EICRA' : '$89', # External Interrupt Control Reg
+ 'EICRA_ISC2': '$30', # External Interrupt Sense Contr
+ 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
+ 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
+ 'EIMSK' : '$41', # External Interrupt Mask Regist
+ 'EIMSK_INT': '$7', # External Interrupt Request 2 E
+ 'EIFR' : '$40', # External Interrupt Flag Regist
+ 'EIFR_INTF': '$7', # External Interrupt Flags
+
+# Module AD_CONVERTER
+ 'ADMUX' : '$28', # The ADC multiplexer Selection
+ 'ADMUX_REFS': '$c0', # Reference Selection Bits
+ 'ADMUX_ADLAR': '$20', # Left Adjust Result
+ 'ADMUX_MUX': '$f', # Analog Channel and Gain Select
+ 'ADCSRA' : '$26', # The ADC Control and Status reg
+ 'ADCSRA_ADEN': '$80', # ADC Enable
+ 'ADCSRA_ADSC': '$40', # ADC Start Conversion
+ 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
+ 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
+ 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
+ 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
+ 'ADC' : '$4c', # ADC Data Register Bytes
+ 'ADCSRB' : '$27', # ADC Control and Status Registe
+ 'ADCSRB_ADHSM': '$80', # ADC High Speed Mode
+ 'ADCSRB_ADNCDIS': '$40', # ADC Noise Canceller Disable
+ 'ADCSRB_ADSSEN': '$10', # ADC Single Shot Enable on PSC'
+ 'ADCSRB_ADTS': '$f', # ADC Auto Trigger Sources
+ 'DIDR0' : '$77', # Digital Input Disable Register
+ 'DIDR0_ADC7D': '$80', #
+ 'DIDR0_ADC6D': '$40', # ADC7 Digital input Disable
+ 'DIDR0_ADC5D': '$20', # ADC5 Digital input Disable
+ 'DIDR0_ADC4D': '$10', # ADC4 Digital input Disable
+ 'DIDR0_ADC3D': '$8', # ADC3 Digital input Disable
+ 'DIDR0_ADC2D': '$4', # ADC2 Digital input Disable
+ 'DIDR0_ADC1D': '$2', # ADC1 Digital input Disable
+ 'DIDR0_ADC0D': '$1', # ADC0 Digital input Disable
+ 'DIDR1' : '$78', # Digital Input Disable Register
+ 'DIDR1_ACMP1MD': '$8', #
+ 'DIDR1_AMP0POSD': '$4', #
+ 'DIDR1_ADC10D': '$2', #
+ 'DIDR1_ADC9D': '$1', #
+ 'AMP0CSR' : '$79', #
+ 'AMP0CSR_AMP0EN': '$80', #
+ 'AMP0CSR_AMP0IS': '$40', #
+ 'AMP0CSR_AMP0G': '$30', #
+ 'AMP0CSR_AMP0GS': '$8', #
+ 'AMP0CSR_AMP0TS': '$3', #
+
+# Module ANALOG_COMPARATOR
+ 'AC3CON' : '$7f', # Analog Comparator3 Control Reg
+ 'AC3CON_AC3EN': '$80', # Analog Comparator3 Enable Bit
+ 'AC3CON_AC3IE': '$40', # Analog Comparator 3 Interrupt
+ 'AC3CON_AC3IS': '$30', # Analog Comparator 3 Interrupt
+ 'AC3CON_AC3OEA': '$8', # Analog Comparator 3 Alternate
+ 'AC3CON_AC3M': '$7', # Analog Comparator 3 Multiplexe
+ 'AC1CON' : '$7d', # Analog Comparator 1 Control Re
+ 'AC1CON_AC1EN': '$80', # Analog Comparator 1 Enable Bit
+ 'AC1CON_AC1IE': '$40', # Analog Comparator 1 Interrupt
+ 'AC1CON_AC1IS': '$30', # Analog Comparator 1 Interrupt
+ 'AC1CON_AC1M': '$7', # Analog Comparator 1 Multiplexe
+ 'AC2CON' : '$7e', # Analog Comparator 2 Control Re
+ 'AC2CON_AC2EN': '$80', # Analog Comparator 2 Enable Bit
+ 'AC2CON_AC2IE': '$40', # Analog Comparator 2 Interrupt
+ 'AC2CON_AC2IS': '$30', # Analog Comparator 2 Interrupt
+ 'AC2CON_AC2M': '$7', # Analog Comparator 2 Multiplexe
+ 'ACSR' : '$20', # Analog Comparator Status Regis
+ 'ACSR_AC3IF': '$80', # Analog Comparator 3 Interrupt
+ 'ACSR_AC2IF': '$40', # Analog Comparator 2 Interrupt
+ 'ACSR_AC1IF': '$20', # Analog Comparator 1 Interrupt
+ 'ACSR_AC3O': '$8', # Analog Comparator 3 Output Bit
+ 'ACSR_AC2O': '$4', # Analog Comparator 2 Output Bit
+ 'ACSR_AC1O': '$2', # Analog Comparator 1 Output Bit
+ 'AC3ECON' : '$7c', #
+ 'AC3ECON_AC3OI': '$20', # Analog Comparator Ouput Invert
+ 'AC3ECON_AC3OE': '$10', # Analog Comparator Ouput Enable
+ 'AC3ECON_AC3H': '$7', # Analog Comparator Hysteresis S
+ 'AC2ECON' : '$7b', #
+ 'AC2ECON_AC2OI': '$20', # Analog Comparator Ouput Invert
+ 'AC2ECON_AC2OE': '$10', # Analog Comparator Ouput Enable
+ 'AC2ECON_AC2H': '$7', # Analog Comparator Hysteresis S
+ 'AC1ECON' : '$7a', #
+ 'AC1ECON_AC1OI': '$20', # Analog Comparator Ouput Invert
+ 'AC1ECON_AC1OE': '$10', # Analog Comparator Ouput Enable
+ 'AC1ECON_AC1ICE': '$8', # Analog Comparator Interrupt Ca
+ 'AC1ECON_AC1H': '$7', # Analog Comparator Hysteresis S
+
+# Module CPU
+ 'SREG' : '$5f', # Status Register
+ 'SREG_I': '$80', # Global Interrupt Enable
+ 'SREG_T': '$40', # Bit Copy Storage
+ 'SREG_H': '$20', # Half Carry Flag
+ 'SREG_S': '$10', # Sign Bit
+ 'SREG_V': '$8', # Two's Complement Overflow Flag
+ 'SREG_N': '$4', # Negative Flag
+ 'SREG_Z': '$2', # Zero Flag
+ 'SREG_C': '$1', # Carry Flag
+ 'SP' : '$5d', # Stack Pointer
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_PUD': '$10', # Pull-up disable
+ 'MCUCR_RSTDIS': '$8', # Reset Pin Disable
+ 'MCUCR_CKRC81': '$4', # Frequency Selection of the Cal
+ 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
+ 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
+ 'MCUSR_BORF': '$4', # Brown-out Reset Flag
+ 'MCUSR_EXTRF': '$2', # External Reset Flag
+ 'MCUSR_PORF': '$1', # Power-on reset flag
+ 'OSCCAL' : '$88', # Oscillator Calibration Value
+ 'CLKPR' : '$83', #
+ 'CLKPR_CLKPCE': '$80', #
+ 'CLKPR_CLKPS': '$f', #
+ 'SMCR' : '$53', # Sleep Mode Control Register
+ 'SMCR_SM': '$e', # Sleep Mode Select bits
+ 'SMCR_SE': '$1', # Sleep Enable
+ 'GPIOR2' : '$3b', # General Purpose IO Register 2
+ 'GPIOR2_GPIOR': '$ff', # General Purpose IO Register 2
+ 'GPIOR1' : '$3a', # General Purpose IO Register 1
+ 'GPIOR1_GPIOR': '$ff', # General Purpose IO Register 1
+ 'GPIOR0' : '$39', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR07': '$80', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR06': '$40', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR05': '$20', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR04': '$10', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR03': '$8', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR02': '$4', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR01': '$2', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR00': '$1', # General Purpose IO Register 0
+ 'PLLCSR' : '$87', # PLL Control And Status Registe
+ 'PLLCSR_PLLF': '$3c', #
+ 'PLLCSR_PLLE': '$2', # PLL Enable
+ 'PLLCSR_PLOCK': '$1', # PLL Lock Detector
+ 'PRR' : '$86', # Power Reduction Register
+ 'PRR_PRPSC2': '$80', # Power Reduction PSC2
+ 'PRR_PRPSCR': '$20', # Power Reduction PSC0
+ 'PRR_PRTIM1': '$10', # Power Reduction Timer/Counter1
+ 'PRR_PRSPI': '$4', # Power Reduction Serial Periphe
+ 'PRR_PRADC': '$1', # Power Reduction ADC
+ 'CLKCSR' : '$84', #
+ 'CLKCSR_CLKCCE': '$80', # Clock Control Change Enable
+ 'CLKCSR_CLKRDY': '$10', # Clock Ready Flag
+ 'CLKCSR_CLKC': '$f', # Clock Control
+ 'CLKSELR' : '$85', #
+ 'CLKSELR_COUT': '$40', # Clock OUT
+ 'CLKSELR_CSUT': '$30', # Clock Start up Time
+ 'CLKSELR_CKSEL': '$f', # Clock Source Select
+ 'BGCCR' : '$81', # BandGap Current Calibration Re
+ 'BGCCR_BGCC': '$f', #
+ 'BGCRR' : '$80', # BandGap Resistor Calibration R
+ 'BGCRR_BGCR': '$f', #
+
+# Module EEPROM
+ 'EEAR' : '$3e', # EEPROM Read/Write Access Byte
+ 'EEDR' : '$3d', # EEPROM Data Register
+ 'EECR' : '$3c', # EEPROM Control Register
+ 'EECR_NVMBSY': '$80', # None Volatile Busy Memory Busy
+ 'EECR_EEPAGE': '$40', # EEPROM Page Access
+ 'EECR_EEPM': '$30', # EEPROM Programming Mode
+ 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
+ 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
+ 'EECR_EEWE': '$2', # EEPROM Write Enable
+ 'EECR_EERE': '$1', # EEPROM Read Enable
+
+# Module PSC0
+ 'PICR0' : '$68', # PSC 0 Input Capture Register
+ 'PFRC0B' : '$63', # PSC 0 Input B Control
+ 'PFRC0B_PCAE0B': '$80', # PSC 0 Capture Enable Input Par
+ 'PFRC0B_PISEL0B': '$40', # PSC 0 Input Select for Part B
+ 'PFRC0B_PELEV0B': '$20', # PSC 0 Edge Level Selector on I
+ 'PFRC0B_PFLTE0B': '$10', # PSC 0 Filter Enable on Input P
+ 'PFRC0B_PRFM0B': '$f', # PSC 0 Retrigger and Fault Mode
+ 'PFRC0A' : '$62', # PSC 0 Input A Control
+ 'PFRC0A_PCAE0A': '$80', # PSC 0 Capture Enable Input Par
+ 'PFRC0A_PISEL0A': '$40', # PSC 0 Input Select for Part A
+ 'PFRC0A_PELEV0A': '$20', # PSC 0 Edge Level Selector on I
+ 'PFRC0A_PFLTE0A': '$10', # PSC 0 Filter Enable on Input P
+ 'PFRC0A_PRFM0A': '$f', # PSC 0 Retrigger and Fault Mode
+ 'PCTL0' : '$32', # PSC 0 Control Register
+ 'PCTL0_PPRE0': '$c0', # PSC 0 Prescaler Selects
+ 'PCTL0_PBFM0': '$24', # PSC 0 Balance Flank Width Modu
+ 'PCTL0_PAOC0B': '$10', # PSC 0 Asynchronous Output Cont
+ 'PCTL0_PAOC0A': '$8', # PSC 0 Asynchronous Output Cont
+ 'PCTL0_PCCYC0': '$2', # PSC0 Complete Cycle
+ 'PCTL0_PRUN0': '$1', # PSC 0 Run
+ 'PCNF0' : '$31', # PSC 0 Configuration Register
+ 'PCNF0_PFIFTY0': '$80', # PSC 0 Fifty
+ 'PCNF0_PALOCK0': '$40', # PSC 0 Autolock
+ 'PCNF0_PLOCK0': '$20', # PSC 0 Lock
+ 'PCNF0_PMODE0': '$18', # PSC 0 Mode
+ 'PCNF0_POP0': '$4', # PSC 0 Output Polarity
+ 'PCNF0_PCLKSEL0': '$2', # PSC 0 Input Clock Select
+ 'OCR0RB' : '$44', # Output Compare RB Register
+ 'OCR0SB' : '$42', # Output Compare SB Register
+ 'OCR0RA' : '$4a', # Output Compare RA Register
+ 'OCR0SA' : '$60', # Output Compare SA Register
+ 'PSOC0' : '$6a', # PSC0 Synchro and Output Config
+ 'PSOC0_PISEL0A1': '$80', # PSC Input Select
+ 'PSOC0_PISEL0B1': '$40', # PSC Input Select
+ 'PSOC0_PSYNC0': '$30', # Synchronisation out for ADC se
+ 'PSOC0_POEN0B': '$4', # PSCOUT01 Output Enable
+ 'PSOC0_POEN0A': '$1', # PSCOUT00 Output Enable
+ 'PIM0' : '$2f', # PSC0 Interrupt Mask Register
+ 'PIM0_PEVE0B': '$10', # External Event B Interrupt Ena
+ 'PIM0_PEVE0A': '$8', # External Event A Interrupt Ena
+ 'PIM0_PEOEPE0': '$2', # End of Enhanced Cycle Enable
+ 'PIM0_PEOPE0': '$1', # End of Cycle Interrupt Enable
+ 'PIFR0' : '$30', # PSC0 Interrupt Flag Register
+ 'PIFR0_POAC0B': '$80', # PSC 0 Output A Activity
+ 'PIFR0_POAC0A': '$40', # PSC 0 Output A Activity
+ 'PIFR0_PEV0B': '$10', # External Event B Interrupt
+ 'PIFR0_PEV0A': '$8', # External Event A Interrupt
+ 'PIFR0_PRN0': '$6', # Ramp Number
+ 'PIFR0_PEOP0': '$1', # End of PSC0 Interrupt
+
+# Module PSC2
+ 'PICR2H' : '$6d', # PSC 2 Input Capture Register H
+ 'PICR2H_PCST2': '$80', # PSC 2 Capture Software Trigger
+ 'PICR2H_PICR21': '$c', #
+ 'PICR2H_PICR2': '$3', #
+ 'PICR2L' : '$6c', # PSC 2 Input Capture Register L
+ 'PFRC2B' : '$67', # PSC 2 Input B Control
+ 'PFRC2B_PCAE2B': '$80', # PSC 2 Capture Enable Input Par
+ 'PFRC2B_PISEL2B': '$40', # PSC 2 Input Select for Part B
+ 'PFRC2B_PELEV2B': '$20', # PSC 2 Edge Level Selector on I
+ 'PFRC2B_PFLTE2B': '$10', # PSC 2 Filter Enable on Input P
+ 'PFRC2B_PRFM2B': '$f', # PSC 2 Retrigger and Fault Mode
+ 'PFRC2A' : '$66', # PSC 2 Input B Control
+ 'PFRC2A_PCAE2A': '$80', # PSC 2 Capture Enable Input Par
+ 'PFRC2A_PISEL2A': '$40', # PSC 2 Input Select for Part A
+ 'PFRC2A_PELEV2A': '$20', # PSC 2 Edge Level Selector on I
+ 'PFRC2A_PFLTE2A': '$10', # PSC 2 Filter Enable on Input P
+ 'PFRC2A_PRFM2A': '$f', # PSC 2 Retrigger and Fault Mode
+ 'PCTL2' : '$36', # PSC 2 Control Register
+ 'PCTL2_PPRE2': '$c0', # PSC 2 Prescaler Selects
+ 'PCTL2_PBFM2': '$20', # Balance Flank Width Modulation
+ 'PCTL2_PAOC2B': '$10', # PSC 2 Asynchronous Output Cont
+ 'PCTL2_PAOC2A': '$8', # PSC 2 Asynchronous Output Cont
+ 'PCTL2_PARUN2': '$4', # PSC2 Auto Run
+ 'PCTL2_PCCYC2': '$2', # PSC2 Complete Cycle
+ 'PCTL2_PRUN2': '$1', # PSC 2 Run
+ 'PCNF2' : '$35', # PSC 2 Configuration Register
+ 'PCNF2_PFIFTY2': '$80', # PSC 2 Fifty
+ 'PCNF2_PALOCK2': '$40', # PSC 2 Autolock
+ 'PCNF2_PLOCK2': '$20', # PSC 2 Lock
+ 'PCNF2_PMODE2': '$18', # PSC 2 Mode
+ 'PCNF2_POP2': '$4', # PSC 2 Output Polarity
+ 'PCNF2_PCLKSEL2': '$2', # PSC 2 Input Clock Select
+ 'PCNF2_POME2': '$1', # PSC 2 Output Matrix Enable
+ 'PCNFE2' : '$70', # PSC 2 Enhanced Configuration R
+ 'PCNFE2_PASDLK2': '$e0', #
+ 'PCNFE2_PBFM21': '$10', #
+ 'PCNFE2_PELEV2A1': '$8', #
+ 'PCNFE2_PELEV2B1': '$4', #
+ 'PCNFE2_PISEL2A1': '$2', #
+ 'PCNFE2_PISEL2B1': '$1', #
+ 'OCR2RB' : '$48', # Output Compare RB Register
+ 'OCR2SB' : '$46', # Output Compare SB Register
+ 'OCR2RA' : '$4e', # Output Compare RA Register
+ 'OCR2SA' : '$64', # Output Compare SA Register
+ 'POM2' : '$6f', # PSC 2 Output Matrix
+ 'POM2_POMV2B': '$f0', # Output Matrix Output B Ramps
+ 'POM2_POMV2A': '$f', # Output Matrix Output A Ramps
+ 'PSOC2' : '$6e', # PSC2 Synchro and Output Config
+ 'PSOC2_POS2': '$c0', # PSC 2 Output 23 Select
+ 'PSOC2_PSYNC2': '$30', # Synchronization Out for ADC Se
+ 'PSOC2_POEN2D': '$8', # PSCOUT23 Output Enable
+ 'PSOC2_POEN2B': '$4', # PSCOUT21 Output Enable
+ 'PSOC2_POEN2C': '$2', # PSCOUT22 Output Enable
+ 'PSOC2_POEN2A': '$1', # PSCOUT20 Output Enable
+ 'PIM2' : '$33', # PSC2 Interrupt Mask Register
+ 'PIM2_PSEIE2': '$20', # PSC 2 Synchro Error Interrupt
+ 'PIM2_PEVE2B': '$10', # External Event B Interrupt Ena
+ 'PIM2_PEVE2A': '$8', # External Event A Interrupt Ena
+ 'PIM2_PEOEPE2': '$2', # End of Enhanced Cycle Interrup
+ 'PIM2_PEOPE2': '$1', # End of Cycle Interrupt Enable
+ 'PIFR2' : '$34', # PSC2 Interrupt Flag Register
+ 'PIFR2_POAC2B': '$80', # PSC 2 Output A Activity
+ 'PIFR2_POAC2A': '$40', # PSC 2 Output A Activity
+ 'PIFR2_PSEI2': '$20', # PSC 2 Synchro Error Interrupt
+ 'PIFR2_PEV2B': '$10', # External Event B Interrupt
+ 'PIFR2_PEV2A': '$8', # External Event A Interrupt
+ 'PIFR2_PRN2': '$6', # Ramp Number
+ 'PIFR2_PEOP2': '$1', # End of PSC2 Interrupt
+ 'PASDLY2' : '$71', # Analog Synchronization Delay R
+
+# Module TIMER_COUNTER_1
+ 'TIMSK1' : '$21', # Timer/Counter Interrupt Mask R
+ 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
+ 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
+ 'TIFR1' : '$22', # Timer/Counter Interrupt Flag r
+ 'TIFR1_ICF1': '$20', # Input Capture Flag 1
+ 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
+ 'TCCR1B' : '$8a', # Timer/Counter1 Control Registe
+ 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
+ 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
+ 'TCCR1B_WGM13': '$10', # Waveform Generation Mode
+ 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
+ 'TCNT1' : '$5a', # Timer/Counter1 Bytes
+ 'ICR1' : '$8c', # Timer/Counter1 Input Capture R
+
+# Module BOOT_LOAD
+ 'SPMCSR' : '$57', # Store Program Memory Control R
+ 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
+ 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
+ 'SPMCSR_SIGRD': '$20', # Signature Row Read
+ 'SPMCSR_RWWSRE': '$10', # Read While Write section read
+ 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
+ 'SPMCSR_PGWRT': '$4', # Page Write
+ 'SPMCSR_PGERS': '$2', # Page Erase
+ 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
+
+ '__amforth_dummy':'0'
+}
diff --git a/amforth-6.5/avr8/devices/at90pwm81/words/no-jtag.asm b/amforth-6.5/avr8/devices/at90pwm81/words/no-jtag.asm
new file mode 100644
index 0000000..352a4bb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90pwm81/words/no-jtag.asm
@@ -0,0 +1,14 @@
+; ( -- )
+; ( -- )
+; MCU
+; disable jtag at runtime
+VE_NOJTAG:
+ .dw $FF05
+ .db "-jtag",0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOJTAG
+XT_NOJTAG:
+ .dw PFA_NOJTAG
+PFA_NOJTAG:
+
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/at90pwm81/words/no-wdt.asm b/amforth-6.5/avr8/devices/at90pwm81/words/no-wdt.asm
new file mode 100644
index 0000000..ff6ddd1
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90pwm81/words/no-wdt.asm
@@ -0,0 +1,34 @@
+; ( -- )
+; MCU
+; disable watch dog timer at runtime
+VE_NOWDT:
+ .dw $ff04
+ .db "-wdt"
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOWDT
+XT_NOWDT:
+ .dw PFA_NOWDT
+PFA_NOWDT:
+
+ in temp1,SREG
+ push temp1
+ ; Turn always off global interrupt.
+ cli
+ ; Reset Watchdog Timer
+ wdr
+ ; Clear WDRF in MCUSR
+ in temp1, MCUSR
+ andi temp1, (0xff & (0<<WDRF))
+ out MCUSR, temp1
+ ; Write logical one to WDCE and WDE
+ ; Keep old prescaler setting to prevent unintentional time-out
+ in_ temp1, WDTCSR
+ ori temp1, (1<<WDCE) | (1<<WDE)
+ out_ WDTCSR, temp1
+ ; Turn off WDT
+ ldi temp1, (0<<WDE)
+ out_ WDTCSR, temp1
+ ; restore status register
+ pop temp1
+ out SREG,temp1
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/at90pwm81/words/sleep.asm b/amforth-6.5/avr8/devices/at90pwm81/words/sleep.asm
new file mode 100644
index 0000000..256249c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/at90pwm81/words/sleep.asm
@@ -0,0 +1,19 @@
+; ( mode -- )
+; MCU
+; put the controller into the specified sleep mode
+VE_SLEEP:
+ .dw $ff05
+ .db "sleep", 0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_SLEEP
+XT_SLEEP:
+ .dw PFA_SLEEP
+PFA_SLEEP:
+ andi tosl, 7 ; leave only legal mode bits
+ lsl tosl ; move to correct location (bits 3-1)
+ ori tosl, 1 ; set the SE bit
+ out_ SMCR, tosl ; set the sleep config
+ sleep ; nighty-night
+ out_ SMCR, zerol ; 0 protects against accidental sleeps
+ loadtos ; pop argument from stack
+ jmp_ DO_NEXT