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-rw-r--r--amforth-6.5/avr8/devices/atmega161/atmega161.frt121
-rw-r--r--amforth-6.5/avr8/devices/atmega161/device.asm113
-rw-r--r--amforth-6.5/avr8/devices/atmega161/device.inc843
-rw-r--r--amforth-6.5/avr8/devices/atmega161/device.py87
4 files changed, 1164 insertions, 0 deletions
diff --git a/amforth-6.5/avr8/devices/atmega161/atmega161.frt b/amforth-6.5/avr8/devices/atmega161/atmega161.frt
new file mode 100644
index 0000000..e8d2119
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega161/atmega161.frt
@@ -0,0 +1,121 @@
+\ Partname: ATmega161
+\ Built using part description XML file version 233
+\ generated automatically
+
+hex
+
+\ ANALOG_COMPARATOR
+28 constant ACSR \ Analog Comparator Control And Status Register
+
+\ CPU
+56 constant EMCUCR \ Extended MCU Control Register
+55 constant MCUCR \ MCU Control Register
+54 constant MCUSR \ MCU Status Register
+5E constant SPH \ Stack Pointer High
+5D constant SPL \ Stack Pointer Low
+57 constant SPMCR \ Store Program Memory Control Register
+5F constant SREG \ Status Register
+
+\ EEPROM
+3F constant EEARH \ EEPROM Address Register High Byte
+3E constant EEARL \ EEPROM Address Register Low Byte
+3C constant EECR \ EEPROM Control Register
+3D constant EEDR \ EEPROM Data Register
+
+\ EXTERNAL_INTERRUPT
+5A constant GIFR \ General Interrupt Flag Register
+5B constant GIMSK \ General Interrupt Mask Register
+
+\ PORTA
+3A constant DDRA \ Port A Data Direction Register
+39 constant PINA \ Port A Input Pins
+3B constant PORTA \ Port A Data Register
+
+\ PORTB
+37 constant DDRB \ Port B Data Direction Register
+36 constant PINB \ Port B Input Pins
+38 constant PORTB \ Port B Data Register
+
+\ PORTC
+34 constant DDRC \ Port C Data Direction Register
+33 constant PINC \ Port C Input Pins
+35 constant PORTC \ Port C Data Register
+
+\ PORTD
+31 constant DDRD \ Port D Data Direction Register
+30 constant PIND \ Port D Input Pins
+32 constant PORTD \ Port D Data Register
+
+\ PORTE
+26 constant DDRE \ Port E Data Direction Register
+25 constant PINE \ Port E Input Pins
+27 constant PORTE \ Port E Data Register
+
+\ SPI
+2D constant SPCR \ SPI Control Register
+2F constant SPDR \ SPI Data Register
+2E constant SPSR \ SPI Status Register
+
+\ TIMER_COUNTER_0
+51 constant OCR0 \ Output Compare Register
+50 constant SFIOR \ Special Function IO Register
+53 constant TCCR0 \ Timer/Counter Control Register
+52 constant TCNT0 \ Timer/Counter Register
+58 constant TIFR \ Timer/Counter Interrupt Flag register
+59 constant TIMSK \ Timer/Counter Interrupt Mask Register
+
+\ TIMER_COUNTER_1
+45 constant ICR1H \ Timer/Counter1 Input Capture Register High Byte
+44 constant ICR1L \ Timer/Counter1 Input Capture Register Low Byte
+4B constant OCR1AH \ Timer/Counter1 Output Compare Register High Byte
+4A constant OCR1AL \ Timer/Counter1 Output Compare Register Low Byte
+49 constant OCR1BH \ Timer/Counter1 Output Compare Register High Byte
+48 constant OCR1BL \ Timer/Counter1 Output Compare Register Low Byte
+4F constant TCCR1A \ Timer/Counter1 Control Register A
+4E constant TCCR1B \ Timer/Counter1 Control Register B
+4D constant TCNT1H \ Timer/Counter1 High Byte
+4C constant TCNT1L \ Timer/Counter1 Low Byte
+
+\ TIMER_COUNTER_2
+46 constant ASSR \ Asynchronous Status Register
+42 constant OCR2 \ Timer/Counter2 Output Compare Register
+47 constant TCCR2 \ Timer/Counter2 Control Register
+43 constant TCNT2 \ Timer/Counter2
+
+\ USART0
+29 constant UBRR0 \ USART Baud Rate Register Byte
+40 constant UBRRHI \ High Byte Baud Rate Register
+2B constant UCSR0A \ USART Control and Status Register A
+2A constant UCSR0B \ USART Control and Status Register B
+2C constant UDR0 \ USART I/O Data Register
+
+\ USART1
+20 constant UBRR1 \ USART Baud Rate Register Byte
+22 constant UCSR1A \ USART Control and Status Register A
+21 constant UCSR1B \ USART Control and Status Register B
+23 constant UDR1 \ USART I/O Data Register
+
+\ WATCHDOG
+41 constant WDTCR \ Watchdog Timer Control Register
+
+\ Interrupts
+002 constant INT0Addr \ External Interrupt 0
+004 constant INT1Addr \ External Interrupt 1
+006 constant INT2Addr \ External Interrupt 2
+008 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
+00A constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
+00C constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+00E constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
+010 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
+012 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+014 constant TIMER0_COMPAddr \ Timer/Counter0 Compare Match
+016 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
+018 constant SPISTCAddr \ Serial Transfer Complete
+01A constant UART0RXAddr \ UART0, Rx Complete
+01C constant UART1RXAddr \ UART1, Rx Complete
+01E constant UART0UDREAddr \ UART0 Data Register Empty
+020 constant UART1UDREAddr \ UART1 Data Register Empty
+022 constant UART0TXAddr \ UART0, Tx Complete
+024 constant UART1TXAddr \ UART1, Tx Complete
+026 constant EE_RDYAddr \ EEPROM Ready
+028 constant ANA_COMPAddr \ Analog Comparator
diff --git a/amforth-6.5/avr8/devices/atmega161/device.asm b/amforth-6.5/avr8/devices/atmega161/device.asm
new file mode 100644
index 0000000..6208a6e
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega161/device.asm
@@ -0,0 +1,113 @@
+; Partname: ATmega161
+; Built using part description XML file version 233
+; generated automatically, do not edit
+
+.nolist
+ .include "m161def.inc"
+.list
+
+.equ ramstart = $60
+.equ CELLSIZE = 2
+.macro readflashcell
+ lsl zl
+ rol zh
+ lpm @0, Z+
+ lpm @1, Z+
+.endmacro
+.macro writeflashcell
+ lsl zl
+ rol zh
+.endmacro
+
+; the following definitions are shortcuts for the respective forth source segments if set to 1
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_CPU = 0
+.set WANT_EEPROM = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_PORTA = 0
+.set WANT_PORTB = 0
+.set WANT_PORTC = 0
+.set WANT_PORTD = 0
+.set WANT_PORTE = 0
+.set WANT_SPI = 0
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_TIMER_COUNTER_2 = 0
+.set WANT_USART0 = 0
+.set WANT_USART1 = 0
+.set WANT_WATCHDOG = 0
+
+
+.ifndef SPMEN
+ .equ SPMEN = SELFPRGEN
+.endif
+
+.ifndef SPMCSR
+ .equ SPMCSR = SPMCR
+.endif
+
+.ifndef EEPE
+ .equ EEPE = EEWE
+.endif
+
+.ifndef EEMPE
+ .equ EEMPE = EEMWE
+.endif
+.equ intvecsize = 2 ; please verify; flash size: 16384 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.equ INTVECTORS = 21
+.org $002
+ rcall isr ; External Interrupt 0
+.org $004
+ rcall isr ; External Interrupt 1
+.org $006
+ rcall isr ; External Interrupt 2
+.org $008
+ rcall isr ; Timer/Counter2 Compare Match
+.org $00A
+ rcall isr ; Timer/Counter2 Overflow
+.org $00C
+ rcall isr ; Timer/Counter1 Capture Event
+.org $00E
+ rcall isr ; Timer/Counter1 Compare Match A
+.org $010
+ rcall isr ; Timer/Counter1 Compare Match B
+.org $012
+ rcall isr ; Timer/Counter1 Overflow
+.org $014
+ rcall isr ; Timer/Counter0 Compare Match
+.org $016
+ rcall isr ; Timer/Counter0 Overflow
+.org $018
+ rcall isr ; Serial Transfer Complete
+.org $01A
+ rcall isr ; UART0, Rx Complete
+.org $01C
+ rcall isr ; UART1, Rx Complete
+.org $01E
+ rcall isr ; UART0 Data Register Empty
+.org $020
+ rcall isr ; UART1 Data Register Empty
+.org $022
+ rcall isr ; UART0, Tx Complete
+.org $024
+ rcall isr ; UART1, Tx Complete
+.org $026
+ rcall isr ; EEPROM Ready
+.org $028
+ rcall isr ; Analog Comparator
+.nooverlap
+mcu_info:
+mcu_ramsize:
+ .dw 1024
+mcu_eepromsize:
+ .dw 512
+mcu_maxdp:
+ .dw 0 ; minimum of 0 (from XML) and 0xffff
+mcu_numints:
+ .dw 21
+mcu_name:
+ .dw 9
+ .db "ATmega161",0
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega161/device.inc b/amforth-6.5/avr8/devices/atmega161/device.inc
new file mode 100644
index 0000000..0cedf69
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega161/device.inc
@@ -0,0 +1,843 @@
+; Partname: ATmega161
+; Built using part description XML file version 233
+; generated automatically, no not edit
+
+; ********
+.if WANT_ANALOG_COMPARATOR == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Control And Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw $28
+
+.endif
+
+; ********
+.if WANT_CPU == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Extended MCU Control Register
+VE_EMCUCR:
+ .dw $ff06
+ .db "EMCUCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EMCUCR
+XT_EMCUCR:
+ .dw PFA_DOVARIABLE
+PFA_EMCUCR:
+ .dw $56
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw $55
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Status Register
+VE_MCUSR:
+ .dw $ff05
+ .db "MCUSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUSR
+XT_MCUSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUSR:
+ .dw $54
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer High
+VE_SPH:
+ .dw $ff03
+ .db "SPH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPH
+XT_SPH:
+ .dw PFA_DOVARIABLE
+PFA_SPH:
+ .dw $5E
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer Low
+VE_SPL:
+ .dw $ff03
+ .db "SPL",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPL
+XT_SPL:
+ .dw PFA_DOVARIABLE
+PFA_SPL:
+ .dw $5D
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control Register
+VE_SPMCR:
+ .dw $ff05
+ .db "SPMCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCR
+XT_SPMCR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCR:
+ .dw $57
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw $5F
+
+.endif
+
+; ********
+.if WANT_EEPROM == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Address Register High Byte
+VE_EEARH:
+ .dw $ff05
+ .db "EEARH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEARH
+XT_EEARH:
+ .dw PFA_DOVARIABLE
+PFA_EEARH:
+ .dw $3F
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Address Register Low Byte
+VE_EEARL:
+ .dw $ff05
+ .db "EEARL",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEARL
+XT_EEARL:
+ .dw PFA_DOVARIABLE
+PFA_EEARL:
+ .dw $3E
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw $3C
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw $3D
+
+.endif
+
+; ********
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; General Interrupt Flag Register
+VE_GIFR:
+ .dw $ff04
+ .db "GIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GIFR
+XT_GIFR:
+ .dw PFA_DOVARIABLE
+PFA_GIFR:
+ .dw $5A
+; ( -- addr ) System Constant
+; R( -- )
+; General Interrupt Mask Register
+VE_GIMSK:
+ .dw $ff05
+ .db "GIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GIMSK
+XT_GIMSK:
+ .dw PFA_DOVARIABLE
+PFA_GIMSK:
+ .dw $5B
+
+.endif
+
+; ********
+.if WANT_PORTA == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Direction Register
+VE_DDRA:
+ .dw $ff04
+ .db "DDRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRA
+XT_DDRA:
+ .dw PFA_DOVARIABLE
+PFA_DDRA:
+ .dw $3A
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Input Pins
+VE_PINA:
+ .dw $ff04
+ .db "PINA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINA
+XT_PINA:
+ .dw PFA_DOVARIABLE
+PFA_PINA:
+ .dw $39
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Register
+VE_PORTA:
+ .dw $ff05
+ .db "PORTA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTA
+XT_PORTA:
+ .dw PFA_DOVARIABLE
+PFA_PORTA:
+ .dw $3B
+
+.endif
+
+; ********
+.if WANT_PORTB == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw $37
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw $36
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw $38
+
+.endif
+
+; ********
+.if WANT_PORTC == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Direction Register
+VE_DDRC:
+ .dw $ff04
+ .db "DDRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRC
+XT_DDRC:
+ .dw PFA_DOVARIABLE
+PFA_DDRC:
+ .dw $34
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Input Pins
+VE_PINC:
+ .dw $ff04
+ .db "PINC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINC
+XT_PINC:
+ .dw PFA_DOVARIABLE
+PFA_PINC:
+ .dw $33
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Register
+VE_PORTC:
+ .dw $ff05
+ .db "PORTC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTC
+XT_PORTC:
+ .dw PFA_DOVARIABLE
+PFA_PORTC:
+ .dw $35
+
+.endif
+
+; ********
+.if WANT_PORTD == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw $31
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw $30
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw $32
+
+.endif
+
+; ********
+.if WANT_PORTE == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Port E Data Direction Register
+VE_DDRE:
+ .dw $ff04
+ .db "DDRE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRE
+XT_DDRE:
+ .dw PFA_DOVARIABLE
+PFA_DDRE:
+ .dw $26
+; ( -- addr ) System Constant
+; R( -- )
+; Port E Input Pins
+VE_PINE:
+ .dw $ff04
+ .db "PINE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINE
+XT_PINE:
+ .dw PFA_DOVARIABLE
+PFA_PINE:
+ .dw $25
+; ( -- addr ) System Constant
+; R( -- )
+; Port E Data Register
+VE_PORTE:
+ .dw $ff05
+ .db "PORTE",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTE
+XT_PORTE:
+ .dw PFA_DOVARIABLE
+PFA_PORTE:
+ .dw $27
+
+.endif
+
+; ********
+.if WANT_SPI == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR:
+ .dw $ff04
+ .db "SPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR
+XT_SPCR:
+ .dw PFA_DOVARIABLE
+PFA_SPCR:
+ .dw $2D
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR:
+ .dw $ff04
+ .db "SPDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR
+XT_SPDR:
+ .dw PFA_DOVARIABLE
+PFA_SPDR:
+ .dw $2F
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR:
+ .dw $ff04
+ .db "SPSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR
+XT_SPSR:
+ .dw PFA_DOVARIABLE
+PFA_SPSR:
+ .dw $2E
+
+.endif
+
+; ********
+.if WANT_TIMER_COUNTER_0 == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare Register
+VE_OCR0:
+ .dw $ff04
+ .db "OCR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0
+XT_OCR0:
+ .dw PFA_DOVARIABLE
+PFA_OCR0:
+ .dw $51
+; ( -- addr ) System Constant
+; R( -- )
+; Special Function IO Register
+VE_SFIOR:
+ .dw $ff05
+ .db "SFIOR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SFIOR
+XT_SFIOR:
+ .dw PFA_DOVARIABLE
+PFA_SFIOR:
+ .dw $50
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register
+VE_TCCR0:
+ .dw $ff05
+ .db "TCCR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0
+XT_TCCR0:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0:
+ .dw $53
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Register
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw $52
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Flag register
+VE_TIFR:
+ .dw $ff04
+ .db "TIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR
+XT_TIFR:
+ .dw PFA_DOVARIABLE
+PFA_TIFR:
+ .dw $58
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Mask Register
+VE_TIMSK:
+ .dw $ff05
+ .db "TIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK
+XT_TIMSK:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK:
+ .dw $59
+
+.endif
+
+; ********
+.if WANT_TIMER_COUNTER_1 == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register High Byte
+VE_ICR1H:
+ .dw $ff05
+ .db "ICR1H",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1H
+XT_ICR1H:
+ .dw PFA_DOVARIABLE
+PFA_ICR1H:
+ .dw $45
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Low Byte
+VE_ICR1L:
+ .dw $ff05
+ .db "ICR1L",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1L
+XT_ICR1L:
+ .dw PFA_DOVARIABLE
+PFA_ICR1L:
+ .dw $44
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register High Byte
+VE_OCR1AH:
+ .dw $ff06
+ .db "OCR1AH"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1AH
+XT_OCR1AH:
+ .dw PFA_DOVARIABLE
+PFA_OCR1AH:
+ .dw $4B
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register Low Byte
+VE_OCR1AL:
+ .dw $ff06
+ .db "OCR1AL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1AL
+XT_OCR1AL:
+ .dw PFA_DOVARIABLE
+PFA_OCR1AL:
+ .dw $4A
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register High Byte
+VE_OCR1BH:
+ .dw $ff06
+ .db "OCR1BH"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1BH
+XT_OCR1BH:
+ .dw PFA_DOVARIABLE
+PFA_OCR1BH:
+ .dw $49
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register Low Byte
+VE_OCR1BL:
+ .dw $ff06
+ .db "OCR1BL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1BL
+XT_OCR1BL:
+ .dw PFA_DOVARIABLE
+PFA_OCR1BL:
+ .dw $48
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw $4F
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw $4E
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 High Byte
+VE_TCNT1H:
+ .dw $ff06
+ .db "TCNT1H"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1H
+XT_TCNT1H:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1H:
+ .dw $4D
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Low Byte
+VE_TCNT1L:
+ .dw $ff06
+ .db "TCNT1L"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1L
+XT_TCNT1L:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1L:
+ .dw $4C
+
+.endif
+
+; ********
+.if WANT_TIMER_COUNTER_2 == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Asynchronous Status Register
+VE_ASSR:
+ .dw $ff04
+ .db "ASSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ASSR
+XT_ASSR:
+ .dw PFA_DOVARIABLE
+PFA_ASSR:
+ .dw $46
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register
+VE_OCR2:
+ .dw $ff04
+ .db "OCR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2
+XT_OCR2:
+ .dw PFA_DOVARIABLE
+PFA_OCR2:
+ .dw $42
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register
+VE_TCCR2:
+ .dw $ff05
+ .db "TCCR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2
+XT_TCCR2:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2:
+ .dw $47
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2
+VE_TCNT2:
+ .dw $ff05
+ .db "TCNT2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT2
+XT_TCNT2:
+ .dw PFA_DOVARIABLE
+PFA_TCNT2:
+ .dw $43
+
+.endif
+
+; ********
+.if WANT_USART0 == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Byte
+VE_UBRR0:
+ .dw $ff05
+ .db "UBRR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR0
+XT_UBRR0:
+ .dw PFA_DOVARIABLE
+PFA_UBRR0:
+ .dw $29
+; ( -- addr ) System Constant
+; R( -- )
+; High Byte Baud Rate Register
+VE_UBRRHI:
+ .dw $ff06
+ .db "UBRRHI"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRRHI
+XT_UBRRHI:
+ .dw PFA_DOVARIABLE
+PFA_UBRRHI:
+ .dw $40
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR0A:
+ .dw $ff06
+ .db "UCSR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0A
+XT_UCSR0A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0A:
+ .dw $2B
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR0B:
+ .dw $ff06
+ .db "UCSR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0B
+XT_UCSR0B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0B:
+ .dw $2A
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR0:
+ .dw $ff04
+ .db "UDR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR0
+XT_UDR0:
+ .dw PFA_DOVARIABLE
+PFA_UDR0:
+ .dw $2C
+
+.endif
+
+; ********
+.if WANT_USART1 == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Byte
+VE_UBRR1:
+ .dw $ff05
+ .db "UBRR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR1
+XT_UBRR1:
+ .dw PFA_DOVARIABLE
+PFA_UBRR1:
+ .dw $20
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR1A:
+ .dw $ff06
+ .db "UCSR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1A
+XT_UCSR1A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1A:
+ .dw $22
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR1B:
+ .dw $ff06
+ .db "UCSR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR1B
+XT_UCSR1B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR1B:
+ .dw $21
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR1:
+ .dw $ff04
+ .db "UDR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR1
+XT_UDR1:
+ .dw PFA_DOVARIABLE
+PFA_UDR1:
+ .dw $23
+
+.endif
+
+; ********
+.if WANT_WATCHDOG == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCR:
+ .dw $ff05
+ .db "WDTCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCR
+XT_WDTCR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCR:
+ .dw $41
+
+.endif
diff --git a/amforth-6.5/avr8/devices/atmega161/device.py b/amforth-6.5/avr8/devices/atmega161/device.py
new file mode 100644
index 0000000..3f30afc
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega161/device.py
@@ -0,0 +1,87 @@
+# Partname: ATmega161
+# Built using part description XML file version 233
+# generated automatically, do not edit
+MCUREGS = {
+ 'ACSR': '$28',
+ 'EMCUCR': '$56',
+ 'MCUCR': '$55',
+ 'MCUSR': '$54',
+ 'SPH': '$5E',
+ 'SPL': '$5D',
+ 'SPMCR': '$57',
+ 'SREG': '$5F',
+ 'EEARH': '$3F',
+ 'EEARL': '$3E',
+ 'EECR': '$3C',
+ 'EEDR': '$3D',
+ 'GIFR': '$5A',
+ 'GIMSK': '$5B',
+ 'DDRA': '$3A',
+ 'PINA': '$39',
+ 'PORTA': '$3B',
+ 'DDRB': '$37',
+ 'PINB': '$36',
+ 'PORTB': '$38',
+ 'DDRC': '$34',
+ 'PINC': '$33',
+ 'PORTC': '$35',
+ 'DDRD': '$31',
+ 'PIND': '$30',
+ 'PORTD': '$32',
+ 'DDRE': '$26',
+ 'PINE': '$25',
+ 'PORTE': '$27',
+ 'SPCR': '$2D',
+ 'SPDR': '$2F',
+ 'SPSR': '$2E',
+ 'OCR0': '$51',
+ 'SFIOR': '$50',
+ 'TCCR0': '$53',
+ 'TCNT0': '$52',
+ 'TIFR': '$58',
+ 'TIMSK': '$59',
+ 'ICR1H': '$45',
+ 'ICR1L': '$44',
+ 'OCR1AH': '$4B',
+ 'OCR1AL': '$4A',
+ 'OCR1BH': '$49',
+ 'OCR1BL': '$48',
+ 'TCCR1A': '$4F',
+ 'TCCR1B': '$4E',
+ 'TCNT1H': '$4D',
+ 'TCNT1L': '$4C',
+ 'ASSR': '$46',
+ 'OCR2': '$42',
+ 'TCCR2': '$47',
+ 'TCNT2': '$43',
+ 'UBRR0': '$29',
+ 'UBRRHI': '$40',
+ 'UCSR0A': '$2B',
+ 'UCSR0B': '$2A',
+ 'UDR0': '$2C',
+ 'UBRR1': '$20',
+ 'UCSR1A': '$22',
+ 'UCSR1B': '$21',
+ 'UDR1': '$23',
+ 'WDTCR': '$41',
+ 'INT0Addr': '$002',
+ 'INT1Addr': '$004',
+ 'INT2Addr': '$006',
+ 'TIMER2_COMPAddr': '$008',
+ 'TIMER2_OVFAddr': '$00A',
+ 'TIMER1_CAPTAddr': '$00C',
+ 'TIMER1_COMPAAddr': '$00E',
+ 'TIMER1_COMPBAddr': '$010',
+ 'TIMER1_OVFAddr': '$012',
+ 'TIMER0_COMPAddr': '$014',
+ 'TIMER0_OVFAddr': '$016',
+ 'SPISTCAddr': '$018',
+ 'UART0RXAddr': '$01A',
+ 'UART1RXAddr': '$01C',
+ 'UART0UDREAddr': '$01E',
+ 'UART1UDREAddr': '$020',
+ 'UART0TXAddr': '$022',
+ 'UART1TXAddr': '$024',
+ 'EE_RDYAddr': '$026',
+ 'ANA_COMPAddr': '$028'
+} \ No newline at end of file