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-rw-r--r--amforth-6.5/avr8/devices/atmega165/atmega165.frt160
-rw-r--r--amforth-6.5/avr8/devices/atmega165/device.asm120
-rw-r--r--amforth-6.5/avr8/devices/atmega165/device.inc1209
-rw-r--r--amforth-6.5/avr8/devices/atmega165/device.py319
4 files changed, 1808 insertions, 0 deletions
diff --git a/amforth-6.5/avr8/devices/atmega165/atmega165.frt b/amforth-6.5/avr8/devices/atmega165/atmega165.frt
new file mode 100644
index 0000000..25fea57
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega165/atmega165.frt
@@ -0,0 +1,160 @@
+\ Partname: ATmega165
+\ Built using part description XML file version 126
+\ generated automatically
+
+hex
+
+\ AD_CONVERTER
+79 constant ADCH \ ADC Data Register High Byte
+78 constant ADCL \ ADC Data Register Low Byte
+7A constant ADCSRA \ The ADC Control and Status register
+7B constant ADCSRB \ ADC Control and Status Register B
+7C constant ADMUX \ The ADC multiplexer Selection Register
+7E constant DIDR0 \ Digital Input Disable Register 0
+
+\ ANALOG_COMPARATOR
+50 constant ACSR \ Analog Comparator Control And Status Register
+7F constant DIDR1 \ Digital Input Disable Register 1
+
+\ BOOT_LOAD
+57 constant SPMCSR \ Store Program Memory Control Register
+
+\ CPU
+61 constant CLKPR \ Clock Prescale Register
+3E constant GPIOR0 \ General Purpose IO Register 0
+4A constant GPIOR1 \ General Purpose IO Register 1
+4B constant GPIOR2 \ General Purpose IO Register 2
+55 constant MCUCR \ MCU Control Register
+54 constant MCUSR \ MCU Status Register
+66 constant OSCCAL \ Oscillator Calibration Value
+64 constant PRR \ Power Reduction Register
+53 constant SMCR \ Sleep Mode Control Register
+5E constant SPH \ Stack Pointer High
+5D constant SPL \ Stack Pointer Low
+5F constant SREG \ Status Register
+
+\ EEPROM
+42 constant EEARH \ EEPROM Address Register High Byte
+41 constant EEARL \ EEPROM Address Register Low Byte
+3F constant EECR \ EEPROM Control Register
+40 constant EEDR \ EEPROM Data Register
+
+\ EXTERNAL_INTERRUPT
+69 constant EICRA \ External Interrupt Control Register
+3C constant EIFR \ External Interrupt Flag Register
+3D constant EIMSK \ External Interrupt Mask Register
+6B constant PCMSK0 \ Pin Change Mask Register 0
+6C constant PCMSK1 \ Pin Change Mask Register 1
+
+\ JTAG
+51 constant OCDR \ On-Chip Debug Related Register in I/O Memory
+
+\ PORTA
+21 constant DDRA \ Port A Data Direction Register
+20 constant PINA \ Port A Input Pins
+22 constant PORTA \ Port A Data Register
+
+\ PORTB
+24 constant DDRB \ Port B Data Direction Register
+23 constant PINB \ Port B Input Pins
+25 constant PORTB \ Port B Data Register
+
+\ PORTC
+27 constant DDRC \ Port C Data Direction Register
+26 constant PINC \ Port C Input Pins
+28 constant PORTC \ Port C Data Register
+
+\ PORTD
+2A constant DDRD \ Port D Data Direction Register
+29 constant PIND \ Port D Input Pins
+2B constant PORTD \ Port D Data Register
+
+\ PORTE
+2D constant DDRE \ Data Direction Register, Port E
+2C constant PINE \ Input Pins, Port E
+2E constant PORTE \ Data Register, Port E
+
+\ PORTF
+30 constant DDRF \ Data Direction Register, Port F
+2F constant PINF \ Input Pins, Port F
+31 constant PORTF \ Data Register, Port F
+
+\ PORTG
+33 constant DDRG \ Port G Data Direction Register
+32 constant PING \ Port G Input Pins
+34 constant PORTG \ Port G Data Register
+
+\ SPI
+4C constant SPCR \ SPI Control Register
+4E constant SPDR \ SPI Data Register
+4D constant SPSR \ SPI Status Register
+
+\ TIMER_COUNTER_0
+43 constant GTCCR \ General Timer/Control Register
+47 constant OCR0A \ Timer/Counter0 Output Compare Register
+44 constant TCCR0A \ Timer/Counter0 Control Register
+46 constant TCNT0 \ Timer/Counter0
+35 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
+6E constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
+
+\ TIMER_COUNTER_1
+87 constant ICR1H \ Timer/Counter1 Input Capture Register High Byte
+86 constant ICR1L \ Timer/Counter1 Input Capture Register Low Byte
+89 constant OCR1AH \ Timer/Counter1 Output Compare Register A High Byte
+88 constant OCR1AL \ Timer/Counter1 Output Compare Register A Low Byte
+8B constant OCR1BH \ Timer/Counter1 Output Compare Register B High Byte
+8A constant OCR1BL \ Timer/Counter1 Output Compare Register B Low Byte
+80 constant TCCR1A \ Timer/Counter1 Control Register A
+81 constant TCCR1B \ Timer/Counter1 Control Register B
+82 constant TCCR1C \ Timer/Counter 1 Control Register C
+85 constant TCNT1H \ Timer/Counter1 High Byte
+84 constant TCNT1L \ Timer/Counter1 Low Byte
+36 constant TIFR1 \ Timer/Counter1 Interrupt Flag register
+6F constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
+
+\ TIMER_COUNTER_2
+B6 constant ASSR \ Asynchronous Status Register
+B3 constant OCR2A \ Timer/Counter2 Output Compare Register
+B0 constant TCCR2A \ Timer/Counter2 Control Register
+B2 constant TCNT2 \ Timer/Counter2
+37 constant TIFR2 \ Timer/Counter2 Interrupt Flag Register
+70 constant TIMSK2 \ Timer/Counter2 Interrupt Mask register
+
+\ USART0
+C5 constant UBRR0H \ USART Baud Rate Register High Byte
+C4 constant UBRR0L \ USART Baud Rate Register Low Byte
+C0 constant UCSR0A \ USART Control and Status Register A
+C1 constant UCSR0B \ USART Control and Status Register B
+C2 constant UCSR0C \ USART Control and Status Register C
+C6 constant UDR0 \ USART I/O Data Register
+
+\ USI
+B8 constant USICR \ USI Control Register
+BA constant USIDR \ USI Data Register
+B9 constant USISR \ USI Status Register
+
+\ WATCHDOG
+60 constant WDTCR \ Watchdog Timer Control Register
+
+\ Interrupts
+002 constant INT0Addr \ External Interrupt Request 0
+004 constant PCINT0Addr \ Pin Change Interrupt Request 0
+006 constant PCINT1Addr \ Pin Change Interrupt Request 1
+008 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
+00A constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
+00C constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+00E constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
+010 constant TIMER1_COMPBAddr \ Timer/Counter Compare Match B
+012 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+014 constant TIMER0_COMPAddr \ Timer/Counter0 Compare Match
+016 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
+018 constant SPI_STCAddr \ SPI Serial Transfer Complete
+01A constant USART0_RXAddr \ USART0, Rx Complete
+01C constant USART0_UDREAddr \ USART0 Data register Empty
+01E constant USART0_TXAddr \ USART0, Tx Complete
+020 constant USI_STARTAddr \ USI Start Condition
+022 constant USI_OVERFLOWAddr \ USI Overflow
+024 constant ANALOG_COMPAddr \ Analog Comparator
+026 constant ADCAddr \ ADC Conversion Complete
+028 constant EE_READYAddr \ EEPROM Ready
+02A constant SPM_READYAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/atmega165/device.asm b/amforth-6.5/avr8/devices/atmega165/device.asm
new file mode 100644
index 0000000..87aad59
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega165/device.asm
@@ -0,0 +1,120 @@
+; Partname: ATmega165
+; Built using part description XML file version 126
+; generated automatically, do not edit
+
+.nolist
+ .include "m165def.inc"
+.list
+
+.equ ramstart = $100
+.equ CELLSIZE = 2
+.macro readflashcell
+ lsl zl
+ rol zh
+ lpm @0, Z+
+ lpm @1, Z+
+.endmacro
+.macro writeflashcell
+ lsl zl
+ rol zh
+.endmacro
+
+; the following definitions are shortcuts for the respective forth source segments if set to 1
+.set WANT_AD_CONVERTER = 0
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_BOOT_LOAD = 0
+.set WANT_CPU = 0
+.set WANT_EEPROM = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_JTAG = 0
+.set WANT_PORTA = 0
+.set WANT_PORTB = 0
+.set WANT_PORTC = 0
+.set WANT_PORTD = 0
+.set WANT_PORTE = 0
+.set WANT_PORTF = 0
+.set WANT_PORTG = 0
+.set WANT_SPI = 0
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_TIMER_COUNTER_2 = 0
+.set WANT_USART0 = 0
+.set WANT_USI = 0
+.set WANT_WATCHDOG = 0
+
+
+.ifndef SPMEN
+ .equ SPMEN = SELFPRGEN
+.endif
+
+.ifndef SPMCSR
+ .equ SPMCSR = SPMCR
+.endif
+
+.ifndef EEPE
+ .equ EEPE = EEWE
+.endif
+
+.ifndef EEMPE
+ .equ EEMPE = EEMWE
+.endif
+.equ intvecsize = 2 ; please verify; flash size: 16384 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.equ INTVECTORS = 22
+.org $002
+ rcall isr ; External Interrupt Request 0
+.org $004
+ rcall isr ; Pin Change Interrupt Request 0
+.org $006
+ rcall isr ; Pin Change Interrupt Request 1
+.org $008
+ rcall isr ; Timer/Counter2 Compare Match
+.org $00A
+ rcall isr ; Timer/Counter2 Overflow
+.org $00C
+ rcall isr ; Timer/Counter1 Capture Event
+.org $00E
+ rcall isr ; Timer/Counter1 Compare Match A
+.org $010
+ rcall isr ; Timer/Counter Compare Match B
+.org $012
+ rcall isr ; Timer/Counter1 Overflow
+.org $014
+ rcall isr ; Timer/Counter0 Compare Match
+.org $016
+ rcall isr ; Timer/Counter0 Overflow
+.org $018
+ rcall isr ; SPI Serial Transfer Complete
+.org $01A
+ rcall isr ; USART0, Rx Complete
+.org $01C
+ rcall isr ; USART0 Data register Empty
+.org $01E
+ rcall isr ; USART0, Tx Complete
+.org $020
+ rcall isr ; USI Start Condition
+.org $022
+ rcall isr ; USI Overflow
+.org $024
+ rcall isr ; Analog Comparator
+.org $026
+ rcall isr ; ADC Conversion Complete
+.org $028
+ rcall isr ; EEPROM Ready
+.org $02A
+ rcall isr ; Store Program Memory Read
+.nooverlap
+mcu_info:
+mcu_ramsize:
+ .dw 1024
+mcu_eepromsize:
+ .dw 512
+mcu_maxdp:
+ .dw 7168 ; minimum of 0x1C00 (from XML) and 0xffff
+mcu_numints:
+ .dw 22
+mcu_name:
+ .dw 9
+ .db "ATmega165",0
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega165/device.inc b/amforth-6.5/avr8/devices/atmega165/device.inc
new file mode 100644
index 0000000..739f874
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega165/device.inc
@@ -0,0 +1,1209 @@
+; Partname: ATmega165
+; Built using part description XML file version 126
+; generated automatically, no not edit
+
+; ********
+.if WANT_AD_CONVERTER == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register High Byte
+VE_ADCH:
+ .dw $ff04
+ .db "ADCH"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCH
+XT_ADCH:
+ .dw PFA_DOVARIABLE
+PFA_ADCH:
+ .dw $79
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register Low Byte
+VE_ADCL:
+ .dw $ff04
+ .db "ADCL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCL
+XT_ADCL:
+ .dw PFA_DOVARIABLE
+PFA_ADCL:
+ .dw $78
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register
+VE_ADCSRA:
+ .dw $ff06
+ .db "ADCSRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRA
+XT_ADCSRA:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRA:
+ .dw $7A
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Control and Status Register B
+VE_ADCSRB:
+ .dw $ff06
+ .db "ADCSRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRB
+XT_ADCSRB:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRB:
+ .dw $7B
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC multiplexer Selection Register
+VE_ADMUX:
+ .dw $ff05
+ .db "ADMUX",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADMUX
+XT_ADMUX:
+ .dw PFA_DOVARIABLE
+PFA_ADMUX:
+ .dw $7C
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 0
+VE_DIDR0:
+ .dw $ff05
+ .db "DIDR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR0
+XT_DIDR0:
+ .dw PFA_DOVARIABLE
+PFA_DIDR0:
+ .dw $7E
+
+.endif
+
+; ********
+.if WANT_ANALOG_COMPARATOR == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Control And Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw $50
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 1
+VE_DIDR1:
+ .dw $ff05
+ .db "DIDR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR1
+XT_DIDR1:
+ .dw PFA_DOVARIABLE
+PFA_DIDR1:
+ .dw $7F
+
+.endif
+
+; ********
+.if WANT_BOOT_LOAD == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control Register
+VE_SPMCSR:
+ .dw $ff06
+ .db "SPMCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCSR
+XT_SPMCSR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCSR:
+ .dw $57
+
+.endif
+
+; ********
+.if WANT_CPU == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Clock Prescale Register
+VE_CLKPR:
+ .dw $ff05
+ .db "CLKPR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKPR
+XT_CLKPR:
+ .dw PFA_DOVARIABLE
+PFA_CLKPR:
+ .dw $61
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 0
+VE_GPIOR0:
+ .dw $ff06
+ .db "GPIOR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR0
+XT_GPIOR0:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR0:
+ .dw $3E
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 1
+VE_GPIOR1:
+ .dw $ff06
+ .db "GPIOR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR1
+XT_GPIOR1:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR1:
+ .dw $4A
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 2
+VE_GPIOR2:
+ .dw $ff06
+ .db "GPIOR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR2
+XT_GPIOR2:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR2:
+ .dw $4B
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw $55
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Status Register
+VE_MCUSR:
+ .dw $ff05
+ .db "MCUSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUSR
+XT_MCUSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUSR:
+ .dw $54
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Calibration Value
+VE_OSCCAL:
+ .dw $ff06
+ .db "OSCCAL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSCCAL
+XT_OSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_OSCCAL:
+ .dw $66
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register
+VE_PRR:
+ .dw $ff03
+ .db "PRR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR
+XT_PRR:
+ .dw PFA_DOVARIABLE
+PFA_PRR:
+ .dw $64
+; ( -- addr ) System Constant
+; R( -- )
+; Sleep Mode Control Register
+VE_SMCR:
+ .dw $ff04
+ .db "SMCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SMCR
+XT_SMCR:
+ .dw PFA_DOVARIABLE
+PFA_SMCR:
+ .dw $53
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer High
+VE_SPH:
+ .dw $ff03
+ .db "SPH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPH
+XT_SPH:
+ .dw PFA_DOVARIABLE
+PFA_SPH:
+ .dw $5E
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer Low
+VE_SPL:
+ .dw $ff03
+ .db "SPL",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPL
+XT_SPL:
+ .dw PFA_DOVARIABLE
+PFA_SPL:
+ .dw $5D
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw $5F
+
+.endif
+
+; ********
+.if WANT_EEPROM == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Address Register High Byte
+VE_EEARH:
+ .dw $ff05
+ .db "EEARH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEARH
+XT_EEARH:
+ .dw PFA_DOVARIABLE
+PFA_EEARH:
+ .dw $42
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Address Register Low Byte
+VE_EEARL:
+ .dw $ff05
+ .db "EEARL",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEARL
+XT_EEARL:
+ .dw PFA_DOVARIABLE
+PFA_EEARL:
+ .dw $41
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw $3F
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw $40
+
+.endif
+
+; ********
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register
+VE_EICRA:
+ .dw $ff05
+ .db "EICRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRA
+XT_EICRA:
+ .dw PFA_DOVARIABLE
+PFA_EICRA:
+ .dw $69
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Flag Register
+VE_EIFR:
+ .dw $ff04
+ .db "EIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIFR
+XT_EIFR:
+ .dw PFA_DOVARIABLE
+PFA_EIFR:
+ .dw $3C
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Mask Register
+VE_EIMSK:
+ .dw $ff05
+ .db "EIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIMSK
+XT_EIMSK:
+ .dw PFA_DOVARIABLE
+PFA_EIMSK:
+ .dw $3D
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 0
+VE_PCMSK0:
+ .dw $ff06
+ .db "PCMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK0
+XT_PCMSK0:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK0:
+ .dw $6B
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 1
+VE_PCMSK1:
+ .dw $ff06
+ .db "PCMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK1
+XT_PCMSK1:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK1:
+ .dw $6C
+
+.endif
+
+; ********
+.if WANT_JTAG == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; On-Chip Debug Related Register in I/O Memory
+VE_OCDR:
+ .dw $ff04
+ .db "OCDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCDR
+XT_OCDR:
+ .dw PFA_DOVARIABLE
+PFA_OCDR:
+ .dw $51
+
+.endif
+
+; ********
+.if WANT_PORTA == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Direction Register
+VE_DDRA:
+ .dw $ff04
+ .db "DDRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRA
+XT_DDRA:
+ .dw PFA_DOVARIABLE
+PFA_DDRA:
+ .dw $21
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Input Pins
+VE_PINA:
+ .dw $ff04
+ .db "PINA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINA
+XT_PINA:
+ .dw PFA_DOVARIABLE
+PFA_PINA:
+ .dw $20
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Register
+VE_PORTA:
+ .dw $ff05
+ .db "PORTA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTA
+XT_PORTA:
+ .dw PFA_DOVARIABLE
+PFA_PORTA:
+ .dw $22
+
+.endif
+
+; ********
+.if WANT_PORTB == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw $24
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw $23
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw $25
+
+.endif
+
+; ********
+.if WANT_PORTC == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Direction Register
+VE_DDRC:
+ .dw $ff04
+ .db "DDRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRC
+XT_DDRC:
+ .dw PFA_DOVARIABLE
+PFA_DDRC:
+ .dw $27
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Input Pins
+VE_PINC:
+ .dw $ff04
+ .db "PINC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINC
+XT_PINC:
+ .dw PFA_DOVARIABLE
+PFA_PINC:
+ .dw $26
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Register
+VE_PORTC:
+ .dw $ff05
+ .db "PORTC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTC
+XT_PORTC:
+ .dw PFA_DOVARIABLE
+PFA_PORTC:
+ .dw $28
+
+.endif
+
+; ********
+.if WANT_PORTD == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw $2A
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw $29
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw $2B
+
+.endif
+
+; ********
+.if WANT_PORTE == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port E
+VE_DDRE:
+ .dw $ff04
+ .db "DDRE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRE
+XT_DDRE:
+ .dw PFA_DOVARIABLE
+PFA_DDRE:
+ .dw $2D
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port E
+VE_PINE:
+ .dw $ff04
+ .db "PINE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINE
+XT_PINE:
+ .dw PFA_DOVARIABLE
+PFA_PINE:
+ .dw $2C
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port E
+VE_PORTE:
+ .dw $ff05
+ .db "PORTE",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTE
+XT_PORTE:
+ .dw PFA_DOVARIABLE
+PFA_PORTE:
+ .dw $2E
+
+.endif
+
+; ********
+.if WANT_PORTF == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port F
+VE_DDRF:
+ .dw $ff04
+ .db "DDRF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRF
+XT_DDRF:
+ .dw PFA_DOVARIABLE
+PFA_DDRF:
+ .dw $30
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port F
+VE_PINF:
+ .dw $ff04
+ .db "PINF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINF
+XT_PINF:
+ .dw PFA_DOVARIABLE
+PFA_PINF:
+ .dw $2F
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port F
+VE_PORTF:
+ .dw $ff05
+ .db "PORTF",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTF
+XT_PORTF:
+ .dw PFA_DOVARIABLE
+PFA_PORTF:
+ .dw $31
+
+.endif
+
+; ********
+.if WANT_PORTG == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Data Direction Register
+VE_DDRG:
+ .dw $ff04
+ .db "DDRG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRG
+XT_DDRG:
+ .dw PFA_DOVARIABLE
+PFA_DDRG:
+ .dw $33
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Input Pins
+VE_PING:
+ .dw $ff04
+ .db "PING"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PING
+XT_PING:
+ .dw PFA_DOVARIABLE
+PFA_PING:
+ .dw $32
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Data Register
+VE_PORTG:
+ .dw $ff05
+ .db "PORTG",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTG
+XT_PORTG:
+ .dw PFA_DOVARIABLE
+PFA_PORTG:
+ .dw $34
+
+.endif
+
+; ********
+.if WANT_SPI == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR:
+ .dw $ff04
+ .db "SPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR
+XT_SPCR:
+ .dw PFA_DOVARIABLE
+PFA_SPCR:
+ .dw $4C
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR:
+ .dw $ff04
+ .db "SPDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR
+XT_SPDR:
+ .dw PFA_DOVARIABLE
+PFA_SPDR:
+ .dw $4E
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR:
+ .dw $ff04
+ .db "SPSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR
+XT_SPSR:
+ .dw PFA_DOVARIABLE
+PFA_SPSR:
+ .dw $4D
+
+.endif
+
+; ********
+.if WANT_TIMER_COUNTER_0 == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; General Timer/Control Register
+VE_GTCCR:
+ .dw $ff05
+ .db "GTCCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GTCCR
+XT_GTCCR:
+ .dw PFA_DOVARIABLE
+PFA_GTCCR:
+ .dw $43
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0A:
+ .dw $ff05
+ .db "OCR0A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0A
+XT_OCR0A:
+ .dw PFA_DOVARIABLE
+PFA_OCR0A:
+ .dw $47
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Control Register
+VE_TCCR0A:
+ .dw $ff06
+ .db "TCCR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0A
+XT_TCCR0A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0A:
+ .dw $44
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw $46
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Flag register
+VE_TIFR0:
+ .dw $ff05
+ .db "TIFR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR0
+XT_TIFR0:
+ .dw PFA_DOVARIABLE
+PFA_TIFR0:
+ .dw $35
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Mask Register
+VE_TIMSK0:
+ .dw $ff06
+ .db "TIMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK0
+XT_TIMSK0:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK0:
+ .dw $6E
+
+.endif
+
+; ********
+.if WANT_TIMER_COUNTER_1 == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register High Byte
+VE_ICR1H:
+ .dw $ff05
+ .db "ICR1H",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1H
+XT_ICR1H:
+ .dw PFA_DOVARIABLE
+PFA_ICR1H:
+ .dw $87
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Low Byte
+VE_ICR1L:
+ .dw $ff05
+ .db "ICR1L",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1L
+XT_ICR1L:
+ .dw PFA_DOVARIABLE
+PFA_ICR1L:
+ .dw $86
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register A High Byte
+VE_OCR1AH:
+ .dw $ff06
+ .db "OCR1AH"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1AH
+XT_OCR1AH:
+ .dw PFA_DOVARIABLE
+PFA_OCR1AH:
+ .dw $89
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register A Low Byte
+VE_OCR1AL:
+ .dw $ff06
+ .db "OCR1AL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1AL
+XT_OCR1AL:
+ .dw PFA_DOVARIABLE
+PFA_OCR1AL:
+ .dw $88
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register B High Byte
+VE_OCR1BH:
+ .dw $ff06
+ .db "OCR1BH"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1BH
+XT_OCR1BH:
+ .dw PFA_DOVARIABLE
+PFA_OCR1BH:
+ .dw $8B
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register B Low Byte
+VE_OCR1BL:
+ .dw $ff06
+ .db "OCR1BL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1BL
+XT_OCR1BL:
+ .dw PFA_DOVARIABLE
+PFA_OCR1BL:
+ .dw $8A
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw $80
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw $81
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter 1 Control Register C
+VE_TCCR1C:
+ .dw $ff06
+ .db "TCCR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1C
+XT_TCCR1C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1C:
+ .dw $82
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 High Byte
+VE_TCNT1H:
+ .dw $ff06
+ .db "TCNT1H"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1H
+XT_TCNT1H:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1H:
+ .dw $85
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Low Byte
+VE_TCNT1L:
+ .dw $ff06
+ .db "TCNT1L"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1L
+XT_TCNT1L:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1L:
+ .dw $84
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Flag register
+VE_TIFR1:
+ .dw $ff05
+ .db "TIFR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR1
+XT_TIFR1:
+ .dw PFA_DOVARIABLE
+PFA_TIFR1:
+ .dw $36
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Mask Register
+VE_TIMSK1:
+ .dw $ff06
+ .db "TIMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK1
+XT_TIMSK1:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK1:
+ .dw $6F
+
+.endif
+
+; ********
+.if WANT_TIMER_COUNTER_2 == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Asynchronous Status Register
+VE_ASSR:
+ .dw $ff04
+ .db "ASSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ASSR
+XT_ASSR:
+ .dw PFA_DOVARIABLE
+PFA_ASSR:
+ .dw $B6
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register
+VE_OCR2A:
+ .dw $ff05
+ .db "OCR2A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2A
+XT_OCR2A:
+ .dw PFA_DOVARIABLE
+PFA_OCR2A:
+ .dw $B3
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register
+VE_TCCR2A:
+ .dw $ff06
+ .db "TCCR2A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2A
+XT_TCCR2A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2A:
+ .dw $B0
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2
+VE_TCNT2:
+ .dw $ff05
+ .db "TCNT2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT2
+XT_TCNT2:
+ .dw PFA_DOVARIABLE
+PFA_TCNT2:
+ .dw $B2
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Interrupt Flag Register
+VE_TIFR2:
+ .dw $ff05
+ .db "TIFR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR2
+XT_TIFR2:
+ .dw PFA_DOVARIABLE
+PFA_TIFR2:
+ .dw $37
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Interrupt Mask register
+VE_TIMSK2:
+ .dw $ff06
+ .db "TIMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK2
+XT_TIMSK2:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK2:
+ .dw $70
+
+.endif
+
+; ********
+.if WANT_USART0 == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register High Byte
+VE_UBRR0H:
+ .dw $ff06
+ .db "UBRR0H"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR0H
+XT_UBRR0H:
+ .dw PFA_DOVARIABLE
+PFA_UBRR0H:
+ .dw $C5
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Low Byte
+VE_UBRR0L:
+ .dw $ff06
+ .db "UBRR0L"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR0L
+XT_UBRR0L:
+ .dw PFA_DOVARIABLE
+PFA_UBRR0L:
+ .dw $C4
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR0A:
+ .dw $ff06
+ .db "UCSR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0A
+XT_UCSR0A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0A:
+ .dw $C0
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR0B:
+ .dw $ff06
+ .db "UCSR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0B
+XT_UCSR0B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0B:
+ .dw $C1
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR0C:
+ .dw $ff06
+ .db "UCSR0C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0C
+XT_UCSR0C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0C:
+ .dw $C2
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR0:
+ .dw $ff04
+ .db "UDR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR0
+XT_UDR0:
+ .dw PFA_DOVARIABLE
+PFA_UDR0:
+ .dw $C6
+
+.endif
+
+; ********
+.if WANT_USI == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; USI Control Register
+VE_USICR:
+ .dw $ff05
+ .db "USICR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USICR
+XT_USICR:
+ .dw PFA_DOVARIABLE
+PFA_USICR:
+ .dw $B8
+; ( -- addr ) System Constant
+; R( -- )
+; USI Data Register
+VE_USIDR:
+ .dw $ff05
+ .db "USIDR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USIDR
+XT_USIDR:
+ .dw PFA_DOVARIABLE
+PFA_USIDR:
+ .dw $BA
+; ( -- addr ) System Constant
+; R( -- )
+; USI Status Register
+VE_USISR:
+ .dw $ff05
+ .db "USISR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USISR
+XT_USISR:
+ .dw PFA_DOVARIABLE
+PFA_USISR:
+ .dw $B9
+
+.endif
+
+; ********
+.if WANT_WATCHDOG == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCR:
+ .dw $ff05
+ .db "WDTCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCR
+XT_WDTCR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCR:
+ .dw $60
+
+.endif
diff --git a/amforth-6.5/avr8/devices/atmega165/device.py b/amforth-6.5/avr8/devices/atmega165/device.py
new file mode 100644
index 0000000..bd637ca
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega165/device.py
@@ -0,0 +1,319 @@
+# Generated Automatically
+
+# Partname ATmega165A
+
+MCUREGS = {
+# Interrupt Vectors
+ 'INT0Addr' : '#2', # External Interrupt Request 0
+ 'PCINT0Addr' : '#4', # Pin Change Interrupt Request 0
+ 'PCINT1Addr' : '#6', # Pin Change Interrupt Request 1
+ 'TIMER2_COMPAddr' : '#8', # Timer/Counter2 Compare Match
+ 'TIMER2_OVFAddr' : '#10', # Timer/Counter2 Overflow
+ 'TIMER1_CAPTAddr' : '#12', # Timer/Counter1 Capture Event
+ 'TIMER1_COMPAAddr' : '#14', # Timer/Counter1 Compare Match A
+ 'TIMER1_COMPBAddr' : '#16', # Timer/Counter Compare Match B
+ 'TIMER1_OVFAddr' : '#18', # Timer/Counter1 Overflow
+ 'TIMER0_COMPAddr' : '#20', # Timer/Counter0 Compare Match
+ 'TIMER0_OVFAddr' : '#22', # Timer/Counter0 Overflow
+ 'SPI_STCAddr' : '#24', # SPI Serial Transfer Complete
+ 'USART0_RXAddr' : '#26', # USART0, Rx Complete
+ 'USART0_UDREAddr' : '#28', # USART0 Data register Empty
+ 'USART0_TXAddr' : '#30', # USART0, Tx Complete
+ 'USI_STARTAddr' : '#32', # USI Start Condition
+ 'USI_OVERFLOWAddr' : '#34', # USI Overflow
+ 'ANALOG_COMPAddr' : '#36', # Analog Comparator
+ 'ADCAddr' : '#38', # ADC Conversion Complete
+ 'EE_READYAddr' : '#40', # EEPROM Ready
+ 'SPM_READYAddr' : '#42', # Store Program Memory Read
+
+# Module TIMER_COUNTER_0
+ 'TCCR0A' : '$44', # Timer/Counter0 Control Registe
+ 'TCCR0A_FOC0A': '$80', # Force Output Compare
+ 'TCCR0A_WGM00': '$40', # Waveform Generation Mode 0
+ 'TCCR0A_COM0A': '$30', # Compare Match Output Modes
+ 'TCCR0A_WGM01': '$8', # Waveform Generation Mode 1
+ 'TCCR0A_CS0': '$7', # Clock Selects
+ 'TCNT0' : '$46', # Timer/Counter0
+ 'OCR0A' : '$47', # Timer/Counter0 Output Compare
+ 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
+ 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
+ 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
+ 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
+ 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
+ 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Control Register
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSR310': '$1', # Prescaler Reset Timer/Counter1
+
+# Module TIMER_COUNTER_1
+ 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
+ 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
+ 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
+ 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
+ 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
+ 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
+ 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
+ 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
+ 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
+ 'TCCR1C' : '$82', # Timer/Counter 1 Control Regist
+ 'TCCR1C_FOC1A': '$80', # Force Output Compare 1A
+ 'TCCR1C_FOC1B': '$40', # Force Output Compare 1B
+ 'TCNT1' : '$84', # Timer/Counter1 Bytes
+ 'OCR1A' : '$88', # Timer/Counter1 Output Compare
+ 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
+ 'ICR1' : '$86', # Timer/Counter1 Input Capture R
+ 'TIMSK1' : '$6f', # Timer/Counter1 Interrupt Mask
+ 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
+ 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output Compare
+ 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
+ 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
+ 'TIFR1' : '$36', # Timer/Counter1 Interrupt Flag
+ 'TIFR1_ICF1': '$20', # Input Capture Flag 1
+ 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
+ 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
+ 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
+
+# Module TIMER_COUNTER_2
+ 'TCCR2A' : '$b0', # Timer/Counter2 Control Registe
+ 'TCCR2A_FOC2A': '$80', # Force Output Compare A
+ 'TCCR2A_WGM20': '$40', # Waveform Generation Mode
+ 'TCCR2A_COM2A': '$30', # Compare Output Mode bits
+ 'TCCR2A_WGM21': '$8', # Waveform Generation Mode
+ 'TCCR2A_CS2': '$7', # Clock Select bits
+ 'TCNT2' : '$b2', # Timer/Counter2
+ 'OCR2A' : '$b3', # Timer/Counter2 Output Compare
+ 'TIMSK2' : '$70', # Timer/Counter2 Interrupt Mask
+ 'TIMSK2_OCIE2A': '$2', # Timer/Counter2 Output Compare
+ 'TIMSK2_TOIE2': '$1', # Timer/Counter2 Overflow Interr
+ 'TIFR2' : '$37', # Timer/Counter2 Interrupt Flag
+ 'TIFR2_OCF2A': '$2', # Timer/Counter2 Output Compare
+ 'TIFR2_TOV2': '$1', # Timer/Counter2 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_PSR2': '$2', # Prescaler Reset Timer/Counter2
+ 'ASSR' : '$b6', # Asynchronous Status Register
+ 'ASSR_EXCLK': '$10', # Enable External Clock Interrup
+ 'ASSR_AS2': '$8', # AS2: Asynchronous Timer/Counte
+ 'ASSR_TCN2UB': '$4', # TCN2UB: Timer/Counter2 Update
+ 'ASSR_OCR2UB': '$2', # Output Compare Register2 Updat
+ 'ASSR_TCR2UB': '$1', # TCR2UB: Timer/Counter Control
+
+# Module WATCHDOG
+ 'WDTCR' : '$60', # Watchdog Timer Control Registe
+ 'WDTCR_WDCE': '$10', # Watchdog Change Enable
+ 'WDTCR_WDE': '$8', # Watch Dog Enable
+ 'WDTCR_WDP': '$7', # Watch Dog Timer Prescaler bits
+
+# Module EEPROM
+ 'EEAR' : '$41', # EEPROM Address Register Bytes
+ 'EEDR' : '$40', # EEPROM Data Register
+ 'EECR' : '$3f', # EEPROM Control Register
+ 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
+ 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
+ 'EECR_EEWE': '$2', # EEPROM Write Enable
+ 'EECR_EERE': '$1', # EEPROM Read Enable
+
+# Module SPI
+ 'SPCR' : '$4c', # SPI Control Register
+ 'SPCR_SPIE': '$80', # SPI Interrupt Enable
+ 'SPCR_SPE': '$40', # SPI Enable
+ 'SPCR_DORD': '$20', # Data Order
+ 'SPCR_MSTR': '$10', # Master/Slave Select
+ 'SPCR_CPOL': '$8', # Clock polarity
+ 'SPCR_CPHA': '$4', # Clock Phase
+ 'SPCR_SPR': '$3', # SPI Clock Rate Selects
+ 'SPSR' : '$4d', # SPI Status Register
+ 'SPSR_SPIF': '$80', # SPI Interrupt Flag
+ 'SPSR_WCOL': '$40', # Write Collision Flag
+ 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
+ 'SPDR' : '$4e', # SPI Data Register
+
+# Module PORTA
+ 'PORTA' : '$22', # Port A Data Register
+ 'DDRA' : '$21', # Port A Data Direction Register
+ 'PINA' : '$20', # Port A Input Pins
+
+# Module PORTB
+ 'PORTB' : '$25', # Port B Data Register
+ 'DDRB' : '$24', # Port B Data Direction Register
+ 'PINB' : '$23', # Port B Input Pins
+
+# Module PORTC
+ 'PORTC' : '$28', # Port C Data Register
+ 'DDRC' : '$27', # Port C Data Direction Register
+ 'PINC' : '$26', # Port C Input Pins
+
+# Module PORTD
+ 'PORTD' : '$2b', # Port D Data Register
+ 'DDRD' : '$2a', # Port D Data Direction Register
+ 'PIND' : '$29', # Port D Input Pins
+
+# Module ANALOG_COMPARATOR
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ACME': '$40', # Analog Comparator Multiplexer
+ 'ACSR' : '$50', # Analog Comparator Control And
+ 'ACSR_ACD': '$80', # Analog Comparator Disable
+ 'ACSR_ACBG': '$40', # Analog Comparator Bandgap Sele
+ 'ACSR_ACO': '$20', # Analog Compare Output
+ 'ACSR_ACI': '$10', # Analog Comparator Interrupt Fl
+ 'ACSR_ACIE': '$8', # Analog Comparator Interrupt En
+ 'ACSR_ACIC': '$4', # Analog Comparator Input Captur
+ 'ACSR_ACIS': '$3', # Analog Comparator Interrupt Mo
+ 'DIDR1' : '$7f', # Digital Input Disable Register
+ 'DIDR1_AIN1D': '$2', # AIN1 Digital Input Disable
+ 'DIDR1_AIN0D': '$1', # AIN0 Digital Input Disable
+
+# Module PORTE
+ 'PORTE' : '$2e', # Data Register, Port E
+ 'DDRE' : '$2d', # Data Direction Register, Port
+ 'PINE' : '$2c', # Input Pins, Port E
+
+# Module PORTF
+ 'PORTF' : '$31', # Data Register, Port F
+ 'DDRF' : '$30', # Data Direction Register, Port
+ 'PINF' : '$2f', # Input Pins, Port F
+
+# Module PORTG
+ 'PORTG' : '$34', # Port G Data Register
+ 'DDRG' : '$33', # Port G Data Direction Register
+ 'PING' : '$32', # Port G Input Pins
+
+# Module JTAG
+ 'OCDR' : '$51', # On-Chip Debug Related Register
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_JTD': '$80', # JTAG Interface Disable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+
+# Module USI
+ 'USIDR' : '$ba', # USI Data Register
+ 'USISR' : '$b9', # USI Status Register
+ 'USISR_USISIF': '$80', # Start Condition Interrupt Flag
+ 'USISR_USIOIF': '$40', # Counter Overflow Interrupt Fla
+ 'USISR_USIPF': '$20', # Stop Condition Flag
+ 'USISR_USIDC': '$10', # Data Output Collision
+ 'USISR_USICNT': '$f', # USI Counter Value Bits
+ 'USICR' : '$b8', # USI Control Register
+ 'USICR_USISIE': '$80', # Start Condition Interrupt Enab
+ 'USICR_USIOIE': '$40', # Counter Overflow Interrupt Ena
+ 'USICR_USIWM': '$30', # USI Wire Mode Bits
+ 'USICR_USICS': '$c', # USI Clock Source Select Bits
+ 'USICR_USICLK': '$2', # Clock Strobe
+ 'USICR_USITC': '$1', # Toggle Clock Port Pin
+
+# Module AD_CONVERTER
+ 'ADMUX' : '$7c', # The ADC multiplexer Selection
+ 'ADMUX_REFS': '$c0', # Reference Selection Bits
+ 'ADMUX_ADLAR': '$20', # Left Adjust Result
+ 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
+ 'ADCSRA' : '$7a', # The ADC Control and Status reg
+ 'ADCSRA_ADEN': '$80', # ADC Enable
+ 'ADCSRA_ADSC': '$40', # ADC Start Conversion
+ 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
+ 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
+ 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
+ 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
+ 'ADC' : '$78', # ADC Data Register Bytes
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ADTS': '$7', # ADC Auto Trigger Sources
+ 'DIDR0' : '$7e', # Digital Input Disable Register
+ 'DIDR0_ADC7D': '$80', # ADC7 Digital input Disable
+ 'DIDR0_ADC6D': '$40', # ADC6 Digital input Disable
+ 'DIDR0_ADC5D': '$20', # ADC5 Digital input Disable
+ 'DIDR0_ADC4D': '$10', # ADC4 Digital input Disable
+ 'DIDR0_ADC3D': '$8', # ADC3 Digital input Disable
+ 'DIDR0_ADC2D': '$4', # ADC2 Digital input Disable
+ 'DIDR0_ADC1D': '$2', # ADC1 Digital input Disable
+ 'DIDR0_ADC0D': '$1', # ADC0 Digital input Disable
+
+# Module BOOT_LOAD
+ 'SPMCSR' : '$57', # Store Program Memory Control R
+ 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
+ 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
+ 'SPMCSR_RWWSRE': '$10', # Read While Write section read
+ 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
+ 'SPMCSR_PGWRT': '$4', # Page Write
+ 'SPMCSR_PGERS': '$2', # Page Erase
+ 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
+
+# Module USART0
+ 'UDR0' : '$c6', # USART I/O Data Register
+ 'UCSR0A' : '$c0', # USART Control and Status Regis
+ 'UCSR0A_RXC0': '$80', # USART Receive Complete
+ 'UCSR0A_TXC0': '$40', # USART Transmit Complete
+ 'UCSR0A_UDRE0': '$20', # USART Data Register Empty
+ 'UCSR0A_FE0': '$10', # Framing Error
+ 'UCSR0A_DOR0': '$8', # Data OverRun
+ 'UCSR0A_UPE0': '$4', # USART Parity Error
+ 'UCSR0A_U2X0': '$2', # Double the USART Transmission
+ 'UCSR0A_MPCM0': '$1', # Multi-processor Communication
+ 'UCSR0B' : '$c1', # USART Control and Status Regis
+ 'UCSR0B_RXCIE0': '$80', # RX Complete Interrupt Enable
+ 'UCSR0B_TXCIE0': '$40', # TX Complete Interrupt Enable
+ 'UCSR0B_UDRIE0': '$20', # USART Data Register Empty Inte
+ 'UCSR0B_RXEN0': '$10', # Receiver Enable
+ 'UCSR0B_TXEN0': '$8', # Transmitter Enable
+ 'UCSR0B_UCSZ02': '$4', # Character Size
+ 'UCSR0B_RXB80': '$2', # Receive Data Bit 8
+ 'UCSR0B_TXB80': '$1', # Transmit Data Bit 8
+ 'UCSR0C' : '$c2', # USART Control and Status Regis
+ 'UCSR0C_UMSEL0': '$40', # USART Mode Select
+ 'UCSR0C_UPM0': '$30', # Parity Mode Bits
+ 'UCSR0C_USBS0': '$8', # Stop Bit Select
+ 'UCSR0C_UCSZ0': '$6', # Character Size
+ 'UCSR0C_UCPOL0': '$1', # Clock Polarity
+ 'UBRR0' : '$c4', # USART Baud Rate Register Byte
+
+# Module EXTERNAL_INTERRUPT
+ 'EICRA' : '$69', # External Interrupt Control Reg
+ 'EICRA_ISC01': '$2', # External Interrupt Sense Contr
+ 'EICRA_ISC00': '$1', # External Interrupt Sense Contr
+ 'EIMSK' : '$3d', # External Interrupt Mask Regist
+ 'EIMSK_PCIE': '$30', # Pin Change Interrupt Enables
+ 'EIMSK_INT0': '$1', # External Interrupt Request 0 E
+ 'EIFR' : '$3c', # External Interrupt Flag Regist
+ 'EIFR_PCIF': '$30', # Pin Change Interrupt Flags
+ 'EIFR_INTF0': '$1', # External Interrupt Flag 0
+ 'PCMSK1' : '$6c', # Pin Change Mask Register 1
+ 'PCMSK1_PCINT': '$ff', # Pin Change Enable Masks
+ 'PCMSK0' : '$6b', # Pin Change Mask Register 0
+ 'PCMSK0_PCINT': '$ff', # Pin Change Enable Masks
+
+# Module CPU
+ 'SREG' : '$5f', # Status Register
+ 'SREG_I': '$80', # Global Interrupt Enable
+ 'SREG_T': '$40', # Bit Copy Storage
+ 'SREG_H': '$20', # Half Carry Flag
+ 'SREG_S': '$10', # Sign Bit
+ 'SREG_V': '$8', # Two's Complement Overflow Flag
+ 'SREG_N': '$4', # Negative Flag
+ 'SREG_Z': '$2', # Zero Flag
+ 'SREG_C': '$1', # Carry Flag
+ 'SP' : '$5d', # Stack Pointer
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_PUD': '$10', # Pull-up disable
+ 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
+ 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+ 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
+ 'MCUSR_BORF': '$4', # Brown-out Reset Flag
+ 'MCUSR_EXTRF': '$2', # External Reset Flag
+ 'MCUSR_PORF': '$1', # Power-on reset flag
+ 'OSCCAL' : '$66', # Oscillator Calibration Value
+ 'CLKPR' : '$61', # Clock Prescale Register
+ 'CLKPR_CLKPCE': '$80', # Clock Prescaler Change Enable
+ 'CLKPR_CLKPS': '$f', # Clock Prescaler Select Bits
+ 'PRR' : '$64', # Power Reduction Register
+ 'PRR_PRTIM1': '$8', # Power Reduction Timer/Counter1
+ 'PRR_PRSPI': '$4', # Power Reduction Serial Periphe
+ 'PRR_PRUSART0': '$2', # Power Reduction USART
+ 'PRR_PRADC': '$1', # Power Reduction ADC
+ 'SMCR' : '$53', # Sleep Mode Control Register
+ 'SMCR_SM': '$e', # Sleep Mode Select bits
+ 'SMCR_SE': '$1', # Sleep Enable
+ 'GPIOR2' : '$4b', # General Purpose IO Register 2
+ 'GPIOR1' : '$4a', # General Purpose IO Register 1
+ 'GPIOR0' : '$3e', # General Purpose IO Register 0
+
+ '__amforth_dummy':'0'
+}