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-rw-r--r--amforth-6.5/avr8/devices/atmega64m1/atmega64m1.frt513
-rw-r--r--amforth-6.5/avr8/devices/atmega64m1/device.asm120
-rw-r--r--amforth-6.5/avr8/devices/atmega64m1/device.inc1734
-rw-r--r--amforth-6.5/avr8/devices/atmega64m1/device.py495
-rw-r--r--amforth-6.5/avr8/devices/atmega64m1/words/no-jtag.asm14
-rw-r--r--amforth-6.5/avr8/devices/atmega64m1/words/no-wdt.asm34
-rw-r--r--amforth-6.5/avr8/devices/atmega64m1/words/sleep.asm19
7 files changed, 2929 insertions, 0 deletions
diff --git a/amforth-6.5/avr8/devices/atmega64m1/atmega64m1.frt b/amforth-6.5/avr8/devices/atmega64m1/atmega64m1.frt
new file mode 100644
index 0000000..135e761
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega64m1/atmega64m1.frt
@@ -0,0 +1,513 @@
+\ Partname: ATmega64M1
+\ generated automatically
+
+\ PORTB
+&37 constant PORTB \ Port B Data Register
+&36 constant DDRB \ Port B Data Direction Register
+&35 constant PINB \ Port B Input Pins
+\ PORTC
+&40 constant PORTC \ Port C Data Register
+&39 constant DDRC \ Port C Data Direction Register
+&38 constant PINC \ Port C Input Pins
+\ PORTD
+&43 constant PORTD \ Port D Data Register
+&42 constant DDRD \ Port D Data Direction Register
+&41 constant PIND \ Port D Input Pins
+\ CAN
+&216 constant CANGCON \ CAN General Control Register
+ $80 constant CANGCON_ABRQ \ Abort Request
+ $40 constant CANGCON_OVRQ \ Overload Frame Request
+ $20 constant CANGCON_TTC \ Time Trigger Communication
+ $10 constant CANGCON_SYNTTC \ Synchronization of TTC
+ $08 constant CANGCON_LISTEN \ Listening Mode
+ $04 constant CANGCON_TEST \ Test Mode
+ $02 constant CANGCON_ENASTB \ Enable / Standby
+ $01 constant CANGCON_SWRES \ Software Reset Request
+&217 constant CANGSTA \ CAN General Status Register
+ $40 constant CANGSTA_OVFG \ Overload Frame Flag
+ $10 constant CANGSTA_TXBSY \ Transmitter Busy
+ $08 constant CANGSTA_RXBSY \ Receiver Busy
+ $04 constant CANGSTA_ENFG \ Enable Flag
+ $02 constant CANGSTA_BOFF \ Bus Off Mode
+ $01 constant CANGSTA_ERRP \ Error Passive Mode
+&218 constant CANGIT \ CAN General Interrupt Register Flags
+ $80 constant CANGIT_CANIT \ General Interrupt Flag
+ $40 constant CANGIT_BOFFIT \ Bus Off Interrupt Flag
+ $20 constant CANGIT_OVRTIM \ Overrun CAN Timer Flag
+ $10 constant CANGIT_BXOK \ Burst Receive Interrupt Flag
+ $08 constant CANGIT_SERG \ Stuff Error General Flag
+ $04 constant CANGIT_CERG \ CRC Error General Flag
+ $02 constant CANGIT_FERG \ Form Error General Flag
+ $01 constant CANGIT_AERG \ Ackknowledgement Error General Flag
+&219 constant CANGIE \ CAN General Interrupt Enable Register
+ $80 constant CANGIE_ENIT \ Enable all Interrupts
+ $40 constant CANGIE_ENBOFF \ Enable Bus Off Interrupt
+ $20 constant CANGIE_ENRX \ Enable Receive Interrupt
+ $10 constant CANGIE_ENTX \ Enable Transmitt Interrupt
+ $08 constant CANGIE_ENERR \ Enable MOb Error Interrupt
+ $04 constant CANGIE_ENBX \ Enable Burst Receive Interrupt
+ $02 constant CANGIE_ENERG \ Enable General Error Interrupt
+ $01 constant CANGIE_ENOVRT \ Enable CAN Timer Overrun Interrupt
+&220 constant CANEN2 \ Enable MOb Register 2
+ $3F constant CANEN2_ENMOB \ Enable MObs
+&221 constant CANEN1 \ Enable MOb Register 1(empty)
+&222 constant CANIE2 \ Enable Interrupt MOb Register 2
+ $3F constant CANIE2_IEMOB \ Interrupt Enable MObs
+&223 constant CANIE1 \ Enable Interrupt MOb Register 1 (empty)
+&224 constant CANSIT2 \ CAN Status Interrupt MOb Register 2
+ $3F constant CANSIT2_SIT \ Status of Interrupt MObs
+&225 constant CANSIT1 \ CAN Status Interrupt MOb Register 1 (empty)
+&226 constant CANBT1 \ CAN Bit Timing Register 1
+ $7E constant CANBT1_BRP \ Baud Rate Prescaler bits
+&227 constant CANBT2 \ CAN Bit Timing Register 2
+ $60 constant CANBT2_SJW \ Re-Sync Jump Width bits
+ $0E constant CANBT2_PRS \ Propagation Time Segment bits
+&228 constant CANBT3 \ CAN Bit Timing Register 3
+ $70 constant CANBT3_PHS2 \ Phase Segment 2 bits
+ $0E constant CANBT3_PHS1 \ Phase Segment 1 bits
+ $01 constant CANBT3_SMP \ Sample Type
+&229 constant CANTCON \ Timer Control Register
+&230 constant CANTIML \ Timer Register Low
+&231 constant CANTIMH \ Timer Register High
+&232 constant CANTTCL \ TTC Timer Register Low
+&233 constant CANTTCH \ TTC Timer Register High
+&234 constant CANTEC \ Transmit Error Counter Register
+&235 constant CANREC \ Receive Error Counter Register
+&236 constant CANHPMOB \ Highest Priority MOb Register
+ $F0 constant CANHPMOB_HPMOB \ Highest Priority MOb Number bits
+ $0F constant CANHPMOB_CGP \ CAN General Purpose bits
+&237 constant CANPAGE \ Page MOb Register
+ $F0 constant CANPAGE_MOBNB \ MOb Number bits
+ $08 constant CANPAGE_AINC \ MOb Data Buffer Auto Increment (Active Low)
+ $07 constant CANPAGE_INDX \ Data Buffer Index bits
+&238 constant CANSTMOB \ MOb Status Register
+ $80 constant CANSTMOB_DLCW \ Data Length Code Warning on MOb
+ $40 constant CANSTMOB_TXOK \ Transmit OK on MOb
+ $20 constant CANSTMOB_RXOK \ Receive OK on MOb
+ $10 constant CANSTMOB_BERR \ Bit Error on MOb
+ $08 constant CANSTMOB_SERR \ Stuff Error on MOb
+ $04 constant CANSTMOB_CERR \ CRC Error on MOb
+ $02 constant CANSTMOB_FERR \ Form Error on MOb
+ $01 constant CANSTMOB_AERR \ Ackknowledgement Error on MOb
+&239 constant CANCDMOB \ MOb Control and DLC Register
+ $C0 constant CANCDMOB_CONMOB \ MOb Config bits
+ $20 constant CANCDMOB_RPLV \ Reply Valid
+ $10 constant CANCDMOB_IDE \ Identifier Extension
+ $0F constant CANCDMOB_DLC \ Data Length Code bits
+&240 constant CANIDT4 \ Identifier Tag Register 4
+ $F8 constant CANIDT4_IDT \
+ $04 constant CANIDT4_RTRTAG \
+ $02 constant CANIDT4_RB1TAG \
+ $01 constant CANIDT4_RB0TAG \
+&241 constant CANIDT3 \ Identifier Tag Register 3
+&242 constant CANIDT2 \ Identifier Tag Register 2
+&243 constant CANIDT1 \ Identifier Tag Register 1
+&244 constant CANIDM4 \ Identifier Mask Register 4
+&245 constant CANIDM3 \ Identifier Mask Register 3
+&246 constant CANIDM2 \ Identifier Mask Register 2
+&247 constant CANIDM1 \ Identifier Mask Register 1
+&248 constant CANSTML \ Time Stamp Register Low
+&249 constant CANSTMH \ Time Stamp Register High
+&250 constant CANMSG \ Message Data Register
+\ ANALOG_COMPARATOR
+&148 constant AC0CON \ Analog Comparator 0 Control Register
+ $80 constant AC0CON_AC0EN \ Analog Comparator 0 Enable Bit
+ $40 constant AC0CON_AC0IE \ Analog Comparator 0 Interrupt Enable Bit
+ $30 constant AC0CON_AC0IS \ Analog Comparator 0 Interrupt Select Bits
+ $08 constant AC0CON_ACCKSEL \ Analog Comparator Clock Select
+ $07 constant AC0CON_AC0M \ Analog Comparator 0 Multiplexer Register
+&149 constant AC1CON \ Analog Comparator 1 Control Register
+ $80 constant AC1CON_AC1EN \ Analog Comparator 1 Enable Bit
+ $40 constant AC1CON_AC1IE \ Analog Comparator 1 Interrupt Enable Bit
+ $30 constant AC1CON_AC1IS \ Analog Comparator 1 Interrupt Select Bit
+ $08 constant AC1CON_AC1ICE \ Analog Comparator 1 Interrupt Capture Enable Bit
+ $07 constant AC1CON_AC1M \ Analog Comparator 1 Multiplexer Register
+&150 constant AC2CON \ Analog Comparator 2 Control Register
+ $80 constant AC2CON_AC2EN \ Analog Comparator 2 Enable Bit
+ $40 constant AC2CON_AC2IE \ Analog Comparator 2 Interrupt Enable Bit
+ $30 constant AC2CON_AC2IS \ Analog Comparator 2 Interrupt Select Bit
+ $07 constant AC2CON_AC2M \ Analog Comparator 2 Multiplexer Register
+&151 constant AC3CON \ Analog Comparator 3 Control Register
+ $80 constant AC3CON_AC3EN \ Analog Comparator 3 Enable Bit
+ $40 constant AC3CON_AC3IE \ Analog Comparator 3 Interrupt Enable Bit
+ $30 constant AC3CON_AC3IS \ Analog Comparator 3 Interrupt Select Bit
+ $07 constant AC3CON_AC3M \ Analog Comparator 3 Multiplexer Register
+&80 constant ACSR \ Analog Comparator Status Register
+ $80 constant ACSR_AC3IF \ Analog Comparator 3 Interrupt Flag Bit
+ $40 constant ACSR_AC2IF \ Analog Comparator 2 Interrupt Flag Bit
+ $20 constant ACSR_AC1IF \ Analog Comparator 1 Interrupt Flag Bit
+ $10 constant ACSR_AC0IF \ Analog Comparator 0 Interrupt Flag Bit
+ $08 constant ACSR_AC3O \ Analog Comparator 3 Output Bit
+ $04 constant ACSR_AC2O \ Analog Comparator 2 Output Bit
+ $02 constant ACSR_AC1O \ Analog Comparator 1 Output Bit
+ $01 constant ACSR_AC0O \ Analog Comparator 0 Output Bit
+\ DA_CONVERTER
+&146 constant DACH \ DAC Data Register High Byte
+ $FF constant DACH_DACH \ DAC Data Register High Byte Bits
+&145 constant DACL \ DAC Data Register Low Byte
+ $FF constant DACL_DACL \ DAC Data Register Low Byte Bits
+&144 constant DACON \ DAC Control Register
+ $80 constant DACON_DAATE \ DAC Auto Trigger Enable Bit
+ $70 constant DACON_DATS \ DAC Trigger Selection Bits
+ $04 constant DACON_DALA \ DAC Left Adjust
+ $01 constant DACON_DAEN \ DAC Enable Bit
+\ CPU
+&87 constant SPMCSR \ Store Program Memory Control Register
+ $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
+ $20 constant SPMCSR_SIGRD \ Signature Row Read
+ $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
+ $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
+ $04 constant SPMCSR_PGWRT \ Page Write
+ $02 constant SPMCSR_PGERS \ Page Erase
+ $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
+&95 constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ $08 constant SREG_V \ Two's Complement Overflow Flag
+ $04 constant SREG_N \ Negative Flag
+ $02 constant SREG_Z \ Zero Flag
+ $01 constant SREG_C \ Carry Flag
+&93 constant SP \ Stack Pointer
+&85 constant MCUCR \ MCU Control Register
+ $80 constant MCUCR_SPIPS \ SPI Pin Select
+ $10 constant MCUCR_PUD \ Pull-up disable
+ $02 constant MCUCR_IVSEL \ Interrupt Vector Select
+ $01 constant MCUCR_IVCE \ Interrupt Vector Change Enable
+&84 constant MCUSR \ MCU Status Register
+ $08 constant MCUSR_WDRF \ Watchdog Reset Flag
+ $04 constant MCUSR_BORF \ Brown-out Reset Flag
+ $02 constant MCUSR_EXTRF \ External Reset Flag
+ $01 constant MCUSR_PORF \ Power-on reset flag
+&102 constant OSCCAL \ Oscillator Calibration Value
+&97 constant CLKPR \
+ $80 constant CLKPR_CLKPCE \
+ $0F constant CLKPR_CLKPS \
+&83 constant SMCR \ Sleep Mode Control Register
+ $0E constant SMCR_SM \ Sleep Mode Select bits
+ $01 constant SMCR_SE \ Sleep Enable
+&58 constant GPIOR2 \ General Purpose IO Register 2
+ $FF constant GPIOR2_GPIOR \ General Purpose IO Register 2 bis
+&57 constant GPIOR1 \ General Purpose IO Register 1
+ $FF constant GPIOR1_GPIOR \ General Purpose IO Register 1 bis
+&62 constant GPIOR0 \ General Purpose IO Register 0
+ $80 constant GPIOR0_GPIOR07 \ General Purpose IO Register 0 bit 7
+ $40 constant GPIOR0_GPIOR06 \ General Purpose IO Register 0 bit 6
+ $20 constant GPIOR0_GPIOR05 \ General Purpose IO Register 0 bit 5
+ $10 constant GPIOR0_GPIOR04 \ General Purpose IO Register 0 bit 4
+ $08 constant GPIOR0_GPIOR03 \ General Purpose IO Register 0 bit 3
+ $04 constant GPIOR0_GPIOR02 \ General Purpose IO Register 0 bit 2
+ $02 constant GPIOR0_GPIOR01 \ General Purpose IO Register 0 bit 1
+ $01 constant GPIOR0_GPIOR00 \ General Purpose IO Register 0 bit 0
+&73 constant PLLCSR \ PLL Control And Status Register
+ $04 constant PLLCSR_PLLF \ PLL Factor
+ $02 constant PLLCSR_PLLE \ PLL Enable
+ $01 constant PLLCSR_PLOCK \ PLL Lock Detector
+&100 constant PRR \ Power Reduction Register
+ $40 constant PRR_PRCAN \ Power Reduction CAN
+ $20 constant PRR_PRPSC \ Power Reduction PSC
+ $10 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
+ $08 constant PRR_PRTIM0 \ Power Reduction Timer/Counter0
+ $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
+ $02 constant PRR_PRLIN \ Power Reduction LIN UART
+ $01 constant PRR_PRADC \ Power Reduction ADC
+\ PORTE
+&46 constant PORTE \ Port E Data Register
+&45 constant DDRE \ Port E Data Direction Register
+&44 constant PINE \ Port E Input Pins
+\ TIMER_COUNTER_0
+&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
+ $04 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare Match B Interrupt Enable
+ $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match A Interrupt Enable
+ $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
+&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
+ $04 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare Flag 0B
+ $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0A
+ $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
+&68 constant TCCR0A \ Timer/Counter Control Register A
+ $C0 constant TCCR0A_COM0A \ Compare Output Mode, Phase Correct PWM Mode
+ $30 constant TCCR0A_COM0B \ Compare Output Mode, Fast PWm
+ $03 constant TCCR0A_WGM0 \ Waveform Generation Mode
+&69 constant TCCR0B \ Timer/Counter Control Register B
+ $80 constant TCCR0B_FOC0A \ Force Output Compare A
+ $40 constant TCCR0B_FOC0B \ Force Output Compare B
+ $08 constant TCCR0B_WGM02 \
+ $07 constant TCCR0B_CS0 \ Clock Select
+&70 constant TCNT0 \ Timer/Counter0
+&71 constant OCR0A \ Timer/Counter0 Output Compare Register
+&72 constant OCR0B \ Timer/Counter0 Output Compare Register
+&67 constant GTCCR \ General Timer/Counter Control Register
+ $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
+ $40 constant GTCCR_ICPSEL1 \ Timer1 Input Capture Selection Bit
+ $01 constant GTCCR_PSR10 \ Prescaler Reset Timer/Counter1 and Timer/Counter0
+\ TIMER_COUNTER_1
+&111 constant TIMSK1 \ Timer/Counter Interrupt Mask Register
+ $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
+ $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output CompareB Match Interrupt Enable
+ $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output CompareA Match Interrupt Enable
+ $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
+&54 constant TIFR1 \ Timer/Counter Interrupt Flag register
+ $20 constant TIFR1_ICF1 \ Input Capture Flag 1
+ $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
+ $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
+ $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
+&128 constant TCCR1A \ Timer/Counter1 Control Register A
+ $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
+ $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
+ $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
+&129 constant TCCR1B \ Timer/Counter1 Control Register B
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
+ $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
+&130 constant TCCR1C \ Timer/Counter1 Control Register C
+ $80 constant TCCR1C_FOC1A \
+ $40 constant TCCR1C_FOC1B \
+&132 constant TCNT1 \ Timer/Counter1 Bytes
+&136 constant OCR1A \ Timer/Counter1 Output Compare Register Bytes
+&138 constant OCR1B \ Timer/Counter1 Output Compare Register Bytes
+&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
+\ AD_CONVERTER
+&124 constant ADMUX \ The ADC multiplexer Selection Register
+ $C0 constant ADMUX_REFS \ Reference Selection Bits
+ $20 constant ADMUX_ADLAR \ Left Adjust Result
+ $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
+&122 constant ADCSRA \ The ADC Control and Status register
+ $80 constant ADCSRA_ADEN \ ADC Enable
+ $40 constant ADCSRA_ADSC \ ADC Start Conversion
+ $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
+ $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
+ $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
+ $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
+&120 constant ADC \ ADC Data Register Bytes
+&123 constant ADCSRB \ ADC Control and Status Register B
+ $80 constant ADCSRB_ADHSM \ ADC High Speed Mode
+ $40 constant ADCSRB_ISRCEN \ Current Source Enable
+ $20 constant ADCSRB_AREFEN \ Analog Reference pin Enable
+ $0F constant ADCSRB_ADTS \ ADC Auto Trigger Sources
+&126 constant DIDR0 \ Digital Input Disable Register 0
+ $80 constant DIDR0_ADC7D \ ADC7 Digital input Disable
+ $40 constant DIDR0_ADC6D \ ADC6 Digital input Disable
+ $20 constant DIDR0_ADC5D \ ADC5 Digital input Disable
+ $10 constant DIDR0_ADC4D \ ADC4 Digital input Disable
+ $08 constant DIDR0_ADC3D \ ADC3 Digital input Disable
+ $04 constant DIDR0_ADC2D \ ADC2 Digital input Disable
+ $02 constant DIDR0_ADC1D \ ADC1 Digital input Disable
+ $01 constant DIDR0_ADC0D \ ADC0 Digital input Disable
+&127 constant DIDR1 \ Digital Input Disable Register 0
+ $40 constant DIDR1_AMP2PD \ AMP2P Pin Digital input Disable
+ $20 constant DIDR1_ACMP0D \ ACMP0 Pin Digital input Disable
+ $10 constant DIDR1_AMP0PD \ AMP0P Pin Digital input Disable
+ $08 constant DIDR1_AMP0ND \ AMP0N Pin Digital input Disable
+ $04 constant DIDR1_ADC10D \ ADC10 Pin Digital input Disable
+ $02 constant DIDR1_ADC9D \ ADC9 Pin Digital input Disable
+ $01 constant DIDR1_ADC8D \ ADC8 Pin Digital input Disable
+&117 constant AMP0CSR \
+ $80 constant AMP0CSR_AMP0EN \
+ $40 constant AMP0CSR_AMP0IS \
+ $30 constant AMP0CSR_AMP0G \
+ $08 constant AMP0CSR_AMPCMP0 \ Amplifier 0 - Comparator 0 Connection
+ $07 constant AMP0CSR_AMP0TS \
+&118 constant AMP1CSR \
+ $80 constant AMP1CSR_AMP1EN \
+ $40 constant AMP1CSR_AMP1IS \
+ $30 constant AMP1CSR_AMP1G \
+ $08 constant AMP1CSR_AMPCMP1 \ Amplifier 1 - Comparator 1 Connection
+ $07 constant AMP1CSR_AMP1TS \
+&119 constant AMP2CSR \
+ $80 constant AMP2CSR_AMP2EN \
+ $40 constant AMP2CSR_AMP2IS \
+ $30 constant AMP2CSR_AMP2G \
+ $08 constant AMP2CSR_AMPCMP2 \ Amplifier 2 - Comparator 2 Connection
+ $07 constant AMP2CSR_AMP2TS \
+\ LINUART
+&200 constant LINCR \ LIN Control Register
+ $80 constant LINCR_LSWRES \ Software Reset
+ $40 constant LINCR_LIN13 \ LIN Standard
+ $30 constant LINCR_LCONF \ LIN Configuration bits
+ $08 constant LINCR_LENA \ LIN or UART Enable
+ $07 constant LINCR_LCMD \ LIN Command and Mode bits
+&201 constant LINSIR \ LIN Status and Interrupt Register
+ $E0 constant LINSIR_LIDST \ Identifier Status bits
+ $10 constant LINSIR_LBUSY \ Busy Signal
+ $08 constant LINSIR_LERR \ Error Interrupt
+ $04 constant LINSIR_LIDOK \ Identifier Interrupt
+ $02 constant LINSIR_LTXOK \ Transmit Performed Interrupt
+ $01 constant LINSIR_LRXOK \ Receive Performed Interrupt
+&202 constant LINENIR \ LIN Enable Interrupt Register
+ $08 constant LINENIR_LENERR \ Enable Error Interrupt
+ $04 constant LINENIR_LENIDOK \ Enable Identifier Interrupt
+ $02 constant LINENIR_LENTXOK \ Enable Transmit Performed Interrupt
+ $01 constant LINENIR_LENRXOK \ Enable Receive Performed Interrupt
+&203 constant LINERR \ LIN Error Register
+ $80 constant LINERR_LABORT \ Abort Flag
+ $40 constant LINERR_LTOERR \ Frame Time Out Error Flag
+ $20 constant LINERR_LOVERR \ Overrun Error Flag
+ $10 constant LINERR_LFERR \ Framing Error Flag
+ $08 constant LINERR_LSERR \ Synchronization Error Flag
+ $04 constant LINERR_LPERR \ Parity Error Flag
+ $02 constant LINERR_LCERR \ Checksum Error Flag
+ $01 constant LINERR_LBERR \ Bit Error Flag
+&204 constant LINBTR \ LIN Bit Timing Register
+ $80 constant LINBTR_LDISR \ Disable Bit Timing Resynchronization
+ $3F constant LINBTR_LBT \ LIN Bit Timing bits
+&205 constant LINBRRL \ LIN Baud Rate Low Register
+ $FF constant LINBRRL_LDIV \
+&206 constant LINBRRH \ LIN Baud Rate High Register
+ $0F constant LINBRRH_LDIV \
+&207 constant LINDLR \ LIN Data Length Register
+ $F0 constant LINDLR_LTXDL \ LIN Transmit Data Length bits
+ $0F constant LINDLR_LRXDL \ LIN Receive Data Length bits
+&208 constant LINIDR \ LIN Identifier Register
+ $C0 constant LINIDR_LP \ Parity bits
+ $3F constant LINIDR_LID \ Identifier bit 5 or Data Length bits
+&209 constant LINSEL \ LIN Data Buffer Selection Register
+ $08 constant LINSEL_LAINC \ Auto Increment of Data Buffer Index (Active Low)
+ $07 constant LINSEL_LINDX \ FIFO LIN Data Buffer Index bits
+&210 constant LINDAT \ LIN Data Register
+ $FF constant LINDAT_LDATA \
+\ SPI
+&76 constant SPCR \ SPI Control Register
+ $80 constant SPCR_SPIE \ SPI Interrupt Enable
+ $40 constant SPCR_SPE \ SPI Enable
+ $20 constant SPCR_DORD \ Data Order
+ $10 constant SPCR_MSTR \ Master/Slave Select
+ $08 constant SPCR_CPOL \ Clock polarity
+ $04 constant SPCR_CPHA \ Clock Phase
+ $03 constant SPCR_SPR \ SPI Clock Rate Selects
+&77 constant SPSR \ SPI Status Register
+ $80 constant SPSR_SPIF \ SPI Interrupt Flag
+ $40 constant SPSR_WCOL \ Write Collision Flag
+ $01 constant SPSR_SPI2X \ Double SPI Speed Bit
+&78 constant SPDR \ SPI Data Register
+\ WATCHDOG
+&96 constant WDTCSR \ Watchdog Timer Control Register
+ $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Flag
+ $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Enable
+ $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
+ $10 constant WDTCSR_WDCE \ Watchdog Change Enable
+ $08 constant WDTCSR_WDE \ Watch Dog Enable
+\ EXTERNAL_INTERRUPT
+&105 constant EICRA \ External Interrupt Control Register
+ $C0 constant EICRA_ISC3 \ External Interrupt Sense Control Bit
+ $30 constant EICRA_ISC2 \ External Interrupt Sense Control Bit
+ $0C constant EICRA_ISC1 \ External Interrupt Sense Control 1 Bits
+ $03 constant EICRA_ISC0 \ External Interrupt Sense Control 0 Bits
+&61 constant EIMSK \ External Interrupt Mask Register
+ $0F constant EIMSK_INT \ External Interrupt Request 3 Enable
+&60 constant EIFR \ External Interrupt Flag Register
+ $0F constant EIFR_INTF \ External Interrupt Flags
+&104 constant PCICR \ Pin Change Interrupt Control Register
+ $0F constant PCICR_PCIE \ Pin Change Interrupt Enables
+&109 constant PCMSK3 \ Pin Change Mask Register 3
+ $07 constant PCMSK3_PCINT \ Pin Change Enable Masks
+&108 constant PCMSK2 \ Pin Change Mask Register 2
+ $FF constant PCMSK2_PCINT \ Pin Change Enable Masks
+&107 constant PCMSK1 \ Pin Change Mask Register 1
+ $FF constant PCMSK1_PCINT \ Pin Change Enable Masks
+&106 constant PCMSK0 \ Pin Change Mask Register 0
+ $FF constant PCMSK0_PCINT \ Pin Change Enable Masks
+&59 constant PCIFR \ Pin Change Interrupt Flag Register
+ $0F constant PCIFR_PCIF \ Pin Change Interrupt Flags
+\ EEPROM
+&65 constant EEAR \ EEPROM Read/Write Access
+&64 constant EEDR \ EEPROM Data Register
+&63 constant EECR \ EEPROM Control Register
+ $30 constant EECR_EEPM \
+ $08 constant EECR_EERIE \ EEProm Ready Interrupt Enable
+ $04 constant EECR_EEMWE \ EEPROM Master Write Enable
+ $02 constant EECR_EEWE \ EEPROM Write Enable
+ $01 constant EECR_EERE \ EEPROM Read Enable
+\ PSC
+&188 constant PIFR \ PSC Interrupt Flag Register
+ $0E constant PIFR_PEV \ PSC External Event 2 Interrupt
+ $01 constant PIFR_PEOP \ PSC End of Cycle Interrupt
+&187 constant PIM \ PSC Interrupt Mask Register
+ $0E constant PIM_PEVE \ External Event 2 Interrupt Enable
+ $01 constant PIM_PEOPE \ PSC End of Cycle Interrupt Enable
+&186 constant PMIC2 \ PSC Module 2 Input Control Register
+ $80 constant PMIC2_POVEN2 \ PSC Module 2 Overlap Enable
+ $40 constant PMIC2_PISEL2 \ PSC Module 2 Input Select
+ $20 constant PMIC2_PELEV2 \ PSC Module 2 Input Level Selector
+ $10 constant PMIC2_PFLTE2 \ PSC Module 2 Input Filter Enable
+ $08 constant PMIC2_PAOC2 \ PSC Module 2 Asynchronous Output Control
+ $07 constant PMIC2_PRFM2 \ PSC Module 2 Input Mode bits
+&185 constant PMIC1 \ PSC Module 1 Input Control Register
+ $80 constant PMIC1_POVEN1 \ PSC Module 1 Overlap Enable
+ $40 constant PMIC1_PISEL1 \ PSC Module 1 Input Select
+ $20 constant PMIC1_PELEV1 \ PSC Module 1 Input Level Selector
+ $10 constant PMIC1_PFLTE1 \ PSC Module 1 Input Filter Enable
+ $08 constant PMIC1_PAOC1 \ PSC Module 1 Asynchronous Output Control
+ $07 constant PMIC1_PRFM1 \ PSC Module 1 Input Mode bits
+&184 constant PMIC0 \ PSC Module 0 Input Control Register
+ $80 constant PMIC0_POVEN0 \ PSC Module 0 Overlap Enable
+ $40 constant PMIC0_PISEL0 \ PSC Module 0 Input Select
+ $20 constant PMIC0_PELEV0 \ PSC Module 0 Input Level Selector
+ $10 constant PMIC0_PFLTE0 \ PSC Module 0 Input Filter Enable
+ $08 constant PMIC0_PAOC0 \ PSC Module 0 Asynchronous Output Control
+ $07 constant PMIC0_PRFM0 \ PSC Module 0 Input Mode bits
+&183 constant PCTL \ PSC Control Register
+ $C0 constant PCTL_PPRE \ PSC Prescaler Select bits
+ $20 constant PCTL_PCLKSEL \ PSC Input Clock Select
+ $02 constant PCTL_PCCYC \ PSC Complete Cycle
+ $01 constant PCTL_PRUN \ PSC Run
+&182 constant POC \ PSC Output Configuration
+ $20 constant POC_POEN2B \ PSC Output 2B Enable
+ $10 constant POC_POEN2A \ PSC Output 2A Enable
+ $08 constant POC_POEN1B \ PSC Output 1B Enable
+ $04 constant POC_POEN1A \ PSC Output 1A Enable
+ $02 constant POC_POEN0B \ PSC Output 0B Enable
+ $01 constant POC_POEN0A \ PSC Output 0A Enable
+&181 constant PCNF \ PSC Configuration Register
+ $20 constant PCNF_PULOCK \ PSC Update Lock
+ $10 constant PCNF_PMODE \ PSC Mode
+ $08 constant PCNF_POPB \ PSC Output B Polarity
+ $04 constant PCNF_POPA \ PSC Output A Polarity
+&180 constant PSYNC \ PSC Synchro Configuration
+ $30 constant PSYNC_PSYNC2 \ Selection of Synchronization Out for ADC
+ $0C constant PSYNC_PSYNC1 \ Selection of Synchronization Out for ADC
+ $03 constant PSYNC_PSYNC0 \ Selection of Synchronization Out for ADC
+&178 constant POCR_RB \ PSC Output Compare RB Register
+&176 constant POCR2SB \ PSC Module 2 Output Compare SB Register
+&174 constant POCR2RA \ PSC Module 2 Output Compare RA Register
+&172 constant POCR2SA \ PSC Module 2 Output Compare SA Register
+&170 constant POCR1SB \ PSC Module 1 Output Compare SB Register
+&168 constant POCR1RA \ PSC Module 1 Output Compare RA Register
+&166 constant POCR1SA \ PSC Output Compare SA Register
+&164 constant POCR0SB \ PSC Output Compare SB Register
+&162 constant POCR0RA \ PSC Module 0 Output Compare RA Register
+&160 constant POCR0SA \ PSC Module 0 Output Compare SA Register
+
+\ Interrupts
+&2 constant ANACOMP0Addr \ Analog Comparator 0
+&4 constant ANACOMP1Addr \ Analog Comparator 1
+&6 constant ANACOMP2Addr \ Analog Comparator 2
+&8 constant ANACOMP3Addr \ Analog Comparator 3
+&10 constant PSC_FAULTAddr \ PSC Fault
+&12 constant PSC_ECAddr \ PSC End of Cycle
+&14 constant INT0Addr \ External Interrupt Request 0
+&16 constant INT1Addr \ External Interrupt Request 1
+&18 constant INT2Addr \ External Interrupt Request 2
+&20 constant INT3Addr \ External Interrupt Request 3
+&22 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+&24 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
+&26 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
+&28 constant TIMER1_OVFAddr \ Timer1/Counter1 Overflow
+&30 constant TIMER0_COMPAAddr \ Timer/Counter0 Compare Match A
+&32 constant TIMER0_COMPBAddr \ Timer/Counter0 Compare Match B
+&34 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
+&36 constant CAN_INTAddr \ CAN MOB, Burst, General Errors
+&38 constant CAN_TOVFAddr \ CAN Timer Overflow
+&40 constant LIN_TCAddr \ LIN Transfer Complete
+&42 constant LIN_ERRAddr \ LIN Error
+&44 constant PCINT0Addr \ Pin Change Interrupt Request 0
+&46 constant PCINT1Addr \ Pin Change Interrupt Request 1
+&48 constant PCINT2Addr \ Pin Change Interrupt Request 2
+&50 constant PCINT3Addr \ Pin Change Interrupt Request 3
+&52 constant SPI__STCAddr \ SPI Serial Transfer Complete
+&54 constant ADCAddr \ ADC Conversion Complete
+&56 constant WDTAddr \ Watchdog Time-Out Interrupt
+&58 constant EE_READYAddr \ EEPROM Ready
+&60 constant SPM_READYAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/atmega64m1/device.asm b/amforth-6.5/avr8/devices/atmega64m1/device.asm
new file mode 100644
index 0000000..7441fc3
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega64m1/device.asm
@@ -0,0 +1,120 @@
+; Partname: ATmega64M1
+; generated automatically, do not edit
+
+.nolist
+ .include "m64M1def.inc"
+.list
+
+.equ ramstart = 256
+.equ CELLSIZE = 2
+.macro readflashcell
+ lsl zl
+ rol zh
+ lpm @0, Z+
+ lpm @1, Z+
+.endmacro
+.macro writeflashcell
+ lsl zl
+ rol zh
+.endmacro
+.set WANT_PORTB = 0
+.set WANT_PORTC = 0
+.set WANT_PORTD = 0
+.set WANT_CAN = 0
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_DA_CONVERTER = 0
+.set WANT_CPU = 0
+.set WANT_PORTE = 0
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_AD_CONVERTER = 0
+.set WANT_LINUART = 0
+.set WANT_SPI = 0
+.set WANT_WATCHDOG = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_EEPROM = 0
+.set WANT_PSC = 0
+.equ intvecsize = 2 ; please verify; flash size: 65536 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.org 2
+ rcall isr ; Analog Comparator 0
+.org 4
+ rcall isr ; Analog Comparator 1
+.org 6
+ rcall isr ; Analog Comparator 2
+.org 8
+ rcall isr ; Analog Comparator 3
+.org 10
+ rcall isr ; PSC Fault
+.org 12
+ rcall isr ; PSC End of Cycle
+.org 14
+ rcall isr ; External Interrupt Request 0
+.org 16
+ rcall isr ; External Interrupt Request 1
+.org 18
+ rcall isr ; External Interrupt Request 2
+.org 20
+ rcall isr ; External Interrupt Request 3
+.org 22
+ rcall isr ; Timer/Counter1 Capture Event
+.org 24
+ rcall isr ; Timer/Counter1 Compare Match A
+.org 26
+ rcall isr ; Timer/Counter1 Compare Match B
+.org 28
+ rcall isr ; Timer1/Counter1 Overflow
+.org 30
+ rcall isr ; Timer/Counter0 Compare Match A
+.org 32
+ rcall isr ; Timer/Counter0 Compare Match B
+.org 34
+ rcall isr ; Timer/Counter0 Overflow
+.org 36
+ rcall isr ; CAN MOB, Burst, General Errors
+.org 38
+ rcall isr ; CAN Timer Overflow
+.org 40
+ rcall isr ; LIN Transfer Complete
+.org 42
+ rcall isr ; LIN Error
+.org 44
+ rcall isr ; Pin Change Interrupt Request 0
+.org 46
+ rcall isr ; Pin Change Interrupt Request 1
+.org 48
+ rcall isr ; Pin Change Interrupt Request 2
+.org 50
+ rcall isr ; Pin Change Interrupt Request 3
+.org 52
+ rcall isr ; SPI Serial Transfer Complete
+.org 54
+ rcall isr ; ADC Conversion Complete
+.org 56
+ rcall isr ; Watchdog Time-Out Interrupt
+.org 58
+ rcall isr ; EEPROM Ready
+.org 60
+ rcall isr ; Store Program Memory Read
+.equ INTVECTORS = 31
+.nooverlap
+
+; compatability layer (maybe empty)
+.equ EEPE = EEWE
+.equ EEMPE = EEMWE
+
+; controller data area, environment query mcu-info
+mcu_info:
+mcu_ramsize:
+ .dw 4096
+mcu_eepromsize:
+ .dw 2048
+mcu_maxdp:
+ .dw 57344
+mcu_numints:
+ .dw 31
+mcu_name:
+ .dw 10
+ .db "ATmega64M1"
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega64m1/device.inc b/amforth-6.5/avr8/devices/atmega64m1/device.inc
new file mode 100644
index 0000000..fa67589
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega64m1/device.inc
@@ -0,0 +1,1734 @@
+; Partname: ATmega64M1
+; generated automatically, no not edit
+
+.if WANT_PORTB == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw 37
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw 36
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw 35
+
+.endif
+.if WANT_PORTC == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Register
+VE_PORTC:
+ .dw $ff05
+ .db "PORTC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTC
+XT_PORTC:
+ .dw PFA_DOVARIABLE
+PFA_PORTC:
+ .dw 40
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Direction Register
+VE_DDRC:
+ .dw $ff04
+ .db "DDRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRC
+XT_DDRC:
+ .dw PFA_DOVARIABLE
+PFA_DDRC:
+ .dw 39
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Input Pins
+VE_PINC:
+ .dw $ff04
+ .db "PINC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINC
+XT_PINC:
+ .dw PFA_DOVARIABLE
+PFA_PINC:
+ .dw 38
+
+.endif
+.if WANT_PORTD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw 43
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw 42
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw 41
+
+.endif
+.if WANT_CAN == 1
+; ( -- addr ) System Constant
+; R( -- )
+; CAN General Control Register
+VE_CANGCON:
+ .dw $ff07
+ .db "CANGCON",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANGCON
+XT_CANGCON:
+ .dw PFA_DOVARIABLE
+PFA_CANGCON:
+ .dw 216
+; ( -- addr ) System Constant
+; R( -- )
+; CAN General Status Register
+VE_CANGSTA:
+ .dw $ff07
+ .db "CANGSTA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANGSTA
+XT_CANGSTA:
+ .dw PFA_DOVARIABLE
+PFA_CANGSTA:
+ .dw 217
+; ( -- addr ) System Constant
+; R( -- )
+; CAN General Interrupt Register Flags
+VE_CANGIT:
+ .dw $ff06
+ .db "CANGIT"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANGIT
+XT_CANGIT:
+ .dw PFA_DOVARIABLE
+PFA_CANGIT:
+ .dw 218
+; ( -- addr ) System Constant
+; R( -- )
+; CAN General Interrupt Enable Register
+VE_CANGIE:
+ .dw $ff06
+ .db "CANGIE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANGIE
+XT_CANGIE:
+ .dw PFA_DOVARIABLE
+PFA_CANGIE:
+ .dw 219
+; ( -- addr ) System Constant
+; R( -- )
+; Enable MOb Register 2
+VE_CANEN2:
+ .dw $ff06
+ .db "CANEN2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANEN2
+XT_CANEN2:
+ .dw PFA_DOVARIABLE
+PFA_CANEN2:
+ .dw 220
+; ( -- addr ) System Constant
+; R( -- )
+; Enable MOb Register 1(empty)
+VE_CANEN1:
+ .dw $ff06
+ .db "CANEN1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANEN1
+XT_CANEN1:
+ .dw PFA_DOVARIABLE
+PFA_CANEN1:
+ .dw 221
+; ( -- addr ) System Constant
+; R( -- )
+; Enable Interrupt MOb Register 2
+VE_CANIE2:
+ .dw $ff06
+ .db "CANIE2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANIE2
+XT_CANIE2:
+ .dw PFA_DOVARIABLE
+PFA_CANIE2:
+ .dw 222
+; ( -- addr ) System Constant
+; R( -- )
+; Enable Interrupt MOb Register 1 (empty)
+VE_CANIE1:
+ .dw $ff06
+ .db "CANIE1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANIE1
+XT_CANIE1:
+ .dw PFA_DOVARIABLE
+PFA_CANIE1:
+ .dw 223
+; ( -- addr ) System Constant
+; R( -- )
+; CAN Status Interrupt MOb Register 2
+VE_CANSIT2:
+ .dw $ff07
+ .db "CANSIT2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANSIT2
+XT_CANSIT2:
+ .dw PFA_DOVARIABLE
+PFA_CANSIT2:
+ .dw 224
+; ( -- addr ) System Constant
+; R( -- )
+; CAN Status Interrupt MOb Register 1 (empty)
+VE_CANSIT1:
+ .dw $ff07
+ .db "CANSIT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANSIT1
+XT_CANSIT1:
+ .dw PFA_DOVARIABLE
+PFA_CANSIT1:
+ .dw 225
+; ( -- addr ) System Constant
+; R( -- )
+; CAN Bit Timing Register 1
+VE_CANBT1:
+ .dw $ff06
+ .db "CANBT1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANBT1
+XT_CANBT1:
+ .dw PFA_DOVARIABLE
+PFA_CANBT1:
+ .dw 226
+; ( -- addr ) System Constant
+; R( -- )
+; CAN Bit Timing Register 2
+VE_CANBT2:
+ .dw $ff06
+ .db "CANBT2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANBT2
+XT_CANBT2:
+ .dw PFA_DOVARIABLE
+PFA_CANBT2:
+ .dw 227
+; ( -- addr ) System Constant
+; R( -- )
+; CAN Bit Timing Register 3
+VE_CANBT3:
+ .dw $ff06
+ .db "CANBT3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANBT3
+XT_CANBT3:
+ .dw PFA_DOVARIABLE
+PFA_CANBT3:
+ .dw 228
+; ( -- addr ) System Constant
+; R( -- )
+; Timer Control Register
+VE_CANTCON:
+ .dw $ff07
+ .db "CANTCON",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANTCON
+XT_CANTCON:
+ .dw PFA_DOVARIABLE
+PFA_CANTCON:
+ .dw 229
+; ( -- addr ) System Constant
+; R( -- )
+; Timer Register Low
+VE_CANTIML:
+ .dw $ff07
+ .db "CANTIML",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANTIML
+XT_CANTIML:
+ .dw PFA_DOVARIABLE
+PFA_CANTIML:
+ .dw 230
+; ( -- addr ) System Constant
+; R( -- )
+; Timer Register High
+VE_CANTIMH:
+ .dw $ff07
+ .db "CANTIMH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANTIMH
+XT_CANTIMH:
+ .dw PFA_DOVARIABLE
+PFA_CANTIMH:
+ .dw 231
+; ( -- addr ) System Constant
+; R( -- )
+; TTC Timer Register Low
+VE_CANTTCL:
+ .dw $ff07
+ .db "CANTTCL",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANTTCL
+XT_CANTTCL:
+ .dw PFA_DOVARIABLE
+PFA_CANTTCL:
+ .dw 232
+; ( -- addr ) System Constant
+; R( -- )
+; TTC Timer Register High
+VE_CANTTCH:
+ .dw $ff07
+ .db "CANTTCH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANTTCH
+XT_CANTTCH:
+ .dw PFA_DOVARIABLE
+PFA_CANTTCH:
+ .dw 233
+; ( -- addr ) System Constant
+; R( -- )
+; Transmit Error Counter Register
+VE_CANTEC:
+ .dw $ff06
+ .db "CANTEC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANTEC
+XT_CANTEC:
+ .dw PFA_DOVARIABLE
+PFA_CANTEC:
+ .dw 234
+; ( -- addr ) System Constant
+; R( -- )
+; Receive Error Counter Register
+VE_CANREC:
+ .dw $ff06
+ .db "CANREC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANREC
+XT_CANREC:
+ .dw PFA_DOVARIABLE
+PFA_CANREC:
+ .dw 235
+; ( -- addr ) System Constant
+; R( -- )
+; Highest Priority MOb Register
+VE_CANHPMOB:
+ .dw $ff08
+ .db "CANHPMOB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANHPMOB
+XT_CANHPMOB:
+ .dw PFA_DOVARIABLE
+PFA_CANHPMOB:
+ .dw 236
+; ( -- addr ) System Constant
+; R( -- )
+; Page MOb Register
+VE_CANPAGE:
+ .dw $ff07
+ .db "CANPAGE",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANPAGE
+XT_CANPAGE:
+ .dw PFA_DOVARIABLE
+PFA_CANPAGE:
+ .dw 237
+; ( -- addr ) System Constant
+; R( -- )
+; MOb Status Register
+VE_CANSTMOB:
+ .dw $ff08
+ .db "CANSTMOB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANSTMOB
+XT_CANSTMOB:
+ .dw PFA_DOVARIABLE
+PFA_CANSTMOB:
+ .dw 238
+; ( -- addr ) System Constant
+; R( -- )
+; MOb Control and DLC Register
+VE_CANCDMOB:
+ .dw $ff08
+ .db "CANCDMOB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANCDMOB
+XT_CANCDMOB:
+ .dw PFA_DOVARIABLE
+PFA_CANCDMOB:
+ .dw 239
+; ( -- addr ) System Constant
+; R( -- )
+; Identifier Tag Register 4
+VE_CANIDT4:
+ .dw $ff07
+ .db "CANIDT4",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANIDT4
+XT_CANIDT4:
+ .dw PFA_DOVARIABLE
+PFA_CANIDT4:
+ .dw 240
+; ( -- addr ) System Constant
+; R( -- )
+; Identifier Tag Register 3
+VE_CANIDT3:
+ .dw $ff07
+ .db "CANIDT3",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANIDT3
+XT_CANIDT3:
+ .dw PFA_DOVARIABLE
+PFA_CANIDT3:
+ .dw 241
+; ( -- addr ) System Constant
+; R( -- )
+; Identifier Tag Register 2
+VE_CANIDT2:
+ .dw $ff07
+ .db "CANIDT2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANIDT2
+XT_CANIDT2:
+ .dw PFA_DOVARIABLE
+PFA_CANIDT2:
+ .dw 242
+; ( -- addr ) System Constant
+; R( -- )
+; Identifier Tag Register 1
+VE_CANIDT1:
+ .dw $ff07
+ .db "CANIDT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANIDT1
+XT_CANIDT1:
+ .dw PFA_DOVARIABLE
+PFA_CANIDT1:
+ .dw 243
+; ( -- addr ) System Constant
+; R( -- )
+; Identifier Mask Register 4
+VE_CANIDM4:
+ .dw $ff07
+ .db "CANIDM4",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANIDM4
+XT_CANIDM4:
+ .dw PFA_DOVARIABLE
+PFA_CANIDM4:
+ .dw 244
+; ( -- addr ) System Constant
+; R( -- )
+; Identifier Mask Register 3
+VE_CANIDM3:
+ .dw $ff07
+ .db "CANIDM3",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANIDM3
+XT_CANIDM3:
+ .dw PFA_DOVARIABLE
+PFA_CANIDM3:
+ .dw 245
+; ( -- addr ) System Constant
+; R( -- )
+; Identifier Mask Register 2
+VE_CANIDM2:
+ .dw $ff07
+ .db "CANIDM2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANIDM2
+XT_CANIDM2:
+ .dw PFA_DOVARIABLE
+PFA_CANIDM2:
+ .dw 246
+; ( -- addr ) System Constant
+; R( -- )
+; Identifier Mask Register 1
+VE_CANIDM1:
+ .dw $ff07
+ .db "CANIDM1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANIDM1
+XT_CANIDM1:
+ .dw PFA_DOVARIABLE
+PFA_CANIDM1:
+ .dw 247
+; ( -- addr ) System Constant
+; R( -- )
+; Time Stamp Register Low
+VE_CANSTML:
+ .dw $ff07
+ .db "CANSTML",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANSTML
+XT_CANSTML:
+ .dw PFA_DOVARIABLE
+PFA_CANSTML:
+ .dw 248
+; ( -- addr ) System Constant
+; R( -- )
+; Time Stamp Register High
+VE_CANSTMH:
+ .dw $ff07
+ .db "CANSTMH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANSTMH
+XT_CANSTMH:
+ .dw PFA_DOVARIABLE
+PFA_CANSTMH:
+ .dw 249
+; ( -- addr ) System Constant
+; R( -- )
+; Message Data Register
+VE_CANMSG:
+ .dw $ff06
+ .db "CANMSG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANMSG
+XT_CANMSG:
+ .dw PFA_DOVARIABLE
+PFA_CANMSG:
+ .dw 250
+
+.endif
+.if WANT_ANALOG_COMPARATOR == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator 0 Control Register
+VE_AC0CON:
+ .dw $ff06
+ .db "AC0CON"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_AC0CON
+XT_AC0CON:
+ .dw PFA_DOVARIABLE
+PFA_AC0CON:
+ .dw 148
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator 1 Control Register
+VE_AC1CON:
+ .dw $ff06
+ .db "AC1CON"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_AC1CON
+XT_AC1CON:
+ .dw PFA_DOVARIABLE
+PFA_AC1CON:
+ .dw 149
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator 2 Control Register
+VE_AC2CON:
+ .dw $ff06
+ .db "AC2CON"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_AC2CON
+XT_AC2CON:
+ .dw PFA_DOVARIABLE
+PFA_AC2CON:
+ .dw 150
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator 3 Control Register
+VE_AC3CON:
+ .dw $ff06
+ .db "AC3CON"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_AC3CON
+XT_AC3CON:
+ .dw PFA_DOVARIABLE
+PFA_AC3CON:
+ .dw 151
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw 80
+
+.endif
+.if WANT_DA_CONVERTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; DAC Data Register High Byte
+VE_DACH:
+ .dw $ff04
+ .db "DACH"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DACH
+XT_DACH:
+ .dw PFA_DOVARIABLE
+PFA_DACH:
+ .dw 146
+; ( -- addr ) System Constant
+; R( -- )
+; DAC Data Register Low Byte
+VE_DACL:
+ .dw $ff04
+ .db "DACL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DACL
+XT_DACL:
+ .dw PFA_DOVARIABLE
+PFA_DACL:
+ .dw 145
+; ( -- addr ) System Constant
+; R( -- )
+; DAC Control Register
+VE_DACON:
+ .dw $ff05
+ .db "DACON",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DACON
+XT_DACON:
+ .dw PFA_DOVARIABLE
+PFA_DACON:
+ .dw 144
+
+.endif
+.if WANT_CPU == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control Register
+VE_SPMCSR:
+ .dw $ff06
+ .db "SPMCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCSR
+XT_SPMCSR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCSR:
+ .dw 87
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw 95
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer
+VE_SP:
+ .dw $ff02
+ .db "SP"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SP
+XT_SP:
+ .dw PFA_DOVARIABLE
+PFA_SP:
+ .dw 93
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw 85
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Status Register
+VE_MCUSR:
+ .dw $ff05
+ .db "MCUSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUSR
+XT_MCUSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUSR:
+ .dw 84
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Calibration Value
+VE_OSCCAL:
+ .dw $ff06
+ .db "OSCCAL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSCCAL
+XT_OSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_OSCCAL:
+ .dw 102
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_CLKPR:
+ .dw $ff05
+ .db "CLKPR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKPR
+XT_CLKPR:
+ .dw PFA_DOVARIABLE
+PFA_CLKPR:
+ .dw 97
+; ( -- addr ) System Constant
+; R( -- )
+; Sleep Mode Control Register
+VE_SMCR:
+ .dw $ff04
+ .db "SMCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SMCR
+XT_SMCR:
+ .dw PFA_DOVARIABLE
+PFA_SMCR:
+ .dw 83
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 2
+VE_GPIOR2:
+ .dw $ff06
+ .db "GPIOR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR2
+XT_GPIOR2:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR2:
+ .dw 58
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 1
+VE_GPIOR1:
+ .dw $ff06
+ .db "GPIOR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR1
+XT_GPIOR1:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR1:
+ .dw 57
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 0
+VE_GPIOR0:
+ .dw $ff06
+ .db "GPIOR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR0
+XT_GPIOR0:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR0:
+ .dw 62
+; ( -- addr ) System Constant
+; R( -- )
+; PLL Control And Status Register
+VE_PLLCSR:
+ .dw $ff06
+ .db "PLLCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PLLCSR
+XT_PLLCSR:
+ .dw PFA_DOVARIABLE
+PFA_PLLCSR:
+ .dw 73
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register
+VE_PRR:
+ .dw $ff03
+ .db "PRR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR
+XT_PRR:
+ .dw PFA_DOVARIABLE
+PFA_PRR:
+ .dw 100
+
+.endif
+.if WANT_PORTE == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port E Data Register
+VE_PORTE:
+ .dw $ff05
+ .db "PORTE",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTE
+XT_PORTE:
+ .dw PFA_DOVARIABLE
+PFA_PORTE:
+ .dw 46
+; ( -- addr ) System Constant
+; R( -- )
+; Port E Data Direction Register
+VE_DDRE:
+ .dw $ff04
+ .db "DDRE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRE
+XT_DDRE:
+ .dw PFA_DOVARIABLE
+PFA_DDRE:
+ .dw 45
+; ( -- addr ) System Constant
+; R( -- )
+; Port E Input Pins
+VE_PINE:
+ .dw $ff04
+ .db "PINE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINE
+XT_PINE:
+ .dw PFA_DOVARIABLE
+PFA_PINE:
+ .dw 44
+
+.endif
+.if WANT_TIMER_COUNTER_0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Mask Register
+VE_TIMSK0:
+ .dw $ff06
+ .db "TIMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK0
+XT_TIMSK0:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK0:
+ .dw 110
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Flag register
+VE_TIFR0:
+ .dw $ff05
+ .db "TIFR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR0
+XT_TIFR0:
+ .dw PFA_DOVARIABLE
+PFA_TIFR0:
+ .dw 53
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register A
+VE_TCCR0A:
+ .dw $ff06
+ .db "TCCR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0A
+XT_TCCR0A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0A:
+ .dw 68
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register B
+VE_TCCR0B:
+ .dw $ff06
+ .db "TCCR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0B
+XT_TCCR0B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0B:
+ .dw 69
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw 70
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0A:
+ .dw $ff05
+ .db "OCR0A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0A
+XT_OCR0A:
+ .dw PFA_DOVARIABLE
+PFA_OCR0A:
+ .dw 71
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0B:
+ .dw $ff05
+ .db "OCR0B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0B
+XT_OCR0B:
+ .dw PFA_DOVARIABLE
+PFA_OCR0B:
+ .dw 72
+; ( -- addr ) System Constant
+; R( -- )
+; General Timer/Counter Control Register
+VE_GTCCR:
+ .dw $ff05
+ .db "GTCCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GTCCR
+XT_GTCCR:
+ .dw PFA_DOVARIABLE
+PFA_GTCCR:
+ .dw 67
+
+.endif
+.if WANT_TIMER_COUNTER_1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Mask Register
+VE_TIMSK1:
+ .dw $ff06
+ .db "TIMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK1
+XT_TIMSK1:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK1:
+ .dw 111
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Flag register
+VE_TIFR1:
+ .dw $ff05
+ .db "TIFR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR1
+XT_TIFR1:
+ .dw PFA_DOVARIABLE
+PFA_TIFR1:
+ .dw 54
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw 128
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw 129
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register C
+VE_TCCR1C:
+ .dw $ff06
+ .db "TCCR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1C
+XT_TCCR1C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1C:
+ .dw 130
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Bytes
+VE_TCNT1:
+ .dw $ff05
+ .db "TCNT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1
+XT_TCNT1:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1:
+ .dw 132
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register Bytes
+VE_OCR1A:
+ .dw $ff05
+ .db "OCR1A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1A
+XT_OCR1A:
+ .dw PFA_DOVARIABLE
+PFA_OCR1A:
+ .dw 136
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register Bytes
+VE_OCR1B:
+ .dw $ff05
+ .db "OCR1B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1B
+XT_OCR1B:
+ .dw PFA_DOVARIABLE
+PFA_OCR1B:
+ .dw 138
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Bytes
+VE_ICR1:
+ .dw $ff04
+ .db "ICR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1
+XT_ICR1:
+ .dw PFA_DOVARIABLE
+PFA_ICR1:
+ .dw 134
+
+.endif
+.if WANT_AD_CONVERTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC multiplexer Selection Register
+VE_ADMUX:
+ .dw $ff05
+ .db "ADMUX",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADMUX
+XT_ADMUX:
+ .dw PFA_DOVARIABLE
+PFA_ADMUX:
+ .dw 124
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register
+VE_ADCSRA:
+ .dw $ff06
+ .db "ADCSRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRA
+XT_ADCSRA:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRA:
+ .dw 122
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register Bytes
+VE_ADC:
+ .dw $ff03
+ .db "ADC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADC
+XT_ADC:
+ .dw PFA_DOVARIABLE
+PFA_ADC:
+ .dw 120
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Control and Status Register B
+VE_ADCSRB:
+ .dw $ff06
+ .db "ADCSRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRB
+XT_ADCSRB:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRB:
+ .dw 123
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 0
+VE_DIDR0:
+ .dw $ff05
+ .db "DIDR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR0
+XT_DIDR0:
+ .dw PFA_DOVARIABLE
+PFA_DIDR0:
+ .dw 126
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 0
+VE_DIDR1:
+ .dw $ff05
+ .db "DIDR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR1
+XT_DIDR1:
+ .dw PFA_DOVARIABLE
+PFA_DIDR1:
+ .dw 127
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_AMP0CSR:
+ .dw $ff07
+ .db "AMP0CSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_AMP0CSR
+XT_AMP0CSR:
+ .dw PFA_DOVARIABLE
+PFA_AMP0CSR:
+ .dw 117
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_AMP1CSR:
+ .dw $ff07
+ .db "AMP1CSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_AMP1CSR
+XT_AMP1CSR:
+ .dw PFA_DOVARIABLE
+PFA_AMP1CSR:
+ .dw 118
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_AMP2CSR:
+ .dw $ff07
+ .db "AMP2CSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_AMP2CSR
+XT_AMP2CSR:
+ .dw PFA_DOVARIABLE
+PFA_AMP2CSR:
+ .dw 119
+
+.endif
+.if WANT_LINUART == 1
+; ( -- addr ) System Constant
+; R( -- )
+; LIN Control Register
+VE_LINCR:
+ .dw $ff05
+ .db "LINCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LINCR
+XT_LINCR:
+ .dw PFA_DOVARIABLE
+PFA_LINCR:
+ .dw 200
+; ( -- addr ) System Constant
+; R( -- )
+; LIN Status and Interrupt Register
+VE_LINSIR:
+ .dw $ff06
+ .db "LINSIR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LINSIR
+XT_LINSIR:
+ .dw PFA_DOVARIABLE
+PFA_LINSIR:
+ .dw 201
+; ( -- addr ) System Constant
+; R( -- )
+; LIN Enable Interrupt Register
+VE_LINENIR:
+ .dw $ff07
+ .db "LINENIR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LINENIR
+XT_LINENIR:
+ .dw PFA_DOVARIABLE
+PFA_LINENIR:
+ .dw 202
+; ( -- addr ) System Constant
+; R( -- )
+; LIN Error Register
+VE_LINERR:
+ .dw $ff06
+ .db "LINERR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LINERR
+XT_LINERR:
+ .dw PFA_DOVARIABLE
+PFA_LINERR:
+ .dw 203
+; ( -- addr ) System Constant
+; R( -- )
+; LIN Bit Timing Register
+VE_LINBTR:
+ .dw $ff06
+ .db "LINBTR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LINBTR
+XT_LINBTR:
+ .dw PFA_DOVARIABLE
+PFA_LINBTR:
+ .dw 204
+; ( -- addr ) System Constant
+; R( -- )
+; LIN Baud Rate Low Register
+VE_LINBRRL:
+ .dw $ff07
+ .db "LINBRRL",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LINBRRL
+XT_LINBRRL:
+ .dw PFA_DOVARIABLE
+PFA_LINBRRL:
+ .dw 205
+; ( -- addr ) System Constant
+; R( -- )
+; LIN Baud Rate High Register
+VE_LINBRRH:
+ .dw $ff07
+ .db "LINBRRH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LINBRRH
+XT_LINBRRH:
+ .dw PFA_DOVARIABLE
+PFA_LINBRRH:
+ .dw 206
+; ( -- addr ) System Constant
+; R( -- )
+; LIN Data Length Register
+VE_LINDLR:
+ .dw $ff06
+ .db "LINDLR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LINDLR
+XT_LINDLR:
+ .dw PFA_DOVARIABLE
+PFA_LINDLR:
+ .dw 207
+; ( -- addr ) System Constant
+; R( -- )
+; LIN Identifier Register
+VE_LINIDR:
+ .dw $ff06
+ .db "LINIDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LINIDR
+XT_LINIDR:
+ .dw PFA_DOVARIABLE
+PFA_LINIDR:
+ .dw 208
+; ( -- addr ) System Constant
+; R( -- )
+; LIN Data Buffer Selection Register
+VE_LINSEL:
+ .dw $ff06
+ .db "LINSEL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LINSEL
+XT_LINSEL:
+ .dw PFA_DOVARIABLE
+PFA_LINSEL:
+ .dw 209
+; ( -- addr ) System Constant
+; R( -- )
+; LIN Data Register
+VE_LINDAT:
+ .dw $ff06
+ .db "LINDAT"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LINDAT
+XT_LINDAT:
+ .dw PFA_DOVARIABLE
+PFA_LINDAT:
+ .dw 210
+
+.endif
+.if WANT_SPI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR:
+ .dw $ff04
+ .db "SPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR
+XT_SPCR:
+ .dw PFA_DOVARIABLE
+PFA_SPCR:
+ .dw 76
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR:
+ .dw $ff04
+ .db "SPSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR
+XT_SPSR:
+ .dw PFA_DOVARIABLE
+PFA_SPSR:
+ .dw 77
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR:
+ .dw $ff04
+ .db "SPDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR
+XT_SPDR:
+ .dw PFA_DOVARIABLE
+PFA_SPDR:
+ .dw 78
+
+.endif
+.if WANT_WATCHDOG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCSR:
+ .dw $ff06
+ .db "WDTCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCSR
+XT_WDTCSR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCSR:
+ .dw 96
+
+.endif
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register
+VE_EICRA:
+ .dw $ff05
+ .db "EICRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRA
+XT_EICRA:
+ .dw PFA_DOVARIABLE
+PFA_EICRA:
+ .dw 105
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Mask Register
+VE_EIMSK:
+ .dw $ff05
+ .db "EIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIMSK
+XT_EIMSK:
+ .dw PFA_DOVARIABLE
+PFA_EIMSK:
+ .dw 61
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Flag Register
+VE_EIFR:
+ .dw $ff04
+ .db "EIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIFR
+XT_EIFR:
+ .dw PFA_DOVARIABLE
+PFA_EIFR:
+ .dw 60
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Interrupt Control Register
+VE_PCICR:
+ .dw $ff05
+ .db "PCICR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCICR
+XT_PCICR:
+ .dw PFA_DOVARIABLE
+PFA_PCICR:
+ .dw 104
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 3
+VE_PCMSK3:
+ .dw $ff06
+ .db "PCMSK3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK3
+XT_PCMSK3:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK3:
+ .dw 109
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 2
+VE_PCMSK2:
+ .dw $ff06
+ .db "PCMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK2
+XT_PCMSK2:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK2:
+ .dw 108
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 1
+VE_PCMSK1:
+ .dw $ff06
+ .db "PCMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK1
+XT_PCMSK1:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK1:
+ .dw 107
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 0
+VE_PCMSK0:
+ .dw $ff06
+ .db "PCMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK0
+XT_PCMSK0:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK0:
+ .dw 106
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Interrupt Flag Register
+VE_PCIFR:
+ .dw $ff05
+ .db "PCIFR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCIFR
+XT_PCIFR:
+ .dw PFA_DOVARIABLE
+PFA_PCIFR:
+ .dw 59
+
+.endif
+.if WANT_EEPROM == 1
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Read/Write Access
+VE_EEAR:
+ .dw $ff04
+ .db "EEAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEAR
+XT_EEAR:
+ .dw PFA_DOVARIABLE
+PFA_EEAR:
+ .dw 65
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw 64
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw 63
+
+.endif
+.if WANT_PSC == 1
+; ( -- addr ) System Constant
+; R( -- )
+; PSC Interrupt Flag Register
+VE_PIFR:
+ .dw $ff04
+ .db "PIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIFR
+XT_PIFR:
+ .dw PFA_DOVARIABLE
+PFA_PIFR:
+ .dw 188
+; ( -- addr ) System Constant
+; R( -- )
+; PSC Interrupt Mask Register
+VE_PIM:
+ .dw $ff03
+ .db "PIM",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIM
+XT_PIM:
+ .dw PFA_DOVARIABLE
+PFA_PIM:
+ .dw 187
+; ( -- addr ) System Constant
+; R( -- )
+; PSC Module 2 Input Control Register
+VE_PMIC2:
+ .dw $ff05
+ .db "PMIC2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PMIC2
+XT_PMIC2:
+ .dw PFA_DOVARIABLE
+PFA_PMIC2:
+ .dw 186
+; ( -- addr ) System Constant
+; R( -- )
+; PSC Module 1 Input Control Register
+VE_PMIC1:
+ .dw $ff05
+ .db "PMIC1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PMIC1
+XT_PMIC1:
+ .dw PFA_DOVARIABLE
+PFA_PMIC1:
+ .dw 185
+; ( -- addr ) System Constant
+; R( -- )
+; PSC Module 0 Input Control Register
+VE_PMIC0:
+ .dw $ff05
+ .db "PMIC0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PMIC0
+XT_PMIC0:
+ .dw PFA_DOVARIABLE
+PFA_PMIC0:
+ .dw 184
+; ( -- addr ) System Constant
+; R( -- )
+; PSC Control Register
+VE_PCTL:
+ .dw $ff04
+ .db "PCTL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCTL
+XT_PCTL:
+ .dw PFA_DOVARIABLE
+PFA_PCTL:
+ .dw 183
+; ( -- addr ) System Constant
+; R( -- )
+; PSC Output Configuration
+VE_POC:
+ .dw $ff03
+ .db "POC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_POC
+XT_POC:
+ .dw PFA_DOVARIABLE
+PFA_POC:
+ .dw 182
+; ( -- addr ) System Constant
+; R( -- )
+; PSC Configuration Register
+VE_PCNF:
+ .dw $ff04
+ .db "PCNF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCNF
+XT_PCNF:
+ .dw PFA_DOVARIABLE
+PFA_PCNF:
+ .dw 181
+; ( -- addr ) System Constant
+; R( -- )
+; PSC Synchro Configuration
+VE_PSYNC:
+ .dw $ff05
+ .db "PSYNC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PSYNC
+XT_PSYNC:
+ .dw PFA_DOVARIABLE
+PFA_PSYNC:
+ .dw 180
+; ( -- addr ) System Constant
+; R( -- )
+; PSC Output Compare RB Register
+VE_POCR_RB:
+ .dw $ff07
+ .db "POCR_RB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_POCR_RB
+XT_POCR_RB:
+ .dw PFA_DOVARIABLE
+PFA_POCR_RB:
+ .dw 178
+; ( -- addr ) System Constant
+; R( -- )
+; PSC Module 2 Output Compare SB Register
+VE_POCR2SB:
+ .dw $ff07
+ .db "POCR2SB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_POCR2SB
+XT_POCR2SB:
+ .dw PFA_DOVARIABLE
+PFA_POCR2SB:
+ .dw 176
+; ( -- addr ) System Constant
+; R( -- )
+; PSC Module 2 Output Compare RA Register
+VE_POCR2RA:
+ .dw $ff07
+ .db "POCR2RA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_POCR2RA
+XT_POCR2RA:
+ .dw PFA_DOVARIABLE
+PFA_POCR2RA:
+ .dw 174
+; ( -- addr ) System Constant
+; R( -- )
+; PSC Module 2 Output Compare SA Register
+VE_POCR2SA:
+ .dw $ff07
+ .db "POCR2SA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_POCR2SA
+XT_POCR2SA:
+ .dw PFA_DOVARIABLE
+PFA_POCR2SA:
+ .dw 172
+; ( -- addr ) System Constant
+; R( -- )
+; PSC Module 1 Output Compare SB Register
+VE_POCR1SB:
+ .dw $ff07
+ .db "POCR1SB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_POCR1SB
+XT_POCR1SB:
+ .dw PFA_DOVARIABLE
+PFA_POCR1SB:
+ .dw 170
+; ( -- addr ) System Constant
+; R( -- )
+; PSC Module 1 Output Compare RA Register
+VE_POCR1RA:
+ .dw $ff07
+ .db "POCR1RA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_POCR1RA
+XT_POCR1RA:
+ .dw PFA_DOVARIABLE
+PFA_POCR1RA:
+ .dw 168
+; ( -- addr ) System Constant
+; R( -- )
+; PSC Output Compare SA Register
+VE_POCR1SA:
+ .dw $ff07
+ .db "POCR1SA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_POCR1SA
+XT_POCR1SA:
+ .dw PFA_DOVARIABLE
+PFA_POCR1SA:
+ .dw 166
+; ( -- addr ) System Constant
+; R( -- )
+; PSC Output Compare SB Register
+VE_POCR0SB:
+ .dw $ff07
+ .db "POCR0SB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_POCR0SB
+XT_POCR0SB:
+ .dw PFA_DOVARIABLE
+PFA_POCR0SB:
+ .dw 164
+; ( -- addr ) System Constant
+; R( -- )
+; PSC Module 0 Output Compare RA Register
+VE_POCR0RA:
+ .dw $ff07
+ .db "POCR0RA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_POCR0RA
+XT_POCR0RA:
+ .dw PFA_DOVARIABLE
+PFA_POCR0RA:
+ .dw 162
+; ( -- addr ) System Constant
+; R( -- )
+; PSC Module 0 Output Compare SA Register
+VE_POCR0SA:
+ .dw $ff07
+ .db "POCR0SA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_POCR0SA
+XT_POCR0SA:
+ .dw PFA_DOVARIABLE
+PFA_POCR0SA:
+ .dw 160
+
+.endif
diff --git a/amforth-6.5/avr8/devices/atmega64m1/device.py b/amforth-6.5/avr8/devices/atmega64m1/device.py
new file mode 100644
index 0000000..c6482be
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega64m1/device.py
@@ -0,0 +1,495 @@
+# Partname: ATmega64M1
+# generated automatically, do not edit
+MCUREGS = {
+ 'PORTB': '&37',
+ 'DDRB': '&36',
+ 'PINB': '&35',
+ 'PORTC': '&40',
+ 'DDRC': '&39',
+ 'PINC': '&38',
+ 'PORTD': '&43',
+ 'DDRD': '&42',
+ 'PIND': '&41',
+ 'CANGCON': '&216',
+ 'CANGCON_ABRQ': '$80',
+ 'CANGCON_OVRQ': '$40',
+ 'CANGCON_TTC': '$20',
+ 'CANGCON_SYNTTC': '$10',
+ 'CANGCON_LISTEN': '$08',
+ 'CANGCON_TEST': '$04',
+ 'CANGCON_ENASTB': '$02',
+ 'CANGCON_SWRES': '$01',
+ 'CANGSTA': '&217',
+ 'CANGSTA_OVFG': '$40',
+ 'CANGSTA_TXBSY': '$10',
+ 'CANGSTA_RXBSY': '$08',
+ 'CANGSTA_ENFG': '$04',
+ 'CANGSTA_BOFF': '$02',
+ 'CANGSTA_ERRP': '$01',
+ 'CANGIT': '&218',
+ 'CANGIT_CANIT': '$80',
+ 'CANGIT_BOFFIT': '$40',
+ 'CANGIT_OVRTIM': '$20',
+ 'CANGIT_BXOK': '$10',
+ 'CANGIT_SERG': '$08',
+ 'CANGIT_CERG': '$04',
+ 'CANGIT_FERG': '$02',
+ 'CANGIT_AERG': '$01',
+ 'CANGIE': '&219',
+ 'CANGIE_ENIT': '$80',
+ 'CANGIE_ENBOFF': '$40',
+ 'CANGIE_ENRX': '$20',
+ 'CANGIE_ENTX': '$10',
+ 'CANGIE_ENERR': '$08',
+ 'CANGIE_ENBX': '$04',
+ 'CANGIE_ENERG': '$02',
+ 'CANGIE_ENOVRT': '$01',
+ 'CANEN2': '&220',
+ 'CANEN2_ENMOB': '$3F',
+ 'CANEN1': '&221',
+ 'CANIE2': '&222',
+ 'CANIE2_IEMOB': '$3F',
+ 'CANIE1': '&223',
+ 'CANSIT2': '&224',
+ 'CANSIT2_SIT': '$3F',
+ 'CANSIT1': '&225',
+ 'CANBT1': '&226',
+ 'CANBT1_BRP': '$7E',
+ 'CANBT2': '&227',
+ 'CANBT2_SJW': '$60',
+ 'CANBT2_PRS': '$0E',
+ 'CANBT3': '&228',
+ 'CANBT3_PHS2': '$70',
+ 'CANBT3_PHS1': '$0E',
+ 'CANBT3_SMP': '$01',
+ 'CANTCON': '&229',
+ 'CANTIML': '&230',
+ 'CANTIMH': '&231',
+ 'CANTTCL': '&232',
+ 'CANTTCH': '&233',
+ 'CANTEC': '&234',
+ 'CANREC': '&235',
+ 'CANHPMOB': '&236',
+ 'CANHPMOB_HPMOB': '$F0',
+ 'CANHPMOB_CGP': '$0F',
+ 'CANPAGE': '&237',
+ 'CANPAGE_MOBNB': '$F0',
+ 'CANPAGE_AINC': '$08',
+ 'CANPAGE_INDX': '$07',
+ 'CANSTMOB': '&238',
+ 'CANSTMOB_DLCW': '$80',
+ 'CANSTMOB_TXOK': '$40',
+ 'CANSTMOB_RXOK': '$20',
+ 'CANSTMOB_BERR': '$10',
+ 'CANSTMOB_SERR': '$08',
+ 'CANSTMOB_CERR': '$04',
+ 'CANSTMOB_FERR': '$02',
+ 'CANSTMOB_AERR': '$01',
+ 'CANCDMOB': '&239',
+ 'CANCDMOB_CONMOB': '$C0',
+ 'CANCDMOB_RPLV': '$20',
+ 'CANCDMOB_IDE': '$10',
+ 'CANCDMOB_DLC': '$0F',
+ 'CANIDT4': '&240',
+ 'CANIDT4_IDT': '$F8',
+ 'CANIDT4_RTRTAG': '$04',
+ 'CANIDT4_RB1TAG': '$02',
+ 'CANIDT4_RB0TAG': '$01',
+ 'CANIDT3': '&241',
+ 'CANIDT2': '&242',
+ 'CANIDT1': '&243',
+ 'CANIDM4': '&244',
+ 'CANIDM3': '&245',
+ 'CANIDM2': '&246',
+ 'CANIDM1': '&247',
+ 'CANSTML': '&248',
+ 'CANSTMH': '&249',
+ 'CANMSG': '&250',
+ 'AC0CON': '&148',
+ 'AC0CON_AC0EN': '$80',
+ 'AC0CON_AC0IE': '$40',
+ 'AC0CON_AC0IS': '$30',
+ 'AC0CON_ACCKSEL': '$08',
+ 'AC0CON_AC0M': '$07',
+ 'AC1CON': '&149',
+ 'AC1CON_AC1EN': '$80',
+ 'AC1CON_AC1IE': '$40',
+ 'AC1CON_AC1IS': '$30',
+ 'AC1CON_AC1ICE': '$08',
+ 'AC1CON_AC1M': '$07',
+ 'AC2CON': '&150',
+ 'AC2CON_AC2EN': '$80',
+ 'AC2CON_AC2IE': '$40',
+ 'AC2CON_AC2IS': '$30',
+ 'AC2CON_AC2M': '$07',
+ 'AC3CON': '&151',
+ 'AC3CON_AC3EN': '$80',
+ 'AC3CON_AC3IE': '$40',
+ 'AC3CON_AC3IS': '$30',
+ 'AC3CON_AC3M': '$07',
+ 'ACSR': '&80',
+ 'ACSR_AC3IF': '$80',
+ 'ACSR_AC2IF': '$40',
+ 'ACSR_AC1IF': '$20',
+ 'ACSR_AC0IF': '$10',
+ 'ACSR_AC3O': '$08',
+ 'ACSR_AC2O': '$04',
+ 'ACSR_AC1O': '$02',
+ 'ACSR_AC0O': '$01',
+ 'DACH': '&146',
+ 'DACH_DACH': '$FF',
+ 'DACL': '&145',
+ 'DACL_DACL': '$FF',
+ 'DACON': '&144',
+ 'DACON_DAATE': '$80',
+ 'DACON_DATS': '$70',
+ 'DACON_DALA': '$04',
+ 'DACON_DAEN': '$01',
+ 'SPMCSR': '&87',
+ 'SPMCSR_SPMIE': '$80',
+ 'SPMCSR_RWWSB': '$40',
+ 'SPMCSR_SIGRD': '$20',
+ 'SPMCSR_RWWSRE': '$10',
+ 'SPMCSR_BLBSET': '$08',
+ 'SPMCSR_PGWRT': '$04',
+ 'SPMCSR_PGERS': '$02',
+ 'SPMCSR_SPMEN': '$01',
+ 'SREG': '&95',
+ 'SREG_I': '$80',
+ 'SREG_T': '$40',
+ 'SREG_H': '$20',
+ 'SREG_S': '$10',
+ 'SREG_V': '$08',
+ 'SREG_N': '$04',
+ 'SREG_Z': '$02',
+ 'SREG_C': '$01',
+ 'SP': '&93',
+ 'MCUCR': '&85',
+ 'MCUCR_SPIPS': '$80',
+ 'MCUCR_PUD': '$10',
+ 'MCUCR_IVSEL': '$02',
+ 'MCUCR_IVCE': '$01',
+ 'MCUSR': '&84',
+ 'MCUSR_WDRF': '$08',
+ 'MCUSR_BORF': '$04',
+ 'MCUSR_EXTRF': '$02',
+ 'MCUSR_PORF': '$01',
+ 'OSCCAL': '&102',
+ 'CLKPR': '&97',
+ 'CLKPR_CLKPCE': '$80',
+ 'CLKPR_CLKPS': '$0F',
+ 'SMCR': '&83',
+ 'SMCR_SM': '$0E',
+ 'SMCR_SE': '$01',
+ 'GPIOR2': '&58',
+ 'GPIOR2_GPIOR': '$FF',
+ 'GPIOR1': '&57',
+ 'GPIOR1_GPIOR': '$FF',
+ 'GPIOR0': '&62',
+ 'GPIOR0_GPIOR07': '$80',
+ 'GPIOR0_GPIOR06': '$40',
+ 'GPIOR0_GPIOR05': '$20',
+ 'GPIOR0_GPIOR04': '$10',
+ 'GPIOR0_GPIOR03': '$08',
+ 'GPIOR0_GPIOR02': '$04',
+ 'GPIOR0_GPIOR01': '$02',
+ 'GPIOR0_GPIOR00': '$01',
+ 'PLLCSR': '&73',
+ 'PLLCSR_PLLF': '$04',
+ 'PLLCSR_PLLE': '$02',
+ 'PLLCSR_PLOCK': '$01',
+ 'PRR': '&100',
+ 'PRR_PRCAN': '$40',
+ 'PRR_PRPSC': '$20',
+ 'PRR_PRTIM1': '$10',
+ 'PRR_PRTIM0': '$08',
+ 'PRR_PRSPI': '$04',
+ 'PRR_PRLIN': '$02',
+ 'PRR_PRADC': '$01',
+ 'PORTE': '&46',
+ 'DDRE': '&45',
+ 'PINE': '&44',
+ 'TIMSK0': '&110',
+ 'TIMSK0_OCIE0B': '$04',
+ 'TIMSK0_OCIE0A': '$02',
+ 'TIMSK0_TOIE0': '$01',
+ 'TIFR0': '&53',
+ 'TIFR0_OCF0B': '$04',
+ 'TIFR0_OCF0A': '$02',
+ 'TIFR0_TOV0': '$01',
+ 'TCCR0A': '&68',
+ 'TCCR0A_COM0A': '$C0',
+ 'TCCR0A_COM0B': '$30',
+ 'TCCR0A_WGM0': '$03',
+ 'TCCR0B': '&69',
+ 'TCCR0B_FOC0A': '$80',
+ 'TCCR0B_FOC0B': '$40',
+ 'TCCR0B_WGM02': '$08',
+ 'TCCR0B_CS0': '$07',
+ 'TCNT0': '&70',
+ 'OCR0A': '&71',
+ 'OCR0B': '&72',
+ 'GTCCR': '&67',
+ 'GTCCR_TSM': '$80',
+ 'GTCCR_ICPSEL1': '$40',
+ 'GTCCR_PSR10': '$01',
+ 'TIMSK1': '&111',
+ 'TIMSK1_ICIE1': '$20',
+ 'TIMSK1_OCIE1B': '$04',
+ 'TIMSK1_OCIE1A': '$02',
+ 'TIMSK1_TOIE1': '$01',
+ 'TIFR1': '&54',
+ 'TIFR1_ICF1': '$20',
+ 'TIFR1_OCF1B': '$04',
+ 'TIFR1_OCF1A': '$02',
+ 'TIFR1_TOV1': '$01',
+ 'TCCR1A': '&128',
+ 'TCCR1A_COM1A': '$C0',
+ 'TCCR1A_COM1B': '$30',
+ 'TCCR1A_WGM1': '$03',
+ 'TCCR1B': '&129',
+ 'TCCR1B_ICNC1': '$80',
+ 'TCCR1B_ICES1': '$40',
+ 'TCCR1B_WGM1': '$18',
+ 'TCCR1B_CS1': '$07',
+ 'TCCR1C': '&130',
+ 'TCCR1C_FOC1A': '$80',
+ 'TCCR1C_FOC1B': '$40',
+ 'TCNT1': '&132',
+ 'OCR1A': '&136',
+ 'OCR1B': '&138',
+ 'ICR1': '&134',
+ 'ADMUX': '&124',
+ 'ADMUX_REFS': '$C0',
+ 'ADMUX_ADLAR': '$20',
+ 'ADMUX_MUX': '$1F',
+ 'ADCSRA': '&122',
+ 'ADCSRA_ADEN': '$80',
+ 'ADCSRA_ADSC': '$40',
+ 'ADCSRA_ADATE': '$20',
+ 'ADCSRA_ADIF': '$10',
+ 'ADCSRA_ADIE': '$08',
+ 'ADCSRA_ADPS': '$07',
+ 'ADC': '&120',
+ 'ADCSRB': '&123',
+ 'ADCSRB_ADHSM': '$80',
+ 'ADCSRB_ISRCEN': '$40',
+ 'ADCSRB_AREFEN': '$20',
+ 'ADCSRB_ADTS': '$0F',
+ 'DIDR0': '&126',
+ 'DIDR0_ADC7D': '$80',
+ 'DIDR0_ADC6D': '$40',
+ 'DIDR0_ADC5D': '$20',
+ 'DIDR0_ADC4D': '$10',
+ 'DIDR0_ADC3D': '$08',
+ 'DIDR0_ADC2D': '$04',
+ 'DIDR0_ADC1D': '$02',
+ 'DIDR0_ADC0D': '$01',
+ 'DIDR1': '&127',
+ 'DIDR1_AMP2PD': '$40',
+ 'DIDR1_ACMP0D': '$20',
+ 'DIDR1_AMP0PD': '$10',
+ 'DIDR1_AMP0ND': '$08',
+ 'DIDR1_ADC10D': '$04',
+ 'DIDR1_ADC9D': '$02',
+ 'DIDR1_ADC8D': '$01',
+ 'AMP0CSR': '&117',
+ 'AMP0CSR_AMP0EN': '$80',
+ 'AMP0CSR_AMP0IS': '$40',
+ 'AMP0CSR_AMP0G': '$30',
+ 'AMP0CSR_AMPCMP0': '$08',
+ 'AMP0CSR_AMP0TS': '$07',
+ 'AMP1CSR': '&118',
+ 'AMP1CSR_AMP1EN': '$80',
+ 'AMP1CSR_AMP1IS': '$40',
+ 'AMP1CSR_AMP1G': '$30',
+ 'AMP1CSR_AMPCMP1': '$08',
+ 'AMP1CSR_AMP1TS': '$07',
+ 'AMP2CSR': '&119',
+ 'AMP2CSR_AMP2EN': '$80',
+ 'AMP2CSR_AMP2IS': '$40',
+ 'AMP2CSR_AMP2G': '$30',
+ 'AMP2CSR_AMPCMP2': '$08',
+ 'AMP2CSR_AMP2TS': '$07',
+ 'LINCR': '&200',
+ 'LINCR_LSWRES': '$80',
+ 'LINCR_LIN13': '$40',
+ 'LINCR_LCONF': '$30',
+ 'LINCR_LENA': '$08',
+ 'LINCR_LCMD': '$07',
+ 'LINSIR': '&201',
+ 'LINSIR_LIDST': '$E0',
+ 'LINSIR_LBUSY': '$10',
+ 'LINSIR_LERR': '$08',
+ 'LINSIR_LIDOK': '$04',
+ 'LINSIR_LTXOK': '$02',
+ 'LINSIR_LRXOK': '$01',
+ 'LINENIR': '&202',
+ 'LINENIR_LENERR': '$08',
+ 'LINENIR_LENIDOK': '$04',
+ 'LINENIR_LENTXOK': '$02',
+ 'LINENIR_LENRXOK': '$01',
+ 'LINERR': '&203',
+ 'LINERR_LABORT': '$80',
+ 'LINERR_LTOERR': '$40',
+ 'LINERR_LOVERR': '$20',
+ 'LINERR_LFERR': '$10',
+ 'LINERR_LSERR': '$08',
+ 'LINERR_LPERR': '$04',
+ 'LINERR_LCERR': '$02',
+ 'LINERR_LBERR': '$01',
+ 'LINBTR': '&204',
+ 'LINBTR_LDISR': '$80',
+ 'LINBTR_LBT': '$3F',
+ 'LINBRRL': '&205',
+ 'LINBRRL_LDIV': '$FF',
+ 'LINBRRH': '&206',
+ 'LINBRRH_LDIV': '$0F',
+ 'LINDLR': '&207',
+ 'LINDLR_LTXDL': '$F0',
+ 'LINDLR_LRXDL': '$0F',
+ 'LINIDR': '&208',
+ 'LINIDR_LP': '$C0',
+ 'LINIDR_LID': '$3F',
+ 'LINSEL': '&209',
+ 'LINSEL_LAINC': '$08',
+ 'LINSEL_LINDX': '$07',
+ 'LINDAT': '&210',
+ 'LINDAT_LDATA': '$FF',
+ 'SPCR': '&76',
+ 'SPCR_SPIE': '$80',
+ 'SPCR_SPE': '$40',
+ 'SPCR_DORD': '$20',
+ 'SPCR_MSTR': '$10',
+ 'SPCR_CPOL': '$08',
+ 'SPCR_CPHA': '$04',
+ 'SPCR_SPR': '$03',
+ 'SPSR': '&77',
+ 'SPSR_SPIF': '$80',
+ 'SPSR_WCOL': '$40',
+ 'SPSR_SPI2X': '$01',
+ 'SPDR': '&78',
+ 'WDTCSR': '&96',
+ 'WDTCSR_WDIF': '$80',
+ 'WDTCSR_WDIE': '$40',
+ 'WDTCSR_WDP': '$27',
+ 'WDTCSR_WDCE': '$10',
+ 'WDTCSR_WDE': '$08',
+ 'EICRA': '&105',
+ 'EICRA_ISC3': '$C0',
+ 'EICRA_ISC2': '$30',
+ 'EICRA_ISC1': '$0C',
+ 'EICRA_ISC0': '$03',
+ 'EIMSK': '&61',
+ 'EIMSK_INT': '$0F',
+ 'EIFR': '&60',
+ 'EIFR_INTF': '$0F',
+ 'PCICR': '&104',
+ 'PCICR_PCIE': '$0F',
+ 'PCMSK3': '&109',
+ 'PCMSK3_PCINT': '$07',
+ 'PCMSK2': '&108',
+ 'PCMSK2_PCINT': '$FF',
+ 'PCMSK1': '&107',
+ 'PCMSK1_PCINT': '$FF',
+ 'PCMSK0': '&106',
+ 'PCMSK0_PCINT': '$FF',
+ 'PCIFR': '&59',
+ 'PCIFR_PCIF': '$0F',
+ 'EEAR': '&65',
+ 'EEDR': '&64',
+ 'EECR': '&63',
+ 'EECR_EEPM': '$30',
+ 'EECR_EERIE': '$08',
+ 'EECR_EEMWE': '$04',
+ 'EECR_EEWE': '$02',
+ 'EECR_EERE': '$01',
+ 'PIFR': '&188',
+ 'PIFR_PEV': '$0E',
+ 'PIFR_PEOP': '$01',
+ 'PIM': '&187',
+ 'PIM_PEVE': '$0E',
+ 'PIM_PEOPE': '$01',
+ 'PMIC2': '&186',
+ 'PMIC2_POVEN2': '$80',
+ 'PMIC2_PISEL2': '$40',
+ 'PMIC2_PELEV2': '$20',
+ 'PMIC2_PFLTE2': '$10',
+ 'PMIC2_PAOC2': '$08',
+ 'PMIC2_PRFM2': '$07',
+ 'PMIC1': '&185',
+ 'PMIC1_POVEN1': '$80',
+ 'PMIC1_PISEL1': '$40',
+ 'PMIC1_PELEV1': '$20',
+ 'PMIC1_PFLTE1': '$10',
+ 'PMIC1_PAOC1': '$08',
+ 'PMIC1_PRFM1': '$07',
+ 'PMIC0': '&184',
+ 'PMIC0_POVEN0': '$80',
+ 'PMIC0_PISEL0': '$40',
+ 'PMIC0_PELEV0': '$20',
+ 'PMIC0_PFLTE0': '$10',
+ 'PMIC0_PAOC0': '$08',
+ 'PMIC0_PRFM0': '$07',
+ 'PCTL': '&183',
+ 'PCTL_PPRE': '$C0',
+ 'PCTL_PCLKSEL': '$20',
+ 'PCTL_PCCYC': '$02',
+ 'PCTL_PRUN': '$01',
+ 'POC': '&182',
+ 'POC_POEN2B': '$20',
+ 'POC_POEN2A': '$10',
+ 'POC_POEN1B': '$08',
+ 'POC_POEN1A': '$04',
+ 'POC_POEN0B': '$02',
+ 'POC_POEN0A': '$01',
+ 'PCNF': '&181',
+ 'PCNF_PULOCK': '$20',
+ 'PCNF_PMODE': '$10',
+ 'PCNF_POPB': '$08',
+ 'PCNF_POPA': '$04',
+ 'PSYNC': '&180',
+ 'PSYNC_PSYNC2': '$30',
+ 'PSYNC_PSYNC1': '$0C',
+ 'PSYNC_PSYNC0': '$03',
+ 'POCR_RB': '&178',
+ 'POCR2SB': '&176',
+ 'POCR2RA': '&174',
+ 'POCR2SA': '&172',
+ 'POCR1SB': '&170',
+ 'POCR1RA': '&168',
+ 'POCR1SA': '&166',
+ 'POCR0SB': '&164',
+ 'POCR0RA': '&162',
+ 'POCR0SA': '&160',
+ 'ANACOMP0Addr': '2',
+ 'ANACOMP1Addr': '4',
+ 'ANACOMP2Addr': '6',
+ 'ANACOMP3Addr': '8',
+ 'PSC_FAULTAddr': '10',
+ 'PSC_ECAddr': '12',
+ 'INT0Addr': '14',
+ 'INT1Addr': '16',
+ 'INT2Addr': '18',
+ 'INT3Addr': '20',
+ 'TIMER1_CAPTAddr': '22',
+ 'TIMER1_COMPAAddr': '24',
+ 'TIMER1_COMPBAddr': '26',
+ 'TIMER1_OVFAddr': '28',
+ 'TIMER0_COMPAAddr': '30',
+ 'TIMER0_COMPBAddr': '32',
+ 'TIMER0_OVFAddr': '34',
+ 'CAN_INTAddr': '36',
+ 'CAN_TOVFAddr': '38',
+ 'LIN_TCAddr': '40',
+ 'LIN_ERRAddr': '42',
+ 'PCINT0Addr': '44',
+ 'PCINT1Addr': '46',
+ 'PCINT2Addr': '48',
+ 'PCINT3Addr': '50',
+ 'SPI__STCAddr': '52',
+ 'ADCAddr': '54',
+ 'WDTAddr': '56',
+ 'EE_READYAddr': '58',
+ 'SPM_READYAddr': '60'
+} \ No newline at end of file
diff --git a/amforth-6.5/avr8/devices/atmega64m1/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega64m1/words/no-jtag.asm
new file mode 100644
index 0000000..352a4bb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega64m1/words/no-jtag.asm
@@ -0,0 +1,14 @@
+; ( -- )
+; ( -- )
+; MCU
+; disable jtag at runtime
+VE_NOJTAG:
+ .dw $FF05
+ .db "-jtag",0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOJTAG
+XT_NOJTAG:
+ .dw PFA_NOJTAG
+PFA_NOJTAG:
+
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega64m1/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega64m1/words/no-wdt.asm
new file mode 100644
index 0000000..ff6ddd1
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega64m1/words/no-wdt.asm
@@ -0,0 +1,34 @@
+; ( -- )
+; MCU
+; disable watch dog timer at runtime
+VE_NOWDT:
+ .dw $ff04
+ .db "-wdt"
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOWDT
+XT_NOWDT:
+ .dw PFA_NOWDT
+PFA_NOWDT:
+
+ in temp1,SREG
+ push temp1
+ ; Turn always off global interrupt.
+ cli
+ ; Reset Watchdog Timer
+ wdr
+ ; Clear WDRF in MCUSR
+ in temp1, MCUSR
+ andi temp1, (0xff & (0<<WDRF))
+ out MCUSR, temp1
+ ; Write logical one to WDCE and WDE
+ ; Keep old prescaler setting to prevent unintentional time-out
+ in_ temp1, WDTCSR
+ ori temp1, (1<<WDCE) | (1<<WDE)
+ out_ WDTCSR, temp1
+ ; Turn off WDT
+ ldi temp1, (0<<WDE)
+ out_ WDTCSR, temp1
+ ; restore status register
+ pop temp1
+ out SREG,temp1
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega64m1/words/sleep.asm b/amforth-6.5/avr8/devices/atmega64m1/words/sleep.asm
new file mode 100644
index 0000000..256249c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega64m1/words/sleep.asm
@@ -0,0 +1,19 @@
+; ( mode -- )
+; MCU
+; put the controller into the specified sleep mode
+VE_SLEEP:
+ .dw $ff05
+ .db "sleep", 0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_SLEEP
+XT_SLEEP:
+ .dw PFA_SLEEP
+PFA_SLEEP:
+ andi tosl, 7 ; leave only legal mode bits
+ lsl tosl ; move to correct location (bits 3-1)
+ ori tosl, 1 ; set the SE bit
+ out_ SMCR, tosl ; set the sleep config
+ sleep ; nighty-night
+ out_ SMCR, zerol ; 0 protects against accidental sleeps
+ loadtos ; pop argument from stack
+ jmp_ DO_NEXT