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authorDimitri Sokolyuk <demon@dim13.org>2019-10-30 20:04:56 +0100
committerDimitri Sokolyuk <demon@dim13.org>2019-10-30 20:04:56 +0100
commita76977af62010a392c16010c367185e61e856ffe (patch)
tree56cf4177d5bc0e3ead781d1c60818c13b1df0f3c /j1demo/synth
parentc0165d167d7cb40d80028bcf7a4a6b160b5a7e83 (diff)
mv to docs
Diffstat (limited to 'j1demo/synth')
-rw-r--r--j1demo/synth/Makefile9
-rw-r--r--j1demo/synth/j1.bmm12
-rw-r--r--j1demo/synth/j1.ucf327
-rw-r--r--j1demo/synth/xilinx.mk174
-rw-r--r--j1demo/synth/xilinx.opt42
5 files changed, 0 insertions, 564 deletions
diff --git a/j1demo/synth/Makefile b/j1demo/synth/Makefile
deleted file mode 100644
index 4cec0ac..0000000
--- a/j1demo/synth/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-project = j1
-vendor = xilinx
-family = spartan3s
-part = xc3s1000-4ft256
-top_module = top
-
-vfiles = ../verilog/top.v ../verilog/j1.v ../verilog/ck_div.v ../verilog/uart.v
-
-include xilinx.mk
diff --git a/j1demo/synth/j1.bmm b/j1demo/synth/j1.bmm
deleted file mode 100644
index 61a7d83..0000000
--- a/j1demo/synth/j1.bmm
+++ /dev/null
@@ -1,12 +0,0 @@
-ADDRESS_SPACE jram RAMB16 [0x00020000:0x00023fff]
- BUS_BLOCK
- j1/ram[7].ram [15:14];
- j1/ram[6].ram [13:12];
- j1/ram[5].ram [11:10];
- j1/ram[4].ram [9:8];
- j1/ram[3].ram [7:6];
- j1/ram[2].ram [5:4];
- j1/ram[1].ram [3:2];
- j1/ram[0].ram [1:0];
- END_BUS_BLOCK;
-END_ADDRESS_SPACE;
diff --git a/j1demo/synth/j1.ucf b/j1demo/synth/j1.ucf
deleted file mode 100644
index f6bbd70..0000000
--- a/j1demo/synth/j1.ucf
+++ /dev/null
@@ -1,327 +0,0 @@
-#####################################################
-#
-# XSA-3S1000 Board FPGA pin assignment constraints
-#
-#####################################################
-#
-# Clocks
-#
-net CLKA loc=T9 | IOSTANDARD = LVCMOS33 ; # 100MHz
-#net CLKB loc=P8 | IOSTANDARD = LVCMOS33 ; # 50MHz
-#net CLKC loc=R9 | IOSTANDARD = LVCMOS33 ; # ??Mhz
-#
-# Push button switches
-#
-#NET SW1_3_N loc=K2 | IOSTANDARD = LVCMOS33 ; # Flash Block select
-#NET SW1_4_N loc=J4 | IOSTANDARD = LVCMOS33 ; # Flash Block
-#NET SW2_N loc=E11 | IOSTANDARD = LVCMOS33 ; # active-low pushbutton
-#NET SW3_N loc=A13 | IOSTANDARD = LVCMOS33 ; # active-low pushbutton
-#
-# PS/2 Keyboard
-#
-net PS2_CLK loc=B16 | IOSTANDARD = LVCMOS33 ;
-net PS2_DAT loc=E13 | IOSTANDARD = LVCMOS33 ;
-#
-# VGA Outputs
-#
-NET VGA_BLUE<0> LOC=C9 | IOSTANDARD = LVCMOS33 ;
-NET VGA_BLUE<1> LOC=E7 | IOSTANDARD = LVCMOS33 ;
-NET VGA_BLUE<2> LOC=D5 | IOSTANDARD = LVCMOS33 ;
-NET VGA_GREEN<0> LOC=A8 | IOSTANDARD = LVCMOS33 ;
-NET VGA_GREEN<1> LOC=A5 | IOSTANDARD = LVCMOS33 ;
-NET VGA_GREEN<2> LOC=C3 | IOSTANDARD = LVCMOS33 ;
-NET VGA_RED<0> LOC=C8 | IOSTANDARD = LVCMOS33 ;
-NET VGA_RED<1> LOC=D6 | IOSTANDARD = LVCMOS33 ;
-NET VGA_RED<2> LOC=B1 | IOSTANDARD = LVCMOS33 ;
-NET VGA_HSYNC_N LOC=B7 | IOSTANDARD = LVCMOS33 ;
-NET VGA_VSYNC_N LOC=D8 | IOSTANDARD = LVCMOS33 ;
-#
-# Manually assign locations for the DCMs along the bottom of the FPGA
-# because PAR sometimes places them in opposing corners and that ruins the clocks.
-#
-#INST "u1/gen_dlls.dllint" LOC="DCM_X0Y0";
-#INST "u1/gen_dlls.dllext" LOC="DCM_X1Y0";
-
-# Manually assign locations for the DCMs along the bottom of the FPGA
-# because PAR sometimes places them in opposing corners and that ruins the clocks.
-#INST "u2_dllint" LOC="DCM_X0Y0";
-#INST "u2_dllext" LOC="DCM_X1Y0";
-#
-# SDRAM memory pin assignments
-#
-#net SDRAM_clkfb loc=N8 | IOSTANDARD = LVCMOS33 ; # feedback SDRAM clock after PCB delays
-#net SDRAM_clkout loc=E10 | IOSTANDARD = LVCMOS33 ; # clock to SDRAM
-#net SDRAM_CKE loc=D7 | IOSTANDARD = LVCMOS33 ; # SDRAM clock enable
-#net SDRAM_CS_N loc=B8 | IOSTANDARD = LVCMOS33 ; # SDRAM chip-select
-#net SDRAM_RAS_N loc=A9 | IOSTANDARD = LVCMOS33 ;
-#net SDRAM_CAS_N loc=A10 | IOSTANDARD = LVCMOS33 ;
-#net SDRAM_WE_N loc=B10 | IOSTANDARD = LVCMOS33 ;
-#net SDRAM_DQMH loc=D9 | IOSTANDARD = LVCMOS33 ;
-#net SDRAM_DQML loc=C10 | IOSTANDARD = LVCMOS33 ;
-#net SDRAM_A<0> loc=B5 | IOSTANDARD = LVCMOS33 ;
-#net SDRAM_A<1> loc=A4 | IOSTANDARD = LVCMOS33 ;
-#net SDRAM_A<2> loc=B4 | IOSTANDARD = LVCMOS33 ;
-#net SDRAM_A<3> loc=E6 | IOSTANDARD = LVCMOS33 ;
-#net SDRAM_A<4> loc=E3 | IOSTANDARD = LVCMOS33 ;
-#net SDRAM_A<5> loc=C1 | IOSTANDARD = LVCMOS33 ;
-#net SDRAM_A<6> loc=E4 | IOSTANDARD = LVCMOS33 ;
-#net SDRAM_A<7> loc=D3 | IOSTANDARD = LVCMOS33 ;
-#net SDRAM_A<8> loc=C2 | IOSTANDARD = LVCMOS33 ;
-#net SDRAM_A<9> loc=A3 | IOSTANDARD = LVCMOS33 ;
-#net SDRAM_A<10> loc=B6 | IOSTANDARD = LVCMOS33 ;
-#net SDRAM_A<11> loc=C5 | IOSTANDARD = LVCMOS33 ;
-#net SDRAM_A<12> loc=C6 | IOSTANDARD = LVCMOS33 ;
-#net SDRAM_D<0> loc=C15 | IOSTANDARD = LVCMOS33 ;
-#net SDRAM_D<1> loc=D12 | IOSTANDARD = LVCMOS33 ;
-#net SDRAM_D<2> loc=A14 | IOSTANDARD = LVCMOS33 ;
-#net SDRAM_D<3> loc=B13 | IOSTANDARD = LVCMOS33 ;
-#net SDRAM_D<4> loc=D11 | IOSTANDARD = LVCMOS33 ;
-#net SDRAM_D<5> loc=A12 | IOSTANDARD = LVCMOS33 ;
-#net SDRAM_D<6> loc=C11 | IOSTANDARD = LVCMOS33 ;
-#net SDRAM_D<7> loc=D10 | IOSTANDARD = LVCMOS33 ;
-#net SDRAM_D<8> loc=B11 | IOSTANDARD = LVCMOS33 ;
-#net SDRAM_D<9> loc=B12 | IOSTANDARD = LVCMOS33 ;
-#net SDRAM_D<10> loc=C12 | IOSTANDARD = LVCMOS33 ;
-#net SDRAM_D<11> loc=B14 | IOSTANDARD = LVCMOS33 ;
-#net SDRAM_D<12> loc=D14 | IOSTANDARD = LVCMOS33 ;
-#net SDRAM_D<13> loc=C16 | IOSTANDARD = LVCMOS33 ;
-#net SDRAM_D<14> loc=F12 | IOSTANDARD = LVCMOS33 ;
-#net SDRAM_D<15> loc=F13 | IOSTANDARD = LVCMOS33 ;
-#net SDRAM_BA<0> loc=A7 | IOSTANDARD = LVCMOS33 ;
-#net SDRAM_BA<1> loc=C7 | IOSTANDARD = LVCMOS33 ;
-#
-# Flash memory interface
-
-net FLASH_A<0> LOC=N5 | IOSTANDARD = LVCMOS33 ;
-net FLASH_A<1> LOC=K14 | IOSTANDARD = LVCMOS33 ;
-net FLASH_A<2> LOC=K13 | IOSTANDARD = LVCMOS33 ;
-net FLASH_A<3> LOC=K12 | IOSTANDARD = LVCMOS33 ;
-net FLASH_A<4> LOC=L14 | IOSTANDARD = LVCMOS33 ;
-net FLASH_A<5> LOC=M16 | IOSTANDARD = LVCMOS33 ;
-net FLASH_A<6> LOC=L13 | IOSTANDARD = LVCMOS33 ;
-net FLASH_A<7> LOC=N16 | IOSTANDARD = LVCMOS33 ;
-net FLASH_A<8> LOC=N14 | IOSTANDARD = LVCMOS33 ;
-net FLASH_A<9> LOC=P15 | IOSTANDARD = LVCMOS33 ;
-net FLASH_A<10> LOC=R16 | IOSTANDARD = LVCMOS33 ;
-net FLASH_A<11> LOC=P14 | IOSTANDARD = LVCMOS33 ;
-net FLASH_A<12> LOC=P13 | IOSTANDARD = LVCMOS33 ;
-net FLASH_A<13> LOC=N12 | IOSTANDARD = LVCMOS33 ;
-net FLASH_A<14> LOC=T14 | IOSTANDARD = LVCMOS33 ;
-net FLASH_A<15> LOC=R13 | IOSTANDARD = LVCMOS33 ;
-net FLASH_A<16> LOC=N10 | IOSTANDARD = LVCMOS33 ;
-net FLASH_A<17> LOC=M14 | IOSTANDARD = LVCMOS33 ;
-net FLASH_A<18> LOC=K3 | IOSTANDARD = LVCMOS33 ;
-net FLASH_A<19> LOC=K4 | IOSTANDARD = LVCMOS33 ;
-
-net FLASH_D<0> LOC=M11 | IOSTANDARD = LVCMOS33 ;
-net FLASH_D<1> LOC=N11 | IOSTANDARD = LVCMOS33 ;
-net FLASH_D<2> LOC=P10 | IOSTANDARD = LVCMOS33 ;
-net FLASH_D<3> LOC=R10 | IOSTANDARD = LVCMOS33 ;
-net FLASH_D<4> LOC=T7 | IOSTANDARD = LVCMOS33 ;
-net FLASH_D<5> LOC=R7 | IOSTANDARD = LVCMOS33 ;
-net FLASH_D<6> LOC=N6 | IOSTANDARD = LVCMOS33 ;
-net FLASH_D<7> LOC=M6 | IOSTANDARD = LVCMOS33 ;
-net FLASH_D<8> LOC=T4 | IOSTANDARD = LVCMOS33 ;
-net FLASH_D<9> LOC=R5 | IOSTANDARD = LVCMOS33 ;
-net FLASH_D<10> LOC=T5 | IOSTANDARD = LVCMOS33 ;
-net FLASH_D<11> LOC=P6 | IOSTANDARD = LVCMOS33 ;
-net FLASH_D<12> LOC=M7 | IOSTANDARD = LVCMOS33 ;
-net FLASH_D<13> LOC=R6 | IOSTANDARD = LVCMOS33 ;
-net FLASH_D<14> LOC=N7 | IOSTANDARD = LVCMOS33 ;
-net FLASH_D<15> LOC=P7 | IOSTANDARD = LVCMOS33 ;
-net FLASH_CE_N LOC=R4 | IOSTANDARD = LVCMOS33 ;
-net FLASH_OE_N LOC=P5 | IOSTANDARD = LVCMOS33 ;
-net FLASH_WE_N LOC=M13 | IOSTANDARD = LVCMOS33 ;
-net FLASH_BYTE_N LOC=T8 | IOSTANDARD = LVCMOS33 ;
-net FLASH_RDY LOC=L12 | IOSTANDARD = LVCMOS33 ;
-net FLASH_RST_N LOC=P16 | IOSTANDARD = LVCMOS33 ;
-
-# FPGA Programming interface
-#
-#net FPGA_D<0> LOC=M11 | IOSTANDARD = LVCMOS33 ; # shared with FLASH_D0, S1, LED_C
-#net FPGA_D<1> LOC=N11 | IOSTANDARD = LVCMOS33 ; # shared with FLASH_D1, S7, LED_DP
-#net FPGA_D<2> LOC=P10 | IOSTANDARD = LVCMOS33 ; # shared with FLASH_D2, S4, LED_B
-#net FPGA_D<3> LOC=R10 | IOSTANDARD = LVCMOS33 ; # shared with FLASH_D3, S6, LED_A
-#net FPGA_D<4> LOC=T7 | IOSTANDARD = LVCMOS33 ; # shared with FLASH_D4, S5, LED_F
-#net FPGA_D<5> LOC=R7 | IOSTANDARD = LVCMOS33 ; # shared with FLASH_D5, S3, LED_G
-#net FPGA_D<6> LOC=N6 | IOSTANDARD = LVCMOS33 ; # shared with FLASH_D6, S2, LED_E
-#net FPGA_D<7> LOC=M6 | IOSTANDARD = LVCMOS33 ; # shared with FLASH_D7, S0, LED_D
-#net FPGA_CCLK LOC=T15 | IOSTANDARD = LVCMOS33 ;
-#net FPGA_DONE LOC=R14 | IOSTANDARD = LVCMOS33 ;
-#net FPGA_INIT_N LOC=N9 | IOSTANDARD = LVCMOS33 ;
-#net FPGA_PROG_N LOC=B3 | IOSTANDARD = LVCMOS33 ;
-#net FPGA_TCK LOC=C14 | IOSTANDARD = LVCMOS33 ;
-#net FPGA_TDI LOC=A2 | IOSTANDARD = LVCMOS33 ;
-#net FPGA_TDI_CSN LOC=R3 | IOSTANDARD = LVCMOS33 ;
-#net FPGA_TDO LOC=A15 | IOSTANDARD = LVCMOS33 ;
-#net FPGA_TDO_WRN LOC=T3 | IOSTANDARD = LVCMOS33 ;
-#net FPGA_TMS LOC=C13 | IOSTANDARD = LVCMOS33 ;
-#net FPGA_TMS_BSY LOC=P9 | IOSTANDARD = LVCMOS33 ;
-#
-# Status LED
-#
-#net S<0> loc=M6 | IOSTANDARD = LVCMOS33 ; # FPGA_D7, LED_D
-#net S<1> loc=M11 | IOSTANDARD = LVCMOS33 ; # FPGA_D0, LED_C
-#net S<2> loc=N6 | IOSTANDARD = LVCMOS33 ; # FPGA_D6, LED_E
-#net S<3> loc=R7 | IOSTANDARD = LVCMOS33 ; # FPGA_D5, LED_G
-#net S<4> loc=P10 | IOSTANDARD = LVCMOS33 ; # FPGA_D2, LED_B
-#net S<5> loc=T7 | IOSTANDARD = LVCMOS33 ; # FPGA_D4, LED_F
-#net S<6> loc=R10 | IOSTANDARD = LVCMOS33 ; # FPGA_D3, LED_A
-#net S<7> loc=N11 | IOSTANDARD = LVCMOS33 ; # FPGA_D1, LED_DP
-#
-# Parallel Port
-#
-#net PPORT_load loc=N14 | IOSTANDARD = LVCMOS33 ;
-#net PPORT_clk loc=P15 | IOSTANDARD = LVCMOS33 ;
-#net PPORT_din<0> loc=R16 | IOSTANDARD = LVCMOS33 ;
-#net PPORT_din<1> loc=P14 | IOSTANDARD = LVCMOS33 ;
-#net PPORT_din<2> loc=P13 | IOSTANDARD = LVCMOS33 ;
-#net PPORT_din<3> loc=N12 | IOSTANDARD = LVCMOS33 ;
-#
-#net PPORT_dout<0> loc=N5 | IOSTANDARD = LVCMOS33 ;
-#net PPORT_dout<1> loc=K14 | IOSTANDARD = LVCMOS33 ;
-#net PPORT_dout<2> loc=K13 | IOSTANDARD = LVCMOS33 ;
-#net PPORT_dout<3> loc=T10 | IOSTANDARD = LVCMOS33 ;
-#
-#net PPORT_d<0> loc=N14 | IOSTANDARD = LVCMOS33 ; # FLASH_A<8> / PPORT_LOAD
-#net PPORT_d<1> loc=P15 | IOSTANDARD = LVCMOS33 ; # FLASH_A<9> / PPORT_CLK
-#net PPORT_d<2> loc=R16 | IOSTANDARD = LVCMOS33 ; # FLASH_A<10> / PPORT_DIN<0>
-#net PPORT_d<3> loc=P14 | IOSTANDARD = LVCMOS33 ; # FLASH_A<11> / PPORT_DIN<1>
-#net PPORT_d<4> loc=P13 | IOSTANDARD = LVCMOS33 ; # FLASH_A<12> / PPORT_DIN<2>
-#net PPORT_d<5> loc=N12 | IOSTANDARD = LVCMOS33 ; # FLASH_A<13> / PPORT_DIN<3>
-##net PPORT_d<6> loc=T14 | IOSTANDARD = LVCMOS33 ; # FLASH_A<14>
-##net PPORT_d<7> loc=R13 | IOSTANDARD = LVCMOS33 ; # FLASH_A<15>
-#
-#net PPORT_s<3> loc=N5 | IOSTANDARD = LVCMOS33 ; # FLASH_A<0> / PPORT_DOUT<0>
-#net PPORT_s<4> loc=K14 | IOSTANDARD = LVCMOS33 ; # FLASH_A<1> / PPORT_DOUT<1>
-#net PPORT_s<5> loc=K13 | IOSTANDARD = LVCMOS33 ; # FLASH_A<2> / PPORT_DOUT<2>
-#net PPORT_s<6> loc=T10 | IOSTANDARD = LVCMOS33 ; # / PPORT_DOUT<3>
-#
-########################################################
-#
-# XST3.0 pins
-#
-########################################################
-#
-# BAR LED
-#
-#net BAR<1> loc=L5 | IOSTANDARD = LVCMOS33 ; # bar led 1, PB_A0
-#net BAR<2> loc=N2 | IOSTANDARD = LVCMOS33 ; # bar led 2, PB_A1
-#net BAR<3> loc=M3 | IOSTANDARD = LVCMOS33 ; # bar led 3, PB_A2
-#net BAR<4> loc=N1 | IOSTANDARD = LVCMOS33 ; # bar led 4, PB_A3
-#net BAR<5> loc=T13 | IOSTANDARD = LVCMOS33 ; # bar led 5, PB_A4
-#net BAR<6> loc=L15 | IOSTANDARD = LVCMOS33 ; # bar led 6, ETHER_IRQ
-#net BAR<7> loc=J13 | IOSTANDARD = LVCMOS33 ; # bar led 7, USB_IRQ_N
-#net BAR<8> loc=H15 | IOSTANDARD = LVCMOS33 ; # bar led 8, IDE_IRQ
-#net BAR<9> loc=J16 | IOSTANDARD = LVCMOS33 ; # bar led 9, SLOT1_IRQ
-#net BAR<10> loc=J14 | IOSTANDARD = LVCMOS33 ; # bar led 10, SLOT2_IRQ
-#
-# Push Buttons
-#
-#net PB1_N loc=H4 | IOSTANDARD = LVCMOS33 ; # Shared with PB_D15
-#net PB2_N loc=L5 | IOSTANDARD = LVCMOS33 ; # Shared with BAR1, PB_A0
-#net PB3_N loc=N2 | IOSTANDARD = LVCMOS33 ; # Shared with BAR2, PB_A1
-#net PB4_N loc=M3 | IOSTANDARD = LVCMOS33 ; # Shared with BAR3, PB_A2
-#
-# RS232 PORT
-#
-net RS232_TXD loc=J2 | IOSTANDARD = LVCMOS33 ; # RS232 TD pin 3
-#net RS232_RXD loc=G5 | IOSTANDARD = LVCMOS33 ; # RS232 RD pin 2
-#net RS232_CTS loc=D1 | IOSTANDARD = LVCMOS33 ; # RS232 CTS
-#net RS232_RTS loc=F4 | IOSTANDARD = LVCMOS33 ; # RS232 RTS
-#
-# 16 Bit Peripheral Bus
-#
-# 5-bit Peripheral address bus
-net PB_A<0> loc=L5 | IOSTANDARD = LVCMOS33 ; # Shared with BAR1, PB2
-net PB_A<1> loc=N2 | IOSTANDARD = LVCMOS33 ; # Shared with BAR2, PB3
-net PB_A<2> loc=M3 | IOSTANDARD = LVCMOS33 ; # Shared with BAR3, PB4
-net PB_A<3> loc=N1 | IOSTANDARD = LVCMOS33 ; # Shared with BAR4
-net PB_A<4> loc=T13 | IOSTANDARD = LVCMOS33 ; # Shared with BAR5
-# 16-bit peripheral data bus
-net PB_D<0> loc=P12 | IOSTANDARD = LVCMOS33 ; # Shared with DIPSW1
-net PB_D<1> loc=J1 | IOSTANDARD = LVCMOS33 ; # Shared with DIPSW2
-net PB_D<2> loc=H1 | IOSTANDARD = LVCMOS33 ; # Shared with DIPSW3
-net PB_D<3> loc=H3 | IOSTANDARD = LVCMOS33 ; # Shared with DIPSW4
-net PB_D<4> loc=G2 | IOSTANDARD = LVCMOS33 ; # Shared with DIPSW5
-net PB_D<5> loc=K15 | IOSTANDARD = LVCMOS33 ; # Shared with DIPSW6
-net PB_D<6> loc=K16 | IOSTANDARD = LVCMOS33 ; # Shared with DIPSW7
-net PB_D<7> loc=F15 | IOSTANDARD = LVCMOS33 ; # Shared with DIPSW8
-net PB_D<8> loc=E2 | IOSTANDARD = LVCMOS33 ; # Shared with LED2_A
-net PB_D<9> loc=E1 | IOSTANDARD = LVCMOS33 ; # Shared with LED2_B
-net PB_D<10> loc=F3 | IOSTANDARD = LVCMOS33 ; # Shared with LED2_C
-net PB_D<11> loc=F2 | IOSTANDARD = LVCMOS33 ; # Shared with LED2_D
-net PB_D<12> loc=G4 | IOSTANDARD = LVCMOS33 ; # Shared with LED2_E
-net PB_D<13> loc=G3 | IOSTANDARD = LVCMOS33 ; # Shared with LED2_F
-net PB_D<14> loc=G1 | IOSTANDARD = LVCMOS33 ; # Shared with LED2_G
-net PB_D<15> loc=H4 | IOSTANDARD = LVCMOS33 ; # Shared with LED2_DP, PB1
-net PB_RD_N loc=P2 | IOSTANDARD = LVCMOS33 ; # disk I/O read control
-net PB_WR_N loc=R1 | IOSTANDARD = LVCMOS33 ; # disk I/O write control
-net RESET_TRIGGER loc=D15 | IOSTANDARD = LVCMOS33 ; # Reset RESET_TRIGGER#
-#
-# IDE Interface
-#
-#net IDE_CS0_N loc=G15 | IOSTANDARD = LVCMOS33 ; # disk register-bank select
-#net IDE_CS1_N loc=G14 | IOSTANDARD = LVCMOS33 ; # disk register-bank select
-#net IDE_DMACK_N loc=K1 | IOSTANDARD = LVCMOS33 ; # (out) IDE DMA acknowledge
-#net IDE_DMARQ loc=L4 | IOSTANDARD = LVCMOS33 ; # (in) IDE DMA request
-#net IDE_IORDY loc=L2 | IOSTANDARD = LVCMOS33 ; # (in) IDE IO ready
-#net IDE_IRQ loc=H15 | IOSTANDARD = LVCMOS33 ; # (in) IDE interrupt # shared with BAR8
-#
-# Ethernet Controller
-# Disable if not used
-#
-net ether_cs_n loc=G13 | IOSTANDARD = LVCMOS33 ; # (out)Ethernet chip-enable
-net ether_aen loc=E14 | IOSTANDARD = LVCMOS33 ; # (out) Ethernet address enable not
-net ether_bhe_n loc=J3 | IOSTANDARD = LVCMOS33 ; # (out) Ethernet bus high enable
-net ether_clk loc=R9 | IOSTANDARD = LVCMOS33 ; # (in) Ethernet clock
-net ether_irq loc=L15 | IOSTANDARD = LVCMOS33 ; # (in) Ethernet irq - Shared with BAR6
-net ether_rdy loc=M2 | IOSTANDARD = LVCMOS33 ; # (in) Ethernet ready
-#
-# Expansion slots
-#
-#net slot1_cs_n loc=E15 | IOSTANDARD = LVCMOS33 ; # (out)
-#net slot1_irq loc=J16 | IOSTANDARD = LVCMOS33 ; # (in) Shared with BAR9
-#net slot2_cs_n loc=D16 | IOSTANDARD = LVCMOS33 ; # (out)
-#net slot2_irq loc=J14 | IOSTANDARD = LVCMOS33 ; # (in) Shared with BAR10
-#
-# Audio codec
-#
-#net audio_lrck loc=R12 | IOSTANDARD = LVCMOS33 ; # (out)
-#net audio_mclk loc=P11 | IOSTANDARD = LVCMOS33 ; # (out)
-#net audio_sclk loc=T12 | IOSTANDARD = LVCMOS33 ; # (out)
-#net audio_sdti loc=M10 | IOSTANDARD = LVCMOS33 ; # (out)
-#net audio_sdto loc=K5 | IOSTANDARD = LVCMOS33 ; # (in)
-#
-# i2c
-#
-#net i2c_scl loc=F5 | IOSTANDARD = LVCMOS33 ; #(out)
-#net i2c_sda loc=D2 | IOSTANDARD = LVCMOS33 ; # (in/out)
-#
-# USB
-#
-#NET USB_CLK LOC=M1 | IOSTANDARD = LVCMOS33 ; # (IN)
-#NET USB_IRQ_N LOC=J13 | IOSTANDARD = LVCMOS33 ; # (IN) Shared with BAR7
-#NET USB_SUSPEND LOC=l3 | IOSTANDARD = LVCMOS33 ; # (IN)
-#
-# VIDEO DIGITIZER
-#
-#NET VIDIN_AVID LOC= | IOSTANDARD = LVCMOS33 ; # (IN)
-#NET VIDIN_CLK LOC=H16 | IOSTANDARD = LVCMOS33 ; # (IN)
-#NET VIDIN_FID LOC= | IOSTANDARD = LVCMOS33 ; # (IN)
-#NET VIDIN_HSYNC LOC= | IOSTANDARD = LVCMOS33 ; # (IN)
-#NET VIDIN_IRQ LOC= | IOSTANDARD = LVCMOS33 ; # (IN)
-#NET VIDIN_VSYNC LOC= | IOSTANDARD = LVCMOS33 ; # (IN)
-#NET VIDIN_Y<0> LOC=H14 | IOSTANDARD = LVCMOS33 ; # (IN) Shared with LED1_A
-#NET VIDIN_Y<1> LOC=M4 | IOSTANDARD = LVCMOS33 ; # (IN) Shared with LED1_B
-#NET VIDIN_Y<2> LOC=P1 | IOSTANDARD = LVCMOS33 ; # (IN) Shared with LED1_C
-#NET VIDIN_Y<3> LOC=N3 | IOSTANDARD = LVCMOS33 ; # (IN) Shared with LED1_D
-#NET VIDIN_Y<4> LOC=M15 | IOSTANDARD = LVCMOS33 ; # (IN) Shared with LED1_E
-#NET VIDIN_Y<5> LOC=H13 | IOSTANDARD = LVCMOS33 ; # (IN) Shared with LED1_F
-#NET VIDIN_Y<6> LOC=G16 | IOSTANDARD = LVCMOS33 ; # (IN) Shared with LED1_G
-#NET VIDIN_Y<7> LOC=N15 | IOSTANDARD = LVCMOS33 ; # (IN) Shared with LED1_DP
-#
-# Timing Constraints
-#
-NET "CLKA" TNM_NET="CLKA";
-TIMESPEC "TS_clk"=PERIOD "CLKA" 10 ns HIGH 50 %;
diff --git a/j1demo/synth/xilinx.mk b/j1demo/synth/xilinx.mk
deleted file mode 100644
index c692fe7..0000000
--- a/j1demo/synth/xilinx.mk
+++ /dev/null
@@ -1,174 +0,0 @@
-# The top level module should define the variables below then include
-# this file. The files listed should be in the same directory as the
-# Makefile.
-#
-# variable description
-# ---------- -------------
-# project project name (top level module should match this name)
-# top_module top level module of the project
-# libdir path to library directory
-# libs library modules used
-# vfiles all local .v files
-# xilinx_cores all local .xco files
-# vendor vendor of FPGA (xilinx, altera, etc.)
-# family FPGA device family (spartan3e)
-# part FPGA part name (xc4vfx12-10-sf363)
-# flashsize size of flash for mcs file (16384)
-# optfile (optional) xst extra opttions file to put in .scr
-# map_opts (optional) options to give to map
-# par_opts (optional) options to give to par
-# intstyle (optional) intstyle option to all tools
-#
-# files description
-# ---------- ------------
-# $(project).ucf ucf file
-#
-# Library modules should have a modules.mk in their root directory,
-# namely $(libdir)/<libname>/module.mk, that simply adds to the vfiles
-# and xilinx_cores variable.
-#
-# all the .xco files listed in xilinx_cores will be generated with core, with
-# the resulting .v and .ngc files placed back in the same directory as
-# the .xco file.
-#
-# TODO: .xco files are device dependant, should use a template based system
-
-coregen_work_dir ?= ./coregen-tmp
-map_opts ?= -timing -ol high -detail -pr b -register_duplication -w
-par_opts ?= -ol high
-isedir ?= /opt/Xilinx/11.1/ISE
-xil_env ?= . $(isedir)/settings32.sh
-flashsize ?= 8192
-
-libmks = $(patsubst %,$(libdir)/%/module.mk,$(libs))
-mkfiles = Makefile $(libmks) xilinx.mk
-include $(libmks)
-
-corengcs = $(foreach core,$(xilinx_cores),$(core:.xco=.ngc))
-local_corengcs = $(foreach ngc,$(corengcs),$(notdir $(ngc)))
-vfiles += $(foreach core,$(xilinx_cores),$(core:.xco=.v))
-junk += $(local_corengcs)
-
-.PHONY: default xilinx_cores clean twr etwr
-default: $(project).bit $(project).mcs
-xilinx_cores: $(corengcs)
-twr: $(project).twr
-etwr: $(project)_err.twr
-
-define cp_template
-$(2): $(1)
- cp $(1) $(2)
-endef
-$(foreach ngc,$(corengcs),$(eval $(call cp_template,$(ngc),$(notdir $(ngc)))))
-
-%.ngc %.v: %.xco
- @echo "=== rebuilding $@"
- if [ -d $(coregen_work_dir) ]; then \
- rm -rf $(coregen_work_dir)/*; \
- else \
- mkdir -p $(coregen_work_dir); \
- fi
- cd $(coregen_work_dir); \
- $(xil_env); \
- coregen -b $$OLDPWD/$<; \
- cd -
- xcodir=`dirname $<`; \
- basename=`basename $< .xco`; \
- if [ ! -r $(coregen_work_dir/$$basename.ngc) ]; then \
- echo "'$@' wasn't created."; \
- exit 1; \
- else \
- cp $(coregen_work_dir)/$$basename.v $(coregen_work_dir)/$$basename.ngc $$xcodir; \
- fi
-junk += $(coregen_work_dir)
-
-date = $(shell date +%F-%H-%M)
-
-# some common junk
-junk += *.xrpt
-
-programming_files: $(project).bit $(project).mcs
- mkdir -p $@/$(date)
- mkdir -p $@/latest
- for x in .bit .mcs .cfi _bd.bmm; do cp $(project)$$x $@/$(date)/$(project)$$x; cp $(project)$$x $@/latest/$(project)$$x; done
- $(xil_env); xst -help | head -1 | sed 's/^/#/' | cat - $(project).scr > $@/$(date)/$(project).scr
-
-$(project).mcs: $(project).bit
- $(xil_env); \
- promgen -w -s $(flashsize) -p mcs -o $@ -u 0 $^
-junk += $(project).mcs $(project).cfi $(project).prm
-
-$(project).bit: $(project)_par.ncd
- $(xil_env); \
- bitgen $(intstyle) -g DriveDone:yes -g StartupClk:Cclk -w $(project)_par.ncd $(project).bit
-junk += $(project).bgn $(project).bit $(project).drc $(project)_bd.bmm
-
-
-$(project)_par.ncd: $(project).ncd
- $(xil_env); \
- if par $(intstyle) $(par_opts) -w $(project).ncd $(project)_par.ncd; then \
- :; \
- else \
- $(MAKE) etwr; \
- fi
-junk += $(project)_par.ncd $(project)_par.par $(project)_par.pad
-junk += $(project)_par_pad.csv $(project)_par_pad.txt
-junk += $(project)_par.grf $(project)_par.ptwx
-junk += $(project)_par.unroutes $(project)_par.xpi
-
-$(project).ncd: $(project).ngd
- if [ -r $(project)_par.ncd ]; then \
- cp $(project)_par.ncd smartguide.ncd; \
- smartguide="-smartguide smartguide.ncd"; \
- else \
- smartguide=""; \
- fi; \
- $(xil_env); \
- map $(intstyle) $(map_opts) $$smartguide $<
-junk += $(project).ncd $(project).pcf $(project).ngm $(project).mrp $(project).map
-junk += smartguide.ncd $(project).psr
-junk += $(project)_summary.xml $(project)_usage.xml
-
-$(project).ngd: $(project).ngc $(project).ucf $(project).bmm
- $(xil_env); ngdbuild $(intstyle) $(project).ngc -bm $(project).bmm
-junk += $(project).ngd $(project).bld
-
-$(project).ngc: $(vfiles) $(local_corengcs) $(project).scr $(project).prj
- $(xil_env); xst $(intstyle) -ifn $(project).scr
-junk += xlnx_auto* $(top_module).lso $(project).srp
-junk += netlist.lst xst $(project).ngc
-
-$(project).prj: $(vfiles) $(mkfiles)
- for src in $(vfiles); do echo "verilog work $$src" >> $(project).tmpprj; done
- sort -u $(project).tmpprj > $(project).prj
- rm -f $(project).tmpprj
-junk += $(project).prj
-
-optfile += $(wildcard $(project).opt)
-top_module ?= $(project)
-$(project).scr: $(optfile) $(mkfiles) ./xilinx.opt
- echo "run" > $@
- echo "-p $(part)" >> $@
- echo "-top $(top_module)" >> $@
- echo "-ifn $(project).prj" >> $@
- echo "-ofn $(project).ngc" >> $@
- cat ./xilinx.opt $(optfile) >> $@
-junk += $(project).scr
-
-$(project).post_map.twr: $(project).ncd
- $(xil_env); trce -e 10 $< $(project).pcf -o $@
-junk += $(project).post_map.twr $(project).post_map.twx smartpreview.twr
-
-$(project).twr: $(project)_par.ncd
- $(xil_env); trce $< $(project).pcf -o $(project).twr
-junk += $(project).twr $(project).twx smartpreview.twr
-
-$(project)_err.twr: $(project)_par.ncd
- $(xil_env); trce -e 10 $< $(project).pcf -o $(project)_err.twr
-junk += $(project)_err.twr $(project)_err.twx
-
-.gitignore: $(mkfiles)
- echo programming_files $(junk) | sed 's, ,\n,g' > .gitignore
-
-clean::
- rm -rf $(junk)
diff --git a/j1demo/synth/xilinx.opt b/j1demo/synth/xilinx.opt
deleted file mode 100644
index 7fe9d8b..0000000
--- a/j1demo/synth/xilinx.opt
+++ /dev/null
@@ -1,42 +0,0 @@
--ifmt mixed
--ofmt NGC
--opt_mode speed
--opt_level 1
--iuc NO
--keep_hierarchy no
--netlist_hierarchy as_optimized
--rtlview no
--glob_opt AllClockNets
--read_cores yes
--write_timing_constraints NO
--cross_clock_analysis NO
--hierarchy_separator /
--bus_delimiter <>
--case maintain
--slice_utilization_ratio 100
--bram_utilization_ratio 100
-#-dsp_utilization_ratio 100
--safe_implementation No
--fsm_extract YES
--fsm_encoding Auto
--fsm_style lut
--ram_extract Yes
--ram_style Auto
--rom_extract Yes
--rom_style Auto
--shreg_extract YES
--auto_bram_packing NO
--resource_sharing YES
--async_to_sync NO
-#-use_dsp48 auto
--iobuf YES
--max_fanout 500
--register_duplication YES
--register_balancing No
--optimize_primitives NO
--use_clock_enable Auto
--use_sync_set Auto
--use_sync_reset Auto
--iob auto
--equivalent_register_removal YES
--slice_utilization_ratio_maxmargin 5