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authorDimitri Sokolyuk <demon@dim13.org>2019-10-30 20:04:56 +0100
committerDimitri Sokolyuk <demon@dim13.org>2019-10-30 20:04:56 +0100
commita76977af62010a392c16010c367185e61e856ffe (patch)
tree56cf4177d5bc0e3ead781d1c60818c13b1df0f3c /j1demo/verilog/ck_div.v
parentc0165d167d7cb40d80028bcf7a4a6b160b5a7e83 (diff)
mv to docs
Diffstat (limited to 'j1demo/verilog/ck_div.v')
-rw-r--r--j1demo/verilog/ck_div.v41
1 files changed, 0 insertions, 41 deletions
diff --git a/j1demo/verilog/ck_div.v b/j1demo/verilog/ck_div.v
deleted file mode 100644
index a753804..0000000
--- a/j1demo/verilog/ck_div.v
+++ /dev/null
@@ -1,41 +0,0 @@
-module ck_div(
-input ck_in,
-output ck_out,
-input sys_rst_i
-//output locked;
-);
-parameter DIV_BY = 1;
-parameter MULT_BY = 1;
-
-wire ck_fb;
-
-//DCM #(
-// .CLKDV_DIVIDE(DIV_BY),
-// .DFS_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for frequency synthesis
-// .DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE
-// .STARTUP_WAIT("TRUE") // Delay configuration DONE until DCM LOCK, TRUE/FALSE
-//) DCM_inst (
-// .CLK0(ck_fb),
-// .CLKDV(ck_out),
-// .CLKFB(ck_fb), // DCM clock feedback
-// .CLKIN(ck_in), // Clock input (from IBUFG, BUFG or DCM)
-// .RST(0)
-//);
-
-DCM #(
- .CLKFX_MULTIPLY(MULT_BY),
- .CLKFX_DIVIDE(DIV_BY),
- .DFS_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for frequency synthesis
- .DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE
- .STARTUP_WAIT("TRUE") // Delay configuration DONE until DCM LOCK, TRUE/FALSE
-) DCM_inst (
- .CLK0(ck_fb),
- .CLKFX(ck_out),
- .CLKFB(ck_fb), // DCM clock feedback
- .CLKIN(ck_in), // Clock input (from IBUFG, BUFG or DCM)
- .RST(0)
-);
-
-//BUFG BUFG_inst(.I(ck_int), .O(ck_out));
-
-endmodule