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authorDimitri Sokolyuk <demon@dim13.org>2019-10-30 20:04:56 +0100
committerDimitri Sokolyuk <demon@dim13.org>2019-10-30 20:04:56 +0100
commita76977af62010a392c16010c367185e61e856ffe (patch)
tree56cf4177d5bc0e3ead781d1c60818c13b1df0f3c /j1eforth/fpga
parentc0165d167d7cb40d80028bcf7a4a6b160b5a7e83 (diff)
mv to docs
Diffstat (limited to 'j1eforth/fpga')
-rw-r--r--j1eforth/fpga/papilio-pro-j1.xise422
-rw-r--r--j1eforth/fpga/papilio_pro_j1.bitbin340703 -> 0 bytes
-rw-r--r--j1eforth/fpga/src/Rxunit.vhd97
-rw-r--r--j1eforth/fpga/src/Txunit.vhd100
-rw-r--r--j1eforth/fpga/src/clock.vhd78
-rw-r--r--j1eforth/fpga/src/j1.v199
-rw-r--r--j1eforth/fpga/src/miniuart.vhd146
-rw-r--r--j1eforth/fpga/src/papilio-pro-j1.vhd117
-rw-r--r--j1eforth/fpga/src/papilio-pro.ucf143
-rw-r--r--j1eforth/fpga/src/utils.vhd132
-rw-r--r--j1eforth/fpga/test/miniuart2_tb.vhd128
-rw-r--r--j1eforth/fpga/test/papilio_pro_j1_tb.vhd96
12 files changed, 0 insertions, 1658 deletions
diff --git a/j1eforth/fpga/papilio-pro-j1.xise b/j1eforth/fpga/papilio-pro-j1.xise
deleted file mode 100644
index d41153c..0000000
--- a/j1eforth/fpga/papilio-pro-j1.xise
+++ /dev/null
@@ -1,422 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
-
- <header>
- <!-- ISE source project file created by Project Navigator. -->
- <!-- -->
- <!-- This file contains project source information including a list of -->
- <!-- project source files, project and process properties. This file, -->
- <!-- along with the project source files, is sufficient to open and -->
- <!-- implement in ISE Project Navigator. -->
- <!-- -->
- <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
- </header>
-
- <version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
-
- <files>
- <file xil_pn:name="src/papilio-pro.ucf" xil_pn:type="FILE_UCF">
- <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
- </file>
- <file xil_pn:name="src/miniuart.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
- </file>
- <file xil_pn:name="src/Rxunit.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
- </file>
- <file xil_pn:name="src/Txunit.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
- </file>
- <file xil_pn:name="src/utils.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
- </file>
- <file xil_pn:name="test/miniuart2_tb.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
- <association xil_pn:name="PostMapSimulation" xil_pn:seqID="231"/>
- <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="231"/>
- <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="231"/>
- </file>
- <file xil_pn:name="test/papilio_pro_j1_tb.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
- <association xil_pn:name="PostMapSimulation" xil_pn:seqID="15"/>
- <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="15"/>
- <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="15"/>
- </file>
- <file xil_pn:name="src/papilio-pro-j1.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
- </file>
- <file xil_pn:name="src/j1.v" xil_pn:type="FILE_VERILOG">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
- </file>
- <file xil_pn:name="src/clock.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
- </file>
- </files>
-
- <properties>
- <property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="AES Key (Hex String) spartan6" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
- <property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Auto Implementation Top" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
- <property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
- <property xil_pn:name="CLB Pack Factor Percentage" xil_pn:value="100" xil_pn:valueState="default"/>
- <property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
- <property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
- <property xil_pn:name="Change Device Speed To" xil_pn:value="-2" xil_pn:valueState="default"/>
- <property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-2" xil_pn:valueState="default"/>
- <property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
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- <property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
- <property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
- <property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
- <property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
- <property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
- <property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
- <property xil_pn:name="Configuration Rate" xil_pn:value="4" xil_pn:valueState="default"/>
- <property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
- <property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
- <property xil_pn:name="Decoder Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
- <property xil_pn:name="Device" xil_pn:value="xc6slx9" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-2" xil_pn:valueState="default"/>
- <property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
- <property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/>
- <property xil_pn:name="Enable Multi-Threading par spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
- <property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
- <property xil_pn:name="Enable Suspend/Wake Global Set/Reset spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Encrypt Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Encrypt Key Select spartan6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
- <property xil_pn:name="Equivalent Register Removal Map" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Essential Bits" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
- <property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/>
- <property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
- <property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
- <property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
- <property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
- <property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
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- <property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
- <property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
- <property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
- <property xil_pn:name="GTS Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
- <property xil_pn:name="GWE Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="5" xil_pn:valueState="default"/>
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- <property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
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- <property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
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- <property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
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- <property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
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- <property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
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- <property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
- <property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
- <property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
- <property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
- <property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
- <property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
- <property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
- <property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
- <property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
- <property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
- <property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Logical Shifter Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Mask Pins for Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="0x00" xil_pn:valueState="default"/>
- <property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
- <property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
- <property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
- <property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile spartan6" xil_pn:value="Enable" xil_pn:valueState="default"/>
- <property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/>
- <property xil_pn:name="MultiBoot: Starting Address for Golden Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
- <property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
- <property xil_pn:name="MultiBoot: Use New Mode for Next Configuration spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="MultiBoot: User-Defined Register for Failsafe Scheme spartan6" xil_pn:value="0x0000" xil_pn:valueState="default"/>
- <property xil_pn:name="Multiplier Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
- <property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
- <property xil_pn:name="Mux Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
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- <property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
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- <property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Output File Name" xil_pn:value="papilio_pro_forth" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
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- <property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
- <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
- <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="papilio_pro_forth_map.v" xil_pn:valueState="non-default"/>
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- <property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
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- <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
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- <property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Project Generator" xil_pn:value="ProjNav" xil_pn:valueState="default"/>
- <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
- <property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
- <property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
- <property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
- <property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
- <property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
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- <property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Register Ordering spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
- <property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
- <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
- <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
- <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="main" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
- <property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
- <property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
- <property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
- <property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
- <property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
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- <property xil_pn:name="Revision Select" xil_pn:value="00" xil_pn:valueState="default"/>
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- <property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
- <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
- <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/miniuart2_tb" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.miniuart2_tb" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
- <property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
- <property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
- <property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
- <property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
- <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
- <property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
- <property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
- <property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
- <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
- <property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
- <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.miniuart2_tb" xil_pn:valueState="default"/>
- <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
- <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
- <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
- <property xil_pn:name="Speed Grade" xil_pn:value="-2" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="1" xil_pn:valueState="default"/>
- <property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
- <property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="1" xil_pn:valueState="default"/>
- <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
- <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
- <property xil_pn:name="Target UCF File Name" xil_pn:value="src/papilio-one.ucf" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Timing Mode Map" xil_pn:value="Non Timing Driven" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
- <property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
- <property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
- <property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
- <property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
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- <property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
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- <property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
- <property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="User Browsed Strategy Files" xil_pn:value="/opt/Xilinx/14.7/ISE_DS/ISE/data/default.xds" xil_pn:valueState="non-default"/>
- <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
- <property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
- <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
- <property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
- <property xil_pn:name="Wait for DLL Lock (Output Events)" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
- <property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
- <property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
- <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
- <property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="XOR Collapsing" xil_pn:value="true" xil_pn:valueState="default"/>
- <!-- -->
- <!-- The following properties are for internal use only. These should not be modified.-->
- <!-- -->
- <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|miniuart2_tb|behavior" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_DesignName" xil_pn:value="forth" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
- <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
- <property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
- <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2012-03-04T11:05:19" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="2646B868CC6AC035FC694292A405C58C" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
- </properties>
-
- <bindings/>
-
- <libraries/>
-
- <autoManagedFiles>
- <!-- The following files are identified by `include statements in verilog -->
- <!-- source files and are automatically managed by Project Navigator. -->
- <!-- -->
- <!-- Do not hand-edit this section, as it will be overwritten when the -->
- <!-- project is analyzed based on files automatically identified as -->
- <!-- include files. -->
- </autoManagedFiles>
-
-</project>
diff --git a/j1eforth/fpga/papilio_pro_j1.bit b/j1eforth/fpga/papilio_pro_j1.bit
deleted file mode 100644
index 1c1372f..0000000
--- a/j1eforth/fpga/papilio_pro_j1.bit
+++ /dev/null
Binary files differ
diff --git a/j1eforth/fpga/src/Rxunit.vhd b/j1eforth/fpga/src/Rxunit.vhd
deleted file mode 100644
index c30a30e..0000000
--- a/j1eforth/fpga/src/Rxunit.vhd
+++ /dev/null
@@ -1,97 +0,0 @@
--------------------------------------------------------------------------------
--- Title : UART
--- Project : UART
--------------------------------------------------------------------------------
--- File : Rxunit.vhd
--- Author : Philippe CARTON
--- (philippe.carton2@libertysurf.fr)
--- Organization:
--- Created : 15/12/2001
--- Last update : 8/1/2003
--- Platform : Foundation 3.1i
--- Simulators : ModelSim 5.5b
--- Synthesizers: Xilinx Synthesis
--- Targets : Xilinx Spartan
--- Dependency : IEEE std_logic_1164
--------------------------------------------------------------------------------
--- Description: RxUnit is a serial to parallel unit Receiver.
--------------------------------------------------------------------------------
--- Copyright (c) notice
--- This core adheres to the GNU public license
---
--------------------------------------------------------------------------------
--- Revisions :
--- Revision Number :
--- Version :
--- Date :
--- Modifier : name <email>
--- Description :
---
-------------------------------------------------------------------------------
-library ieee;
- use ieee.std_logic_1164.all;
-
-entity RxUnit is
- port (
- Clk : in std_logic; -- system clock signal
- Reset : in std_logic; -- Reset input
- Enable : in std_logic; -- Enable input
- ReadA : in Std_logic; -- Async Read Received Byte
- RxD : in std_logic; -- RS-232 data input
- RxAv : out std_logic; -- Byte available
- DataO : out std_logic_vector(7 downto 0)); -- Byte received
-end RxUnit;
-
-architecture Behaviour of RxUnit is
- signal RReg : std_logic_vector(7 downto 0); -- receive register
- signal RRegL : std_logic; -- Byte received
-begin
- -- RxAv process
- RxAvProc : process(RRegL,Reset,ReadA)
- begin
- if ReadA = '1' or Reset = '1' then
- RxAv <= '0'; -- Negate RxAv when RReg read
- elsif Rising_Edge(RRegL) then
- RxAv <= '1'; -- Assert RxAv when RReg written
- end if;
- end process;
-
- -- Rx Process
- RxProc : process(Clk,Reset,Enable,RxD,RReg)
- variable BitPos : INTEGER range 0 to 10; -- Position of the bit in the frame
- variable SampleCnt : INTEGER range 0 to 3; -- Count from 0 to 3 in each bit
- begin
- if Reset = '1' then -- Reset
- RRegL <= '0';
- BitPos := 0;
- elsif Rising_Edge(Clk) then
- if Enable = '1' then
- case BitPos is
- when 0 => -- idle
- RRegL <= '0';
- if RxD = '0' then -- Start Bit
- SampleCnt := 0;
- BitPos := 1;
- end if;
- when 10 => -- Stop Bit
- BitPos := 0; -- next is idle
- RRegL <= '1'; -- Indicate byte received
- DataO <= RReg; -- Store received byte
- when others =>
- if (SampleCnt = 1 and BitPos >= 2) then -- Sample RxD on 1
- RReg(BitPos-2) <= RxD; -- Deserialisation
- end if;
- if SampleCnt = 3 then -- Increment BitPos on 3
- BitPos := BitPos + 1;
- end if;
- end case;
- if SampleCnt = 3 then
- SampleCnt := 0;
- else
- sampleCnt := SampleCnt + 1;
- end if;
-
- end if;
- end if;
- end process;
-end Behaviour;
diff --git a/j1eforth/fpga/src/Txunit.vhd b/j1eforth/fpga/src/Txunit.vhd
deleted file mode 100644
index bdf5b5d..0000000
--- a/j1eforth/fpga/src/Txunit.vhd
+++ /dev/null
@@ -1,100 +0,0 @@
--------------------------------------------------------------------------------
--- Title : UART
--- Project : UART
--------------------------------------------------------------------------------
--- File : Txunit.vhd
--- Author : Philippe CARTON
--- (philippe.carton2@libertysurf.fr)
--- Organization:
--- Created : 15/12/2001
--- Last update : 8/1/2003
--- Platform : Foundation 3.1i
--- Simulators : ModelSim 5.5b
--- Synthesizers: Xilinx Synthesis
--- Targets : Xilinx Spartan
--- Dependency : IEEE std_logic_1164
--------------------------------------------------------------------------------
--- Description: Txunit is a parallel to serial unit transmitter.
--------------------------------------------------------------------------------
--- Copyright (c) notice
--- This core adheres to the GNU public license
---
--------------------------------------------------------------------------------
--- Revisions :
--- Revision Number :
--- Version :
--- Date :
--- Modifier : name <email>
--- Description :
---
-------------------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-
-entity TxUnit is
- port (
- Clk : in std_logic; -- Clock signal
- Reset : in std_logic; -- Reset input
- Enable : in std_logic; -- Enable input
- LoadA : in std_logic; -- Asynchronous Load
- TxD : out std_logic; -- RS-232 data output
- Busy : out std_logic; -- Tx Busy
- DataI : in std_logic_vector(7 downto 0)); -- Byte to transmit
-end TxUnit;
-
-architecture Behaviour of TxUnit is
-
- component synchroniser
- port (
- C1 : in std_logic; -- Asynchronous signal
- C : in std_logic; -- Clock
- O : out Std_logic);-- Synchronised signal
- end component;
-
- signal TBuff : std_logic_vector(7 downto 0); -- transmit buffer
- signal TReg : std_logic_vector(7 downto 0); -- transmit register
- signal TBufL : std_logic; -- Buffer loaded
- signal LoadS : std_logic; -- Synchronised load signal
-
-begin
- -- Synchronise Load on Clk
- SyncLoad : Synchroniser port map (LoadA, Clk, LoadS);
- Busy <= LoadS or TBufL;
-
- -- Tx process
- TxProc : process(Clk, Reset, Enable, DataI, TBuff, TReg, TBufL)
- variable BitPos : INTEGER range 0 to 10; -- Bit position in the frame
- begin
- if Reset = '1' then
- TBufL <= '0';
- BitPos := 0;
- TxD <= '1';
- elsif Rising_Edge(Clk) then
- if LoadS = '1' then
- TBuff <= DataI;
- TBufL <= '1';
- end if;
- if Enable = '1' then
- case BitPos is
- when 0 => -- idle or stop bit
- TxD <= '1';
- if TBufL = '1' then -- start transmit. next is start bit
- TReg <= TBuff;
- TBufL <= '0';
- BitPos := 1;
- end if;
- when 1 => -- Start bit
- TxD <= '0';
- BitPos := 2;
- when others =>
- TxD <= TReg(BitPos-2); -- Serialisation of TReg
- BitPos := BitPos + 1;
- end case;
- if BitPos = 10 then -- bit8. next is stop bit
- BitPos := 0;
- end if;
- end if;
- end if;
- end process;
-end Behaviour;
diff --git a/j1eforth/fpga/src/clock.vhd b/j1eforth/fpga/src/clock.vhd
deleted file mode 100644
index 31536e7..0000000
--- a/j1eforth/fpga/src/clock.vhd
+++ /dev/null
@@ -1,78 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.ALL;
-use ieee.numeric_std.ALL;
-library UNISIM;
-use UNISIM.Vcomponents.ALL;
-
-entity clock is
- port ( clk_in : in std_logic;
- clk : out std_logic;
- clk180 : out std_logic);
-end clock;
-
-architecture BEHAVIORAL of clock is
-
- signal CLKFB_IN : std_logic;
- signal CLKFX_BUF : std_logic;
- signal CLKFX180_BUF : std_logic;
- signal CLKIN_IBUFG : std_logic;
- signal CLK2X_BUF : std_logic;
-
-begin
-
- CLKFX_BUFG_INST : BUFG
- port map (I=>CLKFX_BUF,
- O=>clk);
-
- CLKFX180_BUFG_INST : BUFG
- port map (I=>CLKFX180_BUF,
- O=>clk180);
-
- CLKIN_IBUFG_INST : IBUFG
- port map (I=>clk_in,
- O=>CLKIN_IBUFG);
-
- CLK2X_BUFG_INST : BUFG
- port map (I=>CLK2X_BUF,
- O=>CLKFB_IN);
-
- DCM_SP_INST : DCM_SP
- generic map(
- CLK_FEEDBACK => "2X",
- CLKDV_DIVIDE => 4.0,
- CLKFX_DIVIDE => 1,
- CLKFX_MULTIPLY => 2,
- CLKIN_DIVIDE_BY_2 => FALSE,
- CLKIN_PERIOD => 31.250,
- CLKOUT_PHASE_SHIFT => "NONE",
- DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
- DFS_FREQUENCY_MODE => "LOW",
- DLL_FREQUENCY_MODE => "LOW",
- DUTY_CYCLE_CORRECTION=> TRUE,
- FACTORY_JF => x"C080",
- PHASE_SHIFT => 0,
- STARTUP_WAIT => TRUE)
- port map (
- CLKIN => CLKIN_IBUFG,
- CLKFB => CLKFB_IN,
- DSSEN => '0',
- PSCLK => '0',
- PSEN => '0',
- PSINCDEC => '0',
- RST => '0',
- CLKDV => open,
- CLKFX => CLKFX_BUF,
- CLKFX180 => CLKFX180_BUF,
- CLK2X => CLK2X_BUF,
- CLK2X180 => open,
- CLK0 => open,
- CLK90 => open,
- CLK180 => open,
- CLK270 => open,
- LOCKED => open,
- PSDONE => open,
- STATUS => open);
-
-end BEHAVIORAL;
-
-
diff --git a/j1eforth/fpga/src/j1.v b/j1eforth/fpga/src/j1.v
deleted file mode 100644
index db8901a..0000000
--- a/j1eforth/fpga/src/j1.v
+++ /dev/null
@@ -1,199 +0,0 @@
-/*
-Copyright (c) 2011
- James Bowman All rights reserved.
-
-Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions
-are met:
-1. Redistributions of source code must retain the above copyright
- notice, this list of conditions and the following disclaimer.
-2. Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in the
- documentation and/or other materials provided with the distribution.
-3. Neither the name of James Bowman nor the names of its contributors
- may be used to endorse or promote products derived from this software
- without specific prior written permission.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
-USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
-OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
-SUCH DAMAGE.
-*/
-
-module j1(
- input sys_clk_i, input sys_rst_i, input [15:0] io_din,
- output io_rd, output io_wr, output [15:0] io_addr, output [15:0] io_dout);
-
- reg [15:0] insn;
- wire [15:0] immediate = { 1'b0, insn[14:0] };
-
- reg [4:0] dsp; // Data stack pointer
- reg [4:0] _dsp;
- reg [15:0] st0; // Return stack pointer
- reg [15:0] _st0;
- wire _dstkW; // D stack write
-
- reg [12:0] pc;
- reg [12:0] _pc;
- reg [4:0] rsp;
- reg [4:0] _rsp;
- reg _rstkW; // R stack write
- reg [15:0] _rstkD;
- wire _ramWE; // RAM write enable
-
- wire [15:0] pc_plus_1;
- assign pc_plus_1 = pc + 1;
-
- // The D and R stacks
- reg [15:0] dstack[0:31];
- reg [15:0] rstack[0:31];
- always @(posedge sys_clk_i)
- begin
- if (_dstkW)
- dstack[_dsp] = st0;
- if (_rstkW)
- rstack[_rsp] = _rstkD;
- end
- wire [15:0] st1 = dstack[dsp];
- wire [15:0] rst0 = rstack[rsp];
-
- // st0sel is the ALU operation. For branch and call the operation
- // is T, for 0branch it is N. For ALU ops it is loaded from the instruction
- // field.
- reg [3:0] st0sel;
- always @*
- begin
- case (insn[14:13])
- 2'b00: st0sel = 0; // ubranch
- 2'b10: st0sel = 0; // call
- 2'b01: st0sel = 1; // 0branch
- 2'b11: st0sel = insn[11:8]; // ALU
- default: st0sel = 4'bxxxx;
- endcase
- end
-
-
- // Papilio Pro: main memory to be infered instead of specified explitely.
- reg [15:0] ram[0:16383]; initial $readmemh("../j1.hex", ram);
-
- reg [15:0] mem_din;
- always @(posedge sys_clk_i) begin
- // $monitor("insn_addr= %h, insn = %h, sp=%h, rp=%h, S=%h %h", pc, insn, dsp, rsp, st1, st0);
- insn <= ram[_pc];
- mem_din <= ram[_st0[15:1]];
- if (_ramWE & (_st0[15:14] ==0))
- ram[_st0[15:1]] <= st1[15:0];
- end
-
-
- // Compute the new value of T.
- always @*
- begin
- if (insn[15])
- _st0 = immediate;
- else
- case (st0sel)
- 4'b0000: _st0 = st0;
- 4'b0001: _st0 = st1;
- 4'b0010: _st0 = st0 + st1;
- 4'b0011: _st0 = st0 & st1;
- 4'b0100: _st0 = st0 | st1;
- 4'b0101: _st0 = st0 ^ st1;
- 4'b0110: _st0 = ~st0;
- 4'b0111: _st0 = {16{(st1 == st0)}};
- 4'b1000: _st0 = {16{($signed(st1) < $signed(st0))}};
- 4'b1001: _st0 = st1 >> st0[3:0];
- 4'b1010: _st0 = st0 - 1;
- 4'b1011: _st0 = rst0;
- 4'b1100: _st0 = |st0[15:14] ? io_din : mem_din;
- 4'b1101: _st0 = st1 << st0[3:0];
- 4'b1110: _st0 = {rsp, 3'b000, dsp};
- 4'b1111: _st0 = {16{(st1 < st0)}};
- default: _st0 = 16'hxxxx;
- endcase
- end
-
- wire is_alu = (insn[15:13] == 3'b011);
- wire is_lit = (insn[15]);
-
- assign io_rd = (is_alu & (insn[11:8] == 4'hc));
- assign io_wr = _ramWE;
- assign io_addr = st0;
- assign io_dout = st1;
-
- assign _ramWE = is_alu & insn[5];
- assign _dstkW = is_lit | (is_alu & insn[7]);
-
- wire [1:0] dd = insn[1:0]; // D stack delta
- wire [1:0] rd = insn[3:2]; // R stack delta
-
- always @*
- begin
- if (is_lit) begin // literal
- _dsp = dsp + 1;
- _rsp = rsp;
- _rstkW = 0;
- _rstkD = _pc;
- end else if (is_alu) begin
- _dsp = dsp + {dd[1], dd[1], dd[1], dd};
- _rsp = rsp + {rd[1], rd[1], rd[1], rd};
- _rstkW = insn[6];
- _rstkD = st0;
- end else begin // jump/call
- // predicated jump is like DROP
- if (insn[15:13] == 3'b001) begin
- _dsp = dsp - 1;
- end else begin
- _dsp = dsp;
- end
- if (insn[15:13] == 3'b010) begin // call
- _rsp = rsp + 1;
- _rstkW = 1;
- _rstkD = {pc_plus_1[14:0], 1'b0};
- end else begin
- _rsp = rsp;
- _rstkW = 0;
- _rstkD = _pc;
- end
- end
- end
-
- always @*
- begin
- if (sys_rst_i)
- _pc = pc;
- else
- if ((insn[15:13] == 3'b000) |
- ((insn[15:13] == 3'b001) & (|st0 == 0)) |
- (insn[15:13] == 3'b010))
- _pc = insn[12:0];
- else if (is_alu & insn[12])
- _pc = rst0[15:1];
- else
- _pc = pc_plus_1;
- end
-
- always @(posedge sys_clk_i)
- begin
- if (sys_rst_i) begin
- pc <= 0;
- dsp <= 0;
- st0 <= 0;
- rsp <= 0;
- end else begin
- dsp <= _dsp;
- pc <= _pc;
- st0 <= _st0;
- rsp <= _rsp;
- end
- end
-
-endmodule // j1
diff --git a/j1eforth/fpga/src/miniuart.vhd b/j1eforth/fpga/src/miniuart.vhd
deleted file mode 100644
index 2ee4f3c..0000000
--- a/j1eforth/fpga/src/miniuart.vhd
+++ /dev/null
@@ -1,146 +0,0 @@
--------------------------------------------------------------------------------
--- Title : MINIUART2 -- this is a modified version without Wishbone interface
--- Project : MINIUART2
--------------------------------------------------------------------------------
--- File : MiniUart.vhd
--- Author : Philippe CARTON
--- (philippe.carton2@libertysurf.fr)
--- Organization:
--- Created : 15/12/2001
--- Last update : 8/1/2003
--- Platform : Foundation 3.1i
--- Simulators : ModelSim 5.5b
--- Synthesizers: Xilinx Synthesis
--- Targets : Xilinx Spartan
--- Dependency : IEEE std_logic_1164, Rxunit.vhd, Txunit.vhd, utils.vhd
--------------------------------------------------------------------------------
--- Description: Uart (Universal Asynchronous Receiver Transmitter) for SoC.
--- Wishbone compatable.
--------------------------------------------------------------------------------
--- Copyright (c) notice
--- This core adheres to the GNU public license
---
--------------------------------------------------------------------------------
--- Revisions :
--- Revision Number :
--- Version :
--- Date :
--- Modifier : name <email>
--- Description :
---
--------------------------------------------------------------------------------
--- Revision History:
--- 2014-12-19: removed wishbone interface (uh@xlerb.de)
-
-
-library ieee;
- use ieee.std_logic_1164.all;
-
-entity MINIUART2 is
- generic(BRDIVISOR: INTEGER range 0 to 65535 := 143); -- Baud rate divisor 143 = 115200 at 66 Mhz
- port (
- clk: in STD_LOGIC;
- rst: in STD_LOGIC;
- rx: in STD_LOGIC;
- tx: out STD_LOGIC;
- io_rd: in STD_LOGIC;
- io_wr: in STD_LOGIC;
- io_addr: in STD_LOGIC;
- io_din: in STD_LOGIC_VECTOR (15 downto 0);
- io_dout: out STD_LOGIC_VECTOR (15 downto 0));
-end MINIUART2;
-
--- Architecture for UART for synthesis
-architecture Behaviour of MINIUART2 is
-
- component Counter
- generic(COUNT: INTEGER range 0 to 65535); -- Count revolution
- port (
- Clk : in std_logic; -- Clock
- Reset : in std_logic; -- Reset input
- CE : in std_logic; -- Chip Enable
- O : out std_logic); -- Output
- end component;
-
- component RxUnit
- port (
- Clk : in std_logic; -- system clock signal
- Reset : in std_logic; -- Reset input
- Enable : in std_logic; -- Enable input
- ReadA : in Std_logic; -- Async Read Received Byte
- RxD : in std_logic; -- RS-232 data input
- RxAv : out std_logic; -- Byte available
- DataO : out std_logic_vector(7 downto 0)); -- Byte received
- end component;
-
- component TxUnit
- port (
- Clk : in std_logic; -- Clock signal
- Reset : in std_logic; -- Reset input
- Enable : in std_logic; -- Enable input
- LoadA : in std_logic; -- Asynchronous Load
- TxD : out std_logic; -- RS-232 data output
- Busy : out std_logic; -- Tx Busy
- DataI : in std_logic_vector(7 downto 0)); -- Byte to transmit
- end component;
-
- signal RxData : std_logic_vector(7 downto 0); -- Last Byte received
- signal TxData : std_logic_vector(7 downto 0); -- Last bytes transmitted
- signal SReg : std_logic_vector(7 downto 0); -- Status register
- signal EnabRx : std_logic; -- Enable RX unit
- signal EnabTx : std_logic; -- Enable TX unit
- signal RxAv : std_logic; -- Data Received
- signal TxBusy : std_logic; -- Transmiter Busy
- signal ReadA : std_logic; -- Async Read receive buffer
- signal LoadA : std_logic; -- Async Load transmit buffer
- signal Sig0 : std_logic; -- gnd signal
- signal Sig1 : std_logic; -- vcc signal
-
-
- begin
- sig0 <= '0';
- sig1 <= '1';
- Uart_Rxrate : Counter -- Baud Rate adjust
- generic map (COUNT => BRDIVISOR)
- port map (clk, rst, sig1, EnabRx);
- Uart_Txrate : Counter -- 4 Divider for Tx
- generic map (COUNT => 4)
- port map (clk, rst, EnabRx, EnabTx);
- Uart_TxUnit : TxUnit port map (clk, rst, EnabTX, LoadA, tx, TxBusy, TxData);
- Uart_RxUnit : RxUnit port map (clk, rst, EnabRX, ReadA, rx, RxAv, RxData);
-
- -- status register
- SReg(0) <= RxAv;
- SReg(1) <= TxBusy;
- SReg(7 downto 2) <= (others => '0'); -- the rest is silence
-
- process (clk, rst, io_addr, io_wr, io_din)
- begin
- if Rising_Edge(clk) then
- if rst='1' then
- LoadA <= '0';
- elsif io_wr='1' and io_addr='0' then -- write byte to tx
- TxData <= io_din(7 downto 0);
- LoadA <= '1';
- else
- LoadA <= '0';
- end if;
- end if;
- end process;
-
- process (clk, rst, io_addr, io_rd, RxData, TxBusy, RxAv)
- begin
- if Rising_Edge(clk) then
- if rst='1' then
- ReadA <= '0';
- elsif io_rd='1' and io_addr='0' then
- ReadA <= '1';
- else
- ReadA <= '0';
- end if;
- end if;
- end process;
- io_dout(7 downto 0) <= RxData when io_addr='0' else SReg;
- io_dout(15 downto 8) <= (others => '0');
-
-end Behaviour;
diff --git a/j1eforth/fpga/src/papilio-pro-j1.vhd b/j1eforth/fpga/src/papilio-pro-j1.vhd
deleted file mode 100644
index 4680c07..0000000
--- a/j1eforth/fpga/src/papilio-pro-j1.vhd
+++ /dev/null
@@ -1,117 +0,0 @@
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.NUMERIC_STD.ALL;
-
-entity papilio_pro_j1 is
- port (
- clk_in: in std_logic;
- rx: in std_logic;
- tx: out std_logic;
- wing: out std_logic_vector(15 downto 0));
-end papilio_pro_j1;
-
-architecture Behavioral of papilio_pro_j1 is
-
- component clock is
- port (
- clk_in: in std_logic;
- clk: out std_logic;
- clk180: out std_logic);
- end component;
-
- component j1 is
- port (
- sys_clk_i: in std_logic;
- sys_rst_i: in std_logic;
- io_rd: out std_logic;
- io_wr: out std_logic;
- io_addr: out std_logic_vector (15 downto 0);
- io_din: in std_logic_vector (15 downto 0);
- io_dout: out std_logic_vector (15 downto 0));
- end component;
-
- component miniuart2 is
- port (
- clk: in STD_LOGIC;
- rst: in STD_LOGIC;
- rx: in STD_LOGIC;
- tx: out STD_LOGIC;
- io_rd: in STD_LOGIC;
- io_wr: in STD_LOGIC;
- io_addr: in STD_LOGIC;
- io_din: in STD_LOGIC_VECTOR (15 downto 0);
- io_dout: out STD_LOGIC_VECTOR (15 downto 0));
- end component;
-
-
- signal clk: std_logic;
- signal clk180: std_logic;
-
- signal rst_counter: integer range 0 to 15 := 15;
- signal sys_rst: std_logic := '1';
-
- signal io_rd: std_logic;
- signal io_wr: std_logic;
- signal io_addr: std_logic_vector (15 downto 0);
- signal io_din: std_logic_vector (15 downto 0);
- signal io_dout: std_logic_vector (15 downto 0);
-
- signal uart_en: std_logic;
- signal uart_rd: std_logic;
- signal uart_wr: std_logic;
- signal uart_dout: std_logic_vector (15 downto 0);
-begin
-
- clock_inst: clock
- port map (
- clk_in => clk_in,
- clk => clk,
- clk180 => clk180);
-
- j1_inst: j1
- port map (
- sys_clk_i => clk,
- sys_rst_i => sys_rst,
- io_rd => io_rd,
- io_wr => io_wr,
- io_addr => io_addr,
- io_din => io_din,
- io_dout => io_dout);
-
- uart_inst: miniuart2
- port map(
- clk => clk180,
- rst => sys_rst,
- rx => rx,
- tx => tx,
- io_rd => uart_rd,
- io_wr => uart_wr,
- io_addr => io_addr(0),
- io_din => io_dout,
- io_dout => uart_dout);
-
- process (clk, rst_counter)
- begin
- if rising_edge(clk) and rst_counter>0 then
- rst_counter <= rst_counter-1;
- end if;
- end process;
- sys_rst <= '1' when rst_counter>0 else '0';
-
- uart_en <= '1' when io_addr(15 downto 1)="111100000000000" else '0';
- uart_rd <= io_rd and uart_en;
- uart_wr <= io_wr and uart_en;
-
- process (io_addr, uart_dout)
- begin
- case io_addr(15 downto 1) is
- when "111100000000000" =>
- io_din <= uart_dout;
- when others =>
- io_din <= (others=>'0');
- end case;
- end process;
-
- wing <= (others=>'0');
-
-end Behavioral; \ No newline at end of file
diff --git a/j1eforth/fpga/src/papilio-pro.ucf b/j1eforth/fpga/src/papilio-pro.ucf
deleted file mode 100644
index 338cd2d..0000000
--- a/j1eforth/fpga/src/papilio-pro.ucf
+++ /dev/null
@@ -1,143 +0,0 @@
-# UCF file for the Papilio Pro board
-# Generated by pin_converter, written by Kevin Lindsey
-# https://github.com/thelonious/papilio_pins/tree/development/pin_converter
-
-# Main board wing pin [] to FPGA pin Pxx map
-# -------C------- -------B------- -------A-------
-# [GND] [C00] P114 [GND] [B00] P99 P100 [A15]
-# [2V5] [C01] P115 [2V5] [B01] P97 P98 [A14]
-# [3V3] [C02] P116 [3V3] [B02] P92 P93 [A13]
-# [5V0] [C03] P117 [5V0] [B03] P87 P88 [A12]
-# [C04] P118 [B04] P84 P85 [A11] [5V0]
-# [C05] P119 [B05] P82 P83 [A10] [3V3]
-# [C06] P120 [B06] P80 P81 [A09] [2V5]
-# [C07] P121 [B07] P78 P79 [A08] [GND]
-# [GND] [C08] P123 [GND] [B08] P74 P75 [A07]
-# [2V5] [C09] P124 [2V5] [B09] P95 P67 [A06]
-# [3V3] [C10] P126 [3V3] [B10] P62 P66 [A05]
-# [5V0] [C11] P127 [5V0] [B11] P59 P61 [A04]
-# [C12] P131 [B12] P57 P58 [A03] [5V0]
-# [C13] P132 [B13] P55 P56 [A02] [3V3]
-# [C14] P133 [B14] P50 P51 [A01] [2V5]
-# [C15] P134 [B15] P47 P48 [A00] [GND]
-
-## Prohibit the automatic placement of pins that are connected to VCC or GND for configuration.
-CONFIG PROHIBIT=P144;
-CONFIG PROHIBIT=P69;
-CONFIG PROHIBIT=P60;
-
-NET CLK_IN LOC="P94" | IOSTANDARD=LVTTL | PERIOD=31.25ns; # CLK
-NET RX LOC="P101" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # RX
-NET TX LOC="P105" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # TX
-NET WING(0) LOC="P48" | IOSTANDARD=LVTTL; # A0
-NET WING(1) LOC="P51" | IOSTANDARD=LVTTL; # A1
-NET WING(2) LOC="P56" | IOSTANDARD=LVTTL; # A2
-NET WING(3) LOC="P58" | IOSTANDARD=LVTTL; # A3
-NET WING(4) LOC="P61" | IOSTANDARD=LVTTL; # A4
-NET WING(5) LOC="P66" | IOSTANDARD=LVTTL; # A5
-NET WING(6) LOC="P67" | IOSTANDARD=LVTTL; # A6
-NET WING(7) LOC="P75" | IOSTANDARD=LVTTL; # A7
-NET WING(8) LOC="P79" | IOSTANDARD=LVTTL; # A8
-NET WING(9) LOC="P81" | IOSTANDARD=LVTTL; # A9
-NET WING(10) LOC="P83" | IOSTANDARD=LVTTL; # A10
-NET WING(11) LOC="P85" | IOSTANDARD=LVTTL; # A11
-NET WING(12) LOC="P88" | IOSTANDARD=LVTTL; # A12
-NET WING(13) LOC="P93" | IOSTANDARD=LVTTL; # A13
-NET WING(14) LOC="P98" | IOSTANDARD=LVTTL; # A14
-NET WING(15) LOC="P100" | IOSTANDARD=LVTTL; # A15
-#NET A(0) LOC="P48" | IOSTANDARD=LVTTL; # A0
-#NET A(1) LOC="P51" | IOSTANDARD=LVTTL; # A1
-#NET A(2) LOC="P56" | IOSTANDARD=LVTTL; # A2
-#NET A(3) LOC="P58" | IOSTANDARD=LVTTL; # A3
-#NET A(4) LOC="P61" | IOSTANDARD=LVTTL; # A4
-#NET A(5) LOC="P66" | IOSTANDARD=LVTTL; # A5
-#NET A(6) LOC="P67" | IOSTANDARD=LVTTL; # A6
-#NET A(7) LOC="P75" | IOSTANDARD=LVTTL; # A7
-#NET A(8) LOC="P79" | IOSTANDARD=LVTTL; # A8
-#NET A(9) LOC="P81" | IOSTANDARD=LVTTL; # A9
-#NET A(10) LOC="P83" | IOSTANDARD=LVTTL; # A10
-#NET A(11) LOC="P85" | IOSTANDARD=LVTTL; # A11
-#NET A(12) LOC="P88" | IOSTANDARD=LVTTL; # A12
-#NET A(13) LOC="P93" | IOSTANDARD=LVTTL; # A13
-#NET A(14) LOC="P98" | IOSTANDARD=LVTTL; # A14
-#NET A(15) LOC="P100" | IOSTANDARD=LVTTL; # A15
-#NET B(0) LOC="P99" | IOSTANDARD=LVTTL; # B0
-#NET B(1) LOC="P97" | IOSTANDARD=LVTTL; # B1
-#NET B(2) LOC="P92" | IOSTANDARD=LVTTL; # B2
-#NET B(3) LOC="P87" | IOSTANDARD=LVTTL; # B3
-#NET B(4) LOC="P84" | IOSTANDARD=LVTTL; # B4
-#NET B(5) LOC="P82" | IOSTANDARD=LVTTL; # B5
-#NET B(6) LOC="P80" | IOSTANDARD=LVTTL; # B6
-#NET B(7) LOC="P78" | IOSTANDARD=LVTTL; # B7
-#NET B(8) LOC="P74" | IOSTANDARD=LVTTL; # B8
-#NET B(9) LOC="P95" | IOSTANDARD=LVTTL; # B9
-#NET B(10) LOC="P62" | IOSTANDARD=LVTTL; # B10
-#NET B(11) LOC="P59" | IOSTANDARD=LVTTL; # B11
-#NET B(12) LOC="P57" | IOSTANDARD=LVTTL; # B12
-#NET B(13) LOC="P55" | IOSTANDARD=LVTTL; # B13
-#NET B(14) LOC="P50" | IOSTANDARD=LVTTL; # B14
-#NET B(15) LOC="P47" | IOSTANDARD=LVTTL; # B15
-#NET C(0) LOC="P114" | IOSTANDARD=LVTTL; # C0
-#NET C(1) LOC="P115" | IOSTANDARD=LVTTL; # C1
-#NET C(2) LOC="P116" | IOSTANDARD=LVTTL; # C2
-#NET C(3) LOC="P117" | IOSTANDARD=LVTTL; # C3
-#NET C(4) LOC="P118" | IOSTANDARD=LVTTL; # C4
-#NET C(5) LOC="P119" | IOSTANDARD=LVTTL; # C5
-#NET C(6) LOC="P120" | IOSTANDARD=LVTTL; # C6
-#NET C(7) LOC="P121" | IOSTANDARD=LVTTL; # C7
-#NET C(8) LOC="P123" | IOSTANDARD=LVTTL; # C8
-#NET C(9) LOC="P124" | IOSTANDARD=LVTTL; # C9
-#NET C(10) LOC="P126" | IOSTANDARD=LVTTL; # C10
-#NET C(11) LOC="P127" | IOSTANDARD=LVTTL; # C11
-#NET C(12) LOC="P131" | IOSTANDARD=LVTTL; # C12
-#NET C(13) LOC="P132" | IOSTANDARD=LVTTL; # C13
-#NET C(14) LOC="P133" | IOSTANDARD=LVTTL; # C14
-#NET C(15) LOC="P134" | IOSTANDARD=LVTTL; # C15
-#NET SDRAM_ADDR(0) LOC="P140" | IOSTANDARD=LVTTL; # SDRAM_ADDR0
-#NET SDRAM_ADDR(1) LOC="P139" | IOSTANDARD=LVTTL; # SDRAM_ADDR1
-#NET SDRAM_ADDR(2) LOC="P138" | IOSTANDARD=LVTTL; # SDRAM_ADDR2
-#NET SDRAM_ADDR(3) LOC="P137" | IOSTANDARD=LVTTL; # SDRAM_ADDR3
-#NET SDRAM_ADDR(4) LOC="P46" | IOSTANDARD=LVTTL; # SDRAM_ADDR4
-#NET SDRAM_ADDR(5) LOC="P45" | IOSTANDARD=LVTTL; # SDRAM_ADDR5
-#NET SDRAM_ADDR(6) LOC="P44" | IOSTANDARD=LVTTL; # SDRAM_ADDR6
-#NET SDRAM_ADDR(7) LOC="P43" | IOSTANDARD=LVTTL; # SDRAM_ADDR7
-#NET SDRAM_ADDR(8) LOC="P41" | IOSTANDARD=LVTTL; # SDRAM_ADDR8
-#NET SDRAM_ADDR(9) LOC="P40" | IOSTANDARD=LVTTL; # SDRAM_ADDR9
-#NET SDRAM_ADDR(10) LOC="P141" | IOSTANDARD=LVTTL; # SDRAM_ADDR10
-#NET SDRAM_ADDR(11) LOC="P35" | IOSTANDARD=LVTTL; # SDRAM_ADDR11
-#NET SDRAM_ADDR(12) LOC="P34" | IOSTANDARD=LVTTL; # SDRAM_ADDR12
-#NET SDRAM_DATA(0) LOC="P9" | IOSTANDARD=LVTTL; # SDRAM_DATA0
-#NET SDRAM_DATA(1) LOC="P10" | IOSTANDARD=LVTTL; # SDRAM_DATA1
-#NET SDRAM_DATA(2) LOC="P11" | IOSTANDARD=LVTTL; # SDRAM_DATA2
-#NET SDRAM_DATA(3) LOC="P12" | IOSTANDARD=LVTTL; # SDRAM_DATA3
-#NET SDRAM_DATA(4) LOC="P14" | IOSTANDARD=LVTTL; # SDRAM_DATA4
-#NET SDRAM_DATA(5) LOC="P15" | IOSTANDARD=LVTTL; # SDRAM_DATA5
-#NET SDRAM_DATA(6) LOC="P16" | IOSTANDARD=LVTTL; # SDRAM_DATA6
-#NET SDRAM_DATA(7) LOC="P8" | IOSTANDARD=LVTTL; # SDRAM_DATA7
-#NET SDRAM_DATA(8) LOC="P21" | IOSTANDARD=LVTTL; # SDRAM_DATA8
-#NET SDRAM_DATA(9) LOC="P22" | IOSTANDARD=LVTTL; # SDRAM_DATA9
-#NET SDRAM_DATA(10) LOC="P23" | IOSTANDARD=LVTTL; # SDRAM_DATA10
-#NET SDRAM_DATA(11) LOC="P24" | IOSTANDARD=LVTTL; # SDRAM_DATA11
-#NET SDRAM_DATA(12) LOC="P26" | IOSTANDARD=LVTTL; # SDRAM_DATA12
-#NET SDRAM_DATA(13) LOC="P27" | IOSTANDARD=LVTTL; # SDRAM_DATA13
-#NET SDRAM_DATA(14) LOC="P29" | IOSTANDARD=LVTTL; # SDRAM_DATA14
-#NET SDRAM_DATA(15) LOC="P30" | IOSTANDARD=LVTTL; # SDRAM_DATA15
-#NET SDRAM_DQML LOC="P7" | IOSTANDARD=LVTTL; # SDRAM_DQML
-#NET SDRAM_DQMH LOC="P17" | IOSTANDARD=LVTTL; # SDRAM_DQMH
-#NET SDRAM_BA(0) LOC="P143" | IOSTANDARD=LVTTL; # SDRAM_BA0
-#NET SDRAM_BA(1) LOC="P142" | IOSTANDARD=LVTTL; # SDRAM_BA1
-#NET SDRAM_nWE LOC="P6" | IOSTANDARD=LVTTL; # SDRAM_nWE
-#NET SDRAM_nCAS LOC="P5" | IOSTANDARD=LVTTL; # SDRAM_nCAS
-#NET SDRAM_nRAS LOC="P2" | IOSTANDARD=LVTTL; # SDRAM_nRAS
-#NET SDRAM_CS LOC="P1" | IOSTANDARD=LVTTL; # SDRAM_CS
-#NET SDRAM_CLK LOC="P32" | IOSTANDARD=LVTTL; # SDRAM_CLK
-#NET SDRAM_CKE LOC="P33" | IOSTANDARD=LVTTL; # SDRAM_CKE
-#NET LED1 LOC="P112" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=SLOW; # LED1
-#NET JTAG_TMS LOC="P107" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # JTAG_TMS
-#NET JTAG_TCK LOC="P109" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # JTAG_TCK
-#NET JTAG_TDI LOC="P110" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # JTAG_TDI
-#NET JTAG_TDO LOC="P106" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # JTAG_TDO
-#NET FLASH_CS LOC="P38" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # FLASH_CS
-#NET FLASH_CK LOC="P70" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # FLASH_CK
-#NET FLASH_SI LOC="P64" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # FLASH_SI
-#NET FLASH_SO LOC="P65" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST | PULLUP; # FLASH_SO
diff --git a/j1eforth/fpga/src/utils.vhd b/j1eforth/fpga/src/utils.vhd
deleted file mode 100644
index 19eb1f7..0000000
--- a/j1eforth/fpga/src/utils.vhd
+++ /dev/null
@@ -1,132 +0,0 @@
--------------------------------------------------------------------------------
--- Title : UART
--- Project : UART
--------------------------------------------------------------------------------
--- File : utils.vhd
--- Author : Philippe CARTON
--- (philippe.carton2@libertysurf.fr)
--- Organization:
--- Created : 15/12/2001
--- Last update : 8/1/2003
--- Platform : Foundation 3.1i
--- Simulators : ModelSim 5.5b
--- Synthesizers: Xilinx Synthesis
--- Targets : Xilinx Spartan
--- Dependency : IEEE std_logic_1164
--------------------------------------------------------------------------------
--- Description: VHDL utility file
--------------------------------------------------------------------------------
--- Copyright (c) notice
--- This core adheres to the GNU public license
---
--------------------------------------------------------------------------------
--- Revisions :
--- Revision Number :
--- Version :
--- Date :
--- Modifier : name <email>
--- Description :
---
-------------------------------------------------------------------------------
-
-
--------------------------------------------------------------------------------
--- Revision list
--- Version Author Date Changes
---
--- 1.0 Philippe CARTON 19 December 2001 New model
--- philippe.carton2@libertysurf.fr
--------------------------------------------------------------------------------
-
---------------------------------------------------------------------------------
--- Synchroniser:
--- Synchronize an input signal (C1) with an input clock (C).
--- The result is the O signal which is synchronous of C, and persist for
--- one C clock period.
---------------------------------------------------------------------------------
-library IEEE,STD;
-use IEEE.std_logic_1164.all;
-
-entity synchroniser is
- port (
- C1 : in std_logic;-- Asynchronous signal
- C : in std_logic;-- Clock
- O : out std_logic);-- Synchronised signal
-end synchroniser;
-
-architecture Behaviour of synchroniser is
- signal C1A : std_logic;
- signal C1S : std_logic;
- signal R : std_logic;
-begin
- RiseC1A : process(C1,R)
- begin
- if Rising_Edge(C1) then
- C1A <= '1';
- end if;
- if (R = '1') then
- C1A <= '0';
- end if;
- end process;
-
- SyncP : process(C,R)
- begin
- if Rising_Edge(C) then
- if (C1A = '1') then
- C1S <= '1';
- else C1S <= '0';
- end if;
- if (C1S = '1') then
- R <= '1';
- else R <= '0';
- end if;
- end if;
- if (R = '1') then
- C1S <= '0';
- end if;
- end process;
- O <= C1S;
-end Behaviour;
-
--------------------------------------------------------------------------------
--- Counter
--- This counter is a parametrizable clock divider.
--- The count value is the generic parameter Count.
--- It is CE enabled. (it will count only if CE is high).
--- When it overflow, it will emit a pulse on O.
--- It can be reseted to 0.
--------------------------------------------------------------------------------
-library IEEE,STD;
-use IEEE.std_logic_1164.all;
-
-entity Counter is
- generic(Count: INTEGER range 0 to 65535); -- Count revolution
- port (
- Clk : in std_logic; -- Clock
- Reset : in std_logic; -- Reset input
- CE : in std_logic; -- Chip Enable
- O : out std_logic); -- Output
-end Counter;
-
-architecture Behaviour of Counter is
-begin
- counter : process(Clk,Reset)
- variable Cnt : INTEGER range 0 to Count-1;
- begin
- if Reset = '1' then
- Cnt := Count - 1;
- O <= '0';
- elsif Rising_Edge(Clk) then
- if CE = '1' then
- if Cnt = 0 then
- O <= '1';
- Cnt := Count - 1;
- else
- O <= '0';
- Cnt := Cnt - 1;
- end if;
- else O <= '0';
- end if;
- end if;
- end process;
-end Behaviour;
diff --git a/j1eforth/fpga/test/miniuart2_tb.vhd b/j1eforth/fpga/test/miniuart2_tb.vhd
deleted file mode 100644
index 6049582..0000000
--- a/j1eforth/fpga/test/miniuart2_tb.vhd
+++ /dev/null
@@ -1,128 +0,0 @@
---------------------------------------------------------------------------------
--- Company:
--- Engineer:
---
--- Create Date: 11:48:15 12/20/2014
--- Design Name:
--- Module Name: /mnt/hgfs/Projects/j1eforth/vhdl/test/miniuart2_tb.vhd
--- Project Name: papilio-pro-forth
--- Target Device:
--- Tool versions:
--- Description:
---
--- VHDL Test Bench Created by ISE for module: MINIUART2
---
--- Dependencies:
---
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
--- Notes:
--- This testbench has been automatically generated using types std_logic and
--- std_logic_vector for the ports of the unit under test. Xilinx recommends
--- that these types always be used for the top-level I/O of a design in order
--- to guarantee that the testbench will bind correctly to the post-implementation
--- simulation model.
---------------------------------------------------------------------------------
-LIBRARY ieee;
-USE ieee.std_logic_1164.ALL;
-
--- Uncomment the following library declaration if using
--- arithmetic functions with Signed or Unsigned values
---USE ieee.numeric_std.ALL;
-
-ENTITY miniuart2_tb IS
-END miniuart2_tb;
-
-ARCHITECTURE behavior OF miniuart2_tb IS
-
- -- Component Declaration for the Unit Under Test (UUT)
-
- COMPONENT MINIUART2
- PORT(
- clk : IN std_logic;
- rst : IN std_logic;
- rx : IN std_logic;
- tx : OUT std_logic;
- io_rd : IN std_logic;
- io_wr : IN std_logic;
- io_addr : IN std_logic;
- io_din : IN std_logic_vector(15 downto 0);
- io_dout : OUT std_logic_vector(15 downto 0)
- );
- END COMPONENT;
-
-
- --Inputs
- signal clk : std_logic := '0';
- signal rst : std_logic := '0';
- signal rx : std_logic := '0';
- signal io_rd : std_logic := '0';
- signal io_wr : std_logic := '0';
- signal io_addr : std_logic := '0';
- signal io_din : std_logic_vector(15 downto 0) := (others => '0');
-
- --Outputs
- signal tx : std_logic;
- signal io_dout : std_logic_vector(15 downto 0);
-
- -- Clock period definitions
- constant clk_period : time := 10 ns; -- 31.25 ns;
-
-BEGIN
-
- -- Instantiate the Unit Under Test (UUT)
- uut: MINIUART2 PORT MAP (
- clk => clk,
- rst => rst,
- rx => rx,
- tx => tx,
- io_rd => io_rd,
- io_wr => io_wr,
- io_addr => io_addr,
- io_din => io_din,
- io_dout => io_dout
- );
-
- -- Clock process definitions
- clk_process :process
- begin
- clk <= '0';
- wait for clk_period/2;
- clk <= '1';
- wait for clk_period/2;
- end process;
-
-
- -- Stimulus process
- stim_proc: process
- begin
- -- hold reset state for 100 ns.
- wait for 100 ns;
-
- wait for clk_period*5;
-
- rst <= '1';
-
- wait for clk_period*3;
-
- rst <= '0';
-
- wait for clk_period*3;
-
- -- insert stimulus here
- io_din <= X"002A";
- io_addr <= '1';
- io_wr <= '1';
-
- wait for clk_period;
-
- io_addr <= '0';
- io_din <= X"0000";
- io_wr <= '0';
-
- wait;
- end process;
-
-END;
diff --git a/j1eforth/fpga/test/papilio_pro_j1_tb.vhd b/j1eforth/fpga/test/papilio_pro_j1_tb.vhd
deleted file mode 100644
index 3aedf53..0000000
--- a/j1eforth/fpga/test/papilio_pro_j1_tb.vhd
+++ /dev/null
@@ -1,96 +0,0 @@
---------------------------------------------------------------------------------
--- Company:
--- Engineer:
---
--- Create Date: 22:12:23 03/03/2012
--- Design Name:
--- Module Name: /home/ben/prog/PapilioForth/ise/main_tb.vhd
--- Project Name: PapilioForth
--- Target Device:
--- Tool versions:
--- Description:
---
--- VHDL Test Bench Created by ISE for module: main
---
--- Dependencies:
---
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
--- Notes:
--- This testbench has been automatically generated using types std_logic and
--- std_logic_vector for the ports of the unit under test. Xilinx recommends
--- that these types always be used for the top-level I/O of a design in order
--- to guarantee that the testbench will bind correctly to the post-implementation
--- simulation model.
---------------------------------------------------------------------------------
-LIBRARY ieee;
-USE ieee.std_logic_1164.ALL;
-
--- Uncomment the following library declaration if using
--- arithmetic functions with Signed or Unsigned values
---USE ieee.numeric_std.ALL;
-
-ENTITY papilio_pro_j1_tb IS
-END papilio_pro_j1_tb;
-
-ARCHITECTURE behavior OF papilio_pro_j1_tb IS
-
- -- Component Declaration for the Unit Under Test (UUT)
-
- COMPONENT papilio_pro_j1
- PORT(
- clk_in : IN std_logic;
- rx : IN std_logic;
- tx : OUT std_logic;
- wing : INOUT std_logic_vector(15 downto 0)
- );
- END COMPONENT;
-
-
- --Inputs
- signal clk_in : std_logic := '0';
- signal rx : std_logic := '0';
-
- --Outputs
- signal tx : std_logic;
- signal wing : std_logic_vector(15 downto 0);
-
- -- Clock period definitions
- constant clk_in_period : time := 31.25 ns;
-
-BEGIN
-
- -- Instantiate the Unit Under Test (UUT)
- uut: papilio_pro_j1 PORT MAP (
- clk_in => clk_in,
- rx => rx,
- tx => tx,
- wing => wing
- );
-
- -- Clock process definitions
- clk_in_process :process
- begin
- clk_in <= '0';
- wait for clk_in_period/2;
- clk_in <= '1';
- wait for clk_in_period/2;
- end process;
-
-
- -- Stimulus process
- stim_proc: process
- begin
- -- hold reset state for 100 ns.
- wait for 100 ns;
-
- wait for clk_in_period*50;
-
- -- insert stimulus here
-
- wait;
- end process;
-
-END;