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-rw-r--r--docs/j1eforth/fpga/src/Rxunit.vhd97
-rw-r--r--docs/j1eforth/fpga/src/Txunit.vhd100
-rw-r--r--docs/j1eforth/fpga/src/clock.vhd78
-rw-r--r--docs/j1eforth/fpga/src/j1.v199
-rw-r--r--docs/j1eforth/fpga/src/miniuart.vhd146
-rw-r--r--docs/j1eforth/fpga/src/papilio-pro-j1.vhd117
-rw-r--r--docs/j1eforth/fpga/src/papilio-pro.ucf143
-rw-r--r--docs/j1eforth/fpga/src/utils.vhd132
8 files changed, 1012 insertions, 0 deletions
diff --git a/docs/j1eforth/fpga/src/Rxunit.vhd b/docs/j1eforth/fpga/src/Rxunit.vhd
new file mode 100644
index 0000000..c30a30e
--- /dev/null
+++ b/docs/j1eforth/fpga/src/Rxunit.vhd
@@ -0,0 +1,97 @@
+-------------------------------------------------------------------------------
+-- Title : UART
+-- Project : UART
+-------------------------------------------------------------------------------
+-- File : Rxunit.vhd
+-- Author : Philippe CARTON
+-- (philippe.carton2@libertysurf.fr)
+-- Organization:
+-- Created : 15/12/2001
+-- Last update : 8/1/2003
+-- Platform : Foundation 3.1i
+-- Simulators : ModelSim 5.5b
+-- Synthesizers: Xilinx Synthesis
+-- Targets : Xilinx Spartan
+-- Dependency : IEEE std_logic_1164
+-------------------------------------------------------------------------------
+-- Description: RxUnit is a serial to parallel unit Receiver.
+-------------------------------------------------------------------------------
+-- Copyright (c) notice
+-- This core adheres to the GNU public license
+--
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Revision Number :
+-- Version :
+-- Date :
+-- Modifier : name <email>
+-- Description :
+--
+------------------------------------------------------------------------------
+library ieee;
+ use ieee.std_logic_1164.all;
+
+entity RxUnit is
+ port (
+ Clk : in std_logic; -- system clock signal
+ Reset : in std_logic; -- Reset input
+ Enable : in std_logic; -- Enable input
+ ReadA : in Std_logic; -- Async Read Received Byte
+ RxD : in std_logic; -- RS-232 data input
+ RxAv : out std_logic; -- Byte available
+ DataO : out std_logic_vector(7 downto 0)); -- Byte received
+end RxUnit;
+
+architecture Behaviour of RxUnit is
+ signal RReg : std_logic_vector(7 downto 0); -- receive register
+ signal RRegL : std_logic; -- Byte received
+begin
+ -- RxAv process
+ RxAvProc : process(RRegL,Reset,ReadA)
+ begin
+ if ReadA = '1' or Reset = '1' then
+ RxAv <= '0'; -- Negate RxAv when RReg read
+ elsif Rising_Edge(RRegL) then
+ RxAv <= '1'; -- Assert RxAv when RReg written
+ end if;
+ end process;
+
+ -- Rx Process
+ RxProc : process(Clk,Reset,Enable,RxD,RReg)
+ variable BitPos : INTEGER range 0 to 10; -- Position of the bit in the frame
+ variable SampleCnt : INTEGER range 0 to 3; -- Count from 0 to 3 in each bit
+ begin
+ if Reset = '1' then -- Reset
+ RRegL <= '0';
+ BitPos := 0;
+ elsif Rising_Edge(Clk) then
+ if Enable = '1' then
+ case BitPos is
+ when 0 => -- idle
+ RRegL <= '0';
+ if RxD = '0' then -- Start Bit
+ SampleCnt := 0;
+ BitPos := 1;
+ end if;
+ when 10 => -- Stop Bit
+ BitPos := 0; -- next is idle
+ RRegL <= '1'; -- Indicate byte received
+ DataO <= RReg; -- Store received byte
+ when others =>
+ if (SampleCnt = 1 and BitPos >= 2) then -- Sample RxD on 1
+ RReg(BitPos-2) <= RxD; -- Deserialisation
+ end if;
+ if SampleCnt = 3 then -- Increment BitPos on 3
+ BitPos := BitPos + 1;
+ end if;
+ end case;
+ if SampleCnt = 3 then
+ SampleCnt := 0;
+ else
+ sampleCnt := SampleCnt + 1;
+ end if;
+
+ end if;
+ end if;
+ end process;
+end Behaviour;
diff --git a/docs/j1eforth/fpga/src/Txunit.vhd b/docs/j1eforth/fpga/src/Txunit.vhd
new file mode 100644
index 0000000..bdf5b5d
--- /dev/null
+++ b/docs/j1eforth/fpga/src/Txunit.vhd
@@ -0,0 +1,100 @@
+-------------------------------------------------------------------------------
+-- Title : UART
+-- Project : UART
+-------------------------------------------------------------------------------
+-- File : Txunit.vhd
+-- Author : Philippe CARTON
+-- (philippe.carton2@libertysurf.fr)
+-- Organization:
+-- Created : 15/12/2001
+-- Last update : 8/1/2003
+-- Platform : Foundation 3.1i
+-- Simulators : ModelSim 5.5b
+-- Synthesizers: Xilinx Synthesis
+-- Targets : Xilinx Spartan
+-- Dependency : IEEE std_logic_1164
+-------------------------------------------------------------------------------
+-- Description: Txunit is a parallel to serial unit transmitter.
+-------------------------------------------------------------------------------
+-- Copyright (c) notice
+-- This core adheres to the GNU public license
+--
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Revision Number :
+-- Version :
+-- Date :
+-- Modifier : name <email>
+-- Description :
+--
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity TxUnit is
+ port (
+ Clk : in std_logic; -- Clock signal
+ Reset : in std_logic; -- Reset input
+ Enable : in std_logic; -- Enable input
+ LoadA : in std_logic; -- Asynchronous Load
+ TxD : out std_logic; -- RS-232 data output
+ Busy : out std_logic; -- Tx Busy
+ DataI : in std_logic_vector(7 downto 0)); -- Byte to transmit
+end TxUnit;
+
+architecture Behaviour of TxUnit is
+
+ component synchroniser
+ port (
+ C1 : in std_logic; -- Asynchronous signal
+ C : in std_logic; -- Clock
+ O : out Std_logic);-- Synchronised signal
+ end component;
+
+ signal TBuff : std_logic_vector(7 downto 0); -- transmit buffer
+ signal TReg : std_logic_vector(7 downto 0); -- transmit register
+ signal TBufL : std_logic; -- Buffer loaded
+ signal LoadS : std_logic; -- Synchronised load signal
+
+begin
+ -- Synchronise Load on Clk
+ SyncLoad : Synchroniser port map (LoadA, Clk, LoadS);
+ Busy <= LoadS or TBufL;
+
+ -- Tx process
+ TxProc : process(Clk, Reset, Enable, DataI, TBuff, TReg, TBufL)
+ variable BitPos : INTEGER range 0 to 10; -- Bit position in the frame
+ begin
+ if Reset = '1' then
+ TBufL <= '0';
+ BitPos := 0;
+ TxD <= '1';
+ elsif Rising_Edge(Clk) then
+ if LoadS = '1' then
+ TBuff <= DataI;
+ TBufL <= '1';
+ end if;
+ if Enable = '1' then
+ case BitPos is
+ when 0 => -- idle or stop bit
+ TxD <= '1';
+ if TBufL = '1' then -- start transmit. next is start bit
+ TReg <= TBuff;
+ TBufL <= '0';
+ BitPos := 1;
+ end if;
+ when 1 => -- Start bit
+ TxD <= '0';
+ BitPos := 2;
+ when others =>
+ TxD <= TReg(BitPos-2); -- Serialisation of TReg
+ BitPos := BitPos + 1;
+ end case;
+ if BitPos = 10 then -- bit8. next is stop bit
+ BitPos := 0;
+ end if;
+ end if;
+ end if;
+ end process;
+end Behaviour;
diff --git a/docs/j1eforth/fpga/src/clock.vhd b/docs/j1eforth/fpga/src/clock.vhd
new file mode 100644
index 0000000..31536e7
--- /dev/null
+++ b/docs/j1eforth/fpga/src/clock.vhd
@@ -0,0 +1,78 @@
+library ieee;
+use ieee.std_logic_1164.ALL;
+use ieee.numeric_std.ALL;
+library UNISIM;
+use UNISIM.Vcomponents.ALL;
+
+entity clock is
+ port ( clk_in : in std_logic;
+ clk : out std_logic;
+ clk180 : out std_logic);
+end clock;
+
+architecture BEHAVIORAL of clock is
+
+ signal CLKFB_IN : std_logic;
+ signal CLKFX_BUF : std_logic;
+ signal CLKFX180_BUF : std_logic;
+ signal CLKIN_IBUFG : std_logic;
+ signal CLK2X_BUF : std_logic;
+
+begin
+
+ CLKFX_BUFG_INST : BUFG
+ port map (I=>CLKFX_BUF,
+ O=>clk);
+
+ CLKFX180_BUFG_INST : BUFG
+ port map (I=>CLKFX180_BUF,
+ O=>clk180);
+
+ CLKIN_IBUFG_INST : IBUFG
+ port map (I=>clk_in,
+ O=>CLKIN_IBUFG);
+
+ CLK2X_BUFG_INST : BUFG
+ port map (I=>CLK2X_BUF,
+ O=>CLKFB_IN);
+
+ DCM_SP_INST : DCM_SP
+ generic map(
+ CLK_FEEDBACK => "2X",
+ CLKDV_DIVIDE => 4.0,
+ CLKFX_DIVIDE => 1,
+ CLKFX_MULTIPLY => 2,
+ CLKIN_DIVIDE_BY_2 => FALSE,
+ CLKIN_PERIOD => 31.250,
+ CLKOUT_PHASE_SHIFT => "NONE",
+ DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
+ DFS_FREQUENCY_MODE => "LOW",
+ DLL_FREQUENCY_MODE => "LOW",
+ DUTY_CYCLE_CORRECTION=> TRUE,
+ FACTORY_JF => x"C080",
+ PHASE_SHIFT => 0,
+ STARTUP_WAIT => TRUE)
+ port map (
+ CLKIN => CLKIN_IBUFG,
+ CLKFB => CLKFB_IN,
+ DSSEN => '0',
+ PSCLK => '0',
+ PSEN => '0',
+ PSINCDEC => '0',
+ RST => '0',
+ CLKDV => open,
+ CLKFX => CLKFX_BUF,
+ CLKFX180 => CLKFX180_BUF,
+ CLK2X => CLK2X_BUF,
+ CLK2X180 => open,
+ CLK0 => open,
+ CLK90 => open,
+ CLK180 => open,
+ CLK270 => open,
+ LOCKED => open,
+ PSDONE => open,
+ STATUS => open);
+
+end BEHAVIORAL;
+
+
diff --git a/docs/j1eforth/fpga/src/j1.v b/docs/j1eforth/fpga/src/j1.v
new file mode 100644
index 0000000..db8901a
--- /dev/null
+++ b/docs/j1eforth/fpga/src/j1.v
@@ -0,0 +1,199 @@
+/*
+Copyright (c) 2011
+ James Bowman All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions
+are met:
+1. Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+2. Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+3. Neither the name of James Bowman nor the names of its contributors
+ may be used to endorse or promote products derived from this software
+ without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+SUCH DAMAGE.
+*/
+
+module j1(
+ input sys_clk_i, input sys_rst_i, input [15:0] io_din,
+ output io_rd, output io_wr, output [15:0] io_addr, output [15:0] io_dout);
+
+ reg [15:0] insn;
+ wire [15:0] immediate = { 1'b0, insn[14:0] };
+
+ reg [4:0] dsp; // Data stack pointer
+ reg [4:0] _dsp;
+ reg [15:0] st0; // Return stack pointer
+ reg [15:0] _st0;
+ wire _dstkW; // D stack write
+
+ reg [12:0] pc;
+ reg [12:0] _pc;
+ reg [4:0] rsp;
+ reg [4:0] _rsp;
+ reg _rstkW; // R stack write
+ reg [15:0] _rstkD;
+ wire _ramWE; // RAM write enable
+
+ wire [15:0] pc_plus_1;
+ assign pc_plus_1 = pc + 1;
+
+ // The D and R stacks
+ reg [15:0] dstack[0:31];
+ reg [15:0] rstack[0:31];
+ always @(posedge sys_clk_i)
+ begin
+ if (_dstkW)
+ dstack[_dsp] = st0;
+ if (_rstkW)
+ rstack[_rsp] = _rstkD;
+ end
+ wire [15:0] st1 = dstack[dsp];
+ wire [15:0] rst0 = rstack[rsp];
+
+ // st0sel is the ALU operation. For branch and call the operation
+ // is T, for 0branch it is N. For ALU ops it is loaded from the instruction
+ // field.
+ reg [3:0] st0sel;
+ always @*
+ begin
+ case (insn[14:13])
+ 2'b00: st0sel = 0; // ubranch
+ 2'b10: st0sel = 0; // call
+ 2'b01: st0sel = 1; // 0branch
+ 2'b11: st0sel = insn[11:8]; // ALU
+ default: st0sel = 4'bxxxx;
+ endcase
+ end
+
+
+ // Papilio Pro: main memory to be infered instead of specified explitely.
+ reg [15:0] ram[0:16383]; initial $readmemh("../j1.hex", ram);
+
+ reg [15:0] mem_din;
+ always @(posedge sys_clk_i) begin
+ // $monitor("insn_addr= %h, insn = %h, sp=%h, rp=%h, S=%h %h", pc, insn, dsp, rsp, st1, st0);
+ insn <= ram[_pc];
+ mem_din <= ram[_st0[15:1]];
+ if (_ramWE & (_st0[15:14] ==0))
+ ram[_st0[15:1]] <= st1[15:0];
+ end
+
+
+ // Compute the new value of T.
+ always @*
+ begin
+ if (insn[15])
+ _st0 = immediate;
+ else
+ case (st0sel)
+ 4'b0000: _st0 = st0;
+ 4'b0001: _st0 = st1;
+ 4'b0010: _st0 = st0 + st1;
+ 4'b0011: _st0 = st0 & st1;
+ 4'b0100: _st0 = st0 | st1;
+ 4'b0101: _st0 = st0 ^ st1;
+ 4'b0110: _st0 = ~st0;
+ 4'b0111: _st0 = {16{(st1 == st0)}};
+ 4'b1000: _st0 = {16{($signed(st1) < $signed(st0))}};
+ 4'b1001: _st0 = st1 >> st0[3:0];
+ 4'b1010: _st0 = st0 - 1;
+ 4'b1011: _st0 = rst0;
+ 4'b1100: _st0 = |st0[15:14] ? io_din : mem_din;
+ 4'b1101: _st0 = st1 << st0[3:0];
+ 4'b1110: _st0 = {rsp, 3'b000, dsp};
+ 4'b1111: _st0 = {16{(st1 < st0)}};
+ default: _st0 = 16'hxxxx;
+ endcase
+ end
+
+ wire is_alu = (insn[15:13] == 3'b011);
+ wire is_lit = (insn[15]);
+
+ assign io_rd = (is_alu & (insn[11:8] == 4'hc));
+ assign io_wr = _ramWE;
+ assign io_addr = st0;
+ assign io_dout = st1;
+
+ assign _ramWE = is_alu & insn[5];
+ assign _dstkW = is_lit | (is_alu & insn[7]);
+
+ wire [1:0] dd = insn[1:0]; // D stack delta
+ wire [1:0] rd = insn[3:2]; // R stack delta
+
+ always @*
+ begin
+ if (is_lit) begin // literal
+ _dsp = dsp + 1;
+ _rsp = rsp;
+ _rstkW = 0;
+ _rstkD = _pc;
+ end else if (is_alu) begin
+ _dsp = dsp + {dd[1], dd[1], dd[1], dd};
+ _rsp = rsp + {rd[1], rd[1], rd[1], rd};
+ _rstkW = insn[6];
+ _rstkD = st0;
+ end else begin // jump/call
+ // predicated jump is like DROP
+ if (insn[15:13] == 3'b001) begin
+ _dsp = dsp - 1;
+ end else begin
+ _dsp = dsp;
+ end
+ if (insn[15:13] == 3'b010) begin // call
+ _rsp = rsp + 1;
+ _rstkW = 1;
+ _rstkD = {pc_plus_1[14:0], 1'b0};
+ end else begin
+ _rsp = rsp;
+ _rstkW = 0;
+ _rstkD = _pc;
+ end
+ end
+ end
+
+ always @*
+ begin
+ if (sys_rst_i)
+ _pc = pc;
+ else
+ if ((insn[15:13] == 3'b000) |
+ ((insn[15:13] == 3'b001) & (|st0 == 0)) |
+ (insn[15:13] == 3'b010))
+ _pc = insn[12:0];
+ else if (is_alu & insn[12])
+ _pc = rst0[15:1];
+ else
+ _pc = pc_plus_1;
+ end
+
+ always @(posedge sys_clk_i)
+ begin
+ if (sys_rst_i) begin
+ pc <= 0;
+ dsp <= 0;
+ st0 <= 0;
+ rsp <= 0;
+ end else begin
+ dsp <= _dsp;
+ pc <= _pc;
+ st0 <= _st0;
+ rsp <= _rsp;
+ end
+ end
+
+endmodule // j1
diff --git a/docs/j1eforth/fpga/src/miniuart.vhd b/docs/j1eforth/fpga/src/miniuart.vhd
new file mode 100644
index 0000000..2ee4f3c
--- /dev/null
+++ b/docs/j1eforth/fpga/src/miniuart.vhd
@@ -0,0 +1,146 @@
+-------------------------------------------------------------------------------
+-- Title : MINIUART2 -- this is a modified version without Wishbone interface
+-- Project : MINIUART2
+-------------------------------------------------------------------------------
+-- File : MiniUart.vhd
+-- Author : Philippe CARTON
+-- (philippe.carton2@libertysurf.fr)
+-- Organization:
+-- Created : 15/12/2001
+-- Last update : 8/1/2003
+-- Platform : Foundation 3.1i
+-- Simulators : ModelSim 5.5b
+-- Synthesizers: Xilinx Synthesis
+-- Targets : Xilinx Spartan
+-- Dependency : IEEE std_logic_1164, Rxunit.vhd, Txunit.vhd, utils.vhd
+-------------------------------------------------------------------------------
+-- Description: Uart (Universal Asynchronous Receiver Transmitter) for SoC.
+-- Wishbone compatable.
+-------------------------------------------------------------------------------
+-- Copyright (c) notice
+-- This core adheres to the GNU public license
+--
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Revision Number :
+-- Version :
+-- Date :
+-- Modifier : name <email>
+-- Description :
+--
+-------------------------------------------------------------------------------
+-- Revision History:
+-- 2014-12-19: removed wishbone interface (uh@xlerb.de)
+
+
+library ieee;
+ use ieee.std_logic_1164.all;
+
+entity MINIUART2 is
+ generic(BRDIVISOR: INTEGER range 0 to 65535 := 143); -- Baud rate divisor 143 = 115200 at 66 Mhz
+ port (
+ clk: in STD_LOGIC;
+ rst: in STD_LOGIC;
+ rx: in STD_LOGIC;
+ tx: out STD_LOGIC;
+ io_rd: in STD_LOGIC;
+ io_wr: in STD_LOGIC;
+ io_addr: in STD_LOGIC;
+ io_din: in STD_LOGIC_VECTOR (15 downto 0);
+ io_dout: out STD_LOGIC_VECTOR (15 downto 0));
+end MINIUART2;
+
+-- Architecture for UART for synthesis
+architecture Behaviour of MINIUART2 is
+
+ component Counter
+ generic(COUNT: INTEGER range 0 to 65535); -- Count revolution
+ port (
+ Clk : in std_logic; -- Clock
+ Reset : in std_logic; -- Reset input
+ CE : in std_logic; -- Chip Enable
+ O : out std_logic); -- Output
+ end component;
+
+ component RxUnit
+ port (
+ Clk : in std_logic; -- system clock signal
+ Reset : in std_logic; -- Reset input
+ Enable : in std_logic; -- Enable input
+ ReadA : in Std_logic; -- Async Read Received Byte
+ RxD : in std_logic; -- RS-232 data input
+ RxAv : out std_logic; -- Byte available
+ DataO : out std_logic_vector(7 downto 0)); -- Byte received
+ end component;
+
+ component TxUnit
+ port (
+ Clk : in std_logic; -- Clock signal
+ Reset : in std_logic; -- Reset input
+ Enable : in std_logic; -- Enable input
+ LoadA : in std_logic; -- Asynchronous Load
+ TxD : out std_logic; -- RS-232 data output
+ Busy : out std_logic; -- Tx Busy
+ DataI : in std_logic_vector(7 downto 0)); -- Byte to transmit
+ end component;
+
+ signal RxData : std_logic_vector(7 downto 0); -- Last Byte received
+ signal TxData : std_logic_vector(7 downto 0); -- Last bytes transmitted
+ signal SReg : std_logic_vector(7 downto 0); -- Status register
+ signal EnabRx : std_logic; -- Enable RX unit
+ signal EnabTx : std_logic; -- Enable TX unit
+ signal RxAv : std_logic; -- Data Received
+ signal TxBusy : std_logic; -- Transmiter Busy
+ signal ReadA : std_logic; -- Async Read receive buffer
+ signal LoadA : std_logic; -- Async Load transmit buffer
+ signal Sig0 : std_logic; -- gnd signal
+ signal Sig1 : std_logic; -- vcc signal
+
+
+ begin
+ sig0 <= '0';
+ sig1 <= '1';
+ Uart_Rxrate : Counter -- Baud Rate adjust
+ generic map (COUNT => BRDIVISOR)
+ port map (clk, rst, sig1, EnabRx);
+ Uart_Txrate : Counter -- 4 Divider for Tx
+ generic map (COUNT => 4)
+ port map (clk, rst, EnabRx, EnabTx);
+ Uart_TxUnit : TxUnit port map (clk, rst, EnabTX, LoadA, tx, TxBusy, TxData);
+ Uart_RxUnit : RxUnit port map (clk, rst, EnabRX, ReadA, rx, RxAv, RxData);
+
+ -- status register
+ SReg(0) <= RxAv;
+ SReg(1) <= TxBusy;
+ SReg(7 downto 2) <= (others => '0'); -- the rest is silence
+
+ process (clk, rst, io_addr, io_wr, io_din)
+ begin
+ if Rising_Edge(clk) then
+ if rst='1' then
+ LoadA <= '0';
+ elsif io_wr='1' and io_addr='0' then -- write byte to tx
+ TxData <= io_din(7 downto 0);
+ LoadA <= '1';
+ else
+ LoadA <= '0';
+ end if;
+ end if;
+ end process;
+
+ process (clk, rst, io_addr, io_rd, RxData, TxBusy, RxAv)
+ begin
+ if Rising_Edge(clk) then
+ if rst='1' then
+ ReadA <= '0';
+ elsif io_rd='1' and io_addr='0' then
+ ReadA <= '1';
+ else
+ ReadA <= '0';
+ end if;
+ end if;
+ end process;
+ io_dout(7 downto 0) <= RxData when io_addr='0' else SReg;
+ io_dout(15 downto 8) <= (others => '0');
+
+end Behaviour;
diff --git a/docs/j1eforth/fpga/src/papilio-pro-j1.vhd b/docs/j1eforth/fpga/src/papilio-pro-j1.vhd
new file mode 100644
index 0000000..4680c07
--- /dev/null
+++ b/docs/j1eforth/fpga/src/papilio-pro-j1.vhd
@@ -0,0 +1,117 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+entity papilio_pro_j1 is
+ port (
+ clk_in: in std_logic;
+ rx: in std_logic;
+ tx: out std_logic;
+ wing: out std_logic_vector(15 downto 0));
+end papilio_pro_j1;
+
+architecture Behavioral of papilio_pro_j1 is
+
+ component clock is
+ port (
+ clk_in: in std_logic;
+ clk: out std_logic;
+ clk180: out std_logic);
+ end component;
+
+ component j1 is
+ port (
+ sys_clk_i: in std_logic;
+ sys_rst_i: in std_logic;
+ io_rd: out std_logic;
+ io_wr: out std_logic;
+ io_addr: out std_logic_vector (15 downto 0);
+ io_din: in std_logic_vector (15 downto 0);
+ io_dout: out std_logic_vector (15 downto 0));
+ end component;
+
+ component miniuart2 is
+ port (
+ clk: in STD_LOGIC;
+ rst: in STD_LOGIC;
+ rx: in STD_LOGIC;
+ tx: out STD_LOGIC;
+ io_rd: in STD_LOGIC;
+ io_wr: in STD_LOGIC;
+ io_addr: in STD_LOGIC;
+ io_din: in STD_LOGIC_VECTOR (15 downto 0);
+ io_dout: out STD_LOGIC_VECTOR (15 downto 0));
+ end component;
+
+
+ signal clk: std_logic;
+ signal clk180: std_logic;
+
+ signal rst_counter: integer range 0 to 15 := 15;
+ signal sys_rst: std_logic := '1';
+
+ signal io_rd: std_logic;
+ signal io_wr: std_logic;
+ signal io_addr: std_logic_vector (15 downto 0);
+ signal io_din: std_logic_vector (15 downto 0);
+ signal io_dout: std_logic_vector (15 downto 0);
+
+ signal uart_en: std_logic;
+ signal uart_rd: std_logic;
+ signal uart_wr: std_logic;
+ signal uart_dout: std_logic_vector (15 downto 0);
+begin
+
+ clock_inst: clock
+ port map (
+ clk_in => clk_in,
+ clk => clk,
+ clk180 => clk180);
+
+ j1_inst: j1
+ port map (
+ sys_clk_i => clk,
+ sys_rst_i => sys_rst,
+ io_rd => io_rd,
+ io_wr => io_wr,
+ io_addr => io_addr,
+ io_din => io_din,
+ io_dout => io_dout);
+
+ uart_inst: miniuart2
+ port map(
+ clk => clk180,
+ rst => sys_rst,
+ rx => rx,
+ tx => tx,
+ io_rd => uart_rd,
+ io_wr => uart_wr,
+ io_addr => io_addr(0),
+ io_din => io_dout,
+ io_dout => uart_dout);
+
+ process (clk, rst_counter)
+ begin
+ if rising_edge(clk) and rst_counter>0 then
+ rst_counter <= rst_counter-1;
+ end if;
+ end process;
+ sys_rst <= '1' when rst_counter>0 else '0';
+
+ uart_en <= '1' when io_addr(15 downto 1)="111100000000000" else '0';
+ uart_rd <= io_rd and uart_en;
+ uart_wr <= io_wr and uart_en;
+
+ process (io_addr, uart_dout)
+ begin
+ case io_addr(15 downto 1) is
+ when "111100000000000" =>
+ io_din <= uart_dout;
+ when others =>
+ io_din <= (others=>'0');
+ end case;
+ end process;
+
+ wing <= (others=>'0');
+
+end Behavioral; \ No newline at end of file
diff --git a/docs/j1eforth/fpga/src/papilio-pro.ucf b/docs/j1eforth/fpga/src/papilio-pro.ucf
new file mode 100644
index 0000000..338cd2d
--- /dev/null
+++ b/docs/j1eforth/fpga/src/papilio-pro.ucf
@@ -0,0 +1,143 @@
+# UCF file for the Papilio Pro board
+# Generated by pin_converter, written by Kevin Lindsey
+# https://github.com/thelonious/papilio_pins/tree/development/pin_converter
+
+# Main board wing pin [] to FPGA pin Pxx map
+# -------C------- -------B------- -------A-------
+# [GND] [C00] P114 [GND] [B00] P99 P100 [A15]
+# [2V5] [C01] P115 [2V5] [B01] P97 P98 [A14]
+# [3V3] [C02] P116 [3V3] [B02] P92 P93 [A13]
+# [5V0] [C03] P117 [5V0] [B03] P87 P88 [A12]
+# [C04] P118 [B04] P84 P85 [A11] [5V0]
+# [C05] P119 [B05] P82 P83 [A10] [3V3]
+# [C06] P120 [B06] P80 P81 [A09] [2V5]
+# [C07] P121 [B07] P78 P79 [A08] [GND]
+# [GND] [C08] P123 [GND] [B08] P74 P75 [A07]
+# [2V5] [C09] P124 [2V5] [B09] P95 P67 [A06]
+# [3V3] [C10] P126 [3V3] [B10] P62 P66 [A05]
+# [5V0] [C11] P127 [5V0] [B11] P59 P61 [A04]
+# [C12] P131 [B12] P57 P58 [A03] [5V0]
+# [C13] P132 [B13] P55 P56 [A02] [3V3]
+# [C14] P133 [B14] P50 P51 [A01] [2V5]
+# [C15] P134 [B15] P47 P48 [A00] [GND]
+
+## Prohibit the automatic placement of pins that are connected to VCC or GND for configuration.
+CONFIG PROHIBIT=P144;
+CONFIG PROHIBIT=P69;
+CONFIG PROHIBIT=P60;
+
+NET CLK_IN LOC="P94" | IOSTANDARD=LVTTL | PERIOD=31.25ns; # CLK
+NET RX LOC="P101" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # RX
+NET TX LOC="P105" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # TX
+NET WING(0) LOC="P48" | IOSTANDARD=LVTTL; # A0
+NET WING(1) LOC="P51" | IOSTANDARD=LVTTL; # A1
+NET WING(2) LOC="P56" | IOSTANDARD=LVTTL; # A2
+NET WING(3) LOC="P58" | IOSTANDARD=LVTTL; # A3
+NET WING(4) LOC="P61" | IOSTANDARD=LVTTL; # A4
+NET WING(5) LOC="P66" | IOSTANDARD=LVTTL; # A5
+NET WING(6) LOC="P67" | IOSTANDARD=LVTTL; # A6
+NET WING(7) LOC="P75" | IOSTANDARD=LVTTL; # A7
+NET WING(8) LOC="P79" | IOSTANDARD=LVTTL; # A8
+NET WING(9) LOC="P81" | IOSTANDARD=LVTTL; # A9
+NET WING(10) LOC="P83" | IOSTANDARD=LVTTL; # A10
+NET WING(11) LOC="P85" | IOSTANDARD=LVTTL; # A11
+NET WING(12) LOC="P88" | IOSTANDARD=LVTTL; # A12
+NET WING(13) LOC="P93" | IOSTANDARD=LVTTL; # A13
+NET WING(14) LOC="P98" | IOSTANDARD=LVTTL; # A14
+NET WING(15) LOC="P100" | IOSTANDARD=LVTTL; # A15
+#NET A(0) LOC="P48" | IOSTANDARD=LVTTL; # A0
+#NET A(1) LOC="P51" | IOSTANDARD=LVTTL; # A1
+#NET A(2) LOC="P56" | IOSTANDARD=LVTTL; # A2
+#NET A(3) LOC="P58" | IOSTANDARD=LVTTL; # A3
+#NET A(4) LOC="P61" | IOSTANDARD=LVTTL; # A4
+#NET A(5) LOC="P66" | IOSTANDARD=LVTTL; # A5
+#NET A(6) LOC="P67" | IOSTANDARD=LVTTL; # A6
+#NET A(7) LOC="P75" | IOSTANDARD=LVTTL; # A7
+#NET A(8) LOC="P79" | IOSTANDARD=LVTTL; # A8
+#NET A(9) LOC="P81" | IOSTANDARD=LVTTL; # A9
+#NET A(10) LOC="P83" | IOSTANDARD=LVTTL; # A10
+#NET A(11) LOC="P85" | IOSTANDARD=LVTTL; # A11
+#NET A(12) LOC="P88" | IOSTANDARD=LVTTL; # A12
+#NET A(13) LOC="P93" | IOSTANDARD=LVTTL; # A13
+#NET A(14) LOC="P98" | IOSTANDARD=LVTTL; # A14
+#NET A(15) LOC="P100" | IOSTANDARD=LVTTL; # A15
+#NET B(0) LOC="P99" | IOSTANDARD=LVTTL; # B0
+#NET B(1) LOC="P97" | IOSTANDARD=LVTTL; # B1
+#NET B(2) LOC="P92" | IOSTANDARD=LVTTL; # B2
+#NET B(3) LOC="P87" | IOSTANDARD=LVTTL; # B3
+#NET B(4) LOC="P84" | IOSTANDARD=LVTTL; # B4
+#NET B(5) LOC="P82" | IOSTANDARD=LVTTL; # B5
+#NET B(6) LOC="P80" | IOSTANDARD=LVTTL; # B6
+#NET B(7) LOC="P78" | IOSTANDARD=LVTTL; # B7
+#NET B(8) LOC="P74" | IOSTANDARD=LVTTL; # B8
+#NET B(9) LOC="P95" | IOSTANDARD=LVTTL; # B9
+#NET B(10) LOC="P62" | IOSTANDARD=LVTTL; # B10
+#NET B(11) LOC="P59" | IOSTANDARD=LVTTL; # B11
+#NET B(12) LOC="P57" | IOSTANDARD=LVTTL; # B12
+#NET B(13) LOC="P55" | IOSTANDARD=LVTTL; # B13
+#NET B(14) LOC="P50" | IOSTANDARD=LVTTL; # B14
+#NET B(15) LOC="P47" | IOSTANDARD=LVTTL; # B15
+#NET C(0) LOC="P114" | IOSTANDARD=LVTTL; # C0
+#NET C(1) LOC="P115" | IOSTANDARD=LVTTL; # C1
+#NET C(2) LOC="P116" | IOSTANDARD=LVTTL; # C2
+#NET C(3) LOC="P117" | IOSTANDARD=LVTTL; # C3
+#NET C(4) LOC="P118" | IOSTANDARD=LVTTL; # C4
+#NET C(5) LOC="P119" | IOSTANDARD=LVTTL; # C5
+#NET C(6) LOC="P120" | IOSTANDARD=LVTTL; # C6
+#NET C(7) LOC="P121" | IOSTANDARD=LVTTL; # C7
+#NET C(8) LOC="P123" | IOSTANDARD=LVTTL; # C8
+#NET C(9) LOC="P124" | IOSTANDARD=LVTTL; # C9
+#NET C(10) LOC="P126" | IOSTANDARD=LVTTL; # C10
+#NET C(11) LOC="P127" | IOSTANDARD=LVTTL; # C11
+#NET C(12) LOC="P131" | IOSTANDARD=LVTTL; # C12
+#NET C(13) LOC="P132" | IOSTANDARD=LVTTL; # C13
+#NET C(14) LOC="P133" | IOSTANDARD=LVTTL; # C14
+#NET C(15) LOC="P134" | IOSTANDARD=LVTTL; # C15
+#NET SDRAM_ADDR(0) LOC="P140" | IOSTANDARD=LVTTL; # SDRAM_ADDR0
+#NET SDRAM_ADDR(1) LOC="P139" | IOSTANDARD=LVTTL; # SDRAM_ADDR1
+#NET SDRAM_ADDR(2) LOC="P138" | IOSTANDARD=LVTTL; # SDRAM_ADDR2
+#NET SDRAM_ADDR(3) LOC="P137" | IOSTANDARD=LVTTL; # SDRAM_ADDR3
+#NET SDRAM_ADDR(4) LOC="P46" | IOSTANDARD=LVTTL; # SDRAM_ADDR4
+#NET SDRAM_ADDR(5) LOC="P45" | IOSTANDARD=LVTTL; # SDRAM_ADDR5
+#NET SDRAM_ADDR(6) LOC="P44" | IOSTANDARD=LVTTL; # SDRAM_ADDR6
+#NET SDRAM_ADDR(7) LOC="P43" | IOSTANDARD=LVTTL; # SDRAM_ADDR7
+#NET SDRAM_ADDR(8) LOC="P41" | IOSTANDARD=LVTTL; # SDRAM_ADDR8
+#NET SDRAM_ADDR(9) LOC="P40" | IOSTANDARD=LVTTL; # SDRAM_ADDR9
+#NET SDRAM_ADDR(10) LOC="P141" | IOSTANDARD=LVTTL; # SDRAM_ADDR10
+#NET SDRAM_ADDR(11) LOC="P35" | IOSTANDARD=LVTTL; # SDRAM_ADDR11
+#NET SDRAM_ADDR(12) LOC="P34" | IOSTANDARD=LVTTL; # SDRAM_ADDR12
+#NET SDRAM_DATA(0) LOC="P9" | IOSTANDARD=LVTTL; # SDRAM_DATA0
+#NET SDRAM_DATA(1) LOC="P10" | IOSTANDARD=LVTTL; # SDRAM_DATA1
+#NET SDRAM_DATA(2) LOC="P11" | IOSTANDARD=LVTTL; # SDRAM_DATA2
+#NET SDRAM_DATA(3) LOC="P12" | IOSTANDARD=LVTTL; # SDRAM_DATA3
+#NET SDRAM_DATA(4) LOC="P14" | IOSTANDARD=LVTTL; # SDRAM_DATA4
+#NET SDRAM_DATA(5) LOC="P15" | IOSTANDARD=LVTTL; # SDRAM_DATA5
+#NET SDRAM_DATA(6) LOC="P16" | IOSTANDARD=LVTTL; # SDRAM_DATA6
+#NET SDRAM_DATA(7) LOC="P8" | IOSTANDARD=LVTTL; # SDRAM_DATA7
+#NET SDRAM_DATA(8) LOC="P21" | IOSTANDARD=LVTTL; # SDRAM_DATA8
+#NET SDRAM_DATA(9) LOC="P22" | IOSTANDARD=LVTTL; # SDRAM_DATA9
+#NET SDRAM_DATA(10) LOC="P23" | IOSTANDARD=LVTTL; # SDRAM_DATA10
+#NET SDRAM_DATA(11) LOC="P24" | IOSTANDARD=LVTTL; # SDRAM_DATA11
+#NET SDRAM_DATA(12) LOC="P26" | IOSTANDARD=LVTTL; # SDRAM_DATA12
+#NET SDRAM_DATA(13) LOC="P27" | IOSTANDARD=LVTTL; # SDRAM_DATA13
+#NET SDRAM_DATA(14) LOC="P29" | IOSTANDARD=LVTTL; # SDRAM_DATA14
+#NET SDRAM_DATA(15) LOC="P30" | IOSTANDARD=LVTTL; # SDRAM_DATA15
+#NET SDRAM_DQML LOC="P7" | IOSTANDARD=LVTTL; # SDRAM_DQML
+#NET SDRAM_DQMH LOC="P17" | IOSTANDARD=LVTTL; # SDRAM_DQMH
+#NET SDRAM_BA(0) LOC="P143" | IOSTANDARD=LVTTL; # SDRAM_BA0
+#NET SDRAM_BA(1) LOC="P142" | IOSTANDARD=LVTTL; # SDRAM_BA1
+#NET SDRAM_nWE LOC="P6" | IOSTANDARD=LVTTL; # SDRAM_nWE
+#NET SDRAM_nCAS LOC="P5" | IOSTANDARD=LVTTL; # SDRAM_nCAS
+#NET SDRAM_nRAS LOC="P2" | IOSTANDARD=LVTTL; # SDRAM_nRAS
+#NET SDRAM_CS LOC="P1" | IOSTANDARD=LVTTL; # SDRAM_CS
+#NET SDRAM_CLK LOC="P32" | IOSTANDARD=LVTTL; # SDRAM_CLK
+#NET SDRAM_CKE LOC="P33" | IOSTANDARD=LVTTL; # SDRAM_CKE
+#NET LED1 LOC="P112" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=SLOW; # LED1
+#NET JTAG_TMS LOC="P107" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # JTAG_TMS
+#NET JTAG_TCK LOC="P109" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # JTAG_TCK
+#NET JTAG_TDI LOC="P110" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # JTAG_TDI
+#NET JTAG_TDO LOC="P106" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # JTAG_TDO
+#NET FLASH_CS LOC="P38" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # FLASH_CS
+#NET FLASH_CK LOC="P70" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # FLASH_CK
+#NET FLASH_SI LOC="P64" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # FLASH_SI
+#NET FLASH_SO LOC="P65" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST | PULLUP; # FLASH_SO
diff --git a/docs/j1eforth/fpga/src/utils.vhd b/docs/j1eforth/fpga/src/utils.vhd
new file mode 100644
index 0000000..19eb1f7
--- /dev/null
+++ b/docs/j1eforth/fpga/src/utils.vhd
@@ -0,0 +1,132 @@
+-------------------------------------------------------------------------------
+-- Title : UART
+-- Project : UART
+-------------------------------------------------------------------------------
+-- File : utils.vhd
+-- Author : Philippe CARTON
+-- (philippe.carton2@libertysurf.fr)
+-- Organization:
+-- Created : 15/12/2001
+-- Last update : 8/1/2003
+-- Platform : Foundation 3.1i
+-- Simulators : ModelSim 5.5b
+-- Synthesizers: Xilinx Synthesis
+-- Targets : Xilinx Spartan
+-- Dependency : IEEE std_logic_1164
+-------------------------------------------------------------------------------
+-- Description: VHDL utility file
+-------------------------------------------------------------------------------
+-- Copyright (c) notice
+-- This core adheres to the GNU public license
+--
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Revision Number :
+-- Version :
+-- Date :
+-- Modifier : name <email>
+-- Description :
+--
+------------------------------------------------------------------------------
+
+
+-------------------------------------------------------------------------------
+-- Revision list
+-- Version Author Date Changes
+--
+-- 1.0 Philippe CARTON 19 December 2001 New model
+-- philippe.carton2@libertysurf.fr
+-------------------------------------------------------------------------------
+
+--------------------------------------------------------------------------------
+-- Synchroniser:
+-- Synchronize an input signal (C1) with an input clock (C).
+-- The result is the O signal which is synchronous of C, and persist for
+-- one C clock period.
+--------------------------------------------------------------------------------
+library IEEE,STD;
+use IEEE.std_logic_1164.all;
+
+entity synchroniser is
+ port (
+ C1 : in std_logic;-- Asynchronous signal
+ C : in std_logic;-- Clock
+ O : out std_logic);-- Synchronised signal
+end synchroniser;
+
+architecture Behaviour of synchroniser is
+ signal C1A : std_logic;
+ signal C1S : std_logic;
+ signal R : std_logic;
+begin
+ RiseC1A : process(C1,R)
+ begin
+ if Rising_Edge(C1) then
+ C1A <= '1';
+ end if;
+ if (R = '1') then
+ C1A <= '0';
+ end if;
+ end process;
+
+ SyncP : process(C,R)
+ begin
+ if Rising_Edge(C) then
+ if (C1A = '1') then
+ C1S <= '1';
+ else C1S <= '0';
+ end if;
+ if (C1S = '1') then
+ R <= '1';
+ else R <= '0';
+ end if;
+ end if;
+ if (R = '1') then
+ C1S <= '0';
+ end if;
+ end process;
+ O <= C1S;
+end Behaviour;
+
+-------------------------------------------------------------------------------
+-- Counter
+-- This counter is a parametrizable clock divider.
+-- The count value is the generic parameter Count.
+-- It is CE enabled. (it will count only if CE is high).
+-- When it overflow, it will emit a pulse on O.
+-- It can be reseted to 0.
+-------------------------------------------------------------------------------
+library IEEE,STD;
+use IEEE.std_logic_1164.all;
+
+entity Counter is
+ generic(Count: INTEGER range 0 to 65535); -- Count revolution
+ port (
+ Clk : in std_logic; -- Clock
+ Reset : in std_logic; -- Reset input
+ CE : in std_logic; -- Chip Enable
+ O : out std_logic); -- Output
+end Counter;
+
+architecture Behaviour of Counter is
+begin
+ counter : process(Clk,Reset)
+ variable Cnt : INTEGER range 0 to Count-1;
+ begin
+ if Reset = '1' then
+ Cnt := Count - 1;
+ O <= '0';
+ elsif Rising_Edge(Clk) then
+ if CE = '1' then
+ if Cnt = 0 then
+ O <= '1';
+ Cnt := Count - 1;
+ else
+ O <= '0';
+ Cnt := Cnt - 1;
+ end if;
+ else O <= '0';
+ end if;
+ end if;
+ end process;
+end Behaviour;