aboutsummaryrefslogtreecommitdiff
path: root/j1/verilog/testbench.v
diff options
context:
space:
mode:
Diffstat (limited to 'j1/verilog/testbench.v')
-rw-r--r--j1/verilog/testbench.v30
1 files changed, 0 insertions, 30 deletions
diff --git a/j1/verilog/testbench.v b/j1/verilog/testbench.v
deleted file mode 100644
index 2ec2b5e..0000000
--- a/j1/verilog/testbench.v
+++ /dev/null
@@ -1,30 +0,0 @@
-`timescale 1ns/1ps
-`default_nettype none
-
-module testbench();
-
- reg clk;
- reg resetq;
- integer t;
-
- top #(.FIRMWARE("build/firmware/")) dut(.clk(clk), .resetq(resetq));
-
- initial begin
- clk = 1;
- t = 0;
- resetq = 0;
- #1;
- resetq = 1;
-
- $dumpfile("test.vcd");
- $dumpvars(0, dut);
- end
-
- always #5.0 clk = ~clk;
-
- always @(posedge clk) begin
- t <= t + 1;
- if (t == 300)
- $finish;
- end
-endmodule