aboutsummaryrefslogtreecommitdiff
path: root/docs/j1eforth/fpga/test/miniuart2_tb.vhd
blob: 6049582bc0cadaa9cc6dc6ffb3391e2f89cd5231 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   11:48:15 12/20/2014
-- Design Name:   
-- Module Name:   /mnt/hgfs/Projects/j1eforth/vhdl/test/miniuart2_tb.vhd
-- Project Name:  papilio-pro-forth
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: MINIUART2
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
ENTITY miniuart2_tb IS
END miniuart2_tb;
 
ARCHITECTURE behavior OF miniuart2_tb IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT MINIUART2
    PORT(
         clk : IN  std_logic;
         rst : IN  std_logic;
         rx : IN  std_logic;
         tx : OUT  std_logic;
         io_rd : IN  std_logic;
         io_wr : IN  std_logic;
         io_addr : IN  std_logic;
         io_din : IN  std_logic_vector(15 downto 0);
         io_dout : OUT  std_logic_vector(15 downto 0)
        );
    END COMPONENT;
    

   --Inputs
   signal clk : std_logic := '0';
   signal rst : std_logic := '0';
   signal rx : std_logic := '0';
   signal io_rd : std_logic := '0';
   signal io_wr : std_logic := '0';
   signal io_addr : std_logic := '0';
   signal io_din : std_logic_vector(15 downto 0) := (others => '0');

 	--Outputs
   signal tx : std_logic;
   signal io_dout : std_logic_vector(15 downto 0);

   -- Clock period definitions
   constant clk_period : time := 10 ns; -- 31.25 ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: MINIUART2 PORT MAP (
          clk => clk,
          rst => rst,
          rx => rx,
          tx => tx,
          io_rd => io_rd,
          io_wr => io_wr,
          io_addr => io_addr,
          io_din => io_din,
          io_dout => io_dout
        );

   -- Clock process definitions
   clk_process :process
   begin
		clk <= '0';
		wait for clk_period/2;
		clk <= '1';
		wait for clk_period/2;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 100 ns.
      wait for 100 ns;	

      wait for clk_period*5;
		
		rst <= '1';
		
		wait for clk_period*3;
		
		rst <= '0';
		
      wait for clk_period*3;
		
      -- insert stimulus here 
	   io_din <= X"002A";
       io_addr <= '1';
       io_wr <= '1';
		
		wait for clk_period;
		
		io_addr <= '0';
		io_din <= X"0000";
		io_wr <= '0';
		
      wait;
   end process;

END;