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J1: a small Forth CPU Core for FPGAs
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Mode
Name
Size
-rw-r--r--
common.h
55
log
plain
-rw-r--r--
j1.v
3899
log
plain
-rw-r--r--
stack.v
440
log
plain
-rw-r--r--
testbench.v
434
log
plain
-rw-r--r--
top.v
152
log
plain
-rw-r--r--
uart.v
4295
log
plain
-rw-r--r--
xilinx-top.v
4996
log
plain