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authorDimitri Sokolyuk <demon@dim13.org>2017-08-19 12:15:28 +0200
committerDimitri Sokolyuk <demon@dim13.org>2017-08-19 12:15:28 +0200
commit67d25d837ac55f28a366c0a3b262e439a6e75fc3 (patch)
treedf7715c7724c5935ab87c807f3b8b4ef529315e3 /amforth-6.5/avr8/devices/atmega164a/blocks
parente0d6784e89dba33226c0edb815bb974486fa7c48 (diff)
Add AmForth
Diffstat (limited to 'amforth-6.5/avr8/devices/atmega164a/blocks')
-rw-r--r--amforth-6.5/avr8/devices/atmega164a/blocks/AD_CONVERTER.frt47
-rw-r--r--amforth-6.5/avr8/devices/atmega164a/blocks/ANALOG_COMPARATOR.frt27
-rw-r--r--amforth-6.5/avr8/devices/atmega164a/blocks/BOOT_LOAD.frt21
-rw-r--r--amforth-6.5/avr8/devices/atmega164a/blocks/CPU.frt91
-rw-r--r--amforth-6.5/avr8/devices/atmega164a/blocks/EEPROM.frt17
-rw-r--r--amforth-6.5/avr8/devices/atmega164a/blocks/EXTERNAL_INTERRUPT.frt35
-rw-r--r--amforth-6.5/avr8/devices/atmega164a/blocks/JTAG.frt11
-rw-r--r--amforth-6.5/avr8/devices/atmega164a/blocks/PORTA.frt7
-rw-r--r--amforth-6.5/avr8/devices/atmega164a/blocks/PORTB.frt7
-rw-r--r--amforth-6.5/avr8/devices/atmega164a/blocks/PORTC.frt7
-rw-r--r--amforth-6.5/avr8/devices/atmega164a/blocks/PORTD.frt7
-rw-r--r--amforth-6.5/avr8/devices/atmega164a/blocks/SPI.frt29
-rw-r--r--amforth-6.5/avr8/devices/atmega164a/blocks/TIMER_COUNTER_0.frt42
-rw-r--r--amforth-6.5/avr8/devices/atmega164a/blocks/TIMER_COUNTER_1.frt47
-rw-r--r--amforth-6.5/avr8/devices/atmega164a/blocks/TIMER_COUNTER_2.frt57
-rw-r--r--amforth-6.5/avr8/devices/atmega164a/blocks/TWI.frt34
-rw-r--r--amforth-6.5/avr8/devices/atmega164a/blocks/USART0.frt51
-rw-r--r--amforth-6.5/avr8/devices/atmega164a/blocks/USART1.frt51
-rw-r--r--amforth-6.5/avr8/devices/atmega164a/blocks/WATCHDOG.frt15
19 files changed, 603 insertions, 0 deletions
diff --git a/amforth-6.5/avr8/devices/atmega164a/blocks/AD_CONVERTER.frt b/amforth-6.5/avr8/devices/atmega164a/blocks/AD_CONVERTER.frt
new file mode 100644
index 0000000..12944ca
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega164a/blocks/AD_CONVERTER.frt
@@ -0,0 +1,47 @@
+\ Generated automatically for atmega164a
+\ #require bitnames.frt
+
+\ AD_CONVERTER
+$7c constant ADMUX \ The ADC multiplexer Selection
+ $c0 constant ADMUX_REFS \ Reference Selection Bits
+ 7c $c0 bitmask: ADMUX.REFS \ Reference Selection Bits
+ $20 constant ADMUX_ADLAR \ Left Adjust Result
+ 7c $20 bitmask: ADMUX.ADLAR \ Left Adjust Result
+ $1f constant ADMUX_MUX \ Analog Channel and Gain Select
+ 7c $1f bitmask: ADMUX.MUX \ Analog Channel and Gain Select
+$78 constant ADC \ ADC Data Register Bytes
+$7a constant ADCSRA \ The ADC Control and Status reg
+ $80 constant ADCSRA_ADEN \ ADC Enable
+ 7a $80 bitmask: ADCSRA.ADEN \ ADC Enable
+ $40 constant ADCSRA_ADSC \ ADC Start Conversion
+ 7a $40 bitmask: ADCSRA.ADSC \ ADC Start Conversion
+ $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
+ 7a $20 bitmask: ADCSRA.ADATE \ ADC Auto Trigger Enable
+ $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
+ 7a $10 bitmask: ADCSRA.ADIF \ ADC Interrupt Flag
+ $8 constant ADCSRA_ADIE \ ADC Interrupt Enable
+ 7a $8 bitmask: ADCSRA.ADIE \ ADC Interrupt Enable
+ $7 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
+ 7a $7 bitmask: ADCSRA.ADPS \ ADC Prescaler Select Bits
+$7b constant ADCSRB \ The ADC Control and Status reg
+ $40 constant ADCSRB_ACME \
+ 7b $40 bitmask: ADCSRB.ACME \
+ $7 constant ADCSRB_ADTS \ ADC Auto Trigger Source bits
+ 7b $7 bitmask: ADCSRB.ADTS \ ADC Auto Trigger Source bits
+$7e constant DIDR0 \ Digital Input Disable Register
+ $80 constant DIDR0_ADC7D \
+ 7e $80 bitmask: DIDR0.ADC7D \
+ $40 constant DIDR0_ADC6D \
+ 7e $40 bitmask: DIDR0.ADC6D \
+ $20 constant DIDR0_ADC5D \
+ 7e $20 bitmask: DIDR0.ADC5D \
+ $10 constant DIDR0_ADC4D \
+ 7e $10 bitmask: DIDR0.ADC4D \
+ $8 constant DIDR0_ADC3D \
+ 7e $8 bitmask: DIDR0.ADC3D \
+ $4 constant DIDR0_ADC2D \
+ 7e $4 bitmask: DIDR0.ADC2D \
+ $2 constant DIDR0_ADC1D \
+ 7e $2 bitmask: DIDR0.ADC1D \
+ $1 constant DIDR0_ADC0D \
+ 7e $1 bitmask: DIDR0.ADC0D \
diff --git a/amforth-6.5/avr8/devices/atmega164a/blocks/ANALOG_COMPARATOR.frt b/amforth-6.5/avr8/devices/atmega164a/blocks/ANALOG_COMPARATOR.frt
new file mode 100644
index 0000000..b7caf2f
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega164a/blocks/ANALOG_COMPARATOR.frt
@@ -0,0 +1,27 @@
+\ Generated automatically for atmega164a
+\ #require bitnames.frt
+
+\ ANALOG_COMPARATOR
+$7b constant ADCSRB \ ADC Control and Status Registe
+ $40 constant ADCSRB_ACME \ Analog Comparator Multiplexer
+ 7b $40 bitmask: ADCSRB.ACME \ Analog Comparator Multiplexer
+$50 constant ACSR \ Analog Comparator Control And
+ $80 constant ACSR_ACD \ Analog Comparator Disable
+ 50 $80 bitmask: ACSR.ACD \ Analog Comparator Disable
+ $40 constant ACSR_ACBG \ Analog Comparator Bandgap Sele
+ 50 $40 bitmask: ACSR.ACBG \ Analog Comparator Bandgap Sele
+ $20 constant ACSR_ACO \ Analog Compare Output
+ 50 $20 bitmask: ACSR.ACO \ Analog Compare Output
+ $10 constant ACSR_ACI \ Analog Comparator Interrupt Fl
+ 50 $10 bitmask: ACSR.ACI \ Analog Comparator Interrupt Fl
+ $8 constant ACSR_ACIE \ Analog Comparator Interrupt En
+ 50 $8 bitmask: ACSR.ACIE \ Analog Comparator Interrupt En
+ $4 constant ACSR_ACIC \ Analog Comparator Input Captur
+ 50 $4 bitmask: ACSR.ACIC \ Analog Comparator Input Captur
+ $3 constant ACSR_ACIS \ Analog Comparator Interrupt Mo
+ 50 $3 bitmask: ACSR.ACIS \ Analog Comparator Interrupt Mo
+$7f constant DIDR1 \ Digital Input Disable Register
+ $2 constant DIDR1_AIN1D \ AIN1 Digital Input Disable
+ 7f $2 bitmask: DIDR1.AIN1D \ AIN1 Digital Input Disable
+ $1 constant DIDR1_AIN0D \ AIN0 Digital Input Disable
+ 7f $1 bitmask: DIDR1.AIN0D \ AIN0 Digital Input Disable
diff --git a/amforth-6.5/avr8/devices/atmega164a/blocks/BOOT_LOAD.frt b/amforth-6.5/avr8/devices/atmega164a/blocks/BOOT_LOAD.frt
new file mode 100644
index 0000000..d229c7f
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega164a/blocks/BOOT_LOAD.frt
@@ -0,0 +1,21 @@
+\ Generated automatically for atmega164a
+\ #require bitnames.frt
+
+\ BOOT_LOAD
+$57 constant SPMCSR \ Store Program Memory Control R
+ $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
+ 57 $80 bitmask: SPMCSR.SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
+ 57 $40 bitmask: SPMCSR.RWWSB \ Read While Write Section Busy
+ $20 constant SPMCSR_SIGRD \ Signature Row Read
+ 57 $20 bitmask: SPMCSR.SIGRD \ Signature Row Read
+ $10 constant SPMCSR_RWWSRE \ Read While Write section read
+ 57 $10 bitmask: SPMCSR.RWWSRE \ Read While Write section read
+ $8 constant SPMCSR_BLBSET \ Boot Lock Bit Set
+ 57 $8 bitmask: SPMCSR.BLBSET \ Boot Lock Bit Set
+ $4 constant SPMCSR_PGWRT \ Page Write
+ 57 $4 bitmask: SPMCSR.PGWRT \ Page Write
+ $2 constant SPMCSR_PGERS \ Page Erase
+ 57 $2 bitmask: SPMCSR.PGERS \ Page Erase
+ $1 constant SPMCSR_SPMEN \ Store Program Memory Enable
+ 57 $1 bitmask: SPMCSR.SPMEN \ Store Program Memory Enable
diff --git a/amforth-6.5/avr8/devices/atmega164a/blocks/CPU.frt b/amforth-6.5/avr8/devices/atmega164a/blocks/CPU.frt
new file mode 100644
index 0000000..bbf9d5c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega164a/blocks/CPU.frt
@@ -0,0 +1,91 @@
+\ Generated automatically for atmega164a
+\ #require bitnames.frt
+
+\ CPU
+$5f constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ 5f $80 bitmask: SREG.I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ 5f $40 bitmask: SREG.T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ 5f $20 bitmask: SREG.H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ 5f $10 bitmask: SREG.S \ Sign Bit
+ $8 constant SREG_V \ Two's Complement Overflow Flag
+ 5f $8 bitmask: SREG.V \ Two's Complement Overflow Flag
+ $4 constant SREG_N \ Negative Flag
+ 5f $4 bitmask: SREG.N \ Negative Flag
+ $2 constant SREG_Z \ Zero Flag
+ 5f $2 bitmask: SREG.Z \ Zero Flag
+ $1 constant SREG_C \ Carry Flag
+ 5f $1 bitmask: SREG.C \ Carry Flag
+$5d constant SP \ Stack Pointer
+$55 constant MCUCR \ MCU Control Register
+ $80 constant MCUCR_JTD \ JTAG Interface Disable
+ 55 $80 bitmask: MCUCR.JTD \ JTAG Interface Disable
+ $10 constant MCUCR_PUD \ Pull-up disable
+ 55 $10 bitmask: MCUCR.PUD \ Pull-up disable
+ $2 constant MCUCR_IVSEL \ Interrupt Vector Select
+ 55 $2 bitmask: MCUCR.IVSEL \ Interrupt Vector Select
+ $1 constant MCUCR_IVCE \ Interrupt Vector Change Enable
+ 55 $1 bitmask: MCUCR.IVCE \ Interrupt Vector Change Enable
+$54 constant MCUSR \ MCU Status Register
+ $10 constant MCUSR_JTRF \ JTAG Reset Flag
+ 54 $10 bitmask: MCUSR.JTRF \ JTAG Reset Flag
+ $8 constant MCUSR_WDRF \ Watchdog Reset Flag
+ 54 $8 bitmask: MCUSR.WDRF \ Watchdog Reset Flag
+ $4 constant MCUSR_BORF \ Brown-out Reset Flag
+ 54 $4 bitmask: MCUSR.BORF \ Brown-out Reset Flag
+ $2 constant MCUSR_EXTRF \ External Reset Flag
+ 54 $2 bitmask: MCUSR.EXTRF \ External Reset Flag
+ $1 constant MCUSR_PORF \ Power-on reset flag
+ 54 $1 bitmask: MCUSR.PORF \ Power-on reset flag
+$66 constant OSCCAL \ Oscillator Calibration Value
+$61 constant CLKPR \
+ $80 constant CLKPR_CLKPCE \
+ 61 $80 bitmask: CLKPR.CLKPCE \
+ $f constant CLKPR_CLKPS \
+ 61 $f bitmask: CLKPR.CLKPS \
+$53 constant SMCR \ Sleep Mode Control Register
+ $e constant SMCR_SM \ Sleep Mode Select bits
+ 53 $e bitmask: SMCR.SM \ Sleep Mode Select bits
+ $1 constant SMCR_SE \ Sleep Enable
+ 53 $1 bitmask: SMCR.SE \ Sleep Enable
+$4b constant GPIOR2 \ General Purpose IO Register 2
+ $ff constant GPIOR2_GPIOR \ General Purpose IO Register 2
+ 4b $ff bitmask: GPIOR2.GPIOR \ General Purpose IO Register 2
+$4a constant GPIOR1 \ General Purpose IO Register 1
+ $ff constant GPIOR1_GPIOR \ General Purpose IO Register 1
+ 4a $ff bitmask: GPIOR1.GPIOR \ General Purpose IO Register 1
+$3e constant GPIOR0 \ General Purpose IO Register 0
+ $80 constant GPIOR0_GPIOR07 \ General Purpose IO Register 0
+ 3e $80 bitmask: GPIOR0.GPIOR07 \ General Purpose IO Register 0
+ $40 constant GPIOR0_GPIOR06 \ General Purpose IO Register 0
+ 3e $40 bitmask: GPIOR0.GPIOR06 \ General Purpose IO Register 0
+ $20 constant GPIOR0_GPIOR05 \ General Purpose IO Register 0
+ 3e $20 bitmask: GPIOR0.GPIOR05 \ General Purpose IO Register 0
+ $10 constant GPIOR0_GPIOR04 \ General Purpose IO Register 0
+ 3e $10 bitmask: GPIOR0.GPIOR04 \ General Purpose IO Register 0
+ $8 constant GPIOR0_GPIOR03 \ General Purpose IO Register 0
+ 3e $8 bitmask: GPIOR0.GPIOR03 \ General Purpose IO Register 0
+ $4 constant GPIOR0_GPIOR02 \ General Purpose IO Register 0
+ 3e $4 bitmask: GPIOR0.GPIOR02 \ General Purpose IO Register 0
+ $2 constant GPIOR0_GPIOR01 \ General Purpose IO Register 0
+ 3e $2 bitmask: GPIOR0.GPIOR01 \ General Purpose IO Register 0
+ $1 constant GPIOR0_GPIOR00 \ General Purpose IO Register 0
+ 3e $1 bitmask: GPIOR0.GPIOR00 \ General Purpose IO Register 0
+$64 constant PRR0 \ Power Reduction Register0
+ $80 constant PRR0_PRTWI \ Power Reduction TWI
+ 64 $80 bitmask: PRR0.PRTWI \ Power Reduction TWI
+ $40 constant PRR0_PRTIM2 \ Power Reduction Timer/Counter2
+ 64 $40 bitmask: PRR0.PRTIM2 \ Power Reduction Timer/Counter2
+ $20 constant PRR0_PRTIM0 \ Power Reduction Timer/Counter0
+ 64 $20 bitmask: PRR0.PRTIM0 \ Power Reduction Timer/Counter0
+ $12 constant PRR0_PRUSART \ Power Reduction USARTs
+ 64 $12 bitmask: PRR0.PRUSART \ Power Reduction USARTs
+ $8 constant PRR0_PRTIM1 \ Power Reduction Timer/Counter1
+ 64 $8 bitmask: PRR0.PRTIM1 \ Power Reduction Timer/Counter1
+ $4 constant PRR0_PRSPI \ Power Reduction Serial Periphe
+ 64 $4 bitmask: PRR0.PRSPI \ Power Reduction Serial Periphe
+ $1 constant PRR0_PRADC \ Power Reduction ADC
+ 64 $1 bitmask: PRR0.PRADC \ Power Reduction ADC
diff --git a/amforth-6.5/avr8/devices/atmega164a/blocks/EEPROM.frt b/amforth-6.5/avr8/devices/atmega164a/blocks/EEPROM.frt
new file mode 100644
index 0000000..b18c275
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega164a/blocks/EEPROM.frt
@@ -0,0 +1,17 @@
+\ Generated automatically for atmega164a
+\ #require bitnames.frt
+
+\ EEPROM
+$41 constant EEAR \ EEPROM Address Register Low By
+$40 constant EEDR \ EEPROM Data Register
+$3f constant EECR \ EEPROM Control Register
+ $30 constant EECR_EEPM \ EEPROM Programming Mode Bits
+ 3f $30 bitmask: EECR.EEPM \ EEPROM Programming Mode Bits
+ $8 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
+ 3f $8 bitmask: EECR.EERIE \ EEPROM Ready Interrupt Enable
+ $4 constant EECR_EEMPE \ EEPROM Master Write Enable
+ 3f $4 bitmask: EECR.EEMPE \ EEPROM Master Write Enable
+ $2 constant EECR_EEPE \ EEPROM Write Enable
+ 3f $2 bitmask: EECR.EEPE \ EEPROM Write Enable
+ $1 constant EECR_EERE \ EEPROM Read Enable
+ 3f $1 bitmask: EECR.EERE \ EEPROM Read Enable
diff --git a/amforth-6.5/avr8/devices/atmega164a/blocks/EXTERNAL_INTERRUPT.frt b/amforth-6.5/avr8/devices/atmega164a/blocks/EXTERNAL_INTERRUPT.frt
new file mode 100644
index 0000000..13ed947
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega164a/blocks/EXTERNAL_INTERRUPT.frt
@@ -0,0 +1,35 @@
+\ Generated automatically for atmega164a
+\ #require bitnames.frt
+
+\ EXTERNAL_INTERRUPT
+$69 constant EICRA \ External Interrupt Control Reg
+ $30 constant EICRA_ISC2 \ External Interrupt Sense Contr
+ 69 $30 bitmask: EICRA.ISC2 \ External Interrupt Sense Contr
+ $c constant EICRA_ISC1 \ External Interrupt Sense Contr
+ 69 $c bitmask: EICRA.ISC1 \ External Interrupt Sense Contr
+ $3 constant EICRA_ISC0 \ External Interrupt Sense Contr
+ 69 $3 bitmask: EICRA.ISC0 \ External Interrupt Sense Contr
+$3d constant EIMSK \ External Interrupt Mask Regist
+ $7 constant EIMSK_INT \ External Interrupt Request 2 E
+ 3d $7 bitmask: EIMSK.INT \ External Interrupt Request 2 E
+$3c constant EIFR \ External Interrupt Flag Regist
+ $7 constant EIFR_INTF \ External Interrupt Flags
+ 3c $7 bitmask: EIFR.INTF \ External Interrupt Flags
+$73 constant PCMSK3 \ Pin Change Mask Register 3
+ $ff constant PCMSK3_PCINT \ Pin Change Enable Masks
+ 73 $ff bitmask: PCMSK3.PCINT \ Pin Change Enable Masks
+$6d constant PCMSK2 \ Pin Change Mask Register 2
+ $ff constant PCMSK2_PCINT \ Pin Change Enable Masks
+ 6d $ff bitmask: PCMSK2.PCINT \ Pin Change Enable Masks
+$6c constant PCMSK1 \ Pin Change Mask Register 1
+ $ff constant PCMSK1_PCINT \ Pin Change Enable Masks
+ 6c $ff bitmask: PCMSK1.PCINT \ Pin Change Enable Masks
+$6b constant PCMSK0 \ Pin Change Mask Register 0
+ $ff constant PCMSK0_PCINT \ Pin Change Enable Masks
+ 6b $ff bitmask: PCMSK0.PCINT \ Pin Change Enable Masks
+$3b constant PCIFR \ Pin Change Interrupt Flag Regi
+ $f constant PCIFR_PCIF \ Pin Change Interrupt Flags
+ 3b $f bitmask: PCIFR.PCIF \ Pin Change Interrupt Flags
+$68 constant PCICR \ Pin Change Interrupt Control R
+ $f constant PCICR_PCIE \ Pin Change Interrupt Enables
+ 68 $f bitmask: PCICR.PCIE \ Pin Change Interrupt Enables
diff --git a/amforth-6.5/avr8/devices/atmega164a/blocks/JTAG.frt b/amforth-6.5/avr8/devices/atmega164a/blocks/JTAG.frt
new file mode 100644
index 0000000..cd82742
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega164a/blocks/JTAG.frt
@@ -0,0 +1,11 @@
+\ Generated automatically for atmega164a
+\ #require bitnames.frt
+
+\ JTAG
+$51 constant OCDR \ On-Chip Debug Related Register
+$55 constant MCUCR \ MCU Control Register
+ $80 constant MCUCR_JTD \ JTAG Interface Disable
+ 55 $80 bitmask: MCUCR.JTD \ JTAG Interface Disable
+$54 constant MCUSR \ MCU Status Register
+ $10 constant MCUSR_JTRF \ JTAG Reset Flag
+ 54 $10 bitmask: MCUSR.JTRF \ JTAG Reset Flag
diff --git a/amforth-6.5/avr8/devices/atmega164a/blocks/PORTA.frt b/amforth-6.5/avr8/devices/atmega164a/blocks/PORTA.frt
new file mode 100644
index 0000000..afbaa67
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega164a/blocks/PORTA.frt
@@ -0,0 +1,7 @@
+\ Generated automatically for atmega164a
+\ #require bitnames.frt
+
+\ PORTA
+$22 constant PORTA \ Port A Data Register
+$21 constant DDRA \ Port A Data Direction Register
+$20 constant PINA \ Port A Input Pins
diff --git a/amforth-6.5/avr8/devices/atmega164a/blocks/PORTB.frt b/amforth-6.5/avr8/devices/atmega164a/blocks/PORTB.frt
new file mode 100644
index 0000000..0ec791c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega164a/blocks/PORTB.frt
@@ -0,0 +1,7 @@
+\ Generated automatically for atmega164a
+\ #require bitnames.frt
+
+\ PORTB
+$25 constant PORTB \ Port B Data Register
+$24 constant DDRB \ Port B Data Direction Register
+$23 constant PINB \ Port B Input Pins
diff --git a/amforth-6.5/avr8/devices/atmega164a/blocks/PORTC.frt b/amforth-6.5/avr8/devices/atmega164a/blocks/PORTC.frt
new file mode 100644
index 0000000..9855199
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega164a/blocks/PORTC.frt
@@ -0,0 +1,7 @@
+\ Generated automatically for atmega164a
+\ #require bitnames.frt
+
+\ PORTC
+$28 constant PORTC \ Port C Data Register
+$27 constant DDRC \ Port C Data Direction Register
+$26 constant PINC \ Port C Input Pins
diff --git a/amforth-6.5/avr8/devices/atmega164a/blocks/PORTD.frt b/amforth-6.5/avr8/devices/atmega164a/blocks/PORTD.frt
new file mode 100644
index 0000000..9015b02
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega164a/blocks/PORTD.frt
@@ -0,0 +1,7 @@
+\ Generated automatically for atmega164a
+\ #require bitnames.frt
+
+\ PORTD
+$2b constant PORTD \ Port D Data Register
+$2a constant DDRD \ Port D Data Direction Register
+$29 constant PIND \ Port D Input Pins
diff --git a/amforth-6.5/avr8/devices/atmega164a/blocks/SPI.frt b/amforth-6.5/avr8/devices/atmega164a/blocks/SPI.frt
new file mode 100644
index 0000000..c548ee9
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega164a/blocks/SPI.frt
@@ -0,0 +1,29 @@
+\ Generated automatically for atmega164a
+\ #require bitnames.frt
+
+\ SPI
+$4e constant SPDR0 \ SPI Data Register
+$4d constant SPSR0 \ SPI Status Register
+ $80 constant SPSR0_SPIF0 \ SPI Interrupt Flag
+ 4d $80 bitmask: SPSR0.SPIF0 \ SPI Interrupt Flag
+ $40 constant SPSR0_WCOL0 \ Write Collision Flag
+ 4d $40 bitmask: SPSR0.WCOL0 \ Write Collision Flag
+ $1 constant SPSR0_SPI2X0 \ Double SPI Speed Bit
+ 4d $1 bitmask: SPSR0.SPI2X0 \ Double SPI Speed Bit
+$4c constant SPCR0 \ SPI Control Register
+ $80 constant SPCR0_SPIE0 \ SPI Interrupt Enable
+ 4c $80 bitmask: SPCR0.SPIE0 \ SPI Interrupt Enable
+ $40 constant SPCR0_SPE0 \ SPI Enable
+ 4c $40 bitmask: SPCR0.SPE0 \ SPI Enable
+ $20 constant SPCR0_DORD0 \ Data Order
+ 4c $20 bitmask: SPCR0.DORD0 \ Data Order
+ $10 constant SPCR0_MSTR0 \ Master/Slave Select
+ 4c $10 bitmask: SPCR0.MSTR0 \ Master/Slave Select
+ $8 constant SPCR0_CPOL0 \ Clock polarity
+ 4c $8 bitmask: SPCR0.CPOL0 \ Clock polarity
+ $4 constant SPCR0_CPHA0 \ Clock Phase
+ 4c $4 bitmask: SPCR0.CPHA0 \ Clock Phase
+ $2 constant SPCR0_SPR10 \ SPI Clock Rate Select 1
+ 4c $2 bitmask: SPCR0.SPR10 \ SPI Clock Rate Select 1
+ $1 constant SPCR0_SPR00 \ SPI Clock Rate Select 0
+ 4c $1 bitmask: SPCR0.SPR00 \ SPI Clock Rate Select 0
diff --git a/amforth-6.5/avr8/devices/atmega164a/blocks/TIMER_COUNTER_0.frt b/amforth-6.5/avr8/devices/atmega164a/blocks/TIMER_COUNTER_0.frt
new file mode 100644
index 0000000..c2de345
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega164a/blocks/TIMER_COUNTER_0.frt
@@ -0,0 +1,42 @@
+\ Generated automatically for atmega164a
+\ #require bitnames.frt
+
+\ TIMER_COUNTER_0
+$48 constant OCR0B \ Timer/Counter0 Output Compare
+$47 constant OCR0A \ Timer/Counter0 Output Compare
+$46 constant TCNT0 \ Timer/Counter0
+$45 constant TCCR0B \ Timer/Counter Control Register
+ $80 constant TCCR0B_FOC0A \ Force Output Compare A
+ 45 $80 bitmask: TCCR0B.FOC0A \ Force Output Compare A
+ $40 constant TCCR0B_FOC0B \ Force Output Compare B
+ 45 $40 bitmask: TCCR0B.FOC0B \ Force Output Compare B
+ $8 constant TCCR0B_WGM02 \
+ 45 $8 bitmask: TCCR0B.WGM02 \
+ $7 constant TCCR0B_CS0 \ Clock Select
+ 45 $7 bitmask: TCCR0B.CS0 \ Clock Select
+$44 constant TCCR0A \ Timer/Counter Control Registe
+ $c0 constant TCCR0A_COM0A \ Compare Output Mode, Phase Cor
+ 44 $c0 bitmask: TCCR0A.COM0A \ Compare Output Mode, Phase Cor
+ $30 constant TCCR0A_COM0B \ Compare Output Mode, Fast PWm
+ 44 $30 bitmask: TCCR0A.COM0B \ Compare Output Mode, Fast PWm
+ $3 constant TCCR0A_WGM0 \ Waveform Generation Mode
+ 44 $3 bitmask: TCCR0A.WGM0 \ Waveform Generation Mode
+$6e constant TIMSK0 \ Timer/Counter0 Interrupt Mask
+ $4 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare
+ 6e $4 bitmask: TIMSK0.OCIE0B \ Timer/Counter0 Output Compare
+ $2 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare
+ 6e $2 bitmask: TIMSK0.OCIE0A \ Timer/Counter0 Output Compare
+ $1 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interr
+ 6e $1 bitmask: TIMSK0.TOIE0 \ Timer/Counter0 Overflow Interr
+$35 constant TIFR0 \ Timer/Counter0 Interrupt Flag
+ $4 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare
+ 35 $4 bitmask: TIFR0.OCF0B \ Timer/Counter0 Output Compare
+ $2 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare
+ 35 $2 bitmask: TIFR0.OCF0A \ Timer/Counter0 Output Compare
+ $1 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
+ 35 $1 bitmask: TIFR0.TOV0 \ Timer/Counter0 Overflow Flag
+$43 constant GTCCR \ General Timer/Counter Control
+ $80 constant GTCCR_TSM \ Timer/Counter Synchronization
+ 43 $80 bitmask: GTCCR.TSM \ Timer/Counter Synchronization
+ $1 constant GTCCR_PSRSYNC \ Prescaler Reset Timer/Counter1
+ 43 $1 bitmask: GTCCR.PSRSYNC \ Prescaler Reset Timer/Counter1
diff --git a/amforth-6.5/avr8/devices/atmega164a/blocks/TIMER_COUNTER_1.frt b/amforth-6.5/avr8/devices/atmega164a/blocks/TIMER_COUNTER_1.frt
new file mode 100644
index 0000000..43e5db2
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega164a/blocks/TIMER_COUNTER_1.frt
@@ -0,0 +1,47 @@
+\ Generated automatically for atmega164a
+\ #require bitnames.frt
+
+\ TIMER_COUNTER_1
+$6f constant TIMSK1 \ Timer/Counter1 Interrupt Mask
+ $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture I
+ 6f $20 bitmask: TIMSK1.ICIE1 \ Timer/Counter1 Input Capture I
+ $4 constant TIMSK1_OCIE1B \ Timer/Counter1 Output Compare
+ 6f $4 bitmask: TIMSK1.OCIE1B \ Timer/Counter1 Output Compare
+ $2 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare
+ 6f $2 bitmask: TIMSK1.OCIE1A \ Timer/Counter1 Output Compare
+ $1 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interr
+ 6f $1 bitmask: TIMSK1.TOIE1 \ Timer/Counter1 Overflow Interr
+$36 constant TIFR1 \ Timer/Counter Interrupt Flag r
+ $20 constant TIFR1_ICF1 \ Timer/Counter1 Input Capture F
+ 36 $20 bitmask: TIFR1.ICF1 \ Timer/Counter1 Input Capture F
+ $4 constant TIFR1_OCF1B \ Timer/Counter1 Output Compare
+ 36 $4 bitmask: TIFR1.OCF1B \ Timer/Counter1 Output Compare
+ $2 constant TIFR1_OCF1A \ Timer/Counter1 Output Compare
+ 36 $2 bitmask: TIFR1.OCF1A \ Timer/Counter1 Output Compare
+ $1 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
+ 36 $1 bitmask: TIFR1.TOV1 \ Timer/Counter1 Overflow Flag
+$80 constant TCCR1A \ Timer/Counter1 Control Registe
+ $c0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
+ 80 $c0 bitmask: TCCR1A.COM1A \ Compare Output Mode 1A, bits
+ $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
+ 80 $30 bitmask: TCCR1A.COM1B \ Compare Output Mode 1B, bits
+ $3 constant TCCR1A_WGM1 \ Pulse Width Modulator Select B
+ 80 $3 bitmask: TCCR1A.WGM1 \ Pulse Width Modulator Select B
+$81 constant TCCR1B \ Timer/Counter1 Control Registe
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
+ 81 $80 bitmask: TCCR1B.ICNC1 \ Input Capture 1 Noise Canceler
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ 81 $40 bitmask: TCCR1B.ICES1 \ Input Capture 1 Edge Select
+ $18 constant TCCR1B_WGM1 \ Waveform Generation Mode Bits
+ 81 $18 bitmask: TCCR1B.WGM1 \ Waveform Generation Mode Bits
+ $7 constant TCCR1B_CS1 \ Clock Select1 bits
+ 81 $7 bitmask: TCCR1B.CS1 \ Clock Select1 bits
+$82 constant TCCR1C \ Timer/Counter1 Control Registe
+ $80 constant TCCR1C_FOC1A \ Force Output Compare for Chann
+ 82 $80 bitmask: TCCR1C.FOC1A \ Force Output Compare for Chann
+ $40 constant TCCR1C_FOC1B \ Force Output Compare for Chann
+ 82 $40 bitmask: TCCR1C.FOC1B \ Force Output Compare for Chann
+$84 constant TCNT1 \ Timer/Counter1 Bytes
+$88 constant OCR1A \ Timer/Counter1 Output Compare
+$8a constant OCR1B \ Timer/Counter1 Output Compare
+$86 constant ICR1 \ Timer/Counter1 Input Capture R
diff --git a/amforth-6.5/avr8/devices/atmega164a/blocks/TIMER_COUNTER_2.frt b/amforth-6.5/avr8/devices/atmega164a/blocks/TIMER_COUNTER_2.frt
new file mode 100644
index 0000000..2dd0720
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega164a/blocks/TIMER_COUNTER_2.frt
@@ -0,0 +1,57 @@
+\ Generated automatically for atmega164a
+\ #require bitnames.frt
+
+\ TIMER_COUNTER_2
+$70 constant TIMSK2 \ Timer/Counter Interrupt Mask r
+ $4 constant TIMSK2_OCIE2B \ Timer/Counter2 Output Compare
+ 70 $4 bitmask: TIMSK2.OCIE2B \ Timer/Counter2 Output Compare
+ $2 constant TIMSK2_OCIE2A \ Timer/Counter2 Output Compare
+ 70 $2 bitmask: TIMSK2.OCIE2A \ Timer/Counter2 Output Compare
+ $1 constant TIMSK2_TOIE2 \ Timer/Counter2 Overflow Interr
+ 70 $1 bitmask: TIMSK2.TOIE2 \ Timer/Counter2 Overflow Interr
+$37 constant TIFR2 \ Timer/Counter Interrupt Flag R
+ $4 constant TIFR2_OCF2B \ Output Compare Flag 2B
+ 37 $4 bitmask: TIFR2.OCF2B \ Output Compare Flag 2B
+ $2 constant TIFR2_OCF2A \ Output Compare Flag 2A
+ 37 $2 bitmask: TIFR2.OCF2A \ Output Compare Flag 2A
+ $1 constant TIFR2_TOV2 \ Timer/Counter2 Overflow Flag
+ 37 $1 bitmask: TIFR2.TOV2 \ Timer/Counter2 Overflow Flag
+$b0 constant TCCR2A \ Timer/Counter2 Control Registe
+ $c0 constant TCCR2A_COM2A \ Compare Output Mode bits
+ b0 $c0 bitmask: TCCR2A.COM2A \ Compare Output Mode bits
+ $30 constant TCCR2A_COM2B \ Compare Output Mode bits
+ b0 $30 bitmask: TCCR2A.COM2B \ Compare Output Mode bits
+ $3 constant TCCR2A_WGM2 \ Waveform Genration Mode
+ b0 $3 bitmask: TCCR2A.WGM2 \ Waveform Genration Mode
+$b1 constant TCCR2B \ Timer/Counter2 Control Registe
+ $80 constant TCCR2B_FOC2A \ Force Output Compare A
+ b1 $80 bitmask: TCCR2B.FOC2A \ Force Output Compare A
+ $40 constant TCCR2B_FOC2B \ Force Output Compare B
+ b1 $40 bitmask: TCCR2B.FOC2B \ Force Output Compare B
+ $8 constant TCCR2B_WGM22 \ Waveform Generation Mode
+ b1 $8 bitmask: TCCR2B.WGM22 \ Waveform Generation Mode
+ $7 constant TCCR2B_CS2 \ Clock Select bits
+ b1 $7 bitmask: TCCR2B.CS2 \ Clock Select bits
+$b2 constant TCNT2 \ Timer/Counter2
+$b4 constant OCR2B \ Timer/Counter2 Output Compare
+$b3 constant OCR2A \ Timer/Counter2 Output Compare
+$b6 constant ASSR \ Asynchronous Status Register
+ $40 constant ASSR_EXCLK \ Enable External Clock Input
+ b6 $40 bitmask: ASSR.EXCLK \ Enable External Clock Input
+ $20 constant ASSR_AS2 \ Asynchronous Timer/Counter2
+ b6 $20 bitmask: ASSR.AS2 \ Asynchronous Timer/Counter2
+ $10 constant ASSR_TCN2UB \ Timer/Counter2 Update Busy
+ b6 $10 bitmask: ASSR.TCN2UB \ Timer/Counter2 Update Busy
+ $8 constant ASSR_OCR2AUB \ Output Compare Register2 Updat
+ b6 $8 bitmask: ASSR.OCR2AUB \ Output Compare Register2 Updat
+ $4 constant ASSR_OCR2BUB \ Output Compare Register 2 Upda
+ b6 $4 bitmask: ASSR.OCR2BUB \ Output Compare Register 2 Upda
+ $2 constant ASSR_TCR2AUB \ Timer/Counter Control Register
+ b6 $2 bitmask: ASSR.TCR2AUB \ Timer/Counter Control Register
+ $1 constant ASSR_TCR2BUB \ Timer/Counter Control Register
+ b6 $1 bitmask: ASSR.TCR2BUB \ Timer/Counter Control Register
+$43 constant GTCCR \ General Timer Counter Control
+ $80 constant GTCCR_TSM \ Timer/Counter Synchronization
+ 43 $80 bitmask: GTCCR.TSM \ Timer/Counter Synchronization
+ $2 constant GTCCR_PSRASY \ Prescaler Reset Timer/Counter2
+ 43 $2 bitmask: GTCCR.PSRASY \ Prescaler Reset Timer/Counter2
diff --git a/amforth-6.5/avr8/devices/atmega164a/blocks/TWI.frt b/amforth-6.5/avr8/devices/atmega164a/blocks/TWI.frt
new file mode 100644
index 0000000..d30b667
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega164a/blocks/TWI.frt
@@ -0,0 +1,34 @@
+\ Generated automatically for atmega164a
+\ #require bitnames.frt
+
+\ TWI
+$bd constant TWAMR \ TWI (Slave) Address Mask Regis
+ $fe constant TWAMR_TWAM \
+ bd $fe bitmask: TWAMR.TWAM \
+$b8 constant TWBR \ TWI Bit Rate register
+$bc constant TWCR \ TWI Control Register
+ $80 constant TWCR_TWINT \ TWI Interrupt Flag
+ bc $80 bitmask: TWCR.TWINT \ TWI Interrupt Flag
+ $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
+ bc $40 bitmask: TWCR.TWEA \ TWI Enable Acknowledge Bit
+ $20 constant TWCR_TWSTA \ TWI Start Condition Bit
+ bc $20 bitmask: TWCR.TWSTA \ TWI Start Condition Bit
+ $10 constant TWCR_TWSTO \ TWI Stop Condition Bit
+ bc $10 bitmask: TWCR.TWSTO \ TWI Stop Condition Bit
+ $8 constant TWCR_TWWC \ TWI Write Collition Flag
+ bc $8 bitmask: TWCR.TWWC \ TWI Write Collition Flag
+ $4 constant TWCR_TWEN \ TWI Enable Bit
+ bc $4 bitmask: TWCR.TWEN \ TWI Enable Bit
+ $1 constant TWCR_TWIE \ TWI Interrupt Enable
+ bc $1 bitmask: TWCR.TWIE \ TWI Interrupt Enable
+$b9 constant TWSR \ TWI Status Register
+ $f8 constant TWSR_TWS \ TWI Status
+ b9 $f8 bitmask: TWSR.TWS \ TWI Status
+ $3 constant TWSR_TWPS \ TWI Prescaler
+ b9 $3 bitmask: TWSR.TWPS \ TWI Prescaler
+$bb constant TWDR \ TWI Data register
+$ba constant TWAR \ TWI (Slave) Address register
+ $fe constant TWAR_TWA \ TWI (Slave) Address register B
+ ba $fe bitmask: TWAR.TWA \ TWI (Slave) Address register B
+ $1 constant TWAR_TWGCE \ TWI General Call Recognition E
+ ba $1 bitmask: TWAR.TWGCE \ TWI General Call Recognition E
diff --git a/amforth-6.5/avr8/devices/atmega164a/blocks/USART0.frt b/amforth-6.5/avr8/devices/atmega164a/blocks/USART0.frt
new file mode 100644
index 0000000..ae51362
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega164a/blocks/USART0.frt
@@ -0,0 +1,51 @@
+\ Generated automatically for atmega164a
+\ #require bitnames.frt
+
+\ USART0
+$c6 constant UDR0 \ USART I/O Data Register
+$c0 constant UCSR0A \ USART Control and Status Regis
+ $80 constant UCSR0A_RXC0 \ USART Receive Complete
+ c0 $80 bitmask: UCSR0A.RXC0 \ USART Receive Complete
+ $40 constant UCSR0A_TXC0 \ USART Transmitt Complete
+ c0 $40 bitmask: UCSR0A.TXC0 \ USART Transmitt Complete
+ $20 constant UCSR0A_UDRE0 \ USART Data Register Empty
+ c0 $20 bitmask: UCSR0A.UDRE0 \ USART Data Register Empty
+ $10 constant UCSR0A_FE0 \ Framing Error
+ c0 $10 bitmask: UCSR0A.FE0 \ Framing Error
+ $8 constant UCSR0A_DOR0 \ Data overRun
+ c0 $8 bitmask: UCSR0A.DOR0 \ Data overRun
+ $4 constant UCSR0A_UPE0 \ Parity Error
+ c0 $4 bitmask: UCSR0A.UPE0 \ Parity Error
+ $2 constant UCSR0A_U2X0 \ Double the USART transmission
+ c0 $2 bitmask: UCSR0A.U2X0 \ Double the USART transmission
+ $1 constant UCSR0A_MPCM0 \ Multi-processor Communication
+ c0 $1 bitmask: UCSR0A.MPCM0 \ Multi-processor Communication
+$c1 constant UCSR0B \ USART Control and Status Regis
+ $80 constant UCSR0B_RXCIE0 \ RX Complete Interrupt Enable
+ c1 $80 bitmask: UCSR0B.RXCIE0 \ RX Complete Interrupt Enable
+ $40 constant UCSR0B_TXCIE0 \ TX Complete Interrupt Enable
+ c1 $40 bitmask: UCSR0B.TXCIE0 \ TX Complete Interrupt Enable
+ $20 constant UCSR0B_UDRIE0 \ USART Data register Empty Inte
+ c1 $20 bitmask: UCSR0B.UDRIE0 \ USART Data register Empty Inte
+ $10 constant UCSR0B_RXEN0 \ Receiver Enable
+ c1 $10 bitmask: UCSR0B.RXEN0 \ Receiver Enable
+ $8 constant UCSR0B_TXEN0 \ Transmitter Enable
+ c1 $8 bitmask: UCSR0B.TXEN0 \ Transmitter Enable
+ $4 constant UCSR0B_UCSZ02 \ Character Size
+ c1 $4 bitmask: UCSR0B.UCSZ02 \ Character Size
+ $2 constant UCSR0B_RXB80 \ Receive Data Bit 8
+ c1 $2 bitmask: UCSR0B.RXB80 \ Receive Data Bit 8
+ $1 constant UCSR0B_TXB80 \ Transmit Data Bit 8
+ c1 $1 bitmask: UCSR0B.TXB80 \ Transmit Data Bit 8
+$c2 constant UCSR0C \ USART Control and Status Regis
+ $c0 constant UCSR0C_UMSEL0 \ USART Mode Select
+ c2 $c0 bitmask: UCSR0C.UMSEL0 \ USART Mode Select
+ $30 constant UCSR0C_UPM0 \ Parity Mode Bits
+ c2 $30 bitmask: UCSR0C.UPM0 \ Parity Mode Bits
+ $8 constant UCSR0C_USBS0 \ Stop Bit Select
+ c2 $8 bitmask: UCSR0C.USBS0 \ Stop Bit Select
+ $6 constant UCSR0C_UCSZ0 \ Character Size
+ c2 $6 bitmask: UCSR0C.UCSZ0 \ Character Size
+ $1 constant UCSR0C_UCPOL0 \ Clock Polarity
+ c2 $1 bitmask: UCSR0C.UCPOL0 \ Clock Polarity
+$c4 constant UBRR0 \ USART Baud Rate Register Byte
diff --git a/amforth-6.5/avr8/devices/atmega164a/blocks/USART1.frt b/amforth-6.5/avr8/devices/atmega164a/blocks/USART1.frt
new file mode 100644
index 0000000..6bb4ff9
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega164a/blocks/USART1.frt
@@ -0,0 +1,51 @@
+\ Generated automatically for atmega164a
+\ #require bitnames.frt
+
+\ USART1
+$ce constant UDR1 \ USART I/O Data Register
+$c8 constant UCSR1A \ USART Control and Status Regis
+ $80 constant UCSR1A_RXC1 \ USART Receive Complete
+ c8 $80 bitmask: UCSR1A.RXC1 \ USART Receive Complete
+ $40 constant UCSR1A_TXC1 \ USART Transmitt Complete
+ c8 $40 bitmask: UCSR1A.TXC1 \ USART Transmitt Complete
+ $20 constant UCSR1A_UDRE1 \ USART Data Register Empty
+ c8 $20 bitmask: UCSR1A.UDRE1 \ USART Data Register Empty
+ $10 constant UCSR1A_FE1 \ Framing Error
+ c8 $10 bitmask: UCSR1A.FE1 \ Framing Error
+ $8 constant UCSR1A_DOR1 \ Data overRun
+ c8 $8 bitmask: UCSR1A.DOR1 \ Data overRun
+ $4 constant UCSR1A_UPE1 \ Parity Error
+ c8 $4 bitmask: UCSR1A.UPE1 \ Parity Error
+ $2 constant UCSR1A_U2X1 \ Double the USART transmission
+ c8 $2 bitmask: UCSR1A.U2X1 \ Double the USART transmission
+ $1 constant UCSR1A_MPCM1 \ Multi-processor Communication
+ c8 $1 bitmask: UCSR1A.MPCM1 \ Multi-processor Communication
+$c9 constant UCSR1B \ USART Control and Status Regis
+ $80 constant UCSR1B_RXCIE1 \ RX Complete Interrupt Enable
+ c9 $80 bitmask: UCSR1B.RXCIE1 \ RX Complete Interrupt Enable
+ $40 constant UCSR1B_TXCIE1 \ TX Complete Interrupt Enable
+ c9 $40 bitmask: UCSR1B.TXCIE1 \ TX Complete Interrupt Enable
+ $20 constant UCSR1B_UDRIE1 \ USART Data register Empty Inte
+ c9 $20 bitmask: UCSR1B.UDRIE1 \ USART Data register Empty Inte
+ $10 constant UCSR1B_RXEN1 \ Receiver Enable
+ c9 $10 bitmask: UCSR1B.RXEN1 \ Receiver Enable
+ $8 constant UCSR1B_TXEN1 \ Transmitter Enable
+ c9 $8 bitmask: UCSR1B.TXEN1 \ Transmitter Enable
+ $4 constant UCSR1B_UCSZ12 \ Character Size
+ c9 $4 bitmask: UCSR1B.UCSZ12 \ Character Size
+ $2 constant UCSR1B_RXB81 \ Receive Data Bit 8
+ c9 $2 bitmask: UCSR1B.RXB81 \ Receive Data Bit 8
+ $1 constant UCSR1B_TXB81 \ Transmit Data Bit 8
+ c9 $1 bitmask: UCSR1B.TXB81 \ Transmit Data Bit 8
+$ca constant UCSR1C \ USART Control and Status Regis
+ $c0 constant UCSR1C_UMSEL1 \ USART Mode Select
+ ca $c0 bitmask: UCSR1C.UMSEL1 \ USART Mode Select
+ $30 constant UCSR1C_UPM1 \ Parity Mode Bits
+ ca $30 bitmask: UCSR1C.UPM1 \ Parity Mode Bits
+ $8 constant UCSR1C_USBS1 \ Stop Bit Select
+ ca $8 bitmask: UCSR1C.USBS1 \ Stop Bit Select
+ $6 constant UCSR1C_UCSZ1 \ Character Size
+ ca $6 bitmask: UCSR1C.UCSZ1 \ Character Size
+ $1 constant UCSR1C_UCPOL1 \ Clock Polarity
+ ca $1 bitmask: UCSR1C.UCPOL1 \ Clock Polarity
+$cc constant UBRR1 \ USART Baud Rate Register Byte
diff --git a/amforth-6.5/avr8/devices/atmega164a/blocks/WATCHDOG.frt b/amforth-6.5/avr8/devices/atmega164a/blocks/WATCHDOG.frt
new file mode 100644
index 0000000..3dc985f
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega164a/blocks/WATCHDOG.frt
@@ -0,0 +1,15 @@
+\ Generated automatically for atmega164a
+\ #require bitnames.frt
+
+\ WATCHDOG
+$60 constant WDTCSR \ Watchdog Timer Control Registe
+ $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Fla
+ 60 $80 bitmask: WDTCSR.WDIF \ Watchdog Timeout Interrupt Fla
+ $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Ena
+ 60 $40 bitmask: WDTCSR.WDIE \ Watchdog Timeout Interrupt Ena
+ $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
+ 60 $27 bitmask: WDTCSR.WDP \ Watchdog Timer Prescaler Bits
+ $10 constant WDTCSR_WDCE \ Watchdog Change Enable
+ 60 $10 bitmask: WDTCSR.WDCE \ Watchdog Change Enable
+ $8 constant WDTCSR_WDE \ Watch Dog Enable
+ 60 $8 bitmask: WDTCSR.WDE \ Watch Dog Enable