aboutsummaryrefslogtreecommitdiff
path: root/amforth-6.5/avr8/devices/atmega169
diff options
context:
space:
mode:
authorDimitri Sokolyuk <demon@dim13.org>2017-08-19 12:15:28 +0200
committerDimitri Sokolyuk <demon@dim13.org>2017-08-19 12:15:28 +0200
commit67d25d837ac55f28a366c0a3b262e439a6e75fc3 (patch)
treedf7715c7724c5935ab87c807f3b8b4ef529315e3 /amforth-6.5/avr8/devices/atmega169
parente0d6784e89dba33226c0edb815bb974486fa7c48 (diff)
Add AmForth
Diffstat (limited to 'amforth-6.5/avr8/devices/atmega169')
-rw-r--r--amforth-6.5/avr8/devices/atmega169/atmega169.frt183
-rw-r--r--amforth-6.5/avr8/devices/atmega169/device.asm123
-rw-r--r--amforth-6.5/avr8/devices/atmega169/device.inc1455
-rw-r--r--amforth-6.5/avr8/devices/atmega169/device.py137
4 files changed, 1898 insertions, 0 deletions
diff --git a/amforth-6.5/avr8/devices/atmega169/atmega169.frt b/amforth-6.5/avr8/devices/atmega169/atmega169.frt
new file mode 100644
index 0000000..97e7d87
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega169/atmega169.frt
@@ -0,0 +1,183 @@
+\ Partname: ATmega169
+\ Built using part description XML file version 300
+\ generated automatically
+
+hex
+
+\ AD_CONVERTER
+79 constant ADCH \ ADC Data Register High Byte
+78 constant ADCL \ ADC Data Register Low Byte
+7A constant ADCSRA \ The ADC Control and Status register
+7B constant ADCSRB \ ADC Control and Status Register B
+7C constant ADMUX \ The ADC multiplexer Selection Register
+7E constant DIDR0 \ Digital Input Disable Register 0
+
+\ ANALOG_COMPARATOR
+50 constant ACSR \ Analog Comparator Control And Status Register
+7F constant DIDR1 \ Digital Input Disable Register 1
+
+\ BOOT_LOAD
+57 constant SPMCSR \ Store Program Memory Control Register
+
+\ CPU
+61 constant CLKPR \ Clock Prescale Register
+3E constant GPIOR0 \ General Purpose IO Register 0
+4A constant GPIOR1 \ General Purpose IO Register 1
+4B constant GPIOR2 \ General Purpose IO Register 2
+55 constant MCUCR \ MCU Control Register
+54 constant MCUSR \ MCU Status Register
+66 constant OSCCAL \ Oscillator Calibration Value
+64 constant PRR \ Power Reduction Register
+53 constant SMCR \ Sleep Mode Control Register
+5E constant SPH \ Stack Pointer High
+5D constant SPL \ Stack Pointer Low
+5F constant SREG \ Status Register
+
+\ EEPROM
+42 constant EEARH \ EEPROM Address Register High Byte
+41 constant EEARL \ EEPROM Address Register Low Byte
+3F constant EECR \ EEPROM Control Register
+40 constant EEDR \ EEPROM Data Register
+
+\ EXTERNAL_INTERRUPT
+69 constant EICRA \ External Interrupt Control Register
+3C constant EIFR \ External Interrupt Flag Register
+3D constant EIMSK \ External Interrupt Mask Register
+6B constant PCMSK0 \ Pin Change Mask Register 0
+6C constant PCMSK1 \ Pin Change Mask Register 1
+
+\ JTAG
+51 constant OCDR \ On-Chip Debug Related Register in I/O Memory
+
+\ LCD
+E7 constant LCDCCR \ LCD Contrast Control Register
+E4 constant LCDCRA \ LCD Control Register A
+E5 constant LCDCRB \ LCD Control and Status Register B
+EC constant LCDDR0 \ LCD Data Register 0
+ED constant LCDDR1 \ LCD Data Register 1
+F6 constant LCDDR10 \ LCD Data Register 10
+F7 constant LCDDR11 \ LCD Data Register 11
+F8 constant LCDDR12 \ LCD Data Register 12
+F9 constant LCDDR13 \ LCD Data Register 13
+FB constant LCDDR15 \ LCD Data Register 15
+FC constant LCDDR16 \ LCD Data Register 16
+FD constant LCDDR17 \ LCD Data Register 17
+FE constant LCDDR18 \ LCD Data Register 18
+EE constant LCDDR2 \ LCD Data Register 2
+EF constant LCDDR3 \ LCD Data Register 3
+F1 constant LCDDR5 \ LCD Data Register 5
+F2 constant LCDDR6 \ LCD Data Register 6
+F3 constant LCDDR7 \ LCD Data Register 7
+F4 constant LCDDR8 \ LCD Data Register 8
+E6 constant LCDFRR \ LCD Frame Rate Register
+
+\ PORTA
+21 constant DDRA \ Port A Data Direction Register
+20 constant PINA \ Port A Input Pins
+22 constant PORTA \ Port A Data Register
+
+\ PORTB
+24 constant DDRB \ Port B Data Direction Register
+23 constant PINB \ Port B Input Pins
+25 constant PORTB \ Port B Data Register
+
+\ PORTC
+27 constant DDRC \ Port C Data Direction Register
+26 constant PINC \ Port C Input Pins
+28 constant PORTC \ Port C Data Register
+
+\ PORTD
+2A constant DDRD \ Port D Data Direction Register
+29 constant PIND \ Port D Input Pins
+2B constant PORTD \ Port D Data Register
+
+\ PORTE
+2D constant DDRE \ Data Direction Register, Port E
+2C constant PINE \ Input Pins, Port E
+2E constant PORTE \ Data Register, Port E
+
+\ PORTF
+30 constant DDRF \ Data Direction Register, Port F
+2F constant PINF \ Input Pins, Port F
+31 constant PORTF \ Data Register, Port F
+
+\ PORTG
+33 constant DDRG \ Port G Data Direction Register
+32 constant PING \ Port G Input Pins
+34 constant PORTG \ Port G Data Register
+
+\ SPI
+4C constant SPCR \ SPI Control Register
+4E constant SPDR \ SPI Data Register
+4D constant SPSR \ SPI Status Register
+
+\ TIMER_COUNTER_0
+43 constant GTCCR \ General Timer/Control Register
+47 constant OCR0A \ Timer/Counter0 Output Compare Register
+44 constant TCCR0A \ Timer/Counter0 Control Register
+46 constant TCNT0 \ Timer/Counter0
+35 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
+6E constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
+
+\ TIMER_COUNTER_1
+87 constant ICR1H \ Timer/Counter1 Input Capture Register High Byte
+86 constant ICR1L \ Timer/Counter1 Input Capture Register Low Byte
+89 constant OCR1AH \ Timer/Counter1 Output Compare Register A High Byte
+88 constant OCR1AL \ Timer/Counter1 Output Compare Register A Low Byte
+8B constant OCR1BH \ Timer/Counter1 Output Compare Register B High Byte
+8A constant OCR1BL \ Timer/Counter1 Output Compare Register B Low Byte
+80 constant TCCR1A \ Timer/Counter1 Control Register A
+81 constant TCCR1B \ Timer/Counter1 Control Register B
+82 constant TCCR1C \ Timer/Counter 1 Control Register C
+85 constant TCNT1H \ Timer/Counter1 High Byte
+84 constant TCNT1L \ Timer/Counter1 Low Byte
+36 constant TIFR1 \ Timer/Counter1 Interrupt Flag register
+6F constant TIMSK1 \ Timer/Counter1 Interrupt Mask Register
+
+\ TIMER_COUNTER_2
+B6 constant ASSR \ Asynchronous Status Register
+B3 constant OCR2A \ Timer/Counter2 Output Compare Register
+B0 constant TCCR2A \ Timer/Counter2 Control Register
+B2 constant TCNT2 \ Timer/Counter2
+37 constant TIFR2 \ Timer/Counter2 Interrupt Flag Register
+70 constant TIMSK2 \ Timer/Counter2 Interrupt Mask register
+
+\ USART0
+C5 constant UBRR0H \ USART Baud Rate Register High Byte
+C4 constant UBRR0L \ USART Baud Rate Register Low Byte
+C0 constant UCSR0A \ USART Control and Status Register A
+C1 constant UCSR0B \ USART Control and Status Register B
+C2 constant UCSR0C \ USART Control and Status Register C
+C6 constant UDR0 \ USART I/O Data Register
+
+\ USI
+B8 constant USICR \ USI Control Register
+BA constant USIDR \ USI Data Register
+B9 constant USISR \ USI Status Register
+
+\ WATCHDOG
+60 constant WDTCR \ Watchdog Timer Control Register
+
+\ Interrupts
+002 constant INT0Addr \ External Interrupt Request 0
+004 constant PCINT0Addr \ Pin Change Interrupt Request 0
+006 constant PCINT1Addr \ Pin Change Interrupt Request 1
+008 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
+00A constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
+00C constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+00E constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
+010 constant TIMER1_COMPBAddr \ Timer/Counter Compare Match B
+012 constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
+014 constant TIMER0_COMPAddr \ Timer/Counter0 Compare Match
+016 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
+018 constant SPI_STCAddr \ SPI Serial Transfer Complete
+01A constant USART0_RXAddr \ USART0, Rx Complete
+01C constant USART0_UDREAddr \ USART0 Data register Empty
+01E constant USART0_TXAddr \ USART0, Tx Complete
+020 constant USI_STARTAddr \ USI Start Condition
+022 constant USI_OVERFLOWAddr \ USI Overflow
+024 constant ANALOG_COMPAddr \ Analog Comparator
+026 constant ADCAddr \ ADC Conversion Complete
+028 constant EE_READYAddr \ EEPROM Ready
+02A constant SPM_READYAddr \ Store Program Memory Read
+02C constant LCDAddr \ LCD Start of Frame
diff --git a/amforth-6.5/avr8/devices/atmega169/device.asm b/amforth-6.5/avr8/devices/atmega169/device.asm
new file mode 100644
index 0000000..e80445b
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega169/device.asm
@@ -0,0 +1,123 @@
+; Partname: ATmega169
+; Built using part description XML file version 300
+; generated automatically, do not edit
+
+.nolist
+ .include "m169def.inc"
+.list
+
+.equ ramstart = $100
+.equ CELLSIZE = 2
+.macro readflashcell
+ lsl zl
+ rol zh
+ lpm @0, Z+
+ lpm @1, Z+
+.endmacro
+.macro writeflashcell
+ lsl zl
+ rol zh
+.endmacro
+
+; the following definitions are shortcuts for the respective forth source segments if set to 1
+.set WANT_AD_CONVERTER = 0
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_BOOT_LOAD = 0
+.set WANT_CPU = 0
+.set WANT_EEPROM = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_JTAG = 0
+.set WANT_LCD = 0
+.set WANT_PORTA = 0
+.set WANT_PORTB = 0
+.set WANT_PORTC = 0
+.set WANT_PORTD = 0
+.set WANT_PORTE = 0
+.set WANT_PORTF = 0
+.set WANT_PORTG = 0
+.set WANT_SPI = 0
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_TIMER_COUNTER_2 = 0
+.set WANT_USART0 = 0
+.set WANT_USI = 0
+.set WANT_WATCHDOG = 0
+
+
+.ifndef SPMEN
+ .equ SPMEN = SELFPRGEN
+.endif
+
+.ifndef SPMCSR
+ .equ SPMCSR = SPMCR
+.endif
+
+.ifndef EEPE
+ .equ EEPE = EEWE
+.endif
+
+.ifndef EEMPE
+ .equ EEMPE = EEMWE
+.endif
+.equ intvecsize = 2 ; please verify; flash size: 16384 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.equ INTVECTORS = 23
+.org $002
+ rcall isr ; External Interrupt Request 0
+.org $004
+ rcall isr ; Pin Change Interrupt Request 0
+.org $006
+ rcall isr ; Pin Change Interrupt Request 1
+.org $008
+ rcall isr ; Timer/Counter2 Compare Match
+.org $00A
+ rcall isr ; Timer/Counter2 Overflow
+.org $00C
+ rcall isr ; Timer/Counter1 Capture Event
+.org $00E
+ rcall isr ; Timer/Counter1 Compare Match A
+.org $010
+ rcall isr ; Timer/Counter Compare Match B
+.org $012
+ rcall isr ; Timer/Counter1 Overflow
+.org $014
+ rcall isr ; Timer/Counter0 Compare Match
+.org $016
+ rcall isr ; Timer/Counter0 Overflow
+.org $018
+ rcall isr ; SPI Serial Transfer Complete
+.org $01A
+ rcall isr ; USART0, Rx Complete
+.org $01C
+ rcall isr ; USART0 Data register Empty
+.org $01E
+ rcall isr ; USART0, Tx Complete
+.org $020
+ rcall isr ; USI Start Condition
+.org $022
+ rcall isr ; USI Overflow
+.org $024
+ rcall isr ; Analog Comparator
+.org $026
+ rcall isr ; ADC Conversion Complete
+.org $028
+ rcall isr ; EEPROM Ready
+.org $02A
+ rcall isr ; Store Program Memory Read
+.org $02C
+ rcall isr ; LCD Start of Frame
+.nooverlap
+mcu_info:
+mcu_ramsize:
+ .dw 1024
+mcu_eepromsize:
+ .dw 512
+mcu_maxdp:
+ .dw 7168 ; minimum of 0x1C00 (from XML) and 0xffff
+mcu_numints:
+ .dw 23
+mcu_name:
+ .dw 9
+ .db "ATmega169",0
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega169/device.inc b/amforth-6.5/avr8/devices/atmega169/device.inc
new file mode 100644
index 0000000..84d4954
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega169/device.inc
@@ -0,0 +1,1455 @@
+; Partname: ATmega169
+; Built using part description XML file version 300
+; generated automatically, no not edit
+
+; ********
+.if WANT_AD_CONVERTER == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register High Byte
+VE_ADCH:
+ .dw $ff04
+ .db "ADCH"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCH
+XT_ADCH:
+ .dw PFA_DOVARIABLE
+PFA_ADCH:
+ .dw $79
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register Low Byte
+VE_ADCL:
+ .dw $ff04
+ .db "ADCL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCL
+XT_ADCL:
+ .dw PFA_DOVARIABLE
+PFA_ADCL:
+ .dw $78
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register
+VE_ADCSRA:
+ .dw $ff06
+ .db "ADCSRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRA
+XT_ADCSRA:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRA:
+ .dw $7A
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Control and Status Register B
+VE_ADCSRB:
+ .dw $ff06
+ .db "ADCSRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRB
+XT_ADCSRB:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRB:
+ .dw $7B
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC multiplexer Selection Register
+VE_ADMUX:
+ .dw $ff05
+ .db "ADMUX",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADMUX
+XT_ADMUX:
+ .dw PFA_DOVARIABLE
+PFA_ADMUX:
+ .dw $7C
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 0
+VE_DIDR0:
+ .dw $ff05
+ .db "DIDR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR0
+XT_DIDR0:
+ .dw PFA_DOVARIABLE
+PFA_DIDR0:
+ .dw $7E
+
+.endif
+
+; ********
+.if WANT_ANALOG_COMPARATOR == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Control And Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw $50
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 1
+VE_DIDR1:
+ .dw $ff05
+ .db "DIDR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR1
+XT_DIDR1:
+ .dw PFA_DOVARIABLE
+PFA_DIDR1:
+ .dw $7F
+
+.endif
+
+; ********
+.if WANT_BOOT_LOAD == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control Register
+VE_SPMCSR:
+ .dw $ff06
+ .db "SPMCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCSR
+XT_SPMCSR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCSR:
+ .dw $57
+
+.endif
+
+; ********
+.if WANT_CPU == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Clock Prescale Register
+VE_CLKPR:
+ .dw $ff05
+ .db "CLKPR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKPR
+XT_CLKPR:
+ .dw PFA_DOVARIABLE
+PFA_CLKPR:
+ .dw $61
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 0
+VE_GPIOR0:
+ .dw $ff06
+ .db "GPIOR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR0
+XT_GPIOR0:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR0:
+ .dw $3E
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 1
+VE_GPIOR1:
+ .dw $ff06
+ .db "GPIOR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR1
+XT_GPIOR1:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR1:
+ .dw $4A
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 2
+VE_GPIOR2:
+ .dw $ff06
+ .db "GPIOR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR2
+XT_GPIOR2:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR2:
+ .dw $4B
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw $55
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Status Register
+VE_MCUSR:
+ .dw $ff05
+ .db "MCUSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUSR
+XT_MCUSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUSR:
+ .dw $54
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Calibration Value
+VE_OSCCAL:
+ .dw $ff06
+ .db "OSCCAL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSCCAL
+XT_OSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_OSCCAL:
+ .dw $66
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register
+VE_PRR:
+ .dw $ff03
+ .db "PRR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR
+XT_PRR:
+ .dw PFA_DOVARIABLE
+PFA_PRR:
+ .dw $64
+; ( -- addr ) System Constant
+; R( -- )
+; Sleep Mode Control Register
+VE_SMCR:
+ .dw $ff04
+ .db "SMCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SMCR
+XT_SMCR:
+ .dw PFA_DOVARIABLE
+PFA_SMCR:
+ .dw $53
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer High
+VE_SPH:
+ .dw $ff03
+ .db "SPH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPH
+XT_SPH:
+ .dw PFA_DOVARIABLE
+PFA_SPH:
+ .dw $5E
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer Low
+VE_SPL:
+ .dw $ff03
+ .db "SPL",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPL
+XT_SPL:
+ .dw PFA_DOVARIABLE
+PFA_SPL:
+ .dw $5D
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw $5F
+
+.endif
+
+; ********
+.if WANT_EEPROM == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Address Register High Byte
+VE_EEARH:
+ .dw $ff05
+ .db "EEARH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEARH
+XT_EEARH:
+ .dw PFA_DOVARIABLE
+PFA_EEARH:
+ .dw $42
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Address Register Low Byte
+VE_EEARL:
+ .dw $ff05
+ .db "EEARL",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEARL
+XT_EEARL:
+ .dw PFA_DOVARIABLE
+PFA_EEARL:
+ .dw $41
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw $3F
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw $40
+
+.endif
+
+; ********
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register
+VE_EICRA:
+ .dw $ff05
+ .db "EICRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRA
+XT_EICRA:
+ .dw PFA_DOVARIABLE
+PFA_EICRA:
+ .dw $69
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Flag Register
+VE_EIFR:
+ .dw $ff04
+ .db "EIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIFR
+XT_EIFR:
+ .dw PFA_DOVARIABLE
+PFA_EIFR:
+ .dw $3C
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Mask Register
+VE_EIMSK:
+ .dw $ff05
+ .db "EIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIMSK
+XT_EIMSK:
+ .dw PFA_DOVARIABLE
+PFA_EIMSK:
+ .dw $3D
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 0
+VE_PCMSK0:
+ .dw $ff06
+ .db "PCMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK0
+XT_PCMSK0:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK0:
+ .dw $6B
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 1
+VE_PCMSK1:
+ .dw $ff06
+ .db "PCMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK1
+XT_PCMSK1:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK1:
+ .dw $6C
+
+.endif
+
+; ********
+.if WANT_JTAG == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; On-Chip Debug Related Register in I/O Memory
+VE_OCDR:
+ .dw $ff04
+ .db "OCDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCDR
+XT_OCDR:
+ .dw PFA_DOVARIABLE
+PFA_OCDR:
+ .dw $51
+
+.endif
+
+; ********
+.if WANT_LCD == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Contrast Control Register
+VE_LCDCCR:
+ .dw $ff06
+ .db "LCDCCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDCCR
+XT_LCDCCR:
+ .dw PFA_DOVARIABLE
+PFA_LCDCCR:
+ .dw $E7
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Control Register A
+VE_LCDCRA:
+ .dw $ff06
+ .db "LCDCRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDCRA
+XT_LCDCRA:
+ .dw PFA_DOVARIABLE
+PFA_LCDCRA:
+ .dw $E4
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Control and Status Register B
+VE_LCDCRB:
+ .dw $ff06
+ .db "LCDCRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDCRB
+XT_LCDCRB:
+ .dw PFA_DOVARIABLE
+PFA_LCDCRB:
+ .dw $E5
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 0
+VE_LCDDR0:
+ .dw $ff06
+ .db "LCDDR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR0
+XT_LCDDR0:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR0:
+ .dw $EC
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 1
+VE_LCDDR1:
+ .dw $ff06
+ .db "LCDDR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR1
+XT_LCDDR1:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR1:
+ .dw $ED
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 10
+VE_LCDDR10:
+ .dw $ff07
+ .db "LCDDR10",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR10
+XT_LCDDR10:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR10:
+ .dw $F6
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 11
+VE_LCDDR11:
+ .dw $ff07
+ .db "LCDDR11",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR11
+XT_LCDDR11:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR11:
+ .dw $F7
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 12
+VE_LCDDR12:
+ .dw $ff07
+ .db "LCDDR12",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR12
+XT_LCDDR12:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR12:
+ .dw $F8
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 13
+VE_LCDDR13:
+ .dw $ff07
+ .db "LCDDR13",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR13
+XT_LCDDR13:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR13:
+ .dw $F9
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 15
+VE_LCDDR15:
+ .dw $ff07
+ .db "LCDDR15",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR15
+XT_LCDDR15:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR15:
+ .dw $FB
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 16
+VE_LCDDR16:
+ .dw $ff07
+ .db "LCDDR16",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR16
+XT_LCDDR16:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR16:
+ .dw $FC
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 17
+VE_LCDDR17:
+ .dw $ff07
+ .db "LCDDR17",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR17
+XT_LCDDR17:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR17:
+ .dw $FD
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 18
+VE_LCDDR18:
+ .dw $ff07
+ .db "LCDDR18",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR18
+XT_LCDDR18:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR18:
+ .dw $FE
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 2
+VE_LCDDR2:
+ .dw $ff06
+ .db "LCDDR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR2
+XT_LCDDR2:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR2:
+ .dw $EE
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 3
+VE_LCDDR3:
+ .dw $ff06
+ .db "LCDDR3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR3
+XT_LCDDR3:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR3:
+ .dw $EF
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 5
+VE_LCDDR5:
+ .dw $ff06
+ .db "LCDDR5"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR5
+XT_LCDDR5:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR5:
+ .dw $F1
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 6
+VE_LCDDR6:
+ .dw $ff06
+ .db "LCDDR6"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR6
+XT_LCDDR6:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR6:
+ .dw $F2
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 7
+VE_LCDDR7:
+ .dw $ff06
+ .db "LCDDR7"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR7
+XT_LCDDR7:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR7:
+ .dw $F3
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Data Register 8
+VE_LCDDR8:
+ .dw $ff06
+ .db "LCDDR8"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDDR8
+XT_LCDDR8:
+ .dw PFA_DOVARIABLE
+PFA_LCDDR8:
+ .dw $F4
+; ( -- addr ) System Constant
+; R( -- )
+; LCD Frame Rate Register
+VE_LCDFRR:
+ .dw $ff06
+ .db "LCDFRR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LCDFRR
+XT_LCDFRR:
+ .dw PFA_DOVARIABLE
+PFA_LCDFRR:
+ .dw $E6
+
+.endif
+
+; ********
+.if WANT_PORTA == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Direction Register
+VE_DDRA:
+ .dw $ff04
+ .db "DDRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRA
+XT_DDRA:
+ .dw PFA_DOVARIABLE
+PFA_DDRA:
+ .dw $21
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Input Pins
+VE_PINA:
+ .dw $ff04
+ .db "PINA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINA
+XT_PINA:
+ .dw PFA_DOVARIABLE
+PFA_PINA:
+ .dw $20
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Register
+VE_PORTA:
+ .dw $ff05
+ .db "PORTA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTA
+XT_PORTA:
+ .dw PFA_DOVARIABLE
+PFA_PORTA:
+ .dw $22
+
+.endif
+
+; ********
+.if WANT_PORTB == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw $24
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw $23
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw $25
+
+.endif
+
+; ********
+.if WANT_PORTC == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Direction Register
+VE_DDRC:
+ .dw $ff04
+ .db "DDRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRC
+XT_DDRC:
+ .dw PFA_DOVARIABLE
+PFA_DDRC:
+ .dw $27
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Input Pins
+VE_PINC:
+ .dw $ff04
+ .db "PINC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINC
+XT_PINC:
+ .dw PFA_DOVARIABLE
+PFA_PINC:
+ .dw $26
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Register
+VE_PORTC:
+ .dw $ff05
+ .db "PORTC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTC
+XT_PORTC:
+ .dw PFA_DOVARIABLE
+PFA_PORTC:
+ .dw $28
+
+.endif
+
+; ********
+.if WANT_PORTD == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw $2A
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw $29
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw $2B
+
+.endif
+
+; ********
+.if WANT_PORTE == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port E
+VE_DDRE:
+ .dw $ff04
+ .db "DDRE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRE
+XT_DDRE:
+ .dw PFA_DOVARIABLE
+PFA_DDRE:
+ .dw $2D
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port E
+VE_PINE:
+ .dw $ff04
+ .db "PINE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINE
+XT_PINE:
+ .dw PFA_DOVARIABLE
+PFA_PINE:
+ .dw $2C
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port E
+VE_PORTE:
+ .dw $ff05
+ .db "PORTE",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTE
+XT_PORTE:
+ .dw PFA_DOVARIABLE
+PFA_PORTE:
+ .dw $2E
+
+.endif
+
+; ********
+.if WANT_PORTF == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port F
+VE_DDRF:
+ .dw $ff04
+ .db "DDRF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRF
+XT_DDRF:
+ .dw PFA_DOVARIABLE
+PFA_DDRF:
+ .dw $30
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port F
+VE_PINF:
+ .dw $ff04
+ .db "PINF"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINF
+XT_PINF:
+ .dw PFA_DOVARIABLE
+PFA_PINF:
+ .dw $2F
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port F
+VE_PORTF:
+ .dw $ff05
+ .db "PORTF",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTF
+XT_PORTF:
+ .dw PFA_DOVARIABLE
+PFA_PORTF:
+ .dw $31
+
+.endif
+
+; ********
+.if WANT_PORTG == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Data Direction Register
+VE_DDRG:
+ .dw $ff04
+ .db "DDRG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRG
+XT_DDRG:
+ .dw PFA_DOVARIABLE
+PFA_DDRG:
+ .dw $33
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Input Pins
+VE_PING:
+ .dw $ff04
+ .db "PING"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PING
+XT_PING:
+ .dw PFA_DOVARIABLE
+PFA_PING:
+ .dw $32
+; ( -- addr ) System Constant
+; R( -- )
+; Port G Data Register
+VE_PORTG:
+ .dw $ff05
+ .db "PORTG",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTG
+XT_PORTG:
+ .dw PFA_DOVARIABLE
+PFA_PORTG:
+ .dw $34
+
+.endif
+
+; ********
+.if WANT_SPI == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR:
+ .dw $ff04
+ .db "SPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR
+XT_SPCR:
+ .dw PFA_DOVARIABLE
+PFA_SPCR:
+ .dw $4C
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR:
+ .dw $ff04
+ .db "SPDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR
+XT_SPDR:
+ .dw PFA_DOVARIABLE
+PFA_SPDR:
+ .dw $4E
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR:
+ .dw $ff04
+ .db "SPSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR
+XT_SPSR:
+ .dw PFA_DOVARIABLE
+PFA_SPSR:
+ .dw $4D
+
+.endif
+
+; ********
+.if WANT_TIMER_COUNTER_0 == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; General Timer/Control Register
+VE_GTCCR:
+ .dw $ff05
+ .db "GTCCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GTCCR
+XT_GTCCR:
+ .dw PFA_DOVARIABLE
+PFA_GTCCR:
+ .dw $43
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0A:
+ .dw $ff05
+ .db "OCR0A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0A
+XT_OCR0A:
+ .dw PFA_DOVARIABLE
+PFA_OCR0A:
+ .dw $47
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Control Register
+VE_TCCR0A:
+ .dw $ff06
+ .db "TCCR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0A
+XT_TCCR0A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0A:
+ .dw $44
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw $46
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Flag register
+VE_TIFR0:
+ .dw $ff05
+ .db "TIFR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR0
+XT_TIFR0:
+ .dw PFA_DOVARIABLE
+PFA_TIFR0:
+ .dw $35
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Mask Register
+VE_TIMSK0:
+ .dw $ff06
+ .db "TIMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK0
+XT_TIMSK0:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK0:
+ .dw $6E
+
+.endif
+
+; ********
+.if WANT_TIMER_COUNTER_1 == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register High Byte
+VE_ICR1H:
+ .dw $ff05
+ .db "ICR1H",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1H
+XT_ICR1H:
+ .dw PFA_DOVARIABLE
+PFA_ICR1H:
+ .dw $87
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Low Byte
+VE_ICR1L:
+ .dw $ff05
+ .db "ICR1L",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1L
+XT_ICR1L:
+ .dw PFA_DOVARIABLE
+PFA_ICR1L:
+ .dw $86
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register A High Byte
+VE_OCR1AH:
+ .dw $ff06
+ .db "OCR1AH"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1AH
+XT_OCR1AH:
+ .dw PFA_DOVARIABLE
+PFA_OCR1AH:
+ .dw $89
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register A Low Byte
+VE_OCR1AL:
+ .dw $ff06
+ .db "OCR1AL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1AL
+XT_OCR1AL:
+ .dw PFA_DOVARIABLE
+PFA_OCR1AL:
+ .dw $88
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register B High Byte
+VE_OCR1BH:
+ .dw $ff06
+ .db "OCR1BH"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1BH
+XT_OCR1BH:
+ .dw PFA_DOVARIABLE
+PFA_OCR1BH:
+ .dw $8B
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register B Low Byte
+VE_OCR1BL:
+ .dw $ff06
+ .db "OCR1BL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1BL
+XT_OCR1BL:
+ .dw PFA_DOVARIABLE
+PFA_OCR1BL:
+ .dw $8A
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw $80
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw $81
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter 1 Control Register C
+VE_TCCR1C:
+ .dw $ff06
+ .db "TCCR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1C
+XT_TCCR1C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1C:
+ .dw $82
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 High Byte
+VE_TCNT1H:
+ .dw $ff06
+ .db "TCNT1H"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1H
+XT_TCNT1H:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1H:
+ .dw $85
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Low Byte
+VE_TCNT1L:
+ .dw $ff06
+ .db "TCNT1L"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1L
+XT_TCNT1L:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1L:
+ .dw $84
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Flag register
+VE_TIFR1:
+ .dw $ff05
+ .db "TIFR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR1
+XT_TIFR1:
+ .dw PFA_DOVARIABLE
+PFA_TIFR1:
+ .dw $36
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Interrupt Mask Register
+VE_TIMSK1:
+ .dw $ff06
+ .db "TIMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK1
+XT_TIMSK1:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK1:
+ .dw $6F
+
+.endif
+
+; ********
+.if WANT_TIMER_COUNTER_2 == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Asynchronous Status Register
+VE_ASSR:
+ .dw $ff04
+ .db "ASSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ASSR
+XT_ASSR:
+ .dw PFA_DOVARIABLE
+PFA_ASSR:
+ .dw $B6
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Output Compare Register
+VE_OCR2A:
+ .dw $ff05
+ .db "OCR2A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR2A
+XT_OCR2A:
+ .dw PFA_DOVARIABLE
+PFA_OCR2A:
+ .dw $B3
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Control Register
+VE_TCCR2A:
+ .dw $ff06
+ .db "TCCR2A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR2A
+XT_TCCR2A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR2A:
+ .dw $B0
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2
+VE_TCNT2:
+ .dw $ff05
+ .db "TCNT2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT2
+XT_TCNT2:
+ .dw PFA_DOVARIABLE
+PFA_TCNT2:
+ .dw $B2
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Interrupt Flag Register
+VE_TIFR2:
+ .dw $ff05
+ .db "TIFR2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR2
+XT_TIFR2:
+ .dw PFA_DOVARIABLE
+PFA_TIFR2:
+ .dw $37
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter2 Interrupt Mask register
+VE_TIMSK2:
+ .dw $ff06
+ .db "TIMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK2
+XT_TIMSK2:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK2:
+ .dw $70
+
+.endif
+
+; ********
+.if WANT_USART0 == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register High Byte
+VE_UBRR0H:
+ .dw $ff06
+ .db "UBRR0H"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR0H
+XT_UBRR0H:
+ .dw PFA_DOVARIABLE
+PFA_UBRR0H:
+ .dw $C5
+; ( -- addr ) System Constant
+; R( -- )
+; USART Baud Rate Register Low Byte
+VE_UBRR0L:
+ .dw $ff06
+ .db "UBRR0L"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UBRR0L
+XT_UBRR0L:
+ .dw PFA_DOVARIABLE
+PFA_UBRR0L:
+ .dw $C4
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register A
+VE_UCSR0A:
+ .dw $ff06
+ .db "UCSR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0A
+XT_UCSR0A:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0A:
+ .dw $C0
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register B
+VE_UCSR0B:
+ .dw $ff06
+ .db "UCSR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0B
+XT_UCSR0B:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0B:
+ .dw $C1
+; ( -- addr ) System Constant
+; R( -- )
+; USART Control and Status Register C
+VE_UCSR0C:
+ .dw $ff06
+ .db "UCSR0C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UCSR0C
+XT_UCSR0C:
+ .dw PFA_DOVARIABLE
+PFA_UCSR0C:
+ .dw $C2
+; ( -- addr ) System Constant
+; R( -- )
+; USART I/O Data Register
+VE_UDR0:
+ .dw $ff04
+ .db "UDR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_UDR0
+XT_UDR0:
+ .dw PFA_DOVARIABLE
+PFA_UDR0:
+ .dw $C6
+
+.endif
+
+; ********
+.if WANT_USI == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; USI Control Register
+VE_USICR:
+ .dw $ff05
+ .db "USICR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USICR
+XT_USICR:
+ .dw PFA_DOVARIABLE
+PFA_USICR:
+ .dw $B8
+; ( -- addr ) System Constant
+; R( -- )
+; USI Data Register
+VE_USIDR:
+ .dw $ff05
+ .db "USIDR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USIDR
+XT_USIDR:
+ .dw PFA_DOVARIABLE
+PFA_USIDR:
+ .dw $BA
+; ( -- addr ) System Constant
+; R( -- )
+; USI Status Register
+VE_USISR:
+ .dw $ff05
+ .db "USISR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_USISR
+XT_USISR:
+ .dw PFA_DOVARIABLE
+PFA_USISR:
+ .dw $B9
+
+.endif
+
+; ********
+.if WANT_WATCHDOG == 1
+; ********
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCR:
+ .dw $ff05
+ .db "WDTCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCR
+XT_WDTCR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCR:
+ .dw $60
+
+.endif
diff --git a/amforth-6.5/avr8/devices/atmega169/device.py b/amforth-6.5/avr8/devices/atmega169/device.py
new file mode 100644
index 0000000..4dc59ba
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega169/device.py
@@ -0,0 +1,137 @@
+# Partname: ATmega169
+# Built using part description XML file version 300
+# generated automatically, do not edit
+MCUREGS = {
+ 'ADCH': '$79',
+ 'ADCL': '$78',
+ 'ADCSRA': '$7A',
+ 'ADCSRB': '$7B',
+ 'ADMUX': '$7C',
+ 'DIDR0': '$7E',
+ 'ACSR': '$50',
+ 'DIDR1': '$7F',
+ 'SPMCSR': '$57',
+ 'CLKPR': '$61',
+ 'GPIOR0': '$3E',
+ 'GPIOR1': '$4A',
+ 'GPIOR2': '$4B',
+ 'MCUCR': '$55',
+ 'MCUSR': '$54',
+ 'OSCCAL': '$66',
+ 'PRR': '$64',
+ 'SMCR': '$53',
+ 'SPH': '$5E',
+ 'SPL': '$5D',
+ 'SREG': '$5F',
+ 'EEARH': '$42',
+ 'EEARL': '$41',
+ 'EECR': '$3F',
+ 'EEDR': '$40',
+ 'EICRA': '$69',
+ 'EIFR': '$3C',
+ 'EIMSK': '$3D',
+ 'PCMSK0': '$6B',
+ 'PCMSK1': '$6C',
+ 'OCDR': '$51',
+ 'LCDCCR': '$E7',
+ 'LCDCRA': '$E4',
+ 'LCDCRB': '$E5',
+ 'LCDDR0': '$EC',
+ 'LCDDR1': '$ED',
+ 'LCDDR10': '$F6',
+ 'LCDDR11': '$F7',
+ 'LCDDR12': '$F8',
+ 'LCDDR13': '$F9',
+ 'LCDDR15': '$FB',
+ 'LCDDR16': '$FC',
+ 'LCDDR17': '$FD',
+ 'LCDDR18': '$FE',
+ 'LCDDR2': '$EE',
+ 'LCDDR3': '$EF',
+ 'LCDDR5': '$F1',
+ 'LCDDR6': '$F2',
+ 'LCDDR7': '$F3',
+ 'LCDDR8': '$F4',
+ 'LCDFRR': '$E6',
+ 'DDRA': '$21',
+ 'PINA': '$20',
+ 'PORTA': '$22',
+ 'DDRB': '$24',
+ 'PINB': '$23',
+ 'PORTB': '$25',
+ 'DDRC': '$27',
+ 'PINC': '$26',
+ 'PORTC': '$28',
+ 'DDRD': '$2A',
+ 'PIND': '$29',
+ 'PORTD': '$2B',
+ 'DDRE': '$2D',
+ 'PINE': '$2C',
+ 'PORTE': '$2E',
+ 'DDRF': '$30',
+ 'PINF': '$2F',
+ 'PORTF': '$31',
+ 'DDRG': '$33',
+ 'PING': '$32',
+ 'PORTG': '$34',
+ 'SPCR': '$4C',
+ 'SPDR': '$4E',
+ 'SPSR': '$4D',
+ 'GTCCR': '$43',
+ 'OCR0A': '$47',
+ 'TCCR0A': '$44',
+ 'TCNT0': '$46',
+ 'TIFR0': '$35',
+ 'TIMSK0': '$6E',
+ 'ICR1H': '$87',
+ 'ICR1L': '$86',
+ 'OCR1AH': '$89',
+ 'OCR1AL': '$88',
+ 'OCR1BH': '$8B',
+ 'OCR1BL': '$8A',
+ 'TCCR1A': '$80',
+ 'TCCR1B': '$81',
+ 'TCCR1C': '$82',
+ 'TCNT1H': '$85',
+ 'TCNT1L': '$84',
+ 'TIFR1': '$36',
+ 'TIMSK1': '$6F',
+ 'ASSR': '$B6',
+ 'OCR2A': '$B3',
+ 'TCCR2A': '$B0',
+ 'TCNT2': '$B2',
+ 'TIFR2': '$37',
+ 'TIMSK2': '$70',
+ 'UBRR0H': '$C5',
+ 'UBRR0L': '$C4',
+ 'UCSR0A': '$C0',
+ 'UCSR0B': '$C1',
+ 'UCSR0C': '$C2',
+ 'UDR0': '$C6',
+ 'USICR': '$B8',
+ 'USIDR': '$BA',
+ 'USISR': '$B9',
+ 'WDTCR': '$60',
+ 'INT0Addr': '$002',
+ 'PCINT0Addr': '$004',
+ 'PCINT1Addr': '$006',
+ 'TIMER2_COMPAddr': '$008',
+ 'TIMER2_OVFAddr': '$00A',
+ 'TIMER1_CAPTAddr': '$00C',
+ 'TIMER1_COMPAAddr': '$00E',
+ 'TIMER1_COMPBAddr': '$010',
+ 'TIMER1_OVFAddr': '$012',
+ 'TIMER0_COMPAddr': '$014',
+ 'TIMER0_OVFAddr': '$016',
+ 'SPI_STCAddr': '$018',
+ 'USART0_RXAddr': '$01A',
+ 'USART0_UDREAddr': '$01C',
+ 'USART0_TXAddr': '$01E',
+ 'USI_STARTAddr': '$020',
+ 'USI_OVERFLOWAddr': '$022',
+ 'ANALOG_COMPAddr': '$024',
+ 'ADCAddr': '$026',
+ 'EE_READYAddr': '$028',
+ 'SPM_READYAddr': '$02A',
+ 'LCDAddr': '$02C'
+} \ No newline at end of file