aboutsummaryrefslogtreecommitdiff
path: root/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/SPI.frt
diff options
context:
space:
mode:
authorDimitri Sokolyuk <demon@dim13.org>2017-08-19 12:15:28 +0200
committerDimitri Sokolyuk <demon@dim13.org>2017-08-19 12:15:28 +0200
commit67d25d837ac55f28a366c0a3b262e439a6e75fc3 (patch)
treedf7715c7724c5935ab87c807f3b8b4ef529315e3 /amforth-6.5/avr8/devices/atmega2564rfr2/blocks/SPI.frt
parente0d6784e89dba33226c0edb815bb974486fa7c48 (diff)
Add AmForth
Diffstat (limited to 'amforth-6.5/avr8/devices/atmega2564rfr2/blocks/SPI.frt')
-rw-r--r--amforth-6.5/avr8/devices/atmega2564rfr2/blocks/SPI.frt29
1 files changed, 29 insertions, 0 deletions
diff --git a/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/SPI.frt b/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/SPI.frt
new file mode 100644
index 0000000..bc4823d
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega2564rfr2/blocks/SPI.frt
@@ -0,0 +1,29 @@
+\ Generated automatically for atmega2564rfr2
+\ #require bitnames.frt
+
+\ SPI
+$4c constant SPCR \ SPI Control Register
+ $80 constant SPCR_SPIE \ SPI Interrupt Enable
+ 4c $80 bitmask: SPCR.SPIE \ SPI Interrupt Enable
+ $40 constant SPCR_SPE \ SPI Enable
+ 4c $40 bitmask: SPCR.SPE \ SPI Enable
+ $20 constant SPCR_DORD \ Data Order
+ 4c $20 bitmask: SPCR.DORD \ Data Order
+ $10 constant SPCR_MSTR \ Master/Slave Select
+ 4c $10 bitmask: SPCR.MSTR \ Master/Slave Select
+ $8 constant SPCR_CPOL \ Clock polarity
+ 4c $8 bitmask: SPCR.CPOL \ Clock polarity
+ $4 constant SPCR_CPHA \ Clock Phase
+ 4c $4 bitmask: SPCR.CPHA \ Clock Phase
+ $3 constant SPCR_SPR \ SPI Clock Rate Select 1 and 0
+ 4c $3 bitmask: SPCR.SPR \ SPI Clock Rate Select 1 and 0
+$4d constant SPSR \ SPI Status Register
+ $80 constant SPSR_SPIF \ SPI Interrupt Flag
+ 4d $80 bitmask: SPSR.SPIF \ SPI Interrupt Flag
+ $40 constant SPSR_WCOL \ Write Collision Flag
+ 4d $40 bitmask: SPSR.WCOL \ Write Collision Flag
+ $3e constant SPSR_Res \ Reserved
+ 4d $3e bitmask: SPSR.Res \ Reserved
+ $1 constant SPSR_SPI2X \ Double SPI Speed Bit
+ 4d $1 bitmask: SPSR.SPI2X \ Double SPI Speed Bit
+$4e constant SPDR \ SPI Data Register