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authorDimitri Sokolyuk <demon@dim13.org>2017-08-19 12:15:28 +0200
committerDimitri Sokolyuk <demon@dim13.org>2017-08-19 12:15:28 +0200
commit67d25d837ac55f28a366c0a3b262e439a6e75fc3 (patch)
treedf7715c7724c5935ab87c807f3b8b4ef529315e3 /amforth-6.5/avr8/devices/atmega32c1
parente0d6784e89dba33226c0edb815bb974486fa7c48 (diff)
Add AmForth
Diffstat (limited to 'amforth-6.5/avr8/devices/atmega32c1')
-rw-r--r--amforth-6.5/avr8/devices/atmega32c1/atmega32c1.frt454
-rw-r--r--amforth-6.5/avr8/devices/atmega32c1/device.asm119
-rw-r--r--amforth-6.5/avr8/devices/atmega32c1/device.inc1503
-rw-r--r--amforth-6.5/avr8/devices/atmega32c1/device.py477
-rw-r--r--amforth-6.5/avr8/devices/atmega32c1/words/no-jtag.asm14
-rw-r--r--amforth-6.5/avr8/devices/atmega32c1/words/no-wdt.asm34
-rw-r--r--amforth-6.5/avr8/devices/atmega32c1/words/sleep.asm19
7 files changed, 2620 insertions, 0 deletions
diff --git a/amforth-6.5/avr8/devices/atmega32c1/atmega32c1.frt b/amforth-6.5/avr8/devices/atmega32c1/atmega32c1.frt
new file mode 100644
index 0000000..118eaba
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega32c1/atmega32c1.frt
@@ -0,0 +1,454 @@
+\ Partname: ATmega32C1
+\ generated automatically
+
+\ PORTB
+&37 constant PORTB \ Port B Data Register
+&36 constant DDRB \ Port B Data Direction Register
+&35 constant PINB \ Port B Input Pins
+\ PORTC
+&40 constant PORTC \ Port C Data Register
+&39 constant DDRC \ Port C Data Direction Register
+&38 constant PINC \ Port C Input Pins
+\ PORTD
+&43 constant PORTD \ Port D Data Register
+&42 constant DDRD \ Port D Data Direction Register
+&41 constant PIND \ Port D Input Pins
+\ CAN
+&216 constant CANGCON \ CAN General Control Register
+ $80 constant CANGCON_ABRQ \ Abort Request
+ $40 constant CANGCON_OVRQ \ Overload Frame Request
+ $20 constant CANGCON_TTC \ Time Trigger Communication
+ $10 constant CANGCON_SYNTTC \ Synchronization of TTC
+ $08 constant CANGCON_LISTEN \ Listening Mode
+ $04 constant CANGCON_TEST \ Test Mode
+ $02 constant CANGCON_ENASTB \ Enable / Standby
+ $01 constant CANGCON_SWRES \ Software Reset Request
+&217 constant CANGSTA \ CAN General Status Register
+ $40 constant CANGSTA_OVFG \ Overload Frame Flag
+ $10 constant CANGSTA_TXBSY \ Transmitter Busy
+ $08 constant CANGSTA_RXBSY \ Receiver Busy
+ $04 constant CANGSTA_ENFG \ Enable Flag
+ $02 constant CANGSTA_BOFF \ Bus Off Mode
+ $01 constant CANGSTA_ERRP \ Error Passive Mode
+&218 constant CANGIT \ CAN General Interrupt Register Flags
+ $80 constant CANGIT_CANIT \ General Interrupt Flag
+ $40 constant CANGIT_BOFFIT \ Bus Off Interrupt Flag
+ $20 constant CANGIT_OVRTIM \ Overrun CAN Timer Flag
+ $10 constant CANGIT_BXOK \ Burst Receive Interrupt Flag
+ $08 constant CANGIT_SERG \ Stuff Error General Flag
+ $04 constant CANGIT_CERG \ CRC Error General Flag
+ $02 constant CANGIT_FERG \ Form Error General Flag
+ $01 constant CANGIT_AERG \ Ackknowledgement Error General Flag
+&219 constant CANGIE \ CAN General Interrupt Enable Register
+ $80 constant CANGIE_ENIT \ Enable all Interrupts
+ $40 constant CANGIE_ENBOFF \ Enable Bus Off Interrupt
+ $20 constant CANGIE_ENRX \ Enable Receive Interrupt
+ $10 constant CANGIE_ENTX \ Enable Transmitt Interrupt
+ $08 constant CANGIE_ENERR \ Enable MOb Error Interrupt
+ $04 constant CANGIE_ENBX \ Enable Burst Receive Interrupt
+ $02 constant CANGIE_ENERG \ Enable General Error Interrupt
+ $01 constant CANGIE_ENOVRT \ Enable CAN Timer Overrun Interrupt
+&220 constant CANEN2 \ Enable MOb Register 2
+ $3F constant CANEN2_ENMOB \ Enable MObs
+&221 constant CANEN1 \ Enable MOb Register 1(empty)
+&222 constant CANIE2 \ Enable Interrupt MOb Register 2
+ $3F constant CANIE2_IEMOB \ Interrupt Enable MObs
+&223 constant CANIE1 \ Enable Interrupt MOb Register 1 (empty)
+&224 constant CANSIT2 \ CAN Status Interrupt MOb Register 2
+ $3F constant CANSIT2_SIT \ Status of Interrupt MObs
+&225 constant CANSIT1 \ CAN Status Interrupt MOb Register 1 (empty)
+&226 constant CANBT1 \ CAN Bit Timing Register 1
+ $7E constant CANBT1_BRP \ Baud Rate Prescaler bits
+&227 constant CANBT2 \ CAN Bit Timing Register 2
+ $60 constant CANBT2_SJW \ Re-Sync Jump Width bits
+ $0E constant CANBT2_PRS \ Propagation Time Segment bits
+&228 constant CANBT3 \ CAN Bit Timing Register 3
+ $70 constant CANBT3_PHS2 \ Phase Segment 2 bits
+ $0E constant CANBT3_PHS1 \ Phase Segment 1 bits
+ $01 constant CANBT3_SMP \ Sample Type
+&229 constant CANTCON \ Timer Control Register
+&230 constant CANTIML \ Timer Register Low
+&231 constant CANTIMH \ Timer Register High
+&232 constant CANTTCL \ TTC Timer Register Low
+&233 constant CANTTCH \ TTC Timer Register High
+&234 constant CANTEC \ Transmit Error Counter Register
+&235 constant CANREC \ Receive Error Counter Register
+&236 constant CANHPMOB \ Highest Priority MOb Register
+ $F0 constant CANHPMOB_HPMOB \ Highest Priority MOb Number bits
+ $0F constant CANHPMOB_CGP \ CAN General Purpose bits
+&237 constant CANPAGE \ Page MOb Register
+ $F0 constant CANPAGE_MOBNB \ MOb Number bits
+ $08 constant CANPAGE_AINC \ MOb Data Buffer Auto Increment (Active Low)
+ $07 constant CANPAGE_INDX \ Data Buffer Index bits
+&238 constant CANSTMOB \ MOb Status Register
+ $80 constant CANSTMOB_DLCW \ Data Length Code Warning on MOb
+ $40 constant CANSTMOB_TXOK \ Transmit OK on MOb
+ $20 constant CANSTMOB_RXOK \ Receive OK on MOb
+ $10 constant CANSTMOB_BERR \ Bit Error on MOb
+ $08 constant CANSTMOB_SERR \ Stuff Error on MOb
+ $04 constant CANSTMOB_CERR \ CRC Error on MOb
+ $02 constant CANSTMOB_FERR \ Form Error on MOb
+ $01 constant CANSTMOB_AERR \ Ackknowledgement Error on MOb
+&239 constant CANCDMOB \ MOb Control and DLC Register
+ $C0 constant CANCDMOB_CONMOB \ MOb Config bits
+ $20 constant CANCDMOB_RPLV \ Reply Valid
+ $10 constant CANCDMOB_IDE \ Identifier Extension
+ $0F constant CANCDMOB_DLC \ Data Length Code bits
+&240 constant CANIDT4 \ Identifier Tag Register 4
+ $F8 constant CANIDT4_IDT \
+ $04 constant CANIDT4_RTRTAG \
+ $02 constant CANIDT4_RB1TAG \
+ $01 constant CANIDT4_RB0TAG \
+&241 constant CANIDT3 \ Identifier Tag Register 3
+&242 constant CANIDT2 \ Identifier Tag Register 2
+&243 constant CANIDT1 \ Identifier Tag Register 1
+&244 constant CANIDM4 \ Identifier Mask Register 4
+&245 constant CANIDM3 \ Identifier Mask Register 3
+&246 constant CANIDM2 \ Identifier Mask Register 2
+&247 constant CANIDM1 \ Identifier Mask Register 1
+&248 constant CANSTML \ Time Stamp Register Low
+&249 constant CANSTMH \ Time Stamp Register High
+&250 constant CANMSG \ Message Data Register
+\ ANALOG_COMPARATOR
+&148 constant AC0CON \ Analog Comparator 0 Control Register
+ $80 constant AC0CON_AC0EN \ Analog Comparator 0 Enable Bit
+ $40 constant AC0CON_AC0IE \ Analog Comparator 0 Interrupt Enable Bit
+ $30 constant AC0CON_AC0IS \ Analog Comparator 0 Interrupt Select Bits
+ $08 constant AC0CON_ACCKSEL \ Analog Comparator Clock Select
+ $07 constant AC0CON_AC0M \ Analog Comparator 0 Multiplexer Register
+&149 constant AC1CON \ Analog Comparator 1 Control Register
+ $80 constant AC1CON_AC1EN \ Analog Comparator 1 Enable Bit
+ $40 constant AC1CON_AC1IE \ Analog Comparator 1 Interrupt Enable Bit
+ $30 constant AC1CON_AC1IS \ Analog Comparator 1 Interrupt Select Bit
+ $08 constant AC1CON_AC1ICE \ Analog Comparator 1 Interrupt Capture Enable Bit
+ $07 constant AC1CON_AC1M \ Analog Comparator 1 Multiplexer Register
+&150 constant AC2CON \ Analog Comparator 2 Control Register
+ $80 constant AC2CON_AC2EN \ Analog Comparator 2 Enable Bit
+ $40 constant AC2CON_AC2IE \ Analog Comparator 2 Interrupt Enable Bit
+ $30 constant AC2CON_AC2IS \ Analog Comparator 2 Interrupt Select Bit
+ $07 constant AC2CON_AC2M \ Analog Comparator 2 Multiplexer Register
+&151 constant AC3CON \ Analog Comparator 3 Control Register
+ $80 constant AC3CON_AC3EN \ Analog Comparator 3 Enable Bit
+ $40 constant AC3CON_AC3IE \ Analog Comparator 3 Interrupt Enable Bit
+ $30 constant AC3CON_AC3IS \ Analog Comparator 3 Interrupt Select Bit
+ $07 constant AC3CON_AC3M \ Analog Comparator 3 Multiplexer Register
+&80 constant ACSR \ Analog Comparator Status Register
+ $80 constant ACSR_AC3IF \ Analog Comparator 3 Interrupt Flag Bit
+ $40 constant ACSR_AC2IF \ Analog Comparator 2 Interrupt Flag Bit
+ $20 constant ACSR_AC1IF \ Analog Comparator 1 Interrupt Flag Bit
+ $10 constant ACSR_AC0IF \ Analog Comparator 0 Interrupt Flag Bit
+ $08 constant ACSR_AC3O \ Analog Comparator 3 Output Bit
+ $04 constant ACSR_AC2O \ Analog Comparator 2 Output Bit
+ $02 constant ACSR_AC1O \ Analog Comparator 1 Output Bit
+ $01 constant ACSR_AC0O \ Analog Comparator 0 Output Bit
+\ DA_CONVERTER
+&146 constant DACH \ DAC Data Register High Byte
+ $FF constant DACH_DACH \ DAC Data Register High Byte Bits
+&145 constant DACL \ DAC Data Register Low Byte
+ $FF constant DACL_DACL \ DAC Data Register Low Byte Bits
+&144 constant DACON \ DAC Control Register
+ $80 constant DACON_DAATE \ DAC Auto Trigger Enable Bit
+ $70 constant DACON_DATS \ DAC Trigger Selection Bits
+ $04 constant DACON_DALA \ DAC Left Adjust
+ $01 constant DACON_DAEN \ DAC Enable Bit
+\ CPU
+&87 constant SPMCSR \ Store Program Memory Control Register
+ $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
+ $20 constant SPMCSR_SIGRD \ Signature Row Read
+ $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
+ $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
+ $04 constant SPMCSR_PGWRT \ Page Write
+ $02 constant SPMCSR_PGERS \ Page Erase
+ $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
+&95 constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ $08 constant SREG_V \ Two's Complement Overflow Flag
+ $04 constant SREG_N \ Negative Flag
+ $02 constant SREG_Z \ Zero Flag
+ $01 constant SREG_C \ Carry Flag
+&93 constant SP \ Stack Pointer
+&85 constant MCUCR \ MCU Control Register
+ $80 constant MCUCR_SPIPS \ SPI Pin Select
+ $10 constant MCUCR_PUD \ Pull-up disable
+ $02 constant MCUCR_IVSEL \ Interrupt Vector Select
+ $01 constant MCUCR_IVCE \ Interrupt Vector Change Enable
+&84 constant MCUSR \ MCU Status Register
+ $08 constant MCUSR_WDRF \ Watchdog Reset Flag
+ $04 constant MCUSR_BORF \ Brown-out Reset Flag
+ $02 constant MCUSR_EXTRF \ External Reset Flag
+ $01 constant MCUSR_PORF \ Power-on reset flag
+&102 constant OSCCAL \ Oscillator Calibration Value
+&97 constant CLKPR \
+ $80 constant CLKPR_CLKPCE \
+ $0F constant CLKPR_CLKPS \
+&83 constant SMCR \ Sleep Mode Control Register
+ $0E constant SMCR_SM \ Sleep Mode Select bits
+ $01 constant SMCR_SE \ Sleep Enable
+&58 constant GPIOR2 \ General Purpose IO Register 2
+ $FF constant GPIOR2_GPIOR \ General Purpose IO Register 2 bis
+&57 constant GPIOR1 \ General Purpose IO Register 1
+ $FF constant GPIOR1_GPIOR \ General Purpose IO Register 1 bis
+&62 constant GPIOR0 \ General Purpose IO Register 0
+ $80 constant GPIOR0_GPIOR07 \ General Purpose IO Register 0 bit 7
+ $40 constant GPIOR0_GPIOR06 \ General Purpose IO Register 0 bit 6
+ $20 constant GPIOR0_GPIOR05 \ General Purpose IO Register 0 bit 5
+ $10 constant GPIOR0_GPIOR04 \ General Purpose IO Register 0 bit 4
+ $08 constant GPIOR0_GPIOR03 \ General Purpose IO Register 0 bit 3
+ $04 constant GPIOR0_GPIOR02 \ General Purpose IO Register 0 bit 2
+ $02 constant GPIOR0_GPIOR01 \ General Purpose IO Register 0 bit 1
+ $01 constant GPIOR0_GPIOR00 \ General Purpose IO Register 0 bit 0
+&73 constant PLLCSR \ PLL Control And Status Register
+ $04 constant PLLCSR_PLLF \ PLL Factor
+ $02 constant PLLCSR_PLLE \ PLL Enable
+ $01 constant PLLCSR_PLOCK \ PLL Lock Detector
+&100 constant PRR \ Power Reduction Register
+ $40 constant PRR_PRCAN \ Power Reduction CAN
+ $20 constant PRR_PRPSC \ Power Reduction PSC
+ $10 constant PRR_PRTIM1 \ Power Reduction Timer/Counter1
+ $08 constant PRR_PRTIM0 \ Power Reduction Timer/Counter0
+ $04 constant PRR_PRSPI \ Power Reduction Serial Peripheral Interface
+ $02 constant PRR_PRLIN \ Power Reduction LIN UART
+ $01 constant PRR_PRADC \ Power Reduction ADC
+\ PORTE
+&46 constant PORTE \ Port E Data Register
+&45 constant DDRE \ Port E Data Direction Register
+&44 constant PINE \ Port E Input Pins
+\ TIMER_COUNTER_0
+&110 constant TIMSK0 \ Timer/Counter0 Interrupt Mask Register
+ $04 constant TIMSK0_OCIE0B \ Timer/Counter0 Output Compare Match B Interrupt Enable
+ $02 constant TIMSK0_OCIE0A \ Timer/Counter0 Output Compare Match A Interrupt Enable
+ $01 constant TIMSK0_TOIE0 \ Timer/Counter0 Overflow Interrupt Enable
+&53 constant TIFR0 \ Timer/Counter0 Interrupt Flag register
+ $04 constant TIFR0_OCF0B \ Timer/Counter0 Output Compare Flag 0B
+ $02 constant TIFR0_OCF0A \ Timer/Counter0 Output Compare Flag 0A
+ $01 constant TIFR0_TOV0 \ Timer/Counter0 Overflow Flag
+&68 constant TCCR0A \ Timer/Counter Control Register A
+ $C0 constant TCCR0A_COM0A \ Compare Output Mode, Phase Correct PWM Mode
+ $30 constant TCCR0A_COM0B \ Compare Output Mode, Fast PWm
+ $03 constant TCCR0A_WGM0 \ Waveform Generation Mode
+&69 constant TCCR0B \ Timer/Counter Control Register B
+ $80 constant TCCR0B_FOC0A \ Force Output Compare A
+ $40 constant TCCR0B_FOC0B \ Force Output Compare B
+ $08 constant TCCR0B_WGM02 \
+ $07 constant TCCR0B_CS0 \ Clock Select
+&70 constant TCNT0 \ Timer/Counter0
+&71 constant OCR0A \ Timer/Counter0 Output Compare Register
+&72 constant OCR0B \ Timer/Counter0 Output Compare Register
+&67 constant GTCCR \ General Timer/Counter Control Register
+ $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
+ $40 constant GTCCR_ICPSEL1 \ Timer1 Input Capture Selection Bit
+ $01 constant GTCCR_PSR10 \ Prescaler Reset Timer/Counter1 and Timer/Counter0
+\ TIMER_COUNTER_1
+&111 constant TIMSK1 \ Timer/Counter Interrupt Mask Register
+ $20 constant TIMSK1_ICIE1 \ Timer/Counter1 Input Capture Interrupt Enable
+ $04 constant TIMSK1_OCIE1B \ Timer/Counter1 Output CompareB Match Interrupt Enable
+ $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output CompareA Match Interrupt Enable
+ $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
+&54 constant TIFR1 \ Timer/Counter Interrupt Flag register
+ $20 constant TIFR1_ICF1 \ Input Capture Flag 1
+ $04 constant TIFR1_OCF1B \ Output Compare Flag 1B
+ $02 constant TIFR1_OCF1A \ Output Compare Flag 1A
+ $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
+&128 constant TCCR1A \ Timer/Counter1 Control Register A
+ $C0 constant TCCR1A_COM1A \ Compare Output Mode 1A, bits
+ $30 constant TCCR1A_COM1B \ Compare Output Mode 1B, bits
+ $03 constant TCCR1A_WGM1 \ Waveform Generation Mode
+&129 constant TCCR1B \ Timer/Counter1 Control Register B
+ $80 constant TCCR1B_ICNC1 \ Input Capture 1 Noise Canceler
+ $40 constant TCCR1B_ICES1 \ Input Capture 1 Edge Select
+ $18 constant TCCR1B_WGM1 \ Waveform Generation Mode
+ $07 constant TCCR1B_CS1 \ Prescaler source of Timer/Counter 1
+&130 constant TCCR1C \ Timer/Counter1 Control Register C
+ $80 constant TCCR1C_FOC1A \
+ $40 constant TCCR1C_FOC1B \
+&132 constant TCNT1 \ Timer/Counter1 Bytes
+&136 constant OCR1A \ Timer/Counter1 Output Compare Register Bytes
+&138 constant OCR1B \ Timer/Counter1 Output Compare Register Bytes
+&134 constant ICR1 \ Timer/Counter1 Input Capture Register Bytes
+\ AD_CONVERTER
+&124 constant ADMUX \ The ADC multiplexer Selection Register
+ $C0 constant ADMUX_REFS \ Reference Selection Bits
+ $20 constant ADMUX_ADLAR \ Left Adjust Result
+ $1F constant ADMUX_MUX \ Analog Channel and Gain Selection Bits
+&122 constant ADCSRA \ The ADC Control and Status register
+ $80 constant ADCSRA_ADEN \ ADC Enable
+ $40 constant ADCSRA_ADSC \ ADC Start Conversion
+ $20 constant ADCSRA_ADATE \ ADC Auto Trigger Enable
+ $10 constant ADCSRA_ADIF \ ADC Interrupt Flag
+ $08 constant ADCSRA_ADIE \ ADC Interrupt Enable
+ $07 constant ADCSRA_ADPS \ ADC Prescaler Select Bits
+&120 constant ADC \ ADC Data Register Bytes
+&123 constant ADCSRB \ ADC Control and Status Register B
+ $80 constant ADCSRB_ADHSM \ ADC High Speed Mode
+ $40 constant ADCSRB_ISRCEN \ Current Source Enable
+ $20 constant ADCSRB_AREFEN \ Analog Reference pin Enable
+ $0F constant ADCSRB_ADTS \ ADC Auto Trigger Sources
+&126 constant DIDR0 \ Digital Input Disable Register 0
+ $80 constant DIDR0_ADC7D \ ADC7 Digital input Disable
+ $40 constant DIDR0_ADC6D \ ADC6 Digital input Disable
+ $20 constant DIDR0_ADC5D \ ADC5 Digital input Disable
+ $10 constant DIDR0_ADC4D \ ADC4 Digital input Disable
+ $08 constant DIDR0_ADC3D \ ADC3 Digital input Disable
+ $04 constant DIDR0_ADC2D \ ADC2 Digital input Disable
+ $02 constant DIDR0_ADC1D \ ADC1 Digital input Disable
+ $01 constant DIDR0_ADC0D \ ADC0 Digital input Disable
+&127 constant DIDR1 \ Digital Input Disable Register 0
+ $40 constant DIDR1_AMP2PD \ AMP2P Pin Digital input Disable
+ $20 constant DIDR1_ACMP0D \ ACMP0 Pin Digital input Disable
+ $10 constant DIDR1_AMP0PD \ AMP0P Pin Digital input Disable
+ $08 constant DIDR1_AMP0ND \ AMP0N Pin Digital input Disable
+ $04 constant DIDR1_ADC10D \ ADC10 Pin Digital input Disable
+ $02 constant DIDR1_ADC9D \ ADC9 Pin Digital input Disable
+ $01 constant DIDR1_ADC8D \ ADC8 Pin Digital input Disable
+&117 constant AMP0CSR \
+ $80 constant AMP0CSR_AMP0EN \
+ $40 constant AMP0CSR_AMP0IS \
+ $30 constant AMP0CSR_AMP0G \
+ $08 constant AMP0CSR_AMPCMP0 \ Amplifier 0 - Comparator 0 Connection
+ $07 constant AMP0CSR_AMP0TS \
+&118 constant AMP1CSR \
+ $80 constant AMP1CSR_AMP1EN \
+ $40 constant AMP1CSR_AMP1IS \
+ $30 constant AMP1CSR_AMP1G \
+ $08 constant AMP1CSR_AMPCMP1 \ Amplifier 1 - Comparator 1 Connection
+ $07 constant AMP1CSR_AMP1TS \
+&119 constant AMP2CSR \
+ $80 constant AMP2CSR_AMP2EN \
+ $40 constant AMP2CSR_AMP2IS \
+ $30 constant AMP2CSR_AMP2G \
+ $08 constant AMP2CSR_AMPCMP2 \ Amplifier 2 - Comparator 2 Connection
+ $07 constant AMP2CSR_AMP2TS \
+\ LINUART
+&200 constant LINCR \ LIN Control Register
+ $80 constant LINCR_LSWRES \ Software Reset
+ $40 constant LINCR_LIN13 \ LIN Standard
+ $30 constant LINCR_LCONF \ LIN Configuration bits
+ $08 constant LINCR_LENA \ LIN or UART Enable
+ $07 constant LINCR_LCMD \ LIN Command and Mode bits
+&201 constant LINSIR \ LIN Status and Interrupt Register
+ $E0 constant LINSIR_LIDST \ Identifier Status bits
+ $10 constant LINSIR_LBUSY \ Busy Signal
+ $08 constant LINSIR_LERR \ Error Interrupt
+ $04 constant LINSIR_LIDOK \ Identifier Interrupt
+ $02 constant LINSIR_LTXOK \ Transmit Performed Interrupt
+ $01 constant LINSIR_LRXOK \ Receive Performed Interrupt
+&202 constant LINENIR \ LIN Enable Interrupt Register
+ $08 constant LINENIR_LENERR \ Enable Error Interrupt
+ $04 constant LINENIR_LENIDOK \ Enable Identifier Interrupt
+ $02 constant LINENIR_LENTXOK \ Enable Transmit Performed Interrupt
+ $01 constant LINENIR_LENRXOK \ Enable Receive Performed Interrupt
+&203 constant LINERR \ LIN Error Register
+ $80 constant LINERR_LABORT \ Abort Flag
+ $40 constant LINERR_LTOERR \ Frame Time Out Error Flag
+ $20 constant LINERR_LOVERR \ Overrun Error Flag
+ $10 constant LINERR_LFERR \ Framing Error Flag
+ $08 constant LINERR_LSERR \ Synchronization Error Flag
+ $04 constant LINERR_LPERR \ Parity Error Flag
+ $02 constant LINERR_LCERR \ Checksum Error Flag
+ $01 constant LINERR_LBERR \ Bit Error Flag
+&204 constant LINBTR \ LIN Bit Timing Register
+ $80 constant LINBTR_LDISR \ Disable Bit Timing Resynchronization
+ $3F constant LINBTR_LBT \ LIN Bit Timing bits
+&205 constant LINBRRL \ LIN Baud Rate Low Register
+ $FF constant LINBRRL_LDIV \
+&206 constant LINBRRH \ LIN Baud Rate High Register
+ $0F constant LINBRRH_LDIV \
+&207 constant LINDLR \ LIN Data Length Register
+ $F0 constant LINDLR_LTXDL \ LIN Transmit Data Length bits
+ $0F constant LINDLR_LRXDL \ LIN Receive Data Length bits
+&208 constant LINIDR \ LIN Identifier Register
+ $C0 constant LINIDR_LP \ Parity bits
+ $3F constant LINIDR_LID \ Identifier bit 5 or Data Length bits
+&209 constant LINSEL \ LIN Data Buffer Selection Register
+ $08 constant LINSEL_LAINC \ Auto Increment of Data Buffer Index (Active Low)
+ $07 constant LINSEL_LINDX \ FIFO LIN Data Buffer Index bits
+&210 constant LINDAT \ LIN Data Register
+ $FF constant LINDAT_LDATA \
+\ SPI
+&76 constant SPCR \ SPI Control Register
+ $80 constant SPCR_SPIE \ SPI Interrupt Enable
+ $40 constant SPCR_SPE \ SPI Enable
+ $20 constant SPCR_DORD \ Data Order
+ $10 constant SPCR_MSTR \ Master/Slave Select
+ $08 constant SPCR_CPOL \ Clock polarity
+ $04 constant SPCR_CPHA \ Clock Phase
+ $03 constant SPCR_SPR \ SPI Clock Rate Selects
+&77 constant SPSR \ SPI Status Register
+ $80 constant SPSR_SPIF \ SPI Interrupt Flag
+ $40 constant SPSR_WCOL \ Write Collision Flag
+ $01 constant SPSR_SPI2X \ Double SPI Speed Bit
+&78 constant SPDR \ SPI Data Register
+\ WATCHDOG
+&96 constant WDTCSR \ Watchdog Timer Control Register
+ $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Flag
+ $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Enable
+ $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
+ $10 constant WDTCSR_WDCE \ Watchdog Change Enable
+ $08 constant WDTCSR_WDE \ Watch Dog Enable
+\ EXTERNAL_INTERRUPT
+&105 constant EICRA \ External Interrupt Control Register
+ $C0 constant EICRA_ISC3 \ External Interrupt Sense Control Bit
+ $30 constant EICRA_ISC2 \ External Interrupt Sense Control Bit
+ $0C constant EICRA_ISC1 \ External Interrupt Sense Control 1 Bits
+ $03 constant EICRA_ISC0 \ External Interrupt Sense Control 0 Bits
+&61 constant EIMSK \ External Interrupt Mask Register
+ $0F constant EIMSK_INT \ External Interrupt Request 3 Enable
+&60 constant EIFR \ External Interrupt Flag Register
+ $0F constant EIFR_INTF \ External Interrupt Flags
+&104 constant PCICR \ Pin Change Interrupt Control Register
+ $0F constant PCICR_PCIE \ Pin Change Interrupt Enables
+&109 constant PCMSK3 \ Pin Change Mask Register 3
+ $07 constant PCMSK3_PCINT \ Pin Change Enable Masks
+&108 constant PCMSK2 \ Pin Change Mask Register 2
+ $FF constant PCMSK2_PCINT \ Pin Change Enable Masks
+&107 constant PCMSK1 \ Pin Change Mask Register 1
+ $FF constant PCMSK1_PCINT \ Pin Change Enable Masks
+&106 constant PCMSK0 \ Pin Change Mask Register 0
+ $FF constant PCMSK0_PCINT \ Pin Change Enable Masks
+&59 constant PCIFR \ Pin Change Interrupt Flag Register
+ $0F constant PCIFR_PCIF \ Pin Change Interrupt Flags
+\ EEPROM
+&65 constant EEAR \ EEPROM Read/Write Access
+&64 constant EEDR \ EEPROM Data Register
+&63 constant EECR \ EEPROM Control Register
+ $30 constant EECR_EEPM \
+ $08 constant EECR_EERIE \ EEProm Ready Interrupt Enable
+ $04 constant EECR_EEMWE \ EEPROM Master Write Enable
+ $02 constant EECR_EEWE \ EEPROM Write Enable
+ $01 constant EECR_EERE \ EEPROM Read Enable
+
+\ Interrupts
+&2 constant ANACOMP0Addr \ Analog Comparator 0
+&4 constant ANACOMP1Addr \ Analog Comparator 1
+&6 constant ANACOMP2Addr \ Analog Comparator 2
+&8 constant ANACOMP3Addr \ Analog Comparator 3
+&10 constant PSC_FAULTAddr \ PSC Fault
+&12 constant PSC_ECAddr \ PSC End of Cycle
+&14 constant INT0Addr \ External Interrupt Request 0
+&16 constant INT1Addr \ External Interrupt Request 1
+&18 constant INT2Addr \ External Interrupt Request 2
+&20 constant INT3Addr \ External Interrupt Request 3
+&22 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
+&24 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
+&26 constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
+&28 constant TIMER1_OVFAddr \ Timer1/Counter1 Overflow
+&30 constant TIMER0_COMPAAddr \ Timer/Counter0 Compare Match A
+&32 constant TIMER0_COMPBAddr \ Timer/Counter0 Compare Match B
+&34 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
+&36 constant CAN_INTAddr \ CAN MOB, Burst, General Errors
+&38 constant CAN_TOVFAddr \ CAN Timer Overflow
+&40 constant LIN_TCAddr \ LIN Transfer Complete
+&42 constant LIN_ERRAddr \ LIN Error
+&44 constant PCINT0Addr \ Pin Change Interrupt Request 0
+&46 constant PCINT1Addr \ Pin Change Interrupt Request 1
+&48 constant PCINT2Addr \ Pin Change Interrupt Request 2
+&50 constant PCINT3Addr \ Pin Change Interrupt Request 3
+&52 constant SPI__STCAddr \ SPI Serial Transfer Complete
+&54 constant ADCAddr \ ADC Conversion Complete
+&56 constant WDTAddr \ Watchdog Time-Out Interrupt
+&58 constant EE_READYAddr \ EEPROM Ready
+&60 constant SPM_READYAddr \ Store Program Memory Read
diff --git a/amforth-6.5/avr8/devices/atmega32c1/device.asm b/amforth-6.5/avr8/devices/atmega32c1/device.asm
new file mode 100644
index 0000000..b43163d
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega32c1/device.asm
@@ -0,0 +1,119 @@
+; Partname: ATmega32C1
+; generated automatically, do not edit
+
+.nolist
+ .include "m32C1def.inc"
+.list
+
+.equ ramstart = 256
+.equ CELLSIZE = 2
+.macro readflashcell
+ lsl zl
+ rol zh
+ lpm @0, Z+
+ lpm @1, Z+
+.endmacro
+.macro writeflashcell
+ lsl zl
+ rol zh
+.endmacro
+.set WANT_PORTB = 0
+.set WANT_PORTC = 0
+.set WANT_PORTD = 0
+.set WANT_CAN = 0
+.set WANT_ANALOG_COMPARATOR = 0
+.set WANT_DA_CONVERTER = 0
+.set WANT_CPU = 0
+.set WANT_PORTE = 0
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_AD_CONVERTER = 0
+.set WANT_LINUART = 0
+.set WANT_SPI = 0
+.set WANT_WATCHDOG = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_EEPROM = 0
+.equ intvecsize = 2 ; please verify; flash size: 32768 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.org 2
+ rcall isr ; Analog Comparator 0
+.org 4
+ rcall isr ; Analog Comparator 1
+.org 6
+ rcall isr ; Analog Comparator 2
+.org 8
+ rcall isr ; Analog Comparator 3
+.org 10
+ rcall isr ; PSC Fault
+.org 12
+ rcall isr ; PSC End of Cycle
+.org 14
+ rcall isr ; External Interrupt Request 0
+.org 16
+ rcall isr ; External Interrupt Request 1
+.org 18
+ rcall isr ; External Interrupt Request 2
+.org 20
+ rcall isr ; External Interrupt Request 3
+.org 22
+ rcall isr ; Timer/Counter1 Capture Event
+.org 24
+ rcall isr ; Timer/Counter1 Compare Match A
+.org 26
+ rcall isr ; Timer/Counter1 Compare Match B
+.org 28
+ rcall isr ; Timer1/Counter1 Overflow
+.org 30
+ rcall isr ; Timer/Counter0 Compare Match A
+.org 32
+ rcall isr ; Timer/Counter0 Compare Match B
+.org 34
+ rcall isr ; Timer/Counter0 Overflow
+.org 36
+ rcall isr ; CAN MOB, Burst, General Errors
+.org 38
+ rcall isr ; CAN Timer Overflow
+.org 40
+ rcall isr ; LIN Transfer Complete
+.org 42
+ rcall isr ; LIN Error
+.org 44
+ rcall isr ; Pin Change Interrupt Request 0
+.org 46
+ rcall isr ; Pin Change Interrupt Request 1
+.org 48
+ rcall isr ; Pin Change Interrupt Request 2
+.org 50
+ rcall isr ; Pin Change Interrupt Request 3
+.org 52
+ rcall isr ; SPI Serial Transfer Complete
+.org 54
+ rcall isr ; ADC Conversion Complete
+.org 56
+ rcall isr ; Watchdog Time-Out Interrupt
+.org 58
+ rcall isr ; EEPROM Ready
+.org 60
+ rcall isr ; Store Program Memory Read
+.equ INTVECTORS = 31
+.nooverlap
+
+; compatability layer (maybe empty)
+.equ EEPE = EEWE
+.equ EEMPE = EEMWE
+
+; controller data area, environment query mcu-info
+mcu_info:
+mcu_ramsize:
+ .dw 2048
+mcu_eepromsize:
+ .dw 1024
+mcu_maxdp:
+ .dw 28672
+mcu_numints:
+ .dw 31
+mcu_name:
+ .dw 10
+ .db "ATmega32C1"
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega32c1/device.inc b/amforth-6.5/avr8/devices/atmega32c1/device.inc
new file mode 100644
index 0000000..c2891e4
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega32c1/device.inc
@@ -0,0 +1,1503 @@
+; Partname: ATmega32C1
+; generated automatically, no not edit
+
+.if WANT_PORTB == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw 37
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw 36
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw 35
+
+.endif
+.if WANT_PORTC == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Register
+VE_PORTC:
+ .dw $ff05
+ .db "PORTC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTC
+XT_PORTC:
+ .dw PFA_DOVARIABLE
+PFA_PORTC:
+ .dw 40
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Direction Register
+VE_DDRC:
+ .dw $ff04
+ .db "DDRC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRC
+XT_DDRC:
+ .dw PFA_DOVARIABLE
+PFA_DDRC:
+ .dw 39
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Input Pins
+VE_PINC:
+ .dw $ff04
+ .db "PINC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINC
+XT_PINC:
+ .dw PFA_DOVARIABLE
+PFA_PINC:
+ .dw 38
+
+.endif
+.if WANT_PORTD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Register
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw 43
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Data Direction Register
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw 42
+; ( -- addr ) System Constant
+; R( -- )
+; Port D Input Pins
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw 41
+
+.endif
+.if WANT_CAN == 1
+; ( -- addr ) System Constant
+; R( -- )
+; CAN General Control Register
+VE_CANGCON:
+ .dw $ff07
+ .db "CANGCON",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANGCON
+XT_CANGCON:
+ .dw PFA_DOVARIABLE
+PFA_CANGCON:
+ .dw 216
+; ( -- addr ) System Constant
+; R( -- )
+; CAN General Status Register
+VE_CANGSTA:
+ .dw $ff07
+ .db "CANGSTA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANGSTA
+XT_CANGSTA:
+ .dw PFA_DOVARIABLE
+PFA_CANGSTA:
+ .dw 217
+; ( -- addr ) System Constant
+; R( -- )
+; CAN General Interrupt Register Flags
+VE_CANGIT:
+ .dw $ff06
+ .db "CANGIT"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANGIT
+XT_CANGIT:
+ .dw PFA_DOVARIABLE
+PFA_CANGIT:
+ .dw 218
+; ( -- addr ) System Constant
+; R( -- )
+; CAN General Interrupt Enable Register
+VE_CANGIE:
+ .dw $ff06
+ .db "CANGIE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANGIE
+XT_CANGIE:
+ .dw PFA_DOVARIABLE
+PFA_CANGIE:
+ .dw 219
+; ( -- addr ) System Constant
+; R( -- )
+; Enable MOb Register 2
+VE_CANEN2:
+ .dw $ff06
+ .db "CANEN2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANEN2
+XT_CANEN2:
+ .dw PFA_DOVARIABLE
+PFA_CANEN2:
+ .dw 220
+; ( -- addr ) System Constant
+; R( -- )
+; Enable MOb Register 1(empty)
+VE_CANEN1:
+ .dw $ff06
+ .db "CANEN1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANEN1
+XT_CANEN1:
+ .dw PFA_DOVARIABLE
+PFA_CANEN1:
+ .dw 221
+; ( -- addr ) System Constant
+; R( -- )
+; Enable Interrupt MOb Register 2
+VE_CANIE2:
+ .dw $ff06
+ .db "CANIE2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANIE2
+XT_CANIE2:
+ .dw PFA_DOVARIABLE
+PFA_CANIE2:
+ .dw 222
+; ( -- addr ) System Constant
+; R( -- )
+; Enable Interrupt MOb Register 1 (empty)
+VE_CANIE1:
+ .dw $ff06
+ .db "CANIE1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANIE1
+XT_CANIE1:
+ .dw PFA_DOVARIABLE
+PFA_CANIE1:
+ .dw 223
+; ( -- addr ) System Constant
+; R( -- )
+; CAN Status Interrupt MOb Register 2
+VE_CANSIT2:
+ .dw $ff07
+ .db "CANSIT2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANSIT2
+XT_CANSIT2:
+ .dw PFA_DOVARIABLE
+PFA_CANSIT2:
+ .dw 224
+; ( -- addr ) System Constant
+; R( -- )
+; CAN Status Interrupt MOb Register 1 (empty)
+VE_CANSIT1:
+ .dw $ff07
+ .db "CANSIT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANSIT1
+XT_CANSIT1:
+ .dw PFA_DOVARIABLE
+PFA_CANSIT1:
+ .dw 225
+; ( -- addr ) System Constant
+; R( -- )
+; CAN Bit Timing Register 1
+VE_CANBT1:
+ .dw $ff06
+ .db "CANBT1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANBT1
+XT_CANBT1:
+ .dw PFA_DOVARIABLE
+PFA_CANBT1:
+ .dw 226
+; ( -- addr ) System Constant
+; R( -- )
+; CAN Bit Timing Register 2
+VE_CANBT2:
+ .dw $ff06
+ .db "CANBT2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANBT2
+XT_CANBT2:
+ .dw PFA_DOVARIABLE
+PFA_CANBT2:
+ .dw 227
+; ( -- addr ) System Constant
+; R( -- )
+; CAN Bit Timing Register 3
+VE_CANBT3:
+ .dw $ff06
+ .db "CANBT3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANBT3
+XT_CANBT3:
+ .dw PFA_DOVARIABLE
+PFA_CANBT3:
+ .dw 228
+; ( -- addr ) System Constant
+; R( -- )
+; Timer Control Register
+VE_CANTCON:
+ .dw $ff07
+ .db "CANTCON",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANTCON
+XT_CANTCON:
+ .dw PFA_DOVARIABLE
+PFA_CANTCON:
+ .dw 229
+; ( -- addr ) System Constant
+; R( -- )
+; Timer Register Low
+VE_CANTIML:
+ .dw $ff07
+ .db "CANTIML",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANTIML
+XT_CANTIML:
+ .dw PFA_DOVARIABLE
+PFA_CANTIML:
+ .dw 230
+; ( -- addr ) System Constant
+; R( -- )
+; Timer Register High
+VE_CANTIMH:
+ .dw $ff07
+ .db "CANTIMH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANTIMH
+XT_CANTIMH:
+ .dw PFA_DOVARIABLE
+PFA_CANTIMH:
+ .dw 231
+; ( -- addr ) System Constant
+; R( -- )
+; TTC Timer Register Low
+VE_CANTTCL:
+ .dw $ff07
+ .db "CANTTCL",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANTTCL
+XT_CANTTCL:
+ .dw PFA_DOVARIABLE
+PFA_CANTTCL:
+ .dw 232
+; ( -- addr ) System Constant
+; R( -- )
+; TTC Timer Register High
+VE_CANTTCH:
+ .dw $ff07
+ .db "CANTTCH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANTTCH
+XT_CANTTCH:
+ .dw PFA_DOVARIABLE
+PFA_CANTTCH:
+ .dw 233
+; ( -- addr ) System Constant
+; R( -- )
+; Transmit Error Counter Register
+VE_CANTEC:
+ .dw $ff06
+ .db "CANTEC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANTEC
+XT_CANTEC:
+ .dw PFA_DOVARIABLE
+PFA_CANTEC:
+ .dw 234
+; ( -- addr ) System Constant
+; R( -- )
+; Receive Error Counter Register
+VE_CANREC:
+ .dw $ff06
+ .db "CANREC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANREC
+XT_CANREC:
+ .dw PFA_DOVARIABLE
+PFA_CANREC:
+ .dw 235
+; ( -- addr ) System Constant
+; R( -- )
+; Highest Priority MOb Register
+VE_CANHPMOB:
+ .dw $ff08
+ .db "CANHPMOB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANHPMOB
+XT_CANHPMOB:
+ .dw PFA_DOVARIABLE
+PFA_CANHPMOB:
+ .dw 236
+; ( -- addr ) System Constant
+; R( -- )
+; Page MOb Register
+VE_CANPAGE:
+ .dw $ff07
+ .db "CANPAGE",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANPAGE
+XT_CANPAGE:
+ .dw PFA_DOVARIABLE
+PFA_CANPAGE:
+ .dw 237
+; ( -- addr ) System Constant
+; R( -- )
+; MOb Status Register
+VE_CANSTMOB:
+ .dw $ff08
+ .db "CANSTMOB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANSTMOB
+XT_CANSTMOB:
+ .dw PFA_DOVARIABLE
+PFA_CANSTMOB:
+ .dw 238
+; ( -- addr ) System Constant
+; R( -- )
+; MOb Control and DLC Register
+VE_CANCDMOB:
+ .dw $ff08
+ .db "CANCDMOB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANCDMOB
+XT_CANCDMOB:
+ .dw PFA_DOVARIABLE
+PFA_CANCDMOB:
+ .dw 239
+; ( -- addr ) System Constant
+; R( -- )
+; Identifier Tag Register 4
+VE_CANIDT4:
+ .dw $ff07
+ .db "CANIDT4",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANIDT4
+XT_CANIDT4:
+ .dw PFA_DOVARIABLE
+PFA_CANIDT4:
+ .dw 240
+; ( -- addr ) System Constant
+; R( -- )
+; Identifier Tag Register 3
+VE_CANIDT3:
+ .dw $ff07
+ .db "CANIDT3",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANIDT3
+XT_CANIDT3:
+ .dw PFA_DOVARIABLE
+PFA_CANIDT3:
+ .dw 241
+; ( -- addr ) System Constant
+; R( -- )
+; Identifier Tag Register 2
+VE_CANIDT2:
+ .dw $ff07
+ .db "CANIDT2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANIDT2
+XT_CANIDT2:
+ .dw PFA_DOVARIABLE
+PFA_CANIDT2:
+ .dw 242
+; ( -- addr ) System Constant
+; R( -- )
+; Identifier Tag Register 1
+VE_CANIDT1:
+ .dw $ff07
+ .db "CANIDT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANIDT1
+XT_CANIDT1:
+ .dw PFA_DOVARIABLE
+PFA_CANIDT1:
+ .dw 243
+; ( -- addr ) System Constant
+; R( -- )
+; Identifier Mask Register 4
+VE_CANIDM4:
+ .dw $ff07
+ .db "CANIDM4",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANIDM4
+XT_CANIDM4:
+ .dw PFA_DOVARIABLE
+PFA_CANIDM4:
+ .dw 244
+; ( -- addr ) System Constant
+; R( -- )
+; Identifier Mask Register 3
+VE_CANIDM3:
+ .dw $ff07
+ .db "CANIDM3",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANIDM3
+XT_CANIDM3:
+ .dw PFA_DOVARIABLE
+PFA_CANIDM3:
+ .dw 245
+; ( -- addr ) System Constant
+; R( -- )
+; Identifier Mask Register 2
+VE_CANIDM2:
+ .dw $ff07
+ .db "CANIDM2",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANIDM2
+XT_CANIDM2:
+ .dw PFA_DOVARIABLE
+PFA_CANIDM2:
+ .dw 246
+; ( -- addr ) System Constant
+; R( -- )
+; Identifier Mask Register 1
+VE_CANIDM1:
+ .dw $ff07
+ .db "CANIDM1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANIDM1
+XT_CANIDM1:
+ .dw PFA_DOVARIABLE
+PFA_CANIDM1:
+ .dw 247
+; ( -- addr ) System Constant
+; R( -- )
+; Time Stamp Register Low
+VE_CANSTML:
+ .dw $ff07
+ .db "CANSTML",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANSTML
+XT_CANSTML:
+ .dw PFA_DOVARIABLE
+PFA_CANSTML:
+ .dw 248
+; ( -- addr ) System Constant
+; R( -- )
+; Time Stamp Register High
+VE_CANSTMH:
+ .dw $ff07
+ .db "CANSTMH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANSTMH
+XT_CANSTMH:
+ .dw PFA_DOVARIABLE
+PFA_CANSTMH:
+ .dw 249
+; ( -- addr ) System Constant
+; R( -- )
+; Message Data Register
+VE_CANMSG:
+ .dw $ff06
+ .db "CANMSG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CANMSG
+XT_CANMSG:
+ .dw PFA_DOVARIABLE
+PFA_CANMSG:
+ .dw 250
+
+.endif
+.if WANT_ANALOG_COMPARATOR == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator 0 Control Register
+VE_AC0CON:
+ .dw $ff06
+ .db "AC0CON"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_AC0CON
+XT_AC0CON:
+ .dw PFA_DOVARIABLE
+PFA_AC0CON:
+ .dw 148
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator 1 Control Register
+VE_AC1CON:
+ .dw $ff06
+ .db "AC1CON"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_AC1CON
+XT_AC1CON:
+ .dw PFA_DOVARIABLE
+PFA_AC1CON:
+ .dw 149
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator 2 Control Register
+VE_AC2CON:
+ .dw $ff06
+ .db "AC2CON"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_AC2CON
+XT_AC2CON:
+ .dw PFA_DOVARIABLE
+PFA_AC2CON:
+ .dw 150
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator 3 Control Register
+VE_AC3CON:
+ .dw $ff06
+ .db "AC3CON"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_AC3CON
+XT_AC3CON:
+ .dw PFA_DOVARIABLE
+PFA_AC3CON:
+ .dw 151
+; ( -- addr ) System Constant
+; R( -- )
+; Analog Comparator Status Register
+VE_ACSR:
+ .dw $ff04
+ .db "ACSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ACSR
+XT_ACSR:
+ .dw PFA_DOVARIABLE
+PFA_ACSR:
+ .dw 80
+
+.endif
+.if WANT_DA_CONVERTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; DAC Data Register High Byte
+VE_DACH:
+ .dw $ff04
+ .db "DACH"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DACH
+XT_DACH:
+ .dw PFA_DOVARIABLE
+PFA_DACH:
+ .dw 146
+; ( -- addr ) System Constant
+; R( -- )
+; DAC Data Register Low Byte
+VE_DACL:
+ .dw $ff04
+ .db "DACL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DACL
+XT_DACL:
+ .dw PFA_DOVARIABLE
+PFA_DACL:
+ .dw 145
+; ( -- addr ) System Constant
+; R( -- )
+; DAC Control Register
+VE_DACON:
+ .dw $ff05
+ .db "DACON",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DACON
+XT_DACON:
+ .dw PFA_DOVARIABLE
+PFA_DACON:
+ .dw 144
+
+.endif
+.if WANT_CPU == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control Register
+VE_SPMCSR:
+ .dw $ff06
+ .db "SPMCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCSR
+XT_SPMCSR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCSR:
+ .dw 87
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw 95
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer
+VE_SP:
+ .dw $ff02
+ .db "SP"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SP
+XT_SP:
+ .dw PFA_DOVARIABLE
+PFA_SP:
+ .dw 93
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw 85
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Status Register
+VE_MCUSR:
+ .dw $ff05
+ .db "MCUSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUSR
+XT_MCUSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUSR:
+ .dw 84
+; ( -- addr ) System Constant
+; R( -- )
+; Oscillator Calibration Value
+VE_OSCCAL:
+ .dw $ff06
+ .db "OSCCAL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OSCCAL
+XT_OSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_OSCCAL:
+ .dw 102
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_CLKPR:
+ .dw $ff05
+ .db "CLKPR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CLKPR
+XT_CLKPR:
+ .dw PFA_DOVARIABLE
+PFA_CLKPR:
+ .dw 97
+; ( -- addr ) System Constant
+; R( -- )
+; Sleep Mode Control Register
+VE_SMCR:
+ .dw $ff04
+ .db "SMCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SMCR
+XT_SMCR:
+ .dw PFA_DOVARIABLE
+PFA_SMCR:
+ .dw 83
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 2
+VE_GPIOR2:
+ .dw $ff06
+ .db "GPIOR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR2
+XT_GPIOR2:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR2:
+ .dw 58
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 1
+VE_GPIOR1:
+ .dw $ff06
+ .db "GPIOR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR1
+XT_GPIOR1:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR1:
+ .dw 57
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 0
+VE_GPIOR0:
+ .dw $ff06
+ .db "GPIOR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR0
+XT_GPIOR0:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR0:
+ .dw 62
+; ( -- addr ) System Constant
+; R( -- )
+; PLL Control And Status Register
+VE_PLLCSR:
+ .dw $ff06
+ .db "PLLCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PLLCSR
+XT_PLLCSR:
+ .dw PFA_DOVARIABLE
+PFA_PLLCSR:
+ .dw 73
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register
+VE_PRR:
+ .dw $ff03
+ .db "PRR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR
+XT_PRR:
+ .dw PFA_DOVARIABLE
+PFA_PRR:
+ .dw 100
+
+.endif
+.if WANT_PORTE == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port E Data Register
+VE_PORTE:
+ .dw $ff05
+ .db "PORTE",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTE
+XT_PORTE:
+ .dw PFA_DOVARIABLE
+PFA_PORTE:
+ .dw 46
+; ( -- addr ) System Constant
+; R( -- )
+; Port E Data Direction Register
+VE_DDRE:
+ .dw $ff04
+ .db "DDRE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRE
+XT_DDRE:
+ .dw PFA_DOVARIABLE
+PFA_DDRE:
+ .dw 45
+; ( -- addr ) System Constant
+; R( -- )
+; Port E Input Pins
+VE_PINE:
+ .dw $ff04
+ .db "PINE"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINE
+XT_PINE:
+ .dw PFA_DOVARIABLE
+PFA_PINE:
+ .dw 44
+
+.endif
+.if WANT_TIMER_COUNTER_0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Mask Register
+VE_TIMSK0:
+ .dw $ff06
+ .db "TIMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK0
+XT_TIMSK0:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK0:
+ .dw 110
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Interrupt Flag register
+VE_TIFR0:
+ .dw $ff05
+ .db "TIFR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR0
+XT_TIFR0:
+ .dw PFA_DOVARIABLE
+PFA_TIFR0:
+ .dw 53
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register A
+VE_TCCR0A:
+ .dw $ff06
+ .db "TCCR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0A
+XT_TCCR0A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0A:
+ .dw 68
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Control Register B
+VE_TCCR0B:
+ .dw $ff06
+ .db "TCCR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0B
+XT_TCCR0B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0B:
+ .dw 69
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw 70
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0A:
+ .dw $ff05
+ .db "OCR0A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0A
+XT_OCR0A:
+ .dw PFA_DOVARIABLE
+PFA_OCR0A:
+ .dw 71
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Output Compare Register
+VE_OCR0B:
+ .dw $ff05
+ .db "OCR0B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0B
+XT_OCR0B:
+ .dw PFA_DOVARIABLE
+PFA_OCR0B:
+ .dw 72
+; ( -- addr ) System Constant
+; R( -- )
+; General Timer/Counter Control Register
+VE_GTCCR:
+ .dw $ff05
+ .db "GTCCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GTCCR
+XT_GTCCR:
+ .dw PFA_DOVARIABLE
+PFA_GTCCR:
+ .dw 67
+
+.endif
+.if WANT_TIMER_COUNTER_1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Mask Register
+VE_TIMSK1:
+ .dw $ff06
+ .db "TIMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK1
+XT_TIMSK1:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK1:
+ .dw 111
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Flag register
+VE_TIFR1:
+ .dw $ff05
+ .db "TIFR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR1
+XT_TIFR1:
+ .dw PFA_DOVARIABLE
+PFA_TIFR1:
+ .dw 54
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register A
+VE_TCCR1A:
+ .dw $ff06
+ .db "TCCR1A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1A
+XT_TCCR1A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1A:
+ .dw 128
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw 129
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register C
+VE_TCCR1C:
+ .dw $ff06
+ .db "TCCR1C"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1C
+XT_TCCR1C:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1C:
+ .dw 130
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Bytes
+VE_TCNT1:
+ .dw $ff05
+ .db "TCNT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1
+XT_TCNT1:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1:
+ .dw 132
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register Bytes
+VE_OCR1A:
+ .dw $ff05
+ .db "OCR1A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1A
+XT_OCR1A:
+ .dw PFA_DOVARIABLE
+PFA_OCR1A:
+ .dw 136
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Output Compare Register Bytes
+VE_OCR1B:
+ .dw $ff05
+ .db "OCR1B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1B
+XT_OCR1B:
+ .dw PFA_DOVARIABLE
+PFA_OCR1B:
+ .dw 138
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Input Capture Register Bytes
+VE_ICR1:
+ .dw $ff04
+ .db "ICR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ICR1
+XT_ICR1:
+ .dw PFA_DOVARIABLE
+PFA_ICR1:
+ .dw 134
+
+.endif
+.if WANT_AD_CONVERTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC multiplexer Selection Register
+VE_ADMUX:
+ .dw $ff05
+ .db "ADMUX",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADMUX
+XT_ADMUX:
+ .dw PFA_DOVARIABLE
+PFA_ADMUX:
+ .dw 124
+; ( -- addr ) System Constant
+; R( -- )
+; The ADC Control and Status register
+VE_ADCSRA:
+ .dw $ff06
+ .db "ADCSRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRA
+XT_ADCSRA:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRA:
+ .dw 122
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Data Register Bytes
+VE_ADC:
+ .dw $ff03
+ .db "ADC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADC
+XT_ADC:
+ .dw PFA_DOVARIABLE
+PFA_ADC:
+ .dw 120
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Control and Status Register B
+VE_ADCSRB:
+ .dw $ff06
+ .db "ADCSRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_ADCSRB
+XT_ADCSRB:
+ .dw PFA_DOVARIABLE
+PFA_ADCSRB:
+ .dw 123
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 0
+VE_DIDR0:
+ .dw $ff05
+ .db "DIDR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR0
+XT_DIDR0:
+ .dw PFA_DOVARIABLE
+PFA_DIDR0:
+ .dw 126
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register 0
+VE_DIDR1:
+ .dw $ff05
+ .db "DIDR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR1
+XT_DIDR1:
+ .dw PFA_DOVARIABLE
+PFA_DIDR1:
+ .dw 127
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_AMP0CSR:
+ .dw $ff07
+ .db "AMP0CSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_AMP0CSR
+XT_AMP0CSR:
+ .dw PFA_DOVARIABLE
+PFA_AMP0CSR:
+ .dw 117
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_AMP1CSR:
+ .dw $ff07
+ .db "AMP1CSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_AMP1CSR
+XT_AMP1CSR:
+ .dw PFA_DOVARIABLE
+PFA_AMP1CSR:
+ .dw 118
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_AMP2CSR:
+ .dw $ff07
+ .db "AMP2CSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_AMP2CSR
+XT_AMP2CSR:
+ .dw PFA_DOVARIABLE
+PFA_AMP2CSR:
+ .dw 119
+
+.endif
+.if WANT_LINUART == 1
+; ( -- addr ) System Constant
+; R( -- )
+; LIN Control Register
+VE_LINCR:
+ .dw $ff05
+ .db "LINCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LINCR
+XT_LINCR:
+ .dw PFA_DOVARIABLE
+PFA_LINCR:
+ .dw 200
+; ( -- addr ) System Constant
+; R( -- )
+; LIN Status and Interrupt Register
+VE_LINSIR:
+ .dw $ff06
+ .db "LINSIR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LINSIR
+XT_LINSIR:
+ .dw PFA_DOVARIABLE
+PFA_LINSIR:
+ .dw 201
+; ( -- addr ) System Constant
+; R( -- )
+; LIN Enable Interrupt Register
+VE_LINENIR:
+ .dw $ff07
+ .db "LINENIR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LINENIR
+XT_LINENIR:
+ .dw PFA_DOVARIABLE
+PFA_LINENIR:
+ .dw 202
+; ( -- addr ) System Constant
+; R( -- )
+; LIN Error Register
+VE_LINERR:
+ .dw $ff06
+ .db "LINERR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LINERR
+XT_LINERR:
+ .dw PFA_DOVARIABLE
+PFA_LINERR:
+ .dw 203
+; ( -- addr ) System Constant
+; R( -- )
+; LIN Bit Timing Register
+VE_LINBTR:
+ .dw $ff06
+ .db "LINBTR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LINBTR
+XT_LINBTR:
+ .dw PFA_DOVARIABLE
+PFA_LINBTR:
+ .dw 204
+; ( -- addr ) System Constant
+; R( -- )
+; LIN Baud Rate Low Register
+VE_LINBRRL:
+ .dw $ff07
+ .db "LINBRRL",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LINBRRL
+XT_LINBRRL:
+ .dw PFA_DOVARIABLE
+PFA_LINBRRL:
+ .dw 205
+; ( -- addr ) System Constant
+; R( -- )
+; LIN Baud Rate High Register
+VE_LINBRRH:
+ .dw $ff07
+ .db "LINBRRH",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LINBRRH
+XT_LINBRRH:
+ .dw PFA_DOVARIABLE
+PFA_LINBRRH:
+ .dw 206
+; ( -- addr ) System Constant
+; R( -- )
+; LIN Data Length Register
+VE_LINDLR:
+ .dw $ff06
+ .db "LINDLR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LINDLR
+XT_LINDLR:
+ .dw PFA_DOVARIABLE
+PFA_LINDLR:
+ .dw 207
+; ( -- addr ) System Constant
+; R( -- )
+; LIN Identifier Register
+VE_LINIDR:
+ .dw $ff06
+ .db "LINIDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LINIDR
+XT_LINIDR:
+ .dw PFA_DOVARIABLE
+PFA_LINIDR:
+ .dw 208
+; ( -- addr ) System Constant
+; R( -- )
+; LIN Data Buffer Selection Register
+VE_LINSEL:
+ .dw $ff06
+ .db "LINSEL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LINSEL
+XT_LINSEL:
+ .dw PFA_DOVARIABLE
+PFA_LINSEL:
+ .dw 209
+; ( -- addr ) System Constant
+; R( -- )
+; LIN Data Register
+VE_LINDAT:
+ .dw $ff06
+ .db "LINDAT"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_LINDAT
+XT_LINDAT:
+ .dw PFA_DOVARIABLE
+PFA_LINDAT:
+ .dw 210
+
+.endif
+.if WANT_SPI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Control Register
+VE_SPCR:
+ .dw $ff04
+ .db "SPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPCR
+XT_SPCR:
+ .dw PFA_DOVARIABLE
+PFA_SPCR:
+ .dw 76
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Status Register
+VE_SPSR:
+ .dw $ff04
+ .db "SPSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPSR
+XT_SPSR:
+ .dw PFA_DOVARIABLE
+PFA_SPSR:
+ .dw 77
+; ( -- addr ) System Constant
+; R( -- )
+; SPI Data Register
+VE_SPDR:
+ .dw $ff04
+ .db "SPDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPDR
+XT_SPDR:
+ .dw PFA_DOVARIABLE
+PFA_SPDR:
+ .dw 78
+
+.endif
+.if WANT_WATCHDOG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCSR:
+ .dw $ff06
+ .db "WDTCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCSR
+XT_WDTCSR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCSR:
+ .dw 96
+
+.endif
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register
+VE_EICRA:
+ .dw $ff05
+ .db "EICRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRA
+XT_EICRA:
+ .dw PFA_DOVARIABLE
+PFA_EICRA:
+ .dw 105
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Mask Register
+VE_EIMSK:
+ .dw $ff05
+ .db "EIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIMSK
+XT_EIMSK:
+ .dw PFA_DOVARIABLE
+PFA_EIMSK:
+ .dw 61
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Flag Register
+VE_EIFR:
+ .dw $ff04
+ .db "EIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIFR
+XT_EIFR:
+ .dw PFA_DOVARIABLE
+PFA_EIFR:
+ .dw 60
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Interrupt Control Register
+VE_PCICR:
+ .dw $ff05
+ .db "PCICR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCICR
+XT_PCICR:
+ .dw PFA_DOVARIABLE
+PFA_PCICR:
+ .dw 104
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 3
+VE_PCMSK3:
+ .dw $ff06
+ .db "PCMSK3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK3
+XT_PCMSK3:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK3:
+ .dw 109
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 2
+VE_PCMSK2:
+ .dw $ff06
+ .db "PCMSK2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK2
+XT_PCMSK2:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK2:
+ .dw 108
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 1
+VE_PCMSK1:
+ .dw $ff06
+ .db "PCMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK1
+XT_PCMSK1:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK1:
+ .dw 107
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Mask Register 0
+VE_PCMSK0:
+ .dw $ff06
+ .db "PCMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK0
+XT_PCMSK0:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK0:
+ .dw 106
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Interrupt Flag Register
+VE_PCIFR:
+ .dw $ff05
+ .db "PCIFR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCIFR
+XT_PCIFR:
+ .dw PFA_DOVARIABLE
+PFA_PCIFR:
+ .dw 59
+
+.endif
+.if WANT_EEPROM == 1
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Read/Write Access
+VE_EEAR:
+ .dw $ff04
+ .db "EEAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEAR
+XT_EEAR:
+ .dw PFA_DOVARIABLE
+PFA_EEAR:
+ .dw 65
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw 64
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw 63
+
+.endif
diff --git a/amforth-6.5/avr8/devices/atmega32c1/device.py b/amforth-6.5/avr8/devices/atmega32c1/device.py
new file mode 100644
index 0000000..fe62918
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega32c1/device.py
@@ -0,0 +1,477 @@
+# Generated Automatically
+
+# Partname ATmega32C1
+
+MCUREGS = {
+# Interrupt Vectors
+ 'ANACOMP0Addr' : '#2', # Analog Comparator 0
+ 'ANACOMP1Addr' : '#4', # Analog Comparator 1
+ 'ANACOMP2Addr' : '#6', # Analog Comparator 2
+ 'ANACOMP3Addr' : '#8', # Analog Comparator 3
+ 'PSC_FAULTAddr' : '#10', # PSC Fault
+ 'PSC_ECAddr' : '#12', # PSC End of Cycle
+ 'INT0Addr' : '#14', # External Interrupt Request 0
+ 'INT1Addr' : '#16', # External Interrupt Request 1
+ 'INT2Addr' : '#18', # External Interrupt Request 2
+ 'INT3Addr' : '#20', # External Interrupt Request 3
+ 'TIMER1_CAPTAddr' : '#22', # Timer/Counter1 Capture Event
+ 'TIMER1_COMPAAddr' : '#24', # Timer/Counter1 Compare Match A
+ 'TIMER1_COMPBAddr' : '#26', # Timer/Counter1 Compare Match B
+ 'TIMER1_OVFAddr' : '#28', # Timer1/Counter1 Overflow
+ 'TIMER0_COMPAAddr' : '#30', # Timer/Counter0 Compare Match A
+ 'TIMER0_COMPBAddr' : '#32', # Timer/Counter0 Compare Match B
+ 'TIMER0_OVFAddr' : '#34', # Timer/Counter0 Overflow
+ 'CAN_INTAddr' : '#36', # CAN MOB, Burst, General Errors
+ 'CAN_TOVFAddr' : '#38', # CAN Timer Overflow
+ 'LIN_TCAddr' : '#40', # LIN Transfer Complete
+ 'LIN_ERRAddr' : '#42', # LIN Error
+ 'PCINT0Addr' : '#44', # Pin Change Interrupt Request 0
+ 'PCINT1Addr' : '#46', # Pin Change Interrupt Request 1
+ 'PCINT2Addr' : '#48', # Pin Change Interrupt Request 2
+ 'PCINT3Addr' : '#50', # Pin Change Interrupt Request 3
+ 'SPI_STCAddr' : '#52', # SPI Serial Transfer Complete
+ 'ADCAddr' : '#54', # ADC Conversion Complete
+ 'WDTAddr' : '#56', # Watchdog Time-Out Interrupt
+ 'EE_READYAddr' : '#58', # EEPROM Ready
+ 'SPM_READYAddr' : '#60', # Store Program Memory Read
+
+# Module PORTB
+ 'PORTB' : '$25', # Port B Data Register
+ 'DDRB' : '$24', # Port B Data Direction Register
+ 'PINB' : '$23', # Port B Input Pins
+
+# Module PORTC
+ 'PORTC' : '$28', # Port C Data Register
+ 'DDRC' : '$27', # Port C Data Direction Register
+ 'PINC' : '$26', # Port C Input Pins
+
+# Module PORTD
+ 'PORTD' : '$2b', # Port D Data Register
+ 'DDRD' : '$2a', # Port D Data Direction Register
+ 'PIND' : '$29', # Port D Input Pins
+
+# Module CAN
+ 'CANGCON' : '$d8', # CAN General Control Register
+ 'CANGCON_ABRQ': '$80', # Abort Request
+ 'CANGCON_OVRQ': '$40', # Overload Frame Request
+ 'CANGCON_TTC': '$20', # Time Trigger Communication
+ 'CANGCON_SYNTTC': '$10', # Synchronization of TTC
+ 'CANGCON_LISTEN': '$8', # Listening Mode
+ 'CANGCON_TEST': '$4', # Test Mode
+ 'CANGCON_ENASTB': '$2', # Enable / Standby
+ 'CANGCON_SWRES': '$1', # Software Reset Request
+ 'CANGSTA' : '$d9', # CAN General Status Register
+ 'CANGSTA_OVFG': '$40', # Overload Frame Flag
+ 'CANGSTA_TXBSY': '$10', # Transmitter Busy
+ 'CANGSTA_RXBSY': '$8', # Receiver Busy
+ 'CANGSTA_ENFG': '$4', # Enable Flag
+ 'CANGSTA_BOFF': '$2', # Bus Off Mode
+ 'CANGSTA_ERRP': '$1', # Error Passive Mode
+ 'CANGIT' : '$da', # CAN General Interrupt Register
+ 'CANGIT_CANIT': '$80', # General Interrupt Flag
+ 'CANGIT_BOFFIT': '$40', # Bus Off Interrupt Flag
+ 'CANGIT_OVRTIM': '$20', # Overrun CAN Timer Flag
+ 'CANGIT_BXOK': '$10', # Burst Receive Interrupt Flag
+ 'CANGIT_SERG': '$8', # Stuff Error General Flag
+ 'CANGIT_CERG': '$4', # CRC Error General Flag
+ 'CANGIT_FERG': '$2', # Form Error General Flag
+ 'CANGIT_AERG': '$1', # Ackknowledgement Error General
+ 'CANGIE' : '$db', # CAN General Interrupt Enable R
+ 'CANGIE_ENIT': '$80', # Enable all Interrupts
+ 'CANGIE_ENBOFF': '$40', # Enable Bus Off Interrupt
+ 'CANGIE_ENRX': '$20', # Enable Receive Interrupt
+ 'CANGIE_ENTX': '$10', # Enable Transmitt Interrupt
+ 'CANGIE_ENERR': '$8', # Enable MOb Error Interrupt
+ 'CANGIE_ENBX': '$4', # Enable Burst Receive Interrupt
+ 'CANGIE_ENERG': '$2', # Enable General Error Interrupt
+ 'CANGIE_ENOVRT': '$1', # Enable CAN Timer Overrun Inter
+ 'CANEN2' : '$dc', # Enable MOb Register 2
+ 'CANEN2_ENMOB': '$3f', # Enable MObs
+ 'CANEN1' : '$dd', # Enable MOb Register 1(empty)
+ 'CANIE2' : '$de', # Enable Interrupt MOb Register
+ 'CANIE2_IEMOB': '$3f', # Interrupt Enable MObs
+ 'CANIE1' : '$df', # Enable Interrupt MOb Register
+ 'CANSIT2' : '$e0', # CAN Status Interrupt MOb Regis
+ 'CANSIT2_SIT': '$3f', # Status of Interrupt MObs
+ 'CANSIT1' : '$e1', # CAN Status Interrupt MOb Regis
+ 'CANBT1' : '$e2', # CAN Bit Timing Register 1
+ 'CANBT1_BRP': '$7e', # Baud Rate Prescaler bits
+ 'CANBT2' : '$e3', # CAN Bit Timing Register 2
+ 'CANBT2_SJW': '$60', # Re-Sync Jump Width bits
+ 'CANBT2_PRS': '$e', # Propagation Time Segment bits
+ 'CANBT3' : '$e4', # CAN Bit Timing Register 3
+ 'CANBT3_PHS2': '$70', # Phase Segment 2 bits
+ 'CANBT3_PHS1': '$e', # Phase Segment 1 bits
+ 'CANBT3_SMP': '$1', # Sample Type
+ 'CANTCON' : '$e5', # Timer Control Register
+ 'CANTIML' : '$e6', # Timer Register Low
+ 'CANTIMH' : '$e7', # Timer Register High
+ 'CANTTCL' : '$e8', # TTC Timer Register Low
+ 'CANTTCH' : '$e9', # TTC Timer Register High
+ 'CANTEC' : '$ea', # Transmit Error Counter Registe
+ 'CANREC' : '$eb', # Receive Error Counter Register
+ 'CANHPMOB' : '$ec', # Highest Priority MOb Register
+ 'CANHPMOB_HPMOB': '$f0', # Highest Priority MOb Number bi
+ 'CANHPMOB_CGP': '$f', # CAN General Purpose bits
+ 'CANPAGE' : '$ed', # Page MOb Register
+ 'CANPAGE_MOBNB': '$f0', # MOb Number bits
+ 'CANPAGE_AINC': '$8', # MOb Data Buffer Auto Increment
+ 'CANPAGE_INDX': '$7', # Data Buffer Index bits
+ 'CANSTMOB' : '$ee', # MOb Status Register
+ 'CANSTMOB_DLCW': '$80', # Data Length Code Warning on MO
+ 'CANSTMOB_TXOK': '$40', # Transmit OK on MOb
+ 'CANSTMOB_RXOK': '$20', # Receive OK on MOb
+ 'CANSTMOB_BERR': '$10', # Bit Error on MOb
+ 'CANSTMOB_SERR': '$8', # Stuff Error on MOb
+ 'CANSTMOB_CERR': '$4', # CRC Error on MOb
+ 'CANSTMOB_FERR': '$2', # Form Error on MOb
+ 'CANSTMOB_AERR': '$1', # Ackknowledgement Error on MOb
+ 'CANCDMOB' : '$ef', # MOb Control and DLC Register
+ 'CANCDMOB_CONMOB': '$c0', # MOb Config bits
+ 'CANCDMOB_RPLV': '$20', # Reply Valid
+ 'CANCDMOB_IDE': '$10', # Identifier Extension
+ 'CANCDMOB_DLC': '$f', # Data Length Code bits
+ 'CANIDT4' : '$f0', # Identifier Tag Register 4
+ 'CANIDT4_IDT': '$f8', #
+ 'CANIDT4_RTRTAG': '$4', #
+ 'CANIDT4_RB1TAG': '$2', #
+ 'CANIDT4_RB0TAG': '$1', #
+ 'CANIDT3' : '$f1', # Identifier Tag Register 3
+ 'CANIDT2' : '$f2', # Identifier Tag Register 2
+ 'CANIDT1' : '$f3', # Identifier Tag Register 1
+ 'CANIDM4' : '$f4', # Identifier Mask Register 4
+ 'CANIDM3' : '$f5', # Identifier Mask Register 3
+ 'CANIDM2' : '$f6', # Identifier Mask Register 2
+ 'CANIDM1' : '$f7', # Identifier Mask Register 1
+ 'CANSTML' : '$f8', # Time Stamp Register Low
+ 'CANSTMH' : '$f9', # Time Stamp Register High
+ 'CANMSG' : '$fa', # Message Data Register
+
+# Module ANALOG_COMPARATOR
+ 'AC0CON' : '$94', # Analog Comparator 0 Control Re
+ 'AC0CON_AC0EN': '$80', # Analog Comparator 0 Enable Bit
+ 'AC0CON_AC0IE': '$40', # Analog Comparator 0 Interrupt
+ 'AC0CON_AC0IS': '$30', # Analog Comparator 0 Interrupt
+ 'AC0CON_ACCKSEL': '$8', # Analog Comparator Clock Select
+ 'AC0CON_AC0M': '$7', # Analog Comparator 0 Multiplexe
+ 'AC1CON' : '$95', # Analog Comparator 1 Control Re
+ 'AC1CON_AC1EN': '$80', # Analog Comparator 1 Enable Bit
+ 'AC1CON_AC1IE': '$40', # Analog Comparator 1 Interrupt
+ 'AC1CON_AC1IS': '$30', # Analog Comparator 1 Interrupt
+ 'AC1CON_AC1ICE': '$8', # Analog Comparator 1 Interrupt
+ 'AC1CON_AC1M': '$7', # Analog Comparator 1 Multiplexe
+ 'AC2CON' : '$96', # Analog Comparator 2 Control Re
+ 'AC2CON_AC2EN': '$80', # Analog Comparator 2 Enable Bit
+ 'AC2CON_AC2IE': '$40', # Analog Comparator 2 Interrupt
+ 'AC2CON_AC2IS': '$30', # Analog Comparator 2 Interrupt
+ 'AC2CON_AC2M': '$7', # Analog Comparator 2 Multiplexe
+ 'AC3CON' : '$97', # Analog Comparator 3 Control Re
+ 'AC3CON_AC3EN': '$80', # Analog Comparator 3 Enable Bit
+ 'AC3CON_AC3IE': '$40', # Analog Comparator 3 Interrupt
+ 'AC3CON_AC3IS': '$30', # Analog Comparator 3 Interrupt
+ 'AC3CON_AC3M': '$7', # Analog Comparator 3 Multiplexe
+ 'ACSR' : '$50', # Analog Comparator Status Regis
+ 'ACSR_AC3IF': '$80', # Analog Comparator 3 Interrupt
+ 'ACSR_AC2IF': '$40', # Analog Comparator 2 Interrupt
+ 'ACSR_AC1IF': '$20', # Analog Comparator 1 Interrupt
+ 'ACSR_AC0IF': '$10', # Analog Comparator 0 Interrupt
+ 'ACSR_AC3O': '$8', # Analog Comparator 3 Output Bit
+ 'ACSR_AC2O': '$4', # Analog Comparator 2 Output Bit
+ 'ACSR_AC1O': '$2', # Analog Comparator 1 Output Bit
+ 'ACSR_AC0O': '$1', # Analog Comparator 0 Output Bit
+
+# Module DA_CONVERTER
+ 'DACH' : '$92', # DAC Data Register High Byte
+ 'DACH_DACH': '$ff', # DAC Data Register High Byte Bi
+ 'DACL' : '$91', # DAC Data Register Low Byte
+ 'DACL_DACL': '$ff', # DAC Data Register Low Byte Bit
+ 'DACON' : '$90', # DAC Control Register
+ 'DACON_DAATE': '$80', # DAC Auto Trigger Enable Bit
+ 'DACON_DATS': '$70', # DAC Trigger Selection Bits
+ 'DACON_DALA': '$4', # DAC Left Adjust
+ 'DACON_DAEN': '$1', # DAC Enable Bit
+
+# Module CPU
+ 'SPMCSR' : '$57', # Store Program Memory Control R
+ 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
+ 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
+ 'SPMCSR_SIGRD': '$20', # Signature Row Read
+ 'SPMCSR_RWWSRE': '$10', # Read While Write section read
+ 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
+ 'SPMCSR_PGWRT': '$4', # Page Write
+ 'SPMCSR_PGERS': '$2', # Page Erase
+ 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
+ 'SREG' : '$5f', # Status Register
+ 'SREG_I': '$80', # Global Interrupt Enable
+ 'SREG_T': '$40', # Bit Copy Storage
+ 'SREG_H': '$20', # Half Carry Flag
+ 'SREG_S': '$10', # Sign Bit
+ 'SREG_V': '$8', # Two's Complement Overflow Flag
+ 'SREG_N': '$4', # Negative Flag
+ 'SREG_Z': '$2', # Zero Flag
+ 'SREG_C': '$1', # Carry Flag
+ 'SP' : '$5d', # Stack Pointer
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_SPIPS': '$80', # SPI Pin Select
+ 'MCUCR_PUD': '$10', # Pull-up disable
+ 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
+ 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
+ 'MCUSR_BORF': '$4', # Brown-out Reset Flag
+ 'MCUSR_EXTRF': '$2', # External Reset Flag
+ 'MCUSR_PORF': '$1', # Power-on reset flag
+ 'OSCCAL' : '$66', # Oscillator Calibration Value
+ 'CLKPR' : '$61', #
+ 'CLKPR_CLKPCE': '$80', #
+ 'CLKPR_CLKPS': '$f', #
+ 'SMCR' : '$53', # Sleep Mode Control Register
+ 'SMCR_SM': '$e', # Sleep Mode Select bits
+ 'SMCR_SE': '$1', # Sleep Enable
+ 'GPIOR2' : '$3a', # General Purpose IO Register 2
+ 'GPIOR2_GPIOR': '$ff', # General Purpose IO Register 2
+ 'GPIOR1' : '$39', # General Purpose IO Register 1
+ 'GPIOR1_GPIOR': '$ff', # General Purpose IO Register 1
+ 'GPIOR0' : '$3e', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR07': '$80', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR06': '$40', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR05': '$20', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR04': '$10', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR03': '$8', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR02': '$4', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR01': '$2', # General Purpose IO Register 0
+ 'GPIOR0_GPIOR00': '$1', # General Purpose IO Register 0
+ 'PLLCSR' : '$49', # PLL Control And Status Registe
+ 'PLLCSR_PLLF': '$4', # PLL Factor
+ 'PLLCSR_PLLE': '$2', # PLL Enable
+ 'PLLCSR_PLOCK': '$1', # PLL Lock Detector
+ 'PRR' : '$64', # Power Reduction Register
+ 'PRR_PRCAN': '$40', # Power Reduction CAN
+ 'PRR_PRPSC': '$20', # Power Reduction PSC
+ 'PRR_PRTIM1': '$10', # Power Reduction Timer/Counter1
+ 'PRR_PRTIM0': '$8', # Power Reduction Timer/Counter0
+ 'PRR_PRSPI': '$4', # Power Reduction Serial Periphe
+ 'PRR_PRLIN': '$2', # Power Reduction LIN UART
+ 'PRR_PRADC': '$1', # Power Reduction ADC
+
+# Module PORTE
+ 'PORTE' : '$2e', # Port E Data Register
+ 'DDRE' : '$2d', # Port E Data Direction Register
+ 'PINE' : '$2c', # Port E Input Pins
+
+# Module TIMER_COUNTER_0
+ 'TIMSK0' : '$6e', # Timer/Counter0 Interrupt Mask
+ 'TIMSK0_OCIE0B': '$4', # Timer/Counter0 Output Compare
+ 'TIMSK0_OCIE0A': '$2', # Timer/Counter0 Output Compare
+ 'TIMSK0_TOIE0': '$1', # Timer/Counter0 Overflow Interr
+ 'TIFR0' : '$35', # Timer/Counter0 Interrupt Flag
+ 'TIFR0_OCF0B': '$4', # Timer/Counter0 Output Compare
+ 'TIFR0_OCF0A': '$2', # Timer/Counter0 Output Compare
+ 'TIFR0_TOV0': '$1', # Timer/Counter0 Overflow Flag
+ 'TCCR0A' : '$44', # Timer/Counter Control Registe
+ 'TCCR0A_COM0A': '$c0', # Compare Output Mode, Phase Cor
+ 'TCCR0A_COM0B': '$30', # Compare Output Mode, Fast PWm
+ 'TCCR0A_WGM0': '$3', # Waveform Generation Mode
+ 'TCCR0B' : '$45', # Timer/Counter Control Register
+ 'TCCR0B_FOC0A': '$80', # Force Output Compare A
+ 'TCCR0B_FOC0B': '$40', # Force Output Compare B
+ 'TCCR0B_WGM02': '$8', #
+ 'TCCR0B_CS0': '$7', # Clock Select
+ 'TCNT0' : '$46', # Timer/Counter0
+ 'OCR0A' : '$47', # Timer/Counter0 Output Compare
+ 'OCR0B' : '$48', # Timer/Counter0 Output Compare
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_ICPSEL1': '$40', # Timer1 Input Capture Selection
+ 'GTCCR_PSR10': '$1', # Prescaler Reset Timer/Counter1
+
+# Module TIMER_COUNTER_1
+ 'TIMSK1' : '$6f', # Timer/Counter Interrupt Mask R
+ 'TIMSK1_ICIE1': '$20', # Timer/Counter1 Input Capture I
+ 'TIMSK1_OCIE1B': '$4', # Timer/Counter1 Output CompareB
+ 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output CompareA
+ 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
+ 'TIFR1' : '$36', # Timer/Counter Interrupt Flag r
+ 'TIFR1_ICF1': '$20', # Input Capture Flag 1
+ 'TIFR1_OCF1B': '$4', # Output Compare Flag 1B
+ 'TIFR1_OCF1A': '$2', # Output Compare Flag 1A
+ 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
+ 'TCCR1A' : '$80', # Timer/Counter1 Control Registe
+ 'TCCR1A_COM1A': '$c0', # Compare Output Mode 1A, bits
+ 'TCCR1A_COM1B': '$30', # Compare Output Mode 1B, bits
+ 'TCCR1A_WGM1': '$3', # Waveform Generation Mode
+ 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
+ 'TCCR1B_ICNC1': '$80', # Input Capture 1 Noise Canceler
+ 'TCCR1B_ICES1': '$40', # Input Capture 1 Edge Select
+ 'TCCR1B_WGM1': '$18', # Waveform Generation Mode
+ 'TCCR1B_CS1': '$7', # Prescaler source of Timer/Coun
+ 'TCCR1C' : '$82', # Timer/Counter1 Control Registe
+ 'TCCR1C_FOC1A': '$80', #
+ 'TCCR1C_FOC1B': '$40', #
+ 'TCNT1' : '$84', # Timer/Counter1 Bytes
+ 'OCR1A' : '$88', # Timer/Counter1 Output Compare
+ 'OCR1B' : '$8a', # Timer/Counter1 Output Compare
+ 'ICR1' : '$86', # Timer/Counter1 Input Capture R
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSRSYNC': '$1', # Prescaler Reset Timer/Counter1
+
+# Module AD_CONVERTER
+ 'ADMUX' : '$7c', # The ADC multiplexer Selection
+ 'ADMUX_REFS': '$c0', # Reference Selection Bits
+ 'ADMUX_ADLAR': '$20', # Left Adjust Result
+ 'ADMUX_MUX': '$1f', # Analog Channel and Gain Select
+ 'ADCSRA' : '$7a', # The ADC Control and Status reg
+ 'ADCSRA_ADEN': '$80', # ADC Enable
+ 'ADCSRA_ADSC': '$40', # ADC Start Conversion
+ 'ADCSRA_ADATE': '$20', # ADC Auto Trigger Enable
+ 'ADCSRA_ADIF': '$10', # ADC Interrupt Flag
+ 'ADCSRA_ADIE': '$8', # ADC Interrupt Enable
+ 'ADCSRA_ADPS': '$7', # ADC Prescaler Select Bits
+ 'ADC' : '$78', # ADC Data Register Bytes
+ 'ADCSRB' : '$7b', # ADC Control and Status Registe
+ 'ADCSRB_ADHSM': '$80', # ADC High Speed Mode
+ 'ADCSRB_ISRCEN': '$40', # Current Source Enable
+ 'ADCSRB_AREFEN': '$20', # Analog Reference pin Enable
+ 'ADCSRB_ADTS': '$f', # ADC Auto Trigger Sources
+ 'DIDR0' : '$7e', # Digital Input Disable Register
+ 'DIDR0_ADC7D': '$80', # ADC7 Digital input Disable
+ 'DIDR0_ADC6D': '$40', # ADC6 Digital input Disable
+ 'DIDR0_ADC5D': '$20', # ADC5 Digital input Disable
+ 'DIDR0_ADC4D': '$10', # ADC4 Digital input Disable
+ 'DIDR0_ADC3D': '$8', # ADC3 Digital input Disable
+ 'DIDR0_ADC2D': '$4', # ADC2 Digital input Disable
+ 'DIDR0_ADC1D': '$2', # ADC1 Digital input Disable
+ 'DIDR0_ADC0D': '$1', # ADC0 Digital input Disable
+ 'DIDR1' : '$7f', # Digital Input Disable Register
+ 'DIDR1_AMP2PD': '$40', # AMP2P Pin Digital input Disabl
+ 'DIDR1_ACMP0D': '$20', # ACMP0 Pin Digital input Disabl
+ 'DIDR1_AMP0PD': '$10', # AMP0P Pin Digital input Disabl
+ 'DIDR1_AMP0ND': '$8', # AMP0N Pin Digital input Disabl
+ 'DIDR1_ADC10D': '$4', # ADC10 Pin Digital input Disabl
+ 'DIDR1_ADC9D': '$2', # ADC9 Pin Digital input Disable
+ 'DIDR1_ADC8D': '$1', # ADC8 Pin Digital input Disable
+ 'AMP0CSR' : '$75', #
+ 'AMP0CSR_AMP0EN': '$80', #
+ 'AMP0CSR_AMP0IS': '$40', #
+ 'AMP0CSR_AMP0G': '$30', #
+ 'AMP0CSR_AMPCMP0': '$8', # Amplifier 0 - Comparator 0 Con
+ 'AMP0CSR_AMP0TS': '$7', #
+ 'AMP1CSR' : '$76', #
+ 'AMP1CSR_AMP1EN': '$80', #
+ 'AMP1CSR_AMP1IS': '$40', #
+ 'AMP1CSR_AMP1G': '$30', #
+ 'AMP1CSR_AMPCMP1': '$8', # Amplifier 1 - Comparator 1 Con
+ 'AMP1CSR_AMP1TS': '$7', #
+ 'AMP2CSR' : '$77', #
+ 'AMP2CSR_AMP2EN': '$80', #
+ 'AMP2CSR_AMP2IS': '$40', #
+ 'AMP2CSR_AMP2G': '$30', #
+ 'AMP2CSR_AMPCMP2': '$8', # Amplifier 2 - Comparator 2 Con
+ 'AMP2CSR_AMP2TS': '$7', #
+
+# Module LINUART
+ 'LINCR' : '$c8', # LIN Control Register
+ 'LINCR_LSWRES': '$80', # Software Reset
+ 'LINCR_LIN13': '$40', # LIN Standard
+ 'LINCR_LCONF': '$30', # LIN Configuration bits
+ 'LINCR_LENA': '$8', # LIN or UART Enable
+ 'LINCR_LCMD': '$7', # LIN Command and Mode bits
+ 'LINSIR' : '$c9', # LIN Status and Interrupt Regis
+ 'LINSIR_LIDST': '$e0', # Identifier Status bits
+ 'LINSIR_LBUSY': '$10', # Busy Signal
+ 'LINSIR_LERR': '$8', # Error Interrupt
+ 'LINSIR_LIDOK': '$4', # Identifier Interrupt
+ 'LINSIR_LTXOK': '$2', # Transmit Performed Interrupt
+ 'LINSIR_LRXOK': '$1', # Receive Performed Interrupt
+ 'LINENIR' : '$ca', # LIN Enable Interrupt Register
+ 'LINENIR_LENERR': '$8', # Enable Error Interrupt
+ 'LINENIR_LENIDOK': '$4', # Enable Identifier Interrupt
+ 'LINENIR_LENTXOK': '$2', # Enable Transmit Performed Inte
+ 'LINENIR_LENRXOK': '$1', # Enable Receive Performed Inter
+ 'LINERR' : '$cb', # LIN Error Register
+ 'LINERR_LABORT': '$80', # Abort Flag
+ 'LINERR_LTOERR': '$40', # Frame Time Out Error Flag
+ 'LINERR_LOVERR': '$20', # Overrun Error Flag
+ 'LINERR_LFERR': '$10', # Framing Error Flag
+ 'LINERR_LSERR': '$8', # Synchronization Error Flag
+ 'LINERR_LPERR': '$4', # Parity Error Flag
+ 'LINERR_LCERR': '$2', # Checksum Error Flag
+ 'LINERR_LBERR': '$1', # Bit Error Flag
+ 'LINBTR' : '$cc', # LIN Bit Timing Register
+ 'LINBTR_LDISR': '$80', # Disable Bit Timing Resynchroni
+ 'LINBTR_LBT': '$3f', # LIN Bit Timing bits
+ 'LINBRRL' : '$cd', # LIN Baud Rate Low Register
+ 'LINBRRL_LDIV': '$ff', #
+ 'LINBRRH' : '$ce', # LIN Baud Rate High Register
+ 'LINBRRH_LDIV': '$f', #
+ 'LINDLR' : '$cf', # LIN Data Length Register
+ 'LINDLR_LTXDL': '$f0', # LIN Transmit Data Length bits
+ 'LINDLR_LRXDL': '$f', # LIN Receive Data Length bits
+ 'LINIDR' : '$d0', # LIN Identifier Register
+ 'LINIDR_LP': '$c0', # Parity bits
+ 'LINIDR_LID': '$3f', # Identifier bit 5 or Data Lengt
+ 'LINSEL' : '$d1', # LIN Data Buffer Selection Regi
+ 'LINSEL_LAINC': '$8', # Auto Increment of Data Buffer
+ 'LINSEL_LINDX': '$7', # FIFO LIN Data Buffer Index bit
+ 'LINDAT' : '$d2', # LIN Data Register
+ 'LINDAT_LDATA': '$ff', #
+
+# Module SPI
+ 'SPCR' : '$4c', # SPI Control Register
+ 'SPCR_SPIE': '$80', # SPI Interrupt Enable
+ 'SPCR_SPE': '$40', # SPI Enable
+ 'SPCR_DORD': '$20', # Data Order
+ 'SPCR_MSTR': '$10', # Master/Slave Select
+ 'SPCR_CPOL': '$8', # Clock polarity
+ 'SPCR_CPHA': '$4', # Clock Phase
+ 'SPCR_SPR': '$3', # SPI Clock Rate Selects
+ 'SPSR' : '$4d', # SPI Status Register
+ 'SPSR_SPIF': '$80', # SPI Interrupt Flag
+ 'SPSR_WCOL': '$40', # Write Collision Flag
+ 'SPSR_SPI2X': '$1', # Double SPI Speed Bit
+ 'SPDR' : '$4e', # SPI Data Register
+
+# Module WATCHDOG
+ 'WDTCSR' : '$60', # Watchdog Timer Control Registe
+ 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
+ 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
+ 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
+ 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
+ 'WDTCSR_WDE': '$8', # Watch Dog Enable
+
+# Module EXTERNAL_INTERRUPT
+ 'EICRA' : '$69', # External Interrupt Control Reg
+ 'EICRA_ISC3': '$c0', # External Interrupt Sense Contr
+ 'EICRA_ISC2': '$30', # External Interrupt Sense Contr
+ 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
+ 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
+ 'EIMSK' : '$3d', # External Interrupt Mask Regist
+ 'EIMSK_INT': '$f', # External Interrupt Request 3 E
+ 'EIFR' : '$3c', # External Interrupt Flag Regist
+ 'EIFR_INTF': '$f', # External Interrupt Flags
+ 'PCICR' : '$68', # Pin Change Interrupt Control R
+ 'PCICR_PCIE': '$f', # Pin Change Interrupt Enables
+ 'PCMSK3' : '$6d', # Pin Change Mask Register 3
+ 'PCMSK3_PCINT': '$7', # Pin Change Enable Masks
+ 'PCMSK2' : '$6c', # Pin Change Mask Register 2
+ 'PCMSK2_PCINT': '$ff', # Pin Change Enable Masks
+ 'PCMSK1' : '$6b', # Pin Change Mask Register 1
+ 'PCMSK1_PCINT': '$ff', # Pin Change Enable Masks
+ 'PCMSK0' : '$6a', # Pin Change Mask Register 0
+ 'PCMSK0_PCINT': '$ff', # Pin Change Enable Masks
+ 'PCIFR' : '$3b', # Pin Change Interrupt Flag Regi
+ 'PCIFR_PCIF': '$f', # Pin Change Interrupt Flags
+
+# Module EEPROM
+ 'EEAR' : '$41', # EEPROM Read/Write Access
+ 'EEDR' : '$40', # EEPROM Data Register
+ 'EECR' : '$3f', # EEPROM Control Register
+ 'EECR_EEPM': '$30', #
+ 'EECR_EERIE': '$8', # EEProm Ready Interrupt Enable
+ 'EECR_EEMWE': '$4', # EEPROM Master Write Enable
+ 'EECR_EEWE': '$2', # EEPROM Write Enable
+ 'EECR_EERE': '$1', # EEPROM Read Enable
+
+ '__amforth_dummy':'0'
+}
diff --git a/amforth-6.5/avr8/devices/atmega32c1/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega32c1/words/no-jtag.asm
new file mode 100644
index 0000000..352a4bb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega32c1/words/no-jtag.asm
@@ -0,0 +1,14 @@
+; ( -- )
+; ( -- )
+; MCU
+; disable jtag at runtime
+VE_NOJTAG:
+ .dw $FF05
+ .db "-jtag",0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOJTAG
+XT_NOJTAG:
+ .dw PFA_NOJTAG
+PFA_NOJTAG:
+
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega32c1/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega32c1/words/no-wdt.asm
new file mode 100644
index 0000000..ff6ddd1
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega32c1/words/no-wdt.asm
@@ -0,0 +1,34 @@
+; ( -- )
+; MCU
+; disable watch dog timer at runtime
+VE_NOWDT:
+ .dw $ff04
+ .db "-wdt"
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOWDT
+XT_NOWDT:
+ .dw PFA_NOWDT
+PFA_NOWDT:
+
+ in temp1,SREG
+ push temp1
+ ; Turn always off global interrupt.
+ cli
+ ; Reset Watchdog Timer
+ wdr
+ ; Clear WDRF in MCUSR
+ in temp1, MCUSR
+ andi temp1, (0xff & (0<<WDRF))
+ out MCUSR, temp1
+ ; Write logical one to WDCE and WDE
+ ; Keep old prescaler setting to prevent unintentional time-out
+ in_ temp1, WDTCSR
+ ori temp1, (1<<WDCE) | (1<<WDE)
+ out_ WDTCSR, temp1
+ ; Turn off WDT
+ ldi temp1, (0<<WDE)
+ out_ WDTCSR, temp1
+ ; restore status register
+ pop temp1
+ out SREG,temp1
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega32c1/words/sleep.asm b/amforth-6.5/avr8/devices/atmega32c1/words/sleep.asm
new file mode 100644
index 0000000..256249c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega32c1/words/sleep.asm
@@ -0,0 +1,19 @@
+; ( mode -- )
+; MCU
+; put the controller into the specified sleep mode
+VE_SLEEP:
+ .dw $ff05
+ .db "sleep", 0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_SLEEP
+XT_SLEEP:
+ .dw PFA_SLEEP
+PFA_SLEEP:
+ andi tosl, 7 ; leave only legal mode bits
+ lsl tosl ; move to correct location (bits 3-1)
+ ori tosl, 1 ; set the SE bit
+ out_ SMCR, tosl ; set the sleep config
+ sleep ; nighty-night
+ out_ SMCR, zerol ; 0 protects against accidental sleeps
+ loadtos ; pop argument from stack
+ jmp_ DO_NEXT