aboutsummaryrefslogtreecommitdiff
path: root/amforth-6.5/avr8/devices/atmega406
diff options
context:
space:
mode:
authorDimitri Sokolyuk <demon@dim13.org>2017-08-19 12:15:28 +0200
committerDimitri Sokolyuk <demon@dim13.org>2017-08-19 12:15:28 +0200
commit67d25d837ac55f28a366c0a3b262e439a6e75fc3 (patch)
treedf7715c7724c5935ab87c807f3b8b4ef529315e3 /amforth-6.5/avr8/devices/atmega406
parente0d6784e89dba33226c0edb815bb974486fa7c48 (diff)
Add AmForth
Diffstat (limited to 'amforth-6.5/avr8/devices/atmega406')
-rw-r--r--amforth-6.5/avr8/devices/atmega406/atmega406.frt267
-rw-r--r--amforth-6.5/avr8/devices/atmega406/device.asm104
-rw-r--r--amforth-6.5/avr8/devices/atmega406/device.inc1008
-rw-r--r--amforth-6.5/avr8/devices/atmega406/device.py290
-rw-r--r--amforth-6.5/avr8/devices/atmega406/words/no-jtag.asm14
-rw-r--r--amforth-6.5/avr8/devices/atmega406/words/no-wdt.asm34
-rw-r--r--amforth-6.5/avr8/devices/atmega406/words/sleep.asm19
7 files changed, 1736 insertions, 0 deletions
diff --git a/amforth-6.5/avr8/devices/atmega406/atmega406.frt b/amforth-6.5/avr8/devices/atmega406/atmega406.frt
new file mode 100644
index 0000000..82320fb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega406/atmega406.frt
@@ -0,0 +1,267 @@
+\ Partname: ATmega406
+\ generated automatically
+
+\ AD_CONVERTER
+&124 constant VADMUX \ The VADC multiplexer Selection Register
+ $0F constant VADMUX_VADMUX \ Analog Channel and Gain Selection Bits
+&120 constant VADC \ VADC Data Register Bytes
+&122 constant VADCSR \ The VADC Control and Status register
+ $08 constant VADCSR_VADEN \ VADC Enable
+ $04 constant VADCSR_VADSC \ VADC Satrt Conversion
+ $02 constant VADCSR_VADCCIF \ VADC Conversion Complete Interrupt Flag
+ $01 constant VADCSR_VADCCIE \ VADC Conversion Complete Interrupt Enable
+\ EXTERNAL_INTERRUPT
+&105 constant EICRA \ External Interrupt Control Register
+ $C0 constant EICRA_ISC3 \ External Interrupt Sense Control 3 Bits
+ $30 constant EICRA_ISC2 \ External Interrupt Sense Control 2 Bits
+ $0C constant EICRA_ISC1 \ External Interrupt Sense Control 1 Bits
+ $03 constant EICRA_ISC0 \ External Interrupt Sense Control 0 Bits
+&61 constant EIMSK \ External Interrupt Mask Register
+ $0F constant EIMSK_INT \ External Interrupt Request 1 Enable
+&60 constant EIFR \ External Interrupt Flag Register
+ $0F constant EIFR_INTF \ External Interrupt Flags
+&104 constant PCICR \ Pin Change Interrupt Control Register
+ $03 constant PCICR_PCIE \ Pin Change Interrupt Enables
+&59 constant PCIFR \ Pin Change Interrupt Flag Register
+ $03 constant PCIFR_PCIF \ Pin Change Interrupt Flags
+&108 constant PCMSK1 \ Pin Change Enable Mask Register 1
+&107 constant PCMSK0 \ Pin Change Enable Mask Register 0
+\ TIMER_COUNTER_1
+&129 constant TCCR1B \ Timer/Counter1 Control Register B
+ $08 constant TCCR1B_CTC1 \ Clear Timer/Counter on Compare Match
+ $07 constant TCCR1B_CS1 \ Clock Select1 bits
+&132 constant TCNT1 \ Timer Counter 1 Bytes
+&136 constant OCR1AL \ Output Compare Register 1A Low byte
+&137 constant OCR1AH \ Output Compare Register 1A High byte
+&111 constant TIMSK1 \ Timer/Counter Interrupt Mask Register
+ $02 constant TIMSK1_OCIE1A \ Timer/Counter1 Output Compare Interrupt Enable
+ $01 constant TIMSK1_TOIE1 \ Timer/Counter1 Overflow Interrupt Enable
+&54 constant TIFR1 \ Timer/Counter Interrupt Flag register
+ $02 constant TIFR1_OCF1A \ Timer/Counter1 Output Compare Flag A
+ $01 constant TIFR1_TOV1 \ Timer/Counter1 Overflow Flag
+&67 constant GTCCR \ General Timer/Counter Control Register
+ $80 constant GTCCR_TSM \ Timer/Counter Synchronization Mode
+ $01 constant GTCCR_PSRSYNC \ Prescaler Reset
+\ WAKEUP_TIMER
+&98 constant WUTCSR \ Wake-up Timer Control Register
+ $80 constant WUTCSR_WUTIF \ Wake-up Timer Interrupt Flag
+ $40 constant WUTCSR_WUTIE \ Wake-up Timer Interrupt Enable
+ $20 constant WUTCSR_WUTCF \ Wake-up timer Calibration Flag
+ $10 constant WUTCSR_WUTR \ Wake-up Timer Reset
+ $08 constant WUTCSR_WUTE \ Wake-up Timer Enable
+ $07 constant WUTCSR_WUTP \ Wake-up Timer Prescaler Bits
+\ BATTERY_PROTECTION
+&248 constant BPPLR \ Battery Protection Parameter Lock Register
+ $02 constant BPPLR_BPPLE \ Battery Protection Parameter Lock Enable
+ $01 constant BPPLR_BPPL \ Battery Protection Parameter Lock
+&247 constant BPCR \ Battery Protection Control Register
+ $08 constant BPCR_DUVD \
+ $04 constant BPCR_SCD \
+ $02 constant BPCR_DCD \
+ $01 constant BPCR_CCD \
+&246 constant CBPTR \ Current Battery Protection Timing Register
+ $F0 constant CBPTR_SCPT \
+ $0F constant CBPTR_OCPT \
+&245 constant BPOCD \ Battery Protection OverCurrent Detection Level Register
+ $F0 constant BPOCD_DCDL \
+ $0F constant BPOCD_CCDL \
+&244 constant BPSCD \ Battery Protection Short-Circuit Detection Level Register
+ $0F constant BPSCD_SCDL \
+&243 constant BPDUV \ Battery Protection Deep Under Voltage Register
+ $30 constant BPDUV_DUVT \
+ $0F constant BPDUV_DUDL \
+&242 constant BPIR \ Battery Protection Interrupt Register
+ $80 constant BPIR_DUVIF \ Deep Under-voltage Early Warning Interrupt Flag
+ $40 constant BPIR_COCIF \ Charge Over-current Protection Activated Interrupt Flag
+ $20 constant BPIR_DOCIF \
+ $10 constant BPIR_SCIF \
+ $08 constant BPIR_DUVIE \ Deep Under-voltage Early Warning Interrupt Enable
+ $04 constant BPIR_COCIE \
+ $02 constant BPIR_DOCIE \
+ $01 constant BPIR_SCIE \
+\ FET
+&240 constant FCSR \
+ $20 constant FCSR_PWMOC \ Pulse Width Modulation of OC output
+ $10 constant FCSR_PWMOPC \ Pulse Width Modulation Modulation of OPC output
+ $08 constant FCSR_CPS \ Current Protection Status
+ $04 constant FCSR_DFE \ Discharge FET Enable
+ $02 constant FCSR_CFE \ Charge FET Enable
+ $01 constant FCSR_PFD \ Precharge FET disable
+\ COULOMB_COUNTER
+&228 constant CADCSRA \ CC-ADC Control and Status Register A
+ $80 constant CADCSRA_CADEN \ When the CADEN bit is cleared (zero), the CC-ADC is disabled. When the CADEN bit is set (one), the CC-ADC will continuously measure the voltage drop over the external sense resistor RSENSE. In Power-down, only the Regular Current detection is active. In Power-off, the CC-ADC is always disabled.
+ $20 constant CADCSRA_CADUB \ CC_ADC Update Busy
+ $18 constant CADCSRA_CADAS \ CC_ADC Accumulate Current Select Bits
+ $06 constant CADCSRA_CADSI \ The CADSI bits determine the current sampling interval for the Regular Current detection in Power-down mode. The actual settings remain to be determined.
+ $01 constant CADCSRA_CADSE \ When the CADSE bit is written to one, the ongoing CC-ADC conversion is aborted, and the CC-ADC enters Regular Current detection mode.
+&229 constant CADCSRB \ CC-ADC Control and Status Register B
+ $40 constant CADCSRB_CADACIE \
+ $20 constant CADCSRB_CADRCIE \ Regular Current Interrupt Enable
+ $10 constant CADCSRB_CADICIE \ CAD Instantenous Current Interrupt Enable
+ $04 constant CADCSRB_CADACIF \ CC-ADC Accumulate Current Interrupt Flag
+ $02 constant CADCSRB_CADRCIF \ CC-ADC Accumulate Current Interrupt Flag
+ $01 constant CADCSRB_CADICIF \ CC-ADC Instantaneous Current Interrupt Flag
+&232 constant CADIC \ CC-ADC Instantaneous Current
+&227 constant CADAC3 \ ADC Accumulate Current
+&226 constant CADAC2 \ ADC Accumulate Current
+&225 constant CADAC1 \ ADC Accumulate Current
+&224 constant CADAC0 \ ADC Accumulate Current
+&230 constant CADRCC \ CC-ADC Regular Charge Current
+&231 constant CADRDC \ CC-ADC Regular Discharge Current
+\ CELL_BALANCING
+&241 constant CBCR \ Cell Balancing Control Register
+ $0F constant CBCR_CBE \ Cell Balancing Enables
+\ CPU
+&95 constant SREG \ Status Register
+ $80 constant SREG_I \ Global Interrupt Enable
+ $40 constant SREG_T \ Bit Copy Storage
+ $20 constant SREG_H \ Half Carry Flag
+ $10 constant SREG_S \ Sign Bit
+ $08 constant SREG_V \ Two's Complement Overflow Flag
+ $04 constant SREG_N \ Negative Flag
+ $02 constant SREG_Z \ Zero Flag
+ $01 constant SREG_C \ Carry Flag
+&93 constant SP \ Stack Pointer
+&85 constant MCUCR \ MCU Control Register
+ $80 constant MCUCR_JTD \ JTAG Disable
+ $10 constant MCUCR_PUD \ Pull-up disable
+ $02 constant MCUCR_IVSEL \ Interrupt Vector Select
+ $01 constant MCUCR_IVCE \ Interrupt Vector Change Enable
+&84 constant MCUSR \ MCU Status Register
+ $10 constant MCUSR_JTRF \ JTAG Reset Flag
+ $08 constant MCUSR_WDRF \ Watchdog Reset Flag
+ $04 constant MCUSR_BODRF \ Brown-out Reset Flag
+ $02 constant MCUSR_EXTRF \ External Reset Flag
+ $01 constant MCUSR_PORF \ Power-on reset flag
+&102 constant FOSCCAL \ Fast Oscillator Calibration Value
+&83 constant SMCR \ Sleep Mode Control Register
+ $0E constant SMCR_SM \ Sleep Mode Select bits
+ $01 constant SMCR_SE \ Sleep Enable
+&75 constant GPIOR2 \ General Purpose IO Register 2
+&74 constant GPIOR1 \ General Purpose IO Register 1
+&62 constant GPIOR0 \ General Purpose IO Register 0
+&192 constant CCSR \ Clock Control and Status Register
+ $02 constant CCSR_XOE \ 32 kHz Crystal Oscillator Enable
+ $01 constant CCSR_ACS \ Asynchronous Clock Select
+&126 constant DIDR0 \ Digital Input Disable Register
+&100 constant PRR0 \ Power Reduction Register 0
+ $08 constant PRR0_PRTWI \ Power Reduction TWI
+ $04 constant PRR0_PRTIM1 \ Power Reduction Timer/Counter1
+ $02 constant PRR0_PRTIM0 \ Power Reduction Timer/Counter0
+ $01 constant PRR0_PRVADC \ Power Reduction V-ADC
+\ WATCHDOG
+&96 constant WDTCSR \ Watchdog Timer Control Register
+ $80 constant WDTCSR_WDIF \ Watchdog Timeout Interrupt Flag
+ $40 constant WDTCSR_WDIE \ Watchdog Timeout Interrupt Enable
+ $27 constant WDTCSR_WDP \ Watchdog Timer Prescaler Bits
+ $10 constant WDTCSR_WDCE \ Watchdog Change Enable
+ $08 constant WDTCSR_WDE \ Watch Dog Enable
+\ TIMER_COUNTER_0
+&68 constant TCCR0A \ Timer/Counter0 Control Register
+ $C0 constant TCCR0A_COM0A \ Force Output Compare
+ $30 constant TCCR0A_COM0B \
+ $03 constant TCCR0A_WGM0 \ Clock Select0 bits
+&69 constant TCCR0B \ Timer/Counter0 Control Register
+ $80 constant TCCR0B_FOC0A \ Force Output Compare
+ $40 constant TCCR0B_FOC0B \ Waveform Generation Mode
+ $08 constant TCCR0B_WGM02 \
+ $07 constant TCCR0B_CS0 \ Clock Select0 bits
+&70 constant TCNT0 \ Timer Counter 0
+&71 constant OCR0A \ Output compare Register A
+ $FF constant OCR0A_OCR0A \
+&72 constant OCR0B \ Output compare Register B
+ $FF constant OCR0B_OCR0B \
+&110 constant TIMSK0 \ Timer/Counter Interrupt Mask Register
+ $04 constant TIMSK0_OCIE0B \ Output Compare Interrupt Enable
+ $02 constant TIMSK0_OCIE0A \ Output Compare Interrupt Enable
+ $01 constant TIMSK0_TOIE0 \ Overflow Interrupt Enable
+&53 constant TIFR0 \ Timer/Counter Interrupt Flag register
+ $04 constant TIFR0_OCF0B \ Output Compare Flag
+ $02 constant TIFR0_OCF0A \ Output Compare Flag
+ $01 constant TIFR0_TOV0 \ Overflow Flag
+\ PORTA
+&34 constant PORTA \ Port A Data Register
+&33 constant DDRA \ Port A Data Direction Register
+&32 constant PINA \ Port A Input Pins
+\ PORTB
+&37 constant PORTB \ Port B Data Register
+&36 constant DDRB \ Port B Data Direction Register
+&35 constant PINB \ Port B Input Pins
+\ PORTC
+&40 constant PORTC \ Port C Data Register
+\ PORTD
+&43 constant PORTD \ Data Register, Port D
+&42 constant DDRD \ Data Direction Register, Port D
+&41 constant PIND \ Input Pins, Port D
+\ BOOT_LOAD
+&87 constant SPMCSR \ Store Program Memory Control Register
+ $80 constant SPMCSR_SPMIE \ SPM Interrupt Enable
+ $40 constant SPMCSR_RWWSB \ Read While Write Section Busy
+ $20 constant SPMCSR_SIGRD \ Signature Row Read
+ $10 constant SPMCSR_RWWSRE \ Read While Write section read enable
+ $08 constant SPMCSR_BLBSET \ Boot Lock Bit Set
+ $04 constant SPMCSR_PGWRT \ Page Write
+ $02 constant SPMCSR_PGERS \ Page Erase
+ $01 constant SPMCSR_SPMEN \ Store Program Memory Enable
+\ TWI
+&190 constant TWBCSR \ TWI Bus Control and Status Register
+ $80 constant TWBCSR_TWBCIF \ TWI Bus Connect/Disconnect Interrupt Flag
+ $40 constant TWBCSR_TWBCIE \ TWI Bus Connect/Disconnect Interrupt Enable
+ $06 constant TWBCSR_TWBDT \ TWI Bus Disconnect Time-out Period
+ $01 constant TWBCSR_TWBCIP \ TWI Bus Connect/Disconnect Interrupt Polarity
+&189 constant TWAMR \ TWI (Slave) Address Mask Register
+ $FE constant TWAMR_TWAM \
+&184 constant TWBR \ TWI Bit Rate register
+&188 constant TWCR \ TWI Control Register
+ $80 constant TWCR_TWINT \ TWI Interrupt Flag
+ $40 constant TWCR_TWEA \ TWI Enable Acknowledge Bit
+ $20 constant TWCR_TWSTA \ TWI Start Condition Bit
+ $10 constant TWCR_TWSTO \ TWI Stop Condition Bit
+ $08 constant TWCR_TWWC \ TWI Write Collition Flag
+ $04 constant TWCR_TWEN \ TWI Enable Bit
+ $01 constant TWCR_TWIE \ TWI Interrupt Enable
+&185 constant TWSR \ TWI Status Register
+ $F8 constant TWSR_TWS \ TWI Status
+ $03 constant TWSR_TWPS \ TWI Prescaler
+&187 constant TWDR \ TWI Data register
+&186 constant TWAR \ TWI (Slave) Address register
+ $FE constant TWAR_TWA \ TWI (Slave) Address register Bits
+ $01 constant TWAR_TWGCE \ TWI General Call Recognition Enable Bit
+\ BANDGAP
+&209 constant BGCRR \ Bandgap Calibration of Resistor Ladder
+&208 constant BGCCR \ Bandgap Calibration Register
+ $80 constant BGCCR_BGD \ Setting the BGD bit to one will disable the bandgap voltage reference. This bit must be cleared before enabling CC-ADC or V-ADC, and must remain unset while either ADC is enabled.
+ $3F constant BGCCR_BGCC \ BG Calibration of PTAT Current Bits
+\ EEPROM
+&65 constant EEAR \ EEPROM Address Register Bytes
+&64 constant EEDR \ EEPROM Data Register
+&63 constant EECR \ EEPROM Control Register
+ $30 constant EECR_EEPM \ EEPROM Programming Mode Bits
+ $08 constant EECR_EERIE \ EEPROM Ready Interrupt Enable
+ $04 constant EECR_EEMPE \ EEPROM Master Programming Enable
+ $02 constant EECR_EEPE \ EEPROM Programming Enable
+ $01 constant EECR_EERE \ EEPROM Read Enable
+
+\ Interrupts
+&2 constant BPINTAddr \ Battery Protection Interrupt
+&4 constant INT0Addr \ External Interrupt Request 0
+&6 constant INT1Addr \ External Interrupt Request 1
+&8 constant INT2Addr \ External Interrupt Request 2
+&10 constant INT3Addr \ External Interrupt Request 3
+&12 constant PCINT0Addr \ Pin Change Interrupt 0
+&14 constant PCINT1Addr \ Pin Change Interrupt 1
+&16 constant WDTAddr \ Watchdog Timeout Interrupt
+&18 constant WAKE_UPAddr \ Wakeup timer overflow
+&20 constant TIM1_COMPAddr \ Timer/Counter 1 Compare Match
+&22 constant TIM1_OVFAddr \ Timer/Counter 1 Overflow
+&24 constant TIM0_COMPAAddr \ Timer/Counter0 Compare A Match
+&26 constant TIM0_COMPBAddr \ Timer/Counter0 Compare B Match
+&28 constant TIM0_OVFAddr \ Timer/Counter0 Overflow
+&30 constant TWI_BUS_CDAddr \ Two-Wire Bus Connect/Disconnect
+&32 constant TWIAddr \ Two-Wire Serial Interface
+&34 constant VADCAddr \ Voltage ADC Conversion Complete
+&36 constant CCADC_CONVAddr \ Coulomb Counter ADC Conversion Complete
+&38 constant CCADC_REG_CURAddr \ Coloumb Counter ADC Regular Current
+&40 constant CCADC_ACCAddr \ Coloumb Counter ADC Accumulator
+&42 constant EE_READYAddr \ EEPROM Ready
+&44 constant SPM_READYAddr \ Store Program Memory Ready
diff --git a/amforth-6.5/avr8/devices/atmega406/device.asm b/amforth-6.5/avr8/devices/atmega406/device.asm
new file mode 100644
index 0000000..bce90e4
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega406/device.asm
@@ -0,0 +1,104 @@
+; Partname: ATmega406
+; generated automatically, do not edit
+
+.nolist
+ .include "m406def.inc"
+.list
+
+.equ ramstart = 256
+.equ CELLSIZE = 2
+.macro readflashcell
+ lsl zl
+ rol zh
+ lpm @0, Z+
+ lpm @1, Z+
+.endmacro
+.macro writeflashcell
+ lsl zl
+ rol zh
+.endmacro
+.set WANT_AD_CONVERTER = 0
+.set WANT_EXTERNAL_INTERRUPT = 0
+.set WANT_TIMER_COUNTER_1 = 0
+.set WANT_WAKEUP_TIMER = 0
+.set WANT_BATTERY_PROTECTION = 0
+.set WANT_FET = 0
+.set WANT_COULOMB_COUNTER = 0
+.set WANT_CELL_BALANCING = 0
+.set WANT_CPU = 0
+.set WANT_WATCHDOG = 0
+.set WANT_TIMER_COUNTER_0 = 0
+.set WANT_PORTA = 0
+.set WANT_PORTB = 0
+.set WANT_PORTC = 0
+.set WANT_PORTD = 0
+.set WANT_BOOT_LOAD = 0
+.set WANT_TWI = 0
+.set WANT_BANDGAP = 0
+.set WANT_EEPROM = 0
+.equ intvecsize = 2 ; please verify; flash size: 40960 bytes
+.equ pclen = 2 ; please verify
+.overlap
+.org 2
+ rcall isr ; Battery Protection Interrupt
+.org 4
+ rcall isr ; External Interrupt Request 0
+.org 6
+ rcall isr ; External Interrupt Request 1
+.org 8
+ rcall isr ; External Interrupt Request 2
+.org 10
+ rcall isr ; External Interrupt Request 3
+.org 12
+ rcall isr ; Pin Change Interrupt 0
+.org 14
+ rcall isr ; Pin Change Interrupt 1
+.org 16
+ rcall isr ; Watchdog Timeout Interrupt
+.org 18
+ rcall isr ; Wakeup timer overflow
+.org 20
+ rcall isr ; Timer/Counter 1 Compare Match
+.org 22
+ rcall isr ; Timer/Counter 1 Overflow
+.org 24
+ rcall isr ; Timer/Counter0 Compare A Match
+.org 26
+ rcall isr ; Timer/Counter0 Compare B Match
+.org 28
+ rcall isr ; Timer/Counter0 Overflow
+.org 30
+ rcall isr ; Two-Wire Bus Connect/Disconnect
+.org 32
+ rcall isr ; Two-Wire Serial Interface
+.org 34
+ rcall isr ; Voltage ADC Conversion Complete
+.org 36
+ rcall isr ; Coulomb Counter ADC Conversion Complete
+.org 38
+ rcall isr ; Coloumb Counter ADC Regular Current
+.org 40
+ rcall isr ; Coloumb Counter ADC Accumulator
+.org 42
+ rcall isr ; EEPROM Ready
+.org 44
+ rcall isr ; Store Program Memory Ready
+.equ INTVECTORS = 23
+.nooverlap
+
+; compatability layer (maybe empty)
+
+; controller data area, environment query mcu-info
+mcu_info:
+mcu_ramsize:
+ .dw 2048
+mcu_eepromsize:
+ .dw 512
+mcu_maxdp:
+ .dw 36864
+mcu_numints:
+ .dw 23
+mcu_name:
+ .dw 9
+ .db "ATmega406",0
+.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega406/device.inc b/amforth-6.5/avr8/devices/atmega406/device.inc
new file mode 100644
index 0000000..aa01e8d
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega406/device.inc
@@ -0,0 +1,1008 @@
+; Partname: ATmega406
+; generated automatically, no not edit
+
+.if WANT_AD_CONVERTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; The VADC multiplexer Selection Register
+VE_VADMUX:
+ .dw $ff06
+ .db "VADMUX"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_VADMUX
+XT_VADMUX:
+ .dw PFA_DOVARIABLE
+PFA_VADMUX:
+ .dw 124
+; ( -- addr ) System Constant
+; R( -- )
+; VADC Data Register Bytes
+VE_VADC:
+ .dw $ff04
+ .db "VADC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_VADC
+XT_VADC:
+ .dw PFA_DOVARIABLE
+PFA_VADC:
+ .dw 120
+; ( -- addr ) System Constant
+; R( -- )
+; The VADC Control and Status register
+VE_VADCSR:
+ .dw $ff06
+ .db "VADCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_VADCSR
+XT_VADCSR:
+ .dw PFA_DOVARIABLE
+PFA_VADCSR:
+ .dw 122
+
+.endif
+.if WANT_EXTERNAL_INTERRUPT == 1
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Control Register
+VE_EICRA:
+ .dw $ff05
+ .db "EICRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EICRA
+XT_EICRA:
+ .dw PFA_DOVARIABLE
+PFA_EICRA:
+ .dw 105
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Mask Register
+VE_EIMSK:
+ .dw $ff05
+ .db "EIMSK",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIMSK
+XT_EIMSK:
+ .dw PFA_DOVARIABLE
+PFA_EIMSK:
+ .dw 61
+; ( -- addr ) System Constant
+; R( -- )
+; External Interrupt Flag Register
+VE_EIFR:
+ .dw $ff04
+ .db "EIFR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EIFR
+XT_EIFR:
+ .dw PFA_DOVARIABLE
+PFA_EIFR:
+ .dw 60
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Interrupt Control Register
+VE_PCICR:
+ .dw $ff05
+ .db "PCICR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCICR
+XT_PCICR:
+ .dw PFA_DOVARIABLE
+PFA_PCICR:
+ .dw 104
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Interrupt Flag Register
+VE_PCIFR:
+ .dw $ff05
+ .db "PCIFR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCIFR
+XT_PCIFR:
+ .dw PFA_DOVARIABLE
+PFA_PCIFR:
+ .dw 59
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Enable Mask Register 1
+VE_PCMSK1:
+ .dw $ff06
+ .db "PCMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK1
+XT_PCMSK1:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK1:
+ .dw 108
+; ( -- addr ) System Constant
+; R( -- )
+; Pin Change Enable Mask Register 0
+VE_PCMSK0:
+ .dw $ff06
+ .db "PCMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PCMSK0
+XT_PCMSK0:
+ .dw PFA_DOVARIABLE
+PFA_PCMSK0:
+ .dw 107
+
+.endif
+.if WANT_TIMER_COUNTER_1 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter1 Control Register B
+VE_TCCR1B:
+ .dw $ff06
+ .db "TCCR1B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR1B
+XT_TCCR1B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR1B:
+ .dw 129
+; ( -- addr ) System Constant
+; R( -- )
+; Timer Counter 1 Bytes
+VE_TCNT1:
+ .dw $ff05
+ .db "TCNT1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT1
+XT_TCNT1:
+ .dw PFA_DOVARIABLE
+PFA_TCNT1:
+ .dw 132
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare Register 1A Low byte
+VE_OCR1AL:
+ .dw $ff06
+ .db "OCR1AL"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1AL
+XT_OCR1AL:
+ .dw PFA_DOVARIABLE
+PFA_OCR1AL:
+ .dw 136
+; ( -- addr ) System Constant
+; R( -- )
+; Output Compare Register 1A High byte
+VE_OCR1AH:
+ .dw $ff06
+ .db "OCR1AH"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR1AH
+XT_OCR1AH:
+ .dw PFA_DOVARIABLE
+PFA_OCR1AH:
+ .dw 137
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Mask Register
+VE_TIMSK1:
+ .dw $ff06
+ .db "TIMSK1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK1
+XT_TIMSK1:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK1:
+ .dw 111
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Flag register
+VE_TIFR1:
+ .dw $ff05
+ .db "TIFR1",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR1
+XT_TIFR1:
+ .dw PFA_DOVARIABLE
+PFA_TIFR1:
+ .dw 54
+; ( -- addr ) System Constant
+; R( -- )
+; General Timer/Counter Control Register
+VE_GTCCR:
+ .dw $ff05
+ .db "GTCCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GTCCR
+XT_GTCCR:
+ .dw PFA_DOVARIABLE
+PFA_GTCCR:
+ .dw 67
+
+.endif
+.if WANT_WAKEUP_TIMER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Wake-up Timer Control Register
+VE_WUTCSR:
+ .dw $ff06
+ .db "WUTCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WUTCSR
+XT_WUTCSR:
+ .dw PFA_DOVARIABLE
+PFA_WUTCSR:
+ .dw 98
+
+.endif
+.if WANT_BATTERY_PROTECTION == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Battery Protection Parameter Lock Register
+VE_BPPLR:
+ .dw $ff05
+ .db "BPPLR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_BPPLR
+XT_BPPLR:
+ .dw PFA_DOVARIABLE
+PFA_BPPLR:
+ .dw 248
+; ( -- addr ) System Constant
+; R( -- )
+; Battery Protection Control Register
+VE_BPCR:
+ .dw $ff04
+ .db "BPCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_BPCR
+XT_BPCR:
+ .dw PFA_DOVARIABLE
+PFA_BPCR:
+ .dw 247
+; ( -- addr ) System Constant
+; R( -- )
+; Current Battery Protection Timing Register
+VE_CBPTR:
+ .dw $ff05
+ .db "CBPTR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CBPTR
+XT_CBPTR:
+ .dw PFA_DOVARIABLE
+PFA_CBPTR:
+ .dw 246
+; ( -- addr ) System Constant
+; R( -- )
+; Battery Protection OverCurrent Detection Level Register
+VE_BPOCD:
+ .dw $ff05
+ .db "BPOCD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_BPOCD
+XT_BPOCD:
+ .dw PFA_DOVARIABLE
+PFA_BPOCD:
+ .dw 245
+; ( -- addr ) System Constant
+; R( -- )
+; Battery Protection Short-Circuit Detection Level Register
+VE_BPSCD:
+ .dw $ff05
+ .db "BPSCD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_BPSCD
+XT_BPSCD:
+ .dw PFA_DOVARIABLE
+PFA_BPSCD:
+ .dw 244
+; ( -- addr ) System Constant
+; R( -- )
+; Battery Protection Deep Under Voltage Register
+VE_BPDUV:
+ .dw $ff05
+ .db "BPDUV",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_BPDUV
+XT_BPDUV:
+ .dw PFA_DOVARIABLE
+PFA_BPDUV:
+ .dw 243
+; ( -- addr ) System Constant
+; R( -- )
+; Battery Protection Interrupt Register
+VE_BPIR:
+ .dw $ff04
+ .db "BPIR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_BPIR
+XT_BPIR:
+ .dw PFA_DOVARIABLE
+PFA_BPIR:
+ .dw 242
+
+.endif
+.if WANT_FET == 1
+; ( -- addr ) System Constant
+; R( -- )
+;
+VE_FCSR:
+ .dw $ff04
+ .db "FCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_FCSR
+XT_FCSR:
+ .dw PFA_DOVARIABLE
+PFA_FCSR:
+ .dw 240
+
+.endif
+.if WANT_COULOMB_COUNTER == 1
+; ( -- addr ) System Constant
+; R( -- )
+; CC-ADC Control and Status Register A
+VE_CADCSRA:
+ .dw $ff07
+ .db "CADCSRA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CADCSRA
+XT_CADCSRA:
+ .dw PFA_DOVARIABLE
+PFA_CADCSRA:
+ .dw 228
+; ( -- addr ) System Constant
+; R( -- )
+; CC-ADC Control and Status Register B
+VE_CADCSRB:
+ .dw $ff07
+ .db "CADCSRB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CADCSRB
+XT_CADCSRB:
+ .dw PFA_DOVARIABLE
+PFA_CADCSRB:
+ .dw 229
+; ( -- addr ) System Constant
+; R( -- )
+; CC-ADC Instantaneous Current
+VE_CADIC:
+ .dw $ff05
+ .db "CADIC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CADIC
+XT_CADIC:
+ .dw PFA_DOVARIABLE
+PFA_CADIC:
+ .dw 232
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Accumulate Current
+VE_CADAC3:
+ .dw $ff06
+ .db "CADAC3"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CADAC3
+XT_CADAC3:
+ .dw PFA_DOVARIABLE
+PFA_CADAC3:
+ .dw 227
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Accumulate Current
+VE_CADAC2:
+ .dw $ff06
+ .db "CADAC2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CADAC2
+XT_CADAC2:
+ .dw PFA_DOVARIABLE
+PFA_CADAC2:
+ .dw 226
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Accumulate Current
+VE_CADAC1:
+ .dw $ff06
+ .db "CADAC1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CADAC1
+XT_CADAC1:
+ .dw PFA_DOVARIABLE
+PFA_CADAC1:
+ .dw 225
+; ( -- addr ) System Constant
+; R( -- )
+; ADC Accumulate Current
+VE_CADAC0:
+ .dw $ff06
+ .db "CADAC0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CADAC0
+XT_CADAC0:
+ .dw PFA_DOVARIABLE
+PFA_CADAC0:
+ .dw 224
+; ( -- addr ) System Constant
+; R( -- )
+; CC-ADC Regular Charge Current
+VE_CADRCC:
+ .dw $ff06
+ .db "CADRCC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CADRCC
+XT_CADRCC:
+ .dw PFA_DOVARIABLE
+PFA_CADRCC:
+ .dw 230
+; ( -- addr ) System Constant
+; R( -- )
+; CC-ADC Regular Discharge Current
+VE_CADRDC:
+ .dw $ff06
+ .db "CADRDC"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CADRDC
+XT_CADRDC:
+ .dw PFA_DOVARIABLE
+PFA_CADRDC:
+ .dw 231
+
+.endif
+.if WANT_CELL_BALANCING == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Cell Balancing Control Register
+VE_CBCR:
+ .dw $ff04
+ .db "CBCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CBCR
+XT_CBCR:
+ .dw PFA_DOVARIABLE
+PFA_CBCR:
+ .dw 241
+
+.endif
+.if WANT_CPU == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Status Register
+VE_SREG:
+ .dw $ff04
+ .db "SREG"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SREG
+XT_SREG:
+ .dw PFA_DOVARIABLE
+PFA_SREG:
+ .dw 95
+; ( -- addr ) System Constant
+; R( -- )
+; Stack Pointer
+VE_SP:
+ .dw $ff02
+ .db "SP"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SP
+XT_SP:
+ .dw PFA_DOVARIABLE
+PFA_SP:
+ .dw 93
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Control Register
+VE_MCUCR:
+ .dw $ff05
+ .db "MCUCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUCR
+XT_MCUCR:
+ .dw PFA_DOVARIABLE
+PFA_MCUCR:
+ .dw 85
+; ( -- addr ) System Constant
+; R( -- )
+; MCU Status Register
+VE_MCUSR:
+ .dw $ff05
+ .db "MCUSR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_MCUSR
+XT_MCUSR:
+ .dw PFA_DOVARIABLE
+PFA_MCUSR:
+ .dw 84
+; ( -- addr ) System Constant
+; R( -- )
+; Fast Oscillator Calibration Value
+VE_FOSCCAL:
+ .dw $ff07
+ .db "FOSCCAL",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_FOSCCAL
+XT_FOSCCAL:
+ .dw PFA_DOVARIABLE
+PFA_FOSCCAL:
+ .dw 102
+; ( -- addr ) System Constant
+; R( -- )
+; Sleep Mode Control Register
+VE_SMCR:
+ .dw $ff04
+ .db "SMCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SMCR
+XT_SMCR:
+ .dw PFA_DOVARIABLE
+PFA_SMCR:
+ .dw 83
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 2
+VE_GPIOR2:
+ .dw $ff06
+ .db "GPIOR2"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR2
+XT_GPIOR2:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR2:
+ .dw 75
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 1
+VE_GPIOR1:
+ .dw $ff06
+ .db "GPIOR1"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR1
+XT_GPIOR1:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR1:
+ .dw 74
+; ( -- addr ) System Constant
+; R( -- )
+; General Purpose IO Register 0
+VE_GPIOR0:
+ .dw $ff06
+ .db "GPIOR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_GPIOR0
+XT_GPIOR0:
+ .dw PFA_DOVARIABLE
+PFA_GPIOR0:
+ .dw 62
+; ( -- addr ) System Constant
+; R( -- )
+; Clock Control and Status Register
+VE_CCSR:
+ .dw $ff04
+ .db "CCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_CCSR
+XT_CCSR:
+ .dw PFA_DOVARIABLE
+PFA_CCSR:
+ .dw 192
+; ( -- addr ) System Constant
+; R( -- )
+; Digital Input Disable Register
+VE_DIDR0:
+ .dw $ff05
+ .db "DIDR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DIDR0
+XT_DIDR0:
+ .dw PFA_DOVARIABLE
+PFA_DIDR0:
+ .dw 126
+; ( -- addr ) System Constant
+; R( -- )
+; Power Reduction Register 0
+VE_PRR0:
+ .dw $ff04
+ .db "PRR0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PRR0
+XT_PRR0:
+ .dw PFA_DOVARIABLE
+PFA_PRR0:
+ .dw 100
+
+.endif
+.if WANT_WATCHDOG == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Watchdog Timer Control Register
+VE_WDTCSR:
+ .dw $ff06
+ .db "WDTCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_WDTCSR
+XT_WDTCSR:
+ .dw PFA_DOVARIABLE
+PFA_WDTCSR:
+ .dw 96
+
+.endif
+.if WANT_TIMER_COUNTER_0 == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Control Register
+VE_TCCR0A:
+ .dw $ff06
+ .db "TCCR0A"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0A
+XT_TCCR0A:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0A:
+ .dw 68
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter0 Control Register
+VE_TCCR0B:
+ .dw $ff06
+ .db "TCCR0B"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCCR0B
+XT_TCCR0B:
+ .dw PFA_DOVARIABLE
+PFA_TCCR0B:
+ .dw 69
+; ( -- addr ) System Constant
+; R( -- )
+; Timer Counter 0
+VE_TCNT0:
+ .dw $ff05
+ .db "TCNT0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TCNT0
+XT_TCNT0:
+ .dw PFA_DOVARIABLE
+PFA_TCNT0:
+ .dw 70
+; ( -- addr ) System Constant
+; R( -- )
+; Output compare Register A
+VE_OCR0A:
+ .dw $ff05
+ .db "OCR0A",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0A
+XT_OCR0A:
+ .dw PFA_DOVARIABLE
+PFA_OCR0A:
+ .dw 71
+; ( -- addr ) System Constant
+; R( -- )
+; Output compare Register B
+VE_OCR0B:
+ .dw $ff05
+ .db "OCR0B",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_OCR0B
+XT_OCR0B:
+ .dw PFA_DOVARIABLE
+PFA_OCR0B:
+ .dw 72
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Mask Register
+VE_TIMSK0:
+ .dw $ff06
+ .db "TIMSK0"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIMSK0
+XT_TIMSK0:
+ .dw PFA_DOVARIABLE
+PFA_TIMSK0:
+ .dw 110
+; ( -- addr ) System Constant
+; R( -- )
+; Timer/Counter Interrupt Flag register
+VE_TIFR0:
+ .dw $ff05
+ .db "TIFR0",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TIFR0
+XT_TIFR0:
+ .dw PFA_DOVARIABLE
+PFA_TIFR0:
+ .dw 53
+
+.endif
+.if WANT_PORTA == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Register
+VE_PORTA:
+ .dw $ff05
+ .db "PORTA",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTA
+XT_PORTA:
+ .dw PFA_DOVARIABLE
+PFA_PORTA:
+ .dw 34
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Data Direction Register
+VE_DDRA:
+ .dw $ff04
+ .db "DDRA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRA
+XT_DDRA:
+ .dw PFA_DOVARIABLE
+PFA_DDRA:
+ .dw 33
+; ( -- addr ) System Constant
+; R( -- )
+; Port A Input Pins
+VE_PINA:
+ .dw $ff04
+ .db "PINA"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINA
+XT_PINA:
+ .dw PFA_DOVARIABLE
+PFA_PINA:
+ .dw 32
+
+.endif
+.if WANT_PORTB == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Register
+VE_PORTB:
+ .dw $ff05
+ .db "PORTB",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTB
+XT_PORTB:
+ .dw PFA_DOVARIABLE
+PFA_PORTB:
+ .dw 37
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Data Direction Register
+VE_DDRB:
+ .dw $ff04
+ .db "DDRB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRB
+XT_DDRB:
+ .dw PFA_DOVARIABLE
+PFA_DDRB:
+ .dw 36
+; ( -- addr ) System Constant
+; R( -- )
+; Port B Input Pins
+VE_PINB:
+ .dw $ff04
+ .db "PINB"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PINB
+XT_PINB:
+ .dw PFA_DOVARIABLE
+PFA_PINB:
+ .dw 35
+
+.endif
+.if WANT_PORTC == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Port C Data Register
+VE_PORTC:
+ .dw $ff05
+ .db "PORTC",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTC
+XT_PORTC:
+ .dw PFA_DOVARIABLE
+PFA_PORTC:
+ .dw 40
+
+.endif
+.if WANT_PORTD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Data Register, Port D
+VE_PORTD:
+ .dw $ff05
+ .db "PORTD",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PORTD
+XT_PORTD:
+ .dw PFA_DOVARIABLE
+PFA_PORTD:
+ .dw 43
+; ( -- addr ) System Constant
+; R( -- )
+; Data Direction Register, Port D
+VE_DDRD:
+ .dw $ff04
+ .db "DDRD"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_DDRD
+XT_DDRD:
+ .dw PFA_DOVARIABLE
+PFA_DDRD:
+ .dw 42
+; ( -- addr ) System Constant
+; R( -- )
+; Input Pins, Port D
+VE_PIND:
+ .dw $ff04
+ .db "PIND"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_PIND
+XT_PIND:
+ .dw PFA_DOVARIABLE
+PFA_PIND:
+ .dw 41
+
+.endif
+.if WANT_BOOT_LOAD == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Store Program Memory Control Register
+VE_SPMCSR:
+ .dw $ff06
+ .db "SPMCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_SPMCSR
+XT_SPMCSR:
+ .dw PFA_DOVARIABLE
+PFA_SPMCSR:
+ .dw 87
+
+.endif
+.if WANT_TWI == 1
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Bus Control and Status Register
+VE_TWBCSR:
+ .dw $ff06
+ .db "TWBCSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWBCSR
+XT_TWBCSR:
+ .dw PFA_DOVARIABLE
+PFA_TWBCSR:
+ .dw 190
+; ( -- addr ) System Constant
+; R( -- )
+; TWI (Slave) Address Mask Register
+VE_TWAMR:
+ .dw $ff05
+ .db "TWAMR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWAMR
+XT_TWAMR:
+ .dw PFA_DOVARIABLE
+PFA_TWAMR:
+ .dw 189
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Bit Rate register
+VE_TWBR:
+ .dw $ff04
+ .db "TWBR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWBR
+XT_TWBR:
+ .dw PFA_DOVARIABLE
+PFA_TWBR:
+ .dw 184
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Control Register
+VE_TWCR:
+ .dw $ff04
+ .db "TWCR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWCR
+XT_TWCR:
+ .dw PFA_DOVARIABLE
+PFA_TWCR:
+ .dw 188
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Status Register
+VE_TWSR:
+ .dw $ff04
+ .db "TWSR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWSR
+XT_TWSR:
+ .dw PFA_DOVARIABLE
+PFA_TWSR:
+ .dw 185
+; ( -- addr ) System Constant
+; R( -- )
+; TWI Data register
+VE_TWDR:
+ .dw $ff04
+ .db "TWDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWDR
+XT_TWDR:
+ .dw PFA_DOVARIABLE
+PFA_TWDR:
+ .dw 187
+; ( -- addr ) System Constant
+; R( -- )
+; TWI (Slave) Address register
+VE_TWAR:
+ .dw $ff04
+ .db "TWAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_TWAR
+XT_TWAR:
+ .dw PFA_DOVARIABLE
+PFA_TWAR:
+ .dw 186
+
+.endif
+.if WANT_BANDGAP == 1
+; ( -- addr ) System Constant
+; R( -- )
+; Bandgap Calibration of Resistor Ladder
+VE_BGCRR:
+ .dw $ff05
+ .db "BGCRR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_BGCRR
+XT_BGCRR:
+ .dw PFA_DOVARIABLE
+PFA_BGCRR:
+ .dw 209
+; ( -- addr ) System Constant
+; R( -- )
+; Bandgap Calibration Register
+VE_BGCCR:
+ .dw $ff05
+ .db "BGCCR",0
+ .dw VE_HEAD
+ .set VE_HEAD=VE_BGCCR
+XT_BGCCR:
+ .dw PFA_DOVARIABLE
+PFA_BGCCR:
+ .dw 208
+
+.endif
+.if WANT_EEPROM == 1
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Address Register Bytes
+VE_EEAR:
+ .dw $ff04
+ .db "EEAR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEAR
+XT_EEAR:
+ .dw PFA_DOVARIABLE
+PFA_EEAR:
+ .dw 65
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Data Register
+VE_EEDR:
+ .dw $ff04
+ .db "EEDR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EEDR
+XT_EEDR:
+ .dw PFA_DOVARIABLE
+PFA_EEDR:
+ .dw 64
+; ( -- addr ) System Constant
+; R( -- )
+; EEPROM Control Register
+VE_EECR:
+ .dw $ff04
+ .db "EECR"
+ .dw VE_HEAD
+ .set VE_HEAD=VE_EECR
+XT_EECR:
+ .dw PFA_DOVARIABLE
+PFA_EECR:
+ .dw 63
+
+.endif
diff --git a/amforth-6.5/avr8/devices/atmega406/device.py b/amforth-6.5/avr8/devices/atmega406/device.py
new file mode 100644
index 0000000..46fb5f3
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega406/device.py
@@ -0,0 +1,290 @@
+# Generated Automatically
+
+# Partname ATmega406
+
+MCUREGS = {
+# Interrupt Vectors
+ 'BPINTAddr' : '#2', # Battery Protection Interrupt
+ 'INT0Addr' : '#4', # External Interrupt Request 0
+ 'INT1Addr' : '#6', # External Interrupt Request 1
+ 'INT2Addr' : '#8', # External Interrupt Request 2
+ 'INT3Addr' : '#10', # External Interrupt Request 3
+ 'PCINT0Addr' : '#12', # Pin Change Interrupt 0
+ 'PCINT1Addr' : '#14', # Pin Change Interrupt 1
+ 'WDTAddr' : '#16', # Watchdog Timeout Interrupt
+ 'WAKE_UPAddr' : '#18', # Wakeup timer overflow
+ 'TIM1_COMPAddr' : '#20', # Timer/Counter 1 Compare Match
+ 'TIM1_OVFAddr' : '#22', # Timer/Counter 1 Overflow
+ 'TIM0_COMPAAddr' : '#24', # Timer/Counter0 Compare A Match
+ 'TIM0_COMPBAddr' : '#26', # Timer/Counter0 Compare B Match
+ 'TIM0_OVFAddr' : '#28', # Timer/Counter0 Overflow
+ 'TWI_BUS_CDAddr' : '#30', # Two-Wire Bus Connect/Disconnect
+ 'TWIAddr' : '#32', # Two-Wire Serial Interface
+ 'VADCAddr' : '#34', # Voltage ADC Conversion Complete
+ 'CCADC_CONVAddr' : '#36', # Coulomb Counter ADC Conversion Complete
+ 'CCADC_REG_CURAddr' : '#38', # Coloumb Counter ADC Regular Current
+ 'CCADC_ACCAddr' : '#40', # Coloumb Counter ADC Accumulator
+ 'EE_READYAddr' : '#42', # EEPROM Ready
+ 'SPM_READYAddr' : '#44', # Store Program Memory Ready
+
+# Module AD_CONVERTER
+ 'VADMUX' : '$7c', # The VADC multiplexer Selection
+ 'VADMUX_VADMUX': '$f', # Analog Channel and Gain Select
+ 'VADC' : '$78', # VADC Data Register Bytes
+ 'VADCSR' : '$7a', # The VADC Control and Status re
+ 'VADCSR_VADEN': '$8', # VADC Enable
+ 'VADCSR_VADSC': '$4', # VADC Satrt Conversion
+ 'VADCSR_VADCCIF': '$2', # VADC Conversion Complete Inter
+ 'VADCSR_VADCCIE': '$1', # VADC Conversion Complete Inter
+
+# Module EXTERNAL_INTERRUPT
+ 'EICRA' : '$69', # External Interrupt Control Reg
+ 'EICRA_ISC3': '$c0', # External Interrupt Sense Contr
+ 'EICRA_ISC2': '$30', # External Interrupt Sense Contr
+ 'EICRA_ISC1': '$c', # External Interrupt Sense Contr
+ 'EICRA_ISC0': '$3', # External Interrupt Sense Contr
+ 'EIMSK' : '$3d', # External Interrupt Mask Regist
+ 'EIMSK_INT': '$f', # External Interrupt Request 1 E
+ 'EIFR' : '$3c', # External Interrupt Flag Regist
+ 'EIFR_INTF': '$f', # External Interrupt Flags
+ 'PCICR' : '$68', # Pin Change Interrupt Control R
+ 'PCICR_PCIE': '$3', # Pin Change Interrupt Enables
+ 'PCIFR' : '$3b', # Pin Change Interrupt Flag Regi
+ 'PCIFR_PCIF': '$3', # Pin Change Interrupt Flags
+ 'PCMSK1' : '$6c', # Pin Change Enable Mask Registe
+ 'PCMSK0' : '$6b', # Pin Change Enable Mask Registe
+
+# Module TIMER_COUNTER_1
+ 'TCCR1B' : '$81', # Timer/Counter1 Control Registe
+ 'TCCR1B_CTC1': '$8', # Clear Timer/Counter on Compare
+ 'TCCR1B_CS1': '$7', # Clock Select1 bits
+ 'TCNT1' : '$84', # Timer Counter 1 Bytes
+ 'OCR1AL' : '$88', # Output Compare Register 1A Low
+ 'OCR1AH' : '$89', # Output Compare Register 1A Hig
+ 'TIMSK1' : '$6f', # Timer/Counter Interrupt Mask R
+ 'TIMSK1_OCIE1A': '$2', # Timer/Counter1 Output Compare
+ 'TIMSK1_TOIE1': '$1', # Timer/Counter1 Overflow Interr
+ 'TIFR1' : '$36', # Timer/Counter Interrupt Flag r
+ 'TIFR1_OCF1A': '$2', # Timer/Counter1 Output Compare
+ 'TIFR1_TOV1': '$1', # Timer/Counter1 Overflow Flag
+ 'GTCCR' : '$43', # General Timer/Counter Control
+ 'GTCCR_TSM': '$80', # Timer/Counter Synchronization
+ 'GTCCR_PSRSYNC': '$1', # Prescaler Reset
+
+# Module WAKEUP_TIMER
+ 'WUTCSR' : '$62', # Wake-up Timer Control Register
+ 'WUTCSR_WUTIF': '$80', # Wake-up Timer Interrupt Flag
+ 'WUTCSR_WUTIE': '$40', # Wake-up Timer Interrupt Enable
+ 'WUTCSR_WUTCF': '$20', # Wake-up timer Calibration Flag
+ 'WUTCSR_WUTR': '$10', # Wake-up Timer Reset
+ 'WUTCSR_WUTE': '$8', # Wake-up Timer Enable
+ 'WUTCSR_WUTP': '$7', # Wake-up Timer Prescaler Bits
+
+# Module BATTERY_PROTECTION
+ 'BPPLR' : '$f8', # Battery Protection Parameter L
+ 'BPPLR_BPPLE': '$2', # Battery Protection Parameter L
+ 'BPPLR_BPPL': '$1', # Battery Protection Parameter L
+ 'BPCR' : '$f7', # Battery Protection Control Reg
+ 'BPCR_DUVD': '$8', #
+ 'BPCR_SCD': '$4', #
+ 'BPCR_DCD': '$2', #
+ 'BPCR_CCD': '$1', #
+ 'CBPTR' : '$f6', # Current Battery Protection Tim
+ 'CBPTR_SCPT': '$f0', #
+ 'CBPTR_OCPT': '$f', #
+ 'BPOCD' : '$f5', # Battery Protection OverCurrent
+ 'BPOCD_DCDL': '$f0', #
+ 'BPOCD_CCDL': '$f', #
+ 'BPSCD' : '$f4', # Battery Protection Short-Circu
+ 'BPSCD_SCDL': '$f', #
+ 'BPDUV' : '$f3', # Battery Protection Deep Under
+ 'BPDUV_DUVT': '$30', #
+ 'BPDUV_DUDL': '$f', #
+ 'BPIR' : '$f2', # Battery Protection Interrupt R
+ 'BPIR_DUVIF': '$80', # Deep Under-voltage Early Warni
+ 'BPIR_COCIF': '$40', # Charge Over-current Protection
+ 'BPIR_DOCIF': '$20', #
+ 'BPIR_SCIF': '$10', #
+ 'BPIR_DUVIE': '$8', # Deep Under-voltage Early Warni
+ 'BPIR_COCIE': '$4', #
+ 'BPIR_DOCIE': '$2', #
+ 'BPIR_SCIE': '$1', #
+
+# Module FET
+ 'FCSR' : '$f0', #
+ 'FCSR_PWMOC': '$20', # Pulse Width Modulation of OC o
+ 'FCSR_PWMOPC': '$10', # Pulse Width Modulation Modulat
+ 'FCSR_CPS': '$8', # Current Protection Status
+ 'FCSR_DFE': '$4', # Discharge FET Enable
+ 'FCSR_CFE': '$2', # Charge FET Enable
+ 'FCSR_PFD': '$1', # Precharge FET disable
+
+# Module COULOMB_COUNTER
+ 'CADCSRA' : '$e4', # CC-ADC Control and Status Regi
+ 'CADCSRA_CADEN': '$80', # When the CADEN bit is cleared
+ 'CADCSRA_CADUB': '$20', # CC_ADC Update Busy
+ 'CADCSRA_CADAS': '$18', # CC_ADC Accumulate Current Sele
+ 'CADCSRA_CADSI': '$6', # The CADSI bits determine the c
+ 'CADCSRA_CADSE': '$1', # When the CADSE bit is written
+ 'CADCSRB' : '$e5', # CC-ADC Control and Status Regi
+ 'CADCSRB_CADACIE': '$40', #
+ 'CADCSRB_CADRCIE': '$20', # Regular Current Interrupt Enab
+ 'CADCSRB_CADICIE': '$10', # CAD Instantenous Current Inter
+ 'CADCSRB_CADACIF': '$4', # CC-ADC Accumulate Current Inte
+ 'CADCSRB_CADRCIF': '$2', # CC-ADC Accumulate Current Inte
+ 'CADCSRB_CADICIF': '$1', # CC-ADC Instantaneous Current I
+ 'CADIC' : '$e8', # CC-ADC Instantaneous Current
+ 'CADAC3' : '$e3', # ADC Accumulate Current
+ 'CADAC2' : '$e2', # ADC Accumulate Current
+ 'CADAC1' : '$e1', # ADC Accumulate Current
+ 'CADAC0' : '$e0', # ADC Accumulate Current
+ 'CADRCC' : '$e6', # CC-ADC Regular Charge Current
+ 'CADRDC' : '$e7', # CC-ADC Regular Discharge Curre
+
+# Module CELL_BALANCING
+ 'CBCR' : '$f1', # Cell Balancing Control Registe
+ 'CBCR_CBE': '$f', # Cell Balancing Enables
+
+# Module CPU
+ 'SREG' : '$5f', # Status Register
+ 'SREG_I': '$80', # Global Interrupt Enable
+ 'SREG_T': '$40', # Bit Copy Storage
+ 'SREG_H': '$20', # Half Carry Flag
+ 'SREG_S': '$10', # Sign Bit
+ 'SREG_V': '$8', # Two's Complement Overflow Flag
+ 'SREG_N': '$4', # Negative Flag
+ 'SREG_Z': '$2', # Zero Flag
+ 'SREG_C': '$1', # Carry Flag
+ 'SP' : '$5d', # Stack Pointer
+ 'MCUCR' : '$55', # MCU Control Register
+ 'MCUCR_JTD': '$80', # JTAG Disable
+ 'MCUCR_PUD': '$10', # Pull-up disable
+ 'MCUCR_IVSEL': '$2', # Interrupt Vector Select
+ 'MCUCR_IVCE': '$1', # Interrupt Vector Change Enable
+ 'MCUSR' : '$54', # MCU Status Register
+ 'MCUSR_JTRF': '$10', # JTAG Reset Flag
+ 'MCUSR_WDRF': '$8', # Watchdog Reset Flag
+ 'MCUSR_BODRF': '$4', # Brown-out Reset Flag
+ 'MCUSR_EXTRF': '$2', # External Reset Flag
+ 'MCUSR_PORF': '$1', # Power-on reset flag
+ 'FOSCCAL' : '$66', # Fast Oscillator Calibration Va
+ 'SMCR' : '$53', # Sleep Mode Control Register
+ 'SMCR_SM': '$e', # Sleep Mode Select bits
+ 'SMCR_SE': '$1', # Sleep Enable
+ 'GPIOR2' : '$4b', # General Purpose IO Register 2
+ 'GPIOR1' : '$4a', # General Purpose IO Register 1
+ 'GPIOR0' : '$3e', # General Purpose IO Register 0
+ 'CCSR' : '$c0', # Clock Control and Status Regis
+ 'CCSR_XOE': '$2', # 32 kHz Crystal Oscillator Enab
+ 'CCSR_ACS': '$1', # Asynchronous Clock Select
+ 'DIDR0' : '$7e', # Digital Input Disable Register
+ 'PRR0' : '$64', # Power Reduction Register 0
+ 'PRR0_PRTWI': '$8', # Power Reduction TWI
+ 'PRR0_PRTIM1': '$4', # Power Reduction Timer/Counter1
+ 'PRR0_PRTIM0': '$2', # Power Reduction Timer/Counter0
+ 'PRR0_PRVADC': '$1', # Power Reduction V-ADC
+
+# Module WATCHDOG
+ 'WDTCSR' : '$60', # Watchdog Timer Control Registe
+ 'WDTCSR_WDIF': '$80', # Watchdog Timeout Interrupt Fla
+ 'WDTCSR_WDIE': '$40', # Watchdog Timeout Interrupt Ena
+ 'WDTCSR_WDP': '$27', # Watchdog Timer Prescaler Bits
+ 'WDTCSR_WDCE': '$10', # Watchdog Change Enable
+ 'WDTCSR_WDE': '$8', # Watch Dog Enable
+
+# Module TIMER_COUNTER_0
+ 'TCCR0A' : '$44', # Timer/Counter0 Control Registe
+ 'TCCR0A_COM0A': '$c0', # Force Output Compare
+ 'TCCR0A_COM0B': '$30', #
+ 'TCCR0A_WGM0': '$3', # Clock Select0 bits
+ 'TCCR0B' : '$45', # Timer/Counter0 Control Registe
+ 'TCCR0B_FOC0A': '$80', # Force Output Compare
+ 'TCCR0B_FOC0B': '$40', # Waveform Generation Mode
+ 'TCCR0B_WGM02': '$8', #
+ 'TCCR0B_CS0': '$7', # Clock Select0 bits
+ 'TCNT0' : '$46', # Timer Counter 0
+ 'OCR0A' : '$47', # Output compare Register A
+ 'OCR0A_OCR0A': '$ff', #
+ 'OCR0B' : '$48', # Output compare Register B
+ 'OCR0B_OCR0B': '$ff', #
+ 'TIMSK0' : '$6e', # Timer/Counter Interrupt Mask R
+ 'TIMSK0_OCIE0B': '$4', # Output Compare Interrupt Enabl
+ 'TIMSK0_OCIE0A': '$2', # Output Compare Interrupt Enabl
+ 'TIMSK0_TOIE0': '$1', # Overflow Interrupt Enable
+ 'TIFR0' : '$35', # Timer/Counter Interrupt Flag r
+ 'TIFR0_OCF0B': '$4', # Output Compare Flag
+ 'TIFR0_OCF0A': '$2', # Output Compare Flag
+ 'TIFR0_TOV0': '$1', # Overflow Flag
+
+# Module PORTA
+ 'PORTA' : '$22', # Port A Data Register
+ 'DDRA' : '$21', # Port A Data Direction Register
+ 'PINA' : '$20', # Port A Input Pins
+
+# Module PORTB
+ 'PORTB' : '$25', # Port B Data Register
+ 'DDRB' : '$24', # Port B Data Direction Register
+ 'PINB' : '$23', # Port B Input Pins
+
+# Module PORTC
+ 'PORTC' : '$28', # Port C Data Register
+
+# Module PORTD
+ 'PORTD' : '$2b', # Data Register, Port D
+ 'DDRD' : '$2a', # Data Direction Register, Port
+ 'PIND' : '$29', # Input Pins, Port D
+
+# Module BOOT_LOAD
+ 'SPMCSR' : '$57', # Store Program Memory Control R
+ 'SPMCSR_SPMIE': '$80', # SPM Interrupt Enable
+ 'SPMCSR_RWWSB': '$40', # Read While Write Section Busy
+ 'SPMCSR_SIGRD': '$20', # Signature Row Read
+ 'SPMCSR_RWWSRE': '$10', # Read While Write section read
+ 'SPMCSR_BLBSET': '$8', # Boot Lock Bit Set
+ 'SPMCSR_PGWRT': '$4', # Page Write
+ 'SPMCSR_PGERS': '$2', # Page Erase
+ 'SPMCSR_SPMEN': '$1', # Store Program Memory Enable
+
+# Module TWI
+ 'TWBCSR' : '$be', # TWI Bus Control and Status Reg
+ 'TWBCSR_TWBCIF': '$80', # TWI Bus Connect/Disconnect Int
+ 'TWBCSR_TWBCIE': '$40', # TWI Bus Connect/Disconnect Int
+ 'TWBCSR_TWBDT': '$6', # TWI Bus Disconnect Time-out Pe
+ 'TWBCSR_TWBCIP': '$1', # TWI Bus Connect/Disconnect Int
+ 'TWAMR' : '$bd', # TWI (Slave) Address Mask Regis
+ 'TWAMR_TWAM': '$fe', #
+ 'TWBR' : '$b8', # TWI Bit Rate register
+ 'TWCR' : '$bc', # TWI Control Register
+ 'TWCR_TWINT': '$80', # TWI Interrupt Flag
+ 'TWCR_TWEA': '$40', # TWI Enable Acknowledge Bit
+ 'TWCR_TWSTA': '$20', # TWI Start Condition Bit
+ 'TWCR_TWSTO': '$10', # TWI Stop Condition Bit
+ 'TWCR_TWWC': '$8', # TWI Write Collition Flag
+ 'TWCR_TWEN': '$4', # TWI Enable Bit
+ 'TWCR_TWIE': '$1', # TWI Interrupt Enable
+ 'TWSR' : '$b9', # TWI Status Register
+ 'TWSR_TWS': '$f8', # TWI Status
+ 'TWSR_TWPS': '$3', # TWI Prescaler
+ 'TWDR' : '$bb', # TWI Data register
+ 'TWAR' : '$ba', # TWI (Slave) Address register
+ 'TWAR_TWA': '$fe', # TWI (Slave) Address register B
+ 'TWAR_TWGCE': '$1', # TWI General Call Recognition E
+
+# Module BANDGAP
+ 'BGCRR' : '$d1', # Bandgap Calibration of Resisto
+ 'BGCCR' : '$d0', # Bandgap Calibration Register
+ 'BGCCR_BGD': '$80', # Setting the BGD bit to one wil
+ 'BGCCR_BGCC': '$3f', # BG Calibration of PTAT Current
+
+# Module EEPROM
+ 'EEAR' : '$41', # EEPROM Address Register Bytes
+ 'EEDR' : '$40', # EEPROM Data Register
+ 'EECR' : '$3f', # EEPROM Control Register
+ 'EECR_EEPM': '$30', # EEPROM Programming Mode Bits
+ 'EECR_EERIE': '$8', # EEPROM Ready Interrupt Enable
+ 'EECR_EEMPE': '$4', # EEPROM Master Programming Enab
+ 'EECR_EEPE': '$2', # EEPROM Programming Enable
+ 'EECR_EERE': '$1', # EEPROM Read Enable
+
+ '__amforth_dummy':'0'
+}
diff --git a/amforth-6.5/avr8/devices/atmega406/words/no-jtag.asm b/amforth-6.5/avr8/devices/atmega406/words/no-jtag.asm
new file mode 100644
index 0000000..352a4bb
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega406/words/no-jtag.asm
@@ -0,0 +1,14 @@
+; ( -- )
+; ( -- )
+; MCU
+; disable jtag at runtime
+VE_NOJTAG:
+ .dw $FF05
+ .db "-jtag",0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOJTAG
+XT_NOJTAG:
+ .dw PFA_NOJTAG
+PFA_NOJTAG:
+
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega406/words/no-wdt.asm b/amforth-6.5/avr8/devices/atmega406/words/no-wdt.asm
new file mode 100644
index 0000000..ff6ddd1
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega406/words/no-wdt.asm
@@ -0,0 +1,34 @@
+; ( -- )
+; MCU
+; disable watch dog timer at runtime
+VE_NOWDT:
+ .dw $ff04
+ .db "-wdt"
+ .dw VE_HEAD
+ .set VE_HEAD = VE_NOWDT
+XT_NOWDT:
+ .dw PFA_NOWDT
+PFA_NOWDT:
+
+ in temp1,SREG
+ push temp1
+ ; Turn always off global interrupt.
+ cli
+ ; Reset Watchdog Timer
+ wdr
+ ; Clear WDRF in MCUSR
+ in temp1, MCUSR
+ andi temp1, (0xff & (0<<WDRF))
+ out MCUSR, temp1
+ ; Write logical one to WDCE and WDE
+ ; Keep old prescaler setting to prevent unintentional time-out
+ in_ temp1, WDTCSR
+ ori temp1, (1<<WDCE) | (1<<WDE)
+ out_ WDTCSR, temp1
+ ; Turn off WDT
+ ldi temp1, (0<<WDE)
+ out_ WDTCSR, temp1
+ ; restore status register
+ pop temp1
+ out SREG,temp1
+ jmp_ DO_NEXT
diff --git a/amforth-6.5/avr8/devices/atmega406/words/sleep.asm b/amforth-6.5/avr8/devices/atmega406/words/sleep.asm
new file mode 100644
index 0000000..256249c
--- /dev/null
+++ b/amforth-6.5/avr8/devices/atmega406/words/sleep.asm
@@ -0,0 +1,19 @@
+; ( mode -- )
+; MCU
+; put the controller into the specified sleep mode
+VE_SLEEP:
+ .dw $ff05
+ .db "sleep", 0
+ .dw VE_HEAD
+ .set VE_HEAD = VE_SLEEP
+XT_SLEEP:
+ .dw PFA_SLEEP
+PFA_SLEEP:
+ andi tosl, 7 ; leave only legal mode bits
+ lsl tosl ; move to correct location (bits 3-1)
+ ori tosl, 1 ; set the SE bit
+ out_ SMCR, tosl ; set the sleep config
+ sleep ; nighty-night
+ out_ SMCR, zerol ; 0 protects against accidental sleeps
+ loadtos ; pop argument from stack
+ jmp_ DO_NEXT