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-rw-r--r--amforth-6.5/avr8/devices/atmega103/atmega103.frt124
-rw-r--r--amforth-6.5/avr8/devices/atmega103/device.asm126
-rw-r--r--amforth-6.5/avr8/devices/atmega103/device.inc825
-rw-r--r--amforth-6.5/avr8/devices/atmega103/device.py88
4 files changed, 0 insertions, 1163 deletions
diff --git a/amforth-6.5/avr8/devices/atmega103/atmega103.frt b/amforth-6.5/avr8/devices/atmega103/atmega103.frt
deleted file mode 100644
index 6130f93..0000000
--- a/amforth-6.5/avr8/devices/atmega103/atmega103.frt
+++ /dev/null
@@ -1,124 +0,0 @@
-\ Partname: ATmega103
-\ Built using part description XML file version 236
-\ generated automatically
-
-hex
-
-\ AD_CONVERTER
-25 constant ADCH \ ADC Data Register High Byte
-24 constant ADCL \ ADC Data Register Low Byte
-26 constant ADCSR \ The ADC Control and Status register
-27 constant ADMUX \ The ADC multiplexer Selection Register
-
-\ ANALOG_COMPARATOR
-28 constant ACSR \ Analog Comparator Control And Status Register
-
-\ CPU
-55 constant MCUCR \ MCU Control Register
-54 constant MCUSR \ MCU Status Register
-5B constant RAMPZ \ RAM Page Z Select Register
-5E constant SPH \ Stack Pointer High
-5D constant SPL \ Stack Pointer Low
-5F constant SREG \ Status Register
-5C constant XDIV \ XTAL Divide Control Register
-
-\ EEPROM
-3F constant EEARH \ EEPROM Read/Write Access High Byte
-3E constant EEARL \ EEPROM Read/Write Access Low Byte
-3C constant EECR \ EEPROM Control Register
-3D constant EEDR \ EEPROM Data Register
-
-\ EXTERNAL_INTERRUPT
-5A constant EICR \ External Interrupt Control Register B
-58 constant EIFR \ External Interrupt Flag Register
-59 constant EIMSK \ External Interrupt Mask Register
-
-\ PORTA
-3A constant DDRA \ Port A Data Direction Register
-39 constant PINA \ Port A Input Pins
-3B constant PORTA \ Port A Data Register
-
-\ PORTB
-37 constant DDRB \ Port B Data Direction Register
-36 constant PINB \ Port B Input Pins
-38 constant PORTB \ Port B Data Register
-
-\ PORTC
-35 constant PORTC \ Port C Data Register
-
-\ PORTD
-31 constant DDRD \ Port D Data Direction Register
-30 constant PIND \ Port D Input Pins
-32 constant PORTD \ Port D Data Register
-
-\ PORTE
-22 constant DDRE \ Data Direction Register, Port E
-21 constant PINE \ Input Pins, Port E
-23 constant PORTE \ Data Register, Port E
-
-\ PORTF
-20 constant PINF \ Input Pins, Port F
-
-\ SPI
-2D constant SPCR \ SPI Control Register
-2F constant SPDR \ SPI Data Register
-2E constant SPSR \ SPI Status Register
-
-\ TIMER_COUNTER_0
-50 constant ASSR \ Asynchronus Status Register
-51 constant OCR0 \ Output Compare Register
-53 constant TCCR0 \ Timer/Counter Control Register
-52 constant TCNT0 \ Timer/Counter Register
-56 constant TIFR \ Timer/Counter Interrupt Flag register
-57 constant TIMSK \ Timer/Counter Interrupt Mask Register
-
-\ TIMER_COUNTER_1
-47 constant ICR1H \ Timer/Counter1 Input Capture Register High Byte
-46 constant ICR1L \ Timer/Counter1 Input Capture Register Low Byte
-4B constant OCR1AH \ Timer/Counter1 Output Compare Register High Byte
-4A constant OCR1AL \ Timer/Counter1 Output Compare Register Low Byte
-49 constant OCR1BH \ Timer/Counter1 Output Compare Register High Byte
-48 constant OCR1BL \ Timer/Counter1 Output Compare Register Low Byte
-4F constant TCCR1A \ Timer/Counter1 Control Register A
-4E constant TCCR1B \ Timer/Counter1 Control Register B
-4D constant TCNT1H \ Timer/Counter1 High Byte
-4C constant TCNT1L \ Timer/Counter1 Low Byte
-
-\ TIMER_COUNTER_2
-43 constant OCR2 \ Timer/Counter2 Output Compare Register
-45 constant TCCR2 \ Timer/Counter2 Control Register
-44 constant TCNT2 \ Timer/Counter2
-
-\ UART
-29 constant UBRR \ UART BAUD Rate Register
-2A constant UCR \ UART Control Register
-2C constant UDR \ UART I/O Data Register
-2B constant USR \ UART Status Register
-
-\ WATCHDOG
-41 constant WDTCR \ Watchdog Timer Control Register
-
-\ Interrupts
-002 constant INT0Addr \ External Interrupt 0
-004 constant INT1Addr \ External Interrupt 1
-006 constant INT2Addr \ External Interrupt 2
-008 constant INT3Addr \ External Interrupt 3
-00A constant INT4Addr \ External Interrupt 4
-00C constant INT5Addr \ External Interrupt 5
-00E constant INT6Addr \ External Interrupt 6
-010 constant INT7Addr \ External Interrupt 7
-012 constant TIMER2_COMPAddr \ Timer/Counter2 Compare Match
-014 constant TIMER2_OVFAddr \ Timer/Counter2 Overflow
-016 constant TIMER1_CAPTAddr \ Timer/Counter1 Capture Event
-018 constant TIMER1_COMPAAddr \ Timer/Counter1 Compare Match A
-01A constant TIMER1_COMPBAddr \ Timer/Counter1 Compare Match B
-01C constant TIMER1_OVFAddr \ Timer/Counter1 Overflow
-01E constant TIMER0_COMPAddr \ Timer/Counter0 Compare Match
-020 constant TIMER0_OVFAddr \ Timer/Counter0 Overflow
-022 constant SPISTCAddr \ SPI Serial Transfer Complete
-024 constant UARTRXAddr \ UART, Rx Complete
-026 constant UARTUDREAddr \ UART Data Register Empty
-028 constant UARTTXAddr \ UART, Tx Complete
-02A constant ADCAddr \ ADC Conversion Complete
-02C constant EE_READYAddr \ EEPROM Ready
-02E constant ANALOG_COMPAddr \ Analog Comparator
diff --git a/amforth-6.5/avr8/devices/atmega103/device.asm b/amforth-6.5/avr8/devices/atmega103/device.asm
deleted file mode 100644
index efcb78f..0000000
--- a/amforth-6.5/avr8/devices/atmega103/device.asm
+++ /dev/null
@@ -1,126 +0,0 @@
-; Partname: ATmega103
-; Built using part description XML file version 236
-; generated automatically, do not edit
-
-.nolist
- .include "m103def.inc"
-.list
-
-.equ ramstart = $60
-.equ CELLSIZE = 2
-.macro readflashcell
- clr temp7
- lsl zl
- rol zh
- rol temp7
- out_ RAMPZ, temp7
- elpm @0, Z+
- elpm @1, Z+
-.endmacro
-.macro writeflashcell
- clr temp7
- lsl zl
- rol zh
- rol temp7
- out_ RAMPZ, temp7
-.endmacro
-
-; the following definitions are shortcuts for the respective forth source segments if set to 1
-.set WANT_AD_CONVERTER = 0
-.set WANT_ANALOG_COMPARATOR = 0
-.set WANT_CPU = 0
-.set WANT_EEPROM = 0
-.set WANT_EXTERNAL_INTERRUPT = 0
-.set WANT_PORTA = 0
-.set WANT_PORTB = 0
-.set WANT_PORTC = 0
-.set WANT_PORTD = 0
-.set WANT_PORTE = 0
-.set WANT_PORTF = 0
-.set WANT_SPI = 0
-.set WANT_TIMER_COUNTER_0 = 0
-.set WANT_TIMER_COUNTER_1 = 0
-.set WANT_TIMER_COUNTER_2 = 0
-.set WANT_UART = 0
-.set WANT_WATCHDOG = 0
-
-
-.ifndef SPMEN
- .equ SPMEN = SELFPRGEN
-.endif
-
-.ifndef SPMCSR
- .equ SPMCSR = SPMCR
-.endif
-
-.ifndef EEPE
- .equ EEPE = EEWE
-.endif
-
-.ifndef EEMPE
- .equ EEMPE = EEMWE
-.endif
-.equ intvecsize = 2 ; please verify; flash size: 131072 bytes
-.equ pclen = 2 ; please verify
-.overlap
-.equ INTVECTORS = 24
-.org $002
- rcall isr ; External Interrupt 0
-.org $004
- rcall isr ; External Interrupt 1
-.org $006
- rcall isr ; External Interrupt 2
-.org $008
- rcall isr ; External Interrupt 3
-.org $00A
- rcall isr ; External Interrupt 4
-.org $00C
- rcall isr ; External Interrupt 5
-.org $00E
- rcall isr ; External Interrupt 6
-.org $010
- rcall isr ; External Interrupt 7
-.org $012
- rcall isr ; Timer/Counter2 Compare Match
-.org $014
- rcall isr ; Timer/Counter2 Overflow
-.org $016
- rcall isr ; Timer/Counter1 Capture Event
-.org $018
- rcall isr ; Timer/Counter1 Compare Match A
-.org $01A
- rcall isr ; Timer/Counter1 Compare Match B
-.org $01C
- rcall isr ; Timer/Counter1 Overflow
-.org $01E
- rcall isr ; Timer/Counter0 Compare Match
-.org $020
- rcall isr ; Timer/Counter0 Overflow
-.org $022
- rcall isr ; SPI Serial Transfer Complete
-.org $024
- rcall isr ; UART, Rx Complete
-.org $026
- rcall isr ; UART Data Register Empty
-.org $028
- rcall isr ; UART, Tx Complete
-.org $02A
- rcall isr ; ADC Conversion Complete
-.org $02C
- rcall isr ; EEPROM Ready
-.org $02E
- rcall isr ; Analog Comparator
-.nooverlap
-mcu_info:
-mcu_ramsize:
- .dw 4000
-mcu_eepromsize:
- .dw 4096
-mcu_maxdp:
- .dw 0 ; minimum of (from XML) and 0xffff
-mcu_numints:
- .dw 24
-mcu_name:
- .dw 9
- .db "ATmega103",0
-.set codestart=pc
diff --git a/amforth-6.5/avr8/devices/atmega103/device.inc b/amforth-6.5/avr8/devices/atmega103/device.inc
deleted file mode 100644
index f52a85e..0000000
--- a/amforth-6.5/avr8/devices/atmega103/device.inc
+++ /dev/null
@@ -1,825 +0,0 @@
-; Partname: ATmega103
-; Built using part description XML file version 236
-; generated automatically, no not edit
-
-; ********
-.if WANT_AD_CONVERTER == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register High Byte
-VE_ADCH:
- .dw $ff04
- .db "ADCH"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCH
-XT_ADCH:
- .dw PFA_DOVARIABLE
-PFA_ADCH:
- .dw $25
-; ( -- addr ) System Constant
-; R( -- )
-; ADC Data Register Low Byte
-VE_ADCL:
- .dw $ff04
- .db "ADCL"
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCL
-XT_ADCL:
- .dw PFA_DOVARIABLE
-PFA_ADCL:
- .dw $24
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC Control and Status register
-VE_ADCSR:
- .dw $ff05
- .db "ADCSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADCSR
-XT_ADCSR:
- .dw PFA_DOVARIABLE
-PFA_ADCSR:
- .dw $26
-; ( -- addr ) System Constant
-; R( -- )
-; The ADC multiplexer Selection Register
-VE_ADMUX:
- .dw $ff05
- .db "ADMUX",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ADMUX
-XT_ADMUX:
- .dw PFA_DOVARIABLE
-PFA_ADMUX:
- .dw $27
-
-.endif
-
-; ********
-.if WANT_ANALOG_COMPARATOR == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Analog Comparator Control And Status Register
-VE_ACSR:
- .dw $ff04
- .db "ACSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ACSR
-XT_ACSR:
- .dw PFA_DOVARIABLE
-PFA_ACSR:
- .dw $28
-
-.endif
-
-; ********
-.if WANT_CPU == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Control Register
-VE_MCUCR:
- .dw $ff05
- .db "MCUCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUCR
-XT_MCUCR:
- .dw PFA_DOVARIABLE
-PFA_MCUCR:
- .dw $55
-; ( -- addr ) System Constant
-; R( -- )
-; MCU Status Register
-VE_MCUSR:
- .dw $ff05
- .db "MCUSR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_MCUSR
-XT_MCUSR:
- .dw PFA_DOVARIABLE
-PFA_MCUSR:
- .dw $54
-; ( -- addr ) System Constant
-; R( -- )
-; RAM Page Z Select Register
-VE_RAMPZ:
- .dw $ff05
- .db "RAMPZ",0
- .dw VE_HEAD
- .set VE_HEAD=VE_RAMPZ
-XT_RAMPZ:
- .dw PFA_DOVARIABLE
-PFA_RAMPZ:
- .dw $5B
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer High
-VE_SPH:
- .dw $ff03
- .db "SPH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_SPH
-XT_SPH:
- .dw PFA_DOVARIABLE
-PFA_SPH:
- .dw $5E
-; ( -- addr ) System Constant
-; R( -- )
-; Stack Pointer Low
-VE_SPL:
- .dw $ff03
- .db "SPL",0
- .dw VE_HEAD
- .set VE_HEAD=VE_SPL
-XT_SPL:
- .dw PFA_DOVARIABLE
-PFA_SPL:
- .dw $5D
-; ( -- addr ) System Constant
-; R( -- )
-; Status Register
-VE_SREG:
- .dw $ff04
- .db "SREG"
- .dw VE_HEAD
- .set VE_HEAD=VE_SREG
-XT_SREG:
- .dw PFA_DOVARIABLE
-PFA_SREG:
- .dw $5F
-; ( -- addr ) System Constant
-; R( -- )
-; XTAL Divide Control Register
-VE_XDIV:
- .dw $ff04
- .db "XDIV"
- .dw VE_HEAD
- .set VE_HEAD=VE_XDIV
-XT_XDIV:
- .dw PFA_DOVARIABLE
-PFA_XDIV:
- .dw $5C
-
-.endif
-
-; ********
-.if WANT_EEPROM == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Read/Write Access High Byte
-VE_EEARH:
- .dw $ff05
- .db "EEARH",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EEARH
-XT_EEARH:
- .dw PFA_DOVARIABLE
-PFA_EEARH:
- .dw $3F
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Read/Write Access Low Byte
-VE_EEARL:
- .dw $ff05
- .db "EEARL",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EEARL
-XT_EEARL:
- .dw PFA_DOVARIABLE
-PFA_EEARL:
- .dw $3E
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Control Register
-VE_EECR:
- .dw $ff04
- .db "EECR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EECR
-XT_EECR:
- .dw PFA_DOVARIABLE
-PFA_EECR:
- .dw $3C
-; ( -- addr ) System Constant
-; R( -- )
-; EEPROM Data Register
-VE_EEDR:
- .dw $ff04
- .db "EEDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EEDR
-XT_EEDR:
- .dw PFA_DOVARIABLE
-PFA_EEDR:
- .dw $3D
-
-.endif
-
-; ********
-.if WANT_EXTERNAL_INTERRUPT == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Control Register B
-VE_EICR:
- .dw $ff04
- .db "EICR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EICR
-XT_EICR:
- .dw PFA_DOVARIABLE
-PFA_EICR:
- .dw $5A
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Flag Register
-VE_EIFR:
- .dw $ff04
- .db "EIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_EIFR
-XT_EIFR:
- .dw PFA_DOVARIABLE
-PFA_EIFR:
- .dw $58
-; ( -- addr ) System Constant
-; R( -- )
-; External Interrupt Mask Register
-VE_EIMSK:
- .dw $ff05
- .db "EIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_EIMSK
-XT_EIMSK:
- .dw PFA_DOVARIABLE
-PFA_EIMSK:
- .dw $59
-
-.endif
-
-; ********
-.if WANT_PORTA == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Direction Register
-VE_DDRA:
- .dw $ff04
- .db "DDRA"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRA
-XT_DDRA:
- .dw PFA_DOVARIABLE
-PFA_DDRA:
- .dw $3A
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Input Pins
-VE_PINA:
- .dw $ff04
- .db "PINA"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINA
-XT_PINA:
- .dw PFA_DOVARIABLE
-PFA_PINA:
- .dw $39
-; ( -- addr ) System Constant
-; R( -- )
-; Port A Data Register
-VE_PORTA:
- .dw $ff05
- .db "PORTA",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTA
-XT_PORTA:
- .dw PFA_DOVARIABLE
-PFA_PORTA:
- .dw $3B
-
-.endif
-
-; ********
-.if WANT_PORTB == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Direction Register
-VE_DDRB:
- .dw $ff04
- .db "DDRB"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRB
-XT_DDRB:
- .dw PFA_DOVARIABLE
-PFA_DDRB:
- .dw $37
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Input Pins
-VE_PINB:
- .dw $ff04
- .db "PINB"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINB
-XT_PINB:
- .dw PFA_DOVARIABLE
-PFA_PINB:
- .dw $36
-; ( -- addr ) System Constant
-; R( -- )
-; Port B Data Register
-VE_PORTB:
- .dw $ff05
- .db "PORTB",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTB
-XT_PORTB:
- .dw PFA_DOVARIABLE
-PFA_PORTB:
- .dw $38
-
-.endif
-
-; ********
-.if WANT_PORTC == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Port C Data Register
-VE_PORTC:
- .dw $ff05
- .db "PORTC",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTC
-XT_PORTC:
- .dw PFA_DOVARIABLE
-PFA_PORTC:
- .dw $35
-
-.endif
-
-; ********
-.if WANT_PORTD == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Direction Register
-VE_DDRD:
- .dw $ff04
- .db "DDRD"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRD
-XT_DDRD:
- .dw PFA_DOVARIABLE
-PFA_DDRD:
- .dw $31
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Input Pins
-VE_PIND:
- .dw $ff04
- .db "PIND"
- .dw VE_HEAD
- .set VE_HEAD=VE_PIND
-XT_PIND:
- .dw PFA_DOVARIABLE
-PFA_PIND:
- .dw $30
-; ( -- addr ) System Constant
-; R( -- )
-; Port D Data Register
-VE_PORTD:
- .dw $ff05
- .db "PORTD",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTD
-XT_PORTD:
- .dw PFA_DOVARIABLE
-PFA_PORTD:
- .dw $32
-
-.endif
-
-; ********
-.if WANT_PORTE == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Data Direction Register, Port E
-VE_DDRE:
- .dw $ff04
- .db "DDRE"
- .dw VE_HEAD
- .set VE_HEAD=VE_DDRE
-XT_DDRE:
- .dw PFA_DOVARIABLE
-PFA_DDRE:
- .dw $22
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port E
-VE_PINE:
- .dw $ff04
- .db "PINE"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINE
-XT_PINE:
- .dw PFA_DOVARIABLE
-PFA_PINE:
- .dw $21
-; ( -- addr ) System Constant
-; R( -- )
-; Data Register, Port E
-VE_PORTE:
- .dw $ff05
- .db "PORTE",0
- .dw VE_HEAD
- .set VE_HEAD=VE_PORTE
-XT_PORTE:
- .dw PFA_DOVARIABLE
-PFA_PORTE:
- .dw $23
-
-.endif
-
-; ********
-.if WANT_PORTF == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Input Pins, Port F
-VE_PINF:
- .dw $ff04
- .db "PINF"
- .dw VE_HEAD
- .set VE_HEAD=VE_PINF
-XT_PINF:
- .dw PFA_DOVARIABLE
-PFA_PINF:
- .dw $20
-
-.endif
-
-; ********
-.if WANT_SPI == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Control Register
-VE_SPCR:
- .dw $ff04
- .db "SPCR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPCR
-XT_SPCR:
- .dw PFA_DOVARIABLE
-PFA_SPCR:
- .dw $2D
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Data Register
-VE_SPDR:
- .dw $ff04
- .db "SPDR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPDR
-XT_SPDR:
- .dw PFA_DOVARIABLE
-PFA_SPDR:
- .dw $2F
-; ( -- addr ) System Constant
-; R( -- )
-; SPI Status Register
-VE_SPSR:
- .dw $ff04
- .db "SPSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_SPSR
-XT_SPSR:
- .dw PFA_DOVARIABLE
-PFA_SPSR:
- .dw $2E
-
-.endif
-
-; ********
-.if WANT_TIMER_COUNTER_0 == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Asynchronus Status Register
-VE_ASSR:
- .dw $ff04
- .db "ASSR"
- .dw VE_HEAD
- .set VE_HEAD=VE_ASSR
-XT_ASSR:
- .dw PFA_DOVARIABLE
-PFA_ASSR:
- .dw $50
-; ( -- addr ) System Constant
-; R( -- )
-; Output Compare Register
-VE_OCR0:
- .dw $ff04
- .db "OCR0"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR0
-XT_OCR0:
- .dw PFA_DOVARIABLE
-PFA_OCR0:
- .dw $51
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Control Register
-VE_TCCR0:
- .dw $ff05
- .db "TCCR0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR0
-XT_TCCR0:
- .dw PFA_DOVARIABLE
-PFA_TCCR0:
- .dw $53
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Register
-VE_TCNT0:
- .dw $ff05
- .db "TCNT0",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT0
-XT_TCNT0:
- .dw PFA_DOVARIABLE
-PFA_TCNT0:
- .dw $52
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Flag register
-VE_TIFR:
- .dw $ff04
- .db "TIFR"
- .dw VE_HEAD
- .set VE_HEAD=VE_TIFR
-XT_TIFR:
- .dw PFA_DOVARIABLE
-PFA_TIFR:
- .dw $56
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter Interrupt Mask Register
-VE_TIMSK:
- .dw $ff05
- .db "TIMSK",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TIMSK
-XT_TIMSK:
- .dw PFA_DOVARIABLE
-PFA_TIMSK:
- .dw $57
-
-.endif
-
-; ********
-.if WANT_TIMER_COUNTER_1 == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register High Byte
-VE_ICR1H:
- .dw $ff05
- .db "ICR1H",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1H
-XT_ICR1H:
- .dw PFA_DOVARIABLE
-PFA_ICR1H:
- .dw $47
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Input Capture Register Low Byte
-VE_ICR1L:
- .dw $ff05
- .db "ICR1L",0
- .dw VE_HEAD
- .set VE_HEAD=VE_ICR1L
-XT_ICR1L:
- .dw PFA_DOVARIABLE
-PFA_ICR1L:
- .dw $46
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register High Byte
-VE_OCR1AH:
- .dw $ff06
- .db "OCR1AH"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1AH
-XT_OCR1AH:
- .dw PFA_DOVARIABLE
-PFA_OCR1AH:
- .dw $4B
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register Low Byte
-VE_OCR1AL:
- .dw $ff06
- .db "OCR1AL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1AL
-XT_OCR1AL:
- .dw PFA_DOVARIABLE
-PFA_OCR1AL:
- .dw $4A
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register High Byte
-VE_OCR1BH:
- .dw $ff06
- .db "OCR1BH"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1BH
-XT_OCR1BH:
- .dw PFA_DOVARIABLE
-PFA_OCR1BH:
- .dw $49
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Output Compare Register Low Byte
-VE_OCR1BL:
- .dw $ff06
- .db "OCR1BL"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR1BL
-XT_OCR1BL:
- .dw PFA_DOVARIABLE
-PFA_OCR1BL:
- .dw $48
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register A
-VE_TCCR1A:
- .dw $ff06
- .db "TCCR1A"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1A
-XT_TCCR1A:
- .dw PFA_DOVARIABLE
-PFA_TCCR1A:
- .dw $4F
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Control Register B
-VE_TCCR1B:
- .dw $ff06
- .db "TCCR1B"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR1B
-XT_TCCR1B:
- .dw PFA_DOVARIABLE
-PFA_TCCR1B:
- .dw $4E
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 High Byte
-VE_TCNT1H:
- .dw $ff06
- .db "TCNT1H"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1H
-XT_TCNT1H:
- .dw PFA_DOVARIABLE
-PFA_TCNT1H:
- .dw $4D
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter1 Low Byte
-VE_TCNT1L:
- .dw $ff06
- .db "TCNT1L"
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT1L
-XT_TCNT1L:
- .dw PFA_DOVARIABLE
-PFA_TCNT1L:
- .dw $4C
-
-.endif
-
-; ********
-.if WANT_TIMER_COUNTER_2 == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Output Compare Register
-VE_OCR2:
- .dw $ff04
- .db "OCR2"
- .dw VE_HEAD
- .set VE_HEAD=VE_OCR2
-XT_OCR2:
- .dw PFA_DOVARIABLE
-PFA_OCR2:
- .dw $43
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2 Control Register
-VE_TCCR2:
- .dw $ff05
- .db "TCCR2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCCR2
-XT_TCCR2:
- .dw PFA_DOVARIABLE
-PFA_TCCR2:
- .dw $45
-; ( -- addr ) System Constant
-; R( -- )
-; Timer/Counter2
-VE_TCNT2:
- .dw $ff05
- .db "TCNT2",0
- .dw VE_HEAD
- .set VE_HEAD=VE_TCNT2
-XT_TCNT2:
- .dw PFA_DOVARIABLE
-PFA_TCNT2:
- .dw $44
-
-.endif
-
-; ********
-.if WANT_UART == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; UART BAUD Rate Register
-VE_UBRR:
- .dw $ff04
- .db "UBRR"
- .dw VE_HEAD
- .set VE_HEAD=VE_UBRR
-XT_UBRR:
- .dw PFA_DOVARIABLE
-PFA_UBRR:
- .dw $29
-; ( -- addr ) System Constant
-; R( -- )
-; UART Control Register
-VE_UCR:
- .dw $ff03
- .db "UCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UCR
-XT_UCR:
- .dw PFA_DOVARIABLE
-PFA_UCR:
- .dw $2A
-; ( -- addr ) System Constant
-; R( -- )
-; UART I/O Data Register
-VE_UDR:
- .dw $ff03
- .db "UDR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_UDR
-XT_UDR:
- .dw PFA_DOVARIABLE
-PFA_UDR:
- .dw $2C
-; ( -- addr ) System Constant
-; R( -- )
-; UART Status Register
-VE_USR:
- .dw $ff03
- .db "USR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_USR
-XT_USR:
- .dw PFA_DOVARIABLE
-PFA_USR:
- .dw $2B
-
-.endif
-
-; ********
-.if WANT_WATCHDOG == 1
-; ********
-; ( -- addr ) System Constant
-; R( -- )
-; Watchdog Timer Control Register
-VE_WDTCR:
- .dw $ff05
- .db "WDTCR",0
- .dw VE_HEAD
- .set VE_HEAD=VE_WDTCR
-XT_WDTCR:
- .dw PFA_DOVARIABLE
-PFA_WDTCR:
- .dw $41
-
-.endif
diff --git a/amforth-6.5/avr8/devices/atmega103/device.py b/amforth-6.5/avr8/devices/atmega103/device.py
deleted file mode 100644
index fcd3341..0000000
--- a/amforth-6.5/avr8/devices/atmega103/device.py
+++ /dev/null
@@ -1,88 +0,0 @@
-# Partname: ATmega103
-# Built using part description XML file version 236
-# generated automatically, do not edit
-MCUREGS = {
- 'ADCH': '$25',
- 'ADCL': '$24',
- 'ADCSR': '$26',
- 'ADMUX': '$27',
- 'ACSR': '$28',
- 'MCUCR': '$55',
- 'MCUSR': '$54',
- 'RAMPZ': '$5B',
- 'SPH': '$5E',
- 'SPL': '$5D',
- 'SREG': '$5F',
- 'XDIV': '$5C',
- 'EEARH': '$3F',
- 'EEARL': '$3E',
- 'EECR': '$3C',
- 'EEDR': '$3D',
- 'EICR': '$5A',
- 'EIFR': '$58',
- 'EIMSK': '$59',
- 'DDRA': '$3A',
- 'PINA': '$39',
- 'PORTA': '$3B',
- 'DDRB': '$37',
- 'PINB': '$36',
- 'PORTB': '$38',
- 'PORTC': '$35',
- 'DDRD': '$31',
- 'PIND': '$30',
- 'PORTD': '$32',
- 'DDRE': '$22',
- 'PINE': '$21',
- 'PORTE': '$23',
- 'PINF': '$20',
- 'SPCR': '$2D',
- 'SPDR': '$2F',
- 'SPSR': '$2E',
- 'ASSR': '$50',
- 'OCR0': '$51',
- 'TCCR0': '$53',
- 'TCNT0': '$52',
- 'TIFR': '$56',
- 'TIMSK': '$57',
- 'ICR1H': '$47',
- 'ICR1L': '$46',
- 'OCR1AH': '$4B',
- 'OCR1AL': '$4A',
- 'OCR1BH': '$49',
- 'OCR1BL': '$48',
- 'TCCR1A': '$4F',
- 'TCCR1B': '$4E',
- 'TCNT1H': '$4D',
- 'TCNT1L': '$4C',
- 'OCR2': '$43',
- 'TCCR2': '$45',
- 'TCNT2': '$44',
- 'UBRR': '$29',
- 'UCR': '$2A',
- 'UDR': '$2C',
- 'USR': '$2B',
- 'WDTCR': '$41',
- 'INT0Addr': '$002',
- 'INT1Addr': '$004',
- 'INT2Addr': '$006',
- 'INT3Addr': '$008',
- 'INT4Addr': '$00A',
- 'INT5Addr': '$00C',
- 'INT6Addr': '$00E',
- 'INT7Addr': '$010',
- 'TIMER2_COMPAddr': '$012',
- 'TIMER2_OVFAddr': '$014',
- 'TIMER1_CAPTAddr': '$016',
- 'TIMER1_COMPAAddr': '$018',
- 'TIMER1_COMPBAddr': '$01A',
- 'TIMER1_OVFAddr': '$01C',
- 'TIMER0_COMPAddr': '$01E',
- 'TIMER0_OVFAddr': '$020',
- 'SPISTCAddr': '$022',
- 'UARTRXAddr': '$024',
- 'UARTUDREAddr': '$026',
- 'UARTTXAddr': '$028',
- 'ADCAddr': '$02A',
- 'EE_READYAddr': '$02C',
- 'ANALOG_COMPAddr': '$02E'
-} \ No newline at end of file